diff --git a/.cmake-format.yaml b/.cmake-format.yaml new file mode 100644 index 0000000000..0a6d46dbfd --- /dev/null +++ b/.cmake-format.yaml @@ -0,0 +1,85 @@ +parse: + additional_commands: + dyninst_library: + flags: + - BUILD_SHARED + - BUILD_STATIC + kwargs: + HEADERS: '*' + SOURCES: '*' + DEPENDS: '*' + COMPILE_DEFINITIONS: '*' + COMPILE_FEATURES: '*' + COMPILE_OPTIONS: '*' + DESTINATION: '*' + DEFAULT_VISIBILITY: '*' + INCLUDE_DIRECTORIES: '*' + LINK_LIBRARIES: '*' + LINK_OPTIONS: '*' + PROPERTIES: '*' + dyninst_add_cache_option: + kwargs: + CACHE: '*' + override_spec: {} + vartags: [] + proptags: [] +format: + disable: false + line_width: 90 + tab_size: 2 + use_tabchars: false + fractional_tab_policy: use-space + max_subgroups_hwrap: 2 + max_pargs_hwrap: 6 + max_rows_cmdline: 2 + separate_ctrl_name_with_space: false + separate_fn_name_with_space: false + dangle_parens: false + dangle_align: child + min_prefix_chars: 4 + max_prefix_chars: 10 + max_lines_hwrap: 2 + line_ending: unix + command_case: lower + keyword_case: upper + always_wrap: [] + enable_sort: true + autosort: false + require_valid_layout: false + layout_passes: {} +markup: + bullet_char: '-' + enum_char: '*' + first_comment_is_literal: true + literal_comment_pattern: ^# + fence_pattern: ^\s*([`~]{3}[`~]*)(.*)$ + ruler_pattern: ^\s*[^\w\s]{3}.*[^\w\s]{3}$ + explicit_trailing_pattern: '#<' + hashruler_min_length: 10 + canonicalize_hashrulers: true + enable_markup: false +lint: + disabled_codes: [] + function_pattern: '[0-9a-z_]+' + macro_pattern: '[0-9A-Z_]+' + global_var_pattern: '[A-Z][0-9A-Z_]+' + internal_var_pattern: _[A-Z][0-9A-Z_]+ + local_var_pattern: '[a-z][a-z0-9_]+' + private_var_pattern: _[0-9a-z_]+ + public_var_pattern: '[A-Z][0-9A-Z_]+' + argument_var_pattern: '[a-z][a-z0-9_]+' + keyword_pattern: '[A-Z][0-9A-Z_]+' + max_conditionals_custom_parser: 2 + min_statement_spacing: 1 + max_statement_spacing: 2 + max_returns: 6 + max_branches: 12 + max_arguments: 5 + max_localvars: 15 + max_statements: 50 +encode: + emit_byteorder_mark: false + input_encoding: utf-8 + output_encoding: utf-8 +misc: + per_command: {} diff --git a/.github/CODEOWNERS b/.github/CODEOWNERS new file mode 100644 index 0000000000..433e62d609 --- /dev/null +++ b/.github/CODEOWNERS @@ -0,0 +1 @@ +* @ROCm/rocprof-sys diff --git a/.github/workflows/build.yaml b/.github/workflows/build.yaml new file mode 100644 index 0000000000..5c5403471b --- /dev/null +++ b/.github/workflows/build.yaml @@ -0,0 +1,75 @@ +name: Build Dyninst + +on: + workflow_call: + inputs: + name: + required: true + type: string + os: + required: true + type: string + extra-libs: + required: false + type: string + extra-cmake-flags: + required: false + type: string + c-compiler: + required: true + type: string + cxx-compiler: + required: true + type: string + is-clang: + required: false + type: boolean + default: false + +jobs: + build: + permissions: + packages: read + strategy: + fail-fast: false + matrix: + build-type: ['DEBUG', 'RELWITHDEBINFO', 'RELEASE'] + runs-on: ubuntu-latest + container: + image: ghcr.io/dyninst/amd64/${{ inputs.os }}:latest + credentials: + username: ${{ github.actor }} + password: ${{ secrets.github_token }} + name: ${{ inputs.name }} (${{ matrix.build-type }}) + steps: + # Clang doesn't allow for multiple libomp installations + - name: Clean libomp install + if: ${{ inputs.is-clang }} + run: apt remove --purge -y "libomp*" + + - name: Install C compiler (${{ inputs.c-compiler }}) + run: | + apt update -qq + apt install -qq --no-install-recommends -y ${{ inputs.c-compiler }} + + # There is no apt package for clang++ + - name: Install ${{ inputs.cxx-compiler }} + if: ${{ !inputs.is-clang }} + run: apt install -qq --no-install-recommends -y ${{ inputs.cxx-compiler }} + + - name: Install extra libs (${{ inputs.extra-libs }}) + if: ${{ inputs.extra-libs != '' }} + run: apt install -qq --no-install-recommends -y ${{ inputs.extra-libs }} + + - name: Configure Dyninst (${{ matrix.build-type }}) + shell: bash + run: | + cmake /dyninst/src \ + -DCMAKE_BUILD_TYPE="${{ matrix.build-type }}" \ + -DCMAKE_C_COMPILER="${{ inputs.c-compiler }}" \ + -DCMAKE_CXX_COMPILER="${{ inputs.cxx-compiler }}" \ + -DDYNINST_WARNINGS_AS_ERRORS=ON ${{ inputs.extra-cmake-flags }} + + - name: Build Dyninst + run: | + cmake --build . --parallel 2 diff --git a/.github/workflows/cmake-formatting.yaml b/.github/workflows/cmake-formatting.yaml new file mode 100644 index 0000000000..7507ed1277 --- /dev/null +++ b/.github/workflows/cmake-formatting.yaml @@ -0,0 +1,33 @@ + +name: CMake Formatting + +on: + pull_request: + branches: [ master ] + paths: + - '**.cmake' + - '**CMakeLists.txt' + workflow_dispatch: + +jobs: + cmake-formatting: + runs-on: ubuntu-latest + + steps: + - uses: actions/checkout@v3 + - name: Install dependencies + run: | + sudo apt-get update + sudo apt-get install -y python3-pip + python3 -m pip install cmake-format + - name: cmake-format + run: | + set +e + cmake-format -i $(find . -type f | egrep 'CMakeLists.txt|\.cmake$') + if [ $(git diff | wc -l) -gt 0 ]; then + echo -e "\nError! CMake files not formatted." + echo -e "\nRun the following to fix:" + for f in $(git diff --name-only); do echo -e " cmake-format -i $f"; done + echo + exit 1 + fi diff --git a/.github/workflows/compiler-multibuild.yaml b/.github/workflows/compiler-multibuild.yaml new file mode 100644 index 0000000000..9f2fa173d4 --- /dev/null +++ b/.github/workflows/compiler-multibuild.yaml @@ -0,0 +1,130 @@ +# 1. Build with multiple versions of gcc and clang using the ubuntu-provided compiler +# 2. Using the latest version of each compiler, build against all supported C++ standards + +name: Compiler multibuild + +on: + schedule: + - cron: '0 3 * * 1' # 3AM on Monday + workflow_dispatch: + +jobs: + gcc-ubuntu-20_04: + strategy: + fail-fast: false + matrix: + version: [7, 8, 9, 10] + uses: ./.github/workflows/build.yaml + with: + name: gcc-${{ matrix.version }} + os: "ubuntu-20.04" + c-compiler: "gcc-${{ matrix.version }}" + cxx-compiler: "g++-${{ matrix.version }}" + + gcc-ubuntu-22_04: + strategy: + fail-fast: false + matrix: + version: [11, 12] + uses: ./.github/workflows/build.yaml + with: + name: gcc-${{ matrix.version }} + os: "ubuntu-22.04" + c-compiler: "gcc-${{ matrix.version }}" + cxx-compiler: "g++-${{ matrix.version }}" + + gcc-ubuntu-23_10: + strategy: + fail-fast: false + matrix: + version: [13] + uses: ./.github/workflows/build.yaml + with: + name: gcc-${{ matrix.version }} + os: "ubuntu-23.10" + c-compiler: "gcc-${{ matrix.version }}" + cxx-compiler: "g++-${{ matrix.version }}" + + + clang-ubuntu-20_04: + strategy: + fail-fast: false + matrix: + version: [7, 8, 9, 10, 11, 12] + uses: ./.github/workflows/build.yaml + with: + name: clang-${{ matrix.version }} + os: "ubuntu-20.04" + c-compiler: "clang-${{ matrix.version }}" + cxx-compiler: "clang++-${{ matrix.version }}" + is-clang: true + extra-libs: "libomp-${{ matrix.version }}-dev" + + clang-ubuntu-22_04: + strategy: + fail-fast: false + matrix: + version: [13, 14, 15] + uses: ./.github/workflows/build.yaml + with: + name: clang-${{ matrix.version }} + os: "ubuntu-22.04" + c-compiler: "clang-${{ matrix.version }}" + cxx-compiler: "clang++-${{ matrix.version }}" + is-clang: true + extra-libs: "libomp-${{ matrix.version }}-dev" + + clang-ubuntu-23_10: + strategy: + fail-fast: false + matrix: + version: [16, 17] + uses: ./.github/workflows/build.yaml + with: + name: clang-${{ matrix.version }} + os: "ubuntu-23.10" + c-compiler: "clang-${{ matrix.version }}" + cxx-compiler: "clang++-${{ matrix.version }}" + is-clang: true + extra-libs: "libomp-${{ matrix.version }}-dev" + + gcc-cxx-standards-11-17: + strategy: + fail-fast: false + matrix: + std: [11, 14, 17] + uses: ./.github/workflows/build.yaml + with: + name: gcc-cxx-${{ matrix.std }} + os: "ubuntu-22.04" + c-compiler: "gcc-12" + cxx-compiler: "g++-12" + extra-cmake-flags: "-DDYNINST_CXX_LANGUAGE_STANDARD=${{ matrix.std }}" + + gcc-cxx-standards-20-23: + strategy: + fail-fast: false + matrix: + std: [20, 23] + uses: ./.github/workflows/build.yaml + with: + name: gcc-cxx-${{ matrix.std }} + os: "ubuntu-23.10" + c-compiler: "gcc-13" + cxx-compiler: "g++-13" + extra-cmake-flags: "-DDYNINST_CXX_LANGUAGE_STANDARD=${{ matrix.std }}" + + clang-cxx-standards: + strategy: + fail-fast: false + matrix: + std: [11, 14, 17] # clang has a bug with 20+ and operator== reflexiveness + uses: ./.github/workflows/build.yaml + with: + name: cxx-${{ matrix.std }} + os: "ubuntu-22.04" + c-compiler: "clang-15" + cxx-compiler: "clang++-15" + is-clang: true + extra-cmake-flags: "-DDYNINST_CXX_LANGUAGE_STANDARD=${{ matrix.std }}" + extra-libs: "libomp-15-dev" diff --git a/.github/workflows/consumers.yaml b/.github/workflows/consumers.yaml new file mode 100644 index 0000000000..3a21c3d023 --- /dev/null +++ b/.github/workflows/consumers.yaml @@ -0,0 +1,170 @@ +# Build the latest versions of applications that consume Dyninst + +name: Build Consumers + +on: + schedule: + - cron: '0 3 * * 1' # Monday at 3AM + workflow_dispatch: + +jobs: + spack-build: + strategy: + fail-fast: false + matrix: + consumer: [ + "hpctoolkit@develop", + "must+stackwalker~backward~tsan" +# extrae+dyninst - not yet tested, may not support dyninst >10.0.0 +# omnitrace - Needs updated cmake +# timemory - Needs updated cmake + ] + runs-on: ubuntu-latest + steps: + - name: ${{ matrix.consumer }} + run: | + sudo apt update -qq + sudo apt install -y -qq --no-install-recommends build-essential gcc g++ gfortran m4 cmake autoconf python3 git unzip openmpi-bin libopenmpi-dev + git clone --depth=1 --branch=develop https://github.com/spack/spack + spack/bin/spack compiler find + spack/bin/spack external find --not-buildable cmake python git m4 openmpi gmake + spack/bin/spack install ${{ matrix.consumer }} ^dyninst@master + + systemtap: + permissions: + packages: read + strategy: + fail-fast: true + matrix: + os: ['ubuntu-23.10'] + runs-on: ubuntu-latest + container: + image: ghcr.io/dyninst/amd64/${{ matrix.os }}:latest + credentials: + username: ${{ github.actor }} + password: ${{ secrets.github_token }} + name: systemtap ${{ matrix.os }} + steps: + - name: Install dependencies + run: | + apt update + apt install -y git python3 libjson-c-dev m4 autoconf + - name: Fetch systemtap + run: | + git clone --depth=1 https://sourceware.org/git/systemtap.git + - name: Make symlinks + run: | + ln -s /dyninst/install/include /usr/include/dyninst + ln -s /dyninst/install/lib /usr/lib64/dyninst + - name: Build systemtap + run: | + cd systemtap + autoreconf + mkdir build + cd build + ../configure --with-dyninst --without-python3-probes + make -j2 + + llnl-stat: + permissions: + packages: read + strategy: + fail-fast: true + matrix: + os: ['ubuntu-20.04'] + runs-on: ubuntu-latest + container: + image: ghcr.io/dyninst/amd64/${{ matrix.os }}:latest + credentials: + username: ${{ github.actor }} + password: ${{ secrets.github_token }} + name: llnl-stat ${{ matrix.os }} + steps: + - name: Install dependencies + run: | + apt update + apt install -y nano git bison flex python3 build-essential dh-autoreconf wget libgcrypt20-dev libboost-program-options-dev libboost-regex-dev libboost-wave-dev libpython3-dev python3-distutils + - name: Install GraphLib + run: | + git clone --depth=1 https://github.com/LLNL/graphlib + cd graphlib + mkdir build + cd build + cmake .. + cmake --build . --parallel 2 + cmake --install . # /usr + - name: Install GraphViz + run: | + cd / + git clone --depth=1 https://gitlab.com/graphviz/graphviz.git + cd graphviz + ./autogen.sh + mkdir build + cd build + ../configure --without-qt --without-gts --without-doc --without-expat --without-ghostscript --without-gtkplus --without-libgd --without-pangocairo --without-popler --without-quartz --without-x + make -j2 + make install + - name: Install launchmon + run: | + cd / + git clone --depth=1 https://github.com/llnl/launchmon.git + cd launchmon + ./bootstrap + mkdir build + cd build + ../configure + make -j2 + make install + - name: Install MRNet + run: | + cd / + git clone --depth=1 https://github.com/dyninst/mrnet.git + cd mrnet + mkdir build + cd build + CC=gcc CXX=g++ ../configure --enable-shared + make -j2 + make install + - name: Install STAT + run: | + cd / + git clone --depth=1 https://github.com/llnl/stat.git + cd stat + ./bootstrap + mkdir build + cd build + ../configure --disable-gui --disable-examples --with-stackwalker=/dyninst/install --with-mrnet=/usr/local + make -j2 + tau: + permissions: + packages: read + strategy: + fail-fast: true + matrix: + os: ['ubuntu-20.04'] + runs-on: ubuntu-latest + container: + image: ghcr.io/dyninst/amd64/${{ matrix.os }}:latest + credentials: + username: ${{ github.actor }} + password: ${{ secrets.github_token }} + name: TAU ${{ matrix.os }} + steps: + - name: Install dependencies + run: | + # TAU assumes Dyninst needs libdwarf instead of libdw. This has no real + # effect on Dyninst as we RPATH our deps. It just makes the manually-constructed + # link line in the TAU build work. + apt update + apt install -y git libdwarf1 + - name: Fix libdwarf + run: | + ln -s /usr/lib/x86_64-linux-gnu/libdwarf.so.1.0.0 /usr/lib/x86_64-linux-gnu/libdwarf.so + - name: Fetch TAU + run: | + git clone --depth=1 https://github.com/UO-OACISS/tau2 + - name: Build TAU + run: | + cd tau2 + ./configure -dyninst=/dyninst/install + make -j2 diff --git a/.github/workflows/dependency-version.yaml b/.github/workflows/dependency-version.yaml new file mode 100644 index 0000000000..bb2e3d4bb3 --- /dev/null +++ b/.github/workflows/dependency-version.yaml @@ -0,0 +1,54 @@ +# Ensure the minimum dependency versions found in the various CMake +# files match the expected values. This ensures we synchronize versions +# across containers and workflows. + +name: Check dependency versions + +on: + pull_request: + branches: [ master ] + paths: + - '**.cmake' + - '**CMakeLists.txt' + - 'docker/dependencies.versions' + workflow_dispatch: + +jobs: + check-version: + runs-on: ubuntu-latest + steps: + - name: Checkout + uses: actions/checkout@v3 + + - name: Version check + run: | + res=0 + current=$(awk 'match($0,/set\(_min_version (.+)\)/,a){print a[1]}' cmake/tpls/DyninstBoost.cmake) + expected=$(awk 'match($0,/boost:(.+)/,a){print a[1]}' docker/dependencies.versions) + if test "$current" != "$expected"; then + echo "Boost mismatch: Found $current, expected $expected" >/dev/stderr + res=1 + fi + + current=$(awk 'match($0,/set\(_min_version (.+)\)/,a){print a[1]}' cmake/tpls/DyninstTBB.cmake) + expected=$(awk 'match($0,/tbb:(.+)/,a){print a[1]}' docker/dependencies.versions) + if test "$current" != "$expected"; then + echo "TBB mismatch: Found $current, expected $expected" >/dev/stderr + res=1 + fi + + current=$(awk 'match($0,/set\(_min_version (.+)\)/,a){print a[1]}' cmake/tpls/DyninstElfUtils.cmake) + expected=$(awk 'match($0,/elfutils:(.+)/,a){print a[1]}' docker/dependencies.versions) + if test "$current" != "$expected"; then + echo "Elfutils mismatch: Found $current, expected $expected" >/dev/stderr + res=1 + fi + + current=$(awk 'match($0,/cmake_minimum_required\(VERSION (.+) FATAL_ERROR\)/,a){print a[1]}' CMakeLists.txt) + expected=$(awk 'match($0,/cmake:(.+)/,a){print a[1]}' docker/dependencies.versions) + if test "$current" != "$expected"; then + echo "CMake mismatch: Found $current, expected $expected" >/dev/stderr + res=1 + fi + + exit $res diff --git a/.github/workflows/dev-containers.yaml b/.github/workflows/dev-containers.yaml new file mode 100644 index 0000000000..d85fe5458e --- /dev/null +++ b/.github/workflows/dev-containers.yaml @@ -0,0 +1,42 @@ +name: Build and Deploy Development Containers + +on: + push: + branches: + - master + workflow_dispatch: + +jobs: + build: + permissions: + packages: write + strategy: + fail-fast: false + matrix: + os: ['ubuntu-20.04', 'ubuntu-22.04', 'ubuntu-23.04', 'ubuntu-23.10', 'ubuntu-24.04', 'fedora-37', 'fedora-38', 'fedora-39'] + runs-on: ubuntu-latest + name: Update dev containers + steps: + - name: Checkout + uses: actions/checkout@v3 + + - name: GHCR Login + uses: docker/login-action@v1 + with: + registry: ghcr.io + username: ${{ github.actor }} + password: ${{ secrets.GITHUB_TOKEN }} + + - name: Pull base image + run: docker pull ghcr.io/dyninst/amd64/${{ matrix.os }}-base:latest + + - name: Build Dyninst Dev Container + run: | + cd docker/ + docker build --build-arg base=ghcr.io/dyninst/amd64/${{ matrix.os }}-base:latest \ + --build-arg build_jobs=2 \ + -f Dockerfile \ + -t ghcr.io/dyninst/amd64/${{ matrix.os }}:latest ../ + + - name: Deploy + run: docker push ghcr.io/dyninst/amd64/${{ matrix.os }}:latest diff --git a/.github/workflows/libabigail.yaml b/.github/workflows/libabigail.yaml new file mode 100644 index 0000000000..36ab118611 --- /dev/null +++ b/.github/workflows/libabigail.yaml @@ -0,0 +1,95 @@ +name: Libabigail ABI Checks +on: + pull_request: [] + +jobs: + get-release: + container: ghcr.io/dyninst/dyninst-ubuntu-20.04:v12.1.0 + runs-on: ubuntu-latest + steps: + - name: Upload Libs + uses: actions/upload-artifact@v2-preview + with: + name: release-libs + path: /opt/dyninst-env/install/dyninst/lib + + get-latest: + container: ghcr.io/dyninst/dyninst-ubuntu-20.04:latest + runs-on: ubuntu-latest + steps: + - name: Upload Libs + uses: actions/upload-artifact@v2-preview + with: + name: latest-libs + path: /opt/dyninst-env/install/dyninst/lib + + get-pr: + container: ghcr.io/dyninst/dyninst-ubuntu-20.04:latest + runs-on: ubuntu-latest + steps: + - name: Build Pull Request + uses: actions/checkout@v3 + - name: Build + run: | + rm -rf /code + cp -R $PWD /code + ls /code + cd /opt/dyninst-env + /bin/bash build.sh + + - name: Upload results + uses: actions/upload-artifact@v2-preview + with: + name: pr-libs + path: /opt/dyninst-env/install/dyninst/lib + + abi: + runs-on: ubuntu-latest + needs: [get-latest, get-release, get-pr] + strategy: + fail-fast: false + matrix: + + # Testing every paired library for release vs pr and main vs. pr + libs: ["libcommon.so", + "libdynC_API.so", + "libdynDwarf.so", + "libdynElf.so", + "libdyninstAPI_RT.so", + "libdyninstAPI.so", + "libinstructionAPI.so", + "libparseAPI.so", + "libpatchAPI.so", + "libpcontrol.so", + "libstackwalk.so", + "libsymLite.so", + "libsymtabAPI.so"] + + # Artifact pairs (named) for comparison) + artifacts: [["pr-libs", "latest-libs"], + ["pr-libs", "release-libs"]] + + steps: + - name: Download Previous Version + uses: actions/download-artifact@v2 + with: + name: ${{ matrix.artifacts[1] }} + path: previous/ + + - name: Download Pull Request Version + uses: actions/download-artifact@v2 + with: + name: ${{ matrix.artifacts[0] }} + path: current/ + + - name: Show Files + run: | + ls current/ + ls previous/ + + - name: Run Libabigail + uses: buildsi/libabigail-action@main + env: + lib: ${{ matrix.libs }} + with: + abidiff: previous/${{ env.lib }} current/${{ env.lib }} diff --git a/.github/workflows/pr-tests.yaml b/.github/workflows/pr-tests.yaml new file mode 100644 index 0000000000..ea8751f309 --- /dev/null +++ b/.github/workflows/pr-tests.yaml @@ -0,0 +1,108 @@ +# On each pull request, we build Dyninst, the test suite, the examples from +# dyninst/examples, and the external test from dyninst/external-tests +# +# The builds are carried out for each supported OS using the base containers +# at https://github.com/orgs/dyninst/packages + +name: Pull Request Tests + +on: + pull_request: + branches: + - master + workflow_dispatch: + +jobs: + gcc-build: + permissions: + packages: read + strategy: + fail-fast: false + matrix: + os: ['ubuntu-20.04', 'ubuntu-22.04', 'ubuntu-23.04', 'ubuntu-23.10', 'ubuntu-24.04', 'fedora-37', 'fedora-38', 'fedora-39'] + runs-on: ubuntu-latest + container: + image: ghcr.io/dyninst/amd64/${{ matrix.os }}-base:latest + credentials: + username: ${{ github.actor }} + password: ${{ secrets.github_token }} + name: gcc on ${{ matrix.os }} + steps: + - name: Checkout Dyninst + uses: actions/checkout@v3 + with: + path: dyninst/src + + - name: Build Dyninst + run: | + ln -s $PWD/dyninst /dyninst + export DYNINST_C_FLAGS="-Werror" DYNINST_CXX_FLAGS="-Werror" + export DYNINST_C_COMPILER="gcc" DYNINST_CXX_COMPILER="g++" + bash /dyninst/src/docker/build.sh /dyninst/src 2 + + - name: Checkout Test Suite + uses: actions/checkout@v3 + with: + repository: dyninst/testsuite + path: testsuite + + - name: Build testsuite + run: | + cd testsuite; mkdir build; cd build + cmake .. -DDyninst_DIR=/dyninst/install/lib/cmake/Dyninst + cmake --build . --parallel 2 + + - name: Checkout Examples + uses: actions/checkout@v3 + with: + repository: dyninst/examples + path: examples + + - name: Build examples + run: | + cd examples; mkdir build; cd build + cmake .. -DDyninst_DIR=/dyninst/install/lib/cmake/Dyninst + cmake --build . --parallel 2 + + - name: Checkout External Tests + uses: actions/checkout@v3 + with: + repository: dyninst/external-tests + path: external-tests + + - name: Build external tests + run: | + cd external-tests; mkdir build; cd build + cmake .. -DDyninst_DIR=/dyninst/install/lib/cmake/Dyninst + cmake --build . --parallel 2 + - name: Run tests + run: | + cd external-tests/build + ctest . + + clang-build: + permissions: + packages: read + strategy: + fail-fast: false + matrix: + os: ['ubuntu-20.04', 'ubuntu-22.04', 'ubuntu-23.04', 'ubuntu-23.10', 'ubuntu-24.04'] + runs-on: ubuntu-latest + container: + image: ghcr.io/dyninst/amd64/${{ matrix.os }}-base:latest + credentials: + username: ${{ github.actor }} + password: ${{ secrets.github_token }} + name: clang on ${{ matrix.os }} + steps: + - name: Checkout Dyninst + uses: actions/checkout@v3 + with: + path: dyninst/src + + - name: Build Dyninst + run: | + ln -s $PWD/dyninst /dyninst + export DYNINST_C_FLAGS="-Werror" DYNINST_CXX_FLAGS="-Werror" + export DYNINST_C_COMPILER="clang" DYNINST_CXX_COMPILER="clang++" + bash /dyninst/src/docker/build.sh /dyninst/src 2 diff --git a/.github/workflows/spack-build.yaml b/.github/workflows/spack-build.yaml new file mode 100644 index 0000000000..9a4b143926 --- /dev/null +++ b/.github/workflows/spack-build.yaml @@ -0,0 +1,19 @@ +name: Spack Build + +on: + schedule: + - cron: '0 3 * * 0' # Every Sunday at 3AM + workflow_dispatch: + +jobs: + build: + runs-on: ubuntu-latest + steps: + - name: spack + run: | + sudo apt update -qq + sudo apt install -y -qq --no-install-recommends build-essential gcc g++ m4 cmake autoconf python3 git + git clone --depth=1 --branch=develop https://github.com/spack/spack + spack/bin/spack compiler find + spack/bin/spack external find --not-buildable cmake + spack/bin/spack install dyninst@master diff --git a/.github/workflows/system-libs.yaml b/.github/workflows/system-libs.yaml new file mode 100644 index 0000000000..55cc360bef --- /dev/null +++ b/.github/workflows/system-libs.yaml @@ -0,0 +1,45 @@ +# Do a simple parse of all system libraries + +name: Parse sys libs + +on: + schedule: + - cron: '0 1 * * 1' # 1AM on Monday + workflow_dispatch: + +jobs: + parse: + permissions: + packages: read + strategy: + fail-fast: false + matrix: + os: ['ubuntu-20.04', 'ubuntu-22.04', 'ubuntu-23.04', 'ubuntu-23.10', 'ubuntu-24.04', 'fedora-37', 'fedora-38', 'fedora-39'] + runs-on: ubuntu-latest + container: + image: ghcr.io/dyninst/amd64/${{ matrix.os }}:latest + credentials: + username: ${{ github.actor }} + password: ${{ secrets.github_token }} + name: ${{ matrix.os }} + steps: + - name: Build parser + run: | + git clone --depth=1 https://github.com/dyninst/external-tests + cd external-tests + mkdir build + cd build + cmake .. -DDyninst_DIR=/dyninst/install/lib/cmake/Dyninst + cmake --build . + cp parseAPI/simpleParser / + + - name: Run parser + run: | + cd / + export LD_LIBRARY_PATH=/dyninst/install/lib:$LD_LIBRARY_PATH + for dir in /usr/lib /usr/lib64; do \ + for file in $(find $dir -type f -name "*.so.*"); do \ + echo $file; \ + ./simpleParser $file; \ + done \ + done diff --git a/.github/workflows/unit-tests.yaml b/.github/workflows/unit-tests.yaml new file mode 100644 index 0000000000..dbc7a227f6 --- /dev/null +++ b/.github/workflows/unit-tests.yaml @@ -0,0 +1,53 @@ +name: Unit tests + +on: + pull_request: + branches: + - master + workflow_dispatch: + +jobs: + unit-tests: + permissions: + packages: read + strategy: + fail-fast: false + matrix: + os: ['ubuntu-20.04', 'ubuntu-22.04', 'ubuntu-23.04', 'ubuntu-23.10', 'ubuntu-24.04', 'fedora-37', 'fedora-38', 'fedora-39'] + runs-on: ubuntu-latest + container: + image: ghcr.io/dyninst/amd64/${{ matrix.os }}-base:latest + credentials: + username: ${{ github.actor }} + password: ${{ secrets.github_token }} + name: unit tests + steps: + - name: Checkout Dyninst + uses: actions/checkout@v3 + with: + path: dyninst/src + + - name: Build Dyninst + run: | + ln -s $PWD/dyninst /dyninst + export DYNINST_C_FLAGS="-Werror" DYNINST_CXX_FLAGS="-Werror" + export DYNINST_C_COMPILER="gcc" DYNINST_CXX_COMPILER="g++" + export EXTRA_CMAKE_FLAGS="-DDYNINST_EXPORT_ALL=1" + bash /dyninst/src/docker/build.sh /dyninst/src 2 + + - name: Checkout Unit Tests + uses: actions/checkout@v3 + with: + repository: dyninst/unit-tests + path: unit-tests + + - name: Build unit tests + run: | + cd unit-tests; mkdir build; cd build + cmake .. -DDyninst_DIR=/dyninst/install/lib/cmake/Dyninst -DDYNINST_SOURCE_TREE=/dyninst/src + cmake --build . --parallel 2 + + - name: Run unit tests + run: | + cd unit-tests/build + ctest . diff --git a/.github_changelog_generator b/.github_changelog_generator deleted file mode 100644 index 913f54fa8f..0000000000 --- a/.github_changelog_generator +++ /dev/null @@ -1,3 +0,0 @@ -unreleased=true -future-release=10.1.0 -since-tag=10.0.0 diff --git a/.gitignore b/.gitignore index f4a0e89ff7..465fd49466 100644 --- a/.gitignore +++ b/.gitignore @@ -111,7 +111,7 @@ CHANGELOG *.bak massif.out.* DyninstAPI*.tgz -common/h/version.h +common/h/dyninstversion.h Doxyfile doxyfiles/* *.dir/ @@ -125,3 +125,4 @@ cmake-build-*/ .cproject .settings .pydevproject +*__pycache__* diff --git a/.gitmodules b/.gitmodules deleted file mode 100644 index d6a81b84ba..0000000000 --- a/.gitmodules +++ /dev/null @@ -1,3 +0,0 @@ -[submodule "testsuite"] - path = testsuite - url = https://github.com/dyninst/testsuite diff --git a/CHANGELOG.md b/CHANGELOG.md index 3809907c4c..c2a7ac6a52 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,5 +1,614 @@ # Change Log +## [13.0.0](https://github.com/dyninst/dyninst/tree/v13.0.0) (2024-02-28) +[Full Changelog](https://github.com/dyninst/dyninst/compare/v12.3.0...master) + +- release 13.0.0 versions & docs ([1695](https://github.com/dyninst/dyninst/issues/1695)) +- Unify software interrupt instruction detection ([1693](https://github.com/dyninst/dyninst/issues/1693)) +- Unify system call detection ([1692](https://github.com/dyninst/dyninst/issues/1692)) +- Remove explicit check for system calls in parse_frame_one_iteration ([1691](https://github.com/dyninst/dyninst/issues/1691)) +- update copyright header and date ([1689](https://github.com/dyninst/dyninst/issues/1689)) +- Fix logic error in IA_IAPI::isInterruptOrSyscall ([1683](https://github.com/dyninst/dyninst/issues/1683)) +- Add CMake option to control symbol visibility ([1688](https://github.com/dyninst/dyninst/issues/1688)) +- Improve syscall and interrupt instruction detection ([1686](https://github.com/dyninst/dyninst/issues/1686)) +- Remove unreachable code in BPatch_addressSpace::getRegisters ([1687](https://github.com/dyninst/dyninst/issues/1687)) +- Refactor IA_IAPI::isSyscall,isInterrupt into arch-specific files ([1684](https://github.com/dyninst/dyninst/issues/1684)) +- Remove dyninstAPI/Relocation/Transformers/Defensive.C ([1685](https://github.com/dyninst/dyninst/issues/1685)) +- IndirectAnalyzer: fix potential segfault ([1672](https://github.com/dyninst/dyninst/issues/1672)) +- correctly detect x86 LEA instructions as NOP ([1681](https://github.com/dyninst/dyninst/issues/1681)) +- fix operator<< for Module* ([1682](https://github.com/dyninst/dyninst/issues/1682)) +- Remove unprintable characters from common/src/Timer.C ([1679](https://github.com/dyninst/dyninst/issues/1679)) +- Use code region boundaries for ParseAPI::Function::less comparator ([1668](https://github.com/dyninst/dyninst/issues/1668)) +- GithubCI: update systemtap weekly test build ([1676](https://github.com/dyninst/dyninst/issues/1676)) +- GithubCI: don't fail fast for PR tests ([1666](https://github.com/dyninst/dyninst/issues/1666)) +- GithubCI: only build hpctoolkit@develop ([1667](https://github.com/dyninst/dyninst/issues/1667)) +- GithubCI: Add weekly test for parsing all system libs in containers ([1665](https://github.com/dyninst/dyninst/issues/1665)) +- Github CI: Use gcc-13 for c++2{0,3} ([1664](https://github.com/dyninst/dyninst/issues/1664)) +- Suppress -Wframe-larger-than in power_opcode_table in clang-1{3,7} ([1662](https://github.com/dyninst/dyninst/issues/1662)) +- Fix libstdc++ noexcept requirement for Operand ctor ([1663](https://github.com/dyninst/dyninst/issues/1663)) +- Github CI: Pass '-y' to apt when removing libomp ([1661](https://github.com/dyninst/dyninst/issues/1661)) +- Docker: only build base images in build_base_images.sh ([1660](https://github.com/dyninst/dyninst/issues/1660)) +- GithubCI: Add gcc-13, clang-16,17 to multicompiler builds ([1659](https://github.com/dyninst/dyninst/issues/1659)) +- Don't use capture lambda in ParseAPI::parsing_printf_int ([1658](https://github.com/dyninst/dyninst/issues/1658)) +- Remove common/machineType.h ([1657](https://github.com/dyninst/dyninst/issues/1657)) +- Remove non-printable characters from common/lprintf.h ([1656](https://github.com/dyninst/dyninst/issues/1656)) +- Move addrRange.h into stackwalk ([1655](https://github.com/dyninst/dyninst/issues/1655)) +- Write to stderr in ParseAPI::parsing_printf ([1650](https://github.com/dyninst/dyninst/issues/1650)) +- Remove dataflowAPI/src/templates.C ([1654](https://github.com/dyninst/dyninst/issues/1654)) +- GithubCI : Add more Ubuntu and Fedora versions ([1652](https://github.com/dyninst/dyninst/issues/1652)) +- Remove proccontrol/dumplibpthread.asm ([1651](https://github.com/dyninst/dyninst/issues/1651)) +- Docker: Use named arguments in build scripts ([1648](https://github.com/dyninst/dyninst/issues/1648)) +- Docker: add script to build all base images ([1649](https://github.com/dyninst/dyninst/issues/1649)) +- Fix register check in LivenessAnalyzer::isMMX ([1644](https://github.com/dyninst/dyninst/issues/1644)) +- Remove unused debug code from AMD 908,90a instruction decoder ([1645](https://github.com/dyninst/dyninst/issues/1645)) +- Clean up InstructionAPI::Operation ([1643](https://github.com/dyninst/dyninst/issues/1643)) +- Set new CMake policy for upper-case _ROOT variables ([1642](https://github.com/dyninst/dyninst/issues/1642)) +- Clean up includes in instructionAPI/Result.h ([1641](https://github.com/dyninst/dyninst/issues/1641)) +- Add debugging functions for instructionAPI ([1640](https://github.com/dyninst/dyninst/issues/1640)) +- Add DWARF mappings for cr8-15 and dr8-15 ([1639](https://github.com/dyninst/dyninst/issues/1639)) +- Add missing x86_64 control and debug registers ([1638](https://github.com/dyninst/dyninst/issues/1638)) +- Synchronize x86 mnemonics with Capstone ([1634](https://github.com/dyninst/dyninst/issues/1634)) +- Add x86_{i386,64} memory-management and x87 control/status registers ([1636](https://github.com/dyninst/dyninst/issues/1636)) +- Update x86 DWARF registers maps ([1633](https://github.com/dyninst/dyninst/issues/1633)) +- Remove deleted x86 RegisterDictionary functions ([1632](https://github.com/dyninst/dyninst/issues/1632)) +- Clean up and improve documentation of x86_64 registers ([1630](https://github.com/dyninst/dyninst/issues/1630)) +- Clean up and improve documentation of x86_32 registers ([1629](https://github.com/dyninst/dyninst/issues/1629)) +- Remove MachineRegister::getSubRegValue ([1631](https://github.com/dyninst/dyninst/issues/1631)) +- Construct a Module from the CU's offset not its PC ([1626](https://github.com/dyninst/dyninst/issues/1626)) +- Restructure operand decoding logic for AMDGPU ([1614](https://github.com/dyninst/dyninst/issues/1614)) +- Deprecate Symtab::getOrCreateModule ([1623](https://github.com/dyninst/dyninst/issues/1623)) +- Explicitly mark overridden member functions in Object-elf ([1624](https://github.com/dyninst/dyninst/issues/1624)) +- Clean up dead code in common/ast.C ([1622](https://github.com/dyninst/dyninst/issues/1622)) +- Clean up common/Types.h ([1619](https://github.com/dyninst/dyninst/issues/1619)) +- Fix astOperatorNode semantics ([1621](https://github.com/dyninst/dyninst/issues/1621)) +- Remove dead code binaryEdit.C ([1620](https://github.com/dyninst/dyninst/issues/1620)) +- Remove addTrapTableSpace_win and addTrapTable_win in binaryEdit.C ([1618](https://github.com/dyninst/dyninst/issues/1618)) +- Remove code protected by USE_ADDRESS_MAPS ([1617](https://github.com/dyninst/dyninst/issues/1617)) +- Remove useless assert in binaryEdit::writeFile ([1616](https://github.com/dyninst/dyninst/issues/1616)) +- Remove extraneous variables in Symbol.C ([1615](https://github.com/dyninst/dyninst/issues/1615)) +- Fix MachRegister bool checks ([1613](https://github.com/dyninst/dyninst/issues/1613)) +- Improve name handling in MachRegister ([1612](https://github.com/dyninst/dyninst/issues/1612)) +- Remove locking before calls to convertDebugOffset ([1611](https://github.com/dyninst/dyninst/issues/1611)) +- Make null pointer checks for ParseAPI::Block::_obj consistent ([1608](https://github.com/dyninst/dyninst/issues/1608)) +- Guarantee operands in AstOperatorNode are non-null ([1609](https://github.com/dyninst/dyninst/issues/1609)) +- Remove FunctionBase::ranges_lock ([1596](https://github.com/dyninst/dyninst/issues/1596)) +- Remove redundant declaration of SymtabAPI::FuncRangeCollection ([1597](https://github.com/dyninst/dyninst/issues/1597)) +- Remove Symtab(MappedFile*) ([1598](https://github.com/dyninst/dyninst/issues/1598)) +- Remove Symtab::exportXML,exportBin,importBin ([1599](https://github.com/dyninst/dyninst/issues/1599)) +- Remove module contains check in Symtab::create{Function,Variable} ([1601](https://github.com/dyninst/dyninst/issues/1601)) +- Remove dyninst.h, stringDecl.h ([1600](https://github.com/dyninst/dyninst/issues/1600)) +- Make SymtabAPI::errMsg thread_local ([1602](https://github.com/dyninst/dyninst/issues/1602)) +- Clean up MachRegister class ([1604](https://github.com/dyninst/dyninst/issues/1604)) +- Lazily parse function ranges in Symtab::getContainingFunction ([1603](https://github.com/dyninst/dyninst/issues/1603)) +- Remove char* ctor overload ([1605](https://github.com/dyninst/dyninst/issues/1605)) +- Remove Symtab::newModule declaration ([1606](https://github.com/dyninst/dyninst/issues/1606)) +- Remove BINEDIT_DEBUG ([1607](https://github.com/dyninst/dyninst/issues/1607)) +- Remove Symtab::getSymbolByIndex ([1610](https://github.com/dyninst/dyninst/issues/1610)) +- Remove common/std_namesp.h ([1594](https://github.com/dyninst/dyninst/issues/1594)) +- Remove codeRange::operator<< ([1595](https://github.com/dyninst/dyninst/issues/1595)) +- Refactor common/dyn_regs.h ([1590](https://github.com/dyninst/dyninst/issues/1590)) +- Remove Pair.h and pdpair ([1593](https://github.com/dyninst/dyninst/issues/1593)) +- Remove Singleton.h ([1592](https://github.com/dyninst/dyninst/issues/1592)) +- Remove BPatch_flowGraph::getLoopMinMaxSourceLines ([1591](https://github.com/dyninst/dyninst/issues/1591)) +- Remove instructionAPI/h/RegisterIDs.h ([1589](https://github.com/dyninst/dyninst/issues/1589)) +- Reorder enumerators in instructionAPI::Result::Result_Type ([1588](https://github.com/dyninst/dyninst/issues/1588)) +- Fix redundant parsing of linemap information ([1587](https://github.com/dyninst/dyninst/issues/1587)) +- Move entryIDs into separate data files ([1585](https://github.com/dyninst/dyninst/issues/1585)) +- Remove mapped_module::getAddrFromLine ([1586](https://github.com/dyninst/dyninst/issues/1586)) +- Handle implicit operand for call instruction to ROSE ([1583](https://github.com/dyninst/dyninst/issues/1583)) +- Add missing memory operand sizes and decoding in instructionAPI::Result ([1582](https://github.com/dyninst/dyninst/issues/1582)) +- Fix line information parsing for CUs with no aranges ([1581](https://github.com/dyninst/dyninst/issues/1581)) +- Fix naming of Modules with relative CU paths ([1580](https://github.com/dyninst/dyninst/issues/1580)) +- Replace Module::getAllFunctions ([1579](https://github.com/dyninst/dyninst/issues/1579)) +- Reduce usage of concurrent.h ([1578](https://github.com/dyninst/dyninst/issues/1578)) +- Remove Module::findFunctionByEntryOffset ([1577](https://github.com/dyninst/dyninst/issues/1577)) +- Remove MODULE_ANNOTATABLE_CLASS ([1576](https://github.com/dyninst/dyninst/issues/1576)) +- Remove DWARFisms from Symtab::Module ([1575](https://github.com/dyninst/dyninst/issues/1575)) +- Deprecate mapped_module::truncateLineFilenames ([1574](https://github.com/dyninst/dyninst/issues/1574)) +- Refactor symtab/Module.h ([1573](https://github.com/dyninst/dyninst/issues/1573)) +- Use Symtab::getContainingModule instead of Symtab::findModuleByOffset ([1572](https://github.com/dyninst/dyninst/issues/1572)) +- Add Symtab::getContainingModule(Offset) ([1571](https://github.com/dyninst/dyninst/issues/1571)) +- warning fix: false positive maybe uninitialized ([1570](https://github.com/dyninst/dyninst/issues/1570)) +- fix gcc 6's broken __has_x_attribute ([1569](https://github.com/dyninst/dyninst/issues/1569)) +- Refactor Symtab::getOrCreateModule ([1568](https://github.com/dyninst/dyninst/issues/1568)) +- Remove Symtab::findModuleByName(Module *&, std::string) ([1565](https://github.com/dyninst/dyninst/issues/1565)) +- Remove Module::findFunctionByEntryOffset ([1561](https://github.com/dyninst/dyninst/issues/1561)) +- Remove Module::findFunctionsByName ([1562](https://github.com/dyninst/dyninst/issues/1562)) +- Fix inline detection in findFuncName ([1563](https://github.com/dyninst/dyninst/issues/1563)) +- Improve DWARF debugging in Object::fix_global_symbol_modules_static_dwarf ([1564](https://github.com/dyninst/dyninst/issues/1564)) +- Clean up dead code in dwarfWalker.C ([1566](https://github.com/dyninst/dyninst/issues/1566)) +- Remove Symtab::changeSymbolOffset ([1567](https://github.com/dyninst/dyninst/issues/1567)) +- Remove DwarfWalker::setModuleFromName ([1546](https://github.com/dyninst/dyninst/issues/1546)) +- GithubCI: add testing on Fedora-39 ([1560](https://github.com/dyninst/dyninst/issues/1560)) +- warning fix: improve logical-op handling ([1559](https://github.com/dyninst/dyninst/issues/1559)) +- Create unique names for unnamed partial DWARF DIEs ([1558](https://github.com/dyninst/dyninst/issues/1558)) +- Drop Support for AMDGPU GFX900(VEGA) ([1555](https://github.com/dyninst/dyninst/issues/1555)) +- reorganize and cleanup Symtab.h ([1557](https://github.com/dyninst/dyninst/issues/1557)) +- Mark Symtab::findModuleByOffset(Module*&,Offset) with DYNINST_DEPRECATED ([1551](https://github.com/dyninst/dyninst/issues/1551)) +- fix deprecated annotation warning using clang ([1554](https://github.com/dyninst/dyninst/issues/1554)) +- GithubCI: fix names in consumer weekly build ([1553](https://github.com/dyninst/dyninst/issues/1553)) +- Add Initial Support for GFX940 ([1541](https://github.com/dyninst/dyninst/issues/1541)) +- Add findModulesByName(std::string const&) ([1552](https://github.com/dyninst/dyninst/issues/1552)) +- GithubCI: improve error handling ([1548](https://github.com/dyninst/dyninst/issues/1548)) +- add deprecated annotation support ([1550](https://github.com/dyninst/dyninst/issues/1550)) +- Remove public Symtab API for adding line information ([1547](https://github.com/dyninst/dyninst/issues/1547)) +- Add new Symtab interface for accessing modules by offset ([1545](https://github.com/dyninst/dyninst/issues/1545)) +- Mark SymtabAPI::Function::removeSymbol as 'override' ([1549](https://github.com/dyninst/dyninst/issues/1549)) +- Replace boost::multi_index_container with tbb::concurrent_unordered_set in symtab_impl ([1544](https://github.com/dyninst/dyninst/issues/1544)) +- Make Symtab::getDefaultModule const ([1543](https://github.com/dyninst/dyninst/issues/1543)) +- Make a default module a class invariant in Symtab ([1538](https://github.com/dyninst/dyninst/issues/1538)) +- Default-initialized 'std::once_flag's in symtab_impl ([1539](https://github.com/dyninst/dyninst/issues/1539)) +- Use fully-qualified name in fix_global_symbol_modules_static_dwarf ([1540](https://github.com/dyninst/dyninst/issues/1540)) +- Fix duplicate symbol entries in Symtab:everyFunction ([1542](https://github.com/dyninst/dyninst/issues/1542)) +- Fix overflow of fields in instruction layout ([1476](https://github.com/dyninst/dyninst/issues/1476)) +- Refactor DwarfWalker::dieRanges ([1535](https://github.com/dyninst/dyninst/issues/1535)) +- Remove dwarfWalker::getHighPCLowPC ([1536](https://github.com/dyninst/dyninst/issues/1536)) +- Hide implementations of complex data structures in SymtabAPI::Symtab ([1531](https://github.com/dyninst/dyninst/issues/1531)) +- Refactor Symtab::addSymbolToAggregate ([1534](https://github.com/dyninst/dyninst/issues/1534)) +- Remove dwarfWalker::deallocateLocationList ([1532](https://github.com/dyninst/dyninst/issues/1532)) +- GithubCI: allow manually running all CI workflows ([1533](https://github.com/dyninst/dyninst/issues/1533)) +- Remove Symtab::fixup_SymbolAddr ([1530](https://github.com/dyninst/dyninst/issues/1530)) +- GithubCI: Re-enable consumer builds ([1529](https://github.com/dyninst/dyninst/issues/1529)) +- Github CI: Add weekly build of MUST ([1527](https://github.com/dyninst/dyninst/issues/1527)) +- GithubCI: Allow conumer builds to be run manually ([1528](https://github.com/dyninst/dyninst/issues/1528)) +- Github CI: Build TAU weekly ([1526](https://github.com/dyninst/dyninst/issues/1526)) +- Github CI: Build LLNL/STAT weekly ([1525](https://github.com/dyninst/dyninst/issues/1525)) +- Github CI: Build systemtap weekly ([1524](https://github.com/dyninst/dyninst/issues/1524)) +- Add indirect branch support for gfx908 and gfx90a ([1519](https://github.com/dyninst/dyninst/issues/1519)) +- Fix int size of rose operations return values ([1522](https://github.com/dyninst/dyninst/issues/1522)) +- Fix Implementation for RoseOperation::extractOp ([1511](https://github.com/dyninst/dyninst/issues/1511)) +- Don't create a name for artificial DIEs with a DW_AT_name ([1520](https://github.com/dyninst/dyninst/issues/1520)) +- Github CI: use correct directory when running external-tests on PR ([1521](https://github.com/dyninst/dyninst/issues/1521)) +- Remove DwarfWalker::version member variable ([1516](https://github.com/dyninst/dyninst/issues/1516)) +- Parse all DWARF source files in DwarfWalker::buildSrcFiles ([1515](https://github.com/dyninst/dyninst/issues/1515)) +- Refactor dwarf/dwarf_names.h ([1514](https://github.com/dyninst/dyninst/issues/1514)) +- Github CI: execute external tests on PR ([1512](https://github.com/dyninst/dyninst/issues/1512)) +- Github CI: terminate PR pipeline at first failure ([1513](https://github.com/dyninst/dyninst/issues/1513)) +- Unify naming of Modules ([1500](https://github.com/dyninst/dyninst/issues/1500)) +- Remove ret_lock from SymtabAPI::FunctionBase ([1504](https://github.com/dyninst/dyninst/issues/1504)) +- Remove hasSpecification param from DwarfWalker::getReturnType ([1507](https://github.com/dyninst/dyninst/issues/1507)) +- Use full filenames when handling Modules ([1501](https://github.com/dyninst/dyninst/issues/1501)) +- Fix inverted logic in DwarfDyninst::is_cudie ([1505](https://github.com/dyninst/dyninst/issues/1505)) +- Don't check for existing return type when parsing DWARF subprogram ([1509](https://github.com/dyninst/dyninst/issues/1509)) +- Remove FunctionBase::setReturnType(Type*) ([1503](https://github.com/dyninst/dyninst/issues/1503)) +- Workarounds to align decoder output with llvm-objdump ([1508](https://github.com/dyninst/dyninst/issues/1508)) +- Add newline in log message in DwarfWalker::parseModule ([1506](https://github.com/dyninst/dyninst/issues/1506)) +- Fix responsibility inversion in Module::finalizeRanges ([1498](https://github.com/dyninst/dyninst/issues/1498)) +- Use uniform CU checks in DwarfWalker ([1499](https://github.com/dyninst/dyninst/issues/1499)) +- Remove pd_dwarf_handler ([1496](https://github.com/dyninst/dyninst/issues/1496)) +- Refactor extracting CU tags from DWARF ([1495](https://github.com/dyninst/dyninst/issues/1495)) +- Make Symtab::parseTypesNow thread-safe ([1497](https://github.com/dyninst/dyninst/issues/1497)) +- Move inst2ast example to examples repo ([1492](https://github.com/dyninst/dyninst/issues/1492)) +- Remove parseAPI examples ([1494](https://github.com/dyninst/dyninst/issues/1494)) +- Remove patchAPI/test/findPoint ([1490](https://github.com/dyninst/dyninst/issues/1490)) +- Remove patchAPI/example ([1491](https://github.com/dyninst/dyninst/issues/1491)) +- Remove AObject::symsToModules_ ([1488](https://github.com/dyninst/dyninst/issues/1488)) +- Remove Module::setName ([1485](https://github.com/dyninst/dyninst/issues/1485)) +- Remove declaration of image::getModuleLanguageInfo ([1486](https://github.com/dyninst/dyninst/issues/1486)) +- Remove declaration of Object::load_shared_object ([1487](https://github.com/dyninst/dyninst/issues/1487)) +- Remove unused Object::getFileName ([1489](https://github.com/dyninst/dyninst/issues/1489)) +- Clean up unused global variables in Object-elf.C ([1483](https://github.com/dyninst/dyninst/issues/1483)) +- Remove unused Object::find_symbol in Object-elf ([1480](https://github.com/dyninst/dyninst/issues/1480)) +- Remove Symtab::updateIndices ([1481](https://github.com/dyninst/dyninst/issues/1481)) +- Clean up SymtabAPI::LineInformation class ([1479](https://github.com/dyninst/dyninst/issues/1479)) +- Remove Symtab::forceFullLineInfoParse ([1478](https://github.com/dyninst/dyninst/issues/1478)) +- Don't include compiler-specific headers ([1477](https://github.com/dyninst/dyninst/issues/1477)) +- Fix AMDGPU register formatting ([1473](https://github.com/dyninst/dyninst/issues/1473)) +- Clean up SymtabAPI::Function classes ([1475](https://github.com/dyninst/dyninst/issues/1475)) +- Fix hang when creating ELF dynamic sections ([1474](https://github.com/dyninst/dyninst/issues/1474)) +- Do not decode operands for invalid opcode ([1467](https://github.com/dyninst/dyninst/issues/1467)) +- Add support for EM_INTELGT ([1468](https://github.com/dyninst/dyninst/issues/1468)) +- do not export Instruction::appendOperand ([1466](https://github.com/dyninst/dyninst/issues/1466)) +- add getDisplayOrderedOperands interface ([1465](https://github.com/dyninst/dyninst/issues/1465)) +- modernize ArchSpecificFormatter classes ([1464](https://github.com/dyninst/dyninst/issues/1464)) +- improve intel instruction & operand formatting ([1463](https://github.com/dyninst/dyninst/issues/1463)) +- fix x86_64 ret instruction formatting ([1457](https://github.com/dyninst/dyninst/issues/1457)) +- modernize InstructionAPI::Operand class ([1456](https://github.com/dyninst/dyninst/issues/1456)) +- Fix x86 misspelled, incorrect, and invalid opcodes ([1421](https://github.com/dyninst/dyninst/issues/1421)) +- Remove Object::dwarf_parse_aranges ([1462](https://github.com/dyninst/dyninst/issues/1462)) +- Fix EM_AMDGPU to use RELA as Region Type ([1444](https://github.com/dyninst/dyninst/issues/1444)) +- Remove lazy initialization of IBSTrees in Symtab ([1454](https://github.com/dyninst/dyninst/issues/1454)) +- Make Symtab::getContainingInlinedFunction lazy parsing threadsafe ([1452](https://github.com/dyninst/dyninst/issues/1452)) +- Clean up Symtab constructors ([1451](https://github.com/dyninst/dyninst/issues/1451)) +- Explicitly delete unusable special member functions in Symtab ([1450](https://github.com/dyninst/dyninst/issues/1450)) +- Remove Symtab::mfForDebugInfo ([1449](https://github.com/dyninst/dyninst/issues/1449)) +- Remove Symtab::checkPPC64DescriptorSymbols ([1448](https://github.com/dyninst/dyninst/issues/1448)) +- Remove Symtab copy constructor ([1447](https://github.com/dyninst/dyninst/issues/1447)) +- add header files to directly define std:: syms ([1443](https://github.com/dyninst/dyninst/issues/1443)) +- Fix vector instruction lengths ([1439](https://github.com/dyninst/dyninst/issues/1439)) +- Fix several resource leaks ([1435](https://github.com/dyninst/dyninst/issues/1435)) +- Fix undefined behavior in integer operations ([1434](https://github.com/dyninst/dyninst/issues/1434)) +- Prevent use of possibly-uninitialized local variable ([1433](https://github.com/dyninst/dyninst/issues/1433)) +- Fix uninitialized member variables ([1431](https://github.com/dyninst/dyninst/issues/1431)) +- Fix use of null pointer after check ([1432](https://github.com/dyninst/dyninst/issues/1432)) +- Protect against self-assignment in copy constructors ([1430](https://github.com/dyninst/dyninst/issues/1430)) +- Fix windows warnings ([1429](https://github.com/dyninst/dyninst/issues/1429)) +- Remove virtual calls in constructor/destructor ([1428](https://github.com/dyninst/dyninst/issues/1428)) +- AddressTranslateSysV::adjustForAddrSpaceWrap: Fix C file descriptor leak ([1427](https://github.com/dyninst/dyninst/issues/1427)) +- Make CondVar non-copyable, non-moveable ([1426](https://github.com/dyninst/dyninst/issues/1426)) +- Github CI: increase number of build jobs ([1424](https://github.com/dyninst/dyninst/issues/1424)) +- Github CI: make compiler multi-build a cron job ([1425](https://github.com/dyninst/dyninst/issues/1425)) +- CI compiler multibuilds ([1415](https://github.com/dyninst/dyninst/issues/1415)) +- Use default TBB when doing CI spack build ([1423](https://github.com/dyninst/dyninst/issues/1423)) +- Add ubuntu-22.04 to dev container build ([1419](https://github.com/dyninst/dyninst/issues/1419)) +- Refactor Dockerfile.ubuntu ([1420](https://github.com/dyninst/dyninst/issues/1420)) +- warning fix: stack frame size ([1418](https://github.com/dyninst/dyninst/issues/1418)) +- Make InstructionAPI::isArrayIndexValid const. ([1416](https://github.com/dyninst/dyninst/issues/1416)) +- CMake modernization ([1391](https://github.com/dyninst/dyninst/issues/1391)) +- Add callback for parsing unknown instructions ([1276](https://github.com/dyninst/dyninst/issues/1276)) +- Update GFX90A Decoder ISA-SPEC(02/22/23) ([1407](https://github.com/dyninst/dyninst/issues/1407)) +- Update GFX908 Decoder ISA-SPEC(02/22/23) ([1408](https://github.com/dyninst/dyninst/issues/1408)) +- Add CI workflow to build consumers of Dyninst ([1412](https://github.com/dyninst/dyninst/issues/1412)) +- CI workflow to build from spack ([1411](https://github.com/dyninst/dyninst/issues/1411)) +- Rename Architecture AMDGPU_CDNA2 to AMDGPU_GFX90A ([1404](https://github.com/dyninst/dyninst/issues/1404)) +- Fix link bug in insnCodeGen::loadImmIntoReg on aarch64 ([1405](https://github.com/dyninst/dyninst/issues/1405)) +- remove unneeded zero length files ([1403](https://github.com/dyninst/dyninst/issues/1403)) +- Fix UB in dwarf/dwarf_subrange.cpp::get_type ([1402](https://github.com/dyninst/dyninst/issues/1402)) +- warning fix: stack frame larger than ([1397](https://github.com/dyninst/dyninst/issues/1397)) +- warning fix: unused parameter (conditionally) ([1397](https://github.com/dyninst/dyninst/issues/1397)) +- fix broken call to base class function ([1397](https://github.com/dyninst/dyninst/issues/1397)) +- enable warnings in dataflowAPI/src ([1397](https://github.com/dyninst/dyninst/issues/1397)) +- warning fix: unused variable (clang compiler bug) ([1397](https://github.com/dyninst/dyninst/issues/1397)) +- warning fix: suppress VLA warning ([1397](https://github.com/dyninst/dyninst/issues/1397)) +- warning fix: std::iterator is deprecated ([1397](https://github.com/dyninst/dyninst/issues/1397)) +- warning fix: missing noexcept ([1397](https://github.com/dyninst/dyninst/issues/1397)) +- warning fix: deprecated implicit ctor and op= ([1397](https://github.com/dyninst/dyninst/issues/1397)) +- warning fix: shadow (delete variable) ([1397](https://github.com/dyninst/dyninst/issues/1397)) +- warning fix: shadow (rename) ([1397](https://github.com/dyninst/dyninst/issues/1397)) +- warning fix: potentially evaluated expression ([1397](https://github.com/dyninst/dyninst/issues/1397)) +- warning fix: overloaded virtual overrides ([1397](https://github.com/dyninst/dyninst/issues/1397)) +- warning fix: copy ctor missing base class ([1397](https://github.com/dyninst/dyninst/issues/1397)) +- warning fix: case fallthough ([1397](https://github.com/dyninst/dyninst/issues/1397)) +- warning fix: printf format related ([1397](https://github.com/dyninst/dyninst/issues/1397)) +- warning fix: reorder ctor initialization list ([1397](https://github.com/dyninst/dyninst/issues/1397)) +- warning fix: const correctness ([1397](https://github.com/dyninst/dyninst/issues/1397)) +- warning fix: unused variables ([1397](https://github.com/dyninst/dyninst/issues/1397)) +- warning fix: unused parameters ([1397](https://github.com/dyninst/dyninst/issues/1397)) +- warning fix: variadic macro ([1397](https://github.com/dyninst/dyninst/issues/1397)) +- warning fix: extraneous semicolons ([1397](https://github.com/dyninst/dyninst/issues/1397)) +- Github CI: update dev container deployment ([1400](https://github.com/dyninst/dyninst/issues/1400)) +- Github CI: add line continuation in dev-containers.yaml ([1399](https://github.com/dyninst/dyninst/issues/1399)) +- Add PR testing Github CI ([1393](https://github.com/dyninst/dyninst/issues/1393)) +- Replace 'cerr' with 'dwarf_print' in DwarfWalker::decodeLocationList ([1395](https://github.com/dyninst/dyninst/issues/1395)) +- warning fix: deprecated copy with user dtor ([1394](https://github.com/dyninst/dyninst/issues/1394)) +- warning fix: unneeded internal declaration ([1394](https://github.com/dyninst/dyninst/issues/1394)) +- warning fix: ambiguous reversed operator (derived) ([1394](https://github.com/dyninst/dyninst/issues/1394)) +- warning fix: stack frame larger than ([1394](https://github.com/dyninst/dyninst/issues/1394)) +- warning fix: logical op ([1394](https://github.com/dyninst/dyninst/issues/1394)) +- warning fix: C function decls without prototype ([1394](https://github.com/dyninst/dyninst/issues/1394)) +- warning fix: set but unused variables ([1394](https://github.com/dyninst/dyninst/issues/1394)) +- warning fix: ambiguous reversed operator ([1394](https://github.com/dyninst/dyninst/issues/1394)) +- warning fix: std::random_shuffle is deprecated ([1394](https://github.com/dyninst/dyninst/issues/1394)) +- warning fix: missing noexcept ([1394](https://github.com/dyninst/dyninst/issues/1394)) +- warning fix: std::iterator is deprecated ([1394](https://github.com/dyninst/dyninst/issues/1394)) +- warning fix: unused private field ([1394](https://github.com/dyninst/dyninst/issues/1394)) +- warning fix: deprecated copy/op= with user provided dtor ([1394](https://github.com/dyninst/dyninst/issues/1394)) +- warning fix: remove unused variables/members ([1394](https://github.com/dyninst/dyninst/issues/1394)) +- warning fix: shadow (variables) ([1394](https://github.com/dyninst/dyninst/issues/1394)) +- warning fix: shadow (enumerator names) ([1394](https://github.com/dyninst/dyninst/issues/1394)) +- replace C-style and functional casts ([1394](https://github.com/dyninst/dyninst/issues/1394)) +- write_memory_as to append_memory_as as appropriate ([1394](https://github.com/dyninst/dyninst/issues/1394)) +- warning fix: increased alignment cast (C casts) ([1394](https://github.com/dyninst/dyninst/issues/1394)) +- warning fix: increased alignment cast (pointers) ([1394](https://github.com/dyninst/dyninst/issues/1394)) +- warning fix: increased alignment cast ([1394](https://github.com/dyninst/dyninst/issues/1394)) +- warning fix: pessimizing move ([1394](https://github.com/dyninst/dyninst/issues/1394)) +- warning fix: missing override ([1394](https://github.com/dyninst/dyninst/issues/1394)) +- warning fix: tautological always true comparison ([1394](https://github.com/dyninst/dyninst/issues/1394)) +- warning fix: mismatched class/struct ([1394](https://github.com/dyninst/dyninst/issues/1394)) +- warning fix: [[fallthrough]] requires C++ 17 ([1394](https://github.com/dyninst/dyninst/issues/1394)) +- Restore PPC special-purpose registers in opposite order of saving them ([1392](https://github.com/dyninst/dyninst/issues/1392)) +- Aarch64: Fix restoring special purpose registers order ([1000](https://github.com/dyninst/dyninst/issues/1000)) +- Avoid possible copy in BPatch::createEnum ([1390](https://github.com/dyninst/dyninst/issues/1390)) +- Merge pull request #1389 from dyninst/wuxx1279/gfx908/clang-error +- add InstructionDecoderImpl::makeRegisterExpression to derived classes +- Fix virtual derived signature to match base class +- Update DwarfWalker subrange handling ([1369](https://github.com/dyninst/dyninst/issues/1369)) +- use default allocator for tbb::concurrent_hash_map ([1332](https://github.com/dyninst/dyninst/issues/1332)) +- fix infinite recursion in LineInformation::addLine ([1331](https://github.com/dyninst/dyninst/issues/1331)) +- eliminate deprecated C++ function objects ([1331](https://github.com/dyninst/dyninst/issues/1331)) +- Fix BinaryEdit::getResolvedLibraryPath for Ubuntu 22.04 ([1362](https://github.com/dyninst/dyninst/issues/1362)) +- Make SymtabCodeSource constructor const correct ([1293](https://github.com/dyninst/dyninst/issues/1293)) +- SymtabAPI::Type: add support for C++ r-value references ([1159](https://github.com/dyninst/dyninst/issues/1159)) +- Improve DWARF enum parsing in Symtab::Type ([1164](https://github.com/dyninst/dyninst/issues/1164)) +- Update global ELF ctor/dtor instrumentation for static executables ([1355](https://github.com/dyninst/dyninst/issues/1355)) + + +## [12.3.0](https://github.com/dyninst/dyninst/tree/v12.3.0) (2023-02-22) +[Full Changelog](https://github.com/dyninst/dyninst/compare/v12.2.1...v12.3.0) + +- Add missing includes ([1385](https://github.com/dyninst/dyninst/issues/1385)) +- explicitly include ([1384](https://github.com/dyninst/dyninst/issues/1384)) +- remove trailing usage of cout.clear ([1383](https://github.com/dyninst/dyninst/issues/1383)) +- Fix all-through instructions for newly added AMD gpu gfx908 ([1381](https://github.com/dyninst/dyninst/issues/1381)) +- Added support for gfx908 based on the XML-ISA-DROP for MI100 ([1283](https://github.com/dyninst/dyninst/issues/1283)) +- Allow CFG analysis based on instructionAPI alone w/out semantics ([1379](https://github.com/dyninst/dyninst/issues/1379)) +- Prevent fall-through analysis of amd gpu swap/set pc instructions ([1376](https://github.com/dyninst/dyninst/issues/1376)) +- x86 8-bit immediate values were interpreted incorrectly cross-platform. ([1373](https://github.com/dyninst/dyninst/issues/1373)) +- update spack.yaml for spack v0.19.1 ([1367](https://github.com/dyninst/dyninst/issues/1367)) +- Remove use of couts in the AMDGPU instruction decoders ([1371](https://github.com/dyninst/dyninst/issues/1371)) +- handle ENDBR64 ([1368](https://github.com/dyninst/dyninst/issues/1368)) +- Fixed nullptr issues in dyninstAPI/src/mapped_object.C ([1361](https://github.com/dyninst/dyninst/issues/1361)) +- Fix sema type for vex2 encoded vpand ([1364](https://github.com/dyninst/dyninst/issues/1364)) +- Replace DwarfWalker::findString with DwarfWalker::find_call_file ([1360](https://github.com/dyninst/dyninst/issues/1360)) +- Update detection of DWARF languages ([1357](https://github.com/dyninst/dyninst/issues/1357)) +- Remove AObject::pickLanguage ([1358](https://github.com/dyninst/dyninst/issues/1358)) +- BPatch_snippet::generateArrayRef - fix possible null pointer access ([1356](https://github.com/dyninst/dyninst/issues/1356)) +- Use instrumentation logging in baseTramp::guarded ([1354](https://github.com/dyninst/dyninst/issues/1354)) +- Remove special global ctor/dtor search in ppc for static binaries ([1353](https://github.com/dyninst/dyninst/issues/1353)) +- Refactor common/src/Types.h ([1351](https://github.com/dyninst/dyninst/issues/1351)) +- add missing include file ([1344](https://github.com/dyninst/dyninst/issues/1344)) +- Remove dead implementation of IA_power::isLinkerStub ([1342](https://github.com/dyninst/dyninst/issues/1342)) +- Lookup functions in the binding table directly ([1337](https://github.com/dyninst/dyninst/issues/1337)) +- Remove outdated Boost version checks ([1329](https://github.com/dyninst/dyninst/issues/1329)) + +## [12.2.1](https://github.com/dyninst/dyninst/tree/v12.2.1) (2022-11-21) +[Full Changelog](https://github.com/dyninst/dyninst/compare/v12.2.0...v12.2.1) + +- Fix shadowing of 'filename' member in Elf_X::findDebugFile ([1325](https://github.com/dyninst/dyninst/issues/1325)) +- Ignore unknown pragma warnings when building without OpenMP ([1324](https://github.com/dyninst/dyninst/issues/1324)) +- fix Instruction class to allow valid assignment ([1323](https://github.com/dyninst/dyninst/issues/1323)) +- ParseAPI: improve tail call recognition ([1315](https://github.com/dyninst/dyninst/issues/1315)) +- Support hash_compare concept from TBB >= 2021.1 ([1316](https://github.com/dyninst/dyninst/issues/1316)) +- Remove unused TBB from parseAPI ([1317](https://github.com/dyninst/dyninst/issues/1317)) +- Use dyn_c_hash_map in DwarfWalker ([1318](https://github.com/dyninst/dyninst/issues/1318)) +- Directly link to common in dynC_API ([1319](https://github.com/dyninst/dyninst/issues/1319)) +- Manually add hex prefix when formatting an Operand ([1313](https://github.com/dyninst/dyninst/issues/1313)) +- Allow assignment conversion without framepointer ([1314](https://github.com/dyninst/dyninst/issues/1314)) +- Fix incorrect format string in Result.h for u48 / s48 / u64 / s64 ([1311](https://github.com/dyninst/dyninst/issues/1311)) +- Do not build dyninstAPI_RT as separate CMake project ([1309](https://github.com/dyninst/dyninst/issues/1309)) +- Fix possible null pointer access in BPatch_module::findFunctionByAddress ([1308](https://github.com/dyninst/dyninst/issues/1308)) +- Search 'elfutils' subdirectory for libdebuginfod/includedir ([1307](https://github.com/dyninst/dyninst/issues/1307)) +- Fix public header deletes ([1301](https://github.com/dyninst/dyninst/issues/1301)) +- fix location list PC range values ([1297](https://github.com/dyninst/dyninst/issues/1297)) +- Docker - use ppa for gcc11 ([1291](https://github.com/dyninst/dyninst/issues/1291)) + +## [12.2.0](https://github.com/dyninst/dyninst/tree/v12.2.0) (2022-07-28) +[Full Changelog](https://github.com/dyninst/dyninst/compare/v12.1.0...v12.2.0) + +- Add exec entry point to parse hints is missing +- fix races with parallel analysis of cubins ([1284](https://github.com/dyninst/dyninst/issues/1284)) +- Docker: make build.sh verbose, fix file copy bug in Dockerfile.test ([1273](https://github.com/dyninst/dyninst/issues/1273)) +- Remove endian CMake check ([1270](https://github.com/dyninst/dyninst/issues/1270)) +- Update and enforce formatting of CMake files ([1267](https://github.com/dyninst/dyninst/issues/1267)) +- Fix bug in processing library paths in FindLibIberty.cmake ([1266](https://github.com/dyninst/dyninst/issues/1266)) +- Fix decoding of DWARF expressions into machine registers for Intel GPUs ([1262](https://github.com/dyninst/dyninst/issues/1262)) +- Docker: don't use autamus cache ([1259](https://github.com/dyninst/dyninst/issues/1259)) +- Remove unused build options ([1253](https://github.com/dyninst/dyninst/issues/1253)) +- Fix dyninstAPI_RT files to build with older glibc ([1252](https://github.com/dyninst/dyninst/issues/1252)) +- Redo finalization to get correct function boundiaries when ([1249](https://github.com/dyninst/dyninst/issues/1249)) +- Fix format string errors in stackwalk/callchecker.C ([1250](https://github.com/dyninst/dyninst/issues/1250)) +- Make dyninstAPI_RT files build with standard C ([1246](https://github.com/dyninst/dyninst/issues/1246)) +- Add cmake options for C/C++ language standards ([1246](https://github.com/dyninst/dyninst/issues/1246)) +- Use bfd linker for LTO ([1248](https://github.com/dyninst/dyninst/issues/1248)) +- Cleanup (remove) ancient linux kernel support ([1241](https://github.com/dyninst/dyninst/issues/1241)) +- remove unused files containing pragmas ([1240](https://github.com/dyninst/dyninst/issues/1240)) +- Remove unneeded #pragma's ([1240](https://github.com/dyninst/dyninst/issues/1240)) +- Add compiler warning related cmake options ([1239](https://github.com/dyninst/dyninst/issues/1239)) +- Add cmake option to disable diagnostic suppressions ([1239](https://github.com/dyninst/dyninst/issues/1239)) +- Fix frame-larger-than warning ([1239](https://github.com/dyninst/dyninst/issues/1239)) +- Remove MSC compiler warning suppressions ([1239](https://github.com/dyninst/dyninst/issues/1239)) +- Improve compiler diagnostic suppression handling ([1239](https://github.com/dyninst/dyninst/issues/1239)) +- Remove unused git files ([1244](https://github.com/dyninst/dyninst/issues/1244)) +- Docker: make compile warnings fatal ([1242](https://github.com/dyninst/dyninst/issues/1242)) +- Docker: use external-tests instead of testsuite in base image ([1209](https://github.com/dyninst/dyninst/issues/1209)) +- Docker: don't build Dyninst through spack for the environment ([1222](https://github.com/dyninst/dyninst/issues/1222)) +- Docker: use more OS packages for dependencies ([1221](https://github.com/dyninst/dyninst/issues/1221)) +- Remove void pointer arithmetic when using Valgrind annotations ([1236](https://github.com/dyninst/dyninst/issues/1236)) +- Add parsing of names for inlined functions in DWARF ([1237](https://github.com/dyninst/dyninst/issues/1237)) +- Remove BUILD_RT option ([1238](https://github.com/dyninst/dyninst/issues/1238)) +- Fix warnings with cmake's MINSIZEREL build type ([1235](https://github.com/dyninst/dyninst/issues/1235)) +- Correctly propagate pc ranges for blocks and local variables ([1226](https://github.com/dyninst/dyninst/issues/1226)) +- Docker: testing workflow to run libabigail ([1220](https://github.com/dyninst/dyninst/issues/1220)) +- Remove usage of DW_AT_MIPS_linkage_name ([1223](https://github.com/dyninst/dyninst/issues/1223)) +- Docker: adding a workflow for release ([1219](https://github.com/dyninst/dyninst/issues/1219)) +- Merge pull request #1217 from dyninst/thaines/docker_base_container_defaults +- Update dependency versions in base container config + +## [12.1.0](https://github.com/dyninst/dyninst/tree/v12.1.0) (2022-03-09) +[Full Changelog](https://github.com/dyninst/dyninst/compare/v12.0.1...v12.1.0) + +- Correctly handle DWARF subroutines during parallel parsing ([1215](https://github.com/dyninst/dyninst/issues/1215)) +- Docker: simplify build script ([1212](https://github.com/dyninst/dyninst/issues/1212)) +- Make a couple constant 64-bit ULL to avoid getting truncated during shifts ([1207](https://github.com/dyninst/dyninst/issues/1207)) +- Docker: use more OS packages ([1211](https://github.com/dyninst/dyninst/issues/1211)) +- Fix potential buffer overrun in AMDGPU decoders ([1208](https://github.com/dyninst/dyninst/issues/1208)) +- Code clean up for AMDGPU ([1205](https://github.com/dyninst/dyninst/issues/1205)) +- Tidy up classes in AMDGPU ([1204](https://github.com/dyninst/dyninst/issues/1204)) +- Fix compiler warnings in amdgpu cdna2 code ([1198](https://github.com/dyninst/dyninst/issues/1198)) +- Build fixes for amdgpu/cdna2 ([1203](https://github.com/dyninst/dyninst/issues/1203)) +- Add Support for AMDGPU CDNA2 Architectures based on XML ISA spec ([1107](https://github.com/dyninst/dyninst/issues/1107)) +- fix building of symlite ([1197](https://github.com/dyninst/dyninst/issues/1197)) +- Additional cleanup of memory emulation for hybrid analysis ([1172](https://github.com/dyninst/dyninst/issues/1172)) +- Allow zero-length ELF program headers ([1192](https://github.com/dyninst/dyninst/issues/1192)) +- Remove dead code and variables related to Symtab::data_ptr_ and Symtab::code_ptr_ ([1192](https://github.com/dyninst/dyninst/issues/1192)) +- Remove dead code Object::elf_vaddr_to_ptr ([1192](https://github.com/dyninst/dyninst/issues/1192)) +- glibc r_debug extensions to support multiple namespaces ([1175](https://github.com/dyninst/dyninst/issues/1175)) +- Symtab::module documentation cleanup ([1189](https://github.com/dyninst/dyninst/issues/1189)) +- Dockerfile: use explicit packages for 'spack external find' ([1195](https://github.com/dyninst/dyninst/issues/1195)) +- ParseAPI: Speed up the case where a function is called from many locations ([1190](https://github.com/dyninst/dyninst/issues/1190)) +- ELF+DWARF: always parse first entry in source file table ([1184](https://github.com/dyninst/dyninst/issues/1184)) +- Remove interposed definition of _r_debug ([1176](https://github.com/dyninst/dyninst/issues/1176)) +- start of work to add automated testing to dyninst! ([1183](https://github.com/dyninst/dyninst/issues/1183)) +- adding dyninst release trigger ([1181](https://github.com/dyninst/dyninst/issues/1181)) +- fixing workflow trigger ([1182](https://github.com/dyninst/dyninst/issues/1182)) +- Adding first stage of automated docker build ([1180](https://github.com/dyninst/dyninst/issues/1180)) +- Remove erroneous use of realloc in symtabAPI/Type-mem.h ([1170](https://github.com/dyninst/dyninst/issues/1170)) +- Clean up memoryTracker usage in binaryEdit ([877](https://github.com/dyninst/dyninst/issues/877)) + + +## [12.0.1](https://github.com/dyninst/dyninst/tree/v12.0.1) (2021-11-23) +[Full Changelog](https://github.com/dyninst/dyninst/compare/v12.0.0...v12.0.1) + +**Build Changes** + +- Remove NVIDIA external line map configure check ([1162](https://github.com/dyninst/dyninst/issues/1162)) +- Increase minimum elfutils version to 0.186 ([1161](https://github.com/dyninst/dyninst/issues/1161)) +- Add conflict with CMake 3.19.0 ([1153](https://github.com/dyninst/dyninst/issues/1153)) + +**Enhancements** + +- Refactor dwarfWalker::findConst ([1160](https://github.com/dyninst/dyninst/issues/1160)) +- Add readable name for Symtab::typeRef ([1157](https://github.com/dyninst/dyninst/issues/1157)) +- DwarfWalker: clean up interfaces for findDieName and findName ([1154](https://github.com/dyninst/dyninst/issues/1154)) +- Added automated docker build for development and testing + +## [12.0.0](https://github.com/dyninst/dyninst/tree/v12.0.0) (2021-11-11) +[Full Changelog](https://github.com/dyninst/dyninst/compare/v11.0.1...v12.0.0) + +**GPU Support** + +- Add CMake test to check if libdw supports NVIDIA extended line map +- Adjust interface changes in elfutils regarding NVIDIA extended line map +- Add compile-time checking to see if elfutils support nvidia extended line map when the user have specified ENABLE_NVIDIA_EXT_LINE_MAP +- Fix compilation warning and add cmake option ENABLE_NVIDIA_EXT_LINE_MAP +- 1. Handle unrelocated line map entries for CUBIN 2. Remove redundant addFunctionRange call to improve performance 3. Add some debug logging +- Inline context from nvidia extended line map identifies an inlined call path +- Start to construct inlining call chains using Nvidia's extended line map +- cleaning up code for ingesting nvidia extended linemaps +- first draft of support for nvidia enhanced line maps + +**Enhancements** + +- Load callee's address when the callee and caller are in the same module ([1056](https://github.com/dyninst/dyninst/issues/1056)) +- Give global annotation objects internal linkage and file scope +- Summit fixes ([1108](https://github.com/dyninst/dyninst/issues/1108)) +- Add x86 xsavec instruction ([1074](https://github.com/dyninst/dyninst/issues/1074)) +- Convert TRAMP_\*_OFFSET macros to functions ([1073](https://github.com/dyninst/dyninst/issues/1073)) +- Add x86_64 xrstor instruction ([1070](https://github.com/dyninst/dyninst/issues/1070)) +- Fix insertion operators in BPatch and Symtab ([1069](https://github.com/dyninst/dyninst/issues/1069)) +- Add DWARF4 base type entry encodings to symtabAPI::typeScalar ([1059](https://github.com/dyninst/dyninst/issues/1059)) +- Add xsave instruction ([1055](https://github.com/dyninst/dyninst/issues/1055)) +- Cleanup orphaned code ([1064](https://github.com/dyninst/dyninst/issues/1064)) + +**ABI Breakages** +- Remove AddressSpace::causeTemplateInstantiations ([1149](https://github.com/dyninst/dyninst/issues/1149)) +- Remove unregisterTrapMapping from PCProcess +- Remove thread registration functions from PCProcess +- Remove PCProcess::getDeadCode +- Remove memory emulation ([1146](https://github.com/dyninst/dyninst/issues/1146)) +- Remove unused generateSimple ([1122](https://github.com/dyninst/dyninst/issues/1122)) +- Remove unused variables from Symtab +- Remove special Fortran debug handling +- Remove stabs from symbol demangling +- Remove stabs from BPatch +- Remove stabs from SymtabAPI +- Remove Module::getAllVariables ([1066](https://github.com/dyninst/dyninst/issues/1066)) + +**Documentation** + +- Improve docs for lookup functions in CodeObject ([1147](https://github.com/dyninst/dyninst/issues/1147)) +- Update copyright to 2022 ([1141](https://github.com/dyninst/dyninst/issues/1141)) +- Remove stabs from documentation ([1120](https://github.com/dyninst/dyninst/issues/1120)) + +**Build Changes** +- Remove ppc32 from builds ([1145](https://github.com/dyninst/dyninst/issues/1145)) +- Unify meaning of 'cap_32_64' macro ([1136](https://github.com/dyninst/dyninst/issues/1136)) +- Remove support for Cray CNL ([1137](https://github.com/dyninst/dyninst/issues/1137)) +- Remove xlc macros ([1132](https://github.com/dyninst/dyninst/issues/1132)) +- Remove common/src/language.h ([1131](https://github.com/dyninst/dyninst/issues/1131)) +- Remove usage of arch_ppc and arch_ppc64 ([1129](https://github.com/dyninst/dyninst/issues/1129)) +- Remove usage of x86_64_cnl ([1130](https://github.com/dyninst/dyninst/issues/1130)) +- Remove DynC tests ([1126](https://github.com/dyninst/dyninst/issues/1126)) +- Remove NO_INITIALIZER_LIST_SUPPORT ([1125](https://github.com/dyninst/dyninst/issues/1125)) +- Turn on STERILE_BUILD by default ([1118](https://github.com/dyninst/dyninst/issues/1118)) +- update minimum boost version to 1.70.0 ([1117](https://github.com/dyninst/dyninst/issues/1117)) +- Remove boost_system linking ([1112](https://github.com/dyninst/dyninst/issues/1112)) +- Enforce detection of libiberty ([1099](https://github.com/dyninst/dyninst/issues/1099)) +- fix compiler warnings to work with clang ([1092](https://github.com/dyninst/dyninst/issues/1092)) +- update optimization (-Og) and debug flags (-g3) ([1084](https://github.com/dyninst/dyninst/issues/1084)) +- use the C11 standard for C code in Dyninst ([1086](https://github.com/dyninst/dyninst/issues/1086)) +- Make Dyninst buildable with Clang ([1021](https://github.com/dyninst/dyninst/issues/1021)) +- Remove valueAdded subdirectory completely ([1065](https://github.com/dyninst/dyninst/issues/1065)) +- Remove valueAdded subdirectory ([1063](https://github.com/dyninst/dyninst/issues/1063)) + +**Bug Fixes** +- fix statement-like macros ([1143](https://github.com/dyninst/dyninst/issues/1143)) +- Don't overflow aarch64 float register vector when setting used regs. ([1127](https://github.com/dyninst/dyninst/issues/1127)) +- fix unused const variable warnings +- fix pessimizing std::move warnings +- fix xor operator used as power operator +- fix misleading indentation warning +- fix uninitialized this and variable warnings +- fix float to double promotion warning +- fix unused const variable warnings +- Fix possible buffer overflow in BPatch::processCreate +- Fix uninitialized variable use in DispatcherARM64::iproc_init +- remove executable flag from .dyninst_heap section ([1096](https://github.com/dyninst/dyninst/issues/1096)) +- fix broken cast of a char literal to pointer ([1090](https://github.com/dyninst/dyninst/issues/1090)) +- fix possibly uninitialized variables ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- fix possible null 'this' pointer dereference ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- prevent maybe uninitialized warning ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- adjust large frame threshold for specific sources ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- fix deprecated implicit assignment operator ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- fix buffer overflow ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- fix duplicate branch condition by removing branch ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- fix out of bounds array access ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- fix potentially uninitialized variable warning ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- use unused variable to correct code ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- remove unused variables ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- make printf format and argument types match ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- fix broken bool expression that was always true ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- add missing initializer braces ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- make constructor public so class is usable ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- remove ';' after in-class method definitions ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- eliminate logical op warning ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- make implicit double promotions explicit ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- annotate malloc-like functions ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- make method noexcept, so noexcept expr can be true ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- add missing default to switch statement ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- fix int to void\* cast if sizeof(int) ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- fix unused vars/params/funcs on aarch64 ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- fix ambiguous type name warning ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- remove always true || sub-expression ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- fix possible sprintf buffer overflow ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- delete unnecessary ambiguous forward class decl ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- make destructor virtual if a virtual method exist ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- make printf format and argument signedness match ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- make printf format and argument types match ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- add compiler annotation to printf-like functions ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- fix var-tracking-assignments warnings ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- remove assert(this) as 'this' should never be null ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- remove obvious null pointer dereference ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- fix for C++20 removal of std::allocator methods ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- make cmp function object operator() a const func ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- make Boost and TBB include dirs be system includes ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- fix shadow variable warning, has other brokenness ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- fix duplicate branch warnings ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- eliminate switch case fall through warnings ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- explicit base class initialization in constructor ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- remove default argument from lambda ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- remove non-C++ compound literal ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- do not compile empty compilation units ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- fix deprecated implicit copy constructor if dtor ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- add missing copy assignment ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- fix illegal in C empty brace initialization ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- disable flexible array member warning in C++ ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- fix discard qualifiers: make char\* -> const char\* ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- fix non-standard use of \_\_VA_ARGS\_\_ ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- remove excess semicolons as reported by -pedantic ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- fix overflow warning for 0x90 assigned to a char ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- fix illegal function pointer to void\* compare ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- remove use of GNU binary operator ?: ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- remove non-C++ variable length arrays ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- make printf format and argument types match ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- fix shadow identifier warnings ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- enable more warnings and test compiler support ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- miscellaneous compiler warning cleanups ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- eliminate switch case fall through warnings ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- add header with compiler annotation macros ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- add missing break statements ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- compute num array elements instead of fixed values ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- remove dynamic_ and dynamic() from fileDescriptor ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- remove emptyString static members ([1082](https://github.com/dyninst/dyninst/issues/1082)) +- delete unnecessary .DS_Store file ([1082](https://github.com/dyninst/dyninst/issues/1082)) + + ## [11.0.1](https://github.com/dyninst/dyninst/tree/v11.0.1) (2021-06-14) [Full Changelog](https://github.com/dyninst/dyninst/compare/v11.0.0...v11.0.1) diff --git a/CMakeLists.txt b/CMakeLists.txt index 89e9162bda..5174c479f0 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -1,237 +1,68 @@ -cmake_minimum_required (VERSION 3.4.0) -project (Dyninst) +cmake_minimum_required(VERSION 3.14.0 FATAL_ERROR) -set (DYNINST_ROOT ${PROJECT_SOURCE_DIR}) -set (CMAKE_SKIP_BUILD_RPATH FALSE) -set (CMAKE_BUILD_WITH_INSTALL_RPATH FALSE) -set (CMAKE_INSTALL_RPATH_USE_LINK_PATH TRUE) -set (CMAKE_EXPORT_COMPILE_COMMANDS ON) - -set(STERILE_BUILD OFF CACHE BOOL "Do not download/build any third-party dependencies from source") - -LIST(FIND CMAKE_PLATFORM_IMPLICIT_LINK_DIRECTORIES - "${CMAKE_INSTALL_PREFIX}/lib" isSystemDir) -IF("${isSystemDir}" STREQUAL "-1") - set (CMAKE_INSTALL_RPATH "${CMAKE_INSTALL_PREFIX}/lib") -ENDIF() - -set(RT_SOURCE_DIR ${DYNINST_ROOT}/dyninstAPI_RT) -set(RT_BINARY_DIR ${PROJECT_BINARY_DIR}/dyninstAPI_RT) - -set (CMAKE_MODULE_PATH "${DYNINST_ROOT}/cmake" "${DYNINST_ROOT}/cmake/Modules" ${CMAKE_MODULE_PATH}) - -# Set the C and C++ language standards -include(LanguageStandards) - -# Find the necessary third-party libraries -find_package(ThreadDB) -find_package(Threads) -include(Boost) -include(ThreadingBuildingBlocks) -include(ElfUtils) - -if(UNIX) - include(LibIberty REQUIRED) -endif() - -include(shared) - -if(USE_OpenMP) - find_package(OpenMP REQUIRED) -endif() - -configure_file(cmake/version.h.in common/h/dyninstversion.h) -include_directories(${PROJECT_BINARY_DIR}) -include_directories(${PROJECT_BINARY_DIR}/common/h) -set (HEADER_DIRS common - dataflowAPI - dyninstAPI - instructionAPI - parseAPI - patchAPI - proccontrol - stackwalk - symtabAPI - ) -if(NOT ${PLATFORM} MATCHES nt) - set (HEADER_DIRS ${HEADER_DIRS} - dwarf - elf - symlite - ) -endif() - - - -foreach (dir ${HEADER_DIRS}) - include_directories ( ${DYNINST_ROOT}/${dir}/h ) -endforeach() - -set(ADD_VALGRIND_ANNOTATIONS OFF CACHE BOOL "Enable annotations for Valgrind analysis") -if(ADD_VALGRIND_ANNOTATIONS) - find_package(Valgrind REQUIRED) - include_directories(${Valgrind_INCLUDE_DIRS}) - add_definitions(-DENABLE_VG_ANNOTATIONS) -endif() - -include_directories ( - ${DYNINST_ROOT} - ${DYNINST_ROOT}/external - ${TBB_INCLUDE_DIRS} - ) - -# Component time -add_subdirectory (common) -if(NOT ${PLATFORM} MATCHES nt) - add_subdirectory (elf) - add_subdirectory (dwarf) - add_subdirectory (symlite) - add_subdirectory (parseThat) -endif() -add_subdirectory (instructionAPI) -add_subdirectory (symtabAPI) -add_subdirectory (parseAPI) -add_subdirectory (proccontrol) -add_subdirectory (stackwalk) -add_subdirectory (patchAPI) - -if(${SYMREADER} MATCHES symtabAPI) - add_subdirectory (dyninstAPI) - add_subdirectory (dynC_API) -endif() - -if(BUILD_RTLIB) - # Build the RT library as a separate project so we can change compilers - message(STATUS "Configuring DyninstAPI_RT in ${RT_BINARY_DIR}") - file(REMOVE_RECURSE ${RT_BINARY_DIR}/CMakeCache.txt ${RT_BINARY_DIR}/CMakeFiles ${RT_BINARY_DIR}/Makefile) - file(MAKE_DIRECTORY ${RT_BINARY_DIR}) - set (RT_C_COMPILER ${CMAKE_C_COMPILER} CACHE STRING "Compiler for runtime library") - set (ENABLE_STATIC_LIBS NO CACHE STRING "Build static libraries as well?") - message(STATUS "Configuring RT library") - - execute_process(WORKING_DIRECTORY ${RT_BINARY_DIR} - COMMAND ${CMAKE_COMMAND} - -DCMAKE_C_COMPILER=${RT_C_COMPILER} - -DCMAKE_BUILD_TYPE=${CMAKE_BUILD_TYPE} - -DCMAKE_INSTALL_PREFIX=${CMAKE_INSTALL_PREFIX} - -DCMAKE_PREFIX_PATH=${CMAKE_PREFIX_PATH} - -DINSTALL_LIB_DIR=${INSTALL_LIB_DIR} - -DINSTALL_INCLUDE_DIR=${INSTALL_INCLUDE_DIR} - -DCMAKE_C_FLAGS=${CMAKE_C_FLAGS} - -DBUILD_RTLIB_32=${BUILD_RTLIB_32} - -DPLATFORM=${PLATFORM} - -G ${CMAKE_GENERATOR} - -B ${RT_BINARY_DIR} - -S ${RT_SOURCE_DIR}) - find_file(${RT_MAKEFILE} Makefile PATHS ${RT_BINARY_DIR} NO_DEFAULT_PATH) - message(STATUS "RTlib Makefile: ${RT_MAKEFILE}") - if(MSVC) - include_external_msproject(DyninstAPI_RT dyninstAPI_RT/dyninstAPI_RT.vcxproj) - include_external_msproject(DyninstAPI_RT_static dyninstAPI_RT/dyninstAPI_RT_static.vcxproj) - else() - add_custom_target(DyninstRT - ALL - $(MAKE) - WORKING_DIRECTORY ${RT_BINARY_DIR} - COMMENT "Building DyninstRT") - if(TARGET TBB) - add_dependencies(DyninstRT TBB) - endif() - add_dependencies(dyninstAPI DyninstRT) - if(TARGET dyninstAPI-static) - add_dependencies(dyninstAPI-static DyninstRT) - endif() - if(TARGET boost) - add_dependencies(DyninstRT boost) - endif() - endif() - - install(SCRIPT "${RT_BINARY_DIR}/cmake_install.cmake") - -else() - message(STATUS "Skipping DyninstAPI_RT. Be sure to build this library if you're using instrumentation.") -endif() -set (VERSION_STRING "${DYNINST_MAJOR_VERSION}.${DYNINST_MINOR_VERSION}.${DYNINST_PATCH_VERSION}") -set (DYNINST_NAME "DyninstAPI-${VERSION_STRING}") - -if(BUILD_TARBALLS) - find_package(Git) - if(GIT_FOUND) - if(EXISTS "${DYNINST_ROOT}/.git/") - message(STATUS "Source tree is repository, building archive target") - add_custom_target(package ALL) - add_custom_command(TARGET package - COMMAND ${GIT_EXECUTABLE} archive --prefix="${DYNINST_NAME}/" --format=tar.gz -o "${CMAKE_BINARY_DIR}/${DYNINST_NAME}.tgz" HEAD - WORKING_DIRECTORY ${DYNINST_ROOT} - COMMENT "Packaging Dyninst") - endif() - endif() -endif() -if(BUILD_DOCS) - add_custom_target(doc) - set(LATEX_DOCS dynC_API dataflowAPI instructionAPI parseAPI patchAPI symtabAPI stackwalk) - set(WORD_DOCS proccontrol dyninstAPI) - add_custom_target(proccontrol-doc - DEPENDS ${CMAKE_SOURCE_DIR}/proccontrol/doc/proccontrol.pdf) - add_custom_target(dyninstAPI-doc - DEPENDS ${CMAKE_SOURCE_DIR}/dyninstAPI/doc/dyninstAPI.pdf) - foreach(COMPONENT ${WORD_DOCS}) - add_dependencies(doc ${COMPONENT}-doc) - set_target_properties(${COMPONENT}-doc PROPERTIES EXCLUDE_FROM_DEFAULT_BUILD 1) - install(FILES ${CMAKE_CURRENT_BINARY_DIR}/${COMPONENT}/doc/${COMPONENT}.pdf - DESTINATION ${INSTALL_DOC_DIR} - RENAME ${COMPONENT}-${VERSION_STRING}.pdf - OPTIONAL - ) - endforeach() - - find_package(LATEX) - if(PDFLATEX_COMPILER) - file(COPY ${CMAKE_CURRENT_SOURCE_DIR}/common/doc - DESTINATION ${CMAKE_CURRENT_BINARY_DIR}/common) - foreach(COMPONENT ${LATEX_DOCS}) - file(COPY ${CMAKE_CURRENT_SOURCE_DIR}/${COMPONENT}/doc - DESTINATION ${CMAKE_CURRENT_BINARY_DIR}/${COMPONENT}) - set (DEPS "") - file(GLOB_RECURSE DEPS ${CMAKE_CURRENT_SOURCE_DIR}/${COMPONENT}/doc/*.tex ${CMAKE_CURRENT_SOURCE_DIR}/common/doc/*.tex) - add_custom_command( - OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/${COMPONENT}/doc/${COMPONENT}.aux - DEPENDS ${DEPS} - COMMAND ${PDFLATEX_COMPILER} - ARGS -interaction=batchmode ${COMPONENT}.tex - WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}/${COMPONENT}/doc - COMMENT "Latex (first pass)" - ) - add_custom_command( - OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/${COMPONENT}/doc/${COMPONENT}.log - DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/${COMPONENT}/doc/${COMPONENT}.aux - COMMAND ${PDFLATEX_COMPILER} - ARGS -interaction=batchmode ${COMPONENT}.tex - WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}/${COMPONENT}/doc - COMMENT "Latex (second pass)" - ) - add_custom_target(${COMPONENT}-doc echo - DEPENDS ${CMAKE_CURRENT_BINARY_DIR}/${COMPONENT}/doc/${COMPONENT}.log - ) - add_dependencies(doc ${COMPONENT}-doc) - set_target_properties(${COMPONENT}-doc PROPERTIES EXCLUDE_FROM_DEFAULT_BUILD 1) - install(FILES ${CMAKE_CURRENT_BINARY_DIR}/${COMPONENT}/doc/${COMPONENT}.pdf - DESTINATION ${INSTALL_DOC_DIR} - RENAME ${COMPONENT}-${VERSION_STRING}.pdf - OPTIONAL - ) - endforeach() - else() - message(STATUS "LaTeX not found") - endif() +# There is a bug in 3.19.0 that causes .S files to be treated like C files +if(CMAKE_VERSION VERSION_EQUAL "3.19.0") + message(FATAL_ERROR "Dyninst cannot use CMake version 3.19.0") endif() -if(TARGET boost) - add_dependencies(common boost) +# find_package() uses upper-case _ROOT variables. +if(POLICY CMP0144) + cmake_policy(SET CMP0144 NEW) endif() -#add_subdirectory(testsuite) - -# Copy out all of the cmake files so they can be used by the Testsuite -install(DIRECTORY ${DYNINST_ROOT}/cmake/ DESTINATION ${INSTALL_CMAKE_DIR}) -install(FILES ${PROJECT_BINARY_DIR}/CMakeCache.txt DESTINATION ${INSTALL_CMAKE_DIR}) +set(DYNINST_MAJOR_VERSION 13) +set(DYNINST_MINOR_VERSION 0) +set(DYNINST_PATCH_VERSION 0) + +set(DYNINST_SOVERSION "${DYNINST_MAJOR_VERSION}.${DYNINST_MINOR_VERSION}") +set(DYNINST_VERSION "${DYNINST_SOVERSION}.${DYNINST_PATCH_VERSION}") + +project( + Dyninst + VERSION ${DYNINST_VERSION} + DESCRIPTION "Tools for binary instrumentation, analysis, and modification" + HOMEPAGE_URL "https://github.com/dyninst/dyninst" + LANGUAGES C CXX ASM) + +list(INSERT CMAKE_MODULE_PATH 0 "${PROJECT_SOURCE_DIR}/cmake" + "${PROJECT_SOURCE_DIR}/cmake/tpls" "${PROJECT_SOURCE_DIR}/cmake/Modules") + +# Add dyncompat headers (boost replacement) +include_directories(SYSTEM "${PROJECT_SOURCE_DIR}") + +# These need to be done before anything else +include(DyninstLibrarySettings) +include(DyninstOptions) + +# Set up Dyninst internals +include(DyninstPlatform) +include(DyninstCapArchDef) +include(DyninstLanguageStandards) +include(DyninstWarnings) +include(DyninstOptimization) + +# Locate third-party libraries +include(DyninstThreads) +include(DyninstTBB) +include(DyninstElfUtils) +include(DyninstLibIberty) +include(DyninstThread_DB) +include(DyninstValgrind) +include(DyninstOpenMP) + +add_subdirectory(common) +add_subdirectory(elf) +add_subdirectory(dwarf) +add_subdirectory(symlite) +add_subdirectory(instructionAPI) +add_subdirectory(symtabAPI) +add_subdirectory(parseAPI) +add_subdirectory(proccontrol) +add_subdirectory(stackwalk) +add_subdirectory(patchAPI) +add_subdirectory(dyninstAPI) +add_subdirectory(dynC_API) +add_subdirectory(parseThat) +add_subdirectory(dyninstAPI_RT) + +include(DyninstInstall) diff --git a/COPYRIGHT b/COPYRIGHT index 2ce59090ad..7f2698291b 100644 --- a/COPYRIGHT +++ b/COPYRIGHT @@ -1,4 +1,4 @@ -Paradyn is Copyright (c) 1996-2021 Barton P. Miller +Paradyn is Copyright (c) 1996-2024 Barton P. Miller Contributions to Paradyn were developed by LLNS and have the following copyright: Copyright (c) 2012-2013, Lawrence Livermore National Security, LLC. Produced at diff --git a/DyninstConfigVersion.cmake b/DyninstConfigVersion.cmake deleted file mode 100644 index 8da8c28f64..0000000000 --- a/DyninstConfigVersion.cmake +++ /dev/null @@ -1,7 +0,0 @@ -set (PACKAGE_VERSION "8.2.0") - -if ("${PACKAGE_VERSION}" VERSION_LESS "${PACKAGE_FIND_VERSION}") - set (PACKAGE_VERSION_COMPATIBLE FALSE) -else() - set (PACKAGE_VERSION_COMPATIBLE TRUE) -endif() diff --git a/README.md b/README.md index e33974941b..d706e74a46 100644 --- a/README.md +++ b/README.md @@ -1,12 +1,5 @@ # Dyninst -## Branch states - -| Branch | Status | Notes | -| --------------------------------------- |:-------------:|:--------------------------------------------------:| -| master | stable | See below | -| aarch32 | experimental | Contact Ray Chen (rchen at cs dot umd dot edu) | - ## Notes * Known issues should have open issues associated with them. @@ -15,6 +8,14 @@ ## Build DyninstAPI and its subcomponents +### Docker Containers + +Containers are provided that can be used for Dyninst development (e.g., make changes to Dyninst and quickly rebuild it) +or for development of your own tools (e.g., have a container ready to go with Dyninst). Links will be added +here when the containers are pushed to the Dyninst associated package registries. Instructions for usage +and building locally are provided in the [docker](docker) directory. + + ### Install with Spack ```spack install dyninst``` @@ -25,9 +26,6 @@ ```cmake /path/to/dyninst/source -DCMAKE_INSTALL_PREFIX=/path/to/installation``` - - **NOTE:** If Dyninst builds TBB from source, see the [wiki](https://github.com/dyninst/dyninst/wiki/third-party-deps#tbb_correct_linking) for instructions on ensuring correct usage. - 2. Build and install Dyninst in parallel ```make install -jN``` diff --git a/cmake/Boost.cmake b/cmake/Boost.cmake deleted file mode 100644 index 231f3313dd..0000000000 --- a/cmake/Boost.cmake +++ /dev/null @@ -1,282 +0,0 @@ -#======================================================================================================== -# Boost.cmake -# -# Configure Boost for Dyninst -# -# ---------------------------------------- -# -# Accepts the following CMake variables -# -# Boost_ROOT_DIR - Hint directory that contains the Boost installation -# PATH_BOOST - Alias for Boost_ROOT_DIR -# Boost_MIN_VERSION - Minimum acceptable version of Boost -# Boost_USE_MULTITHREADED - Use the multithreaded version of Boost -# Boost_USE_STATIC_RUNTIME - Use libraries linked statically to the C++ runtime -# -# Options inherited from Modules/FindBoost.cmake that may be useful -# -# BOOST_INCLUDEDIR - Hint directory that contains the Boost headers files -# BOOST_LIBRARYDIR - Hint directory that contains the Boost library files -# -# Advanced options: -# -# Boost_DEBUG - Enable debug output from FindBoost -# Boost_NO_SYSTEM_PATHS - Disable searching in locations not specified by hint variables -# -# Exports the following CMake cache variables -# -# Boost_ROOT_DIR - Computed base directory the of Boost installation -# Boost_INCLUDE_DIRS - Boost include directories -# Boost_INCLUDE_DIR - Alias for Boost_INCLUDE_DIRS -# Boost_LIBRARY_DIRS - Link directories for Boost libraries -# Boost_DEFINES - Boost compiler definitions -# Boost_LIBRARIES - Boost library files -# Boost__LIBRARY_RELEASE - Release libraries to link for component ( is upper-case) -# Boost__LIBRARY_DEBUG - Debug libraries to link for component -# Boost_THREAD_LIBRARY - The filename of the Boost thread library -# Boost_USE_MULTITHREADED - Use the multithreaded version of Boost -# Boost_USE_STATIC_RUNTIME - Use libraries linked statically to the C++ runtime -# -# NOTE: -# The exported Boost_ROOT_DIR can be different from the value provided by the user in the case that -# it is determined to build Boost from source. In such a case, Boost_ROOT_DIR will contain the -# directory of the from-source installation. -# -# See Modules/FindBoost.cmake for additional input and exported variables -# -#======================================================================================================== - -if(Boost_FOUND) - return() -endif() - -# Need at least Boost-1.67 because of deprecated headers -set(_boost_min_version 1.67.0) - -# Provide a default, if the user didn't specify -set(Boost_MIN_VERSION ${_boost_min_version} CACHE STRING "Minimum Boost version") - -# Enforce minimum version -if(${Boost_MIN_VERSION} VERSION_LESS ${_boost_min_version}) - message(FATAL_ERROR "Requested Boost-${Boost_MIN_VERSION} is less than minimum supported version (${_boost_min_version})") -endif() - -# -------------- RUNTIME CONFIGURATION ---------------------------------------- - -# Use the multithreaded version of Boost -# NB: This _must_ be a cache variable as it -# controls the tagged layout of Boost library names -set(Boost_USE_MULTITHREADED ON CACHE BOOL "Enable multithreaded Boost libraries") - -# Don't use libraries linked statically to the C++ runtime -# NB: This _must_ be a cache variable as it -# controls the tagged layout of Boost library names -set(Boost_USE_STATIC_RUNTIME OFF CACHE BOOL - "Enable usage of libraries statically linked to C++ runtime") - -# If using multithreaded Boost, make sure Threads has been intialized -if(Boost_USE_MULTITHREADED AND NOT DEFINED CMAKE_THREAD_LIBS_INIT) - find_package(Threads) -endif() - -# Enable debug output from FindBoost -set(Boost_DEBUG OFF CACHE BOOL "Enable debug output from FindBoost") - -# -------------- PATHS -------------------------------------------------------- - -# By default, search system paths -set(Boost_NO_SYSTEM_PATHS OFF CACHE BOOL "Disable searching in locations not specified by hint variables") - -# A sanity check -# This must be done _before_ the cache variables are set -if(PATH_BOOST AND Boost_ROOT_DIR) - message(FATAL_ERROR "PATH_BOOST AND Boost_ROOT_DIR both specified. Please provide only one") -endif() - -# Provide a default root directory -if(NOT PATH_BOOST AND NOT Boost_ROOT_DIR) - set(PATH_BOOST "/usr") -endif() - -# Set the default location to look for Boost -set(Boost_ROOT_DIR ${PATH_BOOST} CACHE PATH "Base directory the of Boost installation") - -# In FindBoost, Boost_ROOT_DIR is spelled BOOST_ROOT -set(BOOST_ROOT ${Boost_ROOT_DIR}) - -# -------------- COMPILER DEFINES --------------------------------------------- - -set(_boost_defines) - -# Disable auto-linking -list(APPEND _boost_defines -DBOOST_ALL_NO_LIB=1) - -# Disable generating serialization code in boost::multi_index -list(APPEND _boost_defines -DBOOST_MULTI_INDEX_DISABLE_SERIALIZATION) - -# There are broken versions of MSVC that won't handle variadic templates -# correctly (despite the C++11 test case passing). -if(MSVC) - list(APPEND _boost_defines -DBOOST_NO_CXX11_VARIADIC_TEMPLATES) -endif() - -set(Boost_DEFINES ${_boost_defines} CACHE STRING "Boost compiler defines") -add_definitions(${Boost_DEFINES}) - -# -------------- INTERNALS ---------------------------------------------------- - -# Disable Boost's own CMake as it's known to be buggy -# NB: This should not be a cache variable -set(Boost_NO_BOOST_CMAKE ON) - -# The required Boost library components -# NB: These are just the ones that require compilation/linking -# This should _not_ be a cache variable -set(_boost_components atomic chrono date_time filesystem system thread timer) - -find_package(Boost ${Boost_MIN_VERSION} COMPONENTS ${_boost_components}) - -# -------------- SOURCE BUILD ------------------------------------------------- - -if(Boost_FOUND) - # Force the cache entries to be updated - # Normally, these would not be exported. However, we need them in the Testsuite - set(Boost_INCLUDE_DIRS ${Boost_INCLUDE_DIRS} CACHE PATH "Boost include directory" FORCE) - set(Boost_LIBRARY_DIRS ${Boost_LIBRARY_DIRS} CACHE PATH "Boost library directory" FORCE) - set(Boost_INCLUDE_DIR ${Boost_INCLUDE_DIR} CACHE PATH "Boost include directory" FORCE) - add_library(boost SHARED IMPORTED) -elseif(NOT Boost_FOUND AND STERILE_BUILD) - message(FATAL_ERROR "Boost not found and cannot be downloaded because build is sterile.") -else() - # If we didn't find a suitable version on the system, then download one from the web - set(_boost_download_version "1.69.0") - - # If the user specifies a version other than _boost_download_version, use that version. - # NB: We know Boost_MIN_VERSION is >= _boost_min_version from earlier checks - if(${Boost_MIN_VERSION} VERSION_LESS ${_boost_download_version} OR - ${Boost_MIN_VERSION} VERSION_GREATER ${_boost_download_version}) - set(_boost_download_version ${Boost_MIN_VERSION}) - endif() - message(STATUS "${Boost_ERROR_REASON}") - message(STATUS "Attempting to build ${_boost_download_version} as external project") - - # This is an internal consistency check. Normal users should not trip this since - # they cannot affect _boost_download_version. - if(${_boost_download_version} VERSION_LESS ${Boost_MIN_VERSION}) - message(FATAL_ERROR "Download version of Boost (${_boost_download_version}) " - "is older than minimum allowed version (${Boost_MIN_VERSION})") - endif() - - if(Boost_USE_MULTITHREADED) - set(_boost_threading multi) - else() - set(_boost_threading single) - endif() - - if(Boost_USE_STATIC_RUNTIME) - set(_boost_runtime_link static) - else() - set(_boost_runtime_link shared) - endif() - - # Change the base directory - set(Boost_ROOT_DIR ${CMAKE_INSTALL_PREFIX} CACHE PATH "Base directory the of Boost installation" FORCE) - - # Update the exported variables - set(Boost_INCLUDE_DIRS ${Boost_ROOT_DIR}/include CACHE PATH "Boost include directory" FORCE) - set(Boost_LIBRARY_DIRS ${Boost_ROOT_DIR}/lib CACHE PATH "Boost library directory" FORCE) - set(Boost_INCLUDE_DIR ${Boost_INCLUDE_DIRS} CACHE PATH "Boost include directory" FORCE) - - set(BOOST_ARGS - --ignore-site-config - --link=static - --runtime-link=${_boost_runtime_link} - --threading=${_boost_threading}) - if(WIN32) - # NB: We need to build both debug/release on windows - # as we don't use CMAKE_BUILD_TYPE - set(BOOST_BOOTSTRAP call bootstrap.bat) - set(BOOST_BUILD ".\\b2") - if(CMAKE_SIZEOF_VOID_P STREQUAL "8") - list(APPEND BOOST_ARGS address-model=64) - endif() - else() - set(BOOST_BOOTSTRAP "./bootstrap.sh") - set(BOOST_BUILD "./b2") - if(CMAKE_BUILD_TYPE STREQUAL "Debug") - list(APPEND BOOST_ARGS variant=debug) - else() - list(APPEND BOOST_ARGS variant=release) - endif() - endif() - - # Join the component names together to pass to --with-libraries during bootstrap - set(_boost_lib_names "") - foreach(c ${_boost_components}) - # list(JOIN ...) is in cmake 3.12 - string(CONCAT _boost_lib_names "${_boost_lib_names}${c},") - endforeach() - - include(ExternalProject) - string(REPLACE "." "_" _boost_download_filename ${_boost_download_version}) - ExternalProject_Add( - boost - PREFIX ${CMAKE_BINARY_DIR}/boost - URL http://downloads.sourceforge.net/project/boost/boost/${_boost_download_version}/boost_${_boost_download_filename}.zip - BUILD_IN_SOURCE 1 - CONFIGURE_COMMAND CC=${CMAKE_C_COMPILER} CXX=${CMAKE_CXX_COMPILER} ${BOOST_BOOTSTRAP} --prefix=${Boost_ROOT_DIR} --with-libraries=${_boost_lib_names} - BUILD_COMMAND ${BOOST_BUILD} ${BOOST_ARGS} install - INSTALL_COMMAND "" - ) - - if(WIN32) - # We need to specify different library names for debug vs release - set(Boost_LIBRARIES "") - foreach(c ${_boost_components}) - list(APPEND Boost_LIBRARIES "optimized libboost_${c} debug libboost_${c}-gd ") - - # Also export cache variables for the file location of each library - string(TOUPPER ${c} _basename) - set(Boost_${_basename}_LIBRARY_RELEASE "${Boost_LIBRARY_DIRS}/libboost_${c}.dll" CACHE FILEPATH "" FORCE) - set(Boost_${_basename}_LIBRARY_DEBUG "${Boost_LIBRARY_DIRS}/libboost_${c}-gd.dll" CACHE FILEPATH "" FORCE) - endforeach() - else() - # Transform the component names into the library filenames - # e.g., system -> boost_system - set(Boost_LIBRARIES "") - foreach(c ${_boost_components}) - list(APPEND Boost_LIBRARIES "${Boost_LIBRARY_DIRS}/libboost_${c}.so") - - # Also export cache variables for the file location of each library - string(TOUPPER ${c} _basename) - set(Boost_${_basename}_LIBRARY_RELEASE "${Boost_LIBRARY_DIRS}/libboost_${c}.so" CACHE FILEPATH "" FORCE) - set(Boost_${_basename}_LIBRARY_DEBUG "${Boost_LIBRARY_DIRS}/libboost_${c}.so" CACHE FILEPATH "" FORCE) - endforeach() - endif() -endif() - -# -------------- EXPORT VARIABLES --------------------------------------------- - -# Export Boost_THREAD_LIBRARY -list(FIND _boost_components "thread" _building_threads) -if(Boost_USE_MULTITHREADED AND ${_building_threads}) - # On Windows, always use the debug version - # On Linux, we don't use tagged builds, so the debug/release filenames are the same - set(Boost_THREAD_LIBRARY ${Boost_THREAD_LIBRARY_DEBUG} CACHE FILEPATH "Boost thread library") -endif() - -# Add the system thread library -if(Boost_USE_MULTITHREADED) - list(APPEND Boost_LIBRARIES ${CMAKE_THREAD_LIBS_INIT}) -endif() - -# Export the complete set of libraries -set(Boost_LIBRARIES ${Boost_LIBRARIES} CACHE FILEPATH "Boost library files" FORCE) - -link_directories(${Boost_LIBRARY_DIRS}) -include_directories(SYSTEM ${Boost_INCLUDE_DIRS}) - -message(STATUS "Boost includes: ${Boost_INCLUDE_DIRS}") -message(STATUS "Boost library dirs: ${Boost_LIBRARY_DIRS}") -message(STATUS "Boost thread library: ${Boost_THREAD_LIBRARY}") -message(STATUS "Boost libraries: ${Boost_LIBRARIES}") diff --git a/cmake/DyninstCapArchDef.cmake b/cmake/DyninstCapArchDef.cmake new file mode 100644 index 0000000000..a341bfb140 --- /dev/null +++ b/cmake/DyninstCapArchDef.cmake @@ -0,0 +1,80 @@ +# +# -- Define the capabilities for each supported architecture/platform +# +# cap_32_64 - This host 64-bit platform supports modifying 32-bit binaries +# + +include_guard(GLOBAL) + +set(CAP_DEFINES -Dcap_dynamic_heap -Dcap_liveness -Dcap_threads) + +if(DYNINST_ARCH_i386) + set(ARCH_DEFINES -Darch_x86) + set(CAP_DEFINES + ${CAP_DEFINES} + -Dcap_fixpoint_gen + -Dcap_noaddr_gen + -Dcap_stripped_binaries + -Dcap_tramp_liveness + -Dcap_virtual_registers + -Dcap_stack_mods) + +elseif(DYNINST_ARCH_x86_64) + set(ARCH_DEFINES -Darch_x86_64 -Darch_64bit) + set(CAP_DEFINES + ${CAP_DEFINES} + -Dcap_32_64 + -Dcap_fixpoint_gen + -Dcap_noaddr_gen + -Dcap_registers + -Dcap_stripped_binaries + -Dcap_tramp_liveness + -Dcap_stack_mods) + +elseif(DYNINST_ARCH_ppc64le) + set(ARCH_DEFINES -Darch_power -Darch_64bit) + set(CAP_DEFINES ${CAP_DEFINES} -Dcap_32_64 -Dcap_registers -Dcap_toc_64) + +elseif(DYNINST_ARCH_aarch64) + set(ARCH_DEFINES -Darch_aarch64 -Darch_64bit) + set(CAP_DEFINES ${CAP_DEFINES} -Dcap_registers) +endif() + +if(DYNINST_OS_Linux) + set(OS_DEFINES -Dos_linux) + set(CAP_DEFINES ${CAP_DEFINES} -Dcap_async_events -Dcap_binary_rewriter -Dcap_dwarf + -Dcap_mutatee_traps -Dcap_ptrace) + set(BUG_DEFINES -Dbug_syscall_changepc_rewind -Dbug_force_terminate_failure) + + if(DYNINST_ARCH_i386) + set(OLD_DEFINES -Di386_unknown_linux2_0) + elseif(DYNINST_ARCH_x86_64) + set(OLD_DEFINES -Dx86_64_unknown_linux2_4) + elseif(DYNINST_ARCH_ppc64le) + set(OLD_DEFINES -Dppc64_linux) + set(BUG_DEFINES ${BUG_DEFINES} -Dbug_registers_after_exit) + elseif(DYNINST_ARCH_aarch64) + set(OLD_DEFINES -Daarch64_unknown_linux) + endif() + +elseif(DYNINST_OS_FreeBSD) + set(OS_DEFINES -Dos_freebsd) + set(CAP_DEFINES ${CAP_DEFINES} -Dcap_binary_rewriter -Dcap_dwarf -Dcap_mutatee_traps) + set(BUG_DEFINES + -Dbug_freebsd_missing_sigstop -Dbug_freebsd_mt_suspend -Dbug_freebsd_change_pc + -Dbug_phdrs_first_page -Dbug_syscall_changepc_rewind) + + if(DYNINST_ARCH_i386) + set(OLD_DEFINES -Di386_unknown_freebsd7_0) + elseif(DYNINST_ARCH_x86_64) + set(OLD_DEFINES -Damd64_unknown_freebsd7_0) + endif() + +elseif(DYNINST_OS_Windows) + set(OS_DEFINES -Dos_windows) + set(CAP_DEFINES ${CAP_DEFINES} -Dcap_mutatee_traps) + set(OLD_DEFINES -Di386_unknown_nt4_0) +endif() + +set(DYNINST_PLATFORM_CAPABILITIES ${CAP_DEFINES} ${BUG_DEFINES} ${ARCH_DEFINES} + ${OS_DEFINES} ${OLD_DEFINES}) diff --git a/cmake/DyninstConfig.cmake.in b/cmake/DyninstConfig.cmake.in index 7578e4687c..9939e42755 100644 --- a/cmake/DyninstConfig.cmake.in +++ b/cmake/DyninstConfig.cmake.in @@ -1,44 +1,32 @@ -# - Config file for Dyninst and its component libraries -# It defines the following variables: -# -# DYNINST_INCLUDE_DIRS -# DYNINST_LIBRARIES -# DYNINST_INTERNAL_DEFINES - used by the test suite - -# compute paths - -get_filename_component(DYNINST_CMAKE_DIR "${CMAKE_CURRENT_LIST_FILE}" PATH) -set (DYNINST_INCLUDE_DIR @CONF_INCLUDE_DIRS@) - -# Library dependencies -#include ("${DYNINST_CMAKE_DIR}/DyninstTargets.cmake") -foreach(TARG @ALL_DYNINST_TARGETS@) - include ("${DYNINST_CMAKE_DIR}/${TARG}Targets.cmake" OPTIONAL) -endforeach() +# Find Dyninst-provided third-party library modules without tainting the user's paths +set(_DYNINST_module_path_save "${CMAKE_MODULE_PATH}") +list(INSERT CMAKE_MODULE_PATH 0 "${CMAKE_CURRENT_LIST_DIR}/Modules" + "${CMAKE_CURRENT_LIST_DIR}/tpls") + +include(DyninstElfUtils) +include(DyninstTBB) + +set(CMAKE_MODULE_PATH ${_DYNINST_module_path_save}) +unset(_DYNINST_module_path_save) -set (DYNINST_LIBRARIES "dyninstAPI") +@PACKAGE_INIT@ + +include("${CMAKE_CURRENT_LIST_DIR}/DyninstTargets.cmake") # Other variables Dyninst mutators may depend on -set (DYNINST_PLATFORM "@PLATFORM@") -set (DYNINST_INTERNAL_DEFINES @UNIFIED_DEFINES@) - -if(DYNINST_FIND_COMPONENTS) - foreach(COMP DYNINST_FIND_COMPONENTS) - if(NOT TARGET ${COMP}) - set(DYNINST_${COMP}_FOUND 0) - if(DYNINST_FIND_REQUIRED_${COMP}) - MESSAGE(ERROR "${COMP} was not part of the Dyninst build") - endif() - else() - set(DYNINST_${COMP}_FOUND 1) - MESSAGE(STATUS "Found ${COMP}") - endif() - endforeach() -endif() - -if(TARGET dyninstAPI) - set(Dyninst_FOUND 1) -else() - set(Dyninst_FOUND 0) -endif() +set(DYNINST_PLATFORM "@DYNINST_PLATFORM@") +set(DYNINST_INTERNAL_DEFINES @DYNINST_PLATFORM_CAPABILITIES@) + +foreach(COMP ${Dyninst_FIND_COMPONENTS}) + if(TARGET Dyninst::${COMP}) + set(Dyninst_${COMP}_FOUND TRUE) + else() + message(FATAL_ERROR "Unknown Dyninst component '${COMP}'") + endif() +endforeach() + +check_required_components(Dyninst) +# -- DO NOT USE -- This is for legacy purposes only +set_and_check(DYNINST_INCLUDE_DIR + "${CMAKE_CURRENT_LIST_DIR}/../../../@DYNINST_INSTALL_INCLUDEDIR@") diff --git a/cmake/DyninstConfigVersion.cmake.in b/cmake/DyninstConfigVersion.cmake.in deleted file mode 100644 index 8090b4e768..0000000000 --- a/cmake/DyninstConfigVersion.cmake.in +++ /dev/null @@ -1,7 +0,0 @@ -set (PACKAGE_VERSION "@DYNINST_VERSION@") - -if ("${PACKAGE_VERSION}" VERSION_LESS "${PACKAGE_FIND_VERSION}") - set (PACKAGE_VERSION_COMPATIBLE FALSE) -else() - set (PACKAGE_VERSION_COMPATIBLE TRUE) -endif() diff --git a/cmake/DyninstInstall.cmake b/cmake/DyninstInstall.cmake new file mode 100644 index 0000000000..f79bb0c4c9 --- /dev/null +++ b/cmake/DyninstInstall.cmake @@ -0,0 +1,30 @@ +include(CMakePackageConfigHelpers) + +# Export the Find modules for thirdy-party libraries provided by us +install(DIRECTORY ${PROJECT_SOURCE_DIR}/cmake/Modules + DESTINATION ${DYNINST_INSTALL_CMAKEDIR}) +install(DIRECTORY ${PROJECT_SOURCE_DIR}/cmake/tpls + DESTINATION ${DYNINST_INSTALL_CMAKEDIR}) + +configure_package_config_file( + ${PROJECT_SOURCE_DIR}/cmake/${PROJECT_NAME}Config.cmake.in + ${PROJECT_BINARY_DIR}/${PROJECT_NAME}Config.cmake + INSTALL_DESTINATION ${DYNINST_INSTALL_CMAKEDIR} + INSTALL_PREFIX ${CMAKE_INSTALL_PREFIX} + PATH_VARS DYNINST_INSTALL_LIBDIR DYNINST_INSTALL_INCLUDEDIR) + +write_basic_package_version_file( + ${PROJECT_BINARY_DIR}/DyninstConfigVersion.cmake + VERSION ${PROJECT_VERSION} + COMPATIBILITY SameMajorVersion) + +install(FILES ${PROJECT_BINARY_DIR}/${PROJECT_NAME}Config.cmake + ${PROJECT_BINARY_DIR}/${PROJECT_NAME}ConfigVersion.cmake + DESTINATION ${DYNINST_INSTALL_CMAKEDIR}) + +# Export all of the Dyninst libraries created by `dyninst_library` +install( + EXPORT dyninst-targets + NAMESPACE Dyninst:: + FILE DyninstTargets.cmake + DESTINATION ${DYNINST_INSTALL_CMAKEDIR}) diff --git a/cmake/LanguageStandards.cmake b/cmake/DyninstLanguageStandards.cmake similarity index 50% rename from cmake/LanguageStandards.cmake rename to cmake/DyninstLanguageStandards.cmake index d538c2b036..190a996ad9 100644 --- a/cmake/LanguageStandards.cmake +++ b/cmake/DyninstLanguageStandards.cmake @@ -5,25 +5,36 @@ # #========================================================================= +# +# C/C++ language standard cmake options. +# + +set(DYNINST_CXX_LANGUAGE_STANDARD + "17" + CACHE STRING "C++ language standard version.") +set(DYNINST_C_LANGUAGE_STANDARD + "17" + CACHE STRING "C language standard version.") + # # -------- C++ language features ---------------- # -# Disable compiler-specific C++ language extensions (e.g., gnu++11) +# Disable compiler-specific C++ language extensions (e.g., gnu++17) set(CMAKE_CXX_EXTENSIONS OFF) -# Require C++11 support -set(CMAKE_CXX_STANDARD 11) +# Require C++17 support +set(CMAKE_CXX_STANDARD ${DYNINST_CXX_LANGUAGE_STANDARD}) +message(STATUS "C++ language standard: ${DYNINST_CXX_LANGUAGE_STANDARD}") set(CMAKE_CXX_STANDARD_REQUIRED ON) -# Require the standards-compliant C++11 ABI for gcc +# Require the a compiler with usable C++17 support. for gcc if(CMAKE_CXX_COMPILER_ID STREQUAL "GNU") - if(CMAKE_CXX_COMPILER_VERSION VERSION_LESS "6.0") - message(FATAL_ERROR "Dyninst requires gcc >= 6.0") + if(CMAKE_CXX_COMPILER_VERSION VERSION_LESS "10.0") + message(FATAL_ERROR "Dyninst requires gcc >= 10.0") endif() endif() - # # -------- C language features ---------------- # @@ -32,5 +43,6 @@ endif() set(CMAKE_C_EXTENSIONS OFF) # Require C11 support -set(CMAKE_C_STANDARD 11) +set(CMAKE_C_STANDARD ${DYNINST_C_LANGUAGE_STANDARD}) +message(STATUS "C language standard: ${DYNINST_C_LANGUAGE_STANDARD}") set(CMAKE_C_STANDARD_REQUIRED ON) diff --git a/cmake/DyninstLibrary.cmake b/cmake/DyninstLibrary.cmake new file mode 100644 index 0000000000..6f6bb04a86 --- /dev/null +++ b/cmake/DyninstLibrary.cmake @@ -0,0 +1,200 @@ +#[=======================================================================[ +DyninstLibrary +-------------- + +This module provides a uniform interface for creating a Dyninst +toolkit target. + + dyninst_library + + This command is a wrapper around `add_library` that creates a + SHARED and, optionally, STATIC library for a Dyninst toolkit. + + dyninst_library( + [PRIVATE_HEADER_FILES ...] + [PUBLIC_HEADER_FILES ...] + [SOURCE_FILES ...] + [DEFINES ...] + [DYNINST_DEPS ...] + [PUBLIC_DEPS ...] + [PRIVATE_DEPS ...] + ) + + The _TARGETS variable will contain the names of the + created targets for this toolkit. + + The options are: + + PRIVATE_HEADER_FILES + A list of header files that are needed to build , but + are not part of the public interface. These files are not copied + into the install tree. + + PUBLIC_HEADER_FILES + A list of header files that are part of the toolkit's public API. + These files are copied into the install tree. + + SOURCE_FILES + A list of source files for building the library. They are always + considered PRIVATE attributes of the target as in `target_sources`. + + DEFINES + A list of compiler definitions to attach to the target. These are + always PRIVATE attributes of the target. + + DYNINST_DEPS + A list of dependent Dyninst targets. If a target for a static library + is created, it will link against the corresponding static target for + each library container here. + + PUBLIC_DEPS + A list of targets that are PUBLIC dependencies of . + + PRIVATE_DEPS + A list of targets that are PRIVATE dependencies of . + +#]=======================================================================] + +include_guard(DIRECTORY) + +if(LIGHTWEIGHT_SYMTAB) + set(SYMREADER symLite) +else() + set(SYMREADER symtabAPI) +endif() + +set(_dyninst_global_defs) +if(DYNINST_OS_Windows) + list(APPEND _dyninst_global_defs WIN32_LEAN_AND_MEAN) + if(CMAKE_C_COMPILER_VERSION VERSION_GREATER 19) + list(APPEND _dyninst_global_defs _SILENCE_STDEXT_HASH_DEPRECATION_WARNINGS=1) + else() + list(APPEND _dyninst_global_defs snprintf=_snprintf) + endif() +endif() + +if(LIGHTWEIGHT_SYMTAB) + list(APPEND _dyninst_global_defs WITH_SYMLITE) +else() + list(APPEND _dyninst_global_defs WITH_SYMTAB_API) +endif() + +if(DYNINST_DISABLE_DIAGNOSTIC_SUPPRESSIONS) + list(APPEND _dyninst_global_defs DYNINST_DIAGNOSTIC_NO_SUPPRESSIONS) +endif() + +list(APPEND _dyninst_global_defs ${DYNINST_PLATFORM_CAPABILITIES}) + +function(dyninst_library _target) + # cmake-format: off + set(_keywords + PRIVATE_HEADER_FILES + PUBLIC_HEADER_FILES + SOURCE_FILES # Both public and private + DEFINES + DYNINST_DEPS + PUBLIC_DEPS + PRIVATE_DEPS) + # cmake-format: on + cmake_parse_arguments(PARSE_ARGV 0 _target "FORCE_STATIC" "" "${_keywords}") + + add_library(${_target} SHARED ${_target_PUBLIC_HEADER_FILES} + ${_target_PRIVATE_HEADER_FILES} ${_target_SOURCE_FILES}) + + # Depending on another Dyninst library is always public + target_link_libraries(${_target} PUBLIC ${_target_DYNINST_DEPS}) + + set(_all_targets ${_target}) + + if(_target_FORCE_STATIC OR ENABLE_STATIC_LIBS) + list(APPEND _all_targets ${_target}_static) + add_library( + ${_target}_static STATIC ${_target_PUBLIC_HEADER_FILES} + ${_target_PRIVATE_HEADER_FILES} ${_target_SOURCE_FILES}) + + # When building all libraries as static, they have a '_static' suffix + # but not when FORCE_STATIC is active + if(NOT _target_FORCE_STATIC) + set(_suffix "_static") + endif() + + # Link against the corresponding static Dyninst target + foreach(d ${_target_DYNINST_DEPS}) + # Depending on another Dyninst library is always public + target_link_libraries(${_target}_static PUBLIC "${d}${_suffix}") + endforeach() + unset(_suffix) + endif() + + foreach(t ${_all_targets}) + message(STATUS "Adding library '${t}'") + + target_link_options(${t} PRIVATE $<$:${DYNINST_LINK_FLAGS}> + $<$:${DYNINST_CXX_LINK_FLAGS}>) + + target_compile_options( + ${t} PRIVATE $<$:${SUPPORTED_C_WARNING_FLAGS}> + $<$:${SUPPORTED_CXX_WARNING_FLAGS}>) + + target_compile_options( + ${t} + PRIVATE $<$: + $<$:${DYNINST_C_FLAGS_DEBUG}> + $<$:${DYNINST_C_FLAGS_RELWITHDEBINFO}> + $<$:${DYNINST_C_FLAGS_RELEASE}> + $<$:${DYNINST_C_FLAGS_MINSIZEREL}> + > + $<$: + $<$:${DYNINST_CXX_FLAGS_DEBUG}> + $<$:${DYNINST_CXX_FLAGS_RELWITHDEBINFO}> + $<$:${DYNINST_CXX_FLAGS_RELEASE}> + $<$:${DYNINST_CXX_FLAGS_MINSIZEREL}> + >) + + foreach(_v "PUBLIC" "PRIVATE") + set(_d ${_target_${_v}_DEPS}) + if(${t} MATCHES "static") + # OpenMP doesn't work with static libraries, so explicitly + # remove it from link dependencies + list(FILTER _d EXCLUDE REGEX "OpenMP") + endif() + target_link_libraries(${t} ${_v} ${_d}) + unset(_d) + endforeach() + + target_include_directories( + ${t} + PUBLIC + "$" + "$") + + set_target_properties( + ${t} + PROPERTIES INSTALL_RPATH "${DYNINST_RPATH_DIRECTORIES}" + SOVERSION ${DYNINST_SOVERSION} + VERSION ${DYNINST_VERSION}) + + target_compile_definitions(${t} PRIVATE ${_dyninst_global_defs} ${_target_DEFINES}) + endforeach() + + install( + TARGETS ${_all_targets} + EXPORT dyninst-targets + RUNTIME DESTINATION ${DYNINST_INSTALL_BINDIR} + LIBRARY DESTINATION ${DYNINST_INSTALL_LIBDIR} + ARCHIVE DESTINATION ${DYNINST_INSTALL_LIBDIR} + INCLUDES + DESTINATION ${DYNINST_INSTALL_INCLUDEDIR}) + + # Install headers, preserving the directory structure under h/. + # Note: By convention, headers are stored in "h/" + foreach(h ${_target_PUBLIC_HEADER_FILES}) + string(REGEX MATCH "^h/(.*)" _file ${h}) + get_filename_component(_dir ${CMAKE_MATCH_1} DIRECTORY) + install(FILES ${h} DESTINATION "${DYNINST_INSTALL_INCLUDEDIR}/${_dir}") + endforeach() + + set(${_target}_TARGETS + ${_all_targets} + PARENT_SCOPE) +endfunction() diff --git a/cmake/DyninstLibrarySettings.cmake b/cmake/DyninstLibrarySettings.cmake new file mode 100644 index 0000000000..d3627f8789 --- /dev/null +++ b/cmake/DyninstLibrarySettings.cmake @@ -0,0 +1,56 @@ +# ------------------------------------------------------------------- +# +# Various build features of the Dyninst libraries +# +# The values here have a wide range of effects, so this file should +# be included before any other configurations are done. +# +# ------------------------------------------------------------------- + +include_guard(GLOBAL) + +if(NOT CMAKE_BUILD_TYPE) + set(CMAKE_BUILD_TYPE RelWithDebInfo) +endif() + +set(BUILD_SHARED_LIBS ON) + +if(DYNINST_EXPORT_ALL) + set(CMAKE_C_VISIBILITY_PRESET default) + set(CMAKE_CXX_VISIBILITY_PRESET default) + set(CMAKE_VISIBILITY_INLINES_HIDDEN OFF) +else() + set(CMAKE_C_VISIBILITY_PRESET hidden) + set(CMAKE_CXX_VISIBILITY_PRESET hidden) + set(CMAKE_VISIBILITY_INLINES_HIDDEN ON) +endif() + +set(DYNINST_INSTALL_BINDIR "bin") +set(DYNINST_INSTALL_LIBDIR "lib") +set(DYNINST_INSTALL_INCLUDEDIR "include") +set(DYNINST_INSTALL_CMAKEDIR "${DYNINST_INSTALL_LIBDIR}/cmake/Dyninst") + +# -- Set up the RPATH --- +# +# General guidelines: +# https://gitlab.kitware.com/cmake/community/-/wikis/doc/cmake/RPATH-handling +# +# '$ORIGIN' is a special CMake variable that looks up the location of a package's +# private libraries via a relative expression so as to not lose the capability of +# providing a fully relocatable package +# +# CMP0060 is active and so libraries are linked by their full paths even in +# implicit directories (e.g., /usr/lib/foo.so instead of -lfoo) + +# Populate RPATHs for binaries in the build tree +set(CMAKE_SKIP_BUILD_RPATH FALSE) + +# Do not use the install path as the RPATH (this is what $ORIGIN is for) +set(CMAKE_BUILD_WITH_INSTALL_RPATH FALSE) + +# Add paths to any directories outside the project that are in the linker +# search path or contain linked library files +set(CMAKE_INSTALL_RPATH_USE_LINK_PATH TRUE) + +# Always include $ORIGIN +set(DYNINST_RPATH_DIRECTORIES "\$ORIGIN") diff --git a/cmake/DyninstOptimization.cmake b/cmake/DyninstOptimization.cmake new file mode 100644 index 0000000000..eabde1cf08 --- /dev/null +++ b/cmake/DyninstOptimization.cmake @@ -0,0 +1,108 @@ +#[=======================================================================[ +DyninstOptimization +------------------- + +This module provides the global compiler and linker flags. + + Created variables: + + DYNINST_LINK_FLAGS + Generic linker flags that apply to all languages + + DYNINST_CXX_LINK_FLAGS + Linker flags that are specific to the C++ compiler + + DYNINST_FORCE_FRAME_POINTER + Contains the compiler-specific flags needed to force the generation + of a frame pointer in code compiled into a Dyninst library. Currently, + this is only used in some portions of stackwalk. + + --- + + The global CMAKE__FLAGS_ variables are also + populated. Values specified by the user in CMAKE__FLAGS + are forcibly passed to the compiler after CMAKE__FLAGS_ + so that values computed here can be overridden. By default, CMake does + the opposite. + +#]=======================================================================] +include_guard(GLOBAL) + +if(DYNINST_ENABLE_LTO) + include(CheckIPOSupported) + check_ipo_supported(LANGUAGES "C" "CXX") + set(CMAKE_INTERPROCEDURAL_OPTIMIZATION ON) +endif() + +# Make sure we don't get something like CC=gcc CXX=clang++ +if(NOT ${CMAKE_C_COMPILER_ID} STREQUAL ${CMAKE_CXX_COMPILER_ID}) + message(FATAL_ERROR "C and C++ compilers are not the same vendor") +endif() + +set(_linux_compilers "GNU" "Clang" "Intel" "IntelLLVM") + +if(${CMAKE_CXX_COMPILER_ID} IN_LIST _linux_compilers) + if(DYNINST_LINKER) + list(APPEND DYNINST_LINK_FLAGS -fuse-ld=${DYNINST_LINKER}) + endif() + + if(DYNINST_ENABLE_LTO) + if(${DYNINST_LINKER} MATCHES "gold") + message(FATAL_ERROR "Cannot use the gold linker for LTO") + endif() + endif() + + # Used in stackwalk + set(DYNINST_FORCE_FRAME_POINTER -fno-omit-frame-pointer) + + # Dyninst relies on `assert` for correctness. Never let CMake disable it + set(_DEBUG -Og -g3 ${DYNINST_FORCE_FRAME_POINTER} -UNDEBUG) + set(_RELEASE -O3 -UNDEBUG) + set(_RELWITHDEBINFO ${_RELEASE} -g3) + set(_MINSIZEREL -Os -UNDEBUG) + + # Ensure each library is fully linked + list(APPEND DYNINST_LINK_FLAGS -Wl,--no-undefined) + + if(${CMAKE_CXX_COMPILER_ID} STREQUAL "Clang") + if(DYNINST_CXXSTDLIB) + list(APPEND DYNINST_CXX_FLAGS -stdlib=${DYNINST_CXXSTDLIB}) + list(APPEND DYNINST_CXX_LINK_FLAGS -stdlib=${DYNINST_CXXSTDLIB}) + endif() + endif() + + if(DYNINST_FORCE_RUNPATH) + list(APPEND DYNINST_LINK_FLAGS "-Wl,--enable-new-dtags") + endif() +elseif(MSVC) + set(DYNINST_FORCE_FRAME_POINTER /Oy-) + + set(_DEBUG /MP /Od /Zi /MDd /D_DEBUG ${DYNINST_FORCE_FRAME_POINTER}) + set(_RELEASE /MP /O3 /MD /D_DEBUG) + set(_RELWITHDEBINFO ${_RELEASE} /Zi) + set(_MINSIZEREL /MP /O1 /MD /D_DEBUG) +else() + message(FATAL_ERROR "Unknown compiler '${CMAKE_CXX_COMPILER_ID}'") +endif() + +# By default, CMake effectively passes compiler flags in the order +# +# ${CMAKE__FLAGS} ${CMAKE__FLAGS_} +# +# where `` are the values passed to `target_compile_options`. +# This prevents users from overriding values manually computed by us. To +# work around this, we rearrange the values such that CMake now +# effectively (redundantly) does +# +# ${CMAKE__FLAGS} ${CMAKE__FLAGS_} ${CMAKE__FLAGS} +# +string(TOUPPER ${CMAKE_BUILD_TYPE} _build_type) +separate_arguments(_dyninst_c_flags UNIX_COMMAND "${CMAKE_C_FLAGS}") +separate_arguments(_dyninst_cxx_flags UNIX_COMMAND "${CMAKE_CXX_FLAGS}") +set(DYNINST_C_FLAGS_${_build_type} ${_${_build_type}} ${_dyninst_c_flags}) +set(DYNINST_CXX_FLAGS_${_build_type} ${_${_build_type}} ${DYNINST_CXX_FLAGS} + ${_dyninst_cxx_flags}) +unset(_build_type) + +# Merge the link flags for C++ +list(APPEND DYNINST_CXX_LINK_FLAGS ${DYNINST_LINK_FLAGS}) diff --git a/cmake/DyninstOptions.cmake b/cmake/DyninstOptions.cmake new file mode 100644 index 0000000000..641584aa10 --- /dev/null +++ b/cmake/DyninstOptions.cmake @@ -0,0 +1,54 @@ +option(USE_OpenMP "Use OpenMP for parallel parsing" ON) + +option( + LIGHTWEIGHT_SYMTAB + "Use lightweight symtab interface for ParseAPI, ProcControl, and Stackwalker; disables DyninstAPI build" + OFF) + +option(SW_ANALYSIS_STEPPER "Use ParseAPI-based analysis stepper in Stackwalker" ON) + +option(BUILD_RTLIB_32 "Build 32-bit runtime library on mixed 32/64 systems" OFF) + +option(DYNINST_ENABLE_LTO "Enable Link-Time Optimization" OFF) + +option(ENABLE_DEBUGINFOD "Enable debuginfod support" OFF) + +option(STERILE_BUILD "DEPRECATED -- Do not use" OFF) +mark_as_advanced(STERILE_BUILD) + +option(ADD_VALGRIND_ANNOTATIONS "Enable annotations for Valgrind analysis" OFF) + +option(ENABLE_STATIC_LIBS "Build static libraries as well?" OFF) + +option(DYNINST_DISABLE_DIAGNOSTIC_SUPPRESSIONS + "Disable all warning suppressions and frame size overrides." OFF) + +set(DYNINST_EXTRA_WARNINGS + "" + CACHE + STRING + "Additional warning options to enable if available. ;-separated without leading '-' (Wopt1[;Wopt2]...)." + ) + +option(DYNINST_WARNINGS_AS_ERRORS "Treat compilation warnings as errors" OFF) + +option(ENABLE_PARSE_API_GRAPHS "Enable Boost Graph wrappers for parseAPI Functions" OFF) + +set(DYNINST_LINKER + "" + CACHE STRING "The linker to use") +mark_as_advanced(DYNINST_LINKER) + +set(DYNINST_CXXSTDLIB + "libstdc++" + CACHE STRING "The C++ standard library to use; only affects LLVM-based compilers") +mark_as_advanced(DYNINST_CXXSTDLIB) + +option(DYNINST_FORCE_RUNPATH "Require the use of RUNPATH instead of compiler's default" + OFF) + +# This is intended for use by developers to facilitate +# unit testing of internal libraries that don't export +# all of their interfaces. +option(DYNINST_EXPORT_ALL "Export all symbols" OFF) +mark_as_advanced(DYNINST_EXPORT_ALL) diff --git a/cmake/DyninstPlatform.cmake b/cmake/DyninstPlatform.cmake new file mode 100644 index 0000000000..8f673a7920 --- /dev/null +++ b/cmake/DyninstPlatform.cmake @@ -0,0 +1,74 @@ +include_guard(GLOBAL) + +# Equivalent to CMAKE_HOST_SYSTEM_NAME and `uname -s` on Unixes +cmake_host_system_information(RESULT _host_os QUERY OS_NAME) + +set(_known_oses "Linux" "FreeBSD" "Windows") +if(NOT ${_host_os} IN_LIST _known_oses) + message(FATAL_ERROR "Unsupported OS: '${_host_os}'") +endif() + +# Equivalent to CMAKE_HOST_SYSTEM_PROCESSOR and `uname -m` on Unixes +cmake_host_system_information(RESULT _host_arch QUERY OS_PLATFORM) + +set(_known_arches "x86_64" "ppc64le" "aarch64" "i386" "amd64") +if(NOT ${_host_arch} IN_LIST _known_arches) + message(FATAL_ERROR "Unsupported architecture: '${_host_arch}'") +endif() + +# Equivalent to checking CMAKE_SIZEOF_VOID_P +cmake_host_system_information(RESULT _is64bit QUERY IS_64BIT) + +# 32-bit is only supported on i386 +if(NOT _is64bit AND NOT ${_host_arch} STREQUAL "i386") + message(FATAL_ERROR "32-bit programming is only supported on i386") +endif() + +# These checks are redundant, but protect against string name changes +if(${_host_os} STREQUAL "Linux") + set(DYNINST_OS_Linux TRUE) +elseif(${_host_os} STREQUAL "FreeBSD") + set(DYNINST_OS_FreeBSD TRUE) +elseif(${_host_os} STREQUAL "Windows") + set(DYNINST_OS_Windows TRUE) +endif() + +# The CMake `UNIX` covers more than just Linux and FreeBSD, so make +# a more limited version. +if(DYNINST_OS_Linux OR DYNINST_OS_FreeBSD) + set(DYNINST_OS_UNIX TRUE) +endif() + +if(${_host_arch} STREQUAL "x86_64" OR ${_host_arch} STREQUAL "amd64") + set(DYNINST_ARCH_x86_64 TRUE) +elseif(${_host_arch} STREQUAL "aarch64") + set(DYNINST_ARCH_aarch64 TRUE) +elseif(${_host_arch} STREQUAL "ppc64le") + set(DYNINST_ARCH_ppc64le TRUE) +elseif(${_host_arch} STREQUAL "i386") + set(DYNINST_ARCH_i386 TRUE) +endif() + +# --- DEPRECATED --- +# For legacy support in the testsuite ONLY +if(${_host_os} STREQUAL "Linux") + if(NOT _is64bit) + set(DYNINST_PLATFORM i386-unknown-linux2.4) + else() + if(${_host_arch} STREQUAL "x86_64") + set(DYNINST_PLATFORM x86_64-unknown-linux2.4) + elseif(${_host_arch} STREQUAL "aarch64") + set(DYNINST_PLATFORM aarch64-unknown-linux) + else() + set(DYNINST_PLATFORM ppc64_linux) + endif() + endif() +elseif(${_host_os} STREQUAL "FreeBSD") + if(_is64bit) + set(DYNINST_PLATFORM amd64-unknown-freebsd7.2) + else() + set(DYNINST_PLATFORM i386-unknown-freebsd7.2) + endif() +elseif(${_host_os} STREQUAL "Windows") + set(DYNINST_PLATFORM i386-unknown-nt4.0) +endif() diff --git a/cmake/DyninstWarnings.cmake b/cmake/DyninstWarnings.cmake new file mode 100644 index 0000000000..6e450f642f --- /dev/null +++ b/cmake/DyninstWarnings.cmake @@ -0,0 +1,186 @@ +# +# cmake warning options +# + +if(DYNINST_DISABLE_DIAGNOSTIC_SUPPRESSIONS) + message( + STATUS + "DYNINST_DISABLE_DIAGNOSTIC_SUPPRESSIONS set: disabling all dyninst warning suppressions and frame size overrides" + ) +endif() + +# Frame sizes are larger for debug build, so adjust based on build type files with +# functions containing large frames are adjust below (the value could be made +# significantly maller if more files are adjusted). +# +set(defaultDebugMaxFrameSize 24576) +set(defaultNonDebugMaxFrameSize 20480) + +# REQUESTED_WARNING_FLAGS is a list of warning flags for C and C++ programs to enable if +# supported by the compiler. The values do not include the the initial '-' + +list( + APPEND + REQUESTED_WARNING_FLAGS + Wall + Wextra + Wpedantic + Walloca + Wcast-align + Wcast-qual + Wcomma-subscript + Wctor-dtor-privacy + Wdeprecated-copy-dtor + Wdouble-promotion + Wduplicated-branches + Wduplicated-cond + Wenum-conversion + Wextra-semi + Wfloat-equal + Wformat-overflow=2 + Wformat-signedness + Wformat=2 + Wframe-larger-than=${defaultNonDebugMaxFrameSize} + Wjump-misses-init + Wlogical-op + Wmismatched-tags + Wmissing-braces + Wmultichar + Wnoexcept + Wnon-virtual-dtor + Woverloaded-virtual + Wpointer-arith + Wrange-loop-construct + Wrestrict + Wshadow + Wstrict-null-sentinel + Wsuggest-attribute=format + Wsuggest-attribute=malloc + Wuninitialized + Wvla + Wvolatile + Wwrite-strings) + +# cmake-format: off +#list(APPEND REQUESTED_WARNING_FLAGS Werror) +#list(APPEND REQUESTED_WARNING_FLAGS Wredundant-tags) +#list(APPEND REQUESTED_WARNING_FLAGS Wnull-dereference) +#list(APPEND REQUESTED_WARNING_FLAGS Wconversion) +#list(APPEND REQUESTED_WARNING_FLAGS Wzero-as-null-pointer-constant) +#list(APPEND REQUESTED_WARNING_FLAGS Wuseless-cast) +#list(APPEND REQUESTED_WARNING_FLAGS Wsuggest-override) +#list(APPEND REQUESTED_WARNING_FLAGS Wsuggest-final-types) +#list(APPEND REQUESTED_WARNING_FLAGS Wsuggest-final-methods) +#list(APPEND REQUESTED_WARNING_FLAGS Wsign-promo) +#list(APPEND REQUESTED_WARNING_FLAGS Wold-style-cast) +#list(APPEND REQUESTED_WARNING_FLAGS Walloc-zero) +# cmake-format: on + +if(DYNINST_EXTRA_WARNINGS) + list(APPEND REQUESTED_WARNING_FLAGS ${DYNINST_EXTRA_WARNINGS}) + message( + STATUS "DYNINST_EXTRA_WARNINGS set, adding extra warnings: ${DYNINST_EXTRA_WARNINGS}" + ) +endif() + +if(DYNINST_WARNINGS_AS_ERRORS) + list(APPEND REQUESTED_WARNING_FLAGS "Werror") + message(STATUS "DYNINST_WARNINGS_AS_ERRORS set: treating warnings as errors") +endif() + +# If not building with OpenMP or if static libs are enabled, ignore OpenMP pragma +# warnings +if(NOT USE_OpenMP OR ENABLE_STATIC_LIBS) + list(APPEND REQUESTED_WARNING_FLAGS "Wno-unknown-pragmas") +endif() + +if(CMAKE_C_COMPILER_ID MATCHES "^(GNU|Clang)$") + include(CheckCCompilerFlag) + foreach(f IN LISTS REQUESTED_WARNING_FLAGS) + string(REGEX REPLACE "[^a-zA-Z0-9]" "_" v "HAS_C_FLAG_${f}") + set(CMAKE_REQUIRED_FLAGS "-${f}") + check_c_source_compiles("int main(){return 0;}" "${v}" FAIL_REGEX + "warning: *command[- ]line option|-Wunknown-warning-option") + # Previous two lines are equivalent to below, but also catches a 0 exit status + # with a warning message output: check_c_compiler_flag("-${f}" "${v}") + if(${v}) + list(APPEND SUPPORTED_C_WARNING_FLAGS "-${f}") + if(f MATCHES "^(.*)=[0-9]+$") + # set generic variable if warning is parameterized with a number + string(REGEX REPLACE "[^a-zA-Z0-9]" "_" v "HAS_C_FLAG_${CMAKE_MATCH_1}") + set("${v}" 1) + endif() + endif() + endforeach() +endif() + +if(CMAKE_CXX_COMPILER_ID MATCHES "^(GNU|Clang)$") + include(CheckCXXCompilerFlag) + foreach(f IN LISTS REQUESTED_WARNING_FLAGS) + string(REGEX REPLACE "[^a-zA-Z0-9]" "_" v "HAS_CPP_FLAG_${f}") + set(CMAKE_REQUIRED_FLAGS "-${f}") + check_cxx_source_compiles("int main(){return 0;}" "${v}" FAIL_REGEX + "warning: *command[- ]line option|-Wunknown-warning-option") + if(${v}) + list(APPEND SUPPORTED_CXX_WARNING_FLAGS "-${f}") + if(f MATCHES "^(.*)=[0-9]+$") + string(REGEX REPLACE "[^a-zA-Z0-9]" "_" v "HAS_CPP_FLAG_${CMAKE_MATCH_1}") + set("${v}" 1) + endif() + endif() + endforeach() +endif() + +# cmake-format: off +# If -Wframe-larger-than is available adjust the value to allow for larger frames based on +# compiler version and build type for the following 3 files: +# +# instructionAPI/src/InstructionDecoder-power.C (includes instructionAPI/src/power-opcode-table.C) +# instructionAPI/src/AMDGPU/gfx90a/InstructionDecoder-amdgpu-gfx90a.C (includes instructionAPI/src/AMDGPU/gfx90a/finalizeOperands.C) +# common/src/MachSyscall.C (includes common/src/SyscallInformation.C) +# cmake-format: on +# +if(HAS_CPP_FLAG_Wframe_larger_than AND NOT DYNINST_DISABLE_DIAGNOSTIC_SUPPRESSIONS) + # Override the default frame size maximum for DEBUG (-O0) build types as there stack + # frames are larger: + # + add_compile_options($<$:-Wframe-larger-than=${defaultDebugMaxFrameSize}>) + + # Use worst-case values discovered so far. For most gcc versions SyscallInformation.C + # stack frame size is less than than the default and InstructionDecoder-power.C is + # less than 76800, but for some environments and compiler configurations the following + # are needed: + # + if(${CMAKE_CXX_COMPILER_ID} STREQUAL "GNU") + set(debugMaxFrameSizeOverrideSyscallInformation 81920) + set(debugMaxFrameSizeOverridePowerOpcodeTable 358400) + if(${CMAKE_CXX_COMPILER_VERSION} MATCHES "^[7](\.|$)") + set(nonDebugMaxFrameSizeOverridePowerOpcodeTable 38912) + endif() + # most gcc's are under the default using -Og, but rhel's requires 30000 + set(debugMaxFrameSizeOverrideFinalizeOperands 30000) + if(${CMAKE_CXX_COMPILER_VERSION} MATCHES "^[6](\.|$)") + set(nonDebugMaxFrameSizeOverrideFinalizeOperands 30000) + endif() + elseif(${CMAKE_CXX_COMPILER_ID} STREQUAL "Clang") + if(${CMAKE_CXX_COMPILER_VERSION} MATCHES "^1[3-7](\.|$)") + set(debugMaxFrameSizeOverridePowerOpcodeTable 40000) + else() + set(debugMaxFrameSizeOverridePowerOpcodeTable 30000) + endif() + set(nonDebugMaxFrameSizeOverridePowerOpcodeTable 38000) + set(debugMaxFrameSizeOverrideFinalizeOperands 29000) + set(nonDebugMaxFrameSizeOverrideFinalizeOperands 29000) + endif() +endif() + +unset(CMAKE_REQUIRED_FLAGS) + +if(MSVC) + message(STATUS "TODO: Set up custom warning flags for MSVC") +endif() + +message(STATUS "Using C warning flags: ${SUPPORTED_C_WARNING_FLAGS}") +message(STATUS "Using CXX warning flags: ${SUPPORTED_CXX_WARNING_FLAGS}") +message( + STATUS "Extra CXX DEBUG warning flags: -Wframe-larger-than=${defaultDebugMaxFrameSize}") diff --git a/cmake/ElfUtils.cmake b/cmake/ElfUtils.cmake deleted file mode 100644 index ec895c3a7a..0000000000 --- a/cmake/ElfUtils.cmake +++ /dev/null @@ -1,168 +0,0 @@ -#====================================================================================== -# elfutils.cmake -# -# Configure elfutils for Dyninst -# -# ---------------------------------------- -# -# Accepts the following CMake variables -# -# ElfUtils_ROOT_DIR - Base directory the of elfutils installation -# ElfUtils_INCLUDEDIR - Hint directory that contains the elfutils headers files -# ElfUtils_LIBRARYDIR - Hint directory that contains the elfutils library files -# ElfUtils_MIN_VERSION - Minimum acceptable version of elfutils -# -# Directly exports the following CMake variables -# -# ElfUtils_ROOT_DIR - Computed base directory the of elfutils installation -# ElfUtils_INCLUDE_DIRS - elfutils include directories -# ElfUtils_LIBRARY_DIRS - Link directories for elfutils libraries -# ElfUtils_LIBRARIES - elfutils library files -# -# NOTE: -# The exported ElfUtils_ROOT_DIR can be different from the value provided by the user -# in the case that it is determined to build elfutils from source. In such a case, -# ElfUtils_ROOT_DIR will contain the directory of the from-source installation. -# -# See Modules/FindLibElf.cmake and Modules/FindLibDwarf.cmake for details -# -#====================================================================================== - -if(LibElf_FOUND AND LibDwarf_FOUND AND NOT ENABLE_DEBUGINFOD) - return() -endif() - -if(NOT UNIX) - return() -endif() - -# Minimum acceptable version of elfutils -# NB: We need >=0.178 because libdw isn't thread-safe before then -set(_min_version 0.178) - -set(ElfUtils_MIN_VERSION ${_min_version} - CACHE STRING "Minimum acceptable elfutils version") -if(${ElfUtils_MIN_VERSION} VERSION_LESS ${_min_version}) - message( - FATAL_ERROR - "Requested version ${ElfUtils_MIN_VERSION} is less than minimum supported version (${_min_version})" - ) -endif() - -# -------------- PATHS -------------------------------------------------------- - -# Base directory the of elfutils installation -set(ElfUtils_ROOT_DIR "/usr" - CACHE PATH "Base directory the of elfutils installation") - -# Hint directory that contains the elfutils headers files -set(ElfUtils_INCLUDEDIR "${ElfUtils_ROOT_DIR}/include" - CACHE PATH "Hint directory that contains the elfutils headers files") - -# Hint directory that contains the elfutils library files -set(ElfUtils_LIBRARYDIR "${ElfUtils_ROOT_DIR}/lib" - CACHE PATH "Hint directory that contains the elfutils library files") - -# libelf/dwarf-specific directory hints -foreach(l LibElf LibDwarf LibDebuginfod) - foreach(d ROOT_DIR INCLUDEDIR LIBRARYDIR) - set(${l}_${d} ${ElfUtils_${d}}) - endforeach() -endforeach() - -# -------------- PACKAGES------------------------------------------------------ - -find_package(LibElf ${ElfUtils_MIN_VERSION}) - -# Don't search for libdw or libdebuginfod if we didn't find a suitable libelf -if(LibElf_FOUND) - find_package(LibDwarf ${ElfUtils_MIN_VERSION}) - if (ENABLE_DEBUGINFOD) - find_package(LibDebuginfod ${ElfUtils_MIN_VERSION} REQUIRED) - endif() -endif() - -# -------------- SOURCE BUILD ------------------------------------------------- -if(LibElf_FOUND AND LibDwarf_FOUND AND (NOT ENABLE_DEBUGINFOD OR LibDebuginfod_FOUND)) - if(ENABLE_DEBUGINFOD AND LibDebuginfod_FOUND) - set(_eu_root ${ElfUtils_ROOT_DIR}) - set(_eu_inc_dirs ${LibElf_INCLUDE_DIRS} ${LibDwarf_INCLUDE_DIRS} ${LibDebuginfod_INCLUDE_DIRS}) - set(_eu_lib_dirs ${LibElf_LIBRARY_DIRS} ${LibDwarf_LIBRARY_DIRS} ${LibDebuginfod_LIBRARY_DIRS}) - set(_eu_libs ${LibElf_LIBRARIES} ${LibDwarf_LIBRARIES} ${LibDebuginfod_LIBRARIES}) - else() - set(_eu_root ${ElfUtils_ROOT_DIR}) - set(_eu_inc_dirs ${LibElf_INCLUDE_DIRS} ${LibDwarf_INCLUDE_DIRS}) - set(_eu_lib_dirs ${LibElf_LIBRARY_DIRS} ${LibDwarf_LIBRARY_DIRS}) - set(_eu_libs ${LibElf_LIBRARIES} ${LibDwarf_LIBRARIES}) - endif() - add_library(ElfUtils SHARED IMPORTED) -elseif(NOT (LibElf_FOUND AND LibDwarf_FOUND) AND STERILE_BUILD) - message(FATAL_ERROR "Elfutils not found and cannot be downloaded because build is sterile.") -else() - # If we didn't find a suitable version on the system, then download one from the web - # NB: When building from source, we need at least elfutils-0.176 in order to use - # the --enable-install-elf option - set(_elfutils_download_version 0.176) - - # If the user specified a version newer than _elfutils_download_version, use that version. - # NB: We know ElfUtils_MIN_VERSION is >= _min_version from earlier checks - if(${ElfUtils_MIN_VERSION} VERSION_GREATER ${_elfutils_download_version}) - set(_elfutils_download_version ${ElfUtils_MIN_VERSION}) - endif() - - message(STATUS "${ElfUtils_ERROR_REASON}") - message( STATUS "Attempting to build elfutils(${_elfutils_download_version}) as external project") - - if(NOT (${CMAKE_CXX_COMPILER_ID} STREQUAL "GNU") OR NOT (${CMAKE_C_COMPILER_ID} STREQUAL "GNU")) - message(FATAL_ERROR "ElfUtils will only build with the GNU compiler") - endif() - - include(ExternalProject) - externalproject_add( - ElfUtils - PREFIX ${CMAKE_BINARY_DIR}/elfutils - URL https://sourceware.org/elfutils/ftp/${_elfutils_download_version}/elfutils-${_elfutils_download_version}.tar.bz2 - BUILD_IN_SOURCE 1 - CONFIGURE_COMMAND - CFLAGS=-g - CC=${CMAKE_C_COMPILER} CXX=${CMAKE_CXX_COMPILER} - /configure - --enable-install-elfh - --prefix=${CMAKE_INSTALL_PREFIX} - --disable-debuginfod - BUILD_COMMAND make install - INSTALL_COMMAND "" - ) - - set(_eu_root ${CMAKE_INSTALL_PREFIX}) - set(_eu_inc_dirs ${CMAKE_INSTALL_PREFIX}/include - ${CMAKE_INSTALL_PREFIX}/include/elfutils) - set(_eu_lib_dirs ${CMAKE_INSTALL_PREFIX}/lib - ${CMAKE_INSTALL_PREFIX}/lib/elfutils) - set(_eu_libs ${_eu_root}/lib/libelf.so ${_eu_root}/lib/libdw.so) -endif() - -# -------------- EXPORT VARIABLES --------------------------------------------- - -set(ElfUtils_ROOT_DIR ${_eu_root} - CACHE PATH "Base directory the of elfutils installation" - FORCE) -set(ElfUtils_INCLUDE_DIRS ${_eu_inc_dirs} - CACHE PATH "elfutils include directory" - FORCE) -set(ElfUtils_LIBRARY_DIRS ${_eu_lib_dirs} - CACHE PATH "elfutils library directory" - FORCE) -set(ElfUtils_INCLUDE_DIR ${ElfUtils_INCLUDE_DIRS} - CACHE PATH "elfutils include directory" - FORCE) -set(ElfUtils_LIBRARIES ${_eu_libs} - CACHE FILEPATH "elfutils library files" - FORCE) - -link_directories(${ElfUtils_LIBRARY_DIRS}) -include_directories(${ElfUtils_INCLUDE_DIRS}) - -message(STATUS "ElfUtils includes: ${ElfUtils_INCLUDE_DIRS}") -message(STATUS "ElfUtils library dirs: ${ElfUtils_LIBRARY_DIRS}") -message(STATUS "ElfUtils libraries: ${ElfUtils_LIBRARIES}") diff --git a/cmake/LibIberty.cmake b/cmake/LibIberty.cmake deleted file mode 100644 index 1d2ff1c537..0000000000 --- a/cmake/LibIberty.cmake +++ /dev/null @@ -1,71 +0,0 @@ -#====================================================================================== -# LibIberty.cmake -# -# Configure LibIberty for Dyninst -# -# ---------------------------------------- -# -# Directly exports the following CMake variables -# -# LibIberty_ROOT_DIR - Computed base directory the of LibIberty installation -# LibIberty_LIBRARY_DIRS - Link directories for LibIberty libraries -# LibIberty_LIBRARIES - LibIberty library files -# LibIberty_INCLUDE - LibIberty include files -# -# NOTE: -# The exported LibIberty_ROOT_DIR can be different from the value provided by the user -# in the case that it is determined to build LibIberty from source. In such a case, -# LibIberty_ROOT_DIR will contain the directory of the from-source installation. -# -# See Modules/FindLibIberty.cmake for details -# -#====================================================================================== - -if(LibIberty_FOUND) - return() -endif() - -if(NOT UNIX) - return() -endif() - -# -------------- PATHS -------------------------------------------------------- - -# Base directory the of LibIberty installation -set(LibIberty_ROOT_DIR "/usr" - CACHE PATH "Base directory the of LibIberty installation") - -# Hint directory that contains the LibIberty library files -set(LibIberty_LIBRARYDIR "${LibIberty_ROOT_DIR}/lib" - CACHE PATH "Hint directory that contains the LibIberty library files") - -# -------------- PACKAGES ----------------------------------------------------- - -find_package(LibIberty REQUIRED) - - -# -------------- EXPORT VARIABLES --------------------------------------------- - -add_library(LibIberty STATIC IMPORTED GLOBAL) -set_target_properties(LibIberty PROPERTIES IMPORTED_LOCATION ${LibIberty_LIBRARIES}) -set_target_properties(LibIberty PROPERTIES INTERFACE_INCLUDE_DIRECTORIES ${LibIberty_INCLUDE_DIRS}) - -set(LibIberty_ROOT_DIR ${LibIberty_ROOT_DIR} - CACHE PATH "Base directory the of LibIberty installation" - FORCE) -set(LibIberty_INCLUDE_DIRS ${LibIberty_INCLUDE_DIRS} - CACHE PATH "LibIberty include directories" - FORCE) -set(LibIberty_LIBRARY_DIRS ${LibIberty_LIBRARY_DIRS} - CACHE PATH "LibIberty library directory" - FORCE) -set(LibIberty_LIBRARIES ${LibIberty_LIBRARIES} - CACHE FILEPATH "LibIberty library files" - FORCE) - -# For backward compatibility only -set(IBERTY_LIBRARIES ${LibIberty_LIBRARIES}) - -message(STATUS "LibIberty include dirs: ${LibIberty_INCLUDE_DIRS}") -message(STATUS "LibIberty library dirs: ${LibIberty_LIBRARY_DIRS}") -message(STATUS "LibIberty libraries: ${LibIberty_LIBRARIES}") diff --git a/cmake/Modules/DyninstSystemPaths.cmake b/cmake/Modules/DyninstSystemPaths.cmake deleted file mode 100644 index ebabc6451d..0000000000 --- a/cmake/Modules/DyninstSystemPaths.cmake +++ /dev/null @@ -1,22 +0,0 @@ -set(DYNINST_SYSTEM_INCLUDE_PATHS - /usr/include - /usr/include/x86_64-linux-gnu - /usr/local/include - /opt/include - /opt/local/include - /sw/include - ENV CPATH - ENV PATH) - -set(DYNINST_SYSTEM_LIBRARY_PATHS - /usr/lib - /usr/lib64 - /usr/local/lib - /usr/local/lib64 - /usr/lib/x86_64-linux-gnu - /opt/local/lib - /opt/local/lib64 - /sw/lib - ENV LIBRARY_PATH - ENV LD_LIBRARY_PATH - ENV PATH) diff --git a/cmake/Modules/FindBoost.cmake b/cmake/Modules/FindBoost.cmake deleted file mode 100644 index 77c4bb9591..0000000000 --- a/cmake/Modules/FindBoost.cmake +++ /dev/null @@ -1,2186 +0,0 @@ -# Distributed under the OSI-approved BSD 3-Clause License. See accompanying -# file Copyright.txt or https://cmake.org/licensing for details. - -#[=======================================================================[.rst: -#FindBoost -#--------- -# -#Find Boost include dirs and libraries -# -#Use this module by invoking find_package with the form:: -# -# find_package(Boost -# [version] [EXACT] # Minimum or EXACT version e.g. 1.67.0 -# [REQUIRED] # Fail with error if Boost is not found -# [COMPONENTS ...] # Boost libraries by their canonical name -# # e.g. "date_time" for "libboost_date_time" -# [OPTIONAL_COMPONENTS ...] -# # Optional Boost libraries by their canonical name) -# ) # e.g. "date_time" for "libboost_date_time" -# -#This module finds headers and requested component libraries OR a CMake -#package configuration file provided by a "Boost CMake" build. For the -#latter case skip to the "Boost CMake" section below. For the former -#case results are reported in variables:: -# -# Boost_FOUND - True if headers and requested libraries were found -# Boost_INCLUDE_DIRS - Boost include directories -# Boost_LIBRARY_DIRS - Link directories for Boost libraries -# Boost_LIBRARIES - Boost component libraries to be linked -# Boost__FOUND - True if component was found ( is upper-case) -# Boost__LIBRARY - Libraries to link for component (may include -# target_link_libraries debug/optimized keywords) -# Boost_VERSION - BOOST_VERSION value from boost/version.hpp -# Boost_LIB_VERSION - Version string appended to library filenames -# Boost_MAJOR_VERSION - Boost major version number (X in X.y.z) -# Boost_MINOR_VERSION - Boost minor version number (Y in x.Y.z) -# Boost_SUBMINOR_VERSION - Boost subminor version number (Z in x.y.Z) -# Boost_VERSION_STRING - Boost version number in x.y.z format -# Boost_LIB_DIAGNOSTIC_DEFINITIONS (Windows) -# - Pass to add_definitions() to have diagnostic -# information about Boost's automatic linking -# displayed during compilation -# -#Note that Boost Python components require a Python version suffix -#(Boost 1.67 and later), e.g. ``python36`` or ``python27`` for the -#versions built against Python 3.6 and 2.7, respectively. This also -#applies to additional components using Python including -#``mpi_python`` and ``numpy``. Earlier Boost releases may use -#distribution-specific suffixes such as ``2``, ``3`` or ``2.7``. -#These may also be used as suffixes, but note that they are not -#portable. -# -#This module reads hints about search locations from variables:: -# -# BOOST_ROOT - Preferred installation prefix -# (or BOOSTROOT) -# BOOST_INCLUDEDIR - Preferred include directory e.g. /include -# BOOST_LIBRARYDIR - Preferred library directory e.g. /lib -# Boost_NO_SYSTEM_PATHS - Set to ON to disable searching in locations not -# specified by these hint variables. Default is OFF. -# Boost_ADDITIONAL_VERSIONS -# - List of Boost versions not known to this module -# (Boost install locations may contain the version) -# -#and saves search results persistently in CMake cache entries:: -# -# Boost_INCLUDE_DIR - Directory containing Boost headers -# Boost_LIBRARY_DIR_RELEASE - Directory containing release Boost libraries -# Boost_LIBRARY_DIR_DEBUG - Directory containing debug Boost libraries -# Boost__LIBRARY_DEBUG - Component library debug variant -# Boost__LIBRARY_RELEASE - Component library release variant -# -#The following :prop_tgt:`IMPORTED` targets are also defined:: -# -# Boost::boost - Target for header-only dependencies -# (Boost include directory) -# Boost:: - Target for specific component dependency -# (shared or static library); is lower- -# case -# Boost::diagnostic_definitions - interface target to enable diagnostic -# information about Boost's automatic linking -# during compilation (adds BOOST_LIB_DIAGNOSTIC) -# Boost::disable_autolinking - interface target to disable automatic -# linking with MSVC (adds BOOST_ALL_NO_LIB) -# Boost::dynamic_linking - interface target to enable dynamic linking -# linking with MSVC (adds BOOST_ALL_DYN_LINK) -# -#Implicit dependencies such as Boost::filesystem requiring -#Boost::system will be automatically detected and satisfied, even -#if system is not specified when using find_package and if -#Boost::system is not added to target_link_libraries. If using -#Boost::thread, then Threads::Threads will also be added automatically. -# -#It is important to note that the imported targets behave differently -#than variables created by this module: multiple calls to -#find_package(Boost) in the same directory or sub-directories with -#different options (e.g. static or shared) will not override the -#values of the targets created by the first call. -# -#Users may set these hints or results as cache entries. Projects -#should not read these entries directly but instead use the above -#result variables. Note that some hint names start in upper-case -#"BOOST". One may specify these as environment variables if they are -#not specified as CMake variables or cache entries. -# -#This module first searches for the Boost header files using the above -#hint variables (excluding BOOST_LIBRARYDIR) and saves the result in -#Boost_INCLUDE_DIR. Then it searches for requested component libraries -#using the above hints (excluding BOOST_INCLUDEDIR and -#Boost_ADDITIONAL_VERSIONS), "lib" directories near Boost_INCLUDE_DIR, -#and the library name configuration settings below. It saves the -#library directories in Boost_LIBRARY_DIR_DEBUG and -#Boost_LIBRARY_DIR_RELEASE and individual library -#locations in Boost__LIBRARY_DEBUG and Boost__LIBRARY_RELEASE. -#When one changes settings used by previous searches in the same build -#tree (excluding environment variables) this module discards previous -#search results affected by the changes and searches again. -# -#Boost libraries come in many variants encoded in their file name. -#Users or projects may tell this module which variant to find by -#setting variables:: -# -# Boost_USE_DEBUG_LIBS - Set to ON or OFF to specify whether to search -# and use the debug libraries. Default is ON. -# Boost_USE_RELEASE_LIBS - Set to ON or OFF to specify whether to search -# and use the release libraries. Default is ON. -# Boost_USE_MULTITHREADED - Set to OFF to use the non-multithreaded -# libraries ('mt' tag). Default is ON. -# Boost_USE_STATIC_LIBS - Set to ON to force the use of the static -# libraries. Default is OFF. -# Boost_USE_STATIC_RUNTIME - Set to ON or OFF to specify whether to use -# libraries linked statically to the C++ runtime -# ('s' tag). Default is platform dependent. -# Boost_USE_DEBUG_RUNTIME - Set to ON or OFF to specify whether to use -# libraries linked to the MS debug C++ runtime -# ('g' tag). Default is ON. -# Boost_USE_DEBUG_PYTHON - Set to ON to use libraries compiled with a -# debug Python build ('y' tag). Default is OFF. -# Boost_USE_STLPORT - Set to ON to use libraries compiled with -# STLPort ('p' tag). Default is OFF. -# Boost_USE_STLPORT_DEPRECATED_NATIVE_IOSTREAMS -# - Set to ON to use libraries compiled with -# STLPort deprecated "native iostreams" -# ('n' tag). Default is OFF. -# Boost_COMPILER - Set to the compiler-specific library suffix -# (e.g. "-gcc43"). Default is auto-computed -# for the C++ compiler in use. A list may be -# used if multiple compatible suffixes should -# be tested for, in decreasing order of -# preference. -# Boost_ARCHITECTURE - Set to the architecture-specific library suffix -# (e.g. "-x64"). Default is auto-computed for the -# C++ compiler in use. -# Boost_THREADAPI - Suffix for "thread" component library name, -# such as "pthread" or "win32". Names with -# and without this suffix will both be tried. -# Boost_NAMESPACE - Alternate namespace used to build boost with -# e.g. if set to "myboost", will search for -# myboost_thread instead of boost_thread. -# -#Other variables one may set to control this module are:: -# -# Boost_DEBUG - Set to ON to enable debug output from FindBoost. -# Please enable this before filing any bug report. -# Boost_DETAILED_FAILURE_MSG -# - Set to ON to add detailed information to the -# failure message even when the REQUIRED option -# is not given to the find_package call. -# Boost_REALPATH - Set to ON to resolve symlinks for discovered -# libraries to assist with packaging. For example, -# the "system" component library may be resolved to -# "/usr/lib/libboost_system.so.1.67.0" instead of -# "/usr/lib/libboost_system.so". This does not -# affect linking and should not be enabled unless -# the user needs this information. -# Boost_LIBRARY_DIR - Default value for Boost_LIBRARY_DIR_RELEASE and -# Boost_LIBRARY_DIR_DEBUG. -# -#On Visual Studio and Borland compilers Boost headers request automatic -#linking to corresponding libraries. This requires matching libraries -#to be linked explicitly or available in the link library search path. -#In this case setting Boost_USE_STATIC_LIBS to OFF may not achieve -#dynamic linking. Boost automatic linking typically requests static -#libraries with a few exceptions (such as Boost.Python). Use:: -# -# add_definitions(${Boost_LIB_DIAGNOSTIC_DEFINITIONS}) -# -#to ask Boost to report information about automatic linking requests. -# -#Example to find Boost headers only:: -# -# find_package(Boost 1.36.0) -# if(Boost_FOUND) -# include_directories(${Boost_INCLUDE_DIRS}) -# add_executable(foo foo.cc) -# endif() -# -#Example to find Boost libraries and use imported targets:: -# -# find_package(Boost 1.56 REQUIRED COMPONENTS -# date_time filesystem iostreams) -# add_executable(foo foo.cc) -# target_link_libraries(foo Boost::date_time Boost::filesystem -# Boost::iostreams) -# -#Example to find Boost Python 3.6 libraries and use imported targets:: -# -# find_package(Boost 1.67 REQUIRED COMPONENTS -# python36 numpy36) -# add_executable(foo foo.cc) -# target_link_libraries(foo Boost::python36 Boost::numpy36) -# -#Example to find Boost headers and some *static* (release only) libraries:: -# -# set(Boost_USE_STATIC_LIBS ON) # only find static libs -# set(Boost_USE_DEBUG_LIBS OFF) # ignore debug libs and -# set(Boost_USE_RELEASE_LIBS ON) # only find release libs -# set(Boost_USE_MULTITHREADED ON) -# set(Boost_USE_STATIC_RUNTIME OFF) -# find_package(Boost 1.66.0 COMPONENTS date_time filesystem system ...) -# if(Boost_FOUND) -# include_directories(${Boost_INCLUDE_DIRS}) -# add_executable(foo foo.cc) -# target_link_libraries(foo ${Boost_LIBRARIES}) -# endif() -# -#Boost CMake -#^^^^^^^^^^^ -# -#If Boost was built using the boost-cmake project it provides a package -#configuration file for use with find_package's Config mode. This -#module looks for the package configuration file called -#BoostConfig.cmake or boost-config.cmake and stores the result in cache -#entry "Boost_DIR". If found, the package configuration file is loaded -#and this module returns with no further action. See documentation of -#the Boost CMake package configuration for details on what it provides. -# -#Set Boost_NO_BOOST_CMAKE to ON to disable the search for boost-cmake. -#]=======================================================================] - -# Save project's policies -cmake_policy(PUSH) -cmake_policy(SET CMP0057 NEW) # if IN_LIST - -#------------------------------------------------------------------------------- -# Before we go searching, check whether boost-cmake is available, unless the -# user specifically asked NOT to search for boost-cmake. -# -# If Boost_DIR is set, this behaves as any find_package call would. If not, -# it looks at BOOST_ROOT and BOOSTROOT to find Boost. -# -if (NOT Boost_NO_BOOST_CMAKE) - # If Boost_DIR is not set, look for BOOSTROOT and BOOST_ROOT as alternatives, - # since these are more conventional for Boost. - if ("$ENV{Boost_DIR}" STREQUAL "") - if (NOT "$ENV{BOOST_ROOT}" STREQUAL "") - set(ENV{Boost_DIR} $ENV{BOOST_ROOT}) - elseif (NOT "$ENV{BOOSTROOT}" STREQUAL "") - set(ENV{Boost_DIR} $ENV{BOOSTROOT}) - endif() - endif() - - # Do the same find_package call but look specifically for the CMake version. - # Note that args are passed in the Boost_FIND_xxxxx variables, so there is no - # need to delegate them to this find_package call. - find_package(Boost QUIET NO_MODULE) - mark_as_advanced(Boost_DIR) - - # If we found boost-cmake, then we're done. Print out what we found. - # Otherwise let the rest of the module try to find it. - if (Boost_FOUND) - message(STATUS "Boost ${Boost_FIND_VERSION} found.") - if (Boost_FIND_COMPONENTS) - message(STATUS "Found Boost components:\n ${Boost_FIND_COMPONENTS}") - endif() - # Restore project's policies - cmake_policy(POP) - return() - endif() -endif() - - -#------------------------------------------------------------------------------- -# FindBoost functions & macros -# - -############################################ -# -# Check the existence of the libraries. -# -############################################ -# This macro was taken directly from the FindQt4.cmake file that is included -# with the CMake distribution. This is NOT my work. All work was done by the -# original authors of the FindQt4.cmake file. Only minor modifications were -# made to remove references to Qt and make this file more generally applicable -# And ELSE/ENDIF pairs were removed for readability. -######################################################################### - -macro(_Boost_ADJUST_LIB_VARS basename) - if(Boost_INCLUDE_DIR ) - if(Boost_${basename}_LIBRARY_DEBUG AND Boost_${basename}_LIBRARY_RELEASE) - # if the generator is multi-config or if CMAKE_BUILD_TYPE is set for - # single-config generators, set optimized and debug libraries - get_property(_isMultiConfig GLOBAL PROPERTY GENERATOR_IS_MULTI_CONFIG) - if(_isMultiConfig OR CMAKE_BUILD_TYPE) - set(Boost_${basename}_LIBRARY optimized ${Boost_${basename}_LIBRARY_RELEASE} debug ${Boost_${basename}_LIBRARY_DEBUG}) - else() - # For single-config generators where CMAKE_BUILD_TYPE has no value, - # just use the release libraries - set(Boost_${basename}_LIBRARY ${Boost_${basename}_LIBRARY_RELEASE} ) - endif() - # FIXME: This probably should be set for both cases - set(Boost_${basename}_LIBRARIES optimized ${Boost_${basename}_LIBRARY_RELEASE} debug ${Boost_${basename}_LIBRARY_DEBUG}) - endif() - - # if only the release version was found, set the debug variable also to the release version - if(Boost_${basename}_LIBRARY_RELEASE AND NOT Boost_${basename}_LIBRARY_DEBUG) - set(Boost_${basename}_LIBRARY_DEBUG ${Boost_${basename}_LIBRARY_RELEASE}) - set(Boost_${basename}_LIBRARY ${Boost_${basename}_LIBRARY_RELEASE}) - set(Boost_${basename}_LIBRARIES ${Boost_${basename}_LIBRARY_RELEASE}) - endif() - - # if only the debug version was found, set the release variable also to the debug version - if(Boost_${basename}_LIBRARY_DEBUG AND NOT Boost_${basename}_LIBRARY_RELEASE) - set(Boost_${basename}_LIBRARY_RELEASE ${Boost_${basename}_LIBRARY_DEBUG}) - set(Boost_${basename}_LIBRARY ${Boost_${basename}_LIBRARY_DEBUG}) - set(Boost_${basename}_LIBRARIES ${Boost_${basename}_LIBRARY_DEBUG}) - endif() - - # If the debug & release library ends up being the same, omit the keywords - if("${Boost_${basename}_LIBRARY_RELEASE}" STREQUAL "${Boost_${basename}_LIBRARY_DEBUG}") - set(Boost_${basename}_LIBRARY ${Boost_${basename}_LIBRARY_RELEASE} ) - set(Boost_${basename}_LIBRARIES ${Boost_${basename}_LIBRARY_RELEASE} ) - endif() - - if(Boost_${basename}_LIBRARY AND Boost_${basename}_HEADER) - set(Boost_${basename}_FOUND ON) - if("x${basename}" STREQUAL "xTHREAD" AND NOT TARGET Threads::Threads) - string(APPEND Boost_ERROR_REASON_THREAD " (missing dependency: Threads)") - set(Boost_THREAD_FOUND OFF) - endif() - endif() - - endif() - # Make variables changeable to the advanced user - mark_as_advanced( - Boost_${basename}_LIBRARY_RELEASE - Boost_${basename}_LIBRARY_DEBUG - ) -endmacro() - -# Detect changes in used variables. -# Compares the current variable value with the last one. -# In short form: -# v != v_LAST -> CHANGED = 1 -# v is defined, v_LAST not -> CHANGED = 1 -# v is not defined, but v_LAST is -> CHANGED = 1 -# otherwise -> CHANGED = 0 -# CHANGED is returned in variable named ${changed_var} -macro(_Boost_CHANGE_DETECT changed_var) - set(${changed_var} 0) - foreach(v ${ARGN}) - if(DEFINED _Boost_COMPONENTS_SEARCHED) - if(${v}) - if(_${v}_LAST) - string(COMPARE NOTEQUAL "${${v}}" "${_${v}_LAST}" _${v}_CHANGED) - else() - set(_${v}_CHANGED 1) - endif() - elseif(_${v}_LAST) - set(_${v}_CHANGED 1) - endif() - if(_${v}_CHANGED) - set(${changed_var} 1) - endif() - else() - set(_${v}_CHANGED 0) - endif() - endforeach() -endmacro() - -# -# Find the given library (var). -# Use 'build_type' to support different lib paths for RELEASE or DEBUG builds -# -macro(_Boost_FIND_LIBRARY var build_type) - - find_library(${var} ${ARGN}) - - if(${var}) - # If this is the first library found then save Boost_LIBRARY_DIR_[RELEASE,DEBUG]. - if(NOT Boost_LIBRARY_DIR_${build_type}) - get_filename_component(_dir "${${var}}" PATH) - set(Boost_LIBRARY_DIR_${build_type} "${_dir}" CACHE PATH "Boost library directory ${build_type}" FORCE) - endif() - elseif(_Boost_FIND_LIBRARY_HINTS_FOR_COMPONENT) - # Try component-specific hints but do not save Boost_LIBRARY_DIR_[RELEASE,DEBUG]. - find_library(${var} HINTS ${_Boost_FIND_LIBRARY_HINTS_FOR_COMPONENT} ${ARGN}) - endif() - - # If Boost_LIBRARY_DIR_[RELEASE,DEBUG] is known then search only there. - if(Boost_LIBRARY_DIR_${build_type}) - set(_boost_LIBRARY_SEARCH_DIRS_${build_type} ${Boost_LIBRARY_DIR_${build_type}} NO_DEFAULT_PATH NO_CMAKE_FIND_ROOT_PATH) - if(Boost_DEBUG) - message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " - " Boost_LIBRARY_DIR_${build_type} = ${Boost_LIBRARY_DIR_${build_type}}" - " _boost_LIBRARY_SEARCH_DIRS_${build_type} = ${_boost_LIBRARY_SEARCH_DIRS_${build_type}}") - endif() - endif() -endmacro() - -#------------------------------------------------------------------------------- - -# Convert CMAKE_CXX_COMPILER_VERSION to boost compiler suffix version. -function(_Boost_COMPILER_DUMPVERSION _OUTPUT_VERSION _OUTPUT_VERSION_MAJOR _OUTPUT_VERSION_MINOR) - string(REGEX REPLACE "([0-9]+)\\.([0-9]+)(\\.[0-9]+)?" "\\1" - _boost_COMPILER_VERSION_MAJOR "${CMAKE_CXX_COMPILER_VERSION}") - string(REGEX REPLACE "([0-9]+)\\.([0-9]+)(\\.[0-9]+)?" "\\2" - _boost_COMPILER_VERSION_MINOR "${CMAKE_CXX_COMPILER_VERSION}") - - set(_boost_COMPILER_VERSION "${_boost_COMPILER_VERSION_MAJOR}${_boost_COMPILER_VERSION_MINOR}") - - set(${_OUTPUT_VERSION} ${_boost_COMPILER_VERSION} PARENT_SCOPE) - set(${_OUTPUT_VERSION_MAJOR} ${_boost_COMPILER_VERSION_MAJOR} PARENT_SCOPE) - set(${_OUTPUT_VERSION_MINOR} ${_boost_COMPILER_VERSION_MINOR} PARENT_SCOPE) -endfunction() - -# -# Take a list of libraries with "thread" in it -# and prepend duplicates with "thread_${Boost_THREADAPI}" -# at the front of the list -# -function(_Boost_PREPEND_LIST_WITH_THREADAPI _output) - set(_orig_libnames ${ARGN}) - string(REPLACE "thread" "thread_${Boost_THREADAPI}" _threadapi_libnames "${_orig_libnames}") - set(${_output} ${_threadapi_libnames} ${_orig_libnames} PARENT_SCOPE) -endfunction() - -# -# If a library is found, replace its cache entry with its REALPATH -# -function(_Boost_SWAP_WITH_REALPATH _library _docstring) - if(${_library}) - get_filename_component(_boost_filepathreal ${${_library}} REALPATH) - unset(${_library} CACHE) - set(${_library} ${_boost_filepathreal} CACHE FILEPATH "${_docstring}") - endif() -endfunction() - -function(_Boost_CHECK_SPELLING _var) - if(${_var}) - string(TOUPPER ${_var} _var_UC) - message(FATAL_ERROR "ERROR: ${_var} is not the correct spelling. The proper spelling is ${_var_UC}.") - endif() -endfunction() - -# Guesses Boost's compiler prefix used in built library names -# Returns the guess by setting the variable pointed to by _ret -function(_Boost_GUESS_COMPILER_PREFIX _ret) - if("x${CMAKE_CXX_COMPILER_ID}" STREQUAL "xIntel") - if(WIN32) - set (_boost_COMPILER "-iw") - else() - set (_boost_COMPILER "-il") - endif() - elseif (GHSMULTI) - set(_boost_COMPILER "-ghs") - elseif("x${CMAKE_CXX_COMPILER_ID}" STREQUAL "xMSVC") - if(MSVC_TOOLSET_VERSION GREATER_EQUAL 141) - set(_boost_COMPILER "-vc141;-vc140") - elseif(MSVC_TOOLSET_VERSION GREATER_EQUAL 80) - set(_boost_COMPILER "-vc${MSVC_TOOLSET_VERSION}") - elseif(NOT CMAKE_CXX_COMPILER_VERSION VERSION_LESS 13.10) - set(_boost_COMPILER "-vc71") - elseif(NOT CMAKE_CXX_COMPILER_VERSION VERSION_LESS 13) # Good luck! - set(_boost_COMPILER "-vc7") # yes, this is correct - else() # VS 6.0 Good luck! - set(_boost_COMPILER "-vc6") # yes, this is correct - endif() - elseif (BORLAND) - set(_boost_COMPILER "-bcb") - elseif(CMAKE_CXX_COMPILER_ID STREQUAL "SunPro") - set(_boost_COMPILER "-sw") - elseif(CMAKE_CXX_COMPILER_ID STREQUAL "XL") - set(_boost_COMPILER "-xlc") - elseif (MINGW) - if(${Boost_MAJOR_VERSION}.${Boost_MINOR_VERSION} VERSION_LESS 1.34) - set(_boost_COMPILER "-mgw") # no GCC version encoding prior to 1.34 - else() - _Boost_COMPILER_DUMPVERSION(_boost_COMPILER_VERSION _boost_COMPILER_VERSION_MAJOR _boost_COMPILER_VERSION_MINOR) - set(_boost_COMPILER "-mgw${_boost_COMPILER_VERSION}") - endif() - elseif (UNIX) - _Boost_COMPILER_DUMPVERSION(_boost_COMPILER_VERSION _boost_COMPILER_VERSION_MAJOR _boost_COMPILER_VERSION_MINOR) - if(NOT Boost_VERSION VERSION_LESS 106900) - # From GCC 5 and clang 4, versioning changes and minor becomes patch. - # For those compilers, patch is exclude from compiler tag in Boost 1.69+ library naming. - if(CMAKE_CXX_COMPILER_ID STREQUAL "GNU" AND _boost_COMPILER_VERSION_MAJOR VERSION_GREATER 4) - set(_boost_COMPILER_VERSION "${_boost_COMPILER_VERSION_MAJOR}") - elseif(CMAKE_CXX_COMPILER_ID STREQUAL "Clang" AND _boost_COMPILER_VERSION_MAJOR VERSION_GREATER 3) - set(_boost_COMPILER_VERSION "${_boost_COMPILER_VERSION_MAJOR}") - endif() - endif() - - if(CMAKE_CXX_COMPILER_ID STREQUAL "GNU") - if(${Boost_MAJOR_VERSION}.${Boost_MINOR_VERSION} VERSION_LESS 1.34) - set(_boost_COMPILER "-gcc") # no GCC version encoding prior to 1.34 - else() - # Determine which version of GCC we have. - if(APPLE) - if(Boost_MINOR_VERSION) - if(${Boost_MINOR_VERSION} GREATER 35) - # In Boost 1.36.0 and newer, the mangled compiler name used - # on macOS/Darwin is "xgcc". - set(_boost_COMPILER "-xgcc${_boost_COMPILER_VERSION}") - else() - # In Boost <= 1.35.0, there is no mangled compiler name for - # the macOS/Darwin version of GCC. - set(_boost_COMPILER "") - endif() - else() - # We don't know the Boost version, so assume it's - # pre-1.36.0. - set(_boost_COMPILER "") - endif() - else() - set(_boost_COMPILER "-gcc${_boost_COMPILER_VERSION}") - endif() - endif() - elseif(CMAKE_CXX_COMPILER_ID STREQUAL "Clang") - # TODO: Find out any Boost version constraints vs clang support. - set(_boost_COMPILER "-clang${_boost_COMPILER_VERSION}") - endif() - else() - # TODO at least Boost_DEBUG here? - set(_boost_COMPILER "") - endif() - set(${_ret} ${_boost_COMPILER} PARENT_SCOPE) -endfunction() - -# -# Get component dependencies. Requires the dependencies to have been -# defined for the Boost release version. -# -# component - the component to check -# _ret - list of library dependencies -# -function(_Boost_COMPONENT_DEPENDENCIES component _ret) - # Note: to add a new Boost release, run - # - # % cmake -DBOOST_DIR=/path/to/boost/source -P Utilities/Scripts/BoostScanDeps.cmake - # - # The output may be added in a new block below. If it's the same as - # the previous release, simply update the version range of the block - # for the previous release. Also check if any new components have - # been added, and add any new components to - # _Boost_COMPONENT_HEADERS. - # - # This information was originally generated by running - # BoostScanDeps.cmake against every boost release to date supported - # by FindBoost: - # - # % for version in /path/to/boost/sources/* - # do - # cmake -DBOOST_DIR=$version -P Utilities/Scripts/BoostScanDeps.cmake - # done - # - # The output was then updated by search and replace with these regexes: - # - # - Strip message(STATUS) prefix dashes - # s;^-- ;; - # - Indent - # s;^set(; set(;; - # - Add conditionals - # s;Scanning /path/to/boost/sources/boost_\(.*\)_\(.*\)_\(.*); elseif(NOT Boost_VERSION VERSION_LESS \10\20\3 AND Boost_VERSION VERSION_LESS xxxx); - # - # This results in the logic seen below, but will require the xxxx - # replacing with the following Boost release version (or the next - # minor version to be released, e.g. 1.59 was the latest at the time - # of writing, making 1.60 the next, so 106000 is the needed version - # number). Identical consecutive releases were then merged together - # by updating the end range of the first block and removing the - # following redundant blocks. - # - # Running the script against all historical releases should be - # required only if the BoostScanDeps.cmake script logic is changed. - # The addition of a new release should only require it to be run - # against the new release. - - # Handle Python version suffixes - if(component MATCHES "^(python|mpi_python|numpy)([0-9][0-9]?|[0-9]\\.[0-9])\$") - set(component "${CMAKE_MATCH_1}") - set(component_python_version "${CMAKE_MATCH_2}") - endif() - - set(_Boost_IMPORTED_TARGETS TRUE) - if(Boost_VERSION AND Boost_VERSION VERSION_LESS 103300) - message(WARNING "Imported targets and dependency information not available for Boost version ${Boost_VERSION} (all versions older than 1.33)") - set(_Boost_IMPORTED_TARGETS FALSE) - elseif(NOT Boost_VERSION VERSION_LESS 103300 AND Boost_VERSION VERSION_LESS 103500) - set(_Boost_IOSTREAMS_DEPENDENCIES regex thread) - set(_Boost_REGEX_DEPENDENCIES thread) - set(_Boost_WAVE_DEPENDENCIES filesystem thread) - set(_Boost_WSERIALIZATION_DEPENDENCIES serialization) - elseif(NOT Boost_VERSION VERSION_LESS 103500 AND Boost_VERSION VERSION_LESS 103600) - set(_Boost_FILESYSTEM_DEPENDENCIES system) - set(_Boost_IOSTREAMS_DEPENDENCIES regex) - set(_Boost_MPI_DEPENDENCIES serialization) - set(_Boost_MPI_PYTHON_DEPENDENCIES python${component_python_version} mpi serialization) - set(_Boost_WAVE_DEPENDENCIES filesystem system thread) - set(_Boost_WSERIALIZATION_DEPENDENCIES serialization) - elseif(NOT Boost_VERSION VERSION_LESS 103600 AND Boost_VERSION VERSION_LESS 103800) - set(_Boost_FILESYSTEM_DEPENDENCIES system) - set(_Boost_IOSTREAMS_DEPENDENCIES regex) - set(_Boost_MATH_DEPENDENCIES math_c99 math_c99f math_c99l math_tr1 math_tr1f math_tr1l) - set(_Boost_MPI_DEPENDENCIES serialization) - set(_Boost_MPI_PYTHON_DEPENDENCIES python${component_python_version} mpi serialization) - set(_Boost_WAVE_DEPENDENCIES filesystem system thread) - set(_Boost_WSERIALIZATION_DEPENDENCIES serialization) - elseif(NOT Boost_VERSION VERSION_LESS 103800 AND Boost_VERSION VERSION_LESS 104300) - set(_Boost_FILESYSTEM_DEPENDENCIES system) - set(_Boost_IOSTREAMS_DEPENDENCIES regex) - set(_Boost_MATH_DEPENDENCIES math_c99 math_c99f math_c99l math_tr1 math_tr1f math_tr1l) - set(_Boost_MPI_DEPENDENCIES serialization) - set(_Boost_MPI_PYTHON_DEPENDENCIES python${component_python_version} mpi serialization) - set(_Boost_THREAD_DEPENDENCIES date_time) - set(_Boost_WAVE_DEPENDENCIES filesystem system thread date_time) - set(_Boost_WSERIALIZATION_DEPENDENCIES serialization) - elseif(NOT Boost_VERSION VERSION_LESS 104300 AND Boost_VERSION VERSION_LESS 104400) - set(_Boost_FILESYSTEM_DEPENDENCIES system) - set(_Boost_IOSTREAMS_DEPENDENCIES regex) - set(_Boost_MATH_DEPENDENCIES math_c99 math_c99f math_c99l math_tr1 math_tr1f math_tr1l random) - set(_Boost_MPI_DEPENDENCIES serialization) - set(_Boost_MPI_PYTHON_DEPENDENCIES python${component_python_version} mpi serialization) - set(_Boost_THREAD_DEPENDENCIES date_time) - set(_Boost_WAVE_DEPENDENCIES filesystem system thread date_time) - set(_Boost_WSERIALIZATION_DEPENDENCIES serialization) - elseif(NOT Boost_VERSION VERSION_LESS 104400 AND Boost_VERSION VERSION_LESS 104500) - set(_Boost_FILESYSTEM_DEPENDENCIES system) - set(_Boost_IOSTREAMS_DEPENDENCIES regex) - set(_Boost_MATH_DEPENDENCIES math_c99 math_c99f math_c99l math_tr1 math_tr1f math_tr1l random serialization) - set(_Boost_MPI_DEPENDENCIES serialization) - set(_Boost_MPI_PYTHON_DEPENDENCIES python${component_python_version} mpi serialization) - set(_Boost_THREAD_DEPENDENCIES date_time) - set(_Boost_WAVE_DEPENDENCIES serialization filesystem system thread date_time) - set(_Boost_WSERIALIZATION_DEPENDENCIES serialization) - elseif(NOT Boost_VERSION VERSION_LESS 104500 AND Boost_VERSION VERSION_LESS 104700) - set(_Boost_FILESYSTEM_DEPENDENCIES system) - set(_Boost_IOSTREAMS_DEPENDENCIES regex) - set(_Boost_MATH_DEPENDENCIES math_c99 math_c99f math_c99l math_tr1 math_tr1f math_tr1l random) - set(_Boost_MPI_DEPENDENCIES serialization) - set(_Boost_MPI_PYTHON_DEPENDENCIES python${component_python_version} mpi serialization) - set(_Boost_THREAD_DEPENDENCIES date_time) - set(_Boost_WAVE_DEPENDENCIES filesystem system serialization thread date_time) - set(_Boost_WSERIALIZATION_DEPENDENCIES serialization) - elseif(NOT Boost_VERSION VERSION_LESS 104700 AND Boost_VERSION VERSION_LESS 104800) - set(_Boost_CHRONO_DEPENDENCIES system) - set(_Boost_FILESYSTEM_DEPENDENCIES system) - set(_Boost_IOSTREAMS_DEPENDENCIES regex) - set(_Boost_MATH_DEPENDENCIES math_c99 math_c99f math_c99l math_tr1 math_tr1f math_tr1l random) - set(_Boost_MPI_DEPENDENCIES serialization) - set(_Boost_MPI_PYTHON_DEPENDENCIES python${component_python_version} mpi serialization) - set(_Boost_THREAD_DEPENDENCIES date_time) - set(_Boost_WAVE_DEPENDENCIES filesystem system serialization thread date_time) - set(_Boost_WSERIALIZATION_DEPENDENCIES serialization) - elseif(NOT Boost_VERSION VERSION_LESS 104800 AND Boost_VERSION VERSION_LESS 105000) - set(_Boost_CHRONO_DEPENDENCIES system) - set(_Boost_FILESYSTEM_DEPENDENCIES system) - set(_Boost_IOSTREAMS_DEPENDENCIES regex) - set(_Boost_MATH_DEPENDENCIES math_c99 math_c99f math_c99l math_tr1 math_tr1f math_tr1l random) - set(_Boost_MPI_DEPENDENCIES serialization) - set(_Boost_MPI_PYTHON_DEPENDENCIES python${component_python_version} mpi serialization) - set(_Boost_THREAD_DEPENDENCIES date_time) - set(_Boost_TIMER_DEPENDENCIES chrono system) - set(_Boost_WAVE_DEPENDENCIES filesystem system serialization thread date_time) - set(_Boost_WSERIALIZATION_DEPENDENCIES serialization) - elseif(NOT Boost_VERSION VERSION_LESS 105000 AND Boost_VERSION VERSION_LESS 105300) - set(_Boost_CHRONO_DEPENDENCIES system) - set(_Boost_FILESYSTEM_DEPENDENCIES system) - set(_Boost_IOSTREAMS_DEPENDENCIES regex) - set(_Boost_MATH_DEPENDENCIES math_c99 math_c99f math_c99l math_tr1 math_tr1f math_tr1l regex random) - set(_Boost_MPI_DEPENDENCIES serialization) - set(_Boost_MPI_PYTHON_DEPENDENCIES python${component_python_version} mpi serialization) - set(_Boost_THREAD_DEPENDENCIES chrono system date_time) - set(_Boost_TIMER_DEPENDENCIES chrono system) - set(_Boost_WAVE_DEPENDENCIES filesystem system serialization thread chrono date_time) - set(_Boost_WSERIALIZATION_DEPENDENCIES serialization) - elseif(NOT Boost_VERSION VERSION_LESS 105300 AND Boost_VERSION VERSION_LESS 105400) - set(_Boost_ATOMIC_DEPENDENCIES thread chrono system date_time) - set(_Boost_CHRONO_DEPENDENCIES system) - set(_Boost_FILESYSTEM_DEPENDENCIES system) - set(_Boost_IOSTREAMS_DEPENDENCIES regex) - set(_Boost_MATH_DEPENDENCIES math_c99 math_c99f math_c99l math_tr1 math_tr1f math_tr1l regex random) - set(_Boost_MPI_DEPENDENCIES serialization) - set(_Boost_MPI_PYTHON_DEPENDENCIES python${component_python_version} mpi serialization) - set(_Boost_THREAD_DEPENDENCIES chrono system date_time atomic) - set(_Boost_TIMER_DEPENDENCIES chrono system) - set(_Boost_WAVE_DEPENDENCIES filesystem system serialization thread chrono date_time) - set(_Boost_WSERIALIZATION_DEPENDENCIES serialization) - elseif(NOT Boost_VERSION VERSION_LESS 105400 AND Boost_VERSION VERSION_LESS 105500) - set(_Boost_ATOMIC_DEPENDENCIES thread chrono system date_time) - set(_Boost_CHRONO_DEPENDENCIES system) - set(_Boost_FILESYSTEM_DEPENDENCIES system) - set(_Boost_IOSTREAMS_DEPENDENCIES regex) - set(_Boost_LOG_DEPENDENCIES log_setup date_time system filesystem thread regex chrono) - set(_Boost_MATH_DEPENDENCIES math_c99 math_c99f math_c99l math_tr1 math_tr1f math_tr1l regex random) - set(_Boost_MPI_DEPENDENCIES serialization) - set(_Boost_MPI_PYTHON_DEPENDENCIES python${component_python_version} mpi serialization) - set(_Boost_THREAD_DEPENDENCIES chrono system date_time atomic) - set(_Boost_TIMER_DEPENDENCIES chrono system) - set(_Boost_WAVE_DEPENDENCIES filesystem system serialization thread chrono date_time atomic) - set(_Boost_WSERIALIZATION_DEPENDENCIES serialization) - elseif(NOT Boost_VERSION VERSION_LESS 105500 AND Boost_VERSION VERSION_LESS 105600) - set(_Boost_CHRONO_DEPENDENCIES system) - set(_Boost_COROUTINE_DEPENDENCIES context system) - set(_Boost_FILESYSTEM_DEPENDENCIES system) - set(_Boost_IOSTREAMS_DEPENDENCIES regex) - set(_Boost_LOG_DEPENDENCIES log_setup date_time system filesystem thread regex chrono) - set(_Boost_MATH_DEPENDENCIES math_c99 math_c99f math_c99l math_tr1 math_tr1f math_tr1l regex random) - set(_Boost_MPI_DEPENDENCIES serialization) - set(_Boost_MPI_PYTHON_DEPENDENCIES python${component_python_version} mpi serialization) - set(_Boost_THREAD_DEPENDENCIES chrono system date_time atomic) - set(_Boost_TIMER_DEPENDENCIES chrono system) - set(_Boost_WAVE_DEPENDENCIES filesystem system serialization thread chrono date_time atomic) - set(_Boost_WSERIALIZATION_DEPENDENCIES serialization) - elseif(NOT Boost_VERSION VERSION_LESS 105600 AND Boost_VERSION VERSION_LESS 105900) - set(_Boost_CHRONO_DEPENDENCIES system) - set(_Boost_COROUTINE_DEPENDENCIES context system) - set(_Boost_FILESYSTEM_DEPENDENCIES system) - set(_Boost_IOSTREAMS_DEPENDENCIES regex) - set(_Boost_LOG_DEPENDENCIES log_setup date_time system filesystem thread regex chrono) - set(_Boost_MATH_DEPENDENCIES math_c99 math_c99f math_c99l math_tr1 math_tr1f math_tr1l atomic) - set(_Boost_MPI_DEPENDENCIES serialization) - set(_Boost_MPI_PYTHON_DEPENDENCIES python${component_python_version} mpi serialization) - set(_Boost_RANDOM_DEPENDENCIES system) - set(_Boost_THREAD_DEPENDENCIES chrono system date_time atomic) - set(_Boost_TIMER_DEPENDENCIES chrono system) - set(_Boost_WAVE_DEPENDENCIES filesystem system serialization thread chrono date_time atomic) - set(_Boost_WSERIALIZATION_DEPENDENCIES serialization) - elseif(NOT Boost_VERSION VERSION_LESS 105900 AND Boost_VERSION VERSION_LESS 106000) - set(_Boost_CHRONO_DEPENDENCIES system) - set(_Boost_COROUTINE_DEPENDENCIES context system) - set(_Boost_FILESYSTEM_DEPENDENCIES system) - set(_Boost_IOSTREAMS_DEPENDENCIES regex) - set(_Boost_LOG_DEPENDENCIES log_setup date_time system filesystem thread regex chrono atomic) - set(_Boost_MATH_DEPENDENCIES math_c99 math_c99f math_c99l math_tr1 math_tr1f math_tr1l atomic) - set(_Boost_MPI_DEPENDENCIES serialization) - set(_Boost_MPI_PYTHON_DEPENDENCIES python${component_python_version} mpi serialization) - set(_Boost_RANDOM_DEPENDENCIES system) - set(_Boost_THREAD_DEPENDENCIES chrono system date_time atomic) - set(_Boost_TIMER_DEPENDENCIES chrono system) - set(_Boost_WAVE_DEPENDENCIES filesystem system serialization thread chrono date_time atomic) - set(_Boost_WSERIALIZATION_DEPENDENCIES serialization) - elseif(NOT Boost_VERSION VERSION_LESS 106000 AND Boost_VERSION VERSION_LESS 106100) - set(_Boost_CHRONO_DEPENDENCIES system) - set(_Boost_COROUTINE_DEPENDENCIES context system) - set(_Boost_FILESYSTEM_DEPENDENCIES system) - set(_Boost_IOSTREAMS_DEPENDENCIES regex) - set(_Boost_LOG_DEPENDENCIES date_time log_setup system filesystem thread regex chrono atomic) - set(_Boost_MATH_DEPENDENCIES math_c99 math_c99f math_c99l math_tr1 math_tr1f math_tr1l atomic) - set(_Boost_MPI_DEPENDENCIES serialization) - set(_Boost_MPI_PYTHON_DEPENDENCIES python${component_python_version} mpi serialization) - set(_Boost_RANDOM_DEPENDENCIES system) - set(_Boost_THREAD_DEPENDENCIES chrono system date_time atomic) - set(_Boost_TIMER_DEPENDENCIES chrono system) - set(_Boost_WAVE_DEPENDENCIES filesystem system serialization thread chrono date_time atomic) - set(_Boost_WSERIALIZATION_DEPENDENCIES serialization) - elseif(NOT Boost_VERSION VERSION_LESS 106100 AND Boost_VERSION VERSION_LESS 106200) - set(_Boost_CHRONO_DEPENDENCIES system) - set(_Boost_CONTEXT_DEPENDENCIES thread chrono system date_time) - set(_Boost_COROUTINE_DEPENDENCIES context system) - set(_Boost_FILESYSTEM_DEPENDENCIES system) - set(_Boost_IOSTREAMS_DEPENDENCIES regex) - set(_Boost_LOG_DEPENDENCIES date_time log_setup system filesystem thread regex chrono atomic) - set(_Boost_MATH_DEPENDENCIES math_c99 math_c99f math_c99l math_tr1 math_tr1f math_tr1l atomic) - set(_Boost_MPI_DEPENDENCIES serialization) - set(_Boost_MPI_PYTHON_DEPENDENCIES python${component_python_version} mpi serialization) - set(_Boost_RANDOM_DEPENDENCIES system) - set(_Boost_THREAD_DEPENDENCIES chrono system date_time atomic) - set(_Boost_WAVE_DEPENDENCIES filesystem system serialization thread chrono date_time atomic) - set(_Boost_WSERIALIZATION_DEPENDENCIES serialization) - elseif(NOT Boost_VERSION VERSION_LESS 106200 AND Boost_VERSION VERSION_LESS 106300) - set(_Boost_CHRONO_DEPENDENCIES system) - set(_Boost_CONTEXT_DEPENDENCIES thread chrono system date_time) - set(_Boost_COROUTINE_DEPENDENCIES context system) - set(_Boost_FIBER_DEPENDENCIES context thread chrono system date_time) - set(_Boost_FILESYSTEM_DEPENDENCIES system) - set(_Boost_IOSTREAMS_DEPENDENCIES regex) - set(_Boost_LOG_DEPENDENCIES date_time log_setup system filesystem thread regex chrono atomic) - set(_Boost_MATH_DEPENDENCIES math_c99 math_c99f math_c99l math_tr1 math_tr1f math_tr1l atomic) - set(_Boost_MPI_DEPENDENCIES serialization) - set(_Boost_MPI_PYTHON_DEPENDENCIES python${component_python_version} mpi serialization) - set(_Boost_RANDOM_DEPENDENCIES system) - set(_Boost_THREAD_DEPENDENCIES chrono system date_time atomic) - set(_Boost_WAVE_DEPENDENCIES filesystem system serialization thread chrono date_time atomic) - set(_Boost_WSERIALIZATION_DEPENDENCIES serialization) - elseif(NOT Boost_VERSION VERSION_LESS 106300 AND Boost_VERSION VERSION_LESS 106500) - set(_Boost_CHRONO_DEPENDENCIES system) - set(_Boost_CONTEXT_DEPENDENCIES thread chrono system date_time) - set(_Boost_COROUTINE_DEPENDENCIES context system) - set(_Boost_COROUTINE2_DEPENDENCIES context fiber thread chrono system date_time) - set(_Boost_FIBER_DEPENDENCIES context thread chrono system date_time) - set(_Boost_FILESYSTEM_DEPENDENCIES system) - set(_Boost_IOSTREAMS_DEPENDENCIES regex) - set(_Boost_LOG_DEPENDENCIES date_time log_setup system filesystem thread regex chrono atomic) - set(_Boost_MATH_DEPENDENCIES math_c99 math_c99f math_c99l math_tr1 math_tr1f math_tr1l atomic) - set(_Boost_MPI_DEPENDENCIES serialization) - set(_Boost_MPI_PYTHON_DEPENDENCIES python${component_python_version} mpi serialization) - set(_Boost_RANDOM_DEPENDENCIES system) - set(_Boost_THREAD_DEPENDENCIES chrono system date_time atomic) - set(_Boost_WAVE_DEPENDENCIES filesystem system serialization thread chrono date_time atomic) - set(_Boost_WSERIALIZATION_DEPENDENCIES serialization) - elseif(NOT Boost_VERSION VERSION_LESS 106500 AND Boost_VERSION VERSION_LESS 106700) - set(_Boost_CHRONO_DEPENDENCIES system) - set(_Boost_CONTEXT_DEPENDENCIES thread chrono system date_time) - set(_Boost_COROUTINE_DEPENDENCIES context system) - set(_Boost_FIBER_DEPENDENCIES context thread chrono system date_time) - set(_Boost_FILESYSTEM_DEPENDENCIES system) - set(_Boost_IOSTREAMS_DEPENDENCIES regex) - set(_Boost_LOG_DEPENDENCIES date_time log_setup system filesystem thread regex chrono atomic) - set(_Boost_MATH_DEPENDENCIES math_c99 math_c99f math_c99l math_tr1 math_tr1f math_tr1l atomic) - set(_Boost_MPI_DEPENDENCIES serialization) - set(_Boost_MPI_PYTHON_DEPENDENCIES python${component_python_version} mpi serialization) - set(_Boost_NUMPY_DEPENDENCIES python${component_python_version}) - set(_Boost_RANDOM_DEPENDENCIES system) - set(_Boost_THREAD_DEPENDENCIES chrono system date_time atomic) - set(_Boost_TIMER_DEPENDENCIES chrono system) - set(_Boost_WAVE_DEPENDENCIES filesystem system serialization thread chrono date_time atomic) - set(_Boost_WSERIALIZATION_DEPENDENCIES serialization) - elseif(NOT Boost_VERSION VERSION_LESS 106700 AND Boost_VERSION VERSION_LESS 106800) - set(_Boost_CHRONO_DEPENDENCIES system) - set(_Boost_CONTEXT_DEPENDENCIES thread chrono system date_time) - set(_Boost_COROUTINE_DEPENDENCIES context system) - set(_Boost_FIBER_DEPENDENCIES context thread chrono system date_time) - set(_Boost_FILESYSTEM_DEPENDENCIES system) - set(_Boost_IOSTREAMS_DEPENDENCIES regex) - set(_Boost_LOG_DEPENDENCIES date_time log_setup system filesystem thread regex chrono atomic) - set(_Boost_MATH_DEPENDENCIES math_c99 math_c99f math_c99l math_tr1 math_tr1f math_tr1l atomic) - set(_Boost_MPI_DEPENDENCIES serialization) - set(_Boost_MPI_PYTHON_DEPENDENCIES python${component_python_version} mpi serialization) - set(_Boost_NUMPY_DEPENDENCIES python${component_python_version}) - set(_Boost_RANDOM_DEPENDENCIES system) - set(_Boost_THREAD_DEPENDENCIES chrono system date_time atomic) - set(_Boost_TIMER_DEPENDENCIES chrono system) - set(_Boost_WAVE_DEPENDENCIES filesystem system serialization thread chrono date_time atomic) - set(_Boost_WSERIALIZATION_DEPENDENCIES serialization) - elseif(NOT Boost_VERSION VERSION_LESS 106800 AND Boost_VERSION VERSION_LESS 106900) - set(_Boost_CHRONO_DEPENDENCIES system) - set(_Boost_CONTEXT_DEPENDENCIES thread chrono system date_time) - set(_Boost_CONTRACT_DEPENDENCIES thread chrono system date_time) - set(_Boost_COROUTINE_DEPENDENCIES context system) - set(_Boost_FIBER_DEPENDENCIES context thread chrono system date_time) - set(_Boost_FILESYSTEM_DEPENDENCIES system) - set(_Boost_IOSTREAMS_DEPENDENCIES regex) - set(_Boost_LOG_DEPENDENCIES date_time log_setup system filesystem thread regex chrono atomic) - set(_Boost_MATH_DEPENDENCIES math_c99 math_c99f math_c99l math_tr1 math_tr1f math_tr1l atomic) - set(_Boost_MPI_DEPENDENCIES serialization) - set(_Boost_MPI_PYTHON_DEPENDENCIES python${component_python_version} mpi serialization) - set(_Boost_NUMPY_DEPENDENCIES python${component_python_version}) - set(_Boost_RANDOM_DEPENDENCIES system) - set(_Boost_THREAD_DEPENDENCIES chrono system date_time atomic) - set(_Boost_TIMER_DEPENDENCIES chrono system) - set(_Boost_WAVE_DEPENDENCIES filesystem system serialization thread chrono date_time atomic) - set(_Boost_WSERIALIZATION_DEPENDENCIES serialization) - elseif(NOT Boost_VERSION VERSION_LESS 106900 AND Boost_VERSION VERSION_LESS 107000) - set(_Boost_CONTRACT_DEPENDENCIES thread chrono date_time) - set(_Boost_COROUTINE_DEPENDENCIES context) - set(_Boost_FIBER_DEPENDENCIES context) - set(_Boost_IOSTREAMS_DEPENDENCIES regex) - set(_Boost_LOG_DEPENDENCIES date_time log_setup filesystem thread regex chrono atomic) - set(_Boost_MATH_DEPENDENCIES math_c99 math_c99f math_c99l math_tr1 math_tr1f math_tr1l atomic) - set(_Boost_MPI_DEPENDENCIES serialization) - set(_Boost_MPI_PYTHON_DEPENDENCIES python${component_python_version} mpi serialization) - set(_Boost_NUMPY_DEPENDENCIES python${component_python_version}) - set(_Boost_THREAD_DEPENDENCIES chrono date_time atomic) - set(_Boost_TIMER_DEPENDENCIES chrono system) - set(_Boost_WAVE_DEPENDENCIES filesystem serialization thread chrono date_time atomic) - set(_Boost_WSERIALIZATION_DEPENDENCIES serialization) - else() - if(NOT Boost_VERSION VERSION_LESS 107000) - set(_Boost_CONTRACT_DEPENDENCIES thread chrono date_time) - set(_Boost_COROUTINE_DEPENDENCIES context) - set(_Boost_FIBER_DEPENDENCIES context) - set(_Boost_IOSTREAMS_DEPENDENCIES regex) - set(_Boost_LOG_DEPENDENCIES date_time log_setup filesystem thread regex chrono atomic) - set(_Boost_MATH_DEPENDENCIES math_c99 math_c99f math_c99l math_tr1 math_tr1f math_tr1l atomic) - set(_Boost_MPI_DEPENDENCIES serialization) - set(_Boost_MPI_PYTHON_DEPENDENCIES python${component_python_version} mpi serialization) - set(_Boost_NUMPY_DEPENDENCIES python${component_python_version}) - set(_Boost_THREAD_DEPENDENCIES chrono date_time atomic) - set(_Boost_TIMER_DEPENDENCIES chrono system) - set(_Boost_WAVE_DEPENDENCIES filesystem serialization thread chrono date_time atomic) - set(_Boost_WSERIALIZATION_DEPENDENCIES serialization) - endif() - if(NOT Boost_VERSION VERSION_LESS 107100) - message(WARNING "New Boost version may have incorrect or missing dependencies and imported targets") - endif() - endif() - - string(TOUPPER ${component} uppercomponent) - set(${_ret} ${_Boost_${uppercomponent}_DEPENDENCIES} PARENT_SCOPE) - set(_Boost_IMPORTED_TARGETS ${_Boost_IMPORTED_TARGETS} PARENT_SCOPE) - - string(REGEX REPLACE ";" " " _boost_DEPS_STRING "${_Boost_${uppercomponent}_DEPENDENCIES}") - if (NOT _boost_DEPS_STRING) - set(_boost_DEPS_STRING "(none)") - endif() - # message(STATUS "Dependencies for Boost::${component}: ${_boost_DEPS_STRING}") -endfunction() - -# -# Get component headers. This is the primary header (or headers) for -# a given component, and is used to check that the headers are present -# as well as the library itself as an extra sanity check of the build -# environment. -# -# component - the component to check -# _hdrs -# -function(_Boost_COMPONENT_HEADERS component _hdrs) - # Handle Python version suffixes - if(component MATCHES "^(python|mpi_python|numpy)([0-9][0-9]?|[0-9]\\.[0-9])\$") - set(component "${CMAKE_MATCH_1}") - set(component_python_version "${CMAKE_MATCH_2}") - endif() - - # Note: new boost components will require adding here. The header - # must be present in all versions of Boost providing a library. - set(_Boost_ATOMIC_HEADERS "boost/atomic.hpp") - set(_Boost_CHRONO_HEADERS "boost/chrono.hpp") - set(_Boost_CONTAINER_HEADERS "boost/container/container_fwd.hpp") - set(_Boost_CONTRACT_HEADERS "boost/contract.hpp") - if(Boost_VERSION VERSION_LESS 106100) - set(_Boost_CONTEXT_HEADERS "boost/context/all.hpp") - else() - set(_Boost_CONTEXT_HEADERS "boost/context/detail/fcontext.hpp") - endif() - set(_Boost_COROUTINE_HEADERS "boost/coroutine/all.hpp") - set(_Boost_DATE_TIME_HEADERS "boost/date_time/date.hpp") - set(_Boost_EXCEPTION_HEADERS "boost/exception/exception.hpp") - set(_Boost_FIBER_HEADERS "boost/fiber/all.hpp") - set(_Boost_FILESYSTEM_HEADERS "boost/filesystem/path.hpp") - set(_Boost_GRAPH_HEADERS "boost/graph/adjacency_list.hpp") - set(_Boost_GRAPH_PARALLEL_HEADERS "boost/graph/adjacency_list.hpp") - set(_Boost_IOSTREAMS_HEADERS "boost/iostreams/stream.hpp") - set(_Boost_LOCALE_HEADERS "boost/locale.hpp") - set(_Boost_LOG_HEADERS "boost/log/core.hpp") - set(_Boost_LOG_SETUP_HEADERS "boost/log/detail/setup_config.hpp") - set(_Boost_MATH_HEADERS "boost/math_fwd.hpp") - set(_Boost_MATH_C99_HEADERS "boost/math/tr1.hpp") - set(_Boost_MATH_C99F_HEADERS "boost/math/tr1.hpp") - set(_Boost_MATH_C99L_HEADERS "boost/math/tr1.hpp") - set(_Boost_MATH_TR1_HEADERS "boost/math/tr1.hpp") - set(_Boost_MATH_TR1F_HEADERS "boost/math/tr1.hpp") - set(_Boost_MATH_TR1L_HEADERS "boost/math/tr1.hpp") - set(_Boost_MPI_HEADERS "boost/mpi.hpp") - set(_Boost_MPI_PYTHON_HEADERS "boost/mpi/python/config.hpp") - set(_Boost_NUMPY_HEADERS "boost/python/numpy.hpp") - set(_Boost_PRG_EXEC_MONITOR_HEADERS "boost/test/prg_exec_monitor.hpp") - set(_Boost_PROGRAM_OPTIONS_HEADERS "boost/program_options.hpp") - set(_Boost_PYTHON_HEADERS "boost/python.hpp") - set(_Boost_RANDOM_HEADERS "boost/random.hpp") - set(_Boost_REGEX_HEADERS "boost/regex.hpp") - set(_Boost_SERIALIZATION_HEADERS "boost/serialization/serialization.hpp") - set(_Boost_SIGNALS_HEADERS "boost/signals.hpp") - set(_Boost_STACKTRACE_ADDR2LINE_HEADERS "boost/stacktrace.hpp") - set(_Boost_STACKTRACE_BACKTRACE_HEADERS "boost/stacktrace.hpp") - set(_Boost_STACKTRACE_BASIC_HEADERS "boost/stacktrace.hpp") - set(_Boost_STACKTRACE_NOOP_HEADERS "boost/stacktrace.hpp") - set(_Boost_STACKTRACE_WINDBG_CACHED_HEADERS "boost/stacktrace.hpp") - set(_Boost_STACKTRACE_WINDBG_HEADERS "boost/stacktrace.hpp") - set(_Boost_SYSTEM_HEADERS "boost/system/config.hpp") - set(_Boost_TEST_EXEC_MONITOR_HEADERS "boost/test/test_exec_monitor.hpp") - set(_Boost_THREAD_HEADERS "boost/thread.hpp") - set(_Boost_TIMER_HEADERS "boost/timer.hpp") - set(_Boost_TYPE_ERASURE_HEADERS "boost/type_erasure/config.hpp") - set(_Boost_UNIT_TEST_FRAMEWORK_HEADERS "boost/test/framework.hpp") - set(_Boost_WAVE_HEADERS "boost/wave.hpp") - set(_Boost_WSERIALIZATION_HEADERS "boost/archive/text_wiarchive.hpp") - if(WIN32) - set(_Boost_BZIP2_HEADERS "boost/iostreams/filter/bzip2.hpp") - set(_Boost_ZLIB_HEADERS "boost/iostreams/filter/zlib.hpp") - endif() - - string(TOUPPER ${component} uppercomponent) - set(${_hdrs} ${_Boost_${uppercomponent}_HEADERS} PARENT_SCOPE) - - string(REGEX REPLACE ";" " " _boost_HDRS_STRING "${_Boost_${uppercomponent}_HEADERS}") - if (NOT _boost_HDRS_STRING) - set(_boost_HDRS_STRING "(none)") - endif() - # message(STATUS "Headers for Boost::${component}: ${_boost_HDRS_STRING}") -endfunction() - -# -# Determine if any missing dependencies require adding to the component list. -# -# Sets _Boost_${COMPONENT}_DEPENDENCIES for each required component, -# plus _Boost_IMPORTED_TARGETS (TRUE if imported targets should be -# defined; FALSE if dependency information is unavailable). -# -# componentvar - the component list variable name -# extravar - the indirect dependency list variable name -# -# -function(_Boost_MISSING_DEPENDENCIES componentvar extravar) - # _boost_unprocessed_components - list of components requiring processing - # _boost_processed_components - components already processed (or currently being processed) - # _boost_new_components - new components discovered for future processing - # - list(APPEND _boost_unprocessed_components ${${componentvar}}) - - while(_boost_unprocessed_components) - list(APPEND _boost_processed_components ${_boost_unprocessed_components}) - foreach(component ${_boost_unprocessed_components}) - string(TOUPPER ${component} uppercomponent) - set(${_ret} ${_Boost_${uppercomponent}_DEPENDENCIES} PARENT_SCOPE) - _Boost_COMPONENT_DEPENDENCIES("${component}" _Boost_${uppercomponent}_DEPENDENCIES) - set(_Boost_${uppercomponent}_DEPENDENCIES ${_Boost_${uppercomponent}_DEPENDENCIES} PARENT_SCOPE) - set(_Boost_IMPORTED_TARGETS ${_Boost_IMPORTED_TARGETS} PARENT_SCOPE) - foreach(componentdep ${_Boost_${uppercomponent}_DEPENDENCIES}) - if (NOT ("${componentdep}" IN_LIST _boost_processed_components OR "${componentdep}" IN_LIST _boost_new_components)) - list(APPEND _boost_new_components ${componentdep}) - endif() - endforeach() - endforeach() - set(_boost_unprocessed_components ${_boost_new_components}) - unset(_boost_new_components) - endwhile() - set(_boost_extra_components ${_boost_processed_components}) - if(_boost_extra_components AND ${componentvar}) - list(REMOVE_ITEM _boost_extra_components ${${componentvar}}) - endif() - set(${componentvar} ${_boost_processed_components} PARENT_SCOPE) - set(${extravar} ${_boost_extra_components} PARENT_SCOPE) -endfunction() - -# -# Some boost libraries may require particular set of compler features. -# The very first one was `boost::fiber` introduced in Boost 1.62. -# One can check required compiler features of it in -# `${Boost_ROOT}/libs/fiber/build/Jamfile.v2`. -# -function(_Boost_COMPILER_FEATURES component _ret) - # Boost >= 1.62 and < 1.67 - if(NOT Boost_VERSION VERSION_LESS 106200 AND Boost_VERSION VERSION_LESS 106700) - set(_Boost_FIBER_COMPILER_FEATURES - cxx_alias_templates - cxx_auto_type - cxx_constexpr - cxx_defaulted_functions - cxx_final - cxx_lambdas - cxx_noexcept - cxx_nullptr - cxx_rvalue_references - cxx_thread_local - cxx_variadic_templates - ) - endif() - string(TOUPPER ${component} uppercomponent) - set(${_ret} ${_Boost_${uppercomponent}_COMPILER_FEATURES} PARENT_SCOPE) -endfunction() - -# -# Update library search directory hint variable with paths used by prebuilt boost binaries. -# -# Prebuilt windows binaries (https://sourceforge.net/projects/boost/files/boost-binaries/) -# have library directories named using MSVC compiler version and architecture. -# This function would append corresponding directories if MSVC is a current compiler, -# so having `BOOST_ROOT` would be enough to specify to find everything. -# -function(_Boost_UPDATE_WINDOWS_LIBRARY_SEARCH_DIRS_WITH_PREBUILT_PATHS componentlibvar basedir) - if("x${CMAKE_CXX_COMPILER_ID}" STREQUAL "xMSVC") - if(CMAKE_SIZEOF_VOID_P EQUAL 8) - set(_arch_suffix 64) - else() - set(_arch_suffix 32) - endif() - if(MSVC_TOOLSET_VERSION GREATER_EQUAL 141) - list(APPEND ${componentlibvar} ${basedir}/lib${_arch_suffix}-msvc-14.1) - list(APPEND ${componentlibvar} ${basedir}/lib${_arch_suffix}-msvc-14.0) - elseif(MSVC_TOOLSET_VERSION GREATER_EQUAL 80) - math(EXPR _toolset_major_version "${MSVC_TOOLSET_VERSION} / 10") - list(APPEND ${componentlibvar} ${basedir}/lib${_arch_suffix}-msvc-${_toolset_major_version}.0) - endif() - set(${componentlibvar} ${${componentlibvar}} PARENT_SCOPE) - endif() -endfunction() - -# -# End functions/macros -# -#------------------------------------------------------------------------------- - -#------------------------------------------------------------------------------- -# main. -#------------------------------------------------------------------------------- - - -# If the user sets Boost_LIBRARY_DIR, use it as the default for both -# configurations. -if(NOT Boost_LIBRARY_DIR_RELEASE AND Boost_LIBRARY_DIR) - set(Boost_LIBRARY_DIR_RELEASE "${Boost_LIBRARY_DIR}") -endif() -if(NOT Boost_LIBRARY_DIR_DEBUG AND Boost_LIBRARY_DIR) - set(Boost_LIBRARY_DIR_DEBUG "${Boost_LIBRARY_DIR}") -endif() - -if(NOT DEFINED Boost_USE_DEBUG_LIBS) - set(Boost_USE_DEBUG_LIBS TRUE) -endif() -if(NOT DEFINED Boost_USE_RELEASE_LIBS) - set(Boost_USE_RELEASE_LIBS TRUE) -endif() -if(NOT DEFINED Boost_USE_MULTITHREADED) - set(Boost_USE_MULTITHREADED TRUE) -endif() -if(NOT DEFINED Boost_USE_DEBUG_RUNTIME) - set(Boost_USE_DEBUG_RUNTIME TRUE) -endif() - -# Check the version of Boost against the requested version. -if(Boost_FIND_VERSION AND NOT Boost_FIND_VERSION_MINOR) - message(SEND_ERROR "When requesting a specific version of Boost, you must provide at least the major and minor version numbers, e.g., 1.34") -endif() - -if(Boost_FIND_VERSION_EXACT) - # The version may appear in a directory with or without the patch - # level, even when the patch level is non-zero. - set(_boost_TEST_VERSIONS - "${Boost_FIND_VERSION_MAJOR}.${Boost_FIND_VERSION_MINOR}.${Boost_FIND_VERSION_PATCH}" - "${Boost_FIND_VERSION_MAJOR}.${Boost_FIND_VERSION_MINOR}") -else() - # The user has not requested an exact version. Among known - # versions, find those that are acceptable to the user request. - # - # Note: When adding a new Boost release, also update the dependency - # information in _Boost_COMPONENT_DEPENDENCIES and - # _Boost_COMPONENT_HEADERS. See the instructions at the top of - # _Boost_COMPONENT_DEPENDENCIES. - set(_Boost_KNOWN_VERSIONS ${Boost_ADDITIONAL_VERSIONS} - "1.70.0" "1.70" "1.69.0" "1.69" - "1.68.0" "1.68" "1.67.0" "1.67" "1.66.0" "1.66" "1.65.1" "1.65.0" "1.65" - "1.64.0" "1.64" "1.63.0" "1.63" "1.62.0" "1.62" "1.61.0" "1.61" "1.60.0" "1.60" - "1.59.0" "1.59" "1.58.0" "1.58" "1.57.0" "1.57" "1.56.0" "1.56" "1.55.0" "1.55" - "1.54.0" "1.54" "1.53.0" "1.53" "1.52.0" "1.52" "1.51.0" "1.51" - "1.50.0" "1.50" "1.49.0" "1.49" "1.48.0" "1.48" "1.47.0" "1.47" "1.46.1" - "1.46.0" "1.46" "1.45.0" "1.45" "1.44.0" "1.44" "1.43.0" "1.43" "1.42.0" "1.42" - "1.41.0" "1.41" "1.40.0" "1.40" "1.39.0" "1.39" "1.38.0" "1.38" "1.37.0" "1.37" - "1.36.1" "1.36.0" "1.36" "1.35.1" "1.35.0" "1.35" "1.34.1" "1.34.0" - "1.34" "1.33.1" "1.33.0" "1.33") - - set(_boost_TEST_VERSIONS) - if(Boost_FIND_VERSION) - set(_Boost_FIND_VERSION_SHORT "${Boost_FIND_VERSION_MAJOR}.${Boost_FIND_VERSION_MINOR}") - # Select acceptable versions. - foreach(version ${_Boost_KNOWN_VERSIONS}) - if(NOT "${version}" VERSION_LESS "${Boost_FIND_VERSION}") - # This version is high enough. - list(APPEND _boost_TEST_VERSIONS "${version}") - elseif("${version}.99" VERSION_EQUAL "${_Boost_FIND_VERSION_SHORT}.99") - # This version is a short-form for the requested version with - # the patch level dropped. - list(APPEND _boost_TEST_VERSIONS "${version}") - endif() - endforeach() - else() - # Any version is acceptable. - set(_boost_TEST_VERSIONS "${_Boost_KNOWN_VERSIONS}") - endif() -endif() - -# The reason that we failed to find Boost. This will be set to a -# user-friendly message when we fail to find some necessary piece of -# Boost. -set(Boost_ERROR_REASON) - -if(Boost_DEBUG) - # Output some of their choices - message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " - "_boost_TEST_VERSIONS = ${_boost_TEST_VERSIONS}") - message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " - "Boost_USE_MULTITHREADED = ${Boost_USE_MULTITHREADED}") - message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " - "Boost_USE_STATIC_LIBS = ${Boost_USE_STATIC_LIBS}") - message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " - "Boost_USE_STATIC_RUNTIME = ${Boost_USE_STATIC_RUNTIME}") - message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " - "Boost_ADDITIONAL_VERSIONS = ${Boost_ADDITIONAL_VERSIONS}") - message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " - "Boost_NO_SYSTEM_PATHS = ${Boost_NO_SYSTEM_PATHS}") -endif() - -# Supply Boost_LIB_DIAGNOSTIC_DEFINITIONS as a convenience target. It -# will only contain any interface definitions on WIN32, but is created -# on all platforms to keep end user code free from platform dependent -# code. Also provide convenience targets to disable autolinking and -# enable dynamic linking. -if(NOT TARGET Boost::diagnostic_definitions) - add_library(Boost::diagnostic_definitions INTERFACE IMPORTED) - add_library(Boost::disable_autolinking INTERFACE IMPORTED) - add_library(Boost::dynamic_linking INTERFACE IMPORTED) - set_target_properties(Boost::dynamic_linking PROPERTIES - INTERFACE_COMPILE_DEFINITIONS "BOOST_ALL_DYN_LINK") -endif() -if(WIN32) - # In windows, automatic linking is performed, so you do not have - # to specify the libraries. If you are linking to a dynamic - # runtime, then you can choose to link to either a static or a - # dynamic Boost library, the default is to do a static link. You - # can alter this for a specific library "whatever" by defining - # BOOST_WHATEVER_DYN_LINK to force Boost library "whatever" to be - # linked dynamically. Alternatively you can force all Boost - # libraries to dynamic link by defining BOOST_ALL_DYN_LINK. - - # This feature can be disabled for Boost library "whatever" by - # defining BOOST_WHATEVER_NO_LIB, or for all of Boost by defining - # BOOST_ALL_NO_LIB. - - # If you want to observe which libraries are being linked against - # then defining BOOST_LIB_DIAGNOSTIC will cause the auto-linking - # code to emit a #pragma message each time a library is selected - # for linking. - set(Boost_LIB_DIAGNOSTIC_DEFINITIONS "-DBOOST_LIB_DIAGNOSTIC") - set_target_properties(Boost::diagnostic_definitions PROPERTIES - INTERFACE_COMPILE_DEFINITIONS "BOOST_LIB_DIAGNOSTIC") - set_target_properties(Boost::disable_autolinking PROPERTIES - INTERFACE_COMPILE_DEFINITIONS "BOOST_ALL_NO_LIB") -endif() - -_Boost_CHECK_SPELLING(Boost_ROOT) -_Boost_CHECK_SPELLING(Boost_LIBRARYDIR) -_Boost_CHECK_SPELLING(Boost_INCLUDEDIR) - -# Collect environment variable inputs as hints. Do not consider changes. -foreach(v BOOSTROOT BOOST_ROOT BOOST_INCLUDEDIR BOOST_LIBRARYDIR) - set(_env $ENV{${v}}) - if(_env) - file(TO_CMAKE_PATH "${_env}" _ENV_${v}) - else() - set(_ENV_${v} "") - endif() -endforeach() -if(NOT _ENV_BOOST_ROOT AND _ENV_BOOSTROOT) - set(_ENV_BOOST_ROOT "${_ENV_BOOSTROOT}") -endif() - -# Collect inputs and cached results. Detect changes since the last run. -if(NOT BOOST_ROOT AND BOOSTROOT) - set(BOOST_ROOT "${BOOSTROOT}") -endif() -set(_Boost_VARS_DIR - BOOST_ROOT - Boost_NO_SYSTEM_PATHS - ) - -if(Boost_DEBUG) - message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " - "Declared as CMake or Environmental Variables:") - message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " - " BOOST_ROOT = ${BOOST_ROOT}") - message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " - " BOOST_INCLUDEDIR = ${BOOST_INCLUDEDIR}") - message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " - " BOOST_LIBRARYDIR = ${BOOST_LIBRARYDIR}") - message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " - "_boost_TEST_VERSIONS = ${_boost_TEST_VERSIONS}") -endif() - -# ------------------------------------------------------------------------ -# Search for Boost include DIR -# ------------------------------------------------------------------------ - -set(_Boost_VARS_INC BOOST_INCLUDEDIR Boost_INCLUDE_DIR Boost_ADDITIONAL_VERSIONS) -_Boost_CHANGE_DETECT(_Boost_CHANGE_INCDIR ${_Boost_VARS_DIR} ${_Boost_VARS_INC}) -# Clear Boost_INCLUDE_DIR if it did not change but other input affecting the -# location did. We will find a new one based on the new inputs. -if(_Boost_CHANGE_INCDIR AND NOT _Boost_INCLUDE_DIR_CHANGED) - unset(Boost_INCLUDE_DIR CACHE) -endif() - -if(NOT Boost_INCLUDE_DIR) - set(_boost_INCLUDE_SEARCH_DIRS "") - if(BOOST_INCLUDEDIR) - list(APPEND _boost_INCLUDE_SEARCH_DIRS ${BOOST_INCLUDEDIR}) - elseif(_ENV_BOOST_INCLUDEDIR) - list(APPEND _boost_INCLUDE_SEARCH_DIRS ${_ENV_BOOST_INCLUDEDIR}) - endif() - - if( BOOST_ROOT ) - list(APPEND _boost_INCLUDE_SEARCH_DIRS ${BOOST_ROOT}/include ${BOOST_ROOT}) - elseif( _ENV_BOOST_ROOT ) - list(APPEND _boost_INCLUDE_SEARCH_DIRS ${_ENV_BOOST_ROOT}/include ${_ENV_BOOST_ROOT}) - endif() - - if( Boost_NO_SYSTEM_PATHS) - list(APPEND _boost_INCLUDE_SEARCH_DIRS NO_CMAKE_SYSTEM_PATH NO_SYSTEM_ENVIRONMENT_PATH) - else() - if("x${CMAKE_CXX_COMPILER_ID}" STREQUAL "xMSVC") - foreach(ver ${_boost_TEST_VERSIONS}) - string(REPLACE "." "_" ver "${ver}") - list(APPEND _boost_INCLUDE_SEARCH_DIRS PATHS "C:/local/boost_${ver}") - endforeach() - endif() - list(APPEND _boost_INCLUDE_SEARCH_DIRS PATHS - C:/boost/include - C:/boost - /sw/local/include - ) - endif() - - # Try to find Boost by stepping backwards through the Boost versions - # we know about. - # Build a list of path suffixes for each version. - set(_boost_PATH_SUFFIXES) - foreach(_boost_VER ${_boost_TEST_VERSIONS}) - # Add in a path suffix, based on the required version, ideally - # we could read this from version.hpp, but for that to work we'd - # need to know the include dir already - set(_boost_BOOSTIFIED_VERSION) - - # Transform 1.35 => 1_35 and 1.36.0 => 1_36_0 - if(_boost_VER MATCHES "([0-9]+)\\.([0-9]+)\\.([0-9]+)") - set(_boost_BOOSTIFIED_VERSION - "${CMAKE_MATCH_1}_${CMAKE_MATCH_2}_${CMAKE_MATCH_3}") - elseif(_boost_VER MATCHES "([0-9]+)\\.([0-9]+)") - set(_boost_BOOSTIFIED_VERSION - "${CMAKE_MATCH_1}_${CMAKE_MATCH_2}") - endif() - - list(APPEND _boost_PATH_SUFFIXES - "boost-${_boost_BOOSTIFIED_VERSION}" - "boost_${_boost_BOOSTIFIED_VERSION}" - "boost/boost-${_boost_BOOSTIFIED_VERSION}" - "boost/boost_${_boost_BOOSTIFIED_VERSION}" - ) - - endforeach() - - if(Boost_DEBUG) - message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " - "Include debugging info:") - message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " - " _boost_INCLUDE_SEARCH_DIRS = ${_boost_INCLUDE_SEARCH_DIRS}") - message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " - " _boost_PATH_SUFFIXES = ${_boost_PATH_SUFFIXES}") - endif() - - # Look for a standard boost header file. - find_path(Boost_INCLUDE_DIR - NAMES boost/config.hpp - HINTS ${_boost_INCLUDE_SEARCH_DIRS} - PATH_SUFFIXES ${_boost_PATH_SUFFIXES} - ) -endif() - -# ------------------------------------------------------------------------ -# Extract version information from version.hpp -# ------------------------------------------------------------------------ - -# Set Boost_FOUND based only on header location and version. -# It will be updated below for component libraries. -if(Boost_INCLUDE_DIR) - if(Boost_DEBUG) - message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " - "location of version.hpp: ${Boost_INCLUDE_DIR}/boost/version.hpp") - endif() - - # Extract Boost_VERSION and Boost_LIB_VERSION from version.hpp - set(Boost_VERSION 0) - set(Boost_LIB_VERSION "") - file(STRINGS "${Boost_INCLUDE_DIR}/boost/version.hpp" _boost_VERSION_HPP_CONTENTS REGEX "#define BOOST_(LIB_)?VERSION ") - set(_Boost_VERSION_REGEX "([0-9]+)") - set(_Boost_LIB_VERSION_REGEX "\"([0-9_]+)\"") - foreach(v VERSION LIB_VERSION) - if("${_boost_VERSION_HPP_CONTENTS}" MATCHES "#define BOOST_${v} ${_Boost_${v}_REGEX}") - set(Boost_${v} "${CMAKE_MATCH_1}") - endif() - endforeach() - unset(_boost_VERSION_HPP_CONTENTS) - - math(EXPR Boost_MAJOR_VERSION "${Boost_VERSION} / 100000") - math(EXPR Boost_MINOR_VERSION "${Boost_VERSION} / 100 % 1000") - math(EXPR Boost_SUBMINOR_VERSION "${Boost_VERSION} % 100") - set(Boost_VERSION_STRING "${Boost_MAJOR_VERSION}.${Boost_MINOR_VERSION}.${Boost_SUBMINOR_VERSION}") - - string(APPEND Boost_ERROR_REASON - "Boost version: ${Boost_MAJOR_VERSION}.${Boost_MINOR_VERSION}.${Boost_SUBMINOR_VERSION}\nBoost include path: ${Boost_INCLUDE_DIR}") - if(Boost_DEBUG) - message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " - "version.hpp reveals boost " - "${Boost_MAJOR_VERSION}.${Boost_MINOR_VERSION}.${Boost_SUBMINOR_VERSION}") - endif() - - if(Boost_FIND_VERSION) - # Set Boost_FOUND based on requested version. - set(_Boost_VERSION "${Boost_MAJOR_VERSION}.${Boost_MINOR_VERSION}.${Boost_SUBMINOR_VERSION}") - if("${_Boost_VERSION}" VERSION_LESS "${Boost_FIND_VERSION}") - set(Boost_FOUND 0) - set(_Boost_VERSION_AGE "old") - elseif(Boost_FIND_VERSION_EXACT AND - NOT "${_Boost_VERSION}" VERSION_EQUAL "${Boost_FIND_VERSION}") - set(Boost_FOUND 0) - set(_Boost_VERSION_AGE "new") - else() - set(Boost_FOUND 1) - endif() - if(NOT Boost_FOUND) - # State that we found a version of Boost that is too new or too old. - string(APPEND Boost_ERROR_REASON - "\nDetected version of Boost is too ${_Boost_VERSION_AGE}. Requested version was ${Boost_FIND_VERSION_MAJOR}.${Boost_FIND_VERSION_MINOR}") - if (Boost_FIND_VERSION_PATCH) - string(APPEND Boost_ERROR_REASON - ".${Boost_FIND_VERSION_PATCH}") - endif () - if (NOT Boost_FIND_VERSION_EXACT) - string(APPEND Boost_ERROR_REASON " (or newer)") - endif () - string(APPEND Boost_ERROR_REASON ".") - endif () - else() - # Caller will accept any Boost version. - set(Boost_FOUND 1) - endif() -else() - set(Boost_FOUND 0) - string(APPEND Boost_ERROR_REASON - "Unable to find the Boost header files. Please set BOOST_ROOT to the root directory containing Boost or BOOST_INCLUDEDIR to the directory containing Boost's headers.") -endif() - -# ------------------------------------------------------------------------ -# Prefix initialization -# ------------------------------------------------------------------------ - -set(Boost_LIB_PREFIX "") -if ( (GHSMULTI AND Boost_USE_STATIC_LIBS) OR - (WIN32 AND Boost_USE_STATIC_LIBS AND NOT CYGWIN) ) - set(Boost_LIB_PREFIX "lib") -endif() - -if ( NOT Boost_NAMESPACE ) - set(Boost_NAMESPACE "boost") -endif() - -if(Boost_DEBUG) - message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " - "Boost_LIB_PREFIX = ${Boost_LIB_PREFIX}") - message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " - "Boost_NAMESPACE = ${Boost_NAMESPACE}") -endif() - -# ------------------------------------------------------------------------ -# Suffix initialization and compiler suffix detection. -# ------------------------------------------------------------------------ - -set(_Boost_VARS_NAME - Boost_NAMESPACE - Boost_COMPILER - Boost_THREADAPI - Boost_USE_DEBUG_PYTHON - Boost_USE_MULTITHREADED - Boost_USE_STATIC_LIBS - Boost_USE_STATIC_RUNTIME - Boost_USE_STLPORT - Boost_USE_STLPORT_DEPRECATED_NATIVE_IOSTREAMS - ) -_Boost_CHANGE_DETECT(_Boost_CHANGE_LIBNAME ${_Boost_VARS_NAME}) - -# Setting some more suffixes for the library -if (Boost_COMPILER) - set(_boost_COMPILER ${Boost_COMPILER}) - if(Boost_DEBUG) - message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " - "using user-specified Boost_COMPILER = ${_boost_COMPILER}") - endif() -else() - # Attempt to guess the compiler suffix - # NOTE: this is not perfect yet, if you experience any issues - # please report them and use the Boost_COMPILER variable - # to work around the problems. - _Boost_GUESS_COMPILER_PREFIX(_boost_COMPILER) - if(Boost_DEBUG) - message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " - "guessed _boost_COMPILER = ${_boost_COMPILER}") - endif() -endif() - -set (_boost_MULTITHREADED "-mt") -if( NOT Boost_USE_MULTITHREADED ) - set (_boost_MULTITHREADED "") -endif() -if(Boost_DEBUG) - message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " - "_boost_MULTITHREADED = ${_boost_MULTITHREADED}") -endif() - -#====================== -# Systematically build up the Boost ABI tag for the 'tagged' and 'versioned' layouts -# http://boost.org/doc/libs/1_66_0/more/getting_started/windows.html#library-naming -# http://boost.org/doc/libs/1_66_0/boost/config/auto_link.hpp -# http://boost.org/doc/libs/1_66_0/tools/build/src/tools/common.jam -# http://boost.org/doc/libs/1_66_0/boostcpp.jam -set( _boost_RELEASE_ABI_TAG "-") -set( _boost_DEBUG_ABI_TAG "-") -# Key Use this library when: -# s linking statically to the C++ standard library and -# compiler runtime support libraries. -if(Boost_USE_STATIC_RUNTIME) - set( _boost_RELEASE_ABI_TAG "${_boost_RELEASE_ABI_TAG}s") - set( _boost_DEBUG_ABI_TAG "${_boost_DEBUG_ABI_TAG}s") -endif() -# g using debug versions of the standard and runtime -# support libraries -if(WIN32 AND Boost_USE_DEBUG_RUNTIME) - if("x${CMAKE_CXX_COMPILER_ID}" STREQUAL "xMSVC" - OR "x${CMAKE_CXX_COMPILER_ID}" STREQUAL "xClang" - OR "x${CMAKE_CXX_COMPILER_ID}" STREQUAL "xIntel") - string(APPEND _boost_DEBUG_ABI_TAG "g") - endif() -endif() -# y using special debug build of python -if(Boost_USE_DEBUG_PYTHON) - string(APPEND _boost_DEBUG_ABI_TAG "y") -endif() -# d using a debug version of your code -string(APPEND _boost_DEBUG_ABI_TAG "d") -# p using the STLport standard library rather than the -# default one supplied with your compiler -if(Boost_USE_STLPORT) - string(APPEND _boost_RELEASE_ABI_TAG "p") - string(APPEND _boost_DEBUG_ABI_TAG "p") -endif() -# n using the STLport deprecated "native iostreams" feature -# removed from the documentation in 1.43.0 but still present in -# boost/config/auto_link.hpp -if(Boost_USE_STLPORT_DEPRECATED_NATIVE_IOSTREAMS) - string(APPEND _boost_RELEASE_ABI_TAG "n") - string(APPEND _boost_DEBUG_ABI_TAG "n") -endif() - -# -x86 Architecture and address model tag -# First character is the architecture, then word-size, either 32 or 64 -# Only used in 'versioned' layout, added in Boost 1.66.0 -if(DEFINED Boost_ARCHITECTURE) - set(_boost_ARCHITECTURE_TAG "${Boost_ARCHITECTURE}") - if(Boost_DEBUG) - message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " - "using user-specified Boost_ARCHITECTURE = ${_boost_ARCHITECTURE_TAG}") - endif() -else() - set(_boost_ARCHITECTURE_TAG "") - # {CMAKE_CXX_COMPILER_ARCHITECTURE_ID} is not currently set for all compilers - if(NOT "x${CMAKE_CXX_COMPILER_ARCHITECTURE_ID}" STREQUAL "x" AND NOT Boost_VERSION VERSION_LESS 106600) - string(APPEND _boost_ARCHITECTURE_TAG "-") - # This needs to be kept in-sync with the section of CMakePlatformId.h.in - # inside 'defined(_WIN32) && defined(_MSC_VER)' - if(CMAKE_CXX_COMPILER_ARCHITECTURE_ID STREQUAL "IA64") - string(APPEND _boost_ARCHITECTURE_TAG "i") - elseif(CMAKE_CXX_COMPILER_ARCHITECTURE_ID STREQUAL "X86" - OR CMAKE_CXX_COMPILER_ARCHITECTURE_ID STREQUAL "x64") - string(APPEND _boost_ARCHITECTURE_TAG "x") - elseif(CMAKE_CXX_COMPILER_ARCHITECTURE_ID MATCHES "^ARM") - string(APPEND _boost_ARCHITECTURE_TAG "a") - elseif(CMAKE_CXX_COMPILER_ARCHITECTURE_ID STREQUAL "MIPS") - string(APPEND _boost_ARCHITECTURE_TAG "m") - endif() - - if(CMAKE_SIZEOF_VOID_P EQUAL 8) - string(APPEND _boost_ARCHITECTURE_TAG "64") - else() - string(APPEND _boost_ARCHITECTURE_TAG "32") - endif() - endif() -endif() - -if(Boost_DEBUG) - message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " - "_boost_RELEASE_ABI_TAG = ${_boost_RELEASE_ABI_TAG}") - message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " - "_boost_DEBUG_ABI_TAG = ${_boost_DEBUG_ABI_TAG}") -endif() - -# ------------------------------------------------------------------------ -# Begin finding boost libraries -# ------------------------------------------------------------------------ - -set(_Boost_VARS_LIB "") -foreach(c DEBUG RELEASE) - set(_Boost_VARS_LIB_${c} BOOST_LIBRARYDIR Boost_LIBRARY_DIR_${c}) - list(APPEND _Boost_VARS_LIB ${_Boost_VARS_LIB_${c}}) - _Boost_CHANGE_DETECT(_Boost_CHANGE_LIBDIR_${c} ${_Boost_VARS_DIR} ${_Boost_VARS_LIB_${c}} Boost_INCLUDE_DIR) - # Clear Boost_LIBRARY_DIR_${c} if it did not change but other input affecting the - # location did. We will find a new one based on the new inputs. - if(_Boost_CHANGE_LIBDIR_${c} AND NOT _Boost_LIBRARY_DIR_${c}_CHANGED) - unset(Boost_LIBRARY_DIR_${c} CACHE) - endif() - - # If Boost_LIBRARY_DIR_[RELEASE,DEBUG] is set, prefer its value. - if(Boost_LIBRARY_DIR_${c}) - set(_boost_LIBRARY_SEARCH_DIRS_${c} ${Boost_LIBRARY_DIR_${c}} NO_DEFAULT_PATH NO_CMAKE_FIND_ROOT_PATH) - else() - set(_boost_LIBRARY_SEARCH_DIRS_${c} "") - if(BOOST_LIBRARYDIR) - list(APPEND _boost_LIBRARY_SEARCH_DIRS_${c} ${BOOST_LIBRARYDIR}) - elseif(_ENV_BOOST_LIBRARYDIR) - list(APPEND _boost_LIBRARY_SEARCH_DIRS_${c} ${_ENV_BOOST_LIBRARYDIR}) - endif() - - if(BOOST_ROOT) - list(APPEND _boost_LIBRARY_SEARCH_DIRS_${c} ${BOOST_ROOT}/lib ${BOOST_ROOT}/stage/lib) - _Boost_UPDATE_WINDOWS_LIBRARY_SEARCH_DIRS_WITH_PREBUILT_PATHS(_boost_LIBRARY_SEARCH_DIRS_${c} "${BOOST_ROOT}") - elseif(_ENV_BOOST_ROOT) - list(APPEND _boost_LIBRARY_SEARCH_DIRS_${c} ${_ENV_BOOST_ROOT}/lib ${_ENV_BOOST_ROOT}/stage/lib) - _Boost_UPDATE_WINDOWS_LIBRARY_SEARCH_DIRS_WITH_PREBUILT_PATHS(_boost_LIBRARY_SEARCH_DIRS_${c} "${_ENV_BOOST_ROOT}") - endif() - - list(APPEND _boost_LIBRARY_SEARCH_DIRS_${c} - ${Boost_INCLUDE_DIR}/lib - ${Boost_INCLUDE_DIR}/../lib - ${Boost_INCLUDE_DIR}/stage/lib - ) - _Boost_UPDATE_WINDOWS_LIBRARY_SEARCH_DIRS_WITH_PREBUILT_PATHS(_boost_LIBRARY_SEARCH_DIRS_${c} "${Boost_INCLUDE_DIR}/..") - _Boost_UPDATE_WINDOWS_LIBRARY_SEARCH_DIRS_WITH_PREBUILT_PATHS(_boost_LIBRARY_SEARCH_DIRS_${c} "${Boost_INCLUDE_DIR}") - if( Boost_NO_SYSTEM_PATHS ) - list(APPEND _boost_LIBRARY_SEARCH_DIRS_${c} NO_CMAKE_SYSTEM_PATH NO_SYSTEM_ENVIRONMENT_PATH) - else() - foreach(ver ${_boost_TEST_VERSIONS}) - string(REPLACE "." "_" ver "${ver}") - _Boost_UPDATE_WINDOWS_LIBRARY_SEARCH_DIRS_WITH_PREBUILT_PATHS(_boost_LIBRARY_SEARCH_DIRS_${c} "C:/local/boost_${ver}") - endforeach() - _Boost_UPDATE_WINDOWS_LIBRARY_SEARCH_DIRS_WITH_PREBUILT_PATHS(_boost_LIBRARY_SEARCH_DIRS_${c} "C:/boost") - list(APPEND _boost_LIBRARY_SEARCH_DIRS_${c} PATHS - C:/boost/lib - C:/boost - /sw/local/lib - ) - endif() - endif() -endforeach() - -if(Boost_DEBUG) - message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " - "_boost_LIBRARY_SEARCH_DIRS_RELEASE = ${_boost_LIBRARY_SEARCH_DIRS_RELEASE}" - "_boost_LIBRARY_SEARCH_DIRS_DEBUG = ${_boost_LIBRARY_SEARCH_DIRS_DEBUG}") -endif() - -# Support preference of static libs by adjusting CMAKE_FIND_LIBRARY_SUFFIXES -if( Boost_USE_STATIC_LIBS ) - set( _boost_ORIG_CMAKE_FIND_LIBRARY_SUFFIXES ${CMAKE_FIND_LIBRARY_SUFFIXES}) - if(WIN32) - list(INSERT CMAKE_FIND_LIBRARY_SUFFIXES 0 .lib .a) - else() - set(CMAKE_FIND_LIBRARY_SUFFIXES .a) - endif() -endif() - -# We want to use the tag inline below without risking double dashes -if(_boost_RELEASE_ABI_TAG) - if(${_boost_RELEASE_ABI_TAG} STREQUAL "-") - set(_boost_RELEASE_ABI_TAG "") - endif() -endif() -if(_boost_DEBUG_ABI_TAG) - if(${_boost_DEBUG_ABI_TAG} STREQUAL "-") - set(_boost_DEBUG_ABI_TAG "") - endif() -endif() - -# The previous behavior of FindBoost when Boost_USE_STATIC_LIBS was enabled -# on WIN32 was to: -# 1. Search for static libs compiled against a SHARED C++ standard runtime library (use if found) -# 2. Search for static libs compiled against a STATIC C++ standard runtime library (use if found) -# We maintain this behavior since changing it could break people's builds. -# To disable the ambiguous behavior, the user need only -# set Boost_USE_STATIC_RUNTIME either ON or OFF. -set(_boost_STATIC_RUNTIME_WORKAROUND false) -if(WIN32 AND Boost_USE_STATIC_LIBS) - if(NOT DEFINED Boost_USE_STATIC_RUNTIME) - set(_boost_STATIC_RUNTIME_WORKAROUND TRUE) - endif() -endif() - -# On versions < 1.35, remove the System library from the considered list -# since it wasn't added until 1.35. -if(Boost_VERSION AND Boost_FIND_COMPONENTS) - if(Boost_VERSION LESS 103500) - list(REMOVE_ITEM Boost_FIND_COMPONENTS system) - endif() -endif() - -# Additional components may be required via component dependencies. -# Add any missing components to the list. -_Boost_MISSING_DEPENDENCIES(Boost_FIND_COMPONENTS _Boost_EXTRA_FIND_COMPONENTS) - -# If thread is required, get the thread libs as a dependency -if("thread" IN_LIST Boost_FIND_COMPONENTS) - if(Boost_FIND_QUIETLY) - set(_Boost_find_quiet QUIET) - else() - set(_Boost_find_quiet "") - endif() - find_package(Threads ${_Boost_find_quiet}) - unset(_Boost_find_quiet) -endif() - -# If the user changed any of our control inputs flush previous results. -if(_Boost_CHANGE_LIBDIR_DEBUG OR _Boost_CHANGE_LIBDIR_RELEASE OR _Boost_CHANGE_LIBNAME) - foreach(COMPONENT ${_Boost_COMPONENTS_SEARCHED}) - string(TOUPPER ${COMPONENT} UPPERCOMPONENT) - foreach(c DEBUG RELEASE) - set(_var Boost_${UPPERCOMPONENT}_LIBRARY_${c}) - unset(${_var} CACHE) - set(${_var} "${_var}-NOTFOUND") - endforeach() - endforeach() - set(_Boost_COMPONENTS_SEARCHED "") -endif() - -foreach(COMPONENT ${Boost_FIND_COMPONENTS}) - string(TOUPPER ${COMPONENT} UPPERCOMPONENT) - - set( _boost_docstring_release "Boost ${COMPONENT} library (release)") - set( _boost_docstring_debug "Boost ${COMPONENT} library (debug)") - - # Compute component-specific hints. - set(_Boost_FIND_LIBRARY_HINTS_FOR_COMPONENT "") - if(${COMPONENT} STREQUAL "mpi" OR ${COMPONENT} STREQUAL "mpi_python" OR - ${COMPONENT} STREQUAL "graph_parallel") - foreach(lib ${MPI_CXX_LIBRARIES} ${MPI_C_LIBRARIES}) - if(IS_ABSOLUTE "${lib}") - get_filename_component(libdir "${lib}" PATH) - string(REPLACE "\\" "/" libdir "${libdir}") - list(APPEND _Boost_FIND_LIBRARY_HINTS_FOR_COMPONENT ${libdir}) - endif() - endforeach() - endif() - - # Handle Python version suffixes - unset(COMPONENT_PYTHON_VERSION_MAJOR) - unset(COMPONENT_PYTHON_VERSION_MINOR) - if(${COMPONENT} MATCHES "^(python|mpi_python|numpy)([0-9])\$") - set(COMPONENT_UNVERSIONED "${CMAKE_MATCH_1}") - set(COMPONENT_PYTHON_VERSION_MAJOR "${CMAKE_MATCH_2}") - elseif(${COMPONENT} MATCHES "^(python|mpi_python|numpy)([0-9])\\.?([0-9])\$") - set(COMPONENT_UNVERSIONED "${CMAKE_MATCH_1}") - set(COMPONENT_PYTHON_VERSION_MAJOR "${CMAKE_MATCH_2}") - set(COMPONENT_PYTHON_VERSION_MINOR "${CMAKE_MATCH_3}") - endif() - - unset(_Boost_FIND_LIBRARY_HINTS_FOR_COMPONENT_NAME) - if (COMPONENT_PYTHON_VERSION_MINOR) - # Boost >= 1.67 - list(APPEND _Boost_FIND_LIBRARY_HINTS_FOR_COMPONENT_NAME "${COMPONENT_UNVERSIONED}${COMPONENT_PYTHON_VERSION_MAJOR}${COMPONENT_PYTHON_VERSION_MINOR}") - # Debian/Ubuntu (Some versions omit the 2 and/or 3 from the suffix) - list(APPEND _Boost_FIND_LIBRARY_HINTS_FOR_COMPONENT_NAME "${COMPONENT_UNVERSIONED}${COMPONENT_PYTHON_VERSION_MAJOR}-py${COMPONENT_PYTHON_VERSION_MAJOR}${COMPONENT_PYTHON_VERSION_MINOR}") - list(APPEND _Boost_FIND_LIBRARY_HINTS_FOR_COMPONENT_NAME "${COMPONENT_UNVERSIONED}-py${COMPONENT_PYTHON_VERSION_MAJOR}${COMPONENT_PYTHON_VERSION_MINOR}") - # Gentoo - list(APPEND _Boost_FIND_LIBRARY_HINTS_FOR_COMPONENT_NAME "${COMPONENT_UNVERSIONED}-${COMPONENT_PYTHON_VERSION_MAJOR}${COMPONENT_PYTHON_VERSION_MINOR}") - # RPMs - list(APPEND _Boost_FIND_LIBRARY_HINTS_FOR_COMPONENT_NAME "${COMPONENT_UNVERSIONED}-${COMPONENT_PYTHON_VERSION_MAJOR}${COMPONENT_PYTHON_VERSION_MINOR}") - endif() - if (COMPONENT_PYTHON_VERSION_MAJOR AND NOT COMPONENT_PYTHON_VERSION_MINOR) - # Boost < 1.67 - list(APPEND _Boost_FIND_LIBRARY_HINTS_FOR_COMPONENT_NAME "${COMPONENT_UNVERSIONED}${COMPONENT_PYTHON_VERSION_MAJOR}") - endif() - - # Consolidate and report component-specific hints. - if(_Boost_FIND_LIBRARY_HINTS_FOR_COMPONENT_NAME) - list(REMOVE_DUPLICATES _Boost_FIND_LIBRARY_HINTS_FOR_COMPONENT_NAME) - if(Boost_DEBUG) - message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " - "Component-specific library search names for ${COMPONENT_NAME}: " - "${_Boost_FIND_LIBRARY_HINTS_FOR_COMPONENT_NAME}") - endif() - endif() - if(_Boost_FIND_LIBRARY_HINTS_FOR_COMPONENT) - list(REMOVE_DUPLICATES _Boost_FIND_LIBRARY_HINTS_FOR_COMPONENT) - if(Boost_DEBUG) - message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " - "Component-specific library search paths for ${COMPONENT}: " - "${_Boost_FIND_LIBRARY_HINTS_FOR_COMPONENT}") - endif() - endif() - - # - # Find headers - # - _Boost_COMPONENT_HEADERS("${COMPONENT}" Boost_${UPPERCOMPONENT}_HEADER_NAME) - # Look for a standard boost header file. - if(Boost_${UPPERCOMPONENT}_HEADER_NAME) - if(EXISTS "${Boost_INCLUDE_DIR}/${Boost_${UPPERCOMPONENT}_HEADER_NAME}") - set(Boost_${UPPERCOMPONENT}_HEADER ON) - else() - set(Boost_${UPPERCOMPONENT}_HEADER OFF) - endif() - else() - set(Boost_${UPPERCOMPONENT}_HEADER ON) - message(WARNING "No header defined for ${COMPONENT}; skipping header check") - endif() - - # - # Find RELEASE libraries - # - unset(_boost_RELEASE_NAMES) - foreach(component IN LISTS _Boost_FIND_LIBRARY_HINTS_FOR_COMPONENT_NAME COMPONENT) - foreach(compiler IN LISTS _boost_COMPILER) - list(APPEND _boost_RELEASE_NAMES - ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${compiler}${_boost_MULTITHREADED}${_boost_RELEASE_ABI_TAG}${_boost_ARCHITECTURE_TAG}-${Boost_LIB_VERSION} - ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${compiler}${_boost_MULTITHREADED}${_boost_RELEASE_ABI_TAG}${_boost_ARCHITECTURE_TAG} - ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${compiler}${_boost_MULTITHREADED}${_boost_RELEASE_ABI_TAG} ) - endforeach() - list(APPEND _boost_RELEASE_NAMES - ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${_boost_MULTITHREADED}${_boost_RELEASE_ABI_TAG}${_boost_ARCHITECTURE_TAG}-${Boost_LIB_VERSION} - ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${_boost_MULTITHREADED}${_boost_RELEASE_ABI_TAG}${_boost_ARCHITECTURE_TAG} - ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${_boost_MULTITHREADED}${_boost_RELEASE_ABI_TAG} - ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${_boost_MULTITHREADED} - ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component} ) - if(_boost_STATIC_RUNTIME_WORKAROUND) - set(_boost_RELEASE_STATIC_ABI_TAG "-s${_boost_RELEASE_ABI_TAG}") - foreach(compiler IN LISTS _boost_COMPILER) - list(APPEND _boost_RELEASE_NAMES - ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${compiler}${_boost_MULTITHREADED}${_boost_RELEASE_STATIC_ABI_TAG}${_boost_ARCHITECTURE_TAG}-${Boost_LIB_VERSION} - ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${compiler}${_boost_MULTITHREADED}${_boost_RELEASE_STATIC_ABI_TAG}${_boost_ARCHITECTURE_TAG} - ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${compiler}${_boost_MULTITHREADED}${_boost_RELEASE_STATIC_ABI_TAG} ) - endforeach() - list(APPEND _boost_RELEASE_NAMES - ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${_boost_MULTITHREADED}${_boost_RELEASE_STATIC_ABI_TAG}${_boost_ARCHITECTURE_TAG}-${Boost_LIB_VERSION} - ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${_boost_MULTITHREADED}${_boost_RELEASE_STATIC_ABI_TAG}${_boost_ARCHITECTURE_TAG} - ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${_boost_MULTITHREADED}${_boost_RELEASE_STATIC_ABI_TAG} ) - endif() - endforeach() - if(Boost_THREADAPI AND ${COMPONENT} STREQUAL "thread") - _Boost_PREPEND_LIST_WITH_THREADAPI(_boost_RELEASE_NAMES ${_boost_RELEASE_NAMES}) - endif() - if(Boost_DEBUG) - message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " - "Searching for ${UPPERCOMPONENT}_LIBRARY_RELEASE: ${_boost_RELEASE_NAMES}") - endif() - - # if Boost_LIBRARY_DIR_RELEASE is not defined, - # but Boost_LIBRARY_DIR_DEBUG is, look there first for RELEASE libs - if(NOT Boost_LIBRARY_DIR_RELEASE AND Boost_LIBRARY_DIR_DEBUG) - list(INSERT _boost_LIBRARY_SEARCH_DIRS_RELEASE 0 ${Boost_LIBRARY_DIR_DEBUG}) - endif() - - # Avoid passing backslashes to _Boost_FIND_LIBRARY due to macro re-parsing. - string(REPLACE "\\" "/" _boost_LIBRARY_SEARCH_DIRS_tmp "${_boost_LIBRARY_SEARCH_DIRS_RELEASE}") - - if(Boost_USE_RELEASE_LIBS) - _Boost_FIND_LIBRARY(Boost_${UPPERCOMPONENT}_LIBRARY_RELEASE RELEASE - NAMES ${_boost_RELEASE_NAMES} - HINTS ${_boost_LIBRARY_SEARCH_DIRS_tmp} - NAMES_PER_DIR - DOC "${_boost_docstring_release}" - ) - endif() - - # - # Find DEBUG libraries - # - unset(_boost_DEBUG_NAMES) - foreach(component IN LISTS _Boost_FIND_LIBRARY_HINTS_FOR_COMPONENT_NAME COMPONENT) - foreach(compiler IN LISTS _boost_COMPILER) - list(APPEND _boost_DEBUG_NAMES - ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${compiler}${_boost_MULTITHREADED}${_boost_DEBUG_ABI_TAG}${_boost_ARCHITECTURE_TAG}-${Boost_LIB_VERSION} - ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${compiler}${_boost_MULTITHREADED}${_boost_DEBUG_ABI_TAG}${_boost_ARCHITECTURE_TAG} - ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${compiler}${_boost_MULTITHREADED}${_boost_DEBUG_ABI_TAG} ) - endforeach() - list(APPEND _boost_DEBUG_NAMES - ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${_boost_MULTITHREADED}${_boost_DEBUG_ABI_TAG}${_boost_ARCHITECTURE_TAG}-${Boost_LIB_VERSION} - ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${_boost_MULTITHREADED}${_boost_DEBUG_ABI_TAG}${_boost_ARCHITECTURE_TAG} - ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${_boost_MULTITHREADED}${_boost_DEBUG_ABI_TAG} - ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${_boost_MULTITHREADED} - ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component} ) - if(_boost_STATIC_RUNTIME_WORKAROUND) - set(_boost_DEBUG_STATIC_ABI_TAG "-s${_boost_DEBUG_ABI_TAG}") - foreach(compiler IN LISTS _boost_COMPILER) - list(APPEND _boost_DEBUG_NAMES - ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${compiler}${_boost_MULTITHREADED}${_boost_DEBUG_STATIC_ABI_TAG}${_boost_ARCHITECTURE_TAG}-${Boost_LIB_VERSION} - ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${compiler}${_boost_MULTITHREADED}${_boost_DEBUG_STATIC_ABI_TAG}${_boost_ARCHITECTURE_TAG} - ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${compiler}${_boost_MULTITHREADED}${_boost_DEBUG_STATIC_ABI_TAG} ) - endforeach() - list(APPEND _boost_DEBUG_NAMES - ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${_boost_MULTITHREADED}${_boost_DEBUG_STATIC_ABI_TAG}${_boost_ARCHITECTURE_TAG}-${Boost_LIB_VERSION} - ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${_boost_MULTITHREADED}${_boost_DEBUG_STATIC_ABI_TAG}${_boost_ARCHITECTURE_TAG} - ${Boost_LIB_PREFIX}${Boost_NAMESPACE}_${component}${_boost_MULTITHREADED}${_boost_DEBUG_STATIC_ABI_TAG} ) - endif() - endforeach() - if(Boost_THREADAPI AND ${COMPONENT} STREQUAL "thread") - _Boost_PREPEND_LIST_WITH_THREADAPI(_boost_DEBUG_NAMES ${_boost_DEBUG_NAMES}) - endif() - if(Boost_DEBUG) - message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] " - "Searching for ${UPPERCOMPONENT}_LIBRARY_DEBUG: ${_boost_DEBUG_NAMES}") - endif() - - # if Boost_LIBRARY_DIR_DEBUG is not defined, - # but Boost_LIBRARY_DIR_RELEASE is, look there first for DEBUG libs - if(NOT Boost_LIBRARY_DIR_DEBUG AND Boost_LIBRARY_DIR_RELEASE) - list(INSERT _boost_LIBRARY_SEARCH_DIRS_DEBUG 0 ${Boost_LIBRARY_DIR_RELEASE}) - endif() - - # Avoid passing backslashes to _Boost_FIND_LIBRARY due to macro re-parsing. - string(REPLACE "\\" "/" _boost_LIBRARY_SEARCH_DIRS_tmp "${_boost_LIBRARY_SEARCH_DIRS_DEBUG}") - - if(Boost_USE_DEBUG_LIBS) - _Boost_FIND_LIBRARY(Boost_${UPPERCOMPONENT}_LIBRARY_DEBUG DEBUG - NAMES ${_boost_DEBUG_NAMES} - HINTS ${_boost_LIBRARY_SEARCH_DIRS_tmp} - NAMES_PER_DIR - DOC "${_boost_docstring_debug}" - ) - endif () - - if(Boost_REALPATH) - _Boost_SWAP_WITH_REALPATH(Boost_${UPPERCOMPONENT}_LIBRARY_RELEASE "${_boost_docstring_release}") - _Boost_SWAP_WITH_REALPATH(Boost_${UPPERCOMPONENT}_LIBRARY_DEBUG "${_boost_docstring_debug}" ) - endif() - - _Boost_ADJUST_LIB_VARS(${UPPERCOMPONENT}) - - # Check if component requires some compiler features - _Boost_COMPILER_FEATURES(${COMPONENT} _Boost_${UPPERCOMPONENT}_COMPILER_FEATURES) - -endforeach() - -# Restore the original find library ordering -if( Boost_USE_STATIC_LIBS ) - set(CMAKE_FIND_LIBRARY_SUFFIXES ${_boost_ORIG_CMAKE_FIND_LIBRARY_SUFFIXES}) -endif() - -# ------------------------------------------------------------------------ -# End finding boost libraries -# ------------------------------------------------------------------------ - -set(Boost_INCLUDE_DIRS ${Boost_INCLUDE_DIR}) -set(Boost_LIBRARY_DIRS) -if(Boost_LIBRARY_DIR_RELEASE) - list(APPEND Boost_LIBRARY_DIRS ${Boost_LIBRARY_DIR_RELEASE}) -endif() -if(Boost_LIBRARY_DIR_DEBUG) - list(APPEND Boost_LIBRARY_DIRS ${Boost_LIBRARY_DIR_DEBUG}) -endif() -if(Boost_LIBRARY_DIRS) - list(REMOVE_DUPLICATES Boost_LIBRARY_DIRS) -endif() - -# The above setting of Boost_FOUND was based only on the header files. -# Update it for the requested component libraries. -if(Boost_FOUND) - # The headers were found. Check for requested component libs. - set(_boost_CHECKED_COMPONENT FALSE) - set(_Boost_MISSING_COMPONENTS "") - foreach(COMPONENT ${Boost_FIND_COMPONENTS}) - string(TOUPPER ${COMPONENT} UPPERCOMPONENT) - set(_boost_CHECKED_COMPONENT TRUE) - if(NOT Boost_${UPPERCOMPONENT}_FOUND AND Boost_FIND_REQUIRED_${COMPONENT}) - list(APPEND _Boost_MISSING_COMPONENTS ${COMPONENT}) - endif() - endforeach() - if(_Boost_MISSING_COMPONENTS AND _Boost_EXTRA_FIND_COMPONENTS) - # Optional indirect dependencies are not counted as missing. - list(REMOVE_ITEM _Boost_MISSING_COMPONENTS ${_Boost_EXTRA_FIND_COMPONENTS}) - endif() - - if(Boost_DEBUG) - message(STATUS "[ ${CMAKE_CURRENT_LIST_FILE}:${CMAKE_CURRENT_LIST_LINE} ] Boost_FOUND = ${Boost_FOUND}") - endif() - - if (_Boost_MISSING_COMPONENTS) - set(Boost_FOUND 0) - # We were unable to find some libraries, so generate a sensible - # error message that lists the libraries we were unable to find. - string(APPEND Boost_ERROR_REASON - "\nCould not find the following") - if(Boost_USE_STATIC_LIBS) - string(APPEND Boost_ERROR_REASON " static") - endif() - string(APPEND Boost_ERROR_REASON - " Boost libraries:\n") - foreach(COMPONENT ${_Boost_MISSING_COMPONENTS}) - string(TOUPPER ${COMPONENT} UPPERCOMPONENT) - string(APPEND Boost_ERROR_REASON - " ${Boost_NAMESPACE}_${COMPONENT}${Boost_ERROR_REASON_${UPPERCOMPONENT}}\n") - endforeach() - - list(LENGTH Boost_FIND_COMPONENTS Boost_NUM_COMPONENTS_WANTED) - list(LENGTH _Boost_MISSING_COMPONENTS Boost_NUM_MISSING_COMPONENTS) - if (${Boost_NUM_COMPONENTS_WANTED} EQUAL ${Boost_NUM_MISSING_COMPONENTS}) - string(APPEND Boost_ERROR_REASON - "No Boost libraries were found. You may need to set BOOST_LIBRARYDIR to the directory containing Boost libraries or BOOST_ROOT to the location of Boost.") - else () - string(APPEND Boost_ERROR_REASON - "Some (but not all) of the required Boost libraries were found. You may need to install these additional Boost libraries. Alternatively, set BOOST_LIBRARYDIR to the directory containing Boost libraries or BOOST_ROOT to the location of Boost.") - endif () - endif () - - if( NOT Boost_LIBRARY_DIRS AND NOT _boost_CHECKED_COMPONENT ) - # Compatibility Code for backwards compatibility with CMake - # 2.4's FindBoost module. - - # Look for the boost library path. - # Note that the user may not have installed any libraries - # so it is quite possible the Boost_LIBRARY_DIRS may not exist. - set(_boost_LIB_DIR ${Boost_INCLUDE_DIR}) - - if("${_boost_LIB_DIR}" MATCHES "boost-[0-9]+") - get_filename_component(_boost_LIB_DIR ${_boost_LIB_DIR} PATH) - endif() - - if("${_boost_LIB_DIR}" MATCHES "/include$") - # Strip off the trailing "/include" in the path. - get_filename_component(_boost_LIB_DIR ${_boost_LIB_DIR} PATH) - endif() - - if(EXISTS "${_boost_LIB_DIR}/lib") - string(APPEND _boost_LIB_DIR /lib) - elseif(EXISTS "${_boost_LIB_DIR}/stage/lib") - string(APPEND _boost_LIB_DIR "/stage/lib") - else() - set(_boost_LIB_DIR "") - endif() - - if(_boost_LIB_DIR AND EXISTS "${_boost_LIB_DIR}") - set(Boost_LIBRARY_DIRS ${_boost_LIB_DIR}) - endif() - - endif() -else() - # Boost headers were not found so no components were found. - foreach(COMPONENT ${Boost_FIND_COMPONENTS}) - string(TOUPPER ${COMPONENT} UPPERCOMPONENT) - set(Boost_${UPPERCOMPONENT}_FOUND 0) - endforeach() -endif() - -# ------------------------------------------------------------------------ -# Add imported targets -# ------------------------------------------------------------------------ - -if(Boost_FOUND) - # For header-only libraries - if(NOT TARGET Boost::boost) - add_library(Boost::boost INTERFACE IMPORTED) - if(Boost_INCLUDE_DIRS) - set_target_properties(Boost::boost PROPERTIES - INTERFACE_INCLUDE_DIRECTORIES "${Boost_INCLUDE_DIRS}") - endif() - endif() - - foreach(COMPONENT ${Boost_FIND_COMPONENTS}) - if(_Boost_IMPORTED_TARGETS AND NOT TARGET Boost::${COMPONENT}) - string(TOUPPER ${COMPONENT} UPPERCOMPONENT) - if(Boost_${UPPERCOMPONENT}_FOUND) - if(Boost_USE_STATIC_LIBS) - add_library(Boost::${COMPONENT} STATIC IMPORTED) - else() - # Even if Boost_USE_STATIC_LIBS is OFF, we might have static - # libraries as a result. - add_library(Boost::${COMPONENT} UNKNOWN IMPORTED) - endif() - if(Boost_INCLUDE_DIRS) - set_target_properties(Boost::${COMPONENT} PROPERTIES - INTERFACE_INCLUDE_DIRECTORIES "${Boost_INCLUDE_DIRS}") - endif() - if(EXISTS "${Boost_${UPPERCOMPONENT}_LIBRARY}") - set_target_properties(Boost::${COMPONENT} PROPERTIES - IMPORTED_LINK_INTERFACE_LANGUAGES "CXX" - IMPORTED_LOCATION "${Boost_${UPPERCOMPONENT}_LIBRARY}") - endif() - if(EXISTS "${Boost_${UPPERCOMPONENT}_LIBRARY_RELEASE}") - set_property(TARGET Boost::${COMPONENT} APPEND PROPERTY - IMPORTED_CONFIGURATIONS RELEASE) - set_target_properties(Boost::${COMPONENT} PROPERTIES - IMPORTED_LINK_INTERFACE_LANGUAGES_RELEASE "CXX" - IMPORTED_LOCATION_RELEASE "${Boost_${UPPERCOMPONENT}_LIBRARY_RELEASE}") - endif() - if(EXISTS "${Boost_${UPPERCOMPONENT}_LIBRARY_DEBUG}") - set_property(TARGET Boost::${COMPONENT} APPEND PROPERTY - IMPORTED_CONFIGURATIONS DEBUG) - set_target_properties(Boost::${COMPONENT} PROPERTIES - IMPORTED_LINK_INTERFACE_LANGUAGES_DEBUG "CXX" - IMPORTED_LOCATION_DEBUG "${Boost_${UPPERCOMPONENT}_LIBRARY_DEBUG}") - endif() - if(_Boost_${UPPERCOMPONENT}_DEPENDENCIES) - unset(_Boost_${UPPERCOMPONENT}_TARGET_DEPENDENCIES) - foreach(dep ${_Boost_${UPPERCOMPONENT}_DEPENDENCIES}) - list(APPEND _Boost_${UPPERCOMPONENT}_TARGET_DEPENDENCIES Boost::${dep}) - endforeach() - if(COMPONENT STREQUAL "thread") - list(APPEND _Boost_${UPPERCOMPONENT}_TARGET_DEPENDENCIES Threads::Threads) - endif() - set_target_properties(Boost::${COMPONENT} PROPERTIES - INTERFACE_LINK_LIBRARIES "${_Boost_${UPPERCOMPONENT}_TARGET_DEPENDENCIES}") - endif() - if(_Boost_${UPPERCOMPONENT}_COMPILER_FEATURES) - set_target_properties(Boost::${COMPONENT} PROPERTIES - INTERFACE_COMPILE_FEATURES "${_Boost_${UPPERCOMPONENT}_COMPILER_FEATURES}") - endif() - endif() - endif() - endforeach() -endif() - -# ------------------------------------------------------------------------ -# Notification to end user about what was found -# ------------------------------------------------------------------------ - -set(Boost_LIBRARIES "") -if(Boost_FOUND) - if(NOT Boost_FIND_QUIETLY) - message(STATUS "Boost version: ${Boost_MAJOR_VERSION}.${Boost_MINOR_VERSION}.${Boost_SUBMINOR_VERSION}") - if(Boost_FIND_COMPONENTS) - message(STATUS "Found the following Boost libraries:") - endif() - endif() - foreach( COMPONENT ${Boost_FIND_COMPONENTS} ) - string( TOUPPER ${COMPONENT} UPPERCOMPONENT ) - if( Boost_${UPPERCOMPONENT}_FOUND ) - if(NOT Boost_FIND_QUIETLY) - message (STATUS " ${COMPONENT}") - endif() - list(APPEND Boost_LIBRARIES ${Boost_${UPPERCOMPONENT}_LIBRARY}) - if(COMPONENT STREQUAL "thread") - list(APPEND Boost_LIBRARIES ${CMAKE_THREAD_LIBS_INIT}) - endif() - endif() - endforeach() -else() - if(Boost_FIND_REQUIRED) - message(SEND_ERROR "Unable to find the requested Boost libraries.\n${Boost_ERROR_REASON}") - else() - if(NOT Boost_FIND_QUIETLY) - # we opt not to automatically output Boost_ERROR_REASON here as - # it could be quite lengthy and somewhat imposing in its requests - # Since Boost is not always a required dependency we'll leave this - # up to the end-user. - if(Boost_DEBUG OR Boost_DETAILED_FAILURE_MSG) - message(STATUS "Could NOT find Boost\n${Boost_ERROR_REASON}") - else() - message(STATUS "Could NOT find Boost") - endif() - endif() - endif() -endif() - -# Configure display of cache entries in GUI. -foreach(v BOOSTROOT BOOST_ROOT ${_Boost_VARS_INC} ${_Boost_VARS_LIB}) - get_property(_type CACHE ${v} PROPERTY TYPE) - if(_type) - set_property(CACHE ${v} PROPERTY ADVANCED 1) - if("x${_type}" STREQUAL "xUNINITIALIZED") - if("x${v}" STREQUAL "xBoost_ADDITIONAL_VERSIONS") - set_property(CACHE ${v} PROPERTY TYPE STRING) - else() - set_property(CACHE ${v} PROPERTY TYPE PATH) - endif() - endif() - endif() -endforeach() - -# Record last used values of input variables so we can -# detect on the next run if the user changed them. -foreach(v - ${_Boost_VARS_INC} ${_Boost_VARS_LIB} - ${_Boost_VARS_DIR} ${_Boost_VARS_NAME} - ) - if(DEFINED ${v}) - set(_${v}_LAST "${${v}}" CACHE INTERNAL "Last used ${v} value.") - else() - unset(_${v}_LAST CACHE) - endif() -endforeach() - -# Maintain a persistent list of components requested anywhere since -# the last flush. -set(_Boost_COMPONENTS_SEARCHED "${_Boost_COMPONENTS_SEARCHED}") -list(APPEND _Boost_COMPONENTS_SEARCHED ${Boost_FIND_COMPONENTS}) -list(REMOVE_DUPLICATES _Boost_COMPONENTS_SEARCHED) -list(SORT _Boost_COMPONENTS_SEARCHED) -set(_Boost_COMPONENTS_SEARCHED "${_Boost_COMPONENTS_SEARCHED}" - CACHE INTERNAL "Components requested for this build tree.") - -# Restore project's policies -cmake_policy(POP) diff --git a/cmake/Modules/FindElfutils.cmake b/cmake/Modules/FindElfutils.cmake new file mode 100644 index 0000000000..cbec8d6a3b --- /dev/null +++ b/cmake/Modules/FindElfutils.cmake @@ -0,0 +1,133 @@ +#[=======================================================================[.rst: +FindElfutils +------------ + +Find elfutils, a collection of utilities and libraries to read, create +and modify ELF binary files, find and handle DWARF debug data, +symbols, thread state and stacktraces for processes and core files +on GNU/Linux. + +Variables that affect this module + +``ElfUtils_NO_SYSTEM_PATHS`` + If `True`, no system paths are searched. + +Imported targets +^^^^^^^^^^^^^^^^ + +This module defines the following :prop_tgt:`IMPORTED` target: + +``Elfutils::Elfutils`` + The elfutils library, if found. + +This module will set the following variables in your project: + +``Elfutils_INCLUDE_DIRS`` + where to find elfutils headers +``Elfutils_LIBRARIES`` + the libraries to link against to use elfutils. +``Elfutils_FOUND`` + If false, do not try to use elfutils. +``Elfutils_VERSION`` + the version of the elfutils library found + +Support for libdebuginfod can be added by specifying it in ``COMPONENTS``. + +.. code-block:: cmake + + find_package(Elfutils 0.186 EXACT REQUIRED COMPONENTS debuginfod) + +#]=======================================================================] +cmake_policy(SET CMP0074 NEW) # Use _ROOT + +if(${Elfutils_FIND_REQUIRED}) + set(_required "REQUIRED") +endif() + +if(${Elfutils_FIND_QUIETLY}) + set(_quiet "QUIET") +endif() + +if(${Elfutils_FIND_EXACT}) + set(_exact "EXACT") +endif() + +# Propagate ElfUtils_NO_SYSTEM_PATHS +foreach(_n "LibELF" "LibDW" "LibDebuginfod") + set(${_n}_NO_SYSTEM_PATHS ${ElfUtils_NO_SYSTEM_PATHS}) + mark_as_advanced(${_n}_NO_SYSTEM_PATHS) + + # Force the search directory + if(ElfUtils_NO_SYSTEM_PATHS) + set(${_n}_ROOT ${ElfUtils_ROOT_DIR}) + mark_as_advanced(${_n}_ROOT) + endif() +endforeach() + +find_package(LibELF ${Elfutils_FIND_VERSION} ${_exact} ${_required} ${_quiet}) +find_package(LibDW ${Elfutils_FIND_VERSION} ${_exact} ${_required} ${_quiet}) + +if(NOT "x${Elfutils_FIND_COMPONENTS}" STREQUAL "x") + string(TOUPPER ${Elfutils_FIND_COMPONENTS} _tmp) + if(NOT ${_tmp} STREQUAL "DEBUGINFOD") + message(FATAL "Unknown component: '${Elfutils_FIND_COMPONENTS}'") + endif() + find_package(LibDebuginfod ${Elfutils_FIND_VERSION} ${_exact} ${_required} ${_quiet}) + set(_need_debuginfod TRUE) + unset(_tmp) +endif() + +# Ensure that each component has the same version number +set(_versions ${LibDW_VERSION} ${LibELF_VERSION} ${LibDebuginfod_VERSION}) +list(REMOVE_DUPLICATES _versions) +list(LENGTH _versions _len) +if(${_len} GREATER 1) + message(FATAL_ERROR "Elfutils: conflicting versions found: (${_versions})") +endif() +unset(_len) + +set(Elfutils_VERSION ${_versions}) +unset(_versions) + +include(FindPackageHandleStandardArgs) +if(${_need_debuginfod}) + find_package_handle_standard_args( + Elfutils + FOUND_VAR Elfutils_FOUND + REQUIRED_VARS LibDW_INCLUDE_DIRS LibDW_LIBRARIES LibELF_INCLUDE_DIRS LibELF_LIBRARIES + LibDebuginfod_INCLUDE_DIRS LibDebuginfod_LIBRARIES + VERSION_VAR Elfutils_VERSION) +else() + find_package_handle_standard_args( + Elfutils + FOUND_VAR Elfutils_FOUND + REQUIRED_VARS LibDW_INCLUDE_DIRS LibDW_LIBRARIES LibELF_INCLUDE_DIRS LibELF_LIBRARIES + VERSION_VAR Elfutils_VERSION) +endif() + +if(Elfutils_FOUND) + set(Elfutils_INCLUDE_DIRS + ${LibDW_INCLUDE_DIRS} ${LibELF_INCLUDE_DIRS} ${LibDebuginfod_INCLUDE_DIRS} + CACHE PATH "") + mark_as_advanced(Elfutils_INCLUDE_DIRS) + + set(Elfutils_LIBRARIES + ${LibDW_LIBRARIES} ${LibELF_LIBRARIES} ${LibDebuginfod_LIBRARIES} + CACHE PATH "") + mark_as_advanced(Elfutils_LIBRARIES) + + mark_as_advanced(Elfutils_VERSION) + + if(NOT TARGET Elfutils::Elfutils) + add_library(Elfutils::Elfutils INTERFACE IMPORTED) + target_link_libraries(Elfutils::Elfutils INTERFACE LibELF::LibELF LibDW::LibDW) + if(${_need_debuginfod}) + target_link_libraries(Elfutils::Elfutils INTERFACE LibDebuginfod::LibDebuginfod) + endif() + endif() +endif() + +unset(_exact) +unset(_quiet) +unset(_required) +unset(_need_debuginfod) diff --git a/cmake/Modules/FindLibDW.cmake b/cmake/Modules/FindLibDW.cmake new file mode 100644 index 0000000000..26c18cc059 --- /dev/null +++ b/cmake/Modules/FindLibDW.cmake @@ -0,0 +1,140 @@ +#[=======================================================================[.rst: +FindLibDW +--------- + +Find libdw, the elfutils library for DWARF data and ELF file or process inspection. + +Variables that affect this module + +``LibDW_NO_SYSTEM_PATHS`` + If `True`, no system paths are searched. + +Imported targets +^^^^^^^^^^^^^^^^ + +This module defines the following :prop_tgt:`IMPORTED` target: + +``LibDW::LibDW`` + The libdw library, if found. + +Result variables +^^^^^^^^^^^^^^^^ + +This module will set the following variables in your project: + +``LibDW_INCLUDE_DIRS`` + where to find libdw.h, etc. +``LibDW_LIBRARIES`` + the libraries to link against to use libdw. +``LibDW_FOUND`` + If false, do not try to use libdw. +``LibDW_VERSION`` + the version of the libdw library found + +#]=======================================================================] +cmake_policy(SET CMP0074 NEW) # Use _ROOT + +if(LibDW_NO_SYSTEM_PATHS) + set(_find_path_args NO_CMAKE_SYSTEM_PATH NO_SYSTEM_ENVIRONMENT_PATH) +endif() + +# There is no way to tell pkg-config to ignore directories, so disable it +if(NOT LibDW_NO_SYSTEM_PATHS) + find_package(PkgConfig QUIET) + if(PKG_CONFIG_FOUND) + if(NOT "x${LibDW_FIND_VERSION}" STREQUAL "x") + set(_version ">=${LibDW_FIND_VERSION}") + endif() + if(LibDW_FIND_QUIETLY) + set(_quiet "QUIET") + endif() + + pkg_check_modules(PC_LIBDW ${_quiet} "libdw${_version}") + unset(_version) + unset(_quiet) + endif() +endif() + +if(PC_LIBDW_FOUND) + # FindPkgConfig sometimes gets the include dir wrong + if("x${PC_LIBDW_INCLUDE_DIRS}" STREQUAL "x") + pkg_get_variable(PC_LIBDW_INCLUDE_DIRS libdw includedir) + endif() + + set(LibDW_INCLUDE_DIRS + ${PC_LIBDW_INCLUDE_DIRS} + CACHE PATH "") + set(LibDW_LIBRARIES + ${PC_LIBDW_LINK_LIBRARIES} + CACHE PATH "") + set(LibDW_VERSION + ${PC_LIBDW_VERSION} + CACHE STRING "") +else() + find_path( + LibDW_INCLUDE_DIRS + NAMES libdw.h + PATH_SUFFIXES elfutils ${_find_path_args}) + + find_library( + LibDW_LIBRARIES + NAMES libdw dw + PATH_SUFFIXES elfutils ${_find_path_args}) + + if(EXISTS "${LibDW_INCLUDE_DIRS}/version.h") + file(STRINGS "${LibDW_INCLUDE_DIRS}/version.h" _version_line + REGEX "^#define _ELFUTILS_VERSION[ \t]+[0-9]+") + string(REGEX MATCH "[0-9]+" _version "${_version_line}") + if(NOT "x${_version}" STREQUAL "x") + set(LibDW_VERSION "0.${_version}") + endif() + unset(_version_line) + unset(_version) + endif() +endif() + +include(FindPackageHandleStandardArgs) +find_package_handle_standard_args( + LibDW + FOUND_VAR LibDW_FOUND + REQUIRED_VARS LibDW_LIBRARIES LibDW_INCLUDE_DIRS + VERSION_VAR LibDW_VERSION) + +if(LibDW_FOUND) + mark_as_advanced(LibDW_INCLUDE_DIRS) + mark_as_advanced(LibDW_LIBRARIES) + mark_as_advanced(LibDW_VERSION) + + # Some platforms explicitly list libelf as a dependency, so separate it out + list(LENGTH LibDW_LIBRARIES _cnt) + if(${_cnt} GREATER 1) + foreach(_l ${LibDW_LIBRARIES}) + if(${_l} MATCHES "libdw") + set(_libdw ${_l}) + else() + list(APPEND _link_libs ${_l}) + endif() + endforeach() + endif() + unset(_cnt) + + if(NOT TARGET LibDW::LibDW) + add_library(LibDW::LibDW UNKNOWN IMPORTED) + set_target_properties(LibDW::LibDW PROPERTIES INTERFACE_INCLUDE_DIRECTORIES + "${LibDW_INCLUDE_DIRS}") + + if(NOT "x${_link_libs}" STREQUAL "x") + set_target_properties( + LibDW::LibDW PROPERTIES IMPORTED_LINK_INTERFACE_LANGUAGES "C" + IMPORTED_LINK_DEPENDENT_LIBRARIES "${_link_libs}") + set(LibDW_LIBRARIES ${_libdw}) + unset(_libdw) + unset(_link_libs) + endif() + + set_target_properties(LibDW::LibDW PROPERTIES IMPORTED_LINK_INTERFACE_LANGUAGES "C" + IMPORTED_LOCATION "${LibDW_LIBRARIES}") + endif() +endif() + +unset(_find_path_args) diff --git a/cmake/Modules/FindLibDebuginfod.cmake b/cmake/Modules/FindLibDebuginfod.cmake index 5ab73e2db6..07487003ad 100644 --- a/cmake/Modules/FindLibDebuginfod.cmake +++ b/cmake/Modules/FindLibDebuginfod.cmake @@ -1,76 +1,118 @@ -#======================================================================================== -# FindDebuginfod -# ----------- -# -# Find debuginfod library and headers -# -# The module defines the following variables: -# -# This module reads hints about search locations from variables:: -# -# LibDebuginfod_ROOT_DIR - Base directory the of libdebuginfod installation -# LibDebuginfod_INCLUDEDIR - Hint directory that contains the libdebuginfod headers files -# LibDebuginfod_LIBRARYDIR - Hint directory that contains the libdebuginfod library files -# -# and saves search results persistently in CMake cache entries:: -# -# LibDebuginfod_FOUND - True if headers and requested libraries were found -# LibDebuginfod_INCLUDE_DIRS - libdebuginfod include directories -# LibDebuginfod_LIBRARY_DIRS - Link directories for libdebuginfod libraries -# LibDebuginfod_LIBRARIES - libdebuginfod library files -# -# Utilize package config (e.g. /usr/lib64/pkgconfig/libdebuginfod.pc) to fetch -# version information. -# -#======================================================================================== - -find_package(PkgConfig QUIET) -pkg_check_modules(PC_Debuginfod QUIET REQUIRED libdebuginfod>=${ElfUtils_MIN_VERSION}) -set(LibDebuginfod_VERSION "${PC_Debuginfod_VERSION}") - -find_path(LibDebuginfod_INCLUDE_DIRS - NAMES - debuginfod.h - HINTS - ${PC_Debuginfod_INCLUDEDIR} - ${PC_Debuginfod_INCLUDE_DIRS} - ${LibDebuginfod_ROOT_DIR}/include - ${LibDebuginfod_ROOT_DIR} - ${LibDebuginfod_INCLUDEDIR} - PATHS - ${DYNINST_SYSTEM_INCLUDE_PATHS} - PATH_SUFFIXES - ${_path_suffixes} - DOC - "libdebuginfod include directories") - -find_library(LibDebuginfod_LIBRARIES - NAMES - libdebuginfod.so.1 libdebuginfod.so - HINTS - ${PC_Debuginfod_LIBDIR} - ${PC_Debuginfod_LIBRARY_DIRS} - ${LibDebuginfod_ROOT_DIR}/lib - ${LibDebuginfod_ROOT_DIR} - ${LibDebuginfod_LIBRARYDIR} - PATHS - ${DYNINST_SYSTEM_LIBRARY_PATHS} - PATH_SUFFIXES - ${_path_suffixes}) +#[=======================================================================[.rst: +FindLibDebuginfod +----------------- + +Find libdebuginfod, the elfutils library to query debuginfo files from debuginfod servers. + +Variables that affect this module + +``LibDebuginfod_NO_SYSTEM_PATHS`` + If `True`, no system paths are searched. + +Imported targets +^^^^^^^^^^^^^^^^ + +This module defines the following :prop_tgt:`IMPORTED` target: + +``LibDebuginfod::LibDebuginfod`` + The libdebuginfod library, if found. + +Result variables +^^^^^^^^^^^^^^^^ + +This module will set the following variables in your project: + +``LibDebuginfod_INCLUDE_DIRS`` + where to find debuginfod.h, etc. +``LibDebuginfod_LIBRARIES`` + the libraries to link against to use libdebuginfod. +``LibDebuginfod_FOUND`` + If false, do not try to use libdebuginfod. +``LibDebuginfod_VERSION`` + the version of the libdebuginfod library found + +#]=======================================================================] +cmake_policy(SET CMP0074 NEW) # Use _ROOT + +if(LibDebuginfod_NO_SYSTEM_PATHS) + set(_find_path_args NO_CMAKE_SYSTEM_PATH NO_SYSTEM_ENVIRONMENT_PATH) +endif() + +# There is no way to tell pkg-config to ignore directories, so disable it +if(NOT LibDebuginfod_NO_SYSTEM_PATHS) + find_package(PkgConfig QUIET) + if(PKG_CONFIG_FOUND) + if(NOT "x${LibDebuginfod_FIND_VERSION}" STREQUAL "x") + set(_version ">=${LibDebuginfod_FIND_VERSION}") + endif() + if(LibDebuginfod_FIND_QUIETLY) + set(_quiet "QUIET") + endif() + + pkg_check_modules(PC_LIBDEBUGINFOD ${_quiet} "libdebuginfod${_version}") + unset(_version) + unset(_quiet) + endif() +endif() + +if(PC_LIBDEBUGINFOD_FOUND) + # FindPkgConfig sometimes gets the include dir wrong + if("x${PC_LIBDEBUGINFOD_INCLUDE_DIRS}" STREQUAL "x") + pkg_get_variable(PC_LIBDEBUGINFOD_INCLUDE_DIRS libdebuginfod includedir) + endif() + + set(LibDebuginfod_INCLUDE_DIRS + ${PC_LIBDEBUGINFOD_INCLUDE_DIRS} + CACHE PATH "") + set(LibDebuginfod_LIBRARIES + ${PC_LIBDEBUGINFOD_LINK_LIBRARIES} + CACHE PATH "") + set(LibDebuginfod_VERSION + ${PC_LIBDEBUGINFOD_VERSION} + CACHE STRING "") +else() + find_path( + LibDebuginfod_INCLUDE_DIRS + NAMES debuginfod.h + PATH_SUFFIXES elfutils ${_find_path_args}) + + find_library( + LibDebuginfod_LIBRARIES + NAMES libdebuginfod debuginfod + PATH_SUFFIXES elfutils ${_find_path_args}) + + if(EXISTS "${LibDebuginfod_INCLUDE_DIRS}/version.h") + file(STRINGS "${LibDebuginfod_INCLUDE_DIRS}/version.h" _version_line + REGEX "^#define _ELFUTILS_VERSION[ \t]+[0-9]+") + string(REGEX MATCH "[0-9]+" _version "${_version_line}") + if(NOT "x${_version}" STREQUAL "x") + set(LibDebuginfod_VERSION "0.${_version}") + endif() + unset(_version_line) + unset(_version) + endif() +endif() include(FindPackageHandleStandardArgs) -find_package_handle_standard_args(LibDebuginfod - FOUND_VAR - LibDebuginfod_FOUND - REQUIRED_VARS - LibDebuginfod_INCLUDE_DIRS - LibDebuginfod_LIBRARIES - VERSION_VAR - LibDebuginfod_VERSION) +find_package_handle_standard_args( + LibDebuginfod + FOUND_VAR LibDebuginfod_FOUND + REQUIRED_VARS LibDebuginfod_LIBRARIES LibDebuginfod_INCLUDE_DIRS + VERSION_VAR LibDebuginfod_VERSION) if(LibDebuginfod_FOUND) - set(LibDebuginfod_INCLUDE_DIRS ${LibDebuginfod_INCLUDE_DIRS}) - set(LibDebuginfod_LIBRARIES ${LibDebuginfod_LIBRARIES}) - get_filename_component(_debuginfod_dir ${LibDebuginfod_LIBRARIES} DIRECTORY) - set(LibDebuginfod_LIBRARY_DIRS ${_debuginfod_dir} "${_debuginfod_dir}/elfutils") + mark_as_advanced(LibDebuginfod_INCLUDE_DIR) + mark_as_advanced(LibDebuginfod_LIBRARIES) + mark_as_advanced(LibDebuginfod_VERSION) + + if(NOT TARGET LibDebuginfod::LibDebuginfod) + add_library(LibDebuginfod::LibDebuginfod UNKNOWN IMPORTED) + set_target_properties( + LibDebuginfod::LibDebuginfod + PROPERTIES INTERFACE_INCLUDE_DIRECTORIES "${LibDebuginfod_INCLUDE_DIRS}" + IMPORTED_LINK_INTERFACE_LANGUAGES "C" + IMPORTED_LOCATION "${LibDebuginfod_LIBRARIES}") + endif() endif() + +unset(_find_path_args) diff --git a/cmake/Modules/FindLibDwarf.cmake b/cmake/Modules/FindLibDwarf.cmake deleted file mode 100644 index 5821b2eb9e..0000000000 --- a/cmake/Modules/FindLibDwarf.cmake +++ /dev/null @@ -1,90 +0,0 @@ -#=================================================================================== -# FindLibDwarf.cmake -# -# Find libdw include dirs and libraries -# -# ---------------------------------------- -# -# Use this module by invoking find_package with the form:: -# -# find_package(LibDwarf -# [version] [EXACT] # Minimum or EXACT version e.g. 0.173 -# [REQUIRED] # Fail with error if libdw is not found -# ) -# -# This module reads hints about search locations from variables:: -# -# LibDwarf_ROOT_DIR - Base directory the of libdw installation -# LibDwarf_INCLUDEDIR - Hint directory that contains the libdw headers files -# LibDwarf_LIBRARYDIR - Hint directory that contains the libdw library files -# -# and saves search results persistently in CMake cache entries:: -# -# LibDwarf_FOUND - True if headers and requested libraries were found -# LibDwarf_INCLUDE_DIRS - libdw include directories -# LibDwarf_LIBRARY_DIRS - Link directories for libdw libraries -# LibDwarf_LIBRARIES - libdw library files -# -#=================================================================================== - -include(DyninstSystemPaths) - -# Non-standard subdirectories to search -set(_path_suffixes libdw libdwarf elfutils) - -find_path(LibDwarf_INCLUDE_DIR - NAMES libdw.h - HINTS ${LibDwarf_ROOT_DIR}/include ${LibDwarf_ROOT_DIR} ${LibDwarf_INCLUDEDIR} - PATHS ${DYNINST_SYSTEM_INCLUDE_PATHS} - PATH_SUFFIXES ${_path_suffixes} - DOC "libdw include directories") - -find_library(LibDwarf_LIBRARIES - NAMES libdw.so.1 libdw.so - HINTS ${LibDwarf_ROOT_DIR}/lib ${LibDwarf_ROOT_DIR} ${LibDwarf_LIBRARYDIR} - PATHS ${DYNINST_SYSTEM_LIBRARY_PATHS} - PATH_SUFFIXES ${_path_suffixes}) - -# Find the library with the highest version -set(_max_ver 0.0) -set(_max_ver_lib) -foreach(l ${LibDwarf_LIBRARIES}) - get_filename_component(_dw_realpath ${LibDwarf_LIBRARIES} REALPATH) - string(REGEX MATCH - "libdw\\-(.+)\\.so\\.*$" - res - ${_dw_realpath}) - - # The library version number is stored in CMAKE_MATCH_1 - set(_cur_ver ${CMAKE_MATCH_1}) - - if(${_cur_ver} VERSION_GREATER ${_max_ver}) - set(_max_ver ${_cur_ver}) - set(_max_ver_lib ${l}) - endif() -endforeach() - -# Set the exported variables to the best match -set(LibDwarf_LIBRARIES ${_max_ver_lib}) -set(LibDwarf_VERSION ${_max_ver}) - -include(FindPackageHandleStandardArgs) -find_package_handle_standard_args(LibDwarf - FOUND_VAR - LibDwarf_FOUND - REQUIRED_VARS - LibDwarf_LIBRARIES - LibDwarf_INCLUDE_DIR - VERSION_VAR - LibDwarf_VERSION) - -# Export cache variables -if(LibDwarf_FOUND) - set(LibDwarf_INCLUDE_DIRS ${LibDwarf_INCLUDE_DIR}) - set(LibDwarf_LIBRARIES ${LibDwarf_LIBRARIES}) - - # Because we only report the library with the largest version, we are - # guaranteed there is only one file in LibDwarf_LIBRARIES - get_filename_component(_dw_dir ${LibDwarf_LIBRARIES} DIRECTORY) - set(LibDwarf_LIBRARY_DIRS ${_dw_dir}) -endif() diff --git a/cmake/Modules/FindLibELF.cmake b/cmake/Modules/FindLibELF.cmake new file mode 100644 index 0000000000..eed8b480de --- /dev/null +++ b/cmake/Modules/FindLibELF.cmake @@ -0,0 +1,123 @@ +#[=======================================================================[.rst: +FindLibELF +---------- + +Find libelf, the elfutils library to read and write ELF files. + +Variables that affect this module + +``LibELF_NO_SYSTEM_PATHS`` + If `True`, no system paths are searched. + +Imported targets +^^^^^^^^^^^^^^^^ + +This module defines the following :prop_tgt:`IMPORTED` target: + +``LibELF::LibELF`` + The libelf library, if found. + +Result variables +^^^^^^^^^^^^^^^^ + +This module will set the following variables in your project: + +``LibELF_INCLUDE_DIRS`` + where to find libelf.h, etc. +``LibELF_LIBRARIES`` + the libraries to link against to use libelf. +``LibELF_FOUND`` + If false, do not try to use libelf. +``LibELF_VERSION`` + the version of the libelf library found + +#]=======================================================================] +cmake_policy(SET CMP0074 NEW) # Use _ROOT + +if(LibELF_NO_SYSTEM_PATHS) + set(_find_path_args NO_CMAKE_SYSTEM_PATH NO_SYSTEM_ENVIRONMENT_PATH) +endif() + +# There is no way to tell pkg-config to ignore directories, so disable it +if(NOT LibELF_NO_SYSTEM_PATHS) + find_package(PkgConfig QUIET) + if(PKG_CONFIG_FOUND) + if(NOT "x${LibELF_FIND_VERSION}" STREQUAL "x") + set(_version ">=${LibELF_FIND_VERSION}") + endif() + if(LibELF_FIND_QUIETLY) + set(_quiet "QUIET") + endif() + + pkg_check_modules(PC_LIBELF ${_quiet} "libelf${_version}") + unset(_version) + unset(_quiet) + endif() +endif() + +if(PC_LIBELF_FOUND) + # FindPkgConfig sometimes gets the include dir wrong + if("x${PC_LIBELF_INCLUDE_DIRS}" STREQUAL "x") + pkg_get_variable(PC_LIBELF_INCLUDE_DIRS libelf includedir) + endif() + + set(LibELF_INCLUDE_DIRS + ${PC_LIBELF_INCLUDE_DIRS} + CACHE PATH "") + set(LibELF_LIBRARIES + ${PC_LIBELF_LINK_LIBRARIES} + CACHE PATH "") + set(LibELF_VERSION + ${PC_LIBELF_VERSION} + CACHE STRING "") +else() + find_path( + LibELF_INCLUDE_DIRS + NAMES libelf.h + PATH_SUFFIXES elfutils ${_find_path_args}) + + find_library( + LibELF_LIBRARIES + NAMES libelf elf + PATH_SUFFIXES elfutils ${_find_path_args}) + + macro(_check_libelf_version _file) + file(STRINGS ${_file} _version_line REGEX "^#define _ELFUTILS_VERSION[ \t]+[0-9]+") + string(REGEX MATCH "[0-9]+" _version "${_version_line}") + if(NOT "x${_version}" STREQUAL "x") + set(LibELF_VERSION "0.${_version}") + endif() + unset(_version_line) + unset(_version) + endmacro() + + if(EXISTS "${LibELF_INCLUDE_DIRS}/version.h") + _check_libelf_version("${LibELF_INCLUDE_DIRS}/version.h") + elseif(EXISTS "${LibELF_INCLUDE_DIRS}/elfutils/version.h") + _check_libelf_version("${LibELF_INCLUDE_DIRS}/elfutils/version.h") + endif() +endif() + +include(FindPackageHandleStandardArgs) +find_package_handle_standard_args( + LibELF + FOUND_VAR LibELF_FOUND + REQUIRED_VARS LibELF_LIBRARIES LibELF_INCLUDE_DIRS + VERSION_VAR LibELF_VERSION) + +if(LibELF_FOUND) + mark_as_advanced(LibELF_INCLUDE_DIRS) + mark_as_advanced(LibELF_LIBRARIES) + mark_as_advanced(LibELF_VERSION) + + if(NOT TARGET LibELF::LibELF) + add_library(LibELF::LibELF UNKNOWN IMPORTED) + set_target_properties( + LibELF::LibELF + PROPERTIES INTERFACE_INCLUDE_DIRECTORIES "${LibELF_INCLUDE_DIRS}" + IMPORTED_LINK_INTERFACE_LANGUAGES "C" + IMPORTED_LOCATION "${LibELF_LIBRARIES}") + endif() +endif() + +unset(_find_path_args) diff --git a/cmake/Modules/FindLibElf.cmake b/cmake/Modules/FindLibElf.cmake deleted file mode 100644 index f76ead7158..0000000000 --- a/cmake/Modules/FindLibElf.cmake +++ /dev/null @@ -1,93 +0,0 @@ -#======================================================================================== -# FindLibElf.cmake -# -# Find libelf include dirs and libraries -# -# ---------------------------------------- -# -# Use this module by invoking find_package with the form:: -# -# find_package(LibElf -# [version] [EXACT] # Minimum or EXACT version e.g. 0.173 -# [REQUIRED] # Fail with error if libelf is not found -# ) -# -# This module reads hints about search locations from variables:: -# -# LibElf_ROOT_DIR - Base directory the of libelf installation -# LibElf_INCLUDEDIR - Hint directory that contains the libelf headers files -# LibElf_LIBRARYDIR - Hint directory that contains the libelf library files -# -# and saves search results persistently in CMake cache entries:: -# -# LibElf_FOUND - True if headers and requested libraries were found -# LibElf_INCLUDE_DIRS - libelf include directories -# LibElf_LIBRARY_DIRS - Link directories for libelf libraries -# LibElf_LIBRARIES - libelf library files -# -# -# Based on the version by Bernhard Walle Copyright (c) 2008 -# -#======================================================================================== - -include(DyninstSystemPaths) - -# Non-standard subdirectories to search -set(_path_suffixes libelf libelfls elfutils) - -find_path(LibElf_INCLUDE_DIR - NAMES libelf.h - HINTS ${LibElf_ROOT_DIR}/include ${LibElf_ROOT_DIR} ${LibElf_INCLUDEDIR} - PATHS ${DYNINST_SYSTEM_INCLUDE_PATHS} - PATH_SUFFIXES ${_path_suffixes} - DOC "libelf include directories") - -find_library(LibElf_LIBRARIES - NAMES libelf.so.1 libelf.so - HINTS ${LibElf_ROOT_DIR}/lib ${LibElf_ROOT_DIR} ${LibElf_LIBRARYDIR} - PATHS ${DYNINST_SYSTEM_LIBRARY_PATHS} - PATH_SUFFIXES ${_path_suffixes}) - -# Find the library with the highest version -set(_max_ver 0.0) -set(_max_ver_lib) -foreach(l ${LibElf_LIBRARIES}) - get_filename_component(_elf_realpath ${LibElf_LIBRARIES} REALPATH) - string(REGEX MATCH - "libelf\\-(.+)\\.so\\.*$" - res - ${_elf_realpath}) - - # The library version number is stored in CMAKE_MATCH_1 - set(_cur_ver ${CMAKE_MATCH_1}) - - if(${_cur_ver} VERSION_GREATER ${_max_ver}) - set(_max_ver ${_cur_ver}) - set(_max_ver_lib ${l}) - endif() -endforeach() - -# Set the exported variables to the best match -set(LibElf_LIBRARIES ${_max_ver_lib}) -set(LibElf_VERSION ${_max_ver}) - -include(FindPackageHandleStandardArgs) -find_package_handle_standard_args(LibElf - FOUND_VAR - LibElf_FOUND - REQUIRED_VARS - LibElf_LIBRARIES - LibElf_INCLUDE_DIR - VERSION_VAR - LibElf_VERSION) - -# Export cache variables -if(LibElf_FOUND) - set(LibElf_INCLUDE_DIRS ${LibElf_INCLUDE_DIR}) - set(LibElf_LIBRARIES ${LibElf_LIBRARIES}) - - # Because we only report the library with the largest version, we are - # guaranteed there is only one file in LibElf_LIBRARIES - get_filename_component(_elf_dir ${LibElf_LIBRARIES} DIRECTORY) - set(LibElf_LIBRARY_DIRS ${_elf_dir} "${_elf_dir}/elfutils") -endif() diff --git a/cmake/Modules/FindLibIberty.cmake b/cmake/Modules/FindLibIberty.cmake index c52a342d6a..a5075dbfd0 100644 --- a/cmake/Modules/FindLibIberty.cmake +++ b/cmake/Modules/FindLibIberty.cmake @@ -1,81 +1,71 @@ -#======================================================================================== -# FindLibIberty.cmake -# -# Find LibIberty include dirs and libraries -# -# ---------------------------------------- -# -# Use this module by invoking find_package with the form:: -# -# find_package(LibIberty -# [REQUIRED] # Fail with error if LibIberty is not found -# ) -# -# This module reads hints about search locations from variables:: -# -# LibIberty_ROOT_DIR - Base directory the of LibIberty installation -# LibIberty_LIBRARYDIR - Hint directory that contains the LibIberty library files -# IBERTY_LIBRARIES - Alias for LibIberty_LIBRARIES (backwards compatibility only) -# LibIberty_INCLUDEDIR - Hint directory that contains the libiberty headers files -# -# and saves search results persistently in CMake cache entries:: -# -# LibIberty_FOUND - True if headers and requested libraries were found -# IBERTY_FOUND - Alias for LibIberty_FOUND (backwards compatibility only) -# LibIberty_INCLUDE_DIRS - libiberty include directories -# LibIberty_LIBRARY_DIRS - Link directories for LibIberty libraries -# LibIberty_LIBRARIES - LibIberty library files -# IBERTY_LIBRARIES - Alias for LibIberty_LIBRARIES (backwards compatibility only) -# -#======================================================================================== +#[=======================================================================[.rst: +FindLibIberty +------------- -if(LibIberty_FOUND) - return() -endif() +Find libiberty, a collection of subroutines used by various GNU programs. -# Keep the semantics of IBERTY_LIBRARIES for backward compatibility -# NB: If both are specified, LibIberty_LIBRARIES is ignored -if(NOT "${IBERTY_LIBRARIES}" STREQUAL "") - set(LibIberty_LIBRARIES ${IBERTY_LIBRARIES}) -endif() +Variables that affect this module -include(DyninstSystemPaths) +``LibIberty_NO_SYSTEM_PATHS`` + If `True`, no system paths are searched. -# Non-standard subdirectories to search -set(_path_suffixes libiberty iberty) +Imported targets +^^^^^^^^^^^^^^^^ -find_path(LibIberty_INCLUDE_DIRS - NAMES libiberty.h - HINTS ${LibIberty_ROOT_DIR} ${LibIberty_ROOT_DIR}/include ${LibIberty_INCLUDEDIR} - PATHS ${DYNINST_SYSTEM_INCLUDE_PATHS} - PATH_SUFFIXES ${_path_suffixes} - DOC "LibIberty include directories") +This module defines the following :prop_tgt:`IMPORTED` target: -# iberty_pic is for Debian <= wheezy -find_library(LibIberty_LIBRARIES - NAMES iberty_pic iberty - HINTS ${LibIberty_ROOT_DIR} - ${LibIberty_LIBRARYDIR} - ${IBERTY_LIBRARIES} - PATHS ${DYNINST_SYSTEM_LIBRARY_PATHS} - PATH_SUFFIXES ${_path_suffixes}) +``LibIberty::LibIberty`` + The libiberty library, if found. -include(FindPackageHandleStandardArgs) -find_package_handle_standard_args(LibIberty - FOUND_VAR - LibIberty_FOUND - REQUIRED_VARS - LibIberty_LIBRARIES) +Result variables +^^^^^^^^^^^^^^^^ + +This module will set the following variables in your project: + +``LibIberty_INCLUDE_DIRS`` + where to find libiberty.h, etc. +``LibIberty_LIBRARIES`` + the libraries to link against to use libiberty. +``LibIberty_FOUND`` + If false, do not try to use libiberty. + + LibIberty does not have its own version number or release schedule. + See https://gcc.gnu.org/onlinedocs/libiberty/Using.html#Using for details. -# For backwards compatibility only -set(IBERTY_FOUND ${LibIberty_FOUND}) +#]=======================================================================] +cmake_policy(SET CMP0074 NEW) # Use _ROOT + +if(LibIberty_NO_SYSTEM_PATHS) + set(_find_path_args NO_CMAKE_SYSTEM_PATH NO_SYSTEM_ENVIRONMENT_PATH) +endif() + +find_path( + LibIberty_INCLUDE_DIRS + NAMES libiberty.h + PATH_SUFFIXES libiberty ${_find_path_args}) +mark_as_advanced(LibIberty_INCLUDE_DIRS) + +find_library( + LibIberty_LIBRARIES + NAMES libiberty iberty + PATH_SUFFIXES libiberty ${_find_path_args}) +mark_as_advanced(LibIberty_LIBRARIES) + +include(FindPackageHandleStandardArgs) +find_package_handle_standard_args( + LibIberty + FOUND_VAR LibIberty_FOUND + REQUIRED_VARS LibIberty_LIBRARIES LibIberty_INCLUDE_DIRS) if(LibIberty_FOUND) - foreach(l in ${LibIberty_LIBRARIES}) - get_filename_component(_dir ${l} DIRECTORY) - list(APPEND LibIberty_LIBRARY_DIRS ${_dir}) - endforeach() - - # For backwards compatibility only - set(IBERTY_LIBRARIES ${LibIberty_LIBRARIES}) + if(NOT TARGET LibIberty::LibIberty) + add_library(LibIberty::LibIberty UNKNOWN IMPORTED) + set_target_properties( + LibIberty::LibIberty + PROPERTIES INTERFACE_INCLUDE_DIRECTORIES "${LibIberty_INCLUDE_DIRS}" + IMPORTED_LINK_INTERFACE_LANGUAGES "C" + IMPORTED_LOCATION "${LibIberty_LIBRARIES}") + endif() endif() + +unset(_find_path_args) diff --git a/cmake/Modules/FindTBB.cmake b/cmake/Modules/FindTBB.cmake deleted file mode 100644 index 93a9b8c662..0000000000 --- a/cmake/Modules/FindTBB.cmake +++ /dev/null @@ -1,315 +0,0 @@ -#====================================================================================================== -# FindTBB.cmake -# -# Find TBB include directories and libraries. -# -# ---------------------------------------- -# -# Use this module by invoking find_package with the form:: -# -# find_package(TBB -# [major[.minor]] [EXACT] [QUIET] # Minimum or EXACT version e.g. 2018.6 -# [REQUIRED] # Fail with error if TBB is not found -# [[COMPONENTS] [components...]] # Required components -# [OPTIONAL_COMPONENTS components...] # Optional components -# ) -# -# This module reads hints about search locations from variables:: -# -# TBB_ROOT_DIR - The base directory the of TBB installation. -# TBB_INCLUDE_DIR - The directory that contains the TBB headers files. -# TBB_LIBRARY - The directory that contains the TBB library files. -# TBB__LIBRARY - The path of the TBB the corresponding TBB library. -# These libraries override the corresponding library search results. -# TBB_USE_DEBUG_BUILD - Use the debug version of tbb libraries -# -# Environment variable aliases for TBB_ROOT_DIR: -# -# TBB_INSTALL_DIR -# TBBROOT -# LIBRARY_PATH -# -# This module will set the following variables: -# -# TBB_FOUND - If false, or undefined, TBB not found, or don’t want to use TBB. -# TBB__FOUND - If False, optional part of TBB sytem is not available. -# TBB_VERSION - The full version string -# TBB_VERSION_MAJOR - The major version -# TBB_VERSION_MINOR - The minor version -# TBB_INTERFACE_VERSION - The interface version number defined in tbb/tbb_stddef.h. -# TBB__LIBRARY_RELEASE - The path of the TBB release version of . -# TBB__LIBRARY_DEBUG - The path of the TBB debug version of . -# -# The following varibles should be used to build and link with TBB: -# -# TBB_INCLUDE_DIRS - The include directory for TBB. -# TBB_LIBRARY_DIRS - The library directory for TBB. -# TBB_LIBRARIES - The libraries to link against to use TBB. -# TBB_LIBRARIES_RELEASE - The release libraries to link against to use TBB. -# TBB_LIBRARIES_DEBUG - The debug libraries to link against to use TBB. -# TBB_DEFINITIONS - Definitions to use when compiling code that uses TBB. -# TBB_DEFINITIONS_RELEASE - Definitions to use when compiling release code that uses TBB. -# TBB_DEFINITIONS_DEBUG - Definitions to use when compiling debug code that uses TBB. -# -# This module will also create the "TBB" target that may be used when building -# executables and libraries. -# -# Based on the version by Justus Calvin - Copyright (c) 2015 -# -#====================================================================================================== - -if(TBB_FOUND) - return() -endif() - -include(FindPackageHandleStandardArgs) - -# -# Check the build type -# -if(NOT DEFINED TBB_USE_DEBUG_BUILD) - if(CMAKE_BUILD_TYPE MATCHES "(Debug|DEBUG|debug)") - set(TBB_BUILD_TYPE DEBUG) - else() - set(TBB_BUILD_TYPE RELEASE) - endif() -elseif(TBB_USE_DEBUG_BUILD) - set(TBB_BUILD_TYPE DEBUG) -else() - set(TBB_BUILD_TYPE RELEASE) -endif() - -# -# Set the TBB search directories -# - -# Define search paths based on user input and environment variables -set(TBB_SEARCH_DIR ${TBB_ROOT_DIR} $ENV{TBB_INSTALL_DIR} $ENV{TBBROOT}) - -# Define the search directories based on the current platform -if(CMAKE_SYSTEM_NAME STREQUAL "Windows") - set(TBB_DEFAULT_SEARCH_DIR "C:/Program Files/Intel/TBB" - "C:/Program Files (x86)/Intel/TBB") - - # Set the target architecture - if(CMAKE_SIZEOF_VOID_P EQUAL 8) - set(TBB_ARCHITECTURE "intel64") - else() - set(TBB_ARCHITECTURE "ia32") - endif() - - # Set the TBB search library path search suffix based on the version of VC - if(WINDOWS_STORE) - set(TBB_LIB_PATH_SUFFIX "lib/${TBB_ARCHITECTURE}/vc11_ui") - elseif(MSVC14) - set(TBB_LIB_PATH_SUFFIX "lib/${TBB_ARCHITECTURE}/vc14") - elseif(MSVC12) - set(TBB_LIB_PATH_SUFFIX "lib/${TBB_ARCHITECTURE}/vc12") - elseif(MSVC11) - set(TBB_LIB_PATH_SUFFIX "lib/${TBB_ARCHITECTURE}/vc11") - elseif(MSVC10) - set(TBB_LIB_PATH_SUFFIX "lib/${TBB_ARCHITECTURE}/vc10") - endif() - - # Add the library path search suffix for the VC independent version of TBB - list(APPEND TBB_LIB_PATH_SUFFIX "lib/${TBB_ARCHITECTURE}/vc_mt") - -elseif(CMAKE_SYSTEM_NAME STREQUAL "Darwin") - # OS X - set(TBB_DEFAULT_SEARCH_DIR "/opt/intel/tbb") - - # TODO: Check to see which C++ library is being used by the compiler. - if(NOT ${CMAKE_SYSTEM_VERSION} VERSION_LESS 13.0) - # The default C++ library on OS X 10.9 and later is libc++ - set(TBB_LIB_PATH_SUFFIX "lib/libc++" "lib") - else() - set(TBB_LIB_PATH_SUFFIX "lib") - endif() -elseif(CMAKE_SYSTEM_NAME STREQUAL "Linux") - # Linux - set(TBB_DEFAULT_SEARCH_DIR "/opt/intel/tbb") - - # TODO: Check compiler version to see the suffix should be /gcc4.1 or - # /gcc4.1. For now, assume that the compiler is more recent than gcc - # 4.4.x or later. - if(CMAKE_SYSTEM_PROCESSOR STREQUAL "x86_64") - set(TBB_LIB_PATH_SUFFIX "lib/intel64/gcc4.4") - elseif(CMAKE_SYSTEM_PROCESSOR MATCHES "^i.86$") - set(TBB_LIB_PATH_SUFFIX "lib/ia32/gcc4.4") - endif() -endif() - -# -# Find the TBB include dir -# -find_path(TBB_INCLUDE_DIRS tbb/tbb.h - HINTS ${TBB_INCLUDE_DIRS} ${TBB_SEARCH_DIR} - PATHS ${TBB_DEFAULT_SEARCH_DIR} - PATH_SUFFIXES include) - -# -# Set version strings -# -if(TBB_INCLUDE_DIRS) - # Starting in 2020.1.1, tbb_stddef.h is replaced by version.h - set(_version_files - "${TBB_INCLUDE_DIRS}/tbb/tbb_stddef.h" - "${TBB_INCLUDE_DIRS}/tbb/version.h" - ) - foreach(f IN ITEMS ${_version_files}) - if(EXISTS ${f}) - set(_version_file ${f}) - endif() - endforeach() - unset(_version_files) - - file(READ ${_version_file} _tbb_version_file) - string(REGEX - REPLACE ".*#define TBB_VERSION_MAJOR ([0-9]+).*" - "\\1" - TBB_VERSION_MAJOR - "${_tbb_version_file}") - string(REGEX - REPLACE ".*#define TBB_VERSION_MINOR ([0-9]+).*" - "\\1" - TBB_VERSION_MINOR - "${_tbb_version_file}") - string(REGEX - REPLACE ".*#define TBB_INTERFACE_VERSION ([0-9]+).*" - "\\1" - TBB_INTERFACE_VERSION - "${_tbb_version_file}") - - # The TBB_VERSION_MINOR isn't necessarily changed for minor releases - # Hence, we need to read the engineering versioning in TBB_INTERFACE_VERSION - # to get the minor version correct - if("${TBB_VERSION_MINOR}" STREQUAL "0") - math(EXPR _tbb_iface_major_ver "${TBB_INTERFACE_VERSION} / 100") - math(EXPR TBB_VERSION_MINOR "${TBB_INTERFACE_VERSION} - ${_tbb_iface_major_ver} * 100") - endif() - set(TBB_VERSION "${TBB_VERSION_MAJOR}.${TBB_VERSION_MINOR}") -endif() - -# -# Find TBB components -# -if(TBB_VERSION VERSION_LESS 4.3) - set(TBB_SEARCH_COMPOMPONENTS tbb_preview tbbmalloc tbb) -else() - set(TBB_SEARCH_COMPOMPONENTS tbb_preview tbbmalloc_proxy tbbmalloc tbb) -endif() - -set(TBB_LIBRARY_DIRS) - -# Find each component -foreach(_comp ${TBB_SEARCH_COMPOMPONENTS}) - message(STATUS "Searching for ${_comp}...") - message(STATUS "Hints: ${TBB_LIBRARY} ${TBB_SEARCH_DIR}") - if(";${TBB_FIND_COMPONENTS};tbb;" MATCHES ";${_comp};") - - # Search for the libraries - find_library(TBB_${_comp}_LIBRARY_RELEASE ${_comp} - HINTS ${TBB_LIBRARY} ${TBB_SEARCH_DIR} - PATHS ${TBB_DEFAULT_SEARCH_DIR} ENV LIBRARY_PATH - PATH_SUFFIXES ${TBB_LIB_PATH_SUFFIX} lib_release) - - find_library(TBB_${_comp}_LIBRARY_DEBUG ${_comp}_debug - HINTS ${TBB_LIBRARY} ${TBB_SEARCH_DIR} - PATHS ${TBB_DEFAULT_SEARCH_DIR} ENV LIBRARY_PATH - PATH_SUFFIXES ${TBB_LIB_PATH_SUFFIX} lib_debug) - - if(TBB_${_comp}_LIBRARY_DEBUG) - list(APPEND TBB_LIBRARIES_DEBUG "${TBB_${_comp}_LIBRARY_DEBUG}") - message(STATUS "Found ${TBB_${_comp}_LIBRARY_DEBUG}") - endif() - if(TBB_${_comp}_LIBRARY_RELEASE) - list(APPEND TBB_LIBRARIES_RELEASE "${TBB_${_comp}_LIBRARY_RELEASE}") - message(STATUS "Found ${TBB_${_comp}_LIBRARY_RELEASE}") - endif() - if(TBB_${_comp}_LIBRARY_${TBB_BUILD_TYPE} AND NOT TBB_${_comp}_LIBRARY) - set(TBB_${_comp}_LIBRARY "${TBB_${_comp}_LIBRARY_${TBB_BUILD_TYPE}}") - endif() - - if(TBB_${_comp}_LIBRARY AND EXISTS "${TBB_${_comp}_LIBRARY}") - set(TBB_${_comp}_FOUND TRUE) - else() - set(TBB_${_comp}_FOUND FALSE) - endif() - - # Mark internal variables as advanced - mark_as_advanced(TBB_${_comp}_LIBRARY_RELEASE) - mark_as_advanced(TBB_${_comp}_LIBRARY_DEBUG) - mark_as_advanced(TBB_${_comp}_LIBRARY) - - # Save the directory names for each library component - if(TBB_USE_DEBUG_BUILD) - get_filename_component(_dir ${TBB_${_comp}_LIBRARY_DEBUG} DIRECTORY) - else() - get_filename_component(_dir ${TBB_${_comp}_LIBRARY_RELEASE} DIRECTORY) - endif() - list(APPEND TBB_LIBRARY_DIRS ${_dir}) - endif() -endforeach() - -# -# Set compile flags and libraries -# -set(TBB_DEFINITIONS_RELEASE "") -set(TBB_DEFINITIONS_DEBUG "-DTBB_USE_DEBUG=1") - -if(TBB_LIBRARIES_${TBB_BUILD_TYPE}) - set(TBB_DEFINITIONS "${TBB_DEFINITIONS_${TBB_BUILD_TYPE}}") - set(TBB_LIBRARIES "${TBB_LIBRARIES_${TBB_BUILD_TYPE}}") -elseif(TBB_LIBRARIES_RELEASE) - set(TBB_DEFINITIONS "${TBB_DEFINITIONS_RELEASE}") - set(TBB_LIBRARIES "${TBB_LIBRARIES_RELEASE}") -elseif(TBB_LIBRARIES_DEBUG) - set(TBB_DEFINITIONS "${TBB_DEFINITIONS_DEBUG}") - set(TBB_LIBRARIES "${TBB_LIBRARIES_DEBUG}") -endif() - -find_package_handle_standard_args(TBB - REQUIRED_VARS - TBB_INCLUDE_DIRS - TBB_LIBRARIES - HANDLE_COMPONENTS - VERSION_VAR - TBB_VERSION) - -# -# Create targets -# -if(NOT CMAKE_VERSION VERSION_LESS 3.0 AND TBB_FOUND) - add_library(TBB SHARED IMPORTED) - set_target_properties(TBB - PROPERTIES INTERFACE_INCLUDE_DIRECTORIES - ${TBB_INCLUDE_DIRS} - IMPORTED_LOCATION - ${TBB_LIBRARIES}) - if(TBB_LIBRARIES_RELEASE AND TBB_LIBRARIES_DEBUG) - set_target_properties(TBB - PROPERTIES INTERFACE_COMPILE_DEFINITIONS - "$<$:TBB_USE_DEBUG=1>" - IMPORTED_LOCATION_DEBUG - ${TBB_LIBRARIES_DEBUG} - IMPORTED_LOCATION_RELWITHDEBINFO - ${TBB_LIBRARIES_DEBUG} - IMPORTED_LOCATION_RELEASE - ${TBB_LIBRARIES_RELEASE} - IMPORTED_LOCATION_MINSIZEREL - ${TBB_LIBRARIES_RELEASE}) - elseif(TBB_LIBRARIES_RELEASE) - set_target_properties(TBB - PROPERTIES IMPORTED_LOCATION ${TBB_LIBRARIES_RELEASE}) - else() - set_target_properties(TBB - PROPERTIES IMPORTED_LOCATION ${TBB_LIBRARIES_DEBUG}) - endif() -endif() - -mark_as_advanced(TBB_INCLUDE_DIRS TBB_LIBRARIES TBB_LIBRARY_DIRS) - -unset(TBB_ARCHITECTURE) -unset(TBB_BUILD_TYPE) -unset(TBB_LIB_PATH_SUFFIX) -unset(TBB_DEFAULT_SEARCH_DIR) diff --git a/cmake/Modules/FindThreadDB.cmake b/cmake/Modules/FindThreadDB.cmake deleted file mode 100644 index 35bd118d04..0000000000 --- a/cmake/Modules/FindThreadDB.cmake +++ /dev/null @@ -1,52 +0,0 @@ -# - Try to find thread_db -# Once done this will define -# -# THREAD_DB_FOUND - system has thread_db -# THREAD_DB_INCLUDE_DIRS - the thread_db include directory -# THREAD_DB_LIBRARIES - Link these to use thread_db -# THREAD_DB_DEFINITIONS - Compiler switches required for using thread_db -# - -if (THREAD_DB_LIBRARIES AND THREAD_DB_INCLUDE_DIRS) - set (Thread_Db_FIND_QUIETLY TRUE) -endif (THREAD_DB_LIBRARIES AND THREAD_DB_INCLUDE_DIRS) - -find_path (THREAD_DB_INCLUDE_DIR - NAMES - thread_db.h - HINTS - ${THREAD_DB_INCLUDE_DIRS} - PATHS - /usr/include - /usr/include/thread_db - /usr/local/include - /opt/local/include - /sw/include - ENV CPATH) # PATH and INCLUDE will also work - -find_library (THREAD_DB_LIBRARIES - NAMES - thread_db - HINTS - ${THREAD_DB_LIBRARIES} - PATHS - /usr/lib - /usr/lib64 - /usr/local/lib - /usr/local/lib64 - /opt/local/lib - /opt/local/lib64 - /sw/lib - ENV LIBRARY_PATH # PATH and LIB will also work - ENV LD_LIBRARY_PATH) -include (FindPackageHandleStandardArgs) - - -# handle the QUIETLY and REQUIRED arguments and set THREAD_DB_FOUND to TRUE -# if all listed variables are TRUE -FIND_PACKAGE_HANDLE_STANDARD_ARGS(Thread_Db DEFAULT_MSG - THREAD_DB_LIBRARIES - THREAD_DB_INCLUDE_DIR) - -#mark_as_advanced(LIBDW_INCLUDE_DIR DWARF_INCLUDE_DIR) -#mark_as_advanced(THREAD_DB_INCLUDE_DIRS THREAD_DB_LIBRARIES) diff --git a/cmake/Modules/FindThread_DB.cmake b/cmake/Modules/FindThread_DB.cmake new file mode 100644 index 0000000000..433b1a56b4 --- /dev/null +++ b/cmake/Modules/FindThread_DB.cmake @@ -0,0 +1,55 @@ +#[=======================================================================[.rst: +FindThread_DB +------------- + +Find thread_db, the debugger interface for the NPTL library. + +Imported targets +^^^^^^^^^^^^^^^^ + +This module defines the following :prop_tgt:`IMPORTED` target: + +``Thread_DB::Thread_DB`` + The threaddb library, if found. + +Result variables +^^^^^^^^^^^^^^^^ + +This module will set the following variables in your project: + +``Thread_DB_INCLUDE_DIRS`` + where to find thread_db.h, etc. +``Thread_DB_LIBRARIES`` + the libraries to link against to use thread_db. +``Thread_DB_FOUND`` + If false, do not try to use thread_db. + + Thread_DB does not have its own version number or release schedule. + See https://sourceware.org/gdb/current/onlinedocs/gdb/Threads.html for details. + +#]=======================================================================] +cmake_policy(SET CMP0074 NEW) # Use _ROOT + +find_path(Thread_DB_INCLUDE_DIRS NAMES thread_db.h) + +find_library(Thread_DB_LIBRARIES NAMES thread_db) + +include(FindPackageHandleStandardArgs) +find_package_handle_standard_args( + Thread_DB + FOUND_VAR Thread_DB_FOUND + REQUIRED_VARS Thread_DB_LIBRARIES Thread_DB_INCLUDE_DIRS) + +if(Thread_DB_FOUND) + if(NOT TARGET Thread_DB::Thread_DB) + add_library(Thread_DB::Thread_DB UNKNOWN IMPORTED) + set_target_properties( + Thread_DB::Thread_DB + PROPERTIES INTERFACE_INCLUDE_DIRECTORIES "${Thread_DB_INCLUDE_DIRS}" + IMPORTED_LINK_INTERFACE_LANGUAGES "C" + IMPORTED_LOCATION "${Thread_DB_LIBRARIES}") + endif() + + mark_as_advanced(Thread_DB_INCLUDE_DIRS) + mark_as_advanced(Thread_DB_LIBRARIES) +endif() diff --git a/cmake/Modules/FindValgrind.cmake b/cmake/Modules/FindValgrind.cmake index e286e671d1..52946d38b3 100644 --- a/cmake/Modules/FindValgrind.cmake +++ b/cmake/Modules/FindValgrind.cmake @@ -1,45 +1,100 @@ -#======================================================================================== -# FindValgrind.cmake -# -# Find Valgrind include dirs -# -# ---------------------------------------- -# -# Use this module by invoking find_package with the form:: -# -# find_package(Valgrind -# [REQUIRED] # Fail with error if Valgrind headers are not found -# ) -# -# This module reads hints about search locations from variables:: -# -# Valgrind_ROOT_DIR - Base directory the of Valgrind installation -# Valgrind_INCLUDEDIR - Hint directory that contains the Valgrind headers files -# -# and saves search results persistently in CMake cache entries:: -# -# Valgrind_FOUND - True if headers were found -# Valgrind_INCLUDE_DIRS - Valgrind include directories -# -#======================================================================================== - -include(DyninstSystemPaths) - -find_path(Valgrind_INCLUDE_DIR - NAMES valgrind.h - HINTS ${Valgrind_ROOT_DIR}/include ${Valgrind_ROOT_DIR} ${Valgrind_INCLUDEDIR} - PATHS ${DYNINST_SYSTEM_INCLUDE_PATHS} - PATH_SUFFIXES valgrind - DOC "Valgrind include directory") +#[=======================================================================[.rst: +FindLibValgrind +--------------- -include(FindPackageHandleStandardArgs) -find_package_handle_standard_args(Valgrind - FOUND_VAR - Valgrind_FOUND - REQUIRED_VARS - Valgrind_INCLUDE_DIR) - -# Export cache variables -if(Valgrind_FOUND) - set(Valgrind_INCLUDE_DIRS ${Valgrind_INCLUDE_DIR}) +Find valgrind, a dynamic binary instrumentation framework. + +Variables that affect this module + +``Valgrind_NO_SYSTEM_PATHS`` + If `True`, no system paths are searched. + +Imported targets +^^^^^^^^^^^^^^^^ + +This module defines the following :prop_tgt:`IMPORTED` target: + +``Valgrind::Valgrind`` + The valgrind library, if found. + +Result variables +^^^^^^^^^^^^^^^^ + +This module will set the following variables in your project: + +``Valgrind_INCLUDE_DIRS`` + where to find valgrind.h, etc. +``Valgrind_FOUND`` + If false, do not try to use valgrind. +``Valgrind_VERSION`` + the version of the valgrind library found + +#]=======================================================================] +cmake_policy(SET CMP0074 NEW) # Use _ROOT + +if(Valgrind_NO_SYSTEM_PATHS) + set(_find_path_args NO_CMAKE_SYSTEM_PATH NO_SYSTEM_ENVIRONMENT_PATH) endif() + +if(NOT Valgrind_NO_SYSTEM_PATHS) + find_package(PkgConfig QUIET) + if(PKG_CONFIG_FOUND) + if(NOT "x${Valgrind_FIND_VERSION}" STREQUAL "x") + set(_version ">=${Valgrind_FIND_VERSION}") + endif() + if(Valgrind_FIND_QUIETLY) + set(_quiet "QUIET") + endif() + + pkg_check_modules(PC_VALGRIND ${_quiet} "valgrind${_version}") + unset(_version) + unset(_quiet) + endif() +endif() + +if(PC_VALGRIND_FOUND) + # FindPkgConfig sometimes gets the include dir wrong + if("x${PC_VALGRIND_INCLUDE_DIRS}" STREQUAL "x") + pkg_get_variable(PC_VALGRIND_INCLUDE_DIRS valgrind includedir) + endif() + + set(Valgrind_INCLUDE_DIRS + ${PC_VALGRIND_INCLUDE_DIRS} + CACHE PATH "") + set(Valgrind_VERSION + ${PC_VALGRIND_VERSION} + CACHE STRING "") +else() + find_path( + Valgrind_INCLUDE_DIRS + NAMES valgrind.h + PATH_SUFFIXES valgrind ${_find_path_args}) + + macro(_check_valgrind_version _file) + file(STRINGS ${_file} _version_line REGEX "^#define __VALGRIND_MAJOR__[ \t]+[0-9]+") + string(REGEX MATCH "[0-9]+" _major "${_version_line}") + file(STRINGS ${_file} _version_line REGEX "^#define __VALGRIND_MINOR__[ \t]+[0-9]+") + string(REGEX MATCH "[0-9]+" _minor "${_version_line}") + set(Valgrind_VERSION "${_major}.${_minor}") + unset(_version_line) + unset(_major) + unset(_minor) + endmacro() + + if(EXISTS "${Valgrind_INCLUDE_DIRS}/valgrind.h") + _check_valgrind_version("${Valgrind_INCLUDE_DIRS}/valgrind.h") + elseif(EXISTS "${Valgrind_INCLUDE_DIRS}/valgrind/valgrind.h") + _check_valgrind_version("${Valgrind_INCLUDE_DIRS}/valgrind/valgrind.h") + endif() +endif() + +include(FindPackageHandleStandardArgs) +find_package_handle_standard_args( + Valgrind + FOUND_VAR Valgrind_FOUND + REQUIRED_VARS Valgrind_INCLUDE_DIRS + VERSION_VAR Valgrind_VERSION) + +mark_as_advanced(Valgrind_INCLUDE_DIRS) + +unset(_find_path_args) diff --git a/cmake/ThreadingBuildingBlocks.cmake b/cmake/ThreadingBuildingBlocks.cmake deleted file mode 100644 index 551f83156c..0000000000 --- a/cmake/ThreadingBuildingBlocks.cmake +++ /dev/null @@ -1,180 +0,0 @@ -#===================================================================================== -# ThreadingBuildingBlocks.cmake -# -# Configure Intel's Threading Building Blocks for Dyninst -# -# ---------------------------------------- -# -# Accepts the following CMake variables -# -# TBB_ROOT_DIR - Hint directory that contains the TBB installation -# TBB_INCLUDEDIR - Hint directory that contains the TBB headers files -# TBB_LIBRARYDIR - Hint directory that contains the TBB library files -# TBB_LIBRARY - Alias for TBB_LIBRARYDIR -# TBB_USE_DEBUG_BUILD - Use debug version of tbb libraries, if present -# TBB_MIN_VERSION - Minimum acceptable version of TBB -# -# Directly exports the following CMake variables -# -# TBB_ROOT_DIR - Computed base directory of TBB installation -# TBB_INCLUDE_DIRS - TBB include directory -# TBB_INCLUDE_DIR - Alias for TBB_INCLUDE_DIRS -# TBB_LIBRARY_DIRS - TBB library directory -# TBB_LIBRARY_DIR - Alias for TBB_LIBRARY_DIRS -# TBB_DEFINITIONS - TBB compiler definitions -# TBB_LIBRARIES - TBB library files -# -# TBB__LIBRARY_RELEASE - Path to the release version of component -# TBB__LIBRARY_DEBUG - Path to the debug version of component -# -# NOTE: -# The exported TBB_ROOT_DIR can be different from the value provided by the user -# in the case that it is determined to build TBB from source. In such a case, -# TBB_ROOT_DIR will contain the directory of the from-source installation. -# -# -# See Modules/FindTBB.cmake for additional input and exported variables -# -#===================================================================================== - -if(TBB_FOUND) - return() -endif() - -# -------------- RUNTIME CONFIGURATION ---------------------------------------- - -# Use debug versions of TBB libraries -set(TBB_USE_DEBUG_BUILD OFF CACHE BOOL "Use debug versions of TBB libraries") - -# Minimum version of TBB (assumes a dotted-decimal format: YYYY.XX) -if(${CMAKE_CXX_COMPILER_ID} STREQUAL "Clang") - set(_tbb_min_version 2019.7) -else() - set(_tbb_min_version 2018.6) -endif() - -set(TBB_MIN_VERSION ${_tbb_min_version} CACHE STRING "Minimum version of TBB (assumes a dotted-decimal format: YYYY.XX)") - -if(${TBB_MIN_VERSION} VERSION_LESS ${_tbb_min_version}) - message( - FATAL_ERROR - "Requested TBB version ${TBB_MIN_VERSION} is less than minimum supported version ${_tbb_min_version}" - ) -endif() - -# -------------- PATHS -------------------------------------------------------- - -# TBB root directory -set(TBB_ROOT_DIR "/usr" CACHE PATH "TBB root directory") - -# TBB include directory hint -set(TBB_INCLUDEDIR "${TBB_ROOT_DIR}/include" CACHE PATH "TBB include directory") - -# TBB library directory hint -set(TBB_LIBRARYDIR "${TBB_ROOT_DIR}/lib" CACHE PATH "TBB library directory") - -# Translate to FindTBB names -set(TBB_LIBRARY ${TBB_LIBRARYDIR}) -set(TBB_INCLUDE_DIR ${TBB_INCLUDEDIR}) - -# The specific TBB libraries we need -# NB: This should _NOT_ be a cache variable -set(_tbb_components tbb tbbmalloc tbbmalloc_proxy) - -find_package(TBB ${TBB_MIN_VERSION} COMPONENTS ${_tbb_components}) - -# -------------- SOURCE BUILD ------------------------------------------------- -if(TBB_FOUND) - # Force the cache entries to be updated - # Normally, these would not be exported. However, we need them in the Testsuite - set(TBB_INCLUDE_DIRS ${TBB_INCLUDE_DIRS} CACHE PATH "TBB include directory" FORCE) - set(TBB_LIBRARY_DIRS ${TBB_LIBRARY_DIRS} CACHE PATH "TBB library directory" FORCE) - set(TBB_DEFINITIONS ${TBB_DEFINITIONS} CACHE STRING "TBB compiler definitions" FORCE) - set(TBB_LIBRARIES ${TBB_LIBRARIES} CACHE FILEPATH "TBB library files" FORCE) - - if(NOT TARGET TBB) - add_library(TBB SHARED IMPORTED) - endif() -elseif(NOT TBB_FOUND AND STERILE_BUILD) - message(FATAL_ERROR "TBB not found and cannot be downloaded because build is sterile.") -else() - # If we didn't find a suitable version on the system, then download one from the web - message(STATUS "${ThreadingBuildingBlocks_ERROR_REASON}") - message(STATUS "Attempting to build TBB(${TBB_MIN_VERSION}) as external project") - - if(NOT UNIX) - message(FATAL_ERROR "Building TBB from source is not supported on this platform") - endif() - - # Forcibly update the cache variables - set(TBB_ROOT_DIR ${CMAKE_INSTALL_PREFIX} CACHE PATH "TBB root directory" FORCE) - set(TBB_INCLUDE_DIRS ${TBB_ROOT_DIR}/include CACHE PATH "TBB include directory" FORCE) - set(TBB_LIBRARY_DIRS ${TBB_ROOT_DIR}/lib CACHE PATH "TBB library directory" FORCE) - set(TBB_DEFINITIONS "" CACHE STRING "TBB compiler definitions" FORCE) - - set(_tbb_libraries) - set(_tbb_components_cfg) - - foreach(c ${_tbb_components}) - # Generate make target names - if(${c} STREQUAL tbbmalloc_proxy) - # tbbmalloc_proxy is spelled tbbproxy in their Makefiles - list(APPEND _tbb_components_cfg tbbproxy_release) - else() - list(APPEND _tbb_components_cfg ${c}_release) - endif() - - # Generate library filenames - list(APPEND _tbb_libraries "${TBB_LIBRARY_DIRS}/lib${c}.so") - - foreach(t RELEASE DEBUG) - set(TBB_${c}_LIBRARY_${t} "${TBB_LIBRARY_DIRS}/lib${c}.so" CACHE FILEPATH "" FORCE) - endforeach() - endforeach() - - set(TBB_LIBRARIES ${_tbb_libraries} CACHE FILEPATH "TBB library files" FORCE) - - # Split the dotted decimal version into major/minor parts - string(REGEX REPLACE "\\." ";" _tbb_download_name ${TBB_MIN_VERSION}) - list(GET _tbb_download_name 0 _tbb_ver_major) - list(GET _tbb_download_name 1 _tbb_ver_minor) - - include(ExternalProject) - set(_tbb_prefix_dir ${CMAKE_BINARY_DIR}/tbb) - - # Set the compiler for TBB - # It assumes gcc and tests for Intel, so clang is the only - # one that needs special treatment. - if(${CMAKE_CXX_COMPILER_ID} STREQUAL "Clang") - set(_tbb_compiler "compiler=clang") - endif() - - ExternalProject_Add( - TBB - PREFIX ${_tbb_prefix_dir} - URL https://github.com/01org/tbb/archive/${_tbb_ver_major}_U${_tbb_ver_minor}.tar.gz - BUILD_IN_SOURCE 1 - CONFIGURE_COMMAND "" - BUILD_COMMAND - CC=${CMAKE_C_COMPILER} CXX=${CMAKE_CXX_COMPILER} - $(MAKE) -C src - ${_tbb_components_cfg} - tbb_build_dir=${_tbb_prefix_dir}/src - tbb_build_prefix=tbb - ${_tbb_compiler} - INSTALL_COMMAND - ${CMAKE_COMMAND} - -DLIBDIR=${TBB_LIBRARY_DIRS} - -DINCDIR=${TBB_INCLUDE_DIRS} - -DPREFIX=${_tbb_prefix_dir} - -P ${CMAKE_CURRENT_LIST_DIR}/ThreadingBuildingBlocks.install.cmake - ) -endif() - -include_directories(SYSTEM ${TBB_INCLUDE_DIRS}) -link_directories(${TBB_LIBRARY_DIRS}) - -message(STATUS "TBB include directory: ${TBB_INCLUDE_DIRS}") -message(STATUS "TBB library directory: ${TBB_LIBRARY_DIRS}") -message(STATUS "TBB libraries: ${TBB_LIBRARIES}") -message(STATUS "TBB definitions: ${TBB_DEFINITIONS}") diff --git a/cmake/ThreadingBuildingBlocks.install.cmake b/cmake/ThreadingBuildingBlocks.install.cmake deleted file mode 100644 index c1043c389e..0000000000 --- a/cmake/ThreadingBuildingBlocks.install.cmake +++ /dev/null @@ -1,24 +0,0 @@ -################################################################# -# ThreadingBuildingBlocks.cmake -# -# Install Intel's Threading Building Blocks for Dyninst -# -# The default TBB build does not have an 'install' target, so we -# have to do it manually. This file contains the necessary CMake -# commands to complete the installation assuming it has been built -# using ExternalProject_Add. -# -################################################################# - -file(MAKE_DIRECTORY ${LIBDIR} ${INCDIR}) -file(COPY ${PREFIX}/src/tbb_release/ DESTINATION ${LIBDIR} FILES_MATCHING PATTERN "*.so.*") -file(COPY ${PREFIX}/src/TBB/include/tbb DESTINATION ${INCDIR}) - -file(GLOB _tbb_libs ${LIBDIR}/libtbb*.so.*) - -foreach(l ${_tbb_libs}) - string(REGEX REPLACE "\\.2$" "" _l_short ${l}) - execute_process( - COMMAND ${CMAKE_COMMAND} -E create_symlink ${l} ${_l_short} - ) -endforeach() diff --git a/cmake/cap_arch_def.cmake b/cmake/cap_arch_def.cmake deleted file mode 100644 index 6e523018d4..0000000000 --- a/cmake/cap_arch_def.cmake +++ /dev/null @@ -1,151 +0,0 @@ -# The test suite needs this as a list rather than a bunch -# of definitions so that we can append _test to it. - -set (CAP_DEFINES - -Dcap_dynamic_heap - -Dcap_liveness - -Dcap_threads -) - -if (PLATFORM MATCHES i386) -set (ARCH_DEFINES -Darch_x86) -set (CAP_DEFINES ${CAP_DEFINES} - -Dcap_fixpoint_gen - -Dcap_noaddr_gen - -Dcap_stripped_binaries - -Dcap_tramp_liveness - -Dcap_virtual_registers - -Dcap_stack_mods - ) - -elseif (PLATFORM MATCHES x86_64 OR PLATFORM MATCHES amd64) -set (ARCH_DEFINES -Darch_x86_64 -Darch_64bit) -set (CAP_DEFINES ${CAP_DEFINES} - -Dcap_32_64 - -Dcap_fixpoint_gen - -Dcap_noaddr_gen - -Dcap_registers - -Dcap_stripped_binaries - -Dcap_tramp_liveness - -Dcap_stack_mods - ) - -elseif (PLATFORM MATCHES ppc32) -set (ARCH_DEFINES -Darch_power) -set (CAP_DEFINES ${CAP_DEFINES} - -Dcap_registers - ) - -elseif (PLATFORM MATCHES ppc64) - set (ARCH_DEFINES -Darch_power -Darch_64bit) - set (CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -m64") - set (CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -m64") - set (CAP_DEFINES ${CAP_DEFINES} - -Dcap_32_64 - -Dcap_registers - -Dcap_toc_64 - ) - if (SYSPLATFORM MATCHES ppc64le) - set (CAP_DEFINES ${CAP_DEFINES} - -Darch_ppc_little_endian - ) - endif (SYSPLATFORM MATCHES ppc64le) -elseif (PLATFORM MATCHES aarch64) - #set (ARCH_DEFINES -Daarch_64 -Darch_64bit) - set (ARCH_DEFINES -Darch_aarch64 -Darch_64bit) - set (CAP_DEFINES ${CAP_DEFINES} -Dcap_32_64 -Dcap_registers) -endif (PLATFORM MATCHES i386) - -if (PLATFORM MATCHES linux) -set (OS_DEFINES -Dos_linux) -set (CAP_DEFINES ${CAP_DEFINES} - -Dcap_async_events - -Dcap_binary_rewriter - -Dcap_dwarf - -Dcap_mutatee_traps - -Dcap_ptrace - ) -set (BUG_DEFINES -Dbug_syscall_changepc_rewind -Dbug_force_terminate_failure) - -elseif (PLATFORM MATCHES cnl) -set (OS_DEFINES -Dos_linux -Dos_cnl) -set (CAP_DEFINES ${CAP_DEFINES} - -Dcap_async_events - -Dcap_binary_rewriter - -Dcap_dwarf - -Dcap_mutatee_traps - -Dcap_ptrace - ) -set (BUG_DEFINES -Dbug_syscall_changepc_rewind) - -elseif (PLATFORM MATCHES freebsd) -set (OS_DEFINES -Dos_freebsd) -set (CAP_DEFINES ${CAP_DEFINES} - -Dcap_binary_rewriter - -Dcap_dwarf - -Dcap_mutatee_traps - ) -set (BUG_DEFINES -Dbug_freebsd_missing_sigstop - -Dbug_freebsd_mt_suspend - -Dbug_freebsd_change_pc - -Dbug_phdrs_first_page - -Dbug_syscall_changepc_rewind - ) - -elseif (PLATFORM STREQUAL i386-unknown-nt4.0) -set (OS_DEFINES -Dos_windows) -set (CAP_DEFINES ${CAP_DEFINES} - -Dcap_mem_emulation - -Dcap_mutatee_traps - ) -endif (PLATFORM MATCHES linux) - - -if (PLATFORM STREQUAL i386-unknown-linux2.4) -set (OLD_DEFINES -Di386_unknown_linux2_0) - -elseif (PLATFORM STREQUAL x86_64-unknown-linux2.4) -set (OLD_DEFINES -Dx86_64_unknown_linux2_4) - -elseif (PLATFORM STREQUAL ppc32_linux) -set (OLD_DEFINES -Dppc32_linux) -set (BUG_DEFINES ${BUG_DEFINES} -Dbug_registers_after_exit) - -elseif (PLATFORM STREQUAL ppc64_linux) -set (OLD_DEFINES -Dppc64_linux) -set (BUG_DEFINES ${BUG_DEFINES} -Dbug_registers_after_exit) - -elseif (PLATFORM STREQUAL x86_64_cnl) -set (OLD_DEFINES -Dx86_64_cnl -Dx86_64_unknown_linux2_4) - -elseif (PLATFORM STREQUAL i386-unknown-freebsd7.2) -set (OLD_DEFINES -Di386_unknown_freebsd7_0) - -elseif (PLATFORM STREQUAL amd64-unknown-freebsd7.2) -set (OLD_DEFINES -Damd64_unknown_freebsd7_0) - -elseif (PLATFORM STREQUAL i386-unknown-nt4.0) -set (OLD_DEFINES -Di386_unknown_nt4_0) -elseif (PLATFORM STREQUAL aarch64-unknown-linux) - set (OLD_DEFINES -Daarch64_unknown_linux) -else (PLATFORM STREQUAL i386-unknown-linux2.4) - message (FATAL_ERROR "Unknown platform: ${PLATFORM}") -endif (PLATFORM STREQUAL i386-unknown-linux2.4) - -if (THREAD_DB_FOUND) -message (STATUS "-- Enabling ThreadDB support") -set (CAP_DEFINES ${CAP_DEFINES} -Dcap_thread_db) -endif (THREAD_DB_FOUND) - -set (UNIFIED_DEFINES ${CAP_DEFINES} ${BUG_DEFINES} ${ARCH_DEFINES} ${OS_DEFINES} ${OLD_DEFINES}) - -foreach (def ${UNIFIED_DEFINES}) - add_definitions (${def}) -endforeach() - - -set (CMAKE_C_FLAGS "${CMAKE_C_FLAGS} ${UNIFIED_DEF_STRING}") -set (CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} ${UNIFIED_DEF_STRING}") - -message(STATUS "Set arch and platform based definitions") - diff --git a/cmake/version.h.in b/cmake/dyninstversion.h.in similarity index 100% rename from cmake/version.h.in rename to cmake/dyninstversion.h.in diff --git a/cmake/endian.cmake b/cmake/endian.cmake deleted file mode 100644 index c0be21b772..0000000000 --- a/cmake/endian.cmake +++ /dev/null @@ -1,8 +0,0 @@ -INCLUDE(TestBigEndian) - -TEST_BIG_ENDIAN(BIGENDIAN) -if(${BIGENDIAN}) - ADD_DEFINITIONS(-DDYNINST_BIG_ENDIAN) -else() - ADD_DEFINITIONS(-DDYNINST_LITTLE_ENDIAN) -endif(${BIGENDIAN}) diff --git a/cmake/optimization.cmake b/cmake/optimization.cmake deleted file mode 100644 index 1308bbcc31..0000000000 --- a/cmake/optimization.cmake +++ /dev/null @@ -1,50 +0,0 @@ -if (CMAKE_COMPILER_IS_GNUCXX - OR ${CMAKE_C_COMPILER_ID} MATCHES Clang - OR ${CMAKE_C_COMPILER_ID} MATCHES GNU - OR ${CMAKE_C_COMPILER_ID} MATCHES Intel) -if(ENABLE_LTO) - set(LTO_FLAGS "-flto") - set(LTO_LINK_FLAGS "-fuse-ld=gold") -else() - set(LTO_FLAGS "") - set(LTO_LINK_FLAGS "") -endif() -set (CMAKE_C_FLAGS_DEBUG "-Og -g3") -set (CMAKE_CXX_FLAGS_DEBUG "-Og -g3") - -set (CMAKE_C_FLAGS_RELEASE "-O2 ${LTO_FLAGS}") -set (CMAKE_CXX_FLAGS_RELEASE "-O2 ${LTO_FLAGS}") - -set (CMAKE_C_FLAGS_RELWITHDEBINFO "-O2 -g3 ${LTO_FLAGS}") -set (CMAKE_CXX_FLAGS_RELWITHDEBINFO "-O2 -g3 ${LTO_FLAGS}") - -set (FORCE_FRAME_POINTER "-fno-omit-frame-pointer") -# Ensure each library is fully linked -set (CMAKE_SHARED_LINKER_FLAGS "${CMAKE_SHARED_LINKER_FLAGS} -Wl,--no-undefined") - -set (CMAKE_SHARED_LINKER_FLAGS "${CMAKE_SHARED_LINKER_FLAGS} ${LTO_LINK_FLAGS}") -set (CMAKE_MODULE_LINKER_FLAGS "${CMAKE_MODULE_LINKER_FLAGS} ${LTO_LINK_FLAGS}") -else (MSVC) -if(ENABLE_LTO) - set(LTO_FLAGS "/GL") - set(LTO_LINK_FLAGS "/LTCG") -else() - set(LTO_FLAGS "") - set(LTO_LINK_FLAGS "") -endif() -set (CMAKE_C_FLAGS_DEBUG "/MP /Od /Zi /MDd /D_DEBUG") -set (CMAKE_CXX_FLAGS_DEBUG "/MP /Od /Zi /MDd /D_DEBUG") - -set (CMAKE_C_FLAGS_RELEASE "/MP /O2 /MD /D NDEBUG ${LTO_FLAGS}") -set (CMAKE_CXX_FLAGS_RELEASE "/MP /O2 /MD /D NDEBUG ${LTO_FLAGS}") - -set (CMAKE_C_FLAGS_RELWITHDEBINFO "/MP /O2 /Zi /MD /D NDEBUG ${LTO_FLAGS}") -set (CMAKE_CXX_FLAGS_RELWITHDEBINFO "/MP /O2 /Zi /MD /D NDEBUG ${LTO_FLAGS}") - -set (FORCE_FRAME_POINTER "/Oy-") - -set (CMAKE_SHARED_LINKER_FLAGS "${CMAKE_SHARED_LINKER_FLAGS} ${LTO_LINK_FLAGS}") -set (CMAKE_MODULE_LINKER_FLAGS "${CMAKE_MODULE_LINKER_FLAGS} ${LTO_LINK_FLAGS}") -set (CMAKE_STATIC_LINKER_FLAGS "${CMAKE_STATIC_LINKER_FLAGS} ${LTO_LINK_FLAGS}") -endif() -message(STATUS "Set optimization flags") diff --git a/cmake/options.cmake b/cmake/options.cmake deleted file mode 100644 index 1f46d90df2..0000000000 --- a/cmake/options.cmake +++ /dev/null @@ -1,31 +0,0 @@ -# Use OpenMP? -option (USE_OpenMP "Use OpenMP for parallel parsing" ON) - -# Use SymtabAPI or SymLite? -option (LIGHTWEIGHT_SYMTAB "Use lightweight symtab interface for ParseAPI, ProcControl, and Stackwalker; disables DyninstAPI build" OFF) - -# Use ParseAPI analysis in Stackwalker? -option (SW_ANALYSIS_STEPPER "Use ParseAPI-based analysis stepper in Stackwalker" ON) - -option (BUILD_TARBALLS "Build Dyninst package tarballs. Requires git archive, tar, gzip." OFF) -option (BUILD_RTLIB_32 "Build 32-bit runtime library on mixed 32/64 systems" OFF) - -option(BUILD_RTLIB "Building runtime library (can be disabled safely for component-level builds)" ON) -option(BUILD_DOCS "Build manuals from LaTeX sources" ON) - -option (ENABLE_LTO "Enable Link-Time Optimization" OFF) - -option(ENABLE_DEBUGINFOD "Enable debuginfod support" OFF) - -# Some global on/off switches -if (LIGHTWEIGHT_SYMTAB) -add_definitions (-DWITHOUT_SYMTAB_API -DWITH_SYMLITE) -else() -add_definitions (-DWITH_SYMTAB_API -DWITHOUT_SYMLITE) -endif() - -if (SW_ANALYSIS_STEPPER) -add_definitions (-DUSE_PARSE_API) -endif() - -message(STATUS "Options set") diff --git a/cmake/platform.cmake b/cmake/platform.cmake deleted file mode 100644 index 02627009dc..0000000000 --- a/cmake/platform.cmake +++ /dev/null @@ -1,5 +0,0 @@ -if (UNIX) -include (${DYNINST_ROOT}/cmake/platform_unix.cmake) -else () -include (${DYNINST_ROOT}/cmake/platform_windows.cmake) -endif() diff --git a/cmake/platform_unix.cmake b/cmake/platform_unix.cmake deleted file mode 100644 index fa48b98678..0000000000 --- a/cmake/platform_unix.cmake +++ /dev/null @@ -1,40 +0,0 @@ -set (PLATFORM $ENV{PLATFORM}) -message(STATUS "-- Input platform: ${PLATFORM}") -set (VALID_PLATFORMS - amd64-unknown-freebsd7.2 - i386-unknown-freebsd7.2 - i386-unknown-linux2.4 - ppc32_linux - ppc64_linux - x86_64-unknown-linux2.4 - aarch64-unknown-linux - ) - -if (NOT PLATFORM) -set (INVALID_PLATFORM true) -else() -list (FIND VALID_PLATFORMS ${PLATFORM} PLATFORM_FOUND) - if (PLATFORM_FOUND EQUAL -1) - set (INVALID_PLATFORM true) - endif() -endif() - - -execute_process (COMMAND ${DYNINST_ROOT}/scripts/sysname OUTPUT_VARIABLE SYSNAME_OUT) -string(REPLACE "\n" "" SYSPLATFORM ${SYSNAME_OUT}) - -if (INVALID_PLATFORM) -# Try to set it automatically -execute_process (COMMAND ${DYNINST_ROOT}/scripts/dynsysname ${SYSNAME_OUT} - OUTPUT_VARIABLE DYNSYSNAME_OUT - ) -string (REPLACE "\n" "" PLATFORM ${DYNSYSNAME_OUT}) -message (STATUS "-- Attempting to automatically identify platform: ${PLATFORM}") -endif() - -list (FIND VALID_PLATFORMS ${PLATFORM} PLATFORM_FOUND) - -if (PLATFORM_FOUND EQUAL -1) -message (FATAL_ERROR "Error: unknown platform ${PLATFORM}; please set the PLATFORM environment variable to one of the following options: ${VALID_PLATFORMS}") -endif() - diff --git a/cmake/platform_windows.cmake b/cmake/platform_windows.cmake deleted file mode 100644 index dd03b4ebbb..0000000000 --- a/cmake/platform_windows.cmake +++ /dev/null @@ -1 +0,0 @@ -set (PLATFORM i386-unknown-nt4.0) diff --git a/cmake/shared.cmake b/cmake/shared.cmake deleted file mode 100644 index 77ef83499a..0000000000 --- a/cmake/shared.cmake +++ /dev/null @@ -1,131 +0,0 @@ -set (DYNINST_MAJOR_VERSION 11) -set (DYNINST_MINOR_VERSION 0) -set (DYNINST_PATCH_VERSION 1) - -set (SOVERSION "${DYNINST_MAJOR_VERSION}.${DYNINST_MINOR_VERSION}") -set (LIBVERSION "${SOVERSION}.${DYNINST_PATCH_VERSION}") -set (DYNINST_VERSION "${LIBVERSION}") - -if(CMAKE_CONFIGURATION_TYPES) - set(CMAKE_CONFIGURATION_TYPES Debug Release) - set(CMAKE_CONFIGURATION_TYPES "${CMAKE_CONFIGURATION_TYPES}" CACHE STRING - "Reset the available configurations to exclude MinSizeRel and RelWithDebugInfo" FORCE) -endif() - -if (LIGHTWEIGHT_SYMTAB) - set(SYMREADER symLite) -else() - set(SYMREADER symtabAPI) -endif() - -# Link libraries privately when possible -function (target_link_private_libraries target) - if(${CMAKE_VERSION} VERSION_LESS "2.8.7") - target_link_libraries (${target} ${ARGN}) - else() - target_link_libraries (${target} LINK_PRIVATE ${ARGN}) - endif() -endfunction () - -set(ALL_DYNINST_TARGETS "" CACHE INTERNAL "") - -function (dyninst_library target) - add_library (${target} ${SRC_LIST}) - # add boost as a universal dependencies for all sub libraries - if(TARGET boost) - add_dependencies (${target} boost) - endif() - target_link_private_libraries (${target} ${ARGN}) - FILE (GLOB headers "h/*.h" "${CMAKE_CURRENT_BINARY_DIR}/h/*.h") - set (ACTUAL_TARGETS ${target}) - set (ALL_TARGETS "${ARGN};${target}") - if(${ENABLE_STATIC_LIBS}) - set (ACTUAL_TARGETS ${ACTUAL_TARGETS} ${target}_static) - add_library (${target}_static STATIC ${SRC_LIST}) - endif() - message(STATUS "Building ${ACTUAL_TARGETS}...") - set_target_properties (${ACTUAL_TARGETS} PROPERTIES PUBLIC_HEADER "${headers}") - set_target_properties (${ACTUAL_TARGETS} PROPERTIES LIBRARY_OUTPUT_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}) - set_target_properties (${target} PROPERTIES SOVERSION ${SOVERSION} VERSION ${LIBVERSION} CLEAN_DIRECT_OUTPUT 1) - set (INSTALL_TARGETS ${ACTUAL_TARGETS}) - foreach (dep ${ARGN}) - message(STATUS "Processing dependent target ${dep}...") - if(TARGET ${dep}) - get_target_property(dep_dir ${dep} LIBRARY_OUTPUT_DIRECTORY) - if(EXISTS ${dep_dir} AND IS_DIRECTORY ${dep_dir}) - message(STATUS "Found dependency location ${dep_dir}") - install(SCRIPT ${dep_dir}/cmake_install.cmake) - endif() - endif() - endforeach() - install (TARGETS ${INSTALL_TARGETS} - EXPORT ${target}Targets - COMPONENT ${target} - RUNTIME DESTINATION ${INSTALL_LIB_DIR} - LIBRARY DESTINATION ${INSTALL_LIB_DIR} - ARCHIVE DESTINATION ${INSTALL_LIB_DIR} - PUBLIC_HEADER DESTINATION ${INSTALL_INCLUDE_DIR}) - add_custom_target(${target}-install - DEPENDS ${target} - COMMAND "${CMAKE_COMMAND}" -P "${CMAKE_CURRENT_BINARY_DIR}/cmake_install.cmake" - ) - set(ALL_DYNINST_TARGETS "${ALL_DYNINST_TARGETS};${target}" CACHE INTERNAL "") - install (EXPORT ${target}Targets - DESTINATION "${INSTALL_CMAKE_DIR}") - configure_file("${DYNINST_ROOT}/cmake/${PROJECT_NAME}Config.cmake.in" "${PROJECT_BINARY_DIR}/${CMAKE_FILES_DIRECTORY}/${PROJECT_NAME}Config.cmake" @ONLY) - configure_file("${DYNINST_ROOT}/cmake/${PROJECT_NAME}ConfigVersion.cmake.in" "${PROJECT_BINARY_DIR}/${CMAKE_FILES_DIRECTORY}/${PROJECT_NAME}ConfigVersion.cmake" @ONLY) - install (FILES - "${PROJECT_BINARY_DIR}/${CMAKE_FILES_DIRECTORY}/${PROJECT_NAME}Config.cmake" - "${PROJECT_BINARY_DIR}${CMAKE_FILES_DIRECTORY}/${PROJECT_NAME}ConfigVersion.cmake" - DESTINATION "${INSTALL_CMAKE_DIR}") -endfunction() - - -include (${DYNINST_ROOT}/cmake/platform.cmake) -include (${DYNINST_ROOT}/cmake/cap_arch_def.cmake) -include (${DYNINST_ROOT}/cmake/visibility.cmake) -include (${DYNINST_ROOT}/cmake/warnings.cmake) -include (${DYNINST_ROOT}/cmake/options.cmake) -include (${DYNINST_ROOT}/cmake/optimization.cmake) -include (${DYNINST_ROOT}/cmake/endian.cmake) - -set (BUILD_SHARED_LIBS ON) - -set (INSTALL_BIN_DIR bin CACHE PATH "Installation directory for executables") -set (INSTALL_LIB_DIR lib CACHE PATH "Installation directory for libraries") -set (INSTALL_INCLUDE_DIR include CACHE PATH "Installation directory for header files") -set (INSTALL_CMAKE_DIR lib/cmake/${PROJECT_NAME} CACHE PATH "Installation directory for CMake files") -set (INSTALL_DOC_DIR share/doc CACHE PATH "Installation directory for manuals") - -# Make the above absolute paths if necessary -foreach (p BIN LIB INCLUDE CMAKE) - set (var INSTALL_${p}_DIR) - if (NOT IS_ABSOLUTE "${${var}}") - set (${var} "${CMAKE_INSTALL_PREFIX}/${${var}}") - endif() -endforeach() - -if(PLATFORM MATCHES nt OR PLATFORM MATCHES windows) - add_definitions(-DWIN32_LEAN_AND_MEAN) - if (CMAKE_C_COMPILER_VERSION VERSION_GREATER 19) - add_definitions(-D_SILENCE_STDEXT_HASH_DEPRECATION_WARNINGS=1) - else() - add_definitions(-Dsnprintf=_snprintf) - endif() -endif() - -# -# DyninstConfig.cmake - -file (RELATIVE_PATH REL_INCLUDE_DIR "${INSTALL_CMAKE_DIR}" "${INSTALL_INCLUDE_DIR}") - -# For the install tree -set (CONF_INCLUDE_DIRS "\${DYNINST_CMAKE_DIR}/${REL_INCLUDE_DIR}") - -# set default configuration type - -if (NOT CMAKE_BUILD_TYPE) - set (CMAKE_BUILD_TYPE RelWithDebInfo CACHE STRING - "Choose the build type (None, Debug, Release, RelWithDebInfo, MinSizeRel)" FORCE) -endif() - diff --git a/cmake/tpls/DyninstElfUtils.cmake b/cmake/tpls/DyninstElfUtils.cmake new file mode 100644 index 0000000000..ff1275f30e --- /dev/null +++ b/cmake/tpls/DyninstElfUtils.cmake @@ -0,0 +1,59 @@ +#================================================================ +# +# Configure elfutils +# +# ---------------------------------------- +# +# ElfUtils_ROOT_DIR - Location of elfutils installation +# +# The individual find-modules use the _ROOT convention +# as the first location to search for the package. If the user +# specifies ElfUtils_ROOT_DIR, we override the _ROOT +# values and require that each package ignores system directories. +# In effect, this forces the package search to find only +# candidates in _ROOT or CMAKE_PREFIX_PATH. +# +#================================================================ + +include_guard(GLOBAL) + +# elfutils is only available on Unixes; provide a dummy target on other platforms +if(NOT UNIX) + if(NOT TARGET Dyninst::ElfUtils) + add_library(Dyninst::ElfUtils INTERFACE) + endif() + return() +endif() + +# We need >=0.186 because of NVIDIA line map extensions +set(_min_version 0.186) + +if(ENABLE_DEBUGINFOD) + set(_components debuginfod) +endif() + +if(ElfUtils_ROOT_DIR) + set(ElfUtils_NO_SYSTEM_PATHS ON) +endif() + +# If Dyninst::ElfUtils target already exists (created by rocprofiler-systems build), +# skip find_package since dependencies are being built from source +if(TARGET Dyninst::ElfUtils) + message(STATUS "Using pre-configured Dyninst::ElfUtils target (building from source)") + return() +endif() + +find_package(Elfutils ${_min_version} REQUIRED COMPONENTS ${_components}) +unset(_components) + +if(NOT TARGET Dyninst::ElfUtils) + add_library(Dyninst::ElfUtils INTERFACE IMPORTED) + target_include_directories(Dyninst::ElfUtils SYSTEM INTERFACE ${Elfutils_INCLUDE_DIRS}) + target_link_libraries(Dyninst::ElfUtils INTERFACE Elfutils::Elfutils) + if(ENABLE_DEBUGINFOD) + set_property( + TARGET Dyninst::ElfUtils + APPEND + PROPERTY INTERFACE_COMPILE_DEFINITIONS DEBUGINFOD_LIB) + endif() +endif() diff --git a/cmake/tpls/DyninstLibIberty.cmake b/cmake/tpls/DyninstLibIberty.cmake new file mode 100644 index 0000000000..f4612acecd --- /dev/null +++ b/cmake/tpls/DyninstLibIberty.cmake @@ -0,0 +1,49 @@ +#================================================================ +# +# Configure libiberty +# +# ---------------------------------------- +# +# LibIberty_ROOT_DIR - Location of libiberty installation +# +# The individual find-modules use the _ROOT convention +# as the first location to search for the package. If the user +# specifies LibIberty_ROOT_DIR, we override the _ROOT +# values and require that each package ignores system directories. +# In effect, this forces the package search to find only +# candidates in _ROOT or CMAKE_PREFIX_PATH. +# +#================================================================ + +include_guard(GLOBAL) + +# libiberty is only available on Unixes; provide a dummy target on other platforms +if(NOT UNIX) + if(NOT TARGET Dyninst::LibIberty) + add_library(Dyninst::LibIberty INTERFACE) + endif() + return() +endif() + +if(LibIberty_ROOT_DIR) + set(LibIberty_NO_SYSTEM_PATHS ON) + mark_as_advanced(LibIberty_NO_SYSTEM_PATHS) + set(LibIberty_ROOT ${LibIberty_ROOT_DIR}) + mark_as_advanced(LibIberty_ROOT) +endif() + +# If Dyninst::LibIberty target already exists (created by rocprofiler-systems build), +# skip find_package since dependencies are being built from source +if(TARGET Dyninst::LibIberty) + message(STATUS "Using pre-configured Dyninst::LibIberty target (building from source)") + return() +endif() + +find_package(LibIberty REQUIRED) + +if(NOT TARGET Dyninst::LibIberty) + add_library(Dyninst::LibIberty INTERFACE IMPORTED) + target_include_directories(Dyninst::LibIberty SYSTEM + INTERFACE ${LibIberty_INCLUDE_DIRS}) + target_link_libraries(Dyninst::LibIberty INTERFACE LibIberty::LibIberty) +endif() diff --git a/cmake/tpls/DyninstOpenMP.cmake b/cmake/tpls/DyninstOpenMP.cmake new file mode 100644 index 0000000000..8c9a050d11 --- /dev/null +++ b/cmake/tpls/DyninstOpenMP.cmake @@ -0,0 +1,10 @@ +include_guard(GLOBAL) + +if(USE_OpenMP) + find_package(OpenMP REQUIRED) +else() + # Dummy targets so we don't have to check 'USE_OpenMP' everywhere + add_library(OpenMP::OpenMP_C INTERFACE IMPORTED) + add_library(OpenMP::OpenMP_CXX INTERFACE IMPORTED) + add_library(OpenMP::OpenMP_Fortran INTERFACE IMPORTED) +endif() diff --git a/cmake/tpls/DyninstTBB.cmake b/cmake/tpls/DyninstTBB.cmake new file mode 100644 index 0000000000..357ca0f0d7 --- /dev/null +++ b/cmake/tpls/DyninstTBB.cmake @@ -0,0 +1,59 @@ +#===================================================== +# +# Configure Intel's Threading Building Blocks +# +# ---------------------------------------- +# +# TBB_ROOT_DIR - Directory hint for TBB installation +# +# The individual find-modules use the _ROOT convention +# as the first location to search for the package. If the user +# specifies TBB_ROOT_DIR, we override the _ROOT +# values and require that each package ignores system directories. +# In effect, this forces the package search to find only +# candidates in _ROOT or CMAKE_PREFIX_PATH. +# +#===================================================== + +include_guard(GLOBAL) + +# Minimum supported version +set(_min_version 2019.9) + +if(TBB_ROOT_DIR) + set(TBB_ROOT ${TBB_ROOT_DIR}) + mark_as_advanced(TBB_ROOT) + set(_find_path_args NO_CMAKE_SYSTEM_PATH NO_SYSTEM_ENVIRONMENT_PATH) +endif() + +# If Dyninst::TBB target already exists (created by rocprofiler-systems build), +# skip find_package since dependencies are being built from source +if(TARGET Dyninst::TBB) + message(STATUS "Using pre-configured Dyninst::TBB target (building from source)") + return() +endif() + +find_package( + TBB ${_min_version} + COMPONENTS tbb tbbmalloc tbbmalloc_proxy + REQUIRED ${_find_path_args}) + +# Don't let TBB variables seep through +mark_as_advanced(TBB_DIR) + +if(NOT TARGET Dyninst::TBB) + add_library(Dyninst::TBB INTERFACE IMPORTED) + target_link_libraries(Dyninst::TBB INTERFACE TBB::tbb TBB::tbbmalloc + TBB::tbbmalloc_proxy) + target_include_directories( + Dyninst::TBB SYSTEM + INTERFACE $ + $ + $) +endif() + +message(STATUS "Found TBB ${TBB_VERSION}") +get_target_property(_tmp TBB::tbb INTERFACE_INCLUDE_DIRECTORIES) +message(STATUS "TBB include directories: ${_tmp}") + +unset(_find_path_args) diff --git a/cmake/tpls/DyninstThread_DB.cmake b/cmake/tpls/DyninstThread_DB.cmake new file mode 100644 index 0000000000..4c1688d1b6 --- /dev/null +++ b/cmake/tpls/DyninstThread_DB.cmake @@ -0,0 +1,37 @@ +#================================================================ +# +# Configure libthread_db +# +# ---------------------------------------- +# +# thread_db is provided by glibc, so there is no hint variable +# +#================================================================ + +include_guard(GLOBAL) + +# thread_db is only available on Unixes; provide a dummy target on other platforms +if(NOT UNIX) + if(NOT TARGET Dyninst::Thread_DB) + add_library(Dyninst::Thread_DB INTERFACE) + endif() + return() +endif() + +find_package(Thread_DB) + +# It's not required, so just make a dummy target if not found +if(NOT Thread_DB_FOUND) + if(NOT TARGET Dyninst::Thread_DB) + add_library(Dyninst::Thread_DB INTERFACE IMPORTED) + endif() + return() +endif() + +if(NOT TARGET Dyninst::Thread_DB) + add_library(Dyninst::Thread_DB INTERFACE IMPORTED) + target_include_directories(Dyninst::Thread_DB SYSTEM + INTERFACE ${Thread_DB_INCLUDE_DIRS}) + target_link_libraries(Dyninst::Thread_DB INTERFACE Thread_DB::Thread_DB) + target_compile_definitions(Dyninst::Thread_DB INTERFACE cap_thread_db) +endif() diff --git a/cmake/tpls/DyninstThreads.cmake b/cmake/tpls/DyninstThreads.cmake new file mode 100644 index 0000000000..124338b418 --- /dev/null +++ b/cmake/tpls/DyninstThreads.cmake @@ -0,0 +1,12 @@ +include_guard(GLOBAL) + +if(DYNINST_OS_UNIX) + set(_required REQUIRED) +endif() + +find_package(Threads ${_required}) + +if(NOT Threads_FOUND) + # make a dummy + add_library(Threads::Threads INTERFACE) +endif() diff --git a/cmake/tpls/DyninstValgrind.cmake b/cmake/tpls/DyninstValgrind.cmake new file mode 100644 index 0000000000..667545c36c --- /dev/null +++ b/cmake/tpls/DyninstValgrind.cmake @@ -0,0 +1,41 @@ +#================================================================ +# +# Configure valgrind +# +# ---------------------------------------- +# +# Valgrind_ROOT_DIR - Directory hint for valgrind installation +# +# The individual find-modules use the _ROOT convention +# as the first location to search for the package. If the user +# specifies Valgrind_ROOT_DIR, we override the _ROOT +# values and require that each package ignores system directories. +# In effect, this forces the package search to find only +# candidates in _ROOT or CMAKE_PREFIX_PATH. +# +#================================================================ + +include_guard(GLOBAL) + +# valgrind is only available on Unixes; provide a dummy target on other platforms +if(NOT UNIX OR NOT ADD_VALGRIND_ANNOTATIONS) + if(NOT TARGET Dyninst::Valgrind) + add_library(Dyninst::Valgrind INTERFACE IMPORTED) + endif() + return() +endif() + +if(Valgrind_ROOT_DIR) + set(Valgrind_NO_SYSTEM_PATHS ON) + mark_as_advanced(Valgrind_NO_SYSTEM_PATHS) + set(Valgrind_ROOT ${Valgrind_ROOT_DIR}) + mark_as_advanced(Valgrind_ROOT) +endif() + +find_package(Valgrind REQUIRED) + +if(NOT TARGET Dyninst::Valgrind) + add_library(Dyninst::Valgrind INTERFACE IMPORTED) + target_include_directories(Dyninst::Valgrind SYSTEM INTERFACE ${Valgrind_INCLUDE_DIRS}) + target_compile_definitions(Dyninst::Valgrind INTERFACE ENABLE_VG_ANNOTATIONS) +endif() diff --git a/cmake/visibility.cmake b/cmake/visibility.cmake deleted file mode 100644 index e9935e0041..0000000000 --- a/cmake/visibility.cmake +++ /dev/null @@ -1,5 +0,0 @@ -if(CMAKE_COMPILER_IS_GNUCXX OR ${CMAKE_C_COMPILER_ID} MATCHES Clang) - set (CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -fvisibility=hidden") - set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -fvisibility=hidden -fvisibility-inlines-hidden") - message(STATUS "Found g++, enabling -fvisibility=hidden") -endif() diff --git a/cmake/warnings.cmake b/cmake/warnings.cmake deleted file mode 100644 index 6927782b16..0000000000 --- a/cmake/warnings.cmake +++ /dev/null @@ -1,143 +0,0 @@ -# Frame sizes are larger for debug build, so adjust based on build type -# files with functions containing large frames are adjust below -# (the value could be made significantly maller if more files are adjusted). -# -set(defaultDebugMaxFrameSize 24576) -set(defaultNonDebugMaxFrameSize 20480) - - -# REQUESTED_WARNING_FLAGS is a list of warning flags for C and C++ programs -# to enable if supported by the compiler. The values do not include the -# the initial '-' - -list(APPEND REQUESTED_WARNING_FLAGS - Wall - Wextra - Wpedantic - - Walloca - Wcast-align - Wcast-qual - Wcomma-subscript - Wctor-dtor-privacy - Wdeprecated-copy-dtor - Wdouble-promotion - Wduplicated-branches - Wduplicated-cond - Wenum-conversion - Wextra-semi - Wfloat-equal - Wformat-overflow=2 - Wformat-signedness - Wformat=2 - Wframe-larger-than=${defaultNonDebugMaxFrameSize} - Wjump-misses-init - Wlogical-op - Wmismatched-tags - Wmissing-braces - Wmultichar - Wnoexcept - Wnon-virtual-dtor - Woverloaded-virtual - Wpointer-arith - Wrange-loop-construct - Wrestrict - Wshadow - Wstrict-null-sentinel - Wsuggest-attribute=format - Wsuggest-attribute=malloc - Wuninitialized - Wvla - Wvolatile - Wwrite-strings - ) - -#list(APPEND REQUESTED_WARNING_FLAGS Werror) - -#list(APPEND REQUESTED_WARNING_FLAGS Wredundant-tags) -#list(APPEND REQUESTED_WARNING_FLAGS Wnull-dereference) -#list(APPEND REQUESTED_WARNING_FLAGS Wconversion) -#list(APPEND REQUESTED_WARNING_FLAGS Wzero-as-null-pointer-constant) -#list(APPEND REQUESTED_WARNING_FLAGS Wuseless-cast) -#list(APPEND REQUESTED_WARNING_FLAGS Wsuggest-override) -#list(APPEND REQUESTED_WARNING_FLAGS Wsuggest-final-types) -#list(APPEND REQUESTED_WARNING_FLAGS Wsuggest-final-methods) -#list(APPEND REQUESTED_WARNING_FLAGS Wsign-promo) -#list(APPEND REQUESTED_WARNING_FLAGS Wold-style-cast) -#list(APPEND REQUESTED_WARNING_FLAGS Walloc-zero) - -if (CMAKE_C_COMPILER_ID MATCHES "^(GNU|Clang)$") - include(CheckCCompilerFlag) - foreach (f IN LISTS REQUESTED_WARNING_FLAGS) - string(REGEX REPLACE "[^a-zA-Z0-9]" "_" v "HAS_C_FLAG_${f}") - set(CMAKE_REQUIRED_FLAGS "-${f}") - check_c_source_compiles("int main(){return 0;}" "${v}" FAIL_REGEX "warning: *command[- ]line option|-Wunknown-warning-option") - # Previous two lines are equivalent to below, but also catches - # a 0 exit status with a warning message output: - # check_c_compiler_flag("-${f}" "${v}") - if (${v}) - string(APPEND SUPPORTED_C_WARNING_FLAGS " -${f}") - if (f MATCHES "^(.*)=[0-9]+$") - # set generic variable if warning is parameterized with a number - string(REGEX REPLACE "[^a-zA-Z0-9]" "_" v "HAS_C_FLAG_${CMAKE_MATCH_1}") - set("${v}" 1) - endif() - endif() - endforeach() -endif() - -if (CMAKE_CXX_COMPILER_ID MATCHES "^(GNU|Clang)$") - include(CheckCXXCompilerFlag) - foreach (f IN LISTS REQUESTED_WARNING_FLAGS) - string(REGEX REPLACE "[^a-zA-Z0-9]" "_" v "HAS_CPP_FLAG_${f}") - set(CMAKE_REQUIRED_FLAGS "-${f}") - check_cxx_source_compiles("int main(){return 0;}" "${v}" FAIL_REGEX "warning: *command[- ]line option|-Wunknown-warning-option") - if (${v}) - string(APPEND SUPPORTED_CXX_WARNING_FLAGS " -${f}") - if (f MATCHES "^(.*)=[0-9]+$") - string(REGEX REPLACE "[^a-zA-Z0-9]" "_" v "HAS_CPP_FLAG_${CMAKE_MATCH_1}") - set("${v}" 1) - endif() - endif() - endforeach() -endif() - -# If -Wframe-larger-than is available adjust the value to allow for larger -# frames based on compiler version and build type for the following two files: -# -# instructionAPI/src/InstructionDecoder-power.C -# (includes instructionAPI/src/InstructionDecoder-power.C) -# common/src/MachSyscall.C -# (includes common/src/SyscallInformation.C) -# -if (HAS_CPP_FLAG_Wframe_larger_than) - # Override the default frame size maximum for DEBUG (-O0) build types - # as there stack frames are larger: - # - add_compile_options($<$:-Wframe-larger-than=${defaultDebugMaxFrameSize}>) - - # Use worst-case values discovered so far. For most gcc versions - # SyscallInformation.C stack frame size is less than than the default and - # InstructionDecoder-power.C is less than 76800, but for some environments - # and compiler configurations the following are needed: - # - set(debugMaxFrameSizeOverrideSyscallInformation 81920) - set(debugMaxFrameSizeOverridePowerOpcodeTable 358400) - if (${CMAKE_CXX_COMPILER_VERSION} MATCHES "^[7](\.|$)") - set(nonDebugMaxFrameSizeOverridePowerOpcodeTable 38912) - endif() -endif() - -unset(CMAKE_REQUIRED_FLAGS) - -if (MSVC) - message(STATUS "TODO: Set up custom warning flags for MSVC") - string(APPEND CMAKE_C_FLAGS "/wd4251 /wd4091 /wd4503") - string(APPEND CMAKE_CXX_FLAGS "/wd4251 /wd4091 /wd4503") -endif() - -message(STATUS "Using C warning flags: ${SUPPORTED_C_WARNING_FLAGS}") -message(STATUS "Using CXX warning flags: ${SUPPORTED_CXX_WARNING_FLAGS}") -message(STATUS "Extra CXX DEBUG warning flags: -Wframe-larger-than=${defaultDebugMaxFrameSize}") -set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} ${SUPPORTED_C_WARNING_FLAGS}") -set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} ${SUPPORTED_CXX_WARNING_FLAGS}") diff --git a/common/CMakeLists.txt b/common/CMakeLists.txt index 2310d2625a..5301d07bec 100644 --- a/common/CMakeLists.txt +++ b/common/CMakeLists.txt @@ -1,148 +1,178 @@ -# CMake configuration for common directory - -if(NOT WIN32) -include_directories ( - ${PROJECT_SOURCE_DIR}/common/h - ${PROJECT_SOURCE_DIR}/common/src - ) -else() -include_directories ( - ${PROJECT_SOURCE_DIR}/common/h # don't include common/src; anything from there can still collide with default includes. - # stupid Windows case-insensitive naming. - ) -endif() - - -set (SRC_LIST +include_guard(GLOBAL) + +include(DyninstLibrary) + +configure_file(${PROJECT_SOURCE_DIR}/cmake/dyninstversion.h.in + ${CMAKE_CURRENT_SOURCE_DIR}/h/dyninstversion.h) + +set(_public_headers + h/Annotatable.h + h/Architecture.h + h/Buffer.h + h/compiler_annotations.h + h/compiler_diagnostics.h + h/concurrent.h + h/DynAST.h + h/dyn_regs.h + h/dyn_syscalls.h + h/dyntypes.h + h/Edge.h + h/entryIDs.h + h/Graph.h + h/IBSTree-fast.h + h/IBSTree.h + h/MachSyscall.h + h/mnemonics/aarch64_entryIDs.h + h/mnemonics/ppc_entryIDs.h + h/mnemonics/x86_entryIDs.h + h/mnemonics/AMDGPU/gfx908_entryIDs.h + h/mnemonics/AMDGPU/gfx90a_entryIDs.h + h/mnemonics/AMDGPU/gfx940_entryIDs.h + h/mnemonics/IntelGPU/generic_entryIDs.h + h/mnemonics/NVIDIA/generic_entryIDs.h + h/Node.h + h/ProcReader.h + h/registers/MachRegister.h + h/registers/aarch64_regs.h + h/registers/abstract_regs.h + h/registers/AMDGPU/amdgpu_gfx908_regs.h + h/registers/AMDGPU/amdgpu_gfx90a_regs.h + h/registers/AMDGPU/amdgpu_gfx940_regs.h + h/registers/cuda_regs.h + h/registers/MachRegister.h + h/registers/ppc32_regs.h + h/registers/ppc64_regs.h + h/registers/reg_def.h + h/registers/x86_64_regs.h + h/registers/x86_regs.h + h/SymReader.h + h/unaligned_memory_access.h + h/util.h + h/VariableLocation.h + h/dyninstversion.h # generated by cmake/version.h.in at config time + ) + +set(_private_headers + src/addrtranslate.h + src/addrtranslate-sysv.h + src/arch-aarch64.h + src/arch.h + src/arch-power.h + src/arch-x86.h + src/debug_common.h + src/dthread.h + src/dyn_register.h + src/freebsdHeaders.h + src/freebsdKludges.h + src/headers.h + src/ia32_locations.h + src/IntervalTree.h + src/linuxHeaders.h + src/linuxKludges.h + src/lprintf.h + src/lru_cache.h + src/MappedFile.h + src/NodeIterator.h + src/ntHeaders.h + src/parseauxv.h + src/pathName.h + src/pool_allocators.h + src/registers/MachRegister.C + src/sha1.h + src/singleton_object_pool.h + src/stats.h + src/symbolDemangle.h + src/symbolDemangleWithCache.h + src/Timer.h + src/vgannotations.h + src/vm_maps.h) + +set(_sources src/pfq-rwlock.C src/concurrent.C - src/Timer.C - src/Types.C + src/Timer.C src/lprintf.C - src/pathName.C - src/stats.C - src/Annotatable.C - src/MappedFile.C - src/sha1.C + src/pathName.C + src/stats.C + src/Annotatable.C + src/MappedFile.C + src/sha1.C src/util.C - src/Node.C - src/Graph.C - src/Edge.C - src/DOT.C - src/dyn_regs.C - src/AST.C - src/addrtranslate.C - src/arch-x86.C - src/arch-power.C - src/arch-aarch64.C - src/debug_common.C - src/VariableLocation.C + src/Node.C + src/Graph.C + src/Edge.C + src/DOT.C + src/dyn_regs.C + src/AST.C + src/addrtranslate.C + src/arch-x86.C + src/arch-power.C + src/arch-aarch64.C + src/debug_common.C + src/VariableLocation.C src/Buffer.C - src/MachSyscall.C - ) - -set (C_SRC_LIST -) + src/MachSyscall.C) -if (PLATFORM MATCHES freebsd) - set (SRC_LIST ${SRC_LIST} - src/freebsdKludges.C - src/addrtranslate-sysv.C - src/addrtranslate-freebsd.C - src/symbolDemangleWithCache.C - ) - set (C_SRC_LIST ${C_SRC_LIST} - src/symbolDemangle.c - ) +if(DYNINST_OS_UNIX) + list(APPEND _sources src/addrtranslate-sysv.C src/symbolDemangleWithCache.C + src/symbolDemangle.c) endif() -if (PLATFORM MATCHES linux) - set (SRC_LIST ${SRC_LIST} - src/linuxKludges.C - src/parseauxv.C - src/addrtranslate-sysv.C - src/addrtranslate-auxv.C - src/addrtranslate-linux.C - src/symbolDemangleWithCache.C - ) - set (C_SRC_LIST ${C_SRC_LIST} - src/symbolDemangle.c - ) +if(DYNINST_OS_FreeBSD) + list(APPEND _sources src/freebsdKludges.C src/addrtranslate-freebsd.C) +elseif(DYNINST_OS_Linux) + list(APPEND _sources src/linuxKludges.C src/parseauxv.C src/addrtranslate-auxv.C + src/addrtranslate-linux.C) +elseif(DYNINST_OS_Windows) + list(APPEND _sources src/ntKludges.C src/addrtranslate-win.C) endif() -if (PLATFORM MATCHES cnl) - set (SRC_LIST ${SRC_LIST} - src/linuxKludges.C - src/parseauxv.C - src/addrtranslate-sysv.C - src/addrtranslate-auxv.C - src/addrtranslate-linux.C - ) -endif() - -if (PLATFORM MATCHES nt OR PLATFORM MATCHES windows) - set (SRC_LIST ${SRC_LIST} - src/ntKludges.C -# src/dthread-win.C -# src/dthread.C - src/addrtranslate-win.C - ) - add_definitions(-DWIN32 -D_WIN32_WINNT=0x500) -endif() - - -SET_SOURCE_FILES_PROPERTIES(${SRC_LIST} PROPERTIES LANGUAGE CXX) -SET_SOURCE_FILES_PROPERTIES(${C_SRC_LIST} PROPERTIES LANGUAGE C) -set (SRC_LIST ${SRC_LIST} - ${C_SRC_LIST} -) - -if (${CMAKE_CXX_COMPILER_ID} MATCHES "GNU") - if (${CMAKE_CXX_COMPILER_VERSION} MATCHES "^[789](\.|$)") - # Disable var-tracking-assignments for arch-x86.C for gcc 7, 8, & 9. - # The default max size for these compilers is too small so it fails, - # adjusting it using - # - # PROPERTIES COMPILE_FLAGS "--param=max-vartrack-size=600000000" - # - # succeeds, but just disable it. - SET_SOURCE_FILES_PROPERTIES(src/arch-x86.C - PROPERTIES COMPILE_FLAGS "-fno-var-tracking-assignments") - endif() +if(${CMAKE_CXX_COMPILER_ID} MATCHES "GNU") + if(${CMAKE_CXX_COMPILER_VERSION} MATCHES "^[789](\.|$)") + # Disable var-tracking-assignments for arch-x86.C for gcc 7, 8, & 9. The default + # max size for these compilers is too small so it fails, adjusting it using + # + # PROPERTIES COMPILE_FLAGS "--param=max-vartrack-size=600000000" + # + # succeeds, but just disable it. + set_source_files_properties(src/arch-x86.C PROPERTIES COMPILE_FLAGS + "-fno-var-tracking-assignments") + endif() endif() # adjust warning threshold if set in cmake/warnings.cmake -if (debugMaxFrameSizeOverrideSyscallInformation) - SET_SOURCE_FILES_PROPERTIES(src/MachSyscall.C PROPERTIES COMPILE_FLAGS - $<$:-Wframe-larger-than=${debugMaxFrameSizeOverrideSyscallInformation}>) -endif() -if (nonDebugMaxFrameSizeOverrideSyscallInformation) - SET_SOURCE_FILES_PROPERTIES(src/MachSyscall.C PROPERTIES COMPILE_FLAGS - $<$>:-Wframe-larger-than=${nonDebugMaxFrameSizeOverrideSyscallInformation}>) +if(debugMaxFrameSizeOverrideSyscallInformation) + set_source_files_properties( + src/MachSyscall.C + PROPERTIES + COMPILE_FLAGS + $<$:-Wframe-larger-than=${debugMaxFrameSizeOverrideSyscallInformation}> + ) endif() - -ADD_DEFINITIONS(-DCOMMON_LIB) - -dyninst_library(common) - -if(TARGET LibIberty) - add_dependencies(common LibIberty) - target_link_libraries(common PRIVATE LibIberty) - - if(${ENABLE_STATIC_LIBS}) - target_link_libraries(common_static PRIVATE LibIberty) - endif() +if(nonDebugMaxFrameSizeOverrideSyscallInformation) + set_source_files_properties( + src/MachSyscall.C + PROPERTIES + COMPILE_FLAGS + $<$>:-Wframe-larger-than=${nonDebugMaxFrameSizeOverrideSyscallInformation}> + ) endif() -if(TARGET TBB) - add_dependencies(common TBB) -endif() -if(PLATFORM MATCHES nt OR PLATFORM MATCHES windows) - target_link_private_libraries(common Psapi WS2_32 dbghelp) -endif() -target_link_private_libraries(common ${Boost_LIBRARIES}) -target_link_libraries(common PUBLIC ${TBB_LIBRARIES}) +# cmake-format: off +dyninst_library( + common + PUBLIC_HEADER_FILES ${_public_headers} + PRIVATE_HEADER_FILES ${_private_headers} + SOURCE_FILES ${_sources} + DEFINES COMMON_LIB + PUBLIC_DEPS Dyninst::TBB + PRIVATE_DEPS Dyninst::LibIberty OpenMP::OpenMP_CXX Dyninst::Valgrind Threads::Threads +) +# cmake-format: on -if(USE_OpenMP) - set_target_properties(common PROPERTIES COMPILE_FLAGS ${OpenMP_CXX_FLAGS} LINK_FLAGS ${OpenMP_CXX_FLAGS}) +if(DYNINST_OS_Windows) + foreach(t ${common_TARGETS}) + target_compile_definitions(${t} PRIVATE "WIN32" "_WIN32_WINNT=0x500") + target_link_libraries(${t} PRIVATE Psapi WS2_32 dbghelp) + endforeach() endif() diff --git a/common/doc/manual_frontpage.tex b/common/doc/manual_frontpage.tex index e61d3c6246..7a8302dbb5 100644 --- a/common/doc/manual_frontpage.tex +++ b/common/doc/manual_frontpage.tex @@ -42,9 +42,9 @@ % }; \node [anchor=west,font=\sffamily] (rel1) at ($(origin)+(0.75in,-5.0in)$) - {\fontsize{24}{32}\selectfont 11.0 Release}; + {\fontsize{24}{32}\selectfont 13.0 Release}; \node [anchor=west,font=\sffamily] (rel2) at ($(rel1.west)+(0in,-32pt)$) - {\fontsize{24}{32}\selectfont April 2021}; + {\fontsize{24}{32}\selectfont February 2024}; % Contact information % \matrix (UWaddress) [% diff --git a/common/h/Annotatable.h b/common/h/Annotatable.h index 1f4f4b9d36..b5bc5cea14 100644 --- a/common/h/Annotatable.h +++ b/common/h/Annotatable.h @@ -35,6 +35,7 @@ #define DYN_DETAIL_BOOST_NO_INTRINSIC_WCHAR_T 1 #endif #include "dyntypes.h" +#include #include #include #include @@ -351,8 +352,6 @@ class COMMON_EXPORT AnnotatableSparse #if defined (_MSC_VER) typedef dyn_hash_map annos_by_type_t; -#pragma warning (push) -#pragma warning (disable:4251) #else typedef dyn_hash_map annos_by_type_t; #endif @@ -391,7 +390,6 @@ class COMMON_EXPORT AnnotatableSparse // set up to minimize search time, not deletion time. It could // be changed if this becomes a significant time drain. - unsigned int n = 0; for (unsigned int i = 0; i < getAnnos()->size(); ++i) { annos_by_type_t *abt = (*getAnnos())[i]; @@ -409,7 +407,6 @@ class COMMON_EXPORT AnnotatableSparse } abt->erase(iter); - n++; // get rid of this check... just making sure that erase is behaving as // expected... @@ -748,8 +745,4 @@ class COMMON_EXPORT AnnotatableSparse } // namespace -#ifdef _MSC_VER -#pragma warning(pop) -#endif - #endif diff --git a/common/h/Architecture.h b/common/h/Architecture.h new file mode 100644 index 0000000000..137e740650 --- /dev/null +++ b/common/h/Architecture.h @@ -0,0 +1,74 @@ +/* + * See the dyninst/COPYRIGHT file for copyright information. + * + * We provide the Paradyn Tools (below described as "Paradyn") + * on an AS IS basis, and do not warrant its validity or performance. + * We reserve the right to update, modify, or discontinue this + * software at any time. We shall have no obligation to supply such + * updates or modifications or any other form of support to you. + * + * By your use of Paradyn, you understand and agree that we (or any + * other person or entity with proprietary rights in Paradyn) are + * under no obligation to provide either maintenance services, + * update services, notices of latent defects, or correction of + * defects for Paradyn. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef DYNINST_ARCHITECTURE_H +#define DYNINST_ARCHITECTURE_H + +#include + +namespace Dyninst { + + // 0xff000000 is used to encode architecture + typedef enum { + Arch_none = 0x00000000, + Arch_x86 = 0x14000000, + Arch_x86_64 = 0x18000000, + Arch_ppc32 = 0x24000000, + Arch_ppc64 = 0x28000000, + Arch_aarch32 = 0x44000000, // for later use + Arch_aarch64 = 0x48000000, + Arch_cuda = 0x88000000, + Arch_amdgpu_gfx908 = 0x94000000, // future support for gfx908 + Arch_amdgpu_gfx90a = 0x98000000, // future support for gfx90a + Arch_amdgpu_gfx940 = 0x9c000000, // future support for gfx940 + Arch_intelGen9 = 0xb6000000 // same as machine no. retrevied from eu-readelf + } Architecture; + + inline unsigned getArchAddressWidth(Architecture arch) { + switch(arch) { + case Arch_none: return 0; + case Arch_x86: + case Arch_ppc32: return 4; + case Arch_x86_64: + case Arch_ppc64: + case Arch_aarch64: + case Arch_cuda: + case Arch_intelGen9: + case Arch_amdgpu_gfx908: + case Arch_amdgpu_gfx90a: + case Arch_amdgpu_gfx940: return 8; + default: assert(0); return 0; + } + return 0; + } + +} + +#endif diff --git a/common/h/Buffer.h b/common/h/Buffer.h index c9b405d029..ef425abc5d 100644 --- a/common/h/Buffer.h +++ b/common/h/Buffer.h @@ -34,7 +34,7 @@ #include #include "util.h" #include "dyntypes.h" - +#include "unaligned_memory_access.h" namespace Dyninst { // A class to support multiple forms of code generation. The design of this class is as @@ -75,6 +75,7 @@ class COMMON_EXPORT Buffer { public: iterator() : pos((storage *)-1) {} ~iterator() {} + iterator(const iterator&) = default; storage operator*() const { assert(valid); return *pos; @@ -150,8 +151,7 @@ template if (size_ + sizeof(i) >= max_) { increase_allocation(sizeof(i)); } - Input *ptr = (Input *)cur_ptr(); - *ptr = i; + write_memory_as(cur_ptr(), i); size_ += sizeof(i); } diff --git a/common/h/DynAST.h b/common/h/DynAST.h index c0b4bf5c6e..c32127c6cf 100644 --- a/common/h/DynAST.h +++ b/common/h/DynAST.h @@ -31,13 +31,14 @@ #if !defined(AST_H) #define AST_H +#include #include #include #include #include #include #include "util.h" -#include "boost/enable_shared_from_this.hpp" +#include "dyncompat/enable_shared_from_this.hpp" namespace Dyninst { @@ -88,7 +89,7 @@ class ASTVisitor; #define DEF_AST_LEAF_TYPE(name, type) \ class name : public AST { \ public: \ - typedef boost::shared_ptr Ptr; \ + typedef dyncompat::shared_ptr Ptr; \ static Ptr create(type t) { return Ptr(new name(t)); } \ virtual ~name() {} \ virtual const std::string format() const { \ @@ -99,7 +100,7 @@ class name : public AST { \ virtual AST::Ptr accept(ASTVisitor *v) { return v->visit(this); } \ virtual ID getID() const { return V_##name; } \ static Ptr convert(AST::Ptr a) { \ - return ((a->getID() == V_##name) ? boost::static_pointer_cast(a) : Ptr()); \ + return ((a->getID() == V_##name) ? dyncompat::static_pointer_cast(a) : Ptr()); \ } \ const type &val() const { return t_; } \ private: \ @@ -114,7 +115,7 @@ class name : public AST { \ #define DEF_AST_INTERNAL_TYPE(name, type) \ class name : public AST { \ public: \ - typedef boost::shared_ptr Ptr; \ + typedef dyncompat::shared_ptr Ptr; \ virtual ~name() {} \ static Ptr create(type t, AST::Ptr a) { return Ptr(new name(t, a)); } \ static Ptr create(type t, AST::Ptr a, AST::Ptr b) { return Ptr(new name(t, a, b)); } \ @@ -134,7 +135,7 @@ class name : public AST { \ virtual AST::Ptr accept(ASTVisitor *v) { return v->visit(this); } \ virtual ID getID() const { return V_##name; } \ static Ptr convert(AST::Ptr a) { \ - return ((a->getID() == V_##name) ? boost::static_pointer_cast(a) : Ptr()); \ + return ((a->getID() == V_##name) ? dyncompat::static_pointer_cast(a) : Ptr()); \ } \ const type &val() const { return t_; } \ void setChild(int i, AST::Ptr a) { kids_[i] = a; } \ @@ -162,7 +163,7 @@ class name : public AST { \ Children kids_; \ } \ -class COMMON_EXPORT AST : public boost::enable_shared_from_this { +class COMMON_EXPORT AST : public dyncompat::enable_shared_from_this { public: // This is a global list of all AST types, including those that are not @@ -185,7 +186,7 @@ class COMMON_EXPORT AST : public boost::enable_shared_from_this { V_YicesAST, V_SemanticsAST } ID; - typedef boost::shared_ptr Ptr; + typedef dyncompat::shared_ptr Ptr; typedef std::vector Children; AST() {} @@ -235,7 +236,7 @@ class COMMON_EXPORT AST : public boost::enable_shared_from_this { class COMMON_EXPORT ASTVisitor { public: - typedef boost::shared_ptr ASTPtr; + typedef dyncompat::shared_ptr ASTPtr; virtual ASTPtr visit(AST *) {return AST::Ptr();} virtual ASTPtr visit(DataflowAPI::BottomAST *) {return AST::Ptr();} diff --git a/common/h/Edge.h b/common/h/Edge.h index b6c5898f4f..78baaa88f3 100644 --- a/common/h/Edge.h +++ b/common/h/Edge.h @@ -31,8 +31,9 @@ #if !defined(EDGE_H) #define EDGE_H -#include "boost/shared_ptr.hpp" -#include "boost/weak_ptr.hpp" +#include "dyncompat/shared_ptr.hpp" +#include "dyncompat/weak_ptr.hpp" +#include #include #include "Annotatable.h" #include @@ -46,7 +47,7 @@ class COMMON_EXPORT Edge : public AnnotatableSparse { friend class Graph; friend class Creator; public: - typedef boost::shared_ptr Ptr; + typedef dyncompat::shared_ptr Ptr; struct EdgePtrHasher { size_t operator() (const Ptr &e) const noexcept { return (size_t)e.get(); @@ -55,8 +56,8 @@ class COMMON_EXPORT Edge : public AnnotatableSparse { private: - typedef boost::shared_ptr NodeSharedPtr; - typedef boost::weak_ptr NodePtr; + typedef dyncompat::shared_ptr NodeSharedPtr; + typedef dyncompat::weak_ptr NodePtr; public: diff --git a/common/h/FileType b/common/h/FileType deleted file mode 100644 index e69de29bb2..0000000000 diff --git a/common/h/Graph.h b/common/h/Graph.h index d6c94c5a79..8a8ee4e8be 100644 --- a/common/h/Graph.h +++ b/common/h/Graph.h @@ -35,7 +35,8 @@ #define GRAPH_H #include "dyntypes.h" -#include "boost/shared_ptr.hpp" +#include "dyncompat/shared_ptr.hpp" +#include #include #include #include @@ -46,9 +47,6 @@ #include "Annotatable.h" #include "Node.h" -#if defined(_MSC_VER) -#pragma warning(disable:4251) -#endif namespace Dyninst { class Edge; @@ -65,14 +63,14 @@ class COMMON_EXPORT Graph : public AnnotatableSparse { protected: - typedef boost::shared_ptr NodePtr; - typedef boost::shared_ptr EdgePtr; + typedef dyncompat::shared_ptr NodePtr; + typedef dyncompat::shared_ptr EdgePtr; typedef std::unordered_set NodeSet; typedef std::unordered_map NodeMap; public: - typedef boost::shared_ptr Ptr; + typedef dyncompat::shared_ptr Ptr; // Interface class for predicate-based searches. Users // can inherit this class to specify the functor to use @@ -80,7 +78,7 @@ class COMMON_EXPORT Graph : public AnnotatableSparse { class NodePredicate { public: - typedef boost::shared_ptr Ptr; + typedef dyncompat::shared_ptr Ptr; virtual ~NodePredicate() {} virtual bool predicate(const NodePtr &node) = 0; static Ptr getPtr(NodePredicate *p) { diff --git a/common/h/IBSTree-fast.h b/common/h/IBSTree-fast.h index 6d0d98d177..54723cf847 100644 --- a/common/h/IBSTree-fast.h +++ b/common/h/IBSTree-fast.h @@ -31,19 +31,10 @@ #if !defined(IBSTREE_FAST_H) #define IBSTREE_FAST_H #include "IBSTree.h" -#include -#include -#include -#include -#include -#include -#include -#include -#include +#include +#include #include -#include "concurrent.h" - namespace Dyninst { @@ -56,14 +47,22 @@ namespace Dyninst public: typedef typename ITYPE::type interval_type; - IBSTree overlapping_intervals; - typedef boost::multi_index_container > - > > interval_set; + struct interval_by_high { + using is_transparent = void; + + bool operator()(const ITYPE* lhs, const ITYPE* rhs) const + { + if (lhs->high() != rhs->high()) return lhs->high() < rhs->high(); + if (lhs->low() != rhs->low()) return lhs->low() < rhs->low(); + return lhs < rhs; + } - //typedef std::set > interval_set; + bool operator()(const ITYPE* lhs, interval_type rhs) const { return lhs->high() < rhs; } + bool operator()(interval_type lhs, const ITYPE* rhs) const { return lhs < rhs->high(); } + }; + + IBSTree overlapping_intervals; + typedef std::set interval_set; interval_set unique_intervals; IBSTree_fast() @@ -140,8 +139,14 @@ namespace Dyninst dyn_rwlock::unique_lock l(rwlock); overlapping_intervals.remove(entry); - typename interval_set::iterator found = unique_intervals.find(entry->high()); - if(found != unique_intervals.end() && *found == entry) unique_intervals.erase(found); + auto found = unique_intervals.lower_bound(entry->high()); + while (found != unique_intervals.end() && (*found)->high() == entry->high()) { + if (*found == entry) { + unique_intervals.erase(found); + break; + } + ++found; + } } template int IBSTree_fast::find(interval_type X, std::set &results) const @@ -168,7 +173,7 @@ namespace Dyninst int num_overlapping = overlapping_intervals.find(I, results); if(num_overlapping) return num_overlapping; typename interval_set::const_iterator lb = unique_intervals.upper_bound(I->low()); - typename interval_set::iterator ub = lb; + typename interval_set::const_iterator ub = lb; while(ub != unique_intervals.end() && (*ub)->low() < I->high()) { results.insert(*ub); diff --git a/common/h/IBSTree.h b/common/h/IBSTree.h index c5a01c0d6e..f3eab38dcb 100644 --- a/common/h/IBSTree.h +++ b/common/h/IBSTree.h @@ -41,6 +41,8 @@ #include "dyntypes.h" #include "concurrent.h" +#include +#include #include #include #include @@ -100,9 +102,9 @@ class SimpleInterval virtual T high() const { return high_; } virtual U id() const { return id_; } protected: - T low_; - T high_; - U id_; // some arbitrary unique identifier + T low_{}; + T high_{}; + U id_{}; // some arbitrary unique identifier }; template @@ -184,7 +186,7 @@ class IBSTree { private: /** size of tree **/ - boost::atomic treeSize; + dyncompat::atomic treeSize; /** pointer to the tree root **/ IBSNode *root; diff --git a/common/h/Initial b/common/h/Initial deleted file mode 100644 index e69de29bb2..0000000000 diff --git a/common/h/MachSyscall.h b/common/h/MachSyscall.h index 9b1f8d156a..9a1262f065 100644 --- a/common/h/MachSyscall.h +++ b/common/h/MachSyscall.h @@ -2,9 +2,10 @@ #define MACH_SYSCALL_H_ #include -#include "boost/shared_ptr.hpp" +#include "dyncompat/shared_ptr.hpp" -#include "dyn_regs.h" +#include "Architecture.h" +#include "registers/MachRegister.h" #include "dyntypes.h" namespace Dyninst { @@ -34,7 +35,7 @@ namespace ProcControlAPI class Process; MachSyscall makeFromEvent(const EventSyscall * ev); - MachSyscall makeFromID(boost::shared_ptr proc, unsigned long id); + MachSyscall makeFromID(dyncompat::shared_ptr proc, unsigned long id); } class COMMON_EXPORT MachSyscall @@ -49,7 +50,7 @@ class COMMON_EXPORT MachSyscall friend MachSyscall ProcControlAPI::makeFromEvent(const ProcControlAPI::EventSyscall *); // Allows users to construct a MachSyscall - friend MachSyscall ProcControlAPI::makeFromID(boost::shared_ptr, SyscallIDIndependent); + friend MachSyscall ProcControlAPI::makeFromID(dyncompat::shared_ptr, SyscallIDIndependent); static MachSyscall makeFromPlatform(Platform, SyscallIDIndependent); diff --git a/common/h/Node.h b/common/h/Node.h index 6b0dbb595c..c20457a4a6 100644 --- a/common/h/Node.h +++ b/common/h/Node.h @@ -33,15 +33,14 @@ #include #include +#include +#include #include "Edge.h" #include "Annotatable.h" #include "dyntypes.h" -#include "boost/shared_ptr.hpp" +#include "dyncompat/shared_ptr.hpp" -#if defined(_MSC_VER) -#pragma warning(disable:4251) -#endif class BPatch_function; class BPatch_basicBlock; @@ -57,12 +56,12 @@ class COMMON_EXPORT Node { friend class Edge; friend class Graph; - typedef boost::shared_ptr EdgePtr; - typedef boost::shared_ptr GraphPtr; + typedef dyncompat::shared_ptr EdgePtr; + typedef dyncompat::shared_ptr GraphPtr; typedef std::unordered_set EdgeSet; public: - typedef boost::shared_ptr Ptr; + typedef dyncompat::shared_ptr Ptr; struct NodePtrHasher { size_t operator() (const Ptr &n) const noexcept { return (size_t)n.get(); @@ -117,7 +116,7 @@ class COMMON_EXPORT Node { class COMMON_EXPORT PhysicalNode : public Node { public: - typedef boost::shared_ptr Ptr; + typedef dyncompat::shared_ptr Ptr; static Node::Ptr createNode(Address addr); @@ -142,7 +141,7 @@ class COMMON_EXPORT VirtualNode : public Node { friend class Graph; public: - typedef boost::shared_ptr Ptr; + typedef dyncompat::shared_ptr Ptr; static Node::Ptr createNode(); static Node::Ptr createNode(std::string name); diff --git a/common/h/Others b/common/h/Others deleted file mode 100644 index e69de29bb2..0000000000 diff --git a/common/h/ProcReader.h b/common/h/ProcReader.h index 4a633c054b..87b1896ed7 100644 --- a/common/h/ProcReader.h +++ b/common/h/ProcReader.h @@ -32,7 +32,7 @@ #define PROCREADER_H_ #include "dyntypes.h" -#include "dyn_regs.h" +#include "registers/MachRegister.h" namespace Dyninst { diff --git a/common/h/SymReader.h b/common/h/SymReader.h index d5bcbf04d1..e0cfa9a124 100644 --- a/common/h/SymReader.h +++ b/common/h/SymReader.h @@ -32,8 +32,9 @@ #include "dyntypes.h" #include "util.h" -#include "dyn_regs.h" #include +#include +#include "Architecture.h" namespace Dyninst { diff --git a/common/h/VariableLocation.h b/common/h/VariableLocation.h index fefd1caa98..d443507fca 100644 --- a/common/h/VariableLocation.h +++ b/common/h/VariableLocation.h @@ -31,7 +31,7 @@ #if !defined(_Variable_Location_h_) #define _Variable_Location_h_ -#include "dyn_regs.h" +#include "registers/MachRegister.h" #include "dyntypes.h" #include "util.h" diff --git a/common/h/aarch64_sys_regs.h b/common/h/aarch64_sys_regs.h deleted file mode 100644 index 7925de6ad0..0000000000 --- a/common/h/aarch64_sys_regs.h +++ /dev/null @@ -1,427 +0,0 @@ -// -// Created by ssunny on 4/4/16. -// - -#ifndef DYNINST_AARCH64_SYS_REGS_H -#define DYNINST_AARCH64_SYS_REGS_H - -DEF_REGISTER(tlbi_vale3is, 0 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(id_aa64pfr1_el1, 1 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(sder32_el3, 2 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(icc_ctlr_el3, 3 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dacr32_el2, 4 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(ich_vtr_el2, 5 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(icc_dir_el1, 6 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(tlbi_ipas2le1, 7 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(afsr0_el3, 9 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dczid_el0, 10 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(actlr_el1, 11 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(sctlr_el3, 12 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(sctlr_el2, 13 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(at_s1e2r, 14 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(ic_iallu, 15 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(icc_igrpen1_el3, 16 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmceid0_el0, 17 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(tpidr_el0, 18 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(tlbi_ipas2le1is, 19 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(contextidr_el1, 20 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(id_mmfr2_el1, 21 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmevtyper0_el0, 22 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmevtyper1_el0, 23 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmevtyper2_el0, 24 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmevtyper3_el0, 25 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmevtyper4_el0, 26 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmevtyper5_el0, 27 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmevtyper6_el0, 28 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmevtyper7_el0, 29 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmevtyper8_el0, 30 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmevtyper9_el0, 31 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmevtyper10_el0, 32 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmevtyper11_el0, 33 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmevtyper12_el0, 34 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmevtyper13_el0, 35 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmevtyper14_el0, 36 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmevtyper15_el0, 37 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmevtyper16_el0, 38 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmevtyper17_el0, 39 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmevtyper18_el0, 40 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmevtyper19_el0, 41 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmevtyper20_el0, 42 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmevtyper21_el0, 43 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmevtyper22_el0, 44 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmevtyper23_el0, 45 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmevtyper24_el0, 46 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmevtyper25_el0, 47 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmevtyper26_el0, 48 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmevtyper27_el0, 49 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmevtyper28_el0, 50 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmevtyper29_el0, 51 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmevtyper30_el0, 52 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(mair_el1, 53 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(tlbi_vale2is, 54 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(ccsidr_el1, 55 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(spsr_irq, 56 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(elr_el3, 57 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(tlbi_alle3is, 58 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(sp_el0, 59 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(id_mmfr1_el1, 60 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(ic_ivau, 61 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(icc_eoir0_el1, 62 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(icc_sgi0r_el1, 63 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(icc_sgi1r_el1, 64 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(tlbi_vae2, 65 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(cntp_ctl_el0, 66 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(tpidr_el1, 67 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dc_civac, 68 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(tlbi_ipas2e1is, 69 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(cntv_cval_el0, 70 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(icc_bpr0_el1, 71 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(mdccsr_el0, 72 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dbgclaimset_el1, 73 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(ich_ap0r0_el2, 74 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(ich_ap0r1_el2, 75 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(ich_ap0r2_el2, 76 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(ich_ap0r3_el2, 77 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dc_ivac, 78 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(ich_elrsr_el2, 79 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(ich_hcr_el2, 80 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(vbar_el2, 81 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(icc_asgi1r_el1, 82 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(id_aa64afr1_el1, 83 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(nzcv, 84 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(ttbr0_el1, 85 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(actlr_el3, 86 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(mdrar_el1, 87 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(rmr_el3, 88 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(cntkctl_el1, 89 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(rvbar_el3, 90 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(id_dfr0_el1, 91 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(at_s1e1r, 92 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(icc_ap1r0_el1, 93 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(icc_ap1r1_el1, 94 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(icc_ap1r2_el1, 95 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(icc_ap1r3_el1, 96 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(icc_pmr_el1, 97 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmceid1_el0, 98 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dc_csw, 99 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(id_pfr1_el1, 100 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(id_afr0_el1, 101 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(amair_el2, 102 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmovsset_el0, 103 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(tlbi_vmalle1, 104 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(tlbi_vale2, 105 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(at_s12e0w, 106 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(id_isar5_el1, 107 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(tcr_el1, 108 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmevcntr0_el0, 109 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmevcntr1_el0, 110 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmevcntr2_el0, 111 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmevcntr3_el0, 112 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmevcntr4_el0, 113 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmevcntr5_el0, 114 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmevcntr6_el0, 115 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmevcntr7_el0, 116 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmevcntr8_el0, 117 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmevcntr9_el0, 118 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmevcntr10_el0, 119 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmevcntr11_el0, 120 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmevcntr12_el0, 121 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmevcntr13_el0, 122 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmevcntr14_el0, 123 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmevcntr15_el0, 124 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmevcntr16_el0, 125 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmevcntr17_el0, 126 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmevcntr18_el0, 127 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmevcntr19_el0, 128 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmevcntr20_el0, 129 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmevcntr21_el0, 130 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmevcntr22_el0, 131 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmevcntr23_el0, 132 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmevcntr24_el0, 133 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmevcntr25_el0, 134 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmevcntr26_el0, 135 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmevcntr27_el0, 136 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmevcntr28_el0, 137 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmevcntr29_el0, 138 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmevcntr30_el0, 139 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dbgdtr_el0, 140 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(amair_el3, 141 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(rvbar_el1, 142 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dc_cvau, 143 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(afsr0_el2, 144 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(icc_iar0_el1, 145 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(icc_bpr1_el1, 146 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dc_cisw, 147 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(hpfar_el2, 148 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(spsr_abt, 149 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(csselr_el1, 150 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmintenclr_el1, 151 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(tlbi_vaae1, 152 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(far_el2, 153 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(currentel, 154 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dbgprcr_el1, 155 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(tlbi_ipas2e1, 156 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(mair_el3, 157 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(ttbr1_el1, 158 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(cntvct_el0, 159 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(tlbi_aside1is, 160 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(scr_el3, 161 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(mvfr0_el1, 162 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(tlbi_alle1, 163 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmovsclr_el0, 164 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(mvfr1_el1, 165 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(tlbi_vaale1, 166 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(elr_el1, 167 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(rvbar_el2, 168 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(esr_el1, 169 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(tlbi_aside1, 170 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(osdtrrx_el1, 171 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmcntenset_el0, 172 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dspsr_el0, 173 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dc_zva, 174 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(ich_misr_el2, 175 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(vbar_el1, 176 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(id_isar1_el1, 177 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(cpacr_el1, 178 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(par_el1, 179 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(cnthp_ctl_el2, 180 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(actlr_el2, 181 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(spsr_fiq, 182 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(id_aa64pfr0_el1, 183 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(tpidr_el3, 184 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(at_s1e2w, 185 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(tlbi_alle2, 186 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(id_isar4_el1, 187 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dbgvcr32_el2, 188 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(hcr_el2, 189 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(ich_eisr_el2, 190 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(mdccint_el1, 191 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dlr_el0, 192 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(tpidr_el2, 193 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmuserenr_el0, 194 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(oseccr_el1, 195 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(tlbi_vmalls12e1is, 196 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(mdscr_el1, 197 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(ich_vmcr_el2, 198 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(far_el3, 199 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(spsr_el2, 200 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(oslsr_el1, 201 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(tlbi_vae1, 202 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(daif, 203 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(far_el1, 204 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(hstr_el2, 205 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(clidr_el1, 206 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(vttbr_el2, 207 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(id_aa64afr0_el1, 208 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(icc_rpr_el1, 209 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(cntps_ctl_el1, 210 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(afsr1_el1, 211 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(spsel, 212 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmcr_el0, 214 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(tlbi_vaae1is, 215 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(icc_sre_el1, 216 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(cntpct_el0, 217 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(tlbi_alle2is, 218 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(icc_igrpen1_el1, 219 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(ifsr32_el2, 220 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(icc_igrpen0_el1, 221 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(tpidrro_el0, 222 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(hacr_el2, 223 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(at_s1e0w, 224 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmccfiltr_el0, 225 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(cnthp_tval_el2, 226 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(at_s12e0r, 227 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(cntvoff_el2, 228 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(icc_sre_el2, 229 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(spsr_el1, 230 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(isr_el1, 231 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(cnthctl_el2, 232 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(vtcr_el2, 233 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(vmpidr_el2, 234 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmswinc_el0, 235 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(id_mmfr0_el1, 236 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(cntp_cval_el0, 237 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(icc_hppir0_el1, 238 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(mdcr_el3, 239 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dbgwvr0_el1, 240 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dbgwvr1_el1, 241 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dbgwvr2_el1, 242 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dbgwvr3_el1, 243 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dbgwvr4_el1, 244 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dbgwvr5_el1, 245 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dbgwvr6_el1, 246 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dbgwvr7_el1, 247 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dbgwvr8_el1, 248 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dbgwvr9_el1, 249 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dbgwvr10_el1, 250 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dbgwvr11_el1, 251 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dbgwvr12_el1, 252 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dbgwvr13_el1, 253 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dbgwvr14_el1, 254 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dbgwvr15_el1, 255 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dbgauthstatus_el1, 256 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dbgdtrtx_el0, 257 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(icc_eoir1_el1, 258 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(elr_el2, 259 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dbgbvr0_el1, 260 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dbgbvr1_el1, 261 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dbgbvr2_el1, 262 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dbgbvr3_el1, 263 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dbgbvr4_el1, 264 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dbgbvr5_el1, 265 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dbgbvr6_el1, 266 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dbgbvr7_el1, 267 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dbgbvr8_el1, 268 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dbgbvr9_el1, 269 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dbgbvr10_el1, 270 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dbgbvr11_el1, 271 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dbgbvr12_el1, 272 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dbgbvr13_el1, 273 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dbgbvr14_el1, 274 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dbgbvr15_el1, 275 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(ic_ialluis, 276 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(tcr_el3, 277 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(aidr_el1, 278 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(cntfrq_el0, 279 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(tlbi_vae3, 280 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(tlbi_vmalls12e1, 281 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(esr_el2, 282 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(vbar_el3, 283 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dbgwcr0_el1, 284 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dbgwcr1_el1, 285 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dbgwcr2_el1, 286 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dbgwcr3_el1, 287 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dbgwcr4_el1, 288 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dbgwcr5_el1, 289 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dbgwcr6_el1, 290 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dbgwcr7_el1, 291 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dbgwcr8_el1, 292 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dbgwcr9_el1, 293 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dbgwcr10_el1, 294 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dbgwcr11_el1, 295 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dbgwcr12_el1, 296 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dbgwcr13_el1, 297 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dbgwcr14_el1, 298 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dbgwcr15_el1, 299 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(rmr_el1, 300 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(midr_el1, 301 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dc_isw, 302 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(id_isar0_el1, 303 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(ctr_el0, 304 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(sp_el1, 305 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(cntv_tval_el0, 306 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(tlbi_vae3is, 307 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(afsr1_el3, 308 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(id_mmfr4_el1, 309 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(ttbr0_el3, 310 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(spsr_und, 311 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(tlbi_vae2is, 312 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(at_s1e3w, 313 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(osdlr_el1, 314 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(ich_lr0_el2, 315 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(ich_lr1_el2, 316 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(ich_lr2_el2, 317 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(ich_lr3_el2, 318 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(ich_lr4_el2, 319 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(ich_lr5_el2, 320 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(ich_lr6_el2, 321 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(ich_lr7_el2, 322 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(ich_lr8_el2, 323 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(ich_lr9_el2, 324 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(ich_lr10_el2, 325 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(ich_lr11_el2, 326 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(ich_lr12_el2, 327 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(ich_lr13_el2, 328 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(ich_lr14_el2, 329 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(ich_lr15_el2, 330 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dbgclaimclr_el1, 331 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(tlbi_vmalle1is, 332 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(id_aa64mmfr1_el1, 333 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmccntr_el0, 334 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(esr_el3, 335 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(cptr_el3, 336 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(cntp_tval_el0, 337 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(tcr_el2, 338 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dc_cvac, 339 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(tlbi_vaale1is, 340 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmintenset_el1, 341 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dbgbcr0_el1, 342 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dbgbcr1_el1, 343 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dbgbcr2_el1, 344 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dbgbcr3_el1, 345 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dbgbcr4_el1, 346 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dbgbcr5_el1, 347 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dbgbcr6_el1, 348 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dbgbcr7_el1, 349 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dbgbcr8_el1, 350 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dbgbcr9_el1, 351 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dbgbcr10_el1, 352 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dbgbcr11_el1, 353 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dbgbcr12_el1, 354 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dbgbcr13_el1, 355 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dbgbcr14_el1, 356 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dbgbcr15_el1, 357 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmselr_el0, 358 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(tlbi_alle1is, 359 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(icc_hppir1_el1, 360 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(tlbi_vae1is, 361 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(mdcr_el2, 362 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(at_s12e1w, 363 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(vpidr_el2, 364 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(id_aa64dfr0_el1, 365 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(id_isar2_el1, 366 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(ttbr0_el2, 367 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(icc_ap0r0_el1, 368 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(icc_ap0r1_el1, 369 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(icc_ap0r2_el1, 370 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(icc_ap0r3_el1, 371 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(dbgdtrrx_el0, 372 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(fpexc32_el2, 373 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmxevtyper_el0, 374 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(oslar_el1, 375 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(id_pfr0_el1, 376 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(id_mmfr3_el1, 377 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(osdtrtx_el1, 378 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(id_aa64isar0_el1, 379 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(mvfr2_el1, 380 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmcntenclr_el0, 381 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(ich_ap1r0_el2, 382 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(ich_ap1r1_el2, 383 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(ich_ap1r2_el2, 384 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(ich_ap1r3_el2, 385 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(id_aa64mmfr0_el1, 386 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(tlbi_vale3, 387 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(revidr_el1, 388 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(mair_el2, 389 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(sctlr_el1, 390 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(at_s1e0r, 391 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(cptr_el2, 392 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(at_s12e1r, 393 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(pmxevcntr_el0, 394 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(afsr0_el1, 395 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(at_s1e1w, 396 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(id_isar3_el1, 397 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(afsr1_el2, 398 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(tlbi_vale1is, 399 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(sp_el2, 400 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(cntps_cval_el1, 401 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(cntps_tval_el1, 402 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(icc_ctlr_el1, 403 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(cntv_ctl_el0, 404 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(rmr_el2, 405 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(id_aa64dfr1_el1, 406 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(cnthp_cval_el2, 407 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(at_s1e3r, 408 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(id_aa64isar1_el1, 409 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(mpidr_el1, 410 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(amair_el1, 411 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(tlbi_alle3, 412 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(spsr_el3, 413 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(tlbi_vale1, 414 | FULL |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(icc_sre_el3, 415 | D_REG |SYSREG | Arch_aarch64, "aarch64"); -DEF_REGISTER(icc_iar1_el1, 416 | D_REG |SYSREG | Arch_aarch64, "aarch64"); - -DEF_REGISTER(IMPLEMENTATION_DEFINED_SYSREG, 417 | D_REG |SYSREG | Arch_aarch64, "aarch64"); - - -#endif //DYNINST_AARCH64_SYS_REGS_H diff --git a/common/h/amdgpu_op_table.h b/common/h/amdgpu_op_table.h deleted file mode 100644 index 8162eaa5a7..0000000000 --- a/common/h/amdgpu_op_table.h +++ /dev/null @@ -1,416 +0,0 @@ -amdgpu_op_v_max_i16_e64, -amdgpu_op_v_mul_lo_u16_e64, -amdgpu_op_v_max_i16, -amdgpu_op_s_lshsl2_add_u32, -amdgpu_op_s_flbit_i32_b32, -amdgpu_op_tbuffer_store_format_d16_xyzw, -amdgpu_op_s_cmpk_eq_i32, -amdgpu_op_buffer_load_format_xyzw, -amdgpu_op_v_subrev_u32_e64, -amdgpu_op_v_subrev_f16, -amdgpu_op_v_ldexp_f16, -amdgpu_op_s_load_dwordx8, -amdgpu_op_s_cmpk_lt_u32, -amdgpu_op_s_bfe_i64, -amdgpu_op_v_cmp_eq_u64_e64, -amdgpu_op_s_lshl3_add_u32, -amdgpu_op_s_sub_u32, -amdgpu_op_v_mul_u32_u24, -amdgpu_op_s_add_u32, -amdgpu_op_v_madmk_f32, -amdgpu_op_tbuffer_store_format_xyz, -amdgpu_op_v_sub_u16_e64, -amdgpu_op_s_invalid_1, -amdgpu_op_v_cvt_i32_f64_e64, -amdgpu_op_s_addc_u32, -amdgpu_op_s_pack_lh_b32_b16, -amdgpu_op_s_nor_savexec_b64, -amdgpu_op_s_sethalt, -amdgpu_op_v_cvt_flr_i32_f32_e64, -amdgpu_op_v_cvt_u32_f32, -amdgpu_op_s_quadmask_b64, -amdgpu_op_tbuffer_load_format_xyz, -amdgpu_op_s_min_i32, -amdgpu_op_s_cbranch_scc1, -amdgpu_op_s_not_b32, -amdgpu_op_s_lshl_b64, -amdgpu_op_s_invalid_2, -amdgpu_op_s_cbranch_cdbgsys, -amdgpu_op_s_cmp_ge_u32, -amdgpu_op_s_movrels_b64, -amdgpu_op_s_movrels_b32, -amdgpu_op_s_bitcmp1_b32, -amdgpu_op_s_nor_b64, -amdgpu_op_v_mul_f16, -amdgpu_op_v_interp_p2_f32, -amdgpu_op_s_cmp_lt_i32, -amdgpu_op_s_max_i32, -amdgpu_op_s_bcnt1_i32_b64, -amdgpu_op_v_xor_b32, -amdgpu_op_v_max_f16, -amdgpu_op_v_min_u16, -amdgpu_op_v_cmp_ge_u32, -amdgpu_op_v_subrev_f16_e64, -amdgpu_op_v_cmp_class_f32, -amdgpu_op_v_max_i32, -amdgpu_op_s_cbranch_execnz, -amdgpu_op_v_cmp_lt_u32_e64, -amdgpu_op_buffer_store_format_xy, -amdgpu_op_v_mul_hi_i32_i24_e64, -amdgpu_op_v_cvt_f32_f16_e64, -amdgpu_op_v_lshlrev_b32, -amdgpu_op_s_xnor_b64, -amdgpu_op_v_max_u32, -amdgpu_op_v_subrev_co_u32, -amdgpu_op_v_add_u32_e64, -amdgpu_op_v_interp_p1_f32, -amdgpu_op_v_cmp_eq_u64, -amdgpu_op_s_bitcmp0_b64, -amdgpu_op_s_bitset1_b32, -amdgpu_op_v_cmp_ge_u32_e64, -amdgpu_op_s_addk_i32, -amdgpu_op_v_add_co_u32_e64, -amdgpu_op_s_ff0_i32_b64, -amdgpu_op_s_sext_i32_i8, -amdgpu_op_v_min_f16, -amdgpu_op_s_cbranch_vccnz, -amdgpu_op_v_min_u32_e64, -amdgpu_op_v_sub_f16_e64, -amdgpu_op_v_subrev_f32_e64, -amdgpu_op_v_sub_u32_e64, -amdgpu_op_v_cmp_gt_u32_e64, -amdgpu_op_s_mov_b64, -amdgpu_op_s_load_dwordx4, -amdgpu_op_s_wakeup, -amdgpu_op_v_cndmask_b32, -amdgpu_op_v_lshrrev_b16_e64, -amdgpu_op_s_abs_i32, -amdgpu_op_s_dcache_memrealtime, -amdgpu_op_v_cmp_neq_f16, -amdgpu_op_s_cbranch_i_fork, -amdgpu_op_v_xno2_b32_e64, -amdgpu_op_s_cmpk_lg_u32, -amdgpu_op_s_cmpk_lt_i32, -amdgpu_op_v_mul_f16_e64, -amdgpu_op_s_pack_hh_b32_B16, -amdgpu_op_v_cvt_off_f32_i4, -amdgpu_op_v_ashrrev_i16_e64, -amdgpu_op_s_orn1_saveexec_b64, -amdgpu_op_v_subrev_f32, -amdgpu_op_s_cbranch_execz, -amdgpu_op_s_not_b64, -amdgpu_op_s_buffer_load_dwordx2, -amdgpu_op_tbuffer_store_format_xy, -amdgpu_op_v_addc_co_u32, -amdgpu_op_v_pack_b32_f16, -amdgpu_op_v_lshlrev_b32_e64, -amdgpu_op_s_cslect_b32, -amdgpu_op_v_min_f32_e64, -amdgpu_op_v_swap_b32, -amdgpu_op_s_subb_u32, -amdgpu_op_s_dcache_wb_vol, -amdgpu_op_s_store_dwordx2, -amdgpu_op_s_load_dword, -amdgpu_op_v_addc_co_u32_e64, -amdgpu_op_s_bfm_b64, -amdgpu_op_v_mul_legacy_f32, -amdgpu_op_s_branch, -amdgpu_op_s_absdiff_i32, -amdgpu_op_s_getpc_b64, -amdgpu_op_v_readfirstlane_b32_e64, -amdgpu_op_buffer_load_format_xy, -amdgpu_op_s_bfm_b32, -amdgpu_op_v_add_f16, -amdgpu_op_s_movk_i32, -amdgpu_op_load_dword, -amdgpu_op_v_mac_f16_e64, -amdgpu_op_buffer_atomic_dec_x2, -amdgpu_op_s_nand_savexec_b64, -amdgpu_op_s_min_u32, -amdgpu_op_s_andn1_wrexec_b64, -amdgpu_op_s_or_savexec_b64, -amdgpu_op_s_setreg_imm32_b32, -amdgpu_op_load_ubyte, -amdgpu_op_v_mul_f32, -amdgpu_op_s_waitcnt, -amdgpu_op_v_max_u32_e64, -amdgpu_op_v_max_f32_e64, -amdgpu_op_s_lshl_b32, -amdgpu_op_buffer_store_format_xyz, -amdgpu_op_s_flbit_i32_b64, -amdgpu_op_s_sext_i32_i16, -amdgpu_op_v_subb_co_u32_e64, -amdgpu_op_s_setreg_b32, -amdgpu_op_v_cvt_f64_i32_e64, -amdgpu_op_v_cvt_f32_u32, -amdgpu_op_buffer_load_format_x, -amdgpu_op_v_min_i16_e64, -amdgpu_op_v_cmp_ne_u64_e64, -amdgpu_op_s_and_saveexec_b64, -amdgpu_op_v_dot8_u32_u4, -amdgpu_op_v_madak_f32_e64, -amdgpu_op_s_mulk_i32, -amdgpu_op_s_scratch_load_dword, -amdgpu_op_s_bitreplicate_b64_b32, -amdgpu_op_s_set_gpr_idx_mode, -amdgpu_op_v_subbrev_co_u32_e64, -amdgpu_op_v_ashrrev_i32_e64, -amdgpu_op_s_cmovk_i32, -amdgpu_op_s_rfe_restore_b64, -amdgpu_op_s_sendmsghalt, -amdgpu_op_s_nop, -amdgpu_op_tbuffer_load_format_xy, -amdgpu_op_s_dcache_wb, -amdgpu_op_s_bitcmp1_b64, -amdgpu_op_buffer_store_format_xyzw, -amdgpu_op_s_load_dwordx16, -amdgpu_op_s_cmpk_eq_u32, -amdgpu_op_v_min_i32_e64, -amdgpu_op_v_cmp_class_f32_e64, -amdgpu_op_v_cmp_ge_u64, -amdgpu_op_v_cndmask_b32_e64, -amdgpu_op_v_ashrrev_i16, -amdgpu_op_v_sub_co_u32_e64, -amdgpu_op_v_sub_f32, -amdgpu_op_s_cmov_b32, -amdgpu_op_v_subrev_u16_e64, -amdgpu_op_s_cmpk_le_i32, -amdgpu_op_v_mul_hi_u32_u24, -amdgpu_op_ds_read_b128, -amdgpu_op_s_buffer_load_dword, -amdgpu_op_v_mac_b32_e64, -amdgpu_op_s_barrier, -amdgpu_op_v_cvt_i32_f64, -amdgpu_op_s_mul_hi_u32, -amdgpu_op_s_endpgm_ordered_ps_done, -amdgpu_op_v_sub_u32, -amdgpu_op_s_scratch_load_dwordx2, -amdgpu_op_s_xor_savexec_b64, -amdgpu_op_s_sendmsg, -amdgpu_op_s_cbranch_g_fork, -amdgpu_op_s_set_gpr_idx_on, -amdgpu_op_v_min_f16_e64, -amdgpu_op_s_ff0_i32_b32, -amdgpu_op_s_getreg_b32, -amdgpu_op_v_cvt_f16_f32, -amdgpu_op_s_cbranch_cdbguser, -amdgpu_op_v_add_u16_e64, -amdgpu_op_v_cvt_flr_i32_f32, -amdgpu_op_s_lshr_b64, -amdgpu_op_v_max_f32, -amdgpu_op_v_swap_b32_e64, -amdgpu_op_s_cmpk_gt_u32, -amdgpu_op_v_cvt_f32_i32_e64, -amdgpu_op_s_ff1_i32_b32, -amdgpu_op_s_endpgm_saved, -amdgpu_op_s_cbranch_scc0, -amdgpu_op_v_cmp_le_u32_e64, -amdgpu_op_v_xno2_b32, -amdgpu_op_v_cmp_eq_u32_e64, -amdgpu_op_buffer_load_format_xyz, -amdgpu_op_v_readfirstlane_b32, -amdgpu_op_s_orn2_b64, -amdgpu_op_v_cmp_ne_u64, -amdgpu_op_v_mul_lo_u16, -amdgpu_op_v_lshrrev_b32, -amdgpu_op_s_movreld_b64, -amdgpu_op_s_mul_i32, -amdgpu_op_atomic_dec_x2, -amdgpu_op_v_mul_hi_u32_u24_e64, -amdgpu_op_s_bitset0_b32, -amdgpu_op_s_endpgm, -amdgpu_op_v_mac_b32, -amdgpu_op_v_mov_b32, -amdgpu_op_v_cmp_lt_u64, -amdgpu_op_s_sleep, -amdgpu_op_s_rfe_b64, -amdgpu_op_v_lshrrev_b32_e64, -amdgpu_op_s_xor_b64, -amdgpu_op_s_sub_i32, -amdgpu_op_s_cmp_ge_eq_i32, -amdgpu_op_s_cmpk_lg_i32, -amdgpu_op_s_set_gpr_idx_idx, -amdgpu_op_v_add_f16_e64, -amdgpu_op_s_andn2_savexec_b64, -amdgpu_op_v_mad_legacy_f32, -amdgpu_op_s_cmpk_ge_u32, -amdgpu_op_ds_add_u32, -amdgpu_op_v_cvt_i32_f32_e64, -amdgpu_op_s_pack_ll_b32_b16, -amdgpu_op_s_quadmask_b32, -amdgpu_op_s_max_u32, -amdgpu_op_v_subbrev_co_u32, -amdgpu_op_s_buffer_load_dwordx4, -amdgpu_op_s_cmpk_le_u32, -amdgpu_op_v_cvt_rpi_i32_f32, -amdgpu_op_s_load_dwordx2, -amdgpu_op_s_wqm_b64, -amdgpu_op_v_min_i32, -amdgpu_op_s_swappc_b64, -amdgpu_op_s_cmpk_gt_i32, -amdgpu_op_s_brev_b64, -amdgpu_op_s_andn2_b64, -amdgpu_op_v_mul_u32_u24_e64, -amdgpu_op_s_bcnt0_i32_b32, -amdgpu_op_s_nand_b32, -amdgpu_op_v_cmp_gt_u64_e64, -amdgpu_op_s_cmp_le_i32, -amdgpu_op_v_cmp_neq_f16_e64, -amdgpu_op_v_max_i32_e64, -amdgpu_op_s_bitcmp0_b32, -amdgpu_op_v_sub_co_u32, -amdgpu_op_s_and_b32, -amdgpu_op_v_cmp_ne_u32_e64, -amdgpu_op_s_dcache_inv_vol, -amdgpu_op_v_mul_f32_e64, -amdgpu_op_s_mov_b32, -amdgpu_op_s_setpc_b64, -amdgpu_op_s_set_gpr_idx_off, -amdgpu_op_v_min_f32, -amdgpu_op_s_incperflevel, -amdgpu_op_v_min_u32, -amdgpu_op_v_cvt_i32_f32, -amdgpu_op_v_min_u16_e64, -amdgpu_op_v_add_f32, -amdgpu_op_s_bitset0_b64, -amdgpu_op_s_cmp_ge_i32, -amdgpu_op_v_mul_hi_i32_i24, -amdgpu_op_s_setkill, -amdgpu_op_s_scratch_store_dword, -amdgpu_op_v_subrev_u32, -amdgpu_op_s_brev_b32, -amdgpu_op_v_xor_b32_e64, -amdgpu_op_s_buffer_store_dwordx2, -amdgpu_op_v_cmp_le_u64, -amdgpu_op_v_cvt_f16_f32_e64, -amdgpu_op_s_icache_inv, -amdgpu_op_s_cmov_b64, -amdgpu_op_s_fltbit_i32, -amdgpu_op_v_cvt_f32_i32, -amdgpu_op_v_sub_f32_e64, -amdgpu_op_v_cmp_ge_u64_e64, -amdgpu_op_v_mov_b32_e64, -amdgpu_op_v_sub_f16, -amdgpu_op_v_min_i16, -amdgpu_op_s_xor_b32, -amdgpu_op_s_bfe_u64, -amdgpu_op_s_ashr_i32, -amdgpu_op_s_atomic_dec_x2, -amdgpu_op_s_cmp_lt_u32, -amdgpu_op_v_ashrrev_i32, -amdgpu_op_v_add_u16, -amdgpu_op_v_max_u16_e64, -amdgpu_op_s_buffer_load_dwordx8, -amdgpu_op_v_add_u32, -amdgpu_op_s_cmp_lg_u64, -amdgpu_op_v_or_b32, -amdgpu_op_v_subb_co_u32, -amdgpu_op_v_madmk_f32_e64, -amdgpu_op_s_xnor_savexec_b64, -amdgpu_op_v_lshlrev_b16, -amdgpu_op_v_cmp_gt_u32, -amdgpu_op_s_cmp_ge_eq_u32, -amdgpu_op_v_subrev_co_u32_e64, -amdgpu_op_v_cmpx_t_u64_e64, -amdgpu_op_s_ff1_i32_b64, -amdgpu_op_v_max_u16, -amdgpu_op_v_madak_f32, -amdgpu_op_store_dword, -amdgpu_op_v_cmp_lt_u32, -amdgpu_op_s_scratch_store_dwordx2, -amdgpu_op_v_cmp_le_u32, -amdgpu_op_v_cvt_f32_f16, -amdgpu_op_s_cbranch_cdbgsys_or_user, -amdgpu_op_v_add_f32_e64, -amdgpu_op_v_pk_mad_i16, -amdgpu_op_s_nor_b32, -amdgpu_op_v_madmk_f16_e64, -amdgpu_op_v_subrev_u16, -amdgpu_op_s_or_b32, -amdgpu_op_v_nop, -amdgpu_op_s_movreld_b32, -amdgpu_op_v_or_b32_e64, -amdgpu_op_v_cvt_f64_i32, -amdgpu_op_v_cmp_le_u64_e64, -amdgpu_op_s_andn2_b32, -amdgpu_op_s_dcache_inv, -amdgpu_op_s_wqm_b32, -amdgpu_op_s_cmp_lg_i32, -amdgpu_op_s_scratch_store_dwordx4, -amdgpu_op_s_buffer_store_dword, -amdgpu_op_s_nand_b64, -amdgpu_op_v_cmpx_t_u64, -amdgpu_op_buffer_store_format_x, -amdgpu_op_s_mul_hi_i32, -amdgpu_op_s_ashr_i64, -amdgpu_op_s_cbranch_join, -amdgpu_op_tbuffer_load_format_x, -amdgpu_op_v_add_b32_e64, -amdgpu_op_s_buffer_load_dwordx16, -amdgpu_op_v_mad_f32, -amdgpu_op_v_mul_i32_i24, -amdgpu_op_v_ldexp_f16_e64, -amdgpu_op_tbuffer_store_format_x, -amdgpu_op_s_bcnt0_i32_b64, -amdgpu_op_s_cmp_le_u32, -amdgpu_op_s_lshl4_add_u32, -amdgpu_op_v_mul_legacy_f32_e64, -amdgpu_op_s_add_i32, -amdgpu_op_v_lshlrev_b16_e64, -amdgpu_op_v_nop_e64, -amdgpu_op_tbuffer_load_format_xyzw, -amdgpu_op_s_ttracedata, -amdgpu_op_v_cmp_lt_u64_e64, -amdgpu_op_s_store_dword, -amdgpu_op_s_setprio, -amdgpu_op_s_fltbit_i32_i64, -amdgpu_op_s_orn2_savexec_b64, -amdgpu_op_v_add_co_u32, -amdgpu_op_s_bfe_u32, -amdgpu_op_v_mul_i32_i24_e64, -amdgpu_op_s_or_b64, -amdgpu_op_buffer_load_dwordx4, -amdgpu_op_v_cvt_off_f32_i4_e64, -amdgpu_op_s_bitset1_b64, -amdgpu_op_s_cmp_gt_u32, -amdgpu_op_s_cbranch_vccz, -amdgpu_op_s_store_dwordx4, -amdgpu_op_s_orn2_b32, -amdgpu_op_s_bcnt1_i32_b32, -amdgpu_op_v_madak_f16_e64, -amdgpu_op_s_and_b64, -amdgpu_op_s_buffer_store_dwordx4, -amdgpu_op_v_cmp_gt_u64, -amdgpu_op_v_madmk_f16, -amdgpu_op_v_cmp_ne_u32, -amdgpu_op_v_cvt_f32_u32_e64, -amdgpu_op_v_cvt_u32_f32_e64, -amdgpu_op_v_cmp_eq_u32, -amdgpu_op_s_cmp_lg_u32, -amdgpu_op_s_setvkip, -amdgpu_op_s_cslect_b64, -amdgpu_op_s_scratch_load_dwordx4, -amdgpu_op_v_lshrrev_b16, -amdgpu_op_s_cmp_gt_i32, -amdgpu_op_s_call_b64, -amdgpu_op_v_add_b32, -amdgpu_op_s_xnor_b32, -amdgpu_op_s_lshl1_add_u32, -amdgpu_op_v_cvt_rpi_i32_f32_e64, -amdgpu_op_s_trap, -amdgpu_op_s_lshr_b32, -amdgpu_op_v_madak_f16, -amdgpu_op_tbuffer_store_format_xyzw, -amdgpu_op_s_decperflevel, -amdgpu_op_s_andn1_saveexec_b64, -amdgpu_op_s_bfe_i32, -amdgpu_op_s_cmp_eq_u64, -amdgpu_op_v_sub_u16, -amdgpu_op_v_lshlrev_b64, -amdgpu_op_v_interp_mov_f32, -amdgpu_op_s_andn2_wrexec_b64, -amdgpu_op_s_dcache_memtime, -amdgpu_op_s_cbranch_cdbgsys_and_user, -amdgpu_op_s_cmpk_ge_i32, -amdgpu_op_v_max_f16_e64, -amdgpu_op_v_mac_f16, diff --git a/common/h/amdgpu_vega_sys_regs.h b/common/h/amdgpu_vega_sys_regs.h deleted file mode 100644 index 3e6a636354..0000000000 --- a/common/h/amdgpu_vega_sys_regs.h +++ /dev/null @@ -1,1563 +0,0 @@ -#ifndef DYNINST_AMDGPU_VEGA_SYS_REGS_H -#define DYNINST_AMDGPU_VEGA_SYS_REGS_H -DEF_REGISTER(address_mode_32, Arch_amdgpu_vega | HWR | BITS_32 | 0,"amdgpu_vega"); -DEF_REGISTER(exec, Arch_amdgpu_vega | HWR | BITS_64 | 1,"amdgpu_vega"); -DEF_REGISTER(exec_lo, Arch_amdgpu_vega | 0x0 | BITS_32 | 0x8000 | 1,"amdgpu_vega"); -DEF_REGISTER(exec_hi, Arch_amdgpu_vega | 0x200000 | BITS_32 | 0x8000 | 1,"amdgpu_vega"); -DEF_REGISTER(expcnt, Arch_amdgpu_vega | HWR | BITS_3 | 2,"amdgpu_vega"); -DEF_REGISTER(export_icount, Arch_amdgpu_vega | HWR | BITS_8 | 3,"amdgpu_vega"); -DEF_REGISTER(flat_scratch, Arch_amdgpu_vega | HWR | BITS_64 | 4,"amdgpu_vega"); -DEF_REGISTER(flat_scratch_lo, Arch_amdgpu_vega | 0x0 | BITS_32 | 0x8000 | 4,"amdgpu_vega"); -DEF_REGISTER(flat_scratch_hi, Arch_amdgpu_vega | 0x200000 | BITS_32 | 0x8000 | 4,"amdgpu_vega"); -DEF_REGISTER(gpr_alloc, Arch_amdgpu_vega | HWR | BITS_32 | 5,"amdgpu_vega"); -DEF_REGISTER(vgpr_base, Arch_amdgpu_vega | 0x0 | BITS_6 | 0x8000 | 5,"amdgpu_vega"); -DEF_REGISTER(vgpt_size, Arch_amdgpu_vega | 0x80000 | BITS_6 | 0x8000 | 5,"amdgpu_vega"); -DEF_REGISTER(sgpr_base, Arch_amdgpu_vega | 0x100000 | BITS_6 | 0x8000 | 5,"amdgpu_vega"); -DEF_REGISTER(sgpr_size, Arch_amdgpu_vega | 0x180000 | BITS_4 | 0x8000 | 5,"amdgpu_vega"); -DEF_REGISTER(ib_sts, Arch_amdgpu_vega | HWR | BITS_32 | 6,"amdgpu_vega"); -DEF_REGISTER(exp_cnt, Arch_amdgpu_vega | 0x40000 | BITS_3 | 0x8000 | 6,"amdgpu_vega"); -DEF_REGISTER(lgkm_cnt, Arch_amdgpu_vega | 0x80000 | BITS_4 | 0x8000 | 6,"amdgpu_vega"); -DEF_REGISTER(valu_cnt, Arch_amdgpu_vega | 0xc0000 | BITS_3 | 0x8000 | 6,"amdgpu_vega"); -DEF_REGISTER(vm_cnt, Arch_amdgpu_vega | 0xf0000 | BITS_6 | 0x8000 | 6,"amdgpu_vega"); -DEF_REGISTER(lds_alloc, Arch_amdgpu_vega | HWR | BITS_32 | 7,"amdgpu_vega"); -DEF_REGISTER(lds_base, Arch_amdgpu_vega | 0x0 | BITS_8 | 0x8000 | 7,"amdgpu_vega"); -DEF_REGISTER(lds_size, Arch_amdgpu_vega | 0xc0000 | BITS_9 | 0x8000 | 7,"amdgpu_vega"); -DEF_REGISTER(lds_gds_constant_message_count, Arch_amdgpu_vega | HWR | BITS_8 | 8,"amdgpu_vega"); -DEF_REGISTER(lgkmcnt, Arch_amdgpu_vega | HWR | BITS_4 | 9,"amdgpu_vega"); -DEF_REGISTER(m0, Arch_amdgpu_vega | HWR | BITS_32 | 10,"amdgpu_vega"); -DEF_REGISTER(gds_size, Arch_amdgpu_vega | 0x0 | BITS_16 | 0x8000 | 10,"amdgpu_vega"); -DEF_REGISTER(lds_direct_address, Arch_amdgpu_vega | 0x0 | BITS_16 | 0x8000 | 10,"amdgpu_vega"); -DEF_REGISTER(lds_interpolation_parameter_offset, Arch_amdgpu_vega | 0x0 | BITS_16 | 0x8000 | 10,"amdgpu_vega"); -DEF_REGISTER(lds_memory_vfetch_offset, Arch_amdgpu_vega | 0x0 | BITS_16 | 0x8000 | 10,"amdgpu_vega"); -DEF_REGISTER(lds_direct_data_type, Arch_amdgpu_vega | 0x100000 | BITS_3 | 0x8000 | 10,"amdgpu_vega"); -DEF_REGISTER(lds_interpolation_new_prim_mask, Arch_amdgpu_vega | 0x100000 | BITS_15 | 0x8000 | 10,"amdgpu_vega"); -DEF_REGISTER(gds_base, Arch_amdgpu_vega | 0x100000 | BITS_16 | 0x8000 | 10,"amdgpu_vega"); -DEF_REGISTER(mode, Arch_amdgpu_vega | HWR | BITS_32 | 11,"amdgpu_vega"); -DEF_REGISTER(fp_round, Arch_amdgpu_vega | 0x0 | BITS_4 | 0x8000 | 11,"amdgpu_vega"); -DEF_REGISTER(fp_denorm, Arch_amdgpu_vega | 0x40000 | BITS_4 | 0x8000 | 11,"amdgpu_vega"); -DEF_REGISTER(dx10_clamp, Arch_amdgpu_vega | 0x80000 | BITS_1 | 0x8000 | 11,"amdgpu_vega"); -DEF_REGISTER(ieee, Arch_amdgpu_vega | 0x90000 | BITS_1 | 0x8000 | 11,"amdgpu_vega"); -DEF_REGISTER(lod_clamped, Arch_amdgpu_vega | 0xa0000 | BITS_1 | 0x8000 | 11,"amdgpu_vega"); -DEF_REGISTER(debug, Arch_amdgpu_vega | 0xb0000 | BITS_1 | 0x8000 | 11,"amdgpu_vega"); -DEF_REGISTER(excp_en, Arch_amdgpu_vega | 0xc0000 | BITS_7 | 0x8000 | 11,"amdgpu_vega"); -DEF_REGISTER(fp16_ovfl, Arch_amdgpu_vega | 0x170000 | BITS_1 | 0x8000 | 11,"amdgpu_vega"); -DEF_REGISTER(pops_packer0, Arch_amdgpu_vega | 0x180000 | BITS_1 | 0x8000 | 11,"amdgpu_vega"); -DEF_REGISTER(pops_packer1, Arch_amdgpu_vega | 0x190000 | BITS_1 | 0x8000 | 11,"amdgpu_vega"); -DEF_REGISTER(disable_perf, Arch_amdgpu_vega | 0x1a0000 | BITS_1 | 0x8000 | 11,"amdgpu_vega"); -DEF_REGISTER(gpr_idx_en, Arch_amdgpu_vega | 0x1b0000 | BITS_1 | 0x8000 | 11,"amdgpu_vega"); -DEF_REGISTER(vskip, Arch_amdgpu_vega | 0x1c0000 | BITS_1 | 0x8000 | 11,"amdgpu_vega"); -DEF_REGISTER(csp, Arch_amdgpu_vega | 0x1d0000 | BITS_3 | 0x8000 | 11,"amdgpu_vega"); -DEF_REGISTER(pc, Arch_amdgpu_vega | PC | BITS_48 | 0,"amdgpu_vega"); -DEF_REGISTER(pops_exiting_wave_id, Arch_amdgpu_vega | HWR | BITS_64 | 12,"amdgpu_vega"); -DEF_REGISTER(private_base, Arch_amdgpu_vega | HWR | BITS_64 | 13,"amdgpu_vega"); -DEF_REGISTER(private_limit, Arch_amdgpu_vega | HWR | BITS_64 | 14,"amdgpu_vega"); -DEF_REGISTER(shared_base, Arch_amdgpu_vega | HWR | BITS_64 | 15,"amdgpu_vega"); -DEF_REGISTER(shared_limit, Arch_amdgpu_vega | HWR | BITS_64 | 16,"amdgpu_vega"); -DEF_REGISTER(status, Arch_amdgpu_vega | HWR | BITS_32 | 17,"amdgpu_vega"); -DEF_REGISTER(scc, Arch_amdgpu_vega | 0x0 | BITS_1 | 0x8000 | 17,"amdgpu_vega"); -DEF_REGISTER(spi_prio, Arch_amdgpu_vega | 0x10000 | BITS_2 | 0x8000 | 17,"amdgpu_vega"); -DEF_REGISTER(wave_prio, Arch_amdgpu_vega | 0x30000 | BITS_2 | 0x8000 | 17,"amdgpu_vega"); -DEF_REGISTER(priv, Arch_amdgpu_vega | 0x50000 | BITS_1 | 0x8000 | 17,"amdgpu_vega"); -DEF_REGISTER(trap_en, Arch_amdgpu_vega | 0x60000 | BITS_1 | 0x8000 | 17,"amdgpu_vega"); -DEF_REGISTER(ttrace_en, Arch_amdgpu_vega | 0x70000 | BITS_1 | 0x8000 | 17,"amdgpu_vega"); -DEF_REGISTER(export_rdy, Arch_amdgpu_vega | 0x80000 | BITS_1 | 0x8000 | 17,"amdgpu_vega"); -DEF_REGISTER(execz, Arch_amdgpu_vega | 0x90000 | BITS_1 | 0x8000 | 17,"amdgpu_vega"); -DEF_REGISTER(vccz, Arch_amdgpu_vega | 0xa0000 | BITS_1 | 0x8000 | 17,"amdgpu_vega"); -DEF_REGISTER(in_tg, Arch_amdgpu_vega | 0xb0000 | BITS_1 | 0x8000 | 17,"amdgpu_vega"); -DEF_REGISTER(in_barrier, Arch_amdgpu_vega | 0xc0000 | BITS_1 | 0x8000 | 17,"amdgpu_vega"); -DEF_REGISTER(halt, Arch_amdgpu_vega | 0xd0000 | BITS_1 | 0x8000 | 17,"amdgpu_vega"); -DEF_REGISTER(trap, Arch_amdgpu_vega | 0xe0000 | BITS_1 | 0x8000 | 17,"amdgpu_vega"); -DEF_REGISTER(ttrace_cu_en, Arch_amdgpu_vega | 0xf0000 | BITS_1 | 0x8000 | 17,"amdgpu_vega"); -DEF_REGISTER(valid, Arch_amdgpu_vega | 0x100000 | BITS_1 | 0x8000 | 17,"amdgpu_vega"); -DEF_REGISTER(ecc_err, Arch_amdgpu_vega | 0x110000 | BITS_1 | 0x8000 | 17,"amdgpu_vega"); -DEF_REGISTER(skin_export, Arch_amdgpu_vega | 0x120000 | BITS_1 | 0x8000 | 17,"amdgpu_vega"); -DEF_REGISTER(perf_en, Arch_amdgpu_vega | 0x130000 | BITS_1 | 0x8000 | 17,"amdgpu_vega"); -DEF_REGISTER(cond_dbg_user, Arch_amdgpu_vega | 0x140000 | BITS_1 | 0x8000 | 17,"amdgpu_vega"); -DEF_REGISTER(cond_dbg_sys, Arch_amdgpu_vega | 0x150000 | BITS_1 | 0x8000 | 17,"amdgpu_vega"); -DEF_REGISTER(allow_replay, Arch_amdgpu_vega | 0x160000 | BITS_1 | 0x8000 | 17,"amdgpu_vega"); -DEF_REGISTER(must_export, Arch_amdgpu_vega | 0x1b0000 | BITS_1 | 0x8000 | 17,"amdgpu_vega"); -DEF_REGISTER(tba, Arch_amdgpu_vega | HWR | BITS_64 | 18,"amdgpu_vega"); -DEF_REGISTER(tid, Arch_amdgpu_vega | HWR | BITS_32 | 19,"amdgpu_vega"); -DEF_REGISTER(tma, Arch_amdgpu_vega | HWR | BITS_64 | 20,"amdgpu_vega"); -DEF_REGISTER(trap_base_address, Arch_amdgpu_vega | HWR | BITS_64 | 21,"amdgpu_vega"); -DEF_REGISTER(trap_memory_address, Arch_amdgpu_vega | HWR | BITS_64 | 22,"amdgpu_vega"); -DEF_REGISTER(ttmp0, Arch_amdgpu_vega | TTMP_SGPR | BITS_32 | 0,"amdgpu_vega"); -DEF_REGISTER(ttmp1, Arch_amdgpu_vega | TTMP_SGPR | BITS_32 | 1,"amdgpu_vega"); -DEF_REGISTER(ttmp10, Arch_amdgpu_vega | TTMP_SGPR | BITS_32 | 2,"amdgpu_vega"); -DEF_REGISTER(ttmp11, Arch_amdgpu_vega | TTMP_SGPR | BITS_32 | 3,"amdgpu_vega"); -DEF_REGISTER(ttmp12, Arch_amdgpu_vega | TTMP_SGPR | BITS_32 | 4,"amdgpu_vega"); -DEF_REGISTER(ttmp13, Arch_amdgpu_vega | TTMP_SGPR | BITS_32 | 5,"amdgpu_vega"); -DEF_REGISTER(ttmp14, Arch_amdgpu_vega | TTMP_SGPR | BITS_32 | 6,"amdgpu_vega"); -DEF_REGISTER(ttmp15, Arch_amdgpu_vega | TTMP_SGPR | BITS_32 | 7,"amdgpu_vega"); -DEF_REGISTER(ttmp2, Arch_amdgpu_vega | TTMP_SGPR | BITS_32 | 8,"amdgpu_vega"); -DEF_REGISTER(ttmp3, Arch_amdgpu_vega | TTMP_SGPR | BITS_32 | 9,"amdgpu_vega"); -DEF_REGISTER(ttmp4, Arch_amdgpu_vega | TTMP_SGPR | BITS_32 | 10,"amdgpu_vega"); -DEF_REGISTER(ttmp5, Arch_amdgpu_vega | TTMP_SGPR | BITS_32 | 11,"amdgpu_vega"); -DEF_REGISTER(ttmp6, Arch_amdgpu_vega | TTMP_SGPR | BITS_32 | 12,"amdgpu_vega"); -DEF_REGISTER(ttmp7, Arch_amdgpu_vega | TTMP_SGPR | BITS_32 | 13,"amdgpu_vega"); -DEF_REGISTER(ttmp8, Arch_amdgpu_vega | TTMP_SGPR | BITS_32 | 14,"amdgpu_vega"); -DEF_REGISTER(ttmp9, Arch_amdgpu_vega | TTMP_SGPR | BITS_32 | 15,"amdgpu_vega"); -DEF_REGISTER(vcc, Arch_amdgpu_vega | HWR | BITS_64 | 23,"amdgpu_vega"); -DEF_REGISTER(vcc_lo, Arch_amdgpu_vega | 0x0 | BITS_32 | 0x8000 | 23,"amdgpu_vega"); -DEF_REGISTER(vcc_hi, Arch_amdgpu_vega | 0x200000 | BITS_32 | 0x8000 | 23,"amdgpu_vega"); -DEF_REGISTER(vectory_memory_icount, Arch_amdgpu_vega | HWR | BITS_8 | 24,"amdgpu_vega"); -DEF_REGISTER(vmcnt, Arch_amdgpu_vega | HWR | BITS_6 | 25,"amdgpu_vega"); -DEF_REGISTER(xnack_mask, Arch_amdgpu_vega | HWR | BITS_64 | 26,"amdgpu_vega"); -DEF_REGISTER(xnack_mask_lo, Arch_amdgpu_vega | 0x0 | BITS_32 | 0x8000 | 26,"amdgpu_vega"); -DEF_REGISTER(xnack_mask_hi, Arch_amdgpu_vega | 0x200000 | BITS_32 | 0x8000 | 26,"amdgpu_vega"); -DEF_REGISTER(sgpr0, Arch_amdgpu_vega | SGPR | BITS_32 | 0,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec2_0, Arch_amdgpu_vega | SGPR_VEC2 | BITS_64 | 0,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec4_0, Arch_amdgpu_vega | SGPR_VEC4 | BITS_128 | 0,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec8_0, Arch_amdgpu_vega | SGPR_VEC8 | BITS_256 | 0,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec16_0, Arch_amdgpu_vega | SGPR_VEC16 | BITS_512 | 0,"amdgpu_vega"); -DEF_REGISTER(sgpr1, Arch_amdgpu_vega | SGPR | BITS_32 | 1,"amdgpu_vega"); -DEF_REGISTER(sgpr2, Arch_amdgpu_vega | SGPR | BITS_32 | 2,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec2_2, Arch_amdgpu_vega | SGPR_VEC2 | BITS_64 | 2,"amdgpu_vega"); -DEF_REGISTER(sgpr3, Arch_amdgpu_vega | SGPR | BITS_32 | 3,"amdgpu_vega"); -DEF_REGISTER(sgpr4, Arch_amdgpu_vega | SGPR | BITS_32 | 4,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec2_4, Arch_amdgpu_vega | SGPR_VEC2 | BITS_64 | 4,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec4_4, Arch_amdgpu_vega | SGPR_VEC4 | BITS_128 | 4,"amdgpu_vega"); -DEF_REGISTER(sgpr5, Arch_amdgpu_vega | SGPR | BITS_32 | 5,"amdgpu_vega"); -DEF_REGISTER(sgpr6, Arch_amdgpu_vega | SGPR | BITS_32 | 6,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec2_6, Arch_amdgpu_vega | SGPR_VEC2 | BITS_64 | 6,"amdgpu_vega"); -DEF_REGISTER(sgpr7, Arch_amdgpu_vega | SGPR | BITS_32 | 7,"amdgpu_vega"); -DEF_REGISTER(sgpr8, Arch_amdgpu_vega | SGPR | BITS_32 | 8,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec2_8, Arch_amdgpu_vega | SGPR_VEC2 | BITS_64 | 8,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec4_8, Arch_amdgpu_vega | SGPR_VEC4 | BITS_128 | 8,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec8_8, Arch_amdgpu_vega | SGPR_VEC8 | BITS_256 | 8,"amdgpu_vega"); -DEF_REGISTER(sgpr9, Arch_amdgpu_vega | SGPR | BITS_32 | 9,"amdgpu_vega"); -DEF_REGISTER(sgpr10, Arch_amdgpu_vega | SGPR | BITS_32 | 10,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec2_10, Arch_amdgpu_vega | SGPR_VEC2 | BITS_64 | 10,"amdgpu_vega"); -DEF_REGISTER(sgpr11, Arch_amdgpu_vega | SGPR | BITS_32 | 11,"amdgpu_vega"); -DEF_REGISTER(sgpr12, Arch_amdgpu_vega | SGPR | BITS_32 | 12,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec2_12, Arch_amdgpu_vega | SGPR_VEC2 | BITS_64 | 12,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec4_12, Arch_amdgpu_vega | SGPR_VEC4 | BITS_128 | 12,"amdgpu_vega"); -DEF_REGISTER(sgpr13, Arch_amdgpu_vega | SGPR | BITS_32 | 13,"amdgpu_vega"); -DEF_REGISTER(sgpr14, Arch_amdgpu_vega | SGPR | BITS_32 | 14,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec2_14, Arch_amdgpu_vega | SGPR_VEC2 | BITS_64 | 14,"amdgpu_vega"); -DEF_REGISTER(sgpr15, Arch_amdgpu_vega | SGPR | BITS_32 | 15,"amdgpu_vega"); -DEF_REGISTER(sgpr16, Arch_amdgpu_vega | SGPR | BITS_32 | 16,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec2_16, Arch_amdgpu_vega | SGPR_VEC2 | BITS_64 | 16,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec4_16, Arch_amdgpu_vega | SGPR_VEC4 | BITS_128 | 16,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec8_16, Arch_amdgpu_vega | SGPR_VEC8 | BITS_256 | 16,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec16_16, Arch_amdgpu_vega | SGPR_VEC16 | BITS_512 | 16,"amdgpu_vega"); -DEF_REGISTER(sgpr17, Arch_amdgpu_vega | SGPR | BITS_32 | 17,"amdgpu_vega"); -DEF_REGISTER(sgpr18, Arch_amdgpu_vega | SGPR | BITS_32 | 18,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec2_18, Arch_amdgpu_vega | SGPR_VEC2 | BITS_64 | 18,"amdgpu_vega"); -DEF_REGISTER(sgpr19, Arch_amdgpu_vega | SGPR | BITS_32 | 19,"amdgpu_vega"); -DEF_REGISTER(sgpr20, Arch_amdgpu_vega | SGPR | BITS_32 | 20,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec2_20, Arch_amdgpu_vega | SGPR_VEC2 | BITS_64 | 20,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec4_20, Arch_amdgpu_vega | SGPR_VEC4 | BITS_128 | 20,"amdgpu_vega"); -DEF_REGISTER(sgpr21, Arch_amdgpu_vega | SGPR | BITS_32 | 21,"amdgpu_vega"); -DEF_REGISTER(sgpr22, Arch_amdgpu_vega | SGPR | BITS_32 | 22,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec2_22, Arch_amdgpu_vega | SGPR_VEC2 | BITS_64 | 22,"amdgpu_vega"); -DEF_REGISTER(sgpr23, Arch_amdgpu_vega | SGPR | BITS_32 | 23,"amdgpu_vega"); -DEF_REGISTER(sgpr24, Arch_amdgpu_vega | SGPR | BITS_32 | 24,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec2_24, Arch_amdgpu_vega | SGPR_VEC2 | BITS_64 | 24,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec4_24, Arch_amdgpu_vega | SGPR_VEC4 | BITS_128 | 24,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec8_24, Arch_amdgpu_vega | SGPR_VEC8 | BITS_256 | 24,"amdgpu_vega"); -DEF_REGISTER(sgpr25, Arch_amdgpu_vega | SGPR | BITS_32 | 25,"amdgpu_vega"); -DEF_REGISTER(sgpr26, Arch_amdgpu_vega | SGPR | BITS_32 | 26,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec2_26, Arch_amdgpu_vega | SGPR_VEC2 | BITS_64 | 26,"amdgpu_vega"); -DEF_REGISTER(sgpr27, Arch_amdgpu_vega | SGPR | BITS_32 | 27,"amdgpu_vega"); -DEF_REGISTER(sgpr28, Arch_amdgpu_vega | SGPR | BITS_32 | 28,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec2_28, Arch_amdgpu_vega | SGPR_VEC2 | BITS_64 | 28,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec4_28, Arch_amdgpu_vega | SGPR_VEC4 | BITS_128 | 28,"amdgpu_vega"); -DEF_REGISTER(sgpr29, Arch_amdgpu_vega | SGPR | BITS_32 | 29,"amdgpu_vega"); -DEF_REGISTER(sgpr30, Arch_amdgpu_vega | SGPR | BITS_32 | 30,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec2_30, Arch_amdgpu_vega | SGPR_VEC2 | BITS_64 | 30,"amdgpu_vega"); -DEF_REGISTER(sgpr31, Arch_amdgpu_vega | SGPR | BITS_32 | 31,"amdgpu_vega"); -DEF_REGISTER(sgpr32, Arch_amdgpu_vega | SGPR | BITS_32 | 32,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec2_32, Arch_amdgpu_vega | SGPR_VEC2 | BITS_64 | 32,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec4_32, Arch_amdgpu_vega | SGPR_VEC4 | BITS_128 | 32,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec8_32, Arch_amdgpu_vega | SGPR_VEC8 | BITS_256 | 32,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec16_32, Arch_amdgpu_vega | SGPR_VEC16 | BITS_512 | 32,"amdgpu_vega"); -DEF_REGISTER(sgpr33, Arch_amdgpu_vega | SGPR | BITS_32 | 33,"amdgpu_vega"); -DEF_REGISTER(sgpr34, Arch_amdgpu_vega | SGPR | BITS_32 | 34,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec2_34, Arch_amdgpu_vega | SGPR_VEC2 | BITS_64 | 34,"amdgpu_vega"); -DEF_REGISTER(sgpr35, Arch_amdgpu_vega | SGPR | BITS_32 | 35,"amdgpu_vega"); -DEF_REGISTER(sgpr36, Arch_amdgpu_vega | SGPR | BITS_32 | 36,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec2_36, Arch_amdgpu_vega | SGPR_VEC2 | BITS_64 | 36,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec4_36, Arch_amdgpu_vega | SGPR_VEC4 | BITS_128 | 36,"amdgpu_vega"); -DEF_REGISTER(sgpr37, Arch_amdgpu_vega | SGPR | BITS_32 | 37,"amdgpu_vega"); -DEF_REGISTER(sgpr38, Arch_amdgpu_vega | SGPR | BITS_32 | 38,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec2_38, Arch_amdgpu_vega | SGPR_VEC2 | BITS_64 | 38,"amdgpu_vega"); -DEF_REGISTER(sgpr39, Arch_amdgpu_vega | SGPR | BITS_32 | 39,"amdgpu_vega"); -DEF_REGISTER(sgpr40, Arch_amdgpu_vega | SGPR | BITS_32 | 40,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec2_40, Arch_amdgpu_vega | SGPR_VEC2 | BITS_64 | 40,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec4_40, Arch_amdgpu_vega | SGPR_VEC4 | BITS_128 | 40,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec8_40, Arch_amdgpu_vega | SGPR_VEC8 | BITS_256 | 40,"amdgpu_vega"); -DEF_REGISTER(sgpr41, Arch_amdgpu_vega | SGPR | BITS_32 | 41,"amdgpu_vega"); -DEF_REGISTER(sgpr42, Arch_amdgpu_vega | SGPR | BITS_32 | 42,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec2_42, Arch_amdgpu_vega | SGPR_VEC2 | BITS_64 | 42,"amdgpu_vega"); -DEF_REGISTER(sgpr43, Arch_amdgpu_vega | SGPR | BITS_32 | 43,"amdgpu_vega"); -DEF_REGISTER(sgpr44, Arch_amdgpu_vega | SGPR | BITS_32 | 44,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec2_44, Arch_amdgpu_vega | SGPR_VEC2 | BITS_64 | 44,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec4_44, Arch_amdgpu_vega | SGPR_VEC4 | BITS_128 | 44,"amdgpu_vega"); -DEF_REGISTER(sgpr45, Arch_amdgpu_vega | SGPR | BITS_32 | 45,"amdgpu_vega"); -DEF_REGISTER(sgpr46, Arch_amdgpu_vega | SGPR | BITS_32 | 46,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec2_46, Arch_amdgpu_vega | SGPR_VEC2 | BITS_64 | 46,"amdgpu_vega"); -DEF_REGISTER(sgpr47, Arch_amdgpu_vega | SGPR | BITS_32 | 47,"amdgpu_vega"); -DEF_REGISTER(sgpr48, Arch_amdgpu_vega | SGPR | BITS_32 | 48,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec2_48, Arch_amdgpu_vega | SGPR_VEC2 | BITS_64 | 48,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec4_48, Arch_amdgpu_vega | SGPR_VEC4 | BITS_128 | 48,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec8_48, Arch_amdgpu_vega | SGPR_VEC8 | BITS_256 | 48,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec16_48, Arch_amdgpu_vega | SGPR_VEC16 | BITS_512 | 48,"amdgpu_vega"); -DEF_REGISTER(sgpr49, Arch_amdgpu_vega | SGPR | BITS_32 | 49,"amdgpu_vega"); -DEF_REGISTER(sgpr50, Arch_amdgpu_vega | SGPR | BITS_32 | 50,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec2_50, Arch_amdgpu_vega | SGPR_VEC2 | BITS_64 | 50,"amdgpu_vega"); -DEF_REGISTER(sgpr51, Arch_amdgpu_vega | SGPR | BITS_32 | 51,"amdgpu_vega"); -DEF_REGISTER(sgpr52, Arch_amdgpu_vega | SGPR | BITS_32 | 52,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec2_52, Arch_amdgpu_vega | SGPR_VEC2 | BITS_64 | 52,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec4_52, Arch_amdgpu_vega | SGPR_VEC4 | BITS_128 | 52,"amdgpu_vega"); -DEF_REGISTER(sgpr53, Arch_amdgpu_vega | SGPR | BITS_32 | 53,"amdgpu_vega"); -DEF_REGISTER(sgpr54, Arch_amdgpu_vega | SGPR | BITS_32 | 54,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec2_54, Arch_amdgpu_vega | SGPR_VEC2 | BITS_64 | 54,"amdgpu_vega"); -DEF_REGISTER(sgpr55, Arch_amdgpu_vega | SGPR | BITS_32 | 55,"amdgpu_vega"); -DEF_REGISTER(sgpr56, Arch_amdgpu_vega | SGPR | BITS_32 | 56,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec2_56, Arch_amdgpu_vega | SGPR_VEC2 | BITS_64 | 56,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec4_56, Arch_amdgpu_vega | SGPR_VEC4 | BITS_128 | 56,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec8_56, Arch_amdgpu_vega | SGPR_VEC8 | BITS_256 | 56,"amdgpu_vega"); -DEF_REGISTER(sgpr57, Arch_amdgpu_vega | SGPR | BITS_32 | 57,"amdgpu_vega"); -DEF_REGISTER(sgpr58, Arch_amdgpu_vega | SGPR | BITS_32 | 58,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec2_58, Arch_amdgpu_vega | SGPR_VEC2 | BITS_64 | 58,"amdgpu_vega"); -DEF_REGISTER(sgpr59, Arch_amdgpu_vega | SGPR | BITS_32 | 59,"amdgpu_vega"); -DEF_REGISTER(sgpr60, Arch_amdgpu_vega | SGPR | BITS_32 | 60,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec2_60, Arch_amdgpu_vega | SGPR_VEC2 | BITS_64 | 60,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec4_60, Arch_amdgpu_vega | SGPR_VEC4 | BITS_128 | 60,"amdgpu_vega"); -DEF_REGISTER(sgpr61, Arch_amdgpu_vega | SGPR | BITS_32 | 61,"amdgpu_vega"); -DEF_REGISTER(sgpr62, Arch_amdgpu_vega | SGPR | BITS_32 | 62,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec2_62, Arch_amdgpu_vega | SGPR_VEC2 | BITS_64 | 62,"amdgpu_vega"); -DEF_REGISTER(sgpr63, Arch_amdgpu_vega | SGPR | BITS_32 | 63,"amdgpu_vega"); -DEF_REGISTER(sgpr64, Arch_amdgpu_vega | SGPR | BITS_32 | 64,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec2_64, Arch_amdgpu_vega | SGPR_VEC2 | BITS_64 | 64,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec4_64, Arch_amdgpu_vega | SGPR_VEC4 | BITS_128 | 64,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec8_64, Arch_amdgpu_vega | SGPR_VEC8 | BITS_256 | 64,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec16_64, Arch_amdgpu_vega | SGPR_VEC16 | BITS_512 | 64,"amdgpu_vega"); -DEF_REGISTER(sgpr65, Arch_amdgpu_vega | SGPR | BITS_32 | 65,"amdgpu_vega"); -DEF_REGISTER(sgpr66, Arch_amdgpu_vega | SGPR | BITS_32 | 66,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec2_66, Arch_amdgpu_vega | SGPR_VEC2 | BITS_64 | 66,"amdgpu_vega"); -DEF_REGISTER(sgpr67, Arch_amdgpu_vega | SGPR | BITS_32 | 67,"amdgpu_vega"); -DEF_REGISTER(sgpr68, Arch_amdgpu_vega | SGPR | BITS_32 | 68,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec2_68, Arch_amdgpu_vega | SGPR_VEC2 | BITS_64 | 68,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec4_68, Arch_amdgpu_vega | SGPR_VEC4 | BITS_128 | 68,"amdgpu_vega"); -DEF_REGISTER(sgpr69, Arch_amdgpu_vega | SGPR | BITS_32 | 69,"amdgpu_vega"); -DEF_REGISTER(sgpr70, Arch_amdgpu_vega | SGPR | BITS_32 | 70,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec2_70, Arch_amdgpu_vega | SGPR_VEC2 | BITS_64 | 70,"amdgpu_vega"); -DEF_REGISTER(sgpr71, Arch_amdgpu_vega | SGPR | BITS_32 | 71,"amdgpu_vega"); -DEF_REGISTER(sgpr72, Arch_amdgpu_vega | SGPR | BITS_32 | 72,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec2_72, Arch_amdgpu_vega | SGPR_VEC2 | BITS_64 | 72,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec4_72, Arch_amdgpu_vega | SGPR_VEC4 | BITS_128 | 72,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec8_72, Arch_amdgpu_vega | SGPR_VEC8 | BITS_256 | 72,"amdgpu_vega"); -DEF_REGISTER(sgpr73, Arch_amdgpu_vega | SGPR | BITS_32 | 73,"amdgpu_vega"); -DEF_REGISTER(sgpr74, Arch_amdgpu_vega | SGPR | BITS_32 | 74,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec2_74, Arch_amdgpu_vega | SGPR_VEC2 | BITS_64 | 74,"amdgpu_vega"); -DEF_REGISTER(sgpr75, Arch_amdgpu_vega | SGPR | BITS_32 | 75,"amdgpu_vega"); -DEF_REGISTER(sgpr76, Arch_amdgpu_vega | SGPR | BITS_32 | 76,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec2_76, Arch_amdgpu_vega | SGPR_VEC2 | BITS_64 | 76,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec4_76, Arch_amdgpu_vega | SGPR_VEC4 | BITS_128 | 76,"amdgpu_vega"); -DEF_REGISTER(sgpr77, Arch_amdgpu_vega | SGPR | BITS_32 | 77,"amdgpu_vega"); -DEF_REGISTER(sgpr78, Arch_amdgpu_vega | SGPR | BITS_32 | 78,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec2_78, Arch_amdgpu_vega | SGPR_VEC2 | BITS_64 | 78,"amdgpu_vega"); -DEF_REGISTER(sgpr79, Arch_amdgpu_vega | SGPR | BITS_32 | 79,"amdgpu_vega"); -DEF_REGISTER(sgpr80, Arch_amdgpu_vega | SGPR | BITS_32 | 80,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec2_80, Arch_amdgpu_vega | SGPR_VEC2 | BITS_64 | 80,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec4_80, Arch_amdgpu_vega | SGPR_VEC4 | BITS_128 | 80,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec8_80, Arch_amdgpu_vega | SGPR_VEC8 | BITS_256 | 80,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec16_80, Arch_amdgpu_vega | SGPR_VEC16 | BITS_512 | 80,"amdgpu_vega"); -DEF_REGISTER(sgpr81, Arch_amdgpu_vega | SGPR | BITS_32 | 81,"amdgpu_vega"); -DEF_REGISTER(sgpr82, Arch_amdgpu_vega | SGPR | BITS_32 | 82,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec2_82, Arch_amdgpu_vega | SGPR_VEC2 | BITS_64 | 82,"amdgpu_vega"); -DEF_REGISTER(sgpr83, Arch_amdgpu_vega | SGPR | BITS_32 | 83,"amdgpu_vega"); -DEF_REGISTER(sgpr84, Arch_amdgpu_vega | SGPR | BITS_32 | 84,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec2_84, Arch_amdgpu_vega | SGPR_VEC2 | BITS_64 | 84,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec4_84, Arch_amdgpu_vega | SGPR_VEC4 | BITS_128 | 84,"amdgpu_vega"); -DEF_REGISTER(sgpr85, Arch_amdgpu_vega | SGPR | BITS_32 | 85,"amdgpu_vega"); -DEF_REGISTER(sgpr86, Arch_amdgpu_vega | SGPR | BITS_32 | 86,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec2_86, Arch_amdgpu_vega | SGPR_VEC2 | BITS_64 | 86,"amdgpu_vega"); -DEF_REGISTER(sgpr87, Arch_amdgpu_vega | SGPR | BITS_32 | 87,"amdgpu_vega"); -DEF_REGISTER(sgpr88, Arch_amdgpu_vega | SGPR | BITS_32 | 88,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec2_88, Arch_amdgpu_vega | SGPR_VEC2 | BITS_64 | 88,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec4_88, Arch_amdgpu_vega | SGPR_VEC4 | BITS_128 | 88,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec8_88, Arch_amdgpu_vega | SGPR_VEC8 | BITS_256 | 88,"amdgpu_vega"); -DEF_REGISTER(sgpr89, Arch_amdgpu_vega | SGPR | BITS_32 | 89,"amdgpu_vega"); -DEF_REGISTER(sgpr90, Arch_amdgpu_vega | SGPR | BITS_32 | 90,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec2_90, Arch_amdgpu_vega | SGPR_VEC2 | BITS_64 | 90,"amdgpu_vega"); -DEF_REGISTER(sgpr91, Arch_amdgpu_vega | SGPR | BITS_32 | 91,"amdgpu_vega"); -DEF_REGISTER(sgpr92, Arch_amdgpu_vega | SGPR | BITS_32 | 92,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec2_92, Arch_amdgpu_vega | SGPR_VEC2 | BITS_64 | 92,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec4_92, Arch_amdgpu_vega | SGPR_VEC4 | BITS_128 | 92,"amdgpu_vega"); -DEF_REGISTER(sgpr93, Arch_amdgpu_vega | SGPR | BITS_32 | 93,"amdgpu_vega"); -DEF_REGISTER(sgpr94, Arch_amdgpu_vega | SGPR | BITS_32 | 94,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec2_94, Arch_amdgpu_vega | SGPR_VEC2 | BITS_64 | 94,"amdgpu_vega"); -DEF_REGISTER(sgpr95, Arch_amdgpu_vega | SGPR | BITS_32 | 95,"amdgpu_vega"); -DEF_REGISTER(sgpr96, Arch_amdgpu_vega | SGPR | BITS_32 | 96,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec2_96, Arch_amdgpu_vega | SGPR_VEC2 | BITS_64 | 96,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec4_96, Arch_amdgpu_vega | SGPR_VEC4 | BITS_128 | 96,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec8_96, Arch_amdgpu_vega | SGPR_VEC8 | BITS_256 | 96,"amdgpu_vega"); -DEF_REGISTER(sgpr97, Arch_amdgpu_vega | SGPR | BITS_32 | 97,"amdgpu_vega"); -DEF_REGISTER(sgpr98, Arch_amdgpu_vega | SGPR | BITS_32 | 98,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec2_98, Arch_amdgpu_vega | SGPR_VEC2 | BITS_64 | 98,"amdgpu_vega"); -DEF_REGISTER(sgpr99, Arch_amdgpu_vega | SGPR | BITS_32 | 99,"amdgpu_vega"); -DEF_REGISTER(sgpr100, Arch_amdgpu_vega | SGPR | BITS_32 | 100,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec2_100, Arch_amdgpu_vega | SGPR_VEC2 | BITS_64 | 100,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec4_100, Arch_amdgpu_vega | SGPR_VEC4 | BITS_128 | 100,"amdgpu_vega"); -DEF_REGISTER(sgpr101, Arch_amdgpu_vega | SGPR | BITS_32 | 101,"amdgpu_vega"); -DEF_REGISTER(sgpr102, Arch_amdgpu_vega | SGPR | BITS_32 | 102,"amdgpu_vega"); -DEF_REGISTER(sgpr_vec2_102, Arch_amdgpu_vega | SGPR_VEC2 | BITS_64 | 102,"amdgpu_vega"); -DEF_REGISTER(sgpr103, Arch_amdgpu_vega | SGPR | BITS_32 | 103,"amdgpu_vega"); -DEF_REGISTER(vgpr0, Arch_amdgpu_vega | VGPR | BITS_32 | 0,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_0, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 0,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_0, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 0,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_0, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 0,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_0, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 0,"amdgpu_vega"); -DEF_REGISTER(vgpr1, Arch_amdgpu_vega | VGPR | BITS_32 | 1,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_1, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 1,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_1, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 1,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_1, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 1,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_1, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 1,"amdgpu_vega"); -DEF_REGISTER(vgpr2, Arch_amdgpu_vega | VGPR | BITS_32 | 2,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_2, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 2,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_2, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 2,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_2, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 2,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_2, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 2,"amdgpu_vega"); -DEF_REGISTER(vgpr3, Arch_amdgpu_vega | VGPR | BITS_32 | 3,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_3, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 3,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_3, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 3,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_3, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 3,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_3, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 3,"amdgpu_vega"); -DEF_REGISTER(vgpr4, Arch_amdgpu_vega | VGPR | BITS_32 | 4,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_4, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 4,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_4, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 4,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_4, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 4,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_4, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 4,"amdgpu_vega"); -DEF_REGISTER(vgpr5, Arch_amdgpu_vega | VGPR | BITS_32 | 5,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_5, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 5,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_5, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 5,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_5, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 5,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_5, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 5,"amdgpu_vega"); -DEF_REGISTER(vgpr6, Arch_amdgpu_vega | VGPR | BITS_32 | 6,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_6, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 6,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_6, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 6,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_6, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 6,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_6, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 6,"amdgpu_vega"); -DEF_REGISTER(vgpr7, Arch_amdgpu_vega | VGPR | BITS_32 | 7,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_7, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 7,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_7, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 7,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_7, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 7,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_7, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 7,"amdgpu_vega"); -DEF_REGISTER(vgpr8, Arch_amdgpu_vega | VGPR | BITS_32 | 8,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_8, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 8,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_8, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 8,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_8, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 8,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_8, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 8,"amdgpu_vega"); -DEF_REGISTER(vgpr9, Arch_amdgpu_vega | VGPR | BITS_32 | 9,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_9, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 9,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_9, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 9,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_9, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 9,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_9, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 9,"amdgpu_vega"); -DEF_REGISTER(vgpr10, Arch_amdgpu_vega | VGPR | BITS_32 | 10,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_10, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 10,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_10, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 10,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_10, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 10,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_10, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 10,"amdgpu_vega"); -DEF_REGISTER(vgpr11, Arch_amdgpu_vega | VGPR | BITS_32 | 11,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_11, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 11,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_11, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 11,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_11, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 11,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_11, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 11,"amdgpu_vega"); -DEF_REGISTER(vgpr12, Arch_amdgpu_vega | VGPR | BITS_32 | 12,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_12, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 12,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_12, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 12,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_12, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 12,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_12, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 12,"amdgpu_vega"); -DEF_REGISTER(vgpr13, Arch_amdgpu_vega | VGPR | BITS_32 | 13,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_13, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 13,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_13, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 13,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_13, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 13,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_13, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 13,"amdgpu_vega"); -DEF_REGISTER(vgpr14, Arch_amdgpu_vega | VGPR | BITS_32 | 14,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_14, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 14,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_14, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 14,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_14, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 14,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_14, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 14,"amdgpu_vega"); -DEF_REGISTER(vgpr15, Arch_amdgpu_vega | VGPR | BITS_32 | 15,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_15, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 15,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_15, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 15,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_15, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 15,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_15, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 15,"amdgpu_vega"); -DEF_REGISTER(vgpr16, Arch_amdgpu_vega | VGPR | BITS_32 | 16,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_16, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 16,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_16, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 16,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_16, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 16,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_16, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 16,"amdgpu_vega"); -DEF_REGISTER(vgpr17, Arch_amdgpu_vega | VGPR | BITS_32 | 17,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_17, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 17,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_17, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 17,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_17, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 17,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_17, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 17,"amdgpu_vega"); -DEF_REGISTER(vgpr18, Arch_amdgpu_vega | VGPR | BITS_32 | 18,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_18, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 18,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_18, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 18,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_18, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 18,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_18, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 18,"amdgpu_vega"); -DEF_REGISTER(vgpr19, Arch_amdgpu_vega | VGPR | BITS_32 | 19,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_19, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 19,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_19, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 19,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_19, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 19,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_19, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 19,"amdgpu_vega"); -DEF_REGISTER(vgpr20, Arch_amdgpu_vega | VGPR | BITS_32 | 20,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_20, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 20,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_20, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 20,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_20, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 20,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_20, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 20,"amdgpu_vega"); -DEF_REGISTER(vgpr21, Arch_amdgpu_vega | VGPR | BITS_32 | 21,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_21, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 21,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_21, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 21,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_21, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 21,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_21, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 21,"amdgpu_vega"); -DEF_REGISTER(vgpr22, Arch_amdgpu_vega | VGPR | BITS_32 | 22,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_22, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 22,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_22, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 22,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_22, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 22,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_22, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 22,"amdgpu_vega"); -DEF_REGISTER(vgpr23, Arch_amdgpu_vega | VGPR | BITS_32 | 23,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_23, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 23,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_23, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 23,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_23, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 23,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_23, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 23,"amdgpu_vega"); -DEF_REGISTER(vgpr24, Arch_amdgpu_vega | VGPR | BITS_32 | 24,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_24, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 24,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_24, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 24,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_24, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 24,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_24, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 24,"amdgpu_vega"); -DEF_REGISTER(vgpr25, Arch_amdgpu_vega | VGPR | BITS_32 | 25,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_25, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 25,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_25, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 25,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_25, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 25,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_25, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 25,"amdgpu_vega"); -DEF_REGISTER(vgpr26, Arch_amdgpu_vega | VGPR | BITS_32 | 26,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_26, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 26,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_26, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 26,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_26, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 26,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_26, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 26,"amdgpu_vega"); -DEF_REGISTER(vgpr27, Arch_amdgpu_vega | VGPR | BITS_32 | 27,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_27, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 27,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_27, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 27,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_27, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 27,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_27, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 27,"amdgpu_vega"); -DEF_REGISTER(vgpr28, Arch_amdgpu_vega | VGPR | BITS_32 | 28,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_28, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 28,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_28, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 28,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_28, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 28,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_28, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 28,"amdgpu_vega"); -DEF_REGISTER(vgpr29, Arch_amdgpu_vega | VGPR | BITS_32 | 29,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_29, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 29,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_29, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 29,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_29, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 29,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_29, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 29,"amdgpu_vega"); -DEF_REGISTER(vgpr30, Arch_amdgpu_vega | VGPR | BITS_32 | 30,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_30, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 30,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_30, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 30,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_30, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 30,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_30, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 30,"amdgpu_vega"); -DEF_REGISTER(vgpr31, Arch_amdgpu_vega | VGPR | BITS_32 | 31,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_31, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 31,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_31, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 31,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_31, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 31,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_31, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 31,"amdgpu_vega"); -DEF_REGISTER(vgpr32, Arch_amdgpu_vega | VGPR | BITS_32 | 32,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_32, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 32,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_32, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 32,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_32, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 32,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_32, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 32,"amdgpu_vega"); -DEF_REGISTER(vgpr33, Arch_amdgpu_vega | VGPR | BITS_32 | 33,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_33, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 33,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_33, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 33,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_33, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 33,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_33, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 33,"amdgpu_vega"); -DEF_REGISTER(vgpr34, Arch_amdgpu_vega | VGPR | BITS_32 | 34,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_34, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 34,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_34, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 34,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_34, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 34,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_34, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 34,"amdgpu_vega"); -DEF_REGISTER(vgpr35, Arch_amdgpu_vega | VGPR | BITS_32 | 35,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_35, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 35,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_35, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 35,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_35, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 35,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_35, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 35,"amdgpu_vega"); -DEF_REGISTER(vgpr36, Arch_amdgpu_vega | VGPR | BITS_32 | 36,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_36, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 36,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_36, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 36,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_36, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 36,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_36, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 36,"amdgpu_vega"); -DEF_REGISTER(vgpr37, Arch_amdgpu_vega | VGPR | BITS_32 | 37,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_37, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 37,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_37, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 37,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_37, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 37,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_37, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 37,"amdgpu_vega"); -DEF_REGISTER(vgpr38, Arch_amdgpu_vega | VGPR | BITS_32 | 38,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_38, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 38,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_38, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 38,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_38, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 38,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_38, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 38,"amdgpu_vega"); -DEF_REGISTER(vgpr39, Arch_amdgpu_vega | VGPR | BITS_32 | 39,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_39, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 39,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_39, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 39,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_39, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 39,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_39, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 39,"amdgpu_vega"); -DEF_REGISTER(vgpr40, Arch_amdgpu_vega | VGPR | BITS_32 | 40,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_40, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 40,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_40, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 40,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_40, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 40,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_40, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 40,"amdgpu_vega"); -DEF_REGISTER(vgpr41, Arch_amdgpu_vega | VGPR | BITS_32 | 41,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_41, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 41,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_41, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 41,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_41, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 41,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_41, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 41,"amdgpu_vega"); -DEF_REGISTER(vgpr42, Arch_amdgpu_vega | VGPR | BITS_32 | 42,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_42, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 42,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_42, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 42,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_42, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 42,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_42, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 42,"amdgpu_vega"); -DEF_REGISTER(vgpr43, Arch_amdgpu_vega | VGPR | BITS_32 | 43,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_43, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 43,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_43, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 43,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_43, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 43,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_43, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 43,"amdgpu_vega"); -DEF_REGISTER(vgpr44, Arch_amdgpu_vega | VGPR | BITS_32 | 44,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_44, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 44,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_44, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 44,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_44, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 44,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_44, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 44,"amdgpu_vega"); -DEF_REGISTER(vgpr45, Arch_amdgpu_vega | VGPR | BITS_32 | 45,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_45, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 45,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_45, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 45,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_45, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 45,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_45, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 45,"amdgpu_vega"); -DEF_REGISTER(vgpr46, Arch_amdgpu_vega | VGPR | BITS_32 | 46,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_46, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 46,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_46, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 46,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_46, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 46,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_46, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 46,"amdgpu_vega"); -DEF_REGISTER(vgpr47, Arch_amdgpu_vega | VGPR | BITS_32 | 47,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_47, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 47,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_47, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 47,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_47, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 47,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_47, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 47,"amdgpu_vega"); -DEF_REGISTER(vgpr48, Arch_amdgpu_vega | VGPR | BITS_32 | 48,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_48, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 48,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_48, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 48,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_48, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 48,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_48, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 48,"amdgpu_vega"); -DEF_REGISTER(vgpr49, Arch_amdgpu_vega | VGPR | BITS_32 | 49,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_49, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 49,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_49, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 49,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_49, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 49,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_49, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 49,"amdgpu_vega"); -DEF_REGISTER(vgpr50, Arch_amdgpu_vega | VGPR | BITS_32 | 50,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_50, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 50,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_50, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 50,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_50, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 50,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_50, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 50,"amdgpu_vega"); -DEF_REGISTER(vgpr51, Arch_amdgpu_vega | VGPR | BITS_32 | 51,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_51, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 51,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_51, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 51,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_51, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 51,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_51, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 51,"amdgpu_vega"); -DEF_REGISTER(vgpr52, Arch_amdgpu_vega | VGPR | BITS_32 | 52,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_52, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 52,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_52, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 52,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_52, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 52,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_52, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 52,"amdgpu_vega"); -DEF_REGISTER(vgpr53, Arch_amdgpu_vega | VGPR | BITS_32 | 53,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_53, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 53,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_53, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 53,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_53, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 53,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_53, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 53,"amdgpu_vega"); -DEF_REGISTER(vgpr54, Arch_amdgpu_vega | VGPR | BITS_32 | 54,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_54, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 54,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_54, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 54,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_54, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 54,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_54, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 54,"amdgpu_vega"); -DEF_REGISTER(vgpr55, Arch_amdgpu_vega | VGPR | BITS_32 | 55,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_55, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 55,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_55, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 55,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_55, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 55,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_55, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 55,"amdgpu_vega"); -DEF_REGISTER(vgpr56, Arch_amdgpu_vega | VGPR | BITS_32 | 56,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_56, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 56,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_56, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 56,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_56, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 56,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_56, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 56,"amdgpu_vega"); -DEF_REGISTER(vgpr57, Arch_amdgpu_vega | VGPR | BITS_32 | 57,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_57, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 57,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_57, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 57,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_57, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 57,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_57, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 57,"amdgpu_vega"); -DEF_REGISTER(vgpr58, Arch_amdgpu_vega | VGPR | BITS_32 | 58,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_58, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 58,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_58, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 58,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_58, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 58,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_58, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 58,"amdgpu_vega"); -DEF_REGISTER(vgpr59, Arch_amdgpu_vega | VGPR | BITS_32 | 59,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_59, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 59,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_59, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 59,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_59, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 59,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_59, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 59,"amdgpu_vega"); -DEF_REGISTER(vgpr60, Arch_amdgpu_vega | VGPR | BITS_32 | 60,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_60, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 60,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_60, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 60,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_60, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 60,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_60, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 60,"amdgpu_vega"); -DEF_REGISTER(vgpr61, Arch_amdgpu_vega | VGPR | BITS_32 | 61,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_61, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 61,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_61, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 61,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_61, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 61,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_61, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 61,"amdgpu_vega"); -DEF_REGISTER(vgpr62, Arch_amdgpu_vega | VGPR | BITS_32 | 62,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_62, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 62,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_62, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 62,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_62, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 62,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_62, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 62,"amdgpu_vega"); -DEF_REGISTER(vgpr63, Arch_amdgpu_vega | VGPR | BITS_32 | 63,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_63, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 63,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_63, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 63,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_63, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 63,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_63, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 63,"amdgpu_vega"); -DEF_REGISTER(vgpr64, Arch_amdgpu_vega | VGPR | BITS_32 | 64,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_64, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 64,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_64, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 64,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_64, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 64,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_64, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 64,"amdgpu_vega"); -DEF_REGISTER(vgpr65, Arch_amdgpu_vega | VGPR | BITS_32 | 65,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_65, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 65,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_65, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 65,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_65, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 65,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_65, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 65,"amdgpu_vega"); -DEF_REGISTER(vgpr66, Arch_amdgpu_vega | VGPR | BITS_32 | 66,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_66, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 66,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_66, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 66,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_66, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 66,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_66, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 66,"amdgpu_vega"); -DEF_REGISTER(vgpr67, Arch_amdgpu_vega | VGPR | BITS_32 | 67,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_67, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 67,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_67, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 67,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_67, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 67,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_67, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 67,"amdgpu_vega"); -DEF_REGISTER(vgpr68, Arch_amdgpu_vega | VGPR | BITS_32 | 68,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_68, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 68,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_68, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 68,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_68, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 68,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_68, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 68,"amdgpu_vega"); -DEF_REGISTER(vgpr69, Arch_amdgpu_vega | VGPR | BITS_32 | 69,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_69, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 69,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_69, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 69,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_69, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 69,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_69, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 69,"amdgpu_vega"); -DEF_REGISTER(vgpr70, Arch_amdgpu_vega | VGPR | BITS_32 | 70,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_70, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 70,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_70, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 70,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_70, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 70,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_70, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 70,"amdgpu_vega"); -DEF_REGISTER(vgpr71, Arch_amdgpu_vega | VGPR | BITS_32 | 71,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_71, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 71,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_71, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 71,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_71, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 71,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_71, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 71,"amdgpu_vega"); -DEF_REGISTER(vgpr72, Arch_amdgpu_vega | VGPR | BITS_32 | 72,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_72, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 72,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_72, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 72,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_72, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 72,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_72, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 72,"amdgpu_vega"); -DEF_REGISTER(vgpr73, Arch_amdgpu_vega | VGPR | BITS_32 | 73,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_73, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 73,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_73, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 73,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_73, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 73,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_73, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 73,"amdgpu_vega"); -DEF_REGISTER(vgpr74, Arch_amdgpu_vega | VGPR | BITS_32 | 74,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_74, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 74,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_74, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 74,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_74, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 74,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_74, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 74,"amdgpu_vega"); -DEF_REGISTER(vgpr75, Arch_amdgpu_vega | VGPR | BITS_32 | 75,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_75, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 75,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_75, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 75,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_75, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 75,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_75, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 75,"amdgpu_vega"); -DEF_REGISTER(vgpr76, Arch_amdgpu_vega | VGPR | BITS_32 | 76,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_76, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 76,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_76, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 76,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_76, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 76,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_76, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 76,"amdgpu_vega"); -DEF_REGISTER(vgpr77, Arch_amdgpu_vega | VGPR | BITS_32 | 77,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_77, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 77,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_77, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 77,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_77, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 77,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_77, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 77,"amdgpu_vega"); -DEF_REGISTER(vgpr78, Arch_amdgpu_vega | VGPR | BITS_32 | 78,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_78, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 78,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_78, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 78,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_78, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 78,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_78, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 78,"amdgpu_vega"); -DEF_REGISTER(vgpr79, Arch_amdgpu_vega | VGPR | BITS_32 | 79,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_79, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 79,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_79, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 79,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_79, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 79,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_79, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 79,"amdgpu_vega"); -DEF_REGISTER(vgpr80, Arch_amdgpu_vega | VGPR | BITS_32 | 80,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_80, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 80,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_80, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 80,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_80, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 80,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_80, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 80,"amdgpu_vega"); -DEF_REGISTER(vgpr81, Arch_amdgpu_vega | VGPR | BITS_32 | 81,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_81, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 81,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_81, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 81,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_81, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 81,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_81, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 81,"amdgpu_vega"); -DEF_REGISTER(vgpr82, Arch_amdgpu_vega | VGPR | BITS_32 | 82,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_82, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 82,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_82, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 82,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_82, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 82,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_82, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 82,"amdgpu_vega"); -DEF_REGISTER(vgpr83, Arch_amdgpu_vega | VGPR | BITS_32 | 83,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_83, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 83,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_83, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 83,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_83, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 83,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_83, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 83,"amdgpu_vega"); -DEF_REGISTER(vgpr84, Arch_amdgpu_vega | VGPR | BITS_32 | 84,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_84, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 84,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_84, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 84,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_84, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 84,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_84, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 84,"amdgpu_vega"); -DEF_REGISTER(vgpr85, Arch_amdgpu_vega | VGPR | BITS_32 | 85,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_85, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 85,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_85, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 85,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_85, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 85,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_85, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 85,"amdgpu_vega"); -DEF_REGISTER(vgpr86, Arch_amdgpu_vega | VGPR | BITS_32 | 86,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_86, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 86,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_86, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 86,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_86, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 86,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_86, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 86,"amdgpu_vega"); -DEF_REGISTER(vgpr87, Arch_amdgpu_vega | VGPR | BITS_32 | 87,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_87, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 87,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_87, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 87,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_87, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 87,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_87, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 87,"amdgpu_vega"); -DEF_REGISTER(vgpr88, Arch_amdgpu_vega | VGPR | BITS_32 | 88,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_88, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 88,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_88, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 88,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_88, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 88,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_88, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 88,"amdgpu_vega"); -DEF_REGISTER(vgpr89, Arch_amdgpu_vega | VGPR | BITS_32 | 89,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_89, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 89,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_89, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 89,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_89, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 89,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_89, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 89,"amdgpu_vega"); -DEF_REGISTER(vgpr90, Arch_amdgpu_vega | VGPR | BITS_32 | 90,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_90, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 90,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_90, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 90,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_90, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 90,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_90, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 90,"amdgpu_vega"); -DEF_REGISTER(vgpr91, Arch_amdgpu_vega | VGPR | BITS_32 | 91,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_91, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 91,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_91, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 91,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_91, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 91,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_91, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 91,"amdgpu_vega"); -DEF_REGISTER(vgpr92, Arch_amdgpu_vega | VGPR | BITS_32 | 92,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_92, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 92,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_92, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 92,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_92, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 92,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_92, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 92,"amdgpu_vega"); -DEF_REGISTER(vgpr93, Arch_amdgpu_vega | VGPR | BITS_32 | 93,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_93, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 93,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_93, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 93,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_93, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 93,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_93, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 93,"amdgpu_vega"); -DEF_REGISTER(vgpr94, Arch_amdgpu_vega | VGPR | BITS_32 | 94,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_94, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 94,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_94, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 94,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_94, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 94,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_94, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 94,"amdgpu_vega"); -DEF_REGISTER(vgpr95, Arch_amdgpu_vega | VGPR | BITS_32 | 95,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_95, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 95,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_95, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 95,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_95, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 95,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_95, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 95,"amdgpu_vega"); -DEF_REGISTER(vgpr96, Arch_amdgpu_vega | VGPR | BITS_32 | 96,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_96, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 96,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_96, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 96,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_96, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 96,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_96, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 96,"amdgpu_vega"); -DEF_REGISTER(vgpr97, Arch_amdgpu_vega | VGPR | BITS_32 | 97,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_97, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 97,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_97, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 97,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_97, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 97,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_97, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 97,"amdgpu_vega"); -DEF_REGISTER(vgpr98, Arch_amdgpu_vega | VGPR | BITS_32 | 98,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_98, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 98,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_98, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 98,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_98, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 98,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_98, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 98,"amdgpu_vega"); -DEF_REGISTER(vgpr99, Arch_amdgpu_vega | VGPR | BITS_32 | 99,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_99, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 99,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_99, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 99,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_99, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 99,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_99, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 99,"amdgpu_vega"); -DEF_REGISTER(vgpr100, Arch_amdgpu_vega | VGPR | BITS_32 | 100,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_100, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 100,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_100, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 100,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_100, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 100,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_100, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 100,"amdgpu_vega"); -DEF_REGISTER(vgpr101, Arch_amdgpu_vega | VGPR | BITS_32 | 101,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_101, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 101,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_101, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 101,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_101, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 101,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_101, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 101,"amdgpu_vega"); -DEF_REGISTER(vgpr102, Arch_amdgpu_vega | VGPR | BITS_32 | 102,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_102, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 102,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_102, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 102,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_102, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 102,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_102, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 102,"amdgpu_vega"); -DEF_REGISTER(vgpr103, Arch_amdgpu_vega | VGPR | BITS_32 | 103,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_103, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 103,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_103, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 103,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_103, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 103,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_103, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 103,"amdgpu_vega"); -DEF_REGISTER(vgpr104, Arch_amdgpu_vega | VGPR | BITS_32 | 104,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_104, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 104,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_104, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 104,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_104, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 104,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_104, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 104,"amdgpu_vega"); -DEF_REGISTER(vgpr105, Arch_amdgpu_vega | VGPR | BITS_32 | 105,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_105, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 105,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_105, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 105,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_105, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 105,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_105, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 105,"amdgpu_vega"); -DEF_REGISTER(vgpr106, Arch_amdgpu_vega | VGPR | BITS_32 | 106,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_106, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 106,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_106, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 106,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_106, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 106,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_106, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 106,"amdgpu_vega"); -DEF_REGISTER(vgpr107, Arch_amdgpu_vega | VGPR | BITS_32 | 107,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_107, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 107,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_107, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 107,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_107, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 107,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_107, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 107,"amdgpu_vega"); -DEF_REGISTER(vgpr108, Arch_amdgpu_vega | VGPR | BITS_32 | 108,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_108, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 108,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_108, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 108,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_108, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 108,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_108, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 108,"amdgpu_vega"); -DEF_REGISTER(vgpr109, Arch_amdgpu_vega | VGPR | BITS_32 | 109,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_109, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 109,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_109, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 109,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_109, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 109,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_109, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 109,"amdgpu_vega"); -DEF_REGISTER(vgpr110, Arch_amdgpu_vega | VGPR | BITS_32 | 110,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_110, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 110,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_110, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 110,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_110, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 110,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_110, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 110,"amdgpu_vega"); -DEF_REGISTER(vgpr111, Arch_amdgpu_vega | VGPR | BITS_32 | 111,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_111, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 111,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_111, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 111,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_111, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 111,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_111, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 111,"amdgpu_vega"); -DEF_REGISTER(vgpr112, Arch_amdgpu_vega | VGPR | BITS_32 | 112,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_112, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 112,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_112, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 112,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_112, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 112,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_112, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 112,"amdgpu_vega"); -DEF_REGISTER(vgpr113, Arch_amdgpu_vega | VGPR | BITS_32 | 113,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_113, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 113,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_113, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 113,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_113, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 113,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_113, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 113,"amdgpu_vega"); -DEF_REGISTER(vgpr114, Arch_amdgpu_vega | VGPR | BITS_32 | 114,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_114, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 114,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_114, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 114,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_114, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 114,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_114, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 114,"amdgpu_vega"); -DEF_REGISTER(vgpr115, Arch_amdgpu_vega | VGPR | BITS_32 | 115,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_115, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 115,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_115, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 115,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_115, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 115,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_115, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 115,"amdgpu_vega"); -DEF_REGISTER(vgpr116, Arch_amdgpu_vega | VGPR | BITS_32 | 116,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_116, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 116,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_116, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 116,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_116, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 116,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_116, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 116,"amdgpu_vega"); -DEF_REGISTER(vgpr117, Arch_amdgpu_vega | VGPR | BITS_32 | 117,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_117, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 117,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_117, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 117,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_117, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 117,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_117, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 117,"amdgpu_vega"); -DEF_REGISTER(vgpr118, Arch_amdgpu_vega | VGPR | BITS_32 | 118,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_118, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 118,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_118, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 118,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_118, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 118,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_118, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 118,"amdgpu_vega"); -DEF_REGISTER(vgpr119, Arch_amdgpu_vega | VGPR | BITS_32 | 119,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_119, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 119,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_119, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 119,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_119, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 119,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_119, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 119,"amdgpu_vega"); -DEF_REGISTER(vgpr120, Arch_amdgpu_vega | VGPR | BITS_32 | 120,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_120, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 120,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_120, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 120,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_120, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 120,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_120, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 120,"amdgpu_vega"); -DEF_REGISTER(vgpr121, Arch_amdgpu_vega | VGPR | BITS_32 | 121,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_121, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 121,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_121, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 121,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_121, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 121,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_121, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 121,"amdgpu_vega"); -DEF_REGISTER(vgpr122, Arch_amdgpu_vega | VGPR | BITS_32 | 122,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_122, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 122,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_122, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 122,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_122, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 122,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_122, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 122,"amdgpu_vega"); -DEF_REGISTER(vgpr123, Arch_amdgpu_vega | VGPR | BITS_32 | 123,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_123, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 123,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_123, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 123,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_123, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 123,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_123, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 123,"amdgpu_vega"); -DEF_REGISTER(vgpr124, Arch_amdgpu_vega | VGPR | BITS_32 | 124,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_124, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 124,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_124, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 124,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_124, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 124,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_124, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 124,"amdgpu_vega"); -DEF_REGISTER(vgpr125, Arch_amdgpu_vega | VGPR | BITS_32 | 125,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_125, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 125,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_125, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 125,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_125, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 125,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_125, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 125,"amdgpu_vega"); -DEF_REGISTER(vgpr126, Arch_amdgpu_vega | VGPR | BITS_32 | 126,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_126, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 126,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_126, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 126,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_126, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 126,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_126, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 126,"amdgpu_vega"); -DEF_REGISTER(vgpr127, Arch_amdgpu_vega | VGPR | BITS_32 | 127,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_127, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 127,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_127, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 127,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_127, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 127,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_127, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 127,"amdgpu_vega"); -DEF_REGISTER(vgpr128, Arch_amdgpu_vega | VGPR | BITS_32 | 128,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_128, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 128,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_128, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 128,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_128, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 128,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_128, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 128,"amdgpu_vega"); -DEF_REGISTER(vgpr129, Arch_amdgpu_vega | VGPR | BITS_32 | 129,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_129, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 129,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_129, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 129,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_129, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 129,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_129, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 129,"amdgpu_vega"); -DEF_REGISTER(vgpr130, Arch_amdgpu_vega | VGPR | BITS_32 | 130,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_130, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 130,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_130, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 130,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_130, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 130,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_130, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 130,"amdgpu_vega"); -DEF_REGISTER(vgpr131, Arch_amdgpu_vega | VGPR | BITS_32 | 131,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_131, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 131,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_131, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 131,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_131, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 131,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_131, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 131,"amdgpu_vega"); -DEF_REGISTER(vgpr132, Arch_amdgpu_vega | VGPR | BITS_32 | 132,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_132, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 132,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_132, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 132,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_132, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 132,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_132, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 132,"amdgpu_vega"); -DEF_REGISTER(vgpr133, Arch_amdgpu_vega | VGPR | BITS_32 | 133,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_133, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 133,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_133, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 133,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_133, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 133,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_133, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 133,"amdgpu_vega"); -DEF_REGISTER(vgpr134, Arch_amdgpu_vega | VGPR | BITS_32 | 134,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_134, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 134,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_134, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 134,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_134, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 134,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_134, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 134,"amdgpu_vega"); -DEF_REGISTER(vgpr135, Arch_amdgpu_vega | VGPR | BITS_32 | 135,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_135, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 135,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_135, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 135,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_135, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 135,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_135, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 135,"amdgpu_vega"); -DEF_REGISTER(vgpr136, Arch_amdgpu_vega | VGPR | BITS_32 | 136,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_136, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 136,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_136, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 136,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_136, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 136,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_136, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 136,"amdgpu_vega"); -DEF_REGISTER(vgpr137, Arch_amdgpu_vega | VGPR | BITS_32 | 137,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_137, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 137,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_137, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 137,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_137, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 137,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_137, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 137,"amdgpu_vega"); -DEF_REGISTER(vgpr138, Arch_amdgpu_vega | VGPR | BITS_32 | 138,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_138, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 138,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_138, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 138,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_138, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 138,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_138, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 138,"amdgpu_vega"); -DEF_REGISTER(vgpr139, Arch_amdgpu_vega | VGPR | BITS_32 | 139,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_139, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 139,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_139, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 139,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_139, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 139,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_139, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 139,"amdgpu_vega"); -DEF_REGISTER(vgpr140, Arch_amdgpu_vega | VGPR | BITS_32 | 140,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_140, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 140,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_140, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 140,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_140, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 140,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_140, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 140,"amdgpu_vega"); -DEF_REGISTER(vgpr141, Arch_amdgpu_vega | VGPR | BITS_32 | 141,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_141, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 141,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_141, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 141,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_141, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 141,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_141, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 141,"amdgpu_vega"); -DEF_REGISTER(vgpr142, Arch_amdgpu_vega | VGPR | BITS_32 | 142,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_142, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 142,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_142, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 142,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_142, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 142,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_142, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 142,"amdgpu_vega"); -DEF_REGISTER(vgpr143, Arch_amdgpu_vega | VGPR | BITS_32 | 143,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_143, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 143,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_143, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 143,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_143, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 143,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_143, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 143,"amdgpu_vega"); -DEF_REGISTER(vgpr144, Arch_amdgpu_vega | VGPR | BITS_32 | 144,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_144, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 144,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_144, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 144,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_144, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 144,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_144, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 144,"amdgpu_vega"); -DEF_REGISTER(vgpr145, Arch_amdgpu_vega | VGPR | BITS_32 | 145,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_145, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 145,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_145, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 145,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_145, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 145,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_145, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 145,"amdgpu_vega"); -DEF_REGISTER(vgpr146, Arch_amdgpu_vega | VGPR | BITS_32 | 146,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_146, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 146,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_146, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 146,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_146, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 146,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_146, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 146,"amdgpu_vega"); -DEF_REGISTER(vgpr147, Arch_amdgpu_vega | VGPR | BITS_32 | 147,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_147, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 147,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_147, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 147,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_147, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 147,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_147, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 147,"amdgpu_vega"); -DEF_REGISTER(vgpr148, Arch_amdgpu_vega | VGPR | BITS_32 | 148,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_148, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 148,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_148, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 148,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_148, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 148,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_148, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 148,"amdgpu_vega"); -DEF_REGISTER(vgpr149, Arch_amdgpu_vega | VGPR | BITS_32 | 149,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_149, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 149,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_149, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 149,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_149, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 149,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_149, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 149,"amdgpu_vega"); -DEF_REGISTER(vgpr150, Arch_amdgpu_vega | VGPR | BITS_32 | 150,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_150, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 150,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_150, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 150,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_150, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 150,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_150, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 150,"amdgpu_vega"); -DEF_REGISTER(vgpr151, Arch_amdgpu_vega | VGPR | BITS_32 | 151,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_151, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 151,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_151, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 151,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_151, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 151,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_151, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 151,"amdgpu_vega"); -DEF_REGISTER(vgpr152, Arch_amdgpu_vega | VGPR | BITS_32 | 152,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_152, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 152,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_152, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 152,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_152, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 152,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_152, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 152,"amdgpu_vega"); -DEF_REGISTER(vgpr153, Arch_amdgpu_vega | VGPR | BITS_32 | 153,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_153, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 153,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_153, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 153,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_153, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 153,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_153, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 153,"amdgpu_vega"); -DEF_REGISTER(vgpr154, Arch_amdgpu_vega | VGPR | BITS_32 | 154,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_154, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 154,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_154, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 154,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_154, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 154,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_154, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 154,"amdgpu_vega"); -DEF_REGISTER(vgpr155, Arch_amdgpu_vega | VGPR | BITS_32 | 155,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_155, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 155,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_155, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 155,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_155, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 155,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_155, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 155,"amdgpu_vega"); -DEF_REGISTER(vgpr156, Arch_amdgpu_vega | VGPR | BITS_32 | 156,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_156, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 156,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_156, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 156,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_156, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 156,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_156, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 156,"amdgpu_vega"); -DEF_REGISTER(vgpr157, Arch_amdgpu_vega | VGPR | BITS_32 | 157,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_157, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 157,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_157, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 157,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_157, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 157,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_157, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 157,"amdgpu_vega"); -DEF_REGISTER(vgpr158, Arch_amdgpu_vega | VGPR | BITS_32 | 158,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_158, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 158,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_158, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 158,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_158, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 158,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_158, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 158,"amdgpu_vega"); -DEF_REGISTER(vgpr159, Arch_amdgpu_vega | VGPR | BITS_32 | 159,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_159, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 159,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_159, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 159,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_159, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 159,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_159, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 159,"amdgpu_vega"); -DEF_REGISTER(vgpr160, Arch_amdgpu_vega | VGPR | BITS_32 | 160,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_160, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 160,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_160, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 160,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_160, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 160,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_160, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 160,"amdgpu_vega"); -DEF_REGISTER(vgpr161, Arch_amdgpu_vega | VGPR | BITS_32 | 161,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_161, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 161,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_161, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 161,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_161, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 161,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_161, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 161,"amdgpu_vega"); -DEF_REGISTER(vgpr162, Arch_amdgpu_vega | VGPR | BITS_32 | 162,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_162, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 162,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_162, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 162,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_162, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 162,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_162, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 162,"amdgpu_vega"); -DEF_REGISTER(vgpr163, Arch_amdgpu_vega | VGPR | BITS_32 | 163,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_163, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 163,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_163, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 163,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_163, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 163,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_163, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 163,"amdgpu_vega"); -DEF_REGISTER(vgpr164, Arch_amdgpu_vega | VGPR | BITS_32 | 164,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_164, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 164,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_164, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 164,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_164, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 164,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_164, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 164,"amdgpu_vega"); -DEF_REGISTER(vgpr165, Arch_amdgpu_vega | VGPR | BITS_32 | 165,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_165, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 165,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_165, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 165,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_165, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 165,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_165, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 165,"amdgpu_vega"); -DEF_REGISTER(vgpr166, Arch_amdgpu_vega | VGPR | BITS_32 | 166,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_166, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 166,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_166, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 166,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_166, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 166,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_166, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 166,"amdgpu_vega"); -DEF_REGISTER(vgpr167, Arch_amdgpu_vega | VGPR | BITS_32 | 167,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_167, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 167,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_167, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 167,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_167, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 167,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_167, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 167,"amdgpu_vega"); -DEF_REGISTER(vgpr168, Arch_amdgpu_vega | VGPR | BITS_32 | 168,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_168, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 168,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_168, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 168,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_168, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 168,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_168, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 168,"amdgpu_vega"); -DEF_REGISTER(vgpr169, Arch_amdgpu_vega | VGPR | BITS_32 | 169,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_169, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 169,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_169, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 169,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_169, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 169,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_169, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 169,"amdgpu_vega"); -DEF_REGISTER(vgpr170, Arch_amdgpu_vega | VGPR | BITS_32 | 170,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_170, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 170,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_170, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 170,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_170, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 170,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_170, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 170,"amdgpu_vega"); -DEF_REGISTER(vgpr171, Arch_amdgpu_vega | VGPR | BITS_32 | 171,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_171, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 171,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_171, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 171,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_171, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 171,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_171, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 171,"amdgpu_vega"); -DEF_REGISTER(vgpr172, Arch_amdgpu_vega | VGPR | BITS_32 | 172,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_172, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 172,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_172, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 172,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_172, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 172,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_172, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 172,"amdgpu_vega"); -DEF_REGISTER(vgpr173, Arch_amdgpu_vega | VGPR | BITS_32 | 173,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_173, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 173,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_173, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 173,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_173, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 173,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_173, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 173,"amdgpu_vega"); -DEF_REGISTER(vgpr174, Arch_amdgpu_vega | VGPR | BITS_32 | 174,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_174, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 174,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_174, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 174,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_174, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 174,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_174, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 174,"amdgpu_vega"); -DEF_REGISTER(vgpr175, Arch_amdgpu_vega | VGPR | BITS_32 | 175,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_175, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 175,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_175, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 175,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_175, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 175,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_175, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 175,"amdgpu_vega"); -DEF_REGISTER(vgpr176, Arch_amdgpu_vega | VGPR | BITS_32 | 176,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_176, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 176,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_176, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 176,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_176, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 176,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_176, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 176,"amdgpu_vega"); -DEF_REGISTER(vgpr177, Arch_amdgpu_vega | VGPR | BITS_32 | 177,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_177, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 177,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_177, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 177,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_177, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 177,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_177, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 177,"amdgpu_vega"); -DEF_REGISTER(vgpr178, Arch_amdgpu_vega | VGPR | BITS_32 | 178,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_178, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 178,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_178, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 178,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_178, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 178,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_178, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 178,"amdgpu_vega"); -DEF_REGISTER(vgpr179, Arch_amdgpu_vega | VGPR | BITS_32 | 179,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_179, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 179,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_179, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 179,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_179, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 179,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_179, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 179,"amdgpu_vega"); -DEF_REGISTER(vgpr180, Arch_amdgpu_vega | VGPR | BITS_32 | 180,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_180, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 180,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_180, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 180,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_180, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 180,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_180, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 180,"amdgpu_vega"); -DEF_REGISTER(vgpr181, Arch_amdgpu_vega | VGPR | BITS_32 | 181,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_181, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 181,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_181, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 181,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_181, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 181,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_181, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 181,"amdgpu_vega"); -DEF_REGISTER(vgpr182, Arch_amdgpu_vega | VGPR | BITS_32 | 182,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_182, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 182,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_182, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 182,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_182, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 182,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_182, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 182,"amdgpu_vega"); -DEF_REGISTER(vgpr183, Arch_amdgpu_vega | VGPR | BITS_32 | 183,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_183, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 183,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_183, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 183,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_183, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 183,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_183, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 183,"amdgpu_vega"); -DEF_REGISTER(vgpr184, Arch_amdgpu_vega | VGPR | BITS_32 | 184,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_184, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 184,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_184, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 184,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_184, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 184,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_184, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 184,"amdgpu_vega"); -DEF_REGISTER(vgpr185, Arch_amdgpu_vega | VGPR | BITS_32 | 185,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_185, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 185,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_185, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 185,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_185, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 185,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_185, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 185,"amdgpu_vega"); -DEF_REGISTER(vgpr186, Arch_amdgpu_vega | VGPR | BITS_32 | 186,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_186, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 186,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_186, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 186,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_186, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 186,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_186, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 186,"amdgpu_vega"); -DEF_REGISTER(vgpr187, Arch_amdgpu_vega | VGPR | BITS_32 | 187,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_187, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 187,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_187, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 187,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_187, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 187,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_187, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 187,"amdgpu_vega"); -DEF_REGISTER(vgpr188, Arch_amdgpu_vega | VGPR | BITS_32 | 188,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_188, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 188,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_188, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 188,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_188, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 188,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_188, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 188,"amdgpu_vega"); -DEF_REGISTER(vgpr189, Arch_amdgpu_vega | VGPR | BITS_32 | 189,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_189, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 189,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_189, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 189,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_189, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 189,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_189, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 189,"amdgpu_vega"); -DEF_REGISTER(vgpr190, Arch_amdgpu_vega | VGPR | BITS_32 | 190,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_190, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 190,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_190, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 190,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_190, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 190,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_190, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 190,"amdgpu_vega"); -DEF_REGISTER(vgpr191, Arch_amdgpu_vega | VGPR | BITS_32 | 191,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_191, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 191,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_191, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 191,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_191, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 191,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_191, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 191,"amdgpu_vega"); -DEF_REGISTER(vgpr192, Arch_amdgpu_vega | VGPR | BITS_32 | 192,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_192, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 192,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_192, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 192,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_192, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 192,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_192, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 192,"amdgpu_vega"); -DEF_REGISTER(vgpr193, Arch_amdgpu_vega | VGPR | BITS_32 | 193,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_193, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 193,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_193, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 193,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_193, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 193,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_193, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 193,"amdgpu_vega"); -DEF_REGISTER(vgpr194, Arch_amdgpu_vega | VGPR | BITS_32 | 194,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_194, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 194,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_194, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 194,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_194, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 194,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_194, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 194,"amdgpu_vega"); -DEF_REGISTER(vgpr195, Arch_amdgpu_vega | VGPR | BITS_32 | 195,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_195, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 195,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_195, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 195,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_195, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 195,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_195, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 195,"amdgpu_vega"); -DEF_REGISTER(vgpr196, Arch_amdgpu_vega | VGPR | BITS_32 | 196,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_196, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 196,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_196, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 196,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_196, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 196,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_196, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 196,"amdgpu_vega"); -DEF_REGISTER(vgpr197, Arch_amdgpu_vega | VGPR | BITS_32 | 197,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_197, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 197,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_197, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 197,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_197, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 197,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_197, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 197,"amdgpu_vega"); -DEF_REGISTER(vgpr198, Arch_amdgpu_vega | VGPR | BITS_32 | 198,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_198, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 198,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_198, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 198,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_198, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 198,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_198, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 198,"amdgpu_vega"); -DEF_REGISTER(vgpr199, Arch_amdgpu_vega | VGPR | BITS_32 | 199,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_199, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 199,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_199, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 199,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_199, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 199,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_199, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 199,"amdgpu_vega"); -DEF_REGISTER(vgpr200, Arch_amdgpu_vega | VGPR | BITS_32 | 200,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_200, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 200,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_200, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 200,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_200, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 200,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_200, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 200,"amdgpu_vega"); -DEF_REGISTER(vgpr201, Arch_amdgpu_vega | VGPR | BITS_32 | 201,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_201, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 201,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_201, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 201,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_201, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 201,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_201, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 201,"amdgpu_vega"); -DEF_REGISTER(vgpr202, Arch_amdgpu_vega | VGPR | BITS_32 | 202,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_202, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 202,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_202, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 202,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_202, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 202,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_202, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 202,"amdgpu_vega"); -DEF_REGISTER(vgpr203, Arch_amdgpu_vega | VGPR | BITS_32 | 203,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_203, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 203,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_203, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 203,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_203, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 203,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_203, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 203,"amdgpu_vega"); -DEF_REGISTER(vgpr204, Arch_amdgpu_vega | VGPR | BITS_32 | 204,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_204, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 204,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_204, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 204,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_204, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 204,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_204, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 204,"amdgpu_vega"); -DEF_REGISTER(vgpr205, Arch_amdgpu_vega | VGPR | BITS_32 | 205,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_205, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 205,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_205, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 205,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_205, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 205,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_205, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 205,"amdgpu_vega"); -DEF_REGISTER(vgpr206, Arch_amdgpu_vega | VGPR | BITS_32 | 206,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_206, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 206,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_206, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 206,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_206, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 206,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_206, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 206,"amdgpu_vega"); -DEF_REGISTER(vgpr207, Arch_amdgpu_vega | VGPR | BITS_32 | 207,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_207, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 207,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_207, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 207,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_207, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 207,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_207, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 207,"amdgpu_vega"); -DEF_REGISTER(vgpr208, Arch_amdgpu_vega | VGPR | BITS_32 | 208,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_208, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 208,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_208, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 208,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_208, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 208,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_208, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 208,"amdgpu_vega"); -DEF_REGISTER(vgpr209, Arch_amdgpu_vega | VGPR | BITS_32 | 209,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_209, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 209,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_209, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 209,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_209, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 209,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_209, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 209,"amdgpu_vega"); -DEF_REGISTER(vgpr210, Arch_amdgpu_vega | VGPR | BITS_32 | 210,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_210, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 210,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_210, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 210,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_210, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 210,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_210, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 210,"amdgpu_vega"); -DEF_REGISTER(vgpr211, Arch_amdgpu_vega | VGPR | BITS_32 | 211,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_211, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 211,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_211, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 211,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_211, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 211,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_211, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 211,"amdgpu_vega"); -DEF_REGISTER(vgpr212, Arch_amdgpu_vega | VGPR | BITS_32 | 212,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_212, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 212,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_212, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 212,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_212, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 212,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_212, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 212,"amdgpu_vega"); -DEF_REGISTER(vgpr213, Arch_amdgpu_vega | VGPR | BITS_32 | 213,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_213, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 213,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_213, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 213,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_213, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 213,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_213, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 213,"amdgpu_vega"); -DEF_REGISTER(vgpr214, Arch_amdgpu_vega | VGPR | BITS_32 | 214,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_214, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 214,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_214, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 214,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_214, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 214,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_214, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 214,"amdgpu_vega"); -DEF_REGISTER(vgpr215, Arch_amdgpu_vega | VGPR | BITS_32 | 215,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_215, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 215,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_215, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 215,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_215, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 215,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_215, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 215,"amdgpu_vega"); -DEF_REGISTER(vgpr216, Arch_amdgpu_vega | VGPR | BITS_32 | 216,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_216, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 216,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_216, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 216,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_216, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 216,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_216, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 216,"amdgpu_vega"); -DEF_REGISTER(vgpr217, Arch_amdgpu_vega | VGPR | BITS_32 | 217,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_217, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 217,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_217, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 217,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_217, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 217,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_217, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 217,"amdgpu_vega"); -DEF_REGISTER(vgpr218, Arch_amdgpu_vega | VGPR | BITS_32 | 218,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_218, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 218,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_218, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 218,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_218, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 218,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_218, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 218,"amdgpu_vega"); -DEF_REGISTER(vgpr219, Arch_amdgpu_vega | VGPR | BITS_32 | 219,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_219, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 219,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_219, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 219,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_219, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 219,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_219, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 219,"amdgpu_vega"); -DEF_REGISTER(vgpr220, Arch_amdgpu_vega | VGPR | BITS_32 | 220,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_220, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 220,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_220, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 220,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_220, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 220,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_220, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 220,"amdgpu_vega"); -DEF_REGISTER(vgpr221, Arch_amdgpu_vega | VGPR | BITS_32 | 221,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_221, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 221,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_221, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 221,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_221, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 221,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_221, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 221,"amdgpu_vega"); -DEF_REGISTER(vgpr222, Arch_amdgpu_vega | VGPR | BITS_32 | 222,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_222, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 222,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_222, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 222,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_222, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 222,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_222, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 222,"amdgpu_vega"); -DEF_REGISTER(vgpr223, Arch_amdgpu_vega | VGPR | BITS_32 | 223,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_223, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 223,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_223, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 223,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_223, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 223,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_223, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 223,"amdgpu_vega"); -DEF_REGISTER(vgpr224, Arch_amdgpu_vega | VGPR | BITS_32 | 224,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_224, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 224,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_224, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 224,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_224, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 224,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_224, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 224,"amdgpu_vega"); -DEF_REGISTER(vgpr225, Arch_amdgpu_vega | VGPR | BITS_32 | 225,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_225, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 225,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_225, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 225,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_225, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 225,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_225, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 225,"amdgpu_vega"); -DEF_REGISTER(vgpr226, Arch_amdgpu_vega | VGPR | BITS_32 | 226,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_226, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 226,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_226, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 226,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_226, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 226,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_226, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 226,"amdgpu_vega"); -DEF_REGISTER(vgpr227, Arch_amdgpu_vega | VGPR | BITS_32 | 227,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_227, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 227,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_227, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 227,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_227, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 227,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_227, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 227,"amdgpu_vega"); -DEF_REGISTER(vgpr228, Arch_amdgpu_vega | VGPR | BITS_32 | 228,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_228, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 228,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_228, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 228,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_228, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 228,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_228, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 228,"amdgpu_vega"); -DEF_REGISTER(vgpr229, Arch_amdgpu_vega | VGPR | BITS_32 | 229,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_229, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 229,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_229, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 229,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_229, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 229,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_229, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 229,"amdgpu_vega"); -DEF_REGISTER(vgpr230, Arch_amdgpu_vega | VGPR | BITS_32 | 230,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_230, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 230,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_230, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 230,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_230, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 230,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_230, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 230,"amdgpu_vega"); -DEF_REGISTER(vgpr231, Arch_amdgpu_vega | VGPR | BITS_32 | 231,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_231, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 231,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_231, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 231,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_231, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 231,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_231, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 231,"amdgpu_vega"); -DEF_REGISTER(vgpr232, Arch_amdgpu_vega | VGPR | BITS_32 | 232,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_232, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 232,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_232, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 232,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_232, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 232,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_232, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 232,"amdgpu_vega"); -DEF_REGISTER(vgpr233, Arch_amdgpu_vega | VGPR | BITS_32 | 233,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_233, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 233,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_233, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 233,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_233, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 233,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_233, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 233,"amdgpu_vega"); -DEF_REGISTER(vgpr234, Arch_amdgpu_vega | VGPR | BITS_32 | 234,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_234, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 234,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_234, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 234,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_234, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 234,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_234, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 234,"amdgpu_vega"); -DEF_REGISTER(vgpr235, Arch_amdgpu_vega | VGPR | BITS_32 | 235,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_235, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 235,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_235, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 235,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_235, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 235,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_235, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 235,"amdgpu_vega"); -DEF_REGISTER(vgpr236, Arch_amdgpu_vega | VGPR | BITS_32 | 236,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_236, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 236,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_236, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 236,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_236, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 236,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_236, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 236,"amdgpu_vega"); -DEF_REGISTER(vgpr237, Arch_amdgpu_vega | VGPR | BITS_32 | 237,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_237, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 237,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_237, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 237,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_237, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 237,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_237, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 237,"amdgpu_vega"); -DEF_REGISTER(vgpr238, Arch_amdgpu_vega | VGPR | BITS_32 | 238,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_238, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 238,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_238, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 238,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_238, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 238,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_238, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 238,"amdgpu_vega"); -DEF_REGISTER(vgpr239, Arch_amdgpu_vega | VGPR | BITS_32 | 239,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_239, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 239,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_239, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 239,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_239, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 239,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_239, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 239,"amdgpu_vega"); -DEF_REGISTER(vgpr240, Arch_amdgpu_vega | VGPR | BITS_32 | 240,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_240, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 240,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_240, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 240,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_240, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 240,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec16_240, Arch_amdgpu_vega | VGPR_VEC16 | BITS_512 | 240,"amdgpu_vega"); -DEF_REGISTER(vgpr241, Arch_amdgpu_vega | VGPR | BITS_32 | 241,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_241, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 241,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_241, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 241,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_241, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 241,"amdgpu_vega"); -DEF_REGISTER(vgpr242, Arch_amdgpu_vega | VGPR | BITS_32 | 242,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_242, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 242,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_242, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 242,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_242, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 242,"amdgpu_vega"); -DEF_REGISTER(vgpr243, Arch_amdgpu_vega | VGPR | BITS_32 | 243,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_243, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 243,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_243, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 243,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_243, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 243,"amdgpu_vega"); -DEF_REGISTER(vgpr244, Arch_amdgpu_vega | VGPR | BITS_32 | 244,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_244, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 244,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_244, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 244,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_244, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 244,"amdgpu_vega"); -DEF_REGISTER(vgpr245, Arch_amdgpu_vega | VGPR | BITS_32 | 245,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_245, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 245,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_245, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 245,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_245, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 245,"amdgpu_vega"); -DEF_REGISTER(vgpr246, Arch_amdgpu_vega | VGPR | BITS_32 | 246,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_246, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 246,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_246, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 246,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_246, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 246,"amdgpu_vega"); -DEF_REGISTER(vgpr247, Arch_amdgpu_vega | VGPR | BITS_32 | 247,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_247, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 247,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_247, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 247,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_247, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 247,"amdgpu_vega"); -DEF_REGISTER(vgpr248, Arch_amdgpu_vega | VGPR | BITS_32 | 248,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_248, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 248,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_248, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 248,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec8_248, Arch_amdgpu_vega | VGPR_VEC8 | BITS_256 | 248,"amdgpu_vega"); -DEF_REGISTER(vgpr249, Arch_amdgpu_vega | VGPR | BITS_32 | 249,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_249, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 249,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_249, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 249,"amdgpu_vega"); -DEF_REGISTER(vgpr250, Arch_amdgpu_vega | VGPR | BITS_32 | 250,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_250, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 250,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_250, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 250,"amdgpu_vega"); -DEF_REGISTER(vgpr251, Arch_amdgpu_vega | VGPR | BITS_32 | 251,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_251, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 251,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_251, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 251,"amdgpu_vega"); -DEF_REGISTER(vgpr252, Arch_amdgpu_vega | VGPR | BITS_32 | 252,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_252, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 252,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec4_252, Arch_amdgpu_vega | VGPR_VEC4 | BITS_128 | 252,"amdgpu_vega"); -DEF_REGISTER(vgpr253, Arch_amdgpu_vega | VGPR | BITS_32 | 253,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_253, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 253,"amdgpu_vega"); -DEF_REGISTER(vgpr254, Arch_amdgpu_vega | VGPR | BITS_32 | 254,"amdgpu_vega"); -DEF_REGISTER(vgpr_vec2_254, Arch_amdgpu_vega | VGPR_VEC2 | BITS_64 | 254,"amdgpu_vega"); -DEF_REGISTER(vgpr255, Arch_amdgpu_vega | VGPR | BITS_32 | 255,"amdgpu_vega"); -#endif //DYNINST_AMDGPU_VEGA_SYS_REGS_H diff --git a/common/h/compiler_annotations.h b/common/h/compiler_annotations.h index 4e7ee8d352..4612631295 100644 --- a/common/h/compiler_annotations.h +++ b/common/h/compiler_annotations.h @@ -31,6 +31,33 @@ #ifndef COMPILER_ANNOTATIONS_H #define COMPILER_ANNOTATIONS_H + +/*********************************************************************** + * + * INTERNAL HELPER MACROS + * + * Determine if compiler supports __has_cpp_attrribute and __has_c_attribute, + * and check if the attribute can be used without warning giving the language + * version the attribute was introduced (clang and gcc <=6 report true but warn + * if attribute is used). The DYNSINT_STD_FOR_VER_HAS_X_ATTRIBUTES parameter + * is the minumum version of the language that the attribute was introduced. + */ +#if defined(__cplusplus) && defined(__has_cpp_attribute) + #define DYNINST_HAS_HAS_CPP_ATTRIBUTE 1 + #define DYNINST_STD_FOR_VER_HAS_CPP_ATTRIBUTE(minV) (__GNUC__ > 6 || __cplusplus >= (minV)) +#else + #define DYNINST_HAS_HAS_CPP_ATTRIBUTE 0 + #define DYNINST_STD_FOR_VER_HAS_CPP_ATTRIBUTE(minV) 0 +#endif +#if defined(__STDC_VERSION__) && defined(__has_c_attribute) + #define DYNINST_HAS_HAS_C_ATTRIBUTE 1 + #define DYNINST_STD_FOR_VER_HAS_C_ATTRIBUTE(minV) (__GNUC__ > 6 || __STDC_VERSION__ >= (minV)) +#else + #define DYNINST_HAS_HAS_C_ATTRIBUTE 0 + #define DYNINST_STD_FOR_VER_HAS_C_ATTRIBUTE(minV) 0 +#endif + + /*********************************************************************** * * DYNINST_FALLTHROUGH @@ -52,30 +79,32 @@ * } */ -#if defined(__cpluscplus) && defined(__has_cpp_attribute) - #if __has_cpp_attribute(fallthrough) +#if DYNINST_HAS_HAS_CPP_ATTRIBUTE + #if __has_cpp_attribute(fallthrough) && DYNINST_STD_FOR_VER_HAS_CPP_ATTRIBUTE(201703) #define DYNINST_FALLTHROUGH [[fallthrough]] #elif __has_cpp_attribute(gcc::fallthrough) #define DYNINST_FALLTHROUGH [[gcc::fallthrough]] #elif __has_cpp_attribute(clang::fallthrough) #define DYNINST_FALLTHROUGH [[clang::fallthrough]] #endif -#elif !defined(__cpluscplus) && defined(__has_c_attribute) - #if __has_c_attribute(fallthrough) +#elif DYNINST_HAS_HAS_C_ATTRIBUTE + #if __has_c_attribute(fallthrough) && DYNINST_STD_FOR_VER_HAS_C_ATTRIBUTE(202311L) #define DYNINST_FALLTHROUGH [[fallthrough]] - #elif __STDC_VERSION__ > 201710 - // scoped attribute names are only valid in C starting with 2x + #elif __STDC_VERSION__ >= 202311L + // scoped attribute names not valid in C until C23 (:: is not a token) #if __has_c_attribute(gcc::fallthrough) #define DYNINST_FALLTHROUGH [[gcc::fallthrough]] #elif __has_c_attribute(clang::fallthrough) #define DYNINST_FALLTHROUGH [[clang::fallthrough]] #endif #endif -#elif defined(__has_attribute) +#endif + +#if !defined(DYNINST_FALLTHROUGH) && defined(__has_attribute) #if __has_attribute(fallthrough) #define DYNINST_FALLTHROUGH __attribute__((fallthrough)) - #elif __cplusplus || __STDC_VERSION__ > 201710 - // scoped attribute names are only valid in C++ or C starting with 2x + #elif __cplusplus || __STDC_VERSION__ >= 202311L + // scoped attribute names not valid in C until C23 (:: is not a token) #if __has_attribute(gcc::fallthrough) #define DYNINST_FALLTHROUGH __attribute__((gcc::fallthrough)) #elif __has_attribute(clang::fallthrough) @@ -90,6 +119,41 @@ +/*********************************************************************** + * + * DYNINST_DEPRECATED(msg) + * + * Adds an annotation to a function, method, variable or type that it is + * deprecated, and will produce a warning if it used. The parameter msg + * must be a quoted string. + * + * The annotation should be placed before the definition or declaration. + * For example: + * + * DYNINST_DEPRECRATED("Use NewFoo") int Foo(); + */ + +#if DYNINST_HAS_HAS_CPP_ATTRIBUTE && DYNINST_STD_FOR_VER_HAS_CPP_ATTRIBUTE(201402L) + #if __has_cpp_attribute(deprecated) + #define DYNINST_DEPRECATED(msg) [[deprecated(msg)]] + #endif +#elif DYNINST_HAS_HAS_C_ATTRIBUTE && DYNINST_STD_FOR_VER_HAS_C_ATTRIBUTE(202311L) + #if __has_c_attribute(deprecated) + #define DYNINST_DEPRECATED(msg) [[deprecated(msg)]] + #endif +#endif +#if !defined(DYNINST_DEPRECATED) && defined(__has_attribute) + #if __has_attribute(deprecated) + #define DYNINST_DEPRECATED(msg) __attribute__((deprecated(msg))) + #endif +#endif + +#if !defined(DYNINST_DEPRECATED) + #define DYNINST_DEPRECATED(msg) +#endif + + + /*********************************************************************** * * DYNINST_PRINTF_ANNOTATION(fmtIndex, argIndex) diff --git a/common/h/compiler_diagnostics.h b/common/h/compiler_diagnostics.h new file mode 100644 index 0000000000..c67c4ee5ad --- /dev/null +++ b/common/h/compiler_diagnostics.h @@ -0,0 +1,233 @@ +/* + * See the dyninst/COPYRIGHT file for copyright information. + * + * We provide the Paradyn Tools (below described as "Paradyn") + * on an AS IS basis, and do not warrant its validity or performance. + * We reserve the right to update, modify, or discontinue this + * software at any time. We shall have no obligation to supply such + * updates or modifications or any other form of support to you. + * + * By your use of Paradyn, you understand and agree that we (or any + * other person or entity with proprietary rights in Paradyn) are + * under no obligation to provide either maintenance services, + * update services, notices of latent defects, or correction of + * defects for Paradyn. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef COMPILER_DIAGNOSTICS_H +#define COMPILER_DIAGNOSTICS_H + +// This file defines macros to suppress compiler diagnostics for a region of +// code. They are used to suppress diagnostic that are due to 1) non-standard +// code and 2) the compiler produced false positives. They expand to nothing +// if not applicable with the current compiler. +// +// The macros to begin and end the region take the form: +// +// DYNINST_DIAGNOSTIC_BEGIN_SUPPRESS_ +// DYNINST_DIAGNOSTIC_END_SUPPRESS_ +// +// They should be place on a lines of their own without trailing '()' or ';'. +// +// Currently defined value for are +// +// FLEX_ARRAY +// warning about C flexible arrays in C++ +// VLA +// warning about C VLAs (variable length arrays) in C++ +// VLA_EXTENSION +// clang warning about C VLAs in C++ if VLA is suppressed +// VLA_ALL` +// both of the above +// VLA_GCC_PRAGMA_BUG +// gcc <9, 11.0, and 11.1 workaround macro +// LOGICAL_OP +// warning about duplicate subexpressions in a logical expression +// Is a false positive due compiler checks after macro/constant +// propagation (eg. (x == a && x == b) if a and b are distinct +// constants with the same physical value. Only gcc 6-8. +// DUPLICATED_BRANCHES +// similar to LOGICAL_OP except the expressions are the +// conditionals of a chain of if/then/else's. Only gcc 7-8. +// UNUSED_VARIABLE +// clang <10 warns about variables defined solely for RIAA (locks) +// MAYBE_UNINITIALIZED +// gcc 12 warns that dyncompat::optional::value_or may use an +// unitialized value when value_or checks if it is initialized. +// +// Macros to silence unused variable warnings +// +// DYNINST_SUPPRESS_UNUSED_VARIABLE(var) +// indicate that variable var OK to be unused +// +// Define DYNINST_DIAGNOSTIC_NO_SUPPRESSIONS to prevents suppressions. + + +// Define compiler specific suppression codes, an undefined value represents no +// suppression required. Suppression code macro names have the form +// +// DYNINST_SUPPRESS_CODE_ +// +#if defined(__GNUC__) && !defined(__clang__) + #define DYNINST_SUPPRESS_CODE_FLEX_ARRAY "-Wpedantic" + #define DYNINST_SUPPRESS_CODE_VLA "-Wvla" + #if __GNUC__ < 9 + #define DYNINST_SUPPRESS_CODE_LOGICAL_OP "-Wlogical-op" + #endif + #if __GNUC__ >= 7 && __GNUC__ < 9 + #define DYNINST_SUPPRESS_CODE_DUPLICATED_BRANCHES "-Wduplicated-branches" + #endif + #if __GNUC__ == 12 + #define DYNINST_SUPPRESS_CODE_MAYBE_UNINITIALIZED "-Wmaybe-uninitialized" + #endif +#elif defined(__clang__) + #define DYNINST_SUPPRESS_CODE_FLEX_ARRAY "-Wpedantic" + #define DYNINST_SUPPRESS_CODE_VLA "-Wvla" + #define DYNINST_SUPPRESS_CODE_VLA_EXTENSION "-Wvla-extension" + #if __clang_major__ < 10 + #define DYNINST_SUPPRESS_CODE_UNUSED_VARIABLE "-Wunused-variable" + #endif +#elif defined(_MSC_VER) + #define DYNINST_SUPPRESS_CODE_FLEX_ARRAY 4200 +#endif + +// Define DYNISNT_DIAGNOSTIC_BEGIN/END macros, expands to nothing if code undefined +#ifdef DYNINST_SUPPRESS_CODE_FLEX_ARRAY + #define DYNINST_DIAGNOSTIC_BEGIN_SUPPRESS_FLEX_ARRAY DYNINST_DIAGNOSTIC_PUSH_SUPPRESS_CODE(FLEX_ARRAY) + #define DYNINST_DIAGNOSTIC_END_SUPPRESS_FLEX_ARRAY DYNINST_DIAGNOSTIC_POP +#else + #define DYNINST_DIAGNOSTIC_BEGIN_SUPPRESS_FLEX_ARRAY + #define DYNINST_DIAGNOSTIC_END_SUPPRESS_FLEX_ARRAY +#endif + +#ifdef DYNINST_SUPPRESS_CODE_VLA + #define DYNINST_DIAGNOSTIC_BEGIN_SUPPRESS_VLA DYNINST_DIAGNOSTIC_PUSH_SUPPRESS_CODE(VLA) + #define DYNINST_DIAGNOSTIC_END_SUPPRESS_VLA DYNINST_DIAGNOSTIC_POP +#else + #define DYNINST_DIAGNOSTIC_BEGIN_SUPPRESS_VLA + #define DYNINST_DIAGNOSTIC_END_SUPPRESS_VLA +#endif + +#ifdef DYNINST_SUPPRESS_CODE_VLA_EXTENSION + #define DYNINST_DIAGNOSTIC_BEGIN_SUPPRESS_VLA_EXTENSION DYNINST_DIAGNOSTIC_PUSH_SUPPRESS_CODE(VLA_EXTENSION) + #define DYNINST_DIAGNOSTIC_END_SUPPRESS_VLA_EXTENSION DYNINST_DIAGNOSTIC_POP +#else + #define DYNINST_DIAGNOSTIC_BEGIN_SUPPRESS_VLA_EXTENSION + #define DYNINST_DIAGNOSTIC_END_SUPPRESS_VLA_EXTENSION +#endif + +#define DYNINST_DIAGNOSTIC_BEGIN_SUPPRESS_VLA_ALL DYNINST_DIAGNOSTIC_BEGIN_SUPPRESS_VLA DYNINST_DIAGNOSTIC_BEGIN_SUPPRESS_VLA_EXTENSION +#define DYNINST_DIAGNOSTIC_END_SUPPRESS_VLA_ALL DYNINST_DIAGNOSTIC_END_SUPPRESS_VLA DYNINST_DIAGNOSTIC_END_SUPPRESS_VLA_EXTENSION + + +// Suppressions to work around compiler specific diagnostic bugs + +#ifdef DYNINST_SUPPRESS_CODE_LOGICAL_OP + #define DYNINST_DIAGNOSTIC_BEGIN_SUPPRESS_LOGICAL_OP DYNINST_DIAGNOSTIC_PUSH_SUPPRESS_CODE(LOGICAL_OP) + #define DYNINST_DIAGNOSTIC_END_SUPPRESS_LOGICAL_OP DYNINST_DIAGNOSTIC_POP +#else + #define DYNINST_DIAGNOSTIC_BEGIN_SUPPRESS_LOGICAL_OP + #define DYNINST_DIAGNOSTIC_END_SUPPRESS_LOGICAL_OP +#endif + +#ifdef DYNINST_SUPPRESS_CODE_DUPLICATED_BRANCHES + #define DYNINST_DIAGNOSTIC_BEGIN_SUPPRESS_DUPLICATED_BRANCHES DYNINST_DIAGNOSTIC_PUSH_SUPPRESS_CODE(DUPLICATED_BRANCHES) + #define DYNINST_DIAGNOSTIC_END_SUPPRESS_DUPLICATED_BRANCHES DYNINST_DIAGNOSTIC_POP +#else + #define DYNINST_DIAGNOSTIC_BEGIN_SUPPRESS_DUPLICATED_BRANCHES + #define DYNINST_DIAGNOSTIC_END_SUPPRESS_DUPLICATED_BRANCHES +#endif + +#ifdef DYNINST_SUPPRESS_CODE_UNUSED_VARIABLE + #define DYNINST_DIAGNOSTIC_BEGIN_SUPPRESS_UNUSED_VARIABLE DYNINST_DIAGNOSTIC_PUSH_SUPPRESS_CODE(UNUSED_VARIABLE) + #define DYNINST_DIAGNOSTIC_END_SUPPRESS_UNUSED_VARIABLE DYNINST_DIAGNOSTIC_POP +#else + #define DYNINST_DIAGNOSTIC_BEGIN_SUPPRESS_UNUSED_VARIABLE + #define DYNINST_DIAGNOSTIC_END_SUPPRESS_UNUSED_VARIABLE +#endif + +#ifdef DYNINST_SUPPRESS_CODE_MAYBE_UNINITIALIZED + #define DYNINST_DIAGNOSTIC_BEGIN_SUPPRESS_MAYBE_UNINITIALIZED DYNINST_DIAGNOSTIC_PUSH_SUPPRESS_CODE(MAYBE_UNINITIALIZED) + #define DYNINST_DIAGNOSTIC_END_SUPPRESS_MAYBE_UNINITIALIZED DYNINST_DIAGNOSTIC_POP +#else + #define DYNINST_DIAGNOSTIC_BEGIN_SUPPRESS_MAYBE_UNINITIALIZED + #define DYNINST_DIAGNOSTIC_END_SUPPRESS_MAYBE_UNINITIALIZED +#endif + +// gcc <9, 11.0 and 11.1 (there may be others) have a bug where 'pragma +// diagnostic ignores' do not take affect until the next line, so this is a +// workaround for the suppression and VLA are in the same macro +#if defined(__GNUC__) && !defined(__clang__) && (__GNUC__ < 9 || __GNUC__ == 11 && __GNUC_MINOR__ < 2) + #define DYNINST_DIAGNOSTIC_BEGIN_SUPPRESS_VLA_GCC_PRAGMA_BUG DYNINST_DIAGNOSTIC_BEGIN_SUPPRESS_VLA + #define DYNINST_DIAGNOSTIC_END_SUPPRESS_VLA_GCC_PRAGMA_BUG DYNINST_DIAGNOSTIC_END_SUPPRESS_VLA +#else + #define DYNINST_DIAGNOSTIC_BEGIN_SUPPRESS_VLA_GCC_PRAGMA_BUG + #define DYNINST_DIAGNOSTIC_END_SUPPRESS_VLA_GCC_PRAGMA_BUG +#endif + + +// Create pragma from parameters +#define DYNINST_Pragma(x) _Pragma(#x) + +// Create compiler specific macros +// +// DYNINST_DIAGNOSTIC_Pragma(x) - diagnostic pragma for x which is unquoted +// DYNINST_DIAGNOSTIC_SUPPRESS(x) - diagnostic pragma to suppress warning x: +// quoted string (gcc), number (MSVC) + +#ifndef DYNINST_DIAGNOSTIC_NO_SUPPRESSIONS + #if defined(__GNUC__) + #define DYNINST_DIAGNOSTIC_Pragma(x) DYNINST_Pragma(GCC diagnostic x) + #define DYNINST_DIAGNOSTIC_SUPPRESS(x) DYNINST_DIAGNOSTIC_Pragma(ignored x) + #elif defined(_MSC_VER) + #define DYNINST_DIAGNOSTIC_Pragma(x) DYNINST_Pragma(warning(x)) + #define DYNINST_DIAGNOSTIC_SUPPRESS(x) DYNINST_DIAGNOSTIC_Pragma(disable:x) + #endif +#endif + +// if not defined, expand to nothing +#ifndef DYNINST_DIAGNOSTIC_Pragma + #define DYNINST_DIAGNOSTIC_Pragma(x) +#endif +#ifndef DYNINST_DIAGNOSTIC_SUPPRESS + #define DYNINST_DIAGNOSTIC_SUPPRESS(x) +#endif + +// Define macros in terms of compiler specific macros +// +// DYNINST_DIAGNOSTIC_POP - pop stack of pushed diagnostic state +// DYNINST_DIAGNOSTIC_PUSH - push current diagnostic state on stack +// DYNINST_DIAGNOSTIC_PUSH_SUPPRESS(x) - push diagnostic state and add suppression x + +#define DYNINST_DIAGNOSTIC_POP DYNINST_DIAGNOSTIC_Pragma(pop) +#define DYNINST_DIAGNOSTIC_PUSH DYNINST_DIAGNOSTIC_Pragma(push) +#define DYNINST_DIAGNOSTIC_PUSH_SUPPRESS(x) DYNINST_DIAGNOSTIC_PUSH \ + DYNINST_DIAGNOSTIC_SUPPRESS(x) +#define DYNINST_DIAGNOSTIC_PUSH_SUPPRESS_CODE(x) DYNINST_DIAGNOSTIC_PUSH_SUPPRESS(DYNINST_SUPPRESS_CODE_##x) + + +// use the variable in a void expression to indicate use +#ifndef DYNINST_DIAGNOSTIC_NO_SUPPRESSIONS + #define DYNINST_SUPPRESS_UNUSED_VARIABLE(var) (void)(var) +#endif + +// if not defined, expand to nothing +#ifndef DYNINST_SUPPRESS_UNUSED_VARIABLE + #define DYNINST_SUPPRESS_UNUSED_VARIABLE(var) +#endif + +#endif /* COMPILER_DIAGNOSTICS_H */ diff --git a/common/h/concurrent.h b/common/h/concurrent.h index 17982aad24..d4a1ace20c 100644 --- a/common/h/concurrent.h +++ b/common/h/concurrent.h @@ -33,13 +33,16 @@ #include "util.h" #include -#include -#include -#include -#include +#include +#include +#include +#include +#include +#include #include #include #include +#include namespace Dyninst { @@ -52,12 +55,52 @@ namespace dyn_c_annotations { void COMMON_EXPORT runlock(void*); } +namespace concurrent { + template + struct hasher { + size_t operator()(K const& k) const { + return dyncompat::hash{}(k); + } + }; + + namespace detail { + template + class hash_compare; + + // New style tbb_hash_compare concept (TBB_VERSION_MAJOR >= 2021) + template + class hash_compare { + hasher my_hasher; + public: + size_t hash(Key const& k) const { + return my_hasher(k); + } + bool equal(Key const& k1, Key const& k2) const { + return k1 == k2; + } + }; + + // Old style tbb_hash_compare concept + template + class hash_compare { + public: + static size_t hash(Key const& k) { + return hasher{}(k); + } + static bool equal(Key const& k1, Key const& k2) { + return k1 == k2; + } + }; + } +} + template class dyn_c_hash_map : protected tbb::concurrent_hash_map, std::allocator>> { + concurrent::detail::hash_compare= 2021, K>> { + + using base = tbb::concurrent_hash_map= 2021, K>>; - typedef tbb::concurrent_hash_map, std::allocator>> base; public: using typename base::value_type; using typename base::mapped_type; @@ -159,24 +202,24 @@ using dyn_c_vector = tbb::concurrent_vector>; template using dyn_c_queue = tbb::concurrent_queue>; -class dyn_mutex : public boost::mutex { +class dyn_mutex : public dyncompat::mutex { public: - using unique_lock = boost::unique_lock; + using unique_lock = dyncompat::unique_lock; }; class COMMON_EXPORT dyn_rwlock { // Reader management members - boost::atomic rin; - boost::atomic rout; + dyncompat::atomic rin; + dyncompat::atomic rout; unsigned int last; dyn_mutex inlock; - boost::condition_variable rcond; + dyncompat::condition_variable rcond; bool rwakeup[2]; // Writer management members dyn_mutex wlock; dyn_mutex outlock; - boost::condition_variable wcond; + dyncompat::condition_variable wcond; bool wwakeup; public: dyn_rwlock(); @@ -187,12 +230,11 @@ class COMMON_EXPORT dyn_rwlock { void lock(); void unlock(); - using unique_lock = boost::unique_lock; - using shared_lock = boost::shared_lock; + using unique_lock = dyncompat::unique_lock; + using shared_lock = dyncompat::shared_lock; }; class COMMON_EXPORT dyn_thread { - int myid; public: dyn_thread(); unsigned int getId(); diff --git a/common/h/dyn_regs.h b/common/h/dyn_regs.h index a34584ca48..06530ed3f7 100644 --- a/common/h/dyn_regs.h +++ b/common/h/dyn_regs.h @@ -33,1982 +33,18 @@ #define DYN_REGS_H_ #include "util.h" -#include "boost/shared_ptr.hpp" - -#include -#include -#include - -namespace Dyninst -{ - struct x86OperandParser; - struct ppcOperandParser; - struct aarch64OperandParser; - - typedef unsigned long MachRegisterVal; - - //0xff000000 is used to encode architecture - typedef enum - { - Arch_none = 0x00000000, - Arch_x86 = 0x14000000, - Arch_x86_64 = 0x18000000, - Arch_ppc32 = 0x24000000, - Arch_ppc64 = 0x28000000, - Arch_aarch32 = 0x44000000, //for later use - Arch_aarch64 = 0x48000000, - Arch_amdgpu_vega = 0x84000000, - Arch_cuda = 0x88000000, - Arch_amdgpu_rdna = 0x8c000000, //future support for rdna - Arch_intelGen9 = 0xb6000000 //same as machine no. retrevied from eu-readelf - } Architecture; - - - COMMON_EXPORT bool isSegmentRegister(int regClass); - COMMON_EXPORT unsigned getArchAddressWidth(Dyninst::Architecture arch); - class COMMON_EXPORT MachRegister { - friend struct ::Dyninst::x86OperandParser; - friend struct ::Dyninst::ppcOperandParser; - friend struct ::Dyninst::aarch64OperandParser; - private: - signed int reg; - - typedef std::map NameMap; - static boost::shared_ptr names(); - void init_names(); - // reg_class is set to a corresponding enum value that can be found in "external/rose/amdgpuInstructionEnum.h" - // reg_idx is set to the index/id of the register for future lookup - // offset is set to the byte offset from where the register value starts, that is, sub register access ( or register access in a register vector) - void getAMDGPUROSERegister(int ®_class, int ®_idx, int &offset); - public: - - MachRegister(); - explicit MachRegister(signed int r); - explicit MachRegister(signed int r, const char *n); - explicit MachRegister(signed int r, std::string n); - - MachRegister getBaseRegister() const; - Architecture getArchitecture() const; - bool isValid() const; - MachRegisterVal getSubRegValue(const MachRegister& subreg, MachRegisterVal &orig) const; - - std::string name() const; - unsigned int size() const; - bool operator<(const MachRegister &a) const; - bool operator==(const MachRegister &a) const; - operator signed int() const; - signed int val() const; - unsigned int regClass() const; - - static MachRegister getPC(Dyninst::Architecture arch); - static MachRegister getReturnAddress(Dyninst::Architecture arch); - static MachRegister getFramePointer(Dyninst::Architecture arch); - static MachRegister getStackPointer(Dyninst::Architecture arch); - static MachRegister getSyscallNumberReg(Dyninst::Architecture arch); - static MachRegister getSyscallNumberOReg(Dyninst::Architecture arch); - static MachRegister getSyscallReturnValueReg(Dyninst::Architecture arch); - static MachRegister getZeroFlag(Dyninst::Architecture arch); - - bool isPC() const; - bool isFramePointer() const; - bool isStackPointer() const; - bool isSyscallNumberReg() const; - bool isSyscallReturnValueReg() const; - bool isFlag() const; - bool isZeroFlag() const; - - void getROSERegister(int &c, int &n, int &p); - - static MachRegister DwarfEncToReg(int encoding, Dyninst::Architecture arch); - static MachRegister getArchRegFromAbstractReg(MachRegister abstract, Dyninst::Architecture arch); - int getDwarfEnc() const; - - static MachRegister getArchReg(unsigned int regNum, Dyninst::Architecture arch); - }; - - /** - * DEF_REGISTER will define its first parameter as the name of the object - * it's declaring, and 'i' as the integer value representing that object. - * As an example, the name of a register may be - * x86::EAX - * with that register having a value of - * x86::iEAX - * - * The value is mostly useful in the 'case' part switch statements. - **/ -#if defined(DYN_DEFINE_REGS) - //DYN_DEFINE_REGS Should only be defined in libcommon. - //We want one definition, which will be in libcommon, and declarations - //for everyone else. - // - //I wanted these to be const MachRegister objects, but that changes the - //linker scope. Instead they're non-const. Every accessor function is - //const anyways, so we'll just close our eyes and pretend they're declared - //const. -#define DEF_REGISTER(name, value, Arch) \ - const signed int i##name = (value); \ - COMMON_EXPORT MachRegister name(i##name, Arch "::" #name) -#else -#define DEF_REGISTER(name, value, Arch) \ - const signed int i##name = (value); \ - COMMON_EXPORT extern MachRegister name - -#endif - - /** - * For interpreting constants: - * Lowest 16 bits (0x000000ff) is base register ID - * Next 16 bits (0x0000ff00) is the aliasing and subrange ID- - * used on x86/x86_64 to distinguish between things like EAX and AH - * Next 16 bits (0x00ff0000) are the register category, GPR/FPR/MMX/... - * Top 16 bits (0xff000000) are the architecture. - * - * These values/layout are not guaranteed to remain the same as part of the - * public interface, and may change. - **/ - - //Abstract registers used for stackwalking - DEF_REGISTER(InvalidReg, 0 | Arch_none, "abstract"); - DEF_REGISTER(FrameBase, 1 | Arch_none, "abstract"); - DEF_REGISTER(ReturnAddr, 2 | Arch_none, "abstract"); - DEF_REGISTER(StackTop, 3 | Arch_none, "abstract"); - // DWARF-ism; the CFA is the value of the stack pointer in the previous frame - DEF_REGISTER(CFA, 4 | Arch_none, "abstract"); - - namespace x86 - { - const signed int L_REG = 0x00000100; //8-bit, first byte - const signed int H_REG = 0x00000200; //8-bit, second byte - const signed int W_REG = 0x00000300; //16-bit, first word - // MachRegister::getBaseRegister clears the bit field for size, - // so the full register size has to be 0 - const signed int FULL = 0x00000000; //32 bits - const signed int OCT = 0x00000600; //128 bits - const signed int FPDBL = 0x00000700; // 80 bits - const signed int BIT = 0x00000800; // 1 bit - const signed int YMMS = 0x00000900; // YMM are 256 bits - const signed int ZMMS = 0x00000A00; // ZMM are 512 bits - const signed int GPR = 0x00010000; - const signed int SEG = 0x00020000; - const signed int FLAG = 0x00030000; - const signed int MISC = 0x00040000; - const signed int KMASK = 0x00050000; - const signed int XMM = 0x00060000; - const signed int YMM = 0x00070000; - const signed int ZMM = 0x00080000; - const signed int MMX = 0x00090000; - const signed int CTL = 0x000A0000; - const signed int DBG = 0x000B0000; - const signed int TST = 0x000C0000; - const signed int BASEA = 0x0; - const signed int BASEC = 0x1; - const signed int BASED = 0x2; - const signed int BASEB = 0x3; - const signed int BASESP = 0x4; - const signed int BASEBP = 0x5; - const signed int BASESI = 0x6; - const signed int BASEDI = 0x7; - const signed int FLAGS = 0x0; - - const signed int CF = 0x0; - const signed int FLAG1 = 0x1; - const signed int PF = 0x2; - const signed int FLAG3 = 0x3; - const signed int AF = 0x4; - const signed int FLAG5 = 0x5; - const signed int ZF = 0x6; - const signed int SF = 0x7; - const signed int TF = 0x8; - const signed int IF = 0x9; - const signed int DF = 0xa; - const signed int OF = 0xb; - const signed int FLAGC = 0xc; - const signed int FLAGD = 0xd; - const signed int NT = 0xe; - const signed int FLAGF = 0xf; - const signed int RF = 0x10; - - DEF_REGISTER(eax, BASEA | FULL | GPR | Arch_x86, "x86"); - DEF_REGISTER(ecx, BASEC | FULL | GPR | Arch_x86, "x86"); - DEF_REGISTER(edx, BASED | FULL | GPR | Arch_x86, "x86"); - DEF_REGISTER(ebx, BASEB | FULL | GPR | Arch_x86, "x86"); - DEF_REGISTER(esp, BASESP | FULL | GPR | Arch_x86, "x86"); - DEF_REGISTER(ebp, BASEBP | FULL | GPR | Arch_x86, "x86"); - DEF_REGISTER(esi, BASESI | FULL | GPR | Arch_x86, "x86"); - DEF_REGISTER(edi, BASEDI | FULL | GPR | Arch_x86, "x86"); - DEF_REGISTER(ah, BASEA | H_REG | GPR | Arch_x86, "x86"); - DEF_REGISTER(al, BASEA | L_REG | GPR | Arch_x86, "x86"); - DEF_REGISTER(ax, BASEA | W_REG | GPR | Arch_x86, "x86"); - DEF_REGISTER(ch, BASEC | H_REG | GPR | Arch_x86, "x86"); - DEF_REGISTER(cl, BASEC | L_REG | GPR | Arch_x86, "x86"); - DEF_REGISTER(cx, BASEC | W_REG | GPR | Arch_x86, "x86"); - DEF_REGISTER(dh, BASED | H_REG | GPR | Arch_x86, "x86"); - DEF_REGISTER(dl, BASED | L_REG | GPR | Arch_x86, "x86"); - DEF_REGISTER(dx, BASED | W_REG | GPR | Arch_x86, "x86"); - DEF_REGISTER(bh, BASEB | H_REG | GPR | Arch_x86, "x86"); - DEF_REGISTER(bl, BASEB | L_REG | GPR | Arch_x86, "x86"); - DEF_REGISTER(bx, BASEB | W_REG | GPR | Arch_x86, "x86"); - DEF_REGISTER(sp, BASESP | W_REG | GPR | Arch_x86, "x86"); - DEF_REGISTER(bp, BASEBP | W_REG | GPR | Arch_x86, "x86"); - DEF_REGISTER(si, BASESI | W_REG | GPR | Arch_x86, "x86"); - DEF_REGISTER(di, BASEDI | W_REG | GPR | Arch_x86, "x86"); - DEF_REGISTER(eip, 0x10 | FULL | Arch_x86, "x86"); - DEF_REGISTER(flags, FLAGS | FULL | FLAG | Arch_x86, "x86"); - DEF_REGISTER(cf, CF | BIT | FLAG | Arch_x86, "x86"); - DEF_REGISTER(flag1, FLAG1 | BIT | FLAG | Arch_x86, "x86"); - DEF_REGISTER(pf, PF | BIT | FLAG | Arch_x86, "x86"); - DEF_REGISTER(flag3, FLAG3 | BIT | FLAG | Arch_x86, "x86"); - DEF_REGISTER(af, AF | BIT | FLAG | Arch_x86, "x86"); - DEF_REGISTER(flag5, FLAG5 | BIT | FLAG | Arch_x86, "x86"); - DEF_REGISTER(zf, ZF | BIT | FLAG | Arch_x86, "x86"); - DEF_REGISTER(sf, SF | BIT | FLAG | Arch_x86, "x86"); - DEF_REGISTER(tf, TF | BIT | FLAG | Arch_x86, "x86"); - DEF_REGISTER(if_, IF | BIT | FLAG | Arch_x86, "x86"); - DEF_REGISTER(df, DF | BIT | FLAG | Arch_x86, "x86"); - DEF_REGISTER(of, OF | BIT | FLAG | Arch_x86, "x86"); - DEF_REGISTER(flagc, FLAGC | BIT | FLAG | Arch_x86, "x86"); - DEF_REGISTER(flagd, FLAGD | BIT | FLAG | Arch_x86, "x86"); - DEF_REGISTER(nt_, NT | BIT | FLAG | Arch_x86, "x86"); - DEF_REGISTER(flagf, FLAGF | BIT | FLAG | Arch_x86, "x86"); - DEF_REGISTER(rf, RF | BIT | FLAG | Arch_x86, "x86"); - DEF_REGISTER(ds, 0x0 | W_REG | SEG | Arch_x86, "x86"); - DEF_REGISTER(es, 0x1 | W_REG | SEG | Arch_x86, "x86"); - DEF_REGISTER(fs, 0x2 | W_REG | SEG | Arch_x86, "x86"); - DEF_REGISTER(gs, 0x3 | W_REG | SEG | Arch_x86, "x86"); - DEF_REGISTER(cs, 0x4 | W_REG | SEG | Arch_x86, "x86"); - DEF_REGISTER(ss, 0x5 | W_REG | SEG | Arch_x86, "x86"); - DEF_REGISTER(oeax, 0x0 | FULL | MISC | Arch_x86, "x86"); - DEF_REGISTER(fsbase, 0x1 | FULL | MISC | Arch_x86, "x86"); - DEF_REGISTER(gsbase, 0x2 | FULL | MISC | Arch_x86, "x86"); - - DEF_REGISTER(k0, 0x00 | OCT | KMASK| Arch_x86, "x86"); - DEF_REGISTER(k1, 0x01 | OCT | KMASK| Arch_x86, "x86"); - DEF_REGISTER(k2, 0x02 | OCT | KMASK| Arch_x86, "x86"); - DEF_REGISTER(k3, 0x03 | OCT | KMASK| Arch_x86, "x86"); - DEF_REGISTER(k4, 0x04 | OCT | KMASK| Arch_x86, "x86"); - DEF_REGISTER(k5, 0x05 | OCT | KMASK| Arch_x86, "x86"); - DEF_REGISTER(k6, 0x06 | OCT | KMASK| Arch_x86, "x86"); - DEF_REGISTER(k7, 0x07 | OCT | KMASK| Arch_x86, "x86"); - - DEF_REGISTER(xmm0, 0x00 | OCT | XMM | Arch_x86, "x86"); - DEF_REGISTER(xmm1, 0x01 | OCT | XMM | Arch_x86, "x86"); - DEF_REGISTER(xmm2, 0x02 | OCT | XMM | Arch_x86, "x86"); - DEF_REGISTER(xmm3, 0x03 | OCT | XMM | Arch_x86, "x86"); - DEF_REGISTER(xmm4, 0x04 | OCT | XMM | Arch_x86, "x86"); - DEF_REGISTER(xmm5, 0x05 | OCT | XMM | Arch_x86, "x86"); - DEF_REGISTER(xmm6, 0x06 | OCT | XMM | Arch_x86, "x86"); - DEF_REGISTER(xmm7, 0x07 | OCT | XMM | Arch_x86, "x86"); - DEF_REGISTER(xmm8, 0x08 | OCT | XMM | Arch_x86, "x86"); - DEF_REGISTER(xmm9, 0x09 | OCT | XMM | Arch_x86, "x86"); - DEF_REGISTER(xmm10, 0x0A | OCT | XMM | Arch_x86, "x86"); - DEF_REGISTER(xmm11, 0x0B | OCT | XMM | Arch_x86, "x86"); - DEF_REGISTER(xmm12, 0x0C | OCT | XMM | Arch_x86, "x86"); - DEF_REGISTER(xmm13, 0x0D | OCT | XMM | Arch_x86, "x86"); - DEF_REGISTER(xmm14, 0x0E | OCT | XMM | Arch_x86, "x86"); - DEF_REGISTER(xmm15, 0x0F | OCT | XMM | Arch_x86, "x86"); - DEF_REGISTER(xmm16, 0x10 | OCT | XMM | Arch_x86, "x86"); - DEF_REGISTER(xmm17, 0x11 | OCT | XMM | Arch_x86, "x86"); - DEF_REGISTER(xmm18, 0x12 | OCT | XMM | Arch_x86, "x86"); - DEF_REGISTER(xmm19, 0x13 | OCT | XMM | Arch_x86, "x86"); - DEF_REGISTER(xmm20, 0x14 | OCT | XMM | Arch_x86, "x86"); - DEF_REGISTER(xmm21, 0x15 | OCT | XMM | Arch_x86, "x86"); - DEF_REGISTER(xmm22, 0x16 | OCT | XMM | Arch_x86, "x86"); - DEF_REGISTER(xmm23, 0x17 | OCT | XMM | Arch_x86, "x86"); - DEF_REGISTER(xmm24, 0x18 | OCT | XMM | Arch_x86, "x86"); - DEF_REGISTER(xmm25, 0x19 | OCT | XMM | Arch_x86, "x86"); - DEF_REGISTER(xmm26, 0x1A | OCT | XMM | Arch_x86, "x86"); - DEF_REGISTER(xmm27, 0x1B | OCT | XMM | Arch_x86, "x86"); - DEF_REGISTER(xmm28, 0x1C | OCT | XMM | Arch_x86, "x86"); - DEF_REGISTER(xmm29, 0x1D | OCT | XMM | Arch_x86, "x86"); - DEF_REGISTER(xmm30, 0x1E | OCT | XMM | Arch_x86, "x86"); - DEF_REGISTER(xmm31, 0x1F | OCT | XMM | Arch_x86, "x86"); - - - DEF_REGISTER(ymm0, 0x00 | YMMS | YMM | Arch_x86, "x86"); - DEF_REGISTER(ymm1, 0x01 | YMMS | YMM | Arch_x86, "x86"); - DEF_REGISTER(ymm2, 0x02 | YMMS | YMM | Arch_x86, "x86"); - DEF_REGISTER(ymm3, 0x03 | YMMS | YMM | Arch_x86, "x86"); - DEF_REGISTER(ymm4, 0x04 | YMMS | YMM | Arch_x86, "x86"); - DEF_REGISTER(ymm5, 0x05 | YMMS | YMM | Arch_x86, "x86"); - DEF_REGISTER(ymm6, 0x06 | YMMS | YMM | Arch_x86, "x86"); - DEF_REGISTER(ymm7, 0x07 | YMMS | YMM | Arch_x86, "x86"); - DEF_REGISTER(ymm8, 0x08 | YMMS | YMM | Arch_x86, "x86"); - DEF_REGISTER(ymm9, 0x09 | YMMS | YMM | Arch_x86, "x86"); - DEF_REGISTER(ymm10, 0x0A | YMMS | YMM | Arch_x86, "x86"); - DEF_REGISTER(ymm11, 0x0B | YMMS | YMM | Arch_x86, "x86"); - DEF_REGISTER(ymm12, 0x0C | YMMS | YMM | Arch_x86, "x86"); - DEF_REGISTER(ymm13, 0x0D | YMMS | YMM | Arch_x86, "x86"); - DEF_REGISTER(ymm14, 0x0E | YMMS | YMM | Arch_x86, "x86"); - DEF_REGISTER(ymm15, 0x0F | YMMS | YMM | Arch_x86, "x86"); - DEF_REGISTER(ymm16, 0x10 | YMMS | YMM | Arch_x86, "x86"); - DEF_REGISTER(ymm17, 0x11 | YMMS | YMM | Arch_x86, "x86"); - DEF_REGISTER(ymm18, 0x12 | YMMS | YMM | Arch_x86, "x86"); - DEF_REGISTER(ymm19, 0x13 | YMMS | YMM | Arch_x86, "x86"); - DEF_REGISTER(ymm20, 0x14 | YMMS | YMM | Arch_x86, "x86"); - DEF_REGISTER(ymm21, 0x15 | YMMS | YMM | Arch_x86, "x86"); - DEF_REGISTER(ymm22, 0x16 | YMMS | YMM | Arch_x86, "x86"); - DEF_REGISTER(ymm23, 0x17 | YMMS | YMM | Arch_x86, "x86"); - DEF_REGISTER(ymm24, 0x18 | YMMS | YMM | Arch_x86, "x86"); - DEF_REGISTER(ymm25, 0x19 | YMMS | YMM | Arch_x86, "x86"); - DEF_REGISTER(ymm26, 0x1A | YMMS | YMM | Arch_x86, "x86"); - DEF_REGISTER(ymm27, 0x1B | YMMS | YMM | Arch_x86, "x86"); - DEF_REGISTER(ymm28, 0x1C | YMMS | YMM | Arch_x86, "x86"); - DEF_REGISTER(ymm29, 0x1D | YMMS | YMM | Arch_x86, "x86"); - DEF_REGISTER(ymm30, 0x1E | YMMS | YMM | Arch_x86, "x86"); - DEF_REGISTER(ymm31, 0x1F | YMMS | YMM | Arch_x86, "x86"); - - DEF_REGISTER(zmm0, 0x00 | ZMMS | ZMM | Arch_x86, "x86"); - DEF_REGISTER(zmm1, 0x01 | ZMMS | ZMM | Arch_x86, "x86"); - DEF_REGISTER(zmm2, 0x02 | ZMMS | ZMM | Arch_x86, "x86"); - DEF_REGISTER(zmm3, 0x03 | ZMMS | ZMM | Arch_x86, "x86"); - DEF_REGISTER(zmm4, 0x04 | ZMMS | ZMM | Arch_x86, "x86"); - DEF_REGISTER(zmm5, 0x05 | ZMMS | ZMM | Arch_x86, "x86"); - DEF_REGISTER(zmm6, 0x06 | ZMMS | ZMM | Arch_x86, "x86"); - DEF_REGISTER(zmm7, 0x07 | ZMMS | ZMM | Arch_x86, "x86"); - DEF_REGISTER(zmm8, 0x08 | ZMMS | ZMM | Arch_x86, "x86"); - DEF_REGISTER(zmm9, 0x09 | ZMMS | ZMM | Arch_x86, "x86"); - DEF_REGISTER(zmm10, 0x0A | ZMMS | ZMM | Arch_x86, "x86"); - DEF_REGISTER(zmm11, 0x0B | ZMMS | ZMM | Arch_x86, "x86"); - DEF_REGISTER(zmm12, 0x0C | ZMMS | ZMM | Arch_x86, "x86"); - DEF_REGISTER(zmm13, 0x0D | ZMMS | ZMM | Arch_x86, "x86"); - DEF_REGISTER(zmm14, 0x0E | ZMMS | ZMM | Arch_x86, "x86"); - DEF_REGISTER(zmm15, 0x0F | ZMMS | ZMM | Arch_x86, "x86"); - DEF_REGISTER(zmm16, 0x10 | ZMMS | ZMM | Arch_x86, "x86"); - DEF_REGISTER(zmm17, 0x11 | ZMMS | ZMM | Arch_x86, "x86"); - DEF_REGISTER(zmm18, 0x12 | ZMMS | ZMM | Arch_x86, "x86"); - DEF_REGISTER(zmm19, 0x13 | ZMMS | ZMM | Arch_x86, "x86"); - DEF_REGISTER(zmm20, 0x14 | ZMMS | ZMM | Arch_x86, "x86"); - DEF_REGISTER(zmm21, 0x15 | ZMMS | ZMM | Arch_x86, "x86"); - DEF_REGISTER(zmm22, 0x16 | ZMMS | ZMM | Arch_x86, "x86"); - DEF_REGISTER(zmm23, 0x17 | ZMMS | ZMM | Arch_x86, "x86"); - DEF_REGISTER(zmm24, 0x18 | ZMMS | ZMM | Arch_x86, "x86"); - DEF_REGISTER(zmm25, 0x19 | ZMMS | ZMM | Arch_x86, "x86"); - DEF_REGISTER(zmm26, 0x1A | ZMMS | ZMM | Arch_x86, "x86"); - DEF_REGISTER(zmm27, 0x1B | ZMMS | ZMM | Arch_x86, "x86"); - DEF_REGISTER(zmm28, 0x1C | ZMMS | ZMM | Arch_x86, "x86"); - DEF_REGISTER(zmm29, 0x1D | ZMMS | ZMM | Arch_x86, "x86"); - DEF_REGISTER(zmm30, 0x1E | ZMMS | ZMM | Arch_x86, "x86"); - DEF_REGISTER(zmm31, 0x1F | ZMMS | ZMM | Arch_x86, "x86"); - - DEF_REGISTER(mm0, 0x0 | FPDBL | MMX | Arch_x86, "x86"); - DEF_REGISTER(mm1, 0x1 | FPDBL | MMX | Arch_x86, "x86"); - DEF_REGISTER(mm2, 0x2 | FPDBL | MMX | Arch_x86, "x86"); - DEF_REGISTER(mm3, 0x3 | FPDBL | MMX | Arch_x86, "x86"); - DEF_REGISTER(mm4, 0x4 | FPDBL | MMX | Arch_x86, "x86"); - DEF_REGISTER(mm5, 0x5 | FPDBL | MMX | Arch_x86, "x86"); - DEF_REGISTER(mm6, 0x6 | FPDBL | MMX | Arch_x86, "x86"); - DEF_REGISTER(mm7, 0x7 | FPDBL | MMX | Arch_x86, "x86"); - DEF_REGISTER(cr0, 0x0 | FULL | CTL | Arch_x86, "x86"); - DEF_REGISTER(cr1, 0x1 | FULL | CTL | Arch_x86, "x86"); - DEF_REGISTER(cr2, 0x2 | FULL | CTL | Arch_x86, "x86"); - DEF_REGISTER(cr3, 0x3 | FULL | CTL | Arch_x86, "x86"); - DEF_REGISTER(cr4, 0x4 | FULL | CTL | Arch_x86, "x86"); - DEF_REGISTER(cr5, 0x5 | FULL | CTL | Arch_x86, "x86"); - DEF_REGISTER(cr6, 0x6 | FULL | CTL | Arch_x86, "x86"); - DEF_REGISTER(cr7, 0x7 | FULL | CTL | Arch_x86, "x86"); - DEF_REGISTER(dr0, 0x0 | FULL | DBG | Arch_x86, "x86"); - DEF_REGISTER(dr1, 0x1 | FULL | DBG | Arch_x86, "x86"); - DEF_REGISTER(dr2, 0x2 | FULL | DBG | Arch_x86, "x86"); - DEF_REGISTER(dr3, 0x3 | FULL | DBG | Arch_x86, "x86"); - DEF_REGISTER(dr4, 0x4 | FULL | DBG | Arch_x86, "x86"); - DEF_REGISTER(dr5, 0x5 | FULL | DBG | Arch_x86, "x86"); - DEF_REGISTER(dr6, 0x6 | FULL | DBG | Arch_x86, "x86"); - DEF_REGISTER(dr7, 0x7 | FULL | DBG | Arch_x86, "x86"); - DEF_REGISTER(tr0, 0x0 | FULL | TST | Arch_x86, "x86"); - DEF_REGISTER(tr1, 0x1 | FULL | TST | Arch_x86, "x86"); - DEF_REGISTER(tr2, 0x2 | FULL | TST | Arch_x86, "x86"); - DEF_REGISTER(tr3, 0x3 | FULL | TST | Arch_x86, "x86"); - DEF_REGISTER(tr4, 0x4 | FULL | TST | Arch_x86, "x86"); - DEF_REGISTER(tr5, 0x5 | FULL | TST | Arch_x86, "x86"); - DEF_REGISTER(tr6, 0x6 | FULL | TST | Arch_x86, "x86"); - DEF_REGISTER(tr7, 0x7 | FULL | TST | Arch_x86, "x86"); - DEF_REGISTER(st0, 0x0 | FPDBL | MMX | Arch_x86, "x86"); - DEF_REGISTER(st1, 0x1 | FPDBL | MMX | Arch_x86, "x86"); - DEF_REGISTER(st2, 0x2 | FPDBL | MMX | Arch_x86, "x86"); - DEF_REGISTER(st3, 0x3 | FPDBL | MMX | Arch_x86, "x86"); - DEF_REGISTER(st4, 0x4 | FPDBL | MMX | Arch_x86, "x86"); - DEF_REGISTER(st5, 0x5 | FPDBL | MMX | Arch_x86, "x86"); - DEF_REGISTER(st6, 0x6 | FPDBL | MMX | Arch_x86, "x86"); - DEF_REGISTER(st7, 0x7 | FPDBL | MMX | Arch_x86, "x86"); - } - namespace x86_64 - { - const signed int L_REG = 0x00000100; //8-bit, first byte - const signed int H_REG = 0x00000200; //8-bit, second byte - const signed int W_REG = 0x00000300; //16 bit, first work - const signed int D_REG = 0x00000F00; //32 bit, first double word - // MachRegister::getBaseRegister clears the bit field for size, - // so the full register size has to be 0 - const signed int FULL = 0x00000000; //64 bits - const signed int OCT = 0x00000600; //128 bits - const signed int FPDBL = 0x00000700; // 80 bits - const signed int BIT = 0x00000800; // 1 bit - const signed int YMMS = 0x00000900; // YMM are 256 bits - const signed int ZMMS = 0x00000A00; // ZMM are 512 bits - const signed int GPR = 0x00010000; - const signed int SEG = 0x00020000; - const signed int FLAG = 0x00030000; - const signed int MISC = 0x00040000; - const signed int KMASK = 0x00050000; - const signed int XMM = 0x00060000; - const signed int YMM = 0x00070000; - const signed int ZMM = 0x00080000; - const signed int MMX = 0x00090000; - const signed int CTL = 0x000A0000; - const signed int DBG = 0x000B0000; - const signed int TST = 0x000C0000; - const signed int FLAGS = 0x00000000; - const signed int BASEA = 0x0; - const signed int BASEC = 0x1; - const signed int BASED = 0x2; - const signed int BASEB = 0x3; - const signed int BASESP = 0x4; - const signed int BASEBP = 0x5; - const signed int BASESI = 0x6; - const signed int BASEDI = 0x7; - const signed int BASE8 = 0x8; - const signed int BASE9 = 0x9; - const signed int BASE10 = 0xa; - const signed int BASE11 = 0xb; - const signed int BASE12 = 0xc; - const signed int BASE13 = 0xd; - const signed int BASE14 = 0xe; - const signed int BASE15 = 0xf; - - const signed int CF = x86::CF; - const signed int PF = x86::PF; - const signed int AF = x86::AF; - const signed int ZF = x86::ZF; - const signed int SF = x86::SF; - const signed int TF = x86::TF; - const signed int IF = x86::IF; - const signed int DF = x86::DF; - const signed int OF = x86::OF; - const signed int NT = x86::NT; - const signed int RF = x86::RF; - - DEF_REGISTER(rax, BASEA | FULL | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(rcx, BASEC | FULL | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(rdx, BASED | FULL | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(rbx, BASEB | FULL | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(rsp, BASESP | FULL | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(rbp, BASEBP | FULL | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(rsi, BASESI | FULL | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(rdi, BASEDI | FULL | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(r8, BASE8 | FULL | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(r9, BASE9 | FULL | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(r10, BASE10 | FULL | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(r11, BASE11 | FULL | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(r12, BASE12 | FULL | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(r13, BASE13 | FULL | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(r14, BASE14 | FULL | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(r15, BASE15 | FULL | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(ah, BASEA | H_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(al, BASEA | L_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(ax, BASEA | W_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(eax, BASEA | D_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(ch, BASEC | H_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(cl, BASEC | L_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(cx, BASEC | W_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(ecx, BASEC | D_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(dh, BASED | H_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(dl, BASED | L_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(dx, BASED | W_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(edx, BASED | D_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(bh, BASEB | H_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(bl, BASEB | L_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(bx, BASEB | W_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(ebx, BASEB | D_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(spl, BASESP | L_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(sp, BASESP | W_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(esp, BASESP | D_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(bpl, BASEBP | L_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(bp, BASEBP | W_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(ebp, BASEBP | D_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(dil, BASEDI | L_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(di, BASEDI | W_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(edi, BASEDI | D_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(sil, BASESI | L_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(si, BASESI | W_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(esi, BASESI | D_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(r8b, BASE8 | L_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(r8w, BASE8 | W_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(r8d, BASE8 | D_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(r9b, BASE9 | L_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(r9w, BASE9 | W_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(r9d, BASE9 | D_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(r10b, BASE10 | L_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(r10w, BASE10 | W_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(r10d, BASE10 | D_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(r11b, BASE11 | L_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(r11w, BASE11 | W_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(r11d, BASE11 | D_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(r12b, BASE12 | L_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(r12w, BASE12 | W_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(r12d, BASE12 | D_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(r13b, BASE13 | L_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(r13w, BASE13 | W_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(r13d, BASE13 | D_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(r14b, BASE14 | L_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(r14w, BASE14 | W_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(r14d, BASE14 | D_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(r15b, BASE15 | L_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(r15w, BASE15 | W_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(r15d, BASE15 | D_REG | GPR | Arch_x86_64, "x86_64"); - DEF_REGISTER(rip, 0x10 | FULL | Arch_x86_64, "x86_64"); - DEF_REGISTER(eip, 0x10 | D_REG | Arch_x86_64, "x86_64"); - DEF_REGISTER(flags, FLAGS | FULL | FLAG | Arch_x86_64, "x86_64"); - DEF_REGISTER(cf, CF | BIT | FLAG | Arch_x86_64, "x86_64"); - DEF_REGISTER(pf, PF | BIT | FLAG | Arch_x86_64, "x86_64"); - DEF_REGISTER(af, AF | BIT | FLAG | Arch_x86_64, "x86_64"); - DEF_REGISTER(zf, ZF | BIT | FLAG | Arch_x86_64, "x86_64"); - DEF_REGISTER(sf, SF | BIT | FLAG | Arch_x86_64, "x86_64"); - DEF_REGISTER(tf, TF | BIT | FLAG | Arch_x86_64, "x86_64"); - DEF_REGISTER(if_, IF | BIT | FLAG | Arch_x86_64, "x86_64"); - DEF_REGISTER(df, DF | BIT | FLAG | Arch_x86_64, "x86_64"); - DEF_REGISTER(of, OF | BIT | FLAG | Arch_x86_64, "x86_64"); - DEF_REGISTER(nt_, NT | BIT | FLAG | Arch_x86_64, "x86_64"); - DEF_REGISTER(rf, RF | BIT | FLAG | Arch_x86_64, "x86_64"); - DEF_REGISTER(ds, 0x0 | FULL | SEG | Arch_x86_64, "x86_64"); - DEF_REGISTER(es, 0x1 | FULL | SEG | Arch_x86_64, "x86_64"); - DEF_REGISTER(fs, 0x2 | FULL | SEG | Arch_x86_64, "x86_64"); - DEF_REGISTER(gs, 0x3 | FULL | SEG | Arch_x86_64, "x86_64"); - DEF_REGISTER(cs, 0x4 | FULL | SEG | Arch_x86_64, "x86_64"); - DEF_REGISTER(ss, 0x5 | FULL | SEG | Arch_x86_64, "x86_64"); - DEF_REGISTER(orax, 0x0 | FULL | MISC | Arch_x86_64, "x86_64"); - DEF_REGISTER(fsbase, 0x1 | FULL | MISC | Arch_x86_64, "x86_64"); - DEF_REGISTER(gsbase, 0x2 | FULL | MISC | Arch_x86_64, "x86_64"); - DEF_REGISTER(k0, 0x00 | OCT | KMASK| Arch_x86_64, "x86_64"); - DEF_REGISTER(k1, 0x01 | OCT | KMASK| Arch_x86_64, "x86_64"); - DEF_REGISTER(k2, 0x02 | OCT | KMASK| Arch_x86_64, "x86_64"); - DEF_REGISTER(k3, 0x03 | OCT | KMASK| Arch_x86_64, "x86_64"); - DEF_REGISTER(k4, 0x04 | OCT | KMASK| Arch_x86_64, "x86_64"); - DEF_REGISTER(k5, 0x05 | OCT | KMASK| Arch_x86_64, "x86_64"); - DEF_REGISTER(k6, 0x06 | OCT | KMASK| Arch_x86_64, "x86_64"); - DEF_REGISTER(k7, 0x07 | OCT | KMASK| Arch_x86_64, "x86_64"); - DEF_REGISTER(xmm0, 0x00 | OCT | XMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(xmm1, 0x01 | OCT | XMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(xmm2, 0x02 | OCT | XMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(xmm3, 0x03 | OCT | XMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(xmm4, 0x04 | OCT | XMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(xmm5, 0x05 | OCT | XMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(xmm6, 0x06 | OCT | XMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(xmm7, 0x07 | OCT | XMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(xmm8, 0x08 | OCT | XMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(xmm9, 0x09 | OCT | XMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(xmm10, 0x0A | OCT | XMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(xmm11, 0x0B | OCT | XMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(xmm12, 0x0C | OCT | XMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(xmm13, 0x0D | OCT | XMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(xmm14, 0x0E | OCT | XMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(xmm15, 0x0F | OCT | XMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(xmm16, 0x10 | OCT | XMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(xmm17, 0x11 | OCT | XMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(xmm18, 0x12 | OCT | XMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(xmm19, 0x13 | OCT | XMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(xmm20, 0x14 | OCT | XMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(xmm21, 0x15 | OCT | XMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(xmm22, 0x16 | OCT | XMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(xmm23, 0x17 | OCT | XMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(xmm24, 0x18 | OCT | XMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(xmm25, 0x19 | OCT | XMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(xmm26, 0x1A | OCT | XMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(xmm27, 0x1B | OCT | XMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(xmm28, 0x1C | OCT | XMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(xmm29, 0x1D | OCT | XMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(xmm30, 0x1E | OCT | XMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(xmm31, 0x1F | OCT | XMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(ymm0, 0x00 | YMMS | YMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(ymm1, 0x01 | YMMS | YMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(ymm2, 0x02 | YMMS | YMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(ymm3, 0x03 | YMMS | YMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(ymm4, 0x04 | YMMS | YMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(ymm5, 0x05 | YMMS | YMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(ymm6, 0x06 | YMMS | YMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(ymm7, 0x07 | YMMS | YMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(ymm8, 0x08 | YMMS | YMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(ymm9, 0x09 | YMMS | YMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(ymm10, 0x0A | YMMS | YMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(ymm11, 0x0B | YMMS | YMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(ymm12, 0x0C | YMMS | YMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(ymm13, 0x0D | YMMS | YMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(ymm14, 0x0E | YMMS | YMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(ymm15, 0x0F | YMMS | YMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(ymm16, 0x10 | YMMS | YMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(ymm17, 0x11 | YMMS | YMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(ymm18, 0x12 | YMMS | YMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(ymm19, 0x13 | YMMS | YMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(ymm20, 0x14 | YMMS | YMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(ymm21, 0x15 | YMMS | YMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(ymm22, 0x16 | YMMS | YMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(ymm23, 0x17 | YMMS | YMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(ymm24, 0x18 | YMMS | YMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(ymm25, 0x19 | YMMS | YMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(ymm26, 0x1A | YMMS | YMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(ymm27, 0x1B | YMMS | YMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(ymm28, 0x1C | YMMS | YMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(ymm29, 0x1D | YMMS | YMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(ymm30, 0x1E | YMMS | YMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(ymm31, 0x1F | YMMS | YMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(zmm0, 0x00 | ZMMS | ZMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(zmm1, 0x01 | ZMMS | ZMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(zmm2, 0x02 | ZMMS | ZMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(zmm3, 0x03 | ZMMS | ZMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(zmm4, 0x04 | ZMMS | ZMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(zmm5, 0x05 | ZMMS | ZMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(zmm6, 0x06 | ZMMS | ZMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(zmm7, 0x07 | ZMMS | ZMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(zmm8, 0x08 | ZMMS | ZMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(zmm9, 0x09 | ZMMS | ZMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(zmm10, 0x0A | ZMMS | ZMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(zmm11, 0x0B | ZMMS | ZMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(zmm12, 0x0C | ZMMS | ZMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(zmm13, 0x0D | ZMMS | ZMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(zmm14, 0x0E | ZMMS | ZMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(zmm15, 0x0F | ZMMS | ZMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(zmm16, 0x10 | ZMMS | ZMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(zmm17, 0x11 | ZMMS | ZMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(zmm18, 0x12 | ZMMS | ZMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(zmm19, 0x13 | ZMMS | ZMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(zmm20, 0x14 | ZMMS | ZMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(zmm21, 0x15 | ZMMS | ZMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(zmm22, 0x16 | ZMMS | ZMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(zmm23, 0x17 | ZMMS | ZMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(zmm24, 0x18 | ZMMS | ZMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(zmm25, 0x19 | ZMMS | ZMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(zmm26, 0x1A | ZMMS | ZMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(zmm27, 0x1B | ZMMS | ZMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(zmm28, 0x1C | ZMMS | ZMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(zmm29, 0x1D | ZMMS | ZMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(zmm30, 0x1E | ZMMS | ZMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(zmm31, 0x1F | ZMMS | ZMM | Arch_x86_64, "x86_64"); - DEF_REGISTER(mm0, 0x0 | FPDBL | MMX | Arch_x86_64, "x86_64"); - DEF_REGISTER(mm1, 0x1 | FPDBL | MMX | Arch_x86_64, "x86_64"); - DEF_REGISTER(mm2, 0x2 | FPDBL | MMX | Arch_x86_64, "x86_64"); - DEF_REGISTER(mm3, 0x3 | FPDBL | MMX | Arch_x86_64, "x86_64"); - DEF_REGISTER(mm4, 0x4 | FPDBL | MMX | Arch_x86_64, "x86_64"); - DEF_REGISTER(mm5, 0x5 | FPDBL | MMX | Arch_x86_64, "x86_64"); - DEF_REGISTER(mm6, 0x6 | FPDBL | MMX | Arch_x86_64, "x86_64"); - DEF_REGISTER(mm7, 0x7 | FPDBL | MMX | Arch_x86_64, "x86_64"); - DEF_REGISTER(cr0, 0x0 | FULL | CTL | Arch_x86_64, "x86_64"); - DEF_REGISTER(cr1, 0x1 | FULL | CTL | Arch_x86_64, "x86_64"); - DEF_REGISTER(cr2, 0x2 | FULL | CTL | Arch_x86_64, "x86_64"); - DEF_REGISTER(cr3, 0x3 | FULL | CTL | Arch_x86_64, "x86_64"); - DEF_REGISTER(cr4, 0x4 | FULL | CTL | Arch_x86_64, "x86_64"); - DEF_REGISTER(cr5, 0x5 | FULL | CTL | Arch_x86_64, "x86_64"); - DEF_REGISTER(cr6, 0x6 | FULL | CTL | Arch_x86_64, "x86_64"); - DEF_REGISTER(cr7, 0x7 | FULL | CTL | Arch_x86_64, "x86_64"); - DEF_REGISTER(dr0, 0x0 | FULL | DBG | Arch_x86_64, "x86_64"); - DEF_REGISTER(dr1, 0x1 | FULL | DBG | Arch_x86_64, "x86_64"); - DEF_REGISTER(dr2, 0x2 | FULL | DBG | Arch_x86_64, "x86_64"); - DEF_REGISTER(dr3, 0x3 | FULL | DBG | Arch_x86_64, "x86_64"); - DEF_REGISTER(dr4, 0x4 | FULL | DBG | Arch_x86_64, "x86_64"); - DEF_REGISTER(dr5, 0x5 | FULL | DBG | Arch_x86_64, "x86_64"); - DEF_REGISTER(dr6, 0x6 | FULL | DBG | Arch_x86_64, "x86_64"); - DEF_REGISTER(dr7, 0x7 | FULL | DBG | Arch_x86_64, "x86_64"); - DEF_REGISTER(tr0, 0x0 | FULL | TST | Arch_x86_64, "x86_64"); - DEF_REGISTER(tr1, 0x1 | FULL | TST | Arch_x86_64, "x86_64"); - DEF_REGISTER(tr2, 0x2 | FULL | TST | Arch_x86_64, "x86_64"); - DEF_REGISTER(tr3, 0x3 | FULL | TST | Arch_x86_64, "x86_64"); - DEF_REGISTER(tr4, 0x4 | FULL | TST | Arch_x86_64, "x86_64"); - DEF_REGISTER(tr5, 0x5 | FULL | TST | Arch_x86_64, "x86_64"); - DEF_REGISTER(tr6, 0x6 | FULL | TST | Arch_x86_64, "x86_64"); - DEF_REGISTER(tr7, 0x7 | FULL | TST | Arch_x86_64, "x86_64"); - DEF_REGISTER(st0, 0x0 | FPDBL | MMX | Arch_x86_64, "x86_64"); - DEF_REGISTER(st1, 0x1 | FPDBL | MMX | Arch_x86_64, "x86_64"); - DEF_REGISTER(st2, 0x2 | FPDBL | MMX | Arch_x86_64, "x86_64"); - DEF_REGISTER(st3, 0x3 | FPDBL | MMX | Arch_x86_64, "x86_64"); - DEF_REGISTER(st4, 0x4 | FPDBL | MMX | Arch_x86_64, "x86_64"); - DEF_REGISTER(st5, 0x5 | FPDBL | MMX | Arch_x86_64, "x86_64"); - DEF_REGISTER(st6, 0x6 | FPDBL | MMX | Arch_x86_64, "x86_64"); - DEF_REGISTER(st7, 0x7 | FPDBL | MMX | Arch_x86_64, "x86_64"); - } - namespace ppc32 { - const signed int GPR = 0x00010000; - const signed int FPR = 0x00020000; - const signed int FSR = 0x00040000; - const signed int SPR = 0x00080000; - - DEF_REGISTER(r0, 0 | GPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(r1, 1 | GPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(r2, 2 | GPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(r3, 3 | GPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(r4, 4 | GPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(r5, 5 | GPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(r6, 6 | GPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(r7, 7 | GPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(r8, 8 | GPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(r9, 9 | GPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(r10, 10 | GPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(r11, 11 | GPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(r12, 12 | GPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(r13, 13 | GPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(r14, 14 | GPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(r15, 15 | GPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(r16, 16 | GPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(r17, 17 | GPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(r18, 18 | GPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(r19, 19 | GPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(r20, 20 | GPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(r21, 21 | GPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(r22, 22 | GPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(r23, 23 | GPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(r24, 24 | GPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(r25, 25 | GPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(r26, 26 | GPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(r27, 27 | GPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(r28, 28 | GPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(r29, 29 | GPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(r30, 30 | GPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(r31, 31 | GPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpr0, 0 | FPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpr1, 1 | FPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpr2, 2 | FPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpr3, 3 | FPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpr4, 4 | FPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpr5, 5 | FPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpr6, 6 | FPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpr7, 7 | FPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpr8, 8 | FPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpr9, 9 | FPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpr10, 10 | FPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpr11, 11 | FPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpr12, 12 | FPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpr13, 13 | FPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpr14, 14 | FPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpr15, 15 | FPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpr16, 16 | FPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpr17, 17 | FPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpr18, 18 | FPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpr19, 19 | FPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpr20, 20 | FPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpr21, 21 | FPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpr22, 22 | FPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpr23, 23 | FPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpr24, 24 | FPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpr25, 25 | FPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpr26, 26 | FPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpr27, 27 | FPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpr28, 28 | FPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpr29, 29 | FPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpr30, 30 | FPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpr31, 31 | FPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fsr0, 0 | FSR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fsr1, 1 | FSR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fsr2, 2 | FSR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fsr3, 3 | FSR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fsr4, 4 | FSR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fsr5, 5 | FSR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fsr6, 6 | FSR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fsr7, 7 | FSR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fsr8, 8 | FSR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fsr9, 9 | FSR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fsr10, 10 | FSR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fsr11, 11 | FSR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fsr12, 12 | FSR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fsr13, 13 | FSR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fsr14, 14 | FSR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fsr15, 15 | FSR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fsr16, 16 | FSR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fsr17, 17 | FSR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fsr18, 18 | FSR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fsr19, 19 | FSR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fsr20, 20 | FSR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fsr21, 21 | FSR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fsr22, 22 | FSR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fsr23, 23 | FSR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fsr24, 24 | FSR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fsr25, 25 | FSR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fsr26, 26 | FSR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fsr27, 27 | FSR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fsr28, 28 | FSR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fsr29, 29 | FSR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fsr30, 30 | FSR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fsr31, 31 | FSR | Arch_ppc32, "ppc32"); - DEF_REGISTER(mq, 0 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(xer, 1 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(lr, 8 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(ctr, 9 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(amr, 13 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(dscr, 17 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(dsisr, 18 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(dar, 19 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(dec, 22 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(sdr1, 25 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(srr0, 26 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(srr1, 27 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cfar, 28 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(amr_pri, 29 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(pid, 48 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(gdecar, 53 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(decar, 54 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(mcivpr, 55 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(lper, 56 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(lperu, 57 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(csrr0, 58 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(csrr1, 59 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(gtsrwr, 60 | SPR | Arch_ppc32, "ppc32"); -// DEF_REGISTER(iamr, 61 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(esr, 62 | SPR | Arch_ppc32, "ppc32"); -// DEF_REGISTER(ivpr, 66 | SPR | Arch_ppc32, "ppc32"); - - DEF_REGISTER(vrsave, 256 | SPR | Arch_ppc32, "ppc32"); - - - DEF_REGISTER(sprg0, 272 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(sprg1, 273 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(sprg2, 274 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(sprg3, 275 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(sprg4, 276 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(sprg5, 277 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(sprg6, 278 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(sprg7, 279 | SPR | Arch_ppc32, "ppc32"); - - DEF_REGISTER(sprg3_ro, 259 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(sprg4_ro, 260 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(sprg5_ro, 261 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(sprg6_ro, 262 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(sprg7_ro, 263 | SPR | Arch_ppc32, "ppc32"); - - - DEF_REGISTER(ear, 282 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(tbl_wo, 284 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(tbl_ro, 268 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(tbu_wo, 285 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(tbu_ro, 269 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(pvr, 287 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(ibat0u, 528 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(ibat0l, 529 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(ibat1u, 530 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(ibat1l, 531 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(ibat2u, 532 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(ibat2l, 533 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(ibat3u, 534 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(ibat3l, 535 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(dbat0u, 536 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(dbat0l, 537 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(dbat1u, 538 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(dbat1l, 539 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(dbat2u, 540 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(dbat2l, 541 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(dbat3u, 542 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(dbat3l, 543 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(pc, 600 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpscw, 601 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpscw0, 602 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpscw1, 603 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpscw2, 604 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpscw3, 605 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpscw4, 606 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpscw5, 607 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpscw6, 608 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(fpscw7, 609 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(msr, 610 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(ivpr, 611 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(ivor8, 612 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(seg0, 613 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(seg1, 614 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(seg2, 615 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(seg3, 616 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(seg4, 617 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(seg5, 618 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(seg6, 619 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(seg7, 620 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr0, 621 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr1, 622 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr2, 623 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr3, 624 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr4, 625 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr5, 626 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr6, 627 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr7, 628 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr, 629 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(or3, 630 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(trap, 631 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr0l, 700 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr0g, 701 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr0e, 702 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr0s, 703 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr1l, 704 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr1g, 705 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr1e, 706 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr1s, 707 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr2l, 708 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr2g, 709 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr2e, 710 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr2s, 711 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr3l, 712 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr3g, 713 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr3e, 714 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr3s, 715 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr4l, 716 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr4g, 717 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr4e, 718 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr4s, 719 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr5l, 720 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr5g, 721 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr5e, 722 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr5s, 723 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr6l, 724 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr6g, 725 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr6e, 726 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr6s, 727 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr7l, 728 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr7g, 729 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr7e, 730 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(cr7s, 731 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(ppr, 896 | SPR | Arch_ppc32, "ppc32"); - DEF_REGISTER(ppr32, 898 | SPR | Arch_ppc32, "ppc32"); - - - } - namespace ppc64 { - const signed int GPR = 0x00010000; - const signed int FPR = 0x00020000; - const signed int FSR = 0x00040000; - const signed int SPR = 0x00080000; - const signed int VSR = 0x00000000; - - DEF_REGISTER(r0, 0 | GPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(r1, 1 | GPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(r2, 2 | GPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(r3, 3 | GPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(r4, 4 | GPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(r5, 5 | GPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(r6, 6 | GPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(r7, 7 | GPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(r8, 8 | GPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(r9, 9 | GPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(r10, 10 | GPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(r11, 11 | GPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(r12, 12 | GPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(r13, 13 | GPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(r14, 14 | GPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(r15, 15 | GPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(r16, 16 | GPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(r17, 17 | GPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(r18, 18 | GPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(r19, 19 | GPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(r20, 20 | GPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(r21, 21 | GPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(r22, 22 | GPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(r23, 23 | GPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(r24, 24 | GPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(r25, 25 | GPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(r26, 26 | GPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(r27, 27 | GPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(r28, 28 | GPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(r29, 29 | GPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(r30, 30 | GPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(r31, 31 | GPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpr0, 0 | FPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpr1, 1 | FPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpr2, 2 | FPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpr3, 3 | FPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpr4, 4 | FPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpr5, 5 | FPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpr6, 6 | FPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpr7, 7 | FPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpr8, 8 | FPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpr9, 9 | FPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpr10, 10 | FPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpr11, 11 | FPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpr12, 12 | FPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpr13, 13 | FPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpr14, 14 | FPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpr15, 15 | FPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpr16, 16 | FPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpr17, 17 | FPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpr18, 18 | FPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpr19, 19 | FPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpr20, 20 | FPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpr21, 21 | FPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpr22, 22 | FPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpr23, 23 | FPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpr24, 24 | FPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpr25, 25 | FPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpr26, 26 | FPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpr27, 27 | FPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpr28, 28 | FPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpr29, 29 | FPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpr30, 30 | FPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpr31, 31 | FPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fsr0, 0 | FSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fsr1, 1 | FSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fsr2, 2 | FSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fsr3, 3 | FSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fsr4, 4 | FSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fsr5, 5 | FSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fsr6, 6 | FSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fsr7, 7 | FSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fsr8, 8 | FSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fsr9, 9 | FSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fsr10, 10 | FSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fsr11, 11 | FSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fsr12, 12 | FSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fsr13, 13 | FSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fsr14, 14 | FSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fsr15, 15 | FSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fsr16, 16 | FSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fsr17, 17 | FSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fsr18, 18 | FSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fsr19, 19 | FSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fsr20, 20 | FSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fsr21, 21 | FSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fsr22, 22 | FSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fsr23, 23 | FSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fsr24, 24 | FSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fsr25, 25 | FSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fsr26, 26 | FSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fsr27, 27 | FSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fsr28, 28 | FSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fsr29, 29 | FSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fsr30, 30 | FSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fsr31, 31 | FSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(mq, 0 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(xer, 1 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(lr, 8 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(ctr, 9 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(dsisr, 18 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(dar, 19 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(dec, 22 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(sdr1, 25 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(srr0, 26 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(srr1, 27 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vrsave, 256 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(sprg0, 272 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(sprg1, 273 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(sprg2, 274 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(sprg3, 275 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(sprg4, 276 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(sprg5, 277 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(sprg6, 278 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(sprg7, 279 | SPR | Arch_ppc64, "ppc64"); - - DEF_REGISTER(sprg3_ro, 259 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(sprg4_ro, 260 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(sprg5_ro, 261 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(sprg6_ro, 262 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(sprg7_ro, 263 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(ear, 282 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(tbl_wo, 284 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(tbl_ro, 268 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(tbu_wo, 285 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(tbu_ro, 269 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(pvr, 287 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(ibat0u, 528 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(ibat0l, 529 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(ibat1u, 530 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(ibat1l, 531 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(ibat2u, 532 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(ibat2l, 533 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(ibat3u, 534 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(ibat3l, 535 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(dbat0u, 536 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(dbat0l, 537 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(dbat1u, 538 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(dbat1l, 539 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(dbat2u, 540 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(dbat2l, 541 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(dbat3u, 542 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(dbat3l, 543 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(pc, 600 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpscw, 601 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpscw0, 602 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpscw1, 603 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpscw2, 604 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpscw3, 605 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpscw4, 606 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpscw5, 607 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpscw6, 608 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(fpscw7, 609 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(msr, 610 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(ivpr, 611 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(ivor8, 612 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(seg0, 613 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(seg1, 614 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(seg2, 615 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(seg3, 616 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(seg4, 617 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(seg5, 618 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(seg6, 619 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(seg7, 620 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr0, 621 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr1, 622 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr2, 623 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr3, 624 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr4, 625 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr5, 626 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr6, 627 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr7, 628 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr, 629 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(or3, 630 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(trap, 631 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr0l, 700 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr0g, 701 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr0e, 702 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr0s, 703 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr1l, 704 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr1g, 705 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr1e, 706 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr1s, 707 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr2l, 708 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr2g, 709 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr2e, 710 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr2s, 711 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr3l, 712 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr3g, 713 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr3e, 714 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr3s, 715 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr4l, 716 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr4g, 717 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr4e, 718 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr4s, 719 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr5l, 720 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr5g, 721 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr5e, 722 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr5s, 723 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr6l, 724 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr6g, 725 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr6e, 726 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr6s, 727 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr7l, 728 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr7g, 729 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr7e, 730 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(cr7s, 731 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(ppr, 896 | SPR | Arch_ppc64, "ppc64"); - DEF_REGISTER(ppr32, 898 | SPR | Arch_ppc64, "ppc64"); - - DEF_REGISTER(vsr0, 0 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr1, 1 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr2, 2 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr3, 3 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr4, 4 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr5, 5 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr6, 6 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr7, 7 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr8, 8 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr9, 9 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr10, 10 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr11, 11 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr12, 12 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr13, 13 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr14, 14 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr15, 15 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr16, 16 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr17, 17 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr18, 18 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr19, 19 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr20, 20 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr21, 21 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr22, 22 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr23, 23 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr24, 24 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr25, 25 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr26, 26 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr27, 27 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr28, 28 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr29, 29 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr30, 30 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr31, 31 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr32, 32 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr33, 33 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr34, 34 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr35, 35 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr36, 36 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr37, 37 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr38, 38 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr39, 39 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr40, 40 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr41, 41 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr42, 42 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr43, 43 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr44, 44 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr45, 45 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr46, 46 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr47, 47 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr48, 48 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr49, 49 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr50, 50 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr51, 51 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr52, 52 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr53, 53 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr54, 54 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr55, 55 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr56, 56 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr57, 57 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr58, 58 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr59, 59 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr60, 60 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr61, 61 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr62, 62 | VSR | Arch_ppc64, "ppc64"); - DEF_REGISTER(vsr63, 63 | VSR | Arch_ppc64, "ppc64"); - - - - - } - - namespace aarch64{ - //0xff000000 0x00ff0000 0x0000ff00 0x000000ff - //arch reg cat:GPR alias&subrange reg ID - const signed int GPR = 0x00010000; - const signed int FPR = 0x00020000; - const signed int FLAG = 0x00030000; - const signed int FSR = 0x00040000; - const signed int SPR = 0x00080000; - const signed int SYSREG = 0x00100000; - - const signed int BIT = 0x00008000; - const signed int B_REG = 0x00000100; //8bit byte reg - const signed int W_REG = 0x00000300; //16bit half-wor reg - const signed int D_REG = 0x00000f00; //32bit single-word reg - const signed int FULL = 0x00000000; //64bit double-word reg - const signed int Q_REG = 0x00000400; //128bit reg - const signed int HQ_REG = 0x00000500; //second 64bit in 128bit reg - - //31 GPRs, double word long registers - // (name regID| alias | cat | arch arch ) - DEF_REGISTER(x0, 0 | FULL |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(w0, 0 | D_REG |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(x1, 1 | FULL |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(w1, 1 | D_REG |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(x2, 2 | FULL |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(w2, 2 | D_REG |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(x3, 3 | FULL |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(w3, 3 | D_REG |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(x4, 4 | FULL |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(w4, 4 | D_REG |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(x5, 5 | FULL |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(w5, 5 | D_REG |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(x6, 6 | FULL |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(w6, 6 | D_REG |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(x7, 7 | FULL |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(w7, 7 | D_REG |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(x8, 8 | FULL |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(w8, 8 | D_REG |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(x9, 9 | FULL |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(w9, 9 | D_REG |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(x10, 10 | FULL |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(w10, 10 | D_REG |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(x11, 11 | FULL |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(w11, 11 | D_REG |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(x12, 12 | FULL |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(w12, 12 | D_REG |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(x13, 13 | FULL |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(w13, 13 | D_REG |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(x14, 14 | FULL |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(w14, 14 | D_REG |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(x15, 15 | FULL |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(w15, 15 | D_REG |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(x16, 16 | FULL |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(w16, 16 | D_REG |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(x17, 17 | FULL |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(w17, 17 | D_REG |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(x18, 18 | FULL |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(w18, 18 | D_REG |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(x19, 19 | FULL |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(w19, 19 | D_REG |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(x20, 20 | FULL |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(w20, 20 | D_REG |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(x21, 21 | FULL |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(w21, 21 | D_REG |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(x22, 22 | FULL |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(w22, 22 | D_REG |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(x23, 23 | FULL |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(w23, 23 | D_REG |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(x24, 24 | FULL |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(w24, 24 | D_REG |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(x25, 25 | FULL |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(w25, 25 | D_REG |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(x26, 26 | FULL |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(w26, 26 | D_REG |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(x27, 27 | FULL |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(w27, 27 | D_REG |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(x28, 28 | FULL |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(w28, 28 | D_REG |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(x29, 29 | FULL |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(w29, 29 | D_REG |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(x30, 30 | FULL |GPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(w30, 30 | D_REG |GPR | Arch_aarch64, "aarch64"); - - //32 FPRs-----------q-d-s-h-b - //128 bit - DEF_REGISTER(q0, 0 | Q_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(q1, 1 | Q_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(q2, 2 | Q_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(q3, 3 | Q_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(q4, 4 | Q_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(q5, 5 | Q_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(q6, 6 | Q_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(q7, 7 | Q_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(q8, 8 | Q_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(q9, 9 | Q_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(q10, 10 | Q_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(q11, 11 | Q_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(q12, 12 | Q_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(q13, 13 | Q_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(q14, 14 | Q_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(q15, 15 | Q_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(q16, 16 | Q_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(q17, 17 | Q_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(q18, 18 | Q_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(q19, 19 | Q_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(q20, 20 | Q_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(q21, 21 | Q_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(q22, 22 | Q_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(q23, 23 | Q_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(q24, 24 | Q_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(q25, 25 | Q_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(q26, 26 | Q_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(q27, 27 | Q_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(q28, 28 | Q_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(q29, 29 | Q_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(q30, 30 | Q_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(q31, 31 | Q_REG |FPR | Arch_aarch64, "aarch64"); - - // second 64bit - DEF_REGISTER(hq0, 0 | HQ_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(hq1, 1 | HQ_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(hq2, 2 | HQ_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(hq3, 3 | HQ_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(hq4, 4 | HQ_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(hq5, 5 | HQ_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(hq6, 6 | HQ_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(hq7, 7 | HQ_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(hq8, 8 | HQ_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(hq9, 9 | HQ_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(hq10, 10 | HQ_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(hq11, 11 | HQ_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(hq12, 12 | HQ_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(hq13, 13 | HQ_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(hq14, 14 | HQ_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(hq15, 15 | HQ_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(hq16, 16 | HQ_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(hq17, 17 | HQ_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(hq18, 18 | HQ_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(hq19, 19 | HQ_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(hq20, 20 | HQ_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(hq21, 21 | HQ_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(hq22, 22 | HQ_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(hq23, 23 | HQ_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(hq24, 24 | HQ_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(hq25, 25 | HQ_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(hq26, 26 | HQ_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(hq27, 27 | HQ_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(hq28, 28 | HQ_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(hq29, 29 | HQ_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(hq30, 30 | HQ_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(hq31, 31 | HQ_REG |FPR | Arch_aarch64, "aarch64"); - - //64bit FP regs - DEF_REGISTER(d0, 0 | FULL |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(d1, 1 | FULL |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(d2, 2 | FULL |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(d3, 3 | FULL |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(d4, 4 | FULL |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(d5, 5 | FULL |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(d6, 6 | FULL |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(d7, 7 | FULL |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(d8, 8 | FULL |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(d9, 9 | FULL |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(d10, 10 | FULL |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(d11, 11 | FULL |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(d12, 12 | FULL |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(d13, 13 | FULL |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(d14, 14 | FULL |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(d15, 15 | FULL |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(d16, 16 | FULL |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(d17, 17 | FULL |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(d18, 18 | FULL |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(d19, 19 | FULL |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(d20, 20 | FULL |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(d21, 21 | FULL |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(d22, 22 | FULL |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(d23, 23 | FULL |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(d24, 24 | FULL |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(d25, 25 | FULL |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(d26, 26 | FULL |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(d27, 27 | FULL |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(d28, 28 | FULL |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(d29, 29 | FULL |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(d30, 30 | FULL |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(d31, 31 | FULL |FPR | Arch_aarch64, "aarch64"); - - //32 bit FP regs - DEF_REGISTER(s0, 0 | D_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(s1, 1 | D_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(s2, 2 | D_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(s3, 3 | D_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(s4, 4 | D_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(s5, 5 | D_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(s6, 6 | D_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(s7, 7 | D_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(s8, 8 | D_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(s9, 9 | D_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(s10, 10 | D_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(s11, 11 | D_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(s12, 12 | D_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(s13, 13 | D_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(s14, 14 | D_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(s15, 15 | D_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(s16, 16 | D_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(s17, 17 | D_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(s18, 18 | D_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(s19, 19 | D_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(s20, 20 | D_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(s21, 21 | D_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(s22, 22 | D_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(s23, 23 | D_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(s24, 24 | D_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(s25, 25 | D_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(s26, 26 | D_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(s27, 27 | D_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(s28, 28 | D_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(s29, 29 | D_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(s30, 30 | D_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(s31, 31 | D_REG |FPR | Arch_aarch64, "aarch64"); - - - //16 bit FP regs - DEF_REGISTER(h0, 0 | W_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(h1, 1 | W_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(h2, 2 | W_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(h3, 3 | W_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(h4, 4 | W_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(h5, 5 | W_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(h6, 6 | W_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(h7, 7 | W_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(h8, 8 | W_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(h9, 9 | W_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(h10, 10 | W_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(h11, 11 | W_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(h12, 12 | W_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(h13, 13 | W_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(h14, 14 | W_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(h15, 15 | W_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(h16, 16 | W_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(h17, 17 | W_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(h18, 18 | W_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(h19, 19 | W_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(h20, 20 | W_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(h21, 21 | W_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(h22, 22 | W_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(h23, 23 | W_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(h24, 24 | W_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(h25, 25 | W_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(h26, 26 | W_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(h27, 27 | W_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(h28, 28 | W_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(h29, 29 | W_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(h30, 30 | W_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(h31, 31 | W_REG |FPR | Arch_aarch64, "aarch64"); - - //8 bit FP regs - DEF_REGISTER(b0, 0 | B_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(b1, 1 | B_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(b2, 2 | B_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(b3, 3 | B_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(b4, 4 | B_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(b5, 5 | B_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(b6, 6 | B_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(b7, 7 | B_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(b8, 8 | B_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(b9, 9 | B_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(b10, 10 | B_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(b11, 11 | B_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(b12, 12 | B_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(b13, 13 | B_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(b14, 14 | B_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(b15, 15 | B_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(b16, 16 | B_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(b17, 17 | B_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(b18, 18 | B_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(b19, 19 | B_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(b20, 20 | B_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(b21, 21 | B_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(b22, 22 | B_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(b23, 23 | B_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(b24, 24 | B_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(b25, 25 | B_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(b26, 26 | B_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(b27, 27 | B_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(b28, 28 | B_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(b29, 29 | B_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(b30, 30 | B_REG |FPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(b31, 31 | B_REG |FPR | Arch_aarch64, "aarch64"); - -#include "aarch64_sys_regs.h" - - //GPRs aliases: - //by convention - //x29 is used as frame pointer - //x30 is the linking register - //x31 can be sp or zero register depending on the context - - //special registers - //PC is not writable in aarch64 - const signed int N_FLAG = 31; - const signed int Z_FLAG = 30; - const signed int C_FLAG = 29; - const signed int V_FLAG = 28; - - DEF_REGISTER(sp, 31| FULL |SPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(wsp, 0 | D_REG |SPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(pc, 32| FULL |SPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(pstate, 2 | D_REG |SPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(xzr, 3 | FULL |SPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(n, N_FLAG | BIT |FLAG| Arch_aarch64, "aarch64"); - DEF_REGISTER(z, Z_FLAG | BIT |FLAG| Arch_aarch64, "aarch64"); - DEF_REGISTER(c, C_FLAG | BIT |FLAG| Arch_aarch64, "aarch64"); - DEF_REGISTER(v, V_FLAG | BIT |FLAG| Arch_aarch64, "aarch64"); - DEF_REGISTER(wzr, 3 | D_REG |SPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(fpcr, 4 | D_REG |SPR | Arch_aarch64, "aarch64"); - DEF_REGISTER(fpsr, 5 | D_REG |SPR | Arch_aarch64, "aarch64"); - - } //end of aarch64 namespace - namespace amdgpu_vega{ - //0xff000000 0x00ff0000 0x0000ff00 0x000000ff - //arch reg cat:GPR alias&subrange reg ID - const signed int SGPR = 0x00010000; - const signed int SGPR_VEC2 = 0x00020000; - const signed int SGPR_VEC4 = 0x00030000; - const signed int SGPR_VEC8 = 0x00040000; - const signed int SGPR_VEC16 = 0x00050000; - - const signed int VGPR = 0x00060000; - const signed int VGPR_VEC2 = 0x00070000; - const signed int VGPR_VEC4 = 0x00080000; - const signed int VGPR_VEC8 = 0x00090000; - const signed int VGPR_VEC16 = 0x000A0000; - - const signed int HWR = 0x000B0000; - const signed int TTMP_SGPR = 0x000C0000; - const signed int FLAGS = 0x000D0000; - const signed int PC = 0x000E0000; - const signed int SYSREG = 0x00100000; - - // aliasing for flags - // if we found out that it is a flag, we no longer need to use the cat 0x00ff0000 - // so we use thhat part to encode the low offset in the base register - // - - - - const signed int BITS_1 = 0x00000100; - const signed int BITS_2 = 0x00000200; - const signed int BITS_3 = 0x00000300; - const signed int BITS_4 = 0x00000400; - const signed int BITS_6 = 0x00000500; - const signed int BITS_7 = 0x00000600; - const signed int BITS_8 = 0x00000700; - const signed int BITS_9 = 0x00000800; - const signed int BITS_15 = 0x00000900; - const signed int BITS_16 = 0x00000A00; - const signed int BITS_32 = 0x00000B00; - const signed int BITS_48 = 0x00000C00; - const signed int BITS_64 = 0x00000D00; - const signed int BITS_128 = 0x00000E00; - const signed int BITS_256 = 0x00000F00; - const signed int BITS_512 = 0x00001000; - - - - - /*const signed int BIT = 0x00001000; - const signed int D_BIT = 0x00002000; - const signed int T_BIT = 0x00003000; - const signed int Q_BIT = 0x00004000; - const signed int H_BIT = 0x00006000; - const signed int S_BIT = 0x00007000; - const signed int O_BIT = 0x00008000; - const signed int N_BIT = 0x00009000; - const signed int D_REG_BIT = 0x0000A000; - - const signed int B_REG = 0x00000100; //8bit byte reg - const signed int W_REG = 0x00000200; //16bit half-wor reg - const signed int D_REG = 0x00000300; //32bit single-word reg - const signed int FE_REG = 0x00000400; //48bit reg - const signed int FULL = 0x00000500; //64bit double-word reg - const signed int Q_REG = 0x00000600; //128bit reg - const signed int YMMS = 0x00000700; //256bit reg - const signed int ZMMS = 0x00000800; //512bit reg - const signed int HQ_REG = 0x00000900; //second 64bit in 128bit reg*/ - - #include "amdgpu_vega_sys_regs.h" - } - - - namespace cuda { - const signed int GPR = 0x00000000; - const signed int PR = 0x00010000; - const signed int BR = 0x00020000; - const signed int UR = 0x00040000; - const signed int UPR = 0x00080000; - - // General purpose registers - DEF_REGISTER(r0, 0 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r1, 1 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r2, 2 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r3, 3 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r4, 4 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r5, 5 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r6, 6 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r7, 7 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r8, 8 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r9, 9 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r10, 10 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r11, 11 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r12, 12 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r13, 13 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r14, 14 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r15, 15 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r16, 16 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r17, 17 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r18, 18 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r19, 19 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r20, 20 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r21, 21 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r22, 22 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r23, 23 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r24, 24 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r25, 25 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r26, 26 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r27, 27 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r28, 28 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r29, 29 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r30, 30 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r31, 31 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r32, 32 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r33, 33 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r34, 34 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r35, 35 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r36, 36 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r37, 37 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r38, 38 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r39, 39 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r40, 40 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r41, 41 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r42, 42 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r43, 43 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r44, 44 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r45, 45 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r46, 46 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r47, 47 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r48, 48 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r49, 49 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r50, 50 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r51, 51 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r52, 52 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r53, 53 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r54, 54 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r55, 55 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r56, 56 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r57, 57 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r58, 58 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r59, 59 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r60, 60 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r61, 61 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r62, 62 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r63, 63 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r64, 64 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r65, 65 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r66, 66 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r67, 67 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r68, 68 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r69, 69 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r70, 70 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r71, 71 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r72, 72 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r73, 73 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r74, 74 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r75, 75 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r76, 76 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r77, 77 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r78, 78 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r79, 79 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r80, 80 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r81, 81 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r82, 82 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r83, 83 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r84, 84 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r85, 85 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r86, 86 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r87, 87 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r88, 88 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r89, 89 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r90, 90 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r91, 91 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r92, 92 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r93, 93 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r94, 94 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r95, 95 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r96, 96 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r97, 97 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r98, 98 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r99, 99 | GPR | Arch_cuda, "cuda"); - DEF_REGISTER(r100, 100 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r101, 101 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r102, 102 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r103, 103 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r104, 104 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r105, 105 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r106, 106 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r107, 107 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r108, 108 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r109, 109 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r110, 110 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r111, 111 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r112, 112 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r113, 113 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r114, 114 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r115, 115 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r116, 116 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r117, 117 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r118, 118 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r119, 119 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r120, 120 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r121, 121 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r122, 122 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r123, 123 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r124, 124 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r125, 125 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r126, 126 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r127, 127 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r128, 128 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r129, 129 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r130, 130 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r131, 131 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r132, 132 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r133, 133 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r134, 134 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r135, 135 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r136, 136 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r137, 137 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r138, 138 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r139, 139 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r140, 140 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r141, 141 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r142, 142 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r143, 143 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r144, 144 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r145, 145 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r146, 146 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r147, 147 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r148, 148 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r149, 149 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r150, 150 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r151, 151 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r152, 152 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r153, 153 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r154, 154 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r155, 155 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r156, 156 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r157, 157 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r158, 158 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r159, 159 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r160, 160 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r161, 161 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r162, 162 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r163, 163 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r164, 164 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r165, 165 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r166, 166 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r167, 167 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r168, 168 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r169, 169 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r170, 170 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r171, 171 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r172, 172 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r173, 173 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r174, 174 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r175, 175 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r176, 176 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r177, 177 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r178, 178 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r179, 179 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r180, 180 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r181, 181 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r182, 182 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r183, 183 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r184, 184 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r185, 185 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r186, 186 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r187, 187 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r188, 188 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r189, 189 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r190, 190 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r191, 191 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r192, 192 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r193, 193 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r194, 194 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r195, 195 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r196, 196 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r197, 197 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r198, 198 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r199, 199 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r200, 200 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r201, 201 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r202, 202 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r203, 203 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r204, 204 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r205, 205 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r206, 206 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r207, 207 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r208, 208 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r209, 209 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r210, 210 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r211, 211 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r212, 212 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r213, 213 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r214, 214 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r215, 215 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r216, 216 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r217, 217 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r218, 218 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r219, 219 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r220, 220 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r221, 221 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r222, 222 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r223, 223 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r224, 224 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r225, 225 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r226, 226 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r227, 227 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r228, 228 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r229, 229 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r230, 230 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r231, 231 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r232, 232 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r233, 233 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r234, 234 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r235, 235 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r236, 236 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r237, 237 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r238, 238 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r239, 239 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r240, 240 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r241, 241 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r242, 242 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r243, 243 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r244, 244 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r245, 245 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r246, 246 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r247, 247 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r248, 248 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r249, 249 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r250, 250 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r251, 251 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r252, 252 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r253, 253 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r254, 254 | GPR| Arch_cuda, "cuda"); - DEF_REGISTER(r255, 255 | GPR| Arch_cuda, "cuda"); - - // uniform registers - DEF_REGISTER(ur0, 0 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur1, 1 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur2, 2 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur3, 3 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur4, 4 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur5, 5 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur6, 6 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur7, 7 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur8, 8 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur9, 9 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur10, 10 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur11, 11 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur12, 12 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur13, 13 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur14, 14 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur15, 15 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur16, 16 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur17, 17 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur18, 18 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur19, 19 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur20, 20 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur21, 21 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur22, 22 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur23, 23 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur24, 24 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur25, 25 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur26, 26 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur27, 27 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur28, 28 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur29, 29 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur30, 30 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur31, 31 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur32, 32 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur33, 33 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur34, 34 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur35, 35 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur36, 36 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur37, 37 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur38, 38 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur39, 39 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur40, 40 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur41, 41 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur42, 42 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur43, 43 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur44, 44 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur45, 45 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur46, 46 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur47, 47 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur48, 48 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur49, 49 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur50, 50 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur51, 51 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur52, 52 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur53, 53 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur54, 54 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur55, 55 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur56, 56 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur57, 57 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur58, 58 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur59, 59 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur60, 60 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur61, 61 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur62, 62 | UR | Arch_cuda, "cuda"); - DEF_REGISTER(ur63, 63 | UR | Arch_cuda, "cuda"); - - // Placeholder for a pc register, so that we don't assert - DEF_REGISTER(pc, 256 | GPR| Arch_cuda, "cuda"); - - // Predicate registers used as source or dest operands - // Different from a predicate register used as instruction predicate, - // which is handle by operand::isTruePredicate and operand::isFalsePredicate - DEF_REGISTER(p0, 0 | PR | Arch_cuda, "cuda"); - DEF_REGISTER(p1, 1 | PR | Arch_cuda, "cuda"); - DEF_REGISTER(p2, 2 | PR | Arch_cuda, "cuda"); - DEF_REGISTER(p3, 3 | PR | Arch_cuda, "cuda"); - DEF_REGISTER(p4, 4 | PR | Arch_cuda, "cuda"); - DEF_REGISTER(p5, 5 | PR | Arch_cuda, "cuda"); - DEF_REGISTER(p6, 6 | PR | Arch_cuda, "cuda"); - - DEF_REGISTER(b1, 1 | BR | Arch_cuda, "cuda"); - DEF_REGISTER(b2, 2 | BR | Arch_cuda, "cuda"); - DEF_REGISTER(b3, 3 | BR | Arch_cuda, "cuda"); - DEF_REGISTER(b4, 4 | BR | Arch_cuda, "cuda"); - DEF_REGISTER(b5, 5 | BR | Arch_cuda, "cuda"); - DEF_REGISTER(b6, 6 | BR | Arch_cuda, "cuda"); - - // XXX(Keren): not sure how many uprs, use 16 for safety - DEF_REGISTER(up0, 0 | UPR | Arch_cuda, "cuda"); - DEF_REGISTER(up1, 1 | UPR | Arch_cuda, "cuda"); - DEF_REGISTER(up2, 2 | UPR | Arch_cuda, "cuda"); - DEF_REGISTER(up3, 3 | UPR | Arch_cuda, "cuda"); - DEF_REGISTER(up4, 4 | UPR | Arch_cuda, "cuda"); - DEF_REGISTER(up5, 5 | UPR | Arch_cuda, "cuda"); - DEF_REGISTER(up6, 6 | UPR | Arch_cuda, "cuda"); - DEF_REGISTER(up7, 7 | UPR | Arch_cuda, "cuda"); - DEF_REGISTER(up8, 8 | UPR | Arch_cuda, "cuda"); - DEF_REGISTER(up9, 9 | UPR | Arch_cuda, "cuda"); - DEF_REGISTER(up10, 10 | UPR | Arch_cuda, "cuda"); - DEF_REGISTER(up11, 11 | UPR | Arch_cuda, "cuda"); - DEF_REGISTER(up12, 12 | UPR | Arch_cuda, "cuda"); - DEF_REGISTER(up13, 13 | UPR | Arch_cuda, "cuda"); - DEF_REGISTER(up14, 14 | UPR | Arch_cuda, "cuda"); - DEF_REGISTER(up15, 15 | UPR | Arch_cuda, "cuda"); - } //end of cuda namespace -} +#include "Architecture.h" +#include "registers/MachRegister.h" + +#include "registers/abstract_regs.h" +#include "registers/x86_regs.h" +#include "registers/x86_64_regs.h" +#include "registers/ppc32_regs.h" +#include "registers/ppc64_regs.h" +#include "registers/aarch64_regs.h" +#include "registers/AMDGPU/amdgpu_gfx908_regs.h" +#include "registers/AMDGPU/amdgpu_gfx90a_regs.h" +#include "registers/AMDGPU/amdgpu_gfx940_regs.h" +#include "registers/cuda_regs.h" #endif diff --git a/common/h/dyninst_visibility.h b/common/h/dyninst_visibility.h new file mode 100644 index 0000000000..bdd05c6683 --- /dev/null +++ b/common/h/dyninst_visibility.h @@ -0,0 +1,6 @@ +#ifndef DYNINST_COMMON_DYNINST_VISIBILITY_H +#define DYNINST_COMMON_DYNINST_VISIBILITY_H + +#define DYNINST_EXPORT __attribute__((visibility ("default"))) + +#endif diff --git a/common/h/dyntypes.h b/common/h/dyntypes.h index e3b593f8d1..121dc8b7fe 100644 --- a/common/h/dyntypes.h +++ b/common/h/dyntypes.h @@ -40,6 +40,7 @@ #endif #ifndef FILE__ +#include #if defined(_MSC_VER) #define FILE__ (strrchr(__FILE__, '\\') ? strrchr(__FILE__, '\\') + 1 : __FILE__) #else @@ -47,10 +48,11 @@ #endif #endif -#if defined(_POWER) && !defined(__GNUC__) -#define XLC -#endif +#ifdef __cplusplus +#include +#include +#include #include #include @@ -74,13 +76,15 @@ using dyn_hash_set = std::unordered_set; namespace Dyninst { #if defined(_WIN64) - typedef uintptr_t Address; - typedef uintptr_t Offset; + typedef uintptr_t Address; + typedef uintptr_t Offset; #else - typedef unsigned long Address; - typedef unsigned long Offset; + typedef unsigned long Address; + typedef unsigned long Offset; #endif + static constexpr Address ADDR_NULL{0}; + #if defined(_MSC_VER) typedef int PID; typedef HANDLE PROC_HANDLE; @@ -106,7 +110,7 @@ namespace Dyninst #endif #endif - int ThrIDToTid(Dyninst::THR_ID id); + inline int ThrIDToTid(Dyninst::THR_ID id) { return id; } } namespace Dyninst @@ -119,4 +123,9 @@ namespace Dyninst } OSType; } +#else +# define ADDR_NULL (0) +typedef unsigned long Address; +#endif + #endif diff --git a/common/h/entryIDs.h b/common/h/entryIDs.h index 60a7843197..86e54abd44 100644 --- a/common/h/entryIDs.h +++ b/common/h/entryIDs.h @@ -31,2988 +31,24 @@ #if !defined(ENTRYIDS_IA32_H) #define ENTRYIDS_IA32_H +#include #include "dyntypes.h" #include "util.h" +/* clang-format off */ enum entryID : unsigned int { - e_jb = 0, - e_ja, - e_jb_jnaej_j, - e_jbe, - e_jge, - e_jcxz_jec, - e_jl, - e_jle, - e_jmp, - e_jmpq, - e_jmpe, - e_je, - e_jnb, - e_jne, - e_jnb_jae_j, - e_jnbe, - e_jnl, - e_jnle, - e_jno, - e_jnp, - e_jns, - e_jnz, - e_jo, - e_jp, - e_js, - e_jz, - e_jg, - e_jrcxz, - e_loop, - e_loope, - e_loopn, - e_loopne, - e_call, - e_callq, - e_cmp, - e_cmpw, - e_cmpsl, - e_cmppd, - e_cmpps, - e_cmpsb, - e_cmpsd, - e_cmpsd_sse, - e_cmpss, - e_cmpsw, - e_cmpxch, - e_cmpxch8b, - e_ret_far, - e_ret_near, - e_prefetch, - e_prefetchNTA, - e_prefetchT0, - e_prefetchT1, - e_prefetchT2, - e_prefetch_w, - e_prefetchw, - e_prefetcht1, - e_No_Entry, - e_aaa, - e_aad, - e_aam, - e_aas, - e_adc, - e_add, - e_addpd, - e_addps, - e_addsd, - e_addss, - e_addsubpd, - e_addsubps, - e_and, - e_andnpd, - e_andnps, - e_andpd, - e_andps, - e_arpl, - e_blendpd, // SSE 4.1 - e_blendps, // SSE 4.1 - e_blendvpd, // SSE 4.1 - e_blendvps, // SSE 4.1 - e_bound, - e_bsf, - e_bsr, - e_bswap, - e_bt, - e_btc, - e_btr, - e_bts, - e_cbw, - e_cdq, - e_clc, - e_cld, - e_clflush, - e_cli, - e_clts, - e_cmc, - e_cmovbe, - e_cmove, - e_cmovnae, - e_cmovnb, - e_cmovnbe, - e_cmovne, - e_cmovng, - e_cmovnge, - e_cmovnl, - e_cmovno, - e_cmovns, - e_cmovo, - e_cmovpe, - e_cmovpo, - e_cmovs, - e_comisd, - e_comiss, - e_cpuid, - e_crc32, // SSE 4.2 - e_cvtdq2pd, - e_cvtdq2ps, - e_cvtpd2dq, - e_cvtpd2pi, - e_cvtpd2ps, - e_cvtpi2pd, - e_cvtpi2ps, - e_cvtps2dq, - e_cvtps2pd, - e_cvtps2pi, - e_cvtsd2si, - e_cvtsd2ss, - e_cvtsi2sd, - e_cvtsi2ss, - e_cvtss2sd, - e_cvtss2si, - e_cvttpd2dq, - e_cvttpd2pi, - e_cvttps2dq, - e_cvttps2pi, - e_cvttsd2si, - e_cvttss2si, - e_cwd, - e_cwde, - e_cwtl, - e_aesenc, - e_aesenclast, - e_aesdec, - e_aesdeclast, - e_vaesenc, - e_vaesenclast, - e_vaesdec, - e_vaesdeclast, - e_aeskeygenassist, - e_vaeskeygenassist, - e_aesimc, - e_vaesimc, - e_pclmullqlqdq, - e_vpclmullqlqdq, - e_vpperm, - e_daa, - e_das, - e_dec, - e_decl, - e_div, - e_divpd, - e_divps, - e_divsd, - e_divss, - e_dppd, // SSE 4.1 - e_vdppd, // SSE 4.1 - e_dpps, // SSE 4.1 - e_emms, - e_enter, - e_enterq, - e_extractps, // SSE 4.1 - e_extrq, - e_fadd, - e_faddp, - e_f2xm1, - e_fbld, - e_fbstp, - e_fchs, - e_fcmovb, - e_fcmovbe, - e_fcmove, - e_fcmovne, - e_fcmovu, - e_fcmovnu, - e_fcmovnb, - e_fcmovnbe, - e_fcom, - e_fcomi, - e_fcomip, - e_fcomp, - e_fcomps, - e_fcompp, - e_fdiv, - e_fdivp, - e_fdivr, - e_fdivrp, - e_femms, - e_ffree, - e_ffreep, - e_fiadd, - e_ficom, - e_ficomp, - e_fidiv, - e_fidivr, - e_fild, - e_fimul, - e_fist, - e_fistp, - e_fisttp, - e_fisub, - e_fisubr, - e_fld, - e_fld1, // note: numeral '1', as in load the constant - e_fldcw, - e_fldenv, - e_fmul, - e_fmulp, - e_fnop, - e_fnstcw, - e_fprem, - e_frstor, - e_fsave, - e_xbegin, - e_xabort, - e_xrstors, - e_fst, - e_fstcw, - e_fstenv, - e_fstp, - e_fstsw, - e_fsub, - e_fsubl, - e_fsubp, - e_fsubr, - e_fsubrp, - e_fucom, - e_fucomp, - e_fucomi, - e_fucomip, - e_fucompp, - e_fxch, - e_fxrstor, - e_fxsave, - e_xsave, - e_xsavec, - e_xrstor, - e_haddpd, - e_haddps, - e_hlt, - e_hsubpd, - e_hsubps, - e_idiv, - e_imul, - e_in, - e_inc, - e_insb, - e_insd, - e_insertps, // SSE 4.1 - e_insertq, - e_insw, - e_int, - e_int3, - e_int1, - e_int80, - e_into, - e_invd, - e_invlpg, - e_iret, - e_lahf, - e_lar, - e_lddqu, - e_ldmxcsr, - e_lds, - e_lea, - e_leave, - e_leaveq, - e_les, - e_lfence, - e_lfs, - e_lgdt, - e_lgs, - e_lidt, - e_lldt, - e_lmsw, - e_lods, - e_lodsb, - e_lodsd, - e_lodsw, - e_lsl, - e_lss, - e_ltr, - e_maskmovdqu, - e_maskmovq, - e_maxpd, - e_maxps, - e_maxsd, - e_maxss, - e_mfence, - e_minpd, - e_minps, - e_minsd, - e_minss, - e_mmxud, - e_mov, - e_movbe, - e_movsl, - e_movabs, - e_movapd, - e_movaps, - e_movd, - e_movddup, - e_movdq2q, - e_movdqa, - e_movdqu, - e_movhpd, - e_movhps, - e_movhps_movlhps, - e_movlpd, - e_movlps, - e_movlps_movhlps, - e_movmskpd, - e_movmskps, - e_movntdq, - e_movntdqa, // SSE 4.1 - e_movnti, - e_movntpd, - e_movntps, - e_movntq, - e_movntsd, - e_movntss, - e_movq, - e_movq2dq, - e_movsb, - e_movsd, - e_movsd_sse, - e_movshdup, - e_movsldup, - e_movss, - e_movsw, - e_movsx, - e_movsxd, - e_movupd, - e_movups, - e_movzx, - e_mpsadbw, // SSE 4.1 - e_mul, - e_mulpd, - e_mulps, - e_mulsd, - e_mulss, - e_neg, - e_nop, - e_not, - e_or, - e_orpd, - e_orps, - e_out, - e_outsb, - e_outsd, - e_outsw, - e_pabsb, // SSSE3 - e_pabsd, // SSSE3 - e_pabsw, // SSSE3 - e_packssdw, - e_packsswb, - e_packusdw, // SSE 4.1 - e_packuswb, - e_paddb, - e_paddd, - e_paddq, - e_paddsb, - e_paddsw, - e_paddusb, - e_paddusw, - e_paddw, - e_palignr, // SSSE3 - e_pand, - e_pandn, - e_pavgb, - e_pavgw, - e_pblendvb, // SSE 4.1 - e_pblendw, // SSE 4.1 - e_pcmpeqb, - e_pcmpeqd, - e_pcmpeqq, // SSE 4.1 - e_pcmpeqw, - e_pcmpestri, // SSE 4.2 - e_pcmpestrm, // SSE 4.2 - e_pcmpgdt, - e_pcmpgtb, - e_pcmpgtq, // SSE 4.2 - e_pcmpgtw, - e_pcmpistri, // SSE 4.2 - e_pcmpistrm, // SSE 4.2 - e_pextrb, // SSE 4.1 - e_pextrd_pextrq, // SSE 4.1 - e_pextrw, // SSE 4.1 - e_phaddd, // SSSE3 - e_phaddw, // SSSE3 - e_phaddsw, // SSSE3 - e_phminposuw, // SSE 4.1 - e_phsubd, // SSSE3 - e_phsubw, // SSSE3 - e_phsubsw, // SSSE3 - e_pinsrb, // SSE 4.1 - e_pinsrd_pinsrq, // SSE 4.1 - e_pinsrw, - e_pmaddwd, - e_pmaddubsw, // SSSE3 - e_pmaxsb, // SSE 4.1 - e_pmaxsd, // SSE 4.1 - e_pmaxud, // SSE 4.1 - e_pmaxuw, // SSE 4.1 - e_pmaxsw, - e_pmaxub, - e_pminsb, // SSE 4.1 - e_pminsd, // SSE 4.1 - e_pminud, // SSE 4.1 - e_pminuw, // SSE 4.1 - e_pminsw, - e_pminub, - e_pmovmskb, - e_pmovntdqa, // SSE 4.1 - e_pmovsxbd, // SSE 4.1 - e_pmovsxbq, // SSE 4.1 - e_pmovsxbw, // SSE 4.1 - e_pmovsxwd, // SSE 4.1 - e_pmovsxwq, // SSE 4.1 - e_pmovsxdq, // SSE 4.1 - e_pmovzxbd, // SSE 4.1 - e_pmovzxbq, // SSE 4.1 - e_pmovzxbw, // SSE 4.1 - e_pmovzxwd, // SSE 4.1 - e_pmovzxwq, // SSE 4.1 - e_pmovzxdq, // SSE 4.1 - e_pmuldq, // SSE 4.1 - e_pmulhrsw, // SSSE3 - e_pmulhuw, - e_pmulhw, - e_pmulld, // SSE 4.1 - e_pmullw, - e_pmuludq, - e_pop, - e_popa, - e_popad, - e_popf, - e_popfq, - e_popfd, - e_popcnt, - e_por, - e_psadbw, - e_pshufb, // SSSE3 - e_pshufd, - e_pshufhw, - e_pshuflw, - e_pshufw, - e_psignd, // SSSE3 - e_psignw, // SSSE3 - e_psignb, // SSSE3 - e_pslld, - e_pslldq, - e_psllq, - e_psllw, - e_psrad, - e_psraw, - e_psrld, - e_psrldq, - e_psrlq, - e_psrlw, - e_psubb, - e_psubd, - e_psubsb, - e_psubsw, - e_psubusb, - e_psubusw, - e_psubw, - e_ptest, // SSE 4.1 - e_punpckhbw, - e_punpckhdq, - e_punpckhqd, - e_punpckhwd, - e_punpcklbw, - e_punpcklqd, - e_punpcklqld, - e_punpcklwd, - e_push, - e_pusha, - e_pushad, - e_pushf, - e_pushfd, - e_pxor, - e_rcl, - e_rcpps, - e_rcpss, - e_rcr, - e_rdmsr, - e_rdpmc, - e_rdtsc, - e_rdrand, - e_rol, - e_rolb, - e_ror, - e_roundpd, // SSE 4.1 - e_roundps, // SSE 4.1 - e_roundsd, // SSE 4.1 - e_roundss, // SSE 4.1 - e_rsm, - e_rsqrtps, - e_rsqrtss, - e_sahf, - e_salc, - e_sar, - e_sarb, - e_sbb, - e_sbbl, - e_scas, - e_scasb, - e_scasd, - e_scasw, - e_setb, - e_setbe, - e_setl, - e_setle, - e_setnb, - e_setnbe, - e_setnl, - e_setnle, - e_setno, - e_setnp, - e_setns, - e_setnz, - e_seto, - e_setp, - e_sets, - e_setz, - e_sfence, - e_sgdt, - e_shl_sal, - e_shld, - e_shr, - e_shrb, - e_shrd, - e_shufpd, - e_shufps, - e_sha1rnds4, - e_sha1nexte, - e_sha1msg1, - e_sha1msg2, - e_sha256rnds2, - e_sha256msg1, - e_sha256msg2, - e_prefetchwt1, - e_clflushopt, - e_clwb, - e_pcommit, - e_sidt, - e_sldt, - e_smsw, - e_sqrtpd, - e_sqrtps, - e_sqrtsd, - e_sqrtss, - e_stc, - e_std, - e_sti, - e_stmxcsr, - e_stos, - e_stosb, - e_stosd, - e_stosw, - e_str, - e_sub, - e_subpd, - e_subps, - e_subsd, - e_subss, - e_syscall, - e_sysenter, - e_sysexit, - e_sysret, - e_test, - e_ucomisd, - e_ucomiss, - e_ud, - e_ud2, - e_ud2grp10, - e_unpckhpd, - e_unpckhps, - e_unpcklpd, - e_unpcklps, - e_verr, - e_verw, - - e_vaddpd, - e_vaddps, - e_vaddsd, - e_vaddss, - e_vandnpd, - e_vandnps, - e_vandpd, - e_vandps, - e_valignd, - e_valignq, - e_vbroadcastf128, - e_vbroadcasti128, - e_vbroadcastsd, - e_vbroadcastss, - e_vblendmps, - e_vblendmpd, - e_vblendps, - e_vblendvps, - e_vblendvpd, - e_vpblendmw, - e_vpblendmd, - e_vpblendmb, - e_vpblendvb, - e_vcmppd, - e_vcmpps, - e_vcmpsd, - e_vcmpss, - e_vcomisd, - e_vcomiss, - e_vexpandpd, - e_vexpandps, - e_vexp2pd, - e_vexp2ps, - e_vroundpd, - e_vroundps, - e_vroundsd, - e_vroundss, - e_vrcp28pd, - e_vrcp28sd, - e_vrcp28ps, - e_vrcp28ss, - e_vrsqrt28pd, - e_vrsqrt28sd, - e_vrsqrt28ps, - e_vrsqrt28ss, - e_vcvtudq2pd, - e_vcvtudq2ps, - e_vcvtpd2qq, - e_vcvtdq2pd, - e_vcvtdq2ps, - e_vcvtpd2dq, - e_vcvtpd2ps, - e_vcvtph2ps, - e_vcvtps2dq, - e_vcvtps2pd, - e_vcvtps2ph, - e_vcvtsd2si, - e_vcvtsd2ss, - e_vcvtsi2sd, - e_vcvtsi2ss, - e_vcvtss2sd, - e_vcvtss2si, - e_vcvttpd2udq, - e_vcvttpd2uqq, - e_vcvttpd2qq, - e_vcvttpd2dq, - e_vcvttps2dq, - e_vcvttsd2si, - e_vcvttss2si, - e_vcvtpd2udq, - e_vcvtpd2uqq, - e_vcvtps2uqq, - e_vdivpd, - e_vdivps, - e_vdivsd, - e_vdivss, - e_vextractf128, - e_vextracti128, - e_vextractf32x4, - e_vextractf64x2, - e_vextractf32x8, - e_vextractf64x4, - e_vextracti32x4, - e_vextracti64x2, - e_vextracti32x8, - e_vextracti64x4, - e_vextractps, - e_vfixupimmpd, - e_vfixupimmps, - e_vfixupimmsd, - e_vfixupimmss, - e_vfmaddpd, - e_vfmaddps, - e_vfmaddsd, - e_vfmaddss, - e_vfmadd132pd, - e_vfmadd132ps, - e_vfmadd132sd, - e_vfmadd132ss, - e_vfmadd213pd, - e_vfmadd213ps, - e_vfmadd213sd, - e_vfmadd213ss, - e_vfmadd231pd, - e_vfmadd231ps, - e_vfmadd231sd, - e_vfmadd231ss, - e_vfmaddsub132pd, - e_vfmaddsub132ps, - e_vfmaddsub213pd, - e_vfmaddsub213ps, - e_vfmaddsub231pd, - e_vfmaddsub231ps, - e_vfmsubpd, - e_vfmsubsd, - e_vfmsub132pd, - e_vfmsub132ps, - e_vfmsub132sd, - e_vfmsub132ss, - e_vfmsub213pd, - e_vfmsub213ps, - e_vfmsub213sd, - e_vfmsub213ss, - e_vfmsub231pd, - e_vfmsub231ps, - e_vfmsub231sd, - e_vfmsub231ss, - e_vfmsubadd132pd, - e_vfmsubadd132ps, - e_vfmsubadd213pd, - e_vfmsubadd213ps, - e_vfmsubadd231pd, - e_vfmsubadd231ps, - e_vfnmaddpd, - e_vfnmaddsd, - e_vfnmadd132pd, - e_vfnmadd132ps, - e_vfnmadd132sd, - e_vfnmadd132ss, - e_vfnmadd213pd, - e_vfnmadd213ps, - e_vfnmadd213sd, - e_vfnmadd213ss, - e_vfnmadd231pd, - e_vfnmadd231ps, - e_vfnmadd231sd, - e_vfnmadd231ss, - e_vfnmsub132pd, - e_vfnmsub132ps, - e_vfnmsub132sd, - e_vfnmsub132ss, - e_vfnmsub213pd, - e_vfnmsub213ps, - e_vfnmsub213sd, - e_vfnmsub213ss, - e_vfnmsub231pd, - e_vfnmsub231ps, - e_vfnmsub231sd, - e_vfnmsub231ss, - e_vfpclassps, - e_vfpclasspd, - e_vfpclasssd, - e_vfpclassss, - e_vgatherpf0qps, - e_vgatherpf0dps, - e_vgatherpf0dpd, - e_vgatherpf1qps, - e_vgatherpf1dpd, - e_vscatterpf0dps, - e_vscatterpf0qpd, - e_vscatterpf1qps, - e_vscatterpf1qpd, - e_vgatherdpd, - e_vgatherdps, - e_vgatherqpd, - e_vgatherqps, - e_vgetexpps, - e_vgetexppd, - e_vgetexpsd, - e_vgetexpss, - e_vgetmantps, - e_vgetmantpd, - e_vgetmantss, - e_vgetmantsd, - e_vinsertf128, - e_vinserti128, - e_vinsertps, - e_vinsertf32x4, - e_vinsertf64x2, - e_vinsertf32x8, - e_vinsertf64x4, - e_vinserti32x4, - e_vinserti64x2, - e_vinserti32x8, - e_vinserti64x4, - e_vmaskmovpd, - e_vmaskmovps, - e_vmaxpd, - e_vmaxps, - e_vmaxsd, - e_vmaxss, - e_vminpd, - e_vminps, - e_vminsd, - e_vminss, - e_vmovapd, - e_vmovaps, - e_vmovddup, - e_vmovdqa, - e_vmovdqa32, - e_vmovdqa64, - e_vmovdqu32, - e_vmovdqu64, - e_vmovdqu8, - e_vmovdqu16, - e_vmovdqu, - e_vmovhlps, - e_vmovhpd, - e_vmovhps, - e_vmovlhps, - e_vmovlpd, - e_vmovlps, - e_vmovntps, - e_vmovq, - e_vmovsd, - e_vmovshdup, - e_vmovsldup, - e_movslq, - e_vmovss, - e_vmovupd, - e_vmovups, - e_vmulpd, - e_vmulps, - e_vmulsd, - e_vmulss, - e_vorpd, - e_vorps, - e_vpabsb, - e_vpabsd, - e_vpabsw, - e_vpackssdw, - e_vpacksswb, - e_vpackusdw, - e_vpackuswb, - e_vpaddb, - e_vpaddd, - e_vpaddq, - e_vpaddsb, - e_vpaddsw, - e_vpaddusb, - e_vpaddusw, - e_vpaddw, - e_vpalignr, - e_vpand, - e_vpandn, - e_vpandd, - e_vpandq, - e_vpandnd, - e_vpandnq, - e_vpavgb, - e_vpavgw, - e_vpblendd, - e_vpbroadcastb, - e_vpbroadcastd, - e_vpbroadcastq, - e_vpbroadcastw, - e_vpcmpeqd, - e_vpcmpequd, - e_vpcmpub, - e_vpcmpb, - e_vpcmpeqb, - e_vpcmpeqq, - e_vpcmpeqw, - e_vpcmpgtb, - e_vpcmpgtd, - e_vpcmpgtq, - e_vpcmpgtw, - e_vpcomd, - e_vpcompressd, - e_vpcompressq, - e_vpconflictd, - e_vpconflictq, - e_vperm2f128, - e_vperm2i128, - e_vpermd, - e_vpermi2b, - e_vpermi2w, - e_vpermi2d, - e_vpermi2q, - e_vpermi2ps, - e_vpermi2pd, - e_vpermt2b, - e_vpermt2w, - e_vpermt2d, - e_vpermt2q, - e_vpermt2ps, - e_vpermt2pd, - e_vpermb, - e_vpermw, - e_vpermilpd, - e_vpermilps, - e_vpermpd, - e_vpermps, - e_vpermq, - e_vpexpandd, - e_vpexpandq, - e_vplzcntd, - e_vplzcntq, - e_vpextrb, - e_vpextrd, - e_vpextrq, - e_vpextrw, - e_vpgatherdd, - e_vpgatherdq, - e_vpgatherqd, - e_vpgatherqq, - e_vpinsrb, - e_vpinsrd, - e_vpinsrq, - e_vpinsrw, - e_vpmovb2m, - e_vpmacsdd, - e_vpmaddubsw, - e_vpmaddwd, - e_vpmaskmovd, - e_vpmaskmovq, - e_vpmaxsb, - e_vpmaxsd, - e_vpmaxsw, - e_vpmaxub, - e_vpmaxud, - e_vpmaxuw, - e_vpmaxsq, - e_vpmaxuq, - e_vpminsb, - e_vpminsd, - e_vpminsw, - e_vpminub, - e_vpminud, - e_vpminuw, - e_vpminsq, - e_vpminuq, - e_vpmovm2d, - e_vpmovm2b, - e_vpmovsdb, - e_vpmovsdw, - e_vpmovsqb, - e_vpmovsqd, - e_vpmovsqw, - e_vpmovswb, - e_vpmovsxbd, - e_vpmovsxbq, - e_vpmovsxbw, - e_vpmovsxdq, - e_vpmovsxwd, - e_vpmovsxwq, - e_vpmovzxbd, - e_vpmovzxbq, - e_vpmovzxbw, - e_vpmovzxdq, - e_vpmovzxwd, - e_vpmovzxwq, - e_vpmuldq, - e_vpmulhrsw, - e_vpmulhuw, - e_vpmulhw, - e_vpmulld, - e_vpmullw, - e_vpmuludq, - e_vpor, - e_vpord, - e_vporq, - e_vprolvd, - e_vprolvq, - e_vprold, - e_vprolq, - e_vprorvd, - e_vprorvq, - e_vprord, - e_vprorq, - e_vpscatterdd, - e_vpscatterdq, - e_vpscatterqd, - e_vpscatterqq, - e_vpsadbw, - e_vpshufb, - e_vpshufd, - e_vpshufhw, - e_vpshuflw, - e_vpslld, - e_vpslldq, - e_vpsllq, - e_vpsllvd, - e_vpsllvq, - e_vpsllw, - e_vpsrad, - e_vpsravd, - e_vpsraw, - e_vpsrld, - e_vpsrldq, - e_vpsrlq, - e_vpsrlvd, - e_vpsrlvq, - e_vpsrlw, - e_vpsubb, - e_vpsubd, - e_vpsubq, - e_vpsubsb, - e_vpsubsw, - e_vpsubusb, - e_vpsubusw, - e_vpsubw, - e_vpunpckhbw, - e_vpunpckhdq, - e_vpunpckhqdq, - e_vpunpckhwd, - e_vpunpcklbw, - e_vpunpckldq, - e_vpunpcklqdq, - e_vpunpcklwd, - e_vpxor, - e_vshufpd, - e_vshufps, - e_vshuff32x4, - e_vshuff64x2, - e_vsqrtpd, - e_vsqrtps, - e_vsqrtsd, - e_vsqrtss, - e_vsubpd, - e_vsubps, - e_vsubsd, - e_vsubss, - e_vtestpd, - e_vtestps, - e_vucomisd, - e_vucomiss, - e_vunpckhpd, - e_vunpckhps, - e_vunpcklpd, - e_vunpcklps, - e_vxorpd, - e_vxorps, - e_vzeroall, - e_vzeroupper, - e_vmovntpd, - e_vcvttsd2usi, - e_vcvttss2usi, - e_vcvtsd2usi, - e_vcvtss2usi, - e_vcvtusi2sd, - e_vcvtusi2ss, - e_vmovntdq, - e_vpxord, - e_vpxorq, - e_vrangeps, - e_vrangepd, - e_vrangess, - e_vrangesd, - e_vrcp14ps, - e_vrcp14pd, - e_vrcp14ss, - e_vrcp14sd, - e_vreduceps, - e_vreducepd, - e_vreducess, - e_vreducesd, - e_vpcmov, - e_vpshad, - e_vpsrlvw, - e_vpmovuswb, - e_vpsravw, - e_vpsravq, - e_vpmovusdb, - e_vpsllvw, - e_vscatterdps, - e_vscatterdpd, - e_vscatterqps, - e_vscatterqpd, - e_vrsqrt14ps, - e_vrsqrt14pd, - e_vrsqrt14ss, - e_vrsqrt14sd, - e_vpmovusqb, - e_vpmovusdw, - e_vpmovusqw, - e_vpmovusqd, - e_vbroadcastf32x4, - e_vpabsq, - e_vmovntdqa, - e_vpbroadcastmb2q, - e_vpmovwb, - e_vpmovdb, - e_vpmovqb, - e_vpmovdw, - e_vpmovqw, - e_vpmovqd, - e_vpmultishiftqb, - e_vpmadd52luq, - e_vpmadd52huq, - e_vptestmd, - e_vptestnmd, - e_vptestnmb, - e_vpternlogd, - e_vpternlogq, - e_vrndscaleps, - e_vrndscalepd, - e_vrndscaless, - e_vrndscalesd, - e_vdbpsadbw, - e_vmpsadbw, - e_vphaddw, - e_vphaddd, - e_vphaddsw, - e_vphsubw, - e_vphsubd, - e_vphsubsw, - e_vpmovmskb, - e_andn, - e_bextr, - e_blsi, - e_blsmsk, - e_blsr, - e_bzhi, - e_lzcnt, - e_mulx, - e_pdep, - e_pext, - e_rorx, - e_shlx, - e_shrx, - e_sarx, - e_tzcnt, - - e_vcvtsi2sdl, - e_vcvtsi2ssl, - e_kandb, - e_kandd, - e_kandw, - e_kandq, - e_kandnb, - e_kandnd, - e_kandnw, - e_kandnq, - e_knotb, - e_knotd, - e_knotw, - e_knotq, - e_korb, - e_kord, - e_korw, - e_korq, - e_kxnorb, - e_kxnord, - e_kxnorw, - e_kxnorq, - e_kxorb, - e_kxord, - e_kxorw, - e_kxorq, - e_kaddb, - e_kaddd, - e_kaddw, - e_kaddq, - e_kshiftlw, - e_kshiftlb, - e_kshiftlq, - e_kshiftld, - e_kshiftrw, - e_kshiftrb, - e_kshiftrq, - e_kshiftrd, - e_kunpckbw, - e_kunpckwd, - e_kunpckdq, - e_kmovb, - e_kmovd, - e_kmovw, - e_kmovq, - e_kortestd, - e_ktestb, - e_ktestd, - e_ktestw, - e_ktestq, - e_vcmpeqpd, - e_vcmpeqsd, - e_vcmpeqss, - e_vcmpeqps, - e_kortestb, - e_kortestw, - e_kortestq, - - e_vmread, - e_vmwrite, - e_vsyscall, - e_wait, - e_wbinvd, - e_wrmsr, - e_xadd, - e_xchg, - e_xlat, - e_xor, - e_xorpd, - e_xorps, - e_fp_generic, - e_3dnow_generic, - e_getsec, - - power_op_INVALID, - power_op_extended, - power_op_stfdu, - power_op_fadd, - power_op_xoris, - power_op_mulhwu, - power_op_stbux, - power_op_cmpl, - power_op_subf, - power_op_svcs, - power_op_fmuls, - power_op_subfic, - power_op_mcrfs, - power_op_divs, - power_op_lwzx, - power_op_fctiw, - power_op_mtcrf, - power_op_srq, - power_op_sraw, - power_op_lfdx, - power_op_stdcx_rc, - power_op_nor, - power_op_crandc, - power_op_stdu, - power_op_addme, - power_op_fmul, - power_op_sthbrx, - power_op_mtspr, - power_op_lfsx, - power_op_lbzx, - power_op_nand, - power_op_fnmadds, - power_op_fnmadd, - power_op_mulhw, - power_op_sradi, - power_op_fnmsubs, - power_op_addze, - power_op_mulld, - power_op_addic, - power_op_lfs, - power_op_andc, - power_op_eciwx, - power_op_rfid, - power_op_divw, - power_op_creqv, - power_op_fctiwz, - power_op_crnor, - power_op_lbzux, - power_op_td, - power_op_dcbi, - power_op_cli, - power_op_div, - power_op_add, - power_op_extsh, - power_op_divd, - power_op_fmsub, - power_op_stbx, - power_op_nabs, - power_op_isync, - power_op_mfsri, - power_op_stfdx, - power_op_fsqrt, - power_op_dcbz, - power_op_dcbst, - power_op_stswi, - power_op_mulli, - power_op_stfs, - power_op_clf, - power_op_fnmsub, - power_op_lhz, - power_op_ecowx, - power_op_fres, - power_op_stwu, - power_op_lhau, - power_op_slq, - power_op_srawi, - power_op_divwu, - power_op_addis, - power_op_mfmsr, - power_op_mulhd, - power_op_fdivs, - power_op_abs, - power_op_lwzu, - power_op_tlbli, - power_op_orc, - power_op_mtfsf, - power_op_lswx, - power_op_stb, - power_op_andis_rc, - power_op_fsel, - power_op_xori, - power_op_lwax, - power_op_tdi, - power_op_rlwimi, - power_op_stw, - power_op_rldcr, - power_op_sraq, - power_op_fmr, - power_op_tlbld, - power_op_doz, - power_op_lbz, - power_op_stdux, - power_op_mtfsfi, - power_op_srea, - power_op_lscbx, - power_op_rlwinm, - power_op_sld, - power_op_addc, - power_op_lfqux, - power_op_sleq, - power_op_extsb, - power_op_ld, - power_op_ldu, - power_op_fctidz, - power_op_lfq, - power_op_lwbrx, - power_op_fsqrts, - power_op_srd, - power_op_lfdu, - power_op_stfsux, - power_op_lhzu, - power_op_crnand, - power_op_icbi, - power_op_rlwnm, - power_op_rldcl, - power_op_stwcx_rc, - power_op_lhzx, - power_op_stfsx, - power_op_rlmi, - power_op_twi, - power_op_srliq, - power_op_tlbie, - power_op_mfcr, - power_op_tlbsync, - power_op_extsw, - power_op_rldicl, - power_op_bclr, - power_op_rfsvc, - power_op_mcrxr, - power_op_clcs, - power_op_srad, - power_op_subfc, - power_op_mfsrin, - power_op_rfi, - power_op_sreq, - power_op_frsqrte, - power_op_lwz, - power_op_lfqu, - power_op_and, - power_op_stswx, - power_op_stfd, - power_op_fmsubs, - power_op_bcctr, - power_op_lhaux, - power_op_ldux, - power_op_fctid, - power_op_frsp, - power_op_slw, - power_op_cmpli, - power_op_sync, - power_op_cntlzw, - power_op_maskg, - power_op_divdu, - power_op_xor, - power_op_fadds, - power_op_fneg, - power_op_lwaux, - power_op_fsub, - power_op_stfqux, - power_op_srlq, - power_op_lfqx, - power_op_dcbt, - power_op_sliq, - power_op_fcmpo, - power_op_lhax, - power_op_cror, - power_op_dozi, - power_op_crand, - power_op_stfsu, - power_op_lha, - power_op_mcrf, - power_op_fdiv, - power_op_ori, - power_op_fmadd, - power_op_stmw, - power_op_lwarx, - power_op_sle, - power_op_fsubs, - power_op_stdx, - power_op_stwx, - power_op_sthux, - power_op_stwbrx, - power_op_sthu, - power_op_dclst, - power_op_fcmpu, - power_op_subfme, - power_op_stfiwx, - power_op_mul, - power_op_bc, - power_op_stwux, - power_op_sllq, - power_op_mullw, - power_op_cmpi, - power_op_rldicr, - power_op_sth, - power_op_sre, - power_op_slliq, - power_op_rldic, - power_op_fnabs, - power_op_sc, - power_op_addic_rc, - power_op_rldimi, - power_op_stfqu, - power_op_neg, - power_op_oris, - power_op_lfsux, - power_op_mtfsb1, - power_op_dcbtst, - power_op_subfe, - power_op_b, - power_op_lwzux, - power_op_rac, - power_op_lfdux, - power_op_lbzu, - power_op_lhzux, - power_op_lhbrx, - power_op_lfsu, - power_op_srw, - power_op_crxor, - power_op_stfdux, - power_op_lmw, - power_op_adde, - power_op_mfsr, - power_op_sraiq, - power_op_rrib, - power_op_addi, - power_op_sthx, - power_op_stfqx, - power_op_andi_rc, - power_op_or, - power_op_dcbf, - power_op_fcfid, - power_op_fmadds, - power_op_mtfsb0, - power_op_lswi, - power_op_mulhdu, - power_op_ldarx, - power_op_eieio, - power_op_cntlzd, - power_op_subfze, - power_op_fabs, - power_op_tw, - power_op_eqv, - power_op_stfq, - power_op_maskir, - power_op_sriq, - power_op_mfspr, - power_op_ldx, - power_op_crorc, - power_op_lfd, - power_op_cmp, - power_op_stbu, - power_op_stfpdux, - power_op_stfpdx, - power_op_stfpsux, - power_op_stfpsx, - power_op_stfxdux, - power_op_stfxdx, - power_op_stfxsux, - power_op_stfxsx, - power_op_stfsdux, - power_op_stfsdx, - power_op_stfssux, - power_op_stfssx, - power_op_stfpiwx, - power_op_lfpdux, - power_op_lfpdx, - power_op_lfpsux, - power_op_lfpsx, - power_op_lfxdux, - power_op_lfxdx, - power_op_lfxsux, - power_op_lfxsx, - power_op_lfsdux, - power_op_lfsdx, - power_op_lfssux, - power_op_lfssx, - power_op_qvfcfids, - power_op_qvlfsx, - power_op_qvlfsux, - power_op_qvlfcsx, - power_op_qvlfcsux, - power_op_qvlfdx, - power_op_qvlfdux, - power_op_qvlfcdx, - power_op_qvlfcdux, - power_op_qvlfiwax, - power_op_qvlfiwzx, - power_op_qvlpcldx, - power_op_qvlpclsx, - power_op_qvlpcrdx, - power_op_qvlpcrsx, - power_op_qvstfsx, - power_op_qvstfsux, - power_op_qvstfsxi, - power_op_qvstfsuxi, - power_op_qvstfdx, - power_op_qvstfdux, - power_op_qvstfdxi, - power_op_qvstfduxi, - power_op_qvstfcsx, - power_op_qvstfcsux, - power_op_qvstfcsxi, - power_op_qvstfcsuxi, - power_op_qvstfcdx, - power_op_qvstfcdux, - power_op_qvstfcdxi, - power_op_qvstfcduxi, - power_op_qvstfiwx, - power_op_qvfmr, - power_op_qvfcpsgn, - power_op_qvfneg, - power_op_qvfabs, - power_op_qvfnabs, - power_op_qvfadd, - power_op_qvfadds, - power_op_qvfsub, - power_op_qvfsubs, - power_op_qvfmul, - power_op_qvfmuls, - power_op_qvfre, - power_op_qvfres, - power_op_qvfrsqrte, - power_op_qvfrsqrtes, - power_op_qvfmadd, - power_op_qvfmadds, - power_op_qvfmsub, - power_op_qvfmsubs, - power_op_qvfnmadd, - power_op_qvfnmadds, - power_op_qvfnmsub, - power_op_qvfnmsubs, - power_op_qvfxmadd, - power_op_qvfxmadds, - power_op_qvfxxnpmadd, - power_op_qvfxxnpmadds, - power_op_qvfxxmadd, - power_op_qvfxxmadds, - power_op_qvfxxcpnmadd, - power_op_qvfxxcpnmadds, - power_op_qvfxmul, - power_op_qvfxmuls, - power_op_qvfrsp, - power_op_qvfctid, - power_op_qvfctidz, - power_op_qvfctidu, - power_op_qvfctiduz, - power_op_qvfctiw, - power_op_qvfctiwu, - power_op_qvfctiwz, - power_op_qvfctiwuz, - power_op_qvfcfid, - power_op_qvfcfidu, - power_op_qvfcfidus, - power_op_qvfrin, - power_op_qvfriz, - power_op_qvfrip, - power_op_qvfrim, - power_op_qvfcmpgt, - power_op_qvftstnan, - power_op_qvfcmplt, - power_op_qvfcmpeq, - power_op_qvfsel, - power_op_qvfaligni, - power_op_qvfperm, - power_op_qvesplati, - power_op_qvgpci, - power_op_qvflogical, - power_op_qvlstdux, - power_op_qvlstduxi, - power_op_fxcxnms, - power_op_fxcxma, - power_op_fxcxnsma, - power_op_fxcxnpma, - power_op_fxcsnsma, - power_op_fxcpnsma, - power_op_fxcsnpma, - power_op_fxcpnpma, - power_op_fsmtp, - power_op_fsmfp, - power_op_fpctiwz, - power_op_fpctiw, - power_op_fxmr, - power_op_fpsel, - power_op_fpmul, - power_op_fxmul, - power_op_fxpmul, - power_op_fxsmul, - power_op_fpadd, - power_op_fpsub, - power_op_fpre, - power_op_fprsqrte, - power_op_fpmadd, - power_op_fxmadd, - power_op_fxcpmadd, - power_op_fxcsmadd, - power_op_fpnmadd, - power_op_fxnmadd, - power_op_fxcpnmadd, - power_op_fxcsnmadd, - power_op_fpmsub, - power_op_fxmsub, - power_op_fxcpmsub, - power_op_fxcsmsub, - power_op_fpnmsub, - power_op_fxnmsub, - power_op_fxcpnmsub, - power_op_fxcsnmsub, - power_op_fpmr, - power_op_fpabs, - power_op_fpneg, - power_op_fprsp, - power_op_fpnabs, - power_op_fsmr, - power_op_fscmp, - power_op_fsabs, - power_op_fsneg, - power_op_fsnabs, - power_op_lwa, - power_op_popcntb, - power_op_popcntw, - power_op_popcntd, - power_op_wait, - - //Yuhan: started from here - power_op_lxsd, - power_op_lxsdx, - power_op_lxsibzx, - power_op_lxsihzx, - power_op_lxsiwax, - power_op_lxsiwzx, - power_op_lxssp, - power_op_lxsspx, - power_op_lxvb16x, - power_op_lxvd2x, - power_op_lxvl, - power_op_lxvll, - //--skipped: lxv (page 492, new keyword DQ; TX not at the last bit), - //power_op_lxv, - - power_op_lxvx, - power_op_lxvdsx, - power_op_lxvh8x, - power_op_lxvw4x, - power_op_lxvwsx, - //stxsd: page498, included new keyword "VRS", it stands for VSR[VRS+32].dword[0] - power_op_stxsd, - power_op_stxsdx, - power_op_stxsibx, - power_op_stxsihx, - power_op_stxsiwx, - power_op_stxssp, - power_op_stxsspx, - power_op_stvb16x, - power_op_stxvd2x, - power_op_stxvh8x, - power_op_stxvw4x, - //--skipped: stxv (DQ(RA)) - //power_op_stxv, - power_op_stxvl, - power_op_stxvll, - power_op_stxvx, - //ignored the slashes in it - power_op_xsabsdp, - //page512, third level opcode included - power_op_xsabsqp, - - power_op_xsadddp, - power_op_xsaddsp, - //included VRA, VRB (page 520 of manual) - power_op_xsaddqp, - power_op_xscmpexpdp, - power_op_xscmpexpqp, - power_op_xscmpeqdp, - power_op_xscmpgedp, - power_op_xscmpgtdp, - power_op_xscmpodp, - power_op_xscmpoqp, - power_op_xscmpudp, - power_op_xscmpuqp, - power_op_xscpsgndp, - //xscvdphp (page534), third level opcode - power_op_xscvdphp, - power_op_xscvdpqp, - power_op_xscvdpsp, - power_op_xscvdpspn, - power_op_xscvdpsxws, - power_op_xscvdpsxds, - power_op_xscvdpuxds, - power_op_xscvdpuxws, - power_op_xscvhpdp, - power_op_xscvqpdp, - power_op_xscvqpsdz, - power_op_xscvqpswz, - power_op_xscvqpudz, - power_op_xscvqpuwz, - power_op_xscvsdqp, - power_op_xscvspdp, - power_op_xscvspdpn, - power_op_xscvsxddp, - power_op_xscvsxdsp, - - power_op_xscvudqp, - power_op_xscvuxddp, - power_op_xscvuxdsp, - power_op_xsdivdp, - power_op_xsdivsp, - power_op_xsiexpdp, - power_op_xsiexpqp, - power_op_xsmaddadp, - power_op_xsmaddmdp, - power_op_xsmaddasp, - power_op_xsmaddmsp, - power_op_xsmaddqp, - power_op_xsmaxdp, - power_op_xsmaxcdp, - power_op_xsmaxjdp, - power_op_xsmindp, - power_op_xsmincdp, - power_op_xsminjdp, - power_op_xsmsubadp, - power_op_xsmsubmdp, - power_op_xsmsubasp, - power_op_xsmsubmsp, - power_op_xsmsubqp, - power_op_xsmuldp, - power_op_xsmulqp, - power_op_xsmulsp, - power_op_xsnabsdp, - power_op_xsnegdp, - power_op_xsnegqp, - power_op_xsnmaddadp, - power_op_xsnmaddmdp, - power_op_xsnmaddasp, - power_op_xsnmaddmsp, - power_op_xsnmaddqp, - power_op_xsnmsubadp, - power_op_xsnmsubmdp, - power_op_xsnmsubasp, - power_op_xsnmsubmsp, - power_op_xsnmsubqp, - power_op_xsrdpi, - power_op_xsrdpic, - power_op_xsrdpim, - power_op_xsrdpip, - power_op_xsrdpiz, - power_op_xsredp, - power_op_xsresp, - //P634, xsrqpi & xsrqpix sharing the same opcode, differentiated by EX bit - power_op_xsrqpi, - - //P636, included RMC, it always goes along with an R bit at 15th bit. - power_op_xsrqpxp, - power_op_xsrsp, - power_op_xsrsqrtedp, - power_op_xsrsqrtesp, - power_op_xssqrtdp, - power_op_xssqrtqp, - power_op_xssqrtsp, - - power_op_xssubdp, - power_op_xssubqp, - power_op_xssubsp, - power_op_xstdivdp, - power_op_xstsqrtdp, - //P653, included DCMX - power_op_xststdcdp, - power_op_xststdcqp, - power_op_xststdcsp, - power_op_xsxexpdp, - power_op_xsxexpqp, - power_op_xsxsigdp, - power_op_xsxsigqp, - power_op_xvabsdp, - power_op_xvabssp, - power_op_xvadddp, - power_op_xvaddsp, - power_op_xvcmpeqdp, - power_op_xvcmpeqsp, - power_op_xvcmpgedp, - power_op_xvcmpgesp, - power_op_xvcmpgtdp, - power_op_xvcmpgtsp, - power_op_xvcpsgndp, - power_op_xvcpsgnsp, - power_op_xvcvdpsp, - power_op_xvcvdpsxds, - power_op_xvcvdpsxws, - power_op_xvcvdpuxds, - power_op_xvcvdpuxws, - //new third level opcode 60-475 - power_op_xvcvhpsp, - power_op_xvcvspdp, - power_op_xvcvsphp, - power_op_xvcvspsxds, - power_op_xvcvspsxws, - power_op_xvcvspuxds, - power_op_xvcvspuxws, - power_op_xvcvsxddp, - power_op_xvcvsxdsp, - power_op_xvcvsxwdp, - power_op_xvcvsxwsp, - power_op_xvcvuxddp, - power_op_xvcvuxdsp, - power_op_xvcvuxwdp, - power_op_xvcvuxwsp, - power_op_xvdivdp, - power_op_xvdivsp, - power_op_xviexpdp, - power_op_xviexpsp, - power_op_xvmaddadp, - power_op_xvmaddmdp, - power_op_xvmaddasp, - power_op_xvmaddmsp, - power_op_xvmaxdp, - power_op_xvmaxsp, - power_op_xvmindp, - power_op_xvminsp, - power_op_xvmsubadp, - power_op_xvmsubmdp, - power_op_xvmsubasp, - power_op_xvmsubmsp, - power_op_xvmuldp, - power_op_xvmulsp, - power_op_xvnabsdp, - power_op_xvnabssp, - power_op_xvnegdp, - power_op_xvnegsp, - power_op_xvnmaddadp, - power_op_xvnmaddmdp, - power_op_xvnmaddasp, - power_op_xvnmaddmsp, - power_op_xvnmsubadp, - power_op_xvnmsubmdp, - power_op_xvnmsubasp, - power_op_xvnmsubmsp, - power_op_xvrdpi, - power_op_xvrdpic, - power_op_xvrdpim, - power_op_xvrdpip, - power_op_xvrdpiz, - power_op_xvredp, - power_op_xvresp, - power_op_xvrspi, - power_op_xvrspic, - power_op_xvrspim, - power_op_xvrspip, - power_op_xvrspiz, - power_op_xvrsqrtedp, - power_op_xvrsqrtesp, - power_op_xvsqrtdp, - power_op_xvsqrtsp, - power_op_xvsubdp, - power_op_xvsubsp, - power_op_xvtdivdp, - power_op_xvtdivsp, - power_op_xvtsqrtdp, - power_op_xvtsqrtsp, - power_op_xvtstdcdp, - //xvtstdcdp, xvtstdcsp: DCMX is chopped into 3 parts - power_op_xvtstdcsp, - power_op_xvxexpdp, - power_op_xvxexpsp, - power_op_xvxsigdp, - power_op_xvxsigsp, - power_op_xxbrd, - power_op_xxbrh, - power_op_xxbrq, - power_op_xxbrw, - //included: UIM (immediate number), bit 12-15 (P766) - power_op_xxextractuw, - power_op_xxinsertw, - power_op_xxland, - power_op_xxlandc, - power_op_xxleqv, - power_op_xxlnand, - power_op_xxlorc, - power_op_xxlnor, - power_op_xxlor, - power_op_xxlxor, - power_op_xxmrghw, - power_op_xxmrglw, - power_op_xxperm, - power_op_xxpermr, - power_op_xxpermdi, - power_op_xxspltib, - - //power_op_xvdivsp, - //--skipped: xxpermdi (P773), three arbitrary digits - - - //--skipped: xxsel (P773), XX4 form - power_op_xxsel, - - //--skipped: xxsldwi (P774), three arbitrary digits - power_op_xxsldwi, - - //included: UIM (immediate number), bit 14-15 (P774) - power_op_xxspltw, - - - //--------------------------- - //Chapter 6 start from P241 - power_op_lvebx, - power_op_lvehx, - power_op_lvewx, - power_op_lvx, - power_op_lvxl, - power_op_stvebx, - power_op_stvehx, - power_op_stvewx, - power_op_stvx, - power_op_stvxl, - power_op_lvsl, - power_op_lvsr, - power_op_vpkpx, - power_op_vpksdss, - power_op_vpksdus, - power_op_vpkshss, - power_op_vpkshus, - power_op_vpkswss, - power_op_vpkswus, - power_op_vpkudus, - power_op_vpkudum, - power_op_vpkuhum, - power_op_vpkuhus, - power_op_vpkuwus, - power_op_vpkuwum, - power_op_vupkhpx, - power_op_vupklpx, - power_op_vupkhsb, - power_op_vupklsb, - power_op_vupkhsh, - power_op_vupklsh, - power_op_vupkhsw, - power_op_vupklsw, - power_op_vmrghb, - power_op_vmrglb, - power_op_vmrghh, - power_op_vmrglh, - power_op_vmrghw, - power_op_vmrglw, - power_op_vmrgew, - power_op_vmrgow, - power_op_vspltb, - power_op_vspltw, - power_op_vsplth, - power_op_vspltisb, - power_op_vspltish, - power_op_vspltisw, - power_op_vperm, - power_op_vpermr, - power_op_vsel, - power_op_vsldoi, - power_op_vsl, - power_op_vsr, - power_op_vslo, - power_op_vsro, - power_op_vslv, - power_op_vsrv, - power_op_vextractub, - power_op_vextractuh, - power_op_vextractuw, - power_op_vextractd, - power_op_vinsertb, - power_op_vinserth, - power_op_vinsertw, - power_op_vinsertd, - power_op_vaddcuw, - power_op_vaddshs, - power_op_vaddsbs, - power_op_vaddsws, - power_op_vaddudm, - power_op_vaddubm, - power_op_vadduhm, - power_op_vadduwm, - power_op_vaddubs, - power_op_vadduws, - power_op_vadduhs, - power_op_vadduqm, - power_op_vaddcuq, - power_op_vaddeuqm, - power_op_vaddecuq, - power_op_vsubcuw, - power_op_vsubshs, - power_op_vsubsbs, - power_op_vsubsws, - power_op_vsububm, - power_op_vsubuhm, - power_op_vsubudm, - power_op_vsubuwm, - power_op_vsububs, - power_op_vsubuws, - power_op_vsubuhs, - power_op_vsubuqm, - power_op_vsubcuq, - power_op_vsubeuqm, - power_op_vsubecuq, - power_op_vmulesb, - power_op_vmulosb, - power_op_vmuleub, - power_op_vmuloub, - power_op_vmulesh, - power_op_vmulosh, - power_op_vmuleuh, - power_op_vmulouh, - power_op_vmulesw, - power_op_vmulosw, - power_op_vmuleuw, - power_op_vmulouw, - power_op_vmuluwm, - power_op_vmhaddshs, - power_op_vmhraddshs, - power_op_vmladduhm, - power_op_vmsumubm, - power_op_vmsummbm, - power_op_vmsumshm, - power_op_vmsumshs, - power_op_vmsumuhm, - power_op_vmsumuhs, - power_op_vmsumudm, - power_op_vsumsws, - power_op_vsum2sws, - power_op_vsum4sbs, - power_op_vsum4shs, - power_op_vsum4ubs, - power_op_vnegw, - power_op_vnegd, - power_op_vextsb2w, - power_op_vextsh2w, - power_op_vextsb2d, - power_op_vextsh2d, - power_op_vextsw2d, - power_op_vavgsb, - power_op_vavgsw, - power_op_vavgsh, - power_op_vavgub, - power_op_vavguh, - power_op_vavguw, - power_op_vabsdub, - power_op_vabsduh, - power_op_vabsduw, - power_op_vmaxsb, - power_op_vmaxub, - power_op_vmaxsd, - power_op_vmaxud, - power_op_vmaxsh, - power_op_vmaxsw, - power_op_vmaxuh, - power_op_vmaxuw, - power_op_vminsb, - power_op_vminsd, - power_op_vminub, - power_op_vminud, - power_op_vminsh, - power_op_vminsw, - power_op_vminuh, - power_op_vminuw, - power_op_vcmpequb, - power_op_vcmpequh, - power_op_vcmpequw, - power_op_vcmpequd, - power_op_vcmpgtsb, - power_op_vcmpgtsd, - power_op_vcmpgtsh, - power_op_vcmpgtsw, - power_op_vcmpgtub, - power_op_vcmpgtud, - power_op_vcmpgtuh, - power_op_vcmpgtuw, - power_op_vcmpneb, - power_op_vcmpnezb, - power_op_vcmpneh, - power_op_vcmpnezh, - power_op_vcmpnew, - power_op_vcmpnezw, - power_op_vand, - power_op_vandc, - power_op_veqv, - power_op_vnand, - power_op_vorc, - power_op_vnor, - power_op_vor, - power_op_vxor, - power_op_vprtybw, - power_op_vprtybd, - power_op_vprtybq, - power_op_vrlb, - power_op_vrlw, - power_op_vrld, - power_op_vslb, - power_op_vslh, - power_op_vslw, - power_op_vsld, - power_op_vsrb, - power_op_vsrh, - power_op_vsrw, - power_op_vsrd, - power_op_vsrab, - power_op_vsrah, - power_op_vsraw, - power_op_vsrad, - power_op_vrlwnm, - power_op_vrlwmi, - power_op_vrldnm, - power_op_vrldmi, - power_op_vaddfp, - power_op_vsubfp, - power_op_vmaddfp, - power_op_vmaxfp, - power_op_vctsxs, - power_op_vctuxs, - power_op_vcfsx, - power_op_vcfux, - power_op_vrfim, - power_op_vrfin, - power_op_vrfip, - power_op_vrfiz, - power_op_vcmpbfp, - power_op_vcmpeqfp, - power_op_vcmpgefp, - power_op_vcmpgtfp, - power_op_vexptefp, - power_op_vlogefp, - power_op_vrefp, - power_op_vrsqrtefp, - power_op_vcipher, - power_op_vcipherlast, - power_op_vncipher, - power_op_vncipherlast, - power_op_vsbox, - power_op_vshasigmad, - power_op_vshasigmaw, - power_op_vpmsumb, - power_op_vpmsumd, - power_op_vpmsumh, - power_op_vpmsumw, - power_op_vpermxor, - power_op_vgbbd, - power_op_vclzb, - power_op_vclzh, - power_op_vclzw, - power_op_vclzd, - power_op_vctzb, - power_op_vctzh, - power_op_vctzw, - power_op_vctzd, - power_op_vclzlsbb, - power_op_vctzlsbb, - power_op_vextublx, - power_op_vextuhlx, - power_op_vextubrx, - power_op_vextuhrx, - power_op_vextuwlx, - power_op_vextuwrx, - power_op_vpopcntb, - power_op_vpopcntd, - power_op_vpopcnth, - power_op_vpopcntw, - power_op_vbpermd, - power_op_vbpermq, - power_op_bcdadd, - power_op_bcdsub, - power_op_bcdcfz, - power_op_bcdcfn, - power_op_bcdctn, - power_op_bcdctz, - power_op_bcdcfsq, - power_op_bcdctsq, - power_op_vmul10uq, - power_op_vmul10cuq, - power_op_vmul10euq, - power_op_vmul10ecuq, - power_op_bcdcpsgn, - power_op_bcdsetsgn, - power_op_bcds, - power_op_bcdus, - power_op_bcdtrunc, - power_op_bcdutrunc, - power_op_mtvscr, - power_op_mfvscr, - power_op_addex, - power_op_mffs, - power_op_mffsce, - power_op_mffscdrn, - power_op_mffscdrni, - power_op_mffscrn, - power_op_mffscrni, - power_op_mffsl, - power_op_vnmsubfp, - power_op_vrlh, - power_op_vminfp, - power_op_bcdsr, - - power_op_dtstsfiq, - power_op_xscpsgnqp, - power_op_xsdivqp, - power_op_fmrgew, - power_op_fmrgow, - power_op_fcfidu, - power_op_fctidu, - power_op_fctiduz, - power_op_fctiwu, - power_op_fctiwuz, - power_op_ftdiv, - power_op_ftsqrt, - power_op_xsnabsqp, - power_op_daddq, - power_op_dcffixq, - power_op_dcmpoq, - power_op_dcmpuq, - power_op_dctfixq, - power_op_dctqpq, - power_op_ddedpdq, - power_op_denbcdq, - power_op_ddivq, - power_op_diexq, - power_op_dmulq, - power_op_dquaiq, - power_op_dquaq, - power_op_drdpq, - power_op_drintnq, - power_op_drintxq, - power_op_drrndq, - power_op_dscliq, - power_op_dscriq, - power_op_dsubq, - power_op_dtstdcq, - power_op_dtstdgq, - power_op_dtstexq, - power_op_dtstsfq, - power_op_dxexq, - power_op_fcpsgn, - power_op_fre, - power_op_frim, - power_op_frin, - power_op_frip, - power_op_friz, - power_op_slbiag, - power_op_cmpeqb, - power_op_cmprb, - power_op_cnttzw, - power_op_cnttzd, - power_op_cp_abort, - power_op_darn, - power_op_extswsl, - power_op_ldat, - power_op_lwat, - power_op_mcrxrx, - power_op_mfvsrld, - power_op_modud, - power_op_modsw, - power_op_moduw, - power_op_msgsnd, - power_op_msgclr, - power_op_msgsndp, - power_op_msgclrp, - power_op_msgsync, - power_op_mtvsrd, - power_op_mtvsrdd, - power_op_mfvsrwz, - power_op_lwzcix, - power_op_mfvsrd, - power_op_mtvsrwa, - power_op_mtvsrwz, - power_op_mtvsrws, - power_op_setb, - power_op_slbieg, - power_op_slbsync, - power_op_stdat, - power_op_stwat, - power_op_clrbhrb, - power_op_mfbhrbe, - power_op_icbt, - power_op_lqarx, - power_op_stqcx, - power_op_tbegin, - power_op_tend, - power_op_tabort, - power_op_tabortwc, - power_op_tabortwci, - power_op_tabortdc, - power_op_tabortdci, - power_op_tsr, - power_op_tcheck, - power_op_treclaim, - power_op_trechkpt, - power_op_addg6s, - power_op_cdtbcd, - power_op_cbcdtd, - power_op_divde, - power_op_divdeu, - power_op_modsd, - power_op_lbarx, - power_op_lharx, - power_op_ldbrx, - power_op_stbcx, - power_op_stdbrx, - power_op_sthcx, - power_op_lbzcix, - power_op_lhzcix, - power_op_ldcix, - power_op_stbcix, - power_op_sthcix, - power_op_stwcix, - power_op_stdcix, - power_op_lfdpx, - power_op_stfdpx, - power_op_prtyd, - power_op_prtyw, - power_op_slbfee, - power_op_slbmfee, - power_op_slbmfev, - power_op_mfocrf, - power_op_isel, - power_op_tlbiel, - power_op_slbmte, - power_op_mtmsrd, - power_op_mtmsr, - power_op_maddhd, - power_op_maddhdu, - power_op_maddld, - power_op_copy, -power_op_paste, -power_op_extswsli, -power_op_stxvb16x, -power_op_bpermd, -power_op_divwe, -power_op_divweu, -power_op_lfiwzx, -power_op_cmpb, -power_op_lfiwax, -power_op_slbia, -power_op_slbie, -power_op_dtstsfi, -power_op_dcffix, -power_op_fcfids, -power_op_fcfidus, -power_op_dadd, -power_op_dcmpo, -power_op_dcmpu, -power_op_dctdp, -power_op_dctfix, -power_op_ddedpd, -power_op_ddiv, -power_op_denbcd, -power_op_diex, -power_op_dmul, -power_op_dquai, -power_op_dqua, -power_op_drintn, -power_op_drintx, -power_op_drrnd, -power_op_drsp, -power_op_dscli, -power_op_dscri, -power_op_dsub, -power_op_dtstdc, -power_op_dtstdg, -power_op_dtstex, -power_op_dtstsf, -power_op_frsqrtes, -power_op_xscvhphp, -power_op_dxex, -/* - power_op_ - power_op_ - power_op_ - power_op_ - power_op_ - power_op_ - power_op_ - power_op_ - power_op_ - power_op_ - power_op_ - power_op_ - power_op_ - power_op_ -*/ - // *********** - // Steve note: - // aarch64 opcode IDs. - // These are generated by the script in instructionAPI dir - // *********** - aarch64_op_INVALID, - aarch64_op_extended, - aarch64_op_abs_advsimd, - aarch64_op_adc, - aarch64_op_adcs, - aarch64_op_add_addsub_ext, - aarch64_op_add_addsub_imm, - aarch64_op_add_addsub_shift, - aarch64_op_add_advsimd, - aarch64_op_addhn_advsimd, - aarch64_op_addp_advsimd_pair, - aarch64_op_addp_advsimd_vec, - aarch64_op_adds_addsub_ext, - aarch64_op_adds_addsub_imm, - aarch64_op_adds_addsub_shift, - aarch64_op_addv_advsimd, - aarch64_op_adr, - aarch64_op_adrp, - aarch64_op_aesd_advsimd, - aarch64_op_aese_advsimd, - aarch64_op_aesimc_advsimd, - aarch64_op_aesmc_advsimd, - aarch64_op_and_advsimd, - aarch64_op_and_log_imm, - aarch64_op_and_log_shift, - aarch64_op_ands_log_imm, - aarch64_op_ands_log_shift, - aarch64_op_asr_asrv, - aarch64_op_asr_sbfm, - aarch64_op_asrv, - aarch64_op_at_sys, - aarch64_op_b_cond, - aarch64_op_b_uncond, - aarch64_op_bfi_bfm, - aarch64_op_bfm, - aarch64_op_bfxil_bfm, - aarch64_op_bic_advsimd_imm, - aarch64_op_bic_advsimd_reg, - aarch64_op_bic_log_shift, - aarch64_op_bics, - aarch64_op_bif_advsimd, - aarch64_op_bit_advsimd, - aarch64_op_bl, - aarch64_op_blr, - aarch64_op_br, - aarch64_op_brk, - aarch64_op_bsl_advsimd, - aarch64_op_cbnz, - aarch64_op_cbz, - aarch64_op_ccmn_imm, - aarch64_op_ccmn_reg, - aarch64_op_ccmp_imm, - aarch64_op_ccmp_reg, - aarch64_op_cinc_csinc, - aarch64_op_cinv_csinv, - aarch64_op_clrex, - aarch64_op_cls_advsimd, - aarch64_op_cls_int, - aarch64_op_clz_advsimd, - aarch64_op_clz_int, - aarch64_op_cmeq_advsimd_reg, - aarch64_op_cmeq_advsimd_zero, - aarch64_op_cmge_advsimd_reg, - aarch64_op_cmge_advsimd_zero, - aarch64_op_cmgt_advsimd_reg, - aarch64_op_cmgt_advsimd_zero, - aarch64_op_cmhi_advsimd, - aarch64_op_cmhs_advsimd, - aarch64_op_cmle_advsimd, - aarch64_op_cmlt_advsimd, - aarch64_op_cmn_adds_addsub_ext, - aarch64_op_cmn_adds_addsub_imm, - aarch64_op_cmn_adds_addsub_shift, - aarch64_op_cmp_subs_addsub_ext, - aarch64_op_cmp_subs_addsub_imm, - aarch64_op_cmp_subs_addsub_shift, - aarch64_op_cmtst_advsimd, - aarch64_op_cneg_csneg, - aarch64_op_cnt_advsimd, - aarch64_op_crc32, - aarch64_op_crc32c, - aarch64_op_csel, - aarch64_op_cset_csinc, - aarch64_op_csetm_csinv, - aarch64_op_csinc, - aarch64_op_csinv, - aarch64_op_csneg, - aarch64_op_dc_sys, - aarch64_op_dcps1, - aarch64_op_dcps2, - aarch64_op_dcps3, - aarch64_op_dmb, - aarch64_op_drps, - aarch64_op_dsb, - aarch64_op_dup_advsimd_elt, - aarch64_op_dup_advsimd_gen, - aarch64_op_eon, - aarch64_op_eor_advsimd, - aarch64_op_eor_log_imm, - aarch64_op_eor_log_shift, - aarch64_op_eret, - aarch64_op_ext_advsimd, - aarch64_op_extr, - aarch64_op_fabd_advsimd, - aarch64_op_fabs_advsimd, - aarch64_op_fabs_float, - aarch64_op_facge_advsimd, - aarch64_op_facgt_advsimd, - aarch64_op_fadd_advsimd, - aarch64_op_fadd_float, - aarch64_op_faddp_advsimd_pair, - aarch64_op_faddp_advsimd_vec, - aarch64_op_fccmp_float, - aarch64_op_fccmpe_float, - aarch64_op_fcmeq_advsimd_reg, - aarch64_op_fcmeq_advsimd_zero, - aarch64_op_fcmge_advsimd_reg, - aarch64_op_fcmge_advsimd_zero, - aarch64_op_fcmgt_advsimd_reg, - aarch64_op_fcmgt_advsimd_zero, - aarch64_op_fcmle_advsimd, - aarch64_op_fcmlt_advsimd, - aarch64_op_fcmp_float, - aarch64_op_fcmpe_float, - aarch64_op_fcsel_float, - aarch64_op_fcvt_float, - aarch64_op_fcvtas_advsimd, - aarch64_op_fcvtas_float, - aarch64_op_fcvtau_advsimd, - aarch64_op_fcvtau_float, - aarch64_op_fcvtl_advsimd, - aarch64_op_fcvtms_advsimd, - aarch64_op_fcvtms_float, - aarch64_op_fcvtmu_advsimd, - aarch64_op_fcvtmu_float, - aarch64_op_fcvtn_advsimd, - aarch64_op_fcvtns_advsimd, - aarch64_op_fcvtns_float, - aarch64_op_fcvtnu_advsimd, - aarch64_op_fcvtnu_float, - aarch64_op_fcvtps_advsimd, - aarch64_op_fcvtps_float, - aarch64_op_fcvtpu_advsimd, - aarch64_op_fcvtpu_float, - aarch64_op_fcvtxn_advsimd, - aarch64_op_fcvtzs_advsimd_fix, - aarch64_op_fcvtzs_advsimd_int, - aarch64_op_fcvtzs_float_fix, - aarch64_op_fcvtzs_float_int, - aarch64_op_fcvtzu_advsimd_fix, - aarch64_op_fcvtzu_advsimd_int, - aarch64_op_fcvtzu_float_fix, - aarch64_op_fcvtzu_float_int, - aarch64_op_fdiv_advsimd, - aarch64_op_fdiv_float, - aarch64_op_fmadd_float, - aarch64_op_fmax_advsimd, - aarch64_op_fmax_float, - aarch64_op_fmaxnm_advsimd, - aarch64_op_fmaxnm_float, - aarch64_op_fmaxnmp_advsimd_pair, - aarch64_op_fmaxnmp_advsimd_vec, - aarch64_op_fmaxnmv_advsimd, - aarch64_op_fmaxp_advsimd_pair, - aarch64_op_fmaxp_advsimd_vec, - aarch64_op_fmaxv_advsimd, - aarch64_op_fmin_advsimd, - aarch64_op_fmin_float, - aarch64_op_fminnm_advsimd, - aarch64_op_fminnm_float, - aarch64_op_fminnmp_advsimd_pair, - aarch64_op_fminnmp_advsimd_vec, - aarch64_op_fminnmv_advsimd, - aarch64_op_fminp_advsimd_pair, - aarch64_op_fminp_advsimd_vec, - aarch64_op_fminv_advsimd, - aarch64_op_fmla_advsimd_elt, - aarch64_op_fmla_advsimd_vec, - aarch64_op_fmls_advsimd_elt, - aarch64_op_fmls_advsimd_vec, - aarch64_op_fmov_advsimd, - aarch64_op_fmov_float, - aarch64_op_fmov_float_gen, - aarch64_op_fmov_float_imm, - aarch64_op_fmsub_float, - aarch64_op_fmul_advsimd_elt, - aarch64_op_fmul_advsimd_vec, - aarch64_op_fmul_float, - aarch64_op_fmulx_advsimd_elt, - aarch64_op_fmulx_advsimd_vec, - aarch64_op_fneg_advsimd, - aarch64_op_fneg_float, - aarch64_op_fnmadd_float, - aarch64_op_fnmsub_float, - aarch64_op_fnmul_float, - aarch64_op_frecpe_advsimd, - aarch64_op_frecps_advsimd, - aarch64_op_frecpx_advsimd, - aarch64_op_frinta_advsimd, - aarch64_op_frinta_float, - aarch64_op_frinti_advsimd, - aarch64_op_frinti_float, - aarch64_op_frintm_advsimd, - aarch64_op_frintm_float, - aarch64_op_frintn_advsimd, - aarch64_op_frintn_float, - aarch64_op_frintp_advsimd, - aarch64_op_frintp_float, - aarch64_op_frintx_advsimd, - aarch64_op_frintx_float, - aarch64_op_frintz_advsimd, - aarch64_op_frintz_float, - aarch64_op_frsqrte_advsimd, - aarch64_op_frsqrts_advsimd, - aarch64_op_fsqrt_advsimd, - aarch64_op_fsqrt_float, - aarch64_op_fsub_advsimd, - aarch64_op_fsub_float, - aarch64_op_hint, - aarch64_op_hlt, - aarch64_op_hvc, - aarch64_op_ic_sys, - aarch64_op_ins_advsimd_elt, - aarch64_op_ins_advsimd_gen, - aarch64_op_isb, - aarch64_op_ld1_advsimd_mult, - aarch64_op_ld1_advsimd_sngl, - aarch64_op_ld1r_advsimd, - aarch64_op_ld2_advsimd_mult, - aarch64_op_ld2_advsimd_sngl, - aarch64_op_ld2r_advsimd, - aarch64_op_ld3_advsimd_mult, - aarch64_op_ld3_advsimd_sngl, - aarch64_op_ld3r_advsimd, - aarch64_op_ld4_advsimd_mult, - aarch64_op_ld4_advsimd_sngl, - aarch64_op_ld4r_advsimd, - aarch64_op_ldar, - aarch64_op_ldarb, - aarch64_op_ldarh, - aarch64_op_ldaxp, - aarch64_op_ldaxr, - aarch64_op_ldaxrb, - aarch64_op_ldaxrh, - aarch64_op_ldnp_fpsimd, - aarch64_op_ldnp_gen, - aarch64_op_ldp_fpsimd, - aarch64_op_ldp_gen, - aarch64_op_ldpsw, - aarch64_op_ldr_imm_fpsimd, - aarch64_op_ldr_imm_gen, - aarch64_op_ldr_lit_fpsimd, - aarch64_op_ldr_lit_gen, - aarch64_op_ldr_reg_fpsimd, - aarch64_op_ldr_reg_gen, - aarch64_op_ldrb_imm, - aarch64_op_ldrb_reg, - aarch64_op_ldrh_imm, - aarch64_op_ldrh_reg, - aarch64_op_ldrsb_imm, - aarch64_op_ldrsb_reg, - aarch64_op_ldrsh_imm, - aarch64_op_ldrsh_reg, - aarch64_op_ldrsw_imm, - aarch64_op_ldrsw_lit, - aarch64_op_ldrsw_reg, - aarch64_op_ldtr, - aarch64_op_ldtrb, - aarch64_op_ldtrh, - aarch64_op_ldtrsb, - aarch64_op_ldtrsh, - aarch64_op_ldtrsw, - aarch64_op_ldur_fpsimd, - aarch64_op_ldur_gen, - aarch64_op_ldurb, - aarch64_op_ldurh, - aarch64_op_ldursb, - aarch64_op_ldursh, - aarch64_op_ldursw, - aarch64_op_ldxp, - aarch64_op_ldxr, - aarch64_op_ldxrb, - aarch64_op_ldxrh, - aarch64_op_lsl_lslv, - aarch64_op_lsl_ubfm, - aarch64_op_lslv, - aarch64_op_lsr_lsrv, - aarch64_op_lsr_ubfm, - aarch64_op_lsrv, - aarch64_op_madd, - aarch64_op_mla_advsimd_elt, - aarch64_op_mla_advsimd_vec, - aarch64_op_mls_advsimd_elt, - aarch64_op_mls_advsimd_vec, - aarch64_op_mneg_msub, - aarch64_op_mov_add_addsub_imm, - aarch64_op_mov_dup_advsimd_elt, - aarch64_op_mov_ins_advsimd_elt, - aarch64_op_mov_ins_advsimd_gen, - aarch64_op_mov_movn, - aarch64_op_mov_movz, - aarch64_op_mov_orr_advsimd_reg, - aarch64_op_mov_orr_log_imm, - aarch64_op_mov_orr_log_shift, - aarch64_op_mov_umov_advsimd, - aarch64_op_movi_advsimd, - aarch64_op_movk, - aarch64_op_movn, - aarch64_op_movz, - aarch64_op_mrs, - aarch64_op_msr_imm, - aarch64_op_msr_reg, - aarch64_op_msub, - aarch64_op_mul_advsimd_elt, - aarch64_op_mul_advsimd_vec, - aarch64_op_mul_madd, - aarch64_op_mvn_not_advsimd, - aarch64_op_mvn_orn_log_shift, - aarch64_op_mvni_advsimd, - aarch64_op_neg_advsimd, - aarch64_op_neg_sub_addsub_shift, - aarch64_op_negs_subs_addsub_shift, - aarch64_op_ngc_sbc, - aarch64_op_ngcs_sbcs, - aarch64_op_nop_hint, - aarch64_op_not_advsimd, - aarch64_op_orn_advsimd, - aarch64_op_orn_log_shift, - aarch64_op_orr_advsimd_imm, - aarch64_op_orr_advsimd_reg, - aarch64_op_orr_log_imm, - aarch64_op_orr_log_shift, - aarch64_op_pmul_advsimd, - aarch64_op_pmull_advsimd, - aarch64_op_prfm_imm, - aarch64_op_prfm_lit, - aarch64_op_prfm_reg, - aarch64_op_prfum, - aarch64_op_raddhn_advsimd, - aarch64_op_rbit_advsimd, - aarch64_op_rbit_int, - aarch64_op_ret, - aarch64_op_rev, - aarch64_op_rev16_advsimd, - aarch64_op_rev16_int, - aarch64_op_rev32_advsimd, - aarch64_op_rev32_int, - aarch64_op_rev64_advsimd, - aarch64_op_ror_extr, - aarch64_op_ror_rorv, - aarch64_op_rorv, - aarch64_op_rshrn_advsimd, - aarch64_op_rsubhn_advsimd, - aarch64_op_saba_advsimd, - aarch64_op_sabal_advsimd, - aarch64_op_sabd_advsimd, - aarch64_op_sabdl_advsimd, - aarch64_op_sadalp_advsimd, - aarch64_op_saddl_advsimd, - aarch64_op_saddlp_advsimd, - aarch64_op_saddlv_advsimd, - aarch64_op_saddw_advsimd, - aarch64_op_sbc, - aarch64_op_sbcs, - aarch64_op_sbfiz_sbfm, - aarch64_op_sbfm, - aarch64_op_sbfx_sbfm, - aarch64_op_scvtf_advsimd_fix, - aarch64_op_scvtf_advsimd_int, - aarch64_op_scvtf_float_fix, - aarch64_op_scvtf_float_int, - aarch64_op_sdiv, - aarch64_op_sev_hint, - aarch64_op_sevl_hint, - aarch64_op_sha1c_advsimd, - aarch64_op_sha1h_advsimd, - aarch64_op_sha1m_advsimd, - aarch64_op_sha1p_advsimd, - aarch64_op_sha1su0_advsimd, - aarch64_op_sha1su1_advsimd, - aarch64_op_sha256h2_advsimd, - aarch64_op_sha256h_advsimd, - aarch64_op_sha256su0_advsimd, - aarch64_op_sha256su1_advsimd, - aarch64_op_shadd_advsimd, - aarch64_op_shl_advsimd, - aarch64_op_shll_advsimd, - aarch64_op_shrn_advsimd, - aarch64_op_shsub_advsimd, - aarch64_op_sli_advsimd, - aarch64_op_smaddl, - aarch64_op_smax_advsimd, - aarch64_op_smaxp_advsimd, - aarch64_op_smaxv_advsimd, - aarch64_op_smc, - aarch64_op_smin_advsimd, - aarch64_op_sminp_advsimd, - aarch64_op_sminv_advsimd, - aarch64_op_smlal_advsimd_elt, - aarch64_op_smlal_advsimd_vec, - aarch64_op_smlsl_advsimd_elt, - aarch64_op_smlsl_advsimd_vec, - aarch64_op_smnegl_smsubl, - aarch64_op_smov_advsimd, - aarch64_op_smsubl, - aarch64_op_smulh, - aarch64_op_smull_advsimd_elt, - aarch64_op_smull_advsimd_vec, - aarch64_op_smull_smaddl, - aarch64_op_sqabs_advsimd, - aarch64_op_sqadd_advsimd, - aarch64_op_sqdmlal_advsimd_elt, - aarch64_op_sqdmlal_advsimd_vec, - aarch64_op_sqdmlsl_advsimd_elt, - aarch64_op_sqdmlsl_advsimd_vec, - aarch64_op_sqdmulh_advsimd_elt, - aarch64_op_sqdmulh_advsimd_vec, - aarch64_op_sqdmull_advsimd_elt, - aarch64_op_sqdmull_advsimd_vec, - aarch64_op_sqneg_advsimd, - aarch64_op_sqrdmulh_advsimd_elt, - aarch64_op_sqrdmulh_advsimd_vec, - aarch64_op_sqrshl_advsimd, - aarch64_op_sqrshrn_advsimd, - aarch64_op_sqrshrun_advsimd, - aarch64_op_sqshl_advsimd_imm, - aarch64_op_sqshl_advsimd_reg, - aarch64_op_sqshlu_advsimd, - aarch64_op_sqshrn_advsimd, - aarch64_op_sqshrun_advsimd, - aarch64_op_sqsub_advsimd, - aarch64_op_sqxtn_advsimd, - aarch64_op_sqxtun_advsimd, - aarch64_op_srhadd_advsimd, - aarch64_op_sri_advsimd, - aarch64_op_srshl_advsimd, - aarch64_op_srshr_advsimd, - aarch64_op_srsra_advsimd, - aarch64_op_sshl_advsimd, - aarch64_op_sshll_advsimd, - aarch64_op_sshr_advsimd, - aarch64_op_ssra_advsimd, - aarch64_op_ssubl_advsimd, - aarch64_op_ssubw_advsimd, - aarch64_op_st1_advsimd_mult, - aarch64_op_st1_advsimd_sngl, - aarch64_op_st2_advsimd_mult, - aarch64_op_st2_advsimd_sngl, - aarch64_op_st3_advsimd_mult, - aarch64_op_st3_advsimd_sngl, - aarch64_op_st4_advsimd_mult, - aarch64_op_st4_advsimd_sngl, - aarch64_op_stlr, - aarch64_op_stlrb, - aarch64_op_stlrh, - aarch64_op_stlxp, - aarch64_op_stlxr, - aarch64_op_stlxrb, - aarch64_op_stlxrh, - aarch64_op_stnp_fpsimd, - aarch64_op_stnp_gen, - aarch64_op_stp_fpsimd, - aarch64_op_stp_gen, - aarch64_op_str_imm_fpsimd, - aarch64_op_str_imm_gen, - aarch64_op_str_reg_fpsimd, - aarch64_op_str_reg_gen, - aarch64_op_strb_imm, - aarch64_op_strb_reg, - aarch64_op_strh_imm, - aarch64_op_strh_reg, - aarch64_op_sttr, - aarch64_op_sttrb, - aarch64_op_sttrh, - aarch64_op_stur_fpsimd, - aarch64_op_stur_gen, - aarch64_op_sturb, - aarch64_op_sturh, - aarch64_op_stxp, - aarch64_op_stxr, - aarch64_op_stxrb, - aarch64_op_stxrh, - aarch64_op_sub_addsub_ext, - aarch64_op_sub_addsub_imm, - aarch64_op_sub_addsub_shift, - aarch64_op_sub_advsimd, - aarch64_op_subhn_advsimd, - aarch64_op_subs_addsub_ext, - aarch64_op_subs_addsub_imm, - aarch64_op_subs_addsub_shift, - aarch64_op_suqadd_advsimd, - aarch64_op_svc, - aarch64_op_sxtb_sbfm, - aarch64_op_sxth_sbfm, - aarch64_op_sxtl_sshll_advsimd, - aarch64_op_sxtw_sbfm, - aarch64_op_sys, - aarch64_op_sysl, - aarch64_op_tbl_advsimd, - aarch64_op_tbnz, - aarch64_op_tbx_advsimd, - aarch64_op_tbz, - aarch64_op_tlbi_sys, - aarch64_op_trn1_advsimd, - aarch64_op_trn2_advsimd, - aarch64_op_tst_ands_log_imm, - aarch64_op_tst_ands_log_shift, - aarch64_op_uaba_advsimd, - aarch64_op_uabal_advsimd, - aarch64_op_uabd_advsimd, - aarch64_op_uabdl_advsimd, - aarch64_op_uadalp_advsimd, - aarch64_op_uaddl_advsimd, - aarch64_op_uaddlp_advsimd, - aarch64_op_uaddlv_advsimd, - aarch64_op_uaddw_advsimd, - aarch64_op_ubfiz_ubfm, - aarch64_op_ubfm, - aarch64_op_ubfx_ubfm, - aarch64_op_ucvtf_advsimd_fix, - aarch64_op_ucvtf_advsimd_int, - aarch64_op_ucvtf_float_fix, - aarch64_op_ucvtf_float_int, - aarch64_op_udiv, - aarch64_op_uhadd_advsimd, - aarch64_op_uhsub_advsimd, - aarch64_op_umaddl, - aarch64_op_umax_advsimd, - aarch64_op_umaxp_advsimd, - aarch64_op_umaxv_advsimd, - aarch64_op_umin_advsimd, - aarch64_op_uminp_advsimd, - aarch64_op_uminv_advsimd, - aarch64_op_umlal_advsimd_elt, - aarch64_op_umlal_advsimd_vec, - aarch64_op_umlsl_advsimd_elt, - aarch64_op_umlsl_advsimd_vec, - aarch64_op_umnegl_umsubl, - aarch64_op_umov_advsimd, - aarch64_op_umsubl, - aarch64_op_umulh, - aarch64_op_umull_advsimd_elt, - aarch64_op_umull_advsimd_vec, - aarch64_op_umull_umaddl, - aarch64_op_uqadd_advsimd, - aarch64_op_uqrshl_advsimd, - aarch64_op_uqrshrn_advsimd, - aarch64_op_uqshl_advsimd_imm, - aarch64_op_uqshl_advsimd_reg, - aarch64_op_uqshrn_advsimd, - aarch64_op_uqsub_advsimd, - aarch64_op_uqxtn_advsimd, - aarch64_op_urecpe_advsimd, - aarch64_op_urhadd_advsimd, - aarch64_op_urshl_advsimd, - aarch64_op_urshr_advsimd, - aarch64_op_ursqrte_advsimd, - aarch64_op_ursra_advsimd, - aarch64_op_ushl_advsimd, - aarch64_op_ushll_advsimd, - aarch64_op_ushr_advsimd, - aarch64_op_usqadd_advsimd, - aarch64_op_usra_advsimd, - aarch64_op_usubl_advsimd, - aarch64_op_usubw_advsimd, - aarch64_op_uxtb_ubfm, - aarch64_op_uxth_ubfm, - aarch64_op_uxtl_ushll_advsimd, - aarch64_op_uzp1_advsimd, - aarch64_op_uzp2_advsimd, - aarch64_op_wfe_hint, - aarch64_op_wfi_hint, - aarch64_op_xtn_advsimd, - aarch64_op_yield_hint, - aarch64_op_zip1_advsimd, - aarch64_op_zip2_advsimd, - amdgpu_op_sop1_nop, -#include "amdgpu_op_table.h" - cuda_op_general, - cuda_op_call, - intel_gpu_op_general, + #include "mnemonics/x86_entryIDs.h" + #include "mnemonics/ppc_entryIDs.h" + #include "mnemonics/aarch64_entryIDs.h" + #include "mnemonics/AMDGPU/gfx908_entryIDs.h" + #include "mnemonics/AMDGPU/gfx90a_entryIDs.h" + #include "mnemonics/AMDGPU/gfx940_entryIDs.h" + #include "mnemonics/NVIDIA/generic_entryIDs.h" + #include "mnemonics/IntelGPU/generic_entryIDs.h" _entry_ids_max_ }; +/* clang-format on */ + enum prefixEntryID : unsigned int { prefix_none, prefix_rep, @@ -3024,4 +60,4 @@ COMMON_EXPORT extern dyn_hash_map entryNames_IAPI; COMMON_EXPORT extern dyn_hash_map prefixEntryNames_IAPI; } -#endif // defined(ENTRYIDS_IA32_H) +#endif diff --git a/common/h/mnemonics/AMDGPU/gfx908_entryIDs.h b/common/h/mnemonics/AMDGPU/gfx908_entryIDs.h new file mode 100644 index 0000000000..2c54592110 --- /dev/null +++ b/common/h/mnemonics/AMDGPU/gfx908_entryIDs.h @@ -0,0 +1,1216 @@ +amdgpu_gfx908_op_BUFFER_ATOMIC_ADD, +amdgpu_gfx908_op_BUFFER_ATOMIC_ADD_F32, +amdgpu_gfx908_op_BUFFER_ATOMIC_ADD_X2, +amdgpu_gfx908_op_BUFFER_ATOMIC_AND, +amdgpu_gfx908_op_BUFFER_ATOMIC_AND_X2, +amdgpu_gfx908_op_BUFFER_ATOMIC_CMPSWAP, +amdgpu_gfx908_op_BUFFER_ATOMIC_CMPSWAP_X2, +amdgpu_gfx908_op_BUFFER_ATOMIC_DEC, +amdgpu_gfx908_op_BUFFER_ATOMIC_DEC_X2, +amdgpu_gfx908_op_BUFFER_ATOMIC_INC, +amdgpu_gfx908_op_BUFFER_ATOMIC_INC_X2, +amdgpu_gfx908_op_BUFFER_ATOMIC_OR, +amdgpu_gfx908_op_BUFFER_ATOMIC_OR_X2, +amdgpu_gfx908_op_BUFFER_ATOMIC_PK_ADD_F16, +amdgpu_gfx908_op_BUFFER_ATOMIC_SMAX, +amdgpu_gfx908_op_BUFFER_ATOMIC_SMAX_X2, +amdgpu_gfx908_op_BUFFER_ATOMIC_SMIN, +amdgpu_gfx908_op_BUFFER_ATOMIC_SMIN_X2, +amdgpu_gfx908_op_BUFFER_ATOMIC_SUB, +amdgpu_gfx908_op_BUFFER_ATOMIC_SUB_X2, +amdgpu_gfx908_op_BUFFER_ATOMIC_SWAP, +amdgpu_gfx908_op_BUFFER_ATOMIC_SWAP_X2, +amdgpu_gfx908_op_BUFFER_ATOMIC_UMAX, +amdgpu_gfx908_op_BUFFER_ATOMIC_UMAX_X2, +amdgpu_gfx908_op_BUFFER_ATOMIC_UMIN, +amdgpu_gfx908_op_BUFFER_ATOMIC_UMIN_X2, +amdgpu_gfx908_op_BUFFER_ATOMIC_XOR, +amdgpu_gfx908_op_BUFFER_ATOMIC_XOR_X2, +amdgpu_gfx908_op_BUFFER_LOAD_DWORD, +amdgpu_gfx908_op_BUFFER_LOAD_DWORDX2, +amdgpu_gfx908_op_BUFFER_LOAD_DWORDX3, +amdgpu_gfx908_op_BUFFER_LOAD_DWORDX4, +amdgpu_gfx908_op_BUFFER_LOAD_FORMAT_D16_HI_X, +amdgpu_gfx908_op_BUFFER_LOAD_FORMAT_D16_X, +amdgpu_gfx908_op_BUFFER_LOAD_FORMAT_D16_XY, +amdgpu_gfx908_op_BUFFER_LOAD_FORMAT_D16_XYZ, +amdgpu_gfx908_op_BUFFER_LOAD_FORMAT_D16_XYZW, +amdgpu_gfx908_op_BUFFER_LOAD_FORMAT_X, +amdgpu_gfx908_op_BUFFER_LOAD_FORMAT_XY, +amdgpu_gfx908_op_BUFFER_LOAD_FORMAT_XYZ, +amdgpu_gfx908_op_BUFFER_LOAD_FORMAT_XYZW, +amdgpu_gfx908_op_BUFFER_LOAD_SBYTE, +amdgpu_gfx908_op_BUFFER_LOAD_SBYTE_D16, +amdgpu_gfx908_op_BUFFER_LOAD_SBYTE_D16_HI, +amdgpu_gfx908_op_BUFFER_LOAD_SHORT_D16, +amdgpu_gfx908_op_BUFFER_LOAD_SHORT_D16_HI, +amdgpu_gfx908_op_BUFFER_LOAD_SSHORT, +amdgpu_gfx908_op_BUFFER_LOAD_UBYTE, +amdgpu_gfx908_op_BUFFER_LOAD_UBYTE_D16, +amdgpu_gfx908_op_BUFFER_LOAD_UBYTE_D16_HI, +amdgpu_gfx908_op_BUFFER_LOAD_USHORT, +amdgpu_gfx908_op_BUFFER_STORE_BYTE, +amdgpu_gfx908_op_BUFFER_STORE_BYTE_D16_HI, +amdgpu_gfx908_op_BUFFER_STORE_DWORD, +amdgpu_gfx908_op_BUFFER_STORE_DWORDX2, +amdgpu_gfx908_op_BUFFER_STORE_DWORDX3, +amdgpu_gfx908_op_BUFFER_STORE_DWORDX4, +amdgpu_gfx908_op_BUFFER_STORE_FORMAT_D16_HI_X, +amdgpu_gfx908_op_BUFFER_STORE_FORMAT_D16_X, +amdgpu_gfx908_op_BUFFER_STORE_FORMAT_D16_XY, +amdgpu_gfx908_op_BUFFER_STORE_FORMAT_D16_XYZ, +amdgpu_gfx908_op_BUFFER_STORE_FORMAT_D16_XYZW, +amdgpu_gfx908_op_BUFFER_STORE_FORMAT_X, +amdgpu_gfx908_op_BUFFER_STORE_FORMAT_XY, +amdgpu_gfx908_op_BUFFER_STORE_FORMAT_XYZ, +amdgpu_gfx908_op_BUFFER_STORE_FORMAT_XYZW, +amdgpu_gfx908_op_BUFFER_STORE_LDS_DWORD, +amdgpu_gfx908_op_BUFFER_STORE_SHORT, +amdgpu_gfx908_op_BUFFER_STORE_SHORT_D16_HI, +amdgpu_gfx908_op_BUFFER_WBINVL1, +amdgpu_gfx908_op_BUFFER_WBINVL1_VOL, +amdgpu_gfx908_op_DS_ADD_F32, +amdgpu_gfx908_op_DS_ADD_RTN_F32, +amdgpu_gfx908_op_DS_ADD_RTN_U32, +amdgpu_gfx908_op_DS_ADD_RTN_U64, +amdgpu_gfx908_op_DS_ADD_SRC2_F32, +amdgpu_gfx908_op_DS_ADD_SRC2_U32, +amdgpu_gfx908_op_DS_ADD_SRC2_U64, +amdgpu_gfx908_op_DS_ADD_U32, +amdgpu_gfx908_op_DS_ADD_U64, +amdgpu_gfx908_op_DS_AND_B32, +amdgpu_gfx908_op_DS_AND_B64, +amdgpu_gfx908_op_DS_AND_RTN_B32, +amdgpu_gfx908_op_DS_AND_RTN_B64, +amdgpu_gfx908_op_DS_AND_SRC2_B32, +amdgpu_gfx908_op_DS_AND_SRC2_B64, +amdgpu_gfx908_op_DS_APPEND, +amdgpu_gfx908_op_DS_BPERMUTE_B32, +amdgpu_gfx908_op_DS_CMPST_B32, +amdgpu_gfx908_op_DS_CMPST_B64, +amdgpu_gfx908_op_DS_CMPST_F32, +amdgpu_gfx908_op_DS_CMPST_F64, +amdgpu_gfx908_op_DS_CMPST_RTN_B32, +amdgpu_gfx908_op_DS_CMPST_RTN_B64, +amdgpu_gfx908_op_DS_CMPST_RTN_F32, +amdgpu_gfx908_op_DS_CMPST_RTN_F64, +amdgpu_gfx908_op_DS_CONDXCHG32_RTN_B64, +amdgpu_gfx908_op_DS_CONSUME, +amdgpu_gfx908_op_DS_DEC_RTN_U32, +amdgpu_gfx908_op_DS_DEC_RTN_U64, +amdgpu_gfx908_op_DS_DEC_SRC2_U32, +amdgpu_gfx908_op_DS_DEC_SRC2_U64, +amdgpu_gfx908_op_DS_DEC_U32, +amdgpu_gfx908_op_DS_DEC_U64, +amdgpu_gfx908_op_DS_GWS_BARRIER, +amdgpu_gfx908_op_DS_GWS_INIT, +amdgpu_gfx908_op_DS_GWS_SEMA_BR, +amdgpu_gfx908_op_DS_GWS_SEMA_P, +amdgpu_gfx908_op_DS_GWS_SEMA_RELEASE_ALL, +amdgpu_gfx908_op_DS_GWS_SEMA_V, +amdgpu_gfx908_op_DS_INC_RTN_U32, +amdgpu_gfx908_op_DS_INC_RTN_U64, +amdgpu_gfx908_op_DS_INC_SRC2_U32, +amdgpu_gfx908_op_DS_INC_SRC2_U64, +amdgpu_gfx908_op_DS_INC_U32, +amdgpu_gfx908_op_DS_INC_U64, +amdgpu_gfx908_op_DS_MAX_F32, +amdgpu_gfx908_op_DS_MAX_F64, +amdgpu_gfx908_op_DS_MAX_I32, +amdgpu_gfx908_op_DS_MAX_I64, +amdgpu_gfx908_op_DS_MAX_RTN_F32, +amdgpu_gfx908_op_DS_MAX_RTN_F64, +amdgpu_gfx908_op_DS_MAX_RTN_I32, +amdgpu_gfx908_op_DS_MAX_RTN_I64, +amdgpu_gfx908_op_DS_MAX_RTN_U32, +amdgpu_gfx908_op_DS_MAX_RTN_U64, +amdgpu_gfx908_op_DS_MAX_SRC2_F32, +amdgpu_gfx908_op_DS_MAX_SRC2_F64, +amdgpu_gfx908_op_DS_MAX_SRC2_I32, +amdgpu_gfx908_op_DS_MAX_SRC2_I64, +amdgpu_gfx908_op_DS_MAX_SRC2_U32, +amdgpu_gfx908_op_DS_MAX_SRC2_U64, +amdgpu_gfx908_op_DS_MAX_U32, +amdgpu_gfx908_op_DS_MAX_U64, +amdgpu_gfx908_op_DS_MIN_F32, +amdgpu_gfx908_op_DS_MIN_F64, +amdgpu_gfx908_op_DS_MIN_I32, +amdgpu_gfx908_op_DS_MIN_I64, +amdgpu_gfx908_op_DS_MIN_RTN_F32, +amdgpu_gfx908_op_DS_MIN_RTN_F64, +amdgpu_gfx908_op_DS_MIN_RTN_I32, +amdgpu_gfx908_op_DS_MIN_RTN_I64, +amdgpu_gfx908_op_DS_MIN_RTN_U32, +amdgpu_gfx908_op_DS_MIN_RTN_U64, +amdgpu_gfx908_op_DS_MIN_SRC2_F32, +amdgpu_gfx908_op_DS_MIN_SRC2_F64, +amdgpu_gfx908_op_DS_MIN_SRC2_I32, +amdgpu_gfx908_op_DS_MIN_SRC2_I64, +amdgpu_gfx908_op_DS_MIN_SRC2_U32, +amdgpu_gfx908_op_DS_MIN_SRC2_U64, +amdgpu_gfx908_op_DS_MIN_U32, +amdgpu_gfx908_op_DS_MIN_U64, +amdgpu_gfx908_op_DS_MSKOR_B32, +amdgpu_gfx908_op_DS_MSKOR_B64, +amdgpu_gfx908_op_DS_MSKOR_RTN_B32, +amdgpu_gfx908_op_DS_MSKOR_RTN_B64, +amdgpu_gfx908_op_DS_NOP, +amdgpu_gfx908_op_DS_ORDERED_COUNT, +amdgpu_gfx908_op_DS_OR_B32, +amdgpu_gfx908_op_DS_OR_B64, +amdgpu_gfx908_op_DS_OR_RTN_B32, +amdgpu_gfx908_op_DS_OR_RTN_B64, +amdgpu_gfx908_op_DS_OR_SRC2_B32, +amdgpu_gfx908_op_DS_OR_SRC2_B64, +amdgpu_gfx908_op_DS_PERMUTE_B32, +amdgpu_gfx908_op_DS_READ2ST64_B32, +amdgpu_gfx908_op_DS_READ2ST64_B64, +amdgpu_gfx908_op_DS_READ2_B32, +amdgpu_gfx908_op_DS_READ2_B64, +amdgpu_gfx908_op_DS_READ_ADDTID_B32, +amdgpu_gfx908_op_DS_READ_B128, +amdgpu_gfx908_op_DS_READ_B32, +amdgpu_gfx908_op_DS_READ_B64, +amdgpu_gfx908_op_DS_READ_B96, +amdgpu_gfx908_op_DS_READ_I16, +amdgpu_gfx908_op_DS_READ_I8, +amdgpu_gfx908_op_DS_READ_I8_D16, +amdgpu_gfx908_op_DS_READ_I8_D16_HI, +amdgpu_gfx908_op_DS_READ_U16, +amdgpu_gfx908_op_DS_READ_U16_D16, +amdgpu_gfx908_op_DS_READ_U16_D16_HI, +amdgpu_gfx908_op_DS_READ_U8, +amdgpu_gfx908_op_DS_READ_U8_D16, +amdgpu_gfx908_op_DS_READ_U8_D16_HI, +amdgpu_gfx908_op_DS_RSUB_RTN_U32, +amdgpu_gfx908_op_DS_RSUB_RTN_U64, +amdgpu_gfx908_op_DS_RSUB_SRC2_U32, +amdgpu_gfx908_op_DS_RSUB_SRC2_U64, +amdgpu_gfx908_op_DS_RSUB_U32, +amdgpu_gfx908_op_DS_RSUB_U64, +amdgpu_gfx908_op_DS_SUB_RTN_U32, +amdgpu_gfx908_op_DS_SUB_RTN_U64, +amdgpu_gfx908_op_DS_SUB_SRC2_U32, +amdgpu_gfx908_op_DS_SUB_SRC2_U64, +amdgpu_gfx908_op_DS_SUB_U32, +amdgpu_gfx908_op_DS_SUB_U64, +amdgpu_gfx908_op_DS_SWIZZLE_B32, +amdgpu_gfx908_op_DS_WRAP_RTN_B32, +amdgpu_gfx908_op_DS_WRITE2ST64_B32, +amdgpu_gfx908_op_DS_WRITE2ST64_B64, +amdgpu_gfx908_op_DS_WRITE2_B32, +amdgpu_gfx908_op_DS_WRITE2_B64, +amdgpu_gfx908_op_DS_WRITE_ADDTID_B32, +amdgpu_gfx908_op_DS_WRITE_B128, +amdgpu_gfx908_op_DS_WRITE_B16, +amdgpu_gfx908_op_DS_WRITE_B16_D16_HI, +amdgpu_gfx908_op_DS_WRITE_B32, +amdgpu_gfx908_op_DS_WRITE_B64, +amdgpu_gfx908_op_DS_WRITE_B8, +amdgpu_gfx908_op_DS_WRITE_B8_D16_HI, +amdgpu_gfx908_op_DS_WRITE_B96, +amdgpu_gfx908_op_DS_WRITE_SRC2_B32, +amdgpu_gfx908_op_DS_WRITE_SRC2_B64, +amdgpu_gfx908_op_DS_WRXCHG2ST64_RTN_B32, +amdgpu_gfx908_op_DS_WRXCHG2ST64_RTN_B64, +amdgpu_gfx908_op_DS_WRXCHG2_RTN_B32, +amdgpu_gfx908_op_DS_WRXCHG2_RTN_B64, +amdgpu_gfx908_op_DS_WRXCHG_RTN_B32, +amdgpu_gfx908_op_DS_WRXCHG_RTN_B64, +amdgpu_gfx908_op_DS_XOR_B32, +amdgpu_gfx908_op_DS_XOR_B64, +amdgpu_gfx908_op_DS_XOR_RTN_B32, +amdgpu_gfx908_op_DS_XOR_RTN_B64, +amdgpu_gfx908_op_DS_XOR_SRC2_B32, +amdgpu_gfx908_op_DS_XOR_SRC2_B64, +amdgpu_gfx908_op_EXP, +amdgpu_gfx908_op_FLAT_ATOMIC_ADD, +amdgpu_gfx908_op_FLAT_ATOMIC_ADD_X2, +amdgpu_gfx908_op_FLAT_ATOMIC_AND, +amdgpu_gfx908_op_FLAT_ATOMIC_AND_X2, +amdgpu_gfx908_op_FLAT_ATOMIC_CMPSWAP, +amdgpu_gfx908_op_FLAT_ATOMIC_CMPSWAP_X2, +amdgpu_gfx908_op_FLAT_ATOMIC_DEC, +amdgpu_gfx908_op_FLAT_ATOMIC_DEC_X2, +amdgpu_gfx908_op_FLAT_ATOMIC_INC, +amdgpu_gfx908_op_FLAT_ATOMIC_INC_X2, +amdgpu_gfx908_op_FLAT_ATOMIC_OR, +amdgpu_gfx908_op_FLAT_ATOMIC_OR_X2, +amdgpu_gfx908_op_FLAT_ATOMIC_SMAX, +amdgpu_gfx908_op_FLAT_ATOMIC_SMAX_X2, +amdgpu_gfx908_op_FLAT_ATOMIC_SMIN, +amdgpu_gfx908_op_FLAT_ATOMIC_SMIN_X2, +amdgpu_gfx908_op_FLAT_ATOMIC_SUB, +amdgpu_gfx908_op_FLAT_ATOMIC_SUB_X2, +amdgpu_gfx908_op_FLAT_ATOMIC_SWAP, +amdgpu_gfx908_op_FLAT_ATOMIC_SWAP_X2, +amdgpu_gfx908_op_FLAT_ATOMIC_UMAX, +amdgpu_gfx908_op_FLAT_ATOMIC_UMAX_X2, +amdgpu_gfx908_op_FLAT_ATOMIC_UMIN, +amdgpu_gfx908_op_FLAT_ATOMIC_UMIN_X2, +amdgpu_gfx908_op_FLAT_ATOMIC_XOR, +amdgpu_gfx908_op_FLAT_ATOMIC_XOR_X2, +amdgpu_gfx908_op_FLAT_LOAD_DWORD, +amdgpu_gfx908_op_FLAT_LOAD_DWORDX2, +amdgpu_gfx908_op_FLAT_LOAD_DWORDX3, +amdgpu_gfx908_op_FLAT_LOAD_DWORDX4, +amdgpu_gfx908_op_FLAT_LOAD_SBYTE, +amdgpu_gfx908_op_FLAT_LOAD_SBYTE_D16, +amdgpu_gfx908_op_FLAT_LOAD_SBYTE_D16_HI, +amdgpu_gfx908_op_FLAT_LOAD_SHORT_D16, +amdgpu_gfx908_op_FLAT_LOAD_SHORT_D16_HI, +amdgpu_gfx908_op_FLAT_LOAD_SSHORT, +amdgpu_gfx908_op_FLAT_LOAD_UBYTE, +amdgpu_gfx908_op_FLAT_LOAD_UBYTE_D16, +amdgpu_gfx908_op_FLAT_LOAD_UBYTE_D16_HI, +amdgpu_gfx908_op_FLAT_LOAD_USHORT, +amdgpu_gfx908_op_FLAT_STORE_BYTE, +amdgpu_gfx908_op_FLAT_STORE_BYTE_D16_HI, +amdgpu_gfx908_op_FLAT_STORE_DWORD, +amdgpu_gfx908_op_FLAT_STORE_DWORDX2, +amdgpu_gfx908_op_FLAT_STORE_DWORDX3, +amdgpu_gfx908_op_FLAT_STORE_DWORDX4, +amdgpu_gfx908_op_FLAT_STORE_SHORT, +amdgpu_gfx908_op_FLAT_STORE_SHORT_D16_HI, +amdgpu_gfx908_op_GLOBAL_ATOMIC_ADD, +amdgpu_gfx908_op_GLOBAL_ATOMIC_ADD_F32, +amdgpu_gfx908_op_GLOBAL_ATOMIC_ADD_X2, +amdgpu_gfx908_op_GLOBAL_ATOMIC_AND, +amdgpu_gfx908_op_GLOBAL_ATOMIC_AND_X2, +amdgpu_gfx908_op_GLOBAL_ATOMIC_CMPSWAP, +amdgpu_gfx908_op_GLOBAL_ATOMIC_CMPSWAP_X2, +amdgpu_gfx908_op_GLOBAL_ATOMIC_DEC, +amdgpu_gfx908_op_GLOBAL_ATOMIC_DEC_X2, +amdgpu_gfx908_op_GLOBAL_ATOMIC_INC, +amdgpu_gfx908_op_GLOBAL_ATOMIC_INC_X2, +amdgpu_gfx908_op_GLOBAL_ATOMIC_OR, +amdgpu_gfx908_op_GLOBAL_ATOMIC_OR_X2, +amdgpu_gfx908_op_GLOBAL_ATOMIC_PK_ADD_F16, +amdgpu_gfx908_op_GLOBAL_ATOMIC_SMAX, +amdgpu_gfx908_op_GLOBAL_ATOMIC_SMAX_X2, +amdgpu_gfx908_op_GLOBAL_ATOMIC_SMIN, +amdgpu_gfx908_op_GLOBAL_ATOMIC_SMIN_X2, +amdgpu_gfx908_op_GLOBAL_ATOMIC_SUB, +amdgpu_gfx908_op_GLOBAL_ATOMIC_SUB_X2, +amdgpu_gfx908_op_GLOBAL_ATOMIC_SWAP, +amdgpu_gfx908_op_GLOBAL_ATOMIC_SWAP_X2, +amdgpu_gfx908_op_GLOBAL_ATOMIC_UMAX, +amdgpu_gfx908_op_GLOBAL_ATOMIC_UMAX_X2, +amdgpu_gfx908_op_GLOBAL_ATOMIC_UMIN, +amdgpu_gfx908_op_GLOBAL_ATOMIC_UMIN_X2, +amdgpu_gfx908_op_GLOBAL_ATOMIC_XOR, +amdgpu_gfx908_op_GLOBAL_ATOMIC_XOR_X2, +amdgpu_gfx908_op_GLOBAL_LOAD_DWORD, +amdgpu_gfx908_op_GLOBAL_LOAD_DWORDX2, +amdgpu_gfx908_op_GLOBAL_LOAD_DWORDX3, +amdgpu_gfx908_op_GLOBAL_LOAD_DWORDX4, +amdgpu_gfx908_op_GLOBAL_LOAD_SBYTE, +amdgpu_gfx908_op_GLOBAL_LOAD_SBYTE_D16, +amdgpu_gfx908_op_GLOBAL_LOAD_SBYTE_D16_HI, +amdgpu_gfx908_op_GLOBAL_LOAD_SHORT_D16, +amdgpu_gfx908_op_GLOBAL_LOAD_SHORT_D16_HI, +amdgpu_gfx908_op_GLOBAL_LOAD_SSHORT, +amdgpu_gfx908_op_GLOBAL_LOAD_UBYTE, +amdgpu_gfx908_op_GLOBAL_LOAD_UBYTE_D16, +amdgpu_gfx908_op_GLOBAL_LOAD_UBYTE_D16_HI, +amdgpu_gfx908_op_GLOBAL_LOAD_USHORT, +amdgpu_gfx908_op_GLOBAL_STORE_BYTE, +amdgpu_gfx908_op_GLOBAL_STORE_BYTE_D16_HI, +amdgpu_gfx908_op_GLOBAL_STORE_DWORD, +amdgpu_gfx908_op_GLOBAL_STORE_DWORDX2, +amdgpu_gfx908_op_GLOBAL_STORE_DWORDX3, +amdgpu_gfx908_op_GLOBAL_STORE_DWORDX4, +amdgpu_gfx908_op_GLOBAL_STORE_SHORT, +amdgpu_gfx908_op_GLOBAL_STORE_SHORT_D16_HI, +amdgpu_gfx908_op_IMAGE_ATOMIC_ADD, +amdgpu_gfx908_op_IMAGE_ATOMIC_AND, +amdgpu_gfx908_op_IMAGE_ATOMIC_CMPSWAP, +amdgpu_gfx908_op_IMAGE_ATOMIC_DEC, +amdgpu_gfx908_op_IMAGE_ATOMIC_INC, +amdgpu_gfx908_op_IMAGE_ATOMIC_OR, +amdgpu_gfx908_op_IMAGE_ATOMIC_SMAX, +amdgpu_gfx908_op_IMAGE_ATOMIC_SMIN, +amdgpu_gfx908_op_IMAGE_ATOMIC_SUB, +amdgpu_gfx908_op_IMAGE_ATOMIC_SWAP, +amdgpu_gfx908_op_IMAGE_ATOMIC_UMAX, +amdgpu_gfx908_op_IMAGE_ATOMIC_UMIN, +amdgpu_gfx908_op_IMAGE_ATOMIC_XOR, +amdgpu_gfx908_op_IMAGE_GATHER4, +amdgpu_gfx908_op_IMAGE_GATHER4H, +amdgpu_gfx908_op_IMAGE_GATHER4H_PCK, +amdgpu_gfx908_op_IMAGE_GATHER4_B, +amdgpu_gfx908_op_IMAGE_GATHER4_B_CL, +amdgpu_gfx908_op_IMAGE_GATHER4_B_CL_O, +amdgpu_gfx908_op_IMAGE_GATHER4_B_O, +amdgpu_gfx908_op_IMAGE_GATHER4_C, +amdgpu_gfx908_op_IMAGE_GATHER4_CL, +amdgpu_gfx908_op_IMAGE_GATHER4_CL_O, +amdgpu_gfx908_op_IMAGE_GATHER4_C_B, +amdgpu_gfx908_op_IMAGE_GATHER4_C_B_CL, +amdgpu_gfx908_op_IMAGE_GATHER4_C_B_CL_O, +amdgpu_gfx908_op_IMAGE_GATHER4_C_B_O, +amdgpu_gfx908_op_IMAGE_GATHER4_C_CL, +amdgpu_gfx908_op_IMAGE_GATHER4_C_CL_O, +amdgpu_gfx908_op_IMAGE_GATHER4_C_L, +amdgpu_gfx908_op_IMAGE_GATHER4_C_LZ, +amdgpu_gfx908_op_IMAGE_GATHER4_C_LZ_O, +amdgpu_gfx908_op_IMAGE_GATHER4_C_L_O, +amdgpu_gfx908_op_IMAGE_GATHER4_C_O, +amdgpu_gfx908_op_IMAGE_GATHER4_L, +amdgpu_gfx908_op_IMAGE_GATHER4_LZ, +amdgpu_gfx908_op_IMAGE_GATHER4_LZ_O, +amdgpu_gfx908_op_IMAGE_GATHER4_L_O, +amdgpu_gfx908_op_IMAGE_GATHER4_O, +amdgpu_gfx908_op_IMAGE_GATHER8H_PCK, +amdgpu_gfx908_op_IMAGE_GET_LOD, +amdgpu_gfx908_op_IMAGE_GET_RESINFO, +amdgpu_gfx908_op_IMAGE_LOAD, +amdgpu_gfx908_op_IMAGE_LOAD_MIP, +amdgpu_gfx908_op_IMAGE_LOAD_MIP_PCK, +amdgpu_gfx908_op_IMAGE_LOAD_MIP_PCK_SGN, +amdgpu_gfx908_op_IMAGE_LOAD_PCK, +amdgpu_gfx908_op_IMAGE_LOAD_PCK_SGN, +amdgpu_gfx908_op_IMAGE_SAMPLE, +amdgpu_gfx908_op_IMAGE_SAMPLE_B, +amdgpu_gfx908_op_IMAGE_SAMPLE_B_CL, +amdgpu_gfx908_op_IMAGE_SAMPLE_B_CL_O, +amdgpu_gfx908_op_IMAGE_SAMPLE_B_O, +amdgpu_gfx908_op_IMAGE_SAMPLE_C, +amdgpu_gfx908_op_IMAGE_SAMPLE_CD, +amdgpu_gfx908_op_IMAGE_SAMPLE_CD_CL, +amdgpu_gfx908_op_IMAGE_SAMPLE_CD_CL_O, +amdgpu_gfx908_op_IMAGE_SAMPLE_CD_O, +amdgpu_gfx908_op_IMAGE_SAMPLE_CL, +amdgpu_gfx908_op_IMAGE_SAMPLE_CL_O, +amdgpu_gfx908_op_IMAGE_SAMPLE_C_B, +amdgpu_gfx908_op_IMAGE_SAMPLE_C_B_CL, +amdgpu_gfx908_op_IMAGE_SAMPLE_C_B_CL_O, +amdgpu_gfx908_op_IMAGE_SAMPLE_C_B_O, +amdgpu_gfx908_op_IMAGE_SAMPLE_C_CD, +amdgpu_gfx908_op_IMAGE_SAMPLE_C_CD_CL, +amdgpu_gfx908_op_IMAGE_SAMPLE_C_CD_CL_O, +amdgpu_gfx908_op_IMAGE_SAMPLE_C_CD_O, +amdgpu_gfx908_op_IMAGE_SAMPLE_C_CL, +amdgpu_gfx908_op_IMAGE_SAMPLE_C_CL_O, +amdgpu_gfx908_op_IMAGE_SAMPLE_C_D, +amdgpu_gfx908_op_IMAGE_SAMPLE_C_D_CL, +amdgpu_gfx908_op_IMAGE_SAMPLE_C_D_CL_O, +amdgpu_gfx908_op_IMAGE_SAMPLE_C_D_O, +amdgpu_gfx908_op_IMAGE_SAMPLE_C_L, +amdgpu_gfx908_op_IMAGE_SAMPLE_C_LZ, +amdgpu_gfx908_op_IMAGE_SAMPLE_C_LZ_O, +amdgpu_gfx908_op_IMAGE_SAMPLE_C_L_O, +amdgpu_gfx908_op_IMAGE_SAMPLE_C_O, +amdgpu_gfx908_op_IMAGE_SAMPLE_D, +amdgpu_gfx908_op_IMAGE_SAMPLE_D_CL, +amdgpu_gfx908_op_IMAGE_SAMPLE_D_CL_O, +amdgpu_gfx908_op_IMAGE_SAMPLE_D_O, +amdgpu_gfx908_op_IMAGE_SAMPLE_L, +amdgpu_gfx908_op_IMAGE_SAMPLE_LZ, +amdgpu_gfx908_op_IMAGE_SAMPLE_LZ_O, +amdgpu_gfx908_op_IMAGE_SAMPLE_L_O, +amdgpu_gfx908_op_IMAGE_SAMPLE_O, +amdgpu_gfx908_op_IMAGE_STORE, +amdgpu_gfx908_op_IMAGE_STORE_MIP, +amdgpu_gfx908_op_IMAGE_STORE_MIP_PCK, +amdgpu_gfx908_op_IMAGE_STORE_PCK, +amdgpu_gfx908_op_SCRATCH_LOAD_DWORD, +amdgpu_gfx908_op_SCRATCH_LOAD_DWORDX2, +amdgpu_gfx908_op_SCRATCH_LOAD_DWORDX3, +amdgpu_gfx908_op_SCRATCH_LOAD_DWORDX4, +amdgpu_gfx908_op_SCRATCH_LOAD_SBYTE, +amdgpu_gfx908_op_SCRATCH_LOAD_SBYTE_D16, +amdgpu_gfx908_op_SCRATCH_LOAD_SBYTE_D16_HI, +amdgpu_gfx908_op_SCRATCH_LOAD_SHORT_D16, +amdgpu_gfx908_op_SCRATCH_LOAD_SHORT_D16_HI, +amdgpu_gfx908_op_SCRATCH_LOAD_SSHORT, +amdgpu_gfx908_op_SCRATCH_LOAD_UBYTE, +amdgpu_gfx908_op_SCRATCH_LOAD_UBYTE_D16, +amdgpu_gfx908_op_SCRATCH_LOAD_UBYTE_D16_HI, +amdgpu_gfx908_op_SCRATCH_LOAD_USHORT, +amdgpu_gfx908_op_SCRATCH_STORE_BYTE, +amdgpu_gfx908_op_SCRATCH_STORE_BYTE_D16_HI, +amdgpu_gfx908_op_SCRATCH_STORE_DWORD, +amdgpu_gfx908_op_SCRATCH_STORE_DWORDX2, +amdgpu_gfx908_op_SCRATCH_STORE_DWORDX3, +amdgpu_gfx908_op_SCRATCH_STORE_DWORDX4, +amdgpu_gfx908_op_SCRATCH_STORE_SHORT, +amdgpu_gfx908_op_SCRATCH_STORE_SHORT_D16_HI, +amdgpu_gfx908_op_S_ABSDIFF_I32, +amdgpu_gfx908_op_S_ABS_I32, +amdgpu_gfx908_op_S_ADDC_U32, +amdgpu_gfx908_op_S_ADDK_I32, +amdgpu_gfx908_op_S_ADD_I32, +amdgpu_gfx908_op_S_ADD_U32, +amdgpu_gfx908_op_S_ANDN1_SAVEEXEC_B64, +amdgpu_gfx908_op_S_ANDN1_WREXEC_B64, +amdgpu_gfx908_op_S_ANDN2_B32, +amdgpu_gfx908_op_S_ANDN2_B64, +amdgpu_gfx908_op_S_ANDN2_SAVEEXEC_B64, +amdgpu_gfx908_op_S_ANDN2_WREXEC_B64, +amdgpu_gfx908_op_S_AND_B32, +amdgpu_gfx908_op_S_AND_B64, +amdgpu_gfx908_op_S_AND_SAVEEXEC_B64, +amdgpu_gfx908_op_S_ASHR_I32, +amdgpu_gfx908_op_S_ASHR_I64, +amdgpu_gfx908_op_S_ATC_PROBE, +amdgpu_gfx908_op_S_ATC_PROBE_BUFFER, +amdgpu_gfx908_op_S_ATOMIC_ADD, +amdgpu_gfx908_op_S_ATOMIC_ADD_X2, +amdgpu_gfx908_op_S_ATOMIC_AND, +amdgpu_gfx908_op_S_ATOMIC_AND_X2, +amdgpu_gfx908_op_S_ATOMIC_CMPSWAP, +amdgpu_gfx908_op_S_ATOMIC_CMPSWAP_X2, +amdgpu_gfx908_op_S_ATOMIC_DEC, +amdgpu_gfx908_op_S_ATOMIC_DEC_X2, +amdgpu_gfx908_op_S_ATOMIC_INC, +amdgpu_gfx908_op_S_ATOMIC_INC_X2, +amdgpu_gfx908_op_S_ATOMIC_OR, +amdgpu_gfx908_op_S_ATOMIC_OR_X2, +amdgpu_gfx908_op_S_ATOMIC_SMAX, +amdgpu_gfx908_op_S_ATOMIC_SMAX_X2, +amdgpu_gfx908_op_S_ATOMIC_SMIN, +amdgpu_gfx908_op_S_ATOMIC_SMIN_X2, +amdgpu_gfx908_op_S_ATOMIC_SUB, +amdgpu_gfx908_op_S_ATOMIC_SUB_X2, +amdgpu_gfx908_op_S_ATOMIC_SWAP, +amdgpu_gfx908_op_S_ATOMIC_SWAP_X2, +amdgpu_gfx908_op_S_ATOMIC_UMAX, +amdgpu_gfx908_op_S_ATOMIC_UMAX_X2, +amdgpu_gfx908_op_S_ATOMIC_UMIN, +amdgpu_gfx908_op_S_ATOMIC_UMIN_X2, +amdgpu_gfx908_op_S_ATOMIC_XOR, +amdgpu_gfx908_op_S_ATOMIC_XOR_X2, +amdgpu_gfx908_op_S_BARRIER, +amdgpu_gfx908_op_S_BCNT0_I32_B32, +amdgpu_gfx908_op_S_BCNT0_I32_B64, +amdgpu_gfx908_op_S_BCNT1_I32_B32, +amdgpu_gfx908_op_S_BCNT1_I32_B64, +amdgpu_gfx908_op_S_BFE_I32, +amdgpu_gfx908_op_S_BFE_I64, +amdgpu_gfx908_op_S_BFE_U32, +amdgpu_gfx908_op_S_BFE_U64, +amdgpu_gfx908_op_S_BFM_B32, +amdgpu_gfx908_op_S_BFM_B64, +amdgpu_gfx908_op_S_BITCMP0_B32, +amdgpu_gfx908_op_S_BITCMP0_B64, +amdgpu_gfx908_op_S_BITCMP1_B32, +amdgpu_gfx908_op_S_BITCMP1_B64, +amdgpu_gfx908_op_S_BITREPLICATE_B64_B32, +amdgpu_gfx908_op_S_BITSET0_B32, +amdgpu_gfx908_op_S_BITSET0_B64, +amdgpu_gfx908_op_S_BITSET1_B32, +amdgpu_gfx908_op_S_BITSET1_B64, +amdgpu_gfx908_op_S_BRANCH, +amdgpu_gfx908_op_S_BREV_B32, +amdgpu_gfx908_op_S_BREV_B64, +amdgpu_gfx908_op_S_BUFFER_ATOMIC_ADD, +amdgpu_gfx908_op_S_BUFFER_ATOMIC_ADD_X2, +amdgpu_gfx908_op_S_BUFFER_ATOMIC_AND, +amdgpu_gfx908_op_S_BUFFER_ATOMIC_AND_X2, +amdgpu_gfx908_op_S_BUFFER_ATOMIC_CMPSWAP, +amdgpu_gfx908_op_S_BUFFER_ATOMIC_CMPSWAP_X2, +amdgpu_gfx908_op_S_BUFFER_ATOMIC_DEC, +amdgpu_gfx908_op_S_BUFFER_ATOMIC_DEC_X2, +amdgpu_gfx908_op_S_BUFFER_ATOMIC_INC, +amdgpu_gfx908_op_S_BUFFER_ATOMIC_INC_X2, +amdgpu_gfx908_op_S_BUFFER_ATOMIC_OR, +amdgpu_gfx908_op_S_BUFFER_ATOMIC_OR_X2, +amdgpu_gfx908_op_S_BUFFER_ATOMIC_SMAX, +amdgpu_gfx908_op_S_BUFFER_ATOMIC_SMAX_X2, +amdgpu_gfx908_op_S_BUFFER_ATOMIC_SMIN, +amdgpu_gfx908_op_S_BUFFER_ATOMIC_SMIN_X2, +amdgpu_gfx908_op_S_BUFFER_ATOMIC_SUB, +amdgpu_gfx908_op_S_BUFFER_ATOMIC_SUB_X2, +amdgpu_gfx908_op_S_BUFFER_ATOMIC_SWAP, +amdgpu_gfx908_op_S_BUFFER_ATOMIC_SWAP_X2, +amdgpu_gfx908_op_S_BUFFER_ATOMIC_UMAX, +amdgpu_gfx908_op_S_BUFFER_ATOMIC_UMAX_X2, +amdgpu_gfx908_op_S_BUFFER_ATOMIC_UMIN, +amdgpu_gfx908_op_S_BUFFER_ATOMIC_UMIN_X2, +amdgpu_gfx908_op_S_BUFFER_ATOMIC_XOR, +amdgpu_gfx908_op_S_BUFFER_ATOMIC_XOR_X2, +amdgpu_gfx908_op_S_BUFFER_LOAD_DWORD, +amdgpu_gfx908_op_S_BUFFER_LOAD_DWORDX16, +amdgpu_gfx908_op_S_BUFFER_LOAD_DWORDX2, +amdgpu_gfx908_op_S_BUFFER_LOAD_DWORDX4, +amdgpu_gfx908_op_S_BUFFER_LOAD_DWORDX8, +amdgpu_gfx908_op_S_BUFFER_STORE_DWORD, +amdgpu_gfx908_op_S_BUFFER_STORE_DWORDX2, +amdgpu_gfx908_op_S_BUFFER_STORE_DWORDX4, +amdgpu_gfx908_op_S_CALL_B64, +amdgpu_gfx908_op_S_CBRANCH_CDBGSYS, +amdgpu_gfx908_op_S_CBRANCH_CDBGSYS_AND_USER, +amdgpu_gfx908_op_S_CBRANCH_CDBGSYS_OR_USER, +amdgpu_gfx908_op_S_CBRANCH_CDBGUSER, +amdgpu_gfx908_op_S_CBRANCH_EXECNZ, +amdgpu_gfx908_op_S_CBRANCH_EXECZ, +amdgpu_gfx908_op_S_CBRANCH_G_FORK, +amdgpu_gfx908_op_S_CBRANCH_I_FORK, +amdgpu_gfx908_op_S_CBRANCH_JOIN, +amdgpu_gfx908_op_S_CBRANCH_SCC0, +amdgpu_gfx908_op_S_CBRANCH_SCC1, +amdgpu_gfx908_op_S_CBRANCH_VCCNZ, +amdgpu_gfx908_op_S_CBRANCH_VCCZ, +amdgpu_gfx908_op_S_CMOVK_I32, +amdgpu_gfx908_op_S_CMOV_B32, +amdgpu_gfx908_op_S_CMOV_B64, +amdgpu_gfx908_op_S_CMPK_EQ_I32, +amdgpu_gfx908_op_S_CMPK_EQ_U32, +amdgpu_gfx908_op_S_CMPK_GE_I32, +amdgpu_gfx908_op_S_CMPK_GE_U32, +amdgpu_gfx908_op_S_CMPK_GT_I32, +amdgpu_gfx908_op_S_CMPK_GT_U32, +amdgpu_gfx908_op_S_CMPK_LE_I32, +amdgpu_gfx908_op_S_CMPK_LE_U32, +amdgpu_gfx908_op_S_CMPK_LG_I32, +amdgpu_gfx908_op_S_CMPK_LG_U32, +amdgpu_gfx908_op_S_CMPK_LT_I32, +amdgpu_gfx908_op_S_CMPK_LT_U32, +amdgpu_gfx908_op_S_CMP_EQ_I32, +amdgpu_gfx908_op_S_CMP_EQ_U32, +amdgpu_gfx908_op_S_CMP_EQ_U64, +amdgpu_gfx908_op_S_CMP_GE_I32, +amdgpu_gfx908_op_S_CMP_GE_U32, +amdgpu_gfx908_op_S_CMP_GT_I32, +amdgpu_gfx908_op_S_CMP_GT_U32, +amdgpu_gfx908_op_S_CMP_LE_I32, +amdgpu_gfx908_op_S_CMP_LE_U32, +amdgpu_gfx908_op_S_CMP_LG_I32, +amdgpu_gfx908_op_S_CMP_LG_U32, +amdgpu_gfx908_op_S_CMP_LG_U64, +amdgpu_gfx908_op_S_CMP_LT_I32, +amdgpu_gfx908_op_S_CMP_LT_U32, +amdgpu_gfx908_op_S_CSELECT_B32, +amdgpu_gfx908_op_S_CSELECT_B64, +amdgpu_gfx908_op_S_DCACHE_DISCARD, +amdgpu_gfx908_op_S_DCACHE_DISCARD_X2, +amdgpu_gfx908_op_S_DCACHE_INV, +amdgpu_gfx908_op_S_DCACHE_INV_VOL, +amdgpu_gfx908_op_S_DCACHE_WB, +amdgpu_gfx908_op_S_DCACHE_WB_VOL, +amdgpu_gfx908_op_S_DECPERFLEVEL, +amdgpu_gfx908_op_S_ENDPGM, +amdgpu_gfx908_op_S_ENDPGM_ORDERED_PS_DONE, +amdgpu_gfx908_op_S_ENDPGM_SAVED, +amdgpu_gfx908_op_S_FF0_I32_B32, +amdgpu_gfx908_op_S_FF0_I32_B64, +amdgpu_gfx908_op_S_FF1_I32_B32, +amdgpu_gfx908_op_S_FF1_I32_B64, +amdgpu_gfx908_op_S_FLBIT_I32, +amdgpu_gfx908_op_S_FLBIT_I32_B32, +amdgpu_gfx908_op_S_FLBIT_I32_B64, +amdgpu_gfx908_op_S_FLBIT_I32_I64, +amdgpu_gfx908_op_S_GETPC_B64, +amdgpu_gfx908_op_S_GETREG_B32, +amdgpu_gfx908_op_S_ICACHE_INV, +amdgpu_gfx908_op_S_INCPERFLEVEL, +amdgpu_gfx908_op_S_LOAD_DWORD, +amdgpu_gfx908_op_S_LOAD_DWORDX16, +amdgpu_gfx908_op_S_LOAD_DWORDX2, +amdgpu_gfx908_op_S_LOAD_DWORDX4, +amdgpu_gfx908_op_S_LOAD_DWORDX8, +amdgpu_gfx908_op_S_LSHL1_ADD_U32, +amdgpu_gfx908_op_S_LSHL2_ADD_U32, +amdgpu_gfx908_op_S_LSHL3_ADD_U32, +amdgpu_gfx908_op_S_LSHL4_ADD_U32, +amdgpu_gfx908_op_S_LSHL_B32, +amdgpu_gfx908_op_S_LSHL_B64, +amdgpu_gfx908_op_S_LSHR_B32, +amdgpu_gfx908_op_S_LSHR_B64, +amdgpu_gfx908_op_S_MAX_I32, +amdgpu_gfx908_op_S_MAX_U32, +amdgpu_gfx908_op_S_MEMREALTIME, +amdgpu_gfx908_op_S_MEMTIME, +amdgpu_gfx908_op_S_MIN_I32, +amdgpu_gfx908_op_S_MIN_U32, +amdgpu_gfx908_op_S_MOVK_I32, +amdgpu_gfx908_op_S_MOVRELD_B32, +amdgpu_gfx908_op_S_MOVRELD_B64, +amdgpu_gfx908_op_S_MOVRELS_B32, +amdgpu_gfx908_op_S_MOVRELS_B64, +amdgpu_gfx908_op_S_MOV_B32, +amdgpu_gfx908_op_S_MOV_B64, +amdgpu_gfx908_op_S_MULK_I32, +amdgpu_gfx908_op_S_MUL_HI_I32, +amdgpu_gfx908_op_S_MUL_HI_U32, +amdgpu_gfx908_op_S_MUL_I32, +amdgpu_gfx908_op_S_NAND_B32, +amdgpu_gfx908_op_S_NAND_B64, +amdgpu_gfx908_op_S_NAND_SAVEEXEC_B64, +amdgpu_gfx908_op_S_NOP, +amdgpu_gfx908_op_S_NOR_B32, +amdgpu_gfx908_op_S_NOR_B64, +amdgpu_gfx908_op_S_NOR_SAVEEXEC_B64, +amdgpu_gfx908_op_S_NOT_B32, +amdgpu_gfx908_op_S_NOT_B64, +amdgpu_gfx908_op_S_ORN1_SAVEEXEC_B64, +amdgpu_gfx908_op_S_ORN2_B32, +amdgpu_gfx908_op_S_ORN2_B64, +amdgpu_gfx908_op_S_ORN2_SAVEEXEC_B64, +amdgpu_gfx908_op_S_OR_B32, +amdgpu_gfx908_op_S_OR_B64, +amdgpu_gfx908_op_S_OR_SAVEEXEC_B64, +amdgpu_gfx908_op_S_PACK_HH_B32_B16, +amdgpu_gfx908_op_S_PACK_LH_B32_B16, +amdgpu_gfx908_op_S_PACK_LL_B32_B16, +amdgpu_gfx908_op_S_QUADMASK_B32, +amdgpu_gfx908_op_S_QUADMASK_B64, +amdgpu_gfx908_op_S_RFE_B64, +amdgpu_gfx908_op_S_RFE_RESTORE_B64, +amdgpu_gfx908_op_S_SCRATCH_LOAD_DWORD, +amdgpu_gfx908_op_S_SCRATCH_LOAD_DWORDX2, +amdgpu_gfx908_op_S_SCRATCH_LOAD_DWORDX4, +amdgpu_gfx908_op_S_SCRATCH_STORE_DWORD, +amdgpu_gfx908_op_S_SCRATCH_STORE_DWORDX2, +amdgpu_gfx908_op_S_SCRATCH_STORE_DWORDX4, +amdgpu_gfx908_op_S_SENDMSG, +amdgpu_gfx908_op_S_SENDMSGHALT, +amdgpu_gfx908_op_S_SETHALT, +amdgpu_gfx908_op_S_SETKILL, +amdgpu_gfx908_op_S_SETPC_B64, +amdgpu_gfx908_op_S_SETPRIO, +amdgpu_gfx908_op_S_SETREG_B32, +amdgpu_gfx908_op_S_SETREG_IMM32_B32, +amdgpu_gfx908_op_S_SETVSKIP, +amdgpu_gfx908_op_S_SET_GPR_IDX_IDX, +amdgpu_gfx908_op_S_SET_GPR_IDX_MODE, +amdgpu_gfx908_op_S_SET_GPR_IDX_OFF, +amdgpu_gfx908_op_S_SET_GPR_IDX_ON, +amdgpu_gfx908_op_S_SEXT_I32_I16, +amdgpu_gfx908_op_S_SEXT_I32_I8, +amdgpu_gfx908_op_S_SLEEP, +amdgpu_gfx908_op_S_STORE_DWORD, +amdgpu_gfx908_op_S_STORE_DWORDX2, +amdgpu_gfx908_op_S_STORE_DWORDX4, +amdgpu_gfx908_op_S_SUBB_U32, +amdgpu_gfx908_op_S_SUB_I32, +amdgpu_gfx908_op_S_SUB_U32, +amdgpu_gfx908_op_S_SWAPPC_B64, +amdgpu_gfx908_op_S_TRAP, +amdgpu_gfx908_op_S_TTRACEDATA, +amdgpu_gfx908_op_S_WAITCNT, +amdgpu_gfx908_op_S_WAKEUP, +amdgpu_gfx908_op_S_WQM_B32, +amdgpu_gfx908_op_S_WQM_B64, +amdgpu_gfx908_op_S_XNOR_B32, +amdgpu_gfx908_op_S_XNOR_B64, +amdgpu_gfx908_op_S_XNOR_SAVEEXEC_B64, +amdgpu_gfx908_op_S_XOR_B32, +amdgpu_gfx908_op_S_XOR_B64, +amdgpu_gfx908_op_S_XOR_SAVEEXEC_B64, +amdgpu_gfx908_op_TBUFFER_LOAD_FORMAT_D16_X, +amdgpu_gfx908_op_TBUFFER_LOAD_FORMAT_D16_XY, +amdgpu_gfx908_op_TBUFFER_LOAD_FORMAT_D16_XYZ, +amdgpu_gfx908_op_TBUFFER_LOAD_FORMAT_D16_XYZW, +amdgpu_gfx908_op_TBUFFER_LOAD_FORMAT_X, +amdgpu_gfx908_op_TBUFFER_LOAD_FORMAT_XY, +amdgpu_gfx908_op_TBUFFER_LOAD_FORMAT_XYZ, +amdgpu_gfx908_op_TBUFFER_LOAD_FORMAT_XYZW, +amdgpu_gfx908_op_TBUFFER_STORE_FORMAT_D16_X, +amdgpu_gfx908_op_TBUFFER_STORE_FORMAT_D16_XY, +amdgpu_gfx908_op_TBUFFER_STORE_FORMAT_D16_XYZ, +amdgpu_gfx908_op_TBUFFER_STORE_FORMAT_D16_XYZW, +amdgpu_gfx908_op_TBUFFER_STORE_FORMAT_X, +amdgpu_gfx908_op_TBUFFER_STORE_FORMAT_XY, +amdgpu_gfx908_op_TBUFFER_STORE_FORMAT_XYZ, +amdgpu_gfx908_op_TBUFFER_STORE_FORMAT_XYZW, +amdgpu_gfx908_op_V_ACCVGPR_READ, +amdgpu_gfx908_op_V_ACCVGPR_WRITE, +amdgpu_gfx908_op_V_ADD3_U32, +amdgpu_gfx908_op_V_ADDC_CO_U32, +amdgpu_gfx908_op_V_ADD_CO_U32, +amdgpu_gfx908_op_V_ADD_F16, +amdgpu_gfx908_op_V_ADD_F32, +amdgpu_gfx908_op_V_ADD_F64, +amdgpu_gfx908_op_V_ADD_I16, +amdgpu_gfx908_op_V_ADD_I32, +amdgpu_gfx908_op_V_ADD_LSHL_U32, +amdgpu_gfx908_op_V_ADD_U16, +amdgpu_gfx908_op_V_ADD_U32, +amdgpu_gfx908_op_V_ALIGNBIT_B32, +amdgpu_gfx908_op_V_ALIGNBYTE_B32, +amdgpu_gfx908_op_V_AND_B32, +amdgpu_gfx908_op_V_AND_OR_B32, +amdgpu_gfx908_op_V_ASHRREV_I16, +amdgpu_gfx908_op_V_ASHRREV_I32, +amdgpu_gfx908_op_V_ASHRREV_I64, +amdgpu_gfx908_op_V_BCNT_U32_B32, +amdgpu_gfx908_op_V_BFE_I32, +amdgpu_gfx908_op_V_BFE_U32, +amdgpu_gfx908_op_V_BFI_B32, +amdgpu_gfx908_op_V_BFM_B32, +amdgpu_gfx908_op_V_BFREV_B32, +amdgpu_gfx908_op_V_CEIL_F16, +amdgpu_gfx908_op_V_CEIL_F32, +amdgpu_gfx908_op_V_CEIL_F64, +amdgpu_gfx908_op_V_CLREXCP, +amdgpu_gfx908_op_V_CMPX_CLASS_F16, +amdgpu_gfx908_op_V_CMPX_CLASS_F32, +amdgpu_gfx908_op_V_CMPX_CLASS_F64, +amdgpu_gfx908_op_V_CMPX_EQ_F16, +amdgpu_gfx908_op_V_CMPX_EQ_F32, +amdgpu_gfx908_op_V_CMPX_EQ_F64, +amdgpu_gfx908_op_V_CMPX_EQ_I16, +amdgpu_gfx908_op_V_CMPX_EQ_I32, +amdgpu_gfx908_op_V_CMPX_EQ_I64, +amdgpu_gfx908_op_V_CMPX_EQ_U16, +amdgpu_gfx908_op_V_CMPX_EQ_U32, +amdgpu_gfx908_op_V_CMPX_EQ_U64, +amdgpu_gfx908_op_V_CMPX_F_F16, +amdgpu_gfx908_op_V_CMPX_F_F32, +amdgpu_gfx908_op_V_CMPX_F_F64, +amdgpu_gfx908_op_V_CMPX_F_I16, +amdgpu_gfx908_op_V_CMPX_F_I32, +amdgpu_gfx908_op_V_CMPX_F_I64, +amdgpu_gfx908_op_V_CMPX_F_U16, +amdgpu_gfx908_op_V_CMPX_F_U32, +amdgpu_gfx908_op_V_CMPX_F_U64, +amdgpu_gfx908_op_V_CMPX_GE_F16, +amdgpu_gfx908_op_V_CMPX_GE_F32, +amdgpu_gfx908_op_V_CMPX_GE_F64, +amdgpu_gfx908_op_V_CMPX_GE_I16, +amdgpu_gfx908_op_V_CMPX_GE_I32, +amdgpu_gfx908_op_V_CMPX_GE_I64, +amdgpu_gfx908_op_V_CMPX_GE_U16, +amdgpu_gfx908_op_V_CMPX_GE_U32, +amdgpu_gfx908_op_V_CMPX_GE_U64, +amdgpu_gfx908_op_V_CMPX_GT_F16, +amdgpu_gfx908_op_V_CMPX_GT_F32, +amdgpu_gfx908_op_V_CMPX_GT_F64, +amdgpu_gfx908_op_V_CMPX_GT_I16, +amdgpu_gfx908_op_V_CMPX_GT_I32, +amdgpu_gfx908_op_V_CMPX_GT_I64, +amdgpu_gfx908_op_V_CMPX_GT_U16, +amdgpu_gfx908_op_V_CMPX_GT_U32, +amdgpu_gfx908_op_V_CMPX_GT_U64, +amdgpu_gfx908_op_V_CMPX_LE_F16, +amdgpu_gfx908_op_V_CMPX_LE_F32, +amdgpu_gfx908_op_V_CMPX_LE_F64, +amdgpu_gfx908_op_V_CMPX_LE_I16, +amdgpu_gfx908_op_V_CMPX_LE_I32, +amdgpu_gfx908_op_V_CMPX_LE_I64, +amdgpu_gfx908_op_V_CMPX_LE_U16, +amdgpu_gfx908_op_V_CMPX_LE_U32, +amdgpu_gfx908_op_V_CMPX_LE_U64, +amdgpu_gfx908_op_V_CMPX_LG_F16, +amdgpu_gfx908_op_V_CMPX_LG_F32, +amdgpu_gfx908_op_V_CMPX_LG_F64, +amdgpu_gfx908_op_V_CMPX_LT_F16, +amdgpu_gfx908_op_V_CMPX_LT_F32, +amdgpu_gfx908_op_V_CMPX_LT_F64, +amdgpu_gfx908_op_V_CMPX_LT_I16, +amdgpu_gfx908_op_V_CMPX_LT_I32, +amdgpu_gfx908_op_V_CMPX_LT_I64, +amdgpu_gfx908_op_V_CMPX_LT_U16, +amdgpu_gfx908_op_V_CMPX_LT_U32, +amdgpu_gfx908_op_V_CMPX_LT_U64, +amdgpu_gfx908_op_V_CMPX_NEQ_F16, +amdgpu_gfx908_op_V_CMPX_NEQ_F32, +amdgpu_gfx908_op_V_CMPX_NEQ_F64, +amdgpu_gfx908_op_V_CMPX_NE_I16, +amdgpu_gfx908_op_V_CMPX_NE_I32, +amdgpu_gfx908_op_V_CMPX_NE_I64, +amdgpu_gfx908_op_V_CMPX_NE_U16, +amdgpu_gfx908_op_V_CMPX_NE_U32, +amdgpu_gfx908_op_V_CMPX_NE_U64, +amdgpu_gfx908_op_V_CMPX_NGE_F16, +amdgpu_gfx908_op_V_CMPX_NGE_F32, +amdgpu_gfx908_op_V_CMPX_NGE_F64, +amdgpu_gfx908_op_V_CMPX_NGT_F16, +amdgpu_gfx908_op_V_CMPX_NGT_F32, +amdgpu_gfx908_op_V_CMPX_NGT_F64, +amdgpu_gfx908_op_V_CMPX_NLE_F16, +amdgpu_gfx908_op_V_CMPX_NLE_F32, +amdgpu_gfx908_op_V_CMPX_NLE_F64, +amdgpu_gfx908_op_V_CMPX_NLG_F16, +amdgpu_gfx908_op_V_CMPX_NLG_F32, +amdgpu_gfx908_op_V_CMPX_NLG_F64, +amdgpu_gfx908_op_V_CMPX_NLT_F16, +amdgpu_gfx908_op_V_CMPX_NLT_F32, +amdgpu_gfx908_op_V_CMPX_NLT_F64, +amdgpu_gfx908_op_V_CMPX_O_F16, +amdgpu_gfx908_op_V_CMPX_O_F32, +amdgpu_gfx908_op_V_CMPX_O_F64, +amdgpu_gfx908_op_V_CMPX_TRU_F16, +amdgpu_gfx908_op_V_CMPX_TRU_F32, +amdgpu_gfx908_op_V_CMPX_TRU_F64, +amdgpu_gfx908_op_V_CMPX_T_I16, +amdgpu_gfx908_op_V_CMPX_T_I32, +amdgpu_gfx908_op_V_CMPX_T_I64, +amdgpu_gfx908_op_V_CMPX_T_U16, +amdgpu_gfx908_op_V_CMPX_T_U32, +amdgpu_gfx908_op_V_CMPX_T_U64, +amdgpu_gfx908_op_V_CMPX_U_F16, +amdgpu_gfx908_op_V_CMPX_U_F32, +amdgpu_gfx908_op_V_CMPX_U_F64, +amdgpu_gfx908_op_V_CMP_CLASS_F16, +amdgpu_gfx908_op_V_CMP_CLASS_F32, +amdgpu_gfx908_op_V_CMP_CLASS_F64, +amdgpu_gfx908_op_V_CMP_EQ_F16, +amdgpu_gfx908_op_V_CMP_EQ_F32, +amdgpu_gfx908_op_V_CMP_EQ_F64, +amdgpu_gfx908_op_V_CMP_EQ_I16, +amdgpu_gfx908_op_V_CMP_EQ_I32, +amdgpu_gfx908_op_V_CMP_EQ_I64, +amdgpu_gfx908_op_V_CMP_EQ_U16, +amdgpu_gfx908_op_V_CMP_EQ_U32, +amdgpu_gfx908_op_V_CMP_EQ_U64, +amdgpu_gfx908_op_V_CMP_F_F16, +amdgpu_gfx908_op_V_CMP_F_F32, +amdgpu_gfx908_op_V_CMP_F_F64, +amdgpu_gfx908_op_V_CMP_F_I16, +amdgpu_gfx908_op_V_CMP_F_I32, +amdgpu_gfx908_op_V_CMP_F_I64, +amdgpu_gfx908_op_V_CMP_F_U16, +amdgpu_gfx908_op_V_CMP_F_U32, +amdgpu_gfx908_op_V_CMP_F_U64, +amdgpu_gfx908_op_V_CMP_GE_F16, +amdgpu_gfx908_op_V_CMP_GE_F32, +amdgpu_gfx908_op_V_CMP_GE_F64, +amdgpu_gfx908_op_V_CMP_GE_I16, +amdgpu_gfx908_op_V_CMP_GE_I32, +amdgpu_gfx908_op_V_CMP_GE_I64, +amdgpu_gfx908_op_V_CMP_GE_U16, +amdgpu_gfx908_op_V_CMP_GE_U32, +amdgpu_gfx908_op_V_CMP_GE_U64, +amdgpu_gfx908_op_V_CMP_GT_F16, +amdgpu_gfx908_op_V_CMP_GT_F32, +amdgpu_gfx908_op_V_CMP_GT_F64, +amdgpu_gfx908_op_V_CMP_GT_I16, +amdgpu_gfx908_op_V_CMP_GT_I32, +amdgpu_gfx908_op_V_CMP_GT_I64, +amdgpu_gfx908_op_V_CMP_GT_U16, +amdgpu_gfx908_op_V_CMP_GT_U32, +amdgpu_gfx908_op_V_CMP_GT_U64, +amdgpu_gfx908_op_V_CMP_LE_F16, +amdgpu_gfx908_op_V_CMP_LE_F32, +amdgpu_gfx908_op_V_CMP_LE_F64, +amdgpu_gfx908_op_V_CMP_LE_I16, +amdgpu_gfx908_op_V_CMP_LE_I32, +amdgpu_gfx908_op_V_CMP_LE_I64, +amdgpu_gfx908_op_V_CMP_LE_U16, +amdgpu_gfx908_op_V_CMP_LE_U32, +amdgpu_gfx908_op_V_CMP_LE_U64, +amdgpu_gfx908_op_V_CMP_LG_F16, +amdgpu_gfx908_op_V_CMP_LG_F32, +amdgpu_gfx908_op_V_CMP_LG_F64, +amdgpu_gfx908_op_V_CMP_LT_F16, +amdgpu_gfx908_op_V_CMP_LT_F32, +amdgpu_gfx908_op_V_CMP_LT_F64, +amdgpu_gfx908_op_V_CMP_LT_I16, +amdgpu_gfx908_op_V_CMP_LT_I32, +amdgpu_gfx908_op_V_CMP_LT_I64, +amdgpu_gfx908_op_V_CMP_LT_U16, +amdgpu_gfx908_op_V_CMP_LT_U32, +amdgpu_gfx908_op_V_CMP_LT_U64, +amdgpu_gfx908_op_V_CMP_NEQ_F16, +amdgpu_gfx908_op_V_CMP_NEQ_F32, +amdgpu_gfx908_op_V_CMP_NEQ_F64, +amdgpu_gfx908_op_V_CMP_NE_I16, +amdgpu_gfx908_op_V_CMP_NE_I32, +amdgpu_gfx908_op_V_CMP_NE_I64, +amdgpu_gfx908_op_V_CMP_NE_U16, +amdgpu_gfx908_op_V_CMP_NE_U32, +amdgpu_gfx908_op_V_CMP_NE_U64, +amdgpu_gfx908_op_V_CMP_NGE_F16, +amdgpu_gfx908_op_V_CMP_NGE_F32, +amdgpu_gfx908_op_V_CMP_NGE_F64, +amdgpu_gfx908_op_V_CMP_NGT_F16, +amdgpu_gfx908_op_V_CMP_NGT_F32, +amdgpu_gfx908_op_V_CMP_NGT_F64, +amdgpu_gfx908_op_V_CMP_NLE_F16, +amdgpu_gfx908_op_V_CMP_NLE_F32, +amdgpu_gfx908_op_V_CMP_NLE_F64, +amdgpu_gfx908_op_V_CMP_NLG_F16, +amdgpu_gfx908_op_V_CMP_NLG_F32, +amdgpu_gfx908_op_V_CMP_NLG_F64, +amdgpu_gfx908_op_V_CMP_NLT_F16, +amdgpu_gfx908_op_V_CMP_NLT_F32, +amdgpu_gfx908_op_V_CMP_NLT_F64, +amdgpu_gfx908_op_V_CMP_O_F16, +amdgpu_gfx908_op_V_CMP_O_F32, +amdgpu_gfx908_op_V_CMP_O_F64, +amdgpu_gfx908_op_V_CMP_TRU_F16, +amdgpu_gfx908_op_V_CMP_TRU_F32, +amdgpu_gfx908_op_V_CMP_TRU_F64, +amdgpu_gfx908_op_V_CMP_T_I16, +amdgpu_gfx908_op_V_CMP_T_I32, +amdgpu_gfx908_op_V_CMP_T_I64, +amdgpu_gfx908_op_V_CMP_T_U16, +amdgpu_gfx908_op_V_CMP_T_U32, +amdgpu_gfx908_op_V_CMP_T_U64, +amdgpu_gfx908_op_V_CMP_U_F16, +amdgpu_gfx908_op_V_CMP_U_F32, +amdgpu_gfx908_op_V_CMP_U_F64, +amdgpu_gfx908_op_V_CNDMASK_B32, +amdgpu_gfx908_op_V_COS_F16, +amdgpu_gfx908_op_V_COS_F32, +amdgpu_gfx908_op_V_CUBEID_F32, +amdgpu_gfx908_op_V_CUBEMA_F32, +amdgpu_gfx908_op_V_CUBESC_F32, +amdgpu_gfx908_op_V_CUBETC_F32, +amdgpu_gfx908_op_V_CVT_F16_F32, +amdgpu_gfx908_op_V_CVT_F16_I16, +amdgpu_gfx908_op_V_CVT_F16_U16, +amdgpu_gfx908_op_V_CVT_F32_F16, +amdgpu_gfx908_op_V_CVT_F32_F64, +amdgpu_gfx908_op_V_CVT_F32_I32, +amdgpu_gfx908_op_V_CVT_F32_U32, +amdgpu_gfx908_op_V_CVT_F32_UBYTE0, +amdgpu_gfx908_op_V_CVT_F32_UBYTE1, +amdgpu_gfx908_op_V_CVT_F32_UBYTE2, +amdgpu_gfx908_op_V_CVT_F32_UBYTE3, +amdgpu_gfx908_op_V_CVT_F64_F32, +amdgpu_gfx908_op_V_CVT_F64_I32, +amdgpu_gfx908_op_V_CVT_F64_U32, +amdgpu_gfx908_op_V_CVT_FLR_I32_F32, +amdgpu_gfx908_op_V_CVT_I16_F16, +amdgpu_gfx908_op_V_CVT_I32_F32, +amdgpu_gfx908_op_V_CVT_I32_F64, +amdgpu_gfx908_op_V_CVT_NORM_I16_F16, +amdgpu_gfx908_op_V_CVT_NORM_U16_F16, +amdgpu_gfx908_op_V_CVT_OFF_F32_I4, +amdgpu_gfx908_op_V_CVT_PKACCUM_U8_F32, +amdgpu_gfx908_op_V_CVT_PKNORM_I16_F16, +amdgpu_gfx908_op_V_CVT_PKNORM_I16_F32, +amdgpu_gfx908_op_V_CVT_PKNORM_U16_F16, +amdgpu_gfx908_op_V_CVT_PKNORM_U16_F32, +amdgpu_gfx908_op_V_CVT_PKRTZ_F16_F32, +amdgpu_gfx908_op_V_CVT_PK_I16_I32, +amdgpu_gfx908_op_V_CVT_PK_U16_U32, +amdgpu_gfx908_op_V_CVT_PK_U8_F32, +amdgpu_gfx908_op_V_CVT_RPI_I32_F32, +amdgpu_gfx908_op_V_CVT_U16_F16, +amdgpu_gfx908_op_V_CVT_U32_F32, +amdgpu_gfx908_op_V_CVT_U32_F64, +amdgpu_gfx908_op_V_DIV_FIXUP_F16, +amdgpu_gfx908_op_V_DIV_FIXUP_F32, +amdgpu_gfx908_op_V_DIV_FIXUP_F64, +amdgpu_gfx908_op_V_DIV_FIXUP_LEGACY_F16, +amdgpu_gfx908_op_V_DIV_FMAS_F32, +amdgpu_gfx908_op_V_DIV_FMAS_F64, +amdgpu_gfx908_op_V_DIV_SCALE_F32, +amdgpu_gfx908_op_V_DIV_SCALE_F64, +amdgpu_gfx908_op_V_DOT2C_F32_F16, +amdgpu_gfx908_op_V_DOT2C_I32_I16, +amdgpu_gfx908_op_V_DOT2_F32_F16, +amdgpu_gfx908_op_V_DOT2_I32_I16, +amdgpu_gfx908_op_V_DOT2_U32_U16, +amdgpu_gfx908_op_V_DOT4C_I32_I8, +amdgpu_gfx908_op_V_DOT4_I32_I8, +amdgpu_gfx908_op_V_DOT4_U32_U8, +amdgpu_gfx908_op_V_DOT8C_I32_I4, +amdgpu_gfx908_op_V_DOT8_I32_I4, +amdgpu_gfx908_op_V_DOT8_U32_U4, +amdgpu_gfx908_op_V_EXP_F16, +amdgpu_gfx908_op_V_EXP_F32, +amdgpu_gfx908_op_V_EXP_LEGACY_F32, +amdgpu_gfx908_op_V_FFBH_I32, +amdgpu_gfx908_op_V_FFBH_U32, +amdgpu_gfx908_op_V_FFBL_B32, +amdgpu_gfx908_op_V_FLOOR_F16, +amdgpu_gfx908_op_V_FLOOR_F32, +amdgpu_gfx908_op_V_FLOOR_F64, +amdgpu_gfx908_op_V_FMAC_F32, +amdgpu_gfx908_op_V_FMA_F16, +amdgpu_gfx908_op_V_FMA_F32, +amdgpu_gfx908_op_V_FMA_F64, +amdgpu_gfx908_op_V_FMA_LEGACY_F16, +amdgpu_gfx908_op_V_FRACT_F16, +amdgpu_gfx908_op_V_FRACT_F32, +amdgpu_gfx908_op_V_FRACT_F64, +amdgpu_gfx908_op_V_FREXP_EXP_I16_F16, +amdgpu_gfx908_op_V_FREXP_EXP_I32_F32, +amdgpu_gfx908_op_V_FREXP_EXP_I32_F64, +amdgpu_gfx908_op_V_FREXP_MANT_F16, +amdgpu_gfx908_op_V_FREXP_MANT_F32, +amdgpu_gfx908_op_V_FREXP_MANT_F64, +amdgpu_gfx908_op_V_INTERP_MOV_F32, +amdgpu_gfx908_op_V_INTERP_P1LL_F16, +amdgpu_gfx908_op_V_INTERP_P1LV_F16, +amdgpu_gfx908_op_V_INTERP_P1_F32, +amdgpu_gfx908_op_V_INTERP_P2_F16, +amdgpu_gfx908_op_V_INTERP_P2_F32, +amdgpu_gfx908_op_V_INTERP_P2_LEGACY_F16, +amdgpu_gfx908_op_V_LDEXP_F16, +amdgpu_gfx908_op_V_LDEXP_F32, +amdgpu_gfx908_op_V_LDEXP_F64, +amdgpu_gfx908_op_V_LERP_U8, +amdgpu_gfx908_op_V_LOG_F16, +amdgpu_gfx908_op_V_LOG_F32, +amdgpu_gfx908_op_V_LOG_LEGACY_F32, +amdgpu_gfx908_op_V_LSHLREV_B16, +amdgpu_gfx908_op_V_LSHLREV_B32, +amdgpu_gfx908_op_V_LSHLREV_B64, +amdgpu_gfx908_op_V_LSHL_ADD_U32, +amdgpu_gfx908_op_V_LSHL_OR_B32, +amdgpu_gfx908_op_V_LSHRREV_B16, +amdgpu_gfx908_op_V_LSHRREV_B32, +amdgpu_gfx908_op_V_LSHRREV_B64, +amdgpu_gfx908_op_V_MAC_F16, +amdgpu_gfx908_op_V_MAC_F32, +amdgpu_gfx908_op_V_MADAK_F16, +amdgpu_gfx908_op_V_MADAK_F32, +amdgpu_gfx908_op_V_MADMK_F16, +amdgpu_gfx908_op_V_MADMK_F32, +amdgpu_gfx908_op_V_MAD_F16, +amdgpu_gfx908_op_V_MAD_F32, +amdgpu_gfx908_op_V_MAD_I16, +amdgpu_gfx908_op_V_MAD_I32_I16, +amdgpu_gfx908_op_V_MAD_I32_I24, +amdgpu_gfx908_op_V_MAD_I64_I32, +amdgpu_gfx908_op_V_MAD_LEGACY_F16, +amdgpu_gfx908_op_V_MAD_LEGACY_F32, +amdgpu_gfx908_op_V_MAD_LEGACY_I16, +amdgpu_gfx908_op_V_MAD_LEGACY_U16, +amdgpu_gfx908_op_V_MAD_MIXHI_F16, +amdgpu_gfx908_op_V_MAD_MIXLO_F16, +amdgpu_gfx908_op_V_MAD_MIX_F32, +amdgpu_gfx908_op_V_MAD_U16, +amdgpu_gfx908_op_V_MAD_U32_U16, +amdgpu_gfx908_op_V_MAD_U32_U24, +amdgpu_gfx908_op_V_MAD_U64_U32, +amdgpu_gfx908_op_V_MAX3_F16, +amdgpu_gfx908_op_V_MAX3_F32, +amdgpu_gfx908_op_V_MAX3_I16, +amdgpu_gfx908_op_V_MAX3_I32, +amdgpu_gfx908_op_V_MAX3_U16, +amdgpu_gfx908_op_V_MAX3_U32, +amdgpu_gfx908_op_V_MAX_F16, +amdgpu_gfx908_op_V_MAX_F32, +amdgpu_gfx908_op_V_MAX_F64, +amdgpu_gfx908_op_V_MAX_I16, +amdgpu_gfx908_op_V_MAX_I32, +amdgpu_gfx908_op_V_MAX_U16, +amdgpu_gfx908_op_V_MAX_U32, +amdgpu_gfx908_op_V_MBCNT_HI_U32_B32, +amdgpu_gfx908_op_V_MBCNT_LO_U32_B32, +amdgpu_gfx908_op_V_MED3_F16, +amdgpu_gfx908_op_V_MED3_F32, +amdgpu_gfx908_op_V_MED3_I16, +amdgpu_gfx908_op_V_MED3_I32, +amdgpu_gfx908_op_V_MED3_U16, +amdgpu_gfx908_op_V_MED3_U32, +amdgpu_gfx908_op_V_MFMA_F32_16X16X16F16, +amdgpu_gfx908_op_V_MFMA_F32_16X16X1F32, +amdgpu_gfx908_op_V_MFMA_F32_16X16X2BF16, +amdgpu_gfx908_op_V_MFMA_F32_16X16X4F16, +amdgpu_gfx908_op_V_MFMA_F32_16X16X4F32, +amdgpu_gfx908_op_V_MFMA_F32_16X16X8BF16, +amdgpu_gfx908_op_V_MFMA_F32_32X32X1F32, +amdgpu_gfx908_op_V_MFMA_F32_32X32X2BF16, +amdgpu_gfx908_op_V_MFMA_F32_32X32X2F32, +amdgpu_gfx908_op_V_MFMA_F32_32X32X4BF16, +amdgpu_gfx908_op_V_MFMA_F32_32X32X4F16, +amdgpu_gfx908_op_V_MFMA_F32_32X32X8F16, +amdgpu_gfx908_op_V_MFMA_F32_4X4X1F32, +amdgpu_gfx908_op_V_MFMA_F32_4X4X2BF16, +amdgpu_gfx908_op_V_MFMA_F32_4X4X4F16, +amdgpu_gfx908_op_V_MFMA_I32_16X16X16I8, +amdgpu_gfx908_op_V_MFMA_I32_16X16X4I8, +amdgpu_gfx908_op_V_MFMA_I32_32X32X4I8, +amdgpu_gfx908_op_V_MFMA_I32_32X32X8I8, +amdgpu_gfx908_op_V_MFMA_I32_4X4X4I8, +amdgpu_gfx908_op_V_MIN3_F16, +amdgpu_gfx908_op_V_MIN3_F32, +amdgpu_gfx908_op_V_MIN3_I16, +amdgpu_gfx908_op_V_MIN3_I32, +amdgpu_gfx908_op_V_MIN3_U16, +amdgpu_gfx908_op_V_MIN3_U32, +amdgpu_gfx908_op_V_MIN_F16, +amdgpu_gfx908_op_V_MIN_F32, +amdgpu_gfx908_op_V_MIN_F64, +amdgpu_gfx908_op_V_MIN_I16, +amdgpu_gfx908_op_V_MIN_I32, +amdgpu_gfx908_op_V_MIN_U16, +amdgpu_gfx908_op_V_MIN_U32, +amdgpu_gfx908_op_V_MOV_B32, +amdgpu_gfx908_op_V_MQSAD_PK_U16_U8, +amdgpu_gfx908_op_V_MQSAD_U32_U8, +amdgpu_gfx908_op_V_MSAD_U8, +amdgpu_gfx908_op_V_MUL_F16, +amdgpu_gfx908_op_V_MUL_F32, +amdgpu_gfx908_op_V_MUL_F64, +amdgpu_gfx908_op_V_MUL_HI_I32, +amdgpu_gfx908_op_V_MUL_HI_I32_I24, +amdgpu_gfx908_op_V_MUL_HI_U32, +amdgpu_gfx908_op_V_MUL_HI_U32_U24, +amdgpu_gfx908_op_V_MUL_I32_I24, +amdgpu_gfx908_op_V_MUL_LEGACY_F32, +amdgpu_gfx908_op_V_MUL_LO_U16, +amdgpu_gfx908_op_V_MUL_LO_U32, +amdgpu_gfx908_op_V_MUL_U32_U24, +amdgpu_gfx908_op_V_NOP, +amdgpu_gfx908_op_V_NOT_B32, +amdgpu_gfx908_op_V_OR3_B32, +amdgpu_gfx908_op_V_OR_B32, +amdgpu_gfx908_op_V_PACK_B32_F16, +amdgpu_gfx908_op_V_PERM_B32, +amdgpu_gfx908_op_V_PK_ADD_F16, +amdgpu_gfx908_op_V_PK_ADD_I16, +amdgpu_gfx908_op_V_PK_ADD_U16, +amdgpu_gfx908_op_V_PK_ASHRREV_I16, +amdgpu_gfx908_op_V_PK_FMAC_F16, +amdgpu_gfx908_op_V_PK_FMA_F16, +amdgpu_gfx908_op_V_PK_LSHLREV_B16, +amdgpu_gfx908_op_V_PK_LSHRREV_B16, +amdgpu_gfx908_op_V_PK_MAD_I16, +amdgpu_gfx908_op_V_PK_MAD_U16, +amdgpu_gfx908_op_V_PK_MAX_F16, +amdgpu_gfx908_op_V_PK_MAX_I16, +amdgpu_gfx908_op_V_PK_MAX_U16, +amdgpu_gfx908_op_V_PK_MIN_F16, +amdgpu_gfx908_op_V_PK_MIN_I16, +amdgpu_gfx908_op_V_PK_MIN_U16, +amdgpu_gfx908_op_V_PK_MUL_F16, +amdgpu_gfx908_op_V_PK_MUL_LO_U16, +amdgpu_gfx908_op_V_PK_SUB_I16, +amdgpu_gfx908_op_V_PK_SUB_U16, +amdgpu_gfx908_op_V_QSAD_PK_U16_U8, +amdgpu_gfx908_op_V_RCP_F16, +amdgpu_gfx908_op_V_RCP_F32, +amdgpu_gfx908_op_V_RCP_F64, +amdgpu_gfx908_op_V_RCP_IFLAG_F32, +amdgpu_gfx908_op_V_READFIRSTLANE_B32, +amdgpu_gfx908_op_V_READLANE_B32, +amdgpu_gfx908_op_V_RNDNE_F16, +amdgpu_gfx908_op_V_RNDNE_F32, +amdgpu_gfx908_op_V_RNDNE_F64, +amdgpu_gfx908_op_V_RSQ_F16, +amdgpu_gfx908_op_V_RSQ_F32, +amdgpu_gfx908_op_V_RSQ_F64, +amdgpu_gfx908_op_V_SAD_HI_U8, +amdgpu_gfx908_op_V_SAD_U16, +amdgpu_gfx908_op_V_SAD_U32, +amdgpu_gfx908_op_V_SAD_U8, +amdgpu_gfx908_op_V_SAT_PK_U8_I16, +amdgpu_gfx908_op_V_SCREEN_PARTITION_4SE_B32, +amdgpu_gfx908_op_V_SIN_F16, +amdgpu_gfx908_op_V_SIN_F32, +amdgpu_gfx908_op_V_SQRT_F16, +amdgpu_gfx908_op_V_SQRT_F32, +amdgpu_gfx908_op_V_SQRT_F64, +amdgpu_gfx908_op_V_SUBBREV_CO_U32, +amdgpu_gfx908_op_V_SUBB_CO_U32, +amdgpu_gfx908_op_V_SUBREV_CO_U32, +amdgpu_gfx908_op_V_SUBREV_F16, +amdgpu_gfx908_op_V_SUBREV_F32, +amdgpu_gfx908_op_V_SUBREV_U16, +amdgpu_gfx908_op_V_SUBREV_U32, +amdgpu_gfx908_op_V_SUB_CO_U32, +amdgpu_gfx908_op_V_SUB_F16, +amdgpu_gfx908_op_V_SUB_F32, +amdgpu_gfx908_op_V_SUB_I16, +amdgpu_gfx908_op_V_SUB_I32, +amdgpu_gfx908_op_V_SUB_U16, +amdgpu_gfx908_op_V_SUB_U32, +amdgpu_gfx908_op_V_SWAP_B32, +amdgpu_gfx908_op_V_TRIG_PREOP_F64, +amdgpu_gfx908_op_V_TRUNC_F16, +amdgpu_gfx908_op_V_TRUNC_F32, +amdgpu_gfx908_op_V_TRUNC_F64, +amdgpu_gfx908_op_V_WRITELANE_B32, +amdgpu_gfx908_op_V_XAD_U32, +amdgpu_gfx908_op_V_XNOR_B32, +amdgpu_gfx908_op_V_XOR_B32, diff --git a/common/h/mnemonics/AMDGPU/gfx90a_entryIDs.h b/common/h/mnemonics/AMDGPU/gfx90a_entryIDs.h new file mode 100644 index 0000000000..196cdfdf1f --- /dev/null +++ b/common/h/mnemonics/AMDGPU/gfx90a_entryIDs.h @@ -0,0 +1,1135 @@ +amdgpu_gfx90a_op_BUFFER_ATOMIC_ADD, +amdgpu_gfx90a_op_BUFFER_ATOMIC_ADD_F32, +amdgpu_gfx90a_op_BUFFER_ATOMIC_ADD_F64, +amdgpu_gfx90a_op_BUFFER_ATOMIC_ADD_X2, +amdgpu_gfx90a_op_BUFFER_ATOMIC_AND, +amdgpu_gfx90a_op_BUFFER_ATOMIC_AND_X2, +amdgpu_gfx90a_op_BUFFER_ATOMIC_CMPSWAP, +amdgpu_gfx90a_op_BUFFER_ATOMIC_CMPSWAP_X2, +amdgpu_gfx90a_op_BUFFER_ATOMIC_DEC, +amdgpu_gfx90a_op_BUFFER_ATOMIC_DEC_X2, +amdgpu_gfx90a_op_BUFFER_ATOMIC_INC, +amdgpu_gfx90a_op_BUFFER_ATOMIC_INC_X2, +amdgpu_gfx90a_op_BUFFER_ATOMIC_MAX_F64, +amdgpu_gfx90a_op_BUFFER_ATOMIC_MIN_F64, +amdgpu_gfx90a_op_BUFFER_ATOMIC_OR, +amdgpu_gfx90a_op_BUFFER_ATOMIC_OR_X2, +amdgpu_gfx90a_op_BUFFER_ATOMIC_PK_ADD_F16, +amdgpu_gfx90a_op_BUFFER_ATOMIC_SMAX, +amdgpu_gfx90a_op_BUFFER_ATOMIC_SMAX_X2, +amdgpu_gfx90a_op_BUFFER_ATOMIC_SMIN, +amdgpu_gfx90a_op_BUFFER_ATOMIC_SMIN_X2, +amdgpu_gfx90a_op_BUFFER_ATOMIC_SUB, +amdgpu_gfx90a_op_BUFFER_ATOMIC_SUB_X2, +amdgpu_gfx90a_op_BUFFER_ATOMIC_SWAP, +amdgpu_gfx90a_op_BUFFER_ATOMIC_SWAP_X2, +amdgpu_gfx90a_op_BUFFER_ATOMIC_UMAX, +amdgpu_gfx90a_op_BUFFER_ATOMIC_UMAX_X2, +amdgpu_gfx90a_op_BUFFER_ATOMIC_UMIN, +amdgpu_gfx90a_op_BUFFER_ATOMIC_UMIN_X2, +amdgpu_gfx90a_op_BUFFER_ATOMIC_XOR, +amdgpu_gfx90a_op_BUFFER_ATOMIC_XOR_X2, +amdgpu_gfx90a_op_BUFFER_INVL2, +amdgpu_gfx90a_op_BUFFER_LOAD_DWORD, +amdgpu_gfx90a_op_BUFFER_LOAD_DWORDX2, +amdgpu_gfx90a_op_BUFFER_LOAD_DWORDX3, +amdgpu_gfx90a_op_BUFFER_LOAD_DWORDX4, +amdgpu_gfx90a_op_BUFFER_LOAD_FORMAT_D16_HI_X, +amdgpu_gfx90a_op_BUFFER_LOAD_FORMAT_D16_X, +amdgpu_gfx90a_op_BUFFER_LOAD_FORMAT_D16_XY, +amdgpu_gfx90a_op_BUFFER_LOAD_FORMAT_D16_XYZ, +amdgpu_gfx90a_op_BUFFER_LOAD_FORMAT_D16_XYZW, +amdgpu_gfx90a_op_BUFFER_LOAD_FORMAT_X, +amdgpu_gfx90a_op_BUFFER_LOAD_FORMAT_XY, +amdgpu_gfx90a_op_BUFFER_LOAD_FORMAT_XYZ, +amdgpu_gfx90a_op_BUFFER_LOAD_FORMAT_XYZW, +amdgpu_gfx90a_op_BUFFER_LOAD_SBYTE, +amdgpu_gfx90a_op_BUFFER_LOAD_SBYTE_D16, +amdgpu_gfx90a_op_BUFFER_LOAD_SBYTE_D16_HI, +amdgpu_gfx90a_op_BUFFER_LOAD_SHORT_D16, +amdgpu_gfx90a_op_BUFFER_LOAD_SHORT_D16_HI, +amdgpu_gfx90a_op_BUFFER_LOAD_SSHORT, +amdgpu_gfx90a_op_BUFFER_LOAD_UBYTE, +amdgpu_gfx90a_op_BUFFER_LOAD_UBYTE_D16, +amdgpu_gfx90a_op_BUFFER_LOAD_UBYTE_D16_HI, +amdgpu_gfx90a_op_BUFFER_LOAD_USHORT, +amdgpu_gfx90a_op_BUFFER_STORE_BYTE, +amdgpu_gfx90a_op_BUFFER_STORE_BYTE_D16_HI, +amdgpu_gfx90a_op_BUFFER_STORE_DWORD, +amdgpu_gfx90a_op_BUFFER_STORE_DWORDX2, +amdgpu_gfx90a_op_BUFFER_STORE_DWORDX3, +amdgpu_gfx90a_op_BUFFER_STORE_DWORDX4, +amdgpu_gfx90a_op_BUFFER_STORE_FORMAT_D16_HI_X, +amdgpu_gfx90a_op_BUFFER_STORE_FORMAT_D16_X, +amdgpu_gfx90a_op_BUFFER_STORE_FORMAT_D16_XY, +amdgpu_gfx90a_op_BUFFER_STORE_FORMAT_D16_XYZ, +amdgpu_gfx90a_op_BUFFER_STORE_FORMAT_D16_XYZW, +amdgpu_gfx90a_op_BUFFER_STORE_FORMAT_X, +amdgpu_gfx90a_op_BUFFER_STORE_FORMAT_XY, +amdgpu_gfx90a_op_BUFFER_STORE_FORMAT_XYZ, +amdgpu_gfx90a_op_BUFFER_STORE_FORMAT_XYZW, +amdgpu_gfx90a_op_BUFFER_STORE_LDS_DWORD, +amdgpu_gfx90a_op_BUFFER_STORE_SHORT, +amdgpu_gfx90a_op_BUFFER_STORE_SHORT_D16_HI, +amdgpu_gfx90a_op_BUFFER_WBINVL1, +amdgpu_gfx90a_op_BUFFER_WBINVL1_VOL, +amdgpu_gfx90a_op_BUFFER_WBL2, +amdgpu_gfx90a_op_DS_ADD_F32, +amdgpu_gfx90a_op_DS_ADD_F64, +amdgpu_gfx90a_op_DS_ADD_RTN_F32, +amdgpu_gfx90a_op_DS_ADD_RTN_F64, +amdgpu_gfx90a_op_DS_ADD_RTN_U32, +amdgpu_gfx90a_op_DS_ADD_RTN_U64, +amdgpu_gfx90a_op_DS_ADD_U32, +amdgpu_gfx90a_op_DS_ADD_U64, +amdgpu_gfx90a_op_DS_AND_B32, +amdgpu_gfx90a_op_DS_AND_B64, +amdgpu_gfx90a_op_DS_AND_RTN_B32, +amdgpu_gfx90a_op_DS_AND_RTN_B64, +amdgpu_gfx90a_op_DS_APPEND, +amdgpu_gfx90a_op_DS_BPERMUTE_B32, +amdgpu_gfx90a_op_DS_CMPST_B32, +amdgpu_gfx90a_op_DS_CMPST_B64, +amdgpu_gfx90a_op_DS_CMPST_F32, +amdgpu_gfx90a_op_DS_CMPST_F64, +amdgpu_gfx90a_op_DS_CMPST_RTN_B32, +amdgpu_gfx90a_op_DS_CMPST_RTN_B64, +amdgpu_gfx90a_op_DS_CMPST_RTN_F32, +amdgpu_gfx90a_op_DS_CMPST_RTN_F64, +amdgpu_gfx90a_op_DS_CONDXCHG32_RTN_B64, +amdgpu_gfx90a_op_DS_CONSUME, +amdgpu_gfx90a_op_DS_DEC_RTN_U32, +amdgpu_gfx90a_op_DS_DEC_RTN_U64, +amdgpu_gfx90a_op_DS_DEC_U32, +amdgpu_gfx90a_op_DS_DEC_U64, +amdgpu_gfx90a_op_DS_GWS_BARRIER, +amdgpu_gfx90a_op_DS_GWS_INIT, +amdgpu_gfx90a_op_DS_GWS_SEMA_BR, +amdgpu_gfx90a_op_DS_GWS_SEMA_P, +amdgpu_gfx90a_op_DS_GWS_SEMA_RELEASE_ALL, +amdgpu_gfx90a_op_DS_GWS_SEMA_V, +amdgpu_gfx90a_op_DS_INC_RTN_U32, +amdgpu_gfx90a_op_DS_INC_RTN_U64, +amdgpu_gfx90a_op_DS_INC_U32, +amdgpu_gfx90a_op_DS_INC_U64, +amdgpu_gfx90a_op_DS_MAX_F32, +amdgpu_gfx90a_op_DS_MAX_F64, +amdgpu_gfx90a_op_DS_MAX_I32, +amdgpu_gfx90a_op_DS_MAX_I64, +amdgpu_gfx90a_op_DS_MAX_RTN_F32, +amdgpu_gfx90a_op_DS_MAX_RTN_F64, +amdgpu_gfx90a_op_DS_MAX_RTN_I32, +amdgpu_gfx90a_op_DS_MAX_RTN_I64, +amdgpu_gfx90a_op_DS_MAX_RTN_U32, +amdgpu_gfx90a_op_DS_MAX_RTN_U64, +amdgpu_gfx90a_op_DS_MAX_U32, +amdgpu_gfx90a_op_DS_MAX_U64, +amdgpu_gfx90a_op_DS_MIN_F32, +amdgpu_gfx90a_op_DS_MIN_F64, +amdgpu_gfx90a_op_DS_MIN_I32, +amdgpu_gfx90a_op_DS_MIN_I64, +amdgpu_gfx90a_op_DS_MIN_RTN_F32, +amdgpu_gfx90a_op_DS_MIN_RTN_F64, +amdgpu_gfx90a_op_DS_MIN_RTN_I32, +amdgpu_gfx90a_op_DS_MIN_RTN_I64, +amdgpu_gfx90a_op_DS_MIN_RTN_U32, +amdgpu_gfx90a_op_DS_MIN_RTN_U64, +amdgpu_gfx90a_op_DS_MIN_U32, +amdgpu_gfx90a_op_DS_MIN_U64, +amdgpu_gfx90a_op_DS_MSKOR_B32, +amdgpu_gfx90a_op_DS_MSKOR_B64, +amdgpu_gfx90a_op_DS_MSKOR_RTN_B32, +amdgpu_gfx90a_op_DS_MSKOR_RTN_B64, +amdgpu_gfx90a_op_DS_NOP, +amdgpu_gfx90a_op_DS_OR_B32, +amdgpu_gfx90a_op_DS_OR_B64, +amdgpu_gfx90a_op_DS_OR_RTN_B32, +amdgpu_gfx90a_op_DS_OR_RTN_B64, +amdgpu_gfx90a_op_DS_PERMUTE_B32, +amdgpu_gfx90a_op_DS_READ2ST64_B32, +amdgpu_gfx90a_op_DS_READ2ST64_B64, +amdgpu_gfx90a_op_DS_READ2_B32, +amdgpu_gfx90a_op_DS_READ2_B64, +amdgpu_gfx90a_op_DS_READ_ADDTID_B32, +amdgpu_gfx90a_op_DS_READ_B128, +amdgpu_gfx90a_op_DS_READ_B32, +amdgpu_gfx90a_op_DS_READ_B64, +amdgpu_gfx90a_op_DS_READ_B96, +amdgpu_gfx90a_op_DS_READ_I16, +amdgpu_gfx90a_op_DS_READ_I8, +amdgpu_gfx90a_op_DS_READ_I8_D16, +amdgpu_gfx90a_op_DS_READ_I8_D16_HI, +amdgpu_gfx90a_op_DS_READ_U16, +amdgpu_gfx90a_op_DS_READ_U16_D16, +amdgpu_gfx90a_op_DS_READ_U16_D16_HI, +amdgpu_gfx90a_op_DS_READ_U8, +amdgpu_gfx90a_op_DS_READ_U8_D16, +amdgpu_gfx90a_op_DS_READ_U8_D16_HI, +amdgpu_gfx90a_op_DS_RSUB_RTN_U32, +amdgpu_gfx90a_op_DS_RSUB_RTN_U64, +amdgpu_gfx90a_op_DS_RSUB_U32, +amdgpu_gfx90a_op_DS_RSUB_U64, +amdgpu_gfx90a_op_DS_SUB_RTN_U32, +amdgpu_gfx90a_op_DS_SUB_RTN_U64, +amdgpu_gfx90a_op_DS_SUB_U32, +amdgpu_gfx90a_op_DS_SUB_U64, +amdgpu_gfx90a_op_DS_SWIZZLE_B32, +amdgpu_gfx90a_op_DS_WRAP_RTN_B32, +amdgpu_gfx90a_op_DS_WRITE2ST64_B32, +amdgpu_gfx90a_op_DS_WRITE2ST64_B64, +amdgpu_gfx90a_op_DS_WRITE2_B32, +amdgpu_gfx90a_op_DS_WRITE2_B64, +amdgpu_gfx90a_op_DS_WRITE_ADDTID_B32, +amdgpu_gfx90a_op_DS_WRITE_B128, +amdgpu_gfx90a_op_DS_WRITE_B16, +amdgpu_gfx90a_op_DS_WRITE_B16_D16_HI, +amdgpu_gfx90a_op_DS_WRITE_B32, +amdgpu_gfx90a_op_DS_WRITE_B64, +amdgpu_gfx90a_op_DS_WRITE_B8, +amdgpu_gfx90a_op_DS_WRITE_B8_D16_HI, +amdgpu_gfx90a_op_DS_WRITE_B96, +amdgpu_gfx90a_op_DS_WRXCHG2ST64_RTN_B32, +amdgpu_gfx90a_op_DS_WRXCHG2ST64_RTN_B64, +amdgpu_gfx90a_op_DS_WRXCHG2_RTN_B32, +amdgpu_gfx90a_op_DS_WRXCHG2_RTN_B64, +amdgpu_gfx90a_op_DS_WRXCHG_RTN_B32, +amdgpu_gfx90a_op_DS_WRXCHG_RTN_B64, +amdgpu_gfx90a_op_DS_XOR_B32, +amdgpu_gfx90a_op_DS_XOR_B64, +amdgpu_gfx90a_op_DS_XOR_RTN_B32, +amdgpu_gfx90a_op_DS_XOR_RTN_B64, +amdgpu_gfx90a_op_FLAT_ATOMIC_ADD, +amdgpu_gfx90a_op_FLAT_ATOMIC_ADD_F64, +amdgpu_gfx90a_op_FLAT_ATOMIC_ADD_X2, +amdgpu_gfx90a_op_FLAT_ATOMIC_AND, +amdgpu_gfx90a_op_FLAT_ATOMIC_AND_X2, +amdgpu_gfx90a_op_FLAT_ATOMIC_CMPSWAP, +amdgpu_gfx90a_op_FLAT_ATOMIC_CMPSWAP_X2, +amdgpu_gfx90a_op_FLAT_ATOMIC_DEC, +amdgpu_gfx90a_op_FLAT_ATOMIC_DEC_X2, +amdgpu_gfx90a_op_FLAT_ATOMIC_INC, +amdgpu_gfx90a_op_FLAT_ATOMIC_INC_X2, +amdgpu_gfx90a_op_FLAT_ATOMIC_MAX_F64, +amdgpu_gfx90a_op_FLAT_ATOMIC_MIN_F64, +amdgpu_gfx90a_op_FLAT_ATOMIC_OR, +amdgpu_gfx90a_op_FLAT_ATOMIC_OR_X2, +amdgpu_gfx90a_op_FLAT_ATOMIC_SMAX, +amdgpu_gfx90a_op_FLAT_ATOMIC_SMAX_X2, +amdgpu_gfx90a_op_FLAT_ATOMIC_SMIN, +amdgpu_gfx90a_op_FLAT_ATOMIC_SMIN_X2, +amdgpu_gfx90a_op_FLAT_ATOMIC_SUB, +amdgpu_gfx90a_op_FLAT_ATOMIC_SUB_X2, +amdgpu_gfx90a_op_FLAT_ATOMIC_SWAP, +amdgpu_gfx90a_op_FLAT_ATOMIC_SWAP_X2, +amdgpu_gfx90a_op_FLAT_ATOMIC_UMAX, +amdgpu_gfx90a_op_FLAT_ATOMIC_UMAX_X2, +amdgpu_gfx90a_op_FLAT_ATOMIC_UMIN, +amdgpu_gfx90a_op_FLAT_ATOMIC_UMIN_X2, +amdgpu_gfx90a_op_FLAT_ATOMIC_XOR, +amdgpu_gfx90a_op_FLAT_ATOMIC_XOR_X2, +amdgpu_gfx90a_op_FLAT_LOAD_DWORD, +amdgpu_gfx90a_op_FLAT_LOAD_DWORDX2, +amdgpu_gfx90a_op_FLAT_LOAD_DWORDX3, +amdgpu_gfx90a_op_FLAT_LOAD_DWORDX4, +amdgpu_gfx90a_op_FLAT_LOAD_SBYTE, +amdgpu_gfx90a_op_FLAT_LOAD_SBYTE_D16, +amdgpu_gfx90a_op_FLAT_LOAD_SBYTE_D16_HI, +amdgpu_gfx90a_op_FLAT_LOAD_SHORT_D16, +amdgpu_gfx90a_op_FLAT_LOAD_SHORT_D16_HI, +amdgpu_gfx90a_op_FLAT_LOAD_SSHORT, +amdgpu_gfx90a_op_FLAT_LOAD_UBYTE, +amdgpu_gfx90a_op_FLAT_LOAD_UBYTE_D16, +amdgpu_gfx90a_op_FLAT_LOAD_UBYTE_D16_HI, +amdgpu_gfx90a_op_FLAT_LOAD_USHORT, +amdgpu_gfx90a_op_FLAT_STORE_BYTE, +amdgpu_gfx90a_op_FLAT_STORE_BYTE_D16_HI, +amdgpu_gfx90a_op_FLAT_STORE_DWORD, +amdgpu_gfx90a_op_FLAT_STORE_DWORDX2, +amdgpu_gfx90a_op_FLAT_STORE_DWORDX3, +amdgpu_gfx90a_op_FLAT_STORE_DWORDX4, +amdgpu_gfx90a_op_FLAT_STORE_SHORT, +amdgpu_gfx90a_op_FLAT_STORE_SHORT_D16_HI, +amdgpu_gfx90a_op_GLOBAL_ATOMIC_ADD, +amdgpu_gfx90a_op_GLOBAL_ATOMIC_ADD_F32, +amdgpu_gfx90a_op_GLOBAL_ATOMIC_ADD_F64, +amdgpu_gfx90a_op_GLOBAL_ATOMIC_ADD_X2, +amdgpu_gfx90a_op_GLOBAL_ATOMIC_AND, +amdgpu_gfx90a_op_GLOBAL_ATOMIC_AND_X2, +amdgpu_gfx90a_op_GLOBAL_ATOMIC_CMPSWAP, +amdgpu_gfx90a_op_GLOBAL_ATOMIC_CMPSWAP_X2, +amdgpu_gfx90a_op_GLOBAL_ATOMIC_DEC, +amdgpu_gfx90a_op_GLOBAL_ATOMIC_DEC_X2, +amdgpu_gfx90a_op_GLOBAL_ATOMIC_INC, +amdgpu_gfx90a_op_GLOBAL_ATOMIC_INC_X2, +amdgpu_gfx90a_op_GLOBAL_ATOMIC_MAX_F64, +amdgpu_gfx90a_op_GLOBAL_ATOMIC_MIN_F64, +amdgpu_gfx90a_op_GLOBAL_ATOMIC_OR, +amdgpu_gfx90a_op_GLOBAL_ATOMIC_OR_X2, +amdgpu_gfx90a_op_GLOBAL_ATOMIC_PK_ADD_F16, +amdgpu_gfx90a_op_GLOBAL_ATOMIC_SMAX, +amdgpu_gfx90a_op_GLOBAL_ATOMIC_SMAX_X2, +amdgpu_gfx90a_op_GLOBAL_ATOMIC_SMIN, +amdgpu_gfx90a_op_GLOBAL_ATOMIC_SMIN_X2, +amdgpu_gfx90a_op_GLOBAL_ATOMIC_SUB, +amdgpu_gfx90a_op_GLOBAL_ATOMIC_SUB_X2, +amdgpu_gfx90a_op_GLOBAL_ATOMIC_SWAP, +amdgpu_gfx90a_op_GLOBAL_ATOMIC_SWAP_X2, +amdgpu_gfx90a_op_GLOBAL_ATOMIC_UMAX, +amdgpu_gfx90a_op_GLOBAL_ATOMIC_UMAX_X2, +amdgpu_gfx90a_op_GLOBAL_ATOMIC_UMIN, +amdgpu_gfx90a_op_GLOBAL_ATOMIC_UMIN_X2, +amdgpu_gfx90a_op_GLOBAL_ATOMIC_XOR, +amdgpu_gfx90a_op_GLOBAL_ATOMIC_XOR_X2, +amdgpu_gfx90a_op_GLOBAL_LOAD_DWORD, +amdgpu_gfx90a_op_GLOBAL_LOAD_DWORDX2, +amdgpu_gfx90a_op_GLOBAL_LOAD_DWORDX3, +amdgpu_gfx90a_op_GLOBAL_LOAD_DWORDX4, +amdgpu_gfx90a_op_GLOBAL_LOAD_SBYTE, +amdgpu_gfx90a_op_GLOBAL_LOAD_SBYTE_D16, +amdgpu_gfx90a_op_GLOBAL_LOAD_SBYTE_D16_HI, +amdgpu_gfx90a_op_GLOBAL_LOAD_SHORT_D16, +amdgpu_gfx90a_op_GLOBAL_LOAD_SHORT_D16_HI, +amdgpu_gfx90a_op_GLOBAL_LOAD_SSHORT, +amdgpu_gfx90a_op_GLOBAL_LOAD_UBYTE, +amdgpu_gfx90a_op_GLOBAL_LOAD_UBYTE_D16, +amdgpu_gfx90a_op_GLOBAL_LOAD_UBYTE_D16_HI, +amdgpu_gfx90a_op_GLOBAL_LOAD_USHORT, +amdgpu_gfx90a_op_GLOBAL_STORE_BYTE, +amdgpu_gfx90a_op_GLOBAL_STORE_BYTE_D16_HI, +amdgpu_gfx90a_op_GLOBAL_STORE_DWORD, +amdgpu_gfx90a_op_GLOBAL_STORE_DWORDX2, +amdgpu_gfx90a_op_GLOBAL_STORE_DWORDX3, +amdgpu_gfx90a_op_GLOBAL_STORE_DWORDX4, +amdgpu_gfx90a_op_GLOBAL_STORE_SHORT, +amdgpu_gfx90a_op_GLOBAL_STORE_SHORT_D16_HI, +amdgpu_gfx90a_op_IMAGE_ATOMIC_ADD, +amdgpu_gfx90a_op_IMAGE_ATOMIC_AND, +amdgpu_gfx90a_op_IMAGE_ATOMIC_CMPSWAP, +amdgpu_gfx90a_op_IMAGE_ATOMIC_DEC, +amdgpu_gfx90a_op_IMAGE_ATOMIC_INC, +amdgpu_gfx90a_op_IMAGE_ATOMIC_OR, +amdgpu_gfx90a_op_IMAGE_ATOMIC_SMAX, +amdgpu_gfx90a_op_IMAGE_ATOMIC_SMIN, +amdgpu_gfx90a_op_IMAGE_ATOMIC_SUB, +amdgpu_gfx90a_op_IMAGE_ATOMIC_SWAP, +amdgpu_gfx90a_op_IMAGE_ATOMIC_UMAX, +amdgpu_gfx90a_op_IMAGE_ATOMIC_UMIN, +amdgpu_gfx90a_op_IMAGE_ATOMIC_XOR, +amdgpu_gfx90a_op_IMAGE_GET_RESINFO, +amdgpu_gfx90a_op_IMAGE_LOAD, +amdgpu_gfx90a_op_IMAGE_LOAD_MIP, +amdgpu_gfx90a_op_IMAGE_LOAD_MIP_PCK, +amdgpu_gfx90a_op_IMAGE_LOAD_MIP_PCK_SGN, +amdgpu_gfx90a_op_IMAGE_LOAD_PCK, +amdgpu_gfx90a_op_IMAGE_LOAD_PCK_SGN, +amdgpu_gfx90a_op_IMAGE_SAMPLE, +amdgpu_gfx90a_op_IMAGE_STORE, +amdgpu_gfx90a_op_IMAGE_STORE_MIP, +amdgpu_gfx90a_op_IMAGE_STORE_MIP_PCK, +amdgpu_gfx90a_op_IMAGE_STORE_PCK, +amdgpu_gfx90a_op_SCRATCH_LOAD_DWORD, +amdgpu_gfx90a_op_SCRATCH_LOAD_DWORDX2, +amdgpu_gfx90a_op_SCRATCH_LOAD_DWORDX3, +amdgpu_gfx90a_op_SCRATCH_LOAD_DWORDX4, +amdgpu_gfx90a_op_SCRATCH_LOAD_SBYTE, +amdgpu_gfx90a_op_SCRATCH_LOAD_SBYTE_D16, +amdgpu_gfx90a_op_SCRATCH_LOAD_SBYTE_D16_HI, +amdgpu_gfx90a_op_SCRATCH_LOAD_SHORT_D16, +amdgpu_gfx90a_op_SCRATCH_LOAD_SHORT_D16_HI, +amdgpu_gfx90a_op_SCRATCH_LOAD_SSHORT, +amdgpu_gfx90a_op_SCRATCH_LOAD_UBYTE, +amdgpu_gfx90a_op_SCRATCH_LOAD_UBYTE_D16, +amdgpu_gfx90a_op_SCRATCH_LOAD_UBYTE_D16_HI, +amdgpu_gfx90a_op_SCRATCH_LOAD_USHORT, +amdgpu_gfx90a_op_SCRATCH_STORE_BYTE, +amdgpu_gfx90a_op_SCRATCH_STORE_BYTE_D16_HI, +amdgpu_gfx90a_op_SCRATCH_STORE_DWORD, +amdgpu_gfx90a_op_SCRATCH_STORE_DWORDX2, +amdgpu_gfx90a_op_SCRATCH_STORE_DWORDX3, +amdgpu_gfx90a_op_SCRATCH_STORE_DWORDX4, +amdgpu_gfx90a_op_SCRATCH_STORE_SHORT, +amdgpu_gfx90a_op_SCRATCH_STORE_SHORT_D16_HI, +amdgpu_gfx90a_op_S_ABSDIFF_I32, +amdgpu_gfx90a_op_S_ABS_I32, +amdgpu_gfx90a_op_S_ADDC_U32, +amdgpu_gfx90a_op_S_ADDK_I32, +amdgpu_gfx90a_op_S_ADD_I32, +amdgpu_gfx90a_op_S_ADD_U32, +amdgpu_gfx90a_op_S_ANDN1_SAVEEXEC_B64, +amdgpu_gfx90a_op_S_ANDN1_WREXEC_B64, +amdgpu_gfx90a_op_S_ANDN2_B32, +amdgpu_gfx90a_op_S_ANDN2_B64, +amdgpu_gfx90a_op_S_ANDN2_SAVEEXEC_B64, +amdgpu_gfx90a_op_S_ANDN2_WREXEC_B64, +amdgpu_gfx90a_op_S_AND_B32, +amdgpu_gfx90a_op_S_AND_B64, +amdgpu_gfx90a_op_S_AND_SAVEEXEC_B64, +amdgpu_gfx90a_op_S_ASHR_I32, +amdgpu_gfx90a_op_S_ASHR_I64, +amdgpu_gfx90a_op_S_ATC_PROBE, +amdgpu_gfx90a_op_S_ATC_PROBE_BUFFER, +amdgpu_gfx90a_op_S_ATOMIC_ADD, +amdgpu_gfx90a_op_S_ATOMIC_ADD_X2, +amdgpu_gfx90a_op_S_ATOMIC_AND, +amdgpu_gfx90a_op_S_ATOMIC_AND_X2, +amdgpu_gfx90a_op_S_ATOMIC_CMPSWAP, +amdgpu_gfx90a_op_S_ATOMIC_CMPSWAP_X2, +amdgpu_gfx90a_op_S_ATOMIC_DEC, +amdgpu_gfx90a_op_S_ATOMIC_DEC_X2, +amdgpu_gfx90a_op_S_ATOMIC_INC, +amdgpu_gfx90a_op_S_ATOMIC_INC_X2, +amdgpu_gfx90a_op_S_ATOMIC_OR, +amdgpu_gfx90a_op_S_ATOMIC_OR_X2, +amdgpu_gfx90a_op_S_ATOMIC_SMAX, +amdgpu_gfx90a_op_S_ATOMIC_SMAX_X2, +amdgpu_gfx90a_op_S_ATOMIC_SMIN, +amdgpu_gfx90a_op_S_ATOMIC_SMIN_X2, +amdgpu_gfx90a_op_S_ATOMIC_SUB, +amdgpu_gfx90a_op_S_ATOMIC_SUB_X2, +amdgpu_gfx90a_op_S_ATOMIC_SWAP, +amdgpu_gfx90a_op_S_ATOMIC_SWAP_X2, +amdgpu_gfx90a_op_S_ATOMIC_UMAX, +amdgpu_gfx90a_op_S_ATOMIC_UMAX_X2, +amdgpu_gfx90a_op_S_ATOMIC_UMIN, +amdgpu_gfx90a_op_S_ATOMIC_UMIN_X2, +amdgpu_gfx90a_op_S_ATOMIC_XOR, +amdgpu_gfx90a_op_S_ATOMIC_XOR_X2, +amdgpu_gfx90a_op_S_BARRIER, +amdgpu_gfx90a_op_S_BCNT0_I32_B32, +amdgpu_gfx90a_op_S_BCNT0_I32_B64, +amdgpu_gfx90a_op_S_BCNT1_I32_B32, +amdgpu_gfx90a_op_S_BCNT1_I32_B64, +amdgpu_gfx90a_op_S_BFE_I32, +amdgpu_gfx90a_op_S_BFE_I64, +amdgpu_gfx90a_op_S_BFE_U32, +amdgpu_gfx90a_op_S_BFE_U64, +amdgpu_gfx90a_op_S_BFM_B32, +amdgpu_gfx90a_op_S_BFM_B64, +amdgpu_gfx90a_op_S_BITCMP0_B32, +amdgpu_gfx90a_op_S_BITCMP0_B64, +amdgpu_gfx90a_op_S_BITCMP1_B32, +amdgpu_gfx90a_op_S_BITCMP1_B64, +amdgpu_gfx90a_op_S_BITREPLICATE_B64_B32, +amdgpu_gfx90a_op_S_BITSET0_B32, +amdgpu_gfx90a_op_S_BITSET0_B64, +amdgpu_gfx90a_op_S_BITSET1_B32, +amdgpu_gfx90a_op_S_BITSET1_B64, +amdgpu_gfx90a_op_S_BRANCH, +amdgpu_gfx90a_op_S_BREV_B32, +amdgpu_gfx90a_op_S_BREV_B64, +amdgpu_gfx90a_op_S_BUFFER_ATOMIC_ADD, +amdgpu_gfx90a_op_S_BUFFER_ATOMIC_ADD_X2, +amdgpu_gfx90a_op_S_BUFFER_ATOMIC_AND, +amdgpu_gfx90a_op_S_BUFFER_ATOMIC_AND_X2, +amdgpu_gfx90a_op_S_BUFFER_ATOMIC_CMPSWAP, +amdgpu_gfx90a_op_S_BUFFER_ATOMIC_CMPSWAP_X2, +amdgpu_gfx90a_op_S_BUFFER_ATOMIC_DEC, +amdgpu_gfx90a_op_S_BUFFER_ATOMIC_DEC_X2, +amdgpu_gfx90a_op_S_BUFFER_ATOMIC_INC, +amdgpu_gfx90a_op_S_BUFFER_ATOMIC_INC_X2, +amdgpu_gfx90a_op_S_BUFFER_ATOMIC_OR, +amdgpu_gfx90a_op_S_BUFFER_ATOMIC_OR_X2, +amdgpu_gfx90a_op_S_BUFFER_ATOMIC_SMAX, +amdgpu_gfx90a_op_S_BUFFER_ATOMIC_SMAX_X2, +amdgpu_gfx90a_op_S_BUFFER_ATOMIC_SMIN, +amdgpu_gfx90a_op_S_BUFFER_ATOMIC_SMIN_X2, +amdgpu_gfx90a_op_S_BUFFER_ATOMIC_SUB, +amdgpu_gfx90a_op_S_BUFFER_ATOMIC_SUB_X2, +amdgpu_gfx90a_op_S_BUFFER_ATOMIC_SWAP, +amdgpu_gfx90a_op_S_BUFFER_ATOMIC_SWAP_X2, +amdgpu_gfx90a_op_S_BUFFER_ATOMIC_UMAX, +amdgpu_gfx90a_op_S_BUFFER_ATOMIC_UMAX_X2, +amdgpu_gfx90a_op_S_BUFFER_ATOMIC_UMIN, +amdgpu_gfx90a_op_S_BUFFER_ATOMIC_UMIN_X2, +amdgpu_gfx90a_op_S_BUFFER_ATOMIC_XOR, +amdgpu_gfx90a_op_S_BUFFER_ATOMIC_XOR_X2, +amdgpu_gfx90a_op_S_BUFFER_LOAD_DWORD, +amdgpu_gfx90a_op_S_BUFFER_LOAD_DWORDX16, +amdgpu_gfx90a_op_S_BUFFER_LOAD_DWORDX2, +amdgpu_gfx90a_op_S_BUFFER_LOAD_DWORDX4, +amdgpu_gfx90a_op_S_BUFFER_LOAD_DWORDX8, +amdgpu_gfx90a_op_S_BUFFER_STORE_DWORD, +amdgpu_gfx90a_op_S_BUFFER_STORE_DWORDX2, +amdgpu_gfx90a_op_S_BUFFER_STORE_DWORDX4, +amdgpu_gfx90a_op_S_CALL_B64, +amdgpu_gfx90a_op_S_CBRANCH_CDBGSYS, +amdgpu_gfx90a_op_S_CBRANCH_CDBGSYS_AND_USER, +amdgpu_gfx90a_op_S_CBRANCH_CDBGSYS_OR_USER, +amdgpu_gfx90a_op_S_CBRANCH_CDBGUSER, +amdgpu_gfx90a_op_S_CBRANCH_EXECNZ, +amdgpu_gfx90a_op_S_CBRANCH_EXECZ, +amdgpu_gfx90a_op_S_CBRANCH_G_FORK, +amdgpu_gfx90a_op_S_CBRANCH_I_FORK, +amdgpu_gfx90a_op_S_CBRANCH_JOIN, +amdgpu_gfx90a_op_S_CBRANCH_SCC0, +amdgpu_gfx90a_op_S_CBRANCH_SCC1, +amdgpu_gfx90a_op_S_CBRANCH_VCCNZ, +amdgpu_gfx90a_op_S_CBRANCH_VCCZ, +amdgpu_gfx90a_op_S_CMOVK_I32, +amdgpu_gfx90a_op_S_CMOV_B32, +amdgpu_gfx90a_op_S_CMOV_B64, +amdgpu_gfx90a_op_S_CMPK_EQ_I32, +amdgpu_gfx90a_op_S_CMPK_EQ_U32, +amdgpu_gfx90a_op_S_CMPK_GE_I32, +amdgpu_gfx90a_op_S_CMPK_GE_U32, +amdgpu_gfx90a_op_S_CMPK_GT_I32, +amdgpu_gfx90a_op_S_CMPK_GT_U32, +amdgpu_gfx90a_op_S_CMPK_LE_I32, +amdgpu_gfx90a_op_S_CMPK_LE_U32, +amdgpu_gfx90a_op_S_CMPK_LG_I32, +amdgpu_gfx90a_op_S_CMPK_LG_U32, +amdgpu_gfx90a_op_S_CMPK_LT_I32, +amdgpu_gfx90a_op_S_CMPK_LT_U32, +amdgpu_gfx90a_op_S_CMP_EQ_I32, +amdgpu_gfx90a_op_S_CMP_EQ_U32, +amdgpu_gfx90a_op_S_CMP_EQ_U64, +amdgpu_gfx90a_op_S_CMP_GE_I32, +amdgpu_gfx90a_op_S_CMP_GE_U32, +amdgpu_gfx90a_op_S_CMP_GT_I32, +amdgpu_gfx90a_op_S_CMP_GT_U32, +amdgpu_gfx90a_op_S_CMP_LE_I32, +amdgpu_gfx90a_op_S_CMP_LE_U32, +amdgpu_gfx90a_op_S_CMP_LG_I32, +amdgpu_gfx90a_op_S_CMP_LG_U32, +amdgpu_gfx90a_op_S_CMP_LG_U64, +amdgpu_gfx90a_op_S_CMP_LT_I32, +amdgpu_gfx90a_op_S_CMP_LT_U32, +amdgpu_gfx90a_op_S_CSELECT_B32, +amdgpu_gfx90a_op_S_CSELECT_B64, +amdgpu_gfx90a_op_S_DCACHE_DISCARD, +amdgpu_gfx90a_op_S_DCACHE_DISCARD_X2, +amdgpu_gfx90a_op_S_DCACHE_INV, +amdgpu_gfx90a_op_S_DCACHE_INV_VOL, +amdgpu_gfx90a_op_S_DCACHE_WB, +amdgpu_gfx90a_op_S_DCACHE_WB_VOL, +amdgpu_gfx90a_op_S_DECPERFLEVEL, +amdgpu_gfx90a_op_S_ENDPGM, +amdgpu_gfx90a_op_S_ENDPGM_ORDERED_PS_DONE, +amdgpu_gfx90a_op_S_ENDPGM_SAVED, +amdgpu_gfx90a_op_S_FF0_I32_B32, +amdgpu_gfx90a_op_S_FF0_I32_B64, +amdgpu_gfx90a_op_S_FF1_I32_B32, +amdgpu_gfx90a_op_S_FF1_I32_B64, +amdgpu_gfx90a_op_S_FLBIT_I32, +amdgpu_gfx90a_op_S_FLBIT_I32_B32, +amdgpu_gfx90a_op_S_FLBIT_I32_B64, +amdgpu_gfx90a_op_S_FLBIT_I32_I64, +amdgpu_gfx90a_op_S_GETPC_B64, +amdgpu_gfx90a_op_S_GETREG_B32, +amdgpu_gfx90a_op_S_ICACHE_INV, +amdgpu_gfx90a_op_S_INCPERFLEVEL, +amdgpu_gfx90a_op_S_LOAD_DWORD, +amdgpu_gfx90a_op_S_LOAD_DWORDX16, +amdgpu_gfx90a_op_S_LOAD_DWORDX2, +amdgpu_gfx90a_op_S_LOAD_DWORDX4, +amdgpu_gfx90a_op_S_LOAD_DWORDX8, +amdgpu_gfx90a_op_S_LSHL1_ADD_U32, +amdgpu_gfx90a_op_S_LSHL2_ADD_U32, +amdgpu_gfx90a_op_S_LSHL3_ADD_U32, +amdgpu_gfx90a_op_S_LSHL4_ADD_U32, +amdgpu_gfx90a_op_S_LSHL_B32, +amdgpu_gfx90a_op_S_LSHL_B64, +amdgpu_gfx90a_op_S_LSHR_B32, +amdgpu_gfx90a_op_S_LSHR_B64, +amdgpu_gfx90a_op_S_MAX_I32, +amdgpu_gfx90a_op_S_MAX_U32, +amdgpu_gfx90a_op_S_MEMREALTIME, +amdgpu_gfx90a_op_S_MEMTIME, +amdgpu_gfx90a_op_S_MIN_I32, +amdgpu_gfx90a_op_S_MIN_U32, +amdgpu_gfx90a_op_S_MOVK_I32, +amdgpu_gfx90a_op_S_MOVRELD_B32, +amdgpu_gfx90a_op_S_MOVRELD_B64, +amdgpu_gfx90a_op_S_MOVRELS_B32, +amdgpu_gfx90a_op_S_MOVRELS_B64, +amdgpu_gfx90a_op_S_MOV_B32, +amdgpu_gfx90a_op_S_MOV_B64, +amdgpu_gfx90a_op_S_MULK_I32, +amdgpu_gfx90a_op_S_MUL_HI_I32, +amdgpu_gfx90a_op_S_MUL_HI_U32, +amdgpu_gfx90a_op_S_MUL_I32, +amdgpu_gfx90a_op_S_NAND_B32, +amdgpu_gfx90a_op_S_NAND_B64, +amdgpu_gfx90a_op_S_NAND_SAVEEXEC_B64, +amdgpu_gfx90a_op_S_NOP, +amdgpu_gfx90a_op_S_NOR_B32, +amdgpu_gfx90a_op_S_NOR_B64, +amdgpu_gfx90a_op_S_NOR_SAVEEXEC_B64, +amdgpu_gfx90a_op_S_NOT_B32, +amdgpu_gfx90a_op_S_NOT_B64, +amdgpu_gfx90a_op_S_ORN1_SAVEEXEC_B64, +amdgpu_gfx90a_op_S_ORN2_B32, +amdgpu_gfx90a_op_S_ORN2_B64, +amdgpu_gfx90a_op_S_ORN2_SAVEEXEC_B64, +amdgpu_gfx90a_op_S_OR_B32, +amdgpu_gfx90a_op_S_OR_B64, +amdgpu_gfx90a_op_S_OR_SAVEEXEC_B64, +amdgpu_gfx90a_op_S_PACK_HH_B32_B16, +amdgpu_gfx90a_op_S_PACK_LH_B32_B16, +amdgpu_gfx90a_op_S_PACK_LL_B32_B16, +amdgpu_gfx90a_op_S_QUADMASK_B32, +amdgpu_gfx90a_op_S_QUADMASK_B64, +amdgpu_gfx90a_op_S_RFE_B64, +amdgpu_gfx90a_op_S_RFE_RESTORE_B64, +amdgpu_gfx90a_op_S_SCRATCH_LOAD_DWORD, +amdgpu_gfx90a_op_S_SCRATCH_LOAD_DWORDX2, +amdgpu_gfx90a_op_S_SCRATCH_LOAD_DWORDX4, +amdgpu_gfx90a_op_S_SCRATCH_STORE_DWORD, +amdgpu_gfx90a_op_S_SCRATCH_STORE_DWORDX2, +amdgpu_gfx90a_op_S_SCRATCH_STORE_DWORDX4, +amdgpu_gfx90a_op_S_SENDMSG, +amdgpu_gfx90a_op_S_SENDMSGHALT, +amdgpu_gfx90a_op_S_SETHALT, +amdgpu_gfx90a_op_S_SETKILL, +amdgpu_gfx90a_op_S_SETPC_B64, +amdgpu_gfx90a_op_S_SETPRIO, +amdgpu_gfx90a_op_S_SETREG_B32, +amdgpu_gfx90a_op_S_SETREG_IMM32_B32, +amdgpu_gfx90a_op_S_SETVSKIP, +amdgpu_gfx90a_op_S_SET_GPR_IDX_IDX, +amdgpu_gfx90a_op_S_SET_GPR_IDX_MODE, +amdgpu_gfx90a_op_S_SET_GPR_IDX_OFF, +amdgpu_gfx90a_op_S_SET_GPR_IDX_ON, +amdgpu_gfx90a_op_S_SEXT_I32_I16, +amdgpu_gfx90a_op_S_SEXT_I32_I8, +amdgpu_gfx90a_op_S_SLEEP, +amdgpu_gfx90a_op_S_STORE_DWORD, +amdgpu_gfx90a_op_S_STORE_DWORDX2, +amdgpu_gfx90a_op_S_STORE_DWORDX4, +amdgpu_gfx90a_op_S_SUBB_U32, +amdgpu_gfx90a_op_S_SUB_I32, +amdgpu_gfx90a_op_S_SUB_U32, +amdgpu_gfx90a_op_S_SWAPPC_B64, +amdgpu_gfx90a_op_S_TRAP, +amdgpu_gfx90a_op_S_TTRACEDATA, +amdgpu_gfx90a_op_S_WAITCNT, +amdgpu_gfx90a_op_S_WAKEUP, +amdgpu_gfx90a_op_S_WQM_B32, +amdgpu_gfx90a_op_S_WQM_B64, +amdgpu_gfx90a_op_S_XNOR_B32, +amdgpu_gfx90a_op_S_XNOR_B64, +amdgpu_gfx90a_op_S_XNOR_SAVEEXEC_B64, +amdgpu_gfx90a_op_S_XOR_B32, +amdgpu_gfx90a_op_S_XOR_B64, +amdgpu_gfx90a_op_S_XOR_SAVEEXEC_B64, +amdgpu_gfx90a_op_TBUFFER_LOAD_FORMAT_D16_X, +amdgpu_gfx90a_op_TBUFFER_LOAD_FORMAT_D16_XY, +amdgpu_gfx90a_op_TBUFFER_LOAD_FORMAT_D16_XYZ, +amdgpu_gfx90a_op_TBUFFER_LOAD_FORMAT_D16_XYZW, +amdgpu_gfx90a_op_TBUFFER_LOAD_FORMAT_X, +amdgpu_gfx90a_op_TBUFFER_LOAD_FORMAT_XY, +amdgpu_gfx90a_op_TBUFFER_LOAD_FORMAT_XYZ, +amdgpu_gfx90a_op_TBUFFER_LOAD_FORMAT_XYZW, +amdgpu_gfx90a_op_TBUFFER_STORE_FORMAT_D16_X, +amdgpu_gfx90a_op_TBUFFER_STORE_FORMAT_D16_XY, +amdgpu_gfx90a_op_TBUFFER_STORE_FORMAT_D16_XYZ, +amdgpu_gfx90a_op_TBUFFER_STORE_FORMAT_D16_XYZW, +amdgpu_gfx90a_op_TBUFFER_STORE_FORMAT_X, +amdgpu_gfx90a_op_TBUFFER_STORE_FORMAT_XY, +amdgpu_gfx90a_op_TBUFFER_STORE_FORMAT_XYZ, +amdgpu_gfx90a_op_TBUFFER_STORE_FORMAT_XYZW, +amdgpu_gfx90a_op_V_ACCVGPR_MOV_B32, +amdgpu_gfx90a_op_V_ACCVGPR_READ, +amdgpu_gfx90a_op_V_ACCVGPR_WRITE, +amdgpu_gfx90a_op_V_ADD3_U32, +amdgpu_gfx90a_op_V_ADDC_CO_U32, +amdgpu_gfx90a_op_V_ADD_CO_U32, +amdgpu_gfx90a_op_V_ADD_F16, +amdgpu_gfx90a_op_V_ADD_F32, +amdgpu_gfx90a_op_V_ADD_F64, +amdgpu_gfx90a_op_V_ADD_I16, +amdgpu_gfx90a_op_V_ADD_I32, +amdgpu_gfx90a_op_V_ADD_LSHL_U32, +amdgpu_gfx90a_op_V_ADD_U16, +amdgpu_gfx90a_op_V_ADD_U32, +amdgpu_gfx90a_op_V_ALIGNBIT_B32, +amdgpu_gfx90a_op_V_ALIGNBYTE_B32, +amdgpu_gfx90a_op_V_AND_B32, +amdgpu_gfx90a_op_V_AND_OR_B32, +amdgpu_gfx90a_op_V_ASHRREV_I16, +amdgpu_gfx90a_op_V_ASHRREV_I32, +amdgpu_gfx90a_op_V_ASHRREV_I64, +amdgpu_gfx90a_op_V_BCNT_U32_B32, +amdgpu_gfx90a_op_V_BFE_I32, +amdgpu_gfx90a_op_V_BFE_U32, +amdgpu_gfx90a_op_V_BFI_B32, +amdgpu_gfx90a_op_V_BFM_B32, +amdgpu_gfx90a_op_V_BFREV_B32, +amdgpu_gfx90a_op_V_CEIL_F16, +amdgpu_gfx90a_op_V_CEIL_F32, +amdgpu_gfx90a_op_V_CEIL_F64, +amdgpu_gfx90a_op_V_CLREXCP, +amdgpu_gfx90a_op_V_CMPX_CLASS_F16, +amdgpu_gfx90a_op_V_CMPX_CLASS_F32, +amdgpu_gfx90a_op_V_CMPX_CLASS_F64, +amdgpu_gfx90a_op_V_CMPX_EQ_F16, +amdgpu_gfx90a_op_V_CMPX_EQ_F32, +amdgpu_gfx90a_op_V_CMPX_EQ_F64, +amdgpu_gfx90a_op_V_CMPX_EQ_I16, +amdgpu_gfx90a_op_V_CMPX_EQ_I32, +amdgpu_gfx90a_op_V_CMPX_EQ_I64, +amdgpu_gfx90a_op_V_CMPX_EQ_U16, +amdgpu_gfx90a_op_V_CMPX_EQ_U32, +amdgpu_gfx90a_op_V_CMPX_EQ_U64, +amdgpu_gfx90a_op_V_CMPX_F_F16, +amdgpu_gfx90a_op_V_CMPX_F_F32, +amdgpu_gfx90a_op_V_CMPX_F_F64, +amdgpu_gfx90a_op_V_CMPX_F_I16, +amdgpu_gfx90a_op_V_CMPX_F_I32, +amdgpu_gfx90a_op_V_CMPX_F_I64, +amdgpu_gfx90a_op_V_CMPX_F_U16, +amdgpu_gfx90a_op_V_CMPX_F_U32, +amdgpu_gfx90a_op_V_CMPX_F_U64, +amdgpu_gfx90a_op_V_CMPX_GE_F16, +amdgpu_gfx90a_op_V_CMPX_GE_F32, +amdgpu_gfx90a_op_V_CMPX_GE_F64, +amdgpu_gfx90a_op_V_CMPX_GE_I16, +amdgpu_gfx90a_op_V_CMPX_GE_I32, +amdgpu_gfx90a_op_V_CMPX_GE_I64, +amdgpu_gfx90a_op_V_CMPX_GE_U16, +amdgpu_gfx90a_op_V_CMPX_GE_U32, +amdgpu_gfx90a_op_V_CMPX_GE_U64, +amdgpu_gfx90a_op_V_CMPX_GT_F16, +amdgpu_gfx90a_op_V_CMPX_GT_F32, +amdgpu_gfx90a_op_V_CMPX_GT_F64, +amdgpu_gfx90a_op_V_CMPX_GT_I16, +amdgpu_gfx90a_op_V_CMPX_GT_I32, +amdgpu_gfx90a_op_V_CMPX_GT_I64, +amdgpu_gfx90a_op_V_CMPX_GT_U16, +amdgpu_gfx90a_op_V_CMPX_GT_U32, +amdgpu_gfx90a_op_V_CMPX_GT_U64, +amdgpu_gfx90a_op_V_CMPX_LE_F16, +amdgpu_gfx90a_op_V_CMPX_LE_F32, +amdgpu_gfx90a_op_V_CMPX_LE_F64, +amdgpu_gfx90a_op_V_CMPX_LE_I16, +amdgpu_gfx90a_op_V_CMPX_LE_I32, +amdgpu_gfx90a_op_V_CMPX_LE_I64, +amdgpu_gfx90a_op_V_CMPX_LE_U16, +amdgpu_gfx90a_op_V_CMPX_LE_U32, +amdgpu_gfx90a_op_V_CMPX_LE_U64, +amdgpu_gfx90a_op_V_CMPX_LG_F16, +amdgpu_gfx90a_op_V_CMPX_LG_F32, +amdgpu_gfx90a_op_V_CMPX_LG_F64, +amdgpu_gfx90a_op_V_CMPX_LT_F16, +amdgpu_gfx90a_op_V_CMPX_LT_F32, +amdgpu_gfx90a_op_V_CMPX_LT_F64, +amdgpu_gfx90a_op_V_CMPX_LT_I16, +amdgpu_gfx90a_op_V_CMPX_LT_I32, +amdgpu_gfx90a_op_V_CMPX_LT_I64, +amdgpu_gfx90a_op_V_CMPX_LT_U16, +amdgpu_gfx90a_op_V_CMPX_LT_U32, +amdgpu_gfx90a_op_V_CMPX_LT_U64, +amdgpu_gfx90a_op_V_CMPX_NEQ_F16, +amdgpu_gfx90a_op_V_CMPX_NEQ_F32, +amdgpu_gfx90a_op_V_CMPX_NEQ_F64, +amdgpu_gfx90a_op_V_CMPX_NE_I16, +amdgpu_gfx90a_op_V_CMPX_NE_I32, +amdgpu_gfx90a_op_V_CMPX_NE_I64, +amdgpu_gfx90a_op_V_CMPX_NE_U16, +amdgpu_gfx90a_op_V_CMPX_NE_U32, +amdgpu_gfx90a_op_V_CMPX_NE_U64, +amdgpu_gfx90a_op_V_CMPX_NGE_F16, +amdgpu_gfx90a_op_V_CMPX_NGE_F32, +amdgpu_gfx90a_op_V_CMPX_NGE_F64, +amdgpu_gfx90a_op_V_CMPX_NGT_F16, +amdgpu_gfx90a_op_V_CMPX_NGT_F32, +amdgpu_gfx90a_op_V_CMPX_NGT_F64, +amdgpu_gfx90a_op_V_CMPX_NLE_F16, +amdgpu_gfx90a_op_V_CMPX_NLE_F32, +amdgpu_gfx90a_op_V_CMPX_NLE_F64, +amdgpu_gfx90a_op_V_CMPX_NLG_F16, +amdgpu_gfx90a_op_V_CMPX_NLG_F32, +amdgpu_gfx90a_op_V_CMPX_NLG_F64, +amdgpu_gfx90a_op_V_CMPX_NLT_F16, +amdgpu_gfx90a_op_V_CMPX_NLT_F32, +amdgpu_gfx90a_op_V_CMPX_NLT_F64, +amdgpu_gfx90a_op_V_CMPX_O_F16, +amdgpu_gfx90a_op_V_CMPX_O_F32, +amdgpu_gfx90a_op_V_CMPX_O_F64, +amdgpu_gfx90a_op_V_CMPX_TRU_F16, +amdgpu_gfx90a_op_V_CMPX_TRU_F32, +amdgpu_gfx90a_op_V_CMPX_TRU_F64, +amdgpu_gfx90a_op_V_CMPX_T_I16, +amdgpu_gfx90a_op_V_CMPX_T_I32, +amdgpu_gfx90a_op_V_CMPX_T_I64, +amdgpu_gfx90a_op_V_CMPX_T_U16, +amdgpu_gfx90a_op_V_CMPX_T_U32, +amdgpu_gfx90a_op_V_CMPX_T_U64, +amdgpu_gfx90a_op_V_CMPX_U_F16, +amdgpu_gfx90a_op_V_CMPX_U_F32, +amdgpu_gfx90a_op_V_CMPX_U_F64, +amdgpu_gfx90a_op_V_CMP_CLASS_F16, +amdgpu_gfx90a_op_V_CMP_CLASS_F32, +amdgpu_gfx90a_op_V_CMP_CLASS_F64, +amdgpu_gfx90a_op_V_CMP_EQ_F16, +amdgpu_gfx90a_op_V_CMP_EQ_F32, +amdgpu_gfx90a_op_V_CMP_EQ_F64, +amdgpu_gfx90a_op_V_CMP_EQ_I16, +amdgpu_gfx90a_op_V_CMP_EQ_I32, +amdgpu_gfx90a_op_V_CMP_EQ_I64, +amdgpu_gfx90a_op_V_CMP_EQ_U16, +amdgpu_gfx90a_op_V_CMP_EQ_U32, +amdgpu_gfx90a_op_V_CMP_EQ_U64, +amdgpu_gfx90a_op_V_CMP_F_F16, +amdgpu_gfx90a_op_V_CMP_F_F32, +amdgpu_gfx90a_op_V_CMP_F_F64, +amdgpu_gfx90a_op_V_CMP_F_I16, +amdgpu_gfx90a_op_V_CMP_F_I32, +amdgpu_gfx90a_op_V_CMP_F_I64, +amdgpu_gfx90a_op_V_CMP_F_U16, +amdgpu_gfx90a_op_V_CMP_F_U32, +amdgpu_gfx90a_op_V_CMP_F_U64, +amdgpu_gfx90a_op_V_CMP_GE_F16, +amdgpu_gfx90a_op_V_CMP_GE_F32, +amdgpu_gfx90a_op_V_CMP_GE_F64, +amdgpu_gfx90a_op_V_CMP_GE_I16, +amdgpu_gfx90a_op_V_CMP_GE_I32, +amdgpu_gfx90a_op_V_CMP_GE_I64, +amdgpu_gfx90a_op_V_CMP_GE_U16, +amdgpu_gfx90a_op_V_CMP_GE_U32, +amdgpu_gfx90a_op_V_CMP_GE_U64, +amdgpu_gfx90a_op_V_CMP_GT_F16, +amdgpu_gfx90a_op_V_CMP_GT_F32, +amdgpu_gfx90a_op_V_CMP_GT_F64, +amdgpu_gfx90a_op_V_CMP_GT_I16, +amdgpu_gfx90a_op_V_CMP_GT_I32, +amdgpu_gfx90a_op_V_CMP_GT_I64, +amdgpu_gfx90a_op_V_CMP_GT_U16, +amdgpu_gfx90a_op_V_CMP_GT_U32, +amdgpu_gfx90a_op_V_CMP_GT_U64, +amdgpu_gfx90a_op_V_CMP_LE_F16, +amdgpu_gfx90a_op_V_CMP_LE_F32, +amdgpu_gfx90a_op_V_CMP_LE_F64, +amdgpu_gfx90a_op_V_CMP_LE_I16, +amdgpu_gfx90a_op_V_CMP_LE_I32, +amdgpu_gfx90a_op_V_CMP_LE_I64, +amdgpu_gfx90a_op_V_CMP_LE_U16, +amdgpu_gfx90a_op_V_CMP_LE_U32, +amdgpu_gfx90a_op_V_CMP_LE_U64, +amdgpu_gfx90a_op_V_CMP_LG_F16, +amdgpu_gfx90a_op_V_CMP_LG_F32, +amdgpu_gfx90a_op_V_CMP_LG_F64, +amdgpu_gfx90a_op_V_CMP_LT_F16, +amdgpu_gfx90a_op_V_CMP_LT_F32, +amdgpu_gfx90a_op_V_CMP_LT_F64, +amdgpu_gfx90a_op_V_CMP_LT_I16, +amdgpu_gfx90a_op_V_CMP_LT_I32, +amdgpu_gfx90a_op_V_CMP_LT_I64, +amdgpu_gfx90a_op_V_CMP_LT_U16, +amdgpu_gfx90a_op_V_CMP_LT_U32, +amdgpu_gfx90a_op_V_CMP_LT_U64, +amdgpu_gfx90a_op_V_CMP_NEQ_F16, +amdgpu_gfx90a_op_V_CMP_NEQ_F32, +amdgpu_gfx90a_op_V_CMP_NEQ_F64, +amdgpu_gfx90a_op_V_CMP_NE_I16, +amdgpu_gfx90a_op_V_CMP_NE_I32, +amdgpu_gfx90a_op_V_CMP_NE_I64, +amdgpu_gfx90a_op_V_CMP_NE_U16, +amdgpu_gfx90a_op_V_CMP_NE_U32, +amdgpu_gfx90a_op_V_CMP_NE_U64, +amdgpu_gfx90a_op_V_CMP_NGE_F16, +amdgpu_gfx90a_op_V_CMP_NGE_F32, +amdgpu_gfx90a_op_V_CMP_NGE_F64, +amdgpu_gfx90a_op_V_CMP_NGT_F16, +amdgpu_gfx90a_op_V_CMP_NGT_F32, +amdgpu_gfx90a_op_V_CMP_NGT_F64, +amdgpu_gfx90a_op_V_CMP_NLE_F16, +amdgpu_gfx90a_op_V_CMP_NLE_F32, +amdgpu_gfx90a_op_V_CMP_NLE_F64, +amdgpu_gfx90a_op_V_CMP_NLG_F16, +amdgpu_gfx90a_op_V_CMP_NLG_F32, +amdgpu_gfx90a_op_V_CMP_NLG_F64, +amdgpu_gfx90a_op_V_CMP_NLT_F16, +amdgpu_gfx90a_op_V_CMP_NLT_F32, +amdgpu_gfx90a_op_V_CMP_NLT_F64, +amdgpu_gfx90a_op_V_CMP_O_F16, +amdgpu_gfx90a_op_V_CMP_O_F32, +amdgpu_gfx90a_op_V_CMP_O_F64, +amdgpu_gfx90a_op_V_CMP_TRU_F16, +amdgpu_gfx90a_op_V_CMP_TRU_F32, +amdgpu_gfx90a_op_V_CMP_TRU_F64, +amdgpu_gfx90a_op_V_CMP_T_I16, +amdgpu_gfx90a_op_V_CMP_T_I32, +amdgpu_gfx90a_op_V_CMP_T_I64, +amdgpu_gfx90a_op_V_CMP_T_U16, +amdgpu_gfx90a_op_V_CMP_T_U32, +amdgpu_gfx90a_op_V_CMP_T_U64, +amdgpu_gfx90a_op_V_CMP_U_F16, +amdgpu_gfx90a_op_V_CMP_U_F32, +amdgpu_gfx90a_op_V_CMP_U_F64, +amdgpu_gfx90a_op_V_CNDMASK_B32, +amdgpu_gfx90a_op_V_COS_F16, +amdgpu_gfx90a_op_V_COS_F32, +amdgpu_gfx90a_op_V_CUBEID_F32, +amdgpu_gfx90a_op_V_CUBEMA_F32, +amdgpu_gfx90a_op_V_CUBESC_F32, +amdgpu_gfx90a_op_V_CUBETC_F32, +amdgpu_gfx90a_op_V_CVT_F16_F32, +amdgpu_gfx90a_op_V_CVT_F16_I16, +amdgpu_gfx90a_op_V_CVT_F16_U16, +amdgpu_gfx90a_op_V_CVT_F32_F16, +amdgpu_gfx90a_op_V_CVT_F32_F64, +amdgpu_gfx90a_op_V_CVT_F32_I32, +amdgpu_gfx90a_op_V_CVT_F32_U32, +amdgpu_gfx90a_op_V_CVT_F32_UBYTE0, +amdgpu_gfx90a_op_V_CVT_F32_UBYTE1, +amdgpu_gfx90a_op_V_CVT_F32_UBYTE2, +amdgpu_gfx90a_op_V_CVT_F32_UBYTE3, +amdgpu_gfx90a_op_V_CVT_F64_F32, +amdgpu_gfx90a_op_V_CVT_F64_I32, +amdgpu_gfx90a_op_V_CVT_F64_U32, +amdgpu_gfx90a_op_V_CVT_FLR_I32_F32, +amdgpu_gfx90a_op_V_CVT_I16_F16, +amdgpu_gfx90a_op_V_CVT_I32_F32, +amdgpu_gfx90a_op_V_CVT_I32_F64, +amdgpu_gfx90a_op_V_CVT_NORM_I16_F16, +amdgpu_gfx90a_op_V_CVT_NORM_U16_F16, +amdgpu_gfx90a_op_V_CVT_OFF_F32_I4, +amdgpu_gfx90a_op_V_CVT_PKACCUM_U8_F32, +amdgpu_gfx90a_op_V_CVT_PKNORM_I16_F16, +amdgpu_gfx90a_op_V_CVT_PKNORM_I16_F32, +amdgpu_gfx90a_op_V_CVT_PKNORM_U16_F16, +amdgpu_gfx90a_op_V_CVT_PKNORM_U16_F32, +amdgpu_gfx90a_op_V_CVT_PKRTZ_F16_F32, +amdgpu_gfx90a_op_V_CVT_PK_I16_I32, +amdgpu_gfx90a_op_V_CVT_PK_U16_U32, +amdgpu_gfx90a_op_V_CVT_PK_U8_F32, +amdgpu_gfx90a_op_V_CVT_RPI_I32_F32, +amdgpu_gfx90a_op_V_CVT_U16_F16, +amdgpu_gfx90a_op_V_CVT_U32_F32, +amdgpu_gfx90a_op_V_CVT_U32_F64, +amdgpu_gfx90a_op_V_DIV_FIXUP_F16, +amdgpu_gfx90a_op_V_DIV_FIXUP_F32, +amdgpu_gfx90a_op_V_DIV_FIXUP_F64, +amdgpu_gfx90a_op_V_DIV_FIXUP_LEGACY_F16, +amdgpu_gfx90a_op_V_DIV_FMAS_F32, +amdgpu_gfx90a_op_V_DIV_FMAS_F64, +amdgpu_gfx90a_op_V_DIV_SCALE_F32, +amdgpu_gfx90a_op_V_DIV_SCALE_F64, +amdgpu_gfx90a_op_V_DOT2C_F32_F16, +amdgpu_gfx90a_op_V_DOT2C_I32_I16, +amdgpu_gfx90a_op_V_DOT2_F32_F16, +amdgpu_gfx90a_op_V_DOT2_I32_I16, +amdgpu_gfx90a_op_V_DOT2_U32_U16, +amdgpu_gfx90a_op_V_DOT4C_I32_I8, +amdgpu_gfx90a_op_V_DOT4_I32_I8, +amdgpu_gfx90a_op_V_DOT4_U32_U8, +amdgpu_gfx90a_op_V_DOT8C_I32_I4, +amdgpu_gfx90a_op_V_DOT8_I32_I4, +amdgpu_gfx90a_op_V_DOT8_U32_U4, +amdgpu_gfx90a_op_V_EXP_F16, +amdgpu_gfx90a_op_V_EXP_F32, +amdgpu_gfx90a_op_V_EXP_LEGACY_F32, +amdgpu_gfx90a_op_V_FFBH_I32, +amdgpu_gfx90a_op_V_FFBH_U32, +amdgpu_gfx90a_op_V_FFBL_B32, +amdgpu_gfx90a_op_V_FLOOR_F16, +amdgpu_gfx90a_op_V_FLOOR_F32, +amdgpu_gfx90a_op_V_FLOOR_F64, +amdgpu_gfx90a_op_V_FMAC_F32, +amdgpu_gfx90a_op_V_FMAC_F64, +amdgpu_gfx90a_op_V_FMA_F16, +amdgpu_gfx90a_op_V_FMA_F32, +amdgpu_gfx90a_op_V_FMA_F64, +amdgpu_gfx90a_op_V_FMA_LEGACY_F16, +amdgpu_gfx90a_op_V_FRACT_F16, +amdgpu_gfx90a_op_V_FRACT_F32, +amdgpu_gfx90a_op_V_FRACT_F64, +amdgpu_gfx90a_op_V_FREXP_EXP_I16_F16, +amdgpu_gfx90a_op_V_FREXP_EXP_I32_F32, +amdgpu_gfx90a_op_V_FREXP_EXP_I32_F64, +amdgpu_gfx90a_op_V_FREXP_MANT_F16, +amdgpu_gfx90a_op_V_FREXP_MANT_F32, +amdgpu_gfx90a_op_V_FREXP_MANT_F64, +amdgpu_gfx90a_op_V_LDEXP_F16, +amdgpu_gfx90a_op_V_LDEXP_F32, +amdgpu_gfx90a_op_V_LDEXP_F64, +amdgpu_gfx90a_op_V_LERP_U8, +amdgpu_gfx90a_op_V_LOG_F16, +amdgpu_gfx90a_op_V_LOG_F32, +amdgpu_gfx90a_op_V_LOG_LEGACY_F32, +amdgpu_gfx90a_op_V_LSHLREV_B16, +amdgpu_gfx90a_op_V_LSHLREV_B32, +amdgpu_gfx90a_op_V_LSHLREV_B64, +amdgpu_gfx90a_op_V_LSHL_ADD_U32, +amdgpu_gfx90a_op_V_LSHL_OR_B32, +amdgpu_gfx90a_op_V_LSHRREV_B16, +amdgpu_gfx90a_op_V_LSHRREV_B32, +amdgpu_gfx90a_op_V_LSHRREV_B64, +amdgpu_gfx90a_op_V_MAC_F16, +amdgpu_gfx90a_op_V_MAC_F32, +amdgpu_gfx90a_op_V_MADAK_F16, +amdgpu_gfx90a_op_V_MADAK_F32, +amdgpu_gfx90a_op_V_MADMK_F16, +amdgpu_gfx90a_op_V_MADMK_F32, +amdgpu_gfx90a_op_V_MAD_F16, +amdgpu_gfx90a_op_V_MAD_F32, +amdgpu_gfx90a_op_V_MAD_I16, +amdgpu_gfx90a_op_V_MAD_I32_I16, +amdgpu_gfx90a_op_V_MAD_I32_I24, +amdgpu_gfx90a_op_V_MAD_I64_I32, +amdgpu_gfx90a_op_V_MAD_LEGACY_F16, +amdgpu_gfx90a_op_V_MAD_LEGACY_F32, +amdgpu_gfx90a_op_V_MAD_LEGACY_I16, +amdgpu_gfx90a_op_V_MAD_LEGACY_U16, +amdgpu_gfx90a_op_V_MAD_MIXHI_F16, +amdgpu_gfx90a_op_V_MAD_MIXLO_F16, +amdgpu_gfx90a_op_V_MAD_MIX_F32, +amdgpu_gfx90a_op_V_MAD_U16, +amdgpu_gfx90a_op_V_MAD_U32_U16, +amdgpu_gfx90a_op_V_MAD_U32_U24, +amdgpu_gfx90a_op_V_MAD_U64_U32, +amdgpu_gfx90a_op_V_MAX3_F16, +amdgpu_gfx90a_op_V_MAX3_F32, +amdgpu_gfx90a_op_V_MAX3_I16, +amdgpu_gfx90a_op_V_MAX3_I32, +amdgpu_gfx90a_op_V_MAX3_U16, +amdgpu_gfx90a_op_V_MAX3_U32, +amdgpu_gfx90a_op_V_MAX_F16, +amdgpu_gfx90a_op_V_MAX_F32, +amdgpu_gfx90a_op_V_MAX_F64, +amdgpu_gfx90a_op_V_MAX_I16, +amdgpu_gfx90a_op_V_MAX_I32, +amdgpu_gfx90a_op_V_MAX_U16, +amdgpu_gfx90a_op_V_MAX_U32, +amdgpu_gfx90a_op_V_MBCNT_HI_U32_B32, +amdgpu_gfx90a_op_V_MBCNT_LO_U32_B32, +amdgpu_gfx90a_op_V_MED3_F16, +amdgpu_gfx90a_op_V_MED3_F32, +amdgpu_gfx90a_op_V_MED3_I16, +amdgpu_gfx90a_op_V_MED3_I32, +amdgpu_gfx90a_op_V_MED3_U16, +amdgpu_gfx90a_op_V_MED3_U32, +amdgpu_gfx90a_op_V_MFMA_F32_16X16X16BF16_1K, +amdgpu_gfx90a_op_V_MFMA_F32_16X16X16F16, +amdgpu_gfx90a_op_V_MFMA_F32_16X16X1F32, +amdgpu_gfx90a_op_V_MFMA_F32_16X16X2BF16, +amdgpu_gfx90a_op_V_MFMA_F32_16X16X4BF16_1K, +amdgpu_gfx90a_op_V_MFMA_F32_16X16X4F16, +amdgpu_gfx90a_op_V_MFMA_F32_16X16X4F32, +amdgpu_gfx90a_op_V_MFMA_F32_16X16X8BF16, +amdgpu_gfx90a_op_V_MFMA_F32_32X32X1F32, +amdgpu_gfx90a_op_V_MFMA_F32_32X32X2BF16, +amdgpu_gfx90a_op_V_MFMA_F32_32X32X2F32, +amdgpu_gfx90a_op_V_MFMA_F32_32X32X4BF16, +amdgpu_gfx90a_op_V_MFMA_F32_32X32X4BF16_1K, +amdgpu_gfx90a_op_V_MFMA_F32_32X32X4F16, +amdgpu_gfx90a_op_V_MFMA_F32_32X32X8BF16_1K, +amdgpu_gfx90a_op_V_MFMA_F32_32X32X8F16, +amdgpu_gfx90a_op_V_MFMA_F32_4X4X1F32, +amdgpu_gfx90a_op_V_MFMA_F32_4X4X2BF16, +amdgpu_gfx90a_op_V_MFMA_F32_4X4X4BF16_1K, +amdgpu_gfx90a_op_V_MFMA_F32_4X4X4F16, +amdgpu_gfx90a_op_V_MFMA_F64_16X16X4F64, +amdgpu_gfx90a_op_V_MFMA_F64_4X4X4F64, +amdgpu_gfx90a_op_V_MFMA_I32_16X16X16I8, +amdgpu_gfx90a_op_V_MFMA_I32_16X16X4I8, +amdgpu_gfx90a_op_V_MFMA_I32_32X32X4I8, +amdgpu_gfx90a_op_V_MFMA_I32_32X32X8I8, +amdgpu_gfx90a_op_V_MFMA_I32_4X4X4I8, +amdgpu_gfx90a_op_V_MIN3_F16, +amdgpu_gfx90a_op_V_MIN3_F32, +amdgpu_gfx90a_op_V_MIN3_I16, +amdgpu_gfx90a_op_V_MIN3_I32, +amdgpu_gfx90a_op_V_MIN3_U16, +amdgpu_gfx90a_op_V_MIN3_U32, +amdgpu_gfx90a_op_V_MIN_F16, +amdgpu_gfx90a_op_V_MIN_F32, +amdgpu_gfx90a_op_V_MIN_F64, +amdgpu_gfx90a_op_V_MIN_I16, +amdgpu_gfx90a_op_V_MIN_I32, +amdgpu_gfx90a_op_V_MIN_U16, +amdgpu_gfx90a_op_V_MIN_U32, +amdgpu_gfx90a_op_V_MOV_B32, +amdgpu_gfx90a_op_V_MQSAD_PK_U16_U8, +amdgpu_gfx90a_op_V_MQSAD_U32_U8, +amdgpu_gfx90a_op_V_MSAD_U8, +amdgpu_gfx90a_op_V_MUL_F16, +amdgpu_gfx90a_op_V_MUL_F32, +amdgpu_gfx90a_op_V_MUL_F64, +amdgpu_gfx90a_op_V_MUL_HI_I32, +amdgpu_gfx90a_op_V_MUL_HI_I32_I24, +amdgpu_gfx90a_op_V_MUL_HI_U32, +amdgpu_gfx90a_op_V_MUL_HI_U32_U24, +amdgpu_gfx90a_op_V_MUL_I32_I24, +amdgpu_gfx90a_op_V_MUL_LEGACY_F32, +amdgpu_gfx90a_op_V_MUL_LO_U16, +amdgpu_gfx90a_op_V_MUL_LO_U32, +amdgpu_gfx90a_op_V_MUL_U32_U24, +amdgpu_gfx90a_op_V_NOP, +amdgpu_gfx90a_op_V_NOT_B32, +amdgpu_gfx90a_op_V_OR3_B32, +amdgpu_gfx90a_op_V_OR_B32, +amdgpu_gfx90a_op_V_PACK_B32_F16, +amdgpu_gfx90a_op_V_PERM_B32, +amdgpu_gfx90a_op_V_PK_ADD_F16, +amdgpu_gfx90a_op_V_PK_ADD_F32, +amdgpu_gfx90a_op_V_PK_ADD_I16, +amdgpu_gfx90a_op_V_PK_ADD_U16, +amdgpu_gfx90a_op_V_PK_ASHRREV_I16, +amdgpu_gfx90a_op_V_PK_FMAC_F16, +amdgpu_gfx90a_op_V_PK_FMA_F16, +amdgpu_gfx90a_op_V_PK_FMA_F32, +amdgpu_gfx90a_op_V_PK_LSHLREV_B16, +amdgpu_gfx90a_op_V_PK_LSHRREV_B16, +amdgpu_gfx90a_op_V_PK_MAD_I16, +amdgpu_gfx90a_op_V_PK_MAD_U16, +amdgpu_gfx90a_op_V_PK_MAX_F16, +amdgpu_gfx90a_op_V_PK_MAX_I16, +amdgpu_gfx90a_op_V_PK_MAX_U16, +amdgpu_gfx90a_op_V_PK_MIN_F16, +amdgpu_gfx90a_op_V_PK_MIN_I16, +amdgpu_gfx90a_op_V_PK_MIN_U16, +amdgpu_gfx90a_op_V_PK_MOV_B32, +amdgpu_gfx90a_op_V_PK_MUL_F16, +amdgpu_gfx90a_op_V_PK_MUL_F32, +amdgpu_gfx90a_op_V_PK_MUL_LO_U16, +amdgpu_gfx90a_op_V_PK_SUB_I16, +amdgpu_gfx90a_op_V_PK_SUB_U16, +amdgpu_gfx90a_op_V_QSAD_PK_U16_U8, +amdgpu_gfx90a_op_V_RCP_F16, +amdgpu_gfx90a_op_V_RCP_F32, +amdgpu_gfx90a_op_V_RCP_F64, +amdgpu_gfx90a_op_V_RCP_IFLAG_F32, +amdgpu_gfx90a_op_V_READFIRSTLANE_B32, +amdgpu_gfx90a_op_V_READLANE_B32, +amdgpu_gfx90a_op_V_RNDNE_F16, +amdgpu_gfx90a_op_V_RNDNE_F32, +amdgpu_gfx90a_op_V_RNDNE_F64, +amdgpu_gfx90a_op_V_RSQ_F16, +amdgpu_gfx90a_op_V_RSQ_F32, +amdgpu_gfx90a_op_V_RSQ_F64, +amdgpu_gfx90a_op_V_SAD_HI_U8, +amdgpu_gfx90a_op_V_SAD_U16, +amdgpu_gfx90a_op_V_SAD_U32, +amdgpu_gfx90a_op_V_SAD_U8, +amdgpu_gfx90a_op_V_SAT_PK_U8_I16, +amdgpu_gfx90a_op_V_SCREEN_PARTITION_4SE_B32, +amdgpu_gfx90a_op_V_SIN_F16, +amdgpu_gfx90a_op_V_SIN_F32, +amdgpu_gfx90a_op_V_SQRT_F16, +amdgpu_gfx90a_op_V_SQRT_F32, +amdgpu_gfx90a_op_V_SQRT_F64, +amdgpu_gfx90a_op_V_SUBBREV_CO_U32, +amdgpu_gfx90a_op_V_SUBB_CO_U32, +amdgpu_gfx90a_op_V_SUBREV_CO_U32, +amdgpu_gfx90a_op_V_SUBREV_F16, +amdgpu_gfx90a_op_V_SUBREV_F32, +amdgpu_gfx90a_op_V_SUBREV_U16, +amdgpu_gfx90a_op_V_SUBREV_U32, +amdgpu_gfx90a_op_V_SUB_CO_U32, +amdgpu_gfx90a_op_V_SUB_F16, +amdgpu_gfx90a_op_V_SUB_F32, +amdgpu_gfx90a_op_V_SUB_I16, +amdgpu_gfx90a_op_V_SUB_I32, +amdgpu_gfx90a_op_V_SUB_U16, +amdgpu_gfx90a_op_V_SUB_U32, +amdgpu_gfx90a_op_V_SWAP_B32, +amdgpu_gfx90a_op_V_TRIG_PREOP_F64, +amdgpu_gfx90a_op_V_TRUNC_F16, +amdgpu_gfx90a_op_V_TRUNC_F32, +amdgpu_gfx90a_op_V_TRUNC_F64, +amdgpu_gfx90a_op_V_WRITELANE_B32, +amdgpu_gfx90a_op_V_XAD_U32, +amdgpu_gfx90a_op_V_XNOR_B32, +amdgpu_gfx90a_op_V_XOR_B32, diff --git a/common/h/mnemonics/AMDGPU/gfx940_entryIDs.h b/common/h/mnemonics/AMDGPU/gfx940_entryIDs.h new file mode 100644 index 0000000000..5f45ab68b8 --- /dev/null +++ b/common/h/mnemonics/AMDGPU/gfx940_entryIDs.h @@ -0,0 +1,1151 @@ +amdgpu_gfx940_op_BUFFER_ATOMIC_ADD, +amdgpu_gfx940_op_BUFFER_ATOMIC_ADD_F32, +amdgpu_gfx940_op_BUFFER_ATOMIC_ADD_F64, +amdgpu_gfx940_op_BUFFER_ATOMIC_ADD_X2, +amdgpu_gfx940_op_BUFFER_ATOMIC_AND, +amdgpu_gfx940_op_BUFFER_ATOMIC_AND_X2, +amdgpu_gfx940_op_BUFFER_ATOMIC_CMPSWAP, +amdgpu_gfx940_op_BUFFER_ATOMIC_CMPSWAP_X2, +amdgpu_gfx940_op_BUFFER_ATOMIC_DEC, +amdgpu_gfx940_op_BUFFER_ATOMIC_DEC_X2, +amdgpu_gfx940_op_BUFFER_ATOMIC_INC, +amdgpu_gfx940_op_BUFFER_ATOMIC_INC_X2, +amdgpu_gfx940_op_BUFFER_ATOMIC_MAX_F64, +amdgpu_gfx940_op_BUFFER_ATOMIC_MIN_F64, +amdgpu_gfx940_op_BUFFER_ATOMIC_OR, +amdgpu_gfx940_op_BUFFER_ATOMIC_OR_X2, +amdgpu_gfx940_op_BUFFER_ATOMIC_PK_ADD_F16, +amdgpu_gfx940_op_BUFFER_ATOMIC_SMAX, +amdgpu_gfx940_op_BUFFER_ATOMIC_SMAX_X2, +amdgpu_gfx940_op_BUFFER_ATOMIC_SMIN, +amdgpu_gfx940_op_BUFFER_ATOMIC_SMIN_X2, +amdgpu_gfx940_op_BUFFER_ATOMIC_SUB, +amdgpu_gfx940_op_BUFFER_ATOMIC_SUB_X2, +amdgpu_gfx940_op_BUFFER_ATOMIC_SWAP, +amdgpu_gfx940_op_BUFFER_ATOMIC_SWAP_X2, +amdgpu_gfx940_op_BUFFER_ATOMIC_UMAX, +amdgpu_gfx940_op_BUFFER_ATOMIC_UMAX_X2, +amdgpu_gfx940_op_BUFFER_ATOMIC_UMIN, +amdgpu_gfx940_op_BUFFER_ATOMIC_UMIN_X2, +amdgpu_gfx940_op_BUFFER_ATOMIC_XOR, +amdgpu_gfx940_op_BUFFER_ATOMIC_XOR_X2, +amdgpu_gfx940_op_BUFFER_INV, +amdgpu_gfx940_op_BUFFER_LOAD_DWORD, +amdgpu_gfx940_op_BUFFER_LOAD_DWORDX2, +amdgpu_gfx940_op_BUFFER_LOAD_DWORDX3, +amdgpu_gfx940_op_BUFFER_LOAD_DWORDX4, +amdgpu_gfx940_op_BUFFER_LOAD_FORMAT_D16_HI_X, +amdgpu_gfx940_op_BUFFER_LOAD_FORMAT_D16_X, +amdgpu_gfx940_op_BUFFER_LOAD_FORMAT_D16_XY, +amdgpu_gfx940_op_BUFFER_LOAD_FORMAT_D16_XYZ, +amdgpu_gfx940_op_BUFFER_LOAD_FORMAT_D16_XYZW, +amdgpu_gfx940_op_BUFFER_LOAD_FORMAT_X, +amdgpu_gfx940_op_BUFFER_LOAD_FORMAT_XY, +amdgpu_gfx940_op_BUFFER_LOAD_FORMAT_XYZ, +amdgpu_gfx940_op_BUFFER_LOAD_FORMAT_XYZW, +amdgpu_gfx940_op_BUFFER_LOAD_SBYTE, +amdgpu_gfx940_op_BUFFER_LOAD_SBYTE_D16, +amdgpu_gfx940_op_BUFFER_LOAD_SBYTE_D16_HI, +amdgpu_gfx940_op_BUFFER_LOAD_SHORT_D16, +amdgpu_gfx940_op_BUFFER_LOAD_SHORT_D16_HI, +amdgpu_gfx940_op_BUFFER_LOAD_SSHORT, +amdgpu_gfx940_op_BUFFER_LOAD_UBYTE, +amdgpu_gfx940_op_BUFFER_LOAD_UBYTE_D16, +amdgpu_gfx940_op_BUFFER_LOAD_UBYTE_D16_HI, +amdgpu_gfx940_op_BUFFER_LOAD_USHORT, +amdgpu_gfx940_op_BUFFER_STORE_BYTE, +amdgpu_gfx940_op_BUFFER_STORE_BYTE_D16_HI, +amdgpu_gfx940_op_BUFFER_STORE_DWORD, +amdgpu_gfx940_op_BUFFER_STORE_DWORDX2, +amdgpu_gfx940_op_BUFFER_STORE_DWORDX3, +amdgpu_gfx940_op_BUFFER_STORE_DWORDX4, +amdgpu_gfx940_op_BUFFER_STORE_FORMAT_D16_HI_X, +amdgpu_gfx940_op_BUFFER_STORE_FORMAT_D16_X, +amdgpu_gfx940_op_BUFFER_STORE_FORMAT_D16_XY, +amdgpu_gfx940_op_BUFFER_STORE_FORMAT_D16_XYZ, +amdgpu_gfx940_op_BUFFER_STORE_FORMAT_D16_XYZW, +amdgpu_gfx940_op_BUFFER_STORE_FORMAT_X, +amdgpu_gfx940_op_BUFFER_STORE_FORMAT_XY, +amdgpu_gfx940_op_BUFFER_STORE_FORMAT_XYZ, +amdgpu_gfx940_op_BUFFER_STORE_FORMAT_XYZW, +amdgpu_gfx940_op_BUFFER_STORE_SHORT, +amdgpu_gfx940_op_BUFFER_STORE_SHORT_D16_HI, +amdgpu_gfx940_op_BUFFER_WBL2, +amdgpu_gfx940_op_DS_ADD_F32, +amdgpu_gfx940_op_DS_ADD_F64, +amdgpu_gfx940_op_DS_ADD_RTN_F32, +amdgpu_gfx940_op_DS_ADD_RTN_F64, +amdgpu_gfx940_op_DS_ADD_RTN_U32, +amdgpu_gfx940_op_DS_ADD_RTN_U64, +amdgpu_gfx940_op_DS_ADD_U32, +amdgpu_gfx940_op_DS_ADD_U64, +amdgpu_gfx940_op_DS_AND_B32, +amdgpu_gfx940_op_DS_AND_B64, +amdgpu_gfx940_op_DS_AND_RTN_B32, +amdgpu_gfx940_op_DS_AND_RTN_B64, +amdgpu_gfx940_op_DS_APPEND, +amdgpu_gfx940_op_DS_BPERMUTE_B32, +amdgpu_gfx940_op_DS_CMPST_B32, +amdgpu_gfx940_op_DS_CMPST_B64, +amdgpu_gfx940_op_DS_CMPST_F32, +amdgpu_gfx940_op_DS_CMPST_F64, +amdgpu_gfx940_op_DS_CMPST_RTN_B32, +amdgpu_gfx940_op_DS_CMPST_RTN_B64, +amdgpu_gfx940_op_DS_CMPST_RTN_F32, +amdgpu_gfx940_op_DS_CMPST_RTN_F64, +amdgpu_gfx940_op_DS_CONDXCHG32_RTN_B64, +amdgpu_gfx940_op_DS_CONSUME, +amdgpu_gfx940_op_DS_DEC_RTN_U32, +amdgpu_gfx940_op_DS_DEC_RTN_U64, +amdgpu_gfx940_op_DS_DEC_U32, +amdgpu_gfx940_op_DS_DEC_U64, +amdgpu_gfx940_op_DS_GWS_BARRIER, +amdgpu_gfx940_op_DS_GWS_INIT, +amdgpu_gfx940_op_DS_GWS_SEMA_BR, +amdgpu_gfx940_op_DS_GWS_SEMA_P, +amdgpu_gfx940_op_DS_GWS_SEMA_RELEASE_ALL, +amdgpu_gfx940_op_DS_GWS_SEMA_V, +amdgpu_gfx940_op_DS_INC_RTN_U32, +amdgpu_gfx940_op_DS_INC_RTN_U64, +amdgpu_gfx940_op_DS_INC_U32, +amdgpu_gfx940_op_DS_INC_U64, +amdgpu_gfx940_op_DS_MAX_F32, +amdgpu_gfx940_op_DS_MAX_F64, +amdgpu_gfx940_op_DS_MAX_I32, +amdgpu_gfx940_op_DS_MAX_I64, +amdgpu_gfx940_op_DS_MAX_RTN_F32, +amdgpu_gfx940_op_DS_MAX_RTN_F64, +amdgpu_gfx940_op_DS_MAX_RTN_I32, +amdgpu_gfx940_op_DS_MAX_RTN_I64, +amdgpu_gfx940_op_DS_MAX_RTN_U32, +amdgpu_gfx940_op_DS_MAX_RTN_U64, +amdgpu_gfx940_op_DS_MAX_U32, +amdgpu_gfx940_op_DS_MAX_U64, +amdgpu_gfx940_op_DS_MIN_F32, +amdgpu_gfx940_op_DS_MIN_F64, +amdgpu_gfx940_op_DS_MIN_I32, +amdgpu_gfx940_op_DS_MIN_I64, +amdgpu_gfx940_op_DS_MIN_RTN_F32, +amdgpu_gfx940_op_DS_MIN_RTN_F64, +amdgpu_gfx940_op_DS_MIN_RTN_I32, +amdgpu_gfx940_op_DS_MIN_RTN_I64, +amdgpu_gfx940_op_DS_MIN_RTN_U32, +amdgpu_gfx940_op_DS_MIN_RTN_U64, +amdgpu_gfx940_op_DS_MIN_U32, +amdgpu_gfx940_op_DS_MIN_U64, +amdgpu_gfx940_op_DS_MSKOR_B32, +amdgpu_gfx940_op_DS_MSKOR_B64, +amdgpu_gfx940_op_DS_MSKOR_RTN_B32, +amdgpu_gfx940_op_DS_MSKOR_RTN_B64, +amdgpu_gfx940_op_DS_NOP, +amdgpu_gfx940_op_DS_OR_B32, +amdgpu_gfx940_op_DS_OR_B64, +amdgpu_gfx940_op_DS_OR_RTN_B32, +amdgpu_gfx940_op_DS_OR_RTN_B64, +amdgpu_gfx940_op_DS_PERMUTE_B32, +amdgpu_gfx940_op_DS_PK_ADD_BF16, +amdgpu_gfx940_op_DS_PK_ADD_F16, +amdgpu_gfx940_op_DS_PK_ADD_RTN_BF16, +amdgpu_gfx940_op_DS_PK_ADD_RTN_F16, +amdgpu_gfx940_op_DS_READ2ST64_B32, +amdgpu_gfx940_op_DS_READ2ST64_B64, +amdgpu_gfx940_op_DS_READ2_B32, +amdgpu_gfx940_op_DS_READ2_B64, +amdgpu_gfx940_op_DS_READ_ADDTID_B32, +amdgpu_gfx940_op_DS_READ_B128, +amdgpu_gfx940_op_DS_READ_B32, +amdgpu_gfx940_op_DS_READ_B64, +amdgpu_gfx940_op_DS_READ_B96, +amdgpu_gfx940_op_DS_READ_I16, +amdgpu_gfx940_op_DS_READ_I8, +amdgpu_gfx940_op_DS_READ_I8_D16, +amdgpu_gfx940_op_DS_READ_I8_D16_HI, +amdgpu_gfx940_op_DS_READ_U16, +amdgpu_gfx940_op_DS_READ_U16_D16, +amdgpu_gfx940_op_DS_READ_U16_D16_HI, +amdgpu_gfx940_op_DS_READ_U8, +amdgpu_gfx940_op_DS_READ_U8_D16, +amdgpu_gfx940_op_DS_READ_U8_D16_HI, +amdgpu_gfx940_op_DS_RSUB_RTN_U32, +amdgpu_gfx940_op_DS_RSUB_RTN_U64, +amdgpu_gfx940_op_DS_RSUB_U32, +amdgpu_gfx940_op_DS_RSUB_U64, +amdgpu_gfx940_op_DS_SUB_RTN_U32, +amdgpu_gfx940_op_DS_SUB_RTN_U64, +amdgpu_gfx940_op_DS_SUB_U32, +amdgpu_gfx940_op_DS_SUB_U64, +amdgpu_gfx940_op_DS_SWIZZLE_B32, +amdgpu_gfx940_op_DS_WRAP_RTN_B32, +amdgpu_gfx940_op_DS_WRITE2ST64_B32, +amdgpu_gfx940_op_DS_WRITE2ST64_B64, +amdgpu_gfx940_op_DS_WRITE2_B32, +amdgpu_gfx940_op_DS_WRITE2_B64, +amdgpu_gfx940_op_DS_WRITE_ADDTID_B32, +amdgpu_gfx940_op_DS_WRITE_B128, +amdgpu_gfx940_op_DS_WRITE_B16, +amdgpu_gfx940_op_DS_WRITE_B16_D16_HI, +amdgpu_gfx940_op_DS_WRITE_B32, +amdgpu_gfx940_op_DS_WRITE_B64, +amdgpu_gfx940_op_DS_WRITE_B8, +amdgpu_gfx940_op_DS_WRITE_B8_D16_HI, +amdgpu_gfx940_op_DS_WRITE_B96, +amdgpu_gfx940_op_DS_WRXCHG2ST64_RTN_B32, +amdgpu_gfx940_op_DS_WRXCHG2ST64_RTN_B64, +amdgpu_gfx940_op_DS_WRXCHG2_RTN_B32, +amdgpu_gfx940_op_DS_WRXCHG2_RTN_B64, +amdgpu_gfx940_op_DS_WRXCHG_RTN_B32, +amdgpu_gfx940_op_DS_WRXCHG_RTN_B64, +amdgpu_gfx940_op_DS_XOR_B32, +amdgpu_gfx940_op_DS_XOR_B64, +amdgpu_gfx940_op_DS_XOR_RTN_B32, +amdgpu_gfx940_op_DS_XOR_RTN_B64, +amdgpu_gfx940_op_FLAT_ATOMIC_ADD, +amdgpu_gfx940_op_FLAT_ATOMIC_ADD_F32, +amdgpu_gfx940_op_FLAT_ATOMIC_ADD_F64, +amdgpu_gfx940_op_FLAT_ATOMIC_ADD_X2, +amdgpu_gfx940_op_FLAT_ATOMIC_AND, +amdgpu_gfx940_op_FLAT_ATOMIC_AND_X2, +amdgpu_gfx940_op_FLAT_ATOMIC_CMPSWAP, +amdgpu_gfx940_op_FLAT_ATOMIC_CMPSWAP_X2, +amdgpu_gfx940_op_FLAT_ATOMIC_DEC, +amdgpu_gfx940_op_FLAT_ATOMIC_DEC_X2, +amdgpu_gfx940_op_FLAT_ATOMIC_INC, +amdgpu_gfx940_op_FLAT_ATOMIC_INC_X2, +amdgpu_gfx940_op_FLAT_ATOMIC_MAX_F64, +amdgpu_gfx940_op_FLAT_ATOMIC_MIN_F64, +amdgpu_gfx940_op_FLAT_ATOMIC_OR, +amdgpu_gfx940_op_FLAT_ATOMIC_OR_X2, +amdgpu_gfx940_op_FLAT_ATOMIC_PK_ADD_BF16, +amdgpu_gfx940_op_FLAT_ATOMIC_PK_ADD_F16, +amdgpu_gfx940_op_FLAT_ATOMIC_SMAX, +amdgpu_gfx940_op_FLAT_ATOMIC_SMAX_X2, +amdgpu_gfx940_op_FLAT_ATOMIC_SMIN, +amdgpu_gfx940_op_FLAT_ATOMIC_SMIN_X2, +amdgpu_gfx940_op_FLAT_ATOMIC_SUB, +amdgpu_gfx940_op_FLAT_ATOMIC_SUB_X2, +amdgpu_gfx940_op_FLAT_ATOMIC_SWAP, +amdgpu_gfx940_op_FLAT_ATOMIC_SWAP_X2, +amdgpu_gfx940_op_FLAT_ATOMIC_UMAX, +amdgpu_gfx940_op_FLAT_ATOMIC_UMAX_X2, +amdgpu_gfx940_op_FLAT_ATOMIC_UMIN, +amdgpu_gfx940_op_FLAT_ATOMIC_UMIN_X2, +amdgpu_gfx940_op_FLAT_ATOMIC_XOR, +amdgpu_gfx940_op_FLAT_ATOMIC_XOR_X2, +amdgpu_gfx940_op_FLAT_LOAD_DWORD, +amdgpu_gfx940_op_FLAT_LOAD_DWORDX2, +amdgpu_gfx940_op_FLAT_LOAD_DWORDX3, +amdgpu_gfx940_op_FLAT_LOAD_DWORDX4, +amdgpu_gfx940_op_FLAT_LOAD_SBYTE, +amdgpu_gfx940_op_FLAT_LOAD_SBYTE_D16, +amdgpu_gfx940_op_FLAT_LOAD_SBYTE_D16_HI, +amdgpu_gfx940_op_FLAT_LOAD_SHORT_D16, +amdgpu_gfx940_op_FLAT_LOAD_SHORT_D16_HI, +amdgpu_gfx940_op_FLAT_LOAD_SSHORT, +amdgpu_gfx940_op_FLAT_LOAD_UBYTE, +amdgpu_gfx940_op_FLAT_LOAD_UBYTE_D16, +amdgpu_gfx940_op_FLAT_LOAD_UBYTE_D16_HI, +amdgpu_gfx940_op_FLAT_LOAD_USHORT, +amdgpu_gfx940_op_FLAT_STORE_BYTE, +amdgpu_gfx940_op_FLAT_STORE_BYTE_D16_HI, +amdgpu_gfx940_op_FLAT_STORE_DWORD, +amdgpu_gfx940_op_FLAT_STORE_DWORDX2, +amdgpu_gfx940_op_FLAT_STORE_DWORDX3, +amdgpu_gfx940_op_FLAT_STORE_DWORDX4, +amdgpu_gfx940_op_FLAT_STORE_SHORT, +amdgpu_gfx940_op_FLAT_STORE_SHORT_D16_HI, +amdgpu_gfx940_op_GLOBAL_ATOMIC_ADD, +amdgpu_gfx940_op_GLOBAL_ATOMIC_ADD_F32, +amdgpu_gfx940_op_GLOBAL_ATOMIC_ADD_F64, +amdgpu_gfx940_op_GLOBAL_ATOMIC_ADD_X2, +amdgpu_gfx940_op_GLOBAL_ATOMIC_AND, +amdgpu_gfx940_op_GLOBAL_ATOMIC_AND_X2, +amdgpu_gfx940_op_GLOBAL_ATOMIC_CMPSWAP, +amdgpu_gfx940_op_GLOBAL_ATOMIC_CMPSWAP_X2, +amdgpu_gfx940_op_GLOBAL_ATOMIC_DEC, +amdgpu_gfx940_op_GLOBAL_ATOMIC_DEC_X2, +amdgpu_gfx940_op_GLOBAL_ATOMIC_INC, +amdgpu_gfx940_op_GLOBAL_ATOMIC_INC_X2, +amdgpu_gfx940_op_GLOBAL_ATOMIC_MAX_F64, +amdgpu_gfx940_op_GLOBAL_ATOMIC_MIN_F64, +amdgpu_gfx940_op_GLOBAL_ATOMIC_OR, +amdgpu_gfx940_op_GLOBAL_ATOMIC_OR_X2, +amdgpu_gfx940_op_GLOBAL_ATOMIC_PK_ADD_BF16, +amdgpu_gfx940_op_GLOBAL_ATOMIC_PK_ADD_F16, +amdgpu_gfx940_op_GLOBAL_ATOMIC_SMAX, +amdgpu_gfx940_op_GLOBAL_ATOMIC_SMAX_X2, +amdgpu_gfx940_op_GLOBAL_ATOMIC_SMIN, +amdgpu_gfx940_op_GLOBAL_ATOMIC_SMIN_X2, +amdgpu_gfx940_op_GLOBAL_ATOMIC_SUB, +amdgpu_gfx940_op_GLOBAL_ATOMIC_SUB_X2, +amdgpu_gfx940_op_GLOBAL_ATOMIC_SWAP, +amdgpu_gfx940_op_GLOBAL_ATOMIC_SWAP_X2, +amdgpu_gfx940_op_GLOBAL_ATOMIC_UMAX, +amdgpu_gfx940_op_GLOBAL_ATOMIC_UMAX_X2, +amdgpu_gfx940_op_GLOBAL_ATOMIC_UMIN, +amdgpu_gfx940_op_GLOBAL_ATOMIC_UMIN_X2, +amdgpu_gfx940_op_GLOBAL_ATOMIC_XOR, +amdgpu_gfx940_op_GLOBAL_ATOMIC_XOR_X2, +amdgpu_gfx940_op_GLOBAL_LOAD_DWORD, +amdgpu_gfx940_op_GLOBAL_LOAD_DWORDX2, +amdgpu_gfx940_op_GLOBAL_LOAD_DWORDX3, +amdgpu_gfx940_op_GLOBAL_LOAD_DWORDX4, +amdgpu_gfx940_op_GLOBAL_LOAD_LDS_DWORD, +amdgpu_gfx940_op_GLOBAL_LOAD_LDS_SBYTE, +amdgpu_gfx940_op_GLOBAL_LOAD_LDS_SSHORT, +amdgpu_gfx940_op_GLOBAL_LOAD_LDS_UBYTE, +amdgpu_gfx940_op_GLOBAL_LOAD_LDS_USHORT, +amdgpu_gfx940_op_GLOBAL_LOAD_SBYTE, +amdgpu_gfx940_op_GLOBAL_LOAD_SBYTE_D16, +amdgpu_gfx940_op_GLOBAL_LOAD_SBYTE_D16_HI, +amdgpu_gfx940_op_GLOBAL_LOAD_SHORT_D16, +amdgpu_gfx940_op_GLOBAL_LOAD_SHORT_D16_HI, +amdgpu_gfx940_op_GLOBAL_LOAD_SSHORT, +amdgpu_gfx940_op_GLOBAL_LOAD_UBYTE, +amdgpu_gfx940_op_GLOBAL_LOAD_UBYTE_D16, +amdgpu_gfx940_op_GLOBAL_LOAD_UBYTE_D16_HI, +amdgpu_gfx940_op_GLOBAL_LOAD_USHORT, +amdgpu_gfx940_op_GLOBAL_STORE_BYTE, +amdgpu_gfx940_op_GLOBAL_STORE_BYTE_D16_HI, +amdgpu_gfx940_op_GLOBAL_STORE_DWORD, +amdgpu_gfx940_op_GLOBAL_STORE_DWORDX2, +amdgpu_gfx940_op_GLOBAL_STORE_DWORDX3, +amdgpu_gfx940_op_GLOBAL_STORE_DWORDX4, +amdgpu_gfx940_op_GLOBAL_STORE_SHORT, +amdgpu_gfx940_op_GLOBAL_STORE_SHORT_D16_HI, +amdgpu_gfx940_op_SCRATCH_LOAD_DWORD, +amdgpu_gfx940_op_SCRATCH_LOAD_DWORDX2, +amdgpu_gfx940_op_SCRATCH_LOAD_DWORDX3, +amdgpu_gfx940_op_SCRATCH_LOAD_DWORDX4, +amdgpu_gfx940_op_SCRATCH_LOAD_LDS_DWORD, +amdgpu_gfx940_op_SCRATCH_LOAD_LDS_SBYTE, +amdgpu_gfx940_op_SCRATCH_LOAD_LDS_SSHORT, +amdgpu_gfx940_op_SCRATCH_LOAD_LDS_UBYTE, +amdgpu_gfx940_op_SCRATCH_LOAD_LDS_USHORT, +amdgpu_gfx940_op_SCRATCH_LOAD_SBYTE, +amdgpu_gfx940_op_SCRATCH_LOAD_SBYTE_D16, +amdgpu_gfx940_op_SCRATCH_LOAD_SBYTE_D16_HI, +amdgpu_gfx940_op_SCRATCH_LOAD_SHORT_D16, +amdgpu_gfx940_op_SCRATCH_LOAD_SHORT_D16_HI, +amdgpu_gfx940_op_SCRATCH_LOAD_SSHORT, +amdgpu_gfx940_op_SCRATCH_LOAD_UBYTE, +amdgpu_gfx940_op_SCRATCH_LOAD_UBYTE_D16, +amdgpu_gfx940_op_SCRATCH_LOAD_UBYTE_D16_HI, +amdgpu_gfx940_op_SCRATCH_LOAD_USHORT, +amdgpu_gfx940_op_SCRATCH_STORE_BYTE, +amdgpu_gfx940_op_SCRATCH_STORE_BYTE_D16_HI, +amdgpu_gfx940_op_SCRATCH_STORE_DWORD, +amdgpu_gfx940_op_SCRATCH_STORE_DWORDX2, +amdgpu_gfx940_op_SCRATCH_STORE_DWORDX3, +amdgpu_gfx940_op_SCRATCH_STORE_DWORDX4, +amdgpu_gfx940_op_SCRATCH_STORE_SHORT, +amdgpu_gfx940_op_SCRATCH_STORE_SHORT_D16_HI, +amdgpu_gfx940_op_S_ABSDIFF_I32, +amdgpu_gfx940_op_S_ABS_I32, +amdgpu_gfx940_op_S_ADDC_U32, +amdgpu_gfx940_op_S_ADDK_I32, +amdgpu_gfx940_op_S_ADD_I32, +amdgpu_gfx940_op_S_ADD_U32, +amdgpu_gfx940_op_S_ANDN1_SAVEEXEC_B64, +amdgpu_gfx940_op_S_ANDN1_WREXEC_B64, +amdgpu_gfx940_op_S_ANDN2_B32, +amdgpu_gfx940_op_S_ANDN2_B64, +amdgpu_gfx940_op_S_ANDN2_SAVEEXEC_B64, +amdgpu_gfx940_op_S_ANDN2_WREXEC_B64, +amdgpu_gfx940_op_S_AND_B32, +amdgpu_gfx940_op_S_AND_B64, +amdgpu_gfx940_op_S_AND_SAVEEXEC_B64, +amdgpu_gfx940_op_S_ASHR_I32, +amdgpu_gfx940_op_S_ASHR_I64, +amdgpu_gfx940_op_S_ATC_PROBE, +amdgpu_gfx940_op_S_ATC_PROBE_BUFFER, +amdgpu_gfx940_op_S_ATOMIC_ADD, +amdgpu_gfx940_op_S_ATOMIC_ADD_X2, +amdgpu_gfx940_op_S_ATOMIC_AND, +amdgpu_gfx940_op_S_ATOMIC_AND_X2, +amdgpu_gfx940_op_S_ATOMIC_CMPSWAP, +amdgpu_gfx940_op_S_ATOMIC_CMPSWAP_X2, +amdgpu_gfx940_op_S_ATOMIC_DEC, +amdgpu_gfx940_op_S_ATOMIC_DEC_X2, +amdgpu_gfx940_op_S_ATOMIC_INC, +amdgpu_gfx940_op_S_ATOMIC_INC_X2, +amdgpu_gfx940_op_S_ATOMIC_OR, +amdgpu_gfx940_op_S_ATOMIC_OR_X2, +amdgpu_gfx940_op_S_ATOMIC_SMAX, +amdgpu_gfx940_op_S_ATOMIC_SMAX_X2, +amdgpu_gfx940_op_S_ATOMIC_SMIN, +amdgpu_gfx940_op_S_ATOMIC_SMIN_X2, +amdgpu_gfx940_op_S_ATOMIC_SUB, +amdgpu_gfx940_op_S_ATOMIC_SUB_X2, +amdgpu_gfx940_op_S_ATOMIC_SWAP, +amdgpu_gfx940_op_S_ATOMIC_SWAP_X2, +amdgpu_gfx940_op_S_ATOMIC_UMAX, +amdgpu_gfx940_op_S_ATOMIC_UMAX_X2, +amdgpu_gfx940_op_S_ATOMIC_UMIN, +amdgpu_gfx940_op_S_ATOMIC_UMIN_X2, +amdgpu_gfx940_op_S_ATOMIC_XOR, +amdgpu_gfx940_op_S_ATOMIC_XOR_X2, +amdgpu_gfx940_op_S_BARRIER, +amdgpu_gfx940_op_S_BCNT0_I32_B32, +amdgpu_gfx940_op_S_BCNT0_I32_B64, +amdgpu_gfx940_op_S_BCNT1_I32_B32, +amdgpu_gfx940_op_S_BCNT1_I32_B64, +amdgpu_gfx940_op_S_BFE_I32, +amdgpu_gfx940_op_S_BFE_I64, +amdgpu_gfx940_op_S_BFE_U32, +amdgpu_gfx940_op_S_BFE_U64, +amdgpu_gfx940_op_S_BFM_B32, +amdgpu_gfx940_op_S_BFM_B64, +amdgpu_gfx940_op_S_BITCMP0_B32, +amdgpu_gfx940_op_S_BITCMP0_B64, +amdgpu_gfx940_op_S_BITCMP1_B32, +amdgpu_gfx940_op_S_BITCMP1_B64, +amdgpu_gfx940_op_S_BITREPLICATE_B64_B32, +amdgpu_gfx940_op_S_BITSET0_B32, +amdgpu_gfx940_op_S_BITSET0_B64, +amdgpu_gfx940_op_S_BITSET1_B32, +amdgpu_gfx940_op_S_BITSET1_B64, +amdgpu_gfx940_op_S_BRANCH, +amdgpu_gfx940_op_S_BREV_B32, +amdgpu_gfx940_op_S_BREV_B64, +amdgpu_gfx940_op_S_BUFFER_ATOMIC_ADD, +amdgpu_gfx940_op_S_BUFFER_ATOMIC_ADD_X2, +amdgpu_gfx940_op_S_BUFFER_ATOMIC_AND, +amdgpu_gfx940_op_S_BUFFER_ATOMIC_AND_X2, +amdgpu_gfx940_op_S_BUFFER_ATOMIC_CMPSWAP, +amdgpu_gfx940_op_S_BUFFER_ATOMIC_CMPSWAP_X2, +amdgpu_gfx940_op_S_BUFFER_ATOMIC_DEC, +amdgpu_gfx940_op_S_BUFFER_ATOMIC_DEC_X2, +amdgpu_gfx940_op_S_BUFFER_ATOMIC_INC, +amdgpu_gfx940_op_S_BUFFER_ATOMIC_INC_X2, +amdgpu_gfx940_op_S_BUFFER_ATOMIC_OR, +amdgpu_gfx940_op_S_BUFFER_ATOMIC_OR_X2, +amdgpu_gfx940_op_S_BUFFER_ATOMIC_SMAX, +amdgpu_gfx940_op_S_BUFFER_ATOMIC_SMAX_X2, +amdgpu_gfx940_op_S_BUFFER_ATOMIC_SMIN, +amdgpu_gfx940_op_S_BUFFER_ATOMIC_SMIN_X2, +amdgpu_gfx940_op_S_BUFFER_ATOMIC_SUB, +amdgpu_gfx940_op_S_BUFFER_ATOMIC_SUB_X2, +amdgpu_gfx940_op_S_BUFFER_ATOMIC_SWAP, +amdgpu_gfx940_op_S_BUFFER_ATOMIC_SWAP_X2, +amdgpu_gfx940_op_S_BUFFER_ATOMIC_UMAX, +amdgpu_gfx940_op_S_BUFFER_ATOMIC_UMAX_X2, +amdgpu_gfx940_op_S_BUFFER_ATOMIC_UMIN, +amdgpu_gfx940_op_S_BUFFER_ATOMIC_UMIN_X2, +amdgpu_gfx940_op_S_BUFFER_ATOMIC_XOR, +amdgpu_gfx940_op_S_BUFFER_ATOMIC_XOR_X2, +amdgpu_gfx940_op_S_BUFFER_LOAD_DWORD, +amdgpu_gfx940_op_S_BUFFER_LOAD_DWORDX16, +amdgpu_gfx940_op_S_BUFFER_LOAD_DWORDX2, +amdgpu_gfx940_op_S_BUFFER_LOAD_DWORDX4, +amdgpu_gfx940_op_S_BUFFER_LOAD_DWORDX8, +amdgpu_gfx940_op_S_BUFFER_STORE_DWORD, +amdgpu_gfx940_op_S_BUFFER_STORE_DWORDX2, +amdgpu_gfx940_op_S_BUFFER_STORE_DWORDX4, +amdgpu_gfx940_op_S_CALL_B64, +amdgpu_gfx940_op_S_CBRANCH_CDBGSYS, +amdgpu_gfx940_op_S_CBRANCH_CDBGSYS_AND_USER, +amdgpu_gfx940_op_S_CBRANCH_CDBGSYS_OR_USER, +amdgpu_gfx940_op_S_CBRANCH_CDBGUSER, +amdgpu_gfx940_op_S_CBRANCH_EXECNZ, +amdgpu_gfx940_op_S_CBRANCH_EXECZ, +amdgpu_gfx940_op_S_CBRANCH_G_FORK, +amdgpu_gfx940_op_S_CBRANCH_I_FORK, +amdgpu_gfx940_op_S_CBRANCH_JOIN, +amdgpu_gfx940_op_S_CBRANCH_SCC0, +amdgpu_gfx940_op_S_CBRANCH_SCC1, +amdgpu_gfx940_op_S_CBRANCH_VCCNZ, +amdgpu_gfx940_op_S_CBRANCH_VCCZ, +amdgpu_gfx940_op_S_CMOVK_I32, +amdgpu_gfx940_op_S_CMOV_B32, +amdgpu_gfx940_op_S_CMOV_B64, +amdgpu_gfx940_op_S_CMPK_EQ_I32, +amdgpu_gfx940_op_S_CMPK_EQ_U32, +amdgpu_gfx940_op_S_CMPK_GE_I32, +amdgpu_gfx940_op_S_CMPK_GE_U32, +amdgpu_gfx940_op_S_CMPK_GT_I32, +amdgpu_gfx940_op_S_CMPK_GT_U32, +amdgpu_gfx940_op_S_CMPK_LE_I32, +amdgpu_gfx940_op_S_CMPK_LE_U32, +amdgpu_gfx940_op_S_CMPK_LG_I32, +amdgpu_gfx940_op_S_CMPK_LG_U32, +amdgpu_gfx940_op_S_CMPK_LT_I32, +amdgpu_gfx940_op_S_CMPK_LT_U32, +amdgpu_gfx940_op_S_CMP_EQ_I32, +amdgpu_gfx940_op_S_CMP_EQ_U32, +amdgpu_gfx940_op_S_CMP_EQ_U64, +amdgpu_gfx940_op_S_CMP_GE_I32, +amdgpu_gfx940_op_S_CMP_GE_U32, +amdgpu_gfx940_op_S_CMP_GT_I32, +amdgpu_gfx940_op_S_CMP_GT_U32, +amdgpu_gfx940_op_S_CMP_LE_I32, +amdgpu_gfx940_op_S_CMP_LE_U32, +amdgpu_gfx940_op_S_CMP_LG_I32, +amdgpu_gfx940_op_S_CMP_LG_U32, +amdgpu_gfx940_op_S_CMP_LG_U64, +amdgpu_gfx940_op_S_CMP_LT_I32, +amdgpu_gfx940_op_S_CMP_LT_U32, +amdgpu_gfx940_op_S_CSELECT_B32, +amdgpu_gfx940_op_S_CSELECT_B64, +amdgpu_gfx940_op_S_DCACHE_DISCARD, +amdgpu_gfx940_op_S_DCACHE_DISCARD_X2, +amdgpu_gfx940_op_S_DCACHE_INV, +amdgpu_gfx940_op_S_DCACHE_INV_VOL, +amdgpu_gfx940_op_S_DCACHE_WB, +amdgpu_gfx940_op_S_DCACHE_WB_VOL, +amdgpu_gfx940_op_S_DECPERFLEVEL, +amdgpu_gfx940_op_S_ENDPGM, +amdgpu_gfx940_op_S_ENDPGM_ORDERED_PS_DONE, +amdgpu_gfx940_op_S_ENDPGM_SAVED, +amdgpu_gfx940_op_S_FF0_I32_B32, +amdgpu_gfx940_op_S_FF0_I32_B64, +amdgpu_gfx940_op_S_FF1_I32_B32, +amdgpu_gfx940_op_S_FF1_I32_B64, +amdgpu_gfx940_op_S_FLBIT_I32, +amdgpu_gfx940_op_S_FLBIT_I32_B32, +amdgpu_gfx940_op_S_FLBIT_I32_B64, +amdgpu_gfx940_op_S_FLBIT_I32_I64, +amdgpu_gfx940_op_S_GETPC_B64, +amdgpu_gfx940_op_S_GETREG_B32, +amdgpu_gfx940_op_S_ICACHE_INV, +amdgpu_gfx940_op_S_INCPERFLEVEL, +amdgpu_gfx940_op_S_LOAD_DWORD, +amdgpu_gfx940_op_S_LOAD_DWORDX16, +amdgpu_gfx940_op_S_LOAD_DWORDX2, +amdgpu_gfx940_op_S_LOAD_DWORDX4, +amdgpu_gfx940_op_S_LOAD_DWORDX8, +amdgpu_gfx940_op_S_LSHL1_ADD_U32, +amdgpu_gfx940_op_S_LSHL2_ADD_U32, +amdgpu_gfx940_op_S_LSHL3_ADD_U32, +amdgpu_gfx940_op_S_LSHL4_ADD_U32, +amdgpu_gfx940_op_S_LSHL_B32, +amdgpu_gfx940_op_S_LSHL_B64, +amdgpu_gfx940_op_S_LSHR_B32, +amdgpu_gfx940_op_S_LSHR_B64, +amdgpu_gfx940_op_S_MAX_I32, +amdgpu_gfx940_op_S_MAX_U32, +amdgpu_gfx940_op_S_MEMREALTIME, +amdgpu_gfx940_op_S_MEMTIME, +amdgpu_gfx940_op_S_MIN_I32, +amdgpu_gfx940_op_S_MIN_U32, +amdgpu_gfx940_op_S_MOVK_I32, +amdgpu_gfx940_op_S_MOVRELD_B32, +amdgpu_gfx940_op_S_MOVRELD_B64, +amdgpu_gfx940_op_S_MOVRELS_B32, +amdgpu_gfx940_op_S_MOVRELS_B64, +amdgpu_gfx940_op_S_MOV_B32, +amdgpu_gfx940_op_S_MOV_B64, +amdgpu_gfx940_op_S_MULK_I32, +amdgpu_gfx940_op_S_MUL_HI_I32, +amdgpu_gfx940_op_S_MUL_HI_U32, +amdgpu_gfx940_op_S_MUL_I32, +amdgpu_gfx940_op_S_NAND_B32, +amdgpu_gfx940_op_S_NAND_B64, +amdgpu_gfx940_op_S_NAND_SAVEEXEC_B64, +amdgpu_gfx940_op_S_NOP, +amdgpu_gfx940_op_S_NOR_B32, +amdgpu_gfx940_op_S_NOR_B64, +amdgpu_gfx940_op_S_NOR_SAVEEXEC_B64, +amdgpu_gfx940_op_S_NOT_B32, +amdgpu_gfx940_op_S_NOT_B64, +amdgpu_gfx940_op_S_ORN1_SAVEEXEC_B64, +amdgpu_gfx940_op_S_ORN2_B32, +amdgpu_gfx940_op_S_ORN2_B64, +amdgpu_gfx940_op_S_ORN2_SAVEEXEC_B64, +amdgpu_gfx940_op_S_OR_B32, +amdgpu_gfx940_op_S_OR_B64, +amdgpu_gfx940_op_S_OR_SAVEEXEC_B64, +amdgpu_gfx940_op_S_PACK_HH_B32_B16, +amdgpu_gfx940_op_S_PACK_LH_B32_B16, +amdgpu_gfx940_op_S_PACK_LL_B32_B16, +amdgpu_gfx940_op_S_QUADMASK_B32, +amdgpu_gfx940_op_S_QUADMASK_B64, +amdgpu_gfx940_op_S_RFE_B64, +amdgpu_gfx940_op_S_RFE_RESTORE_B64, +amdgpu_gfx940_op_S_SCRATCH_LOAD_DWORD, +amdgpu_gfx940_op_S_SCRATCH_LOAD_DWORDX2, +amdgpu_gfx940_op_S_SCRATCH_LOAD_DWORDX4, +amdgpu_gfx940_op_S_SCRATCH_STORE_DWORD, +amdgpu_gfx940_op_S_SCRATCH_STORE_DWORDX2, +amdgpu_gfx940_op_S_SCRATCH_STORE_DWORDX4, +amdgpu_gfx940_op_S_SENDMSG, +amdgpu_gfx940_op_S_SENDMSGHALT, +amdgpu_gfx940_op_S_SETHALT, +amdgpu_gfx940_op_S_SETKILL, +amdgpu_gfx940_op_S_SETPC_B64, +amdgpu_gfx940_op_S_SETPRIO, +amdgpu_gfx940_op_S_SETREG_B32, +amdgpu_gfx940_op_S_SETVSKIP, +amdgpu_gfx940_op_S_SET_GPR_IDX_IDX, +amdgpu_gfx940_op_S_SET_GPR_IDX_MODE, +amdgpu_gfx940_op_S_SET_GPR_IDX_OFF, +amdgpu_gfx940_op_S_SET_GPR_IDX_ON, +amdgpu_gfx940_op_S_SET_VALU_COEXEC_MODE, +amdgpu_gfx940_op_S_SEXT_I32_I16, +amdgpu_gfx940_op_S_SEXT_I32_I8, +amdgpu_gfx940_op_S_SLEEP, +amdgpu_gfx940_op_S_STORE_DWORD, +amdgpu_gfx940_op_S_STORE_DWORDX2, +amdgpu_gfx940_op_S_STORE_DWORDX4, +amdgpu_gfx940_op_S_SUBB_U32, +amdgpu_gfx940_op_S_SUB_I32, +amdgpu_gfx940_op_S_SUB_U32, +amdgpu_gfx940_op_S_SWAPPC_B64, +amdgpu_gfx940_op_S_TRAP, +amdgpu_gfx940_op_S_TTRACEDATA, +amdgpu_gfx940_op_S_WAITCNT, +amdgpu_gfx940_op_S_WAKEUP, +amdgpu_gfx940_op_S_WQM_B32, +amdgpu_gfx940_op_S_WQM_B64, +amdgpu_gfx940_op_S_XNOR_B32, +amdgpu_gfx940_op_S_XNOR_B64, +amdgpu_gfx940_op_S_XNOR_SAVEEXEC_B64, +amdgpu_gfx940_op_S_XOR_B32, +amdgpu_gfx940_op_S_XOR_B64, +amdgpu_gfx940_op_S_XOR_SAVEEXEC_B64, +amdgpu_gfx940_op_TBUFFER_LOAD_FORMAT_D16_X, +amdgpu_gfx940_op_TBUFFER_LOAD_FORMAT_D16_XY, +amdgpu_gfx940_op_TBUFFER_LOAD_FORMAT_D16_XYZ, +amdgpu_gfx940_op_TBUFFER_LOAD_FORMAT_D16_XYZW, +amdgpu_gfx940_op_TBUFFER_LOAD_FORMAT_X, +amdgpu_gfx940_op_TBUFFER_LOAD_FORMAT_XY, +amdgpu_gfx940_op_TBUFFER_LOAD_FORMAT_XYZ, +amdgpu_gfx940_op_TBUFFER_LOAD_FORMAT_XYZW, +amdgpu_gfx940_op_TBUFFER_STORE_FORMAT_D16_X, +amdgpu_gfx940_op_TBUFFER_STORE_FORMAT_D16_XY, +amdgpu_gfx940_op_TBUFFER_STORE_FORMAT_D16_XYZ, +amdgpu_gfx940_op_TBUFFER_STORE_FORMAT_D16_XYZW, +amdgpu_gfx940_op_TBUFFER_STORE_FORMAT_X, +amdgpu_gfx940_op_TBUFFER_STORE_FORMAT_XY, +amdgpu_gfx940_op_TBUFFER_STORE_FORMAT_XYZ, +amdgpu_gfx940_op_TBUFFER_STORE_FORMAT_XYZW, +amdgpu_gfx940_op_V_ACCVGPR_MOV_B32, +amdgpu_gfx940_op_V_ACCVGPR_READ, +amdgpu_gfx940_op_V_ACCVGPR_WRITE, +amdgpu_gfx940_op_V_ADD3_U32, +amdgpu_gfx940_op_V_ADDC_CO_U32, +amdgpu_gfx940_op_V_ADD_CO_U32, +amdgpu_gfx940_op_V_ADD_F16, +amdgpu_gfx940_op_V_ADD_F32, +amdgpu_gfx940_op_V_ADD_F64, +amdgpu_gfx940_op_V_ADD_I16, +amdgpu_gfx940_op_V_ADD_I32, +amdgpu_gfx940_op_V_ADD_LSHL_U32, +amdgpu_gfx940_op_V_ADD_U16, +amdgpu_gfx940_op_V_ADD_U32, +amdgpu_gfx940_op_V_ALIGNBIT_B32, +amdgpu_gfx940_op_V_ALIGNBYTE_B32, +amdgpu_gfx940_op_V_AND_B32, +amdgpu_gfx940_op_V_AND_OR_B32, +amdgpu_gfx940_op_V_ASHRREV_I16, +amdgpu_gfx940_op_V_ASHRREV_I32, +amdgpu_gfx940_op_V_ASHRREV_I64, +amdgpu_gfx940_op_V_BCNT_U32_B32, +amdgpu_gfx940_op_V_BFE_I32, +amdgpu_gfx940_op_V_BFE_U32, +amdgpu_gfx940_op_V_BFI_B32, +amdgpu_gfx940_op_V_BFM_B32, +amdgpu_gfx940_op_V_BFREV_B32, +amdgpu_gfx940_op_V_CEIL_F16, +amdgpu_gfx940_op_V_CEIL_F32, +amdgpu_gfx940_op_V_CEIL_F64, +amdgpu_gfx940_op_V_CLREXCP, +amdgpu_gfx940_op_V_CMPX_CLASS_F16, +amdgpu_gfx940_op_V_CMPX_CLASS_F32, +amdgpu_gfx940_op_V_CMPX_CLASS_F64, +amdgpu_gfx940_op_V_CMPX_EQ_F16, +amdgpu_gfx940_op_V_CMPX_EQ_F32, +amdgpu_gfx940_op_V_CMPX_EQ_F64, +amdgpu_gfx940_op_V_CMPX_EQ_I16, +amdgpu_gfx940_op_V_CMPX_EQ_I32, +amdgpu_gfx940_op_V_CMPX_EQ_I64, +amdgpu_gfx940_op_V_CMPX_EQ_U16, +amdgpu_gfx940_op_V_CMPX_EQ_U32, +amdgpu_gfx940_op_V_CMPX_EQ_U64, +amdgpu_gfx940_op_V_CMPX_F_F16, +amdgpu_gfx940_op_V_CMPX_F_F32, +amdgpu_gfx940_op_V_CMPX_F_F64, +amdgpu_gfx940_op_V_CMPX_F_I16, +amdgpu_gfx940_op_V_CMPX_F_I32, +amdgpu_gfx940_op_V_CMPX_F_I64, +amdgpu_gfx940_op_V_CMPX_F_U16, +amdgpu_gfx940_op_V_CMPX_F_U32, +amdgpu_gfx940_op_V_CMPX_F_U64, +amdgpu_gfx940_op_V_CMPX_GE_F16, +amdgpu_gfx940_op_V_CMPX_GE_F32, +amdgpu_gfx940_op_V_CMPX_GE_F64, +amdgpu_gfx940_op_V_CMPX_GE_I16, +amdgpu_gfx940_op_V_CMPX_GE_I32, +amdgpu_gfx940_op_V_CMPX_GE_I64, +amdgpu_gfx940_op_V_CMPX_GE_U16, +amdgpu_gfx940_op_V_CMPX_GE_U32, +amdgpu_gfx940_op_V_CMPX_GE_U64, +amdgpu_gfx940_op_V_CMPX_GT_F16, +amdgpu_gfx940_op_V_CMPX_GT_F32, +amdgpu_gfx940_op_V_CMPX_GT_F64, +amdgpu_gfx940_op_V_CMPX_GT_I16, +amdgpu_gfx940_op_V_CMPX_GT_I32, +amdgpu_gfx940_op_V_CMPX_GT_I64, +amdgpu_gfx940_op_V_CMPX_GT_U16, +amdgpu_gfx940_op_V_CMPX_GT_U32, +amdgpu_gfx940_op_V_CMPX_GT_U64, +amdgpu_gfx940_op_V_CMPX_LE_F16, +amdgpu_gfx940_op_V_CMPX_LE_F32, +amdgpu_gfx940_op_V_CMPX_LE_F64, +amdgpu_gfx940_op_V_CMPX_LE_I16, +amdgpu_gfx940_op_V_CMPX_LE_I32, +amdgpu_gfx940_op_V_CMPX_LE_I64, +amdgpu_gfx940_op_V_CMPX_LE_U16, +amdgpu_gfx940_op_V_CMPX_LE_U32, +amdgpu_gfx940_op_V_CMPX_LE_U64, +amdgpu_gfx940_op_V_CMPX_LG_F16, +amdgpu_gfx940_op_V_CMPX_LG_F32, +amdgpu_gfx940_op_V_CMPX_LG_F64, +amdgpu_gfx940_op_V_CMPX_LT_F16, +amdgpu_gfx940_op_V_CMPX_LT_F32, +amdgpu_gfx940_op_V_CMPX_LT_F64, +amdgpu_gfx940_op_V_CMPX_LT_I16, +amdgpu_gfx940_op_V_CMPX_LT_I32, +amdgpu_gfx940_op_V_CMPX_LT_I64, +amdgpu_gfx940_op_V_CMPX_LT_U16, +amdgpu_gfx940_op_V_CMPX_LT_U32, +amdgpu_gfx940_op_V_CMPX_LT_U64, +amdgpu_gfx940_op_V_CMPX_NEQ_F16, +amdgpu_gfx940_op_V_CMPX_NEQ_F32, +amdgpu_gfx940_op_V_CMPX_NEQ_F64, +amdgpu_gfx940_op_V_CMPX_NE_I16, +amdgpu_gfx940_op_V_CMPX_NE_I32, +amdgpu_gfx940_op_V_CMPX_NE_I64, +amdgpu_gfx940_op_V_CMPX_NE_U16, +amdgpu_gfx940_op_V_CMPX_NE_U32, +amdgpu_gfx940_op_V_CMPX_NE_U64, +amdgpu_gfx940_op_V_CMPX_NGE_F16, +amdgpu_gfx940_op_V_CMPX_NGE_F32, +amdgpu_gfx940_op_V_CMPX_NGE_F64, +amdgpu_gfx940_op_V_CMPX_NGT_F16, +amdgpu_gfx940_op_V_CMPX_NGT_F32, +amdgpu_gfx940_op_V_CMPX_NGT_F64, +amdgpu_gfx940_op_V_CMPX_NLE_F16, +amdgpu_gfx940_op_V_CMPX_NLE_F32, +amdgpu_gfx940_op_V_CMPX_NLE_F64, +amdgpu_gfx940_op_V_CMPX_NLG_F16, +amdgpu_gfx940_op_V_CMPX_NLG_F32, +amdgpu_gfx940_op_V_CMPX_NLG_F64, +amdgpu_gfx940_op_V_CMPX_NLT_F16, +amdgpu_gfx940_op_V_CMPX_NLT_F32, +amdgpu_gfx940_op_V_CMPX_NLT_F64, +amdgpu_gfx940_op_V_CMPX_O_F16, +amdgpu_gfx940_op_V_CMPX_O_F32, +amdgpu_gfx940_op_V_CMPX_O_F64, +amdgpu_gfx940_op_V_CMPX_TRU_F16, +amdgpu_gfx940_op_V_CMPX_TRU_F32, +amdgpu_gfx940_op_V_CMPX_TRU_F64, +amdgpu_gfx940_op_V_CMPX_T_I16, +amdgpu_gfx940_op_V_CMPX_T_I32, +amdgpu_gfx940_op_V_CMPX_T_I64, +amdgpu_gfx940_op_V_CMPX_T_U16, +amdgpu_gfx940_op_V_CMPX_T_U32, +amdgpu_gfx940_op_V_CMPX_T_U64, +amdgpu_gfx940_op_V_CMPX_U_F16, +amdgpu_gfx940_op_V_CMPX_U_F32, +amdgpu_gfx940_op_V_CMPX_U_F64, +amdgpu_gfx940_op_V_CMP_CLASS_F16, +amdgpu_gfx940_op_V_CMP_CLASS_F32, +amdgpu_gfx940_op_V_CMP_CLASS_F64, +amdgpu_gfx940_op_V_CMP_EQ_F16, +amdgpu_gfx940_op_V_CMP_EQ_F32, +amdgpu_gfx940_op_V_CMP_EQ_F64, +amdgpu_gfx940_op_V_CMP_EQ_I16, +amdgpu_gfx940_op_V_CMP_EQ_I32, +amdgpu_gfx940_op_V_CMP_EQ_I64, +amdgpu_gfx940_op_V_CMP_EQ_U16, +amdgpu_gfx940_op_V_CMP_EQ_U32, +amdgpu_gfx940_op_V_CMP_EQ_U64, +amdgpu_gfx940_op_V_CMP_F_F16, +amdgpu_gfx940_op_V_CMP_F_F32, +amdgpu_gfx940_op_V_CMP_F_F64, +amdgpu_gfx940_op_V_CMP_F_I16, +amdgpu_gfx940_op_V_CMP_F_I32, +amdgpu_gfx940_op_V_CMP_F_I64, +amdgpu_gfx940_op_V_CMP_F_U16, +amdgpu_gfx940_op_V_CMP_F_U32, +amdgpu_gfx940_op_V_CMP_F_U64, +amdgpu_gfx940_op_V_CMP_GE_F16, +amdgpu_gfx940_op_V_CMP_GE_F32, +amdgpu_gfx940_op_V_CMP_GE_F64, +amdgpu_gfx940_op_V_CMP_GE_I16, +amdgpu_gfx940_op_V_CMP_GE_I32, +amdgpu_gfx940_op_V_CMP_GE_I64, +amdgpu_gfx940_op_V_CMP_GE_U16, +amdgpu_gfx940_op_V_CMP_GE_U32, +amdgpu_gfx940_op_V_CMP_GE_U64, +amdgpu_gfx940_op_V_CMP_GT_F16, +amdgpu_gfx940_op_V_CMP_GT_F32, +amdgpu_gfx940_op_V_CMP_GT_F64, +amdgpu_gfx940_op_V_CMP_GT_I16, +amdgpu_gfx940_op_V_CMP_GT_I32, +amdgpu_gfx940_op_V_CMP_GT_I64, +amdgpu_gfx940_op_V_CMP_GT_U16, +amdgpu_gfx940_op_V_CMP_GT_U32, +amdgpu_gfx940_op_V_CMP_GT_U64, +amdgpu_gfx940_op_V_CMP_LE_F16, +amdgpu_gfx940_op_V_CMP_LE_F32, +amdgpu_gfx940_op_V_CMP_LE_F64, +amdgpu_gfx940_op_V_CMP_LE_I16, +amdgpu_gfx940_op_V_CMP_LE_I32, +amdgpu_gfx940_op_V_CMP_LE_I64, +amdgpu_gfx940_op_V_CMP_LE_U16, +amdgpu_gfx940_op_V_CMP_LE_U32, +amdgpu_gfx940_op_V_CMP_LE_U64, +amdgpu_gfx940_op_V_CMP_LG_F16, +amdgpu_gfx940_op_V_CMP_LG_F32, +amdgpu_gfx940_op_V_CMP_LG_F64, +amdgpu_gfx940_op_V_CMP_LT_F16, +amdgpu_gfx940_op_V_CMP_LT_F32, +amdgpu_gfx940_op_V_CMP_LT_F64, +amdgpu_gfx940_op_V_CMP_LT_I16, +amdgpu_gfx940_op_V_CMP_LT_I32, +amdgpu_gfx940_op_V_CMP_LT_I64, +amdgpu_gfx940_op_V_CMP_LT_U16, +amdgpu_gfx940_op_V_CMP_LT_U32, +amdgpu_gfx940_op_V_CMP_LT_U64, +amdgpu_gfx940_op_V_CMP_NEQ_F16, +amdgpu_gfx940_op_V_CMP_NEQ_F32, +amdgpu_gfx940_op_V_CMP_NEQ_F64, +amdgpu_gfx940_op_V_CMP_NE_I16, +amdgpu_gfx940_op_V_CMP_NE_I32, +amdgpu_gfx940_op_V_CMP_NE_I64, +amdgpu_gfx940_op_V_CMP_NE_U16, +amdgpu_gfx940_op_V_CMP_NE_U32, +amdgpu_gfx940_op_V_CMP_NE_U64, +amdgpu_gfx940_op_V_CMP_NGE_F16, +amdgpu_gfx940_op_V_CMP_NGE_F32, +amdgpu_gfx940_op_V_CMP_NGE_F64, +amdgpu_gfx940_op_V_CMP_NGT_F16, +amdgpu_gfx940_op_V_CMP_NGT_F32, +amdgpu_gfx940_op_V_CMP_NGT_F64, +amdgpu_gfx940_op_V_CMP_NLE_F16, +amdgpu_gfx940_op_V_CMP_NLE_F32, +amdgpu_gfx940_op_V_CMP_NLE_F64, +amdgpu_gfx940_op_V_CMP_NLG_F16, +amdgpu_gfx940_op_V_CMP_NLG_F32, +amdgpu_gfx940_op_V_CMP_NLG_F64, +amdgpu_gfx940_op_V_CMP_NLT_F16, +amdgpu_gfx940_op_V_CMP_NLT_F32, +amdgpu_gfx940_op_V_CMP_NLT_F64, +amdgpu_gfx940_op_V_CMP_O_F16, +amdgpu_gfx940_op_V_CMP_O_F32, +amdgpu_gfx940_op_V_CMP_O_F64, +amdgpu_gfx940_op_V_CMP_TRU_F16, +amdgpu_gfx940_op_V_CMP_TRU_F32, +amdgpu_gfx940_op_V_CMP_TRU_F64, +amdgpu_gfx940_op_V_CMP_T_I16, +amdgpu_gfx940_op_V_CMP_T_I32, +amdgpu_gfx940_op_V_CMP_T_I64, +amdgpu_gfx940_op_V_CMP_T_U16, +amdgpu_gfx940_op_V_CMP_T_U32, +amdgpu_gfx940_op_V_CMP_T_U64, +amdgpu_gfx940_op_V_CMP_U_F16, +amdgpu_gfx940_op_V_CMP_U_F32, +amdgpu_gfx940_op_V_CMP_U_F64, +amdgpu_gfx940_op_V_CNDMASK_B32, +amdgpu_gfx940_op_V_COS_F16, +amdgpu_gfx940_op_V_COS_F32, +amdgpu_gfx940_op_V_CUBEID_F32, +amdgpu_gfx940_op_V_CUBEMA_F32, +amdgpu_gfx940_op_V_CUBESC_F32, +amdgpu_gfx940_op_V_CUBETC_F32, +amdgpu_gfx940_op_V_CVT_F16_F32, +amdgpu_gfx940_op_V_CVT_F16_I16, +amdgpu_gfx940_op_V_CVT_F16_U16, +amdgpu_gfx940_op_V_CVT_F32_BF8, +amdgpu_gfx940_op_V_CVT_F32_F16, +amdgpu_gfx940_op_V_CVT_F32_F64, +amdgpu_gfx940_op_V_CVT_F32_FP8, +amdgpu_gfx940_op_V_CVT_F32_I32, +amdgpu_gfx940_op_V_CVT_F32_U32, +amdgpu_gfx940_op_V_CVT_F32_UBYTE0, +amdgpu_gfx940_op_V_CVT_F32_UBYTE1, +amdgpu_gfx940_op_V_CVT_F32_UBYTE2, +amdgpu_gfx940_op_V_CVT_F32_UBYTE3, +amdgpu_gfx940_op_V_CVT_F64_F32, +amdgpu_gfx940_op_V_CVT_F64_I32, +amdgpu_gfx940_op_V_CVT_F64_U32, +amdgpu_gfx940_op_V_CVT_FLR_I32_F32, +amdgpu_gfx940_op_V_CVT_I16_F16, +amdgpu_gfx940_op_V_CVT_I32_F32, +amdgpu_gfx940_op_V_CVT_I32_F64, +amdgpu_gfx940_op_V_CVT_NORM_I16_F16, +amdgpu_gfx940_op_V_CVT_NORM_U16_F16, +amdgpu_gfx940_op_V_CVT_OFF_F32_I4, +amdgpu_gfx940_op_V_CVT_PKACCUM_U8_F32, +amdgpu_gfx940_op_V_CVT_PKNORM_I16_F16, +amdgpu_gfx940_op_V_CVT_PKNORM_I16_F32, +amdgpu_gfx940_op_V_CVT_PKNORM_U16_F16, +amdgpu_gfx940_op_V_CVT_PKNORM_U16_F32, +amdgpu_gfx940_op_V_CVT_PKRTZ_F16_F32, +amdgpu_gfx940_op_V_CVT_PK_BF8_F32, +amdgpu_gfx940_op_V_CVT_PK_F32_BF8, +amdgpu_gfx940_op_V_CVT_PK_F32_FP8, +amdgpu_gfx940_op_V_CVT_PK_FP8_F32, +amdgpu_gfx940_op_V_CVT_PK_I16_I32, +amdgpu_gfx940_op_V_CVT_PK_U16_U32, +amdgpu_gfx940_op_V_CVT_PK_U8_F32, +amdgpu_gfx940_op_V_CVT_RPI_I32_F32, +amdgpu_gfx940_op_V_CVT_SR_BF8_F32, +amdgpu_gfx940_op_V_CVT_SR_FP8_F32, +amdgpu_gfx940_op_V_CVT_U16_F16, +amdgpu_gfx940_op_V_CVT_U32_F32, +amdgpu_gfx940_op_V_CVT_U32_F64, +amdgpu_gfx940_op_V_DIV_FIXUP_F16, +amdgpu_gfx940_op_V_DIV_FIXUP_F32, +amdgpu_gfx940_op_V_DIV_FIXUP_F64, +amdgpu_gfx940_op_V_DIV_FIXUP_LEGACY_F16, +amdgpu_gfx940_op_V_DIV_FMAS_F32, +amdgpu_gfx940_op_V_DIV_FMAS_F64, +amdgpu_gfx940_op_V_DIV_SCALE_F32, +amdgpu_gfx940_op_V_DIV_SCALE_F64, +amdgpu_gfx940_op_V_DOT2C_F32_F16, +amdgpu_gfx940_op_V_DOT2C_I32_I16, +amdgpu_gfx940_op_V_DOT2_F32_F16, +amdgpu_gfx940_op_V_DOT2_I32_I16, +amdgpu_gfx940_op_V_DOT2_U32_U16, +amdgpu_gfx940_op_V_DOT4C_I32_I8, +amdgpu_gfx940_op_V_DOT4_I32_I8, +amdgpu_gfx940_op_V_DOT4_U32_U8, +amdgpu_gfx940_op_V_DOT8C_I32_I4, +amdgpu_gfx940_op_V_DOT8_I32_I4, +amdgpu_gfx940_op_V_DOT8_U32_U4, +amdgpu_gfx940_op_V_EXP_F16, +amdgpu_gfx940_op_V_EXP_F32, +amdgpu_gfx940_op_V_EXP_LEGACY_F32, +amdgpu_gfx940_op_V_FFBH_I32, +amdgpu_gfx940_op_V_FFBH_U32, +amdgpu_gfx940_op_V_FFBL_B32, +amdgpu_gfx940_op_V_FLOOR_F16, +amdgpu_gfx940_op_V_FLOOR_F32, +amdgpu_gfx940_op_V_FLOOR_F64, +amdgpu_gfx940_op_V_FMAAK_F32, +amdgpu_gfx940_op_V_FMAC_F32, +amdgpu_gfx940_op_V_FMAC_F64, +amdgpu_gfx940_op_V_FMAMK_F32, +amdgpu_gfx940_op_V_FMA_F16, +amdgpu_gfx940_op_V_FMA_F32, +amdgpu_gfx940_op_V_FMA_F64, +amdgpu_gfx940_op_V_FMA_LEGACY_F16, +amdgpu_gfx940_op_V_FRACT_F16, +amdgpu_gfx940_op_V_FRACT_F32, +amdgpu_gfx940_op_V_FRACT_F64, +amdgpu_gfx940_op_V_FREXP_EXP_I16_F16, +amdgpu_gfx940_op_V_FREXP_EXP_I32_F32, +amdgpu_gfx940_op_V_FREXP_EXP_I32_F64, +amdgpu_gfx940_op_V_FREXP_MANT_F16, +amdgpu_gfx940_op_V_FREXP_MANT_F32, +amdgpu_gfx940_op_V_FREXP_MANT_F64, +amdgpu_gfx940_op_V_LDEXP_F16, +amdgpu_gfx940_op_V_LDEXP_F32, +amdgpu_gfx940_op_V_LDEXP_F64, +amdgpu_gfx940_op_V_LERP_U8, +amdgpu_gfx940_op_V_LOG_F16, +amdgpu_gfx940_op_V_LOG_F32, +amdgpu_gfx940_op_V_LOG_LEGACY_F32, +amdgpu_gfx940_op_V_LSHLREV_B16, +amdgpu_gfx940_op_V_LSHLREV_B32, +amdgpu_gfx940_op_V_LSHLREV_B64, +amdgpu_gfx940_op_V_LSHL_ADD_U32, +amdgpu_gfx940_op_V_LSHL_ADD_U64, +amdgpu_gfx940_op_V_LSHL_OR_B32, +amdgpu_gfx940_op_V_LSHRREV_B16, +amdgpu_gfx940_op_V_LSHRREV_B32, +amdgpu_gfx940_op_V_LSHRREV_B64, +amdgpu_gfx940_op_V_MAC_F16, +amdgpu_gfx940_op_V_MADAK_F16, +amdgpu_gfx940_op_V_MADMK_F16, +amdgpu_gfx940_op_V_MAD_F16, +amdgpu_gfx940_op_V_MAD_I16, +amdgpu_gfx940_op_V_MAD_I32_I16, +amdgpu_gfx940_op_V_MAD_I32_I24, +amdgpu_gfx940_op_V_MAD_I64_I32, +amdgpu_gfx940_op_V_MAD_LEGACY_F16, +amdgpu_gfx940_op_V_MAD_LEGACY_I16, +amdgpu_gfx940_op_V_MAD_LEGACY_U16, +amdgpu_gfx940_op_V_MAD_MIXHI_F16, +amdgpu_gfx940_op_V_MAD_MIXLO_F16, +amdgpu_gfx940_op_V_MAD_MIX_F32, +amdgpu_gfx940_op_V_MAD_U16, +amdgpu_gfx940_op_V_MAD_U32_U16, +amdgpu_gfx940_op_V_MAD_U32_U24, +amdgpu_gfx940_op_V_MAD_U64_U32, +amdgpu_gfx940_op_V_MAX3_F16, +amdgpu_gfx940_op_V_MAX3_F32, +amdgpu_gfx940_op_V_MAX3_I16, +amdgpu_gfx940_op_V_MAX3_I32, +amdgpu_gfx940_op_V_MAX3_U16, +amdgpu_gfx940_op_V_MAX3_U32, +amdgpu_gfx940_op_V_MAX_F16, +amdgpu_gfx940_op_V_MAX_F32, +amdgpu_gfx940_op_V_MAX_F64, +amdgpu_gfx940_op_V_MAX_I16, +amdgpu_gfx940_op_V_MAX_I32, +amdgpu_gfx940_op_V_MAX_U16, +amdgpu_gfx940_op_V_MAX_U32, +amdgpu_gfx940_op_V_MBCNT_HI_U32_B32, +amdgpu_gfx940_op_V_MBCNT_LO_U32_B32, +amdgpu_gfx940_op_V_MED3_F16, +amdgpu_gfx940_op_V_MED3_F32, +amdgpu_gfx940_op_V_MED3_I16, +amdgpu_gfx940_op_V_MED3_I32, +amdgpu_gfx940_op_V_MED3_U16, +amdgpu_gfx940_op_V_MED3_U32, +amdgpu_gfx940_op_V_MFMA_F32_16X16X16_BF16, +amdgpu_gfx940_op_V_MFMA_F32_16X16X16_F16, +amdgpu_gfx940_op_V_MFMA_F32_16X16X1_4B_F32, +amdgpu_gfx940_op_V_MFMA_F32_16X16X32_BF8_BF8, +amdgpu_gfx940_op_V_MFMA_F32_16X16X32_BF8_FP8, +amdgpu_gfx940_op_V_MFMA_F32_16X16X32_FP8_BF8, +amdgpu_gfx940_op_V_MFMA_F32_16X16X32_FP8_FP8, +amdgpu_gfx940_op_V_MFMA_F32_16X16X4_4B_BF16, +amdgpu_gfx940_op_V_MFMA_F32_16X16X4_4B_F16, +amdgpu_gfx940_op_V_MFMA_F32_16X16X4_F32, +amdgpu_gfx940_op_V_MFMA_F32_16X16X8_XF32, +amdgpu_gfx940_op_V_MFMA_F32_32X32X16_BF8_BF8, +amdgpu_gfx940_op_V_MFMA_F32_32X32X16_BF8_FP8, +amdgpu_gfx940_op_V_MFMA_F32_32X32X16_FP8_BF8, +amdgpu_gfx940_op_V_MFMA_F32_32X32X16_FP8_FP8, +amdgpu_gfx940_op_V_MFMA_F32_32X32X1_2B_F32, +amdgpu_gfx940_op_V_MFMA_F32_32X32X2_F32, +amdgpu_gfx940_op_V_MFMA_F32_32X32X4_2B_BF16, +amdgpu_gfx940_op_V_MFMA_F32_32X32X4_2B_F16, +amdgpu_gfx940_op_V_MFMA_F32_32X32X4_XF32, +amdgpu_gfx940_op_V_MFMA_F32_32X32X8_BF16, +amdgpu_gfx940_op_V_MFMA_F32_32X32X8_F16, +amdgpu_gfx940_op_V_MFMA_F32_4X4X1_16B_F32, +amdgpu_gfx940_op_V_MFMA_F32_4X4X4_16B_BF16, +amdgpu_gfx940_op_V_MFMA_F32_4X4X4_16B_F16, +amdgpu_gfx940_op_V_MFMA_F64_16X16X4_F64, +amdgpu_gfx940_op_V_MFMA_F64_4X4X4_4B_F64, +amdgpu_gfx940_op_V_MFMA_I32_16X16X32_I8, +amdgpu_gfx940_op_V_MFMA_I32_16X16X4_4B_I8, +amdgpu_gfx940_op_V_MFMA_I32_32X32X16_I8, +amdgpu_gfx940_op_V_MFMA_I32_32X32X4_2B_I8, +amdgpu_gfx940_op_V_MFMA_I32_4X4X4_16B_I8, +amdgpu_gfx940_op_V_MIN3_F16, +amdgpu_gfx940_op_V_MIN3_F32, +amdgpu_gfx940_op_V_MIN3_I16, +amdgpu_gfx940_op_V_MIN3_I32, +amdgpu_gfx940_op_V_MIN3_U16, +amdgpu_gfx940_op_V_MIN3_U32, +amdgpu_gfx940_op_V_MIN_F16, +amdgpu_gfx940_op_V_MIN_F32, +amdgpu_gfx940_op_V_MIN_F64, +amdgpu_gfx940_op_V_MIN_I16, +amdgpu_gfx940_op_V_MIN_I32, +amdgpu_gfx940_op_V_MIN_U16, +amdgpu_gfx940_op_V_MIN_U32, +amdgpu_gfx940_op_V_MOV_B32, +amdgpu_gfx940_op_V_MOV_B64, +amdgpu_gfx940_op_V_MQSAD_PK_U16_U8, +amdgpu_gfx940_op_V_MQSAD_U32_U8, +amdgpu_gfx940_op_V_MSAD_U8, +amdgpu_gfx940_op_V_MUL_F16, +amdgpu_gfx940_op_V_MUL_F32, +amdgpu_gfx940_op_V_MUL_F64, +amdgpu_gfx940_op_V_MUL_HI_I32, +amdgpu_gfx940_op_V_MUL_HI_I32_I24, +amdgpu_gfx940_op_V_MUL_HI_U32, +amdgpu_gfx940_op_V_MUL_HI_U32_U24, +amdgpu_gfx940_op_V_MUL_I32_I24, +amdgpu_gfx940_op_V_MUL_LEGACY_F32, +amdgpu_gfx940_op_V_MUL_LO_U16, +amdgpu_gfx940_op_V_MUL_LO_U32, +amdgpu_gfx940_op_V_MUL_U32_U24, +amdgpu_gfx940_op_V_NOP, +amdgpu_gfx940_op_V_NOT_B32, +amdgpu_gfx940_op_V_OR3_B32, +amdgpu_gfx940_op_V_OR_B32, +amdgpu_gfx940_op_V_PACK_B32_F16, +amdgpu_gfx940_op_V_PERM_B32, +amdgpu_gfx940_op_V_PK_ADD_F16, +amdgpu_gfx940_op_V_PK_ADD_F32, +amdgpu_gfx940_op_V_PK_ADD_I16, +amdgpu_gfx940_op_V_PK_ADD_U16, +amdgpu_gfx940_op_V_PK_ASHRREV_I16, +amdgpu_gfx940_op_V_PK_FMAC_F16, +amdgpu_gfx940_op_V_PK_FMA_F16, +amdgpu_gfx940_op_V_PK_FMA_F32, +amdgpu_gfx940_op_V_PK_LSHLREV_B16, +amdgpu_gfx940_op_V_PK_LSHRREV_B16, +amdgpu_gfx940_op_V_PK_MAD_I16, +amdgpu_gfx940_op_V_PK_MAD_U16, +amdgpu_gfx940_op_V_PK_MAX_F16, +amdgpu_gfx940_op_V_PK_MAX_I16, +amdgpu_gfx940_op_V_PK_MAX_U16, +amdgpu_gfx940_op_V_PK_MIN_F16, +amdgpu_gfx940_op_V_PK_MIN_I16, +amdgpu_gfx940_op_V_PK_MIN_U16, +amdgpu_gfx940_op_V_PK_MOV_B32, +amdgpu_gfx940_op_V_PK_MUL_F16, +amdgpu_gfx940_op_V_PK_MUL_F32, +amdgpu_gfx940_op_V_PK_MUL_LO_U16, +amdgpu_gfx940_op_V_PK_SUB_I16, +amdgpu_gfx940_op_V_PK_SUB_U16, +amdgpu_gfx940_op_V_QSAD_PK_U16_U8, +amdgpu_gfx940_op_V_RCP_F16, +amdgpu_gfx940_op_V_RCP_F32, +amdgpu_gfx940_op_V_RCP_F64, +amdgpu_gfx940_op_V_RCP_IFLAG_F32, +amdgpu_gfx940_op_V_READFIRSTLANE_B32, +amdgpu_gfx940_op_V_READLANE_B32, +amdgpu_gfx940_op_V_RNDNE_F16, +amdgpu_gfx940_op_V_RNDNE_F32, +amdgpu_gfx940_op_V_RNDNE_F64, +amdgpu_gfx940_op_V_RSQ_F16, +amdgpu_gfx940_op_V_RSQ_F32, +amdgpu_gfx940_op_V_RSQ_F64, +amdgpu_gfx940_op_V_SAD_HI_U8, +amdgpu_gfx940_op_V_SAD_U16, +amdgpu_gfx940_op_V_SAD_U32, +amdgpu_gfx940_op_V_SAD_U8, +amdgpu_gfx940_op_V_SAT_PK_U8_I16, +amdgpu_gfx940_op_V_SCREEN_PARTITION_4SE_B32, +amdgpu_gfx940_op_V_SIN_F16, +amdgpu_gfx940_op_V_SIN_F32, +amdgpu_gfx940_op_V_SMFMAC_F32_16X16X32_BF16, +amdgpu_gfx940_op_V_SMFMAC_F32_16X16X32_F16, +amdgpu_gfx940_op_V_SMFMAC_F32_16X16X64_BF8_BF8, +amdgpu_gfx940_op_V_SMFMAC_F32_16X16X64_BF8_FP8, +amdgpu_gfx940_op_V_SMFMAC_F32_16X16X64_FP8_BF8, +amdgpu_gfx940_op_V_SMFMAC_F32_16X16X64_FP8_FP8, +amdgpu_gfx940_op_V_SMFMAC_F32_32X32X16_BF16, +amdgpu_gfx940_op_V_SMFMAC_F32_32X32X16_F16, +amdgpu_gfx940_op_V_SMFMAC_F32_32X32X32_BF8_BF8, +amdgpu_gfx940_op_V_SMFMAC_F32_32X32X32_BF8_FP8, +amdgpu_gfx940_op_V_SMFMAC_F32_32X32X32_FP8_BF8, +amdgpu_gfx940_op_V_SMFMAC_F32_32X32X32_FP8_FP8, +amdgpu_gfx940_op_V_SMFMAC_I32_16X16X64_I8, +amdgpu_gfx940_op_V_SMFMAC_I32_32X32X32_I8, +amdgpu_gfx940_op_V_SQRT_F16, +amdgpu_gfx940_op_V_SQRT_F32, +amdgpu_gfx940_op_V_SQRT_F64, +amdgpu_gfx940_op_V_SUBBREV_CO_U32, +amdgpu_gfx940_op_V_SUBB_CO_U32, +amdgpu_gfx940_op_V_SUBREV_CO_U32, +amdgpu_gfx940_op_V_SUBREV_F16, +amdgpu_gfx940_op_V_SUBREV_F32, +amdgpu_gfx940_op_V_SUBREV_U16, +amdgpu_gfx940_op_V_SUBREV_U32, +amdgpu_gfx940_op_V_SUB_CO_U32, +amdgpu_gfx940_op_V_SUB_F16, +amdgpu_gfx940_op_V_SUB_F32, +amdgpu_gfx940_op_V_SUB_I16, +amdgpu_gfx940_op_V_SUB_I32, +amdgpu_gfx940_op_V_SUB_U16, +amdgpu_gfx940_op_V_SUB_U32, +amdgpu_gfx940_op_V_SWAP_B32, +amdgpu_gfx940_op_V_TRIG_PREOP_F64, +amdgpu_gfx940_op_V_TRUNC_F16, +amdgpu_gfx940_op_V_TRUNC_F32, +amdgpu_gfx940_op_V_TRUNC_F64, +amdgpu_gfx940_op_V_WRITELANE_B32, +amdgpu_gfx940_op_V_XAD_U32, +amdgpu_gfx940_op_V_XNOR_B32, +amdgpu_gfx940_op_V_XOR_B32, diff --git a/common/h/mnemonics/IntelGPU/generic_entryIDs.h b/common/h/mnemonics/IntelGPU/generic_entryIDs.h new file mode 100644 index 0000000000..b48bbdd09b --- /dev/null +++ b/common/h/mnemonics/IntelGPU/generic_entryIDs.h @@ -0,0 +1 @@ +intel_gpu_op_general, diff --git a/common/h/mnemonics/NVIDIA/generic_entryIDs.h b/common/h/mnemonics/NVIDIA/generic_entryIDs.h new file mode 100644 index 0000000000..acc3b9769f --- /dev/null +++ b/common/h/mnemonics/NVIDIA/generic_entryIDs.h @@ -0,0 +1,2 @@ +cuda_op_general, +cuda_op_call, diff --git a/common/h/mnemonics/aarch64_entryIDs.h b/common/h/mnemonics/aarch64_entryIDs.h new file mode 100644 index 0000000000..e2f2f63af8 --- /dev/null +++ b/common/h/mnemonics/aarch64_entryIDs.h @@ -0,0 +1,576 @@ +aarch64_op_INVALID, +aarch64_op_abs_advsimd, +aarch64_op_adc, +aarch64_op_adcs, +aarch64_op_add_addsub_ext, +aarch64_op_add_addsub_imm, +aarch64_op_add_addsub_shift, +aarch64_op_add_advsimd, +aarch64_op_addhn_advsimd, +aarch64_op_addp_advsimd_pair, +aarch64_op_addp_advsimd_vec, +aarch64_op_adds_addsub_ext, +aarch64_op_adds_addsub_imm, +aarch64_op_adds_addsub_shift, +aarch64_op_addv_advsimd, +aarch64_op_adr, +aarch64_op_adrp, +aarch64_op_aesd_advsimd, +aarch64_op_aese_advsimd, +aarch64_op_aesimc_advsimd, +aarch64_op_aesmc_advsimd, +aarch64_op_and_advsimd, +aarch64_op_and_log_imm, +aarch64_op_and_log_shift, +aarch64_op_ands_log_imm, +aarch64_op_ands_log_shift, +aarch64_op_asr_asrv, +aarch64_op_asr_sbfm, +aarch64_op_asrv, +aarch64_op_at_sys, +aarch64_op_b_cond, +aarch64_op_b_uncond, +aarch64_op_bfi_bfm, +aarch64_op_bfm, +aarch64_op_bfxil_bfm, +aarch64_op_bic_advsimd_imm, +aarch64_op_bic_advsimd_reg, +aarch64_op_bic_log_shift, +aarch64_op_bics, +aarch64_op_bif_advsimd, +aarch64_op_bit_advsimd, +aarch64_op_bl, +aarch64_op_blr, +aarch64_op_br, +aarch64_op_brk, +aarch64_op_bsl_advsimd, +aarch64_op_cbnz, +aarch64_op_cbz, +aarch64_op_ccmn_imm, +aarch64_op_ccmn_reg, +aarch64_op_ccmp_imm, +aarch64_op_ccmp_reg, +aarch64_op_cinc_csinc, +aarch64_op_cinv_csinv, +aarch64_op_clrex, +aarch64_op_cls_advsimd, +aarch64_op_cls_int, +aarch64_op_clz_advsimd, +aarch64_op_clz_int, +aarch64_op_cmeq_advsimd_reg, +aarch64_op_cmeq_advsimd_zero, +aarch64_op_cmge_advsimd_reg, +aarch64_op_cmge_advsimd_zero, +aarch64_op_cmgt_advsimd_reg, +aarch64_op_cmgt_advsimd_zero, +aarch64_op_cmhi_advsimd, +aarch64_op_cmhs_advsimd, +aarch64_op_cmle_advsimd, +aarch64_op_cmlt_advsimd, +aarch64_op_cmn_adds_addsub_ext, +aarch64_op_cmn_adds_addsub_imm, +aarch64_op_cmn_adds_addsub_shift, +aarch64_op_cmp_subs_addsub_ext, +aarch64_op_cmp_subs_addsub_imm, +aarch64_op_cmp_subs_addsub_shift, +aarch64_op_cmtst_advsimd, +aarch64_op_cneg_csneg, +aarch64_op_cnt_advsimd, +aarch64_op_crc32, +aarch64_op_crc32c, +aarch64_op_csel, +aarch64_op_cset_csinc, +aarch64_op_csetm_csinv, +aarch64_op_csinc, +aarch64_op_csinv, +aarch64_op_csneg, +aarch64_op_dc_sys, +aarch64_op_dcps1, +aarch64_op_dcps2, +aarch64_op_dcps3, +aarch64_op_dmb, +aarch64_op_drps, +aarch64_op_dsb, +aarch64_op_dup_advsimd_elt, +aarch64_op_dup_advsimd_gen, +aarch64_op_eon, +aarch64_op_eor_advsimd, +aarch64_op_eor_log_imm, +aarch64_op_eor_log_shift, +aarch64_op_eret, +aarch64_op_ext_advsimd, +aarch64_op_extended, +aarch64_op_extr, +aarch64_op_fabd_advsimd, +aarch64_op_fabs_advsimd, +aarch64_op_fabs_float, +aarch64_op_facge_advsimd, +aarch64_op_facgt_advsimd, +aarch64_op_fadd_advsimd, +aarch64_op_fadd_float, +aarch64_op_faddp_advsimd_pair, +aarch64_op_faddp_advsimd_vec, +aarch64_op_fccmp_float, +aarch64_op_fccmpe_float, +aarch64_op_fcmeq_advsimd_reg, +aarch64_op_fcmeq_advsimd_zero, +aarch64_op_fcmge_advsimd_reg, +aarch64_op_fcmge_advsimd_zero, +aarch64_op_fcmgt_advsimd_reg, +aarch64_op_fcmgt_advsimd_zero, +aarch64_op_fcmle_advsimd, +aarch64_op_fcmlt_advsimd, +aarch64_op_fcmp_float, +aarch64_op_fcmpe_float, +aarch64_op_fcsel_float, +aarch64_op_fcvt_float, +aarch64_op_fcvtas_advsimd, +aarch64_op_fcvtas_float, +aarch64_op_fcvtau_advsimd, +aarch64_op_fcvtau_float, +aarch64_op_fcvtl_advsimd, +aarch64_op_fcvtms_advsimd, +aarch64_op_fcvtms_float, +aarch64_op_fcvtmu_advsimd, +aarch64_op_fcvtmu_float, +aarch64_op_fcvtn_advsimd, +aarch64_op_fcvtns_advsimd, +aarch64_op_fcvtns_float, +aarch64_op_fcvtnu_advsimd, +aarch64_op_fcvtnu_float, +aarch64_op_fcvtps_advsimd, +aarch64_op_fcvtps_float, +aarch64_op_fcvtpu_advsimd, +aarch64_op_fcvtpu_float, +aarch64_op_fcvtxn_advsimd, +aarch64_op_fcvtzs_advsimd_fix, +aarch64_op_fcvtzs_advsimd_int, +aarch64_op_fcvtzs_float_fix, +aarch64_op_fcvtzs_float_int, +aarch64_op_fcvtzu_advsimd_fix, +aarch64_op_fcvtzu_advsimd_int, +aarch64_op_fcvtzu_float_fix, +aarch64_op_fcvtzu_float_int, +aarch64_op_fdiv_advsimd, +aarch64_op_fdiv_float, +aarch64_op_fmadd_float, +aarch64_op_fmax_advsimd, +aarch64_op_fmax_float, +aarch64_op_fmaxnm_advsimd, +aarch64_op_fmaxnm_float, +aarch64_op_fmaxnmp_advsimd_pair, +aarch64_op_fmaxnmp_advsimd_vec, +aarch64_op_fmaxnmv_advsimd, +aarch64_op_fmaxp_advsimd_pair, +aarch64_op_fmaxp_advsimd_vec, +aarch64_op_fmaxv_advsimd, +aarch64_op_fmin_advsimd, +aarch64_op_fmin_float, +aarch64_op_fminnm_advsimd, +aarch64_op_fminnm_float, +aarch64_op_fminnmp_advsimd_pair, +aarch64_op_fminnmp_advsimd_vec, +aarch64_op_fminnmv_advsimd, +aarch64_op_fminp_advsimd_pair, +aarch64_op_fminp_advsimd_vec, +aarch64_op_fminv_advsimd, +aarch64_op_fmla_advsimd_elt, +aarch64_op_fmla_advsimd_vec, +aarch64_op_fmls_advsimd_elt, +aarch64_op_fmls_advsimd_vec, +aarch64_op_fmov_advsimd, +aarch64_op_fmov_float, +aarch64_op_fmov_float_gen, +aarch64_op_fmov_float_imm, +aarch64_op_fmsub_float, +aarch64_op_fmul_advsimd_elt, +aarch64_op_fmul_advsimd_vec, +aarch64_op_fmul_float, +aarch64_op_fmulx_advsimd_elt, +aarch64_op_fmulx_advsimd_vec, +aarch64_op_fneg_advsimd, +aarch64_op_fneg_float, +aarch64_op_fnmadd_float, +aarch64_op_fnmsub_float, +aarch64_op_fnmul_float, +aarch64_op_frecpe_advsimd, +aarch64_op_frecps_advsimd, +aarch64_op_frecpx_advsimd, +aarch64_op_frinta_advsimd, +aarch64_op_frinta_float, +aarch64_op_frinti_advsimd, +aarch64_op_frinti_float, +aarch64_op_frintm_advsimd, +aarch64_op_frintm_float, +aarch64_op_frintn_advsimd, +aarch64_op_frintn_float, +aarch64_op_frintp_advsimd, +aarch64_op_frintp_float, +aarch64_op_frintx_advsimd, +aarch64_op_frintx_float, +aarch64_op_frintz_advsimd, +aarch64_op_frintz_float, +aarch64_op_frsqrte_advsimd, +aarch64_op_frsqrts_advsimd, +aarch64_op_fsqrt_advsimd, +aarch64_op_fsqrt_float, +aarch64_op_fsub_advsimd, +aarch64_op_fsub_float, +aarch64_op_hint, +aarch64_op_hlt, +aarch64_op_hvc, +aarch64_op_ic_sys, +aarch64_op_ins_advsimd_elt, +aarch64_op_ins_advsimd_gen, +aarch64_op_isb, +aarch64_op_ld1_advsimd_mult, +aarch64_op_ld1_advsimd_sngl, +aarch64_op_ld1r_advsimd, +aarch64_op_ld2_advsimd_mult, +aarch64_op_ld2_advsimd_sngl, +aarch64_op_ld2r_advsimd, +aarch64_op_ld3_advsimd_mult, +aarch64_op_ld3_advsimd_sngl, +aarch64_op_ld3r_advsimd, +aarch64_op_ld4_advsimd_mult, +aarch64_op_ld4_advsimd_sngl, +aarch64_op_ld4r_advsimd, +aarch64_op_ldar, +aarch64_op_ldarb, +aarch64_op_ldarh, +aarch64_op_ldaxp, +aarch64_op_ldaxr, +aarch64_op_ldaxrb, +aarch64_op_ldaxrh, +aarch64_op_ldnp_fpsimd, +aarch64_op_ldnp_gen, +aarch64_op_ldp_fpsimd, +aarch64_op_ldp_gen, +aarch64_op_ldpsw, +aarch64_op_ldr_imm_fpsimd, +aarch64_op_ldr_imm_gen, +aarch64_op_ldr_lit_fpsimd, +aarch64_op_ldr_lit_gen, +aarch64_op_ldr_reg_fpsimd, +aarch64_op_ldr_reg_gen, +aarch64_op_ldrb_imm, +aarch64_op_ldrb_reg, +aarch64_op_ldrh_imm, +aarch64_op_ldrh_reg, +aarch64_op_ldrsb_imm, +aarch64_op_ldrsb_reg, +aarch64_op_ldrsh_imm, +aarch64_op_ldrsh_reg, +aarch64_op_ldrsw_imm, +aarch64_op_ldrsw_lit, +aarch64_op_ldrsw_reg, +aarch64_op_ldtr, +aarch64_op_ldtrb, +aarch64_op_ldtrh, +aarch64_op_ldtrsb, +aarch64_op_ldtrsh, +aarch64_op_ldtrsw, +aarch64_op_ldur_fpsimd, +aarch64_op_ldur_gen, +aarch64_op_ldurb, +aarch64_op_ldurh, +aarch64_op_ldursb, +aarch64_op_ldursh, +aarch64_op_ldursw, +aarch64_op_ldxp, +aarch64_op_ldxr, +aarch64_op_ldxrb, +aarch64_op_ldxrh, +aarch64_op_lsl_lslv, +aarch64_op_lsl_ubfm, +aarch64_op_lslv, +aarch64_op_lsr_lsrv, +aarch64_op_lsr_ubfm, +aarch64_op_lsrv, +aarch64_op_madd, +aarch64_op_mla_advsimd_elt, +aarch64_op_mla_advsimd_vec, +aarch64_op_mls_advsimd_elt, +aarch64_op_mls_advsimd_vec, +aarch64_op_mneg_msub, +aarch64_op_mov_add_addsub_imm, +aarch64_op_mov_dup_advsimd_elt, +aarch64_op_mov_ins_advsimd_elt, +aarch64_op_mov_ins_advsimd_gen, +aarch64_op_mov_movn, +aarch64_op_mov_movz, +aarch64_op_mov_orr_advsimd_reg, +aarch64_op_mov_orr_log_imm, +aarch64_op_mov_orr_log_shift, +aarch64_op_mov_umov_advsimd, +aarch64_op_movi_advsimd, +aarch64_op_movk, +aarch64_op_movn, +aarch64_op_movz, +aarch64_op_mrs, +aarch64_op_msr_imm, +aarch64_op_msr_reg, +aarch64_op_msub, +aarch64_op_mul_advsimd_elt, +aarch64_op_mul_advsimd_vec, +aarch64_op_mul_madd, +aarch64_op_mvn_not_advsimd, +aarch64_op_mvn_orn_log_shift, +aarch64_op_mvni_advsimd, +aarch64_op_neg_advsimd, +aarch64_op_neg_sub_addsub_shift, +aarch64_op_negs_subs_addsub_shift, +aarch64_op_ngc_sbc, +aarch64_op_ngcs_sbcs, +aarch64_op_nop_hint, +aarch64_op_not_advsimd, +aarch64_op_orn_advsimd, +aarch64_op_orn_log_shift, +aarch64_op_orr_advsimd_imm, +aarch64_op_orr_advsimd_reg, +aarch64_op_orr_log_imm, +aarch64_op_orr_log_shift, +aarch64_op_pmul_advsimd, +aarch64_op_pmull_advsimd, +aarch64_op_prfm_imm, +aarch64_op_prfm_lit, +aarch64_op_prfm_reg, +aarch64_op_prfum, +aarch64_op_raddhn_advsimd, +aarch64_op_rbit_advsimd, +aarch64_op_rbit_int, +aarch64_op_ret, +aarch64_op_rev, +aarch64_op_rev16_advsimd, +aarch64_op_rev16_int, +aarch64_op_rev32_advsimd, +aarch64_op_rev32_int, +aarch64_op_rev64_advsimd, +aarch64_op_ror_extr, +aarch64_op_ror_rorv, +aarch64_op_rorv, +aarch64_op_rshrn_advsimd, +aarch64_op_rsubhn_advsimd, +aarch64_op_saba_advsimd, +aarch64_op_sabal_advsimd, +aarch64_op_sabd_advsimd, +aarch64_op_sabdl_advsimd, +aarch64_op_sadalp_advsimd, +aarch64_op_saddl_advsimd, +aarch64_op_saddlp_advsimd, +aarch64_op_saddlv_advsimd, +aarch64_op_saddw_advsimd, +aarch64_op_sbc, +aarch64_op_sbcs, +aarch64_op_sbfiz_sbfm, +aarch64_op_sbfm, +aarch64_op_sbfx_sbfm, +aarch64_op_scvtf_advsimd_fix, +aarch64_op_scvtf_advsimd_int, +aarch64_op_scvtf_float_fix, +aarch64_op_scvtf_float_int, +aarch64_op_sdiv, +aarch64_op_sev_hint, +aarch64_op_sevl_hint, +aarch64_op_sha1c_advsimd, +aarch64_op_sha1h_advsimd, +aarch64_op_sha1m_advsimd, +aarch64_op_sha1p_advsimd, +aarch64_op_sha1su0_advsimd, +aarch64_op_sha1su1_advsimd, +aarch64_op_sha256h2_advsimd, +aarch64_op_sha256h_advsimd, +aarch64_op_sha256su0_advsimd, +aarch64_op_sha256su1_advsimd, +aarch64_op_shadd_advsimd, +aarch64_op_shl_advsimd, +aarch64_op_shll_advsimd, +aarch64_op_shrn_advsimd, +aarch64_op_shsub_advsimd, +aarch64_op_sli_advsimd, +aarch64_op_smaddl, +aarch64_op_smax_advsimd, +aarch64_op_smaxp_advsimd, +aarch64_op_smaxv_advsimd, +aarch64_op_smc, +aarch64_op_smin_advsimd, +aarch64_op_sminp_advsimd, +aarch64_op_sminv_advsimd, +aarch64_op_smlal_advsimd_elt, +aarch64_op_smlal_advsimd_vec, +aarch64_op_smlsl_advsimd_elt, +aarch64_op_smlsl_advsimd_vec, +aarch64_op_smnegl_smsubl, +aarch64_op_smov_advsimd, +aarch64_op_smsubl, +aarch64_op_smulh, +aarch64_op_smull_advsimd_elt, +aarch64_op_smull_advsimd_vec, +aarch64_op_smull_smaddl, +aarch64_op_sqabs_advsimd, +aarch64_op_sqadd_advsimd, +aarch64_op_sqdmlal_advsimd_elt, +aarch64_op_sqdmlal_advsimd_vec, +aarch64_op_sqdmlsl_advsimd_elt, +aarch64_op_sqdmlsl_advsimd_vec, +aarch64_op_sqdmulh_advsimd_elt, +aarch64_op_sqdmulh_advsimd_vec, +aarch64_op_sqdmull_advsimd_elt, +aarch64_op_sqdmull_advsimd_vec, +aarch64_op_sqneg_advsimd, +aarch64_op_sqrdmulh_advsimd_elt, +aarch64_op_sqrdmulh_advsimd_vec, +aarch64_op_sqrshl_advsimd, +aarch64_op_sqrshrn_advsimd, +aarch64_op_sqrshrun_advsimd, +aarch64_op_sqshl_advsimd_imm, +aarch64_op_sqshl_advsimd_reg, +aarch64_op_sqshlu_advsimd, +aarch64_op_sqshrn_advsimd, +aarch64_op_sqshrun_advsimd, +aarch64_op_sqsub_advsimd, +aarch64_op_sqxtn_advsimd, +aarch64_op_sqxtun_advsimd, +aarch64_op_srhadd_advsimd, +aarch64_op_sri_advsimd, +aarch64_op_srshl_advsimd, +aarch64_op_srshr_advsimd, +aarch64_op_srsra_advsimd, +aarch64_op_sshl_advsimd, +aarch64_op_sshll_advsimd, +aarch64_op_sshr_advsimd, +aarch64_op_ssra_advsimd, +aarch64_op_ssubl_advsimd, +aarch64_op_ssubw_advsimd, +aarch64_op_st1_advsimd_mult, +aarch64_op_st1_advsimd_sngl, +aarch64_op_st2_advsimd_mult, +aarch64_op_st2_advsimd_sngl, +aarch64_op_st3_advsimd_mult, +aarch64_op_st3_advsimd_sngl, +aarch64_op_st4_advsimd_mult, +aarch64_op_st4_advsimd_sngl, +aarch64_op_stlr, +aarch64_op_stlrb, +aarch64_op_stlrh, +aarch64_op_stlxp, +aarch64_op_stlxr, +aarch64_op_stlxrb, +aarch64_op_stlxrh, +aarch64_op_stnp_fpsimd, +aarch64_op_stnp_gen, +aarch64_op_stp_fpsimd, +aarch64_op_stp_gen, +aarch64_op_str_imm_fpsimd, +aarch64_op_str_imm_gen, +aarch64_op_str_reg_fpsimd, +aarch64_op_str_reg_gen, +aarch64_op_strb_imm, +aarch64_op_strb_reg, +aarch64_op_strh_imm, +aarch64_op_strh_reg, +aarch64_op_sttr, +aarch64_op_sttrb, +aarch64_op_sttrh, +aarch64_op_stur_fpsimd, +aarch64_op_stur_gen, +aarch64_op_sturb, +aarch64_op_sturh, +aarch64_op_stxp, +aarch64_op_stxr, +aarch64_op_stxrb, +aarch64_op_stxrh, +aarch64_op_sub_addsub_ext, +aarch64_op_sub_addsub_imm, +aarch64_op_sub_addsub_shift, +aarch64_op_sub_advsimd, +aarch64_op_subhn_advsimd, +aarch64_op_subs_addsub_ext, +aarch64_op_subs_addsub_imm, +aarch64_op_subs_addsub_shift, +aarch64_op_suqadd_advsimd, +aarch64_op_svc, +aarch64_op_sxtb_sbfm, +aarch64_op_sxth_sbfm, +aarch64_op_sxtl_sshll_advsimd, +aarch64_op_sxtw_sbfm, +aarch64_op_sys, +aarch64_op_sysl, +aarch64_op_tbl_advsimd, +aarch64_op_tbnz, +aarch64_op_tbx_advsimd, +aarch64_op_tbz, +aarch64_op_tlbi_sys, +aarch64_op_trn1_advsimd, +aarch64_op_trn2_advsimd, +aarch64_op_tst_ands_log_imm, +aarch64_op_tst_ands_log_shift, +aarch64_op_uaba_advsimd, +aarch64_op_uabal_advsimd, +aarch64_op_uabd_advsimd, +aarch64_op_uabdl_advsimd, +aarch64_op_uadalp_advsimd, +aarch64_op_uaddl_advsimd, +aarch64_op_uaddlp_advsimd, +aarch64_op_uaddlv_advsimd, +aarch64_op_uaddw_advsimd, +aarch64_op_ubfiz_ubfm, +aarch64_op_ubfm, +aarch64_op_ubfx_ubfm, +aarch64_op_ucvtf_advsimd_fix, +aarch64_op_ucvtf_advsimd_int, +aarch64_op_ucvtf_float_fix, +aarch64_op_ucvtf_float_int, +aarch64_op_udiv, +aarch64_op_uhadd_advsimd, +aarch64_op_uhsub_advsimd, +aarch64_op_umaddl, +aarch64_op_umax_advsimd, +aarch64_op_umaxp_advsimd, +aarch64_op_umaxv_advsimd, +aarch64_op_umin_advsimd, +aarch64_op_uminp_advsimd, +aarch64_op_uminv_advsimd, +aarch64_op_umlal_advsimd_elt, +aarch64_op_umlal_advsimd_vec, +aarch64_op_umlsl_advsimd_elt, +aarch64_op_umlsl_advsimd_vec, +aarch64_op_umnegl_umsubl, +aarch64_op_umov_advsimd, +aarch64_op_umsubl, +aarch64_op_umulh, +aarch64_op_umull_advsimd_elt, +aarch64_op_umull_advsimd_vec, +aarch64_op_umull_umaddl, +aarch64_op_uqadd_advsimd, +aarch64_op_uqrshl_advsimd, +aarch64_op_uqrshrn_advsimd, +aarch64_op_uqshl_advsimd_imm, +aarch64_op_uqshl_advsimd_reg, +aarch64_op_uqshrn_advsimd, +aarch64_op_uqsub_advsimd, +aarch64_op_uqxtn_advsimd, +aarch64_op_urecpe_advsimd, +aarch64_op_urhadd_advsimd, +aarch64_op_urshl_advsimd, +aarch64_op_urshr_advsimd, +aarch64_op_ursqrte_advsimd, +aarch64_op_ursra_advsimd, +aarch64_op_ushl_advsimd, +aarch64_op_ushll_advsimd, +aarch64_op_ushr_advsimd, +aarch64_op_usqadd_advsimd, +aarch64_op_usra_advsimd, +aarch64_op_usubl_advsimd, +aarch64_op_usubw_advsimd, +aarch64_op_uxtb_ubfm, +aarch64_op_uxth_ubfm, +aarch64_op_uxtl_ushll_advsimd, +aarch64_op_uzp1_advsimd, +aarch64_op_uzp2_advsimd, +aarch64_op_wfe_hint, +aarch64_op_wfi_hint, +aarch64_op_xtn_advsimd, +aarch64_op_yield_hint, +aarch64_op_zip1_advsimd, +aarch64_op_zip2_advsimd, diff --git a/common/h/mnemonics/ppc_entryIDs.h b/common/h/mnemonics/ppc_entryIDs.h new file mode 100644 index 0000000000..f6b03b9488 --- /dev/null +++ b/common/h/mnemonics/ppc_entryIDs.h @@ -0,0 +1,1137 @@ +power_op_INVALID, +power_op_abs, +power_op_add, +power_op_addc, +power_op_adde, +power_op_addex, +power_op_addg6s, +power_op_addi, +power_op_addic, +power_op_addic_rc, +power_op_addis, +power_op_addme, +power_op_addze, +power_op_and, +power_op_andc, +power_op_andi_rc, +power_op_andis_rc, +power_op_b, +power_op_bc, +power_op_bcctr, +power_op_bcdadd, +power_op_bcdcfn, +power_op_bcdcfsq, +power_op_bcdcfz, +power_op_bcdcpsgn, +power_op_bcdctn, +power_op_bcdctsq, +power_op_bcdctz, +power_op_bcds, +power_op_bcdsetsgn, +power_op_bcdsr, +power_op_bcdsub, +power_op_bcdtrunc, +power_op_bcdus, +power_op_bcdutrunc, +power_op_bclr, +power_op_bpermd, +power_op_cbcdtd, +power_op_cdtbcd, +power_op_clcs, +power_op_clf, +power_op_cli, +power_op_clrbhrb, +power_op_cmp, +power_op_cmpb, +power_op_cmpeqb, +power_op_cmpi, +power_op_cmpl, +power_op_cmpli, +power_op_cmprb, +power_op_cntlzd, +power_op_cntlzw, +power_op_cnttzd, +power_op_cnttzw, +power_op_copy, +power_op_cp_abort, +power_op_crand, +power_op_crandc, +power_op_creqv, +power_op_crnand, +power_op_crnor, +power_op_cror, +power_op_crorc, +power_op_crxor, +power_op_dadd, +power_op_daddq, +power_op_darn, +power_op_dcbf, +power_op_dcbi, +power_op_dcbst, +power_op_dcbt, +power_op_dcbtst, +power_op_dcbz, +power_op_dcffix, +power_op_dcffixq, +power_op_dclst, +power_op_dcmpo, +power_op_dcmpoq, +power_op_dcmpu, +power_op_dcmpuq, +power_op_dctdp, +power_op_dctfix, +power_op_dctfixq, +power_op_dctqpq, +power_op_ddedpd, +power_op_ddedpdq, +power_op_ddiv, +power_op_ddivq, +power_op_denbcd, +power_op_denbcdq, +power_op_diex, +power_op_diexq, +power_op_div, +power_op_divd, +power_op_divde, +power_op_divdeu, +power_op_divdu, +power_op_divs, +power_op_divw, +power_op_divwe, +power_op_divweu, +power_op_divwu, +power_op_dmul, +power_op_dmulq, +power_op_doz, +power_op_dozi, +power_op_dqua, +power_op_dquai, +power_op_dquaiq, +power_op_dquaq, +power_op_drdpq, +power_op_drintn, +power_op_drintnq, +power_op_drintx, +power_op_drintxq, +power_op_drrnd, +power_op_drrndq, +power_op_drsp, +power_op_dscli, +power_op_dscliq, +power_op_dscri, +power_op_dscriq, +power_op_dsub, +power_op_dsubq, +power_op_dtstdc, +power_op_dtstdcq, +power_op_dtstdg, +power_op_dtstdgq, +power_op_dtstex, +power_op_dtstexq, +power_op_dtstsf, +power_op_dtstsfi, +power_op_dtstsfiq, +power_op_dtstsfq, +power_op_dxex, +power_op_dxexq, +power_op_eciwx, +power_op_ecowx, +power_op_eieio, +power_op_eqv, +power_op_extended, +power_op_extsb, +power_op_extsh, +power_op_extsw, +power_op_extswsl, +power_op_extswsli, +power_op_fabs, +power_op_fadd, +power_op_fadds, +power_op_fcfid, +power_op_fcfids, +power_op_fcfidu, +power_op_fcfidus, +power_op_fcmpo, +power_op_fcmpu, +power_op_fcpsgn, +power_op_fctid, +power_op_fctidu, +power_op_fctiduz, +power_op_fctidz, +power_op_fctiw, +power_op_fctiwu, +power_op_fctiwuz, +power_op_fctiwz, +power_op_fdiv, +power_op_fdivs, +power_op_fmadd, +power_op_fmadds, +power_op_fmr, +power_op_fmrgew, +power_op_fmrgow, +power_op_fmsub, +power_op_fmsubs, +power_op_fmul, +power_op_fmuls, +power_op_fnabs, +power_op_fneg, +power_op_fnmadd, +power_op_fnmadds, +power_op_fnmsub, +power_op_fnmsubs, +power_op_fpabs, +power_op_fpadd, +power_op_fpctiw, +power_op_fpctiwz, +power_op_fpmadd, +power_op_fpmr, +power_op_fpmsub, +power_op_fpmul, +power_op_fpnabs, +power_op_fpneg, +power_op_fpnmadd, +power_op_fpnmsub, +power_op_fpre, +power_op_fprsp, +power_op_fprsqrte, +power_op_fpsel, +power_op_fpsub, +power_op_fre, +power_op_fres, +power_op_frim, +power_op_frin, +power_op_frip, +power_op_friz, +power_op_frsp, +power_op_frsqrte, +power_op_frsqrtes, +power_op_fsabs, +power_op_fscmp, +power_op_fsel, +power_op_fsmfp, +power_op_fsmr, +power_op_fsmtp, +power_op_fsnabs, +power_op_fsneg, +power_op_fsqrt, +power_op_fsqrts, +power_op_fsub, +power_op_fsubs, +power_op_ftdiv, +power_op_ftsqrt, +power_op_fxcpmadd, +power_op_fxcpmsub, +power_op_fxcpnmadd, +power_op_fxcpnmsub, +power_op_fxcpnpma, +power_op_fxcpnsma, +power_op_fxcsmadd, +power_op_fxcsmsub, +power_op_fxcsnmadd, +power_op_fxcsnmsub, +power_op_fxcsnpma, +power_op_fxcsnsma, +power_op_fxcxma, +power_op_fxcxnms, +power_op_fxcxnpma, +power_op_fxcxnsma, +power_op_fxmadd, +power_op_fxmr, +power_op_fxmsub, +power_op_fxmul, +power_op_fxnmadd, +power_op_fxnmsub, +power_op_fxpmul, +power_op_fxsmul, +power_op_icbi, +power_op_icbt, +power_op_isel, +power_op_isync, +power_op_lbarx, +power_op_lbz, +power_op_lbzcix, +power_op_lbzu, +power_op_lbzux, +power_op_lbzx, +power_op_ld, +power_op_ldarx, +power_op_ldat, +power_op_ldbrx, +power_op_ldcix, +power_op_ldu, +power_op_ldux, +power_op_ldx, +power_op_lfd, +power_op_lfdpx, +power_op_lfdu, +power_op_lfdux, +power_op_lfdx, +power_op_lfiwax, +power_op_lfiwzx, +power_op_lfpdux, +power_op_lfpdx, +power_op_lfpsux, +power_op_lfpsx, +power_op_lfq, +power_op_lfqu, +power_op_lfqux, +power_op_lfqx, +power_op_lfs, +power_op_lfsdux, +power_op_lfsdx, +power_op_lfssux, +power_op_lfssx, +power_op_lfsu, +power_op_lfsux, +power_op_lfsx, +power_op_lfxdux, +power_op_lfxdx, +power_op_lfxsux, +power_op_lfxsx, +power_op_lha, +power_op_lharx, +power_op_lhau, +power_op_lhaux, +power_op_lhax, +power_op_lhbrx, +power_op_lhz, +power_op_lhzcix, +power_op_lhzu, +power_op_lhzux, +power_op_lhzx, +power_op_lmw, +power_op_lqarx, +power_op_lscbx, +power_op_lswi, +power_op_lswx, +power_op_lvebx, +power_op_lvehx, +power_op_lvewx, +power_op_lvsl, +power_op_lvsr, +power_op_lvx, +power_op_lvxl, +power_op_lwa, +power_op_lwarx, +power_op_lwat, +power_op_lwaux, +power_op_lwax, +power_op_lwbrx, +power_op_lwz, +power_op_lwzcix, +power_op_lwzu, +power_op_lwzux, +power_op_lwzx, +power_op_lxsd, +power_op_lxsdx, +power_op_lxsibzx, +power_op_lxsihzx, +power_op_lxsiwax, +power_op_lxsiwzx, +power_op_lxssp, +power_op_lxsspx, +power_op_lxvb16x, +power_op_lxvd2x, +power_op_lxvdsx, +power_op_lxvh8x, +power_op_lxvl, +power_op_lxvll, +power_op_lxvw4x, +power_op_lxvwsx, +power_op_lxvx, +power_op_maddhd, +power_op_maddhdu, +power_op_maddld, +power_op_maskg, +power_op_maskir, +power_op_mcrf, +power_op_mcrfs, +power_op_mcrxr, +power_op_mcrxrx, +power_op_mfbhrbe, +power_op_mfcr, +power_op_mffs, +power_op_mffscdrn, +power_op_mffscdrni, +power_op_mffsce, +power_op_mffscrn, +power_op_mffscrni, +power_op_mffsl, +power_op_mfmsr, +power_op_mfocrf, +power_op_mfspr, +power_op_mfsr, +power_op_mfsri, +power_op_mfsrin, +power_op_mfvscr, +power_op_mfvsrd, +power_op_mfvsrld, +power_op_mfvsrwz, +power_op_modsd, +power_op_modsw, +power_op_modud, +power_op_moduw, +power_op_msgclr, +power_op_msgclrp, +power_op_msgsnd, +power_op_msgsndp, +power_op_msgsync, +power_op_mtcrf, +power_op_mtfsb0, +power_op_mtfsb1, +power_op_mtfsf, +power_op_mtfsfi, +power_op_mtmsr, +power_op_mtmsrd, +power_op_mtspr, +power_op_mtvscr, +power_op_mtvsrd, +power_op_mtvsrdd, +power_op_mtvsrwa, +power_op_mtvsrws, +power_op_mtvsrwz, +power_op_mul, +power_op_mulhd, +power_op_mulhdu, +power_op_mulhw, +power_op_mulhwu, +power_op_mulld, +power_op_mulli, +power_op_mullw, +power_op_nabs, +power_op_nand, +power_op_neg, +power_op_nor, +power_op_or, +power_op_orc, +power_op_ori, +power_op_oris, +power_op_paste, +power_op_popcntb, +power_op_popcntd, +power_op_popcntw, +power_op_prtyd, +power_op_prtyw, +power_op_qvesplati, +power_op_qvfabs, +power_op_qvfadd, +power_op_qvfadds, +power_op_qvfaligni, +power_op_qvfcfid, +power_op_qvfcfids, +power_op_qvfcfidu, +power_op_qvfcfidus, +power_op_qvfcmpeq, +power_op_qvfcmpgt, +power_op_qvfcmplt, +power_op_qvfcpsgn, +power_op_qvfctid, +power_op_qvfctidu, +power_op_qvfctiduz, +power_op_qvfctidz, +power_op_qvfctiw, +power_op_qvfctiwu, +power_op_qvfctiwuz, +power_op_qvfctiwz, +power_op_qvflogical, +power_op_qvfmadd, +power_op_qvfmadds, +power_op_qvfmr, +power_op_qvfmsub, +power_op_qvfmsubs, +power_op_qvfmul, +power_op_qvfmuls, +power_op_qvfnabs, +power_op_qvfneg, +power_op_qvfnmadd, +power_op_qvfnmadds, +power_op_qvfnmsub, +power_op_qvfnmsubs, +power_op_qvfperm, +power_op_qvfre, +power_op_qvfres, +power_op_qvfrim, +power_op_qvfrin, +power_op_qvfrip, +power_op_qvfriz, +power_op_qvfrsp, +power_op_qvfrsqrte, +power_op_qvfrsqrtes, +power_op_qvfsel, +power_op_qvfsub, +power_op_qvfsubs, +power_op_qvftstnan, +power_op_qvfxmadd, +power_op_qvfxmadds, +power_op_qvfxmul, +power_op_qvfxmuls, +power_op_qvfxxcpnmadd, +power_op_qvfxxcpnmadds, +power_op_qvfxxmadd, +power_op_qvfxxmadds, +power_op_qvfxxnpmadd, +power_op_qvfxxnpmadds, +power_op_qvgpci, +power_op_qvlfcdux, +power_op_qvlfcdx, +power_op_qvlfcsux, +power_op_qvlfcsx, +power_op_qvlfdux, +power_op_qvlfdx, +power_op_qvlfiwax, +power_op_qvlfiwzx, +power_op_qvlfsux, +power_op_qvlfsx, +power_op_qvlpcldx, +power_op_qvlpclsx, +power_op_qvlpcrdx, +power_op_qvlpcrsx, +power_op_qvlstdux, +power_op_qvlstduxi, +power_op_qvstfcdux, +power_op_qvstfcduxi, +power_op_qvstfcdx, +power_op_qvstfcdxi, +power_op_qvstfcsux, +power_op_qvstfcsuxi, +power_op_qvstfcsx, +power_op_qvstfcsxi, +power_op_qvstfdux, +power_op_qvstfduxi, +power_op_qvstfdx, +power_op_qvstfdxi, +power_op_qvstfiwx, +power_op_qvstfsux, +power_op_qvstfsuxi, +power_op_qvstfsx, +power_op_qvstfsxi, +power_op_rac, +power_op_rfi, +power_op_rfid, +power_op_rfsvc, +power_op_rldcl, +power_op_rldcr, +power_op_rldic, +power_op_rldicl, +power_op_rldicr, +power_op_rldimi, +power_op_rlmi, +power_op_rlwimi, +power_op_rlwinm, +power_op_rlwnm, +power_op_rrib, +power_op_sc, +power_op_setb, +power_op_slbfee, +power_op_slbia, +power_op_slbiag, +power_op_slbie, +power_op_slbieg, +power_op_slbmfee, +power_op_slbmfev, +power_op_slbmte, +power_op_slbsync, +power_op_sld, +power_op_sle, +power_op_sleq, +power_op_sliq, +power_op_slliq, +power_op_sllq, +power_op_slq, +power_op_slw, +power_op_srad, +power_op_sradi, +power_op_sraiq, +power_op_sraq, +power_op_sraw, +power_op_srawi, +power_op_srd, +power_op_sre, +power_op_srea, +power_op_sreq, +power_op_sriq, +power_op_srliq, +power_op_srlq, +power_op_srq, +power_op_srw, +power_op_stb, +power_op_stbcix, +power_op_stbcx, +power_op_stbu, +power_op_stbux, +power_op_stbx, +power_op_stdat, +power_op_stdbrx, +power_op_stdcix, +power_op_stdcx_rc, +power_op_stdu, +power_op_stdux, +power_op_stdx, +power_op_stfd, +power_op_stfdpx, +power_op_stfdu, +power_op_stfdux, +power_op_stfdx, +power_op_stfiwx, +power_op_stfpdux, +power_op_stfpdx, +power_op_stfpiwx, +power_op_stfpsux, +power_op_stfpsx, +power_op_stfq, +power_op_stfqu, +power_op_stfqux, +power_op_stfqx, +power_op_stfs, +power_op_stfsdux, +power_op_stfsdx, +power_op_stfssux, +power_op_stfssx, +power_op_stfsu, +power_op_stfsux, +power_op_stfsx, +power_op_stfxdux, +power_op_stfxdx, +power_op_stfxsux, +power_op_stfxsx, +power_op_sth, +power_op_sthbrx, +power_op_sthcix, +power_op_sthcx, +power_op_sthu, +power_op_sthux, +power_op_sthx, +power_op_stmw, +power_op_stqcx, +power_op_stswi, +power_op_stswx, +power_op_stvb16x, +power_op_stvebx, +power_op_stvehx, +power_op_stvewx, +power_op_stvx, +power_op_stvxl, +power_op_stw, +power_op_stwat, +power_op_stwbrx, +power_op_stwcix, +power_op_stwcx_rc, +power_op_stwu, +power_op_stwux, +power_op_stwx, +power_op_stxsd, +power_op_stxsdx, +power_op_stxsibx, +power_op_stxsihx, +power_op_stxsiwx, +power_op_stxssp, +power_op_stxsspx, +power_op_stxvb16x, +power_op_stxvd2x, +power_op_stxvh8x, +power_op_stxvl, +power_op_stxvll, +power_op_stxvw4x, +power_op_stxvx, +power_op_subf, +power_op_subfc, +power_op_subfe, +power_op_subfic, +power_op_subfme, +power_op_subfze, +power_op_svcs, +power_op_sync, +power_op_tabort, +power_op_tabortdc, +power_op_tabortdci, +power_op_tabortwc, +power_op_tabortwci, +power_op_tbegin, +power_op_tcheck, +power_op_td, +power_op_tdi, +power_op_tend, +power_op_tlbie, +power_op_tlbiel, +power_op_tlbld, +power_op_tlbli, +power_op_tlbsync, +power_op_trechkpt, +power_op_treclaim, +power_op_tsr, +power_op_tw, +power_op_twi, +power_op_vabsdub, +power_op_vabsduh, +power_op_vabsduw, +power_op_vaddcuq, +power_op_vaddcuw, +power_op_vaddecuq, +power_op_vaddeuqm, +power_op_vaddfp, +power_op_vaddsbs, +power_op_vaddshs, +power_op_vaddsws, +power_op_vaddubm, +power_op_vaddubs, +power_op_vaddudm, +power_op_vadduhm, +power_op_vadduhs, +power_op_vadduqm, +power_op_vadduwm, +power_op_vadduws, +power_op_vand, +power_op_vandc, +power_op_vavgsb, +power_op_vavgsh, +power_op_vavgsw, +power_op_vavgub, +power_op_vavguh, +power_op_vavguw, +power_op_vbpermd, +power_op_vbpermq, +power_op_vcfsx, +power_op_vcfux, +power_op_vcipher, +power_op_vcipherlast, +power_op_vclzb, +power_op_vclzd, +power_op_vclzh, +power_op_vclzlsbb, +power_op_vclzw, +power_op_vcmpbfp, +power_op_vcmpeqfp, +power_op_vcmpequb, +power_op_vcmpequd, +power_op_vcmpequh, +power_op_vcmpequw, +power_op_vcmpgefp, +power_op_vcmpgtfp, +power_op_vcmpgtsb, +power_op_vcmpgtsd, +power_op_vcmpgtsh, +power_op_vcmpgtsw, +power_op_vcmpgtub, +power_op_vcmpgtud, +power_op_vcmpgtuh, +power_op_vcmpgtuw, +power_op_vcmpneb, +power_op_vcmpneh, +power_op_vcmpnew, +power_op_vcmpnezb, +power_op_vcmpnezh, +power_op_vcmpnezw, +power_op_vctsxs, +power_op_vctuxs, +power_op_vctzb, +power_op_vctzd, +power_op_vctzh, +power_op_vctzlsbb, +power_op_vctzw, +power_op_veqv, +power_op_vexptefp, +power_op_vextractd, +power_op_vextractub, +power_op_vextractuh, +power_op_vextractuw, +power_op_vextsb2d, +power_op_vextsb2w, +power_op_vextsh2d, +power_op_vextsh2w, +power_op_vextsw2d, +power_op_vextublx, +power_op_vextubrx, +power_op_vextuhlx, +power_op_vextuhrx, +power_op_vextuwlx, +power_op_vextuwrx, +power_op_vgbbd, +power_op_vinsertb, +power_op_vinsertd, +power_op_vinserth, +power_op_vinsertw, +power_op_vlogefp, +power_op_vmaddfp, +power_op_vmaxfp, +power_op_vmaxsb, +power_op_vmaxsd, +power_op_vmaxsh, +power_op_vmaxsw, +power_op_vmaxub, +power_op_vmaxud, +power_op_vmaxuh, +power_op_vmaxuw, +power_op_vmhaddshs, +power_op_vmhraddshs, +power_op_vminfp, +power_op_vminsb, +power_op_vminsd, +power_op_vminsh, +power_op_vminsw, +power_op_vminub, +power_op_vminud, +power_op_vminuh, +power_op_vminuw, +power_op_vmladduhm, +power_op_vmrgew, +power_op_vmrghb, +power_op_vmrghh, +power_op_vmrghw, +power_op_vmrglb, +power_op_vmrglh, +power_op_vmrglw, +power_op_vmrgow, +power_op_vmsummbm, +power_op_vmsumshm, +power_op_vmsumshs, +power_op_vmsumubm, +power_op_vmsumudm, +power_op_vmsumuhm, +power_op_vmsumuhs, +power_op_vmul10cuq, +power_op_vmul10ecuq, +power_op_vmul10euq, +power_op_vmul10uq, +power_op_vmulesb, +power_op_vmulesh, +power_op_vmulesw, +power_op_vmuleub, +power_op_vmuleuh, +power_op_vmuleuw, +power_op_vmulosb, +power_op_vmulosh, +power_op_vmulosw, +power_op_vmuloub, +power_op_vmulouh, +power_op_vmulouw, +power_op_vmuluwm, +power_op_vnand, +power_op_vncipher, +power_op_vncipherlast, +power_op_vnegd, +power_op_vnegw, +power_op_vnmsubfp, +power_op_vnor, +power_op_vor, +power_op_vorc, +power_op_vperm, +power_op_vpermr, +power_op_vpermxor, +power_op_vpkpx, +power_op_vpksdss, +power_op_vpksdus, +power_op_vpkshss, +power_op_vpkshus, +power_op_vpkswss, +power_op_vpkswus, +power_op_vpkudum, +power_op_vpkudus, +power_op_vpkuhum, +power_op_vpkuhus, +power_op_vpkuwum, +power_op_vpkuwus, +power_op_vpmsumb, +power_op_vpmsumd, +power_op_vpmsumh, +power_op_vpmsumw, +power_op_vpopcntb, +power_op_vpopcntd, +power_op_vpopcnth, +power_op_vpopcntw, +power_op_vprtybd, +power_op_vprtybq, +power_op_vprtybw, +power_op_vrefp, +power_op_vrfim, +power_op_vrfin, +power_op_vrfip, +power_op_vrfiz, +power_op_vrlb, +power_op_vrld, +power_op_vrldmi, +power_op_vrldnm, +power_op_vrlh, +power_op_vrlw, +power_op_vrlwmi, +power_op_vrlwnm, +power_op_vrsqrtefp, +power_op_vsbox, +power_op_vsel, +power_op_vshasigmad, +power_op_vshasigmaw, +power_op_vsl, +power_op_vslb, +power_op_vsld, +power_op_vsldoi, +power_op_vslh, +power_op_vslo, +power_op_vslv, +power_op_vslw, +power_op_vspltb, +power_op_vsplth, +power_op_vspltisb, +power_op_vspltish, +power_op_vspltisw, +power_op_vspltw, +power_op_vsr, +power_op_vsrab, +power_op_vsrad, +power_op_vsrah, +power_op_vsraw, +power_op_vsrb, +power_op_vsrd, +power_op_vsrh, +power_op_vsro, +power_op_vsrv, +power_op_vsrw, +power_op_vsubcuq, +power_op_vsubcuw, +power_op_vsubecuq, +power_op_vsubeuqm, +power_op_vsubfp, +power_op_vsubsbs, +power_op_vsubshs, +power_op_vsubsws, +power_op_vsububm, +power_op_vsububs, +power_op_vsubudm, +power_op_vsubuhm, +power_op_vsubuhs, +power_op_vsubuqm, +power_op_vsubuwm, +power_op_vsubuws, +power_op_vsum2sws, +power_op_vsum4sbs, +power_op_vsum4shs, +power_op_vsum4ubs, +power_op_vsumsws, +power_op_vupkhpx, +power_op_vupkhsb, +power_op_vupkhsh, +power_op_vupkhsw, +power_op_vupklpx, +power_op_vupklsb, +power_op_vupklsh, +power_op_vupklsw, +power_op_vxor, +power_op_wait, +power_op_xor, +power_op_xori, +power_op_xoris, +power_op_xsabsdp, +power_op_xsabsqp, +power_op_xsadddp, +power_op_xsaddqp, +power_op_xsaddsp, +power_op_xscmpeqdp, +power_op_xscmpexpdp, +power_op_xscmpexpqp, +power_op_xscmpgedp, +power_op_xscmpgtdp, +power_op_xscmpodp, +power_op_xscmpoqp, +power_op_xscmpudp, +power_op_xscmpuqp, +power_op_xscpsgndp, +power_op_xscpsgnqp, +power_op_xscvdphp, +power_op_xscvdpqp, +power_op_xscvdpsp, +power_op_xscvdpspn, +power_op_xscvdpsxds, +power_op_xscvdpsxws, +power_op_xscvdpuxds, +power_op_xscvdpuxws, +power_op_xscvhpdp, +power_op_xscvhphp, +power_op_xscvqpdp, +power_op_xscvqpsdz, +power_op_xscvqpswz, +power_op_xscvqpudz, +power_op_xscvqpuwz, +power_op_xscvsdqp, +power_op_xscvspdp, +power_op_xscvspdpn, +power_op_xscvsxddp, +power_op_xscvsxdsp, +power_op_xscvudqp, +power_op_xscvuxddp, +power_op_xscvuxdsp, +power_op_xsdivdp, +power_op_xsdivqp, +power_op_xsdivsp, +power_op_xsiexpdp, +power_op_xsiexpqp, +power_op_xsmaddadp, +power_op_xsmaddasp, +power_op_xsmaddmdp, +power_op_xsmaddmsp, +power_op_xsmaddqp, +power_op_xsmaxcdp, +power_op_xsmaxdp, +power_op_xsmaxjdp, +power_op_xsmincdp, +power_op_xsmindp, +power_op_xsminjdp, +power_op_xsmsubadp, +power_op_xsmsubasp, +power_op_xsmsubmdp, +power_op_xsmsubmsp, +power_op_xsmsubqp, +power_op_xsmuldp, +power_op_xsmulqp, +power_op_xsmulsp, +power_op_xsnabsdp, +power_op_xsnabsqp, +power_op_xsnegdp, +power_op_xsnegqp, +power_op_xsnmaddadp, +power_op_xsnmaddasp, +power_op_xsnmaddmdp, +power_op_xsnmaddmsp, +power_op_xsnmaddqp, +power_op_xsnmsubadp, +power_op_xsnmsubasp, +power_op_xsnmsubmdp, +power_op_xsnmsubmsp, +power_op_xsnmsubqp, +power_op_xsrdpi, +power_op_xsrdpic, +power_op_xsrdpim, +power_op_xsrdpip, +power_op_xsrdpiz, +power_op_xsredp, +power_op_xsresp, +power_op_xsrqpi, +power_op_xsrqpxp, +power_op_xsrsp, +power_op_xsrsqrtedp, +power_op_xsrsqrtesp, +power_op_xssqrtdp, +power_op_xssqrtqp, +power_op_xssqrtsp, +power_op_xssubdp, +power_op_xssubqp, +power_op_xssubsp, +power_op_xstdivdp, +power_op_xstsqrtdp, +power_op_xststdcdp, +power_op_xststdcqp, +power_op_xststdcsp, +power_op_xsxexpdp, +power_op_xsxexpqp, +power_op_xsxsigdp, +power_op_xsxsigqp, +power_op_xvabsdp, +power_op_xvabssp, +power_op_xvadddp, +power_op_xvaddsp, +power_op_xvcmpeqdp, +power_op_xvcmpeqsp, +power_op_xvcmpgedp, +power_op_xvcmpgesp, +power_op_xvcmpgtdp, +power_op_xvcmpgtsp, +power_op_xvcpsgndp, +power_op_xvcpsgnsp, +power_op_xvcvdpsp, +power_op_xvcvdpsxds, +power_op_xvcvdpsxws, +power_op_xvcvdpuxds, +power_op_xvcvdpuxws, +power_op_xvcvhpsp, +power_op_xvcvspdp, +power_op_xvcvsphp, +power_op_xvcvspsxds, +power_op_xvcvspsxws, +power_op_xvcvspuxds, +power_op_xvcvspuxws, +power_op_xvcvsxddp, +power_op_xvcvsxdsp, +power_op_xvcvsxwdp, +power_op_xvcvsxwsp, +power_op_xvcvuxddp, +power_op_xvcvuxdsp, +power_op_xvcvuxwdp, +power_op_xvcvuxwsp, +power_op_xvdivdp, +power_op_xvdivsp, +power_op_xviexpdp, +power_op_xviexpsp, +power_op_xvmaddadp, +power_op_xvmaddasp, +power_op_xvmaddmdp, +power_op_xvmaddmsp, +power_op_xvmaxdp, +power_op_xvmaxsp, +power_op_xvmindp, +power_op_xvminsp, +power_op_xvmsubadp, +power_op_xvmsubasp, +power_op_xvmsubmdp, +power_op_xvmsubmsp, +power_op_xvmuldp, +power_op_xvmulsp, +power_op_xvnabsdp, +power_op_xvnabssp, +power_op_xvnegdp, +power_op_xvnegsp, +power_op_xvnmaddadp, +power_op_xvnmaddasp, +power_op_xvnmaddmdp, +power_op_xvnmaddmsp, +power_op_xvnmsubadp, +power_op_xvnmsubasp, +power_op_xvnmsubmdp, +power_op_xvnmsubmsp, +power_op_xvrdpi, +power_op_xvrdpic, +power_op_xvrdpim, +power_op_xvrdpip, +power_op_xvrdpiz, +power_op_xvredp, +power_op_xvresp, +power_op_xvrspi, +power_op_xvrspic, +power_op_xvrspim, +power_op_xvrspip, +power_op_xvrspiz, +power_op_xvrsqrtedp, +power_op_xvrsqrtesp, +power_op_xvsqrtdp, +power_op_xvsqrtsp, +power_op_xvsubdp, +power_op_xvsubsp, +power_op_xvtdivdp, +power_op_xvtdivsp, +power_op_xvtsqrtdp, +power_op_xvtsqrtsp, +power_op_xvtstdcdp, +power_op_xvtstdcsp, +power_op_xvxexpdp, +power_op_xvxexpsp, +power_op_xvxsigdp, +power_op_xvxsigsp, +power_op_xxbrd, +power_op_xxbrh, +power_op_xxbrq, +power_op_xxbrw, +power_op_xxextractuw, +power_op_xxinsertw, +power_op_xxland, +power_op_xxlandc, +power_op_xxleqv, +power_op_xxlnand, +power_op_xxlnor, +power_op_xxlor, +power_op_xxlorc, +power_op_xxlxor, +power_op_xxmrghw, +power_op_xxmrglw, +power_op_xxperm, +power_op_xxpermdi, +power_op_xxpermr, +power_op_xxsel, +power_op_xxsldwi, +power_op_xxspltib, +power_op_xxspltw, diff --git a/common/h/mnemonics/x86_entryIDs.h b/common/h/mnemonics/x86_entryIDs.h new file mode 100644 index 0000000000..49cf67e0d3 --- /dev/null +++ b/common/h/mnemonics/x86_entryIDs.h @@ -0,0 +1,1593 @@ +e_No_Entry, /* pseudo mnemonic */ +e_3dnow_generic, /* pseudo mnemonic */ +e_fp_generic, /* pseudo mnemonic */ +e_int80, /* pseudo mnemonic */ +e_jb_jnaej_j, /* pseudo mnemonic */ +e_jcxz_jec, /* pseudo mnemonic */ +e_jnb_jae_j, /* pseudo mnemonic */ +e_movlps_movhlps, /* pseudo mnemonic */ +e_movhps_movlhps, /* pseudo mnemonic */ +e_movsd_sse, /* pseudo mnemonic */ +e_pextrd_pextrq, /* pseudo mnemonic */ +e_pinsrd_pinsrq, /* pseudo mnemonic */ +e_prefetch_w, /* pseudo mnemonic */ +e_ud2grp10 , /* pseudo mnemonic */ +e_ret_far, /* pseudo mnemonic */ +e_ret_near, /* pseudo mnemonic */ +e_lcall, /* pseudo mnemonic */ +e_clzero, /* pseudo mnemonic */ +e_aaa, +e_aad, +e_aam, +e_aas, +e_adc, +e_adcx, +e_add, +e_addpd, +e_addps, +e_addsd, +e_addss, +e_addsubpd, +e_addsubps, +e_adox, +e_aesdec, +e_aesdeclast, +e_aesenc, +e_aesenclast, +e_aesimc, +e_aeskeygenassist, +e_and, +e_andn, +e_andnpd, +e_andnps, +e_andpd, +e_andps, +e_arpl, +e_bextr, +e_blcfill, +e_blci, +e_blcic, +e_blcmsk, +e_blcs, +e_blendpd, +e_blendps, +e_blendvpd, +e_blendvps, +e_blsfill, +e_blsi, +e_blsic, +e_blsmsk, +e_blsr, +e_bndcl, +e_bndcn, +e_bndcu = e_bndcn, +e_bndldx, +e_bndmk, +e_bndmov, +e_bndstx, +e_bound, +e_bsf, +e_bsr, +e_bswap, +e_bt, +e_btc, +e_btr, +e_bts, +e_bzhi, +e_call, +e_cbw, +e_cdqe = e_cbw, +e_cdq, +e_cwd = e_cdq, +e_cqo = e_cdq, +e_clac, +e_clc, +e_cld, +e_cldemote, +e_clflush, +e_clflushopt, +e_clgi, +e_cli, +e_clrssbsy, +e_clts, +e_clwb, +e_cmc, +e_cmova, +e_cmovnbe = e_cmova, +e_cmovae, +e_cmovnb = e_cmovae, +e_cmovnc = e_cmovae, +e_cmovb, +e_cmovc = e_cmovb, +e_cmovnae = e_cmovb, +e_cmovbe, +e_cmovna = e_cmovbe, +e_cmove, +e_cmovz = e_cmove, +e_cmovg, +e_cmovnle = e_cmovg, +e_cmovge, +e_cmovnl = e_cmovge, +e_cmovl, +e_cmovnge = e_cmovl, +e_cmovle, +e_cmovng = e_cmovle, +e_cmovne, +e_cmovnz = e_cmovne, +e_cmovno, +e_cmovnp, +e_cmovpo = e_cmovnp, +e_cmovns, +e_cmovo, +e_cmovp, +e_cmovpe = e_cmovp, +e_cmovs, +e_cmp, +e_cmppd, +e_cmpps, +e_cmpsb, +e_cmpsd, +e_cmpsq, +e_cmpss, +e_cmpsw, +e_cmpxchg, +e_cmpxchg16b, +e_cmpxchg8b, +e_comisd, +e_comiss, +e_cpuid, +e_crc32, +e_cvtdq2pd, +e_cvtdq2ps, +e_cvtpd2dq, +e_cvtpd2pi, +e_cvtpd2ps, +e_cvtpi2pd, +e_cvtpi2ps, +e_cvtps2dq, +e_cvtps2pd, +e_cvtps2pi, +e_cvtsd2si, +e_cvtsd2ss, +e_cvtsi2sd, +e_cvtsi2ss, +e_cvtss2sd, +e_cvtss2si, +e_cvttpd2dq, +e_cvttpd2pi, +e_cvttps2dq, +e_cvttps2pi, +e_cvttsd2si, +e_cvttss2si, +e_cwde, +e_daa, +e_das, +e_data16, +e_dec, +e_div, +e_divpd, +e_divps, +e_divsd, +e_divss, +e_dppd, +e_dpps, +e_emms, +e_encls, +e_enclu, +e_enclv, +e_endbr32, +e_endbr64, +e_enter, +e_extractps, +e_extrq, +e_f2xm1, +e_fabs, +e_fadd, +e_faddp, +e_fbld, +e_fbstp, +e_fchs, +e_fcmovb, +e_fcmovbe, +e_fcmove, +e_fcmovnb, +e_fcmovnbe, +e_fcmovne, +e_fcmovnp, +e_fcmovnu, +e_fcmovu, +e_fcom, +e_fcomi, +e_fcomp, +e_fcompi, +e_fcomip = e_fcompi, +e_fcompp, +e_fcos, +e_fdecstp, +e_fdisi8087_nop, +e_fdiv, +e_fdivp, +e_fdivr, +e_fdivrp, +e_femms, +e_feni8087_nop, +e_ffree, +e_ffreep, +e_fiadd, +e_ficom, +e_ficomp, +e_fidiv, +e_fidivr, +e_fild, +e_fimul, +e_fincstp, +e_fist, +e_fistp, +e_fisttp, +e_fisub, +e_fisubr, +e_fld, +e_fld1, +e_fldcw, +e_fldenv, +e_fldl2e, +e_fldl2t, +e_fldlg2, +e_fldln2, +e_fldpi, +e_fldz, +e_fmul, +e_fmulp, +e_fnclex, +e_fninit, +e_fnop, +e_fnsave, +e_fnstcw, +e_fnstenv, +e_fnstsw, +e_fpatan, +e_fprem, +e_fprem1, +e_fptan, +e_frndint, +e_frstor, +e_fscale, +e_fsetpm, +e_fsin, +e_fsincos, +e_fsqrt, +e_fst, +e_fstp, +e_fstpnce, +e_fsub, +e_fsubp, +e_fsubr, +e_fsubrp, +e_ftst, +e_fucom, +e_fucomi, +e_fucomp, +e_fucompi, +e_fucomip = e_fucompi, +e_fucompp, +e_fxam, +e_fxch, +e_fxrstor, +e_fxrstor64, +e_fxsave, +e_fxsave64, +e_fxtract, +e_fyl2x, +e_fyl2xp1, +e_getsec, +e_gf2p8affineinvqb, +e_gf2p8affineqb, +e_gf2p8mulb, +e_haddpd, +e_haddps, +e_hlt, +e_hsubpd, +e_hsubps, +e_idiv, +e_imul, +e_in, +e_inc, +e_incsspd, +e_incsspq, +e_insb, +e_insd, +e_insertps, +e_insertq, +e_insw, +e_int, +e_int1, +e_int3, +e_into, +e_invd, +e_invept, +e_invlpg, +e_invlpga, +e_invpcid, +e_invvpid, +e_iret, +e_iretd = e_iret, +e_iretq = e_iret, +e_ja, +e_jnbe = e_ja, +e_jae, +e_jnb = e_jae, +e_jnc = e_jae, +e_jb, +e_jc = e_jb, +e_jnae = e_jb, +e_jbe, +e_jna = e_jbe, +e_jcxz, +e_jecxz = e_jcxz, +e_jrcxz = e_jcxz, +e_je, +e_jz = e_je, +e_jg, +e_jnle = e_jg, +e_jge, +e_jnl = e_jge, +e_jl, +e_jnge = e_jl, +e_jle, +e_jng = e_jle, +e_jmp, +e_jne, +e_jnz = e_jne, +e_jno, +e_jnp, +e_jpo = e_jnp, +e_jns, +e_jo, +e_jp, +e_jpe = e_jp, +e_js, +e_kaddb, +e_kaddd, +e_kaddq, +e_kaddw, +e_kandb, +e_kandd, +e_kandnb, +e_kandnd, +e_kandnq, +e_kandnw, +e_kandq, +e_kandw, +e_kmovb, +e_kmovd, +e_kmovq, +e_kmovw, +e_knotb, +e_knotd, +e_knotq, +e_knotw, +e_korb, +e_kord, +e_korq, +e_kortestb, +e_kortestd, +e_kortestq, +e_kortestw, +e_korw, +e_kshiftlb, +e_kshiftld, +e_kshiftlq, +e_kshiftlw, +e_kshiftrb, +e_kshiftrd, +e_kshiftrq, +e_kshiftrw, +e_ktestb, +e_ktestd, +e_ktestq, +e_ktestw, +e_kunpckbw, +e_kunpckdq, +e_kunpckwd, +e_kxnorb, +e_kxnord, +e_kxnorq, +e_kxnorw, +e_kxorb, +e_kxord, +e_kxorq, +e_kxorw, +e_lahf, +e_lar, +e_lddqu, +e_ldmxcsr, +e_lds, +e_lea, +e_leave, +e_les, +e_lfence, +e_lfs, +e_lgdt, +e_lgs, +e_lidt, +e_ljmp, +e_lldt, +e_llwpcb, +e_lmsw, +e_lock, +e_lodsb, +e_lods = e_lodsb, +e_lodsd, +e_lodsq, +e_lodsw, +e_loop, +e_loope, +e_loopz = e_loope, +e_loopne, +e_loopnz = e_loopne, +e_lsl, +e_lss, +e_ltr, +e_lwpins, +e_lwpval, +e_lzcnt, +e_maskmovdqu, +e_maskmovq, +e_maxpd, +e_maxps, +e_maxsd, +e_maxss, +e_mfence, +e_minpd, +e_minps, +e_minsd, +e_minss, +e_monitor, +e_monitorx = e_monitor, +e_montmul, +e_mov, +e_movabs, +e_movapd, +e_movaps, +e_movbe, +e_movd, +e_movddup, +e_movdir64b, +e_movdiri, +e_movdq2q, +e_movdqa, +e_movdqu, +e_movhlps, +e_movhpd, +e_movhps, +e_movlhps, +e_movlpd, +e_movlps, +e_movmskpd, +e_movmskps, +e_movntdq, +e_movntdqa, +e_movnti, +e_movntpd, +e_movntps, +e_movntq, +e_movntsd, +e_movntss, +e_movq, +e_movq2dq, +e_movsb, +e_movsd, +e_movshdup, +e_movsldup, +e_movsq, +e_movss, +e_movsw, +e_movsx, +e_movsxd, +e_movupd, +e_movups, +e_movzx, +e_mpsadbw, +e_mul, +e_mulpd, +e_mulps, +e_mulsd, +e_mulss, +e_mulx, +e_mwait, +e_mwaitx = e_mwait, +e_neg, +e_nop, +e_not, +e_or, +e_orpd, +e_orps, +e_out, +e_outsb, +e_outsd, +e_outsw, +e_pabsb, +e_pabsd, +e_pabsw, +e_packssdw, +e_packsswb, +e_packusdw, +e_packuswb, +e_paddb, +e_paddd, +e_paddq, +e_paddsb, +e_paddsw, +e_paddusb, +e_paddusw, +e_paddw, +e_palignr, +e_pand, +e_pandn, +e_pause, +e_pavgb, +e_pavgusb, +e_pavgw, +e_pblendvb, +e_pblendw, +e_pclmulqdq, +e_pcmpeqb, +e_pcmpeqd, +e_pcmpeqq, +e_pcmpeqw, +e_pcmpestri, +e_pcmpestrm, +e_pcmpgtb, +e_pcmpgtd, +e_pcmpgtq, +e_pcmpgtw, +e_pcmpistri, +e_pcmpistrm, +e_pconfig, +e_pdep, +e_pext, +e_pextrb, +e_pextrd, +e_pextrq, +e_pextrw, +e_pf2id, +e_pf2iw, +e_pfacc, +e_pfadd, +e_pfcmpeq, +e_pfcmpge, +e_pfcmpgt, +e_pfmax, +e_pfmin, +e_pfmul, +e_pfnacc, +e_pfpnacc, +e_pfrcp, +e_pfrcpit1, +e_pfrcpit2, +e_pfrsqit1, +e_pfrsqrt, +e_pfsub, +e_pfsubr, +e_phaddd, +e_phaddsw, +e_phaddw, +e_phminposuw, +e_phsubd, +e_phsubsw, +e_phsubw, +e_pi2fd, +e_pi2fw, +e_pinsrb, +e_pinsrd, +e_pinsrq, +e_pinsrw, +e_pmaddubsw, +e_pmaddwd, +e_pmaxsb, +e_pmaxsd, +e_pmaxsw, +e_pmaxub, +e_pmaxud, +e_pmaxuw, +e_pminsb, +e_pminsd, +e_pminsw, +e_pminub, +e_pminud, +e_pminuw, +e_pmovmskb, +e_pmovsxbd, +e_pmovsxbq, +e_pmovsxbw, +e_pmovsxdq, +e_pmovsxwd, +e_pmovsxwq, +e_pmovzxbd, +e_pmovzxbq, +e_pmovzxbw, +e_pmovzxdq, +e_pmovzxwd, +e_pmovzxwq, +e_pmuldq, +e_pmulhrsw, +e_pmulhrw, +e_pmulhuw, +e_pmulhw, +e_pmulld, +e_pmullw, +e_pmuludq, +e_pop, +e_popal, +e_popa = e_popal, +e_popaw, +e_popad = e_popaw, +e_popcnt, +e_popf, +e_popfd, +e_popfq, +e_por, +e_prefetch, +e_prefetchnta, +e_prefetcht0, +e_prefetcht1, +e_prefetcht2, +e_prefetchw, +e_prefetchwt1, +e_psadbw, +e_pshufb, +e_pshufd, +e_pshufhw, +e_pshuflw, +e_pshufw, +e_psignb, +e_psignd, +e_psignw, +e_pslld, +e_pslldq, +e_psllq, +e_psllw, +e_psrad, +e_psraw, +e_psrld, +e_psrldq, +e_psrlq, +e_psrlw, +e_psubb, +e_psubd, +e_psubq, +e_psubsb, +e_psubsw, +e_psubusb, +e_psubusw, +e_psubw, +e_pswapd, +e_ptest, +e_ptwrite, +e_punpckhbw, +e_punpckhdq, +e_punpckhqdq, +e_punpckhwd, +e_punpcklbw, +e_punpckldq, +e_punpcklqdq, +e_punpcklwd, +e_push, +e_pushal, +e_pusha = e_pushal, +e_pushad = e_pushal, +e_pushaw = e_pushal, +e_pushf, +e_pushfd = e_pushf, +e_pushfq = e_pushf, +e_pxor, +e_rcl, +e_rcpps, +e_rcpss, +e_rcr, +e_rdfsbase, +e_rdgsbase, +e_rdmsr, +e_rdpid, +e_rdpkru, +e_rdpmc, +e_rdrand, +e_rdseed, +e_rdsspd, +e_rdsspq, +e_rdtsc, +e_rdtscp, +e_rep, +e_repne, +e_ret, +e_retf, +e_retfq = e_retf, +e_rex64, +e_rol, +e_ror, +e_rorx, +e_roundpd, +e_roundps, +e_roundsd, +e_roundss, +e_rsm, +e_rsqrtps, +e_rsqrtss, +e_rstorssp, +e_sahf, +e_sal, +e_salc, +e_sar, +e_sarx, +e_saveprevssp, +e_sbb, +e_scasb, +e_scasd, +e_scasq, +e_scasw, +e_seta, +e_setnbe = e_seta, +e_setae, +e_setnb = e_setae, +e_setnc = e_setae, +e_setb, +e_setc = e_setb, +e_setnae = e_setb, +e_setbe, +e_setna = e_setbe, +e_sete, +e_setz = e_sete, +e_setg, +e_setnle = e_setg, +e_setge, +e_setnl = e_setge, +e_setl, +e_setnge = e_setl, +e_setle, +e_setng = e_setle, +e_setne, +e_setnz = e_setne, +e_setno, +e_setnp, +e_setpo = e_setnp, +e_setns, +e_seto, +e_setp, +e_setpe = e_setp, +e_sets, +e_setssbsy, +e_sfence, +e_sgdt, +e_sha1msg1, +e_sha1msg2, +e_sha1nexte, +e_sha1rnds4, +e_sha256msg1, +e_sha256msg2, +e_sha256rnds2, +e_shl, +e_shld, +e_shlx, +e_shr, +e_shrd, +e_shrx, +e_shufpd, +e_shufps, +e_sidt, +e_skinit, +e_sldt, +e_slwpcb, +e_smsw, +e_sqrtpd, +e_sqrtps, +e_sqrtsd, +e_sqrtss, +e_stac, +e_stc, +e_std, +e_stgi, +e_sti, +e_stmxcsr, +e_stosb, +e_stosd, +e_stosq, +e_stosw, +e_str, +e_sub, +e_subpd, +e_subps, +e_subsd, +e_subss, +e_swapgs, +e_syscall, +e_sysenter, +e_sysexit, +e_sysexitq, +e_sysret, +e_sysretq, +e_t1mskc, +e_test, +e_tpause, +e_tzcnt, +e_tzmsk, +e_ucomisd, +e_ucomiss, +e_ud0, +e_ud1, +e_ud2, +e_umonitor, +e_umwait, +e_unpckhpd, +e_unpckhps, +e_unpcklpd, +e_unpcklps, +e_v4fmaddps, +e_v4fmaddss, +e_v4fnmaddps, +e_v4fnmaddss, +e_vaddpd, +e_vaddps, +e_vaddsd, +e_vaddss, +e_vaddsubpd, +e_vaddsubps, +e_vaesdec, +e_vaesdeclast, +e_vaesenc, +e_vaesenclast, +e_vaesimc, +e_vaeskeygenassist, +e_valignd, +e_valignq, +e_vandnpd, +e_vandnps, +e_vandpd, +e_vandps, +e_vblendmpd, +e_vblendmps, +e_vblendpd, +e_vblendps, +e_vblendvpd, +e_vblendvps, +e_vbroadcastf128, +e_vbroadcastf32x2, +e_vbroadcastf32x4, +e_vbroadcastf32x8, +e_vbroadcastf64x2, +e_vbroadcastf64x4, +e_vbroadcasti128, +e_vbroadcasti32x2, +e_vbroadcasti32x4, +e_vbroadcasti32x8, +e_vbroadcasti64x2, +e_vbroadcasti64x4, +e_vbroadcastsd, +e_vbroadcastss, +e_vcmp, +e_vcmppd, +e_vcmpps, +e_vcmpsd, +e_vcmpss, +e_vcomisd, +e_vcomiss, +e_vcompresspd, +e_vcompressps, +e_vcvtdq2pd, +e_vcvtdq2ps, +e_vcvtpd2dq, +e_vcvtpd2ps, +e_vcvtpd2qq, +e_vcvtpd2udq, +e_vcvtpd2uqq, +e_vcvtph2ps, +e_vcvtps2dq, +e_vcvtps2pd, +e_vcvtps2ph, +e_vcvtps2qq, +e_vcvtps2udq, +e_vcvtps2uqq, +e_vcvtqq2pd, +e_vcvtqq2ps, +e_vcvtsd2si, +e_vcvtsd2ss, +e_vcvtsd2usi, +e_vcvtsi2sd, +e_vcvtsi2ss, +e_vcvtss2sd, +e_vcvtss2si, +e_vcvtss2usi, +e_vcvttpd2dq, +e_vcvttpd2qq, +e_vcvttpd2udq, +e_vcvttpd2uqq, +e_vcvttps2dq, +e_vcvttps2qq, +e_vcvttps2udq, +e_vcvttps2uqq, +e_vcvttsd2si, +e_vcvttsd2usi, +e_vcvttss2si, +e_vcvttss2usi, +e_vcvtudq2pd, +e_vcvtudq2ps, +e_vcvtuqq2pd, +e_vcvtuqq2ps, +e_vcvtusi2sd, +e_vcvtusi2ss, +e_vdbpsadbw, +e_vdivpd, +e_vdivps, +e_vdivsd, +e_vdivss, +e_vdppd, +e_vdpps, +e_verr, +e_verw, +e_vexp2pd, +e_vexp2ps, +e_vexpandpd, +e_vexpandps, +e_vextractf128, +e_vextractf32x4, +e_vextractf32x8, +e_vextractf64x2, +e_vextractf64x4, +e_vextracti128, +e_vextracti32x4, +e_vextracti32x8, +e_vextracti64x2, +e_vextracti64x4, +e_vextractps, +e_vfixupimmpd, +e_vfixupimmps, +e_vfixupimmsd, +e_vfixupimmss, +e_vfmadd132pd, +e_vfmadd132ps, +e_vfmadd132sd, +e_vfmadd132ss, +e_vfmadd213pd, +e_vfmadd213ps, +e_vfmadd213sd, +e_vfmadd213ss, +e_vfmadd231pd, +e_vfmadd231ps, +e_vfmadd231sd, +e_vfmadd231ss, +e_vfmaddpd, +e_vfmaddps, +e_vfmaddsd, +e_vfmaddss, +e_vfmaddsub132pd, +e_vfmaddsub132ps, +e_vfmaddsub213pd, +e_vfmaddsub213ps, +e_vfmaddsub231pd, +e_vfmaddsub231ps, +e_vfmaddsubpd, +e_vfmaddsubps, +e_vfmsub132pd, +e_vfmsub132ps, +e_vfmsub132sd, +e_vfmsub132ss, +e_vfmsub213pd, +e_vfmsub213ps, +e_vfmsub213sd, +e_vfmsub213ss, +e_vfmsub231pd, +e_vfmsub231ps, +e_vfmsub231sd, +e_vfmsub231ss, +e_vfmsubadd132pd, +e_vfmsubadd132ps, +e_vfmsubadd213pd, +e_vfmsubadd213ps, +e_vfmsubadd231pd, +e_vfmsubadd231ps, +e_vfmsubaddpd, +e_vfmsubaddps, +e_vfmsubpd, +e_vfmsubps, +e_vfmsubsd, +e_vfmsubss, +e_vfnmadd132pd, +e_vfnmadd132ps, +e_vfnmadd132sd, +e_vfnmadd132ss, +e_vfnmadd213pd, +e_vfnmadd213ps, +e_vfnmadd213sd, +e_vfnmadd213ss, +e_vfnmadd231pd, +e_vfnmadd231ps, +e_vfnmadd231sd, +e_vfnmadd231ss, +e_vfnmaddpd, +e_vfnmaddps, +e_vfnmaddsd, +e_vfnmaddss, +e_vfnmsub132pd, +e_vfnmsub132ps, +e_vfnmsub132sd, +e_vfnmsub132ss, +e_vfnmsub213pd, +e_vfnmsub213ps, +e_vfnmsub213sd, +e_vfnmsub213ss, +e_vfnmsub231pd, +e_vfnmsub231ps, +e_vfnmsub231sd, +e_vfnmsub231ss, +e_vfnmsubpd, +e_vfnmsubps, +e_vfnmsubsd, +e_vfnmsubss, +e_vfpclasspd, +e_vfpclassps, +e_vfpclasssd, +e_vfpclassss, +e_vfrczpd, +e_vfrczps, +e_vfrczsd, +e_vfrczss, +e_vgatherdpd, +e_vgatherdps, +e_vgatherpf0dpd, +e_vgatherpf0dps, +e_vgatherpf0qpd, +e_vgatherpf0qps, +e_vgatherpf1dpd, +e_vgatherpf1dps, +e_vgatherpf1qpd, +e_vgatherpf1qps, +e_vgatherqpd, +e_vgatherqps, +e_vgetexppd, +e_vgetexpps, +e_vgetexpsd, +e_vgetexpss, +e_vgetmantpd, +e_vgetmantps, +e_vgetmantsd, +e_vgetmantss, +e_vgf2p8affineinvqb, +e_vgf2p8affineqb, +e_vgf2p8mulb, +e_vhaddpd, +e_vhaddps, +e_vhsubpd, +e_vhsubps, +e_vinsertf128, +e_vinsertf32x4, +e_vinsertf32x8, +e_vinsertf64x2, +e_vinsertf64x4, +e_vinserti128, +e_vinserti32x4, +e_vinserti32x8, +e_vinserti64x2, +e_vinserti64x4, +e_vinsertps, +e_vlddqu, +e_vldmxcsr, +e_vmaskmovdqu, +e_vmaskmovpd, +e_vmaskmovps, +e_vmaxpd, +e_vmaxps, +e_vmaxsd, +e_vmaxss, +e_vmcall, +e_vmclear, +e_vmfunc, +e_vminpd, +e_vminps, +e_vminsd, +e_vminss, +e_vmlaunch, +e_vmload, +e_vmmcall, +e_vmovapd, +e_vmovaps, +e_vmovd, +e_vmovddup, +e_vmovdqa, +e_vmovdqa32, +e_vmovdqa64, +e_vmovdqu, +e_vmovdqu16, +e_vmovdqu32, +e_vmovdqu64, +e_vmovdqu8, +e_vmovhlps, +e_vmovhpd, +e_vmovhps, +e_vmovlhps, +e_vmovlpd, +e_vmovlps, +e_vmovmskpd, +e_vmovmskps, +e_vmovntdq, +e_vmovntdqa, +e_vmovntpd, +e_vmovntps, +e_vmovq, +e_vmovsd, +e_vmovshdup, +e_vmovsldup, +e_vmovss, +e_vmovupd, +e_vmovups, +e_vmpsadbw, +e_vmptrld, +e_vmptrst, +e_vmread, +e_vmresume, +e_vmrun, +e_vmsave, +e_vmulpd, +e_vmulps, +e_vmulsd, +e_vmulss, +e_vmwrite, +e_vmxoff, +e_vmxon, +e_vorpd, +e_vorps, +e_vp4dpwssd, +e_vp4dpwssds, +e_vpabsb, +e_vpabsd, +e_vpabsq, +e_vpabsw, +e_vpackssdw, +e_vpacksswb, +e_vpackusdw, +e_vpackuswb, +e_vpaddb, +e_vpaddd, +e_vpaddq, +e_vpaddsb, +e_vpaddsw, +e_vpaddusb, +e_vpaddusw, +e_vpaddw, +e_vpalignr, +e_vpand, +e_vpandd, +e_vpandn, +e_vpandnd, +e_vpandnq, +e_vpandq, +e_vpavgb, +e_vpavgw, +e_vpblendd, +e_vpblendmb, +e_vpblendmd, +e_vpblendmq, +e_vpblendmw, +e_vpblendvb, +e_vpblendw, +e_vpbroadcastb, +e_vpbroadcastd, +e_vpbroadcastmb2q, +e_vpbroadcastmw2d, +e_vpbroadcastq, +e_vpbroadcastw, +e_vpclmulqdq, +e_vpcmov, +e_vpcmp, +e_vpcmpb, +e_vpcmpd, +e_vpcmpeqb, +e_vpcmpeqd, +e_vpcmpeqq, +e_vpcmpeqw, +e_vpcmpestri, +e_vpcmpestrm, +e_vpcmpgtb, +e_vpcmpgtd, +e_vpcmpgtq, +e_vpcmpgtw, +e_vpcmpistri, +e_vpcmpistrm, +e_vpcmpq, +e_vpcmpub, +e_vpcmpud, +e_vpcmpuq, +e_vpcmpuw, +e_vpcmpw, +e_vpcom, +e_vpcomb, +e_vpcomd, +e_vpcompressb, +e_vpcompressd, +e_vpcompressq, +e_vpcompressw, +e_vpcomq, +e_vpcomub, +e_vpcomud, +e_vpcomuq, +e_vpcomuw, +e_vpcomw, +e_vpconflictd, +e_vpconflictq, +e_vpdpbusd, +e_vpdpbusds, +e_vpdpwssd, +e_vpdpwssds, +e_vperm2f128, +e_vperm2i128, +e_vpermb, +e_vpermd, +e_vpermi2b, +e_vpermi2d, +e_vpermi2pd, +e_vpermi2ps, +e_vpermi2q, +e_vpermi2w, +e_vpermil2pd, +e_vpermil2ps, +e_vpermilpd, +e_vpermilps, +e_vpermpd, +e_vpermps, +e_vpermq, +e_vpermt2b, +e_vpermt2d, +e_vpermt2pd, +e_vpermt2ps, +e_vpermt2q, +e_vpermt2w, +e_vpermw, +e_vpexpandb, +e_vpexpandd, +e_vpexpandq, +e_vpexpandw, +e_vpextrb, +e_vpextrd, +e_vpextrq, +e_vpextrw, +e_vpgatherdd, +e_vpgatherdq, +e_vpgatherqd, +e_vpgatherqq, +e_vphaddbd, +e_vphaddbq, +e_vphaddbw, +e_vphaddd, +e_vphadddq, +e_vphaddsw, +e_vphaddubd, +e_vphaddubq, +e_vphaddubw, +e_vphaddudq, +e_vphadduwd, +e_vphadduwq, +e_vphaddw, +e_vphaddwd, +e_vphaddwq, +e_vphminposuw, +e_vphsubbw, +e_vphsubd, +e_vphsubdq, +e_vphsubsw, +e_vphsubw, +e_vphsubwd, +e_vpinsrb, +e_vpinsrd, +e_vpinsrq, +e_vpinsrw, +e_vplzcntd, +e_vplzcntq, +e_vpmacsdd, +e_vpmacsdqh, +e_vpmacsdql, +e_vpmacssdd, +e_vpmacssdqh, +e_vpmacssdql, +e_vpmacsswd, +e_vpmacssww, +e_vpmacswd, +e_vpmacsww, +e_vpmadcsswd, +e_vpmadcswd, +e_vpmadd52huq, +e_vpmadd52luq, +e_vpmaddubsw, +e_vpmaddwd, +e_vpmaskmovd, +e_vpmaskmovq, +e_vpmaxsb, +e_vpmaxsd, +e_vpmaxsq, +e_vpmaxsw, +e_vpmaxub, +e_vpmaxud, +e_vpmaxuq, +e_vpmaxuw, +e_vpminsb, +e_vpminsd, +e_vpminsq, +e_vpminsw, +e_vpminub, +e_vpminud, +e_vpminuq, +e_vpminuw, +e_vpmovb2m, +e_vpmovd2m, +e_vpmovdb, +e_vpmovdw, +e_vpmovm2b, +e_vpmovm2d, +e_vpmovm2q, +e_vpmovm2w, +e_vpmovmskb, +e_vpmovq2m, +e_vpmovqb, +e_vpmovqd, +e_vpmovqw, +e_vpmovsdb, +e_vpmovsdw, +e_vpmovsqb, +e_vpmovsqd, +e_vpmovsqw, +e_vpmovswb, +e_vpmovsxbd, +e_vpmovsxbq, +e_vpmovsxbw, +e_vpmovsxdq, +e_vpmovsxwd, +e_vpmovsxwq, +e_vpmovusdb, +e_vpmovusdw, +e_vpmovusqb, +e_vpmovusqd, +e_vpmovusqw, +e_vpmovuswb, +e_vpmovw2m, +e_vpmovwb, +e_vpmovzxbd, +e_vpmovzxbq, +e_vpmovzxbw, +e_vpmovzxdq, +e_vpmovzxwd, +e_vpmovzxwq, +e_vpmuldq, +e_vpmulhrsw, +e_vpmulhuw, +e_vpmulhw, +e_vpmulld, +e_vpmullq, +e_vpmullw, +e_vpmultishiftqb, +e_vpmuludq, +e_vpopcntb, +e_vpopcntd, +e_vpopcntq, +e_vpopcntw, +e_vpor, +e_vpord, +e_vporq, +e_vpperm, +e_vprold, +e_vprolq, +e_vprolvd, +e_vprolvq, +e_vprord, +e_vprorq, +e_vprorvd, +e_vprorvq, +e_vprotb, +e_vprotd, +e_vprotq, +e_vprotw, +e_vpsadbw, +e_vpscatterdd, +e_vpscatterdq, +e_vpscatterqd, +e_vpscatterqq, +e_vpshab, +e_vpshad, +e_vpshaq, +e_vpshaw, +e_vpshlb, +e_vpshld, +e_vpshldd, +e_vpshldq, +e_vpshldvd, +e_vpshldvq, +e_vpshldvw, +e_vpshldw, +e_vpshlq, +e_vpshlw, +e_vpshrdd, +e_vpshrdq, +e_vpshrdvd, +e_vpshrdvq, +e_vpshrdvw, +e_vpshrdw, +e_vpshufb, +e_vpshufbitqmb, +e_vpshufd, +e_vpshufhw, +e_vpshuflw, +e_vpsignb, +e_vpsignd, +e_vpsignw, +e_vpslld, +e_vpslldq, +e_vpsllq, +e_vpsllvd, +e_vpsllvq, +e_vpsllvw, +e_vpsllw, +e_vpsrad, +e_vpsraq, +e_vpsravd, +e_vpsravq, +e_vpsravw, +e_vpsraw, +e_vpsrld, +e_vpsrldq, +e_vpsrlq, +e_vpsrlvd, +e_vpsrlvq, +e_vpsrlvw, +e_vpsrlw, +e_vpsubb, +e_vpsubd, +e_vpsubq, +e_vpsubsb, +e_vpsubsw, +e_vpsubusb, +e_vpsubusw, +e_vpsubw, +e_vpternlogd, +e_vpternlogq, +e_vptest, +e_vptestmb, +e_vptestmd, +e_vptestmq, +e_vptestmw, +e_vptestnmb, +e_vptestnmd, +e_vptestnmq, +e_vptestnmw, +e_vpunpckhbw, +e_vpunpckhdq, +e_vpunpckhqdq, +e_vpunpckhwd, +e_vpunpcklbw, +e_vpunpckldq, +e_vpunpcklqdq, +e_vpunpcklwd, +e_vpxor, +e_vpxord, +e_vpxorq, +e_vrangepd, +e_vrangeps, +e_vrangesd, +e_vrangess, +e_vrcp14pd, +e_vrcp14ps, +e_vrcp14sd, +e_vrcp14ss, +e_vrcp28pd, +e_vrcp28ps, +e_vrcp28sd, +e_vrcp28ss, +e_vrcpps, +e_vrcpss, +e_vreducepd, +e_vreduceps, +e_vreducesd, +e_vreducess, +e_vrndscalepd, +e_vrndscaleps, +e_vrndscalesd, +e_vrndscaless, +e_vroundpd, +e_vroundps, +e_vroundsd, +e_vroundss, +e_vrsqrt14pd, +e_vrsqrt14ps, +e_vrsqrt14sd, +e_vrsqrt14ss, +e_vrsqrt28pd, +e_vrsqrt28ps, +e_vrsqrt28sd, +e_vrsqrt28ss, +e_vrsqrtps, +e_vrsqrtss, +e_vscalefpd, +e_vscalefps, +e_vscalefsd, +e_vscalefss, +e_vscatterdpd, +e_vscatterdps, +e_vscatterpf0dpd, +e_vscatterpf0dps, +e_vscatterpf0qpd, +e_vscatterpf0qps, +e_vscatterpf1dpd, +e_vscatterpf1dps, +e_vscatterpf1qpd, +e_vscatterpf1qps, +e_vscatterqpd, +e_vscatterqps, +e_vshuff32x4, +e_vshuff64x2, +e_vshufi32x4, +e_vshufi64x2, +e_vshufpd, +e_vshufps, +e_vsqrtpd, +e_vsqrtps, +e_vsqrtsd, +e_vsqrtss, +e_vstmxcsr, +e_vsubpd, +e_vsubps, +e_vsubsd, +e_vsubss, +e_vtestpd, +e_vtestps, +e_vucomisd, +e_vucomiss, +e_vunpckhpd, +e_vunpckhps, +e_vunpcklpd, +e_vunpcklps, +e_vxorpd, +e_vxorps, +e_vzeroall, +e_vzeroupper, +e_wait, +e_fwait = e_wait, +e_wbinvd, +e_wbnoinvd, +e_wrfsbase, +e_wrgsbase, +e_wrmsr, +e_wrpkru, +e_wrssd, +e_wrssq, +e_wrussd, +e_wrussq, +e_xabort, +e_xacquire, +e_xadd, +e_xbegin, +e_xchg, +e_xcryptcbc, +e_xcryptcfb, +e_xcryptctr, +e_xcryptecb, +e_xcryptofb, +e_xend, +e_xgetbv, +e_xlatb, +e_xlat = e_xlatb, +e_xor, +e_xorpd, +e_xorps, +e_xrelease, +e_xrstor, +e_xrstor64, +e_xrstors, +e_xrstors64, +e_xsave, +e_xsave64, +e_xsavec, +e_xsavec64, +e_xsaveopt, +e_xsaveopt64, +e_xsaves, +e_xsaves64, +e_xsetbv, +e_xsha1, +e_xsha256, +e_xstore, +e_xtest, diff --git a/common/h/registers/AMDGPU/amdgpu_gfx908_regs.h b/common/h/registers/AMDGPU/amdgpu_gfx908_regs.h new file mode 100644 index 0000000000..38a6e0e2b0 --- /dev/null +++ b/common/h/registers/AMDGPU/amdgpu_gfx908_regs.h @@ -0,0 +1,853 @@ +/* + * See the dyninst/COPYRIGHT file for copyright information. + * + * We provide the Paradyn Tools (below described as "Paradyn") + * on an AS IS basis, and do not warrant its validity or performance. + * We reserve the right to update, modify, or discontinue this + * software at any time. We shall have no obligation to supply such + * updates or modifications or any other form of support to you. + * + * By your use of Paradyn, you understand and agree that we (or any + * other person or entity with proprietary rights in Paradyn) are + * under no obligation to provide either maintenance services, + * update services, notices of latent defects, or correction of + * defects for Paradyn. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef DYNINST_AMDGPU_GFX908_REGS_H +#define DYNINST_AMDGPU_GFX908_REGS_H + +//clang-format: off + +#include "Architecture.h" +#include "registers/reg_def.h" + +namespace Dyninst { namespace amdgpu_gfx908 { + + /** + * For interpreting constants: + * Lowest 16 bits (0x000000ff) is base register ID + * Next 16 bits (0x0000ff00) is the aliasing and subrange ID- + * used on x86/x86_64 to distinguish between things like EAX and AH + * Next 16 bits (0x00ff0000) are the register category, GPR/FPR/MMX/... + * Top 16 bits (0xff000000) are the architecture. + * + * These values/layout are not guaranteed to remain the same as part of the + * public interface, and may change. + **/ + + // 0xff000000 0x00ff0000 0x0000ff00 0x000000ff + // arch reg cat:GPR alias&subrange reg ID + const signed int SGPR = 0x00010000; + const signed int VGPR = 0x00060000; + const signed int ACC_VGPR = 0x000B0000; + + const signed int HWR = 0x000C0000; + const signed int TTMP_SGPR = 0x000D0000; + const signed int FLAGS = 0x000E0000; + const signed int PC = 0x000F0000; + const signed int SYSREG = 0x00100000; + const signed int TGT = 0x00110000; // I have no idea what TGT is yet + const signed int ATTR = 0x00120000; + const signed int PARAM = 0x00130000; // LDS Parameter + const signed int INFO = 0x00140000; // Addition Info + + // aliasing for flags + // if we found out that it is a flag, we no longer need to use the cat 0x00ff0000 + // so we use that part to encode the low offset in the base register + const signed int BITS_1 = 0x00000100; + const signed int BITS_2 = 0x00000200; + const signed int BITS_3 = 0x00000300; + const signed int BITS_4 = 0x00000400; + const signed int BITS_6 = 0x00000500; + const signed int BITS_7 = 0x00000600; + const signed int BITS_8 = 0x00000700; + const signed int BITS_9 = 0x00000800; + const signed int BITS_15 = 0x00000900; + const signed int BITS_16 = 0x00000A00; + const signed int BITS_32 = 0x00000B00; + const signed int BITS_48 = 0x00000C00; + const signed int BITS_64 = 0x00000D00; + const signed int BITS_128 = 0x00000E00; + const signed int BITS_256 = 0x00000F00; + const signed int BITS_512 = 0x00001000; + + // ( name, ID | alias | cat | arch, arch) + DEF_REGISTER( tid, 0 | BITS_32 | SYSREG |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + + DEF_REGISTER( invalid, 1 | BITS_32 | SYSREG |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( pc_all, 0 | BITS_48 | PC |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + + DEF_REGISTER( src_scc, 0 | BITS_32 | HWR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + + DEF_REGISTER( src_vccz, 1 | BITS_1 | HWR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( vcc_lo, 2 | BITS_32 | HWR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( vcc_hi, 3 | BITS_32 | HWR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( vcc, 2 | BITS_64 | HWR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + + DEF_REGISTER( src_execz, 4 | BITS_1 | HWR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( exec_lo, 5 | BITS_32 | HWR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( exec_hi, 6 | BITS_32 | HWR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( exec, 5 | BITS_64 | HWR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + + DEF_REGISTER( flat_scratch_lo, 7 | BITS_64 | HWR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( flat_scratch_hi, 8 | BITS_32 | HWR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( flat_scratch_all, 7 | BITS_32 | HWR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + + DEF_REGISTER( m0, 10 | BITS_32 | HWR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + + DEF_REGISTER( src_literal, 11 | BITS_32 | HWR |Arch_amdgpu_gfx908, "amdgpu_gfx908");//TODO + DEF_REGISTER(src_pops_exiting_wave_id, 12 | BITS_32 | HWR |Arch_amdgpu_gfx908, "amdgpu_gfx908");//TODO + + DEF_REGISTER( src_private_base, 13 | BITS_32 | HWR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( src_private_limit, 14 | BITS_32 | HWR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( src_shared_base, 15 | BITS_32 | HWR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( src_shared_limit, 16 | BITS_32 | HWR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + + DEF_REGISTER( xnack_mask_lo, 17 | BITS_32 | HWR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( xnack_mask_hi, 18 | BITS_32 | HWR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + + DEF_REGISTER( src_lds_direct, 19 | BITS_32 | HWR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( vmcnt, 20 | BITS_32 | HWR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( expcnt, 21 | BITS_32 | HWR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( lgkmcnt, 22 | BITS_32 | HWR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( dsmem, 23 | BITS_32 | HWR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + + DEF_REGISTER( ttmp0, 0 | BITS_32 | TTMP_SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( ttmp1, 1 | BITS_32 | TTMP_SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( ttmp2, 2 | BITS_32 | TTMP_SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( ttmp3, 3 | BITS_32 | TTMP_SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( ttmp4, 4 | BITS_32 | TTMP_SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( ttmp5, 5 | BITS_32 | TTMP_SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( ttmp6, 6 | BITS_32 | TTMP_SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( ttmp7, 7 | BITS_32 | TTMP_SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( ttmp8, 8 | BITS_32 | TTMP_SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( ttmp9, 9 | BITS_32 | TTMP_SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( ttmp10, 10 | BITS_32 | TTMP_SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( ttmp11, 11 | BITS_32 | TTMP_SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( ttmp12, 12 | BITS_32 | TTMP_SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( ttmp13, 13 | BITS_32 | TTMP_SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( ttmp14, 14 | BITS_32 | TTMP_SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( ttmp15, 15 | BITS_32 | TTMP_SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + + DEF_REGISTER( mrt0, 0 | BITS_32 | TGT |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( mrt1, 1 | BITS_32 | TGT |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( mrt2, 2 | BITS_32 | TGT |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( mrt3, 3 | BITS_32 | TGT |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( mrt4, 4 | BITS_32 | TGT |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( mrt5, 5 | BITS_32 | TGT |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( mrt6, 6 | BITS_32 | TGT |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( mrt7, 7 | BITS_32 | TGT |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( mrtz, 8 | BITS_32 | TGT |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( null, 9 | BITS_32 | TGT |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( pos0, 12 | BITS_32 | TGT |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( pos1, 13 | BITS_32 | TGT |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( pos2, 14 | BITS_32 | TGT |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( pos3, 15 | BITS_32 | TGT |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( param0, 32 | BITS_32 | TGT |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( param1, 33 | BITS_32 | TGT |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( param2, 34 | BITS_32 | TGT |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( param3, 35 | BITS_32 | TGT |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( param4, 36 | BITS_32 | TGT |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( param5, 37 | BITS_32 | TGT |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( param6, 38 | BITS_32 | TGT |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( param7, 39 | BITS_32 | TGT |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( param8, 40 | BITS_32 | TGT |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( param9, 41 | BITS_32 | TGT |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( param10, 42 | BITS_32 | TGT |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( param11, 43 | BITS_32 | TGT |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( param12, 44 | BITS_32 | TGT |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( param13, 45 | BITS_32 | TGT |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( param14, 46 | BITS_32 | TGT |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( param15, 47 | BITS_32 | TGT |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( param16, 48 | BITS_32 | TGT |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( param17, 49 | BITS_32 | TGT |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( param18, 50 | BITS_32 | TGT |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( param19, 51 | BITS_32 | TGT |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( param20, 52 | BITS_32 | TGT |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( param21, 53 | BITS_32 | TGT |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( param22, 54 | BITS_32 | TGT |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( param23, 55 | BITS_32 | TGT |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( param24, 56 | BITS_32 | TGT |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( param25, 57 | BITS_32 | TGT |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( param26, 58 | BITS_32 | TGT |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( param27, 59 | BITS_32 | TGT |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( param28, 60 | BITS_32 | TGT |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( param29, 61 | BITS_32 | TGT |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( param30, 62 | BITS_32 | TGT |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( param31, 63 | BITS_32 | TGT |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + + DEF_REGISTER( attr0, 0 | BITS_32 | ATTR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( attr1, 1 | BITS_32 | ATTR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( attr2, 2 | BITS_32 | ATTR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( attr3, 3 | BITS_32 | ATTR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( attr4, 4 | BITS_32 | ATTR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( attr5, 5 | BITS_32 | ATTR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( attr6, 6 | BITS_32 | ATTR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( attr7, 7 | BITS_32 | ATTR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( attr8, 8 | BITS_32 | ATTR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( attr9, 9 | BITS_32 | ATTR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( attr10, 10 | BITS_32 | ATTR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( attr11, 11 | BITS_32 | ATTR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( attr12, 12 | BITS_32 | ATTR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( attr13, 13 | BITS_32 | ATTR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( attr14, 14 | BITS_32 | ATTR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( attr15, 15 | BITS_32 | ATTR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( attr16, 16 | BITS_32 | ATTR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( attr17, 17 | BITS_32 | ATTR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( attr18, 18 | BITS_32 | ATTR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( attr19, 19 | BITS_32 | ATTR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( attr20, 20 | BITS_32 | ATTR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( attr21, 21 | BITS_32 | ATTR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( attr22, 22 | BITS_32 | ATTR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( attr23, 23 | BITS_32 | ATTR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( attr24, 24 | BITS_32 | ATTR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( attr25, 25 | BITS_32 | ATTR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( attr26, 26 | BITS_32 | ATTR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( attr27, 27 | BITS_32 | ATTR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( attr28, 28 | BITS_32 | ATTR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( attr29, 29 | BITS_32 | ATTR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( attr30, 30 | BITS_32 | ATTR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( attr31, 31 | BITS_32 | ATTR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( attr32, 32 | BITS_32 | ATTR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + + DEF_REGISTER( p10, 0 | BITS_32 | PARAM |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( p20, 1 | BITS_32 | PARAM |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( p0, 2 | BITS_32 | PARAM |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + + DEF_REGISTER( idxen, 0 | BITS_1 | INFO |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( offen, 1 | BITS_1 | INFO |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( off, 2 | BITS_1 | INFO |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + + DEF_REGISTER( s0, 0 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s1, 1 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s2, 2 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s3, 3 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s4, 4 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s5, 5 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s6, 6 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s7, 7 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s8, 8 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s9, 9 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s10, 10 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s11, 11 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s12, 12 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s13, 13 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s14, 14 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s15, 15 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s16, 16 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s17, 17 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s18, 18 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s19, 19 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s20, 20 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s21, 21 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s22, 22 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s23, 23 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s24, 24 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s25, 25 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s26, 26 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s27, 27 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s28, 28 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s29, 29 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s30, 30 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s31, 31 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s32, 32 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s33, 33 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s34, 34 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s35, 35 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s36, 36 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s37, 37 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s38, 38 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s39, 39 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s40, 40 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s41, 41 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s42, 42 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s43, 43 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s44, 44 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s45, 45 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s46, 46 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s47, 47 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s48, 48 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s49, 49 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s50, 50 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s51, 51 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s52, 52 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s53, 53 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s54, 54 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s55, 55 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s56, 56 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s57, 57 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s58, 58 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s59, 59 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s60, 60 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s61, 61 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s62, 62 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s63, 63 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s64, 64 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s65, 65 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s66, 66 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s67, 67 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s68, 68 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s69, 69 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s70, 70 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s71, 71 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s72, 72 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s73, 73 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s74, 74 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s75, 75 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s76, 76 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s77, 77 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s78, 78 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s79, 79 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s80, 80 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s81, 81 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s82, 82 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s83, 83 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s84, 84 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s85, 85 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s86, 86 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s87, 87 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s88, 88 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s89, 89 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s90, 90 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s91, 91 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s92, 92 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s93, 93 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s94, 94 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s95, 95 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s96, 96 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s97, 97 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s98, 98 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s99, 99 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s100, 100 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( s101, 101 | BITS_32 | SGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v0, 0 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v1, 1 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v2, 2 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v3, 3 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v4, 4 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v5, 5 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v6, 6 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v7, 7 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v8, 8 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v9, 9 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v10, 10 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v11, 11 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v12, 12 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v13, 13 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v14, 14 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v15, 15 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v16, 16 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v17, 17 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v18, 18 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v19, 19 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v20, 20 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v21, 21 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v22, 22 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v23, 23 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v24, 24 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v25, 25 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v26, 26 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v27, 27 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v28, 28 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v29, 29 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v30, 30 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v31, 31 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v32, 32 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v33, 33 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v34, 34 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v35, 35 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v36, 36 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v37, 37 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v38, 38 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v39, 39 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v40, 40 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v41, 41 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v42, 42 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v43, 43 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v44, 44 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v45, 45 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v46, 46 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v47, 47 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v48, 48 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v49, 49 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v50, 50 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v51, 51 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v52, 52 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v53, 53 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v54, 54 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v55, 55 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v56, 56 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v57, 57 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v58, 58 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v59, 59 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v60, 60 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v61, 61 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v62, 62 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v63, 63 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v64, 64 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v65, 65 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v66, 66 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v67, 67 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v68, 68 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v69, 69 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v70, 70 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v71, 71 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v72, 72 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v73, 73 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v74, 74 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v75, 75 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v76, 76 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v77, 77 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v78, 78 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v79, 79 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v80, 80 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v81, 81 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v82, 82 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v83, 83 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v84, 84 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v85, 85 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v86, 86 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v87, 87 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v88, 88 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v89, 89 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v90, 90 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v91, 91 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v92, 92 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v93, 93 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v94, 94 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v95, 95 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v96, 96 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v97, 97 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v98, 98 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v99, 99 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v100, 100 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v101, 101 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v102, 102 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v103, 103 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v104, 104 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v105, 105 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v106, 106 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v107, 107 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v108, 108 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v109, 109 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v110, 110 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v111, 111 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v112, 112 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v113, 113 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v114, 114 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v115, 115 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v116, 116 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v117, 117 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v118, 118 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v119, 119 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v120, 120 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v121, 121 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v122, 122 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v123, 123 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v124, 124 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v125, 125 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v126, 126 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v127, 127 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v128, 128 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v129, 129 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v130, 130 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v131, 131 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v132, 132 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v133, 133 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v134, 134 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v135, 135 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v136, 136 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v137, 137 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v138, 138 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v139, 139 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v140, 140 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v141, 141 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v142, 142 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v143, 143 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v144, 144 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v145, 145 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v146, 146 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v147, 147 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v148, 148 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v149, 149 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v150, 150 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v151, 151 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v152, 152 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v153, 153 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v154, 154 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v155, 155 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v156, 156 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v157, 157 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v158, 158 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v159, 159 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v160, 160 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v161, 161 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v162, 162 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v163, 163 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v164, 164 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v165, 165 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v166, 166 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v167, 167 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v168, 168 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v169, 169 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v170, 170 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v171, 171 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v172, 172 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v173, 173 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v174, 174 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v175, 175 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v176, 176 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v177, 177 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v178, 178 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v179, 179 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v180, 180 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v181, 181 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v182, 182 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v183, 183 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v184, 184 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v185, 185 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v186, 186 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v187, 187 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v188, 188 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v189, 189 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v190, 190 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v191, 191 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v192, 192 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v193, 193 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v194, 194 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v195, 195 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v196, 196 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v197, 197 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v198, 198 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v199, 199 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v200, 200 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v201, 201 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v202, 202 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v203, 203 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v204, 204 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v205, 205 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v206, 206 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v207, 207 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v208, 208 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v209, 209 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v210, 210 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v211, 211 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v212, 212 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v213, 213 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v214, 214 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v215, 215 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v216, 216 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v217, 217 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v218, 218 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v219, 219 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v220, 220 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v221, 221 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v222, 222 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v223, 223 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v224, 224 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v225, 225 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v226, 226 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v227, 227 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v228, 228 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v229, 229 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v230, 230 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v231, 231 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v232, 232 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v233, 233 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v234, 234 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v235, 235 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v236, 236 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v237, 237 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v238, 238 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v239, 239 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v240, 240 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v241, 241 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v242, 242 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v243, 243 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v244, 244 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v245, 245 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v246, 246 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v247, 247 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v248, 248 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v249, 249 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v250, 250 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v251, 251 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v252, 252 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v253, 253 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v254, 254 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( v255, 255 | BITS_32 | VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc0, 0 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc1, 1 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc2, 2 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc3, 3 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc4, 4 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc5, 5 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc6, 6 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc7, 7 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc8, 8 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc9, 9 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc10, 10 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc11, 11 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc12, 12 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc13, 13 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc14, 14 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc15, 15 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc16, 16 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc17, 17 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc18, 18 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc19, 19 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc20, 20 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc21, 21 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc22, 22 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc23, 23 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc24, 24 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc25, 25 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc26, 26 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc27, 27 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc28, 28 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc29, 29 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc30, 30 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc31, 31 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc32, 32 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc33, 33 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc34, 34 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc35, 35 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc36, 36 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc37, 37 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc38, 38 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc39, 39 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc40, 40 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc41, 41 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc42, 42 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc43, 43 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc44, 44 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc45, 45 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc46, 46 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc47, 47 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc48, 48 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc49, 49 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc50, 50 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc51, 51 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc52, 52 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc53, 53 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc54, 54 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc55, 55 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc56, 56 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc57, 57 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc58, 58 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc59, 59 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc60, 60 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc61, 61 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc62, 62 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc63, 63 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc64, 64 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc65, 65 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc66, 66 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc67, 67 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc68, 68 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc69, 69 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc70, 70 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc71, 71 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc72, 72 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc73, 73 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc74, 74 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc75, 75 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc76, 76 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc77, 77 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc78, 78 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc79, 79 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc80, 80 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc81, 81 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc82, 82 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc83, 83 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc84, 84 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc85, 85 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc86, 86 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc87, 87 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc88, 88 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc89, 89 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc90, 90 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc91, 91 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc92, 92 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc93, 93 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc94, 94 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc95, 95 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc96, 96 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc97, 97 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc98, 98 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc99, 99 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc100, 100 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc101, 101 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc102, 102 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc103, 103 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc104, 104 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc105, 105 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc106, 106 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc107, 107 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc108, 108 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc109, 109 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc110, 110 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc111, 111 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc112, 112 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc113, 113 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc114, 114 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc115, 115 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc116, 116 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc117, 117 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc118, 118 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc119, 119 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc120, 120 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc121, 121 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc122, 122 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc123, 123 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc124, 124 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc125, 125 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc126, 126 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc127, 127 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc128, 128 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc129, 129 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc130, 130 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc131, 131 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc132, 132 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc133, 133 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc134, 134 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc135, 135 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc136, 136 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc137, 137 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc138, 138 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc139, 139 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc140, 140 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc141, 141 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc142, 142 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc143, 143 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc144, 144 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc145, 145 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc146, 146 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc147, 147 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc148, 148 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc149, 149 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc150, 150 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc151, 151 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc152, 152 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc153, 153 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc154, 154 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc155, 155 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc156, 156 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc157, 157 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc158, 158 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc159, 159 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc160, 160 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc161, 161 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc162, 162 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc163, 163 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc164, 164 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc165, 165 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc166, 166 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc167, 167 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc168, 168 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc169, 169 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc170, 170 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc171, 171 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc172, 172 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc173, 173 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc174, 174 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc175, 175 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc176, 176 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc177, 177 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc178, 178 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc179, 179 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc180, 180 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc181, 181 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc182, 182 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc183, 183 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc184, 184 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc185, 185 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc186, 186 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc187, 187 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc188, 188 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc189, 189 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc190, 190 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc191, 191 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc192, 192 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc193, 193 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc194, 194 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc195, 195 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc196, 196 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc197, 197 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc198, 198 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc199, 199 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc200, 200 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc201, 201 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc202, 202 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc203, 203 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc204, 204 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc205, 205 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc206, 206 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc207, 207 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc208, 208 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc209, 209 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc210, 210 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc211, 211 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc212, 212 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc213, 213 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc214, 214 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc215, 215 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc216, 216 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc217, 217 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc218, 218 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc219, 219 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc220, 220 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc221, 221 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc222, 222 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc223, 223 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc224, 224 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc225, 225 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc226, 226 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc227, 227 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc228, 228 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc229, 229 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc230, 230 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc231, 231 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc232, 232 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc233, 233 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc234, 234 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc235, 235 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc236, 236 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc237, 237 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc238, 238 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc239, 239 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc240, 240 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc241, 241 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc242, 242 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc243, 243 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc244, 244 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc245, 245 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc246, 246 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc247, 247 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc248, 248 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc249, 249 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc250, 250 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc251, 251 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc252, 252 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc253, 253 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc254, 254 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + DEF_REGISTER( acc255, 255 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx908, "amdgpu_gfx908"); + +}} + +#endif diff --git a/common/h/registers/AMDGPU/amdgpu_gfx90a_regs.h b/common/h/registers/AMDGPU/amdgpu_gfx90a_regs.h new file mode 100644 index 0000000000..3d0222f6c2 --- /dev/null +++ b/common/h/registers/AMDGPU/amdgpu_gfx90a_regs.h @@ -0,0 +1,855 @@ +/* + * See the dyninst/COPYRIGHT file for copyright information. + * + * We provide the Paradyn Tools (below described as "Paradyn") + * on an AS IS basis, and do not warrant its validity or performance. + * We reserve the right to update, modify, or discontinue this + * software at any time. We shall have no obligation to supply such + * updates or modifications or any other form of support to you. + * + * By your use of Paradyn, you understand and agree that we (or any + * other person or entity with proprietary rights in Paradyn) are + * under no obligation to provide either maintenance services, + * update services, notices of latent defects, or correction of + * defects for Paradyn. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef DYNINST_AMDGPU_GFX90A_REGS_H +#define DYNINST_AMDGPU_GFX90A_REGS_H + +//clang-format: off + +#include "Architecture.h" +#include "registers/reg_def.h" + +namespace Dyninst { namespace amdgpu_gfx90a { + + /** + * For interpreting constants: + * Lowest 16 bits (0x000000ff) is base register ID + * Next 16 bits (0x0000ff00) is the aliasing and subrange ID- + * used on x86/x86_64 to distinguish between things like EAX and AH + * Next 16 bits (0x00ff0000) are the register category, GPR/FPR/MMX/... + * Top 16 bits (0xff000000) are the architecture. + * + * These values/layout are not guaranteed to remain the same as part of the + * public interface, and may change. + **/ + + // 0xff000000 0x00ff0000 0x0000ff00 0x000000ff + // arch reg cat:GPR alias&subrange reg ID + const signed int SGPR = 0x00010000; + const signed int VGPR = 0x00060000; + const signed int ACC_VGPR = 0x000B0000; + + const signed int HWR = 0x000C0000; + const signed int TTMP_SGPR = 0x000D0000; + const signed int FLAGS = 0x000E0000; + const signed int PC = 0x000F0000; + const signed int SYSREG = 0x00100000; + const signed int TGT = 0x00110000; // I have no idea what TGT is yet + const signed int ATTR = 0x00120000; + const signed int PARAM = 0x00130000; // LDS Parameter + const signed int INFO = 0x00130000; // Additional Info + + // aliasing for flags + // if we found out that it is a flag, we no longer need to use the cat 0x00ff0000 + // so we use that part to encode the low offset in the base register + // + + const signed int BITS_1 = 0x00000100; + const signed int BITS_2 = 0x00000200; + const signed int BITS_3 = 0x00000300; + const signed int BITS_4 = 0x00000400; + const signed int BITS_6 = 0x00000500; + const signed int BITS_7 = 0x00000600; + const signed int BITS_8 = 0x00000700; + const signed int BITS_9 = 0x00000800; + const signed int BITS_15 = 0x00000900; + const signed int BITS_16 = 0x00000A00; + const signed int BITS_32 = 0x00000B00; + const signed int BITS_48 = 0x00000C00; + const signed int BITS_64 = 0x00000D00; + const signed int BITS_128 = 0x00000E00; + const signed int BITS_256 = 0x00000F00; + const signed int BITS_512 = 0x00001000; + + // ( name, ID | alias | cat | arch, arch ) + DEF_REGISTER( tid, 0 | BITS_32 | SYSREG |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + + DEF_REGISTER( invalid, 1 | BITS_32 | SYSREG |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( pc_all, 0 | BITS_48 | PC |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + + DEF_REGISTER( src_scc, 0 | BITS_32 | HWR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + + DEF_REGISTER( src_vccz, 1 | BITS_1 | HWR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( vcc_lo, 2 | BITS_32 | HWR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( vcc_hi, 3 | BITS_32 | HWR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( vcc, 2 | BITS_64 | HWR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + + DEF_REGISTER( src_execz, 4 | BITS_1 | HWR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( exec_lo, 5 | BITS_32 | HWR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( exec_hi, 6 | BITS_32 | HWR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( exec, 5 | BITS_64 | HWR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + + DEF_REGISTER( flat_scratch_lo, 7 | BITS_64 | HWR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( flat_scratch_hi, 8 | BITS_32 | HWR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( flat_scratch_all, 7 | BITS_32 | HWR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + + DEF_REGISTER( m0, 10 | BITS_32 | HWR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + + DEF_REGISTER( src_literal, 11 | BITS_32 | HWR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a");//TODO + DEF_REGISTER(src_pops_exiting_wave_id, 12 | BITS_32 | HWR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a");//TODO + + DEF_REGISTER( src_private_base, 13 | BITS_32 | HWR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( src_private_limit, 14 | BITS_32 | HWR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( src_shared_base, 15 | BITS_32 | HWR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( src_shared_limit, 16 | BITS_32 | HWR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + + DEF_REGISTER( xnack_mask_lo, 17 | BITS_32 | HWR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( xnack_mask_hi, 18 | BITS_32 | HWR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + + DEF_REGISTER( src_lds_direct, 19 | BITS_32 | HWR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( vmcnt, 20 | BITS_32 | HWR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( expcnt, 21 | BITS_32 | HWR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( lgkmcnt, 22 | BITS_32 | HWR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( dsmem, 23 | BITS_32 | HWR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + + DEF_REGISTER( ttmp0, 0 | BITS_32 | TTMP_SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( ttmp1, 1 | BITS_32 | TTMP_SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( ttmp2, 2 | BITS_32 | TTMP_SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( ttmp3, 3 | BITS_32 | TTMP_SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( ttmp4, 4 | BITS_32 | TTMP_SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( ttmp5, 5 | BITS_32 | TTMP_SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( ttmp6, 6 | BITS_32 | TTMP_SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( ttmp7, 7 | BITS_32 | TTMP_SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( ttmp8, 8 | BITS_32 | TTMP_SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( ttmp9, 9 | BITS_32 | TTMP_SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( ttmp10, 10 | BITS_32 | TTMP_SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( ttmp11, 11 | BITS_32 | TTMP_SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( ttmp12, 12 | BITS_32 | TTMP_SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( ttmp13, 13 | BITS_32 | TTMP_SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( ttmp14, 14 | BITS_32 | TTMP_SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( ttmp15, 15 | BITS_32 | TTMP_SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + + DEF_REGISTER( mrt0, 0 | BITS_32 | TGT |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( mrt1, 1 | BITS_32 | TGT |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( mrt2, 2 | BITS_32 | TGT |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( mrt3, 3 | BITS_32 | TGT |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( mrt4, 4 | BITS_32 | TGT |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( mrt5, 5 | BITS_32 | TGT |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( mrt6, 6 | BITS_32 | TGT |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( mrt7, 7 | BITS_32 | TGT |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( mrtz, 8 | BITS_32 | TGT |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( null, 9 | BITS_32 | TGT |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( pos0, 12 | BITS_32 | TGT |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( pos1, 13 | BITS_32 | TGT |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( pos2, 14 | BITS_32 | TGT |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( pos3, 15 | BITS_32 | TGT |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( param0, 32 | BITS_32 | TGT |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( param1, 33 | BITS_32 | TGT |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( param2, 34 | BITS_32 | TGT |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( param3, 35 | BITS_32 | TGT |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( param4, 36 | BITS_32 | TGT |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( param5, 37 | BITS_32 | TGT |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( param6, 38 | BITS_32 | TGT |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( param7, 39 | BITS_32 | TGT |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( param8, 40 | BITS_32 | TGT |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( param9, 41 | BITS_32 | TGT |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( param10, 42 | BITS_32 | TGT |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( param11, 43 | BITS_32 | TGT |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( param12, 44 | BITS_32 | TGT |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( param13, 45 | BITS_32 | TGT |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( param14, 46 | BITS_32 | TGT |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( param15, 47 | BITS_32 | TGT |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( param16, 48 | BITS_32 | TGT |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( param17, 49 | BITS_32 | TGT |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( param18, 50 | BITS_32 | TGT |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( param19, 51 | BITS_32 | TGT |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( param20, 52 | BITS_32 | TGT |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( param21, 53 | BITS_32 | TGT |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( param22, 54 | BITS_32 | TGT |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( param23, 55 | BITS_32 | TGT |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( param24, 56 | BITS_32 | TGT |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( param25, 57 | BITS_32 | TGT |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( param26, 58 | BITS_32 | TGT |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( param27, 59 | BITS_32 | TGT |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( param28, 60 | BITS_32 | TGT |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( param29, 61 | BITS_32 | TGT |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( param30, 62 | BITS_32 | TGT |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( param31, 63 | BITS_32 | TGT |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + + DEF_REGISTER( attr0, 0 | BITS_32 | ATTR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( attr1, 1 | BITS_32 | ATTR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( attr2, 2 | BITS_32 | ATTR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( attr3, 3 | BITS_32 | ATTR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( attr4, 4 | BITS_32 | ATTR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( attr5, 5 | BITS_32 | ATTR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( attr6, 6 | BITS_32 | ATTR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( attr7, 7 | BITS_32 | ATTR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( attr8, 8 | BITS_32 | ATTR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( attr9, 9 | BITS_32 | ATTR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( attr10, 10 | BITS_32 | ATTR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( attr11, 11 | BITS_32 | ATTR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( attr12, 12 | BITS_32 | ATTR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( attr13, 13 | BITS_32 | ATTR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( attr14, 14 | BITS_32 | ATTR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( attr15, 15 | BITS_32 | ATTR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( attr16, 16 | BITS_32 | ATTR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( attr17, 17 | BITS_32 | ATTR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( attr18, 18 | BITS_32 | ATTR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( attr19, 19 | BITS_32 | ATTR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( attr20, 20 | BITS_32 | ATTR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( attr21, 21 | BITS_32 | ATTR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( attr22, 22 | BITS_32 | ATTR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( attr23, 23 | BITS_32 | ATTR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( attr24, 24 | BITS_32 | ATTR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( attr25, 25 | BITS_32 | ATTR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( attr26, 26 | BITS_32 | ATTR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( attr27, 27 | BITS_32 | ATTR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( attr28, 28 | BITS_32 | ATTR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( attr29, 29 | BITS_32 | ATTR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( attr30, 30 | BITS_32 | ATTR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( attr31, 31 | BITS_32 | ATTR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( attr32, 32 | BITS_32 | ATTR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + + DEF_REGISTER( p10, 0 | BITS_32 | PARAM |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( p20, 1 | BITS_32 | PARAM |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( p0, 2 | BITS_32 | PARAM |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + + DEF_REGISTER( idxen, 0 | BITS_1 | INFO |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( offen, 1 | BITS_1 | INFO |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( off, 2 | BITS_1 | INFO |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + + DEF_REGISTER( s0, 0 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s1, 1 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s2, 2 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s3, 3 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s4, 4 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s5, 5 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s6, 6 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s7, 7 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s8, 8 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s9, 9 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s10, 10 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s11, 11 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s12, 12 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s13, 13 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s14, 14 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s15, 15 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s16, 16 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s17, 17 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s18, 18 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s19, 19 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s20, 20 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s21, 21 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s22, 22 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s23, 23 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s24, 24 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s25, 25 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s26, 26 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s27, 27 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s28, 28 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s29, 29 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s30, 30 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s31, 31 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s32, 32 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s33, 33 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s34, 34 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s35, 35 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s36, 36 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s37, 37 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s38, 38 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s39, 39 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s40, 40 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s41, 41 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s42, 42 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s43, 43 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s44, 44 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s45, 45 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s46, 46 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s47, 47 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s48, 48 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s49, 49 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s50, 50 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s51, 51 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s52, 52 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s53, 53 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s54, 54 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s55, 55 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s56, 56 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s57, 57 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s58, 58 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s59, 59 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s60, 60 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s61, 61 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s62, 62 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s63, 63 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s64, 64 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s65, 65 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s66, 66 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s67, 67 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s68, 68 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s69, 69 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s70, 70 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s71, 71 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s72, 72 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s73, 73 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s74, 74 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s75, 75 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s76, 76 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s77, 77 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s78, 78 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s79, 79 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s80, 80 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s81, 81 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s82, 82 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s83, 83 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s84, 84 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s85, 85 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s86, 86 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s87, 87 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s88, 88 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s89, 89 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s90, 90 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s91, 91 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s92, 92 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s93, 93 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s94, 94 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s95, 95 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s96, 96 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s97, 97 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s98, 98 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s99, 99 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s100, 100 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( s101, 101 | BITS_32 | SGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v0, 0 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v1, 1 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v2, 2 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v3, 3 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v4, 4 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v5, 5 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v6, 6 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v7, 7 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v8, 8 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v9, 9 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v10, 10 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v11, 11 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v12, 12 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v13, 13 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v14, 14 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v15, 15 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v16, 16 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v17, 17 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v18, 18 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v19, 19 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v20, 20 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v21, 21 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v22, 22 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v23, 23 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v24, 24 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v25, 25 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v26, 26 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v27, 27 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v28, 28 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v29, 29 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v30, 30 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v31, 31 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v32, 32 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v33, 33 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v34, 34 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v35, 35 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v36, 36 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v37, 37 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v38, 38 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v39, 39 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v40, 40 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v41, 41 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v42, 42 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v43, 43 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v44, 44 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v45, 45 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v46, 46 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v47, 47 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v48, 48 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v49, 49 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v50, 50 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v51, 51 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v52, 52 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v53, 53 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v54, 54 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v55, 55 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v56, 56 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v57, 57 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v58, 58 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v59, 59 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v60, 60 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v61, 61 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v62, 62 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v63, 63 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v64, 64 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v65, 65 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v66, 66 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v67, 67 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v68, 68 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v69, 69 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v70, 70 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v71, 71 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v72, 72 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v73, 73 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v74, 74 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v75, 75 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v76, 76 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v77, 77 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v78, 78 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v79, 79 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v80, 80 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v81, 81 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v82, 82 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v83, 83 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v84, 84 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v85, 85 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v86, 86 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v87, 87 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v88, 88 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v89, 89 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v90, 90 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v91, 91 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v92, 92 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v93, 93 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v94, 94 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v95, 95 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v96, 96 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v97, 97 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v98, 98 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v99, 99 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v100, 100 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v101, 101 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v102, 102 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v103, 103 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v104, 104 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v105, 105 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v106, 106 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v107, 107 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v108, 108 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v109, 109 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v110, 110 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v111, 111 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v112, 112 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v113, 113 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v114, 114 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v115, 115 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v116, 116 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v117, 117 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v118, 118 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v119, 119 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v120, 120 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v121, 121 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v122, 122 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v123, 123 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v124, 124 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v125, 125 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v126, 126 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v127, 127 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v128, 128 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v129, 129 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v130, 130 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v131, 131 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v132, 132 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v133, 133 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v134, 134 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v135, 135 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v136, 136 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v137, 137 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v138, 138 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v139, 139 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v140, 140 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v141, 141 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v142, 142 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v143, 143 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v144, 144 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v145, 145 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v146, 146 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v147, 147 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v148, 148 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v149, 149 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v150, 150 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v151, 151 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v152, 152 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v153, 153 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v154, 154 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v155, 155 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v156, 156 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v157, 157 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v158, 158 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v159, 159 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v160, 160 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v161, 161 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v162, 162 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v163, 163 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v164, 164 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v165, 165 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v166, 166 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v167, 167 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v168, 168 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v169, 169 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v170, 170 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v171, 171 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v172, 172 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v173, 173 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v174, 174 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v175, 175 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v176, 176 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v177, 177 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v178, 178 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v179, 179 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v180, 180 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v181, 181 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v182, 182 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v183, 183 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v184, 184 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v185, 185 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v186, 186 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v187, 187 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v188, 188 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v189, 189 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v190, 190 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v191, 191 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v192, 192 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v193, 193 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v194, 194 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v195, 195 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v196, 196 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v197, 197 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v198, 198 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v199, 199 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v200, 200 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v201, 201 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v202, 202 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v203, 203 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v204, 204 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v205, 205 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v206, 206 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v207, 207 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v208, 208 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v209, 209 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v210, 210 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v211, 211 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v212, 212 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v213, 213 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v214, 214 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v215, 215 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v216, 216 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v217, 217 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v218, 218 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v219, 219 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v220, 220 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v221, 221 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v222, 222 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v223, 223 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v224, 224 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v225, 225 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v226, 226 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v227, 227 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v228, 228 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v229, 229 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v230, 230 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v231, 231 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v232, 232 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v233, 233 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v234, 234 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v235, 235 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v236, 236 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v237, 237 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v238, 238 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v239, 239 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v240, 240 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v241, 241 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v242, 242 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v243, 243 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v244, 244 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v245, 245 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v246, 246 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v247, 247 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v248, 248 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v249, 249 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v250, 250 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v251, 251 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v252, 252 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v253, 253 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v254, 254 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( v255, 255 | BITS_32 | VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc0, 0 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc1, 1 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc2, 2 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc3, 3 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc4, 4 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc5, 5 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc6, 6 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc7, 7 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc8, 8 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc9, 9 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc10, 10 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc11, 11 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc12, 12 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc13, 13 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc14, 14 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc15, 15 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc16, 16 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc17, 17 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc18, 18 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc19, 19 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc20, 20 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc21, 21 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc22, 22 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc23, 23 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc24, 24 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc25, 25 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc26, 26 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc27, 27 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc28, 28 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc29, 29 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc30, 30 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc31, 31 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc32, 32 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc33, 33 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc34, 34 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc35, 35 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc36, 36 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc37, 37 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc38, 38 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc39, 39 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc40, 40 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc41, 41 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc42, 42 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc43, 43 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc44, 44 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc45, 45 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc46, 46 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc47, 47 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc48, 48 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc49, 49 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc50, 50 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc51, 51 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc52, 52 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc53, 53 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc54, 54 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc55, 55 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc56, 56 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc57, 57 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc58, 58 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc59, 59 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc60, 60 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc61, 61 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc62, 62 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc63, 63 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc64, 64 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc65, 65 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc66, 66 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc67, 67 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc68, 68 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc69, 69 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc70, 70 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc71, 71 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc72, 72 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc73, 73 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc74, 74 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc75, 75 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc76, 76 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc77, 77 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc78, 78 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc79, 79 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc80, 80 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc81, 81 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc82, 82 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc83, 83 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc84, 84 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc85, 85 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc86, 86 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc87, 87 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc88, 88 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc89, 89 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc90, 90 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc91, 91 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc92, 92 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc93, 93 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc94, 94 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc95, 95 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc96, 96 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc97, 97 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc98, 98 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc99, 99 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc100, 100 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc101, 101 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc102, 102 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc103, 103 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc104, 104 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc105, 105 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc106, 106 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc107, 107 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc108, 108 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc109, 109 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc110, 110 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc111, 111 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc112, 112 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc113, 113 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc114, 114 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc115, 115 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc116, 116 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc117, 117 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc118, 118 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc119, 119 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc120, 120 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc121, 121 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc122, 122 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc123, 123 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc124, 124 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc125, 125 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc126, 126 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc127, 127 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc128, 128 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc129, 129 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc130, 130 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc131, 131 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc132, 132 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc133, 133 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc134, 134 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc135, 135 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc136, 136 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc137, 137 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc138, 138 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc139, 139 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc140, 140 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc141, 141 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc142, 142 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc143, 143 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc144, 144 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc145, 145 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc146, 146 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc147, 147 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc148, 148 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc149, 149 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc150, 150 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc151, 151 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc152, 152 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc153, 153 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc154, 154 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc155, 155 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc156, 156 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc157, 157 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc158, 158 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc159, 159 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc160, 160 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc161, 161 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc162, 162 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc163, 163 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc164, 164 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc165, 165 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc166, 166 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc167, 167 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc168, 168 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc169, 169 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc170, 170 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc171, 171 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc172, 172 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc173, 173 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc174, 174 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc175, 175 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc176, 176 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc177, 177 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc178, 178 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc179, 179 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc180, 180 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc181, 181 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc182, 182 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc183, 183 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc184, 184 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc185, 185 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc186, 186 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc187, 187 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc188, 188 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc189, 189 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc190, 190 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc191, 191 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc192, 192 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc193, 193 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc194, 194 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc195, 195 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc196, 196 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc197, 197 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc198, 198 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc199, 199 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc200, 200 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc201, 201 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc202, 202 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc203, 203 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc204, 204 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc205, 205 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc206, 206 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc207, 207 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc208, 208 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc209, 209 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc210, 210 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc211, 211 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc212, 212 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc213, 213 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc214, 214 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc215, 215 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc216, 216 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc217, 217 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc218, 218 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc219, 219 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc220, 220 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc221, 221 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc222, 222 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc223, 223 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc224, 224 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc225, 225 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc226, 226 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc227, 227 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc228, 228 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc229, 229 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc230, 230 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc231, 231 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc232, 232 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc233, 233 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc234, 234 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc235, 235 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc236, 236 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc237, 237 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc238, 238 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc239, 239 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc240, 240 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc241, 241 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc242, 242 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc243, 243 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc244, 244 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc245, 245 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc246, 246 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc247, 247 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc248, 248 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc249, 249 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc250, 250 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc251, 251 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc252, 252 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc253, 253 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc254, 254 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + DEF_REGISTER( acc255, 255 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx90a, "amdgpu_gfx90a"); + +}} + +#endif diff --git a/common/h/registers/AMDGPU/amdgpu_gfx940_regs.h b/common/h/registers/AMDGPU/amdgpu_gfx940_regs.h new file mode 100644 index 0000000000..dffcf52616 --- /dev/null +++ b/common/h/registers/AMDGPU/amdgpu_gfx940_regs.h @@ -0,0 +1,855 @@ +/* + * See the dyninst/COPYRIGHT file for copyright information. + * + * We provide the Paradyn Tools (below described as "Paradyn") + * on an AS IS basis, and do not warrant its validity or performance. + * We reserve the right to update, modify, or discontinue this + * software at any time. We shall have no obligation to supply such + * updates or modifications or any other form of support to you. + * + * By your use of Paradyn, you understand and agree that we (or any + * other person or entity with proprietary rights in Paradyn) are + * under no obligation to provide either maintenance services, + * update services, notices of latent defects, or correction of + * defects for Paradyn. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef DYNINST_AMDGPU_GFX940_REGS_H +#define DYNINST_AMDGPU_GFX940_REGS_H + +//clang-format: off + +#include "Architecture.h" +#include "registers/reg_def.h" + +namespace Dyninst { namespace amdgpu_gfx940 { + + /** + * For interpreting constants: + * Lowest 16 bits (0x000000ff) is base register ID + * Next 16 bits (0x0000ff00) is the aliasing and subrange ID- + * used on x86/x86_64 to distinguish between things like EAX and AH + * Next 16 bits (0x00ff0000) are the register category, GPR/FPR/MMX/... + * Top 16 bits (0xff000000) are the architecture. + * + * These values/layout are not guaranteed to remain the same as part of the + * public interface, and may change. + **/ + + // 0xff000000 0x00ff0000 0x0000ff00 0x000000ff + // arch reg cat:GPR alias&subrange reg ID +const signed int SGPR = 0x00010000; +const signed int VGPR = 0x00060000; +const signed int ACC_VGPR = 0x000B0000; + +const signed int HWR = 0x000C0000; +const signed int TTMP_SGPR = 0x000D0000; +const signed int FLAGS = 0x000E0000; +const signed int PC = 0x000F0000; +const signed int SYSREG = 0x00100000; +const signed int TGT = 0x00110000; // I have no idea what TGT is yet +const signed int ATTR = 0x00120000; +const signed int PARAM = 0x00130000; // LDS Parameter +const signed int INFO = 0x00130000; // Additional Info + +// aliasing for flags +// if we found out that it is a flag, we no longer need to use the cat 0x00ff0000 +// so we use that part to encode the low offset in the base register +// + +const signed int BITS_1 = 0x00000100; +const signed int BITS_2 = 0x00000200; +const signed int BITS_3 = 0x00000300; +const signed int BITS_4 = 0x00000400; +const signed int BITS_6 = 0x00000500; +const signed int BITS_7 = 0x00000600; +const signed int BITS_8 = 0x00000700; +const signed int BITS_9 = 0x00000800; +const signed int BITS_15 = 0x00000900; +const signed int BITS_16 = 0x00000A00; +const signed int BITS_32 = 0x00000B00; +const signed int BITS_48 = 0x00000C00; +const signed int BITS_64 = 0x00000D00; +const signed int BITS_128 = 0x00000E00; +const signed int BITS_256 = 0x00000F00; +const signed int BITS_512 = 0x00001000; + + // ( name, ID | alias | cat | arch, arch ) + DEF_REGISTER( tid, 0 | BITS_32 | SYSREG |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + + DEF_REGISTER( invalid, 1 | BITS_32 | SYSREG |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( pc_all, 0 | BITS_48 | PC |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + + DEF_REGISTER( src_scc, 0 | BITS_32 | HWR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + + DEF_REGISTER( src_vccz, 1 | BITS_1 | HWR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( vcc_lo, 2 | BITS_32 | HWR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( vcc_hi, 3 | BITS_32 | HWR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( vcc, 2 | BITS_64 | HWR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + + DEF_REGISTER( src_execz, 4 | BITS_1 | HWR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( exec_lo, 5 | BITS_32 | HWR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( exec_hi, 6 | BITS_32 | HWR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( exec, 5 | BITS_64 | HWR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + + DEF_REGISTER( flat_scratch_lo, 7 | BITS_64 | HWR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( flat_scratch_hi, 8 | BITS_32 | HWR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( flat_scratch_all, 7 | BITS_32 | HWR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + + DEF_REGISTER( m0, 10 | BITS_32 | HWR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + + DEF_REGISTER( src_literal, 11 | BITS_32 | HWR |Arch_amdgpu_gfx940, "amdgpu_gfx940");//TODO + DEF_REGISTER(src_pops_exiting_wave_id, 12 | BITS_32 | HWR |Arch_amdgpu_gfx940, "amdgpu_gfx940");//TODO + + DEF_REGISTER( src_private_base, 13 | BITS_32 | HWR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( src_private_limit, 14 | BITS_32 | HWR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( src_shared_base, 15 | BITS_32 | HWR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( src_shared_limit, 16 | BITS_32 | HWR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + + DEF_REGISTER( xnack_mask_lo, 17 | BITS_32 | HWR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( xnack_mask_hi, 18 | BITS_32 | HWR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + + DEF_REGISTER( src_lds_direct, 19 | BITS_32 | HWR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( vmcnt, 20 | BITS_32 | HWR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( expcnt, 21 | BITS_32 | HWR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( lgkmcnt, 22 | BITS_32 | HWR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( dsmem, 23 | BITS_32 | HWR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + + DEF_REGISTER( ttmp0, 0 | BITS_32 | TTMP_SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( ttmp1, 1 | BITS_32 | TTMP_SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( ttmp2, 2 | BITS_32 | TTMP_SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( ttmp3, 3 | BITS_32 | TTMP_SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( ttmp4, 4 | BITS_32 | TTMP_SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( ttmp5, 5 | BITS_32 | TTMP_SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( ttmp6, 6 | BITS_32 | TTMP_SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( ttmp7, 7 | BITS_32 | TTMP_SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( ttmp8, 8 | BITS_32 | TTMP_SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( ttmp9, 9 | BITS_32 | TTMP_SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( ttmp10, 10 | BITS_32 | TTMP_SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( ttmp11, 11 | BITS_32 | TTMP_SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( ttmp12, 12 | BITS_32 | TTMP_SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( ttmp13, 13 | BITS_32 | TTMP_SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( ttmp14, 14 | BITS_32 | TTMP_SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( ttmp15, 15 | BITS_32 | TTMP_SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + + DEF_REGISTER( mrt0, 0 | BITS_32 | TGT |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( mrt1, 1 | BITS_32 | TGT |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( mrt2, 2 | BITS_32 | TGT |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( mrt3, 3 | BITS_32 | TGT |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( mrt4, 4 | BITS_32 | TGT |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( mrt5, 5 | BITS_32 | TGT |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( mrt6, 6 | BITS_32 | TGT |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( mrt7, 7 | BITS_32 | TGT |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( mrtz, 8 | BITS_32 | TGT |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( null, 9 | BITS_32 | TGT |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( pos0, 12 | BITS_32 | TGT |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( pos1, 13 | BITS_32 | TGT |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( pos2, 14 | BITS_32 | TGT |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( pos3, 15 | BITS_32 | TGT |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( param0, 32 | BITS_32 | TGT |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( param1, 33 | BITS_32 | TGT |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( param2, 34 | BITS_32 | TGT |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( param3, 35 | BITS_32 | TGT |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( param4, 36 | BITS_32 | TGT |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( param5, 37 | BITS_32 | TGT |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( param6, 38 | BITS_32 | TGT |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( param7, 39 | BITS_32 | TGT |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( param8, 40 | BITS_32 | TGT |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( param9, 41 | BITS_32 | TGT |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( param10, 42 | BITS_32 | TGT |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( param11, 43 | BITS_32 | TGT |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( param12, 44 | BITS_32 | TGT |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( param13, 45 | BITS_32 | TGT |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( param14, 46 | BITS_32 | TGT |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( param15, 47 | BITS_32 | TGT |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( param16, 48 | BITS_32 | TGT |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( param17, 49 | BITS_32 | TGT |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( param18, 50 | BITS_32 | TGT |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( param19, 51 | BITS_32 | TGT |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( param20, 52 | BITS_32 | TGT |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( param21, 53 | BITS_32 | TGT |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( param22, 54 | BITS_32 | TGT |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( param23, 55 | BITS_32 | TGT |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( param24, 56 | BITS_32 | TGT |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( param25, 57 | BITS_32 | TGT |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( param26, 58 | BITS_32 | TGT |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( param27, 59 | BITS_32 | TGT |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( param28, 60 | BITS_32 | TGT |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( param29, 61 | BITS_32 | TGT |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( param30, 62 | BITS_32 | TGT |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( param31, 63 | BITS_32 | TGT |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + + DEF_REGISTER( attr0, 0 | BITS_32 | ATTR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( attr1, 1 | BITS_32 | ATTR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( attr2, 2 | BITS_32 | ATTR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( attr3, 3 | BITS_32 | ATTR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( attr4, 4 | BITS_32 | ATTR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( attr5, 5 | BITS_32 | ATTR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( attr6, 6 | BITS_32 | ATTR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( attr7, 7 | BITS_32 | ATTR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( attr8, 8 | BITS_32 | ATTR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( attr9, 9 | BITS_32 | ATTR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( attr10, 10 | BITS_32 | ATTR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( attr11, 11 | BITS_32 | ATTR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( attr12, 12 | BITS_32 | ATTR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( attr13, 13 | BITS_32 | ATTR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( attr14, 14 | BITS_32 | ATTR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( attr15, 15 | BITS_32 | ATTR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( attr16, 16 | BITS_32 | ATTR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( attr17, 17 | BITS_32 | ATTR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( attr18, 18 | BITS_32 | ATTR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( attr19, 19 | BITS_32 | ATTR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( attr20, 20 | BITS_32 | ATTR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( attr21, 21 | BITS_32 | ATTR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( attr22, 22 | BITS_32 | ATTR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( attr23, 23 | BITS_32 | ATTR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( attr24, 24 | BITS_32 | ATTR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( attr25, 25 | BITS_32 | ATTR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( attr26, 26 | BITS_32 | ATTR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( attr27, 27 | BITS_32 | ATTR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( attr28, 28 | BITS_32 | ATTR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( attr29, 29 | BITS_32 | ATTR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( attr30, 30 | BITS_32 | ATTR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( attr31, 31 | BITS_32 | ATTR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( attr32, 32 | BITS_32 | ATTR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + + DEF_REGISTER( p10, 0 | BITS_32 | PARAM |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( p20, 1 | BITS_32 | PARAM |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( p0, 2 | BITS_32 | PARAM |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + + DEF_REGISTER( idxen, 0 | BITS_1 | INFO |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( offen, 1 | BITS_1 | INFO |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( off, 2 | BITS_1 | INFO |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + + DEF_REGISTER( s0, 0 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s1, 1 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s2, 2 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s3, 3 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s4, 4 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s5, 5 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s6, 6 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s7, 7 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s8, 8 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s9, 9 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s10, 10 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s11, 11 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s12, 12 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s13, 13 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s14, 14 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s15, 15 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s16, 16 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s17, 17 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s18, 18 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s19, 19 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s20, 20 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s21, 21 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s22, 22 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s23, 23 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s24, 24 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s25, 25 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s26, 26 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s27, 27 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s28, 28 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s29, 29 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s30, 30 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s31, 31 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s32, 32 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s33, 33 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s34, 34 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s35, 35 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s36, 36 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s37, 37 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s38, 38 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s39, 39 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s40, 40 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s41, 41 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s42, 42 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s43, 43 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s44, 44 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s45, 45 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s46, 46 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s47, 47 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s48, 48 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s49, 49 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s50, 50 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s51, 51 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s52, 52 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s53, 53 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s54, 54 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s55, 55 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s56, 56 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s57, 57 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s58, 58 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s59, 59 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s60, 60 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s61, 61 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s62, 62 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s63, 63 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s64, 64 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s65, 65 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s66, 66 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s67, 67 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s68, 68 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s69, 69 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s70, 70 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s71, 71 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s72, 72 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s73, 73 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s74, 74 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s75, 75 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s76, 76 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s77, 77 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s78, 78 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s79, 79 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s80, 80 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s81, 81 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s82, 82 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s83, 83 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s84, 84 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s85, 85 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s86, 86 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s87, 87 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s88, 88 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s89, 89 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s90, 90 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s91, 91 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s92, 92 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s93, 93 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s94, 94 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s95, 95 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s96, 96 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s97, 97 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s98, 98 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s99, 99 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s100, 100 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( s101, 101 | BITS_32 | SGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v0, 0 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v1, 1 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v2, 2 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v3, 3 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v4, 4 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v5, 5 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v6, 6 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v7, 7 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v8, 8 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v9, 9 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v10, 10 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v11, 11 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v12, 12 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v13, 13 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v14, 14 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v15, 15 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v16, 16 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v17, 17 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v18, 18 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v19, 19 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v20, 20 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v21, 21 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v22, 22 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v23, 23 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v24, 24 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v25, 25 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v26, 26 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v27, 27 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v28, 28 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v29, 29 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v30, 30 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v31, 31 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v32, 32 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v33, 33 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v34, 34 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v35, 35 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v36, 36 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v37, 37 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v38, 38 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v39, 39 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v40, 40 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v41, 41 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v42, 42 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v43, 43 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v44, 44 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v45, 45 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v46, 46 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v47, 47 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v48, 48 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v49, 49 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v50, 50 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v51, 51 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v52, 52 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v53, 53 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v54, 54 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v55, 55 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v56, 56 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v57, 57 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v58, 58 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v59, 59 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v60, 60 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v61, 61 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v62, 62 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v63, 63 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v64, 64 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v65, 65 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v66, 66 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v67, 67 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v68, 68 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v69, 69 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v70, 70 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v71, 71 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v72, 72 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v73, 73 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v74, 74 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v75, 75 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v76, 76 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v77, 77 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v78, 78 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v79, 79 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v80, 80 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v81, 81 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v82, 82 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v83, 83 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v84, 84 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v85, 85 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v86, 86 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v87, 87 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v88, 88 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v89, 89 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v90, 90 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v91, 91 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v92, 92 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v93, 93 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v94, 94 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v95, 95 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v96, 96 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v97, 97 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v98, 98 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v99, 99 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v100, 100 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v101, 101 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v102, 102 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v103, 103 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v104, 104 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v105, 105 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v106, 106 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v107, 107 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v108, 108 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v109, 109 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v110, 110 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v111, 111 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v112, 112 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v113, 113 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v114, 114 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v115, 115 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v116, 116 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v117, 117 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v118, 118 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v119, 119 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v120, 120 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v121, 121 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v122, 122 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v123, 123 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v124, 124 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v125, 125 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v126, 126 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v127, 127 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v128, 128 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v129, 129 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v130, 130 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v131, 131 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v132, 132 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v133, 133 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v134, 134 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v135, 135 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v136, 136 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v137, 137 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v138, 138 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v139, 139 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v140, 140 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v141, 141 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v142, 142 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v143, 143 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v144, 144 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v145, 145 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v146, 146 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v147, 147 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v148, 148 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v149, 149 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v150, 150 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v151, 151 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v152, 152 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v153, 153 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v154, 154 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v155, 155 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v156, 156 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v157, 157 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v158, 158 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v159, 159 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v160, 160 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v161, 161 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v162, 162 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v163, 163 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v164, 164 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v165, 165 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v166, 166 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v167, 167 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v168, 168 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v169, 169 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v170, 170 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v171, 171 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v172, 172 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v173, 173 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v174, 174 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v175, 175 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v176, 176 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v177, 177 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v178, 178 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v179, 179 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v180, 180 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v181, 181 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v182, 182 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v183, 183 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v184, 184 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v185, 185 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v186, 186 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v187, 187 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v188, 188 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v189, 189 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v190, 190 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v191, 191 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v192, 192 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v193, 193 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v194, 194 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v195, 195 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v196, 196 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v197, 197 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v198, 198 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v199, 199 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v200, 200 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v201, 201 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v202, 202 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v203, 203 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v204, 204 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v205, 205 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v206, 206 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v207, 207 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v208, 208 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v209, 209 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v210, 210 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v211, 211 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v212, 212 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v213, 213 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v214, 214 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v215, 215 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v216, 216 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v217, 217 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v218, 218 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v219, 219 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v220, 220 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v221, 221 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v222, 222 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v223, 223 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v224, 224 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v225, 225 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v226, 226 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v227, 227 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v228, 228 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v229, 229 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v230, 230 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v231, 231 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v232, 232 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v233, 233 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v234, 234 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v235, 235 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v236, 236 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v237, 237 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v238, 238 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v239, 239 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v240, 240 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v241, 241 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v242, 242 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v243, 243 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v244, 244 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v245, 245 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v246, 246 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v247, 247 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v248, 248 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v249, 249 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v250, 250 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v251, 251 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v252, 252 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v253, 253 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v254, 254 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( v255, 255 | BITS_32 | VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc0, 0 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc1, 1 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc2, 2 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc3, 3 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc4, 4 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc5, 5 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc6, 6 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc7, 7 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc8, 8 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc9, 9 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc10, 10 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc11, 11 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc12, 12 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc13, 13 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc14, 14 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc15, 15 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc16, 16 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc17, 17 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc18, 18 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc19, 19 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc20, 20 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc21, 21 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc22, 22 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc23, 23 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc24, 24 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc25, 25 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc26, 26 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc27, 27 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc28, 28 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc29, 29 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc30, 30 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc31, 31 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc32, 32 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc33, 33 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc34, 34 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc35, 35 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc36, 36 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc37, 37 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc38, 38 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc39, 39 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc40, 40 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc41, 41 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc42, 42 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc43, 43 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc44, 44 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc45, 45 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc46, 46 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc47, 47 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc48, 48 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc49, 49 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc50, 50 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc51, 51 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc52, 52 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc53, 53 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc54, 54 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc55, 55 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc56, 56 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc57, 57 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc58, 58 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc59, 59 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc60, 60 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc61, 61 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc62, 62 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc63, 63 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc64, 64 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc65, 65 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc66, 66 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc67, 67 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc68, 68 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc69, 69 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc70, 70 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc71, 71 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc72, 72 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc73, 73 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc74, 74 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc75, 75 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc76, 76 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc77, 77 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc78, 78 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc79, 79 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc80, 80 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc81, 81 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc82, 82 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc83, 83 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc84, 84 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc85, 85 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc86, 86 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc87, 87 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc88, 88 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc89, 89 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc90, 90 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc91, 91 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc92, 92 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc93, 93 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc94, 94 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc95, 95 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc96, 96 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc97, 97 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc98, 98 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc99, 99 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc100, 100 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc101, 101 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc102, 102 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc103, 103 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc104, 104 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc105, 105 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc106, 106 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc107, 107 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc108, 108 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc109, 109 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc110, 110 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc111, 111 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc112, 112 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc113, 113 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc114, 114 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc115, 115 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc116, 116 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc117, 117 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc118, 118 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc119, 119 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc120, 120 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc121, 121 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc122, 122 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc123, 123 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc124, 124 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc125, 125 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc126, 126 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc127, 127 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc128, 128 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc129, 129 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc130, 130 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc131, 131 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc132, 132 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc133, 133 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc134, 134 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc135, 135 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc136, 136 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc137, 137 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc138, 138 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc139, 139 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc140, 140 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc141, 141 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc142, 142 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc143, 143 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc144, 144 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc145, 145 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc146, 146 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc147, 147 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc148, 148 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc149, 149 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc150, 150 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc151, 151 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc152, 152 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc153, 153 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc154, 154 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc155, 155 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc156, 156 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc157, 157 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc158, 158 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc159, 159 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc160, 160 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc161, 161 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc162, 162 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc163, 163 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc164, 164 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc165, 165 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc166, 166 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc167, 167 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc168, 168 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc169, 169 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc170, 170 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc171, 171 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc172, 172 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc173, 173 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc174, 174 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc175, 175 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc176, 176 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc177, 177 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc178, 178 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc179, 179 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc180, 180 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc181, 181 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc182, 182 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc183, 183 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc184, 184 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc185, 185 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc186, 186 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc187, 187 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc188, 188 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc189, 189 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc190, 190 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc191, 191 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc192, 192 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc193, 193 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc194, 194 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc195, 195 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc196, 196 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc197, 197 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc198, 198 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc199, 199 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc200, 200 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc201, 201 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc202, 202 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc203, 203 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc204, 204 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc205, 205 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc206, 206 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc207, 207 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc208, 208 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc209, 209 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc210, 210 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc211, 211 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc212, 212 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc213, 213 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc214, 214 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc215, 215 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc216, 216 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc217, 217 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc218, 218 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc219, 219 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc220, 220 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc221, 221 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc222, 222 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc223, 223 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc224, 224 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc225, 225 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc226, 226 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc227, 227 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc228, 228 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc229, 229 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc230, 230 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc231, 231 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc232, 232 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc233, 233 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc234, 234 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc235, 235 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc236, 236 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc237, 237 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc238, 238 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc239, 239 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc240, 240 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc241, 241 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc242, 242 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc243, 243 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc244, 244 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc245, 245 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc246, 246 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc247, 247 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc248, 248 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc249, 249 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc250, 250 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc251, 251 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc252, 252 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc253, 253 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc254, 254 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + DEF_REGISTER( acc255, 255 | BITS_32 | ACC_VGPR |Arch_amdgpu_gfx940, "amdgpu_gfx940"); + +}} + +#endif diff --git a/common/h/registers/MachRegister.h b/common/h/registers/MachRegister.h new file mode 100644 index 0000000000..cb65cb0efa --- /dev/null +++ b/common/h/registers/MachRegister.h @@ -0,0 +1,93 @@ +/* + * See the dyninst/COPYRIGHT file for copyright information. + * + * We provide the Paradyn Tools (below described as "Paradyn") + * on an AS IS basis, and do not warrant its validity or performance. + * We reserve the right to update, modify, or discontinue this + * software at any time. We shall have no obligation to supply such + * updates or modifications or any other form of support to you. + * + * By your use of Paradyn, you understand and agree that we (or any + * other person or entity with proprietary rights in Paradyn) are + * under no obligation to provide either maintenance services, + * update services, notices of latent defects, or correction of + * defects for Paradyn. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef DYNINST_MACHREGISTER_h +#define DYNINST_MACHREGISTER_h + +#include "Architecture.h" +#include "util.h" + +#include + +namespace Dyninst { + typedef unsigned long MachRegisterVal; + + class COMMON_EXPORT MachRegister { + private: + signed int reg; + + public: + MachRegister(); + explicit MachRegister(signed int r); + explicit MachRegister(signed int r, std::string n); + + MachRegister getBaseRegister() const; + Architecture getArchitecture() const; + bool isValid() const; + + std::string const& name() const; + unsigned int size() const; + bool operator<(const MachRegister& a) const; + bool operator==(const MachRegister& a) const; + operator signed int() const; + signed int val() const; + + // Return the category of the MachRegister + unsigned int regClass() const; + + static MachRegister getPC(Dyninst::Architecture arch); + static MachRegister getReturnAddress(Dyninst::Architecture arch); + static MachRegister getFramePointer(Dyninst::Architecture arch); + static MachRegister getStackPointer(Dyninst::Architecture arch); + static MachRegister getSyscallNumberReg(Dyninst::Architecture arch); + static MachRegister getSyscallNumberOReg(Dyninst::Architecture arch); + static MachRegister getSyscallReturnValueReg(Dyninst::Architecture arch); + static MachRegister getZeroFlag(Dyninst::Architecture arch); + + bool isPC() const; + bool isFramePointer() const; + bool isStackPointer() const; + bool isSyscallNumberReg() const; + bool isSyscallReturnValueReg() const; + bool isFlag() const; + bool isZeroFlag() const; + + void getROSERegister(int& c, int& n, int& p); + + static MachRegister DwarfEncToReg(int encoding, Dyninst::Architecture arch); + static MachRegister getArchRegFromAbstractReg(MachRegister abstract, + Dyninst::Architecture arch); + int getDwarfEnc() const; + + static MachRegister getArchReg(unsigned int regNum, Dyninst::Architecture arch); + }; +} + +#endif diff --git a/common/h/registers/aarch64_regs.h b/common/h/registers/aarch64_regs.h new file mode 100644 index 0000000000..61274c7010 --- /dev/null +++ b/common/h/registers/aarch64_regs.h @@ -0,0 +1,788 @@ +/* + * See the dyninst/COPYRIGHT file for copyright information. + * + * We provide the Paradyn Tools (below described as "Paradyn") + * on an AS IS basis, and do not warrant its validity or performance. + * We reserve the right to update, modify, or discontinue this + * software at any time. We shall have no obligation to supply such + * updates or modifications or any other form of support to you. + * + * By your use of Paradyn, you understand and agree that we (or any + * other person or entity with proprietary rights in Paradyn) are + * under no obligation to provide either maintenance services, + * update services, notices of latent defects, or correction of + * defects for Paradyn. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef DYNINST_AARCH64_REGS_H +#define DYNINST_AARCH64_REGS_H + +//clang-format: off + +#include "Architecture.h" +#include "registers/reg_def.h" + +namespace Dyninst { namespace aarch64 { + + /** + * For interpreting constants: + * Lowest 16 bits (0x000000ff) is base register ID + * Next 16 bits (0x0000ff00) is the aliasing and subrange ID- + * used on x86/x86_64 to distinguish between things like EAX and AH + * Next 16 bits (0x00ff0000) are the register category, GPR/FPR/MMX/... + * Top 16 bits (0xff000000) are the architecture. + * + * These values/layout are not guaranteed to remain the same as part of the + * public interface, and may change. + **/ + + // 0xff000000 0x00ff0000 0x0000ff00 0x000000ff + // arch reg cat:GPR alias&subrange reg ID + const signed int GPR = 0x00010000; + const signed int FPR = 0x00020000; + const signed int FLAG = 0x00030000; + const signed int FSR = 0x00040000; + const signed int SPR = 0x00080000; + const signed int SYSREG = 0x00100000; + + const signed int BIT = 0x00008000; + const signed int B_REG = 0x00000100; // 8bit byte reg + const signed int W_REG = 0x00000300; // 16bit half-wor reg + const signed int D_REG = 0x00000f00; // 32bit single-word reg + const signed int FULL = 0x00000000; // 64bit double-word reg + const signed int Q_REG = 0x00000400; // 128bit reg + const signed int HQ_REG = 0x00000500; // second 64bit in 128bit reg + + // 31 GPRs, double word long registers + // ( name, ID | alias | cat | arch, arch) + DEF_REGISTER( x0, 0 | FULL | GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( w0, 0 | D_REG | GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( x1, 1 | FULL | GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( w1, 1 | D_REG | GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( x2, 2 | FULL | GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( w2, 2 | D_REG | GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( x3, 3 | FULL | GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( w3, 3 | D_REG | GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( x4, 4 | FULL | GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( w4, 4 | D_REG | GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( x5, 5 | FULL | GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( w5, 5 | D_REG | GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( x6, 6 | FULL | GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( w6, 6 | D_REG | GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( x7, 7 | FULL | GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( w7, 7 | D_REG | GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( x8, 8 | FULL | GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( w8, 8 | D_REG | GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( x9, 9 | FULL | GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( w9, 9 | D_REG | GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( x10, 10 | FULL | GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( w10, 10 | D_REG | GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( x11, 11 | FULL | GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( w11, 11 | D_REG | GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( x12, 12 | FULL | GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( w12, 12 | D_REG | GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( x13, 13 | FULL | GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( w13, 13 | D_REG | GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( x14, 14 | FULL | GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( w14, 14 | D_REG | GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( x15, 15 | FULL | GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( w15, 15 | D_REG | GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( x16, 16 | FULL | GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( w16, 16 | D_REG | GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( x17, 17 | FULL | GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( w17, 17 | D_REG | GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( x18, 18 | FULL | GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( w18, 18 | D_REG | GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( x19, 19 | FULL | GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( w19, 19 | D_REG | GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( x20, 20 | FULL | GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( w20, 20 | D_REG | GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( x21, 21 | FULL | GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( w21, 21 | D_REG | GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( x22, 22 | FULL | GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( w22, 22 | D_REG | GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( x23, 23 | FULL | GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( w23, 23 | D_REG | GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( x24, 24 | FULL | GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( w24, 24 | D_REG | GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( x25, 25 | FULL | GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( w25, 25 | D_REG | GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( x26, 26 | FULL | GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( w26, 26 | D_REG | GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( x27, 27 | FULL | GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( w27, 27 | D_REG | GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( x28, 28 | FULL | GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( w28, 28 | D_REG | GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( x29, 29 | FULL | GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( w29, 29 | D_REG | GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( x30, 30 | FULL | GPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( w30, 30 | D_REG | GPR | Arch_aarch64, "aarch64"); + + // 32 FPRs-----------q-d-s-h-b + // 128 bit + DEF_REGISTER( q0, 0 | Q_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( q1, 1 | Q_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( q2, 2 | Q_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( q3, 3 | Q_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( q4, 4 | Q_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( q5, 5 | Q_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( q6, 6 | Q_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( q7, 7 | Q_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( q8, 8 | Q_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( q9, 9 | Q_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( q10, 10 | Q_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( q11, 11 | Q_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( q12, 12 | Q_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( q13, 13 | Q_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( q14, 14 | Q_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( q15, 15 | Q_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( q16, 16 | Q_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( q17, 17 | Q_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( q18, 18 | Q_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( q19, 19 | Q_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( q20, 20 | Q_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( q21, 21 | Q_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( q22, 22 | Q_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( q23, 23 | Q_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( q24, 24 | Q_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( q25, 25 | Q_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( q26, 26 | Q_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( q27, 27 | Q_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( q28, 28 | Q_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( q29, 29 | Q_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( q30, 30 | Q_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( q31, 31 | Q_REG | FPR | Arch_aarch64, "aarch64"); + + // second 64bit + DEF_REGISTER( hq0, 0 | HQ_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( hq1, 1 | HQ_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( hq2, 2 | HQ_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( hq3, 3 | HQ_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( hq4, 4 | HQ_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( hq5, 5 | HQ_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( hq6, 6 | HQ_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( hq7, 7 | HQ_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( hq8, 8 | HQ_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( hq9, 9 | HQ_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( hq10, 10 | HQ_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( hq11, 11 | HQ_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( hq12, 12 | HQ_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( hq13, 13 | HQ_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( hq14, 14 | HQ_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( hq15, 15 | HQ_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( hq16, 16 | HQ_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( hq17, 17 | HQ_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( hq18, 18 | HQ_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( hq19, 19 | HQ_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( hq20, 20 | HQ_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( hq21, 21 | HQ_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( hq22, 22 | HQ_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( hq23, 23 | HQ_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( hq24, 24 | HQ_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( hq25, 25 | HQ_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( hq26, 26 | HQ_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( hq27, 27 | HQ_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( hq28, 28 | HQ_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( hq29, 29 | HQ_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( hq30, 30 | HQ_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( hq31, 31 | HQ_REG | FPR | Arch_aarch64, "aarch64"); + + // 64bit FP regs + DEF_REGISTER( d0, 0 | FULL | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( d1, 1 | FULL | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( d2, 2 | FULL | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( d3, 3 | FULL | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( d4, 4 | FULL | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( d5, 5 | FULL | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( d6, 6 | FULL | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( d7, 7 | FULL | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( d8, 8 | FULL | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( d9, 9 | FULL | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( d10, 10 | FULL | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( d11, 11 | FULL | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( d12, 12 | FULL | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( d13, 13 | FULL | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( d14, 14 | FULL | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( d15, 15 | FULL | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( d16, 16 | FULL | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( d17, 17 | FULL | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( d18, 18 | FULL | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( d19, 19 | FULL | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( d20, 20 | FULL | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( d21, 21 | FULL | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( d22, 22 | FULL | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( d23, 23 | FULL | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( d24, 24 | FULL | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( d25, 25 | FULL | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( d26, 26 | FULL | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( d27, 27 | FULL | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( d28, 28 | FULL | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( d29, 29 | FULL | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( d30, 30 | FULL | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( d31, 31 | FULL | FPR | Arch_aarch64, "aarch64"); + + // 32 bit FP regs + DEF_REGISTER( s0, 0 | D_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( s1, 1 | D_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( s2, 2 | D_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( s3, 3 | D_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( s4, 4 | D_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( s5, 5 | D_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( s6, 6 | D_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( s7, 7 | D_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( s8, 8 | D_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( s9, 9 | D_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( s10, 10 | D_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( s11, 11 | D_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( s12, 12 | D_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( s13, 13 | D_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( s14, 14 | D_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( s15, 15 | D_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( s16, 16 | D_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( s17, 17 | D_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( s18, 18 | D_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( s19, 19 | D_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( s20, 20 | D_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( s21, 21 | D_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( s22, 22 | D_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( s23, 23 | D_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( s24, 24 | D_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( s25, 25 | D_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( s26, 26 | D_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( s27, 27 | D_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( s28, 28 | D_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( s29, 29 | D_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( s30, 30 | D_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( s31, 31 | D_REG | FPR | Arch_aarch64, "aarch64"); + + // 16 bit FP regs + DEF_REGISTER( h0, 0 | W_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( h1, 1 | W_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( h2, 2 | W_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( h3, 3 | W_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( h4, 4 | W_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( h5, 5 | W_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( h6, 6 | W_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( h7, 7 | W_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( h8, 8 | W_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( h9, 9 | W_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( h10, 10 | W_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( h11, 11 | W_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( h12, 12 | W_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( h13, 13 | W_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( h14, 14 | W_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( h15, 15 | W_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( h16, 16 | W_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( h17, 17 | W_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( h18, 18 | W_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( h19, 19 | W_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( h20, 20 | W_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( h21, 21 | W_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( h22, 22 | W_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( h23, 23 | W_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( h24, 24 | W_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( h25, 25 | W_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( h26, 26 | W_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( h27, 27 | W_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( h28, 28 | W_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( h29, 29 | W_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( h30, 30 | W_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( h31, 31 | W_REG | FPR | Arch_aarch64, "aarch64"); + + // 8 bit FP regs + DEF_REGISTER( b0, 0 | B_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( b1, 1 | B_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( b2, 2 | B_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( b3, 3 | B_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( b4, 4 | B_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( b5, 5 | B_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( b6, 6 | B_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( b7, 7 | B_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( b8, 8 | B_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( b9, 9 | B_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( b10, 10 | B_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( b11, 11 | B_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( b12, 12 | B_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( b13, 13 | B_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( b14, 14 | B_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( b15, 15 | B_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( b16, 16 | B_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( b17, 17 | B_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( b18, 18 | B_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( b19, 19 | B_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( b20, 20 | B_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( b21, 21 | B_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( b22, 22 | B_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( b23, 23 | B_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( b24, 24 | B_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( b25, 25 | B_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( b26, 26 | B_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( b27, 27 | B_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( b28, 28 | B_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( b29, 29 | B_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( b30, 30 | B_REG | FPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( b31, 31 | B_REG | FPR | Arch_aarch64, "aarch64"); + + DEF_REGISTER( tlbi_vale3is, 0 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( id_aa64pfr1_el1, 1 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( sder32_el3, 2 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( icc_ctlr_el3, 3 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dacr32_el2, 4 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( ich_vtr_el2, 5 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( icc_dir_el1, 6 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( tlbi_ipas2le1, 7 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( afsr0_el3, 9 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dczid_el0, 10 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( actlr_el1, 11 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( sctlr_el3, 12 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( sctlr_el2, 13 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( at_s1e2r, 14 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( ic_iallu, 15 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( icc_igrpen1_el3, 16 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmceid0_el0, 17 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( tpidr_el0, 18 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( tlbi_ipas2le1is, 19 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( contextidr_el1, 20 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( id_mmfr2_el1, 21 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmevtyper0_el0, 22 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmevtyper1_el0, 23 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmevtyper2_el0, 24 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmevtyper3_el0, 25 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmevtyper4_el0, 26 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmevtyper5_el0, 27 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmevtyper6_el0, 28 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmevtyper7_el0, 29 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmevtyper8_el0, 30 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmevtyper9_el0, 31 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmevtyper10_el0, 32 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmevtyper11_el0, 33 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmevtyper12_el0, 34 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmevtyper13_el0, 35 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmevtyper14_el0, 36 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmevtyper15_el0, 37 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmevtyper16_el0, 38 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmevtyper17_el0, 39 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmevtyper18_el0, 40 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmevtyper19_el0, 41 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmevtyper20_el0, 42 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmevtyper21_el0, 43 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmevtyper22_el0, 44 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmevtyper23_el0, 45 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmevtyper24_el0, 46 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmevtyper25_el0, 47 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmevtyper26_el0, 48 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmevtyper27_el0, 49 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmevtyper28_el0, 50 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmevtyper29_el0, 51 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmevtyper30_el0, 52 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( mair_el1, 53 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( tlbi_vale2is, 54 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( ccsidr_el1, 55 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( spsr_irq, 56 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( elr_el3, 57 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( tlbi_alle3is, 58 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( sp_el0, 59 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( id_mmfr1_el1, 60 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( ic_ivau, 61 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( icc_eoir0_el1, 62 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( icc_sgi0r_el1, 63 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( icc_sgi1r_el1, 64 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( tlbi_vae2, 65 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( cntp_ctl_el0, 66 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( tpidr_el1, 67 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dc_civac, 68 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( tlbi_ipas2e1is, 69 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( cntv_cval_el0, 70 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( icc_bpr0_el1, 71 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( mdccsr_el0, 72 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dbgclaimset_el1, 73 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( ich_ap0r0_el2, 74 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( ich_ap0r1_el2, 75 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( ich_ap0r2_el2, 76 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( ich_ap0r3_el2, 77 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dc_ivac, 78 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( ich_elrsr_el2, 79 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( ich_hcr_el2, 80 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( vbar_el2, 81 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( icc_asgi1r_el1, 82 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( id_aa64afr1_el1, 83 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( nzcv, 84 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( ttbr0_el1, 85 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( actlr_el3, 86 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( mdrar_el1, 87 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( rmr_el3, 88 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( cntkctl_el1, 89 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( rvbar_el3, 90 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( id_dfr0_el1, 91 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( at_s1e1r, 92 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( icc_ap1r0_el1, 93 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( icc_ap1r1_el1, 94 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( icc_ap1r2_el1, 95 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( icc_ap1r3_el1, 96 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( icc_pmr_el1, 97 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmceid1_el0, 98 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dc_csw, 99 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( id_pfr1_el1, 100 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( id_afr0_el1, 101 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( amair_el2, 102 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmovsset_el0, 103 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( tlbi_vmalle1, 104 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( tlbi_vale2, 105 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( at_s12e0w, 106 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( id_isar5_el1, 107 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( tcr_el1, 108 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmevcntr0_el0, 109 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmevcntr1_el0, 110 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmevcntr2_el0, 111 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmevcntr3_el0, 112 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmevcntr4_el0, 113 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmevcntr5_el0, 114 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmevcntr6_el0, 115 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmevcntr7_el0, 116 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmevcntr8_el0, 117 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmevcntr9_el0, 118 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmevcntr10_el0, 119 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmevcntr11_el0, 120 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmevcntr12_el0, 121 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmevcntr13_el0, 122 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmevcntr14_el0, 123 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmevcntr15_el0, 124 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmevcntr16_el0, 125 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmevcntr17_el0, 126 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmevcntr18_el0, 127 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmevcntr19_el0, 128 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmevcntr20_el0, 129 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmevcntr21_el0, 130 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmevcntr22_el0, 131 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmevcntr23_el0, 132 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmevcntr24_el0, 133 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmevcntr25_el0, 134 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmevcntr26_el0, 135 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmevcntr27_el0, 136 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmevcntr28_el0, 137 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmevcntr29_el0, 138 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmevcntr30_el0, 139 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dbgdtr_el0, 140 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( amair_el3, 141 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( rvbar_el1, 142 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dc_cvau, 143 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( afsr0_el2, 144 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( icc_iar0_el1, 145 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( icc_bpr1_el1, 146 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dc_cisw, 147 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( hpfar_el2, 148 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( spsr_abt, 149 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( csselr_el1, 150 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmintenclr_el1, 151 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( tlbi_vaae1, 152 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( far_el2, 153 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( currentel, 154 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dbgprcr_el1, 155 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( tlbi_ipas2e1, 156 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( mair_el3, 157 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( ttbr1_el1, 158 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( cntvct_el0, 159 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( tlbi_aside1is, 160 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( scr_el3, 161 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( mvfr0_el1, 162 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( tlbi_alle1, 163 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmovsclr_el0, 164 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( mvfr1_el1, 165 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( tlbi_vaale1, 166 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( elr_el1, 167 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( rvbar_el2, 168 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( esr_el1, 169 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( tlbi_aside1, 170 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( osdtrrx_el1, 171 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmcntenset_el0, 172 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dspsr_el0, 173 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dc_zva, 174 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( ich_misr_el2, 175 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( vbar_el1, 176 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( id_isar1_el1, 177 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( cpacr_el1, 178 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( par_el1, 179 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( cnthp_ctl_el2, 180 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( actlr_el2, 181 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( spsr_fiq, 182 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( id_aa64pfr0_el1, 183 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( tpidr_el3, 184 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( at_s1e2w, 185 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( tlbi_alle2, 186 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( id_isar4_el1, 187 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dbgvcr32_el2, 188 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( hcr_el2, 189 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( ich_eisr_el2, 190 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( mdccint_el1, 191 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dlr_el0, 192 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( tpidr_el2, 193 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmuserenr_el0, 194 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( oseccr_el1, 195 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( tlbi_vmalls12e1is, 196 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( mdscr_el1, 197 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( ich_vmcr_el2, 198 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( far_el3, 199 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( spsr_el2, 200 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( oslsr_el1, 201 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( tlbi_vae1, 202 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( daif, 203 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( far_el1, 204 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( hstr_el2, 205 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( clidr_el1, 206 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( vttbr_el2, 207 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( id_aa64afr0_el1, 208 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( icc_rpr_el1, 209 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( cntps_ctl_el1, 210 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( afsr1_el1, 211 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( spsel, 212 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmcr_el0, 214 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( tlbi_vaae1is, 215 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( icc_sre_el1, 216 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( cntpct_el0, 217 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( tlbi_alle2is, 218 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( icc_igrpen1_el1, 219 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( ifsr32_el2, 220 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( icc_igrpen0_el1, 221 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( tpidrro_el0, 222 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( hacr_el2, 223 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( at_s1e0w, 224 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmccfiltr_el0, 225 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( cnthp_tval_el2, 226 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( at_s12e0r, 227 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( cntvoff_el2, 228 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( icc_sre_el2, 229 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( spsr_el1, 230 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( isr_el1, 231 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( cnthctl_el2, 232 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( vtcr_el2, 233 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( vmpidr_el2, 234 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmswinc_el0, 235 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( id_mmfr0_el1, 236 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( cntp_cval_el0, 237 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( icc_hppir0_el1, 238 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( mdcr_el3, 239 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dbgwvr0_el1, 240 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dbgwvr1_el1, 241 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dbgwvr2_el1, 242 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dbgwvr3_el1, 243 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dbgwvr4_el1, 244 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dbgwvr5_el1, 245 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dbgwvr6_el1, 246 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dbgwvr7_el1, 247 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dbgwvr8_el1, 248 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dbgwvr9_el1, 249 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dbgwvr10_el1, 250 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dbgwvr11_el1, 251 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dbgwvr12_el1, 252 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dbgwvr13_el1, 253 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dbgwvr14_el1, 254 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dbgwvr15_el1, 255 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dbgauthstatus_el1, 256 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dbgdtrtx_el0, 257 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( icc_eoir1_el1, 258 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( elr_el2, 259 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dbgbvr0_el1, 260 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dbgbvr1_el1, 261 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dbgbvr2_el1, 262 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dbgbvr3_el1, 263 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dbgbvr4_el1, 264 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dbgbvr5_el1, 265 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dbgbvr6_el1, 266 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dbgbvr7_el1, 267 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dbgbvr8_el1, 268 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dbgbvr9_el1, 269 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dbgbvr10_el1, 270 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dbgbvr11_el1, 271 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dbgbvr12_el1, 272 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dbgbvr13_el1, 273 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dbgbvr14_el1, 274 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dbgbvr15_el1, 275 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( ic_ialluis, 276 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( tcr_el3, 277 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( aidr_el1, 278 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( cntfrq_el0, 279 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( tlbi_vae3, 280 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( tlbi_vmalls12e1, 281 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( esr_el2, 282 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( vbar_el3, 283 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dbgwcr0_el1, 284 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dbgwcr1_el1, 285 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dbgwcr2_el1, 286 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dbgwcr3_el1, 287 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dbgwcr4_el1, 288 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dbgwcr5_el1, 289 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dbgwcr6_el1, 290 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dbgwcr7_el1, 291 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dbgwcr8_el1, 292 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dbgwcr9_el1, 293 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dbgwcr10_el1, 294 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dbgwcr11_el1, 295 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dbgwcr12_el1, 296 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dbgwcr13_el1, 297 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dbgwcr14_el1, 298 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dbgwcr15_el1, 299 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( rmr_el1, 300 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( midr_el1, 301 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dc_isw, 302 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( id_isar0_el1, 303 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( ctr_el0, 304 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( sp_el1, 305 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( cntv_tval_el0, 306 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( tlbi_vae3is, 307 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( afsr1_el3, 308 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( id_mmfr4_el1, 309 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( ttbr0_el3, 310 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( spsr_und, 311 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( tlbi_vae2is, 312 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( at_s1e3w, 313 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( osdlr_el1, 314 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( ich_lr0_el2, 315 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( ich_lr1_el2, 316 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( ich_lr2_el2, 317 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( ich_lr3_el2, 318 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( ich_lr4_el2, 319 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( ich_lr5_el2, 320 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( ich_lr6_el2, 321 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( ich_lr7_el2, 322 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( ich_lr8_el2, 323 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( ich_lr9_el2, 324 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( ich_lr10_el2, 325 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( ich_lr11_el2, 326 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( ich_lr12_el2, 327 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( ich_lr13_el2, 328 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( ich_lr14_el2, 329 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( ich_lr15_el2, 330 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dbgclaimclr_el1, 331 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( tlbi_vmalle1is, 332 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( id_aa64mmfr1_el1, 333 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmccntr_el0, 334 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( esr_el3, 335 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( cptr_el3, 336 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( cntp_tval_el0, 337 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( tcr_el2, 338 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dc_cvac, 339 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( tlbi_vaale1is, 340 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmintenset_el1, 341 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dbgbcr0_el1, 342 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dbgbcr1_el1, 343 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dbgbcr2_el1, 344 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dbgbcr3_el1, 345 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dbgbcr4_el1, 346 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dbgbcr5_el1, 347 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dbgbcr6_el1, 348 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dbgbcr7_el1, 349 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dbgbcr8_el1, 350 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dbgbcr9_el1, 351 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dbgbcr10_el1, 352 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dbgbcr11_el1, 353 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dbgbcr12_el1, 354 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dbgbcr13_el1, 355 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dbgbcr14_el1, 356 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dbgbcr15_el1, 357 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmselr_el0, 358 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( tlbi_alle1is, 359 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( icc_hppir1_el1, 360 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( tlbi_vae1is, 361 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( mdcr_el2, 362 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( at_s12e1w, 363 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( vpidr_el2, 364 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( id_aa64dfr0_el1, 365 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( id_isar2_el1, 366 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( ttbr0_el2, 367 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( icc_ap0r0_el1, 368 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( icc_ap0r1_el1, 369 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( icc_ap0r2_el1, 370 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( icc_ap0r3_el1, 371 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( dbgdtrrx_el0, 372 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( fpexc32_el2, 373 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmxevtyper_el0, 374 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( oslar_el1, 375 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( id_pfr0_el1, 376 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( id_mmfr3_el1, 377 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( osdtrtx_el1, 378 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( id_aa64isar0_el1, 379 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( mvfr2_el1, 380 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmcntenclr_el0, 381 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( ich_ap1r0_el2, 382 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( ich_ap1r1_el2, 383 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( ich_ap1r2_el2, 384 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( ich_ap1r3_el2, 385 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( id_aa64mmfr0_el1, 386 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( tlbi_vale3, 387 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( revidr_el1, 388 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( mair_el2, 389 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( sctlr_el1, 390 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( at_s1e0r, 391 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( cptr_el2, 392 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( at_s12e1r, 393 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( pmxevcntr_el0, 394 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( afsr0_el1, 395 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( at_s1e1w, 396 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( id_isar3_el1, 397 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( afsr1_el2, 398 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( tlbi_vale1is, 399 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( sp_el2, 400 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( cntps_cval_el1, 401 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( cntps_tval_el1, 402 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( icc_ctlr_el1, 403 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( cntv_ctl_el0, 404 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( rmr_el2, 405 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( id_aa64dfr1_el1, 406 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( cnthp_cval_el2, 407 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( at_s1e3r, 408 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( id_aa64isar1_el1, 409 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( mpidr_el1, 410 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( amair_el1, 411 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( tlbi_alle3, 412 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( spsr_el3, 413 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( tlbi_vale1, 414 | FULL | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( icc_sre_el3, 415 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + DEF_REGISTER( icc_iar1_el1, 416 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + + DEF_REGISTER(IMPLEMENTATION_DEFINED_SYSREG, 417 | D_REG | SYSREG | Arch_aarch64, "aarch64"); + + // GPRs aliases: + // by convention + // x29 is used as frame pointer + // x30 is the linking register + // x31 can be sp or zero register depending on the context + + // special registers + // PC is not writable in aarch64 + const signed int N_FLAG = 31; + const signed int Z_FLAG = 30; + const signed int C_FLAG = 29; + const signed int V_FLAG = 28; + + DEF_REGISTER( sp, 31 | FULL | SPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( wsp, 0 | D_REG | SPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( pc, 32 | FULL | SPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( pstate, 2 | D_REG | SPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( xzr, 3 | FULL | SPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( n, N_FLAG | BIT | FLAG | Arch_aarch64, "aarch64"); + DEF_REGISTER( z, Z_FLAG | BIT | FLAG | Arch_aarch64, "aarch64"); + DEF_REGISTER( c, C_FLAG | BIT | FLAG | Arch_aarch64, "aarch64"); + DEF_REGISTER( v, V_FLAG | BIT | FLAG | Arch_aarch64, "aarch64"); + DEF_REGISTER( wzr, 3 | D_REG | SPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( fpcr, 4 | D_REG | SPR | Arch_aarch64, "aarch64"); + DEF_REGISTER( fpsr, 5 | D_REG | SPR | Arch_aarch64, "aarch64"); + +} // end of aarch64 namespace + +} + +#endif diff --git a/dyninstAPI/src/MemoryEmulator/memEmulatorStub.h b/common/h/registers/abstract_regs.h similarity index 56% rename from dyninstAPI/src/MemoryEmulator/memEmulatorStub.h rename to common/h/registers/abstract_regs.h index 242dc03c6d..1a1f71a2af 100644 --- a/dyninstAPI/src/MemoryEmulator/memEmulatorStub.h +++ b/common/h/registers/abstract_regs.h @@ -1,60 +1,65 @@ /* * See the dyninst/COPYRIGHT file for copyright information. - * + * * We provide the Paradyn Tools (below described as "Paradyn") * on an AS IS basis, and do not warrant its validity or performance. * We reserve the right to update, modify, or discontinue this * software at any time. We shall have no obligation to supply such * updates or modifications or any other form of support to you. - * + * * By your use of Paradyn, you understand and agree that we (or any * other person or entity with proprietary rights in Paradyn) are * under no obligation to provide either maintenance services, * update services, notices of latent defects, or correction of * defects for Paradyn. - * + * * This library is free software; you can redistribute it and/or * modify it under the terms of the GNU Lesser General Public * License as published by the Free Software Foundation; either * version 2.1 of the License, or (at your option) any later version. - * + * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU * Lesser General Public License for more details. - * + * * You should have received a copy of the GNU Lesser General Public * License along with this library; if not, write to the Free Software * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ -#if !defined(MEM_EMULATOR_STUB) -#define MEM_EMULATOR_STUB -#if defined(cap_mem_emulation) -#error -#endif +#ifndef DYNINST_ABSTRACT_REGS_H +#define DYNINST_ABSTRACT_REGS_H + +//clang-format: off -class mapped_object; +#include "Architecture.h" +#include "registers/reg_def.h" namespace Dyninst { -class MemoryEmulator { - public: - MemoryEmulator(AddressSpace *) {} - void addSpringboard(SymtabAPI::Region *, Address, int) {} - void removeSpringboards(func_instance*) {} - void removeSpringboards(const block_instance*) {} - void addAllocatedRegion(Address, unsigned) {} - void addRegion(mapped_object *) {} - void removeRegion(Address, unsigned) {} - void removeRegion(mapped_object *) {} - void update() {} - void synchShadowOrig(bool) {} - std::pair translate(Address) { return std::make_pair(false, 0); } - std::pair translateBackwards(Address) { return std::make_pair(false, 0); } - static const int STACK_SHIFT_VAL = 0; - void debug() {} - -}; + /** + * For interpreting constants: + * Lowest 16 bits (0x000000ff) is base register ID + * Next 16 bits (0x0000ff00) is the aliasing and subrange ID- + * used on x86/x86_64 to distinguish between things like EAX and AH + * Next 16 bits (0x00ff0000) are the register category, GPR/FPR/MMX/... + * Top 16 bits (0xff000000) are the architecture. + * + * These values/layout are not guaranteed to remain the same as part of the + * public interface, and may change. + **/ + + // Abstract registers used for stackwalking + + // ( name, ID | arch, arch) + DEF_REGISTER(InvalidReg, 0 | Arch_none, "abstract"); + DEF_REGISTER( FrameBase, 1 | Arch_none, "abstract"); + DEF_REGISTER(ReturnAddr, 2 | Arch_none, "abstract"); + DEF_REGISTER( StackTop, 3 | Arch_none, "abstract"); + + // DWARF-ism; the CFA is the value of the stack pointer in the previous frame + DEF_REGISTER( CFA, 4 | Arch_none, "abstract"); + } #endif diff --git a/common/h/registers/cuda_regs.h b/common/h/registers/cuda_regs.h new file mode 100644 index 0000000000..95df023032 --- /dev/null +++ b/common/h/registers/cuda_regs.h @@ -0,0 +1,425 @@ +/* + * See the dyninst/COPYRIGHT file for copyright information. + * + * We provide the Paradyn Tools (below described as "Paradyn") + * on an AS IS basis, and do not warrant its validity or performance. + * We reserve the right to update, modify, or discontinue this + * software at any time. We shall have no obligation to supply such + * updates or modifications or any other form of support to you. + * + * By your use of Paradyn, you understand and agree that we (or any + * other person or entity with proprietary rights in Paradyn) are + * under no obligation to provide either maintenance services, + * update services, notices of latent defects, or correction of + * defects for Paradyn. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef DYNINST_CUDA_REGS_H +#define DYNINST_CUDA_REGS_H + +//clang-format: off + +#include "Architecture.h" +#include "registers/reg_def.h" + +namespace Dyninst { namespace cuda { + + /** + * For interpreting constants: + * Lowest 16 bits (0x000000ff) is base register ID + * Next 16 bits (0x0000ff00) is the aliasing and subrange ID- + * used on x86/x86_64 to distinguish between things like EAX and AH + * Next 16 bits (0x00ff0000) are the register category, GPR/FPR/MMX/... + * Top 16 bits (0xff000000) are the architecture. + * + * These values/layout are not guaranteed to remain the same as part of the + * public interface, and may change. + **/ + + const signed int GPR = 0x00000000; + const signed int PR = 0x00010000; + const signed int BR = 0x00020000; + const signed int UR = 0x00040000; + const signed int UPR = 0x00080000; + + // General purpose registers + // ( name, ID | cat | arch, arch) + DEF_REGISTER( r0, 0 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r1, 1 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r2, 2 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r3, 3 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r4, 4 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r5, 5 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r6, 6 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r7, 7 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r8, 8 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r9, 9 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r10, 10 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r11, 11 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r12, 12 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r13, 13 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r14, 14 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r15, 15 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r16, 16 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r17, 17 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r18, 18 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r19, 19 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r20, 20 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r21, 21 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r22, 22 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r23, 23 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r24, 24 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r25, 25 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r26, 26 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r27, 27 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r28, 28 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r29, 29 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r30, 30 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r31, 31 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r32, 32 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r33, 33 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r34, 34 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r35, 35 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r36, 36 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r37, 37 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r38, 38 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r39, 39 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r40, 40 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r41, 41 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r42, 42 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r43, 43 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r44, 44 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r45, 45 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r46, 46 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r47, 47 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r48, 48 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r49, 49 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r50, 50 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r51, 51 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r52, 52 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r53, 53 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r54, 54 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r55, 55 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r56, 56 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r57, 57 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r58, 58 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r59, 59 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r60, 60 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r61, 61 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r62, 62 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r63, 63 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r64, 64 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r65, 65 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r66, 66 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r67, 67 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r68, 68 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r69, 69 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r70, 70 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r71, 71 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r72, 72 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r73, 73 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r74, 74 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r75, 75 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r76, 76 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r77, 77 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r78, 78 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r79, 79 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r80, 80 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r81, 81 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r82, 82 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r83, 83 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r84, 84 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r85, 85 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r86, 86 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r87, 87 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r88, 88 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r89, 89 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r90, 90 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r91, 91 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r92, 92 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r93, 93 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r94, 94 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r95, 95 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r96, 96 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r97, 97 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r98, 98 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r99, 99 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r100, 100 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r101, 101 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r102, 102 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r103, 103 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r104, 104 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r105, 105 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r106, 106 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r107, 107 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r108, 108 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r109, 109 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r110, 110 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r111, 111 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r112, 112 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r113, 113 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r114, 114 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r115, 115 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r116, 116 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r117, 117 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r118, 118 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r119, 119 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r120, 120 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r121, 121 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r122, 122 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r123, 123 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r124, 124 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r125, 125 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r126, 126 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r127, 127 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r128, 128 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r129, 129 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r130, 130 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r131, 131 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r132, 132 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r133, 133 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r134, 134 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r135, 135 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r136, 136 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r137, 137 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r138, 138 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r139, 139 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r140, 140 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r141, 141 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r142, 142 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r143, 143 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r144, 144 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r145, 145 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r146, 146 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r147, 147 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r148, 148 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r149, 149 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r150, 150 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r151, 151 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r152, 152 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r153, 153 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r154, 154 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r155, 155 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r156, 156 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r157, 157 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r158, 158 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r159, 159 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r160, 160 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r161, 161 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r162, 162 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r163, 163 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r164, 164 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r165, 165 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r166, 166 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r167, 167 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r168, 168 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r169, 169 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r170, 170 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r171, 171 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r172, 172 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r173, 173 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r174, 174 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r175, 175 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r176, 176 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r177, 177 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r178, 178 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r179, 179 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r180, 180 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r181, 181 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r182, 182 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r183, 183 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r184, 184 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r185, 185 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r186, 186 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r187, 187 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r188, 188 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r189, 189 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r190, 190 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r191, 191 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r192, 192 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r193, 193 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r194, 194 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r195, 195 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r196, 196 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r197, 197 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r198, 198 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r199, 199 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r200, 200 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r201, 201 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r202, 202 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r203, 203 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r204, 204 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r205, 205 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r206, 206 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r207, 207 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r208, 208 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r209, 209 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r210, 210 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r211, 211 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r212, 212 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r213, 213 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r214, 214 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r215, 215 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r216, 216 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r217, 217 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r218, 218 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r219, 219 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r220, 220 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r221, 221 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r222, 222 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r223, 223 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r224, 224 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r225, 225 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r226, 226 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r227, 227 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r228, 228 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r229, 229 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r230, 230 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r231, 231 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r232, 232 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r233, 233 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r234, 234 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r235, 235 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r236, 236 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r237, 237 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r238, 238 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r239, 239 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r240, 240 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r241, 241 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r242, 242 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r243, 243 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r244, 244 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r245, 245 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r246, 246 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r247, 247 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r248, 248 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r249, 249 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r250, 250 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r251, 251 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r252, 252 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r253, 253 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r254, 254 | GPR | Arch_cuda, "cuda"); + DEF_REGISTER( r255, 255 | GPR | Arch_cuda, "cuda"); + + // uniform registers + DEF_REGISTER( ur0, 0 | UR | Arch_cuda, "cuda"); + DEF_REGISTER( ur1, 1 | UR | Arch_cuda, "cuda"); + DEF_REGISTER( ur2, 2 | UR | Arch_cuda, "cuda"); + DEF_REGISTER( ur3, 3 | UR | Arch_cuda, "cuda"); + DEF_REGISTER( ur4, 4 | UR | Arch_cuda, "cuda"); + DEF_REGISTER( ur5, 5 | UR | Arch_cuda, "cuda"); + DEF_REGISTER( ur6, 6 | UR | Arch_cuda, "cuda"); + DEF_REGISTER( ur7, 7 | UR | Arch_cuda, "cuda"); + DEF_REGISTER( ur8, 8 | UR | Arch_cuda, "cuda"); + DEF_REGISTER( ur9, 9 | UR | Arch_cuda, "cuda"); + DEF_REGISTER( ur10, 10 | UR | Arch_cuda, "cuda"); + DEF_REGISTER( ur11, 11 | UR | Arch_cuda, "cuda"); + DEF_REGISTER( ur12, 12 | UR | Arch_cuda, "cuda"); + DEF_REGISTER( ur13, 13 | UR | Arch_cuda, "cuda"); + DEF_REGISTER( ur14, 14 | UR | Arch_cuda, "cuda"); + DEF_REGISTER( ur15, 15 | UR | Arch_cuda, "cuda"); + DEF_REGISTER( ur16, 16 | UR | Arch_cuda, "cuda"); + DEF_REGISTER( ur17, 17 | UR | Arch_cuda, "cuda"); + DEF_REGISTER( ur18, 18 | UR | Arch_cuda, "cuda"); + DEF_REGISTER( ur19, 19 | UR | Arch_cuda, "cuda"); + DEF_REGISTER( ur20, 20 | UR | Arch_cuda, "cuda"); + DEF_REGISTER( ur21, 21 | UR | Arch_cuda, "cuda"); + DEF_REGISTER( ur22, 22 | UR | Arch_cuda, "cuda"); + DEF_REGISTER( ur23, 23 | UR | Arch_cuda, "cuda"); + DEF_REGISTER( ur24, 24 | UR | Arch_cuda, "cuda"); + DEF_REGISTER( ur25, 25 | UR | Arch_cuda, "cuda"); + DEF_REGISTER( ur26, 26 | UR | Arch_cuda, "cuda"); + DEF_REGISTER( ur27, 27 | UR | Arch_cuda, "cuda"); + DEF_REGISTER( ur28, 28 | UR | Arch_cuda, "cuda"); + DEF_REGISTER( ur29, 29 | UR | Arch_cuda, "cuda"); + DEF_REGISTER( ur30, 30 | UR | Arch_cuda, "cuda"); + DEF_REGISTER( ur31, 31 | UR | Arch_cuda, "cuda"); + DEF_REGISTER( ur32, 32 | UR | Arch_cuda, "cuda"); + DEF_REGISTER( ur33, 33 | UR | Arch_cuda, "cuda"); + DEF_REGISTER( ur34, 34 | UR | Arch_cuda, "cuda"); + DEF_REGISTER( ur35, 35 | UR | Arch_cuda, "cuda"); + DEF_REGISTER( ur36, 36 | UR | Arch_cuda, "cuda"); + DEF_REGISTER( ur37, 37 | UR | Arch_cuda, "cuda"); + DEF_REGISTER( ur38, 38 | UR | Arch_cuda, "cuda"); + DEF_REGISTER( ur39, 39 | UR | Arch_cuda, "cuda"); + DEF_REGISTER( ur40, 40 | UR | Arch_cuda, "cuda"); + DEF_REGISTER( ur41, 41 | UR | Arch_cuda, "cuda"); + DEF_REGISTER( ur42, 42 | UR | Arch_cuda, "cuda"); + DEF_REGISTER( ur43, 43 | UR | Arch_cuda, "cuda"); + DEF_REGISTER( ur44, 44 | UR | Arch_cuda, "cuda"); + DEF_REGISTER( ur45, 45 | UR | Arch_cuda, "cuda"); + DEF_REGISTER( ur46, 46 | UR | Arch_cuda, "cuda"); + DEF_REGISTER( ur47, 47 | UR | Arch_cuda, "cuda"); + DEF_REGISTER( ur48, 48 | UR | Arch_cuda, "cuda"); + DEF_REGISTER( ur49, 49 | UR | Arch_cuda, "cuda"); + DEF_REGISTER( ur50, 50 | UR | Arch_cuda, "cuda"); + DEF_REGISTER( ur51, 51 | UR | Arch_cuda, "cuda"); + DEF_REGISTER( ur52, 52 | UR | Arch_cuda, "cuda"); + DEF_REGISTER( ur53, 53 | UR | Arch_cuda, "cuda"); + DEF_REGISTER( ur54, 54 | UR | Arch_cuda, "cuda"); + DEF_REGISTER( ur55, 55 | UR | Arch_cuda, "cuda"); + DEF_REGISTER( ur56, 56 | UR | Arch_cuda, "cuda"); + DEF_REGISTER( ur57, 57 | UR | Arch_cuda, "cuda"); + DEF_REGISTER( ur58, 58 | UR | Arch_cuda, "cuda"); + DEF_REGISTER( ur59, 59 | UR | Arch_cuda, "cuda"); + DEF_REGISTER( ur60, 60 | UR | Arch_cuda, "cuda"); + DEF_REGISTER( ur61, 61 | UR | Arch_cuda, "cuda"); + DEF_REGISTER( ur62, 62 | UR | Arch_cuda, "cuda"); + DEF_REGISTER( ur63, 63 | UR | Arch_cuda, "cuda"); + + // Placeholder for a pc register, so that we don't assert + DEF_REGISTER( pc, 256 | GPR | Arch_cuda, "cuda"); + + // Predicate registers used as source or dest operands + // Different from a predicate register used as instruction predicate, + // which is handle by operand::isTruePredicate and operand::isFalsePredicate + DEF_REGISTER( p0, 0 | PR | Arch_cuda, "cuda"); + DEF_REGISTER( p1, 1 | PR | Arch_cuda, "cuda"); + DEF_REGISTER( p2, 2 | PR | Arch_cuda, "cuda"); + DEF_REGISTER( p3, 3 | PR | Arch_cuda, "cuda"); + DEF_REGISTER( p4, 4 | PR | Arch_cuda, "cuda"); + DEF_REGISTER( p5, 5 | PR | Arch_cuda, "cuda"); + DEF_REGISTER( p6, 6 | PR | Arch_cuda, "cuda"); + + DEF_REGISTER( b1, 1 | BR | Arch_cuda, "cuda"); + DEF_REGISTER( b2, 2 | BR | Arch_cuda, "cuda"); + DEF_REGISTER( b3, 3 | BR | Arch_cuda, "cuda"); + DEF_REGISTER( b4, 4 | BR | Arch_cuda, "cuda"); + DEF_REGISTER( b5, 5 | BR | Arch_cuda, "cuda"); + DEF_REGISTER( b6, 6 | BR | Arch_cuda, "cuda"); + + // XXX(Keren): not sure how many uprs, use 16 for safety + DEF_REGISTER( up0, 0 | UPR | Arch_cuda, "cuda"); + DEF_REGISTER( up1, 1 | UPR | Arch_cuda, "cuda"); + DEF_REGISTER( up2, 2 | UPR | Arch_cuda, "cuda"); + DEF_REGISTER( up3, 3 | UPR | Arch_cuda, "cuda"); + DEF_REGISTER( up4, 4 | UPR | Arch_cuda, "cuda"); + DEF_REGISTER( up5, 5 | UPR | Arch_cuda, "cuda"); + DEF_REGISTER( up6, 6 | UPR | Arch_cuda, "cuda"); + DEF_REGISTER( up7, 7 | UPR | Arch_cuda, "cuda"); + DEF_REGISTER( up8, 8 | UPR | Arch_cuda, "cuda"); + DEF_REGISTER( up9, 9 | UPR | Arch_cuda, "cuda"); + DEF_REGISTER( up10, 10 | UPR | Arch_cuda, "cuda"); + DEF_REGISTER( up11, 11 | UPR | Arch_cuda, "cuda"); + DEF_REGISTER( up12, 12 | UPR | Arch_cuda, "cuda"); + DEF_REGISTER( up13, 13 | UPR | Arch_cuda, "cuda"); + DEF_REGISTER( up14, 14 | UPR | Arch_cuda, "cuda"); + DEF_REGISTER( up15, 15 | UPR | Arch_cuda, "cuda"); + +}} + +#endif diff --git a/common/h/registers/ppc32_regs.h b/common/h/registers/ppc32_regs.h new file mode 100644 index 0000000000..19f57e8698 --- /dev/null +++ b/common/h/registers/ppc32_regs.h @@ -0,0 +1,289 @@ +/* + * See the dyninst/COPYRIGHT file for copyright information. + * + * We provide the Paradyn Tools (below described as "Paradyn") + * on an AS IS basis, and do not warrant its validity or performance. + * We reserve the right to update, modify, or discontinue this + * software at any time. We shall have no obligation to supply such + * updates or modifications or any other form of support to you. + * + * By your use of Paradyn, you understand and agree that we (or any + * other person or entity with proprietary rights in Paradyn) are + * under no obligation to provide either maintenance services, + * update services, notices of latent defects, or correction of + * defects for Paradyn. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef DYNINST_PPC32_REGS_H +#define DYNINST_PPC32_REGS_H + +//clang-format: off + +#include "Architecture.h" +#include "registers/reg_def.h" + +namespace Dyninst { namespace ppc32 { + /** + * For interpreting constants: + * Lowest 16 bits (0x000000ff) is base register ID + * Next 16 bits (0x0000ff00) is the aliasing and subrange ID- + * used on x86/x86_64 to distinguish between things like EAX and AH + * Next 16 bits (0x00ff0000) are the register category, GPR/FPR/MMX/... + * Top 16 bits (0xff000000) are the architecture. + * + * These values/layout are not guaranteed to remain the same as part of the + * public interface, and may change. + **/ + + const signed int GPR = 0x00010000; + const signed int FPR = 0x00020000; + const signed int FSR = 0x00040000; + const signed int SPR = 0x00080000; + + // ( name, ID | cat | arch, arch ) + DEF_REGISTER( r0, 0 | GPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( r1, 1 | GPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( r2, 2 | GPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( r3, 3 | GPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( r4, 4 | GPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( r5, 5 | GPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( r6, 6 | GPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( r7, 7 | GPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( r8, 8 | GPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( r9, 9 | GPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( r10, 10 | GPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( r11, 11 | GPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( r12, 12 | GPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( r13, 13 | GPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( r14, 14 | GPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( r15, 15 | GPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( r16, 16 | GPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( r17, 17 | GPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( r18, 18 | GPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( r19, 19 | GPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( r20, 20 | GPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( r21, 21 | GPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( r22, 22 | GPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( r23, 23 | GPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( r24, 24 | GPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( r25, 25 | GPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( r26, 26 | GPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( r27, 27 | GPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( r28, 28 | GPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( r29, 29 | GPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( r30, 30 | GPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( r31, 31 | GPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( fpr0, 0 | FPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( fpr1, 1 | FPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( fpr2, 2 | FPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( fpr3, 3 | FPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( fpr4, 4 | FPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( fpr5, 5 | FPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( fpr6, 6 | FPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( fpr7, 7 | FPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( fpr8, 8 | FPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( fpr9, 9 | FPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( fpr10, 10 | FPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( fpr11, 11 | FPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( fpr12, 12 | FPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( fpr13, 13 | FPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( fpr14, 14 | FPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( fpr15, 15 | FPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( fpr16, 16 | FPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( fpr17, 17 | FPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( fpr18, 18 | FPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( fpr19, 19 | FPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( fpr20, 20 | FPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( fpr21, 21 | FPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( fpr22, 22 | FPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( fpr23, 23 | FPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( fpr24, 24 | FPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( fpr25, 25 | FPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( fpr26, 26 | FPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( fpr27, 27 | FPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( fpr28, 28 | FPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( fpr29, 29 | FPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( fpr30, 30 | FPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( fpr31, 31 | FPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( fsr0, 0 | FSR | Arch_ppc32, "ppc32"); + DEF_REGISTER( fsr1, 1 | FSR | Arch_ppc32, "ppc32"); + DEF_REGISTER( fsr2, 2 | FSR | Arch_ppc32, "ppc32"); + DEF_REGISTER( fsr3, 3 | FSR | Arch_ppc32, "ppc32"); + DEF_REGISTER( fsr4, 4 | FSR | Arch_ppc32, "ppc32"); + DEF_REGISTER( fsr5, 5 | FSR | Arch_ppc32, "ppc32"); + DEF_REGISTER( fsr6, 6 | FSR | Arch_ppc32, "ppc32"); + DEF_REGISTER( fsr7, 7 | FSR | Arch_ppc32, "ppc32"); + DEF_REGISTER( fsr8, 8 | FSR | Arch_ppc32, "ppc32"); + DEF_REGISTER( fsr9, 9 | FSR | Arch_ppc32, "ppc32"); + DEF_REGISTER( fsr10, 10 | FSR | Arch_ppc32, "ppc32"); + DEF_REGISTER( fsr11, 11 | FSR | Arch_ppc32, "ppc32"); + DEF_REGISTER( fsr12, 12 | FSR | Arch_ppc32, "ppc32"); + DEF_REGISTER( fsr13, 13 | FSR | Arch_ppc32, "ppc32"); + DEF_REGISTER( fsr14, 14 | FSR | Arch_ppc32, "ppc32"); + DEF_REGISTER( fsr15, 15 | FSR | Arch_ppc32, "ppc32"); + DEF_REGISTER( fsr16, 16 | FSR | Arch_ppc32, "ppc32"); + DEF_REGISTER( fsr17, 17 | FSR | Arch_ppc32, "ppc32"); + DEF_REGISTER( fsr18, 18 | FSR | Arch_ppc32, "ppc32"); + DEF_REGISTER( fsr19, 19 | FSR | Arch_ppc32, "ppc32"); + DEF_REGISTER( fsr20, 20 | FSR | Arch_ppc32, "ppc32"); + DEF_REGISTER( fsr21, 21 | FSR | Arch_ppc32, "ppc32"); + DEF_REGISTER( fsr22, 22 | FSR | Arch_ppc32, "ppc32"); + DEF_REGISTER( fsr23, 23 | FSR | Arch_ppc32, "ppc32"); + DEF_REGISTER( fsr24, 24 | FSR | Arch_ppc32, "ppc32"); + DEF_REGISTER( fsr25, 25 | FSR | Arch_ppc32, "ppc32"); + DEF_REGISTER( fsr26, 26 | FSR | Arch_ppc32, "ppc32"); + DEF_REGISTER( fsr27, 27 | FSR | Arch_ppc32, "ppc32"); + DEF_REGISTER( fsr28, 28 | FSR | Arch_ppc32, "ppc32"); + DEF_REGISTER( fsr29, 29 | FSR | Arch_ppc32, "ppc32"); + DEF_REGISTER( fsr30, 30 | FSR | Arch_ppc32, "ppc32"); + DEF_REGISTER( fsr31, 31 | FSR | Arch_ppc32, "ppc32"); + DEF_REGISTER( mq, 0 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( xer, 1 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( lr, 8 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( ctr, 9 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( amr, 13 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( dscr, 17 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( dsisr, 18 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( dar, 19 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( dec, 22 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( sdr1, 25 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( srr0, 26 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( srr1, 27 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( cfar, 28 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( amr_pri, 29 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( pid, 48 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( gdecar, 53 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( decar, 54 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( mcivpr, 55 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( lper, 56 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( lperu, 57 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( csrr0, 58 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( csrr1, 59 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( gtsrwr, 60 | SPR | Arch_ppc32, "ppc32"); + //DEF_REGISTER( iamr, 61 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( esr, 62 | SPR | Arch_ppc32, "ppc32"); + //DEF_REGISTER( ivpr, 66 | SPR | Arch_ppc32, "ppc32"); + + DEF_REGISTER( vrsave, 256 | SPR | Arch_ppc32, "ppc32"); + + DEF_REGISTER( sprg0, 272 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( sprg1, 273 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( sprg2, 274 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( sprg3, 275 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( sprg4, 276 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( sprg5, 277 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( sprg6, 278 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( sprg7, 279 | SPR | Arch_ppc32, "ppc32"); + + DEF_REGISTER( sprg3_ro, 259 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( sprg4_ro, 260 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( sprg5_ro, 261 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( sprg6_ro, 262 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( sprg7_ro, 263 | SPR | Arch_ppc32, "ppc32"); + + DEF_REGISTER( ear, 282 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( tbl_wo, 284 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( tbl_ro, 268 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( tbu_wo, 285 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( tbu_ro, 269 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( pvr, 287 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( ibat0u, 528 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( ibat0l, 529 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( ibat1u, 530 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( ibat1l, 531 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( ibat2u, 532 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( ibat2l, 533 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( ibat3u, 534 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( ibat3l, 535 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( dbat0u, 536 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( dbat0l, 537 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( dbat1u, 538 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( dbat1l, 539 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( dbat2u, 540 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( dbat2l, 541 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( dbat3u, 542 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( dbat3l, 543 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( pc, 600 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( fpscw, 601 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( fpscw0, 602 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( fpscw1, 603 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( fpscw2, 604 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( fpscw3, 605 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( fpscw4, 606 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( fpscw5, 607 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( fpscw6, 608 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( fpscw7, 609 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( msr, 610 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( ivpr, 611 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( ivor8, 612 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( seg0, 613 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( seg1, 614 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( seg2, 615 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( seg3, 616 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( seg4, 617 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( seg5, 618 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( seg6, 619 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( seg7, 620 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( cr0, 621 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( cr1, 622 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( cr2, 623 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( cr3, 624 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( cr4, 625 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( cr5, 626 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( cr6, 627 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( cr7, 628 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( cr, 629 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( or3, 630 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( trap, 631 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( cr0l, 700 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( cr0g, 701 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( cr0e, 702 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( cr0s, 703 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( cr1l, 704 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( cr1g, 705 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( cr1e, 706 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( cr1s, 707 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( cr2l, 708 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( cr2g, 709 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( cr2e, 710 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( cr2s, 711 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( cr3l, 712 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( cr3g, 713 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( cr3e, 714 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( cr3s, 715 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( cr4l, 716 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( cr4g, 717 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( cr4e, 718 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( cr4s, 719 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( cr5l, 720 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( cr5g, 721 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( cr5e, 722 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( cr5s, 723 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( cr6l, 724 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( cr6g, 725 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( cr6e, 726 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( cr6s, 727 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( cr7l, 728 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( cr7g, 729 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( cr7e, 730 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( cr7s, 731 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( ppr, 896 | SPR | Arch_ppc32, "ppc32"); + DEF_REGISTER( ppr32, 898 | SPR | Arch_ppc32, "ppc32"); + +}} + +#endif diff --git a/common/h/registers/ppc64_regs.h b/common/h/registers/ppc64_regs.h new file mode 100644 index 0000000000..d867181329 --- /dev/null +++ b/common/h/registers/ppc64_regs.h @@ -0,0 +1,335 @@ +/* + * See the dyninst/COPYRIGHT file for copyright information. + * + * We provide the Paradyn Tools (below described as "Paradyn") + * on an AS IS basis, and do not warrant its validity or performance. + * We reserve the right to update, modify, or discontinue this + * software at any time. We shall have no obligation to supply such + * updates or modifications or any other form of support to you. + * + * By your use of Paradyn, you understand and agree that we (or any + * other person or entity with proprietary rights in Paradyn) are + * under no obligation to provide either maintenance services, + * update services, notices of latent defects, or correction of + * defects for Paradyn. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef DYNINST_PPC64_REGS_H +#define DYNINST_PPC64_REGS_H + +//clang-format: off + +#include "registers/reg_def.h" + +namespace Dyninst { namespace ppc64 { + /** + * For interpreting constants: + * Lowest 16 bits (0x000000ff) is base register ID + * Next 16 bits (0x0000ff00) is the aliasing and subrange ID- + * used on x86/x86_64 to distinguish between things like EAX and AH + * Next 16 bits (0x00ff0000) are the register category, GPR/FPR/MMX/... + * Top 16 bits (0xff000000) are the architecture. + * + * These values/layout are not guaranteed to remain the same as part of the + * public interface, and may change. + **/ + + const signed int GPR = 0x00010000; + const signed int FPR = 0x00020000; + const signed int FSR = 0x00040000; + const signed int SPR = 0x00080000; + const signed int VSR = 0x00000000; + + // ( name, ID | cat | arch, arch ) + DEF_REGISTER( r0, 0 | GPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( r1, 1 | GPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( r2, 2 | GPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( r3, 3 | GPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( r4, 4 | GPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( r5, 5 | GPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( r6, 6 | GPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( r7, 7 | GPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( r8, 8 | GPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( r9, 9 | GPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( r10, 10 | GPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( r11, 11 | GPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( r12, 12 | GPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( r13, 13 | GPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( r14, 14 | GPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( r15, 15 | GPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( r16, 16 | GPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( r17, 17 | GPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( r18, 18 | GPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( r19, 19 | GPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( r20, 20 | GPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( r21, 21 | GPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( r22, 22 | GPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( r23, 23 | GPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( r24, 24 | GPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( r25, 25 | GPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( r26, 26 | GPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( r27, 27 | GPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( r28, 28 | GPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( r29, 29 | GPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( r30, 30 | GPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( r31, 31 | GPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( fpr0, 0 | FPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( fpr1, 1 | FPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( fpr2, 2 | FPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( fpr3, 3 | FPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( fpr4, 4 | FPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( fpr5, 5 | FPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( fpr6, 6 | FPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( fpr7, 7 | FPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( fpr8, 8 | FPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( fpr9, 9 | FPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( fpr10, 10 | FPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( fpr11, 11 | FPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( fpr12, 12 | FPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( fpr13, 13 | FPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( fpr14, 14 | FPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( fpr15, 15 | FPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( fpr16, 16 | FPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( fpr17, 17 | FPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( fpr18, 18 | FPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( fpr19, 19 | FPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( fpr20, 20 | FPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( fpr21, 21 | FPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( fpr22, 22 | FPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( fpr23, 23 | FPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( fpr24, 24 | FPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( fpr25, 25 | FPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( fpr26, 26 | FPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( fpr27, 27 | FPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( fpr28, 28 | FPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( fpr29, 29 | FPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( fpr30, 30 | FPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( fpr31, 31 | FPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( fsr0, 0 | FSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( fsr1, 1 | FSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( fsr2, 2 | FSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( fsr3, 3 | FSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( fsr4, 4 | FSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( fsr5, 5 | FSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( fsr6, 6 | FSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( fsr7, 7 | FSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( fsr8, 8 | FSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( fsr9, 9 | FSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( fsr10, 10 | FSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( fsr11, 11 | FSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( fsr12, 12 | FSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( fsr13, 13 | FSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( fsr14, 14 | FSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( fsr15, 15 | FSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( fsr16, 16 | FSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( fsr17, 17 | FSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( fsr18, 18 | FSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( fsr19, 19 | FSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( fsr20, 20 | FSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( fsr21, 21 | FSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( fsr22, 22 | FSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( fsr23, 23 | FSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( fsr24, 24 | FSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( fsr25, 25 | FSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( fsr26, 26 | FSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( fsr27, 27 | FSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( fsr28, 28 | FSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( fsr29, 29 | FSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( fsr30, 30 | FSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( fsr31, 31 | FSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( mq, 0 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( xer, 1 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( lr, 8 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( ctr, 9 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( dsisr, 18 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( dar, 19 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( dec, 22 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( sdr1, 25 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( srr0, 26 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( srr1, 27 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( vrsave, 256 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( sprg0, 272 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( sprg1, 273 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( sprg2, 274 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( sprg3, 275 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( sprg4, 276 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( sprg5, 277 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( sprg6, 278 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( sprg7, 279 | SPR | Arch_ppc64, "ppc64"); + + DEF_REGISTER( sprg3_ro, 259 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( sprg4_ro, 260 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( sprg5_ro, 261 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( sprg6_ro, 262 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( sprg7_ro, 263 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( ear, 282 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( tbl_wo, 284 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( tbl_ro, 268 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( tbu_wo, 285 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( tbu_ro, 269 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( pvr, 287 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( ibat0u, 528 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( ibat0l, 529 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( ibat1u, 530 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( ibat1l, 531 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( ibat2u, 532 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( ibat2l, 533 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( ibat3u, 534 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( ibat3l, 535 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( dbat0u, 536 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( dbat0l, 537 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( dbat1u, 538 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( dbat1l, 539 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( dbat2u, 540 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( dbat2l, 541 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( dbat3u, 542 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( dbat3l, 543 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( pc, 600 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( fpscw, 601 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( fpscw0, 602 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( fpscw1, 603 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( fpscw2, 604 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( fpscw3, 605 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( fpscw4, 606 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( fpscw5, 607 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( fpscw6, 608 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( fpscw7, 609 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( msr, 610 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( ivpr, 611 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( ivor8, 612 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( seg0, 613 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( seg1, 614 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( seg2, 615 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( seg3, 616 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( seg4, 617 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( seg5, 618 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( seg6, 619 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( seg7, 620 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( cr0, 621 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( cr1, 622 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( cr2, 623 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( cr3, 624 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( cr4, 625 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( cr5, 626 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( cr6, 627 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( cr7, 628 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( cr, 629 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( or3, 630 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( trap, 631 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( cr0l, 700 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( cr0g, 701 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( cr0e, 702 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( cr0s, 703 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( cr1l, 704 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( cr1g, 705 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( cr1e, 706 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( cr1s, 707 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( cr2l, 708 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( cr2g, 709 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( cr2e, 710 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( cr2s, 711 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( cr3l, 712 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( cr3g, 713 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( cr3e, 714 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( cr3s, 715 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( cr4l, 716 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( cr4g, 717 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( cr4e, 718 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( cr4s, 719 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( cr5l, 720 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( cr5g, 721 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( cr5e, 722 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( cr5s, 723 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( cr6l, 724 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( cr6g, 725 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( cr6e, 726 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( cr6s, 727 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( cr7l, 728 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( cr7g, 729 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( cr7e, 730 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( cr7s, 731 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( ppr, 896 | SPR | Arch_ppc64, "ppc64"); + DEF_REGISTER( ppr32, 898 | SPR | Arch_ppc64, "ppc64"); + + DEF_REGISTER( vsr0, 0 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( vsr1, 1 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( vsr2, 2 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( vsr3, 3 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( vsr4, 4 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( vsr5, 5 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( vsr6, 6 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( vsr7, 7 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( vsr8, 8 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( vsr9, 9 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( vsr10, 10 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( vsr11, 11 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( vsr12, 12 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( vsr13, 13 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( vsr14, 14 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( vsr15, 15 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( vsr16, 16 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( vsr17, 17 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( vsr18, 18 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( vsr19, 19 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( vsr20, 20 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( vsr21, 21 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( vsr22, 22 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( vsr23, 23 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( vsr24, 24 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( vsr25, 25 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( vsr26, 26 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( vsr27, 27 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( vsr28, 28 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( vsr29, 29 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( vsr30, 30 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( vsr31, 31 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( vsr32, 32 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( vsr33, 33 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( vsr34, 34 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( vsr35, 35 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( vsr36, 36 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( vsr37, 37 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( vsr38, 38 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( vsr39, 39 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( vsr40, 40 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( vsr41, 41 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( vsr42, 42 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( vsr43, 43 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( vsr44, 44 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( vsr45, 45 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( vsr46, 46 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( vsr47, 47 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( vsr48, 48 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( vsr49, 49 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( vsr50, 50 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( vsr51, 51 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( vsr52, 52 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( vsr53, 53 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( vsr54, 54 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( vsr55, 55 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( vsr56, 56 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( vsr57, 57 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( vsr58, 58 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( vsr59, 59 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( vsr60, 60 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( vsr61, 61 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( vsr62, 62 | VSR | Arch_ppc64, "ppc64"); + DEF_REGISTER( vsr63, 63 | VSR | Arch_ppc64, "ppc64"); + +}} + +#endif diff --git a/dyninstAPI/src/MemoryEmulator/memEmulatorTransformer.h b/common/h/registers/reg_def.h similarity index 50% rename from dyninstAPI/src/MemoryEmulator/memEmulatorTransformer.h rename to common/h/registers/reg_def.h index 1e65f8ee94..60b0e27c60 100644 --- a/dyninstAPI/src/MemoryEmulator/memEmulatorTransformer.h +++ b/common/h/registers/reg_def.h @@ -1,87 +1,65 @@ /* * See the dyninst/COPYRIGHT file for copyright information. - * + * * We provide the Paradyn Tools (below described as "Paradyn") * on an AS IS basis, and do not warrant its validity or performance. * We reserve the right to update, modify, or discontinue this * software at any time. We shall have no obligation to supply such * updates or modifications or any other form of support to you. - * + * * By your use of Paradyn, you understand and agree that we (or any * other person or entity with proprietary rights in Paradyn) are * under no obligation to provide either maintenance services, * update services, notices of latent defects, or correction of * defects for Paradyn. - * + * * This library is free software; you can redistribute it and/or * modify it under the terms of the GNU Lesser General Public * License as published by the Free Software Foundation; either * version 2.1 of the License, or (at your option) any later version. - * + * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU * Lesser General Public License for more details. - * + * * You should have received a copy of the GNU Lesser General Public * License along with this library; if not, write to the Free Software * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ -#if !defined(cap_mem_emulation) -#error -#endif - -#if !defined(_R_T_EMULATE_MEMORY_H_) -#define _R_T_EMULATE_MEMORY_H_ - -#include "dyninstAPI/src/Relocation/Transformers/Transformer.h" -#include "dyninstAPI/src/Relocation/Transformers/Modification.h" -#include "dataflowAPI/h/Absloc.h" // MemEmulator analysis -#include "dataflowAPI/h/AbslocInterface.h" // And more of the same - -class func_instance; - -namespace Dyninst { -namespace Relocation { - -class InsnWidget; - -class MemEmulatorTransformer : public Transformer { - typedef boost::shared_ptr InsnWidgetPtr; - - public: - typedef std::map TranslatorMap; - - virtual bool process(RelocBlock *, RelocGraph *); - - MemEmulatorTransformer() : - aConverter(false, false) {}; +#ifndef DYNINST_REG_DEF_H +#define DYNINST_REG_DEF_H + +#include "registers/MachRegister.h" + +/** + * DEF_REGISTER will define its first parameter as the name of the object + * it's declaring, and 'i' as the integer value representing that object. + * As an example, the name of a register may be + * x86::EAX + * with that register having a value of + * x86::iEAX + * + * The value is mostly useful in the 'case' part switch statements. + **/ +#if defined(DYN_DEFINE_REGS) +// DYN_DEFINE_REGS Should only be defined in libcommon. +// We want one definition, which will be in libcommon, and declarations +// for everyone else. +// +// I wanted these to be const MachRegister objects, but that changes the +// linker scope. Instead they're non-const. Every accessor function is +// const anyways, so we'll just close our eyes and pretend they're declared +// const. +# define DEF_REGISTER(name, value, Arch) \ + const signed int i##name = (value); \ + COMMON_EXPORT MachRegister name(i##name, Arch "::" #name) +#else +# define DEF_REGISTER(name, value, Arch) \ + const signed int i##name = (value); \ + COMMON_EXPORT extern MachRegister name - virtual ~MemEmulatorTransformer() {}; - - private: - - WidgetPtr createReplacement(InsnWidgetPtr reloc, - func_instance *func, block_instance *); - - bool canRewriteMemInsn(InsnWidgetPtr reloc, - func_instance *func); - - bool isSensitive(InsnWidgetPtr reloc, - func_instance *func, - block_instance *block); - - void createTranslator(Register r); - - bool override(InsnWidgetPtr reloc); - - TranslatorMap translators_; - - AssignmentConverter aConverter; - -}; -}; -}; +#endif #endif diff --git a/common/h/registers/x86_64_regs.h b/common/h/registers/x86_64_regs.h new file mode 100644 index 0000000000..da2990a21b --- /dev/null +++ b/common/h/registers/x86_64_regs.h @@ -0,0 +1,431 @@ +/* + * See the dyninst/COPYRIGHT file for copyright information. + * + * We provide the Paradyn Tools (below described as "Paradyn") + * on an AS IS basis, and do not warrant its validity or performance. + * We reserve the right to update, modify, or discontinue this + * software at any time. We shall have no obligation to supply such + * updates or modifications or any other form of support to you. + * + * By your use of Paradyn, you understand and agree that we (or any + * other person or entity with proprietary rights in Paradyn) are + * under no obligation to provide either maintenance services, + * update services, notices of latent defects, or correction of + * defects for Paradyn. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef DYNINST_X86_64_REGS_H +#define DYNINST_X86_64_REGS_H + +//clang-format: off + +#include "Architecture.h" +#include "registers/reg_def.h" +#include "registers/x86_regs.h" + +namespace Dyninst { namespace x86_64 { + + /* Register lengths + * + * NOTE: + * + * MachRegister::getBaseRegister clears the bit field for size, so + * the full register size has to be represented as 0x0. + * + * The {L,H,W}_REG sizes represent the aliased portions of the GPR + * registers that are historically referred to by name (e.g., AL is + * the lower 8 bits of EAX). + */ + const signed int FULL = 0x00000000; // 64 bits + const signed int BIT = 0x00000100; // 1-bit EFLAGS + const signed int L_REG = 0x00000200; // 8-bit, first byte + const signed int H_REG = 0x00000300; // 8-bit, second byte + const signed int W_REG = 0x00000400; // 16-bit, first word + const signed int D_REG = 0x00000500; // 32 bit, first double word + const signed int FPDBL = 0x00000600; // 80-bit x87 FPU + const signed int MMS = 0x00000700; // 64-bit MMX and 3DNow! + const signed int XMMS = 0x00000800; // 128-bit SSE, FC16, XOP, AVX, and FMA3/4 + const signed int YMMS = 0x00000900; // 256-bit SSE, AVX2, FMA3/4 + const signed int ZMMS = 0x00000A00; // 512-bit AVX-512/AVX10 + const signed int KMSKS = 0x00000B00; // 64-bit mask from AVX-512/AVX10 + + /* Register Categories */ + const signed int GPR = 0x00010000; // General-Purpose Registers + const signed int SEG = 0x00020000; // Segment Registers + const signed int FLAG = 0x00030000; // RFLAGS Register + const signed int MISC = 0x00040000; // Internal ProcControlAPI Register + const signed int CTL = 0x00050000; // Control Registers CR0-CR7 + const signed int DBG = 0x00060000; // Debug Registers DR0-DR7 + const signed int TST = 0x00070000; // Internal InstructionAPI Registers + const signed int X87 = 0x00080000; // x87 FPU Registers + const signed int MMX = 0x00090000; // MM0-MM7 Registers + const signed int XMM = 0x000A0000; // XMM0-XMM15 Registers from SSE (XMM0-XMM31 for AVX-512) + const signed int YMM = 0x000B0000; // YMM0-YMM15 Registers from AVX2/FMA (YMM0-YMM31 for AVX-512) + const signed int ZMM = 0x000C0000; // ZMM0-ZMM31 Registers from AVX-512 + const signed int KMASK = 0x000D0000; // K0-K7 opmask Registers from AVX-512 + const signed int FPCTL = 0x000E0000; // control/status Registers from x87, SSE, and AVX + + /* Base IDs for aliased GPRs */ + const signed int FLAGS = 0x00; // RFLAGS Register + const signed int BASEA = 0x00; + const signed int BASEC = 0x01; + const signed int BASED = 0x02; + const signed int BASEB = 0x03; + const signed int BASESP = 0x04; + const signed int BASEBP = 0x05; + const signed int BASESI = 0x06; + const signed int BASEDI = 0x07; + const signed int BASE8 = 0x08; + const signed int BASE9 = 0x09; + const signed int BASE10 = 0x0A; + const signed int BASE11 = 0x0B; + const signed int BASE12 = 0x0C; + const signed int BASE13 = 0x0D; + const signed int BASE14 = 0x0E; + const signed int BASE15 = 0x0F; + + /* Base IDs for memory segment registers */ + const signed int BASEDS = 0x0; // Data Segment register + const signed int BASESS = 0x1; // Stack Segment register + const signed int BASEFS = 0x2; // F Segment register + const signed int BASEGS = 0x3; // G Segment register + const signed int BASECS = 0x4; // Code Segment register + const signed int BASEES = 0x5; // Extended data Segment register + const signed int BASEGD = 0x6; // Global Descriptor Table + const signed int BASELD = 0x7; // Local Descriptor Table + const signed int BASEID = 0X8; // Interrupt Descriptor Table + const signed int BASETR = 0x9; // Task Register + + /* Base IDs for each bit in RFLAGS */ + const signed int CF = x86::CF; // Carry Flag + const signed int FLAG1 = x86::FLAG1; // Reserved + const signed int PF = x86::PF; // Parity Flag + const signed int FLAG3 = x86::FLAG3; // Reserved + const signed int AF = x86::AF; // Auxiliary Carry Flag + const signed int FLAG5 = x86::FLAG5; // Reserved + const signed int ZF = x86::ZF; // Zero Flag + const signed int SF = x86::SF; // Sign Flag + const signed int TF = x86::TF; // Trap Flag + const signed int IF = x86::IF; // Interrupt Enable Flag + const signed int DF = x86::DF; // Direction Flag + const signed int OF = x86::OF; // Overflow Flag + const signed int FLAGC = x86::FLAGC; // I/O Privilege Level (bits 12 and 13) + const signed int FLAGD = x86::FLAGD; // I/O Privilege Level (bits 12 and 13) + const signed int NT = x86::NT; // Nested Task + const signed int FLAGF = x86::FLAGF; // Reserved + const signed int RF = x86::RF; // Resume Flag + const signed int VM = x86::VM; // Virtual-8086 Mode + const signed int AC = x86::AC; // Alignment Check/Access Control + const signed int VIF = x86::VIF; // Virtual Interrupt Flag + const signed int VIP = x86::VIP; // Virtual Interrupt Pending + const signed int ID = x86::ID; // ID Flag + /* Flags 22-63 are reserved */ + + /* Format of constants: + * [0x000000ff] Lower 16 bits are base register ID + * [0x0000ff00] Next 16 bits are the aliasing and subrange ID used to distinguish + * between whole and aliased registers like EAX and AH. + * [0x00ff0000] Next 16 bits are the register category, GPR, FLAG, etc. + * [0xff000000] Upper 16 bits are the architecture. + */ + // ( name, ID | alias | cat | arch, arch) + DEF_REGISTER( rax, BASEA | FULL | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER( eax, BASEA | D_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER( ax, BASEA | W_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER( ah, BASEA | H_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER( al, BASEA | L_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER( rcx, BASEC | FULL | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER( ecx, BASEC | D_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER( cx, BASEC | W_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER( ch, BASEC | H_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER( cl, BASEC | L_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER( rdx, BASED | FULL | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER( edx, BASED | D_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER( dx, BASED | W_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER( dh, BASED | H_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER( dl, BASED | L_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER( rbx, BASEB | FULL | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER( ebx, BASEB | D_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER( bx, BASEB | W_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER( bh, BASEB | H_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER( bl, BASEB | L_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER( rsp, BASESP | FULL | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER( esp, BASESP | D_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER( sp, BASESP | W_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER( spl, BASESP | L_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER( rbp, BASEBP | FULL | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER( ebp, BASEBP | D_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER( bp, BASEBP | W_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER( bpl, BASEBP | L_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER( rsi, BASESI | FULL | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER( esi, BASESI | D_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER( si, BASESI | W_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER( sil, BASESI | L_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER( rdi, BASEDI | FULL | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER( edi, BASEDI | D_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER( di, BASEDI | W_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER( dil, BASEDI | L_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER( r8, BASE8 | FULL | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER( r8b, BASE8 | L_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER( r8w, BASE8 | W_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER( r8d, BASE8 | D_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER( r9, BASE9 | FULL | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER( r9b, BASE9 | L_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER( r9w, BASE9 | W_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER( r9d, BASE9 | D_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER( r10, BASE10 | FULL | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER( r10b, BASE10 | L_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER( r10w, BASE10 | W_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER( r10d, BASE10 | D_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER( r11, BASE11 | FULL | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER( r11b, BASE11 | L_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER( r11w, BASE11 | W_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER( r11d, BASE11 | D_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER( r12, BASE12 | FULL | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER( r12b, BASE12 | L_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER( r12w, BASE12 | W_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER( r12d, BASE12 | D_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER( r13, BASE13 | FULL | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER( r13b, BASE13 | L_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER( r13w, BASE13 | W_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER( r13d, BASE13 | D_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER( r14, BASE14 | FULL | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER( r14b, BASE14 | L_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER( r14w, BASE14 | W_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER( r14d, BASE14 | D_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER( r15, BASE15 | FULL | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER( r15b, BASE15 | L_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER( r15w, BASE15 | W_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER( r15d, BASE15 | D_REG | GPR | Arch_x86_64, "x86_64"); + DEF_REGISTER( rip, 0x10 | FULL | Arch_x86_64, "x86_64"); + DEF_REGISTER( eip, 0x10 | D_REG | Arch_x86_64, "x86_64"); + + DEF_REGISTER( flags, FLAGS | FULL | FLAG | Arch_x86_64, "x86_64"); + DEF_REGISTER( cf, CF | BIT | FLAG | Arch_x86_64, "x86_64"); + DEF_REGISTER( flag1, FLAG1 | BIT | FLAG | Arch_x86_64, "x86_64"); + DEF_REGISTER( pf, PF | BIT | FLAG | Arch_x86_64, "x86_64"); + DEF_REGISTER( flag3, FLAG3 | BIT | FLAG | Arch_x86_64, "x86_64"); + DEF_REGISTER( af, AF | BIT | FLAG | Arch_x86_64, "x86_64"); + DEF_REGISTER( flag5, FLAG5 | BIT | FLAG | Arch_x86_64, "x86_64"); + DEF_REGISTER( zf, ZF | BIT | FLAG | Arch_x86_64, "x86_64"); + DEF_REGISTER( sf, SF | BIT | FLAG | Arch_x86_64, "x86_64"); + DEF_REGISTER( tf, TF | BIT | FLAG | Arch_x86_64, "x86_64"); + DEF_REGISTER( if_, IF | BIT | FLAG | Arch_x86_64, "x86_64"); + DEF_REGISTER( df, DF | BIT | FLAG | Arch_x86_64, "x86_64"); + DEF_REGISTER( of, OF | BIT | FLAG | Arch_x86_64, "x86_64"); + DEF_REGISTER( flagc, FLAGC | BIT | FLAG | Arch_x86_64, "x86_64"); + DEF_REGISTER( flagd, FLAGD | BIT | FLAG | Arch_x86_64, "x86_64"); + DEF_REGISTER( nt_, NT | BIT | FLAG | Arch_x86_64, "x86_64"); + DEF_REGISTER( flagf, FLAGF | BIT | FLAG | Arch_x86_64, "x86_64"); + DEF_REGISTER( rf, RF | BIT | FLAG | Arch_x86_64, "x86_64"); + DEF_REGISTER( vm, VM | BIT | FLAG | Arch_x86_64, "x86_64"); + DEF_REGISTER( ac, AC | BIT | FLAG | Arch_x86_64, "x86_64"); + DEF_REGISTER( vif, VIF | BIT | FLAG | Arch_x86_64, "x86_64"); + DEF_REGISTER( vip, VIP | BIT | FLAG | Arch_x86_64, "x86_64"); + DEF_REGISTER( id, ID | BIT | FLAG | Arch_x86_64, "x86_64"); + + DEF_REGISTER( ds, BASEDS | FULL | SEG | Arch_x86_64, "x86_64"); + DEF_REGISTER( es, BASEES | FULL | SEG | Arch_x86_64, "x86_64"); + DEF_REGISTER( fs, BASEFS | FULL | SEG | Arch_x86_64, "x86_64"); + DEF_REGISTER( gs, BASEGS | FULL | SEG | Arch_x86_64, "x86_64"); + DEF_REGISTER( cs, BASECS | FULL | SEG | Arch_x86_64, "x86_64"); + DEF_REGISTER( ss, BASESS | FULL | SEG | Arch_x86_64, "x86_64"); + DEF_REGISTER( gdtr, BASEGD | W_REG | SEG | Arch_x86_64, "x86_64"); + DEF_REGISTER( ldtr, BASELD | W_REG | SEG | Arch_x86_64, "x86_64"); + DEF_REGISTER( idtr, BASEID | W_REG | SEG | Arch_x86_64, "x86_64"); + DEF_REGISTER( tr, BASETR | W_REG | SEG | Arch_x86_64, "x86_64"); + + DEF_REGISTER( cr0, 0x0 | FULL | CTL | Arch_x86_64, "x86_64"); + DEF_REGISTER( cr1, 0x1 | FULL | CTL | Arch_x86_64, "x86_64"); + DEF_REGISTER( cr2, 0x2 | FULL | CTL | Arch_x86_64, "x86_64"); + DEF_REGISTER( cr3, 0x3 | FULL | CTL | Arch_x86_64, "x86_64"); + DEF_REGISTER( cr4, 0x4 | FULL | CTL | Arch_x86_64, "x86_64"); + DEF_REGISTER( cr5, 0x5 | FULL | CTL | Arch_x86_64, "x86_64"); + DEF_REGISTER( cr6, 0x6 | FULL | CTL | Arch_x86_64, "x86_64"); + DEF_REGISTER( cr7, 0x7 | FULL | CTL | Arch_x86_64, "x86_64"); + DEF_REGISTER( cr8, 0x8 | FULL | CTL | Arch_x86_64, "x86_64"); + DEF_REGISTER( cr9, 0x9 | FULL | CTL | Arch_x86_64, "x86_64"); + DEF_REGISTER( cr10, 0xA | FULL | CTL | Arch_x86_64, "x86_64"); + DEF_REGISTER( cr11, 0xB | FULL | CTL | Arch_x86_64, "x86_64"); + DEF_REGISTER( cr12, 0xC | FULL | CTL | Arch_x86_64, "x86_64"); + DEF_REGISTER( cr13, 0xD | FULL | CTL | Arch_x86_64, "x86_64"); + DEF_REGISTER( cr14, 0xE | FULL | CTL | Arch_x86_64, "x86_64"); + DEF_REGISTER( cr15, 0xF | FULL | CTL | Arch_x86_64, "x86_64"); + + DEF_REGISTER( dr0, 0x0 | FULL | DBG | Arch_x86_64, "x86_64"); + DEF_REGISTER( dr1, 0x1 | FULL | DBG | Arch_x86_64, "x86_64"); + DEF_REGISTER( dr2, 0x2 | FULL | DBG | Arch_x86_64, "x86_64"); + DEF_REGISTER( dr3, 0x3 | FULL | DBG | Arch_x86_64, "x86_64"); + DEF_REGISTER( dr4, 0x4 | FULL | DBG | Arch_x86_64, "x86_64"); + DEF_REGISTER( dr5, 0x5 | FULL | DBG | Arch_x86_64, "x86_64"); + DEF_REGISTER( dr6, 0x6 | FULL | DBG | Arch_x86_64, "x86_64"); + DEF_REGISTER( dr7, 0x7 | FULL | DBG | Arch_x86_64, "x86_64"); + DEF_REGISTER( dr8, 0x8 | FULL | DBG | Arch_x86_64, "x86_64"); + DEF_REGISTER( dr9, 0x9 | FULL | DBG | Arch_x86_64, "x86_64"); + DEF_REGISTER( dr10, 0xA | FULL | DBG | Arch_x86_64, "x86_64"); + DEF_REGISTER( dr11, 0xB | FULL | DBG | Arch_x86_64, "x86_64"); + DEF_REGISTER( dr12, 0xC | FULL | DBG | Arch_x86_64, "x86_64"); + DEF_REGISTER( dr13, 0xD | FULL | DBG | Arch_x86_64, "x86_64"); + DEF_REGISTER( dr14, 0xE | FULL | DBG | Arch_x86_64, "x86_64"); + DEF_REGISTER( dr15, 0xF | FULL | DBG | Arch_x86_64, "x86_64"); + + DEF_REGISTER( st0, 0x0 | FPDBL | X87 | Arch_x86_64, "x86_64"); + DEF_REGISTER( st1, 0x1 | FPDBL | X87 | Arch_x86_64, "x86_64"); + DEF_REGISTER( st2, 0x2 | FPDBL | X87 | Arch_x86_64, "x86_64"); + DEF_REGISTER( st3, 0x3 | FPDBL | X87 | Arch_x86_64, "x86_64"); + DEF_REGISTER( st4, 0x4 | FPDBL | X87 | Arch_x86_64, "x86_64"); + DEF_REGISTER( st5, 0x5 | FPDBL | X87 | Arch_x86_64, "x86_64"); + DEF_REGISTER( st6, 0x6 | FPDBL | X87 | Arch_x86_64, "x86_64"); + DEF_REGISTER( st7, 0x7 | FPDBL | X87 | Arch_x86_64, "x86_64"); + DEF_REGISTER( fcw, 0x8 | W_REG | FPCTL | Arch_x86_64, "x86_64"); + DEF_REGISTER( fsw, 0x9 | W_REG | FPCTL | Arch_x86_64, "x86_64"); + + DEF_REGISTER( mm0, 0x0 | MMS | MMX | Arch_x86_64, "x86_64"); + DEF_REGISTER( mm1, 0x1 | MMS | MMX | Arch_x86_64, "x86_64"); + DEF_REGISTER( mm2, 0x2 | MMS | MMX | Arch_x86_64, "x86_64"); + DEF_REGISTER( mm3, 0x3 | MMS | MMX | Arch_x86_64, "x86_64"); + DEF_REGISTER( mm4, 0x4 | MMS | MMX | Arch_x86_64, "x86_64"); + DEF_REGISTER( mm5, 0x5 | MMS | MMX | Arch_x86_64, "x86_64"); + DEF_REGISTER( mm6, 0x6 | MMS | MMX | Arch_x86_64, "x86_64"); + DEF_REGISTER( mm7, 0x7 | MMS | MMX | Arch_x86_64, "x86_64"); + + DEF_REGISTER( xmm0, 0x00 | XMMS | XMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( xmm1, 0x01 | XMMS | XMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( xmm2, 0x02 | XMMS | XMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( xmm3, 0x03 | XMMS | XMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( xmm4, 0x04 | XMMS | XMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( xmm5, 0x05 | XMMS | XMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( xmm6, 0x06 | XMMS | XMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( xmm7, 0x07 | XMMS | XMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( xmm8, 0x08 | XMMS | XMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( xmm9, 0x09 | XMMS | XMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( xmm10, 0x0A | XMMS | XMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( xmm11, 0x0B | XMMS | XMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( xmm12, 0x0C | XMMS | XMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( xmm13, 0x0D | XMMS | XMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( xmm14, 0x0E | XMMS | XMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( xmm15, 0x0F | XMMS | XMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( xmm16, 0x10 | XMMS | XMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( xmm17, 0x11 | XMMS | XMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( xmm18, 0x12 | XMMS | XMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( xmm19, 0x13 | XMMS | XMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( xmm20, 0x14 | XMMS | XMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( xmm21, 0x15 | XMMS | XMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( xmm22, 0x16 | XMMS | XMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( xmm23, 0x17 | XMMS | XMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( xmm24, 0x18 | XMMS | XMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( xmm25, 0x19 | XMMS | XMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( xmm26, 0x1A | XMMS | XMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( xmm27, 0x1B | XMMS | XMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( xmm28, 0x1C | XMMS | XMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( xmm29, 0x1D | XMMS | XMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( xmm30, 0x1E | XMMS | XMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( xmm31, 0x1F | XMMS | XMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( mxcsr, 0x20 | D_REG | FPCTL | Arch_x86_64, "x86_64"); + + DEF_REGISTER( ymm0, 0x00 | YMMS | YMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( ymm1, 0x01 | YMMS | YMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( ymm2, 0x02 | YMMS | YMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( ymm3, 0x03 | YMMS | YMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( ymm4, 0x04 | YMMS | YMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( ymm5, 0x05 | YMMS | YMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( ymm6, 0x06 | YMMS | YMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( ymm7, 0x07 | YMMS | YMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( ymm8, 0x08 | YMMS | YMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( ymm9, 0x09 | YMMS | YMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( ymm10, 0x0A | YMMS | YMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( ymm11, 0x0B | YMMS | YMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( ymm12, 0x0C | YMMS | YMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( ymm13, 0x0D | YMMS | YMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( ymm14, 0x0E | YMMS | YMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( ymm15, 0x0F | YMMS | YMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( ymm16, 0x10 | YMMS | YMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( ymm17, 0x11 | YMMS | YMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( ymm18, 0x12 | YMMS | YMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( ymm19, 0x13 | YMMS | YMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( ymm20, 0x14 | YMMS | YMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( ymm21, 0x15 | YMMS | YMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( ymm22, 0x16 | YMMS | YMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( ymm23, 0x17 | YMMS | YMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( ymm24, 0x18 | YMMS | YMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( ymm25, 0x19 | YMMS | YMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( ymm26, 0x1A | YMMS | YMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( ymm27, 0x1B | YMMS | YMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( ymm28, 0x1C | YMMS | YMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( ymm29, 0x1D | YMMS | YMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( ymm30, 0x1E | YMMS | YMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( ymm31, 0x1F | YMMS | YMM | Arch_x86_64, "x86_64"); + + DEF_REGISTER( zmm0, 0x00 | ZMMS | ZMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( zmm1, 0x01 | ZMMS | ZMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( zmm2, 0x02 | ZMMS | ZMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( zmm3, 0x03 | ZMMS | ZMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( zmm4, 0x04 | ZMMS | ZMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( zmm5, 0x05 | ZMMS | ZMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( zmm6, 0x06 | ZMMS | ZMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( zmm7, 0x07 | ZMMS | ZMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( zmm8, 0x08 | ZMMS | ZMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( zmm9, 0x09 | ZMMS | ZMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( zmm10, 0x0A | ZMMS | ZMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( zmm11, 0x0B | ZMMS | ZMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( zmm12, 0x0C | ZMMS | ZMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( zmm13, 0x0D | ZMMS | ZMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( zmm14, 0x0E | ZMMS | ZMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( zmm15, 0x0F | ZMMS | ZMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( zmm16, 0x10 | ZMMS | ZMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( zmm17, 0x11 | ZMMS | ZMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( zmm18, 0x12 | ZMMS | ZMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( zmm19, 0x13 | ZMMS | ZMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( zmm20, 0x14 | ZMMS | ZMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( zmm21, 0x15 | ZMMS | ZMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( zmm22, 0x16 | ZMMS | ZMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( zmm23, 0x17 | ZMMS | ZMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( zmm24, 0x18 | ZMMS | ZMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( zmm25, 0x19 | ZMMS | ZMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( zmm26, 0x1A | ZMMS | ZMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( zmm27, 0x1B | ZMMS | ZMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( zmm28, 0x1C | ZMMS | ZMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( zmm29, 0x1D | ZMMS | ZMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( zmm30, 0x1E | ZMMS | ZMM | Arch_x86_64, "x86_64"); + DEF_REGISTER( zmm31, 0x1F | ZMMS | ZMM | Arch_x86_64, "x86_64"); + + DEF_REGISTER( k0, 0x00 | KMSKS | KMASK | Arch_x86_64, "x86_64"); + DEF_REGISTER( k1, 0x01 | KMSKS | KMASK | Arch_x86_64, "x86_64"); + DEF_REGISTER( k2, 0x02 | KMSKS | KMASK | Arch_x86_64, "x86_64"); + DEF_REGISTER( k3, 0x03 | KMSKS | KMASK | Arch_x86_64, "x86_64"); + DEF_REGISTER( k4, 0x04 | KMSKS | KMASK | Arch_x86_64, "x86_64"); + DEF_REGISTER( k5, 0x05 | KMSKS | KMASK | Arch_x86_64, "x86_64"); + DEF_REGISTER( k6, 0x06 | KMSKS | KMASK | Arch_x86_64, "x86_64"); + DEF_REGISTER( k7, 0x07 | KMSKS | KMASK | Arch_x86_64, "x86_64"); + + + /* Pseudo-registers for internal use only */ + DEF_REGISTER( orax, 0x0 | FULL | MISC | Arch_x86_64, "x86_64"); + DEF_REGISTER( fsbase, 0x1 | FULL | MISC | Arch_x86_64, "x86_64"); + DEF_REGISTER( gsbase, 0x2 | FULL | MISC | Arch_x86_64, "x86_64"); + DEF_REGISTER( tr0, 0x0 | FULL | TST | Arch_x86_64, "x86_64"); + DEF_REGISTER( tr1, 0x1 | FULL | TST | Arch_x86_64, "x86_64"); + DEF_REGISTER( tr2, 0x2 | FULL | TST | Arch_x86_64, "x86_64"); + DEF_REGISTER( tr3, 0x3 | FULL | TST | Arch_x86_64, "x86_64"); + DEF_REGISTER( tr4, 0x4 | FULL | TST | Arch_x86_64, "x86_64"); + DEF_REGISTER( tr5, 0x5 | FULL | TST | Arch_x86_64, "x86_64"); + DEF_REGISTER( tr6, 0x6 | FULL | TST | Arch_x86_64, "x86_64"); + DEF_REGISTER( tr7, 0x7 | FULL | TST | Arch_x86_64, "x86_64"); + +}} + +#endif diff --git a/common/h/registers/x86_regs.h b/common/h/registers/x86_regs.h new file mode 100644 index 0000000000..41a085f3fb --- /dev/null +++ b/common/h/registers/x86_regs.h @@ -0,0 +1,301 @@ +/* + * See the dyninst/COPYRIGHT file for copyright information. + * + * We provide the Paradyn Tools (below described as "Paradyn") + * on an AS IS basis, and do not warrant its validity or performance. + * We reserve the right to update, modify, or discontinue this + * software at any time. We shall have no obligation to supply such + * updates or modifications or any other form of support to you. + * + * By your use of Paradyn, you understand and agree that we (or any + * other person or entity with proprietary rights in Paradyn) are + * under no obligation to provide either maintenance services, + * update services, notices of latent defects, or correction of + * defects for Paradyn. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef DYNINST_X86_REGS_H +#define DYNINST_X86_REGS_H + +//clang-format: off + +#include "Architecture.h" +#include "registers/reg_def.h" + +namespace Dyninst { namespace x86 { + + /* Register lengths + * + * NOTE: + * + * MachRegister::getBaseRegister clears the bit field for size, so + * the full register size has to be represented as 0x0. + * + * The {L,H,W}_REG sizes represent the aliased portions of the GPR + * registers that are historically referred to by name (e.g., AL is + * the lower 8 bits of EAX). + * + * The SSE registers are given the correct size of 64 bits even + * though they alias the lower 64 bits of the x87 FPU registers. + * + * No attempt is made to represent aliased portions of other registers. + */ + const signed int FULL = 0x00000000; // 32 bits + const signed int BIT = 0x00000100; // 1-bit EFLAGS + const signed int L_REG = 0x00000200; // 8-bit, first byte + const signed int H_REG = 0x00000300; // 8-bit, second byte + const signed int W_REG = 0x00000400; // 16-bit, first word + const signed int FPDBL = 0x00000500; // 80-bit x87 FPU + const signed int MMS = 0x00000600; // 64-bit MMX and 3DNow! + const signed int XMMS = 0x00000700; // 128-bit SSE, FC16, XOP, AVX, and FMA3/4 + const signed int YMMS = 0x00000800; // 256-bit SSE, AVX2, FMA3/4 + const signed int ZMMS = 0x00000900; // 512-bit AVX-512/AVX10 + const signed int KMSKS = 0x00000A00; // 64-bit mask from AVX-512/AVX10 + + /* Register Categories */ + const signed int GPR = 0x00010000; // General-Purpose Registers + const signed int SEG = 0x00020000; // Segment Registers + const signed int FLAG = 0x00030000; // EFLAGS Register + const signed int MISC = 0x00040000; // Internal ProcControlAPI Register + const signed int CTL = 0x00050000; // Control Registers CR0-CR7 + const signed int DBG = 0x00060000; // Debug Registers DR0-DR7 + const signed int TST = 0x00070000; // Internal InstructionAPI Registers + const signed int X87 = 0x00080000; // x87 FPU Registers + const signed int MMX = 0x00090000; // MM0-MM7 Registers + const signed int XMM = 0x000A0000; // XMM0-XMM7 Registers from SSE + const signed int YMM = 0x000B0000; // YMM0-YMM7 Registers from AVX2/FMA + const signed int ZMM = 0x000C0000; // ZMM0-ZMM7 Registers from AVX-512 + const signed int KMASK = 0x000D0000; // K0-K7 opmask Registers from AVX-512 + const signed int FPCTL = 0x000E0000; // control/status Registers from x87, SSE, and AVX + + /* Base IDs for aliased GPRs */ + const signed int BASEA = 0x0; + const signed int BASEC = 0x1; + const signed int BASED = 0x2; + const signed int BASEB = 0x3; + const signed int BASESP = 0x4; + const signed int BASEBP = 0x5; + const signed int BASESI = 0x6; + const signed int BASEDI = 0x7; + const signed int FLAGS = 0x0; + + /* Base IDs for memory segment registers */ + const signed int BASEDS = 0x0; // Data Segment register + const signed int BASESS = 0x1; // Stack Segment register + const signed int BASEFS = 0x2; // F Segment register + const signed int BASEGS = 0x3; // G Segment register + const signed int BASECS = 0x4; // Code Segment register + const signed int BASEES = 0x5; // Extended data Segment register + const signed int BASEGD = 0x6; // Global Descriptor Table + const signed int BASELD = 0x7; // Local Descriptor Table + const signed int BASEID = 0X8; // Interrupt Descriptor Table + const signed int BASETR = 0x9; // Task Register + + /* Base IDs for each bit in EFLAGS */ + const signed int CF = 0x00; // Carry Flag + const signed int FLAG1 = 0x01; // Reserved + const signed int PF = 0x02; // Parity Flag + const signed int FLAG3 = 0x03; // Reserved + const signed int AF = 0x04; // Auxiliary Carry Flag + const signed int FLAG5 = 0x05; // Reserved + const signed int ZF = 0x06; // Zero Flag + const signed int SF = 0x07; // Sign Flag + const signed int TF = 0x08; // Trap Flag + const signed int IF = 0x09; // Interrupt Enable Flag + const signed int DF = 0x0A; // Direction Flag + const signed int OF = 0x0B; // Overflow Flag + const signed int FLAGC = 0x0C; // I/O Privilege Level (bits 12 and 13) + const signed int FLAGD = 0x0D; // I/O Privilege Level (bits 12 and 13) + const signed int NT = 0x0E; // Nested Task + const signed int FLAGF = 0x0F; // Reserved + const signed int RF = 0x10; // Resume Flag + const signed int VM = 0x11; // Virtual-8086 Mode + const signed int AC = 0x12; // Alignment Check/Access Control + const signed int VIF = 0x13; // Virtual Interrupt Flag + const signed int VIP = 0x14; // Virtual Interrupt Pending + const signed int ID = 0x15; // ID Flag + /* Flags 22-31 are reserved */ + + + /** + * Format of constants: + * [0x000000ff] Lower 8 bits are base register ID + * [0x0000ff00] Next 8 bits are the aliasing and subrange ID used to distinguish + * between whole and aliased registers like EAX and AH. + * [0x00ff0000] Next 8 bits are the register category, GPR, FLAG, etc. + * [0xff000000] Upper 8 bits are the architecture. + **/ + + /* General-purpose Registers */ + // ( name, ID | alias | cat | arch, arch) + DEF_REGISTER( eax, BASEA | FULL | GPR | Arch_x86, "x86"); + DEF_REGISTER( ax, BASEA | W_REG | GPR | Arch_x86, "x86"); + DEF_REGISTER( ah, BASEA | H_REG | GPR | Arch_x86, "x86"); + DEF_REGISTER( al, BASEA | L_REG | GPR | Arch_x86, "x86"); + DEF_REGISTER( ecx, BASEC | FULL | GPR | Arch_x86, "x86"); + DEF_REGISTER( cx, BASEC | W_REG | GPR | Arch_x86, "x86"); + DEF_REGISTER( ch, BASEC | H_REG | GPR | Arch_x86, "x86"); + DEF_REGISTER( cl, BASEC | L_REG | GPR | Arch_x86, "x86"); + DEF_REGISTER( edx, BASED | FULL | GPR | Arch_x86, "x86"); + DEF_REGISTER( dx, BASED | W_REG | GPR | Arch_x86, "x86"); + DEF_REGISTER( dh, BASED | H_REG | GPR | Arch_x86, "x86"); + DEF_REGISTER( dl, BASED | L_REG | GPR | Arch_x86, "x86"); + DEF_REGISTER( ebx, BASEB | FULL | GPR | Arch_x86, "x86"); + DEF_REGISTER( bx, BASEB | W_REG | GPR | Arch_x86, "x86"); + DEF_REGISTER( bh, BASEB | H_REG | GPR | Arch_x86, "x86"); + DEF_REGISTER( bl, BASEB | L_REG | GPR | Arch_x86, "x86"); + DEF_REGISTER( esp, BASESP | FULL | GPR | Arch_x86, "x86"); + DEF_REGISTER( sp, BASESP | W_REG | GPR | Arch_x86, "x86"); + DEF_REGISTER( ebp, BASEBP | FULL | GPR | Arch_x86, "x86"); + DEF_REGISTER( bp, BASEBP | W_REG | GPR | Arch_x86, "x86"); + DEF_REGISTER( esi, BASESI | FULL | GPR | Arch_x86, "x86"); + DEF_REGISTER( si, BASESI | W_REG | GPR | Arch_x86, "x86"); + DEF_REGISTER( edi, BASEDI | FULL | GPR | Arch_x86, "x86"); + DEF_REGISTER( di, BASEDI | W_REG | GPR | Arch_x86, "x86"); + DEF_REGISTER( eip, 0x10 | FULL | Arch_x86, "x86"); + + DEF_REGISTER( cs, BASECS | W_REG | SEG | Arch_x86, "x86"); + DEF_REGISTER( ds, BASEDS | W_REG | SEG | Arch_x86, "x86"); + DEF_REGISTER( es, BASEES | W_REG | SEG | Arch_x86, "x86"); + DEF_REGISTER( ss, BASESS | W_REG | SEG | Arch_x86, "x86"); + DEF_REGISTER( fs, BASEFS | W_REG | SEG | Arch_x86, "x86"); + DEF_REGISTER( gs, BASEGS | W_REG | SEG | Arch_x86, "x86"); + DEF_REGISTER( gdtr, BASEGD | W_REG | SEG | Arch_x86, "x86"); + DEF_REGISTER( ldtr, BASELD | W_REG | SEG | Arch_x86, "x86"); + DEF_REGISTER( idtr, BASEID | W_REG | SEG | Arch_x86, "x86"); + DEF_REGISTER( tr, BASETR | W_REG | SEG | Arch_x86, "x86"); + + DEF_REGISTER( flags, FLAGS | FULL | FLAG | Arch_x86, "x86"); + DEF_REGISTER( cf, CF | BIT | FLAG | Arch_x86, "x86"); + DEF_REGISTER( flag1, FLAG1 | BIT | FLAG | Arch_x86, "x86"); + DEF_REGISTER( pf, PF | BIT | FLAG | Arch_x86, "x86"); + DEF_REGISTER( flag3, FLAG3 | BIT | FLAG | Arch_x86, "x86"); + DEF_REGISTER( af, AF | BIT | FLAG | Arch_x86, "x86"); + DEF_REGISTER( flag5, FLAG5 | BIT | FLAG | Arch_x86, "x86"); + DEF_REGISTER( zf, ZF | BIT | FLAG | Arch_x86, "x86"); + DEF_REGISTER( sf, SF | BIT | FLAG | Arch_x86, "x86"); + DEF_REGISTER( tf, TF | BIT | FLAG | Arch_x86, "x86"); + DEF_REGISTER( if_, IF | BIT | FLAG | Arch_x86, "x86"); + DEF_REGISTER( df, DF | BIT | FLAG | Arch_x86, "x86"); + DEF_REGISTER( of, OF | BIT | FLAG | Arch_x86, "x86"); + DEF_REGISTER( flagc, FLAGC | BIT | FLAG | Arch_x86, "x86"); + DEF_REGISTER( flagd, FLAGD | BIT | FLAG | Arch_x86, "x86"); + DEF_REGISTER( nt_, NT | BIT | FLAG | Arch_x86, "x86"); + DEF_REGISTER( flagf, FLAGF | BIT | FLAG | Arch_x86, "x86"); + DEF_REGISTER( rf, RF | BIT | FLAG | Arch_x86, "x86"); + DEF_REGISTER( vm, VM | BIT | FLAG | Arch_x86, "x86"); + DEF_REGISTER( ac, AC | BIT | FLAG | Arch_x86, "x86"); + DEF_REGISTER( vif, VIF | BIT | FLAG | Arch_x86, "x86"); + DEF_REGISTER( vip, VIP | BIT | FLAG | Arch_x86, "x86"); + DEF_REGISTER( id, ID | BIT | FLAG | Arch_x86, "x86"); + + DEF_REGISTER( cr0, 0x0 | FULL | CTL | Arch_x86, "x86"); + DEF_REGISTER( cr1, 0x1 | FULL | CTL | Arch_x86, "x86"); + DEF_REGISTER( cr2, 0x2 | FULL | CTL | Arch_x86, "x86"); + DEF_REGISTER( cr3, 0x3 | FULL | CTL | Arch_x86, "x86"); + DEF_REGISTER( cr4, 0x4 | FULL | CTL | Arch_x86, "x86"); + DEF_REGISTER( cr5, 0x5 | FULL | CTL | Arch_x86, "x86"); + DEF_REGISTER( cr6, 0x6 | FULL | CTL | Arch_x86, "x86"); + DEF_REGISTER( cr7, 0x7 | FULL | CTL | Arch_x86, "x86"); + + DEF_REGISTER( dr0, 0x0 | FULL | DBG | Arch_x86, "x86"); + DEF_REGISTER( dr1, 0x1 | FULL | DBG | Arch_x86, "x86"); + DEF_REGISTER( dr2, 0x2 | FULL | DBG | Arch_x86, "x86"); + DEF_REGISTER( dr3, 0x3 | FULL | DBG | Arch_x86, "x86"); + DEF_REGISTER( dr4, 0x4 | FULL | DBG | Arch_x86, "x86"); + DEF_REGISTER( dr5, 0x5 | FULL | DBG | Arch_x86, "x86"); + DEF_REGISTER( dr6, 0x6 | FULL | DBG | Arch_x86, "x86"); + DEF_REGISTER( dr7, 0x7 | FULL | DBG | Arch_x86, "x86"); + + DEF_REGISTER( st0, 0x0 | FPDBL | X87 | Arch_x86, "x86"); + DEF_REGISTER( st1, 0x1 | FPDBL | X87 | Arch_x86, "x86"); + DEF_REGISTER( st2, 0x2 | FPDBL | X87 | Arch_x86, "x86"); + DEF_REGISTER( st3, 0x3 | FPDBL | X87 | Arch_x86, "x86"); + DEF_REGISTER( st4, 0x4 | FPDBL | X87 | Arch_x86, "x86"); + DEF_REGISTER( st5, 0x5 | FPDBL | X87 | Arch_x86, "x86"); + DEF_REGISTER( st6, 0x6 | FPDBL | X87 | Arch_x86, "x86"); + DEF_REGISTER( st7, 0x7 | FPDBL | X87 | Arch_x86, "x86"); + DEF_REGISTER( fcw, 0x8 | W_REG | FPCTL | Arch_x86, "x86"); + DEF_REGISTER( fsw, 0x9 | W_REG | FPCTL | Arch_x86, "x86"); + + DEF_REGISTER( mm0, 0x0 | MMS | MMX | Arch_x86, "x86"); + DEF_REGISTER( mm1, 0x1 | MMS | MMX | Arch_x86, "x86"); + DEF_REGISTER( mm2, 0x2 | MMS | MMX | Arch_x86, "x86"); + DEF_REGISTER( mm3, 0x3 | MMS | MMX | Arch_x86, "x86"); + DEF_REGISTER( mm4, 0x4 | MMS | MMX | Arch_x86, "x86"); + DEF_REGISTER( mm5, 0x5 | MMS | MMX | Arch_x86, "x86"); + DEF_REGISTER( mm6, 0x6 | MMS | MMX | Arch_x86, "x86"); + DEF_REGISTER( mm7, 0x7 | MMS | MMX | Arch_x86, "x86"); + + DEF_REGISTER( xmm0, 0x00 | XMMS | XMM | Arch_x86, "x86"); + DEF_REGISTER( xmm1, 0x01 | XMMS | XMM | Arch_x86, "x86"); + DEF_REGISTER( xmm2, 0x02 | XMMS | XMM | Arch_x86, "x86"); + DEF_REGISTER( xmm3, 0x03 | XMMS | XMM | Arch_x86, "x86"); + DEF_REGISTER( xmm4, 0x04 | XMMS | XMM | Arch_x86, "x86"); + DEF_REGISTER( xmm5, 0x05 | XMMS | XMM | Arch_x86, "x86"); + DEF_REGISTER( xmm6, 0x06 | XMMS | XMM | Arch_x86, "x86"); + DEF_REGISTER( xmm7, 0x07 | XMMS | XMM | Arch_x86, "x86"); + DEF_REGISTER( mxcsr, 0x08 | FULL | FPCTL | Arch_x86, "x86"); + + DEF_REGISTER( ymm0, 0x00 | YMMS | YMM | Arch_x86, "x86"); + DEF_REGISTER( ymm1, 0x01 | YMMS | YMM | Arch_x86, "x86"); + DEF_REGISTER( ymm2, 0x02 | YMMS | YMM | Arch_x86, "x86"); + DEF_REGISTER( ymm3, 0x03 | YMMS | YMM | Arch_x86, "x86"); + DEF_REGISTER( ymm4, 0x04 | YMMS | YMM | Arch_x86, "x86"); + DEF_REGISTER( ymm5, 0x05 | YMMS | YMM | Arch_x86, "x86"); + DEF_REGISTER( ymm6, 0x06 | YMMS | YMM | Arch_x86, "x86"); + DEF_REGISTER( ymm7, 0x07 | YMMS | YMM | Arch_x86, "x86"); + + DEF_REGISTER( zmm0, 0x00 | ZMMS | ZMM | Arch_x86, "x86"); + DEF_REGISTER( zmm1, 0x01 | ZMMS | ZMM | Arch_x86, "x86"); + DEF_REGISTER( zmm2, 0x02 | ZMMS | ZMM | Arch_x86, "x86"); + DEF_REGISTER( zmm3, 0x03 | ZMMS | ZMM | Arch_x86, "x86"); + DEF_REGISTER( zmm4, 0x04 | ZMMS | ZMM | Arch_x86, "x86"); + DEF_REGISTER( zmm5, 0x05 | ZMMS | ZMM | Arch_x86, "x86"); + DEF_REGISTER( zmm6, 0x06 | ZMMS | ZMM | Arch_x86, "x86"); + DEF_REGISTER( zmm7, 0x07 | ZMMS | ZMM | Arch_x86, "x86"); + + DEF_REGISTER( k0, 0x00 | KMSKS | KMASK | Arch_x86, "x86"); + DEF_REGISTER( k1, 0x01 | KMSKS | KMASK | Arch_x86, "x86"); + DEF_REGISTER( k2, 0x02 | KMSKS | KMASK | Arch_x86, "x86"); + DEF_REGISTER( k3, 0x03 | KMSKS | KMASK | Arch_x86, "x86"); + DEF_REGISTER( k4, 0x04 | KMSKS | KMASK | Arch_x86, "x86"); + DEF_REGISTER( k5, 0x05 | KMSKS | KMASK | Arch_x86, "x86"); + DEF_REGISTER( k6, 0x06 | KMSKS | KMASK | Arch_x86, "x86"); + DEF_REGISTER( k7, 0x07 | KMSKS | KMASK | Arch_x86, "x86"); + + /* Pseudo-registers for internal use only */ + DEF_REGISTER( oeax, 0x0 | FULL | MISC | Arch_x86, "x86"); + DEF_REGISTER( fsbase, 0x1 | FULL | MISC | Arch_x86, "x86"); + DEF_REGISTER( gsbase, 0x2 | FULL | MISC | Arch_x86, "x86"); + DEF_REGISTER( tr0, 0x0 | FULL | TST | Arch_x86, "x86"); + DEF_REGISTER( tr1, 0x1 | FULL | TST | Arch_x86, "x86"); + DEF_REGISTER( tr2, 0x2 | FULL | TST | Arch_x86, "x86"); + DEF_REGISTER( tr3, 0x3 | FULL | TST | Arch_x86, "x86"); + DEF_REGISTER( tr4, 0x4 | FULL | TST | Arch_x86, "x86"); + DEF_REGISTER( tr5, 0x5 | FULL | TST | Arch_x86, "x86"); + DEF_REGISTER( tr6, 0x6 | FULL | TST | Arch_x86, "x86"); + DEF_REGISTER( tr7, 0x7 | FULL | TST | Arch_x86, "x86"); +} + +inline bool isSegmentRegister(int regClass) { + return 0 != (regClass & x86::SEG); +} + +} + +#endif diff --git a/common/h/unaligned_memory_access.h b/common/h/unaligned_memory_access.h new file mode 100644 index 0000000000..1530fc8134 --- /dev/null +++ b/common/h/unaligned_memory_access.h @@ -0,0 +1,159 @@ +/* + * See the dyninst/COPYRIGHT file for copyright information. + * + * We provide the Paradyn Tools (below described as "Paradyn") + * on an AS IS basis, and do not warrant its validity or performance. + * We reserve the right to update, modify, or discontinue this + * software at any time. We shall have no obligation to supply such + * updates or modifications or any other form of support to you. + * + * By your use of Paradyn, you understand and agree that we (or any + * other person or entity with proprietary rights in Paradyn) are + * under no obligation to provide either maintenance services, + * update services, notices of latent defects, or correction of + * defects for Paradyn. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef unaligned_memory_access_h_ +#define unaligned_memory_access_h_ + + +/* + * Routines to access data at an arbitrary memory location (that is possibly + * unaligned for the data type) via char*-like pointer with no alignment + * restrictions. The set of functions range from safe read and write of memory + * cast to a type; to functions that cast to a pointer with more restrictive + * alignment (caller is responsible for addr's alignment correctness). + */ + + +#ifdef __cplusplus + +#include +#include + +namespace Dyninst { + +/* + * read_memory_as(addr) + * + * Return an object of TYPE created by reading sizeof(TYPE) bytes at addr. + * The address addr does not have to be properly aligned for the type. + */ +template +inline ResultType read_memory_as(const void *addr) +{ + ResultType r; + std::memcpy(static_cast(&r), addr, sizeof r); + return r; +} + + +/* + * write_memory_as(adrr, &data) + * + * Write sizeof(TYPE) bytes to the memory pointed to by addr by copying the + * bytes of the supplied parameter. The address addr does not have to be + * properly aligned for the type. + */ +template +inline void write_memory_as(void *addr, const DataType &data) +{ + std::memcpy(addr, static_cast(&data), sizeof data); +} + + +/* + * append_memory_as(adrr, &data) + * + * Write sizeof(TYPE) bytes to the memory pointed to by addr by copying the + * bytes of the supplied parameter, and adjust addr by sizeof(TYPE). The + * address addr does not have to be properly aligned for the type. + */ +template +inline void append_memory_as(PointerType *&addr, const DataType &data) +{ + write_memory_as(addr, data); + *reinterpret_cast(&addr) += sizeof(data); +} + + +/* + * append_memory_as_byte(adrr, data) + * + * Convenience function to avoid uint8_t cast when calling append_memory_as + * with a uint8_t type. + */ +template +inline void append_memory_as_byte(PointerType *&addr, std::uint8_t data) +{ + append_memory_as(addr, data); +} + + +/* + * alignas_cast(addr) + * + * Convert the addr pointer to TYPE*, that avoids triggering a warning that the + * alignment of the new pointer type is larger than the current pointer type. + * + * WARNING: The caller is responsible to ensure that the alignment is correct + * if the pointer is dereferenced. Uncomment the assert to audit proper + * alignment of addr. + * + * Use read_memory_as or write_memory_as if possible and definitely if the + * alignment of addr can not be guaranteed. + */ +template +inline DataType* alignas_cast(const void *addr) +{ + // assert((reinterpret_cast(addr) % alignof(DataType)) == 0); + return static_cast(addr); +} + + +template +inline DataType* alignas_cast(void *addr) +{ + // assert((reinterpret_cast(addr) % alignof(DataType)) == 0); + return static_cast(addr); +} + + +} + +#else + +/* + * C language - functions + */ + +/* CAST_WITHOUT_ALIGNMENT_WARNING(toType, addr) + * + * C language macro that casts the expression addr to type toType + * without producing a warning that alignment of the new pointer type is + * larger than the current pointer type. + * + * WARNING: The caller is responsible to ensure that the alignment is + * correct or use memcpy if the pointer is dereferenced. + */ +#define CAST_WITHOUT_ALIGNMENT_WARNING(toType, addr) (toType)(void*)(addr) + + +#endif + +#endif diff --git a/common/h/util.h b/common/h/util.h index eb0a1dc912..a76885e0a3 100644 --- a/common/h/util.h +++ b/common/h/util.h @@ -204,10 +204,6 @@ #include #include "dyntypes.h" -#if defined(_MSC_VER) -#pragma warning(disable: 4251 4275 4396 4996) -#endif - namespace Dyninst { diff --git a/common/src/AST.C b/common/src/AST.C index 625ebea6df..738f4d3896 100644 --- a/common/src/AST.C +++ b/common/src/AST.C @@ -28,6 +28,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include "DynAST.h" #include "../../dyninstAPI/src/debug.h" #include "../../common/src/singleton_object_pool.h" diff --git a/common/src/Annotatable.C b/common/src/Annotatable.C index b68d26e6e3..babeea5b1c 100644 --- a/common/src/Annotatable.C +++ b/common/src/Annotatable.C @@ -30,6 +30,7 @@ // $Id: Annotatable.C,v 1.12 2008/11/03 15:19:23 jaw Exp $ +#include #include "common/src/headers.h" #include "dyntypes.h" #include "Annotatable.h" diff --git a/common/src/Buffer.C b/common/src/Buffer.C index 648a86797b..6628ca0815 100644 --- a/common/src/Buffer.C +++ b/common/src/Buffer.C @@ -27,6 +27,7 @@ * License along with this library; if not, write to the Free Software * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include "Buffer.h" #include diff --git a/common/src/DOT.C b/common/src/DOT.C index f7200aec5a..a1be02ac4a 100644 --- a/common/src/DOT.C +++ b/common/src/DOT.C @@ -28,6 +28,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include "Graph.h" #include "Node.h" #include "Edge.h" diff --git a/common/src/Edge.C b/common/src/Edge.C index 6e3719e2b6..495b2e1f4b 100644 --- a/common/src/Edge.C +++ b/common/src/Edge.C @@ -30,6 +30,7 @@ // Edge class implementation +#include #include "Graph.h" #include "Edge.h" #include "Node.h" @@ -106,6 +107,7 @@ bool EdgeIterator::operator==(const EdgeIterator &rhs) const { } EdgeIterator &EdgeIterator::operator=(const EdgeIterator &rhs) { + if(this == &rhs) return *this; if (rhs.iter_ == NULL) { if (iter_) delete iter_; // No leaking! iter_ = rhs.iter_; diff --git a/common/src/Graph.C b/common/src/Graph.C index 979d12b20f..2d2d7074a9 100644 --- a/common/src/Graph.C +++ b/common/src/Graph.C @@ -30,6 +30,7 @@ // Graph class implementation +#include #include "Graph.h" #include "Edge.h" #include "Node.h" @@ -40,7 +41,7 @@ using namespace Dyninst; -const Dyninst::Address Graph::INITIAL_ADDR = (Address) -1; +const Dyninst::Address Graph::INITIAL_ADDR = (Dyninst::Address) -1; diff --git a/common/src/IntervalTree.h b/common/src/IntervalTree.h index 4aea3b2198..eb8f4b8ab0 100644 --- a/common/src/IntervalTree.h +++ b/common/src/IntervalTree.h @@ -33,6 +33,7 @@ #include #include +#include #include #include diff --git a/common/src/MachSyscall.C b/common/src/MachSyscall.C index d5e0eed4f5..f35deadac7 100644 --- a/common/src/MachSyscall.C +++ b/common/src/MachSyscall.C @@ -1,3 +1,4 @@ +#include #include "MachSyscall.h" #include "dyntypes.h" diff --git a/common/src/MappedFile.C b/common/src/MappedFile.C index a36838438b..0f2e15843c 100644 --- a/common/src/MappedFile.C +++ b/common/src/MappedFile.C @@ -27,6 +27,7 @@ * License along with this library; if not, write to the Free Software * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include "common/src/MappedFile.h" #include "common/src/pathName.h" #include @@ -169,7 +170,7 @@ void MappedFile::closeMappedFile(MappedFile *&mf) if (mf->refCount <= 0) { dyn_hash_map::iterator iter; - iter = mapped_files.find(mf->pathname()); + iter = mapped_files.find(mf->filename()); if (iter != mapped_files.end()) { @@ -414,16 +415,11 @@ bool MappedFile::close_file() return true; } -std::string MappedFile::pathname() +std::string MappedFile::filename() { return fullpath; } -std::string MappedFile::filename() -{ - return extract_pathname_tail(fullpath); -} - void MappedFile::setSharing(bool s) { can_share = s; diff --git a/common/src/MappedFile.h b/common/src/MappedFile.h index 87aef45de5..ccca79a085 100644 --- a/common/src/MappedFile.h +++ b/common/src/MappedFile.h @@ -33,7 +33,7 @@ #include "headers.h" #include -#include "Types.h" +#include "util.h" class MappedFile { static dyn_hash_map mapped_files; @@ -43,7 +43,6 @@ class MappedFile { COMMON_EXPORT static MappedFile *createMappedFile(void *map_loc, unsigned long size_, const std::string &name); COMMON_EXPORT static void closeMappedFile(MappedFile *&mf); - COMMON_EXPORT std::string pathname(); COMMON_EXPORT std::string filename(); COMMON_EXPORT void *base_addr() {return map_addr;} #if defined(os_windows) diff --git a/common/src/Node.C b/common/src/Node.C index eb78b6c4ff..2e78a52459 100644 --- a/common/src/Node.C +++ b/common/src/Node.C @@ -31,6 +31,7 @@ // Node class implementation +#include #include "Graph.h" #include "Edge.h" #include "Node.h" @@ -196,6 +197,7 @@ bool NodeIterator::operator==(const NodeIterator &rhs) const { } NodeIterator &NodeIterator::operator=(const NodeIterator &rhs) { + if(this == &rhs) return *this; if (iter_) delete iter_; iter_ = rhs.copy(); return *this; diff --git a/common/src/NodeIterator.h b/common/src/NodeIterator.h index ab9b5378ac..7a036ac696 100644 --- a/common/src/NodeIterator.h +++ b/common/src/NodeIterator.h @@ -33,6 +33,10 @@ #if !defined(NODE_ITERATOR_H) #define NODE_ITERATOR_H +#include +#include +#include +#include #include "Node.h" #include "Edge.h" @@ -328,7 +332,7 @@ class NodeIteratorPredicateObj : public NodeIteratorImpl { // next is now a matching node. If the start wasn't, // then we need to increment... if ((cur != end) && !pred->predicate(*cur)) { - inc(); + NodeIteratorPredicateObj::inc(); } } void setNext() { @@ -391,7 +395,7 @@ class NodeIteratorPredicateFunc : public NodeIteratorImpl { // next is now a matching node. If the start wasn't, // then we need to increment... if ((cur != end) && !pred(*cur, user_arg)) { - inc(); + NodeIteratorPredicateFunc::inc(); } } void setNext() { diff --git a/common/src/Pair.h b/common/src/Pair.h deleted file mode 100644 index 4e02316d7f..0000000000 --- a/common/src/Pair.h +++ /dev/null @@ -1,108 +0,0 @@ -/* - * See the dyninst/COPYRIGHT file for copyright information. - * - * We provide the Paradyn Tools (below described as "Paradyn") - * on an AS IS basis, and do not warrant its validity or performance. - * We reserve the right to update, modify, or discontinue this - * software at any time. We shall have no obligation to supply such - * updates or modifications or any other form of support to you. - * - * By your use of Paradyn, you understand and agree that we (or any - * other person or entity with proprietary rights in Paradyn) are - * under no obligation to provide either maintenance services, - * update services, notices of latent defects, or correction of - * defects for Paradyn. - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/************************************************************************ - * Pair.h: definition of pairs for dictionaries and sets. -************************************************************************/ - -#if defined(external_templates) -#pragma interface -#endif - -#if !defined(_Pair_h_) -#define _Pair_h_ - -//#ifdef STL... -//#include -//#else - -/************************************************************************ - * template struct pdpair -************************************************************************/ - -// Note that pdpaired classes must provide operator== and operator< - -template -struct pdpair { - public: //needed so nt build doesn't think members are private - T1 first; - T2 second; - - bool operator==(const pdpair& p) { - return (first == p.first) && (second == p.second); - } - bool operator!=(const pdpair& p) { - return !((first == p.first) && (second == p.second)); - } - /* - bool operator<(const pdpair& p) { - return (first < p.first) || (!(p.first < first) && second < p.second); - } - bool operator>(const pdpair& p) { - return (p.first < first) || (!(first < p.first) && p.second < second); - } - */ - pdpair () : first(), second() {} - pdpair (const T1& k) : first(k), second(0) {} - pdpair (const T1& k, const T2& v) : first(k), second(v) {} - pdpair(const pdpair& p) : first(p.first), second(p.second) {} -}; - -// Return a T1 pair containing the min and max elements of a vector of -// type T2. If the vector contains no elements a 0,0 pair is returned. -template -pdpair min_max_pdpair (const T2 & vect) -{ - if (vect.size() == 0) { - T1 def = 0; - return pdpair(def, def); - } - - if (vect.size() == 1) { - return pdpair(vect[0], vect[0]); - } - - T1 min = vect[0]; - T1 max = vect[0]; - - for (unsigned int i = 0; i < vect.size (); i++) { - if (vect[i] < min) - min = vect[i]; - - if (vect[i] > max) - max = vect[i]; - } - - return pdpair(min, max); -} - -//#endif - -#endif /* !defined(_PDPair_h_) */ diff --git a/common/src/SyscallInformation.C b/common/src/SyscallInformation.C index 020480ddb5..03c9b2ad01 100644 --- a/common/src/SyscallInformation.C +++ b/common/src/SyscallInformation.C @@ -1,5 +1,5 @@ /* This file was autogenerated from syscalls/generateSyscallInformation.py */ -#include "dyn_regs.h" +#include "Architecture.h" #include "dyn_syscalls.h" SyscallInformation::SyscallInformation() { diff --git a/common/src/Timer.C b/common/src/Timer.C index 1a2a354cac..39076f5e28 100644 --- a/common/src/Timer.C +++ b/common/src/Timer.C @@ -131,7 +131,6 @@ timer::is_running() const { return (activation_count_ > 0); } - /************************************************************************ @@ -139,13 +138,11 @@ timer::is_running() const { ************************************************************************/ - #undef HAVE_GET_CURRENT_DEFINITION - #if defined(os_windows) #if !defined(HAVE_GET_CURRENT_DEFINITION) @@ -185,7 +182,6 @@ timer::get_current(double& u, double& s, double& w) { #endif /* defined(os_windows) */ - #if !defined(HAVE_GET_CURRENT_DEFINITION) diff --git a/common/src/Timer.h b/common/src/Timer.h index 82e54b0655..fca2f20ffe 100644 --- a/common/src/Timer.h +++ b/common/src/Timer.h @@ -41,8 +41,7 @@ * header files. ************************************************************************/ #include "common/src/headers.h" -#include "common/src/std_namesp.h" - +#include "common/h/util.h" /************************************************************************ * class timer diff --git a/common/src/Types.C b/common/src/Types.C deleted file mode 100644 index 6d8ae68978..0000000000 --- a/common/src/Types.C +++ /dev/null @@ -1,75 +0,0 @@ -/* - * See the dyninst/COPYRIGHT file for copyright information. - * - * We provide the Paradyn Tools (below described as "Paradyn") - * on an AS IS basis, and do not warrant its validity or performance. - * We reserve the right to update, modify, or discontinue this - * software at any time. We shall have no obligation to supply such - * updates or modifications or any other form of support to you. - * - * By your use of Paradyn, you understand and agree that we (or any - * other person or entity with proprietary rights in Paradyn) are - * under no obligation to provide either maintenance services, - * update services, notices of latent defects, or correction of - * defects for Paradyn. - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/************************************************************************ - * $Id: Types.C,v 1.7 2007/05/30 19:20:17 legendre Exp $ - * Types.C: commonly used type-handling functions. -************************************************************************/ - -#include "common/src/Types.h" -#include -#include - -// verify the size of the defined Address type -void Address_chk () -{ - assert (sizeof(Address) == sizeof(void*)); -} - -static const unsigned int _numaddrstrs=8; - // maximum number of addresses per outstanding printf! -static char _addrstr[_numaddrstrs][19]; // "0x"+16+'\0' - -// Format an address string according to the size of the Address type. -// Note that "%x" outputs incorrect/incomplete addresses, and that "%lx" -// or system-dependent "%p" (generally also requiring a typecast to (void*)) -// must be used instead! -char *Address_str (Address addr) -{ - static int i=0; - i=(i+1)%_numaddrstrs; - if (sizeof(Address) == sizeof(int)) - snprintf(_addrstr[i],19,"0x%08X",(unsigned int)addr); - else - snprintf(_addrstr[i],19,"0x%016lX",(unsigned long)addr); - return (_addrstr[i]); -} - - -int ThrIDToTid(Dyninst::THR_ID id) -{ -#if defined(os_windows) - // This is vista-only; for the time being, we'll return the handle as a dword - // return GetThreadId(id); - return (unsigned long) id; -#else - return (int) id; -#endif -} diff --git a/common/src/Types.h b/common/src/Types.h deleted file mode 100644 index 20dbe90d72..0000000000 --- a/common/src/Types.h +++ /dev/null @@ -1,195 +0,0 @@ -/* - * See the dyninst/COPYRIGHT file for copyright information. - * - * We provide the Paradyn Tools (below described as "Paradyn") - * on an AS IS basis, and do not warrant its validity or performance. - * We reserve the right to update, modify, or discontinue this - * software at any time. We shall have no obligation to supply such - * updates or modifications or any other form of support to you. - * - * By your use of Paradyn, you understand and agree that we (or any - * other person or entity with proprietary rights in Paradyn) are - * under no obligation to provide either maintenance services, - * update services, notices of latent defects, or correction of - * defects for Paradyn. - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/************************************************************************ - * $Id: Types.h,v 1.38 2008/08/29 21:45:10 legendre Exp $ - * Types.h: commonly used types (used by runtime libs and other modules) -************************************************************************/ - -#if !defined(_Types_h_) -#define _Types_h_ - -/* Sets up 64 and 32 bit - types: - int64_t uint64_t int32_t uint32_t - constant macros: - I64_C(x) UI64_C(x) - limits: - I64_MAX I64_MIN UI64_MAX - I32_MAX I32_MIN UI32_MAX - - note: needs to be included before anything that includes inttypes.h - (eg. stdio on some systems) -*/ - -/* Set up the 32 AND 64 BIT TYPES ===================================== */ -/* - --- inttypes.h --- - int32_t uint32_t int64_t uint64_t 32B lmts 64Blmts 64BlitMacros# -Linux yes yes yes yes yes yes yes -FreeBSD yes yes yes yes yes yes yes -WindowsNT nonexistant - - # we rename all of the 64 bit literal macros to our shortened name -*/ - -#if defined(os_windows) - typedef signed __int64 int64_t; - typedef signed __int32 int32_t; - typedef signed __int16 int16_t; - typedef signed __int8 int8_t; - typedef unsigned __int64 uint64_t; - typedef unsigned __int32 uint32_t; - typedef unsigned __int16 uint16_t; - typedef unsigned __int8 uint8_t; - -#elif defined(os_linux) -#if !defined(__STDC_CONSTANT_MACROS) -#define __STDC_CONSTANT_MACROS -#endif -#if !defined(__STDC_LIMIT_MACROS) -#define __STDC_LIMIT_MACROS -#endif -#include -#if defined(arch_x86_64) || defined(arch_64bit) -#define TYPE64BIT -#endif -typedef long double double128_t; - -#elif defined(os_freebsd) -#if !defined(__STDC_CONSTANT_MACROS) -#define __STDC_CONSTANT_MACROS -#endif -#if !defined(__STDC_LIMIT_MACROS) -#define __STDC_LIMIT_MACROS -#endif -#include -typedef long double double128_t; - -/* FreeBSD doesn't define this */ -typedef int64_t off64_t; - -#else -#error Unknown architecture -#endif - - -/* Set up the 64 BIT LITERAL MACROS =================================== */ -#if defined(os_windows) - /* nt ----------------------------- */ -#define I64_C(x) (x##i64) -#define UI64_C(x) (x##ui64) -#else /* linux, freebsd ----------------- */ -#define I64_C(x) INT64_C(x) -#define UI64_C(x) UINT64_C(x) -#endif - -/* Set up the 32 and 64 BIT LIMITS for those not already set up ======= */ -#if defined(os_windows) - /* nt ----------------------------- */ -#include -#define I64_MAX _I64_MAX -#define UI64_MAX _UI64_MAX -#define I64_MIN _I64_MIN -#define I32_MAX _I32_MAX -#define I32_MIN _I32_MIN -#define UI32_MAX _UI32_MAX -#else /* linux, freebsd ----------------- */ -#define I64_MAX INT64_MAX -#define UI64_MAX UINT64_MAX -#define I64_MIN INT64_MIN -#define I32_MAX INT32_MAX -#define I32_MIN INT32_MIN -#define UI32_MAX UINT32_MAX -#endif - - /* -typedef int64_t time64; -*/ - -#if defined(__cplusplus) -#include "common/h/dyntypes.h" -using namespace Dyninst; -static const Address ADDR_NULL = (Address)(0); -#else -#define ADDR_NULL (0) -typedef unsigned long Address; -#endif -/* Note the inherent assumption that the size of a "long" integer matches - that of an address (void*) on every supported Paradyn/Dyninst system! - (This can be checked with Address_chk().) -*/ - -typedef unsigned int Word; - -typedef long long int RegValue; /* register content 64-bit */ -/* This needs to be an int since it is sometimes used to pass offsets - to the code generator (i.e. if-statement) - jkh 5/24/99 */ -typedef unsigned int Register; /* a register number, e.g., [0..31] */ -static const Register Null_Register = (Register)(-1); /* '255' */ -/* Easily noticeable name... */ -static const Register REG_NULL = (Register)(-1); - -// Virtual Memory Map -- shared between platforms -#define PREMS_PRIVATE (1 << 4) -#define PREMS_SHARED (1 << 3) -#define PREMS_READ (1 << 2) -#define PREMS_WRITE (1 << 1) -#define PREMS_EXEC (1 << 0) - -#define MAPENTRIES_PATH_SIZE 512 -#define MAPENTRIES_PATH_SIZE_STR "512" -typedef struct maps_entries { - Address start; - Address end; - unsigned prems; - Address offset; - int dev_major; - int dev_minor; - unsigned long inode; - char path[MAPENTRIES_PATH_SIZE]; -} map_entries; - -#ifdef __cplusplus - -#include "common/h/util.h" - -COMMON_EXPORT void Address_chk (); -COMMON_EXPORT char *Address_str (Address addr); - -// NB: this is probably inappropriate for 64-bit addresses! -inline unsigned hash_address(const Address& addr) { - return (unsigned) ((addr >> 2) & 0xffffffff); -} -#endif /* __cplusplus */ - -#endif /* !defined(_Types_h_) */ - - diff --git a/common/src/addrtranslate-freebsd.C b/common/src/addrtranslate-freebsd.C index 91dd74eddf..12bd29c5cd 100644 --- a/common/src/addrtranslate-freebsd.C +++ b/common/src/addrtranslate-freebsd.C @@ -31,7 +31,7 @@ #include "common/src/headers.h" #include "common/src/addrtranslate-sysv.h" #include "common/src/freebsdKludges.h" - +#include "common/src/vm_maps.h" #include #include diff --git a/common/src/addrtranslate-linux.C b/common/src/addrtranslate-linux.C index 318c814e9f..0750f2b4b1 100644 --- a/common/src/addrtranslate-linux.C +++ b/common/src/addrtranslate-linux.C @@ -189,7 +189,7 @@ string AddressTranslateSysV::getExecName() if (exec_name.empty()) { char name[64]; snprintf(name, 64, "/proc/%d/exe", pid); - exec_name = std::move(resolve_file_path(name)); + exec_name = resolve_file_path(name); } return exec_name; } diff --git a/common/src/addrtranslate-sysv.C b/common/src/addrtranslate-sysv.C index 49e2bb84e2..3e93370f0f 100644 --- a/common/src/addrtranslate-sysv.C +++ b/common/src/addrtranslate-sysv.C @@ -28,6 +28,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include #include #include @@ -50,7 +51,7 @@ #include "common/src/parseauxv.h" #include "common/src/headers.h" #include "common/src/pathName.h" - +#include "common/src/vm_maps.h" #include "common/src/addrtranslate.h" #include "common/src/addrtranslate-sysv.h" @@ -866,7 +867,7 @@ FCNode::FCNode(string f, dev_t d, ino_t i, SymbolReaderFactory *factory_) : symreader(NULL), factory(factory_) { - filename = std::move(resolve_file_path(std::move(f))); + filename = resolve_file_path(std::move(f)); } string FCNode::getFilename() { @@ -1043,16 +1044,25 @@ Address AddressTranslateSysV::adjustForAddrSpaceWrap(Address base, std::string n lseek(fd, 0, SEEK_SET); Elf32_Ehdr e_hdr; - if (read(fd, &e_hdr, sizeof(e_hdr)) != sizeof(e_hdr)) return base; + if (read(fd, &e_hdr, sizeof(e_hdr)) != sizeof(e_hdr)) { + close(fd); + return base; + } - if (e_hdr.e_phoff == 0) return base; + if (e_hdr.e_phoff == 0) { + close(fd); + return base; + } lseek(fd, e_hdr.e_phoff, SEEK_SET); Address codeOffset = 0; while (true) { Elf32_Phdr p_hdr; - if (read(fd, &p_hdr, sizeof(p_hdr)) != sizeof(p_hdr)) return base; + if (read(fd, &p_hdr, sizeof(p_hdr)) != sizeof(p_hdr)) { + close(fd); + return base; + } Address p_vaddr = p_hdr.p_vaddr; unsigned type = p_hdr.p_type; diff --git a/common/src/addrtranslate-sysv.h b/common/src/addrtranslate-sysv.h index f787b3831a..6cbda44c9c 100644 --- a/common/src/addrtranslate-sysv.h +++ b/common/src/addrtranslate-sysv.h @@ -31,6 +31,9 @@ #if !defined(addrtranslate_sysv_h_) #define addrtranslate_sysv_h_ +#include +#include +#include #include "common/src/addrtranslate.h" namespace Dyninst { diff --git a/common/src/addrtranslate-win.C b/common/src/addrtranslate-win.C index f22ff96e54..9c7a718a2f 100644 --- a/common/src/addrtranslate-win.C +++ b/common/src/addrtranslate-win.C @@ -96,7 +96,7 @@ void printSysError(unsigned errNo) { fprintf(stderr, "Couldn't print error message\n"); printSysError(GetLastError()); } - fprintf(stderr, "*** System error [%d]: %s\n", errNo, buf); + fprintf(stderr, "*** System error [%u]: %s\n", errNo, buf); fflush(stderr); } @@ -165,7 +165,7 @@ AddressTranslateWin::AddressTranslateWin(PID pid, PROC_HANDLE phandle_) : AddressTranslate(pid, phandle_), no_proc(false) { - init(); + AddressTranslateWin::init(); } Address AddressTranslateWin::getLibraryTrapAddrSysV() diff --git a/common/src/addrtranslate.h b/common/src/addrtranslate.h index cf5c57993c..1ab31597a3 100644 --- a/common/src/addrtranslate.h +++ b/common/src/addrtranslate.h @@ -36,7 +36,6 @@ #include #include -#include "common/src/Types.h" #include "common/h/dyntypes.h" #include "common/h/SymReader.h" #include "common/h/ProcReader.h" diff --git a/common/src/arch-aarch64.C b/common/src/arch-aarch64.C index e6ea542694..13586c3e0e 100644 --- a/common/src/arch-aarch64.C +++ b/common/src/arch-aarch64.C @@ -28,8 +28,8 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "common/src/Types.h" #include "common/src/arch-aarch64.h" +#include "unaligned_memory_access.h" namespace NS_aarch64 { @@ -76,7 +76,7 @@ unsigned instruction::getTargetReg() const { return -1; } -Address instruction::getTarget(Address addr) const { +Dyninst::Address instruction::getTarget(Dyninst::Address addr) const { if (isUncondBranch() || isCondBranch()) { return getBranchOffset() + addr; } @@ -85,7 +85,7 @@ Address instruction::getTarget(Address addr) const { } // TODO: argument _needs_ to be an int, or ABS() doesn't work. -void instruction::setBranchOffset(Address /*newOffset*/) { +void instruction::setBranchOffset(Dyninst::Address /*newOffset*/) { assert(0); } @@ -97,14 +97,13 @@ bool instruction::isCall() const return false; } -void instruction::setInstruction(codeBuf_t * /*ptr*/, Address) { +void instruction::setInstruction(codeBuf_t * /*ptr*/, Dyninst::Address) { assert(0); } -void instruction::setInstruction(unsigned char *ptr, Address) { +void instruction::setInstruction(unsigned char *ptr, Dyninst::Address) { // We don't need the addr on this platform - instructUnion *insnPtr = (instructUnion *)ptr; - insn_ = *insnPtr; + insn_ = Dyninst::read_memory_as(ptr); } bool instruction::isBranchReg() const{ @@ -129,13 +128,13 @@ bool instruction::isCondBranch() const { return false; } -unsigned instruction::jumpSize(Address /*from*/, Address /*to*/, unsigned /*addr_width*/) { +unsigned instruction::jumpSize(Dyninst::Address /*from*/, Dyninst::Address /*to*/, unsigned /*addr_width*/) { assert(0); return -1; } // -1 is infinite, don't ya know. -unsigned instruction::jumpSize(Address /*disp*/, unsigned /*addr_width*/) { +unsigned instruction::jumpSize(Dyninst::Address /*disp*/, unsigned /*addr_width*/) { assert(0); return instruction::size(); } @@ -197,7 +196,7 @@ unsigned instruction::getBranchTargetReg() const{ return -1; } -Address instruction::getBranchOffset() const { +Dyninst::Address instruction::getBranchOffset() const { if (isUncondBranch()) { if( CHECK_INST(UNCOND_BR.IMM) ){ return signExtend(GET_OFFSET32(UNCOND_BR.IMM), 26+2 ); diff --git a/common/src/arch-aarch64.h b/common/src/arch-aarch64.h index a1a5278f3e..fd1546166f 100644 --- a/common/src/arch-aarch64.h +++ b/common/src/arch-aarch64.h @@ -35,8 +35,9 @@ // Code generation -#include "common/src/Types.h" -#include "common/h/dyn_regs.h" +#include "dyntypes.h" +#include "registers/aarch64_regs.h" +#include #include class AddressSpace; @@ -204,7 +205,7 @@ class COMMON_EXPORT instruction { instruction *copy() const; void clear() { insn_.raw = 0; } - void setInstruction(codeBuf_t *ptr, Address = 0); + void setInstruction(codeBuf_t *ptr, Dyninst::Address = 0); void setBits(unsigned int pos, unsigned int len, unsigned int value) { unsigned int mask; @@ -218,7 +219,7 @@ class COMMON_EXPORT instruction { insn_.raw = insn_.raw | value; } unsigned int asInt() const { return insn_.raw; } - void setInstruction(unsigned char *ptr, Address = 0); + void setInstruction(unsigned char *ptr, Dyninst::Address = 0); // To solve host/target endian mismatches @@ -228,14 +229,14 @@ class COMMON_EXPORT instruction { // We need instruction::size() all _over_ the place. static unsigned size() { return sizeof(instructUnion); } - Address getBranchOffset() const; - Address getBranchTargetAddress() const; - void setBranchOffset(Address newOffset); + Dyninst::Address getBranchOffset() const; + Dyninst::Address getBranchTargetAddress() const; + void setBranchOffset(Dyninst::Address newOffset); // And tell us how much space we'll need... // Returns -1 if we can't do a branch due to architecture limitations - static unsigned jumpSize(Address from, Address to, unsigned addr_width); - static unsigned jumpSize(Address disp, unsigned addr_width); + static unsigned jumpSize(Dyninst::Address from, Dyninst::Address to, unsigned addr_width); + static unsigned jumpSize(Dyninst::Address disp, unsigned addr_width); static unsigned maxJumpSize(unsigned addr_width); static unsigned maxInterFunctionJumpSize(unsigned addr_width); @@ -260,7 +261,7 @@ class COMMON_EXPORT instruction { return ((insn_.raw & mask) == match); } - Address getTarget(Address insnAddr) const; + Dyninst::Address getTarget(Dyninst::Address insnAddr) const; unsigned spaceToRelocate() const; bool getUsedRegs(std::vector ®s); @@ -272,7 +273,7 @@ class COMMON_EXPORT instruction { bool isCall() const; - static bool isAligned(Address addr) { + static bool isAligned(Dyninst::Address addr) { return !(addr & 0x3); } diff --git a/common/src/arch-power.C b/common/src/arch-power.C index bfa65adece..ccfc4c515a 100644 --- a/common/src/arch-power.C +++ b/common/src/arch-power.C @@ -28,8 +28,8 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "common/src/Types.h" #include "common/src/arch-power.h" +#include "unaligned_memory_access.h" #include using namespace NS_power; @@ -72,7 +72,7 @@ instruction *instruction::copy() const { return new instruction(*this); } -Address instruction::getTarget(Address addr) const { +Dyninst::Address instruction::getTarget(Dyninst::Address addr) const { if (isUncondBranch() || isCondBranch()) { return getBranchOffset() + addr; } @@ -85,7 +85,7 @@ Address instruction::getTarget(Address addr) const { } // TODO: argument _needs_ to be an int, or ABS() doesn't work. -void instruction::setBranchOffset(Address newOffset) { +void instruction::setBranchOffset(Dyninst::Address newOffset) { if (isUncondBranch()) { assert(ABS((int) newOffset) < MAX_BRANCH); IFORM_LI_SET(*this, newOffset >> 2); @@ -110,16 +110,15 @@ bool instruction::isCall() const return(isInsnType(OPmask | AALKmask, CALLmatch)); } -void instruction::setInstruction(codeBuf_t *ptr, Address) { +void instruction::setInstruction(codeBuf_t *ptr, Dyninst::Address) { // We don't need the addr on this platform instructUnion *insnPtr = (instructUnion *)ptr; insn_.raw = (*insnPtr).raw; } -void instruction::setInstruction(unsigned char *ptr, Address) { +void instruction::setInstruction(unsigned char *ptr, Dyninst::Address) { // We don't need the addr on this platform - instructUnion *insnPtr = (instructUnion *)ptr; - insn_ = *insnPtr; + insn_ = Dyninst::read_memory_as(ptr); } bool instruction::isUncondBranch() const { @@ -130,13 +129,13 @@ bool instruction::isCondBranch() const { return isInsnType(Bmask, BCmatch); } -unsigned instruction::jumpSize(Address from, Address to, unsigned addr_width) { - Address disp = ABS((long)(to - from)); +unsigned instruction::jumpSize(Dyninst::Address from, Dyninst::Address to, unsigned addr_width) { + Dyninst::Address disp = ABS((long)(to - from)); return jumpSize(disp, addr_width); } // -1 is infinite, don't ya know. -unsigned instruction::jumpSize(Address disp, unsigned addr_width) { +unsigned instruction::jumpSize(Dyninst::Address disp, unsigned addr_width) { if (ABS(disp) >= MAX_BRANCH) { return maxInterFunctionJumpSize(addr_width); } @@ -244,7 +243,7 @@ bool instruction::isThunk() const { return true; } -Address instruction::getBranchOffset() const { +Dyninst::Address instruction::getBranchOffset() const { if (isUncondBranch()) { return (IFORM_LI(*this) << 2); } diff --git a/common/src/arch-power.h b/common/src/arch-power.h index 1629c49480..149a3d6c6f 100644 --- a/common/src/arch-power.h +++ b/common/src/arch-power.h @@ -35,8 +35,8 @@ // Code generation -#include "common/src/Types.h" -#include "dyn_regs.h" +#include "registers/ppc32_regs.h" +#include "registers/ppc64_regs.h" #include class AddressSpace; @@ -812,7 +812,7 @@ class COMMON_EXPORT instruction { instruction *copy() const; void clear() { insn_.raw = 0; } - void setInstruction(codeBuf_t *ptr, Address = 0); + void setInstruction(codeBuf_t *ptr, Dyninst::Address = 0); void setBits(unsigned int pos, unsigned int len, unsigned int value) { unsigned int mask; @@ -826,7 +826,7 @@ class COMMON_EXPORT instruction { insn_.raw = insn_.raw | value; } unsigned int asInt() const { return insn_.raw; } - void setInstruction(unsigned char *ptr, Address = 0); + void setInstruction(unsigned char *ptr, Dyninst::Address = 0); // To solve host/target endian mismatches @@ -836,13 +836,13 @@ class COMMON_EXPORT instruction { // We need instruction::size() all _over_ the place. static unsigned size() { return sizeof(instructUnion); } - Address getBranchOffset() const; - void setBranchOffset(Address newOffset); + Dyninst::Address getBranchOffset() const; + void setBranchOffset(Dyninst::Address newOffset); // And tell us how much space we'll need... // Returns -1 if we can't do a branch due to architecture limitations - static unsigned jumpSize(Address from, Address to, unsigned addr_width); - static unsigned jumpSize(Address disp, unsigned addr_width); + static unsigned jumpSize(Dyninst::Address from, Dyninst::Address to, unsigned addr_width); + static unsigned jumpSize(Dyninst::Address disp, unsigned addr_width); static unsigned maxJumpSize(unsigned addr_width); static unsigned maxInterFunctionJumpSize(unsigned addr_width); @@ -867,7 +867,7 @@ class COMMON_EXPORT instruction { return ((insn_.raw & mask) == match); } - Address getTarget(Address insnAddr) const; + Dyninst::Address getTarget(Dyninst::Address insnAddr) const; unsigned spaceToRelocate() const; bool getUsedRegs(std::vector ®s); @@ -889,7 +889,7 @@ class COMMON_EXPORT instruction { bool isCall() const; - static bool isAligned(Address addr) { + static bool isAligned(Dyninst::Address addr) { return !(addr & 0x3); } diff --git a/common/src/arch-x86.C b/common/src/arch-x86.C index d955d4d0ba..49db100a61 100644 --- a/common/src/arch-x86.C +++ b/common/src/arch-x86.C @@ -129,11 +129,9 @@ // This include *really must* come first in the file. +#include #include "common/src/vgannotations.h" -// This include *must* come first in the file. -#include "common/src/Types.h" - #include #include #include @@ -141,20 +139,24 @@ #include #include // once_flag, call_once -#include "boost/assign/list_of.hpp" -#include "boost/assign/std/vector.hpp" -#include "boost/assign/std/set.hpp" -#include -#include +#include "dyncompat/assign/list_of.hpp" +#include "dyncompat/assign/std/vector.hpp" +#include "dyncompat/assign/std/set.hpp" +#include +#include #include "common/src/arch-x86.h" -#include "dyn_regs.h" +#include "registers/x86_regs.h" +#include "registers/x86_64_regs.h" #include "compiler_annotations.h" +#include "unaligned_memory_access.h" +#include // #define VEX_DEBUG // #define VEX_PEDANTIC using namespace std; -using namespace boost::assign; +using namespace dyncompat::assign; +using namespace Dyninst; namespace NS_x86 { @@ -885,7 +887,7 @@ COMMON_EXPORT dyn_hash_map entryNames_IAPI = map_list_of (e_aesdeclast, "aesdeclast") (e_aeskeygenassist, "aeskeygenassist") (e_aesimc, "aesimc") - (e_pclmullqlqdq, "pclmullqlqdq") + (e_pclmulqdq, "pclmulqdq") (e_and, "and") (e_andnpd, "andnpd") (e_andnps, "andnps") @@ -915,29 +917,28 @@ COMMON_EXPORT dyn_hash_map entryNames_IAPI = map_list_of (e_cmc, "cmc") (e_cmovbe, "cmovbe") (e_cmove, "cmove") - (e_cmovnae, "cmovnae") - (e_cmovnb, "cmovnb") - (e_cmovnbe, "cmovnbe") + (e_cmovb, "cmovb") + (e_cmovae, "cmovae") + (e_cmova, "cmova") (e_cmovne, "cmovne") - (e_cmovng, "cmovng") - (e_cmovnge, "cmovnge") - (e_cmovnl, "cmovnl") + (e_cmovle, "cmovle") + (e_cmovl, "cmovl") + (e_cmovge, "cmovge") (e_cmovno, "cmovno") (e_cmovns, "cmovns") (e_cmovo, "cmovo") - (e_cmovpe, "cmovpe") - (e_cmovpo, "cmovpo") + (e_cmovp, "cmovp") + (e_cmovnp, "cmovnp") (e_cmovs, "cmovs") (e_cmp, "cmp") (e_cmppd, "cmppd") (e_cmpps, "cmpps") (e_cmpsb, "cmpsb") (e_cmpsd, "cmpsd") - (e_cmpsd_sse, "cmpsd") (e_cmpss, "cmpss") (e_cmpsw, "cmpsw") - (e_cmpxch, "cmpxch") - (e_cmpxch8b, "cmpxch8b") + (e_cmpxchg, "cmpxchg") + (e_cmpxchg8b, "cmpxchg8b") (e_comisd, "comisd") (e_comiss, "comiss") (e_cpuid, "cpuid") @@ -978,6 +979,8 @@ COMMON_EXPORT dyn_hash_map entryNames_IAPI = map_list_of (e_vdppd, "vdppd") (e_dpps, "dpps") (e_emms, "emms") + (e_endbr32, "endbr32") + (e_endbr64, "endbr64") (e_enter, "enter") (e_extractps, "extractps") (e_extrq, "extrq") @@ -997,7 +1000,7 @@ COMMON_EXPORT dyn_hash_map entryNames_IAPI = map_list_of (e_fcmovnbe, "fcmovnbe") (e_fcom, "fcom") (e_fcomi, "fcomi") - (e_fcomip, "fcomip") + (e_fcompi, "fcompi") (e_fcomp, "fcomp") (e_fcompp, "fcompp") (e_fdiv, "fdiv") @@ -1028,12 +1031,12 @@ COMMON_EXPORT dyn_hash_map entryNames_IAPI = map_list_of (e_fnop, "fnop") (e_fprem, "fprem") (e_frstor, "frstor") - (e_fsave, "fsave") + (e_fnsave, "fnsave") (e_fst, "fst") - (e_fstcw, "fstcw") - (e_fstenv, "fstenv") + (e_fnstcw, "fnstcw") + (e_fnstenv, "fnstenv") (e_fstp, "fstp") - (e_fstsw, "fstsw") + (e_fnstsw, "fnstsw") (e_fsub, "fsub") (e_fsubp, "fsubp") (e_fsubr, "fsubr") @@ -1041,7 +1044,7 @@ COMMON_EXPORT dyn_hash_map entryNames_IAPI = map_list_of (e_fucom, "fucom") (e_fucomp, "fucomp") (e_fucomi, "fucomi") - (e_fucomip, "fucomip") + (e_fucompi, "fucompi") (e_fucompp, "fucompp") (e_fxch, "fxch") (e_fxrstor, "fxrstor") @@ -1082,19 +1085,19 @@ COMMON_EXPORT dyn_hash_map entryNames_IAPI = map_list_of (e_jl, "jl") (e_jle, "jle") (e_jmp, "jmp") - (e_jnb, "jnb") + (e_jae, "jae") (e_jnb_jae_j, "jnb") - (e_jnbe, "jnbe") - (e_jnl, "jnl") - (e_jnle, "jnle") + (e_ja, "ja") + (e_jge, "jge") + (e_jg, "jg") (e_jno, "jno") (e_jnp, "jnp") (e_jns, "jns") - (e_jnz, "jnz") + (e_jne, "jne") (e_jo, "jo") (e_jp, "jp") (e_js, "js") - (e_jz, "jz") + (e_je, "je") (e_lahf, "lahf") (e_lar, "lar") (e_ldmxcsr, "ldmxcsr") @@ -1115,7 +1118,7 @@ COMMON_EXPORT dyn_hash_map entryNames_IAPI = map_list_of (e_lodsw, "lodsw") (e_loop, "loop") (e_loope, "loope") - (e_loopn, "loopn") + (e_loopne, "loopne") (e_lsl, "lsl") (e_lss, "lss") (e_ltr, "ltr") @@ -1130,7 +1133,6 @@ COMMON_EXPORT dyn_hash_map entryNames_IAPI = map_list_of (e_minps, "minps") (e_minsd, "minsd") (e_minss, "minss") - (e_mmxud, "mmxud") (e_mov, "mov") (e_movapd, "movapd") (e_movaps, "movaps") @@ -1161,7 +1163,6 @@ COMMON_EXPORT dyn_hash_map entryNames_IAPI = map_list_of (e_movsd_sse, "movsd") (e_movshdup, "movshdup") (e_movsldup, "movsldup") - (e_movslq, "movslq") (e_movss, "movss") (e_movsw, "movsw") (e_movsx, "movsx") @@ -1213,7 +1214,7 @@ COMMON_EXPORT dyn_hash_map entryNames_IAPI = map_list_of (e_pcmpeqw, "pcmpeqw") (e_pcmpestri, "pcmpestri") (e_pcmpestrm, "pcmpestrm") - (e_pcmpgdt, "pcmpgdt") + (e_pcmpgtd, "pcmpgtd") (e_pcmpgtb, "pcmpgtb") (e_pcmpgtq, "pcmpgtq") (e_pcmpgtw, "pcmpgtw") @@ -1229,7 +1230,6 @@ COMMON_EXPORT dyn_hash_map entryNames_IAPI = map_list_of (e_phsubd, "phsubd") (e_phsubsw, "phsubsw") (e_phsubw, "phsubw") - (e_phsubsw, "phsubsw") (e_pinsrb, "pinsrb") (e_pinsrd_pinsrq, "pinsrd/pinsrq") (e_pinsrw, "pinsrw") @@ -1268,18 +1268,18 @@ COMMON_EXPORT dyn_hash_map entryNames_IAPI = map_list_of (e_pmulld, "pmulld") (e_pmuludq, "pmuludq") (e_pop, "pop") - (e_popa, "popa") - (e_popad, "popad") + (e_popal, "popa") + (e_popaw, "popad") (e_popcnt, "popcnt") (e_popf, "popf") (e_popfd, "popfd") (e_por, "por") (e_prefetch, "prefetch") - (e_prefetchNTA, "prefetchNTA") - (e_prefetchT0, "prefetchT0") - (e_prefetchT1, "prefetchT1") - (e_prefetchT2, "prefetchT2") - (e_prefetch_w, "prefetch(w)") + (e_prefetchnta, "prefetchnta") + (e_prefetcht0, "prefetcht0") + (e_prefetcht1, "prefetchT1") + (e_prefetcht2, "prefetchT2") + (e_prefetch_w, "prefetchw") (e_prefetchw, "prefetchw") (e_prefetchwt1, "prefetchwt1") (e_psadbw, "psadbw") @@ -1311,17 +1311,15 @@ COMMON_EXPORT dyn_hash_map entryNames_IAPI = map_list_of (e_ptest, "ptest") (e_punpckhbw, "punpckhbw") (e_punpckhdq, "punpckhdq") - (e_punpckhqd, "punpckhqd") + (e_punpckhqdq, "punpckhqdq") (e_punpckhwd, "punpckhwd") (e_punpcklbw, "punpcklbw") - (e_punpcklqd, "punpcklqd") - (e_punpcklqld, "punpcklqld") + (e_punpckldq, "punpckldq") + (e_punpcklqdq, "punpcklqdq") (e_punpcklwd, "punpcklwd") (e_push, "push") - (e_pusha, "pusha") - (e_pushad, "pushad") + (e_pushal, "pusha") (e_pushf, "pushf") - (e_pushfd, "pushfd") (e_pxor, "pxor") (e_rcl, "rcl") (e_rcpps, "rcpps") @@ -1353,21 +1351,21 @@ COMMON_EXPORT dyn_hash_map entryNames_IAPI = map_list_of (e_setbe, "setbe") (e_setl, "setl") (e_setle, "setle") - (e_setnb, "setnb") - (e_setnbe, "setnbe") - (e_setnl, "setnl") - (e_setnle, "setnle") + (e_setae, "setae") + (e_seta, "seta") + (e_setge, "setge") + (e_setg, "setg") (e_setno, "setno") (e_setnp, "setnp") (e_setns, "setns") - (e_setnz, "setnz") + (e_setne, "setne") (e_seto, "seto") (e_setp, "setp") (e_sets, "sets") - (e_setz, "setz") + (e_sete, "sete") (e_sfence, "sfence") (e_sgdt, "sgdt") - (e_shl_sal, "shl/sal") + (e_shl, "shl") (e_shld, "shld") (e_shr, "shr") (e_shrd, "shrd") @@ -1380,12 +1378,9 @@ COMMON_EXPORT dyn_hash_map entryNames_IAPI = map_list_of (e_sha256rnds2, "sha256rnds2") (e_sha256msg1, "sha256msg1") (e_sha256msg2, "sha256msg2") - (e_shlx, "shlx") (e_sarx, "sarx") - (e_prefetchwt1, "prefetchwt1") (e_clflushopt, "clflushopt") (e_clwb, "clwb") - (e_pcommit, "pcommit") (e_sidt, "sidt") (e_sldt, "sldt") (e_smsw, "smsw") @@ -1426,7 +1421,7 @@ COMMON_EXPORT dyn_hash_map entryNames_IAPI = map_list_of (e_wrmsr, "wrmsr") (e_xadd, "xadd") (e_xchg, "xchg") - (e_xlat, "xlat") + (e_xlatb, "xlatb") (e_xor, "xor") (e_xorpd, "xorpd") (e_xorps, "xorps") @@ -1436,14 +1431,14 @@ COMMON_EXPORT dyn_hash_map entryNames_IAPI = map_list_of (e_vaesdeclast, "vaesdeclast") (e_vaeskeygenassist, "vaeskeygenassist") (e_vaesimc, "vaesimc") - (e_vpclmullqlqdq, "vpclmullqlqdq") - (e_vpperm, "e_vpperm") + (e_vpclmulqdq, "vpclmulqdq") + (e_vpperm, "vpperm") (e_vmpsadbw, "vmpsadbw") (e_vmwrite, "vmwrite") (e_vmread, "vmread") (e_vphaddw, "vphaddw") (e_vphaddd, "vphaddd") - (e_vphaddsw, "vpaddsw") + (e_vphaddsw, "vphaddsw") (e_vphsubw, "vphsubw") (e_vphsubd, "vphsubd") (e_vpmovb2m, "vpmovb2m") @@ -1464,7 +1459,6 @@ COMMON_EXPORT dyn_hash_map entryNames_IAPI = map_list_of (e_pdep, "pdep") (e_pext, "pext") (e_rorx, "rorx") - (e_sarx, "sarx") (e_shlx, "shlx") (e_shrx, "shrx") (e_tzcnt, "tzcnt") @@ -1485,9 +1479,8 @@ COMMON_EXPORT dyn_hash_map entryNames_IAPI = map_list_of (e_vblendmps, "vblendmps") (e_vblendmpd, "vblendmpd") (e_vblendps, "vblendps") - (e_vblendvpd, "vblendpd") - (e_vblendvps, "vblendvps") (e_vblendvpd, "vblendvpd") + (e_vblendvps, "vblendvps") (e_vpblendmb, "vpblendmb") (e_vpblendmw, "vpblendmw") (e_vpblendvb, "vpblendvb") @@ -1736,7 +1729,6 @@ COMMON_EXPORT dyn_hash_map entryNames_IAPI = map_list_of (e_vpcmov, "vpcmov") (e_vpcmpub, "vpcmpub") (e_vpcmpb, "vpcmpb") - (e_vpcmpequd, "vpcmpequd") (e_vpcmpeqb, "vpcmpeqb") (e_vpcmpeqd, "vpcmpeqd") (e_vpcmpeqq, "vpcmpeqq") @@ -1745,7 +1737,7 @@ COMMON_EXPORT dyn_hash_map entryNames_IAPI = map_list_of (e_vpcmpgtd, "vpcmpgtd") (e_vpcmpgtq, "vpcmpgtq") (e_vpcmpgtw, "vpcmpgtw") - (e_vpcomd, "vpcmod") + (e_vpcomd, "vpcomd") (e_vpcompressd, "vpcompressd") (e_vpcompressq, "vpcompressq") (e_vpconflictd, "vpconflictd") @@ -1788,8 +1780,6 @@ COMMON_EXPORT dyn_hash_map entryNames_IAPI = map_list_of (e_vpinsrd, "vpinsrd") (e_vpinsrq, "vpinsrq") (e_vpinsrw, "vpinsrw") - (e_vpmaddubsw, "vpmaddubsw") - (e_vpmaddwd, "vpmaddwd") (e_vpmaskmovd, "vpmaskmovd") (e_vpmaskmovq, "vpmaskmovq") (e_vpmaxsq, "vpmaxsq") @@ -1836,8 +1826,8 @@ COMMON_EXPORT dyn_hash_map entryNames_IAPI = map_list_of (e_vpor, "vpor") (e_vpord, "vpord") (e_vporq, "vporq") - (e_vprolvd, "vporlvd") - (e_vprolvq, "vporlvq") + (e_vprolvd, "vprolvd") + (e_vprolvq, "vprolvq") (e_vprold, "vprold") (e_vprolq, "vprolq") (e_vprorvd, "vprorvd") @@ -1875,7 +1865,6 @@ COMMON_EXPORT dyn_hash_map entryNames_IAPI = map_list_of (e_vpsrld, "vpsrld") (e_vpsrlq, "vpsrlq") (e_vpsrlvd, "vpsrlvd") - (e_vpsrlvq, "vprlvq") (e_vpsrlvq, "vpsrlvq") (e_vpsrlw, "vpsrlw") (e_vpsubb, "vpsubb") @@ -1989,10 +1978,6 @@ COMMON_EXPORT dyn_hash_map entryNames_IAPI = map_list_of (e_ktestd, "ktestd") (e_ktestw, "ktestw") (e_ktestq, "ktestq") - (e_vcmppd, "vcmppd") - (e_vcmpps, "vcmpps") - (e_vcmpsd, "vcmpsd") - (e_vcmpss, "vcmpss") (e_vmovntpd, "vmovntpd") (e_vcvttsd2usi, "vcvttsd2usi") (e_vcvttss2usi, "vcvttss2usi") @@ -2031,14 +2016,6 @@ COMMON_EXPORT dyn_hash_map entryNames_IAPI = map_list_of (e_vdbpsadbw, "vdbpsadbw") (e_vphsubsw, "vphsubsw") -/* What are these? */ - (e_vpmovswb, "vpmovswb") - (e_vpmovsdb, "vpmovsdb") - (e_vpmovsqb, "vpmovsqb") - (e_vpmovsdw, "vpmovsdw") - (e_vpmovsqw, "vpmovsqw") - (e_vpmovsqd, "vpmovsqd") - (e_fp_generic, "[FIXME: GENERIC FPU INSN]") (e_3dnow_generic, "[FIXME: GENERIC 3DNow INSN]") (e_No_Entry, "No_Entry") @@ -2087,26 +2064,26 @@ void ia32_instruction::initFlagTable(dyn_hash_map& flagTable_ flagTable_[e_cmc] = flagInfo(vector(), list_of(x86::cf)); flagTable_[e_cmovbe] = flagInfo(list_of(x86::of)(x86::sf)(x86::zf)(x86::pf)(x86::cf), vector()); flagTable_[e_cmove] = flagInfo(list_of(x86::of)(x86::sf)(x86::zf)(x86::pf)(x86::cf), vector()); - flagTable_[e_cmovnae] = flagInfo(list_of(x86::of)(x86::sf)(x86::zf)(x86::pf)(x86::cf), vector()); - flagTable_[e_cmovnb] = flagInfo(list_of(x86::of)(x86::sf)(x86::zf)(x86::pf)(x86::cf), vector()); - flagTable_[e_cmovnbe] = flagInfo(list_of(x86::of)(x86::sf)(x86::zf)(x86::pf)(x86::cf), vector()); + flagTable_[e_cmovb] = flagInfo(list_of(x86::of)(x86::sf)(x86::zf)(x86::pf)(x86::cf), vector()); + flagTable_[e_cmovae] = flagInfo(list_of(x86::of)(x86::sf)(x86::zf)(x86::pf)(x86::cf), vector()); + flagTable_[e_cmova] = flagInfo(list_of(x86::of)(x86::sf)(x86::zf)(x86::pf)(x86::cf), vector()); flagTable_[e_cmovne] = flagInfo(list_of(x86::of)(x86::sf)(x86::zf)(x86::pf)(x86::cf), vector()); - flagTable_[e_cmovng] = flagInfo(list_of(x86::of)(x86::sf)(x86::zf)(x86::pf)(x86::cf), vector()); - flagTable_[e_cmovnge] = flagInfo(list_of(x86::of)(x86::sf)(x86::zf)(x86::pf)(x86::cf), vector()); - flagTable_[e_cmovnl] = flagInfo(list_of(x86::of)(x86::sf)(x86::zf)(x86::pf)(x86::cf), vector()); + flagTable_[e_cmovle] = flagInfo(list_of(x86::of)(x86::sf)(x86::zf)(x86::pf)(x86::cf), vector()); + flagTable_[e_cmovl] = flagInfo(list_of(x86::of)(x86::sf)(x86::zf)(x86::pf)(x86::cf), vector()); + flagTable_[e_cmovge] = flagInfo(list_of(x86::of)(x86::sf)(x86::zf)(x86::pf)(x86::cf), vector()); flagTable_[e_cmovno] = flagInfo(list_of(x86::of)(x86::sf)(x86::zf)(x86::pf)(x86::cf), vector()); flagTable_[e_cmovns] = flagInfo(list_of(x86::of)(x86::sf)(x86::zf)(x86::pf)(x86::cf), vector()); flagTable_[e_cmovo] = flagInfo(list_of(x86::of)(x86::sf)(x86::zf)(x86::pf)(x86::cf), vector()); - flagTable_[e_cmovpe] = flagInfo(list_of(x86::of)(x86::sf)(x86::zf)(x86::pf)(x86::cf), vector()); - flagTable_[e_cmovpo] = flagInfo(list_of(x86::of)(x86::sf)(x86::zf)(x86::pf)(x86::cf), vector()); + flagTable_[e_cmovp] = flagInfo(list_of(x86::of)(x86::sf)(x86::zf)(x86::pf)(x86::cf), vector()); + flagTable_[e_cmovnp] = flagInfo(list_of(x86::of)(x86::sf)(x86::zf)(x86::pf)(x86::cf), vector()); flagTable_[e_cmovs] = flagInfo(list_of(x86::of)(x86::sf)(x86::zf)(x86::pf)(x86::cf), vector()); flagTable_[e_cmp] = flagInfo(vector(), standardFlags); flagTable_[e_cmpsb] = flagInfo(vector(), standardFlags); flagTable_[e_cmpsd] = flagInfo(vector(), standardFlags); flagTable_[e_cmpss] = flagInfo(vector(), standardFlags); flagTable_[e_cmpsw] = flagInfo(vector(), standardFlags); - flagTable_[e_cmpxch] = flagInfo(vector(), standardFlags); - flagTable_[e_cmpxch8b] = flagInfo(vector(), list_of(x86::zf)); + flagTable_[e_cmpxchg] = flagInfo(vector(), standardFlags); + flagTable_[e_cmpxchg8b] = flagInfo(vector(), list_of(x86::zf)); flagTable_[e_comisd] = flagInfo(vector(), standardFlags); flagTable_[e_comiss] = flagInfo(vector(), standardFlags); flagTable_[e_daa] = flagInfo(list_of(x86::af)(x86::cf), standardFlags); @@ -2134,25 +2111,25 @@ list_of(x86::of)(x86::sf)(x86::zf)(x86::af)(x86::pf)(x86::cf)(x86::tf)(x86::if_) flagTable_[e_jbe] = flagInfo(list_of(x86::of)(x86::sf)(x86::zf)(x86::pf)(x86::cf), vector()); flagTable_[e_jl] = flagInfo(list_of(x86::of)(x86::sf)(x86::zf)(x86::pf)(x86::cf), vector()); flagTable_[e_jle] = flagInfo(list_of(x86::of)(x86::sf)(x86::zf)(x86::pf)(x86::cf), vector()); - flagTable_[e_jnb] = flagInfo(list_of(x86::of)(x86::sf)(x86::zf)(x86::pf)(x86::cf), vector()); + flagTable_[e_jae] = flagInfo(list_of(x86::of)(x86::sf)(x86::zf)(x86::pf)(x86::cf), vector()); flagTable_[e_jnb_jae_j] = flagInfo(list_of(x86::of)(x86::sf)(x86::zf)(x86::pf)(x86::cf), vector()); - flagTable_[e_jnbe] = flagInfo(list_of(x86::of)(x86::sf)(x86::zf)(x86::pf)(x86::cf), vector()); - flagTable_[e_jnl] = flagInfo(list_of(x86::of)(x86::sf)(x86::zf)(x86::pf)(x86::cf), vector()); - flagTable_[e_jnle] = flagInfo(list_of(x86::of)(x86::sf)(x86::zf)(x86::pf)(x86::cf), vector()); + flagTable_[e_ja] = flagInfo(list_of(x86::of)(x86::sf)(x86::zf)(x86::pf)(x86::cf), vector()); + flagTable_[e_jge] = flagInfo(list_of(x86::of)(x86::sf)(x86::zf)(x86::pf)(x86::cf), vector()); + flagTable_[e_jg] = flagInfo(list_of(x86::of)(x86::sf)(x86::zf)(x86::pf)(x86::cf), vector()); flagTable_[e_jno] = flagInfo(list_of(x86::of)(x86::sf)(x86::zf)(x86::pf)(x86::cf), vector()); flagTable_[e_jnp] = flagInfo(list_of(x86::of)(x86::sf)(x86::zf)(x86::pf)(x86::cf), vector()); flagTable_[e_jns] = flagInfo(list_of(x86::of)(x86::sf)(x86::zf)(x86::pf)(x86::cf), vector()); - flagTable_[e_jnz] = flagInfo(list_of(x86::of)(x86::sf)(x86::zf)(x86::pf)(x86::cf), vector()); + flagTable_[e_jne] = flagInfo(list_of(x86::of)(x86::sf)(x86::zf)(x86::pf)(x86::cf), vector()); flagTable_[e_jo] = flagInfo(list_of(x86::of)(x86::sf)(x86::zf)(x86::pf)(x86::cf), vector()); flagTable_[e_jp] = flagInfo(list_of(x86::of)(x86::sf)(x86::zf)(x86::pf)(x86::cf), vector()); flagTable_[e_js] = flagInfo(list_of(x86::of)(x86::sf)(x86::zf)(x86::pf)(x86::cf), vector()); - flagTable_[e_jz] = flagInfo(list_of(x86::of)(x86::sf)(x86::zf)(x86::pf)(x86::cf), vector()); + flagTable_[e_je] = flagInfo(list_of(x86::of)(x86::sf)(x86::zf)(x86::pf)(x86::cf), vector()); flagTable_[e_lar] = flagInfo(vector(), list_of(x86::zf)); flagTable_[e_lodsb] = flagInfo(list_of(x86::df), vector()); flagTable_[e_lodsd] = flagInfo(list_of(x86::df), vector()); flagTable_[e_lodsw] = flagInfo(list_of(x86::df), vector()); flagTable_[e_loope] = flagInfo(list_of(x86::zf), vector()); - flagTable_[e_loopn] = flagInfo(list_of(x86::zf), vector()); + flagTable_[e_loopne] = flagInfo(list_of(x86::zf), vector()); flagTable_[e_lsl] = flagInfo(vector(), list_of(x86::zf)); // I'd expect that mov control/debug/test gets handled when we do operand analysis // If it doesn't, fix later @@ -2181,21 +2158,21 @@ list_of(x86::of)(x86::sf)(x86::zf)(x86::af)(x86::pf)(x86::cf)(x86::tf)(x86::if_) flagTable_[e_setbe] = flagInfo(list_of(x86::of)(x86::sf)(x86::zf)(x86::pf)(x86::cf), vector()); flagTable_[e_setl] = flagInfo(list_of(x86::of)(x86::sf)(x86::zf)(x86::pf)(x86::cf), vector()); flagTable_[e_setle] = flagInfo(list_of(x86::of)(x86::sf)(x86::zf)(x86::pf)(x86::cf), vector()); - flagTable_[e_setnb] = flagInfo(list_of(x86::of)(x86::sf)(x86::zf)(x86::pf)(x86::cf), vector()); - flagTable_[e_setnbe] = flagInfo(list_of(x86::of)(x86::sf)(x86::zf)(x86::pf)(x86::cf), vector()); - flagTable_[e_setnl] = flagInfo(list_of(x86::of)(x86::sf)(x86::zf)(x86::pf)(x86::cf), vector()); - flagTable_[e_setnle] = flagInfo(list_of(x86::of)(x86::sf)(x86::zf)(x86::pf)(x86::cf), vector()); + flagTable_[e_setae] = flagInfo(list_of(x86::of)(x86::sf)(x86::zf)(x86::pf)(x86::cf), vector()); + flagTable_[e_seta] = flagInfo(list_of(x86::of)(x86::sf)(x86::zf)(x86::pf)(x86::cf), vector()); + flagTable_[e_setge] = flagInfo(list_of(x86::of)(x86::sf)(x86::zf)(x86::pf)(x86::cf), vector()); + flagTable_[e_setg] = flagInfo(list_of(x86::of)(x86::sf)(x86::zf)(x86::pf)(x86::cf), vector()); flagTable_[e_setno] = flagInfo(list_of(x86::of)(x86::sf)(x86::zf)(x86::pf)(x86::cf), vector()); flagTable_[e_setnp] = flagInfo(list_of(x86::of)(x86::sf)(x86::zf)(x86::pf)(x86::cf), vector()); flagTable_[e_setns] = flagInfo(list_of(x86::of)(x86::sf)(x86::zf)(x86::pf)(x86::cf), vector()); - flagTable_[e_setnz] = flagInfo(list_of(x86::of)(x86::sf)(x86::zf)(x86::pf)(x86::cf), vector()); + flagTable_[e_setne] = flagInfo(list_of(x86::of)(x86::sf)(x86::zf)(x86::pf)(x86::cf), vector()); flagTable_[e_seto] = flagInfo(list_of(x86::of)(x86::sf)(x86::zf)(x86::pf)(x86::cf), vector()); flagTable_[e_setp] = flagInfo(list_of(x86::of)(x86::sf)(x86::zf)(x86::pf)(x86::cf), vector()); flagTable_[e_sets] = flagInfo(list_of(x86::of)(x86::sf)(x86::zf)(x86::pf)(x86::cf), vector()); - flagTable_[e_setz] = flagInfo(list_of(x86::of)(x86::sf)(x86::zf)(x86::pf)(x86::cf), vector()); + flagTable_[e_sete] = flagInfo(list_of(x86::of)(x86::sf)(x86::zf)(x86::pf)(x86::cf), vector()); flagTable_[e_shld] = flagInfo(vector(), standardFlags); flagTable_[e_shrd] = flagInfo(vector(), standardFlags); - flagTable_[e_shl_sal] = flagInfo(vector(), standardFlags); + flagTable_[e_shl] = flagInfo(vector(), standardFlags); flagTable_[e_stc] = flagInfo(vector(), list_of(x86::cf)); flagTable_[e_std] = flagInfo(vector(), list_of(x86::df)); flagTable_[e_sti] = flagInfo(vector(), list_of(x86::if_)); @@ -2357,8 +2334,8 @@ static ia32_entry oneByteMap[256] = { { e_pop, t_done, 0, false, { rSI, eSP, Zz }, 0, s1W2RW, s2I }, { e_pop, t_done, 0, false, { rDI, eSP, Zz }, 0, s1W2RW, s2I }, /* 60 */ - { e_pushad, t_done, 0, false, { GPRS, eSP, Zz }, 0, s1R2RW, s2I }, - { e_popad, t_done, 0, false, { GPRS, eSP, Zz }, 0, s1W2RW, s2I }, + { e_pushal, t_done, 0, false, { GPRS, eSP, Zz }, 0, s1R2RW, s2I }, + { e_popaw, t_done, 0, false, { GPRS, eSP, Zz }, 0, s1W2RW, s2I }, { e_bound, t_done, 0, true, { Gv, Ma, Zz }, 0, s1R2R, 0 }, // or VEX { e_arpl, t_done, 0, true, { Ew, Gw, Zz }, 0, s1R2R, 0 }, /* No REX */ { e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0, 0 }, // PREFIX_SEG_OVR @@ -2379,19 +2356,19 @@ static ia32_entry oneByteMap[256] = { { e_jno, t_done, 0, false, { Jb, Zz, Zz }, (IS_JCC | REL_B), s1R, 0 }, { e_jb_jnaej_j, t_done, 0, false, { Jb, Zz, Zz }, (IS_JCC | REL_B), s1R, 0 }, { e_jnb_jae_j, t_done, 0, false, { Jb, Zz, Zz }, (IS_JCC | REL_B), s1R, 0 }, - { e_jz, t_done, 0, false, { Jb, Zz, Zz }, (IS_JCC | REL_B), s1R, 0 }, - { e_jnz, t_done, 0, false, { Jb, Zz, Zz }, (IS_JCC | REL_B), s1R, 0 }, + { e_je, t_done, 0, false, { Jb, Zz, Zz }, (IS_JCC | REL_B), s1R, 0 }, + { e_jne, t_done, 0, false, { Jb, Zz, Zz }, (IS_JCC | REL_B), s1R, 0 }, { e_jbe, t_done, 0, false, { Jb, Zz, Zz }, (IS_JCC | REL_B), s1R, 0 }, - { e_jnbe, t_done, 0, false, { Jb, Zz, Zz }, (IS_JCC | REL_B), s1R, 0 }, + { e_ja, t_done, 0, false, { Jb, Zz, Zz }, (IS_JCC | REL_B), s1R, 0 }, /* 78 */ { e_js, t_done, 0, false, { Jb, Zz, Zz }, (IS_JCC | REL_B), s1R, 0 }, { e_jns, t_done, 0, false, { Jb, Zz, Zz }, (IS_JCC | REL_B), s1R, 0 }, { e_jp, t_done, 0, false, { Jb, Zz, Zz }, (IS_JCC | REL_B), s1R, 0 }, { e_jnp, t_done, 0, false, { Jb, Zz, Zz }, (IS_JCC | REL_B), s1R, 0 }, { e_jl, t_done, 0, false, { Jb, Zz, Zz }, (IS_JCC | REL_B), s1R, 0 }, - { e_jnl, t_done, 0, false, { Jb, Zz, Zz }, (IS_JCC | REL_B), s1R, 0 }, + { e_jge, t_done, 0, false, { Jb, Zz, Zz }, (IS_JCC | REL_B), s1R, 0 }, { e_jle, t_done, 0, false, { Jb, Zz, Zz }, (IS_JCC | REL_B), s1R, 0 }, - { e_jnle, t_done, 0, false, { Jb, Zz, Zz }, (IS_JCC | REL_B), s1R, 0 }, + { e_jg, t_done, 0, false, { Jb, Zz, Zz }, (IS_JCC | REL_B), s1R, 0 }, /* 80 */ { e_No_Entry, t_grp, Grp1a, true, { Zz, Zz, Zz }, 0, 0, 0 }, { e_No_Entry, t_grp, Grp1b, true, { Zz, Zz, Zz }, 0, 0, 0 }, @@ -2425,7 +2402,7 @@ static ia32_entry oneByteMap[256] = { { e_cdq, t_done, 0, false, { eDX, eAX, Zz }, 0, s1W2R, s1I }, { e_call, t_done, 0, false, { Ap, Zz, Zz }, IS_CALL | PTR_WX, s1R, 0 }, { e_wait, t_done, 0, false, { Zz, Zz, Zz }, 0, sNONE, 0 }, - { e_pushfd, t_done, 0, false, { Fv, rSP, Zz }, 0, s1R2RW, s2I }, + { e_pushf, t_done, 0, false, { Fv, rSP, Zz }, 0, s1R2RW, s2I }, { e_popfd, t_done, 0, false, { Fv, rSP, Zz }, 0, s1W2RW, s2I }, { e_sahf, t_done, 0, false, { Zz, Zz, Zz }, 0, 0, 0 }, // FIXME Intel { e_lahf, t_done, 0, false, { Zz, Zz, Zz }, 0, 0, 0 }, // FIXME Intel @@ -2492,7 +2469,7 @@ static ia32_entry oneByteMap[256] = { { e_aam, t_done, 0, false, { AX, Ib, Zz }, 0, s1RW2R, s1I | s2I }, { e_aad, t_done, 0, false, { AX, Ib, Zz }, 0, s1RW2R, s1I | s2I }, { e_salc, t_done, 0, false, { Zz, Zz, Zz }, 0, sNONE, 0 }, // undocumeted - { e_xlat, t_done, 0, false, { Zz, Zz, Zz }, 0, fXLAT << FPOS, 0 }, // scream + { e_xlatb, t_done, 0, false, { Zz, Zz, Zz }, 0, fXLAT << FPOS, 0 }, // scream /* D8 */ { e_No_Entry, t_coprocEsc, GrpD8, true, { Zz, Zz, Zz }, 0, 0, 0 }, { e_No_Entry, t_coprocEsc, GrpD9, true, { Zz, Zz, Zz }, 0, 0, 0 }, @@ -2503,7 +2480,7 @@ static ia32_entry oneByteMap[256] = { { e_No_Entry, t_coprocEsc, GrpDE, true, { Zz, Zz, Zz }, 0, 0, 0 }, { e_No_Entry, t_coprocEsc, GrpDF, true, { Zz, Zz, Zz }, 0, 0, 0 }, /* E0 */ - { e_loopn, t_done, 0, false, { Jb, eCX, Zz }, (IS_JCC | REL_B), s1R2R, 0 }, + { e_loopne, t_done, 0, false, { Jb, eCX, Zz }, (IS_JCC | REL_B), s1R2R, 0 }, { e_loope, t_done, 0, false, { Jb, eCX, Zz }, (IS_JCC | REL_B), s1R2R, 0 }, { e_loop, t_done, 0, false, { Jb, eCX, Zz }, (IS_JCC | REL_B), s1R2R, 0 }, { e_jcxz_jec, t_done, 0, false, { Jb, eCX, Zz }, (IS_JCC | REL_B), s1R2R, 0 }, @@ -2630,7 +2607,7 @@ static ia32_entry twoByteMap[256] = { { e_cmovo, t_done, 0, true, { Gv, Ev, Zz }, 0, s1RW2R | (fCOND << FPOS), 0 }, { e_No_Entry, t_sse_vex_mult, SSEVEX41, false, { Zz, Zz, Zz }, 0, 0, 0 }, { e_No_Entry, t_sse_vex_mult, SSEVEX42, false, { Zz, Zz, Zz }, 0, 0, 0 }, - { e_cmovnb, t_done, 0, true, { Gv, Ev, Zz }, 0, s1RW2R | (fCOND << FPOS), 0 }, + { e_cmovae, t_done, 0, true, { Gv, Ev, Zz }, 0, s1RW2R | (fCOND << FPOS), 0 }, { e_No_Entry, t_sse_vex_mult, SSEVEX44, false, { Zz, Zz, Zz }, 0, 0, 0 }, { e_No_Entry, t_sse_vex_mult, SSEVEX45, false, { Zz, Zz, Zz }, 0, 0, 0 }, { e_No_Entry, t_sse_vex_mult, SSEVEX46, false, { Zz, Zz, Zz }, 0, 0, 0 }, @@ -2640,10 +2617,10 @@ static ia32_entry twoByteMap[256] = { { e_cmovns, t_done, 0, true, { Gv, Ev, Zz }, 0, s1RW2R | (fCOND << FPOS), 0 }, { e_No_Entry, t_sse_vex_mult, SSEVEX4A, false, { Zz, Zz, Zz }, 0, 0, 0 }, { e_No_Entry, t_sse_vex_mult, SSEVEX4B, false, { Zz, Zz, Zz }, 0, 0, 0 }, - { e_cmovnge, t_done, 0, true, { Gv, Ev, Zz }, 0, s1RW2R | (fCOND << FPOS), 0 }, - { e_cmovnl, t_done, 0, true, { Gv, Ev, Zz }, 0, s1RW2R | (fCOND << FPOS), 0 }, - { e_cmovng, t_done, 0, true, { Gv, Ev, Zz }, 0, s1RW2R | (fCOND << FPOS), 0 }, - { e_cmovnl, t_done, 0, true, { Gv, Ev, Zz }, 0, s1RW2R | (fCOND << FPOS), 0 }, + { e_cmovl, t_done, 0, true, { Gv, Ev, Zz }, 0, s1RW2R | (fCOND << FPOS), 0 }, + { e_cmovge, t_done, 0, true, { Gv, Ev, Zz }, 0, s1RW2R | (fCOND << FPOS), 0 }, + { e_cmovle, t_done, 0, true, { Gv, Ev, Zz }, 0, s1RW2R | (fCOND << FPOS), 0 }, + { e_cmovge, t_done, 0, true, { Gv, Ev, Zz }, 0, s1RW2R | (fCOND << FPOS), 0 }, /* 50 */ { e_No_Entry, t_sse, SSE50, true, { Zz, Zz, Zz }, 0, 0, 0 }, { e_No_Entry, t_sse, SSE51, true, { Zz, Zz, Zz }, 0, 0, 0 }, @@ -2702,38 +2679,38 @@ static ia32_entry twoByteMap[256] = { { e_jo, t_done, 0, false, { Jz, Zz, Zz }, (IS_JCC | REL_X), s1R | (fCOND << FPOS), 0 }, { e_jno, t_done, 0, false, { Jz, Zz, Zz }, (IS_JCC | REL_X), s1R | (fCOND << FPOS), 0 }, { e_jb, t_done, 0, false, { Jz, Zz, Zz }, (IS_JCC | REL_X), s1R | (fCOND << FPOS), 0 }, - { e_jnb, t_done, 0, false, { Jz, Zz, Zz }, (IS_JCC | REL_X), s1R | (fCOND << FPOS), 0 }, - { e_jz, t_done, 0, false, { Jz, Zz, Zz }, (IS_JCC | REL_X), s1R | (fCOND << FPOS), 0 }, - { e_jnz, t_done, 0, false, { Jz, Zz, Zz }, (IS_JCC | REL_X), s1R | (fCOND << FPOS), 0 }, + { e_jae, t_done, 0, false, { Jz, Zz, Zz }, (IS_JCC | REL_X), s1R | (fCOND << FPOS), 0 }, + { e_je, t_done, 0, false, { Jz, Zz, Zz }, (IS_JCC | REL_X), s1R | (fCOND << FPOS), 0 }, + { e_jne, t_done, 0, false, { Jz, Zz, Zz }, (IS_JCC | REL_X), s1R | (fCOND << FPOS), 0 }, { e_jbe, t_done, 0, false, { Jz, Zz, Zz }, (IS_JCC | REL_X), s1R | (fCOND << FPOS), 0 }, - { e_jnbe, t_done, 0, false, { Jz, Zz, Zz }, (IS_JCC | REL_X), s1R | (fCOND << FPOS), 0 }, + { e_ja, t_done, 0, false, { Jz, Zz, Zz }, (IS_JCC | REL_X), s1R | (fCOND << FPOS), 0 }, /* 88 */ { e_js, t_done, 0, false, { Jz, Zz, Zz }, (IS_JCC | REL_X), s1R | (fCOND << FPOS), 0 }, { e_jns, t_done, 0, false, { Jz, Zz, Zz }, (IS_JCC | REL_X), s1R | (fCOND << FPOS), 0 }, { e_jp, t_done, 0, false, { Jz, Zz, Zz }, (IS_JCC | REL_X), s1R | (fCOND << FPOS), 0 }, { e_jnp, t_done, 0, false, { Jz, Zz, Zz }, (IS_JCC | REL_X), s1R | (fCOND << FPOS), 0 }, { e_jl, t_done, 0, false, { Jz, Zz, Zz }, (IS_JCC | REL_X), s1R | (fCOND << FPOS), 0 }, - { e_jnl, t_done, 0, false, { Jz, Zz, Zz }, (IS_JCC | REL_X), s1R | (fCOND << FPOS), 0 }, + { e_jge, t_done, 0, false, { Jz, Zz, Zz }, (IS_JCC | REL_X), s1R | (fCOND << FPOS), 0 }, { e_jle, t_done, 0, false, { Jz, Zz, Zz }, (IS_JCC | REL_X), s1R | (fCOND << FPOS), 0 }, - { e_jnle, t_done, 0, false, { Jz, Zz, Zz }, (IS_JCC | REL_X), s1R | (fCOND << FPOS), 0 }, + { e_jg, t_done, 0, false, { Jz, Zz, Zz }, (IS_JCC | REL_X), s1R | (fCOND << FPOS), 0 }, /* 90 */ { e_No_Entry, t_sse_vex_mult, SSEVEX90, false, { Zz, Zz, Zz }, 0, 0, 0 }, { e_No_Entry, t_sse_vex_mult, SSEVEX91, false, { Zz, Zz, Zz }, 0, 0, 0 }, { e_No_Entry, t_sse_vex_mult, SSEVEX92, false, { Zz, Zz, Zz }, 0, 0, 0 }, { e_No_Entry, t_sse_vex_mult, SSEVEX93, false, { Zz, Zz, Zz }, 0, 0, 0 }, - { e_setz, t_done, 0, true, { Eb, Zz, Zz }, 0, s1W | (fCOND << FPOS), 0 }, - { e_setnz, t_done, 0, true, { Eb, Zz, Zz }, 0, s1W | (fCOND << FPOS), 0 }, + { e_sete, t_done, 0, true, { Eb, Zz, Zz }, 0, s1W | (fCOND << FPOS), 0 }, + { e_setne, t_done, 0, true, { Eb, Zz, Zz }, 0, s1W | (fCOND << FPOS), 0 }, { e_setbe, t_done, 0, true, { Eb, Zz, Zz }, 0, s1W | (fCOND << FPOS), 0 }, - { e_setnbe, t_done, 0, true, { Eb, Zz, Zz }, 0, s1W | (fCOND << FPOS), 0 }, + { e_seta, t_done, 0, true, { Eb, Zz, Zz }, 0, s1W | (fCOND << FPOS), 0 }, /* 98 */ { e_No_Entry, t_sse_vex_mult, SSEVEX98, false, { Zz, Zz, Zz }, 0, 0, 0 }, { e_No_Entry, t_sse_vex_mult, SSEVEX99, false, { Zz, Zz, Zz }, 0, 0, 0 }, { e_setp, t_done, 0, true, { Eb, Zz, Zz }, 0, s1W | (fCOND << FPOS), 0 }, { e_setnp, t_done, 0, true, { Eb, Zz, Zz }, 0, s1W | (fCOND << FPOS), 0 }, { e_setl, t_done, 0, true, { Eb, Zz, Zz }, 0, s1W | (fCOND << FPOS), 0 }, - { e_setnl, t_done, 0, true, { Eb, Zz, Zz }, 0, s1W | (fCOND << FPOS), 0 }, + { e_setge, t_done, 0, true, { Eb, Zz, Zz }, 0, s1W | (fCOND << FPOS), 0 }, { e_setle, t_done, 0, true, { Eb, Zz, Zz }, 0, s1W | (fCOND << FPOS), 0 }, - { e_setnle, t_done, 0, true, { Eb, Zz, Zz }, 0, s1W | (fCOND << FPOS), 0 }, + { e_setg, t_done, 0, true, { Eb, Zz, Zz }, 0, s1W | (fCOND << FPOS), 0 }, /* A0 */ { e_push, t_done, 0, false, { FS, eSP, Zz }, 0, s1R2RW, s2I }, { e_pop, t_done, 0, false, { FS, eSP, Zz }, 0, s1W2RW, s2I }, @@ -2756,8 +2733,8 @@ static ia32_entry twoByteMap[256] = { // Assuming this is used with LOCK prefix, the destination gets a write anyway // This is not the case without lock prefix, but I ignore that case // Also, given that the 3rd operand is a register I ignore that it may be written - { e_cmpxch, t_done, 0, true, { Eb, Gb, AL }, 0, s1RW2R3R | (fCMPXCH << FPOS), s2I }, - { e_cmpxch, t_done, 0, true, { Ev, Gv, eAX }, 0, s1RW2R3R | (fCMPXCH << FPOS), s2I }, + { e_cmpxchg, t_done, 0, true, { Eb, Gb, AL }, 0, s1RW2R3R | (fCMPXCH << FPOS), s2I }, + { e_cmpxchg, t_done, 0, true, { Ev, Gv, eAX }, 0, s1RW2R3R | (fCMPXCH << FPOS), s2I }, { e_lss, t_done, 0, true, { SS, Gv, Mp }, 0, s1W2W3R, 0 }, { e_btr, t_done, 0, true, { Ev, Gv, Zz }, 0, s1RW2R, 0 }, { e_lfs, t_done, 0, true, { FS, Gv, Mp }, 0, s1W2W3R, 0 }, @@ -3477,8 +3454,8 @@ static ia32_entry fpuMap[][2][8] = { { e_fstp, t_done, 0, true, { Ef, ST0, Zz }, 0, s1W2R, 0 }, // stack pop { e_fldenv, t_done, 0, true, { M14, Zz, Zz }, 0, s1R, 0 }, { e_fldcw, t_done, 0, true, { Ew, Zz, Zz }, 0, s1R, 0 }, - { e_fstenv, t_done, 0, true, { M14, Zz, Zz }, 0, s1W, 0 }, - { e_fstcw, t_done, 0, true, { Ew, Zz, Zz }, 0, s1W, 0 } + { e_fnstenv, t_done, 0, true, { M14, Zz, Zz }, 0, s1W, 0 }, + { e_fnstcw, t_done, 0, true, { Ew, Zz, Zz }, 0, s1W, 0 } }, { // D9 { e_fld, t_done, 0, true, { ST0, Ef, Zz }, 0, s1W2R, 0 }, // stack push @@ -3565,8 +3542,8 @@ static ia32_entry fpuMap[][2][8] = { { e_fstp, t_done, 0, true, { Efd, ST0, Zz }, 0, s1W2R, 0 }, // stack pop { e_frstor, t_done, 0, true, { M512, Zz, Zz }, 0, s1R, 0 }, { e_fucomp, t_done, 0, true, { ST0, Efd, Zz }, 0, s1R2R, 0 }, // stack pop - { e_fsave, t_done, 0, true, { M512, Zz, Zz }, 0, s1W, 0 }, - { e_fstsw, t_done, 0, true, { Ew, Zz, Zz }, 0, s1W, 0 } + { e_fnsave, t_done, 0, true, { M512, Zz, Zz }, 0, s1W, 0 }, + { e_fnstsw, t_done, 0, true, { Ew, Zz, Zz }, 0, s1W, 0 } }, { // DD TODO semantics check { e_ffree, t_done, 0, true, { Efd, Zz, Zz }, 0, s1W, 0 }, @@ -3617,9 +3594,9 @@ static ia32_entry fpuMap[][2][8] = { { e_fxch, t_done, 0, true, { ST0, Ef, Zz }, 0, s1RW2RW, 0 }, { e_fstp, t_done, 0, true, { Ef, ST0, Zz }, 0, sNONE, 0 }, { e_fstp, t_done, 0, true, { Ef, ST0, Zz }, 0, sNONE, 0 }, - { e_fstsw, t_done, 0, true, { AX, Zz, Zz }, 0, s1W, 0 }, - { e_fucomip, t_done, 0, true, { ST0, Ef, Zz }, 0, s1RW2R, 0 }, // stack pop - { e_fcomip, t_done, 0, true, { ST0, Ef, Zz }, 0, s1RW2R, 0 }, // stack pop + { e_fnstsw, t_done, 0, true, { AX, Zz, Zz }, 0, s1W, 0 }, + { e_fucompi, t_done, 0, true, { ST0, Ef, Zz }, 0, s1RW2R, 0 }, // stack pop + { e_fcompi, t_done, 0, true, { ST0, Ef, Zz }, 0, s1RW2R, 0 }, // stack pop { e_No_Entry, t_done, 0, true, { Zz, Zz, Zz }, 0, sNONE, 0 }, } } @@ -3699,9 +3676,9 @@ static ia32_entry groupMap[][8] = { { e_ror, t_done, 0, true, { Zz, Zz, Zz }, 0, 0, 0 }, { e_rcl, t_done, 0, true, { Zz, Zz, Zz }, 0, 0, 0 }, { e_rcr, t_done, 0, true, { Zz, Zz, Zz }, 0, 0, 0 }, - { e_shl_sal, t_done, 0, true, { Zz, Zz, Zz }, 0, 0, 0 }, + { e_shl, t_done, 0, true, { Zz, Zz, Zz }, 0, 0, 0 }, { e_shr, t_done, 0, true, { Zz, Zz, Zz }, 0, 0, 0 }, - { e_shl_sal, t_done, 0, true, { Zz, Zz, Zz }, 0, 0, 0 }, + { e_shl, t_done, 0, true, { Zz, Zz, Zz }, 0, 0, 0 }, { e_sar, t_done, 0, true, { Zz, Zz, Zz }, 0, 0, 0 } }, @@ -3788,7 +3765,7 @@ static ia32_entry groupMap[][8] = { { /* group 9 - operands are defined here */ { e_No_Entry, t_ill, 0, true, { Zz, Zz, Zz }, 0, 0, 0 }, // see comments for cmpxch - { e_cmpxch8b, t_done, 0, true, { EDXEAX, Mq, ECXEBX }, 0, s1RW2RW3R | (fCMPXCH8 << FPOS), s2I }, + { e_cmpxchg8b, t_done, 0, true, { EDXEAX, Mq, ECXEBX }, 0, s1RW2RW3R | (fCMPXCH8 << FPOS), s2I }, { e_No_Entry, t_ill, 0, true, { Zz, Zz, Zz }, 0, 0, 0 }, { e_xrstors, t_done, 0, true, { Wps, Zz, Zz }, 0, 0, 0 }, { e_xsavec, t_done, 0, true, { Md, Zz, Zz }, s1W, 0, 0 }, @@ -3940,10 +3917,10 @@ static ia32_entry groupMap2[][2][8] = { }, { /* group 16 */ { - { e_prefetchNTA, t_done, 0, true, { Mb, Zz, Zz }, 0, s1R | (fPREFETCHNT << FPOS), 0 }, - { e_prefetchT0, t_done, 0, true, { Mb, Zz, Zz }, 0, s1R | (fPREFETCHT0 << FPOS), 0 }, - { e_prefetchT1, t_done, 0, true, { Mb, Zz, Zz }, 0, s1R | (fPREFETCHT1 << FPOS), 0 }, - { e_prefetchT2, t_done, 0, true, { Mb, Zz, Zz }, 0, s1R | (fPREFETCHT1 << FPOS), 0 }, + { e_prefetchnta, t_done, 0, true, { Mb, Zz, Zz }, 0, s1R | (fPREFETCHNT << FPOS), 0 }, + { e_prefetcht0, t_done, 0, true, { Mb, Zz, Zz }, 0, s1R | (fPREFETCHT0 << FPOS), 0 }, + { e_prefetcht1, t_done, 0, true, { Mb, Zz, Zz }, 0, s1R | (fPREFETCHT1 << FPOS), 0 }, + { e_prefetcht2, t_done, 0, true, { Mb, Zz, Zz }, 0, s1R | (fPREFETCHT1 << FPOS), 0 }, { e_No_Entry, t_ill, 0, true, { Zz, Zz, Zz }, 0, 0, 0 }, { e_No_Entry, t_ill, 0, true, { Zz, Zz, Zz }, 0, 0, 0 }, { e_No_Entry, t_ill, 0, true, { Zz, Zz, Zz }, 0, 0, 0 }, @@ -4028,7 +4005,7 @@ static ia32_entry sseVexMult[][4] = { { e_No_Entry, t_sse, SSE41, false, { Zz, Zz, Zz }, 0, 0, 0 }, { e_No_Entry, t_sse, SSE41, false, { Zz, Zz, Zz }, 0, 0, 0 }, }, { /* SSEVEX42 */ - { e_cmovnae, t_done, 0, true, { Gv, Ev, Zz }, 0, s1RW2R | (fCOND << FPOS), 0 }, + { e_cmovb, t_done, 0, true, { Gv, Ev, Zz }, 0, s1RW2R | (fCOND << FPOS), 0 }, { e_No_Entry, t_sse, SSE42, false, { Zz, Zz, Zz }, 0, 0, 0 }, { e_No_Entry, t_sse, SSE42, false, { Zz, Zz, Zz }, 0, 0, 0 }, { e_No_Entry, t_sse, SSE42, false, { Zz, Zz, Zz }, 0, 0, 0 }, @@ -4048,17 +4025,17 @@ static ia32_entry sseVexMult[][4] = { { e_No_Entry, t_sse, SSE46, false, { Zz, Zz, Zz }, 0, 0, 0 }, { e_No_Entry, t_sse, SSE46, false, { Zz, Zz, Zz }, 0, 0, 0 }, }, { /* SSEVEX47 */ - { e_cmovnbe, t_done, 0, true, { Gv, Ev, Zz }, 0, s1RW2R | (fCOND << FPOS), 0 }, + { e_cmova, t_done, 0, true, { Gv, Ev, Zz }, 0, s1RW2R | (fCOND << FPOS), 0 }, { e_No_Entry, t_sse, SSE47, false, { Zz, Zz, Zz }, 0, 0, 0 }, { e_No_Entry, t_sse, SSE47, false, { Zz, Zz, Zz }, 0, 0, 0 }, { e_No_Entry, t_sse, SSE47, false, { Zz, Zz, Zz }, 0, 0, 0 }, }, { /* SSEVEX4A */ - { e_cmovpe, t_done, 0, true, { Gv, Ev, Zz }, 0, s1RW2R | (fCOND << FPOS), 0 }, + { e_cmovp, t_done, 0, true, { Gv, Ev, Zz }, 0, s1RW2R | (fCOND << FPOS), 0 }, { e_No_Entry, t_sse, SSE4A, false, { Zz, Zz, Zz }, 0, 0, 0 }, { e_No_Entry, t_sse, SSE4A, false, { Zz, Zz, Zz }, 0, 0, 0 }, { e_No_Entry, t_sse, SSE4A, false, { Zz, Zz, Zz }, 0, 0, 0 }, }, { /* SSEVEX4B */ - { e_cmovpo, t_done, 0, true, { Gv, Ev, Zz }, 0, s1RW2R | (fCOND << FPOS), 0 }, + { e_cmovnp, t_done, 0, true, { Gv, Ev, Zz }, 0, s1RW2R | (fCOND << FPOS), 0 }, { e_No_Entry, t_sse, SSE4B, false, { Zz, Zz, Zz }, 0, 0, 0 }, { e_No_Entry, t_sse, SSE4B, false, { Zz, Zz, Zz }, 0, 0, 0 }, { e_No_Entry, t_sse, SSE4B, false, { Zz, Zz, Zz }, 0, 0, 0 }, @@ -4088,7 +4065,7 @@ static ia32_entry sseVexMult[][4] = { { e_No_Entry, t_sse, SSE92, false, { Zz, Zz, Zz }, 0, 0, 0 }, { e_No_Entry, t_sse, SSE92, false, { Zz, Zz, Zz }, 0, 0, 0 } }, { /* SSEVEX93 */ - { e_setnb, t_done, 0, true, { Eb, Zz, Zz }, 0, s1W | (fCOND << FPOS), 0 }, + { e_setae, t_done, 0, true, { Eb, Zz, Zz }, 0, s1W | (fCOND << FPOS), 0 }, { e_No_Entry, t_sse, SSE93, false, { Zz, Zz, Zz }, 0, 0, 0 }, { e_No_Entry, t_sse, SSE93, false, { Zz, Zz, Zz }, 0, 0, 0 }, { e_No_Entry, t_sse, SSE93, false, { Zz, Zz, Zz }, 0, 0, 0 } @@ -4362,9 +4339,9 @@ static ia32_entry sseMap[][4] = { { e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0, 0 }, }, { /* SSE62 */ - { e_punpcklqd, t_done, 0, true, { Pq, Qd, Zz }, 0, s1RW2R, 0 }, + { e_punpckldq, t_done, 0, true, { Pq, Qd, Zz }, 0, s1RW2R, 0 }, { e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0, 0 }, - { e_punpcklqd, t_sse_mult, SSE62_66, true, { Vdq, Wdq, Zz }, 0, s1RW2R, 0 }, + { e_punpckldq, t_sse_mult, SSE62_66, true, { Vdq, Wdq, Zz }, 0, s1RW2R, 0 }, { e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0, 0 }, }, { /* SSE63 */ @@ -4386,9 +4363,9 @@ static ia32_entry sseMap[][4] = { { e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0, 0 }, }, { /* SSE66 */ - { e_pcmpgdt, t_done, 0, true, { Pq, Qq, Zz }, 0, s1R2R, 0 }, + { e_pcmpgtd, t_done, 0, true, { Pq, Qq, Zz }, 0, s1R2R, 0 }, { e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0, 0 }, - { e_pcmpgdt, t_sse_mult, SSE66_66, true, { Vdq, Wdq, Zz }, 0, s1R2R, 0 }, + { e_pcmpgtd, t_sse_mult, SSE66_66, true, { Vdq, Wdq, Zz }, 0, s1R2R, 0 }, { e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0, 0 }, }, { /* SSE67 */ @@ -4424,13 +4401,13 @@ static ia32_entry sseMap[][4] = { { /* SSE6C */ { e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0, 0 }, { e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0, 0 }, - { e_punpcklqld, t_sse_mult, SSE6C_66, true, { Vdq, Wdq, Zz }, 0, s1RW2R, 0 }, + { e_punpcklqdq, t_sse_mult, SSE6C_66, true, { Vdq, Wdq, Zz }, 0, s1RW2R, 0 }, { e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0, 0 }, }, { /* SSE6D */ { e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0, 0 }, { e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0, 0 }, - { e_punpckhqd, t_sse_mult, SSE6D_66, true, { Vdq, Wdq, Zz }, 0, s1RW2R, 0 }, + { e_punpckhqdq, t_sse_mult, SSE6D_66, true, { Vdq, Wdq, Zz }, 0, s1RW2R, 0 }, { e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0, 0 }, }, { /* SSE6E */ @@ -4578,7 +4555,7 @@ static ia32_entry sseMap[][4] = { { e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0, 0 } }, { /* SSEB8 */ - { e_jmpe, t_done, 0, false, { Jz, Zz, Zz }, 0, s1R, 0 }, + { e_No_Entry, t_done, 0, false, { Zz, Zz, Zz }, 0, s1R, 0 }, { e_popcnt, t_done, 0, true, { Gv, Ev, Zz }, 0, s1W2R, 0 }, { e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0, 0 }, { e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0, 0 }, @@ -4593,7 +4570,7 @@ static ia32_entry sseMap[][4] = { { e_cmpps, t_sse_mult, SSEC2_NO, true, { Vps, Wps, Ib }, 0, s1RW2R3R, 0 }, // comparison writes to dest! { e_cmpss, t_sse_mult, SSEC2_F3, true, { Vss, Wss, Ib }, 0, s1RW2R3R, 0 }, { e_cmppd, t_sse_mult, SSEC2_66, true, { Vpd, Wpd, Ib }, 0, s1RW2R3R, 0 }, - { e_cmpsd_sse, t_sse_mult, SSEC2_F2, true, { Vsd, Wsd, Ib }, 0, s1RW2R3R, 0 }, + { e_cmpsd, t_sse_mult, SSEC2_F2, true, { Vsd, Wsd, Ib }, 0, s1RW2R3R, 0 }, }, { /* SSEC4 */ { e_pinsrw, t_done, 0, true, { Pq, Ed, Ib }, 0, s1RW2R3R, 0 }, @@ -4896,9 +4873,9 @@ static ia32_entry sseMap[][4] = { { e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0, 0 }, }, { /* SSEFF */ - { e_ud, t_done, 0, false, { Zz, Zz, Zz }, 0, 0, 0 }, + { e_ud0, t_done, 0, false, { Zz, Zz, Zz }, 0, 0, 0 }, { e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0, 0 }, - { e_ud, t_done, 0, false, { Zz, Zz, Zz }, 0, 0, 0 }, + { e_ud0, t_done, 0, false, { Zz, Zz, Zz }, 0, 0, 0 }, { e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0, 0 }, } }; @@ -5861,7 +5838,7 @@ static ia32_entry sseMapTer[][3] = { e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0, 0 } }, { /* SSET02 */ { e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0, 0 }, - { e_vpblendd, t_done, 0, true, { Vpd, Hpd, Upd }, 0, s1W2R3R4R, 0 }, + { e_vpblendd, t_done, 0, true, { Vpd, Hpd, Wpd }, 0, s1W2R3R4R, 0 }, { e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0, 0 } }, { /* SSET03 */ { e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0, 0 }, @@ -6037,7 +6014,7 @@ static ia32_entry sseMapTer[][3] = { e_mpsadbw, t_done, 0, true, { Vdq, Wdq, Ib }, 0, s1RW2R3R, 0 }, }, { /* SSET44 */ { e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0, 0 }, - { e_pclmullqlqdq, t_sse_ter_mult, SSET44_66, true, { Vps, Wps, Ib }, 0, s1RW2R3R, 0 }, + { e_pclmulqdq, t_sse_ter_mult, SSET44_66, true, { Vps, Wps, Ib }, 0, s1RW2R3R, 0 }, { e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0, 0 }, }, { /* SSET46 */ { e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0, 0 }, @@ -6640,23 +6617,23 @@ ia32_entry sseMapMult[][3] = }, { /* SSE79_F3 */ { e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0, 0 }, { e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0, 0 }, - { e_vcvtss2usi, t_done, 0, true, { Ev, Vps, Zz }, 0, s1W2R, 0 } + { e_vcvtss2usi, t_done, 0, true, { Gv, Wps, Zz }, 0, s1W2R, 0 } }, { /* SSE79_NO */ { e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0, 0 }, { e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0, 0 }, - { e_vcvtpd2udq, t_done, 0, true, { Vpd, Vps, Zz }, 0, s1W2R, 0 } + { e_vcvtpd2udq, t_done, 0, true, { Vpd, Wps, Zz }, 0, s1W2R, 0 } }, { /* SSE7A_66 */ { e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0, 0 }, { e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0, 0 }, - { e_vcvttpd2qq, t_done, 0, true, { Vpd, Vpd, Zz }, 0, s1W2R, 0 }, + { e_vcvttpd2qq, t_done, 0, true, { Vpd, Wpd, Zz }, 0, s1W2R, 0 }, }, { /* SSE7A_F2 */ { e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0, 0 }, { e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0, 0 }, - { e_vcvtudq2ps, t_done, 0, true, { Vpd, Vpd, Zz }, 0, s1W2R, 0 }, + { e_vcvtudq2ps, t_done, 0, true, { Vpd, Wpd, Zz }, 0, s1W2R, 0 }, }, { /* SSE7A_F3 */ { e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0, 0 }, { e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0, 0 }, - { e_vcvtudq2pd, t_done, 0, true, { Ev, Vpd, Zz }, 0, 0, 0 } + { e_vcvtudq2pd, t_done, 0, true, { Vps, Wpd, Zz }, 0, 0, 0 } }, { /* SSE7B_66 */ { e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0, 0 }, { e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0, 0 }, @@ -6790,7 +6767,7 @@ ia32_entry sseMapMult[][3] = { e_vpminub, t_done, 0, true, { Vps, Hps, Wps }, 0, s1W2R3R, 0 }, { e_vpminub, t_done, 0, true, { Vps, Hps, Wps }, 0, s1W2R3R, 0 }, }, { /* SSEDB_66 */ - { e_vpand, t_done, 0, true, { Vps, Hps, Wps }, 0, s1RW2R, 0 }, + { e_vpand, t_done, 0, true, { Vps, Hps, Wps }, 0, s1W2R3R, 0 }, { e_No_Entry, t_vexw, VEXW91, false, { Zz, Zz, Zz }, 0, 0, 0 }, { e_No_Entry, t_vexw, VEXW64, false, { Zz, Zz, Zz }, 0, 0, 0 } }, { /* SSEDC_66 */ @@ -7626,7 +7603,7 @@ ia32_entry sseMapTerMult[][3] = }, { /* SSET01_66 */ { e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0, 0 }, { e_vpermpd, t_done, 0, true, { Wpd, Vpd, Ib }, 0, s1W2R3R, 0 }, - { e_vpermpd, t_done, 0, true, { Vpd, Hpd, Ib }, 0, s1W2R3R, 0 }, + { e_vpermpd, t_done, 0, true, { Wpd, Vpd, Ib }, 0, s1W2R3R, 0 }, }, { /* SSET03_66 */ { e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0, 0 }, { e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0, 0 }, @@ -7698,7 +7675,7 @@ ia32_entry sseMapTerMult[][3] = }, { /* SSET1E_66 */ { e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0, 0 }, { e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0, 0 }, - { e_vpcmpequd, t_done, 0, true, { Wpd, Hps, IK }, 0, s1W2R3R, 0 } + { e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0, 0 }, }, { /* SSET1F_66 */ { e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0, 0 }, { e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0, 0 }, @@ -7777,7 +7754,7 @@ ia32_entry sseMapTerMult[][3] = { e_vdbpsadbw, t_done, 0, true, { Vps, Hps, Wps }, 0, s1W2R3R4R, 0 } }, { /* SSET44_66 */ { e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0, 0 }, - { e_vpclmullqlqdq, t_done, 0, true, { Vps, Hps, Wps }, 0, s1W2R3R4R, 0 }, + { e_vpclmulqdq, t_done, 0, true, { Vps, Hps, Wps }, 0, s1W2R3R4R, 0 }, { e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0, 0 }, }, { /* SSET4A_66 */ { e_No_Entry, t_ill, 0, false, { Zz, Zz, Zz }, 0, 0, 0 }, @@ -10490,9 +10467,7 @@ static unsigned int ia32_decode_modrm(const unsigned int addrSzAttr, const unsig addr++; /* Get displacements we're going to use */ - const char* disp8 = (const char*)addr; - const short* disp16 = (const short*)addr; - const int* disp32 = (const int*)addr; + auto dispAddr = addr; // addrSzAttr equals 1 means the address size override prefix is // not present. On 64-bit platforms, this means the default address @@ -10526,7 +10501,7 @@ static unsigned int ia32_decode_modrm(const unsigned int addrSzAttr, const unsig macadr->set16(mDI, -1, 0); break; case 6: - macadr->set16(-1, -1, *disp16); + macadr->set16(-1, -1, Dyninst::read_memory_as(dispAddr)); if (loc) { loc->disp_position = loc->modrm_position + 1; @@ -10552,31 +10527,32 @@ static unsigned int ia32_decode_modrm(const unsigned int addrSzAttr, const unsig loc->disp_size = 1; } + auto disp8 = read_memory_as(dispAddr); switch (rm) { case 0: - macadr->set16(mBX, mSI, *disp8); + macadr->set16(mBX, mSI, disp8); break; case 1: - macadr->set16(mBX, mDI, *disp8); + macadr->set16(mBX, mDI, disp8); break; case 2: - macadr->set16(mBP, mSI, *disp8); + macadr->set16(mBP, mSI, disp8); break; case 3: - macadr->set16(mBP, mDI, *disp8); + macadr->set16(mBP, mDI, disp8); break; case 4: - macadr->set16(mSI, -1, *disp8); + macadr->set16(mSI, -1, disp8); break; case 5: - macadr->set16(mDI, -1, *disp8); + macadr->set16(mDI, -1, disp8); break; case 6: - macadr->set16(mBP, -1, *disp8); + macadr->set16(mBP, -1, disp8); break; case 7: - macadr->set16(mBX, -1, *disp8); + macadr->set16(mBX, -1, disp8); break; default: assert(0); @@ -10594,31 +10570,32 @@ static unsigned int ia32_decode_modrm(const unsigned int addrSzAttr, const unsig loc->disp_size = 2; } + auto disp16 = Dyninst::read_memory_as(dispAddr); switch (rm) { case 0: - macadr->set16(mBX, mSI, *disp16); + macadr->set16(mBX, mSI, disp16); break; case 1: - macadr->set16(mBX, mDI, *disp16); + macadr->set16(mBX, mDI, disp16); break; case 2: - macadr->set16(mBP, mSI, *disp16); + macadr->set16(mBP, mSI, disp16); break; case 3: - macadr->set16(mBP, mDI, *disp16); + macadr->set16(mBP, mDI, disp16); break; case 4: - macadr->set16(mSI, -1, *disp16); + macadr->set16(mSI, -1, disp16); break; case 5: - macadr->set16(mDI, -1, *disp16); + macadr->set16(mDI, -1, disp16); break; case 6: - macadr->set16(mBP, -1, *disp16); + macadr->set16(mBP, -1, disp16); break; case 7: - macadr->set16(mBX, -1, *disp16); + macadr->set16(mBX, -1, disp16); break; default: assert(0); @@ -10675,9 +10652,7 @@ static unsigned int ia32_decode_modrm(const unsigned int addrSzAttr, const unsig } /* Update displacement pointers */ - disp8 = (const char*)addr; - disp16 = (const short*)addr; - disp32 = (const int*)addr; + dispAddr = addr; /* this is tricky: there is a disp32 iff (1) rm == 5 or (2) hassib && base == 5 */ unsigned char check5 = hassib ? base : rm; @@ -10711,8 +10686,9 @@ static unsigned int ia32_decode_modrm(const unsigned int addrSzAttr, const unsig loc->disp_size = 4; } + auto disp32 = Dyninst::read_memory_as(dispAddr); macadr->set_sib(-1, scale, apply_rex_bit(index, pref->rexX()), - *disp32, addrSzAttr); + disp32, addrSzAttr); } else { macadr->set_sib(apply_rex_bit(base, pref->rexB()), scale, apply_rex_bit(index, pref->rexX()), 0, addrSzAttr); @@ -10727,10 +10703,11 @@ static unsigned int ia32_decode_modrm(const unsigned int addrSzAttr, const unsig loc->disp_size = 4; } + auto disp32 = Dyninst::read_memory_as(dispAddr); if (mode_64) - macadr->set(mRIP, *disp32, addrSzAttr); + macadr->set(mRIP, disp32, addrSzAttr); else - macadr->set(-1, *disp32, addrSzAttr); + macadr->set(-1, disp32, addrSzAttr); break; } case 6: @@ -10755,19 +10732,20 @@ static unsigned int ia32_decode_modrm(const unsigned int addrSzAttr, const unsig loc->disp_size = 1; } + auto disp8 = Dyninst::read_memory_as(dispAddr); switch (rm) { case 0: - macadr->set(apply_rex_bit(mEAX, pref->rexB()), *disp8, addrSzAttr); + macadr->set(apply_rex_bit(mEAX, pref->rexB()), disp8, addrSzAttr); break; case 1: - macadr->set(apply_rex_bit(mECX, pref->rexB()), *disp8, addrSzAttr); + macadr->set(apply_rex_bit(mECX, pref->rexB()), disp8, addrSzAttr); break; case 2: - macadr->set(apply_rex_bit(mEDX, pref->rexB()), *disp8, addrSzAttr); + macadr->set(apply_rex_bit(mEDX, pref->rexB()), disp8, addrSzAttr); break; case 3: - macadr->set(apply_rex_bit(mEBX, pref->rexB()), *disp8, addrSzAttr); + macadr->set(apply_rex_bit(mEBX, pref->rexB()), disp8, addrSzAttr); break; case 4: // disp8[EBP + index<disp_size = 1; } macadr->set_sib(apply_rex_bit(base, pref->rexB()), scale, apply_rex_bit(index, pref->rexX()), - *disp8, addrSzAttr); + disp8, addrSzAttr); break; case 5: - macadr->set(apply_rex_bit(mEBP, pref->rexB()), *disp8, addrSzAttr); + macadr->set(apply_rex_bit(mEBP, pref->rexB()), disp8, addrSzAttr); break; case 6: - macadr->set(apply_rex_bit(mESI, pref->rexB()), *disp8, addrSzAttr); + macadr->set(apply_rex_bit(mESI, pref->rexB()), disp8, addrSzAttr); break; case 7: - macadr->set(apply_rex_bit(mEDI, pref->rexB()), *disp8, addrSzAttr); + macadr->set(apply_rex_bit(mEDI, pref->rexB()), disp8, addrSzAttr); break; } } @@ -10800,19 +10778,20 @@ static unsigned int ia32_decode_modrm(const unsigned int addrSzAttr, const unsig loc->disp_size = 4; } + auto disp32 = Dyninst::read_memory_as(dispAddr); switch (rm) { case 0: - macadr->set(apply_rex_bit(mEAX, pref->rexB()), *disp32, addrSzAttr); + macadr->set(apply_rex_bit(mEAX, pref->rexB()), disp32, addrSzAttr); break; case 1: - macadr->set(apply_rex_bit(mECX, pref->rexB()), *disp32, addrSzAttr); + macadr->set(apply_rex_bit(mECX, pref->rexB()), disp32, addrSzAttr); break; case 2: - macadr->set(apply_rex_bit(mEDX, pref->rexB()), *disp32, addrSzAttr); + macadr->set(apply_rex_bit(mEDX, pref->rexB()), disp32, addrSzAttr); break; case 3: - macadr->set(apply_rex_bit(mEBX, pref->rexB()), *disp32, addrSzAttr); + macadr->set(apply_rex_bit(mEBX, pref->rexB()), disp32, addrSzAttr); break; case 4: // disp32[EBP + index<disp_size = 4; } macadr->set_sib(apply_rex_bit(base, pref->rexB()), scale, apply_rex_bit(index, pref->rexX()), - *disp32, addrSzAttr); + disp32, addrSzAttr); break; case 5: - macadr->set(apply_rex_bit(mEBP, pref->rexB()), *disp32, addrSzAttr); + macadr->set(apply_rex_bit(mEBP, pref->rexB()), disp32, addrSzAttr); break; case 6: - macadr->set(apply_rex_bit(mESI, pref->rexB()), *disp32, addrSzAttr); + macadr->set(apply_rex_bit(mESI, pref->rexB()), disp32, addrSzAttr); break; case 7: - macadr->set(apply_rex_bit(mEDI, pref->rexB()), *disp32, addrSzAttr); + macadr->set(apply_rex_bit(mEDI, pref->rexB()), disp32, addrSzAttr); break; default: assert(0); @@ -10953,17 +10932,17 @@ unsigned int ia32_decode_operands (const ia32_prefixes& pref, nib += wordSzB * addrSzAttr; if(mac) { - int offset = 0; + long offset = 0; switch(addrSzAttr) { case 1: // 16-bit offset - offset = *((const short int*)addr); + offset = Dyninst::read_memory_as(addr); break; case 2: // 32-bit offset - offset = *((const int*)addr); + offset = Dyninst::read_memory_as(addr); break; case 4: // 64-bit - offset = *((const long*)addr); + offset = Dyninst::read_memory_as(addr); break; default: assert(0); @@ -11741,28 +11720,28 @@ int displacement(const unsigned char *instr, unsigned type) { if(*instr == 0x38 || *instr == 0x3A) instr++; } // Skip the instr opcode and the MOD/RM byte - disp = *(const int *)(instr+2); + disp = Dyninst::read_memory_as(instr+2); } else if (type & IS_JUMP) { if (type & REL_B) { - disp = *(const char *)(instr+1); + disp = Dyninst::read_memory_as(instr+1); } else if (type & REL_W) { - disp = *(const short *)(instr+1); // skip opcode + disp = Dyninst::read_memory_as(instr+1); // skip opcode } else if (type & REL_D) { - disp = *(const int *)(instr+1); + disp = Dyninst::read_memory_as(instr+1); } } else if (type & IS_JCC) { if (type & REL_B) { - disp = *(const char *)(instr+1); + disp = Dyninst::read_memory_as(instr+1); } else if (type & REL_W) { - disp = *(const short *)(instr+2); // skip two byte opcode + disp = Dyninst::read_memory_as(instr+2); // skip two byte opcode } else if (type & REL_D) { - disp = *(const int *)(instr+2); // skip two byte opcode + disp = Dyninst::read_memory_as(instr+2); // skip two byte opcode } } else if (type & IS_CALL) { if (type & REL_W) { - disp = *(const short *)(instr+1); // skip opcode + disp = Dyninst::read_memory_as(instr+1); // skip opcode } else if (type & REL_D) { - disp = *(const int *)(instr+1); + disp = Dyninst::read_memory_as(instr+1); } } @@ -11886,7 +11865,7 @@ bool convert_to_rel32(const unsigned char*&origInsn, unsigned char *&newInsn) { //Determine appropriate scale, index, and base given SIB byte. -void decode_SIB(unsigned sib, unsigned& scale, Register& index_reg, Register& base_reg){ +void decode_SIB(unsigned sib, unsigned& scale, Dyninst::Register& index_reg, Dyninst::Register& base_reg){ scale = sib >> 6; //scale = 2^scale diff --git a/common/src/arch-x86.h b/common/src/arch-x86.h index 21a168dd7d..0e00e00af1 100644 --- a/common/src/arch-x86.h +++ b/common/src/arch-x86.h @@ -34,26 +34,24 @@ #ifndef _ARCH_X86_H #define _ARCH_X86_H -#include "common/src/Types.h" +#include "dyntypes.h" +#include +#include #include #include #include #include -#include "dyn_regs.h" #include "entryIDs.h" - +#include "registers/MachRegister.h" #include "common/src/ia32_locations.h" +#include "dyn_register.h" -#if defined(i386_unknown_nt4_0) -// disable VC++ warning C4800: (performance warning) -// forcing 'unsigned int' value to bool 'true' or 'false' -#pragma warning (disable : 4800) -#endif namespace NS_x86 { /* operand types */ -typedef char byte_t; /* a byte operand */ +/* signed char required for correct immediate value interpretation */ +typedef signed char byte_t; /* a byte operand */ typedef short word_t; /* a word (16-bit) operand */ typedef int dword_t; /* a double word (32-bit) operand */ @@ -989,8 +987,8 @@ COMMON_EXPORT unsigned get_instruction(const unsigned char *instr, unsigned &instType, const unsigned char **op_ptr, bool mode_64); /* get the target of a jump or call */ -COMMON_EXPORT Address get_target(const unsigned char *instr, unsigned type, unsigned size, - Address addr); +COMMON_EXPORT Dyninst::Address get_target(const unsigned char *instr, unsigned type, unsigned size, + Dyninst::Address addr); // Size of a jump rel32 instruction #define JUMP_REL32_SZ (6) @@ -1057,15 +1055,15 @@ class instruction { setInstruction((const unsigned char *) ptr, 0, mode_64); } - unsigned setInstruction(const unsigned char *p, Address, bool mode_64) { + unsigned setInstruction(const unsigned char *p, Dyninst::Address, bool mode_64) { ptr_ = p; size_ = get_instruction(ptr_, type_, &op_ptr_, mode_64); return size_; } // if the instruction is a jump or call, return the target, else return zero - Address getTarget(Address addr) const { - return (Address)get_target(ptr_, type_, size_, addr); + Dyninst::Address getTarget(Dyninst::Address addr) const { + return (Dyninst::Address)get_target(ptr_, type_, size_, addr); } // return the size of the instruction in bytes @@ -1090,7 +1088,7 @@ class instruction { static unsigned maxInterFunctionJumpSize(unsigned addr_width) { return maxJumpSize(addr_width); } // And tell us how much space we'll need... - COMMON_EXPORT static unsigned jumpSize(Address from, Address to, unsigned addr_width); + COMMON_EXPORT static unsigned jumpSize(Dyninst::Address from, Dyninst::Address to, unsigned addr_width); COMMON_EXPORT static unsigned jumpSize(long disp, unsigned addr_width); COMMON_EXPORT static unsigned maxJumpSize(unsigned addr_width); @@ -1131,7 +1129,7 @@ class instruction { bool isSysCallInsn() const { return op_ptr_[0] == SYSCALL[0] && op_ptr_[1] == SYSCALL[1]; } - static bool isAligned(const Address ) { return true; } + static bool isAligned(const Dyninst::Address ) { return true; } void print() { @@ -1164,17 +1162,17 @@ inline bool is_disp16(long disp) { } inline bool is_disp32(long disp) { - return (disp <= I32_MAX && disp >= I32_MIN); + return (disp <= INT32_MAX && disp >= INT32_MIN); } -inline bool is_disp32(Address a1, Address a2) { +inline bool is_disp32(Dyninst::Address a1, Dyninst::Address a2) { return is_disp32(a2 - (a1 + JUMP_REL32_SZ)); } -inline bool is_addr32(Address addr) { - return (addr < UI32_MAX); +inline bool is_addr32(Dyninst::Address addr) { + return (addr < UINT32_MAX); } COMMON_EXPORT void decode_SIB(unsigned sib, unsigned& scale, - Register& index_reg, Register& base_reg); + Dyninst::Register& index_reg, Dyninst::Register& base_reg); COMMON_EXPORT const unsigned char* skip_headers(const unsigned char*, ia32_instruction* = NULL); @@ -1182,14 +1180,14 @@ COMMON_EXPORT const unsigned char* skip_headers(const unsigned char*, /* Address bounds of new dynamic heap segments. On x86 we don't try to allocate new segments near base tramps, so heap segments can be allocated anywhere (the tramp address "x" is ignored). */ -inline Address region_lo(const Address /*x*/) { return 0x00000000; } -inline Address region_hi(const Address /*x*/) { return 0xf0000000; } +inline Dyninst::Address region_lo(const Dyninst::Address /*x*/) { return 0x00000000; } +inline Dyninst::Address region_hi(const Dyninst::Address /*x*/) { return 0xf0000000; } #if defined(arch_x86_64) // range functions for AMD64 -inline Address region_lo_64(const Address x) { return x & 0xffffffff80000000; } -inline Address region_hi_64(const Address x) { return x | 0x000000007fffffff; } +inline Dyninst::Address region_lo_64(const Dyninst::Address x) { return x & 0xffffffff80000000; } +inline Dyninst::Address region_hi_64(const Dyninst::Address x) { return x | 0x000000007fffffff; } #endif diff --git a/common/src/concurrent.C b/common/src/concurrent.C index da959985b5..c3037ce69c 100644 --- a/common/src/concurrent.C +++ b/common/src/concurrent.C @@ -75,18 +75,18 @@ void dyn_c_annotations::rwdeinit(void* ptr) { } void dyn_c_annotations::wlock(void* ptr) { ANNOTATE_RWLOCK_ACQUIRED(ptr, 1 /* writer mode */); - ANNOTATE_HAPPENS_AFTER(ptr + 1); // After all the readers + ANNOTATE_HAPPENS_AFTER(static_cast(ptr) + 1); // After all the readers } void dyn_c_annotations::wunlock(void* ptr) { - ANNOTATE_HAPPENS_BEFORE(ptr + 2); + ANNOTATE_HAPPENS_BEFORE(static_cast(ptr) + 2); ANNOTATE_RWLOCK_RELEASED(ptr, 1 /* writer mode */); } void dyn_c_annotations::rlock(void* ptr) { ANNOTATE_RWLOCK_ACQUIRED(ptr, 0 /* reader mode */); - ANNOTATE_HAPPENS_AFTER(ptr + 2); // After the last writer + ANNOTATE_HAPPENS_AFTER(static_cast(ptr) + 2); // After the last writer } void dyn_c_annotations::runlock(void* ptr) { - ANNOTATE_HAPPENS_BEFORE(ptr + 1); + ANNOTATE_HAPPENS_BEFORE(static_cast(ptr) + 1); ANNOTATE_RWLOCK_RELEASED(ptr, 0 /* reader mode */); } #endif diff --git a/common/src/debug_common.C b/common/src/debug_common.C index ee5b69e800..b2bbed4b47 100644 --- a/common/src/debug_common.C +++ b/common/src/debug_common.C @@ -40,11 +40,6 @@ int common_debug_lineinfo = 0; int common_debug_parsing = 0; int common_debug_initialized = 0; -#if defined(_MSC_VER) -#pragma warning(push) -#pragma warning(disable:4996) -#endif - bool init_debug_common() { if (common_debug_initialized) return true; common_debug_initialized = 1; @@ -125,8 +120,3 @@ int common_parsing_printf_int(const char *format, ...) return ret; } - -#if defined(_MSC_VER) -#pragma warning(pop) -#endif - diff --git a/common/src/dthread.h b/common/src/dthread.h index b9e551942a..68e79b50d4 100644 --- a/common/src/dthread.h +++ b/common/src/dthread.h @@ -35,13 +35,13 @@ #include "util.h" #include -#include -#include -#include -#include -#include -#include -#include +#include +#include +#include +#include + + +#include #if !defined(os_windows) #define cap_pthreads @@ -85,12 +85,12 @@ class PC_EXPORT DThread { template struct boost_mutex_selector { - typedef boost::mutex mutex; + typedef dyncompat::mutex mutex; }; template<> struct boost_mutex_selector { - typedef boost::recursive_mutex mutex; + typedef dyncompat::recursive_mutex mutex; }; template @@ -103,7 +103,7 @@ class PC_EXPORT Mutex : public boost_mutex_selector::mutex { template > class PC_EXPORT CondVar { - boost::condition_variable_any cond; + dyncompat::condition_variable_any cond; mutex_t *mutex; bool created_mutex; public: @@ -117,6 +117,11 @@ class PC_EXPORT CondVar { } ~CondVar() { if(created_mutex) delete mutex; } + CondVar(CondVar const&) = delete; + CondVar& operator=(CondVar const&) = delete; + CondVar(CondVar &&) = delete; + CondVar& operator=(CondVar &&rhs) = delete; + void unlock() { mutex->unlock(); } bool trylock() { return mutex->try_lock(); } void lock() { mutex->lock(); } @@ -127,10 +132,10 @@ class PC_EXPORT CondVar { }; template > -class ScopeLock : public boost::interprocess::scoped_lock +class ScopeLock : public dyncompat::interprocess::scoped_lock { public: - ScopeLock(Mut &mut) : boost::interprocess::scoped_lock(mut) {} + ScopeLock(Mut &mut) : dyncompat::interprocess::scoped_lock(mut) {} }; diff --git a/dyninstAPI/src/dyninst.h b/common/src/dyn_register.h similarity index 76% rename from dyninstAPI/src/dyninst.h rename to common/src/dyn_register.h index fc127c448d..6deac6a573 100644 --- a/dyninstAPI/src/dyninst.h +++ b/common/src/dyn_register.h @@ -1,41 +1,49 @@ /* * See the dyninst/COPYRIGHT file for copyright information. - * + * * We provide the Paradyn Tools (below described as "Paradyn") * on an AS IS basis, and do not warrant its validity or performance. * We reserve the right to update, modify, or discontinue this * software at any time. We shall have no obligation to supply such * updates or modifications or any other form of support to you. - * + * * By your use of Paradyn, you understand and agree that we (or any * other person or entity with proprietary rights in Paradyn) are * under no obligation to provide either maintenance services, * update services, notices of latent defects, or correction of * defects for Paradyn. - * + * * This library is free software; you can redistribute it and/or * modify it under the terms of the GNU Lesser General Public * License as published by the Free Software Foundation; either * version 2.1 of the License, or (at your option) any later version. - * + * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU * Lesser General Public License for more details. - * + * * You should have received a copy of the GNU Lesser General Public * License along with this library; if not, write to the Free Software * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ -// $Id: dyninst.h,v 1.20 2006/07/07 00:01:02 jaw Exp $ -// dyninst.h - exported interface to instrumentation. +#ifndef DYNINST_REGISTER +#define DYNINST_REGISTER -#ifndef INSTRUMENTATION_H -#define INSTRUMENTATION_H +namespace Dyninst { +/* This needs to be an int since it is sometimes used to pass offsets + to the code generator (i.e. if-statement) - jkh 5/24/99 */ -#include "dyninstAPI_RT/h/dyninstAPI_RT.h" -#include "common/src/stringDecl.h" +/* a register number, e.g., [0..31] */ +typedef unsigned int Register; +/* register content 64-bit */ +typedef long long int RegValue; + +/* '255' */ +constexpr Register Null_Register{static_cast(-1)}; + +} #endif diff --git a/common/src/dyn_regs.C b/common/src/dyn_regs.C index e64a16fb17..3fcd194a71 100644 --- a/common/src/dyn_regs.C +++ b/common/src/dyn_regs.C @@ -28,2213 +28,8 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +//clang-format: off #define DYN_DEFINE_REGS -#include "common/h/dyn_regs.h" -#include "common/src/debug_common.h" - -#include "external/rose/rose-compat.h" -#include "external/rose/powerpcInstructionEnum.h" -#include "external/rose/armv8InstructionEnum.h" -#include "external/rose/amdgpuInstructionEnum.h" -#include - -using namespace Dyninst; - -boost::shared_ptr MachRegister::names() -{ - static boost::shared_ptr store = - boost::shared_ptr(new MachRegister::NameMap); - return store; -} - -MachRegister::MachRegister() : - reg(0) -{ -} - -MachRegister::MachRegister(signed int r) : - reg(r) -{ -} - -MachRegister::MachRegister(signed int r, const char *n) : - reg(r) -{ - (*names())[r] = std::string(n); -} - -MachRegister::MachRegister(signed int r, std::string n) : - reg(r) -{ - (*names())[r] = n; -} - -unsigned int MachRegister::regClass() const -{ - return reg & 0x00ff0000; -} - -MachRegister MachRegister::getBaseRegister() const { - signed int category = (reg & 0x00ff0000); - switch (getArchitecture()) { - case Arch_x86: - if (category == x86::GPR) return MachRegister(reg & 0xfffff0ff); - else if (category == x86::FLAG) return x86::flags; - else return *this; - case Arch_x86_64: - if (category == x86_64::GPR) return MachRegister(reg & 0xfffff0ff); - else if (category == x86_64::FLAG) return x86_64::flags; - else return *this; - case Arch_ppc32: - case Arch_ppc64: - case Arch_none: - return *this; - case Arch_amdgpu_vega: - switch (category){ - case amdgpu_vega::SGPR: - case amdgpu_vega::SGPR_VEC2: - case amdgpu_vega::SGPR_VEC4: - case amdgpu_vega::SGPR_VEC8: - case amdgpu_vega::SGPR_VEC16: - return MachRegister( (reg & 0x000000ff) | amdgpu_vega::sgpr0); - case amdgpu_vega::VGPR: - case amdgpu_vega::VGPR_VEC2: - case amdgpu_vega::VGPR_VEC4: - case amdgpu_vega::VGPR_VEC8: - case amdgpu_vega::VGPR_VEC16: - return MachRegister( (reg & 0x000000ff) | amdgpu_vega::vgpr0); - case amdgpu_vega::HWR: - return MachRegister(reg); - - default: - return *this; - } - case Arch_aarch32: - case Arch_aarch64: - case Arch_intelGen9: - case Arch_cuda: - //not verified - return *this; - default: - return InvalidReg; - } - return InvalidReg; -} - -Architecture MachRegister::getArchitecture() const { - return (Architecture) (reg & 0xff000000); -} - -bool MachRegister::isValid() const { - return (reg != InvalidReg.reg); -} - -MachRegisterVal MachRegister::getSubRegValue(const MachRegister& subreg, - MachRegisterVal &orig) const -{ - if (subreg.reg == reg || - getArchitecture() == Arch_ppc32 || - getArchitecture() == Arch_ppc64) - return orig; - - assert(subreg.getBaseRegister() == getBaseRegister()); - switch ((subreg.reg & 0x00000f00) >> 8) { - case 0x0: return orig; - case 0x1: return (orig & 0xff); - case 0x2: return (orig & 0xff00) >> 8; - case 0x3: return (orig & 0xffff); - case 0xf: return (orig & 0xffffffff); - default: assert(0); return orig; - } -} - -std::string MachRegister::name() const { - assert(names() != NULL); - NameMap::const_iterator iter = names()->find(reg); - - std::string ret; - if (iter != names()->end()) { - if ( getArchitecture() == Arch_amdgpu_vega){ - signed int category = reg & 0x00ff0000; - signed int base_val = reg & 0x000000ff; - switch(category){ - case amdgpu_vega::SGPR_VEC2: - base_val -= (amdgpu_vega::sgpr_vec2_0&0xff); - ret = std::string("SGPR["+std::to_string(base_val)+"-"+std::to_string(base_val+1)+"]"); - break; - case amdgpu_vega::VGPR_VEC2: - base_val -= (amdgpu_vega::vgpr_vec2_0&0xff); - ret = std::string("VGPR["+std::to_string(base_val)+"-"+std::to_string(base_val+1)+"]"); - break; - case amdgpu_vega::SGPR_VEC4: - base_val -= (amdgpu_vega::sgpr_vec4_0&0xff); - ret = std::string("SGPR["+std::to_string(base_val)+"-"+std::to_string(base_val+3)+"]"); - break; - case amdgpu_vega::VGPR_VEC4: - base_val -= (amdgpu_vega::vgpr_vec4_0&0xff); - ret = std::string("VGPR["+std::to_string(base_val)+"-"+std::to_string(base_val+3)+"]"); - break; - case amdgpu_vega::SGPR_VEC8: - base_val -= (amdgpu_vega::sgpr_vec8_0&0xff); - ret = std::string("SGPR["+std::to_string(base_val)+"-"+std::to_string(base_val+7)+"]"); - break; - case amdgpu_vega::VGPR_VEC8: - base_val -= (amdgpu_vega::vgpr_vec8_0&0xff); - ret = std::string("VGPR["+std::to_string(base_val)+"-"+std::to_string(base_val+7)+"]"); - break; - case amdgpu_vega::SGPR_VEC16: - base_val -= (amdgpu_vega::sgpr_vec16_0&0xff); - ret = std::string("SGPR["+std::to_string(base_val)+"-"+std::to_string(base_val+15)+"]"); - break; - case amdgpu_vega::VGPR_VEC16: - base_val -= (amdgpu_vega::vgpr_vec16_0&0xff); - ret = std::string("VGPR["+std::to_string(base_val)+"-"+std::to_string(base_val+15)+"]"); - break; - default: - ret = iter->second; - break; - } - return ret; - }else{ - return iter->second; - } - } - common_parsing_printf(" can't find register with index %x\n", (unsigned int)reg); - return std::string(""); - -} - -unsigned int MachRegister::size() const { - switch (getArchitecture()) - { - case Arch_x86: - switch (reg & 0x0000ff00) { - case x86::L_REG: //L_REG - case x86::H_REG: //H_REG - return 1; - case x86::W_REG: //W_REG - return 2; - case x86::FULL: //FULL - return 4; - // Commented out because no register - // is defined with this size type - //case x86::QUAD: - // return 8; - case x86::OCT: - return 16; - case x86::FPDBL: - return 10; - case x86::BIT: - return 0; - case x86::YMMS: - return 32; - case x86::ZMMS: - return 64; - default: - return 0;//KEVINTODO: removed sanity-check assert because of asprotect fuzz testing, could use this as a sign that the parse has gone into junk - assert(0); - } - case Arch_x86_64: - switch (reg & 0x0000ff00) { - case x86_64::L_REG: //L_REG - case x86_64::H_REG: //H_REG - return 1; - case x86_64::W_REG: //W_REG - return 2; - case x86_64::FULL: //FULL - return 8; - case x86_64::D_REG: - return 4; - case x86_64::OCT: - return 16; - case x86_64::FPDBL: - return 10; - case x86_64::BIT: - return 0; - case x86_64::YMMS: - return 32; - case x86_64::ZMMS: - return 64; - default: - return 0; // Xiaozhu: do not assert, but return 0 as an indication of parsing junk. - assert(0); - } - case Arch_ppc32: { - int reg_class = reg & 0x00ff0000; - if (reg_class == ppc32::FPR || reg_class == ppc32::FSR) - return 8; - return 4; - } - case Arch_ppc64: { - if((reg & 0x00ff0000) == aarch64::FPR) - return 16; - return 8; - } - case Arch_aarch32: - assert(0); - break; - - case Arch_cuda: - return 8; - case Arch_amdgpu_vega:{ - int reg_class = (reg&0x00ff0000 ) ; - if ( reg_class == amdgpu_vega::SGPR || reg_class == amdgpu_vega::VGPR){ - return 4; - }else if (reg_class == amdgpu_vega::SGPR_VEC2 || reg_class == amdgpu_vega::VGPR_VEC2){ - return 8; - }else if (reg_class == amdgpu_vega::SGPR_VEC4 || reg_class == amdgpu_vega::VGPR_VEC4){ - return 16; - }else if (reg_class == amdgpu_vega::SGPR_VEC8 || reg_class == amdgpu_vega::VGPR_VEC8){ - return 32; - }else if (reg_class == amdgpu_vega::SGPR_VEC16 || reg_class == amdgpu_vega::VGPR_VEC16){ - return 64; - }else{ - switch(reg & 0x00007f00){ - case amdgpu_vega::BITS_1: - case amdgpu_vega::BITS_2: - case amdgpu_vega::BITS_3: - case amdgpu_vega::BITS_4: - case amdgpu_vega::BITS_6: - case amdgpu_vega::BITS_7: - case amdgpu_vega::BITS_8: - return 1; - case amdgpu_vega::BITS_9: - case amdgpu_vega::BITS_15: - case amdgpu_vega::BITS_16: - return 2; - case amdgpu_vega::BITS_32: - return 4; - case amdgpu_vega::BITS_48: - case amdgpu_vega::BITS_64: - return 8; - case amdgpu_vega::BITS_128: - return 16; - case amdgpu_vega::BITS_256: - return 32; - case amdgpu_vega::BITS_512: - return 64; - } - common_parsing_printf(" unknown reg size %x\n", (unsigned int)reg); - assert(0); - } - } - case Arch_aarch64:{ - if((reg & 0x00ff0000) == aarch64::FPR) - { - switch(reg & 0x0000ff00) - { - case aarch64::B_REG: return 1; - case aarch64::W_REG: return 2; - case aarch64::D_REG: return 4; - case aarch64::FULL: - case aarch64::HQ_REG: return 8; - case aarch64::Q_REG: return 16; - default: - assert(0); - return 0; - } - } - else if((reg & 0x00ff0000) == aarch64::GPR || (reg & 0x00ff0000) == aarch64::SPR || - (reg & 0x00ff0000) == aarch64::SYSREG || (reg & 0x00ff0000) == aarch64::FLAG) - switch(reg & 0x0000ff00) - { - case aarch64::FULL : return 8; - case aarch64::D_REG: return 4; - case aarch64::BIT: return 0; - default: return 0; - } - else - return 4; - break; - } - case Arch_amdgpu_rdna: - case Arch_intelGen9: - { - assert(0); - break; - } - - case Arch_none: - return 0; - } - return 0; //Unreachable, but disable warnings -} - -bool MachRegister::operator<(const MachRegister &a) const { - return (reg < a.reg); -} - -bool MachRegister::operator==(const MachRegister &a) const { - return (reg == a.reg); -} - -MachRegister::operator signed int() const { - return reg; -} - -signed int MachRegister::val() const { - return reg; -} - - -MachRegister MachRegister::getPC(Dyninst::Architecture arch) -{ - switch (arch) - { - case Arch_x86: - return x86::eip; - case Arch_x86_64: - return x86_64::rip; - case Arch_ppc32: - return ppc32::pc; - case Arch_ppc64: - return ppc64::pc; - case Arch_aarch64: //aarch64: pc is not writable - return aarch64::pc; - case Arch_aarch32: - return InvalidReg; - case Arch_cuda: - return cuda::pc; - case Arch_intelGen9: - return InvalidReg; - case Arch_amdgpu_vega: - return amdgpu_vega::pc; - case Arch_amdgpu_rdna: - case Arch_none: - return InvalidReg; - } - return InvalidReg; -} - - -MachRegister MachRegister::getReturnAddress(Dyninst::Architecture arch) -{ - switch (arch) - { - case Arch_x86: - assert(0); //not implemented - case Arch_x86_64: - assert(0); //not implemented - case Arch_ppc32: - assert(0); //not implemented - case Arch_ppc64: - assert(0); //not implemented - case Arch_aarch64: //aarch64: x30 stores the RA for current frame - return aarch64::x30; - case Arch_aarch32: - case Arch_cuda: - case Arch_amdgpu_vega: // TODO:Since amdgpu functions are all inlined, the return address is highly likely in sgpr[30:31] - case Arch_amdgpu_rdna: - case Arch_intelGen9: - assert(0); - case Arch_none: - return InvalidReg; - } - return InvalidReg; -} - -MachRegister MachRegister::getFramePointer(Dyninst::Architecture arch) -{ - switch (arch) - { - case Arch_x86: - return x86::ebp; - case Arch_x86_64: - return x86_64::rbp; - case Arch_ppc32: - return ppc32::r1; - case Arch_ppc64: - return ppc64::r1; - case Arch_aarch64: - return aarch64::x29; //aarch64: frame pointer is X29 by convention - - case Arch_amdgpu_vega: - case Arch_none: - return InvalidReg; - - default: - assert(0); - return InvalidReg; - } - return InvalidReg; -} - -MachRegister MachRegister::getStackPointer(Dyninst::Architecture arch) -{ - switch (arch) - { - case Arch_x86: - return x86::esp; - case Arch_x86_64: - return x86_64::rsp; - case Arch_ppc32: - return ppc32::r1; - case Arch_ppc64: - return ppc64::r1; - case Arch_aarch64: - return aarch64::sp; //aarch64: stack pointer is an independent register - case Arch_aarch32: - case Arch_cuda: - assert(0); - case Arch_none: - case Arch_amdgpu_vega: - return InvalidReg; - default: - assert(0); - return InvalidReg; - } - return InvalidReg; -} - -MachRegister MachRegister::getSyscallNumberReg(Dyninst::Architecture arch) -{ - switch (arch) - { - case Arch_x86: - return x86::eax; - case Arch_x86_64: - return x86_64::rax; - case Arch_ppc32: - return ppc32::r0; - case Arch_ppc64: - return ppc64::r0; - case Arch_aarch64: - return aarch64::x8; - case Arch_aarch32: - case Arch_cuda: - case Arch_amdgpu_vega: - assert(0); - case Arch_none: - return InvalidReg; - default: - assert(0); - return InvalidReg; - } - return InvalidReg; -} - -MachRegister MachRegister::getSyscallNumberOReg(Dyninst::Architecture arch) -{ - switch (arch) - { - case Arch_x86: - return x86::oeax; - case Arch_x86_64: - return x86_64::orax; - case Arch_ppc32: - return ppc32::r0; - case Arch_ppc64: - return ppc64::r0; - case Arch_aarch64: - return aarch64::x8; - case Arch_none: - return InvalidReg; - default: - assert(0); - return InvalidReg; - } - return InvalidReg; -} - -MachRegister MachRegister::getSyscallReturnValueReg(Dyninst::Architecture arch) -{ - switch (arch) - { - case Arch_x86: - return x86::eax; - case Arch_x86_64: - return x86_64::rax; - case Arch_ppc32: - return ppc32::r3; - case Arch_ppc64: - return ppc64::r3; - case Arch_aarch64: - return aarch64::x0; //returned value is save in x0 - case Arch_none: - return InvalidReg; - default: - assert(0); - return InvalidReg; - } - return InvalidReg; -} - -MachRegister MachRegister::getArchRegFromAbstractReg(MachRegister abstract, - Dyninst::Architecture arch) { - switch(arch){ - case Arch_aarch64: - if( abstract == ReturnAddr) - return aarch64::x30; - if( abstract == FrameBase) - return aarch64::x29; - if( abstract == StackTop) - return aarch64::sp; - if( abstract == CFA) - assert(0); //don't know what to do - //not abstract, return arch reg - return abstract; - default: - assert(0); - } - - return Dyninst::InvalidReg; -} - -MachRegister MachRegister::getZeroFlag(Dyninst::Architecture arch) -{ - switch (arch) - { - case Arch_x86: - return x86::zf; - case Arch_x86_64: - return x86_64::zf; - case Arch_aarch64: - return aarch64::z; - case Arch_aarch32: - assert(!"Not implemented"); - case Arch_ppc32: - return ppc32::cr0e; - case Arch_ppc64: - return ppc64::cr0e; - case Arch_cuda: - case Arch_amdgpu_vega: - assert(0); - case Arch_none: - return InvalidReg; - default: - return InvalidReg; - } - - return InvalidReg; -} - - -bool MachRegister::isPC() const -{ - return (*this == x86_64::rip || *this == x86::eip || - *this == ppc32::pc || *this == ppc64::pc || - *this == aarch64::pc ); -} - -bool MachRegister::isFramePointer() const -{ - return (*this == x86_64::rbp || *this == x86::ebp || - *this == FrameBase || - *this == aarch64::x29); -} - -bool MachRegister::isStackPointer() const -{ - return (*this == x86_64::rsp || *this == x86::esp || - *this == ppc32::r1 || *this == ppc64::r1 || - *this == aarch64::sp); -} - -bool MachRegister::isSyscallNumberReg() const -{ - return ( *this == x86_64::orax || *this == x86::oeax || - *this == ppc32::r1 || *this == ppc64::r1 || - *this == aarch64::x8 - ); -} - -bool MachRegister::isSyscallReturnValueReg() const -{ - if(getArchitecture() == Arch_aarch64) - assert(0); - return (*this == x86_64::rax || *this == x86::eax || - *this == ppc32::r1 || *this == ppc64::r1 || - *this == aarch64::x0 - ); -} - -bool MachRegister::isFlag() const -{ - int regC = regClass(); - switch (getArchitecture()) - { - case Arch_x86: - return regC == x86::FLAG; - case Arch_x86_64: - return regC == x86_64::FLAG; - case Arch_aarch64: - return regC == aarch64::FLAG; - case Arch_ppc32: - case Arch_ppc64:{ - // For power, we have a different register representation. - // We do not use the subrange field for MachReigsters - // and all lower 32 bits are base ID - int baseID = reg & 0x0000FFFF; - return (baseID <= 731 && baseID >= 700) || (baseID <= 629 && baseID >= 621); - } - case Arch_amdgpu_vega:{ - return (reg & 0x0000F000); - } - case Arch_cuda: - return false; - - default: - assert(!"Not implemented!"); - } - return false; -} - -bool MachRegister::isZeroFlag() const -{ - switch (getArchitecture()) - { - case Arch_x86: - return *this == x86::zf; - case Arch_x86_64: - return *this == x86_64::zf; - case Arch_aarch64: - return *this == aarch64::z; - case Arch_ppc32: - case Arch_ppc64:{ - // For power, we have a different register representation. - // We do not use the subrange field for MachReigsters - // and all lower 32 bits are base ID - int baseID = reg & 0x0000FFFF; - return (baseID <= 731 && baseID >= 700 && baseID % 4 == 2) || (baseID <= 628 && baseID >= 621); - } - default: - assert(!"Not implemented!"); - } - return false; -} - -COMMON_EXPORT bool Dyninst::isSegmentRegister(int regClass) -{ - return 0 != (regClass & x86::SEG); -} - - -// reg_idx needs to be set as the offset from base register -// offset needs to be set as the offset inside the register - -void MachRegister::getAMDGPUROSERegister(int ®_class, int ®_idx, int &offset){ - signed int category = (reg & 0x00ff0000); - //signed int subrange = (reg & 0x0000ff00); TODO:subrange is used to identify flags within the range of a single register - signed int baseID = (reg & 0x000000ff); - //std::cout << "calling " << __func__ << " category = " << category << std::endl; - offset = 0; - reg_idx = baseID; - switch(category){ - case amdgpu_vega::SGPR:{ - reg_class = amdgpu_regclass_sgpr; - break; - } - case amdgpu_vega::VGPR: { - reg_class = amdgpu_regclass_vgpr; - break; - } - case amdgpu_vega::PC: { - reg_class = amdgpu_regclass_pc; - reg_idx = amdgpu_pc; - break; - } - case amdgpu_vega::SGPR_VEC2:{ - reg_class = amdgpu_regclass_sgpr_vec2; - break; - } - default:{ - assert(0 && "un suppoprted register type for amdgpu "); - } - - } - return; -} - -/* This function should has a boolean return value - * to indicate whether there is a corresponding - * ROSE register. - * - * Since historically, this function does not - * have a return value. We set c to -1 to represent - * error cases - * c is set to regClass - * n is set to regNum - * p is set to regPosition - * see dataflowAPI/src/ExpressionConversionVisitor.C - */ - -void MachRegister::getROSERegister(int &c, int &n, int &p) -{ - // Rose: class, number, position - // Dyninst: category, base id, subrange - if (getArchitecture()==Arch_amdgpu_vega){ - getAMDGPUROSERegister(c,n,p); - return; - } - signed int category = (reg & 0x00ff0000); - signed int subrange = (reg & 0x0000ff00); - signed int baseID = (reg & 0x000000ff); - - switch (getArchitecture()) { - case Arch_x86: - switch (category) { - case x86::GPR: - c = x86_regclass_gpr; - switch (baseID) { - case x86::BASEA: - n = x86_gpr_ax; - break; - case x86::BASEC: - n = x86_gpr_cx; - break; - case x86::BASED: - n = x86_gpr_dx; - break; - case x86::BASEB: - n = x86_gpr_bx; - break; - case x86::BASESP: - n = x86_gpr_sp; - break; - case x86::BASEBP: - n = x86_gpr_bp; - break; - case x86::BASESI: - n = x86_gpr_si; - break; - case x86::BASEDI: - n = x86_gpr_di; - break; - default: - n = 0; - break; - } - break; - case x86::SEG: - c = x86_regclass_segment; - switch (baseID) { - case 0x0: - n = x86_segreg_ds; - break; - case 0x1: - n = x86_segreg_es; - break; - case 0x2: - n = x86_segreg_fs; - break; - case 0x3: - n = x86_segreg_gs; - break; - case 0x4: - n = x86_segreg_cs; - break; - case 0x5: - n = x86_segreg_ss; - break; - default: - n = 0; - break; - } - break; - case x86::FLAG: - c = x86_regclass_flags; - switch(baseID) { - case x86::CF: - n = x86_flag_cf; - break; - case x86::PF: - n = x86_flag_pf; - break; - case x86::AF: - n = x86_flag_af; - break; - case x86::ZF: - n = x86_flag_zf; - break; - case x86::SF: - n = x86_flag_sf; - break; - case x86::TF: - n = x86_flag_tf; - break; - case x86::IF: - n = x86_flag_if; - break; - case x86::DF: - n = x86_flag_df; - break; - case x86::OF: - n = x86_flag_of; - break; - default: - assert(0); - break; - } - break; - case x86::MISC: - c = x86_regclass_unknown; - break; - case x86::XMM: - c = x86_regclass_xmm; - n = baseID; - break; - case x86::MMX: - c = x86_regclass_mm; - n = baseID; - break; - case x86::CTL: - c = x86_regclass_cr; - n = baseID; - break; - case x86::DBG: - c = x86_regclass_dr; - n = baseID; - break; - case x86::TST: - c = x86_regclass_unknown; - break; - case 0: - switch (baseID) { - case 0x10: - c = x86_regclass_ip; - n = 0; - break; - default: - c = x86_regclass_unknown; - break; - } - break; - } - break; - case Arch_x86_64: - switch (category) { - case x86_64::GPR: - c = x86_regclass_gpr; - switch (baseID) { - case x86_64::BASEA: - n = x86_gpr_ax; - break; - case x86_64::BASEC: - n = x86_gpr_cx; - break; - case x86_64::BASED: - n = x86_gpr_dx; - break; - case x86_64::BASEB: - n = x86_gpr_bx; - break; - case x86_64::BASESP: - n = x86_gpr_sp; - break; - case x86_64::BASEBP: - n = x86_gpr_bp; - break; - case x86_64::BASESI: - n = x86_gpr_si; - break; - case x86_64::BASEDI: - n = x86_gpr_di; - break; - case x86_64::BASE8: - n = x86_gpr_r8; - break; - case x86_64::BASE9: - n = x86_gpr_r9; - break; - case x86_64::BASE10: - n = x86_gpr_r10; - break; - case x86_64::BASE11: - n = x86_gpr_r11; - break; - case x86_64::BASE12: - n = x86_gpr_r12; - break; - case x86_64::BASE13: - n = x86_gpr_r13; - break; - case x86_64::BASE14: - n = x86_gpr_r14; - break; - case x86_64::BASE15: - n = x86_gpr_r15; - break; - default: - n = 0; - break; - } - break; - case x86_64::SEG: - c = x86_regclass_segment; - switch (baseID) { - case 0x0: - n = x86_segreg_ds; - break; - case 0x1: - n = x86_segreg_es; - break; - case 0x2: - n = x86_segreg_fs; - break; - case 0x3: - n = x86_segreg_gs; - break; - case 0x4: - n = x86_segreg_cs; - break; - case 0x5: - n = x86_segreg_ss; - break; - default: - n = 0; - break; - } - break; - case x86_64::FLAG: - c = x86_regclass_flags; - switch(baseID) { - case x86_64::CF: - n = x86_flag_cf; - break; - case x86_64::PF: - n = x86_flag_pf; - break; - case x86_64::AF: - n = x86_flag_af; - break; - case x86_64::ZF: - n = x86_flag_zf; - break; - case x86_64::SF: - n = x86_flag_sf; - break; - case x86_64::TF: - n = x86_flag_tf; - break; - case x86_64::IF: - n = x86_flag_if; - break; - case x86_64::DF: - n = x86_flag_df; - break; - case x86_64::OF: - n = x86_flag_of; - break; - default: - c = -1; - return; - break; - } - break; - case x86_64::MISC: - c = x86_regclass_unknown; - break; - case x86_64::KMASK: - c = x86_regclass_kmask; - n = baseID; - break; - case x86_64::ZMM: - c = x86_regclass_zmm; - n = baseID; - break; - case x86_64::YMM: - c = x86_regclass_ymm; - n = baseID; - break; - case x86_64::XMM: - c = x86_regclass_xmm; - n = baseID; - break; - case x86_64::MMX: - c = x86_regclass_mm; - n = baseID; - break; - case x86_64::CTL: - c = x86_regclass_cr; - n = baseID; - break; - case x86_64::DBG: - c = x86_regclass_dr; - n = baseID; - break; - case x86_64::TST: - c = x86_regclass_unknown; - break; - case 0: - switch (baseID) { - case 0x10: - c = x86_regclass_ip; - n = 0; - break; - default: - c = x86_regclass_unknown; - break; - } - break; - } - break; - case Arch_ppc32: - case Arch_ppc64: // 64-bit not supported in ROSE - { - baseID = reg & 0x0000FFFF; - n = baseID; - switch(category) - { - case ppc32::GPR: - c = powerpc_regclass_gpr; - break; - case ppc32::FPR: - case ppc32::FSR: - c = powerpc_regclass_fpr; - break; - case ppc32::SPR: - { - if(baseID < 613) { - c = powerpc_regclass_spr; - } else if(baseID < 621 ) { - c = powerpc_regclass_sr; - } else { - c = powerpc_regclass_cr; - n = 0; - p = baseID - 621; - /* n = baseID - 621; - if(n > 7) { - n = 0; - p = powerpc_condreggranularity_whole; - } else { - p = powerpc_condreggranularity_field; - } - */ - } - } - break; - default: - c = -1; - return; - } - return; - } - break; - case Arch_aarch64: { - p = 0; - switch (category) { - case aarch64::GPR: { - c = armv8_regclass_gpr; - int regnum = baseID - (aarch64::x0 & 0xFF); - n = armv8_gpr_r0 + regnum; - } - break; - case aarch64::SPR: { - n = 0; - if (baseID == (aarch64::pstate & 0xFF)) { - c = armv8_regclass_pstate; - } else if(baseID == (aarch64::xzr & 0xFF) || baseID == (aarch64::wzr & 0xFF)) { - c = armv8_regclass_gpr; - n = armv8_gpr_zr; - } else if (baseID == (aarch64::pc & 0xFF)) { - c = armv8_regclass_pc; - } else if (baseID == (aarch64::sp & 0xFF) || baseID == (aarch64::wsp & 0xFF)) { - c = armv8_regclass_sp; - } - } - break; - case aarch64::FPR: { - c = armv8_regclass_simd_fpr; - - int firstRegId; - switch(reg & 0xFF00) { - case aarch64::Q_REG: firstRegId = (aarch64::q0 & 0xFF); - break; - case aarch64::HQ_REG: firstRegId = (aarch64::hq0 & 0xFF); - p = 64; - break; - case aarch64::FULL: firstRegId = (aarch64::d0 & 0xFF); - break; - case aarch64::D_REG: firstRegId = (aarch64::s0 & 0xFF); - break; - case aarch64::W_REG: firstRegId = (aarch64::h0 & 0xFF); - break; - case aarch64::B_REG: firstRegId = (aarch64::b0 & 0xFF); - break; - default:assert(!"invalid register subcategory for ARM64!"); - break; - } - n = armv8_simdfpr_v0 + (baseID - firstRegId); - } - break; - case aarch64::FLAG: { - c = armv8_regclass_pstate; - n = 0; - switch (baseID) { - case aarch64::N_FLAG: - p = armv8_pstatefield_n; - break; - case aarch64::Z_FLAG: - p = armv8_pstatefield_z; - break; - case aarch64::V_FLAG: - p = armv8_pstatefield_v; - break; - case aarch64::C_FLAG: - p = armv8_pstatefield_c; - break; - default: - c = -1; - return; - } - } - break; - default: - // We do not want to assert here. - // Set these output variable to invalid values and let the - // semantics code to throw exceptions - p = -1; - c = -1; - n = -1; - // assert(!"unknown register type!"); - break; - } - return; - } - break; - default: - c = x86_regclass_unknown; - n = 0; - break; - } - - switch (getArchitecture()) { - case Arch_x86: - switch (subrange) { - case x86::OCT: - case x86::FPDBL: - p = x86_regpos_qword; - break; - case x86::H_REG: - p = x86_regpos_high_byte; - break; - case x86::L_REG: - p = x86_regpos_low_byte; - break; - case x86::W_REG: - p = x86_regpos_word; - break; - case x86::FULL: - case x86_64::D_REG: - p = x86_regpos_dword; - break; - case x86::BIT: - p = x86_regpos_all; - break; - } - break; - - case Arch_x86_64: - switch (subrange) { - case x86::FULL: - case x86::OCT: - case x86::FPDBL: - p = x86_regpos_qword; - break; - case x86::H_REG: - p = x86_regpos_high_byte; - break; - case x86::L_REG: - p = x86_regpos_low_byte; - break; - case x86::W_REG: - p = x86_regpos_word; - break; - case x86_64::D_REG: - p = x86_regpos_dword; - break; - case x86::BIT: - p = x86_regpos_all; - break; - } - break; - case Arch_aarch64: - { - c = -1; - return; - } - default: - p = x86_regpos_unknown; - } -} - -MachRegister MachRegister::DwarfEncToReg(int encoding, Dyninst::Architecture arch) -{ - switch (arch) - { - case Arch_x86: - switch (encoding) { - case 0: return Dyninst::x86::eax; - case 1: return Dyninst::x86::ecx; - case 2: return Dyninst::x86::edx; - case 3: return Dyninst::x86::ebx; - case 4: return Dyninst::x86::esp; - case 5: return Dyninst::x86::ebp; - case 6: return Dyninst::x86::esi; - case 7: return Dyninst::x86::edi; - case 8: return Dyninst::x86::eip; - case 9: return Dyninst::x86::flags; - case 10: return Dyninst::InvalidReg; - case 11: return Dyninst::x86::st0; - case 12: return Dyninst::x86::st1; - case 13: return Dyninst::x86::st2; - case 14: return Dyninst::x86::st3; - case 15: return Dyninst::x86::st4; - case 16: return Dyninst::x86::st5; - case 17: return Dyninst::x86::st6; - case 18: return Dyninst::x86::st7; - case 19: return Dyninst::InvalidReg; - case 20: return Dyninst::InvalidReg; - case 21: return Dyninst::x86::xmm0; - case 22: return Dyninst::x86::xmm1; - case 23: return Dyninst::x86::xmm2; - case 24: return Dyninst::x86::xmm3; - case 25: return Dyninst::x86::xmm4; - case 26: return Dyninst::x86::xmm5; - case 27: return Dyninst::x86::xmm6; - case 28: return Dyninst::x86::xmm7; - case 29: return Dyninst::x86::mm0; - case 30: return Dyninst::x86::mm1; - case 31: return Dyninst::x86::mm2; - case 32: return Dyninst::x86::mm3; - case 33: return Dyninst::x86::mm4; - case 34: return Dyninst::x86::mm5; - case 35: return Dyninst::x86::mm6; - case 36: return Dyninst::x86::mm7; - case 37: return Dyninst::InvalidReg; //fcw - case 38: return Dyninst::InvalidReg; //fsw - case 39: return Dyninst::InvalidReg; //mxcsr - case 40: return Dyninst::x86::es; - case 41: return Dyninst::x86::cs; - case 42: return Dyninst::x86::ss; - case 43: return Dyninst::x86::ds; - case 44: return Dyninst::x86::fs; - case 45: return Dyninst::x86::gs; - case 46: return Dyninst::InvalidReg; - case 47: return Dyninst::InvalidReg; - case 48: return Dyninst::InvalidReg; //tr - case 49: return Dyninst::InvalidReg; //ldtr - default: return Dyninst::InvalidReg; - } - break; - case Arch_x86_64: - switch (encoding) { - case 0: return Dyninst::x86_64::rax; - case 1: return Dyninst::x86_64::rdx; - case 2: return Dyninst::x86_64::rcx; - case 3: return Dyninst::x86_64::rbx; - case 4: return Dyninst::x86_64::rsi; - case 5: return Dyninst::x86_64::rdi; - case 6: return Dyninst::x86_64::rbp; - case 7: return Dyninst::x86_64::rsp; - case 8: return Dyninst::x86_64::r8; - case 9: return Dyninst::x86_64::r9; - case 10: return Dyninst::x86_64::r10; - case 11: return Dyninst::x86_64::r11; - case 12: return Dyninst::x86_64::r12; - case 13: return Dyninst::x86_64::r13; - case 14: return Dyninst::x86_64::r14; - case 15: return Dyninst::x86_64::r15; - case 16: return Dyninst::x86_64::rip; - case 17: return Dyninst::x86_64::k0; - case 18: return Dyninst::x86_64::k1; - case 19: return Dyninst::x86_64::k2; - case 20: return Dyninst::x86_64::k3; - case 21: return Dyninst::x86_64::k4; - case 22: return Dyninst::x86_64::k5; - case 23: return Dyninst::x86_64::k6; - case 24: return Dyninst::x86_64::k7; - case 25: return Dyninst::x86_64::zmm0; - case 26: return Dyninst::x86_64::zmm1; - case 27: return Dyninst::x86_64::zmm2; - case 28: return Dyninst::x86_64::zmm3; - case 29: return Dyninst::x86_64::zmm4; - case 30: return Dyninst::x86_64::zmm5; - case 31: return Dyninst::x86_64::zmm6; - case 32: return Dyninst::x86_64::zmm7; - case 33: return Dyninst::x86_64::zmm8; - case 34: return Dyninst::x86_64::zmm9; - case 35: return Dyninst::x86_64::zmm10; - case 36: return Dyninst::x86_64::zmm11; - case 37: return Dyninst::x86_64::zmm12; - case 38: return Dyninst::x86_64::zmm13; - case 39: return Dyninst::x86_64::zmm14; - case 40: return Dyninst::x86_64::zmm15; - case 41: return Dyninst::x86_64::zmm16; - case 42: return Dyninst::x86_64::zmm17; - case 43: return Dyninst::x86_64::zmm18; - case 44: return Dyninst::x86_64::zmm19; - case 45: return Dyninst::x86_64::zmm20; - case 46: return Dyninst::x86_64::zmm21; - case 47: return Dyninst::x86_64::zmm22; - case 48: return Dyninst::x86_64::zmm23; - case 49: return Dyninst::x86_64::zmm24; - case 50: return Dyninst::x86_64::zmm25; - case 51: return Dyninst::x86_64::zmm26; - case 52: return Dyninst::x86_64::zmm27; - case 53: return Dyninst::x86_64::zmm28; - case 54: return Dyninst::x86_64::zmm29; - case 55: return Dyninst::x86_64::zmm30; - case 56: return Dyninst::x86_64::zmm31; - case 57: return Dyninst::x86_64::ymm0; - case 58: return Dyninst::x86_64::ymm1; - case 59: return Dyninst::x86_64::ymm2; - case 60: return Dyninst::x86_64::ymm3; - case 61: return Dyninst::x86_64::ymm4; - case 62: return Dyninst::x86_64::ymm5; - case 63: return Dyninst::x86_64::ymm6; - case 64: return Dyninst::x86_64::ymm7; - case 65: return Dyninst::x86_64::ymm8; - case 66: return Dyninst::x86_64::ymm9; - case 67: return Dyninst::x86_64::ymm10; - case 68: return Dyninst::x86_64::ymm11; - case 69: return Dyninst::x86_64::ymm12; - case 70: return Dyninst::x86_64::ymm13; - case 71: return Dyninst::x86_64::ymm14; - case 72: return Dyninst::x86_64::ymm15; - case 73: return Dyninst::x86_64::ymm16; - case 74: return Dyninst::x86_64::ymm17; - case 75: return Dyninst::x86_64::ymm18; - case 76: return Dyninst::x86_64::ymm19; - case 77: return Dyninst::x86_64::ymm20; - case 78: return Dyninst::x86_64::ymm21; - case 79: return Dyninst::x86_64::ymm22; - case 80: return Dyninst::x86_64::ymm23; - case 81: return Dyninst::x86_64::ymm24; - case 82: return Dyninst::x86_64::ymm25; - case 83: return Dyninst::x86_64::ymm26; - case 84: return Dyninst::x86_64::ymm27; - case 85: return Dyninst::x86_64::ymm28; - case 86: return Dyninst::x86_64::ymm29; - case 87: return Dyninst::x86_64::ymm30; - case 88: return Dyninst::x86_64::ymm31; - case 89: return Dyninst::x86_64::xmm0; - case 90: return Dyninst::x86_64::xmm1; - case 91: return Dyninst::x86_64::xmm2; - case 92: return Dyninst::x86_64::xmm3; - case 93: return Dyninst::x86_64::xmm4; - case 94: return Dyninst::x86_64::xmm5; - case 95: return Dyninst::x86_64::xmm6; - case 96: return Dyninst::x86_64::xmm7; - case 97: return Dyninst::x86_64::xmm8; - case 98: return Dyninst::x86_64::xmm9; - case 99: return Dyninst::x86_64::xmm10; - case 100: return Dyninst::x86_64::xmm11; - case 101: return Dyninst::x86_64::xmm12; - case 102: return Dyninst::x86_64::xmm13; - case 103: return Dyninst::x86_64::xmm14; - case 104: return Dyninst::x86_64::xmm15; - case 105: return Dyninst::x86_64::xmm16; - case 106: return Dyninst::x86_64::xmm17; - case 107: return Dyninst::x86_64::xmm18; - case 108: return Dyninst::x86_64::xmm19; - case 109: return Dyninst::x86_64::xmm20; - case 110: return Dyninst::x86_64::xmm21; - case 111: return Dyninst::x86_64::xmm22; - case 112: return Dyninst::x86_64::xmm23; - case 113: return Dyninst::x86_64::xmm24; - case 114: return Dyninst::x86_64::xmm25; - case 115: return Dyninst::x86_64::xmm26; - case 116: return Dyninst::x86_64::xmm27; - case 117: return Dyninst::x86_64::xmm28; - case 118: return Dyninst::x86_64::xmm29; - case 119: return Dyninst::x86_64::xmm30; - case 120: return Dyninst::x86_64::xmm31; - case 121: return Dyninst::x86_64::st0; - case 122: return Dyninst::x86_64::st1; - case 123: return Dyninst::x86_64::st2; - case 124: return Dyninst::x86_64::st3; - case 125: return Dyninst::x86_64::st4; - case 126: return Dyninst::x86_64::st5; - case 127: return Dyninst::x86_64::st6; - case 128: return Dyninst::x86_64::st7; - case 129: return Dyninst::x86_64::mm0; - case 130: return Dyninst::x86_64::mm1; - case 131: return Dyninst::x86_64::mm2; - case 132: return Dyninst::x86_64::mm3; - case 133: return Dyninst::x86_64::mm4; - case 134: return Dyninst::x86_64::mm5; - case 135: return Dyninst::x86_64::mm6; - case 136: return Dyninst::x86_64::mm7; - case 137: return Dyninst::x86_64::flags; - case 138: return Dyninst::x86_64::es; - case 139: return Dyninst::x86_64::cs; - case 140: return Dyninst::x86_64::ss; - case 141: return Dyninst::x86_64::ds; - case 142: return Dyninst::x86_64::fs; - case 143: return Dyninst::x86_64::gs; - case 144: return Dyninst::InvalidReg; - case 145: return Dyninst::InvalidReg; - case 146: return Dyninst::x86_64::fsbase; - case 147: return Dyninst::x86_64::gsbase; - case 148: return Dyninst::InvalidReg; - case 149: return Dyninst::InvalidReg; - case 150: return Dyninst::InvalidReg; //tr - case 151: return Dyninst::InvalidReg; //ldtr - case 152: return Dyninst::InvalidReg; //mxcsr - case 153: return Dyninst::InvalidReg; //fcw - case 154: return Dyninst::InvalidReg; //fsw - } - break; - case Arch_ppc32: - switch (encoding) { - case 0: return Dyninst::ppc32::r0; - case 1: return Dyninst::ppc32::r1; - case 2: return Dyninst::ppc32::r2; - case 3: return Dyninst::ppc32::r3; - case 4: return Dyninst::ppc32::r4; - case 5: return Dyninst::ppc32::r5; - case 6: return Dyninst::ppc32::r6; - case 7: return Dyninst::ppc32::r7; - case 8: return Dyninst::ppc32::r8; - case 9: return Dyninst::ppc32::r9; - case 10: return Dyninst::ppc32::r10; - case 11: return Dyninst::ppc32::r11; - case 12: return Dyninst::ppc32::r12; - case 13: return Dyninst::ppc32::r13; - case 14: return Dyninst::ppc32::r14; - case 15: return Dyninst::ppc32::r15; - case 16: return Dyninst::ppc32::r16; - case 17: return Dyninst::ppc32::r17; - case 18: return Dyninst::ppc32::r18; - case 19: return Dyninst::ppc32::r19; - case 20: return Dyninst::ppc32::r20; - case 21: return Dyninst::ppc32::r21; - case 22: return Dyninst::ppc32::r22; - case 23: return Dyninst::ppc32::r23; - case 24: return Dyninst::ppc32::r24; - case 25: return Dyninst::ppc32::r25; - case 26: return Dyninst::ppc32::r26; - case 27: return Dyninst::ppc32::r27; - case 28: return Dyninst::ppc32::r28; - case 29: return Dyninst::ppc32::r29; - case 30: return Dyninst::ppc32::r30; - case 31: return Dyninst::ppc32::r31; - case 32: return Dyninst::ppc32::fpr0; - case 33: return Dyninst::ppc32::fpr1; - case 34: return Dyninst::ppc32::fpr2; - case 35: return Dyninst::ppc32::fpr3; - case 36: return Dyninst::ppc32::fpr4; - case 37: return Dyninst::ppc32::fpr5; - case 38: return Dyninst::ppc32::fpr6; - case 39: return Dyninst::ppc32::fpr7; - case 40: return Dyninst::ppc32::fpr8; - case 41: return Dyninst::ppc32::fpr9; - case 42: return Dyninst::ppc32::fpr10; - case 43: return Dyninst::ppc32::fpr11; - case 44: return Dyninst::ppc32::fpr12; - case 45: return Dyninst::ppc32::fpr13; - case 46: return Dyninst::ppc32::fpr14; - case 47: return Dyninst::ppc32::fpr15; - case 48: return Dyninst::ppc32::fpr16; - case 49: return Dyninst::ppc32::fpr17; - case 50: return Dyninst::ppc32::fpr18; - case 51: return Dyninst::ppc32::fpr19; - case 52: return Dyninst::ppc32::fpr20; - case 53: return Dyninst::ppc32::fpr21; - case 54: return Dyninst::ppc32::fpr22; - case 55: return Dyninst::ppc32::fpr23; - case 56: return Dyninst::ppc32::fpr24; - case 57: return Dyninst::ppc32::fpr25; - case 58: return Dyninst::ppc32::fpr26; - case 59: return Dyninst::ppc32::fpr27; - case 60: return Dyninst::ppc32::fpr28; - case 61: return Dyninst::ppc32::fpr29; - case 62: return Dyninst::ppc32::fpr30; - case 63: return Dyninst::ppc32::fpr31; - case 64: return Dyninst::ppc32::cr; - case 65: return Dyninst::InvalidReg; //FPSCR - } - //Seperate switch statements to give compilers an easier time of - // optimizing - switch (encoding) { - case 100: return Dyninst::ppc32::mq; - case 101: return Dyninst::ppc32::xer; - case 102: return Dyninst::InvalidReg; - case 103: return Dyninst::InvalidReg; - case 104: return Dyninst::InvalidReg; //RTCU - case 105: return Dyninst::InvalidReg; //RTCL - case 106: return Dyninst::InvalidReg; - case 107: return Dyninst::InvalidReg; - case 108: return Dyninst::ppc32::lr; - case 109: return Dyninst::ppc32::ctr; - default: return Dyninst::InvalidReg; - } - break; - case Arch_ppc64: - switch (encoding) { - case 0: return Dyninst::ppc64::r0; - case 1: return Dyninst::ppc64::r1; - case 2: return Dyninst::ppc64::r2; - case 3: return Dyninst::ppc64::r3; - case 4: return Dyninst::ppc64::r4; - case 5: return Dyninst::ppc64::r5; - case 6: return Dyninst::ppc64::r6; - case 7: return Dyninst::ppc64::r7; - case 8: return Dyninst::ppc64::r8; - case 9: return Dyninst::ppc64::r9; - case 10: return Dyninst::ppc64::r10; - case 11: return Dyninst::ppc64::r11; - case 12: return Dyninst::ppc64::r12; - case 13: return Dyninst::ppc64::r13; - case 14: return Dyninst::ppc64::r14; - case 15: return Dyninst::ppc64::r15; - case 16: return Dyninst::ppc64::r16; - case 17: return Dyninst::ppc64::r17; - case 18: return Dyninst::ppc64::r18; - case 19: return Dyninst::ppc64::r19; - case 20: return Dyninst::ppc64::r20; - case 21: return Dyninst::ppc64::r21; - case 22: return Dyninst::ppc64::r22; - case 23: return Dyninst::ppc64::r23; - case 24: return Dyninst::ppc64::r24; - case 25: return Dyninst::ppc64::r25; - case 26: return Dyninst::ppc64::r26; - case 27: return Dyninst::ppc64::r27; - case 28: return Dyninst::ppc64::r28; - case 29: return Dyninst::ppc64::r29; - case 30: return Dyninst::ppc64::r30; - case 31: return Dyninst::ppc64::r31; - case 32: return Dyninst::ppc64::fpr0; - case 33: return Dyninst::ppc64::fpr1; - case 34: return Dyninst::ppc64::fpr2; - case 35: return Dyninst::ppc64::fpr3; - case 36: return Dyninst::ppc64::fpr4; - case 37: return Dyninst::ppc64::fpr5; - case 38: return Dyninst::ppc64::fpr6; - case 39: return Dyninst::ppc64::fpr7; - case 40: return Dyninst::ppc64::fpr8; - case 41: return Dyninst::ppc64::fpr9; - case 42: return Dyninst::ppc64::fpr10; - case 43: return Dyninst::ppc64::fpr11; - case 44: return Dyninst::ppc64::fpr12; - case 45: return Dyninst::ppc64::fpr13; - case 46: return Dyninst::ppc64::fpr14; - case 47: return Dyninst::ppc64::fpr15; - case 48: return Dyninst::ppc64::fpr16; - case 49: return Dyninst::ppc64::fpr17; - case 50: return Dyninst::ppc64::fpr18; - case 51: return Dyninst::ppc64::fpr19; - case 52: return Dyninst::ppc64::fpr20; - case 53: return Dyninst::ppc64::fpr21; - case 54: return Dyninst::ppc64::fpr22; - case 55: return Dyninst::ppc64::fpr23; - case 56: return Dyninst::ppc64::fpr24; - case 57: return Dyninst::ppc64::fpr25; - case 58: return Dyninst::ppc64::fpr26; - case 59: return Dyninst::ppc64::fpr27; - case 60: return Dyninst::ppc64::fpr28; - case 61: return Dyninst::ppc64::fpr29; - case 62: return Dyninst::ppc64::fpr30; - case 63: return Dyninst::ppc64::fpr31; - case 64: return Dyninst::ppc64::cr; - case 65: return Dyninst::InvalidReg; //FPSCR - } - //Seperate switch statements to give compilers an easier time of - // optimizing - switch (encoding) { - case 100: return Dyninst::ppc64::mq; - case 101: return Dyninst::ppc64::xer; - case 102: return Dyninst::InvalidReg; - case 103: return Dyninst::InvalidReg; - case 104: return Dyninst::InvalidReg; //RTCU - case 105: return Dyninst::InvalidReg; //RTCL - case 106: return Dyninst::InvalidReg; - case 107: return Dyninst::InvalidReg; - case 108: return Dyninst::ppc64::lr; - case 109: return Dyninst::ppc64::ctr; - default: return Dyninst::InvalidReg; - } - break; - case Arch_aarch64: - { - // this info can be found in - // DWARF for the ARM ® 64-bit Architecture (AArch64) - switch(encoding){ - case 0: return Dyninst::aarch64::x0; - case 1: return Dyninst::aarch64::x1; - case 2: return Dyninst::aarch64::x2; - case 3: return Dyninst::aarch64::x3; - case 4: return Dyninst::aarch64::x4; - case 5: return Dyninst::aarch64::x5; - case 6: return Dyninst::aarch64::x6; - case 7: return Dyninst::aarch64::x7; - case 8: return Dyninst::aarch64::x8; - case 9: return Dyninst::aarch64::x9; - case 10: return Dyninst::aarch64::x10; - case 11: return Dyninst::aarch64::x11; - case 12: return Dyninst::aarch64::x12; - case 13: return Dyninst::aarch64::x13; - case 14: return Dyninst::aarch64::x14; - case 15: return Dyninst::aarch64::x15; - case 16: return Dyninst::aarch64::x16; - case 17: return Dyninst::aarch64::x17; - case 18: return Dyninst::aarch64::x18; - case 19: return Dyninst::aarch64::x19; - case 20: return Dyninst::aarch64::x20; - case 21: return Dyninst::aarch64::x21; - case 22: return Dyninst::aarch64::x22; - case 23: return Dyninst::aarch64::x23; - case 24: return Dyninst::aarch64::x24; - case 25: return Dyninst::aarch64::x25; - case 26: return Dyninst::aarch64::x26; - case 27: return Dyninst::aarch64::x27; - case 28: return Dyninst::aarch64::x28; - case 29: return Dyninst::aarch64::x29; - case 30: return Dyninst::aarch64::x30; - case 31: return Dyninst::aarch64::sp; - case 32: return Dyninst::InvalidReg; - } - switch(encoding){ - case 64: return Dyninst::aarch64::q0; - case 65: return Dyninst::aarch64::q1; - case 66: return Dyninst::aarch64::q2; - case 67: return Dyninst::aarch64::q3; - case 68: return Dyninst::aarch64::q4; - case 69: return Dyninst::aarch64::q5; - case 70: return Dyninst::aarch64::q6; - case 71: return Dyninst::aarch64::q7; - case 72: return Dyninst::aarch64::q8; - case 73: return Dyninst::aarch64::q9; - case 74: return Dyninst::aarch64::q10; - case 75: return Dyninst::aarch64::q11; - case 76: return Dyninst::aarch64::q12; - case 77: return Dyninst::aarch64::q13; - case 78: return Dyninst::aarch64::q14; - case 79: return Dyninst::aarch64::q15; - case 80: return Dyninst::aarch64::q16; - case 81: return Dyninst::aarch64::q17; - case 82: return Dyninst::aarch64::q18; - case 83: return Dyninst::aarch64::q19; - case 84: return Dyninst::aarch64::q20; - case 85: return Dyninst::aarch64::q21; - case 86: return Dyninst::aarch64::q22; - case 87: return Dyninst::aarch64::q23; - case 88: return Dyninst::aarch64::q24; - case 89: return Dyninst::aarch64::q25; - case 90: return Dyninst::aarch64::q26; - case 91: return Dyninst::aarch64::q27; - case 92: return Dyninst::aarch64::q28; - case 93: return Dyninst::aarch64::q29; - case 94: return Dyninst::aarch64::q30; - case 95: return Dyninst::aarch64::q31; - - default: return Dyninst::InvalidReg; - break; - } - return Dyninst::InvalidReg; - } - case Arch_cuda: - // ignore CUDA register encodings for now - return Dyninst::InvalidReg; - break; - case Arch_amdgpu_vega: - // ignore CUDA register encodings for now - return Dyninst::InvalidReg; - break; - - case Arch_none: - return Dyninst::InvalidReg; - break; - default: - assert(0); - return InvalidReg; - } - //Invalid Architecture passed - return Dyninst::InvalidReg; - -} - -int MachRegister::getDwarfEnc() const -{ - switch (getArchitecture()) - { - case Arch_x86: - switch (val()) { - case Dyninst::x86::ieax: return 0; - case Dyninst::x86::iecx: return 1; - case Dyninst::x86::iedx: return 2; - case Dyninst::x86::iebx: return 3; - case Dyninst::x86::iesp: return 4; - case Dyninst::x86::iebp: return 5; - case Dyninst::x86::iesi: return 6; - case Dyninst::x86::iedi: return 7; - case Dyninst::x86::ieip: return 8; - case Dyninst::x86::iflags: return 9; - case Dyninst::x86::ixmm0: return 21; - case Dyninst::x86::ixmm1: return 22; - case Dyninst::x86::ixmm2: return 23; - case Dyninst::x86::ixmm3: return 24; - case Dyninst::x86::ixmm4: return 25; - case Dyninst::x86::ixmm5: return 26; - case Dyninst::x86::ixmm6: return 27; - case Dyninst::x86::ixmm7: return 28; - case Dyninst::x86::imm0: return 29; - case Dyninst::x86::imm1: return 30; - case Dyninst::x86::imm2: return 31; - case Dyninst::x86::imm3: return 32; - case Dyninst::x86::imm4: return 33; - case Dyninst::x86::imm5: return 34; - case Dyninst::x86::imm6: return 35; - case Dyninst::x86::imm7: return 36; - case Dyninst::x86::ies: return 40; - case Dyninst::x86::ics: return 41; - case Dyninst::x86::iss: return 42; - case Dyninst::x86::ids: return 43; - case Dyninst::x86::ifs: return 44; - case Dyninst::x86::igs: return 45; - default: return -1; - } - break; - case Arch_x86_64: - switch (val()) { - case Dyninst::x86_64::irax: return 0; - case Dyninst::x86_64::irdx: return 1; - case Dyninst::x86_64::ircx: return 2; - case Dyninst::x86_64::irbx: return 3; - case Dyninst::x86_64::irsi: return 4; - case Dyninst::x86_64::irdi: return 5; - case Dyninst::x86_64::irbp: return 6; - case Dyninst::x86_64::irsp: return 7; - case Dyninst::x86_64::ir8: return 8; - case Dyninst::x86_64::ir9: return 9; - case Dyninst::x86_64::ir10: return 10; - case Dyninst::x86_64::ir11: return 11; - case Dyninst::x86_64::ir12: return 12; - case Dyninst::x86_64::ir13: return 13; - case Dyninst::x86_64::ir14: return 14; - case Dyninst::x86_64::ir15: return 15; - case Dyninst::x86_64::irip: return 16; - case Dyninst::x86_64::ik0: return 17; - case Dyninst::x86_64::ik1: return 18; - case Dyninst::x86_64::ik2: return 19; - case Dyninst::x86_64::ik3: return 20; - case Dyninst::x86_64::ik4: return 21; - case Dyninst::x86_64::ik5: return 22; - case Dyninst::x86_64::ik6: return 23; - case Dyninst::x86_64::ik7: return 24; - case Dyninst::x86_64::izmm0: return 25; - case Dyninst::x86_64::izmm1: return 26; - case Dyninst::x86_64::izmm2: return 27; - case Dyninst::x86_64::izmm3: return 28; - case Dyninst::x86_64::izmm4: return 29; - case Dyninst::x86_64::izmm5: return 30; - case Dyninst::x86_64::izmm6: return 31; - case Dyninst::x86_64::izmm7: return 32; - case Dyninst::x86_64::izmm8: return 33; - case Dyninst::x86_64::izmm9: return 34; - case Dyninst::x86_64::izmm10: return 35; - case Dyninst::x86_64::izmm11: return 36; - case Dyninst::x86_64::izmm12: return 37; - case Dyninst::x86_64::izmm13: return 38; - case Dyninst::x86_64::izmm14: return 39; - case Dyninst::x86_64::izmm15: return 40; - case Dyninst::x86_64::izmm16: return 41; - case Dyninst::x86_64::izmm17: return 42; - case Dyninst::x86_64::izmm18: return 43; - case Dyninst::x86_64::izmm19: return 44; - case Dyninst::x86_64::izmm20: return 45; - case Dyninst::x86_64::izmm21: return 46; - case Dyninst::x86_64::izmm22: return 47; - case Dyninst::x86_64::izmm23: return 48; - case Dyninst::x86_64::izmm24: return 49; - case Dyninst::x86_64::izmm25: return 50; - case Dyninst::x86_64::izmm26: return 51; - case Dyninst::x86_64::izmm27: return 52; - case Dyninst::x86_64::izmm28: return 53; - case Dyninst::x86_64::izmm29: return 54; - case Dyninst::x86_64::izmm30: return 55; - case Dyninst::x86_64::izmm31: return 56; - case Dyninst::x86_64::iymm0: return 57; - case Dyninst::x86_64::iymm1: return 58; - case Dyninst::x86_64::iymm2: return 59; - case Dyninst::x86_64::iymm3: return 60; - case Dyninst::x86_64::iymm4: return 61; - case Dyninst::x86_64::iymm5: return 62; - case Dyninst::x86_64::iymm6: return 63; - case Dyninst::x86_64::iymm7: return 64; - case Dyninst::x86_64::iymm8: return 65; - case Dyninst::x86_64::iymm9: return 66; - case Dyninst::x86_64::iymm10: return 67; - case Dyninst::x86_64::iymm11: return 68; - case Dyninst::x86_64::iymm12: return 69; - case Dyninst::x86_64::iymm13: return 70; - case Dyninst::x86_64::iymm14: return 71; - case Dyninst::x86_64::iymm15: return 72; - case Dyninst::x86_64::iymm16: return 73; - case Dyninst::x86_64::iymm17: return 74; - case Dyninst::x86_64::iymm18: return 75; - case Dyninst::x86_64::iymm19: return 76; - case Dyninst::x86_64::iymm20: return 77; - case Dyninst::x86_64::iymm21: return 78; - case Dyninst::x86_64::iymm22: return 79; - case Dyninst::x86_64::iymm23: return 80; - case Dyninst::x86_64::iymm24: return 81; - case Dyninst::x86_64::iymm25: return 82; - case Dyninst::x86_64::iymm26: return 83; - case Dyninst::x86_64::iymm27: return 84; - case Dyninst::x86_64::iymm28: return 85; - case Dyninst::x86_64::iymm29: return 86; - case Dyninst::x86_64::iymm30: return 87; - case Dyninst::x86_64::iymm31: return 88; - case Dyninst::x86_64::ixmm0: return 89; - case Dyninst::x86_64::ixmm1: return 90; - case Dyninst::x86_64::ixmm2: return 91; - case Dyninst::x86_64::ixmm3: return 92; - case Dyninst::x86_64::ixmm4: return 93; - case Dyninst::x86_64::ixmm5: return 94; - case Dyninst::x86_64::ixmm6: return 95; - case Dyninst::x86_64::ixmm7: return 96; - case Dyninst::x86_64::ixmm8: return 97; - case Dyninst::x86_64::ixmm9: return 98; - case Dyninst::x86_64::ixmm10: return 99; - case Dyninst::x86_64::ixmm11: return 100; - case Dyninst::x86_64::ixmm12: return 101; - case Dyninst::x86_64::ixmm13: return 102; - case Dyninst::x86_64::ixmm14: return 103; - case Dyninst::x86_64::ixmm15: return 104; - case Dyninst::x86_64::ixmm16: return 105; - case Dyninst::x86_64::ixmm17: return 106; - case Dyninst::x86_64::ixmm18: return 107; - case Dyninst::x86_64::ixmm19: return 108; - case Dyninst::x86_64::ixmm20: return 109; - case Dyninst::x86_64::ixmm21: return 110; - case Dyninst::x86_64::ixmm22: return 111; - case Dyninst::x86_64::ixmm23: return 112; - case Dyninst::x86_64::ixmm24: return 113; - case Dyninst::x86_64::ixmm25: return 114; - case Dyninst::x86_64::ixmm26: return 115; - case Dyninst::x86_64::ixmm27: return 116; - case Dyninst::x86_64::ixmm28: return 117; - case Dyninst::x86_64::ixmm29: return 118; - case Dyninst::x86_64::ixmm30: return 119; - case Dyninst::x86_64::ixmm31: return 120; - //case Dyninst::x86_64::ist0: return 121; - //case Dyninst::x86_64::ist1: return 122; - //case Dyninst::x86_64::ist2: return 123; - //case Dyninst::x86_64::ist3: return 124; - //case Dyninst::x86_64::ist4: return 125; - //case Dyninst::x86_64::ist5: return 126; - //case Dyninst::x86_64::ist6: return 127; - //case Dyninst::x86_64::ist7: return 128; - case Dyninst::x86_64::imm0: return 129; - case Dyninst::x86_64::imm1: return 130; - case Dyninst::x86_64::imm2: return 131; - case Dyninst::x86_64::imm3: return 132; - case Dyninst::x86_64::imm4: return 133; - case Dyninst::x86_64::imm5: return 134; - case Dyninst::x86_64::imm6: return 135; - case Dyninst::x86_64::imm7: return 136; - case Dyninst::x86_64::iflags: return 137; - case Dyninst::x86_64::ies: return 138; - case Dyninst::x86_64::ics: return 139; - case Dyninst::x86_64::iss: return 140; - case Dyninst::x86_64::ids: return 141; - case Dyninst::x86_64::ifs: return 142; - case Dyninst::x86_64::igs: return 143; - // INVALID REG 144 - // INVALID REG 145 - case Dyninst::x86_64::ifsbase: return 146; - case Dyninst::x86_64::igsbase: return 147; - default: return -1; - } - break; - case Arch_ppc32: - switch (val()) { - case Dyninst::ppc32::ir0: return 0; - case Dyninst::ppc32::ir1: return 1; - case Dyninst::ppc32::ir2: return 2; - case Dyninst::ppc32::ir3: return 3; - case Dyninst::ppc32::ir4: return 4; - case Dyninst::ppc32::ir5: return 5; - case Dyninst::ppc32::ir6: return 6; - case Dyninst::ppc32::ir7: return 7; - case Dyninst::ppc32::ir8: return 8; - case Dyninst::ppc32::ir9: return 9; - case Dyninst::ppc32::ir10: return 10; - case Dyninst::ppc32::ir11: return 11; - case Dyninst::ppc32::ir12: return 12; - case Dyninst::ppc32::ir13: return 13; - case Dyninst::ppc32::ir14: return 14; - case Dyninst::ppc32::ir15: return 15; - case Dyninst::ppc32::ir16: return 16; - case Dyninst::ppc32::ir17: return 17; - case Dyninst::ppc32::ir18: return 18; - case Dyninst::ppc32::ir19: return 19; - case Dyninst::ppc32::ir20: return 20; - case Dyninst::ppc32::ir21: return 21; - case Dyninst::ppc32::ir22: return 22; - case Dyninst::ppc32::ir23: return 23; - case Dyninst::ppc32::ir24: return 24; - case Dyninst::ppc32::ir25: return 25; - case Dyninst::ppc32::ir26: return 26; - case Dyninst::ppc32::ir27: return 27; - case Dyninst::ppc32::ir28: return 28; - case Dyninst::ppc32::ir29: return 29; - case Dyninst::ppc32::ir30: return 30; - case Dyninst::ppc32::ir31: return 31; - case Dyninst::ppc32::ifpr0: return 32; - case Dyninst::ppc32::ifpr1: return 33; - case Dyninst::ppc32::ifpr2: return 34; - case Dyninst::ppc32::ifpr3: return 35; - case Dyninst::ppc32::ifpr4: return 36; - case Dyninst::ppc32::ifpr5: return 37; - case Dyninst::ppc32::ifpr6: return 38; - case Dyninst::ppc32::ifpr7: return 39; - case Dyninst::ppc32::ifpr8: return 40; - case Dyninst::ppc32::ifpr9: return 41; - case Dyninst::ppc32::ifpr10: return 42; - case Dyninst::ppc32::ifpr11: return 43; - case Dyninst::ppc32::ifpr12: return 44; - case Dyninst::ppc32::ifpr13: return 45; - case Dyninst::ppc32::ifpr14: return 46; - case Dyninst::ppc32::ifpr15: return 47; - case Dyninst::ppc32::ifpr16: return 48; - case Dyninst::ppc32::ifpr17: return 49; - case Dyninst::ppc32::ifpr18: return 50; - case Dyninst::ppc32::ifpr19: return 51; - case Dyninst::ppc32::ifpr20: return 52; - case Dyninst::ppc32::ifpr21: return 53; - case Dyninst::ppc32::ifpr22: return 54; - case Dyninst::ppc32::ifpr23: return 55; - case Dyninst::ppc32::ifpr24: return 56; - case Dyninst::ppc32::ifpr25: return 57; - case Dyninst::ppc32::ifpr26: return 58; - case Dyninst::ppc32::ifpr27: return 59; - case Dyninst::ppc32::ifpr28: return 60; - case Dyninst::ppc32::ifpr29: return 61; - case Dyninst::ppc32::ifpr30: return 62; - case Dyninst::ppc32::ifpr31: return 63; - case Dyninst::ppc32::icr: return 64; - case Dyninst::ppc32::imq: return 100; - case Dyninst::ppc32::ixer: return 101; - case Dyninst::ppc32::ilr: return 108; - case Dyninst::ppc32::ictr: return 109; - default: return -1; - } - case Arch_ppc64: - switch (val()) { - case Dyninst::ppc64::ir0: return 0; - case Dyninst::ppc64::ir1: return 1; - case Dyninst::ppc64::ir2: return 2; - case Dyninst::ppc64::ir3: return 3; - case Dyninst::ppc64::ir4: return 4; - case Dyninst::ppc64::ir5: return 5; - case Dyninst::ppc64::ir6: return 6; - case Dyninst::ppc64::ir7: return 7; - case Dyninst::ppc64::ir8: return 8; - case Dyninst::ppc64::ir9: return 9; - case Dyninst::ppc64::ir10: return 10; - case Dyninst::ppc64::ir11: return 11; - case Dyninst::ppc64::ir12: return 12; - case Dyninst::ppc64::ir13: return 13; - case Dyninst::ppc64::ir14: return 14; - case Dyninst::ppc64::ir15: return 15; - case Dyninst::ppc64::ir16: return 16; - case Dyninst::ppc64::ir17: return 17; - case Dyninst::ppc64::ir18: return 18; - case Dyninst::ppc64::ir19: return 19; - case Dyninst::ppc64::ir20: return 20; - case Dyninst::ppc64::ir21: return 21; - case Dyninst::ppc64::ir22: return 22; - case Dyninst::ppc64::ir23: return 23; - case Dyninst::ppc64::ir24: return 24; - case Dyninst::ppc64::ir25: return 25; - case Dyninst::ppc64::ir26: return 26; - case Dyninst::ppc64::ir27: return 27; - case Dyninst::ppc64::ir28: return 28; - case Dyninst::ppc64::ir29: return 29; - case Dyninst::ppc64::ir30: return 30; - case Dyninst::ppc64::ir31: return 31; - case Dyninst::ppc64::ifpr0: return 32; - case Dyninst::ppc64::ifpr1: return 33; - case Dyninst::ppc64::ifpr2: return 34; - case Dyninst::ppc64::ifpr3: return 35; - case Dyninst::ppc64::ifpr4: return 36; - case Dyninst::ppc64::ifpr5: return 37; - case Dyninst::ppc64::ifpr6: return 38; - case Dyninst::ppc64::ifpr7: return 39; - case Dyninst::ppc64::ifpr8: return 40; - case Dyninst::ppc64::ifpr9: return 41; - case Dyninst::ppc64::ifpr10: return 42; - case Dyninst::ppc64::ifpr11: return 43; - case Dyninst::ppc64::ifpr12: return 44; - case Dyninst::ppc64::ifpr13: return 45; - case Dyninst::ppc64::ifpr14: return 46; - case Dyninst::ppc64::ifpr15: return 47; - case Dyninst::ppc64::ifpr16: return 48; - case Dyninst::ppc64::ifpr17: return 49; - case Dyninst::ppc64::ifpr18: return 50; - case Dyninst::ppc64::ifpr19: return 51; - case Dyninst::ppc64::ifpr20: return 52; - case Dyninst::ppc64::ifpr21: return 53; - case Dyninst::ppc64::ifpr22: return 54; - case Dyninst::ppc64::ifpr23: return 55; - case Dyninst::ppc64::ifpr24: return 56; - case Dyninst::ppc64::ifpr25: return 57; - case Dyninst::ppc64::ifpr26: return 58; - case Dyninst::ppc64::ifpr27: return 59; - case Dyninst::ppc64::ifpr28: return 60; - case Dyninst::ppc64::ifpr29: return 61; - case Dyninst::ppc64::ifpr30: return 62; - case Dyninst::ppc64::ifpr31: return 63; - case Dyninst::ppc64::icr: return 64; - case Dyninst::ppc64::imq: return 100; - case Dyninst::ppc64::ixer: return 101; - case Dyninst::ppc64::ilr: return 108; - case Dyninst::ppc64::ictr: return 109; - default: return -1; - } - break; - case Arch_aarch64: - switch (val()) { - case Dyninst::aarch64::ix0: return 0; - case Dyninst::aarch64::ix1: return 1; - case Dyninst::aarch64::ix2: return 2; - case Dyninst::aarch64::ix3: return 3; - case Dyninst::aarch64::ix4: return 4; - case Dyninst::aarch64::ix5: return 5; - case Dyninst::aarch64::ix6: return 6; - case Dyninst::aarch64::ix7: return 7; - case Dyninst::aarch64::ix8: return 8; - case Dyninst::aarch64::ix9: return 9; - case Dyninst::aarch64::ix10: return 10; - case Dyninst::aarch64::ix11: return 11; - case Dyninst::aarch64::ix12: return 12; - case Dyninst::aarch64::ix13: return 13; - case Dyninst::aarch64::ix14: return 14; - case Dyninst::aarch64::ix15: return 15; - case Dyninst::aarch64::ix16: return 16; - case Dyninst::aarch64::ix17: return 17; - case Dyninst::aarch64::ix18: return 18; - case Dyninst::aarch64::ix19: return 19; - case Dyninst::aarch64::ix20: return 20; - case Dyninst::aarch64::ix21: return 21; - case Dyninst::aarch64::ix22: return 22; - case Dyninst::aarch64::ix23: return 23; - case Dyninst::aarch64::ix24: return 24; - case Dyninst::aarch64::ix25: return 25; - case Dyninst::aarch64::ix26: return 26; - case Dyninst::aarch64::ix27: return 27; - case Dyninst::aarch64::ix28: return 28; - case Dyninst::aarch64::ix29: return 29; - case Dyninst::aarch64::ix30: return 30; - case Dyninst::aarch64::isp: return 31; - - case Dyninst::aarch64::iq0: return 64; - case Dyninst::aarch64::iq1: return 65; - case Dyninst::aarch64::iq2: return 66; - case Dyninst::aarch64::iq3: return 67; - case Dyninst::aarch64::iq4: return 68; - case Dyninst::aarch64::iq5: return 69; - case Dyninst::aarch64::iq6: return 70; - case Dyninst::aarch64::iq7: return 71; - case Dyninst::aarch64::iq8: return 72; - case Dyninst::aarch64::iq9: return 73; - case Dyninst::aarch64::iq10: return 74; - case Dyninst::aarch64::iq11: return 75; - case Dyninst::aarch64::iq12: return 76; - case Dyninst::aarch64::iq13: return 77; - case Dyninst::aarch64::iq14: return 78; - case Dyninst::aarch64::iq15: return 79; - case Dyninst::aarch64::iq16: return 80; - case Dyninst::aarch64::iq17: return 81; - case Dyninst::aarch64::iq18: return 82; - case Dyninst::aarch64::iq19: return 83; - case Dyninst::aarch64::iq20: return 84; - case Dyninst::aarch64::iq21: return 85; - case Dyninst::aarch64::iq22: return 86; - case Dyninst::aarch64::iq23: return 87; - case Dyninst::aarch64::iq24: return 88; - case Dyninst::aarch64::iq25: return 89; - case Dyninst::aarch64::iq26: return 90; - case Dyninst::aarch64::iq27: return 91; - case Dyninst::aarch64::iq28: return 92; - case Dyninst::aarch64::iq29: return 93; - case Dyninst::aarch64::iq30: return 94; - case Dyninst::aarch64::iq31: return 95; - - default: return -1; - } - break; - case Arch_none: - assert(0); - return -1; - default: - assert(0); - return -1; - } - //Invalid register passed - return -1; -} - -unsigned Dyninst::getArchAddressWidth(Dyninst::Architecture arch) -{ - switch (arch) { - case Arch_none: - return 0; - case Arch_x86: - case Arch_ppc32: - return 4; - case Arch_x86_64: - case Arch_ppc64: - case Arch_aarch64: - case Arch_cuda: - case Arch_intelGen9: - case Arch_amdgpu_vega: - return 8; - default: - assert(0); - return InvalidReg; - } - return 0; -} - -MachRegister MachRegister::getArchReg(unsigned int regNum, Dyninst::Architecture arch){ - switch(arch){ - case Arch_aarch64: - switch(regNum){ - case 0: return Dyninst::aarch64::x0; - case 1: return Dyninst::aarch64::x1; - case 2: return Dyninst::aarch64::x2; - case 3: return Dyninst::aarch64::x3; - case 4: return Dyninst::aarch64::x4; - case 5: return Dyninst::aarch64::x5; - case 6: return Dyninst::aarch64::x6; - case 7: return Dyninst::aarch64::x7; - case 8: return Dyninst::aarch64::x8; - case 9: return Dyninst::aarch64::x9; - case 10: return Dyninst::aarch64::x10; - case 11: return Dyninst::aarch64::x11; - case 12: return Dyninst::aarch64::x12; - case 13: return Dyninst::aarch64::x13; - case 14: return Dyninst::aarch64::x14; - case 15: return Dyninst::aarch64::x15; - case 16: return Dyninst::aarch64::x16; - case 17: return Dyninst::aarch64::x17; - case 18: return Dyninst::aarch64::x18; - case 19: return Dyninst::aarch64::x19; - case 20: return Dyninst::aarch64::x20; - case 21: return Dyninst::aarch64::x21; - case 22: return Dyninst::aarch64::x22; - case 23: return Dyninst::aarch64::x23; - case 24: return Dyninst::aarch64::x24; - case 25: return Dyninst::aarch64::x25; - case 26: return Dyninst::aarch64::x26; - case 27: return Dyninst::aarch64::x27; - case 28: return Dyninst::aarch64::x28; - case 29: return Dyninst::aarch64::x29; - case 30: return Dyninst::aarch64::x30; - - case 100: return Dyninst::aarch64::sp; - case 101: return Dyninst::aarch64::pc; - case 102: return Dyninst::aarch64::pstate; - case 103: return Dyninst::aarch64::xzr; - default: - return InvalidReg; - } - default: - return InvalidReg; - } - return InvalidReg; -} +#include "dyn_regs.h" +#undef DYN_DEFINE_REGS +//clang-format: on diff --git a/common/src/freebsdHeaders.h b/common/src/freebsdHeaders.h index 16a77129d5..954bfebc06 100644 --- a/common/src/freebsdHeaders.h +++ b/common/src/freebsdHeaders.h @@ -33,6 +33,8 @@ #define _freebsd_headers_h #include +#include +#include #include #include #include diff --git a/common/src/freebsdKludges.C b/common/src/freebsdKludges.C index ffe32ea31b..3fe46d812b 100644 --- a/common/src/freebsdKludges.C +++ b/common/src/freebsdKludges.C @@ -28,6 +28,8 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include +#include "freebsdKludges.h" #include "common/src/headers.h" #include #include diff --git a/common/src/freebsdKludges.h b/common/src/freebsdKludges.h index e2c342e75c..d8ef0586e6 100644 --- a/common/src/freebsdKludges.h +++ b/common/src/freebsdKludges.h @@ -34,7 +34,8 @@ #include #include #include - +#include "dyntypes.h" +#include "common/src/vm_maps.h" #include #include diff --git a/common/src/headers.h b/common/src/headers.h index 9d331ed180..78e16f97eb 100644 --- a/common/src/headers.h +++ b/common/src/headers.h @@ -35,6 +35,8 @@ #define KLUDGES_H #include +#include +#include #ifndef FILE__ #define FILE__ strrchr(__FILE__, '/') ? strrchr(__FILE__, '/') + 1 : __FILE__ @@ -44,8 +46,6 @@ * Kludges to handle broken system includes and such... */ -#include "common/src/Types.h" - #if defined(os_linux) #include "common/src/linuxHeaders.h" diff --git a/common/src/linuxHeaders.h b/common/src/linuxHeaders.h index ad3ce57759..00e9943e1b 100644 --- a/common/src/linuxHeaders.h +++ b/common/src/linuxHeaders.h @@ -32,6 +32,8 @@ #if !defined(_linux_headers_h) #define _linux_headers_h +#include +#include #include #include #include @@ -60,6 +62,8 @@ #include #include "compiler_annotations.h" +#include "dyntypes.h" +#include "common/h/util.h" #define PDSOCKET_ERROR (-1) typedef int PDSOCKET; @@ -231,16 +235,16 @@ inline ssize_t P_recv(int s, void *buf, int len, int flags) { /* Ugly */ #if 0 -inline long int P_ptrace(int req, pid_t pid, Address addr, Address data, int word_len = -1) { - if (word_len != -1 && word_len != sizeof(Address)) { +inline long int P_ptrace(int req, pid_t pid, Dyninst::Address addr, Dyninst::Address data, int word_len = -1) { + if (word_len != -1 && word_len != sizeof(Dyninst::Address)) { return (ptrace((enum __ptrace_request)req, pid, (uint32_t)addr, (uint32_t)data)); } else { return (ptrace((enum __ptrace_request)req, pid, addr, data)); } } -// long int P_ptrace(int req, pid_t pid, Address addr, Address data, int word_len); +// long int P_ptrace(int req, pid_t pid, Dyninst::Address addr, Dyninst::Address data, int word_len); #else -inline long int P_ptrace(int req, pid_t pid, Address addr, Address data, int = -1) { +inline long int P_ptrace(int req, pid_t pid, Dyninst::Address addr, Dyninst::Address data, int = -1) { return (ptrace((enum __ptrace_request)req, pid, addr, data));} #endif diff --git a/common/src/linuxKludges.C b/common/src/linuxKludges.C index 195337c98f..fb0d8fb580 100644 --- a/common/src/linuxKludges.C +++ b/common/src/linuxKludges.C @@ -31,8 +31,6 @@ #include "common/src/headers.h" #include "common/src/parseauxv.h" #include "common/src/linuxKludges.h" -#include "common/src/Types.h" - #include #include @@ -112,13 +110,13 @@ std::string P_cplus_demangle( const std::string &symbol, bool includeTypes ) } /* end P_cplus_demangle() */ -bool PtraceBulkRead(Address inTraced, unsigned size, void *inSelf, int pid) +bool PtraceBulkRead(Dyninst::Address inTraced, unsigned size, void *inSelf, int pid) { static bool have_process_vm_readv = true; const unsigned char *ap = (const unsigned char*) inTraced; unsigned char *dp = (unsigned char *) inSelf; - Address w = 0x0; /* ptrace I/O buffer */ + Dyninst::Address w = 0x0; /* ptrace I/O buffer */ int len = sizeof(void *); unsigned cnt; @@ -158,7 +156,7 @@ bool PtraceBulkRead(Address inTraced, unsigned size, void *inSelf, int pid) /* Read the segment containing the unaligned portion, and copy what was requested to DP. */ errno = 0; - w = P_ptrace(PTRACE_PEEKDATA, pid, (Address) (ap-cnt), w, len); + w = P_ptrace(PTRACE_PEEKDATA, pid, (Dyninst::Address) (ap-cnt), w, len); if (errno) { return false; } @@ -176,7 +174,7 @@ bool PtraceBulkRead(Address inTraced, unsigned size, void *inSelf, int pid) /* Copy aligned portion */ while (size >= (u_int)len) { errno = 0; - w = P_ptrace(PTRACE_PEEKTEXT, pid, (Address) ap, 0, len); + w = P_ptrace(PTRACE_PEEKTEXT, pid, (Dyninst::Address) ap, 0, len); if (errno) { return false; } @@ -193,7 +191,7 @@ bool PtraceBulkRead(Address inTraced, unsigned size, void *inSelf, int pid) /* Read the segment containing the unaligned portion, and copy what was requested to DP. */ errno = 0; - w = P_ptrace(PTRACE_PEEKTEXT, pid, (Address) ap, 0, len); + w = P_ptrace(PTRACE_PEEKTEXT, pid, (Dyninst::Address) ap, 0, len); if (errno) { return false; } @@ -211,8 +209,8 @@ bool PtraceBulkWrite(Dyninst::Address inTraced, unsigned nbytes, unsigned char *ap = (unsigned char*) inTraced; const unsigned char *dp = (const unsigned char*) inSelf; - Address w = 0x0; /* ptrace I/O buffer */ - int len = sizeof(Address); /* address alignment of ptrace I/O requests */ + Dyninst::Address w = 0x0; /* ptrace I/O buffer */ + int len = sizeof(Dyninst::Address); /* address alignment of ptrace I/O requests */ unsigned cnt; if (0 == nbytes) { @@ -243,14 +241,14 @@ bool PtraceBulkWrite(Dyninst::Address inTraced, unsigned nbytes, } } - if ((cnt = ((Address)ap) % len)) { + if ((cnt = ((Dyninst::Address)ap) % len)) { /* Start of request is not aligned. */ unsigned char *p = (unsigned char*) &w; /* Read the segment containing the unaligned portion, edit in the data from DP, and write the segment back. */ errno = 0; - w = P_ptrace(PTRACE_PEEKTEXT, pid, (Address) (ap-cnt), 0); + w = P_ptrace(PTRACE_PEEKTEXT, pid, (Dyninst::Address) (ap-cnt), 0); if (errno) { return false; @@ -259,7 +257,7 @@ bool PtraceBulkWrite(Dyninst::Address inTraced, unsigned nbytes, for (unsigned i = 0; i < len-cnt && i < nbytes; i++) p[cnt+i] = dp[i]; - if (0 > P_ptrace(PTRACE_POKETEXT, pid, (Address) (ap-cnt), w)) { + if (0 > P_ptrace(PTRACE_POKETEXT, pid, (Dyninst::Address) (ap-cnt), w)) { return false; } @@ -274,9 +272,9 @@ bool PtraceBulkWrite(Dyninst::Address inTraced, unsigned nbytes, /* Copy aligned portion */ while (nbytes >= (u_int)len) { - assert(0 == ((Address)ap) % len); + assert(0 == ((Dyninst::Address)ap) % len); memcpy(&w, dp, len); - int retval = P_ptrace(PTRACE_POKETEXT, pid, (Address) ap, w); + int retval = P_ptrace(PTRACE_POKETEXT, pid, (Dyninst::Address) ap, w); if (retval < 0) { return false; } @@ -294,7 +292,7 @@ bool PtraceBulkWrite(Dyninst::Address inTraced, unsigned nbytes, /* Read the segment containing the unaligned portion, edit in the data from DP, and write it back. */ errno = 0; - w = P_ptrace(PTRACE_PEEKTEXT, pid, (Address) ap, 0); + w = P_ptrace(PTRACE_PEEKTEXT, pid, (Dyninst::Address) ap, 0); if (errno) { return false; @@ -304,7 +302,7 @@ bool PtraceBulkWrite(Dyninst::Address inTraced, unsigned nbytes, for (unsigned i = 0; i < nbytes; i++) p[i] = dp[i]; - if (0 > P_ptrace(PTRACE_POKETEXT, pid, (Address) ap, w)) { + if (0 > P_ptrace(PTRACE_POKETEXT, pid, (Dyninst::Address) ap, w)) { return false; } } @@ -325,7 +323,7 @@ bool PtraceBulkWrite(Dyninst::Address inTraced, unsigned nbytes, #define AT_SYSINFO_EHDR 33 #endif -static bool couldBeVsyscallPage(map_entries *entry, bool strict, Address) { +static bool couldBeVsyscallPage(map_entries *entry, bool strict, Dyninst::Address) { if (strict) { if (entry->prems != PREMS_PRIVATE) return false; @@ -352,7 +350,7 @@ bool AuxvParser::readAuxvInfo() uint32_t *buffer32 = NULL; uint64_t *buffer64 = NULL; unsigned pos = 0; - Address dso_start = 0x0, text_start = 0x0; + Dyninst::Address dso_start = 0x0, text_start = 0x0; struct { unsigned long type; @@ -428,7 +426,7 @@ bool AuxvParser::readAuxvInfo() * can be larger than a single page. Thus we look through /proc/pid/maps * for known, default, or guessed start address(es). **/ - std::vector
guessed_addrs; + std::vector guessed_addrs; /* The first thing to check is the auxvinfo, if we have any. */ if( dso_start != 0x0 ) @@ -458,7 +456,7 @@ bool AuxvParser::readAuxvInfo() map_entries *secondary_match = NULL; map_entries *maps = getVMMaps(pid, num_maps); for (unsigned i=0; istart || addr >= entry->end) @@ -618,9 +616,9 @@ static unsigned long get_word_at(process *p, unsigned long addr, bool &err) { * Check the machine's stack pointer, page align it, and start walking * back looking for an unaccessible page. **/ -static Address getStackTop(AddrSpaceReader *proc, bool &err) { - Address stack_pointer; - Address pagesize = getpagesize(); +static Dyninst::Address getStackTop(AddrSpaceReader *proc, bool &err) { + Dyninst::Address stack_pointer; + Dyninst::Address pagesize = getpagesize(); bool result; long word; err = false; @@ -941,51 +939,6 @@ bool findProcLWPs(pid_t pid, std::vector &lwps) closedir(dirhandle); return true; } - /** - * Linux 2.4: - * - * PIDs that are created by pthreads have a '.' prepending their name - * in /proc. We'll check all of those for the ones that have this lwp - * as a parent pid. - **/ - dirhandle = opendir("/proc"); - if (!dirhandle) - { - //No /proc directory. I give up. No threads for you. - return false; - } - while ((direntry = readdir(dirhandle)) != NULL) - { - if (direntry->d_name[0] != '.') { - //fprintf(stderr, "%s[%d]: Skipping entry %s\n", FILE__, __LINE__, direntry->d_name); - continue; - } - unsigned lwp_id = atoi(direntry->d_name+1); - int lwp_ppid = 0; - if (!lwp_id) - continue; - sprintf(name, "/proc/%u/status", lwp_id); - FILE *fd = P_fopen(name, "r"); - if (!fd) { - continue; - } - char buffer[1024]; - while (fgets(buffer, 1024, fd)) { - if (strncmp(buffer, "Tgid", 4) == 0) { - sscanf(buffer, "%*s %d", &lwp_ppid); - break; - } - } - - fclose(fd); - - if (lwp_ppid != pid) { - continue; - } - lwps.push_back(lwp_id); - } - closedir(dirhandle); - lwps.push_back(pid); - return true; + return false; } diff --git a/common/src/linuxKludges.h b/common/src/linuxKludges.h index e8d340c4bc..e8a521f736 100644 --- a/common/src/linuxKludges.h +++ b/common/src/linuxKludges.h @@ -33,6 +33,9 @@ #define _linux_kludges_h #include +#include "dyntypes.h" +#include "common/src/vm_maps.h" +#include "common/h/util.h" COMMON_EXPORT bool PtraceBulkRead(Dyninst::Address inTraced, unsigned size, void *inSelf, int pid); diff --git a/common/src/lprintf.h b/common/src/lprintf.h index 563fe2a808..02a41af63b 100644 --- a/common/src/lprintf.h +++ b/common/src/lprintf.h @@ -33,7 +33,6 @@ ************************************************************************/ - #if !defined(_lprintf_h_) @@ -41,7 +40,6 @@ #include "compiler_annotations.h" - /************************************************************************ @@ -54,7 +52,6 @@ extern COMMON_EXPORT void log_printf(void (*)(const char *), const char *, ...) extern COMMON_EXPORT void log_perror(void (*)(const char *), const char *); - #endif /* !defined(_lprintf_h_) */ diff --git a/common/src/ntHeaders.h b/common/src/ntHeaders.h index 55e0228bcc..8af397449b 100644 --- a/common/src/ntHeaders.h +++ b/common/src/ntHeaders.h @@ -34,8 +34,6 @@ #if !defined(pd_nt_headers_h) #define pd_nt_headers_h -#pragma warning( disable : 4996 ) - #include #include @@ -48,6 +46,8 @@ #include #include +#include +#include #include #include #include diff --git a/common/src/parseauxv.C b/common/src/parseauxv.C index f3b9b726b8..41fdacc4f7 100644 --- a/common/src/parseauxv.C +++ b/common/src/parseauxv.C @@ -97,7 +97,7 @@ AuxvParser::AuxvParser(int pid_, unsigned addr_size_) : create_err = !readAuxvInfo(); } -Address AuxvParser::getInterpreterBase() +Dyninst::Address AuxvParser::getInterpreterBase() { return interpreter_base; } @@ -107,27 +107,27 @@ bool AuxvParser::parsedVsyscall() return found_vsyscall; } -Address AuxvParser::getVsyscallBase() +Dyninst::Address AuxvParser::getVsyscallBase() { return vsyscall_base; } -Address AuxvParser::getVsyscallText() +Dyninst::Address AuxvParser::getVsyscallText() { return vsyscall_text; } -Address AuxvParser::getVsyscallEnd() +Dyninst::Address AuxvParser::getVsyscallEnd() { return vsyscall_end; } -Address AuxvParser::getProgramBase() +Dyninst::Address AuxvParser::getProgramBase() { return phdr; } -Address AuxvParser::getPageSize() +Dyninst::Address AuxvParser::getPageSize() { return page_size; } diff --git a/common/src/parseauxv.h b/common/src/parseauxv.h index 3f774f4054..a25fa1fd72 100644 --- a/common/src/parseauxv.h +++ b/common/src/parseauxv.h @@ -31,8 +31,9 @@ #ifndef auxvparser_h #define auxvparser_h -#include "common/src/Types.h" +#include "util.h" #include +#include "dyntypes.h" class COMMON_EXPORT AuxvParser { @@ -40,12 +41,12 @@ class COMMON_EXPORT AuxvParser int pid; unsigned ref_count; bool create_err; - Address interpreter_base; - Address vsyscall_base; - Address vsyscall_text; - Address vsyscall_end; + Dyninst::Address interpreter_base; + Dyninst::Address vsyscall_base; + Dyninst::Address vsyscall_text; + Dyninst::Address vsyscall_end; bool found_vsyscall; - Address phdr; + Dyninst::Address phdr; unsigned page_size; unsigned addr_size; @@ -53,7 +54,7 @@ class COMMON_EXPORT AuxvParser bool readAuxvInfo(); void *readAuxvFromProc(); void *readAuxvFromStack(); - Address getStackTop(bool &err); + Dyninst::Address getStackTop(bool &err); AuxvParser(int pid, unsigned asize); static std::map pid_to_parser; @@ -64,13 +65,13 @@ class COMMON_EXPORT AuxvParser void deleteAuxvParser(); ~AuxvParser(); - Address getInterpreterBase(); + Dyninst::Address getInterpreterBase(); bool parsedVsyscall(); - Address getVsyscallBase(); - Address getVsyscallText(); - Address getVsyscallEnd(); - Address getProgramBase(); - Address getPageSize(); + Dyninst::Address getVsyscallBase(); + Dyninst::Address getVsyscallText(); + Dyninst::Address getVsyscallEnd(); + Dyninst::Address getProgramBase(); + Dyninst::Address getPageSize(); }; diff --git a/common/src/pathName.C b/common/src/pathName.C index 3942fd54b0..33d6ad7e16 100644 --- a/common/src/pathName.C +++ b/common/src/pathName.C @@ -34,9 +34,9 @@ #include #include #include "common/src/pathName.h" -#include -#include -#include +#include +#include +#include #if defined(os_windows) //ccw 20 july 2000 : 29 mar 2001 #define S_ISDIR(x) ((x) & _S_IFDIR) @@ -268,7 +268,7 @@ bool executableFromArgv0AndPathAndCwd(std::string &result, std::string extract_pathname_tail(const std::string &path) { - boost::filesystem::path p(path); + std::filesystem::path p(path); return p.filename().string(); } @@ -276,26 +276,28 @@ std::string resolve_file_path(char const* path) { return resolve_file_path(std::string{path}); } std::string resolve_file_path(std::string path) { - namespace ba = boost::algorithm; - namespace bf = boost::filesystem; + namespace bf = std::filesystem; // Remove all leading and trailing spaces in-place. - ba::trim(path); + auto not_space = [](unsigned char c){ return !std::isspace(c); }; + path.erase(path.begin(), std::find_if(path.begin(), path.end(), not_space)); + path.erase(std::find_if(path.rbegin(), path.rend(), not_space).base(), path.end()); #ifndef os_windows // On Linux-like OSes, collapse doubled directory separators - // similar to POSIX `realpath`. On Windows, '//' is a (possibly) - // meaningful separator, so don't change it. - ba::replace_all(path, "//", "/"); + std::string::size_type pos = 0; + while((pos = path.find("//", pos)) != std::string::npos) { + path.replace(pos, 2, "/"); + } #endif // If it has a tilde, expand tilde pathname // This is a no-op on Windows if(path.find("~") != std::string::npos) { - path = std::move(expand_tilde_pathname(path)); + path = expand_tilde_pathname(path); } - // Convert to a boost::filesystem::path + // Convert to a std::filesystem::path // This makes a copy of `path`. auto boost_path = bf::path(path); @@ -312,15 +314,11 @@ std::string resolve_file_path(std::string path) { * * NOTE: makes a copy of the path. */ - boost::system::error_code ec; + std::error_code ec; auto canonical_path = bf::canonical(boost_path, ec); - if(ec != boost::system::errc::success) { + if(ec) { return {}; } - /* This is a bit strange, but is most optimal as it is the only - * member string-conversion function that does not inhibit moving - * the return value out (required here by C++11). - */ - return canonical_path.string(); + return canonical_path.string(); } diff --git a/common/src/pfq-rwlock.C b/common/src/pfq-rwlock.C index 267ecfbe08..a102077e87 100644 --- a/common/src/pfq-rwlock.C +++ b/common/src/pfq-rwlock.C @@ -92,12 +92,12 @@ dyn_rwlock::~dyn_rwlock() { void dyn_rwlock::lock_shared() { // Register a ticket, and check for writers. - unsigned int ticket = rin.fetch_add(TICKET, boost::memory_order_acquire); + unsigned int ticket = rin.fetch_add(TICKET, std::memory_order_acquire); unsigned int phase = ticket & PHASE; if (ticket & WRITER) { // There is a writer present, try to wait. - boost::unique_lock l(inlock); + dyncompat::unique_lock l(inlock); rcond.wait(l, [this,&phase](){ return rwakeup[phase]; }); } @@ -112,11 +112,11 @@ void dyn_rwlock::unlock_shared() { ANNOTATE_RWLOCK_RELEASED(this, 0 /* reader mode */); // Pull off an outgoing ticket and see if we're the last reader. - unsigned int ticket = rout.fetch_add(TICKET, boost::memory_order_acq_rel); + unsigned int ticket = rout.fetch_add(TICKET, std::memory_order_acq_rel); if (ticket & WRITER && ticket == last) { // Wake up the writer, its our job. - boost::unique_lock l(outlock); + dyncompat::unique_lock l(outlock); wwakeup = true; wcond.notify_one(); } @@ -127,16 +127,16 @@ void dyn_rwlock::lock() { wlock.lock(); // Choose the final reader, and make sure no others come in. - unsigned int lr = rin.fetch_xor(PHASE|WRITER, boost::memory_order_acquire); + unsigned int lr = rin.fetch_xor(PHASE|WRITER, std::memory_order_acquire); last = (lr - TICKET) ^ (PHASE | WRITER); // Let the last reader know that they should wake me up. // Rel to "release" the previous write to last. - unsigned int cr = rout.fetch_xor(PHASE|WRITER, boost::memory_order_acq_rel); + unsigned int cr = rout.fetch_xor(PHASE|WRITER, std::memory_order_acq_rel); if (cr != lr) { // There actually was a reader inside. Wait for him to leave. - boost::unique_lock l(outlock); + dyncompat::unique_lock l(outlock); wcond.wait(l, [this](){ return wwakeup; }); wwakeup = false; } @@ -155,15 +155,15 @@ void dyn_rwlock::unlock() { ANNOTATE_RWLOCK_RELEASED(this, 1 /* writer mode */); // Make sure any speedy readers don't try to wake me up again. - rout.fetch_xor(WRITER, boost::memory_order_relaxed); + rout.fetch_xor(WRITER, std::memory_order_relaxed); // Let in any new readers, since we're done with it at the moment. - unsigned int phase = rin.fetch_xor(WRITER, boost::memory_order_acq_rel); + unsigned int phase = rin.fetch_xor(WRITER, std::memory_order_acq_rel); phase &= PHASE; // Wake up any readers that were waiting for us. { - boost::unique_lock l(inlock); + dyncompat::unique_lock l(inlock); rwakeup[phase] = true; rcond.notify_all(); } diff --git a/common/src/pool_allocators.h b/common/src/pool_allocators.h index 1456d3be84..e69de29bb2 100644 --- a/common/src/pool_allocators.h +++ b/common/src/pool_allocators.h @@ -1,66 +0,0 @@ -/* - * See the dyninst/COPYRIGHT file for copyright information. - * - * We provide the Paradyn Tools (below described as "Paradyn") - * on an AS IS basis, and do not warrant its validity or performance. - * We reserve the right to update, modify, or discontinue this - * software at any time. We shall have no obligation to supply such - * updates or modifications or any other form of support to you. - * - * By your use of Paradyn, you understand and agree that we (or any - * other person or entity with proprietary rights in Paradyn) are - * under no obligation to provide either maintenance services, - * update services, notices of latent defects, or correction of - * defects for Paradyn. - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - */ -#if !defined(POOL_ALLOCATORS_H) -#define POOL_ALLOCATORS_H - - -#include -#include -#include - -template -struct unlocked_fast_alloc -{ - typedef boost::fast_pool_allocator type; -}; - -template -struct unlocked_pool_alloc -{ - typedef boost::pool_allocator type; -}; - -template -struct pooled_set -{ - typedef std::set, typename unlocked_fast_alloc::type > type; -}; - - -template -struct pooled_vector -{ - typedef std::vector::type > type; -}; - - - - -#endif //!defined(POOL_ALLOCATORS_H) diff --git a/common/src/refCounter.h b/common/src/refCounter.h deleted file mode 100644 index 51ebd90e80..0000000000 --- a/common/src/refCounter.h +++ /dev/null @@ -1,130 +0,0 @@ -/* - * See the dyninst/COPYRIGHT file for copyright information. - * - * We provide the Paradyn Tools (below described as "Paradyn") - * on an AS IS basis, and do not warrant its validity or performance. - * We reserve the right to update, modify, or discontinue this - * software at any time. We shall have no obligation to supply such - * updates or modifications or any other form of support to you. - * - * By your use of Paradyn, you understand and agree that we (or any - * other person or entity with proprietary rights in Paradyn) are - * under no obligation to provide either maintenance services, - * update services, notices of latent defects, or correction of - * defects for Paradyn. - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - */ - - -// $Id: refCounter.h,v 1.7 2007/05/30 19:20:03 legendre Exp $ -// refCounter.h -// Ariel Tamches - -#ifndef _REF_COUNTER_H_ -#define _REF_COUNTER_H_ - -#ifdef external_templates -#pragma interface -#endif - -#include - -template -class refCounter { - private: - class actualData { - private: - mutable unsigned refCount; - T data; - public: - actualData(const T &src) : data(src) {refCount=0;} - ~actualData() {} - void reference() const {refCount++;} - bool dereference() const { - assert(refCount > 0); - return (--refCount == 0); - } - T &getData() {return data;} - const T &getData() const {return data;} - }; - actualData *theData; - // allocated with new, but not necessarily by us. _Never_ NULL. - - private: - void reference() const { - assert(theData); - theData->reference(); - } - void dereference() const { - assert(theData); - if (theData->dereference()) - delete theData; - } - - // explicitly disallowed - // (Visual C++ still requires a body, however) - refCounter() {} - - public: - refCounter(const T &src) { - // examples: - // T y; (y is initialized somehow...) - // refCounter x = y; or - // refCounter x(y); - theData = new actualData(src); - assert(theData); - reference(); - } - refCounter(const refCounter &src) { - // This constructor is what this whole class revolves around. It's fast. - // examples: - // refCounter y; (y is initialized somehow...) - // refCounter x = y; or - // refCounter x(y); - src.reference(); // just bumps up a ref count --> fast - theData = src.theData; // just a ptr assignment --> fast - } - ~refCounter() { - dereference(); - } - refCounter &operator=(const refCounter &src) { - if (this == &src) - return *this; // protect against x=x - - dereference(); - - // ...and attach to the new stuff efficiently - theData = src.theData; // just a ptr assignment --> fast - reference(); // just bumps a ref cnt --> fast - return *this; - } - refCounter &operator=(const T &src) { - dereference(); - theData = new actualData(src); - reference(); - return *this; - } - T &getData() { - assert(theData); - return theData->getData(); - } - const T &getData() const { - assert(theData); - return theData->getData(); - } -}; - -#endif diff --git a/common/src/registers/MachRegister.C b/common/src/registers/MachRegister.C new file mode 100644 index 0000000000..8d02c1b0bf --- /dev/null +++ b/common/src/registers/MachRegister.C @@ -0,0 +1,2633 @@ +#include +#include "common/h/registers/MachRegister.h" +#include "debug_common.h" +#include "dyn_regs.h" +#include "external/rose/amdgpuInstructionEnum.h" +#include "external/rose/armv8InstructionEnum.h" +#include "external/rose/powerpcInstructionEnum.h" +#include "external/rose/rose-compat.h" + +#include +#include + +namespace { + std::unordered_map names; + const std::string invalid_reg_name{""}; +} + +namespace Dyninst { + + MachRegister::MachRegister() : reg(0) {} + + MachRegister::MachRegister(signed int r) : reg(r) {} + + MachRegister::MachRegister(signed int r, std::string n) : reg(r) { names.emplace(r, std::move(n)); } + + unsigned int MachRegister::regClass() const { return reg & 0x00ff0000; } + + MachRegister MachRegister::getBaseRegister() const { + signed int category = (reg & 0x00ff0000); + switch(getArchitecture()) { + case Arch_x86: + if(category == x86::GPR) + return MachRegister(reg & 0xffff00ff); + else if(category == x86::FLAG) + return x86::flags; + else if(category == x86::MMX) + // Keep the register number, but change the category to X87 (e.g., MMX1 -> st1). + return MachRegister((reg & ~0x00ff0000) | x86::X87); + else if(category == x86::XMM) + // assume CPU is new enough that it always has AVX registers + // Keep the register number, but change the category to ZMM (e.g., XMM1 -> ZMM1). + return MachRegister((reg & ~0x00ff0000) | x86::ZMM); + else if(category == x86::YMM) + // assume CPU is new enough that it always has AVX-512 registers + // Keep the register number, but change the category to ZMM (e.g., YMM1 -> ZMM1). + return MachRegister((reg & ~0x00ff0000) | x86::ZMM); + else + return *this; + case Arch_x86_64: + if(category == x86_64::GPR) + return MachRegister(reg & 0xffff00ff); + else if(category == x86_64::FLAG) + return x86_64::flags; + else if(category == x86_64::MMX) + // Keep the register number, but change the category to X87 (e.g., MMX1 -> st1). + return MachRegister((reg & ~0x00ff0000) | x86_64::X87); + else if(category == x86_64::XMM) + // Keep the register number, but change the category to ZMM (e.g., XMM1 -> ZMM1). + return MachRegister((reg & ~0x00ff0000) | x86_64::ZMM); + else if(category == x86_64::YMM) + // Keep the register number, but change the category to ZMM (e.g., YMM1 -> ZMM1). + return MachRegister((reg & ~0x00ff0000) | x86_64::ZMM); + else + return *this; + case Arch_ppc32: + case Arch_ppc64: + case Arch_none: return *this; + case Arch_amdgpu_gfx908: + switch(category) { + case amdgpu_gfx908::SGPR: return MachRegister((reg & 0x000000ff) | amdgpu_gfx908::s0); + case amdgpu_gfx908::VGPR: return MachRegister((reg & 0x000000ff) | amdgpu_gfx908::v0); + case amdgpu_gfx908::HWR: return MachRegister(reg); + + default: return *this; + } + + case Arch_amdgpu_gfx90a: + switch(category) { + case amdgpu_gfx90a::SGPR: return MachRegister((reg & 0x000000ff) | amdgpu_gfx90a::s0); + case amdgpu_gfx90a::VGPR: return MachRegister((reg & 0x000000ff) | amdgpu_gfx90a::v0); + case amdgpu_gfx90a::HWR: return MachRegister(reg); + + default: return *this; + } + case Arch_amdgpu_gfx940: + switch(category) { + case amdgpu_gfx940::SGPR: return MachRegister((reg & 0x000000ff) | amdgpu_gfx940::s0); + case amdgpu_gfx940::VGPR: return MachRegister((reg & 0x000000ff) | amdgpu_gfx940::v0); + case amdgpu_gfx940::HWR: return MachRegister(reg); + + default: return *this; + } + + case Arch_aarch32: + case Arch_aarch64: + case Arch_intelGen9: + case Arch_cuda: + // not verified + return *this; + default: return InvalidReg; + } + return InvalidReg; + } + + Architecture MachRegister::getArchitecture() const { return (Architecture)(reg & 0xff000000); } + + bool MachRegister::isValid() const { return (reg != InvalidReg.reg); } + + std::string const& MachRegister::name() const { + auto iter = names.find(reg); + if(iter != names.end()) { + return iter->second; + } + common_parsing_printf("No MachRegister found with value %x\n", static_cast(reg)); + return invalid_reg_name; + } + + unsigned int MachRegister::size() const { + switch(getArchitecture()) { + case Arch_x86: + switch(reg & 0x0000ff00) { + case x86::FULL: return 4; + case x86::BIT: return 0; + case x86::L_REG: + case x86::H_REG: return 1; + case x86::W_REG: return 2; + case x86::FPDBL: return 10; + case x86::MMS: return 8; + case x86::XMMS: return 16; + case x86::YMMS: return 32; + case x86::ZMMS: return 64; + case x86::KMSKS: return 8; + default: + return 0; + } + break; + case Arch_x86_64: + switch(reg & 0x0000ff00) { + case x86_64::L_REG: + case x86_64::H_REG: return 1; + case x86_64::W_REG: return 2; + case x86_64::D_REG: return 4; + case x86_64::FULL: return 8; + case x86_64::MMS: return 8; + case x86_64::XMMS: return 16; + case x86_64::FPDBL: return 10; + case x86_64::BIT: return 0; + case x86_64::YMMS: return 32; + case x86_64::ZMMS: return 64; + case x86_64::KMSKS: return 8; + default: + return 0; // Xiaozhu: return 0 as an indication of parsing junk. + } + break; + case Arch_ppc32: { + int reg_class = reg & 0x00ff0000; + if(reg_class == ppc32::FPR || reg_class == ppc32::FSR) + return 8; + return 4; + } + case Arch_ppc64: { + if((reg & 0x00ff0000) == aarch64::FPR) + return 16; + return 8; + } + case Arch_aarch32: assert(0); break; + + case Arch_cuda: return 8; + case Arch_amdgpu_gfx908: { + int reg_class = (reg & 0x00ff0000); + if(reg_class == amdgpu_gfx908::SGPR || reg_class == amdgpu_gfx908::VGPR) { + return 4; + } else { + switch(reg & 0x00007f00) { + case amdgpu_gfx908::BITS_1: + case amdgpu_gfx908::BITS_2: + case amdgpu_gfx908::BITS_3: + case amdgpu_gfx908::BITS_4: + case amdgpu_gfx908::BITS_6: + case amdgpu_gfx908::BITS_7: + case amdgpu_gfx908::BITS_8: return 1; + case amdgpu_gfx908::BITS_9: + case amdgpu_gfx908::BITS_15: + case amdgpu_gfx908::BITS_16: return 2; + case amdgpu_gfx908::BITS_32: return 4; + case amdgpu_gfx908::BITS_48: return 6; + case amdgpu_gfx908::BITS_64: return 8; + case amdgpu_gfx908::BITS_128: return 16; + case amdgpu_gfx908::BITS_256: return 32; + case amdgpu_gfx908::BITS_512: return 64; + default: + common_parsing_printf(" unknown reg size %x\n", (unsigned int)reg); + assert(0); + } + } + } + break; + case Arch_amdgpu_gfx90a: { + int reg_class = (reg & 0x00ff0000); + if(reg_class == amdgpu_gfx90a::SGPR || reg_class == amdgpu_gfx90a::VGPR) { + return 4; + } else { + switch(reg & 0x00007f00) { + case amdgpu_gfx90a::BITS_1: + case amdgpu_gfx90a::BITS_2: + case amdgpu_gfx90a::BITS_3: + case amdgpu_gfx90a::BITS_4: + case amdgpu_gfx90a::BITS_6: + case amdgpu_gfx90a::BITS_7: + case amdgpu_gfx90a::BITS_8: return 1; + case amdgpu_gfx90a::BITS_9: + case amdgpu_gfx90a::BITS_15: + case amdgpu_gfx90a::BITS_16: return 2; + case amdgpu_gfx90a::BITS_32: return 4; + case amdgpu_gfx90a::BITS_48: return 6; + case amdgpu_gfx90a::BITS_64: return 8; + case amdgpu_gfx90a::BITS_128: return 16; + case amdgpu_gfx90a::BITS_256: return 32; + case amdgpu_gfx90a::BITS_512: return 64; + default: + common_parsing_printf(" unknown reg size %x\n", (unsigned int)reg); + assert(0); + } + } + } + break; + case Arch_amdgpu_gfx940: { + int reg_class = (reg & 0x00ff0000); + if(reg_class == amdgpu_gfx940::SGPR || reg_class == amdgpu_gfx940::VGPR) { + return 4; + } else { + switch(reg & 0x00007f00) { + case amdgpu_gfx940::BITS_1: + case amdgpu_gfx940::BITS_2: + case amdgpu_gfx940::BITS_3: + case amdgpu_gfx940::BITS_4: + case amdgpu_gfx940::BITS_6: + case amdgpu_gfx940::BITS_7: + case amdgpu_gfx940::BITS_8: return 1; + case amdgpu_gfx940::BITS_9: + case amdgpu_gfx940::BITS_15: + case amdgpu_gfx940::BITS_16: return 2; + case amdgpu_gfx940::BITS_32: return 4; + case amdgpu_gfx940::BITS_48: return 6; + case amdgpu_gfx940::BITS_64: return 8; + case amdgpu_gfx940::BITS_128: return 16; + case amdgpu_gfx940::BITS_256: return 32; + case amdgpu_gfx940::BITS_512: return 64; + default: + common_parsing_printf(" unknown reg size %x\n", (unsigned int)reg); + assert(0); + } + } + } + break; + case Arch_aarch64: { + if((reg & 0x00ff0000) == aarch64::FPR) { + switch(reg & 0x0000ff00) { + case aarch64::B_REG: return 1; + case aarch64::W_REG: return 2; + case aarch64::D_REG: return 4; + case aarch64::FULL: + case aarch64::HQ_REG: return 8; + case aarch64::Q_REG: return 16; + default: assert(0); return 0; + } + } else if((reg & 0x00ff0000) == aarch64::GPR || (reg & 0x00ff0000) == aarch64::SPR || + (reg & 0x00ff0000) == aarch64::SYSREG || (reg & 0x00ff0000) == aarch64::FLAG) + switch(reg & 0x0000ff00) { + case aarch64::FULL: return 8; + case aarch64::D_REG: return 4; + case aarch64::BIT: return 0; + default: return 0; + } + else + return 4; + break; + } + case Arch_intelGen9: { + assert(0); + break; + } + + case Arch_none: return 0; + } + return 0; // Unreachable, but disable warnings + } + + bool MachRegister::operator<(const MachRegister& a) const { return (reg < a.reg); } + + bool MachRegister::operator==(const MachRegister& a) const { return (reg == a.reg); } + + MachRegister::operator signed int() const { return reg; } + + signed int MachRegister::val() const { return reg; } + + MachRegister MachRegister::getPC(Dyninst::Architecture arch) { + switch(arch) { + case Arch_x86: return x86::eip; + case Arch_x86_64: return x86_64::rip; + case Arch_ppc32: return ppc32::pc; + case Arch_ppc64: return ppc64::pc; + case Arch_aarch64: // aarch64: pc is not writable + return aarch64::pc; + case Arch_aarch32: return InvalidReg; + case Arch_cuda: return cuda::pc; + case Arch_intelGen9: return InvalidReg; + case Arch_amdgpu_gfx908: return amdgpu_gfx908::pc_all; + case Arch_amdgpu_gfx90a: return amdgpu_gfx90a::pc_all; + case Arch_amdgpu_gfx940: return amdgpu_gfx940::pc_all; + case Arch_none: return InvalidReg; + } + return InvalidReg; + } + + MachRegister MachRegister::getReturnAddress(Dyninst::Architecture arch) { + switch(arch) { + case Arch_x86: assert(0); break; // not implemented + case Arch_x86_64: assert(0); break; // not implemented + case Arch_ppc32: assert(0); break; // not implemented + case Arch_ppc64: assert(0); break; // not implemented + case Arch_aarch64: // aarch64: x30 stores the RA for current frame + return aarch64::x30; + case Arch_aarch32: + case Arch_cuda: + case Arch_amdgpu_gfx908: + case Arch_amdgpu_gfx90a: + case Arch_amdgpu_gfx940: + case Arch_intelGen9: assert(0); break; + case Arch_none: return InvalidReg; + } + return InvalidReg; + } + + MachRegister MachRegister::getFramePointer(Dyninst::Architecture arch) { + switch(arch) { + case Arch_x86: return x86::ebp; + case Arch_x86_64: return x86_64::rbp; + case Arch_ppc32: return ppc32::r1; + case Arch_ppc64: return ppc64::r1; + case Arch_aarch64: return aarch64::x29; // aarch64: frame pointer is X29 by convention + case Arch_aarch32: + case Arch_cuda: + case Arch_intelGen9: + case Arch_amdgpu_gfx908: + case Arch_amdgpu_gfx90a: + case Arch_amdgpu_gfx940: + case Arch_none: return InvalidReg; + } + return InvalidReg; + } + + MachRegister MachRegister::getStackPointer(Dyninst::Architecture arch) { + switch(arch) { + case Arch_x86: return x86::esp; + case Arch_x86_64: return x86_64::rsp; + case Arch_ppc32: return ppc32::r1; + case Arch_ppc64: return ppc64::r1; + case Arch_aarch64: return aarch64::sp; // aarch64: stack pointer is an independent register + case Arch_aarch32: + case Arch_cuda: + case Arch_intelGen9: + case Arch_amdgpu_gfx908: + case Arch_amdgpu_gfx90a: + case Arch_amdgpu_gfx940: + case Arch_none: return InvalidReg; + } + return InvalidReg; + } + + MachRegister MachRegister::getSyscallNumberReg(Dyninst::Architecture arch) { + switch(arch) { + case Arch_x86: return x86::eax; + case Arch_x86_64: return x86_64::rax; + case Arch_ppc32: return ppc32::r0; + case Arch_ppc64: return ppc64::r0; + case Arch_aarch64: return aarch64::x8; + case Arch_aarch32: + case Arch_cuda: + case Arch_intelGen9: + case Arch_amdgpu_gfx908: + case Arch_amdgpu_gfx90a: + case Arch_amdgpu_gfx940: + case Arch_none: return InvalidReg; + } + return InvalidReg; + } + + MachRegister MachRegister::getSyscallNumberOReg(Dyninst::Architecture arch) { + switch(arch) { + case Arch_x86: return x86::oeax; + case Arch_x86_64: return x86_64::orax; + case Arch_ppc32: return ppc32::r0; + case Arch_ppc64: return ppc64::r0; + case Arch_aarch64: return aarch64::x8; + case Arch_none: return InvalidReg; + default: assert(0); return InvalidReg; + } + return InvalidReg; + } + + MachRegister MachRegister::getSyscallReturnValueReg(Dyninst::Architecture arch) { + switch(arch) { + case Arch_x86: return x86::eax; + case Arch_x86_64: return x86_64::rax; + case Arch_ppc32: return ppc32::r3; + case Arch_ppc64: return ppc64::r3; + case Arch_aarch64: return aarch64::x0; // returned value is save in x0 + case Arch_aarch32: + case Arch_cuda: + case Arch_intelGen9: + case Arch_amdgpu_gfx908: + case Arch_amdgpu_gfx90a: + case Arch_amdgpu_gfx940: + case Arch_none: return InvalidReg; + } + return InvalidReg; + } + + MachRegister MachRegister::getArchRegFromAbstractReg(MachRegister abstract, + Dyninst::Architecture arch) { + switch(arch) { + case Arch_aarch64: + if(abstract == ReturnAddr) + return aarch64::x30; + if(abstract == FrameBase) + return aarch64::x29; + if(abstract == StackTop) + return aarch64::sp; + if(abstract == CFA) + assert(0); // don't know what to do + // not abstract, return arch reg + return abstract; + default: assert(0); + } + + return Dyninst::InvalidReg; + } + + MachRegister MachRegister::getZeroFlag(Dyninst::Architecture arch) { + switch(arch) { + case Arch_x86: return x86::zf; + case Arch_x86_64: return x86_64::zf; + case Arch_ppc32: return ppc32::cr0e; + case Arch_ppc64: return ppc64::cr0e; + case Arch_aarch64: return aarch64::z; + case Arch_aarch32: + case Arch_cuda: + case Arch_intelGen9: + case Arch_amdgpu_gfx908: + case Arch_amdgpu_gfx90a: + case Arch_amdgpu_gfx940: + case Arch_none: return InvalidReg; + } + + return InvalidReg; + } + + bool MachRegister::isPC() const { + if(*this == InvalidReg) return false; + return *this == getPC(getArchitecture()); + } + + bool MachRegister::isFramePointer() const { + if(*this == InvalidReg) return false; + return *this == FrameBase || *this == getFramePointer(getArchitecture()); + } + + bool MachRegister::isStackPointer() const { + if(*this == InvalidReg) return false; + return *this == StackTop || *this == getStackPointer(getArchitecture()); + } + + bool MachRegister::isSyscallNumberReg() const { + if(*this == InvalidReg) return false; + return *this == getSyscallNumberReg(getArchitecture()); + } + + bool MachRegister::isSyscallReturnValueReg() const { + if(*this == InvalidReg) return false; + return *this == getSyscallReturnValueReg(getArchitecture()); + } + + bool MachRegister::isFlag() const { + int regC = regClass(); + switch(getArchitecture()) { + case Arch_x86: return regC == x86::FLAG; + case Arch_x86_64: return regC == x86_64::FLAG; + case Arch_aarch64: return regC == aarch64::FLAG; + case Arch_ppc32: + case Arch_ppc64: { + // For power, we have a different register representation. + // We do not use the subrange field for MachReigsters + // and all lower 32 bits are base ID + int baseID = reg & 0x0000FFFF; + return (baseID <= 731 && baseID >= 700) || (baseID <= 629 && baseID >= 621); + } + case Arch_amdgpu_gfx908: + case Arch_amdgpu_gfx90a: + case Arch_amdgpu_gfx940: { + return (reg & 0x0000F000); + } + case Arch_cuda: return false; + + default: assert(!"Not implemented!"); + } + return false; + } + + bool MachRegister::isZeroFlag() const { + if(*this == InvalidReg) return false; + switch(getArchitecture()) { + case Arch_ppc32: + case Arch_ppc64: { + // For power, we have a different register representation. + // We do not use the subrange field for MachReigsters + // and all lower 32 bits are base ID + int baseID = reg & 0x0000FFFF; + return (baseID <= 731 && baseID >= 700 && baseID % 4 == 2) || + (baseID <= 628 && baseID >= 621); + } + default: + return *this == getZeroFlag(getArchitecture()); + } + return false; + } + + // reg_idx needs to be set as the offset from base register + // offset needs to be set as the offset inside the register + + static void getAmdgpuGfx908RoseRegister(int& reg_class, int& reg_idx, int& offset, + const int& reg) { + signed int category = (reg & 0x00ff0000); + signed int baseID = (reg & 0x000000ff); + + offset = 0; + reg_idx = baseID; + switch(category) { + case amdgpu_gfx908::SGPR: { + reg_class = amdgpu_regclass_sgpr; + break; + } + + case amdgpu_gfx908::VGPR: { + reg_class = amdgpu_regclass_vgpr; + break; + } + + case amdgpu_gfx908::PC: { + reg_class = amdgpu_regclass_pc; + reg_idx = amdgpu_pc; + break; + } + + case amdgpu_gfx908::HWR: { + reg_class = amdgpu_regclass_pc; + reg_idx = amdgpu_pc; + break; + } + + default: { + assert(0 && "unsupported register type for amdgpu gfx908"); + } + } + return; + } + + static void getAmdgpuGfx90aRoseRegister(int& reg_class, int& reg_idx, int& offset, + const int& reg) { + signed int category = (reg & 0x00ff0000); + signed int baseID = (reg & 0x000000ff); + + offset = 0; + reg_idx = baseID; + switch(category) { + case amdgpu_gfx90a::SGPR: { + reg_class = amdgpu_regclass_sgpr; + break; + } + + case amdgpu_gfx90a::VGPR: { + reg_class = amdgpu_regclass_vgpr; + break; + } + + case amdgpu_gfx90a::PC: { + reg_class = amdgpu_regclass_pc; + reg_idx = amdgpu_pc; + break; + } + + case amdgpu_gfx90a::HWR: { + reg_class = amdgpu_regclass_pc; + reg_idx = amdgpu_pc; + break; + } + + default: { + assert(0 && "unsupported register type for amdgpu gfx90a"); + } + } + return; + } + + static void getAmdgpuGfx940RoseRegister(int& reg_class, int& reg_idx, int& offset, + const int& reg) { + signed int category = (reg & 0x00ff0000); + signed int baseID = (reg & 0x000000ff); + + offset = 0; + reg_idx = baseID; + switch(category) { + case amdgpu_gfx940::SGPR: { + reg_class = amdgpu_regclass_sgpr; + break; + } + + case amdgpu_gfx940::VGPR: { + reg_class = amdgpu_regclass_vgpr; + break; + } + + case amdgpu_gfx940::PC: { + reg_class = amdgpu_regclass_pc; + reg_idx = amdgpu_pc; + break; + } + + case amdgpu_gfx940::HWR: { + reg_class = amdgpu_regclass_pc; + reg_idx = amdgpu_pc; + break; + } + + default: { + assert(0 && "unsupported register type for amdgpu gfx940"); + } + } + return; + } + + /* This function should has a boolean return value + * to indicate whether there is a corresponding + * ROSE register. + * + * Since historically, this function does not + * have a return value. We set c to -1 to represent + * error cases + * c is set to regClass + * n is set to regNum + * p is set to regPosition + * see dataflowAPI/src/ExpressionConversionVisitor.C + */ + + void MachRegister::getROSERegister(int& c, int& n, int& p) { + // Rose: class, number, position + // Dyninst: category, base id, subrange + + signed int category = (reg & 0x00ff0000); + signed int subrange = (reg & 0x0000ff00); + signed int baseID = (reg & 0x000000ff); + + switch(getArchitecture()) { + case Arch_amdgpu_gfx908: { + getAmdgpuGfx908RoseRegister(c, n, p, reg); + return; + } + case Arch_amdgpu_gfx90a: { + getAmdgpuGfx90aRoseRegister(c, n, p, reg); + return; + } + case Arch_amdgpu_gfx940: { + getAmdgpuGfx940RoseRegister(c, n, p, reg); + return; + } + case Arch_x86: + switch(category) { + case x86::GPR: + c = x86_regclass_gpr; + switch(baseID) { + case x86::BASEA: n = x86_gpr_ax; break; + case x86::BASEC: n = x86_gpr_cx; break; + case x86::BASED: n = x86_gpr_dx; break; + case x86::BASEB: n = x86_gpr_bx; break; + case x86::BASESP: n = x86_gpr_sp; break; + case x86::BASEBP: n = x86_gpr_bp; break; + case x86::BASESI: n = x86_gpr_si; break; + case x86::BASEDI: n = x86_gpr_di; break; + default: n = 0; break; + } + break; + case x86::SEG: + c = x86_regclass_segment; + switch(baseID) { + case x86::BASEDS: n = x86_segreg_ds; break; + case x86::BASEES: n = x86_segreg_es; break; + case x86::BASEFS: n = x86_segreg_fs; break; + case x86::BASEGS: n = x86_segreg_gs; break; + case x86::BASECS: n = x86_segreg_cs; break; + case x86::BASESS: n = x86_segreg_ss; break; + default: n = 0; break; + } + break; + case x86::FLAG: + c = x86_regclass_flags; + switch(baseID) { + case x86::CF: n = x86_flag_cf; break; + case x86::PF: n = x86_flag_pf; break; + case x86::AF: n = x86_flag_af; break; + case x86::ZF: n = x86_flag_zf; break; + case x86::SF: n = x86_flag_sf; break; + case x86::TF: n = x86_flag_tf; break; + case x86::IF: n = x86_flag_if; break; + case x86::DF: n = x86_flag_df; break; + case x86::OF: n = x86_flag_of; break; + case x86::FLAGC: n= x86_flag_iopl0; break; + case x86::FLAGD: n= x86_flag_iopl1; break; + case x86::NT: n = x86_flag_nt; break; + case x86::RF: n = x86_flag_rf; break; + case x86::VM: n= x86_flag_vm; break; + case x86::AC: n = x86_flag_ac; break; + case x86::VIF: n = x86_flag_vif; break; + case x86::VIP: n = x86_flag_vip; break; + case x86::ID: n = x86_flag_id; break; + default: assert(0); break; + } + break; + case x86::MISC: c = x86_regclass_unknown; break; + case x86::XMM: + c = x86_regclass_xmm; + n = baseID; + break; + case x86::MMX: + c = x86_regclass_mm; + n = baseID; + break; + case x86::X87: + c = x86_regclass_st_top; + n = baseID; + break; + case x86::YMM: + c = x86_regclass_ymm; + n = baseID; + break; + case x86::ZMM: + c = x86_regclass_zmm; + n = baseID; + break; + case x86::CTL: + c = x86_regclass_cr; + n = baseID; + break; + case x86::DBG: + c = x86_regclass_dr; + n = baseID; + break; + case x86::TST: c = x86_regclass_unknown; break; + case 0: + switch(baseID) { + case 0x10: + c = x86_regclass_ip; + n = 0; + break; + default: c = x86_regclass_unknown; break; + } + break; + default: + common_parsing_printf("Unknown category '%d' for Arch_x86\n", category); + break; + } + break; + case Arch_x86_64: + switch(category) { + case x86_64::GPR: + c = x86_regclass_gpr; + switch(baseID) { + case x86_64::BASEA: n = x86_gpr_ax; break; + case x86_64::BASEC: n = x86_gpr_cx; break; + case x86_64::BASED: n = x86_gpr_dx; break; + case x86_64::BASEB: n = x86_gpr_bx; break; + case x86_64::BASESP: n = x86_gpr_sp; break; + case x86_64::BASEBP: n = x86_gpr_bp; break; + case x86_64::BASESI: n = x86_gpr_si; break; + case x86_64::BASEDI: n = x86_gpr_di; break; + case x86_64::BASE8: n = x86_gpr_r8; break; + case x86_64::BASE9: n = x86_gpr_r9; break; + case x86_64::BASE10: n = x86_gpr_r10; break; + case x86_64::BASE11: n = x86_gpr_r11; break; + case x86_64::BASE12: n = x86_gpr_r12; break; + case x86_64::BASE13: n = x86_gpr_r13; break; + case x86_64::BASE14: n = x86_gpr_r14; break; + case x86_64::BASE15: n = x86_gpr_r15; break; + default: n = 0; break; + } + break; + case x86_64::SEG: + c = x86_regclass_segment; + switch(baseID) { + case x86_64::BASEDS: n = x86_segreg_ds; break; + case x86_64::BASEES: n = x86_segreg_es; break; + case x86_64::BASEFS: n = x86_segreg_fs; break; + case x86_64::BASEGS: n = x86_segreg_gs; break; + case x86_64::BASECS: n = x86_segreg_cs; break; + case x86_64::BASESS: n = x86_segreg_ss; break; + default: n = 0; break; + } + break; + case x86_64::FLAG: + c = x86_regclass_flags; + switch(baseID) { + case x86_64::CF: n = x86_flag_cf; break; + case x86_64::FLAG1: n = x86_flag_1; break; + case x86_64::PF: n = x86_flag_pf; break; + case x86_64::FLAG3: n = x86_flag_3; break; + case x86_64::AF: n = x86_flag_af; break; + case x86_64::FLAG5: n = x86_flag_5; break; + case x86_64::ZF: n = x86_flag_zf; break; + case x86_64::SF: n = x86_flag_sf; break; + case x86_64::TF: n = x86_flag_tf; break; + case x86_64::IF: n = x86_flag_if; break; + case x86_64::DF: n = x86_flag_df; break; + case x86_64::OF: n = x86_flag_of; break; + case x86_64::FLAGC: n = x86_flag_iopl0; break; + case x86_64::FLAGD: n = x86_flag_iopl1; break; + case x86_64::NT: n = x86_flag_nt; break; + case x86_64::FLAGF: n = x86_flag_15; break; + case x86_64::VM: n = x86_flag_vm; break; + case x86_64::RF: n = x86_flag_rf; break; + case x86_64::AC: n = x86_flag_ac; break; + case x86_64::VIF: n = x86_flag_vif; break; + case x86_64::VIP: n = x86_flag_vip; break; + case x86_64::ID: n = x86_flag_id; break; + default: + c = -1; + return; + break; + } + break; + case x86_64::MISC: c = x86_regclass_unknown; break; + case x86_64::KMASK: + c = x86_regclass_kmask; + n = baseID; + break; + case x86_64::ZMM: + c = x86_regclass_zmm; + n = baseID; + break; + case x86_64::YMM: + c = x86_regclass_ymm; + n = baseID; + break; + case x86_64::XMM: + c = x86_regclass_xmm; + n = baseID; + break; + case x86_64::MMX: + c = x86_regclass_mm; + n = baseID; + break; + case x86_64::X87: + c = x86_regclass_st_top; + n = baseID; + break; + case x86_64::CTL: + c = x86_regclass_cr; + n = baseID; + break; + case x86_64::DBG: + c = x86_regclass_dr; + n = baseID; + break; + case x86_64::TST: c = x86_regclass_unknown; break; + case 0: + switch(baseID) { + case 0x10: + c = x86_regclass_ip; + n = 0; + break; + default: c = x86_regclass_unknown; break; + } + break; + default: + common_parsing_printf("Unknown category '%d' for Arch_x86_64\n", category); + break; + } + break; + case Arch_ppc32: { + baseID = reg & 0x0000FFFF; + n = baseID; + switch(category) { + case ppc32::GPR: c = powerpc_regclass_gpr; break; + case ppc32::FPR: + case ppc32::FSR: c = powerpc_regclass_fpr; break; + case ppc32::SPR: { + if(baseID < 613) { + c = powerpc_regclass_spr; + } else if(baseID < 621) { + c = powerpc_regclass_sr; + } else { + c = powerpc_regclass_cr; + n = 0; + p = baseID - 621; + } + } break; + default: c = -1; return; + } + return; + } break; + case Arch_ppc64: { + baseID = reg & 0x0000FFFF; + n = baseID; + switch(category) { + case ppc64::GPR: c = powerpc_regclass_gpr; break; + case ppc64::FPR: + case ppc64::FSR: c = powerpc_regclass_fpr; break; + case ppc64::SPR: { + if(baseID < 613) { + c = powerpc_regclass_spr; + } else if(baseID < 621) { + c = powerpc_regclass_sr; + } else { + c = powerpc_regclass_cr; + n = 0; + p = baseID - 621; + } + } break; + default: c = -1; return; + } + return; + } break; + case Arch_aarch64: { + p = 0; + switch(category) { + case aarch64::GPR: { + c = armv8_regclass_gpr; + int regnum = baseID - (aarch64::x0 & 0xFF); + n = armv8_gpr_r0 + regnum; + } break; + case aarch64::SPR: { + n = 0; + if(baseID == (aarch64::pstate & 0xFF)) { + c = armv8_regclass_pstate; + } else if(baseID == (aarch64::xzr & 0xFF) || baseID == (aarch64::wzr & 0xFF)) { + c = armv8_regclass_gpr; + n = armv8_gpr_zr; + } else if(baseID == (aarch64::pc & 0xFF)) { + c = armv8_regclass_pc; + } else if(baseID == (aarch64::sp & 0xFF) || baseID == (aarch64::wsp & 0xFF)) { + c = armv8_regclass_sp; + } + } break; + case aarch64::FPR: { + c = armv8_regclass_simd_fpr; + + int firstRegId; + switch(reg & 0xFF00) { + case aarch64::Q_REG: firstRegId = (aarch64::q0 & 0xFF); break; + case aarch64::HQ_REG: + firstRegId = (aarch64::hq0 & 0xFF); + p = 64; + break; + case aarch64::FULL: firstRegId = (aarch64::d0 & 0xFF); break; + case aarch64::D_REG: firstRegId = (aarch64::s0 & 0xFF); break; + case aarch64::W_REG: firstRegId = (aarch64::h0 & 0xFF); break; + case aarch64::B_REG: firstRegId = (aarch64::b0 & 0xFF); break; + default: assert(!"invalid register subcategory for ARM64!"); break; + } + n = armv8_simdfpr_v0 + (baseID - firstRegId); + } break; + case aarch64::FLAG: { + c = armv8_regclass_pstate; + n = 0; + switch(baseID) { + case aarch64::N_FLAG: p = armv8_pstatefield_n; break; + case aarch64::Z_FLAG: p = armv8_pstatefield_z; break; + case aarch64::V_FLAG: p = armv8_pstatefield_v; break; + case aarch64::C_FLAG: p = armv8_pstatefield_c; break; + default: c = -1; return; + } + } break; + default: + // We do not want to assert here. + // Set these output variable to invalid values and let the + // semantics code to throw exceptions + p = -1; + c = -1; + n = -1; + break; + } + return; + } break; + default: + c = x86_regclass_unknown; + n = 0; + break; + } + + switch(getArchitecture()) { + case Arch_x86: + switch(subrange) { + case x86::XMMS: + case x86::YMMS: + case x86::ZMMS: + case x86::KMSKS: + case x86::FPDBL: p = x86_regpos_qword; break; + case x86::MMS: p = x86_regpos_qword; break; + case x86::H_REG: p = x86_regpos_high_byte; break; + case x86::L_REG: p = x86_regpos_low_byte; break; + case x86::W_REG: p = x86_regpos_word; break; + case x86::FULL: + case x86::BIT: p = x86_regpos_all; break; + default: + common_parsing_printf("Unknown subrange value '%d' for Arch_x86\n", subrange); + break; + } + break; + + case Arch_x86_64: + switch(subrange) { + case x86_64::FULL: + case x86_64::XMMS: + case x86_64::MMS: + case x86_64::KMSKS: + case x86_64::YMMS: + case x86_64::ZMMS: + case x86_64::FPDBL: p = x86_regpos_qword; break; + case x86_64::H_REG: p = x86_regpos_high_byte; break; + case x86_64::L_REG: p = x86_regpos_low_byte; break; + case x86_64::W_REG: p = x86_regpos_word; break; + case x86_64::D_REG: p = x86_regpos_dword; break; + case x86_64::BIT: p = x86_regpos_all; break; + default: + common_parsing_printf("Unknown subrange value '%d' for Arch_x86_64\n", subrange); + break; + } + break; + case Arch_aarch64: { + c = -1; + return; + } + default: p = x86_regpos_unknown; + } + } + + /* + * DWARF Encodings + * + * x86: + * System V Application Binary Interface + * Intel386 Architecture Processor Supplement + * Version 1.0 February 3, 2015 + * Table 2.14: DWARF Register Number Mapping + * https://gitlab.com/x86-psABIs/i386-ABI + * + * x86_64: + * System V Application Binary Interface + * AMD64 Architecture Processor Supplement + * Version 1.0 June 21, 2022 + * Table 3.36: DWARF Register Number Mapping + * https://gitlab.com/x86-psABIs/x86-64-ABI + */ + MachRegister MachRegister::DwarfEncToReg(int encoding, Dyninst::Architecture arch) { + switch(arch) { + case Arch_x86: + switch(encoding) { + case 0: return Dyninst::x86::eax; + case 1: return Dyninst::x86::ecx; + case 2: return Dyninst::x86::edx; + case 3: return Dyninst::x86::ebx; + case 4: return Dyninst::x86::esp; + case 5: return Dyninst::x86::ebp; + case 6: return Dyninst::x86::esi; + case 7: return Dyninst::x86::edi; + case 8: return Dyninst::x86::eip; + case 9: return Dyninst::x86::flags; + case 10: return Dyninst::InvalidReg; + case 11: return Dyninst::x86::st0; + case 12: return Dyninst::x86::st1; + case 13: return Dyninst::x86::st2; + case 14: return Dyninst::x86::st3; + case 15: return Dyninst::x86::st4; + case 16: return Dyninst::x86::st5; + case 17: return Dyninst::x86::st6; + case 18: return Dyninst::x86::st7; + case 19: return Dyninst::InvalidReg; + case 20: return Dyninst::InvalidReg; + case 21: return Dyninst::x86::xmm0; + case 22: return Dyninst::x86::xmm1; + case 23: return Dyninst::x86::xmm2; + case 24: return Dyninst::x86::xmm3; + case 25: return Dyninst::x86::xmm4; + case 26: return Dyninst::x86::xmm5; + case 27: return Dyninst::x86::xmm6; + case 28: return Dyninst::x86::xmm7; + case 29: return Dyninst::x86::mm0; + case 30: return Dyninst::x86::mm1; + case 31: return Dyninst::x86::mm2; + case 32: return Dyninst::x86::mm3; + case 33: return Dyninst::x86::mm4; + case 34: return Dyninst::x86::mm5; + case 35: return Dyninst::x86::mm6; + case 36: return Dyninst::x86::mm7; + case 37: return Dyninst::InvalidReg; + case 38: return Dyninst::InvalidReg; + case 39: return Dyninst::x86::mxcsr; + case 40: return Dyninst::x86::es; + case 41: return Dyninst::x86::cs; + case 42: return Dyninst::x86::ss; + case 43: return Dyninst::x86::ds; + case 44: return Dyninst::x86::fs; + case 45: return Dyninst::x86::gs; + case 46: return Dyninst::InvalidReg; + case 47: return Dyninst::InvalidReg; + case 48: return Dyninst::x86::tr; + case 49: return Dyninst::x86::ldtr; + case 50: return Dyninst::InvalidReg; + case 51: return Dyninst::InvalidReg; + case 52: return Dyninst::InvalidReg; + case 53: return Dyninst::InvalidReg; + case 54: return Dyninst::InvalidReg; + case 55: return Dyninst::InvalidReg; + case 56: return Dyninst::InvalidReg; + case 57: return Dyninst::InvalidReg; + case 58: return Dyninst::InvalidReg; + case 59: return Dyninst::InvalidReg; + case 60: return Dyninst::InvalidReg; + case 61: return Dyninst::InvalidReg; + case 62: return Dyninst::InvalidReg; + case 63: return Dyninst::InvalidReg; + case 64: return Dyninst::InvalidReg; + case 65: return Dyninst::InvalidReg; + case 66: return Dyninst::InvalidReg; + case 67: return Dyninst::InvalidReg; + case 68: return Dyninst::InvalidReg; + case 69: return Dyninst::InvalidReg; + case 70: return Dyninst::InvalidReg; + case 71: return Dyninst::InvalidReg; + case 72: return Dyninst::InvalidReg; + case 73: return Dyninst::InvalidReg; + case 74: return Dyninst::InvalidReg; + case 75: return Dyninst::InvalidReg; + case 76: return Dyninst::InvalidReg; + case 77: return Dyninst::InvalidReg; + case 78: return Dyninst::InvalidReg; + case 79: return Dyninst::InvalidReg; + case 80: return Dyninst::InvalidReg; + case 81: return Dyninst::InvalidReg; + case 82: return Dyninst::InvalidReg; + case 83: return Dyninst::InvalidReg; + case 84: return Dyninst::InvalidReg; + case 85: return Dyninst::InvalidReg; + case 86: return Dyninst::InvalidReg; + case 87: return Dyninst::InvalidReg; + case 88: return Dyninst::InvalidReg; + case 89: return Dyninst::InvalidReg; + case 90: return Dyninst::InvalidReg; + case 91: return Dyninst::InvalidReg; + case 92: return Dyninst::InvalidReg; + + /* End of documented registers */ + /* The rest of these are assigned arbitrary values for internal Dyninst use. */ + case 1024: return Dyninst::x86::ax; + case 1025: return Dyninst::x86::ah; + case 1026: return Dyninst::x86::al; + case 1027: return Dyninst::x86::cx; + case 1028: return Dyninst::x86::ch; + case 1029: return Dyninst::x86::cl; + case 1030: return Dyninst::x86::dx; + case 1031: return Dyninst::x86::dh; + case 1032: return Dyninst::x86::dl; + case 1033: return Dyninst::x86::bx; + case 1034: return Dyninst::x86::bh; + case 1035: return Dyninst::x86::bl; + case 1036: return Dyninst::x86::sp; + case 1037: return Dyninst::x86::bp; + case 1038: return Dyninst::x86::si; + case 1039: return Dyninst::x86::di; + case 1040: return Dyninst::x86::gdtr; + case 1041: return Dyninst::x86::idtr; + case 1042: return Dyninst::x86::cf; + case 1043: return Dyninst::x86::flag1; + case 1044: return Dyninst::x86::pf; + case 1045: return Dyninst::x86::flag3; + case 1046: return Dyninst::x86::af; + case 1047: return Dyninst::x86::flag5; + case 1048: return Dyninst::x86::zf; + case 1049: return Dyninst::x86::sf; + case 1050: return Dyninst::x86::tf; + case 1051: return Dyninst::x86::if_; + case 1052: return Dyninst::x86::df; + case 1053: return Dyninst::x86::of; + case 1054: return Dyninst::x86::flagc; + case 1055: return Dyninst::x86::flagd; + case 1056: return Dyninst::x86::nt_; + case 1057: return Dyninst::x86::flagf; + case 1058: return Dyninst::x86::rf; + case 1059: return Dyninst::x86::vm; + case 1060: return Dyninst::x86::ac; + case 1061: return Dyninst::x86::vif; + case 1062: return Dyninst::x86::vip; + case 1063: return Dyninst::x86::id; + case 1064: return Dyninst::x86::cr0; + case 1065: return Dyninst::x86::cr1; + case 1066: return Dyninst::x86::cr2; + case 1067: return Dyninst::x86::cr3; + case 1068: return Dyninst::x86::cr4; + case 1069: return Dyninst::x86::cr5; + case 1070: return Dyninst::x86::cr6; + case 1071: return Dyninst::x86::cr7; + case 1072: return Dyninst::x86::dr0; + case 1073: return Dyninst::x86::dr1; + case 1074: return Dyninst::x86::dr2; + case 1075: return Dyninst::x86::dr3; + case 1076: return Dyninst::x86::dr4; + case 1077: return Dyninst::x86::dr5; + case 1078: return Dyninst::x86::dr6; + case 1079: return Dyninst::x86::dr7; + case 1080: return Dyninst::x86::fcw; + case 1081: return Dyninst::x86::fsw; + case 1082: return Dyninst::x86::ymm0; + case 1083: return Dyninst::x86::ymm1; + case 1084: return Dyninst::x86::ymm2; + case 1085: return Dyninst::x86::ymm3; + case 1086: return Dyninst::x86::ymm4; + case 1087: return Dyninst::x86::ymm5; + case 1088: return Dyninst::x86::ymm6; + case 1089: return Dyninst::x86::ymm7; + case 1090: return Dyninst::x86::zmm0; + case 1091: return Dyninst::x86::zmm1; + case 1092: return Dyninst::x86::zmm2; + case 1093: return Dyninst::x86::zmm3; + case 1094: return Dyninst::x86::zmm4; + case 1095: return Dyninst::x86::zmm5; + case 1096: return Dyninst::x86::zmm6; + case 1097: return Dyninst::x86::zmm7; + case 1098: return Dyninst::x86::k0; + case 1099: return Dyninst::x86::k1; + case 1100: return Dyninst::x86::k2; + case 1101: return Dyninst::x86::k3; + case 1102: return Dyninst::x86::k4; + case 1103: return Dyninst::x86::k5; + case 1104: return Dyninst::x86::k6; + case 1105: return Dyninst::x86::k7; + case 1106: return Dyninst::x86::oeax; + case 1107: return Dyninst::x86::fsbase; + case 1108: return Dyninst::x86::gsbase; + case 1109: return Dyninst::x86::tr0; + case 1110: return Dyninst::x86::tr1; + case 1111: return Dyninst::x86::tr2; + case 1112: return Dyninst::x86::tr3; + case 1113: return Dyninst::x86::tr4; + case 1114: return Dyninst::x86::tr5; + case 1115: return Dyninst::x86::tr6; + case 1116: return Dyninst::x86::tr7; + default: return Dyninst::InvalidReg; + } + break; + case Arch_x86_64: + switch(encoding) { + case 0: return Dyninst::x86_64::rax; + case 1: return Dyninst::x86_64::rdx; + case 2: return Dyninst::x86_64::rcx; + case 3: return Dyninst::x86_64::rbx; + case 4: return Dyninst::x86_64::rsi; + case 5: return Dyninst::x86_64::rdi; + case 6: return Dyninst::x86_64::rbp; + case 7: return Dyninst::x86_64::rsp; + case 8: return Dyninst::x86_64::r8; + case 9: return Dyninst::x86_64::r9; + case 10: return Dyninst::x86_64::r10; + case 11: return Dyninst::x86_64::r11; + case 12: return Dyninst::x86_64::r12; + case 13: return Dyninst::x86_64::r13; + case 14: return Dyninst::x86_64::r14; + case 15: return Dyninst::x86_64::r15; + case 16: return Dyninst::x86_64::rip; + case 17: return Dyninst::x86_64::xmm0; + case 18: return Dyninst::x86_64::xmm1; + case 19: return Dyninst::x86_64::xmm2; + case 20: return Dyninst::x86_64::xmm3; + case 21: return Dyninst::x86_64::xmm4; + case 22: return Dyninst::x86_64::xmm5; + case 23: return Dyninst::x86_64::xmm6; + case 24: return Dyninst::x86_64::xmm7; + case 25: return Dyninst::x86_64::xmm8; + case 26: return Dyninst::x86_64::xmm9; + case 27: return Dyninst::x86_64::xmm10; + case 28: return Dyninst::x86_64::xmm11; + case 29: return Dyninst::x86_64::xmm12; + case 30: return Dyninst::x86_64::xmm13; + case 31: return Dyninst::x86_64::xmm14; + case 32: return Dyninst::x86_64::xmm15; + case 33: return Dyninst::x86_64::st0; + case 34: return Dyninst::x86_64::st1; + case 35: return Dyninst::x86_64::st2; + case 36: return Dyninst::x86_64::st3; + case 37: return Dyninst::x86_64::st4; + case 38: return Dyninst::x86_64::st5; + case 39: return Dyninst::x86_64::st6; + case 40: return Dyninst::x86_64::st7; + case 41: return Dyninst::x86_64::mm0; + case 42: return Dyninst::x86_64::mm1; + case 43: return Dyninst::x86_64::mm2; + case 44: return Dyninst::x86_64::mm3; + case 45: return Dyninst::x86_64::mm4; + case 46: return Dyninst::x86_64::mm5; + case 47: return Dyninst::x86_64::mm6; + case 48: return Dyninst::x86_64::mm7; + case 49: return Dyninst::x86_64::flags; + case 50: return Dyninst::x86_64::es; + case 51: return Dyninst::x86_64::cs; + case 52: return Dyninst::x86_64::ss; + case 53: return Dyninst::x86_64::ds; + case 54: return Dyninst::x86_64::fs; + case 55: return Dyninst::x86_64::gs; + case 56: return Dyninst::InvalidReg; + case 57: return Dyninst::InvalidReg; + case 58: return Dyninst::x86_64::fsbase; + case 59: return Dyninst::x86_64::gsbase; + case 60: return Dyninst::InvalidReg; + case 61: return Dyninst::InvalidReg; + case 62: return Dyninst::x86_64::tr; + case 63: return Dyninst::x86_64::ldtr; + case 64: return Dyninst::x86_64::mxcsr; + case 65: return Dyninst::x86_64::fcw; + case 66: return Dyninst::x86_64::fsw; + case 67: return Dyninst::x86_64::xmm16; + case 68: return Dyninst::x86_64::xmm17; + case 69: return Dyninst::x86_64::xmm18; + case 70: return Dyninst::x86_64::xmm19; + case 71: return Dyninst::x86_64::xmm20; + case 72: return Dyninst::x86_64::xmm21; + case 73: return Dyninst::x86_64::xmm22; + case 74: return Dyninst::x86_64::xmm23; + case 75: return Dyninst::x86_64::xmm24; + case 76: return Dyninst::x86_64::xmm25; + case 77: return Dyninst::x86_64::xmm26; + case 78: return Dyninst::x86_64::xmm27; + case 79: return Dyninst::x86_64::xmm28; + case 80: return Dyninst::x86_64::xmm29; + case 81: return Dyninst::x86_64::xmm30; + case 82: return Dyninst::x86_64::xmm31; + case 83: return Dyninst::InvalidReg; + case 84: return Dyninst::InvalidReg; + case 85: return Dyninst::InvalidReg; + case 86: return Dyninst::InvalidReg; + case 87: return Dyninst::InvalidReg; + case 88: return Dyninst::InvalidReg; + case 89: return Dyninst::InvalidReg; + case 90: return Dyninst::InvalidReg; + case 91: return Dyninst::InvalidReg; + case 92: return Dyninst::InvalidReg; + case 93: return Dyninst::InvalidReg; + case 94: return Dyninst::InvalidReg; + case 95: return Dyninst::InvalidReg; + case 96: return Dyninst::InvalidReg; + case 97: return Dyninst::InvalidReg; + case 98: return Dyninst::InvalidReg; + case 99: return Dyninst::InvalidReg; + case 100: return Dyninst::InvalidReg; + case 101: return Dyninst::InvalidReg; + case 102: return Dyninst::InvalidReg; + case 103: return Dyninst::InvalidReg; + case 104: return Dyninst::InvalidReg; + case 105: return Dyninst::InvalidReg; + case 106: return Dyninst::InvalidReg; + case 107: return Dyninst::InvalidReg; + case 108: return Dyninst::InvalidReg; + case 109: return Dyninst::InvalidReg; + case 110: return Dyninst::InvalidReg; + case 111: return Dyninst::InvalidReg; + case 112: return Dyninst::InvalidReg; + case 113: return Dyninst::InvalidReg; + case 114: return Dyninst::InvalidReg; + case 115: return Dyninst::InvalidReg; + case 116: return Dyninst::InvalidReg; + case 117: return Dyninst::InvalidReg; + case 118: return Dyninst::x86_64::k0; + case 119: return Dyninst::x86_64::k1; + case 120: return Dyninst::x86_64::k2; + case 121: return Dyninst::x86_64::k3; + case 122: return Dyninst::x86_64::k4; + case 123: return Dyninst::x86_64::k5; + case 124: return Dyninst::x86_64::k6; + case 125: return Dyninst::x86_64::k7; + case 126: return Dyninst::InvalidReg; + case 127: return Dyninst::InvalidReg; + case 128: return Dyninst::InvalidReg; + case 129: return Dyninst::InvalidReg; + + /* End of documented registers */ + /* The rest of these are assigned arbitrary values for internal Dyninst use. */ + case 1024: return Dyninst::x86_64::eax; + case 1025: return Dyninst::x86_64::ax; + case 1026: return Dyninst::x86_64::ah; + case 1027: return Dyninst::x86_64::al; + case 1028: return Dyninst::x86_64::ecx; + case 1029: return Dyninst::x86_64::cx; + case 1030: return Dyninst::x86_64::ch; + case 1031: return Dyninst::x86_64::cl; + case 1032: return Dyninst::x86_64::edx; + case 1033: return Dyninst::x86_64::dx; + case 1034: return Dyninst::x86_64::dh; + case 1035: return Dyninst::x86_64::dl; + case 1036: return Dyninst::x86_64::ebx; + case 1037: return Dyninst::x86_64::bx; + case 1038: return Dyninst::x86_64::bh; + case 1039: return Dyninst::x86_64::bl; + case 1040: return Dyninst::x86_64::esp; + case 1041: return Dyninst::x86_64::sp; + case 1042: return Dyninst::x86_64::spl; + case 1043: return Dyninst::x86_64::ebp; + case 1044: return Dyninst::x86_64::bp; + case 1045: return Dyninst::x86_64::bpl; + case 1046: return Dyninst::x86_64::esi; + case 1047: return Dyninst::x86_64::si; + case 1048: return Dyninst::x86_64::sil; + case 1049: return Dyninst::x86_64::edi; + case 1050: return Dyninst::x86_64::di; + case 1051: return Dyninst::x86_64::dil; + case 1052: return Dyninst::x86_64::r8b; + case 1053: return Dyninst::x86_64::r8w; + case 1054: return Dyninst::x86_64::r8d; + case 1055: return Dyninst::x86_64::r9b; + case 1056: return Dyninst::x86_64::r9w; + case 1057: return Dyninst::x86_64::r9d; + case 1058: return Dyninst::x86_64::r10b; + case 1059: return Dyninst::x86_64::r10w; + case 1060: return Dyninst::x86_64::r10d; + case 1061: return Dyninst::x86_64::r11b; + case 1062: return Dyninst::x86_64::r11w; + case 1063: return Dyninst::x86_64::r11d; + case 1064: return Dyninst::x86_64::r12b; + case 1065: return Dyninst::x86_64::r12w; + case 1066: return Dyninst::x86_64::r12d; + case 1067: return Dyninst::x86_64::r13b; + case 1068: return Dyninst::x86_64::r13w; + case 1069: return Dyninst::x86_64::r13d; + case 1070: return Dyninst::x86_64::r14b; + case 1071: return Dyninst::x86_64::r14w; + case 1072: return Dyninst::x86_64::r14d; + case 1073: return Dyninst::x86_64::r15b; + case 1074: return Dyninst::x86_64::r15w; + case 1075: return Dyninst::x86_64::r15d; + case 1076: return Dyninst::x86_64::eip; + case 1077: return Dyninst::x86_64::cf; + case 1078: return Dyninst::x86_64::flag1; + case 1079: return Dyninst::x86_64::pf; + case 1080: return Dyninst::x86_64::flag3; + case 1081: return Dyninst::x86_64::af; + case 1082: return Dyninst::x86_64::flag5; + case 1083: return Dyninst::x86_64::zf; + case 1084: return Dyninst::x86_64::sf; + case 1085: return Dyninst::x86_64::tf; + case 1086: return Dyninst::x86_64::if_; + case 1087: return Dyninst::x86_64::df; + case 1088: return Dyninst::x86_64::of; + case 1089: return Dyninst::x86_64::flagc; + case 1090: return Dyninst::x86_64::flagd; + case 1091: return Dyninst::x86_64::nt_; + case 1092: return Dyninst::x86_64::flagf; + case 1093: return Dyninst::x86_64::rf; + case 1094: return Dyninst::x86_64::vm; + case 1095: return Dyninst::x86_64::ac; + case 1096: return Dyninst::x86_64::vif; + case 1097: return Dyninst::x86_64::vip; + case 1098: return Dyninst::x86_64::id; + case 1099: return Dyninst::x86_64::gdtr; + case 1100: return Dyninst::x86_64::idtr; + case 1101: return Dyninst::x86_64::cr0; + case 1102: return Dyninst::x86_64::cr1; + case 1103: return Dyninst::x86_64::cr2; + case 1104: return Dyninst::x86_64::cr3; + case 1105: return Dyninst::x86_64::cr4; + case 1106: return Dyninst::x86_64::cr5; + case 1107: return Dyninst::x86_64::cr6; + case 1108: return Dyninst::x86_64::cr7; + case 1109: return Dyninst::x86_64::cr8; + case 1110: return Dyninst::x86_64::cr9; + case 1111: return Dyninst::x86_64::cr10; + case 1112: return Dyninst::x86_64::cr11; + case 1113: return Dyninst::x86_64::cr12; + case 1114: return Dyninst::x86_64::cr13; + case 1115: return Dyninst::x86_64::cr14; + case 1116: return Dyninst::x86_64::cr15; + case 1117: return Dyninst::x86_64::dr0; + case 1118: return Dyninst::x86_64::dr1; + case 1119: return Dyninst::x86_64::dr2; + case 1120: return Dyninst::x86_64::dr3; + case 1121: return Dyninst::x86_64::dr4; + case 1122: return Dyninst::x86_64::dr5; + case 1123: return Dyninst::x86_64::dr6; + case 1124: return Dyninst::x86_64::dr7; + case 1125: return Dyninst::x86_64::dr8; + case 1126: return Dyninst::x86_64::dr9; + case 1127: return Dyninst::x86_64::dr10; + case 1128: return Dyninst::x86_64::dr11; + case 1129: return Dyninst::x86_64::dr12; + case 1130: return Dyninst::x86_64::dr13; + case 1131: return Dyninst::x86_64::dr14; + case 1132: return Dyninst::x86_64::dr15; + case 1133: return Dyninst::x86_64::ymm0; + case 1134: return Dyninst::x86_64::ymm1; + case 1135: return Dyninst::x86_64::ymm2; + case 1136: return Dyninst::x86_64::ymm3; + case 1137: return Dyninst::x86_64::ymm4; + case 1138: return Dyninst::x86_64::ymm5; + case 1139: return Dyninst::x86_64::ymm6; + case 1140: return Dyninst::x86_64::ymm7; + case 1141: return Dyninst::x86_64::ymm8; + case 1142: return Dyninst::x86_64::ymm9; + case 1143: return Dyninst::x86_64::ymm10; + case 1144: return Dyninst::x86_64::ymm11; + case 1145: return Dyninst::x86_64::ymm12; + case 1146: return Dyninst::x86_64::ymm13; + case 1147: return Dyninst::x86_64::ymm14; + case 1148: return Dyninst::x86_64::ymm15; + case 1149: return Dyninst::x86_64::ymm16; + case 1150: return Dyninst::x86_64::ymm17; + case 1151: return Dyninst::x86_64::ymm18; + case 1152: return Dyninst::x86_64::ymm19; + case 1153: return Dyninst::x86_64::ymm20; + case 1154: return Dyninst::x86_64::ymm21; + case 1155: return Dyninst::x86_64::ymm22; + case 1156: return Dyninst::x86_64::ymm23; + case 1157: return Dyninst::x86_64::ymm24; + case 1158: return Dyninst::x86_64::ymm25; + case 1159: return Dyninst::x86_64::ymm26; + case 1160: return Dyninst::x86_64::ymm27; + case 1161: return Dyninst::x86_64::ymm28; + case 1162: return Dyninst::x86_64::ymm29; + case 1163: return Dyninst::x86_64::ymm30; + case 1164: return Dyninst::x86_64::ymm31; + case 1165: return Dyninst::x86_64::zmm0; + case 1166: return Dyninst::x86_64::zmm1; + case 1167: return Dyninst::x86_64::zmm2; + case 1168: return Dyninst::x86_64::zmm3; + case 1169: return Dyninst::x86_64::zmm4; + case 1170: return Dyninst::x86_64::zmm5; + case 1171: return Dyninst::x86_64::zmm6; + case 1172: return Dyninst::x86_64::zmm7; + case 1173: return Dyninst::x86_64::zmm8; + case 1174: return Dyninst::x86_64::zmm9; + case 1175: return Dyninst::x86_64::zmm10; + case 1176: return Dyninst::x86_64::zmm11; + case 1177: return Dyninst::x86_64::zmm12; + case 1178: return Dyninst::x86_64::zmm13; + case 1179: return Dyninst::x86_64::zmm14; + case 1180: return Dyninst::x86_64::zmm15; + case 1181: return Dyninst::x86_64::zmm16; + case 1182: return Dyninst::x86_64::zmm17; + case 1183: return Dyninst::x86_64::zmm18; + case 1184: return Dyninst::x86_64::zmm19; + case 1185: return Dyninst::x86_64::zmm20; + case 1186: return Dyninst::x86_64::zmm21; + case 1187: return Dyninst::x86_64::zmm22; + case 1188: return Dyninst::x86_64::zmm23; + case 1189: return Dyninst::x86_64::zmm24; + case 1190: return Dyninst::x86_64::zmm25; + case 1191: return Dyninst::x86_64::zmm26; + case 1192: return Dyninst::x86_64::zmm27; + case 1193: return Dyninst::x86_64::zmm28; + case 1194: return Dyninst::x86_64::zmm29; + case 1195: return Dyninst::x86_64::zmm30; + case 1196: return Dyninst::x86_64::zmm31; + case 1197: return Dyninst::x86_64::orax; + case 1198: return Dyninst::x86_64::tr0; + case 1199: return Dyninst::x86_64::tr1; + case 1200: return Dyninst::x86_64::tr2; + case 1201: return Dyninst::x86_64::tr3; + case 1202: return Dyninst::x86_64::tr4; + case 1203: return Dyninst::x86_64::tr5; + case 1204: return Dyninst::x86_64::tr6; + case 1205: return Dyninst::x86_64::tr7; + default: return Dyninst::InvalidReg; + } + break; + case Arch_ppc32: + switch(encoding) { + case 0: return Dyninst::ppc32::r0; + case 1: return Dyninst::ppc32::r1; + case 2: return Dyninst::ppc32::r2; + case 3: return Dyninst::ppc32::r3; + case 4: return Dyninst::ppc32::r4; + case 5: return Dyninst::ppc32::r5; + case 6: return Dyninst::ppc32::r6; + case 7: return Dyninst::ppc32::r7; + case 8: return Dyninst::ppc32::r8; + case 9: return Dyninst::ppc32::r9; + case 10: return Dyninst::ppc32::r10; + case 11: return Dyninst::ppc32::r11; + case 12: return Dyninst::ppc32::r12; + case 13: return Dyninst::ppc32::r13; + case 14: return Dyninst::ppc32::r14; + case 15: return Dyninst::ppc32::r15; + case 16: return Dyninst::ppc32::r16; + case 17: return Dyninst::ppc32::r17; + case 18: return Dyninst::ppc32::r18; + case 19: return Dyninst::ppc32::r19; + case 20: return Dyninst::ppc32::r20; + case 21: return Dyninst::ppc32::r21; + case 22: return Dyninst::ppc32::r22; + case 23: return Dyninst::ppc32::r23; + case 24: return Dyninst::ppc32::r24; + case 25: return Dyninst::ppc32::r25; + case 26: return Dyninst::ppc32::r26; + case 27: return Dyninst::ppc32::r27; + case 28: return Dyninst::ppc32::r28; + case 29: return Dyninst::ppc32::r29; + case 30: return Dyninst::ppc32::r30; + case 31: return Dyninst::ppc32::r31; + case 32: return Dyninst::ppc32::fpr0; + case 33: return Dyninst::ppc32::fpr1; + case 34: return Dyninst::ppc32::fpr2; + case 35: return Dyninst::ppc32::fpr3; + case 36: return Dyninst::ppc32::fpr4; + case 37: return Dyninst::ppc32::fpr5; + case 38: return Dyninst::ppc32::fpr6; + case 39: return Dyninst::ppc32::fpr7; + case 40: return Dyninst::ppc32::fpr8; + case 41: return Dyninst::ppc32::fpr9; + case 42: return Dyninst::ppc32::fpr10; + case 43: return Dyninst::ppc32::fpr11; + case 44: return Dyninst::ppc32::fpr12; + case 45: return Dyninst::ppc32::fpr13; + case 46: return Dyninst::ppc32::fpr14; + case 47: return Dyninst::ppc32::fpr15; + case 48: return Dyninst::ppc32::fpr16; + case 49: return Dyninst::ppc32::fpr17; + case 50: return Dyninst::ppc32::fpr18; + case 51: return Dyninst::ppc32::fpr19; + case 52: return Dyninst::ppc32::fpr20; + case 53: return Dyninst::ppc32::fpr21; + case 54: return Dyninst::ppc32::fpr22; + case 55: return Dyninst::ppc32::fpr23; + case 56: return Dyninst::ppc32::fpr24; + case 57: return Dyninst::ppc32::fpr25; + case 58: return Dyninst::ppc32::fpr26; + case 59: return Dyninst::ppc32::fpr27; + case 60: return Dyninst::ppc32::fpr28; + case 61: return Dyninst::ppc32::fpr29; + case 62: return Dyninst::ppc32::fpr30; + case 63: return Dyninst::ppc32::fpr31; + case 64: return Dyninst::ppc32::cr; + case 65: return Dyninst::InvalidReg; // FPSCR + default: return Dyninst::InvalidReg; + } + // Seperate switch statements to give compilers an easier time of + // optimizing + switch(encoding) { + case 100: return Dyninst::ppc32::mq; + case 101: return Dyninst::ppc32::xer; + case 102: return Dyninst::InvalidReg; + case 103: return Dyninst::InvalidReg; + case 104: return Dyninst::InvalidReg; // RTCU + case 105: return Dyninst::InvalidReg; // RTCL + case 106: return Dyninst::InvalidReg; + case 107: return Dyninst::InvalidReg; + case 108: return Dyninst::ppc32::lr; + case 109: return Dyninst::ppc32::ctr; + default: return Dyninst::InvalidReg; + } + break; + case Arch_ppc64: + switch(encoding) { + case 0: return Dyninst::ppc64::r0; + case 1: return Dyninst::ppc64::r1; + case 2: return Dyninst::ppc64::r2; + case 3: return Dyninst::ppc64::r3; + case 4: return Dyninst::ppc64::r4; + case 5: return Dyninst::ppc64::r5; + case 6: return Dyninst::ppc64::r6; + case 7: return Dyninst::ppc64::r7; + case 8: return Dyninst::ppc64::r8; + case 9: return Dyninst::ppc64::r9; + case 10: return Dyninst::ppc64::r10; + case 11: return Dyninst::ppc64::r11; + case 12: return Dyninst::ppc64::r12; + case 13: return Dyninst::ppc64::r13; + case 14: return Dyninst::ppc64::r14; + case 15: return Dyninst::ppc64::r15; + case 16: return Dyninst::ppc64::r16; + case 17: return Dyninst::ppc64::r17; + case 18: return Dyninst::ppc64::r18; + case 19: return Dyninst::ppc64::r19; + case 20: return Dyninst::ppc64::r20; + case 21: return Dyninst::ppc64::r21; + case 22: return Dyninst::ppc64::r22; + case 23: return Dyninst::ppc64::r23; + case 24: return Dyninst::ppc64::r24; + case 25: return Dyninst::ppc64::r25; + case 26: return Dyninst::ppc64::r26; + case 27: return Dyninst::ppc64::r27; + case 28: return Dyninst::ppc64::r28; + case 29: return Dyninst::ppc64::r29; + case 30: return Dyninst::ppc64::r30; + case 31: return Dyninst::ppc64::r31; + case 32: return Dyninst::ppc64::fpr0; + case 33: return Dyninst::ppc64::fpr1; + case 34: return Dyninst::ppc64::fpr2; + case 35: return Dyninst::ppc64::fpr3; + case 36: return Dyninst::ppc64::fpr4; + case 37: return Dyninst::ppc64::fpr5; + case 38: return Dyninst::ppc64::fpr6; + case 39: return Dyninst::ppc64::fpr7; + case 40: return Dyninst::ppc64::fpr8; + case 41: return Dyninst::ppc64::fpr9; + case 42: return Dyninst::ppc64::fpr10; + case 43: return Dyninst::ppc64::fpr11; + case 44: return Dyninst::ppc64::fpr12; + case 45: return Dyninst::ppc64::fpr13; + case 46: return Dyninst::ppc64::fpr14; + case 47: return Dyninst::ppc64::fpr15; + case 48: return Dyninst::ppc64::fpr16; + case 49: return Dyninst::ppc64::fpr17; + case 50: return Dyninst::ppc64::fpr18; + case 51: return Dyninst::ppc64::fpr19; + case 52: return Dyninst::ppc64::fpr20; + case 53: return Dyninst::ppc64::fpr21; + case 54: return Dyninst::ppc64::fpr22; + case 55: return Dyninst::ppc64::fpr23; + case 56: return Dyninst::ppc64::fpr24; + case 57: return Dyninst::ppc64::fpr25; + case 58: return Dyninst::ppc64::fpr26; + case 59: return Dyninst::ppc64::fpr27; + case 60: return Dyninst::ppc64::fpr28; + case 61: return Dyninst::ppc64::fpr29; + case 62: return Dyninst::ppc64::fpr30; + case 63: return Dyninst::ppc64::fpr31; + case 64: return Dyninst::ppc64::cr; + case 65: return Dyninst::InvalidReg; // FPSCR + default: return Dyninst::InvalidReg; + } + // Seperate switch statements to give compilers an easier time of + // optimizing + switch(encoding) { + case 100: return Dyninst::ppc64::mq; + case 101: return Dyninst::ppc64::xer; + case 102: return Dyninst::InvalidReg; + case 103: return Dyninst::InvalidReg; + case 104: return Dyninst::InvalidReg; // RTCU + case 105: return Dyninst::InvalidReg; // RTCL + case 106: return Dyninst::InvalidReg; + case 107: return Dyninst::InvalidReg; + case 108: return Dyninst::ppc64::lr; + case 109: return Dyninst::ppc64::ctr; + default: return Dyninst::InvalidReg; + } + break; + case Arch_aarch64: { + // this info can be found in + // DWARF for the ARM ® 64-bit Architecture (AArch64) + switch(encoding) { + case 0: return Dyninst::aarch64::x0; + case 1: return Dyninst::aarch64::x1; + case 2: return Dyninst::aarch64::x2; + case 3: return Dyninst::aarch64::x3; + case 4: return Dyninst::aarch64::x4; + case 5: return Dyninst::aarch64::x5; + case 6: return Dyninst::aarch64::x6; + case 7: return Dyninst::aarch64::x7; + case 8: return Dyninst::aarch64::x8; + case 9: return Dyninst::aarch64::x9; + case 10: return Dyninst::aarch64::x10; + case 11: return Dyninst::aarch64::x11; + case 12: return Dyninst::aarch64::x12; + case 13: return Dyninst::aarch64::x13; + case 14: return Dyninst::aarch64::x14; + case 15: return Dyninst::aarch64::x15; + case 16: return Dyninst::aarch64::x16; + case 17: return Dyninst::aarch64::x17; + case 18: return Dyninst::aarch64::x18; + case 19: return Dyninst::aarch64::x19; + case 20: return Dyninst::aarch64::x20; + case 21: return Dyninst::aarch64::x21; + case 22: return Dyninst::aarch64::x22; + case 23: return Dyninst::aarch64::x23; + case 24: return Dyninst::aarch64::x24; + case 25: return Dyninst::aarch64::x25; + case 26: return Dyninst::aarch64::x26; + case 27: return Dyninst::aarch64::x27; + case 28: return Dyninst::aarch64::x28; + case 29: return Dyninst::aarch64::x29; + case 30: return Dyninst::aarch64::x30; + case 31: return Dyninst::aarch64::sp; + case 32: return Dyninst::InvalidReg; + default: return Dyninst::InvalidReg; + } + switch(encoding) { + case 64: return Dyninst::aarch64::q0; + case 65: return Dyninst::aarch64::q1; + case 66: return Dyninst::aarch64::q2; + case 67: return Dyninst::aarch64::q3; + case 68: return Dyninst::aarch64::q4; + case 69: return Dyninst::aarch64::q5; + case 70: return Dyninst::aarch64::q6; + case 71: return Dyninst::aarch64::q7; + case 72: return Dyninst::aarch64::q8; + case 73: return Dyninst::aarch64::q9; + case 74: return Dyninst::aarch64::q10; + case 75: return Dyninst::aarch64::q11; + case 76: return Dyninst::aarch64::q12; + case 77: return Dyninst::aarch64::q13; + case 78: return Dyninst::aarch64::q14; + case 79: return Dyninst::aarch64::q15; + case 80: return Dyninst::aarch64::q16; + case 81: return Dyninst::aarch64::q17; + case 82: return Dyninst::aarch64::q18; + case 83: return Dyninst::aarch64::q19; + case 84: return Dyninst::aarch64::q20; + case 85: return Dyninst::aarch64::q21; + case 86: return Dyninst::aarch64::q22; + case 87: return Dyninst::aarch64::q23; + case 88: return Dyninst::aarch64::q24; + case 89: return Dyninst::aarch64::q25; + case 90: return Dyninst::aarch64::q26; + case 91: return Dyninst::aarch64::q27; + case 92: return Dyninst::aarch64::q28; + case 93: return Dyninst::aarch64::q29; + case 94: return Dyninst::aarch64::q30; + case 95: return Dyninst::aarch64::q31; + + default: return Dyninst::InvalidReg; break; + } + return Dyninst::InvalidReg; + } + case Arch_cuda: + // ignore CUDA register encodings for now + return Dyninst::InvalidReg; + break; + case Arch_amdgpu_gfx908: + case Arch_amdgpu_gfx90a: + case Arch_amdgpu_gfx940: + // ignore AMD register encodings for now + return Dyninst::InvalidReg; + break; + case Arch_intelGen9: return Dyninst::InvalidReg; break; + case Arch_none: return Dyninst::InvalidReg; break; + default: assert(0); return InvalidReg; + } + // Invalid Architecture passed + return Dyninst::InvalidReg; + } + + int MachRegister::getDwarfEnc() const { + switch(getArchitecture()) { + case Arch_x86: + switch(val()) { + case Dyninst::x86::ieax: return 0; + case Dyninst::x86::iecx: return 1; + case Dyninst::x86::iedx: return 2; + case Dyninst::x86::iebx: return 3; + case Dyninst::x86::iesp: return 4; + case Dyninst::x86::iebp: return 5; + case Dyninst::x86::iesi: return 6; + case Dyninst::x86::iedi: return 7; + case Dyninst::x86::ieip: return 8; + case Dyninst::x86::iflags: return 9; + /*[10] Reserved */ + case Dyninst::x86::ist0: return 11; + case Dyninst::x86::ist1: return 12; + case Dyninst::x86::ist2: return 13; + case Dyninst::x86::ist3: return 14; + case Dyninst::x86::ist4: return 15; + case Dyninst::x86::ist5: return 16; + case Dyninst::x86::ist6: return 17; + case Dyninst::x86::ist7: return 18; + /*[19] Reserved */ + /*[20] Reserved */ + case Dyninst::x86::ixmm0: return 21; + case Dyninst::x86::ixmm1: return 22; + case Dyninst::x86::ixmm2: return 23; + case Dyninst::x86::ixmm3: return 24; + case Dyninst::x86::ixmm4: return 25; + case Dyninst::x86::ixmm5: return 26; + case Dyninst::x86::ixmm6: return 27; + case Dyninst::x86::ixmm7: return 28; + case Dyninst::x86::imm0: return 29; + case Dyninst::x86::imm1: return 30; + case Dyninst::x86::imm2: return 31; + case Dyninst::x86::imm3: return 32; + case Dyninst::x86::imm4: return 33; + case Dyninst::x86::imm5: return 34; + case Dyninst::x86::imm6: return 35; + case Dyninst::x86::imm7: return 36; + /*[37] Reserved */ + /*[38] Reserved */ + case Dyninst::x86::imxcsr: return 39; + case Dyninst::x86::ies: return 40; + case Dyninst::x86::ics: return 41; + case Dyninst::x86::iss: return 42; + case Dyninst::x86::ids: return 43; + case Dyninst::x86::ifs: return 44; + case Dyninst::x86::igs: return 45; + /*[46] Reserved */ + /*[47] Reserved */ + case Dyninst::x86::itr: return 48; + case Dyninst::x86::ildtr: return 49; + /*[50] Reserved */ + /*[51] Reserved */ + /*[52] Reserved */ + /*[53] Reserved */ + /*[54] Reserved */ + /*[55] Reserved */ + /*[56] Reserved */ + /*[57] Reserved */ + /*[58] Reserved */ + /*[59] Reserved */ + /*[60] Reserved */ + /*[61] Reserved */ + /*[62] Reserved */ + /*[63] Reserved */ + /*[64] Reserved */ + /*[65] Reserved */ + /*[66] Reserved */ + /*[67] Reserved */ + /*[68] Reserved */ + /*[69] Reserved */ + /*[70] Reserved */ + /*[71] Reserved */ + /*[72] Reserved */ + /*[73] Reserved */ + /*[74] Reserved */ + /*[75] Reserved */ + /*[76] Reserved */ + /*[77] Reserved */ + /*[78] Reserved */ + /*[79] Reserved */ + /*[80] Reserved */ + /*[81] Reserved */ + /*[82] Reserved */ + /*[83] Reserved */ + /*[84] Reserved */ + /*[85] Reserved */ + /*[86] Reserved */ + /*[87] Reserved */ + /*[88] Reserved */ + /*[89] Reserved */ + /*[90] Reserved */ + /*[91] Reserved */ + /*[92] Reserved */ + + /* End of documented registers */ + /* The rest of these are assigned arbitrary values for internal Dyninst use. */ + case Dyninst::x86::iax: return 1024; + case Dyninst::x86::iah: return 1025; + case Dyninst::x86::ial: return 1026; + case Dyninst::x86::icx: return 1027; + case Dyninst::x86::ich: return 1028; + case Dyninst::x86::icl: return 1029; + case Dyninst::x86::idx: return 1030; + case Dyninst::x86::idh: return 1031; + case Dyninst::x86::idl: return 1032; + case Dyninst::x86::ibx: return 1033; + case Dyninst::x86::ibh: return 1034; + case Dyninst::x86::ibl: return 1035; + case Dyninst::x86::isp: return 1036; + case Dyninst::x86::ibp: return 1037; + case Dyninst::x86::isi: return 1038; + case Dyninst::x86::idi: return 1039; + case Dyninst::x86::igdtr: return 1040; + case Dyninst::x86::iidtr: return 1041; + case Dyninst::x86::icf: return 1042; + case Dyninst::x86::iflag1: return 1043; + case Dyninst::x86::ipf: return 1044; + case Dyninst::x86::iflag3: return 1045; + case Dyninst::x86::iaf: return 1046; + case Dyninst::x86::iflag5: return 1047; + case Dyninst::x86::izf: return 1048; + case Dyninst::x86::isf: return 1049; + case Dyninst::x86::itf: return 1050; + case Dyninst::x86::iif_: return 1051; + case Dyninst::x86::idf: return 1052; + case Dyninst::x86::iof: return 1053; + case Dyninst::x86::iflagc: return 1054; + case Dyninst::x86::iflagd: return 1055; + case Dyninst::x86::int_: return 1056; + case Dyninst::x86::iflagf: return 1057; + case Dyninst::x86::irf: return 1058; + case Dyninst::x86::ivm: return 1059; + case Dyninst::x86::iac: return 1060; + case Dyninst::x86::ivif: return 1061; + case Dyninst::x86::ivip: return 1062; + case Dyninst::x86::iid: return 1063; + case Dyninst::x86::icr0: return 1064; + case Dyninst::x86::icr1: return 1065; + case Dyninst::x86::icr2: return 1066; + case Dyninst::x86::icr3: return 1067; + case Dyninst::x86::icr4: return 1068; + case Dyninst::x86::icr5: return 1069; + case Dyninst::x86::icr6: return 1070; + case Dyninst::x86::icr7: return 1071; + case Dyninst::x86::idr0: return 1072; + case Dyninst::x86::idr1: return 1073; + case Dyninst::x86::idr2: return 1074; + case Dyninst::x86::idr3: return 1075; + case Dyninst::x86::idr4: return 1076; + case Dyninst::x86::idr5: return 1077; + case Dyninst::x86::idr6: return 1078; + case Dyninst::x86::idr7: return 1079; + case Dyninst::x86::ifcw: return 1080; + case Dyninst::x86::ifsw: return 1081; + case Dyninst::x86::iymm0: return 1082; + case Dyninst::x86::iymm1: return 1083; + case Dyninst::x86::iymm2: return 1084; + case Dyninst::x86::iymm3: return 1085; + case Dyninst::x86::iymm4: return 1086; + case Dyninst::x86::iymm5: return 1087; + case Dyninst::x86::iymm6: return 1088; + case Dyninst::x86::iymm7: return 1089; + case Dyninst::x86::izmm0: return 1090; + case Dyninst::x86::izmm1: return 1091; + case Dyninst::x86::izmm2: return 1092; + case Dyninst::x86::izmm3: return 1093; + case Dyninst::x86::izmm4: return 1094; + case Dyninst::x86::izmm5: return 1095; + case Dyninst::x86::izmm6: return 1096; + case Dyninst::x86::izmm7: return 1097; + case Dyninst::x86::ik0: return 1098; + case Dyninst::x86::ik1: return 1099; + case Dyninst::x86::ik2: return 1100; + case Dyninst::x86::ik3: return 1101; + case Dyninst::x86::ik4: return 1102; + case Dyninst::x86::ik5: return 1103; + case Dyninst::x86::ik6: return 1104; + case Dyninst::x86::ik7: return 1105; + case Dyninst::x86::ioeax: return 1106; + case Dyninst::x86::ifsbase: return 1107; + case Dyninst::x86::igsbase: return 1108; + case Dyninst::x86::itr0: return 1109; + case Dyninst::x86::itr1: return 1110; + case Dyninst::x86::itr2: return 1111; + case Dyninst::x86::itr3: return 1112; + case Dyninst::x86::itr4: return 1113; + case Dyninst::x86::itr5: return 1114; + case Dyninst::x86::itr6: return 1115; + case Dyninst::x86::itr7: return 1116; + default: return -1; + } + break; + case Arch_x86_64: + switch(val()) { + case Dyninst::x86_64::irax: return 0; + case Dyninst::x86_64::irdx: return 1; + case Dyninst::x86_64::ircx: return 2; + case Dyninst::x86_64::irbx: return 3; + case Dyninst::x86_64::irsi: return 4; + case Dyninst::x86_64::irdi: return 5; + case Dyninst::x86_64::irbp: return 6; + case Dyninst::x86_64::irsp: return 7; + case Dyninst::x86_64::ir8: return 8; + case Dyninst::x86_64::ir9: return 9; + case Dyninst::x86_64::ir10: return 10; + case Dyninst::x86_64::ir11: return 11; + case Dyninst::x86_64::ir12: return 12; + case Dyninst::x86_64::ir13: return 13; + case Dyninst::x86_64::ir14: return 14; + case Dyninst::x86_64::ir15: return 15; + case Dyninst::x86_64::irip: return 16; + case Dyninst::x86_64::ixmm0: return 17; + case Dyninst::x86_64::ixmm1: return 18; + case Dyninst::x86_64::ixmm2: return 19; + case Dyninst::x86_64::ixmm3: return 20; + case Dyninst::x86_64::ixmm4: return 21; + case Dyninst::x86_64::ixmm5: return 22; + case Dyninst::x86_64::ixmm6: return 23; + case Dyninst::x86_64::ixmm7: return 24; + case Dyninst::x86_64::ixmm8: return 25; + case Dyninst::x86_64::ixmm9: return 26; + case Dyninst::x86_64::ixmm10: return 27; + case Dyninst::x86_64::ixmm11: return 28; + case Dyninst::x86_64::ixmm12: return 29; + case Dyninst::x86_64::ixmm13: return 30; + case Dyninst::x86_64::ixmm14: return 31; + case Dyninst::x86_64::ixmm15: return 32; + case Dyninst::x86_64::ist0: return 33; + case Dyninst::x86_64::ist1: return 34; + case Dyninst::x86_64::ist2: return 35; + case Dyninst::x86_64::ist3: return 36; + case Dyninst::x86_64::ist4: return 37; + case Dyninst::x86_64::ist5: return 38; + case Dyninst::x86_64::ist6: return 39; + case Dyninst::x86_64::ist7: return 40; + case Dyninst::x86_64::imm0: return 41; + case Dyninst::x86_64::imm1: return 42; + case Dyninst::x86_64::imm2: return 43; + case Dyninst::x86_64::imm3: return 44; + case Dyninst::x86_64::imm4: return 45; + case Dyninst::x86_64::imm5: return 46; + case Dyninst::x86_64::imm6: return 47; + case Dyninst::x86_64::imm7: return 48; + case Dyninst::x86_64::iflags: return 49; + case Dyninst::x86_64::ies: return 50; + case Dyninst::x86_64::ics: return 51; + case Dyninst::x86_64::iss: return 52; + case Dyninst::x86_64::ids: return 53; + case Dyninst::x86_64::ifs: return 54; + case Dyninst::x86_64::igs: return 55; + /*[56] Reserved */ + /*[57] Reserved */ + case Dyninst::x86_64::ifsbase: return 58; + case Dyninst::x86_64::igsbase: return 59; + /*[60] Reserved */ + /*[61] Reserved */ + case Dyninst::x86_64::itr: return 62; + case Dyninst::x86_64::ildtr: return 63; + case Dyninst::x86_64::imxcsr: return 64; + case Dyninst::x86_64::ifcw: return 65; + case Dyninst::x86_64::ifsw: return 66; + case Dyninst::x86_64::ixmm16: return 67; + case Dyninst::x86_64::ixmm17: return 68; + case Dyninst::x86_64::ixmm18: return 69; + case Dyninst::x86_64::ixmm19: return 70; + case Dyninst::x86_64::ixmm20: return 71; + case Dyninst::x86_64::ixmm21: return 72; + case Dyninst::x86_64::ixmm22: return 73; + case Dyninst::x86_64::ixmm23: return 74; + case Dyninst::x86_64::ixmm24: return 75; + case Dyninst::x86_64::ixmm25: return 76; + case Dyninst::x86_64::ixmm26: return 77; + case Dyninst::x86_64::ixmm27: return 78; + case Dyninst::x86_64::ixmm28: return 79; + case Dyninst::x86_64::ixmm29: return 80; + case Dyninst::x86_64::ixmm30: return 81; + case Dyninst::x86_64::ixmm31: return 82; + /*[83] Reserved */ + /*[84] Reserved */ + /*[85] Reserved */ + /*[86] Reserved */ + /*[87] Reserved */ + /*[88] Reserved */ + /*[89] Reserved */ + /*[90] Reserved */ + /*[91] Reserved */ + /*[92] Reserved */ + /*[93] Reserved */ + /*[94] Reserved */ + /*[95] Reserved */ + /*[96] Reserved */ + /*[97] Reserved */ + /*[98] Reserved */ + /*[99] Reserved */ + /*[100] Reserved */ + /*[101] Reserved */ + /*[102] Reserved */ + /*[103] Reserved */ + /*[104] Reserved */ + /*[105] Reserved */ + /*[106] Reserved */ + /*[107] Reserved */ + /*[108] Reserved */ + /*[109] Reserved */ + /*[110] Reserved */ + /*[111] Reserved */ + /*[112] Reserved */ + /*[113] Reserved */ + /*[114] Reserved */ + /*[115] Reserved */ + /*[116] Reserved */ + /*[117] Reserved */ + case Dyninst::x86_64::ik0: return 118; + case Dyninst::x86_64::ik1: return 119; + case Dyninst::x86_64::ik2: return 120; + case Dyninst::x86_64::ik3: return 121; + case Dyninst::x86_64::ik4: return 122; + case Dyninst::x86_64::ik5: return 123; + case Dyninst::x86_64::ik6: return 124; + case Dyninst::x86_64::ik7: return 125; + /*[126] Reserved */ + /*[127] Reserved */ + /*[128] Reserved */ + /*[129] Reserved */ + + /* End of documented registers */ + /* The rest of these are assigned arbitrary values for internal Dyninst use. */ + case Dyninst::x86_64::ieax: return 1024; + case Dyninst::x86_64::iax: return 1025; + case Dyninst::x86_64::iah: return 1026; + case Dyninst::x86_64::ial: return 1027; + case Dyninst::x86_64::iecx: return 1028; + case Dyninst::x86_64::icx: return 1029; + case Dyninst::x86_64::ich: return 1030; + case Dyninst::x86_64::icl: return 1031; + case Dyninst::x86_64::iedx: return 1032; + case Dyninst::x86_64::idx: return 1033; + case Dyninst::x86_64::idh: return 1034; + case Dyninst::x86_64::idl: return 1035; + case Dyninst::x86_64::iebx: return 1036; + case Dyninst::x86_64::ibx: return 1037; + case Dyninst::x86_64::ibh: return 1038; + case Dyninst::x86_64::ibl: return 1039; + case Dyninst::x86_64::iesp: return 1040; + case Dyninst::x86_64::isp: return 1041; + case Dyninst::x86_64::ispl: return 1042; + case Dyninst::x86_64::iebp: return 1043; + case Dyninst::x86_64::ibp: return 1044; + case Dyninst::x86_64::ibpl: return 1045; + case Dyninst::x86_64::iesi: return 1046; + case Dyninst::x86_64::isi: return 1047; + case Dyninst::x86_64::isil: return 1048; + case Dyninst::x86_64::iedi: return 1049; + case Dyninst::x86_64::idi: return 1050; + case Dyninst::x86_64::idil: return 1051; + case Dyninst::x86_64::ir8b: return 1052; + case Dyninst::x86_64::ir8w: return 1053; + case Dyninst::x86_64::ir8d: return 1054; + case Dyninst::x86_64::ir9b: return 1055; + case Dyninst::x86_64::ir9w: return 1056; + case Dyninst::x86_64::ir9d: return 1057; + case Dyninst::x86_64::ir10b: return 1058; + case Dyninst::x86_64::ir10w: return 1059; + case Dyninst::x86_64::ir10d: return 1060; + case Dyninst::x86_64::ir11b: return 1061; + case Dyninst::x86_64::ir11w: return 1062; + case Dyninst::x86_64::ir11d: return 1063; + case Dyninst::x86_64::ir12b: return 1064; + case Dyninst::x86_64::ir12w: return 1065; + case Dyninst::x86_64::ir12d: return 1066; + case Dyninst::x86_64::ir13b: return 1067; + case Dyninst::x86_64::ir13w: return 1068; + case Dyninst::x86_64::ir13d: return 1069; + case Dyninst::x86_64::ir14b: return 1070; + case Dyninst::x86_64::ir14w: return 1071; + case Dyninst::x86_64::ir14d: return 1072; + case Dyninst::x86_64::ir15b: return 1073; + case Dyninst::x86_64::ir15w: return 1074; + case Dyninst::x86_64::ir15d: return 1075; + case Dyninst::x86_64::ieip: return 1076; + case Dyninst::x86_64::icf: return 1077; + case Dyninst::x86_64::iflag1: return 1078; + case Dyninst::x86_64::ipf: return 1079; + case Dyninst::x86_64::iflag3: return 1080; + case Dyninst::x86_64::iaf: return 1081; + case Dyninst::x86_64::iflag5: return 1082; + case Dyninst::x86_64::izf: return 1083; + case Dyninst::x86_64::isf: return 1084; + case Dyninst::x86_64::itf: return 1085; + case Dyninst::x86_64::iif_: return 1086; + case Dyninst::x86_64::idf: return 1087; + case Dyninst::x86_64::iof: return 1088; + case Dyninst::x86_64::iflagc: return 1089; + case Dyninst::x86_64::iflagd: return 1090; + case Dyninst::x86_64::int_: return 1091; + case Dyninst::x86_64::iflagf: return 1092; + case Dyninst::x86_64::irf: return 1093; + case Dyninst::x86_64::ivm: return 1094; + case Dyninst::x86_64::iac: return 1095; + case Dyninst::x86_64::ivif: return 1096; + case Dyninst::x86_64::ivip: return 1097; + case Dyninst::x86_64::iid: return 1098; + case Dyninst::x86_64::igdtr: return 1099; + case Dyninst::x86_64::iidtr: return 1100; + case Dyninst::x86_64::icr0: return 1101; + case Dyninst::x86_64::icr1: return 1102; + case Dyninst::x86_64::icr2: return 1103; + case Dyninst::x86_64::icr3: return 1104; + case Dyninst::x86_64::icr4: return 1105; + case Dyninst::x86_64::icr5: return 1106; + case Dyninst::x86_64::icr6: return 1107; + case Dyninst::x86_64::icr7: return 1108; + case Dyninst::x86_64::icr8: return 1109; + case Dyninst::x86_64::icr9: return 1110; + case Dyninst::x86_64::icr10: return 1111; + case Dyninst::x86_64::icr11: return 1112; + case Dyninst::x86_64::icr12: return 1113; + case Dyninst::x86_64::icr13: return 1114; + case Dyninst::x86_64::icr14: return 1115; + case Dyninst::x86_64::icr15: return 1116; + case Dyninst::x86_64::idr0: return 1117; + case Dyninst::x86_64::idr1: return 1118; + case Dyninst::x86_64::idr2: return 1119; + case Dyninst::x86_64::idr3: return 1120; + case Dyninst::x86_64::idr4: return 1121; + case Dyninst::x86_64::idr5: return 1122; + case Dyninst::x86_64::idr6: return 1123; + case Dyninst::x86_64::idr7: return 1124; + case Dyninst::x86_64::idr8: return 1125; + case Dyninst::x86_64::idr9: return 1126; + case Dyninst::x86_64::idr10: return 1127; + case Dyninst::x86_64::idr11: return 1128; + case Dyninst::x86_64::idr12: return 1129; + case Dyninst::x86_64::idr13: return 1130; + case Dyninst::x86_64::idr14: return 1131; + case Dyninst::x86_64::idr15: return 1132; + case Dyninst::x86_64::iymm0: return 1133; + case Dyninst::x86_64::iymm1: return 1134; + case Dyninst::x86_64::iymm2: return 1135; + case Dyninst::x86_64::iymm3: return 1136; + case Dyninst::x86_64::iymm4: return 1137; + case Dyninst::x86_64::iymm5: return 1138; + case Dyninst::x86_64::iymm6: return 1139; + case Dyninst::x86_64::iymm7: return 1140; + case Dyninst::x86_64::iymm8: return 1141; + case Dyninst::x86_64::iymm9: return 1142; + case Dyninst::x86_64::iymm10: return 1143; + case Dyninst::x86_64::iymm11: return 1144; + case Dyninst::x86_64::iymm12: return 1145; + case Dyninst::x86_64::iymm13: return 1146; + case Dyninst::x86_64::iymm14: return 1147; + case Dyninst::x86_64::iymm15: return 1148; + case Dyninst::x86_64::iymm16: return 1149; + case Dyninst::x86_64::iymm17: return 1150; + case Dyninst::x86_64::iymm18: return 1151; + case Dyninst::x86_64::iymm19: return 1152; + case Dyninst::x86_64::iymm20: return 1153; + case Dyninst::x86_64::iymm21: return 1154; + case Dyninst::x86_64::iymm22: return 1155; + case Dyninst::x86_64::iymm23: return 1156; + case Dyninst::x86_64::iymm24: return 1157; + case Dyninst::x86_64::iymm25: return 1158; + case Dyninst::x86_64::iymm26: return 1159; + case Dyninst::x86_64::iymm27: return 1160; + case Dyninst::x86_64::iymm28: return 1161; + case Dyninst::x86_64::iymm29: return 1162; + case Dyninst::x86_64::iymm30: return 1163; + case Dyninst::x86_64::iymm31: return 1164; + case Dyninst::x86_64::izmm0: return 1165; + case Dyninst::x86_64::izmm1: return 1166; + case Dyninst::x86_64::izmm2: return 1167; + case Dyninst::x86_64::izmm3: return 1168; + case Dyninst::x86_64::izmm4: return 1169; + case Dyninst::x86_64::izmm5: return 1170; + case Dyninst::x86_64::izmm6: return 1171; + case Dyninst::x86_64::izmm7: return 1172; + case Dyninst::x86_64::izmm8: return 1173; + case Dyninst::x86_64::izmm9: return 1174; + case Dyninst::x86_64::izmm10: return 1175; + case Dyninst::x86_64::izmm11: return 1176; + case Dyninst::x86_64::izmm12: return 1177; + case Dyninst::x86_64::izmm13: return 1178; + case Dyninst::x86_64::izmm14: return 1179; + case Dyninst::x86_64::izmm15: return 1180; + case Dyninst::x86_64::izmm16: return 1181; + case Dyninst::x86_64::izmm17: return 1182; + case Dyninst::x86_64::izmm18: return 1183; + case Dyninst::x86_64::izmm19: return 1184; + case Dyninst::x86_64::izmm20: return 1185; + case Dyninst::x86_64::izmm21: return 1186; + case Dyninst::x86_64::izmm22: return 1187; + case Dyninst::x86_64::izmm23: return 1188; + case Dyninst::x86_64::izmm24: return 1189; + case Dyninst::x86_64::izmm25: return 1190; + case Dyninst::x86_64::izmm26: return 1191; + case Dyninst::x86_64::izmm27: return 1192; + case Dyninst::x86_64::izmm28: return 1193; + case Dyninst::x86_64::izmm29: return 1194; + case Dyninst::x86_64::izmm30: return 1195; + case Dyninst::x86_64::izmm31: return 1196; + case Dyninst::x86_64::iorax: return 1197; + case Dyninst::x86_64::itr0: return 1198; + case Dyninst::x86_64::itr1: return 1199; + case Dyninst::x86_64::itr2: return 1200; + case Dyninst::x86_64::itr3: return 1201; + case Dyninst::x86_64::itr4: return 1202; + case Dyninst::x86_64::itr5: return 1203; + case Dyninst::x86_64::itr6: return 1204; + case Dyninst::x86_64::itr7: return 1205; + default: return -1; + } + break; + case Arch_ppc32: + switch(val()) { + case Dyninst::ppc32::ir0: return 0; + case Dyninst::ppc32::ir1: return 1; + case Dyninst::ppc32::ir2: return 2; + case Dyninst::ppc32::ir3: return 3; + case Dyninst::ppc32::ir4: return 4; + case Dyninst::ppc32::ir5: return 5; + case Dyninst::ppc32::ir6: return 6; + case Dyninst::ppc32::ir7: return 7; + case Dyninst::ppc32::ir8: return 8; + case Dyninst::ppc32::ir9: return 9; + case Dyninst::ppc32::ir10: return 10; + case Dyninst::ppc32::ir11: return 11; + case Dyninst::ppc32::ir12: return 12; + case Dyninst::ppc32::ir13: return 13; + case Dyninst::ppc32::ir14: return 14; + case Dyninst::ppc32::ir15: return 15; + case Dyninst::ppc32::ir16: return 16; + case Dyninst::ppc32::ir17: return 17; + case Dyninst::ppc32::ir18: return 18; + case Dyninst::ppc32::ir19: return 19; + case Dyninst::ppc32::ir20: return 20; + case Dyninst::ppc32::ir21: return 21; + case Dyninst::ppc32::ir22: return 22; + case Dyninst::ppc32::ir23: return 23; + case Dyninst::ppc32::ir24: return 24; + case Dyninst::ppc32::ir25: return 25; + case Dyninst::ppc32::ir26: return 26; + case Dyninst::ppc32::ir27: return 27; + case Dyninst::ppc32::ir28: return 28; + case Dyninst::ppc32::ir29: return 29; + case Dyninst::ppc32::ir30: return 30; + case Dyninst::ppc32::ir31: return 31; + case Dyninst::ppc32::ifpr0: return 32; + case Dyninst::ppc32::ifpr1: return 33; + case Dyninst::ppc32::ifpr2: return 34; + case Dyninst::ppc32::ifpr3: return 35; + case Dyninst::ppc32::ifpr4: return 36; + case Dyninst::ppc32::ifpr5: return 37; + case Dyninst::ppc32::ifpr6: return 38; + case Dyninst::ppc32::ifpr7: return 39; + case Dyninst::ppc32::ifpr8: return 40; + case Dyninst::ppc32::ifpr9: return 41; + case Dyninst::ppc32::ifpr10: return 42; + case Dyninst::ppc32::ifpr11: return 43; + case Dyninst::ppc32::ifpr12: return 44; + case Dyninst::ppc32::ifpr13: return 45; + case Dyninst::ppc32::ifpr14: return 46; + case Dyninst::ppc32::ifpr15: return 47; + case Dyninst::ppc32::ifpr16: return 48; + case Dyninst::ppc32::ifpr17: return 49; + case Dyninst::ppc32::ifpr18: return 50; + case Dyninst::ppc32::ifpr19: return 51; + case Dyninst::ppc32::ifpr20: return 52; + case Dyninst::ppc32::ifpr21: return 53; + case Dyninst::ppc32::ifpr22: return 54; + case Dyninst::ppc32::ifpr23: return 55; + case Dyninst::ppc32::ifpr24: return 56; + case Dyninst::ppc32::ifpr25: return 57; + case Dyninst::ppc32::ifpr26: return 58; + case Dyninst::ppc32::ifpr27: return 59; + case Dyninst::ppc32::ifpr28: return 60; + case Dyninst::ppc32::ifpr29: return 61; + case Dyninst::ppc32::ifpr30: return 62; + case Dyninst::ppc32::ifpr31: return 63; + case Dyninst::ppc32::icr: return 64; + case Dyninst::ppc32::imq: return 100; + case Dyninst::ppc32::ixer: return 101; + case Dyninst::ppc32::ilr: return 108; + case Dyninst::ppc32::ictr: return 109; + default: return -1; + } + case Arch_ppc64: + switch(val()) { + case Dyninst::ppc64::ir0: return 0; + case Dyninst::ppc64::ir1: return 1; + case Dyninst::ppc64::ir2: return 2; + case Dyninst::ppc64::ir3: return 3; + case Dyninst::ppc64::ir4: return 4; + case Dyninst::ppc64::ir5: return 5; + case Dyninst::ppc64::ir6: return 6; + case Dyninst::ppc64::ir7: return 7; + case Dyninst::ppc64::ir8: return 8; + case Dyninst::ppc64::ir9: return 9; + case Dyninst::ppc64::ir10: return 10; + case Dyninst::ppc64::ir11: return 11; + case Dyninst::ppc64::ir12: return 12; + case Dyninst::ppc64::ir13: return 13; + case Dyninst::ppc64::ir14: return 14; + case Dyninst::ppc64::ir15: return 15; + case Dyninst::ppc64::ir16: return 16; + case Dyninst::ppc64::ir17: return 17; + case Dyninst::ppc64::ir18: return 18; + case Dyninst::ppc64::ir19: return 19; + case Dyninst::ppc64::ir20: return 20; + case Dyninst::ppc64::ir21: return 21; + case Dyninst::ppc64::ir22: return 22; + case Dyninst::ppc64::ir23: return 23; + case Dyninst::ppc64::ir24: return 24; + case Dyninst::ppc64::ir25: return 25; + case Dyninst::ppc64::ir26: return 26; + case Dyninst::ppc64::ir27: return 27; + case Dyninst::ppc64::ir28: return 28; + case Dyninst::ppc64::ir29: return 29; + case Dyninst::ppc64::ir30: return 30; + case Dyninst::ppc64::ir31: return 31; + case Dyninst::ppc64::ifpr0: return 32; + case Dyninst::ppc64::ifpr1: return 33; + case Dyninst::ppc64::ifpr2: return 34; + case Dyninst::ppc64::ifpr3: return 35; + case Dyninst::ppc64::ifpr4: return 36; + case Dyninst::ppc64::ifpr5: return 37; + case Dyninst::ppc64::ifpr6: return 38; + case Dyninst::ppc64::ifpr7: return 39; + case Dyninst::ppc64::ifpr8: return 40; + case Dyninst::ppc64::ifpr9: return 41; + case Dyninst::ppc64::ifpr10: return 42; + case Dyninst::ppc64::ifpr11: return 43; + case Dyninst::ppc64::ifpr12: return 44; + case Dyninst::ppc64::ifpr13: return 45; + case Dyninst::ppc64::ifpr14: return 46; + case Dyninst::ppc64::ifpr15: return 47; + case Dyninst::ppc64::ifpr16: return 48; + case Dyninst::ppc64::ifpr17: return 49; + case Dyninst::ppc64::ifpr18: return 50; + case Dyninst::ppc64::ifpr19: return 51; + case Dyninst::ppc64::ifpr20: return 52; + case Dyninst::ppc64::ifpr21: return 53; + case Dyninst::ppc64::ifpr22: return 54; + case Dyninst::ppc64::ifpr23: return 55; + case Dyninst::ppc64::ifpr24: return 56; + case Dyninst::ppc64::ifpr25: return 57; + case Dyninst::ppc64::ifpr26: return 58; + case Dyninst::ppc64::ifpr27: return 59; + case Dyninst::ppc64::ifpr28: return 60; + case Dyninst::ppc64::ifpr29: return 61; + case Dyninst::ppc64::ifpr30: return 62; + case Dyninst::ppc64::ifpr31: return 63; + case Dyninst::ppc64::icr: return 64; + case Dyninst::ppc64::imq: return 100; + case Dyninst::ppc64::ixer: return 101; + case Dyninst::ppc64::ilr: return 108; + case Dyninst::ppc64::ictr: return 109; + default: return -1; + } + break; + case Arch_aarch64: + switch(val()) { + case Dyninst::aarch64::ix0: return 0; + case Dyninst::aarch64::ix1: return 1; + case Dyninst::aarch64::ix2: return 2; + case Dyninst::aarch64::ix3: return 3; + case Dyninst::aarch64::ix4: return 4; + case Dyninst::aarch64::ix5: return 5; + case Dyninst::aarch64::ix6: return 6; + case Dyninst::aarch64::ix7: return 7; + case Dyninst::aarch64::ix8: return 8; + case Dyninst::aarch64::ix9: return 9; + case Dyninst::aarch64::ix10: return 10; + case Dyninst::aarch64::ix11: return 11; + case Dyninst::aarch64::ix12: return 12; + case Dyninst::aarch64::ix13: return 13; + case Dyninst::aarch64::ix14: return 14; + case Dyninst::aarch64::ix15: return 15; + case Dyninst::aarch64::ix16: return 16; + case Dyninst::aarch64::ix17: return 17; + case Dyninst::aarch64::ix18: return 18; + case Dyninst::aarch64::ix19: return 19; + case Dyninst::aarch64::ix20: return 20; + case Dyninst::aarch64::ix21: return 21; + case Dyninst::aarch64::ix22: return 22; + case Dyninst::aarch64::ix23: return 23; + case Dyninst::aarch64::ix24: return 24; + case Dyninst::aarch64::ix25: return 25; + case Dyninst::aarch64::ix26: return 26; + case Dyninst::aarch64::ix27: return 27; + case Dyninst::aarch64::ix28: return 28; + case Dyninst::aarch64::ix29: return 29; + case Dyninst::aarch64::ix30: return 30; + case Dyninst::aarch64::isp: return 31; + + case Dyninst::aarch64::iq0: return 64; + case Dyninst::aarch64::iq1: return 65; + case Dyninst::aarch64::iq2: return 66; + case Dyninst::aarch64::iq3: return 67; + case Dyninst::aarch64::iq4: return 68; + case Dyninst::aarch64::iq5: return 69; + case Dyninst::aarch64::iq6: return 70; + case Dyninst::aarch64::iq7: return 71; + case Dyninst::aarch64::iq8: return 72; + case Dyninst::aarch64::iq9: return 73; + case Dyninst::aarch64::iq10: return 74; + case Dyninst::aarch64::iq11: return 75; + case Dyninst::aarch64::iq12: return 76; + case Dyninst::aarch64::iq13: return 77; + case Dyninst::aarch64::iq14: return 78; + case Dyninst::aarch64::iq15: return 79; + case Dyninst::aarch64::iq16: return 80; + case Dyninst::aarch64::iq17: return 81; + case Dyninst::aarch64::iq18: return 82; + case Dyninst::aarch64::iq19: return 83; + case Dyninst::aarch64::iq20: return 84; + case Dyninst::aarch64::iq21: return 85; + case Dyninst::aarch64::iq22: return 86; + case Dyninst::aarch64::iq23: return 87; + case Dyninst::aarch64::iq24: return 88; + case Dyninst::aarch64::iq25: return 89; + case Dyninst::aarch64::iq26: return 90; + case Dyninst::aarch64::iq27: return 91; + case Dyninst::aarch64::iq28: return 92; + case Dyninst::aarch64::iq29: return 93; + case Dyninst::aarch64::iq30: return 94; + case Dyninst::aarch64::iq31: return 95; + + default: return -1; + } + break; + case Arch_none: assert(0); return -1; + default: assert(0); return -1; + } + // Invalid register passed + return -1; + } + + MachRegister MachRegister::getArchReg(unsigned int regNum, Dyninst::Architecture arch) { + switch(arch) { + case Arch_aarch64: + switch(regNum) { + case 0: return Dyninst::aarch64::x0; + case 1: return Dyninst::aarch64::x1; + case 2: return Dyninst::aarch64::x2; + case 3: return Dyninst::aarch64::x3; + case 4: return Dyninst::aarch64::x4; + case 5: return Dyninst::aarch64::x5; + case 6: return Dyninst::aarch64::x6; + case 7: return Dyninst::aarch64::x7; + case 8: return Dyninst::aarch64::x8; + case 9: return Dyninst::aarch64::x9; + case 10: return Dyninst::aarch64::x10; + case 11: return Dyninst::aarch64::x11; + case 12: return Dyninst::aarch64::x12; + case 13: return Dyninst::aarch64::x13; + case 14: return Dyninst::aarch64::x14; + case 15: return Dyninst::aarch64::x15; + case 16: return Dyninst::aarch64::x16; + case 17: return Dyninst::aarch64::x17; + case 18: return Dyninst::aarch64::x18; + case 19: return Dyninst::aarch64::x19; + case 20: return Dyninst::aarch64::x20; + case 21: return Dyninst::aarch64::x21; + case 22: return Dyninst::aarch64::x22; + case 23: return Dyninst::aarch64::x23; + case 24: return Dyninst::aarch64::x24; + case 25: return Dyninst::aarch64::x25; + case 26: return Dyninst::aarch64::x26; + case 27: return Dyninst::aarch64::x27; + case 28: return Dyninst::aarch64::x28; + case 29: return Dyninst::aarch64::x29; + case 30: return Dyninst::aarch64::x30; + + case 100: return Dyninst::aarch64::sp; + case 101: return Dyninst::aarch64::pc; + case 102: return Dyninst::aarch64::pstate; + case 103: return Dyninst::aarch64::xzr; + default: return InvalidReg; + } + default: return InvalidReg; + } + return InvalidReg; + } + +} diff --git a/common/src/sha1.C b/common/src/sha1.C index 81725ee213..1e5d8136fb 100644 --- a/common/src/sha1.C +++ b/common/src/sha1.C @@ -100,10 +100,11 @@ A million repetitions of "a" /* #define SHA1HANDSOFF */ +#include #include #include -#include "common/src/Types.h" +#include "dyntypes.h" #include "common/src/sha1.h" /* #include */ /* prototype for exit() - JHB */ /* Using return() instead of exit() - SWR */ diff --git a/common/src/singleton_object_pool.h b/common/src/singleton_object_pool.h index 814b2228db..122a4384c1 100644 --- a/common/src/singleton_object_pool.h +++ b/common/src/singleton_object_pool.h @@ -30,6 +30,7 @@ #if !defined(SINGLETON_OBJECT_POOL_H) #define SINGLETON_OBJECT_POOL_H +#include #include "pool_allocators.h" #include "dthread.h" #include "compiler_annotations.h" @@ -83,9 +84,9 @@ struct PoolDestructor }; template inline -boost::shared_ptr make_shared(T* t) +dyncompat::shared_ptr make_shared(T* t) { - return boost::shared_ptr(t, PoolDestructor()/*, typename unlocked_fast_alloc::type()*/); + return dyncompat::shared_ptr(t, PoolDestructor()/*, typename unlocked_fast_alloc::type()*/); } diff --git a/common/src/stats.C b/common/src/stats.C index d5028b415c..3e7dfaa63a 100644 --- a/common/src/stats.C +++ b/common/src/stats.C @@ -33,6 +33,7 @@ * $Id: stats.C,v 1.2 2008/07/01 19:26:49 legendre Exp $ */ +#include #include "common/src/headers.h" #include "common/src/stats.h" #include "common/h/util.h" diff --git a/common/src/symbolDemangle.c b/common/src/symbolDemangle.c index 41fb58af33..decfecf33b 100644 --- a/common/src/symbolDemangle.c +++ b/common/src/symbolDemangle.c @@ -38,13 +38,13 @@ // Returns a malloc'd string that is the demangled symbol name. THe caller is // responsible for the freeing this memory. Returns NULL on malloc failure. // The symbol name symName is demangled using the cplus_demangle function after -// first removing any versioning suffixes (first '@') or stabs suffixes (first -// ':') to create the mangled name. If cplus_demangle fails, the mangled name +// first removing any versioning suffixes (first '@') +// to create the mangled name. If cplus_demangle fails, the mangled name // is returned unmodified. If cplus_demangle succeeds and includeParams is // false, then any clone suffixes (the first '.' to the end of the mangled // name) are appended to the value from cplus_demangle. // -// Other than the removal of versioning and stabs suffixes, and appending any +// Other than the removal of versioning suffixes, and appending any // clone suffixes if includeParams is false to the result, the result should be // equivalent to using c++filt. Below are the c++filt and cplus_demangle // options @@ -57,34 +57,34 @@ char *symbol_demangle(const char *symName, int includeParams) { int cloneOffset = -1; // offset to clone suffix - int versionOrStabsOffset = -1; // offset to version or stabs suffix - int lastOffset; // offset to version or stabs suffix + int versionOffset = -1; // offset to version suffix + int lastOffset; // offset to version suffix // if present, else null of symName - // find both clone, and then version or stabs suffixes if any + // find both clone, and then version suffixes if any for (lastOffset = 0; symName[lastOffset]; ++lastOffset) { char c = symName[lastOffset]; if (c == '.' && cloneOffset == -1) { // clone suffix start with first '.' cloneOffset = lastOffset; - } else if (c == '@' || c == ':') { - // version ('@') or stabs (':') suffix found - versionOrStabsOffset = lastOffset; + } else if (c == '@') { + // version ('@') suffix found + versionOffset = lastOffset; // stop searching break; } } - const char *mangledName = symName; // symName without version/stabs suffix + const char *mangledName = symName; // symName without version suffix char *allocatedMangledName = 0; - if (versionOrStabsOffset != -1) { - // make a copy of the symName without version or stabs suffix - allocatedMangledName = malloc(versionOrStabsOffset + 1); + if (versionOffset != -1) { + // make a copy of the symName without version suffix + allocatedMangledName = malloc(versionOffset + 1); if (allocatedMangledName == 0) { return NULL; } - memcpy(allocatedMangledName, symName, versionOrStabsOffset); - allocatedMangledName[versionOrStabsOffset] = '\0'; + memcpy(allocatedMangledName, symName, versionOffset); + allocatedMangledName[versionOffset] = '\0'; mangledName = allocatedMangledName; } diff --git a/common/src/util.C b/common/src/util.C index 904c5d8424..f24c8a4a51 100644 --- a/common/src/util.C +++ b/common/src/util.C @@ -208,8 +208,6 @@ const char *platform_string() #if defined (os_linux) #if defined (arch_64bit) return "ppc64_linux"; -#else - return "ppc32_linux"; #endif #endif #endif diff --git a/common/src/vm_maps.h b/common/src/vm_maps.h new file mode 100644 index 0000000000..fac1bf8c17 --- /dev/null +++ b/common/src/vm_maps.h @@ -0,0 +1,60 @@ +/* + * See the dyninst/COPYRIGHT file for copyright information. + * + * We provide the Paradyn Tools (below described as "Paradyn") + * on an AS IS basis, and do not warrant its validity or performance. + * We reserve the right to update, modify, or discontinue this + * software at any time. We shall have no obligation to supply such + * updates or modifications or any other form of support to you. + * + * By your use of Paradyn, you understand and agree that we (or any + * other person or entity with proprietary rights in Paradyn) are + * under no obligation to provide either maintenance services, + * update services, notices of latent defects, or correction of + * defects for Paradyn. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef DYNINST_VM_MAPS +#define DYNINST_VM_MAPS + +#include "dyntypes.h" + +// Virtual Memory Map -- shared between platforms +#define PREMS_PRIVATE (1 << 4) +#define PREMS_SHARED (1 << 3) +#define PREMS_READ (1 << 2) +#define PREMS_WRITE (1 << 1) +#define PREMS_EXEC (1 << 0) + +#define MAPENTRIES_PATH_SIZE 512 +#define MAPENTRIES_PATH_SIZE_STR "512" + +typedef struct maps_entries { +#if defined __cplusplus + using Address = Dyninst::Address; +#endif + Address start; + Address end; + unsigned prems; + Address offset; + int dev_major; + int dev_minor; + unsigned long inode; + char path[MAPENTRIES_PATH_SIZE]; +} map_entries; + +#endif diff --git a/dataflowAPI/doc/dataflowAPI.pdf b/dataflowAPI/doc/dataflowAPI.pdf index fce535adb4..496e2c5a8c 100644 Binary files a/dataflowAPI/doc/dataflowAPI.pdf and b/dataflowAPI/doc/dataflowAPI.pdf differ diff --git a/dataflowAPI/h/ABI.h b/dataflowAPI/h/ABI.h index cf94608102..372db066f1 100644 --- a/dataflowAPI/h/ABI.h +++ b/dataflowAPI/h/ABI.h @@ -30,7 +30,7 @@ #ifndef ABI_H #define ABI_H -#include "dyn_regs.h" +#include "registers/MachRegister.h" #include "bitArray.h" #include diff --git a/dataflowAPI/h/Absloc.h b/dataflowAPI/h/Absloc.h index b4e9edc201..181e1bf2bb 100644 --- a/dataflowAPI/h/Absloc.h +++ b/dataflowAPI/h/Absloc.h @@ -48,6 +48,12 @@ #include #endif +#include +#include +#include +#include +#include +#include #include "Instruction.h" #include "DynAST.h" @@ -276,7 +282,7 @@ class AbsRegion { class Assignment { public: - typedef boost::shared_ptr Ptr; + typedef dyncompat::shared_ptr Ptr; struct AssignmentPtrHasher { size_t operator() (const Ptr& ap) const noexcept { return (size_t)ap.get(); diff --git a/dataflowAPI/h/AbslocInterface.h b/dataflowAPI/h/AbslocInterface.h index b035c7526f..caa327cb10 100644 --- a/dataflowAPI/h/AbslocInterface.h +++ b/dataflowAPI/h/AbslocInterface.h @@ -32,8 +32,11 @@ #if !defined(Absloc_Interface_H) #define Absloc_Interface_H -#include "Instruction.h" +#include +#include + #include "Register.h" +#include "Instruction.h" #include "Expression.h" #include "Operand.h" #include "Absloc.h" diff --git a/dataflowAPI/h/SymEval.h b/dataflowAPI/h/SymEval.h index 80dfadbafe..e897063add 100644 --- a/dataflowAPI/h/SymEval.h +++ b/dataflowAPI/h/SymEval.h @@ -34,6 +34,13 @@ #define SymEval_h #include +#include +#include +#include +#include +#include +#include +#include #include "Absloc.h" #include "DynAST.h" @@ -325,8 +332,8 @@ class SymEvalPolicy; class SymEval { public: - typedef boost::shared_ptr SliceNodePtr; - typedef boost::shared_ptr InstructionPtr; + typedef dyncompat::shared_ptr SliceNodePtr; + typedef dyncompat::shared_ptr InstructionPtr; public: typedef enum { FAILED, diff --git a/dataflowAPI/h/bitArray.h b/dataflowAPI/h/bitArray.h index aae7e794a1..5b84c6494f 100644 --- a/dataflowAPI/h/bitArray.h +++ b/dataflowAPI/h/bitArray.h @@ -32,8 +32,9 @@ #ifndef _BITARRAY_ #define _BITARRAY_ -#include -typedef boost::dynamic_bitset > bitArray; +#include +#include +typedef dyncompat::dynamic_bitset > bitArray; // Bitarrays for register liveness. This could move to registerSpace... #define SPEC_GPR_BIT(x) (x.size() - 3) diff --git a/dataflowAPI/h/liveness.h b/dataflowAPI/h/liveness.h index d919fa060f..25a9eb4397 100644 --- a/dataflowAPI/h/liveness.h +++ b/dataflowAPI/h/liveness.h @@ -35,13 +35,13 @@ #include "CodeSource.h" #include "Location.h" #include "Instruction.h" -#include "Register.h" #include "InstructionDecoder.h" #include "InstructionCache.h" #include "bitArray.h" #include "ABI.h" #include #include +#include "Register.h" using namespace Dyninst; diff --git a/dataflowAPI/h/slicing.h b/dataflowAPI/h/slicing.h index ba77864842..c731eafa5e 100644 --- a/dataflowAPI/h/slicing.h +++ b/dataflowAPI/h/slicing.h @@ -42,6 +42,10 @@ #include #include #include +#include +#include +#include +#include #include "util.h" #include "Node.h" @@ -49,7 +53,7 @@ #include "AbslocInterface.h" -#include +#include namespace Dyninst { @@ -61,15 +65,15 @@ namespace ParseAPI { class Assignment; class AbsRegion; -typedef boost::shared_ptr AssignmentPtr; +typedef dyncompat::shared_ptr AssignmentPtr; class Graph; -typedef boost::shared_ptr GraphPtr; +typedef dyncompat::shared_ptr GraphPtr; namespace InstructionAPI { class Instruction; } - typedef boost::shared_ptr InstructionPtr; + typedef dyncompat::shared_ptr InstructionPtr; class Slicer; @@ -78,7 +82,7 @@ typedef boost::shared_ptr GraphPtr; // the DDG code. class DATAFLOW_EXPORT SliceNode : public Node { public: - typedef boost::shared_ptr Ptr; + typedef dyncompat::shared_ptr Ptr; static SliceNode::Ptr create(AssignmentPtr ptr, ParseAPI::Block *block, @@ -114,7 +118,7 @@ class DATAFLOW_EXPORT SliceNode : public Node { class SliceEdge : public Edge { public: - typedef boost::shared_ptr Ptr; + typedef dyncompat::shared_ptr Ptr; DATAFLOW_EXPORT static SliceEdge::Ptr create(SliceNode::Ptr source, SliceNode::Ptr target, @@ -725,7 +729,7 @@ class Slicer { struct EdgeTupleHasher { size_t operator() (const EdgeTuple& et) const { size_t seed = (size_t)(et.s.get()); - boost::hash_combine( seed , (size_t)(et.d.get())); + dyncompat::hash_combine( seed , (size_t)(et.d.get())); return seed; } }; diff --git a/dataflowAPI/h/stackanalysis.h b/dataflowAPI/h/stackanalysis.h index 01ceb6c380..5b309f3c81 100644 --- a/dataflowAPI/h/stackanalysis.h +++ b/dataflowAPI/h/stackanalysis.h @@ -35,6 +35,10 @@ #include #endif +#include +#include +#include +#include #include #include #include @@ -45,7 +49,6 @@ #include "Absloc.h" #include "dyntypes.h" -#include "dyn_regs.h" #include "util.h" // FreeBSD is missing a MINLONG and MAXLONG @@ -73,8 +76,8 @@ namespace Dyninst { class StackAnalysis { public: - typedef boost::shared_ptr InstructionPtr; - typedef boost::shared_ptr ExpressionPtr; + typedef dyncompat::shared_ptr InstructionPtr; + typedef dyncompat::shared_ptr ExpressionPtr; // This class represents a stack pointer definition by recording the block // and address of the definition, as well as the original absloc that was diff --git a/dataflowAPI/rose/ExtentMap.C b/dataflowAPI/rose/ExtentMap.C index af3d9070e8..0669757181 100644 --- a/dataflowAPI/rose/ExtentMap.C +++ b/dataflowAPI/rose/ExtentMap.C @@ -3,9 +3,11 @@ * single extent. This class is used to keep track of what parts of a binary file have been parsed, and is also used to * manage string table free lists, among other things. */ +#include #include "util/StringUtility.h" #include "ExtentMap.h" -#include +#include +#include #define DUMP_FIELD_WIDTH 64 @@ -19,7 +21,7 @@ AddressInterval toAddressInterval(const Extent &x) { ExtentMap toExtentMap(const AddressIntervalSet &x) { ExtentMap retval; - BOOST_FOREACH (const AddressInterval &interval, x.intervals()) + DYN_FOREACH (const AddressInterval &interval, x.intervals()) retval.insert(toExtent(interval)); return retval; } @@ -44,7 +46,7 @@ std::ostream& operator<<(std::ostream &out, const AddressInterval &x) { std::ostream& operator<<(std::ostream &out, const AddressIntervalSet &x) { out <<"{"; - BOOST_FOREACH (const AddressInterval &interval, x.intervals()) + DYN_FOREACH (const AddressInterval &interval, x.intervals()) out <<" " < +#include #include "rangemap.h" #include "typedefs.h" #include "util/Interval.h" diff --git a/dataflowAPI/rose/RegisterDescriptor.h b/dataflowAPI/rose/RegisterDescriptor.h index 8801281ef8..256c71f102 100644 --- a/dataflowAPI/rose/RegisterDescriptor.h +++ b/dataflowAPI/rose/RegisterDescriptor.h @@ -25,37 +25,37 @@ struct RegisterDescriptor { public: RegisterDescriptor() : majr(0), minr(0), offset(0), nbits(0) {} - RegisterDescriptor(unsigned majr, unsigned minr, unsigned offset, unsigned nbits) - : majr(majr), minr(minr), offset(offset), nbits(nbits) {} + RegisterDescriptor(unsigned majr_, unsigned minr_, unsigned offset_, unsigned nbits_) + : majr(majr_), minr(minr_), offset(offset_), nbits(nbits_) {} unsigned get_major() const { return majr; } bool is_valid() const { return nbits!=0; } - RegisterDescriptor &set_major(unsigned majr) { - this->majr = majr; + RegisterDescriptor &set_major(unsigned majr_) { + this->majr = majr_; return *this; } unsigned get_minor() const { return minr; } - RegisterDescriptor &set_minor(unsigned minr) { - this->minr = minr; + RegisterDescriptor &set_minor(unsigned minr_) { + this->minr = minr_; return *this; } unsigned get_offset() const { return offset; } - RegisterDescriptor &set_offset(unsigned offset) { - this->offset = offset; + RegisterDescriptor &set_offset(unsigned offset_) { + this->offset = offset_; return *this; } unsigned get_nbits() const { return nbits; } - RegisterDescriptor &set_nbits(unsigned nbits) { - this->nbits = nbits; + RegisterDescriptor &set_nbits(unsigned nbits_) { + this->nbits = nbits_; return *this; } bool operator<(const RegisterDescriptor &other) const; diff --git a/dataflowAPI/rose/SgAsmAMDGPUInstruction.h b/dataflowAPI/rose/SgAsmAMDGPUInstruction.h new file mode 100644 index 0000000000..9d545a28c5 --- /dev/null +++ b/dataflowAPI/rose/SgAsmAMDGPUInstruction.h @@ -0,0 +1,52 @@ +#ifndef SG_ASM_AMDGPU_INSN_H +#define SG_ASM_AMDGPU_INSN_H + +#include +#include "external/rose/amdgpuInstructionEnum.h" +#include "typedefs.h" +#include "SgAsmInstruction.h" + +class SgAsmAMDGPUInstruction : public SgAsmInstruction { +public: + +/*! \brief returns a string representing the class name */ + virtual std::string class_name() const; + +/*! \brief returns new style SageIII enum values */ + virtual VariantT variantT() const; // MS: new variant used in tree traversal + +/*! \brief static variant value */ + enum { + static_variant = V_SgAsmAMDGPUInstruction + }; + +/* the generated cast function */ +/*! \brief Casts pointer from base class to derived class */ + friend SgAsmAMDGPUInstruction *isSgAsmAMDGPUInstruction( SgNode * s ); + +/*! \brief Casts pointer from base class to derived class (for const pointers) */ + friend const SgAsmAMDGPUInstruction *isSgAsmAMDGPUInstruction(const SgNode *s); + +public: + AMDGPUInstructionKind get_kind() const; + + void set_kind(AMDGPUInstructionKind kind); + +public: + virtual ~SgAsmAMDGPUInstruction(); + + +public: + SgAsmAMDGPUInstruction(rose_addr_t address = 0, std::string mnemonic = "", + AMDGPUInstructionKind kind = rose_amdgpu_op_INVALID); + + +protected: +// Start of memberFunctionString + AMDGPUInstructionKind p_kind; + +// End of memberFunctionString + +}; + +#endif diff --git a/dataflowAPI/rose/SgAsmAmdgpuVegaInstruction.h b/dataflowAPI/rose/SgAsmAmdgpuVegaInstruction.h deleted file mode 100644 index d4602f1abf..0000000000 --- a/dataflowAPI/rose/SgAsmAmdgpuVegaInstruction.h +++ /dev/null @@ -1,51 +0,0 @@ -#ifndef SG_ASM_AMDGPU_VEGA_INSN_H -#define SG_ASM_AMDGPU_VEGA_INSN_H - -#include "external/rose/amdgpuInstructionEnum.h" -#include "typedefs.h" -#include "SgAsmInstruction.h" - -class SgAsmAmdgpuVegaInstruction : public SgAsmInstruction { -public: - -/*! \brief returns a string representing the class name */ - virtual std::string class_name() const; - -/*! \brief returns new style SageIII enum values */ - virtual VariantT variantT() const; // MS: new variant used in tree traversal - -/*! \brief static variant value */ - enum { - static_variant = V_SgAsmAmdgpuVegaInstruction - }; - -/* the generated cast function */ -/*! \brief Casts pointer from base class to derived class */ - friend SgAsmAmdgpuVegaInstruction *isSgAsmAmdgpuVegaInstruction( SgNode * s ); - -/*! \brief Casts pointer from base class to derived class (for const pointers) */ - friend const SgAsmAmdgpuVegaInstruction *isSgAsmAmdgpuVegaInstruction(const SgNode *s); - -public: - AmdgpuVegaInstructionKind get_kind() const; - - void set_kind(AmdgpuVegaInstructionKind kind); - -public: - virtual ~SgAsmAmdgpuVegaInstruction(); - - -public: - SgAsmAmdgpuVegaInstruction(rose_addr_t address = 0, std::string mnemonic = "", - AmdgpuVegaInstructionKind kind = rose_amdgpu_op_INVALID); - - -protected: -// Start of memberFunctionString - AmdgpuVegaInstructionKind p_kind; - -// End of memberFunctionString - -}; - -#endif diff --git a/dataflowAPI/rose/SgAsmArmv8Instruction.h b/dataflowAPI/rose/SgAsmArmv8Instruction.h index eecaec16f9..56aa7ea6c5 100644 --- a/dataflowAPI/rose/SgAsmArmv8Instruction.h +++ b/dataflowAPI/rose/SgAsmArmv8Instruction.h @@ -1,6 +1,7 @@ #ifndef SG_ASM_ARMV8_INSN_H #define SG_ASM_ARMV8_INSN_H +#include #include "external/rose/armv8InstructionEnum.h" #include "typedefs.h" #include "SgAsmInstruction.h" diff --git a/dataflowAPI/rose/SgAsmExpression.h b/dataflowAPI/rose/SgAsmExpression.h index f52d2dd6d6..90f6d5ca52 100644 --- a/dataflowAPI/rose/SgAsmExpression.h +++ b/dataflowAPI/rose/SgAsmExpression.h @@ -7,17 +7,11 @@ #include "SgAsmType.h" #include "external/rose/powerpcInstructionEnum.h" - -#if defined(_MSC_VER) -#include "external/stdint-win.h" -#include "external/inttypes-win.h" -#else - -#include +#include +#include +#include #include -#endif - class SgAsmExpression : public SgAsmNode { public: @@ -58,6 +52,8 @@ class SgAsmExpression : public SgAsmNode { SgAsmExpression(); + SgAsmExpression(const SgAsmExpression&) = default; + protected: std::string p_replacement; @@ -584,6 +580,8 @@ class SgAsmBinaryExpression : public SgAsmExpression { public: virtual ~SgAsmBinaryExpression(); + SgAsmBinaryExpression& operator=(const SgAsmBinaryExpression&) = default; + SgAsmBinaryExpression(const SgAsmBinaryExpression&) = default; public: @@ -1241,7 +1239,7 @@ class SgAsmRegisterReferenceExpression : public SgAsmExpression { protected: // Start of memberFunctionString - SgAsmType *p_type; + SgAsmType *p_type{}; // End of memberFunctionString public: diff --git a/dataflowAPI/rose/SgAsmInstruction.h b/dataflowAPI/rose/SgAsmInstruction.h index 8c3de4f5bb..69d2673091 100644 --- a/dataflowAPI/rose/SgAsmInstruction.h +++ b/dataflowAPI/rose/SgAsmInstruction.h @@ -13,6 +13,7 @@ #include "SgNode.h" #include "SgAsmOperandList.h" +#include #include class SgAsmStatement : public SgAsmNode { diff --git a/dataflowAPI/rose/SgAsmOperandList.h b/dataflowAPI/rose/SgAsmOperandList.h index 81c13a8197..73c3ad871a 100644 --- a/dataflowAPI/rose/SgAsmOperandList.h +++ b/dataflowAPI/rose/SgAsmOperandList.h @@ -2,6 +2,7 @@ #if !defined(SG_ASM_OPERAND_LIST_H) #define SG_ASM_OPERAND_LIST_H +#include #include "SgAsmType.h" #include "typedefs.h" diff --git a/dataflowAPI/rose/SgAsmPowerpcInstruction.h b/dataflowAPI/rose/SgAsmPowerpcInstruction.h index 1c63024503..2189dfd436 100644 --- a/dataflowAPI/rose/SgAsmPowerpcInstruction.h +++ b/dataflowAPI/rose/SgAsmPowerpcInstruction.h @@ -13,6 +13,7 @@ #if !defined(SG_ASM_POWERPC_INSN_H) #define SG_ASM_POWERPC_INSN_H +#include #include "external/rose/rose-compat.h" #include "typedefs.h" #include "external/rose/powerpcInstructionEnum.h" @@ -52,7 +53,7 @@ class SgAsmPowerpcInstruction : public SgAsmInstruction powerpc_unknown_instruction); protected: - rose_addr_t p_address; + rose_addr_t p_address{}; PowerpcInstructionKind p_kind; SgAsmOperandList* p_operandList; std::string p_mnemonic; diff --git a/dataflowAPI/rose/SgAsmType.h b/dataflowAPI/rose/SgAsmType.h index bdc7fd9696..2fb85a31e9 100644 --- a/dataflowAPI/rose/SgAsmType.h +++ b/dataflowAPI/rose/SgAsmType.h @@ -1,6 +1,9 @@ #if !defined(SG_ASM_TYPE_H) #define SG_ASM_TYPE_H +#include +#include +#include #include "SgNode.h" #include "util/Sawyer.h" #include "util/BitVector.h" @@ -31,6 +34,7 @@ class SgAsmNode : public SgNode { public: SgAsmNode(); + SgAsmNode(const SgAsmNode &) = default; }; //TODO: check for other members @@ -62,6 +66,7 @@ class SgAsmType : public SgAsmNode { public: SgAsmType(); + SgAsmType(const SgAsmType &) = default; protected: diff --git a/dataflowAPI/rose/SgAsmx86Instruction.h b/dataflowAPI/rose/SgAsmx86Instruction.h index d4076ab21b..440c0c4d9d 100644 --- a/dataflowAPI/rose/SgAsmx86Instruction.h +++ b/dataflowAPI/rose/SgAsmx86Instruction.h @@ -7,6 +7,8 @@ // All methods that do not appear to be used by x86InstructionSemantics.h // have been commented out. +#include +#include #include "external/rose/rose-compat.h" #include "typedefs.h" #include "SgAsmInstruction.h" diff --git a/dataflowAPI/rose/SgNode.h b/dataflowAPI/rose/SgNode.h index a08c451ff3..de5dcbc7e0 100644 --- a/dataflowAPI/rose/SgNode.h +++ b/dataflowAPI/rose/SgNode.h @@ -10,7 +10,9 @@ class SgNode { /*! \brief returns new style SageIII enum values */ virtual VariantT variantT() const = 0; // MS: new variant used in tree traversal - virtual ~SgNode() {}; + virtual ~SgNode() {} + SgNode() = default; + SgNode(const SgNode&) = default; }; #endif diff --git a/dataflowAPI/rose/conversions.h b/dataflowAPI/rose/conversions.h index 249c05148f..debdcbefb6 100644 --- a/dataflowAPI/rose/conversions.h +++ b/dataflowAPI/rose/conversions.h @@ -1,6 +1,8 @@ #if !defined(ROSE_CONVERSIONS_H) #define ROSE_CONVERSIONS_H +#include + class SgNode; class SgAsmExpression; class SgAsmValueExpression; @@ -57,7 +59,7 @@ class SgAsmScalarType; class SgAsmIntegerType; class SgAsmFloatType; class SgAsmArmv8Instruction; -class SgAsmAmdgpuVegaInstruction; +class SgAsmAMDGPUInstruction; class SgAsmx86Instruction; class SgAsmPowerpcInstruction; @@ -165,8 +167,8 @@ SgAsmPowerpcInstruction* isSgAsmPowerpcInstruction( SgNode *); const SgAsmPowerpcInstruction* isSgAsmPowerpcInstruction( const SgNode * s ); SgAsmArmv8Instruction* isSgAsmArmv8Instruction( SgNode *); const SgAsmArmv8Instruction* isSgAsmArmv8Instruction( const SgNode * s ); -SgAsmAmdgpuVegaInstruction* isSgAsmAmdgpuVegaInstruction( SgNode *); -const SgAsmAmdgpuVegaInstruction* isSgAsmAmdgpuVegaInstruction( const SgNode * s ); +SgAsmAMDGPUInstruction* isSgAsmAMDGPUInstruction( SgNode *); +const SgAsmAMDGPUInstruction* isSgAsmAMDGPUInstruction( const SgNode * s ); SgAsmConstantExpression *isSgAsmConstantExpression( SgNode * ); const SgAsmConstantExpression *isSgAsmConstantExpression( const SgNode *s ); SgAsmIntegerValueExpression *isSgAsmIntegerValueExpression( SgNode * ); diff --git a/dataflowAPI/rose/integerOps.h b/dataflowAPI/rose/integerOps.h index 6b1a40e13e..7985d527f9 100644 --- a/dataflowAPI/rose/integerOps.h +++ b/dataflowAPI/rose/integerOps.h @@ -1,17 +1,19 @@ #ifndef ROSE_INTEGEROPS_H #define ROSE_INTEGEROPS_H +#include +#include #include #include -#include -#include +#include +#include namespace IntegerOpsPrivate { template struct NumBits { - BOOST_STATIC_ASSERT (std::numeric_limits::radix == 2); - BOOST_STATIC_ASSERT (std::numeric_limits::is_integer); + DYN_STATIC_ASSERT (std::numeric_limits::radix == 2); + DYN_STATIC_ASSERT (std::numeric_limits::is_integer); static const size_t value = std::numeric_limits::digits; }; @@ -300,15 +302,15 @@ namespace IntegerOps { /** Optionally returns the zero-origin position of the most significant set bit. Returns nothing if no bits are set. */ template - inline boost::optional msb_set(T val) + inline dyncompat::optional msb_set(T val) { if (val!=0) { for (size_t bitno = 8*sizeof(T); bitno>0; --bitno) { if (0 != (val & shl1(bitno-1))) - return boost::optional(bitno-1); + return dyncompat::optional(bitno-1); } } - return boost::optional(); + return dyncompat::optional(); } } // namespace diff --git a/dataflowAPI/rose/rangemap.h b/dataflowAPI/rose/rangemap.h index aa8a5c160c..e665e93c47 100644 --- a/dataflowAPI/rose/rangemap.h +++ b/dataflowAPI/rose/rangemap.h @@ -18,6 +18,8 @@ #ifndef __STDC_FORMAT_MACROS #define __STDC_FORMAT_MACROS #endif +#include +#include #include #include @@ -581,7 +583,7 @@ class RangeMapVoid { * copying and then deleting other_value. * * Returns true if merging occurred, false otherwise. */ - bool merge(const Range &my_range, const Range &other_range, const RangeMapVoid &other_value) { + bool merge(const Range &my_range, const Range &other_range, const RangeMapVoid &/*other_value*/) { assert(!my_range.empty() && !other_range.empty()); return true; } @@ -595,7 +597,7 @@ class RangeMapVoid { return RangeMapVoid(); } - void print(std::ostream &o) const {} + void print(std::ostream &/*o*/) const {} friend std::ostream& operator<<(std::ostream &o, const RangeMapVoid &x) { x.print(o); return o; diff --git a/dataflowAPI/rose/rose.h b/dataflowAPI/rose/rose.h index 0dcc26d94b..5fb6e94ca8 100644 --- a/dataflowAPI/rose/rose.h +++ b/dataflowAPI/rose/rose.h @@ -1,6 +1,7 @@ #if !defined(ROSE_H) #define ROSE_H +#include #define ROSE_ASSERT assert #endif diff --git a/dataflowAPI/rose/semantics/BaseSemantics2.C b/dataflowAPI/rose/semantics/BaseSemantics2.C index 52a6968633..3a17a7f527 100644 --- a/dataflowAPI/rose/semantics/BaseSemantics2.C +++ b/dataflowAPI/rose/semantics/BaseSemantics2.C @@ -1,3 +1,4 @@ +#include #include "../util/StringUtility.h" //#include "sage3basic.h" #include "BaseSemantics2.h" @@ -433,7 +434,7 @@ Dispatcher::advanceInstructionPointer(SgAsmInstruction *insn) { BaseSemantics::SValuePtr ipValue; if (!autoResetInstructionPointer_ && operators->currentState() && operators->currentState()->registerState()) { BaseSemantics::RegisterStateGenericPtr grState = - boost::dynamic_pointer_cast(operators->currentState()->registerState()); + dyncompat::dynamic_pointer_cast(operators->currentState()->registerState()); if (grState && grState->is_partly_stored(ipReg)) ipValue = operators->readRegister(ipReg); } diff --git a/dataflowAPI/rose/semantics/BaseSemantics2.h b/dataflowAPI/rose/semantics/BaseSemantics2.h index 04b0b75083..a4539a034f 100644 --- a/dataflowAPI/rose/semantics/BaseSemantics2.h +++ b/dataflowAPI/rose/semantics/BaseSemantics2.h @@ -7,9 +7,14 @@ #include "../conversions.h" #include "SMTSolver.h" -#include -#include -#include +#include +#include +#include +#include +#include +#include +#include +#include #include "../SgAsmInstruction.h" #include "../SgAsmExpression.h" #include "../util/Assert.h" @@ -81,7 +86,7 @@ namespace rose { * * Most of the instruction semantics components have abstract base classes. Instances of concrete subclasses thereof are * passed around by pointers, and in order to simplify memory management issues, those objects are reference counted. Most - * objects use boost::shared_ptr, but SValue objects use a faster custom smart pointer (it also uses a custom + * objects use dyncompat::shared_ptr, but SValue objects use a faster custom smart pointer (it also uses a custom * allocator, and testing showed a substantial speed improvement over Boost when compiled with GCC's "-O3" switch). In any * case, to alleviate the user from having to remember which kind of objects use which smart pointer implementation, pointer * typedefs are created for each class—their names are the same as the class but suffixed with "Ptr". Users will almost @@ -161,7 +166,7 @@ namespace rose { * * @code * // Smart pointer for the subclass - * typedef boost::shared_ptr MyThingPtr; + * typedef dyncompat::shared_ptr MyThingPtr; * * // Class derived from OtherThing, which eventually derives from a class * // defined in BinarySemantics::InstructionSemantics2::BaseSemantics--lets @@ -219,7 +224,7 @@ namespace rose { * // Define the checking dynamic pointer cast. * public: * static MyThingPtr promomte(const BaseSemantics::ThingPtr &obj) { - * MyThingPtr retval = boost::dynamic_pointer_cast(obj); + * MyThingPtr retval = dyncompat::dynamic_pointer_cast(obj); * assert(retval!=NULL); * return NULL; * } @@ -416,7 +421,7 @@ namespace rose { Formatter &fmt; std::string old_line_prefix; public: - Indent(Formatter &fmt) : fmt(fmt) { + Indent(Formatter &fmt_) : fmt(fmt_) { old_line_prefix = fmt.get_line_prefix(); fmt.set_line_prefix(old_line_prefix + fmt.get_indentation_suffix()); } @@ -461,16 +466,16 @@ namespace rose { public: SgAsmInstruction *insn; - Exception(const std::string &mesg, SgAsmInstruction *insn) : std::runtime_error(mesg), - insn(insn) { } + Exception(const std::string &mesg, SgAsmInstruction *insn_) : std::runtime_error(mesg), + insn(insn_) { } void print(std::ostream &) const; }; class NotImplemented : public Exception { public: - NotImplemented(const std::string &mesg, SgAsmInstruction *insn) - : Exception(mesg, insn) { } + NotImplemented(const std::string &mesg, SgAsmInstruction *insn_) + : Exception(mesg, insn_) { } }; @@ -553,7 +558,7 @@ namespace rose { // Normal, protected, C++ constructors protected: explicit SValue(size_t nbits) : width(nbits) { } // hot - SValue(const SValue &other) : width(other.width) { } + SValue(const SValue &other) : SharedObject(other), width(other.width) { } public: /** Shared-ownership pointer for an @ref SValue object. See @ref heap_object_shared_ownership. */ @@ -723,7 +728,7 @@ namespace rose { SValuePtr obj; Formatter &fmt; public: - WithFormatter(const SValuePtr &svalue, Formatter &fmt) : obj(svalue), fmt(fmt) { } + WithFormatter(const SValuePtr &svalue, Formatter &fmt_) : obj(svalue), fmt(fmt_) { } void print(std::ostream &stream) const { obj->print(stream, fmt); } }; @@ -758,12 +763,12 @@ namespace rose { //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// /** Shared-ownership pointer to a register state. See @ref heap_object_shared_ownership. */ - typedef boost::shared_ptr RegisterStatePtr; + typedef dyncompat::shared_ptr RegisterStatePtr; /** The set of all registers and their values. RegisterState objects are allocated on the heap and reference counted. The * BaseSemantics::RegisterState is an abstract class that defines the interface. See the * rose::BinaryAnalysis::InstructionSemantics2 namespace for an overview of how the parts fit together.*/ - class RegisterState : public boost::enable_shared_from_this { + class RegisterState : public dyncompat::enable_shared_from_this { private: MergerPtr merger_; SValuePtr protoval_; /**< Prototypical value for virtual constructors. */ @@ -774,8 +779,8 @@ namespace rose { //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// // Real constructors protected: - RegisterState(const SValuePtr &protoval, const RegisterDictionary *regdict) - : protoval_(protoval), regdict(regdict) { + RegisterState(const SValuePtr &protoval, const RegisterDictionary *regdict_) + : protoval_(protoval), regdict(regdict_) { ASSERT_not_null(protoval_); } @@ -906,7 +911,7 @@ namespace rose { RegisterStatePtr obj; Formatter &fmt; public: - WithFormatter(const RegisterStatePtr &obj, Formatter &fmt) : obj(obj), fmt(fmt) { } + WithFormatter(const RegisterStatePtr &obj_, Formatter &fmt_) : obj(obj_), fmt(fmt_) { } void print(std::ostream &stream) const { obj->print(stream, fmt); } }; @@ -931,12 +936,12 @@ namespace rose { //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// /** Shared-ownership pointer to a memory state. See @ref heap_object_shared_ownership. */ - typedef boost::shared_ptr MemoryStatePtr; + typedef dyncompat::shared_ptr MemoryStatePtr; /** Represents all memory in the state. MemoryState objects are allocated on the heap and reference counted. The * BaseSemantics::MemoryState is an abstract class that defines the interface. See the * rose::BinaryAnalysis::InstructionSemantics2 namespace for an overview of how the parts fit together.*/ - class MemoryState : public boost::enable_shared_from_this { + class MemoryState : public dyncompat::enable_shared_from_this { SValuePtr addrProtoval_; /**< Prototypical value for addresses. */ SValuePtr valProtoval_; @@ -1105,7 +1110,7 @@ namespace rose { MemoryStatePtr obj; Formatter &fmt; public: - WithFormatter(const MemoryStatePtr &obj, Formatter &fmt) : obj(obj), fmt(fmt) { } + WithFormatter(const MemoryStatePtr &obj_, Formatter &fmt_) : obj(obj_), fmt(fmt_) { } void print(std::ostream &stream) const { obj->print(stream, fmt); } }; @@ -1130,7 +1135,7 @@ namespace rose { //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// /** Shared-ownership pointer to a semantic state. See @ref heap_object_shared_ownership. */ - typedef boost::shared_ptr StatePtr; + typedef dyncompat::shared_ptr StatePtr; /** Base class for semantics machine states. * @@ -1148,7 +1153,7 @@ namespace rose { * State objects are allocated on the heap and reference counted. The BaseSemantics::State is an abstract class that defines * the interface. See the rose::BinaryAnalysis::InstructionSemantics2 namespace for an overview of how the parts fit * together. */ - class State : public boost::enable_shared_from_this { + class State : public dyncompat::enable_shared_from_this { SValuePtr protoval_; // Initial value used to create additional values as needed. RegisterStatePtr registers_; // All machine register values for this semantic state. MemoryStatePtr memory_; // All memory for this semantic state. @@ -1167,7 +1172,8 @@ namespace rose { // deep-copy the registers and memory State(const State &other) - : protoval_(other.protoval_) { + : dyncompat::enable_shared_from_this(other), + protoval_(other.protoval_) { registers_ = other.registers_->clone(); memory_ = other.memory_->clone(); } @@ -1204,7 +1210,7 @@ namespace rose { * objects because many analyses depend on being able to make a copy of the entire semantic state at each machine * instruction, at each CFG vertex, etc. */ virtual StatePtr clone() const { - StatePtr self = boost::const_pointer_cast(shared_from_this()); + StatePtr self = dyncompat::const_pointer_cast(shared_from_this()); return instance(self); } @@ -1344,7 +1350,7 @@ namespace rose { StatePtr obj; Formatter &fmt; public: - WithFormatter(const StatePtr &obj, Formatter &fmt) : obj(obj), fmt(fmt) { } + WithFormatter(const StatePtr &obj_, Formatter &fmt_) : obj(obj_), fmt(fmt_) { } void print(std::ostream &stream) const { obj->print(stream, fmt); } }; @@ -1376,7 +1382,7 @@ namespace rose { //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// /** Shared-ownership pointer to a RISC operators object. See @ref heap_object_shared_ownership. */ - typedef boost::shared_ptr RiscOperatorsPtr; + typedef dyncompat::shared_ptr RiscOperatorsPtr; /** Base class for most instruction semantics RISC operators. * @@ -1398,7 +1404,7 @@ namespace rose { * RiscOperator objects are allocated on the heap and reference counted. The BaseSemantics::RiscOperator is an abstract class * that defines the interface. See the rose::BinaryAnalysis::InstructionSemantics2 namespace for an overview of how the parts * fit together. */ - class RiscOperators : public boost::enable_shared_from_this { + class RiscOperators : public dyncompat::enable_shared_from_this { SValuePtr protoval_; // Prototypical value used for its virtual constructors StatePtr currentState_; // State upon which RISC operators operate StatePtr initialState_; // Lazily updated initial state; see readMemory @@ -1586,7 +1592,7 @@ namespace rose { RiscOperatorsPtr obj; Formatter &fmt; public: - WithFormatter(const RiscOperatorsPtr &obj, Formatter &fmt) : obj(obj), fmt(fmt) { } + WithFormatter(const RiscOperatorsPtr &obj_, Formatter &fmt_) : obj(obj_), fmt(fmt_) { } void print(std::ostream &stream) const { obj->print(stream, fmt); } }; @@ -1641,7 +1647,7 @@ namespace rose { ASSERT_not_null(insn); ASSERT_require(currentInsn_ == insn); currentInsn_ = NULL; - }; + } //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// @@ -2087,7 +2093,7 @@ namespace rose { //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// /** Shared-ownership pointer to a semantics instruction dispatcher. See @ref heap_object_shared_ownership. */ - typedef boost::shared_ptr DispatcherPtr; + typedef dyncompat::shared_ptr DispatcherPtr; /** Functor that knows how to dispatch a single kind of instruction. */ class InsnProcessor { @@ -2110,7 +2116,7 @@ namespace rose { * Dispatcher objects are allocated on the heap and reference counted. The BaseSemantics::Dispatcher is an abstract class * that defines the interface. See the rose::BinaryAnalysis::InstructionSemantics2 namespace for an overview of how the parts * fit together. */ - class Dispatcher : public boost::enable_shared_from_this { + class Dispatcher : public dyncompat::enable_shared_from_this { protected: RiscOperatorsPtr operators; const RegisterDictionary *regdict; @@ -2262,8 +2268,8 @@ namespace rose { return regdict; } - virtual void set_register_dictionary(const RegisterDictionary *regdict) { - this->regdict = regdict; + virtual void set_register_dictionary(const RegisterDictionary *regdict_) { + this->regdict = regdict_; } /** @} */ diff --git a/dataflowAPI/rose/semantics/BinarySymbolicExpr.C b/dataflowAPI/rose/semantics/BinarySymbolicExpr.C index 380dcedf07..32fc0d5c93 100644 --- a/dataflowAPI/rose/semantics/BinarySymbolicExpr.C +++ b/dataflowAPI/rose/semantics/BinarySymbolicExpr.C @@ -1,6 +1,7 @@ #define __STDC_LIMIT_MACROS //#include "sage3basic.h" +#include #include "../util/StringUtility.h" #include "BinarySymbolicExpr.h" @@ -9,9 +10,9 @@ #include "../integerOps.h" #include "../util/Combinatorics.h" -#include -#include -#include +#include +#include +#include namespace rose { namespace BinaryAnalysis { @@ -22,15 +23,15 @@ namespace SymbolicExpr { //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// // A mutex that's used by various methods in this namespace -static boost::mutex symbolicExprMutex; +static dyncompat::mutex symbolicExprMutex; // Returns the next name counter. If @p useThis is specified then return that value and make sure the next value to be // returned is larger. static uint64_t nextNameCounter(uint64_t useThis = (uint64_t)(-1)) { - static boost::mutex mutex; + static dyncompat::mutex mutex; static uint64_t counter = 0; - boost::lock_guard lock(mutex); + dyncompat::lock_guard lock(mutex); if (useThis == (uint64_t)(-1)) return ++counter; counter = std::max(counter, useThis); @@ -83,7 +84,7 @@ escapeCharacter(char ch) { static std::string nameEscape(const std::string &s) { std::string retval; - BOOST_FOREACH (char ch, s) { + DYN_FOREACH (char ch, s) { switch (ch) { case '(': case ')': @@ -110,7 +111,7 @@ commentEscape(const std::string &s) { // leave that as an exercise for the reader. ;-) bool escapeAngleBrackets = false; int angleBracketDepth = 0; - BOOST_FOREACH (char ch, s) { + DYN_FOREACH (char ch, s) { if ('<' == ch) { ++angleBracketDepth; } else if ('>' == ch && --angleBracketDepth < 0) { @@ -119,7 +120,7 @@ commentEscape(const std::string &s) { } } - BOOST_FOREACH (char ch, s) { + DYN_FOREACH (char ch, s) { switch (ch) { case '<': case '>': @@ -232,7 +233,7 @@ struct Hasher: Visitor { InteriorPtr inode = node->isInteriorNode(); ASSERT_not_null(inode); h = hash(h, inode->getOperator()); - BOOST_FOREACH (const Ptr &child, inode->children()) { + DYN_FOREACH (const Ptr &child, inode->children()) { ASSERT_require(child->isHashed()); h = hash(h, child->hash()); } @@ -261,13 +262,13 @@ Node::hash() { Hasher hasher; depthFirstTraversal(hasher); } - boost::unique_lock lock(symbolicExprMutex); + dyncompat::unique_lock lock(symbolicExprMutex); return hashval_; } void Node::hash(uint64_t h) { - boost::unique_lock lock(symbolicExprMutex); + dyncompat::unique_lock lock(symbolicExprMutex); hashval_ = h; } @@ -417,7 +418,7 @@ Interior::adjustWidth() { } case OP_CONCAT: { size_t totalWidth = 0; - BOOST_FOREACH (const Ptr &child, children_) { + DYN_FOREACH (const Ptr &child, children_) { if (!child->isScalar()) throw Exception(toStr(op_) + " operator's arguments must be scalar"); totalWidth += child->nBits(); @@ -595,7 +596,7 @@ Interior::adjustWidth() { void Interior::adjustBitFlags(unsigned flags) { flags_ = flags; - BOOST_FOREACH (const Ptr &child, children_) + DYN_FOREACH (const Ptr &child, children_) flags_ |= child->flags(); } @@ -1384,7 +1385,8 @@ ExtractSimplifier::rewrite(Interior *inode) const { if (from_node && to_node && from_node->isNumber() && to_node->isNumber() && ioperand && OP_CONCAT==ioperand->getOperator()) { size_t partAt = 0; // starting bit number in child - BOOST_REVERSE_FOREACH (const Ptr part, ioperand->children()) { // concatenated parts + for (auto it = ioperand->children().rbegin(); it != ioperand->children().rend(); ++it) { // concatenated parts + const Ptr part = *it; size_t partEnd = partAt + part->nBits(); if (partEnd <= from) { // Part is entirely left of what we need @@ -1976,9 +1978,9 @@ SetSimplifier::rewrite(Interior *inode) const { // Remove duplicate arguments bool removedDuplicate = false; Nodes elements; - BOOST_FOREACH (const Ptr &elmt1, inode->children()) { + DYN_FOREACH (const Ptr &elmt1, inode->children()) { bool isDuplicate = false; - BOOST_FOREACH (const Ptr &elmt2, elements) { + DYN_FOREACH (const Ptr &elmt2, elements) { if (elmt1->mustEqual(elmt2, solver)) { isDuplicate = true; break; diff --git a/dataflowAPI/rose/semantics/BinarySymbolicExpr.h b/dataflowAPI/rose/semantics/BinarySymbolicExpr.h index 2f6101355a..371179bdd4 100644 --- a/dataflowAPI/rose/semantics/BinarySymbolicExpr.h +++ b/dataflowAPI/rose/semantics/BinarySymbolicExpr.h @@ -7,8 +7,11 @@ #include "../util/Map.h" +#include +#include +#include #include -#include +#include #include #include "../util/Attribute.h" #include "../util/BitVector.h" @@ -267,7 +270,7 @@ namespace rose { /**< Optional comment. Only for debugging; not significant for any calculation. */ uint64_t hashval_; /**< Optional hash used as a quick way to indicate that two expressions are different. */ - boost::any userData_; /**< Additional user-specified data. This is not part of the hash. */ + dyncompat::any userData_; /**< Additional user-specified data. This is not part of the hash. */ public: // Bit flags @@ -398,11 +401,11 @@ namespace rose { * expressions. * * @{ */ - void userData(boost::any &data) { + void userData(dyncompat::any &data) { userData_ = data; } - const boost::any &userData() { + const dyncompat::any &userData() { return userData_; } /** @} */ @@ -533,7 +536,7 @@ namespace rose { Ptr node; Formatter &formatter; public: - WithFormatter(const Ptr &node, Formatter &formatter) : node(node), formatter(formatter) { } + WithFormatter(const Ptr &node_, Formatter &formatter_) : node(node_), formatter(formatter_) { } void print(std::ostream &stream) const { node->print(stream, formatter); } }; @@ -764,19 +767,19 @@ namespace rose { struct ShiftSimplifier : Simplifier { bool newbits; - ShiftSimplifier(bool newbits) : newbits(newbits) { } + ShiftSimplifier(bool newbits_) : newbits(newbits_) { } Ptr combine_strengths(Ptr strength1, Ptr strength2, size_t value_width) const; }; struct ShlSimplifier : ShiftSimplifier { - ShlSimplifier(bool newbits) : ShiftSimplifier(newbits) { } + ShlSimplifier(bool newbits_) : ShiftSimplifier(newbits_) { } virtual Ptr rewrite(Interior *) const; }; struct ShrSimplifier : ShiftSimplifier { - ShrSimplifier(bool newbits) : ShiftSimplifier(newbits) { } + ShrSimplifier(bool newbits_) : ShiftSimplifier(newbits_) { } virtual Ptr rewrite(Interior *) const; }; @@ -1343,7 +1346,7 @@ namespace rose { } } - VisitAction postVisit(const Ptr &node) { + VisitAction postVisit(const Ptr &/*node*/) { return CONTINUE; } } visitor; diff --git a/dataflowAPI/rose/semantics/ByteOrder.h b/dataflowAPI/rose/semantics/ByteOrder.h index 5ef5315f99..27392594d7 100644 --- a/dataflowAPI/rose/semantics/ByteOrder.h +++ b/dataflowAPI/rose/semantics/ByteOrder.h @@ -1,6 +1,8 @@ #ifndef ROSE_ByteOrder_H #define ROSE_ByteOrder_H +#include +#include #include "../typedefs.h" namespace ByteOrder { diff --git a/dataflowAPI/rose/semantics/ConcreteSemantics2.C b/dataflowAPI/rose/semantics/ConcreteSemantics2.C index 00afbdcbe2..f986913b56 100644 --- a/dataflowAPI/rose/semantics/ConcreteSemantics2.C +++ b/dataflowAPI/rose/semantics/ConcreteSemantics2.C @@ -1,3 +1,4 @@ +#include #include "../util/StringUtility.h" //#include "sage3basic.h" #include "ConcreteSemantics2.h" diff --git a/dataflowAPI/rose/semantics/ConcreteSemantics2.h b/dataflowAPI/rose/semantics/ConcreteSemantics2.h index db351d229d..b137f2ceb1 100644 --- a/dataflowAPI/rose/semantics/ConcreteSemantics2.h +++ b/dataflowAPI/rose/semantics/ConcreteSemantics2.h @@ -5,6 +5,8 @@ #define __STDC_FORMAT_MACROS #endif +#include +#include #include #include "../integerOps.h" @@ -166,7 +168,7 @@ namespace rose { //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// /** Shared-ownership pointer to a concrete memory state. See @ref heap_object_shared_ownership. */ - typedef boost::shared_ptr MemoryStatePtr; + typedef dyncompat::shared_ptr MemoryStatePtr; /** Byte-addressable memory. * @@ -188,7 +190,7 @@ namespace rose { MemoryState(const MemoryState &other) : BaseSemantics::MemoryState(other), map_(other.map_), pageSize_(other.pageSize_) { - BOOST_FOREACH(MemoryMap::Segment & segment, map_.values()) + DYN_FOREACH(MemoryMap::Segment & segment, map_.values()) segment.buffer()->copyOnWrite(true); } @@ -240,7 +242,7 @@ namespace rose { /** Recasts a base pointer to a concrete memory state. This is a checked cast that will fail if the specified pointer does * not have a run-time type that is a ConcreteSemantics::MemoryState or subclass thereof. */ static MemoryStatePtr promote(const BaseSemantics::MemoryStatePtr &x) { - MemoryStatePtr retval = boost::dynamic_pointer_cast(x); + MemoryStatePtr retval = dyncompat::dynamic_pointer_cast(x); ASSERT_not_null(retval); return retval; } @@ -314,7 +316,7 @@ namespace rose { //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// /** Shared-ownership pointer to concrete RISC operations. See @ref heap_object_shared_ownership. */ - typedef boost::shared_ptr RiscOperatorsPtr; + typedef dyncompat::shared_ptr RiscOperatorsPtr; /** Defines RISC operators for the ConcreteSemantics domain. * @@ -396,7 +398,7 @@ namespace rose { /** Run-time promotion of a base RiscOperators pointer to concrete operators. This is a checked conversion--it * will fail if @p x does not point to a ConcreteSemantics::RiscOperators object. */ static RiscOperatorsPtr promote(const BaseSemantics::RiscOperatorsPtr &x) { - RiscOperatorsPtr retval = boost::dynamic_pointer_cast(x); + RiscOperatorsPtr retval = dyncompat::dynamic_pointer_cast(x); ASSERT_not_null(retval); return retval; } diff --git a/dataflowAPI/rose/semantics/DispatcherAMDGPU.C b/dataflowAPI/rose/semantics/DispatcherAMDGPU.C new file mode 100644 index 0000000000..78d7e2b547 --- /dev/null +++ b/dataflowAPI/rose/semantics/DispatcherAMDGPU.C @@ -0,0 +1,312 @@ +#include "../util/StringUtility.h" +//#include "sage3basic.h" +#include "BaseSemantics2.h" +//#include "Diagnostics.h" +#include "DispatcherAMDGPU.h" +#include "../integerOps.h" +#include "SymEvalSemantics.h" + +#include "../SgAsmExpression.h" +#include "../conversions.h" + +#undef si_value // name pollution from siginfo.h + +namespace rose { + namespace BinaryAnalysis { + namespace InstructionSemantics2 { + +/******************************************************************************************************************************* + * Support functions + *******************************************************************************************************************************/ + + static inline size_t asm_type_width(SgAsmType *ty) { + ASSERT_not_null(ty); + return ty->get_nBits(); + } + +/******************************************************************************************************************************* + * Base AMDGPU instruction processor + *******************************************************************************************************************************/ + namespace AMDGPU { + + void + InsnProcessor::process(const BaseSemantics::DispatcherPtr &dispatcher_, SgAsmInstruction *insn_) { + DispatcherAMDGPUPtr dispatcher = DispatcherAMDGPU::promote(dispatcher_); + BaseSemantics::RiscOperatorsPtr operators = dispatcher->get_operators(); + SgAsmAMDGPUInstruction *insn = isSgAsmAMDGPUInstruction(insn_); + ASSERT_require(insn != NULL && insn == operators->currentInstruction()); + dispatcher->advanceInstructionPointer(insn); + SgAsmExpressionPtrList &operands = insn->get_operandList()->get_operands(); + //check_arg_width(dispatcher.get(), insn, operands); + + uint32_t raw = 0; + std::vector rawBytes = insn->get_raw_bytes(); + for (int idx = 0; idx < rawBytes.size(); idx++) { + raw |= (rawBytes[idx] << (8 * idx)); + } + p(dispatcher.get(), operators.get(), insn, operands, raw); + } + + void + InsnProcessor::assert_args(I insn, A args, size_t nargs) { + if (args.size() != nargs) { + std::string mesg = "instruction has incorrect number of args"; + throw BaseSemantics::Exception(mesg, insn); + } + } + +/******************************************************************************************************************************* + * Functors that handle individual AMDGPU instructions kinds + *******************************************************************************************************************************/ + typedef InsnProcessor P; + struct IP_s_add_u32 : P { + void p(D d, Ops ops, I insn, A args, B raw) { + + BaseSemantics::SValuePtr src1; + BaseSemantics::SValuePtr src0; + if(SgAsmIntegerValueExpression * ival = isSgAsmIntegerValueExpression(args[1])){ + src1 = ops->number_(64, ival->get_value()); + }else{ + src1 = ops->unsignedExtend(d->read(args[1]),64); + } + if(SgAsmIntegerValueExpression * ival = isSgAsmIntegerValueExpression(args[2])){ + src0 = ops->number_(64, ival->get_value()); + }else{ + src0 = ops->unsignedExtend(d->read(args[2]),64); + } + + + BaseSemantics::SValuePtr result; + BaseSemantics::SValuePtr n, z, c, v; + + result = d->doAddOperation( src0 , src1 ,false,ops->boolean_(false),n,z,c,v); + + BaseSemantics::SValuePtr scc_value; + + scc_value = ops->ite( + ops->isUnsignedGreaterThanOrEqual(result,ops->number_(64,0x100000000)), + ops->number_(1,1), + ops->number_(1,0)); + + d->writeRegister(d->REG_SCC,scc_value); + + d->write(args[0],ops->extract(result,0,32)); + //d->writeRegister(d->REG_SCC,c); + } + }; + struct IP_s_addc_u32 : P { + void p(D d, Ops ops, I insn, A args, B raw) { + + BaseSemantics::SValuePtr src1; + BaseSemantics::SValuePtr src0; + + if(SgAsmIntegerValueExpression * ival = isSgAsmIntegerValueExpression(args[1])){ + src1 = ops->number_(64, ival->get_value()); + + }else{ + src1 = ops->unsignedExtend(d->read(args[1]),64); + } + if(SgAsmIntegerValueExpression * ival = isSgAsmIntegerValueExpression(args[2])){ + src0 = ops->number_(64, ival->get_value()); + }else{ + src0 = ops->unsignedExtend(d->read(args[2]),64); + } + + + BaseSemantics::SValuePtr result; + BaseSemantics::SValuePtr n, z, c, v; + BaseSemantics::SValuePtr old_scc = d->readRegister(d->REG_SCC); + result = d->doAddOperation( src0 , src1 ,false, + d->readRegister(d->REG_SCC) + ,n,z,c,v); + + + + d->write(args[0],ops->extract(result,0,32)); + d->writeRegister(d->REG_SCC,c); + + } + }; + + struct IP_s_getpc_b64 : P { + void p(D d, Ops ops, I insn, A args, B raw) { + + SgAsmIntegerValueExpression *ival = isSgAsmIntegerValueExpression(args[2]); + BaseSemantics::SValuePtr result = ops->number_(ival->get_significantBits(), ival->get_value()); + BaseSemantics::SValuePtr lowPC = ops->extract(result,0,32); + BaseSemantics::SValuePtr highPC = ops->shiftRight(result,ops->number_(32,32)); + + d->write(args[0],lowPC); + d->write(args[1],highPC); + } + }; + + struct IP_s_setpc_b64 : P { + void p(D d, Ops ops, I insn, A args, B raw) { + BaseSemantics::SValuePtr result; + BaseSemantics::SValuePtr lowPC = ops->extract(d->read(args[0]),0,32); + BaseSemantics::SValuePtr highPC = d->ZeroExtend(d->read(args[1]),64); + BaseSemantics::SValuePtr n, z, c, v; + result = d->doAddOperation( ops->shiftLeft(highPC, ops->number_(32,32)) , lowPC,false,ops->boolean_(false),n,z,c,v); + d->writeRegister(d->REG_PC, result); + } + }; + struct IP_s_swappc_b64 : P { + + void p(D d, Ops ops, I insn, A args, B raw) { + BaseSemantics::SValuePtr result = d->readRegister(d->REG_PC); + BaseSemantics::SValuePtr storelowPC = result; + BaseSemantics::SValuePtr storehighPC = ops->shiftRight(result,ops->number_(32,32)); + + d->write(args[0],storelowPC); + d->write(args[1],storehighPC); + + BaseSemantics::SValuePtr n, z, c, v; + BaseSemantics::SValuePtr lowPC = ops->extract(d->read(args[2]),0,32); + BaseSemantics::SValuePtr highPC = d->ZeroExtend(d->read(args[3]),64); + result = d->doAddOperation( ops->shiftLeft(highPC, ops->number_(32,32)) , lowPC,false,ops->boolean_(false),n,z,c,v); + d->writeRegister(d->REG_PC, result); + } + + }; + + + } // namespace + +/******************************************************************************************************************************* + * DispatcherAMDGPU + *******************************************************************************************************************************/ + + void + DispatcherAMDGPU::iproc_init() { + + iproc_set(rose_amdgpu_op_s_getpc_b64, new AMDGPU::IP_s_getpc_b64); + iproc_set(rose_amdgpu_op_s_setpc_b64, new AMDGPU::IP_s_setpc_b64); + iproc_set(rose_amdgpu_op_s_swappc_b64, new AMDGPU::IP_s_swappc_b64); + iproc_set(rose_amdgpu_op_s_add_u32, new AMDGPU::IP_s_add_u32); + iproc_set(rose_amdgpu_op_s_addc_u32, new AMDGPU::IP_s_addc_u32); + } + + void + DispatcherAMDGPU::regcache_init() { + if (regdict) { + REG_PC = findRegister("pc_all", 64); + REG_SCC = findRegister("src_scc", 1); + } + } + + void + DispatcherAMDGPU::memory_init() { + if (BaseSemantics::StatePtr state = currentState()) { + if (BaseSemantics::MemoryStatePtr memory = state->memoryState()) { + switch (memory->get_byteOrder()) { + case ByteOrder::ORDER_LSB: + break; + case ByteOrder::ORDER_MSB: + break; + case ByteOrder::ORDER_UNSPECIFIED: + memory->set_byteOrder(ByteOrder::ORDER_LSB); + break; + } + } + } + } + + RegisterDescriptor + DispatcherAMDGPU::instructionPointerRegister() const { + return REG_PC; + } + + RegisterDescriptor + DispatcherAMDGPU::stackPointerRegister() const { + assert(0 && "not implemented"); + return REG_SCC; + } + + void + DispatcherAMDGPU::set_register_dictionary(const RegisterDictionary *regdict) { + BaseSemantics::Dispatcher::set_register_dictionary(regdict); + regcache_init(); + } + + void + DispatcherAMDGPU::setFlagsForResult(const BaseSemantics::SValuePtr &result, + const BaseSemantics::SValuePtr &carries, + bool invertCarries, size_t nbits, + BaseSemantics::SValuePtr &n, BaseSemantics::SValuePtr &z, + BaseSemantics::SValuePtr &c, BaseSemantics::SValuePtr &v) { + size_t width = result->get_width(); + + n = operators->extract(result, width - 1, width); + z = operators->equalToZero(result); + + BaseSemantics::SValuePtr sign = operators->extract(carries, nbits - 1, nbits); + BaseSemantics::SValuePtr ofbit = operators->extract(carries, nbits - 2, nbits - 1); + c = invertMaybe(sign, invertCarries); + v = operators->xor_(sign, ofbit); + } + + BaseSemantics::SValuePtr + DispatcherAMDGPU::invertMaybe(const BaseSemantics::SValuePtr &value, bool maybe) { + return maybe ? operators->invert(value) : value; + } + + BaseSemantics::SValuePtr + DispatcherAMDGPU::SignExtend(const BaseSemantics::SValuePtr &expr, size_t newsize) { + ASSERT_require(newsize > 0); + return operators->signExtend(expr, newsize); + } + + BaseSemantics::SValuePtr + DispatcherAMDGPU::ZeroExtend(const BaseSemantics::SValuePtr &expr, size_t newsize) { + ASSERT_require(newsize > 0); + return operators->unsignedExtend(expr, newsize); + } + + BaseSemantics::SValuePtr + DispatcherAMDGPU::doAddOperation(BaseSemantics::SValuePtr a, BaseSemantics::SValuePtr b, + bool invertCarries, const BaseSemantics::SValuePtr &carryIn, + BaseSemantics::SValuePtr &n, BaseSemantics::SValuePtr &z, + BaseSemantics::SValuePtr &c, BaseSemantics::SValuePtr &v) { + if (a->get_width() > b->get_width()) { + b = operators->signExtend(b, a->get_width()); + } else if (a->get_width() < b->get_width()) { + a = operators->signExtend(a, b->get_width()); + } + + ASSERT_require(1 == carryIn->get_width()); + size_t nbits = a->get_width(); + BaseSemantics::SValuePtr carries; + BaseSemantics::SValuePtr result = operators->addWithCarries(a, b, + invertMaybe(carryIn, invertCarries), + carries/*out*/); + setFlagsForResult(result, carries, invertCarries, a->get_width(), n, z, c, v); + return result; + } + + BaseSemantics::SValuePtr + DispatcherAMDGPU::readRegister(const RegisterDescriptor ®) { + return operators->readRegister(reg); + } + + void + DispatcherAMDGPU::writeRegister(const RegisterDescriptor ®, const BaseSemantics::SValuePtr &value) { + operators->writeRegister(reg, value); + } + + void + DispatcherAMDGPU::write(SgAsmExpression *e, const BaseSemantics::SValuePtr &value, + size_t addr_nbits/*=0*/) { + if (SgAsmDirectRegisterExpression *re = isSgAsmDirectRegisterExpression(e)) { + writeRegister(re->get_descriptor(), value); + } else { + Dispatcher::write(e, value, addr_nbits); // defer to super class + } + } + + } // namespace + } // namespace +} // namespace + +//using namespace rose::Diagnostics; + diff --git a/dataflowAPI/rose/semantics/DispatcherAMDGPU.h b/dataflowAPI/rose/semantics/DispatcherAMDGPU.h new file mode 100644 index 0000000000..c61006ea99 --- /dev/null +++ b/dataflowAPI/rose/semantics/DispatcherAMDGPU.h @@ -0,0 +1,196 @@ +#ifndef ROSE_DispatcherAMDGPU_H +#define ROSE_DispatcherAMDGPU_H + +#include +#include +#include +#include "BaseSemantics2.h" +#include "../SgAsmAMDGPUInstruction.h" +#include "external/rose/amdgpuInstructionEnum.h" + + + +namespace rose { + namespace BinaryAnalysis { + namespace InstructionSemantics2 { + +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// Dispatcher +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + +/** Shared-ownership pointer to an AMDGPU instruction dispatcher. See @ref heap_object_shared_ownership. */ + typedef dyncompat::shared_ptr DispatcherAMDGPUPtr; + + class DispatcherAMDGPU : public BaseSemantics::Dispatcher { + protected: + // Prototypical constructor + DispatcherAMDGPU() + : BaseSemantics::Dispatcher(64, RegisterDictionary::dictionary_amdgpu()) { } + + // Prototypical constructor + DispatcherAMDGPU(size_t addrWidth, const RegisterDictionary *regs/*=NULL*/) + : BaseSemantics::Dispatcher(addrWidth, regs ? regs : RegisterDictionary::dictionary_amdgpu()) { } + + // Normal constructor + DispatcherAMDGPU(const BaseSemantics::RiscOperatorsPtr &ops, size_t addrWidth, + const RegisterDictionary *regs) + : BaseSemantics::Dispatcher(ops, addrWidth, + regs ? regs : RegisterDictionary::dictionary_amdgpu()) { + regcache_init(); + iproc_init(); + memory_init(); + } + + public: + + /** Loads the iproc table with instruction processing functors. This normally happens from the constructor. */ + void iproc_init(); + + /** Load the cached register descriptors. This happens at construction and on set_register_dictionary() calls. */ + void regcache_init(); + + /** Make sure memory is set up correctly. For instance, byte order should be little endian. */ + void memory_init(); + + public: + /** Cached register. This register is cached so that there are not so many calls to Dispatcher::findRegister(). The + * register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()). + * + * Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for + * 32-bit architectures, etc. The other register names have specific sizes--such as REG_EAX being 32 bits--and are + * defined only on architectures that support them. + * + * @{ */ + + RegisterDescriptor REG_PC, REG_SCC; + + /** @}*/ + + /** Construct a prototypical dispatcher. The only thing this dispatcher can be used for is to create another dispatcher + * with the virtual @ref create method. */ + static DispatcherAMDGPUPtr instance() { + return DispatcherAMDGPUPtr(new DispatcherAMDGPU); + } + + /** Construct a prototyipcal dispatcher. Construct a prototypical dispatcher with a specified address size. The only thing + * this dispatcher can be used for is to create another dispatcher with the virtual @ref create method. */ + static DispatcherAMDGPUPtr instance(size_t addrWidth, const RegisterDictionary *regs = NULL) { + return DispatcherAMDGPUPtr(new DispatcherAMDGPU(addrWidth, regs)); + } + + /** Constructor. */ + static DispatcherAMDGPUPtr instance(const BaseSemantics::RiscOperatorsPtr &ops, size_t addrWidth, + const RegisterDictionary *regs = NULL) { + return DispatcherAMDGPUPtr(new DispatcherAMDGPU(ops, addrWidth, regs)); + } + + /** Virtual constructor. */ + virtual BaseSemantics::DispatcherPtr create(const BaseSemantics::RiscOperatorsPtr &ops, + size_t addrWidth = 0, + const RegisterDictionary *regs = NULL) const { + if (0 == addrWidth) { + //TODO + //addressWidth(64); + addrWidth = 64;//addressWidth(); + } + + return instance(ops, addrWidth, regs); + } + + /** Dynamic cast to a DispatcherAMDGPUPtr with assertion. */ + static DispatcherAMDGPUPtr promote(const BaseSemantics::DispatcherPtr &d) { + DispatcherAMDGPUPtr retval = dyncompat::dynamic_pointer_cast(d); + assert(retval != NULL); + return retval; + } + + virtual void set_register_dictionary(const RegisterDictionary *regdict); + + virtual RegisterDescriptor instructionPointerRegister() const; + + virtual RegisterDescriptor stackPointerRegister() const; + + virtual int iproc_key(SgAsmInstruction *insn_) const { + SgAsmAMDGPUInstruction *insn = isSgAsmAMDGPUInstruction(insn_); + assert(insn != NULL); + return insn->get_kind(); + } + + virtual void write(SgAsmExpression *e, const BaseSemantics::SValuePtr &value, size_t addr_nbits = 0); + + /** Architecture-specific read from register. + * + * Similar to RiscOperators::readRegister, but might do additional architecture-specific things. */ + virtual BaseSemantics::SValuePtr readRegister(const RegisterDescriptor &); + + /** Architecture-specific write to register. + * + * Similar to RiscOperators::writeRegister, but might do additional architecture-specific things. For instance, writing to + * a 32-bit GPR such as "eax" on x86-64 will write zeros to the upper half of "rax". */ + virtual void writeRegister(const RegisterDescriptor &, const BaseSemantics::SValuePtr &result); + + /** Set parity, sign, and zero flags appropriate for result value. */ + virtual void setFlagsForResult(const BaseSemantics::SValuePtr &result, + const BaseSemantics::SValuePtr &carries, + bool invertCarries, size_t nbits, + BaseSemantics::SValuePtr &n, + BaseSemantics::SValuePtr &z, + BaseSemantics::SValuePtr &c, + BaseSemantics::SValuePtr &v); + + /** Conditionally invert the bits of @p value. The bits are inverted if @p maybe is true, otherwise @p value is returned. */ + virtual BaseSemantics::SValuePtr invertMaybe(const BaseSemantics::SValuePtr &value, bool maybe); + + /** Adds two values and adjusts flags. This method can be used for subtraction if @p b is two's complement and @p + * invertCarries is set. If @p cond is supplied, then the addition and flag adjustments are conditional. + * @{ */ + virtual BaseSemantics::SValuePtr doAddOperation(BaseSemantics::SValuePtr a, BaseSemantics::SValuePtr b, + bool invertCarries, + const BaseSemantics::SValuePtr &carryIn, + BaseSemantics::SValuePtr &n, + BaseSemantics::SValuePtr &z, + BaseSemantics::SValuePtr &c, + BaseSemantics::SValuePtr &v); + + /** Returns the input value sign extended to the provided length. */ + virtual BaseSemantics::SValuePtr SignExtend(const BaseSemantics::SValuePtr &expr, size_t newsize); + + /** Returns the input value zero extended to the provided length. */ + virtual BaseSemantics::SValuePtr ZeroExtend(const BaseSemantics::SValuePtr &expr, size_t newsize); + + }; + +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// Instruction processors +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + + namespace AMDGPU { + +/** Base class for all AMDGPU instruction processors. + * + * This class provides single-letter names for some types that are used in all instructions: D, I, A, and Ops for the + * dispatcher raw pointer, instruction pointer, argument list pointer, and RISC operators raw pointer. It also takes care + * of advancing the instruction pointer prior to handing the instruction to the subclass, which by the way is done via + * @ref p method (short for "process"). See examples in DispatcherX86.C -- there are lots of them. */ + class InsnProcessor : public BaseSemantics::InsnProcessor { + public: + typedef DispatcherAMDGPU *D; + typedef BaseSemantics::RiscOperators *Ops; + typedef SgAsmAMDGPUInstruction *I; + typedef const SgAsmExpressionPtrList &A; + typedef uint32_t B; + + virtual void p(D, Ops, I, A, B) = 0; + + virtual void process(const BaseSemantics::DispatcherPtr &, SgAsmInstruction *); + + virtual void assert_args(I insn, A args, size_t nargs); + }; + + } // namespace + + } // namespace + } // namespace +} // namespace + +#endif diff --git a/dataflowAPI/rose/semantics/DispatcherARM64.C b/dataflowAPI/rose/semantics/DispatcherARM64.C index 4e84742e23..ec46c4539d 100644 --- a/dataflowAPI/rose/semantics/DispatcherARM64.C +++ b/dataflowAPI/rose/semantics/DispatcherARM64.C @@ -5118,7 +5118,7 @@ namespace rose { RegisterDictionary::RegisterDescriptors registers = regdict->get_largest_registers(); registers.erase(std::remove_if(registers.begin(), registers.end(), isStatusRegister), registers.end()); - BOOST_FOREACH( + DYN_FOREACH( const RegisterDescriptor ®, regdict->get_smallest_registers()) { if (isStatusRegister(reg)) registers.push_back(reg); @@ -5291,7 +5291,7 @@ namespace rose { DispatcherARM64::getBitfieldMask(int immr, int imms, int N, bool iswmask, int datasize) { int hsbarg = (N << 6) | (~imms); - int len; + int len = 0; for (int idx = 0; idx < 7; idx++) { if ((hsbarg & 0x1) == 1) len = idx; @@ -5684,4 +5684,3 @@ namespace rose { } // namespace //using namespace rose::Diagnostics; - diff --git a/dataflowAPI/rose/semantics/DispatcherARM64.h b/dataflowAPI/rose/semantics/DispatcherARM64.h index 1c1df0b12a..a1c2c1f32f 100644 --- a/dataflowAPI/rose/semantics/DispatcherARM64.h +++ b/dataflowAPI/rose/semantics/DispatcherARM64.h @@ -1,6 +1,9 @@ #ifndef ROSE_DispatcherARM64_H #define ROSE_DispatcherARM64_H +#include +#include +#include #include "BaseSemantics2.h" #include "../SgAsmArmv8Instruction.h" #include "external/rose/armv8InstructionEnum.h" @@ -14,7 +17,7 @@ namespace rose { //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// /** Shared-ownership pointer to an ARM instruction dispatcher. See @ref heap_object_shared_ownership. */ - typedef boost::shared_ptr DispatcherARM64Ptr; + typedef dyncompat::shared_ptr DispatcherARM64Ptr; class DispatcherARM64 : public BaseSemantics::Dispatcher { protected: @@ -94,7 +97,7 @@ namespace rose { /** Dynamic cast to a DispatcherARM64Ptr with assertion. */ static DispatcherARM64Ptr promote(const BaseSemantics::DispatcherPtr &d) { - DispatcherARM64Ptr retval = boost::dynamic_pointer_cast(d); + DispatcherARM64Ptr retval = dyncompat::dynamic_pointer_cast(d); assert(retval != NULL); return retval; } diff --git a/dataflowAPI/rose/semantics/DispatcherAmdgpuVega.C b/dataflowAPI/rose/semantics/DispatcherAmdgpuVega.C deleted file mode 100644 index 79ddaee6eb..0000000000 --- a/dataflowAPI/rose/semantics/DispatcherAmdgpuVega.C +++ /dev/null @@ -1,787 +0,0 @@ -#include "../util/StringUtility.h" -//#include "sage3basic.h" -#include "BaseSemantics2.h" -//#include "Diagnostics.h" -#include "DispatcherAmdgpuVega.h" -#include "../integerOps.h" -#include "SymEvalSemantics.h" - -#include "../SgAsmExpression.h" -#include "../conversions.h" - -#undef si_value // name pollution from siginfo.h - -namespace rose { - namespace BinaryAnalysis { - namespace InstructionSemantics2 { - -#define EXTR(lo, hi) IntegerOps::extract2(lo, hi, raw) - -/******************************************************************************************************************************* - * Support functions - *******************************************************************************************************************************/ - - static inline size_t asm_type_width(SgAsmType *ty) { - ASSERT_not_null(ty); - return ty->get_nBits(); - } - -/******************************************************************************************************************************* - * Base AmdgpuVega instruction processor - *******************************************************************************************************************************/ - namespace AmdgpuVega { - - void - InsnProcessor::process(const BaseSemantics::DispatcherPtr &dispatcher_, SgAsmInstruction *insn_) { - DispatcherAmdgpuVegaPtr dispatcher = DispatcherAmdgpuVega::promote(dispatcher_); - BaseSemantics::RiscOperatorsPtr operators = dispatcher->get_operators(); - SgAsmAmdgpuVegaInstruction *insn = isSgAsmAmdgpuVegaInstruction(insn_); - ASSERT_require(insn != NULL && insn == operators->currentInstruction()); - dispatcher->advanceInstructionPointer(insn); - SgAsmExpressionPtrList &operands = insn->get_operandList()->get_operands(); - //check_arg_width(dispatcher.get(), insn, operands); - - uint32_t raw = 0; - std::vector rawBytes = insn->get_raw_bytes(); - for (int idx = 0; idx < rawBytes.size(); idx++) { - raw |= (rawBytes[idx] << (8 * idx)); - } - p(dispatcher.get(), operators.get(), insn, operands, raw); - } - - void - InsnProcessor::assert_args(I insn, A args, size_t nargs) { - if (args.size() != nargs) { - std::string mesg = "instruction has incorrect number of args"; - throw BaseSemantics::Exception(mesg, insn); - } - } - -/******************************************************************************************************************************* - * Functors that handle individual AmdgpuVega instructions kinds - *******************************************************************************************************************************/ - typedef InsnProcessor P; - struct IP_s_add_u32 : P { - void p(D d, Ops ops, I insn, A args, B raw) { - - BaseSemantics::SValuePtr src1; - BaseSemantics::SValuePtr src0; - if(SgAsmIntegerValueExpression * ival = isSgAsmIntegerValueExpression(args[1])){ - src1 = ops->number_(ival->get_significantBits(), ival->get_value()); - }else{ - src1 = d->read(args[1]); - } - if(SgAsmIntegerValueExpression * ival = isSgAsmIntegerValueExpression(args[2])){ - src0 = ops->number_(ival->get_significantBits(), ival->get_value()); - }else{ - src0 = d->read(args[2]); - } - - - BaseSemantics::SValuePtr result; - BaseSemantics::SValuePtr n, z, c, v; - - result = d->doAddOperation( src0 , src1 ,false,ops->boolean_(false),n,z,c,v); - d->write(args[0],ops->extract(result,0,32)); - - BaseSemantics::SValuePtr scc_value; - scc_value = ops->ite( - ops->isUnsignedGreaterThan(result,ops->number_(64,0x100000000)), - ops->number_(1,1), - ops->number_(1,0)); - - d->writeRegister(d->REG_SCC,scc_value); - } - }; - struct IP_s_addc_u32 : P { - void p(D d, Ops ops, I insn, A args, B raw) { - - BaseSemantics::SValuePtr src1; - BaseSemantics::SValuePtr src0; - - if(SgAsmIntegerValueExpression * ival = isSgAsmIntegerValueExpression(args[1])){ - src1 = ops->number_(ival->get_significantBits(), ival->get_value()); - - }else{ - src1 = d->read(args[1]); - } - if(SgAsmIntegerValueExpression * ival = isSgAsmIntegerValueExpression(args[2])){ - src0 = ops->number_(ival->get_significantBits(), ival->get_value()); - }else{ - src0 = d->read(args[2]); - } - - - BaseSemantics::SValuePtr result; - BaseSemantics::SValuePtr n, z, c, v; - BaseSemantics::SValuePtr old_scc = d->readRegister(d->REG_SCC); - result = d->doAddOperation( src0 , src1 ,false, - d->readRegister(d->REG_SCC) - ,n,z,c,v); - - - - d->write(args[0],ops->extract(result,0,32)); - d->writeRegister(d->REG_SCC,c); - - } - }; - - struct IP_s_getpc_b64 : P { - void p(D d, Ops ops, I insn, A args, B raw) { - - SgAsmIntegerValueExpression *ival = isSgAsmIntegerValueExpression(args[2]); - BaseSemantics::SValuePtr result = ops->number_(ival->get_significantBits(), ival->get_value()); - BaseSemantics::SValuePtr lowPC = ops->extract(result,0,32); - BaseSemantics::SValuePtr highPC = ops->shiftRight(result,ops->number_(32,32)); - - d->write(args[0],lowPC); - d->write(args[1],highPC); - } - }; - - struct IP_s_setpc_b64 : P { - void p(D d, Ops ops, I insn, A args, B raw) { - BaseSemantics::SValuePtr result; - BaseSemantics::SValuePtr lowPC = ops->extract(d->read(args[0]),0,32); - BaseSemantics::SValuePtr highPC = d->ZeroExtend(d->read(args[1]),64); - BaseSemantics::SValuePtr n, z, c, v; - result = d->doAddOperation( ops->shiftLeft(highPC, ops->number_(32,32)) , lowPC,false,ops->boolean_(false),n,z,c,v); - d->writeRegister(d->REG_PC, result); - } - }; - struct IP_s_swappc_b64 : P { - - void p(D d, Ops ops, I insn, A args, B raw) { - BaseSemantics::SValuePtr result = d->readRegister(d->REG_PC); - BaseSemantics::SValuePtr storelowPC = result; - BaseSemantics::SValuePtr storehighPC = ops->shiftRight(result,ops->number_(32,32)); - - d->write(args[2],storelowPC); - d->write(args[3],storehighPC); - - BaseSemantics::SValuePtr n, z, c, v; - BaseSemantics::SValuePtr lowPC = ops->extract(d->read(args[0]),0,32); - BaseSemantics::SValuePtr highPC = d->ZeroExtend(d->read(args[1]),64); - result = d->doAddOperation( ops->shiftLeft(highPC, ops->number_(32,32)) , lowPC,false,ops->boolean_(false),n,z,c,v); - d->writeRegister(d->REG_PC, result); - } - - }; - - - } // namespace - -/******************************************************************************************************************************* - * DispatcherAmdgpuVega - *******************************************************************************************************************************/ - - void - DispatcherAmdgpuVega::iproc_init() { - - iproc_set(rose_amdgpu_op_s_getpc_b64, new AmdgpuVega::IP_s_getpc_b64); - iproc_set(rose_amdgpu_op_s_setpc_b64, new AmdgpuVega::IP_s_setpc_b64); - iproc_set(rose_amdgpu_op_s_swappc_b64, new AmdgpuVega::IP_s_swappc_b64); - iproc_set(rose_amdgpu_op_s_add_u32, new AmdgpuVega::IP_s_add_u32); - iproc_set(rose_amdgpu_op_s_addc_u32, new AmdgpuVega::IP_s_addc_u32); - } - - void - DispatcherAmdgpuVega::regcache_init() { - if (regdict) { - REG_PC = findRegister("pc", 64); - REG_SCC = findRegister("scc", 1); - } - } - - void - DispatcherAmdgpuVega::memory_init() { - if (BaseSemantics::StatePtr state = currentState()) { - if (BaseSemantics::MemoryStatePtr memory = state->memoryState()) { - switch (memory->get_byteOrder()) { - case ByteOrder::ORDER_LSB: - break; - case ByteOrder::ORDER_MSB: - break; - case ByteOrder::ORDER_UNSPECIFIED: - memory->set_byteOrder(ByteOrder::ORDER_LSB); - break; - } - } - } - } - - RegisterDescriptor - DispatcherAmdgpuVega::instructionPointerRegister() const { - return REG_PC; - } - - RegisterDescriptor - DispatcherAmdgpuVega::stackPointerRegister() const { - assert(0 && "not implemented"); - return REG_SCC; - } - - static bool - isStatusRegister(const RegisterDescriptor ®) { - assert( 0 && "not implemented yet"); - return reg.get_major() == armv8_regclass_pstate && reg.get_minor() == 0; - } - - RegisterDictionary::RegisterDescriptors - DispatcherAmdgpuVega::get_usual_registers() const { - RegisterDictionary::RegisterDescriptors registers = regdict->get_largest_registers(); - registers.erase(std::remove_if(registers.begin(), registers.end(), isStatusRegister), - registers.end()); - BOOST_FOREACH( - const RegisterDescriptor ®, regdict->get_smallest_registers()) { - if (isStatusRegister(reg)) - registers.push_back(reg); - } - return registers; - } - - void - DispatcherAmdgpuVega::set_register_dictionary(const RegisterDictionary *regdict) { - BaseSemantics::Dispatcher::set_register_dictionary(regdict); - regcache_init(); - } - - void - DispatcherAmdgpuVega::setFlagsForResult(const BaseSemantics::SValuePtr &result, - const BaseSemantics::SValuePtr &carries, - bool invertCarries, size_t nbits, - BaseSemantics::SValuePtr &n, BaseSemantics::SValuePtr &z, - BaseSemantics::SValuePtr &c, BaseSemantics::SValuePtr &v) { - size_t width = result->get_width(); - - n = operators->extract(result, width - 1, width); - z = operators->equalToZero(result); - - BaseSemantics::SValuePtr sign = operators->extract(carries, nbits - 1, nbits); - BaseSemantics::SValuePtr ofbit = operators->extract(carries, nbits - 2, nbits - 1); - c = invertMaybe(sign, invertCarries); - v = operators->xor_(sign, ofbit); - } - - BaseSemantics::SValuePtr - DispatcherAmdgpuVega::parity(const BaseSemantics::SValuePtr &v) { - ASSERT_require(v->get_width() == 8); - BaseSemantics::SValuePtr p1 = operators->extract(v, 1, 2); - BaseSemantics::SValuePtr p01 = operators->xor_(operators->extract(v, 0, 1), p1); - BaseSemantics::SValuePtr p3 = operators->extract(v, 3, 4); - BaseSemantics::SValuePtr p23 = operators->xor_(operators->extract(v, 2, 3), p3); - BaseSemantics::SValuePtr p5 = operators->extract(v, 5, 6); - BaseSemantics::SValuePtr p45 = operators->xor_(operators->extract(v, 4, 5), p5); - BaseSemantics::SValuePtr p7 = operators->extract(v, 7, 8); - BaseSemantics::SValuePtr p67 = operators->xor_(operators->extract(v, 6, 7), p7); - BaseSemantics::SValuePtr p0123 = operators->xor_(p01, p23); - BaseSemantics::SValuePtr p4567 = operators->xor_(p45, p67); - BaseSemantics::SValuePtr pall = operators->xor_(p0123, p4567); - return operators->invert(pall); - } - - BaseSemantics::SValuePtr - DispatcherAmdgpuVega::invertMaybe(const BaseSemantics::SValuePtr &value, bool maybe) { - return maybe ? operators->invert(value) : value; - } - - BaseSemantics::SValuePtr - DispatcherAmdgpuVega::isZero(const BaseSemantics::SValuePtr &value) { - return operators->equalToZero(value); - } - - BaseSemantics::SValuePtr - DispatcherAmdgpuVega::ConditionHolds(const BaseSemantics::SValuePtr &cond) { - - BaseSemantics::SValuePtr result = operators->unspecified_(1); - /*Dyninst::AST::Ptr condExpr = SymEvalSemantics::SValue::promote(cond)->get_expression(); - Dyninst::DataflowAPI::ConstantAST * - constAST = dynamic_cast(condExpr.get()); - - ASSERT_not_null(constAST); - Dyninst::DataflowAPI::Constant constVal = constAST->val(); - uint64_t condVal = constVal.val; - - BaseSemantics::SValuePtr nVal = readRegister(REG_N); - BaseSemantics::SValuePtr zVal = readRegister(REG_Z); - BaseSemantics::SValuePtr cVal = readRegister(REG_C); - BaseSemantics::SValuePtr vVal = readRegister(REG_V); - BaseSemantics::SValuePtr result = operators->unspecified_(1); - - switch (((condVal & 0xF) >> 1)) { - case 0: - result = operators->isEqual(zVal, operators->number_(1, 1)); - break; - case 1: - result = operators->isEqual(cVal, operators->number_(1, 1)); - break; - case 2: - result = operators->isEqual(nVal, operators->number_(1, 1)); - break; - case 3: - result = operators->isEqual(vVal, operators->number_(1, 1)); - break; - case 4: - result = operators->ite(operators->isEqual(cVal, operators->number_(1, 1)), - operators->ite( - operators->isEqual(zVal, operators->number_(1, 0)), - operators->boolean_(true), operators->boolean_(false)), - operators->boolean_(false)); - break; - case 5: - result = operators->isEqual(nVal, vVal); - break; - case 6: - result = operators->ite(operators->isEqual(nVal, vVal), - operators->ite(operators->isEqual(zVal, - operators->number_(1, 0)), - operators->boolean_(true), - operators->boolean_(false)), - operators->boolean_(false)); - break; - case 7: - result = operators->boolean_(true); - break; - default: - assert(!"invalid 3-bit value!"); - break; - } - - if ((condVal & 0x1) == 1 && (condVal & 0xF) != 0xF) - result = operators->invert(result);*/ - - return result; - } - - BaseSemantics::SValuePtr - DispatcherAmdgpuVega::NOT(const BaseSemantics::SValuePtr &expr) { - return operators->invert(expr); - } - - void - DispatcherAmdgpuVega::BranchTo(const BaseSemantics::SValuePtr &target) { - ASSERT_require(target != NULL); - writeRegister(REG_PC, operators->extract(target, 0, 64)); - } - - BaseSemantics::SValuePtr - DispatcherAmdgpuVega::Zeros(const unsigned int nbits) { - ASSERT_require(nbits > 0); - return operators->number_(nbits, 0); - } - - BaseSemantics::SValuePtr - DispatcherAmdgpuVega::SignExtend(const BaseSemantics::SValuePtr &expr, size_t newsize) { - ASSERT_require(newsize > 0); - return operators->signExtend(expr, newsize); - } - - BaseSemantics::SValuePtr - DispatcherAmdgpuVega::ZeroExtend(const BaseSemantics::SValuePtr &expr, size_t newsize) { - ASSERT_require(newsize > 0); - return operators->unsignedExtend(expr, newsize); - } - - BaseSemantics::SValuePtr - DispatcherAmdgpuVega::ROR(const BaseSemantics::SValuePtr &expr, const BaseSemantics::SValuePtr &amt) { - ASSERT_not_null(amt); - return operators->rotateRight(expr, amt); - } - - BaseSemantics::SValuePtr - DispatcherAmdgpuVega::Replicate(const BaseSemantics::SValuePtr &expr) { - ASSERT_not_null(expr); - ASSERT_always_require(64 % expr->get_width() == 0); - - int blocknums = 64 / expr->get_width(); - BaseSemantics::SValuePtr ret = expr; - for (int idx = 0; idx < blocknums; idx++) { - ret = operators->or_(ret, - operators->shiftLeft(ret, operators->number_(8, expr->get_width() * idx))); - } - - return ret; - } - - BaseSemantics::SValuePtr - DispatcherAmdgpuVega::getBitfieldMask(int immr, int imms, - int N, bool iswmask, int datasize) { - int hsbarg = (N << 6) | (~imms); - int len; - for (int idx = 0; idx < 7; idx++) { - if ((hsbarg & 0x1) == 1) - len = idx; - hsbarg >>= 1; - } - - if (len < 1 || (1 << len) > 64) - assert(!"Reserved value found in bitfield extract instruction!"); - - int levels = ((1 << len) - 1); - int S = imms & levels; - int R = immr & levels; - int diff = S - R; - - int d = diff & levels; - int welem = (1 << (S + 1)) - 1, telem = (1 << (d + 1)) - 1; - - if (iswmask) { - BaseSemantics::SValuePtr wmask = operators->number_(datasize, welem); - wmask = ROR(wmask, operators->number_(32, R)); - return Replicate(wmask); - } else { - BaseSemantics::SValuePtr tmask = operators->number_(datasize, telem); - return Replicate(tmask); - } - } - - size_t - DispatcherAmdgpuVega::getRegSize(uint32_t raw) { - if (IntegerOps::extract2(23, 23, raw) == 0) { - if (IntegerOps::extract2(30, 31, raw) == 0x3) - return 64; - else - return 32; - } else { - if (IntegerOps::extract2(22, 22, raw) == 1) - return 32; - else - return 64; - } - } - - size_t - DispatcherAmdgpuVega::ldStrLiteralAccessSize(uint32_t raw) { - int opc = IntegerOps::extract2(30, 31, raw); - - switch (opc) { - case 2: - case 0: - return 32; - case 1: - return 64; - default: - assert("Memory prefetch instruction not implemented yet!"); - return 0; - } - } - - bool - DispatcherAmdgpuVega::inzero(uint32_t raw) { - switch (IntegerOps::extract2(29, 30, raw)) { - case 0: - case 2: - return true; - case 1: - return false; - default: - assert(!"Bitfield extract instruction has invalid opc field for inzero!"); - break; - } - } - - bool - DispatcherAmdgpuVega::extend(uint32_t raw) { - switch (IntegerOps::extract2(29, 30, raw)) { - case 2: - case 1: - return false; - case 0: - return true; - default: - assert(!"Bitfield extract instruction has invalid opc field for extend!"); - break; - } - } - - int - DispatcherAmdgpuVega::op(uint32_t raw) { - switch (IntegerOps::extract2(29, 30, raw)) { - case 0: - case 3: - return static_cast(AmdgpuVega::InsnProcessor::LogicalOp_AND); - case 1: - return static_cast(AmdgpuVega::InsnProcessor::LogicalOp_ORR); - case 2: - return static_cast(AmdgpuVega::InsnProcessor::LogicalOp_EOR); - default: - assert(!"Invalid code for opc field in logical OR instruction variant!"); - break; - } - } - - bool - DispatcherAmdgpuVega::setflags(uint32_t raw) { - if (IntegerOps::extract2(24, 28, raw) == 0x0A) { - switch (IntegerOps::extract2(29, 30, raw)) { - case 0: - case 1: - case 2: - return false; - case 3: - return true; - default: - assert(!"Invalid code for opc field in logical instruction!"); - break; - } - } else { - return IntegerOps::extract2(29, 29, raw) == 1; - } - } - - int - DispatcherAmdgpuVega::getDatasize(uint32_t raw) { - if(IntegerOps::extract2(25, 27, raw) == 0x5) { - return 32 * (1 + (IntegerOps::extract2(31, 31, raw) & 0x1)); - } else { - int v27_29 = IntegerOps::extract2(27, 29, raw), v23_25 = IntegerOps::extract2(23, 25, raw); - int retval, v30_31 = IntegerOps::extract2(30, 31, raw);; - - if (v27_29 == 0x5 && v23_25 < 0x4) { - retval = 0x8 << (2 + (v30_31 & 0x1)); - } else { - retval = 0x8 << v30_31; - } - - return retval * 8; - } - } - - int - DispatcherAmdgpuVega::getShiftType(uint32_t raw) { - int v10_11 = IntegerOps::extract2(10, 11, raw); - - switch(v10_11) { - case 0: return static_cast(AmdgpuVega::InsnProcessor::ShiftType_LSL); - case 1: return static_cast(AmdgpuVega::InsnProcessor::ShiftType_LSR); - case 2: return static_cast(AmdgpuVega::InsnProcessor::ShiftType_ASR); - case 3: return static_cast(AmdgpuVega::InsnProcessor::ShiftType_ROR); - default: ASSERT_not_reachable("Cannot have a value greater than 3 for a 2-bit field (field: op2, bits: 10..11)!"); - } - } - - int - DispatcherAmdgpuVega::getConditionVal(uint32_t raw) { - if(IntegerOps::extract2(24, 31, raw) == 0x54 && IntegerOps::extract2(4, 4, raw) == 0) - return IntegerOps::extract2(0, 3, raw); - else - return IntegerOps::extract2(12, 15, raw); - } - - int - DispatcherAmdgpuVega::opcode(uint32_t raw) { - if(IntegerOps::extract2(23, 28, raw) == 0x25) - return IntegerOps::extract2(29, 30, raw); - else - return IntegerOps::extract2(10, 10, raw); - } - - bool - DispatcherAmdgpuVega::subop(uint32_t raw) { - if(IntegerOps::extract2(24, 28, raw) == 0x1B) { - return IntegerOps::extract2(15, 15, raw) == 0x1; - } else { - return IntegerOps::extract2(30, 30, raw) == 0x1; - } - } - - BaseSemantics::SValuePtr - DispatcherAmdgpuVega::doAddOperation(BaseSemantics::SValuePtr a, BaseSemantics::SValuePtr b, - bool invertCarries, const BaseSemantics::SValuePtr &carryIn, - BaseSemantics::SValuePtr &n, BaseSemantics::SValuePtr &z, - BaseSemantics::SValuePtr &c, BaseSemantics::SValuePtr &v) { - if (a->get_width() > b->get_width()) { - b = operators->signExtend(b, a->get_width()); - } else if (a->get_width() < b->get_width()) { - a = operators->signExtend(a, b->get_width()); - } - - ASSERT_require(1 == carryIn->get_width()); - size_t nbits = a->get_width(); - BaseSemantics::SValuePtr carries; - BaseSemantics::SValuePtr result = operators->addWithCarries(a, b, - invertMaybe(carryIn, invertCarries), - carries/*out*/); - setFlagsForResult(result, carries, invertCarries, a->get_width(), n, z, c, v); - return result; - } - - BaseSemantics::SValuePtr - DispatcherAmdgpuVega::effectiveAddress(SgAsmExpression *e, size_t nbits) { - SgAsmExpression *addressExpression; - if (SgAsmMemoryReferenceExpression *memoryReferenceExpression = isSgAsmMemoryReferenceExpression(e)) - addressExpression = memoryReferenceExpression->get_address(); - else - addressExpression = e; - - BaseSemantics::SValuePtr retval; - - if (SgAsmRegisterReferenceExpression *rre = isSgAsmRegisterReferenceExpression(addressExpression)) { - const RegisterDescriptor ® = rre->get_descriptor(); - retval = operators->readRegister(reg); - } else if (SgAsmBinaryAdd *op = isSgAsmBinaryAdd(addressExpression)) { - BaseSemantics::SValuePtr lhs = effectiveAddress(op->get_lhs(), nbits); - BaseSemantics::SValuePtr rhs = effectiveAddress(op->get_rhs(), nbits); - retval = operators->add(lhs, rhs); - } else if (SgAsmBinaryMultiply *op = isSgAsmBinaryMultiply(addressExpression)) { - BaseSemantics::SValuePtr lhs = effectiveAddress(op->get_lhs(), nbits); - BaseSemantics::SValuePtr rhs = effectiveAddress(op->get_rhs(), nbits); - retval = operators->unsignedMultiply(lhs, rhs); - } else if (SgAsmBinaryLsl *lshift = isSgAsmBinaryLsl(addressExpression)) { - SgAsmExpression *lhs = lshift->get_lhs(); - SgAsmExpression *rhs = lshift->get_rhs(); - size_t nbits = std::max(lhs->get_nBits(), rhs->get_nBits()); - retval = operators->shiftLeft(read(lhs, lhs->get_nBits()), read(rhs, rhs->get_nBits())); - } else if (SgAsmIntegerValueExpression *ival = isSgAsmIntegerValueExpression(addressExpression)) { - retval = operators->number_(ival->get_significantBits(), ival->get_value()); - } - - ASSERT_not_null(retval); - if (retval->get_width() < nbits) { - retval = operators->signExtend(retval, nbits); - } else if (retval->get_width() > nbits) { - retval = operators->extract(retval, 0, nbits); - } - - return retval; - } - - BaseSemantics::SValuePtr - DispatcherAmdgpuVega::readRegister(const RegisterDescriptor ®) { - return operators->readRegister(reg); - } - - void - DispatcherAmdgpuVega::writeRegister(const RegisterDescriptor ®, const BaseSemantics::SValuePtr &value) { - operators->writeRegister(reg, value); - } - - void - DispatcherAmdgpuVega::write(SgAsmExpression *e, const BaseSemantics::SValuePtr &value, - size_t addr_nbits/*=0*/) { - if (SgAsmDirectRegisterExpression *re = isSgAsmDirectRegisterExpression(e)) { - writeRegister(re->get_descriptor(), value); - } else { - Dispatcher::write(e, value, addr_nbits); // defer to super class - } - } - - BaseSemantics::SValuePtr - DispatcherAmdgpuVega::fixMemoryAddress(const BaseSemantics::SValuePtr &addr) const { - if (size_t addrWidth = addressWidth()) { - if (addr->get_width() < addrWidth) - return operators->signExtend(addr, addrWidth); - if (addr->get_width() > addrWidth) - return operators->unsignedExtend(addr, addrWidth); - } - return addr; - } - - BaseSemantics::SValuePtr - DispatcherAmdgpuVega::readMemory(const BaseSemantics::SValuePtr &addr, size_t readSize) { - SymEvalSemantics::StateASTPtr state = SymEvalSemantics::StateAST::promote(operators->currentState()); - - //The second, third and fourth arguments will remain unused - return state->readMemory(addr, operators->unspecified_(1), NULL, NULL, readSize); - } - - void - DispatcherAmdgpuVega::writeMemory(const BaseSemantics::SValuePtr &addr, size_t writeSize, const BaseSemantics::SValuePtr &data) { - SymEvalSemantics::StateASTPtr state = SymEvalSemantics::StateAST::promote(operators->currentState()); - - //The third and fourth arguments will remain unused - state->writeMemory(addr, data, NULL, NULL, writeSize); - } - - SgAsmExpression * - DispatcherAmdgpuVega::getWriteBackTarget(SgAsmExpression *expr) { - SgAsmMemoryReferenceExpression *memoryExpression = isSgAsmMemoryReferenceExpression(expr); - ASSERT_not_null(memoryExpression); - - SgAsmExpression *address = memoryExpression->get_address(); - ASSERT_not_null(address); - - if (isSgAsmBinaryAdd(address)) { - return isSgAsmBinaryAdd(address)->get_lhs(); - } else { - SgAsmRegisterReferenceExpression *retval = isSgAsmRegisterReferenceExpression(address); - ASSERT_not_null(retval); - - return retval; - } - } - - /*Just returning the expression as-is, since there is no flag or variable in semantics indicating whether or not - a SValue should be treated as signed/unsigned. The signed-ness should be taken into account when performing an - operation on this value instead */ - BaseSemantics::SValuePtr - DispatcherAmdgpuVega::UInt(const BaseSemantics::SValuePtr &expr) { - ASSERT_not_null(expr); - return expr; - } - - BaseSemantics::SValuePtr - DispatcherAmdgpuVega::ShiftReg(const BaseSemantics::SValuePtr &src, int shiftType, const BaseSemantics::SValuePtr &amount) { - ASSERT_not_null(amount); - - switch(static_cast(shiftType)) { - case AmdgpuVega::InsnProcessor::ShiftType_LSL: return operators->shiftLeft(src, amount); - case AmdgpuVega::InsnProcessor::ShiftType_LSR: return operators->shiftRight(src, amount); - case AmdgpuVega::InsnProcessor::ShiftType_ASR: return operators->shiftRightArithmetic(src, amount); - case AmdgpuVega::InsnProcessor::ShiftType_ROR: return operators->rotateRight(src, amount); - default: ASSERT_not_reachable("Found invalid shift type for shift instruction!"); - } - } - - BaseSemantics::SValuePtr - DispatcherAmdgpuVega::CountLeadingZeroBits(const BaseSemantics::SValuePtr &expr) { - size_t len = expr->get_width(); - - for(int idx = len - 1; idx >= 0; idx--) - if(operators->isEqual(operators->extract(expr, len, len + 1), operators->number_(1, 1))) - return operators->number_(expr->get_width(), len - 1 - idx); - - return operators->number_(expr->get_width(), len); - } - - BaseSemantics::SValuePtr - DispatcherAmdgpuVega::CountLeadingSignBits(const BaseSemantics::SValuePtr &expr) { - size_t len = expr->get_width(); - BaseSemantics::SValuePtr arg = operators->xor_(operators->extract(expr, 1, len), operators->extract(expr, 0, len - 1)); - return CountLeadingZeroBits(arg); - } - - BaseSemantics::SValuePtr - DispatcherAmdgpuVega::Int(const BaseSemantics::SValuePtr &expr, bool isUnsigned) { - if(isUnsigned) - return UInt(expr); - else { - int len = expr->get_width(); - BaseSemantics::SValuePtr ret = Zeros(len); - - for(int idx = 0; idx < len; idx++) - if(operators->isEqual(operators->extract(expr, idx, idx + 1), operators->number_(1, 1))) - ret = operators->add(ret, operators->number_(len, 2<isEqual(operators->extract(expr, len, len + 1), operators->number_(1, 1))) - ret = operators->add(ret, operators->negate(operators->number_(len + 1, 2< DispatcherAmdgpuVegaPtr; - - class DispatcherAmdgpuVega : public BaseSemantics::Dispatcher { - protected: - // Prototypical constructor - DispatcherAmdgpuVega() - : BaseSemantics::Dispatcher(64, RegisterDictionary::dictionary_amdgpu_vega()) { } - - // Prototypical constructor - DispatcherAmdgpuVega(size_t addrWidth, const RegisterDictionary *regs/*=NULL*/) - : BaseSemantics::Dispatcher(addrWidth, regs ? regs : RegisterDictionary::dictionary_amdgpu_vega()) { } - - // Normal constructor - DispatcherAmdgpuVega(const BaseSemantics::RiscOperatorsPtr &ops, size_t addrWidth, - const RegisterDictionary *regs) - : BaseSemantics::Dispatcher(ops, addrWidth, - regs ? regs : RegisterDictionary::dictionary_amdgpu_vega()) { - regcache_init(); - iproc_init(); - memory_init(); - } - - public: - - /** Loads the iproc table with instruction processing functors. This normally happens from the constructor. */ - void iproc_init(); - - /** Load the cached register descriptors. This happens at construction and on set_register_dictionary() calls. */ - void regcache_init(); - - /** Make sure memory is set up correctly. For instance, byte order should be little endian. */ - void memory_init(); - - public: - /** Cached register. This register is cached so that there are not so many calls to Dispatcher::findRegister(). The - * register descriptor is updated only when the register dictionary is changed (see set_register_dictionary()). - * - * Register names like REG_anyAX have sizes that depend on the architecture: 16 bits for 16-bit architectures, 32 bits for - * 32-bit architectures, etc. The other register names have specific sizes--such as REG_EAX being 32 bits--and are - * defined only on architectures that support them. - * - * @{ */ - - RegisterDescriptor REG_PC, REG_SCC; - - /** @}*/ - - /** Construct a prototypical dispatcher. The only thing this dispatcher can be used for is to create another dispatcher - * with the virtual @ref create method. */ - static DispatcherAmdgpuVegaPtr instance() { - return DispatcherAmdgpuVegaPtr(new DispatcherAmdgpuVega); - } - - /** Construct a prototyipcal dispatcher. Construct a prototypical dispatcher with a specified address size. The only thing - * this dispatcher can be used for is to create another dispatcher with the virtual @ref create method. */ - static DispatcherAmdgpuVegaPtr instance(size_t addrWidth, const RegisterDictionary *regs = NULL) { - return DispatcherAmdgpuVegaPtr(new DispatcherAmdgpuVega(addrWidth, regs)); - } - - /** Constructor. */ - static DispatcherAmdgpuVegaPtr instance(const BaseSemantics::RiscOperatorsPtr &ops, size_t addrWidth, - const RegisterDictionary *regs = NULL) { - return DispatcherAmdgpuVegaPtr(new DispatcherAmdgpuVega(ops, addrWidth, regs)); - } - - /** Virtual constructor. */ - virtual BaseSemantics::DispatcherPtr create(const BaseSemantics::RiscOperatorsPtr &ops, - size_t addrWidth = 0, - const RegisterDictionary *regs = NULL) const { - if (0 == addrWidth) { - //TODO - //addressWidth(64); - addrWidth = 64;//addressWidth(); - } - - return instance(ops, addrWidth, regs); - } - - /** Dynamic cast to a DispatcherAmdgpuVegaPtr with assertion. */ - static DispatcherAmdgpuVegaPtr promote(const BaseSemantics::DispatcherPtr &d) { - DispatcherAmdgpuVegaPtr retval = boost::dynamic_pointer_cast(d); - assert(retval != NULL); - return retval; - } - - virtual void set_register_dictionary(const RegisterDictionary *regdict); - - /** Get list of common registers. Returns a list of non-overlapping registers composed of the largest registers except - * using individual flags for the fields of the FLAGS/EFLAGS register. */ - virtual RegisterDictionary::RegisterDescriptors get_usual_registers() const; - - virtual RegisterDescriptor instructionPointerRegister() const; - - virtual RegisterDescriptor stackPointerRegister() const; - - virtual BaseSemantics::SValuePtr effectiveAddress(SgAsmExpression *, size_t nbits = 0); - - virtual int iproc_key(SgAsmInstruction *insn_) const { - SgAsmAmdgpuVegaInstruction *insn = isSgAsmAmdgpuVegaInstruction(insn_); - assert(insn != NULL); - return insn->get_kind(); - } - - virtual void write(SgAsmExpression *e, const BaseSemantics::SValuePtr &value, size_t addr_nbits = 0); - - /** Architecture-specific read from register. - * - * Similar to RiscOperators::readRegister, but might do additional architecture-specific things. */ - virtual BaseSemantics::SValuePtr readRegister(const RegisterDescriptor &); - - /** Architecture-specific write to register. - * - * Similar to RiscOperators::writeRegister, but might do additional architecture-specific things. For instance, writing to - * a 32-bit GPR such as "eax" on x86-64 will write zeros to the upper half of "rax". */ - virtual void writeRegister(const RegisterDescriptor &, const BaseSemantics::SValuePtr &result); - - /** Set parity, sign, and zero flags appropriate for result value. */ - virtual void setFlagsForResult(const BaseSemantics::SValuePtr &result, - const BaseSemantics::SValuePtr &carries, - bool invertCarries, size_t nbits, - BaseSemantics::SValuePtr &n, - BaseSemantics::SValuePtr &z, - BaseSemantics::SValuePtr &c, - BaseSemantics::SValuePtr &v); - - /** Returns true if byte @p v has an even number of bits set; false for an odd number */ - virtual BaseSemantics::SValuePtr parity(const BaseSemantics::SValuePtr &v); - - /** Conditionally invert the bits of @p value. The bits are inverted if @p maybe is true, otherwise @p value is returned. */ - virtual BaseSemantics::SValuePtr invertMaybe(const BaseSemantics::SValuePtr &value, bool maybe); - - /** Adds two values and adjusts flags. This method can be used for subtraction if @p b is two's complement and @p - * invertCarries is set. If @p cond is supplied, then the addition and flag adjustments are conditional. - * @{ */ - virtual BaseSemantics::SValuePtr doAddOperation(BaseSemantics::SValuePtr a, BaseSemantics::SValuePtr b, - bool invertCarries, - const BaseSemantics::SValuePtr &carryIn, - BaseSemantics::SValuePtr &n, - BaseSemantics::SValuePtr &z, - BaseSemantics::SValuePtr &c, - BaseSemantics::SValuePtr &v); - - //FIXME - /** Implements the RCL, RCR, ROL, and ROR instructions for various operand sizes. The rotate amount is always 8 bits wide - * in the instruction, but the semantics mask off all but the low-order bits, keeping 5 bits in 32-bit mode and 6 bits in - * 64-bit mode (indicated by the rotateSignificantBits argument). */ - /*virtual BaseSemantics::SValuePtr doRotateOperation(ARMv8InstructionKind kind, - const BaseSemantics::SValuePtr &operand, - const BaseSemantics::SValuePtr &total_rotate, - size_t rotateSignificantBits);*/ - - //FIXME - /** Implements the SHR, SAR, SHL, SAL, SHRD, and SHLD instructions for various operand sizes. The shift amount is always 8 - * bits wide in the instruction, but the semantics mask off all but the low-order bits, keeping 5 bits in 32-bit mode and - * 7 bits in 64-bit mode (indicated by the @p shiftSignificantBits argument). The semantics of SHL and SAL are - * identical (in fact, ROSE doesn't even define x86_sal). The @p source_bits argument contains the bits to be shifted into - * the result and is used only for SHRD and SHLD instructions. */ - /*virtual BaseSemantics::SValuePtr doShiftOperation(ARMv8InstructionKind kind, - const BaseSemantics::SValuePtr &operand, - const BaseSemantics::SValuePtr &source_bits, - const BaseSemantics::SValuePtr &total_shift, - size_t shiftSignificantBits);*/ - - /** Extend or truncate value to propert memory address width. */ - virtual BaseSemantics::SValuePtr fixMemoryAddress(const BaseSemantics::SValuePtr &address) const; - - /** Checks if the supplied value is or isn't equal to zero */ - virtual BaseSemantics::SValuePtr isZero(const BaseSemantics::SValuePtr &value); - - virtual BaseSemantics::SValuePtr ConditionHolds(const BaseSemantics::SValuePtr &cond); - - /** Inverts the passed in expression and returns the result */ - virtual BaseSemantics::SValuePtr NOT(const BaseSemantics::SValuePtr &expr); - - /** Execute a branch -- equivalent to writing the target address value to the PC */ - virtual void BranchTo(const BaseSemantics::SValuePtr &target); - - /** Returns a value that equals 0. nbits specifies what should be the bit-length of the value, - * but is irrelevant in practice as a 64-bit zero is returned anyway. */ - virtual BaseSemantics::SValuePtr Zeros(const unsigned int nbits); - - /** Returns the input value sign extended to the provided length. */ - virtual BaseSemantics::SValuePtr SignExtend(const BaseSemantics::SValuePtr &expr, size_t newsize); - - /** Returns the input value zero extended to the provided length. */ - virtual BaseSemantics::SValuePtr ZeroExtend(const BaseSemantics::SValuePtr &expr, size_t newsize); - - /** Returns the input value right rotated by the provided amount. */ - virtual BaseSemantics::SValuePtr ROR(const BaseSemantics::SValuePtr &expr, const BaseSemantics::SValuePtr &amt); - - /** Replicates the value contained in expr to fill the full 64-bit width. */ - virtual BaseSemantics::SValuePtr Replicate(const BaseSemantics::SValuePtr &expr); - - BaseSemantics::SValuePtr getBitfieldMask(int immr, int imms, int N, bool iswmask, int datasize); - - size_t getRegSize(uint32_t raw); - - size_t ldStrLiteralAccessSize(uint32_t raw); - - bool inzero(uint32_t raw); - - bool extend(uint32_t raw); - - int op(uint32_t raw); - - bool setflags(uint32_t raw); - - int getDatasize(uint32_t raw); - - int getShiftType(uint32_t raw); - - int getConditionVal(uint32_t raw); - - int opcode(uint32_t raw); - - bool subop(uint32_t raw); - - /** Reads memory of size readSize bits from address addr. */ - BaseSemantics::SValuePtr readMemory(const BaseSemantics::SValuePtr &addr, size_t readSize); - - /** Writes value data of size writeSize bits to memory at address addr. */ - void writeMemory(const BaseSemantics::SValuePtr &addr, size_t writeSize, const BaseSemantics::SValuePtr &data); - - /** Returns the register expression containing the target address for a write-back in case of memory-access instructions. */ - SgAsmExpression *getWriteBackTarget(SgAsmExpression *expr); - - /** Returns an expression that is an unsigned representation of expr. */ - BaseSemantics::SValuePtr UInt(const BaseSemantics::SValuePtr &expr); - - /** Applies a shift operation of type shiftType (defined in enum ShiftType) and shift length of amount to src. */ - BaseSemantics::SValuePtr ShiftReg(const BaseSemantics::SValuePtr &src, int shiftType, const BaseSemantics::SValuePtr &amount); - - /** Returns an expression representing the number of leading 0s in expr. */ - BaseSemantics::SValuePtr CountLeadingZeroBits(const BaseSemantics::SValuePtr &expr); - - /** Returns an expression representing the number of leading contiguous bits that match the sign bit in expr. */ - BaseSemantics::SValuePtr CountLeadingSignBits(const BaseSemantics::SValuePtr &expr); - - /** Returns an expression that is a signed representation of expr if unSigned is false and calls UInt if unSigned is true. */ - BaseSemantics::SValuePtr Int(const BaseSemantics::SValuePtr &expr, bool isUnsigned); - - /** Rounds a number to zero (upwards if it is negative, downwards if it is positive. */ - BaseSemantics::SValuePtr RoundTowardsZero(const BaseSemantics::SValuePtr &expr); - }; - -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// Instruction processors -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - - namespace AmdgpuVega { - -/** Base class for all Amdgpu Vega instruction processors. - * - * This class provides single-letter names for some types that are used in all instructions: D, I, A, and Ops for the - * dispatcher raw pointer, instruction pointer, argument list pointer, and RISC operators raw pointer. It also takes care - * of advancing the instruction pointer prior to handing the instruction to the subclass, which by the way is done via - * @ref p method (short for "process"). See examples in DispatcherX86.C -- there are lots of them. */ - class InsnProcessor : public BaseSemantics::InsnProcessor { - public: - typedef DispatcherAmdgpuVega *D; - typedef BaseSemantics::RiscOperators *Ops; - typedef SgAsmAmdgpuVegaInstruction *I; - typedef const SgAsmExpressionPtrList &A; - typedef uint32_t B; - - virtual void p(D, Ops, I, A, B) = 0; - - virtual void process(const BaseSemantics::DispatcherPtr &, SgAsmInstruction *); - - virtual void assert_args(I insn, A args, size_t nargs); - //void check_arg_width(D d, I insn, A args); - - public: - enum MemOp { - MemOp_STORE, - MemOp_LOAD - }; - - enum MoveWideOp { - MoveWideOp_N, - MoveWideOp_Z, - MoveWideOp_K - }; - - enum LogicalOp { - LogicalOp_AND, - LogicalOp_ORR, - LogicalOp_EOR - }; - - enum ShiftType { - ShiftType_LSL, - ShiftType_LSR, - ShiftType_ASR, - ShiftType_ROR - }; - - enum CountOp { - CountOp_CLZ, - CountOp_CLS, - CountOp_CNT - }; - }; - - } // namespace - - } // namespace - } // namespace -} // namespace - -#endif diff --git a/dataflowAPI/rose/semantics/DispatcherPowerpc.h b/dataflowAPI/rose/semantics/DispatcherPowerpc.h index 41f6678946..e0f82775dc 100644 --- a/dataflowAPI/rose/semantics/DispatcherPowerpc.h +++ b/dataflowAPI/rose/semantics/DispatcherPowerpc.h @@ -9,6 +9,8 @@ #ifndef ROSE_DispatcherPpc_H #define ROSE_DispatcherPpc_H +#include +#include #include "BaseSemantics2.h" #include "../SgAsmPowerpcInstruction.h" #include "external/rose/powerpcInstructionEnum.h" @@ -18,7 +20,7 @@ namespace BinaryAnalysis { namespace InstructionSemantics2 { /** Shared-ownership pointer to a PowerPC instruction dispatcher. See @ref heap_object_shared_ownership. */ -typedef boost::shared_ptr DispatcherPowerpcPtr; +typedef dyncompat::shared_ptr DispatcherPowerpcPtr; class DispatcherPowerpc: public BaseSemantics::Dispatcher { protected: @@ -73,7 +75,7 @@ class DispatcherPowerpc: public BaseSemantics::Dispatcher { /** Dynamic cast to a DispatcherPowerpcPtr with assertion. */ static DispatcherPowerpcPtr promote(const BaseSemantics::DispatcherPtr &d) { - DispatcherPowerpcPtr retval = boost::dynamic_pointer_cast(d); + DispatcherPowerpcPtr retval = dyncompat::dynamic_pointer_cast(d); assert(retval!=NULL); return retval; } diff --git a/dataflowAPI/rose/semantics/MemoryMap.C b/dataflowAPI/rose/semantics/MemoryMap.C index 31c3880624..d35c937040 100644 --- a/dataflowAPI/rose/semantics/MemoryMap.C +++ b/dataflowAPI/rose/semantics/MemoryMap.C @@ -1,4 +1,5 @@ //#include "sage3basic.h" +#include #include "../util/StringUtility.h" //#include "Diagnostics.h" @@ -7,11 +8,11 @@ #include "../util/rose_getline.h" #include "../util/rose_strtoull.h" -#include -#include +#include +#include -#include -#ifndef BOOST_WINDOWS +#include +#ifndef _WIN32 # include // for open() # include // for ptrace() # include // for waitpid() @@ -125,7 +126,7 @@ MemoryMap::segmentTitle(const Segment &segment) { size_t MemoryMap::insertFile(const std::string &fileName, rose_addr_t startVa, bool writable, std::string segmentName) { if (segmentName.empty()) - segmentName = FileSystem::toString(boost::filesystem::path(fileName).filename()); + segmentName = FileSystem::toString(std::filesystem::path(fileName).filename()); Segment segment = Segment::fileInstance(fileName, READABLE | (writable?WRITABLE:0), segmentName); AddressInterval fileInterval = AddressInterval::baseSize(startVa, segment.buffer()->size()); insert(fileInterval, segment); @@ -246,7 +247,7 @@ MemoryMap::insertFile(const std::string &locatorString) { std::string fileName = s; if (fileName.size()!=strlen(fileName.c_str())) throw insertFileError(locatorString, "invalid file name"); - std::string segmentName = FileSystem::toString(boost::filesystem::path(fileName).filename()); + std::string segmentName = FileSystem::toString(std::filesystem::path(fileName).filename()); //-------------------------------- // Open the file and read the data @@ -264,7 +265,7 @@ MemoryMap::insertFile(const std::string &locatorString) { // If no file size was specified then try to get one, or delay getting one until later. On POSIX systems we can use stat // to get the file size, which is useful because infinite devices (like /dev/zero) will return zero. Otherwise we'll get // the file size by trying to read from the file. -#if !defined(BOOST_WINDOWS) // not targeting Windows; i.e., not Microsoft C++ and not MinGW +#if !defined(_WIN32) // not targeting Windows; i.e., not Microsoft C++ and not MinGW if (!optionalFSize) { struct stat sb; if (0==stat(fileName.c_str(), &sb)) @@ -317,7 +318,7 @@ MemoryMap::insertFile(const std::string &locatorString) { // Choose accessibility if (!optionalAccess) { -#ifdef BOOST_WINDOWS +#ifdef _WIN32 optionalAccess = READABLE | WRITABLE; #else unsigned a = 0; @@ -383,7 +384,7 @@ insertProcessError(const std::string &locatorString, const std::string &mesg) { // FIXME[Robb P. Matzke 2014-10-09]: No idea how to do this in Microsoft Windows! void MemoryMap::insertProcess(const std::string &locatorString) { -#ifdef BOOST_WINDOWS // FIXME[Robb P. Matzke 2014-10-10] +#ifdef _WIN32 // FIXME[Robb P. Matzke 2014-10-10] throw std::runtime_error("MemoryMap::insertProcess is not available on Microsoft Windows"); #else @@ -413,7 +414,7 @@ MemoryMap::insertProcess(const std::string &locatorString) { if (':'!=*s++) throw insertProcessError(locatorString, "initial colon expected"); while (':'!=*s) { - if (boost::starts_with(s, "noattach")) { + if (dyncompat::starts_with(s, "noattach")) { doAttach = false; s += strlen("noattach"); } else { @@ -439,7 +440,7 @@ MemoryMap::insertProcess(const std::string &locatorString) { throw insertProcessError(locatorString, "process exited before it could be read"); if (WIFSIGNALED(wstat)) throw insertProcessError(locatorString, "process died with " + - boost::to_lower_copy(std::string(strsignal(WTERMSIG(wstat)))) + + dyncompat::to_lower_copy(std::string(strsignal(WTERMSIG(wstat)))) + " before it could be read"); local.resumeProcess = pid; ASSERT_require2(WIFSTOPPED(wstat) && WSTOPSIG(wstat)==SIGSTOP, "subordinate process did not stop"); @@ -521,7 +522,7 @@ MemoryMap::insertProcess(const std::string &locatorString) { continue; //mlog[WARN] <= minsize) toRemove.insert(zeroInterval); - BOOST_FOREACH (const AddressInterval &interval, toRemove.intervals()) + DYN_FOREACH (const AddressInterval &interval, toRemove.intervals()) erase(interval); } @@ -692,7 +693,7 @@ MemoryMap::dump(std::ostream &out, std::string prefix) const return; } - BOOST_FOREACH (const Node &node, nodes()) { + DYN_FOREACH (const Node &node, nodes()) { const AddressInterval &range = node.key(); const Segment &segment = node.value(); out < +#include +#include +#include +#include #include "ByteOrder.h" #include "../util/Access.h" @@ -51,7 +56,7 @@ T alignDown(T address, T alignment) { * initialize(myData, myDataSize); * * // Create the two buffers: one for the file, one for the overlay data - * Buffer::Ptr fileBuf = MappedBuffer::instance("the_file", boost::iostreams::mapped_file::readonly); + * Buffer::Ptr fileBuf = MappedBuffer::instance("the_file", 0); * Buffer::Ptr dataBuf = StaticBuffer::instance(myData, myDataSize); * * // Create the memory map. diff --git a/dataflowAPI/rose/semantics/RegisterParts.C b/dataflowAPI/rose/semantics/RegisterParts.C index 88fad3001d..48636d2016 100644 --- a/dataflowAPI/rose/semantics/RegisterParts.C +++ b/dataflowAPI/rose/semantics/RegisterParts.C @@ -1,8 +1,12 @@ +#include #include "../util/StringUtility.h" //#include "sage3basic.h" +#include #include "Registers.h" +#include #include "RegisterParts.h" -#include +#include +#include namespace rose { namespace BinaryAnalysis { @@ -19,8 +23,8 @@ RegisterParts::erase(const RegisterDescriptor ®) { RegisterParts& RegisterParts::operator-=(const RegisterParts &other) { - BOOST_FOREACH (const Map::Node &node, other.map_.nodes()) { - BOOST_FOREACH (const BitRange &bits, node.value().intervals()) + DYN_FOREACH (const Map::Node &node, other.map_.nodes()) { + DYN_FOREACH (const BitRange &bits, node.value().intervals()) erase(RegisterDescriptor(node.key().get_major(), node.key().get_minor(), bits.least(), bits.size())); } return *this; @@ -35,7 +39,7 @@ RegisterParts::operator-(const RegisterParts &other) const { RegisterParts& RegisterParts::operator|=(const RegisterParts &other) { - BOOST_FOREACH (const Map::Node &node, other.map_.nodes()) + DYN_FOREACH (const Map::Node &node, other.map_.nodes()) map_.insertMaybeDefault(node.key()).insertMultiple(node.value()); return *this; } @@ -49,7 +53,7 @@ RegisterParts::operator|(const RegisterParts &other) const { RegisterParts& RegisterParts::operator&=(const RegisterParts &other) { - BOOST_FOREACH (const Map::Node &node, other.map_.nodes()) { + DYN_FOREACH (const Map::Node &node, other.map_.nodes()) { if (map_.exists(node.key())) { BitSet &set = map_[node.key()]; set.eraseMultiple(node.value()); @@ -74,10 +78,10 @@ RegisterParts::extract(const RegisterDictionary *regDict, bool extractAll) { return retval; if (regDict) { - BOOST_FOREACH (const RegisterDictionary::Entries::value_type &pair, regDict->get_registers()) + DYN_FOREACH (const RegisterDictionary::Entries::value_type &pair, regDict->get_registers()) allRegs.push_back(pair.second); std::sort(allRegs.begin(), allRegs.end(), RegisterDictionary::SortBySize(RegisterDictionary::SortBySize::DESCENDING)); - BOOST_FOREACH (const RegisterDescriptor ®, allRegs) { + DYN_FOREACH (const RegisterDescriptor ®, allRegs) { if (existsAll(reg)) { retval.push_back(reg); erase(reg); @@ -88,8 +92,8 @@ RegisterParts::extract(const RegisterDictionary *regDict, bool extractAll) { } if (!regDict || extractAll) { - BOOST_FOREACH (const Map::Node &node, map_.nodes()) { - BOOST_FOREACH (const BitRange &bits, node.value().intervals()) + DYN_FOREACH (const Map::Node &node, map_.nodes()) { + DYN_FOREACH (const BitRange &bits, node.value().intervals()) retval.push_back(RegisterDescriptor(node.key().get_major(), node.key().get_minor(), bits.least(), bits.size())); } clear(); diff --git a/dataflowAPI/rose/semantics/RegisterParts.h b/dataflowAPI/rose/semantics/RegisterParts.h index 2fc2a16b0a..39846c11bd 100644 --- a/dataflowAPI/rose/semantics/RegisterParts.h +++ b/dataflowAPI/rose/semantics/RegisterParts.h @@ -1,6 +1,8 @@ #ifndef ROSE_BinaryAnalysis_RegisterParts_H #define ROSE_BinaryAnalysis_RegisterParts_H +#include +#include #include "../util/IntervalSet.h" #include "../util/Map.h" #include "../RegisterDescriptor.h" diff --git a/dataflowAPI/rose/semantics/RegisterStateGeneric.C b/dataflowAPI/rose/semantics/RegisterStateGeneric.C index c6f4a22bca..1dc5342341 100644 --- a/dataflowAPI/rose/semantics/RegisterStateGeneric.C +++ b/dataflowAPI/rose/semantics/RegisterStateGeneric.C @@ -1,3 +1,4 @@ +#include #include "../util/StringUtility.h" //#include //#include @@ -86,9 +87,9 @@ RegisterStateGeneric::assertStorageConditions(const std::string &when, const Reg ++ncalls; #endif std::ostringstream error; - BOOST_FOREACH (const Registers::Node &rnode, registers_.nodes()) { + DYN_FOREACH (const Registers::Node &rnode, registers_.nodes()) { Sawyer::Container::IntervalSet foundLocations; - BOOST_FOREACH (const RegPair ®pair, rnode.value()) { + DYN_FOREACH (const RegPair ®pair, rnode.value()) { if (!regpair.desc.is_valid()) { error <<"invalid register descriptor"; } else if (regpair.desc.get_major() != rnode.key().majr || regpair.desc.get_minor() != rnode.key().minr) { @@ -111,7 +112,7 @@ RegisterStateGeneric::assertStorageConditions(const std::string &when, const Reg /*mlog[FATAL] < Locations; Locations newLocations; newLocations.insert(accessedLocation); - BOOST_FOREACH (const RegPair ®pair, accessedParts) + DYN_FOREACH (const RegPair ®pair, accessedParts) newLocations -= regpair.location(); // Create values for the parts of the accessed register that weren't stored in the state, but don't store them yet. RegPairs newParts; if (accessCreatesLocations_) { - BOOST_FOREACH (const BitRange &newLocation, newLocations.intervals()) { + DYN_FOREACH (const BitRange &newLocation, newLocations.intervals()) { RegisterDescriptor subreg(reg.get_major(), reg.get_minor(), newLocation.least(), newLocation.size()); ASSERT_require(newLocation.least() >= reg.get_offset()); SValuePtr newval = ops->extract(dflt, @@ -237,7 +238,7 @@ RegisterStateGeneric::readRegister(const RegisterDescriptor ®, const SValuePt RegPairs retvalParts = accessedParts; retvalParts.insert(retvalParts.end(), newParts.begin(), newParts.end()); std::sort(retvalParts.begin(), retvalParts.end(), sortByOffset); - BOOST_FOREACH (const RegPair ®pair, retvalParts) + DYN_FOREACH (const RegPair ®pair, retvalParts) retval = retval ? ops->concat(retval, regpair.value) : regpair.value; ASSERT_require(retval->get_width() == reg.get_nbits()); @@ -279,7 +280,7 @@ RegisterStateGeneric::writeRegister(const RegisterDescriptor ®, const SValueP // Check that we're allowed to add storage locations if necessary. if (!accessCreatesLocations_) { size_t nBitsFound = 0; - BOOST_FOREACH (const RegPair ®pair, registers_.getOrDefault(reg)) + DYN_FOREACH (const RegPair ®pair, registers_.getOrDefault(reg)) nBitsFound += (regpair.location() & accessedLocation).size(); ASSERT_require(nBitsFound <= accessedLocation.size()); if (nBitsFound < accessedLocation.size()) @@ -297,7 +298,7 @@ RegisterStateGeneric::writeRegister(const RegisterDescriptor ®, const SValueP typedef Sawyer::Container::IntervalSet Locations; Locations newLocations; newLocations.insert(accessedLocation); - BOOST_FOREACH (const RegPair ®pair, accessedParts) + DYN_FOREACH (const RegPair ®pair, accessedParts) newLocations -= regpair.location(); // Update the register state by writing to the accessed area. @@ -309,7 +310,7 @@ RegisterStateGeneric::writeRegister(const RegisterDescriptor ®, const SValueP pairList.push_back(RegPair(reg, value)); } else { // Don't insert/erase locations that existed already -- only change their values. - BOOST_FOREACH (RegPair ®pair, pairList) { + DYN_FOREACH (RegPair ®pair, pairList) { BitRange storedLocation = regpair.location(); if (BitRange overlap = storedLocation & accessedLocation) { SValuePtr valueToWrite; @@ -339,7 +340,7 @@ RegisterStateGeneric::writeRegister(const RegisterDescriptor ®, const SValueP } // Insert the parts that didn't exist before - BOOST_FOREACH (const BitRange &newLocation, newLocations.intervals()) { + DYN_FOREACH (const BitRange &newLocation, newLocations.intervals()) { size_t extractBegin = newLocation.least() - accessedLocation.least(); size_t extractEnd = extractBegin + newLocation.size(); SValuePtr valueToWrite = ops->extract(value, extractBegin, extractEnd); @@ -363,7 +364,7 @@ RegisterStateGeneric::updateReadProperties(const RegisterDescriptor ®) { insertProperties(reg, IO_READ); BitProperties &props = properties_.insertMaybeDefault(reg); BitRange where = BitRange::baseSize(reg.get_offset(), reg.get_nbits()); - BOOST_FOREACH (BitProperties::Node &node, props.findAll(where)) { + DYN_FOREACH (BitProperties::Node &node, props.findAll(where)) { if (!node.value().exists(IO_WRITE)) { node.value().insert(IO_READ_BEFORE_WRITE); if (!node.value().exists(IO_INIT)) @@ -391,7 +392,7 @@ RegisterStateGeneric::erase_register(const RegisterDescriptor ®, RiscOperator // need to eventually add the non-overlapping part back into the list. RegPairs nonoverlaps; // the non-overlapping parts of overlapping registers Extent need_extent(reg.get_offset(), reg.get_nbits()); - BOOST_FOREACH (RegPair ®_val, pairList) { + DYN_FOREACH (RegPair ®_val, pairList) { BitRange haveLocation = reg_val.location(); if (BitRange intersection = accessedLocation & haveLocation) { if (haveLocation.least() < intersection.least()) { @@ -419,7 +420,7 @@ RegisterStateGeneric::RegPairs RegisterStateGeneric::get_stored_registers() const { RegPairs retval; - BOOST_FOREACH (const RegPairs &pairlist, registers_.values()) + DYN_FOREACH (const RegPairs &pairlist, registers_.values()) retval.insert(retval.end(), pairlist.begin(), pairlist.end()); return retval; } @@ -427,8 +428,8 @@ RegisterStateGeneric::get_stored_registers() const void RegisterStateGeneric::traverse(Visitor &visitor) { - BOOST_FOREACH (RegPairs &pairlist, registers_.values()) { - BOOST_FOREACH (RegPair &pair, pairlist) { + DYN_FOREACH (RegPairs &pairlist, registers_.values()) { + DYN_FOREACH (RegPair &pair, pairlist) { if (SValuePtr newval = (visitor)(pair.desc, pair.value)) { ASSERT_require(newval->get_width() == pair.desc.get_nbits()); pair.value = newval; @@ -440,8 +441,8 @@ RegisterStateGeneric::traverse(Visitor &visitor) void RegisterStateGeneric::deep_copy_values() { - BOOST_FOREACH (RegPairs &pairlist, registers_.values()) { - BOOST_FOREACH (RegPair &pair, pairlist) + DYN_FOREACH (RegPairs &pairlist, registers_.values()) { + DYN_FOREACH (RegPair &pair, pairlist) pair.value = pair.value->copy(); } } @@ -450,7 +451,7 @@ bool RegisterStateGeneric::is_partly_stored(const RegisterDescriptor &desc) const { BitRange want = BitRange::baseSize(desc.get_offset(), desc.get_nbits()); - BOOST_FOREACH (const RegPair &pair, registers_.getOrDefault(desc)) { + DYN_FOREACH (const RegPair &pair, registers_.getOrDefault(desc)) { if (want & pair.location()) return true; } @@ -462,7 +463,7 @@ RegisterStateGeneric::is_wholly_stored(const RegisterDescriptor &desc) const { Sawyer::Container::IntervalSet desired; desired.insert(BitRange::baseSize(desc.get_offset(), desc.get_nbits())); - BOOST_FOREACH (const RegPair &pair, registers_.getOrDefault(desc)) + DYN_FOREACH (const RegPair &pair, registers_.getOrDefault(desc)) desired -= pair.location(); return desired.isEmpty(); } @@ -470,7 +471,7 @@ RegisterStateGeneric::is_wholly_stored(const RegisterDescriptor &desc) const bool RegisterStateGeneric::is_exactly_stored(const RegisterDescriptor &desc) const { - BOOST_FOREACH (const RegPair &pair, registers_.getOrDefault(desc)) { + DYN_FOREACH (const RegPair &pair, registers_.getOrDefault(desc)) { if (desc == pair.desc) return true; } @@ -482,7 +483,7 @@ RegisterStateGeneric::stored_parts(const RegisterDescriptor &desc) const { ExtentMap retval; Extent want(desc.get_offset(), desc.get_nbits()); - BOOST_FOREACH (const RegPair &pair, registers_.getOrDefault(desc)) { + DYN_FOREACH (const RegPair &pair, registers_.getOrDefault(desc)) { Extent have(pair.desc.get_offset(), pair.desc.get_nbits()); retval.insert(want.intersect(have)); } @@ -494,7 +495,7 @@ RegisterStateGeneric::overlappingRegisters(const RegisterDescriptor &needle) con ASSERT_require(needle.is_valid()); BitRange needleBits = BitRange::baseSize(needle.get_offset(), needle.get_nbits()); RegPairs retval; - BOOST_FOREACH (const RegPair &pair, registers_.getOrDefault(needle)) { + DYN_FOREACH (const RegPair &pair, registers_.getOrDefault(needle)) { if (needleBits & pair.location()) retval.push_back(pair); } @@ -702,15 +703,15 @@ std::vector RegisterStateGeneric::findProperties(const InputOutputPropertySet &required, const InputOutputPropertySet &prohibited) const { std::vector retval; typedef Sawyer::Container::IntervalSet Bits; - BOOST_FOREACH (const RegisterProperties::Node ®Node, properties_.nodes()) { + DYN_FOREACH (const RegisterProperties::Node ®Node, properties_.nodes()) { unsigned majr = regNode.key().majr; unsigned minr = regNode.key().minr; Bits bits; - BOOST_FOREACH (const BitProperties::Node &bitNode, regNode.value().nodes()) { + DYN_FOREACH (const BitProperties::Node &bitNode, regNode.value().nodes()) { if (bitNode.value().existsAll(required) && !bitNode.value().existsAny(prohibited)) bits.insert(bitNode.key()); } - BOOST_FOREACH (const BitRange &bitRange, bits.intervals()) { + DYN_FOREACH (const BitRange &bitRange, bits.intervals()) { RegisterDescriptor reg(majr, minr, bitRange.least(), bitRange.size()); retval.push_back(reg); } @@ -721,12 +722,12 @@ RegisterStateGeneric::findProperties(const InputOutputPropertySet &required, con bool RegisterStateGeneric::merge(const BaseSemantics::RegisterStatePtr &other_, RiscOperators *ops) { ASSERT_not_null(ops); - RegisterStateGenericPtr other = boost::dynamic_pointer_cast(other_); + RegisterStateGenericPtr other = dyncompat::dynamic_pointer_cast(other_); ASSERT_not_null(other); bool changed = false; // Merge values stored in registers. - BOOST_FOREACH (const RegPair &otherRegVal, other->get_stored_registers()) { + DYN_FOREACH (const RegPair &otherRegVal, other->get_stored_registers()) { const RegisterDescriptor &otherReg = otherRegVal.desc; const BaseSemantics::SValuePtr &otherValue = otherRegVal.value; if (is_partly_stored(otherReg)) { @@ -744,10 +745,10 @@ RegisterStateGeneric::merge(const BaseSemantics::RegisterStatePtr &other_, RiscO } // Merge writer sets. - BOOST_FOREACH (const RegisterAddressSet::Node &wmNode, other->writers_.nodes()) { + DYN_FOREACH (const RegisterAddressSet::Node &wmNode, other->writers_.nodes()) { const BitAddressSet &otherWriters = wmNode.value(); BitAddressSet &thisWriters = writers_.insertMaybeDefault(wmNode.key()); - BOOST_FOREACH (const BitAddressSet::Node &otherWritten, otherWriters.nodes()) { + DYN_FOREACH (const BitAddressSet::Node &otherWritten, otherWriters.nodes()) { bool inserted = thisWriters.insert(otherWritten.key(), otherWritten.value()); if (inserted) changed = true; @@ -755,10 +756,10 @@ RegisterStateGeneric::merge(const BaseSemantics::RegisterStatePtr &other_, RiscO } // Merge property sets. - BOOST_FOREACH (const RegisterProperties::Node &otherRegNode, other->properties_.nodes()) { + DYN_FOREACH (const RegisterProperties::Node &otherRegNode, other->properties_.nodes()) { const BitProperties &otherBitProps = otherRegNode.value(); BitProperties &thisBitProps = properties_.insertMaybeDefault(otherRegNode.key()); - BOOST_FOREACH (const BitProperties::Node &otherBitNode, otherBitProps.nodes()) { + DYN_FOREACH (const BitProperties::Node &otherBitNode, otherBitProps.nodes()) { bool inserted = thisBitProps.insert(otherBitNode.key(), otherBitNode.value()); if (inserted) changed = true; @@ -780,10 +781,10 @@ RegisterStateGeneric::print(std::ostream &stream, Formatter &fmt) const FormatRestorer oflags(stream); size_t maxlen = 6; // use at least this many columns even if register names are short. for (int i=0; i<2; ++i) { - BOOST_FOREACH (const RegPairs &pl, registers_.values()) { + DYN_FOREACH (const RegPairs &pl, registers_.values()) { RegPairs regPairs = pl; std::sort(regPairs.begin(), regPairs.end(), sortByOffset); - BOOST_FOREACH (const RegPair &pair, regPairs) { + DYN_FOREACH (const RegPair &pair, regPairs) { std::string regname = regnames(pair.desc); if (!fmt.get_suppress_initial_values() || pair.value->get_comment().empty() || 0!=pair.value->get_comment().compare(regname+"_0")) { diff --git a/dataflowAPI/rose/semantics/RegisterStateGeneric.h b/dataflowAPI/rose/semantics/RegisterStateGeneric.h index e73ef1ee8a..7a1f08d973 100644 --- a/dataflowAPI/rose/semantics/RegisterStateGeneric.h +++ b/dataflowAPI/rose/semantics/RegisterStateGeneric.h @@ -1,6 +1,11 @@ #ifndef ROSE_BinaryAnalysis_InstructionSemantics2_RegisterStateGeneric_H #define ROSE_BinaryAnalysis_InstructionSemantics2_RegisterStateGeneric_H +#include +#include +#include +#include +#include #include "BaseSemantics2.h" namespace rose { @@ -9,7 +14,7 @@ namespace InstructionSemantics2 { namespace BaseSemantics { /** Shared-ownership pointer to generic register states. See @ref heap_object_shared_ownership. */ -typedef boost::shared_ptr RegisterStateGenericPtr; +typedef dyncompat::shared_ptr RegisterStateGenericPtr; /** A RegisterState for any architecture. * @@ -191,7 +196,7 @@ class RegisterStateGeneric: public RegisterState { /** Run-time promotion of a base register state pointer to a RegisterStateGeneric pointer. This is a checked conversion--it * will fail if @p from does not point to a RegisterStateGeneric object. */ static RegisterStateGenericPtr promote(const RegisterStatePtr &from) { - RegisterStateGenericPtr retval = boost::dynamic_pointer_cast(from); + RegisterStateGenericPtr retval = dyncompat::dynamic_pointer_cast(from); ASSERT_not_null(retval); return retval; } diff --git a/dataflowAPI/rose/semantics/Registers.C b/dataflowAPI/rose/semantics/Registers.C index 16278408fd..118dc0f295 100644 --- a/dataflowAPI/rose/semantics/Registers.C +++ b/dataflowAPI/rose/semantics/Registers.C @@ -1,11 +1,15 @@ +#include #include "../util/StringUtility.h" //#include "sage3basic.h" +#include #include "Registers.h" +#include #include "external/rose/armv8InstructionEnum.h" +#include #include "external/rose/amdgpuInstructionEnum.h" #include "external/rose/rose-compat.h" #include "external/rose/powerpcInstructionEnum.h" -#include +#include #include // These are here temporarily until the classes in this file can be moved into rose::BinaryAnalysis @@ -190,7 +194,7 @@ RegisterDictionary::resize(const std::string &name, unsigned new_nbits) { RegisterParts RegisterDictionary::getAllParts() const { RegisterParts retval; - BOOST_FOREACH (const Entries::value_type &node, forward) + DYN_FOREACH (const Entries::value_type &node, forward) retval.insert(node.second); return retval; } @@ -245,368 +249,24 @@ RegisterDictionary::print(std::ostream &o) const { } } -/** Intel 8086 registers. - * - * The Intel 8086 has fourteen 16-bit registers. Four of them (AX, BX, CX, DX) are general registers (although each may have - * an additional purpose; for example only CX can be used as a counter with the loop instruction). Each can be accessed as two - * separate bytes (thus BX's high byte can be accessed as BH and low byte as BL). Four segment registers (CS, DS, SS and ES) - * are used to form a memory address. There are two pointer registers. SP points to the bottom of the stack and BP which is - * used to point at some other place in the stack or the memory(Offset). Two registers (SI and DI) are for array - * indexing. The FLAGS register contains flags such as carry flag, overflow flag and zero flag. Finally, the instruction - * pointer (IP) points to the next instruction that will be fetched from memory and then executed. */ -//const RegisterDictionary * -//RegisterDictionary::dictionary_i8086() { -// static RegisterDictionary *regs = NULL; -// if (!regs) { -// regs = new RegisterDictionary("i8086"); -// -// /* 16-bit general purpose registers. Each has three names depending on which bytes are reference. */ -// regs->insert("al", x86_regclass_gpr, x86_gpr_ax, 0, 8); -// regs->insert("ah", x86_regclass_gpr, x86_gpr_ax, 8, 8); -// regs->insert("ax", x86_regclass_gpr, x86_gpr_ax, 0, 16); -// -// regs->insert("bl", x86_regclass_gpr, x86_gpr_bx, 0, 8); -// regs->insert("bh", x86_regclass_gpr, x86_gpr_bx, 8, 8); -// regs->insert("bx", x86_regclass_gpr, x86_gpr_bx, 0, 16); -// -// regs->insert("cl", x86_regclass_gpr, x86_gpr_cx, 0, 8); -// regs->insert("ch", x86_regclass_gpr, x86_gpr_cx, 8, 8); -// regs->insert("cx", x86_regclass_gpr, x86_gpr_cx, 0, 16); -// -// regs->insert("dl", x86_regclass_gpr, x86_gpr_dx, 0, 8); -// regs->insert("dh", x86_regclass_gpr, x86_gpr_dx, 8, 8); -// regs->insert("dx", x86_regclass_gpr, x86_gpr_dx, 0, 16); -// -// /* 16-bit segment registers */ -// regs->insert("cs", x86_regclass_segment, x86_segreg_cs, 0, 16); -// regs->insert("ds", x86_regclass_segment, x86_segreg_ds, 0, 16); -// regs->insert("ss", x86_regclass_segment, x86_segreg_ss, 0, 16); -// regs->insert("es", x86_regclass_segment, x86_segreg_es, 0, 16); -// -// /* 16-bit pointer registers */ -// regs->insert("sp", x86_regclass_gpr, x86_gpr_sp, 0, 16); /* stack pointer */ -// regs->insert("spl", x86_regclass_gpr, x86_gpr_sp, 0, 8); -// -// regs->insert("bp", x86_regclass_gpr, x86_gpr_bp, 0, 16); /* base pointer */ -// regs->insert("bpl", x86_regclass_gpr, x86_gpr_bp, 0, 8); -// -// regs->insert("ip", x86_regclass_ip, 0, 0, 16); /* instruction pointer */ -// regs->insert("ipl", x86_regclass_ip, 0, 0, 8); -// -// /* Array indexing registers */ -// regs->insert("si", x86_regclass_gpr, x86_gpr_si, 0, 16); -// regs->insert("sil", x86_regclass_gpr, x86_gpr_si, 0, 8); -// -// regs->insert("di", x86_regclass_gpr, x86_gpr_di, 0, 16); -// regs->insert("dil", x86_regclass_gpr, x86_gpr_di, 0, 8); -// -// /* Flags with official names. */ -// regs->insert("flags", x86_regclass_flags, x86_flags_status, 0, 16); /* all flags */ -// regs->insert("cf", x86_regclass_flags, x86_flags_status, 0, 1); /* carry status flag */ -// regs->insert("pf", x86_regclass_flags, x86_flags_status, 2, 1); /* parity status flag */ -// regs->insert("af", x86_regclass_flags, x86_flags_status, 4, 1); /* adjust status flag */ -// regs->insert("zf", x86_regclass_flags, x86_flags_status, 6, 1); /* zero status flag */ -// regs->insert("sf", x86_regclass_flags, x86_flags_status, 7, 1); /* sign status flag */ -// regs->insert("tf", x86_regclass_flags, x86_flags_status, 8, 1); /* trap system flag */ -// regs->insert("if", x86_regclass_flags, x86_flags_status, 9, 1); /* interrupt enable system flag */ -// regs->insert("df", x86_regclass_flags, x86_flags_status, 10, 1); /* direction control flag */ -// regs->insert("of", x86_regclass_flags, x86_flags_status, 11, 1); /* overflow status flag */ -// regs->insert("nt", x86_regclass_flags, x86_flags_status, 14, 1); /* nested task system flag */ -// -// /* Flags without names */ -// regs->insert("f1", x86_regclass_flags, x86_flags_status, 1, 1); -// regs->insert("f3", x86_regclass_flags, x86_flags_status, 3, 1); -// regs->insert("f5", x86_regclass_flags, x86_flags_status, 5, 1); -// regs->insert("f12", x86_regclass_flags, x86_flags_status, 12, 1); -// regs->insert("f13", x86_regclass_flags, x86_flags_status, 13, 1); -// regs->insert("f15", x86_regclass_flags, x86_flags_status, 15, 1); -// } -// return regs; -//} -// -///** Intel 8088 registers. -// * -// * Intel 8088 has the same set of registers as Intel 8086. */ -//const RegisterDictionary * -//RegisterDictionary::dictionary_i8088() -//{ -// static RegisterDictionary *regs = NULL; -// if (!regs) { -// regs = new RegisterDictionary("i8088"); -// regs->insert(dictionary_i8086()); -// } -// return regs; -//} -// -///** Intel 80286 registers. -// * -// * The 80286 has the same registers as the 8086 but adds two new flags to the "flags" register. */ -//const RegisterDictionary * -//RegisterDictionary::dictionary_i286() -//{ -// static RegisterDictionary *regs = NULL; -// if (!regs) { -// regs = new RegisterDictionary("i286"); -// regs->insert(dictionary_i8086()); -// regs->insert("iopl", x86_regclass_flags, x86_flags_status, 12, 2); /* I/O privilege level flag */ -// regs->insert("nt", x86_regclass_flags, x86_flags_status, 14, 1); /* nested task system flag */ -// } -// return regs; -//} -// -///** Intel 80386 registers. -// * -// * The 80386 has the same registers as the 80286 but extends the general-purpose registers, base registers, index registers, -// * instruction pointer, and flags register to 32 bits. Register names from the 80286 refer to the same offsets and sizes while -// * the full 32 bits are accessed by names prefixed with "e" as in "eax" (the "e" means "extended"). Two new segment registers -// * (FS and GS) were added and all segment registers remain 16 bits. */ -//const RegisterDictionary * -//RegisterDictionary::dictionary_i386() -//{ -// static RegisterDictionary *regs = NULL; -// if (!regs) { -// regs = new RegisterDictionary("i386"); -// regs->insert(dictionary_i286()); -// -// /* Additional 32-bit registers */ -// regs->insert("eax", x86_regclass_gpr, x86_gpr_ax, 0, 32); -// regs->insert("ebx", x86_regclass_gpr, x86_gpr_bx, 0, 32); -// regs->insert("ecx", x86_regclass_gpr, x86_gpr_cx, 0, 32); -// regs->insert("edx", x86_regclass_gpr, x86_gpr_dx, 0, 32); -// regs->insert("esp", x86_regclass_gpr, x86_gpr_sp, 0, 32); -// regs->insert("ebp", x86_regclass_gpr, x86_gpr_bp, 0, 32); -// regs->insert("eip", x86_regclass_ip, 0, 0, 32); -// regs->insert("esi", x86_regclass_gpr, x86_gpr_si, 0, 32); -// regs->insert("edi", x86_regclass_gpr, x86_gpr_di, 0, 32); -// regs->insert("eflags", x86_regclass_flags, x86_flags_status, 0, 32); -// -// /* Additional 16-bit segment registers */ -// regs->insert("fs", x86_regclass_segment, x86_segreg_fs, 0, 16); -// regs->insert("gs", x86_regclass_segment, x86_segreg_gs, 0, 16); -// -// /* Additional flags */ -// regs->insert("rf", x86_regclass_flags, x86_flags_status, 16, 1); /* resume system flag */ -// regs->insert("vm", x86_regclass_flags, x86_flags_status, 17, 1); /* virtual 8086 mode flag */ -// -// /* Additional flag bits that have no official names */ -// for (unsigned i=18; i<32; ++i) -// regs->insert("f"+StringUtility::numberToString(i), x86_regclass_flags, x86_flags_status, i, 1); -// -// /* Control registers */ -// regs->insert("cr0", x86_regclass_cr, 0, 0, 32); -// regs->insert("cr1", x86_regclass_cr, 1, 0, 32); -// regs->insert("cr2", x86_regclass_cr, 2, 0, 32); -// regs->insert("cr3", x86_regclass_cr, 3, 0, 32); -// regs->insert("cr4", x86_regclass_cr, 4, 0, 32); -// -// /* Debug registers */ -// regs->insert("dr0", x86_regclass_dr, 0, 0, 32); -// regs->insert("dr1", x86_regclass_dr, 1, 0, 32); -// regs->insert("dr2", x86_regclass_dr, 2, 0, 32); -// regs->insert("dr3", x86_regclass_dr, 3, 0, 32); /* dr4 and dr5 are reserved */ -// regs->insert("dr6", x86_regclass_dr, 6, 0, 32); -// regs->insert("dr7", x86_regclass_dr, 7, 0, 32); -// -// } -// return regs; -//} -// -///** Intel 80386 with 80387 math co-processor. */ -//const RegisterDictionary * -//RegisterDictionary::dictionary_i386_387() -//{ -// static RegisterDictionary *regs = NULL; -// if (!regs) { -// regs = new RegisterDictionary("i386 w/387"); -// regs->insert(dictionary_i386()); -// -// // The 387 contains eight floating-point registers that have no names (we call them "st0" through "st7"), and defines -// // expressions of the form "st(n)" to refer to the current nth register from the top of a circular stack. These -// // expressions are implemented usng SgAsmIndexedRegisterExpression IR nodes, which have a base register which is -// // "st0", a stride which increments the minor number, an offset which is the current top-of-stack value, an index -// // which is the value "n" in the expression "st(n)", and a modulus of eight. The current top-of-stack value is held in -// // the three-bit register "fpstatus_top", which normally has a concrete value. -// regs->insert("st0", x86_regclass_st, x86_st_0, 0, 80); -// regs->insert("st1", x86_regclass_st, x86_st_1, 0, 80); -// regs->insert("st2", x86_regclass_st, x86_st_2, 0, 80); -// regs->insert("st3", x86_regclass_st, x86_st_3, 0, 80); -// regs->insert("st4", x86_regclass_st, x86_st_4, 0, 80); -// regs->insert("st5", x86_regclass_st, x86_st_5, 0, 80); -// regs->insert("st6", x86_regclass_st, x86_st_6, 0, 80); -// regs->insert("st7", x86_regclass_st, x86_st_7, 0, 80); -// -// // Floating-point tag registers, two bits per ST register. -// regs->insert("fptag", x86_regclass_flags, x86_flags_fptag, 0, 16); // all tags -// regs->insert("fptag_st0", x86_regclass_flags, x86_flags_fptag, 0, 2); // tag for st0 -// regs->insert("fptag_st1", x86_regclass_flags, x86_flags_fptag, 2, 2); // tag for st1 -// regs->insert("fptag_st2", x86_regclass_flags, x86_flags_fptag, 4, 2); // tag for st2 -// regs->insert("fptag_st3", x86_regclass_flags, x86_flags_fptag, 6, 2); // tag for st3 -// regs->insert("fptag_st4", x86_regclass_flags, x86_flags_fptag, 8, 2); // tag for st4 -// regs->insert("fptag_st5", x86_regclass_flags, x86_flags_fptag, 10, 2); // tag for st5 -// regs->insert("fptag_st6", x86_regclass_flags, x86_flags_fptag, 12, 2); // tag for st6 -// regs->insert("fptag_st7", x86_regclass_flags, x86_flags_fptag, 14, 2); // tag for st7 -// -// // Floating-point status register -// regs->insert("fpstatus", x86_regclass_flags, x86_flags_fpstatus, 0, 16); -// regs->insert("fpstatus_ie", x86_regclass_flags, x86_flags_fpstatus, 0, 1); // invalid operation -// regs->insert("fpstatus_de", x86_regclass_flags, x86_flags_fpstatus, 1, 1); // denormalized operand -// regs->insert("fpstatus_ze", x86_regclass_flags, x86_flags_fpstatus, 2, 1); // zero divide -// regs->insert("fpstatus_oe", x86_regclass_flags, x86_flags_fpstatus, 3, 1); // overflow -// regs->insert("fpstatus_ue", x86_regclass_flags, x86_flags_fpstatus, 4, 1); // underflow -// regs->insert("fpstatus_pe", x86_regclass_flags, x86_flags_fpstatus, 5, 1); // precision -// regs->insert("fpstatus_ir", x86_regclass_flags, x86_flags_fpstatus, 7, 1); // interrupt request -// regs->insert("fpstatus_c4", x86_regclass_flags, x86_flags_fpstatus, 8, 1); // condition code -// regs->insert("fpstatus_c1", x86_regclass_flags, x86_flags_fpstatus, 9, 1); // condition code -// regs->insert("fpstatus_c2", x86_regclass_flags, x86_flags_fpstatus, 10, 1); // condition code -// regs->insert("fpstatus_top", x86_regclass_flags, x86_flags_fpstatus, 11, 3); // top of stack -// regs->insert("fpstatus_c3", x86_regclass_flags, x86_flags_fpstatus, 14, 1); // condition code -// regs->insert("fpstatus_b", x86_regclass_flags, x86_flags_fpstatus, 15, 1); // busy -// -// // Floating-point control register -// regs->insert("fpctl", x86_regclass_flags, x86_flags_fpctl, 0, 16); -// regs->insert("fpctl_im", x86_regclass_flags, x86_flags_fpctl, 0, 1); // invalid operation -// regs->insert("fpctl_dm", x86_regclass_flags, x86_flags_fpctl, 1, 1); // denormalized operand -// regs->insert("fpctl_zm", x86_regclass_flags, x86_flags_fpctl, 2, 1); // zero divide -// regs->insert("fpctl_om", x86_regclass_flags, x86_flags_fpctl, 3, 1); // overflow -// regs->insert("fpctl_um", x86_regclass_flags, x86_flags_fpctl, 4, 1); // underflow -// regs->insert("fpctl_pm", x86_regclass_flags, x86_flags_fpctl, 5, 1); // precision -// regs->insert("fpctl_m", x86_regclass_flags, x86_flags_fpctl, 7, 1); // interrupt mask -// regs->insert("fpctl_pc", x86_regclass_flags, x86_flags_fpctl, 8, 2); // precision control -// regs->insert("fpctl_rc", x86_regclass_flags, x86_flags_fpctl, 10, 2); // rounding control -// regs->insert("fpctl_ic", x86_regclass_flags, x86_flags_fpctl, 12, 1); // infinity control -// } -// return regs; -//} -// -// -///** Intel 80486 registers. -// * -// * The 80486 has the same registers as the 80386 with '387 co-processor but adds a new flag to the "eflags" register. */ -//const RegisterDictionary * -//RegisterDictionary::dictionary_i486() -//{ -// static RegisterDictionary *regs = NULL; -// if (!regs) { -// regs = new RegisterDictionary("i486"); -// regs->insert(dictionary_i386_387()); -// regs->insert("ac", x86_regclass_flags, x86_flags_status, 18, 1); /* alignment check system flag */ -// } -// return regs; -//} -// -///** Intel Pentium registers. -// * -// * The Pentium has the same registers as the 80486 but adds a few flags to the "eflags" register and MMX registers. */ -//const RegisterDictionary * -//RegisterDictionary::dictionary_pentium() -//{ -// static RegisterDictionary *regs = NULL; -// if (!regs) { -// regs = new RegisterDictionary("pentium"); -// regs->insert(dictionary_i486()); -// -// /* Additional flags */ -// regs->insert("vif", x86_regclass_flags, x86_flags_status, 19, 1); /* virtual interrupt flag */ -// regs->insert("vip", x86_regclass_flags, x86_flags_status, 20, 1); /* virt interrupt pending */ -// regs->insert("id", x86_regclass_flags, x86_flags_status, 21, 1); /* ident system flag */ -// -// /* The MMi registers are aliases for the ST(i) registers but are absolute rather than relative to the top of the -// * stack. We're creating the static definitions, so MMi will point to the same storage as ST(i) for 0<=i<=7. Note that -// * a write to one of the 64-bit MMi registers causes the high-order 16 bits of the corresponding ST(j) register to be -// * set to all ones to indicate a NaN value. */ -// regs->insert("mm0", x86_regclass_st, x86_st_0, 0, 64); -// regs->insert("mm1", x86_regclass_st, x86_st_1, 0, 64); -// regs->insert("mm2", x86_regclass_st, x86_st_2, 0, 64); -// regs->insert("mm3", x86_regclass_st, x86_st_3, 0, 64); -// regs->insert("mm4", x86_regclass_st, x86_st_4, 0, 64); -// regs->insert("mm5", x86_regclass_st, x86_st_5, 0, 64); -// regs->insert("mm6", x86_regclass_st, x86_st_6, 0, 64); -// regs->insert("mm7", x86_regclass_st, x86_st_7, 0, 64); -// } -// return regs; -//} -// -///** Intel Pentium III registers. -// * -// * The Pentium III has the same register set as the Pentium but adds the xmm0 through xmm7 registers for the SSE instruction -// * set. */ -//const RegisterDictionary * -//RegisterDictionary::dictionary_pentiumiii() -//{ -// static RegisterDictionary *regs = NULL; -// if (!regs) { -// regs = new RegisterDictionary("pentiumiii"); -// regs->insert(dictionary_pentium()); -// regs->insert("xmm0", x86_regclass_xmm, 0, 0, 128); -// regs->insert("xmm1", x86_regclass_xmm, 1, 0, 128); -// regs->insert("xmm2", x86_regclass_xmm, 2, 0, 128); -// regs->insert("xmm3", x86_regclass_xmm, 3, 0, 128); -// regs->insert("xmm4", x86_regclass_xmm, 4, 0, 128); -// regs->insert("xmm5", x86_regclass_xmm, 5, 0, 128); -// regs->insert("xmm6", x86_regclass_xmm, 6, 0, 128); -// regs->insert("xmm7", x86_regclass_xmm, 7, 0, 128); -// -// /** SSE status and control register. */ -// regs->insert("mxcsr", x86_regclass_flags, x86_flags_mxcsr, 0, 32); -// regs->insert("mxcsr_ie", x86_regclass_flags, x86_flags_mxcsr, 0, 1); // invalid operation flag -// regs->insert("mxcsr_de", x86_regclass_flags, x86_flags_mxcsr, 1, 1); // denormal flag -// regs->insert("mxcsr_ze", x86_regclass_flags, x86_flags_mxcsr, 2, 1); // divide by zero flag -// regs->insert("mxcsr_oe", x86_regclass_flags, x86_flags_mxcsr, 3, 1); // overflow flag -// regs->insert("mxcsr_ue", x86_regclass_flags, x86_flags_mxcsr, 4, 1); // underflow flag -// regs->insert("mxcsr_pe", x86_regclass_flags, x86_flags_mxcsr, 5, 1); // precision flag -// regs->insert("mxcsr_daz", x86_regclass_flags, x86_flags_mxcsr, 6, 1); // denormals are zero -// regs->insert("mxcsr_im", x86_regclass_flags, x86_flags_mxcsr, 7, 1); // invalid operation mask -// regs->insert("mxcsr_dm", x86_regclass_flags, x86_flags_mxcsr, 8, 1); // denormal mask -// regs->insert("mxcsr_zm", x86_regclass_flags, x86_flags_mxcsr, 9, 1); // divide by zero mask -// regs->insert("mxcsr_om", x86_regclass_flags, x86_flags_mxcsr, 10, 1); // overflow mask -// regs->insert("mxcsr_um", x86_regclass_flags, x86_flags_mxcsr, 11, 1); // underflow mask -// regs->insert("mxcsr_pm", x86_regclass_flags, x86_flags_mxcsr, 12, 1); // precision mask -// regs->insert("mxcsr_r", x86_regclass_flags, x86_flags_mxcsr, 13, 2); // rounding mode -// regs->insert("mxcsr_fz", x86_regclass_flags, x86_flags_mxcsr, 15, 1); // flush to zero -// } -// return regs; -//} -// -///** Intel Pentium 4 registers. */ -//const RegisterDictionary * -//RegisterDictionary::dictionary_pentium4() -//{ -// static RegisterDictionary *regs = NULL; -// if (!regs) { -// regs = new RegisterDictionary("pentium4"); -// regs->insert(dictionary_pentiumiii()); -// } -// return regs; -//} -// - - /** AMDGPU Registers * Scalar Registers : total 104 registers of 32 bits * */ const RegisterDictionary * -RegisterDictionary::dictionary_amdgpu_vega() { +RegisterDictionary::dictionary_amdgpu() { static std::once_flag initialized; static RegisterDictionary *regs = NULL; std::call_once(initialized, []() { - regs = new RegisterDictionary("amdgpu_vega"); + regs = new RegisterDictionary("AMDGPU"); - /* All 60 variations (32- and 64-bit) of the 32 general purpose registers */ for (unsigned idx = 0; idx < 104; idx++) { regs->insert("sgpr" + StringUtility::numberToString(idx), amdgpu_regclass_sgpr, amdgpu_sgpr0 + idx, 0, 32); } - /* 64-bit program counter register */ - regs->insert("pc", amdgpu_regclass_pc, 0, 0, 64); - - regs->insert("scc", amdgpu_regclass_hwr, amdgpu_status, 0, 1); - - - /* 32-bit pstate register and the four relevant flags.*/ - /* Each flag is added as a separate register for individual access. Only allowed minor is 0 (since there is only one pstate register); - * the different offsets indicate the positions of the flags within the pstate register. */ + regs->insert("pc_all", amdgpu_regclass_pc, 0, 0, 64); + regs->insert("src_scc", amdgpu_regclass_hwr, amdgpu_status, 0, 1); }); return regs; } diff --git a/dataflowAPI/rose/semantics/Registers.h b/dataflowAPI/rose/semantics/Registers.h index 633b853b43..8e406305cb 100644 --- a/dataflowAPI/rose/semantics/Registers.h +++ b/dataflowAPI/rose/semantics/Registers.h @@ -5,6 +5,11 @@ #include "../util/Map.h" #include "RegisterParts.h" +#include +#include +#include +#include +#include #include #include #include @@ -35,25 +40,12 @@ class RegisterDictionary { typedef std::vector RegisterDescriptors; /* Functions that return a dictionary for a particular machine architecute. (See implementation for documentation.) */ - /*static const RegisterDictionary *dictionary_i8086(); // Intel 8086 - static const RegisterDictionary *dictionary_i8088(); // Intel 8088 - static const RegisterDictionary *dictionary_i286(); // Intel 80286 - static const RegisterDictionary *dictionary_i386(); // Intel 80386 - static const RegisterDictionary *dictionary_i386_387(); // Intel 80386 with 80387 math coprocessor - static const RegisterDictionary *dictionary_i486(); // Intel 80486 - static const RegisterDictionary *dictionary_pentium(); // Intel Pentium - static const RegisterDictionary *dictionary_pentiumiii(); // Intel Pentium III - static const RegisterDictionary *dictionary_pentium4(); // Intel Pentium 4 - static const RegisterDictionary *dictionary_amd64(); // AMD Athlon 64*/ static const RegisterDictionary *dictionary_armv8(); // ARMv8-A architecture - static const RegisterDictionary *dictionary_amdgpu_vega(); // ARMv8-A architecture + static const RegisterDictionary *dictionary_amdgpu(); // AMDGPU architecture static const RegisterDictionary *dictionary_powerpc(); - RegisterDictionary(const std::string &name) - :name(name) {} - RegisterDictionary(const RegisterDictionary& other) { - *this = other; - } + RegisterDictionary(const std::string &name_) + :name(name_) {} /** Obtain the name of the dictionary. */ const std::string &get_architecture_name() const { @@ -62,8 +54,8 @@ class RegisterDictionary { /** Set the name of the dictionary. Dictionary names are generally architecture names. Dictionaries created by one of the * built-in static methods of this class have the same name as the method that created it. */ - void set_architecture_name(const std::string &name) { - this->name = name; + void set_architecture_name(const std::string &name_) { + this->name = name_; } /** Insert a definition into the dictionary. If the name already exists in the dictionary then the new RegisterDescriptor diff --git a/dataflowAPI/rose/semantics/SMTSolver.C b/dataflowAPI/rose/semantics/SMTSolver.C index 4d3386202c..dcc0188376 100644 --- a/dataflowAPI/rose/semantics/SMTSolver.C +++ b/dataflowAPI/rose/semantics/SMTSolver.C @@ -6,8 +6,8 @@ #include "../util/rose_getline.h" #include "SMTSolver.h" -#include -#include +#include +#include #include /*for O_RDWR, etc.*/ #include "../util/Stopwatch.h" @@ -21,7 +21,7 @@ namespace rose { } SMTSolver::Stats SMTSolver::class_stats; - boost::mutex SMTSolver::class_stats_mutex; + dyncompat::mutex SMTSolver::class_stats_mutex; void SMTSolver::init() { } @@ -29,14 +29,14 @@ namespace rose { // class method SMTSolver::Stats SMTSolver::get_class_stats() { - boost::lock_guard lock(class_stats_mutex); + dyncompat::lock_guard lock(class_stats_mutex); return class_stats; } // class method void SMTSolver::reset_class_stats() { - boost::lock_guard lock(class_stats_mutex); + dyncompat::lock_guard lock(class_stats_mutex); class_stats = Stats(); } @@ -80,7 +80,7 @@ namespace rose { // Keep track of how often we call the SMT solver. ++stats.ncalls; { - boost::lock_guard lock(class_stats_mutex); + dyncompat::lock_guard lock(class_stats_mutex); ++class_stats.ncalls; } output_text = ""; @@ -120,7 +120,7 @@ namespace rose { //ASSERT_require(status >= 0); stats.input_size += sb.st_size; { - boost::lock_guard lock(class_stats_mutex); + dyncompat::lock_guard lock(class_stats_mutex); class_stats.input_size += sb.st_size; } @@ -148,7 +148,7 @@ namespace rose { while ((nread = rose_getline(&line, &line_alloc, output)) > 0) { stats.output_size += nread; { - boost::lock_guard lock(class_stats_mutex); + dyncompat::lock_guard lock(class_stats_mutex); class_stats.output_size += nread; } if (!got_satunsat_line) { diff --git a/dataflowAPI/rose/semantics/SMTSolver.h b/dataflowAPI/rose/semantics/SMTSolver.h index cf031f114c..23304b8521 100644 --- a/dataflowAPI/rose/semantics/SMTSolver.h +++ b/dataflowAPI/rose/semantics/SMTSolver.h @@ -1,8 +1,13 @@ #ifndef Rose_SMTSolver_H #define Rose_SMTSolver_H +#include +#include +#include +#include +#include #include "BinarySymbolicExpr.h" -#include +#include /* Enable type formatting macros, not enabled by default in C++ */ #ifndef __STDC_FORMAT_MACROS @@ -19,7 +24,7 @@ namespace rose { class SMTSolver { public: struct Exception { - Exception(const std::string &mesg) : mesg(mesg) { } + Exception(const std::string &mesg_) : mesg(mesg_) { } friend std::ostream &operator<<(std::ostream &, const SMTSolver::Exception &); @@ -75,7 +80,7 @@ namespace rose { virtual SymbolicExpr::Ptr evidence_for_variable(uint64_t varno) { char buf[64]; //FIXME - snprintf(buf, sizeof(buf), "v%llu"/*PRIu64*/, varno); + snprintf(buf, sizeof(buf), "v%" PRIu64, varno); return evidence_for_name(buf); } @@ -141,13 +146,13 @@ namespace rose { /** Parses evidence of satisfiability. Some solvers can emit information about what variable bindings satisfy the * expression. This information is parsed by this function and added to a mapping of variable to value. */ - virtual void parse_evidence() { }; + virtual void parse_evidence() { } /** Additional output obtained by satisfiable(). */ std::string output_text; // Statistics - static boost::mutex class_stats_mutex; + static dyncompat::mutex class_stats_mutex; static Stats class_stats; // all access must be protected by class_stats_mutex Stats stats; diff --git a/dataflowAPI/rose/semantics/SymEvalSemantics.C b/dataflowAPI/rose/semantics/SymEvalSemantics.C index 0467fff718..be9273992c 100644 --- a/dataflowAPI/rose/semantics/SymEvalSemantics.C +++ b/dataflowAPI/rose/semantics/SymEvalSemantics.C @@ -2,10 +2,15 @@ // Created by ssunny on 7/1/16. // -#include +#include #include "SymEvalSemantics.h" +#include "Register.h" +#include "BaseSemantics2.h" +#include "dyn_regs.h" + using namespace rose::BinaryAnalysis::InstructionSemantics2; +using RoseException = BaseSemantics::Exception; /////////////////////////////////////////////////////// // StateAST @@ -95,60 +100,155 @@ Dyninst::Absloc SymEvalSemantics::RegisterStateAST::convert(const RegisterDescri ASSERT_always_forbid("converting ROSE register to Dyninst register is platform specific, should not call this base class method."); } - -Dyninst::Absloc SymEvalSemantics::RegisterStateAST_AMDGPU_VEGA::convert(const RegisterDescriptor ®) { +Dyninst::Absloc SymEvalSemantics::RegisterStateAST_amdgpu_gfx908::convert(const RegisterDescriptor ®) { Dyninst::MachRegister mreg; unsigned int major = reg.get_major(); unsigned int minor = reg.get_minor(); unsigned int size = reg.get_nbits(); unsigned int offset = reg.get_offset(); - //std::cout << "in func " << __func__ << " major = " << major << " minor = " << minor << std::endl; + //std::cout << "in func " << __func__ << " major = " << major << " minor = " << minor << std::endl; bool found = false; switch (major) { - case amdgpu_regclass_sgpr_vec2 : { - Dyninst::MachRegister base = Dyninst::amdgpu_vega::sgpr_vec2_0; - - // std::cout << "dealing with sgpr pair in , offset = " << minor << std::endl; - mreg = Dyninst::MachRegister(base.val() + minor) ; - found = true; + case amdgpu_regclass_sgpr : { + Dyninst::MachRegister base = Dyninst::amdgpu_gfx908::s0; + //std::cout << "dealing with sgpr pair in , offset = " << minor << std::endl; + mreg = Dyninst::MachRegister(base.val() + minor) ; + + found = true; + break; + } + case amdgpu_regclass_pc : { + mreg = Dyninst::amdgpu_gfx908::pc_all; + + found = true; + break; + } + case amdgpu_regclass_hwr : { + switch(minor){ + case amdgpu_status:{ + switch (offset) { + case 0: + mreg = Dyninst::amdgpu_gfx908::src_scc; + found = true; + break; + default: + break; + } break; } - case amdgpu_regclass_sgpr : { - Dyninst::MachRegister base = Dyninst::amdgpu_vega::sgpr0; - //std::cout << "dealing with sgpr pair in , offset = " << minor << std::endl; - mreg = Dyninst::MachRegister(base.val() + minor) ; - - found = true; + default: break; + } - case amdgpu_regclass_pc : { - mreg = Dyninst::amdgpu_vega::pc; + break; + } + default: + ASSERT_always_forbid("Unexpected register major type."); + } + if(found) + return Dyninst::Absloc(mreg); + + ASSERT_always_forbid("Unexpected register major type."); +} + +Dyninst::Absloc SymEvalSemantics::RegisterStateAST_amdgpu_gfx90a::convert(const RegisterDescriptor ®) { + Dyninst::MachRegister mreg; - found = true; + unsigned int major = reg.get_major(); + unsigned int minor = reg.get_minor(); + unsigned int size = reg.get_nbits(); + unsigned int offset = reg.get_offset(); + //std::cout << "in func " << __func__ << " major = " << major << " minor = " << minor << std::endl; + bool found = false; + switch (major) { + case amdgpu_regclass_sgpr : { + Dyninst::MachRegister base = Dyninst::amdgpu_gfx90a::s0; + //std::cout << "dealing with sgpr pair in , offset = " << minor << std::endl; + mreg = Dyninst::MachRegister(base.val() + minor) ; + + found = true; + break; + } + case amdgpu_regclass_pc : { + mreg = Dyninst::amdgpu_gfx90a::pc_all; + + found = true; + break; + } + case amdgpu_regclass_hwr : { + switch(minor){ + case amdgpu_status:{ + switch (offset) { + case 0: + mreg = Dyninst::amdgpu_gfx90a::src_scc; + found = true; + break; + default: + break; + } break; } - case amdgpu_regclass_hwr : { - switch(minor){ - case amdgpu_status:{ - switch (offset) { - case 0: - mreg = Dyninst::amdgpu_vega::scc; - found = true; - break; - default: - break; - } - break; - } - default: - break; + default: + break; + } + break; + } + default: + ASSERT_always_forbid("Unexpected register major type."); + } + if(found) + return Dyninst::Absloc(mreg); + + ASSERT_always_forbid("Unexpected register major type."); +} + +Dyninst::Absloc SymEvalSemantics::RegisterStateAST_amdgpu_gfx940::convert(const RegisterDescriptor ®) { + Dyninst::MachRegister mreg; + + unsigned int major = reg.get_major(); + unsigned int minor = reg.get_minor(); + unsigned int size = reg.get_nbits(); + unsigned int offset = reg.get_offset(); + //std::cout << "in func " << __func__ << " major = " << major << " minor = " << minor << std::endl; + bool found = false; + switch (major) { + case amdgpu_regclass_sgpr : { + Dyninst::MachRegister base = Dyninst::amdgpu_gfx940::s0; + //std::cout << "dealing with sgpr pair in , offset = " << minor << std::endl; + mreg = Dyninst::MachRegister(base.val() + minor) ; + + found = true; + break; + } + case amdgpu_regclass_pc : { + mreg = Dyninst::amdgpu_gfx940::pc_all; + + found = true; + break; + } + case amdgpu_regclass_hwr : { + switch(minor){ + case amdgpu_status:{ + switch (offset) { + case 0: + mreg = Dyninst::amdgpu_gfx940::src_scc; + found = true; + break; + default: + break; } break; } default: - ASSERT_always_forbid("Unexpected register major type."); + break; + + } + break; + } + default: + ASSERT_always_forbid("Unexpected register major type."); } if(found) return Dyninst::Absloc(mreg); @@ -156,6 +256,7 @@ Dyninst::Absloc SymEvalSemantics::RegisterStateAST_AMDGPU_VEGA::convert(const Re ASSERT_always_forbid("Unexpected register major type."); } + Dyninst::Absloc SymEvalSemantics::RegisterStateASTARM64::convert(const RegisterDescriptor ®) { Dyninst::MachRegister mreg; @@ -194,7 +295,8 @@ Dyninst::Absloc SymEvalSemantics::RegisterStateASTARM64::convert(const RegisterD break; case 128: base = Dyninst::aarch64::q0; break; - default:assert(!"invalid size of RegisterDescriptor!"); + default: + throw RoseException("invalid size of RegisterDescriptor!", nullptr); break; } mreg = Dyninst::MachRegister(base.val() + (minor - armv8_simdfpr_v0)); @@ -267,13 +369,13 @@ Dyninst::Absloc SymEvalSemantics::RegisterStateASTPPC32::convert(const RegisterD Dyninst::MachRegister base = Dyninst::ppc32::cr0l; mreg = Dyninst::MachRegister(base.val() + offset); } else { - assert(!"bad cr register size"); + throw RoseException("bad cr register size", nullptr); } } break; case powerpc_regclass_fpscr: - assert(!"not implemented register class fpscr"); + throw RoseException("not implemented register class fpscr", nullptr); break; case powerpc_regclass_spr: { @@ -298,12 +400,12 @@ Dyninst::Absloc SymEvalSemantics::RegisterStateASTPPC32::convert(const RegisterD mreg = Dyninst::ppc32::dec; break; default: - assert(!"not implemented special register"); + throw RoseException("not implemented special register", nullptr); } } break; case powerpc_regclass_tbr: - assert(!"not implemented regclass tbr"); + throw RoseException("not implemented regclass tbr", nullptr); break; case powerpc_regclass_msr: @@ -311,7 +413,7 @@ Dyninst::Absloc SymEvalSemantics::RegisterStateASTPPC32::convert(const RegisterD break; case powerpc_regclass_sr: - assert(!"not implemented regclass sr"); + throw RoseException("not implemented regclass sr", nullptr); break; case powerpc_regclass_iar: @@ -361,13 +463,13 @@ Dyninst::Absloc SymEvalSemantics::RegisterStateASTPPC64::convert(const RegisterD Dyninst::MachRegister base = Dyninst::ppc64::cr0l; mreg = Dyninst::MachRegister(base.val() + offset); } else { - assert(!"bad cr register size"); + throw RoseException("bad cr register size", nullptr); } } break; case powerpc_regclass_fpscr: - assert(!"not implemented register class fpscr"); + throw RoseException("not implemented register class fpscr", nullptr); break; case powerpc_regclass_spr: { @@ -392,12 +494,12 @@ Dyninst::Absloc SymEvalSemantics::RegisterStateASTPPC64::convert(const RegisterD mreg = Dyninst::ppc64::dec; break; default: - assert(!"not implemented special register"); + throw RoseException("not implemented special register", nullptr); } } break; case powerpc_regclass_tbr: - assert(!"not implemented regclass tbr"); + throw RoseException("not implemented regclass tbr", nullptr); break; case powerpc_regclass_msr: @@ -405,7 +507,7 @@ Dyninst::Absloc SymEvalSemantics::RegisterStateASTPPC64::convert(const RegisterD break; case powerpc_regclass_sr: - assert(!"not implemented regclass sr"); + throw RoseException("not implemented regclass sr", nullptr); break; case powerpc_regclass_iar: diff --git a/dataflowAPI/rose/semantics/SymEvalSemantics.h b/dataflowAPI/rose/semantics/SymEvalSemantics.h index ad766e5bbb..e2d7010b94 100644 --- a/dataflowAPI/rose/semantics/SymEvalSemantics.h +++ b/dataflowAPI/rose/semantics/SymEvalSemantics.h @@ -5,10 +5,16 @@ #ifndef DYNINST_SYMEVALSEMANTICS_H #define DYNINST_SYMEVALSEMANTICS_H +#include +#include +#include +#include +#include #include "external/rose/armv8InstructionEnum.h" #include "external/rose/amdgpuInstructionEnum.h" #include "BaseSemantics2.h" #include "../../h/SymEval.h" +#include "dyntypes.h" namespace rose { namespace BinaryAnalysis { @@ -33,12 +39,12 @@ namespace rose { expr = Dyninst::DataflowAPI::ConstantAST::create(Dyninst::DataflowAPI::Constant(num, nbits)); } - SValue(Dyninst::AST::Ptr expr): BaseSemantics::SValue(64) { - this->expr = expr; + SValue(Dyninst::AST::Ptr expr_): BaseSemantics::SValue(64) { + this->expr = expr_; } // Added this version to set register size according to descriptor - SValue(Dyninst::AST::Ptr expr, size_t nbits ): BaseSemantics::SValue(nbits) { - this->expr = expr; + SValue(Dyninst::AST::Ptr expr_, size_t nbits ): BaseSemantics::SValue(nbits) { + this->expr = expr_; } public: static SValuePtr instance(Dyninst::Absloc r, Dyninst::Address addr) { @@ -63,12 +69,12 @@ namespace rose { return SValuePtr(new SValue(32, nbits)); } - virtual BaseSemantics::SValuePtr unspecified_(size_t nbits) const { + virtual BaseSemantics::SValuePtr unspecified_(size_t /*nbits*/) const { return SValuePtr(new SValue(Dyninst::DataflowAPI::BottomAST::create(false))); } //TODO - virtual BaseSemantics::SValuePtr bottom_(size_t nbits) const { + virtual BaseSemantics::SValuePtr bottom_(size_t /*nbits*/) const { return SValuePtr(new SValue(Dyninst::DataflowAPI::BottomAST::create(true))); } @@ -88,7 +94,7 @@ namespace rose { } virtual Sawyer::Optional - createOptionalMerge(const BaseSemantics::SValuePtr &other, const BaseSemantics::MergerPtr&, SMTSolver*) const { + createOptionalMerge(const BaseSemantics::SValuePtr &/*other*/, const BaseSemantics::MergerPtr&, SMTSolver*) const { ASSERT_not_implemented("SValue::createOptionalMerge not implemented for use in dyninst"); } @@ -115,7 +121,7 @@ namespace rose { virtual uint64_t get_number() const { assert(expr->getID() == Dyninst::AST::V_ConstantAST); //TODO - Dyninst::DataflowAPI::Constant constant = boost::dynamic_pointer_cast(expr)->val(); + Dyninst::DataflowAPI::Constant constant = dyncompat::dynamic_pointer_cast(expr)->val(); return constant.val; } @@ -128,16 +134,17 @@ namespace rose { /* Register State */ /***************************************************************************************************/ - typedef boost::shared_ptr RegisterStateASTPtr; - typedef boost::shared_ptr RegisterStateASTARM64Ptr; - typedef boost::shared_ptr RegisterStateASTPPC32Ptr; - typedef boost::shared_ptr RegisterStateASTPPC64Ptr; - typedef boost::shared_ptr RegisterStateAST_AMDGPU_VEGA_Ptr; - + typedef dyncompat::shared_ptr RegisterStateASTPtr; + typedef dyncompat::shared_ptr RegisterStateASTARM64Ptr; + typedef dyncompat::shared_ptr RegisterStateASTPPC32Ptr; + typedef dyncompat::shared_ptr RegisterStateASTPPC64Ptr; + typedef dyncompat::shared_ptr RegisterStateAST_amdgpu_gfx908_Ptr; + typedef dyncompat::shared_ptr RegisterStateAST_amdgpu_gfx90a_Ptr; + typedef dyncompat::shared_ptr RegisterStateAST_amdgpu_gfx940_Ptr; class RegisterStateAST : public BaseSemantics::RegisterState { public: RegisterStateAST(const BaseSemantics::SValuePtr &protoval, - const RegisterDictionary *regdict) : RegisterState(protoval, regdict) { } + const RegisterDictionary *regdict_) : RegisterState(protoval, regdict_) { } public: static RegisterStateASTPtr instance(const BaseSemantics::SValuePtr &protoval, @@ -146,8 +153,8 @@ namespace rose { } virtual BaseSemantics::RegisterStatePtr create(const BaseSemantics::SValuePtr &protoval, - const RegisterDictionary *regdict) const { - return instance(protoval, regdict); + const RegisterDictionary *regdict_) const { + return instance(protoval, regdict_); } virtual BaseSemantics::RegisterStatePtr clone() const { @@ -155,7 +162,7 @@ namespace rose { } static RegisterStateASTPtr promote(const BaseSemantics::RegisterStatePtr &from) { - RegisterStateASTPtr retval = boost::dynamic_pointer_cast(from); + RegisterStateASTPtr retval = dyncompat::dynamic_pointer_cast(from); ASSERT_not_null(retval); return retval; } @@ -174,7 +181,7 @@ namespace rose { virtual void print(std::ostream &, BaseSemantics::Formatter &) const {} - virtual bool merge(const BaseSemantics::RegisterStatePtr &other, BaseSemantics::RiscOperators *ops) { + virtual bool merge(const BaseSemantics::RegisterStatePtr &/*other*/, BaseSemantics::RiscOperators * /*ops*/) { return true; } @@ -194,7 +201,7 @@ namespace rose { class RegisterStateASTARM64 : public RegisterStateAST { public: RegisterStateASTARM64(const BaseSemantics::SValuePtr &protoval, - const RegisterDictionary *regdict) : RegisterStateAST(protoval, regdict) { } + const RegisterDictionary *regdict_) : RegisterStateAST(protoval, regdict_) { } static RegisterStateASTARM64Ptr instance(const BaseSemantics::SValuePtr &protoval, const RegisterDictionary *regdict) { @@ -202,7 +209,7 @@ namespace rose { } static RegisterStateASTARM64Ptr promote(const BaseSemantics::RegisterStatePtr &from) { - RegisterStateASTARM64Ptr retval = boost::dynamic_pointer_cast(from); + RegisterStateASTARM64Ptr retval = dyncompat::dynamic_pointer_cast(from); ASSERT_not_null(retval); return retval; } @@ -214,7 +221,7 @@ namespace rose { class RegisterStateASTPPC32 : public RegisterStateAST { public: RegisterStateASTPPC32(const BaseSemantics::SValuePtr &protoval, - const RegisterDictionary *regdict) : RegisterStateAST(protoval, regdict) { } + const RegisterDictionary *regdict_) : RegisterStateAST(protoval, regdict_) { } static RegisterStateASTPPC32Ptr instance(const BaseSemantics::SValuePtr &protoval, const RegisterDictionary *regdict) { @@ -222,7 +229,7 @@ namespace rose { } static RegisterStateASTPPC32Ptr promote(const BaseSemantics::RegisterStatePtr &from) { - RegisterStateASTPPC32Ptr retval = boost::dynamic_pointer_cast(from); + RegisterStateASTPPC32Ptr retval = dyncompat::dynamic_pointer_cast(from); ASSERT_not_null(retval); return retval; } @@ -233,7 +240,7 @@ namespace rose { class RegisterStateASTPPC64 : public RegisterStateAST { public: RegisterStateASTPPC64(const BaseSemantics::SValuePtr &protoval, - const RegisterDictionary *regdict) : RegisterStateAST(protoval, regdict) { } + const RegisterDictionary *regdict_) : RegisterStateAST(protoval, regdict_) { } static RegisterStateASTPPC64Ptr instance(const BaseSemantics::SValuePtr &protoval, const RegisterDictionary *regdict) { @@ -241,7 +248,7 @@ namespace rose { } static RegisterStateASTPPC64Ptr promote(const BaseSemantics::RegisterStatePtr &from) { - RegisterStateASTPPC64Ptr retval = boost::dynamic_pointer_cast(from); + RegisterStateASTPPC64Ptr retval = dyncompat::dynamic_pointer_cast(from); ASSERT_not_null(retval); return retval; } @@ -249,39 +256,74 @@ namespace rose { private: virtual Dyninst::Absloc convert(const RegisterDescriptor ®); }; - /** - * Register State AST for ADMGPU VEGA for Architecture - * (Copied from RegisterSTateASTARM64) - * - * - */ - class RegisterStateAST_AMDGPU_VEGA : public RegisterStateAST { - public: - RegisterStateAST_AMDGPU_VEGA(const BaseSemantics::SValuePtr &protoval, - const RegisterDictionary *regdict) : RegisterStateAST(protoval, regdict) { } + + class RegisterStateAST_amdgpu_gfx908 : public RegisterStateAST { + public: + RegisterStateAST_amdgpu_gfx908(const BaseSemantics::SValuePtr &protoval, + const RegisterDictionary *regdict_) : RegisterStateAST(protoval, regdict_) { } + + static RegisterStateAST_amdgpu_gfx908_Ptr instance(const BaseSemantics::SValuePtr &protoval, + const RegisterDictionary *regdict) { + return RegisterStateAST_amdgpu_gfx908_Ptr(new RegisterStateAST_amdgpu_gfx908(protoval, regdict)); + } - static RegisterStateAST_AMDGPU_VEGA_Ptr instance(const BaseSemantics::SValuePtr &protoval, - const RegisterDictionary *regdict) { - return RegisterStateAST_AMDGPU_VEGA_Ptr(new RegisterStateAST_AMDGPU_VEGA(protoval, regdict)); - } + static RegisterStateAST_amdgpu_gfx908_Ptr promote(const BaseSemantics::RegisterStatePtr &from) { + RegisterStateAST_amdgpu_gfx908_Ptr retval = dyncompat::dynamic_pointer_cast(from); + ASSERT_not_null(retval); + return retval; + } - static RegisterStateAST_AMDGPU_VEGA_Ptr promote(const BaseSemantics::RegisterStatePtr &from) { - RegisterStateAST_AMDGPU_VEGA_Ptr retval = boost::dynamic_pointer_cast(from); - ASSERT_not_null(retval); - return retval; - } + private: + // Given a register decriptor of roseformat, convert it back to MachRegister and encapsulate it in Dyninst Abstract location + virtual Dyninst::Absloc convert(const RegisterDescriptor ®); + }; - private: - // Given a register decriptor of roseformat, convert it back to MachRegister and encapsulate it in Dyninst Abstract location - virtual Dyninst::Absloc convert(const RegisterDescriptor ®); - }; - + class RegisterStateAST_amdgpu_gfx90a : public RegisterStateAST { + public: + RegisterStateAST_amdgpu_gfx90a(const BaseSemantics::SValuePtr &protoval, + const RegisterDictionary *regdict_) : RegisterStateAST(protoval, regdict_) { } + + static RegisterStateAST_amdgpu_gfx90a_Ptr instance(const BaseSemantics::SValuePtr &protoval, + const RegisterDictionary *regdict) { + return RegisterStateAST_amdgpu_gfx90a_Ptr(new RegisterStateAST_amdgpu_gfx90a(protoval, regdict)); + } + + static RegisterStateAST_amdgpu_gfx90a_Ptr promote(const BaseSemantics::RegisterStatePtr &from) { + RegisterStateAST_amdgpu_gfx90a_Ptr retval = dyncompat::dynamic_pointer_cast(from); + ASSERT_not_null(retval); + return retval; + } + + private: + // Given a register decriptor of roseformat, convert it back to MachRegister and encapsulate it in Dyninst Abstract location + virtual Dyninst::Absloc convert(const RegisterDescriptor ®); + }; + class RegisterStateAST_amdgpu_gfx940 : public RegisterStateAST { + public: + RegisterStateAST_amdgpu_gfx940(const BaseSemantics::SValuePtr &protoval, + const RegisterDictionary *regdict_) : RegisterStateAST(protoval, regdict_) { } + + static RegisterStateAST_amdgpu_gfx940_Ptr instance(const BaseSemantics::SValuePtr &protoval, + const RegisterDictionary *regdict) { + return RegisterStateAST_amdgpu_gfx940_Ptr(new RegisterStateAST_amdgpu_gfx940(protoval, regdict)); + } + + static RegisterStateAST_amdgpu_gfx940_Ptr promote(const BaseSemantics::RegisterStatePtr &from) { + RegisterStateAST_amdgpu_gfx940_Ptr retval = dyncompat::dynamic_pointer_cast(from); + ASSERT_not_null(retval); + return retval; + } + + private: + // Given a register decriptor of roseformat, convert it back to MachRegister and encapsulate it in Dyninst Abstract location + virtual Dyninst::Absloc convert(const RegisterDescriptor ®); + }; /***************************************************************************************************/ /* Memory State */ /***************************************************************************************************/ - typedef boost::shared_ptr MemoryStateASTPtr; + typedef dyncompat::shared_ptr MemoryStateASTPtr; class MemoryStateAST : public BaseSemantics::MemoryState { protected: @@ -298,7 +340,7 @@ namespace rose { } static MemoryStateASTPtr promote(const BaseSemantics::MemoryStatePtr &from) { - MemoryStateASTPtr retval = boost::dynamic_pointer_cast(from); + MemoryStateASTPtr retval = dyncompat::dynamic_pointer_cast(from); ASSERT_not_null(retval); return retval; } @@ -316,7 +358,7 @@ namespace rose { // } - virtual bool merge(const BaseSemantics::MemoryStatePtr &other, BaseSemantics::RiscOperators *addrOps, BaseSemantics::RiscOperators *valOps) { + virtual bool merge(const BaseSemantics::MemoryStatePtr &/*other*/, BaseSemantics::RiscOperators * /*addrOps*/, BaseSemantics::RiscOperators * /*valOps*/) { return true; } @@ -338,7 +380,7 @@ namespace rose { /* State */ /***************************************************************************************************/ - typedef boost::shared_ptr StateASTPtr; + typedef dyncompat::shared_ptr StateASTPtr; class StateAST : public BaseSemantics::State { public: @@ -347,24 +389,24 @@ namespace rose { Dyninst::Architecture ac, Dyninst::InstructionAPI::Instruction insn_, const BaseSemantics::RegisterStatePtr ®isters, - const BaseSemantics::MemoryStatePtr &memory): BaseSemantics::State(registers, memory), res(r), addr(a), arch(ac), insn(insn_) { + const BaseSemantics::MemoryStatePtr &memory): BaseSemantics::State(registers, memory), res(r), arch(ac), addr(a), insn(insn_) { for (Dyninst::DataflowAPI::Result_t::iterator iter = r.begin(); iter != r.end(); ++iter) { - Dyninst::Assignment::Ptr a = iter->first; + Dyninst::Assignment::Ptr ap = iter->first; // For a different instruction... - if (a->addr() != addr) + if (ap->addr() != addr) continue; - Dyninst::AbsRegion &o = a->out(); + Dyninst::AbsRegion &o = ap->out(); if (o.containsOfType(Dyninst::Absloc::Register)) { // We're assuming this is a single register... - //std::cerr << "Marking register " << a << std::endl; - aaMap[o.absloc()] = a; + //std::cerr << "Marking register " << ap << std::endl; + aaMap[o.absloc()] = ap; } else { // Use sufficiently-unique (Heap,0) Absloc // to represent a definition to a memory absloc - aaMap[Dyninst::Absloc(0)] = a; + aaMap[Dyninst::Absloc(0)] = ap; } } } @@ -379,6 +421,7 @@ namespace rose { return StateASTPtr(new StateAST(r, a, ac, insn_, registers, memory)); } + using BaseSemantics::State::create; virtual BaseSemantics::StatePtr create(Dyninst::DataflowAPI::Result_t &r, Dyninst::Address a, Dyninst::Architecture ac, @@ -389,7 +432,7 @@ namespace rose { } static StateASTPtr promote(const BaseSemantics::StatePtr &from) { - StateASTPtr retval = boost::dynamic_pointer_cast(from); + StateASTPtr retval = dyncompat::dynamic_pointer_cast(from); ASSERT_not_null(retval); return retval; } @@ -397,6 +440,7 @@ namespace rose { public: virtual BaseSemantics::SValuePtr readRegister(const RegisterDescriptor ®, const BaseSemantics::SValuePtr &dflt, BaseSemantics::RiscOperators *ops); virtual void writeRegister(const RegisterDescriptor ®, const BaseSemantics::SValuePtr &value, BaseSemantics::RiscOperators *ops); + using BaseSemantics::State::readMemory; virtual BaseSemantics::SValuePtr readMemory(const BaseSemantics::SValuePtr &address, const BaseSemantics::SValuePtr &dflt, BaseSemantics::RiscOperators *addrOps, BaseSemantics::RiscOperators *valOps, size_t readSize = 0); virtual void writeMemory(const BaseSemantics::SValuePtr &addr, const BaseSemantics::SValuePtr &value, BaseSemantics::RiscOperators *addrOps, @@ -417,7 +461,7 @@ namespace rose { /***************************************************************************************************/ /* RiscOperators */ /***************************************************************************************************/ - typedef boost::shared_ptr RiscOperatorsASTPtr; + typedef dyncompat::shared_ptr RiscOperatorsASTPtr; /** RISC operators for use by the Symbolic Semantics Domain of Dyninst. * @@ -459,7 +503,7 @@ namespace rose { /** Run-time promotion of a base RiscOperators pointer to symbolic operators. This is a checked conversion--it * will fail if @p x does not point to a SymbolicSemantics::RiscOperators object. */ static RiscOperatorsASTPtr promote(const BaseSemantics::RiscOperatorsPtr &x) { - RiscOperatorsASTPtr retval = boost::dynamic_pointer_cast(x); + RiscOperatorsASTPtr retval = dyncompat::dynamic_pointer_cast(x); ASSERT_not_null(retval); return retval; } diff --git a/dataflowAPI/rose/semanticsModule.h b/dataflowAPI/rose/semanticsModule.h index 93bd7497a8..d31fcdaffb 100644 --- a/dataflowAPI/rose/semanticsModule.h +++ b/dataflowAPI/rose/semanticsModule.h @@ -4,13 +4,7 @@ #include "SgAsmType.h" //#include "rose.h" -#if defined(_MSC_VER) -#include "external/stdint-win.h" -#include "external/inttypes-win.h" -#else -#include #include -#endif #ifndef __STDC_FORMAT_MACROS #define __STDC_FORMAT_MACROS diff --git a/dataflowAPI/rose/typedefs.h b/dataflowAPI/rose/typedefs.h index 65ecf0fe57..b56ad5799e 100644 --- a/dataflowAPI/rose/typedefs.h +++ b/dataflowAPI/rose/typedefs.h @@ -2,11 +2,7 @@ #define ROSE_TYPEDEFS_H #include -#if defined(_MSC_VER) -#include "external/stdint-win.h" -#else #include -#endif typedef std::vector SgUnsignedCharList; diff --git a/dataflowAPI/rose/util/AddressMap.h b/dataflowAPI/rose/util/AddressMap.h index d275ff7ece..250ce97608 100644 --- a/dataflowAPI/rose/util/AddressMap.h +++ b/dataflowAPI/rose/util/AddressMap.h @@ -17,11 +17,17 @@ #include "IntervalMap.h" #include "IntervalSet.h" #include "Sawyer.h" -#include -#include -#include -#include -#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include namespace Sawyer { namespace Container { @@ -165,7 +171,7 @@ class AddressMapConstraints { } if (!nameSubstring_.empty()) { out <<", substr=\""; - BOOST_FOREACH (char ch, nameSubstring_) { + DYN_FOREACH (char ch, nameSubstring_) { switch (ch) { case '\a': out <<"\\a"; break; case '\b': out <<"\\b"; break; @@ -305,12 +311,12 @@ class AddressMapConstraints { /** Limit addresses. See @ref AddressMap::after. */ AddressMapConstraints after(Address x) const { - return x==boost::integer_traits
::const_max ? none() : atOrAfter(x+1); + return x==dyncompat::integer_traits
::const_max ? none() : atOrAfter(x+1); } /** Limit addreses. See @ref AddressMap::before. */ AddressMapConstraints before(Address x) const { - return x==boost::integer_traits
::const_min ? none() : atOrBefore(x-1); + return x==dyncompat::integer_traits
::const_min ? none() : atOrBefore(x-1); } /** Limit matching to single segment. See @ref AddressMap::singleSegment. */ @@ -428,12 +434,12 @@ class AddressMapConstraints { //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// // Methods that directly call the AddressMap public: - boost::iterator_range::NodeIterator> + dyncompat::iterator_range::NodeIterator> nodes(MatchFlags flags=0) const { return map_->nodes(*this, flags); } - boost::iterator_range::SegmentIterator> + dyncompat::iterator_range::SegmentIterator> segments(MatchFlags flags=0) const { return map_->segments(*this, flags); } @@ -549,7 +555,7 @@ struct MatchedConstraints { typedef typename AddressMap::Address Address; Sawyer::Container::Interval
interval_; typedef typename AddressMapTraits::NodeIterator NodeIterator; - boost::iterator_range nodes_; + dyncompat::iterator_range nodes_; }; // Finds the minimum possible address and node iterator for the specified constraints in this map and returns that @@ -635,7 +641,7 @@ isSatisfied(const typename AddressMap::Node &node, const AddressMapConstraints::Args(node.key(), node.value()))) return false; // user-supplied predicates failed @@ -649,7 +655,7 @@ matchForward(AddressMap &amap, const AddressMapConstraints &c, Match typedef typename AddressMap::Address Address; typedef typename AddressMapTraits::NodeIterator Iterator; MatchedConstraints retval; - retval.nodes_ = boost::iterator_range(amap.nodes().end(), amap.nodes().end()); + retval.nodes_ = dyncompat::iterator_range(amap.nodes().end(), amap.nodes().end()); if (c.neverMatches() || amap.isEmpty()) return retval; @@ -708,7 +714,7 @@ matchForward(AddressMap &amap, const AddressMapConstraints &c, Match // Build the result retval.interval_ = Sawyer::Container::Interval
::hull(minAddr, maxAddr); - retval.nodes_ = boost::iterator_range(begin, end); + retval.nodes_ = dyncompat::iterator_range(begin, end); return retval; } @@ -719,7 +725,7 @@ matchBackward(AddressMap &amap, const AddressMapConstraints &c, Matc typedef typename AddressMap::Address Address; typedef typename AddressMapTraits::NodeIterator Iterator; MatchedConstraints retval; - retval.nodes_ = boost::iterator_range(amap.nodes().end(), amap.nodes().end()); + retval.nodes_ = dyncompat::iterator_range(amap.nodes().end(), amap.nodes().end()); if (c.neverMatches() || amap.isEmpty()) return retval; @@ -784,7 +790,7 @@ matchBackward(AddressMap &amap, const AddressMapConstraints &c, Matc // Build the result retval.interval_ = Sawyer::Container::Interval
::hull(minAddr, maxAddr); - retval.nodes_ = boost::iterator_range(begin, end); + retval.nodes_ = dyncompat::iterator_range(begin, end); return retval; } @@ -954,7 +960,7 @@ matchConstraints(AddressMap &amap, const AddressMapConstraints &c, M * causes problems for AddressMap because unqualified references to %Interval should refer to the * Sawyer::Container::Interval class template, but instead they refer to the @ref IntervalMap::Interval "Interval" typedef in * the base class. Our work around is to qualify all occurrences of %Interval where Microsoft compilers go wrong. */ -template +template class AddressMap: public IntervalMap, AddressSegment, AddressMapImpl::SegmentMergePolicy > { // "Interval" is qualified to work around bug in Microsoft compilers. See doxygen note above. typedef IntervalMap, AddressSegment, AddressMapImpl::SegmentMergePolicy > Super; @@ -991,7 +997,7 @@ class AddressMap: public IntervalMap, AddressSegment, AddressM * an @ref AllocatingBuffer. */ AddressMap(const AddressMap &other, bool copyOnWrite=false): Super(other) { if (copyOnWrite) { - BOOST_FOREACH (Segment &segment, this->values()) { + DYN_FOREACH (Segment &segment, this->values()) { if (const typename Buffer::Ptr &buffer = segment.buffer()) buffer->copyOnWrite(true); } @@ -1257,20 +1263,20 @@ class AddressMap: public IntervalMap, AddressSegment, AddressM * * @li Checks that the buffers of the map are appropriate sizes for the address interval in which they're mapped. */ void checkConsistency() const { - BOOST_FOREACH (const Node &node, nodes()) { + DYN_FOREACH (const Node &node, nodes()) { const Sawyer::Container::Interval
&interval = node.key(); const Segment &segment = node.value(); if (segment.buffer()==NULL) { throw std::runtime_error("AddressMap null buffer for interval [" + - boost::lexical_cast(interval.least()) + - "," + boost::lexical_cast(interval.greatest()) + "]"); + dyncompat::lexical_cast(interval.least()) + + "," + dyncompat::lexical_cast(interval.greatest()) + "]"); } Address bufAvail = segment.buffer()->available(segment.offset()); if (bufAvail < interval.size()) { - throw std::runtime_error("AddressMap segment at [" + boost::lexical_cast(interval.least()) + - "," + boost::lexical_cast(interval.greatest()) + "] points to only " + - boost::lexical_cast(bufAvail) + (1==bufAvail?" value":" values") + - " but the interval size is " + boost::lexical_cast(interval.size())); + throw std::runtime_error("AddressMap segment at [" + dyncompat::lexical_cast(interval.least()) + + "," + dyncompat::lexical_cast(interval.greatest()) + "] points to only " + + dyncompat::lexical_cast(bufAvail) + (1==bufAvail?" value":" values") + + " but the interval size is " + dyncompat::lexical_cast(interval.size())); } } } @@ -1288,8 +1294,8 @@ class AddressMap: public IntervalMap, AddressSegment, AddressM * This is just an alias for the @ref values method defined in the super class. * * @{ */ - boost::iterator_range segments() { return this->values(); } - boost::iterator_range segments() const { return this->values(); } + dyncompat::iterator_range segments() { return this->values(); } + dyncompat::iterator_range segments() const { return this->values(); } /** Segments that overlap with constraints. * @@ -1306,27 +1312,27 @@ class AddressMap: public IntervalMap, AddressSegment, AddressM * * @code * typedef AddressMap::Segment Segment; - * BOOST_FOREACH (Segment &segment, map.substr("IAT").segments(MATCH_NONCONTIGUOUS)) + * DYN_FOREACH (Segment &segment, map.substr("IAT").segments(MATCH_NONCONTIGUOUS)) * segment.accessibility(segment.accessibility() & ~EXECUTABLE); * @endcode * * @{ */ - boost::iterator_range + dyncompat::iterator_range segments(const AddressMapConstraints &c, MatchFlags flags=0) const { using namespace AddressMapImpl; if (0==(flags & (MATCH_CONTIGUOUS|MATCH_NONCONTIGUOUS))) flags |= MATCH_CONTIGUOUS; MatchedConstraints m = matchConstraints(*this, c, flags); - return boost::iterator_range(m.nodes_.begin(), m.nodes_.end()); + return dyncompat::iterator_range(m.nodes_.begin(), m.nodes_.end()); } - boost::iterator_range + dyncompat::iterator_range segments(const AddressMapConstraints &c, MatchFlags flags=0) { using namespace AddressMapImpl; if (0==(flags & (MATCH_CONTIGUOUS|MATCH_NONCONTIGUOUS))) flags |= MATCH_CONTIGUOUS; MatchedConstraints m = matchConstraints(*this, c, flags); - return boost::iterator_range(m.nodes_); + return dyncompat::iterator_range(m.nodes_); } /** @} */ @@ -1336,8 +1342,8 @@ class AddressMap: public IntervalMap, AddressSegment, AddressM * name that takes a constraint and thus returns only some nodes. * * @{ */ - boost::iterator_range nodes() { return Super::nodes(); } - boost::iterator_range nodes() const { return Super::nodes(); } + dyncompat::iterator_range nodes() { return Super::nodes(); } + dyncompat::iterator_range nodes() const { return Super::nodes(); } /** @} */ /** Nodes that overlap with constraints. @@ -1354,12 +1360,12 @@ class AddressMap: public IntervalMap, AddressSegment, AddressM * * @code * typedef AddressMap::Node Node; - * BOOST_FOREACH (const Node &node, map.within(1000,2000).substr("IAT").nodes(MATCH_NONCONTIGUOUS)) + * DYN_FOREACH (const Node &node, map.within(1000,2000).substr("IAT").nodes(MATCH_NONCONTIGUOUS)) * std::cout <<"segment at " < + dyncompat::iterator_range nodes(const AddressMapConstraints &c, MatchFlags flags=0) const { using namespace AddressMapImpl; if (0==(flags & (MATCH_CONTIGUOUS|MATCH_NONCONTIGUOUS))) @@ -1368,7 +1374,7 @@ class AddressMap: public IntervalMap, AddressSegment, AddressM return m.nodes_; } - boost::iterator_range + dyncompat::iterator_range nodes(const AddressMapConstraints &c, MatchFlags flags=0) { using namespace AddressMapImpl; if (0==(flags & (MATCH_CONTIGUOUS|MATCH_NONCONTIGUOUS))) @@ -1400,7 +1406,7 @@ class AddressMap: public IntervalMap, AddressSegment, AddressM * but a slightly faster test (that is also more self-documenting) is: * * @code - * if (a == boost::integer_traits
::const_max) + * if (a == dyncompat::integer_traits
::const_max) * break; * @endcode * @@ -1567,7 +1573,7 @@ class AddressMap: public IntervalMap, AddressSegment, AddressM void traverse(Functor &functor, const AddressMapConstraints &c, MatchFlags flags=0) const { using namespace AddressMapImpl; MatchedConstraints m = matchConstraints(*this, c, flags); - BOOST_FOREACH (const Node &node, m.nodes_) { + DYN_FOREACH (const Node &node, m.nodes_) { Sawyer::Container::Interval
part = m.interval_ & node.key(); if (!functor(*this, part)) return; @@ -1578,7 +1584,7 @@ class AddressMap: public IntervalMap, AddressSegment, AddressM void traverse(Functor &functor, const AddressMapConstraints &c, MatchFlags flags=0) { using namespace AddressMapImpl; MatchedConstraints m = matchConstraints(*this, c, flags); - BOOST_FOREACH (const Node &node, m.nodes_) { + DYN_FOREACH (const Node &node, m.nodes_) { Sawyer::Container::Interval
part = m.interval_ & node.key(); if (!functor(*this, part)) return; @@ -1614,7 +1620,7 @@ class AddressMap: public IntervalMap, AddressSegment, AddressM * std::vector buf(1024); * while (Interval
accessed = map.atOrAfter(a).read(buf)) { * a = accessed.least(); - * BOOST_FOREACH (const Value &v, buf) + * DYN_FOREACH (const Value &v, buf) * std::cout <, AddressSegment, AddressM flags |= MATCH_CONTIGUOUS; MatchedConstraints m = matchConstraints(*this, c, flags); if (buf) { - BOOST_FOREACH (const Node &node, m.nodes_) { + DYN_FOREACH (const Node &node, m.nodes_) { Sawyer::Container::Interval
part = m.interval_ & node.key(); // part of segment to read ASSERT_forbid(part.isEmpty()); Address bufferOffset = part.least() - node.key().least() + node.value().offset(); @@ -1700,7 +1706,7 @@ class AddressMap: public IntervalMap, AddressSegment, AddressM flags |= MATCH_CONTIGUOUS; MatchedConstraints m = matchConstraints(*this, c.prohibit(Access::IMMUTABLE), flags); if (buf) { - BOOST_FOREACH (Node &node, m.nodes_) { + DYN_FOREACH (Node &node, m.nodes_) { Segment &segment = node.value(); Sawyer::Container::Interval
part = m.interval_ & node.key(); // part of segment to write ASSERT_forbid(part.isEmpty()); @@ -1753,11 +1759,11 @@ class AddressMap: public IntervalMap, AddressSegment, AddressM if (0==(flags & (MATCH_CONTIGUOUS|MATCH_NONCONTIGUOUS))) flags |= MATCH_NONCONTIGUOUS; MatchedConstraints m = matchConstraints(*this, c.addressConstraints(), flags); - BOOST_FOREACH (const Node &node, m.nodes_) { + DYN_FOREACH (const Node &node, m.nodes_) { if (isSatisfied(node, c)) toErase.insert(node.key() & m.interval_); } - BOOST_FOREACH (const Sawyer::Container::Interval
&interval, toErase.intervals()) + DYN_FOREACH (const Sawyer::Container::Interval
&interval, toErase.intervals()) this->erase(interval); } @@ -1780,12 +1786,12 @@ class AddressMap: public IntervalMap, AddressSegment, AddressM flags |= MATCH_NONCONTIGUOUS; IntervalSet > toKeep; MatchedConstraints m = matchConstraints(*this, c.addressConstraints(), flags); - BOOST_FOREACH (const Node &node, m.nodes_) { + DYN_FOREACH (const Node &node, m.nodes_) { if (isSatisfied(node, c)) toKeep.insert(node.key() & m.interval_); } toKeep.invert(); - BOOST_FOREACH (const Sawyer::Container::Interval
&interval, toKeep.intervals()) + DYN_FOREACH (const Sawyer::Container::Interval
&interval, toKeep.intervals()) this->erase(interval); } @@ -1816,7 +1822,7 @@ class AddressMap: public IntervalMap, AddressSegment, AddressM typedef std::pair, Segment> ISPair; std::vector newSegments; MatchedConstraints m = matchConstraints(*this, c.addressConstraints(), flags); - BOOST_FOREACH (Node &node, m.nodes_) { + DYN_FOREACH (Node &node, m.nodes_) { Segment &segment = node.value(); if (isSatisfied(node, c)) { unsigned newAccess = (segment.accessibility() | requiredAccess) & ~prohibitedAccess; @@ -1831,7 +1837,7 @@ class AddressMap: public IntervalMap, AddressSegment, AddressM } } } - BOOST_FOREACH (const ISPair &pair, newSegments) + DYN_FOREACH (const ISPair &pair, newSegments) this->insert(pair.first, pair.second); } diff --git a/dataflowAPI/rose/util/AddressSegment.h b/dataflowAPI/rose/util/AddressSegment.h index bd0f3f10f7..6456cb0c3d 100644 --- a/dataflowAPI/rose/util/AddressSegment.h +++ b/dataflowAPI/rose/util/AddressSegment.h @@ -8,7 +8,10 @@ #ifndef Sawyer_AddressSegment_H #define Sawyer_AddressSegment_H -#include +#include +#include +#include +#include #include "Access.h" #include "AllocatingBuffer.h" #include "MappedBuffer.h" @@ -29,7 +32,7 @@ namespace Container { * containing the segment. A segment points to a buffer which might not be the same size as what is entered in the map; * buffers that are longer than the mapped interval of address space have data which is not accessible (at least not through * that segment), and buffers that are shorter may return short data from read and write operations. */ -template +template class AddressSegment { typename Buffer::Ptr buffer_; // reference counted buffer A offset_; // initial offset into buffer @@ -103,9 +106,9 @@ class AddressSegment { /** Map a file into an address space. */ static AddressSegment fileInstance(const std::string &fileName, unsigned accessBits=Access::READABLE, const std::string &name="") { - boost::iostreams::mapped_file::mapmode mode = (accessBits & Access::WRITABLE)!=0 ? - boost::iostreams::mapped_file::readwrite : - boost::iostreams::mapped_file::readonly; + int mode = (accessBits & Access::WRITABLE)!=0 ? + 1 : + 0; return AddressSegment(MappedBuffer::instance(fileName, mode), 0, accessBits, name); } diff --git a/dataflowAPI/rose/util/AllocatingBuffer.h b/dataflowAPI/rose/util/AllocatingBuffer.h index 0a346118ac..f1d087207e 100644 --- a/dataflowAPI/rose/util/AllocatingBuffer.h +++ b/dataflowAPI/rose/util/AllocatingBuffer.h @@ -11,7 +11,7 @@ #include "Buffer.h" #include "Sawyer.h" -#include +#include #include // memcpy #include #include @@ -50,8 +50,8 @@ class AllocatingBuffer: public Buffer { Address nWritten = newBuffer->write(&values_[0], 0, this->size()); if (nWritten != this->size()) { throw std::runtime_error("AllocatingBuffer::copy() failed after copying " + - boost::lexical_cast(nWritten) + " of " + - boost::lexical_cast(this->size()) + + dyncompat::lexical_cast(nWritten) + " of " + + dyncompat::lexical_cast(this->size()) + (1==this->size()?" value":" values")); } return newBuffer; diff --git a/dataflowAPI/rose/util/Attribute.C b/dataflowAPI/rose/util/Attribute.C index 0cdf7b5959..0fc7c7c076 100644 --- a/dataflowAPI/rose/util/Attribute.C +++ b/dataflowAPI/rose/util/Attribute.C @@ -7,8 +7,8 @@ #include "Attribute.h" #include "BiMap.h" -#include -#include +#include +#include namespace Sawyer { namespace Attribute { @@ -43,17 +43,16 @@ void Storage::checkBoost() const { // We do not support boost 1.54 with C++11 because of boost ticket #9215 [https://svn.boost.org/trac/boost/ticket/9215]. It // is better if we check for this at runtime rather than compile time because many other features of boost 1.54 work - // fine. If we allow the user to continue, then boost::any's move constructor will enter infinite recursion eventually + // fine. If we allow the user to continue, then dyncompat::any's move constructor will enter infinite recursion eventually // ending with a segmentation fault (although probably not occuring as a result of calling just Storage's c'tor). - ASSERT_always_forbid2(BOOST_VERSION == 105400 && __cplusplus >= 201103L, - "boost::any move constructor has infinite recursion in boost-1.54"); + // boost version check removed — no longer using boost::any } SAWYER_EXPORT std::vector Storage::attributeIds() const { std::vector retval; retval.reserve(values_.size()); - BOOST_FOREACH (Id id, values_.keys()) + DYN_FOREACH (Id id, values_.keys()) retval.push_back(id); return retval; } diff --git a/dataflowAPI/rose/util/Attribute.h b/dataflowAPI/rose/util/Attribute.h index 36a6d5a9d8..337e390638 100644 --- a/dataflowAPI/rose/util/Attribute.h +++ b/dataflowAPI/rose/util/Attribute.h @@ -48,8 +48,9 @@ #ifndef Sawyer_Attribute_H #define Sawyer_Attribute_H -#include -#include +#include +#include +#include #include "Exception.h" #include "Map.h" #include "Optional.h" @@ -181,18 +182,18 @@ class SAWYER_EXPORT AlreadyExists: public Exception::AlreadyExists { /** Constructor taking an attribute name or description. */ AlreadyExists(const std::string &attrName, Id id) : Exception::AlreadyExists(attrName + " is already a declared attribute (id=" + - boost::lexical_cast(id) + ")") {} + dyncompat::lexical_cast(id) + ")") {} }; /** Exception thrown when wrong data type is queried. */ -typedef boost::bad_any_cast WrongQueryType; +typedef std::bad_any_cast WrongQueryType; /** API and storage for attributes. * * This is the interface inherited by objects that can store attributes. See the @ref Attribute "namespace" for usage and * examples. */ class SAWYER_EXPORT Storage { - typedef Sawyer::Container::Map AttrMap; + typedef Sawyer::Container::Map AttrMap; AttrMap values_; public: /** Check attribute existence. @@ -222,7 +223,7 @@ class SAWYER_EXPORT Storage { * retrieving the attribute. */ template void setAttribute(Id id, const T &value) { - values_.insert(id, boost::any(value)); + values_.insert(id, dyncompat::any(value)); } /** Get an attribute that is known to exist. @@ -236,13 +237,13 @@ class SAWYER_EXPORT Storage { if (found == values_.nodes().end()) { std::string name = Attribute::name(id); if (name.empty()) { - throw DoesNotExist("attribute id " + boost::lexical_cast(id) + " [not declared]"); + throw DoesNotExist("attribute id " + dyncompat::lexical_cast(id) + " [not declared]"); } else { throw DoesNotExist(name); } } checkBoost(); - return boost::any_cast(values_.getOptional(id).orDefault()); + return dyncompat::any_cast(values_.getOptional(id).orDefault()); } /** Return an attribute or a specified value. @@ -253,7 +254,7 @@ class SAWYER_EXPORT Storage { template T attributeOrElse(Id id, const T &dflt) const { checkBoost(); - return boost::any_cast(values_.getOptional(id).orElse(dflt)); + return dyncompat::any_cast(values_.getOptional(id).orElse(dflt)); } /** Return an attribute or a default-constructed value. @@ -266,7 +267,7 @@ class SAWYER_EXPORT Storage { AttrMap::ConstNodeIterator found = values_.find(id); if (found == values_.nodes().end()) return T(); - return boost::any_cast(found->value()); + return dyncompat::any_cast(found->value()); } /** Return the attribute as an optional value. @@ -277,7 +278,7 @@ class SAWYER_EXPORT Storage { AttrMap::ConstNodeIterator found = values_.find(id); if (found == values_.nodes().end()) return Sawyer::Nothing(); - return boost::any_cast(found->value()); + return dyncompat::any_cast(found->value()); } /** Number of attributes stored. */ diff --git a/dataflowAPI/rose/util/BiMap.h b/dataflowAPI/rose/util/BiMap.h index 361d22c155..72263c2367 100644 --- a/dataflowAPI/rose/util/BiMap.h +++ b/dataflowAPI/rose/util/BiMap.h @@ -10,7 +10,7 @@ #include "Map.h" #include "Sawyer.h" -#include +#include namespace Sawyer { namespace Container { @@ -48,7 +48,7 @@ class BiMap { * map across both input maps. */ template BiMap(const BiMap &a, const BiMap &b) { - BOOST_FOREACH (const typename Forward::Node &anode, a.forward_.nodes()) { + DYN_FOREACH (const typename Forward::Node &anode, a.forward_.nodes()) { if (b.forward_.exists(anode.value())) { const Target &target = b.forward_[anode.value()]; forward_.insert(anode.key(), target); diff --git a/dataflowAPI/rose/util/BitVector.h b/dataflowAPI/rose/util/BitVector.h index 9abf3630a2..68c6d4e351 100644 --- a/dataflowAPI/rose/util/BitVector.h +++ b/dataflowAPI/rose/util/BitVector.h @@ -8,8 +8,14 @@ #ifndef Sawyer_BitVector_H #define Sawyer_BitVector_H -#include -#include +#include +#include +#include +#include +#include +#include +#include +#include #include "Assert.h" #include "BitVectorSupport.h" #include "Optional.h" @@ -19,7 +25,7 @@ namespace Sawyer { namespace Container { -#ifdef BOOST_WINDOWS +#ifdef _WIN32 /** Log base 2. * * Returns the logorithm base 2 of n by the change-of-base formula. */ @@ -96,19 +102,19 @@ class BitVector { // Radix information size_t bitsPerDigit = 0; const char *digits = NULL; - if (boost::starts_with(str, "0x")) { + if (dyncompat::starts_with(str, "0x")) { bitsPerDigit = 4; digits = "0123456789abcdefABCDEF"; str = str.substr(2); - } else if (boost::starts_with(str, "0b")) { + } else if (dyncompat::starts_with(str, "0b")) { bitsPerDigit = 1; digits = "01"; str = str.substr(2); - } else if (boost::ends_with(str, "h")) { + } else if (dyncompat::ends_with(str, "h")) { bitsPerDigit = 4; digits = "0123456789abcdefABCDEF"; str = str.substr(0, str.size()-1); - } else if (boost::starts_with(str, "0")) { + } else if (dyncompat::starts_with(str, "0")) { bitsPerDigit = 2; digits = "01234567"; str = str.substr(1); @@ -1088,7 +1094,7 @@ class BitVector { * * Returns the bits of the specified range by interpreting them as an unsigned integer. The range must be valid for this * vector. If the range contains more than 64 bits then only the low-order 64 bits are considered. */ - boost::uint64_t toInteger(const BitRange &range) const { + uint64_t toInteger(const BitRange &range) const { checkRange(range); return BitVectorSupport::toInteger(data(), range); } @@ -1097,7 +1103,7 @@ class BitVector { * * Returns the bits of this vector by interpreting them as an unsigned integer. If this vector contains more than 64 bits * then only the low-order 64 bits are considered. */ - boost::uint64_t toInteger() const { + uint64_t toInteger() const { if (size() <= 64) return BitVectorSupport::toInteger(data(), size()); return BitVectorSupport::toInteger(data(), hull()); @@ -1166,7 +1172,7 @@ class BitVector { * Assigns the specified value to the bits indicated by @p range of this vector. If the range contains fewer than 64 bits * then only the low order bits of @p value are used; if the range contains more than 64 bits then the high-order bits are * cleared. The range must be a valid range for this vector. */ - BitVector& fromInteger(const BitRange &range, boost::uint64_t value) { + BitVector& fromInteger(const BitRange &range, uint64_t value) { checkRange(range); BitVectorSupport::fromInteger(data(), range, value); return *this; @@ -1179,7 +1185,7 @@ class BitVector { * vector is not changed by this operation. * * @sa The assignment operator. */ - BitVector& fromInteger(boost::uint64_t value) { + BitVector& fromInteger(uint64_t value) { BitVectorSupport::fromInteger(data(), hull(), value); return *this; } diff --git a/dataflowAPI/rose/util/BitVectorSupport.h b/dataflowAPI/rose/util/BitVectorSupport.h index 459feb0a12..b3f82518db 100644 --- a/dataflowAPI/rose/util/BitVectorSupport.h +++ b/dataflowAPI/rose/util/BitVectorSupport.h @@ -8,10 +8,11 @@ #ifndef Sawyer_BitVectorSupport_H #define Sawyer_BitVectorSupport_H -#include +#include +#include #include -#include -#include +#include +#include #include #include "Assert.h" #include "Interval.h" @@ -20,6 +21,8 @@ #include #include +DYNINST_DIAGNOSTIC_BEGIN_SUPPRESS_VLA_GCC_PRAGMA_BUG + namespace Sawyer { namespace Container { @@ -927,7 +930,7 @@ void bitwiseXor(const Word *vec1, const BitRange &range1, Word *vec2, const BitR * * Zero extends or truncates @p value to the same width as @p range and copies it into the bit vector. */ template -void fromInteger(Word *words, const BitRange &range, boost::uint64_t value) { +void fromInteger(Word *words, const BitRange &range, uint64_t value) { ASSERT_require(8==sizeof value); if (range.isEmpty()) return; @@ -953,8 +956,8 @@ void fromInteger(Word *words, const BitRange &range, boost::uint64_t value) { * Converts the specified range to an unsigned 64-bit value and returns that value. Returns zero if the range is empty. If * the range is wider than 64 bits then all of its high-order bits are ignored and only the lowest 64 bits are used. */ template -boost::uint64_t toInteger(const Word *words, const BitRange &range) { - boost::uint64_t result = 0; +uint64_t toInteger(const Word *words, const BitRange &range) { + uint64_t result = 0; ASSERT_require(8==sizeof result); // Copy the bits into the low bits of a temporary bit vector @@ -967,7 +970,7 @@ boost::uint64_t toInteger(const Word *words, const BitRange &range) { // Convert the temporary bit vector to an integer for (size_t i=0; i::value); + result |= (uint64_t)tmp[i] << (i * bitsPerWord::value); return result; } @@ -975,12 +978,12 @@ boost::uint64_t toInteger(const Word *words, const BitRange &range) { * * Faster version of @ref toInteger for instances where the range offset is zero, and the size is not greater than 64 bits. */ template -boost::uint64_t toInteger(const Word *words, size_t nbits) { - boost::uint64_t result = 0; +uint64_t toInteger(const Word *words, size_t nbits) { + uint64_t result = 0; ASSERT_require(nbits <= 64); size_t nTmpWords = numberOfWords(nbits); for (size_t i=0; i::value); + result |= (uint64_t)words[i] << (i * bitsPerWord::value); if (nbits < 64) result &= ~((~/*UINT64_C(0)*/0ULL) << nbits); return result; @@ -1051,7 +1054,7 @@ void negate(Word *vec1, const BitRange &range) { template struct AddBits { bool carry; - AddBits(bool carry): carry(carry) {} + AddBits(bool carry_): carry(carry_) {} bool operator()(const Word &w1, Word &w2, size_t nbits) { Word mask = bitMask(0, nbits); Word addend1(carry ? 1 : 0); @@ -1363,8 +1366,8 @@ void fromString(Word *vec, const BitRange &range, const std::string &input) { for (size_t idx=0; idx(input[idx]) >= Word(1) << bitsPerDigit) { throw std::runtime_error(std::string("invalid character '") + input[idx] + "' at index " + - boost::lexical_cast(idx) + " in base-" + - boost::lexical_cast(1 << bitsPerDigit) + " input string"); + dyncompat::lexical_cast(idx) + " in base-" + + dyncompat::lexical_cast(1 << bitsPerDigit) + " input string"); } } @@ -1397,10 +1400,10 @@ void fromString(Word *vec, const BitRange &range, const std::string &input) { * parse to more than 64 bits. */ template void fromDecimal(Word *vec, const BitRange &range, const std::string &input) { - boost::uint64_t v = 0; - BOOST_FOREACH (char ch, input) { + uint64_t v = 0; + DYN_FOREACH (char ch, input) { if (isdigit(ch)) { - boost::uint64_t tmp = v * 10 + (ch - '0'); + uint64_t tmp = v * 10 + (ch - '0'); if (tmp < v) throw std::runtime_error("overflow parsing decimal string"); v = tmp; @@ -1449,4 +1452,7 @@ void fromBinary(Word *vec, const BitRange &range, const std::string &input) { } // namespace } // namespace } // namespace + +DYNINST_DIAGNOSTIC_END_SUPPRESS_VLA_GCC_PRAGMA_BUG + #endif diff --git a/dataflowAPI/rose/util/Combinatorics.h b/dataflowAPI/rose/util/Combinatorics.h index 42b868106e..1db8f82572 100644 --- a/dataflowAPI/rose/util/Combinatorics.h +++ b/dataflowAPI/rose/util/Combinatorics.h @@ -3,6 +3,7 @@ #include "LinearCongruentialGenerator.h" +#include #include #include #include diff --git a/dataflowAPI/rose/util/Exception.h b/dataflowAPI/rose/util/Exception.h index 3c795fca39..d444907e6b 100644 --- a/dataflowAPI/rose/util/Exception.h +++ b/dataflowAPI/rose/util/Exception.h @@ -8,6 +8,7 @@ #ifndef Sawyer_Exception_H #define Sawyer_Exception_H +#include #include "Sawyer.h" namespace Sawyer { diff --git a/dataflowAPI/rose/util/FileSystem.C b/dataflowAPI/rose/util/FileSystem.C index 4582d52a6f..e69de29bb2 100644 --- a/dataflowAPI/rose/util/FileSystem.C +++ b/dataflowAPI/rose/util/FileSystem.C @@ -1,229 +0,0 @@ -#include "FileSystem.h" -#include -#include -#include - -#if BOOST_FILESYSTEM_VERSION == 2 // FIXME[Robb P. Matzke 2014-11-18]: Remove version 2 support -#include -#endif - -namespace rose { -namespace FileSystem { - -const char *tempNamePattern = "rose-%%%%%%%-%%%%%%%"; - -bool -baseNameMatches::operator()(const Path &path) { -#if BOOST_FILESYSTEM_VERSION == 2 - return boost::regex_match(path.filename(), re_); -#else - return boost::regex_match(path.filename().string(), re_); -#endif -} - -bool -isExisting(const Path &path) { - return boost::filesystem::exists(path); -} - -bool -isFile(const Path &path) { - return boost::filesystem::is_regular_file(path); -} - -bool -isDirectory(const Path &path) { - return boost::filesystem::is_directory(path); -} - -bool -isSymbolicLink(const Path &path) { - return boost::filesystem::is_symlink(path); -} - -bool -isNotSymbolicLink(const Path &path) { - return !boost::filesystem::is_symlink(path); -} - -Path -createTemporaryDirectory() { -#if BOOST_FILESYSTEM_VERSION == 2 // FIXME[Robb P. Matzke 2014-11-18]: Remove version 2 support -#ifdef _MSC_VER - Path dirName = "/tmp"; // FIXME[Robb P. Matzke 2014-11-18]: is this right for Windows? -#else - Path dirName = "/tmp"; - if (0 != geteuid() && NULL != getenv("TMPDIR")) { - dirName = getenv("TMPDIR"); - } else { -#ifdef P_tmpdir - dirName = P_tmpdir; -#endif - } -#endif - std::string base = tempNamePattern; - LinearCongruentialGenerator lcg; - for (size_t i=0; i components; - for (boost::filesystem::path::const_iterator i=path.begin(); i!=path.end(); ++i) { -#if BOOST_FILESYSTEM_VERSION == 2 // FIXME[Robb P. Matzke 2014-11-18]: Remove version 2 support - if (0 == i->compare("..") && !components.empty()) { - components.pop_back(); - } else if (0 != i->compare(".")) { - components.push_back(*i); - } -#else - if (0 == i->string().compare("..") && !components.empty()) { - components.pop_back(); - } else if (0 != i->string().compare(".")) { - components.push_back(*i); - } -#endif - } - Path result; - BOOST_FOREACH (const Path &component, components) - result /= component; - return result; -} - -Path -makeAbsolute(const Path &path, const Path &root) { -#if BOOST_FILESYSTEM_VERSION == 2 // FIXME[Robb P. Matzke 2014-11-18]: Remove version 2 support - Path retval; - if (path.has_root_name()) { - if (path.has_root_directory()) { - retval = path; - } else { - retval = Path(path.root_name()) / makeAbsolute(root).root_directory() / - makeAbsolute(root).relative_path() / path.relative_path(); - } - } else { - Path absoluteRoot; - if (root.has_root_directory()) { - absoluteRoot = root; - } else { - absoluteRoot = makeAbsolute(root); - } - - if (path.has_root_directory()) { - retval = absoluteRoot.root_name() / path; - } else { - retval = absoluteRoot / path; - } - } - return makeNormal(retval); -#else - return makeNormal(path.is_absolute() ? path : absolute(root / path)); -#endif -} - -Path -makeRelative(const Path &path_, const Path &root_) { - Path path = makeAbsolute(path_); - Path root = makeAbsolute(root_); - - boost::filesystem::path::const_iterator rootIter = root.begin(); - boost::filesystem::path::const_iterator pathIter = path.begin(); - - // Skip past common prefix - while (rootIter!=root.end() && pathIter!=path.end() && *rootIter==*pathIter) { - ++rootIter; - ++pathIter; - } - - // Return value must back out of remaining A components - Path retval; - while (rootIter!=root.end()) { - if (*rootIter++ != ".") - retval /= ".."; - } - - // Append path components - while (pathIter!=path.end()) - retval /= *pathIter++; - return retval; -} - -std::vector -findNames(const Path &root) { - return findNames(root, isExisting); -} - -std::vector -findNamesRecursively(const Path &root) { - return findNamesRecursively(root, isExisting, isDirectory); -} - -// This doesn't make any sense! First, BOOST_COMPILED_WITH_CXX11 is never defined in any version of boost. Second, even if it -// were defined, it would come from boost header files which are always compiled with the same compile as that which is -// compiling this source file. [Robb Matzke 2016-02-17] -//#if (__cplusplus >= 201103L) -//#if !defined(BOOST_COMPILED_WITH_CXX11) -// #warning "Compiling ROSE with C++11 mode: BOOST NOT compiled with C++11 support." -//#else -// #warning "Compiling ROSE with C++11 mode: BOOST WAS compiled with C++11 support." -//#endif -//#endif - -void -copyFile(const Path &src, const Path &dst) { - // Do not use boost::filesystem::copy_file in boost 1.56 and earlier because it is not possible to cross link c++11 rose - // with c++89 boost when using this symbol. Boost issue #6124 fixed in boost 1.57 and later. Our solution is to use C++ - // stream I/O instead, which should still work on non-POSIX systems (Microsoft) although the exception situations might not - // be exactly precise as POSIX. Use path::string rather than path::native in order to support Filesystem version 2. - std::ifstream in(src.string().c_str(), std::ios::binary); - std::ofstream out(dst.string().c_str(), std::ios::binary); - out < &fileNames, const Path &root, const Path &dstDir) { - std::set dirs; - BOOST_FOREACH (const Path &fileName, fileNames) { - Path dirName = dstDir / makeRelative(fileName.parent_path(), root); - if (dirs.insert(dirName).second) - boost::filesystem::create_directories(dirName); - Path outputName = dirName / fileName.filename(); - copyFile(fileName, outputName); - } -} - -std::vector -findRoseFilesRecursively(const Path &root) { - return findNamesRecursively(root, baseNameMatches(boost::regex("rose_.*")), isDirectory); -} - -// Don't use this if you can help it! -std::string -toString(const Path &path) { -#if BOOST_FILESYSTEM_VERSION == 2 // FIXME[Robb P. Matzke 2014-11-18]: Remove version 2 support - return path.string(); -#else - return path.generic_string(); -#endif -} - -} // namespace -} // namespace diff --git a/dataflowAPI/rose/util/FileSystem.h b/dataflowAPI/rose/util/FileSystem.h index 4034b9ac97..e69de29bb2 100644 --- a/dataflowAPI/rose/util/FileSystem.h +++ b/dataflowAPI/rose/util/FileSystem.h @@ -1,191 +0,0 @@ -#ifndef ROSE_FileSystem_H -#define ROSE_FileSystem_H - -#include -#include -#include - -namespace rose { - -/** Functions for operating on files in a filesystem. */ - namespace FileSystem { - -/** Pattern to use when creating temporary files. */ - extern const char *tempNamePattern; - -/** Name of entities in a filesystem. */ - typedef boost::filesystem::path Path; - -/** Iterate over directory contents non-recursively. */ - typedef boost::filesystem::directory_iterator DirectoryIterator; - -/** Iterate recursively into subdirectories. */ - typedef boost::filesystem::recursive_directory_iterator RecursiveDirectoryIterator; - -/** Predicate returning true if path exists. */ - bool isExisting(const Path &path); - -/** Predicate returning true for existing regular files. */ - bool isFile(const Path &path); - -/** Predicate returning true for existing directories. */ - bool isDirectory(const Path &path); - -/** Predicate returning true for existing symbolic links. */ - bool isSymbolicLink(const Path &path); - -/** Predicate returning inverse of @ref isSymbolicLink. */ - bool isNotSymbolicLink(const Path &path); - -/** Predicate returning true for matching names. - * - * Returns true if and only if the final component of the path matches the specified regular expression. - * - * For example, to find all files whose base name matches the glob "rose_*" use this (note that the corresponding regular - * expression is "rose_.*", with a dot): - * - * @code - * using namespace rose::FileSystem; - * Path top = "/foo/bar"; // where the search starts - * std::vector roseFiles = findAllNames(top, baseNameMatches(boost::regex("rose_.*"))); - * @endcode */ - class baseNameMatches { - const boost::regex &re_; - public: - baseNameMatches(const boost::regex &re) : re_(re) { } - - bool operator()(const Path &path); - }; - -/** Create a temporary directory. - * - * The temporary directory is created as a subdirectory of the directory which is suitable for temporary files under the - * conventions of the operating system. The specifics of how this path is determined are implementation defined (see - * boost::filesystem::temp_directory_path). The created subdirectory has a name of the form - * "rose-%%%%%%%%-%%%%%%%%" where each "%" is a random hexadecimal digit. Returns the path to this directory. */ - Path createTemporaryDirectory(); - -/** Normalize a path name. - * - * Normalizes a path by removing "." and ".." components to the extent which is possible. - * - * For instance, a name like "/foo/bar/../baz" will become "/foo/baz" and the name "/foo/./baz" will become - * "/foo/baz". However, the names "/../foo" and "./foo" cannot be changed because removing the ".." in the first case would - * place it in a different directory if the name were appended to another name, and in the second case it would convert a - * relative name to an absolute name. */ - Path makeNormal(const Path &); - -/** Make path relative. - * - * Makes the specified path relative to another path or the current working directory. */ - Path makeRelative(const Path &path, const Path &root = boost::filesystem::current_path()); - -/** Make path absolute. - * - * Makes the specified path an absolute path if it is a relative path. If relative, then assume @p root is what the path is - * relative to. */ - Path makeAbsolute(const Path &path, const Path &root = boost::filesystem::current_path()); - -/** Entries within a directory. - * - * Returns a list of entries in a directory--the contents of a directory--without recursing into subdirectories. The return - * value is a sorted list of paths, each of which contains @p root as a prefix. If a @p select predicate is supplied then - * only paths for which the predicate returns true become part of the return value. The predicate is called with the path that - * would become part of the return value. The @p root itself is never returned and never tested by the predicate. - * - * If @p select is not specified then all entries are returned. - * - * @{ */ - template - std::vector findNames(const Path &root, Select select) { - std::vector matching; - if (isDirectory(root)) { - for (DirectoryIterator iter(root); iter != DirectoryIterator(); ++iter) { - if (select(iter->path())) - matching.push_back(iter->path()); - } - } - std::sort(matching.begin(), matching.end()); - return matching; - } - - std::vector findNames(const Path &root); -/** @} */ - -/** Recursive list of names satisfying predicate. - * - * Returns a list of entries in a directory and all subdirectories recursively. The return value is a sorted list of - * paths, each of which contains @p root as a prefix. If a @p select predicate is supplied then only paths for which the - * predicate returns true become part of the return value. If a @p descend predicate is supplied then this algorithm only - * recurses into subdirectories for which @p descend returns true. The predicates are called with the path that would become - * part of the return value. The @p root itself is never returned and never tested by the @p select or @p descend predicates. - * - * If @p select is not specified then all entries are returned. If @p descend is not specified then the algorithm traverses - * into all subdirectories. Symbolic links to directories are never followed, but are returned if the @p select predicate - * allows them. - * - * @{ */ - template - std::vector findNamesRecursively(const Path &root, Select select, Descend descend) { - std::vector matching; - RecursiveDirectoryIterator end; - for (RecursiveDirectoryIterator dentry(root); dentry != end; ++dentry) { - if (select(dentry->path())) - matching.push_back(dentry->path()); - if (!descend(dentry->path())) - dentry.no_push(); - } - std::sort(matching.begin(), matching.end()); - return matching; - } - - template - std::vector findNamesRecursively(const Path &root, Select select) { - return findNamesRecursively(root, select, isDirectory); - } - - std::vector findNamesRecursively(const Path &root); -/** @} */ - -/** Copy a file. - * - * Copies the contents of the source file to the destination file, overwriting the destination file if it existed. */ - void copyFile(const Path &sourceFileName, const Path &destinationFileName); - -/** Copy files from one directory to another. - * - * Each of the specified files are copied from their location under @p root to a similar location under @p - * destinationDirectory. Subdirectories of the destination directory are created as necessary. - * - * Any file whose name is outside the @p root directory will similarly be created outside the @p destinationDirectory. - * For instance, copyFiles(["bar/baz"], "foo", "frob") will copy "bar/baz" to "frob/../bar/baz" since "bar" is apparently - * a sibling of "foo", and therefore must be a sibling of "frob". - * - * Throws a boost::filesystem::filesystem_error on failure. */ - void copyFiles(const std::vector &files, const Path &root, const Path &destinationDirectory); - -/** Recursively copy files. - * - * Get a list of files by recursively matching files under @p root and then copy them to similar locations relative to @p - * destination. The @p root and @p destination must not overlap. The @p select and @p descend arguments are the same as - * for the @ref findAllNames method. */ - template - void copyFilesRecursively(const Path &root, const Path &destination, Select select, Descend descend) { - std::vector files = findNamesRecursively(root, select, descend); - files.erase(files.begin(), std::remove_if(files.begin(), files.end(), isFile)); // keep only isFile names - copyFiles(files, root, destination); - } - -/** Return a list of all rose_* files */ - std::vector findRoseFilesRecursively(const Path &root); - -/** Convert a path to a string. - * - * Try not to use this. Paths contain more information than std::string and the conversion may loose that info. */ - std::string toString(const Path &); - - - } // namespace -} // namespace - -#endif diff --git a/dataflowAPI/rose/util/Interval.h b/dataflowAPI/rose/util/Interval.h index 14e18d2e28..2464a2a0d0 100644 --- a/dataflowAPI/rose/util/Interval.h +++ b/dataflowAPI/rose/util/Interval.h @@ -10,7 +10,8 @@ #include "Assert.h" #include "Sawyer.h" -#include +#include +#include namespace Sawyer { namespace Container { @@ -72,7 +73,7 @@ class Interval { /** Construct an interval that covers the entire domain. */ static Interval whole() { - return hull(boost::integer_traits::const_min, boost::integer_traits::const_max); + return hull(dyncompat::integer_traits::const_min, dyncompat::integer_traits::const_max); } /** Assignment from an interval. */ @@ -107,7 +108,7 @@ class Interval { bool isSingleton() const { return lo_ == hi_; } /** True if interval covers entire space. */ - bool isWhole() const { return lo_==boost::integer_traits::const_min && hi_==boost::integer_traits::const_max; } + bool isWhole() const { return lo_==dyncompat::integer_traits::const_min && hi_==dyncompat::integer_traits::const_max; } /** True if two intervals overlap. * diff --git a/dataflowAPI/rose/util/IntervalMap.h b/dataflowAPI/rose/util/IntervalMap.h index 5413bca07b..2f3e8d5a0b 100644 --- a/dataflowAPI/rose/util/IntervalMap.h +++ b/dataflowAPI/rose/util/IntervalMap.h @@ -8,7 +8,8 @@ #ifndef Sawyer_IntervalMap_H #define Sawyer_IntervalMap_H -#include +#include +#include #include "Assert.h" #include "Map.h" #include "Optional.h" @@ -46,7 +47,7 @@ class MergePolicy { * * The @p rightValue is merged into the @p leftValue if possible, or this method returns false without changing either * value. After a successful merge, the @p rightValue will be removed from the IntervalMap and its destructor called. */ - bool merge(const Interval &leftInterval, Value &leftValue, const Interval &rightInterval, Value &rightValue) { + bool merge(const Interval &/*leftInterval*/, Value &leftValue, const Interval &/*rightInterval*/, Value &rightValue) { return leftValue == rightValue; } @@ -56,13 +57,13 @@ class MergePolicy { * splitPoint argument is the split point and becomes the least value of the right interval. The @p value argument is * modified in place to become the left value, and the right value is returned. This method is only invoked when the * result would be two non-empty intervals. */ - Value split(const Interval &interval, Value &value, const typename Interval::Value &splitPoint) { return value; } + Value split(const Interval &/*interval*/, Value &value, const typename Interval::Value &/*splitPoint*/) { return value; } /** Discard the right part of a value. * * This method is the same as @ref split except the right part of the resulting value is discarded. This is sometimes * more efficient than calling @ref split and then destroying the return value. */ - void truncate(const Interval &interval, Value &value, const typename Interval::Value &splitPoint) {} + void truncate(const Interval &/*interval*/, Value &/*value*/, const typename Interval::Value &/*splitPoint*/) {} }; /** An associative container whose keys are non-overlapping intervals. @@ -129,7 +130,7 @@ class MergePolicy { * Here's another way: * * @code - * BOOST_FOREACH (const Map::Node &node, map.nodes()) { + * DYN_FOREACH (const Map::Node &node, map.nodes()) { * const Interval &interval = node.key(); * const Stats &stats = node.value(); * ... @@ -248,15 +249,15 @@ class IntervalMap { * are traversed in key order. * * @{ */ - boost::iterator_range nodes() { return map_.nodes(); } - boost::iterator_range nodes() const { return map_.nodes(); } + dyncompat::iterator_range nodes() { return map_.nodes(); } + dyncompat::iterator_range nodes() const { return map_.nodes(); } /** @} */ /** Iterators for traversing keys. * * Returns a range of iteratores that traverse all keys (non-overlapping intervals) of this container according to the * order of the intervals. */ - boost::iterator_range intervals() const { return map_.keys(); } + dyncompat::iterator_range intervals() const { return map_.keys(); } /** Iterators for traversing values. * @@ -264,8 +265,8 @@ class IntervalMap { * in the order of their associated keys. * * @{ */ - boost::iterator_range values() { return map_.values(); } - boost::iterator_range values() const { return map_.values(); } + dyncompat::iterator_range values() { return map_.values(); } + dyncompat::iterator_range values() const { return map_.values(); } /** @} */ /** Find the first node whose interval ends at or above the specified scalar key. @@ -355,23 +356,23 @@ class IntervalMap { * Returns an iterator range that enumerates the nodes that overlap with the specified interval. * * @{ */ - boost::iterator_range findAll(const Interval &interval) { + dyncompat::iterator_range findAll(const Interval &interval) { return findAllImpl(*this, interval); } - boost::iterator_range findAll(const Interval &interval) const { + dyncompat::iterator_range findAll(const Interval &interval) const { return findAllImpl(*this, interval); } template - static boost::iterator_range::NodeIterator> + static dyncompat::iterator_range::NodeIterator> findAllImpl(IMap &imap, const Interval &interval) { typedef typename IntervalMapTraits::NodeIterator Iter; if (interval.isEmpty()) - return boost::iterator_range(imap.nodes().end(), imap.nodes().end()); + return dyncompat::iterator_range(imap.nodes().end(), imap.nodes().end()); Iter begin = imap.lowerBound(interval.least()); if (begin==imap.nodes().end() || begin->key().least() > interval.greatest()) - return boost::iterator_range(imap.nodes().end(), imap.nodes().end()); - return boost::iterator_range(begin, imap.upperBound(interval.greatest())); + return dyncompat::iterator_range(imap.nodes().end(), imap.nodes().end()); + return dyncompat::iterator_range(begin, imap.upperBound(interval.greatest())); } /** @} */ @@ -924,7 +925,7 @@ class IntervalMap { } // a more convenient way to check whether interval contains at least size items and still handle overflow - static bool isLarge(const Interval &interval, boost::uint64_t size) { + static bool isLarge(const Interval &interval, uint64_t size) { return !interval.isEmpty() && (interval.size()==0 || interval.size() >= size); } }; diff --git a/dataflowAPI/rose/util/IntervalSet.h b/dataflowAPI/rose/util/IntervalSet.h index d68803beb0..7a78d2f454 100644 --- a/dataflowAPI/rose/util/IntervalSet.h +++ b/dataflowAPI/rose/util/IntervalSet.h @@ -12,8 +12,10 @@ #include "Optional.h" #include "Sawyer.h" -#include -#include +#include +#include +#include +#include namespace Sawyer { namespace Container { @@ -38,7 +40,7 @@ namespace Container { * // Build the functionExtent and count total instruction size * Sawyer::Container::IntervalSet functionExtent; * uint32_t insnTotalSize = 0; - * BOOST_FOREACH (const AddressInterval &insnInterval, instructionIntervals) { + * DYN_FOREACH (const AddressInterval &insnInterval, instructionIntervals) { * functionExtent.insert(insnInterval); * insnTotalSize += insnInterval.size(); * } @@ -62,14 +64,14 @@ class IntervalSet { * * Iterates over the intervals of the container, which are the Interval type provided as a class template * parameter. Dereferencing the iterator will return a const reference to an interval (possibly a singlton interval). */ - class ConstIntervalIterator: public boost::iterator_facade { + class ConstIntervalIterator: public dyncompat::iterator_facade { typedef typename IntervalMap::ConstNodeIterator MapNodeIterator; MapNodeIterator iter_; public: ConstIntervalIterator() {} private: - friend class boost::iterator_core_access; + friend struct dyncompat::iterator_core_access; friend class IntervalSet; explicit ConstIntervalIterator(MapNodeIterator iter): iter_(iter) {} const Interval& dereference() const { return iter_->key(); } @@ -86,8 +88,8 @@ class IntervalSet { * @li The set can hold a very large number of values, even the entire value space, in which case iterating over values * rather than storage nodes could take a very long time. * @li Iterating over values for a non-integral type is most likely nonsensical. */ - class ConstScalarIterator: public boost::iterator_facade { + class ConstScalarIterator: public dyncompat::iterator_facade { ConstIntervalIterator iter_; typename Interval::Value offset_; mutable typename Interval::Value value_; // so dereference() can return a reference @@ -95,7 +97,7 @@ class IntervalSet { ConstScalarIterator(): offset_(0) {} ConstScalarIterator(ConstIntervalIterator iter): iter_(iter), offset_(0) {} private: - friend class boost::iterator_core_access; + friend struct dyncompat::iterator_core_access; friend class IntervalSet; const typename Interval::Value& dereference() const { ASSERT_require2(iter_->least() <= iter_->greatest(), "stored interval cannot be empty"); @@ -161,7 +163,7 @@ class IntervalSet { * The newly constructed set will contain copies of the intervals from the specified iterator range. The range's * dereferenced iterators must be convertible to the set's interval type. */ template - IntervalSet(const boost::iterator_range &intervals) { + IntervalSet(const dyncompat::iterator_range &intervals) { for (Iterator iter=intervals.begin(); iter!=intervals.end(); ++iter) insert(*iter); } @@ -199,7 +201,7 @@ class IntervalSet { * The newly constructed set will contain copies of the intervals from the specified iterator range. The range's * dereferenced iterators must be convertible to the set's interval type. */ template - IntervalSet& operator=(const boost::iterator_range &intervals) { + IntervalSet& operator=(const dyncompat::iterator_range &intervals) { clear(); for (Iterator iter=intervals.begin(); iter!=intervals.end(); ++iter) insert(*iter); @@ -211,14 +213,14 @@ class IntervalSet { //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// /** Iterator range for all intervals actually stored by this set. */ - boost::iterator_range intervals() const { - return boost::iterator_range(ConstIntervalIterator(map_.nodes().begin()), + dyncompat::iterator_range intervals() const { + return dyncompat::iterator_range(ConstIntervalIterator(map_.nodes().begin()), ConstIntervalIterator(map_.nodes().end())); } /** Iterator range for all scalar values logically represented by this set. */ - boost::iterator_range scalars() const { - return boost::iterator_range(ConstScalarIterator(intervals().begin()), + dyncompat::iterator_range scalars() const { + return dyncompat::iterator_range(ConstScalarIterator(intervals().begin()), ConstScalarIterator(intervals().end())); } @@ -253,9 +255,9 @@ class IntervalSet { /** Finds all nodes overlapping the specified interval. * * Returns an iterator range that enumerates the nodes that overlap with the specified interval. */ - boost::iterator_range findAll(const Interval &interval) const { - boost::iterator_range range = map_.findAll(interval); - return boost::iterator_range(ConstIntervalIterator(range.begin()), + dyncompat::iterator_range findAll(const Interval &interval) const { + dyncompat::iterator_range range = map_.findAll(interval); + return dyncompat::iterator_range(ConstIntervalIterator(range.begin()), ConstIntervalIterator(range.end())); } @@ -342,7 +344,7 @@ class IntervalSet { * * @{ */ template - bool isDistinct(const Interval2 &interval) const { + bool isDistinct(const Interval2 &/*interval*/) const { return !isOverlapping(); } diff --git a/dataflowAPI/rose/util/IntervalSetMap.h b/dataflowAPI/rose/util/IntervalSetMap.h index 2c1ef7c0d3..ba0746c911 100644 --- a/dataflowAPI/rose/util/IntervalSetMap.h +++ b/dataflowAPI/rose/util/IntervalSetMap.h @@ -8,7 +8,8 @@ #ifndef Sawyer_Container_IntervalSetMap_H #define Sawyer_Container_IntervalSetMap_H -#include +#include +#include #include "IntervalMap.h" #include "Sawyer.h" @@ -91,8 +92,8 @@ class IntervalSetMap: public IntervalMap { * Returns the union of the sets stored across an interval of keys. */ Set getUnion(const Interval &interval) const { Set retval; - BOOST_FOREACH (const typename Super::Node &node, this->findAll(interval)) { - BOOST_FOREACH (const typename Set::Value &member, node.value().values()) { + DYN_FOREACH (const typename Super::Node &node, this->findAll(interval)) { + DYN_FOREACH (const typename Set::Value &member, node.value().values()) { retval.insert(member); } } @@ -105,7 +106,7 @@ class IntervalSetMap: public IntervalMap { Set getIntersection(const Interval &interval) const { Set retval; size_t nNodes = 0; - BOOST_FOREACH (const typename Super::Node &node, this->findAll(interval)) { + DYN_FOREACH (const typename Super::Node &node, this->findAll(interval)) { const Set &set = this->get(node.key().least()); if (1 == ++nNodes) { retval = set; @@ -133,7 +134,7 @@ class IntervalSetMap: public IntervalMap { * returns false if the @p interval is empty. This is more efficient than calling getUnion(interval) and * checking whether it contains @p value. */ bool existsAnywhere(const Interval &interval, const typename Set::Value &value) const { - BOOST_FOREACH (const typename Super::Node &node, this->findAll(interval)) { + DYN_FOREACH (const typename Super::Node &node, this->findAll(interval)) { if (node.value().exists(value)) return true; } @@ -148,7 +149,7 @@ class IntervalSetMap: public IntervalMap { bool existsEverywhere(const Interval &interval, const typename Set::Value &value) const { if (interval.isEmpty()) return false; - BOOST_FOREACH (const typename Super::Node &node, this->findAll(interval)) { + DYN_FOREACH (const typename Super::Node &node, this->findAll(interval)) { if (!node.value().exists(value)) return false; } diff --git a/dataflowAPI/rose/util/LinearCongruentialGenerator.C b/dataflowAPI/rose/util/LinearCongruentialGenerator.C index 28478e652d..bb588093c7 100644 --- a/dataflowAPI/rose/util/LinearCongruentialGenerator.C +++ b/dataflowAPI/rose/util/LinearCongruentialGenerator.C @@ -1,14 +1,20 @@ #define __STDC_LIMIT_MACROS #include "LinearCongruentialGenerator.h" +#include #include "../integerOps.h" +#include #include +#include #include +#include #include +#include #ifndef _MSC_VER #include +#include #endif #ifndef _MSC_VER diff --git a/dataflowAPI/rose/util/LinearCongruentialGenerator.h b/dataflowAPI/rose/util/LinearCongruentialGenerator.h index f32f9602b9..b321ebd032 100644 --- a/dataflowAPI/rose/util/LinearCongruentialGenerator.h +++ b/dataflowAPI/rose/util/LinearCongruentialGenerator.h @@ -1,6 +1,7 @@ #ifndef ROSE_LinearCongruentialGenerator_H #define ROSE_LinearCongruentialGenerator_H +#include #include #include diff --git a/dataflowAPI/rose/util/Map.h b/dataflowAPI/rose/util/Map.h index d304017511..3b02213505 100644 --- a/dataflowAPI/rose/util/Map.h +++ b/dataflowAPI/rose/util/Map.h @@ -11,7 +11,10 @@ #include "Interval.h" #include "Optional.h" #include "Sawyer.h" -#include +#include +#include +#include +#include #include #include @@ -100,7 +103,13 @@ class Map { //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// private: template - class BidirectionalIterator: public std::iterator { + class BidirectionalIterator { + public: + using iterator_category = std::bidirectional_iterator_tag; + using value_type = Value; + using difference_type = std::ptrdiff_t; + using pointer = value_type*; + using reference = value_type&; protected: BaseIterator base_; BidirectionalIterator() {} @@ -128,7 +137,6 @@ class Map { typedef BidirectionalIterator Super; public: NodeIterator() {} - NodeIterator(const NodeIterator &other): Super(other) {} // std::map stores std::pair nodes, but we want to return Node, which must have the same layout. Node& operator*() const { return *(Node*)&*this->base_; } Node* operator->() const { return (Node*)&*this->base_; } @@ -230,7 +238,7 @@ class Map { template Map(const Map &other) { typedef typename Map::ConstNodeIterator OtherIterator; - boost::iterator_range otherNodes = other.nodes(); + dyncompat::iterator_range otherNodes = other.nodes(); for (OtherIterator otherIter=otherNodes.begin(); otherIter!=otherNodes.end(); ++otherIter) map_.insert(map_.end(), std::make_pair(Key(otherIter->key()), Value(otherIter->value()))); } @@ -242,7 +250,7 @@ class Map { Map& operator=(const Map &other) { typedef typename Map::ConstNodeIterator OtherIterator; clear(); - boost::iterator_range otherNodes = other.nodes(); + dyncompat::iterator_range otherNodes = other.nodes(); for (OtherIterator otherIter=otherNodes.begin(); otherIter!=otherNodes.end(); ++otherIter) map_.insert(map_.end(), std::make_pair(Key(otherIter->key()), Value(otherIter->value()))); } @@ -257,11 +265,11 @@ class Map { * This returns a range of node-iterators that will traverse all nodes (key/value pairs) of this container. * * @{ */ - boost::iterator_range nodes() { - return boost::iterator_range(NodeIterator(map_.begin()), NodeIterator(map_.end())); + dyncompat::iterator_range nodes() { + return dyncompat::iterator_range(NodeIterator(map_.begin()), NodeIterator(map_.end())); } - boost::iterator_range nodes() const { - return boost::iterator_range(ConstNodeIterator(map_.begin()), ConstNodeIterator(map_.end())); + dyncompat::iterator_range nodes() const { + return dyncompat::iterator_range(ConstNodeIterator(map_.begin()), ConstNodeIterator(map_.end())); } /** @} */ @@ -270,11 +278,11 @@ class Map { * Returns a range of key-iterators that will traverse the keys of this container. * * @{ */ - boost::iterator_range keys() { - return boost::iterator_range(NodeIterator(map_.begin()), NodeIterator(map_.end())); + dyncompat::iterator_range keys() { + return dyncompat::iterator_range(NodeIterator(map_.begin()), NodeIterator(map_.end())); } - boost::iterator_range keys() const { - return boost::iterator_range(ConstNodeIterator(map_.begin()), ConstNodeIterator(map_.end())); + dyncompat::iterator_range keys() const { + return dyncompat::iterator_range(ConstNodeIterator(map_.begin()), ConstNodeIterator(map_.end())); } /** @} */ @@ -284,11 +292,11 @@ class Map { * key order, although the keys are not directly available via these iterators. * * @{ */ - boost::iterator_range values() { - return boost::iterator_range(NodeIterator(map_.begin()), NodeIterator(map_.end())); + dyncompat::iterator_range values() { + return dyncompat::iterator_range(NodeIterator(map_.begin()), NodeIterator(map_.end())); } - boost::iterator_range values() const { - return boost::iterator_range(ConstNodeIterator(map_.begin()), ConstNodeIterator(map_.end())); + dyncompat::iterator_range values() const { + return dyncompat::iterator_range(ConstNodeIterator(map_.begin()), ConstNodeIterator(map_.end())); } /** @} */ @@ -558,7 +566,7 @@ class Map { return *this; } template - Map& insertMultiple(const boost::iterator_range &range) { + Map& insertMultiple(const dyncompat::iterator_range &range) { return insertMultiple(range.begin(), range.end()); } /** @} */ @@ -592,7 +600,7 @@ class Map { * * @sa insert insertDefault insertMaybe insertMaybeDefault insertMultiple */ template - Map& insertMaybeMultiple(const boost::iterator_range &range) { + Map& insertMaybeMultiple(const dyncompat::iterator_range &range) { for (OtherNodeIterator otherIter=range.begin(); otherIter!=range.end(); ++otherIter) insert(Key(otherIter->key()), Value(otherIter->value())); return *this; @@ -628,7 +636,7 @@ class Map { * * @sa erase eraseAt eraseAtMultiple */ template - Map& eraseMultiple(const boost::iterator_range &range) { + Map& eraseMultiple(const dyncompat::iterator_range &range) { for (OtherKeyIterator otherIter=range.begin(); otherIter!=range.end(); ++otherIter) map_.erase(Key(*otherIter)); return *this; @@ -668,7 +676,7 @@ class Map { return *this; } template - Map& eraseAtMultiple(const boost::iterator_range &range) { + Map& eraseAtMultiple(const dyncompat::iterator_range &range) { map_.erase(range.begin().base(), range.end().base()); return *this; } diff --git a/dataflowAPI/rose/util/MappedBuffer.h b/dataflowAPI/rose/util/MappedBuffer.h index 36ccabb999..e69de29bb2 100644 --- a/dataflowAPI/rose/util/MappedBuffer.h +++ b/dataflowAPI/rose/util/MappedBuffer.h @@ -1,112 +0,0 @@ -// WARNING: Changes to this file must be contributed back to Sawyer or else they will -// be clobbered by the next update from Sawyer. The Sawyer repository is at -// https://github.com/matzke1/sawyer. - - - - -#ifndef Sawyer_MappedBuffer_H -#define Sawyer_MappedBuffer_H - -#include "AllocatingBuffer.h" -#include "Buffer.h" -#include "Sawyer.h" - -#include -#include -#include - -namespace Sawyer { -namespace Container { - -/** Memory mapped file. - * - * This buffer points to a file that is mapped into memory by the operating system. The API supports a common divisor for - * POSIX and Microsoft Windows and is therefore not all that powerful, but it does allow simple maps to be created that have a - * file as backing store. See http://www.boost.org/doc/libs for more information. - * - * Access modes are the following enumerated constants: - * - * @li boost::iostreams::mapped_file::readonly: shared read-only access - * @li boost::iostreams::mapped_file::readwrite: shared read/write access - * @li boost::iostreams::mapped_file::priv: private read/write access - * - * When a file is mapped with private access changes written to the buffer are not reflected in the underlying file. */ -template -class MappedBuffer: public Buffer { - boost::iostreams::mapped_file_params params_; - boost::iostreams::mapped_file device_; -public: - typedef A Address; - typedef T Value; -protected: - MappedBuffer(const boost::iostreams::mapped_file_params ¶ms): params_(params), device_(params) {} - -public: - /** Map a file according to boost parameters. - * - * The parameters describe which file (by name) and part thereof should be mapped into memory. */ - static typename Buffer::Ptr instance(const boost::iostreams::mapped_file_params ¶ms) { - return typename Buffer::Ptr(new MappedBuffer(params)); - } - - /** Map a file by name. - * - * The specified file, which must already exist, is mapped into memory and pointed to by this new buffer. */ - static typename Buffer::Ptr - instance(const std::string &path, - boost::iostreams::mapped_file::mapmode mode=boost::iostreams::mapped_file::readonly, - boost::intmax_t offset=0, - boost::iostreams::mapped_file::size_type length=boost::iostreams::mapped_file::max_length) { - boost::iostreams::mapped_file_params params(path); - params.flags = mode; - params.length = length; - params.offset = offset; - return typename Buffer::Ptr(new MappedBuffer(params)); - } - - // It doesn't make sense to copy a memory-mapped buffer since the point of copying is to result in two independent buffers - // pointing to non-shared data. If a shared, writable, memory-mapped buffer is backed by a file and we make a new copy also - // backed by the file, then changing one buffer would change the other. Therefore, we allocate new memory that will hold a - // snapshot of the source buffer. - typename Buffer::Ptr copy() const /*override*/ { - typename Buffer::Ptr newBuffer = AllocatingBuffer::instance(this->size()); - Address nWritten = newBuffer->write((const Value*)device_.data(), 0, this->size()); - if (nWritten != this->size()) { - throw std::runtime_error("MappedBuffer::copy() failed after copying " + - boost::lexical_cast(nWritten) + " of " + - boost::lexical_cast(this->size()) + - (1==this->size()?" value":" values")); - } - return newBuffer; - } - - Address available(Address address) const /*override*/ { - return address >= device_.size() ? Address(0) : (Address(device_.size()) - address) / sizeof(Value); - } - - void resize(Address n) /*override*/ { - if (n != device_.size()) - throw std::runtime_error("resizing not allowed for MappedBuffer"); - } - - Address read(Value *buf, Address address, Address n) const /*override*/ { - Address nread = std::min(n, available(address)); - memcpy(buf, device_.const_data() + address, nread * sizeof(Value)); - return nread; - } - - Address write(const Value *buf, Address address, Address n) /*override*/ { - Address nwritten = std::min(n, available(address)); - memcpy(device_.data() + address, buf, nwritten * sizeof(Value)); - return nwritten; - } - - const Value* data() const /*override*/ { - return (Value*)device_.const_data(); - } -}; - -} // namespace -} // namespace -#endif diff --git a/dataflowAPI/rose/util/Message.C b/dataflowAPI/rose/util/Message.C index 5e276f97df..b74a7ec721 100644 --- a/dataflowAPI/rose/util/Message.C +++ b/dataflowAPI/rose/util/Message.C @@ -5,17 +5,19 @@ +#include #include "Message.h" -#include -#include -#include -#include -#include -#include +#include +#include +#include +#include +#include +#include #include #include #include +#include #include #include #include "Sawyer.h" @@ -25,7 +27,7 @@ #include #include -#ifdef BOOST_WINDOWS +#ifdef _WIN32 //# include # include # include @@ -35,8 +37,8 @@ #endif #if defined(SAWYER_HAVE_BOOST_CHRONO) -# include -#elif defined(BOOST_WINDOWS) +#include +#elif defined(_WIN32) # include # include # undef ERROR // not sure where this pollution comes from @@ -121,11 +123,11 @@ SAWYER_EXPORT double now() { #if defined(SAWYER_HAVE_BOOST_CHRONO) // Boost::chrono is thread-safe since we're using only stack allocated objects - boost::chrono::system_clock::time_point curtime = boost::chrono::system_clock::now(); - boost::chrono::system_clock::time_point epoch; - boost::chrono::duration diff = curtime - epoch; + std::chrono::system_clock::time_point curtime = std::chrono::system_clock::now(); + std::chrono::system_clock::time_point epoch; + std::chrono::duration diff = curtime - epoch; return diff.count(); -#elif defined(BOOST_WINDOWS) +#elif defined(_WIN32) FILETIME ft; GetSystemTimeAsFileTime(&ft); unsigned __int64 t = ft.dwHighDateTime; @@ -177,7 +179,7 @@ MesgProps::merge(const MesgProps &other) const { retval.facilityName = other.facilityName; if (!importance) retval.importance = other.importance; - if (indeterminate(isBuffered)) + if (dyncompat::indeterminate(isBuffered)) retval.isBuffered = other.isBuffered; if (!completionStr) retval.completionStr = other.completionStr; @@ -187,7 +189,7 @@ MesgProps::merge(const MesgProps &other) const { retval.cancelationStr = other.cancelationStr; if (!lineTermination) retval.lineTermination = other.lineTermination; - if (indeterminate(useColor)) + if (dyncompat::indeterminate(useColor)) retval.useColor = other.useColor; return retval; } @@ -211,7 +213,7 @@ MesgProps::print(std::ostream &o) const { } o <<", isBuffered="; - if (!indeterminate(isBuffered)) { + if (!dyncompat::indeterminate(isBuffered)) { o <<(isBuffered ? "yes" : "no"); } else { o <<"undef"; @@ -246,7 +248,7 @@ MesgProps::print(std::ostream &o) const { } o <<", useColor="; - if (!indeterminate(useColor)) { + if (!dyncompat::indeterminate(useColor)) { o <<(useColor ? "yes" : "no"); } else { o <<"undef"; @@ -288,7 +290,7 @@ Mesg::post(const BakedDestinations &baked) const { SAWYER_EXPORT bool Mesg::hasText() const { - return boost::find_token(text_, boost::is_graph()); + return std::any_of(text_.begin(), text_.end(), [](unsigned char c){ return std::isgraph(c); }); } //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// @@ -654,7 +656,7 @@ Prefix::silentInstance() { // thread-safe (assuming Windows API is thread-safe) SAWYER_EXPORT void Prefix::setProgramName() { -#ifdef BOOST_WINDOWS +#ifdef _WIN32 # if 0 // [Robb Matzke 2014-06-13] temporarily disable for ROSE linking error (needs psapi.lib in Windows) if (HANDLE handle = OpenProcess(PROCESS_QUERY_INFORMATION | PROCESS_VM_READ, FALSE, GetCurrentProcessId())) { TCHAR buffer[MAX_PATH]; @@ -755,7 +757,7 @@ Prefix::toString(const Mesg &mesg, const MesgProps &props) const { programNameShown = *programName_; retval <<*programName_; if (showThreadId_) { -#ifdef BOOST_WINDOWS +#ifdef _WIN32 retval <<"[" <get(imp).enable(impset_.find(imp)!=impset_.end()); @@ -1669,7 +1671,7 @@ Facilities::reenable() { SAWYER_EXPORT Facilities& Facilities::reenableFrom(const Facilities &other) { LockGuard2 lock(mutex_, other.mutex_); - BOOST_FOREACH (const FacilityMap::Node &src, other.facilities_.nodes()) { + DYN_FOREACH (const FacilityMap::Node &src, other.facilities_.nodes()) { FacilityMap::NodeIterator fi_dst = facilities_.find(src.key()); if (fi_dst!=facilities_.nodes().end()) { for (int i=0; iget(imp).enable(b); return *this; } @@ -1724,7 +1726,7 @@ Facilities::enableNS(Importance imp, bool b) { SAWYER_EXPORT Facilities& Facilities::enable(bool b) { SAWYER_THREAD_TRAITS::LockGuard lock(mutex_); - BOOST_FOREACH (Facility *facility, facilities_.values()) { + DYN_FOREACH (Facility *facility, facilities_.values()) { if (b) { for (int i=0; i Facilities::facilityNames() const { SAWYER_THREAD_TRAITS::LockGuard lock(mutex_); std::vector allNames; - BOOST_FOREACH (const std::string &name, facilities_.keys()) + DYN_FOREACH (const std::string &name, facilities_.keys()) allNames.push_back(name); return allNames; } @@ -2048,7 +2050,7 @@ Facilities::print(std::ostream &log) const { if (facilities_.isEmpty()) { log <<"no message facilities registered\n"; } else { - BOOST_FOREACH (const FacilityMap::Node &fnode, facilities_.nodes()) { + DYN_FOREACH (const FacilityMap::Node &fnode, facilities_.nodes()) { Facility *facility = fnode.value(); // A short easy to read format. Letters indicate the importances that are enabled; dashes keep them aligned. @@ -2068,7 +2070,7 @@ Facilities::print(std::ostream &log) const { void FacilitiesGuard::save() { - BOOST_FOREACH (const std::string &facilityName, facilities_.facilityNames()) { + DYN_FOREACH (const std::string &facilityName, facilities_.facilityNames()) { std::vector facilityState = state_.insertMaybeDefault(facilityName); facilityState.resize(N_IMPORTANCE, false); Facility &facility = facilities_.facility(facilityName); @@ -2079,7 +2081,7 @@ FacilitiesGuard::save() { void FacilitiesGuard::restore() { - BOOST_FOREACH (const State::Node &saved, state_.nodes()) { + DYN_FOREACH (const State::Node &saved, state_.nodes()) { try { Facility &facility = facilities_.facility(saved.key()); for (int i=0; i -#include +#include +#include +#include +#include #include #include #include @@ -373,7 +375,7 @@ struct SAWYER_EXPORT ColorSpec { AnsiColor foreground; /**< Foreground color, or @ref COLOR_DEFAULT. */ AnsiColor background; /**< Background color, or @ref COLOR_DEFAULT. */ #include "WarningsOff.h" - boost::tribool bold; /**< Use ANSI "bold" attribute? */ + dyncompat::tribool bold; /**< Use ANSI "bold" attribute? */ #include "WarningsRestore.h" /** Constructs an object with default foreground and background colors. */ @@ -426,15 +428,15 @@ struct SAWYER_EXPORT MesgProps { #include "WarningsOff.h" Optional facilityName; /**< The name of the logging facility that produced this message. */ Optional importance; /**< The message importance level. */ - boost::tribool isBuffered; /**< Whether the output buffered and emitted on a per-message basis. */ + dyncompat::tribool isBuffered; /**< Whether the output buffered and emitted on a per-message basis. */ Optional completionStr; /**< String to append to the end of each complete message. */ Optional interruptionStr; /**< String to append when a partial message is interrupted. */ Optional cancelationStr; /**< String to append to a partial message when it is destroyed. */ Optional lineTermination; /**< Line termination for completion, interruption, and cancelation. */ - boost::tribool useColor; /**< Whether to use ANSI escape sequences to colorize output. */ + dyncompat::tribool useColor; /**< Whether to use ANSI escape sequences to colorize output. */ #include "WarningsRestore.h" - MesgProps(): isBuffered(boost::indeterminate), useColor(boost::indeterminate) {} + MesgProps(): isBuffered(dyncompat::indeterminate), useColor(dyncompat::indeterminate) {} /** Merge the specified properties into this object and return new properties. Each property of the return value will be * the value from this object, except when this object's property is missing, in which case the property value from the @@ -1326,7 +1328,7 @@ class SAWYER_EXPORT StreamSink: public UnformattedSink { virtual void post(const Mesg&, const MesgProps&) /*override*/; }; -#ifndef BOOST_WINDOWS +#ifndef _WIN32 /** Sends messages to the syslog daemon. * * Thread safety: Unknown (depends on whether syslog is thread-safe). */ diff --git a/dataflowAPI/rose/util/Optional.h b/dataflowAPI/rose/util/Optional.h index dcfb9d28f5..b043f9f55e 100644 --- a/dataflowAPI/rose/util/Optional.h +++ b/dataflowAPI/rose/util/Optional.h @@ -36,7 +36,7 @@ class Nothing { // final /** Holds a value or nothing. * - * This class is similar to boost::optional except simpler in order to avoid problems we were seeing with Microsoft + * This class is similar to dyncompat::optional except simpler in order to avoid problems we were seeing with Microsoft * compilers. * * The stored value type (@ref Value) cannot be a reference type. */ @@ -300,13 +300,13 @@ class Optional { // if (x && *x == y) // what they really meant // if (x.isEqual(y)) // another valid way to write it template -bool operator==(const Optional &lhs, const U &rhs) { +bool operator==(const Optional &lhs, const U &/*rhs*/) { lhs.this_type_does_not_support_comparisons(); return false; } template -bool operator!=(const Optional &lhs, const U &rhs) { +bool operator!=(const Optional &lhs, const U &/*rhs*/) { lhs.this_type_does_not_support_comparisons(); return false; } diff --git a/dataflowAPI/rose/util/PoolAllocator.h b/dataflowAPI/rose/util/PoolAllocator.h index cf695eb9ce..df6de8d356 100644 --- a/dataflowAPI/rose/util/PoolAllocator.h +++ b/dataflowAPI/rose/util/PoolAllocator.h @@ -8,10 +8,16 @@ #ifndef Sawyer_PoolAllocator_H #define Sawyer_PoolAllocator_H -#include -#include -#include -#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include #include #include "Assert.h" #include "Interval.h" @@ -70,7 +76,7 @@ class PoolAllocatorBase { // Singly-linked list of cells (units of object backing store) that are not being used by the caller. struct FreeCell { FreeCell *next; }; - typedef Sawyer::Container::Interval ChunkAddressInterval; + typedef Sawyer::Container::Interval ChunkAddressInterval; //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// // Basic unit of allocation. @@ -79,7 +85,7 @@ class PoolAllocatorBase { class Chunk { unsigned char data_[chunkSize]; public: - BOOST_STATIC_ASSERT(chunkSize >= sizeof(FreeCell)); + DYN_STATIC_ASSERT(chunkSize >= sizeof(FreeCell)); FreeCell* fill(size_t cellSize) { // create a free list for this chunk ASSERT_require(cellSize >= sizeof(FreeCell)); @@ -95,8 +101,8 @@ class PoolAllocatorBase { } ChunkAddressInterval extent() const { - return ChunkAddressInterval::hull(reinterpret_cast(data_), - reinterpret_cast(data_+chunkSize-1)); + return ChunkAddressInterval::hull(reinterpret_cast(data_), + reinterpret_cast(data_+chunkSize-1)); } }; @@ -108,7 +114,7 @@ class PoolAllocatorBase { const Chunk *chunk; size_t nUsed; ChunkInfo(): chunk(NULL), nUsed(0) {} - ChunkInfo(const Chunk *chunk, size_t nUsed): chunk(chunk), nUsed(nUsed) {} + ChunkInfo(const Chunk *chunk_, size_t nUsed_): chunk(chunk_), nUsed(nUsed_) {} bool operator==(const ChunkInfo &other) const { return chunk==other.chunk && nUsed==other.nUsed; } @@ -163,7 +169,7 @@ class PoolAllocatorBase { Pool(const Pool&); // nonsense public: - Pool(): cellSize_(0) {} + Pool(): cellSize_(0), freeLists_{} {} void init(size_t cellSize) { assert(cellSize_ == 0); @@ -180,6 +186,8 @@ class PoolAllocatorBase { delete *ci; } +DYNINST_DIAGNOSTIC_BEGIN_SUPPRESS_UNUSED_VARIABLE + bool isEmpty() const { SAWYER_THREAD_TRAITS::LockGuard lock(chunkMutex_); return chunks_.empty(); @@ -192,7 +200,7 @@ class PoolAllocatorBase { if (!freeLists_[freeListIdx]) { Chunk *chunk = new Chunk; freeLists_[freeListIdx] = chunk->fill(cellSize_); - SAWYER_THREAD_TRAITS::LockGuard lock(chunkMutex_); + SAWYER_THREAD_TRAITS::LockGuard chunkLock(chunkMutex_); chunks_.push_back(chunk); } ASSERT_not_null(freeLists_[freeListIdx]); @@ -212,14 +220,16 @@ class PoolAllocatorBase { freeLists_[freeListIdx] = freedCell; } +DYNINST_DIAGNOSTIC_END_SUPPRESS_UNUSED_VARIABLE + // Information about each chunk. ChunkInfoMap chunkInfoNS() const { ChunkInfoMap map; - BOOST_FOREACH (const Chunk* chunk, chunks_) + DYN_FOREACH (const Chunk* chunk, chunks_) map.insert(chunk->extent(), ChunkInfo(chunk, chunkSize / cellSize_)); for (size_t freeListIdx = 0; freeListIdx < N_FREE_LISTS; ++freeListIdx) { for (FreeCell *cell=freeLists_[freeListIdx]; cell!=NULL; cell=cell->next) { - typename ChunkInfoMap::ValueIterator found = map.find(reinterpret_cast(cell)); + typename ChunkInfoMap::ValueIterator found = map.find(reinterpret_cast(cell)); ASSERT_require2(found!=map.values().end(), "each freelist item must be some chunk cell"); ASSERT_require2(found->nUsed > 0, "freelist must be consistent with chunk capacities"); --found->nUsed; @@ -281,7 +291,7 @@ class PoolAllocatorBase { FreeCell *next = NULL; for (FreeCell *cell = freeLists_[oldFreeListIdx]; cell != NULL; cell = next) { next = cell->next; - boost::uint64_t cellAddr = reinterpret_cast(cell); + uint64_t cellAddr = reinterpret_cast(cell); if (map[cellAddr].nUsed != 0) { // Keep this cell by round-robin inserting it into a new free list. cell->next = newFreeLists[newFreeListIdx]; @@ -297,7 +307,7 @@ class PoolAllocatorBase { typename std::list::iterator iter = chunks_.begin(); while (iter!=chunks_.end()) { Chunk *chunk = *iter; - boost::uint64_t cellAddr = chunk->extent().least(); // any cell will do + uint64_t cellAddr = chunk->extent().least(); // any cell will do if (map[cellAddr].nUsed == 0) { delete chunk; iter = chunks_.erase(iter); @@ -316,7 +326,7 @@ class PoolAllocatorBase { const size_t nCells = chunkSize / cellSize_; size_t totalUsed=0; - BOOST_FOREACH (const ChunkInfo &info, cim.values()) { + DYN_FOREACH (const ChunkInfo &info, cim.values()) { out <<" chunk " < -#include +#include +#include +#include +#include +#include #include #include @@ -329,7 +332,7 @@ #define SAWYER_THREAD_LOCAL /*void*/ #endif -#ifdef BOOST_WINDOWS +#ifdef _WIN32 // FIXME[Robb Matzke 2014-06-18]: get rid of ROSE_UTIL_EXPORTS; cmake can only have one DEFINE_SYMBOL # if defined(SAWYER_DO_EXPORTS) || defined(ROSE_UTIL_EXPORTS) // defined in CMake when compiling libsawyer # define SAWYER_EXPORT __declspec(dllexport) @@ -369,12 +372,12 @@ SAWYER_EXPORT bool initializeLibrary(size_t vmajor=SAWYER_VERSION_MAJOR, /** Portable replacement for ::strtoll * * Microsoft doesn't define this function, so we define it in the Sawyer namespace. */ -SAWYER_EXPORT boost::int64_t strtoll(const char*, char**, int); +SAWYER_EXPORT int64_t strtoll(const char*, char**, int); /** Portable replacement for ::strtoull * * Microsoft doesn't define this function, so we define it in the Sawyer namespace. */ -SAWYER_EXPORT boost::uint64_t strtoull(const char*, char**, int); +SAWYER_EXPORT uint64_t strtoull(const char*, char**, int); /** Reads one line of input from a file. * @@ -406,9 +409,9 @@ SAWYER_EXPORT std::string generateSequentialName(size_t length=3); // preprocessor. // // The following macros are used to distinguish between different target environments, regardless of what compiler is being -// used or the environment which is doing the compiling. For instance, BOOST_WINDOWS will be defined when using the MinGW +// used or the environment which is doing the compiling. For instance, _WIN32 will be defined when using the MinGW // compiler on Linux to target a Windows environment. -// BOOST_WINDOWS The Windows API is present. This is defined (or not) by including . +// _WIN32 The Windows API is present. This is defined (or not) by including . // //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// @@ -464,8 +467,9 @@ SAWYER_EXPORT std::string generateSequentialName(size_t length=3); // causes the initialization to happen as early as possible after the C++ runtime. # define SAWYER_STATIC_INIT __attribute__((init_priority(101))) +#include "compiler_diagnostics.h" # define SAWYER_VARIABLE_LENGTH_ARRAY(TYPE, NAME, SIZE) \ - TYPE NAME[SIZE]; + DYNINST_DIAGNOSTIC_BEGIN_SUPPRESS_VLA_ALL TYPE NAME[SIZE]; DYNINST_DIAGNOSTIC_END_SUPPRESS_VLA_ALL #endif diff --git a/dataflowAPI/rose/util/Set.h b/dataflowAPI/rose/util/Set.h index 440d8103c4..8207e47354 100644 --- a/dataflowAPI/rose/util/Set.h +++ b/dataflowAPI/rose/util/Set.h @@ -11,8 +11,10 @@ #include "Interval.h" #include "Sawyer.h" -#include -#include +#include +#include +#include +#include #include #include @@ -82,8 +84,8 @@ class Set { : set_(begin, end, comparator, allocator) {} template - explicit Set(const boost::iterator_range &range, - const Comparator &comparator = Comparator(), const Allocator &allocator = Allocator()) + explicit Set(const dyncompat::iterator_range &range, + const Comparator &/*comparator*/ = Comparator(), const Allocator &/*allocator*/ = Allocator()) : set_(range.begin(), range.end()) {} /** @} */ @@ -104,8 +106,8 @@ class Set { /** Value iterator range. * * Returns an iterator range that covers all values in the set. */ - boost::iterator_range values() const { - return boost::iterator_range(set_.begin(), set_.end()); + dyncompat::iterator_range values() const { + return dyncompat::iterator_range(set_.begin(), set_.end()); } //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// @@ -130,7 +132,7 @@ class Set { * * Returns true if any of the specified values exist in this set. */ bool existsAny(const Set &other) const { - BOOST_FOREACH (const Value &otherValue, other.values()) { + DYN_FOREACH (const Value &otherValue, other.values()) { if (exists(otherValue)) return true; } @@ -141,7 +143,7 @@ class Set { * * Returns true if all specified values exist in this set. */ bool existsAll(const Set &other) const { - BOOST_FOREACH (const Value &otherValue, other.values()) { + DYN_FOREACH (const Value &otherValue, other.values()) { if (!exists(otherValue)) return false; } @@ -215,7 +217,7 @@ class Set { * already members of this set. */ bool insert(const Set &values) { bool isInserted = false; - BOOST_FOREACH (const Value &value, values.values()) { + DYN_FOREACH (const Value &value, values.values()) { if (set_.insert(value).second) isInserted = true; } @@ -235,7 +237,7 @@ class Set { * were members of this set. */ bool erase(const Set &values) { bool isErased = false; - BOOST_FOREACH (const Value &value, values.values()) { + DYN_FOREACH (const Value &value, values.values()) { if (1 == set_.erase(value)) isErased = true; } @@ -255,11 +257,11 @@ class Set { Set& operator&=(const Set &other) { std::vector toErase; toErase.reserve(set_.size()); - BOOST_FOREACH (const Value &value, set_) { + DYN_FOREACH (const Value &value, set_) { if (!other.exists(value)) toErase.push_back(value); } - BOOST_FOREACH (const Value &value, toErase) + DYN_FOREACH (const Value &value, toErase) set_.erase(value); return *this; } @@ -268,7 +270,7 @@ class Set { * * Adds those members of @p other that are not already members of this set. */ Set& operator|=(const Set &other) { - BOOST_FOREACH (const Value &v, other.values()) + DYN_FOREACH (const Value &v, other.values()) set_.insert(v); return *this; } @@ -280,11 +282,11 @@ class Set { Set& operator-=(const Set &other) { std::vector toErase; toErase.reserve(set_.size()); - BOOST_FOREACH (const Value &value, set_) { + DYN_FOREACH (const Value &value, set_) { if (other.exists(value)) toErase.push_back(value); } - BOOST_FOREACH (const Value &value, toErase) + DYN_FOREACH (const Value &value, toErase) set_.erase(value); return *this; } diff --git a/dataflowAPI/rose/util/SharedPointer.h b/dataflowAPI/rose/util/SharedPointer.h index e69d79fd8d..99badff223 100644 --- a/dataflowAPI/rose/util/SharedPointer.h +++ b/dataflowAPI/rose/util/SharedPointer.h @@ -8,6 +8,8 @@ #ifndef Sawyer_SharedPtr_H #define Sawyer_SharedPtr_H +#include +#include #include #include #include "Assert.h" @@ -20,7 +22,7 @@ namespace Sawyer { /** Reference-counting smart pointer. * * This class is a reference-counting pointer to an object that inherits from @ref SharedObject. Usage is similar to - * boost::shared_ptr. + * dyncompat::shared_ptr. * * @sa SharedObject, @ref SharedFromThis * @@ -353,6 +355,8 @@ class SharedFromThis { // Implementations //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +DYNINST_DIAGNOSTIC_BEGIN_SUPPRESS_UNUSED_VARIABLE + template inline size_t SharedPointer::ownershipCount(T *rawPtr) { if (rawPtr) { @@ -381,5 +385,7 @@ inline size_t SharedPointer::releaseOwnership(Pointee *rawPtr) { } } +DYNINST_DIAGNOSTIC_END_SUPPRESS_UNUSED_VARIABLE + } // namespace #endif diff --git a/dataflowAPI/rose/util/SmallObject.h b/dataflowAPI/rose/util/SmallObject.h index e09d4d1c43..0b8906c4f4 100644 --- a/dataflowAPI/rose/util/SmallObject.h +++ b/dataflowAPI/rose/util/SmallObject.h @@ -8,6 +8,7 @@ #ifndef Sawyer_SmallObject_H #define Sawyer_SmallObject_H +#include #include "PoolAllocator.h" #include "Sawyer.h" diff --git a/dataflowAPI/rose/util/StaticBuffer.h b/dataflowAPI/rose/util/StaticBuffer.h index a306b49e34..43eb6a410f 100644 --- a/dataflowAPI/rose/util/StaticBuffer.h +++ b/dataflowAPI/rose/util/StaticBuffer.h @@ -8,6 +8,8 @@ #ifndef Sawyer_StaticBuffer_H #define Sawyer_StaticBuffer_H +#include +#include #include "AllocatingBuffer.h" #include "Assert.h" #include "Buffer.h" @@ -61,8 +63,8 @@ class StaticBuffer: public Buffer { Address nWritten = newBuffer->write(values_, 0, size_); if (nWritten != size_) { throw std::runtime_error("StaticBuffer::copy() failed after copying " + - boost::lexical_cast(nWritten) + " of " + - boost::lexical_cast(size_) + + dyncompat::lexical_cast(nWritten) + " of " + + dyncompat::lexical_cast(size_) + (1==size_?" value":" values")); } return newBuffer; diff --git a/dataflowAPI/rose/util/Stopwatch.C b/dataflowAPI/rose/util/Stopwatch.C index 0512aecb7d..bb8b6a1f6f 100644 --- a/dataflowAPI/rose/util/Stopwatch.C +++ b/dataflowAPI/rose/util/Stopwatch.C @@ -10,9 +10,9 @@ #include #if defined(SAWYER_HAVE_BOOST_CHRONO) -# include -# include -#elif defined(BOOST_WINDOWS) +#include + +#elif defined(_WIN32) # include # include # undef ERROR // not sure where this pollution comes from @@ -25,8 +25,8 @@ namespace Sawyer { static Stopwatch::TimePoint getCurrentTime() { #if defined(SAWYER_HAVE_BOOST_CHRONO) - return boost::chrono::high_resolution_clock::now(); -#elif defined(BOOST_WINDOWS) + return std::chrono::high_resolution_clock::now(); +#elif defined(_WIN32) FILETIME ft; GetSystemTimeAsFileTime(&ft); unsigned __int64 t = ft.dwHighDateTime; diff --git a/dataflowAPI/rose/util/Stopwatch.h b/dataflowAPI/rose/util/Stopwatch.h index 01889b0d59..b31181cf4a 100644 --- a/dataflowAPI/rose/util/Stopwatch.h +++ b/dataflowAPI/rose/util/Stopwatch.h @@ -8,11 +8,12 @@ #ifndef Sawyer_Stopwatch_H #define Sawyer_Stopwatch_H +#include #include "Sawyer.h" #ifdef SAWYER_HAVE_BOOST_CHRONO -# include -# include +#include + #endif namespace Sawyer { @@ -41,8 +42,8 @@ namespace Sawyer { class SAWYER_EXPORT Stopwatch { public: #ifdef SAWYER_HAVE_BOOST_CHRONO - typedef boost::chrono::high_resolution_clock::time_point TimePoint; - typedef boost::chrono::duration Duration; + typedef std::chrono::high_resolution_clock::time_point TimePoint; + typedef std::chrono::duration Duration; #else typedef double TimePoint; typedef double Duration; diff --git a/dataflowAPI/rose/util/StringUtility.C b/dataflowAPI/rose/util/StringUtility.C index 85e82a780d..9f12551234 100644 --- a/dataflowAPI/rose/util/StringUtility.C +++ b/dataflowAPI/rose/util/StringUtility.C @@ -44,10 +44,10 @@ #include "StringUtility.h" -#include +#include // DQ (8/31/2009): This now compiles properly (at least for analysis, it might still fail for the code generation). // #ifndef USE_ROSE -#include +#include // #endif // DQ (9/29/2006): This is required for 64-bit g++ 3.4.4 compiler. @@ -369,7 +369,7 @@ StringUtility:: tokenize ( std::string X, char delim ) { // DQ (8/31/2009): This now compiles properly (at least for analysis, it might still fail for the code generation). // #ifdef USE_ROSE #if 0 -// Liao, 2/11/2009, Alternative to boost::lexical_cast, +// Liao, 2/11/2009, Alternative to dyncompat::lexical_cast, // since ROSE has problem in compiling it. Bug 313 // https://outreach.scidac.gov/tracker/index.php?func=detail&aid=313&group_id=24&atid=185 template @@ -386,7 +386,7 @@ StringUtility::numberToString ( long long x ) { // DQ (8/31/2009): This now compiles properly (at least for analysis, it might still fail for the code generation). // #ifndef USE_ROSE - return boost::lexical_cast(x); + return dyncompat::lexical_cast(x); // #else // return numToString(x); //#endif @@ -397,7 +397,7 @@ StringUtility::numberToString ( unsigned long long x ) { // DQ (8/31/2009): This now compiles properly (at least for analysis, it might still fail for the code generation). // #ifndef USE_ROSE - return boost::lexical_cast(x); + return dyncompat::lexical_cast(x); // #else // return numToString(x); // #endif @@ -408,7 +408,7 @@ StringUtility::numberToString ( long x ) { // DQ (8/31/2009): This now compiles properly (at least for analysis, it might still fail for the code generation). // #ifndef USE_ROSE - return boost::lexical_cast(x); + return dyncompat::lexical_cast(x); // #else // return numToString(x); // #endif @@ -419,7 +419,7 @@ StringUtility::numberToString ( unsigned long x ) { // DQ (8/31/2009): This now compiles properly (at least for analysis, it might still fail for the code generation). // #ifndef USE_ROSE - return boost::lexical_cast(x); + return dyncompat::lexical_cast(x); // #else // return numToString(x); // #endif @@ -430,7 +430,7 @@ StringUtility::numberToString ( int x ) { // DQ (8/31/2009): This now compiles properly (at least for analysis, it might still fail for the code generation). // #ifndef USE_ROSE - return boost::lexical_cast(x); + return dyncompat::lexical_cast(x); // #else // return numToString(x); // #endif @@ -441,7 +441,7 @@ StringUtility::numberToString ( unsigned int x ) { // DQ (8/31/2009): This now compiles properly (at least for analysis, it might still fail for the code generation). // #ifndef USE_ROSE - return boost::lexical_cast(x); + return dyncompat::lexical_cast(x); // #else // return numToString(x); // #endif @@ -492,17 +492,17 @@ StringUtility::numberToString ( double x ) string StringUtility::numberToString ( __int128 x ) { - // DQ (2/22/2014): I don't think that the boost::lexical_cast can support __int128 yet. + // DQ (2/22/2014): I don't think that the dyncompat::lexical_cast can support __int128 yet. long long temp_x = (long long) x; - return boost::lexical_cast(temp_x); + return dyncompat::lexical_cast(temp_x); } string StringUtility::numberToString ( unsigned __int128 x ) { - // DQ (2/22/2014): I don't think that the boost::lexical_cast can support __int128 yet. + // DQ (2/22/2014): I don't think that the dyncompat::lexical_cast can support __int128 yet. unsigned long long temp_x = (unsigned long long) x; - return boost::lexical_cast(temp_x); + return dyncompat::lexical_cast(temp_x); } #endif #endif @@ -511,7 +511,7 @@ StringUtility::numberToString ( unsigned __int128 x ) std::string StringUtility::cEscape(const std::string &s) { std::string result; - BOOST_FOREACH (char ch, s) { + DYN_FOREACH (char ch, s) { switch (ch) { case '\a': result += "\\a"; diff --git a/dataflowAPI/rose/util/StringUtility.h b/dataflowAPI/rose/util/StringUtility.h index 23e81ddd57..529009dc2e 100644 --- a/dataflowAPI/rose/util/StringUtility.h +++ b/dataflowAPI/rose/util/StringUtility.h @@ -2,6 +2,8 @@ #define ROSE_StringUtility_H //#include "commandline_processing.h" +#include +#include #include #include #include @@ -12,17 +14,13 @@ #include "../rose.h" -#if ROSE_MICROSOFT_OS -// This is the boost solution for lack of support for stdint.h (e.g. types such as "uint64_t") -#include "external/stdint-win.h" -#endif /** Functions for operating on strings. * * This name space provides functions for operating on strings. * * It also provides some unrelated functions: functions for operating on file names (see also @ref rose::FileSystem and - * boost::filesystem for better implementations), and functions for performing file I/O. These unrelated functions should + * std::filesystem for better implementations), and functions for performing file I/O. These unrelated functions should * eventually move to other name spaces. */ namespace StringUtility { @@ -132,7 +130,7 @@ namespace StringUtility { /** Convert an integer to a string. * - * These functions are wrappers around boost::lexical_cast. + * These functions are wrappers around dyncompat::lexical_cast. * * @{ */ std::string numberToString(long long); @@ -569,8 +567,8 @@ namespace StringUtility { //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// // This part of the StringUtility API deals with file names and should be moved to some other name space. In particular, it // provides no definitions for "path", "filename", "extension", etc. and many of these functions won't work properly on a -// non-POSIX system. Therefore, consider using rose::FileSystem, which is mostly a thin wrapper around boost::filesystem. The -// boost::filesystem documentation has good definitions for what the various terms should mean and works on non-POSIX file +// non-POSIX system. Therefore, consider using rose::FileSystem, which is mostly a thin wrapper around std::filesystem. The +// std::filesystem documentation has good definitions for what the various terms should mean and works on non-POSIX file // systems. //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// @@ -612,7 +610,7 @@ namespace StringUtility { * * Removes the "path" part of a "filename" (if there is one) and returns just the file name. * - * Terms are loosely defined and not likely to work for non-POSIX systems; consider using boost::filesystem instead. */ + * Terms are loosely defined and not likely to work for non-POSIX systems; consider using std::filesystem instead. */ std::string stripPathFromFileName(const std::string &fileNameWithPath); /** Returns all but the last component of a path in a filesystem. @@ -621,18 +619,18 @@ namespace StringUtility { * Make it safe to input a filename without a path name (return the filename). * * Terms are loosely defined and this function possibly doesn't work for non-POSIX file systems; consider using - * boost::filesystem instead. */ + * std::filesystem instead. */ std::string getPathFromFileName(const std::string &fileNameWithPath); /** Get the file name without the ".suffix". * * Terms are loosely defined and it's not clear what happens for inputs like ".", ".foo", "..", ".foo.bar", "/.", - * etc. Consider using boost::filesystem instead. */ + * etc. Consider using std::filesystem instead. */ std::string stripFileSuffixFromFileName(const std::string &fileNameWithSuffix); /** Get the absolute path from the relative path. * - * Terms are loosely defined and this function is not likely to work on non-POSIX systems. Consider using boost::filesystem + * Terms are loosely defined and this function is not likely to work on non-POSIX systems. Consider using std::filesystem * instead. */ std::string getAbsolutePathFromRelativePath(const std::string &relativePath, bool printErrorIfAny = false); @@ -642,7 +640,7 @@ namespace StringUtility { * returns the original fileName. * * Terms are loosely defined and this function is not likely to work correctly in some situations, such as when the "." is not - * in the last component of the file name. Consider using boost::filesystem instead. */ + * in the last component of the file name. Consider using std::filesystem instead. */ std::string fileNameSuffix(const std::string &fileName); /** Find file names non-recursively. @@ -651,7 +649,7 @@ namespace StringUtility { * substring of their name. Note that @p patternString is not a glob or regular expression. The return value strings are * formed by concatenating the @p pathString and the file name with an intervening slash. * - * This function does not work for non-POSIX systems. Consider using boost::filesystem instead, which has a directory iterator + * This function does not work for non-POSIX systems. Consider using std::filesystem instead, which has a directory iterator * that works for non-POSIX systems also. */ std::list findfile(std::string patternString, std::string pathString); diff --git a/dataflowAPI/rose/util/Synchronization.C b/dataflowAPI/rose/util/Synchronization.C index 8284604c49..babe755317 100644 --- a/dataflowAPI/rose/util/Synchronization.C +++ b/dataflowAPI/rose/util/Synchronization.C @@ -7,18 +7,11 @@ #include "Synchronization.h" -#include -#if BOOST_VERSION >= 104700 - #include - #define SAWYER_PRN_GENERATOR boost::random::mt11213b - #define SAWYER_UNIFORM_SIZE_T boost::random::uniform_smallint -#else - // Boost 1.45 and 1.46 say that mt11213b is only 44% as fast as rand48. Also, these things were not part of the - // boost::random namespace in those versions. - #include // 64% as fast as mersenne_twister according to boost 1.59 - #define SAWYER_PRN_GENERATOR boost::rand48 - #define SAWYER_UNIFORM_SIZE_T boost::uniform_smallint -#endif +#include +#include + +#define SAWYER_PRN_GENERATOR std::mt19937 +#define SAWYER_UNIFORM_SIZE_T std::uniform_int_distribution namespace Sawyer { diff --git a/dataflowAPI/rose/util/Synchronization.h b/dataflowAPI/rose/util/Synchronization.h index a472d55f2f..a70c534338 100644 --- a/dataflowAPI/rose/util/Synchronization.h +++ b/dataflowAPI/rose/util/Synchronization.h @@ -9,25 +9,27 @@ #define Sawyer_Synchronization_H #include "Sawyer.h" +#include +#include #if SAWYER_MULTI_THREADED // It appears as though a certain version of GNU libc interacts badly with C++03 GCC and LLVM compilers. Some system header // file defines _XOPEN_UNIX as "1" and __UINTPTR_TYPE__ as "unsigned long int" but doesn't provide a definition for - // "uintptr_t". This triggers a compilation error in for boost-1.54 because it assumes that + // "uintptr_t". This triggers a compilation error in for the 1.54 compatibility model because it assumes that // "uintptr_t" is available based on the preprocessor macros and the included files. These errors occur (at a minimum) on // Debian 8.2 and 8.3 using C++03 mode of gcc-4.8.4, gcc-4.9.2, or llvm-3.5. - #include - #if __cplusplus < 201103L && BOOST_VERSION == 105400 - #include // must be included before + #include + #if __cplusplus < 201103L && DYNCOMPAT_VERSION == 105400 + #include // must be included before #endif - #include - #include - #include - #include - #include - #include - #include + #include + #include + #include + #include + #include + #include + #include #endif namespace Sawyer { @@ -79,7 +81,7 @@ class LockGuard2 { public: LockGuard2(Mutex &m1, Mutex &m2): m1_(m1), m2_(m2) { #if SAWYER_MULTI_THREADED - boost::lock(m1, m2); + dyncompat::lock(m1, m2); #endif } ~LockGuard2() { @@ -97,13 +99,13 @@ template<> struct SynchronizationTraits { #if SAWYER_MULTI_THREADED enum { SUPPORTED = 1 }; - typedef boost::mutex Mutex; - typedef boost::recursive_mutex RecursiveMutex; - typedef boost::lock_guard LockGuard; - typedef boost::unique_lock UniqueLock; - typedef boost::lock_guard RecursiveLockGuard; - typedef boost::condition_variable_any ConditionVariable; - typedef boost::barrier Barrier; + typedef dyncompat::mutex Mutex; + typedef dyncompat::recursive_mutex RecursiveMutex; + typedef dyncompat::lock_guard LockGuard; + typedef dyncompat::unique_lock UniqueLock; + typedef dyncompat::lock_guard RecursiveLockGuard; + typedef dyncompat::condition_variable_any ConditionVariable; + typedef dyncompat::barrier Barrier; #else enum { SUPPORTED = 0 }; typedef NullMutex Mutex; diff --git a/dataflowAPI/rose/x86InstructionSemantics.h b/dataflowAPI/rose/x86InstructionSemantics.h index 40cd8d5817..11fa4e2cc9 100644 --- a/dataflowAPI/rose/x86InstructionSemantics.h +++ b/dataflowAPI/rose/x86InstructionSemantics.h @@ -3,6 +3,8 @@ //#include "rose.h" #include "semanticsModule.h" +#include +#include #include #include #include @@ -39,8 +41,8 @@ struct X86InstructionSemantics { Policy& policy; - X86InstructionSemantics(Policy& policy) - : policy(policy) + X86InstructionSemantics(Policy& policy_) + : policy(policy_) {} virtual ~X86InstructionSemantics() {} @@ -1350,7 +1352,6 @@ struct X86InstructionSemantics { case 4: { Word(32) op1 = read32(operands[0]); Word(32) op2 = read32(operands[1]); - Word(5) shiftCount = extract<0, 5>(read8(operands[2])); Word(32) output1 = policy.shiftLeft(op1, shiftCount); Word(32) output2 = policy.ite(policy.equalToZero(shiftCount), number<32>(0), diff --git a/dataflowAPI/rose/x86_64InstructionSemantics.h b/dataflowAPI/rose/x86_64InstructionSemantics.h index 50479d7aaa..99723405a6 100644 --- a/dataflowAPI/rose/x86_64InstructionSemantics.h +++ b/dataflowAPI/rose/x86_64InstructionSemantics.h @@ -2,6 +2,9 @@ #define ROSE_X86_64INSTRUCTIONSEMANTICS_H //#include "rose.h" +#include +#include +#include #include "semanticsModule.h" #include #include @@ -49,8 +52,8 @@ struct X86_64InstructionSemantics { Policy& policy; - X86_64InstructionSemantics(Policy& policy) - : policy(policy) + X86_64InstructionSemantics(Policy& policy_) + : policy(policy_) {} virtual ~X86_64InstructionSemantics() {} @@ -193,6 +196,7 @@ struct X86_64InstructionSemantics { default: ROSE_ASSERT(!"Bad position in register"); } } + break; default: { fprintf(stderr, "Bad register class %s\n", regclassToString(rre->get_register_class())); throw rose::BinaryAnalysis::InstructionSemantics2::BaseSemantics::Exception("", NULL);; @@ -302,6 +306,7 @@ struct X86_64InstructionSemantics { ROSE_ASSERT(!"bad position in register"); } } + break; case x86_regclass_segment: { ROSE_ASSERT(rre->get_position_in_register() == x86_regpos_dword || rre->get_position_in_register() == x86_regpos_all); @@ -366,6 +371,7 @@ struct X86_64InstructionSemantics { ROSE_ASSERT(!"bad position in register"); } } + break; case x86_regclass_segment: { ROSE_ASSERT(rre->get_position_in_register() == x86_regpos_dword || rre->get_position_in_register() == x86_regpos_all); diff --git a/dataflowAPI/src/ABI.C b/dataflowAPI/src/ABI.C index 11ebe80528..c5398daf5b 100644 --- a/dataflowAPI/src/ABI.C +++ b/dataflowAPI/src/ABI.C @@ -28,10 +28,25 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include "dataflowAPI/h/ABI.h" #include "dataflowAPI/src/RegisterMap.h" #include +#if defined(arch_x86) || defined(arch_x86_64) +# include "registers/x86_regs.h" +# include "registers/x86_64_regs.h" +#endif + +#if defined(arch_power) +# include "registers/ppc32_regs.h" +# include "registers/ppc64_regs.h" +#endif + +#if defined(arch_aarch64) +# include "registers/aarch64_regs.h" +#endif + using namespace Dyninst; using namespace DataflowAPI; @@ -91,8 +106,12 @@ ABI* ABI::getABI(int addr_width){ globalABI64_->index = &machRegIndex_aarch64(); #endif +// We _only_ support instrumenting 32-bit binaries on 64-bit systems +#if !defined arch_64bit || defined cap_32_64 initialize32(); -#if defined(cap_32_64) +#endif + +#ifdef arch_64bit initialize64(); #endif } @@ -553,10 +572,6 @@ void ABI::initialize64(){ //#warning "This is not verified!" #if defined(arch_aarch64) -void ABI::initialize32(){ - return; -} - void ABI::initialize64(){ RegisterMap aarch64Map = machRegIndex_aarch64(); int sz = aarch64Map.size(); diff --git a/dataflowAPI/src/Absloc.C b/dataflowAPI/src/Absloc.C index 838d45e4b5..f973a8c986 100644 --- a/dataflowAPI/src/Absloc.C +++ b/dataflowAPI/src/Absloc.C @@ -28,6 +28,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include "Absloc.h" #include diff --git a/dataflowAPI/src/AbslocInterface.C b/dataflowAPI/src/AbslocInterface.C index 8dfa1c3ebd..1aea975746 100644 --- a/dataflowAPI/src/AbslocInterface.C +++ b/dataflowAPI/src/AbslocInterface.C @@ -29,12 +29,14 @@ */ +#include +#include #include "Absloc.h" #include "AbslocInterface.h" +#include "Register.h" // Pile of InstructionAPI includes #include "Expression.h" -#include "Register.h" #include "Result.h" #include "Dereference.h" #include "BinaryFunction.h" @@ -44,12 +46,13 @@ #include "common/src/singleton_object_pool.h" #include "parseAPI/h/CFG.h" #include "parseAPI/h/CodeObject.h" +#include "registers/aarch64_regs.h" using namespace Dyninst; using namespace Dyninst::InstructionAPI; extern int df_debug_stackanalysis; -template class std::vector >; +template class std::vector >; void AbsRegionConverter::convertAll(InstructionAPI::Expression::Ptr expr, Address addr, @@ -58,7 +61,7 @@ void AbsRegionConverter::convertAll(InstructionAPI::Expression::Ptr expr, std::vector ®ions) { // If we're a memory dereference, then convert us and all // used registers. - if (boost::dynamic_pointer_cast(expr)) { + if (dyncompat::dynamic_pointer_cast(expr)) { std::vector tmp; // Strip dereference... expr->getChildren(tmp); @@ -74,7 +77,7 @@ void AbsRegionConverter::convertAll(InstructionAPI::Expression::Ptr expr, expr->getUses(used); for (std::set::const_iterator j = used.begin(); j != used.end(); ++j) { - regions.push_back(convert(boost::dynamic_pointer_cast(*j))); + regions.push_back(convert(dyncompat::dynamic_pointer_cast(*j))); } } @@ -428,10 +431,8 @@ bool AbsRegionConverter::getCurrentStackHeight(ParseAPI::Function *func, StackAnalysis::Height heightSA = sA.findSP(block, addr); - // Ensure that analysis has been performed. - assert(!heightSA.isTop()); - - if (heightSA.isBottom()) { + // return false if height unknown + if (heightSA.isBottom() || heightSA.isTop()) { return false; } @@ -449,10 +450,8 @@ bool AbsRegionConverter::getCurrentFrameHeight(ParseAPI::Function *func, StackAnalysis::Height heightSA = sA.find(block, addr, MachRegister::getFramePointer(func->isrc()->getArch()));; - // Ensure that analysis has been performed. - assert(!heightSA.isTop()); - - if (heightSA.isBottom()) { + // return false if height unknown + if (heightSA.isBottom() || heightSA.isTop()) { return false; } @@ -511,222 +510,199 @@ void AssignmentConverter::convert(const Instruction &I, // Non-PC handling section switch(I.getOperation().getID()) { - case amdgpu_op_s_getpc_b64: { - // SGPR_PAIR[0] = PC & 0xffffffff - // SGPR_PARI[1] = PC >> 32 - // - std::vector operands; - I.getOperands(operands); - assert(operands.size() == 1); - RegisterAST::Ptr sgpr_pair = boost::dynamic_pointer_cast(operands[0].getValue()); - unsigned int offset = sgpr_pair->getID() - amdgpu_vega::sgpr_vec2_0 ; - AbsRegion lowpc_dst = AbsRegion(MachRegister(amdgpu_vega::sgpr0+offset)) ; - AbsRegion highpc_dst = AbsRegion(MachRegister(amdgpu_vega::sgpr0+offset+1)) ; - - //AbsRegion pc = AbsRegion(Absloc::makePC(func->isrc()->getArch())); - AbsRegion pc = AbsRegion(Absloc(addr)); - - Assignment::Ptr lowpcA = Assignment::makeAssignment(I, - addr, - func, - block, - lowpc_dst); - Assignment::Ptr highpcA = Assignment::makeAssignment(I, - addr, - func, - block, - highpc_dst); - //lowpcA->addInput(pc); // treating pc as constant - //highpcA->addInput(pc); //treating pc as constant - - assignments.push_back(lowpcA); - assignments.push_back(highpcA); - // The slicing stops as long as we find at least one of the above assgignment - - // TODO: - // DST_SGPR_PAIR = PC+4 - break; - } - case amdgpu_op_s_setpc_b64: { - // TODO: - // PC = SRC_SGPR_PAIR - AbsRegion pc = AbsRegion(Absloc::makePC(func->isrc()->getArch())); - Assignment::Ptr pcA = Assignment::makeAssignment(I, - addr, - func, - block, - pc); - - std::vector operands; - I.getOperands(operands); - // SETPC_B64 should only have one operand, which is the SGPR_PAIR that stores the new PC VALUE - // Since we don't want to introduce extra Class at the instructionAPI level, we need to break it down ourserlves here - // So we don't need to deal with reading the value in rose DispatcherAmdgpuVega - // Depends on the situation, we might also need to differentaite betwwen vega and rdna, but for now we focus on vega - assert(operands.size() == 1); - RegisterAST::Ptr sgpr_pair = boost::dynamic_pointer_cast(operands[0].getValue()); - unsigned int offset = sgpr_pair->getID() - amdgpu_vega::sgpr_vec2_0 ; - AbsRegion oper0 = AbsRegion(MachRegister(amdgpu_vega::sgpr0+offset)) ; - AbsRegion oper1 = AbsRegion(MachRegister(amdgpu_vega::sgpr0+offset+1)) ; - pcA->addInput(oper0); - pcA->addInput(oper1); - - assignments.push_back(pcA); - break; - } - case amdgpu_op_s_swappc_b64: { - // TODO:DST_SGPR_PAIR= PC + 4 - // PC = SRC_SGPR_PAIR - - //PC = OPR[0] - //OPR[1] = OLD_PC + 4 - // => - //PC = OPR[0:1] - //OPR[2:3] = OLD_PC + 4 - // - std::vector operands; - I.getOperands(operands); - assert(operands.size() == 2); - - RegisterAST::Ptr store_sgpr_pair = boost::dynamic_pointer_cast(operands[1].getValue()); - unsigned int store_offset = store_sgpr_pair->getID() - amdgpu_vega::sgpr_vec2_0 ; - AbsRegion store_oper0 = AbsRegion(MachRegister(amdgpu_vega::sgpr0+store_offset)) ; - AbsRegion store_oper1 = AbsRegion(MachRegister(amdgpu_vega::sgpr0+store_offset+1)) ; - - - AbsRegion pc = AbsRegion(Absloc::makePC(func->isrc()->getArch())); - - Assignment::Ptr store_pc_lowA = Assignment::makeAssignment(I, - addr, - func, - block, - store_oper0); - store_pc_lowA->addInput(pc); - - - Assignment::Ptr store_pc_highA = Assignment::makeAssignment(I, - addr, - func, - block, - store_oper1); - store_pc_highA->addInput(pc); - - Assignment::Ptr pcA = Assignment::makeAssignment(I, - addr, - func, - block, - pc); - - RegisterAST::Ptr target_sgpr_pair = boost::dynamic_pointer_cast(operands[0].getValue()); - unsigned int target_offset = target_sgpr_pair->getID() - amdgpu_vega::sgpr_vec2_0 ; - AbsRegion target_oper0 = AbsRegion(MachRegister(amdgpu_vega::sgpr0+target_offset)) ; - AbsRegion target_oper1 = AbsRegion(MachRegister(amdgpu_vega::sgpr0+target_offset+1)) ; - - pcA->addInput(target_oper0); - pcA->addInput(target_oper1); - - assignments.push_back(pcA); - // while the below 2 assignments are also there, we comment it out for now TODO: - //assignments.push_back(store_pc_lowA); - //assignments.push_back(store_pc_highA); - - - break; - } - case amdgpu_op_s_add_u32: { - std::vector operands; - I.getOperands(operands); - - - assert(operands.size() == 3 && "add_u32 needs 3 operands"); - - RegisterAST::Ptr dst_sgpr = boost::dynamic_pointer_cast(operands[0].getValue()); - - std::vector regions; - - aConverter.convertAll(operands[0].getValue(), addr, func, block, regions); - AbsRegion dst1 = regions[0]; - regions.clear(); - aConverter.convertAll(operands[1].getValue(), addr, func, block, regions); - AbsRegion src1 = regions[0]; - regions.clear(); - aConverter.convertAll(operands[2].getValue(), addr, func, block, regions); - AbsRegion src0 = regions[0]; - regions.clear(); - - - - AbsRegion scc = AbsRegion(MachRegister(amdgpu_vega::scc)) ; - Assignment::Ptr scc_assign = Assignment::makeAssignment(I, - addr, - func, - block, - scc); + case amdgpu_gfx908_op_S_GETPC_B64: + case amdgpu_gfx90a_op_S_GETPC_B64: + case amdgpu_gfx940_op_S_GETPC_B64: { + // SGPR_PAIR[0] = PC & 0xffffffff + // SGPR_PARI[1] = PC >> 32 + // + std::vector operands; + I.getOperands(operands); + assert(operands.size() == 3); + RegisterAST::Ptr lowpc_reg = dyncompat::dynamic_pointer_cast(operands[0].getValue()); + RegisterAST::Ptr highpc_reg = dyncompat::dynamic_pointer_cast(operands[1].getValue()); + AbsRegion lowpc_dst = AbsRegion(lowpc_reg->getID()) ; + AbsRegion highpc_dst = AbsRegion(highpc_reg->getID()) ; + + //AbsRegion pc = AbsRegion(Absloc::makePC(func->isrc()->getArch())); + AbsRegion pc = AbsRegion(Absloc(addr)); + + Assignment::Ptr lowpcA = Assignment::makeAssignment(I, + addr, + func, + block, + lowpc_dst); + Assignment::Ptr highpcA = Assignment::makeAssignment(I, + addr, + func, + block, + highpc_dst); + + assignments.push_back(lowpcA); + assignments.push_back(highpcA); + + break; + } + case amdgpu_gfx908_op_S_SETPC_B64: + case amdgpu_gfx90a_op_S_SETPC_B64: + case amdgpu_gfx940_op_S_SETPC_B64: { + // TODO: + // PC = SRC_SGPR_PAIR + AbsRegion pc = AbsRegion(Absloc::makePC(func->isrc()->getArch())); + Assignment::Ptr pcA = Assignment::makeAssignment(I, + addr, + func, + block, + pc); + + std::vector operands; + I.getOperands(operands); + assert(operands.size() == 3); + RegisterAST::Ptr lowpc_reg = dyncompat::dynamic_pointer_cast(operands[0].getValue()); + RegisterAST::Ptr highpc_reg = dyncompat::dynamic_pointer_cast(operands[1].getValue()); + AbsRegion lowpc_src = AbsRegion(lowpc_reg->getID()) ; + AbsRegion highpc_src = AbsRegion(highpc_reg->getID()) ; + + pcA->addInput(lowpc_src); + pcA->addInput(highpc_src); + assignments.push_back(pcA); + break; + } + case amdgpu_gfx908_op_S_SWAPPC_B64: + case amdgpu_gfx90a_op_S_SWAPPC_B64: + case amdgpu_gfx940_op_S_SWAPPC_B64: { + std::vector operands; + I.getOperands(operands); + assert(operands.size() == 6); + + RegisterAST::Ptr new_pc_value_low = dyncompat::dynamic_pointer_cast(operands[2].getValue()); + RegisterAST::Ptr new_pc_value_high = dyncompat::dynamic_pointer_cast(operands[3].getValue()); + AbsRegion new_pc_reg_low = AbsRegion(new_pc_value_low->getID()) ; + AbsRegion new_pc_reg_high = AbsRegion(new_pc_value_high->getID()) ; + AbsRegion pc = AbsRegion(Absloc::makePC(func->isrc()->getArch())); + + Assignment::Ptr pcA = Assignment::makeAssignment(I, + addr, + func, + block, + pc); + + pcA->addInput(new_pc_reg_low); + pcA->addInput(new_pc_reg_high); - - Assignment::Ptr add_assign = Assignment::makeAssignment(I, - addr, - func, - block, - dst1); +/* + RegisterAST::Ptr backup_pc_low = dyncompat::dynamic_pointer_cast(operands[0].getValue()); + RegisterAST::Ptr backup_pc_high = dyncompat::dynamic_pointer_cast(operands[1].getValue()); + AbsRegion backup_pc_low_reg = AbsRegion(backup_pc_low->getID()) ; + AbsRegion backup_pc_high_reg = AbsRegion(backup_pc_high->getID()) ; + + Assignment::Ptr backup_pc_lowA = Assignment::makeAssignment(I, + addr, + func, + block, + backup_pc_low_reg); + backup_pc_lowA->addInput(pc); + + Assignment::Ptr backup_pc_highA = Assignment::makeAssignment(I, + addr, + func, + block, + backup_pc_high_reg); + backup_pc_highA->addInput(pc); +*/ + + assignments.push_back(pcA); + //assignments.push_back(backup_pc_lowA); + //assignments.push_back(backup_pc_highA); + + + break; + } + case amdgpu_gfx908_op_S_ADD_U32: + case amdgpu_gfx90a_op_S_ADD_U32: + case amdgpu_gfx940_op_S_ADD_U32: { + std::vector operands; + I.getOperands(operands); - add_assign->addInput(src1); - add_assign->addInput(src0); - - scc_assign->addInput(src1); - scc_assign->addInput(src0); + assert(operands.size() == 4); - assignments.push_back(add_assign); - assignments.push_back(scc_assign); + RegisterAST::Ptr dst_sgpr = dyncompat::dynamic_pointer_cast(operands[0].getValue()); + std::vector regions; - // TODO: - // D.U = S0.u +S1.U - // SCC= (S0.u + S1.U >= 0x100000000ULL ? 1 : 0 ) - break; - } + aConverter.convertAll(operands[0].getValue(), addr, func, block, regions); + AbsRegion dst1 = regions[0]; + regions.clear(); + aConverter.convertAll(operands[1].getValue(), addr, func, block, regions); + AbsRegion src1 = regions[0]; + regions.clear(); + aConverter.convertAll(operands[2].getValue(), addr, func, block, regions); + AbsRegion src0 = regions[0]; + regions.clear(); + aConverter.convertAll(operands[3].getValue(), addr, func, block, regions); + AbsRegion scc = regions[0]; + regions.clear(); - case amdgpu_op_s_addc_u32: { - std::vector operands; - I.getOperands(operands); + Assignment::Ptr scc_assign = Assignment::makeAssignment(I, + addr, + func, + block, + scc); - assert(operands.size() == 3 && "add_u32 needs 3 operands"); + Assignment::Ptr add_assign = Assignment::makeAssignment(I, + addr, + func, + block, + dst1); - RegisterAST::Ptr dst_sgpr = boost::dynamic_pointer_cast(operands[0].getValue()); + add_assign->addInput(src1); + add_assign->addInput(src0); - std::vector regions; - - aConverter.convertAll(operands[0].getValue(), addr, func, block, regions); - AbsRegion dst1 = regions[0]; - regions.clear(); - aConverter.convertAll(operands[1].getValue(), addr, func, block, regions); - AbsRegion src1 = regions[0]; - regions.clear(); - aConverter.convertAll(operands[2].getValue(), addr, func, block, regions); - AbsRegion src0 = regions[0]; - regions.clear(); + scc_assign->addInput(src1); + scc_assign->addInput(src0); - AbsRegion scc = AbsRegion(MachRegister(amdgpu_vega::scc)) ; + assignments.push_back(add_assign); + assignments.push_back(scc_assign); + break; + } - - Assignment::Ptr add_assign = Assignment::makeAssignment(I, - addr, - func, - block, - dst1); - add_assign->addInput(src1); - add_assign->addInput(src0); - add_assign->addInput(scc); - assignments.push_back(add_assign); - - // TODO: - // D.U = S0.U +S1. U - SCC - // SCC= (S0.U +S1.U +SCC>= 0x100000000ULL? 1 : 0) - break; - } + case amdgpu_gfx908_op_S_ADDC_U32: + case amdgpu_gfx90a_op_S_ADDC_U32: + case amdgpu_gfx940_op_S_ADDC_U32: { + std::vector operands; + I.getOperands(operands); + assert(operands.size() == 5); + + RegisterAST::Ptr dst_sgpr = dyncompat::dynamic_pointer_cast(operands[0].getValue()); + std::vector regions; + + aConverter.convertAll(operands[0].getValue(), addr, func, block, regions); + AbsRegion dst1 = regions[0]; + regions.clear(); + aConverter.convertAll(operands[1].getValue(), addr, func, block, regions); + AbsRegion src1 = regions[0]; + regions.clear(); + aConverter.convertAll(operands[2].getValue(), addr, func, block, regions); + AbsRegion src0 = regions[0]; + regions.clear(); + aConverter.convertAll(operands[3].getValue(), addr, func, block, regions); + AbsRegion scc = regions[0]; + regions.clear(); + + Assignment::Ptr add_assign = Assignment::makeAssignment(I, + addr, + func, + block, + dst1); + add_assign->addInput(src1); + add_assign->addInput(src0); + add_assign->addInput(scc); + assignments.push_back(add_assign); + break; + } case e_push: { // SP = SP - 4 diff --git a/dataflowAPI/src/ExpressionConversionVisitor.C b/dataflowAPI/src/ExpressionConversionVisitor.C index 7fcdce61de..6ac8a08448 100644 --- a/dataflowAPI/src/ExpressionConversionVisitor.C +++ b/dataflowAPI/src/ExpressionConversionVisitor.C @@ -29,13 +29,14 @@ */ #include "ExpressionConversionVisitor.h" -#include "Register.h" #include "Immediate.h" #include "BinaryFunction.h" #include "Dereference.h" +#include "compiler_annotations.h" #include +#include "Register.h" #include "../rose/SgAsmExpression.h" using namespace Dyninst; @@ -53,11 +54,12 @@ void ExpressionConversionVisitor::visit(InstructionAPI::Immediate *immed) { // TODO rose doesn't handle large values (XMM?) // build different kind of rose value object based on type - if(arch == Arch_aarch64 || arch == Arch_ppc32 || arch == Arch_ppc64 || arch == Arch_amdgpu_vega) { + if(arch == Arch_aarch64 || arch == Arch_ppc32 || arch == Arch_ppc64 || arch == Arch_amdgpu_gfx908 || arch == Arch_amdgpu_gfx90a || arch == Arch_amdgpu_gfx940) { bool isSigned = false; switch (value.type) { case s8: isSigned = true; + DYNINST_FALLTHROUGH; case u8: roseExpression = new SgAsmIntegerValueExpression(value.val.u8val, new SgAsmIntegerType(ByteOrder::ORDER_UNSPECIFIED, 8, @@ -65,6 +67,7 @@ void ExpressionConversionVisitor::visit(InstructionAPI::Immediate *immed) { break; case s16: isSigned = true; + DYNINST_FALLTHROUGH; case u16: roseExpression = new SgAsmIntegerValueExpression(value.val.u16val, new SgAsmIntegerType(ByteOrder::ORDER_LSB, 16, @@ -72,6 +75,7 @@ void ExpressionConversionVisitor::visit(InstructionAPI::Immediate *immed) { break; case s32: isSigned = true; + DYNINST_FALLTHROUGH; case u32: roseExpression = new SgAsmIntegerValueExpression(value.val.u32val, new SgAsmIntegerType(ByteOrder::ORDER_LSB, 32, @@ -79,6 +83,7 @@ void ExpressionConversionVisitor::visit(InstructionAPI::Immediate *immed) { break; case s48: isSigned = true; + DYNINST_FALLTHROUGH; case u48: roseExpression = new SgAsmIntegerValueExpression(value.val.u32val, new SgAsmIntegerType(ByteOrder::ORDER_LSB, 32, @@ -86,6 +91,7 @@ void ExpressionConversionVisitor::visit(InstructionAPI::Immediate *immed) { break; case s64: isSigned = true; + DYNINST_FALLTHROUGH; case u64: roseExpression = new SgAsmIntegerValueExpression(value.val.u64val, new SgAsmIntegerType(ByteOrder::ORDER_LSB, 64, @@ -167,26 +173,30 @@ void ExpressionConversionVisitor::visit(Dereference *deref) { // TODO fix some mismatched types? // pick correct type - if(arch == Arch_aarch64 || arch == Arch_ppc32 || arch == Arch_ppc64 || arch == Arch_amdgpu_vega) { + if(arch == Arch_aarch64 || arch == Arch_ppc32 || arch == Arch_ppc64 || arch == Arch_amdgpu_gfx908 || arch == Arch_amdgpu_gfx90a || arch == Arch_amdgpu_gfx940) { bool isSigned = false; switch (deref->eval().type) { case s8: isSigned = true; + DYNINST_FALLTHROUGH; case u8: type = new SgAsmIntegerType(ByteOrder::ORDER_LSB, 8, isSigned); break; case s16: isSigned = true; + DYNINST_FALLTHROUGH; case u16: type = new SgAsmIntegerType(ByteOrder::ORDER_LSB, 16, isSigned); break; case s32: isSigned = true; + DYNINST_FALLTHROUGH; case u32: type = new SgAsmIntegerType(ByteOrder::ORDER_LSB, 32, isSigned); break; case s64: isSigned = true; + DYNINST_FALLTHROUGH; case u64: type = new SgAsmIntegerType(ByteOrder::ORDER_LSB, 64, isSigned); break; @@ -246,7 +256,7 @@ void ExpressionConversionVisitor::visit(Dereference *deref) { } SgAsmExpression *ExpressionConversionVisitor::archSpecificRegisterProc(InstructionAPI::RegisterAST *regast, - uint64_t addr, uint64_t size) { + uint64_t addr_, uint64_t size_) { MachRegister machReg = regast->getID(); @@ -254,71 +264,72 @@ SgAsmExpression *ExpressionConversionVisitor::archSpecificRegisterProc(Instructi switch (arch) { case Arch_x86: case Arch_x86_64: { - int regClass; + int regClass_; int regNum; int regPos; - MachRegister machReg = regast->getID(); if (machReg.isPC()) { // ideally this would be symbolic // When ip is read, the value read is not the address of the current instruction, // but the address of the next instruction. SgAsmExpression *constAddrExpr; if (arch == Arch_x86) - constAddrExpr = new SgAsmDoubleWordValueExpression(addr + size); + constAddrExpr = new SgAsmDoubleWordValueExpression(addr_ + size_); else - constAddrExpr = new SgAsmQuadWordValueExpression(addr + size); + constAddrExpr = new SgAsmQuadWordValueExpression(addr_ + size_); return constAddrExpr; } - machReg.getROSERegister(regClass, regNum, regPos); - if (regClass < 0) return NULL; - return new SgAsmx86RegisterReferenceExpression((X86RegisterClass) regClass, + machReg.getROSERegister(regClass_, regNum, regPos); + if (regClass_ < 0) return NULL; + return new SgAsmx86RegisterReferenceExpression((X86RegisterClass) regClass_, regNum, (X86PositionInRegister) regPos); } case Arch_ppc32: case Arch_ppc64: { - int regClass; + int regClass_; int regNum; int regPos; SgAsmDirectRegisterExpression *dre; - machReg.getROSERegister(regClass, regNum, regPos); - if (regClass < 0) return NULL; - if (regClass == powerpc_regclass_cr) { + machReg.getROSERegister(regClass_, regNum, regPos); + if (regClass_ < 0) return NULL; + if (regClass_ == powerpc_regclass_cr) { // ROSE treats CR as one register, so regNum is always 0. // CR0 to CR7 are 8 subfields within CR. // CR0 has register offset 0 // CR1 has register offset 4 - dre = new SgAsmDirectRegisterExpression(RegisterDescriptor(regClass, regNum, regPos * 4, 4)); + dre = new SgAsmDirectRegisterExpression(RegisterDescriptor(regClass_, regNum, regPos * 4, 4)); dre->set_type(new SgAsmIntegerType(ByteOrder::ORDER_LSB, 4, false)); } else { - dre = new SgAsmDirectRegisterExpression(RegisterDescriptor(regClass, regNum, regPos, machReg.size() * 8)); + dre = new SgAsmDirectRegisterExpression(RegisterDescriptor(regClass_, regNum, regPos, machReg.size() * 8)); dre->set_type(new SgAsmIntegerType(ByteOrder::ORDER_LSB, machReg.size() * 8, false)); } return dre; } case Arch_aarch64: { - int regClass; + int regClass_; int regNum; int regPos; - machReg.getROSERegister(regClass, regNum, regPos); - if (regClass < 0) return NULL; - SgAsmDirectRegisterExpression *dre = new SgAsmDirectRegisterExpression(RegisterDescriptor(regClass, regNum, regPos, machReg.size() * 8)); + machReg.getROSERegister(regClass_, regNum, regPos); + if (regClass_ < 0) return NULL; + SgAsmDirectRegisterExpression *dre = new SgAsmDirectRegisterExpression(RegisterDescriptor(regClass_, regNum, regPos, machReg.size() * 8)); dre->set_type(new SgAsmIntegerType(ByteOrder::ORDER_LSB, machReg.size() * 8, false)); return dre; } - case Arch_amdgpu_vega: { - int regClass; + case Arch_amdgpu_gfx908: + case Arch_amdgpu_gfx90a: + case Arch_amdgpu_gfx940: { + int regClass_; int regNum; int regPos; - machReg.getROSERegister(regClass, regNum, regPos); - if (regClass < 0) return NULL; - //std::cout << " after get rose register, regClass = " << regClass << " regNum = " << regNum << std::endl; + machReg.getROSERegister(regClass_, regNum, regPos); + if (regClass_ < 0) return NULL; + //std::cout << " after get rose register, regClass_ = " << regClass_ << " regNum = " << regNum << std::endl; // TODO : it is not clear how regsize adn such should be set, for now we just follow aarch64's implementation - SgAsmDirectRegisterExpression *dre = new SgAsmDirectRegisterExpression(RegisterDescriptor(regClass, regNum, regPos, machReg.size() * 8)); + SgAsmDirectRegisterExpression *dre = new SgAsmDirectRegisterExpression(RegisterDescriptor(regClass_, regNum, regPos, machReg.size() * 8)); dre->set_type(new SgAsmIntegerType(ByteOrder::ORDER_LSB, machReg.size() * 8, false)); return dre; } diff --git a/dataflowAPI/src/ExpressionConversionVisitor.h b/dataflowAPI/src/ExpressionConversionVisitor.h index 6c24b2dcce..f4f784cb65 100644 --- a/dataflowAPI/src/ExpressionConversionVisitor.h +++ b/dataflowAPI/src/ExpressionConversionVisitor.h @@ -27,13 +27,13 @@ * License along with this library; if not, write to the Free Software * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ -#pragma once #if !defined(_EXPRESSION_CONVERSION_VISITOR_H_) #define _EXPRESSION_CONVERSION_VISITOR_H_ -#include "dyn_regs.h" +#include "util.h" +#include "Architecture.h" class SgAsmx86Instruction; class SgAsmExpression; @@ -46,11 +46,7 @@ class SgAsmPowerpcRegisterReferenceExpression; #include "external/rose/powerpcInstructionEnum.h" #include "Visitor.h" -#if defined(_MSC_VER) -#include "external/stdint-win.h" -#else #include -#endif #include @@ -69,7 +65,7 @@ namespace Dyninst public: DATAFLOW_EXPORT ExpressionConversionVisitor(Architecture a, uint64_t ad, uint64_t s) : - roseExpression(NULL), arch(a), addr(ad), size(s) {}; + roseExpression(NULL), arch(a), addr(ad), size(s) {} DATAFLOW_EXPORT SgAsmExpression *getRoseExpression() { return roseExpression; } diff --git a/dataflowAPI/src/InstructionCache.C b/dataflowAPI/src/InstructionCache.C index 4b47c95ce7..f98fb3c157 100644 --- a/dataflowAPI/src/InstructionCache.C +++ b/dataflowAPI/src/InstructionCache.C @@ -28,6 +28,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include "InstructionCache.h" using namespace Dyninst; using namespace Dyninst::ParseAPI; diff --git a/dataflowAPI/src/RegisterMap.C b/dataflowAPI/src/RegisterMap.C index 90a192056b..ac4f1dee20 100644 --- a/dataflowAPI/src/RegisterMap.C +++ b/dataflowAPI/src/RegisterMap.C @@ -29,11 +29,7 @@ */ #include "dataflowAPI/src/RegisterMap.h" -#include -#include -#include - -using namespace boost::assign; +#include "dyn_regs.h" // We use the singleton approach, rather than static construction, to ensure the // register maps are created correctly. In at least one case (Ubuntu 12.04) they @@ -42,11 +38,6 @@ using namespace boost::assign; namespace Dyninst { namespace DataflowAPI { -#if !defined(NO_INITIALIZER_LIST_SUPPORT) && (!defined(os_windows) || _MSC_VER >= 1900) - // This doesn't fail on VS 2015, but may fail on other versions post 2010. - // This fails on VS2010; revisit when we move to VS2012. - // Also on gcc 4.3. - RegisterMap &machRegIndex_x86() { static dyn_tls RegisterMap* mrmap = NULL; if (mrmap == NULL) { @@ -103,30 +94,6 @@ RegisterMap &machRegIndex_x86() { {x86::zmm5, 48}, {x86::zmm6, 49}, {x86::zmm7, 50}, - {x86::zmm8, 51}, - {x86::zmm9, 52}, - {x86::zmm10, 53}, - {x86::zmm11, 54}, - {x86::zmm12, 55}, - {x86::zmm13, 56}, - {x86::zmm14, 57}, - {x86::zmm15, 58}, - {x86::zmm16, 59}, - {x86::zmm17, 60}, - {x86::zmm18, 61}, - {x86::zmm19, 62}, - {x86::zmm20, 63}, - {x86::zmm21, 64}, - {x86::zmm22, 65}, - {x86::zmm23, 66}, - {x86::zmm24, 67}, - {x86::zmm25, 68}, - {x86::zmm26, 69}, - {x86::zmm27, 70}, - {x86::zmm28, 71}, - {x86::zmm29, 72}, - {x86::zmm30, 73}, - {x86::zmm31, 74}, {x86::ymm0, 75}, {x86::ymm1, 76}, {x86::ymm2, 77}, @@ -135,30 +102,6 @@ RegisterMap &machRegIndex_x86() { {x86::ymm5, 80}, {x86::ymm6, 81}, {x86::ymm7, 82}, - {x86::ymm8, 83}, - {x86::ymm9, 84}, - {x86::ymm10, 85}, - {x86::ymm11, 86}, - {x86::ymm12, 87}, - {x86::ymm13, 88}, - {x86::ymm14, 89}, - {x86::ymm15, 90}, - {x86::ymm16, 91}, - {x86::ymm17, 92}, - {x86::ymm18, 93}, - {x86::ymm19, 94}, - {x86::ymm20, 95}, - {x86::ymm21, 96}, - {x86::ymm22, 97}, - {x86::ymm23, 98}, - {x86::ymm24, 99}, - {x86::ymm25, 100}, - {x86::ymm26, 101}, - {x86::ymm27, 102}, - {x86::ymm28, 103}, - {x86::ymm29, 104}, - {x86::ymm30, 105}, - {x86::ymm31, 106}, {x86::xmm0, 107}, {x86::xmm1, 108}, {x86::xmm2, 109}, @@ -167,30 +110,6 @@ RegisterMap &machRegIndex_x86() { {x86::xmm5, 112}, {x86::xmm6, 113}, {x86::xmm7, 114}, - {x86::xmm8, 115}, - {x86::xmm9, 116}, - {x86::xmm10, 117}, - {x86::xmm11, 118}, - {x86::xmm12, 119}, - {x86::xmm13, 120}, - {x86::xmm14, 121}, - {x86::xmm15, 122}, - {x86::xmm16, 123}, - {x86::xmm17, 124}, - {x86::xmm18, 125}, - {x86::xmm19, 126}, - {x86::xmm20, 127}, - {x86::xmm21, 128}, - {x86::xmm22, 129}, - {x86::xmm23, 130}, - {x86::xmm24, 131}, - {x86::xmm25, 132}, - {x86::xmm26, 133}, - {x86::xmm27, 134}, - {x86::xmm28, 135}, - {x86::xmm29, 136}, - {x86::xmm30, 137}, - {x86::xmm31, 138}, {x86::mm0, 139}, // mm0 to mm7 and st0 to st7 collapse to mm0 {x86::cr0, 140}, {x86::cr1, 141}, @@ -867,732 +786,5 @@ RegisterMap &machRegIndex_aarch64() { return *mrmap; } -#else - // This fails on VS 2015... but not VS 2010... -RegisterMap &machRegIndex_x86() { - static dyn_tls RegisterMap* mrmap = NULL; - if (mrmap == NULL) { - mrmap = new RegisterMap(); - *mrmap = map_list_of - (x86::eax, 0) - (x86::ecx, 1) - (x86::edx, 2) - (x86::ebx, 3) - (x86::esp, 4) - (x86::ebp, 5) - (x86::esi, 6) - (x86::edi, 7) - (x86::eip, 8) - (x86::cf, 9) - (x86::flag1, 10) - (x86::pf, 11) - (x86::flag3, 12) - (x86::af, 13) - (x86::flag5, 14) - (x86::zf, 15) - (x86::sf, 16) - (x86::tf, 17) - (x86::if_, 18) - (x86::df, 19) - (x86::of, 20) - (x86::flagc, 21) - (x86::flagd, 22) - (x86::nt_, 23) - (x86::flagf, 24) - (x86::rf, 25) - (x86::ds, 26) - (x86::es, 27) - (x86::fs, 28) - (x86::gs, 29) - (x86::cs, 30) - (x86::ss, 31) - (x86::oeax, 32) - (x86::fsbase, 33) - (x86::gsbase, 34) - (x86::xmm0, 35) - (x86::xmm1, 36) - (x86::xmm2, 37) - (x86::xmm3, 38) - (x86::xmm4, 39) - (x86::xmm5, 40) - (x86::xmm6, 41) - (x86::xmm7, 42) - (x86::mm0, 43) // mm0 to mm7 and st0 to st7 collapse to mm0 - (x86::cr0, 44) - (x86::cr1, 45) - (x86::cr2, 46) - (x86::cr3, 47) - (x86::cr4, 48) - (x86::cr5, 49) - (x86::cr6, 50) - (x86::cr7, 51) - (x86::dr0, 52) - (x86::dr1, 53) - (x86::dr2, 54) - (x86::dr3, 55) - (x86::dr4, 56) - (x86::dr5, 57) - (x86::dr6, 58) - (x86::dr7, 59) - (x86::tr0, 60) - (x86::tr1, 61) - (x86::tr2, 62) - (x86::tr3, 63) - (x86::tr4, 64) - (x86::tr5, 65) - (x86::tr6, 66) - (x86::tr7, 67); - } - return *mrmap; } - -RegisterMap &machRegIndex_x86_64() { - static dyn_tls RegisterMap* mrmap = NULL; - if (mrmap == NULL) { - mrmap = new RegisterMap(); - *mrmap = map_list_of - (x86_64::rax, 0) - (x86_64::rcx, 1) - (x86_64::rdx, 2) - (x86_64::rbx, 3) - (x86_64::rsp, 4) - (x86_64::rbp, 5) - (x86_64::rsi, 6) - (x86_64::rdi, 7) - (x86_64::r8, 8) - (x86_64::r9, 9) - (x86_64::r10, 10) - (x86_64::r11, 11) - (x86_64::r12, 12) - (x86_64::r13, 13) - (x86_64::r14, 14) - (x86_64::r15, 15) - (x86_64::rip, 16) - (x86_64::cf, 17) - (x86_64::pf, 18) - (x86_64::af, 19) - (x86_64::zf, 20) - (x86_64::sf, 21) - (x86_64::tf, 22) - (x86_64::if_, 23) - (x86_64::df, 24) - (x86_64::of, 25) - (x86_64::nt_, 26) - (x86_64::rf, 27) - (x86_64::ds, 28) - (x86_64::es, 29) - (x86_64::fs, 30) - (x86_64::gs, 31) - (x86_64::cs, 32) - (x86_64::ss, 33) - (x86_64::orax, 34) - (x86_64::fsbase, 35) - (x86_64::gsbase, 36) - (x86_64::k0, 37) - (x86_64::k1, 38) - (x86_64::k2, 39) - (x86_64::k3, 40) - (x86_64::k4, 41) - (x86_64::k5, 42) - (x86_64::k6, 43) - (x86_64::k7, 44) - (x86_64::zmm0, 45) - (x86_64::zmm1, 46) - (x86_64::zmm2, 47) - (x86_64::zmm3, 48) - (x86_64::zmm4, 49) - (x86_64::zmm5, 50) - (x86_64::zmm6, 51) - (x86_64::zmm7, 52) - (x86_64::zmm8, 53) - (x86_64::zmm9, 54) - (x86_64::zmm10, 55) - (x86_64::zmm11, 56) - (x86_64::zmm12, 57) - (x86_64::zmm13, 58) - (x86_64::zmm14, 59) - (x86_64::zmm15, 60) - (x86_64::zmm16, 61) - (x86_64::zmm17, 62) - (x86_64::zmm18, 63) - (x86_64::zmm19, 64) - (x86_64::zmm20, 65) - (x86_64::zmm21, 66) - (x86_64::zmm22, 67) - (x86_64::zmm23, 68) - (x86_64::zmm24, 69) - (x86_64::zmm25, 70) - (x86_64::zmm26, 71) - (x86_64::zmm27, 72) - (x86_64::zmm28, 73) - (x86_64::zmm29, 74) - (x86_64::zmm30, 75) - (x86_64::zmm31, 75) - (x86_64::ymm0, 76) - (x86_64::ymm1, 77) - (x86_64::ymm2, 78) - (x86_64::ymm3, 79) - (x86_64::ymm4, 80) - (x86_64::ymm5, 81) - (x86_64::ymm6, 82) - (x86_64::ymm7, 83) - (x86_64::ymm8, 84) - (x86_64::ymm9, 85) - (x86_64::ymm10, 86) - (x86_64::ymm11, 87) - (x86_64::ymm12, 88) - (x86_64::ymm13, 89) - (x86_64::ymm14, 90) - (x86_64::ymm15, 91) - (x86_64::ymm16, 92) - (x86_64::ymm17, 93) - (x86_64::ymm18, 94) - (x86_64::ymm19, 95) - (x86_64::ymm20, 96) - (x86_64::ymm21, 97) - (x86_64::ymm22, 98) - (x86_64::ymm23, 99) - (x86_64::ymm24, 100) - (x86_64::ymm25, 101) - (x86_64::ymm26, 102) - (x86_64::ymm27, 103) - (x86_64::ymm28, 104) - (x86_64::ymm29, 105) - (x86_64::ymm30, 106) - (x86_64::ymm31, 107) - (x86_64::xmm0, 108) - (x86_64::xmm1, 109) - (x86_64::xmm2, 110) - (x86_64::xmm3, 111) - (x86_64::xmm4, 112) - (x86_64::xmm5, 113) - (x86_64::xmm6, 114) - (x86_64::xmm7, 115) - (x86_64::xmm8, 116) - (x86_64::xmm9, 117) - (x86_64::xmm10, 118) - (x86_64::xmm11, 119) - (x86_64::xmm12, 120) - (x86_64::xmm13, 121) - (x86_64::xmm14, 122) - (x86_64::xmm15, 123) - (x86_64::xmm16, 124) - (x86_64::xmm17, 125) - (x86_64::xmm18, 126) - (x86_64::xmm19, 127) - (x86_64::xmm20, 128) - (x86_64::xmm21, 129) - (x86_64::xmm22, 130) - (x86_64::xmm23, 131) - (x86_64::xmm24, 132) - (x86_64::xmm25, 133) - (x86_64::xmm26, 134) - (x86_64::xmm27, 135) - (x86_64::xmm28, 136) - (x86_64::xmm29, 137) - (x86_64::xmm30, 138) - (x86_64::xmm31, 139) - (x86_64::mm0, 140) // mm0 to mm7 and st0 to st7 collapse to mm0 - (x86_64::cr0, 141) - (x86_64::cr1, 142) - (x86_64::cr2, 143) - (x86_64::cr3, 144) - (x86_64::cr4, 145) - (x86_64::cr5, 146) - (x86_64::cr6, 147) - (x86_64::cr7, 148) - (x86_64::dr0, 149) - (x86_64::dr1, 150) - (x86_64::dr2, 151) - (x86_64::dr3, 152) - (x86_64::dr4, 153) - (x86_64::dr5, 154) - (x86_64::dr6, 155) - (x86_64::dr7, 156) - (x86_64::tr0, 157) - (x86_64::tr1, 158) - (x86_64::tr2, 159) - (x86_64::tr3, 160) - (x86_64::tr4, 161) - (x86_64::tr5, 162) - (x86_64::tr6, 163) - (x86_64::tr7, 164) - ; - } - return *mrmap; } - -RegisterMap &machRegIndex_ppc() { - static dyn_tls RegisterMap* mrmap = NULL; - if (mrmap == NULL) { - mrmap = new RegisterMap(); - *mrmap = map_list_of - (ppc32::r0, 0) - (ppc32::r1, 1) - (ppc32::r2, 2) - (ppc32::r3, 3) - (ppc32::r4, 4) - (ppc32::r5, 5) - (ppc32::r6, 6) - (ppc32::r7, 7) - (ppc32::r8, 8) - (ppc32::r9, 9) - (ppc32::r10, 10) - (ppc32::r11, 11) - (ppc32::r12, 12) - (ppc32::r13, 13) - (ppc32::r14, 14) - (ppc32::r15, 15) - (ppc32::r16, 16) - (ppc32::r17, 17) - (ppc32::r18, 18) - (ppc32::r19, 19) - (ppc32::r20, 20) - (ppc32::r21, 21) - (ppc32::r22, 22) - (ppc32::r23, 23) - (ppc32::r24, 24) - (ppc32::r25, 25) - (ppc32::r26, 26) - (ppc32::r27, 27) - (ppc32::r28, 28) - (ppc32::r29, 29) - (ppc32::r30, 30) - (ppc32::r31, 31) - (ppc32::fpr0, 32) - (ppc32::fpr1, 33) - (ppc32::fpr2, 34) - (ppc32::fpr3, 35) - (ppc32::fpr4, 36) - (ppc32::fpr5, 37) - (ppc32::fpr6, 38) - (ppc32::fpr7, 39) - (ppc32::fpr8, 40) - (ppc32::fpr9, 41) - (ppc32::fpr10, 42) - (ppc32::fpr11, 43) - (ppc32::fpr12, 44) - (ppc32::fpr13, 45) - (ppc32::fpr14, 46) - (ppc32::fpr15, 47) - (ppc32::fpr16, 48) - (ppc32::fpr17, 49) - (ppc32::fpr18, 50) - (ppc32::fpr19, 51) - (ppc32::fpr20, 52) - (ppc32::fpr21, 53) - (ppc32::fpr22, 54) - (ppc32::fpr23, 55) - (ppc32::fpr24, 56) - (ppc32::fpr25, 57) - (ppc32::fpr26, 58) - (ppc32::fpr27, 59) - (ppc32::fpr28, 60) - (ppc32::fpr29, 61) - (ppc32::fpr30, 62) - (ppc32::fpr31, 63) - (ppc32::fsr0, 64) - (ppc32::fsr1, 65) - (ppc32::fsr2, 66) - (ppc32::fsr3, 67) - (ppc32::fsr4, 68) - (ppc32::fsr5, 69) - (ppc32::fsr6, 70) - (ppc32::fsr7, 71) - (ppc32::fsr8, 72) - (ppc32::fsr9, 73) - (ppc32::fsr10, 74) - (ppc32::fsr11, 75) - (ppc32::fsr12, 76) - (ppc32::fsr13, 77) - (ppc32::fsr14, 78) - (ppc32::fsr15, 79) - (ppc32::fsr16, 80) - (ppc32::fsr17, 81) - (ppc32::fsr18, 82) - (ppc32::fsr19, 83) - (ppc32::fsr20, 84) - (ppc32::fsr21, 85) - (ppc32::fsr22, 86) - (ppc32::fsr23, 87) - (ppc32::fsr24, 88) - (ppc32::fsr25, 89) - (ppc32::fsr26, 90) - (ppc32::fsr27, 91) - (ppc32::fsr28, 92) - (ppc32::fsr29, 93) - (ppc32::fsr30, 94) - (ppc32::fsr31, 95) - (ppc32::mq, 96) - (ppc32::xer, 97) - (ppc32::lr, 98) - (ppc32::ctr, 99) - (ppc32::dsisr, 100) - (ppc32::dar, 101) - (ppc32::dec, 102) - (ppc32::sdr1, 103) - (ppc32::srr0, 104) - (ppc32::srr1, 105) - (ppc32::sprg0, 106) - (ppc32::sprg1, 107) - (ppc32::sprg2, 108) - (ppc32::sprg3, 109) - (ppc32::sprg3_ro, 109) - (ppc32::ear, 110) - (ppc32::tbl_wo, 111) - (ppc32::tbl_ro, 111) - (ppc32::tbu_wo, 112) - (ppc32::tbu_ro, 112) - (ppc32::pvr, 113) - (ppc32::ibat0u, 114) - (ppc32::ibat0l, 115) - (ppc32::ibat1u, 116) - (ppc32::ibat1l, 117) - (ppc32::ibat2u, 118) - (ppc32::ibat2l, 119) - (ppc32::ibat3u, 120) - (ppc32::ibat3l, 121) - (ppc32::dbat0u, 122) - (ppc32::dbat0l, 123) - (ppc32::dbat1u, 124) - (ppc32::dbat1l, 125) - (ppc32::dbat2u, 126) - (ppc32::dbat2l, 127) - (ppc32::dbat3u, 128) - (ppc32::dbat3l, 129) - (ppc32::pc, 130) - (ppc32::fpscw, 131) - (ppc32::fpscw0, 132) - (ppc32::fpscw1, 133) - (ppc32::fpscw2, 134) - (ppc32::fpscw3, 135) - (ppc32::fpscw4, 136) - (ppc32::fpscw5, 137) - (ppc32::fpscw6, 138) - (ppc32::fpscw7, 139) - (ppc32::msr, 140) - (ppc32::ivpr, 141) - (ppc32::ivor8, 142) - (ppc32::seg0, 143) - (ppc32::seg1, 144) - (ppc32::seg2, 145) - (ppc32::seg3, 146) - (ppc32::seg4, 147) - (ppc32::seg5, 148) - (ppc32::seg6, 149) - (ppc32::seg7, 150) - (ppc32::cr0, 151) - (ppc32::cr1, 152) - (ppc32::cr2, 153) - (ppc32::cr3, 154) - (ppc32::cr4, 155) - (ppc32::cr5, 156) - (ppc32::cr6, 157) - (ppc32::cr7, 158) - (ppc32::cr, 159) - (ppc32::sprg4, 160) - (ppc32::sprg4_ro, 160) - (ppc32::sprg5, 161) - (ppc32::sprg5_ro, 161) - (ppc32::sprg6, 162) - (ppc32::sprg6_ro, 162) - (ppc32::sprg7, 163) - (ppc32::sprg7_ro, 163); - } - return *mrmap; -} - -RegisterMap &machRegIndex_ppc_64() { - static dyn_tls RegisterMap* mrmap = NULL; - if (mrmap == NULL) { - mrmap = new RegisterMap(); - *mrmap = map_list_of - (ppc64::r0, 0) - (ppc64::r1, 1) - (ppc64::r2, 2) - (ppc64::r3, 3) - (ppc64::r4, 4) - (ppc64::r5, 5) - (ppc64::r6, 6) - (ppc64::r7, 7) - (ppc64::r8, 8) - (ppc64::r9, 9) - (ppc64::r10, 10) - (ppc64::r11, 11) - (ppc64::r12, 12) - (ppc64::r13, 13) - (ppc64::r14, 14) - (ppc64::r15, 15) - (ppc64::r16, 16) - (ppc64::r17, 17) - (ppc64::r18, 18) - (ppc64::r19, 19) - (ppc64::r20, 20) - (ppc64::r21, 21) - (ppc64::r22, 22) - (ppc64::r23, 23) - (ppc64::r24, 24) - (ppc64::r25, 25) - (ppc64::r26, 26) - (ppc64::r27, 27) - (ppc64::r28, 28) - (ppc64::r29, 29) - (ppc64::r30, 30) - (ppc64::r31, 31) - (ppc64::fpr0, 32) - (ppc64::fpr1, 33) - (ppc64::fpr2, 34) - (ppc64::fpr3, 35) - (ppc64::fpr4, 36) - (ppc64::fpr5, 37) - (ppc64::fpr6, 38) - (ppc64::fpr7, 39) - (ppc64::fpr8, 40) - (ppc64::fpr9, 41) - (ppc64::fpr10, 42) - (ppc64::fpr11, 43) - (ppc64::fpr12, 44) - (ppc64::fpr13, 45) - (ppc64::fpr14, 46) - (ppc64::fpr15, 47) - (ppc64::fpr16, 48) - (ppc64::fpr17, 49) - (ppc64::fpr18, 50) - (ppc64::fpr19, 51) - (ppc64::fpr20, 52) - (ppc64::fpr21, 53) - (ppc64::fpr22, 54) - (ppc64::fpr23, 55) - (ppc64::fpr24, 56) - (ppc64::fpr25, 57) - (ppc64::fpr26, 58) - (ppc64::fpr27, 59) - (ppc64::fpr28, 60) - (ppc64::fpr29, 61) - (ppc64::fpr30, 62) - (ppc64::fpr31, 63) - (ppc64::fsr0, 64) - (ppc64::fsr1, 65) - (ppc64::fsr2, 66) - (ppc64::fsr3, 67) - (ppc64::fsr4, 68) - (ppc64::fsr5, 69) - (ppc64::fsr6, 70) - (ppc64::fsr7, 71) - (ppc64::fsr8, 72) - (ppc64::fsr9, 73) - (ppc64::fsr10, 74) - (ppc64::fsr11, 75) - (ppc64::fsr12, 76) - (ppc64::fsr13, 77) - (ppc64::fsr14, 78) - (ppc64::fsr15, 79) - (ppc64::fsr16, 80) - (ppc64::fsr17, 81) - (ppc64::fsr18, 82) - (ppc64::fsr19, 83) - (ppc64::fsr20, 84) - (ppc64::fsr21, 85) - (ppc64::fsr22, 86) - (ppc64::fsr23, 87) - (ppc64::fsr24, 88) - (ppc64::fsr25, 89) - (ppc64::fsr26, 90) - (ppc64::fsr27, 91) - (ppc64::fsr28, 92) - (ppc64::fsr29, 93) - (ppc64::fsr30, 94) - (ppc64::fsr31, 95) - (ppc64::mq, 96) - (ppc64::xer, 97) - (ppc64::lr, 98) - (ppc64::ctr, 99) - (ppc64::dsisr, 100) - (ppc64::dar, 101) - (ppc64::dec, 102) - (ppc64::sdr1, 103) - (ppc64::srr0, 104) - (ppc64::srr1, 105) - (ppc64::sprg0, 106) - (ppc64::sprg1, 107) - (ppc64::sprg2, 108) - (ppc64::sprg3, 109) - (ppc64::sprg3_ro, 109) - (ppc64::ear, 110) - (ppc64::tbl_wo, 111) - (ppc64::tbl_ro, 111) - (ppc64::tbu_wo, 112) - (ppc64::tbu_ro, 112) - (ppc64::pvr, 113) - (ppc64::ibat0u, 114) - (ppc64::ibat0l, 115) - (ppc64::ibat1u, 116) - (ppc64::ibat1l, 117) - (ppc64::ibat2u, 118) - (ppc64::ibat2l, 119) - (ppc64::ibat3u, 120) - (ppc64::ibat3l, 121) - (ppc64::dbat0u, 122) - (ppc64::dbat0l, 123) - (ppc64::dbat1u, 124) - (ppc64::dbat1l, 125) - (ppc64::dbat2u, 126) - (ppc64::dbat2l, 127) - (ppc64::dbat3u, 128) - (ppc64::dbat3l, 129) - (ppc64::pc, 130) - (ppc64::fpscw, 131) - (ppc64::fpscw0, 132) - (ppc64::fpscw1, 133) - (ppc64::fpscw2, 134) - (ppc64::fpscw3, 135) - (ppc64::fpscw4, 136) - (ppc64::fpscw5, 137) - (ppc64::fpscw6, 138) - (ppc64::fpscw7, 139) - (ppc64::msr, 140) - (ppc64::ivpr, 141) - (ppc64::ivor8, 142) - (ppc64::seg0, 143) - (ppc64::seg1, 144) - (ppc64::seg2, 145) - (ppc64::seg3, 146) - (ppc64::seg4, 147) - (ppc64::seg5, 148) - (ppc64::seg6, 149) - (ppc64::seg7, 150) - (ppc64::cr0, 151) - (ppc64::cr1, 152) - (ppc64::cr2, 153) - (ppc64::cr3, 154) - (ppc64::cr4, 155) - (ppc64::cr5, 156) - (ppc64::cr6, 157) - (ppc64::cr7, 158) - (ppc64::cr, 159) - (ppc64::sprg4, 160) - (ppc64::sprg4_ro, 160) - (ppc64::sprg5, 161) - (ppc64::sprg5_ro, 161) - (ppc64::sprg6, 162) - (ppc64::sprg6_ro, 162) - (ppc64::sprg7, 163) - (ppc64::sprg7_ro, 163); - } - return *mrmap; -} - -RegisterMap &machRegIndex_aarch64() { - static dyn_tls RegisterMap* mrmap = NULL; - if (mrmap == NULL) { - mrmap = new RegisterMap(); - *mrmap = map_list_of - (aarch64::x0, 0) - (aarch64::x1, 1) - (aarch64::x2, 2) - (aarch64::x3, 3) - (aarch64::x4, 4) - (aarch64::x5, 5) - (aarch64::x6, 6) - (aarch64::x7, 7) - (aarch64::x8, 8) - (aarch64::x9, 9) - (aarch64::x10, 10) - (aarch64::x11, 11) - (aarch64::x12, 12) - (aarch64::x13, 13) - (aarch64::x14, 14) - (aarch64::x15, 15) - (aarch64::x16, 16) - (aarch64::x17, 17) - (aarch64::x18, 18) - (aarch64::x19, 19) - (aarch64::x20, 20) - (aarch64::x21, 21) - (aarch64::x22, 22) - (aarch64::x23, 23) - (aarch64::x24, 24) - (aarch64::x25, 25) - (aarch64::x26, 26) - (aarch64::x27, 27) - (aarch64::x28, 28) - (aarch64::x29, 29) - (aarch64::x30, 30) - (aarch64::w0, 0) - (aarch64::w1, 1) - (aarch64::w2, 2) - (aarch64::w3, 3) - (aarch64::w4, 4) - (aarch64::w5, 5) - (aarch64::w6, 6) - (aarch64::w7, 7) - (aarch64::w8, 8) - (aarch64::w9, 9) - (aarch64::w10, 10) - (aarch64::w11, 11) - (aarch64::w12, 12) - (aarch64::w13, 13) - (aarch64::w14, 14) - (aarch64::w15, 15) - (aarch64::w16, 16) - (aarch64::w17, 17) - (aarch64::w18, 18) - (aarch64::w19, 19) - (aarch64::w20, 20) - (aarch64::w21, 21) - (aarch64::w22, 22) - (aarch64::w23, 23) - (aarch64::w24, 24) - (aarch64::w25, 25) - (aarch64::w26, 26) - (aarch64::w27, 27) - (aarch64::w28, 28) - (aarch64::w29, 29) - (aarch64::w30, 30) - (aarch64::q0, 31) - (aarch64::q1, 32) - (aarch64::q2, 33) - (aarch64::q3, 34) - (aarch64::q4, 35) - (aarch64::q5, 36) - (aarch64::q6, 37) - (aarch64::q7, 38) - (aarch64::q8, 39) - (aarch64::q9, 40) - (aarch64::q10, 41) - (aarch64::q11, 42) - (aarch64::q12, 43) - (aarch64::q13, 44) - (aarch64::q14, 45) - (aarch64::q15, 46) - (aarch64::q16, 47) - (aarch64::q17, 48) - (aarch64::q18, 49) - (aarch64::q19, 50) - (aarch64::q20, 51) - (aarch64::q21, 52) - (aarch64::q22, 53) - (aarch64::q23, 54) - (aarch64::q24, 55) - (aarch64::q25, 56) - (aarch64::q26, 57) - (aarch64::q27, 58) - (aarch64::q28, 59) - (aarch64::q29, 60) - (aarch64::q30, 61) - (aarch64::q31, 62) - (aarch64::fpcr,63) - (aarch64::fpsr,64) - (aarch64::pc, 65) - (aarch64::sp, 66) - (aarch64::pstate, 67) - (aarch64::xzr, 68); - } - - return mrmap; -} - -#endif - -}; -}; diff --git a/dataflowAPI/src/RegisterMap.h b/dataflowAPI/src/RegisterMap.h index 1145ab89d0..3c292eb56c 100644 --- a/dataflowAPI/src/RegisterMap.h +++ b/dataflowAPI/src/RegisterMap.h @@ -31,7 +31,7 @@ #define REGISTERMAP_H #include -#include "common/h/dyn_regs.h" +#include "registers/MachRegister.h" namespace Dyninst { namespace DataflowAPI { @@ -44,7 +44,7 @@ RegisterMap &machRegIndex_ppc(); RegisterMap &machRegIndex_ppc_64(); RegisterMap &machRegIndex_aarch64(); -}; -}; +} +} #endif //REGISTERMAP_H diff --git a/dataflowAPI/src/RoseImpl.C b/dataflowAPI/src/RoseImpl.C index abf21c4f74..33410e67d9 100644 --- a/dataflowAPI/src/RoseImpl.C +++ b/dataflowAPI/src/RoseImpl.C @@ -35,7 +35,7 @@ #include "../rose/SgAsmx86Instruction.h" #include "../rose/SgAsmPowerpcInstruction.h" #include "../rose/SgAsmArmv8Instruction.h" -#include "../rose/SgAsmAmdgpuVegaInstruction.h" +#include "../rose/SgAsmAMDGPUInstruction.h" #include "external/rose/rose-compat.h" #include "../rose/RegisterDescriptor.h" #include "../rose/x86InstructionSemantics.h" @@ -725,12 +725,12 @@ SgAsmFloatValueExpression::~SgAsmFloatValueExpression() { } -SgAsmFloatValueExpression::SgAsmFloatValueExpression(double value, SgAsmType *type) { +SgAsmFloatValueExpression::SgAsmFloatValueExpression(double value, SgAsmType * /*type*/) { p_nativeValue = value; p_nativeValueIsValid = true; } -SgAsmFloatValueExpression::SgAsmFloatValueExpression(const Sawyer::Container::BitVector &bv, SgAsmType *type) { +SgAsmFloatValueExpression::SgAsmFloatValueExpression(const Sawyer::Container::BitVector &bv, SgAsmType * /*type*/) { p_nativeValue = 0.0; p_nativeValueIsValid = false; p_bitVector = bv; @@ -795,10 +795,7 @@ SgAsmBinaryAdd::SgAsmBinaryAdd(SgAsmExpression *lhs, SgAsmExpression *rhs) } SgAsmType *SgAsmBinaryAdd::get_type() const { - SgAsmBinaryExpression *addExpr = &(*(const_cast(this))); - SgAsmBinaryExpression binExpr = *addExpr; - return (&binExpr)->get_type(); - //return ((SgAsmBinaryExpression *) this)->get_type(); + return SgAsmBinaryExpression::get_type(); } std::string SgAsmBinaryAdd::class_name() const { @@ -838,7 +835,7 @@ SgAsmBinaryMultiply::SgAsmBinaryMultiply(SgAsmExpression *lhs, SgAsmExpression * } SgAsmType *SgAsmBinaryMultiply::get_type() const { - return ((SgAsmBinaryExpression *) this)->get_type(); + return SgAsmBinaryExpression::get_type(); } std::string SgAsmBinaryMultiply::class_name() const { @@ -1367,32 +1364,37 @@ size_t SgAsmInstruction::get_size() const { return p_raw_bytes.size(); } -// defs for SgAsmAmdgpuVegaInstruction -std::string SgAsmAmdgpuVegaInstruction::class_name() const { - return "SgAsmAmdgpuVegaInstruction"; +// defs for SgAsmAMDGPUInstruction +SgAsmAMDGPUInstruction *isSgAsmAMDGPUInstruction(SgNode *s) { + return dynamic_cast(s); } -VariantT SgAsmAmdgpuVegaInstruction::variantT() const { - return V_SgAsmAmdgpuVegaInstruction; +std::string SgAsmAMDGPUInstruction::class_name() const { + return "SgAsmAMDGPUGfx90aInstruction"; } -SgAsmAmdgpuVegaInstruction::SgAsmAmdgpuVegaInstruction(rose_addr_t address, std::string mnemonic, AmdgpuVegaInstructionKind kind) : +VariantT SgAsmAMDGPUInstruction::variantT() const { + return V_SgAsmAMDGPUInstruction; +} + +SgAsmAMDGPUInstruction::SgAsmAMDGPUInstruction(rose_addr_t address, std::string mnemonic, AMDGPUInstructionKind kind) : SgAsmInstruction(address, mnemonic) { p_kind = kind; } -AmdgpuVegaInstructionKind SgAsmAmdgpuVegaInstruction::get_kind() const { +AMDGPUInstructionKind SgAsmAMDGPUInstruction::get_kind() const { return p_kind; } -void SgAsmAmdgpuVegaInstruction::set_kind(AmdgpuVegaInstructionKind kind) { +void SgAsmAMDGPUInstruction::set_kind(AMDGPUInstructionKind kind) { p_kind = kind; } -SgAsmAmdgpuVegaInstruction::~SgAsmAmdgpuVegaInstruction() { +SgAsmAMDGPUInstruction::~SgAsmAMDGPUInstruction() { p_kind = rose_amdgpu_op_INVALID; } + // defs for SgAsmArmv8Instruction std::string SgAsmArmv8Instruction::class_name() const { return "SgAsmArmv8Instruction"; @@ -1633,10 +1635,6 @@ SgAsmArmv8Instruction *isSgAsmArmv8Instruction(SgNode *s) { return dynamic_cast(s); } -SgAsmAmdgpuVegaInstruction *isSgAsmAmdgpuVegaInstruction(SgNode *s) { - return dynamic_cast(s); -} - SgAsmPowerpcInstruction *isSgAsmPowerpcInstruction(SgNode *s) { return dynamic_cast(s); diff --git a/dataflowAPI/src/RoseInsnFactory.C b/dataflowAPI/src/RoseInsnFactory.C index b0120f5e90..e5edee42cd 100644 --- a/dataflowAPI/src/RoseInsnFactory.C +++ b/dataflowAPI/src/RoseInsnFactory.C @@ -27,6 +27,7 @@ * License along with this library; if not, write to the Free Software * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include "RoseInsnFactory.h" #include "Instruction.h" @@ -37,7 +38,7 @@ #include "../rose/SgAsmInstruction.h" #include "../rose/SgAsmPowerpcInstruction.h" -#include "../rose/SgAsmAmdgpuVegaInstruction.h" +#include "../rose/SgAsmAMDGPUInstruction.h" #include "../rose/SgAsmArmv8Instruction.h" #include "../rose/SgAsmx86Instruction.h" @@ -152,11 +153,13 @@ void RoseInsnX86Factory::massageOperands(const Instruction &insn, operands.resize(2); break; } + case e_call: case e_push: case e_pop: + // ROSE does not need implicit registers operands.resize(1); break; - case e_cmpxch: + case e_cmpxchg: operands.resize(2); break; case e_movsb: @@ -192,8 +195,8 @@ void RoseInsnX86Factory::massageOperands(const Instruction &insn, // Nada operands.clear(); break; - case e_popad: - case e_pushfd: + case e_popaw: + case e_pushf: operands.clear(); break; case e_lodsd: @@ -201,12 +204,12 @@ void RoseInsnX86Factory::massageOperands(const Instruction &insn, case e_lodsw: operands.clear(); break; - case e_pushad: + case e_pushal: operands.clear(); break; case e_loop: case e_loope: - case e_loopn: + case e_loopne: operands.resize(1); break; case e_ret_far: @@ -316,7 +319,7 @@ bool RoseInsnPPCFactory::handleSpecialCases(entryID iapi_opcode, // It looks like the ROSE semantics code will infer the target from // the bo field. So, what is passed in as the third operands does not matter - if(branch_target) { + if(power_op_b == iapi_opcode || power_op_bc == iapi_opcode) { rose_operands->append_operand(new SgAsmDoubleWordValueExpression(branch_target)); } else if(power_op_bcctr == iapi_opcode) { rose_operands->append_operand(new SgAsmPowerpcRegisterReferenceExpression(powerpc_regclass_spr, powerpc_spr_ctr)); @@ -389,7 +392,7 @@ void RoseInsnPPCFactory::massageOperands(const Instruction &insn, return; } -void RoseInsnArmv8Factory::setSizes(SgAsmInstruction */*insn*/) { +void RoseInsnArmv8Factory::setSizes(SgAsmInstruction * /*insn*/) { } @@ -406,96 +409,55 @@ bool RoseInsnArmv8Factory::handleSpecialCases(entryID, SgAsmInstruction *, SgAsm return false; } -void RoseInsnArmv8Factory::massageOperands(const Instruction &insn, - std::vector &operands) { +void RoseInsnArmv8Factory::massageOperands(const Instruction &/*insn*/, + std::vector &/*operands*/) { } - -void RoseInsnAmdgpuVegaFactory::setSizes(SgAsmInstruction */*insn*/) { +void RoseInsnAMDGPUFactory::setSizes(SgAsmInstruction * /*insn*/) { } -SgAsmInstruction *RoseInsnAmdgpuVegaFactory::createInsn() { - return new SgAsmAmdgpuVegaInstruction; +SgAsmInstruction *RoseInsnAMDGPUFactory::createInsn() { + return new SgAsmAMDGPUInstruction; } -void RoseInsnAmdgpuVegaFactory::setOpcode(SgAsmInstruction *insn, entryID opcode, prefixEntryID, std::string) { - SgAsmAmdgpuVegaInstruction *tmp = static_cast(insn); - tmp->set_kind(convertKind(opcode)); -} -bool RoseInsnAmdgpuVegaFactory::handleSpecialCases(entryID, SgAsmInstruction *, SgAsmOperandList *) { - return false; +void RoseInsnAMDGPUFactory::setOpcode(SgAsmInstruction *insn, entryID opcode, prefixEntryID, std::string) { + SgAsmAMDGPUInstruction *tmp = static_cast(insn); + tmp->set_kind(convertKind(opcode)); } - -// This helper function expand a single sgpr pair operand into two constructing components -static std::pair expandSgprPair(InstructionAPI::Operand orig){ - RegisterAST::Ptr sgpr_pair = boost::dynamic_pointer_cast(orig.getValue()); - unsigned int offset = sgpr_pair->getID() - amdgpu_vega::sgpr_vec2_0 ; - - MachRegister m_low = MachRegister(amdgpu_vega::sgpr0+offset) ; - MachRegister m_high = MachRegister(amdgpu_vega::sgpr0+offset+1) ; - Expression::Ptr e_oper0 = make_shared(singleton_object_pool::construct(m_low,0,m_low.size()*8)); - Expression::Ptr e_oper1 = make_shared(singleton_object_pool::construct(m_high,0,m_high.size()*8)); - - auto oper0 = Operand(e_oper0,orig.isRead(),orig.isWritten()); - auto oper1 = Operand(e_oper1,orig.isRead(),orig.isWritten()); - - return std::make_pair(oper0,oper1); +bool RoseInsnAMDGPUFactory::handleSpecialCases(entryID, SgAsmInstruction *, SgAsmOperandList *) { + return false; } // TODO: Turn sgpr_pair operands into individual registers -void RoseInsnAmdgpuVegaFactory::massageOperands(const Instruction &insn, +void RoseInsnAMDGPUFactory::massageOperands(const Instruction &insn, std::vector &operands) { switch (insn.getOperation().getID()) { - case amdgpu_op_s_swappc_b64: - { - // swap pc has two operands - // first one is the source of new pc - // second one is dst for storing the pc, so we turn it into 4 registers - // TODO : Make this a function call - assert(operands.size() == 2); - InstructionAPI::Operand oper0,oper1,oper2,oper3; - std::tie(oper0,oper1) = expandSgprPair(operands[0]); - std::tie(oper2,oper3) = expandSgprPair(operands[1]); - operands.resize(4); - operands[0] = oper0; - operands[1] = oper1; - operands[2] = oper2; - operands[3] = oper3; - break; - - - } - - case amdgpu_op_s_setpc_b64: - { - assert(operands.size() == 1); - - InstructionAPI::Operand oper0,oper1; - std::tie(oper0,oper1) = expandSgprPair(operands[0]); - operands.resize(2); - operands[0] = oper0; - operands[1] = oper1; - - break; - - } - case amdgpu_op_s_getpc_b64: - { - assert(operands.size() == 1); - - InstructionAPI::Operand oper0,oper1; - std::tie(oper0,oper1) = expandSgprPair(operands[0]); - operands.resize(3); - operands[0] = oper0; - operands[1] = oper1; - operands[2] = Operand(InstructionAPI::Immediate::makeImmediate(Result(u64,_addr+4)),false,false); - - break; - } - default: - break; + + case amdgpu_gfx908_op_S_SWAPPC_B64: + case amdgpu_gfx90a_op_S_SWAPPC_B64: + case amdgpu_gfx940_op_S_SWAPPC_B64: { + assert(operands.size() == 6); + break; + } + case amdgpu_gfx908_op_S_SETPC_B64: + case amdgpu_gfx90a_op_S_SETPC_B64: + case amdgpu_gfx940_op_S_SETPC_B64: { + assert(operands.size() == 3); + break; + + } + case amdgpu_gfx908_op_S_GETPC_B64: + case amdgpu_gfx90a_op_S_GETPC_B64: + case amdgpu_gfx940_op_S_GETPC_B64: { + assert(operands.size() == 3); + operands[2] = Operand(InstructionAPI::Immediate::makeImmediate(Result(u64,_addr+4)),false,false); + break; } + default: + break; + } + } diff --git a/dataflowAPI/src/RoseInsnFactory.h b/dataflowAPI/src/RoseInsnFactory.h index b3d671c720..9d2dae0760 100644 --- a/dataflowAPI/src/RoseInsnFactory.h +++ b/dataflowAPI/src/RoseInsnFactory.h @@ -27,7 +27,6 @@ * License along with this library; if not, write to the Free Software * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ -#pragma once #if !defined(_ROSE_INSN_FACTORY_H_) #define _ROSE_INSN_FACTORY_H_ @@ -40,16 +39,13 @@ #include "Visitor.h" #include "Instruction.h" #include "common/h/util.h" -#include "boost/shared_ptr.hpp" +#include "dyncompat/shared_ptr.hpp" #include - -#if defined(_MSC_VER) -#include "external/stdint-win.h" -#else +#include +#include #include -#endif class SgAsmInstruction; @@ -85,13 +81,13 @@ namespace Dyninst { namespace DataflowAPI { class RoseInsnFactory { protected: - typedef boost::shared_ptr ExpressionPtr; - typedef boost::shared_ptr InstructionPtr; + typedef dyncompat::shared_ptr ExpressionPtr; + typedef dyncompat::shared_ptr InstructionPtr; uint64_t _addr = 0 ; public: - DATAFLOW_EXPORT RoseInsnFactory(void) { }; + DATAFLOW_EXPORT RoseInsnFactory(void) { } - DATAFLOW_EXPORT virtual ~RoseInsnFactory(void) { }; + DATAFLOW_EXPORT virtual ~RoseInsnFactory(void) { } DATAFLOW_EXPORT virtual SgAsmInstruction *convert(const InstructionAPI::Instruction &insn, uint64_t addr); @@ -111,14 +107,14 @@ namespace Dyninst { friend class ExpressionConversionVisitor; - virtual Architecture arch() { return Arch_none; }; + virtual Architecture arch() { return Arch_none; } }; class RoseInsnX86Factory : public RoseInsnFactory { public: - DATAFLOW_EXPORT RoseInsnX86Factory(Architecture arch) : a(arch) { }; + DATAFLOW_EXPORT RoseInsnX86Factory(Architecture arch) : a(arch) { } - DATAFLOW_EXPORT virtual ~RoseInsnX86Factory() { }; + DATAFLOW_EXPORT virtual ~RoseInsnX86Factory() { } private: Architecture a; @@ -136,14 +132,14 @@ namespace Dyninst { X86InstructionKind convertKind(entryID opcode, prefixEntryID prefix); - virtual Architecture arch() { return a; }; + virtual Architecture arch() { return a; } }; class RoseInsnPPCFactory : public RoseInsnFactory { public: - DATAFLOW_EXPORT RoseInsnPPCFactory(void) { }; + DATAFLOW_EXPORT RoseInsnPPCFactory(void) { } - DATAFLOW_EXPORT virtual ~RoseInsnPPCFactory(void) { }; + DATAFLOW_EXPORT virtual ~RoseInsnPPCFactory(void) { } private: virtual SgAsmInstruction *createInsn(); @@ -161,15 +157,15 @@ namespace Dyninst { PowerpcInstructionKind makeRoseBranchOpcode(entryID iapi_opcode, bool isAbsolute, bool isLink); - virtual Architecture arch() { return Arch_ppc32; }; + virtual Architecture arch() { return Arch_ppc32; } PowerpcInstructionKind kind; }; class RoseInsnArmv8Factory : public RoseInsnFactory { public: - DATAFLOW_EXPORT RoseInsnArmv8Factory(Architecture arch) : a(arch) { }; + DATAFLOW_EXPORT RoseInsnArmv8Factory(Architecture arch) : a(arch) { } - DATAFLOW_EXPORT virtual ~RoseInsnArmv8Factory() { }; + DATAFLOW_EXPORT virtual ~RoseInsnArmv8Factory() { } private: Architecture a; @@ -187,14 +183,14 @@ namespace Dyninst { ARMv8InstructionKind convertKind(entryID opcode); - virtual Architecture arch() { return a; }; + virtual Architecture arch() { return a; } }; - - class RoseInsnAmdgpuVegaFactory : public RoseInsnFactory { + + class RoseInsnAMDGPUFactory : public RoseInsnFactory { public: - DATAFLOW_EXPORT RoseInsnAmdgpuVegaFactory(Architecture arch) : a(arch) { }; + DATAFLOW_EXPORT RoseInsnAMDGPUFactory(Architecture arch) : a(arch) { } - DATAFLOW_EXPORT virtual ~RoseInsnAmdgpuVegaFactory() { }; + DATAFLOW_EXPORT virtual ~RoseInsnAMDGPUFactory() { } private: Architecture a; @@ -210,12 +206,12 @@ namespace Dyninst { virtual void setSizes(SgAsmInstruction *insn); - AmdgpuVegaInstructionKind convertKind(entryID opcode); + AMDGPUInstructionKind convertKind(entryID opcode); - virtual Architecture arch() { return a; }; + virtual Architecture arch() { return a; } }; - }; -}; + } +} #endif diff --git a/dataflowAPI/src/SymEval.C b/dataflowAPI/src/SymEval.C index 89e1eea2df..83b86771be 100644 --- a/dataflowAPI/src/SymEval.C +++ b/dataflowAPI/src/SymEval.C @@ -28,6 +28,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include #include #include @@ -55,7 +56,10 @@ #include "debug_dataflow.h" -#include "boost/tuple/tuple.hpp" +#include "dyncompat/tuple/tuple.hpp" + +/* once flag for the warning of unimplemented symbolic expansion */ +#include using namespace std; using namespace Dyninst; @@ -139,7 +143,7 @@ void dfs(Node::Ptr source, //state[source]++; std::map::iterator ssit = state.find(source); if(ssit == state.end()) - boost::tuples::tie(ssit,boost::tuples::ignore) = + dyncompat::tuples::tie(ssit,dyncompat::tuples::ignore) = state.insert(make_pair(source,1)); else (*ssit).second++; @@ -217,7 +221,7 @@ class ExpandOrder { Edge::Ptr edge = *begin; if(skip_edges.find(edge) == skip_edges.end()) { SliceNode::Ptr parent = - boost::static_pointer_cast( + dyncompat::static_pointer_cast( edge->source()); if(done.find(parent) == done.end()) ++pcnt; @@ -246,7 +250,7 @@ class ExpandOrder { Edge::Ptr edge = *begin; if(skip_edges.find(edge) == skip_edges.end()) { SliceNode::Ptr child = - boost::static_pointer_cast( + dyncompat::static_pointer_cast( edge->target()); if(remove(child)) children.insert(child); @@ -320,7 +324,7 @@ SymEval::Retval_t SymEval::expand(Dyninst::Graph::Ptr slice, DataflowAPI::Result for ( ; gbegin != gend; ++gbegin) { Node::Ptr ptr = *gbegin; expand_cerr << "pushing " << (*gbegin)->format() << " to sortVector" << endl; - SliceNode::Ptr cur = boost::static_pointer_cast(ptr); + SliceNode::Ptr cur = dyncompat::static_pointer_cast(ptr); sortVector.push_back(cur); } std::stable_sort(sortVector.begin(), sortVector.end(), vectorSort); @@ -332,7 +336,7 @@ SymEval::Retval_t SymEval::expand(Dyninst::Graph::Ptr slice, DataflowAPI::Result std::vector::iterator vit = sortVector.begin(); for ( ; vit != sortVector.end(); ++vit) { SliceNode::Ptr ptr = *vit; - Node::Ptr cur = boost::static_pointer_cast(ptr); + Node::Ptr cur = dyncompat::static_pointer_cast(ptr); dfs_worklist.push(cur); } @@ -349,7 +353,7 @@ SymEval::Retval_t SymEval::expand(Dyninst::Graph::Ptr slice, DataflowAPI::Result expand_cerr << "adding " << (*gbegin)->format() << " to worklist" << endl; Node::Ptr ptr = *gbegin; SliceNode::Ptr sptr = - boost::static_pointer_cast(ptr); + dyncompat::static_pointer_cast(ptr); worklist.insert(sptr,false); } @@ -362,7 +366,7 @@ SymEval::Retval_t SymEval::expand(Dyninst::Graph::Ptr slice, DataflowAPI::Result SliceNode::Ptr aNode; int order; - boost::tie(aNode,order) = worklist.pop_next(); + std::tie(aNode,order) = worklist.pop_next(); if (order == -1) // empty break; @@ -413,7 +417,7 @@ SymEval::Retval_t SymEval::expand(Dyninst::Graph::Ptr slice, DataflowAPI::Result for (; oB != oE; ++oB) { if(worklist.skipEdges().find(*oB) == worklist.skipEdges().end()) { SliceNode::Ptr out = - boost::static_pointer_cast( + dyncompat::static_pointer_cast( (*oB)->target()); worklist.insert(out); } @@ -517,27 +521,70 @@ bool SymEval::expandInsn(const Instruction &insn, break; } - case Arch_amdgpu_vega: { + case Arch_amdgpu_gfx908: { + + RoseInsnAMDGPUFactory fac(Arch_amdgpu_gfx908); + auto roseInsn = std::unique_ptr(fac.convert(insn, addr)); + if (!roseInsn) return false; + + SymbolicExpansion exp; + const RegisterDictionary *reg_dict = RegisterDictionary::dictionary_amdgpu(); - RoseInsnAmdgpuVegaFactory fac(Arch_amdgpu_vega); - auto roseInsn = std::unique_ptr(fac.convert(insn, addr)); - if (!roseInsn) return false; + BaseSemantics::SValuePtr protoval = SymEvalSemantics::SValue::instance(1, 0); + BaseSemantics::RegisterStatePtr registerState = SymEvalSemantics::RegisterStateAST_amdgpu_gfx908::instance(protoval, reg_dict); + BaseSemantics::MemoryStatePtr memoryState = SymEvalSemantics::MemoryStateAST::instance(protoval, protoval); + BaseSemantics::StatePtr state = SymEvalSemantics::StateAST::instance(res, addr, insn.getArch(), insn, registerState, memoryState); + BaseSemantics::RiscOperatorsPtr ops = SymEvalSemantics::RiscOperatorsAST::instance(state); + exp.expandAMDGPU(roseInsn.get(), ops, insn.format()); + + break; + } + case Arch_amdgpu_gfx90a: { - SymbolicExpansion exp; - const RegisterDictionary *reg_dict = RegisterDictionary::dictionary_amdgpu_vega(); + RoseInsnAMDGPUFactory fac(Arch_amdgpu_gfx90a); + auto roseInsn = std::unique_ptr(fac.convert(insn, addr)); + if (!roseInsn) return false; + + SymbolicExpansion exp; + const RegisterDictionary *reg_dict = RegisterDictionary::dictionary_amdgpu(); + + BaseSemantics::SValuePtr protoval = SymEvalSemantics::SValue::instance(1, 0); + BaseSemantics::RegisterStatePtr registerState = SymEvalSemantics::RegisterStateAST_amdgpu_gfx90a::instance(protoval, reg_dict); + BaseSemantics::MemoryStatePtr memoryState = SymEvalSemantics::MemoryStateAST::instance(protoval, protoval); + BaseSemantics::StatePtr state = SymEvalSemantics::StateAST::instance(res, addr, insn.getArch(), insn, registerState, memoryState); + BaseSemantics::RiscOperatorsPtr ops = SymEvalSemantics::RiscOperatorsAST::instance(state); + exp.expandAMDGPU(roseInsn.get(), ops, insn.format()); + + break; + } + case Arch_amdgpu_gfx940: { - BaseSemantics::SValuePtr protoval = SymEvalSemantics::SValue::instance(1, 0); - BaseSemantics::RegisterStatePtr registerState = SymEvalSemantics::RegisterStateAST_AMDGPU_VEGA::instance(protoval, reg_dict); - BaseSemantics::MemoryStatePtr memoryState = SymEvalSemantics::MemoryStateAST::instance(protoval, protoval); - BaseSemantics::StatePtr state = SymEvalSemantics::StateAST::instance(res, addr, insn.getArch(), insn, registerState, memoryState); - BaseSemantics::RiscOperatorsPtr ops = SymEvalSemantics::RiscOperatorsAST::instance(state); - exp.expandAmdgpuVega(roseInsn.get(), ops, insn.format()); + RoseInsnAMDGPUFactory fac(Arch_amdgpu_gfx940); + auto roseInsn = std::unique_ptr(fac.convert(insn, addr)); + if (!roseInsn) return false; + + SymbolicExpansion exp; + const RegisterDictionary *reg_dict = RegisterDictionary::dictionary_amdgpu(); + + BaseSemantics::SValuePtr protoval = SymEvalSemantics::SValue::instance(1, 0); + BaseSemantics::RegisterStatePtr registerState = SymEvalSemantics::RegisterStateAST_amdgpu_gfx940::instance(protoval, reg_dict); + BaseSemantics::MemoryStatePtr memoryState = SymEvalSemantics::MemoryStateAST::instance(protoval, protoval); + BaseSemantics::StatePtr state = SymEvalSemantics::StateAST::instance(res, addr, insn.getArch(), insn, registerState, memoryState); + BaseSemantics::RiscOperatorsPtr ops = SymEvalSemantics::RiscOperatorsAST::instance(state); + exp.expandAMDGPU(roseInsn.get(), ops, insn.format()); + + break; + } - break; - } default: - assert(0 && "Unimplemented symbolic expansion architecture"); - break; + /* once per arch would be better, but ... */ + static std::once_flag arch_warning_flag; + std::call_once(arch_warning_flag, [&]{ + cerr << "Unimplemented symbolic expansion architecture: " << insn.getArch() << endl; + } + ); + return false; + break; } return true; @@ -563,8 +610,8 @@ SymEval::Retval_t SymEval::process(SliceNode::Ptr ptr, ptr->ins(begin, end); for (; begin != end; ++begin) { - SliceEdge::Ptr edge = boost::static_pointer_cast(*begin); - SliceNode::Ptr source = boost::static_pointer_cast(edge->source()); + SliceEdge::Ptr edge = dyncompat::static_pointer_cast(*begin); + SliceNode::Ptr source = dyncompat::static_pointer_cast(edge->source()); // Skip this one to break a cycle. if (skipEdges.find(edge) != skipEdges.end()) { @@ -588,7 +635,7 @@ SymEval::Retval_t SymEval::process(SliceNode::Ptr ptr, // If not (like this one), add it AST::Ptr ast; - boost::tie(ast, failedTranslation) = SymEval::expand(ptr->assign()); + std::tie(ast, failedTranslation) = SymEval::expand(ptr->assign()); // expand_cerr << "\t ... resulting in " << dbase.format() << endl; // We have an AST. Now substitute in all of its predecessors. diff --git a/dataflowAPI/src/SymEvalPolicy.C b/dataflowAPI/src/SymEvalPolicy.C index 8230d591be..3aa5351c0a 100644 --- a/dataflowAPI/src/SymEvalPolicy.C +++ b/dataflowAPI/src/SymEvalPolicy.C @@ -29,7 +29,11 @@ */ #include "SymEvalPolicy.h" -#include "dyn_regs.h" +#include "registers/x86_regs.h" +#include "registers/x86_64_regs.h" +#include "registers/ppc32_regs.h" +#include "registers/ppc64_regs.h" + using namespace Dyninst; using namespace Dyninst::DataflowAPI; @@ -49,20 +53,20 @@ SymEvalPolicy::SymEvalPolicy(Result_t &r, // We also need to build aaMap FTW!!! for (Result_t::iterator iter = r.begin(); iter != r.end(); ++iter) { - Assignment::Ptr a = iter->first; + Assignment::Ptr ap = iter->first; // For a different instruction... - if (a->addr() != addr) continue; - AbsRegion &o = a->out(); + if (ap->addr() != addr) continue; + AbsRegion &o = ap->out(); if (o.containsOfType(Absloc::Register)) { // We're assuming this is a single register... - //std::cerr << "Marking register " << a << std::endl; - aaMap[o.absloc()] = a; + //std::cerr << "Marking register " << ap << std::endl; + aaMap[o.absloc()] = ap; } else { // Use sufficiently-unique (Heap,0) Absloc // to represent a definition to a memory absloc - aaMap[Absloc(0)] = a; + aaMap[Absloc(0)] = ap; } } } @@ -259,20 +263,20 @@ SymEvalPolicy_64::SymEvalPolicy_64(Result_t &r, // We also need to build aaMap FTW!!! for (Result_t::iterator iter = r.begin(); iter != r.end(); ++iter) { - Assignment::Ptr a = iter->first; + Assignment::Ptr ap = iter->first; // For a different instruction... - if (a->addr() != addr) continue; - AbsRegion &o = a->out(); + if (ap->addr() != addr) continue; + AbsRegion &o = ap->out(); if (o.containsOfType(Absloc::Register)) { // We're assuming this is a single register... //std::cerr << "Marking register " << a << std::endl; - aaMap[o.absloc()] = a; + aaMap[o.absloc()] = ap; } else { // Use sufficiently-unique (Heap,0) Absloc // to represent a definition to a memory absloc - aaMap[Absloc(0)] = a; + aaMap[Absloc(0)] = ap; } } } @@ -448,10 +452,16 @@ Absloc SymEvalPolicy_64::convert(X86Flag f) switch (f) { case x86_flag_cf: return Absloc(x86_64::cf); + case x86_flag_1: + return Absloc(x86_64::flag1); case x86_flag_pf: return Absloc(x86_64::pf); + case x86_flag_3: + return Absloc(x86_64::flag3); case x86_flag_af: return Absloc(x86_64::af); + case x86_flag_5: + return Absloc(x86_64::flag5); case x86_flag_zf: return Absloc(x86_64::zf); case x86_flag_sf: @@ -464,8 +474,14 @@ Absloc SymEvalPolicy_64::convert(X86Flag f) return Absloc(x86_64::df); case x86_flag_of: return Absloc(x86_64::of); + case x86_flag_iopl0: + return Absloc(x86_64::FLAGC); + case x86_flag_iopl1: + return Absloc(x86_64::FLAGD); case x86_flag_nt: return Absloc(x86_64::nt_); + case x86_flag_15: + return Absloc(x86_64::FLAGF); default: assert(0); return Absloc(); diff --git a/dataflowAPI/src/SymEvalPolicy.h b/dataflowAPI/src/SymEvalPolicy.h index 06836aa007..d5ea6989f1 100644 --- a/dataflowAPI/src/SymEvalPolicy.h +++ b/dataflowAPI/src/SymEvalPolicy.h @@ -56,15 +56,14 @@ #include "Operation_impl.h" #include "../h/Absloc.h" +#include +#include +#include #include #include #include -#if defined(_MSC_VER) -#include "external/stdint-win.h" -#else #include -#endif #include "../rose/SgAsmx86Instruction.h" @@ -96,11 +95,11 @@ struct Handle { AST::Ptr *v_; Handle() : v_(NULL) { assert(0); - }; + } Handle(AST::Ptr v) { assert(v); v_ = new AST::Ptr(v); - }; + } Handle(const Handle &rhs) { v_ = new AST::Ptr(rhs.var()); } @@ -109,7 +108,7 @@ struct Handle { v_ = new AST::Ptr(rhs.var()); return *this; } - ~Handle() { if (v_) delete v_; }; + ~Handle() { if (v_) delete v_; } template bool operator==(const Handle &rhs) { @@ -133,7 +132,7 @@ struct Handle { Dyninst::Architecture a, InstructionAPI::Instruction insn); - ~SymEvalPolicy() {}; + ~SymEvalPolicy() {} void undefinedInstruction(SgAsmx86Instruction *); void undefinedInstruction(SgAsmPowerpcInstruction *); @@ -202,7 +201,7 @@ struct Handle { } void systemCall(unsigned char value) { - fprintf(stderr, "WARNING: syscall %d detected; unhandled by semantics!\n", (unsigned int)(value)); + fprintf(stderr, "WARNING: syscall %u detected; unhandled by semantics!\n", (unsigned int)(value)); } void writeSegreg(X86SegmentRegister r, Handle<16> value) { std::map::iterator i = aaMap.find(convert(r)); @@ -246,32 +245,32 @@ struct Handle { template Handle readMemory(X86SegmentRegister /*segreg*/, - Handle<32> addr, + Handle<32> addr_, Handle<1> cond) { if (cond == true_()) { return Handle(getUnaryAST(ROSEOperation::derefOp, - addr.var(), + addr_.var(), Len)); } else { return Handle(getBinaryAST(ROSEOperation::derefOp, - addr.var(), + addr_.var(), cond.var(), Len)); } } template - Handle readMemory(Handle<32> addr, + Handle readMemory(Handle<32> addr_, Handle<1> cond) { return Handle(getBinaryAST(ROSEOperation::derefOp, - addr.var(), + addr_.var(), cond.var(), Len)); } template void writeMemory(X86SegmentRegister, - Handle<32> addr, + Handle<32> addr_, Handle data, Handle<32> repeat, Handle<1> cond) { @@ -282,7 +281,7 @@ struct Handle { std::map::iterator i = aaMap.find(Absloc(0)); if (i != aaMap.end()) { - i->second->out().setGenerator(addr.var()); + i->second->out().setGenerator(addr_.var()); i->second->out().setSize(Len); if (cond == true_()) { @@ -300,12 +299,12 @@ struct Handle { } template - void writeMemory(Handle<32> addr, + void writeMemory(Handle<32> addr_, Handle data, Handle<1> cond) { std::map::iterator i = aaMap.find(Absloc(0)); if (i != aaMap.end()) { - i->second->out().setGenerator(addr.var()); + i->second->out().setGenerator(addr_.var()); i->second->out().setSize(Len); if (cond == true_()) { // Thinking about it... I think we avoid the "writeOp" @@ -325,12 +324,12 @@ struct Handle { template void writeMemory(X86SegmentRegister, - Handle<32> addr, + Handle<32> addr_, Handle data, Handle<1> cond) { std::map::iterator i = aaMap.find(Absloc(0)); if (i != aaMap.end()) { - i->second->out().setGenerator(addr.var()); + i->second->out().setGenerator(addr_.var()); i->second->out().setSize(Len); if (cond == true_()) { // Thinking about it... I think we avoid the "writeOp" @@ -549,8 +548,8 @@ struct Handle { // Misc - void hlt() {}; - void interrupt(uint8_t) {}; + void hlt() {} + void interrupt(uint8_t) {} Handle<64> rdtsc() { return number<64>(0); @@ -653,7 +652,7 @@ struct Handle { Dyninst::Architecture a, Dyninst::InstructionAPI::Instruction insn); - ~SymEvalPolicy_64() {}; + ~SymEvalPolicy_64() {} void undefinedInstruction(SgAsmx86Instruction *); void undefinedInstruction(SgAsmPowerpcInstruction *); @@ -722,7 +721,7 @@ struct Handle { } void systemCall(unsigned char value) { - fprintf(stderr, "WARNING: syscall %d detected; unhandled by semantics!\n", (unsigned int)(value)); + fprintf(stderr, "WARNING: syscall %u detected; unhandled by semantics!\n", (unsigned int)(value)); } void writeSegreg(X86SegmentRegister r, Handle<16> value) { std::map::iterator i = aaMap.find(convert(r)); @@ -766,32 +765,32 @@ struct Handle { template Handle readMemory(X86SegmentRegister /*segreg*/, - Handle<64> addr, + Handle<64> addr_, Handle<1> cond) { if (cond == true_()) { return Handle(getUnaryAST(ROSEOperation::derefOp, - addr.var(), + addr_.var(), Len)); } else { return Handle(getBinaryAST(ROSEOperation::derefOp, - addr.var(), + addr_.var(), cond.var(), Len)); } } template - Handle readMemory(Handle<64> addr, + Handle readMemory(Handle<64> addr_, Handle<1> cond) { return Handle(getBinaryAST(ROSEOperation::derefOp, - addr.var(), + addr_.var(), cond.var(), Len)); } template void writeMemory(X86SegmentRegister, - Handle<64> addr, + Handle<64> addr_, Handle data, Handle<64> repeat, Handle<1> cond) { @@ -802,7 +801,7 @@ struct Handle { std::map::iterator i = aaMap.find(Absloc(0)); if (i != aaMap.end()) { - i->second->out().setGenerator(addr.var()); + i->second->out().setGenerator(addr_.var()); i->second->out().setSize(Len); if (cond == true_()) { @@ -820,12 +819,12 @@ struct Handle { } template - void writeMemory(Handle<64> addr, + void writeMemory(Handle<64> addr_, Handle data, Handle<1> cond) { std::map::iterator i = aaMap.find(Absloc(0)); if (i != aaMap.end()) { - i->second->out().setGenerator(addr.var()); + i->second->out().setGenerator(addr_.var()); i->second->out().setSize(Len); if (cond == true_()) { // Thinking about it... I think we avoid the "writeOp" @@ -845,12 +844,12 @@ struct Handle { template void writeMemory(X86SegmentRegister, - Handle<64> addr, + Handle<64> addr_, Handle data, Handle<1> cond) { std::map::iterator i = aaMap.find(Absloc(0)); if (i != aaMap.end()) { - i->second->out().setGenerator(addr.var()); + i->second->out().setGenerator(addr_.var()); i->second->out().setSize(Len); if (cond == true_()) { // Thinking about it... I think we avoid the "writeOp" @@ -1069,8 +1068,8 @@ struct Handle { // Misc - void hlt() {}; - void interrupt(uint8_t) {}; + void hlt() {} + void interrupt(uint8_t) {} Handle<64> rdtsc() { return number<64>(0); @@ -1161,6 +1160,6 @@ struct Handle { return RoseAST::create(ROSEOperation(op, s), a, b, c); } }; -}; -}; +} +} #endif diff --git a/dataflowAPI/src/SymEvalVisitors.h b/dataflowAPI/src/SymEvalVisitors.h index a4ea7113a2..f8c4137e61 100644 --- a/dataflowAPI/src/SymEvalVisitors.h +++ b/dataflowAPI/src/SymEvalVisitors.h @@ -49,7 +49,7 @@ class StackVisitor : public ASTVisitor { ParseAPI::Function *func, StackAnalysis::Height &stackHeight, StackAnalysis::Height &frameHeight) : - addr_(a), func_(func), stack_(stackHeight), frame_(frameHeight) {}; + addr_(a), func_(func), stack_(stackHeight), frame_(frameHeight) {} DATAFLOW_EXPORT virtual AST::Ptr visit(AST *); DATAFLOW_EXPORT virtual AST::Ptr visit(BottomAST *); @@ -57,13 +57,13 @@ class StackVisitor : public ASTVisitor { DATAFLOW_EXPORT virtual AST::Ptr visit(VariableAST *); DATAFLOW_EXPORT virtual AST::Ptr visit(RoseAST *); DATAFLOW_EXPORT virtual AST::Ptr visit(StackAST *); - DATAFLOW_EXPORT virtual ASTPtr visit(InputVariableAST *) {return AST::Ptr();}; - DATAFLOW_EXPORT virtual ASTPtr visit(ReferenceAST *) {return AST::Ptr();}; - DATAFLOW_EXPORT virtual ASTPtr visit(StpAST *) {return AST::Ptr();}; - DATAFLOW_EXPORT virtual ASTPtr visit(YicesAST *) {return AST::Ptr();}; - DATAFLOW_EXPORT virtual ASTPtr visit(SemanticsAST *) {return AST::Ptr();}; + DATAFLOW_EXPORT virtual ASTPtr visit(InputVariableAST *) {return AST::Ptr();} + DATAFLOW_EXPORT virtual ASTPtr visit(ReferenceAST *) {return AST::Ptr();} + DATAFLOW_EXPORT virtual ASTPtr visit(StpAST *) {return AST::Ptr();} + DATAFLOW_EXPORT virtual ASTPtr visit(YicesAST *) {return AST::Ptr();} + DATAFLOW_EXPORT virtual ASTPtr visit(SemanticsAST *) {return AST::Ptr();} - DATAFLOW_EXPORT virtual ~StackVisitor() {}; + DATAFLOW_EXPORT virtual ~StackVisitor() {} private: Address addr_; @@ -75,7 +75,7 @@ class StackVisitor : public ASTVisitor { // Simplify boolean expressions for PPC class BooleanVisitor : public ASTVisitor { public: - BooleanVisitor() {}; + BooleanVisitor() {} DATAFLOW_EXPORT virtual AST::Ptr visit(AST *); DATAFLOW_EXPORT virtual AST::Ptr visit(BottomAST *); @@ -83,19 +83,19 @@ class BooleanVisitor : public ASTVisitor { DATAFLOW_EXPORT virtual AST::Ptr visit(VariableAST *); DATAFLOW_EXPORT virtual AST::Ptr visit(RoseAST *); DATAFLOW_EXPORT virtual AST::Ptr visit(StackAST *); - DATAFLOW_EXPORT virtual ASTPtr visit(InputVariableAST *) {return AST::Ptr();}; - DATAFLOW_EXPORT virtual ASTPtr visit(ReferenceAST *) {return AST::Ptr();}; - DATAFLOW_EXPORT virtual ASTPtr visit(StpAST *) {return AST::Ptr();}; - DATAFLOW_EXPORT virtual ASTPtr visit(YicesAST *) {return AST::Ptr();}; - DATAFLOW_EXPORT virtual ASTPtr visit(SemanticsAST *) {return AST::Ptr();}; + DATAFLOW_EXPORT virtual ASTPtr visit(InputVariableAST *) {return AST::Ptr();} + DATAFLOW_EXPORT virtual ASTPtr visit(ReferenceAST *) {return AST::Ptr();} + DATAFLOW_EXPORT virtual ASTPtr visit(StpAST *) {return AST::Ptr();} + DATAFLOW_EXPORT virtual ASTPtr visit(YicesAST *) {return AST::Ptr();} + DATAFLOW_EXPORT virtual ASTPtr visit(SemanticsAST *) {return AST::Ptr();} - DATAFLOW_EXPORT virtual ~BooleanVisitor() {}; + DATAFLOW_EXPORT virtual ~BooleanVisitor() {} private: }; -}; -}; +} +} #endif diff --git a/dataflowAPI/src/SymbolicExpansion.C b/dataflowAPI/src/SymbolicExpansion.C index 002cf3b246..6ef863e702 100644 --- a/dataflowAPI/src/SymbolicExpansion.C +++ b/dataflowAPI/src/SymbolicExpansion.C @@ -34,13 +34,12 @@ #include "../rose/SgAsmInstruction.h" #include "../rose/SgAsmPowerpcInstruction.h" #include "../rose/SgAsmx86Instruction.h" -#include "../rose/SgAsmAmdgpuVegaInstruction.h" #include "../rose/x86InstructionSemantics.h" #include "../rose/x86_64InstructionSemantics.h" #include "../rose/semantics/DispatcherARM64.h" -#include "../rose/semantics/DispatcherAmdgpuVega.h" +#include "../rose/semantics/DispatcherAMDGPU.h" #include "../rose/semantics/DispatcherPowerpc.h" using namespace Dyninst; @@ -70,7 +69,7 @@ bool SymbolicExpansion::expandX86_64(SgAsmInstruction *rose_insn, bool SymbolicExpansion::expandPPC32(SgAsmInstruction *rose_insn, BaseSemantics::RiscOperatorsPtr ops, - const std::string &insn_dump) { + const std::string &/*insn_dump*/) { SgAsmPowerpcInstruction *insn = static_cast(rose_insn); BaseSemantics::DispatcherPtr cpu = DispatcherPowerpc::instance(ops, 32); @@ -85,7 +84,7 @@ bool SymbolicExpansion::expandPPC32(SgAsmInstruction *rose_insn, } bool SymbolicExpansion::expandPPC64(SgAsmInstruction *rose_insn, BaseSemantics::RiscOperatorsPtr ops, - const std::string &insn_dump) { + const std::string &/*insn_dump*/) { SgAsmPowerpcInstruction *insn = static_cast(rose_insn); BaseSemantics::DispatcherPtr cpu = DispatcherPowerpc::instance(ops, 64); @@ -100,7 +99,7 @@ bool SymbolicExpansion::expandPPC64(SgAsmInstruction *rose_insn, return true; } -bool SymbolicExpansion::expandAarch64(SgAsmInstruction *rose_insn, BaseSemantics::RiscOperatorsPtr ops, const std::string &insn_dump) { +bool SymbolicExpansion::expandAarch64(SgAsmInstruction *rose_insn, BaseSemantics::RiscOperatorsPtr ops, const std::string &/*insn_dump*/) { SgAsmArmv8Instruction *insn = static_cast(rose_insn); BaseSemantics::DispatcherPtr cpu = DispatcherARM64::instance(ops, 64); @@ -114,10 +113,11 @@ bool SymbolicExpansion::expandAarch64(SgAsmInstruction *rose_insn, BaseSemantics return false; } -bool SymbolicExpansion::expandAmdgpuVega(SgAsmInstruction *rose_insn, BaseSemantics::RiscOperatorsPtr ops, const std::string &insn_dump) { - SgAsmAmdgpuVegaInstruction *insn = static_cast(rose_insn); - BaseSemantics::DispatcherPtr cpu = DispatcherAmdgpuVega::instance(ops, 64); +bool SymbolicExpansion::expandAMDGPU(SgAsmInstruction *rose_insn, BaseSemantics::RiscOperatorsPtr ops, const std::string &/*insn_dump*/) { + SgAsmAMDGPUInstruction *insn = static_cast(rose_insn); + + BaseSemantics::DispatcherPtr cpu = DispatcherAMDGPU::instance(ops, 64); try { cpu->processInstruction(insn); diff --git a/dataflowAPI/src/SymbolicExpansion.h b/dataflowAPI/src/SymbolicExpansion.h index 6f351bf753..a41f7d9ae4 100644 --- a/dataflowAPI/src/SymbolicExpansion.h +++ b/dataflowAPI/src/SymbolicExpansion.h @@ -29,6 +29,7 @@ */ #include #include "../rose/semantics/SymEvalSemantics.h" +#include #if !defined(_SYMBOLIC_EXPANSION_H_) #define _SYMBOLIC_EXPANSION_H_ @@ -65,14 +66,15 @@ namespace Dyninst { BaseSemantics::RiscOperatorsPtr ops, const std::string &insn_dump); - static bool expandAmdgpuVega(SgAsmInstruction *rose_insn, + static bool expandAMDGPU(SgAsmInstruction *rose_insn, BaseSemantics::RiscOperatorsPtr ops, const std::string &insn_dump); + }; - }; -}; + } +} #endif diff --git a/dataflowAPI/src/Visitors.C b/dataflowAPI/src/Visitors.C index 6731d44c54..df8c562956 100644 --- a/dataflowAPI/src/Visitors.C +++ b/dataflowAPI/src/Visitors.C @@ -106,12 +106,16 @@ AST::Ptr StackVisitor::visit(RoseAST *r) { ConstantAST::Ptr to = ConstantAST::convert(newKids[2]); ConstantAST::Ptr val = ConstantAST::convert(newKids[0]); - unsigned long mask = 0; - for (uint64_t i = from->val().val; i <= to->val().val; ++i) { - mask |= 1 << i; - } - return ConstantAST::create(Constant(val->val().val & mask, to->val().val - from->val().val)); + auto lowBitPos{from->val().val}; + auto highBitPos{to->val().val}; + uint64_t newValue{val->val().val}; + if(highBitPos < 64) + newValue &= ((1ULL << highBitPos) - 1); // zero highBitPos and higher + newValue >>= lowBitPos; // shift to bit 0, eliminating unwanted low bits + + return ConstantAST::create(Constant(newValue, highBitPos - lowBitPos)); + } return RoseAST::create(r->val(), newKids); diff --git a/dataflowAPI/src/convertOpcodes.C b/dataflowAPI/src/convertOpcodes.C index 6e3d7e5cbe..a853328d9a 100644 --- a/dataflowAPI/src/convertOpcodes.C +++ b/dataflowAPI/src/convertOpcodes.C @@ -32,6 +32,7 @@ //#include "SymEval.h" //#include "SymEvalPolicy.h" +#include #include "RoseInsnFactory.h" #include "../rose/RegisterDescriptor.h" @@ -102,17 +103,15 @@ X86InstructionKind RoseInsnX86Factory::convertKind(entryID opcode, prefixEntryID return x86_jle; case e_jmp: return x86_jmp; - case e_jmpe: - return x86_jmpe; - case e_jnb: + case e_jae: return x86_jae; case e_jnb_jae_j: return x86_jae; - case e_jnbe: + case e_ja: return x86_ja; - case e_jnl: + case e_jge: return x86_jge; - case e_jnle: + case e_jg: return x86_jg; case e_jno: return x86_jno; @@ -120,7 +119,7 @@ X86InstructionKind RoseInsnX86Factory::convertKind(entryID opcode, prefixEntryID return x86_jpo; case e_jns: return x86_jns; - case e_jnz: + case e_jne: return x86_jne; case e_jo: return x86_jo; @@ -128,13 +127,13 @@ X86InstructionKind RoseInsnX86Factory::convertKind(entryID opcode, prefixEntryID return x86_jpe; case e_js: return x86_js; - case e_jz: + case e_je: return x86_je; case e_loop: return x86_loop; case e_loope: return x86_loopz; - case e_loopn: + case e_loopne: return x86_loopnz; case e_call: return x86_call; @@ -152,9 +151,9 @@ X86InstructionKind RoseInsnX86Factory::convertKind(entryID opcode, prefixEntryID return x86_cmpss; case e_cmpsw: return x86_cmpsw; - case e_cmpxch: + case e_cmpxchg: return x86_cmpxchg; - case e_cmpxch8b: + case e_cmpxchg8b: return x86_cmpxchg8b; case e_ret_far: return x86_retf; @@ -162,13 +161,13 @@ X86InstructionKind RoseInsnX86Factory::convertKind(entryID opcode, prefixEntryID return x86_ret; case e_prefetch: return x86_prefetch; - case e_prefetchNTA: + case e_prefetchnta: return x86_prefetchnta; - case e_prefetchT0: + case e_prefetcht0: return x86_prefetcht0; - case e_prefetchT1: + case e_prefetcht1: return x86_prefetcht1; - case e_prefetchT2: + case e_prefetcht2: return x86_prefetcht2; case e_prefetch_w: return x86_prefetchw; @@ -248,19 +247,19 @@ X86InstructionKind RoseInsnX86Factory::convertKind(entryID opcode, prefixEntryID return x86_cmovbe; case e_cmove: return x86_cmove; - case e_cmovnae: + case e_cmovb: return x86_cmovb; - case e_cmovnb: + case e_cmovae: return x86_cmovae; - case e_cmovnbe: + case e_cmova: return x86_cmova; case e_cmovne: return x86_cmovne; - case e_cmovng: + case e_cmovle: return x86_cmovle; - case e_cmovnge: + case e_cmovl: return x86_cmovl; - case e_cmovnl: + case e_cmovge: return x86_cmovge; case e_cmovno: return x86_cmovno; @@ -268,9 +267,9 @@ X86InstructionKind RoseInsnX86Factory::convertKind(entryID opcode, prefixEntryID return x86_cmovns; case e_cmovo: return x86_cmovo; - case e_cmovpe: + case e_cmovp: return x86_cmovpe; - case e_cmovpo: + case e_cmovnp: return x86_cmovpo; case e_cmovs: return x86_cmovs; @@ -324,8 +323,6 @@ X86InstructionKind RoseInsnX86Factory::convertKind(entryID opcode, prefixEntryID return x86_cvttsd2si; case e_cvttss2si: return x86_cvttss2si; - case e_cwd: - return x86_cwd; case e_cwde: return x86_cwde; case e_daa: @@ -402,17 +399,17 @@ X86InstructionKind RoseInsnX86Factory::convertKind(entryID opcode, prefixEntryID return x86_fnop; case e_frstor: return x86_frstor; - case e_fsave: + case e_fnsave: return x86_fnsave; case e_fst: return x86_fst; - case e_fstcw: + case e_fnstcw: return x86_fnstcw; - case e_fstenv: + case e_fnstenv: return x86_fnstenv; case e_fstp: return x86_fstp; - case e_fstsw: + case e_fnstsw: return x86_fnstsw; case e_fsub: return x86_fsub; @@ -528,8 +525,6 @@ X86InstructionKind RoseInsnX86Factory::convertKind(entryID opcode, prefixEntryID return x86_minsd; case e_minss: return x86_minss; - case e_mmxud: - return x86_unknown_instruction; case e_mov: return x86_mov; case e_movapd: @@ -668,7 +663,7 @@ X86InstructionKind RoseInsnX86Factory::convertKind(entryID opcode, prefixEntryID return x86_pcmpeqd; case e_pcmpeqw: return x86_pcmpeqw; - case e_pcmpgdt: + case e_pcmpgtd: return x86_pcmpgtd; case e_pcmpgtb: return x86_pcmpgtb; @@ -700,9 +695,9 @@ X86InstructionKind RoseInsnX86Factory::convertKind(entryID opcode, prefixEntryID return x86_pmuludq; case e_pop: return x86_pop; - case e_popa: + case e_popal: return x86_popa; - case e_popad: + case e_popaw: return x86_popad; case e_popf: return x86_popf; @@ -760,28 +755,24 @@ X86InstructionKind RoseInsnX86Factory::convertKind(entryID opcode, prefixEntryID return x86_punpckhbw; case e_punpckhdq: return x86_punpckhdq; - case e_punpckhqd: - return x86_punpckhdq; + case e_punpckhqdq: + return x86_punpckhqdq; case e_punpckhwd: return x86_punpckhwd; case e_punpcklbw: return x86_punpcklbw; - case e_punpcklqd: + case e_punpckldq: return x86_punpckldq; - case e_punpcklqld: + case e_punpcklqdq: return x86_punpcklqdq; case e_punpcklwd: return x86_punpcklwd; case e_push: return x86_push; - case e_pusha: - return x86_pusha; - case e_pushad: + case e_pushal: return x86_pushad; case e_pushf: return x86_pushf; - case e_pushfd: - return x86_pushfd; case e_pxor: return x86_pxor; case e_rcl: @@ -830,13 +821,13 @@ X86InstructionKind RoseInsnX86Factory::convertKind(entryID opcode, prefixEntryID return x86_setl; case e_setle: return x86_setle; - case e_setnb: + case e_setae: return x86_setae; - case e_setnbe: + case e_seta: return x86_seta; - case e_setnl: + case e_setge: return x86_setge; - case e_setnle: + case e_setg: return x86_setg; case e_setno: return x86_setno; @@ -844,7 +835,7 @@ X86InstructionKind RoseInsnX86Factory::convertKind(entryID opcode, prefixEntryID return x86_setpo; case e_setns: return x86_setns; - case e_setnz: + case e_setne: return x86_setne; case e_seto: return x86_seto; @@ -852,13 +843,13 @@ X86InstructionKind RoseInsnX86Factory::convertKind(entryID opcode, prefixEntryID return x86_setpe; case e_sets: return x86_sets; - case e_setz: + case e_sete: return x86_sete; case e_sfence: return x86_sfence; case e_sgdt: return x86_sgdt; - case e_shl_sal: + case e_shl: return x86_shl; case e_shld: return x86_shld; @@ -924,7 +915,7 @@ X86InstructionKind RoseInsnX86Factory::convertKind(entryID opcode, prefixEntryID return x86_ucomisd; case e_ucomiss: return x86_ucomiss; - case e_ud: + case e_ud0: return x86_unknown_instruction; case e_ud2: return x86_ud2; @@ -956,7 +947,7 @@ X86InstructionKind RoseInsnX86Factory::convertKind(entryID opcode, prefixEntryID return x86_xadd; case e_xchg: return x86_xchg; - case e_xlat: + case e_xlatb: return x86_xlatb; case e_xor: return x86_xor; @@ -2030,14 +2021,28 @@ ARMv8InstructionKind RoseInsnArmv8Factory::convertKind(entryID opcode) { } } // TODO: + // This function should just translate each instructionAPI opcode to a rose equivalent version -AmdgpuVegaInstructionKind RoseInsnAmdgpuVegaFactory::convertKind(entryID opcode) { +AMDGPUInstructionKind RoseInsnAMDGPUFactory::convertKind(entryID opcode) { switch(opcode) { - case amdgpu_op_s_setpc_b64 : return rose_amdgpu_op_s_setpc_b64; - case amdgpu_op_s_swappc_b64 : return rose_amdgpu_op_s_swappc_b64; - case amdgpu_op_s_getpc_b64 : return rose_amdgpu_op_s_getpc_b64; - case amdgpu_op_s_add_u32 : return rose_amdgpu_op_s_add_u32; - case amdgpu_op_s_addc_u32 : return rose_amdgpu_op_s_addc_u32; + case amdgpu_gfx908_op_S_SETPC_B64 : return rose_amdgpu_op_s_setpc_b64; + case amdgpu_gfx908_op_S_SWAPPC_B64 : return rose_amdgpu_op_s_swappc_b64; + case amdgpu_gfx908_op_S_GETPC_B64 : return rose_amdgpu_op_s_getpc_b64; + case amdgpu_gfx908_op_S_ADD_U32 : return rose_amdgpu_op_s_add_u32; + case amdgpu_gfx908_op_S_ADDC_U32 : return rose_amdgpu_op_s_addc_u32; + + case amdgpu_gfx90a_op_S_SETPC_B64 : return rose_amdgpu_op_s_setpc_b64; + case amdgpu_gfx90a_op_S_SWAPPC_B64 : return rose_amdgpu_op_s_swappc_b64; + case amdgpu_gfx90a_op_S_GETPC_B64 : return rose_amdgpu_op_s_getpc_b64; + case amdgpu_gfx90a_op_S_ADD_U32 : return rose_amdgpu_op_s_add_u32; + case amdgpu_gfx90a_op_S_ADDC_U32 : return rose_amdgpu_op_s_addc_u32; + + case amdgpu_gfx940_op_S_SETPC_B64 : return rose_amdgpu_op_s_setpc_b64; + case amdgpu_gfx940_op_S_SWAPPC_B64 : return rose_amdgpu_op_s_swappc_b64; + case amdgpu_gfx940_op_S_GETPC_B64 : return rose_amdgpu_op_s_getpc_b64; + case amdgpu_gfx940_op_S_ADD_U32 : return rose_amdgpu_op_s_add_u32; + case amdgpu_gfx940_op_S_ADDC_U32 : return rose_amdgpu_op_s_addc_u32; + default: return rose_amdgpu_op_INVALID; } } diff --git a/dataflowAPI/src/debug_dataflow.C b/dataflowAPI/src/debug_dataflow.C index 35a17b4c80..dbfd47f143 100644 --- a/dataflowAPI/src/debug_dataflow.C +++ b/dataflowAPI/src/debug_dataflow.C @@ -57,10 +57,6 @@ static int check_debug_flag(int &flag) { static std::once_flag initialized; -#if defined(_MSC_VER) -#pragma warning(push) -#pragma warning(disable:4996) -#endif std::call_once(initialized, []() { @@ -91,10 +87,6 @@ static int check_debug_flag(int &flag) }); -#if defined(_MSC_VER) -#pragma warning(pop) -#endif - return flag; } diff --git a/dataflowAPI/src/debug_dataflow.h b/dataflowAPI/src/debug_dataflow.h index 0d993e2703..0c069f8daa 100644 --- a/dataflowAPI/src/debug_dataflow.h +++ b/dataflowAPI/src/debug_dataflow.h @@ -32,6 +32,7 @@ #define _DATAFLOW_DEBUG_H_ #include +#include "compiler_annotations.h" extern int df_debug_slicing_on(); extern int df_debug_stackanalysis_on(); @@ -45,29 +46,25 @@ extern int df_debug_liveness_on(); #define expand_cerr if (df_debug_expand_on()) cerr #define liveness_cerr if (df_debug_liveness_on()) cerr -extern int slicing_printf_int(const char *format, ...); -extern int stackanalysis_printf_int(const char *format, ...); -extern int convert_printf_int(const char *format, ...); -extern int expand_printf_int(const char *format, ...); -extern int liveness_printf_int(const char *format, ...); +extern int slicing_printf_int(const char *format, ...) + DYNINST_PRINTF_ANNOTATION(1, 2); +extern int stackanalysis_printf_int(const char *format, ...) + DYNINST_PRINTF_ANNOTATION(1, 2); +extern int convert_printf_int(const char *format, ...) + DYNINST_PRINTF_ANNOTATION(1, 2); +extern int expand_printf_int(const char *format, ...) + DYNINST_PRINTF_ANNOTATION(1, 2); +extern int liveness_printf_int(const char *format, ...) + DYNINST_PRINTF_ANNOTATION(1, 2); -#if defined(__GNUC__) -#define slicing_printf(format, args...) do {if (df_debug_slicing_on()) slicing_printf_int(format, ## args); } while(0) -#define stackanalysis_printf(format, args...) do {if (df_debug_stackanalysis_on()) stackanalysis_printf_int(format, ## args); } while(0) -#define convert_printf(format, args...) do {if (df_debug_convert_on()) convert_printf_int(format, ## args); } while(0) -#define expand_printf(format, args...) do {if (df_debug_expand_on()) expand_printf_int(format, ## args); } while(0) -#define liveness_printf(format, args...) do {if (df_debug_liveness_on()) liveness_printf_int(format, ## args); } while(0) -#else -// Non-GCC doesn't have the ## macro -#define slicing_printf slicing_printf_int -#define stackanalysis_printf stackanalysis_printf_int -#define convert_printf convert_printf_int -#define expand_printf expand_printf_int -#define liveness_printf liveness_printf_int +#define dataflow_debug_printf(debug_sys, ...) do {if (df_debug_##debug_sys##_on()) debug_sys##_printf_int(__VA_ARGS__); } while(0) - -#endif +#define slicing_printf(...) dataflow_debug_printf(slicing, __VA_ARGS__) +#define stackanalysis_printf(...) dataflow_debug_printf(stackanalysis, __VA_ARGS__) +#define convert_printf(...) dataflow_debug_printf(convert, __VA_ARGS__) +#define expand_printf(...) dataflow_debug_printf(expand, __VA_ARGS__) +#define liveness_printf(...) dataflow_debug_printf(liveness, __VA_ARGS__) // And initialization diff --git a/dataflowAPI/src/liveness.C b/dataflowAPI/src/liveness.C index a93b65630d..cc91ffe284 100644 --- a/dataflowAPI/src/liveness.C +++ b/dataflowAPI/src/liveness.C @@ -30,16 +30,20 @@ // $Id: liveness.C,v 1.12 2008/09/04 21:06:20 bill Exp $ +#include #include "debug_dataflow.h" #include "parseAPI/h/CFG.h" #include "parseAPI/h/Location.h" #include "instructionAPI/h/InstructionDecoder.h" #include "instructionAPI/h/Register.h" #include "instructionAPI/h/Instruction.h" - +#include "registers/x86_regs.h" +#include "registers/x86_64_regs.h" #include "dataflowAPI/h/liveness.h" #include "dataflowAPI/h/ABI.h" -#include +#include +#include "instructionAPI/h/syscalls.h" +#include "instructionAPI/h/interrupts.h" std::string regs1 = " ttttttttddddddddcccccccmxxxxxxxxxxxxxxxxgf rrrrrrrrrrrrrrrrr"; std::string regs2 = " rrrrrrrrrrrrrrrrrrrrrrrm1111110000000000ssoscgfedrnoditszapci11111100dsbsbdca"; @@ -102,19 +106,19 @@ const bitArray& LivenessAnalyzer::getLivenessOut(Block *block, bitArray &allRegs // OUT(X) = UNION(IN(Y)) for all successors Y of X - boost::lock_guard g(*block); + dyncompat::lock_guard g(*block); const Block::edgelist & target_edges = block -> targets(); liveness_cerr << "getLivenessOut for block [" << hex << block->start() << "," << block->end() << "]" << dec << endl; - std::for_each(boost::make_filter_iterator(epred, target_edges.begin(), target_edges.end()), - boost::make_filter_iterator(epred, target_edges.end(), target_edges.end()), - boost::bind(&LivenessAnalyzer::processEdgeLiveness, + std::for_each(dyncompat::make_filter_iterator(epred, target_edges.begin(), target_edges.end()), + dyncompat::make_filter_iterator(epred, target_edges.end(), target_edges.end()), + dyncompat::bind(&LivenessAnalyzer::processEdgeLiveness, this, - boost::placeholders::_1, - boost::ref(data), + dyncompat::placeholders::_1, + dyncompat::ref(data), block, - boost::ref(allRegsDefined))); + dyncompat::ref(allRegsDefined))); liveness_cerr << " Returning liveness for out " << endl; liveness_cerr << " " << data.out << endl; @@ -545,30 +549,9 @@ ReadWriteInfo LivenessAnalyzer::calcRWSets(Instruction curInsn, Block *blk, Addr break; default: { - bool isInterrupt = false; - bool isSyscall = false; - - - if ((curInsn.getOperation().getID() == e_int) || - (curInsn.getOperation().getID() == e_int3)) { - isInterrupt = true; - } - static RegisterAST::Ptr gs(new RegisterAST(x86::gs)); - if (((curInsn.getOperation().getID() == e_call) && - /*(curInsn()->getOperation().isRead(gs))) ||*/ - (curInsn.getOperand(0).format(curInsn.getArch()) == "16")) || - (curInsn.getOperation().getID() == e_syscall) || - (curInsn.getOperation().getID() == e_int) || - (curInsn.getOperation().getID() == power_op_sc)) { - isSyscall = true; - } + const bool isInterrupt = Dyninst::InstructionAPI::isSoftwareInterrupt(curInsn); + const bool isSyscall = Dyninst::InstructionAPI::isSystemCall(curInsn); - if (curInsn.getOperation().getID() == power_op_svcs) { - isSyscall = true; - } - if (curInsn.getOperation().getID() == aarch64_op_svc) { - isSyscall = true; - } if (isInterrupt || isSyscall) { ret.read |= (abi->getSyscallReadRegisters()); ret.written |= (abi->getSyscallWrittenRegisters()); @@ -587,7 +570,7 @@ void *LivenessAnalyzer::getPtrToInstruction(Block *block, Address addr) const{ } bool LivenessAnalyzer::isExitBlock(Block *block) { - boost::lock_guard g(*block); + dyncompat::lock_guard g(*block); const Block::edgelist & trgs = block->targets(); bool interprocEdge = false; @@ -622,9 +605,12 @@ void LivenessAnalyzer::clean(Function *func){ } bool LivenessAnalyzer::isMMX(MachRegister machReg){ - if ((machReg.val() & Arch_x86) == Arch_x86 || (machReg.val() & Arch_x86_64) == Arch_x86_64){ - assert( ((machReg.val() & x86::MMX) == x86::MMX) == ((machReg.val() & x86_64::MMX) == x86_64::MMX) ); - return (machReg.val() & x86::MMX) == x86::MMX; + auto const arch = machReg.getArchitecture(); + if (arch == Arch_x86) { + return machReg.regClass() == x86::MMX; + } + if (arch == Arch_x86_64) { + return machReg.regClass() == x86_64::MMX; } return false; } diff --git a/dataflowAPI/src/slicing.C b/dataflowAPI/src/slicing.C index 1eef918a25..08ae84f46e 100644 --- a/dataflowAPI/src/slicing.C +++ b/dataflowAPI/src/slicing.C @@ -27,6 +27,7 @@ * License along with this library; if not, write to the Free Software * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include #include #include @@ -40,7 +41,8 @@ #include "dataflowAPI/h/slicing.h" #include "ABI.h" #include "bitArray.h" - +#include "registers/x86_regs.h" +#include "registers/x86_64_regs.h" #include "common/h/Graph.h" #include "instructionAPI/h/Instruction.h" @@ -176,10 +178,10 @@ Slicer::sliceInternal( if(dir == forward) { slicing_printf("Inserting entry node %p/%s\n", - aP.get(),aP->format().c_str()); + static_cast(aP.get()),aP->format().c_str()); } else { slicing_printf("Inserting exit node %p/%s\n", - aP.get(),aP->format().c_str()); + static_cast(aP.get()),aP->format().c_str()); } // add to graph @@ -218,7 +220,7 @@ void Slicer::sliceInternalAux( vector nextCands; DefCache& mydefs = singleCache[cand.addr()]; - slicing_printf("\tslicing from %lx, currently watching %ld regions\n", + slicing_printf("\tslicing from %lx, currently watching %lu regions\n", cand.addr(),cand.active.size()); // Find assignments at this point that affect the active @@ -228,7 +230,7 @@ void Slicer::sliceInternalAux( if (!skip) { if (!updateAndLink(g,dir,cand, mydefs, p)) return; - slicing_printf("\t\tfinished udpateAndLink, active.size: %ld\n", + slicing_printf("\t\tfinished udpateAndLink, active.size: %lu\n", cand.active.size()); // If the analysis that uses the slicing can stop for // analysis specifc reasons on a path, the cache @@ -251,7 +253,7 @@ void Slicer::sliceInternalAux( widenAll(g,dir,cand); } - slicing_printf("\t\tgetNextCandidates returned %ld, success: %d\n", + slicing_printf("\t\tgetNextCandidates returned %lu, success: %d\n", nextCands.size(),success); for (unsigned i=0; i < nextCands.size(); ++i) { @@ -263,7 +265,7 @@ void Slicer::sliceInternalAux( CacheEdge e(cand.addr(),f.addr()); - slicing_printf("\t\t candidate %d is at %lx, %ld active\n", + slicing_printf("\t\t candidate %u is at %lx, %lu active\n", i,f.addr(),f.active.size()); if (visited.find(e) != visited.end()) { @@ -780,8 +782,7 @@ Slicer::getPredecessors( //a predicate for each active abstract region to see whether //we should continue bool cont = false; - SliceFrame::ActiveMap::const_iterator ait = cand.active.begin(); - for( ; ait != cand.active.end(); ++ait) { + for (SliceFrame::ActiveMap::const_iterator ait = cand.active.begin(); ait != cand.active.end(); ++ait) { bool add = p.addPredecessor((*ait).first); if(add) { if (nf == NULL) { @@ -799,8 +800,7 @@ Slicer::getPredecessors( nf->loc.addr()); slicing_printf("\t\t\t\t Current regions are:\n"); if(df_debug_slicing_on()) { - SliceFrame::ActiveMap::const_iterator ait = cand.active.begin(); - for( ; ait != cand.active.end(); ++ait) { + for (SliceFrame::ActiveMap::const_iterator ait = cand.active.begin(); ait != cand.active.end(); ++ait) { slicing_printf("\t\t\t\t%s\n", (*ait).first.format().c_str()); @@ -1079,7 +1079,7 @@ Slicer::handleReturnDetails( assert(!cur.con.empty()); - slicing_printf("\t%s, \n", + slicing_printf("\t%s (%d), \n", (cur.con.front().func ? cur.con.front().func->name().c_str() : "NULL"), cur.con.front().stackDepth); @@ -1376,11 +1376,11 @@ Slicer::Slicer(Assignment::Ptr a, ParseAPI::Function *func, bool cache, bool stackAnalysis) : + insnCache_(new InsnCache()), + own_insnCache(true), a_(a), b_(block), f_(func), - insnCache_(new InsnCache()), - own_insnCache(true), converter(new AssignmentConverter(cache, stackAnalysis)), own_converter(true) { @@ -1390,11 +1390,11 @@ Slicer::Slicer(Assignment::Ptr a, ParseAPI::Block *block, ParseAPI::Function *func, AssignmentConverter* ac): + insnCache_(new InsnCache()), + own_insnCache(true), a_(a), b_(block), f_(func), - insnCache_(new InsnCache()), - own_insnCache(true), converter(ac), own_converter(false) { @@ -1405,11 +1405,11 @@ Slicer::Slicer(Assignment::Ptr a, ParseAPI::Function *func, AssignmentConverter* ac, InsnCache* c): + insnCache_(c), + own_insnCache(false), a_(a), b_(block), f_(func), - insnCache_(c), - own_insnCache(false), converter(ac), own_converter(false) { @@ -1479,7 +1479,7 @@ void Slicer::pushContext(Context &context, << endl; context.push_front(ContextElement(callee, stackDepth)); -}; +} void Slicer::popContext(Context &context) { context.pop_front(); @@ -1750,7 +1750,7 @@ void Slicer::cleanGraph(Graph::Ptr ret) { expand_cerr << "NodeIterator in cleanGraph: " << (*nbegin)->format() << endl; numNodes++; SliceNode::Ptr foozle = - boost::dynamic_pointer_cast(*nbegin); + dyncompat::dynamic_pointer_cast(*nbegin); //cerr << "Checking " << foozle << "/" << foozle->format() << endl; if ((*nbegin)->hasOutEdges()) { slicing_cerr << "\t has out edges, leaving in" << endl; @@ -1822,7 +1822,7 @@ ParseAPI::Block *Slicer::getBlock(ParseAPI::Edge *e, bool Slicer::isWidenNode(Node::Ptr n) { SliceNode::Ptr foozle = - boost::dynamic_pointer_cast(n); + dyncompat::dynamic_pointer_cast(n); if (!foozle) return false; if (!foozle->assign()) return true; return false; diff --git a/dataflowAPI/src/stackanalysis.C b/dataflowAPI/src/stackanalysis.C index 2ba8d6e103..65cace253c 100644 --- a/dataflowAPI/src/stackanalysis.C +++ b/dataflowAPI/src/stackanalysis.C @@ -28,9 +28,10 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include "stackanalysis.h" -#include +#include #include #include #include @@ -45,10 +46,15 @@ #include "instructionAPI/h/Result.h" #include "parseAPI/h/CFG.h" #include "parseAPI/h/CodeObject.h" +#include "common/h/compiler_diagnostics.h" #include "ABI.h" #include "Annotatable.h" #include "debug_dataflow.h" +#include "registers/x86_regs.h" +#include "registers/x86_64_regs.h" +#include "registers/ppc32_regs.h" +#include "registers/ppc64_regs.h" using namespace std; using namespace Dyninst; @@ -60,6 +66,8 @@ const StackAnalysis::Height StackAnalysis::Height::bottom( const StackAnalysis::Height StackAnalysis::Height::top( StackAnalysis::Height::uninitialized, StackAnalysis::Height::TOP); +namespace +{ AnnotationClass Stack_Anno_Intervals(std::string("Stack_Anno_Intervals"), NULL); AnnotationClass @@ -68,6 +76,7 @@ AnnotationClass Stack_Anno_Insn_Effects(std::string("Stack_Anno_Insn_Effects"), NULL); AnnotationClass Stack_Anno_Call_Effects(std::string("Stack_Anno_Call_Effects"), NULL); +} template class std::list; template class std::map; @@ -262,13 +271,13 @@ void StackAnalysis::summarizeBlocks(bool verbose) { } // Add blocks reachable from this one to the work stack - boost::lock_guard g(*block); + dyncompat::lock_guard g(*block); const Block::edgelist &targs = block->targets(); std::for_each( - boost::make_filter_iterator(epred, targs.begin(), targs.end()), - boost::make_filter_iterator(epred, targs.end(), targs.end()), - boost::bind(add_target_exclude, boost::ref(workstack), - boost::ref(doneSet), boost::placeholders::_1) + dyncompat::make_filter_iterator(epred, targs.begin(), targs.end()), + dyncompat::make_filter_iterator(epred, targs.end(), targs.end()), + dyncompat::bind(add_target_exclude, dyncompat::ref(workstack), + dyncompat::ref(doneSet), dyncompat::placeholders::_1) ); } } @@ -302,7 +311,7 @@ void StackAnalysis::fixpoint(bool verbose) { } } else { if (verbose) { - stackanalysis_printf("\t Calculating meet with block [%x-%x]\n", + stackanalysis_printf("\t Calculating meet with block [%lx-%lx]\n", block->start(), block->lastInsnAddr()); } meetInputs(block, blockInputs[block], input); @@ -337,13 +346,13 @@ void StackAnalysis::fixpoint(bool verbose) { } // Step 4: push all children on the worklist. - boost::lock_guard g(*block); + dyncompat::lock_guard g(*block); const Block::edgelist &outEdges = block->targets(); std::for_each( - boost::make_filter_iterator(epred2, outEdges.begin(), outEdges.end()), - boost::make_filter_iterator(epred2, outEdges.end(), outEdges.end()), - boost::bind(add_target_list_exclude, boost::ref(worklist), - boost::ref(workSet), boost::placeholders::_1) + dyncompat::make_filter_iterator(epred2, outEdges.begin(), outEdges.end()), + dyncompat::make_filter_iterator(epred2, outEdges.end(), outEdges.end()), + dyncompat::bind(add_target_list_exclude, dyncompat::ref(worklist), + dyncompat::ref(workSet), dyncompat::placeholders::_1) ); firstBlock = false; @@ -365,7 +374,7 @@ void getRetAndTailCallBlocks(Function *func, std::set &retBlocks) { Block *currBlock = workstack.top(); workstack.pop(); - boost::lock_guard g(*currBlock); + dyncompat::lock_guard g(*currBlock); const Block::edgelist &targs = currBlock->targets(); for (auto iter = targs.begin(); iter != targs.end(); iter++) { Edge *currEdge = *iter; @@ -376,14 +385,14 @@ void getRetAndTailCallBlocks(Function *func, std::set &retBlocks) { } std::for_each( - boost::make_filter_iterator(epred, targs.begin(), targs.end()), - boost::make_filter_iterator(epred, targs.end(), targs.end()), - boost::bind(add_target_exclude, boost::ref(workstack), - boost::ref(doneSet), boost::placeholders::_1) + dyncompat::make_filter_iterator(epred, targs.begin(), targs.end()), + dyncompat::make_filter_iterator(epred, targs.end(), targs.end()), + dyncompat::bind(add_target_exclude, dyncompat::ref(workstack), + dyncompat::ref(doneSet), dyncompat::placeholders::_1) ); } } -}; // namespace +} // namespace // Looks for return edges in the function, following tail calls if necessary. @@ -492,13 +501,13 @@ void StackAnalysis::summaryFixpoint() { (*blockEffects)[block].accumulate(input, blockSummaryOutputs[block]); // Step 4: push all children on the worklist. - boost::lock_guard g(*block); + dyncompat::lock_guard g(*block); const Block::edgelist &outEdges = block->targets(); std::for_each( - boost::make_filter_iterator(epred2, outEdges.begin(), outEdges.end()), - boost::make_filter_iterator(epred2, outEdges.end(), outEdges.end()), - boost::bind(add_target, boost::ref(worklist), boost::placeholders::_1) + dyncompat::make_filter_iterator(epred2, outEdges.begin(), outEdges.end()), + dyncompat::make_filter_iterator(epred2, outEdges.end(), outEdges.end()), + dyncompat::bind(add_target, dyncompat::ref(worklist), dyncompat::placeholders::_1) ); firstBlock = false; @@ -585,7 +594,7 @@ void StackAnalysis::summarize() { Block *block = bIter->first; for (auto aIter = (*intervals_)[block].begin(); aIter != (*intervals_)[block].end(); aIter++) { - Address addr = aIter->first; + //Address addr = aIter->first; AbslocState &as = aIter->second; for (auto tIter = as.begin(); tIter != as.end(); tIter++) { const Absloc &target = tIter->first; @@ -675,17 +684,17 @@ void StackAnalysis::computeInsnEffects(ParseAPI::Block *block, case e_leave: handleLeave(block, off, xferFuncs); break; - case e_pushfd: + case e_pushf: sign = -1; //FALLTHROUGH case e_popfd: handlePushPopFlags(sign, xferFuncs); break; - case e_pushad: + case e_pushal: sign = -1; handlePushPopRegs(sign, xferFuncs); break; - case e_popad: + case e_popaw: // This nukes all registers handleDefault(insn, block, off, xferFuncs); break; @@ -730,24 +739,24 @@ void StackAnalysis::computeInsnEffects(ParseAPI::Block *block, } } -StackAnalysis::Height StackAnalysis::getStackCleanAmount(Function *func) { +StackAnalysis::Height StackAnalysis::getStackCleanAmount(Function *func_) { // Cache previous work... - if (funcCleanAmounts.find(func) != funcCleanAmounts.end()) { - return funcCleanAmounts[func]; + if (funcCleanAmounts.find(func_) != funcCleanAmounts.end()) { + return funcCleanAmounts[func_]; } - if (!func->cleansOwnStack()) { - funcCleanAmounts[func] = 0; - return funcCleanAmounts[func]; + if (!func_->cleansOwnStack()) { + funcCleanAmounts[func_] = 0; + return funcCleanAmounts[func_]; } InstructionDecoder decoder((const unsigned char*) NULL, 0, - func->isrc()->getArch()); + func_->isrc()->getArch()); unsigned char *cur; std::set returnCleanVals; - Function::const_blocklist returnBlocks = func->returnBlocks(); + Function::const_blocklist returnBlocks = func_->returnBlocks(); for (auto rets = returnBlocks.begin(); rets != returnBlocks.end(); ++rets) { Block *ret = *rets; cur = (unsigned char *) ret->region()->getPtrToInstruction( @@ -775,7 +784,7 @@ StackAnalysis::Height StackAnalysis::getStackCleanAmount(Function *func) { // Non-returning or tail-call exits? clean = Height::bottom; } - funcCleanAmounts[func] = clean; + funcCleanAmounts[func_] = clean; return clean; } @@ -1292,9 +1301,9 @@ void StackAnalysis::handleDiv(Instruction insn, STACKANALYSIS_ASSERT(dynamic_cast(remainder.get())); STACKANALYSIS_ASSERT(!dynamic_cast(divisor.get())); - MachRegister quotientReg = (boost::dynamic_pointer_cast(quotient))->getID(); - MachRegister remainderReg = (boost::dynamic_pointer_cast(remainder))->getID(); xferFuncs.push_back(TransferFunc::retopFunc(Absloc(quotientReg))); @@ -1319,7 +1328,7 @@ void StackAnalysis::handleMul(Instruction insn, Expression::Ptr target = operands[0].getValue(); STACKANALYSIS_ASSERT(dynamic_cast(target.get())); - MachRegister targetReg = (boost::dynamic_pointer_cast(target))->getID(); if (operands.size() == 2) { @@ -1341,7 +1350,7 @@ void StackAnalysis::handleMul(Instruction insn, } else if (multiplierVal == 1) { if (dynamic_cast(multiplicand.get())) { // mul reg1, reg2, 1 - MachRegister multiplicandReg = boost::dynamic_pointer_cast< + MachRegister multiplicandReg = dyncompat::dynamic_pointer_cast< RegisterAST>(multiplicand)->getID(); Absloc targetLoc(targetReg); Absloc multiplicandLoc(multiplicandReg); @@ -1363,7 +1372,7 @@ void StackAnalysis::handleMul(Instruction insn, STACKANALYSIS_ASSERT(dynamic_cast(multiplicand.get())); STACKANALYSIS_ASSERT(dynamic_cast(multiplier.get()) || dynamic_cast(multiplier.get())); - MachRegister multiplicandReg = boost::dynamic_pointer_cast< + MachRegister multiplicandReg = dyncompat::dynamic_pointer_cast< RegisterAST>(multiplicand)->getID(); xferFuncs.push_back(TransferFunc::retopFunc(Absloc(targetReg))); xferFuncs.push_back(TransferFunc::retopFunc(Absloc(multiplicandReg))); @@ -1402,7 +1411,7 @@ void StackAnalysis::handlePushPop(Instruction insn, Block *block, Expression::Ptr readExpr = insn.getOperand(0).getValue(); if (dynamic_cast(readExpr.get())) { // Get copied register - MachRegister readReg = boost::dynamic_pointer_cast( + MachRegister readReg = dyncompat::dynamic_pointer_cast( readExpr)->getID(); Absloc readLoc(readReg); xferFuncs.push_back(TransferFunc::copyFunc(readLoc, writtenLoc)); @@ -1452,7 +1461,7 @@ void StackAnalysis::handlePushPop(Instruction insn, Block *block, // Get target register Expression::Ptr targExpr = insn.getOperand(0).getValue(); STACKANALYSIS_ASSERT(dynamic_cast(targExpr.get())); - MachRegister targReg = boost::dynamic_pointer_cast( + MachRegister targReg = dyncompat::dynamic_pointer_cast( targExpr)->getID(); Absloc targLoc(targReg); @@ -1725,7 +1734,7 @@ void StackAnalysis::handleLEA(Instruction insn, if (readSet.size() == 0) { // op1: imm - STACKANALYSIS_ASSERT(typeid(*srcExpr) == typeid(Immediate)); + STACKANALYSIS_ASSERT(dynamic_cast(srcExpr.get())); long immVal = srcExpr->eval().convert(); xferFuncs.push_back(TransferFunc::absFunc(writeloc, immVal)); retopBaseSubReg(written, xferFuncs); @@ -1767,7 +1776,7 @@ void StackAnalysis::handleLEA(Instruction insn, STACKANALYSIS_ASSERT(false); } - MachRegister reg = (boost::dynamic_pointer_cast(regExpr))->getID(); long scale = 1; @@ -1825,9 +1834,9 @@ void StackAnalysis::handleLEA(Instruction insn, STACKANALYSIS_ASSERT(dynamic_cast(indexExpr.get())); STACKANALYSIS_ASSERT(dynamic_cast(scaleExpr.get())); - MachRegister base = (boost::dynamic_pointer_cast(baseExpr))->getID(); - MachRegister index = (boost::dynamic_pointer_cast(indexExpr))->getID(); long scale = scaleExpr->eval().convert(); @@ -2454,7 +2463,7 @@ bool StackAnalysis::handleNormalCall(Instruction insn, Block *block, if (off != block->lastInsnAddr()) return false; Address calledAddr = 0; - boost::lock_guard g(*block); + dyncompat::lock_guard g(*block); const Block::edgelist &outs = block->targets(); for (auto eit = outs.begin(); eit != outs.end(); eit++) { Edge *edge = *eit; @@ -2625,7 +2634,7 @@ bool StackAnalysis::handleNormalCall(Instruction insn, Block *block, bool StackAnalysis::handleJump(Instruction insn, Block *block, Offset off, TransferFuncs &xferFuncs, TransferSet &funcSummary) { Address calledAddr = 0; - boost::lock_guard g(*block); + dyncompat::lock_guard g(*block); const Block::edgelist &outs = block->targets(); for (auto eit = outs.begin(); eit != outs.end(); eit++) { Edge *edge = *eit; @@ -2824,6 +2833,7 @@ void StackAnalysis::createEntryInput(AbslocState &input) { input[Absloc(x86_64::esp)].addInitSet(Height(-word_size)); } #else + DYNINST_SUPPRESS_UNUSED_VARIABLE(input); STACKANALYSIS_ASSERT(0 && "Unimplemented architecture"); #endif } @@ -2879,15 +2889,15 @@ void StackAnalysis::meetInputs(Block *block, AbslocState &blockInput, intra_nosink_nocatch epred2; stackanalysis_printf("\t ... In edges: "); - boost::lock_guard g(*block); + dyncompat::lock_guard g(*block); const Block::edgelist & inEdges = block->sources(); std::for_each( - boost::make_filter_iterator(epred2, inEdges.begin(), inEdges.end()), - boost::make_filter_iterator(epred2, inEdges.end(), inEdges.end()), - boost::bind(&StackAnalysis::meet, this, - boost::bind(&StackAnalysis::getSrcOutputLocs, this, boost::placeholders::_1), - boost::ref(input))); + dyncompat::make_filter_iterator(epred2, inEdges.begin(), inEdges.end()), + dyncompat::make_filter_iterator(epred2, inEdges.end(), inEdges.end()), + dyncompat::bind(&StackAnalysis::meet, this, + dyncompat::bind(&StackAnalysis::getSrcOutputLocs, this, dyncompat::placeholders::_1), + dyncompat::ref(input))); stackanalysis_printf("\n"); meet(blockInput, input); @@ -2898,15 +2908,15 @@ void StackAnalysis::meetSummaryInputs(Block *block, TransferSet &blockInput, TransferSet &input) { input.clear(); intra_nosink_nocatch epred2; - boost::lock_guard g(*block); + dyncompat::lock_guard g(*block); const Block::edgelist & inEdges = block->sources(); std::for_each( - boost::make_filter_iterator(epred2, inEdges.begin(), inEdges.end()), - boost::make_filter_iterator(epred2, inEdges.end(), inEdges.end()), - boost::bind(&StackAnalysis::meetSummary, this, - boost::bind(&StackAnalysis::getSummarySrcOutputLocs, this, boost::placeholders::_1), - boost::ref(input))); + dyncompat::make_filter_iterator(epred2, inEdges.begin(), inEdges.end()), + dyncompat::make_filter_iterator(epred2, inEdges.end(), inEdges.end()), + dyncompat::bind(&StackAnalysis::meetSummary, this, + dyncompat::bind(&StackAnalysis::getSummarySrcOutputLocs, this, dyncompat::placeholders::_1), + dyncompat::ref(input))); meetSummary(blockInput, input); } @@ -3293,9 +3303,9 @@ StackAnalysis::DefHeightSet StackAnalysis::TransferFunc::apply( return inputSet; } - AbslocState::const_iterator iter = inputs.find(target); - if (iter != inputs.end()) { - inputSet = iter->second; + AbslocState::const_iterator iter_ = inputs.find(target); + if (iter_ != inputs.end()) { + inputSet = iter_->second; } else { inputSet.makeTopSet(); } @@ -3307,7 +3317,7 @@ StackAnalysis::DefHeightSet StackAnalysis::TransferFunc::apply( for (auto iter = fromRegs.begin(); iter != fromRegs.end(); ++iter) { Absloc curLoc = (*iter).first; long curScale = (*iter).second.first; - bool curTopBottom = (*iter).second.second; + //bool curTopBottom = (*iter).second.second; auto findLoc = inputs.find(curLoc); Height locInput; if (findLoc == inputs.end()) { @@ -3344,7 +3354,7 @@ StackAnalysis::DefHeightSet StackAnalysis::TransferFunc::apply( // Copy the input value from whatever we're a copy of. AbslocState::const_iterator iter2 = inputs.find(from); if (iter2 != inputs.end()) { - const Definition &def = iter2->second.getDefSet(); + //const Definition &def = iter2->second.getDefSet(); const Height &h = iter2->second.getHeightSet(); if (!h.isBottom() && !h.isTop()) { if ((from.isSP() || from.isFP()) && @@ -3705,8 +3715,8 @@ void StackAnalysis::SummaryFunc::add(TransferFuncs &xferFuncs) { // We need to update our register->xferFunc map // with the effects of each of the transferFuncs. for (auto iter = xferFuncs.begin(); iter != xferFuncs.end(); ++iter) { - TransferFunc &func = *iter; - func.accumulate(accumFuncs); + TransferFunc &func_ = *iter; + func_.accumulate(accumFuncs); } validate(); } @@ -3716,8 +3726,8 @@ void StackAnalysis::SummaryFunc::addSummary(const TransferSet &summary) { TransferSet newAccumFuncs = accumFuncs; for (auto iter = summary.begin(); iter != summary.end(); ++iter) { const Absloc &loc = iter->first; - const TransferFunc &func = iter->second; - newAccumFuncs[loc] = func.summaryAccumulate(accumFuncs); + const TransferFunc &func_ = iter->second; + newAccumFuncs[loc] = func_.summaryAccumulate(accumFuncs); } accumFuncs = newAccumFuncs; validate(); @@ -3726,11 +3736,11 @@ void StackAnalysis::SummaryFunc::addSummary(const TransferSet &summary) { void StackAnalysis::SummaryFunc::validate() const { for (TransferSet::const_iterator iter = accumFuncs.begin(); iter != accumFuncs.end(); ++iter) { - const TransferFunc &func = iter->second; - STACKANALYSIS_ASSERT(func.target.isValid()); - if (func.isCopy()) STACKANALYSIS_ASSERT(!func.isAbs()); - if (func.isAbs()) STACKANALYSIS_ASSERT(!func.isCopy()); - if (func.isBottom()) STACKANALYSIS_ASSERT(!func.isCopy()); + const TransferFunc &func_ = iter->second; + STACKANALYSIS_ASSERT(func_.target.isValid()); + if (func_.isCopy()) STACKANALYSIS_ASSERT(!func_.isAbs()); + if (func_.isAbs()) STACKANALYSIS_ASSERT(!func_.isCopy()); + if (func_.isBottom()) STACKANALYSIS_ASSERT(!func_.isCopy()); } } diff --git a/dataflowAPI/src/templates.C b/dataflowAPI/src/templates.C deleted file mode 100644 index f229aa47ab..0000000000 --- a/dataflowAPI/src/templates.C +++ /dev/null @@ -1,29 +0,0 @@ -/* - * See the dyninst/COPYRIGHT file for copyright information. - * - * We provide the Paradyn Tools (below described as "Paradyn") - * on an AS IS basis, and do not warrant its validity or performance. - * We reserve the right to update, modify, or discontinue this - * software at any time. We shall have no obligation to supply such - * updates or modifications or any other form of support to you. - * - * By your use of Paradyn, you understand and agree that we (or any - * other person or entity with proprietary rights in Paradyn) are - * under no obligation to provide either maintenance services, - * update services, notices of latent defects, or correction of - * defects for Paradyn. - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - */ diff --git a/dataflowAPI/tests/inst2ast/Makefile b/dataflowAPI/tests/inst2ast/Makefile deleted file mode 100644 index 4d3b3244ad..0000000000 --- a/dataflowAPI/tests/inst2ast/Makefile +++ /dev/null @@ -1,22 +0,0 @@ - -CC = g++ -g -DYNINST_CFLAGS = -I$(DYNINST_ROOT)/dyninst/dynutil/h -I$(DYNINST_ROOT)/include -I$(DYNINST_ROOT)/dyninst/symEval/src \ --I$(DYNINST_ROOT)/dyninst/symEval/h -I$(DYNINST_ROOT)/dyninst - - - -LIB_FLAGS = -L$(DYNINST_ROOT)/$(PLATFORM)/lib -L$(DYNINST_ROOT)/dyninst/symEval/$(PLATFORM) - -XTARGET = inst2ast - -all: $(XTARGET) - -$(XTARGET): $(XTARGET).o - $(CC) $(XTARGET).o $(LIB_FLAGS) -ldyninstAPI -lsymEval -lcommon -liberty -o $(XTARGET) - -$(XTARGET).o: $(XTARGET).C - $(CC) -c $(CFLAGS) $(DYNINST_CFLAGS) $(XTARGET).C - -clean: - rm -f $(XTARGET) $(XTARGET).o - diff --git a/dataflowAPI/tests/inst2ast/foo.c b/dataflowAPI/tests/inst2ast/foo.c deleted file mode 100644 index 871ac99a7a..0000000000 --- a/dataflowAPI/tests/inst2ast/foo.c +++ /dev/null @@ -1,39 +0,0 @@ -/* - * See the dyninst/COPYRIGHT file for copyright information. - * - * We provide the Paradyn Tools (below described as "Paradyn") - * on an AS IS basis, and do not warrant its validity or performance. - * We reserve the right to update, modify, or discontinue this - * software at any time. We shall have no obligation to supply such - * updates or modifications or any other form of support to you. - * - * By your use of Paradyn, you understand and agree that we (or any - * other person or entity with proprietary rights in Paradyn) are - * under no obligation to provide either maintenance services, - * update services, notices of latent defects, or correction of - * defects for Paradyn. - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - */ -int a = 1; -int b = 2; -int c = 3; -int d = 4; -int e = 5; -int f = 6; - -int main() { - return (a + b) / (c + d) * (e + f); -} diff --git a/dataflowAPI/tests/inst2ast/inst.txt b/dataflowAPI/tests/inst2ast/inst.txt deleted file mode 100644 index 020b59c3d0..0000000000 --- a/dataflowAPI/tests/inst2ast/inst.txt +++ /dev/null @@ -1,18 +0,0 @@ -Some test instructions: - -Move constant to register ----- -bf 58 06 40 00 - -mov %eax,0xfffffffffffffffc(%rbp) ----- -89 45 fc - -mov %eax,%ebx ----- -89 c3 - -mov 0xfffffffffffffffc(%rbp),%eax ----- -8b 45 fc - diff --git a/dataflowAPI/tests/inst2ast/inst2ast.C b/dataflowAPI/tests/inst2ast/inst2ast.C deleted file mode 100644 index 7769747b8a..0000000000 --- a/dataflowAPI/tests/inst2ast/inst2ast.C +++ /dev/null @@ -1,120 +0,0 @@ -/* - * See the dyninst/COPYRIGHT file for copyright information. - * - * We provide the Paradyn Tools (below described as "Paradyn") - * on an AS IS basis, and do not warrant its validity or performance. - * We reserve the right to update, modify, or discontinue this - * software at any time. We shall have no obligation to supply such - * updates or modifications or any other form of support to you. - * - * By your use of Paradyn, you understand and agree that we (or any - * other person or entity with proprietary rights in Paradyn) are - * under no obligation to provide either maintenance services, - * update services, notices of latent defects, or correction of - * defects for Paradyn. - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - */ -// Inst2AST -// Convert a single instruction to an AST and print - -#include "BPatch.h" -#include "BPatch_function.h" -#include "BPatch_Vector.h" -#include "BPatch_thread.h" -#include "AbslocInterface.h" -#include "BPatch_flowGraph.h" -#include "BPatch_basicBlock.h" - -#include "SymEval.h" - -#include "InstructionDecoder.h" -using namespace Dyninst; -using namespace Dyninst::InstructionAPI; -using namespace Dyninst::DataflowAPI; - -#include -#include -#include -#include -#include -using namespace std; - -int main(int argc, char *argv[]) -{ - // Symbolic evaluation of all instructions - // in a provided binary/function - - BPatch bpatch; - - if( argc < 3 ) { - cerr << "Usage: " << argv[0] - << "inst2ast " - << endl; - exit(-1); - } - - BPatch_addressSpace *app = bpatch.openBinary(argv[1], true); - - BPatch_image* appImage = app->getImage(); - - BPatch_Vector function; - appImage->findFunction(argv[2], - function); - - BPatch_flowGraph *cfg = function[0]->getCFG(); - std::set blocks; - cfg->getAllBasicBlocks(blocks); - - AssignmentConverter converter(true); - - for (std::set::iterator b_iter = blocks.begin(); - b_iter != blocks.end(); ++b_iter) { - std::vector > insns; - (*b_iter)->getInstructions(insns); - for (unsigned i = 0; i < insns.size(); ++i) { - std::vector assigns; - cerr << insns[i].first->format() << endl; - - converter.convert(insns[i].first, - insns[i].second, - function[0], - assigns); - - // Build a map stating which assignments we're interested in - Result_t res; - for (std::vector::iterator a_iter = assigns.begin(); - a_iter != assigns.end(); ++a_iter) { - //cerr << "Recording interest in " << (*a_iter)->format() << endl; - res[*a_iter] = AST::Ptr(); - } - - // Feed the map into the symbolic evaluator - SymEval::expand(res); - - // What do we have here? - for (Result_t::const_iterator r_iter = res.begin(); - r_iter != res.end(); ++r_iter) { - cout << "-----------------" << endl; - cout << r_iter->first->format(); - cout << " == "; - cout << r_iter->second->format() << endl; - } - cout << endl << "====================" << endl; - } - } - - return 0; -} diff --git a/docker/Dockerfile b/docker/Dockerfile new file mode 100644 index 0000000000..6506cb8a9d --- /dev/null +++ b/docker/Dockerfile @@ -0,0 +1,12 @@ +ARG base +FROM ${base} + +ARG build_jobs=1 + +LABEL maintainer="@hainest" + +COPY . /dyninst/src +COPY docker/build.sh docker/dependencies.versions / + +# Build Dyninst +RUN bash build.sh /dyninst/src $build_jobs && rm -rf /dyninst/src/.git diff --git a/docker/Dockerfile.fedora b/docker/Dockerfile.fedora new file mode 100644 index 0000000000..3bbb864782 --- /dev/null +++ b/docker/Dockerfile.fedora @@ -0,0 +1,30 @@ +ARG version +FROM fedora:${version} + +##################################################### +# +# Base container for a Fedora environment +# +# The dependencies are purposefully unversioned +# so that the distribution-default ones are used. +# +##################################################### + +LABEL maintainer="@hainest" + +ENV TZ=America/Chicago + +RUN yum update -y && \ + yum install -y \ + binutils-devel \ + boost-devel \ + cmake \ + elfutils-devel \ + gcc \ + g++ \ + git \ + glibc-static \ + libdwarf-devel \ + libstdc++-static \ + tbb-devel + \ No newline at end of file diff --git a/docker/Dockerfile.ubuntu b/docker/Dockerfile.ubuntu new file mode 100644 index 0000000000..1d13234ea9 --- /dev/null +++ b/docker/Dockerfile.ubuntu @@ -0,0 +1,48 @@ +ARG version +FROM ubuntu:${version} + +ARG build_elfutils="no" +ARG build_jobs=1 + +##################################################### +# +# Base container for an Ubuntu environment +# +# The dependencies are purposefully unversioned +# so that the distribution-default ones are used. +# +# If the distro's elfutils is too old, it can be +# built by using `--build-arg build_elfutils=yes`. +# +##################################################### + +LABEL maintainer="@hainest,@vsoch" + +ENV DEBIAN_FRONTEND=noninteractive +ENV TZ=America/Chicago + +RUN apt-get -qq update && \ + apt-get -qq install -y --no-install-recommends \ + build-essential \ + cmake \ + libboost-atomic-dev \ + libboost-chrono-dev \ + libboost-date-time-dev \ + libboost-filesystem-dev \ + libboost-thread-dev \ + libboost-timer-dev \ + libtbb-dev \ + gettext \ + bzip2 \ + zlib1g-dev \ + m4 \ + libiberty-dev \ + pkg-config \ + clang \ + libomp-dev + +COPY docker/build_elfutils.sh docker/dependencies.versions / + +RUN bash build_elfutils.sh --from-source ${build_elfutils} --jobs ${build_jobs} + +RUN rm build_elfutils.sh dependencies.versions diff --git a/docker/README.md b/docker/README.md new file mode 100644 index 0000000000..12e267f505 --- /dev/null +++ b/docker/README.md @@ -0,0 +1,84 @@ +# Dyninst Containers + +This is a testing set of Dockerfile for building a Dyninst base container. + +## Strategy + +For development, we want to be able to: + + 1. Pull a container with dyninst ready to go (for development or dyninst or another library) + 2. Quickly update with our own source code without needing to build everything. + +And for testing, we want to be able to: + + 1. Have a set of base containers that make dependency preparation minimal + 2. Use those base containers to quickly test a PR's dyninst and report results + +These are both achieved using a single workflow based on a set of base images with each containing a minimal OS environment and the package-provided versions of the various Dyninst dependencies. There is no source for Dyninst or any of its components. The development image is a small layer on top of a base and contains the Dyninst source and binaries. They are named by both the base OS and the hardware architecture. For example, the base container for Ubuntu 20.04 on x86_64 is `dyninst-amd64-base:ubuntu-20.04`. The corresponding development container is named `dyninst-amd64:ubuntu-20.04`. + +## Usage + +The Dockerfiles provided are intended for building the base and development containers from scratch. We don't recommend using these directly as images are provided as [packages](https://github.com/orgs/dyninst/packages). + +### Build + +A [Dockerfile](Dockerfile) is provided that makes it easy to bring up a development environment. The following builds the Ubuntu 20.04 images. + +```bash +$ cd path/to/Dyninst/source + +# Base image (Ubuntu 20.04 needs a newer elfutils) +$ docker build -f docker/Dockerfile.ubuntu -t dyninst-base:ubuntu-20.04 --build-arg version=20.04 --build-arg build_elfutils=yes . + +# Development image +$ docker build -f docker/Dockerfile -t dyninst:ubuntu-20.04 --build-arg build_jobs=16 --build-arg base=dyninst-base:ubuntu-20.04 . +``` + +In the development container, Dyninst is installed in `/dyninst/install`. + +### Develop + +You can then shell inside to interact with dyninst: + +```bash +$ docker run -it dyninst:ubuntu-20.04 bash +``` + +For a more interactive development environment, you can bind the present working directory with the +Dyninst source code bound to `/code` instead: + +```bash +$ docker run -it -v $PWD:/code dyninst:ubuntu-20.04 +``` + +And again navigate to the bound source code - this time the files are on your local machine, so you can edit +them locally and build in the container! + +```bash +# This is bound to your host - edit files there +$ cd /code +``` + +## Maintainers + +### Adding a new OS image + +1. Add the relevant information to 'build_base_images.sh'. For example, `make_image ubuntu 24.10`. + +2. Run `build_base_images.sh --push` to build and push _all_ container images. + +3. Running the script above will print a complete list of supported OSes. These need to be added to the + GitHub "os:" fields in the workflow files dev-containers.yaml and pr-tests.yaml. + Make a PR to add these updated files. + +4. After committing the PR above, the 'Build and Deploy Development Containers' workflow will update/generate + the associated development containers automatically on the next committed PR. It can be run manually via + the Github interface, if preferred. + +### Adding a dependency + +Assuming all of the requisite CMake files are in place, a new dependency can be added to the container images. If +the dependency can be installed by the package provider, add it to the `Dockerfile.` file, and run +`build_base_images.sh --push`. If it needs to be built from source, add a new build script (e.g., build_foo.sh) +and call it from the `Dockerfile.` files. If the dependency only sometimes needs to be built from source, +see the usage of 'build_elfutils.sh' for guidance. diff --git a/docker/build.sh b/docker/build.sh new file mode 100644 index 0000000000..4aa26e29d6 --- /dev/null +++ b/docker/build.sh @@ -0,0 +1,41 @@ +#! /bin/bash + +set -e + +if test "x$1" = "x"; then + echo "No source directory given\nUsage: $0 src [num_jobs]" >stderr + exit 1 +fi + +num_jobs=1 +if test "x$2" != "x"; then + num_jobs=$2 +fi + +printf "⭐️ Preparing to build Dyninst\n" +echo "::group::build dyninst" + +SRC_DIR=$1 +BUILD_DIR=/dyninst/build +INSTALL_DIR=/dyninst/install +mkdir -p $BUILD_DIR $INSTALL_DIR + +printf "⭐️ Configuring\n" +cd $BUILD_DIR +FLAGS="-DCMAKE_C_FLAGS=${DYNINST_C_FLAGS} -DCMAKE_CXX_FLAGS=${DYNINST_CXX_FLAGS}" +if test x"${DYNINST_C_COMPILER}" = x; then DYNINST_C_COMPILER=gcc; fi +if test x"${DYNINST_CXX_COMPILER}" = x; then DYNINST_CXX_COMPILER=g++; fi +COMPILERS="-DCMAKE_C_COMPILER=${DYNINST_C_COMPILER} -DCMAKE_CXX_COMPILER=${DYNINST_CXX_COMPILER}" +cmake $SRC_DIR -DCMAKE_INSTALL_PREFIX=$INSTALL_DIR ${FLAGS} ${COMPILERS} ${EXTRA_CMAKE_FLAGS} + +printf "⭐️ Building\n" +cmake --build . --parallel $num_jobs + +printf "⭐️ Installing\n" +cmake --install . + +printf "⭐️ Cleaning up\n" +cd / +rm -rf $BUILD_DIR + +echo "::endgroup::" diff --git a/docker/build_base_images.sh b/docker/build_base_images.sh new file mode 100644 index 0000000000..26bf321d09 --- /dev/null +++ b/docker/build_base_images.sh @@ -0,0 +1,47 @@ +#!/bin/bash + +set -e + +jobs=1 # run builds with N jobs (same as 'make -jN') +push=no # push images after building + +while [[ "$#" -gt 0 ]]; do + case $1 in + -j|--jobs) jobs="$2"; shift 2; ;; + -p|--push) push=yes; shift; ;; + esac +done + +declare -a os_versions + +function make_image { + distro=$1 + version=$2 + extra=$3 + base="ghcr.io/dyninst/amd64/${distro}-${version}-base:latest" + docker pull ${distro}:${version} # Always use latest distro image; ignoring any cached versions + docker build -f docker/Dockerfile.${distro} -t $base --build-arg build_jobs=${jobs} --build-arg version=${version} ${extra} . + + if test "${push}" = "yes"; then + docker push ${base} + fi + + os_versions+=("${distro}-${version}") +} + + +make_image ubuntu 20.04 "--build-arg build_elfutils=yes" +make_image ubuntu 22.04 +make_image ubuntu 23.04 +make_image ubuntu 23.10 +make_image ubuntu 24.04 + +make_image fedora 37 +make_image fedora 38 +make_image fedora 39 + +echo -n "[" +for v in "${os_versions[@]}"; do + echo -n "'$v', " +done +echo "]" diff --git a/docker/build_elfutils.sh b/docker/build_elfutils.sh new file mode 100644 index 0000000000..6fc2e5893d --- /dev/null +++ b/docker/build_elfutils.sh @@ -0,0 +1,33 @@ +#! /bin/bash + +set -e + +jobs=1 # run builds with N jobs (same as 'make -jN') +source=no # push images after building + +while [[ "$#" -gt 0 ]]; do + case $1 in + -j|--jobs) jobs="$2"; shift 2; ;; + -s|--from-source) source="$2"; shift 2; ;; + esac +done + +if test "$source" = "no"; then + apt install -qq -y --no-install-recommends elfutils libelf-dev libdw-dev libdebuginfod-dev + exit +fi + +apt install -qq -y --no-install-recommends libcurl4-openssl-dev wget libzstd-dev libbz2-dev liblzma-dev + +version=$(grep elfutils dependencies.versions | awk '{split($0,a,":"); print a[2]}') + +wget --no-check-certificate https://sourceware.org/elfutils/ftp/${version}/elfutils-${version}.tar.bz2 +bunzip2 elfutils-${version}.tar.bz2 +tar -xf elfutils-${version}.tar +cd elfutils-${version}/ +mkdir build +cd build +../configure --enable-libdebuginfod --disable-debuginfod +make install -j ${jobs} +cd / +rm -rf elfutils-${version}/ elfutils-${version}.tar diff --git a/docker/dependencies.versions b/docker/dependencies.versions new file mode 100644 index 0000000000..a3f1dd14a0 --- /dev/null +++ b/docker/dependencies.versions @@ -0,0 +1,4 @@ +boost:1.71.0 +tbb:2019.9 +elfutils:0.186 +cmake:3.14.0 \ No newline at end of file diff --git a/dwarf/CMakeLists.txt b/dwarf/CMakeLists.txt index e959351b20..576de56d82 100644 --- a/dwarf/CMakeLists.txt +++ b/dwarf/CMakeLists.txt @@ -1,25 +1,28 @@ -# CMake configuration for dynDwarf (dwarf) directory +include_guard(GLOBAL) -if (NOT UNIX) +include(DyninstLibrary) + +if(NOT DYNINST_OS_UNIX) + if(NOT TARGET dynDwarf) + add_library(dynDwarf INTERFACE) + endif() return() endif() -include_directories ( - src - h - ${PROJECT_SOURCE_DIR}/elf/h - ${PROJECT_SOURCE_DIR}/common/src - ) -add_definitions(-DDYNDWARF_LIB) - -set (SRC_LIST - src/dwarfResult.C - src/dwarfExprParser.C - src/dwarfFrameParser.C - src/dwarfHandle.C - ) +set(_public_headers h/dwarfExprParser.h h/dwarfFrameParser.h h/dwarfHandle.h + h/dwarfResult.h h/dwarf_unit_info.h) +set(_sources src/dwarfResult.C src/dwarfExprParser.C src/dwarfFrameParser.C + src/dwarfHandle.C src/dwarf_subrange.cpp) -dyninst_library(dynDwarf dynElf common ${LibDwarf_LIBRARIES}) -add_dependencies(dynDwarf ElfUtils) -target_link_private_libraries(dynDwarf ${Boost_LIBRARIES} ${ElfUtils_LIBRARIES}) +# cmake-format: off +dyninst_library( + dynDwarf + PUBLIC_HEADER_FILES ${_public_headers} + SOURCE_FILES ${_sources} + DEFINES DYNDWARF_LIB + DYNINST_DEPS dynElf common + PUBLIC_DEPS + PRIVATE_DEPS Dyninst::ElfUtils +) +# cmake-format: on diff --git a/dwarf/h/dwarfExprParser.h b/dwarf/h/dwarfExprParser.h index 95274505a3..beb9f23d63 100644 --- a/dwarf/h/dwarfExprParser.h +++ b/dwarf/h/dwarfExprParser.h @@ -32,7 +32,7 @@ #define DWARF_EXPR_H #include -#include "dyn_regs.h" +#include "Architecture.h" #include "elfutils/libdw.h" #include "dwarf.h" #include "util.h" diff --git a/dwarf/h/dwarfFrameParser.h b/dwarf/h/dwarfFrameParser.h index 3b8a48f77f..f0316ac252 100644 --- a/dwarf/h/dwarfFrameParser.h +++ b/dwarf/h/dwarfFrameParser.h @@ -31,14 +31,18 @@ #if !defined(DWARF_SW_H_) #define DWARF_SW_H_ +#include +#include #include #include #include "dyntypes.h" -#include "dyn_regs.h" +#include "Architecture.h" +#include "registers/MachRegister.h" #include "ProcReader.h" #include "elfutils/libdw.h" #include "util.h" -#include +#include +#include #include "concurrent.h" namespace Dyninst { @@ -60,7 +64,7 @@ typedef enum { class DYNDWARF_EXPORT DwarfFrameParser { public: - typedef boost::shared_ptr Ptr; + typedef dyncompat::shared_ptr Ptr; static Ptr create(Dwarf * dbg, Elf * eh_frame, Architecture arch); @@ -150,7 +154,7 @@ class DYNDWARF_EXPORT DwarfFrameParser { Architecture arch; - boost::once_flag fde_dwarf_once; + dyncompat::once_flag fde_dwarf_once; dwarf_status_t fde_dwarf_status; dyn_mutex cfi_lock; diff --git a/dwarf/h/dwarfHandle.h b/dwarf/h/dwarfHandle.h index ec2ea72405..7aad26c9e5 100644 --- a/dwarf/h/dwarfHandle.h +++ b/dwarf/h/dwarfHandle.h @@ -35,6 +35,7 @@ #include "dyntypes.h" #include #include +#include namespace Dyninst { class Elf_X; @@ -42,7 +43,7 @@ class Elf_X; namespace DwarfDyninst { class DwarfFrameParser; -typedef boost::shared_ptr DwarfFrameParserPtr; +typedef dyncompat::shared_ptr DwarfFrameParserPtr; class DYNDWARF_EXPORT DwarfHandle { public: diff --git a/dwarf/h/dwarfResult.h b/dwarf/h/dwarfResult.h index 96c153d68e..838de23366 100644 --- a/dwarf/h/dwarfResult.h +++ b/dwarf/h/dwarfResult.h @@ -31,7 +31,8 @@ #include #include -#include "dyn_regs.h" +#include "Architecture.h" +#include "registers/MachRegister.h" #include "dyntypes.h" #include "elfutils/libdw.h" #include "util.h" @@ -78,6 +79,7 @@ class DYNDWARF_EXPORT DwarfResult { DwarfResult(Architecture a) : arch(a), error(false) {} + DwarfResult(const DwarfResult &) = default; virtual ~DwarfResult() = default; virtual void pushReg(Dyninst::MachRegister reg) = 0; @@ -165,12 +167,12 @@ class DYNDWARF_EXPORT ConcreteDwarfResult : public DwarfResult { bool eval(MachRegisterVal &v); private: - ProcessReader *reader; + ProcessReader *reader{}; // For getting access to other expressions - Address pc; - Dwarf * dbg; - Elf * dbg_eh_frame; + Address pc{}; + Dwarf * dbg{}; + Elf * dbg_eh_frame{}; // Dwarf lets you access within the "stack", so we model // it as a vector. diff --git a/dwarf/h/dwarf_cu_info.h b/dwarf/h/dwarf_cu_info.h new file mode 100644 index 0000000000..9964b967db --- /dev/null +++ b/dwarf/h/dwarf_cu_info.h @@ -0,0 +1,136 @@ +/* + * See the dyninst/COPYRIGHT file for copyright information. + * + * We provide the Paradyn Tools (below described as "Paradyn") + * on an AS IS basis, and do not warrant its validity or performance. + * We reserve the right to update, modify, or discontinue this + * software at any time. We shall have no obligation to supply such + * updates or modifications or any other form of support to you. + * + * By your use of Paradyn, you understand and agree that we (or any + * other person or entity with proprietary rights in Paradyn) are + * under no obligation to provide either maintenance services, + * update services, notices of latent defects, or correction of + * defects for Paradyn. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef DWARFDYNINST_DWARF_CU_INFO_HPP +#define DWARFDYNINST_DWARF_CU_INFO_HPP + +#include "dwarf_names.h" +#include "dwarf_unit_info.h" +#include +#include +#include + +namespace Dyninst { namespace DwarfDyninst { + + inline bool is_cudie(Dwarf_Die die) { + // If there is not an inner CU attribute, then it's not a CU + if (!die.cu) + return false; + + // These are best guess. Ideally, we'd like to interrogate + // the internals of the die, but that's not currently possible + // with libdw. The internal function there is `is_cudie`. + return is_full_unit(die) || is_partial_unit(die); + } + + /* + * Check if `die` corresponds to a DWARF unit that should be parsed + * + * DW_TAG_imported_unit may need to be included here, but is currently handled + * separately in DwarfWalker::parse_int. + * + */ + inline bool is_parseable_unit(Dwarf_Die die) { + return is_cudie(die) || is_type_unit(die); + } + + /* + * The name of the directory where the source file was compiled. + * + * If present, it is always an absolute path. Returns an empty string if not found. + * + */ + inline std::string cu_dirname(Dwarf_Die cuDie) { + return detail::comp_dir_name(cuDie); + } + /* + * The name of the compilation unit (CU) referred to by `cuDie` + * + * This is the name of the source file used to create the CU (e.g., test.cpp) + * made into an absolute path (if present, see below). + * + * The user MUST ensure that `cuDie` refers to a CU (see `dwarf_is_cudie` above). Otherwise, + * the returned name is nonsense. It would be very weird- but technically possible- for + * a CU die to be artificial. In that case, a unique name is generated. + * + * If the CU has no name- which would be even weirder- a unique one is created for it. + * + */ + inline std::string cu_name(Dwarf_Die cuDie) { + + // This takes care of the DW_AT_artificial case for us. + auto name = DwarfDyninst::die_name(cuDie); + + // Make the name absolute wrt the compilation directory + return detail::absolute_path(name, detail::comp_dir_name(cuDie)); + } + + /* + * Find the compilation unit (CU) die that starts at the address `addr`. + * + */ + inline Dwarf_Die *find_cu(Dwarf *dbg, Dwarf_Addr addr, Dwarf_Die *result) { + // The .debug_info DIE offset is the starting address for modules. + if(dwarf_offdie(dbg, addr, result)) { + return result; + } + + // Search for the given address (assumes .debug_aranges is present) + Dwarf_Die cuDIE{}; + if (dwarf_addrdie(dbg, addr, &cuDIE)) { + *result = cuDIE; + return result; + } + + // As of libdw 0.189, `dwarf_addrdie` assumes the presence of .debug_aranges. + // For compilers that do not emit one, or emit an invalid one (e.g., gtpin binaries), + // then manually search through all of the CUs to find a match. + size_t cu_header_size{}; + for (Dwarf_Off cu_off = 0, next_cu_off=0; + dwarf_nextcu(dbg, cu_off, &next_cu_off, &cu_header_size, NULL, NULL, NULL) == 0; + cu_off = next_cu_off) { + Dwarf_Off cu_die_off = cu_off + cu_header_size; + Dwarf_Die cu_die{}, *cu_die_p{}; + cu_die_p = dwarf_offdie(dbg, cu_die_off, &cu_die); + if (!cu_die_p) + continue; + Dwarf_Addr low_pc{}; + if (dwarf_lowpc(cu_die_p, &low_pc) == 0) { + if (low_pc == addr) { + *result = *cu_die_p; + return result; + } + } + } + return nullptr; + } +}} + +#endif diff --git a/dwarf/h/dwarf_names.h b/dwarf/h/dwarf_names.h new file mode 100644 index 0000000000..6a8db99227 --- /dev/null +++ b/dwarf/h/dwarf_names.h @@ -0,0 +1,143 @@ +/* + * See the dyninst/COPYRIGHT file for copyright information. + * + * We provide the Paradyn Tools (below described as "Paradyn") + * on an AS IS basis, and do not warrant its validity or performance. + * We reserve the right to update, modify, or discontinue this + * software at any time. We shall have no obligation to supply such + * updates or modifications or any other form of support to you. + * + * By your use of Paradyn, you understand and agree that we (or any + * other person or entity with proprietary rights in Paradyn) are + * under no obligation to provide either maintenance services, + * update services, notices of latent defects, or correction of + * defects for Paradyn. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef DWARFDYNINST_DWARF_NAMES_HPP +#define DWARFDYNINST_DWARF_NAMES_HPP + +#include +#include +#include +#include +#include +#include "dwarf_unit_info.h" + +namespace Dyninst { namespace DwarfDyninst { + + namespace detail { + + inline std::string die_name(Dwarf_Die die) { + auto name = dwarf_diename(&die); + if (!name) + return {}; // can't make a std::string from nullptr + return name; + } + + /* The absolute path of `filename` relative to `base` + * + * We could use std::filesystem::absolute here, but we don't need to pay the cost of + * its flexibility for multiple path separators since DWARF is currently only on + * Unix-like platforms. + */ + inline std::string absolute_path(std::string const &filename, std::string const &base) { + // If base is empty, don't make any conversion + if (base.empty()) { + return filename; + } + + if (filename.find('/') == 0UL) { + // It starts with a leading slash, so assume it's already absolute + return filename; + } + return base + "/" + filename; + } + + /* The compilation directory for the CU + * + * Returns an empty string if not found + */ + inline std::string comp_dir_name(Dwarf_Die cuDie) { + Dwarf_Attribute attr; + const char *comp_dir = dwarf_formstring(dwarf_attr(&cuDie, DW_AT_comp_dir, &attr)); + if (!comp_dir) + return {}; + return comp_dir; + } + + /* + * Make a string representation of the DIEs offset + */ + inline std::string die_offset(Dwarf_Die die) { + auto off_die = dwarf_dieoffset(&die); + std::stringstream suffix; + suffix << std::hex << off_die; + return "0x" + suffix.str(); + } + } + + /* Check if the die is anonymous + * + * True if it has no DW_AT_name attribute + * + * This only checks if the immediate die has a name. We + * don't care if any of its parents have a name. + */ + inline bool is_anonymous_die(Dwarf_Die die) { return !dwarf_hasattr(&die, DW_AT_name); } + + /* Detect if the current DIE has been marked as artificial + * + * From the DWARF5 standard (2.11 Artificial Entries): + * + * A compiler may wish to generate debugging information entries for objects + * or types that were not actually declared in the source of the application. + */ + inline bool is_artificial_die(Dwarf_Die die) { + bool has_art_attr = dwarf_hasattr(&die, DW_AT_artificial); + + // Some compilers name the DIE `` and some provide the + // DW_AT_artificial attribute, so check both + return detail::die_name(die) == "" || has_art_attr; + } + + /* The name of the die referred to by `die` + * + * If the `die` is artificial, a unique name is returned. + * If this case is important to the caller, then `is_artificial` + * should be checked. + * + * Anonymous DIEs are purposefully left unnamed because of explicit + * checks in DwarfWalker::nameDefined. + */ + inline std::string die_name(Dwarf_Die die) { + + auto name = detail::die_name(die); + + // For artificial DIEs or partial units, append the DIE's location to its name (if any). + // For C++ member functions, compilers will sometimes add a DW_AT_name called 'this', + // and we don't want to mangle that. + if (name.empty() && (is_artificial_die(die) || is_partial_unit(die))) { + name += "(" + detail::die_offset(die) + ")"; + return name; + } + + return name; + } +}} + +#endif diff --git a/common/src/language.h b/dwarf/h/dwarf_unit_info.h similarity index 70% rename from common/src/language.h rename to dwarf/h/dwarf_unit_info.h index be8f04130b..2113a8d7bb 100644 --- a/common/src/language.h +++ b/dwarf/h/dwarf_unit_info.h @@ -1,60 +1,43 @@ /* * See the dyninst/COPYRIGHT file for copyright information. - * + * * We provide the Paradyn Tools (below described as "Paradyn") * on an AS IS basis, and do not warrant its validity or performance. * We reserve the right to update, modify, or discontinue this * software at any time. We shall have no obligation to supply such * updates or modifications or any other form of support to you. - * + * * By your use of Paradyn, you understand and agree that we (or any * other person or entity with proprietary rights in Paradyn) are * under no obligation to provide either maintenance services, * update services, notices of latent defects, or correction of * defects for Paradyn. - * + * * This library is free software; you can redistribute it and/or * modify it under the terms of the GNU Lesser General Public * License as published by the Free Software Foundation; either * version 2.1 of the License, or (at your option) any later version. - * + * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU * Lesser General Public License for more details. - * + * * You should have received a copy of the GNU Lesser General Public * License along with this library; if not, write to the Free Software * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef DWARF_UNIT_INFO_H +#define DWARF_UNIT_INFO_H - -// $Id: language.h,v - -// Put C++ language specific code in here - -#ifndef __LANGUAGE__ -#define __LANGUAGE__ - -#if ! defined( TYPENAME ) - -#if defined( __GNUC__ ) -# define TYPENAME typename -#elif defined(__SUNPRO_CC) -# define TYPENAME typename -#elif defined (__XLC__) || defined(__xlC__) -#define TYPENAME typename -#elif defined(_MSC_VER) && (_MSC_VER >= 1310) - // Visual Studio .NET or greater -# define TYPENAME typename -#else // other compilers may not support the typename keyword yet -#define TYPENAME -#endif +namespace Dyninst { namespace DwarfDyninst { + // We purposefully don't include DW_TAG_skeleton_unit here as + // libdw should merge those into a single CU for us. + inline bool is_full_unit(Dwarf_Die die) { return dwarf_tag(&die) == DW_TAG_compile_unit; } + inline bool is_partial_unit(Dwarf_Die die) { return dwarf_tag(&die) == DW_TAG_partial_unit; } + inline bool is_type_unit(Dwarf_Die die) { return dwarf_tag(&die) == DW_TAG_type_unit; } + inline bool is_imported_unit(Dwarf_Die die) { return dwarf_tag(&die) == DW_TAG_imported_unit; } +}} #endif - - - -#endif - diff --git a/dwarf/src/dwarfExprParser.C b/dwarf/src/dwarfExprParser.C index 6d804de844..ac5ba7bb51 100644 --- a/dwarf/src/dwarfExprParser.C +++ b/dwarf/src/dwarfExprParser.C @@ -30,13 +30,13 @@ #include #include -#include "dyn_regs.h" +#include "Architecture.h" +#include "registers/MachRegister.h" #include "dwarfExprParser.h" #include "dwarfResult.h" #include "debug_common.h" #include "VariableLocation.h" #include "ProcReader.h" -#include "Types.h" #include "compiler_annotations.h" using namespace std; diff --git a/dwarf/src/dwarfFrameParser.C b/dwarf/src/dwarfFrameParser.C index afcc32222c..fbe478ea74 100644 --- a/dwarf/src/dwarfFrameParser.C +++ b/dwarf/src/dwarfFrameParser.C @@ -27,6 +27,7 @@ * License along with this library; if not, write to the Free Software * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include "common/src/vgannotations.h" #include #include @@ -34,12 +35,12 @@ #include "dwarfExprParser.h" #include "dwarfResult.h" #include "VariableLocation.h" -#include "Types.h" #include "elfutils/libdw.h" #include #include #include "debug_common.h" // dwarf_printf #include +#include "registers/abstract_regs.h" using namespace Dyninst; using namespace DwarfDyninst; @@ -70,9 +71,7 @@ DwarfFrameParser::DwarfFrameParser(Dwarf * dbg_, Elf * eh_frame, Architecture ar dbg(dbg_), dbg_eh_frame(eh_frame), arch(arch_), -#ifndef BOOST_THREAD_PROVIDES_ONCE_CXX11 - fde_dwarf_once(BOOST_ONCE_INIT), -#endif + fde_dwarf_once(DYNCOMPAT_ONCE_INIT), fde_dwarf_status(dwarf_status_uninitialized) { } @@ -177,7 +176,7 @@ bool DwarfFrameParser::getRegsForFunction( return false; } - boost::unique_lock l(cfi_lock); + dyncompat::unique_lock l(cfi_lock); for(size_t i=0; i #include "elfutils/libdw.h" #include "elfutils/libdwfl.h" #include "Elf_X.h" @@ -197,29 +198,36 @@ bool DwarfHandle::init_dbg() case EM_CUDA: arch = Dyninst::Arch_cuda; break; - case EM_AMDGPU: { + case EM_AMDGPU: { // TODO: This part of logic needs to be updated to reflect the table on the llvm website unsigned int ef_amdgpu_mach = 0x000000ff & file->e_flags(); - switch(ef_amdgpu_mach){ - case 0x33: case 0x34: case 0x35: case 0x36: case 0x37: case 0x38: - arch = Dyninst::Arch_amdgpu_rdna; + switch(ef_amdgpu_mach){ + case 0x40: + arch = Dyninst::Arch_amdgpu_gfx940; break; - case 0x28: case 0x29: case 0x2a: case 0x2b: case 0x2c: case 0x2d: case 0x2e: case 0x2f: case 0x30: case 0x31: - arch = Dyninst::Arch_amdgpu_vega; + case 0x3f: + arch = Dyninst::Arch_amdgpu_gfx90a; break; - case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17: case 0x18: - case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f: - assert(0 && "reserved for r600 architecture"); - case 0x27: case 0x32 : case 0x39: - assert(0 && "reserved"); - default: - assert(0 && "probably won't be supported"); - } + case 0x30: + case 0x28: case 0x29: case 0x2a: case 0x2b: case 0x2c: case 0x2d: case 0x2e: case 0x2f: case 0x31: + arch = Dyninst::Arch_amdgpu_gfx908; + break; + case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17: case 0x18: + case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f: + assert(0 && "reserved for r600 architecture"); + case 0x27: case 0x32 : case 0x39: + assert(0 && "reserved"); + default: + assert(0 && "probably won't be supported"); + } break; } case EM_INTEL_GEN9: arch = Arch_intelGen9; break; + case EM_INTELGT: + arch = Arch_intelGen9; // temporary for compatibility + break; default: assert(0 && "Unsupported archiecture in ELF file."); return false; diff --git a/dwarf/src/dwarfResult.C b/dwarf/src/dwarfResult.C index c840535322..ee7dfcfd18 100644 --- a/dwarf/src/dwarfResult.C +++ b/dwarf/src/dwarfResult.C @@ -33,8 +33,8 @@ #include "dwarfFrameParser.h" #include "ProcReader.h" #include "dyntypes.h" -#include "dyn_regs.h" -#include "Types.h" +#include "registers/MachRegister.h" +#include "registers/abstract_regs.h" #include "debug_common.h" #include #include "debug_common.h" @@ -43,7 +43,7 @@ using namespace Dyninst; using namespace DwarfDyninst; using namespace std; -#define CHECK_OPER(n) if (operands.size() < n) { error = true; break; } +#define CHECK_OPER(n) do { if (operands.size() < (n)) { error = true; return; } } while (0) void SymbolicDwarfResult::pushReg(MachRegister reg) { dwarf_printf("\t\tPush %s\n", reg.name().c_str()); diff --git a/dwarf/src/dwarf_subrange.cpp b/dwarf/src/dwarf_subrange.cpp new file mode 100644 index 0000000000..7a17ad74be --- /dev/null +++ b/dwarf/src/dwarf_subrange.cpp @@ -0,0 +1,206 @@ +/* + * See the dyninst/COPYRIGHT file for copyright information. + * + * We provide the Paradyn Tools (below described as "Paradyn") + * on an AS IS basis, and do not warrant its validity or performance. + * We reserve the right to update, modify, or discontinue this + * software at any time. We shall have no obligation to supply such + * updates or modifications or any other form of support to you. + * + * By your use of Paradyn, you understand and agree that we (or any + * other person or entity with proprietary rights in Paradyn) are + * under no obligation to provide either maintenance services, + * update services, notices of latent defects, or correction of + * defects for Paradyn. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "dwarf_subrange.h" + +namespace { + +Dwarf_Die *get_type(Dwarf_Die *die, Dwarf_Die *result) { + Dwarf_Attribute scratch_attr; + dwarf_attr_integrate(die, DW_AT_type, &scratch_attr); + Dwarf_Die *type = dwarf_formref_die(&scratch_attr, result); + + if (!type || dwarf_peel_type(type, type) != 0) + return nullptr; + + return type; +} + +bool is_signed(Dwarf_Die *die) { + Dwarf_Attribute attr; + Dwarf_Die scratch; + if (dwarf_attr(get_type(die, &scratch), DW_AT_encoding, &attr)) { + Dwarf_Word encoding; + if (dwarf_formudata(&attr, &encoding) == 0) + return encoding == DW_ATE_signed || encoding == DW_ATE_signed_char; + } + return false; +} +} // namespace + +namespace Dyninst { +namespace DwarfDyninst { + +static dwarf_result upper_bound(Dwarf_Die *die) { + Dwarf_Attribute attr; + if (dwarf_attr_integrate(die, DW_AT_upper_bound, &attr)) { + if (is_signed(die)) { + Dwarf_Sword upper; + if (dwarf_formsdata(&attr, &upper) != 0) + return dwarf_error{}; + return upper; + } + Dwarf_Word unsigned_upper; + if (dwarf_formudata(&attr, &unsigned_upper) != 0) + return dwarf_error{}; + return unsigned_upper; + } + + // Nothing was found, but there was no error + return dwarf_result{}; +} + +static dwarf_result lower_bound(Dwarf_Die *die) { + Dwarf_Attribute attr; + if (dwarf_attr_integrate(die, DW_AT_lower_bound, &attr)) { + if (is_signed(die)) { + Dwarf_Sword lower; + if (dwarf_formsdata(&attr, &lower) != 0) + return dwarf_error{}; + return lower; + } + Dwarf_Word unsigned_lower; + if (dwarf_formudata(&attr, &unsigned_lower) != 0) + return dwarf_error{}; + return unsigned_lower; + } + + // Nothing was found, but there was no error + return dwarf_result{}; +} + +static dwarf_result lower_bound_by_language(Dwarf_Die *die) { + int lang = dwarf_srclang(die); + if (lang != -1) { + Dwarf_Sword lower; + if (dwarf_default_lower_bound(lang, &lower) != 0) + return dwarf_error{}; + return lower; + } + + // Nothing was found, but there was no error + return dwarf_result{}; +} + +static dwarf_result length_from_count(Dwarf_Die *die) { + Dwarf_Attribute attr; + if (dwarf_attr_integrate(die, DW_AT_count, &attr)) { + Dwarf_Word count; + if (dwarf_formudata(&attr, &count) != 0) + return dwarf_error{}; + return count; + } + + // Nothing was found, but there was no error + return dwarf_result{}; +} + +dwarf_bounds dwarf_subrange_bounds(Dwarf_Die *die) { + /* + * DWARF5 - Section 5.13 Subrange Type Entries + * + * The subrange entry may have the attributes DW_AT_lower_bound and + * DW_AT_upper_bound to specify, respectively, the lower and upper + * bound values of the subrange. + */ + dwarf_bounds bounds{lower_bound(die), upper_bound(die)}; + + // Don't continue if we encountered an error in either lookup + if (!bounds.lower || !bounds.upper) { + return bounds; + } + + // If the lower bound value is missing, the value is assumed to + // be a language-dependent default constant + if (!bounds.lower.value) { + bounds.lower = lower_bound_by_language(die); + + // If there was a dwarf error, bail out + if (!bounds.lower) { + return bounds; + } + } + + /* + * The DW_AT_upper_bound attribute may be replaced by a DW_AT_count + * attribute, whose value describes the number of elements in the + * subrange rather than the value of the last element. + */ + auto count = length_from_count(die); + + // If there was a dwarf error, explicitly mark the upper bound as bad + if (!count) { + bounds.upper = dwarf_error{}; + return bounds; + } + + if (count.value) { + auto const lb = [&bounds]() { + // If we have a lower bound, use it + if (bounds.lower.value) return bounds.lower.value.get(); + + // Otherwise, assume the array is zero-based + return static_cast(0); + }(); + bounds.upper = dwarf_result{lb + count.value.get() - static_cast(1)}; + } + + // If the upper bound and count are missing, then the upper bound value is unknown. + return bounds; +} + +dwarf_result dwarf_subrange_length_from_enum(Dwarf_Die *die) { + /* We have to find the DW_TAG_enumerator child with the + highest value to know the array's element count. */ + Dwarf_Die enum_child; + int has_children = dwarf_child(die, &enum_child); + if (has_children < 0) + return dwarf_error{}; + if (has_children > 0) { + Dwarf_Attribute attr; + Dwarf_Word count{}; + do { + if (dwarf_tag(&enum_child) == DW_TAG_enumerator) { + dwarf_attr_integrate(&enum_child, DW_AT_const_value, &attr); + Dwarf_Word value; + if (dwarf_formudata(&attr, &value) != 0) + return dwarf_error{}; + if (value >= count) + count = value + 1; + } + } while (dwarf_siblingof(&enum_child, &enum_child) > 0); + return count; + } + + // Nothing was found, but there was no error + return dwarf_result{}; +} +} // namespace DwarfDyninst +} // namespace Dyninst diff --git a/dwarf/src/dwarf_subrange.h b/dwarf/src/dwarf_subrange.h new file mode 100644 index 0000000000..0764fc3e56 --- /dev/null +++ b/dwarf/src/dwarf_subrange.h @@ -0,0 +1,58 @@ +/* + * See the dyninst/COPYRIGHT file for copyright information. + * + * We provide the Paradyn Tools (below described as "Paradyn") + * on an AS IS basis, and do not warrant its validity or performance. + * We reserve the right to update, modify, or discontinue this + * software at any time. We shall have no obligation to supply such + * updates or modifications or any other form of support to you. + * + * By your use of Paradyn, you understand and agree that we (or any + * other person or entity with proprietary rights in Paradyn) are + * under no obligation to provide either maintenance services, + * update services, notices of latent defects, or correction of + * defects for Paradyn. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "util.h" +#include +#include +#include + +namespace Dyninst { +namespace DwarfDyninst { + +struct dwarf_error {}; + +struct dwarf_result { + dyncompat::optional value; + bool error = false; + dwarf_result() = default; + dwarf_result(Dwarf_Word t) : value{t} {} + dwarf_result(dwarf_error) : error{true} {} + explicit operator bool() const { return !error; } +}; + +struct dwarf_bounds { + dwarf_result lower, upper; +}; + +DYNDWARF_EXPORT dwarf_bounds dwarf_subrange_bounds(Dwarf_Die *die); +DYNDWARF_EXPORT dwarf_result dwarf_subrange_length_from_enum(Dwarf_Die *die); + +} // namespace DwarfDyninst +} // namespace Dyninst diff --git a/dynC_API/CMakeLists.txt b/dynC_API/CMakeLists.txt index 9c0d49605e..e88bd56c7f 100644 --- a/dynC_API/CMakeLists.txt +++ b/dynC_API/CMakeLists.txt @@ -1,17 +1,32 @@ +include_guard(GLOBAL) -file(GLOB SRC_LIST "src/*.C") +include(DyninstLibrary) -include_directories(h - src - ${PROJECT_SOURCE_DIR}/dyninstAPI/src - ${PROJECT_SOURCE_DIR}/proccontrol/h +# dynC requires symtabAPI +if(LIGHTWEIGHT_SYMTAB) + message(STATUS "LIGHTWEIGHT_SYMTAB enabled; dynC_API not built.") + return() +endif() + +set(_public_headers h/dynC.h h/snippetGen.h) + +set(_private_headers src/dynC.tab.h) + +set(_sources src/dynC.C src/dynC.tab.C src/lex.dynC.C src/snippetGen.C) + +# cmake-format: off +dyninst_library( + dynC_API + PUBLIC_HEADER_FILES ${_public_headers} + PRIVATE_HEADER_FILES ${_private_headers} + SOURCE_FILES ${_sources} + DEFINES DYNC_EXPORTS + DYNINST_DEPS common dyninstAPI symtabAPI ) +# cmake-format: on -set_source_files_properties(${SRC_LIST} PROPERTIES LANGUAGE CXX) -add_definitions(-DDYNC_EXPORTS) -if(WIN32) -add_definitions(-DYY_NO_UNISTD_H) +if(DYNINST_OS_Windows) + foreach(t ${dynC_API_TARGETS}) + target_compile_definitions(${t} PRIVATE "YY_NO_UNISTD_H") + endforeach() endif() - -dyninst_library(dynC_API dyninstAPI) -target_link_private_libraries(dynC_API ${Boost_LIBRARIES}) diff --git a/dynC_API/doc/dynC_API.pdf b/dynC_API/doc/dynC_API.pdf index be663e32ce..80dae9366f 100644 Binary files a/dynC_API/doc/dynC_API.pdf and b/dynC_API/doc/dynC_API.pdf differ diff --git a/dynC_API/h/dynC.h b/dynC_API/h/dynC.h index e7baf9c437..ada9a39f6b 100644 --- a/dynC_API/h/dynC.h +++ b/dynC_API/h/dynC.h @@ -39,6 +39,7 @@ #include #include #include +#include #if !defined(DYNC_EXPORT) #if defined(_MSC_VER) diff --git a/dynC_API/h/snippetGen.h b/dynC_API/h/snippetGen.h index afa9376059..190d9abcff 100644 --- a/dynC_API/h/snippetGen.h +++ b/dynC_API/h/snippetGen.h @@ -38,6 +38,7 @@ #include "BPatch.h" #include #include +#include @@ -65,7 +66,7 @@ class SnippetGenerator{ private: std::stringstream lastError; - SGError lastErrorInfo; + SGError lastErrorInfo{}; BPatch_point *point; BPatch_addressSpace *addSpace; BPatch_image *image; diff --git a/dynC_API/make.test.module.tmpl b/dynC_API/make.test.module.tmpl deleted file mode 100644 index fc4e2fa4e0..0000000000 --- a/dynC_API/make.test.module.tmpl +++ /dev/null @@ -1,39 +0,0 @@ -# -# Common makefile template for dyninst Tests. This file is not intended to -# be a useful Makefile in isolation; instead, it should be included -# from within an architecture-specific Makefile. -# -# $Id: make.module.tmpl,v 1.26 2008/02/20 08:31:02 jaw Exp $ -# - -SUITE_NAME = DynC -RELEASE_NUM = 5.00 -#BUILD_MARK should be (re-)defined in core/make.config.local rather than here! - -SRCS += ../$(TARGET).C - -IFLAGS += -I$(TO_CORE)/dyninstAPI/h -IFLAGS += -I$(TO_CORE)/dyninstAPI/src -IFLAGS += -I$(TO_CORE)/symtabAPI/h -IFLAGS += -I$(TO_CORE)/dynutil/h -IFLAGS += -I$(TO_CORE)/commandAPI/h -IFLAGS += -I$(TO_CORE)/commandAPI/src -IFLAGS += -I$(TO_CORE)/instructionAPI/h - -CXXFLAGS += $(BASICWARNINGS) -CFLAGS += $(BASICWARNINGS) - -# GCC has a new mangled name squisher (-fsquangle) which can be -# set to "on" by default. This causes linker problems, so we -# default to "off". - -ifdef GCC_2_95 -CFLAGS += -fno-squangle -CXXFLAGS += -fno-squangle -endif - -LIBS += -ldyninstAPI -lsymtabAPI -lcommon -L$(TO_CORE)/dynCAPI/$(PLATFORM) -ldynCAPI - -SYSLIBS += -liberty -L$(TCLTK_LIB_DIR) $(TCL_LIB) - -all: $(TARGET) diff --git a/dynC_API/src/C.l b/dynC_API/src/C.l index e941866d37..7f70e6b673 100644 --- a/dynC_API/src/C.l +++ b/dynC_API/src/C.l @@ -22,6 +22,14 @@ IS(u|U|l|L)* #include "dynC.tab.h" #include "snippetGen.h" #include "compiler_annotations.h" +#include "compiler_diagnostics.h" + + +// clang warns of an unneeded internal declaration for yyinput. Since +// yyinput is generated by flex, just suppress it for the whole file. +#ifdef __clang__ +DYNINST_DIAGNOSTIC_SUPPRESS("-Wunneeded-internal-declaration") +#endif void *dynCalloc (yy_size_t size ) DYNINST_MALLOC_ANNOTATION; diff --git a/dynC_API/src/dynC.tab.C b/dynC_API/src/dynC.tab.C index 5eba6a040d..b28f40da48 100644 --- a/dynC_API/src/dynC.tab.C +++ b/dynC_API/src/dynC.tab.C @@ -83,6 +83,7 @@ +#include #include #include #include diff --git a/dynC_API/src/lex.dynC.C b/dynC_API/src/lex.dynC.C index 8ce63cfb14..f98712de42 100644 --- a/dynC_API/src/lex.dynC.C +++ b/dynC_API/src/lex.dynC.C @@ -916,6 +916,14 @@ char *dynCtext; #include "dynC.tab.h" #include "snippetGen.h" #include "compiler_annotations.h" +#include "compiler_diagnostics.h" + + +// clang warns of an unneeded internal declaration for yyinput. Since +// yyinput is generated by flex, just suppress it for the whole file. +#ifdef __clang__ +DYNINST_DIAGNOSTIC_SUPPRESS("-Wunneeded-internal-declaration") +#endif void *dynCalloc (yy_size_t size ) DYNINST_MALLOC_ANNOTATION; diff --git a/dynC_API/src/snippetGen.C b/dynC_API/src/snippetGen.C index 9dac35b8c6..f38f04e15b 100644 --- a/dynC_API/src/snippetGen.C +++ b/dynC_API/src/snippetGen.C @@ -28,6 +28,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ #include "snippetGen.h" +#include "dyntypes.h" extern "C" { void getErrorBase(char *errbase, int length); diff --git a/dynC_API/tests/i386-unknown-linux2.4/Makefile b/dynC_API/tests/i386-unknown-linux2.4/Makefile deleted file mode 100644 index 53a2265345..0000000000 --- a/dynC_API/tests/i386-unknown-linux2.4/Makefile +++ /dev/null @@ -1,36 +0,0 @@ -BASE = -DYNINST_ROOT = ../../../.. -CXX = g++ -CXXFLAGS = -g -Wall -Dos_linux=24 -Wall -fno-inline -INCLUDE = -LDFLAGS = - -PLATFORM = i386-unknown-linux2.4 -DYNLDFLAGS = -L/p/paradyn/packages/libelf/lib\ - -L/p/paradyn/packages/libdwarf/lib\ - -L$(DYNINST_ROOT)/$(PLATFORM)/lib\ - -lelf -ldwarf -lcommon -linstructionAPI -lsymtabAPI\ - -lparseAPI -ldyninstAPI -ldynC_API -DYNINCLUDE = -I$(DYNINST_ROOT)/dyninst/dyninstAPI/h -I$(DYNINST_ROOT)/include - -#DYNCXXFLAGS += -Dos_linux=24 -Wall -o -Darch_x86_64 - -TARG = myMutatee myMutator -#V = @ #Verbose (comment to make verbose) - -all: $(TARG) - -%.o:../%.cpp - @echo + cc $< - $(V)$(CXX) -c $(CXXFLAGS) $(INCLUDE) $(DYNINCLUDE) -o $@ $< - -myMutatee: testMutatee.o - @echo + ld $@ - $(V)$(CXX) $(CXXFLAGS) $(LDFLAGS) -o $@ $^ - -myMutator: testMutator.o - @echo + ld $@ - $(V)$(CXX) $(CXXFLAGS) $(LDFLAGS) $(DYNLDFLAGS) -o $@ $^ - -clean: - rm -f *.o core.* $(TARG) diff --git a/dynC_API/tests/i386-unknown-nt4.0/Makefile b/dynC_API/tests/i386-unknown-nt4.0/Makefile deleted file mode 100644 index 10089ddf72..0000000000 --- a/dynC_API/tests/i386-unknown-nt4.0/Makefile +++ /dev/null @@ -1,36 +0,0 @@ -BASE = -DYNINST_ROOT = ../../../.. -CXX = g++ -CXXFLAGS = -g -Wall -Dos_linux=24 -Wall -Darch_x86_64 -fno-inline -INCLUDE = -LDFLAGS = - -PLATFORM = i386-unknown-nt4.0 -DYNLDFLAGS = -L/p/paradyn/packages/libelf/lib\ - -L/p/paradyn/packages/libdwarf/lib\ - -L$(DYNINST_ROOT)/$(PLATFORM)/lib\ - -lelf -ldwarf -lcommon -linstructionAPI -lsymtabAPI\ - -lparseAPI -ldyninstAPI -ldynC_API -DYNINCLUDE = -I$(DYNINST_ROOT)/dyninst/dyninstAPI/h -I$(DYNINST_ROOT)/include - -#DYNCXXFLAGS += -Dos_linux=24 -Wall -o -Darch_x86_64 - -TARG = myMutatee myMutator -#V = @ #Verbose (comment to make verbose) - -all: $(TARG) - -%.o:../%.cpp - @echo + cc $< - $(V)$(CXX) -c $(CXXFLAGS) $(INCLUDE) $(DYNINCLUDE) -o $@ $< - -myMutatee: testMutatee.o - @echo + ld $@ - $(V)$(CXX) $(CXXFLAGS) $(LDFLAGS) -o $@ $^ - -myMutator: testMutator.o - @echo + ld $@ - $(V)$(CXX) $(CXXFLAGS) $(LDFLAGS) $(DYNLDFLAGS) -o $@ $^ - -clean: - rm -f *.o core.* $(TARG) diff --git a/dynC_API/tests/i386-unknown-winXP/Makefile b/dynC_API/tests/i386-unknown-winXP/Makefile deleted file mode 100644 index 170bbf90cd..0000000000 --- a/dynC_API/tests/i386-unknown-winXP/Makefile +++ /dev/null @@ -1,36 +0,0 @@ -BASE = -DYNINST_ROOT = ../../../.. -CXX = g++ -CXXFLAGS = -g -Wall -Dos_linux=24 -Wall -Darch_x86_64 -fno-inline -INCLUDE = -LDFLAGS = - -PLATFORM = i386-unknown-winXP -DYNLDFLAGS = -L/p/paradyn/packages/libelf/lib\ - -L/p/paradyn/packages/libdwarf/lib\ - -L$(DYNINST_ROOT)/$(PLATFORM)/lib\ - -lelf -ldwarf -lcommon -linstructionAPI -lsymtabAPI\ - -lparseAPI -ldyninstAPI -ldynC_API -DYNINCLUDE = -I$(DYNINST_ROOT)/dyninst/dyninstAPI/h -I$(DYNINST_ROOT)/include - -#DYNCXXFLAGS += -Dos_linux=24 -Wall -o -Darch_x86_64 - -TARG = myMutatee myMutator -#V = @ #Verbose (comment to make verbose) - -all: $(TARG) - -%.o:../%.cpp - @echo + cc $< - $(V)$(CXX) -c $(CXXFLAGS) $(INCLUDE) $(DYNINCLUDE) -o $@ $< - -myMutatee: testMutatee.o - @echo + ld $@ - $(V)$(CXX) $(CXXFLAGS) $(LDFLAGS) -o $@ $^ - -myMutator: testMutator.o - @echo + ld $@ - $(V)$(CXX) $(CXXFLAGS) $(LDFLAGS) $(DYNLDFLAGS) -o $@ $^ - -clean: - rm -f *.o core.* $(TARG) diff --git a/dynC_API/tests/ppc32_linux/Makefile b/dynC_API/tests/ppc32_linux/Makefile deleted file mode 100644 index a7d3dd643f..0000000000 --- a/dynC_API/tests/ppc32_linux/Makefile +++ /dev/null @@ -1,36 +0,0 @@ -BASE = -DYNINST_ROOT = ../../../.. -CXX = g++ -CXXFLAGS = -g -Wall -Dos_linux=24 -Wall -Darch_x86_64 -fno-inline -INCLUDE = -LDFLAGS = - -PLATFORM = ppc32_linux -DYNLDFLAGS = -L/p/paradyn/packages/libelf/lib\ - -L/p/paradyn/packages/libdwarf/lib\ - -L$(DYNINST_ROOT)/$(PLATFORM)/lib\ - -lelf -ldwarf -lcommon -linstructionAPI -lsymtabAPI\ - -lparseAPI -ldyninstAPI -ldynC_API -DYNINCLUDE = -I$(DYNINST_ROOT)/dyninst/dyninstAPI/h -I$(DYNINST_ROOT)/include - -#DYNCXXFLAGS += -Dos_linux=24 -Wall -o -Darch_x86_64 - -TARG = myMutatee myMutator -#V = @ #Verbose (comment to make verbose) - -all: $(TARG) - -%.o:../%.cpp - @echo + cc $< - $(V)$(CXX) -c $(CXXFLAGS) $(INCLUDE) $(DYNINCLUDE) -o $@ $< - -myMutatee: testMutatee.o - @echo + ld $@ - $(V)$(CXX) $(CXXFLAGS) $(LDFLAGS) -o $@ $^ - -myMutator: testMutator.o - @echo + ld $@ - $(V)$(CXX) $(CXXFLAGS) $(LDFLAGS) $(DYNLDFLAGS) -o $@ $^ - -clean: - rm -f *.o core.* $(TARG) diff --git a/dynC_API/tests/ppc64_linux/Makefile b/dynC_API/tests/ppc64_linux/Makefile deleted file mode 100644 index 02317ead95..0000000000 --- a/dynC_API/tests/ppc64_linux/Makefile +++ /dev/null @@ -1,36 +0,0 @@ -BASE = -DYNINST_ROOT = ../../../.. -CXX = g++ -CXXFLAGS = -g -Wall -Dos_linux=24 -Wall -Darch_x86_64 -fno-inline -INCLUDE = -LDFLAGS = - -PLATFORM = ppc64_linux -DYNLDFLAGS = -L/p/paradyn/packages/libelf/lib\ - -L/p/paradyn/packages/libdwarf/lib\ - -L$(DYNINST_ROOT)/$(PLATFORM)/lib\ - -lelf -ldwarf -lcommon -linstructionAPI -lsymtabAPI\ - -lparseAPI -ldyninstAPI -ldynC_API -DYNINCLUDE = -I$(DYNINST_ROOT)/dyninst/dyninstAPI/h -I$(DYNINST_ROOT)/include - -#DYNCXXFLAGS += -Dos_linux=24 -Wall -o -Darch_x86_64 - -TARG = myMutatee myMutator -#V = @ #Verbose (comment to make verbose) - -all: $(TARG) - -%.o:../%.cpp - @echo + cc $< - $(V)$(CXX) -c $(CXXFLAGS) $(INCLUDE) $(DYNINCLUDE) -o $@ $< - -myMutatee: testMutatee.o - @echo + ld $@ - $(V)$(CXX) $(CXXFLAGS) $(LDFLAGS) -o $@ $^ - -myMutator: testMutator.o - @echo + ld $@ - $(V)$(CXX) $(CXXFLAGS) $(LDFLAGS) $(DYNLDFLAGS) -o $@ $^ - -clean: - rm -f *.o core.* $(TARG) diff --git a/dynC_API/tests/testMutatee.cpp b/dynC_API/tests/testMutatee.cpp deleted file mode 100644 index 9183caa087..0000000000 --- a/dynC_API/tests/testMutatee.cpp +++ /dev/null @@ -1,62 +0,0 @@ -// myMutatee - -#include -int hi = 0; -int zarray[0]; -int array[5] = {1,2,3,4,5}; -int array2[5] = {6, 7, 8, 9, 10}; -int arrayField = array[2]; -struct myStructType{ - int i; - char *s; - char *sa[4]; -}mystruct = {3, "house", {"how", "now", "brown", "cow"}}; -//int i = 232; -int count(int i); - -int zomg = 2; - -int main(){ - - int i = 0; - int r = 0; - while (i < 10){ - i = count(i); - ++hi; - r = hi * 10; - } - return 0; -} - -void hello(){ -/* - using std::cout; - using std::endl; - cout << "hello!" << endl; -*/ -} - -int count(int i) { - using std::cout; - using std::endl; - if(i % 2 == 0){hello();} -// cout << "The current count is " << i << endl; - array[i % 5]++; - return i + 1; -} - -int count(int i, char *n){ - printf(n); - return i + 1; -} - -int printfWrapper(char *s){ - printf(s); - return 1; -} - -int count(char *s){ - printf("%s\n",s); - return 1; -} - diff --git a/dynC_API/tests/testMutator.cpp b/dynC_API/tests/testMutator.cpp deleted file mode 100644 index baf3017780..0000000000 --- a/dynC_API/tests/testMutator.cpp +++ /dev/null @@ -1,135 +0,0 @@ -//tester.C -#include -#include -#include - -#include "dynC.h" -#include "BPatch.h" -#include "BPatch_process.h" -#include "BPatch_snippet.h" -#include "BPatch_function.h" - -#define STATEMENT_PATH "../testStatements" -#define STATEMENT_PATH_2 "../testStatements2" -const char *MUTATEE_PATH = "myMutatee"; -const char *MUTATEE_ARGS[3]; -const char *MODULE_NAME = "testMutatee.cpp"; - - -BPatch bpatch; - -int main(){ - - using std::string; - using std::ifstream; - using std::cout; - using std::endl; - using std::getline; - - ifstream myfile(STATEMENT_PATH); - ifstream myfile2(STATEMENT_PATH_2); - - FILE *myCFILE = fopen(STATEMENT_PATH, "r"); - -// cout << "Starting binary " << MUTATEE_PATH << "... "; - BPatch_addressSpace * appProc; - bool rewrite = false; - if(rewrite){ - appProc = bpatch.openBinary(MUTATEE_PATH, true); - }else{ - appProc = bpatch.processCreate(MUTATEE_PATH, MUTATEE_ARGS); - } -// cout << "complete" << endl; - if (!appProc) return -1; - - BPatch_image *appImage = appProc->getImage(); - BPatch_module *mutatee = appImage->findModule(MODULE_NAME); - - if (mutatee == NULL){cout << "Bad Mutatee!" << endl;} - - const std::vector * functions = mutatee->getProcedures(); - - - appProc->malloc(*appImage->findType("long"), std::string("globalVar")); - - - std::vector * entry_points = (*functions)[0]->findPoint(BPatch_entry); - std::vector * exit_points = (*functions)[0]->findPoint(BPatch_exit);; - - for(unsigned int n = 1; n < functions->size(); n++){ - entry_points->push_back((*(*functions)[n]->findPoint(BPatch_entry))[0]); - exit_points->push_back((*(*functions)[n]->findPoint(BPatch_exit))[0]); - } - - -///////////////////////////////////////////////////////// - std::map *entry_snippets, exit_snippets; - entry_snippets = dynC_API::createSnippet(myCFILE, *entry_points); -// BPatch_snippet *testSn = dynC_API::createSnippet(fileString, *(*entry_points)[0]); - if(entry_snippets == NULL){ - fprintf(stderr, "entry_snippets is null.\n"); - exit(-1); - } - std::map::iterator it; - for(it = entry_snippets->begin(); it != entry_snippets->end(); ++it){ - if((*it).first == NULL){ - fprintf(stderr, "point is null.\n"); - exit(-1); - } - if((*it).second == NULL){ - fprintf(stderr, "snippet is null.\n"); - } else{ - printf("Snippet inserted\n"); - char funcName[512]; - printf("Point's function is %s.\n",((*it).first)->getFunction()->getName(funcName, 512)); - BPatchSnippetHandle *handle = appProc->insertSnippet(*(*it).second, *(*it).first); - printf("Handle is %s.\n", handle == NULL ? "null": "not null"); - } - } - -/* - for(unsigned int i = 0; i < entry_points->size(); ++i){ - if((*entry_points)[i] == NULL){ - printf("entry point %d is null \n", i); - } - BPatch_snippet *entrySnippet = dynC_API::createSnippet(fileString, *(*entry_points)[i]); - if (entrySnippet != NULL){ - appProc->insertSnippet(*entrySnippet, *(*entry_points)[i]); - } - BPatch_snippet *exitSnippet= dynC_API::createSnippet(fileString2.c_str(), *(*exit_points)[i], "exitSnippet"); - if (exitSnippet != NULL){ - appProc->insertSnippet(*exitSnippet, *(*exit_points)[i]); - } - -// BPatch_snippet *auxSnippet = dynC_API::createSnippet(&myfile2, "AuxSnippet"); - } -*/ -///////////////////////////////////////////////////////// - - -// appProc->insertSnippet(*auxSnippet, *exit_points); - - - printf("Snippet's inserted!\n"); - if(!rewrite){ - BPatch_process *aProc = static_cast(appProc); - aProc->continueExecution(); - - while (!aProc->isTerminated()){ - bpatch.waitForStatusChange(); - } - - if (aProc->terminationStatus() == ExitedNormally) { - printf("Application exited with code %d\n", aProc->getExitCode()); - } else if (aProc->terminationStatus() == ExitedViaSignal) { - printf("!!! Application exited with signal %d\n", aProc->getExitSignal()); - } else { - printf("Unknown application exit\n"); - } - }else{ - BPatch_binaryEdit *aProc = static_cast(appProc); - aProc->writeFile("myMutatee.out"); - } - - return 0; -} diff --git a/dynC_API/tests/testStatements b/dynC_API/tests/testStatements deleted file mode 100644 index 34820f2997..0000000000 --- a/dynC_API/tests/testStatements +++ /dev/null @@ -1 +0,0 @@ -func`printf("Hello.\n"); diff --git a/dynC_API/tests/testStatements2 b/dynC_API/tests/testStatements2 deleted file mode 100644 index 6e80446561..0000000000 --- a/dynC_API/tests/testStatements2 +++ /dev/null @@ -1 +0,0 @@ -inf`printf("Goodbye from %s.\n", dyninst`function_name); diff --git a/dynC_API/tests/testStatements3 b/dynC_API/tests/testStatements3 deleted file mode 100644 index e9805175d8..0000000000 --- a/dynC_API/tests/testStatements3 +++ /dev/null @@ -1,5 +0,0 @@ -//welcome to testStatements3 -{% -int f; -%} -//printf("{%d, %d, %d, %d, %d}\n", array[0], array[1], array[2], array[3], array[4]); diff --git a/dynC_API/tests/x86_64-unknown-linux2.4/Makefile b/dynC_API/tests/x86_64-unknown-linux2.4/Makefile deleted file mode 100644 index 2d72069eb7..0000000000 --- a/dynC_API/tests/x86_64-unknown-linux2.4/Makefile +++ /dev/null @@ -1,36 +0,0 @@ -BASE = -DYNINST_ROOT = ../../../.. -CXX = g++ -CXXFLAGS = -g -Wall -Dos_linux=24 -Wall -Darch_x86_64 -fno-inline -INCLUDE = -LDFLAGS = - -PLATFORM = x86_64-unknown-linux2.4 -DYNLDFLAGS = -L/p/paradyn/packages/libelf/lib\ - -L/p/paradyn/packages/libdwarf/lib\ - -L$(DYNINST_ROOT)/$(PLATFORM)/lib\ - -lelf -ldwarf -lcommon -linstructionAPI -lsymtabAPI\ - -lparseAPI -ldyninstAPI -ldynC_API -DYNINCLUDE = -I$(DYNINST_ROOT)/dyninst/dyninstAPI/h -I$(DYNINST_ROOT)/include - -#DYNCXXFLAGS += -Dos_linux=24 -Wall -o -Darch_x86_64 - -TARG = myMutatee myMutator -#V = @ #Verbose (comment to make verbose) - -all: $(TARG) - -%.o:../%.cpp - @echo + cc $< - $(V)$(CXX) -c $(CXXFLAGS) $(INCLUDE) $(DYNINCLUDE) -o $@ $< - -myMutatee: testMutatee.o - @echo + ld $@ - $(V)$(CXX) $(CXXFLAGS) $(LDFLAGS) -o $@ $^ - -myMutator: testMutator.o - @echo + ld $@ - $(V)$(CXX) $(CXXFLAGS) $(LDFLAGS) $(DYNLDFLAGS) -o $@ $^ - -clean: - rm -f *.o core.* $(TARG) diff --git a/dynC_API/tests/x86_64-unknown-linux2.4/foo.txt b/dynC_API/tests/x86_64-unknown-linux2.4/foo.txt deleted file mode 100644 index a39e1b8a17..0000000000 --- a/dynC_API/tests/x86_64-unknown-linux2.4/foo.txt +++ /dev/null @@ -1,254 +0,0 @@ -Starting binary myMutatee... complete -Entry to parseStabTypes for ld-linux-x86-64.so.2 - Parsing 0 stab entries -Entry to parseStabTypes for myMutatee - Parsing 0 stab entries -Type lookup for dynC_internal_0 returned (nil) - bpatch type is -findOrCreateVar(dynC_internal_0) returned 0x1c46e8f0 -Entry to parseStabTypes for libc.so.6 - Parsing 0 stab entries -Type lookup for array returned 0x1c46f4d0 - bpatch type is -findOrCreateVar(array) returned 0x1c459660 -findOrCreateVar(array) returned 0x1c459660 -Type lookup for hi returned 0x1bf6c160 int - bpatch type is int -findOrCreateVar(hi) returned 0x1c45e6b0 -findOrCreateVar(hi) returned 0x1c45e6b0 -findOrCreateVar(hi) returned 0x1c45e6b0 -findOrCreateVar(hi) returned 0x1c45e6b0 -Type lookup for dynC_mangled_i_TestSnippet_int[3]_local returned (nil) - bpatch type is -findOrCreateVar(dynC_mangled_i_TestSnippet_int[3]_local) returned 0x1c463480 -findOrCreateVar(dynC_internal_0) returned 0x1c46e8f0 -findOrCreateVar(dynC_internal_0) returned 0x1c46e8f0 -findOrCreateVar(dynC_mangled_i_TestSnippet_int[3]_local) returned 0x1c463480 -findOrCreateVar(array) returned 0x1c459660 -findOrCreateVar(array) returned 0x1c459660 -findOrCreateVar(hi) returned 0x1c45e6b0 -findOrCreateVar(hi) returned 0x1c45e6b0 -findOrCreateVar(hi) returned 0x1c45e6b0 -findOrCreateVar(hi) returned 0x1c45e6b0 -findOrCreateVar(dynC_mangled_i_TestSnippet_int[3]_local) returned 0x1c463480 -findOrCreateVar(dynC_internal_0) returned 0x1c46e8f0 -findOrCreateVar(dynC_internal_0) returned 0x1c46e8f0 -findOrCreateVar(dynC_mangled_i_TestSnippet_int[3]_local) returned 0x1c463480 -findOrCreateVar(array) returned 0x1c459660 -findOrCreateVar(array) returned 0x1c459660 -findOrCreateVar(hi) returned 0x1c45e6b0 -findOrCreateVar(hi) returned 0x1c45e6b0 -findOrCreateVar(hi) returned 0x1c45e6b0 -findOrCreateVar(hi) returned 0x1c45e6b0 -findOrCreateVar(dynC_mangled_i_TestSnippet_int[3]_local) returned 0x1c463480 -findOrCreateVar(dynC_internal_0) returned 0x1c46e8f0 -findOrCreateVar(dynC_internal_0) returned 0x1c46e8f0 -findOrCreateVar(dynC_mangled_i_TestSnippet_int[3]_local) returned 0x1c463480 -findOrCreateVar(array) returned 0x1c459660 -findOrCreateVar(array) returned 0x1c459660 -findOrCreateVar(hi) returned 0x1c45e6b0 -findOrCreateVar(hi) returned 0x1c45e6b0 -findOrCreateVar(hi) returned 0x1c45e6b0 -findOrCreateVar(hi) returned 0x1c45e6b0 -findOrCreateVar(dynC_mangled_i_TestSnippet_int[3]_local) returned 0x1c463480 -findOrCreateVar(dynC_internal_0) returned 0x1c46e8f0 -findOrCreateVar(dynC_internal_0) returned 0x1c46e8f0 -findOrCreateVar(dynC_mangled_i_TestSnippet_int[3]_local) returned 0x1c463480 -findOrCreateVar(array) returned 0x1c459660 -findOrCreateVar(array) returned 0x1c459660 -findOrCreateVar(hi) returned 0x1c45e6b0 -findOrCreateVar(hi) returned 0x1c45e6b0 -findOrCreateVar(hi) returned 0x1c45e6b0 -findOrCreateVar(hi) returned 0x1c45e6b0 -findOrCreateVar(dynC_mangled_i_TestSnippet_int[3]_local) returned 0x1c463480 -findOrCreateVar(dynC_internal_0) returned 0x1c46e8f0 -findOrCreateVar(dynC_internal_0) returned 0x1c46e8f0 -findOrCreateVar(dynC_mangled_i_TestSnippet_int[3]_local) returned 0x1c463480 -findOrCreateVar(array) returned 0x1c459660 -findOrCreateVar(array) returned 0x1c459660 -findOrCreateVar(hi) returned 0x1c45e6b0 -findOrCreateVar(hi) returned 0x1c45e6b0 -findOrCreateVar(hi) returned 0x1c45e6b0 -findOrCreateVar(hi) returned 0x1c45e6b0 -findOrCreateVar(dynC_mangled_i_TestSnippet_int[3]_local) returned 0x1c463480 -findOrCreateVar(dynC_internal_0) returned 0x1c46e8f0 -findOrCreateVar(dynC_internal_0) returned 0x1c46e8f0 -findOrCreateVar(dynC_mangled_i_TestSnippet_int[3]_local) returned 0x1c463480 -findOrCreateVar(array) returned 0x1c459660 -findOrCreateVar(array) returned 0x1c459660 -findOrCreateVar(hi) returned 0x1c45e6b0 -findOrCreateVar(hi) returned 0x1c45e6b0 -findOrCreateVar(hi) returned 0x1c45e6b0 -findOrCreateVar(hi) returned 0x1c45e6b0 -findOrCreateVar(dynC_mangled_i_TestSnippet_int[3]_local) returned 0x1c463480 -findOrCreateVar(dynC_internal_0) returned 0x1c46e8f0 -findOrCreateVar(dynC_internal_0) returned 0x1c46e8f0 -findOrCreateVar(dynC_mangled_i_TestSnippet_int[3]_local) returned 0x1c463480 -findOrCreateVar(array) returned 0x1c459660 -findOrCreateVar(array) returned 0x1c459660 -mangled = dynC_mangled_i_TestSnippet_int[3]_local -Array name = int -BPatch_DyninstAllocateArray: arrayName = dynC_mangled_i_TestSnippet_int[3]_local. typeName = int. size = 3. arrayTypeName = int[3]. -BPatch_variableExpr is null? no -BPatch_DyninstAllocateArray: Var type: int[3] -*** array (0x1c459660) (0x1c459660): -*** array (varExpr) -*** array (varExprGbl) -BPatch_variableExpr is null? no -BPatch_AppVar: varExpr type is: -BPatch_DyninstArrayRef: has replaceNode? false -BPatch_DyninstArrayRef: Arg[0] type:typeArray -*** hi (0x1c45e6b0) (0x1c45e6b0): -*** hi (varExpr) -*** hi (varExprGbl) -BPatch_variableExpr is null? no -BPatch_AppVar: varExpr type is: int -*** hi (0x1c45e6b0) (0x1c45e6b0): -*** hi (varExpr) -*** hi (varExprGbl) -BPatch_variableExpr is null? no -BPatch_AppVar: varExpr type is: int -*** array (0x1c459660) (0x1c459660): -*** array (varExpr) -*** array (varExprGbl) -BPatch_variableExpr is null? no -BPatch_AppVar: varExpr type is: -BPatch_DyninstArrayRef: has replaceNode? false -BPatch_DyninstArrayRef: Arg[0] type:typeArray -*** hi (0x1c45e6b0) (0x1c45e6b0): -*** hi (varExpr) -*** hi (varExprGbl) -BPatch_variableExpr is null? no -BPatch_AppVar: varExpr type is: int -*** hi (0x1c45e6b0) (0x1c45e6b0): -*** hi (varExpr) -*** hi (varExprGbl) -BPatch_variableExpr is null? no -BPatch_AppVar: varExpr type is: int -*** array (0x1c459660) (0x1c459660): -*** array (varExpr) -*** array (varExprGbl) -BPatch_variableExpr is null? no -BPatch_AppVar: varExpr type is: -BPatch_DyninstArrayRef: has replaceNode? false -BPatch_DyninstArrayRef: Arg[0] type:typeArray -*** hi (0x1c45e6b0) (0x1c45e6b0): -*** hi (varExpr) -*** hi (varExprGbl) -BPatch_variableExpr is null? no -BPatch_AppVar: varExpr type is: int -*** hi (0x1c45e6b0) (0x1c45e6b0): -*** hi (varExpr) -*** hi (varExprGbl) -BPatch_variableExpr is null? no -BPatch_AppVar: varExpr type is: int -*** array (0x1c459660) (0x1c459660): -*** array (varExpr) -*** array (varExprGbl) -BPatch_variableExpr is null? no -BPatch_AppVar: varExpr type is: -BPatch_DyninstArrayRef: has replaceNode? false -BPatch_DyninstArrayRef: Arg[0] type:typeArray -*** hi (0x1c45e6b0) (0x1c45e6b0): -*** hi (varExpr) -*** hi (varExprGbl) -BPatch_variableExpr is null? no -BPatch_AppVar: varExpr type is: int -*** hi (0x1c45e6b0) (0x1c45e6b0): -*** hi (varExpr) -*** hi (varExprGbl) -BPatch_variableExpr is null? no -BPatch_AppVar: varExpr type is: int -*** array (0x1c459660) (0x1c459660): -*** array (varExpr) -*** array (varExprGbl) -BPatch_variableExpr is null? no -BPatch_AppVar: varExpr type is: -BPatch_DyninstArrayRef: has replaceNode? false -BPatch_DyninstArrayRef: Arg[0] type:typeArray -*** hi (0x1c45e6b0) (0x1c45e6b0): -*** hi (varExpr) -*** hi (varExprGbl) -BPatch_variableExpr is null? no -BPatch_AppVar: varExpr type is: int -*** hi (0x1c45e6b0) (0x1c45e6b0): -*** hi (varExpr) -*** hi (varExprGbl) -BPatch_variableExpr is null? no -BPatch_AppVar: varExpr type is: int -*** array (0x1c459660) (0x1c459660): -*** array (varExpr) -*** array (varExprGbl) -BPatch_variableExpr is null? no -BPatch_AppVar: varExpr type is: -BPatch_DyninstArrayRef: has replaceNode? false -BPatch_DyninstArrayRef: Arg[0] type:typeArray -*** hi (0x1c45e6b0) (0x1c45e6b0): -*** hi (varExpr) -*** hi (varExprGbl) -BPatch_variableExpr is null? no -BPatch_AppVar: varExpr type is: int -*** hi (0x1c45e6b0) (0x1c45e6b0): -*** hi (varExpr) -*** hi (varExprGbl) -BPatch_variableExpr is null? no -BPatch_AppVar: varExpr type is: int -*** array (0x1c459660) (0x1c459660): -*** array (varExpr) -*** array (varExprGbl) -BPatch_variableExpr is null? no -BPatch_AppVar: varExpr type is: -BPatch_DyninstArrayRef: has replaceNode? false -BPatch_DyninstArrayRef: Arg[0] type:typeArray -*** hi (0x1c45e6b0) (0x1c45e6b0): -*** hi (varExpr) -*** hi (varExprGbl) -BPatch_variableExpr is null? no -BPatch_AppVar: varExpr type is: int -*** hi (0x1c45e6b0) (0x1c45e6b0): -*** hi (varExpr) -*** hi (varExprGbl) -BPatch_variableExpr is null? no -BPatch_AppVar: varExpr type is: int -*** array (0x1c459660) (0x1c459660): -*** array (varExpr) -*** array (varExprGbl) -BPatch_variableExpr is null? no -BPatch_AppVar: varExpr type is: -BPatch_DyninstArrayRef: has replaceNode? false -BPatch_DyninstAfindOrCreateVar(hi) returned 0x1c45e6b0 -findOrCreateVar(hi) returned 0x1c45e6b0 -findOrCreateVar(hi) returned 0x1c45e6b0 -findOrCreateVar(hi) returned 0x1c45e6b0 -findOrCreateVar(dynC_mangled_i_TestSnippet_int[3]_local) returned 0x1c463480 -Welcome to testMutatee.cpp! -4 -4 -4 -4 -4 -4 -4 -4 -4 -4 -4 -4 -4 -4 -4 -4 -4 -rrayRef: Arg[0] type:typeArray -*** hi (0x1c45e6b0) (0x1c45e6b0): -*** hi (varExpr) -*** hi (varExprGbl) -BPatch_variableExpr is null? no -BPatch_AppVar: varExpr type is: int -*** hi (0x1c45e6b0) (0x1c45e6b0): -*** hi (varExpr) -*** hi (varExprGbl) -BPatch_variableExpr is null? no -BPatch_AppVar: varExpr type is: int -Snippet's inserted! -Application exited with code 0 diff --git a/dyncompat/algorithm/string.hpp b/dyncompat/algorithm/string.hpp new file mode 100644 index 0000000000..226f66f3e2 --- /dev/null +++ b/dyncompat/algorithm/string.hpp @@ -0,0 +1,8 @@ +#ifndef DYNINST_DYNCOMPAT_ALGORITHM_STRING_HPP +#define DYNINST_DYNCOMPAT_ALGORITHM_STRING_HPP + +#include "string/case_conv.hpp" +#include "string/join.hpp" +#include "string/predicate.hpp" + +#endif diff --git a/dyncompat/algorithm/string/case_conv.hpp b/dyncompat/algorithm/string/case_conv.hpp new file mode 100644 index 0000000000..8e65755ad0 --- /dev/null +++ b/dyncompat/algorithm/string/case_conv.hpp @@ -0,0 +1,20 @@ +#ifndef DYNINST_DYNCOMPAT_ALGORITHM_STRING_CASE_CONV_HPP +#define DYNINST_DYNCOMPAT_ALGORITHM_STRING_CASE_CONV_HPP + +#include +#include +#include + +namespace dyncompat { +namespace algorithm { + +inline void trim_right(std::string& value) { + while(!value.empty() && std::isspace(static_cast(value.back())) != 0) { + value.pop_back(); + } +} + +} // namespace algorithm +} // namespace dyncompat + +#endif diff --git a/dyncompat/algorithm/string/classification.hpp b/dyncompat/algorithm/string/classification.hpp new file mode 100644 index 0000000000..899be97845 --- /dev/null +++ b/dyncompat/algorithm/string/classification.hpp @@ -0,0 +1,20 @@ +#ifndef DYNINST_DYNCOMPAT_ALGORITHM_STRING_CLASSIFICATION_HPP +#define DYNINST_DYNCOMPAT_ALGORITHM_STRING_CLASSIFICATION_HPP + +#include + +namespace dyncompat { + +struct is_graph_predicate { + bool operator()(char ch) const { + return std::isgraph(static_cast(ch)) != 0; + } +}; + +inline is_graph_predicate is_graph() { + return {}; +} + +} // namespace dyncompat + +#endif diff --git a/dyncompat/algorithm/string/find.hpp b/dyncompat/algorithm/string/find.hpp new file mode 100644 index 0000000000..afd4c3dde1 --- /dev/null +++ b/dyncompat/algorithm/string/find.hpp @@ -0,0 +1,17 @@ +#ifndef DYNINST_DYNCOMPAT_ALGORITHM_STRING_FIND_HPP +#define DYNINST_DYNCOMPAT_ALGORITHM_STRING_FIND_HPP + +#include + +namespace dyncompat { + +template +auto find_token(Range&& range, Predicate predicate) { + using std::begin; + using std::end; + return std::find_if(begin(range), end(range), predicate); +} + +} // namespace dyncompat + +#endif diff --git a/dyncompat/algorithm/string/join.hpp b/dyncompat/algorithm/string/join.hpp new file mode 100644 index 0000000000..0b4185dad1 --- /dev/null +++ b/dyncompat/algorithm/string/join.hpp @@ -0,0 +1,28 @@ +#ifndef DYNINST_DYNCOMPAT_ALGORITHM_STRING_JOIN_HPP +#define DYNINST_DYNCOMPAT_ALGORITHM_STRING_JOIN_HPP + +#include +#include + +namespace dyncompat { +namespace algorithm { + +template +std::string join(const Range& parts, const std::string& separator) { + std::ostringstream os; + auto it = parts.begin(); + if(it == parts.end()) { + return os.str(); + } + os << *it; + ++it; + for(; it != parts.end(); ++it) { + os << separator << *it; + } + return os.str(); +} + +} // namespace algorithm +} // namespace dyncompat + +#endif diff --git a/dyncompat/algorithm/string/predicate.hpp b/dyncompat/algorithm/string/predicate.hpp new file mode 100644 index 0000000000..25a9d447f2 --- /dev/null +++ b/dyncompat/algorithm/string/predicate.hpp @@ -0,0 +1,30 @@ +#ifndef DYNINST_DYNCOMPAT_ALGORITHM_STRING_PREDICATE_HPP +#define DYNINST_DYNCOMPAT_ALGORITHM_STRING_PREDICATE_HPP + +#include +#include +#include +#include + +namespace dyncompat { + +inline bool starts_with(std::string_view value, std::string_view prefix) { + return value.substr(0, prefix.size()) == prefix; +} + +inline bool ends_with(std::string_view value, std::string_view suffix) { + return value.size() >= suffix.size() && + value.substr(value.size() - suffix.size()) == suffix; +} + +inline bool iequals(std::string_view lhs, std::string_view rhs) { + return lhs.size() == rhs.size() && + std::equal(lhs.begin(), lhs.end(), rhs.begin(), rhs.end(), [](char a, char b) { + return std::tolower(static_cast(a)) == + std::tolower(static_cast(b)); + }); +} + +} // namespace dyncompat + +#endif diff --git a/dyncompat/any.hpp b/dyncompat/any.hpp new file mode 100644 index 0000000000..8abd3e428e --- /dev/null +++ b/dyncompat/any.hpp @@ -0,0 +1,14 @@ +#ifndef DYNINST_DYNCOMPAT_ANY_HPP +#define DYNINST_DYNCOMPAT_ANY_HPP + +#include + +namespace dyncompat { + +using any = std::any; +using bad_any_cast = std::bad_any_cast; +using std::any_cast; + +} // namespace dyncompat + +#endif diff --git a/dyncompat/assign/list_of.hpp b/dyncompat/assign/list_of.hpp new file mode 100644 index 0000000000..1fd4594c8b --- /dev/null +++ b/dyncompat/assign/list_of.hpp @@ -0,0 +1,83 @@ +#ifndef DYNINST_DYNCOMPAT_ASSIGN_LIST_OF_HPP +#define DYNINST_DYNCOMPAT_ASSIGN_LIST_OF_HPP + +#include +#include +#include +#include +#include +#include + +namespace dyncompat { +namespace assign { + +template +class list_builder { +public: + explicit list_builder(const T& value) : values_{value} {} + + list_builder& operator()(const T& value) { + values_.push_back(value); + return *this; + } + + operator std::vector() const { return std::vector(values_.begin(), values_.end()); } + + template + operator Container() const { + return Container(values_.begin(), values_.end()); + } + + template + Container convert_to_container() const { + return Container(values_.begin(), values_.end()); + } + +private: + std::vector values_; +}; + +template +list_builder> list_of(T&& value) { + return list_builder>(std::forward(value)); +} + +template +class map_builder { +public: + map_builder(const K& key, const V& value) { values_.emplace_back(key, value); } + + map_builder& operator()(const K& key, const V& value) { + values_.emplace_back(key, value); + return *this; + } + + operator std::map() const { return std::map(values_.begin(), values_.end()); } + + operator std::unordered_map() const { + return std::unordered_map(values_.begin(), values_.end()); + } + + template + operator Map() const { + return Map(values_.begin(), values_.end()); + } + + template + Map convert_to_container() const { + return Map(values_.begin(), values_.end()); + } + +private: + std::vector> values_; +}; + +template +map_builder, std::decay_t> map_list_of(K&& key, V&& value) { + return map_builder, std::decay_t>(std::forward(key), std::forward(value)); +} + +} // namespace assign +} // namespace dyncompat + +#endif diff --git a/dyncompat/assign/std/set.hpp b/dyncompat/assign/std/set.hpp new file mode 100644 index 0000000000..a0f70748b7 --- /dev/null +++ b/dyncompat/assign/std/set.hpp @@ -0,0 +1,6 @@ +#ifndef DYNINST_DYNCOMPAT_ASSIGN_STD_SET_HPP +#define DYNINST_DYNCOMPAT_ASSIGN_STD_SET_HPP + +#include "../list_of.hpp" + +#endif diff --git a/dyncompat/assign/std/vector.hpp b/dyncompat/assign/std/vector.hpp new file mode 100644 index 0000000000..dcf99e8b46 --- /dev/null +++ b/dyncompat/assign/std/vector.hpp @@ -0,0 +1,6 @@ +#ifndef DYNINST_DYNCOMPAT_ASSIGN_STD_VECTOR_HPP +#define DYNINST_DYNCOMPAT_ASSIGN_STD_VECTOR_HPP + +#include "../list_of.hpp" + +#endif diff --git a/dyncompat/atomic.hpp b/dyncompat/atomic.hpp new file mode 100644 index 0000000000..607bbbd687 --- /dev/null +++ b/dyncompat/atomic.hpp @@ -0,0 +1,22 @@ +#ifndef DYNINST_DYNCOMPAT_ATOMIC_HPP +#define DYNINST_DYNCOMPAT_ATOMIC_HPP + +#include + +namespace dyncompat { + +template +using atomic = std::atomic; + +using memory_order = std::memory_order; + +inline constexpr auto memory_order_relaxed = std::memory_order_relaxed; +inline constexpr auto memory_order_consume = std::memory_order_consume; +inline constexpr auto memory_order_acquire = std::memory_order_acquire; +inline constexpr auto memory_order_release = std::memory_order_release; +inline constexpr auto memory_order_acq_rel = std::memory_order_acq_rel; +inline constexpr auto memory_order_seq_cst = std::memory_order_seq_cst; + +} // namespace dyncompat + +#endif diff --git a/dyncompat/bind/bind.hpp b/dyncompat/bind/bind.hpp new file mode 100644 index 0000000000..5ea34ba0c8 --- /dev/null +++ b/dyncompat/bind/bind.hpp @@ -0,0 +1,15 @@ +#ifndef DYNINST_DYNCOMPAT_BIND_BIND_HPP +#define DYNINST_DYNCOMPAT_BIND_BIND_HPP + +#include + +namespace dyncompat { + +using std::bind; +using std::ref; + +namespace placeholders = std::placeholders; + +} // namespace dyncompat + +#endif diff --git a/dyncompat/checked_delete.hpp b/dyncompat/checked_delete.hpp new file mode 100644 index 0000000000..34b9418b3a --- /dev/null +++ b/dyncompat/checked_delete.hpp @@ -0,0 +1,6 @@ +#ifndef DYNINST_DYNCOMPAT_CHECKED_DELETE_HPP +#define DYNINST_DYNCOMPAT_CHECKED_DELETE_HPP + +#include "shared_ptr.hpp" + +#endif diff --git a/dyncompat/config.hpp b/dyncompat/config.hpp new file mode 100644 index 0000000000..7b5aebc859 --- /dev/null +++ b/dyncompat/config.hpp @@ -0,0 +1,10 @@ +#ifndef DYNINST_DYNCOMPAT_CONFIG_HPP +#define DYNINST_DYNCOMPAT_CONFIG_HPP + +#include "version.hpp" + +#if defined(_WIN32) || defined(_WIN64) +#define DYNCOMPAT_WINDOWS 1 +#endif + +#endif diff --git a/dyncompat/container_hash/hash.hpp b/dyncompat/container_hash/hash.hpp new file mode 100644 index 0000000000..70260471bc --- /dev/null +++ b/dyncompat/container_hash/hash.hpp @@ -0,0 +1,6 @@ +#ifndef DYNINST_DYNCOMPAT_CONTAINER_HASH_HASH_HPP +#define DYNINST_DYNCOMPAT_CONTAINER_HASH_HASH_HPP + +#include "../functional/hash.hpp" + +#endif diff --git a/dyncompat/core/enable_if.hpp b/dyncompat/core/enable_if.hpp new file mode 100644 index 0000000000..454ed3dc46 --- /dev/null +++ b/dyncompat/core/enable_if.hpp @@ -0,0 +1,13 @@ +#ifndef DYNINST_DYNCOMPAT_CORE_ENABLE_IF_HPP +#define DYNINST_DYNCOMPAT_CORE_ENABLE_IF_HPP + +#include + +namespace dyncompat { + +template +struct enable_if : std::enable_if {}; + +} // namespace dyncompat + +#endif diff --git a/dyncompat/crc.hpp b/dyncompat/crc.hpp new file mode 100644 index 0000000000..2c5041bca2 --- /dev/null +++ b/dyncompat/crc.hpp @@ -0,0 +1,34 @@ +#ifndef DYNINST_DYNCOMPAT_CRC_HPP +#define DYNINST_DYNCOMPAT_CRC_HPP + +#include +#include + +namespace dyncompat { + +class crc_32_type { +public: + crc_32_type() { reset(); } + + void reset() { crc_ = 0xffffffffu; } + + void process_bytes(const void* data, std::size_t size) { + const auto* bytes = static_cast(data); + for(std::size_t i = 0; i < size; ++i) { + crc_ ^= bytes[i]; + for(unsigned bit = 0; bit < 8; ++bit) { + const auto mask = static_cast(-(crc_ & 1u)); + crc_ = (crc_ >> 1u) ^ (0xedb88320u & mask); + } + } + } + + std::uint32_t checksum() const { return crc_ ^ 0xffffffffu; } + +private: + std::uint32_t crc_{0xffffffffu}; +}; + +} // namespace dyncompat + +#endif diff --git a/dyncompat/cstdint.hpp b/dyncompat/cstdint.hpp new file mode 100644 index 0000000000..3016e1205d --- /dev/null +++ b/dyncompat/cstdint.hpp @@ -0,0 +1,19 @@ +#ifndef DYNINST_DYNCOMPAT_CSTDINT_HPP +#define DYNINST_DYNCOMPAT_CSTDINT_HPP + +#include + +namespace dyncompat { + +using std::int8_t; +using std::int16_t; +using std::int32_t; +using std::int64_t; +using std::uint8_t; +using std::uint16_t; +using std::uint32_t; +using std::uint64_t; + +} // namespace dyncompat + +#endif diff --git a/dyncompat/dynamic_bitset.hpp b/dyncompat/dynamic_bitset.hpp new file mode 100644 index 0000000000..f0ffbe91c1 --- /dev/null +++ b/dyncompat/dynamic_bitset.hpp @@ -0,0 +1,209 @@ +#ifndef DYNINST_DYNCOMPAT_DYNAMIC_BITSET_HPP +#define DYNINST_DYNCOMPAT_DYNAMIC_BITSET_HPP + +#include +#include +#include +#include +#include +#include +#include +#include + +namespace dyncompat { + +template > +class dynamic_bitset { + static_assert(std::is_unsigned_v, "dynamic_bitset requires an unsigned block type"); + +public: + using block_type = Block; + using size_type = std::size_t; + + class reference { + public: + reference(dynamic_bitset& owner, size_type pos) : owner_(owner), pos_(pos) {} + + reference& operator=(bool value) { + owner_.set(pos_, value); + return *this; + } + + operator bool() const { return owner_.test(pos_); } + + private: + dynamic_bitset& owner_; + size_type pos_; + }; + + dynamic_bitset() = default; + + explicit dynamic_bitset(size_type size, unsigned long value = 0) + : size_(size), blocks_(block_count(size), 0) { + for(size_type i = 0; i < size_ && value != 0; ++i, value >>= 1u) { + if((value & 1u) != 0u) { + set(i); + } + } + } + + size_type size() const { return size_; } + bool empty() const { return size_ == 0; } + + reference operator[](size_type pos) { return reference(*this, pos); } + bool operator[](size_type pos) const { return test(pos); } + + dynamic_bitset& set() { + std::fill(blocks_.begin(), blocks_.end(), all_bits_set()); + trim_unused_bits(); + return *this; + } + + dynamic_bitset& set(size_type pos, bool value = true) { + assert(pos < size_); + const auto mask = block_type(1) << bit_offset(pos); + if(value) { + blocks_[block_index(pos)] |= mask; + } else { + blocks_[block_index(pos)] &= ~mask; + } + return *this; + } + + dynamic_bitset& reset() { + std::fill(blocks_.begin(), blocks_.end(), 0); + return *this; + } + + dynamic_bitset& reset(size_type pos) { + return set(pos, false); + } + + bool test(size_type pos) const { + assert(pos < size_); + return (blocks_[block_index(pos)] & (block_type(1) << bit_offset(pos))) != 0; + } + + size_type count() const { + size_type result = 0; + for(auto block : blocks_) { + while(block != 0) { + result += block & 1u; + block >>= 1u; + } + } + return result; + } + + dynamic_bitset& operator|=(const dynamic_bitset& other) { + resize_to_match(other); + for(size_type i = 0; i < blocks_.size(); ++i) { + blocks_[i] |= other.blocks_[i]; + } + trim_unused_bits(); + return *this; + } + + dynamic_bitset& operator&=(const dynamic_bitset& other) { + resize_to_match(other); + for(size_type i = 0; i < blocks_.size(); ++i) { + blocks_[i] &= other.blocks_[i]; + } + return *this; + } + + dynamic_bitset& operator^=(const dynamic_bitset& other) { + resize_to_match(other); + for(size_type i = 0; i < blocks_.size(); ++i) { + blocks_[i] ^= other.blocks_[i]; + } + trim_unused_bits(); + return *this; + } + + friend dynamic_bitset operator|(dynamic_bitset lhs, const dynamic_bitset& rhs) { + lhs |= rhs; + return lhs; + } + + friend dynamic_bitset operator&(dynamic_bitset lhs, const dynamic_bitset& rhs) { + lhs &= rhs; + return lhs; + } + + friend dynamic_bitset operator^(dynamic_bitset lhs, const dynamic_bitset& rhs) { + lhs ^= rhs; + return lhs; + } + + friend dynamic_bitset operator-(dynamic_bitset lhs, const dynamic_bitset& rhs) { + lhs &= ~rhs; + return lhs; + } + + friend dynamic_bitset operator~(dynamic_bitset value) { + for(auto& block : value.blocks_) { + block = ~block; + } + value.trim_unused_bits(); + return value; + } + + friend bool operator==(const dynamic_bitset& lhs, const dynamic_bitset& rhs) { + return lhs.size_ == rhs.size_ && lhs.blocks_ == rhs.blocks_; + } + + friend bool operator!=(const dynamic_bitset& lhs, const dynamic_bitset& rhs) { + return !(lhs == rhs); + } + + template + friend std::basic_ostream& operator<<(std::basic_ostream& os, + const dynamic_bitset& value) { + for(size_type i = value.size_; i > 0; --i) { + os << (value.test(i - 1) ? Char('1') : Char('0')); + } + return os; + } + +private: + static constexpr size_type bits_per_block = std::numeric_limits::digits; + + static size_type block_count(size_type size) { + return size == 0 ? 0 : (size + bits_per_block - 1) / bits_per_block; + } + + static constexpr block_type all_bits_set() { + return static_cast(~block_type(0)); + } + + static size_type block_index(size_type pos) { + return pos / bits_per_block; + } + + static size_type bit_offset(size_type pos) { + return pos % bits_per_block; + } + + void resize_to_match(const dynamic_bitset& other) { + assert(size_ == other.size_); + (void)other; + } + + void trim_unused_bits() { + if(size_ == 0 || blocks_.empty()) { + return; + } + const auto used_bits = bit_offset(size_); + if(used_bits != 0) { + blocks_.back() &= (block_type(1) << used_bits) - 1; + } + } + + size_type size_{0}; + std::vector blocks_; +}; + +} // namespace dyncompat + +#endif diff --git a/dyncompat/dyninst_thread_compat.hpp b/dyncompat/dyninst_thread_compat.hpp new file mode 100644 index 0000000000..200b74446d --- /dev/null +++ b/dyncompat/dyninst_thread_compat.hpp @@ -0,0 +1,115 @@ +#ifndef DYNINST_DYNCOMPAT_THREAD_COMPAT_HPP +#define DYNINST_DYNCOMPAT_THREAD_COMPAT_HPP + +#include +#include +#include +#include +#include +#include + +namespace dyncompat { + +using mutex = std::mutex; +using recursive_mutex = std::recursive_mutex; +using shared_mutex = std::shared_mutex; +using condition_variable = std::condition_variable_any; +using condition_variable_any = std::condition_variable_any; +using thread = std::thread; + +template +using unique_lock = std::unique_lock; + +template +using shared_lock = std::shared_lock; + +template +using lock_guard = std::lock_guard; + +template +lock_guard make_lock_guard(Mutex& mutex_ref) { + return lock_guard(mutex_ref); +} + +using std::lock; + +struct once_init_t {}; + +class once_flag { +public: + constexpr once_flag() noexcept = default; + constexpr once_flag(once_init_t) noexcept {} + + once_flag(const once_flag&) = delete; + once_flag& operator=(const once_flag&) = delete; + +private: + std::once_flag flag_; + + template + friend void call_once(once_flag&, Callable&&, Args&&...); +}; + +template +void call_once(once_flag& flag, Callable&& callable, Args&&... args) { + std::call_once(flag.flag_, std::forward(callable), std::forward(args)...); +} + +class barrier { +public: + explicit barrier(unsigned count) + : threshold_(count), count_(count), generation_(0) {} + + barrier(const barrier&) = delete; + barrier& operator=(const barrier&) = delete; + + bool wait() { + std::unique_lock lock(mutex_); + const auto generation = generation_; + + if(--count_ == 0) { + generation_++; + count_ = threshold_; + cv_.notify_all(); + return true; + } + + cv_.wait(lock, [&] { return generation != generation_; }); + return false; + } + +private: + std::mutex mutex_; + std::condition_variable cv_; + const unsigned threshold_; + unsigned count_; + unsigned generation_; +}; + +template +class basic_lockable_adapter { +public: + using mutex_type = Mutex; + + basic_lockable_adapter() = default; + basic_lockable_adapter(const basic_lockable_adapter&) = delete; + basic_lockable_adapter& operator=(const basic_lockable_adapter&) = delete; + + void lock() const { mutex_.lock(); } + void unlock() const { mutex_.unlock(); } + bool try_lock() const { return mutex_.try_lock(); } + + Mutex& lockable() const { return mutex_; } + +private: + mutable Mutex mutex_{}; +}; + +template +using lockable_adapter = basic_lockable_adapter; + +} // namespace dyncompat + +#define DYNCOMPAT_ONCE_INIT ::dyncompat::once_init_t{} + +#endif diff --git a/dyncompat/enable_shared_from_this.hpp b/dyncompat/enable_shared_from_this.hpp new file mode 100644 index 0000000000..a34e2ddee4 --- /dev/null +++ b/dyncompat/enable_shared_from_this.hpp @@ -0,0 +1,6 @@ +#ifndef DYNINST_DYNCOMPAT_ENABLE_SHARED_FROM_THIS_HPP +#define DYNINST_DYNCOMPAT_ENABLE_SHARED_FROM_THIS_HPP + +#include "shared_ptr.hpp" + +#endif diff --git a/dyncompat/filter_iterator.hpp b/dyncompat/filter_iterator.hpp new file mode 100644 index 0000000000..3ebc8f70a8 --- /dev/null +++ b/dyncompat/filter_iterator.hpp @@ -0,0 +1,6 @@ +#ifndef DYNINST_DYNCOMPAT_FILTER_ITERATOR_HPP +#define DYNINST_DYNCOMPAT_FILTER_ITERATOR_HPP + +#include "iterator/filter_iterator.hpp" + +#endif diff --git a/dyncompat/foreach.hpp b/dyncompat/foreach.hpp new file mode 100644 index 0000000000..49cd2968d9 --- /dev/null +++ b/dyncompat/foreach.hpp @@ -0,0 +1,6 @@ +#ifndef DYNINST_DYNCOMPAT_FOREACH_HPP +#define DYNINST_DYNCOMPAT_FOREACH_HPP + +#define DYN_FOREACH(VAR, COL) for (VAR : (COL)) + +#endif diff --git a/dyncompat/function.hpp b/dyncompat/function.hpp new file mode 100644 index 0000000000..55a93885cd --- /dev/null +++ b/dyncompat/function.hpp @@ -0,0 +1,15 @@ +#ifndef DYNINST_DYNCOMPAT_FUNCTION_HPP +#define DYNINST_DYNCOMPAT_FUNCTION_HPP + +#include + +namespace dyncompat { + +template +using function = std::function; + +using std::ref; + +} // namespace dyncompat + +#endif diff --git a/dyncompat/functional/hash.hpp b/dyncompat/functional/hash.hpp new file mode 100644 index 0000000000..cc6346aeac --- /dev/null +++ b/dyncompat/functional/hash.hpp @@ -0,0 +1,34 @@ +#ifndef DYNINST_DYNCOMPAT_FUNCTIONAL_HASH_HPP +#define DYNINST_DYNCOMPAT_FUNCTIONAL_HASH_HPP + +#include +#include +#include + +namespace dyncompat { + +template +struct hash { + std::size_t operator()(const T& value) const { + return std::hash{}(value); + } +}; + +template +inline void hash_combine(std::size_t& seed, const T& value) { + seed ^= std::hash{}(value) + 0x9e3779b9u + (seed << 6) + (seed >> 2); +} + +template +struct hash> { + std::size_t operator()(const std::pair& value) const { + std::size_t seed = 0; + hash_combine(seed, value.first); + hash_combine(seed, value.second); + return seed; + } +}; + +} // namespace dyncompat + +#endif diff --git a/dyncompat/integer_traits.hpp b/dyncompat/integer_traits.hpp new file mode 100644 index 0000000000..4209680681 --- /dev/null +++ b/dyncompat/integer_traits.hpp @@ -0,0 +1,16 @@ +#ifndef DYNINST_DYNCOMPAT_INTEGER_TRAITS_HPP +#define DYNINST_DYNCOMPAT_INTEGER_TRAITS_HPP + +#include + +namespace dyncompat { + +template +struct integer_traits { + static constexpr T const_min = std::numeric_limits::lowest(); + static constexpr T const_max = std::numeric_limits::max(); +}; + +} // namespace dyncompat + +#endif diff --git a/dyncompat/interprocess/sync/scoped_lock.hpp b/dyncompat/interprocess/sync/scoped_lock.hpp new file mode 100644 index 0000000000..c3a25a9483 --- /dev/null +++ b/dyncompat/interprocess/sync/scoped_lock.hpp @@ -0,0 +1,15 @@ +#ifndef DYNINST_DYNCOMPAT_INTERPROCESS_SYNC_SCOPED_LOCK_HPP +#define DYNINST_DYNCOMPAT_INTERPROCESS_SYNC_SCOPED_LOCK_HPP + +#include + +namespace dyncompat { +namespace interprocess { + +template +using scoped_lock = std::unique_lock; + +} // namespace interprocess +} // namespace dyncompat + +#endif diff --git a/dyncompat/iterator/filter_iterator.hpp b/dyncompat/iterator/filter_iterator.hpp new file mode 100644 index 0000000000..bb8ad6cfa5 --- /dev/null +++ b/dyncompat/iterator/filter_iterator.hpp @@ -0,0 +1,61 @@ +#ifndef DYNINST_DYNCOMPAT_ITERATOR_FILTER_ITERATOR_HPP +#define DYNINST_DYNCOMPAT_ITERATOR_FILTER_ITERATOR_HPP + +#include +#include + +namespace dyncompat { + +template +class filter_iterator { +public: + using iterator_category = std::forward_iterator_tag; + using value_type = typename std::iterator_traits::value_type; + using difference_type = typename std::iterator_traits::difference_type; + using pointer = typename std::iterator_traits::pointer; + using reference = typename std::iterator_traits::reference; + + filter_iterator() = default; + filter_iterator(Predicate predicate, Iterator current, Iterator end) + : predicate_(std::move(predicate)), current_(current), end_(end) { + satisfy(); + } + + reference operator*() const { return *current_; } + pointer operator->() const { return std::addressof(*current_); } + + filter_iterator& operator++() { + ++current_; + satisfy(); + return *this; + } + + filter_iterator operator++(int) { + filter_iterator tmp(*this); + ++(*this); + return tmp; + } + + bool operator==(const filter_iterator& other) const { return current_ == other.current_; } + bool operator!=(const filter_iterator& other) const { return !(*this == other); } + +private: + void satisfy() { + while(current_ != end_ && !predicate_(*current_)) { + ++current_; + } + } + + Predicate predicate_{}; + Iterator current_{}; + Iterator end_{}; +}; + +template +filter_iterator make_filter_iterator(Predicate predicate, Iterator current, Iterator end) { + return filter_iterator(std::move(predicate), current, end); +} + +} // namespace dyncompat + +#endif diff --git a/dyncompat/iterator/function_output_iterator.hpp b/dyncompat/iterator/function_output_iterator.hpp new file mode 100644 index 0000000000..e92a399f42 --- /dev/null +++ b/dyncompat/iterator/function_output_iterator.hpp @@ -0,0 +1,41 @@ +#ifndef DYNINST_DYNCOMPAT_ITERATOR_FUNCTION_OUTPUT_ITERATOR_HPP +#define DYNINST_DYNCOMPAT_ITERATOR_FUNCTION_OUTPUT_ITERATOR_HPP + +#include +#include + +namespace dyncompat { + +template +class function_output_iterator { +public: + using iterator_category = std::output_iterator_tag; + using difference_type = std::ptrdiff_t; + using value_type = void; + using pointer = void; + using reference = void; + + explicit function_output_iterator(Function function) : function_(std::move(function)) {} + + function_output_iterator& operator*() { return *this; } + function_output_iterator& operator++() { return *this; } + function_output_iterator operator++(int) { return *this; } + + template + function_output_iterator& operator=(T&& value) { + function_(std::forward(value)); + return *this; + } + +private: + Function function_; +}; + +template +function_output_iterator make_function_output_iterator(Function function) { + return function_output_iterator(std::move(function)); +} + +} // namespace dyncompat + +#endif diff --git a/dyncompat/iterator/iterator_facade.hpp b/dyncompat/iterator/iterator_facade.hpp new file mode 100644 index 0000000000..abf490e162 --- /dev/null +++ b/dyncompat/iterator/iterator_facade.hpp @@ -0,0 +1,96 @@ +#ifndef DYNINST_DYNCOMPAT_ITERATOR_ITERATOR_FACADE_HPP +#define DYNINST_DYNCOMPAT_ITERATOR_ITERATOR_FACADE_HPP + +#include +#include +#include +#include + +namespace dyncompat { + +using bidirectional_traversal_tag = std::bidirectional_iterator_tag; + +struct iterator_core_access { + template + static decltype(auto) dereference(const Derived& derived) { + return derived.dereference(); + } + + template + static bool equal(const Derived& lhs, const Derived& rhs) { + return lhs.equal(rhs); + } + + template + static void increment(Derived& derived) { + derived.increment(); + } + + template + static void decrement(Derived& derived) { + derived.decrement(); + } +}; + +template +class iterator_facade { +public: + using iterator_category = Category; + using value_type = Value; + using reference = Reference; + using difference_type = Difference; + using pointer = std::add_pointer_t; + + reference operator*() const { + return iterator_core_access::dereference(derived()); + } + + pointer operator->() const { + if constexpr (std::is_reference_v) { + return std::addressof(iterator_core_access::dereference(derived())); + } else { + cache_ = iterator_core_access::dereference(derived()); + return std::addressof(*cache_); + } + } + + Derived& operator++() { + iterator_core_access::increment(derived()); + return derived(); + } + + Derived operator++(int) { + Derived tmp = derived(); + ++(*this); + return tmp; + } + + Derived& operator--() { + iterator_core_access::decrement(derived()); + return derived(); + } + + Derived operator--(int) { + Derived tmp = derived(); + --(*this); + return tmp; + } + + friend bool operator==(const iterator_facade& lhs, const iterator_facade& rhs) { + return iterator_core_access::equal(lhs.derived(), rhs.derived()); + } + + friend bool operator!=(const iterator_facade& lhs, const iterator_facade& rhs) { + return !(lhs == rhs); + } + +private: + Derived& derived() { return static_cast(*this); } + const Derived& derived() const { return static_cast(*this); } + + mutable std::optional cache_{}; +}; + +} // namespace dyncompat + +#endif diff --git a/dyncompat/iterator/transform_iterator.hpp b/dyncompat/iterator/transform_iterator.hpp new file mode 100644 index 0000000000..0590c6f6ac --- /dev/null +++ b/dyncompat/iterator/transform_iterator.hpp @@ -0,0 +1,75 @@ +#ifndef DYNINST_DYNCOMPAT_ITERATOR_TRANSFORM_ITERATOR_HPP +#define DYNINST_DYNCOMPAT_ITERATOR_TRANSFORM_ITERATOR_HPP + +#include +#include +#include +#include +#include + +namespace dyncompat { + +template +class transform_iterator { +public: + using iterator_category = std::forward_iterator_tag; + using difference_type = typename std::iterator_traits::difference_type; + using value_type = std::decay_t()(*std::declval()))>; + using reference = decltype(std::declval()(*std::declval())); + using pointer = std::add_pointer_t; + + transform_iterator() = default; + explicit transform_iterator(Iterator iterator) : iterator_(iterator), function_() {} + transform_iterator(Iterator iterator, UnaryFunction function) + : iterator_(iterator), function_(std::move(function)) {} + + reference operator*() const { return function_(*iterator_); } + + pointer operator->() const { + if constexpr (std::is_reference_v) { + return std::addressof(function_(*iterator_)); + } else { + cache_ = function_(*iterator_); + return std::addressof(*cache_); + } + } + + transform_iterator& operator++() { + ++iterator_; + return *this; + } + + transform_iterator operator++(int) { + transform_iterator tmp(*this); + ++(*this); + return tmp; + } + + transform_iterator& operator--() { + --iterator_; + return *this; + } + + transform_iterator operator--(int) { + transform_iterator tmp(*this); + --(*this); + return tmp; + } + + bool operator==(const transform_iterator& other) const { return iterator_ == other.iterator_; } + bool operator!=(const transform_iterator& other) const { return !(*this == other); } + +private: + Iterator iterator_{}; + UnaryFunction function_{}; + mutable std::optional cache_{}; +}; + +template +transform_iterator make_transform_iterator(Iterator iterator, UnaryFunction function) { + return transform_iterator(iterator, std::move(function)); +} + +} // namespace dyncompat + +#endif diff --git a/dyncompat/lexical_cast.hpp b/dyncompat/lexical_cast.hpp new file mode 100644 index 0000000000..161abd6b1b --- /dev/null +++ b/dyncompat/lexical_cast.hpp @@ -0,0 +1,38 @@ +#ifndef DYNINST_DYNCOMPAT_LEXICAL_CAST_HPP +#define DYNINST_DYNCOMPAT_LEXICAL_CAST_HPP + +#include +#include +#include +#include + +namespace dyncompat { + +class bad_lexical_cast : public std::bad_cast { +public: + const char* what() const noexcept override { return "bad lexical cast"; } +}; + +template +Target lexical_cast(const Source& source) { + if constexpr(std::is_same_v) { + std::ostringstream os; + os << source; + if(!os) { + throw bad_lexical_cast(); + } + return os.str(); + } else { + std::istringstream is(lexical_cast(source)); + Target target{}; + is >> target; + if(!is || !is.eof()) { + throw bad_lexical_cast(); + } + return target; + } +} + +} // namespace dyncompat + +#endif diff --git a/dyncompat/logic/tribool.hpp b/dyncompat/logic/tribool.hpp new file mode 100644 index 0000000000..99cc91d8ed --- /dev/null +++ b/dyncompat/logic/tribool.hpp @@ -0,0 +1,47 @@ +#ifndef DYNINST_DYNCOMPAT_LOGIC_TRIBOOL_HPP +#define DYNINST_DYNCOMPAT_LOGIC_TRIBOOL_HPP + +namespace dyncompat { + +class tribool; + +struct indeterminate_keyword_t { + tribool operator()() const; + bool operator()(tribool value) const; +}; + +class tribool { +public: + enum class value_t { false_value, true_value, indeterminate_value }; + + tribool() : value_(value_t::false_value) {} + tribool(bool value) : value_(value ? value_t::true_value : value_t::false_value) {} + tribool(indeterminate_keyword_t) : value_(value_t::indeterminate_value) {} + + explicit operator bool() const { return value_ == value_t::true_value; } + + friend tribool operator!(tribool value) { + if(value.value_ == value_t::indeterminate_value) { + return tribool(indeterminate_keyword_t{}); + } + return tribool(value.value_ == value_t::false_value); + } + +private: + friend struct indeterminate_keyword_t; + value_t value_; +}; + +inline tribool indeterminate_keyword_t::operator()() const { + return tribool(*this); +} + +inline bool indeterminate_keyword_t::operator()(tribool value) const { + return value.value_ == tribool::value_t::indeterminate_value; +} + +inline constexpr indeterminate_keyword_t indeterminate{}; + +} // namespace dyncompat + +#endif diff --git a/dyncompat/make_shared.hpp b/dyncompat/make_shared.hpp new file mode 100644 index 0000000000..7e11a0f457 --- /dev/null +++ b/dyncompat/make_shared.hpp @@ -0,0 +1,17 @@ +#ifndef DYNINST_DYNCOMPAT_MAKE_SHARED_HPP +#define DYNINST_DYNCOMPAT_MAKE_SHARED_HPP + +#include "shared_ptr.hpp" +#include +#include + +namespace dyncompat { + +template +shared_ptr make_shared(Args&&... args) { + return shared_ptr(std::make_shared(std::forward(args)...)); +} + +} // namespace dyncompat + +#endif diff --git a/dyncompat/optional.hpp b/dyncompat/optional.hpp new file mode 100644 index 0000000000..be5de69831 --- /dev/null +++ b/dyncompat/optional.hpp @@ -0,0 +1,56 @@ +#ifndef DYNINST_DYNCOMPAT_OPTIONAL_HPP +#define DYNINST_DYNCOMPAT_OPTIONAL_HPP + +#include +#include +#include + +namespace dyncompat { + +template +class optional : public std::optional { + using base = std::optional; + +public: + using base::base; + using base::operator=; + + optional() = default; + optional(const optional&) = default; + optional(optional&&) = default; + optional(const base& other) : base(other) {} + optional(base&& other) : base(std::move(other)) {} + + optional& operator=(const optional&) = default; + optional& operator=(optional&&) = default; + + optional& operator=(const base& other) { + base::operator=(other); + return *this; + } + + optional& operator=(base&& other) { + base::operator=(std::move(other)); + return *this; + } + + T& get() { + return this->value(); + } + + const T& get() const { + return this->value(); + } +}; + +using std::nullopt; +using std::nullopt_t; + +template +optional> make_optional(T&& value) { + return optional>(std::forward(value)); +} + +} // namespace dyncompat + +#endif diff --git a/dyncompat/range/iterator_range.hpp b/dyncompat/range/iterator_range.hpp new file mode 100644 index 0000000000..aa336c8d2a --- /dev/null +++ b/dyncompat/range/iterator_range.hpp @@ -0,0 +1,31 @@ +#ifndef DYNINST_DYNCOMPAT_RANGE_ITERATOR_RANGE_HPP +#define DYNINST_DYNCOMPAT_RANGE_ITERATOR_RANGE_HPP + +namespace dyncompat { + +template +class iterator_range { +public: + using iterator = Iterator; + using const_iterator = Iterator; + + iterator_range() = default; + iterator_range(Iterator first, Iterator last) : first_(first), last_(last) {} + + Iterator begin() const { return first_; } + Iterator end() const { return last_; } + bool empty() const { return first_ == last_; } + +private: + Iterator first_{}; + Iterator last_{}; +}; + +template +iterator_range make_iterator_range(Iterator first, Iterator last) { + return iterator_range(first, last); +} + +} // namespace dyncompat + +#endif diff --git a/dyncompat/regex.h b/dyncompat/regex.h new file mode 100644 index 0000000000..ceb1c09da5 --- /dev/null +++ b/dyncompat/regex.h @@ -0,0 +1,18 @@ +#ifndef DYNINST_DYNCOMPAT_REGEX_H +#define DYNINST_DYNCOMPAT_REGEX_H + +#include + +namespace dyncompat { + +using regex = std::regex; +using smatch = std::smatch; +using cmatch = std::cmatch; +using std::regex_match; +using std::regex_search; + +namespace regex_constants = std::regex_constants; + +} // namespace dyncompat + +#endif diff --git a/dyncompat/shared_ptr.hpp b/dyncompat/shared_ptr.hpp new file mode 100644 index 0000000000..ae7fbcd00a --- /dev/null +++ b/dyncompat/shared_ptr.hpp @@ -0,0 +1,210 @@ +#ifndef DYNINST_DYNCOMPAT_SHARED_PTR_HPP +#define DYNINST_DYNCOMPAT_SHARED_PTR_HPP + +#include +#include +#include +#include + +#ifndef DYNCOMPAT_NOEXCEPT +#define DYNCOMPAT_NOEXCEPT noexcept +#endif + +namespace dyncompat { + +template +void checked_delete(T* ptr) DYNCOMPAT_NOEXCEPT; + +template +class shared_ptr : public std::shared_ptr { + using base = std::shared_ptr; + +public: + using element_type = typename base::element_type; + + shared_ptr() DYNCOMPAT_NOEXCEPT = default; + shared_ptr(std::nullptr_t) DYNCOMPAT_NOEXCEPT : base(nullptr) {} + shared_ptr(const shared_ptr&) DYNCOMPAT_NOEXCEPT = default; + shared_ptr(shared_ptr&&) DYNCOMPAT_NOEXCEPT = default; + + template >> + shared_ptr(Integer value) : base(nullptr) { + assert(value == 0); + (void)value; + } + + shared_ptr(const base& other) DYNCOMPAT_NOEXCEPT : base(other) {} + shared_ptr(base&& other) DYNCOMPAT_NOEXCEPT : base(std::move(other)) {} + + template + shared_ptr(const shared_ptr& other) DYNCOMPAT_NOEXCEPT : base(other) {} + + template + shared_ptr(shared_ptr&& other) DYNCOMPAT_NOEXCEPT : base(std::move(other)) {} + + explicit shared_ptr(T* ptr) : base(ptr, &dyncompat::checked_delete) {} + + template + explicit shared_ptr(U* ptr) : base(ptr, &dyncompat::checked_delete) {} + + template + shared_ptr(U* ptr, Deleter deleter) : base(ptr, deleter) {} + + template + shared_ptr(U* ptr, Deleter deleter, Allocator alloc) : base(ptr, deleter, alloc) {} + + template + explicit shared_ptr(const std::weak_ptr& other) : base(other) {} + + template + shared_ptr(const shared_ptr& other, T* ptr) DYNCOMPAT_NOEXCEPT : base(other, ptr) {} + + shared_ptr& operator=(const shared_ptr&) DYNCOMPAT_NOEXCEPT = default; + shared_ptr& operator=(shared_ptr&&) DYNCOMPAT_NOEXCEPT = default; + + template >> + shared_ptr& operator=(Integer value) { + assert(value == 0); + (void)value; + base::reset(); + return *this; + } + + shared_ptr& operator=(const base& other) DYNCOMPAT_NOEXCEPT { + base::operator=(other); + return *this; + } + + shared_ptr& operator=(base&& other) DYNCOMPAT_NOEXCEPT { + base::operator=(std::move(other)); + return *this; + } + + template + shared_ptr& operator=(const shared_ptr& other) DYNCOMPAT_NOEXCEPT { + base::operator=(other); + return *this; + } + + template + shared_ptr& operator=(shared_ptr&& other) DYNCOMPAT_NOEXCEPT { + base::operator=(std::move(other)); + return *this; + } + + void reset() DYNCOMPAT_NOEXCEPT { + base::reset(); + } + + template + void reset(U* ptr) { + base::reset(ptr, &dyncompat::checked_delete); + } + + template + void reset(U* ptr, Deleter deleter) { + base::reset(ptr, deleter); + } + + template + void reset(U* ptr, Deleter deleter, Allocator alloc) { + base::reset(ptr, deleter, alloc); + } +}; + +template +class weak_ptr : public std::weak_ptr { + using base = std::weak_ptr; + +public: + weak_ptr() DYNCOMPAT_NOEXCEPT = default; + weak_ptr(const weak_ptr&) DYNCOMPAT_NOEXCEPT = default; + weak_ptr(weak_ptr&&) DYNCOMPAT_NOEXCEPT = default; + + weak_ptr(const base& other) DYNCOMPAT_NOEXCEPT : base(other) {} + weak_ptr(base&& other) DYNCOMPAT_NOEXCEPT : base(std::move(other)) {} + + template + weak_ptr(const shared_ptr& other) DYNCOMPAT_NOEXCEPT : base(other) {} + + template + weak_ptr(const weak_ptr& other) DYNCOMPAT_NOEXCEPT : base(other) {} + + weak_ptr& operator=(const weak_ptr&) DYNCOMPAT_NOEXCEPT = default; + weak_ptr& operator=(weak_ptr&&) DYNCOMPAT_NOEXCEPT = default; + + weak_ptr& operator=(const base& other) DYNCOMPAT_NOEXCEPT { + base::operator=(other); + return *this; + } + + weak_ptr& operator=(base&& other) DYNCOMPAT_NOEXCEPT { + base::operator=(std::move(other)); + return *this; + } + + template + weak_ptr& operator=(const shared_ptr& other) DYNCOMPAT_NOEXCEPT { + base::operator=(other); + return *this; + } + + template + weak_ptr& operator=(const weak_ptr& other) DYNCOMPAT_NOEXCEPT { + base::operator=(other); + return *this; + } + + shared_ptr lock() const DYNCOMPAT_NOEXCEPT { + return shared_ptr(base::lock()); + } +}; + +template +class enable_shared_from_this : public std::enable_shared_from_this { +public: + shared_ptr shared_from_this() { + return shared_ptr(std::enable_shared_from_this::shared_from_this()); + } + + shared_ptr shared_from_this() const { + return shared_ptr(std::enable_shared_from_this::shared_from_this()); + } + + weak_ptr weak_from_this() DYNCOMPAT_NOEXCEPT { + return std::enable_shared_from_this::weak_from_this(); + } + + weak_ptr weak_from_this() const DYNCOMPAT_NOEXCEPT { + return std::enable_shared_from_this::weak_from_this(); + } +}; + +template +shared_ptr const_pointer_cast(const shared_ptr& ptr) DYNCOMPAT_NOEXCEPT { + return shared_ptr(std::const_pointer_cast(static_cast&>(ptr))); +} + +template +shared_ptr dynamic_pointer_cast(const shared_ptr& ptr) DYNCOMPAT_NOEXCEPT { + return shared_ptr(std::dynamic_pointer_cast(static_cast&>(ptr))); +} + +template +shared_ptr reinterpret_pointer_cast(const shared_ptr& ptr) DYNCOMPAT_NOEXCEPT { + return shared_ptr(std::reinterpret_pointer_cast(static_cast&>(ptr))); +} + +template +shared_ptr static_pointer_cast(const shared_ptr& ptr) DYNCOMPAT_NOEXCEPT { + return shared_ptr(std::static_pointer_cast(static_cast&>(ptr))); +} + +template +void checked_delete(T* ptr) DYNCOMPAT_NOEXCEPT { + delete ptr; +} + +} // namespace dyncompat + +#endif diff --git a/dyncompat/smart_ptr/make_shared.hpp b/dyncompat/smart_ptr/make_shared.hpp new file mode 100644 index 0000000000..5a6f7b3d53 --- /dev/null +++ b/dyncompat/smart_ptr/make_shared.hpp @@ -0,0 +1,6 @@ +#ifndef DYNINST_DYNCOMPAT_SMART_PTR_MAKE_SHARED_HPP +#define DYNINST_DYNCOMPAT_SMART_PTR_MAKE_SHARED_HPP + +#include "../make_shared.hpp" + +#endif diff --git a/dyncompat/static_assert.hpp b/dyncompat/static_assert.hpp new file mode 100644 index 0000000000..bb791859e8 --- /dev/null +++ b/dyncompat/static_assert.hpp @@ -0,0 +1,6 @@ +#ifndef DYNINST_DYNCOMPAT_STATIC_ASSERT_HPP +#define DYNINST_DYNCOMPAT_STATIC_ASSERT_HPP + +#define DYN_STATIC_ASSERT(...) static_assert((__VA_ARGS__), #__VA_ARGS__) + +#endif diff --git a/dyncompat/thread.hpp b/dyncompat/thread.hpp new file mode 100644 index 0000000000..55a2cce5c1 --- /dev/null +++ b/dyncompat/thread.hpp @@ -0,0 +1,6 @@ +#ifndef DYNINST_DYNCOMPAT_THREAD_HPP +#define DYNINST_DYNCOMPAT_THREAD_HPP + +#include "dyninst_thread_compat.hpp" + +#endif diff --git a/dyncompat/thread/barrier.hpp b/dyncompat/thread/barrier.hpp new file mode 100644 index 0000000000..cfa5dcaccf --- /dev/null +++ b/dyncompat/thread/barrier.hpp @@ -0,0 +1,6 @@ +#ifndef DYNINST_DYNCOMPAT_THREAD_BARRIER_HPP +#define DYNINST_DYNCOMPAT_THREAD_BARRIER_HPP + +#include "../dyninst_thread_compat.hpp" + +#endif diff --git a/dyncompat/thread/condition_variable.hpp b/dyncompat/thread/condition_variable.hpp new file mode 100644 index 0000000000..e7f5210c70 --- /dev/null +++ b/dyncompat/thread/condition_variable.hpp @@ -0,0 +1,6 @@ +#ifndef DYNINST_DYNCOMPAT_THREAD_CONDITION_VARIABLE_HPP +#define DYNINST_DYNCOMPAT_THREAD_CONDITION_VARIABLE_HPP + +#include "../dyninst_thread_compat.hpp" + +#endif diff --git a/dyncompat/thread/lock_guard.hpp b/dyncompat/thread/lock_guard.hpp new file mode 100644 index 0000000000..2d30abc010 --- /dev/null +++ b/dyncompat/thread/lock_guard.hpp @@ -0,0 +1,6 @@ +#ifndef DYNINST_DYNCOMPAT_THREAD_LOCK_GUARD_HPP +#define DYNINST_DYNCOMPAT_THREAD_LOCK_GUARD_HPP + +#include "../dyninst_thread_compat.hpp" + +#endif diff --git a/dyncompat/thread/lockable_adapter.hpp b/dyncompat/thread/lockable_adapter.hpp new file mode 100644 index 0000000000..5d7d198fbf --- /dev/null +++ b/dyncompat/thread/lockable_adapter.hpp @@ -0,0 +1,6 @@ +#ifndef DYNINST_DYNCOMPAT_THREAD_LOCKABLE_ADAPTER_HPP +#define DYNINST_DYNCOMPAT_THREAD_LOCKABLE_ADAPTER_HPP + +#include "../dyninst_thread_compat.hpp" + +#endif diff --git a/dyncompat/thread/locks.hpp b/dyncompat/thread/locks.hpp new file mode 100644 index 0000000000..d0396c6aab --- /dev/null +++ b/dyncompat/thread/locks.hpp @@ -0,0 +1,6 @@ +#ifndef DYNINST_DYNCOMPAT_THREAD_LOCKS_HPP +#define DYNINST_DYNCOMPAT_THREAD_LOCKS_HPP + +#include "../dyninst_thread_compat.hpp" + +#endif diff --git a/dyncompat/thread/mutex.hpp b/dyncompat/thread/mutex.hpp new file mode 100644 index 0000000000..5bc0df66ff --- /dev/null +++ b/dyncompat/thread/mutex.hpp @@ -0,0 +1,6 @@ +#ifndef DYNINST_DYNCOMPAT_THREAD_MUTEX_HPP +#define DYNINST_DYNCOMPAT_THREAD_MUTEX_HPP + +#include "../dyninst_thread_compat.hpp" + +#endif diff --git a/dyncompat/thread/once.hpp b/dyncompat/thread/once.hpp new file mode 100644 index 0000000000..100dde70f6 --- /dev/null +++ b/dyncompat/thread/once.hpp @@ -0,0 +1,6 @@ +#ifndef DYNINST_DYNCOMPAT_THREAD_ONCE_HPP +#define DYNINST_DYNCOMPAT_THREAD_ONCE_HPP + +#include "../dyninst_thread_compat.hpp" + +#endif diff --git a/dyncompat/thread/recursive_mutex.hpp b/dyncompat/thread/recursive_mutex.hpp new file mode 100644 index 0000000000..18d9861623 --- /dev/null +++ b/dyncompat/thread/recursive_mutex.hpp @@ -0,0 +1,6 @@ +#ifndef DYNINST_DYNCOMPAT_THREAD_RECURSIVE_MUTEX_HPP +#define DYNINST_DYNCOMPAT_THREAD_RECURSIVE_MUTEX_HPP + +#include "../dyninst_thread_compat.hpp" + +#endif diff --git a/dyncompat/thread/shared_mutex.hpp b/dyncompat/thread/shared_mutex.hpp new file mode 100644 index 0000000000..7f81515bbf --- /dev/null +++ b/dyncompat/thread/shared_mutex.hpp @@ -0,0 +1,6 @@ +#ifndef DYNINST_DYNCOMPAT_THREAD_SHARED_MUTEX_HPP +#define DYNINST_DYNCOMPAT_THREAD_SHARED_MUTEX_HPP + +#include "../dyninst_thread_compat.hpp" + +#endif diff --git a/dyncompat/thread/synchronized_value.hpp b/dyncompat/thread/synchronized_value.hpp new file mode 100644 index 0000000000..06c9502f82 --- /dev/null +++ b/dyncompat/thread/synchronized_value.hpp @@ -0,0 +1,20 @@ +#ifndef DYNINST_DYNCOMPAT_THREAD_SYNCHRONIZED_VALUE_HPP +#define DYNINST_DYNCOMPAT_THREAD_SYNCHRONIZED_VALUE_HPP + +#include "../dyninst_thread_compat.hpp" + +namespace dyncompat { + +template +class synchronized_value { +public: + synchronized_value() = default; + explicit synchronized_value(const T& value) : value_(value) {} + +private: + T value_{}; +}; + +} // namespace dyncompat + +#endif diff --git a/dyncompat/tuple/tuple.hpp b/dyncompat/tuple/tuple.hpp new file mode 100644 index 0000000000..0a00c99587 --- /dev/null +++ b/dyncompat/tuple/tuple.hpp @@ -0,0 +1,22 @@ +#ifndef DYNINST_DYNCOMPAT_TUPLE_TUPLE_HPP +#define DYNINST_DYNCOMPAT_TUPLE_TUPLE_HPP + +#include + +namespace dyncompat { + +template +using tuple = std::tuple; + +using std::get; +using std::make_tuple; +using std::tie; + +namespace tuples { +using std::ignore; +using std::tie; +} // namespace tuples + +} // namespace dyncompat + +#endif diff --git a/dyncompat/type_traits.hpp b/dyncompat/type_traits.hpp new file mode 100644 index 0000000000..ee023f3e80 --- /dev/null +++ b/dyncompat/type_traits.hpp @@ -0,0 +1,13 @@ +#ifndef DYNINST_DYNCOMPAT_TYPE_TRAITS_HPP +#define DYNINST_DYNCOMPAT_TYPE_TRAITS_HPP + +#include + +namespace dyncompat { + +using std::integral_constant; +using std::is_same; + +} // namespace dyncompat + +#endif diff --git a/dyncompat/type_traits/is_same.hpp b/dyncompat/type_traits/is_same.hpp new file mode 100644 index 0000000000..0f4edb5458 --- /dev/null +++ b/dyncompat/type_traits/is_same.hpp @@ -0,0 +1,6 @@ +#ifndef DYNINST_DYNCOMPAT_TYPE_TRAITS_IS_SAME_HPP +#define DYNINST_DYNCOMPAT_TYPE_TRAITS_IS_SAME_HPP + +#include "../type_traits.hpp" + +#endif diff --git a/dyncompat/variant2/variant.hpp b/dyncompat/variant2/variant.hpp new file mode 100644 index 0000000000..ac4801366c --- /dev/null +++ b/dyncompat/variant2/variant.hpp @@ -0,0 +1,19 @@ +#ifndef DYNINST_DYNCOMPAT_VARIANT2_VARIANT_HPP +#define DYNINST_DYNCOMPAT_VARIANT2_VARIANT_HPP + +#include + +namespace dyncompat { +namespace variant2 { + +template +using variant = std::variant; + +using std::get; +using std::get_if; +using std::holds_alternative; + +} // namespace variant2 +} // namespace dyncompat + +#endif diff --git a/dyncompat/version.hpp b/dyncompat/version.hpp new file mode 100644 index 0000000000..b29acf8e33 --- /dev/null +++ b/dyncompat/version.hpp @@ -0,0 +1,7 @@ +#ifndef DYNINST_DYNCOMPAT_VERSION_HPP +#define DYNINST_DYNCOMPAT_VERSION_HPP + +#define DYNCOMPAT_VERSION 108700 +#define DYNCOMPAT_LIB_VERSION "1_87" + +#endif diff --git a/dyncompat/weak_ptr.hpp b/dyncompat/weak_ptr.hpp new file mode 100644 index 0000000000..c3f72faff2 --- /dev/null +++ b/dyncompat/weak_ptr.hpp @@ -0,0 +1,6 @@ +#ifndef DYNINST_DYNCOMPAT_WEAK_PTR_HPP +#define DYNINST_DYNCOMPAT_WEAK_PTR_HPP + +#include "shared_ptr.hpp" + +#endif diff --git a/dyninstAPI/CMakeLists.txt b/dyninstAPI/CMakeLists.txt index 1b89f71d8b..157176c952 100644 --- a/dyninstAPI/CMakeLists.txt +++ b/dyninstAPI/CMakeLists.txt @@ -1,222 +1,328 @@ -# CMake configuration for dyninstAPI directory +include_guard(GLOBAL) -include_directories ( - src - h - ${PROJECT_SOURCE_DIR}/proccontrol/h - ) +# dyninstAPI doesn't work with symlite +if(LIGHTWEIGHT_SYMTAB) + message(STATUS "LIGHTWEIGHT_SYMTAB enabled; dyninstAPI not built.") + return() +endif() -set (SRC_LIST - src/BPatch.C - src/BPatch_image.C - src/BPatch_function.C - src/BPatch_snippet.C - src/BPatch_thread.C - src/BPatch_process.C - src/BPatch_type.C - src/BPatch_module.C - src/BPatch_object.C - src/BPatch_point.C - src/BPatch_collections.C - src/BPatch_sourceBlock.C - src/BPatch_basicBlock.C - src/BPatch_basicBlockLoop.C - src/BPatch_edge.C - src/BPatch_loopTreeNode.C - src/BPatch_flowGraph.C - src/BPatch_frame.C - src/BPatch_parRegion.C - src/BPatch_statement.C - src/BPatch_addressSpace.C - src/BPatch_binaryEdit.C - src/BPatch_memoryAccess.C - src/debug.C - src/ast.C - src/registerSpace.C - src/codegen.C - src/inst.C - src/instPoint.C - src/baseTramp.C - src/addressSpace.C - src/binaryEdit.C - src/infHeap.C - src/frame.C - src/codeRange.C - src/image.C - src/parse-cfg.C - src/mapped_object.C - src/mapped_module.C - src/function.C - src/block.C - src/edge.C - src/variable.C - src/util.C - src/BPatch_instruction.C - src/parRegion.C - src/Parsing.C - src/Parsing-arch.C - src/hybridInstrumentation.C - src/hybridOverwrites.C - src/hybridCallbacks.C - src/dynProcess.C - src/dynThread.C - src/pcEventHandler.C - src/pcEventMuxer.C - src/Relocation/CodeMover.C - src/Relocation/CFG/RelocGraph.C - src/Relocation/CFG/RelocBlock.C - src/Relocation/CFG/RelocEdge.C - src/Relocation/CFG/RelocTarget.C - src/Relocation/Springboard.C - src/Relocation/Widgets/ASTWidget.C - src/Relocation/Widgets/CFWidget.C - src/Relocation/Widgets/CallbackWidget.C - src/Relocation/Widgets/InsnWidget.C - src/Relocation/Widgets/InstWidget.C - src/Relocation/Widgets/PCWidget.C - src/Relocation/Widgets/RelDataWidget.C - src/Relocation/Widgets/StackModWidget.C - src/Relocation/Transformers/Transformer.C - src/Relocation/Transformers/Instrumenter.C - src/Relocation/Transformers/Modification.C - src/Relocation/Transformers/Movement-adhoc.C - src/Relocation/Transformers/Movement-analysis.C - src/Relocation/CodeTracker.C - src/Relocation/CodeBuffer.C - src/Relocation/patchapi_debug.C - src/Relocation/DynObject.C - src/Relocation/DynAddrSpace.C - src/Relocation/DynPointMaker.C - src/Relocation/DynCFGMaker.C - src/Relocation/DynInstrumenter.C - src/Patching.C - src/frameChecker.C - src/BPatch_memoryAccessAdapter.C -) +include(DyninstLibrary) -# This is just .. messy. Sorry. +set(_public_headers + h/BPatch_addressSpace.h + h/BPatch_basicBlock.h + h/BPatch_basicBlockLoop.h + h/BPatch_binaryEdit.h + h/BPatch_callbacks.h + h/BPatch_dll.h + h/BPatch_edge.h + h/BPatch_enums.h + h/BPatch_flowGraph.h + h/BPatch_frame.h + h/BPatch_function.h + h/BPatch.h + h/BPatch_image.h + h/BPatch_instruction.h + h/BPatch_loopTreeNode.h + h/BPatch_memoryAccess_NP.h + h/BPatch_module.h + h/BPatch_object.h + h/BPatch_parRegion.h + h/BPatch_point.h + h/BPatch_process.h + h/BPatch_Set.h + h/BPatch_snippet.h + h/BPatch_sourceBlock.h + h/BPatch_sourceObj.h + h/BPatch_statement.h + h/BPatch_thread.h + h/BPatch_type.h + h/BPatch_Vector.h + h/StackMod.h) -get_directory_property(local_comp_defs COMPILE_DEFINITIONS) -list (FIND local_comp_defs cap_stack_mods cap_stack_mods_found) -if (cap_stack_mods_found GREATER -1) -set (SRC_LIST ${SRC_LIST} - src/StackMod/OffsetVector.C - src/StackMod/StackAccess.C - src/StackMod/StackLocation.C - src/StackMod/StackMod.C - src/StackMod/StackModExpr.C - src/StackMod/StackModChecker.C - src/StackMod/TMap.C -) -endif () +set(_private_headers + src/addressSpace.h + src/arch-forward-decl.h + src/ast.h + src/baseTramp.h + src/binaryEdit.h + src/block.h + src/BPatch_collections.h + src/BPatch_libInfo.h + src/BPatch_memoryAccessAdapter.h + src/BPatch_private.h + src/codegen-aarch64.h + src/codegen.h + src/codegen-power.h + src/codegen-x86.h + src/codeRange.h + src/debug.h + src/dynProcess.h + src/dynThread.h + src/ELF_Section.h + src/emit-aarch64.h + src/emit-power.h + src/emitter.h + src/emit-x86.h + src/frameChecker.h + src/frame.h + src/freebsd.h + src/freebsd-x86.h + src/function.h + src/hybridAnalysis.h + src/IAPI_to_AST.h + src/image.h + src/infHeap.h + src/inst-aarch64.h + src/inst.h + src/instP.h + src/instPoint.h + src/inst-power.h + src/inst-x86.h + src/legacy-instruction.h + src/LinearVariable.h + src/linux-aarch64.h + src/linux.h + src/linux-power.h + src/linux-x86.h + src/mapped_module.h + src/mapped_object.h + src/nt_signal_emul.h + src/opcode.h + src/os.h + src/parRegion.h + src/parse-cfg.h + src/Parsing.h + src/patch.h + src/Patching.h + src/pcEventHandler.h + src/pcEventMuxer.h + src/pcrel.h + src/pdwinnt.h + src/RegisterConversion.h + src/registerSpace.h + src/syscallNotification.h + src/syscalltrap.h + src/trapMappings.h + src/unix.h + src/util.h) -if (PLATFORM MATCHES i386 OR PLATFORM MATCHES amd64 OR PLATFORM MATCHES x86_64) -set (SRC_LIST ${SRC_LIST} - src/RegisterConversion-x86.C - src/Relocation/Widgets/CFWidget-x86.C - src/Relocation/Widgets/PCWidget-x86.C - src/inst-x86.C - src/emit-x86.C - src/codegen-x86.C - src/stackwalk-x86.C - src/dynProcess-x86.C - src/parse-x86.C - src/IAPI_to_AST.C -) -elseif (PLATFORM MATCHES ppc) -set (SRC_LIST ${SRC_LIST} - src/inst-power.C - src/codegen-power.C - src/parse-power.C - src/RegisterConversion-ppc.C - src/stackwalk-ppc.C - src/Relocation/Widgets/CFWidget-ppc.C - src/Relocation/Widgets/PCWidget-ppc.C -) -elseif (PLATFORM MATCHES aarch64) -set (SRC_LIST ${SRC_LIST} - src/inst-aarch64.C - src/emit-aarch64.C - src/codegen-aarch64.C - src/parse-aarch64.C - src/RegisterConversion-aarch64.C - src/stackwalk-aarch64.C - src/Relocation/Widgets/CFWidget-aarch64.C - src/Relocation/Widgets/PCWidget-aarch64.C -) -endif () +set(_sources + src/addressSpace.C + src/ast.C + src/baseTramp.C + src/binaryEdit.C + src/block.C + src/codeRange.C + src/codegen.C + src/debug.C + src/dynProcess.C + src/dynThread.C + src/edge.C + src/frame.C + src/frameChecker.C + src/function.C + src/hybridCallbacks.C + src/hybridInstrumentation.C + src/hybridOverwrites.C + src/image.C + src/infHeap.C + src/inst.C + src/instPoint.C + src/mapped_module.C + src/mapped_object.C + src/parRegion.C + src/parse-cfg.C + src/pcEventHandler.C + src/pcEventMuxer.C + src/registerSpace.C + src/util.C + src/variable.C + src/BPatch.C + src/BPatch_addressSpace.C + src/BPatch_basicBlock.C + src/BPatch_basicBlockLoop.C + src/BPatch_binaryEdit.C + src/BPatch_collections.C + src/BPatch_edge.C + src/BPatch_flowGraph.C + src/BPatch_frame.C + src/BPatch_function.C + src/BPatch_image.C + src/BPatch_instruction.C + src/BPatch_loopTreeNode.C + src/BPatch_memoryAccess.C + src/BPatch_memoryAccessAdapter.C + src/BPatch_module.C + src/BPatch_object.C + src/BPatch_parRegion.C + src/BPatch_point.C + src/BPatch_process.C + src/BPatch_snippet.C + src/BPatch_sourceBlock.C + src/BPatch_statement.C + src/BPatch_thread.C + src/BPatch_type.C + src/Parsing-arch.C + src/Parsing.C + src/Patching.C + src/Relocation/CFG/RelocBlock.C + src/Relocation/CFG/RelocEdge.C + src/Relocation/CFG/RelocGraph.C + src/Relocation/CFG/RelocTarget.C + src/Relocation/CodeBuffer.C + src/Relocation/CodeMover.C + src/Relocation/CodeTracker.C + src/Relocation/DynAddrSpace.C + src/Relocation/DynCFGMaker.C + src/Relocation/DynInstrumenter.C + src/Relocation/DynObject.C + src/Relocation/DynPointMaker.C + src/Relocation/Springboard.C + src/Relocation/Transformers/Instrumenter.C + src/Relocation/Transformers/Modification.C + src/Relocation/Transformers/Movement-adhoc.C + src/Relocation/Transformers/Movement-analysis.C + src/Relocation/Transformers/Transformer.C + src/Relocation/Widgets/ASTWidget.C + src/Relocation/Widgets/CFWidget.C + src/Relocation/Widgets/CallbackWidget.C + src/Relocation/Widgets/InsnWidget.C + src/Relocation/Widgets/InstWidget.C + src/Relocation/Widgets/PCWidget.C + src/Relocation/Widgets/RelDataWidget.C + src/Relocation/Widgets/StackModWidget.C + src/Relocation/patchapi_debug.C) -if (PLATFORM MATCHES freebsd) -set (SRC_LIST ${SRC_LIST} - src/freebsd.C - src/unix.C - src/freebsd-x86.C - src/syscallNotification.C - src/syscall-freebsd.C -) -elseif (PLATFORM MATCHES linux) -set (SRC_LIST ${SRC_LIST} - src/linux.C - src/inst-linux.C - src/unix.C - src/syscallNotification.C - src/syscall-linux.C -) - if (PLATFORM MATCHES i386 OR PLATFORM MATCHES x86_64) - set (SRC_LIST ${SRC_LIST} src/linux-x86.C) - elseif (PLATFORM MATCHES ppc) - set (SRC_LIST ${SRC_LIST} src/linux-power.C) - elseif (PLATFORM MATCHES aarch64) - set (SRC_LIST ${SRC_LIST} src/linux-aarch64.C) - endif() -elseif(PLATFORM MATCHES windows OR PLATFORM MATCHES nt) - set (SRC_LIST ${SRC_LIST} - src/hybridCallbacks.C - src/hybridInstrumentation.C - src/hybridOverwrites.C - src/inst-winnt.C - src/pdwinnt.C - src/syscall-nt.C - src/MemoryEmulator/memEmulator.C - src/MemoryEmulator/memEmulatorTransformer.C - src/MemoryEmulator/memEmulatorWidget.C - src/Relocation/DynAddrSpace.C - src/Relocation/DynCFGMaker.C - src/Relocation/DynInstrumenter.C - src/Relocation/DynObject.C - src/Relocation/DynPointMaker.C - ) +list(FIND DYNINST_PLATFORM_CAPABILITIES "-Dcap_stack_mods" cap_stack_mods_found) +if(cap_stack_mods_found GREATER -1) + list( + APPEND + _sources + src/StackMod/OffsetVector.C + src/StackMod/StackAccess.C + src/StackMod/StackLocation.C + src/StackMod/StackMod.C + src/StackMod/StackModExpr.C + src/StackMod/StackModChecker.C + src/StackMod/TMap.C) endif() -set_source_files_properties(${SRC_LIST} PROPERTIES LANGUAGE CXX) -add_definitions(-DBPATCH_DLL_BUILD) -if (PLATFORM MATCHES i386 AND UNIX) -set (SRC_LIST ${SRC_LIST} src/cpuid-x86.S) -set_source_files_properties(src/cpuid-x86.S PROPERTIES LANGUAGE C) -endif () +if(DYNINST_ARCH_i386 OR DYNINST_ARCH_x86_64) + list( + APPEND + _sources + src/RegisterConversion-x86.C + src/Relocation/Widgets/CFWidget-x86.C + src/Relocation/Widgets/PCWidget-x86.C + src/inst-x86.C + src/emit-x86.C + src/codegen-x86.C + src/stackwalk-x86.C + src/dynProcess-x86.C + src/parse-x86.C + src/IAPI_to_AST.C) +elseif(DYNINST_ARCH_ppc64le) + list( + APPEND + _sources + src/inst-power.C + src/codegen-power.C + src/parse-power.C + src/RegisterConversion-ppc.C + src/stackwalk-ppc.C + src/Relocation/Widgets/CFWidget-ppc.C + src/Relocation/Widgets/PCWidget-ppc.C) +elseif(DYNINST_ARCH_aarch64) + list( + APPEND + _sources + src/inst-aarch64.C + src/emit-aarch64.C + src/codegen-aarch64.C + src/parse-aarch64.C + src/RegisterConversion-aarch64.C + src/stackwalk-aarch64.C + src/Relocation/Widgets/CFWidget-aarch64.C + src/Relocation/Widgets/PCWidget-aarch64.C) +endif() -dyninst_library(dyninstAPI common instructionAPI stackwalk pcontrol patchAPI parseAPI symtabAPI) +if(DYNINST_OS_FreeBSD) + list( + APPEND + _sources + src/freebsd.C + src/unix.C + src/freebsd-x86.C + src/syscallNotification.C + src/syscall-freebsd.C) +elseif(DYNINST_OS_Linux) + list( + APPEND + _sources + src/linux.C + src/inst-linux.C + src/unix.C + src/syscallNotification.C + src/syscall-linux.C) + if(DYNINST_ARCH_i386 OR DYNINST_ARCH_x86_64) + list(APPEND _sources src/linux-x86.C) + elseif(DYNINST_ARCH_ppc64le) + list(APPEND _sources src/linux-power.C) + elseif(DYNINST_ARCH_aarch64) + list(APPEND _sources src/linux-aarch64.C) + endif() +elseif(DYNINST_OS_Windows) + list( + APPEND + _sources + src/hybridCallbacks.C + src/hybridInstrumentation.C + src/hybridOverwrites.C + src/inst-winnt.C + src/pdwinnt.C + src/syscall-nt.C + src/Relocation/DynAddrSpace.C + src/Relocation/DynCFGMaker.C + src/Relocation/DynInstrumenter.C + src/Relocation/DynObject.C + src/Relocation/DynPointMaker.C) +endif() -target_link_private_libraries(dyninstAPI ${Boost_LIBRARIES} ${TBB_LIBRARIES}) -if (UNIX) - # Boost auto-links on Windows; don't double-link - target_link_private_libraries (dyninstAPI pthread) -else() - target_link_private_libraries(dyninstAPI dbghelp WS2_32 imagehlp) +if(DYNINST_ARCH_i386 AND DYNINST_OS_UNIX) + list(APPEND _sources src/cpuid-x86.S) + set_source_files_properties(src/cpuid-x86.S PROPERTIES LANGUAGE C) endif() -if(UNIX) - # gcc/clang search directories - if(CMAKE_CXX_COMPILER_ID STREQUAL "GNU" OR CMAKE_CXX_COMPILER_ID STREQUAL "Clang") - execute_process( - COMMAND ${CMAKE_CXX_COMPILER} -print-search-dirs - OUTPUT_VARIABLE SEARCH_DIRS - ) - if(SEARCH_DIRS MATCHES "libraries:[ ]?[=]?(.+)\n") - set(DYNINST_COMPILER_SEARCH_DIRS ${CMAKE_MATCH_1}) - endif() - endif() - target_compile_definitions(dyninstAPI PRIVATE DYNINST_COMPILER_SEARCH_DIRS=${DYNINST_COMPILER_SEARCH_DIRS}) +# cmake-format: off +dyninst_library( + dyninstAPI + PUBLIC_HEADER_FILES ${_public_headers} + SOURCE_FILES ${_sources} + DEFINES BPATCH_DLL_BUILD + DYNINST_DEPS common instructionAPI stackwalk pcontrol patchAPI parseAPI symtabAPI + PUBLIC_DEPS + PRIVATE_DEPS Dyninst::ElfUtils Threads::Threads +) +# cmake-format: on + +# gcc/clang search directories +if(CMAKE_CXX_COMPILER_ID MATCHES "GNU|Clang") + execute_process(COMMAND ${CMAKE_CXX_COMPILER} -print-search-dirs + OUTPUT_VARIABLE SEARCH_DIRS) + if(SEARCH_DIRS MATCHES "libraries:[ ]?[=]?(.+)\n") + set(DYNINST_COMPILER_SEARCH_DIRS ${CMAKE_MATCH_1}) + endif() endif() -install(SCRIPT "${RT_BINARY_DIR}/cmake_install.cmake") +foreach(t ${dyninstAPI_TARGETS}) + if(DYNINST_OS_Windows) + target_link_libraries(${t} PRIVATE dbghelp WS2_32 imagehlp) + endif() + + if(DYNINST_OS_UNIX) + target_link_libraries(${t} PRIVATE pthread) + target_compile_definitions( + ${t} PRIVATE "DYNINST_COMPILER_SEARCH_DIRS=${DYNINST_COMPILER_SEARCH_DIRS}") + endif() +endforeach() diff --git a/dyninstAPI/doc/dyninstAPI.docx b/dyninstAPI/doc/dyninstAPI.docx index 22a814df8f..9bcb68efbd 100644 Binary files a/dyninstAPI/doc/dyninstAPI.docx and b/dyninstAPI/doc/dyninstAPI.docx differ diff --git a/dyninstAPI/doc/dyninstAPI.pdf b/dyninstAPI/doc/dyninstAPI.pdf index ae58a18a8d..1c11b14656 100644 Binary files a/dyninstAPI/doc/dyninstAPI.pdf and b/dyninstAPI/doc/dyninstAPI.pdf differ diff --git a/dyninstAPI/h/BPatch.h b/dyninstAPI/h/BPatch.h index afceef77fd..ab3628fee5 100644 --- a/dyninstAPI/h/BPatch.h +++ b/dyninstAPI/h/BPatch.h @@ -41,8 +41,10 @@ #include "BPatch_enums.h" #include "BPatch_callbacks.h" #include - +#include +#include "dyntypes.h" #include "dyninstversion.h" +#include "compiler_diagnostics.h" class BPatch_typeCollection; class BPatch_libInfo; @@ -73,10 +75,6 @@ class func_instance; #define DYNINST_MINOR DYNINST_MINOR_VERSION #define DYNINST_SUBMINOR DYNINST_PATCH_VERSION -#ifdef _MSC_VER -#pragma warning(push) -#pragma warning(disable:4251) -#endif // BPatch_stats is a collection of instrumentation statistics. // Introduced to export this information to paradyn, which @@ -482,7 +480,8 @@ class BPATCH_DLL_EXPORT BPatch { // Turn on/off line info truncating - void truncateLineInfoFilenames(bool x); + DYNINST_DEPRECATED("Does nothing") + void truncateLineInfoFilenames(bool); // BPatch::setTrampRecursive: // Turn on/off recursive trampolines @@ -679,9 +678,5 @@ class BPATCH_DLL_EXPORT BPatch { void addNonReturningFunc(std::string name); }; -#ifdef _MSC_VER -#pragma warning(pop) -#endif - #endif /* _BPatch_h_ */ diff --git a/dyninstAPI/h/BPatch_Set.h b/dyninstAPI/h/BPatch_Set.h index 8b36f68207..ae0ed2e198 100644 --- a/dyninstAPI/h/BPatch_Set.h +++ b/dyninstAPI/h/BPatch_Set.h @@ -31,10 +31,6 @@ #ifndef _BPatch_Set_h_ #define _BPatch_Set_h_ -#if defined(external_templates) -#pragma interface -#endif - /*******************************************************/ /* header files */ /*******************************************************/ diff --git a/dyninstAPI/h/BPatch_Vector.h b/dyninstAPI/h/BPatch_Vector.h index 8b314a02ae..b245aed077 100644 --- a/dyninstAPI/h/BPatch_Vector.h +++ b/dyninstAPI/h/BPatch_Vector.h @@ -31,6 +31,7 @@ #ifndef _BPatch_Vector_h_ #define _BPatch_Vector_h_ +#include #include template > diff --git a/dyninstAPI/h/BPatch_addressSpace.h b/dyninstAPI/h/BPatch_addressSpace.h index c9734180ab..2b43901a50 100644 --- a/dyninstAPI/h/BPatch_addressSpace.h +++ b/dyninstAPI/h/BPatch_addressSpace.h @@ -31,18 +31,21 @@ #ifndef _BPatch_addressSpace_h_ #define _BPatch_addressSpace_h_ -#include "boost/shared_ptr.hpp" +#include "dyncompat/shared_ptr.hpp" #include "BPatch_dll.h" #include "BPatch_Vector.h" #include "BPatch_enums.h" #include "BPatch_instruction.h" // for register type #include "BPatch_callbacks.h" - +#include "dyntypes.h" +#include +#include #include - +#include #include #include -#include +#include +#include "dyntypes.h" // PatchAPI stuffs //#include "Command.h" @@ -56,9 +59,9 @@ namespace Dyninst { class Instance; class PatchFunction; class Point; - typedef boost::shared_ptr PatchMgrPtr; - typedef boost::shared_ptr DynAddrSpacePtr; - typedef boost::shared_ptr InstancePtr; + typedef dyncompat::shared_ptr PatchMgrPtr; + typedef dyncompat::shared_ptr DynAddrSpacePtr; + typedef dyncompat::shared_ptr InstancePtr; BPATCH_DLL_EXPORT PatchMgrPtr convert(const BPatch_addressSpace *); } namespace SymtabAPI { diff --git a/dyninstAPI/h/BPatch_basicBlock.h b/dyninstAPI/h/BPatch_basicBlock.h index 37547d40c4..7394a7c010 100644 --- a/dyninstAPI/h/BPatch_basicBlock.h +++ b/dyninstAPI/h/BPatch_basicBlock.h @@ -31,6 +31,10 @@ #ifndef _BPatch_basicBlock_h_ #define _BPatch_basicBlock_h_ +#include +#include +#include +#include #include "BPatch_dll.h" #include "BPatch_Vector.h" #include "BPatch_Set.h" @@ -38,6 +42,7 @@ #include "BPatch_instruction.h" #include "Instruction.h" #include "BPatch_enums.h" +#include "dyntypes.h" //#include "BPatch_edge.h" class image; @@ -89,8 +94,10 @@ struct comparison { */ class BPatch_flowGraph; -struct BPATCH_DLL_EXPORT insnPredicate : public std::unary_function +struct BPATCH_DLL_EXPORT insnPredicate { + using result_type = bool; + using argument_type = Dyninst::InstructionAPI::Instruction; virtual result_type operator()(argument_type arg) = 0; virtual ~insnPredicate() {} diff --git a/dyninstAPI/h/BPatch_basicBlockLoop.h b/dyninstAPI/h/BPatch_basicBlockLoop.h index 76c3cb9746..a009c27b92 100644 --- a/dyninstAPI/h/BPatch_basicBlockLoop.h +++ b/dyninstAPI/h/BPatch_basicBlockLoop.h @@ -33,6 +33,8 @@ #include #include +#include +#include #include "Annotatable.h" #include "BPatch_dll.h" #include "BPatch_Vector.h" diff --git a/dyninstAPI/h/BPatch_binaryEdit.h b/dyninstAPI/h/BPatch_binaryEdit.h index 05e19a8ee5..16d99ac982 100644 --- a/dyninstAPI/h/BPatch_binaryEdit.h +++ b/dyninstAPI/h/BPatch_binaryEdit.h @@ -41,6 +41,8 @@ #include "BPatch_callbacks.h" #include +#include +#include #include #include diff --git a/dyninstAPI/h/BPatch_callbacks.h b/dyninstAPI/h/BPatch_callbacks.h index 8f74daa864..16bb5c20d3 100644 --- a/dyninstAPI/h/BPatch_callbacks.h +++ b/dyninstAPI/h/BPatch_callbacks.h @@ -31,7 +31,10 @@ #ifndef _BPATCH_ERROR_H_ #define _BPATCH_ERROR_H_ +#include #include "BPatch_Vector.h" +#include "dyntypes.h" + class BPatch_process; class BPatch_thread; class BPatch_module; diff --git a/dyninstAPI/h/BPatch_dll.h b/dyninstAPI/h/BPatch_dll.h index 1621c7d7ff..0c350567d0 100644 --- a/dyninstAPI/h/BPatch_dll.h +++ b/dyninstAPI/h/BPatch_dll.h @@ -28,10 +28,6 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ -#if defined(_MSC_VER) -#pragma warning(disable:4251) -#endif - #ifndef _BPatch_dll_h_ #define _BPatch_dll_h_ @@ -44,14 +40,6 @@ #define BPATCH_DLL_EXPORT #else #if defined(_MSC_VER) -// we get numerous spurious warnings about having some template classes -// needing to have a dll-interface if instances of these classes are -// to be used by classes whose public interfaces are exported from a DLL. -// Specifing the template classes with a DLL export interface doesn't -// satisfy the compiler. Until the compiler handles instantiated -// templates exported from DLLs better, we disable the warning when building -// or using the dyninstAPI DLL. -#pragma warning(disable:4251) #ifdef BPATCH_DLL_BUILD // we are building the dyninstAPI DLL diff --git a/dyninstAPI/h/BPatch_flowGraph.h b/dyninstAPI/h/BPatch_flowGraph.h index f182e3dd6b..0ad5d8d21d 100644 --- a/dyninstAPI/h/BPatch_flowGraph.h +++ b/dyninstAPI/h/BPatch_flowGraph.h @@ -33,6 +33,7 @@ #include #include +#include #include "Annotatable.h" #include "BPatch_dll.h" #include "BPatch_Vector.h" @@ -41,6 +42,7 @@ #include "BPatch_basicBlockLoop.h" #include "BPatch_loopTreeNode.h" #include "BPatch_edge.h" +#include "dyntypes.h" class func_instance; class AddressSpace; diff --git a/dyninstAPI/h/BPatch_function.h b/dyninstAPI/h/BPatch_function.h index dccfd47070..68f9eb52eb 100644 --- a/dyninstAPI/h/BPatch_function.h +++ b/dyninstAPI/h/BPatch_function.h @@ -31,6 +31,10 @@ #ifndef _BPatch_function_h_ #define _BPatch_function_h_ +#include +#include +#include +#include #include "Annotatable.h" #include "BPatch_dll.h" #include "BPatch_Vector.h" @@ -40,6 +44,7 @@ #include "BPatch_module.h" #include "BPatch_memoryAccess_NP.h" #include "StackMod.h" +#include "dyntypes.h" class func_instance; @@ -102,17 +107,8 @@ class BPATCH_DLL_EXPORT BPatch_function : void identifyParamDependencies(BPatch_function* callee, void* calleeAddress); -#if defined(_MSC_VER) -#pragma warning(push) -#pragma warning(disable:4251) -#endif - // Disable warning that these vectors cannot be used externally, - // which is irrelevant since the vectors are private std::map local_vars; BPatch_Vector params; -#if defined(_MSC_VER) -#pragma warning(pop) -#endif public: //dynC internal use only diff --git a/dyninstAPI/h/BPatch_image.h b/dyninstAPI/h/BPatch_image.h index e1aaca42a7..8133cc5151 100644 --- a/dyninstAPI/h/BPatch_image.h +++ b/dyninstAPI/h/BPatch_image.h @@ -41,6 +41,8 @@ #include "BPatch_parRegion.h" #include "dyntypes.h" +#include +#include #include #include @@ -60,7 +62,7 @@ namespace Dyninst { } namespace PatchAPI { class PatchMgr; - typedef boost::shared_ptr PatchMgrPtr; + typedef dyncompat::shared_ptr PatchMgrPtr; BPATCH_DLL_EXPORT PatchMgrPtr convert(const BPatch_image *); } } @@ -300,10 +302,6 @@ class BPATCH_DLL_EXPORT BPatch_image: public BPatch_sourceObj { void removeObject(BPatch_object *obj); void removeAllModules(); -#if defined(_MSC_VER) -#pragma warning(push) -#pragma warning(disable:4251) -#endif typedef std::map ModMap; typedef std::map ObjMap; @@ -315,9 +313,6 @@ class BPATCH_DLL_EXPORT BPatch_image: public BPatch_sourceObj { BPatch_Vector removed_list; BPatch_Vector unresolvedCF; -#if defined(_MSC_VER) -#pragma warning(pop) -#endif // These private "find" functions convert from internal func_instance // representation to the exported BPatch_Function type diff --git a/dyninstAPI/h/BPatch_instruction.h b/dyninstAPI/h/BPatch_instruction.h index b54b6cc1a9..7693e96227 100644 --- a/dyninstAPI/h/BPatch_instruction.h +++ b/dyninstAPI/h/BPatch_instruction.h @@ -32,7 +32,7 @@ #define _BPatch_instruction_h_ #include "BPatch_dll.h" - +#include "dyntypes.h" #include class BPatch_basicBlock; diff --git a/dyninstAPI/h/BPatch_loopTreeNode.h b/dyninstAPI/h/BPatch_loopTreeNode.h index 45a7b1e200..5624ef27e5 100644 --- a/dyninstAPI/h/BPatch_loopTreeNode.h +++ b/dyninstAPI/h/BPatch_loopTreeNode.h @@ -31,6 +31,8 @@ #ifndef _BPatch_loopTreeNode_h_ #define _BPatch_loopTreeNode_h_ +#include +#include #include "BPatch_dll.h" #include "BPatch_Vector.h" #include "BPatch_function.h" diff --git a/dyninstAPI/h/BPatch_memoryAccess_NP.h b/dyninstAPI/h/BPatch_memoryAccess_NP.h index 04a6bb3db6..55b48af40f 100644 --- a/dyninstAPI/h/BPatch_memoryAccess_NP.h +++ b/dyninstAPI/h/BPatch_memoryAccess_NP.h @@ -36,6 +36,7 @@ #include "BPatch_Vector.h" #include #include "BPatch_instruction.h" +#include "dyntypes.h" class BPatch_point; class internal_instruction; diff --git a/dyninstAPI/h/BPatch_module.h b/dyninstAPI/h/BPatch_module.h index 41900c507d..296d2ca7ae 100644 --- a/dyninstAPI/h/BPatch_module.h +++ b/dyninstAPI/h/BPatch_module.h @@ -35,6 +35,7 @@ #include "BPatch_sourceObj.h" #include "BPatch_enums.h" #include "dyntypes.h" +#include #include #include @@ -112,7 +113,6 @@ class BPATCH_DLL_EXPORT BPatch_module: public BPatch_sourceObj{ bool getSourceObj(BPatch_Vector&); BPatch_sourceObj *getObjParent(); void parseTypes(); - char *parseStabStringSymbol(int line, char *stabstr, void *stabptr); void setDefaultNamespacePrefix(char *name); void handleUnload(); bool isExploratoryModeOn();// true if exploratory or defensive mode is on @@ -263,9 +263,7 @@ class BPATCH_DLL_EXPORT BPatch_module: public BPatch_sourceObj{ bool parseTypesIfNecessary(); BPatch_typeCollection *moduleTypes; - // In particular, we understand the type information - // in both DWARF and STABS format. - void parseStabTypes(); + // We understand the type information in DWARF format. void parseDwarfTypes(); BPatch_funcMap func_map; diff --git a/dyninstAPI/h/BPatch_object.h b/dyninstAPI/h/BPatch_object.h index a0bf665b2f..df1ea77b5c 100644 --- a/dyninstAPI/h/BPatch_object.h +++ b/dyninstAPI/h/BPatch_object.h @@ -33,6 +33,8 @@ #include #include +#include +#include #include "dyntypes.h" #include "BPatch_dll.h" #include "StackMod.h" @@ -102,11 +104,15 @@ class BPATCH_DLL_EXPORT BPatch_object { // BPatch_object::name // Returns the file name of the object - std::string name(); + std::string name() const; // BPatch_object::pathName // Returns the full pathname of the object - std::string pathName(); + std::string pathName() const; + + // BPatch_object::isSharedLib + // Returns true if this object represents a shared library + bool isSharedLib() const; // BPatch_object::offsetToAddr diff --git a/dyninstAPI/h/BPatch_parRegion.h b/dyninstAPI/h/BPatch_parRegion.h index e73eab8b64..068d330f28 100644 --- a/dyninstAPI/h/BPatch_parRegion.h +++ b/dyninstAPI/h/BPatch_parRegion.h @@ -31,6 +31,7 @@ #ifndef _BPatch_parRegion_h_ #define _BPatch_parRegion_h_ +#include #include "BPatch_dll.h" #include "BPatch_Vector.h" diff --git a/dyninstAPI/h/BPatch_point.h b/dyninstAPI/h/BPatch_point.h index 70075720d4..5d44524e41 100644 --- a/dyninstAPI/h/BPatch_point.h +++ b/dyninstAPI/h/BPatch_point.h @@ -31,10 +31,14 @@ #ifndef _BPatch_point_h_ #define _BPatch_point_h_ +#include +#include #include "BPatch_dll.h" #include "BPatch_Vector.h" #include "BPatch_Set.h" #include "BPatch_enums.h" +#include "dyntypes.h" + class instPoint; class BPatch_thread; class BPatch_image; @@ -58,7 +62,7 @@ namespace Dyninst { namespace PatchAPI { class Instance; class Point; - typedef boost::shared_ptr InstancePtr; + typedef dyncompat::shared_ptr InstancePtr; BPATCH_DLL_EXPORT Point *convert(const BPatch_point *, BPatch_callWhen); } } @@ -147,18 +151,9 @@ class BPATCH_DLL_EXPORT BPatch_point { AddressSpace *getAS(); private: -#if defined(_MSC_VER) -#pragma warning(push) -#pragma warning(disable:4251) -#endif - // Disable warning that these vectors cannot be used externally, - // which is irrelevant since the vectors are private BPatch_Vector preSnippets; BPatch_Vector postSnippets; BPatch_Vector allSnippets; -#if defined(_MSC_VER) -#pragma warning(pop) -#endif public: //~BPatch_point() { delete memacc; }; diff --git a/dyninstAPI/h/BPatch_process.h b/dyninstAPI/h/BPatch_process.h index 82f9096919..8f3bb11308 100644 --- a/dyninstAPI/h/BPatch_process.h +++ b/dyninstAPI/h/BPatch_process.h @@ -37,10 +37,14 @@ // #include "BPatch_image.h" #include "BPatch_addressSpace.h" #include "BPatch_enums.h" - +#include "dyntypes.h" #include "BPatch_callbacks.h" #include "PCProcess.h" +#include +#include +#include +#include #include #include diff --git a/dyninstAPI/h/BPatch_snippet.h b/dyninstAPI/h/BPatch_snippet.h index ae1adb0335..8391ff2a24 100644 --- a/dyninstAPI/h/BPatch_snippet.h +++ b/dyninstAPI/h/BPatch_snippet.h @@ -31,6 +31,7 @@ #ifndef _BPatch_snippet_h_ #define _BPatch_snippet_h_ +#include #include "BPatch_dll.h" #include "BPatch_Vector.h" #include "BPatch_sourceObj.h" @@ -41,22 +42,17 @@ #include "BPatch_callbacks.h" #include "BPatch_instruction.h" // for register type #include "BPatch_enums.h" -#include "boost/shared_ptr.hpp" +#include "dyncompat/shared_ptr.hpp" class AstNode; // Don't include the boost shared_ptr library class BPatch_snippet; -typedef boost::shared_ptr AstNodePtr; -namespace boost { - template< typename T > class shared_ptr; - template<> class shared_ptr; -} - +typedef dyncompat::shared_ptr AstNodePtr; namespace Dyninst { namespace PatchAPI { class Snippet; - typedef boost::shared_ptr SnippetPtr; + typedef dyncompat::shared_ptr SnippetPtr; BPATCH_DLL_EXPORT SnippetPtr convert(const BPatch_snippet *); } } diff --git a/dyninstAPI/h/BPatch_sourceObj.h b/dyninstAPI/h/BPatch_sourceObj.h index c4409096c5..fc239a4b4f 100644 --- a/dyninstAPI/h/BPatch_sourceObj.h +++ b/dyninstAPI/h/BPatch_sourceObj.h @@ -44,7 +44,6 @@ typedef enum BPatch_language { BPatch_fortran, BPatch_fortran77, BPatch_fortran90, - BPatch_f90_demangled_stabstr, BPatch_fortran95, BPatch_assembly, BPatch_mixed, @@ -94,7 +93,6 @@ class BPATCH_DLL_EXPORT BPatch_sourceObj { case BPatch_fortran: return "BPatch_fortran"; case BPatch_fortran77: return "BPatch_fortran77"; case BPatch_fortran90: return "BPatch_fortran90"; - case BPatch_f90_demangled_stabstr: return "BPatch_fortran90_demangled_stabstr"; case BPatch_fortran95: return "BPatch_fortran95"; case BPatch_assembly: return "BPatch_assembly"; case BPatch_mixed: return "BPatch_mixed"; diff --git a/dyninstAPI/h/BPatch_statement.h b/dyninstAPI/h/BPatch_statement.h index 5d96d59aa2..744b771eac 100644 --- a/dyninstAPI/h/BPatch_statement.h +++ b/dyninstAPI/h/BPatch_statement.h @@ -32,7 +32,7 @@ #define _BPATCH_STATEMENT_H_ #include "BPatch_dll.h" -#include "Module.h" +#include "Statement.h" class BPatch_module; @@ -69,8 +69,6 @@ class BPATCH_DLL_EXPORT BPatch_statement // (do we guarantee contiguity of addresses here? not sure) void *endAddr(); - ~BPatch_statement() {} - private: // Full parameter ctor -- can only built by friend classes diff --git a/dyninstAPI/h/BPatch_type.h b/dyninstAPI/h/BPatch_type.h index 27728778a5..598b92b9d6 100644 --- a/dyninstAPI/h/BPatch_type.h +++ b/dyninstAPI/h/BPatch_type.h @@ -34,6 +34,8 @@ #include "BPatch_dll.h" #include "BPatch_Vector.h" #include +#include +#include #include "Type.h" #include "Variable.h" @@ -42,7 +44,7 @@ class BPatch_type; namespace Dyninst { namespace SymtabAPI { class Type; - BPATCH_DLL_EXPORT boost::shared_ptr convert(const BPatch_type *, Type::do_share_t); + BPATCH_DLL_EXPORT dyncompat::shared_ptr convert(const BPatch_type *, Type::do_share_t); inline Type* convert(const BPatch_type* t) { return convert(t, Type::share).get(); } @@ -226,7 +228,7 @@ class BPATCH_DLL_EXPORT BPatch_cblock { // which functions use this list BPatch_Vector functions; - Dyninst::SymtabAPI::CBlock *cBlk; + Dyninst::SymtabAPI::CBlock *cBlk{}; void fixupUnknowns(BPatch_module *); public: @@ -252,7 +254,7 @@ class BPATCH_DLL_EXPORT BPatch_type{ BPatch_dataClass type_; //Symtab type - boost::shared_ptr typ; + dyncompat::shared_ptr typ; /* For common blocks */ @@ -265,7 +267,7 @@ class BPATCH_DLL_EXPORT BPatch_type{ protected: // Simple Destructor virtual ~BPatch_type(); - static BPatch_type *findOrCreateType(boost::shared_ptr type); + static BPatch_type *findOrCreateType(dyncompat::shared_ptr type); static BPatch_type *findOrCreateType(Dyninst::SymtabAPI::Type* ty) { return findOrCreateType(ty->reshare()); } @@ -281,7 +283,7 @@ class BPATCH_DLL_EXPORT BPatch_type{ public: BPatch_type(const char *name = NULL, int _ID = 0, BPatch_dataClass = BPatch_dataNullType); - BPatch_type(boost::shared_ptr typ_); + BPatch_type(dyncompat::shared_ptr typ_); BPatch_type(Dyninst::SymtabAPI::Type* t) : BPatch_type(t->reshare()) {} virtual bool operator==(const BPatch_type &) const; @@ -290,7 +292,7 @@ class BPATCH_DLL_EXPORT BPatch_type{ unsigned int getSize(); - boost::shared_ptr getSymtabType(Dyninst::SymtabAPI::Type::do_share_t) const; + dyncompat::shared_ptr getSymtabType(Dyninst::SymtabAPI::Type::do_share_t) const; Dyninst::SymtabAPI::Type* getSymtabType() const { return getSymtabType(Dyninst::SymtabAPI::Type::share).get(); } @@ -323,11 +325,11 @@ class BPATCH_DLL_EXPORT BPatch_localVar{ friend class BPatch; friend class BPatch_function; - BPatch_type *type; - BPatch_storageClass storageClass; + BPatch_type *type{}; + BPatch_storageClass storageClass{}; // scope_t scope; - Dyninst::SymtabAPI::localVar *lVar; + Dyninst::SymtabAPI::localVar *lVar{}; public: // Internal use only diff --git a/dyninstAPI/h/StackMod.h b/dyninstAPI/h/StackMod.h index 20ab274579..5b869f3995 100644 --- a/dyninstAPI/h/StackMod.h +++ b/dyninstAPI/h/StackMod.h @@ -31,6 +31,7 @@ #ifndef _StackMod_h_ #define _StackMod_h_ +#include #include "BPatch_dll.h" #include "stackanalysis.h" @@ -77,8 +78,8 @@ class BPATCH_DLL_EXPORT StackMod virtual std::string format() const { return ""; } protected: - MOrder _order; - MType _type; + MOrder _order{}; + MType _type{}; }; /* Modification to insert stack space at [low, high) */ @@ -99,8 +100,8 @@ class BPATCH_DLL_EXPORT Insert : public StackMod private: Insert(MOrder, int, int); - int _low; - int _high; + int _low{}; + int _high{}; }; /* Modification to remove stack space at [low, high) */ @@ -121,8 +122,8 @@ class BPATCH_DLL_EXPORT Remove : public StackMod private: Remove(MOrder, int, int); - int _low; - int _high; + int _low{}; + int _high{}; }; /* Modification to move stack space from [srcLow, srcHigh) @@ -144,10 +145,10 @@ class BPATCH_DLL_EXPORT Move : public StackMod std::string format() const; private: - int _srcLow; - int _srcHigh; - int _destLow; - int _destHigh; + int _srcLow{}; + int _srcHigh{}; + int _destLow{}; + int _destHigh{}; }; /* Modification to insert a stack canary at function entry @@ -180,9 +181,9 @@ class BPATCH_DLL_EXPORT Canary : public StackMod std::string format() const; private: - int _low; - int _high; - BPatch_function* _failFunc; + int _low{}; + int _high{}; + BPatch_function* _failFunc{}; }; /* Modification to randomize the locations of the DWARF-specified @@ -201,8 +202,8 @@ class BPATCH_DLL_EXPORT Randomize : public StackMod std::string format() const; private: - bool _isSeeded; - int _seed; + bool _isSeeded{}; + int _seed{}; }; #endif diff --git a/dyninstAPI/src/BPatch.C b/dyninstAPI/src/BPatch.C index a08690cb2c..e7999e23b5 100644 --- a/dyninstAPI/src/BPatch.C +++ b/dyninstAPI/src/BPatch.C @@ -28,6 +28,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include #include #include @@ -38,7 +39,6 @@ #endif #define BPATCH_FILE -#include "common/src/Pair.h" #include "common/src/stats.h" #include "BPatch.h" #include "BPatch_libInfo.h" @@ -61,6 +61,7 @@ #endif #include +#include using namespace std; using namespace SymtabAPI; @@ -163,7 +164,7 @@ BPatch::BPatch() APITypes = BPatch_typeCollection::getGlobalTypeCollection(); stdTypes = BPatch_typeCollection::getGlobalTypeCollection(); - vector> sTypes; + vector> sTypes; Symtab::getAllstdTypes(sTypes); BPatch_type* type = NULL; for(const auto& t: sTypes) { @@ -1156,17 +1157,15 @@ BPatch_process *BPatch::processCreate(const char *path, const char *argv[], // just a sanity check for the exitence of struct stat statbuf; if (-1 == stat(path, &statbuf)) { - char ebuf[2048]; - sprintf(ebuf, "createProcess(%s,...): file does not exist\n", path); - reportError(BPatchFatal, 68, ebuf); + auto msg = std::string("createProcess(") + path + ",...): file does not exist\n"; + reportError(BPatchFatal, 68, msg.c_str()); return NULL; } // and ensure its a regular file: if (!S_ISREG(statbuf.st_mode)) { - char ebuf[2048]; - sprintf(ebuf, "createProcess(%s,...): not a regular file \n", path); - reportError(BPatchFatal, 68, ebuf); + auto msg = std::string("createProcess(") + path + ",...): not a regular file\n"; + reportError(BPatchFatal, 68, msg.c_str()); return NULL; } @@ -1174,9 +1173,8 @@ BPatch_process *BPatch::processCreate(const char *path, const char *argv[], if (! ( (statbuf.st_mode & S_IXUSR) || (statbuf.st_mode & S_IXGRP) || (statbuf.st_mode & S_IXOTH) )) { - char ebuf[2048]; - sprintf(ebuf, "createProcess(%s,...): not an executable \n", path); - reportError(BPatchFatal, 68, ebuf); + auto msg = std::string("createProcess(") + path + "%s,...): not an executable\n"; + reportError(BPatchFatal, 68, msg.c_str()); return NULL; } @@ -1395,20 +1393,18 @@ BPatch_type * BPatch::createEnum( const char * name, if (elementNames.size() != elementIds.size()) { return NULL; } - string typeName = name; - dyn_c_vector *>elements; - for (unsigned int i=0; i < elementNames.size(); i++) - elements.push_back(new pair(elementNames[i], elementIds[i])); - - boost::shared_ptr typ(typeEnum::create( typeName, elements)); - if (!typ) return NULL; - - BPatch_type *newType = new BPatch_type(typ); - if (!newType) return NULL; - - APITypes->addType(newType); - return(newType); + // Make the underlying type a 4-byte signed int + dyncompat::shared_ptr underlying_type = dyncompat::make_shared(4, "int", true); + + auto *tenum = new typeEnum(underlying_type, name); + for(auto i=0UL; iaddConstant(elementNames[i], elementIds[i]); + } + + BPatch_type *newType = new BPatch_type(tenum); + APITypes->addType(newType); + return newType; } @@ -1424,20 +1420,10 @@ BPatch_type * BPatch::createEnum( const char * name, BPatch_type * BPatch::createEnum( const char * name, BPatch_Vector &elementNames) { - string typeName = name; - dyn_c_vector *>elements; - for (unsigned int i=0; i < elementNames.size(); i++) - elements.push_back(new pair(elementNames[i], i)); - - boost::shared_ptr typ(typeEnum::create( typeName, elements)); - if (!typ) return NULL; - - BPatch_type *newType = new BPatch_type(typ); - if (!newType) return NULL; - - APITypes->addType(newType); - - return(newType); + // We were only given names, so assume sequentially-ordered values + BPatch_Vector ids(elementNames.size()); + std::iota(ids.begin(), ids.end(), 0); + return createEnum(name, elementNames, ids); } /* @@ -1461,15 +1447,15 @@ BPatch_type * BPatch::createStruct( const char * name, } string typeName = name; - dyn_c_vector > *> fields; + dyn_c_vector > *> fields; for(i=0; i>(fieldNames[i], fieldTypes[i]->getSymtabType(Type::share))); + fields.push_back(new pair>(fieldNames[i], fieldTypes[i]->getSymtabType(Type::share))); } - boost::shared_ptr typ(typeStruct::create(typeName, fields)); + dyncompat::shared_ptr typ(typeStruct::create(typeName, fields)); if (!typ) return NULL; BPatch_type *newType = new BPatch_type(typ); @@ -1501,15 +1487,15 @@ BPatch_type * BPatch::createUnion( const char * name, } string typeName = name; - dyn_c_vector > *> fields; + dyn_c_vector > *> fields; for(i=0; i > (fieldNames[i], fieldTypes[i]->getSymtabType(Type::share))); + fields.push_back(new pair > (fieldNames[i], fieldTypes[i]->getSymtabType(Type::share))); } - boost::shared_ptr typ(typeUnion::create(typeName, fields)); + dyncompat::shared_ptr typ(typeUnion::create(typeName, fields)); if (!typ) return NULL; BPatch_type *newType = new BPatch_type(typ); @@ -1538,7 +1524,7 @@ BPatch_type * BPatch::createArray( const char * name, BPatch_type * ptr, return NULL; string typeName = name; - boost::shared_ptr typ(typeArray::create(typeName, ptr->getSymtabType(Type::share), low, hi)); + dyncompat::shared_ptr typ(typeArray::create(typeName, ptr->getSymtabType(Type::share), low, hi)); if (!typ) return NULL; newType = new BPatch_type(typ); @@ -1565,7 +1551,7 @@ BPatch_type * BPatch::createPointer(const char * name, BPatch_type * ptr, return NULL; string typeName = name; - boost::shared_ptr typ(typePointer::create(typeName, ptr->getSymtabType(Type::share))); + dyncompat::shared_ptr typ(typePointer::create(typeName, ptr->getSymtabType(Type::share))); if (!typ) return NULL; newType = new BPatch_type(typ); @@ -1590,7 +1576,7 @@ BPatch_type * BPatch::createScalar( const char * name, int size) BPatch_type * newType; string typeName = name; - boost::shared_ptr typ(typeScalar::create(typeName, size)); + dyncompat::shared_ptr typ(typeScalar::create(typeName, size)); if (!typ) return NULL; newType = new BPatch_type(typ); @@ -1616,7 +1602,7 @@ BPatch_type * BPatch::createTypedef( const char * name, BPatch_type * ptr) return NULL; string typeName = name; - boost::shared_ptr typ(typeTypedef::create(typeName, ptr->getSymtabType(Type::share))); + dyncompat::shared_ptr typ(typeTypedef::create(typeName, ptr->getSymtabType(Type::share))); if (!typ) return NULL; newType = new BPatch_type(typ); @@ -1865,11 +1851,7 @@ int BPatch::getNotificationFD() { #endif } -/* If true, we return just filenames when the user asks for line info - otherwise, we return filename plus path information. */ -void BPatch::truncateLineInfoFilenames(bool newval) { - mapped_module::truncateLineFilenames = newval; -} +void BPatch::truncateLineInfoFilenames(bool) {} void BPatch::getBPatchVersion(int &major, int &minor, int &subminor) { diff --git a/dyninstAPI/src/BPatch_addressSpace.C b/dyninstAPI/src/BPatch_addressSpace.C index 1313e82c53..aeecf25d36 100644 --- a/dyninstAPI/src/BPatch_addressSpace.C +++ b/dyninstAPI/src/BPatch_addressSpace.C @@ -306,7 +306,7 @@ bool BPatch_addressSpace::deleteSnippet(BPatchSnippetHandle *handle) mal_printf("deleting snippet handle from func at %lx, point at %lx of type %d\n", (Address)handle->getFunc()->getBaseAddr(), handle->instances_.empty() ? 0 : handle->instances_[0]->point()->addr(), - handle->instances_.empty() ? -1 : handle->instances_[0]->point()->type()); + handle->instances_.empty() ? -1 : static_cast(handle->instances_[0]->point()->type())); // if this is a process, check to see if the instrumentation is // executing on the call stack @@ -1010,9 +1010,6 @@ bool BPatch_addressSpace::getRegisters(std::vector ®s) { init_registers(); regs = registers_; return true; - - regs = registers_; - return true; } BPatch_addressSpace::register_iter BPatch_addressSpace::getRegisters_begin() { diff --git a/dyninstAPI/src/BPatch_basicBlock.C b/dyninstAPI/src/BPatch_basicBlock.C index 81e833bf77..bc5706f2d0 100644 --- a/dyninstAPI/src/BPatch_basicBlock.C +++ b/dyninstAPI/src/BPatch_basicBlock.C @@ -30,12 +30,12 @@ #define BPATCH_FILE +#include #include #include -#include +#include #include "util.h" -#include "common/src/Types.h" #include "BPatch_flowGraph.h" #include "BPatch_collections.h" @@ -124,11 +124,11 @@ void BPatch_basicBlock::getSources(BPatch_Vector& srcs){ func_instance *func = flowGraph->getFunction()->lowlevel_func(); SingleContext epred_(func->ifunc(),false,true); //Intraproc epred(&epred_); - std::for_each(boost::make_filter_iterator(epred_, isrcs.begin(), isrcs.end()), - boost::make_filter_iterator(epred_, isrcs.end(), isrcs.end()), - boost::bind(source_helper, - boost::placeholders::_1, - boost::ref(srcs), + std::for_each(dyncompat::make_filter_iterator(epred_, isrcs.begin(), isrcs.end()), + dyncompat::make_filter_iterator(epred_, isrcs.end(), isrcs.end()), + dyncompat::bind(source_helper, + dyncompat::placeholders::_1, + dyncompat::ref(srcs), flowGraph, func)); diff --git a/dyninstAPI/src/BPatch_basicBlockLoop.C b/dyninstAPI/src/BPatch_basicBlockLoop.C index f07ba794f2..2b610bfe77 100644 --- a/dyninstAPI/src/BPatch_basicBlockLoop.C +++ b/dyninstAPI/src/BPatch_basicBlockLoop.C @@ -33,7 +33,6 @@ #include #include #include -#include "common/src/std_namesp.h" #include "BPatch_basicBlockLoop.h" #include #include diff --git a/dyninstAPI/src/BPatch_binaryEdit.C b/dyninstAPI/src/BPatch_binaryEdit.C index 60bc7ae291..69b8b120b1 100644 --- a/dyninstAPI/src/BPatch_binaryEdit.C +++ b/dyninstAPI/src/BPatch_binaryEdit.C @@ -30,6 +30,7 @@ #define BPATCH_FILE +#include #include "binaryEdit.h" #include "addressSpace.h" #include "inst.h" @@ -60,7 +61,7 @@ #include "mapped_object.h" #include "Relocation/DynAddrSpace.h" -#include "boost/filesystem.hpp" +#include using Dyninst::PatchAPI::DynAddrSpacePtr; using Dyninst::PatchAPI::DynAddrSpace; @@ -281,7 +282,7 @@ bool BPatch_binaryEdit::finalizeInsertionSet(bool /*atomic*/, bool * /*modified* BPatch_object *BPatch_binaryEdit::loadLibrary(const char *libname, bool deps) { - boost::filesystem::path p(libname); + std::filesystem::path p(libname); string filename = p.filename().string(); auto loaded = loadedLibrary.find(filename); if (loaded != loadedLibrary.end()) { diff --git a/dyninstAPI/src/BPatch_collections.C b/dyninstAPI/src/BPatch_collections.C index f4e2986a37..589e19dad1 100644 --- a/dyninstAPI/src/BPatch_collections.C +++ b/dyninstAPI/src/BPatch_collections.C @@ -28,6 +28,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include #define BPATCH_FILE diff --git a/dyninstAPI/src/BPatch_collections.h b/dyninstAPI/src/BPatch_collections.h index 692fa7276d..e4cbad506f 100644 --- a/dyninstAPI/src/BPatch_collections.h +++ b/dyninstAPI/src/BPatch_collections.h @@ -103,7 +103,7 @@ class BPatch_typeCollection { /* Some debug formats allow forward references. Rather than fill in forward in a second pass, generate placeholder types, and fill them in as we go. Because we require - One True Pointer for each type (in parseStab.C), when + One True Pointer for each type, when updating a type, return that One True Pointer. */ BPatch_type * findOrCreateType( const int & ID ); BPatch_type * addOrUpdateType( BPatch_type * type ); diff --git a/dyninstAPI/src/BPatch_edge.C b/dyninstAPI/src/BPatch_edge.C index 29fc5c1e89..aa12aefac5 100644 --- a/dyninstAPI/src/BPatch_edge.C +++ b/dyninstAPI/src/BPatch_edge.C @@ -117,9 +117,12 @@ BPatch_point *BPatch_edge::getPoint() BPatch_flowGraph *cfg = getFlowGraph(); instPoint *ip = instPoint::edge(cfg->ll_func(), edge); + if (ip == nullptr) { + return point; + } AddressSpace *as = cfg->getllAddSpace(); assert(as); - + BPatch_point *newPoint = new BPatch_point(cfg->getAddSpace(), cfg->getFunction(), this, diff --git a/dyninstAPI/src/BPatch_flowGraph.C b/dyninstAPI/src/BPatch_flowGraph.C index fc5715365f..b2db492b18 100644 --- a/dyninstAPI/src/BPatch_flowGraph.C +++ b/dyninstAPI/src/BPatch_flowGraph.C @@ -30,15 +30,14 @@ #define BPATCH_FILE +#include #include #include #include #include #include -#include "common/src/Types.h" #include -#include "common/src/Pair.h" #include "BPatch_process.h" #include "BPatch_edge.h" @@ -588,32 +587,6 @@ void BPatch_flowGraph::fillPostDominatorInfo() } -// return a pair of the min and max source lines for this loop -pdpair -getLoopMinMaxSourceLines(BPatch_loop * loop) -{ - BPatch_Vector blocks; - loop->getLoopBasicBlocks(blocks); - - BPatch_Vector lines; - - for (u_int j = 0; j < blocks.size (); j++) { - BPatch_Vector sourceBlocks; - blocks[j]->getSourceBlocks(sourceBlocks); - - for (u_int k = 0; k < sourceBlocks.size (); k++) { - BPatch_Vector sourceLines; - sourceBlocks[k]->getSourceLines(sourceLines); - for (u_int l = 0; l < sourceLines.size(); l++) - lines.push_back(sourceLines[l]); - } - } - - pdpair mm = min_max_pdpair(lines); - return mm; -} - - BPatch_loopTreeNode *BPatch_flowGraph::getLoopTree() { if (loopRoot == NULL) { @@ -633,9 +606,6 @@ BPatch_loop *BPatch_flowGraph::findLoop(const char *name) void BPatch_flowGraph::dfsPrintLoops(BPatch_loopTreeNode *n) { if (n->loop != NULL) { - // pdpair mm = getLoopMinMaxSourceLines(n->loop); - // printf("%s (source %d-%d)\n", n->name(), mm.first, mm.second); - printf("%s %s\n", n->name(),ll_func()->prettyName().c_str()); } diff --git a/dyninstAPI/src/BPatch_function.C b/dyninstAPI/src/BPatch_function.C index 6ae905ef50..67ac1596de 100644 --- a/dyninstAPI/src/BPatch_function.C +++ b/dyninstAPI/src/BPatch_function.C @@ -32,6 +32,7 @@ #define BPATCH_FILE +#include #include #include #include "function.h" @@ -59,7 +60,6 @@ #include "StackMod/StackModChecker.h" #endif -#include "common/src/Types.h" #include "Point.h" #include "PatchMgr.h" @@ -954,7 +954,7 @@ BPatch_variableExpr *BPatch_function::getFunctionRef() // But since we are adding this as part of the DPCL compatibility process // we use the IBM API, to eliminate one API difference. - AstNodePtr ast(AstNode::operandNode(AstNode::Constant, (void *) remoteAddress)); + AstNodePtr ast(AstNode::operandNode(AstNode::operandType::Constant, (void *) remoteAddress)); // the variableExpr owns the ast now. return new BPatch_variableExpr(fname.c_str(), addSpace, lladdSpace, ast, diff --git a/dyninstAPI/src/BPatch_image.C b/dyninstAPI/src/BPatch_image.C index 16294c8cef..546cc5cf78 100644 --- a/dyninstAPI/src/BPatch_image.C +++ b/dyninstAPI/src/BPatch_image.C @@ -32,6 +32,7 @@ #define BPATCH_FILE +#include #include #include #include @@ -279,7 +280,7 @@ bool BPatch_image::setFuncModulesCallback(BPatch_function *bpf, void *data) if ( bpf->getModule() == NULL ) { char name[256]; - fprintf(stderr, "Warning: bpf '%s' unclaimed, setting to DEFAULT_MODULE\n", + fprintf(stderr, "Warning: bpf '%s' unclaimed, setting to default module\n", bpf->getName( name, 255 ) ); bpf->setModule( img->defaultModule ); } diff --git a/dyninstAPI/src/BPatch_instruction.C b/dyninstAPI/src/BPatch_instruction.C index b460f0eeb8..318557e2d4 100644 --- a/dyninstAPI/src/BPatch_instruction.C +++ b/dyninstAPI/src/BPatch_instruction.C @@ -28,8 +28,6 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "common/src/Types.h" - #include #include #include diff --git a/dyninstAPI/src/BPatch_libInfo.h b/dyninstAPI/src/BPatch_libInfo.h index 76bdd710d2..1c44af28e2 100644 --- a/dyninstAPI/src/BPatch_libInfo.h +++ b/dyninstAPI/src/BPatch_libInfo.h @@ -35,7 +35,7 @@ #include "dyninstAPI/h/BPatch_process.h" #include "dyninstAPI/h/BPatch_point.h" #include -#include "common/src/Types.h" +#include "dyntypes.h" #include "common/h/util.h" #include "util.h" @@ -47,14 +47,14 @@ class BPatch_libInfo { {} bool registerMonitoredPoint(BPatch_point *point); - BPatch_point *getMonitoredPoint(Address addr); + BPatch_point *getMonitoredPoint(Dyninst::Address addr); - int getStopThreadCallbackID(Address cb); + int getStopThreadCallbackID(Dyninst::Address cb); protected: int stopThreadIDCounter_; - std::unordered_map stopThreadCallbacks_; - std::unordered_map monitoredPoints_; + std::unordered_map stopThreadCallbacks_; + std::unordered_map monitoredPoints_; }; #endif /* _BPatch_libInfo_h_ */ diff --git a/dyninstAPI/src/BPatch_memoryAccess.C b/dyninstAPI/src/BPatch_memoryAccess.C index 6d51be31b3..2a00f73c26 100644 --- a/dyninstAPI/src/BPatch_memoryAccess.C +++ b/dyninstAPI/src/BPatch_memoryAccess.C @@ -33,7 +33,6 @@ #include #include -#include "../../common/src/Types.h" #include "BPatch_memoryAccess_NP.h" #include "BPatch_Vector.h" #include "BPatch_point.h" @@ -138,7 +137,7 @@ BPatch_memoryAccess* BPatch_memoryAccess::init_tables() } // initializes only the first access; #bytes is a constant -BPatch_memoryAccess::BPatch_memoryAccess(internal_instruction *insn, Address _addr, +BPatch_memoryAccess::BPatch_memoryAccess(internal_instruction *insn, Dyninst::Address _addr, bool _isLoad, bool _isStore, unsigned int _bytes, long _imm, int _ra, int _rb, unsigned int _scale, int _cond, bool _nt) : @@ -151,7 +150,7 @@ BPatch_memoryAccess::BPatch_memoryAccess(internal_instruction *insn, Address _ad } // initializes only the first access; #bytes is an expression w/scale -BPatch_memoryAccess::BPatch_memoryAccess(internal_instruction *insn, Address _addr, +BPatch_memoryAccess::BPatch_memoryAccess(internal_instruction *insn, Dyninst::Address _addr, bool _isLoad, bool _isStore, long _imm_s, int _ra_s, int _rb_s, unsigned int _scale_s, long _imm_c, int _ra_c, int _rb_c, unsigned int _scale_c, int _cond, bool _nt, int _preFcn) : @@ -164,7 +163,7 @@ BPatch_memoryAccess::BPatch_memoryAccess(internal_instruction *insn, Address _ad } // initializes only the first access; #bytes is an expression -BPatch_memoryAccess::BPatch_memoryAccess(internal_instruction *insn, Address _addr, +BPatch_memoryAccess::BPatch_memoryAccess(internal_instruction *insn, Dyninst::Address _addr, bool _isLoad, bool _isStore, bool _isPrefetch, long _imm_s, int _ra_s, int _rb_s, long _imm_c, int _ra_c, int _rb_c, unsigned short _preFcn) : @@ -178,7 +177,7 @@ BPatch_memoryAccess::BPatch_memoryAccess(internal_instruction *insn, Address _ad } // initializes only the first access; #bytes is an expression & not a prefetch -BPatch_memoryAccess::BPatch_memoryAccess(internal_instruction *insn, Address _addr, +BPatch_memoryAccess::BPatch_memoryAccess(internal_instruction *insn, Dyninst::Address _addr, bool _isLoad, bool _isStore, long _imm_s, int _ra_s, int _rb_s, long _imm_c, int _ra_c, int _rb_c) : BPatch_instruction(insn, _addr) @@ -224,7 +223,7 @@ void BPatch_memoryAccess::set2nd(bool _isLoad, bool _isStore, } // initializes both accesses; #bytes is a constant -BPatch_memoryAccess::BPatch_memoryAccess(internal_instruction *insn, Address _addr, +BPatch_memoryAccess::BPatch_memoryAccess(internal_instruction *insn, Dyninst::Address _addr, bool _isLoad, bool _isStore, unsigned int _bytes, long _imm, int _ra, int _rb, unsigned int _scale, bool _isLoad2, bool _isStore2, unsigned int _bytes2, @@ -238,7 +237,7 @@ BPatch_memoryAccess::BPatch_memoryAccess(internal_instruction *insn, Address _ad } // initializes both accesses; #bytes is an expression & not a prefetch -BPatch_memoryAccess::BPatch_memoryAccess(internal_instruction *insn, Address _addr, +BPatch_memoryAccess::BPatch_memoryAccess(internal_instruction *insn, Dyninst::Address _addr, bool _isLoad, bool _isStore, long _imm_s, int _ra_s, int _rb_s, unsigned int _scale_s, long _imm_c, int _ra_c, int _rb_c, unsigned int _scale_c, bool _isLoad2, bool _isStore2, long _imm2_s, diff --git a/dyninstAPI/src/BPatch_memoryAccessAdapter.C b/dyninstAPI/src/BPatch_memoryAccessAdapter.C index 5dcfc47d0a..4a87c4648d 100644 --- a/dyninstAPI/src/BPatch_memoryAccessAdapter.C +++ b/dyninstAPI/src/BPatch_memoryAccessAdapter.C @@ -44,7 +44,7 @@ using namespace InstructionAPI; BPatch_memoryAccess* BPatch_memoryAccessAdapter::convert(Instruction insn, - Address current, bool is64) + Dyninst::Address current, bool is64) { #if defined(arch_x86) || defined(arch_x86_64) static unsigned int log2[] = { 0, 0, 1, 1, 2, 2, 2, 2, 3 }; @@ -179,7 +179,7 @@ BPatch_memoryAccess* BPatch_memoryAccessAdapter::convert(Instruction insn, } assert(nac < 3); return bmap; -#elif defined(arch_ppc)||defined(arch_ppc64) +#elif defined arch_power std::vector operands; insn.getOperands(operands); for(std::vector::iterator op = operands.begin(); @@ -195,7 +195,7 @@ BPatch_memoryAccess* BPatch_memoryAccessAdapter::convert(Instruction insn, insn.getOperation().getID() == power_op_stmw) { RegisterAST::Ptr byteOverride = - boost::dynamic_pointer_cast(insn.getOperand(0).getValue()); + dyncompat::dynamic_pointer_cast(insn.getOperand(0).getValue()); assert(byteOverride); MachRegister base = byteOverride->getID().getBaseRegister(); unsigned int converted = base.val() & 0xFFFF; @@ -205,7 +205,7 @@ BPatch_memoryAccess* BPatch_memoryAccessAdapter::convert(Instruction insn, insn.getOperation().getID() == power_op_stswi) { Immediate::Ptr byteOverride = - boost::dynamic_pointer_cast(insn.getOperand(2).getValue()); + dyncompat::dynamic_pointer_cast(insn.getOperand(2).getValue()); assert(byteOverride); bytes = byteOverride->eval().convert(); if(bytes == 0) bytes = 32; @@ -268,7 +268,7 @@ void BPatch_memoryAccessAdapter::visit(RegisterAST* r) //fprintf(stderr, "base: %d\n", base.val()); unsigned int converted = base.val() & 0xFFFF; - #if defined(arch_ppc)||defined(arch_ppc64) + #if defined arch_power if((ra == -1) && !setImm) { ra = converted; return; diff --git a/dyninstAPI/src/BPatch_memoryAccessAdapter.h b/dyninstAPI/src/BPatch_memoryAccessAdapter.h index 9da082ee1c..f1a8d39392 100644 --- a/dyninstAPI/src/BPatch_memoryAccessAdapter.h +++ b/dyninstAPI/src/BPatch_memoryAccessAdapter.h @@ -32,7 +32,7 @@ #include "Visitor.h" #include "Instruction.h" -#include "common/src/Types.h" +#include "dyntypes.h" class BPatch_memoryAccess; @@ -41,14 +41,14 @@ class BPatch_memoryAccessAdapter : public Dyninst::InstructionAPI::Visitor public: BPatch_memoryAccessAdapter() : bytes(0), imm(0), ra(-1), rb(-1), sc(0), - leftshift(false), setImm(false) { + setImm(false) { } virtual ~BPatch_memoryAccessAdapter() { } BPatch_memoryAccess* convert(Dyninst::InstructionAPI::Instruction insn, - Address current, bool is64); + Dyninst::Address current, bool is64); virtual void visit(Dyninst::InstructionAPI::BinaryFunction* b); virtual void visit(Dyninst::InstructionAPI::Dereference* d); virtual void visit(Dyninst::InstructionAPI::RegisterAST* r); @@ -59,7 +59,6 @@ class BPatch_memoryAccessAdapter : public Dyninst::InstructionAPI::Visitor int ra; int rb; int sc; - bool leftshift; bool setImm; }; diff --git a/dyninstAPI/src/BPatch_module.C b/dyninstAPI/src/BPatch_module.C index 6a7b0548e3..a55c6c6000 100644 --- a/dyninstAPI/src/BPatch_module.C +++ b/dyninstAPI/src/BPatch_module.C @@ -28,6 +28,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include #include #include @@ -114,7 +115,7 @@ const char *BPatch_module::libraryName() return NULL; if (isSharedLib()) - return mod->fullName().c_str(); + return mod->fileName().c_str(); return NULL; } @@ -123,7 +124,7 @@ char *BPatch_module::getFullName(char *buffer, int length) { if (!mod) return NULL; - string str = mod->fullName(); + string str = mod->fileName(); strncpy(buffer, str.c_str(), length); @@ -155,10 +156,6 @@ BPatch_module::BPatch_module(BPatch_addressSpace *_addSpace, setLanguage( BPatch_cPlusPlus ); break; - case lang_Fortran_with_pretty_debug: - setLanguage( BPatch_f90_demangled_stabstr ); - break; - case lang_Fortran: case lang_CMFortran: setLanguage( BPatch_fortran ); @@ -260,7 +257,7 @@ bool BPatch_module::parseTypesIfNecessary() mod->pmod()->mod()->exec()->parseTypesNow(); moduleTypes = BPatch_typeCollection::getModTypeCollection(this); - vector> modtypes; + vector> modtypes; mod->pmod()->mod()->getAllTypes(modtypes); if (modtypes.empty()) @@ -273,7 +270,7 @@ bool BPatch_module::parseTypesIfNecessary() moduleTypes->addType(type); } - vector > > globalVars; + vector > > globalVars; mod->pmod()->mod()->getAllGlobalVars(globalVars); if (globalVars.empty()) @@ -531,9 +528,7 @@ BPatch_module::findFunctionByAddress(void *addr, BPatch_VectorfileName()); - BPatch_reportError(BPatchSerious, 100, msg.c_str()); + BPatch_reportError(BPatchSerious, 100, "Module is not valid"); } return NULL; } diff --git a/dyninstAPI/src/BPatch_object.C b/dyninstAPI/src/BPatch_object.C index 705767facb..1503b6cb36 100644 --- a/dyninstAPI/src/BPatch_object.C +++ b/dyninstAPI/src/BPatch_object.C @@ -28,6 +28,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include #include @@ -45,6 +46,7 @@ #include "BPatch_function.h" #include "debug.h" #include "BPatch_point.h" +#include "registers/x86_64_regs.h" const Dyninst::Address BPatch_object::E_OUT_OF_BOUNDS((Dyninst::Address) -1); @@ -71,14 +73,18 @@ AddressSpace *BPatch_object::ll_as() { return obj->proc(); } BPatch_addressSpace *BPatch_object::as() { return img->getAddressSpace(); } -std::string BPatch_object::name() { +std::string BPatch_object::name() const { return obj->fileName(); } -std::string BPatch_object::pathName() { +std::string BPatch_object::pathName() const { return obj->fullName(); } +bool BPatch_object::isSharedLib() const { + return obj->isSharedLib(); +} + Dyninst::Address BPatch_object::fileOffsetToAddr(const Dyninst::Offset fileOffset) { // File offset, so duck into SymtabAPI to turn it into a "mem offset" // (aka ELF shifted) address diff --git a/dyninstAPI/src/BPatch_point.C b/dyninstAPI/src/BPatch_point.C index 29eb5c48f2..a0d5b64ed9 100644 --- a/dyninstAPI/src/BPatch_point.C +++ b/dyninstAPI/src/BPatch_point.C @@ -574,37 +574,37 @@ bool BPatchToInternalArgs(BPatch_point *point, return false; // - // Check for valid combinations of BPatch_procedureLocation & call* - // Right now we don't allow - // BPatch_callBefore + BPatch_exit - // BPatch_callAfter + BPatch_entry - // - // These combinations are intended to be used to mark the point that - // is the last, first valid point where the local variables are - // valid. This is different than the first/last instruction of - // a subroutine which is what the other combinations of BPatch_entry - // and BPatch_exit refer to. - // - if (when == BPatch_callBefore && point->getPointType() == BPatch_exit) { - BPatch_reportError(BPatchSerious, 113, - "BPatch_callBefore at BPatch_exit not supported yet"); - return false; - } - if (when == BPatch_callAfter && point->getPointType() == BPatch_entry) { - BPatch_reportError(BPatchSerious, 113, - "BPatch_callAfter at BPatch_entry not supported yet"); - return false; - } + // Check for valid combinations of BPatch_procedureLocation & call* + // Right now we don't allow + // BPatch_callBefore + BPatch_exit + // BPatch_callAfter + BPatch_entry + // + // These combinations are intended to be used to mark the point that + // is the last, first valid point where the local variables are + // valid. This is different than the first/last instruction of + // a subroutine which is what the other combinations of BPatch_entry + // and BPatch_exit refer to. + // + if (when == BPatch_callBefore && point->getPointType() == BPatch_exit) { + BPatch_reportError(BPatchSerious, 113, + "BPatch_callBefore at BPatch_exit not supported yet"); + return false; + } + if (when == BPatch_callAfter && point->getPointType() == BPatch_entry) { + BPatch_reportError(BPatchSerious, 113, + "BPatch_callAfter at BPatch_entry not supported yet"); + return false; + } - if ((point->getPointType() == BPatch_exit)) { - // XXX - Hack! - // The semantics of pre/post insn at exit are setup for the new - // defintion of using this to control before/after stack creation, - // but the lower levels of dyninst don't know about this yet. - ipWhen = callPreInsn; - } + if ((point->getPointType() == BPatch_exit)) { + // XXX - Hack! + // The semantics of pre/post insn at exit are setup for the new + // defintion of using this to control before/after stack creation, + // but the lower levels of dyninst don't know about this yet. + ipWhen = callPreInsn; + } - return true; + return true; } BPatch_procedureLocation BPatch_point::convertInstPointType_t(int intType) diff --git a/dyninstAPI/src/BPatch_private.h b/dyninstAPI/src/BPatch_private.h index 2bd007e2fa..0748cc7578 100644 --- a/dyninstAPI/src/BPatch_private.h +++ b/dyninstAPI/src/BPatch_private.h @@ -36,6 +36,7 @@ class BPatchSnippetHandle; class BPatch_point; class BPatch_snippet; +#include #include "BPatch_snippet.h" // TODO: this is bpatch-specific, move to BPatch_private.h? diff --git a/dyninstAPI/src/BPatch_process.C b/dyninstAPI/src/BPatch_process.C index b331fc65a5..76ce2a8493 100644 --- a/dyninstAPI/src/BPatch_process.C +++ b/dyninstAPI/src/BPatch_process.C @@ -30,6 +30,7 @@ #define BPATCH_FILE +#include #include #include "inst.h" @@ -57,8 +58,7 @@ #include "parseAPI/h/CFG.h" #include "ast.h" #include "debug.h" -#include "MemoryEmulator/memEmulator.h" -#include +#include #include "PatchMgr.h" #include "PatchModifier.h" @@ -231,54 +231,6 @@ BPatch_process::BPatch_process(const char *path, const char *argv[], startup_cerr << "BPatch_process::BPatch_process, completed." << endl; } -#if defined(os_linux) -/* Particular linux kernels running dyninst in particular patterns - (namely, with a single process having spawned the mutator and the - mutatee) are susceptible to a kernel bug that will cause a panic - if the mutator exits before the mutatee. See the comment above - class ForkNewProcessCallback : public DBICallbackBase in - debuggerinterface.h for details. -*/ -bool LinuxConsideredHarmful(pid_t pid) // PUSH -{ - int major, minor, sub, subsub; // version numbers - pid_t my_ppid, my_pid, mutatee_ppid = 0; - FILE *fd; - char buf[1024]; - char filename[64]; - - get_linux_version(major,minor,sub,subsub); - - if( major == 2 && minor == 6 && - (sub < 11 || (sub == 11 && subsub <= 11)) ) - { - my_ppid = getppid(); - my_pid = getpid(); - // If anybody knows a better way to get the parent pid, be my - // guest to change this. - snprintf(filename, 64, "/proc/%d/status", pid); - fd = fopen(filename, "r"); - if (!fd) { - startup_printf("Failed to open %s, assuming no linux kernel bug\n", - filename); - return false; - } - while (fgets(buf, 1024, fd)) { - if (strncmp(buf, "PPid", 4) == 0) { - sscanf(buf, "%*s %d", &mutatee_ppid); - break; - } - } - fclose(fd); - - if(my_ppid == mutatee_ppid || - my_pid == mutatee_ppid) - return true; - } - - return false; -} -#endif /* * BPatch_process::BPatch_process * @@ -299,23 +251,6 @@ BPatch_process::BPatch_process image = NULL; pendingInsertions = NULL; -#if defined(os_linux) - /* We need to test whether we are in kernel 2.6.9 - 2.6.11.11 (inclusive). - If so, and if the mutatee's parent and our parent are one and the same, - we are exposing the user to a potential kernel panic. - */ - startup_printf("Checking for potential Linux kernel bug...\n"); - if(LinuxConsideredHarmful(pid)) - { - fprintf(stderr, - "\nWARNING: You are running a Linux kernel between 2.6.9 and \n" - "2.6.11.11 (inclusive). Executing Dyninst under this kernel \n" - "may exercise a bug in the Linux kernel and lead to a panic \n" - "under some conditions. We STRONGLY suggest that you upgrade \n" - "your kernel to 2.6.11.12 or higher.\n\n"); - } -#endif - assert(BPatch::bpatch != NULL); startup_printf("%s[%d]: creating new BPatch_image...\n", FILE__, __LINE__); @@ -1453,11 +1388,6 @@ unsigned char * BPatch_process::makeShadowPage(Dyninst::Address pageAddr) pageAddr = (pageAddr / pagesize) * pagesize; Address shadowAddr = pageAddr; - if (llproc->isMemoryEmulated()) { - bool valid = false; - boost::tie(valid, shadowAddr) = llproc->getMemEm()->translate(pageAddr); - assert(valid); - } unsigned char* buf = (unsigned char*) ::malloc(pagesize); llproc->readDataSpace((void*)shadowAddr, pagesize, buf, true); @@ -1507,12 +1437,10 @@ void BPatch_process::overwriteAnalysisUpdate /*2. remove dead code from the analysis */ - // identify the dead code (see getDeadCode for its parameter definitions) std::set delBlocks; std::map > elimMap; std::list deadFuncs; std::map newFuncEntries; - llproc->getDeadCode(owBBIs,delBlocks,elimMap,deadFuncs,newFuncEntries); // remove instrumentation from affected funcs beginInsertionSet(); diff --git a/dyninstAPI/src/BPatch_snippet.C b/dyninstAPI/src/BPatch_snippet.C index 9762705440..ced1c7ce41 100644 --- a/dyninstAPI/src/BPatch_snippet.C +++ b/dyninstAPI/src/BPatch_snippet.C @@ -32,6 +32,7 @@ #define BPATCH_FILE +#include #include #include "BPatch.h" @@ -150,11 +151,11 @@ BPatch_snippet::~BPatch_snippet() AstNodePtr generateVariableBase(const BPatch_snippet &lOperand) { AstNodePtr variableBase; - if(lOperand.ast_wrapper->getoType() == AstNode::variableValue) + if(lOperand.ast_wrapper->getoType() == AstNode::operandType::variableValue) { - variableBase = AstNode::operandNode(AstNode::variableAddr, lOperand.ast_wrapper->getOVar()); + variableBase = AstNode::operandNode(AstNode::operandType::variableAddr, lOperand.ast_wrapper->getOVar()); } - else if(lOperand.ast_wrapper->getoType() == AstNode::variableAddr) + else if(lOperand.ast_wrapper->getoType() == AstNode::operandType::variableAddr) { variableBase = lOperand.ast_wrapper; } @@ -183,25 +184,25 @@ AstNodePtr generateArrayRef(const BPatch_snippet &lOperand, // We have to be a little forgiving of the - typeArray *arrayType = lOperand.ast_wrapper->getType()->getSymtabType(Type::share)->getArrayType(); - if (!arrayType) + if (lOperand.ast_wrapper->getType() == NULL) { - if (lOperand.ast_wrapper->getType() == NULL) - { - BPatch_reportError(BPatchSerious, 109, - "array reference has no type information"); - } - else - { - fprintf(stderr, "%s[%d]: error here: type is %s\n", FILE__, __LINE__, - lOperand.ast_wrapper->getType()->getName()); - BPatch_reportError(BPatchSerious, 109, - "array reference has array reference to non-array type"); - } + BPatch_reportError(BPatchSerious, 109, + "array reference has no type information"); assert(0); return AstNodePtr(); } + typeArray *arrayType = lOperand.ast_wrapper->getType()->getSymtabType(Type::share)->getArrayType(); + if (!arrayType) + { + fprintf(stderr, "%s[%d]: error here: type is %s\n", FILE__, __LINE__, + lOperand.ast_wrapper->getType()->getName()); + BPatch_reportError(BPatchSerious, 109, + "array reference has array reference to non-array type"); + assert(0); + return AstNodePtr(); + } + auto elementType = arrayType->getBaseType(Type::share); assert(elementType); long int elementSize = elementType->getSize(); @@ -251,11 +252,11 @@ AstNodePtr generateArrayRef(const BPatch_snippet &lOperand, // AstNodePtr arrayBase = generateVariableBase(lOperand); - AstNodePtr ast = AstNode::operandNode(AstNode::DataIndir, + AstNodePtr ast = AstNode::operandNode(AstNode::operandType::DataIndir, AstNode::operatorNode(plusOp, arrayBase, AstNode::operatorNode(timesOp, - AstNode::operandNode(AstNode::Constant, + AstNode::operandNode(AstNode::operandType::Constant, (void *)elementSize), rOperand.ast_wrapper))); @@ -308,7 +309,7 @@ AstNodePtr generateFieldRef(const BPatch_snippet &lOperand, BPatch_type *fieldType = const_cast(rOperand.ast_wrapper->getType()); - if (rOperand.ast_wrapper->getoType()!=AstNode::ConstantString + if (rOperand.ast_wrapper->getoType()!=AstNode::operandType::ConstantString || !fieldType || strcmp(fieldType->getName(), "char *")) { @@ -355,10 +356,10 @@ AstNodePtr generateFieldRef(const BPatch_snippet &lOperand, AstNodePtr structBase = generateVariableBase(lOperand); - AstNodePtr ast = AstNode::operandNode(AstNode::DataIndir, + AstNodePtr ast = AstNode::operandNode(AstNode::operandType::DataIndir, AstNode::operatorNode(plusOp, structBase, - AstNode::operandNode(AstNode::Constant, + AstNode::operandNode(AstNode::operandType::Constant, (void *)offset))); extern AnnotationClass TypeUpPtrAnno; @@ -482,7 +483,7 @@ BPatch_arithExpr::BPatch_arithExpr(BPatch_unOp op, switch(op) { case BPatch_negate: { - AstNodePtr negOne = AstNode::operandNode(AstNode::Constant, + AstNodePtr negOne = AstNode::operandNode(AstNode::operandType::Constant, (void *)-1); BPatch_type *type = BPatch::bpatch->stdTypes->findType("int"); assert(type != NULL); @@ -515,7 +516,7 @@ BPatch_arithExpr::BPatch_arithExpr(BPatch_unOp op, ast_wrapper = AstNodePtr(AstNode::operandNode(AstNode::DataIndir, lOperand.ast_wrapper)); } #endif - ast_wrapper = AstNodePtr(AstNode::operandNode(AstNode::DataIndir, lOperand.ast_wrapper)); + ast_wrapper = AstNodePtr(AstNode::operandNode(AstNode::operandType::DataIndir, lOperand.ast_wrapper)); BPatch_type *type = const_cast (lOperand.ast_wrapper->getType()); if (!type || (type->getDataClass() != BPatch_dataPointer)) { @@ -596,7 +597,7 @@ BPatch_boolExpr::BPatch_boolExpr(BPatch_relOp op, BPatch_constExpr::BPatch_constExpr( signed int value ) { assert( BPatch::bpatch != NULL ); - ast_wrapper = AstNodePtr(AstNode::operandNode(AstNode::Constant, + ast_wrapper = AstNodePtr(AstNode::operandNode(AstNode::operandType::Constant, (void *)(uintptr_t) value)); ast_wrapper->setTypeChecking( BPatch::bpatch->isTypeChecked() ); @@ -608,7 +609,7 @@ BPatch_constExpr::BPatch_constExpr( signed int value ) { BPatch_constExpr::BPatch_constExpr( unsigned int value ) { assert( BPatch::bpatch != NULL ); - ast_wrapper = AstNodePtr(AstNode::operandNode(AstNode::Constant, + ast_wrapper = AstNodePtr(AstNode::operandNode(AstNode::operandType::Constant, (void *)(uintptr_t) value)); ast_wrapper->setTypeChecking( BPatch::bpatch->isTypeChecked() ); @@ -620,7 +621,7 @@ BPatch_constExpr::BPatch_constExpr( unsigned int value ) { BPatch_constExpr::BPatch_constExpr( signed long value ) { assert( BPatch::bpatch != NULL ); - ast_wrapper = AstNodePtr(AstNode::operandNode(AstNode::Constant, + ast_wrapper = AstNodePtr(AstNode::operandNode(AstNode::operandType::Constant, (void *)(uintptr_t) value)); ast_wrapper->setTypeChecking( BPatch::bpatch->isTypeChecked() ); @@ -632,7 +633,7 @@ BPatch_constExpr::BPatch_constExpr( signed long value ) { BPatch_constExpr::BPatch_constExpr( unsigned long value ) { assert( BPatch::bpatch != NULL ); - ast_wrapper = AstNodePtr(AstNode::operandNode(AstNode::Constant, + ast_wrapper = AstNodePtr(AstNode::operandNode(AstNode::operandType::Constant, (void *)(uintptr_t) value)); ast_wrapper->setTypeChecking( BPatch::bpatch->isTypeChecked() ); BPatch_type * type = BPatch::bpatch->stdTypes->findType( "unsigned long" ); @@ -643,7 +644,7 @@ BPatch_constExpr::BPatch_constExpr( unsigned long value ) { BPatch_constExpr::BPatch_constExpr(unsigned long long value) { assert(BPatch::bpatch != NULL); - ast_wrapper = AstNodePtr(AstNode::operandNode(AstNode::Constant, + ast_wrapper = AstNodePtr(AstNode::operandNode(AstNode::operandType::Constant, (void *)(uintptr_t)value)); ast_wrapper->setTypeChecking(BPatch::bpatch->isTypeChecked()); BPatch_type * type = BPatch::bpatch->stdTypes->findType("unsigned long long"); @@ -660,7 +661,7 @@ BPatch_constExpr::BPatch_constExpr(unsigned long long value) { */ BPatch_constExpr::BPatch_constExpr(const char *value) { - ast_wrapper = AstNodePtr(AstNode::operandNode(AstNode::ConstantString, (void *)const_cast(value))); + ast_wrapper = AstNodePtr(AstNode::operandNode(AstNode::operandType::ConstantString, (void *)const_cast(value))); assert(BPatch::bpatch != NULL); ast_wrapper->setTypeChecking(BPatch::bpatch->isTypeChecked()); @@ -681,7 +682,7 @@ BPatch_constExpr::BPatch_constExpr(const char *value) */ BPatch_constExpr::BPatch_constExpr(const void *value) { - ast_wrapper = AstNodePtr(AstNode::operandNode(AstNode::Constant, (void *)const_cast(value))); + ast_wrapper = AstNodePtr(AstNode::operandNode(AstNode::operandType::Constant, (void *)const_cast(value))); assert(BPatch::bpatch != NULL); ast_wrapper->setTypeChecking(BPatch::bpatch->isTypeChecked()); @@ -694,7 +695,7 @@ BPatch_constExpr::BPatch_constExpr(const void *value) BPatch_constExpr::BPatch_constExpr(long long value) { - ast_wrapper = AstNodePtr(AstNode::operandNode(AstNode::Constant, (void *)(uintptr_t)value)); + ast_wrapper = AstNodePtr(AstNode::operandNode(AstNode::operandType::Constant, (void *)(uintptr_t)value)); assert(BPatch::bpatch != NULL); ast_wrapper->setTypeChecking(BPatch::bpatch->isTypeChecked()); @@ -824,13 +825,13 @@ BPatch_paramExpr::BPatch_paramExpr(int n, BPatch_ploc loc) AstNode::operandType opType; switch(loc) { case (BPatch_ploc_guess): - opType = AstNode::Param; + opType = AstNode::operandType::Param; break; case (BPatch_ploc_call): - opType = AstNode::ParamAtCall; + opType = AstNode::operandType::ParamAtCall; break; case (BPatch_ploc_entry): - opType = AstNode::ParamAtEntry; + opType = AstNode::operandType::ParamAtEntry; break; default: assert(0); @@ -854,7 +855,7 @@ BPatch_paramExpr::BPatch_paramExpr(int n, BPatch_ploc loc) */ BPatch_retExpr::BPatch_retExpr() { - ast_wrapper = AstNodePtr(AstNode::operandNode(AstNode::ReturnVal, (void *)0)); + ast_wrapper = AstNodePtr(AstNode::operandNode(AstNode::operandType::ReturnVal, (void *)0)); assert(BPatch::bpatch != NULL); ast_wrapper->setTypeChecking(BPatch::bpatch->isTypeChecked()); @@ -870,7 +871,7 @@ BPatch_retExpr::BPatch_retExpr() */ BPatch_retAddrExpr::BPatch_retAddrExpr() { - ast_wrapper = AstNodePtr(AstNode::operandNode(AstNode::ReturnAddr, (void *)0)); + ast_wrapper = AstNodePtr(AstNode::operandNode(AstNode::operandType::ReturnAddr, (void *)0)); assert(BPatch::bpatch != NULL); ast_wrapper->setTypeChecking(BPatch::bpatch->isTypeChecked()); } @@ -885,7 +886,7 @@ BPatch_retAddrExpr::BPatch_retAddrExpr() */ BPatch_registerExpr::BPatch_registerExpr(BPatch_register reg) { - ast_wrapper = AstNodePtr(AstNode::operandNode(AstNode::origRegister, + ast_wrapper = AstNodePtr(AstNode::operandNode(AstNode::operandType::origRegister, (void *)(long)reg.number_)); assert(BPatch::bpatch != NULL); @@ -898,7 +899,7 @@ BPatch_registerExpr::BPatch_registerExpr(BPatch_register reg) BPatch_registerExpr::BPatch_registerExpr(Dyninst::MachRegister mach) { bool whocares; Register reg = convertRegID(mach, whocares); - ast_wrapper = AstNodePtr(AstNode::operandNode(AstNode::origRegister, + ast_wrapper = AstNodePtr(AstNode::operandNode(AstNode::operandType::origRegister, (void *)(intptr_t)reg)); assert(BPatch::bpatch != NULL); @@ -994,11 +995,11 @@ BPatch_variableExpr::BPatch_variableExpr(BPatch_addressSpace *in_addSpace, size = type_->getSize(); if(img_var) { - ast_wrapper = AstNodePtr(AstNode::operandNode(AstNode::variableValue, img_var)); + ast_wrapper = AstNodePtr(AstNode::operandNode(AstNode::operandType::variableValue, img_var)); } else { - ast_wrapper = AstNodePtr(AstNode::operandNode(AstNode::DataAddr, (void*)(NULL))); + ast_wrapper = AstNodePtr(AstNode::operandNode(AstNode::operandType::DataAddr, (void*)(NULL))); } @@ -1108,7 +1109,7 @@ BPatch_variableExpr::BPatch_variableExpr(BPatch_addressSpace *in_addSpace, type = BPatch::bpatch->type_Untyped; switch (in_storage) { case BPatch_storageAddr: - variableAst = AstNodePtr(AstNode::operandNode(AstNode::DataAddr, address)); + variableAst = AstNodePtr(AstNode::operandNode(AstNode::operandType::DataAddr, address)); isLocal = false; break; case BPatch_storageAddrRef: @@ -1116,7 +1117,7 @@ BPatch_variableExpr::BPatch_variableExpr(BPatch_addressSpace *in_addSpace, isLocal = false; break; case BPatch_storageReg: - variableAst = AstNodePtr(AstNode::operandNode(AstNode::origRegister, + variableAst = AstNodePtr(AstNode::operandNode(AstNode::operandType::origRegister, (void *)(long)in_register)); isLocal = true; break; @@ -1125,14 +1126,14 @@ BPatch_variableExpr::BPatch_variableExpr(BPatch_addressSpace *in_addSpace, isLocal = true; break; case BPatch_storageRegOffset: - variableAst = AstNodePtr(AstNode::operandNode(AstNode::RegOffset, - AstNode::operandNode(AstNode::DataAddr, + variableAst = AstNodePtr(AstNode::operandNode(AstNode::operandType::RegOffset, + AstNode::operandNode(AstNode::operandType::DataAddr, address))); variableAst->setOValue( (void *)(long int)in_register ); isLocal = true; break; case BPatch_storageFrameOffset: - variableAst = AstNodePtr(AstNode::operandNode(AstNode::FrameAddr, address)); + variableAst = AstNodePtr(AstNode::operandNode(AstNode::operandType::FrameAddr, address)); isLocal = true; break; } @@ -1193,7 +1194,7 @@ BPatch_variableExpr::BPatch_variableExpr(BPatch_addressSpace *in_addSpace, int in_register = convertRegID(locs[i].mr_reg, ignored); switch (in_storage) { case BPatch_storageAddr: - variableAst = AstNode::operandNode(AstNode::DataAddr, in_address); + variableAst = AstNode::operandNode(AstNode::operandType::DataAddr, in_address); isLocal = false; address = in_address; break; @@ -1201,7 +1202,7 @@ BPatch_variableExpr::BPatch_variableExpr(BPatch_addressSpace *in_addSpace, //assert( 0 ); // Not implemented yet. continue; case BPatch_storageReg: - variableAst = AstNode::operandNode(AstNode::origRegister, + variableAst = AstNode::operandNode(AstNode::operandType::origRegister, (void *)(long)in_register); isLocal = true; break; @@ -1209,14 +1210,14 @@ BPatch_variableExpr::BPatch_variableExpr(BPatch_addressSpace *in_addSpace, //assert( 0 ); // Not implemented yet. continue; case BPatch_storageRegOffset: - variableAst = AstNode::operandNode(AstNode::RegOffset, - AstNode::operandNode(AstNode::DataAddr, + variableAst = AstNode::operandNode(AstNode::operandType::RegOffset, + AstNode::operandNode(AstNode::operandType::DataAddr, in_address)); variableAst->setOValue( (void *)(long int)in_register ); isLocal = true; break; case BPatch_storageFrameOffset: - variableAst = AstNode::operandNode(AstNode::FrameAddr, in_address); + variableAst = AstNode::operandNode(AstNode::operandType::FrameAddr, in_address); isLocal = true; break; } @@ -1403,10 +1404,10 @@ BPatch_Vector *BPatch_variableExpr::getComponents() BPatch_variableExpr *newVar; // convert to *(&basrVar + offset) - AstNodePtr fieldExpr = AstNode::operandNode(AstNode::DataIndir, + AstNodePtr fieldExpr = AstNode::operandNode(AstNode::operandType::DataIndir, AstNode::operatorNode(plusOp, generateVariableBase(*this), - AstNode::operandNode(AstNode::Constant, (void *)offset))); + AstNode::operandNode(AstNode::operandType::Constant, (void *)offset))); if( field->getType() != NULL ) { AstNodePtr newAst = fieldExpr; newVar = new BPatch_variableExpr(const_cast (field->getName()), @@ -1450,8 +1451,6 @@ BPatch_effectiveAddressExpr::BPatch_effectiveAddressExpr(int _which, int size) { #if defined(i386_unknown_nt4_0) assert(_which >= 0 && _which <= 2); -#elif defined (__XLC__) || defined(__xlC__) - assert(_which >= 0 && _which <= 1); #else assert(_which >= 0 && _which <= (int) BPatch_instruction::nmaxacc_NP); #endif @@ -1468,8 +1467,6 @@ BPatch_bytesAccessedExpr::BPatch_bytesAccessedExpr(int _which) { #if defined(i386_unknown_nt4_0) assert(_which >= 0 && _which <= 2); -#elif defined (__XLC__) || defined(__xlC__) - assert(_which >= 0 && _which <= 1); #else assert(_which >= 0 && _which <= (int)BPatch_instruction::nmaxacc_NP); #endif @@ -1550,7 +1547,7 @@ static void constructorHelper( // create callback ID argument intptr_t cb_id = BPatch::bpatch->getStopThreadCallbackID(bp_cb); - idNode = AstNode::operandNode(AstNode::Constant, (void*) cb_id ); + idNode = AstNode::operandNode(AstNode::operandType::Constant, (void*) cb_id ); BPatch_type *inttype = BPatch::bpatch->stdTypes->findType("int"); assert(inttype != NULL); idNode->setType(inttype); @@ -1563,7 +1560,7 @@ static void constructorHelper( ic += 2; else if (interp == BPatch_interpAsReturnAddr) ic += 4; - icNode = AstNode::operandNode(AstNode::Constant, (void*) ic ); + icNode = AstNode::operandNode(AstNode::operandType::Constant, (void*) ic ); icNode->setType(inttype); } @@ -1614,9 +1611,9 @@ BPatch_stopThreadExpr::BPatch_stopThreadExpr( Address objStart = obj.codeBase(); Address objEnd = objStart + obj.imageSize(); AstNodePtr objStartNode = AstNode::operandNode( - AstNode::Constant, (void*) objStart); + AstNode::operandType::Constant, (void*) objStart); AstNodePtr objEndNode = AstNode::operandNode( - AstNode::Constant, (void*) objEnd); + AstNode::operandType::Constant, (void*) objEnd); BPatch_type *ulongtype = BPatch::bpatch->stdTypes->findType("unsigned long"); objStartNode->setType(ulongtype); objEndNode->setType(ulongtype); @@ -1651,10 +1648,10 @@ BPatch_shadowExpr::BPatch_shadowExpr // set up funcCall args std::vector ast_args; if (entry) { - ast_args.push_back(AstNode::operandNode(AstNode::Constant, (void *)1)); + ast_args.push_back(AstNode::operandNode(AstNode::operandType::Constant, (void *)1)); } else { - ast_args.push_back(AstNode::operandNode(AstNode::Constant, (void *)0)); + ast_args.push_back(AstNode::operandNode(AstNode::operandType::Constant, (void *)0)); } ast_args.back()->setType(BPatch::bpatch->type_Untyped); diff --git a/dyninstAPI/src/BPatch_sourceBlock.C b/dyninstAPI/src/BPatch_sourceBlock.C index 080212479d..fb1fb4bfb6 100644 --- a/dyninstAPI/src/BPatch_sourceBlock.C +++ b/dyninstAPI/src/BPatch_sourceBlock.C @@ -30,8 +30,8 @@ #define BPATCH_FILE +#include #include -#include "common/src/std_namesp.h" #include "BPatch_sourceBlock.h" #include diff --git a/dyninstAPI/src/BPatch_statement.C b/dyninstAPI/src/BPatch_statement.C index b2997ff03a..1ee8d8d551 100644 --- a/dyninstAPI/src/BPatch_statement.C +++ b/dyninstAPI/src/BPatch_statement.C @@ -30,7 +30,7 @@ #include "BPatch_statement.h" #include "BPatch_module.h" -#include "Module.h" +#include "Statement.h" #include "mapped_object.h" #include "mapped_module.h" BPatch_statement::BPatch_statement(BPatch_module *mod, Dyninst::SymtabAPI::Statement::ConstPtr s) : diff --git a/dyninstAPI/src/BPatch_type.C b/dyninstAPI/src/BPatch_type.C index faf508553c..784abb602f 100644 --- a/dyninstAPI/src/BPatch_type.C +++ b/dyninstAPI/src/BPatch_type.C @@ -28,6 +28,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include #define BPATCH_FILE @@ -41,6 +42,7 @@ #include "BPatch.h" #include "mapped_module.h" #include "RegisterConversion.h" +#include "registers/abstract_regs.h" //#include "Annotatable.h" using namespace Dyninst; @@ -79,7 +81,7 @@ BPatch_type *BPatch_type::createFake(const char *_name) { * */ -BPatch_type::BPatch_type(boost::shared_ptr typ_): ID(typ_->getID()), typ(typ_), +BPatch_type::BPatch_type(dyncompat::shared_ptr typ_): ID(typ_->getID()), typ(typ_), refCount(1) { // if a derived type, make sure the upPtr is set for the base type. @@ -128,7 +130,7 @@ BPatch_type::BPatch_type(const char *_name, int _ID, BPatch_dataClass _type) : type_map[typ.get()] = this; } -BPatch_type *BPatch_type::findOrCreateType(boost::shared_ptr type) +BPatch_type *BPatch_type::findOrCreateType(dyncompat::shared_ptr type) { std::map::iterator elem = type_map.find(type.get()); if (elem != type_map.end()) { @@ -160,12 +162,12 @@ const char *BPatch_type::getName() const return typ->getName().c_str(); } -boost::shared_ptr BPatch_type::getSymtabType(Type::do_share_t) const +dyncompat::shared_ptr BPatch_type::getSymtabType(Type::do_share_t) const { return typ; } -boost::shared_ptr SymtabAPI::convert(const BPatch_type *t, Type::do_share_t) { +dyncompat::shared_ptr SymtabAPI::convert(const BPatch_type *t, Type::do_share_t) { return t->getSymtabType(Type::share); } @@ -181,7 +183,7 @@ bool BPatch_type::isCompatible(BPatch_type *otype) BPatch_type *BPatch_type::getConstituentType() const { - boost::shared_ptr ctype; + dyncompat::shared_ptr ctype; // Pointer, reference, typedef if (typ->isDerivedType()) ctype = typ->asDerivedType().getConstituentType(Type::share); diff --git a/dyninstAPI/src/IAPI_to_AST.C b/dyninstAPI/src/IAPI_to_AST.C index a27909a396..e63d900f09 100644 --- a/dyninstAPI/src/IAPI_to_AST.C +++ b/dyninstAPI/src/IAPI_to_AST.C @@ -29,9 +29,10 @@ */ #include "IAPI_to_AST.h" + +#include "Register.h" #include "BinaryFunction.h" #include "Immediate.h" -#include "Register.h" #include "Dereference.h" #if defined(arch_x86) || defined(arch_x86_64) #include "RegisterConversion.h" @@ -69,19 +70,12 @@ void ASTFactory::visit(Dereference* ) { AstNodePtr effaddr = m_stack.back(); m_stack.pop_back(); - // We need to translate the addr to handle emulation shadow pages - // before we dereference - std::vector args; - args.push_back(effaddr); - args.push_back(AstNode::operandNode(AstNode::Constant, (void *) 0xdeadbeef)); - args.push_back(AstNode::operandNode(AstNode::Constant, (void *) 0xcafebabe)); - AstNodePtr funcCall = AstNode::funcCallNode("RTtranslateMemory", args); - m_stack.push_back(AstNode::operandNode(AstNode::DataIndir, funcCall)); + m_stack.push_back(AstNode::operandNode(AstNode::operandType::DataIndir, effaddr)); } void ASTFactory::visit(Immediate* i) { - m_stack.push_back(AstNode::operandNode(AstNode::Constant, + m_stack.push_back(AstNode::operandNode(AstNode::operandType::Constant, (void*)(i->eval().convert()))); } @@ -89,7 +83,7 @@ void ASTFactory::visit(RegisterAST* r) { #if defined(arch_x86) || defined(arch_x86_64) bool unused; - m_stack.push_back(AstNode::operandNode(AstNode::origRegister, + m_stack.push_back(AstNode::operandNode(AstNode::operandType::origRegister, (void*)(intptr_t)(convertRegID(r, unused)))); #else MachRegister reg = r->getID(); diff --git a/dyninstAPI/src/MemoryEmulator/memEmulator.C b/dyninstAPI/src/MemoryEmulator/memEmulator.C deleted file mode 100644 index 15ddfd9440..0000000000 --- a/dyninstAPI/src/MemoryEmulator/memEmulator.C +++ /dev/null @@ -1,544 +0,0 @@ -/* - * See the dyninst/COPYRIGHT file for copyright information. - * - * We provide the Paradyn Tools (below described as "Paradyn") - * on an AS IS basis, and do not warrant its validity or performance. - * We reserve the right to update, modify, or discontinue this - * software at any time. We shall have no obligation to supply such - * updates or modifications or any other form of support to you. - * - * By your use of Paradyn, you understand and agree that we (or any - * other person or entity with proprietary rights in Paradyn) are - * under no obligation to provide either maintenance services, - * update services, notices of latent defects, or correction of - * defects for Paradyn. - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include "parseAPI/h/CodeObject.h" -#include "dyninstAPI/src/addressSpace.h" -#include "memEmulator.h" -#include "dyninstAPI/src/mapped_object.h" -#include "dyninstAPI/src/image.h" -#include "symtabAPI/h/Symtab.h" -#include "symtabAPI/h/Region.h" -#include "dyninstAPI/src/dynProcess.h" -#include "dyninstAPI/src/function.h" -#include "dyninstAPI/src/debug.h" - -using namespace Dyninst; -using namespace SymtabAPI; - -bool MemoryEmulator::findMutateeTable() { - if (mutateeBase_ != 0) return true; - - std::vector memoryMapperTable; - if (!aS_->findVarsByAll("RTmemoryMapper", memoryMapperTable)) { - return false; - } - - if (memoryMapperTable.size() > 1) { - // ??? - return false; - } - mutateeBase_ = memoryMapperTable[0]->getAddress(); - return true; -} - -void MemoryEmulator::update() { - if (!findMutateeTable()) return; - - // 1) Create shadow copies for any MappedObject we - // have modified. - // 2) Update the runtime's MemoryMapper structure - // to correspond to this. - - // First step: nonblocking synchro. - int guardValue; - aS_->readDataSpace((void *)mutateeBase_, - sizeof(int), - &guardValue, - false); - guardValue++; - aS_->writeDataSpace((void *)mutateeBase_, - sizeof(int), - &guardValue); - - sensitivity_cerr << "UpdateMemEmulator: writing guard value " << guardValue << endl; - // 64->32 bit is annoying... - if (addrWidth() == 4) { - struct MemoryMapper32 newMapper; - - aS_->readDataSpace((void *)mutateeBase_, - sizeof(newMapper), - &newMapper, - false); - - // First step: - newMapper.guard1 = guardValue; - newMapper.guard2 = guardValue; - newMapper.size = memoryMap_.size(); - sensitivity_cerr << "\t new values: " << newMapper.guard1 << "/" << newMapper.guard2 << "/" << newMapper.size << endl; - std::vector elements; - memoryMap_.elements(elements); - for (unsigned i = 0; i < elements.size(); ++i) { - Address base = elements[i].first.first; - - newMapper.elements[i].lo = base; - newMapper.elements[i].hi = elements[i].first.second; - assert(newMapper.elements[i].hi > newMapper.elements[i].lo); - newMapper.elements[i].shift = elements[i].second; - } - aS_->writeDataSpace((void *)mutateeBase_, - sizeof(newMapper), - &newMapper); - - } - else { - // TODO copy - //assert(0); - } -} - -void MemoryEmulator::addAllocatedRegion(Address start, unsigned size) { - addRegion(start, size, -1); -} - -void MemoryEmulator::addRegion(mapped_object *obj) { - if (aS_->runtime_lib.find(obj) != aS_->runtime_lib.end()) - { - // Runtime library, skip - return; - } - // Add each code region - std::vector codeRegions; - obj->parse_img()->getObject()->getCodeRegions(codeRegions); - - for (unsigned i = 0; i < codeRegions.size(); ++i) { - Region *reg = codeRegions[i]; - - addRegion(reg, obj->codeBase(), 0, 0); - } -} - -void MemoryEmulator::removeRegion(mapped_object *obj) { - sensitivity_cerr << "Removing region " << obj->fileName() << endl; - sensitivity_cerr << "\t Before: " << endl; - debug(); - // Remove each code region - std::vector codeRegions; - obj->parse_img()->getObject()->getCodeRegions(codeRegions); - - for (unsigned i = 0; i < codeRegions.size(); ++i) { - Region *reg = codeRegions[i]; - - removeRegion(reg, obj->codeBase()); - } - sensitivity_cerr << "\t After: " << endl; - debug(); -} - -void MemoryEmulator::addRegion(Region *reg, Address base, Address, Address) { - - if (addedRegions_.find(reg) != addedRegions_.end()) return; - - PCProcess *proc = dynamic_cast(aS_); - char *buffer = (char *)malloc(reg->getMemSize()); - if (proc) { - if (!proc->readDataSpace((void*)(base + reg->getMemOffset()), - reg->getMemSize(), buffer, false)) { - assert(0); - } - } else { - memset(buffer, 0, reg->getMemSize()); - memcpy(buffer, reg->getPtrToRawData(), reg->getDiskSize()); - } - - unsigned long allocSize = reg->getMemSize(); - allocSize += 0x1000; - - Address mutateeBase = aS_->inferiorMalloc(allocSize); - assert(mutateeBase); - - // "Upcast" it to align with a page boundary - Kevin's request - if (proc) { - mutateeBase += proc->getMemoryPageSize(); - mutateeBase -= mutateeBase % proc->getMemoryPageSize(); - } - - aS_->writeDataSpace((void *)mutateeBase, - reg->getMemSize(), - (void *)buffer); - if (aS_->proc() && BPatch_defensiveMode == aS_->proc()->getHybridMode()) { - using namespace SymtabAPI; - PCProcess::PCMemPerm memPerm_; - Region::perm_t reg_rights = reg->getRegionPermissions(); - switch (reg_rights) { - case Region::RP_R: - memPerm_.setR(); // PAGE_READONLY; - break; - case Region::RP_RW: - memPerm_.setR().setW(); // PAGE_READWRITE; - break; - case Region::RP_RX: - memPerm_.setR().setX(); // PAGE_EXECUTE_READ; - break; - case Region::RP_RWX: - memPerm_.setR().setW().setX(); // PAGE_EXECUTE_READWRITE; - break; - default: - assert(0); - } - - PCProcess *proc = aS_->proc(); - assert(proc); - proc->stopProcess(); - proc->changeMemoryProtections(mutateeBase, reg->getMemSize(), memPerm_, false); - } - - Address regionBase = base + reg->getMemOffset(); - - addRegion(regionBase, - reg->getMemSize(), - mutateeBase - regionBase); - - - addedRegions_[reg] = std::make_pair(base + reg->getMemOffset(), mutateeBase); - free(buffer); -} - -void MemoryEmulator::removeRegion(Region *reg, Address base) { - - //cerr << "\t\t Region " << i << ": " << hex - //<< codeRegions[i]->getMemOffset() + obj->codeBase() << " -> " - //<< codeRegions[i]->getMemOffset() + codeRegions[i]->getMemSize() + obj->codeBase() << endl; - - RegionMap::iterator iter = addedRegions_.find(reg); - if (iter == addedRegions_.end()) return; - - // First, nuke our track of the springboards - springboards_.erase(reg); - - // Second, nuke it from the list of regions to copy on a sync - addedRegions_.erase(reg); - - // Deallocate the shadow pages in the mutatee - // -- this is TODO; we mangle the allocation base and therefore can't - // really call inferiorfree on it. - - // Remove the region from the translation map - removeRegion(base + reg->getMemOffset(), reg->getMemSize()); -} - -void MemoryEmulator::addRegion(Address start, unsigned size, Address shift) { - if (size == 0) return; - //debug(); - //cerr << endl; - Address end = start + size; - assert(end > start); - - // Okay. For efficiency, we want to merge this if possible with an existing - // range. We do this because our allocation tends to be contiguous. - // Two options: we're immediately above an existing range or we're immediately - // below. Check both. - - - Address lb, ub; - unsigned long val; - if (memoryMap_.find(start, lb, ub, val)) { - // This is possibly very bad. - if (start != ub) { - if ((start == lb) && - (end == ub) && - (val == shift)) { - return; - } - // Yeah, data inconsistency == bad - assert(0); - } - if (val == shift) { - // Accumulate - memoryMap_.remove(lb); - memoryMap_.insert(lb, end, shift); - return; - } - else { - memoryMap_.insert(start, end, shift); - } - } - else if (memoryMap_.find(end, lb, ub, val)) { - // See the above - if (end != ub) { - fprintf(stderr, "ERROR: adding range 0x%lx -> 0x%lx (0x%lx), found range 0x%lx -> 0x%lx (0x%lx)\n", - start, end, shift, lb, ub, val); - - assert(0); - } - if (val == shift) { - memoryMap_.remove(lb); - memoryMap_.insert(start, ub, shift); - } - else { - memoryMap_.insert(start, end, shift); - } - } - else { - memoryMap_.insert(start, end, shift); - } - - if (shift != (unsigned long) -1) { - reverseMemoryMap_.insert(start + shift, end + shift, shift); - } - //debug(); - return; -} - -void MemoryEmulator::removeRegion(Address addr, unsigned size) { - Address lb = 0, ub = 0; - unsigned long shiftVal; - - cerr << "MemoryEmulator: removing region " << hex << addr << " : " << size << dec << endl; - - //debug(); - //cerr << endl; - - Address lowLB = 0, lowUB = 0, hiLB = 0, hiUB = 0; - - // We are guaranteed to be either our own allocated range or - // coalesced with another range. - if (!memoryMap_.find(addr, lb, ub, shiftVal)) { - return; - } - - if ((lb != 0) && (lb < addr)) { - lowLB = lb; - lowUB = addr; - } - if ((ub != 0) && (ub > (addr + size))) { - hiLB = (addr + size); - hiUB = ub; - } - memoryMap_.remove(lb); - if (lowLB || lowUB) { - memoryMap_.insert(lowLB, lowUB, shiftVal); - } - if (hiLB || hiUB) { - memoryMap_.insert(hiLB, hiUB, shiftVal); - } - - reverseMemoryMap_.remove(addr + shiftVal); - //debug(); -} - -unsigned MemoryEmulator::addrWidth() { - return aS_->getAddressWidth(); -} - -std::pair MemoryEmulator::translate(Address orig) { - // Mimic the translation performed in the RT library - Address lb, ub; - unsigned long val; - if (!memoryMap_.find(orig, lb, ub, val)) { - return std::make_pair(false, 0); - } - if (val == (unsigned long) -1) { - return std::make_pair(true, orig); - } - return std::make_pair(true, orig + val); -} - -std::pair MemoryEmulator::translateBackwards(Address addr) { - // Mimic the translation performed in the RT library - Address lb, ub; - unsigned long val; - if (!reverseMemoryMap_.find(addr, lb, ub, val)) { - return std::make_pair(false, 0); - } - if (val == (unsigned long) -1) { - return std::make_pair(true, addr); - } - return std::make_pair(true, addr - val); -} - -void MemoryEmulator::synchShadowOrig(bool toOrig) -{ - - if (toOrig) { - malware_cerr << "Syncing shadow to orig" << endl; - } - else { - malware_cerr << "Syncing orig to shadow" << endl; - } - - using namespace SymtabAPI; - - for (RegionMap::iterator iter = addedRegions_.begin(); - iter != addedRegions_.end(); ++iter) { - Region * reg = iter->first; - - // We copy "source" (where we're copying from) and "target" (where we're - // copying to). We then select snippets of target (where springboards reside) - // and copy them into source, and then write source into target. - - unsigned char *source = (unsigned char*) malloc(reg->getMemSize()); - unsigned char *target = (unsigned char *) malloc(reg->getMemSize()); - - Address from = 0; - Address to = 0; - if (toOrig) { - from = iter->second.second; - to = iter->second.first; - } else { - from = iter->second.first; - to = iter->second.second; - } - - if (!aS_->readDataSpace((void *)from, - reg->getMemSize(), - source, - false)) - { - assert(0); - } - if (!aS_->readDataSpace((void *)to, - reg->getMemSize(), - target, - false)) - { - assert(0); - } - - std::map::const_iterator sit = springboards_[reg].begin(); - for (; sit != springboards_[reg].end(); sit++) { - - Address fromLB = (Address) target + sit->first; - Address toLB = (Address) source + sit->first; - memcpy((void *)toLB, (void *)fromLB, sit->second); - } - - if (!aS_->writeDataSpace((void *)to, - reg->getMemSize(), - source)) - { - assert(0); - } - free(source); - free(target); - - } - -} - - -void MemoryEmulator::addSpringboard(Region *reg, Address offset, int size) -{ - // Look up whether there is a previous springboard that overlaps with us; - // clearly, it's getting removed. - - std::map >::iterator s_iter = springboards_.find(reg); - if (s_iter == springboards_.end()) { - springboards_[reg][offset] = size; - return; - } - std::map &smap = s_iter->second; - - springboard_cerr << "Inserting SB [" << hex << offset << "," << offset + size << "]" << dec << endl; - - std::map::iterator iter = smap.find(offset); - if (iter == smap.end()) { - smap[offset] = size; - } - else if (size > iter->second) { - smap[offset] = size; - } - // Otherwise keep the current value - springboard_cerr << "\t New value: " << hex << offset << " -> " << smap[offset] + offset << dec << endl; -} - -void MemoryEmulator::removeSpringboards(func_instance * func) -{ - malware_cerr << "untracking springboards from deadfunc " << hex << func->addr() << dec << endl; - - const PatchFunction::Blockset & blocks = func->blocks(); - PatchFunction::Blockset::const_iterator bit = blocks.begin(); - for (; bit != blocks.end(); bit++) { - removeSpringboards(SCAST_BI(*bit)); - } -} - -void MemoryEmulator::removeSpringboards(const block_instance *bbi) -{ - malware_cerr << " untracking springboards from deadblock [" << hex - << bbi->start() << " " << bbi->end() << ")" << dec <llb()->region())->symRegion(); - springboards_[reg].erase(bbi->llb()->start() - reg->getMemOffset()); - if (springboards_[reg].empty()) springboards_.erase(reg); -} - -void MemoryEmulator::debug() const { - if (!dyn_debug_sensitivity) { - return; - } - std::vector elements; - memoryMap_.elements(elements); - cerr << "\t Forward map: " << endl; - for (std::vector::iterator iter = elements.begin(); iter != elements.end(); ++iter) - { - cerr << "\t\t " << hex << "[" << iter->first.first << "," << iter->first.second << "]: " << iter->second << dec << endl; -#if 0 // debug output - if (iter->first.first == 0x40d000) { - Address val; - Address addr = (iter->second + 0x40d84b); - assert(sizeof(Address) == aS_->getAddressWidth()); - Address width = aS_->getAddressWidth(); - for (Address idx=0; idx < 0x40; idx+=width) { - aS_->readDataSpace((void*)(addr+idx), width, &val, true); - cerr << hex << " " << 0x40d84b + idx << "[" << addr+idx << "]: "; - fprintf(stderr,"%2x",((unsigned char*)&val)[3]); - fprintf(stderr,"%2x",((unsigned char*)&val)[2]); - fprintf(stderr,"%2x",((unsigned char*)&val)[1]); - fprintf(stderr,"%2x\n",((unsigned char*)&val)[0]); - } - } -#endif - } - elements.clear(); - cerr << "\t Backwards map: " << endl; - reverseMemoryMap_.elements(elements); - for (std::vector::iterator iter = elements.begin(); iter != elements.end(); ++iter) - { - cerr << "\t\t " << hex << "[" << iter->first.first << "," << iter->first.second << "]: " << iter->second << dec << endl; - } - elements.clear(); - -} - -void MemoryEmulator::addPOPAD(Address addr) -{ - emulatedPOPADs_.insert(addr); -} - -bool MemoryEmulator::isEmulPOPAD(Address addr) -{ - Address orig = -1; - std::vector dontcare1; - baseTramp *dontcare2; - if (!aS_->getAddrInfo(addr, orig, dontcare1, dontcare2)) { - assert(0); - } - return emulatedPOPADs_.end() != emulatedPOPADs_.find(orig); -} diff --git a/dyninstAPI/src/MemoryEmulator/memEmulator.h b/dyninstAPI/src/MemoryEmulator/memEmulator.h deleted file mode 100644 index 422c9162ff..0000000000 --- a/dyninstAPI/src/MemoryEmulator/memEmulator.h +++ /dev/null @@ -1,116 +0,0 @@ -/* - * See the dyninst/COPYRIGHT file for copyright information. - * - * We provide the Paradyn Tools (below described as "Paradyn") - * on an AS IS basis, and do not warrant its validity or performance. - * We reserve the right to update, modify, or discontinue this - * software at any time. We shall have no obligation to supply such - * updates or modifications or any other form of support to you. - * - * By your use of Paradyn, you understand and agree that we (or any - * other person or entity with proprietary rights in Paradyn) are - * under no obligation to provide either maintenance services, - * update services, notices of latent defects, or correction of - * defects for Paradyn. - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#if !defined(cap_mem_emulation) -#include "memEmulatorStub.h" -#else - - - -#if !defined(_MEMORY_EMULATOR_H_) -#define _MEMORY_EMULATOR_H_ - -#include "common/src/IntervalTree.h" -#include "dyninstAPI/src/MemoryEmulator/memEmulatorTransformer.h" -#include "dyninstAPI/src/MemoryEmulator/memEmulatorWidget.h" - -class AddressSpace; -class mapped_object; -class int_variable; - -namespace Dyninst { - namespace SymtabAPI { - class Region; - }; - -class MemoryEmulator { - public: - MemoryEmulator(AddressSpace *addrSpace) - : aS_(addrSpace), mutateeBase_(0) {}; - ~MemoryEmulator() {}; - - void addAllocatedRegion(Address start, unsigned size); - void addRegion(mapped_object *obj); - void addRegion(SymtabAPI::Region *reg, Address base, Address bufferStart, Address bufferEnd); - void update(); - - void removeRegion(mapped_object *obj); - void removeRegion(SymtabAPI::Region *reg, Address base); - void removeRegion(Address start, unsigned size); - - void reprocess(mapped_object *obj); - - std::pair translate(Address addr); - std::pair translateBackwards(Address addr); - - const std::map & getSpringboards(SymtabAPI::Region*) const; - void removeSpringboards(func_instance* deadfunc); - void removeSpringboards(const block_instance* deadBBI); - void addSpringboard(SymtabAPI::Region*, - Address offset,/*from start of region*/ - int size); - void synchShadowOrig(bool toOrig); - - void addPOPAD(Address addr); - bool isEmulPOPAD(Address addr); - - static const int STACK_SHIFT_VAL=256; - - void debug() const; - - private: - void addRegion(Address start, unsigned size, Address newBase); - - - bool findMutateeTable(); - unsigned addrWidth(); - - AddressSpace *aS_; - - // Track what the address space looks like for defensive mode. - typedef IntervalTree MemoryMapTree; - MemoryMapTree memoryMap_; - MemoryMapTree reverseMemoryMap_; - - Address mutateeBase_; - - std::map > springboards_; - - // First address: original base in memory. Second address: shadow base. - typedef std::map > RegionMap; - RegionMap addedRegions_; - - std::map saved; - std::set
emulatedPOPADs_; -}; -}; - -#endif -#endif diff --git a/dyninstAPI/src/MemoryEmulator/memEmulatorTransformer.C b/dyninstAPI/src/MemoryEmulator/memEmulatorTransformer.C deleted file mode 100644 index ef056dcdbc..0000000000 --- a/dyninstAPI/src/MemoryEmulator/memEmulatorTransformer.C +++ /dev/null @@ -1,214 +0,0 @@ -/* - * See the dyninst/COPYRIGHT file for copyright information. - * - * We provide the Paradyn Tools (below described as "Paradyn") - * on an AS IS basis, and do not warrant its validity or performance. - * We reserve the right to update, modify, or discontinue this - * software at any time. We shall have no obligation to supply such - * updates or modifications or any other form of support to you. - * - * By your use of Paradyn, you understand and agree that we (or any - * other person or entity with proprietary rights in Paradyn) are - * under no obligation to provide either maintenance services, - * update services, notices of latent defects, or correction of - * defects for Paradyn. - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - */ - - - -#include "dyninstAPI/src/Relocation/Transformers/Transformer.h" -#include "memEmulatorTransformer.h" -#include "dyninstAPI/src/debug.h" -#include "dyninstAPI/src/Relocation/Widgets/Widget.h" -#include "dyninstAPI/src/Relocation/Widgets/InsnWidget.h" -#include "memEmulatorWidget.h" -#include "dyninstAPI/src/instPoint.h" // Memory insn modelling requirement. -#include "dyninstAPI/src/mapped_object.h" -#include "dyninstAPI/h/BPatch_enums.h" -#include -#include "dyninstAPI/src/Relocation/CFG/RelocBlock.h" - -using namespace std; -using namespace Dyninst; -using namespace Relocation; -using namespace InstructionAPI; - - -// Replace all memory accesses to a non-statically-determinable -// location with an emulation sequence -bool MemEmulatorTransformer::process(RelocBlock *rblock, RelocGraph *rgraph) -{ - if (!(rblock->block())) return true; - - // AssignmentConverter is written in terms of parse_func, - // so translate - func_instance *func = rblock->func(); - - WidgetList &elements = rblock->elements(); - - for (WidgetList::iterator e_iter = elements.begin(); - e_iter != elements.end(); ++e_iter) { - // If we're not an instruction then skip... - InsnWidget::Ptr reloc = boost::dynamic_pointer_cast(*e_iter); - if (!reloc) continue; - - relocation_cerr << "Memory emulation considering addr " << hex << reloc->addr() << dec << endl; - - if (BPatch_defensiveMode != func->obj()->hybridMode() || !isSensitive(reloc, func, rblock->block())) { - relocation_cerr << "\t Not sensitive, skipping" << endl; - continue; - } - - if (!canRewriteMemInsn(reloc, func)) { - malware_cerr << "\tUnable to rewrite memory access at "<< hex << reloc->addr() <<": " << reloc->format() << dec << endl; - continue; - } - - Widget::Ptr replacement = createReplacement(reloc, func, rblock->block()); - if (!replacement) return false; - - (*e_iter).swap(replacement); - } - return true; -} - -bool MemEmulatorTransformer::canRewriteMemInsn(InsnWidget::Ptr reloc, - func_instance *func) { - // Let's see if this is an instruction we can rewrite; - // otherwise complain but let it through (for testing purposes) - if (override(reloc)) - return true; - - codeGen tmpGen(1024); - tmpGen.setAddrSpace(func->proc()); // needed by insn::generateMem - - instruction ugly_insn(reloc->insn()->ptr()); - if (!insnCodeGen::generateMem(tmpGen, - ugly_insn, - 0, - 0, - 0, - Null_Register)) { - return false; - } - return true; -} - -bool MemEmulatorTransformer::override(InsnWidget::Ptr reloc) { - unsigned char *buf = (unsigned char *)reloc->insn()->ptr(); - if ((unsigned char) 0xa0 <= buf[0] && - buf[0] <= (unsigned char) 0xa3) { - // Read/write with addr specified in an operand - return true; - } - const InstructionAPI::Instruction::Ptr &insn = reloc->insn(); - - const InstructionAPI::Operation &op = insn->getOperation(); - - switch(op.getID()) { - case e_scasb: - case e_scasd: - case e_scasw: - case e_lodsb: - case e_lodsd: - case e_lodsw: - case e_movsb: - case e_movsd: - case e_movsw: - case e_stosb: - case e_stosd: - case e_stosw: - case e_cmpsb: - case e_cmpsd: - case e_cmpsw: - case e_insb: - case e_insd: - case e_insw: - case e_outsb: - case e_outsd: - case e_outsw: - case e_popad: - return true; - default: - break; - } - return false; -} - -Widget::Ptr MemEmulatorTransformer::createReplacement(InsnWidget::Ptr reloc, - func_instance *func, - block_instance *block) { - // MemEmulators want instPoints. How unreasonable. - instPoint *point = instPoint::preInsn(func, block, reloc->addr(), reloc->insn(), true); - if (!point) return Widget::Ptr(); - - // Replace this instruction with a MemEmulator - Widget::Ptr memE = MemEmulator::create(reloc->insn(), - reloc->addr(), - point); - - return memE; -} - -bool MemEmulatorTransformer::isSensitive(InsnWidget::Ptr reloc, - func_instance *func, - block_instance *block) { - - parse_func *ifunc = func->ifunc(); - Address image_addr = func->addrToOffset(reloc->addr()); - - std::vector assignments; - aConverter.convert(reloc->insn(), - image_addr, - ifunc, - block->llb(), - assignments); - - for (std::vector::const_iterator a_iter = assignments.begin(); - a_iter != assignments.end(); ++a_iter) { - - const std::vector &ins = (*a_iter)->inputs(); - for (std::vector::const_iterator i = ins.begin(); - i != ins.end(); ++i) { - //relocation_cerr << "\t\t Input: " << i->format() << endl; - if (i->contains(Absloc::Heap)) { - return true; - } - if (i->absloc().type() == Absloc::Heap) { - return true; - } - } - // Writes too - //relocation_cerr << "\t\t Output: " << (*a_iter)->out().format() << endl; - if ((*a_iter)->out().contains(Absloc::Heap)) { - return true; - } - if ((*a_iter)->out().absloc().type() == Absloc::Heap) { - return true; - } - } - - return false; -} - -#if 0 -void MemEmulatorTransformer::createTranslator(Register r) { - Widget::Ptr translator = MemEmulatorTranslator::create(r); - RelocBlock::Ptr newRelocBlock = RelocBlock::create(translator); - translators_[r] = newRelocBlock; -}; -#endif diff --git a/dyninstAPI/src/MemoryEmulator/memEmulatorWidget.C b/dyninstAPI/src/MemoryEmulator/memEmulatorWidget.C deleted file mode 100644 index ab0173a561..0000000000 --- a/dyninstAPI/src/MemoryEmulator/memEmulatorWidget.C +++ /dev/null @@ -1,800 +0,0 @@ -/* - * See the dyninst/COPYRIGHT file for copyright information. - * - * We provide the Paradyn Tools (below described as "Paradyn") - * on an AS IS basis, and do not warrant its validity or performance. - * We reserve the right to update, modify, or discontinue this - * software at any time. We shall have no obligation to supply such - * updates or modifications or any other form of support to you. - * - * By your use of Paradyn, you understand and agree that we (or any - * other person or entity with proprietary rights in Paradyn) are - * under no obligation to provide either maintenance services, - * update services, notices of latent defects, or correction of - * defects for Paradyn. - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - */ - - -#include "dyninstAPI/src/Relocation/Widgets/Widget.h" -#include "dyninstAPI/src/Relocation/CFG/RelocTarget.h" -#include "dyninstAPI/src/Relocation/Widgets/CFWidget.h" // CFPatch - -// For our horribly horked memory effective address system -// Which I'm not fixing here. -#include "dyninstAPI/h/BPatch_memoryAccess_NP.h" -#include "dyninstAPI/h/BPatch_addressSpace.h" // bpatch_address... you get the picture -#include "dyninstAPI/h/BPatch_point.h" -// Memory hackitude -#include "dyninstAPI/src/emit-x86.h" -#include "dyninstAPI/src/inst-x86.h" - -#include "instructionAPI/h/Instruction.h" -#include "dyninstAPI/src/addressSpace.h" -#include "dyninstAPI/src/debug.h" -#include "dyninstAPI/src/registerSpace.h" -#include "dyninstAPI/src/mapped_object.h" -#include "dyninstAPI/src/Relocation/CodeBuffer.h" -#include "common/src/arch-x86.h" - -#include "memEmulatorWidget.h" - -#include "dyninstAPI/src/RegisterConversion.h" - -#include "boost/tuple/tuple.hpp" -#include "memEmulator.h" - - -using namespace Dyninst; -using namespace Relocation; -using namespace InstructionAPI; - - -MemEmulator::Ptr MemEmulator::create(Instruction::Ptr insn, - Address addr, - instPoint *point) { - MemEmulator::Ptr ptr = MemEmulator::Ptr(new MemEmulator(insn, addr, point)); - return ptr; -} - -const int ESI_SHIFT_REG = REGNUM_EBP; -const int EDI_SHIFT_REG = REGNUM_EBX; - -bool MemEmulator::initialize(const codeGen &templ, const RelocBlock *t) { - // Number chosen arbitrarily - scratch.allocate(128); - scratch.applyTemplate(templ); - - block = t->block(); - - effAddr = Null_Register; - stackOffset = 0; - effAddrSaveOffset = 0; - usesESI = false; - usesEDI = false; - debug = false; - - return true; -} - -/* Block comment ho! - * - * - * We're trying to "emulate" the memory operation. That is, we want to redirect it - * to (or from) a shadow of original memory. In general, this is simple, using the following - * code fragment: - * - * -- EAX if it isn't read by the instruction; else ECX; else EDX. - * -- so we don't stomp on any data the program stores under the stack. - * -- eax, ecx, edx; we save all three since we don't trust liveness. - * -- see the above comment - * -- LEA so we don't harm registers - * -- EAX, and debugging arguments - * -- leaves new pointer in EAX - * - * - * - * - * - * -- via a mov instruction - * - * Now, that's the overview. But this is x86, and things get tricky. We handle the following special cases: - * 1) Push/pop - * 2) Write to (ESP) - * 3) a1-a3 implicit use of EAX - * 4) scas/ins/outs/cmps/stos/movs/lods implicit use of ESI/EDI - * - * 1) Push/pop. I believe we can structure the common code to leave ESP untouched at the memory operation time, - * which means this case is trivially solved. However, we need to be sure to restore effAddr from the right place. - * 2) Write to (ESP). See case 1) - * 3) a1-a3 implicit use of EAX. These are of the form mov eax, [mem] or mov [mem], eax; thus, we _skip_ all of - * the above complexity and just statically translate [mem]. - * 4) Implicit use of ESI/EDI (either or both). First, we need to keep two effective address registers, and we - * need to call translate twice (possibly). Second, these operations modify ESI/EDI, and we want to emulate - * that modification as well. So we do the following: - * 1) shiftESI := translate_shift(ESI) - return is the amount that esi needs to be _shifted_ to be translated. - * 2) shiftEDI := translate_shift(EDI) - * 3) ESI += shiftESI - * 4) EDI += shiftEDI - * 5) Emulate instruction - * 6) ESI -= shiftESI (note: we can't use an LEA for this, thus we sub and have to save flags) - * 7) EDI -= shiftEDI (see above) - */ - -bool MemEmulator::generate(const codeGen &templ, - const RelocBlock *t, - CodeBuffer &buffer) -{ - if (!initialize(templ, t)) return false; - - if (generateViaOverride(buffer)) - return true; - if (generateViaModRM(buffer)) - return true; - - cerr << "Error: failed to emulate memory operation @ " << hex << addr() << dec << ", " << insn()->format() << endl; - unsigned char *tmp = (unsigned char *)insn()->ptr(); - cerr << hex << "\t raw: "; - for (unsigned i = 0; i < insn()->size(); ++i) { - cerr << tmp[i]; - } - cerr << dec << endl; - assert(0); - return false; -} - -bool MemEmulator::generateViaOverride(CodeBuffer &buffer) -{ - // Watch for a0/a1/a2/a3 moves - unsigned char *buf = (unsigned char *)insn_->ptr(); - if ((unsigned char) 0xa0 <= buf[0] && - buf[0] <= (unsigned char) 0xa3) { - if (!generateEAXMove(buf[0], buffer)) - assert(0); - return true; - } - - const InstructionAPI::Operation &op = insn_->getOperation(); - switch(op.getID()) { - case e_scasb: - case e_scasd: - case e_scasw: - case e_lodsb: - case e_lodsd: - case e_lodsw: - case e_stosb: - case e_stosd: - case e_stosw: - case e_movsb: - case e_movsd: - case e_movsw: - case e_cmpsb: - case e_cmpsd: - case e_cmpsw: - case e_insb: - case e_insd: - case e_insw: - case e_outsb: - case e_outsd: - case e_outsw: - if (!generateESI_EDI(buffer)) { - assert(0); - } - return true; - break; - case e_popad: - if (!generatePOPAD(buffer)) { - assert(0); - } - return true; - break; - default: - break; - } - return false; -} - -bool MemEmulator::generateEAXMove(unsigned char opcode, - CodeBuffer &buffer) -{ - // mov [offset], eax - // We hates them. - - Address origTarget; - switch(opcode) { - case 0xa0: - case 0xa1: { - // read from memory - std::set reads; - insn_->getMemoryReadOperands(reads); - assert(reads.size() == 1); - Result res = (*(reads.begin()))->eval(); - assert(res.defined); - origTarget = res.convert
(); - break; - } - case 0xa2: - case 0xa3: { - // write - std::set writes; - insn_->getMemoryWriteOperands(writes); - assert(writes.size() == 1); - Result res = (*(writes.begin()))->eval(); - assert(res.defined); - origTarget = res.convert
(); - break; - } - default: - assert(0); - break; - } - // Map it to the new location - bool valid; Address target; - boost::tie(valid, target) = scratch.addrSpace()->getMemEm()->translate(origTarget); - if (!valid) target = origTarget; - //cerr << "Handling mov EAX, [offset]: opcode " << hex << opcode << ", orig dest " << origTarget << " and translated " << target << dec << endl; - // And emit the insn - assert(insn_->size() == 5); - GET_PTR(buf, scratch); - *buf = (char) opcode; buf++; - int *tmp = (int *)buf; - *tmp = target; tmp++; - buf = (codeBuf_t *)tmp; - SET_PTR(buf, scratch); - buffer.addPIC(scratch, tracker()); - return true; -} - -bool MemEmulator::generateViaModRM(CodeBuffer &buffer) { - // We need a BPatch_something to do the memory handling. If that's - // not present, assume we don't need to emulate this piece of - // memory. - if (!scratch.addrSpace()->up_ptr()) { - buffer.addPIC(insn_->ptr(), insn_->size(), tracker()); - assert(0); - return true; - } - - insertDebugMarker(); - - // Choose a register to hold the effective address - if (!generateModRMInitialize()) return false; - insertDebugMarker(); - // Shift the stack, save registers, calculate original effective address - if (!generateTranslatorSetup()) return false; - copyScratchToCodeBuffer(buffer); - - // Make the call to the translation function - if (!generateTranslatorCall(buffer)) return false; - // Teardown the call saves - insertDebugMarker(); - if (!generateTranslatorTeardown()) return false; - insertDebugMarker(); - - copyScratchToCodeBuffer(buffer); - - return true; -} - -void MemEmulator::insertDebugMarker() { - if (debug || (dyn_debug_trap /*&& addr() > 0xab000 && addr() <0xad000*/)) - scratch.fill(1, codeGen::cgTrap); -} - -bool MemEmulator::generateModRMInitialize() { - // Placeholder for good code design... - - return true; -} - -bool MemEmulator::generateTranslatorSetup() { - // Our job: - // Shift the stack down - // Decide who will hold the effective address - // Save caller-save registers - // Calculate the original effective address - // Save flags - - if (!shiftStack()) return false; - if (!determineEffAddr()) return false; - if (!saveRegisters()) return false; - if (!calculateEffAddr()) return false; - if (!saveFlags()) return false; - - return true; -} - -bool MemEmulator::generateTranslatorCall(CodeBuffer &buffer) { - - // This is easy. We don't know where we are, - // so we have to use the patch mechanic, but that's - // not too bad. - // We also set up the arguments in the patch code so that we - // have access to the current address (for debugging purposes) - - Address target = getTranslatorAddr(false); - if (!target) return false; - buffer.addPatch(new MemEmulatorPatch(effAddr, effAddr, addr_, target), tracker()); - return true; -} - -bool MemEmulator::generateTranslatorTeardown() { - // Restore flags - // Restore registers (except effAddr) - // Shift stack back up - // Emulate memory operation - // Restore effAddr - insertDebugMarker(); - if (!restoreFlags()) return false; - insertDebugMarker(); - if (!restoreRegisters()) return false; - insertDebugMarker(); - if (!restoreStack()) return false; - insertDebugMarker(); - if (!emulateOriginalInstruction()) return false; - if (!restoreEffectiveAddr()) return false; - - return true; -} - -bool MemEmulator::shiftStack() { - ::emitLEA(RealRegister(REGNUM_ESP), RealRegister(Null_Register), 0, -1*MemoryEmulator::STACK_SHIFT_VAL, RealRegister(REGNUM_ESP), scratch); - stackOffset -= MemoryEmulator::STACK_SHIFT_VAL; - return true; -} - -bool MemEmulator::determineEffAddr() { - // We want to use whichever register isn't used by the instruction. - // Technically, _written_ by the instruction. As that would be silly. - - // Theory: we can always use either ECX or EDX, as they're getting saved - // anyway. - - // We can use a register if it's only used for a memory operand. We cannot use - // it if it's directly used, either mov [ptr], reg or mov reg, [ptr]. - // Technically, we could do mov reg, [ptr] so long as we don't restore reg. - // I'm not too worried, though. - - static RegisterAST::Ptr ecx = RegisterAST::Ptr(new RegisterAST(x86::ecx)); - static RegisterAST::Ptr edx = RegisterAST::Ptr(new RegisterAST(x86::edx)); - - bool useECX = true; - bool useEDX = true; - std::vector operands; - insn_->getOperands(operands); - for (unsigned i = 0; i < operands.size(); ++i) { - if (operands[i].readsMemory()) continue; - if (operands[i].writesMemory()) continue; - if (operands[i].isRead(ecx) || operands[i].isWritten(ecx)) useECX = false; - if (operands[i].isRead(edx) || operands[i].isWritten(edx)) useEDX = false; - } - - if (useECX) { - effAddr = REGNUM_ECX; - } - if (useEDX) { - effAddr = REGNUM_EDX; - } - - block->obj()->addEmulInsn(addr(),effAddr); - - return (useECX || useEDX); -} - -bool MemEmulator::saveRegisters() { - // Theoretically we could use liveness to determine - // whether to save a register or not. - // We want to save the effAddr register _first_ to make - // our lives easier. - if (effAddr == REGNUM_ECX) { - push(REGNUM_ECX); - effAddrSaveOffset = stackOffset; - push(REGNUM_EDX); - } - else { - push(REGNUM_EDX); - effAddrSaveOffset = stackOffset; - push(REGNUM_ECX); - } - push(REGNUM_EAX); - - return true; -} - - -bool MemEmulator::calculateEffAddr() { - // Luckily, we have code to do this already. - assert(scratch.addrSpace()); - BPatch_addressSpace *bproc = (BPatch_addressSpace *)scratch.addrSpace()->up_ptr(); - assert(bproc); - - assert(point_); - BPatch_point *bpoint = bproc->findOrCreateBPPoint(NULL, point_, BPatch_locInstruction); - if (bpoint == NULL) { - fprintf(stderr, "ERROR: Unable to find BPatch point for internal point %p/0x%lx\n", - point_, addr_); - return false; - } - const BPatch_memoryAccess *ma = bpoint->getMemoryAccess(); - - const BPatch_addrSpec_NP *start = ma->getStartAddr(0); // Guessing on 0, here... - - // Now that we've done all the background work, we can emit an LEA to grab the - // effective address. - // The stackOffset parameter is a magic "if you used ESP, be sure to take into - // account the fact we movled it". - emitASload(start, effAddr, stackOffset, scratch, true); - - return true; -} - -bool MemEmulator::saveFlags() { - // nice thing is, eax is already saved at this point. So our live, it be easy. - emitSimpleInsn(0x9f, scratch); - emitSaveO(scratch); - - push(REGNUM_EAX); - return true; -} - -bool MemEmulator::restoreFlags() { - pop(REGNUM_EAX); - - emitRestoreO(scratch); - emitSimpleInsn(0x9E, scratch); - - return true; -} - -bool MemEmulator::restoreRegisters() { - // Order needs to match that in saveRegisters - // Also, don't restore over effAddr. Yet. - pop(REGNUM_EAX); - if (effAddr == REGNUM_ECX) - pop(REGNUM_EDX); - else - pop(REGNUM_ECX); - return true; -} - -bool MemEmulator::restoreStack() { - // We track stack depth in the stackOffset - // parameter... - ::emitLEA(RealRegister(REGNUM_ESP), RealRegister(Null_Register), 0, -1*stackOffset, RealRegister(REGNUM_ESP), scratch); - stackOffset = 0; - return true; -} - -using namespace NS_x86; - -bool MemEmulator::emulateOriginalInstruction() { - NS_x86::instruction ugly_insn(insn_->ptr()); - - if (!insnCodeGen::generateMem(scratch, - ugly_insn, - 0, // ignored - 0, // ignored - effAddr, - Null_Register)) - return false; - - // Do we mess with the stack pointer? - if (insn_->getOperation().getID() == e_push) { - stackOffset -= 4; - } - if (insn_->getOperation().getID() == e_pop) { - stackOffset += 4; - } - - return true; -} - -bool MemEmulator::restoreEffectiveAddr() { - // We want to pull it out of wherever it is on the stack - // We could LEA esp down, pop, and back up. But really. - // Instead, use a mov. - int restoreOffset = (effAddrSaveOffset - stackOffset); - - ::emitMovRMToReg(RealRegister(effAddr), RealRegister(REGNUM_ESP), restoreOffset, scratch); - return true; -} - -bool MemEmulator::copyScratchToCodeBuffer(CodeBuffer &buffer) { - // Copy it in and re-initialize the scratch buffer to hold more - // goodies. - if (scratch.used() == 0) return true; - - buffer.addPIC(scratch, tracker()); - - scratch.allocate(128); - return true; -} - -TrackerElement *MemEmulator::tracker() const { - EmulatorTracker *e = new EmulatorTracker(addr_, block, point_->func()); - return e; -} - -bool MemEmulator::push(Register reg) { - ::emitPush(RealRegister(reg), scratch); - stackOffset -= 4; - return true; -} - -bool MemEmulator::pop(Register reg) { - ::emitPop(RealRegister(reg), scratch); - stackOffset += 4; - return true; -} - -// wrap whole thing in check that esp is outside of the stack segment? -bool MemEmulator::generatePOPAD(CodeBuffer &buffer) { - point_->func()->proc()->getMemEm()->addPOPAD(addr()); - scratch.fill(1, codeGen::cgTrap); - buffer.addPIC(scratch, tracker()); - return true; -} - -/* Block quote redux! - * - * We need to: - * 1) Determine if we use ESI, EDI, or both; - * 2) Shift the stack - * 3) Retain a register (ECX) for the "shift" involved in translating ESI - * (that is, tESI = ESI + ECX) - * 4) Do the same for EDI/EDX - * 5) Save caller-saved registers - * 6) Save the flags - * 7) If using ESI, ECX := shift(ESI) - * 8) If using ESI, ESI += ECX - * 9) If using EDI, EDX := shift(EDI) - * 10) If using EDI, EDI += EDX - * 11) Restore flags and EAX. The "EAX" is very important. - * 12) Run the instruction - * 13) Save EAX and flags (again) - * 14) If using ESI, ESI -= ECX - * 15) If using EDI, EDI -= EDX - * 16) Restore EAX and flags - * 17) Restore the stack. - */ - -bool MemEmulator::generateESI_EDI(CodeBuffer &buffer) { - if (!determineESI_EDIUse()) return false; - - insertDebugMarker(); - - if (!shiftStack()) return false; - - if (!saveRegistersESI_EDI()) return false; - - if (!saveFlags()) return false; - - copyScratchToCodeBuffer(buffer); - - if (usesESI && !generateESIShift(buffer)) return false; - if (usesEDI && !generateEDIShift(buffer)) return false; - - if (!saveShiftsAndRestoreRegs()) return false; - - insertDebugMarker(); - if (!emulateOriginalESI_EDI()) return false; - if (!emulateESI_EDIValues()) return false; - if (!restoreAllRegistersESI_EDI()) return false; - if (!restoreStack()) return false; - assert(stackOffset == 0); - insertDebugMarker(); - - copyScratchToCodeBuffer(buffer); - - return true; -} - - -bool MemEmulator::determineESI_EDIUse() { - const InstructionAPI::Operation &op = insn_->getOperation(); - - switch(op.getID()) { - case e_insb: - case e_insd: - case e_insw: - usesEDI = true; - break; - case e_movsb: - case e_movsd: - case e_movsw: - usesESI = true; - usesEDI = true; - break; - case e_outsb: - case e_outsd: - case e_outsw: - usesESI = true; - break; - case e_lodsb: - case e_lodsd: - case e_lodsw: - usesESI = true; - break; - case e_stosb: - case e_stosd: - case e_stosw: - usesEDI = true; - break; - case e_cmpsb: - case e_cmpsw: - case e_cmpsd: - usesESI = true; - usesEDI = true; - break; - case e_scasb: - case e_scasd: - case e_scasw: - usesEDI = true; - break; - default: - assert(0); - break; - } - return true; -} - -bool MemEmulator::saveRegistersESI_EDI() { - // Always save EAX, but save it last - // so that it's easy to access. - - // We use EBX/EBP to hold shift values so that we can restore EA/C/DX pre-instruction - - push(REGNUM_EBX); - push(REGNUM_EBP); - - push(REGNUM_EDX); - push(REGNUM_ECX); - push(REGNUM_EAX); - return true; -} - -bool MemEmulator::generateESIShift(CodeBuffer &buffer) { - Address destination = getTranslatorAddr(true); - if (!destination) return false; - buffer.addPatch(new MemEmulatorPatch(REGNUM_ESI, ESI_SHIFT_REG, addr_, destination), tracker()); - - // Also, set up ESI to have the right value - ::emitLEA(RealRegister(REGNUM_ESI), RealRegister(ESI_SHIFT_REG), 0, 0, RealRegister(REGNUM_ESI), scratch); - copyScratchToCodeBuffer(buffer); - - return true; -} - -bool MemEmulator::generateEDIShift(CodeBuffer &buffer) { - Address destination = getTranslatorAddr(true); - if (!destination) return false; - buffer.addPatch(new MemEmulatorPatch(REGNUM_EDI, EDI_SHIFT_REG, addr_, destination), tracker()); - - ::emitLEA(RealRegister(REGNUM_EDI), RealRegister(EDI_SHIFT_REG), 0, 0, RealRegister(REGNUM_EDI), scratch); - - copyScratchToCodeBuffer(buffer); - - return true; -} - -bool MemEmulator::saveShiftsAndRestoreRegs() { - // Several instructions implicitly use EAX, and the REP prefix can use ECX. - - // Currently the stack looks like this: - // - // EBX - // EBP - // EDX - // ECX - // EAX - // Flags - - // We want it to look like this: - // - // EBX - // EBP - - if (!restoreFlags()) return false; - pop(REGNUM_EAX); - pop(REGNUM_ECX); - pop(REGNUM_EDX); - - return true; -} - -bool MemEmulator::emulateOriginalESI_EDI() { - scratch.copy(insn_->ptr(), insn_->size()); - return true; -} - -bool MemEmulator::emulateESI_EDIValues() { - // We need to: - // EDI -= EDX - // ESI -= ECX - // And "subtract" means "save the flags" - // ... which in turn means "save eax, fool" - push(REGNUM_EAX); - saveFlags(); - - if (usesESI) ::emitSubRegReg(RealRegister(REGNUM_ESI), RealRegister(ESI_SHIFT_REG), scratch); - if (usesEDI) ::emitSubRegReg(RealRegister(REGNUM_EDI), RealRegister(EDI_SHIFT_REG), scratch); - - restoreFlags(); - pop(REGNUM_EAX); - return true; -} - -bool MemEmulator::restoreAllRegistersESI_EDI() { - - pop(REGNUM_EBP); - pop(REGNUM_EBX); - return true; -} - -string MemEmulator::format() const { - stringstream ret; - ret << "MemE(" << insn_->format() - << "," << std::hex << addr_ << std::dec - << ")"; - - return ret.str(); -} - -Address MemEmulator::getTranslatorAddr(bool wantShift) { - if (wantShift) { - // Function lookup time - func_instance *func = scratch.addrSpace()->findOnlyOneFunction("RTtranslateMemoryShift"); - // FIXME for static rewriting; this is a dynamic-only hack for proof of concept. - if (!func) return 0; - // assert(func); - return func->addr(); - } - else { - // Function lookup time - func_instance *func = scratch.addrSpace()->findOnlyOneFunction("RTtranslateMemory"); - // FIXME for static rewriting; this is a dynamic-only hack for proof of concept. - if (!func) return 0; - // assert(func); - return func->addr(); - } -} - -bool MemEmulatorPatch::apply(codeGen &gen, - CodeBuffer *) { - relocation_cerr << "MemEmulatorPatch::apply @ " << hex << gen.currAddr() << dec << endl; - relocation_cerr << "\tSource reg " << source_ << endl; - assert(!gen.bt()); - - // Two debugging assists - ::emitPushImm(gen.currAddr(), gen); - ::emitPushImm(orig_, gen); - // And our argument - ::emitPush(RealRegister(source_), gen); - - // Step 2: call the translator - Address src = gen.currAddr() + 5; - relocation_cerr << "\tCall " << hex << dest_ << ", offset " << dest_ - src << dec << endl; - assert(dest_); - emitCallRel32(dest_ - src, gen); - if (target_ != REGNUM_EAX) - { - ::emitMovRegToReg(RealRegister(target_), RealRegister(REGNUM_EAX), gen); - } - ::emitLEA(RealRegister(REGNUM_ESP), RealRegister(Null_Register), 0, 12, RealRegister(REGNUM_ESP), gen); - - return true; -} - diff --git a/dyninstAPI/src/MemoryEmulator/memEmulatorWidget.h b/dyninstAPI/src/MemoryEmulator/memEmulatorWidget.h deleted file mode 100644 index 853b3e05b6..0000000000 --- a/dyninstAPI/src/MemoryEmulator/memEmulatorWidget.h +++ /dev/null @@ -1,185 +0,0 @@ -/* - * See the dyninst/COPYRIGHT file for copyright information. - * - * We provide the Paradyn Tools (below described as "Paradyn") - * on an AS IS basis, and do not warrant its validity or performance. - * We reserve the right to update, modify, or discontinue this - * software at any time. We shall have no obligation to supply such - * updates or modifications or any other form of support to you. - * - * By your use of Paradyn, you understand and agree that we (or any - * other person or entity with proprietary rights in Paradyn) are - * under no obligation to provide either maintenance services, - * update services, notices of latent defects, or correction of - * defects for Paradyn. - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#if !defined(cap_mem_emulation) -#error -#endif - - -#if !defined (_R_E_MEM_EMULATOR_H_) -#define _R_E_MEM_EMULATOR_H_ - -#include "dyninstAPI/src/Relocation/Widgets/Widget.h" -#include "dyninstAPI/src/codegen.h" -#include -class registerSlot; - - -namespace Dyninst { -namespace Relocation { - -class MemEmulatorTranslator; - -class MemEmulator : public Widget { - friend class MemEmulatorTranslator; - typedef std::map TranslatorMap; - public: - typedef boost::shared_ptr Ptr; - - static Ptr create(InstructionAPI::Instruction::Ptr insn, - Address addr, - instPoint *point); - - virtual bool generate(const codeGen &, const RelocBlock *, CodeBuffer &); - - virtual ~MemEmulator() {}; - virtual std::string format() const; - - virtual Address addr() const { return addr_; } - virtual unsigned size() const { return insn_->size(); } - virtual InstructionAPI::Instruction::Ptr insn() const { return insn_; } - - private: - MemEmulator(InstructionAPI::Instruction::Ptr insn, - Address addr, - instPoint *point) - : insn_(insn), - addr_(addr), - point_(point) - {}; - - // Set up the codeGen structures we use to hold code. - bool initialize(const codeGen &templ, const RelocBlock *); - - // Handle a0-a3 implicit EAX uses, or ESI/EDI instructions - bool generateViaOverride(CodeBuffer &buffer); - - // Handle generic MOD/RM using instructions - bool generateViaModRM(CodeBuffer &buffer); - - // Handle a0-a3 implicit EAX moves - bool generateEAXMove(unsigned char opcode, CodeBuffer &buffer); - - // Handle ESI/EDI instructions - bool generateESI_EDI(CodeBuffer &buffer); - - // Handle POPAD instructions - bool generatePOPAD(CodeBuffer &buffer); - - // Drop in a trap for later debugging assistance - void insertDebugMarker(); - - // Initialize mod/rm specific data - bool generateModRMInitialize(); - // Create the pre-call handling for MOD/RM instructions - bool generateTranslatorSetup(); - // Create the call to the translator function - bool generateTranslatorCall(CodeBuffer &buffer); - // Create the teardown code - bool generateTranslatorTeardown(); - - // Move the stack down by a known amount - bool shiftStack(); - // Determine which register we can use for the effective address - bool determineEffAddr(); - // Save eax/ecx/edx - bool saveRegisters(); - // Run the effective address calculation before we modify anything (except the stack pointer, sigh) - bool calculateEffAddr(); - // Save the flags - bool saveFlags(); - - // Restore flags after the call - bool restoreFlags(); - // Restore caller-saved registers (except effAddr) - bool restoreRegisters(); - // Restore the stack - bool restoreStack(); - // Emulate the original instruction using effAddr instead of the original expression - bool emulateOriginalInstruction(); - // And restore the effective address register - bool restoreEffectiveAddr(); - - // ESI/EDI implicit shtuff - bool determineESI_EDIUse(); - bool saveRegistersESI_EDI(); // Almost, but not quite the same as saveRegisters. Yuck. - bool generateESIShift(CodeBuffer &buffer); - bool generateEDIShift(CodeBuffer &buffer); - bool saveShiftsAndRestoreRegs(); - bool emulateOriginalESI_EDI(); - bool emulateESI_EDIValues(); - bool restoreAllRegistersESI_EDI(); - - // Copy code into the CodeBuffer (and reset the scratch codegen) - bool copyScratchToCodeBuffer(CodeBuffer &); - TrackerElement *tracker() const; - bool push(Register); - bool pop(Register); - Address getTranslatorAddr(bool wantShiftFunc); - - - /// Members - Register effAddr; - int stackOffset; - int effAddrSaveOffset; - block_instance *block; - - bool usesESI; - bool usesEDI; - - codeGen scratch; - bool debug; - - InstructionAPI::Instruction::Ptr insn_; - Address addr_; - instPoint *point_; -}; - -struct MemEmulatorPatch : public Patch { - // Put in a call to the RTtranslateMemory - // function - MemEmulatorPatch(Register s, - Register t, - Address o, - Address d) - : source_(s), target_(t), orig_(o), dest_(d) {}; - virtual bool apply(codeGen &gen, CodeBuffer *buf); - virtual unsigned estimate(codeGen &) { return 7; }; - virtual ~MemEmulatorPatch() {}; - - Register source_; - Register target_; - Address orig_; - Address dest_; -}; - -}; -}; -#endif diff --git a/dyninstAPI/src/Parsing.C b/dyninstAPI/src/Parsing.C index c8f43bb552..a282fa4e3c 100644 --- a/dyninstAPI/src/Parsing.C +++ b/dyninstAPI/src/Parsing.C @@ -27,6 +27,7 @@ * License along with this library; if not, write to the Free Software * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include #include "InstructionDecoder.h" @@ -263,12 +264,6 @@ DynParseCallback::patch_nop_jump(Address addr) void DynParseCallback::interproc_cf(Function*f,Block *b,Address /*addr*/,interproc_details*det) { -#if defined(ppc32_linux) - if(det->type == interproc_details::call) { - parse_func * ifunc = static_cast(f); - _img->updatePltFunc(ifunc,det->data.call.target); - } -#endif (void) f; // compiler warning if (det->type == ParseCallback::interproc_details::unresolved) { static_cast(b)->setUnresolvedCF(true); diff --git a/dyninstAPI/src/Parsing.h b/dyninstAPI/src/Parsing.h index 600604149e..1e9da08638 100644 --- a/dyninstAPI/src/Parsing.h +++ b/dyninstAPI/src/Parsing.h @@ -30,16 +30,20 @@ #ifndef _PARSING_H_ #define _PARSING_H_ +#include +#include +#include #include "parseAPI/h/CFGFactory.h" #include "parseAPI/h/CodeSource.h" #include "parseAPI/h/InstructionSource.h" #include "parseAPI/h/CFG.h" #include "parseAPI/h/ParseCallback.h" +#include "dyntypes.h" // some useful types -using ParseAPI::EdgeTypeEnum; -using ParseAPI::FuncReturnStatus; -using ParseAPI::FuncSource; +using Dyninst::ParseAPI::EdgeTypeEnum; +using Dyninst::ParseAPI::FuncReturnStatus; +using Dyninst::ParseAPI::FuncSource; using std::vector; /*** The image_* object factory ***/ @@ -56,26 +60,26 @@ class DynCFGFactory : public Dyninst::ParseAPI::CFGFactory { DynCFGFactory(image * im); ~DynCFGFactory() {} - ParseAPI::Function * mkfunc(Address addr, FuncSource src, std::string name, - ParseAPI::CodeObject * obj, ParseAPI::CodeRegion * reg, - InstructionSource * isrc); - ParseAPI::Block * mkblock(ParseAPI::Function * f, ParseAPI::CodeRegion * r, - Address addr); - ParseAPI::Edge * mkedge(ParseAPI::Block * src, ParseAPI::Block * trg, + Dyninst::ParseAPI::Function * mkfunc(Dyninst::Address addr, FuncSource src, std::string name, + Dyninst::ParseAPI::CodeObject * obj, Dyninst::ParseAPI::CodeRegion * reg, + Dyninst::InstructionSource * isrc); + Dyninst::ParseAPI::Block * mkblock(Dyninst::ParseAPI::Function * f, Dyninst::ParseAPI::CodeRegion * r, + Dyninst::Address addr); + Dyninst::ParseAPI::Edge * mkedge(Dyninst::ParseAPI::Block * src, Dyninst::ParseAPI::Block * trg, EdgeTypeEnum type); - ParseAPI::Block * mksink(ParseAPI::CodeObject *obj, ParseAPI::CodeRegion*r); + Dyninst::ParseAPI::Block * mksink(Dyninst::ParseAPI::CodeObject *obj, Dyninst::ParseAPI::CodeRegion*r); // leaving default atm - //void free_func(ParseAPI::Function * f); - //void free_block(ParseAPI::Block * b); - //void free_edge(ParseAPI::Edge * e); + //void free_func(Dyninst::ParseAPI::Function * f); + //void free_block(Dyninst::ParseAPI::Block * b); + //void free_edge(Dyninst::ParseAPI::Edge * e); //void free_all(); void dump_stats(); private: - boost::mutex _mtx; + dyncompat::mutex _mtx; image * _img; std::vector _func_allocs; std::vector _edge_allocs; @@ -83,14 +87,14 @@ class DynCFGFactory : public Dyninst::ParseAPI::CFGFactory { int _sink_block_allocs; //int _sink_edge_allocs; FIXME can't determine - void _record_func_alloc(ParseAPI::FuncSource fs) + void _record_func_alloc(Dyninst::ParseAPI::FuncSource fs) { - assert(fs < ParseAPI::_funcsource_end_); + assert(fs < Dyninst::ParseAPI::_funcsource_end_); ++_func_allocs[fs]; } - void _record_edge_alloc(ParseAPI::EdgeTypeEnum et,bool /* sink */) + void _record_edge_alloc(Dyninst::ParseAPI::EdgeTypeEnum et,bool /* sink */) { - assert(et < ParseAPI::_edgetype_end_); + assert(et < Dyninst::ParseAPI::_edgetype_end_); ++_edge_allocs[et]; //if(sink) @@ -105,34 +109,34 @@ class DynCFGFactory : public Dyninst::ParseAPI::CFGFactory { }; class image; -class DynParseCallback : public ParseAPI::ParseCallback { +class DynParseCallback : public Dyninst::ParseAPI::ParseCallback { public: - DynParseCallback(image * img) : ParseAPI::ParseCallback(), _img(img) { } + DynParseCallback(image * img) : Dyninst::ParseAPI::ParseCallback(), _img(img) { } ~DynParseCallback() { } protected: // defensive and exploratory mode callbacks - virtual void abruptEnd_cf(Address,ParseAPI::Block *,default_details*); - virtual void newfunction_retstatus(ParseAPI::Function*); - virtual void patch_nop_jump(Address); - virtual bool hasWeirdInsns(const ParseAPI::Function*) const; - virtual void foundWeirdInsns(ParseAPI::Function*); + virtual void abruptEnd_cf(Dyninst::Address,Dyninst::ParseAPI::Block *,default_details*); + virtual void newfunction_retstatus(Dyninst::ParseAPI::Function*); + virtual void patch_nop_jump(Dyninst::Address); + virtual bool hasWeirdInsns(const Dyninst::ParseAPI::Function*) const; + virtual void foundWeirdInsns(Dyninst::ParseAPI::Function*); // other callbacks - virtual void interproc_cf(ParseAPI::Function*,ParseAPI::Block*,Address,interproc_details*); - virtual void overlapping_blocks(ParseAPI::Block*,ParseAPI::Block*); - virtual bool updateCodeBytes(Address target); // updates if needed - virtual void split_block_cb(ParseAPI::Block *, ParseAPI::Block *); // needed for defensive mode + virtual void interproc_cf(Dyninst::ParseAPI::Function*,Dyninst::ParseAPI::Block*,Dyninst::Address,interproc_details*); + virtual void overlapping_blocks(Dyninst::ParseAPI::Block*,Dyninst::ParseAPI::Block*); + virtual bool updateCodeBytes(Dyninst::Address target); // updates if needed + virtual void split_block_cb(Dyninst::ParseAPI::Block *, Dyninst::ParseAPI::Block *); // needed for defensive mode - virtual void destroy_cb(ParseAPI::Block *); - virtual void destroy_cb(ParseAPI::Edge *); - virtual void destroy_cb(ParseAPI::Function *); + virtual void destroy_cb(Dyninst::ParseAPI::Block *); + virtual void destroy_cb(Dyninst::ParseAPI::Edge *); + virtual void destroy_cb(Dyninst::ParseAPI::Function *); - virtual void remove_edge_cb(ParseAPI::Block *, ParseAPI::Edge *, edge_type_t); - virtual void remove_block_cb(ParseAPI::Function *, ParseAPI::Block *); + virtual void remove_edge_cb(Dyninst::ParseAPI::Block *, Dyninst::ParseAPI::Edge *, edge_type_t); + virtual void remove_block_cb(Dyninst::ParseAPI::Function *, Dyninst::ParseAPI::Block *); #if defined(arch_power) || defined(arch_aarch64) - void instruction_cb(ParseAPI::Function*, ParseAPI::Block *, Address, insn_details*); + void instruction_cb(Dyninst::ParseAPI::Function*, Dyninst::ParseAPI::Block *, Dyninst::Address, insn_details*); #endif private: image * _img; diff --git a/dyninstAPI/src/RegisterConversion-aarch64.C b/dyninstAPI/src/RegisterConversion-aarch64.C index fcd67730a6..9085c51020 100644 --- a/dyninstAPI/src/RegisterConversion-aarch64.C +++ b/dyninstAPI/src/RegisterConversion-aarch64.C @@ -28,19 +28,22 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include "RegisterConversion.h" #include "registerSpace.h" #include -#include +#include + #include "Register.h" -#include "dyn_regs.h" +#include "registers/MachRegister.h" +#include "registers/abstract_regs.h" #include "registerSpace.h" using namespace Dyninst; using namespace Dyninst::InstructionAPI; using namespace std; -using namespace boost::assign; +using namespace dyncompat::assign; //#warning "This file is not verified yet!" multimap regToMachReg64 = map_list_of diff --git a/dyninstAPI/src/RegisterConversion-ppc.C b/dyninstAPI/src/RegisterConversion-ppc.C index 0eb89bf306..c99c651d96 100644 --- a/dyninstAPI/src/RegisterConversion-ppc.C +++ b/dyninstAPI/src/RegisterConversion-ppc.C @@ -28,19 +28,22 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include "RegisterConversion.h" #include "registerSpace.h" #include -#include +#include + #include "Register.h" -#include "dyn_regs.h" +#include "registers/ppc32_regs.h" +#include "registers/abstract_regs.h" #include "registerSpace.h" using namespace Dyninst; using namespace Dyninst::InstructionAPI; using namespace std; -using namespace boost::assign; +using namespace dyncompat::assign; multimap regToMachReg32 = map_list_of (registerSpace::r0, ppc32::r0) diff --git a/dyninstAPI/src/RegisterConversion-x86.C b/dyninstAPI/src/RegisterConversion-x86.C index e00d9747a4..8a34656ab4 100644 --- a/dyninstAPI/src/RegisterConversion-x86.C +++ b/dyninstAPI/src/RegisterConversion-x86.C @@ -28,18 +28,21 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include "RegisterConversion.h" #include "inst-x86.h" #include -#include +#include + #include "Register.h" -#include "dyn_regs.h" +#include "registers/x86_regs.h" +#include "registers/x86_64_regs.h" using namespace Dyninst; using namespace Dyninst::InstructionAPI; using namespace std; -using namespace boost::assign; +using namespace dyncompat::assign; using namespace NS_x86; multimap regToMachReg32 = map_list_of diff --git a/dyninstAPI/src/RegisterConversion.h b/dyninstAPI/src/RegisterConversion.h index 1907d5f72d..8d0ff0dc9d 100644 --- a/dyninstAPI/src/RegisterConversion.h +++ b/dyninstAPI/src/RegisterConversion.h @@ -31,10 +31,11 @@ #if !defined(REGISTER_CONVERSION_H) #define REGISTER_CONVERSION_H -#include "Register.h" -#include "common/src/Types.h" -#include "common/h/dyn_regs.h" +#include "registers/MachRegister.h" +#include "Architecture.h" #include +#include "dyn_register.h" +#include "Register.h" using namespace Dyninst; diff --git a/dyninstAPI/src/Relocation/CFG/RelocBlock.C b/dyninstAPI/src/Relocation/CFG/RelocBlock.C index f1f4f26a76..a2c1535c82 100644 --- a/dyninstAPI/src/Relocation/CFG/RelocBlock.C +++ b/dyninstAPI/src/Relocation/CFG/RelocBlock.C @@ -28,10 +28,11 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include #include -#include "../dyninstAPI/src/debug.h" +#include "dyninstAPI/src/debug.h" #include "../Widgets/Widget.h" #include "../Widgets/InsnWidget.h" // Default Widget in each RelocBlock @@ -45,7 +46,7 @@ #include "../Transformers/Transformer.h" // transformer class #include "RelocGraph.h" -#include "boost/tuple/tuple.hpp" +#include "dyncompat/tuple/tuple.hpp" using namespace Dyninst; using namespace Relocation; @@ -188,7 +189,7 @@ void RelocBlock::processEdge(EdgeDirection e, edge_instance *edge, RelocGraph *c case ParseAPI::DIRECT: { bool valid; Address addr; - boost::tie(valid, addr) = getJumpTarget(); + std::tie(valid, addr) = getJumpTarget(); if (valid) { cfg->makeEdge(new Target(this), new Target
(addr), diff --git a/dyninstAPI/src/Relocation/CFG/RelocBlock.h b/dyninstAPI/src/Relocation/CFG/RelocBlock.h index 0e490b3066..7770c3fbb3 100644 --- a/dyninstAPI/src/Relocation/CFG/RelocBlock.h +++ b/dyninstAPI/src/Relocation/CFG/RelocBlock.h @@ -31,7 +31,10 @@ #if !defined(PATCHAPI_TRACE_H_) #define PATCHAPI_TRACE_H_ -#include "common/src/Types.h" // Address +#include +#include +#include +#include "dyntypes.h" #include "dyninstAPI/src/codegen.h" // codeGen #include "dyninstAPI/src/function.h" #include "instructionAPI/h/Instruction.h" // Instruction::Ptr @@ -55,9 +58,9 @@ class CodeTracker; class CodeBuffer; class CFWidget; -typedef boost::shared_ptr CFWidgetPtr; +typedef dyncompat::shared_ptr CFWidgetPtr; class Widget; -typedef boost::shared_ptr WidgetPtr; +typedef dyncompat::shared_ptr WidgetPtr; struct RelocEdge; struct RelocEdges; diff --git a/dyninstAPI/src/Relocation/CFG/RelocEdge.C b/dyninstAPI/src/Relocation/CFG/RelocEdge.C index f6e78d5f65..e55cb4e49a 100644 --- a/dyninstAPI/src/Relocation/CFG/RelocEdge.C +++ b/dyninstAPI/src/Relocation/CFG/RelocEdge.C @@ -27,6 +27,7 @@ * License along with this library; if not, write to the Free Software * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include "RelocBlock.h" #include "RelocTarget.h" #include "RelocEdge.h" diff --git a/dyninstAPI/src/Relocation/CFG/RelocEdge.h b/dyninstAPI/src/Relocation/CFG/RelocEdge.h index 28e2e55104..da09bda30c 100644 --- a/dyninstAPI/src/Relocation/CFG/RelocEdge.h +++ b/dyninstAPI/src/Relocation/CFG/RelocEdge.h @@ -30,6 +30,8 @@ #if !defined(RELOC_EDGE_H_) #define RELOC_EDGE_H_ +#include + namespace Dyninst { namespace Relocation { diff --git a/dyninstAPI/src/Relocation/CFG/RelocGraph.C b/dyninstAPI/src/Relocation/CFG/RelocGraph.C index 17ada1205f..482f1a5127 100644 --- a/dyninstAPI/src/Relocation/CFG/RelocGraph.C +++ b/dyninstAPI/src/Relocation/CFG/RelocGraph.C @@ -28,6 +28,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include "RelocGraph.h" #include "RelocBlock.h" #include diff --git a/dyninstAPI/src/Relocation/CFG/RelocGraph.h b/dyninstAPI/src/Relocation/CFG/RelocGraph.h index f3d26f8c70..fe12c551e3 100644 --- a/dyninstAPI/src/Relocation/CFG/RelocGraph.h +++ b/dyninstAPI/src/Relocation/CFG/RelocGraph.h @@ -37,6 +37,8 @@ #include "RelocTarget.h" // Targets #include #include +#include +#include class codeGen; class block_instance; @@ -50,7 +52,7 @@ class RelocBlock; struct RelocEdge; class TargetInt; class Widget; -typedef boost::shared_ptr WidgetPtr; +typedef dyncompat::shared_ptr WidgetPtr; typedef std::list WidgetList; class RelocGraph { diff --git a/dyninstAPI/src/Relocation/CFG/RelocTarget.h b/dyninstAPI/src/Relocation/CFG/RelocTarget.h index 836f31aa1b..b84efff0bd 100644 --- a/dyninstAPI/src/Relocation/CFG/RelocTarget.h +++ b/dyninstAPI/src/Relocation/CFG/RelocTarget.h @@ -31,6 +31,8 @@ #if !defined (_R_E_TARGET_H_) #define _R_E_TARGET_H_ +#include +#include #include "../Widgets/Widget.h" #include "RelocBlock.h" diff --git a/dyninstAPI/src/Relocation/CodeBuffer.C b/dyninstAPI/src/Relocation/CodeBuffer.C index 295baaa6f4..acb791d154 100644 --- a/dyninstAPI/src/Relocation/CodeBuffer.C +++ b/dyninstAPI/src/Relocation/CodeBuffer.C @@ -28,6 +28,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include "CodeBuffer.h" #include "CodeTracker.h" #include "Widgets/Widget.h" // Currently Patch is defined here; we may want to move it. @@ -47,7 +48,13 @@ using namespace InstructionAPI; const unsigned CodeBuffer::Label::INVALID = (unsigned) -1; -CodeBuffer::BufferElement::BufferElement() : addr_(0), size_(0), patch_(NULL), labelID_(Label::INVALID) {} +CodeBuffer::BufferElement::BufferElement() = default; + +CodeBuffer::BufferElement::BufferElement(CodeBuffer::BufferElement&& other) { + *this = other; + other.patch_ = nullptr; +} + CodeBuffer::BufferElement::~BufferElement() { if (patch_) delete patch_; @@ -115,7 +122,7 @@ bool CodeBuffer::BufferElement::generate(CodeBuffer *buf, if (patch_) { // Now things get interesting if (!patch_->apply(gen, buf)) { - relocation_cerr << "Patch failed application, ret false" << endl; + relocation_cerr << "Patch failed application, ret false" << std::endl; return false; } } @@ -296,7 +303,7 @@ void CodeBuffer::disassemble() const { Instruction cur = decoder.decode(); while (cur.isValid()) { - cerr << "\t" << std::hex << addr << std::dec << ": " << cur.format() << endl; + cerr << "\t" << std::hex << addr << std::dec << ": " << cur.format() << std::endl; addr += cur.size(); cur = decoder.decode(); } @@ -307,7 +314,7 @@ void CodeBuffer::updateLabel(unsigned id, Address offset, bool ®enerate) { if (id >= labels_.size()) { - cerr << "ERROR: id of " << id << " but only " << labels_.size() << " labels!" << endl; + cerr << "ERROR: id of " << id << " but only " << labels_.size() << " labels!" << std::endl; } assert(id < labels_.size()); assert(id > 0); @@ -334,7 +341,7 @@ Address CodeBuffer::getLabelAddr(unsigned id) { Address CodeBuffer::predictedAddr(unsigned id) { if (id >= labels_.size()) { - cerr << "ERROR: id of " << id << " but only " << labels_.size() << " labels!" << endl; + cerr << "ERROR: id of " << id << " but only " << labels_.size() << " labels!" << std::endl; } assert(id < labels_.size()); assert(id > 0); diff --git a/dyninstAPI/src/Relocation/CodeBuffer.h b/dyninstAPI/src/Relocation/CodeBuffer.h index 96bd47de34..ffcfb09c3c 100644 --- a/dyninstAPI/src/Relocation/CodeBuffer.h +++ b/dyninstAPI/src/Relocation/CodeBuffer.h @@ -56,6 +56,9 @@ // of code they have provided. #include "common/h/dyntypes.h" +#include +#include +#include #include #include "dyninstAPI/src/codegen.h" @@ -100,7 +103,7 @@ class CodeBuffer { static const unsigned INVALID; - Label() + Label() noexcept : type(Invalid), id(0), iteration(0), addr(0) {} Label(Type a, Id b, Address c) : type(a), id(b), iteration(0), addr(c) { assert(id != INVALID); } @@ -111,6 +114,8 @@ class CodeBuffer { friend class CodeBuffer; public: BufferElement(); + BufferElement(const BufferElement&) = delete; + BufferElement(BufferElement&&); ~BufferElement(); void setLabelID(unsigned id); void addPIC(const unsigned char *input, unsigned size, TrackerElement *tracker); @@ -126,13 +131,14 @@ class CodeBuffer { bool extractTrackers(CodeTracker *t); private: + BufferElement& operator=(BufferElement&) = default; void addTracker(TrackerElement *tracker); - Address addr_; - unsigned size_; + Address addr_{}; + unsigned size_{}; Buffer buffer_; - Patch *patch_; - unsigned labelID_; + Patch *patch_{}; + unsigned labelID_{Label::INVALID}; // Here the Offset is an offset within the buffer, starting at 0. typedef std::map Trackers; Trackers trackers_; diff --git a/dyninstAPI/src/Relocation/CodeMover.C b/dyninstAPI/src/Relocation/CodeMover.C index 38160cd20f..7a5e5d2362 100644 --- a/dyninstAPI/src/Relocation/CodeMover.C +++ b/dyninstAPI/src/Relocation/CodeMover.C @@ -28,6 +28,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include "Relocation.h" #include "CodeMover.h" #include "Widgets/Widget.h" diff --git a/dyninstAPI/src/Relocation/CodeMover.h b/dyninstAPI/src/Relocation/CodeMover.h index 207e33982a..62cf1d3901 100644 --- a/dyninstAPI/src/Relocation/CodeMover.h +++ b/dyninstAPI/src/Relocation/CodeMover.h @@ -33,7 +33,9 @@ #define _R_CODE_MOVER_H_ #include "CFG.h" -#include "common/src/Types.h" +#include +#include +#include #include #include #include "dyninstAPI/src/codegen.h" // codeGen structure @@ -63,7 +65,7 @@ typedef std::map, Priority> Priorit class CodeMover { public: - typedef boost::shared_ptr Ptr; + typedef dyncompat::shared_ptr Ptr; typedef std::set FuncSet; typedef std::set BlockSet; diff --git a/dyninstAPI/src/Relocation/CodeTracker.C b/dyninstAPI/src/Relocation/CodeTracker.C index 4e72734cc8..5535d5d361 100644 --- a/dyninstAPI/src/Relocation/CodeTracker.C +++ b/dyninstAPI/src/Relocation/CodeTracker.C @@ -28,6 +28,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include "CodeTracker.h" #include "dyninstAPI/src/debug.h" #include "dyninstAPI/src/function.h" diff --git a/dyninstAPI/src/Relocation/CodeTracker.h b/dyninstAPI/src/Relocation/CodeTracker.h index 516ec6245c..ba8c3a3783 100644 --- a/dyninstAPI/src/Relocation/CodeTracker.h +++ b/dyninstAPI/src/Relocation/CodeTracker.h @@ -35,6 +35,8 @@ #define _R_CODE_TRACKER_H_ #include "common/h/dyntypes.h" +#include +#include #include #include #include diff --git a/dyninstAPI/src/Relocation/DynAddrSpace.h b/dyninstAPI/src/Relocation/DynAddrSpace.h index e1c2b2d2f6..a43e500fa1 100644 --- a/dyninstAPI/src/Relocation/DynAddrSpace.h +++ b/dyninstAPI/src/Relocation/DynAddrSpace.h @@ -32,6 +32,8 @@ #ifndef PATCHAPI_H_DYNINST_DYNADDRSPACE_H_ #define PATCHAPI_H_DYNINST_DYNADDRSPACE_H_ +#include +#include #include "DynCommon.h" class AddressSpace; diff --git a/dyninstAPI/src/Relocation/DynCommon.h b/dyninstAPI/src/Relocation/DynCommon.h index a79e441896..cdbaca037b 100644 --- a/dyninstAPI/src/Relocation/DynCommon.h +++ b/dyninstAPI/src/Relocation/DynCommon.h @@ -37,7 +37,7 @@ // Dyninst Internal #include "dyninstAPI/src/addressSpace.h" -#define DYN_CAST(type, obj) boost::dynamic_pointer_cast(obj) +#define DYN_CAST(type, obj) dyncompat::dynamic_pointer_cast(obj) // Shortcuts for type casting #define SCAST_MO(o) static_cast(o) diff --git a/dyninstAPI/src/Relocation/DynInstrumenter.C b/dyninstAPI/src/Relocation/DynInstrumenter.C index 8151a069b6..91518e0c63 100644 --- a/dyninstAPI/src/Relocation/DynInstrumenter.C +++ b/dyninstAPI/src/Relocation/DynInstrumenter.C @@ -27,6 +27,7 @@ * License along with this library; if not, write to the Free Software * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include "DynInstrumenter.h" #include "BPatch_point.h" #include "BPatch_addressSpace.h" diff --git a/dyninstAPI/src/Relocation/DynObject.h b/dyninstAPI/src/Relocation/DynObject.h index 28ce602d6b..8399baccd9 100644 --- a/dyninstAPI/src/Relocation/DynObject.h +++ b/dyninstAPI/src/Relocation/DynObject.h @@ -72,7 +72,7 @@ class DynCFGMaker : public Dyninst::PatchAPI::CFGMaker { virtual PatchEdge* makeEdge(ParseAPI::Edge*, PatchBlock*, PatchBlock*, PatchObject*); virtual PatchEdge* copyEdge(PatchEdge*, PatchObject*); }; -typedef boost::shared_ptr DynCFGMakerPtr; +typedef dyncompat::shared_ptr DynCFGMakerPtr; } } diff --git a/dyninstAPI/src/Relocation/DynPointMaker.C b/dyninstAPI/src/Relocation/DynPointMaker.C index 26ed8ed69c..56d7c2e2af 100644 --- a/dyninstAPI/src/Relocation/DynPointMaker.C +++ b/dyninstAPI/src/Relocation/DynPointMaker.C @@ -27,12 +27,9 @@ * License along with this library; if not, write to the Free Software * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "common/src/Types.h" - #include "DynPointMaker.h" #include "dyninstAPI/src/function.h" #include "dyninstAPI/src/instPoint.h" -#include "common/src/Types.h" #include "instructionAPI/h/Instruction.h" Point *DynPointMaker::mkFuncPoint(Point::Type t, PatchMgrPtr m, PatchFunction *f) { diff --git a/dyninstAPI/src/Relocation/DynPointMaker.h b/dyninstAPI/src/Relocation/DynPointMaker.h index 32eeaacb6c..f41d46135b 100644 --- a/dyninstAPI/src/Relocation/DynPointMaker.h +++ b/dyninstAPI/src/Relocation/DynPointMaker.h @@ -31,7 +31,6 @@ #define PATCHAPI_DYNPOINTMAKER_H_ #include "Point.h" -#include "common/src/Types.h" #include "instructionAPI/h/Instruction.h" @@ -52,8 +51,8 @@ class DynPointMaker : public Dyninst::PatchAPI::PointMaker { virtual Point *mkFuncPoint(Point::Type t, PatchMgrPtr m, PatchFunction *); virtual Point *mkFuncSitePoint(Point::Type t, PatchMgrPtr m, PatchFunction *, PatchBlock *); virtual Point *mkBlockPoint(Point::Type t, PatchMgrPtr m, PatchBlock *, PatchFunction *context); - virtual Point *mkInsnPoint(Point::Type t, PatchMgrPtr m, PatchBlock *, Address, - InstructionAPI::Instruction, PatchFunction *context); + virtual Point *mkInsnPoint(Point::Type t, PatchMgrPtr m, PatchBlock *, Dyninst::Address, + Dyninst::InstructionAPI::Instruction, PatchFunction *context); virtual Point *mkEdgePoint(Point::Type t, PatchMgrPtr m, PatchEdge *, PatchFunction *f); }; diff --git a/dyninstAPI/src/Relocation/Relocation.h b/dyninstAPI/src/Relocation/Relocation.h index 417ddf0466..35c8e36802 100644 --- a/dyninstAPI/src/Relocation/Relocation.h +++ b/dyninstAPI/src/Relocation/Relocation.h @@ -35,11 +35,10 @@ #if !defined(_RELOCATION_H_) #define _RELOCATION_H_ -#include "common/src/Types.h" #include #include #include "dyninstAPI/src/codegen.h" // codeGen structure -#include "boost/shared_ptr.hpp" +#include "dyncompat/shared_ptr.hpp" namespace Dyninst { namespace Relocation { @@ -49,8 +48,8 @@ class SpringboardMap; struct SpringboardReq; class SpringboardBuilder; -typedef boost::shared_ptr CodeMoverPtr; -typedef boost::shared_ptr SpringboardBuilderPtr; +typedef dyncompat::shared_ptr CodeMoverPtr; +typedef dyncompat::shared_ptr SpringboardBuilderPtr; } } diff --git a/dyninstAPI/src/Relocation/Springboard.C b/dyninstAPI/src/Relocation/Springboard.C index 361bfe68c0..33221f0fd0 100644 --- a/dyninstAPI/src/Relocation/Springboard.C +++ b/dyninstAPI/src/Relocation/Springboard.C @@ -28,6 +28,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include "CFG.h" #include "Springboard.h" #include "dyninstAPI/src/debug.h" diff --git a/dyninstAPI/src/Relocation/Springboard.h b/dyninstAPI/src/Relocation/Springboard.h index 9633ae006c..a17118371b 100644 --- a/dyninstAPI/src/Relocation/Springboard.h +++ b/dyninstAPI/src/Relocation/Springboard.h @@ -32,6 +32,9 @@ #if !defined(_R_SPRINGBOARD_H_) #define _R_SPRINGBOARD_H_ +#include +#include +#include #include #include "common/src/IntervalTree.h" #include "common/h/dyntypes.h" @@ -222,7 +225,7 @@ struct SpringboardInfo { class InstalledSpringboards { public: - typedef boost::shared_ptr Ptr; + typedef dyncompat::shared_ptr Ptr; static const int Allocated; static const int UnallocatedStart; InstalledSpringboards() {} @@ -277,7 +280,7 @@ class SpringboardBuilder { Succeeded } generateResult_t; public: - typedef boost::shared_ptr Ptr; + typedef dyncompat::shared_ptr Ptr; typedef std::set FuncSet; static Ptr createFunc(FuncSet::const_iterator begin, FuncSet::const_iterator end, AddressSpace *addrSpace); diff --git a/dyninstAPI/src/Relocation/Transformers/Defensive.C b/dyninstAPI/src/Relocation/Transformers/Defensive.C deleted file mode 100644 index 46f26691dd..0000000000 --- a/dyninstAPI/src/Relocation/Transformers/Defensive.C +++ /dev/null @@ -1,167 +0,0 @@ -/* - * See the dyninst/COPYRIGHT file for copyright information. - * - * We provide the Paradyn Tools (below described as "Paradyn") - * on an AS IS basis, and do not warrant its validity or performance. - * We reserve the right to update, modify, or discontinue this - * software at any time. We shall have no obligation to supply such - * updates or modifications or any other form of support to you. - * - * By your use of Paradyn, you understand and agree that we (or any - * other person or entity with proprietary rights in Paradyn) are - * under no obligation to provide either maintenance services, - * update services, notices of latent defects, or correction of - * defects for Paradyn. - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - */ - - - -#include "Transformer.h" -#include "Defensive.h" -#include "dyninstAPI/src/debug.h" -#include "../Atoms/Atom.h" -#include "dyninstAPI/src/function.h" -#include "../Atoms/DefensivePadding.h" -#include "../Atoms/CFAtom.h" -#include "../Atoms/Target.h" - -using namespace std; -using namespace Dyninst; -using namespace Relocation; -using namespace InstructionAPI; - -// This transformer supports Kevin's run-time parsing of binaries. Specifically, -// it handles the case of calls that we do not have a return status for. When we -// see such a call we append a block of null operations (a pad). If the call returns, -// we use this block to insert a jump to the newly parsed code. -// -// Logically, this code exists in the CFG between the call return and the newly parsed -// code. Since we are inserting a branch to that new code, it is more tightly tied to -// its successor than the call. In addition, it has to place nicely with things like -// post-call instrumentation. Therefore, we are implementing this as a CFG transformation; -// the padding consists of a new Trace that is added between the call trace C and the new trace -// N. - -bool DefensiveTransformer::processTrace(TraceList::iterator &iter) { - relocation_cerr << "DefensiveMode, processing block " - << std::hex << (*iter)->origAddr() << std::dec << endl; - int_block *bbl = (*iter)->bbl(); - if (!bbl) return true; - - if (!requiresDefensivePad(bbl)) { - return true; - } - - // Create a new Trace for this, and add - // a TODO to insert it during postprocess - DefensivePadding::Ptr pad = DefensivePadding::create(bbl); - TracePtr trace = Trace::create(pad, bbl->end(), bbl->func()); - - // Add it as a fallthrough from the prior block, and if the block had a fallthrough - // reassign it to us. - - // 1) Fallthrough for old block. - // 1a) Get CF atom for the block - CFAtom::Ptr cf = boost::dynamic_pointer_cast((*iter)->elements().back()); - assert(cf); - // 1b) Cache old fallthrough if it exists - TargetInt *oldFallthrough = cf->getDestination(CFAtom::Fallthrough); - // 1c) Set us to be fallthrough - Target *t = new Target(trace); - cf->addDestination(CFAtom::Fallthrough, t); - - // 2) Fallthrough for us - CFAtom::Ptr newCFAtom = CFAtom::create(bbl); - newCFAtom->updateAddr(bbl->end()); - trace->elements().push_back(newCFAtom); - if (oldFallthrough) { - newCFAtom->addDestination(CFAtom::Fallthrough, oldFallthrough); - } - - defensivePads_[*iter] = trace; - - return true; -} - -bool DefensiveTransformer::postprocess(TraceList &l) { - for (TraceList::iterator iter = l.begin(); - iter != l.end(); ++iter) - { - InsertionMap::iterator foo = defensivePads_.find(*iter); - if (foo != defensivePads_.end()) { - // We want the new one _after_ the current location. - if (iter == l.end()) { - // Oddd.... - l.push_back(foo->second); - } - else { - ++iter; - l.insert(iter, foo->second); - --iter; - } - } - } - return true; -} -// First parameter: do we need a defensive -bool DefensiveTransformer::requiresDefensivePad(const int_block *block) { - // Find if the program does anything funky with a call fallthrough - // 1) A call edge with no fallthrough - // 2) A gap between the call block and the fallthrough block. - - ParseAPI::Edge *callEdge = NULL; - ParseAPI::Edge *ftEdge = NULL; - - const ParseAPI::Block::edgelist &targets = block->llb()->targets(); - ParseAPI::Block::edgelist::iterator iter = targets.begin(); - for (; iter != targets.end(); ++iter) { - if ((*iter)->type() == ParseAPI::CALL) { - callEdge = *iter; - } - if ((*iter)->type() == ParseAPI::CALL_FT) { - ftEdge = *iter; - } - } - - if (callEdge && !ftEdge) { - malware_cerr << "Found call edge w/o fallthrough, block @ " - << hex << block->start() << " gets defensive pad " << dec << endl; - return true; - } - else if (callEdge && ftEdge) { - return false; - } - - - // See big comment in ControlFlow.C ; we're omitting edges from the ParseAPI - // and that makes things go badly. - - using namespace InstructionAPI; - - int_block::InsnInstances insns; - block->getInsnInstances(insns); - - // Hack: this also triggers on call-next thunks; only go if we have _no_ - // targets. - if ((insns.back().first->getCategory() == c_CallInsn) && - (targets.empty())) - { - cerr << "Hacky defensive pad for block @ " << hex << block->start() << dec << endl; - return true; - } - return false; -} diff --git a/dyninstAPI/src/Relocation/Transformers/Instrumenter.C b/dyninstAPI/src/Relocation/Transformers/Instrumenter.C index f176007f7b..4bddcf4907 100644 --- a/dyninstAPI/src/Relocation/Transformers/Instrumenter.C +++ b/dyninstAPI/src/Relocation/Transformers/Instrumenter.C @@ -30,9 +30,10 @@ +#include #include "Transformer.h" #include "Instrumenter.h" -#include "../dyninstAPI/src/debug.h" +#include "dyninstAPI/src/debug.h" #include "../Widgets/Widget.h" #include "../CFG/RelocTarget.h" #include "dyninstAPI/src/instPoint.h" @@ -370,6 +371,14 @@ bool Instrumenter::handleCondDirExits(RelocBlock *trace, RelocGraph *cfg, instPo RelocEdge *cond = trace->outs()->find(ParseAPI::COND_TAKEN); + if(!cond || !cond->trg) + { + relocation_cerr << __FILE__ << ":" << __LINE__ << " :: " << __FUNCTION__ + << " failed due to nullptr. Dyninst could not redirect to" + << " the instrumentation block\n"; + return false; + } + cfg->makeEdge(new Target(instRelocBlock), cond->trg->copy(), NULL, diff --git a/dyninstAPI/src/Relocation/Transformers/Instrumenter.h b/dyninstAPI/src/Relocation/Transformers/Instrumenter.h index 0e44037d75..f76c8661e1 100644 --- a/dyninstAPI/src/Relocation/Transformers/Instrumenter.h +++ b/dyninstAPI/src/Relocation/Transformers/Instrumenter.h @@ -31,6 +31,9 @@ #if !defined(_R_T_INSTRUMENTER_H_) #define _R_T_INSTRUMENTER_H_ +#include +#include +#include #include "Transformer.h" #include "dyninstAPI/src/instPoint.h" @@ -55,7 +58,7 @@ class Instrumenter : public Transformer { typedef std::pair InsertPoint; typedef std::map > EdgeRelocBlocks; - typedef boost::shared_ptr CFWidgetPtr; + typedef dyncompat::shared_ptr CFWidgetPtr; // The instrumenters that can add new RelocBlocks have the CFG as an // argument diff --git a/dyninstAPI/src/Relocation/Transformers/Modification.C b/dyninstAPI/src/Relocation/Transformers/Modification.C index f38811a130..0577805679 100644 --- a/dyninstAPI/src/Relocation/Transformers/Modification.C +++ b/dyninstAPI/src/Relocation/Transformers/Modification.C @@ -28,9 +28,10 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include "Transformer.h" #include "Modification.h" -#include "../dyninstAPI/src/debug.h" +#include "dyninstAPI/src/debug.h" #include "../CFG/RelocTarget.h" #include "../Widgets/Widget.h" #include "../Widgets/CFWidget.h" diff --git a/dyninstAPI/src/Relocation/Transformers/Modification.h b/dyninstAPI/src/Relocation/Transformers/Modification.h index 88253236c0..c4c42bf633 100644 --- a/dyninstAPI/src/Relocation/Transformers/Modification.h +++ b/dyninstAPI/src/Relocation/Transformers/Modification.h @@ -34,6 +34,7 @@ #include "Transformer.h" #include "../Widgets/Widget.h" #include "dyninstAPI/src/addressSpace.h" +#include #include #include #include diff --git a/dyninstAPI/src/Relocation/Transformers/Movement-adhoc.C b/dyninstAPI/src/Relocation/Transformers/Movement-adhoc.C index b5d68cb2b5..29338c7b85 100644 --- a/dyninstAPI/src/Relocation/Transformers/Movement-adhoc.C +++ b/dyninstAPI/src/Relocation/Transformers/Movement-adhoc.C @@ -28,9 +28,10 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include "Transformer.h" #include "Movement-adhoc.h" -#include "../dyninstAPI/src/debug.h" +#include "dyninstAPI/src/debug.h" #include "../Widgets/Widget.h" #include "../Widgets/RelDataWidget.h" #include "../Widgets/StackModWidget.h" @@ -144,7 +145,7 @@ bool adhocMovementTransformer::process(RelocBlock *cur, RelocGraph *cfg) { Absloc aloc; if (isPCDerefCF(*iter, insn, target)) { - CFWidget::Ptr cf = boost::dynamic_pointer_cast(*iter); + CFWidget::Ptr cf = dyncompat::dynamic_pointer_cast(*iter); assert(cf); cf->setOrigTarget(target); } diff --git a/dyninstAPI/src/Relocation/Transformers/Movement-adhoc.h b/dyninstAPI/src/Relocation/Transformers/Movement-adhoc.h index d5b6ddb988..871b56884d 100644 --- a/dyninstAPI/src/Relocation/Transformers/Movement-adhoc.h +++ b/dyninstAPI/src/Relocation/Transformers/Movement-adhoc.h @@ -33,9 +33,11 @@ class AddressSpace; +#include +#include #include "Transformer.h" -#include "dataflowAPI/h/Absloc.h" // MemEmulator analysis +#include "dataflowAPI/h/Absloc.h" #include "dyninstAPI/src/function.h" @@ -49,8 +51,8 @@ class RelocInsn; // Identify PC-relative memory accesses and replace // them with a dedicated Widget class adhocMovementTransformer : public Transformer { - typedef boost::shared_ptr RelocInsnPtr; - typedef boost::shared_ptr InsnPtr; + typedef dyncompat::shared_ptr RelocInsnPtr; + typedef dyncompat::shared_ptr InsnPtr; public: virtual bool process(RelocBlock *, RelocGraph *); diff --git a/dyninstAPI/src/Relocation/Transformers/Movement-analysis.C b/dyninstAPI/src/Relocation/Transformers/Movement-analysis.C index 0a5bef259b..25d26a516a 100644 --- a/dyninstAPI/src/Relocation/Transformers/Movement-analysis.C +++ b/dyninstAPI/src/Relocation/Transformers/Movement-analysis.C @@ -30,10 +30,11 @@ +#include #include "Transformer.h" #include "Movement-analysis.h" #include "Modification.h" -#include "../dyninstAPI/src/debug.h" +#include "dyninstAPI/src/debug.h" #include "../Widgets/Widget.h" #include "dyninstAPI/src/function.h" #include "../Widgets/CFWidget.h" @@ -44,9 +45,9 @@ #include "dyninstAPI/src/mapped_object.h" #include "instructionAPI/h/InstructionDecoder.h" #include "dyninstAPI/src/instPoint.h" - +#include "registers/x86_regs.h" #include "dataflowAPI/h/slicing.h" - +#include "instructionAPI/h/syscalls.h" #include "../CFG/RelocBlock.h" #include "../CFG/RelocGraph.h" @@ -121,7 +122,7 @@ bool PCSensitiveTransformer::process(RelocBlock *reloc, RelocGraph *g) { // 2) Is it externally sensitive... will this instruction cause the program // to produce a different result. - if (isSyscall(insn, addr)) { + if (Dyninst::InstructionAPI::isSystemCall(insn)) { continue; } @@ -388,7 +389,7 @@ bool PCSensitiveTransformer::determineSensitivity(Graph::Ptr slice, slice->exitNodes(exitBegin, exitEnd); for (; exitBegin != exitEnd; ++exitBegin) { - SliceNode::Ptr aNode = boost::static_pointer_cast(*exitBegin); + SliceNode::Ptr aNode = dyncompat::static_pointer_cast(*exitBegin); // By definition, a widen point is potentially behavior changing. if (Slicer::isWidenNode(*exitBegin)) { @@ -562,7 +563,7 @@ void PCSensitiveTransformer::emulateInsn(RelocBlock *reloc, } else { //cerr << "... end of block" << endl; - CFWidget::Ptr cf = boost::dynamic_pointer_cast(*iter); + CFWidget::Ptr cf = dyncompat::dynamic_pointer_cast(*iter); // We don't want to be doing this pre-CF-creation... assert(cf); @@ -882,15 +883,3 @@ bool ExtPCSensVisitor::isExtSens(AST::Ptr a) { return (diffs_.top().b != 0); } } - -bool PCSensitiveTransformer::isSyscall(Instruction insn, Address) { - // call *%gs:0x10 - // Build a GS - static Expression::Ptr x86_gs(new RegisterAST(x86::gs)); - - if (insn.isRead(x86_gs)) { - //relocation_cerr << "Skipping syscall " << insn->format() << hex << "@ " << addr << dec << endl; - return true; - } - return false; -} diff --git a/dyninstAPI/src/Relocation/Transformers/Movement-analysis.h b/dyninstAPI/src/Relocation/Transformers/Movement-analysis.h index add95fdaa7..54512aed98 100644 --- a/dyninstAPI/src/Relocation/Transformers/Movement-analysis.h +++ b/dyninstAPI/src/Relocation/Transformers/Movement-analysis.h @@ -31,10 +31,13 @@ #if !defined(_R_T_MOVEMENT_ANALYSIS_H_) #define _R_T_MOVEMENT_ANALYSIS_H_ +#include +#include +#include #include "Transformer.h" #include "dyninstAPI/src/LinearVariable.h" -#include "dataflowAPI/h/Absloc.h" // MemEmulator analysis +#include "dataflowAPI/h/Absloc.h" #include "dataflowAPI/h/AbslocInterface.h" // And more of the same #include "common/h/Graph.h" // PC-sensitive transformer @@ -90,14 +93,14 @@ class ExtPCSensVisitor : public ASTVisitor { }; class PCSensitiveTransformer : public Transformer { - typedef boost::shared_ptr RelocInsnPtr; + typedef dyncompat::shared_ptr RelocInsnPtr; typedef std::list AssignList; public: virtual bool process(RelocBlock *, RelocGraph *); - PCSensitiveTransformer(AddressSpace *as, PriorityMap &p) - : aConverter(false, false), addrSpace(as), priMap(p), + PCSensitiveTransformer(AddressSpace *as, PriorityMap &) + : aConverter(false, false), addrSpace(as), Sens_(0), extSens_(0), intSens_(0), thunk_(0), overApprox_(0), adhoc(as) {} virtual ~PCSensitiveTransformer() {} @@ -134,8 +137,6 @@ class PCSensitiveTransformer : public Transformer { bool exceptionSensitive(Address addr, const block_instance *bbl); - bool isSyscall(InstructionAPI::Instruction insn, Address addr); - static void cacheAnalysis(const block_instance *bbl, Address addr, bool intSens, bool extSens); static bool queryCache(const block_instance *bbl, Address addr, bool &intSens, bool &extSens); @@ -144,8 +145,6 @@ class PCSensitiveTransformer : public Transformer { AddressSpace *addrSpace; - PriorityMap &priMap; - long Sens_; long extSens_; long intSens_; diff --git a/dyninstAPI/src/Relocation/Transformers/Transformer.C b/dyninstAPI/src/Relocation/Transformers/Transformer.C index 219d21878b..d68a1f2eae 100644 --- a/dyninstAPI/src/Relocation/Transformers/Transformer.C +++ b/dyninstAPI/src/Relocation/Transformers/Transformer.C @@ -34,6 +34,8 @@ #include "dyninstAPI/src/Relocation/CFG/RelocBlock.h" #include "dyninstAPI/src/Relocation/CFG/RelocTarget.h" #include "../CFG/RelocGraph.h" +#include "dyninstAPI/src/function.h" +#include "dyninstAPI/src/mapped_module.h" using namespace Dyninst; using namespace Relocation; @@ -41,10 +43,20 @@ using namespace Relocation; bool Transformer::processGraph(RelocGraph *cfg) { for (RelocBlock *cur = cfg->head; cur != NULL; cur = cur->next()) { if (!process(cur, cfg)) { - cerr << "Failed to transform trace " << cur->id() << endl; + cerr << "Failed to transform trace " << cur->id(); + if (cur->func()) { + cerr << " in function '" << cur->func()->prettyName() << "'"; + if (cur->func()->mod()) + cerr << " in module '" << cur->func()->mod()->fileName() << "'"; + if (cur->func()->obj()) + cerr << " in object '" << cur->func()->obj()->fileName() << "'"; + } + auto savedFlags = cerr.flags(); + cerr << " at address " << showbase << hex << cur->origAddr(); + cerr.flags(savedFlags); + cerr << endl; return false; } } return true; } - diff --git a/dyninstAPI/src/Relocation/Transformers/Transformer.h b/dyninstAPI/src/Relocation/Transformers/Transformer.h index 9ae59fdffd..6fb0623c97 100644 --- a/dyninstAPI/src/Relocation/Transformers/Transformer.h +++ b/dyninstAPI/src/Relocation/Transformers/Transformer.h @@ -31,12 +31,11 @@ #if !defined(_R_T_BASE_H_) #define _R_T_BASE_H_ -#include "common/src/Types.h" // Address #include #include #include #include "parseAPI/h/CFG.h" -#include "boost/shared_ptr.hpp" +#include "dyncompat/shared_ptr.hpp" class block_instance; class baseTramp; @@ -67,7 +66,7 @@ class RelocGraph; class Transformer { public: - typedef boost::shared_ptr WidgetPtr; + typedef dyncompat::shared_ptr WidgetPtr; typedef std::list WidgetList; typedef std::map RelocBlockMap; diff --git a/dyninstAPI/src/Relocation/Widgets/ASTWidget.C b/dyninstAPI/src/Relocation/Widgets/ASTWidget.C index 1890a02e16..0e46b01d73 100644 --- a/dyninstAPI/src/Relocation/Widgets/ASTWidget.C +++ b/dyninstAPI/src/Relocation/Widgets/ASTWidget.C @@ -30,12 +30,13 @@ #include "ASTWidget.h" #include "dyninstAPI/src/ast.h" -#include "../dyninstAPI/src/debug.h" +#include "dyninstAPI/src/debug.h" #include "dyninstAPI/src/registerSpace.h" #include "dyninstAPI/src/instPoint.h" #include "../CodeBuffer.h" #include "CFG.h" #include +#include #include "../CodeTracker.h" using namespace Dyninst; @@ -64,7 +65,7 @@ std::string ASTWidget::format() const { // Could be a lot smarter here... bool AstPatch::apply(codeGen &gen, CodeBuffer *) { - relocation_cerr << "\t\t AstPatch::apply" << endl; + relocation_cerr << "\t\t AstPatch::apply" << std::endl; registerSpace *localRegSpace = registerSpace::actualRegSpace(point); gen.setRegisterSpace(localRegSpace); diff --git a/dyninstAPI/src/Relocation/Widgets/ASTWidget.h b/dyninstAPI/src/Relocation/Widgets/ASTWidget.h index b32aec9985..773d89ee3a 100644 --- a/dyninstAPI/src/Relocation/Widgets/ASTWidget.h +++ b/dyninstAPI/src/Relocation/Widgets/ASTWidget.h @@ -31,10 +31,11 @@ #if !defined (_R_E_AST_H_) #define _R_E_AST_H_ +#include #include "Widget.h" class AstNode; -typedef boost::shared_ptr AstNodePtr; +typedef dyncompat::shared_ptr AstNodePtr; class instPoint; namespace Dyninst { @@ -42,7 +43,7 @@ namespace Relocation { class ASTWidget : public Widget { public: - typedef boost::shared_ptr Ptr; + typedef dyncompat::shared_ptr Ptr; static Ptr create(AstNodePtr, instPoint *); diff --git a/dyninstAPI/src/Relocation/Widgets/CFWidget-aarch64.C b/dyninstAPI/src/Relocation/Widgets/CFWidget-aarch64.C index 5de3d558cd..83da67ebde 100644 --- a/dyninstAPI/src/Relocation/Widgets/CFWidget-aarch64.C +++ b/dyninstAPI/src/Relocation/Widgets/CFWidget-aarch64.C @@ -35,7 +35,7 @@ #include "instructionAPI/h/Instruction.h" -#include "../dyninstAPI/src/debug.h" +#include "dyninstAPI/src/debug.h" #include "../CodeTracker.h" #include "../CodeBuffer.h" @@ -219,16 +219,3 @@ bool CFPatch::handleTOCUpdate(codeGen &gen) { } */ -bool CFWidget::generateAddressTranslator(CodeBuffer &/*buffer*/, - const codeGen &/*templ*/, - Register &/*reg*/, - const RelocBlock */*trace*/) { -#if !defined(cap_mem_emulation) - return true; -#else - assert(0); - return false; -#endif - -} - diff --git a/dyninstAPI/src/Relocation/Widgets/CFWidget-ppc.C b/dyninstAPI/src/Relocation/Widgets/CFWidget-ppc.C index b9bab37c04..2442eb5646 100644 --- a/dyninstAPI/src/Relocation/Widgets/CFWidget-ppc.C +++ b/dyninstAPI/src/Relocation/Widgets/CFWidget-ppc.C @@ -35,7 +35,7 @@ #include "instructionAPI/h/Instruction.h" -#include "../dyninstAPI/src/debug.h" +#include "dyninstAPI/src/debug.h" #include "../CodeTracker.h" #include "../CodeBuffer.h" @@ -283,18 +283,3 @@ bool CFPatch::handleTOCUpdate(codeGen &gen) { return false; } } - -bool CFWidget::generateAddressTranslator(CodeBuffer & /*buffer*/, - const codeGen & /*templ*/, - Register & /*reg*/, - const RelocBlock * /*trace*/) -{ -#if !defined(cap_mem_emulation) - return true; -#else - assert(0); - return false; -#endif - -} - diff --git a/dyninstAPI/src/Relocation/Widgets/CFWidget-x86.C b/dyninstAPI/src/Relocation/Widgets/CFWidget-x86.C index 0cb91f46ec..b1f9f4e434 100644 --- a/dyninstAPI/src/Relocation/Widgets/CFWidget-x86.C +++ b/dyninstAPI/src/Relocation/Widgets/CFWidget-x86.C @@ -29,13 +29,14 @@ */ // x86-specific methods for generating control flow +#include #include "CFWidget.h" #include "Widget.h" #include "../CFG/RelocTarget.h" #include "instructionAPI/h/Instruction.h" -#include "../dyninstAPI/src/debug.h" +#include "dyninstAPI/src/debug.h" #include "../CodeTracker.h" #include "../CodeBuffer.h" @@ -46,10 +47,6 @@ #include "dyninstAPI/src/inst-x86.h" #include "dyninstAPI/h/BPatch_memoryAccess_NP.h" -#if defined(cap_mem_emulation) -#include "dyninstAPI/src/MemoryEmulator/memEmulatorWidget.h" -#endif - using namespace Dyninst; using namespace Relocation; using namespace InstructionAPI; @@ -293,113 +290,3 @@ bool CFPatch::applyPLT(codeGen &gen, CodeBuffer *) { return true; } - -#if !defined(cap_mem_emulation) -bool CFWidget::generateAddressTranslator(CodeBuffer &,const codeGen &,Register &,const RelocBlock *) { - return true; -} -#else -bool CFWidget::generateAddressTranslator(CodeBuffer &buffer, - const codeGen &templ, - Register ®, - const RelocBlock *trace) -{ - if (!templ.addrSpace()->isMemoryEmulated() || - BPatch_defensiveMode != trace->block()->obj()->hybridMode()) - return true; - - if (insn_->getOperation().getID() == e_ret_near || - insn_->getOperation().getID() == e_ret_far) { - // Oops! - return true; - } - if (!insn_->readsMemory()) { - return true; - } - - BPatch_memoryAccessAdapter converter; - BPatch_memoryAccess *acc = converter.convert(insn_, addr_, false); - if (!acc) { - reg = Null_Register; - return true; - } - - codeGen patch(128); - patch.applyTemplate(templ); - - // TODO: we probably want this in a form that doesn't stomp the stack... - // But we can probably get away with this for now. Check that. - - // step 1: create space on the stack. - ::emitPush(RealRegister(REGNUM_EAX), patch); - - // step 2: save registers that will be affected by the call - ::emitPush(RealRegister(REGNUM_ECX), patch); - ::emitPush(RealRegister(REGNUM_EDX), patch); - ::emitPush(RealRegister(REGNUM_EAX), patch); - - // Step 3: LEA this sucker into ECX. - const BPatch_addrSpec_NP *start = acc->getStartAddr(0); - if (start->getReg(0) == REGNUM_ESP || - start->getReg(1) == REGNUM_ESP) { - cerr << "ERROR: CF insn that uses the stack pointer! " << insn_->format() << endl; - } - - int stackShift = -16; - // If we are a call _instruction_ but isCall is false, then we've got an extra word - // on the stack from an emulated return address - if (!isCall_ && insn_->getCategory() == c_CallInsn) stackShift -= 4; - - emitASload(start, REGNUM_ECX, stackShift, patch, true); - - // Step 4: save flags post-LEA - emitSimpleInsn(0x9f, patch); - emitSaveO(patch); - ::emitPush(RealRegister(REGNUM_EAX), patch); - - // This might look a lot like a memEmulatorWidget. That's, well, because it - // is. - buffer.addPIC(patch, tracker(trace)); - - // Where are we going? - func_instance *func = templ.addrSpace()->findOnlyOneFunction("RTtranslateMemory"); - // FIXME for static rewriting; this is a dynamic-only hack for proof of concept. - assert(func); - - // Now we start stealing from memEmulatorWidget. We need to call our translation function, - // which means a non-PIC patch to the CodeBuffer. I don't feel like rewriting everything, - // so there we go. - buffer.addPatch(new MemEmulatorPatch(REGNUM_ECX, REGNUM_ECX, addr_, func->addr()), - tracker(trace)); - patch.setIndex(0); - - // Restore flags - ::emitPop(RealRegister(REGNUM_EAX), patch); - emitRestoreO(patch); - emitSimpleInsn(0x9E, patch); - ::emitPop(RealRegister(REGNUM_EAX), patch); - ::emitPop(RealRegister(REGNUM_EDX), patch); - - // ECX now holds the pointer to the destination... - // Dereference - ::emitMovRMToReg(RealRegister(REGNUM_ECX), - RealRegister(REGNUM_ECX), - 0, - patch); - - // ECX now holds the _actual_ destination, so move it on to the stack. - // We've got ECX saved - ::emitMovRegToRM(RealRegister(REGNUM_ESP), - 1*4, - RealRegister(REGNUM_ECX), - patch); - ::emitPop(RealRegister(REGNUM_ECX), patch); - // And tell our people to use the top of the stack - // for their work. - // TODO: trust liveness and leave this in a register. - - buffer.addPIC(patch, tracker(trace)); - reg = REGNUM_ESP; - return true; -} -#endif diff --git a/dyninstAPI/src/Relocation/Widgets/CFWidget.C b/dyninstAPI/src/Relocation/Widgets/CFWidget.C index e1b2e6e1ca..91935966b4 100644 --- a/dyninstAPI/src/Relocation/Widgets/CFWidget.C +++ b/dyninstAPI/src/Relocation/Widgets/CFWidget.C @@ -28,6 +28,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include "CFWidget.h" #include "Widget.h" #include "../CFG/RelocTarget.h" @@ -38,15 +39,7 @@ #include "dyninstAPI/src/inst-x86.h" #include "dyninstAPI/src/debug.h" -#if defined(cap_mem_emulation) -#include "dyninstAPI/src/MemoryEmulator/memEmulatorWidget.h" -#include "dyninstAPI/src/BPatch_memoryAccessAdapter.h" -#include "dyninstAPI/h/BPatch_memoryAccess_NP.h" -#include "dyninstAPI/src/MemoryEmulator/memEmulatorWidget.h" -#include "dyninstAPI/src/registerSpace.h" -#endif - -#include "../dyninstAPI/src/debug.h" +#include "dyninstAPI/src/debug.h" #include "../CodeTracker.h" #include "../CodeBuffer.h" @@ -133,7 +126,7 @@ CFWidget::CFWidget(InstructionAPI::Instruction insn, Address addr) : } -bool CFWidget::generate(const codeGen &templ, +bool CFWidget::generate(const codeGen &, const RelocBlock *trace, CodeBuffer &buffer) { @@ -269,10 +262,7 @@ bool CFWidget::generate(const codeGen &templ, } case Indirect: { Register reg = Null_Register; /* = originalRegister... */ - // Originally for use in helping with jump tables, I'm taking - // this for the memory emulation effort. Huzzah! - if (!generateAddressTranslator(buffer, templ, reg, trace)) - return false; + // If this is an indirect tail call, we still treat it // as an indirect call if (isCall_ || trace->block()->llb()->isIndirectTailCallBlock()) { diff --git a/dyninstAPI/src/Relocation/Widgets/CFWidget.h b/dyninstAPI/src/Relocation/Widgets/CFWidget.h index e9a4cd714a..1a39cc10db 100644 --- a/dyninstAPI/src/Relocation/Widgets/CFWidget.h +++ b/dyninstAPI/src/Relocation/Widgets/CFWidget.h @@ -31,6 +31,8 @@ #if !defined (_R_E_CONTROL_FLOW_H_) #define _R_E_CONTROL_FLOW_H_ +#include +#include #include "Widget.h" class block_instance; @@ -81,7 +83,7 @@ class CFWidget : public Widget { static const Address Fallthrough; static const Address Taken; - typedef boost::shared_ptr Ptr; + typedef dyncompat::shared_ptr Ptr; typedef std::map DestinationMap; static Ptr create(Address addr); @@ -187,12 +189,6 @@ class CFWidget : public Widget { InstructionAPI::Instruction insn, const RelocBlock *trace, Address origAddr); - - bool generateAddressTranslator(CodeBuffer &buffer, - const codeGen &templ, - Register ®, - const RelocBlock *trace); - }; struct CFPatch : public Patch { diff --git a/dyninstAPI/src/Relocation/Widgets/CallbackWidget.C b/dyninstAPI/src/Relocation/Widgets/CallbackWidget.C index 5b3e198900..5c16d11971 100644 --- a/dyninstAPI/src/Relocation/Widgets/CallbackWidget.C +++ b/dyninstAPI/src/Relocation/Widgets/CallbackWidget.C @@ -29,7 +29,7 @@ */ #include "CallbackWidget.h" -#include "../dyninstAPI/src/debug.h" +#include "dyninstAPI/src/debug.h" #include "CFG.h" #include "../CodeTracker.h" diff --git a/dyninstAPI/src/Relocation/Widgets/CallbackWidget.h b/dyninstAPI/src/Relocation/Widgets/CallbackWidget.h index 242720d3a6..fde3395cb9 100644 --- a/dyninstAPI/src/Relocation/Widgets/CallbackWidget.h +++ b/dyninstAPI/src/Relocation/Widgets/CallbackWidget.h @@ -31,6 +31,7 @@ #if !defined (_R_E_CALLBACK_H_) #define _R_E_CALLBACK_H_ +#include #include "Widget.h" @@ -41,7 +42,7 @@ struct Patch; class CallbackWidget : public Widget { public: - typedef boost::shared_ptr Ptr; + typedef dyncompat::shared_ptr Ptr; // I believe I can patch in the current code generation // system here... diff --git a/dyninstAPI/src/Relocation/Widgets/InsnWidget.h b/dyninstAPI/src/Relocation/Widgets/InsnWidget.h index 988a9e6fca..2b3baf44a8 100644 --- a/dyninstAPI/src/Relocation/Widgets/InsnWidget.h +++ b/dyninstAPI/src/Relocation/Widgets/InsnWidget.h @@ -31,6 +31,7 @@ #if !defined (_PATCHAPI_INSN_ATOM_H_) #define _PATCHAPI_INSN_ATOM_H_ +#include #include "Widget.h" class block_instance; @@ -41,7 +42,7 @@ namespace Relocation { class InsnWidget : public Widget { public: - typedef boost::shared_ptr Ptr; + typedef dyncompat::shared_ptr Ptr; virtual bool generate(const codeGen &, const RelocBlock *, diff --git a/dyninstAPI/src/Relocation/Widgets/InstWidget.C b/dyninstAPI/src/Relocation/Widgets/InstWidget.C index 8491436bcf..72bb059da2 100644 --- a/dyninstAPI/src/Relocation/Widgets/InstWidget.C +++ b/dyninstAPI/src/Relocation/Widgets/InstWidget.C @@ -31,12 +31,13 @@ #include "InstWidget.h" #include "dyninstAPI/src/baseTramp.h" #include "dyninstAPI/src/instPoint.h" -#include "../dyninstAPI/src/debug.h" +#include "dyninstAPI/src/debug.h" #include "CFG.h" #include "../CodeTracker.h" #include "../CodeBuffer.h" #include +#include using namespace Dyninst; using namespace Relocation; @@ -82,7 +83,7 @@ std::string InstWidget::format() const { // Could be a lot smarter here... bool InstWidgetPatch::apply(codeGen &gen, CodeBuffer *) { - relocation_cerr << "\t\t InstWidgetPatch::apply " << this << " /w/ tramp " << tramp << endl; + relocation_cerr << "\t\t InstWidgetPatch::apply " << this << " /w/ tramp " << tramp << std::endl; gen.registerInstrumentation(tramp, gen.currAddr()); bool ret = tramp->generateCode(gen, gen.currAddr()); diff --git a/dyninstAPI/src/Relocation/Widgets/InstWidget.h b/dyninstAPI/src/Relocation/Widgets/InstWidget.h index 2cdc5e5325..2cd182a1c9 100644 --- a/dyninstAPI/src/Relocation/Widgets/InstWidget.h +++ b/dyninstAPI/src/Relocation/Widgets/InstWidget.h @@ -31,6 +31,7 @@ #if !defined (_R_E_INSTRUMENTATION_H_) #define _R_E_INSTRUMENTATION_H_ +#include #include "Widget.h" class instPoint; @@ -40,7 +41,7 @@ namespace Relocation { class InstWidget : public Widget { public: - typedef boost::shared_ptr Ptr; + typedef dyncompat::shared_ptr Ptr; // I believe I can patch in the current code generation // system here... diff --git a/dyninstAPI/src/Relocation/Widgets/PCWidget-aarch64.C b/dyninstAPI/src/Relocation/Widgets/PCWidget-aarch64.C index e758fa4b02..9458e6baff 100644 --- a/dyninstAPI/src/Relocation/Widgets/PCWidget-aarch64.C +++ b/dyninstAPI/src/Relocation/Widgets/PCWidget-aarch64.C @@ -30,7 +30,7 @@ #include "PCWidget.h" #include "instructionAPI/h/Instruction.h" -#include "../dyninstAPI/src/debug.h" +#include "dyninstAPI/src/debug.h" #include "../CFG/RelocBlock.h" #include "../CodeBuffer.h" #include "../CodeTracker.h" diff --git a/dyninstAPI/src/Relocation/Widgets/PCWidget-ppc.C b/dyninstAPI/src/Relocation/Widgets/PCWidget-ppc.C index d1ce8ed893..af352c5d54 100644 --- a/dyninstAPI/src/Relocation/Widgets/PCWidget-ppc.C +++ b/dyninstAPI/src/Relocation/Widgets/PCWidget-ppc.C @@ -30,7 +30,7 @@ #include "PCWidget.h" #include "instructionAPI/h/Instruction.h" -#include "../dyninstAPI/src/debug.h" +#include "dyninstAPI/src/debug.h" #include "../CFG/RelocBlock.h" #include "../CodeBuffer.h" #include "../CodeTracker.h" @@ -71,7 +71,7 @@ bool PCWidget::PCtoReturnAddr(const codeGen &templ, const RelocBlock *t, CodeBuf Address origRet = addr() + insn_.size(); Register scratch = gen.rs()->getScratchRegister(gen, true); bool createFrame = false; - if (scratch == REG_NULL) { + if (scratch == Null_Register) { stackSize = insnCodeGen::createStackFrame(gen, 1, freeReg, excludeReg); assert(stackSize == 1); scratch = freeReg[0]; @@ -138,14 +138,14 @@ bool IPPatch::apply(codeGen &gen, CodeBuffer *) { excludeReg.push_back(scratchPCReg); Register scratchReg = gen.rs()->getScratchRegister(gen, excludeReg, true); - if ((scratchPCReg == REG_NULL) && (scratchReg == REG_NULL)) { + if ((scratchPCReg == Null_Register) && (scratchReg == Null_Register)) { excludeReg.clear(); stackSize = insnCodeGen::createStackFrame(gen, 2, freeReg, excludeReg); assert(stackSize == 2); scratchPCReg = freeReg[0]; scratchReg = freeReg[1]; - } else if (scratchReg == REG_NULL && scratchPCReg != REG_NULL) { + } else if (scratchReg == Null_Register && scratchPCReg != Null_Register) { stackSize = insnCodeGen::createStackFrame(gen, 1, freeReg, excludeReg); assert(stackSize == 1); scratchReg = freeReg[0]; diff --git a/dyninstAPI/src/Relocation/Widgets/PCWidget-x86.C b/dyninstAPI/src/Relocation/Widgets/PCWidget-x86.C index 0b574b12cf..ced8d5f752 100644 --- a/dyninstAPI/src/Relocation/Widgets/PCWidget-x86.C +++ b/dyninstAPI/src/Relocation/Widgets/PCWidget-x86.C @@ -30,7 +30,7 @@ #include "PCWidget.h" #include "instructionAPI/h/Instruction.h" -#include "../dyninstAPI/src/debug.h" +#include "dyninstAPI/src/debug.h" #include "../CFG/RelocBlock.h" #include "../CodeBuffer.h" #include "../CodeTracker.h" @@ -42,6 +42,10 @@ #include "dyninstAPI/src/emitter.h" +#include "unaligned_memory_access.h" +#include +#include + using namespace Dyninst; using namespace Relocation; using namespace InstructionAPI; @@ -108,29 +112,23 @@ bool IPPatch::apply(codeGen &gen, CodeBuffer *) { // Emit a call to the next instruction to get current PC // This is necessary for PIC code GET_PTR(newInsn, gen); - *newInsn = 0xE8; - newInsn++; - unsigned int *temp = (uint32_t *) newInsn; - *temp = 0; - newInsn += sizeof(uint32_t); + append_memory_as_byte(newInsn, 0xE8); + append_memory_as(newInsn, uint32_t{0}); SET_PTR(newInsn, gen); // Compensating PC on stack to the original location - Address offset = addr - gen.currAddr() + insn.size(); + int64_t offset = addr - gen.currAddr() + insn.size(); REGET_PTR(newInsn, gen); - *newInsn = 0x81; - newInsn++; - *newInsn = 0x04; - newInsn++; - *newInsn = 0x24; - newInsn++; - temp = (uint32_t *) newInsn; - *temp = offset; - newInsn += sizeof(uint32_t); + append_memory_as_byte(newInsn, 0x81); + append_memory_as_byte(newInsn, 0x04); + append_memory_as_byte(newInsn, 0x24); + // offset is 64-bits, assert if the value does not fit in 32-bits + assert(numeric_limits::lowest() <= offset && offset <= numeric_limits::max() && "offset more than 32 bits"); + append_memory_as(newInsn, static_cast(offset)); if (type == Reg) { assert(reg != (Register) -1); // pop... - *newInsn++ = static_cast(0x58 + reg); // POP family + append_memory_as_byte(newInsn, 0x58 + reg); // POP family } SET_PTR(newInsn, gen); return true; diff --git a/dyninstAPI/src/Relocation/Widgets/PCWidget.C b/dyninstAPI/src/Relocation/Widgets/PCWidget.C index e08d613457..62fd65542b 100644 --- a/dyninstAPI/src/Relocation/Widgets/PCWidget.C +++ b/dyninstAPI/src/Relocation/Widgets/PCWidget.C @@ -30,7 +30,7 @@ #include "PCWidget.h" #include "instructionAPI/h/Instruction.h" -#include "../dyninstAPI/src/debug.h" +#include "dyninstAPI/src/debug.h" #include "../CFG/RelocBlock.h" #include "../CodeBuffer.h" #include "../CodeTracker.h" diff --git a/dyninstAPI/src/Relocation/Widgets/PCWidget.h b/dyninstAPI/src/Relocation/Widgets/PCWidget.h index 16c46d4cb9..45f01ec292 100644 --- a/dyninstAPI/src/Relocation/Widgets/PCWidget.h +++ b/dyninstAPI/src/Relocation/Widgets/PCWidget.h @@ -31,9 +31,10 @@ #if !defined (_PATCHAPI_PC_ATOM_H_) #define _PATCHAPI_PC_ATOM_H_ -#include "Widget.h" +#include -// Define where the PC value is supposed to go +#include "dyn_register.h" +#include "Widget.h" #include "dataflowAPI/h/Absloc.h" class block_instance; @@ -44,7 +45,7 @@ namespace Relocation { class PCWidget : public Widget { public: - typedef boost::shared_ptr Ptr; + typedef dyncompat::shared_ptr Ptr; static Ptr create(InstructionAPI::Instruction insn, Address addr, diff --git a/dyninstAPI/src/Relocation/Widgets/RelDataWidget.C b/dyninstAPI/src/Relocation/Widgets/RelDataWidget.C index 9afa5e8d85..34684d1119 100644 --- a/dyninstAPI/src/Relocation/Widgets/RelDataWidget.C +++ b/dyninstAPI/src/Relocation/Widgets/RelDataWidget.C @@ -31,7 +31,7 @@ #include #include "RelDataWidget.h" #include "instructionAPI/h/Instruction.h" -#include "../dyninstAPI/src/debug.h" +#include "dyninstAPI/src/debug.h" #include "CFG.h" #include "../CFG/RelocBlock.h" diff --git a/dyninstAPI/src/Relocation/Widgets/RelDataWidget.h b/dyninstAPI/src/Relocation/Widgets/RelDataWidget.h index 91bf9a5f3e..8ab2184a3a 100644 --- a/dyninstAPI/src/Relocation/Widgets/RelDataWidget.h +++ b/dyninstAPI/src/Relocation/Widgets/RelDataWidget.h @@ -31,6 +31,7 @@ #if !defined (_PATCHAPI_REL_DATA_ATOM_H_) #define _PATCHAPI_REL_DATA_ATOM_H_ +#include #include "Widget.h" class block_instance; @@ -41,7 +42,7 @@ namespace Relocation { class RelDataWidget : public Widget { public: - typedef boost::shared_ptr Ptr; + typedef dyncompat::shared_ptr Ptr; virtual bool generate(const codeGen &, const RelocBlock *, CodeBuffer &); @@ -82,12 +83,12 @@ struct RelDataPatch : public Patch { void setBlock(block_instance *_block) { block = _block; } InstructionAPI::Instruction orig_insn; - Address target_addr; - Address orig; + Address target_addr{}; + Address orig{}; private: - func_instance *func; - block_instance *block; + func_instance *func{}; + block_instance *block{}; }; diff --git a/dyninstAPI/src/Relocation/Widgets/StackModWidget.C b/dyninstAPI/src/Relocation/Widgets/StackModWidget.C index 854ad737f6..229a1d3428 100644 --- a/dyninstAPI/src/Relocation/Widgets/StackModWidget.C +++ b/dyninstAPI/src/Relocation/Widgets/StackModWidget.C @@ -30,7 +30,7 @@ #include "StackModWidget.h" #include "instructionAPI/h/Instruction.h" -#include "../dyninstAPI/src/debug.h" +#include "dyninstAPI/src/debug.h" #include "CFG.h" #include "../CFG/RelocBlock.h" diff --git a/dyninstAPI/src/Relocation/Widgets/StackModWidget.h b/dyninstAPI/src/Relocation/Widgets/StackModWidget.h index cbfd893602..8c7d633c6b 100644 --- a/dyninstAPI/src/Relocation/Widgets/StackModWidget.h +++ b/dyninstAPI/src/Relocation/Widgets/StackModWidget.h @@ -31,6 +31,7 @@ #ifndef _STACKMODWIDGET_H_ #define _STACKMODWIDGET_H_ +#include #include "Widget.h" class block_instance; @@ -39,7 +40,7 @@ namespace Relocation { class StackModWidget : public Widget { public: - typedef boost::shared_ptr Ptr; + typedef dyncompat::shared_ptr Ptr; virtual bool generate(const codeGen &, const RelocBlock *, CodeBuffer &); diff --git a/dyninstAPI/src/Relocation/Widgets/Widget.h b/dyninstAPI/src/Relocation/Widgets/Widget.h index 04b012e1d5..1a8c9260fb 100644 --- a/dyninstAPI/src/Relocation/Widgets/Widget.h +++ b/dyninstAPI/src/Relocation/Widgets/Widget.h @@ -31,8 +31,8 @@ #if !defined(PATCHAPI_ATOM_H_) #define PATCHAPI_ATOM_H_ -#include "common/src/Types.h" // Address #include "instructionAPI/h/Instruction.h" // Instruction::Ptr +#include #include // stl::list class baseTramp; @@ -58,8 +58,8 @@ class CodeBuffer; class Widget { friend class Transformer; public: - typedef boost::shared_ptr Ptr; - typedef boost::shared_ptr RelocBlockPtr; + typedef dyncompat::shared_ptr Ptr; + typedef dyncompat::shared_ptr RelocBlockPtr; Widget() {} diff --git a/dyninstAPI/src/StackMod/OffsetVector.C b/dyninstAPI/src/StackMod/OffsetVector.C index 0460a38679..52410333db 100644 --- a/dyninstAPI/src/StackMod/OffsetVector.C +++ b/dyninstAPI/src/StackMod/OffsetVector.C @@ -28,6 +28,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include "debug.h" #include "OffsetVector.h" diff --git a/dyninstAPI/src/StackMod/OffsetVector.h b/dyninstAPI/src/StackMod/OffsetVector.h index 2ada9037d5..1f471fa4cd 100644 --- a/dyninstAPI/src/StackMod/OffsetVector.h +++ b/dyninstAPI/src/StackMod/OffsetVector.h @@ -31,7 +31,10 @@ #ifndef _OFFSETVECTOR_H_ #define _OFFSETVECTOR_H_ -#include "dyn_regs.h" +#include +#include +#include +#include "registers/MachRegister.h" #include "common/src/IntervalTree.h" #include "stackanalysis.h" diff --git a/dyninstAPI/src/StackMod/StackAccess.C b/dyninstAPI/src/StackMod/StackAccess.C index dbd20d0696..a053d2e3f3 100644 --- a/dyninstAPI/src/StackMod/StackAccess.C +++ b/dyninstAPI/src/StackMod/StackAccess.C @@ -28,6 +28,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include #include "debug.h" @@ -36,14 +37,14 @@ #include "InstructionCategories.h" #include "InstructionDecoder.h" #include "Expression.h" -#include "Register.h" #include "Result.h" #include "Dereference.h" #include "Immediate.h" #include "BinaryFunction.h" #include "CFG.h" - +#include "registers/x86_regs.h" +#include "registers/x86_64_regs.h" #include "ABI.h" #include "slicing.h" #include "SymEval.h" @@ -56,23 +57,23 @@ using namespace Dyninst; std::string StackAccess::printStackAccessType(StackAccess::StackAccessType t) { switch(t) { - case(StackAccess::READ): + case StackAccess::StackAccessType::READ: return "READ"; - case(StackAccess::WRITE): + case StackAccess::StackAccessType::WRITE: return "WRITE"; - case(StackAccess::SAVED): + case StackAccess::StackAccessType::SAVED: return "SAVED"; - case(StackAccess::READWRITE): + case StackAccess::StackAccessType::READWRITE: return "READWRITE"; - case(StackAccess::REGHEIGHT): + case StackAccess::StackAccessType::REGHEIGHT: return "REGHEIGHT"; - case(StackAccess::DEBUGINFO_LOCAL): + case StackAccess::StackAccessType::DEBUGINFO_LOCAL: return "DEBUGINFO_LOCAL"; - case(StackAccess::DEBUGINFO_PARAM): + case StackAccess::StackAccessType::DEBUGINFO_PARAM: return "DEBUGINFO_PARAM"; - case(StackAccess::UNKNOWN): + case StackAccess::StackAccessType::UNKNOWN: return "UNKNOWN"; - case (StackAccess::MISUNDERSTOOD): + case StackAccess::StackAccessType::MISUNDERSTOOD: return "MISUNDERSTOOD"; default: return "NOT RECOGNIZED ACCESS TYPE"; @@ -93,8 +94,8 @@ std::string StackAccess::format() bool isDebugType(StackAccess::StackAccessType t) { - return (t==StackAccess::DEBUGINFO_LOCAL || - t==StackAccess::DEBUGINFO_PARAM); + return (t==StackAccess::StackAccessType::DEBUGINFO_LOCAL || + t==StackAccess::StackAccessType::DEBUGINFO_PARAM); } int getAccessSize(InstructionAPI::Instruction insn) @@ -618,19 +619,19 @@ bool getMemoryOffset(ParseAPI::Function *func, bool isOffsetSet = false; // Determine how memory is accessed - StackAccess::StackAccessType type = StackAccess::UNKNOWN; + StackAccess::StackAccessType type = StackAccess::StackAccessType::UNKNOWN; if (analyzeDefinition) { - type = StackAccess::DEFINITION; + type = StackAccess::StackAccessType::DEFINITION; } else if (insn.readsMemory() && insn.writesMemory()) { - type = StackAccess::READWRITE; + type = StackAccess::StackAccessType::READWRITE; } else if (insn.readsMemory()) { - type = StackAccess::READ; + type = StackAccess::StackAccessType::READ; } else if (insn.writesMemory()) { - type = StackAccess::WRITE; + type = StackAccess::StackAccessType::WRITE; } // If memory is not accessed, no need to find an offset - if (type == StackAccess::UNKNOWN) { + if (type == StackAccess::StackAccessType::UNKNOWN) { return false; } @@ -686,7 +687,7 @@ bool getMemoryOffset(ParseAPI::Function *func, if (children.size() == 1) { InstructionAPI::InstructionAST::Ptr child = children.front(); - val = boost::dynamic_pointer_cast(child); } } @@ -714,7 +715,7 @@ bool getMemoryOffset(ParseAPI::Function *func, } stackmods_printf("\t\t\t\t found offset %ld, disp = %ld, " - "type = %d\n", offset, disp, type); + "type = %d\n", offset, disp, static_cast(type)); } } } @@ -750,7 +751,7 @@ bool getMemoryOffset(ParseAPI::Function *func, else width = 8; ret->setRegHeight(ret->regHeight() - width); ret->setReadHeight(ret->readHeight() - width); - ret->setType(StackAccess::SAVED); + ret->setType(StackAccess::StackAccessType::SAVED); } } diff --git a/dyninstAPI/src/StackMod/StackAccess.h b/dyninstAPI/src/StackMod/StackAccess.h index 0753f2d1da..1e05e42f0a 100644 --- a/dyninstAPI/src/StackMod/StackAccess.h +++ b/dyninstAPI/src/StackMod/StackAccess.h @@ -31,7 +31,10 @@ #ifndef _STACKACCESS_H_ #define _STACKACCESS_H_ -#include "dyn_regs.h" +#include +#include +#include +#include "registers/MachRegister.h" #include "Instruction.h" #include "stackanalysis.h" @@ -39,7 +42,7 @@ using namespace Dyninst; class StackAccess { public: - enum StackAccessType { + enum class StackAccessType { DEBUGINFO_LOCAL, DEBUGINFO_PARAM, SAVED, diff --git a/dyninstAPI/src/StackMod/StackLocation.h b/dyninstAPI/src/StackMod/StackLocation.h index 4b1d731e61..6600b5cb13 100644 --- a/dyninstAPI/src/StackMod/StackLocation.h +++ b/dyninstAPI/src/StackMod/StackLocation.h @@ -31,12 +31,13 @@ #ifndef _STACKLOCATION_H_ #define _STACKLOCATION_H_ +#include #include -#include "dyn_regs.h" +#include "registers/MachRegister.h" #include "common/src/IntervalTree.h" #include "stackanalysis.h" - +#include "dyntypes.h" #include "StackAccess.h" using namespace Dyninst; @@ -69,7 +70,7 @@ class StackLocation { {} StackLocation(MachRegister r, int s) : - _type(StackAccess::UNKNOWN), + _type(StackAccess::StackAccessType::UNKNOWN), _size(s), _isStackMemory(false), _isRegister(true), @@ -79,8 +80,11 @@ class StackLocation { {} StackLocation() : + _type(StackAccess::StackAccessType::UNKNOWN), + _size{}, _isStackMemory(false), _isRegister(false), + _reg{}, _isNull(true), _valid(NULL) {} @@ -122,7 +126,7 @@ class StackLocation { bool _isStackMemory; StackAnalysis::Height _off; - bool _isRegisterHeight; + bool _isRegisterHeight{}; bool _isRegister; MachRegister _reg; @@ -132,7 +136,8 @@ class StackLocation { ValidPCRange* _valid; }; -struct less_StackLocation: public std::binary_function { +struct less_StackLocation +{ bool operator()(StackLocation* a, StackLocation* b) const { if (a->isStackMemory() && b->isStackMemory()) { if (a->off().height() == b->off().height()) { @@ -178,7 +183,7 @@ class tmpObject ValidPCRange* _valid; }; -struct less_tmpObject: public std::binary_function +struct less_tmpObject { bool operator()(tmpObject a, tmpObject b) const { if (a.offset() < b.offset()) { diff --git a/dyninstAPI/src/StackMod/StackModChecker.C b/dyninstAPI/src/StackMod/StackModChecker.C index f9930a5ce9..e3e8781b58 100644 --- a/dyninstAPI/src/StackMod/StackModChecker.C +++ b/dyninstAPI/src/StackMod/StackModChecker.C @@ -28,6 +28,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include "BPatch.h" #include "BPatch_addressSpace.h" #include "BPatch_flowGraph.h" diff --git a/dyninstAPI/src/StackMod/StackModChecker.h b/dyninstAPI/src/StackMod/StackModChecker.h index 5058a93fa9..fa1c1c42fe 100644 --- a/dyninstAPI/src/StackMod/StackModChecker.h +++ b/dyninstAPI/src/StackMod/StackModChecker.h @@ -31,6 +31,10 @@ #ifndef _StackModChecker_h_ #define _StackModChecker_h_ +#include +#include +#include +#include #include "BPatch_function.h" #include "Instruction.h" diff --git a/dyninstAPI/src/StackMod/TMap.C b/dyninstAPI/src/StackMod/TMap.C index 021c9d62d7..f8622e47ec 100644 --- a/dyninstAPI/src/StackMod/TMap.C +++ b/dyninstAPI/src/StackMod/TMap.C @@ -28,8 +28,9 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include "debug.h" -#include "dyn_regs.h" +#include "registers/MachRegister.h" #include "StackLocation.h" #include "TMap.h" diff --git a/dyninstAPI/src/StackMod/TMap.h b/dyninstAPI/src/StackMod/TMap.h index c18a9fbdfd..2c99c7c581 100644 --- a/dyninstAPI/src/StackMod/TMap.h +++ b/dyninstAPI/src/StackMod/TMap.h @@ -31,7 +31,8 @@ #ifndef _TMAP_H_ #define _TMAP_H_ -#include "dyn_regs.h" +#include +#include #include "StackLocation.h" diff --git a/dyninstAPI/src/addressSpace.C b/dyninstAPI/src/addressSpace.C index 74feb6edcb..b31ba148a2 100644 --- a/dyninstAPI/src/addressSpace.C +++ b/dyninstAPI/src/addressSpace.C @@ -28,6 +28,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include "addressSpace.h" #include "codeRange.h" #include "dynProcess.h" @@ -50,9 +51,8 @@ #include "Relocation/Transformers/Include.h" #include "Relocation/CodeTracker.h" -#include "MemoryEmulator/memEmulator.h" #include "parseAPI/h/CodeObject.h" -#include +#include #include "PatchMgr.h" #include "Patching.h" @@ -61,10 +61,11 @@ #include "Relocation/DynObject.h" #include "Relocation/DynInstrumenter.h" -#include +#include #include "dynThread.h" #include "pcEventHandler.h" +#include "unaligned_memory_access.h" // Implementations of non-virtual functions in the address space // class. @@ -89,20 +90,8 @@ AddressSpace::AddressSpace () : up_ptr_(NULL), costAddr_(0), installedSpringboards_(new Relocation::InstalledSpringboards()), - memEmulator_(NULL), - emulateMem_(false), - emulatePC_(false), delayRelocation_(false) { -#if 0 - // Disabled for now; used by defensive mode - if ( getenv("DYNINST_EMULATE_MEMORY") ) { - printf("emulating memory & pc\n"); - memEmulator_ = new MemoryEmulator(this); - emulateMem_ = true; - emulatePC_ = true; - } -#endif // Historically, we only use SIGTRAP as the signal for tramopline. // However, SIGTRAP is always intercepted by GDB, causing it is // almost impossible to debug through signal trampolines. @@ -116,8 +105,6 @@ AddressSpace::AddressSpace () : } AddressSpace::~AddressSpace() { - if (memEmulator_) - delete memEmulator_; if (mgr_) static_cast(mgr_->as())->removeAddrSpace(this); @@ -235,10 +222,6 @@ void AddressSpace::copyAddressSpace(AddressSpace *parent) { func_instance *to = findFunction(SCAST_FI(iter->second.first)->ifunc()); fwm[from] = std::make_pair(to, iter->second.second); } - - if (memEmulator_) assert(0 && "FIXME!"); - emulateMem_ = parent->emulateMem_; - emulatePC_ = parent->emulatePC_; } void AddressSpace::deleteAddressSpace() { @@ -271,9 +254,6 @@ void AddressSpace::deleteAddressSpace() { // up_ptr_ is untouched costAddr_ = 0; - - if (memEmulator_) delete memEmulator_; - memEmulator_ = NULL; } @@ -306,7 +286,7 @@ void AddressSpace::inferiorFreeCompact() { unsigned i, nbuf = freeList.size(); /* sort buffers by address */ - std::sort(freeList.begin(), freeList.end(), ptr_fun(heapItemLessByAddr)); + std::sort(freeList.begin(), freeList.end(), heapItemLessByAddr); /* combine adjacent buffers */ bool needToCompact = false; @@ -393,13 +373,9 @@ void AddressSpace::addHeap(heapItem *h) { heap_.heapFree.push_back(h2); /* When we add an item to heapFree, make sure it remains in sorted order */ - std::sort(heap_.heapFree.begin(), heap_.heapFree.end(), ptr_fun(heapItemLessByAddr)); + std::sort(heap_.heapFree.begin(), heap_.heapFree.end(), heapItemLessByAddr); heap_.totalFreeMemAvailable += h2->length; - - if (h->dynamic) { - addAllocatedRegion(h->addr, h->length); - } } void AddressSpace::initializeHeap() { @@ -451,7 +427,7 @@ Address AddressSpace::inferiorMallocInternal(unsigned size, } /* When we update an item in heapFree, make sure it remains in sorted order */ - std::sort(heap_.heapFree.begin(), heap_.heapFree.end(), ptr_fun(heapItemLessByAddr)); + std::sort(heap_.heapFree.begin(), heap_.heapFree.end(), heapItemLessByAddr); // add allocated block to active list h->length = size; @@ -481,7 +457,7 @@ void AddressSpace::inferiorFreeInternal(Address block) { heap_.heapFree.push_back(h); /* When we add an item to heapFree, make sure it remains in sorted order */ - std::sort(heap_.heapFree.begin(), heap_.heapFree.end(), ptr_fun(heapItemLessByAddr)); + std::sort(heap_.heapFree.begin(), heap_.heapFree.end(), heapItemLessByAddr); heap_.totalFreeMemAvailable += h->length; heap_.freed += h->length; @@ -587,7 +563,7 @@ bool AddressSpace::inferiorShrinkBlock(heapItem *h, heap_.heapFree.push_back(freeEnd); /* When we add an item to heapFree, make sure it remains sorted */ - std::sort(heap_.heapFree.begin(), heap_.heapFree.end(), ptr_fun(heapItemLessByAddr)); + std::sort(heap_.heapFree.begin(), heap_.heapFree.end(), heapItemLessByAddr); } heap_.totalFreeMemAvailable += shrink; @@ -1029,7 +1005,7 @@ AstNodePtr AddressSpace::trampGuardAST() { if (trampGuardAST_) return trampGuardAST_; - trampGuardAST_ = AstNode::operandNode(AstNode::variableAddr, trampGuardBase_->ivar()); + trampGuardAST_ = AstNode::operandNode(AstNode::operandType::variableAddr, trampGuardBase_->ivar()); return trampGuardAST_; } @@ -1140,7 +1116,6 @@ bool mapping_sort(const trampTrapMappings::tramp_mapping_t *lhs, return lhs->from_addr < rhs->from_addr; } -#if defined(cap_32_64) void trampTrapMappings::writeToBuffer(unsigned char *buffer, unsigned long val, unsigned addr_width) { @@ -1149,19 +1124,14 @@ void trampTrapMappings::writeToBuffer(unsigned char *buffer, unsigned long val, //Currently only support 64-bit mutators with 32-bit mutatees assert(addr_width == 4); assert(sizeof(Address) == 8); - *((uint32_t *) buffer) = (uint32_t) val; +#if defined(cap_32_64) + assert(val <= numeric_limits::max() && "val more than 32 bits"); + write_memory_as(buffer, static_cast(val)); return; +#endif } - *((unsigned long *) buffer) = val; -} -#else -void trampTrapMappings::writeToBuffer(unsigned char *buffer, unsigned long val, - unsigned) -{ - *((unsigned long *)(void*) buffer) = val; + write_memory_as(buffer, static_cast(val)); } -#endif - void trampTrapMappings::writeTrampVariable(const int_variable *var, unsigned long val) @@ -1718,8 +1688,6 @@ bool AddressSpace::relocate() { modFuncs = actualModFuncs; } - addModifiedRegion(iter->first); - Address middle = (iter->first->codeAbs() + (iter->first->imageSize() / 2)); if (!relocateInt(iter->second.begin(), iter->second.end(), middle)) { @@ -1731,7 +1699,6 @@ bool AddressSpace::relocate() { - updateMemEmulator(); modifiedFunctions_.clear(); @@ -1883,13 +1850,6 @@ bool AddressSpace::transform(CodeMover::Ptr cm) { cm->transform(pc); } -#if defined(cap_mem_emulation) - if (emulateMem_) { - MemEmulatorTransformer m; - cm->transform(m); - } -#endif - // Add instrumentation relocation_cerr << "Inst transformer" << endl; Instrumenter i; @@ -2003,25 +1963,11 @@ bool AddressSpace::patchCode(CodeMover::Ptr cm, // HACK: code modification will make this happen... return false; } - - mapped_object *obj = findObject(iter->startAddr()); - if (obj && runtime_lib.end() == runtime_lib.find(obj)) { - Address objBase = obj->codeBase(); - SymtabAPI::Region * reg = obj->parse_img()->getObject()-> - findEnclosingRegion(iter->startAddr() - objBase); - if (memEmulator_) - memEmulator_->addSpringboard(reg, - iter->startAddr() - objBase - reg->getMemOffset(), - iter->used()); - } } return true; } -void AddressSpace::causeTemplateInstantiations() { -} - void AddressSpace::getRelocAddrs(Address orig, block_instance *block, func_instance *func, @@ -2163,23 +2109,6 @@ void AddressSpace::addInstrumentationInstance(baseTramp *bt, instrumentationInstances_[bt].insert(a); } -void AddressSpace::addAllocatedRegion(Address start, unsigned size) { - if (memEmulator_) memEmulator_->addAllocatedRegion(start, size); -} - -void AddressSpace::addModifiedRegion(mapped_object *obj) { - if (memEmulator_) memEmulator_->addRegion(obj); - return; -} - -void AddressSpace::updateMemEmulator() { - if (memEmulator_) memEmulator_->update(); -} - -MemoryEmulator * AddressSpace::getMemEm() { - return memEmulator_; -} - void updateSrcListAndVisited(ParseAPI::Edge* e, std::list& srcList, std::set& visited) @@ -2239,12 +2168,12 @@ AddressSpace::getStubs(const std::list &owBlocks, SingleContext epred_((*fit)->ifunc(),true,true); //Intraproc epred(&epred_); std::list srcList; - std::for_each(boost::make_filter_iterator(epred_, sourceEdges.begin(), sourceEdges.end()), - boost::make_filter_iterator(epred_, sourceEdges.end(), sourceEdges.end()), - boost::bind(updateSrcListAndVisited, - boost::placeholders::_1, - boost::ref(srcList), - boost::ref(visited))); + std::for_each(dyncompat::make_filter_iterator(epred_, sourceEdges.begin(), sourceEdges.end()), + dyncompat::make_filter_iterator(epred_, sourceEdges.end(), sourceEdges.end()), + dyncompat::bind(updateSrcListAndVisited, + dyncompat::placeholders::_1, + dyncompat::ref(srcList), + dyncompat::ref(visited))); // find all stub blocks for this edge @@ -2262,12 +2191,12 @@ AddressSpace::getStubs(const std::list &owBlocks, } else { const Block::edgelist &srcSrcs = isrc->sources(); - std::for_each(boost::make_filter_iterator(epred_, srcSrcs.begin(), srcSrcs.end()), - boost::make_filter_iterator(epred_, srcSrcs.end(), srcSrcs.end()), - boost::bind(updateSrcListAndVisited, - boost::placeholders::_1, - boost::ref(srcList), - boost::ref(visited))); + std::for_each(dyncompat::make_filter_iterator(epred_, srcSrcs.begin(), srcSrcs.end()), + dyncompat::make_filter_iterator(epred_, srcSrcs.end(), srcSrcs.end()), + dyncompat::bind(updateSrcListAndVisited, + dyncompat::placeholders::_1, + dyncompat::ref(srcList), + dyncompat::ref(visited))); } diff --git a/dyninstAPI/src/addressSpace.h b/dyninstAPI/src/addressSpace.h index f00e04a4ef..77832b822b 100644 --- a/dyninstAPI/src/addressSpace.h +++ b/dyninstAPI/src/addressSpace.h @@ -38,8 +38,14 @@ #include "ast.h" #include "symtabAPI/h/Symtab.h" #include "dyninstAPI/src/trapMappings.h" +#include +#include +#include +#include +#include +#include #include - +#include "dyntypes.h" #include "common/src/IntervalTree.h" #include "parseAPI/h/CodeObject.h" @@ -88,7 +94,6 @@ class trampTrapMappings; class baseTramp; namespace Dyninst { - class MemoryEmulator; namespace InstructionAPI { class Instruction; @@ -339,7 +344,7 @@ class AddressSpace : public InstructionSource { const func_instance *isFunctionReplacement(func_instance *func) const; // And this.... - typedef boost::shared_ptr InstructionPtr; + typedef dyncompat::shared_ptr InstructionPtr; bool getDynamicCallSiteArgs(InstructionAPI::Instruction insn, Address addr, std::vector &args); @@ -464,8 +469,6 @@ class AddressSpace : public InstructionSource { RelocInfo &relocInfo); // defensive mode code // - void causeTemplateInstantiations(); - // Debugging method bool inEmulatedCode(Address addr); @@ -485,11 +488,6 @@ class AddressSpace : public InstructionSource { void addModifiedFunction(func_instance *func); void addModifiedBlock(block_instance *block); - void updateMemEmulator(); - bool isMemoryEmulated() { return emulateMem_; } - bool emulatingPC() { return emulatePC_; } - MemoryEmulator *getMemEm(); - bool delayRelocation() const; protected: @@ -552,14 +550,6 @@ class AddressSpace : public InstructionSource { // FuncModMap functionReplacements_; // FuncModMap functionWraps_; - void addAllocatedRegion(Address start, unsigned size); - void addModifiedRegion(mapped_object *obj); - - MemoryEmulator *memEmulator_; - - bool emulateMem_; - bool emulatePC_; - bool delayRelocation_; std::map wrappedFunctionWorklist_; diff --git a/dyninstAPI/src/ast.C b/dyninstAPI/src/ast.C index 441fd2a4d4..9ca80ddd64 100644 --- a/dyninstAPI/src/ast.C +++ b/dyninstAPI/src/ast.C @@ -30,6 +30,7 @@ // $Id: ast.C,v 1.209 2008/09/15 18:37:49 jaw Exp $ +#include #include "dyninstAPI/src/image.h" #include "function.h" #include "inst.h" @@ -62,8 +63,6 @@ using namespace Dyninst::InstructionAPI; #elif defined(arch_x86) || defined (arch_x86_64) #include "inst-x86.h" #include "emit-x86.h" -extern int tramp_pre_frame_size_32; -extern int tramp_pre_frame_size_64; #elif defined(arch_aarch64) #include "inst-aarch64.h" #else @@ -96,10 +95,6 @@ AstNodePtr AstNode::actualAddrNode_ = AstNodePtr(); AstNodePtr AstNode::dynamicTargetNode_ = AstNodePtr(); AstNode::AstNode() { -#if defined(ASTDEBUG) - ASTcounter(); -#endif - // dyn_debug_ast = 0; referenceCount = 0; useCount = 0; @@ -209,7 +204,7 @@ AstNodePtr AstNode::sequenceNode(std::vector &sequence) { } AstNodePtr AstNode::variableNode(vector &ast_wrappers, - vector >*ranges) { + vector >*ranges) { return AstNodePtr(new AstVariableNode(ast_wrappers, ranges)); } @@ -320,33 +315,35 @@ AstOperatorNode::AstOperatorNode(opCode opC, AstNodePtr l, AstNodePtr r, AstNode eoperand(e) { // Optimization pass... - - if (op == plusOp) { - if (loperand->getoType() == Constant) { - // Swap left and right... - AstNodePtr temp = loperand; - loperand = roperand; - roperand = temp; - } - } - if (op == timesOp) { - if (roperand->getoType() == undefOperandType) { - // ... - } - else if (roperand->getoType() != Constant) { - AstNodePtr temp = roperand; - roperand = loperand; - loperand = temp; - } - else { - int result; - if (!isPowerOf2((Address)roperand->getOValue(),result) && - isPowerOf2((Address)loperand->getOValue(),result)) { - AstNodePtr temp = roperand; - roperand = loperand; - loperand = temp; - } - } + if(!loperand) return; + if(roperand) { + if (op == plusOp) { + if (loperand->getoType() == operandType::Constant) { + // Swap left and right... + AstNodePtr temp = loperand; + loperand = roperand; + roperand = temp; + } + } + if (op == timesOp) { + if (roperand->getoType() == operandType::undefOperandType) { + // ... + } + else if (roperand->getoType() != operandType::Constant) { + AstNodePtr temp = roperand; + roperand = loperand; + loperand = temp; + } + else { + int result; + if (!isPowerOf2((Address)roperand->getOValue(),result) && + isPowerOf2((Address)loperand->getOValue(),result)) { + AstNodePtr temp = roperand; + roperand = loperand; + loperand = temp; + } + } + } } if (l != AstNodePtr()) { @@ -354,7 +351,7 @@ AstOperatorNode::AstOperatorNode(opCode opC, AstNodePtr l, AstNodePtr r, AstNode // don't actually reference their loperand--they reference // the child of the loperand. Handle that here to keep // reference counts sane. - if (op == storeOp && loperand->getoType() == DataIndir) + if (op == storeOp && loperand->getoType() == operandType::DataIndir) l->operand()->referenceCount++; else l->referenceCount++; @@ -373,7 +370,7 @@ AstOperandNode::AstOperandNode(operandType ot, void *arg) : operand_() { - if (ot == ConstantString) + if (ot == operandType::ConstantString) oValue = (void *)P_strdup((char *)arg); else oValue = (void *) arg; @@ -462,7 +459,7 @@ AstSequenceNode::AstSequenceNode(std::vector &sequence) : } } -AstVariableNode::AstVariableNode(vector&ast_wrappers, vector > *ranges) : +AstVariableNode::AstVariableNode(vector&ast_wrappers, vector > *ranges) : ast_wrappers_(ast_wrappers), ranges_(ranges), index(0) { vector::iterator i; @@ -532,31 +529,6 @@ AstNodePtr AstNode::threadIndexNode() { return indexNode_; } - -#if defined(ASTDEBUG) -#define AST_PRINT -#endif - -#if defined(AST_PRINT) -void AstNode::printRC() -{ - sprintf(errorLine,"RC referenceCount=%d\n",referenceCount); - logLine(errorLine); - if (loperand) { - logLine("RC loperand\n"); - loperand->printRC(); - } - if (roperand) { - logLine("RC roperand\n"); - roperand->printRC(); - } - if (eoperand) { - logLine("RC eoperand\n"); - eoperand->printRC(); - } -} -#endif - AstNode::~AstNode() { //printf("at ~AstNode() count=%d\n", referenceCount); } @@ -568,7 +540,7 @@ Address AstMiniTrampNode::generateTramp(codeGen &gen, static AstNodePtr preamble; if (costAst == AstNodePtr()) - costAst = AstNode::operandNode(AstNode::Constant, (void *)0); + costAst = AstNode::operandNode(AstNode::operandType::Constant, (void *)0); if (preamble == AstNodePtr()) preamble = AstNode::operatorNode(trampPreamble, costAst); @@ -657,14 +629,14 @@ void AstNode::cleanUseCount(void) // Allocate a register and make it available for sharing if our // node is shared -Register AstNode::allocateAndKeep(codeGen &gen, bool noCost) +Dyninst::Register AstNode::allocateAndKeep(codeGen &gen, bool noCost) { ast_printf("Allocating register for node %p, useCount %d\n", (void*)this, useCount); // Allocate a register - Register dest = gen.rs()->allocateRegister(gen, noCost); + Dyninst::Register dest = gen.rs()->allocateRegister(gen, noCost); ast_printf("Allocator returned %u\n", dest); - assert(dest != REG_NULL); + assert(dest != Dyninst::Null_Register); if (useCount > 1) { ast_printf("Adding kept register %u for node %p: useCount %d\n", dest, (void*)this, useCount); @@ -703,7 +675,7 @@ Register AstNode::allocateAndKeep(codeGen &gen, bool noCost) bool AstNode::generateCode(codeGen &gen, bool noCost, Address &retAddr, - Register &retReg) { + Dyninst::Register &retReg) { static bool entered = false; @@ -758,17 +730,17 @@ bool AstNode::generateCode(codeGen &gen, bool AstNode::generateCode(codeGen &gen, bool noCost) { Address unused = ADDR_NULL; - Register unusedReg = REG_NULL; + Dyninst::Register unusedReg = Dyninst::Null_Register; bool ret = generateCode(gen, noCost, unused, unusedReg); gen.rs()->freeRegister(unusedReg); return ret; } -bool AstNode::previousComputationValid(Register ®, +bool AstNode::previousComputationValid(Dyninst::Register ®, codeGen &gen) { - Register keptReg = gen.tracker()->hasKeptRegister(this); - if (keptReg != REG_NULL) { + Dyninst::Register keptReg = gen.tracker()->hasKeptRegister(this); + if (keptReg != Dyninst::Null_Register) { reg = keptReg; ast_printf("Returning previously used register %u for node %p\n", reg, (void*)this); return true; @@ -777,9 +749,9 @@ bool AstNode::previousComputationValid(Register ®, } // We're going to use this fragment over and over and over... -#define RETURN_KEPT_REG(r) { if (previousComputationValid(r, gen)) { decUseCount(gen); gen.rs()->incRefCount(r); return true;} } -#define ERROR_RETURN { fprintf(stderr, "[%s:%d] ERROR: failure to generate operand\n", __FILE__, __LINE__); return false; } -#define REGISTER_CHECK(r) if (r == REG_NULL) { fprintf(stderr, "[%s: %d] ERROR: returned register invalid\n", __FILE__, __LINE__); return false; } +#define RETURN_KEPT_REG(r) do { if (previousComputationValid(r, gen)) { decUseCount(gen); gen.rs()->incRefCount(r); return true;} } while (0) +#define ERROR_RETURN do { fprintf(stderr, "[%s:%d] ERROR: failure to generate operand\n", __FILE__, __LINE__); return false; } while (0) +#define REGISTER_CHECK(r) do { if ((r) == Dyninst::Null_Register) { fprintf(stderr, "[%s: %d] ERROR: returned register invalid\n", __FILE__, __LINE__); return false; } } while (0) bool AstNode::initRegisters(codeGen &g) { @@ -796,7 +768,7 @@ bool AstNode::initRegisters(codeGen &g) { bool AstNode::generateCode_phase2(codeGen &, bool, Address &, - Register &) { + Dyninst::Register &) { fprintf(stderr, "ERROR: call to AstNode generateCode_phase2; should be handled by subclass\n"); fprintf(stderr, "Undefined phase2 for:\n"); if (dynamic_cast(this)) fprintf(stderr, "nullNode\n"); @@ -817,9 +789,9 @@ bool AstNode::generateCode_phase2(codeGen &, bool, bool AstNullNode::generateCode_phase2(codeGen &gen, bool, Address &retAddr, - Register &retReg) { + Dyninst::Register &retReg) { retAddr = ADDR_NULL; - retReg = REG_NULL; + retReg = Dyninst::Null_Register; decUseCount(gen); @@ -828,7 +800,7 @@ bool AstNullNode::generateCode_phase2(codeGen &gen, bool, bool AstNode::allocateCanaryRegister(codeGen& gen, bool noCost, - Register& reg, + Dyninst::Register& reg, bool& needSaveAndRestore) { // Let's see if we can find a dead register to use! @@ -837,8 +809,8 @@ bool AstNode::allocateCanaryRegister(codeGen& gen, // Try to get a scratch register from the register space registerSpace* regSpace = registerSpace::actualRegSpace(point); bool realReg = true; - Register tmpReg = regSpace->getScratchRegister(gen, noCost, realReg); - if (tmpReg != REG_NULL) { + Dyninst::Register tmpReg = regSpace->getScratchRegister(gen, noCost, realReg); + if (tmpReg != Dyninst::Null_Register) { reg = tmpReg; needSaveAndRestore = false; if (gen.getArch() == Arch_x86) { @@ -850,7 +822,7 @@ bool AstNode::allocateCanaryRegister(codeGen& gen, // Couldn't find a dead register to use :-( registerSpace* deadRegSpace = registerSpace::optimisticRegSpace(gen.addrSpace()); reg = deadRegSpace->getScratchRegister(gen, noCost, realReg); - if (reg == REG_NULL) { + if (reg == Dyninst::Null_Register) { fprintf(stderr, "WARNING: using default allocateAndKeep in allocateCanaryRegister\n"); reg = allocateAndKeep(gen, noCost); } @@ -864,14 +836,14 @@ bool AstNode::allocateCanaryRegister(codeGen& gen, #if defined(cap_stack_mods) bool AstStackInsertNode::generateCode_phase2(codeGen &gen, bool noCost, Address &, - Register &) + Dyninst::Register &) { // Turn off default basetramp instrumentation saves & restores gen.setInsertNaked(true); gen.setModifiedStackFrame(true); bool ignored; - Register reg_sp = convertRegID(MachRegister::getStackPointer(gen.getArch()), ignored); + Dyninst::Register reg_sp = convertRegID(MachRegister::getStackPointer(gen.getArch()), ignored); Emitterx86* emitter = dynamic_cast(gen.codeEmitter()); assert(emitter); @@ -882,16 +854,16 @@ bool AstStackInsertNode::generateCode_phase2(codeGen &gen, bool noCost, /* Move stack pointer to accomodate new value */ if (gen.getArch() == Arch_x86) { - emitter->emitLEA(reg_sp, Null_Register, 0, -size, reg_sp, gen); + emitter->emitLEA(reg_sp, Dyninst::Null_Register, 0, -size, reg_sp, gen); } else if (gen.getArch() == Arch_x86_64) { - emitter->emitLEA(reg_sp, Null_Register, 0, -size, reg_sp, gen); + emitter->emitLEA(reg_sp, Dyninst::Null_Register, 0, -size, reg_sp, gen); } } else if (type == CANARY_AST){ // gen.setCanary(true); // Find a register to use - Register canaryReg = Null_Register; + Dyninst::Register canaryReg = Dyninst::Null_Register; bool needSaveAndRestore = true; // 64-bit requires stack alignment @@ -903,7 +875,7 @@ bool AstStackInsertNode::generateCode_phase2(codeGen &gen, bool noCost, int canarySize = 8; int off = AMD64_STACK_ALIGNMENT - canarySize; // canary - emitter->emitLEA(reg_sp, Null_Register, 0, -off, reg_sp, gen); + emitter->emitLEA(reg_sp, Dyninst::Null_Register, 0, -off, reg_sp, gen); } else { canaryReg = REGNUM_EAX; needSaveAndRestore = true; @@ -913,14 +885,14 @@ bool AstStackInsertNode::generateCode_phase2(codeGen &gen, bool noCost, if (needSaveAndRestore) { if (gen.getArch() == Arch_x86) { int disp = 4; - emitter->emitLEA(reg_sp, Null_Register, 0, -disp, reg_sp, gen); + emitter->emitLEA(reg_sp, Dyninst::Null_Register, 0, -disp, reg_sp, gen); gen.codeEmitter()->emitPush(gen, canaryReg); - emitter->emitLEA(reg_sp, Null_Register, 0, 2*disp, reg_sp, gen); + emitter->emitLEA(reg_sp, Dyninst::Null_Register, 0, 2*disp, reg_sp, gen); } else if (gen.getArch() == Arch_x86_64) { int disp = 8; - emitter->emitLEA(reg_sp, Null_Register, 0, -disp, reg_sp, gen); + emitter->emitLEA(reg_sp, Dyninst::Null_Register, 0, -disp, reg_sp, gen); gen.codeEmitter()->emitPush(gen, canaryReg); - emitter->emitLEA(reg_sp, Null_Register, 0, 2*disp, reg_sp, gen); + emitter->emitLEA(reg_sp, Dyninst::Null_Register, 0, 2*disp, reg_sp, gen); } } @@ -952,11 +924,11 @@ bool AstStackInsertNode::generateCode_phase2(codeGen &gen, bool noCost, if (needSaveAndRestore) { if (gen.getArch() == Arch_x86) { int disp = 4; - emitter->emitLEA(reg_sp, Null_Register, 0, -disp, reg_sp, gen); + emitter->emitLEA(reg_sp, Dyninst::Null_Register, 0, -disp, reg_sp, gen); gen.codeEmitter()->emitPop(gen, canaryReg); } else if (gen.getArch() == Arch_x86_64) { int disp = 8; - emitter->emitLEA(reg_sp, Null_Register, 0, -disp, reg_sp, gen); + emitter->emitLEA(reg_sp, Dyninst::Null_Register, 0, -disp, reg_sp, gen); emitter->emitPop(gen, canaryReg); } } @@ -970,14 +942,14 @@ bool AstStackInsertNode::generateCode_phase2(codeGen &gen, bool noCost, bool AstStackRemoveNode::generateCode_phase2(codeGen &gen, bool noCost, Address &, - Register &) + Dyninst::Register &) { // Turn off default basetramp instrumentation saves & restores gen.setInsertNaked(true); gen.setModifiedStackFrame(true); bool ignored; - Register reg_sp = convertRegID(MachRegister::getStackPointer(gen.getArch()), ignored); + Dyninst::Register reg_sp = convertRegID(MachRegister::getStackPointer(gen.getArch()), ignored); Emitterx86* emitter = dynamic_cast(gen.codeEmitter()); assert(emitter); @@ -986,15 +958,15 @@ bool AstStackRemoveNode::generateCode_phase2(codeGen &gen, bool noCost, /* Adjust stack pointer by size */ int disp = size; if (gen.getArch() == Arch_x86) { - emitter->emitLEA(reg_sp, Null_Register, 0, disp, reg_sp, gen); + emitter->emitLEA(reg_sp, Dyninst::Null_Register, 0, disp, reg_sp, gen); } else if (gen.getArch() == Arch_x86_64) { - emitter->emitLEA(reg_sp, Null_Register, 0, disp, reg_sp, gen); + emitter->emitLEA(reg_sp, Dyninst::Null_Register, 0, disp, reg_sp, gen); } } else if (type == CANARY_AST) { // gen.setCanary(true); // Find a register to use - Register canaryReg = Null_Register; + Dyninst::Register canaryReg = Dyninst::Null_Register; bool needSaveAndRestore = true; if (gen.getArch() == Arch_x86_64) { allocateCanaryRegister(gen, noCost, canaryReg, needSaveAndRestore); @@ -1009,10 +981,10 @@ bool AstStackRemoveNode::generateCode_phase2(codeGen &gen, bool noCost, if (gen.getArch() == Arch_x86) { int disp = 4; gen.codeEmitter()->emitPush(gen, canaryReg); - emitter->emitLEA(reg_sp, Null_Register, 0, disp, reg_sp, gen); + emitter->emitLEA(reg_sp, Dyninst::Null_Register, 0, disp, reg_sp, gen); } else if (gen.getArch() == Arch_x86_64) { int disp = 8; - emitter->emitLEA(reg_sp, Null_Register, 0, disp, reg_sp, gen); + emitter->emitLEA(reg_sp, Dyninst::Null_Register, 0, disp, reg_sp, gen); } } @@ -1022,11 +994,11 @@ bool AstStackRemoveNode::generateCode_phase2(codeGen &gen, bool noCost, } else { Address canaryOffset = -1*(Address)(canaryHeight_); if (gen.getArch() == Arch_x86) { - Register destReg = reg_sp; + Dyninst::Register destReg = reg_sp; RealRegister canaryReg_r = gen.rs()->loadVirtualForWrite(canaryReg, gen); emitMovRMToReg(canaryReg_r, RealRegister(destReg), canaryOffset, gen); } else if (gen.getArch() == Arch_x86_64) { - Register destReg = reg_sp; + Dyninst::Register destReg = reg_sp; gen.codeEmitter()->emitLoadRelative(canaryReg, canaryOffset, destReg, 0, gen); } } @@ -1048,11 +1020,11 @@ bool AstStackRemoveNode::generateCode_phase2(codeGen &gen, bool noCost, if (needSaveAndRestore) { if (gen.getArch() == Arch_x86) { int disp = 4; - emitter->emitLEA(reg_sp, Null_Register, 0, -disp, reg_sp, gen); + emitter->emitLEA(reg_sp, Dyninst::Null_Register, 0, -disp, reg_sp, gen); gen.codeEmitter()->emitPop(gen, canaryReg); } else if (gen.getArch() == Arch_x86_64) { int disp = 8; - emitter->emitLEA(reg_sp, Null_Register, 0, -disp, reg_sp, gen); + emitter->emitLEA(reg_sp, Dyninst::Null_Register, 0, -disp, reg_sp, gen); gen.codeEmitter()->emitPop(gen, canaryReg); } } @@ -1061,10 +1033,10 @@ bool AstStackRemoveNode::generateCode_phase2(codeGen &gen, bool noCost, if (canaryAfterPrologue_) { if (gen.getArch() == Arch_x86) { int disp = 4; - emitter->emitLEA(reg_sp, Null_Register, 0, -1*canaryHeight_ + disp, reg_sp, gen); + emitter->emitLEA(reg_sp, Dyninst::Null_Register, 0, -1*canaryHeight_ + disp, reg_sp, gen); } else if (gen.getArch() == Arch_x86_64) { int disp = 8; - emitter->emitLEA(reg_sp, Null_Register, 0, -1*canaryHeight_ + disp, reg_sp, gen); + emitter->emitLEA(reg_sp, Dyninst::Null_Register, 0, -1*canaryHeight_ + disp, reg_sp, gen); } } @@ -1073,7 +1045,7 @@ bool AstStackRemoveNode::generateCode_phase2(codeGen &gen, bool noCost, // 64-bit requires stack alignment (this will include canary cleanup) int canarySize = 8; int off = AMD64_STACK_ALIGNMENT - canarySize; - emitter->emitLEA(reg_sp, Null_Register, 0, off, reg_sp, gen); + emitter->emitLEA(reg_sp, Dyninst::Null_Register, 0, off, reg_sp, gen); } // If the canary value is valid, jmp to next expected instruction @@ -1103,7 +1075,7 @@ bool AstStackRemoveNode::generateCode_phase2(codeGen &gen, bool noCost, return true; } -bool AstStackGenericNode::generateCode_phase2(codeGen& gen, bool, Address&, Register&) +bool AstStackGenericNode::generateCode_phase2(codeGen& gen, bool, Address&, Dyninst::Register&) { gen.setInsertNaked(true); gen.setModifiedStackFrame(true); @@ -1115,18 +1087,18 @@ bool AstStackGenericNode::generateCode_phase2(codeGen& gen, bool, Address&, Regi #else bool AstStackInsertNode::generateCode_phase2(codeGen&, bool, Address &, - Register &) { + Dyninst::Register &) { return false; } bool AstStackRemoveNode::generateCode_phase2(codeGen&, bool, Address &, - Register &) + Dyninst::Register &) { return false; } -bool AstStackGenericNode::generateCode_phase2(codeGen&, bool, Address&, Register&) +bool AstStackGenericNode::generateCode_phase2(codeGen&, bool, Address&, Dyninst::Register&) { return false; } @@ -1134,13 +1106,13 @@ bool AstStackGenericNode::generateCode_phase2(codeGen&, bool, Address&, Register bool AstLabelNode::generateCode_phase2(codeGen &gen, bool, Address &retAddr, - Register &retReg) { + Dyninst::Register &retReg) { assert(generatedAddr_ == 0); // Pick up the address we were added at generatedAddr_ = gen.currAddr(); retAddr = ADDR_NULL; - retReg = REG_NULL; + retReg = Dyninst::Null_Register; decUseCount(gen); @@ -1159,36 +1131,39 @@ bool AstOperatorNode::initRegisters(codeGen &g) { #if !defined(arch_x86) // Override: if we're trying to save to an original // register, make sure it's saved on the stack. - if (op == storeOp) { - if (loperand->getoType() == origRegister) { - Address origReg = (Address) loperand->getOValue(); - // Mark that register as live so we are sure to save it. - registerSlot *r = (*(g.rs()))[origReg]; - r->liveState = registerSlot::live; + if(loperand) { + if (op == storeOp) { + if (loperand->getoType() == operandType::origRegister) { + Address origReg = (Address) loperand->getOValue(); + // Mark that register as live so we are sure to save it. + registerSlot *r = (*(g.rs()))[origReg]; + r->liveState = registerSlot::live; } + } } #endif return ret; } - #if defined(arch_x86) || defined(arch_x86_64) bool AstOperatorNode::generateOptimizedAssignment(codeGen &gen, int size_, bool noCost) { + if(!(loperand && roperand)) { return false; } + //Recognize the common case of 'a = a op constant' and try to // generate optimized code for this case. Address laddr; - if (loperand->getoType() == DataAddr) + if (loperand->getoType() == operandType::DataAddr) { laddr = (Address) loperand->getOValue(); } else { - if(loperand->getoType() == variableValue) + if(loperand->getoType() == operandType::variableValue) { - boost::shared_ptr lnode = - boost::dynamic_pointer_cast(loperand); + dyncompat::shared_ptr lnode = + dyncompat::dynamic_pointer_cast(loperand); int_variable* var = lnode->lookUpVar(gen.addrSpace()); if (!var || gen.addrSpace()->needsPIC(var)) @@ -1203,7 +1178,7 @@ bool AstOperatorNode::generateOptimizedAssignment(codeGen &gen, int size_, bool } - if (roperand->getoType() == Constant) { + if (roperand->getoType() == operandType::Constant) { //Looks like 'global = constant' #if defined(arch_x86_64) if (laddr >> 32 || ((Address) roperand->getOValue()) >> 32 || size_ == 8) { @@ -1233,12 +1208,12 @@ bool AstOperatorNode::generateOptimizedAssignment(codeGen &gen, int size_, bool return false; AstNode *const_oper = NULL; - if (arithl->getoType() == DataAddr && arithr->getoType() == Constant && + if (arithl->getoType() == operandType::DataAddr && arithr->getoType() == operandType::Constant && laddr == (Address) arithl->getOValue()) { const_oper = arithr; } - else if (arithl->getoType() == variableValue && arithr->getoType() == Constant) + else if (arithl->getoType() == operandType::variableValue && arithr->getoType() == operandType::Constant) { Address addr = 0; int_variable* var = arithl->lookUpVar(gen.addrSpace()); @@ -1249,12 +1224,12 @@ bool AstOperatorNode::generateOptimizedAssignment(codeGen &gen, int size_, bool const_oper = arithr; } } - else if (arithr->getoType() == DataAddr && arithl->getoType() == Constant && + else if (arithr->getoType() == operandType::DataAddr && arithl->getoType() == operandType::Constant && laddr == (Address) arithr->getOValue() && roper->op == plusOp) { const_oper = arithl; } - else if (arithl->getoType() == variableValue && arithr->getoType() == Constant) + else if (arithl->getoType() == operandType::variableValue && arithr->getoType() == operandType::Constant) { Address addr = 0; int_variable* var = arithl->lookUpVar(gen.addrSpace()); @@ -1294,7 +1269,8 @@ bool AstOperatorNode::generateOptimizedAssignment(codeGen &, int, bool) bool AstOperatorNode::generateCode_phase2(codeGen &gen, bool noCost, Address &retAddr, - Register &retReg) { + Dyninst::Register &retReg) { + if(!loperand) { return false; } retAddr = ADDR_NULL; // We won't be setting this... // retReg may have a value or be the (register) equivalent of NULL. @@ -1305,27 +1281,27 @@ bool AstOperatorNode::generateCode_phase2(codeGen &gen, bool noCost, Address addr = ADDR_NULL; - Register src1 = Null_Register; - Register src2 = Null_Register; + Dyninst::Register src1 = Dyninst::Null_Register; + Dyninst::Register src2 = Dyninst::Null_Register; - Register right_dest = Null_Register; - Register tmp = Null_Register; + Dyninst::Register right_dest = Dyninst::Null_Register; + Dyninst::Register tmp = Dyninst::Null_Register; switch(op) { case branchOp: { - assert(loperand->getoType() == Constant); - unsigned offset = (Register) (long) loperand->getOValue(); + assert(loperand->getoType() == operandType::Constant); + unsigned offset = (Dyninst::Register) (long) loperand->getOValue(); // We are not calling loperand->generateCode_phase2, // so we decrement its useCount by hand. // Would be nice to allow register branches... loperand->decUseCount(gen); - (void)emitA(branchOp, 0, 0, (Register)offset, gen, rc_no_control, noCost); - retReg = REG_NULL; // No return register + (void)emitA(branchOp, 0, 0, (Dyninst::Register)offset, gen, rc_no_control, noCost); + retReg = Dyninst::Null_Register; // No return register break; } case ifOp: { + if(!roperand) { return false; } // This ast cannot be shared because it doesn't return a register - if (!loperand->generateCode_phase2(gen, noCost, addr, src1)) ERROR_RETURN; REGISTER_CHECK(src1); codeBufIndex_t ifIndex= gen.getIndex(); @@ -1337,7 +1313,7 @@ bool AstOperatorNode::generateCode_phase2(codeGen &gen, bool noCost, // We can reuse src1 for the body of the conditional; however, keep the value here // so that we can use it for the branch fix below. - Register src1_copy = src1; + Dyninst::Register src1_copy = src1; if (loperand->decRefCount()) gen.rs()->freeRegister(src1); @@ -1382,10 +1358,10 @@ bool AstOperatorNode::generateCode_phase2(codeGen &gen, bool noCost, // This backtracks over current code. // If/when we vectorize, we can do this in a two-pass arrangement (void) emitA(op, src1_copy, 0, - (Register) codeGen::getDisplacement(thenSkipStart, elseStartIndex), + (Dyninst::Register) codeGen::getDisplacement(thenSkipStart, elseStartIndex), gen, rc_no_control, noCost); // Now we can free the register - // Register has already been freed; we're just re-using it. + // Dyninst::Register has already been freed; we're just re-using it. //gen.rs()->freeRegister(src1); gen.setIndex(elseStartIndex); @@ -1419,12 +1395,12 @@ bool AstOperatorNode::generateCode_phase2(codeGen &gen, bool noCost, else { gen.setIndex(elseSkipIndex); emitA(branchOp, 0, 0, - (Register) codeGen::getDisplacement(elseSkipStart, endIndex), + (Dyninst::Register) codeGen::getDisplacement(elseSkipStart, endIndex), gen, rc_no_control, noCost); gen.setIndex(endIndex); } } - retReg = REG_NULL; + retReg = Dyninst::Null_Register; break; } case ifMCOp: { @@ -1475,6 +1451,7 @@ bool AstOperatorNode::generateCode_phase2(codeGen &gen, bool noCost, break; } case whileOp: { + if(!roperand) { return false; } codeBufIndex_t top = gen.getIndex(); // BEGIN from ifOp @@ -1489,7 +1466,7 @@ bool AstOperatorNode::generateCode_phase2(codeGen &gen, bool noCost, // We can reuse src1 for the body of the conditional; however, keep the value here // so that we can use it for the branch fix below. - Register src1_copy = src1; + Dyninst::Register src1_copy = src1; if (loperand->decRefCount()) gen.rs()->freeRegister(src1); @@ -1529,16 +1506,16 @@ bool AstOperatorNode::generateCode_phase2(codeGen &gen, bool noCost, // This backtracks over current code. // If/when we vectorize, we can do this in a two-pass arrangement (void) emitA(ifOp, src1_copy, 0, - (Register) codeGen::getDisplacement(thenSkipStart, elseStartIndex), + (Dyninst::Register) codeGen::getDisplacement(thenSkipStart, elseStartIndex), gen, rc_no_control, noCost); // Now we can free the register - // Register has already been freed; we're just re-using it. + // Dyninst::Register has already been freed; we're just re-using it. //gen.rs()->freeRegister(src1); gen.setIndex(elseStartIndex); } // END from ifOp - retReg = REG_NULL; + retReg = Dyninst::Null_Register; break; } case doOp: { @@ -1547,26 +1524,26 @@ bool AstOperatorNode::generateCode_phase2(codeGen &gen, bool noCost, } case getAddrOp: { switch(loperand->getoType()) { - case variableAddr: - if (retReg == REG_NULL) { + case operandType::variableAddr: + if (retReg == Dyninst::Null_Register) { retReg = allocateAndKeep(gen, noCost); } assert (loperand->getOVar()); loperand->emitVariableLoad(loadConstOp, retReg, retReg, gen, noCost, gen.rs(), size, gen.point(), gen.addrSpace()); break; - case variableValue: - if (retReg == REG_NULL) { + case operandType::variableValue: + if (retReg == Dyninst::Null_Register) { retReg = allocateAndKeep(gen, noCost); } assert (loperand->getOVar()); loperand->emitVariableLoad(loadOp, retReg, retReg, gen, noCost, gen.rs(), size, gen.point(), gen.addrSpace()); break; - case DataAddr: + case operandType::DataAddr: { addr = reinterpret_cast
(loperand->getOValue()); - if (retReg == REG_NULL) { + if (retReg == Dyninst::Null_Register) { retReg = allocateAndKeep(gen, noCost); } assert(!loperand->getOVar()); @@ -1574,22 +1551,21 @@ bool AstOperatorNode::generateCode_phase2(codeGen &gen, bool noCost, noCost, gen.rs(), size, gen.point(), gen.addrSpace()); } break; - case FrameAddr: { + case operandType::FrameAddr: { // load the address fp + addr into dest - if (retReg == REG_NULL) + if (retReg == Dyninst::Null_Register) retReg = allocateAndKeep(gen, noCost); - Register temp = gen.rs()->getScratchRegister(gen, noCost); + Dyninst::Register temp = gen.rs()->getScratchRegister(gen, noCost); addr = (Address) loperand->getOValue(); emitVload(loadFrameAddr, addr, temp, retReg, gen, noCost, gen.rs(), size, gen.point(), gen.addrSpace()); break; } - case RegOffset: { - assert(loperand); + case operandType::RegOffset: { assert(loperand->operand()); // load the address reg + addr into dest - if (retReg == REG_NULL) { + if (retReg == Dyninst::Null_Register) { retReg = allocateAndKeep(gen, noCost); } addr = (Address) loperand->operand()->getOValue(); @@ -1598,7 +1574,7 @@ bool AstOperatorNode::generateCode_phase2(codeGen &gen, bool noCost, noCost, gen.rs(), size, gen.point(), gen.addrSpace()); break; } - case DataIndir: + case operandType::DataIndir: // taking address of pointer de-ref returns the original // expression, so we simple generate the left child's // code to get the address @@ -1608,19 +1584,20 @@ bool AstOperatorNode::generateCode_phase2(codeGen &gen, bool noCost, retReg)) ERROR_RETURN; // Broken refCounts? break; - case origRegister: + case operandType::origRegister: // Added 2NOV11 Bernat - some variables live in original registers, // and so we need to be able to dereference their contents. if (!loperand->generateCode_phase2(gen, noCost, addr, retReg)) ERROR_RETURN; break; default: - cerr << "Uh oh, unknown loperand type in getAddrOp: " << loperand->getoType() << endl; + cerr << "Uh oh, unknown loperand type in getAddrOp: " << static_cast(loperand->getoType()) << endl; cerr << "\t Generating ast " << hex << this << dec << endl; assert(0); } break; } case storeOp: { + if(!roperand) { return false; } bool result = generateOptimizedAssignment(gen, size, noCost); if (result) break; @@ -1640,12 +1617,12 @@ bool AstOperatorNode::generateCode_phase2(codeGen &gen, bool noCost, src2 = gen.rs()->allocateRegister(gen, noCost); switch (loperand->getoType()) { - case variableValue: + case operandType::variableValue: loperand->emitVariableStore(storeOp, src1, src2, gen, noCost, gen.rs(), size, gen.point(), gen.addrSpace()); loperand->decUseCount(gen); break; - case DataAddr: + case operandType::DataAddr: addr = (Address) loperand->getOValue(); assert(loperand->getOVar() == NULL); emitVstore(storeOp, src1, src2, addr, gen, @@ -1654,13 +1631,13 @@ bool AstOperatorNode::generateCode_phase2(codeGen &gen, bool noCost, // so need to decrement the refcount by hand loperand->decUseCount(gen); break; - case FrameAddr: + case operandType::FrameAddr: addr = (Address) loperand->getOValue(); emitVstore(storeFrameRelativeOp, src1, src2, addr, gen, noCost, gen.rs(), size, gen.point(), gen.addrSpace()); loperand->decUseCount(gen); break; - case RegOffset: { + case operandType::RegOffset: { assert(loperand->operand()); addr = (Address) loperand->operand()->getOValue(); @@ -1675,7 +1652,7 @@ bool AstOperatorNode::generateCode_phase2(codeGen &gen, bool noCost, loperand->decUseCount(gen); break; } - case DataIndir: { + case operandType::DataIndir: { // store to a an expression (e.g. an array or field use) // *(+ base offset) = src1 if (!loperand->operand()->generateCode_phase2(gen, @@ -1691,32 +1668,32 @@ bool AstOperatorNode::generateCode_phase2(codeGen &gen, bool noCost, loperand->decUseCount(gen); break; } - case origRegister: - gen.rs()->writeProgramRegister(gen, (Register)(long)loperand->getOValue(), + case operandType::origRegister: + gen.rs()->writeProgramRegister(gen, (Dyninst::Register)(long)loperand->getOValue(), src1, getSize()); //emitStorePreviousStackFrameRegister((Address) loperand->getOValue(), //src1, gen, getSize(), noCost); loperand->decUseCount(gen); break; - case Param: - case ParamAtCall: - case ParamAtEntry: { - boost::shared_ptr lnode = - boost::dynamic_pointer_cast(loperand); + case operandType::Param: + case operandType::ParamAtCall: + case operandType::ParamAtEntry: { + dyncompat::shared_ptr lnode = + dyncompat::dynamic_pointer_cast(loperand); emitR(getParamOp, (Address)lnode->oValue, src1, src2, gen, noCost, gen.point(), gen.addrSpace()->multithread_capable()); loperand->decUseCount(gen); break; } - case ReturnVal: - emitR(getRetValOp, Null_Register, + case operandType::ReturnVal: + emitR(getRetValOp, Dyninst::Null_Register, src1, src2, gen, noCost, gen.point(), gen.addrSpace()->multithread_capable()); loperand->decUseCount(gen); break; - case ReturnAddr: - emitR(getRetAddrOp, Null_Register, + case operandType::ReturnAddr: + emitR(getRetAddrOp, Dyninst::Null_Register, src1, src2, gen, noCost, gen.point(), gen.addrSpace()->multithread_capable()); break; @@ -1735,11 +1712,11 @@ bool AstOperatorNode::generateCode_phase2(codeGen &gen, bool noCost, if (roperand->decRefCount()) gen.rs()->freeRegister(src1); gen.rs()->freeRegister(src2); - retReg = REG_NULL; + retReg = Dyninst::Null_Register; break; } case storeIndirOp: { - + if(!roperand) { return false; } if (!roperand->generateCode_phase2(gen, noCost, addr, src1)) ERROR_RETURN; if (!loperand->generateCode_phase2(gen, noCost, addr, src2)) ERROR_RETURN; REGISTER_CHECK(src1); @@ -1749,12 +1726,12 @@ bool AstOperatorNode::generateCode_phase2(codeGen &gen, bool noCost, gen.rs()->freeRegister(src1); if (loperand->decRefCount()) gen.rs()->freeRegister(src2); - retReg = REG_NULL; + retReg = Dyninst::Null_Register; break; } case trampPreamble: { // This ast cannot be shared because it doesn't return a register - retReg = REG_NULL; + retReg = Dyninst::Null_Register; break; } case plusOp: @@ -1772,19 +1749,17 @@ bool AstOperatorNode::generateCode_phase2(codeGen &gen, bool noCost, case geOp: default: { + if(!roperand) { return false; } bool signedOp = IsSignedOperation(loperand->getType(), roperand->getType()); - src1 = Null_Register; - right_dest = Null_Register; - if (loperand) { + src1 = Dyninst::Null_Register; + right_dest = Dyninst::Null_Register; if (!loperand->generateCode_phase2(gen, noCost, addr, src1)) ERROR_RETURN; REGISTER_CHECK(src1); - } - if (roperand && - (roperand->getoType() == Constant) && + if ((roperand->getoType() == operandType::Constant) && doNotOverflow((int64_t)roperand->getOValue())) { - if (retReg == REG_NULL) { + if (retReg == Dyninst::Null_Register) { retReg = allocateAndKeep(gen, noCost); ast_printf("Operator node, const RHS, allocated register %u\n", retReg); } @@ -1793,7 +1768,7 @@ bool AstOperatorNode::generateCode_phase2(codeGen &gen, bool noCost, emitImm(op, src1, (RegValue) roperand->getOValue(), retReg, gen, noCost, gen.rs(), signedOp); - if (src1 != Null_Register && loperand->decRefCount()) + if (src1 != Dyninst::Null_Register && loperand->decRefCount()) gen.rs()->freeRegister(src1); // We do not .generateCode for roperand, so need to update its @@ -1801,20 +1776,18 @@ bool AstOperatorNode::generateCode_phase2(codeGen &gen, bool noCost, roperand->decUseCount(gen); } else { - if (roperand) { if (!roperand->generateCode_phase2(gen, noCost, addr, right_dest)) ERROR_RETURN; REGISTER_CHECK(right_dest); - } - if (retReg == REG_NULL) { + if (retReg == Dyninst::Null_Register) { retReg = allocateAndKeep(gen, noCost); } emitV(op, src1, right_dest, retReg, gen, noCost, gen.rs(), size, gen.point(), gen.addrSpace(), signedOp); - if (src1 != Null_Register && loperand->decRefCount()) { + if (src1 != Dyninst::Null_Register && loperand->decRefCount()) { // Don't free inputs until afterwards; we have _no_ idea gen.rs()->freeRegister(src1); } // what the underlying code might do with a temporary register. - if (right_dest != Null_Register && roperand->decRefCount()) + if (right_dest != Dyninst::Null_Register && roperand->decRefCount()) gen.rs()->freeRegister(right_dest); } } @@ -1825,34 +1798,30 @@ bool AstOperatorNode::generateCode_phase2(codeGen &gen, bool noCost, bool AstOperandNode::generateCode_phase2(codeGen &gen, bool noCost, Address &, - Register &retReg) { + Dyninst::Register &retReg) { RETURN_KEPT_REG(retReg); Address addr = ADDR_NULL; - Register src = Null_Register; + Dyninst::Register src = Dyninst::Null_Register; -#if defined(ASTDEBUG) - sprintf(errorLine,"### location: %p ###\n", (void*)gen.point()); - logLine(errorLine); -#endif // Allocate a register to return - if (oType != DataReg) { - if (retReg == REG_NULL) { + if (oType != operandType::DataReg) { + if (retReg == Dyninst::Null_Register) { retReg = allocateAndKeep(gen, noCost); } } - Register temp; + Dyninst::Register temp; int tSize; int len; BPatch_type *Type; switch (oType) { - case Constant: + case operandType::Constant: assert(oVar == NULL); emitVload(loadConstOp, (Address)oValue, retReg, retReg, gen, noCost, gen.rs(), size, gen.point(), gen.addrSpace()); break; - case DataIndir: + case operandType::DataIndir: if (!operand_->generateCode_phase2(gen, noCost, addr, src)) ERROR_RETURN; REGISTER_CHECK(src); Type = const_cast (getType()); @@ -1865,26 +1834,26 @@ bool AstOperandNode::generateCode_phase2(codeGen &gen, bool noCost, if (operand_->decRefCount()) gen.rs()->freeRegister(src); break; - case DataReg: - retReg = (Register) (long) oValue; + case operandType::DataReg: + retReg = (Dyninst::Register) (long) oValue; break; - case origRegister: - gen.rs()->readProgramRegister(gen, (Register)(long)oValue, retReg, size); + case operandType::origRegister: + gen.rs()->readProgramRegister(gen, (Dyninst::Register)(long)oValue, retReg, size); //emitLoadPreviousStackFrameRegister((Address) oValue, retReg, gen, //size, noCost); break; - case variableAddr: + case operandType::variableAddr: assert(oVar); emitVariableLoad(loadConstOp, retReg, retReg, gen, noCost, gen.rs(), size, gen.point(), gen.addrSpace()); break; - case variableValue: + case operandType::variableValue: assert(oVar); emitVariableLoad(loadOp, retReg, retReg, gen, noCost, gen.rs(), size, gen.point(), gen.addrSpace()); break; - case ReturnVal: - src = emitR(getRetValOp, 0, Null_Register, retReg, gen, noCost, gen.point(), + case operandType::ReturnVal: + src = emitR(getRetValOp, 0, Dyninst::Null_Register, retReg, gen, noCost, gen.point(), gen.addrSpace()->multithread_capable()); REGISTER_CHECK(src); if (src != retReg) { @@ -1893,8 +1862,8 @@ bool AstOperandNode::generateCode_phase2(codeGen &gen, bool noCost, emitImm(orOp, src, 0, retReg, gen, noCost, gen.rs()); } break; - case ReturnAddr: - src = emitR(getRetAddrOp, 0, Null_Register, retReg, gen, noCost, gen.point(), + case operandType::ReturnAddr: + src = emitR(getRetAddrOp, 0, Dyninst::Null_Register, retReg, gen, noCost, gen.point(), gen.addrSpace()->multithread_capable()); REGISTER_CHECK(src); if (src != retReg) { @@ -1903,25 +1872,25 @@ bool AstOperandNode::generateCode_phase2(codeGen &gen, bool noCost, emitImm(orOp, src, 0, retReg, gen, noCost, gen.rs()); } break; - case Param: - case ParamAtCall: - case ParamAtEntry: { + case operandType::Param: + case operandType::ParamAtCall: + case operandType::ParamAtEntry: { opCode paramOp = undefOp; switch(oType) { - case Param: + case operandType::Param: paramOp = getParamOp; break; - case ParamAtCall: + case operandType::ParamAtCall: paramOp = getParamAtCallOp; break; - case ParamAtEntry: + case operandType::ParamAtEntry: paramOp = getParamAtEntryOp; break; default: assert(0); break; } - src = emitR(paramOp, (Address)oValue, Null_Register, + src = emitR(paramOp, (Address)oValue, Dyninst::Null_Register, retReg, gen, noCost, gen.point(), gen.addrSpace()->multithread_capable()); REGISTER_CHECK(src); @@ -1932,19 +1901,19 @@ bool AstOperandNode::generateCode_phase2(codeGen &gen, bool noCost, } } break; - case DataAddr: + case operandType::DataAddr: assert(oVar == NULL); addr = reinterpret_cast
(oValue); emitVload(loadOp, addr, retReg, retReg, gen, noCost, NULL, size, gen.point(), gen.addrSpace()); break; - case FrameAddr: + case operandType::FrameAddr: addr = (Address) oValue; temp = gen.rs()->allocateRegister(gen, noCost); emitVload(loadFrameRelativeOp, addr, temp, retReg, gen, noCost, gen.rs(), size, gen.point(), gen.addrSpace()); gen.rs()->freeRegister(temp); break; - case RegOffset: + case operandType::RegOffset: // Prepare offset from value in any general register (not just fp). // This AstNode holds the register number, and loperand holds offset. assert(operand_); @@ -1952,7 +1921,7 @@ bool AstOperandNode::generateCode_phase2(codeGen &gen, bool noCost, emitVload(loadRegRelativeOp, addr, (long)oValue, retReg, gen, noCost, gen.rs(), size, gen.point(), gen.addrSpace()); break; - case ConstantString: + case operandType::ConstantString: // XXX This is for the std::string type. If/when we fix the std::string type // to make it less of a hack, we'll need to change this. len = strlen((char *)oValue) + 1; @@ -1976,7 +1945,7 @@ bool AstOperandNode::generateCode_phase2(codeGen &gen, bool noCost, break; default: fprintf(stderr, "[%s:%d] ERROR: Unknown operand type %d in AstOperandNode generation\n", - __FILE__, __LINE__, oType); + __FILE__, __LINE__, static_cast(oType)); return false; break; } @@ -1986,14 +1955,14 @@ bool AstOperandNode::generateCode_phase2(codeGen &gen, bool noCost, bool AstMemoryNode::generateCode_phase2(codeGen &gen, bool noCost, Address &, - Register &retReg) { + Dyninst::Register &retReg) { RETURN_KEPT_REG(retReg); const BPatch_memoryAccess* ma; const BPatch_addrSpec_NP *start; const BPatch_countSpec_NP *count; - if (retReg == REG_NULL) + if (retReg == Dyninst::Null_Register) retReg = allocateAndKeep(gen, noCost); switch(mem_) { case EffectiveAddr: { @@ -2093,7 +2062,7 @@ bool AstCallNode::initRegisters(codeGen &gen) { bool AstCallNode::generateCode_phase2(codeGen &gen, bool noCost, Address &, - Register &retReg) { + Dyninst::Register &retReg) { // We call this anyway... not that we'll ever be kept. // Well... if we can somehow know a function is entirely // dependent on arguments (a flag?) we can keep it around. @@ -2116,7 +2085,7 @@ bool AstCallNode::generateCode_phase2(codeGen &gen, bool noCost, assert(use_func); // Otherwise we've got trouble... } - Register tmp = 0; + Dyninst::Register tmp = 0; if (use_func && !callReplace_) { tmp = emitFuncCall(callOp, gen, args_, @@ -2140,11 +2109,11 @@ bool AstCallNode::generateCode_phase2(codeGen &gen, bool noCost, // TODO: put register allocation here and have emitCall just // move the return result. - if (tmp == REG_NULL) { + if (tmp == Dyninst::Null_Register) { // Happens in function replacement... didn't allocate // a return register. } - else if (retReg == REG_NULL) { + else if (retReg == Dyninst::Null_Register) { //emitFuncCall allocated tmp; we can use it, but let's see // if we should keep it around. retReg = tmp; @@ -2167,9 +2136,9 @@ bool AstCallNode::generateCode_phase2(codeGen &gen, bool noCost, bool AstSequenceNode::generateCode_phase2(codeGen &gen, bool noCost, Address &, - Register &retReg) { + Dyninst::Register &retReg) { RETURN_KEPT_REG(retReg); - Register tmp = REG_NULL; + Dyninst::Register tmp = Dyninst::Null_Register; Address unused = ADDR_NULL; if (sequence_.size() == 0) { @@ -2184,7 +2153,7 @@ bool AstSequenceNode::generateCode_phase2(codeGen &gen, bool noCost, tmp)) ERROR_RETURN; if (sequence_[i]->decRefCount()) gen.rs()->freeRegister(tmp); - tmp = REG_NULL; + tmp = Dyninst::Null_Register; } // We keep the last one @@ -2197,19 +2166,19 @@ bool AstSequenceNode::generateCode_phase2(codeGen &gen, bool noCost, bool AstVariableNode::generateCode_phase2(codeGen &gen, bool noCost, Address &addr, - Register &retReg) { + Dyninst::Register &retReg) { return ast_wrappers_[index]->generateCode_phase2(gen, noCost, addr, retReg); } bool AstOriginalAddrNode::generateCode_phase2(codeGen &gen, bool noCost, Address &, - Register &retReg) { + Dyninst::Register &retReg) { RETURN_KEPT_REG(retReg); - if (retReg == REG_NULL) { + if (retReg == Dyninst::Null_Register) { retReg = allocateAndKeep(gen, noCost); } - if (retReg == REG_NULL) return false; + if (retReg == Dyninst::Null_Register) return false; emitVload(loadConstOp, (Address) gen.point()->addr_compat(), @@ -2220,11 +2189,11 @@ bool AstOriginalAddrNode::generateCode_phase2(codeGen &gen, bool AstActualAddrNode::generateCode_phase2(codeGen &gen, bool noCost, Address &, - Register &retReg) { - if (retReg == REG_NULL) { + Dyninst::Register &retReg) { + if (retReg == Dyninst::Null_Register) { retReg = allocateAndKeep(gen, noCost); } - if (retReg == REG_NULL) return false; + if (retReg == Dyninst::Null_Register) return false; emitVload(loadConstOp, (Address) gen.currAddr(), @@ -2237,7 +2206,7 @@ bool AstActualAddrNode::generateCode_phase2(codeGen &gen, bool AstDynamicTargetNode::generateCode_phase2(codeGen &gen, bool noCost, Address & retAddr, - Register &retReg) + Dyninst::Register &retReg) { if (gen.point()->type() != instPoint::PreCall && gen.point()->type() != instPoint::FuncExit && @@ -2247,10 +2216,10 @@ bool AstDynamicTargetNode::generateCode_phase2(codeGen &gen, InstructionAPI::Instruction insn = gen.point()->block()->getInsn(gen.point()->block()->last()); if (insn.getCategory() == c_ReturnInsn) { // if this is a return instruction our AST reads the top stack value - if (retReg == REG_NULL) { + if (retReg == Dyninst::Null_Register) { retReg = allocateAndKeep(gen, noCost); } - if (retReg == REG_NULL) return false; + if (retReg == Dyninst::Null_Register) return false; #if defined (arch_x86) emitVload(loadRegRelativeOp, @@ -2294,7 +2263,7 @@ bool AstDynamicTargetNode::generateCode_phase2(codeGen &gen, bool AstScrambleRegistersNode::generateCode_phase2(codeGen &gen, bool , Address&, - Register& ) + Dyninst::Register& ) { (void)gen; // unused #if defined(arch_x86_64) @@ -2307,45 +2276,6 @@ bool AstScrambleRegistersNode::generateCode_phase2(codeGen &gen, return true; } -#if defined(AST_PRINT) -std::string getOpString(opCode op) -{ - switch (op) { - case plusOp: return("+"); - case minusOp: return("-"); - case xorOp: return("^"); - case timesOp: return("*"); - case divOp: return("/"); - case lessOp: return("<"); - case leOp: return("<="); - case greaterOp: return(">"); - case geOp: return(">="); - case eqOp: return("=="); - case neOp: return("!="); - case loadOp: return("lda"); - case loadConstOp: return("load"); - case storeOp: return("="); - case ifOp: return("if"); - case ifMCOp: return("ifMC"); - case whileOp: return("while") ; - case doOp: return("while") ; - case trampPreamble: return("preTramp"); - case branchOp: return("goto"); - case noOp: return("nop"); - case andOp: return("and"); - case orOp: return("or"); - case loadIndirOp: return("load&"); - case storeIndirOp: return("=&"); - case loadFrameRelativeOp: return("load $fp"); - case loadRegRelativeOp: return("load $reg"); - case loadFrameAddr: return("$fp"); - case storeFrameRelativeOp: return("store $fp"); - case getAddrOp: return("&"); - default: return("ERROR"); - } -} -#endif - #undef MIN #define MIN(x,y) ((x)>(y) ? (y) : (x)) #undef MAX @@ -2400,16 +2330,16 @@ int AstOperatorNode::costHelper(enum CostStyleType costStyle) const { int AstOperandNode::costHelper(enum CostStyleType costStyle) const { int total = 0; - if (oType == Constant) { + if (oType == operandType::Constant) { total = getInsnCost(loadConstOp); - } else if (oType == DataIndir) { + } else if (oType == operandType::DataIndir) { total = getInsnCost(loadIndirOp); total += operand()->costHelper(costStyle); - } else if (oType == DataAddr) { + } else if (oType == operandType::DataAddr) { total = getInsnCost(loadOp); - } else if (oType == DataReg) { + } else if (oType == operandType::DataReg) { total = getInsnCost(loadIndirOp); - } else if (oType == Param || oType == ParamAtCall || oType == ParamAtEntry) { + } else if (oType == operandType::Param || oType == operandType::ParamAtCall || oType == operandType::ParamAtEntry) { total = getInsnCost(getParamOp); } return total; @@ -2440,72 +2370,6 @@ int AstVariableNode::costHelper(enum CostStyleType /*costStyle*/) const{ return total; } -#if defined(AST_PRINT) -void AstNode::print() const { - if (this) { -#if defined(ASTDEBUG) - bpfatal("{%d}", referenceCount) ; -#endif - if (type == operandNode) { - if (oType == Constant) { - fprintf(stderr,"%d", (int)(Address) oValue); - } else if (oType == ConstantString) { - fprintf(stderr," %s", (char *)oValue); - } else if (oType == DataIndir) { - fprintf(stderr," @["); - loperand->print(); - fprintf(stderr,"]"); - } else if (oType == DataReg) { - fprintf(stderr," reg%d ",(int)(Address)oValue); - loperand->print(); - } else if (oType == Param || oType == ParamAtCall || oType == ParamAtEntry) { - fprintf(stderr," param[%d]", (int)(Address) oValue); - } else if (oType == ReturnVal) { - fprintf(stderr,"retVal"); - } else if (oType == ReturnAddr) { - fprintf(stderr, "retAddr"); - } else if (oType == DataAddr) { - if(!oVar) - { - fprintf(stderr," [0x%lx]", (long) oValue); - } - else - { - fprintf(stderr," [%s]", oVar->symTabName().c_str()); - } - - } else if (oType == FrameAddr) { - fprintf(stderr," [$fp + %d]", (int)(Address) oValue); - } else if (oType == RegOffset) { - fprintf(stderr," [$%d + %d]", (int)(Address) loperand->getOValue(), (int)(Address) oValue); - } else if (oType == EffectiveAddr) { - fprintf(stderr," <>"); - } else if (oType == BytesAccessed) { - fprintf(stderr," <>"); - } else { - fprintf(stderr," "); - } - } else if (type == opCodeNode_t) { - cerr << "(" << getOpString(op); - if (loperand) loperand->print(); - if (roperand) roperand->print(); - if (eoperand) eoperand->print(); - fprintf(stderr,")\n"); - } else if (type == callNode) { - cerr << "(" << callee; - for (unsigned u = 0; u < operands.size(); u++) - operands[u]->print(); - fprintf(stderr,")\n"); - } else if (type == sequenceNode_t) { - if (loperand) loperand->print(); - fprintf(stderr,","); - if (roperand) roperand->print(); - fprintf(stderr,"\n"); - } - } -} -#endif - BPatch_type *AstNode::checkType(BPatch_function*) { return BPatch::bpatch->type_Untyped; } @@ -2576,20 +2440,6 @@ BPatch_type *AstOperatorNode::checkType(BPatch_function* func) { ret = BPatch::bpatch->type_Untyped; } -#if defined(ASTDEBUG) - // it would be useful to have some indication of what the type applied to - // (currently it appears to be copious amounts of contextless junk) - if (ret) { - logLine(" type is "); - if (ret->getName()){ - logLine(ret->getName()); - } else { - logLine(" "); - logLine("\n"); - } - } -#endif - // remember what type we are setType(ret); @@ -2616,18 +2466,18 @@ BPatch_type *AstOperandNode::checkType(BPatch_function* func) if (type == BPatch::bpatch->type_Error) errorFlag = true; - if (oType == DataIndir) { + if (oType == operandType::DataIndir) { // XXX Should really be pointer to lType -- jkh 7/23/99 ret = BPatch::bpatch->type_Untyped; } - else if ((oType == Param) || (oType == ParamAtCall) || - (oType == ParamAtEntry) || (oType == ReturnVal) - || (oType == ReturnAddr)) { + else if ((oType == operandType::Param) || (oType == operandType::ParamAtCall) || + (oType == operandType::ParamAtEntry) || (oType == operandType::ReturnVal) + || (oType == operandType::ReturnAddr)) { if(func) { switch(oType) { - case ReturnVal: + case operandType::ReturnVal: { ret = func->getReturnType(); if(!ret || (ret->isCompatible(BPatch::bpatch->builtInTypes->findBuiltInType("void")))) { @@ -2649,7 +2499,7 @@ BPatch_type *AstOperandNode::checkType(BPatch_function* func) ret = BPatch::bpatch->type_Untyped; } } - else if (oType == origRegister) { + else if (oType == operandType::origRegister) { ret = BPatch::bpatch->type_Untyped; } else { @@ -2663,19 +2513,6 @@ BPatch_type *AstOperandNode::checkType(BPatch_function* func) ret = BPatch::bpatch->type_Untyped; } -#if defined(ASTDEBUG) - // it would be useful to have some indication of what the type applied to - // (currently it appears to be copious amounts of contextless junk) - if (ret) { - logLine(" type is "); - if (ret->getName()) - logLine(ret->getName()); - else - logLine(" "); - logLine("\n"); - } -#endif - // remember what type we are setType(ret); @@ -2709,19 +2546,6 @@ BPatch_type *AstCallNode::checkType(BPatch_function* func) { ret = BPatch::bpatch->type_Untyped; } -#if defined(ASTDEBUG) - // it would be useful to have some indication of what the type applied to - // (currently it appears to be copious amounts of contextless junk) - if (ret) { - logLine(" type is "); - if (ret->getName()) - logLine(ret->getName()); - else - logLine(" "); - logLine("\n"); - } -#endif - // remember what type we are setType(ret); @@ -2758,19 +2582,6 @@ BPatch_type *AstSequenceNode::checkType(BPatch_function* func) { ret = BPatch::bpatch->type_Untyped; } -#if defined(ASTDEBUG) - // it would be useful to have some indication of what the type applied to - // (currently it appears to be copious amounts of contextless junk) - if (ret) { - logLine(" type is "); - if (ret->getName()) - logLine(ret->getName()); - else - logLine(" "); - logLine("\n"); - } -#endif - // remember what type we are setType(ret); @@ -2778,19 +2589,6 @@ BPatch_type *AstSequenceNode::checkType(BPatch_function* func) { } bool AstNode::accessesParam() { -#if 0 - fprintf(stderr, "Undefined call to getChildren for type: "); - if (dynamic_cast(this)) fprintf(stderr, "nullNode\n"); - else if (dynamic_cast(this)) fprintf(stderr, "operatorNode\n"); - else if (dynamic_cast(this)) fprintf(stderr, "operandNode\n"); - else if (dynamic_cast(this)) fprintf(stderr, "callNode\n"); - else if (dynamic_cast(this)) fprintf(stderr, "seqNode\n"); - else if (dynamic_cast(this)) fprintf(stderr, "varNode\n"); - else if (dynamic_cast(this)) fprintf(stderr, "insnNode\n"); - else if (dynamic_cast(this)) fprintf(stderr, "miniTrampNode\n"); - else if (dynamic_cast(this)) fprintf(stderr, "memoryNode\n"); - else fprintf(stderr, "unknownNode\n"); -#endif return false; } @@ -2870,12 +2668,12 @@ bool AstOperatorNode::canBeKept() const { bool AstOperandNode::canBeKept() const { switch (oType) { - case DataReg: - case DataIndir: - case RegOffset: - case origRegister: - case DataAddr: - case variableValue: + case operandType::DataReg: + case operandType::DataIndir: + case operandType::RegOffset: + case operandType::origRegister: + case operandType::DataAddr: + case operandType::variableValue: return false; default: break; @@ -3214,7 +3012,7 @@ void AstVariableNode::setVariableAST(codeGen &gen){ index = 0; return; } - Address addr = gen.point()->addr_compat(); //Offset of inst point from function base address + Address addr = gen.point()->addr_compat(); //Dyninst::Offset of inst point from function base address bool found = false; for(unsigned i=0; i< ranges_->size();i++){ if((*ranges_)[i].first<=addr && addr<=(*ranges_)[i].second) { @@ -3336,13 +3134,13 @@ bool AstOperatorNode::usesAppRegister() const { } bool AstOperandNode::usesAppRegister() const { - if (oType == AstNode::FrameAddr || - oType == AstNode::RegOffset || - oType == AstNode::origRegister || - oType == AstNode::Param || - oType == AstNode::ParamAtEntry || - oType == AstNode::ParamAtCall || - oType == AstNode::ReturnVal) + if (oType == AstNode::operandType::FrameAddr || + oType == AstNode::operandType::RegOffset || + oType == AstNode::operandType::origRegister || + oType == AstNode::operandType::Param || + oType == AstNode::operandType::ParamAtEntry || + oType == AstNode::operandType::ParamAtCall || + oType == AstNode::operandType::ReturnVal) { return true; } @@ -3418,7 +3216,7 @@ bool AstScrambleRegistersNode::usesAppRegister() const return true; } -void regTracker_t::addKeptRegister(codeGen &gen, AstNode *n, Register reg) { +void regTracker_t::addKeptRegister(codeGen &gen, AstNode *n, Dyninst::Register reg) { assert(n); if (tracker.find(n) != tracker.end()) { assert(tracker[n].keptRegister == reg); @@ -3439,17 +3237,17 @@ void regTracker_t::removeKeptRegister(codeGen &gen, AstNode *n) { tracker.erase(iter); } -Register regTracker_t::hasKeptRegister(AstNode *n) { +Dyninst::Register regTracker_t::hasKeptRegister(AstNode *n) { auto iter = tracker.find(n); if (iter == tracker.end()) - return REG_NULL; + return Dyninst::Null_Register; else return iter->second.keptRegister; } // Find if the given register is "owned" by an AST node, // and if so nuke it. -bool regTracker_t::stealKeptRegister(Register r) { +bool regTracker_t::stealKeptRegister(Dyninst::Register r) { ast_printf("STEALING kept register %u for someone else\n", r); for (auto iter = tracker.begin(); iter != tracker.end(); ++iter) { if (iter->second.keptRegister == r) { @@ -3531,7 +3329,7 @@ int_variable* AstOperandNode::lookUpVar(AddressSpace* as) return NULL; } -void AstOperandNode::emitVariableLoad(opCode op, Register src2, Register dest, codeGen& gen, +void AstOperandNode::emitVariableLoad(opCode op, Dyninst::Register src2, Dyninst::Register dest, codeGen& gen, bool noCost, registerSpace* rs, int size_, const instPoint* point, AddressSpace* as) { @@ -3546,7 +3344,7 @@ void AstOperandNode::emitVariableLoad(opCode op, Register src2, Register dest, c } } -void AstOperandNode::emitVariableStore(opCode op, Register src1, Register src2, codeGen& gen, +void AstOperandNode::emitVariableStore(opCode op, Dyninst::Register src1, Dyninst::Register src2, codeGen& gen, bool noCost, registerSpace* rs, int size_, const instPoint* point, AddressSpace* as) { @@ -3588,7 +3386,7 @@ bool AstNode::generate(Point *point, Buffer &buffer) { bool AstSnippetNode::generateCode_phase2(codeGen &gen, bool, Address &, - Register &) { + Dyninst::Register &) { Buffer buf(gen.currAddr(), 1024); if (!snip_->generate(gen.point(), buf)) return false; gen.copy(buf.start_ptr(), buf.size()); @@ -3696,21 +3494,21 @@ std::string AstMemoryNode::format(std::string indent) { std::string AstNode::convert(operandType type) { switch(type) { - case Constant: return "Constant"; - case ConstantString: return "ConstantString"; - case DataReg: return "DataReg"; - case DataIndir: return "DataIndir"; - case Param: return "Param"; - case ParamAtCall: return "ParamAtCall"; - case ParamAtEntry: return "ParamAtEntry"; - case ReturnVal: return "ReturnVal"; - case ReturnAddr: return "ReturnAddr"; - case DataAddr: return "DataAddr"; - case FrameAddr: return "FrameAddr"; - case RegOffset: return "RegOffset"; - case origRegister: return "OrigRegister"; - case variableAddr: return "variableAddr"; - case variableValue: return "variableValue"; + case operandType::Constant: return "Constant"; + case operandType::ConstantString: return "ConstantString"; + case operandType::DataReg: return "DataReg"; + case operandType::DataIndir: return "DataIndir"; + case operandType::Param: return "Param"; + case operandType::ParamAtCall: return "ParamAtCall"; + case operandType::ParamAtEntry: return "ParamAtEntry"; + case operandType::ReturnVal: return "ReturnVal"; + case operandType::ReturnAddr: return "ReturnAddr"; + case operandType::DataAddr: return "DataAddr"; + case operandType::FrameAddr: return "FrameAddr"; + case operandType::RegOffset: return "RegOffset"; + case operandType::origRegister: return "OrigRegister"; + case operandType::variableAddr: return "variableAddr"; + case operandType::variableValue: return "variableValue"; default: return "UnknownOperand"; } } @@ -3777,7 +3575,7 @@ bool AstOperandNode::initRegisters(codeGen &g) { } // If we're an origRegister, override its state as live. - if (oType == origRegister) { + if (oType == operandType::origRegister) { Address origReg = (Address) oValue; // Mark that register as live so we are sure to save it. registerSlot *r = (*(g.rs()))[origReg]; diff --git a/dyninstAPI/src/ast.h b/dyninstAPI/src/ast.h index 73b39a3d20..1e5fb90105 100644 --- a/dyninstAPI/src/ast.h +++ b/dyninstAPI/src/ast.h @@ -38,11 +38,14 @@ // +#include +#include +#include #include #include #include -#include "common/src/Types.h" +#include "dyn_register.h" #include "Point.h" #include "BPatch_snippet.h" @@ -56,22 +59,16 @@ class AddressSpace; class instPoint; class func_instance; class int_variable; - class codeGen; -class codeRange; -class BPatch_instruction; // Memory, etc. are at BPatch. Might want to move 'em. -//class BPatch_type; class image_variable; -// a register number, e.g. [0,31] -// typedef int reg; // see new Register type in "common/src/Types.h" #include "opcode.h" -// Register retention mechanism... +// Dyninst::Register retention mechanism... // If we've already calculated a result, then we want to reuse it if it's // still available. This means it was calculated along a path that reaches the // current point (not inside a conditional) and the register hasn't been @@ -94,9 +91,9 @@ class image_variable; // with the lowest usage count. class AstNode; -typedef boost::shared_ptr AstNodePtr; +typedef dyncompat::shared_ptr AstNodePtr; class AstMiniTrampNode; -typedef boost::shared_ptr AstMiniTrampNodePtr; +typedef dyncompat::shared_ptr AstMiniTrampNodePtr; typedef enum { cfj_unset = 0, @@ -111,9 +108,9 @@ class regTracker_t { public: class commonExpressionTracker { public: - Register keptRegister; + Dyninst::Register keptRegister; int keptLevel; - commonExpressionTracker() : keptRegister(REG_NULL), keptLevel(-1) {} + commonExpressionTracker() : keptRegister(Dyninst::Null_Register), keptLevel(-1) {} }; int condLevel; @@ -124,10 +121,10 @@ class regTracker_t { std::unordered_map tracker; - void addKeptRegister(codeGen &gen, AstNode *n, Register reg); + void addKeptRegister(codeGen &gen, AstNode *n, Dyninst::Register reg); void removeKeptRegister(codeGen &gen, AstNode *n); - Register hasKeptRegister(AstNode *n); - bool stealKeptRegister(Register reg); + Dyninst::Register hasKeptRegister(AstNode *n); + bool stealKeptRegister(Dyninst::Register reg); void reset(); @@ -143,7 +140,7 @@ class dataReqNode; class AstNode : public Dyninst::PatchAPI::Snippet { public: enum nodeType { sequenceNode_t, opCodeNode_t, operandNode_t, callNode_t, scrambleRegisters_t}; - enum operandType { Constant, + enum class operandType { Constant, ConstantString, DataReg, DataIndir, @@ -210,7 +207,7 @@ class AstNode : public Dyninst::PatchAPI::Snippet { static AstNodePtr stackRemoveNode(int size, MSpecialType type); static AstNodePtr stackRemoveNode(int size, MSpecialType type, func_instance* func, bool canaryAfterPrologue, long canaryHeight); static AstNodePtr stackGenericNode(); - bool allocateCanaryRegister(codeGen& gen, bool noCost, Register& reg, bool& needSaveAndRestore); + bool allocateCanaryRegister(codeGen& gen, bool noCost, Dyninst::Register& reg, bool& needSaveAndRestore); static AstNodePtr labelNode(std::string &label); @@ -222,7 +219,7 @@ class AstNode : public Dyninst::PatchAPI::Snippet { static AstNodePtr sequenceNode(std::vector &sequence); - static AstNodePtr variableNode(std::vector&ast_wrappers_, std::vector > *ranges = NULL); + static AstNodePtr variableNode(std::vector&ast_wrappers_, std::vector > *ranges = NULL); static AstNodePtr operatorNode(opCode ot, AstNodePtr l = AstNodePtr(), @@ -232,7 +229,7 @@ class AstNode : public Dyninst::PatchAPI::Snippet { static AstNodePtr funcCallNode(const std::string &func, std::vector &args, AddressSpace *addrSpace = NULL); static AstNodePtr funcCallNode(func_instance *func, std::vector &args); static AstNodePtr funcCallNode(func_instance *func); // Special case for function call replacement. - static AstNodePtr funcCallNode(Address addr, std::vector &args); // For when you absolutely need + static AstNodePtr funcCallNode(Dyninst::Address addr, std::vector &args); // For when you absolutely need // to jump somewhere. // Acquire the thread index value - a 0...n labelling of threads. @@ -264,8 +261,8 @@ class AstNode : public Dyninst::PatchAPI::Snippet { virtual bool generateCode(codeGen &gen, bool noCost, - Address &retAddr, - Register &retReg); + Dyninst::Address &retAddr, + Dyninst::Register &retReg); // Can't use default references.... virtual bool generateCode(codeGen &gen, @@ -274,8 +271,8 @@ class AstNode : public Dyninst::PatchAPI::Snippet { // Can't use default references.... virtual bool generateCode(codeGen &gen, bool noCost, - Register &retReg) { - Address unused = ADDR_NULL; + Dyninst::Register &retReg) { + Dyninst::Address unused = Dyninst::ADDR_NULL; return generateCode(gen, noCost, unused, retReg); } @@ -283,8 +280,8 @@ class AstNode : public Dyninst::PatchAPI::Snippet { // so we'll toss in two different return types. virtual bool generateCode_phase2(codeGen &gen, bool noCost, - Address &retAddr, - Register &retReg); + Dyninst::Address &retAddr, + Dyninst::Register &retReg); // Perform whatever pre-processing steps are necessary. virtual bool initRegisters(codeGen &gen); @@ -297,7 +294,7 @@ class AstNode : public Dyninst::PatchAPI::Snippet { bool decRefCount(); - bool previousComputationValid(Register ®, + bool previousComputationValid(Dyninst::Register ®, codeGen &gen); // Remove any kept register at a greater level than // that provided (AKA that had been calculated within @@ -349,10 +346,10 @@ class AstNode : public Dyninst::PatchAPI::Snippet { // Allocate a register and make it available for sharing if our // node is shared - Register allocateAndKeep(codeGen &gen, bool noCost); + Dyninst::Register allocateAndKeep(codeGen &gen, bool noCost); // If someone needs to take this guy away. - bool stealRegister(Register reg); + bool stealRegister(Dyninst::Register reg); // Check to see if path1 is a subpath of path2 bool subpath(const std::vector &path1, @@ -361,7 +358,6 @@ class AstNode : public Dyninst::PatchAPI::Snippet { // Return all children of this node ([lre]operand, ..., operands[]) virtual void getChildren(std::vector &); - void printRC(void); virtual bool accessesParam(void); virtual void setOValue(void *) { assert(0); } @@ -370,13 +366,13 @@ class AstNode : public Dyninst::PatchAPI::Snippet { return NULL; } - virtual void emitVariableStore(opCode, Register, Register, codeGen&, + virtual void emitVariableStore(opCode, Dyninst::Register, Dyninst::Register, codeGen&, bool, registerSpace*, int, const instPoint*, AddressSpace*) { assert(!"Never call this on anything but an operand"); } - virtual void emitVariableLoad(opCode, Register, Register, codeGen&, + virtual void emitVariableLoad(opCode, Dyninst::Register, Dyninst::Register, codeGen&, bool, registerSpace*, int, const instPoint*, AddressSpace*) { @@ -391,7 +387,7 @@ class AstNode : public Dyninst::PatchAPI::Snippet { // DEBUG - virtual operandType getoType() const { return undefOperandType; } + virtual operandType getoType() const { return operandType::undefOperandType; } virtual void setConstFunc(bool) {} @@ -435,8 +431,8 @@ class AstNullNode : public AstNode { private: virtual bool generateCode_phase2(codeGen &gen, bool noCost, - Address &retAddr, - Register &retReg); + Dyninst::Address &retAddr, + Dyninst::Register &retReg); }; /* Stack Frame Modification */ @@ -455,8 +451,8 @@ class AstStackInsertNode : public AstNode { private: virtual bool generateCode_phase2(codeGen &gen, bool noCost, - Address &retAddr, - Register &retReg); + Dyninst::Address &retAddr, + Dyninst::Register &retReg); int size; MSpecialType type; @@ -486,15 +482,15 @@ class AstStackRemoveNode : public AstNode { private: virtual bool generateCode_phase2(codeGen &gen, bool noCost, - Address &retAddr, - Register &retReg); + Dyninst::Address &retAddr, + Dyninst::Register &retReg); int size; MSpecialType type; - func_instance* func_; - bool canaryAfterPrologue_; - long canaryHeight_; + func_instance* func_{}; + bool canaryAfterPrologue_{}; + long canaryHeight_{}; }; class AstStackGenericNode : public AstNode { @@ -507,8 +503,8 @@ class AstStackGenericNode : public AstNode { private: virtual bool generateCode_phase2(codeGen &gen, bool noCost, - Address &retAddr, - Register &retReg); + Dyninst::Address &retAddr, + Dyninst::Register &retReg); }; class AstLabelNode : public AstNode { @@ -521,22 +517,16 @@ class AstLabelNode : public AstNode { private: virtual bool generateCode_phase2(codeGen &gen, bool noCost, - Address &retAddr, - Register &retReg); + Dyninst::Address &retAddr, + Dyninst::Register &retReg); std::string label_; - Address generatedAddr_; + Dyninst::Address generatedAddr_; }; class AstOperatorNode : public AstNode { public: AstOperatorNode(opCode opC, AstNodePtr l, AstNodePtr r = AstNodePtr(), AstNodePtr e = AstNodePtr()); - - ~AstOperatorNode() { - //printf("at ~AstOperatorode()\n"); - //debugPrint(); - } - virtual std::string format(std::string indent); virtual int costHelper(enum CostStyleType costStyle) const; @@ -564,13 +554,12 @@ class AstOperatorNode : public AstNode { virtual bool generateCode_phase2(codeGen &gen, bool noCost, - Address &retAddr, - Register &retReg); + Dyninst::Address &retAddr, + Dyninst::Register &retReg); bool generateOptimizedAssignment(codeGen &gen, int size, bool noCost); - AstOperatorNode() {} - opCode op; + opCode op{}; AstNodePtr loperand; AstNodePtr roperand; AstNodePtr eoperand; @@ -592,7 +581,7 @@ class AstOperandNode : public AstNode { ~AstOperandNode() { //printf("at ~AstOperandNode()\n"); //debugPrint(); - if (oType == ConstantString) free((char *)oValue); + if (oType == operandType::ConstantString) free((char *)oValue); } // Arguably, the previous should be an operation... @@ -616,7 +605,7 @@ class AstOperandNode : public AstNode { virtual BPatch_type *checkType(BPatch_function* func = NULL); - virtual bool accessesParam(void) { return (oType == Param || oType == ParamAtEntry || oType == ParamAtCall); } + virtual bool accessesParam(void) { return (oType == operandType::Param || oType == operandType::ParamAtEntry || oType == operandType::ParamAtCall); } virtual bool canBeKept() const; virtual void getChildren(std::vector &children); @@ -630,10 +619,10 @@ class AstOperandNode : public AstNode { virtual bool usesAppRegister() const; - virtual void emitVariableStore(opCode op, Register src1, Register src2, codeGen& gen, + virtual void emitVariableStore(opCode op, Dyninst::Register src1, Dyninst::Register src2, codeGen& gen, bool noCost, registerSpace* rs, int size, const instPoint* point, AddressSpace* as); - virtual void emitVariableLoad(opCode op, Register src2, Register dest, codeGen& gen, + virtual void emitVariableLoad(opCode op, Dyninst::Register src2, Dyninst::Register dest, codeGen& gen, bool noCost, registerSpace* rs, int size, const instPoint* point, AddressSpace* as); @@ -642,11 +631,11 @@ class AstOperandNode : public AstNode { private: virtual bool generateCode_phase2(codeGen &gen, bool noCost, - Address &retAddr, - Register &retReg); + Dyninst::Address &retAddr, + Dyninst::Register &retReg); int_variable* lookUpVar(AddressSpace* as); - AstOperandNode(): oType(undefOperandType), oValue(NULL), oVar(NULL) {} + AstOperandNode(): oType(operandType::undefOperandType), oValue(NULL), oVar(NULL) {} operandType oType; void *oValue; @@ -660,7 +649,7 @@ class AstCallNode : public AstNode { AstCallNode(func_instance *func, std::vector&args); AstCallNode(const std::string &str, std::vector&args); - AstCallNode(Address addr, std::vector &args); + AstCallNode(Dyninst::Address addr, std::vector &args); AstCallNode(func_instance *func); ~AstCallNode() {} @@ -689,13 +678,13 @@ class AstCallNode : public AstNode { private: virtual bool generateCode_phase2(codeGen &gen, bool noCost, - Address &retAddr, - Register &retReg); + Dyninst::Address &retAddr, + Dyninst::Register &retReg); AstCallNode(): func_addr_(0), func_(NULL), callReplace_(false), constFunc_(false) {} // Sometimes we just don't have enough information... const std::string func_name_; - Address func_addr_; + Dyninst::Address func_addr_; func_instance *func_; std::vector args_; @@ -735,8 +724,8 @@ class AstSequenceNode : public AstNode { private: virtual bool generateCode_phase2(codeGen &gen, bool noCost, - Address &retAddr, - Register &retReg); + Dyninst::Address &retAddr, + Dyninst::Register &retReg); AstSequenceNode() {} std::vector sequence_; @@ -744,7 +733,7 @@ class AstSequenceNode : public AstNode { class AstVariableNode : public AstNode { public: - AstVariableNode(std::vector&ast_wrappers, std::vector >*ranges); + AstVariableNode(std::vector&ast_wrappers, std::vector >*ranges); ~AstVariableNode() {} @@ -773,12 +762,12 @@ class AstVariableNode : public AstNode { private: virtual bool generateCode_phase2(codeGen &gen, bool noCost, - Address &retAddr, - Register &retReg); + Dyninst::Address &retAddr, + Dyninst::Register &retReg); AstVariableNode(): ranges_(NULL), index(0) {} std::vectorast_wrappers_; - std::vector > *ranges_; + std::vector > *ranges_; unsigned index; }; @@ -793,7 +782,7 @@ class AstMiniTrampNode : public AstNode { } - Address generateTramp(codeGen &gen, + Dyninst::Address generateTramp(codeGen &gen, int &trampCost, bool noCost); @@ -835,12 +824,12 @@ class AstMemoryNode : public AstNode { private: virtual bool generateCode_phase2(codeGen &gen, bool noCost, - Address &retAddr, - Register &retReg); + Dyninst::Address &retAddr, + Dyninst::Register &retReg); AstMemoryNode() {} - memoryType mem_; - unsigned which_; + memoryType mem_{}; + unsigned which_{}; }; class AstOriginalAddrNode : public AstNode { @@ -859,8 +848,8 @@ class AstOriginalAddrNode : public AstNode { private: virtual bool generateCode_phase2(codeGen &gen, bool noCost, - Address &retAddr, - Register &retReg); + Dyninst::Address &retAddr, + Dyninst::Register &retReg); }; class AstActualAddrNode : public AstNode { @@ -878,8 +867,8 @@ class AstActualAddrNode : public AstNode { private: virtual bool generateCode_phase2(codeGen &gen, bool noCost, - Address &retAddr, - Register &retReg); + Dyninst::Address &retAddr, + Dyninst::Register &retReg); }; class AstDynamicTargetNode : public AstNode { @@ -897,8 +886,8 @@ class AstDynamicTargetNode : public AstNode { private: virtual bool generateCode_phase2(codeGen &gen, bool noCost, - Address &retAddr, - Register &retReg); + Dyninst::Address &retAddr, + Dyninst::Register &retReg); }; class AstScrambleRegistersNode : public AstNode { public: @@ -913,8 +902,8 @@ class AstScrambleRegistersNode : public AstNode { private: virtual bool generateCode_phase2(codeGen &gen, bool noCost, - Address &retAddr, - Register &retReg); + Dyninst::Address &retAddr, + Dyninst::Register &retReg); }; @@ -932,24 +921,24 @@ class AstSnippetNode : public AstNode { private: virtual bool generateCode_phase2(codeGen &gen, bool noCost, - Address &retAddr, - Register &retReg); + Dyninst::Address &retAddr, + Dyninst::Register &retReg); Dyninst::PatchAPI::SnippetPtr snip_; }; -void emitLoadPreviousStackFrameRegister(Address register_num, - Register dest, +void emitLoadPreviousStackFrameRegister(Dyninst::Address register_num, + Dyninst::Register dest, codeGen &gen, int size, bool noCost); -void emitStorePreviousStackFrameRegister(Address register_num, - Register src, +void emitStorePreviousStackFrameRegister(Dyninst::Address register_num, + Dyninst::Register src, codeGen &gen, int size, bool noCost); -#define SCAST_AST(ast) boost::static_pointer_cast(ast) -#define DCAST_AST(ast) boost::dynamic_pointer_cast(ast) +#define SCAST_AST(ast) dyncompat::static_pointer_cast(ast) +#define DCAST_AST(ast) dyncompat::dynamic_pointer_cast(ast) #endif /* AST_HDR */ diff --git a/dyninstAPI/src/baseTramp.C b/dyninstAPI/src/baseTramp.C index 805c1bff0c..a87e9c2000 100644 --- a/dyninstAPI/src/baseTramp.C +++ b/dyninstAPI/src/baseTramp.C @@ -188,7 +188,7 @@ bool baseTramp::shouldRegenBaseTramp(registerSpace *rs) } bool baseTramp::generateCode(codeGen &gen, - Address baseInMutatee) { + Dyninst::Address baseInMutatee) { inst_printf("baseTramp %p ::generateCode(%p, 0x%lx, %u)\n", (void*)this, gen.start_ptr(), baseInMutatee, gen.used()); initializeFlags(); @@ -261,7 +261,7 @@ bool baseTramp::generateCode(codeGen &gen, #include "BPatch_collections.h" bool baseTramp::generateCodeInlined(codeGen &gen, - Address) { + Dyninst::Address) { // We're generating something like so: // // @@ -526,8 +526,9 @@ bool baseTramp::guarded() const { } if (recursive && guarded) { - cerr << "Warning: mix of recursive and guarded snippets @ " << point_ - << ", picking guarded" << endl; + inst_printf( + "Warning: mix of recursive and guarded snippets @ %p, picking guarded \n", + static_cast(point_)); return true; } if (guarded) return true; diff --git a/dyninstAPI/src/baseTramp.h b/dyninstAPI/src/baseTramp.h index 47faa48000..aabeec4686 100644 --- a/dyninstAPI/src/baseTramp.h +++ b/dyninstAPI/src/baseTramp.h @@ -35,7 +35,7 @@ #ifndef BASE_TRAMP_H #define BASE_TRAMP_H -#include "common/src/Types.h" +#include "dyntypes.h" #include "inst.h" // callWhen #include "dyninstAPI/src/codeRange.h" //#include "arch.h" @@ -63,10 +63,10 @@ class baseTramp { void initializeFlags(); bool generateCode(codeGen &gen, - Address baseInMutatee); + Dyninst::Address baseInMutatee); bool generateCodeInlined(codeGen &gen, - Address baseInMutatee); + Dyninst::Address baseInMutatee); bool checkForFuncCalls(); diff --git a/dyninstAPI/src/binaryEdit.C b/dyninstAPI/src/binaryEdit.C index 7973419e50..2a00eb6b6b 100644 --- a/dyninstAPI/src/binaryEdit.C +++ b/dyninstAPI/src/binaryEdit.C @@ -30,6 +30,7 @@ // $Id: binaryEdit.C,v 1.26 2008/10/28 18:42:44 bernat Exp $ +#include #include "binaryEdit.h" #include "common/src/headers.h" #include "mapped_object.h" @@ -38,11 +39,10 @@ #include "os.h" #include "instPoint.h" #include "function.h" +#include "Object.h" using namespace Dyninst::SymtabAPI; -// #define USE_ADDRESS_MAPS - // Reading and writing get somewhat interesting. We are building // a false address space - that of the "inferior" binary we're editing. // However, that address space doesn't exist - and so we must overlay @@ -60,7 +60,7 @@ bool BinaryEdit::readTextSpace(const void *inOther, // Look up this address in the code range tree of memory codeRange *range = NULL; - if (!memoryTracker_->find(addr, range)) + if (!memoryTracker_.find(addr, range)) return false; assert(addr >= range->get_address()); @@ -86,7 +86,7 @@ bool BinaryEdit::writeTextSpace(void *inOther, while (to_do) { // Look up this address in the code range tree of memory codeRange *range = NULL; - if (!memoryTracker_->find(addr, range)) { + if (!memoryTracker_.find(addr, range)) { return false; } @@ -112,7 +112,6 @@ bool BinaryEdit::writeTextSpace(void *inOther, void *local_ptr = ((void *) (offset + (Address)range->get_local_ptr())); inst_printf("Copying to 0x%p [base=0x%p] from 0x%lx (%u bytes) target=0x%lx offset=0x%lx\n", local_ptr, range->get_local_ptr(), local, chunk_size, addr, offset); - //range->print_range(); memcpy(local_ptr, (void *)local, chunk_size); memoryTracker* mt = dynamic_cast(range); assert(mt); @@ -197,10 +196,7 @@ Address BinaryEdit::inferiorMalloc(unsigned size, if (ret) { memoryTracker *newTracker = new memoryTracker(ret, size); newTracker->alloced = true; - if (!memoryTracker_) - memoryTracker_ = new codeRangeTree(); - memoryTracker_->insert(newTracker); - + memoryTracker_.insert(newTracker); break; } } @@ -212,17 +208,11 @@ void BinaryEdit::inferiorFree(Address item) { inferiorFreeInternal(item); - codeRange *obj; - if(!memoryTracker_->find(item, obj)) - { - // Warn the user? - return; - } - - - delete obj; - - memoryTracker_->remove(item); + codeRange *obj{}; + if(memoryTracker_.find(item, obj)) delete obj; + + // Remove it from the tree + memoryTracker_.remove(item); } bool BinaryEdit::inferiorRealloc(Address item, unsigned newsize) @@ -234,17 +224,17 @@ bool BinaryEdit::inferiorRealloc(Address item, unsigned newsize) maxAllocedAddr(); codeRange *obj; - result = memoryTracker_->find(item, obj); + result = memoryTracker_.find(item, obj); assert(result); - memoryTracker_->remove(item); + memoryTracker_.remove(item); memoryTracker *mem_track = dynamic_cast(obj); assert(mem_track); mem_track->realloc(newsize); - memoryTracker_->insert(obj); + memoryTracker_.insert(obj); return true; } @@ -276,7 +266,7 @@ BinaryEdit::BinaryEdit() : highWaterMark_(0), lowWaterMark_(0), isDirty_(false), - memoryTracker_(NULL), + memoryTracker_{}, mobj(NULL), multithread_capable_(false), writing_(false) @@ -294,7 +284,12 @@ BinaryEdit::~BinaryEdit() for(auto *rel : dependentRelocations) { delete rel; } - delete memoryTracker_; + + std::vector x; + memoryTracker_.elements(x); + for(auto const *c : x) { + delete c; + } } BinaryEdit *BinaryEdit::openFile(const std::string &file, @@ -476,21 +471,6 @@ bool BinaryEdit::getAllDependencies(std::map& deps) return true; } -#if 0 //KEVINTODO: I think this is redundant, SymtabAPI::emitWin.C does this -static unsigned long addTrapTableSpace_win(AddressSpace *as) -{ -#if defined (os_windows) - return as->getAddressWidth() + 16; -#else - return 0; -#endif -} - -void addTrapTable_win(newSectionPtr, Address tableAddr) -{ -} -#endif - bool BinaryEdit::writeFile(const std::string &newFileName) { // Step 1: changes. @@ -528,24 +508,14 @@ bool BinaryEdit::writeFile(const std::string &newFileName) // Now, we need to copy in the memory of the new segments for (unsigned i = 0; i < oldSegs.size(); i++) { codeRange *segRange = NULL; - if (!memoryTracker_->find(oldSegs[i]->getMemOffset(), segRange)) { -#if 0 - // Looks like BSS - if (newSegs[i].name == ".bss") -#endif + if (!memoryTracker_.find(oldSegs[i]->getMemOffset(), segRange)) { continue; - //inst_printf (" segment name: %s\n", newSegs[i].name.c_str()); - //assert(0); } - //inst_printf(" ==> memtracker: Copying to 0x%lx from 0x%lx\n", - //newSegs[i].loadaddr, segRange->get_local_ptr()); memoryTracker* mt = dynamic_cast(segRange); assert(mt); if(mt->dirty) { oldSegs[i]->setPtrToRawData(segRange->get_local_ptr(), oldSegs[i]->getMemSize()); } - - //newSegs[i].data = segRange->get_local_ptr(); } // Okay, that does it for the old stuff. @@ -556,15 +526,12 @@ bool BinaryEdit::writeFile(const std::string &newFileName) void *newSectionPtr = calloc(highWaterMark_ - lowWaterMark_, 1); std::vector writes; - memoryTracker_->elements(writes); + memoryTracker_.elements(writes); for (unsigned i = 0; i < writes.size(); i++) { assert(newSectionPtr); memoryTracker *tracker = dynamic_cast(writes[i]); assert(tracker); - //inst_printf("memory tracker: 0x%lx load=0x%lx size=%d %s\n", - //tracker->get_local_ptr(), tracker->get_address(), tracker->get_size(), - //tracker->alloced ? "[A]" : ""); if (!tracker->alloced) continue; // Copy whatever is in there into the big buffer, at the appropriate address @@ -610,51 +577,22 @@ bool BinaryEdit::writeFile(const std::string &newFileName) for (unsigned i=0; i < dependentRelocations.size(); i++) { Address to = dependentRelocations[i]->getAddress(); Symbol *referring = dependentRelocations[i]->getReferring(); - /* - if (!symObj->isStaticBinary() && !symObj->hasReldyn() && !symObj->hasReladyn()) { - Address addr = referring->getOffset(); - bool result = writeDataSpace((void *) to, getAddressWidth(), &addr); - assert(result); - continue; - } - */ // Create the relocationEntry relocationEntry localRel(to, referring->getMangledName(), referring, relocationEntry::getGlobalRelType(getAddressWidth(), referring)); - /* - if( mobj->isSharedLib() ) { - localRel.setRelAddr(to - mobj->imageOffset()); - } - */ - symObj->addExternalSymbolReference(referring, newSec, localRel); - - /* - newSymbol = new Symbol(referring->getName(), - Symbol::ST_FUNCTION, - Symbol::SL_GLOBAL, - Symbol::SV_DEFAULT, - (Address)0, - symObj->getDefaultModule(), - NULL, - 8, - true, - false); - symObj->addSymbol(newSymbol, referring); - if (!symObj->hasReldyn() && symObj->hasReladyn()) { - newSec->addRelocationEntry(to, newSymbol, relocationEntry::dynrel, Region::RT_RELA); - } else { - newSec->addRelocationEntry(to, newSymbol, relocationEntry::dynrel); - } - */ } } std::vector newSyms; - buildDyninstSymbols(newSyms, newSec, symObj->getOrCreateModule("dyninstInst", - lowWaterMark_)); + auto *mod = symObj->getContainingModule(lowWaterMark_); + if(!mod) { + mod = new Module(lang_Unknown, lowWaterMark_, "dyninstInst", symObj); + symObj->getObject()->addModule(mod); + } + buildDyninstSymbols(newSyms, newSec, mod); for (unsigned i = 0; i < newSyms.size(); i++) { symObj->addSymbol(newSyms[i]); } @@ -671,11 +609,9 @@ bool BinaryEdit::writeFile(const std::string &newFileName) // Symtab::emit(std::string filename) // First, text - assert(symObj); // And now we generate the new binary - //if (!symObj->emit(newFileName.c_str())) { if (!symObj->emit(newFileName.c_str())) { SymtabError lastError = Symtab::getLastSymtabError(); showErrorCallback(109, Symtab::printError(lastError)); @@ -700,11 +636,6 @@ Address BinaryEdit::maxAllocedAddr() { bool BinaryEdit::inferiorMallocStatic(unsigned size) { // Should be set by now assert(highWaterMark_ != 0); - -#if defined(USE_ADDRESS_MAPS) - void *buf = malloc(size); - if (!buf) return false; -#endif Address newStart = highWaterMark_; @@ -747,24 +678,16 @@ bool BinaryEdit::createMemoryBackingStore(mapped_object *obj) { symObj->getAllRegions(regs); for (unsigned i = 0; i < regs.size(); i++) { - memoryTracker *newTracker = NULL; if (regs[i]->getRegionType() == Region::RT_BSS || (regs[i]->getMemSize() == 0)) { continue; } - else { - newTracker = new memoryTracker(regs[i]->getMemOffset(), - regs[i]->getMemSize(), - regs[i]->getPtrToRawData()); - - } + auto *newTracker = new memoryTracker(regs[i]->getMemOffset(), + regs[i]->getMemSize(), + regs[i]->getPtrToRawData()); newTracker->alloced = false; - if (!memoryTracker_) - memoryTracker_ = new codeRangeTree(); - memoryTracker_->insert(newTracker); + memoryTracker_.insert(newTracker); } - - return true; } diff --git a/dyninstAPI/src/binaryEdit.h b/dyninstAPI/src/binaryEdit.h index 28d7e2d7a5..86f22a7d00 100644 --- a/dyninstAPI/src/binaryEdit.h +++ b/dyninstAPI/src/binaryEdit.h @@ -33,6 +33,9 @@ #ifndef BINARY_H #define BINARY_H +#include +#include +#include #include #include @@ -211,7 +214,7 @@ class BinaryEdit : public AddressSpace { /* Function specific to rewritting static binaries */ bool doStaticBinarySpecialCases(); - codeRangeTree* memoryTracker_; + codeRangeTree memoryTracker_; mapped_object * addSharedObject(const std::string *fullPath); diff --git a/dyninstAPI/src/block.h b/dyninstAPI/src/block.h index ad6560a0f5..812bb1e8ea 100644 --- a/dyninstAPI/src/block.h +++ b/dyninstAPI/src/block.h @@ -31,6 +31,9 @@ #if !defined(_DYN_BLOCK_H_) #define _DYN_BLOCK_H_ +#include +#include +#include #include "parse-cfg.h" #include "parseAPI/h/CFG.h" #include "instPoint.h" diff --git a/dyninstAPI/src/codeRange.C b/dyninstAPI/src/codeRange.C index e211289cd6..6173fbc274 100644 --- a/dyninstAPI/src/codeRange.C +++ b/dyninstAPI/src/codeRange.C @@ -179,7 +179,7 @@ void codeRangeTree::deleteFixup(entry* x){ // fails if the key value is already in the tree (happens for shared code) -codeRangeTree::entry *codeRangeTree::treeInsert(Address key, codeRange *value) +codeRangeTree::entry *codeRangeTree::treeInsert(Dyninst::Address key, codeRange *value) { entry* y = NULL; entry* x = setData; @@ -228,7 +228,7 @@ codeRangeTree::entry *codeRangeTree::treeSuccessor(entry* x) const{ } -codeRangeTree::entry *codeRangeTree::find_internal(Address element) const{ +codeRangeTree::entry *codeRangeTree::find_internal(Dyninst::Address element) const{ entry* x = setData; while(x != nil){ if (element < x->key) { @@ -319,7 +319,7 @@ void codeRangeTree::insert(codeRange *value) { setData->color = TREE_BLACK; } - void codeRangeTree::remove(Address key){ + void codeRangeTree::remove(Dyninst::Address key){ entry* z = find_internal(key); if(!z) { return; } if(z->key != key) { return; } @@ -359,7 +359,7 @@ void codeRangeTree::destroy(entry* node){ delete node; } -bool codeRangeTree::find(Address key, codeRange *& value) const{ +bool codeRangeTree::find(Dyninst::Address key, codeRange *& value) const{ value = NULL; if (!precessor(key, value)) return false; @@ -396,7 +396,7 @@ bool codeRangeTree::find(Address key, codeRange *& value) const{ #endif } -bool codeRangeTree::precessor(Address key, codeRange * &value) const{ +bool codeRangeTree::precessor(Dyninst::Address key, codeRange * &value) const{ entry *x = setData; entry *last = nil; while (x != nil) { @@ -427,7 +427,7 @@ bool codeRangeTree::precessor(Address key, codeRange * &value) const{ return false; } -bool codeRangeTree::successor(Address key, codeRange * &value) const{ +bool codeRangeTree::successor(Dyninst::Address key, codeRange * &value) const{ entry *x = setData; entry *last = nil; while (x != nil) { @@ -478,7 +478,7 @@ void codeRangeTree::clear() { } #define PRINT_COMMA if (print_comma) fprintf(stderr, ", "); print_comma = true -void codeRange::print_range(Address) { +void codeRange::print_range(Dyninst::Address) { bool print_comma = false; image *img_ptr = is_image(); mapped_object *mapped_ptr = is_mapped_object(); diff --git a/dyninstAPI/src/codeRange.h b/dyninstAPI/src/codeRange.h index 47a7ead81b..b0639e7fd6 100644 --- a/dyninstAPI/src/codeRange.h +++ b/dyninstAPI/src/codeRange.h @@ -41,8 +41,7 @@ #include #include #include -#include "common/src/Types.h" -#include "common/src/std_namesp.h" +#include "dyntypes.h" #include "dyninstAPI/src/patch.h" /** template class for codeRangeTree. The implementation is based on red black @@ -67,10 +66,10 @@ class parse_block; class codeRange : public patchTarget { public: //These are now inherited from relocTarget - //virtual Address get_address() const = 0; + //virtual Dyninst::Address get_address() const = 0; //virtual unsigned get_size() const = 0; - virtual void *getPtrToInstruction(Address) const { assert(0); return NULL; } + virtual void *getPtrToInstruction(Dyninst::Address) const { assert(0); return NULL; } // This returns a local pointer to the "beginning" of the // code range - as opposed to get_address, which returns @@ -99,9 +98,11 @@ class codeRange : public patchTarget { inferiorRPCinProgress *is_inferior_rpc(); //Prints codeRange info to stderr. - void print_range(Address addr = 0); + void print_range(Dyninst::Address addr = 0); - friend ostream &operator<<(ostream &s, const codeRange &c); + codeRange() = default; + codeRange(const codeRange&) = default; + virtual ~codeRange() = default; }; class codeRangeTree { @@ -110,7 +111,7 @@ class codeRangeTree { /** tree implementation structure. Used to implement the RB tree */ typedef struct entry { - Address key; + Dyninst::Address key; codeRange *value; color_t color; /* color of the node */ struct entry* left; /* left child */ @@ -131,7 +132,7 @@ class codeRangeTree { * @param d data element * @param e nill entry */ - entry(Address key_, codeRange *value_, entry* e) + entry(Dyninst::Address key_, codeRange *value_, entry* e) : key(key_), value(value_), color(TREE_RED), left(e), right(e), parent(NULL) {} @@ -168,7 +169,7 @@ class codeRangeTree { // insertion to a binary search tree. It returns the new element pointer // that is inserted. If element is already there it returns NULL - entry* treeInsert(Address, codeRange *); + entry* treeInsert(Dyninst::Address, codeRange *); // finds the elemnts in the tree that will be replaced with the element // being deleted in the deletion. That is the element with the largest @@ -177,7 +178,7 @@ class codeRangeTree { // method that returns the entry pointer for the element that is searched //for. If the entry is not found then it retuns NULL - entry* find_internal(Address) const; + entry* find_internal(Dyninst::Address) const; // infix traverse of the RB tree. It traverses the tree in ascending order void traverse(codeRange **,entry*,int&) const; @@ -221,22 +222,22 @@ class codeRangeTree { /** removes the element in the tree * @param 1 element that will be removed */ - void remove(Address); + void remove(Dyninst::Address); /** returns true if the argument is member of the codeRangeTree * @param e the element that will be searched for */ - bool find(Address, codeRange *&) const; + bool find(Dyninst::Address, codeRange *&) const; /** Returns the largest value less than or equal to the * key given */ - bool precessor(Address, codeRange *&) const; + bool precessor(Dyninst::Address, codeRange *&) const; /** Returns the smallest value greater than or equal to the * key given */ - bool successor(Address, codeRange *&) const; + bool successor(Dyninst::Address, codeRange *&) const; /** fill an buffer array with the sorted * elements of the codeRangeTree in ascending order according to comparison function diff --git a/dyninstAPI/src/codegen-aarch64.C b/dyninstAPI/src/codegen-aarch64.C index b9159326ea..207771a453 100644 --- a/dyninstAPI/src/codegen-aarch64.C +++ b/dyninstAPI/src/codegen-aarch64.C @@ -28,6 +28,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include #include "dyninstAPI/src/codegen.h" #include "dyninstAPI/src/debug.h" @@ -113,7 +114,7 @@ void insnCodeGen::generateBranch(codeGen &gen, long disp, bool link) { insnCodeGen::generate(gen, insn); } -void insnCodeGen::generateBranch(codeGen &gen, Address from, Address to, bool link) { +void insnCodeGen::generateBranch(codeGen &gen, Dyninst::Address from, Dyninst::Address to, bool link) { long disp = (to - from); if (labs(disp) > MAX_BRANCH_OFFSET) { @@ -122,16 +123,16 @@ void insnCodeGen::generateBranch(codeGen &gen, Address from, Address to, bool li generateBranch(gen, disp, link); } -void insnCodeGen::generateCall(codeGen &gen, Address from, Address to) { +void insnCodeGen::generateCall(codeGen &gen, Dyninst::Address from, Dyninst::Address to) { generateBranch(gen, from, to, true); } void insnCodeGen::generateLongBranch(codeGen &gen, - Address from, - Address to, + Dyninst::Address from, + Dyninst::Address to, bool isCall) { - auto generateBReg = [&isCall, &gen](Register s) -> void + auto generateBReg = [&isCall, &gen](Dyninst::Register s) -> void { instruction branchInsn; branchInsn.clear(); @@ -152,14 +153,14 @@ void insnCodeGen::generateLongBranch(codeGen &gen, insnCodeGen::generate(gen, branchInsn); }; - Register scratch = REG_NULL; + Dyninst::Register scratch = Null_Register; if(isCall) { - // use Link Register as scratch since it will be overwritten at return + // use Link Dyninst::Register as scratch since it will be overwritten at return scratch = 30; //load disp to r30 - loadImmIntoReg
(gen, scratch, to); + loadImmIntoReg(gen, scratch, to); //generate call generateBReg(scratch); return; @@ -174,18 +175,18 @@ void insnCodeGen::generateLongBranch(codeGen &gen, scratch = rs->getScratchRegister(gen, true); } - if (scratch == REG_NULL) + if (scratch == Null_Register) { //fprintf(stderr, " %s[%d] No registers. Calling generateBranchViaTrap...\n", FILE__, __LINE__); generateBranchViaTrap(gen, from, to, isCall); return; } - loadImmIntoReg
(gen, scratch, to); + loadImmIntoReg(gen, scratch, to); generateBReg(scratch); } -void insnCodeGen::generateBranchViaTrap(codeGen &gen, Address from, Address to, bool isCall) { +void insnCodeGen::generateBranchViaTrap(codeGen &gen, Dyninst::Address from, Dyninst::Address to, bool isCall) { long disp = to - from; if (labs(disp) <= MAX_BRANCH_OFFSET) { // We shouldn't be here, since this is an internal-called-only func. @@ -210,7 +211,7 @@ void insnCodeGen::generateBranchViaTrap(codeGen &gen, Address from, Address to, } } -void insnCodeGen::generateConditionalBranch(codeGen& gen, Address to, unsigned opcode, bool s) +void insnCodeGen::generateConditionalBranch(codeGen& gen, Dyninst::Address to, unsigned opcode, bool s) { instruction insn; insn.clear(); @@ -248,8 +249,8 @@ void insnCodeGen::generateConditionalBranch(codeGen& gen, Address to, unsigned o void insnCodeGen::generateAddSubShifted( - codeGen &gen, insnCodeGen::ArithOp op, int shift, int imm6, Register rm, - Register rn, Register rd, bool is64bit) + codeGen &gen, insnCodeGen::ArithOp op, int shift, int imm6, Dyninst::Register rm, + Dyninst::Register rn, Dyninst::Register rd, bool is64bit) { instruction insn; insn.clear(); @@ -277,7 +278,7 @@ void insnCodeGen::generateAddSubShifted( } void insnCodeGen::generateAddSubImmediate( - codeGen &gen, insnCodeGen::ArithOp op, int shift, int imm12, Register rn, Register rd, bool is64bit) + codeGen &gen, insnCodeGen::ArithOp op, int shift, int imm12, Dyninst::Register rn, Dyninst::Register rd, bool is64bit) { instruction insn; insn.clear(); @@ -302,7 +303,7 @@ void insnCodeGen::generateAddSubImmediate( insnCodeGen::generate(gen, insn); } -void insnCodeGen::generateMul(codeGen &gen, Register rm, Register rn, Register rd, bool is64bit) { +void insnCodeGen::generateMul(codeGen &gen, Dyninst::Register rm, Dyninst::Register rn, Dyninst::Register rd, bool is64bit) { instruction insn; insn.clear(); @@ -325,7 +326,7 @@ void insnCodeGen::generateMul(codeGen &gen, Register rm, Register rn, Register r //#sasha is rm or rn the denominator? void insnCodeGen::generateDiv( - codeGen &gen, Register rm, Register rn, Register rd, bool is64bit, bool s) + codeGen &gen, Dyninst::Register rm, Dyninst::Register rn, Dyninst::Register rd, bool is64bit, bool s) { instruction insn; insn.clear(); @@ -354,8 +355,8 @@ void insnCodeGen::generateDiv( } void insnCodeGen::generateBitwiseOpShifted( - codeGen &gen, insnCodeGen::BitwiseOp op, int shift, Register rm, int imm6, - Register rn, Register rd, bool is64bit) + codeGen &gen, insnCodeGen::BitwiseOp op, int shift, Dyninst::Register rm, int imm6, + Dyninst::Register rn, Dyninst::Register rd, bool is64bit) { instruction insn; insn.clear(); @@ -394,35 +395,35 @@ void insnCodeGen::generateBitwiseOpShifted( insnCodeGen::generate(gen, insn); } -void insnCodeGen::generateLoadReg(codeGen &, Register, - Register, Register) +void insnCodeGen::generateLoadReg(codeGen &, Dyninst::Register, + Dyninst::Register, Dyninst::Register) { assert(0); //#warning "This function is not implemented yet!" } -void insnCodeGen::generateStoreReg(codeGen &, Register, - Register, Register) +void insnCodeGen::generateStoreReg(codeGen &, Dyninst::Register, + Dyninst::Register, Dyninst::Register) { assert(0); //#warning "This function is not implemented yet!" } -void insnCodeGen::generateLoadReg64(codeGen &, Register, - Register, Register) +void insnCodeGen::generateLoadReg64(codeGen &, Dyninst::Register, + Dyninst::Register, Dyninst::Register) { assert(0); //#warning "This function is not implemented yet!" } -void insnCodeGen::generateStoreReg64(codeGen &, Register, - Register, Register) +void insnCodeGen::generateStoreReg64(codeGen &, Dyninst::Register, + Dyninst::Register, Dyninst::Register) { assert(0); //#warning "This function is not implemented yet!" } -void insnCodeGen::generateMove(codeGen &gen, int imm16, int shift, Register rd, MoveOp movOp) +void insnCodeGen::generateMove(codeGen &gen, int imm16, int shift, Dyninst::Register rd, MoveOp movOp) { instruction insn; insn.clear(); @@ -446,12 +447,12 @@ void insnCodeGen::generateMove(codeGen &gen, int imm16, int shift, Register rd, } void insnCodeGen::generateMove( - codeGen &gen, Register rd, Register rm, bool is64bit) + codeGen &gen, Dyninst::Register rd, Dyninst::Register rm, bool is64bit) { insnCodeGen::generateBitwiseOpShifted(gen, insnCodeGen::Or, 0, rm, 0, 0x1f, rd, is64bit); } -void insnCodeGen::generateMoveSP(codeGen &gen, Register rn, Register rd, bool is64bit) { +void insnCodeGen::generateMoveSP(codeGen &gen, Dyninst::Register rn, Dyninst::Register rd, bool is64bit) { instruction insn; insn.clear(); @@ -469,38 +470,23 @@ void insnCodeGen::generateMoveSP(codeGen &gen, Register rn, Register rd, bool is } -Register insnCodeGen::moveValueToReg(codeGen &gen, long int val, std::vector *exclude) { - Register scratchReg; +Dyninst::Register insnCodeGen::moveValueToReg(codeGen &gen, long int val, std::vector *exclude) { + Dyninst::Register scratchReg; if(exclude) scratchReg = gen.rs()->getScratchRegister(gen, *exclude, true); else scratchReg = gen.rs()->getScratchRegister(gen, true); - if (scratchReg == REG_NULL) { + if (scratchReg == Null_Register) { fprintf(stderr, " %s[%d] No scratch register available to generate add instruction!", FILE__, __LINE__); assert(0); } - loadImmIntoReg(gen, scratchReg, val); + loadImmIntoReg(gen, scratchReg, static_cast(val)); return scratchReg; } - -template -void insnCodeGen::loadImmIntoReg(codeGen &gen, Register rt, T value) -{ - assert(value >= 0); - - insnCodeGen::generateMove(gen, (value & 0xFFFF), 0, rt, MovOp_MOVZ); - if(value > 0xFFFF) - insnCodeGen::generateMove(gen, ((value >> 16) & 0xFFFF), 0x1, rt, MovOp_MOVK); - if(value > 0xFFFFFFFF) - insnCodeGen::generateMove(gen, ((value >> 32) & 0xFFFF), 0x2, rt, MovOp_MOVK); - if(value > 0xFFFFFFFFFFFF) - insnCodeGen::generateMove(gen, ((value >> 48) & 0xFFFF), 0x3, rt, MovOp_MOVK); -} - // Generate memory access through Load or Store // Instructions generated: // LDR/STR (immediate) for 32-bit or 64-bit @@ -509,7 +495,7 @@ void insnCodeGen::loadImmIntoReg(codeGen &gen, Register rt, T value) // // Encoding classes allowed: Post-index, Pre-index and Unsigned Offset void insnCodeGen::generateMemAccess(codeGen &gen, LoadStore accType, - Register r1, Register r2, int immd, unsigned size, IndexMode im) + Dyninst::Register r1, Dyninst::Register r2, int immd, unsigned size, IndexMode im) { instruction insn; insn.clear(); @@ -543,7 +529,7 @@ void insnCodeGen::generateMemAccess(codeGen &gen, LoadStore accType, // This is for generating STR/LDR (SIMD&FP) (immediate) for indexing modes of Post, Pre and Offset void insnCodeGen::generateMemAccessFP(codeGen &gen, LoadStore accType, - Register rt, Register rn, int immd, int size, bool is128bit, IndexMode im) + Dyninst::Register rt, Dyninst::Register rn, int immd, int size, bool is128bit, IndexMode im) { instruction insn; insn.clear(); @@ -584,28 +570,28 @@ void insnCodeGen::generateMemAccessFP(codeGen &gen, LoadStore accType, } // rlwinm ra,rs,n,0,31-n -void insnCodeGen::generateLShift(codeGen &, Register, int, Register) +void insnCodeGen::generateLShift(codeGen &, Dyninst::Register, int, Dyninst::Register) { assert(0); //#warning "This function is not implemented yet!" } // rlwinm ra,rs,32-n,n,31 -void insnCodeGen::generateRShift(codeGen &, Register, int, Register) +void insnCodeGen::generateRShift(codeGen &, Dyninst::Register, int, Dyninst::Register) { assert(0); //#warning "This function is not implemented yet!" } // sld ra, rs, rb -void insnCodeGen::generateLShift64(codeGen &, Register, int, Register) +void insnCodeGen::generateLShift64(codeGen &, Dyninst::Register, int, Dyninst::Register) { assert(0); //#warning "This function is not implemented yet!" } // srd ra, rs, rb -void insnCodeGen::generateRShift64(codeGen &, Register, int, Register) +void insnCodeGen::generateRShift64(codeGen &, Dyninst::Register, int, Dyninst::Register) { assert(0); //not implemented @@ -624,29 +610,21 @@ void insnCodeGen::generateNOOP(codeGen &gen, unsigned size) { } } -void insnCodeGen::generateSimple(codeGen &, int, - Register, Register, - Register) -{ -assert(0); -//#warning "This function is not implemented yet!" -} - -void insnCodeGen::generateRelOp(codeGen &, int, int, Register, - Register, Register) +void insnCodeGen::generateRelOp(codeGen &, int, int, Dyninst::Register, + Dyninst::Register, Dyninst::Register) { assert(0); //#warning "This function is not implemented yet!" } -void insnCodeGen::saveRegister(codeGen &gen, Register r, int sp_offset, IndexMode im) +void insnCodeGen::saveRegister(codeGen &gen, Dyninst::Register r, int sp_offset, IndexMode im) { generateMemAccess(gen, Store, r, REG_SP, sp_offset, 8, im); } -void insnCodeGen::restoreRegister(codeGen &gen, Register r, int sp_offset, IndexMode im) +void insnCodeGen::restoreRegister(codeGen &gen, Dyninst::Register r, int sp_offset, IndexMode im) { generateMemAccess(gen, Load, r, REG_SP, sp_offset, 8, im); } @@ -655,13 +633,13 @@ void insnCodeGen::restoreRegister(codeGen &gen, Register r, int sp_offset, Index // Helper method. Fills register with partial value to be completed // by an operation with a 16-bit signed immediate. Such as loads and // stores. -void insnCodeGen::loadPartialImmIntoReg(codeGen &, Register, long) +void insnCodeGen::loadPartialImmIntoReg(codeGen &, Dyninst::Register, long) { assert(0); //#warning "This function is not implemented yet!" } -int insnCodeGen::createStackFrame(codeGen &, int, std::vector& freeReg, std::vector&){ +int insnCodeGen::createStackFrame(codeGen &, int, std::vector& freeReg, std::vector&){ assert(0); //#warning "This function is not implemented yet!" return freeReg.size(); @@ -674,29 +652,29 @@ assert(0); bool insnCodeGen::generateMem(codeGen &, instruction&, - Address, - Address, - Register, - Register) { + Dyninst::Address, + Dyninst::Address, + Dyninst::Register, + Dyninst::Register) { assert(0); //#warning "This function is not implemented yet!" return false; } -void insnCodeGen::generateMoveFromLR(codeGen &, Register) { +void insnCodeGen::generateMoveFromLR(codeGen &, Dyninst::Register) { assert(0); //#warning "This function is not implemented yet!" } -void insnCodeGen::generateMoveToLR(codeGen &, Register) { +void insnCodeGen::generateMoveToLR(codeGen &, Dyninst::Register) { assert(0); //#warning "This function is not implemented yet!" } -void insnCodeGen::generateMoveToCR(codeGen &, Register) { +void insnCodeGen::generateMoveToCR(codeGen &, Dyninst::Register) { assert(0); //#warning "This function is not implemented yet!" } -bool insnCodeGen::modifyJump(Address target, +bool insnCodeGen::modifyJump(Dyninst::Address target, NS_aarch64::instruction &insn, codeGen &gen) { long disp = target - gen.currAddr(); @@ -727,7 +705,7 @@ bool insnCodeGen::modifyJump(Address target, * bit-twiddling functions can then be defined if necessary in the codegen-* files * and called as necessary by the common, refactored logic. */ -bool insnCodeGen::modifyJcc(Address target, +bool insnCodeGen::modifyJcc(Dyninst::Address target, NS_aarch64::instruction &insn, codeGen &gen) { long disp = target - gen.currAddr(); @@ -736,7 +714,7 @@ bool insnCodeGen::modifyJcc(Address target, if(labs(disp) > MAX_CBRANCH_OFFSET || (isTB && labs(disp) > MAX_TBRANCH_OFFSET)) { - Address origFrom = gen.currAddr(); + Dyninst::Address origFrom = gen.currAddr(); /* * A conditional branch of the form: @@ -777,7 +755,7 @@ bool insnCodeGen::modifyJcc(Address target, * bytes (8 actually, but I'm not hardcoding this) ahead of the original 'from' address. * So adjust it accordingly.*/ codeBufIndex_t curIdx = gen.getIndex(); - Address newFrom = origFrom + (unsigned)(curIdx - startIdx); + Dyninst::Address newFrom = origFrom + (unsigned)(curIdx - startIdx); insnCodeGen::generateBranch(gen, newFrom, target); } else @@ -796,7 +774,7 @@ bool insnCodeGen::modifyJcc(Address target, return true; } -bool insnCodeGen::modifyCall(Address target, +bool insnCodeGen::modifyCall(Dyninst::Address target, NS_aarch64::instruction &insn, codeGen &gen) { if (insn.isUncondBranch()) @@ -805,7 +783,7 @@ bool insnCodeGen::modifyCall(Address target, return modifyJcc(target, insn, gen); } -bool insnCodeGen::modifyData(Address target, +bool insnCodeGen::modifyData(Dyninst::Address target, NS_aarch64::instruction &insn, codeGen &gen) { @@ -816,14 +794,14 @@ bool insnCodeGen::modifyData(Address target, isneg = true; if (((raw >> 24) & 0x1F) == 0x10) { - Address offset; + Dyninst::Address offset; if((static_cast(raw) >> 31) & 0x1) { target &= 0xFFFFF000; - Address cur = gen.currAddr() & 0xFFFFF000; + Dyninst::Address cur = gen.currAddr() & 0xFFFFF000; offset = isneg ? (cur - target) : (target - cur); offset >>= 12; } else { - Address cur = gen.currAddr(); + Dyninst::Address cur = gen.currAddr(); offset = isneg ? (cur - target) : (target - cur); } signed long imm = isneg ? -((signed long)offset) : offset; @@ -837,8 +815,8 @@ bool insnCodeGen::modifyData(Address target, } //Else, generate move instructions to move the value to the same register else { - //Register rd = raw & 0x1F; - //loadImmIntoReg
(gen, rd, target); + //Dyninst::Register rd = raw & 0x1F; + //loadImmIntoReg(gen, rd, target); instruction newInsn; instruction newInsn2; newInsn.clear(); @@ -859,7 +837,7 @@ bool insnCodeGen::modifyData(Address target, } } else if (((raw >> 24) & 0x3F) == 0x18 || ((raw >> 24) & 0x3F) == 0x1C) { - Address offset = !isneg ? (target - gen.currAddr()) : (gen.currAddr() - target); + Dyninst::Address offset = !isneg ? (target - gen.currAddr()) : (gen.currAddr() - target); //If offset is within +/- 1 MB, modify the instruction (LDR/LDRSW) with the new offset if (offset <= (1 << 20)) { instruction newInsn(insn); @@ -873,16 +851,16 @@ bool insnCodeGen::modifyData(Address target, //If it's larger than |1MB|, move target to register and generate LDR else { // Get scratch register - Register scratch = gen.rs()->getScratchRegister(gen, true); - if(scratch == REG_NULL) + Dyninst::Register scratch = gen.rs()->getScratchRegister(gen, true); + if(scratch == Null_Register) assert(!"No scratch register available to load the target \ address into for a PC-relative data access using LDR/LDRSW!"); // Load the target address into scratch register - loadImmIntoReg
(gen, scratch, target); + loadImmIntoReg(gen, scratch, target); // Generate LDR(immediate) to load into r the the content of [scratch] - Register r = raw & 0x1F; + Dyninst::Register r = raw & 0x1F; generateMemAccess(gen, Load, r, scratch, 0, 8, Offset); } } else { diff --git a/dyninstAPI/src/codegen-aarch64.h b/dyninstAPI/src/codegen-aarch64.h index b3a42cf063..73069ce83d 100644 --- a/dyninstAPI/src/codegen-aarch64.h +++ b/dyninstAPI/src/codegen-aarch64.h @@ -31,6 +31,10 @@ #ifndef _CODEGEN_AARCH64_H #define _CODEGEN_AARCH64_H +#include +#include "dyntypes.h" +#include "common/src/dyn_register.h" + class AddressSpace; class codeGen; @@ -79,116 +83,120 @@ class insnCodeGen { bool link = false); static void generateBranch(codeGen &gen, - Address from, - Address to, + Dyninst::Address from, + Dyninst::Address to, bool link = false); static void generateCall(codeGen &gen, - Address from, - Address to); + Dyninst::Address from, + Dyninst::Address to); static void generateLongBranch(codeGen &gen, - Address from, - Address to, + Dyninst::Address from, + Dyninst::Address to, bool isCall); // Using the process trap mapping for a branch static void generateBranchViaTrap(codeGen &gen, - Address from, - Address to, + Dyninst::Address from, + Dyninst::Address to, bool isCall); // Generate conditional branch - static void generateConditionalBranch(codeGen& gen, Address to, unsigned opcode, bool s); + static void generateConditionalBranch(codeGen& gen, Dyninst::Address to, unsigned opcode, bool s); // LDR/STR (immediate) // immd in the range -256 to 255 - static void generateMemAccess(codeGen &gen, LoadStore accType, Register r1, - Register r2, int immd, unsigned size, IndexMode im=Post); + static void generateMemAccess(codeGen &gen, LoadStore accType, Dyninst::Register r1, + Dyninst::Register r2, int immd, unsigned size, IndexMode im=Post); - static void generateMemAccessFP(codeGen &gen, LoadStore accType, Register rt, - Register rn, int immd, int size, bool is128bit, IndexMode im=Offset); + static void generateMemAccessFP(codeGen &gen, LoadStore accType, Dyninst::Register rt, + Dyninst::Register rn, int immd, int size, bool is128bit, IndexMode im=Offset); - template - static void loadImmIntoReg(codeGen &gen, Register rt, T value); + static inline void loadImmIntoReg(codeGen &gen, Dyninst::Register rt, Dyninst::Address value) + { + insnCodeGen::generateMove(gen, (value & 0xFFFF), 0, rt, MovOp_MOVZ); + if(value > 0xFFFF) + insnCodeGen::generateMove(gen, ((value >> 16) & 0xFFFF), 0x1, rt, MovOp_MOVK); + if(value > 0xFFFFFFFF) + insnCodeGen::generateMove(gen, ((value >> 32) & 0xFFFF), 0x2, rt, MovOp_MOVK); + if(value > 0xFFFFFFFFFFFF) + insnCodeGen::generateMove(gen, ((value >> 48) & 0xFFFF), 0x3, rt, MovOp_MOVK); + } - static void saveRegister(codeGen &gen, Register r, int sp_offset, IndexMode im=Offset); + static void saveRegister(codeGen &gen, Dyninst::Register r, int sp_offset, IndexMode im=Offset); - static void restoreRegister(codeGen &gen, Register r, int sp_offset, IndexMode im=Offset); + static void restoreRegister(codeGen &gen, Dyninst::Register r, int sp_offset, IndexMode im=Offset); /** TODO **/ - static void generateLoadReg(codeGen &gen, Register rt, - Register ra, Register rb); - - static void generateStoreReg(codeGen &gen, Register rs, - Register ra, Register rb); + static void generateLoadReg(codeGen &gen, Dyninst::Register rt, + Dyninst::Register ra, Dyninst::Register rb); - static void generateLoadReg64(codeGen &gen, Register rt, - Register ra, Register rb); + static void generateStoreReg(codeGen &gen, Dyninst::Register rs, + Dyninst::Register ra, Dyninst::Register rb); - static void generateStoreReg64(codeGen &gen, Register rs, - Register ra, Register rb); + static void generateLoadReg64(codeGen &gen, Dyninst::Register rt, + Dyninst::Register ra, Dyninst::Register rb); - static void generateLShift(codeGen &gen, Register rs, - int shift, Register ra); + static void generateStoreReg64(codeGen &gen, Dyninst::Register rs, + Dyninst::Register ra, Dyninst::Register rb); - static void generateRShift(codeGen &gen, Register rs, - int shift, Register ra); + static void generateLShift(codeGen &gen, Dyninst::Register rs, + int shift, Dyninst::Register ra); - static void generateLShift64(codeGen &gen, Register rs, - int shift, Register ra); + static void generateRShift(codeGen &gen, Dyninst::Register rs, + int shift, Dyninst::Register ra); - static void generateRShift64(codeGen &gen, Register rs, - int shift, Register ra); + static void generateLShift64(codeGen &gen, Dyninst::Register rs, + int shift, Dyninst::Register ra); - static void generateSimple(codeGen &gen, - int op, Register src1, - Register src2, Register dest); + static void generateRShift64(codeGen &gen, Dyninst::Register rs, + int shift, Dyninst::Register ra); static void generateRelOp(codeGen &gen, int cond, - int mode, Register rs1, - Register rs2, Register rd); + int mode, Dyninst::Register rs1, + Dyninst::Register rs2, Dyninst::Register rd); - static void loadPartialImmIntoReg(codeGen &gen, Register rt, + static void loadPartialImmIntoReg(codeGen &gen, Dyninst::Register rt, long value); - static void generateMoveFromLR(codeGen &gen, Register rt); + static void generateMoveFromLR(codeGen &gen, Dyninst::Register rt); - static void generateMoveToLR(codeGen &gen, Register rs); + static void generateMoveToLR(codeGen &gen, Dyninst::Register rs); - static void generateMoveToCR(codeGen &gen, Register rs); + static void generateMoveToCR(codeGen &gen, Dyninst::Register rs); static bool generateMem(codeGen &gen, instruction &insn, - Address origAddr, - Address newAddr, - Register newLoadReg, - Register newStoreReg); + Dyninst::Address origAddr, + Dyninst::Address newAddr, + Dyninst::Register newLoadReg, + Dyninst::Register newStoreReg); /** *** **/ static void generateAddSubShifted( - codeGen &gen, ArithOp op, int shift, int imm6, Register rm, Register rn, Register rd, bool is64bit); + codeGen &gen, ArithOp op, int shift, int imm6, Dyninst::Register rm, Dyninst::Register rn, Dyninst::Register rd, bool is64bit); static void generateAddSubImmediate( - codeGen &gen, ArithOp op, int shift, int imm12, Register rn, Register rd, bool is64bit); + codeGen &gen, ArithOp op, int shift, int imm12, Dyninst::Register rn, Dyninst::Register rd, bool is64bit); - static void generateMul(codeGen &gen, Register rm, Register rn, Register rd, bool is64bit); + static void generateMul(codeGen &gen, Dyninst::Register rm, Dyninst::Register rn, Dyninst::Register rd, bool is64bit); - static void generateDiv(codeGen &gen, Register rm, Register rn, Register rd, bool is64bit, bool s); + static void generateDiv(codeGen &gen, Dyninst::Register rm, Dyninst::Register rn, Dyninst::Register rd, bool is64bit, bool s); static void generateBitwiseOpShifted(codeGen &gen, BitwiseOp op, int shift, - Register rm, int imm6, Register rn, Register rd, bool is64bit); + Dyninst::Register rm, int imm6, Dyninst::Register rn, Dyninst::Register rd, bool is64bit); // This is for MOVK, MOVN, and MOVZ. For MOV use the other generateMove() - static void generateMove(codeGen &gen, int imm16, int shift, Register rd, MoveOp movOp); + static void generateMove(codeGen &gen, int imm16, int shift, Dyninst::Register rd, MoveOp movOp); // This is for MOV, which is an alias for ORR. See ARMv8 Documentation. - static void generateMove(codeGen &gen, Register rd, Register rm, bool is64bit = true); + static void generateMove(codeGen &gen, Dyninst::Register rd, Dyninst::Register rm, bool is64bit = true); - static void generateMoveSP(codeGen &gen, Register rn, Register rd, bool is64bit); + static void generateMoveSP(codeGen &gen, Dyninst::Register rn, Dyninst::Register rd, bool is64bit); - static Register moveValueToReg(codeGen &gen, long int val, std::vector *exclude = NULL); + static Dyninst::Register moveValueToReg(codeGen &gen, long int val, std::vector *exclude = NULL); static void generate(codeGen &gen, instruction &insn); @@ -200,15 +208,15 @@ class insnCodeGen { static bool generate(codeGen &gen, instruction &insn, AddressSpace *proc, - Address origAddr, - Address newAddr, + Dyninst::Address origAddr, + Dyninst::Address newAddr, patchTarget *fallthroughOverride = NULL, patchTarget *targetOverride = NULL); //TODO // Routines to create/remove a new stack frame for getting scratch registers - static int createStackFrame(codeGen &gen, int numRegs, std::vector &freeReg, - std::vector &excludeReg); + static int createStackFrame(codeGen &gen, int numRegs, std::vector &freeReg, + std::vector &excludeReg); //TODO static void removeStackFrame(codeGen &gen); @@ -216,19 +224,19 @@ class insnCodeGen { static void generateNOOP(codeGen &gen, unsigned size = 4); - static bool modifyJump(Address target, + static bool modifyJump(Dyninst::Address target, NS_aarch64::instruction &insn, codeGen &gen); - static bool modifyJcc(Address target, + static bool modifyJcc(Dyninst::Address target, NS_aarch64::instruction &insn, codeGen &gen); - static bool modifyCall(Address target, + static bool modifyCall(Dyninst::Address target, NS_aarch64::instruction &insn, codeGen &gen); - static bool modifyData(Address target, + static bool modifyData(Dyninst::Address target, NS_aarch64::instruction &insn, codeGen &gen); }; diff --git a/dyninstAPI/src/codegen-power.C b/dyninstAPI/src/codegen-power.C index fd1e3d8812..1857371cc5 100644 --- a/dyninstAPI/src/codegen-power.C +++ b/dyninstAPI/src/codegen-power.C @@ -28,6 +28,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include "dyninstAPI/src/codegen.h" #include "dyninstAPI/src/debug.h" #include "dyninstAPI/src/instPoint.h" @@ -46,6 +47,7 @@ #include #include "common/src/arch-power.h" #include +#include bool shouldAssertIfInLongBranch = true; bool failedLongBranchLocal = false; @@ -181,7 +183,7 @@ void insnCodeGen::generateBranch(codeGen &gen, long disp, bool link) insnCodeGen::generate(gen,insn); } -void insnCodeGen::generateBranch(codeGen &gen, Address from, Address to, bool link) { +void insnCodeGen::generateBranch(codeGen &gen, Dyninst::Address from, Dyninst::Address to, bool link) { long disp = (to - from); // fprintf(stderr, "[insnCodeGen::generateBranch] Generating branch from %p to %p\n", from, to); @@ -197,7 +199,7 @@ void insnCodeGen::generateBranch(codeGen &gen, Address from, Address to, bool li } -void insnCodeGen::generateCall(codeGen &gen, Address from, Address to) { +void insnCodeGen::generateCall(codeGen &gen, Dyninst::Address from, Dyninst::Address to) { //fprintf(stderr, "info: %s:%d: \n", __FILE__, __LINE__); generateBranch(gen, from, to, true); } @@ -254,11 +256,11 @@ void GenerateRestoresBaseTrampStyle(codeGen &gen) { popStack(gen); } -void insnCodeGen::generateMoveToSPR(codeGen &gen, Register toSPR, +void insnCodeGen::generateMoveToSPR(codeGen &gen, Dyninst::Register toSPR, unsigned sprReg) { // Check that this SPR exists if (sprReg != SPR_TAR && sprReg != SPR_LR && sprReg != SPR_CTR) - assert("SPR Register is not valid" == 0); + assert("SPR Dyninst::Register is not valid" == 0); // Move the register to the spr instruction moveToBr; @@ -271,11 +273,11 @@ void insnCodeGen::generateMoveToSPR(codeGen &gen, Register toSPR, insnCodeGen::generate(gen,moveToBr); } -void insnCodeGen::generateMoveFromSPR(codeGen &gen, Register toSPR, +void insnCodeGen::generateMoveFromSPR(codeGen &gen, Dyninst::Register toSPR, unsigned sprReg) { // Check that this SPR exists if (sprReg != SPR_TAR && sprReg != SPR_LR && sprReg != SPR_CTR) - assert("SPR Register is not valid" == 0); + assert("SPR Dyninst::Register is not valid" == 0); // Move the register to the spr instruction moveToBr; @@ -288,7 +290,7 @@ void insnCodeGen::generateMoveFromSPR(codeGen &gen, Register toSPR, insnCodeGen::generate(gen,moveToBr); } -void insnCodeGen::generateVectorLoad(codeGen &gen, unsigned vectorReg, Register RegAddress) { +void insnCodeGen::generateVectorLoad(codeGen &gen, unsigned vectorReg, Dyninst::Register RegAddress) { //insnCodeGen::generateImm(gen, CALop, rt, 0, BOT_LO(value)); instruction loadInstruction; XLFORM_OP_SET(loadInstruction, LXVD2Xop); @@ -300,7 +302,7 @@ void insnCodeGen::generateVectorLoad(codeGen &gen, unsigned vectorReg, Register insnCodeGen::generate(gen,loadInstruction); } -void insnCodeGen::generateVectorStore(codeGen & gen, unsigned vectorReg, Register RegAddress) { +void insnCodeGen::generateVectorStore(codeGen & gen, unsigned vectorReg, Dyninst::Register RegAddress) { instruction storeInstruction; XLFORM_OP_SET(storeInstruction, STXVD2Xop); XLFORM_BT_SET(storeInstruction, vectorReg); // From architecture manual @@ -324,8 +326,8 @@ void insnCodeGen::restoreVectors(codeGen & gen, int startStackOffset) { } } -bool insnCodeGen::generateBranchTar(codeGen &gen, Register scratch, - Address dest, +bool insnCodeGen::generateBranchTar(codeGen &gen, Dyninst::Register scratch, + Dyninst::Address dest, bool isCall) { // Generates a branch using TAR to the address specified in dest. // Returns true if this branch type was successfully used @@ -352,8 +354,8 @@ bool insnCodeGen::generateBranchTar(codeGen &gen, Register scratch, return true; } -bool insnCodeGen::generateBranchLR(codeGen &gen, Register scratch, - Address dest, +bool insnCodeGen::generateBranchLR(codeGen &gen, Dyninst::Register scratch, + Dyninst::Address dest, bool isCall) { // Generates a branch using LR to the address specified in dest. // Returns true if this branch type was successfully used @@ -382,8 +384,8 @@ bool insnCodeGen::generateBranchLR(codeGen &gen, Register scratch, bool insnCodeGen::generateBranchCTR(codeGen &gen, - Register scratch, - Address dest, + Dyninst::Register scratch, + Dyninst::Address dest, bool isCall) { // Generates a branch using TAR to the address specified in dest. // Returns true if this branch type was successfully used @@ -415,7 +417,7 @@ bool insnCodeGen::generateBranchCTR(codeGen &gen, #include "addressSpace.h" #include "instPoint.h" #include "function.h" -instPoint * GetInstPointPower(codeGen & gen, Address from) { +instPoint * GetInstPointPower(codeGen & gen, Dyninst::Address from) { // If this point is straight availible from the generator, return it instPoint *point = gen.point(); if (point) @@ -442,8 +444,8 @@ instPoint * GetInstPointPower(codeGen & gen, Address from) { return NULL; } void insnCodeGen::generateLongBranch(codeGen &gen, - Address from, - Address to, + Dyninst::Address from, + Dyninst::Address to, bool isCall) { bool usingLR = false; bool usingCTR = false; @@ -486,10 +488,10 @@ void insnCodeGen::generateLongBranch(codeGen &gen, // 4. Restore the original register value (if a scratch register was not found) // 5. build the branch instruction. //fprintf(stderr, "info: %s:%d: \n", __FILE__, __LINE__); - Register scratch = REG_NULL; + Dyninst::Register scratch = Null_Register; // TODO: Fix this, this should work.... //= gen.rs()->getScratchRegister(gen); - if (scratch == REG_NULL) { + if (scratch == Null_Register) { //fprintf(stderr, "info: %s:%d: \n", __FILE__, __LINE__); instPoint *point = GetInstPointPower(gen, from);//gen.point(); if (!point) { @@ -499,7 +501,7 @@ void insnCodeGen::generateLongBranch(codeGen &gen, } // Grab the register space, and see if LR or CTR are free. // What we are going to do here is use the LR/CTR as temporary store for an existing register value - std::vector potentialRegisters = {registerSpace::r3, registerSpace::r4, registerSpace::r5, registerSpace::r6, registerSpace::r7, registerSpace::r8, registerSpace::r9, registerSpace::r10}; + std::vector potentialRegisters = {registerSpace::r3, registerSpace::r4, registerSpace::r5, registerSpace::r6, registerSpace::r7, registerSpace::r8, registerSpace::r9, registerSpace::r10}; bitArray liveRegs = point->liveRegisters(); for (int iter = potentialRegisters.size() - 1; iter >= 0; iter = iter - 1) { @@ -508,10 +510,10 @@ void insnCodeGen::generateLongBranch(codeGen &gen, break; } } - if (scratch == REG_NULL) { + if (scratch == Null_Register) { if (liveRegs[registerSpace::lr] == false && isCall) { usingLR = true; - // Register 11 is the chosen one for using temporarily. + // Dyninst::Register 11 is the chosen one for using temporarily. generateMoveToSPR(gen, registerSpace::r10, SPR_LR); } else if (liveRegs[registerSpace::ctr] == false) { usingCTR = true; @@ -522,13 +524,13 @@ void insnCodeGen::generateLongBranch(codeGen &gen, return generateBranchViaTrap(gen, from, to, isCall); } } - } else if (scratch != REG_NULL) { + } else if (scratch != Null_Register) { //fprintf(stderr, "%s\n", "Generating branch with TAR....."); insnCodeGen::generateBranchTar(gen, scratch, to, isCall); return; } - if (scratch == REG_NULL) { + if (scratch == Null_Register) { // Now the fun stuff.... // Loed destination value into r11, copy it to SPR_TAR, restore the original R11 value. insnCodeGen::loadImmIntoReg(gen, registerSpace::r10, to); @@ -583,11 +585,11 @@ void insnCodeGen::generateLongBranch(codeGen &gen, // // code there and we don't want to hit that. // registerSpace *rs = registerSpace::actualRegSpace(point); // gen.setRegisterSpace(rs); - // Register scratch = rs->getScratchRegister(gen, true); + // Dyninst::Register scratch = rs->getScratchRegister(gen, true); // // - // assert(scratch == REG_NULL); + // assert(scratch == Null_Register); - // if (scratch == REG_NULL) { + // if (scratch == Null_Register) { // // Just save and restore everything, this is bad but its likely safe and can be revisted later. // // GenerateSavesBaseTrampStyle(gen); // // everythingSaved = true; @@ -663,7 +665,7 @@ void insnCodeGen::generateLongBranch(codeGen &gen, // GenerateRestoresBaseTrampStyle(gen); } -void insnCodeGen::generateBranchViaTrap(codeGen &gen, Address from, Address to, bool isCall) { +void insnCodeGen::generateBranchViaTrap(codeGen &gen, Dyninst::Address from, Dyninst::Address to, bool isCall) { //fprintf(stderr, "[insnCodeGen::generateBranchViaTrap] Generating branch via trap from %p to %p\n", from, to); long disp = to - from; @@ -719,8 +721,8 @@ void insnCodeGen::generateBranchViaTrap(codeGen &gen, Address from, Address to, } } -void insnCodeGen::generateAddReg (codeGen & gen, int op, Register rt, - Register ra, Register rb) +void insnCodeGen::generateAddReg (codeGen & gen, int op, Dyninst::Register rt, + Dyninst::Register ra, Dyninst::Register rb) { instruction insn; @@ -736,8 +738,8 @@ void insnCodeGen::generateAddReg (codeGen & gen, int op, Register rt, insnCodeGen::generate (gen,insn); } -void insnCodeGen::generateLoadReg(codeGen &gen, Register rt, - Register ra, Register rb) +void insnCodeGen::generateLoadReg(codeGen &gen, Dyninst::Register rt, + Dyninst::Register ra, Dyninst::Register rb) { instruction insn; insn.clear(); @@ -751,8 +753,8 @@ void insnCodeGen::generateLoadReg(codeGen &gen, Register rt, insnCodeGen::generate (gen,insn); } -void insnCodeGen::generateStoreReg(codeGen &gen, Register rt, - Register ra, Register rb) +void insnCodeGen::generateStoreReg(codeGen &gen, Dyninst::Register rt, + Dyninst::Register ra, Dyninst::Register rb) { instruction insn; insn.clear(); @@ -766,8 +768,8 @@ void insnCodeGen::generateStoreReg(codeGen &gen, Register rt, insnCodeGen::generate (gen,insn); } -void insnCodeGen::generateLoadReg64(codeGen &gen, Register rt, - Register ra, Register rb) +void insnCodeGen::generateLoadReg64(codeGen &gen, Dyninst::Register rt, + Dyninst::Register ra, Dyninst::Register rb) { instruction insn; insn.clear(); @@ -781,8 +783,8 @@ void insnCodeGen::generateLoadReg64(codeGen &gen, Register rt, insnCodeGen::generate(gen, insn); } -void insnCodeGen::generateStoreReg64(codeGen &gen, Register rs, - Register ra, Register rb) +void insnCodeGen::generateStoreReg64(codeGen &gen, Dyninst::Register rs, + Dyninst::Register ra, Dyninst::Register rb) { instruction insn; insn.clear(); @@ -796,7 +798,7 @@ void insnCodeGen::generateStoreReg64(codeGen &gen, Register rs, insnCodeGen::generate(gen, insn); } -void insnCodeGen::generateImm(codeGen &gen, int op, Register rt, Register ra, int immd) +void insnCodeGen::generateImm(codeGen &gen, int op, Dyninst::Register rt, Dyninst::Register ra, int immd) { // something should be here to make sure immd is within bounds // bound check really depends on op since we have both signed and unsigned @@ -822,7 +824,7 @@ void insnCodeGen::generateImm(codeGen &gen, int op, Register rt, Register ra, in insnCodeGen::generate(gen,insn); } -void insnCodeGen::generateMemAccess64(codeGen &gen, int op, int xop, Register r1, Register r2, int immd) +void insnCodeGen::generateMemAccess64(codeGen &gen, int op, int xop, Dyninst::Register r1, Dyninst::Register r2, int immd) { assert(MIN_IMM16 <= immd && immd <= MAX_IMM16); assert((immd & 0x3) == 0); @@ -840,7 +842,7 @@ void insnCodeGen::generateMemAccess64(codeGen &gen, int op, int xop, Register r1 } // rlwinm ra,rs,n,0,31-n -void insnCodeGen::generateLShift(codeGen &gen, Register rs, int shift, Register ra) +void insnCodeGen::generateLShift(codeGen &gen, Dyninst::Register rs, int shift, Dyninst::Register ra) { instruction insn; @@ -862,7 +864,7 @@ void insnCodeGen::generateLShift(codeGen &gen, Register rs, int shift, Register } // rlwinm ra,rs,32-n,n,31 -void insnCodeGen::generateRShift(codeGen &gen, Register rs, int shift, Register ra, bool s) +void insnCodeGen::generateRShift(codeGen &gen, Dyninst::Register rs, int shift, Dyninst::Register ra, bool s) { instruction insn; @@ -884,7 +886,7 @@ void insnCodeGen::generateRShift(codeGen &gen, Register rs, int shift, Register } // sld ra, rs, rb -void insnCodeGen::generateLShift64(codeGen &gen, Register rs, int shift, Register ra) +void insnCodeGen::generateLShift64(codeGen &gen, Dyninst::Register rs, int shift, Dyninst::Register ra) { instruction insn; @@ -904,7 +906,7 @@ void insnCodeGen::generateLShift64(codeGen &gen, Register rs, int shift, Registe } // srd ra, rs, rb -void insnCodeGen::generateRShift64(codeGen &gen, Register rs, int shift, Register ra, bool) +void insnCodeGen::generateRShift64(codeGen &gen, Dyninst::Register rs, int shift, Dyninst::Register ra, bool) { // This function uses rotate-left to implement right shift. // Rotate left 64-n bits is rotating right n bits. @@ -941,43 +943,8 @@ void insnCodeGen::generateNOOP(codeGen &gen, unsigned size) } } -void insnCodeGen::generateSimple(codeGen &gen, int op, - Register src1, Register src2, - Register dest) -{ - instruction insn; - - int xop=-1; - insn.clear(); - XFORM_OP_SET(insn, op); - XFORM_RT_SET(insn, src1); - XFORM_RA_SET(insn, dest); - XFORM_RB_SET(insn, src2); - if (op==ANDop) { - xop=ANDxop; - /* - * FIXME: The "else if" condition and code below are commented out to remove - * a duplicate branch condition as both ANDop and ORop have the same value. - * This implies that the assignment in this branch is never executed. - * Further tests to distinguish between the AND and OR op are needed or this - * code should be eliminated - * - - } else if (op==ORop) { - xop=ORxop; - - * - */ - } else { - // only AND and OR are currently designed to use genSimpleInsn - assert(0); - } - XFORM_XO_SET(insn, xop); - insnCodeGen::generate(gen,insn); -} - -void insnCodeGen::generateRelOp(codeGen &gen, int cond, int mode, Register rs1, - Register rs2, Register rd, bool s) +void insnCodeGen::generateRelOp(codeGen &gen, int cond, int mode, Dyninst::Register rs1, + Dyninst::Register rs2, Dyninst::Register rd, bool s) { instruction insn; @@ -1011,7 +978,7 @@ void insnCodeGen::generateRelOp(codeGen &gen, int cond, int mode, Register rs1, } // Given a value, load it into a register. -void insnCodeGen::loadImmIntoReg(codeGen &gen, Register rt, long value) +void insnCodeGen::loadImmIntoReg(codeGen &gen, Dyninst::Register rt, long value) { // Writing a full 64 bits takes 5 instructions in the worst case. // Let's see if we use sign-extention to cheat. @@ -1047,7 +1014,7 @@ void insnCodeGen::loadImmIntoReg(codeGen &gen, Register rt, long value) // Helper method. Fills register with partial value to be completed // by an operation with a 16-bit signed immediate. Such as loads and // stores. -void insnCodeGen::loadPartialImmIntoReg(codeGen &gen, Register rt, long value) +void insnCodeGen::loadPartialImmIntoReg(codeGen &gen, Dyninst::Register rt, long value) { if (MIN_IMM16 <= value && value <= MAX_IMM16) return; @@ -1056,10 +1023,7 @@ void insnCodeGen::loadPartialImmIntoReg(codeGen &gen, Register rt, long value) // the next op will cause the wrong effective addr to be computed. // so we subtract the sign ext value from the other half-words. // sounds odd, but works and saves an instruction - jkh 5/25/95 - - // Modified to be 64-bit compatible. Use (-1 >> 16) instead of - // 0xFFFF constant. - value = ((value >> 16) - (-1 >> 16)) << 16; + value = ((value >> 16) - (std::numeric_limits::max() >> 16)) << 16; } if (MIN_IMM32 <= value && value <= MAX_IMM32) { @@ -1083,7 +1047,7 @@ void insnCodeGen::loadPartialImmIntoReg(codeGen &gen, Register rt, long value) #endif } -int insnCodeGen::createStackFrame(codeGen &gen, int numRegs, std::vector& freeReg, std::vector& excludeReg){ +int insnCodeGen::createStackFrame(codeGen &gen, int numRegs, std::vector& freeReg, std::vector& excludeReg){ int gpr_off, stack_size; //create new stack frame gpr_off = TRAMP_GPR_OFFSET_32; @@ -1092,8 +1056,8 @@ int insnCodeGen::createStackFrame(codeGen &gen, int numRegs, std::vectorgetScratchRegister(gen, excludeReg, true); - assert (scratchReg != REG_NULL); + Dyninst::Register scratchReg = gen.rs()->getScratchRegister(gen, excludeReg, true); + assert (scratchReg != Null_Register); freeReg.push_back(scratchReg); excludeReg.push_back(scratchReg); } @@ -1110,12 +1074,12 @@ void insnCodeGen::removeStackFrame(codeGen &gen) { // {insn_ = {byte = {0xa6, 0x3, 0x8, 0x7c}, raw = 0x7c0803a6}} bool insnCodeGen::generateMem(codeGen &, instruction&, - Address, - Address, - Register, - Register) {return false; } + Dyninst::Address, + Dyninst::Address, + Dyninst::Register, + Dyninst::Register) {return false; } -void insnCodeGen::generateMoveFromLR(codeGen &gen, Register rt) { +void insnCodeGen::generateMoveFromLR(codeGen &gen, Dyninst::Register rt) { instruction insn; insn.clear(); XFORM_OP_SET(insn, MFSPRop); @@ -1126,7 +1090,7 @@ void insnCodeGen::generateMoveFromLR(codeGen &gen, Register rt) { generate(gen,insn); } -void insnCodeGen::generateMoveToLR(codeGen &gen, Register rs) { +void insnCodeGen::generateMoveToLR(codeGen &gen, Dyninst::Register rs) { instruction insn; insn.clear(); XFORM_OP_SET(insn, MTSPRop); @@ -1136,7 +1100,7 @@ void insnCodeGen::generateMoveToLR(codeGen &gen, Register rs) { XFORM_XO_SET(insn, MTSPRxop); generate(gen,insn); } -void insnCodeGen::generateMoveToCR(codeGen &gen, Register rs) { +void insnCodeGen::generateMoveToCR(codeGen &gen, Dyninst::Register rs) { instruction insn; insn.clear(); XFORM_OP_SET(insn, MTSPRop); @@ -1147,12 +1111,12 @@ void insnCodeGen::generateMoveToCR(codeGen &gen, Register rs) { generate(gen,insn); } -bool insnCodeGen::modifyJump(Address target, +bool insnCodeGen::modifyJump(Dyninst::Address target, NS_power::instruction &, codeGen &gen) { failedLongBranchLocal = false; shouldAssertIfInLongBranch = false; -// fprintf(stderr, "Setting link: %d Target Address: %p\n", IFORM_LK(insn), target); +// fprintf(stderr, "Setting link: %d Target Dyninst::Address: %p\n", IFORM_LK(insn), target); //assert(IFORM_LK(insn) == true); generateBranch(gen, gen.currAddr(), @@ -1166,12 +1130,12 @@ bool insnCodeGen::modifyJump(Address target, return true; } -bool insnCodeGen::modifyJumpCall(Address target, +bool insnCodeGen::modifyJumpCall(Dyninst::Address target, NS_power::instruction &, codeGen &gen) { failedLongBranchLocal = false; shouldAssertIfInLongBranch = false; - //fprintf(stderr, "Setting link: %d Target Address: %p\n", IFORM_LK(insn), target); + //fprintf(stderr, "Setting link: %d Target Dyninst::Address: %p\n", IFORM_LK(insn), target); //assert(IFORM_LK(insn) == true); generateBranch(gen, gen.currAddr(), @@ -1186,7 +1150,7 @@ bool insnCodeGen::modifyJumpCall(Address target, } -bool insnCodeGen::modifyJcc(Address target, +bool insnCodeGen::modifyJcc(Dyninst::Address target, NS_power::instruction &insn, codeGen &gen) { // We can be handed a conditional call or return instruction here. In these cases, @@ -1280,7 +1244,7 @@ bool insnCodeGen::modifyJcc(Address target, return false; } -bool insnCodeGen::modifyCall(Address target, +bool insnCodeGen::modifyCall(Dyninst::Address target, NS_power::instruction &insn, codeGen &gen) { // This is actually a mashup of conditional/unconditional handling @@ -1292,7 +1256,7 @@ bool insnCodeGen::modifyCall(Address target, //FIXME //This function is used for PC-relative and hence may not be required for PPC. Consider for update/removal. -bool insnCodeGen::modifyData(Address /*target*/, +bool insnCodeGen::modifyData(Dyninst::Address /*target*/, NS_power::instruction &insn, codeGen &gen) { // Only know how to "modify" syscall... diff --git a/dyninstAPI/src/codegen-power.h b/dyninstAPI/src/codegen-power.h index 2465e725ee..f3d027f3b5 100644 --- a/dyninstAPI/src/codegen-power.h +++ b/dyninstAPI/src/codegen-power.h @@ -31,6 +31,10 @@ #ifndef _CODEGEN_POWER_H #define _CODEGEN_POWER_H +#include +#include "dyntypes.h" +#include "dyn_register.h" + class AddressSpace; class codeGen; @@ -47,66 +51,63 @@ class insnCodeGen { long jump_off, bool link = false); static void generateBranch(codeGen &gen, - Address from, - Address to, + Dyninst::Address from, + Dyninst::Address to, bool link = false); static void generateCall(codeGen &gen, - Address from, - Address to); + Dyninst::Address from, + Dyninst::Address to); // This is a register-stomping, full-range branch. Uses one GPR // and either LR or CTR. New addition: use liveness information to // calculate which registers to use; otherwise, trap. static void generateLongBranch(codeGen &gen, - Address from, - Address to, + Dyninst::Address from, + Dyninst::Address to, bool isCall); // Using the process trap mapping for a branch static void generateBranchViaTrap(codeGen &gen, - Address from, - Address to, + Dyninst::Address from, + Dyninst::Address to, bool isCall); - static void generateLoadReg(codeGen &gen, Register rt, - Register ra, Register rb); - static void generateStoreReg(codeGen &gen, Register rs, - Register ra, Register rb); - static void generateLoadReg64(codeGen &gen, Register rt, - Register ra, Register rb); - static void generateStoreReg64(codeGen &gen, Register rs, - Register ra, Register rb); + static void generateLoadReg(codeGen &gen, Dyninst::Register rt, + Dyninst::Register ra, Dyninst::Register rb); + static void generateStoreReg(codeGen &gen, Dyninst::Register rs, + Dyninst::Register ra, Dyninst::Register rb); + static void generateLoadReg64(codeGen &gen, Dyninst::Register rt, + Dyninst::Register ra, Dyninst::Register rb); + static void generateStoreReg64(codeGen &gen, Dyninst::Register rs, + Dyninst::Register ra, Dyninst::Register rb); static void generateAddReg(codeGen &gen, int op, - Register rt, Register ra, Register rb); + Dyninst::Register rt, Dyninst::Register ra, Dyninst::Register rb); static void generateImm(codeGen &gen, int op, - Register rt, Register ra, int immd); + Dyninst::Register rt, Dyninst::Register ra, int immd); static void generateMemAccess64(codeGen &gen, int op, int xop, - Register r1, Register r2, int immd); - static void generateLShift(codeGen &gen, Register rs, - int shift, Register ra); - static void generateRShift(codeGen &gen, Register rs, - int shift, Register ra, bool s); - static void generateLShift64(codeGen &gen, Register rs, - int shift, Register ra); - static void generateRShift64(codeGen &gen, Register rs, - int shift, Register ra, bool s); + Dyninst::Register r1, Dyninst::Register r2, int immd); + static void generateLShift(codeGen &gen, Dyninst::Register rs, + int shift, Dyninst::Register ra); + static void generateRShift(codeGen &gen, Dyninst::Register rs, + int shift, Dyninst::Register ra, bool s); + static void generateLShift64(codeGen &gen, Dyninst::Register rs, + int shift, Dyninst::Register ra); + static void generateRShift64(codeGen &gen, Dyninst::Register rs, + int shift, Dyninst::Register ra, bool s); static void generateNOOP(codeGen &gen, unsigned size = 4); - static void generateSimple(codeGen &gen, - int op, Register src1, - Register src2, Register dest); static void generateRelOp(codeGen &gen, int cond, - int mode, Register rs1, - Register rs2, Register rd, bool s); - static void loadImmIntoReg(codeGen &gen, Register rt, + int mode, Dyninst::Register rs1, + Dyninst::Register rs2, Dyninst::Register rd, bool s); + static void loadImmIntoReg(codeGen &gen, Dyninst::Register rt, long value); - static void loadPartialImmIntoReg(codeGen &gen, Register rt, + static void loadPartialImmIntoReg(codeGen &gen, Dyninst::Register rt, long value); - static void generateMoveFromLR(codeGen &gen, Register rt); - static void generateMoveToLR(codeGen &gen, Register rs); - static void generateMoveToCR(codeGen &gen, Register rs); + static void generateMoveFromLR(codeGen &gen, Dyninst::Register rt); + static void generateMoveToLR(codeGen &gen, Dyninst::Register rs); + static void generateMoveToCR(codeGen &gen, Dyninst::Register rs); static void generate(codeGen &gen, instruction &insn); static void write(codeGen &gen, instruction &insn) { generate(gen,insn); } @@ -114,52 +115,52 @@ class insnCodeGen { static bool generate(codeGen &gen, instruction &insn, AddressSpace *proc, - Address origAddr, - Address newAddr, + Dyninst::Address origAddr, + Dyninst::Address newAddr, patchTarget *fallthroughOverride = NULL, patchTarget *targetOverride = NULL); static bool generateMem(codeGen &gen, instruction &insn, - Address origAddr, - Address newAddr, - Register newLoadReg, - Register newStoreReg); + Dyninst::Address origAddr, + Dyninst::Address newAddr, + Dyninst::Register newLoadReg, + Dyninst::Register newStoreReg); // Routines to create/remove a new stack frame for getting scratch registers - static int createStackFrame(codeGen &gen, int numRegs, std::vector& freeReg, std::vector& excludeReg); + static int createStackFrame(codeGen &gen, int numRegs, std::vector& freeReg, std::vector& excludeReg); static void removeStackFrame(codeGen &gen); - static void generateVectorLoad(codeGen &gen, unsigned vectorReg, Register RegAddress); - static void generateVectorStore(codeGen & gen, unsigned vectorReg, Register RegAddress); + static void generateVectorLoad(codeGen &gen, unsigned vectorReg, Dyninst::Register RegAddress); + static void generateVectorStore(codeGen & gen, unsigned vectorReg, Dyninst::Register RegAddress); - static bool modifyJump(Address target, + static bool modifyJump(Dyninst::Address target, NS_power::instruction &insn, codeGen &gen); - static bool modifyJumpCall(Address target, + static bool modifyJumpCall(Dyninst::Address target, NS_power::instruction &insn, codeGen &gen); - static bool modifyJcc(Address target, + static bool modifyJcc(Dyninst::Address target, NS_power::instruction &insn, codeGen &gen); - static bool modifyCall(Address target, + static bool modifyCall(Dyninst::Address target, NS_power::instruction &insn, codeGen &gen); - static bool modifyData(Address target, + static bool modifyData(Dyninst::Address target, NS_power::instruction &insn, codeGen &gen); - static void generateMoveToSPR(codeGen &gen,Register toSPR, unsigned sprReg); - static void generateMoveFromSPR(codeGen &gen,Register toSPR, + static void generateMoveToSPR(codeGen &gen,Dyninst::Register toSPR, unsigned sprReg); + static void generateMoveFromSPR(codeGen &gen,Dyninst::Register toSPR, unsigned sprReg); - static bool generateBranchTar(codeGen &gen,Register scratch, - Address dest, + static bool generateBranchTar(codeGen &gen,Dyninst::Register scratch, + Dyninst::Address dest, bool isCall); - static bool generateBranchLR(codeGen &gen, Register scratch, - Address dest, + static bool generateBranchLR(codeGen &gen, Dyninst::Register scratch, + Dyninst::Address dest, bool isCall); - static bool generateBranchCTR(codeGen &gen,Register scratch, - Address dest, + static bool generateBranchCTR(codeGen &gen,Dyninst::Register scratch, + Dyninst::Address dest, bool isCall); static void saveVectors(codeGen & gen, int startStackOffset); static void restoreVectors(codeGen & gen, int startStackOffset); diff --git a/dyninstAPI/src/codegen-x86.C b/dyninstAPI/src/codegen-x86.C index 55d95f8f8f..cd0547b778 100644 --- a/dyninstAPI/src/codegen-x86.C +++ b/dyninstAPI/src/codegen-x86.C @@ -30,12 +30,11 @@ #include #include -#include "boost/assign/list_of.hpp" -#include "boost/assign/std/vector.hpp" -#include "boost/assign/std/set.hpp" +#include "dyncompat/assign/list_of.hpp" +#include "dyncompat/assign/std/vector.hpp" +#include "dyncompat/assign/std/set.hpp" #include #include -#include "common/src/Types.h" #include "common/src/ia32_locations.h" #include "codegen.h" #include "util.h" @@ -47,13 +46,14 @@ #include "emit-x86.h" #include "inst-x86.h" -#include "instructionAPI/h/RegisterIDs.h" #include "pcrel.h" #include "StackMod/StackAccess.h" +#include "unaligned_memory_access.h" + using namespace std; -using namespace boost::assign; +using namespace dyncompat::assign; using namespace Dyninst::InstructionAPI; @@ -83,7 +83,7 @@ unsigned copy_prefixes(const unsigned char *&origInsn, unsigned char *&newInsn, return nPrefixes; } -//Copy all prefixes but the Operand-Size and Address-Size prefixes (0x66 and 0x67) +//Copy all prefixes but the Operand-Size and Dyninst::Address-Size prefixes (0x66 and 0x67) unsigned copy_prefixes_nosize(const unsigned char *&origInsn, unsigned char *&newInsn, unsigned insnType) { @@ -102,7 +102,7 @@ unsigned copy_prefixes_nosize(const unsigned char *&origInsn, unsigned char *&ne return retval; } -//Copy all prefixes but the Operand-Size and Address-Size prefixes (0x66 and 0x67) +//Copy all prefixes but the Operand-Size and Dyninst::Address-Size prefixes (0x66 and 0x67) // Returns the number of bytes copied unsigned copy_prefixes_nosize_or_segments(const unsigned char *&origInsn, unsigned char *&newInsn, unsigned insnType) @@ -191,23 +191,16 @@ bool convert_to_rel32(const unsigned char*&origInsn, unsigned char *&newInsn) { } -// We keep array-lets that represents various fixed insns. -// They are larger than necessary so static analyzers don't think -// they'll be read out of bounds. -static const unsigned char illegalRep[8] = {0x0f, 0x0b}; -static const unsigned char trapRep[8] = {0xCC}; - - void insnCodeGen::generateIllegal(codeGen &gen) { GET_PTR(insn, gen); - *insn++ = 0x0f; - *insn++ = 0x0b; + append_memory_as_byte(insn, 0x0f); + append_memory_as_byte(insn, 0x0b); SET_PTR(insn, gen); } void insnCodeGen::generateTrap(codeGen &gen) { GET_PTR(insn, gen); - *insn++ = 0xCC; + append_memory_as_byte(insn, 0xCC); SET_PTR(insn, gen); } @@ -217,14 +210,14 @@ void insnCodeGen::generateTrap(codeGen &gen) { */ void insnCodeGen::generateBranch(codeGen &gen, - Address fromAddr, Address toAddr) + Dyninst::Address fromAddr, Dyninst::Address toAddr) { GET_PTR(insn, gen); long disp; disp = toAddr - (fromAddr + 2); if (is_disp8(disp)) { - *insn++ = 0xEB; + append_memory_as_byte(insn, 0xEB); *((signed char*) insn) = (signed char) disp; insn += sizeof(signed char); SET_PTR(insn, gen); @@ -233,8 +226,8 @@ void insnCodeGen::generateBranch(codeGen &gen, /* disp = toAddr - (fromAddr + 4); if (is_disp16(disp) && gen.addrSpace()->getAddressWidth() != 8) { - *insn++ = 0x66; - *insn++ = 0xE9; + append_memory_as_byte(insn, 0x66); + append_memory_as_byte(insn, 0xE9); *((signed short*) insn) = (signed short) disp; insn += sizeof(signed short); SET_PTR(insn, gen); @@ -268,11 +261,10 @@ void insnCodeGen::generateBranch(codeGen &gen, assert ((unsigned)(-disp32) < (unsigned(1)<<31)); GET_PTR(insn, gen); - *insn++ = 0xE9; + append_memory_as_byte(insn, 0xE9); // 5 for a 5-byte branch. - *((int *)insn) = disp32 - 5; - insn += sizeof(int); + append_memory_as(insn, int32_t{disp32 - 5}); SET_PTR(insn, gen); return; @@ -280,16 +272,15 @@ void insnCodeGen::generateBranch(codeGen &gen, // Unified the 64-bit push between branch and call -void insnCodeGen::generatePush64(codeGen &gen, Address val) +void insnCodeGen::generatePush64(codeGen &gen, Dyninst::Address val) { GET_PTR(insn, gen); #if 0 for (int i = 3; i >= 0; i--) { - unsigned short word = static_cast((val >> (16 * i)) & 0xffff); - *insn++ = 0x66; // operand size override - *insn++ = 0x68; // push immediate (16-bits b/c of prefix) - *(unsigned short *)insn = word; - insn += 2; + uint16_t word = static_cast((val >> (16 * i)) & 0xffff); + append_memory_as_byte(insn, 0x66); // operand size override + append_memory_as_byte(insn, 0x68); // push immediate (16-bits b/c of prefix) + append_memory_as(insn, uint32_t{word}); } #endif // NOTE: The size of this generated instruction(+1 for the ret) is stored in CALL_ABS64_SZ @@ -297,22 +288,20 @@ void insnCodeGen::generatePush64(codeGen &gen, Address val) unsigned int low = static_cast(val); // push the low 4 - *insn++ = 0x68; - *(unsigned int*)insn = low; - insn += 4; + append_memory_as_byte(insn, 0x68); + append_memory_as(insn, uint32_t{low}); // move the high 4 to rsp+4 - *insn++ = 0xC7; - *insn++ = 0x44; - *insn++ = 0x24; - *insn++ = 0x04; - *(unsigned int*)insn = high; - insn += 4; + append_memory_as_byte(insn, 0xC7); + append_memory_as_byte(insn, 0x44); + append_memory_as_byte(insn, 0x24); + append_memory_as_byte(insn, 0x04); + append_memory_as(insn, uint32_t{high}); SET_PTR(insn, gen); } -void insnCodeGen::generateBranch64(codeGen &gen, Address to) +void insnCodeGen::generateBranch64(codeGen &gen, Dyninst::Address to) { // "long jump" - generates sequence to jump to any 64-bit address // pushes the value on the stack (using 4 16-bit pushes) the uses a 'RET' @@ -320,33 +309,32 @@ void insnCodeGen::generateBranch64(codeGen &gen, Address to) generatePush64(gen, to); GET_PTR(insn, gen); - *insn++ = 0xC3; // RET + append_memory_as_byte(insn, 0xC3); // RET SET_PTR(insn, gen); } -void insnCodeGen::generateBranch32(codeGen &gen, Address to) +void insnCodeGen::generateBranch32(codeGen &gen, Dyninst::Address to) { // "long jump" - generates sequence to jump to any 32-bit address emitPushImm(to, gen); GET_PTR(insn, gen); - *insn++ = 0xC3; // RET + append_memory_as_byte(insn, 0xC3); // RET SET_PTR(insn, gen); } void insnCodeGen::generateCall(codeGen &gen, - Address from, - Address target) + Dyninst::Address from, + Dyninst::Address target) { //assert(target); long disp = target - (from + CALL_REL32_SZ); if (is_disp32(disp)) { GET_PTR(insn, gen); - *insn++ = 0xE8; - *((int *)insn) = (int) disp; - insn += sizeof(int); + append_memory_as_byte(insn, 0xE8); + append_memory_as(insn, static_cast(disp)); SET_PTR(insn, gen); } else { @@ -384,7 +372,7 @@ void insnCodeGen::generateNOOP(codeGen &gen, unsigned size) { // Be more efficient here... while (size) { GET_PTR(insn, gen); - *insn++ = NOP; + append_memory_as_byte(insn, NOP); SET_PTR(insn, gen); size -= sizeof(unsigned char); } @@ -405,7 +393,7 @@ pcRelJump::pcRelJump(patchTarget *t, const instruction &i, bool copyPrefixes) : { } -pcRelJump::pcRelJump(Address target, const instruction &i, bool copyPrefixes) : +pcRelJump::pcRelJump(Dyninst::Address target, const instruction &i, bool copyPrefixes) : pcRelRegion(i), addr_targ(target), targ(NULL), @@ -413,7 +401,7 @@ pcRelJump::pcRelJump(Address target, const instruction &i, bool copyPrefixes) : { } -Address pcRelJump::get_target() +Dyninst::Address pcRelJump::get_target() { if (targ) return targ->get_address(); @@ -424,7 +412,7 @@ pcRelJump::~pcRelJump() { } -unsigned pcRelJump::apply(Address addr) +unsigned pcRelJump::apply(Dyninst::Address addr) { const unsigned char *origInsn = orig_instruc.ptr(); unsigned insnType = orig_instruc.type(); @@ -467,14 +455,14 @@ pcRelJCC::pcRelJCC(patchTarget *t, const instruction &i) : { } -pcRelJCC::pcRelJCC(Address target, const instruction &i) : +pcRelJCC::pcRelJCC(Dyninst::Address target, const instruction &i) : pcRelRegion(i), addr_targ(target), targ(NULL) { } -Address pcRelJCC::get_target() +Dyninst::Address pcRelJCC::get_target() { if (targ) return targ->get_address(); @@ -485,12 +473,12 @@ pcRelJCC::~pcRelJCC() { } -unsigned pcRelJCC::apply(Address addr) +unsigned pcRelJCC::apply(Dyninst::Address addr) { const unsigned char *origInsn = orig_instruc.ptr(); unsigned insnType = orig_instruc.type(); - Address target = get_target(); - Address potential; + Dyninst::Address target = get_target(); + Dyninst::Address potential; signed long disp; codeBufIndex_t start = gen->getIndex(); GET_PTR(newInsn, *gen); @@ -528,8 +516,7 @@ unsigned pcRelJCC::apply(Address addr) disp = target - potential; if (is_disp32(disp)) { convert_to_rel32(origInsn, newInsn); - *((signed int *) newInsn) = (signed int) disp; - newInsn += 4; + append_memory_as(newInsn, static_cast(disp)); SET_PTR(newInsn, *gen); return (unsigned) gen->getIndex() - start; } @@ -559,7 +546,7 @@ unsigned pcRelJCC::apply(Address addr) // Original address is a little skewed... // We've moved past the original address (to the tune of nPrefixes + 2 (JCC) + 2 (J)) - Address currAddr = addr + (unsigned) gen->getIndex() - start; + Dyninst::Address currAddr = addr + (unsigned) gen->getIndex() - start; insnCodeGen::generateBranch(*gen, currAddr, target); codeBufIndex_t done = gen->getIndex(); @@ -598,14 +585,14 @@ pcRelCall::pcRelCall(patchTarget *t, const instruction &i) : { } -pcRelCall::pcRelCall(Address target, const instruction &i) : +pcRelCall::pcRelCall(Dyninst::Address target, const instruction &i) : pcRelRegion(i), targ_addr(target), targ(NULL) { } -Address pcRelCall::get_target() +Dyninst::Address pcRelCall::get_target() { if (targ) return targ->get_address(); @@ -616,7 +603,7 @@ pcRelCall::~pcRelCall() { } -unsigned pcRelCall::apply(Address addr) +unsigned pcRelCall::apply(Dyninst::Address addr) { const unsigned char *origInsn = orig_instruc.ptr(); unsigned insnType = orig_instruc.type(); @@ -646,7 +633,7 @@ bool pcRelCall::canPreApply() return gen->startAddr() && (!targ || get_target()); } -pcRelData::pcRelData(Address a, const instruction &i) : +pcRelData::pcRelData(Dyninst::Address a, const instruction &i) : pcRelRegion(i), data_addr(a) { @@ -655,13 +642,13 @@ pcRelData::pcRelData(Address a, const instruction &i) : #define REL_DATA_MAXSIZE 2/*push r*/ + 10/*movImmToReg64*/ + 7/*orig insn*/ + 2/*pop r*/ #if !defined(arch_x86_64) -unsigned pcRelData::apply(Address) { +unsigned pcRelData::apply(Dyninst::Address) { assert(0); return 0; } #else -unsigned pcRelData::apply(Address addr) +unsigned pcRelData::apply(Dyninst::Address addr) { // We may need to change these from 32-bit relative // to 64-bit absolute. This happens with the jumps and calls @@ -688,7 +675,7 @@ unsigned pcRelData::apply(Address addr) if ((*(origInsn + nPrefixes) == 0x0F) && (*(origInsn + nPrefixes + 1) == 0x38 || *(origInsn + nPrefixes + 1) == 0x3A)) nOpcodeBytes = 3; - Register pointer_reg = (Register)-1; + Dyninst::Register pointer_reg = (Dyninst::Register)-1; if (!is_disp32(newDisp+insnSz) && !is_addr32(data_addr)) { // Case C: replace with 64-bit. @@ -708,31 +695,30 @@ unsigned pcRelData::apply(Address addr) addr += copy_prefixes(origInsn, newInsn, insnType); if (*origInsn == 0x0F) { - *newInsn++ = *origInsn++; + append_memory_as_byte(newInsn, *origInsn++); // 3-byte opcode support if (*origInsn == 0x38 || *origInsn == 0x3A) { - *newInsn++ = *origInsn++; + append_memory_as_byte(newInsn, *origInsn++); } } // And the normal opcode - *newInsn++ = *origInsn++; + append_memory_as_byte(newInsn, *origInsn++); if (is_data_abs64) { // change ModRM byte to use [pointer_reg]: requires // us to change last three bits (the r/m field) // to the value of pointer_reg unsigned char mod_rm = *origInsn++; - assert(pointer_reg != (Register)-1); + assert(pointer_reg != (Dyninst::Register)-1); mod_rm = (mod_rm & 0xf8) + pointer_reg; - *newInsn++ = mod_rm; + append_memory_as_byte(newInsn, mod_rm); } else if (is_disp32(newDisp+insnSz)) { // Whee easy case - *newInsn++ = *origInsn++; + append_memory_as_byte(newInsn, *origInsn++); // Size doesn't change.... - *((int *)newInsn) = (int)(newDisp - insnSz); - newInsn += 4; + append_memory_as(newInsn, static_cast(newDisp - insnSz)); } else if (is_addr32(data_addr)) { assert(!is_disp32(newDisp+insnSz)); @@ -740,14 +726,13 @@ unsigned pcRelData::apply(Address addr) // change ModRM byte to use SIB addressing (r/m == 4) mod_rm = (mod_rm & 0xf8) + 4; - *newInsn++ = mod_rm; + append_memory_as_byte(newInsn, mod_rm); // SIB == 0x25 specifies [disp32] addressing when mod == 0 - *newInsn++ = 0x25; + append_memory_as_byte(newInsn, 0x25); // now throw in the displacement (the absolute 32-bit address) - *((int *)newInsn) = (int)(data_addr); - newInsn += 4; + append_memory_as(newInsn, static_cast(data_addr)); } else { // Should never be reached... @@ -758,13 +743,13 @@ unsigned pcRelData::apply(Address addr) // so we copy over the rest of the instruction here origInsn += 4; while (origInsn - origInsnStart < (int)insnSz) - *newInsn++ = *origInsn++; + append_memory_as_byte(newInsn, *origInsn++); SET_PTR(newInsn, *gen); if (is_data_abs64) { // Cleanup on aisle pointer_reg... - assert(pointer_reg != (Register)-1); + assert(pointer_reg != (Dyninst::Register)-1); emitPopReg64(pointer_reg, *gen); } return (unsigned) (newInsn - orig_loc); @@ -789,9 +774,9 @@ bool pcRelData::canPreApply() * The comments and naming schemes in this function assume some familiarity with * the IA32/IA32e instruction encoding. If you don't understand this, I suggest * you start with Chapter 2 of: - * _IA-32 Intel Architecture Software Developer's Manual, Volume 2a_ + * _IA-32 Intel Dyninst::Architecture Software Developer's Manual, Volume 2a_ * and appendix A of: - * _IA-32 Intel Architecture Software Developer's Manual, Volume 2b_ + * _IA-32 Intel Dyninst::Architecture Software Developer's Manual, Volume 2b_ * * This function takes an instruction that accesses memory, and emits a * copy of that instruction that has the load/store replaces with a load/store @@ -802,15 +787,15 @@ bool pcRelData::canPreApply() **/ bool insnCodeGen::generateMem(codeGen &gen, instruction & insn, - Address /*origAddr*/, - Address /*newAddr*/, - Register loadExpr, - Register storeExpr) + Dyninst::Address /*origAddr*/, + Dyninst::Address /*newAddr*/, + Dyninst::Register loadExpr, + Dyninst::Register storeExpr) { /********** * Check parameters **********/ - Register newreg = Null_Register; + Dyninst::Register newreg = Null_Register; if (loadExpr != Null_Register && storeExpr != Null_Register) { cerr << "can't rewrite insn\nerror 1" << endl; return false; //Can only do one memory replace per instruction now @@ -1007,8 +992,8 @@ bool insnCodeGen::generateMem(codeGen &gen, } -bool insnCodeGen::modifyJump(Address targetAddr, NS_x86::instruction &insn, codeGen &gen) { - Address from = gen.currAddr(); +bool insnCodeGen::modifyJump(Dyninst::Address targetAddr, NS_x86::instruction &insn, codeGen &gen) { + Dyninst::Address from = gen.currAddr(); const unsigned char *origInsn = insn.ptr(); unsigned insnType = insn.type(); @@ -1025,12 +1010,12 @@ bool insnCodeGen::modifyJump(Address targetAddr, NS_x86::instruction &insn, code return true; } -bool insnCodeGen::modifyJcc(Address targetAddr, NS_x86::instruction &insn, codeGen &gen) { +bool insnCodeGen::modifyJcc(Dyninst::Address targetAddr, NS_x86::instruction &insn, codeGen &gen) { const unsigned char *origInsn = insn.ptr(); unsigned insnType = insn.type(); - Address from = gen.currAddr(); + Dyninst::Address from = gen.currAddr(); - Address potential; + Dyninst::Address potential; signed long disp; codeBufIndex_t start = gen.getIndex(); GET_PTR(newInsn, gen); @@ -1043,7 +1028,7 @@ bool insnCodeGen::modifyJcc(Address targetAddr, NS_x86::instruction &insn, codeG disp = targetAddr - potential; if (is_disp8(disp)) { convert_to_rel8(origInsn, newInsn); - *newInsn++ = (signed char) disp; + append_memory_as_byte(newInsn, disp); SET_PTR(newInsn, gen); return true; } @@ -1068,8 +1053,7 @@ bool insnCodeGen::modifyJcc(Address targetAddr, NS_x86::instruction &insn, codeG disp = targetAddr - potential; if (is_disp32(disp)) { convert_to_rel32(origInsn, newInsn); - *((signed int *) newInsn) = (signed int) disp; - newInsn += 4; + append_memory_as(newInsn, static_cast(disp)); SET_PTR(newInsn, gen); return true; } @@ -1086,10 +1070,10 @@ bool insnCodeGen::modifyJcc(Address targetAddr, NS_x86::instruction &insn, codeG // Moves as appropriate... convert_to_rel8(origInsn, newInsn); // We now want a 2-byte branch past the branch at B - *newInsn++ = 2; + append_memory_as_byte(newInsn, 2); // Now for the branch to C - unconditional branch - *newInsn++ = 0xEB; + append_memory_as_byte(newInsn, 0xEB); SET_PTR(newInsn, gen); // We now want to 1) move forward a byte (the offset we haven't filled // in yet) and track that we want to fill it in once we're done. @@ -1099,7 +1083,7 @@ bool insnCodeGen::modifyJcc(Address targetAddr, NS_x86::instruction &insn, codeG // Original address is a little skewed... // We've moved past the original address (to the tune of nPrefixes + 2 (JCC) + 2 (J)) - Address currAddr = from + (unsigned) gen.getIndex() - start; + Dyninst::Address currAddr = from + (unsigned) gen.getIndex() - start; insnCodeGen::generateBranch(gen, currAddr, targetAddr); codeBufIndex_t done = gen.getIndex(); @@ -1109,13 +1093,13 @@ bool insnCodeGen::modifyJcc(Address targetAddr, NS_x86::instruction &insn, codeG //Go back and fill in the size of the jump at B into the 'jump ' // The -1 is because - *newInsn = gen.getDisplacement(jump_from_index, done); + append_memory_as_byte(newInsn, gen.getDisplacement(jump_from_index, done)); SET_PTR(newInsn, gen); gen.setIndex(done); return true; } -bool insnCodeGen::modifyCall(Address targetAddr, NS_x86::instruction &insn, codeGen &gen) { +bool insnCodeGen::modifyCall(Dyninst::Address targetAddr, NS_x86::instruction &insn, codeGen &gen) { // If we're within a 32-bit displacement, we reuse the original call. // Otherwise we say "welp, sucks to be us", strip any prefixes, // and do a 64-bit long thang @@ -1145,7 +1129,7 @@ bool insnCodeGen::modifyCall(Address targetAddr, NS_x86::instruction &insn, code return true; } -bool insnCodeGen::modifyData(Address targetAddr, instruction &insn, codeGen &gen) +bool insnCodeGen::modifyData(Dyninst::Address targetAddr, instruction &insn, codeGen &gen) { // We may need to change these from 32-bit relative // to 64-bit absolute. This happens with the jumps and calls @@ -1159,13 +1143,13 @@ bool insnCodeGen::modifyData(Address targetAddr, instruction &insn, codeGen &gen const unsigned char* origInsnStart = origInsn; // unsigned insnType = insn.type(); unsigned insnSz = insn.size(); - Address from = gen.currAddr(); + Dyninst::Address from = gen.currAddr(); bool is_data_abs64 = false; signed long newDisp = targetAddr - from; GET_PTR(newInsn, gen); - Register pointer_reg = (Register)-1; + Dyninst::Register pointer_reg = (Dyninst::Register)-1; /******************************************* prefix/opcode ****************/ @@ -1220,28 +1204,26 @@ bool insnCodeGen::modifyData(Address targetAddr, instruction &insn, codeGen &gen mod_rm = (mod_rm & 0xf8) | pointer_reg; /* Set the new ModR/M byte of the new instruction */ - *newInsn++ = mod_rm; + append_memory_as_byte(newInsn, mod_rm); } else if (is_disp32(newDisp + insnSz)) { /* Instruction can remain a 32 bit instruction */ /* Copy the ModR/M byte */ - *newInsn++ = mod_rm; + append_memory_as_byte(newInsn, mod_rm); /* Use the new relative displacement */ - *((int *)newInsn) = (int)(newDisp - insnSz); - newInsn += 4; + append_memory_as(newInsn, static_cast(newDisp - insnSz)); } else if (is_addr32(targetAddr)) { // change ModRM byte to use SIB addressing (r/m == 4) mod_rm = (mod_rm & 0xf8) + 4; - *newInsn++ = mod_rm; + append_memory_as_byte(newInsn, mod_rm); // SIB == 0x25 specifies [disp32] addressing when mod == 0 - *newInsn++ = 0x25; + append_memory_as_byte(newInsn, 0x25); // now throw in the displacement (the absolute 32-bit address) - *((int *)newInsn) = (int)(targetAddr); - newInsn += 4; + append_memory_as(newInsn, static_cast(targetAddr)); } else { /* Impossible case */ assert(0); @@ -1251,14 +1233,14 @@ bool insnCodeGen::modifyData(Address targetAddr, instruction &insn, codeGen &gen // so we copy over the rest of the instruction here origInsn += 4; while (origInsn - origInsnStart < (int)insnSz) - *newInsn++ = *origInsn++; + append_memory_as_byte(newInsn, *origInsn++); SET_PTR(newInsn, gen); #if defined(arch_x86_64) if (is_data_abs64) { // Cleanup on aisle pointer_reg... - assert(pointer_reg != (Register)-1); + assert(pointer_reg != (Dyninst::Register)-1); emitPopReg64(pointer_reg, gen); } #endif @@ -1266,7 +1248,7 @@ bool insnCodeGen::modifyData(Address targetAddr, instruction &insn, codeGen &gen return true; } -bool insnCodeGen::modifyDisp(signed long newDisp, instruction &insn, codeGen &gen, Architecture arch, Address addr) { +bool insnCodeGen::modifyDisp(signed long newDisp, instruction &insn, codeGen &gen, Dyninst::Architecture arch, Dyninst::Address addr) { relocation_cerr << "\t\tmodifyDisp " << std::hex << addr @@ -1275,8 +1257,6 @@ bool insnCodeGen::modifyDisp(signed long newDisp, instruction &insn, codeGen &ge const unsigned char* origInsn = insn.ptr(); unsigned insnSz = insn.size(); - unsigned newInsnSz = 0; - InstructionAPI::InstructionDecoder d2(origInsn, insnSz, arch); InstructionAPI::Instruction origInsnPtr = d2.decode(); @@ -1333,9 +1313,6 @@ bool insnCodeGen::modifyDisp(signed long newDisp, instruction &insn, codeGen &ge newInsn += opcode_len; origInsn += opcode_len; - /* Update the new instruction size */ - newInsnSz = pref_count + opcode_len; - /******************************************* modRM *************************/ // Update displacement size (mod bits in ModRM), if necessary int expectedDifference = 0; @@ -1405,16 +1382,13 @@ bool insnCodeGen::modifyDisp(signed long newDisp, instruction &insn, codeGen &ge } // Copy MODRM byte - *newInsn++ = modrm; - newInsnSz++; + append_memory_as_byte(newInsn, modrm); // Copy SIB byte - *newInsn++ = sib; - newInsnSz++; + append_memory_as_byte(newInsn, sib); } else { // Copy MODRM byte - *newInsn++ = modrm; - newInsnSz++; + append_memory_as_byte(newInsn, modrm); // Skip SIB byte } @@ -1425,13 +1399,9 @@ bool insnCodeGen::modifyDisp(signed long newDisp, instruction &insn, codeGen &ge if (origDisp != newDisp) { // Replace displacement if (is_disp8(newDisp)) { - *((signed char *)newInsn) = (signed char)(newDisp); - newInsn += sizeof(signed char); - newInsnSz += sizeof(signed char); + append_memory_as_byte(newInsn, newDisp); } else if (is_disp32(newDisp)) { - *((int *)newInsn) = (int)(newDisp); - newInsn += sizeof(int); - newInsnSz += sizeof(int); + append_memory_as(newInsn, static_cast(newDisp)); } else { // Should never be reached... assert(0); @@ -1441,9 +1411,9 @@ bool insnCodeGen::modifyDisp(signed long newDisp, instruction &insn, codeGen &ge if (origDispSize == -1) { // Do nothing } else if (origDispSize == 8) { - origInsn += sizeof(signed char); + origInsn += sizeof(uint8_t); } else if (origDispSize == 32) { - origInsn += sizeof(int); + origInsn += sizeof(uint32_t); } else { // Should never be reached assert(0); @@ -1454,13 +1424,13 @@ bool insnCodeGen::modifyDisp(signed long newDisp, instruction &insn, codeGen &ge // there may be an immediate after the displacement // so we copy over the rest of the instruction here while (origInsn - origInsnStart < (int)insnSz) { - unsigned char nextByte = *origInsn++; - *newInsn++ = nextByte; - newInsnSz++; + auto nextByte = Dyninst::read_memory_as(origInsn); + append_memory_as_byte(newInsn, nextByte); } /******************************** done ************************************/ + auto newInsnSz = newInsn - newInsnStart; InstructionAPI::InstructionDecoder d(newInsnStart, newInsnSz, arch); InstructionAPI::Instruction i = d.decode(); diff --git a/dyninstAPI/src/codegen-x86.h b/dyninstAPI/src/codegen-x86.h index 8bc091f414..308b0b7c8b 100644 --- a/dyninstAPI/src/codegen-x86.h +++ b/dyninstAPI/src/codegen-x86.h @@ -32,9 +32,10 @@ #include #include #include -#include "dyn_regs.h" +#include "Architecture.h" #include "entryIDs.h" - +#include "dyntypes.h" +#include "dyn_register.h" #if !defined(arch_x86) && !defined(arch_x86_64) @@ -62,14 +63,14 @@ class insnCodeGen { public: // More code generation - static void generatePush64(codeGen &gen, Address val); + static void generatePush64(codeGen &gen, Dyninst::Address val); // Code generation - static void generateBranch(codeGen &gen, Address from, Address to); + static void generateBranch(codeGen &gen, Dyninst::Address from, Dyninst::Address to); static void generateBranch(codeGen &gen, int disp); - static void generateBranch64(codeGen &gen, Address to); - static void generateBranch32(codeGen &gen, Address to); - static void generateCall(codeGen &gen, Address from, Address to); + static void generateBranch64(codeGen &gen, Dyninst::Address to); + static void generateBranch32(codeGen &gen, Dyninst::Address to); + static void generateCall(codeGen &gen, Dyninst::Address from, Dyninst::Address to); // We may want to generate an efficient set 'o nops static void generateNOOP(codeGen &gen, unsigned size = 1); @@ -86,33 +87,33 @@ class insnCodeGen { static bool generate(codeGen &gen, instruction & insn, AddressSpace *addrSpace, - Address origAddr, - Address newAddr, + Dyninst::Address origAddr, + Dyninst::Address newAddr, patchTarget *fallthroughOverride = NULL, patchTarget *targetOverride = NULL); static bool generateMem(codeGen &gen, instruction & insn, - Address origAddr, - Address newAddr, - Register newLoadReg, - Register newStoreReg); + Dyninst::Address origAddr, + Dyninst::Address newAddr, + Dyninst::Register newLoadReg, + Dyninst::Register newStoreReg); - static bool modifyJump(Address target, + static bool modifyJump(Dyninst::Address target, NS_x86::instruction &insn, codeGen &gen); - static bool modifyJcc(Address target, + static bool modifyJcc(Dyninst::Address target, NS_x86::instruction &insn, codeGen &gen); - static bool modifyCall(Address target, + static bool modifyCall(Dyninst::Address target, NS_x86::instruction &insn, codeGen &gen); - static bool modifyData(Address target, + static bool modifyData(Dyninst::Address target, NS_x86::instruction &insn, codeGen &gen); static bool modifyDisp(signed long newDisp, NS_x86::instruction &insn, - codeGen &gen, Architecture arch, Address addr); + codeGen &gen, Dyninst::Architecture arch, Dyninst::Address addr); }; diff --git a/dyninstAPI/src/codegen.C b/dyninstAPI/src/codegen.C index 09760a6f98..5e016ecd8d 100644 --- a/dyninstAPI/src/codegen.C +++ b/dyninstAPI/src/codegen.C @@ -30,6 +30,7 @@ // Code generation +#include #include #include #include @@ -37,7 +38,6 @@ #include "addressSpace.h" #include "dynThread.h" #include "dynProcess.h" -#include "common/src/Types.h" #include "compiler_annotations.h" #include "codegen.h" #include "util.h" @@ -70,7 +70,7 @@ codeGen::codeGen() : thr_(NULL), rs_(NULL), t_(NULL), - addr_((Address)-1), + addr_((Dyninst::Address)-1), ip_(NULL), f_(NULL), bt_(NULL), @@ -94,7 +94,7 @@ codeGen::codeGen(unsigned size) : thr_(NULL), rs_(NULL), t_(NULL), - addr_((Address)-1), + addr_((Dyninst::Address)-1), ip_(NULL), f_(NULL), bt_(NULL), @@ -125,7 +125,7 @@ codeGen::codeGen(codeBuf_t *buffer, int size) : thr_(NULL), rs_(NULL), t_(NULL), - addr_((Address)-1), + addr_((Dyninst::Address)-1), ip_(NULL), f_(NULL), bt_(NULL), @@ -440,13 +440,13 @@ long codeGen::getDisplacement(codeBufIndex_t from, codeBufIndex_t to) { return ((to_l - from_l) * CODE_GEN_OFFSET_SIZE); } -Address codeGen::currAddr() const { - if(addr_ == (Address) -1) return (Address) -1; - assert(addr_ != (Address) -1); +Dyninst::Address codeGen::currAddr() const { + if(addr_ == (Dyninst::Address) -1) return (Dyninst::Address) -1; + assert(addr_ != (Dyninst::Address) -1); return currAddr(addr_); } -Address codeGen::currAddr(Address base) const { +Dyninst::Address codeGen::currAddr(Dyninst::Address base) const { return (offset_ * CODE_GEN_OFFSET_SIZE) + base; } @@ -529,7 +529,7 @@ void codeGen::addPCRelRegion(pcRelRegion *reg) { reg->gen = this; reg->cur_offset = used(); - if (startAddr() != (Address) -1 && reg->canPreApply()) { + if (startAddr() != (Dyninst::Address) -1 && reg->canPreApply()) { //If we already have addressess for everything (usually when relocating a function) // then don't bother creating the region, just generate the code. reg->apply(startAddr() + reg->cur_offset); @@ -542,7 +542,7 @@ void codeGen::addPCRelRegion(pcRelRegion *reg) { } } -void codeGen::applyPCRels(Address base) +void codeGen::applyPCRels(Dyninst::Address base) { vector::iterator i; @@ -633,14 +633,14 @@ void relocPatch::applyPatch() if (applied_) return; - Address addr = source_->get_address(); + Dyninst::Address addr = source_->get_address(); switch (ptype_) { - case pcrel: + case patch_type_t::pcrel: addr = addr - (gen_->startAddr() + offset_); DYNINST_FALLTHROUGH; - case abs: + case patch_type_t::abs: gen_->copy(&addr, size_, dest_); break; default: @@ -666,7 +666,7 @@ std::string patchTarget::get_name() const { toAddressPatch::~toAddressPatch() { } -Address toAddressPatch::get_address() const +Dyninst::Address toAddressPatch::get_address() const { return addr; } @@ -675,7 +675,7 @@ unsigned toAddressPatch::get_size() const { return 0; } -void toAddressPatch::set_address(Address a) { +void toAddressPatch::set_address(Dyninst::Address a) { addr = a; } @@ -744,13 +744,13 @@ const bitArray &codeGen::getRegsDefined() return regsDefined_; } -void codeGen::markRegDefined(Register r) { +void codeGen::markRegDefined(Dyninst::Register r) { if (!trackRegDefs_) return; regsDefined_[r] = true; } -bool codeGen::isRegDefined(Register r) { +bool codeGen::isRegDefined(Dyninst::Register r) { assert(trackRegDefs_); return regsDefined_[r]; } @@ -768,8 +768,8 @@ Dyninst::Architecture codeGen::getArch() const { return Arch_none; } -void codeGen::registerDefensivePad(block_instance *callBlock, Address padStart, unsigned padSize) { - // Register a match between a call instruction +void codeGen::registerDefensivePad(block_instance *callBlock, Dyninst::Address padStart, unsigned padSize) { + // Dyninst::Register a match between a call instruction // and a padding area post-reloc-call for // control flow interception purposes. // This is kind of hacky, btw. @@ -786,7 +786,7 @@ std::string codeGen::format() const { stringstream ret; - Address base = (addr_ != (Address)-1) ? addr_ : 0; + Dyninst::Address base = (addr_ != (Dyninst::Address)-1) ? addr_ : 0; InstructionDecoder deco (buffer_,used(),aSpace_->getArch()); Instruction insn = deco.decode(); diff --git a/dyninstAPI/src/codegen.h b/dyninstAPI/src/codegen.h index 97a61fa2ac..d66319072e 100644 --- a/dyninstAPI/src/codegen.h +++ b/dyninstAPI/src/codegen.h @@ -30,10 +30,12 @@ #if !defined(_codegen_h_) #define _codegen_h_ +#include #include #include #include - +#include "dyntypes.h" +#include "dyn_register.h" #include "common/src/arch.h" #include "dyninstAPI/src/patch.h" @@ -168,8 +170,8 @@ class codeGen { // For code generation -- given the current state of // generation and a base address in the mutatee, // produce a "current" address. - Address currAddr() const; - Address currAddr(Address base) const; + Dyninst::Address currAddr() const; + Dyninst::Address currAddr(Dyninst::Address base) const; enum { cgNOP, cgTrap, cgIllegal }; @@ -185,7 +187,7 @@ class codeGen { //Have each region generate code with this codeGen object being // placed at addr - void applyPCRels(Address addr); + void applyPCRels(Dyninst::Address addr); //Return true if there are any active regions. bool hasPCRels() const; @@ -195,8 +197,8 @@ class codeGen { //Create a patch into the codeRange void addPatch(codeBufIndex_t index, patchTarget *source, - unsigned size = sizeof(Address), - relocPatch::patch_type_t ptype = relocPatch::abs, + unsigned size = sizeof(Dyninst::Address), + relocPatch::patch_type_t ptype = relocPatch::patch_type_t::abs, Dyninst::Offset off = 0); std::vector &allPatches(); @@ -207,7 +209,7 @@ class codeGen { void setAddrSpace(AddressSpace *a); void setThread(PCThread *t) { thr_ = t; } void setRegisterSpace(registerSpace *r) { rs_ = r; } - void setAddr(Address a) { addr_ = a; } + void setAddr(Dyninst::Address a) { addr_ = a; } void setPoint(instPoint *i) { ip_ = i; } void setRegTracker(regTracker_t *t) { t_ = t; } void setCodeEmitter(Emitter *emitter) { emitter_ = emitter; } @@ -218,7 +220,7 @@ class codeGen { unsigned width() const; AddressSpace *addrSpace() const; PCThread *thread(); - Address startAddr() const { return addr_; } + Dyninst::Address startAddr() const { return addr_; } instPoint *point() const; baseTramp *bt() const { return bt_; } func_instance *func() const; @@ -239,24 +241,24 @@ class codeGen { void beginTrackRegDefs(); void endTrackRegDefs(); const bitArray &getRegsDefined(); - void markRegDefined(Register r); - bool isRegDefined(Register r); + void markRegDefined(Dyninst::Register r); + bool isRegDefined(Dyninst::Register r); void setPCRelUseCount(int c) { pc_rel_use_count = c; } int getPCRelUseCount() const { return pc_rel_use_count; } // SD-DYNINST // - typedef std::pair Extent; - void registerDefensivePad(block_instance *, Address, unsigned); + typedef std::pair Extent; + void registerDefensivePad(block_instance *, Dyninst::Address, unsigned); std::map &getDefensivePads() { return defensivePads_; } // Immediate uninstrumentation - void registerInstrumentation(baseTramp *bt, Address loc) { instrumentation_[bt] = loc; } - std::map &getInstrumentation() { return instrumentation_; } + void registerInstrumentation(baseTramp *bt, Dyninst::Address loc) { instrumentation_[bt] = loc; } + std::map &getInstrumentation() { return instrumentation_; } - void registerRemovedInstrumentation(baseTramp *bt, Address loc) { removedInstrumentation_[bt] = loc; } - std::map &getRemovedInstrumentation() { return removedInstrumentation_; } + void registerRemovedInstrumentation(baseTramp *bt, Dyninst::Address loc) { removedInstrumentation_[bt] = loc; } + std::map &getRemovedInstrumentation() { return removedInstrumentation_; } private: void realloc(unsigned newSize); @@ -274,7 +276,7 @@ class codeGen { PCThread *thr_; registerSpace *rs_; regTracker_t *t_; - Address addr_; + Dyninst::Address addr_; instPoint *ip_; func_instance *f_; baseTramp *bt_; @@ -292,8 +294,8 @@ class codeGen { std::vector pcrels_; std::map defensivePads_; - std::map instrumentation_; - std::map removedInstrumentation_; + std::map instrumentation_; + std::map removedInstrumentation_; }; #endif diff --git a/dyninstAPI/src/debug.C b/dyninstAPI/src/debug.C index 7e6862bf2c..24f46a1cf2 100644 --- a/dyninstAPI/src/debug.C +++ b/dyninstAPI/src/debug.C @@ -34,7 +34,6 @@ #include #include #include -#include "common/src/Pair.h" #include "util.h" #include "BPatch.h" #include "dyninstAPI/src/debug.h" diff --git a/dyninstAPI/src/debug.h b/dyninstAPI/src/debug.h index d0da2c527c..e600b3d53f 100644 --- a/dyninstAPI/src/debug.h +++ b/dyninstAPI/src/debug.h @@ -32,7 +32,6 @@ #define SHOWERROR_H #include -#include "common/src/Pair.h" #include "compiler_annotations.h" #define BPFATAL(x) bpfatal_lf(__FILE__, __LINE__, x) diff --git a/dyninstAPI/src/dynProcess.C b/dyninstAPI/src/dynProcess.C index 31a77cb3a0..96fc823f20 100644 --- a/dyninstAPI/src/dynProcess.C +++ b/dyninstAPI/src/dynProcess.C @@ -28,6 +28,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include "dynProcess.h" #include "dynThread.h" #include "pcEventHandler.h" @@ -46,8 +47,7 @@ #include "common/src/pathName.h" #include "PCErrors.h" -#include "MemoryEmulator/memEmulator.h" -#include +#include #include "symtabAPI/h/SymtabReader.h" #include "patchAPI/h/PatchMgr.h" @@ -56,6 +56,24 @@ #include +namespace { + // maximum number of addresses per outstanding printf! + const unsigned int _numaddrstrs=8; + char _addrstr[_numaddrstrs][19]; // "0x"+16+'\0' + + // Format an address string according to the size of the Address type. + // Note that "%x" outputs incorrect/incomplete addresses, and that "%lx" + // or system-dependent "%p" (generally also requiring a typecast to (void*)) + // must be used instead! + char *Address_str (Dyninst::Address addr) + { + static int i=0; + i=(i+1)%_numaddrstrs; + snprintf(_addrstr[i],19,"0x%016lX", addr); + return (_addrstr[i]); + } +} + using namespace Dyninst::ProcControlAPI; using std::map; using std::vector; @@ -839,7 +857,7 @@ bool PCProcess::loadRTLib() { // Install a breakpoint in DYNINSTtrapFunction. // This is used as RT signal. - Address addr = getRTTrapFuncAddr(); + Dyninst::Address addr = getRTTrapFuncAddr(); if (addr == 0) { startup_printf("%s[%d]: Cannot find DYNINSTtrapFunction. Needed as RT signal\n", FILE__, __LINE__); return false; @@ -944,10 +962,12 @@ bool PCProcess::insertBreakpointAtMain() { FILE__, __LINE__); return false; } - Address addr = main_function_->addr(); + Dyninst::Address addr = main_function_->addr(); + + // Libraries loaded before reaching 'main' can launch threads, so + // ensure they are all stopped before "executing" this breakpoint. + mainBrkPt_ = Breakpoint::newSynchronousBreakpoint(); - // Create the breakpoint - mainBrkPt_ = Breakpoint::newBreakpoint(); if( !pcProc_->addBreakpoint(addr, mainBrkPt_) ) { startup_printf("%s[%d]: failed to insert a breakpoint at main entry: 0x%lx\n", FILE__, __LINE__, addr); @@ -967,7 +987,7 @@ bool PCProcess::removeBreakpointAtMain() { return true; } - Address addr = main_function_->addr(); + Dyninst::Address addr = main_function_->addr(); if( !pcProc_->rmBreakpoint(addr, mainBrkPt_) ) { startup_printf("%s[%d]: failed to remove breakpoint at main entry: 0x%lx\n", @@ -1196,7 +1216,7 @@ bool PCProcess::writeDataSpace(void *inTracedProcess, u_int amount, cerr << "Writing to terminated process!" << endl; return false; } - bool result = pcProc_->writeMemory((Address)inTracedProcess, inSelf, + bool result = pcProc_->writeMemory((Dyninst::Address)inTracedProcess, inSelf, amount); if( BPatch_defensiveMode == proc()->getHybridMode() && !result ) { @@ -1204,7 +1224,7 @@ bool PCProcess::writeDataSpace(void *inTracedProcess, u_int amount, // from the page, remove them and try again PCMemPerm origRights, rights(true, true, true); - if (!pcProc_->setMemoryAccessRights((Address)inTracedProcess, + if (!pcProc_->setMemoryAccessRights((Dyninst::Address)inTracedProcess, amount, rights, origRights)) { cerr << "Fail to set memory permissions!" << endl; return false; @@ -1219,7 +1239,7 @@ bool PCProcess::writeDataSpace(void *inTracedProcess, u_int amount, */ if( origRights.isRX() || origRights.isR() ) { - result = pcProc_->writeMemory((Address)inTracedProcess, inSelf, + result = pcProc_->writeMemory((Dyninst::Address)inTracedProcess, inSelf, amount); /* @@ -1365,112 +1385,6 @@ bool PCProcess::removeThread(dynthread_t tid) { } extern Address getVarAddr(PCProcess *proc, std::string str); -#if 0 -bool PCProcess::registerThread(PCThread *thread) { - - Address tid = (Address) thread->getTid(); - Address index = thread->getIndex(); - - Address tmp = 0; - unsigned ptrsize = getAddressWidth(); - - if (tid == (Address) -1) return true; - if (index == (Address) -1) return true; - - if (!initializeRegisterThread()) { - startup_printf("%s[%d]: initializeRegisterThread failed\n", - FILE__, __LINE__); - - return false; - } - // Must match the "hash" algorithm used in the RT lib - int working = (tid % thread_hash_size); - while(1) { - tmp = 0; - if (!readDataWord(( void *)(thread_hash_indices + (working * ptrsize)), ptrsize, &tmp, false)) { - startup_printf("%s[%d]: Failed to read index slot, base 0x%lx, active 0x%lx\n", FILE__, __LINE__, - thread_hash_indices, thread_hash_indices + (working * ptrsize)); - return false; - } - startup_printf("%s[%d]: value of tid in slot %p is 0x%lx\n", - FILE__, __LINE__, thread_hash_indices + (working * ptrsize), tmp); - if (ptrsize == 4 && tmp == 0xffffffff) { - int index_int = (int) index; - int tid_int = (int) tid; - startup_printf("%s[%d]: writing %d to %p and 0x%x to %p\n", - FILE__, __LINE__, index_int, thread_hash_indices + (working * ptrsize), - tid_int, thread_hash_tids + (working * ptrsize)); - writeDataWord(( void *)(thread_hash_indices + (working * ptrsize)), ptrsize, &index_int); - writeDataWord(( void *)(thread_hash_tids + (working * ptrsize)), ptrsize, &tid_int); - break; - } - else if (ptrsize == 8 && tmp == (Address)-1) { - writeDataWord(( void *)(thread_hash_indices + (working * ptrsize)), ptrsize, &index); - writeDataWord(( void *)(thread_hash_tids + (working * ptrsize)), ptrsize, &tid); - break; - } - working++; - if (working == thread_hash_size) working = 0; - if (working == (int) (tid % thread_hash_size)) { - startup_printf("%s[%d]: Failed to find empty tid slot\n", FILE__, __LINE__); - return false; - } - } - return true; -} -bool PCProcess::unregisterThread(PCThread *thread) { - return true; - Address tid = (Address) thread->getTid(); - Address index = thread->getIndex(); - Address tmp = 0; - - unsigned ptrsize = getAddressWidth(); - if (tid == (Address) -1) return true; - if (index == (Address) -1) return true; - - initializeRegisterThread(); - - // Must match the "hash" algorithm used in the RT lib - int working = tid % thread_hash_size; - while(1) { - tmp = 0; - if (!readDataWord((void *)(thread_hash_tids + (working * ptrsize)), ptrsize, &tmp, false)) return false; - if (tmp == tid) { - // Zero it out - tmp = (Address) -1; - writeDataWord(( void *)(thread_hash_indices + (working * ptrsize)), ptrsize, &tmp); - break; - } - working++; - if (working == thread_hash_size) working = 0; - if (working == (int) (tid % thread_hash_size)) return false; - } - return true; -} - -bool PCProcess::initializeRegisterThread() { -// if (thread_hash_tids) return true; - - unsigned ptrsize = getAddressWidth(); - - Address tidPtr = getVarAddr(this, "DYNINST_thread_hash_tids"); - if (!tidPtr) return false; - Address indexPtr = getVarAddr(this, "DYNINST_thread_hash_indices"); - if (!indexPtr) return false; - Address sizePtr = getVarAddr(this, "DYNINST_thread_hash_size"); - if (!sizePtr) return false; - - if (!readDataWord((const void *)tidPtr, ptrsize, &thread_hash_tids, false)) return false; - - if (!readDataWord((const void *)indexPtr, ptrsize, &thread_hash_indices, false)) return false; - - if (!readDataWord((const void *)sizePtr, sizeof(int), &thread_hash_size, false)) return false; - - return true; -} -#endif - - void PCProcess::addThread(PCThread *thread) { pair::iterator, bool> result; result = threadsByTid_.insert(make_pair(thread->getTid(), thread)); @@ -1728,9 +1642,9 @@ bool PCProcess::inferiorMallocDynamic(int size, Address lo, Address hi) { // build AstNode for "DYNINSTos_malloc" call std::string callee = "DYNINSTos_malloc"; std::vector args(3); - args[0] = AstNode::operandNode(AstNode::Constant, (void *)(Address)size); - args[1] = AstNode::operandNode(AstNode::Constant, (void *)lo); - args[2] = AstNode::operandNode(AstNode::Constant, (void *)hi); + args[0] = AstNode::operandNode(AstNode::operandType::Constant, (void *)(Address)size); + args[1] = AstNode::operandNode(AstNode::operandType::Constant, (void *)lo); + args[2] = AstNode::operandNode(AstNode::operandType::Constant, (void *)hi); AstNodePtr code = AstNode::funcCallNode(callee, args); // issue RPC and wait for result @@ -1831,7 +1745,7 @@ void PCProcess::installInstrRequests(const std::vector &requests) } else { std::vector def_args; - def_args.push_back(AstNode::operandNode(AstNode::Constant, + def_args.push_back(AstNode::operandNode(AstNode::operandType::Constant, (void *)0)); ast = AstNode::funcCallNode(req->inst, def_args); @@ -1889,7 +1803,7 @@ bool PCProcess::postIRPC(void* buffer, int size, void* userData, bool runProcess return postIRPC_internal(buffer, size, size, - REG_NULL, + Null_Register, addr, userData, runProcessWhenDone, @@ -1936,7 +1850,7 @@ bool PCProcess::postIRPC(AstNodePtr action, void *userData, return false; } - Register resultReg = REG_NULL; + Register resultReg = Null_Register; if( !action->generateCode(irpcBuf, false, resultReg) ) { proccontrol_printf("%s[%d]: failed to generate code from AST\n", FILE__, __LINE__); @@ -2203,12 +2117,6 @@ bool PCProcess::getOverwrittenBlocks // 1. Read the modified page in from memory Address readAddr = curPageAddr; - if (isMemoryEmulated()) { - bool valid = false; - boost::tie(valid,readAddr) = getMemEm()->translate(curPageAddr); - cerr << "\t\t Reading from shadow page " << hex << readAddr << " instead of original " << curPageAddr << endl; - assert(valid); - } readTextSpace((void*)readAddr, MEM_PAGE_SIZE, memVersion); // 2. build overwritten region list by comparing shadow, memory @@ -2283,185 +2191,6 @@ void PCProcess::updateCodeBytes assert(objRanges.size() <= 1); //o/w analysis code may not be prepared for other cases } -#if 0 -static void otherFuncBlocks(func_instance *func, - const set &blks, - set &otherBlks) -{ - const func_instance::BlockSet &allBlocks = - func->blocks(); - for (func_instance::BlockSet::const_iterator bit = - allBlocks.begin(); - bit != allBlocks.end(); - bit++) - { - if (blks.end() == blks.find((*bit))) { - otherBlks.insert((*bit)); - } - } -} -#endif - -/* Summary - * Given a list of overwritten blocks, find blocks that are unreachable, - * functions that have been overwritten at their entry points and can go away, - * and new function entry for functions that are being overwritten while still - * executing - * - * variables - * f: the overwritten function - * ow: the set of overwritten blocks - * ex: the set of blocks that are executing on the call stack that were not overwritten - * - * primitives - * R(b,s): yields set of reachable blocks for collection of blocks b, starting - * at seed blocks s. - * B(f): the blocks pertaining to function f - * EP(f): the entry point of function f - * F(b): functions containing block b - * - * calculations - * Elim(f): the set of blocks to eliminate from function f. - * Elim(f) = B(f) - R( B(f)-ow , EP(f) ) - * New(f): new function entry candidates for f's surviving blocks. - * If EB(f) not in ow(f), empty set - * Else, all blocks b such that ( b in ex AND e in Elim(f) ) - * Eliminate New(f) elements that have ancestors in New(f) - * Del(f): A block can be deleted altogether if - * forall f in F(b): B(F) - R( B(f) - ow , New(f) U (EP(f) \ ow(f)) U (ex(f) intersect Elim(f)) ), - * b is not in the resulting set. In other words, b is not - * reachable from non-overwritten blocks in the functions in - * which it appears, seeded at new entry points and original - * non-overwritten entry points to the function, and at f's - * executing blocks if these will be deleted from the - * function (they constitute an entry point into the function - * even if they've been overwritten). - * DeadF: the set of functions that have no executing blocks - * and were overwritten in their entry blocks - * EP(f) in ow(f) AND ex(f) is empty - */ -bool PCProcess::getDeadCode -( const std::list & /*owBlocks*/, // input - std::set & /*delBlocks*/, //output: Del(for all f) - std::map > & /*elimMap*/, //output: elimF - std::list & /*deadFuncs*/, //output: DeadF - std::map & /*newFuncEntries*/) //output: newF -{ - assert(0 && "TODO"); - return false; -#if 0 - // do a stackwalk to see which functions are currently executing - std::vector > stacks; - std::vector
pcs; - if (!walkStacks(stacks)) { - inst_printf("%s[%d]: walkStacks failed\n", FILE__, __LINE__); - return false; - } - for (unsigned i = 0; i < stacks.size(); ++i) { - std::vector &stack = stacks[i]; - for (unsigned int j = 0; j < stack.size(); ++j) { - Address origPC = 0; - vector dontcare1; - baseTramp *dontcare2 = NULL; - getAddrInfo(stack[j].getPC(), origPC, dontcare1, dontcare2); - pcs.push_back( origPC ); - } - } - - // group blocks by function - std::map > deadMap; - std::set deadEntryFuncs; - std::set
owBlockAddrs; - for (list::const_iterator bIter=owBlocks.begin(); - bIter != owBlocks.end(); - bIter++) - { - deadMap[(*bIter)->func()].insert(*bIter); - owBlockAddrs.insert((*bIter)->start()); - if ((*bIter)->llb() == (*bIter)->func()->ifunc()->entry()) { - deadEntryFuncs.insert((*bIter)->func()); - } - } - - // for each modified function, calculate ex, ElimF, NewF, DelF - for (map >::iterator fit = deadMap.begin(); - fit != deadMap.end(); - fit++) - { - - // calculate ex(f) - set execBlocks; - for (unsigned pidx=0; pidx < pcs.size(); pidx++) { - std::set candidateBlocks; - fit->first->findBlocksByAddr(pcs[pidx], candidateBlocks); - for (std::set::iterator cb_iter = candidateBlocks.begin(); - cb_iter != candidateBlocks.end(); ++cb_iter) { - block_instance *exB = *cb_iter; - if (exB && owBlockAddrs.end() == owBlockAddrs.find( - exB->start())) - { - execBlocks.insert(exB); - } - } - } - - // calculate DeadF: EP(f) in ow and EP(f) not in ex - if ( 0 == execBlocks.size() ) { - set::iterator eb = fit->second.find( - fit->first->entryBlock()); - if (eb != fit->second.end()) { - deadFuncs.push_back(fit->first); - continue;// treated specially, don't need elimF, NewF or DelF - } - } - - // calculate elimF - set keepF; - list seedBs; - seedBs.push_back(fit->first->entryBlock()); - fit->first->getReachableBlocks(fit->second, seedBs, keepF); - otherFuncBlocks(fit->first, keepF, elimMap[fit->first]); - - // calculate NewF - if (deadEntryFuncs.end() != deadEntryFuncs.find(fit->first)) { - for (set::iterator bit = execBlocks.begin(); - bit != execBlocks.end(); - bit++) - { - if (elimMap[fit->first].end() != - elimMap[fit->first].find(*bit)) - { - newFuncEntries[fit->first] = *bit; - break; // just need one candidate - } - } - } - - // calculate Del(f) - seedBs.clear(); - if (deadEntryFuncs.end() == deadEntryFuncs.find(fit->first)) { - seedBs.push_back(fit->first->entryBlock()); - } - else if (newFuncEntries.end() != newFuncEntries.find(fit->first)) { - seedBs.push_back(newFuncEntries[fit->first]); - } - for (set::iterator xit = execBlocks.begin(); - xit != execBlocks.end(); - xit++) - { - if (elimMap[fit->first].end() != elimMap[fit->first].find(*xit)) { - seedBs.push_back(*xit); - } - } - keepF.clear(); - fit->first->getReachableBlocks(fit->second, seedBs, keepF); - otherFuncBlocks(fit->first, keepF, delBlocks); - - } - - return true; -#endif -} // will flush addresses of all addresses in the specified range, if the // range is null, flush all addresses from the cache. Also flush diff --git a/dyninstAPI/src/dynProcess.h b/dyninstAPI/src/dynProcess.h index 34585aae6b..516d7b4a54 100644 --- a/dyninstAPI/src/dynProcess.h +++ b/dyninstAPI/src/dynProcess.h @@ -36,6 +36,11 @@ * A class that encapsulates a ProcControlAPI Process for the rest of Dyninst. */ +#include +#include +#include +#include +#include #include #include #include @@ -232,13 +237,6 @@ class PCProcess : public AddressSpace { std::list >& overwrittenRegions,//output std::list &writtenBBIs);//output - bool getDeadCode - ( const std::list &owBlocks, // input - std::set &delBlocks, //output: Del(for all f) - std::map > &elimMap, //output: elimF - std::list &deadFuncs, //output: DeadF - std::map &newFuncEntries); //output: newF - // synch modified mapped objects with current memory contents mapped_object *createObjectNoFile(Address addr); void updateCodeBytes( const std::list > &owRegions); @@ -289,7 +287,6 @@ class PCProcess : public AddressSpace { virtual bool multithread_capable(bool ignoreIfMtNotSet = false); // platform-specific virtual bool multithread_ready(bool ignoreIfMtNotSet = false); virtual bool needsPIC(); - //virtual bool unregisterTrapMapping(Address from); virtual void addTrap(Address from, Address to, codeGen &gen); virtual void removeTrap(Address from); @@ -627,7 +624,7 @@ class inferiorRPCinProgress : public codeRange { rpc(ProcControlAPI::IRPC::ptr()), rpcStartAddr(0), rpcCompletionAddr(0), - resultRegister(REG_NULL), + resultRegister(Null_Register), returnValue(NULL), runProcWhenDone(false), isComplete(false), diff --git a/dyninstAPI/src/dynThread.C b/dyninstAPI/src/dynThread.C index 1e0bc1a606..7a53eefe18 100644 --- a/dyninstAPI/src/dynThread.C +++ b/dyninstAPI/src/dynThread.C @@ -34,7 +34,6 @@ #include "function.h" #include "mapped_module.h" #include "mapped_object.h" -#include "dyninst.h" using namespace Dyninst::ProcControlAPI; diff --git a/dyninstAPI/src/dynThread.h b/dyninstAPI/src/dynThread.h index f788f3ba7a..edeb70a3a6 100644 --- a/dyninstAPI/src/dynThread.h +++ b/dyninstAPI/src/dynThread.h @@ -31,6 +31,7 @@ #ifndef DYNTHREAD_H #define DYNTHREAD_H +#include #include "frame.h" #include "PCProcess.h" diff --git a/dyninstAPI/src/emit-aarch64.C b/dyninstAPI/src/emit-aarch64.C index f797dfd71c..31c9bde5f4 100644 --- a/dyninstAPI/src/emit-aarch64.C +++ b/dyninstAPI/src/emit-aarch64.C @@ -35,7 +35,6 @@ /* #include #include -#include "common/src/Types.h" #include "dyninstAPI/src/codegen.h" #include "dyninstAPI/src/function.h" #include "dyninstAPI/src/inst-x86.h" @@ -81,7 +80,7 @@ codeBufIndex_t EmitterAARCH64::emitIf( void EmitterAARCH64::emitLoadConst(Register dest, Address imm, codeGen &gen) { - insnCodeGen::loadImmIntoReg
(gen, dest, imm); + insnCodeGen::loadImmIntoReg(gen, dest, imm); } @@ -89,7 +88,7 @@ void EmitterAARCH64::emitLoad(Register dest, Address addr, int size, codeGen &ge { Register scratch = gen.rs()->getScratchRegister(gen); - insnCodeGen::loadImmIntoReg
(gen, scratch, addr); + insnCodeGen::loadImmIntoReg(gen, scratch, addr); insnCodeGen::generateMemAccess(gen, insnCodeGen::Load, dest, scratch, 0, size, insnCodeGen::Post); @@ -102,7 +101,7 @@ void EmitterAARCH64::emitStore(Address addr, Register src, int size, codeGen &ge { Register scratch = gen.rs()->getScratchRegister(gen); - insnCodeGen::loadImmIntoReg
(gen, scratch, addr); + insnCodeGen::loadImmIntoReg(gen, scratch, addr); insnCodeGen::generateMemAccess(gen, insnCodeGen::Store, src, scratch, 0, size, insnCodeGen::Pre); @@ -153,14 +152,14 @@ void EmitterAARCH64::emitRelOp( insnCodeGen::generateAddSubShifted(gen, insnCodeGen::Sub, 0, 0, src2, src1, dest, true); // make dest = 1, meaning true - insnCodeGen::loadImmIntoReg
(gen, dest, 0x1); + insnCodeGen::loadImmIntoReg(gen, dest, 0x1); // insert conditional jump to skip dest=0 in case the comparison resulted true // therefore keeping dest=1 insnCodeGen::generateConditionalBranch(gen, 8, opcode, s); // make dest = 0, in case it fails the branch - insnCodeGen::loadImmIntoReg
(gen, dest, 0x0); + insnCodeGen::loadImmIntoReg(gen, dest, 0x0); } @@ -209,14 +208,14 @@ void EmitterAARCH64::emitRelOpImm( insnCodeGen::generateAddSubShifted(gen, insnCodeGen::Sub, 0, 0, src2, src1, dest, true); // make dest = 1, meaning true - insnCodeGen::loadImmIntoReg
(gen, dest, 0x1); + insnCodeGen::loadImmIntoReg(gen, dest, 0x1); // insert conditional jump to skip dest=0 in case the comparison resulted true // therefore keeping dest=1 insnCodeGen::generateConditionalBranch(gen, 8, opcode, s); // make dest = 0, in case it fails the branch - insnCodeGen::loadImmIntoReg
(gen, dest, 0x0); + insnCodeGen::loadImmIntoReg(gen, dest, 0x0); gen.rs()->freeRegister(src2); gen.markRegDefined(dest); @@ -260,7 +259,7 @@ void EmitterAARCH64::emitLoadOrigRegRelative( { // load the stored register 'base' into dest emitLoadOrigRegister(base, scratch, gen); - insnCodeGen::loadImmIntoReg(gen, dest, offset); + insnCodeGen::loadImmIntoReg(gen, dest, offset); insnCodeGen::generateAddSubShifted(gen, insnCodeGen::Add, 0, 0, dest, scratch, dest, true); } } diff --git a/dyninstAPI/src/emit-aarch64.h b/dyninstAPI/src/emit-aarch64.h index 65a524921f..d436dfa8ec 100644 --- a/dyninstAPI/src/emit-aarch64.h +++ b/dyninstAPI/src/emit-aarch64.h @@ -32,6 +32,8 @@ #ifndef _EMITTER_AARCH64_H #define _EMITTER_AARCH64_H +#include +#include #include "common/src/headers.h" #include "dyninstAPI/src/instPoint.h" #include "dyninstAPI/src/baseTramp.h" diff --git a/dyninstAPI/src/emit-power.h b/dyninstAPI/src/emit-power.h index 58ccd24c2d..235a551d09 100644 --- a/dyninstAPI/src/emit-power.h +++ b/dyninstAPI/src/emit-power.h @@ -36,6 +36,8 @@ #ifndef _EMITTER_POWER_H #define _EMITTER_POWER_H +#include +#include #include "common/src/headers.h" #include "dyninstAPI/src/instPoint.h" #include "dyninstAPI/src/baseTramp.h" diff --git a/dyninstAPI/src/emit-x86.C b/dyninstAPI/src/emit-x86.C index 9519f32e13..ac5f681ba7 100644 --- a/dyninstAPI/src/emit-x86.C +++ b/dyninstAPI/src/emit-x86.C @@ -33,9 +33,9 @@ * $Id: emit-x86.C,v 1.64 2008/09/11 20:14:14 mlam Exp $ */ +#include #include #include -#include "common/src/Types.h" #include "compiler_annotations.h" #include "dyninstAPI/src/codegen.h" #include "dyninstAPI/src/function.h" @@ -56,6 +56,7 @@ #include "ABI.h" #include "liveness.h" #include "RegisterConversion.h" +#include "unaligned_memory_access.h" const int EmitterIA32::mt_offset = -4; #if defined(arch_x86_64) @@ -73,24 +74,25 @@ static void emitXMMRegsSaveRestore(codeGen& gen, bool isRestore) continue; } unsigned char offset = reg * 16; - *insn++ = 0x66; *insn++ = 0x0f; + append_memory_as_byte(insn, 0x66); + append_memory_as_byte(insn, 0x0f); // 6f to save, 7f to restore if(isRestore) { - *insn++ = 0x6f; + append_memory_as_byte(insn, 0x6f); } else { - *insn++ = 0x7f; + append_memory_as_byte(insn, 0x7f); } if (reg == 0) { - *insn++ = 0x00; + append_memory_as_byte(insn, 0x00); } else { unsigned char modrm = 0x40 + (0x8 * reg); - *insn++ = modrm; - *insn++ = offset; + append_memory_as_byte(insn, modrm); + append_memory_as_byte(insn, offset); } } SET_PTR(insn, gen); @@ -139,7 +141,7 @@ codeBufIndex_t EmitterIA32::emitIf(Register expr_reg, Register target, RegContro // Jump displacements are from the end of the insn, not start. The // one we're emitting has a size of 6. - int disp = 0; + int32_t disp = 0; if (target) disp = target - 6; @@ -147,12 +149,12 @@ codeBufIndex_t EmitterIA32::emitIf(Register expr_reg, Register target, RegContro gen.rs()->pushNewRegState(); GET_PTR(insn, gen); // je dest - *insn++ = 0x0F; - *insn++ = 0x84; - *((int *)insn) = disp; + append_memory_as_byte(insn, 0x0F); + append_memory_as_byte(insn, 0x84); + write_memory_as(insn, int32_t{disp}); if (disp == 0) { SET_PTR(insn, gen); - gen.addPatch(gen.getIndex(), NULL, sizeof(int), relocPatch::pcrel, + gen.addPatch(gen.getIndex(), NULL, sizeof(int), relocPatch::patch_type_t::pcrel, gen.used() + sizeof(int)); REGET_PTR(insn, gen); } @@ -185,7 +187,7 @@ void EmitterIA32::emitRelOp(unsigned op, Register dest, Register src1, Register unsigned char opcode = cmovOpcodeFromRelOp(op, s); GET_PTR(insn, gen); - *insn++ = 0x0f; + append_memory_as_byte(insn, 0x0f); SET_PTR(insn, gen); emitOpRegReg(opcode, dest_r, scratch_r, gen); //CMOVcc scratch,dest gen.rs()->freeRegister(scratch); @@ -341,11 +343,11 @@ bool EmitterIA32::emitLoadRelativeSegReg(Register /*dest*/, Address offset, Regi // WARNING: dest is hard-coded to EAX currently emitSegPrefix(base, gen); GET_PTR(insn, gen); - *insn++ = 0xa1; - *insn++ = offset; - *insn++ = 0x00; - *insn++ = 0x00; - *insn++ = 0x00; + append_memory_as_byte(insn, 0xa1); + append_memory_as_byte(insn, offset); + append_memory_as_byte(insn, 0x00); + append_memory_as_byte(insn, 0x00); + append_memory_as_byte(insn, 0x00); SET_PTR(insn, gen); return true; } @@ -762,10 +764,10 @@ bool EmitterIA32::emitBTSaves(baseTramp* bt, codeGen &gen) // fxsave (%esp) ; 0x0f 0xae 0x04 0x24 GET_PTR(insn, gen); - *insn++ = 0x0f; - *insn++ = 0xae; - *insn++ = 0x04; - *insn++ = 0x24; + append_memory_as_byte(insn, 0x0f); + append_memory_as_byte(insn, 0xae); + append_memory_as_byte(insn, 0x04); + append_memory_as_byte(insn, 0x24); SET_PTR(insn, gen); } else { @@ -803,10 +805,10 @@ bool EmitterIA32::emitBTRestores(baseTramp* bt,codeGen &gen) // restore saved FP state // fxrstor (%rsp) ; 0x0f 0xae 0x04 0x24 GET_PTR(insn, gen); - *insn++ = 0x0f; - *insn++ = 0xae; - *insn++ = 0x0c; - *insn++ = 0x24; + append_memory_as_byte(insn, 0x0f); + append_memory_as_byte(insn, 0xae); + append_memory_as_byte(insn, 0x0c); + append_memory_as_byte(insn, 0x24); SET_PTR(insn, gen); } else @@ -918,15 +920,15 @@ void emitAddMem(Address addr, int imm, codeGen &gen) { GET_PTR(insn, gen); if (imm < 128 && imm > -127) { if (gen.rs()->getAddressWidth() == 8) - *insn++ = 0x48; // REX byte for a quad-add - *insn++ = 0x83; - *insn++ = 0x04; - *insn++ = 0x25; + append_memory_as_byte(insn, 0x48); // REX byte for a quad-add + append_memory_as_byte(insn, 0x83); + append_memory_as_byte(insn, 0x04); + append_memory_as_byte(insn, 0x25); - *((int *)insn) = addr; //Write address - insn += sizeof(int); + assert(addr <= numeric_limits::max() && "addr more than 32-bits"); + append_memory_as(insn, static_cast(addr)); //Write address - *insn++ = (char) imm; + append_memory_as(insn, static_cast(imm)); SET_PTR(insn, gen); return; } @@ -934,28 +936,27 @@ void emitAddMem(Address addr, int imm, codeGen &gen) { if (imm == 1) { if (gen.rs()->getAddressWidth() == 4) { - *insn++ = 0xFF; //incl - *insn++ = 0x05; + append_memory_as_byte(insn, 0xFF); //incl + append_memory_as_byte(insn, 0x05); } else { assert(gen.rs()->getAddressWidth() == 8); - *insn++ = 0xFF; //inlc with SIB - *insn++ = 0x04; - *insn++ = 0x25; + append_memory_as_byte(insn, 0xFF); //inlc with SIB + append_memory_as_byte(insn, 0x04); + append_memory_as_byte(insn, 0x25); } } else { - *insn++ = 0x81; //addl - *insn++ = 0x4; - *insn++ = 0x25; + append_memory_as_byte(insn, 0x81); //addl + append_memory_as_byte(insn, 0x4); + append_memory_as_byte(insn, 0x25); } - *((int *)insn) = addr; //Write address - insn += sizeof(int); + assert(addr <= numeric_limits::max() && "addr more than 32-bits"); + append_memory_as(insn, static_cast(addr)); //Write address if (imm != 1) { - *((int*)insn) = imm; //Write immediate value to add - insn += sizeof(int); + append_memory_as(insn, int32_t{imm}); //Write immediate value to add } SET_PTR(insn, gen); @@ -975,9 +976,8 @@ void emitMovImmToReg64(Register dest, long imm, bool is_64, codeGen &gen) emitRex(is_64, NULL, NULL, &tmp_dest, gen); if (is_64) { GET_PTR(insn, gen); - *insn++ = static_cast(0xB8 + tmp_dest); - *((long *)insn) = imm; - insn += sizeof(long); + append_memory_as_byte(insn, 0xB8 + tmp_dest); + append_memory_as(insn, int64_t{imm}); SET_PTR(insn, gen); } else @@ -1039,17 +1039,16 @@ void emitMovPCRMToReg64(Register dest, int offset, int size, codeGen &gen, bool { GET_PTR(insn, gen); if (size == 8) - *insn++ = static_cast((dest & 0x8)>>1 | 0x48); // REX prefix + append_memory_as_byte(insn, (dest & 0x8)>>1 | 0x48); // REX prefix else { - *insn++ = static_cast((dest & 0x8)>>1 | 0x40); // REX prefix + append_memory_as_byte(insn, (dest & 0x8)>>1 | 0x40); // REX prefix } if (deref_result) - *insn++ = 0x8B; // MOV instruction + append_memory_as_byte(insn, 0x8B); // MOV instruction else - *insn++ = 0x8D; // LEA instruction - *insn++ = static_cast(((dest & 0x7) << 3) | 0x5); // ModRM byte - *((int *)insn) = offset-7; // offset - insn += sizeof(int); + append_memory_as_byte(insn, 0x8D); // LEA instruction + append_memory_as_byte(insn, ((dest & 0x7) << 3) | 0x5); // ModRM byte + append_memory_as(insn, int32_t{offset - 7}); // offset gen.markRegDefined(dest); SET_PTR(insn, gen); } @@ -1064,11 +1063,11 @@ static void emitMovRMToReg64(Register dest, Register base, int disp, int size, c { emitRex(true, &tmp_dest, NULL, &tmp_base, gen); GET_PTR(insn, gen); - *insn++ = 0x0f; + append_memory_as_byte(insn, 0x0f); if (size == 1) - *insn++ = 0xb6; + append_memory_as_byte(insn, 0xb6); else if (size == 2) - *insn++ = 0xb7; + append_memory_as_byte(insn, 0xb7); SET_PTR(insn, gen); emitAddressingMode(tmp_base, 0, tmp_dest, gen); } @@ -1112,9 +1111,9 @@ static void emitMovRegToRM64(Register base, int disp, Register src, int size, co emitRex(false, NULL, NULL, &tmp_base, gen); GET_PTR(insn, gen); if (size == 1) - *insn++ = 0x88; + append_memory_as_byte(insn, 0x88); else if (size == 2) - *insn++ = 0x89; + append_memory_as_byte(insn, 0x89); SET_PTR(insn, gen); emitAddressingMode(tmp_base, 0, REGNUM_RAX, gen); } @@ -1151,10 +1150,9 @@ void emitOpRegImm64(unsigned opcode, unsigned opcode_ext, Register rm_reg, int i emitRex(is_64, NULL, NULL, &tmp_rm_reg, gen); GET_PTR(insn, gen); - *insn++ = opcode; - *insn++ = 0xC0 | ((opcode_ext & 0x7) << 3) | tmp_rm_reg; - *((int *)insn) = imm; - insn+= sizeof(int); + append_memory_as_byte(insn, opcode); + append_memory_as_byte(insn, 0xC0 | ((opcode_ext & 0x7) << 3) | tmp_rm_reg); + append_memory_as(insn, int32_t{imm}); SET_PTR(insn, gen); gen.markRegDefined(rm_reg); } @@ -1168,10 +1166,9 @@ static void emitOpMemImm64(unsigned opcode, unsigned opcode_ext, Register base, emitRex(is_64, NULL, NULL, &tmp_base, gen); GET_PTR(insn, gen); - *insn++ = opcode; - *insn++ = ((opcode_ext & 0x7) << 3) | tmp_base; - *((int *)insn) = imm; - insn+= sizeof(int); + append_memory_as_byte(insn, opcode); + append_memory_as_byte(insn, ((opcode_ext & 0x7) << 3) | tmp_base); + append_memory_as(insn, int32_t{imm}); SET_PTR(insn, gen); } @@ -1180,8 +1177,7 @@ static void emitOpRegRegImm64(unsigned opcode, Register dest, Register src1, int { emitOpRegReg64(opcode, dest, src1, is_64, gen); GET_PTR(insn, gen); - *((int *)insn) = imm; - insn+= sizeof(int); + append_memory_as(insn, int32_t{imm}); SET_PTR(insn, gen); gen.markRegDefined(dest); } @@ -1192,9 +1188,9 @@ static void emitOpRegImm8_64(unsigned opcode, unsigned opcode_ext, Register dest Register tmp_dest = dest; emitRex(is_64, NULL, NULL, &tmp_dest, gen); GET_PTR(insn, gen); - *insn++ = opcode; - *insn++ = 0xC0 | ((opcode_ext & 0x7) << 3) | tmp_dest; - *insn++ = imm; + append_memory_as_byte(insn, opcode); + append_memory_as_byte(insn, 0xC0 | ((opcode_ext & 0x7) << 3) | tmp_dest); + append_memory_as_byte(insn, imm); SET_PTR(insn, gen); gen.markRegDefined(dest); } @@ -1218,21 +1214,19 @@ void emitMovImmToRM64(Register base, int disp, int imm, bool is_64, { GET_PTR(insn, gen); if (base == Null_Register) { - *insn++ = 0xC7; - *insn++ = 0x84; - *insn++ = 0x25; - *((int*)insn) = disp; - insn += sizeof(int); + append_memory_as_byte(insn, 0xC7); + append_memory_as_byte(insn, 0x84); + append_memory_as_byte(insn, 0x25); + append_memory_as(insn, int32_t{disp}); } else { emitRex(is_64, &base, NULL, NULL, gen); - *insn++ = 0xC7; + append_memory_as_byte(insn, 0xC7); SET_PTR(insn, gen); emitAddressingMode(base, disp, 0, gen); REGET_PTR(insn, gen); } - *((int*)insn) = imm; - insn += sizeof(int); + append_memory_as(insn, int32_t{imm}); SET_PTR(insn, gen); } @@ -1241,8 +1235,8 @@ void emitAddRM64(Register dest, int imm, bool is_64, codeGen &gen) if (imm == 1) { emitRex(is_64, &dest, NULL, NULL, gen); GET_PTR(insn, gen); - *insn++ = 0xFF; - *insn++ = dest & 0x7; + append_memory_as_byte(insn, 0xFF); + append_memory_as_byte(insn, dest & 0x7); SET_PTR(insn, gen); return; } @@ -1290,14 +1284,13 @@ codeBufIndex_t EmitterAMD64::emitIf(Register expr_reg, Register target, RegContr // Jump displacements are from the end of the insn, not start. The // one we're emitting has a size of 6. - int disp = target - 6; + int32_t disp = target - 6; // je target GET_PTR(insn, gen); - *insn++ = 0x0F; - *insn++ = 0x84; - *((int *)insn) = disp; - insn += sizeof(int); + append_memory_as_byte(insn, 0x0F); + append_memory_as_byte(insn, 0x84); + append_memory_as(insn, int32_t{disp}); SET_PTR(insn, gen); return retval; @@ -1335,7 +1328,7 @@ void EmitterAMD64::emitRelOp(unsigned op, Register dest, Register src1, Register // jcc by two or three, depdending on size of mov unsigned char jcc_opcode = jccOpcodeFromRelOp(op, s); GET_PTR(insn, gen); - *insn++ = jcc_opcode; + append_memory_as_byte(insn, jcc_opcode); SET_PTR(insn, gen); codeBufIndex_t jcc_disp = gen.used(); @@ -1348,10 +1341,10 @@ void EmitterAMD64::emitRelOp(unsigned op, Register dest, Register src1, Register gen.setIndex(jcc_disp); REGET_PTR(insn, gen); - *insn = (char) codeGen::getDisplacement(after_jcc, after_mov); + append_memory_as_byte(insn, codeGen::getDisplacement(after_jcc, after_mov)); SET_PTR(insn, gen); - gen.setIndex(after_mov); + gen.setIndex(after_mov); // overrides previous SET_PTR } void EmitterAMD64::emitRelOpImm(unsigned op, Register dest, Register src1, RegValue src2imm, @@ -1379,7 +1372,7 @@ void EmitterAMD64::emitRelOpImm(unsigned op, Register dest, Register src1, RegVa // jcc by two or three, depdending on size of mov unsigned char opcode = jccOpcodeFromRelOp(op, s); GET_PTR(insn, gen); - *insn++ = opcode; + append_memory_as_byte(insn, opcode); SET_PTR(insn, gen); codeBufIndex_t jcc_disp = gen.used(); gen.fill(1, codeGen::cgNOP); @@ -1391,10 +1384,10 @@ void EmitterAMD64::emitRelOpImm(unsigned op, Register dest, Register src1, RegVa gen.setIndex(jcc_disp); REGET_PTR(insn, gen); - *insn = (char) codeGen::getDisplacement(after_jcc, after_mov); - + append_memory_as_byte(insn, codeGen::getDisplacement(after_jcc, after_mov)); SET_PTR(insn, gen); - gen.setIndex(after_mov); + + gen.setIndex(after_mov); // overrides previous SET_PTR } void EmitterAMD64::emitDiv(Register dest, Register src1, Register src2, codeGen &gen, bool s) @@ -1868,14 +1861,14 @@ Register EmitterAMD64::emitCall(opCode op, codeGen &gen, const std::vector= 0; u--) { Address unused = ADDR_NULL; - unsigned reg = REG_NULL; + unsigned reg = Null_Register; if(u >= (int)AMD64_ARG_REGS) { if (!operands[u]->generateCode_phase2(gen, noCost, unused, reg)) assert(0); - assert(reg != REG_NULL); + assert(reg != Null_Register); emitPushReg64(reg, gen); gen.rs()->freeRegister(reg); frame_size++; @@ -1906,7 +1899,7 @@ Register EmitterAMD64::emitCall(opCode op, codeGen &gen, const std::vectorincStack(-alignment); } - if (!inInstrumentation) return REG_NULL; + if (!inInstrumentation) return Null_Register; // We now have a bit of an ordering problem. // The RS thinks all registers are free; this is not the case @@ -1995,8 +1988,8 @@ bool EmitterAMD64Dyn::emitCallInstruction(codeGen &gen, func_instance *callee, R emitRex(false, NULL, NULL, &effective, gen); } GET_PTR(insn, gen); - *insn++ = 0xFF; - *insn++ = static_cast(0xD0 | effective); + append_memory_as_byte(insn, 0xFF); + append_memory_as_byte(insn, static_cast(0xD0 | effective)); SET_PTR(insn, gen); return true; @@ -2033,12 +2026,13 @@ bool EmitterAMD64Stat::emitPLTJump(func_instance *callee, codeGen &gen) { // create or retrieve jump slot Address dest = getInterModuleFuncAddr(callee, gen); GET_PTR(insn, gen); - *insn++ = 0xFF; + append_memory_as_byte(insn, 0xFF); // Note: this is a combination of 00 (MOD), 100 (opcode extension), and 101 // (disp32) - *insn++ = 0x25; - *(unsigned int*)insn = dest - (gen.currAddr() + sizeof(unsigned int) + 2); - insn += sizeof(unsigned int); + append_memory_as_byte(insn, 0x25); + int64_t offset = dest - (gen.currAddr() + sizeof(int32_t) + 2); + assert(numeric_limits::lowest() <= offset && offset <= numeric_limits::max() && "offset more than 32 bits"); + append_memory_as(insn, static_cast(offset)); SET_PTR(insn, gen); return true; } @@ -2047,10 +2041,11 @@ bool EmitterAMD64Stat::emitPLTCall(func_instance *callee, codeGen &gen) { // create or retrieve jump slot Address dest = getInterModuleFuncAddr(callee, gen); GET_PTR(insn, gen); - *insn++ = 0xFF; - *insn++ = 0x15; - *(unsigned int*)insn = dest - (gen.currAddr() + sizeof(unsigned int) + 2); - insn += sizeof(unsigned int); + append_memory_as_byte(insn, 0xFF); + append_memory_as_byte(insn, 0x15); + int64_t offset = dest - (gen.currAddr() + sizeof(int32_t) + 2); + assert(numeric_limits::lowest() <= offset && offset <= numeric_limits::max() && "offset more than 32 bits"); + append_memory_as(insn, static_cast(offset)); SET_PTR(insn, gen); return true; } @@ -2071,14 +2066,14 @@ void EmitterAMD64::emitGetRetVal(Register dest, bool addr_of, codeGen &gen) registerSlot *rax = (*gen.rs())[REGNUM_RAX]; assert(rax); loc.offset += (rax->saveOffset * 8); - emitLEA(loc.reg.reg(), REG_NULL, 0, loc.offset, dest, gen); + emitLEA(loc.reg.reg(), Null_Register, 0, loc.offset, dest, gen); } void EmitterAMD64::emitGetRetAddr(Register dest, codeGen &gen) { stackItemLocation loc = getHeightOf(stackItem::stacktop, gen); - emitLEA(loc.reg.reg(), REG_NULL, 0, loc.offset, dest, gen); + emitLEA(loc.reg.reg(), Null_Register, 0, loc.offset, dest, gen); } @@ -2096,7 +2091,7 @@ void EmitterAMD64::emitGetParam(Register dest, Register param_num, instPoint::Ty registerSlot *regSlot = (*gen.rs())[reg]; assert(regSlot); loc.offset += (regSlot->saveOffset * 8); - emitLEA(loc.reg.reg(), REG_NULL, 0, loc.offset, dest, gen); + emitLEA(loc.reg.reg(), Null_Register, 0, loc.offset, dest, gen); return; } assert(param_num >= 6); @@ -2139,10 +2134,10 @@ static void emitPushImm16_64(unsigned short imm, codeGen &gen) GET_PTR(insn, gen); // operand-size prefix - *insn++ = 0x66; + append_memory_as_byte(insn, 0x66); // PUSH imm opcode - *insn++ = 0x68; + append_memory_as_byte(insn, 0x68); // and the immediate *(unsigned short*)insn = imm; @@ -2371,15 +2366,10 @@ bool shouldSaveReg(registerSlot *reg, baseTramp *inst, bool saveFlags) if (saveFlags) { // Saving flags takes up EAX/RAX, and so if they're live they must // be saved even if we don't explicitly use them -#if !defined(__GNUC__) || __GNUC__ >= 10 + DYNINST_DIAGNOSTIC_BEGIN_SUPPRESS_LOGICAL_OP if (reg->number == REGNUM_EAX || reg->number == REGNUM_RAX) return true; -#else - // eliminate warning with gcc < 10 about duplicate logical or clauses - // since REGNUM_EAX is a macro that with value 0 and REGNUM_RAX is an - // enum that has a value 0 - if (reg->number == REGNUM_EAX) return true; -#endif + DYNINST_DIAGNOSTIC_END_SUPPRESS_LOGICAL_OP } if (inst && inst->validOptimizationInfo() && !inst->definedRegs[reg->encoding()]) { regalloc_printf("\t Base tramp instance doesn't have reg %u (num %u) defined; concluding don't save\n", @@ -3117,12 +3107,12 @@ bool EmitterIA32::emitXorRegSegReg(Register /*dest*/, Register base, int disp, c // WARNING: dest is hard-coded to EDX currently emitSegPrefix(base, gen); GET_PTR(insn, gen); - *insn++ = 0x33; - *insn++ = 0x15; - *insn++ = disp; - *insn++ = 0x00; - *insn++ = 0x00; - *insn++ = 0x00; + append_memory_as_byte(insn, 0x33); + append_memory_as_byte(insn, 0x15); + append_memory_as_byte(insn, disp); + append_memory_as_byte(insn, 0x00); + append_memory_as_byte(insn, 0x00); + append_memory_as_byte(insn, 0x00); SET_PTR(insn, gen); return true; } diff --git a/dyninstAPI/src/emit-x86.h b/dyninstAPI/src/emit-x86.h index 08d67cf763..6d3db1a719 100644 --- a/dyninstAPI/src/emit-x86.h +++ b/dyninstAPI/src/emit-x86.h @@ -36,6 +36,8 @@ #ifndef _EMIT_X86_H #define _EMIT_X86_H +#include +#include #include "common/src/headers.h" #include "common/src/arch.h" #include "dyninstAPI/src/instPoint.h" diff --git a/dyninstAPI/src/emitter.h b/dyninstAPI/src/emitter.h index b02456f3aa..26a4751076 100644 --- a/dyninstAPI/src/emitter.h +++ b/dyninstAPI/src/emitter.h @@ -36,6 +36,8 @@ #ifndef _EMITTER_H #define _EMITTER_H +#include +#include #include "common/src/headers.h" #include "dyninstAPI/src/instPoint.h" #include "dyninstAPI/src/baseTramp.h" diff --git a/dyninstAPI/src/frame.h b/dyninstAPI/src/frame.h index 6f29e8ecde..6948cceacd 100644 --- a/dyninstAPI/src/frame.h +++ b/dyninstAPI/src/frame.h @@ -33,8 +33,8 @@ #ifndef FRAME_H #define FRAME_H -#include "common/src/std_namesp.h" -#include "common/src/Types.h" +#include +#include #include "instPoint.h" #include "baseTramp.h" @@ -48,14 +48,6 @@ class PCProcess; class Frame { public: - typedef enum { unset, - instrumentation, - signalhandler, - normal, - syscall, - iRPC, - unknown } frameType_t; - // default ctor (zero frame) Frame(); @@ -79,7 +71,7 @@ class Frame { return *this; } - bool operator==(const Frame &F) { + bool operator==(const Frame &F) const { return ((uppermost_ == F.uppermost_) && (sw_frame_ == F.sw_frame_) && (proc_ == F.proc_) && diff --git a/dyninstAPI/src/frameChecker.C b/dyninstAPI/src/frameChecker.C index 488f428560..2788f6e571 100644 --- a/dyninstAPI/src/frameChecker.C +++ b/dyninstAPI/src/frameChecker.C @@ -30,7 +30,8 @@ #include "frameChecker.h" #include "instructionAPI/h/InstructionDecoder.h" -#include "dyn_regs.h" +#include "Architecture.h" +#include "registers/MachRegister.h" using namespace Dyninst; diff --git a/dyninstAPI/src/frameChecker.h b/dyninstAPI/src/frameChecker.h index 31a55776db..8acd584f36 100644 --- a/dyninstAPI/src/frameChecker.h +++ b/dyninstAPI/src/frameChecker.h @@ -31,6 +31,8 @@ #if !defined(FRAMECHECKER_H) #define FRAMECHECKER_H +#include +#include #include "instructionAPI/h/Instruction.h" class frameChecker diff --git a/dyninstAPI/src/freebsd.C b/dyninstAPI/src/freebsd.C index 8aaae37eb8..ec8c194214 100644 --- a/dyninstAPI/src/freebsd.C +++ b/dyninstAPI/src/freebsd.C @@ -28,6 +28,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include #include #include diff --git a/dyninstAPI/src/freebsd.h b/dyninstAPI/src/freebsd.h index 236a49098a..48c687b9a7 100644 --- a/dyninstAPI/src/freebsd.h +++ b/dyninstAPI/src/freebsd.h @@ -35,7 +35,6 @@ #ifndef FREEBSD_PD_HDR #define FREEBSD_PD_HDR -#include "common/src/Types.h" #include "common/src/freebsdKludges.h" #include "symtabAPI/h/Symtab.h" #include "symtabAPI/h/Archive.h" diff --git a/dyninstAPI/src/function.C b/dyninstAPI/src/function.C index c224afaf3b..1756148954 100644 --- a/dyninstAPI/src/function.C +++ b/dyninstAPI/src/function.C @@ -30,6 +30,8 @@ // $Id: function.C,v 1.10 2005/03/02 19:44:45 bernat Exp +#include +#include #include "function.h" #include "instPoint.h" #include "debug.h" @@ -38,7 +40,6 @@ #include "mapped_object.h" #include "mapped_module.h" #include "InstructionDecoder.h" -#include "MemoryEmulator/memEmulator.h" #include "Relocation/Transformers/Movement-analysis.h" #include "PatchMgr.h" // Scope @@ -181,8 +182,8 @@ block_instance * func_instance::setNewEntry(block_instance *def, ParseAPI::Intraproc epred; const Block::edgelist & ib_ins = block->llb()->sources(); - if(std::distance(boost::make_filter_iterator(epred, ib_ins.begin(), ib_ins.end()), - boost::make_filter_iterator(epred, ib_ins.end(), ib_ins.end())) == 0) + if(std::distance(dyncompat::make_filter_iterator(epred, ib_ins.begin(), ib_ins.end()), + dyncompat::make_filter_iterator(epred, ib_ins.end(), ib_ins.end())) == 0) { if (NULL != newEntry) { fprintf(stderr,"WARNING: multiple blocks in function %lx " @@ -1077,8 +1078,6 @@ bool func_instance::createOffsetVector() return ret; } -static int randomNumGenerator (int i) { return std::rand()%i; } - static bool matchRanges(ValidPCRange* a, ValidPCRange* b) { auto aIter = a->begin(); @@ -1144,7 +1143,7 @@ bool func_instance::randomize(TMap* tMap, bool seeded, int seed) (curLoc->off() < raLoc) && (curLoc->off()+curLoc->size() < raLoc) && /* Skip non-debug */ - ((curLoc->type() != StackAccess::DEBUGINFO_LOCAL) && (curLoc->type() != StackAccess::DEBUGINFO_PARAM))) { + ((curLoc->type() != StackAccess::StackAccessType::DEBUGINFO_LOCAL) && (curLoc->type() != StackAccess::StackAccessType::DEBUGINFO_PARAM))) { ++iter; if (iter == stack.end()) { break; @@ -1163,7 +1162,7 @@ bool func_instance::randomize(TMap* tMap, bool seeded, int seed) break; } - if ((curLoc->type() != StackAccess::DEBUGINFO_LOCAL) && (curLoc->type() != StackAccess::DEBUGINFO_PARAM)) { + if ((curLoc->type() != StackAccess::StackAccessType::DEBUGINFO_LOCAL) && (curLoc->type() != StackAccess::StackAccessType::DEBUGINFO_PARAM)) { break; } @@ -1211,7 +1210,9 @@ bool func_instance::randomize(TMap* tMap, bool seeded, int seed) } randomizedRange = true; - std::random_shuffle(vec.begin(), vec.end(), randomNumGenerator); + std::random_device rd; + std::mt19937 urbg{rd()}; + std::shuffle(vec.begin(), vec.end(), urbg); StackAnalysis::Height nextLoc = (*iter).first.height(); for (auto viter = vec.begin(); viter != vec.end(); ++viter) { @@ -1247,15 +1248,7 @@ bool func_instance::createOffsetVector_Symbols() _hasDebugSymbols = true; // Calculate base pointer height for locals; the frame offset is relative to this - int width; Architecture arch = ifunc()->isrc()->getArch(); - if (arch == Arch_x86) { width = 4; } - else if (arch == Arch_x86_64) { width = 8; } - else { assert(0); } - int base = -width; - if (!ifunc()->hasNoStackFrame()) { - base -= width; // account for BP save - } for (auto vIter = _vars.begin(); vIter != _vars.end(); ++vIter) { SymtabAPI::localVar* var = *vIter; @@ -1291,7 +1284,7 @@ bool func_instance::createOffsetVector_Symbols() } } - StackAccess::StackAccessType sat = StackAccess::DEBUGINFO_LOCAL; + StackAccess::StackAccessType sat = StackAccess::StackAccessType::DEBUGINFO_LOCAL; if (var->getType(Type::share)->getSize() == 0) { _tmpObjects->insert(tmpObject(offset, 4, sat, valid)); } else { @@ -1334,7 +1327,7 @@ bool func_instance::createOffsetVector_Symbols() } } - StackAccess::StackAccessType sat = StackAccess::DEBUGINFO_PARAM; + StackAccess::StackAccessType sat = StackAccess::StackAccessType::DEBUGINFO_PARAM; if (var->getType(Type::share)->getSize() == 0) { _tmpObjects->insert(tmpObject(offset, 4, sat, valid)); } else { @@ -1384,7 +1377,7 @@ bool func_instance::createOffsetVector_Analysis(ParseAPI::Function *func, assert(!access->skipReg()); if (!addToOffsetVector(access->regHeight(), 1, - StackAccess::REGHEIGHT, true, NULL, access->reg())) { + StackAccess::StackAccessType::REGHEIGHT, true, NULL, access->reg())) { stackmods_printf("\t\t\t INVALID: addToOffsetVector " "failed\n"); return false; @@ -1451,7 +1444,7 @@ bool func_instance::addToOffsetVector(StackAnalysis::Height off, int size, Stack if (isDebugType(type)) { // Silently skip; doesn't hurt--if there's an actual access, the others will catch it. // Okay to skip here because getAccesses won't return this one because it came from the DWARF. - type = StackAccess::MISUNDERSTOOD; + type = StackAccess::StackAccessType::MISUNDERSTOOD; } else { return false; } @@ -1497,12 +1490,12 @@ bool func_instance::addToOffsetVector(StackAnalysis::Height off, int size, Stack break; } else { // We know the new one overlaps with existing - existing->setType(StackAccess::MISUNDERSTOOD); + existing->setType(StackAccess::StackAccessType::MISUNDERSTOOD); // But, it also overlaps with existing2 - existing2->setType(StackAccess::MISUNDERSTOOD); + existing2->setType(StackAccess::StackAccessType::MISUNDERSTOOD); - StackLocation* tmp = new StackLocation(off, size, StackAccess::MISUNDERSTOOD, isRegisterHeight, valid); + StackLocation* tmp = new StackLocation(off, size, StackAccess::StackAccessType::MISUNDERSTOOD, isRegisterHeight, valid); assert(tmp); _offVec->insert(off, off+size, tmp, isRegisterHeight); } @@ -1540,16 +1533,16 @@ bool func_instance::addToOffsetVector(StackAnalysis::Height off, int size, Stack if (_offVec->find(off+i, lb2, ub2, existing2)) { if (existing2 != existing) { stackmods_printf("\t\t\t\t\t\t Range overlaps with another existing range %s\n", existing2->format().c_str()); - existing2->setType(StackAccess::MISUNDERSTOOD); + existing2->setType(StackAccess::StackAccessType::MISUNDERSTOOD); } } } // We know we're in conflict with the existing range, since lb != off - existing->setType(StackAccess::MISUNDERSTOOD); + existing->setType(StackAccess::StackAccessType::MISUNDERSTOOD); // Add new range as misunderstood - StackLocation* tmp = new StackLocation(off, size, StackAccess::MISUNDERSTOOD, isRegisterHeight, valid); + StackLocation* tmp = new StackLocation(off, size, StackAccess::StackAccessType::MISUNDERSTOOD, isRegisterHeight, valid); assert(tmp); _offVec->insert(off, off+size, tmp, isRegisterHeight); } @@ -1681,7 +1674,7 @@ void func_instance::createTMap_internal(StackMod* mod, TMap* tMap) StackAnalysis::Height c(insertMod->low()); StackAnalysis::Height d(insertMod->high()); StackLocation* tmpSrc = new StackLocation(); - StackLocation* tmpDest = new StackLocation(c, (d-c).height(), StackAccess::UNKNOWN, false); + StackLocation* tmpDest = new StackLocation(c, (d-c).height(), StackAccess::StackAccessType::UNKNOWN, false); tMap->insert(make_pair(tmpSrc, tmpDest)); stackmods_printf("\t\t\t Adding to tMap: %s -> %s\n", tmpSrc->format().c_str(), tmpDest->format().c_str()); } @@ -1703,6 +1696,8 @@ void func_instance::createTMap_internal(StackMod* mod, TMap* tMap) } } +namespace +{ AnnotationClass Stack_Anno_Intervals(std::string("Stack_Anno_Intervals"), NULL); AnnotationClass @@ -1711,6 +1706,7 @@ AnnotationClass Stack_Anno_Insn_Effects(std::string("Stack_Anno_Insn_Effects"), NULL); AnnotationClass Stack_Anno_Call_Effects(std::string("Stack_Anno_Call_Effects"), NULL); +} void func_instance::freeStackMod() { // Free stack analysis intervals StackAnalysis::Intervals *i = NULL; diff --git a/dyninstAPI/src/function.h b/dyninstAPI/src/function.h index a500253c4e..0188999eca 100644 --- a/dyninstAPI/src/function.h +++ b/dyninstAPI/src/function.h @@ -34,8 +34,11 @@ #define FUNCTION_H #include -#include "common/src/Types.h" -#include "common/src/Pair.h" +#include +#include +#include +#include +#include #include "codegen.h" #include "codeRange.h" #include "util.h" diff --git a/dyninstAPI/src/hybridAnalysis.h b/dyninstAPI/src/hybridAnalysis.h index 5f570ab53d..770d672c93 100644 --- a/dyninstAPI/src/hybridAnalysis.h +++ b/dyninstAPI/src/hybridAnalysis.h @@ -32,6 +32,8 @@ #define _HYBRIDANALYSIS_H_ #include +#include +#include #include #include #include diff --git a/dyninstAPI/src/hybridCallbacks.C b/dyninstAPI/src/hybridCallbacks.C index cda52f88ed..87f34d6855 100644 --- a/dyninstAPI/src/hybridCallbacks.C +++ b/dyninstAPI/src/hybridCallbacks.C @@ -28,6 +28,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include "hybridAnalysis.h" #include "debug.h" #include "BPatch_point.h" @@ -37,7 +38,6 @@ #include "instPoint.h" #include "function.h" #include "dynProcess.h" -#include "MemoryEmulator/memEmulator.h" #include "PatchModifier.h" #include "BPatch_image.h" #include "mapped_object.h" @@ -56,11 +56,6 @@ void HybridAnalysis::synchShadowOrigCB(BPatch_point *point, bool toOrig) mal_printf("in synch callback for point 0x%lx toOrig=%d\n", (Address)point->getAddress(), (int) (long) toOrig); - - proc()->lowlevel_process()->getMemEm()->synchShadowOrig - ((bool) toOrig); - - std::vector *mods = proc()->getImage()->getModules(); // fix up page rights so that the program can proceed @@ -369,8 +364,6 @@ void HybridAnalysis::virtualFreeCB(BPatch_point *, void *t) { if (!bpfunc) continue; PatchAPI::PatchModifier::remove(bpfunc->lowlevel_func()); } - - proc()->lowlevel_process()->getMemEm()->removeRegion(virtualFreeAddr_, virtualFreeSize_); // And nuke the RT cache proc()->lowlevel_process()->proc()->flushAddressCache_RT(virtualFreeAddr_, virtualFreeSize_); diff --git a/dyninstAPI/src/hybridInstrumentation.C b/dyninstAPI/src/hybridInstrumentation.C index 446ac589ce..1424ab6784 100644 --- a/dyninstAPI/src/hybridInstrumentation.C +++ b/dyninstAPI/src/hybridInstrumentation.C @@ -28,6 +28,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include "hybridAnalysis.h" #include "BPatch.h" #include "BPatch_process.h" @@ -41,7 +42,6 @@ #include "debug.h" #include "dynProcess.h" #include "mapped_object.h" -#include "MemoryEmulator/memEmulator.h" #include "mapped_module.h" #include #include @@ -153,44 +153,6 @@ bool HybridAnalysis::init() proc()->finalizeInsertionSet(false); // Done instrumenting VirtualFree - - if (proc()->lowlevel_process()->isMemoryEmulated()) { - // read in the list of whitelisted Windows API functions (those that - // don't use pointers) so we save time by not to synchronizing around - // them - char *dyn_root = getenv("DYNINST_ROOT"); - if (!dyn_root) { - fprintf(stderr, "ERROR: DYNINST_ROOT environment variable was not " - "declared, couldn't find the list of non-pointer Windows API " - "functions, will synchronize memory at all inter-library calls" - " %s[%d]\n",FILE__,__LINE__); - } - else { - string fname = string(dyn_root) + "\\dyninst\\dyninstAPI\\nosynchfuncs.txt"; - ifstream nsf_file(fname.c_str()); - if ( ! nsf_file.is_open() ) { - fprintf(stderr, "ERROR: failed to open file %s, which should " - "contain the list of non-pointer Windows API functions, " - "will synchronize memory at all inter-library calls " - "%s[%d]\n",fname.c_str(),FILE__,__LINE__); - } - else { - std::string curfunc; - while (nsf_file.good()) { - getline(nsf_file, curfunc); - skipShadowFuncs_.insert(curfunc); - } - } - } - skipShadowFuncs_.insert("GetCurrentProcessId"); - skipShadowFuncs_.insert("VirtualAlloc"); - skipShadowFuncs_.insert("VirtualFree"); - skipShadowFuncs_.insert("GetCurrentThreadId"); - skipShadowFuncs_.insert("GetLocalTime"); - skipShadowFuncs_.insert("LocalAlloc"); - skipShadowFuncs_.insert("TlsAlloc"); - skipShadowFuncs_.insert("TlsSetValue"); - } #endif //mal_printf(" pre-inst "); proc()->printKTimer(); @@ -362,12 +324,6 @@ bool HybridAnalysis::instrumentFunction(BPatch_function *func, assert(proc()); assert(proc()->lowlevel_process()); - if (proc()->lowlevel_process()->isMemoryEmulated() && - BPatch_defensiveMode == func->lowlevel_func()->obj()->hybridMode()) - { // we have to relocate all functions to emulate their memory accesses - proc()->lowlevel_process()->addModifiedFunction(func->lowlevel_func()); - } - if (instrumentedFuncs->end() == instrumentedFuncs->find(func)) { (*instrumentedFuncs)[func] = new std::map(); @@ -634,7 +590,7 @@ bool HybridAnalysis::instrumentFunction(BPatch_function *func, } // close insertion set - if (proc()->lowlevel_process()->isMemoryEmulated() || pointCount) { + if (pointCount) { mal_printf("instrumented %d points in function at %p\n", pointCount, func->getBaseAddr()); if (useInsertionSet) { @@ -682,40 +638,6 @@ void HybridAnalysis::removeInstrumentation(BPatch_function *func, // 1. Remove elements from instrumentedFuncs if (instrumentedFuncs->end() != instrumentedFuncs->find(func)) { - if (proc()->lowlevel_process()->isMemoryEmulated()) { - map::iterator - pit = (*instrumentedFuncs)[func]->begin(); - for (; pit != (*instrumentedFuncs)[func]->end(); pit++) { - if (synchMap_pre_.end() != synchMap_pre_.find(pit->first)) - { - SynchHandle *shandle = synchMap_pre_[pit->first]; - // Note: the points in this snippet handle may have been deleted, and thus - // should not be dereferenced; use them only as key values in maps. - - synchMap_pre_.erase(shandle->prePt_); - /* - // Don't remove an instrumentation point that we haven't specifically found; - // it might be in a different function. - synchMap_post_.erase(shandle->postPt_); - */ - delete shandle; - } - else if (synchMap_post_.end() != synchMap_post_.find(pit->first)) - { - SynchHandle *shandle = synchMap_post_[pit->first]; - // Note: the points in this snippet handle may have been deleted, and thus - // should not be dereferenced; use them only as key values in maps. - - /* - // Do not remove an instrumentation point that we haven't specifically found; - // it might be in a different function. - synchMap_pre_.erase(shandle->prePt_); - */ - synchMap_post_.erase(shandle->postPt_); - delete shandle; - } - } - } (*instrumentedFuncs)[func]->clear(); delete (*instrumentedFuncs)[func]; instrumentedFuncs->erase(func); diff --git a/dyninstAPI/src/hybridOverwrites.C b/dyninstAPI/src/hybridOverwrites.C index 45cd5070f5..f85f003c85 100644 --- a/dyninstAPI/src/hybridOverwrites.C +++ b/dyninstAPI/src/hybridOverwrites.C @@ -28,6 +28,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include "hybridAnalysis.h" #include "BPatch_process.h" #include "BPatch_function.h" @@ -46,7 +47,6 @@ #include "instPoint.h" #include "mapped_object.h" #include "mapped_module.h" -#include "MemoryEmulator/memEmulator.h" using namespace Dyninst; @@ -1321,9 +1321,6 @@ void HybridAnalysisOW::overwriteAnalysis(BPatch_point *point, void *loopID_) proc()->finalizeInsertionSet(false); proc()->protectAnalyzedCode(); malware_cerr << "overWriteAnalysis returns" << endl; - - proc()->lowlevel_process()->getMemEm()->debug(); - } #endif diff --git a/dyninstAPI/src/image.C b/dyninstAPI/src/image.C index 3d108cede0..aeed7c37b4 100644 --- a/dyninstAPI/src/image.C +++ b/dyninstAPI/src/image.C @@ -28,6 +28,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include #include #include @@ -102,7 +103,7 @@ char main_function_names[NUMBER_OF_MAIN_POSSIBILITIES][20] = { fileDescriptor::fileDescriptor(): code_(0), data_(0), - pid_(0), length_(0), rawPtr_(NULL) + pid_(0), length_(0) { // This shouldn't be called... must be public for std::vector, though } @@ -172,7 +173,7 @@ extern unsigned enable_pd_sharedobj_debug; int codeBytesSeen = 0; -#if defined(ppc32_linux) || defined(ppc64_linux) +#if defined(ppc64_linux) #include #include @@ -475,7 +476,7 @@ class FindMainVisitor : public ASTVisitor */ int image::findMain() { -#if defined(ppc32_linux) || defined(ppc64_linux) +#if defined(ppc64_linux) using namespace Dyninst::InstructionAPI; // Only look for main in executables, but do allow position-independent @@ -1030,10 +1031,6 @@ pdmodule *image::findModule(const string &name, bool wildcard) //cerr << " (image::findModule) found module in modsByFileName" << endl; found = modsByFileName[name]; } - else if (modsByFullName.find(name) != modsByFullName.end()) { - //cerr << " (image::findModule) found module in modsByFullName" << endl; - found = modsByFullName[name]; - } } else { // if we want a substring, have to iterate over all module names @@ -1047,8 +1044,7 @@ pdmodule *image::findModule(const string &name, bool wildcard) { str = mi->first; mod = mi->second; - if (wildcardEquiv(pds, mod->fileName()) || - wildcardEquiv(pds, mod->fullName())) { + if (wildcardEquiv(pds, mod->fileName())) { found = mod; break; } @@ -1515,7 +1511,7 @@ image::image(fileDescriptor &desc, interested **/ struct filt_heap : SymtabCodeSource::hint_filt { bool operator()(SymtabAPI::Function * f) { - return f && f->getModule() && f->getModule()->fullName() == "DYNINSTheap"; + return f && f->getModule() && f->getModule()->fileName() == "DYNINSTheap"; } } nuke_heap; filt = &nuke_heap; @@ -1702,10 +1698,9 @@ parse_func *image::addFunction(Address functionEntryAddr, const char *fName) } region = *(regions.begin()); // XXX pick one, throwing up hands. - std::set st_mod; - linkedFile->findModuleByOffset(st_mod, functionEntryAddr); + auto *m = linkedFile->getContainingModule(functionEntryAddr); - pdmodule *mod = getOrCreateModule(*(st_mod.begin())); + pdmodule *mod = getOrCreateModule(m); // copy or create function name char funcName[32]; @@ -1764,11 +1759,6 @@ const string &pdmodule::fileName() const return mod_->fileName(); } -const string &pdmodule::fullName() const -{ - return mod_->fullName(); -} - SymtabAPI::supportedLanguages pdmodule::language() const { @@ -1798,7 +1788,6 @@ pdmodule *image::getOrCreateModule(Module *mod) { mods_[mod] = pdmod; modsByFileName[pdmod->fileName()] = pdmod; - modsByFullName[pdmod->fullName()] = pdmod; return pdmod; } diff --git a/dyninstAPI/src/image.h b/dyninstAPI/src/image.h index 2c993093dd..fb235f0f9f 100644 --- a/dyninstAPI/src/image.h +++ b/dyninstAPI/src/image.h @@ -34,6 +34,9 @@ #define SYMTAB_HDR #define REGEX_CHARSET "^*|?" +#include +#include +#include #include #include #include @@ -45,7 +48,6 @@ #include -#include "dyninstAPI/src/dyninst.h" #include "dyninstAPI/src/util.h" #include "dyninstAPI/src/codeRange.h" #include "dyninstAPI/src/infHeap.h" @@ -53,7 +55,6 @@ #include "dyninstAPI/h/BPatch_enums.h" #include -#include "common/src/Types.h" #if defined(os_linux)||defined(os_freebsd) #include "symtabAPI/h/Archive.h" @@ -135,12 +136,12 @@ class fileDescriptor { code_(code), data_(data), pid_(0), - length_(0), - rawPtr_(NULL) {} + length_(0) + {} // ctor for non-files fileDescriptor(string file, Address code, Address data, - Address length, void* rawPtr) : + Address length, void* ) : #if defined(os_windows) procHandle_(INVALID_HANDLE_VALUE), fileHandle_(INVALID_HANDLE_VALUE), @@ -149,8 +150,8 @@ class fileDescriptor { code_(code), data_(data), pid_(0), - length_(length), - rawPtr_(rawPtr) {} + length_(length) + {} bool operator==(const fileDescriptor &fd) const { return IsEqual(fd ); @@ -207,7 +208,6 @@ class fileDescriptor { Address data_; int pid_; Address length_; // set only if this is not really a file - void* rawPtr_; // set only if this is not really a file bool IsEqual( const fileDescriptor &fd ) const; }; @@ -233,8 +233,8 @@ class image_variable { pdmodule *pdmod() const { return pdmod_; } SymtabAPI::Variable *svar() const { return var_; } - SymtabAPI::Variable *var_; - pdmodule *pdmod_; + SymtabAPI::Variable *var_{}; + pdmodule *pdmod_{}; }; @@ -422,7 +422,6 @@ class image : public codeRange { bool determineImageType(); bool addSymtabVariables(); - void getModuleLanguageInfo(std::unordered_map *mod_langs); void setModuleLanguages(std::unordered_map *mod_langs); // We have a _lot_ of lookup types; this handles proper entry @@ -488,14 +487,7 @@ class image : public codeRange { // unique (by image) numbering of basic blocks int nextBlockID_; - // TODO -- get rid of one of these - // Note : as of 971001 (mcheyney), these hash tables only - // hold entries in includedMods --> this implies that - // it may sometimes be necessary to do a linear sort - // through excludedMods if searching for a module which - // was excluded.... dyn_hash_map modsByFileName; - dyn_hash_map modsByFullName; // "Function" symbol names that are PLT entries or the equivalent // FIXME remove @@ -548,7 +540,6 @@ class pdmodule { std::vector &found); void dumpMangled(std::string &prefix) const; const string &fileName() const; - const string &fullName() const; SymtabAPI::supportedLanguages language() const; Address addr() const; bool isShared() const; diff --git a/dyninstAPI/src/infHeap.h b/dyninstAPI/src/infHeap.h index 62d17fa434..a951e1ff8c 100644 --- a/dyninstAPI/src/infHeap.h +++ b/dyninstAPI/src/infHeap.h @@ -38,7 +38,7 @@ #include #include #include -#include "common/src/Types.h" +#include "dyntypes.h" #include "common/h/util.h" #include "util.h" @@ -50,7 +50,7 @@ typedef enum { textHeap=0x01, anyHeap=0x7, // OR of the previous three lowmemHeap=0x1000 } inferiorHeapType; -typedef std::vector
addrVecType; +typedef std::vector addrVecType; class heapItem { public: @@ -59,7 +59,7 @@ class heapItem { type(anyHeap), dynamic(true), status(HEAPfree), buffer(NULL) {} - heapItem(Address a, int n, + heapItem(Dyninst::Address a, int n, inferiorHeapType t, bool d = true, heapStatus s = HEAPfree) : @@ -88,7 +88,7 @@ class heapItem { void setBuffer(void *b) { buffer = b; } - Address addr; + Dyninst::Address addr; unsigned length; inferiorHeapType type; bool dynamic; // part of a dynamically allocated segment? @@ -105,7 +105,7 @@ class heapItem { // (i.e. prior minitramp/basetramp code) class disabledItem { public: - disabledItem() : block() {} + disabledItem() noexcept : block() {} disabledItem(heapItem *h, const std::vector &preds) : block(h), pointsToCheck(preds) {} @@ -125,7 +125,7 @@ class disabledItem { heapItem block; // inferior heap block std::vector pointsToCheck; // list of addresses to check against PCs - Address getPointer() const {return block.addr;} + Dyninst::Address getPointer() const {return block.addr;} inferiorHeapType getHeapType() const {return block.type;} const std::vector &getPointsToCheck() const {return pointsToCheck;} std::vector &getPointsToCheck() {return pointsToCheck;} @@ -139,28 +139,19 @@ class disabledItem { class heapDescriptor { public: heapDescriptor(const std::string name, - Address addr, + Dyninst::Address addr, unsigned int size, const inferiorHeapType type): name_(name),addr_(addr),size_(size), type_(type) {} heapDescriptor(): - name_(std::string("")),addr_(0),size_(0),type_(anyHeap) {} - ~heapDescriptor() {} - heapDescriptor &operator=(const heapDescriptor& h) - { - name_ = h.name(); - addr_ = h.addr(); - size_ = h.size(); - type_ = h.type(); - return *this; - } + name_{},addr_{},size_{},type_(anyHeap) {} const std::string &name() const {return name_;} - const Address &addr() const {return addr_;} + const Dyninst::Address &addr() const {return addr_;} const unsigned &size() const {return size_;} const inferiorHeapType &type() const {return type_;} private: std::string name_; - Address addr_; + Dyninst::Address addr_; unsigned size_; inferiorHeapType type_; }; @@ -176,7 +167,7 @@ class inferiorHeap { inferiorHeap(const inferiorHeap &src); // create a new heap that is a copy // of src (used on fork) inferiorHeap& operator=(const inferiorHeap &src); - std::unordered_map heapActive; // active part of heap + std::unordered_map heapActive; // active part of heap std::vector heapFree; // free block of data inferior heap std::vector disabledList; // items waiting to be freed. int disabledListTotalMem; // total size of item waiting to free diff --git a/dyninstAPI/src/inst-aarch64.C b/dyninstAPI/src/inst-aarch64.C index 337a666b48..69004c0e28 100644 --- a/dyninstAPI/src/inst-aarch64.C +++ b/dyninstAPI/src/inst-aarch64.C @@ -56,8 +56,8 @@ #include "emitter.h" #include "emit-aarch64.h" -#include -using namespace boost::assign; +#include +using namespace dyncompat::assign; #include #include "dyninstAPI/h/BPatch_memoryAccess_NP.h" @@ -138,7 +138,7 @@ void registerSpace::initialize() { void EmitterAARCH64SaveRegs::saveSPR(codeGen &gen, Register scratchReg, int sprnum, int stkOffset) { - assert(scratchReg!=REG_NULL); + assert(scratchReg!=Null_Register); //TODO move map to common location map sysRegCodeMap = map_list_of(SPR_NZCV, 0x5A10)(SPR_FPCR, 0x5A20)(SPR_FPSR, 0x5A21); @@ -313,11 +313,12 @@ unsigned EmitterAARCH64RestoreRegs::restoreSPRegisters( std::vector spRegs; map regMap; - registerSlot *regNzcv = (*theRegSpace)[registerSpace::pstate]; - assert(regNzcv); - regMap[regNzcv] = SPR_NZCV; - if(force_save || regNzcv->liveState == registerSlot::spilled) - spRegs.push_back(regNzcv); + + registerSlot *regFpsr = (*theRegSpace)[registerSpace::fpsr]; + assert(regFpsr); + regMap[regFpsr] = SPR_FPSR; + if(force_save || regFpsr->liveState == registerSlot::spilled) + spRegs.push_back(regFpsr); registerSlot *regFpcr = (*theRegSpace)[registerSpace::fpcr]; assert(regFpcr); @@ -325,11 +326,11 @@ unsigned EmitterAARCH64RestoreRegs::restoreSPRegisters( if(force_save || regFpcr->liveState == registerSlot::spilled) spRegs.push_back(regFpcr); - registerSlot *regFpsr = (*theRegSpace)[registerSpace::fpsr]; - assert(regFpsr); - regMap[regFpsr] = SPR_FPSR; - if(force_save || regFpsr->liveState == registerSlot::spilled) - spRegs.push_back(regFpsr); + registerSlot *regNzcv = (*theRegSpace)[registerSpace::pstate]; + assert(regNzcv); + regMap[regNzcv] = SPR_NZCV; + if(force_save || regNzcv->liveState == registerSlot::spilled) + spRegs.push_back(regNzcv); for(std::vector::iterator itr = spRegs.begin(); itr != spRegs.end(); itr++) { registerSlot *cur = *itr; @@ -551,8 +552,13 @@ bool EmitterAARCH64::clobberAllFuncCall(registerSpace *rs, rs->GPRs()[*itr]->beenUsed = true; std::set *fpRegs = callee->ifunc()->usedFPRs(); - for(std::set::iterator itr = fpRegs->begin(); itr != fpRegs->end(); itr++) - rs->FPRs()[*itr]->beenUsed = true; + for(std::set::iterator itr = fpRegs->begin(); itr != fpRegs->end(); itr++) { + if (*itr <= rs->FPRs().size()) + rs->FPRs()[*itr]->beenUsed = true; + else + // parse_func::calcUsedRegs includes the subtype; we only want the regno + rs->FPRs()[*itr & 0xff]->beenUsed = true; + } } else { for(int idx = 0; idx < rs->numGPRs(); idx++) rs->GPRs()[idx]->beenUsed = true; @@ -639,24 +645,26 @@ Register EmitterAARCH64::emitCall(opCode op, // Passing operands to registers for(size_t id = 0; id < operands.size(); id++) { - Register reg = REG_NULL; + Register reg = Null_Register; if (gen.rs()->allocateSpecificRegister(gen, registerSpace::r0 + id, true)) reg = registerSpace::r0 + id; Address unnecessary = ADDR_NULL; if (!operands[id]->generateCode_phase2(gen, false, unnecessary, reg)) assert(0); - assert(reg!=REG_NULL); + assert(reg!=Null_Register); } assert(gen.rs()); - //Address of function to call in scratch register + // Address of function to call in scratch register Register scratch = gen.rs()->getScratchRegister(gen); - assert(scratch != REG_NULL && "cannot get a scratch register"); + assert(scratch != Null_Register && "cannot get a scratch register"); gen.markRegDefined(scratch); - if (gen.addrSpace()->edit() != NULL) { + if (gen.addrSpace()->edit() != NULL + && (gen.func()->obj() != callee->obj() + || gen.addrSpace()->needsPIC())) { // gen.as.edit() checks if we are in rewriter mode Address dest = getInterModuleFuncAddr(callee, gen); @@ -666,7 +674,6 @@ Register EmitterAARCH64::emitCall(opCode op, instruction insn; insn.clear(); INSN_SET(insn, 31, 31, 0); - //INSN_SET(insn, 29, 30, disp & 0x3); INSN_SET(insn, 28, 28, 1); INSN_SET(insn, 5, 23, disp >> 2); INSN_SET(insn, 0, 4, scratch); @@ -674,7 +681,7 @@ Register EmitterAARCH64::emitCall(opCode op, insnCodeGen::generateMemAccess(gen, insnCodeGen::Load, scratch, scratch, 0, 8, insnCodeGen::Offset); } else { - insnCodeGen::loadImmIntoReg
(gen, scratch, callee->addr()); + insnCodeGen::loadImmIntoReg(gen, scratch, callee->addr()); } instruction branchInsn; @@ -763,7 +770,7 @@ Register emitR(opCode op, Register src1, Register src2, Register dest, // TODO: PARAM_OFFSET(addrWidth) is currently not used // should delete that macro if it's useless - if (src2 != REG_NULL) insnCodeGen::saveRegister(gen, src2, stkOffset); + if (src2 != Null_Register) insnCodeGen::saveRegister(gen, src2, stkOffset); insnCodeGen::restoreRegister(gen, dest, stkOffset); return dest; @@ -781,7 +788,7 @@ Register emitR(opCode op, Register src1, Register src2, Register dest, { int offset = TRAMP_GPR_OFFSET(addrWidth); // its on the stack so load it. - //if (src2 != REG_NULL) saveRegister(gen, src2, reg, offset); + //if (src2 != Null_Register) saveRegister(gen, src2, reg, offset); insnCodeGen::restoreRegister(gen, dest, offset + (reg * gen.width())); return(dest); } @@ -877,20 +884,20 @@ void emitASload(const BPatch_addrSpec_NP *as, Register dest, int stackShift, if(ra == 32) { // Special case where the actual address is store in imm. // Need to change this for rewriting PIE or shared libraries - insnCodeGen::loadImmIntoReg(gen, dest, imm); + insnCodeGen::loadImmIntoReg(gen, dest, static_cast
(imm)); return; } else { restoreGPRtoGPR(gen, ra, dest); } } else { - insnCodeGen::loadImmIntoReg(gen, dest, 0); + insnCodeGen::loadImmIntoReg(gen, dest, static_cast
(0)); } if(rb > -1) { std::vector exclude; exclude.push_back(dest); Register scratch = gen.rs()->getScratchRegister(gen, exclude); - assert(scratch != REG_NULL && "cannot get a scratch register"); + assert(scratch != Null_Register && "cannot get a scratch register"); gen.markRegDefined(scratch); restoreGPRtoGPR(gen, rb, scratch); // call adds, save 2^scale * rb to dest @@ -1190,8 +1197,8 @@ bool AddressSpace::getDynamicCallSiteArgs(InstructionAPI::Instruction i, if(branch_target == registerSpace::ignored) return false; //jumping to Xn (BLR Xn) - args.push_back(AstNode::operandNode(AstNode::origRegister,(void *)(long)branch_target)); - args.push_back(AstNode::operandNode(AstNode::Constant, (void *) addr)); + args.push_back(AstNode::operandNode(AstNode::operandType::origRegister,(void *)(long)branch_target)); + args.push_back(AstNode::operandNode(AstNode::operandType::Constant, (void *) addr)); //inst_printf("%s[%d]: Inserting dynamic call site instrumentation for %s\n", // FILE__, __LINE__, cft->format(insn.getArch()).c_str()); @@ -1297,7 +1304,7 @@ bool EmitterAARCH6432Stat::emitPIC(codeGen& gen, Address origAddr, Address reloc int stack_size = 0; int gpr_off, fpr_off, ctr_off; //fprintf(stderr, " emitPIC origAddr 0x%lx reloc 0x%lx Registers PC %d scratch %d \n", origAddr, relocAddr, scratchPCReg, scratchReg); - if ((scratchPCReg == REG_NULL) || (scratchReg == REG_NULL)) { + if ((scratchPCReg == Null_Register) || (scratchReg == Null_Register)) { //fprintf(stderr, " Creating new stack frame for 0x%lx to 0x%lx \n", origAddr, relocAddr); newStackFrame = true; @@ -1313,11 +1320,11 @@ bool EmitterAARCH6432Stat::emitPIC(codeGen& gen, Address origAddr, Address reloc stack_size = saveGPRegisters(gen, gen.rs(), gpr_off, 2); scratchPCReg = gen.rs()->getScratchRegister(gen, true); - assert(scratchPCReg != REG_NULL); + assert(scratchPCReg != Null_Register); excludeReg.clear(); excludeReg.push_back(scratchPCReg); scratchReg = gen.rs()->getScratchRegister(gen, excludeReg, true); - assert(scratchReg != REG_NULL); + assert(scratchReg != Null_Register); // relocaAddr has moved since we added instructions to setup a new stack frame relocAddr = relocAddr + ((stack_size + 1)*(gen.width())); //fprintf(stderr, " emitPIC origAddr 0x%lx reloc 0x%lx stack size %d Registers PC %d scratch %d \n", origAddr, relocAddr, stack_size, scratchPCReg, scratchReg); @@ -1344,7 +1351,7 @@ bool EmitterAARCH64Dyn::emitPIC(codeGen &gen, Address origAddr, Address relocAdd Address origRet = origAddr + 4; Register scratch = gen.rs()->getScratchRegister(gen, true); - assert(scratch != REG_NULL); + assert(scratch != Null_Register); instruction::loadImmIntoReg(gen, scratch, origRet); insnCodeGen::generateMoveToLR(gen, scratch); return true; @@ -1409,7 +1416,7 @@ bool EmitterAARCH64Stat::emitPLTCommon(func_instance *callee, bool call, codeGen Register scratchReg = 3; // = gen.rs()->getScratchRegister(gen, true); int stackSize = 0; - if (scratchReg == REG_NULL) { + if (scratchReg == Null_Register) { std::vector freeReg; std::vector excludeReg; stackSize = insnCodeGen::createStackFrame(gen, 1, freeReg, excludeReg); @@ -1450,7 +1457,7 @@ bool EmitterAARCH64Stat::emitPLTCall(func_instance *callee, codeGen &gen) { long varOffset = dest - gen.currAddr(); Register baseReg = gen.rs()->getScratchRegister(gen, true); - assert(baseReg != REG_NULL && "cannot get a scratch register"); + assert(baseReg != Null_Register && "cannot get a scratch register"); emitMovePCToReg(baseReg, gen); std::vector exclude; @@ -1486,7 +1493,7 @@ bool EmitterAARCH64Stat::emitPLTJump(func_instance *callee, codeGen &gen) { long varOffset = dest - gen.currAddr(); Register baseReg = gen.rs()->getScratchRegister(gen, true); - assert(baseReg != REG_NULL && "cannot get a scratch register"); + assert(baseReg != Null_Register && "cannot get a scratch register"); emitMovePCToReg(baseReg, gen); std::vector exclude; @@ -1567,7 +1574,7 @@ void EmitterAARCH64::emitLoadShared(opCode op, Register dest, const image_variab // load register with address from jump slot Register baseReg = gen.rs()->getScratchRegister(gen, true); - assert(baseReg != REG_NULL && "cannot get a scratch register"); + assert(baseReg != Null_Register && "cannot get a scratch register"); emitMovePCToReg(baseReg, gen); Address varOffset = addr - gen.currAddr() + 4; @@ -1615,7 +1622,7 @@ void EmitterAARCH64::emitStoreShared(Register source, const image_variable *var, // load register with address from jump slot Register baseReg = gen.rs()->getScratchRegister(gen, true); - assert(baseReg != REG_NULL && "cannot get a scratch register"); + assert(baseReg != Null_Register && "cannot get a scratch register"); emitMovePCToReg(baseReg, gen); Address varOffset = addr - gen.currAddr() + 4; @@ -1624,7 +1631,7 @@ void EmitterAARCH64::emitStoreShared(Register source, const image_variable *var, std::vector exclude; exclude.push_back(baseReg); Register scratchReg1 = gen.rs()->getScratchRegister(gen, exclude, true); - assert(scratchReg1 != REG_NULL && "cannot get a scratch register"); + assert(scratchReg1 != Null_Register && "cannot get a scratch register"); emitLoadRelative(scratchReg1, varOffset, baseReg, gen.width(), gen); emitStoreRelative(source, 0, scratchReg1, size, gen); } else { diff --git a/dyninstAPI/src/inst-aarch64.h b/dyninstAPI/src/inst-aarch64.h index 99633bed9c..2c36754af9 100644 --- a/dyninstAPI/src/inst-aarch64.h +++ b/dyninstAPI/src/inst-aarch64.h @@ -28,6 +28,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include #ifndef INST_AARCH64_H diff --git a/dyninstAPI/src/inst-linux.C b/dyninstAPI/src/inst-linux.C index 1f25e0b478..842c70de58 100644 --- a/dyninstAPI/src/inst-linux.C +++ b/dyninstAPI/src/inst-linux.C @@ -35,7 +35,6 @@ #endif #include "dyninstAPI/src/os.h" -#include "dyninstAPI/src/dyninst.h" #include "dyninstAPI/src/image.h" #include "dyninstAPI/src/inst.h" #include "dyninstAPI/src/instP.h" diff --git a/dyninstAPI/src/inst-power.C b/dyninstAPI/src/inst-power.C index f8fd9b265a..4968c052f2 100644 --- a/dyninstAPI/src/inst-power.C +++ b/dyninstAPI/src/inst-power.C @@ -33,6 +33,7 @@ * $Id: inst-power.C,v 1.291 2008/06/19 22:13:42 jaw Exp $ */ +#include #include "common/src/headers.h" #include "dyninstAPI/h/BPatch_memoryAccess_NP.h" #include "dyninstAPI/src/image.h" @@ -411,11 +412,11 @@ unsigned registerSpace::SPR(Register x) { break; case cr: fprintf(stderr, "Error: condition register has no encoding!\n"); - return REG_NULL; + return Null_Register; break; default: assert(0); - return REG_NULL; + return Null_Register; break; } } @@ -1003,11 +1004,13 @@ unsigned restoreSPRegisters(codeGen &gen, fpscr_off = STK_FP_CR_64; } - registerSlot *regCR = (*(gen.rs()))[registerSpace::cr]; - assert (regCR != NULL); - if (force_save || regCR->liveState == registerSlot::spilled) + restoreFPSCR(gen, 10, save_off + fpscr_off); num_restored++; + + registerSlot *regXER = (*(gen.rs()))[registerSpace::xer]; + assert (regXER != NULL); + if (force_save || regXER->liveState == registerSlot::spilled) { - restoreCR(gen, 10, save_off + cr_off); num_restored++; + restoreSPR(gen, 10, SPR_XER, save_off + xer_off); num_restored++; } registerSlot *regCTR = (*(gen.rs()))[registerSpace::ctr]; assert (regCTR != NULL); @@ -1015,13 +1018,12 @@ unsigned restoreSPRegisters(codeGen &gen, { restoreSPR(gen, 10, SPR_CTR, save_off + ctr_off); num_restored++; } - registerSlot *regXER = (*(gen.rs()))[registerSpace::xer]; - assert (regXER != NULL); - if (force_save || regXER->liveState == registerSlot::spilled) + registerSlot *regCR = (*(gen.rs()))[registerSpace::cr]; + assert (regCR != NULL); + if (force_save || regCR->liveState == registerSlot::spilled) { - restoreSPR(gen, 10, SPR_XER, save_off + xer_off); num_restored++; + restoreCR(gen, 10, save_off + cr_off); num_restored++; } - restoreFPSCR(gen, 10, save_off + fpscr_off); num_restored++; return num_restored; } @@ -1309,7 +1311,7 @@ Register EmitterPOWER::emitCallReplacement(opCode ocode, } // What to return here? - return REG_NULL; + return Null_Register; } @@ -1363,7 +1365,7 @@ Register EmitterPOWER::emitCallReplacement(opCode ocode, // } // // What to return here? -// return REG_NULL; +// return Null_Register; // } // There are four "axes" going on here: // 32 bit vs 64 bit @@ -1493,17 +1495,17 @@ Register EmitterPOWER::emitCall(opCode ocode, insnCodeGen::generateImm(gen, CALop, dummyReg, 0, 0); } */ - //Register src = REG_NULL; + //Register src = Null_Register; // Try to target the code generation - Register reg = REG_NULL; + Register reg = Null_Register; // Try to allocate the correct parameter register if (gen.rs()->allocateSpecificRegister(gen, registerSpace::r3 + u, true)) reg = registerSpace::r3 + u; //fprintf(stderr, "info: %s:%d: Register: %d \n", __FILE__, __LINE__, reg); Address unused = ADDR_NULL; if (!operands[u]->generateCode_phase2( gen, false, unused, reg)) assert(0); - assert(reg != REG_NULL); + assert(reg != Null_Register); srcs.push_back(reg); //bperr( "Generated operand %d, base %d\n", u, base); } @@ -1588,7 +1590,7 @@ Register EmitterPOWER::emitCall(opCode ocode, emitCallInstruction(gen, callee, setTOC, toc_anchor); // ALL instrumentation - Register retReg = REG_NULL; + Register retReg = Null_Register; if (inInstrumentation) { // get a register to keep the return value in. retReg = gen.rs()->allocateRegister(gen, noCost); @@ -1702,7 +1704,7 @@ Register emitR(opCode op, Register src1, Register src2, Register dest, // 8 are stored on the caller's stack at an offset. // // src1 is the argument number 0..X, the first 8 are stored in regs - // src2 (if not REG_NULL) holds the value to be written into src1 + // src2 (if not Null_Register) holds the value to be written into src1 if(src1 < 8) { // src1 is 0..8 - it's a parameter number, not a register @@ -1731,7 +1733,7 @@ Register emitR(opCode op, Register src1, Register src2, Register dest, PARAM_OFFSET(addrWidth); } - if (src2 != REG_NULL) saveRegisterAtOffset(gen, src2, stkOffset); + if (src2 != Null_Register) saveRegisterAtOffset(gen, src2, stkOffset); restoreRegisterAtOffset(gen, dest, stkOffset); return(dest); } @@ -1756,7 +1758,7 @@ Register emitR(opCode op, Register src1, Register src2, Register dest, int offset = TRAMP_GPR_OFFSET(addrWidth); // its on the stack so load it. - if (src2 != REG_NULL) saveRegister(gen, src2, reg, offset); + if (src2 != Null_Register) saveRegister(gen, src2, reg, offset); restoreRegister(gen, reg, dest, offset); return(dest); } @@ -1772,7 +1774,7 @@ Register emitR(opCode op, Register src1, Register src2, Register dest, } assert(0); - return REG_NULL; + return Null_Register; } void emitJmpMC(int /*condition*/, int /*offset*/, codeGen &) @@ -2581,11 +2583,11 @@ bool AddressSpace::getDynamicCallSiteArgs(InstructionAPI::Instruction i, if(branch_target != registerSpace::ignored) { // Where we're jumping to (link register, count register) - args.push_back( AstNode::operandNode(AstNode::origRegister, + args.push_back( AstNode::operandNode(AstNode::operandType::origRegister, (void *)(long)branch_target)); // Where we are now - args.push_back( AstNode::operandNode(AstNode::Constant, + args.push_back( AstNode::operandNode(AstNode::operandType::Constant, (void *) addr)); return true; @@ -2933,7 +2935,7 @@ bool EmitterPOWER32Stat::emitPIC(codeGen& gen, Address origAddr, Address relocAd int stack_size = 0; int gpr_off, fpr_off, ctr_off; //fprintf(stderr, " emitPIC origAddr 0x%lx reloc 0x%lx Registers PC %d scratch %d \n", origAddr, relocAddr, scratchPCReg, scratchReg); - if ((scratchPCReg == REG_NULL) || (scratchReg == REG_NULL)) { + if ((scratchPCReg == Null_Register) || (scratchReg == Null_Register)) { //fprintf(stderr, " Creating new stack frame for 0x%lx to 0x%lx \n", origAddr, relocAddr); newStackFrame = true; @@ -2949,11 +2951,11 @@ bool EmitterPOWER32Stat::emitPIC(codeGen& gen, Address origAddr, Address relocAd stack_size = saveGPRegisters(gen, gen.rs(), gpr_off, 2); scratchPCReg = gen.rs()->getScratchRegister(gen, true); - assert(scratchPCReg != REG_NULL); + assert(scratchPCReg != Null_Register); excludeReg.clear(); excludeReg.push_back(scratchPCReg); scratchReg = gen.rs()->getScratchRegister(gen, excludeReg, true); - assert(scratchReg != REG_NULL); + assert(scratchReg != Null_Register); // relocaAddr has moved since we added instructions to setup a new stack frame relocAddr = relocAddr + ((stack_size + 1)*(gen.width())); //fprintf(stderr, " emitPIC origAddr 0x%lx reloc 0x%lx stack size %d Registers PC %d scratch %d \n", origAddr, relocAddr, stack_size, scratchPCReg, scratchReg); @@ -2980,7 +2982,7 @@ bool EmitterPOWERDyn::emitPIC(codeGen &gen, Address origAddr, Address relocAddr) Address origRet = origAddr + 4; Register scratch = gen.rs()->getScratchRegister(gen, true); - assert(scratch != REG_NULL); + assert(scratch != Null_Register); instruction::loadImmIntoReg(gen, scratch, origRet); insnCodeGen::generateMoveToLR(gen, scratch); return true; @@ -3003,12 +3005,12 @@ bool EmitterPOWER32Stat::emitCallInstruction(codeGen& gen, func_instance* callee bool EmitterPOWER32Stat::emitPLTCommon(func_instance *callee, bool call, codeGen &gen) { Register scratchReg = gen.rs()->getScratchRegister(gen, true); - if (scratchReg == REG_NULL) return false; + if (scratchReg == Null_Register) return false; - Register scratchLR = REG_NULL; + Register scratchLR = Null_Register; std::vector excluded; excluded.push_back(scratchReg); scratchLR = gen.rs()->getScratchRegister(gen, excluded, true); - if (scratchLR == REG_NULL) { + if (scratchLR == Null_Register) { if (scratchReg == registerSpace::r0) return false; // We can use r0 for this, since it's volatile. scratchLR = registerSpace::r0; @@ -3068,12 +3070,12 @@ bool EmitterPOWER32Stat::emitTOCJump(block_instance *block, codeGen &gen) { bool EmitterPOWER32Stat::emitTOCCommon(block_instance *block, bool call, codeGen &gen) { Register scratchReg = gen.rs()->getScratchRegister(gen, true); - if (scratchReg == REG_NULL) return false; + if (scratchReg == Null_Register) return false; - Register scratchLR = REG_NULL; + Register scratchLR = Null_Register; std::vector excluded; excluded.push_back(scratchReg); scratchLR = gen.rs()->getScratchRegister(gen, excluded, true); - if (scratchLR == REG_NULL) { + if (scratchLR == Null_Register) { if (scratchReg == registerSpace::r0) return false; // We can use r0 for this, since it's volatile. scratchReg = registerSpace::r0; @@ -3434,7 +3436,7 @@ void EmitterPOWER::emitLoadShared(opCode op, Register dest, const image_variable addr, gen.currAddr(), addr - gen.currAddr()+4, addr - gen.currAddr()+4, size); Register scratchReg = gen.rs()->getScratchRegister(gen, true); - if (scratchReg == REG_NULL) { + if (scratchReg == Null_Register) { std::vector freeReg; std::vector excludeReg; stackSize = insnCodeGen::createStackFrame(gen, 1, freeReg, excludeReg); @@ -3494,7 +3496,7 @@ void EmitterPOWER::emitStoreShared(Register source, const image_variable * var, // load register with address from jump slot Register scratchReg = gen.rs()->getScratchRegister(gen, true); - if (scratchReg == REG_NULL) { + if (scratchReg == Null_Register) { std::vector freeReg; std::vector excludeReg; stackSize = insnCodeGen::createStackFrame(gen, 1, freeReg, excludeReg); @@ -3512,7 +3514,7 @@ void EmitterPOWER::emitStoreShared(Register source, const image_variable * var, std::vector exclude; exclude.push_back(scratchReg); Register scratchReg1 = gen.rs()->getScratchRegister(gen, exclude, true); - if (scratchReg1 == REG_NULL) { + if (scratchReg1 == Null_Register) { std::vector freeReg; std::vector excludeReg; stackSize = insnCodeGen::createStackFrame(gen, 1, freeReg, excludeReg); diff --git a/dyninstAPI/src/inst-power.h b/dyninstAPI/src/inst-power.h index 60cb461206..5e1ce973d9 100644 --- a/dyninstAPI/src/inst-power.h +++ b/dyninstAPI/src/inst-power.h @@ -36,6 +36,8 @@ #ifndef INST_POWER_H #define INST_POWER_H +#include + /* "pseudo" instructions that are placed in the tramp code for the inst funcs * to patch up. This must be invalid instructions (any instruction with diff --git a/dyninstAPI/src/inst-winnt.C b/dyninstAPI/src/inst-winnt.C index 623a781931..0516d879ff 100644 --- a/dyninstAPI/src/inst-winnt.C +++ b/dyninstAPI/src/inst-winnt.C @@ -31,7 +31,6 @@ // $Id: inst-winnt.C,v 1.31 2008/06/19 22:13:42 jaw Exp $ #include "dyninstAPI/src/os.h" -#include "dyninstAPI/src/dyninst.h" #include "dyninstAPI/src/image.h" #include "dyninstAPI/src/dynProcess.h" #include "dyninstAPI/src/inst.h" @@ -46,7 +45,7 @@ #include "Instruction.h" #include "InstructionDecoder.h" -#include +#include using namespace Dyninst::InstructionAPI; diff --git a/dyninstAPI/src/inst-x86.C b/dyninstAPI/src/inst-x86.C index f8bdcf245f..d1510575b9 100644 --- a/dyninstAPI/src/inst-x86.C +++ b/dyninstAPI/src/inst-x86.C @@ -37,6 +37,7 @@ #include #include "common/src/headers.h" #include "compiler_annotations.h" +#include "compiler_diagnostics.h" #include #include "dyninstAPI/src/image.h" #include "dyninstAPI/src/inst.h" @@ -67,6 +68,7 @@ #include "Instruction.h" #include #include +#include "unaligned_memory_access.h" class ExpandInstruction; class InsertNops; @@ -197,7 +199,7 @@ void registerSpace::initialize32() { } -#if defined(cap_32_64) +#if defined arch_x86_64 void registerSpace::initialize64() { static bool done = false; if (done) return; @@ -538,7 +540,7 @@ void registerSpace::initialize() initialize32(); -#if defined(cap_32_64) +#if defined arch_x86_64 initialize64(); #endif } @@ -602,8 +604,8 @@ bool baseTramp::generateRestores(codeGen &gen, registerSpace*) { void emitJccR8(int condition_code, char jump_offset, codeGen &gen) { GET_PTR(insn, gen); - *insn++ = static_cast(condition_code); - *insn++ = jump_offset; + append_memory_as_byte(insn, condition_code); + append_memory_as_byte(insn, jump_offset); SET_PTR(insn, gen); } @@ -625,15 +627,14 @@ void emitJcc(int condition, int offset, if(!willRegen && (offset >= -128 && offset <= 127)) { // jcc rel8 opcode = 0x70 | (unsigned char)condition; - *insn++ = opcode; - *insn++ = (unsigned char) (offset & 0xFF); + append_memory_as_byte(insn, opcode); + append_memory_as_byte(insn, offset & 0xFF); } else { // jcc near rel32 opcode = 0x80 | (unsigned char)condition; - *insn++ = 0x0F; - *insn++ = opcode; - *((int*)insn) = offset; - insn += sizeof(int); + append_memory_as_byte(insn, 0x0F); + append_memory_as_byte(insn, opcode); + append_memory_as(insn, int32_t{offset}); } SET_PTR(insn, gen); } @@ -756,18 +757,18 @@ void emitAddressingMode(unsigned base, RegValue disp, } GET_PTR(insn, gen); if (base == Null_Register) { - *insn++ = makeModRMbyte(0, reg_opcode, 5); - *((int *)insn) = disp; - insn += sizeof(int); + append_memory_as_byte(insn, makeModRMbyte(0, reg_opcode, 5)); + assert(numeric_limits::lowest() <= disp && disp <= numeric_limits::max() && "disp more than 32 bits"); + append_memory_as(insn, static_cast(disp)); } else if (disp == 0 && base != REGNUM_EBP) { - *insn++ = makeModRMbyte(0, reg_opcode, base); + append_memory_as_byte(insn, makeModRMbyte(0, reg_opcode, base)); } else if (disp >= -128 && disp <= 127) { - *insn++ = makeModRMbyte(1, reg_opcode, base); - *((char *)insn++) = (char) disp; + append_memory_as_byte(insn, makeModRMbyte(1, reg_opcode, base)); + append_memory_as(insn, static_cast(disp)); } else { - *insn++ = makeModRMbyte(2, reg_opcode, base); - *((int *)insn) = disp; - insn += sizeof(int); + append_memory_as_byte(insn, makeModRMbyte(2, reg_opcode, base)); + assert(numeric_limits::lowest() <= disp && disp <= numeric_limits::max() && "disp more than 32 bits"); + append_memory_as(insn, static_cast(disp)); } SET_PTR(insn, gen); } @@ -795,25 +796,25 @@ void emitAddressingMode(unsigned base, unsigned index, GET_PTR(insn, gen); if(base == Null_Register) { // we have to emit [index<::lowest() <= disp && disp <= numeric_limits::max() && "disp more than 32 bits"); + append_memory_as(insn, static_cast(disp)); } else if(disp == 0 && base != REGNUM_EBP) { // EBP must have 0 disp8; emit [base+index<= -128 && disp <= 127) { // emit [base+index<(disp)); } else { // emit [base+index<::lowest() <= disp && disp <= numeric_limits::max() && "disp more than 32 bits"); + append_memory_as(insn, static_cast(disp)); } SET_PTR(insn, gen); @@ -823,16 +824,15 @@ void emitAddressingMode(unsigned base, unsigned index, /* emit a simple one-byte instruction */ void emitSimpleInsn(unsigned op, codeGen &gen) { GET_PTR(insn, gen); - *insn++ = static_cast(op); + append_memory_as(insn, static_cast(op)); SET_PTR(insn, gen); } void emitPushImm(unsigned int imm, codeGen &gen) { GET_PTR(insn, gen); - *insn++ = 0x68; - *((unsigned int *)insn) = imm; - insn += sizeof(unsigned int); + append_memory_as_byte(insn, 0x68); + append_memory_as(insn, uint32_t{imm}); SET_PTR(insn, gen); if (gen.rs()) gen.rs()->incStack(gen.addrSpace()->getAddressWidth()); @@ -845,34 +845,32 @@ void emitOpRegReg(unsigned opcode, RealRegister dest, RealRegister src, { GET_PTR(insn, gen); if (opcode <= 0xFF) - *insn++ = static_cast(opcode); + append_memory_as_byte(insn,opcode); else { - *insn++ = static_cast(opcode >> 8); - *insn++ = static_cast(opcode & 0xFF); + append_memory_as_byte(insn, opcode >> 8); + append_memory_as_byte(insn, opcode & 0xFF); } // ModRM byte define the operands: Mod = 3, Reg = dest, RM = src - *insn++ = makeModRMbyte(3, dest.reg(), src.reg()); + append_memory_as_byte(insn, makeModRMbyte(3, dest.reg(), src.reg())); SET_PTR(insn, gen); } void emitOpRegImm(int opcode, RealRegister dest, int imm, codeGen &gen) { GET_PTR(insn, gen); - *insn++ = 0x81; - *insn++ = makeModRMbyte(3, opcode, dest.reg()); - *((int *)insn) = imm; - insn+= sizeof(int); + append_memory_as_byte(insn, 0x81); + append_memory_as_byte(insn, makeModRMbyte(3, opcode, dest.reg())); + append_memory_as(insn, int32_t{imm}); SET_PTR(insn, gen); } void emitOpSegRMReg(unsigned opcode, RealRegister dest, RealRegister, int disp, codeGen &gen) { GET_PTR(insn, gen); - *insn++ = opcode; - *insn++ = makeModRMbyte(0, dest.reg(), 4); - *insn++ = 0x25; - *((int*)insn) = disp; - insn += sizeof(int); + append_memory_as_byte(insn, opcode); + append_memory_as_byte(insn, makeModRMbyte(0, dest.reg(), 4)); + append_memory_as_byte(insn, 0x25); + append_memory_as(insn, int32_t{disp}); SET_PTR(insn, gen); } @@ -883,10 +881,10 @@ void emitOpRegRM(unsigned opcode, RealRegister dest, RealRegister base, { GET_PTR(insn, gen); if (opcode <= 0xff) { - *insn++ = static_cast(opcode); + append_memory_as_byte(insn, opcode); } else { - *insn++ = static_cast(opcode >> 8); - *insn++ = static_cast(opcode & 0xff); + append_memory_as_byte(insn, opcode >> 8); + append_memory_as_byte(insn, opcode & 0xff); } SET_PTR(insn, gen); emitAddressingMode(base.reg(), disp, dest.reg(), gen); @@ -896,7 +894,7 @@ void emitOpRegRM(unsigned opcode, RealRegister dest, RealRegister base, void emitOpRMReg(unsigned opcode, RealRegister base, int disp, RealRegister src, codeGen &gen) { GET_PTR(insn, gen); - *insn++ = static_cast(opcode); + append_memory_as_byte(insn, opcode); SET_PTR(insn, gen); emitAddressingMode(base.reg(), disp, src.reg(), gen); } @@ -906,10 +904,9 @@ void emitOpExtRegImm(int opcode, int ext, RealRegister dest, int imm, codeGen &gen) { GET_PTR(insn, gen); - *insn++ = opcode; - *insn++ = makeModRMbyte(3, (char) ext, dest.reg()); - *((int *)insn) = imm; - insn+= sizeof(int); + append_memory_as_byte(insn, opcode); + append_memory_as_byte(insn, makeModRMbyte(3, (char) ext, dest.reg())); + append_memory_as(insn, int32_t{imm}); SET_PTR(insn, gen); } @@ -917,36 +914,34 @@ void emitOpExtRegImm8(int opcode, char ext, RealRegister dest, unsigned char imm codeGen &gen) { GET_PTR(insn, gen); - *insn++ = opcode; - *insn++ = makeModRMbyte(3, ext, dest.reg()); - *((unsigned char *)insn) = imm; - insn+= sizeof(unsigned char); + append_memory_as_byte(insn, opcode); + append_memory_as_byte(insn, makeModRMbyte(3, ext, dest.reg())); + append_memory_as_byte(insn, imm); SET_PTR(insn, gen); } void emitOpExtReg(unsigned opcode, unsigned char ext, RealRegister reg, codeGen &gen) { GET_PTR(insn, gen); - *insn++ = opcode; - *insn++ = makeModRMbyte(3, ext, reg.reg()); + append_memory_as_byte(insn, opcode); + append_memory_as_byte(insn, makeModRMbyte(3, ext, reg.reg())); SET_PTR(insn, gen); } void emitMovRegToReg(RealRegister dest, RealRegister src, codeGen &gen) { GET_PTR(insn, gen); - *insn++ = 0x8B; - *insn++ = makeModRMbyte(3, dest.reg(), src.reg()); + append_memory_as_byte(insn, 0x8B); + append_memory_as_byte(insn, makeModRMbyte(3, dest.reg(), src.reg())); SET_PTR(insn, gen); } void emitOpRegRegImm(unsigned opcode, RealRegister dest, RealRegister src, unsigned imm, codeGen &gen) { GET_PTR(insn, gen); - *insn++ = opcode; - *insn++ = makeModRMbyte(3, dest.reg(), src.reg()); - *((int *)insn) = imm; - insn += sizeof(int); + append_memory_as_byte(insn, opcode); + append_memory_as_byte(insn, makeModRMbyte(3, dest.reg(), src.reg())); + append_memory_as(insn, uint32_t{imm}); SET_PTR(insn, gen); } @@ -954,8 +949,8 @@ void emitOpRegRegImm(unsigned opcode, RealRegister dest, RealRegister src, unsig void emitMovIRegToReg(RealRegister dest, RealRegister src, codeGen &gen) { GET_PTR(insn, gen); - *insn++ = 0x8B; - *insn++ = makeModRMbyte(0, dest.reg(), src.reg()); + append_memory_as_byte(insn, 0x8B); + append_memory_as_byte(insn, makeModRMbyte(0, dest.reg(), src.reg())); SET_PTR(insn, gen); gen.markRegDefined(dest.reg()); } @@ -968,7 +963,7 @@ void emitLEA(RealRegister base, RealRegister index, unsigned int scale, if (dest.reg() != REGNUM_ESP) gen.markRegDefined(dest.reg()); GET_PTR(insn, gen); - *insn++ = 0x8D; + append_memory_as_byte(insn, 0x8D); SET_PTR(insn, gen); emitAddressingMode(base.reg(), index.reg(), scale, disp, (int)dest.reg(), gen); } @@ -978,10 +973,9 @@ void emitLEA(RealRegister base, unsigned displacement, RealRegister dest, { gen.markRegDefined(dest.reg()); GET_PTR(insn, gen); - *insn++ = 0x8D; - *insn++ = makeModRMbyte(2, dest.reg(), base.reg()); - *((unsigned *) insn) = displacement; - insn += sizeof(unsigned); + append_memory_as_byte(insn, 0x8D); + append_memory_as_byte(insn, makeModRMbyte(2, dest.reg(), base.reg())); + append_memory_as(insn, uint32_t{displacement}); SET_PTR(insn, gen); } @@ -1020,12 +1014,12 @@ void emitMovPCRMToReg(RealRegister dest, int offset, codeGen &gen, bool deref_re pc_reg = gen.rs()->loadVirtualForWrite(gen.rs()->pc_rel_reg, gen); } gen.rs()->pc_rel_offset() = used + 5; - *insn++ = 0xE8; - *insn++ = 0x00; - *insn++ = 0x00; - *insn++ = 0x00; - *insn++ = 0x00; - *insn++ = static_cast(0x58 + pc_reg.reg()); + append_memory_as_byte(insn, 0xE8); + append_memory_as_byte(insn, 0x00); + append_memory_as_byte(insn, 0x00); + append_memory_as_byte(insn, 0x00); + append_memory_as_byte(insn, 0x00); + append_memory_as_byte(insn, 0x58 + pc_reg.reg()); SET_PTR(insn, gen); } else { @@ -1059,7 +1053,7 @@ void emitMovRMToReg(RealRegister dest, RealRegister base, int disp, codeGen &gen) { GET_PTR(insn, gen); - *insn++ = 0x8B; + append_memory_as_byte(insn, 0x8B); SET_PTR(insn, gen); emitAddressingMode(base.reg(), disp, dest.reg(), gen); } @@ -1069,7 +1063,7 @@ void emitMovRegToRM(RealRegister base, int disp, RealRegister src, codeGen &gen) { GET_PTR(insn, gen); - *insn++ = 0x89; + append_memory_as_byte(insn, 0x89); SET_PTR(insn, gen); emitAddressingMode(base.reg(), disp, src.reg(), gen); } @@ -1078,7 +1072,7 @@ void emitMovRegToRM(RealRegister base, int disp, RealRegister src, void emitMovRegToM(int disp, RealRegister src, codeGen &gen) { GET_PTR(insn, gen); - *insn++ = 0x89; + append_memory_as_byte(insn, 0x89); SET_PTR(insn, gen); emitAddressingMode(Null_Register, disp, src.reg(), gen); } @@ -1087,10 +1081,9 @@ void emitMovRegToM(int disp, RealRegister src, codeGen &gen) void emitMovRegToMB(int disp, RealRegister src, codeGen &gen) { GET_PTR(insn, gen); - *insn++ = 0x88; - *insn++ = makeModRMbyte(0, src.reg(), 5); - *((int *) insn) = disp; - insn += sizeof(int); + append_memory_as_byte(insn, 0x88); + append_memory_as_byte(insn, makeModRMbyte(0, src.reg(), 5)); + append_memory_as(insn, int32_t{disp}); SET_PTR(insn, gen); } @@ -1098,11 +1091,10 @@ void emitMovRegToMB(int disp, RealRegister src, codeGen &gen) void emitMovRegToMW(int disp, RealRegister src, codeGen &gen) { GET_PTR(insn, gen); - *insn++ = 0x66; - *insn++ = 0x88; - *insn++ = makeModRMbyte(0, src.reg(), 5); - *((int *) insn) = disp; - insn += sizeof(int); + append_memory_as_byte(insn, 0x66); + append_memory_as_byte(insn, 0x88); + append_memory_as_byte(insn, makeModRMbyte(0, src.reg(), 5)); + append_memory_as(insn, int32_t{disp}); SET_PTR(insn, gen); } @@ -1111,7 +1103,7 @@ void emitMovMToReg(RealRegister dest, int disp, codeGen &gen) { gen.markRegDefined(dest.reg()); GET_PTR(insn, gen); - *insn++ = 0x8B; + append_memory_as_byte(insn, 0x8B); SET_PTR(insn, gen); emitAddressingMode(Null_Register, disp, dest.reg(), gen); } @@ -1121,8 +1113,8 @@ void emitMovMBToReg(RealRegister dest, int disp, codeGen &gen) { gen.markRegDefined(dest.reg()); GET_PTR(insn, gen); - *insn++ = 0x0F; - *insn++ = 0xBE; + append_memory_as_byte(insn, 0x0F); + append_memory_as_byte(insn, 0xBE); SET_PTR(insn, gen); emitAddressingMode(Null_Register, disp, dest.reg(), gen); } @@ -1132,8 +1124,8 @@ void emitMovMWToReg(RealRegister dest, int disp, codeGen &gen) { gen.markRegDefined(dest.reg()); GET_PTR(insn, gen); - *insn++ = 0x0F; - *insn++ = 0xBF; + append_memory_as_byte(insn, 0x0F); + append_memory_as_byte(insn, 0xBF); SET_PTR(insn, gen); emitAddressingMode(Null_Register, disp, dest.reg(), gen); } @@ -1142,9 +1134,8 @@ void emitMovMWToReg(RealRegister dest, int disp, codeGen &gen) void emitMovImmToReg(RealRegister dest, int imm, codeGen &gen) { GET_PTR(insn, gen); - *insn++ = static_cast(0xB8 + dest.reg()); - *((int *)insn) = imm; - insn += sizeof(int); + append_memory_as_byte(insn, 0xB8 + dest.reg()); + append_memory_as(insn, int32_t{imm}); SET_PTR(insn, gen); } @@ -1152,12 +1143,11 @@ void emitMovImmToReg(RealRegister dest, int imm, codeGen &gen) void emitMovImmToRM(RealRegister base, int disp, int imm, codeGen &gen) { GET_PTR(insn, gen); - *insn++ = 0xC7; + append_memory_as_byte(insn, 0xC7); SET_PTR(insn, gen); emitAddressingMode(base.reg(), disp, 0, gen); REGET_PTR(insn, gen); - *((int*)insn) = imm; - insn += sizeof(int); + append_memory_as(insn, int32_t{imm}); SET_PTR(insn, gen); } @@ -1169,7 +1159,7 @@ void emitMovImmToMem(Address maddr, int imm, // address operand (in both x86 and x86_64), the full ModRM + SIB // syntax must be used. GET_PTR(insn, gen); - *insn++ = 0xC7; + append_memory_as_byte(insn, 0xC7); // FIXME: To adhere strictly to the x86 and x86_64 ISAs, we specify an // absolute (32-bit) address by emitting a ModRM and SIB byte of the @@ -1179,13 +1169,12 @@ void emitMovImmToMem(Address maddr, int imm, // Current forms of emitAddressingMode() do not allow for this, and so // we do it manually here. emitAddressingMode() should be made more // robust. - *insn++ = makeModRMbyte(0, 0, 4); - *insn++ = makeSIBbyte(0, 4, 5); - *((int *)insn) = maddr; - insn += sizeof(unsigned); + append_memory_as_byte(insn, makeModRMbyte(0, 0, 4)); + append_memory_as_byte(insn, makeSIBbyte(0, 4, 5)); + assert(maddr <= numeric_limits::max() && "maddr more than 32 bits"); + append_memory_as(insn, static_cast(maddr)); - *((int*)insn) = imm; - insn += sizeof(int); + append_memory_as(insn, int32_t{imm}); SET_PTR(insn, gen); } @@ -1193,12 +1182,11 @@ void emitMovImmToMem(Address maddr, int imm, void emitAddMemImm32(Address addr, int imm, codeGen &gen) { GET_PTR(insn, gen); - *insn++ = 0x81; - *insn++ = 0x05; - *((unsigned *)insn) = addr; - insn += sizeof(unsigned); - *((int *)insn) = imm; - insn += sizeof(int); + append_memory_as_byte(insn, 0x81); + append_memory_as_byte(insn, 0x05); + assert(addr <= numeric_limits::max() && "addr more than 32 bits"); + append_memory_as(insn, static_cast(addr)); + append_memory_as(insn, int32_t{imm}); SET_PTR(insn, gen); } @@ -1207,16 +1195,14 @@ void emitAddRegImm32(RealRegister reg, int imm, codeGen &gen) { GET_PTR(insn, gen); if (imm >= -128 && imm <= 127) { - *insn++ = 0x83; - *insn++ = makeModRMbyte(3, 0, reg.reg()); - *((char *)insn) = (char) imm; - insn += sizeof(char); + append_memory_as_byte(insn, 0x83); + append_memory_as_byte(insn, makeModRMbyte(3, 0, reg.reg())); + append_memory_as_byte(insn, static_cast(imm)); } else { - *insn++ = 0x81; - *insn++ = makeModRMbyte(3, 0, reg.reg()); - *((int *)insn) = imm; - insn += sizeof(int); + append_memory_as_byte(insn, 0x81); + append_memory_as_byte(insn, makeModRMbyte(3, 0, reg.reg())); + append_memory_as(insn, int32_t{imm}); } SET_PTR(insn, gen); } @@ -1226,8 +1212,8 @@ void emitSubRegReg(RealRegister dest, RealRegister src, codeGen &gen) { gen.markRegDefined(dest.reg()); GET_PTR(insn, gen); - *insn++ = 0x2B; - *insn++ = makeModRMbyte(3, dest.reg(), src.reg()); + append_memory_as_byte(insn, 0x2B); + append_memory_as_byte(insn, makeModRMbyte(3, dest.reg(), src.reg())); SET_PTR(insn, gen); } @@ -1271,19 +1257,19 @@ unsigned char jccOpcodeFromRelOp(unsigned op, bool s) return 0x0; } -Register emitFuncCall(opCode, codeGen &, std::vector &, bool, Address) { +Dyninst::Register emitFuncCall(opCode, codeGen &, std::vector &, bool, Address) { assert(0); return 0; } // this function just multiplexes between the 32-bit and 64-bit versions -Register emitFuncCall(opCode op, +Dyninst::Register emitFuncCall(opCode op, codeGen &gen, std::vector &operands, bool noCost, func_instance *callee) { - Register reg = gen.codeEmitter()->emitCall(op, gen, operands, noCost, callee); + Dyninst::Register reg = gen.codeEmitter()->emitCall(op, gen, operands, noCost, callee); return reg; } @@ -1335,7 +1321,7 @@ void EmitterIA32::setFPSaveOrNot(const int * liveFPReg,bool saveOrNot) } -Register EmitterIA32::emitCall(opCode op, +Dyninst::Register EmitterIA32::emitCall(opCode op, codeGen &gen, const std::vector &operands, bool noCost, func_instance *callee) { @@ -1353,9 +1339,9 @@ Register EmitterIA32::emitCall(opCode op, cerr << "ERROR: emitCall with op == " << op << endl; } assert(op == callOp); - std::vector srcs; + std::vector srcs; int param_size; - std::vector saves; + std::vector saves; // Sanity check for NULL address arg if (!callee) { @@ -1368,14 +1354,14 @@ Register EmitterIA32::emitCall(opCode op, param_size = emitCallParams(gen, operands, callee, saves, noCost); - //Register ret = gen.rs()->allocateRegister(gen, noCost); - Register ret = REGNUM_EAX; + //Dyninst::Register ret = gen.rs()->allocateRegister(gen, noCost); + Dyninst::Register ret = REGNUM_EAX; emitCallInstruction(gen, callee, ret); emitCallCleanup(gen, callee, param_size, saves); - if (!inInstrumentation) return REG_NULL; + if (!inInstrumentation) return Null_Register; // allocate a (virtual) register to store the return value // Virtual register @@ -1389,7 +1375,7 @@ Register EmitterIA32::emitCall(opCode op, * base is the next free position on ibuf where code is to be generated */ -codeBufIndex_t emitA(opCode op, Register src1, Register /*src2*/, long dest, +codeBufIndex_t emitA(opCode op, Dyninst::Register src1, Dyninst::Register /*src2*/, long dest, codeGen &gen, RegControl rc, bool /*noCost*/) { //bperr("emitA(op=%d,src1=%d,src2=XX,dest=%d)\n",op,src1,dest); @@ -1425,7 +1411,7 @@ codeBufIndex_t emitA(opCode op, Register src1, Register /*src2*/, long dest, return retval; } -Register emitR(opCode op, Register src1, Register src2, Register dest, +Dyninst::Register emitR(opCode op, Dyninst::Register src1, Dyninst::Register src2, Dyninst::Register dest, codeGen &gen, bool noCost, const instPoint *location, bool /*for_multithreaded*/) { @@ -1473,10 +1459,10 @@ void emitSHL(RealRegister dest, unsigned char pos, codeGen &gen) //bperr( "Emiting SHL\n"); gen.markRegDefined(dest.reg()); GET_PTR(insn, gen); - *insn++ = 0xC1; - *insn++ = makeModRMbyte(3 /* rm gives register */, - 4 /* opcode ext. */, dest.reg()); - *insn++ = pos; + append_memory_as_byte(insn, 0xC1); + append_memory_as_byte(insn, makeModRMbyte(3 /* rm gives register */, + 4 /* opcode ext. */, dest.reg())); + append_memory_as_byte(insn, pos); SET_PTR(insn, gen); } @@ -1532,19 +1518,15 @@ stackItemLocation getHeightOf(stackItem sitem, codeGen &gen) RealRegister reg; int addr_width = gen.addrSpace()->getAddressWidth(); -#if defined(__GNUC__) - #pragma GCC diagnostic push - #if __GNUC__ >= 7 - // disable warning as the registers numbers are identical for 32-bit - // and 64-bit but use semantically distinct names - #pragma GCC diagnostic ignored "-Wduplicated-branches" - #endif -#endif + + // Suppress warning (for compilers where it is a false positive) + // The value of REGNUM_EBP and REGNUM_RBP are identical + DYNINST_DIAGNOSTIC_BEGIN_SUPPRESS_DUPLICATED_BRANCHES + RealRegister plat_bp(addr_width == 4 ? REGNUM_EBP : REGNUM_RBP); RealRegister plat_sp(addr_width == 4 ? REGNUM_ESP : REGNUM_RSP); -#if defined(__GNUC__) - #pragma GCC diagnostic pop -#endif + + DYNINST_DIAGNOSTIC_END_SUPPRESS_DUPLICATED_BRANCHES if (sitem.item == stackItem::reg_item && sitem.reg.reg() == plat_sp.reg()) { @@ -1606,13 +1588,13 @@ stackItemLocation getHeightOf(stackItem sitem, codeGen &gen) } } assert(0); - return stackItemLocation(RealRegister(REG_NULL), 0); + return stackItemLocation(RealRegister(Null_Register), 0); } // Restore mutatee value of GPR reg to dest (real) GPR -Register restoreGPRtoReg(RealRegister reg, codeGen &gen, RealRegister *dest_to_use) +Dyninst::Register restoreGPRtoReg(RealRegister reg, codeGen &gen, RealRegister *dest_to_use) { - Register dest = REG_NULL; + Dyninst::Register dest = Null_Register; RealRegister dest_r(-1); if (dest_to_use) { dest_r = *dest_to_use; @@ -1662,7 +1644,7 @@ Register restoreGPRtoReg(RealRegister reg, codeGen &gen, RealRegister *dest_to_u if (r->spilledState == registerSlot::unspilled || !gen.isRegDefined(reg.reg())) { - //Register is still in its pristine state from app, leave it. + //Dyninst::Register is still in its pristine state from app, leave it. if (dest_r.reg() == -1) gen.rs()->noteVirtualInReal(dest, reg); else if (dest_r.reg() != reg.reg()) @@ -1687,7 +1669,7 @@ void restoreGPRtoGPR(RealRegister src, RealRegister dest, codeGen &gen) // VG(11/07/01): Load in destination the effective address given // by the address descriptor. Used for memory access stuff. -void emitASload(const BPatch_addrSpec_NP *as, Register dest, int stackShift, codeGen &gen, bool /* noCost */) +void emitASload(const BPatch_addrSpec_NP *as, Dyninst::Register dest, int stackShift, codeGen &gen, bool /* noCost */) { // TODO 16-bit registers, rep hacks long imm = as->getImm(); @@ -1698,7 +1680,7 @@ void emitASload(const BPatch_addrSpec_NP *as, Register dest, int stackShift, cod gen.codeEmitter()->emitASload(ra, rb, sc, imm, dest, stackShift, gen); } -void EmitterIA32::emitASload(int ra, int rb, int sc, long imm, Register dest, int stackOffset, codeGen &gen) +void EmitterIA32::emitASload(int ra, int rb, int sc, long imm, Dyninst::Register dest, int stackOffset, codeGen &gen) { bool havera = ra > -1, haverb = rb > -1; @@ -1719,7 +1701,7 @@ void EmitterIA32::emitASload(int ra, int rb, int sc, long imm, Register dest, in } RealRegister src1_r(-1); - Register src1 = REG_NULL; + Dyninst::Register src1 = Null_Register; if (havera) { if (gen.inInstrumentation()) { src1 = restoreGPRtoReg(RealRegister(ra), gen); @@ -1738,7 +1720,7 @@ void EmitterIA32::emitASload(int ra, int rb, int sc, long imm, Register dest, in } RealRegister src2_r(-1); - Register src2 = REG_NULL; + Dyninst::Register src2 = Null_Register; if (haverb) { if (ra == rb) { src2_r = src1_r; @@ -1785,17 +1767,17 @@ void EmitterIA32::emitASload(int ra, int rb, int sc, long imm, Register dest, in } ::emitLEA(src1_r, src2_r, sc, (long) imm, dest_r, gen); - if (src1 != REG_NULL) { + if (src1 != Null_Register) { gen.rs()->unKeepRegister(src1); gen.rs()->freeRegister(src1); } - if (src2 != REG_NULL) { + if (src2 != Null_Register) { gen.rs()->unKeepRegister(src2); gen.rs()->freeRegister(src2); } } -void emitCSload(const BPatch_countSpec_NP *as, Register dest, +void emitCSload(const BPatch_countSpec_NP *as, Dyninst::Register dest, codeGen &gen, bool /* noCost */ ) { // VG(7/30/02): different from ASload on this platform, no LEA business @@ -1808,7 +1790,7 @@ void emitCSload(const BPatch_countSpec_NP *as, Register dest, gen.codeEmitter()->emitCSload(ra, rb, sc, imm, dest, gen); } -void EmitterIA32::emitCSload(int ra, int rb, int sc, long imm, Register dest, codeGen &gen) +void EmitterIA32::emitCSload(int ra, int rb, int sc, long imm, Dyninst::Register dest, codeGen &gen) { // count is at most 1 register or constant or hack (aka pseudoregister) assert((ra == -1) && @@ -1923,7 +1905,7 @@ void EmitterIA32::emitCSload(int ra, int rb, int sc, long imm, Register dest, co } } -void emitVload(opCode op, Address src1, Register src2, Register dest, +void emitVload(opCode op, Address src1, Dyninst::Register src2, Dyninst::Register dest, codeGen &gen, bool /*noCost*/, registerSpace * /*rs*/, int size, const instPoint * /* location */, AddressSpace * /* proc */) @@ -1965,7 +1947,7 @@ void emitVload(opCode op, Address src1, Register src2, Register dest, } } -void emitVstore(opCode op, Register src1, Register src2, Address dest, +void emitVstore(opCode op, Dyninst::Register src1, Dyninst::Register src2, Address dest, codeGen &gen, bool /*noCost*/, registerSpace * /*rs*/, int size, const instPoint * /* location */, AddressSpace * /* proc */) @@ -1988,7 +1970,7 @@ void emitVstore(opCode op, Register src1, Register src2, Address dest, } } -void emitV(opCode op, Register src1, Register src2, Register dest, +void emitV(opCode op, Dyninst::Register src1, Dyninst::Register src2, Dyninst::Register dest, codeGen &gen, bool /*noCost*/, registerSpace * /*rs*/, int size, const instPoint * /* location */, AddressSpace * /* proc */, bool s) @@ -2083,7 +2065,7 @@ void emitV(opCode op, Register src1, Register src2, Register dest, return; } -void emitImm(opCode op, Register src1, RegValue src2imm, Register dest, +void emitImm(opCode op, Dyninst::Register src1, RegValue src2imm, Dyninst::Register dest, codeGen &gen, bool, registerSpace *, bool s) { if (op == storeOp) { @@ -2218,12 +2200,12 @@ int getInsnCost(opCode op) return 0; } -bool EmitterIA32::emitPush(codeGen &gen, Register reg) { +bool EmitterIA32::emitPush(codeGen &gen, Dyninst::Register reg) { RealRegister real_reg = gen.rs()->loadVirtual(reg, gen); return ::emitPush(real_reg, gen); } -bool EmitterIA32::emitPop(codeGen &gen, Register reg) { +bool EmitterIA32::emitPop(codeGen &gen, Dyninst::Register reg) { RealRegister real_reg = gen.rs()->loadVirtual(reg, gen); return ::emitPop(real_reg, gen); } @@ -2233,7 +2215,7 @@ bool emitPush(RealRegister reg, codeGen &gen) { int r = reg.reg(); assert(r < 8); - *insn++ = static_cast(0x50 + r); // 0x50 is push EAX, and it increases from there. + append_memory_as_byte(insn, 0x50 + r); // 0x50 is push EAX, and it increases from there. SET_PTR(insn, gen); if (gen.inInstrumentation()) { @@ -2246,7 +2228,7 @@ bool emitPop(RealRegister reg, codeGen &gen) { GET_PTR(insn, gen); int r = reg.reg(); assert(r < 8); - *insn++ = static_cast(0x58 + r); + append_memory_as_byte(insn, 0x58 + r); SET_PTR(insn, gen); if (gen.inInstrumentation()) { gen.rs()->incStack(-4); @@ -2266,7 +2248,7 @@ bool EmitterIA32::emitAdjustStackPointer(int index, codeGen &gen) { void emitLoadPreviousStackFrameRegister(Address register_num, - Register dest, + Dyninst::Register dest, codeGen &gen, int, bool){ @@ -2274,7 +2256,7 @@ void emitLoadPreviousStackFrameRegister(Address register_num, } void emitStorePreviousStackFrameRegister(Address register_num, - Register src, + Dyninst::Register src, codeGen &gen, int, bool) { @@ -2294,7 +2276,7 @@ bool AddressSpace::getDynamicCallSiteArgs(InstructionAPI::Instruction insn, cft->apply(&f); assert(f.m_stack.size() == 1); args.push_back(f.m_stack[0]); - args.push_back(AstNode::operandNode(AstNode::Constant, + args.push_back(AstNode::operandNode(AstNode::operandType::Constant, (void *) addr)); inst_printf("%s[%d]: Inserting dynamic call site instrumentation for %s\n", FILE__, __LINE__, cft->format(insn.getArch()).c_str()); @@ -2382,18 +2364,13 @@ Emitter *AddressSpace::getEmitter() #if defined(arch_x86_64) int registerSpace::framePointer() { -#if defined(__GNUC__) - #pragma GCC diagnostic push - #if __GNUC__ >= 7 - // disable warning as the registers numbers are identical for 32-bit - // and 64-bit but use semantically distinct names - #pragma GCC diagnostic ignored "-Wduplicated-branches" - #endif -#endif + // Suppress warning (for compilers where it is a false positive) + // The value of REGNUM_EBP and REGNUM_RBP are identical + DYNINST_DIAGNOSTIC_BEGIN_SUPPRESS_DUPLICATED_BRANCHES + return addr_width == 8 ? REGNUM_RBP : REGNUM_EBP; -#if defined(__GNUC__) - #pragma GCC diagnostic pop -#endif + + DYNINST_DIAGNOSTIC_END_SUPPRESS_DUPLICATED_BRANCHES } #elif defined(arch_x86) int registerSpace::framePointer() { @@ -2480,36 +2457,34 @@ regState_t::regState_t() : void emitSaveO(codeGen &gen) { GET_PTR(insn, gen); - *insn++ = 0x0f; - *insn++ = 0x90; - *insn++ = 0xC0; + append_memory_as_byte(insn, 0x0f); + append_memory_as_byte(insn, 0x90); + append_memory_as_byte(insn, 0xC0); SET_PTR(insn, gen); } void emitRestoreO(codeGen &gen) { GET_PTR(insn, gen); - *insn++ = 0x80; - *insn++ = 0xC0; - *insn++ = 0x7f; + append_memory_as_byte(insn, 0x80); + append_memory_as_byte(insn, 0xC0); + append_memory_as_byte(insn, 0x7f); SET_PTR(insn, gen); } void emitCallRel32(unsigned disp32, codeGen &gen) { GET_PTR(insn, gen); - *insn++ = 0xE8; - *((int *) insn) = disp32; - insn += sizeof(int); + append_memory_as_byte(insn, 0xE8); + append_memory_as(insn, uint32_t{disp32}); SET_PTR(insn, gen); } void emitJump(unsigned disp32, codeGen &gen) { GET_PTR(insn, gen); - *insn++ = 0xE9; - *((int *) insn) = disp32; - insn += sizeof(int); + append_memory_as_byte(insn, 0xE9); + append_memory_as(insn, uint32_t{disp32}); SET_PTR(insn, gen); } @@ -2522,20 +2497,20 @@ void emitJump(unsigned disp32, codeGen &gen) int EmitterIA32::emitCallParams(codeGen &gen, const std::vector &operands, func_instance */*target*/, - std::vector &/*extra_saves*/, + std::vector &/*extra_saves*/, bool noCost) { - std::vector srcs; + std::vector srcs; unsigned frame_size = 0; unsigned u; for (u = 0; u < operands.size(); u++) { Address unused = ADDR_NULL; - Register reg = REG_NULL; + Dyninst::Register reg = Null_Register; if (!operands[u]->generateCode_phase2(gen, noCost, unused, reg)) assert(0); // ARGH.... - assert (reg != REG_NULL); // Give me a real return path! + assert (reg != Null_Register); // Give me a real return path! srcs.push_back(reg); } @@ -2554,7 +2529,7 @@ int EmitterIA32::emitCallParams(codeGen &gen, bool EmitterIA32::emitCallCleanup(codeGen &gen, func_instance * /*target*/, int frame_size, - std::vector &/*extra_saves*/) + std::vector &/*extra_saves*/) { if (frame_size) emitOpRegImm(0, RealRegister(REGNUM_ESP), frame_size, gen); // add esp, frame_size diff --git a/dyninstAPI/src/inst-x86.h b/dyninstAPI/src/inst-x86.h index 5c45c2c38e..47c02d47d3 100644 --- a/dyninstAPI/src/inst-x86.h +++ b/dyninstAPI/src/inst-x86.h @@ -55,6 +55,7 @@ */ +#include #include "dyninstAPI/src/registerSpace.h" #define NUM_VIRTUAL_REGISTERS (32) /* number of virtual registers */ @@ -158,9 +159,9 @@ class codeGen; #define SAVE_VIRTUAL64(x, insn) emitMovRegToRM(REGNUM_RBP, -1*(x*8), REGNUM_RAX, insn) void emitAddressingMode(unsigned base, unsigned index, - unsigned int scale, RegValue disp, + unsigned int scale, Dyninst::RegValue disp, int reg_opcode, codeGen &gen); -void emitAddressingMode(unsigned base, RegValue disp, +void emitAddressingMode(unsigned base, Dyninst::RegValue disp, unsigned reg_opcode, codeGen &gen); @@ -191,7 +192,7 @@ void emitMovImmToReg(RealRegister dest, int imm, codeGen &gen); void emitMovImmToRM(RealRegister base, int disp, int imm, codeGen &gen); void emitMovRegToRM(RealRegister base, int disp, RealRegister src, codeGen &gen); void emitMovRMToReg(RealRegister dest, RealRegister base, int disp, codeGen &gen); -void emitMovImmToMem(Address maddr, int imm, codeGen &gen); +void emitMovImmToMem(Dyninst::Address maddr, int imm, codeGen &gen); void emitPushImm(unsigned int imm, codeGen &gen); void emitSaveO(codeGen &gen); void emitRestoreO(codeGen &gen); @@ -202,10 +203,10 @@ void emitSubRegReg(RealRegister dest, RealRegister src, codeGen &gen); void emitSHL(RealRegister dest, unsigned char pos, codeGen &gen); void restoreGPRtoGPR(RealRegister reg, RealRegister dest, codeGen &gen); -Register restoreGPRtoReg(RealRegister reg, codeGen &gen, RealRegister *dest_to_use = NULL); +Dyninst::Register restoreGPRtoReg(RealRegister reg, codeGen &gen, RealRegister *dest_to_use = NULL); void emitLEA(RealRegister base, RealRegister index, unsigned int scale, - RegValue disp, RealRegister dest, codeGen &gen); + Dyninst::RegValue disp, RealRegister dest, codeGen &gen); bool emitPush(RealRegister reg, codeGen &gen); bool emitPop(RealRegister reg, codeGen &gen); @@ -216,7 +217,7 @@ void emitJccR8(int condition_code, char jump_offset, codeGen &gen); void emitJcc(int condition, int offset, codeGen &gen, bool willRegen=true); void emitPushImm(unsigned int imm, codeGen &gen); -void emitAddMemImm32(Address dest, int imm, codeGen &gen); +void emitAddMemImm32(Dyninst::Address dest, int imm, codeGen &gen); void emitCallRel32(unsigned disp32, codeGen &gen); void emitJmpMC(int condition, int offset, codeGen &gen); @@ -237,7 +238,7 @@ struct stackItem { reg_item, stacktop, framebase - } item; + } item{}; RealRegister reg; stackItem(stackItem_t i) { assert(i != reg_item); item = i; } stackItem(RealRegister r) { item = reg_item; reg = r; } diff --git a/dyninstAPI/src/inst.C b/dyninstAPI/src/inst.C index bf9fdf688a..0d2d191022 100644 --- a/dyninstAPI/src/inst.C +++ b/dyninstAPI/src/inst.C @@ -32,6 +32,7 @@ // Code to install and remove instrumentation from a running process. // Misc constructs. +#include #include #include "dyninstAPI/src/image.h" #include "dyninstAPI/src/inst.h" @@ -76,8 +77,8 @@ unsigned findTags(const std::string ) { } unsigned generateAndWriteBranch(AddressSpace *proc, - Address fromAddr, - Address newAddr, + Dyninst::Address fromAddr, + Dyninst::Address newAddr, unsigned fillSize) { assert(fillSize != 0); diff --git a/dyninstAPI/src/inst.h b/dyninstAPI/src/inst.h index be9875161b..47ceeb25dd 100644 --- a/dyninstAPI/src/inst.h +++ b/dyninstAPI/src/inst.h @@ -34,16 +34,18 @@ #define INST_HDR #include +#include +#include #include #include "opcode.h" // enum opCode now defined here. -#include "common/src/Types.h" +#include "dyn_register.h" #include "codegen.h" // codeBufIndex_t #include "dyninstAPI/src/ast.h" // astNodePtr namespace Dyninst { namespace PatchAPI { class Instance; - typedef boost::shared_ptr InstancePtr; + typedef dyncompat::shared_ptr InstancePtr; } } @@ -155,7 +157,7 @@ unsigned getPrimitiveCost(const std::string &name); * Generate an instruction. * Previously this was handled by the polymorphic "emit" function, which * took a variety of argument types and variously returned either an - * Address or a Register or nothing of value. The following family of + * Dyninst::Address or a Dyninst::Register or nothing of value. The following family of * functions replace "emit" with more strongly typed versions. */ @@ -167,47 +169,47 @@ typedef enum gnenum { // The return value is a magic "hand this in when we update" black box; // emitA handles emission of things like ifs that need to be updated later. -codeBufIndex_t emitA(opCode op, Register src1, Register src2, long dst, +codeBufIndex_t emitA(opCode op, Dyninst::Register src1, Dyninst::Register src2, long dst, codeGen &gen, RegControl rc, bool noCost); -// for operations requiring a Register to be returned +// for operations requiring a Dyninst::Register to be returned // (e.g., getRetValOp, getRetAddrOp, getParamOp, getSysRetValOp, getSysParamOp) -Register emitR(opCode op, Register src1, Register src2, Register dst, +Dyninst::Register emitR(opCode op, Dyninst::Register src1, Dyninst::Register src2, Dyninst::Register dst, codeGen &gen, bool noCost, const instPoint *location, bool for_multithreaded); // for general arithmetic and logic operations which return nothing -void emitV(opCode op, Register src1, Register src2, Register dst, +void emitV(opCode op, Dyninst::Register src1, Dyninst::Register src2, Dyninst::Register dst, codeGen &gen, bool noCost, registerSpace *rs = NULL, int size = 4, const instPoint * location = NULL, AddressSpace * proc = NULL, bool s = true); -// for loadOp and loadConstOp (reading from an Address) -void emitVload(opCode op, Address src1, Register src2, Register dst, +// for loadOp and loadConstOp (reading from an Dyninst::Address) +void emitVload(opCode op, Dyninst::Address src1, Dyninst::Register src2, Dyninst::Register dst, codeGen &gen, bool noCost, registerSpace *rs = NULL, int size = 4, const instPoint * location = NULL, AddressSpace * proc = NULL); -// for storeOp (writing to an Address) -void emitVstore(opCode op, Register src1, Register src2, Address dst, +// for storeOp (writing to an Dyninst::Address) +void emitVstore(opCode op, Dyninst::Register src1, Dyninst::Register src2, Dyninst::Address dst, codeGen &gen, bool noCost, registerSpace *rs = NULL, int size = 4, const instPoint * location = NULL, AddressSpace * proc = NULL); -// for loadOp and loadConstOp (reading from an Address) -void emitVload(opCode op, const image_variable* src1, Register src2, Register dst, +// for loadOp and loadConstOp (reading from an Dyninst::Address) +void emitVload(opCode op, const image_variable* src1, Dyninst::Register src2, Dyninst::Register dst, codeGen &gen, bool noCost, registerSpace *rs = NULL, int size = 4, const instPoint * location = NULL, AddressSpace * proc = NULL); -// for storeOp (writing to an Address) -void emitVstore(opCode op, Register src1, Register src2, const image_variable* dst, +// for storeOp (writing to an Dyninst::Address) +void emitVstore(opCode op, Dyninst::Register src1, Dyninst::Register src2, const image_variable* dst, codeGen &gen, bool noCost, registerSpace *rs = NULL, int size = 4, const instPoint * location = NULL, AddressSpace * proc = NULL); // and the retyped original emitImm companion -void emitImm(opCode op, Register src, RegValue src2imm, Register dst, +void emitImm(opCode op, Dyninst::Register src, Dyninst::RegValue src2imm, Dyninst::Register dst, codeGen &gen, bool noCost, registerSpace *rs = NULL, bool s = true); @@ -220,21 +222,21 @@ typedef BPatch_addrSpec_NP BPatch_countSpec_NP; void emitJmpMC(int condition, int offset, codeGen &gen); -void emitASload(const BPatch_addrSpec_NP *as, Register dest, int stackShift, codeGen &gen, bool noCost); +void emitASload(const BPatch_addrSpec_NP *as, Dyninst::Register dest, int stackShift, codeGen &gen, bool noCost); -void emitCSload(const BPatch_countSpec_NP *as, Register dest, codeGen &gen, bool noCost); +void emitCSload(const BPatch_countSpec_NP *as, Dyninst::Register dest, codeGen &gen, bool noCost); // VG(11/06/01): moved here and added location -Register emitFuncCall(opCode op, codeGen &gen, +Dyninst::Register emitFuncCall(opCode op, codeGen &gen, std::vector &operands, bool noCost, func_instance *func); // Obsolete version that uses an address. DON'T USE THIS or expect it to survive. -Register emitFuncCall(opCode op, codeGen &gen, +Dyninst::Register emitFuncCall(opCode op, codeGen &gen, std::vector &operands, bool noCost, - Address callee_addr_); + Dyninst::Address callee_addr_); int getInsnCost(opCode t); @@ -242,7 +244,7 @@ int getInsnCost(opCode t); * get the requested parameter into a register. * */ -Register getParameter(Register dest, int param); +Dyninst::Register getParameter(Dyninst::Register dest, int param); extern std::string getProcessStatus(const AddressSpace *p); @@ -250,23 +252,23 @@ extern std::string getProcessStatus(const AddressSpace *p); // expects the symbol name advanced past the underscore extern unsigned findTags(const std::string funcName); -extern Address getMaxBranch(); +extern Dyninst::Address getMaxBranch(); // find these internal functions before finding any other functions // extern std::unordered_map tagDict; extern std::map primitiveCosts; -bool writeFunctionPtr(AddressSpace *p, Address addr, func_instance *f); +bool writeFunctionPtr(AddressSpace *p, Dyninst::Address addr, func_instance *f); /** * A set of optimized emiters for common idioms. Return * false if the platform can't perform any optimizations. **/ //Store constant in memory at address -bool emitStoreConst(Address addr, int imm, codeGen &gen, bool noCost); +bool emitStoreConst(Dyninst::Address addr, int imm, codeGen &gen, bool noCost); //Add constant to memory at address -bool emitAddSignedImm(Address addr, long int imm, codeGen &gen, bool noCost); +bool emitAddSignedImm(Dyninst::Address addr, long int imm, codeGen &gen, bool noCost); //Subtract constant from memory at address -bool emitSubSignedImm(Address addr, long int imm, codeGen &gen, bool noCost); +bool emitSubSignedImm(Dyninst::Address addr, long int imm, codeGen &gen, bool noCost); #endif diff --git a/dyninstAPI/src/instPoint.C b/dyninstAPI/src/instPoint.C index 3cc2efa9e1..e7a2d3a419 100644 --- a/dyninstAPI/src/instPoint.C +++ b/dyninstAPI/src/instPoint.C @@ -32,6 +32,7 @@ // instPoint code +#include #include #include "dyninstAPI/src/image.h" #include "dyninstAPI/src/inst.h" diff --git a/dyninstAPI/src/instPoint.h b/dyninstAPI/src/instPoint.h index 0e568cbe9c..b513ded66f 100644 --- a/dyninstAPI/src/instPoint.h +++ b/dyninstAPI/src/instPoint.h @@ -34,8 +34,9 @@ #ifndef _INST_POINT_H_ #define _INST_POINT_H_ +#include +#include #include -#include "common/src/Types.h" #include "dyninstAPI/src/inst.h" #include "common/src/arch.h" // instruction #include "dyninstAPI/src/codeRange.h" diff --git a/dyninstAPI/src/linux-aarch64.C b/dyninstAPI/src/linux-aarch64.C index c052e151c9..8529250d32 100644 --- a/dyninstAPI/src/linux-aarch64.C +++ b/dyninstAPI/src/linux-aarch64.C @@ -51,12 +51,12 @@ const char DL_OPEN_FUNC_INTERNAL[] = "_dl_open"; const char DL_OPEN_FUNC_NAME[] = "do_dlopen"; const char DL_OPEN_LIBC_FUNC_EXPORTED[] = "__libc_dlopen_mode"; -Address PCProcess::getLibcStartMainParam(PCThread *) { +Dyninst::Address PCProcess::getLibcStartMainParam(PCThread *) { assert(!"This function is unimplemented"); return 0; } -Address PCProcess::getTOCoffsetInfo(Address dest) { +Dyninst::Address PCProcess::getTOCoffsetInfo(Dyninst::Address dest) { if ( getAddressWidth() == 4 ) return 0; // We have an address, and want to find the module the addr is @@ -69,14 +69,14 @@ Address PCProcess::getTOCoffsetInfo(Address dest) { // Very odd case if this is not defined. assert(mobj); - Address TOCOffset = mobj->parse_img()->getObject()->getTOCoffset(); + Dyninst::Address TOCOffset = mobj->parse_img()->getObject()->getTOCoffset(); if (!TOCOffset) return 0; return TOCOffset + mobj->dataBase(); } -Address PCProcess::getTOCoffsetInfo(func_instance *func) { +Dyninst::Address PCProcess::getTOCoffsetInfo(func_instance *func) { if ( getAddressWidth() == 4 ) return 0; mapped_object *mobj = func->obj(); @@ -84,7 +84,7 @@ Address PCProcess::getTOCoffsetInfo(func_instance *func) { return mobj->parse_img()->getObject()->getTOCoffset() + mobj->dataBase(); } -bool PCProcess::getOPDFunctionAddr(Address &) { +bool PCProcess::getOPDFunctionAddr(Dyninst::Address &) { return true; } @@ -93,8 +93,8 @@ AstNodePtr PCProcess::createUnprotectStackAST() { return AstNode::nullNode(); } -bool Frame::setPC(Address newpc) { - Address pcAddr = getPClocation(); +bool Frame::setPC(Dyninst::Address newpc) { + Dyninst::Address pcAddr = getPClocation(); if (!pcAddr) { //fprintf(stderr, "[%s:%u] - Frame::setPC aborted", __FILE__, __LINE__); @@ -189,8 +189,8 @@ bool AddressSpace::getDyninstRTLibName() { // floor of inferior malloc address range within a single branch of x // for 32-bit ELF PowerPC mutatees -Address region_lo(const Address x) { - const Address floor = getpagesize(); +Dyninst::Address region_lo(const Dyninst::Address x) { + const Dyninst::Address floor = getpagesize(); assert(x >= floor); @@ -203,8 +203,8 @@ Address region_lo(const Address x) { // floor of inferior malloc address range within a single branch of x // for 64-bit ELF PowerPC mutatees -Address region_lo_64(const Address x) { - const Address floor = getpagesize(); +Dyninst::Address region_lo_64(const Dyninst::Address x) { + const Dyninst::Address floor = getpagesize(); assert(x >= floor); @@ -217,8 +217,8 @@ Address region_lo_64(const Address x) { // ceiling of inferior malloc address range within a single branch of x // for 32-bit ELF PowerPC mutatees -Address region_hi(const Address x) { - const Address ceiling = ~(Address)0 & 0xffffffff; +Dyninst::Address region_hi(const Dyninst::Address x) { + const Dyninst::Address ceiling = ~(Dyninst::Address)0 & 0xffffffff; assert(x < ceiling); @@ -231,8 +231,8 @@ Address region_hi(const Address x) { // ceiling of inferior malloc address range within a single branch of x // for 64-bit ELF PowerPC mutatees -Address region_hi_64(const Address x) { - const Address ceiling = ~(Address)0; +Dyninst::Address region_hi_64(const Dyninst::Address x) { + const Dyninst::Address ceiling = ~(Dyninst::Address)0; assert(x < ceiling); diff --git a/dyninstAPI/src/linux-aarch64.h b/dyninstAPI/src/linux-aarch64.h index 4a6e114604..efbfe13367 100644 --- a/dyninstAPI/src/linux-aarch64.h +++ b/dyninstAPI/src/linux-aarch64.h @@ -36,22 +36,22 @@ #ifndef LINUX_AARCH64_HDR #define LINUX_AARCH64_HDR -#include "common/src/Types.h" +#include "dyntypes.h" // floor of inferior malloc address range within a single branch of x // for 32-bit ELF PowerPC mutatees -extern Address region_lo(const Address x); +extern Dyninst::Address region_lo(const Dyninst::Address x); // floor of inferior malloc address range within a single branch of x // for 64-bit ELF PowerPC mutatees -extern Address region_lo_64(const Address x); +extern Dyninst::Address region_lo_64(const Dyninst::Address x); // ceiling of inferior malloc address range within a single branch of x // for 32-bit ELF PowerPC mutatees -extern Address region_hi(const Address x); +extern Dyninst::Address region_hi(const Dyninst::Address x); // ceiling of inferior malloc address range within a single branch of x // for 64-bit ELF PowerPC mutatees -extern Address region_hi_64(const Address x); +extern Dyninst::Address region_hi_64(const Dyninst::Address x); #endif diff --git a/dyninstAPI/src/linux-power.C b/dyninstAPI/src/linux-power.C index 5a1a4cccc6..e6898173fd 100644 --- a/dyninstAPI/src/linux-power.C +++ b/dyninstAPI/src/linux-power.C @@ -51,12 +51,12 @@ const char DL_OPEN_FUNC_INTERNAL[] = "_dl_open"; const char DL_OPEN_FUNC_NAME[] = "do_dlopen"; const char DL_OPEN_LIBC_FUNC_EXPORTED[] = "__libc_dlopen_mode"; -Address PCProcess::getLibcStartMainParam(PCThread *) { +Dyninst::Address PCProcess::getLibcStartMainParam(PCThread *) { assert(!"This function is unimplemented"); return 0; } -Address PCProcess::getTOCoffsetInfo(Address dest) { +Dyninst::Address PCProcess::getTOCoffsetInfo(Dyninst::Address dest) { if ( getAddressWidth() == 4 ) return 0; // We have an address, and want to find the module the addr is @@ -69,14 +69,14 @@ Address PCProcess::getTOCoffsetInfo(Address dest) { // Very odd case if this is not defined. assert(mobj); - Address TOCOffset = mobj->parse_img()->getObject()->getTOCoffset(); + Dyninst::Address TOCOffset = mobj->parse_img()->getObject()->getTOCoffset(); if (!TOCOffset) return 0; return TOCOffset + mobj->dataBase(); } -Address PCProcess::getTOCoffsetInfo(func_instance *func) { +Dyninst::Address PCProcess::getTOCoffsetInfo(func_instance *func) { if ( getAddressWidth() == 4 ) return 0; mapped_object *mobj = func->obj(); @@ -84,10 +84,10 @@ Address PCProcess::getTOCoffsetInfo(func_instance *func) { return mobj->parse_img()->getObject()->getTOCoffset() + mobj->dataBase(); } -bool PCProcess::getOPDFunctionAddr(Address &addr) { +bool PCProcess::getOPDFunctionAddr(Dyninst::Address &addr) { bool result = true; if( getAddressWidth() == 8 ) { - Address resultAddr = 0; + Dyninst::Address resultAddr = 0; if( !readDataSpace((const void *)addr, getAddressWidth(), (void *)&resultAddr, false) ) { @@ -104,8 +104,8 @@ AstNodePtr PCProcess::createUnprotectStackAST() { return AstNode::nullNode(); } -bool Frame::setPC(Address newpc) { - Address pcAddr = getPClocation(); +bool Frame::setPC(Dyninst::Address newpc) { + Dyninst::Address pcAddr = getPClocation(); if (!pcAddr) { //fprintf(stderr, "[%s:%u] - Frame::setPC aborted", __FILE__, __LINE__); @@ -200,8 +200,8 @@ bool AddressSpace::getDyninstRTLibName() { // floor of inferior malloc address range within a single branch of x // for 32-bit ELF PowerPC mutatees -Address region_lo(const Address x) { - const Address floor = getpagesize(); +Dyninst::Address region_lo(const Dyninst::Address x) { + const Dyninst::Address floor = getpagesize(); assert(x >= floor); @@ -214,8 +214,8 @@ Address region_lo(const Address x) { // floor of inferior malloc address range within a single branch of x // for 64-bit ELF PowerPC mutatees -Address region_lo_64(const Address x) { - const Address floor = getpagesize(); +Dyninst::Address region_lo_64(const Dyninst::Address x) { + const Dyninst::Address floor = getpagesize(); assert(x >= floor); @@ -228,8 +228,8 @@ Address region_lo_64(const Address x) { // ceiling of inferior malloc address range within a single branch of x // for 32-bit ELF PowerPC mutatees -Address region_hi(const Address x) { - const Address ceiling = ~(Address)0 & 0xffffffff; +Dyninst::Address region_hi(const Dyninst::Address x) { + const Dyninst::Address ceiling = ~(Dyninst::Address)0 & 0xffffffff; assert(x < ceiling); @@ -242,8 +242,8 @@ Address region_hi(const Address x) { // ceiling of inferior malloc address range within a single branch of x // for 64-bit ELF PowerPC mutatees -Address region_hi_64(const Address x) { - const Address ceiling = ~(Address)0; +Dyninst::Address region_hi_64(const Dyninst::Address x) { + const Dyninst::Address ceiling = ~(Dyninst::Address)0; assert(x < ceiling); diff --git a/dyninstAPI/src/linux-power.h b/dyninstAPI/src/linux-power.h index 840f91e911..b7f2f0e718 100644 --- a/dyninstAPI/src/linux-power.h +++ b/dyninstAPI/src/linux-power.h @@ -37,22 +37,22 @@ #ifndef LINUX_POWER_HDR #define LINUX_POWER_HDR -#include "common/src/Types.h" +#include "dyntypes.h" // floor of inferior malloc address range within a single branch of x // for 32-bit ELF PowerPC mutatees -extern Address region_lo(const Address x); +extern Dyninst::Address region_lo(const Dyninst::Address x); // floor of inferior malloc address range within a single branch of x // for 64-bit ELF PowerPC mutatees -extern Address region_lo_64(const Address x); +extern Dyninst::Address region_lo_64(const Dyninst::Address x); // ceiling of inferior malloc address range within a single branch of x // for 32-bit ELF PowerPC mutatees -extern Address region_hi(const Address x); +extern Dyninst::Address region_hi(const Dyninst::Address x); // ceiling of inferior malloc address range within a single branch of x // for 64-bit ELF PowerPC mutatees -extern Address region_hi_64(const Address x); +extern Dyninst::Address region_hi_64(const Dyninst::Address x); #endif diff --git a/dyninstAPI/src/linux-x86.C b/dyninstAPI/src/linux-x86.C index ccfb24c967..c0ec1ee130 100644 --- a/dyninstAPI/src/linux-x86.C +++ b/dyninstAPI/src/linux-x86.C @@ -49,13 +49,13 @@ #include "common/src/headers.h" #include "dyninstAPI/src/os.h" #include "common/src/stats.h" -#include "common/src/Types.h" #include "dyninstAPI/src/debug.h" #include "dyninstAPI/src/util.h" // getCurrWallTime #include "common/src/pathName.h" #include "dyninstAPI/src/inst-x86.h" #include "dyninstAPI/src/emit-x86.h" - +#include "registers/x86_regs.h" +#include "registers/x86_64_regs.h" #include "dyninstAPI/src/mapped_object.h" #include "dyninstAPI/src/linux.h" @@ -175,10 +175,10 @@ AstNodePtr PCProcess::createUnprotectStackAST() { func_instance *mprot = funcs[0]; std::vector args; - args.push_back(AstNode::operandNode(AstNode::Constant, (void *)page_start)); - args.push_back(AstNode::operandNode(AstNode::Constant, (void *)(intptr_t)size)); + args.push_back(AstNode::operandNode(AstNode::operandType::Constant, (void *)page_start)); + args.push_back(AstNode::operandNode(AstNode::operandType::Constant, (void *)(intptr_t)size)); // prot = READ|WRITE|EXECUTE - args.push_back(AstNode::operandNode(AstNode::Constant, (void *)7)); + args.push_back(AstNode::operandNode(AstNode::operandType::Constant, (void *)7)); return AstNode::funcCallNode(mprot, args); } diff --git a/dyninstAPI/src/linux.C b/dyninstAPI/src/linux.C index 164bedb536..270eef7d33 100644 --- a/dyninstAPI/src/linux.C +++ b/dyninstAPI/src/linux.C @@ -30,6 +30,7 @@ // $Id: linux.C,v 1.279 2008/09/03 06:08:44 jaw Exp $ +#include #include "binaryEdit.h" #include "dynProcess.h" #include "image.h" @@ -43,7 +44,13 @@ #include "linux.h" #include -#include "boost/shared_ptr.hpp" +#include +#include +#include +#include +#include + +#include "dyncompat/shared_ptr.hpp" #include "pcEventMuxer.h" @@ -174,40 +181,84 @@ bool PCEventMuxer::useCallback(Dyninst::ProcControlAPI::EventType et) return false; } -bool BinaryEdit::getResolvedLibraryPath(const string &filename, std::vector &paths) { - char *libPathStr, *libPath; - std::vector libPaths; - struct stat dummy; - char buffer[512]; - char *pos, *key, *val; +namespace +{ +template , + typename PredicateT = std::string (*)(const std::string&)> +inline ContainerT +delimit( + const std::string& line, const std::string& delimiters = ":", + PredicateT&& predicate = [](const std::string& s) -> std::string { return s; }) +{ + size_t _beginp = 0; // position that is the beginning of the new string + size_t _delimp = 0; // position of the delimiter in the string + ContainerT _result = {}; + while(_beginp < line.length() && _delimp < line.length()) + { + // find the first character (starting at _delimp) that is not a delimiter + _beginp = line.find_first_not_of(delimiters, _delimp); + // if no a character after or at _end that is not a delimiter is not found + // then we are done + if(_beginp == std::string::npos) + break; + // starting at the position of the new string, find the next delimiter + _delimp = line.find_first_of(delimiters, _beginp); + std::string _tmp{}; + try + { + // starting at the position of the new string, get the characters + // between this position and the next delimiter + if(_beginp < line.length()) + _tmp = line.substr(_beginp, _delimp - _beginp); + } catch(std::exception& e) + { + // print the exception but don't fail, unless maybe it should? + fprintf(stderr, "[%s:%i] %s (delimiters: %s) :: %s\n", __FILE__, __LINE__, + line.c_str(), delimiters.c_str(), e.what()); + } + // don't add empty strings + if(!_tmp.empty()) + { + _result.emplace_back(std::forward(predicate)(_tmp)); + } + } + return _result; +} +} // namespace + +bool +BinaryEdit::getResolvedLibraryPath(const string& filename, std::vector& paths) +{ + auto _path_exists = [](const std::string& _filename) { + struct stat dummy; + return (_filename.empty()) ? false : (stat(_filename.c_str(), &dummy) == 0); + }; + + auto _emplace_if_exists = [&paths, filename, + _path_exists](const std::string& _directory) { + auto _filename = _directory + "/" + filename; + if(_path_exists(_filename)) + paths.emplace_back(std::move(_filename)); + }; // prefer qualified file paths - if (stat(filename.c_str(), &dummy) == 0) { - paths.push_back(filename); - } + if(_path_exists(filename)) + paths.emplace_back(filename); // For cross-rewriting - char *dyn_path = getenv("DYNINST_REWRITER_PATHS"); - if (dyn_path) { - libPathStr = strdup(dyn_path); - libPath = strtok(libPathStr, ":"); - while (libPath != NULL) { - libPaths.push_back(string(libPath)); - libPath = strtok(NULL, ":"); - } - free(libPathStr); + char* dyn_path = getenv("DYNINST_REWRITER_PATHS"); + if(dyn_path) + { + for(const auto& itr : delimit(dyn_path, ":")) + _emplace_if_exists(itr); } // search paths from environment variables - char *ld_path = getenv("LD_LIBRARY_PATH"); - if (ld_path) { - libPathStr = strdup(ld_path); - libPath = strtok(libPathStr, ":"); - while (libPath != NULL) { - libPaths.push_back(string(libPath)); - libPath = strtok(NULL, ":"); - } - free(libPathStr); + char* ld_path = getenv("LD_LIBRARY_PATH"); + if(ld_path) + { + for(const auto& itr : delimit(ld_path, ":")) + _emplace_if_exists(itr); } #ifdef DYNINST_COMPILER_SEARCH_DIRS @@ -215,77 +266,82 @@ bool BinaryEdit::getResolvedLibraryPath(const string &filename, std::vector (...) => + // example: + // libz.so (libc6,x86-64) => /lib/x86_64-linux-gnu/libz.so + auto _get_entry = [](const std::string& _inp) { + auto _paren_pos = _inp.find('('); + auto _arrow_pos = _inp.find("=>", _paren_pos); + if(_arrow_pos == std::string::npos || _paren_pos == std::string::npos) + return std::string{}; + if(_arrow_pos + 2 < _inp.length()) + { + auto _pos = _inp.find_first_not_of(" \t", _arrow_pos + 2); + if(_pos < _inp.length()) + return _inp.substr(_pos); + } + return std::string{}; + }; + + auto _data = std::stringstream{}; + while(fgets(buffer, buffer_size, ldconfig) != nullptr) + { + _data << buffer; + auto _len = strnlen(buffer, buffer_size); + if(_len > 0 && buffer[_len - 1] == '\n') + { + auto _v = _data.str(); + if(!_v.empty()) + { + _v = _v.substr(_v.find_first_not_of(" \t")); + if(_v.length() > 1) + { + auto _entry = _get_entry(_v.substr(0, _v.length() - 1)); + if(!_entry.empty()) + _emplace_if_exists(_entry); + } + } + _data = std::stringstream{}; + } } } pclose(ldconfig); } // search hard-coded system paths - libPaths.clear(); - libPaths.push_back("/usr/local/lib"); - libPaths.push_back("/usr/share/lib"); - libPaths.push_back("/usr/lib"); - libPaths.push_back("/usr/lib64"); - libPaths.push_back("/usr/lib/x86_64-linux-gnu"); - libPaths.push_back("/lib"); - libPaths.push_back("/lib64"); - libPaths.push_back("/lib/x86_64-linux-gnu"); - libPaths.push_back("/usr/lib/i386-linux-gnu"); - libPaths.push_back("/usr/lib32"); - for (unsigned int i = 0; i < libPaths.size(); i++) { - string str = libPaths[i] + "/" + filename; - if (stat(str.c_str(), &dummy) == 0) { - paths.push_back(str); - } + for(const char* itr : + { "/usr/local/lib", "/usr/share/lib", "/usr/lib", "/usr/lib64", + "/usr/lib/x86_64-linux-gnu", "/lib", "/lib64", "/lib/x86_64-linux-gnu", + "/usr/lib/i386-linux-gnu", "/usr/lib32" }) + { + _emplace_if_exists(itr); } - return ( 0 < paths.size() ); + return (!paths.empty()); } bool BinaryEdit::archSpecificMultithreadCapable() { diff --git a/dyninstAPI/src/linux.h b/dyninstAPI/src/linux.h index 0f81d082f0..f1e9f0b07f 100644 --- a/dyninstAPI/src/linux.h +++ b/dyninstAPI/src/linux.h @@ -38,7 +38,6 @@ #define LINUX_PD_HDR class PCProcess; -#include "common/src/Types.h" #include "common/src/linuxKludges.h" #include "symtabAPI/h/Symtab.h" #include "symtabAPI/h/Archive.h" diff --git a/dyninstAPI/src/mapped_module.C b/dyninstAPI/src/mapped_module.C index d884f26e01..abe4e3672f 100644 --- a/dyninstAPI/src/mapped_module.C +++ b/dyninstAPI/src/mapped_module.C @@ -30,6 +30,7 @@ // $Id: mapped_module.C,v 1.29 2008/06/19 19:53:30 legendre Exp $ +#include #include "dyninstAPI/src/mapped_module.h" #include "dyninstAPI/src/mapped_object.h" #include "dyninstAPI/src/image.h" @@ -40,8 +41,6 @@ #include #include -bool mapped_module::truncateLineFilenames = true; - const std::vector &mapped_module::getAllFunctions() { std::vector pdfuncs; @@ -102,14 +101,9 @@ void mapped_module::remove(func_instance *func) assert(0 && "Tried to remove function that's not in the module"); } -const string &mapped_module::fileName() const -{ - return pmod()->fileName(); -} - -const string &mapped_module::fullName() const +const string &mapped_module::fileName() const { - return pmod()->fullName(); + return pmod()->fileName(); } mapped_object *mapped_module::obj() const diff --git a/dyninstAPI/src/mapped_module.h b/dyninstAPI/src/mapped_module.h index cc883f4f91..db3e339a3f 100644 --- a/dyninstAPI/src/mapped_module.h +++ b/dyninstAPI/src/mapped_module.h @@ -44,7 +44,8 @@ class pdmodule; class image; #include -#include "common/src/Types.h" +#include +#include #include "dyninstAPI/src/image.h" #include "symtabAPI/h/Symtab.h" @@ -66,7 +67,6 @@ class mapped_module { pdmodule *pmod() const; const string &fileName() const; - const string &fullName() const; AddressSpace *proc() const; @@ -103,20 +103,12 @@ class mapped_module { std::string processDirectories(const std::string &fn) const; - // Given a line in the module, get the set of addresses that it maps - // to. Calls the internal getAddrFromLine and then adds the base - // address to the returned list of offsets. - bool getAddrFromLine(unsigned lineNum, - std::vector
&addresses, - bool exactMatch); - void addFunction(func_instance *func); void addVariable(int_variable *var); int_variable* createVariable(std::string name, Address offset, int size); void remove(func_instance *func); - static bool truncateLineFilenames; unsigned int getFuncVectorSize() { return everyUniqueFunction.size(); } private: diff --git a/dyninstAPI/src/mapped_object.C b/dyninstAPI/src/mapped_object.C index b6d99e8826..18f2cc7dbc 100644 --- a/dyninstAPI/src/mapped_object.C +++ b/dyninstAPI/src/mapped_object.C @@ -46,8 +46,7 @@ #include "InstructionDecoder.h" #include "Parsing.h" #include "instPoint.h" -#include "MemoryEmulator/memEmulator.h" -#include +#include #include "BPatch_image.h" #include "PatchCFG.h" #include "PCProcess.h" @@ -350,10 +349,8 @@ mapped_module *mapped_object::findModule(string m_name, bool wildcard) std::string tmp = m_name.c_str(); for (unsigned i = 0; i < everyModule.size(); i++) { if (everyModule[i]->fileName() == m_name || - everyModule[i]->fullName() == m_name || (wildcard && - (wildcardEquiv(tmp, everyModule[i]->fileName()) || - wildcardEquiv(tmp, everyModule[i]->fullName())))) { + (wildcardEquiv(tmp, everyModule[i]->fileName())))) { //parsing_printf("... found!\n"); return everyModule[i]; } @@ -426,7 +423,7 @@ void mapped_object::set_short_name() { const std::vector *mapped_object::findFuncVectorByPretty(const std::string &funcname) { - if (funcname.c_str() == 0) return NULL; + if (funcname.empty()) return NULL; // First, check the underlying image. const std::vector *img_funcs = parse_img()->findFuncVectorByPretty(funcname); if (img_funcs == NULL) { @@ -436,7 +433,7 @@ const std::vector *mapped_object::findFuncVectorByPretty(const assert(img_funcs->size()); // Fast path: auto iter = allFunctionsByPrettyName.find(funcname); - if (iter != allFunctionsByPrettyName.end()) { + if (iter != allFunctionsByPrettyName.end() && iter->second != nullptr) { // Okay, we've pulled in some of the functions before (this can happen as a // side effect of adding functions). But did we get them all? std::vector *map_funcs = iter->second; @@ -461,7 +458,7 @@ const std::vector *mapped_object::findFuncVectorByPretty(const const std::vector *mapped_object::findFuncVectorByMangled(const std::string &funcname) { - if (funcname.c_str() == 0) return NULL; + if (funcname.empty()) return NULL; // First, check the underlying image. const std::vector *img_funcs = parse_img()->findFuncVectorByMangled(funcname); @@ -472,7 +469,7 @@ const std::vector *mapped_object::findFuncVectorByMangled(cons assert(img_funcs->size()); // Fast path: auto iter = allFunctionsByMangledName.find(funcname); - if (iter != allFunctionsByMangledName.end()) { + if (iter != allFunctionsByMangledName.end() && iter->second != nullptr) { // Okay, we've pulled in some of the functions before (this can happen as a // side effect of adding functions). But did we get them all? std::vector *map_funcs = iter->second; @@ -498,7 +495,7 @@ const std::vector *mapped_object::findFuncVectorByMangled(cons const std::vector *mapped_object::findVarVectorByPretty(const std::string &varname) { - if (varname.c_str() == 0) return NULL; + if (varname.empty()) return NULL; // First, check the underlying image. const std::vector *img_vars = parse_img()->findVarVectorByPretty(varname); @@ -507,7 +504,7 @@ const std::vector *mapped_object::findVarVectorByPretty(const st assert(img_vars->size()); // Fast path: auto iter = allVarsByPrettyName.find(varname); - if (iter != allVarsByPrettyName.end()) { + if (iter != allVarsByPrettyName.end() && iter->second != nullptr) { // Okay, we've pulled in some of the variabletions before (this can happen as a // side effect of adding variabletions). But did we get them all? std::vector *map_variables = iter->second; @@ -532,7 +529,7 @@ const std::vector *mapped_object::findVarVectorByPretty(const st const std::vector *mapped_object::findVarVectorByMangled(const std::string &varname) { - if (varname.c_str() == 0) return NULL; + if (varname.empty()) return NULL; // First, check the underlying image. const std::vector *img_vars = parse_img()->findVarVectorByMangled(varname); @@ -542,7 +539,7 @@ const std::vector *mapped_object::findVarVectorByMangled(const // Fast path: auto iter = allVarsByMangledName.find(varname); - if (iter != allVarsByMangledName.end()) { + if (iter != allVarsByMangledName.end() && iter->second != nullptr) { // Okay, we've pulled in some of the variabletions before (this can happen as a // side effect of adding variables). But did we get them all? std::vector *map_variables = iter->second; @@ -1040,9 +1037,6 @@ mapped_module *mapped_object::getOrCreateForkedModule(mapped_module *parMod) mapped_module* mapped_object::getDefaultModule() { - mapped_module* ret = findModule("DEFAULT_MODULE"); - if(ret) return ret; - // Make sure the everyModule vector is initialized getModules(); @@ -1327,11 +1321,6 @@ void mapped_object::expandCodeBytes(SymtabAPI::Region *reg) // 1. copy memory into regBuf Address readAddr = regStart + codeBase(); - if (proc()->isMemoryEmulated()) { - bool valid = false; - boost::tie(valid, readAddr) = proc()->getMemEm()->translate(readAddr); - assert(valid); - } if (!proc()->readDataSpace((void*)readAddr, copySize, regBuf, @@ -1344,8 +1333,6 @@ void mapped_object::expandCodeBytes(SymtabAPI::Region *reg) mal_printf("EXTEND_CB: copied to [%lx %lx)\n", codeBase()+regStart, codeBase()+regStart+copySize); - if ( ! proc()->isMemoryEmulated() ) { - // 2. copy code bytes back into the regBuf to wipe out instrumentation // and set regBuf to be the data for the region @@ -1378,7 +1365,6 @@ void mapped_object::expandCodeBytes(SymtabAPI::Region *reg) } mal_printf("Expand region: %lx blocks copied back into mapped file\n", analyzedBlocks.size()); - } if (reg->isDirty()) { // if isDirty is true, the pointer was created via malloc @@ -1410,7 +1396,6 @@ void mapped_object::expandCodeBytes(SymtabAPI::Region *reg) // 2. copy overwritten regions into the mapped objects void mapped_object::updateCodeBytes(const list > &owRanges) { - bool memEmulation = proc()->isMemoryEmulated(); // 1. use other update functions to update non-code areas of mapped files, // expanding them if we wrote in un-initialized memory using namespace SymtabAPI; @@ -1447,11 +1432,6 @@ void mapped_object::updateCodeBytes(const list > &owRanges for(rIter = owRanges.begin(); rIter != owRanges.end(); rIter++) { Address readAddr = rIter->first; - if (memEmulation) { - bool valid = false; - boost::tie(valid, readAddr) = proc()->getMemEm()->translate(readAddr); - assert(valid); - } Region *reg = parse_img()->getObject()->findEnclosingRegion ( (*rIter).first - baseAddress ); @@ -1518,11 +1498,6 @@ void mapped_object::updateCodeBytes(SymtabAPI::Region * symReg) if (prevEndAddr < curB->start()) { // update the mapped file Address readAddr = prevEndAddr + base; - if (proc()->isMemoryEmulated()) { - bool valid = false; - boost::tie(valid, readAddr) = proc()->getMemEm()->translate(readAddr); - assert(valid); - } if (!proc()->readDataSpace( (void*)readAddr, curB->start() - prevEndAddr, @@ -1550,11 +1525,6 @@ void mapped_object::updateCodeBytes(SymtabAPI::Region * symReg) // (will read in whole region if there are no ranges in the region) if (prevEndAddr < regStart + symReg->getDiskSize()) { Address readAddr = prevEndAddr + base; - if (proc()->isMemoryEmulated()) { - bool valid = false; - boost::tie(valid, readAddr) = proc()->getMemEm()->translate(readAddr); - assert(valid); - } if (!proc()->readDataSpace( (void*)readAddr, regStart + symReg->getDiskSize() - prevEndAddr, @@ -1632,12 +1602,6 @@ bool mapped_object::isUpdateNeeded(Address entry) ? comparison_size : page_size; regBuf = malloc(comparison_size); Address readAddr = entry; - if (proc()->isMemoryEmulated()) { - bool valid = false; - Address translated = 0; - boost::tie(valid, translated) = proc()->getMemEm()->translate(readAddr); - if (valid) readAddr = translated; - } // mal_printf("%s[%d] Comparing %lx bytes starting at %lx\n", // FILE__,__LINE__,comparison_size,entry); @@ -1682,11 +1646,6 @@ bool mapped_object::isExpansionNeeded(Address entry) // see if the first few bytes have been updated Address compareStart = base + reg->getMemOffset() + reg->getDiskSize(); - if (proc()->isMemoryEmulated()) { - bool valid = false; - boost::tie(valid, compareStart) = proc()->getMemEm()->translate(compareStart); - assert(valid); - } unsigned compareSize = InstructionAPI::InstructionDecoder::maxInstructionLength; Address uninitSize = reg->getMemSize() - reg->getDiskSize(); @@ -1772,10 +1731,6 @@ bool mapped_object::updateCodeBytesIfNeeded(Address entry) } void mapped_object::remove(func_instance *func) { - - if (as()->isMemoryEmulated()) { - as()->getMemEm()->removeSpringboards(func); - } // clear out module- and BPatch-level data structures BPatch_addressSpace* bpAS = (BPatch_addressSpace*)proc()->up_ptr(); @@ -1842,9 +1797,6 @@ void mapped_object::remove(instPoint *point) // does not delete void mapped_object::destroy(PatchAPI::PatchBlock *b) { calleeNames_.erase(SCAST_BI(b)); - if (as()->isMemoryEmulated()) { - as()->getMemEm()->removeSpringboards(SCAST_BI(b)); - } } // does not delete diff --git a/dyninstAPI/src/mapped_object.h b/dyninstAPI/src/mapped_object.h index 49a1c8a30e..f0c695324d 100644 --- a/dyninstAPI/src/mapped_object.h +++ b/dyninstAPI/src/mapped_object.h @@ -34,7 +34,11 @@ #define _mapped_object_h #include -#include "common/src/Types.h" +#include +#include +#include +#include +#include #include "dyninstAPI/src/image.h" #include "dyninstAPI/h/BPatch_enums.h" #include @@ -98,12 +102,12 @@ class int_variable { //AddressSpace *as() const { return mod()->proc(); } const image_variable *ivar() const { return ivar_; } - Address addr_; - unsigned size_; + Address addr_{}; + unsigned size_{}; // type? - image_variable *ivar_; + image_variable *ivar_{}; - mapped_module *mod_; + mapped_module *mod_{}; }; struct edgeStub { @@ -114,7 +118,7 @@ struct edgeStub { block_instance* src; Address trg; EdgeTypeEnum type; - bool checked; + bool checked{}; }; diff --git a/dyninstAPI/src/os.h b/dyninstAPI/src/os.h index 4eff09c6b3..804442aed1 100644 --- a/dyninstAPI/src/os.h +++ b/dyninstAPI/src/os.h @@ -52,7 +52,7 @@ #endif #include -#include "common/src/Types.h" +#include class OS { public: diff --git a/dyninstAPI/src/parRegion.C b/dyninstAPI/src/parRegion.C index 207bbbd624..d1759342b1 100644 --- a/dyninstAPI/src/parRegion.C +++ b/dyninstAPI/src/parRegion.C @@ -28,6 +28,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include "parRegion.h" #include "parse-cfg.h" #include "function.h" @@ -40,7 +41,7 @@ image_parRegion::image_parRegion(parse_func * imageFunc) { } -image_parRegion::image_parRegion(Address firstOffset, parse_func * imageFunc) +image_parRegion::image_parRegion(Dyninst::Address firstOffset, parse_func * imageFunc) : regionIf_(imageFunc), parentIf_(NULL), firstInsnOffset_(firstOffset), lastInsnOffset_(0), regionType(OMP_NONE) @@ -146,12 +147,12 @@ void image_parRegion::setClause(const char *key, int value) clauses[key] = value; } -void image_parRegion::setClauseLoc(const char *key, Address value) +void image_parRegion::setClauseLoc(const char *key, Dyninst::Address value) { clauses[key] = value; } -int_parRegion::int_parRegion(image_parRegion *ip, Address baseAddr, func_instance * iFunc) +int_parRegion::int_parRegion(image_parRegion *ip, Dyninst::Address baseAddr, func_instance * iFunc) { ip_ = ip; addr_ = baseAddr + ip->get_address(); @@ -177,12 +178,12 @@ int image_parRegion::getClause(const char * key) } -Address int_parRegion::getClauseLoc(const char * key) +Dyninst::Address int_parRegion::getClauseLoc(const char * key) { return ip_->getClauseLoc(key); } -Address image_parRegion::getClauseLoc(const char * key) +Dyninst::Address image_parRegion::getClauseLoc(const char * key) { if (clauses.find(key) != clauses.end()) return clauses[key]; @@ -195,9 +196,9 @@ int int_parRegion::replaceOMPParameter(const char * key, int value) { // parReg->replaceOMPParameter(key,value); - Address writeAddy = getClauseLoc(key); + Dyninst::Address writeAddy = getClauseLoc(key); - Address writeValue = 0x39000000; + Dyninst::Address writeValue = 0x39000000; if (value > 0 ) writeValue += (unsigned) value; diff --git a/dyninstAPI/src/parRegion.h b/dyninstAPI/src/parRegion.h index 7d5f552764..41c10b2c07 100644 --- a/dyninstAPI/src/parRegion.h +++ b/dyninstAPI/src/parRegion.h @@ -32,14 +32,14 @@ #ifndef PARREGION_H #define PARREGION_H +#include #include -#include "common/src/Types.h" -#include "common/src/Pair.h" #include "codeRange.h" #include "common/src/arch.h" // instruction #include "dyninstAPI/h/BPatch_parRegion.h" #include #include +#include "dyntypes.h" class mapped_module; class mapped_object; @@ -67,15 +67,15 @@ struct ltstr class image_parRegion : public codeRange { public: image_parRegion(parse_func * imageFunc); - image_parRegion(Address firstOffset, parse_func * imageFunc); + image_parRegion(Dyninst::Address firstOffset, parse_func * imageFunc); - Address firstInsnOffset() const { return firstInsnOffset_; } + Dyninst::Address firstInsnOffset() const { return firstInsnOffset_; } - void setLastInsn(Address last) { lastInsnOffset_ = last;} - Address lastInsnOffset() const { return lastInsnOffset_; } - Address getSize() const { return lastInsnOffset_ - firstInsnOffset_; } + void setLastInsn(Dyninst::Address last) { lastInsnOffset_ = last;} + Dyninst::Address lastInsnOffset() const { return lastInsnOffset_; } + Dyninst::Address getSize() const { return lastInsnOffset_ - firstInsnOffset_; } - Address get_address() const {return firstInsnOffset_; } + Dyninst::Address get_address() const {return firstInsnOffset_; } unsigned int get_size() const {return 0;} parRegType getRegionType(){return regionType;} @@ -90,8 +90,8 @@ class image_parRegion : public codeRange { void setClause(const char * key, int value); int getClause(const char * key); - void setClauseLoc(const char * key, Address value); - Address getClauseLoc(const char * key); + void setClauseLoc(const char * key, Dyninst::Address value); + Dyninst::Address getClauseLoc(const char * key); void printDetails(); @@ -100,21 +100,21 @@ class image_parRegion : public codeRange { private: parse_func *regionIf_; parse_func *parentIf_; - Address firstInsnOffset_; - Address lastInsnOffset_; + Dyninst::Address firstInsnOffset_; + Dyninst::Address lastInsnOffset_; parRegType regionType; std::map clauses; - std::map clause_locations; + std::map clause_locations; }; class int_parRegion { public: - int_parRegion(image_parRegion *ip, Address baseAddr, func_instance * ); + int_parRegion(image_parRegion *ip, Dyninst::Address baseAddr, func_instance * ); ~int_parRegion(); - Address firstInsnAddr() {return addr_;} - Address endAddr() {return endAddr_;} + Dyninst::Address firstInsnAddr() {return addr_;} + Dyninst::Address endAddr() {return endAddr_;} const image_parRegion * imagePar() const { return ip_; } @@ -123,12 +123,12 @@ class int_parRegion { const func_instance * intFunc() { return intFunc_;} int getClause(const char * key); - Address getClauseLoc(const char * key); + Dyninst::Address getClauseLoc(const char * key); int replaceOMPParameter(const char * key, int value); - Address addr_; /* Absolute address of start of region */ - Address endAddr_; /* Address of end of region */ + Dyninst::Address addr_; /* Absolute address of start of region */ + Dyninst::Address endAddr_; /* Dyninst::Address of end of region */ func_instance * intFunc_; diff --git a/dyninstAPI/src/parse-aarch64.C b/dyninstAPI/src/parse-aarch64.C index ec2c595c7c..4fe6d950ad 100644 --- a/dyninstAPI/src/parse-aarch64.C +++ b/dyninstAPI/src/parse-aarch64.C @@ -61,14 +61,12 @@ //#warning "This file is not implemented yet!" using namespace Dyninst::SymtabAPI; -static const std::string LIBC_CTOR_HANDLER("__libc_csu_init"); -static const std::string LIBC_DTOR_HANDLER("__libc_csu_fini"); -static const std::string DYNINST_CTOR_HANDLER("DYNINSTglobal_ctors_handler"); -static const std::string DYNINST_CTOR_LIST("DYNINSTctors_addr"); -static const std::string DYNINST_DTOR_HANDLER("DYNINSTglobal_dtors_handler"); -static const std::string DYNINST_DTOR_LIST("DYNINSTdtors_addr"); -static const std::string SYMTAB_CTOR_LIST_REL("__SYMTABAPI_CTOR_LIST__"); -static const std::string SYMTAB_DTOR_LIST_REL("__SYMTABAPI_DTOR_LIST__"); +namespace { + char const* LIBC_CTOR_HANDLER("__libc_csu_init"); + char const* LIBC_DTOR_HANDLER("__libc_csu_fini"); + char const* DYNINST_CTOR_HANDLER("DYNINSTglobal_ctors_handler"); + char const* DYNINST_DTOR_HANDLER("DYNINSTglobal_dtors_handler"); +} /* By parsing the function that actually sets up the parameters for the OMP @@ -77,6 +75,7 @@ dealing with */ bool parse_func::parseOMPParent(image_parRegion * /*iPar*/, int /*desiredNum*/, int & /*currentSectionNum*/ ) { assert(0); + return false; } @@ -86,6 +85,7 @@ std::string parse_func::calcParentFunc(const parse_func *, std::vector &/*pR*/) { assert(0); + return {}; } @@ -172,58 +172,67 @@ using namespace Dyninst::SymtabAPI; */ bool BinaryEdit::doStaticBinarySpecialCases() { - Symtab *origBinary = mobj->parse_img()->getObject(); - - /* Special Case 1: Handling global constructor and destructor Regions - * Invoke Dyninst constructor after all static constructors are called - * and invoke Dyninst destructor before staitc destructors - */ - - // First, find all the necessary symbol info. - - func_instance *globalCtorHandler = mobj->findGlobalConstructorFunc(LIBC_CTOR_HANDLER); - if( !globalCtorHandler ) { - logLine("failed to find libc constructor handler\n"); - fprintf (stderr, "failed to find libc constructor handler\n"); - return false; - } - + /* Special Case 1A: Handling global constructors + * + * Place the Dyninst constructor handler after the global ELF ctors so it is invoked last. + * + * Prior to glibc-2.34, this was in the exit point(s) of __libc_csu_init which + * calls all of the initializers in preinit_array and init_array as per SystemV + * before __libc_start_main is invoked. + * + * In glibc-2.34, the code from the csu_* functions was moved into __libc_start_main, so + * now the only place where we are guaranteed that the global constructors have all been + * called is at the beginning of 'main'. + */ func_instance *dyninstCtorHandler = findOnlyOneFunction(DYNINST_CTOR_HANDLER); if( !dyninstCtorHandler ) { logLine("failed to find Dyninst constructor handler\n"); - fprintf (stderr,"failed to find Dyninst constructor handler\n"); return false; } - - func_instance *globalDtorHandler = mobj->findGlobalDestructorFunc(LIBC_DTOR_HANDLER); - if( !globalDtorHandler ) { - logLine ("failed to find libc destructor handler\n"); - fprintf (stderr,"failed to find libc destructor handler\n"); - return false; + if(auto *ctor = mobj->findGlobalConstructorFunc(LIBC_CTOR_HANDLER)) { + // Wire in our handler at libc ctor exits + vector init_pts; + ctor->funcExitPoints(&init_pts); + for(auto *exit_pt : init_pts) { + add_handler(exit_pt, dyninstCtorHandler); + } + } else if(auto *main = findOnlyOneFunction("main")) { + // Insert constructor into the beginning of 'main' + add_handler(main->funcEntryPoint(true), dyninstCtorHandler); + } else { + logLine("failed to find place to insert Dyninst constructors\n"); + return false; } + /* Special Case 1B: Handling global destructors + * + * Place the Dyninst destructor handler before the global ELF dtors so it is invoked first. + * + * Prior to glibc-2.34, this was in the entry point of __libc_csu_fini. + * + * In glibc-2.34, the code in __libc_csu_fini was moved into a hidden function that is + * registered with atexit. To ensure the Dyninst destructors are always called first, we + * have to insert the handler at the beginning of `exit`. + * + * This is a fragile solution as there is no requirement that a symbol for `exit` is + * exported. If we can't find it, we'll just fail here. + */ func_instance *dyninstDtorHandler = findOnlyOneFunction(DYNINST_DTOR_HANDLER); if( !dyninstDtorHandler ) { logLine("failed to find Dyninst destructor handler\n"); - fprintf (stderr,"failed to find Dyninst destructor handler\n"); return false; } - - // Instrument the exits of global constructor function - vector init_pts; - instPoint* fini_point; - globalCtorHandler->funcExitPoints(&init_pts); - - // Instrument the entry of global destructor function - fini_point = globalDtorHandler->funcEntryPoint(true); - // convert points to instpoints - for(auto exit_pt = init_pts.begin(); - exit_pt != init_pts.end(); - ++exit_pt) - { - add_handler(*exit_pt, dyninstCtorHandler); + if(auto *dtor = mobj->findGlobalDestructorFunc(LIBC_DTOR_HANDLER)) { + // Insert destructor into beginning of libc global dtor handler + add_handler(dtor->funcEntryPoint(true), dyninstDtorHandler); + } else if(auto *exit_ = findOnlyOneFunction("exit")) { + // Insert destructor into beginning of `exit` + add_handler(exit_->funcEntryPoint(true), dyninstDtorHandler); + } else { + logLine("failed to find place to insert Dyninst destructors\n"); + return false; } - add_handler(fini_point, dyninstDtorHandler); + AddressSpace::patch(this); @@ -243,6 +252,7 @@ bool BinaryEdit::doStaticBinarySpecialCases() { vector libs; vector::iterator libIter; + Symtab *origBinary = mobj->parse_img()->getObject(); if( origBinary->getLinkingResources(libs) ) { for(libIter = libs.begin(); libIter != libs.end(); ++libIter) { if( (*libIter)->name().find("libpthread") != std::string::npos || diff --git a/dyninstAPI/src/parse-cfg.C b/dyninstAPI/src/parse-cfg.C index 2b81d2a7b6..6d82e4b881 100644 --- a/dyninstAPI/src/parse-cfg.C +++ b/dyninstAPI/src/parse-cfg.C @@ -30,6 +30,7 @@ // $Id: parse-cfg.C,v 1.60 2008/11/03 15:19:24 jaw Exp $ +#include #include "function.h" #include "instPoint.h" diff --git a/dyninstAPI/src/parse-cfg.h b/dyninstAPI/src/parse-cfg.h index a6b86f9a46..bd448b59cb 100644 --- a/dyninstAPI/src/parse-cfg.h +++ b/dyninstAPI/src/parse-cfg.h @@ -33,9 +33,13 @@ #ifndef IMAGE_FUNC_H #define IMAGE_FUNC_H +#include +#include +#include +#include +#include +#include #include -#include "common/src/Types.h" -#include "common/src/Pair.h" #include "common/src/arch.h" // instruction #include "codeRange.h" #include "parRegion.h" diff --git a/dyninstAPI/src/parse-power.C b/dyninstAPI/src/parse-power.C index 96f7a64bfc..8a1e23b05a 100644 --- a/dyninstAPI/src/parse-power.C +++ b/dyninstAPI/src/parse-power.C @@ -60,16 +60,12 @@ using namespace Dyninst::SymtabAPI; -static const std::string LIBC_CTOR_HANDLER("__libc_csu_init"); -static const std::string LIBC_DTOR_HANDLER("__libc_csu_fini"); -static const std::string DYNINST_CTOR_HANDLER("DYNINSTglobal_ctors_handler"); -static const std::string DYNINST_CTOR_BEGIN("DYNINSTctors_begin"); -static const std::string DYNINST_CTOR_END("DYNINSTctors_end"); -static const std::string DYNINST_DTOR_HANDLER("DYNINSTglobal_dtors_handler"); -static const std::string DYNINST_DTOR_BEGIN("DYNINSTdtors_begin"); -static const std::string DYNINST_DTOR_END("DYNINSTdtors_end"); -static const std::string SYMTAB_CTOR_LIST_REL("__SYMTABAPI_CTOR_LIST__"); -static const std::string SYMTAB_DTOR_LIST_REL("__SYMTABAPI_DTOR_LIST__"); +namespace { + char const* LIBC_CTOR_HANDLER("__libc_csu_init"); + char const* LIBC_DTOR_HANDLER("__libc_csu_fini"); + char const* DYNINST_CTOR_HANDLER("DYNINSTglobal_ctors_handler"); + char const* DYNINST_DTOR_HANDLER("DYNINSTglobal_dtors_handler"); +} static void add_handler(instPoint* pt, func_instance* add_me) { @@ -98,7 +94,8 @@ std::string parse_func::calcParentFunc(const parse_func * imf, /* We need to figure out the function that called the outlined parallel region function. We do this by chopping off the last @OL@number */ - const char * nameStart = imf->prettyName().c_str(); + auto const& tmp = imf->prettyName(); + const char * nameStart = tmp.c_str(); const char * nameEnd = strrchr(nameStart, '@'); int strSize = nameEnd - nameStart - 3; @@ -257,58 +254,66 @@ using namespace Dyninst::SymtabAPI; */ bool BinaryEdit::doStaticBinarySpecialCases() { - Symtab *origBinary = mobj->parse_img()->getObject(); - - /* Special Case 1: Handling global constructor and destructor Regions - * Invoke Dyninst constructor after all static constructors are called - * and invoke Dyninst destructor before staitc destructors - */ - - // First, find all the necessary symbol info. - - func_instance *globalCtorHandler = mobj->findGlobalConstructorFunc(LIBC_CTOR_HANDLER); - if( !globalCtorHandler ) { - logLine("failed to find libc constructor handler\n"); - fprintf (stderr, "failed to find libc constructor handler\n"); - return false; - } - + /* Special Case 1A: Handling global constructors + * + * Place the Dyninst constructor handler after the global ELF ctors so it is invoked last. + * + * Prior to glibc-2.34, this was in the exit point(s) of __libc_csu_init which + * calls all of the initializers in preinit_array and init_array as per SystemV + * before __libc_start_main is invoked. + * + * In glibc-2.34, the code from the csu_* functions was moved into __libc_start_main, so + * now the only place where we are guaranteed that the global constructors have all been + * called is at the beginning of 'main'. + */ func_instance *dyninstCtorHandler = findOnlyOneFunction(DYNINST_CTOR_HANDLER); if( !dyninstCtorHandler ) { logLine("failed to find Dyninst constructor handler\n"); - fprintf (stderr,"failed to find Dyninst constructor handler\n"); return false; } - - func_instance *globalDtorHandler = mobj->findGlobalDestructorFunc(LIBC_DTOR_HANDLER); - if( !globalDtorHandler ) { - logLine ("failed to find libc destructor handler\n"); - fprintf (stderr,"failed to find libc destructor handler\n"); - return false; + if(auto *ctor = mobj->findGlobalConstructorFunc(LIBC_CTOR_HANDLER)) { + // Wire in our handler at libc ctor exits + vector init_pts; + ctor->funcExitPoints(&init_pts); + for(auto *exit_pt : init_pts) { + add_handler(exit_pt, dyninstCtorHandler); + } + } else if(auto *main = findOnlyOneFunction("main")) { + // Insert constructor into the beginning of 'main' + add_handler(main->funcEntryPoint(true), dyninstCtorHandler); + } else { + logLine("failed to find place to insert Dyninst constructors\n"); + return false; } + /* Special Case 1B: Handling global destructors + * + * Place the Dyninst destructor handler before the global ELF dtors so it is invoked first. + * + * Prior to glibc-2.34, this was in the entry point of __libc_csu_fini. + * + * In glibc-2.34, the code in __libc_csu_fini was moved into a hidden function that is + * registered with atexit. To ensure the Dyninst destructors are always called first, we + * have to insert the handler at the beginning of `exit`. + * + * This is a fragile solution as there is no requirement that a symbol for `exit` is + * exported. If we can't find it, we'll just fail here. + */ func_instance *dyninstDtorHandler = findOnlyOneFunction(DYNINST_DTOR_HANDLER); if( !dyninstDtorHandler ) { logLine("failed to find Dyninst destructor handler\n"); - fprintf (stderr,"failed to find Dyninst destructor handler\n"); return false; } - - // Instrument the exits of global constructor function - vector init_pts; - instPoint* fini_point; - globalCtorHandler->funcExitPoints(&init_pts); - - // Instrument the entry of global destructor function - fini_point = globalDtorHandler->funcEntryPoint(true); - // convert points to instpoints - for(auto exit_pt = init_pts.begin(); - exit_pt != init_pts.end(); - ++exit_pt) - { - add_handler(*exit_pt, dyninstCtorHandler); + if(auto *dtor = mobj->findGlobalDestructorFunc(LIBC_DTOR_HANDLER)) { + // Insert destructor into beginning of libc global dtor handler + add_handler(dtor->funcEntryPoint(true), dyninstDtorHandler); + } else if(auto *exit_ = findOnlyOneFunction("exit")) { + // Insert destructor into beginning of `exit` + add_handler(exit_->funcEntryPoint(true), dyninstDtorHandler); + } else { + logLine("failed to find place to insert Dyninst destructors\n"); + return false; } - add_handler(fini_point, dyninstDtorHandler); AddressSpace::patch(this); @@ -328,6 +333,7 @@ bool BinaryEdit::doStaticBinarySpecialCases() { vector libs; vector::iterator libIter; + Symtab *origBinary = mobj->parse_img()->getObject(); if( origBinary->getLinkingResources(libs) ) { for(libIter = libs.begin(); libIter != libs.end(); ++libIter) { if( (*libIter)->name().find("libpthread") != std::string::npos || @@ -407,110 +413,7 @@ func_instance *mapped_object::findGlobalConstructorFunc(const std::string &ctorH return ctorFuncs->at(0); } - /* If the symbol isn't found, try looking for it in a call instruction in - * the .init section - * - * On Linux, the instruction sequence is: - * ... - * some instructions - * ... - * call call_gmon_start - * call frame_dummy - * call ctor_handler - * - * On FreeBSD, the instruction sequence is: - * ... - * some instructions - * ... - * call frame_dummy - * call ctor_handler - */ - Symtab *linkedFile = parse_img()->getObject(); - Region *initRegion = NULL; - if( !linkedFile->findRegion(initRegion, ".init") ) { - vector symFuncs; - if( linkedFile->findFunctionsByName(symFuncs, "_init") ) { - initRegion = symFuncs[0]->getRegion(); - }else{ - logLine("failed to locate .init Region or _init function\n"); - return NULL; - } - } - - if( initRegion == NULL ) { - logLine("failed to locate .init Region or _init function\n"); - return NULL; - } - - // Search for last of a fixed number of calls -#if defined(os_freebsd) - const unsigned CTOR_NUM_CALLS = 2; -#else - const unsigned CTOR_NUM_CALLS = 3; -#endif - - Address ctorAddress = 0; - unsigned bytesSeen = 0; - unsigned numCalls = 0; - const unsigned char *p = reinterpret_cast(initRegion->getPtrToRawData()); - - InstructionDecoder decoder(p, initRegion->getDiskSize(), - parse_img()->codeObject()->cs()->getArch()); - - Instruction curInsn = decoder.decode(); - while(numCalls < CTOR_NUM_CALLS && curInsn.isValid() && - bytesSeen < initRegion->getDiskSize()) - { - InsnCategory category = curInsn.getCategory(); - if( category == c_CallInsn ) { - numCalls++; - } - if( numCalls < CTOR_NUM_CALLS ) { - bytesSeen += curInsn.size(); - curInsn = decoder.decode(); - } - } - - if( numCalls != CTOR_NUM_CALLS ) { - logLine("heuristic for finding global constructor function failed\n"); - return NULL; - } - - Address callAddress = initRegion->getMemOffset() + bytesSeen; - - RegisterAST thePC = RegisterAST( - Dyninst::MachRegister::getPC(parse_img()->codeObject()->cs()->getArch())); - - Expression::Ptr callTarget = curInsn.getControlFlowTarget(); - if( !callTarget.get() ) { - logLine("failed to find global constructor function\n"); - return NULL; - } - callTarget->bind(&thePC, Result(s64, callAddress)); - - Result actualTarget = callTarget->eval(); - if( actualTarget.defined ) { - ctorAddress = actualTarget.convert
(); - }else{ - logLine("failed to find global constructor function\n"); - return NULL; - } - - if( !ctorAddress || !parse_img()->codeObject()->cs()->isValidAddress(ctorAddress) ) { - logLine("invalid address for global constructor function\n"); - return NULL; - } - - func_instance *ret; - if( (ret = findFuncByEntry(ctorAddress)) == NULL ) { - logLine("unable to create representation for global constructor function\n"); - return NULL; - } - - inst_printf("%s[%d]: set global constructor address to 0x%lx\n", FILE__, __LINE__, - ctorAddress); - - return ret; + return NULL; } func_instance *mapped_object::findGlobalDestructorFunc(const std::string &dtorHandler) { @@ -520,103 +423,6 @@ func_instance *mapped_object::findGlobalDestructorFunc(const std::string &dtorHa if( ctorFuncs != NULL ) { return ctorFuncs->at(0); } - - /* - * If the symbol isn't found, try looking for it in a call in the - * .fini section. It is the last call in .fini. - * - * The pattern is: - * - * _fini: - * - * ... some code ... - * - * call dtor_handler - * - * ... prologue ... - */ - Symtab *linkedFile = parse_img()->getObject(); - Region *finiRegion = NULL; - if( !linkedFile->findRegion(finiRegion, ".fini") ) { - vector symFuncs; - if( linkedFile->findFunctionsByName(symFuncs, "_fini") ) { - finiRegion = symFuncs[0]->getRegion(); - }else{ - logLine("failed to locate .fini Region or _fini function\n"); - return NULL; - } - } - - if( finiRegion == NULL ) { - logLine("failed to locate .fini Region or _fini function\n"); - return NULL; - } - - // Search for last call in the function - Address dtorAddress = 0; - unsigned bytesSeen = 0; - const unsigned char *p = reinterpret_cast(finiRegion->getPtrToRawData()); - - InstructionDecoder decoder(p, finiRegion->getDiskSize(), - parse_img()->codeObject()->cs()->getArch()); - - Instruction lastCall; - Instruction curInsn = decoder.decode(); - bool find = false; - - while(curInsn.isValid() && - bytesSeen < finiRegion->getDiskSize()) - { - InsnCategory category = curInsn.getCategory(); - if( category == c_CallInsn ) { - find = true; - lastCall = curInsn; - break; - } - - bytesSeen += curInsn.size(); - curInsn = decoder.decode(); - } - - if( !find || !lastCall.isValid() ) { - logLine("heuristic for finding global destructor function failed\n"); - return NULL; - } - - Address callAddress = finiRegion->getMemOffset() + bytesSeen; - - RegisterAST thePC = RegisterAST( - Dyninst::MachRegister::getPC(parse_img()->codeObject()->cs()->getArch())); - - Expression::Ptr callTarget = lastCall.getControlFlowTarget(); - if( !callTarget.get() ) { - logLine("failed to find global destructor function\n"); - return NULL; - } - callTarget->bind(&thePC, Result(s64, callAddress)); - - Result actualTarget = callTarget->eval(); - if( actualTarget.defined ) { - dtorAddress = actualTarget.convert
(); - }else{ - logLine("failed to find global destructor function\n"); - return NULL; - } - - if( !dtorAddress || !parse_img()->codeObject()->cs()->isValidAddress(dtorAddress) ) { - logLine("invalid address for global destructor function\n"); - return NULL; - } - - // A targ stub should have been created at the address - func_instance *ret = NULL; - if( (ret = findFuncByEntry(dtorAddress)) == NULL ) { - logLine("unable to find global destructor function\n"); - return NULL; - } - inst_printf("%s[%d]: set global destructor address to 0x%lx\n", FILE__, __LINE__, - dtorAddress); - - return ret; + return NULL; } diff --git a/dyninstAPI/src/parse-x86.C b/dyninstAPI/src/parse-x86.C index 0dd63f6df3..7109745439 100644 --- a/dyninstAPI/src/parse-x86.C +++ b/dyninstAPI/src/parse-x86.C @@ -41,7 +41,7 @@ #include #include #include -//#include "arch.h" +#include "registers/x86_regs.h" #include "instructionAPI/h/Instruction.h" #include "instructionAPI/h/InstructionDecoder.h" @@ -181,22 +181,18 @@ using namespace Dyninst::SymtabAPI; * the GNU toolchain. However, it should be straightforward to extend these * operations to other toolchains. */ -static const std::string LIBC_CTOR_HANDLER("__libc_csu_init"); -static const std::string LIBC_DTOR_HANDLER("__libc_csu_fini"); -static const std::string DYNINST_CTOR_HANDLER("DYNINSTglobal_ctors_handler"); -static const std::string DYNINST_CTOR_BEGIN("DYNINSTctors_begin"); -static const std::string DYNINST_CTOR_END("DYNINSTctors_end"); -static const std::string DYNINST_DTOR_HANDLER("DYNINSTglobal_dtors_handler"); -static const std::string DYNINST_DTOR_BEGIN("DYNINSTdtors_begin"); -static const std::string DYNINST_DTOR_END("DYNINSTdtors_end"); -static const std::string SYMTAB_CTOR_LIST_REL("__SYMTABAPI_CTOR_LIST__"); -static const std::string SYMTAB_DTOR_LIST_REL("__SYMTABAPI_DTOR_LIST__"); -static const std::string LIBC_IREL_HANDLER("__libc_csu_irel"); -static const std::string DYNINST_IREL_HANDLER("DYNINSTglobal_irel_handler"); -static const std::string DYNINST_IREL_START("DYNINSTirel_start"); -static const std::string DYNINST_IREL_END("DYNINSTirel_end"); -static const std::string SYMTAB_IREL_START("__SYMTABAPI_IREL_START__"); -static const std::string SYMTAB_IREL_END("__SYMTABAPI_IREL_END__"); +namespace { + char const* LIBC_CTOR_HANDLER("__libc_csu_init"); + char const* LIBC_DTOR_HANDLER("__libc_csu_fini"); + char const* DYNINST_CTOR_HANDLER("DYNINSTglobal_ctors_handler"); + char const* DYNINST_DTOR_HANDLER("DYNINSTglobal_dtors_handler"); + char const* LIBC_IREL_HANDLER("__libc_csu_irel"); + char const* DYNINST_IREL_HANDLER("DYNINSTglobal_irel_handler"); + char const* DYNINST_IREL_START("DYNINSTirel_start"); + char const* DYNINST_IREL_END("DYNINSTirel_end"); + char const* SYMTAB_IREL_START("__SYMTABAPI_IREL_START__"); + char const* SYMTAB_IREL_END("__SYMTABAPI_IREL_END__"); +} static bool replaceHandler(func_instance *origHandler, func_instance *newHandler, @@ -242,7 +238,7 @@ static bool replaceHandler(func_instance *origHandler, func_instance *newHandler return true; } -void add_handler(instPoint* pt, func_instance* add_me) +static void add_handler(instPoint* pt, func_instance* add_me) { vector args; // no args, just add @@ -253,92 +249,108 @@ void add_handler(instPoint* pt, func_instance* add_me) bool BinaryEdit::doStaticBinarySpecialCases() { - Symtab *origBinary = mobj->parse_img()->getObject(); - - /* Special Case 1: Handling global constructor and destructor Regions + /* Special Case 1A: Handling global constructors * - * Replace global ctors function with special ctors function, - * and create a special relocation for the ctors list used by the special - * ctors function + * Place the Dyninst constructor handler after the global ELF ctors so it is invoked last. * - * Replace global dtors function with special dtors function, - * and create a special relocation for the dtors list used by the special - * dtors function - */ - - // First, find all the necessary symbol info. - - func_instance *globalCtorHandler = mobj->findGlobalConstructorFunc(LIBC_CTOR_HANDLER); - if( !globalCtorHandler ) { - logLine("failed to find libc destructor handler\n"); - return false; - } + * Prior to glibc-2.34, this was in the exit point(s) of __libc_csu_init which + * calls all of the initializers in preinit_array and init_array as per SystemV + * before __libc_start_main is invoked. + * + * In glibc-2.34, the code from the csu_* functions was moved into __libc_start_main, so + * now the only place where we are guaranteed that the global constructors have all been + * called is at the beginning of 'main'. + */ func_instance *dyninstCtorHandler = findOnlyOneFunction(DYNINST_CTOR_HANDLER); if( !dyninstCtorHandler ) { logLine("failed to find Dyninst constructor handler\n"); return false; } - - func_instance *globalDtorHandler = mobj->findGlobalDestructorFunc(LIBC_DTOR_HANDLER); - if( !globalDtorHandler ) { - logLine("failed to find libc destructor handler\n"); - return false; + if(auto *ctor = mobj->findGlobalConstructorFunc(LIBC_CTOR_HANDLER)) { + // Wire in our handler at libc ctor exits + vector init_pts; + ctor->funcExitPoints(&init_pts); + for(auto *exit_pt : init_pts) { + add_handler(exit_pt, dyninstCtorHandler); + } + } else if(auto *main = findOnlyOneFunction("main")) { + // Insert constructor into the beginning of 'main' + add_handler(main->funcEntryPoint(true), dyninstCtorHandler); + } else { + logLine("failed to find place to insert Dyninst constructors\n"); + return false; } + /* Special Case 1B: Handling global destructors + * + * Place the Dyninst destructor handler before the global ELF dtors so it is invoked first. + * + * Prior to glibc-2.34, this was in the entry point of __libc_csu_fini. + * + * In glibc-2.34, the code in __libc_csu_fini was moved into a hidden function that is + * registered with atexit. To ensure the Dyninst destructors are always called first, we + * have to insert the handler at the beginning of `exit`. + * + * This is a fragile solution as there is no requirement that a symbol for `exit` is + * exported. If we can't find it, we'll just fail here. + */ func_instance *dyninstDtorHandler = findOnlyOneFunction(DYNINST_DTOR_HANDLER); if( !dyninstDtorHandler ) { logLine("failed to find Dyninst destructor handler\n"); return false; } - // Wire in our handlers at libc ctor exit/dtor entry - vector init_pts; - instPoint* fini_point; - globalCtorHandler->funcExitPoints(&init_pts); - fini_point = globalDtorHandler->funcEntryPoint(true); - // convert points to instpoints - for(auto exit_pt = init_pts.begin(); - exit_pt != init_pts.end(); - ++exit_pt) - { - add_handler(*exit_pt, dyninstCtorHandler); + if(auto *dtor = mobj->findGlobalDestructorFunc(LIBC_DTOR_HANDLER)) { + // Insert destructor into beginning of libc global dtor handler + add_handler(dtor->funcEntryPoint(true), dyninstDtorHandler); + } else if(auto *exit_ = findOnlyOneFunction("exit")) { + // Insert destructor into beginning of `exit` + add_handler(exit_->funcEntryPoint(true), dyninstDtorHandler); + } else { + logLine("failed to find place to insert Dyninst destructors\n"); + return false; } - add_handler(fini_point, dyninstDtorHandler); + AddressSpace::patch(this); + /* Special Case 1C: Instrument irel handlers + * + * Replace the irel handler with our extended version, since they hard-code + * ALL THE OFFSETS in the function. + * + * __libc_csu_irel was removed from glibc-2.19 in 2013. + * + * irel handlers are not instrumented on the other architectures. We leave this + * here for posterity. + */ + if(auto *globalIrelHandler = findOnlyOneFunction(LIBC_IREL_HANDLER)) { + func_instance *dyninstIrelHandler = findOnlyOneFunction(DYNINST_IREL_HANDLER); + int_symbol irelStart; + int_symbol irelEnd; + bool irs_found = false; + bool ire_found = false; + for (auto rtlib_it = rtlib.begin(); rtlib_it != rtlib.end(); ++rtlib_it) { + if( (*rtlib_it)->getSymbolInfo(DYNINST_IREL_START, irelStart) ) { + irs_found = true; + } - /* - * Replace the irel handler with our extended version, since they - * hard-code ALL THE OFFSETS in the function - */ - func_instance *globalIrelHandler = findOnlyOneFunction(LIBC_IREL_HANDLER); - func_instance *dyninstIrelHandler = findOnlyOneFunction(DYNINST_IREL_HANDLER); - int_symbol irelStart; - int_symbol irelEnd; - bool irs_found = false; - bool ire_found = false; - for (auto rtlib_it = rtlib.begin(); rtlib_it != rtlib.end(); ++rtlib_it) { - if( (*rtlib_it)->getSymbolInfo(DYNINST_IREL_START, irelStart) ) { - irs_found = true; - } - - if( (*rtlib_it)->getSymbolInfo(DYNINST_IREL_END, irelEnd) ) { - ire_found = true; + if( (*rtlib_it)->getSymbolInfo(DYNINST_IREL_END, irelEnd) ) { + ire_found = true; + } + if (irs_found && ire_found) break; } - if (irs_found && ire_found) break; - } - if (globalIrelHandler) { - assert(dyninstIrelHandler); - assert(irs_found); - assert(ire_found); - std::vector > tmp; - tmp.push_back(make_pair(&irelStart, SYMTAB_IREL_START)); - tmp.push_back(make_pair(&irelEnd, SYMTAB_IREL_END)); - if (!replaceHandler(globalIrelHandler, dyninstIrelHandler, tmp)) { - return false; + if (globalIrelHandler) { + assert(dyninstIrelHandler); + assert(irs_found); + assert(ire_found); + std::vector > tmp; + tmp.push_back(make_pair(&irelStart, SYMTAB_IREL_START)); + tmp.push_back(make_pair(&irelEnd, SYMTAB_IREL_END)); + if (!replaceHandler(globalIrelHandler, dyninstIrelHandler, tmp)) { + return false; + } } } - /* * Special Case 2: Issue a warning if attempting to link pthreads into a binary * that originally did not support it or into a binary that is stripped. This @@ -350,7 +362,7 @@ bool BinaryEdit::doStaticBinarySpecialCases() { */ bool isMTCapable = isMultiThreadCapable(); bool foundPthreads = false; - + Symtab *origBinary = mobj->parse_img()->getObject(); vector libs; vector::iterator libIter; if( origBinary->getLinkingResources(libs) ) { diff --git a/dyninstAPI/src/patch.h b/dyninstAPI/src/patch.h index 6f09de9669..744a56073b 100644 --- a/dyninstAPI/src/patch.h +++ b/dyninstAPI/src/patch.h @@ -32,6 +32,7 @@ #define patch_h #include +#include "dyntypes.h" class codeGen; @@ -41,27 +42,29 @@ class codeGen; class patchTarget { public: - virtual Address get_address() const = 0; + virtual Dyninst::Address get_address() const = 0; virtual unsigned get_size() const = 0; virtual std::string get_name() const; + patchTarget() = default; + patchTarget(const patchTarget&) = default; virtual ~patchTarget() = default; }; class toAddressPatch : public patchTarget { private: - Address addr; + Dyninst::Address addr; public: - toAddressPatch(Address a) : addr(a) {} + toAddressPatch(Dyninst::Address a) : addr(a) {} virtual ~toAddressPatch(); - virtual Address get_address() const; + virtual Dyninst::Address get_address() const; virtual unsigned get_size() const; - void set_address(Address a); + void set_address(Dyninst::Address a); }; class relocPatch { public: - typedef enum { + enum class patch_type_t { abs, //Patch the absolute address of the source into dest pcrel, //Patch a PC relative address from codeGen start + offset abs_lo, //Patch lower half of source's bytes into dest @@ -70,7 +73,7 @@ class relocPatch { abs_quad2, //Patch the second quarter of source's bytes into dest abs_quad3, //Patch the third quarter of source's bytes into dest abs_quad4 //Patch the forth quarter of source's bytes into dest - } patch_type_t; + }; relocPatch(unsigned d, patchTarget *s, relocPatch::patch_type_t ptype, @@ -96,7 +99,7 @@ class ifTargetPatch : public patchTarget signed int targetOffset; public: ifTargetPatch(signed int o) { targetOffset = o; } - virtual Address get_address() const { return (Address) targetOffset; } + virtual Dyninst::Address get_address() const { return (Dyninst::Address) targetOffset; } virtual unsigned get_size() const { return 0; } virtual std::string get_name() const { return std::string("ifTarget"); } virtual ~ifTargetPatch() { } diff --git a/dyninstAPI/src/pcEventHandler.C b/dyninstAPI/src/pcEventHandler.C index e97662d91f..3e4053b312 100644 --- a/dyninstAPI/src/pcEventHandler.C +++ b/dyninstAPI/src/pcEventHandler.C @@ -27,6 +27,7 @@ * License along with this library; if not, write to the Free Software * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include "pcEventHandler.h" #include "BPatch.h" #include "debug.h" @@ -36,7 +37,6 @@ #include "registerSpace.h" #include "RegisterConversion.h" #include "function.h" -#include "MemoryEmulator/memEmulator.h" #include "dynThread.h" #include "Mailbox.h" @@ -368,6 +368,15 @@ bool PCEventHandler::handleThreadCreate(EventNewThread::const_ptr ev, PCProcess proccontrol_printf("%s[%d]: entering handleThreadCreate for %d/%d\n", FILE__, __LINE__, evProc->getPid(), ev->getLWP()); + // Check if the thread still exists +#if defined(os_linux) || defined(os_freebsd) + if (!ev->getNewThread()) { + proccontrol_printf("%s[%d]: thread %d/%d not found, it may have already exited. Ignoring thread create event.\n", + FILE__, __LINE__, evProc->getPid(), ev->getLWP()); + return true; + } +#endif + if( !ev->getNewThread()->haveUserThreadInfo() ) { proccontrol_printf("%s[%d]: no user thread info for thread %d/%d, postponing thread create\n", FILE__, __LINE__, evProc->getPid(), ev->getLWP()); @@ -424,6 +433,13 @@ bool PCEventHandler::handleThreadDestroy(EventThreadDestroy::const_ptr ev, PCPro FILE__, __LINE__, evProc->getPid(), ev->getThread()->getLWP()); BPatch_process *bpproc = BPatch::bpatch->getProcessByPid(evProc->getPid()); if( bpproc == NULL ) { +#if defined(os_linux) || defined(os_freebsd) + if (ev->getEventType().code() == EventType::LWPDestroy) { + proccontrol_printf("%s[%d]: failed to locate process %d, for corresponding LWPDestroy event. It may have already exited. Ignoring event.\n", + FILE__, __LINE__, evProc->getPid()); + return true; + } +#endif proccontrol_printf("%s[%d]: failed to locate BPatch_process for process %d\n", FILE__, __LINE__, evProc->getPid()); return false; @@ -460,16 +476,6 @@ bool PCEventHandler::handleSignal(EventSignal::const_ptr ev, PCProcess *evProc) Address addr = ev->getAddress(); mapped_object* obj = evProc->findObject(addr); - // retry finding object by its original address. - if (obj == NULL && evProc->isMemoryEmulated()) { - std::pair trans = - evProc->getMemEm()->translateBackwards(addr); - if (trans.first) { - addr = trans.second; - obj = evProc->findObject(addr); - } - } - // change permissions if we can find this originally writable region if (obj != NULL) { SymtabAPI::Region* reg = diff --git a/dyninstAPI/src/pcEventHandler.h b/dyninstAPI/src/pcEventHandler.h index d9542ad585..dfd0efdb8d 100644 --- a/dyninstAPI/src/pcEventHandler.h +++ b/dyninstAPI/src/pcEventHandler.h @@ -35,7 +35,7 @@ #include "dyninstAPI/h/BPatch_process.h" #include -#include "common/src/Types.h" +#include "dyntypes.h" #include "common/src/dthread.h" #include "syscallNotification.h" @@ -57,7 +57,7 @@ class PCEventMuxer; */ class PCEventHandler { - typedef ProcControlAPI::Event::const_ptr EventPtr; + typedef Dyninst::ProcControlAPI::Event::const_ptr EventPtr; // Why syscallNotification is a friend: // // It is a friend because it reaches in to determine whether to install @@ -76,17 +76,17 @@ class PCEventHandler { bool handle_internal(EventPtr ev); - bool handleExit(ProcControlAPI::EventExit::const_ptr ev, PCProcess *evProc) const; - bool handleFork(ProcControlAPI::EventFork::const_ptr ev, PCProcess *evProc) const; - bool handleExec(ProcControlAPI::EventExec::const_ptr ev, PCProcess *&evProc) const; - bool handleCrash(ProcControlAPI::EventCrash::const_ptr ev, PCProcess *evProc) const; - bool handleForceTerminate(ProcControlAPI::EventForceTerminate::const_ptr ev, PCProcess *evProc) const; - bool handleThreadCreate(ProcControlAPI::EventNewThread::const_ptr ev, PCProcess *evProc) const; - bool handleThreadDestroy(ProcControlAPI::EventThreadDestroy::const_ptr ev, PCProcess *evProc) const; - bool handleSignal(ProcControlAPI::EventSignal::const_ptr ev, PCProcess *evProc) const; - bool handleLibrary(ProcControlAPI::EventLibrary::const_ptr ev, PCProcess *evProc) const; - bool handleBreakpoint(ProcControlAPI::EventBreakpoint::const_ptr ev, PCProcess *evProc) const; - bool handleRPC(ProcControlAPI::EventRPC::const_ptr ev, PCProcess *evProc) const; + bool handleExit(Dyninst::ProcControlAPI::EventExit::const_ptr ev, PCProcess *evProc) const; + bool handleFork(Dyninst::ProcControlAPI::EventFork::const_ptr ev, PCProcess *evProc) const; + bool handleExec(Dyninst::ProcControlAPI::EventExec::const_ptr ev, PCProcess *&evProc) const; + bool handleCrash(Dyninst::ProcControlAPI::EventCrash::const_ptr ev, PCProcess *evProc) const; + bool handleForceTerminate(Dyninst::ProcControlAPI::EventForceTerminate::const_ptr ev, PCProcess *evProc) const; + bool handleThreadCreate(Dyninst::ProcControlAPI::EventNewThread::const_ptr ev, PCProcess *evProc) const; + bool handleThreadDestroy(Dyninst::ProcControlAPI::EventThreadDestroy::const_ptr ev, PCProcess *evProc) const; + bool handleSignal(Dyninst::ProcControlAPI::EventSignal::const_ptr ev, PCProcess *evProc) const; + bool handleLibrary(Dyninst::ProcControlAPI::EventLibrary::const_ptr ev, PCProcess *evProc) const; + bool handleBreakpoint(Dyninst::ProcControlAPI::EventBreakpoint::const_ptr ev, PCProcess *evProc) const; + bool handleRPC(Dyninst::ProcControlAPI::EventRPC::const_ptr ev, PCProcess *evProc) const; enum RTBreakpointVal { NoRTBreakpoint, @@ -94,14 +94,14 @@ class PCEventHandler { SoftRTBreakpoint }; - bool handleRTBreakpoint(ProcControlAPI::EventBreakpoint::const_ptr ev, PCProcess *evProc) const; - bool handleStopThread(PCProcess *evProc, Address rt_arg) const; - bool handleUserMessage(PCProcess *evProc, BPatch_process *bpProc, Address rt_arg) const; - bool handleDynFuncCall(PCProcess *evProc, BPatch_process *bpProc, Address rt_arg) const; + bool handleRTBreakpoint(Dyninst::ProcControlAPI::EventBreakpoint::const_ptr ev, PCProcess *evProc) const; + bool handleStopThread(PCProcess *evProc, Dyninst::Address rt_arg) const; + bool handleUserMessage(PCProcess *evProc, BPatch_process *bpProc, Dyninst::Address rt_arg) const; + bool handleDynFuncCall(PCProcess *evProc, BPatch_process *bpProc, Dyninst::Address rt_arg) const; // platform-specific static bool shouldStopForSignal(int signal); - static bool isValidRTSignal(int signal, RTBreakpointVal breakpointVal, Address arg1, int status); + static bool isValidRTSignal(int signal, RTBreakpointVal breakpointVal, Dyninst::Address arg1, int status); static bool isCrashSignal(int signal); static bool isKillSignal(int signal); diff --git a/dyninstAPI/src/pcEventMuxer.C b/dyninstAPI/src/pcEventMuxer.C index bc4853c4c9..379834934b 100644 --- a/dyninstAPI/src/pcEventMuxer.C +++ b/dyninstAPI/src/pcEventMuxer.C @@ -27,6 +27,7 @@ * License along with this library; if not, write to the Free Software * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include "pcEventMuxer.h" #include "pcEventHandler.h" #include "BPatch.h" @@ -423,7 +424,7 @@ PCEventMuxer::cb_ret_t PCEventMuxer::RPCCallback(EventPtr ev) { return ret; } - if( rpcInProg->resultRegister == REG_NULL ) { + if( rpcInProg->resultRegister == Null_Register ) { // If the resultRegister isn't set, the returnValue shouldn't matter rpcInProg->returnValue = NULL; }else{ diff --git a/dyninstAPI/src/pcEventMuxer.h b/dyninstAPI/src/pcEventMuxer.h index bcf54bf3ac..9b00478dd2 100644 --- a/dyninstAPI/src/pcEventMuxer.h +++ b/dyninstAPI/src/pcEventMuxer.h @@ -32,12 +32,12 @@ #define PCEVENTMUXER_H #include "common/src/dthread.h" -#include "common/src/Types.h" #include "Event.h" #include "dyninstAPI/h/BPatch_process.h" #include "dyninstAPI/src/syscallNotification.h" +#include #include /* * Overall design comment @@ -76,14 +76,14 @@ class PCEventMailbox { PCEventMailbox(); ~PCEventMailbox(); - void enqueue(ProcControlAPI::Event::const_ptr ev); - ProcControlAPI::Event::const_ptr dequeue(bool block); + void enqueue(Dyninst::ProcControlAPI::Event::const_ptr ev); + Dyninst::ProcControlAPI::Event::const_ptr dequeue(bool block); unsigned int size(); bool find(PCProcess *proc); protected: std::map procCount; - std::queue eventQueue; + std::queue eventQueue; CondVar<> queueCond; }; @@ -164,8 +164,8 @@ class PCEventMuxer { * case 2: register the callback, insert the breakpoint * case 3: don't register the callback, insert the breakpoint */ - static bool useCallback(ProcControlAPI::EventType et); - static bool useBreakpoint(ProcControlAPI::EventType et); + static bool useCallback(Dyninst::ProcControlAPI::EventType et); + static bool useBreakpoint(Dyninst::ProcControlAPI::EventType et); private: // We need to use a separate thread so that we can fast-handle certain @@ -185,9 +185,9 @@ class PCEventMuxer { EventPtr dequeue(bool block); bool handle(EventPtr); - static ProcControlAPI::Process::cb_ret_t ret_stopped; - static ProcControlAPI::Process::cb_ret_t ret_continue; - static ProcControlAPI::Process::cb_ret_t ret_default; + static Dyninst::ProcControlAPI::Process::cb_ret_t ret_stopped; + static Dyninst::ProcControlAPI::Process::cb_ret_t ret_continue; + static Dyninst::ProcControlAPI::Process::cb_ret_t ret_default; PCEventMailbox mailbox_; diff --git a/dyninstAPI/src/pcrel.h b/dyninstAPI/src/pcrel.h index dc5d4189e9..8347117abb 100644 --- a/dyninstAPI/src/pcrel.h +++ b/dyninstAPI/src/pcrel.h @@ -39,7 +39,7 @@ class pcRelRegion { unsigned cur_offset; unsigned cur_size; pcRelRegion(const instruction &i); - virtual unsigned apply(Address addr) = 0; + virtual unsigned apply(Dyninst::Address addr) = 0; virtual unsigned maxSize() = 0; virtual bool canPreApply(); virtual ~pcRelRegion(); @@ -48,15 +48,15 @@ class pcRelRegion { class pcRelJump : public pcRelRegion { private: - Address addr_targ; + Dyninst::Address addr_targ; patchTarget *targ; bool copy_prefixes_; - Address get_target(); + Dyninst::Address get_target(); public: pcRelJump(patchTarget *t, const instruction &i, bool copyPrefixes = true); - pcRelJump(Address target, const instruction &i, bool copyPrefixes = true); - virtual unsigned apply(Address addr); + pcRelJump(Dyninst::Address target, const instruction &i, bool copyPrefixes = true); + virtual unsigned apply(Dyninst::Address addr); virtual unsigned maxSize(); virtual bool canPreApply(); virtual ~pcRelJump(); @@ -64,14 +64,14 @@ class pcRelJump : public pcRelRegion { class pcRelJCC : public pcRelRegion { private: - Address addr_targ; + Dyninst::Address addr_targ; patchTarget *targ; - Address get_target(); + Dyninst::Address get_target(); public: pcRelJCC(patchTarget *t, const instruction &i); - pcRelJCC(Address target, const instruction &i); - virtual unsigned apply(Address addr); + pcRelJCC(Dyninst::Address target, const instruction &i); + virtual unsigned apply(Dyninst::Address addr); virtual unsigned maxSize(); virtual bool canPreApply(); virtual ~pcRelJCC(); @@ -79,15 +79,15 @@ class pcRelJCC : public pcRelRegion { class pcRelCall: public pcRelRegion { private: - Address targ_addr; + Dyninst::Address targ_addr; patchTarget *targ; - Address get_target(); + Dyninst::Address get_target(); public: pcRelCall(patchTarget *t, const instruction &i); - pcRelCall(Address targ_addr, const instruction &i); + pcRelCall(Dyninst::Address targ_addr, const instruction &i); - virtual unsigned apply(Address addr); + virtual unsigned apply(Dyninst::Address addr); virtual unsigned maxSize(); virtual bool canPreApply(); ~pcRelCall(); @@ -95,10 +95,10 @@ class pcRelCall: public pcRelRegion { class pcRelData : public pcRelRegion { private: - Address data_addr; + Dyninst::Address data_addr; public: - pcRelData(Address a, const instruction &i); - virtual unsigned apply(Address addr); + pcRelData(Dyninst::Address a, const instruction &i); + virtual unsigned apply(Dyninst::Address addr); virtual unsigned maxSize(); virtual bool canPreApply(); }; diff --git a/dyninstAPI/src/pdwinnt.C b/dyninstAPI/src/pdwinnt.C index 5eee0bb55e..f887e37a6f 100644 --- a/dyninstAPI/src/pdwinnt.C +++ b/dyninstAPI/src/pdwinnt.C @@ -28,7 +28,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "common/src/std_namesp.h" +#include #include #include #include "common/src/headers.h" @@ -36,7 +36,6 @@ #include "dyninstAPI/src/addressSpace.h" #include "binaryEdit.h" #include "common/src/stats.h" -#include "common/src/Types.h" #include "dyninstAPI/src/debug.h" #include "dyninstAPI/src/instPoint.h" #include "common/src/ntHeaders.h" @@ -46,8 +45,7 @@ #include "dyninstAPI/src/inst-x86.h" #include "dyninstAPI/src/registerSpace.h" #include "image.h" -#include "MemoryEmulator/memEmulator.h" -#include +#include #include "dyninstAPI/src/ast.h" @@ -75,7 +73,7 @@ void printSysError(unsigned errNo) { fprintf(stderr, "Couldn't print error message\n"); printSysError(GetLastError()); } - fprintf(stderr, "*** System error [%d]: %s\n", errNo, buf); + fprintf(stderr, "*** System error [%u]: %s\n", errNo, buf); fflush(stderr); } @@ -174,29 +172,6 @@ void PCProcess::changeMemoryProtections(Address addr, size_t size, rights, oldRights)) { mal_printf("ERROR: failed to set access rights " "for page %lx, %s[%d]\n", addr, FILE__, __LINE__); - } else if (isMemoryEmulated() && setShadow) { - Address shadowAddr = 0; - PCMemPerm shadowRights; - bool valid = false; - boost::tie(valid, shadowAddr) = getMemEm()->translate(idx); - if (!valid) { - mal_printf("WARNING: set access rights on page %lx that has " - "no shadow %s[%d]\n",addr,FILE__,__LINE__); - } else { - if(!pcProc_->setMemoryAccessRights(shadowAddr, pageSize, - rights, shadowRights)) { - mal_printf("ERROR: failed to set access rights " - "for page %lx, %s[%d]\n", - shadowAddr, FILE__, __LINE__); - } - - if (shadowRights != oldRights) { - mal_printf("WARNING: shadow page[%lx] rights %s did not " - "match orig-page [%lx] rights %s\n", - shadowAddr, shadowRights.getPermName().c_str(), - addr, oldRights.getPermName().c_str()); - } - } } } } @@ -462,7 +437,7 @@ int EmitterIA32::emitCallParams(codeGen &gen, callType call_conven = target->getCallingConvention(); int estimatedFrameSize = 0; std::vector srcs; - Register ecx_target = REG_NULL, edx_target = REG_NULL; + Register ecx_target = Null_Register, edx_target = Null_Register; Address unused = ADDR_NULL; const int num_operands = operands.size(); @@ -472,10 +447,10 @@ int EmitterIA32::emitCallParams(codeGen &gen, case stdcall_call: //Push all registers onto stack for (unsigned u = 0; u < operands.size(); u++) { - Register src = REG_NULL; + Register src = Null_Register; Address unused = ADDR_NULL; if (!operands[u]->generateCode_phase2( gen, false, unused, src)) assert(0); - assert(src != REG_NULL); + assert(src != Null_Register); srcs.push_back(src); } break; @@ -493,10 +468,10 @@ int EmitterIA32::emitCallParams(codeGen &gen, srcs.push_back(Null_Register); //Push other registers onto the stack for (unsigned u = 1; u < operands.size(); u++) { - Register src = REG_NULL; + Register src = Null_Register; Address unused = ADDR_NULL; if (!operands[u]->generateCode_phase2( gen, false, unused, src)) assert(0); - assert(src != REG_NULL); + assert(src != Null_Register); srcs.push_back(src); } break; @@ -529,10 +504,10 @@ int EmitterIA32::emitCallParams(codeGen &gen, //Push other registers onto the stack for (unsigned u = 2; u < operands.size(); u++) { - Register src = REG_NULL; + Register src = Null_Register; Address unused = ADDR_NULL; if (!operands[u]->generateCode_phase2( gen, false, unused, src)) assert(0); - assert(src != REG_NULL); + assert(src != Null_Register); srcs.push_back(src); } break; @@ -552,12 +527,12 @@ int EmitterIA32::emitCallParams(codeGen &gen, gen.rs()->freeRegister(srcs[i]); } - if (ecx_target != REG_NULL) { + if (ecx_target != Null_Register) { //Store the parameter in ecx gen.rs()->loadVirtualToSpecific(ecx_target, RealRegister(REGNUM_ECX), gen); } - if (edx_target != REG_NULL) { + if (edx_target != Null_Register) { gen.rs()->loadVirtualToSpecific(edx_target, RealRegister(REGNUM_EDX), gen); } return estimatedFrameSize; diff --git a/dyninstAPI/src/pdwinntDL.C b/dyninstAPI/src/pdwinntDL.C index e0944f9a03..fd1ca09148 100644 --- a/dyninstAPI/src/pdwinntDL.C +++ b/dyninstAPI/src/pdwinntDL.C @@ -100,7 +100,7 @@ bool dynamic_linking::handleIfDueToSharedObjectMapping(EventRecord &ev, (DWORD64) ev.info.u.LoadDll.lpBaseOfDll, 0); if (!iresult) { printSysError(GetLastError()); - fprintf(stderr, "[%s:%u] - Couldn't SymLoadModule64\n", FILE__, __LINE__); + fprintf(stderr, "[%s:%d] - Couldn't SymLoadModule64\n", FILE__, __LINE__); return true; } @@ -120,7 +120,7 @@ bool dynamic_linking::handleIfDueToSharedObjectMapping(EventRecord &ev, mapped_object *newobj = mapped_object::createMappedObject(desc, proc, mode, parseGaps); if (!newobj) { - fprintf(stderr, "[%s:%u] - Couldn't parse loaded module %s\n", + fprintf(stderr, "[%s:%d] - Couldn't parse loaded module %s\n", FILE__,__LINE__, imageName.c_str()); return true; } @@ -136,7 +136,7 @@ bool dynamic_linking::handleIfDueToSharedObjectMapping(EventRecord &ev, bool result = SymUnloadModule64(procHandle, base); if (!result) { printSysError(GetLastError()); - fprintf(stderr, "[%s:%u] - Couldn't SymUnloadModule64\n", FILE__, __LINE__); + fprintf(stderr, "[%s:%d] - Couldn't SymUnloadModule64\n", FILE__, __LINE__); } mapped_object *oldobj = NULL; diff --git a/dyninstAPI/src/registerSpace.C b/dyninstAPI/src/registerSpace.C index 47ab1a2ab1..39dc8ec1c0 100644 --- a/dyninstAPI/src/registerSpace.C +++ b/dyninstAPI/src/registerSpace.C @@ -30,6 +30,7 @@ // $Id: registerSpace.C,v 1.25 2008/10/27 17:23:53 mlam Exp $ +#include #include "dyninstAPI/src/image.h" #include "dyninstAPI/src/inst.h" #include "dyninstAPI/src/instP.h" @@ -100,7 +101,7 @@ unsigned registerSlot::encoding() const { break; default: assert(0); - return REG_NULL; + return Null_Register; break; } #elif defined(arch_x86) || defined(arch_x86_64) @@ -116,7 +117,7 @@ unsigned registerSlot::encoding() const { break; default: assert(0); - return REG_NULL; + return Null_Register; break; } #else @@ -432,7 +433,7 @@ Register registerSpace::getScratchRegister(codeGen &gen, std::vector & if (toUse == NULL) { // Crap. // debugPrint(); - return REG_NULL; + return Null_Register; } toUse->alloc_num = num_allocs; @@ -452,7 +453,7 @@ Register registerSpace::allocateRegister(codeGen &gen, regalloc_printf("Allocating and retaining register...\n"); Register reg = getScratchRegister(gen, noCost, realReg); regalloc_printf("retaining register %u\n", reg); - if (reg == REG_NULL) return REG_NULL; + if (reg == Null_Register) return Null_Register; if (realReg) { physicalRegs(reg)->refCount = 1; } @@ -820,7 +821,7 @@ bool registerSpace::writeProgramRegister(codeGen &gen, registerSlot *registerSpace::findRegister(Register source) { // Oh, oops... we're handed a register number... and we can't tell if it's // GPR, FPR, or SPR... - if (source == REG_NULL) return NULL; + if (source == Null_Register) return NULL; auto iter = registers_.find(source); if (iter == registers_.end()) return NULL; @@ -1004,7 +1005,7 @@ void registerSpace::getAllRegisterNames(std::vector &ret) { Register registerSpace::getRegByName(const std::string name) { map::iterator cur = registersByName.find(name); if (cur == registersByName.end()) - return REG_NULL; + return Null_Register; return (*cur).second; } diff --git a/dyninstAPI/src/registerSpace.h b/dyninstAPI/src/registerSpace.h index b386337985..a8e29632fb 100644 --- a/dyninstAPI/src/registerSpace.h +++ b/dyninstAPI/src/registerSpace.h @@ -35,10 +35,12 @@ #include #include +#include +#include #include #include #include -#include "common/src/Types.h" +#include "dyn_register.h" #include "inst.h" // callWhen... #include "bitArray.h" @@ -68,9 +70,9 @@ class baseTramp; class RealRegister { //This is currently only used on x86_32 to represent the - // virtual/real register difference. 'Register' still refers + // virtual/real register difference. 'Dyninst::Register' still refers // to virtual registers on this platform. Contained in a struct - // so that no one can accidently cast a Register into a RealRegister + // so that no one can accidently cast a Dyninst::Register into a RealRegister friend class registerSpace; signed int r; public: @@ -86,7 +88,7 @@ class RealRegister { class registerSlot { public: int alloc_num; //MATT TODO: Remove - const Register number; // what register is it, using our Register enum + const Dyninst::Register number; // what register is it, using our Dyninst::Register enum const std::string name; typedef enum { deadAlways, deadABI, liveAlways } initialLiveness_t; @@ -146,14 +148,20 @@ class registerSlot { // Don't want to use this... registerSlot() : alloc_num(0), - number(REG_NULL), + number(Dyninst::Null_Register), name("DEFAULT REGISTER"), initialState(deadAlways), offLimits(true), - type(invalid) + type(invalid), + refCount(0), + liveState(live), + keptValue(false), + beenUsed(false), + spilledState(unspilled), + saveOffset(-1) {} - registerSlot(Register num, + registerSlot(Dyninst::Register num, std::string name_, bool offLimits_, initialLiveness_t initial, @@ -229,39 +237,39 @@ class registerSpace { // memory (including the register itself), and stick it in actual register // destination. So the source is the label, and destination is an actual. // Size is a legacy parameter for places where we don't have register information - bool readProgramRegister(codeGen &gen, Register source, - Register destination, + bool readProgramRegister(codeGen &gen, Dyninst::Register source, + Dyninst::Register destination, unsigned size); // And the reverse - bool writeProgramRegister(codeGen &gen, Register destination, - Register source, + bool writeProgramRegister(codeGen &gen, Dyninst::Register destination, + Dyninst::Register source, unsigned size); - Register allocateRegister(codeGen &gen, bool noCost, bool realReg = false); - bool allocateSpecificRegister(codeGen &gen, Register r, bool noCost = true); + Dyninst::Register allocateRegister(codeGen &gen, bool noCost, bool realReg = false); + bool allocateSpecificRegister(codeGen &gen, Dyninst::Register r, bool noCost = true); // Like allocate, but don't keep it around; if someone else tries to // allocate they might get this one. - Register getScratchRegister(codeGen &gen, bool noCost = true, bool realReg = false); + Dyninst::Register getScratchRegister(codeGen &gen, bool noCost = true, bool realReg = false); // Like the above, but excluding a set of registers (that we don't want // to touch) - Register getScratchRegister(codeGen &gen, std::vector &excluded, bool noCost = true, bool realReg = false); + Dyninst::Register getScratchRegister(codeGen &gen, std::vector &excluded, bool noCost = true, bool realReg = false); - bool trySpecificRegister(codeGen &gen, Register reg, bool noCost = true); + bool trySpecificRegister(codeGen &gen, Dyninst::Register reg, bool noCost = true); bool saveAllRegisters(codeGen &gen, bool noCost); bool restoreAllRegisters(codeGen &gen, bool noCost); // For now, we save registers elsewhere and mark them here. - bool markSavedRegister(Register num, int offsetFromFP); + bool markSavedRegister(Dyninst::Register num, int offsetFromFP); bool markSavedRegister(RealRegister num, int offsetFromFP); // - bool markKeptRegister(Register num); + bool markKeptRegister(Dyninst::Register num); // Things that will be modified implicitly by anything else we // generate - condition registers, etc. @@ -270,11 +278,11 @@ class registerSpace { bool restoreVolatileRegisters(codeGen &gen); // Free the specified register (decrement its refCount) - void freeRegister(Register k); + void freeRegister(Dyninst::Register k); // Free the register even if its refCount is greater that 1 - void forceFreeRegister(Register k); + void forceFreeRegister(Dyninst::Register k); // And mark a register as not being kept any more - void unKeepRegister(Register k); + void unKeepRegister(Dyninst::Register k); // Mark all registers as unallocated, but keep live/dead info @@ -285,23 +293,23 @@ class registerSpace { // a scratch register; do that with trySpecificRegister // or allocateSpecificRegister. This is _ONLY_ to determine // if a register should be saved (e.g., over a call). - bool isFreeRegister(Register k); + bool isFreeRegister(Dyninst::Register k); // Checks to see if register starts live - bool isRegStartsLive(Register reg); - int fillDeadRegs(Register * deadRegs, int num); + bool isRegStartsLive(Dyninst::Register reg); + int fillDeadRegs(Dyninst::Register * deadRegs, int num); // Bump up the reference count. Occasionally, we underestimate it // and call this routine to correct this. - void incRefCount(Register k); + void incRefCount(Dyninst::Register k); // Reset when the regSpace is reset - marked offlimits for // allocation. - bool markReadOnly(Register k); - bool readOnlyRegister(Register k); + bool markReadOnly(Dyninst::Register k); + bool readOnlyRegister(Dyninst::Register k); // Make sure that no registers remain allocated, except "to_exclude" // Used for assertion checking. - void checkLeaks(Register to_exclude); + void checkLeaks(Dyninst::Register to_exclude); int getAddressWidth() { return addr_width; } void debugPrint(); @@ -320,9 +328,9 @@ class registerSpace { std::vector &trampRegs(); //realRegs() on x86-32, GPRs on all others - registerSlot *physicalRegs(Register reg) { return physicalRegisters_[reg]; } + registerSlot *physicalRegs(Dyninst::Register reg) { return physicalRegisters_[reg]; } - registerSlot *operator[](Register); + registerSlot *operator[](Dyninst::Register); // For platforms with "save all" semantics... bool anyLiveGPRsAtEntry() const; @@ -332,18 +340,18 @@ class registerSpace { /** * The following set of 'public' and 'private' methods and data deal with - * virtual registers, currently used only on x86. The above 'Register' class + * virtual registers, currently used only on x86. The above 'Dyninst::Register' class * allocates and uses virtual registers, these methods provide mappings from * virtual registers to real registers. **/ public: //Put VReg into RReg RealRegister loadVirtual(registerSlot *virt_r, codeGen &gen); - RealRegister loadVirtual(Register virt_r, codeGen &gen); + RealRegister loadVirtual(Dyninst::Register virt_r, codeGen &gen); //Put VReg into specific real register void loadVirtualToSpecific(registerSlot *virt_r, RealRegister real_r, codeGen &gen); - void loadVirtualToSpecific(Register virt_r, RealRegister real_r, codeGen &gen); + void loadVirtualToSpecific(Dyninst::Register virt_r, RealRegister real_r, codeGen &gen); //Spill away any virtual register in a real so that the real // can be used freely. Careful with this, no guarentee it won't @@ -351,17 +359,17 @@ class registerSpace { void makeRegisterAvail(RealRegister r, codeGen &gen); //Tell the tracker that we've manually put some virtual into a real - void noteVirtualInReal(Register v_r, RealRegister r_r); + void noteVirtualInReal(Dyninst::Register v_r, RealRegister r_r); void noteVirtualInReal(registerSlot *v_r, RealRegister r_r); //Like loadVirtual, but don't load orig value first - RealRegister loadVirtualForWrite(Register virt_r, codeGen &gen); + RealRegister loadVirtualForWrite(Dyninst::Register virt_r, codeGen &gen); RealRegister loadVirtualForWrite(registerSlot *virt_r, codeGen &gen); - void markVirtualDead(Register num); + void markVirtualDead(Dyninst::Register num); bool spilledAnything(); - Register pc_rel_reg; + Dyninst::Register pc_rel_reg; int pc_rel_use_count; int& pc_rel_offset(); void incStack(int val); @@ -404,16 +412,16 @@ class registerSpace { registerSpace(const registerSpace &); - registerSlot &getRegisterSlot(Register reg); + registerSlot &getRegisterSlot(Dyninst::Register reg); - registerSlot *findRegister(Register reg); + registerSlot *findRegister(Dyninst::Register reg); registerSlot *findRegister(RealRegister reg); - bool spillRegister(Register reg, codeGen &gen, bool noCost); - bool stealRegister(Register reg, codeGen &gen, bool noCost); + bool spillRegister(Dyninst::Register reg, codeGen &gen, bool noCost); + bool stealRegister(Dyninst::Register reg, codeGen &gen, bool noCost); - bool restoreRegister(Register reg, codeGen &gen, bool noCost); - bool popRegister(Register reg, codeGen &gen, bool noCost); + bool restoreRegister(Dyninst::Register reg, codeGen &gen, bool noCost); + bool popRegister(Dyninst::Register reg, codeGen &gen, bool noCost); bool markSavedRegister(registerSlot *num, int offsetFromFP); @@ -421,9 +429,9 @@ class registerSpace { // This structure is permanently tainted by its association with // virtual registers... - std::unordered_map registers_; + std::unordered_map registers_; - std::map physicalRegisters_; + std::map physicalRegisters_; // And convenience vectors std::vector GPRs_; @@ -447,7 +455,7 @@ class registerSpace { void specializeSpace(rs_location_t state); void specializeSpace(const bitArray &); - bool checkLive(Register reg, const bitArray &liveRegs); + bool checkLive(Dyninst::Register reg, const bitArray &liveRegs); unsigned addr_width; @@ -465,9 +473,9 @@ class registerSpace { fpr21, fpr22, fpr23, fpr24, fpr25, fpr26, fpr27, fpr28, fpr29, fpr30, fpr31, xer, lr, ctr, mq, cr, lastReg, ignored } powerRegisters_t; - static unsigned GPR(Register x) { return x; } - static unsigned FPR(Register x) { return x - fpr0; } - static unsigned SPR(Register x); + static unsigned GPR(Dyninst::Register x) { return x; } + static unsigned FPR(Dyninst::Register x) { return x - fpr0; } + static unsigned SPR(Dyninst::Register x); int framePointer() { return r1; } #endif #if defined(arch_x86) || defined(arch_x86_64) @@ -485,16 +493,16 @@ class registerSpace { fpr21, fpr22, fpr23, fpr24, fpr25, fpr26, fpr27, fpr28, fpr29, fpr30, fpr31, lr, sp, pc, pstate, fpcr, fpsr, ignored } aarch64Registers_t; - static unsigned GPR(Register x) { return x; } - static unsigned FPR(Register x) { return x - fpr0; } + static unsigned GPR(Dyninst::Register x) { return x; } + static unsigned FPR(Dyninst::Register x) { return x - fpr0; } int framePointer() { return r29; } #endif // Create a map of register names to register numbers - std::map registersByName; + std::map registersByName; // The reverse map can be handled by doing a rs[x]->name - Register getRegByName(const std::string name); - std::string getRegByNumber(Register num); + Dyninst::Register getRegByName(const std::string name); + std::string getRegByNumber(Dyninst::Register num); void getAllRegisterNames(std::vector &ret); diff --git a/dyninstAPI/src/syscallNotification.C b/dyninstAPI/src/syscallNotification.C index b5b298ec0b..19a61b610b 100644 --- a/dyninstAPI/src/syscallNotification.C +++ b/dyninstAPI/src/syscallNotification.C @@ -101,7 +101,7 @@ bool syscallNotification::installPreFork() { bool syscallNotification::installPostFork() { if (!PCEventMuxer::useBreakpoint(EventType(EventType::Post, EventType::Fork))) return true; - AstNodePtr returnVal = AstNode::operandNode(AstNode::ReturnVal, (void *)0); + AstNodePtr returnVal = AstNode::operandNode(AstNode::operandType::ReturnVal, (void *)0); postForkInst = new instMapping(getForkFuncName(), "DYNINST_instForkExit", FUNC_EXIT|FUNC_ARG, returnVal); @@ -121,7 +121,7 @@ bool syscallNotification::installPostFork() { bool syscallNotification::installPreExec() { if (!PCEventMuxer::useBreakpoint(EventType(EventType::Pre, EventType::Exec))) return true; - AstNodePtr arg0 = AstNode::operandNode(AstNode::Param, (void *)0); + AstNodePtr arg0 = AstNode::operandNode(AstNode::operandType::Param, (void *)0); preExecInst = new instMapping(getExecFuncName(), "DYNINST_instExecEntry", FUNC_ENTRY|FUNC_ARG, arg0); @@ -148,7 +148,7 @@ bool syscallNotification::installPostExec() { bool syscallNotification::installPreExit() { if (!PCEventMuxer::useBreakpoint(EventType(EventType::Pre, EventType::Exit))) return true; - AstNodePtr arg0 = AstNode::operandNode(AstNode::Param, (void *)0); + AstNodePtr arg0 = AstNode::operandNode(AstNode::operandType::Param, (void *)0); preExitInst = new instMapping(getExitFuncName(), "DYNINST_instExitEntry", FUNC_ENTRY|FUNC_ARG, arg0); diff --git a/dyninstAPI/src/syscallNotification.h b/dyninstAPI/src/syscallNotification.h index 782ebf40c8..5948556ada 100644 --- a/dyninstAPI/src/syscallNotification.h +++ b/dyninstAPI/src/syscallNotification.h @@ -62,7 +62,8 @@ class syscallNotification { syscallNotification() : preForkInst(NULL), postForkInst(NULL), preExecInst(NULL), postExecInst(NULL), - preExitInst(NULL), preLwpExitInst(NULL) + preExitInst(NULL), preLwpExitInst(NULL), + proc(NULL) { assert(0 && "ILLEGAL USE OF DEFAULT CONSTRUCTOR"); } syscallNotification(PCProcess *p) : diff --git a/dyninstAPI/src/syscalltrap.h b/dyninstAPI/src/syscalltrap.h index 27757cc34f..058c6c0b2b 100644 --- a/dyninstAPI/src/syscalltrap.h +++ b/dyninstAPI/src/syscalltrap.h @@ -34,7 +34,6 @@ #ifndef _SYSCALL_TRAP_H_ #define _SYSCALL_TRAP_H_ -#include "common/src/Types.h" /* * This file provides prototypes for the data structures which track diff --git a/dyninstAPI/src/trapMappings.h b/dyninstAPI/src/trapMappings.h index 60b7668295..5e98198c70 100644 --- a/dyninstAPI/src/trapMappings.h +++ b/dyninstAPI/src/trapMappings.h @@ -36,6 +36,7 @@ #include #include +#include "dyntypes.h" class AddressSpace; class int_variable; @@ -43,15 +44,15 @@ class int_variable; class trampTrapMappings { public: typedef struct { - Address from_addr; - Address to_addr; + Dyninst::Address from_addr; + Dyninst::Address to_addr; bool written; bool mutatee_side; unsigned cur_index; } tramp_mapping_t; private: - dyn_hash_map mapping; + dyn_hash_map mapping; std::set updated_mappings; static void arrange_mapping(tramp_mapping_t &m, bool should_sort, @@ -74,8 +75,8 @@ class trampTrapMappings { unsigned long table_used; unsigned long table_allocated; unsigned long table_mutatee_size; - Address current_table; - Address table_header; + Dyninst::Address current_table; + Dyninst::Address table_header; bool blockFlushes; public: @@ -83,9 +84,9 @@ class trampTrapMappings { void copyTrapMappings(trampTrapMappings *parent); void clearTrapMappings(); - void addTrapMapping(Address from, Address to, bool write_to_mutatee = false); - Address getTrapMapping(Address from); - bool definesTrapMapping(Address from); + void addTrapMapping(Dyninst::Address from, Dyninst::Address to, bool write_to_mutatee = false); + Dyninst::Address getTrapMapping(Dyninst::Address from); + bool definesTrapMapping(Dyninst::Address from); bool needsUpdating(); void flush(); void allocateTable(); diff --git a/dyninstAPI/src/unix.C b/dyninstAPI/src/unix.C index 868204d9ad..5e126dc611 100644 --- a/dyninstAPI/src/unix.C +++ b/dyninstAPI/src/unix.C @@ -30,6 +30,7 @@ // $Id: unix.C,v 1.243 2008/06/30 17:33:31 legendre Exp $ +#include #include "os.h" #include "debug.h" #include "mapped_object.h" @@ -185,7 +186,7 @@ bool PCProcess::instrumentMTFuncs() { for (unsigned j=0; jprettyName().c_str(), ps->mod()->fullName().c_str(), + ps->prettyName().c_str(), ps->mod()->fileName().c_str(), ps->addr()); } return false; @@ -530,11 +531,12 @@ bool PCProcess::hasPassedMain() bool PCProcess::startDebugger() { std::stringstream pidStr; pidStr << getPid(); + auto tmp = pidStr.str(); const char *args[4]; args[0] = dyn_debug_crash_debugger; args[1] = file_.c_str(); - args[2] = pidStr.str().c_str(); + args[2] = tmp.c_str(); args[3] = NULL; proccontrol_printf("%s[%d]: Launching %s %s %s\n", FILE__, __LINE__, @@ -666,7 +668,7 @@ mapped_object *BinaryEdit::openResolvedLibraryName(std::string filename, #include "dyninstAPI/src/mapped_object.h" #include "dyninstAPI/src/binaryEdit.h" #include "dyninstAPI/src/debug.h" -#include "boost/tuple/tuple.hpp" +#include "dyncompat/tuple/tuple.hpp" #include #if defined(os_linux) @@ -734,7 +736,7 @@ func_instance *block_instance::callee() { // Do this the hard way - an inter-module jump // get the target address of this function Address target_addr; bool success; - boost::tie(success, target_addr) = llb()->callTarget(); + std::tie(success, target_addr) = llb()->callTarget(); if(!success) { // this is either not a call instruction or an indirect call instr // that we can't get the target address @@ -743,45 +745,21 @@ func_instance *block_instance::callee() { // get the relocation information for this image Symtab *sym = obj()->parse_img()->getObject(); - std::vector fbt; - if (!sym->getFuncBindingTable(fbt)) { - return NULL; - } - - - /** - * Object files and static binaries will not have a function binding table - * because the function binding table holds relocations used by the dynamic - * linker - */ - if (!fbt.size() && !sym->isStaticBinary() && - sym->getObjectType() != obj_RelocatableFile ) - { - fprintf(stderr, "%s[%d]: WARN: zero func bindings\n", FILE__, __LINE__); - } - - std::map pltFuncs; - obj()->parse_img()->getPltFuncs(pltFuncs); - // find the target address in the list of relocationEntries - if (pltFuncs.find(target_addr) != pltFuncs.end()) { + relocationEntry function_binding; + if(sym->findPltEntryByTarget(target_addr, function_binding)) { Address base_addr = obj()->codeBase(); - for (u_int i=0; i < fbt.size(); i++) { - if (fbt[i].target_addr() == target_addr) - { // check to see if this function has been bound yet...if the // PLT entry for this function has been modified by the runtime // linker func_instance *target_pdf = 0; - if (proc()->hasBeenBound(fbt[i], target_pdf, base_addr)) { + if (proc()->hasBeenBound(function_binding, target_pdf, base_addr)) { updateCallTarget(target_pdf); obj()->setCalleeName(this, target_pdf->symTabName()); obj()->setCallee(this, target_pdf); return target_pdf; } - } - } - return callee(pltFuncs[target_addr]); + return callee(function_binding.name()); } else { /* * Sometimes, the PLT address and the CFG target aren't the same diff --git a/dyninstAPI/src/unix.h b/dyninstAPI/src/unix.h index 6cfe204830..a1b7016f39 100644 --- a/dyninstAPI/src/unix.h +++ b/dyninstAPI/src/unix.h @@ -108,6 +108,7 @@ typedef pthread_cond_t EventCond_t; #define STRERROR(x,y) strerror(x) #endif +#include #include #include #include diff --git a/dyninstAPI/src/util.h b/dyninstAPI/src/util.h index fb592f05f7..0036b9766d 100644 --- a/dyninstAPI/src/util.h +++ b/dyninstAPI/src/util.h @@ -34,12 +34,12 @@ #define UTIL_H #ifndef FILE__ +#include #define FILE__ strrchr(__FILE__, '/') ? strrchr(__FILE__, '/') + 1 : __FILE__ #endif #include #include "common/src/headers.h" -#include "common/src/Types.h" #include "common/src/stats.h" extern void printDyninstStats(); diff --git a/dyninstAPI_RT/CMakeLists.txt b/dyninstAPI_RT/CMakeLists.txt index 0055e0194b..4ff4e9fcfd 100644 --- a/dyninstAPI_RT/CMakeLists.txt +++ b/dyninstAPI_RT/CMakeLists.txt @@ -1,257 +1,143 @@ -# CMake configuration for dyninstAPI_RT directory -cmake_minimum_required (VERSION 2.6.4) -project (DyninstRT C) +include_guard(GLOBAL) -set (DYNINST_ROOT ${PROJECT_SOURCE_DIR}/..) +include(DyninstLibrary) -include (${DYNINST_ROOT}/cmake/shared.cmake) +set(_public_headers h/dyninstAPI_RT.h h/dyninstRTExport.h) -include_directories ( - ${DYNINST_ROOT}/dyninstAPI_RT/src - ${DYNINST_ROOT}/dyninstAPI_RT/h - ${DYNINST_ROOT} - ) +set(_private_headers src/RTcommon.h src/RTheap.h src/RTthread.h) -set (SRC_LIST - src/RTcommon.c - src/RTmemEmulator.c -) +set(_sources src/RTcommon.c src/RTheap.c src/RTthread.c) -if (PLATFORM MATCHES freebsd) -set (SRC_LIST ${SRC_LIST} +if(DYNINST_OS_FreeBSD) + list( + APPEND + _sources src/RTposix.c - src/RTfreebsd.c - src/RTheap.c - src/RTheap-freebsd.c - src/RTthread.c - src/RTspace.S - src/RTsignal.c -) -elseif (PLATFORM MATCHES linux) -set (SRC_LIST ${SRC_LIST} - src/RTposix.c - src/RTlinux.c - src/RTheap.c - src/RTheap-linux.c - src/RTthread.c - src/RTspace.S - src/RTsignal.c -) -set (RT_STATIC_ONLY_SRC_LIST ${RT_STATIC_ONLY_SRC_LIST} - src/RTstatic_ctors_dtors_begin.c - src/RTstatic_ctors_dtors_end.c -) -elseif (PLATFORM MATCHES nt OR PLATFORM MATCHES windows) -set (SRC_LIST ${SRC_LIST} - src/RTheap.c - src/RTheap-win.c - src/RTwinnt.c - src/RTthread.c - src/RTthread-x86.c -) -endif () - -set (SRC_LIST_i386 - src/RTthread-x86.c - src/RTtlsgetaddr-x86.S -) -set (RT_STATIC_ONLY_SRC_LIST_i386 - src/RTstatic_ctors_dtors-x86.c -) -set (SRC_LIST_x86_64 - src/RTthread-x86-64.c - src/RTtlsgetaddr-x86.S -) -set (RT_STATIC_ONLY_SRC_LIST_x86_64 - src/RTstatic_ctors_dtors-x86.c -) -set (SRC_LIST_ppc32 - src/RTthread-powerpc.c - src/RTthread-powerpc-asm.S -) -set (RT_STATIC_ONLY_SRC_LIST_ppc32 - src/RTstatic_ctors_dtors-ppc32.c -) -set (SRC_LIST_ppc64 - src/RTthread-powerpc.c - src/RTthread-powerpc-asm.S -) -set (RT_STATIC_ONLY_SRC_LIST_ppc64 - src/RTstatic_ctors_dtors-ppc64.c -) -set (SRC_LIST_aarch64 - src/RTthread-aarch64.c - #src/RTthread-aarch64-asm.S -) -set (RT_STATIC_ONLY_SRC_LIST_aarch64 - src/RTstatic_ctors_dtors-aarch64.c -) - - -# We use gcc to compile the various assembly files, but -# cmake doesn't default to knowing that gcc can -# handle .S. -ENABLE_LANGUAGE(ASM) -file (GLOB SRC_ASSEMBLY "src/*.S") -if(NEED_NATIVE_ASSEMBER MATCHES YES) -set_source_files_properties(${SRC_ASSEMBLY} - PROPERTIES - LANGUAGE ASM) -else() -set_source_files_properties(${SRC_ASSEMBLY} - PROPERTIES - LANGUAGE C) + src/RTfreebsd.c + src/RTheap-freebsd.c + src/RTspace.S + src/RTsignal.c) +elseif(DYNINST_OS_Linux) + set(_static_sources src/RTstatic_ctors_dtors_begin.c src/RTstatic_ctors_dtors_end.c) + list( + APPEND + _sources + src/RTposix.c + src/RTlinux.c + src/RTheap-linux.c + src/RTspace.S + src/RTsignal.c) +elseif(DYNINST_OS_Windows) + list(APPEND _sources src/RTheap-win.c src/RTwinnt.c src/RTthread-x86.c) endif() # The arch-specific files other than RTthread-x86 are Unix-only. -if(UNIX) -if (PLATFORM MATCHES amd64 OR PLATFORM MATCHES x86_64) -set (SRC_LIST_mabi ${SRC_LIST} ${SRC_LIST_i386}) -set (RT_STATIC_ONLY_SRC_LIST_mabi ${RT_STATIC_ONLY_SRC_LIST} ${RT_STATIC_ONLY_SRC_LIST_i386}) -set (SRC_LIST ${SRC_LIST} ${SRC_LIST_x86_64}) -set (RT_STATIC_ONLY_SRC_LIST ${RT_STATIC_ONLY_SRC_LIST} ${RT_STATIC_ONLY_SRC_LIST_x86_64}) -elseif (PLATFORM MATCHES ppc64) -set (SRC_LIST_mabi ${SRC_LIST} ${SRC_LIST_ppc32}) -set (RT_STATIC_ONLY_SRC_LIST_mabi ${RT_STATIC_ONLY_SRC_LIST} ${RT_STATIC_ONLY_SRC_LIST_ppc32}) -set (SRC_LIST ${SRC_LIST} ${SRC_LIST_ppc64}) -set (RT_STATIC_ONLY_SRC_LIST ${RT_STATIC_ONLY_SRC_LIST} ${RT_STATIC_ONLY_SRC_LIST_ppc64}) -elseif (PLATFORM MATCHES i386) -set (SRC_LIST ${SRC_LIST} ${SRC_LIST_i386}) -set (RT_STATIC_ONLY_SRC_LIST ${RT_STATIC_ONLY_SRC_LIST} ${RT_STATIC_ONLY_SRC_LIST_i386}) -elseif (PLATFORM MATCHES ppc32) -set (SRC_LIST ${SRC_LIST} ${SRC_LIST_ppc32}) -set (RT_STATIC_ONLY_SRC_LIST ${RT_STATIC_ONLY_SRC_LIST} ${RT_STATIC_ONLY_SRC_LIST_ppc32}) -elseif (PLATFORM MATCHES aarch64) -set (SRC_LIST ${SRC_LIST} ${SRC_LIST_aarch64}) -set (RT_STATIC_ONLY_SRC_LIST ${RT_STATIC_ONLY_SRC_LIST} ${RT_STATIC_ONLY_SRC_LIST_aarch64}) -endif() -endif() - -add_library (dyninstAPI_RT SHARED ${SRC_LIST}) -if(TARGET TBB) - add_dependencies(dyninstAPI_RT TBB) -endif() - -if (NOT PLATFORM MATCHES nt AND NOT PLATFORM MATCHES windows) - target_link_libraries (dyninstAPI_RT ${CMAKE_DL_LIBS}) -else() # windows - target_link_libraries (dyninstAPI_RT ws2_32 dbghelp psapi) -endif() - -add_library (dyninstAPI_RT_static STATIC ${SRC_LIST} ${RT_STATIC_ONLY_SRC_LIST}) -if(TARGET TBB) - add_dependencies(dyninstAPI_RT_static TBB) +if(DYNINST_OS_UNIX) + if(DYNINST_ARCH_x86_64) + list(APPEND _sources src/RTthread-x86-64.c src/RTtlsgetaddr-x86.S) + elseif(DYNINST_ARCH_i386) + list(APPEND _sources src/RTthread-x86.c src/RTtlsgetaddr-x86.S) + elseif(DYNINST_ARCH_ppc64le) + list(APPEND _sources src/RTthread-powerpc.c src/RTthread-powerpc-asm.S) + elseif(DYNINST_ARCH_aarch64) + list(APPEND _sources src/RTthread-aarch64.c) + endif() + + if(DYNINST_ARCH_x86_64) + list(APPEND _static_sources src/RTstatic_ctors_dtors-x86.c) + elseif(DYNINST_ARCH_i386) + list(APPEND _static_sources src/RTstatic_ctors_dtors-x86.c) + elseif(DYNINST_ARCH_ppc64le) + list(APPEND _static_sources src/RTstatic_ctors_dtors-ppc64.c) + elseif(DYNINST_ARCH_aarch64) + list(APPEND _static_sources src/RTstatic_ctors_dtors-aarch64.c) + endif() endif() -# this should carry over from CMakeLists.txt -set_target_properties (dyninstAPI_RT - PROPERTIES - OUTPUT_NAME dyninstAPI_RT - SOVERSION ${SOVERSION} - VERSION ${LIBVERSION}) - -# this will not -set_target_properties (dyninstAPI_RT_static - PROPERTIES - OUTPUT_NAME dyninstAPI_RT - COMPILE_DEFINITIONS DYNINST_RT_STATIC_LIB) - -set_target_properties (dyninstAPI_RT PROPERTIES CLEAN_DIRECT_OUTPUT 1) -set_target_properties (dyninstAPI_RT_static PROPERTIES CLEAN_DIRECT_OUTPUT 1) - - -message(STATUS "dyninstAPI RT library SOVERSION: ${SOVERSION}") -message(STATUS "dyninstAPI RT library LIBVERSION: ${LIBVERSION}") - -FILE (GLOB headers "h/*.h") -# append, you fool! -set_target_properties (dyninstAPI_RT dyninstAPI_RT_static PROPERTIES PUBLIC_HEADER "${headers}") - -INSTALL (TARGETS dyninstAPI_RT dyninstAPI_RT_static - EXPORT DyninstTargets - RUNTIME DESTINATION ${INSTALL_LIB_DIR} - LIBRARY DESTINATION ${INSTALL_LIB_DIR} - ARCHIVE DESTINATION ${INSTALL_LIB_DIR} - PUBLIC_HEADER DESTINATION ${INSTALL_INCLUDE_DIR}) - -# Test to see if we want the 32-bit library - -if (SRC_LIST_mabi) - -# The following code is from CheckCCompilerFlag.cmake. It uses a -# simple program that can be compiled even if 32-bit includes are -# missing; we need to extend it somewhat - -INCLUDE(CheckCSourceCompiles) - -MACRO (CHECK_C_COMPILER_FLAG_EXTENDED _FLAG _RESULT) - SET(SAFE_CMAKE_C_FLAGS "${CMAKE_C_FLAGS}") - SET(CMAKE_C_FLAGS "${_FLAG}") - -# Addition here: use signal.h - CHECK_C_SOURCE_COMPILES("#include - int main(void) { return 0; }" - ${_RESULT} -# End addition - # Some compilers do not fail with a bad flag - FAIL_REGEX "warning: command line option .* is valid for .* but not for C" - # Apple gcc - FAIL_REGEX "unrecognized .*option" # GNU - FAIL_REGEX "unknown .*option" # Clang - FAIL_REGEX "ignoring unknown option" # MSVC - FAIL_REGEX "warning D9002" # MSVC, any lang - FAIL_REGEX "[Uu]nknown option" # HP - FAIL_REGEX "[Ww]arning: [Oo]ption" # SunPro - FAIL_REGEX "command option .* is not recognized" # XL - ) - SET(CMAKE_C_FLAGS "${SAFE_CMAKE_C_FLAGS}") -ENDMACRO (CHECK_C_COMPILER_FLAG_EXTENDED) - - -message (STATUS "Checking for 32-bit runtime library...") - -CHECK_C_COMPILER_FLAG_EXTENDED ("-m32" CHECK_RT_LIB_32) -if (CHECK_RT_LIB_32 AND NOT ${BUILD_RTLIB_32} MATCHES "OFF") -message (STATUS "Enabling 32-bit runtime library; change BUILD_RTLIB_32 to OFF to disable") -SET (BUILD_RTLIB_32 ON) -ELSE () -message (STATUS "Disabling 32-bit runtime library; change BUILD_RTLIB_32 to ON and install 32-bit build environment to enable") -SET (BUILD_RTLIB_32 OFF) -ENDIF() - -if (BUILD_RTLIB_32 MATCHES "ON") - -add_library (dyninstAPI_RT_m32 SHARED ${SRC_LIST_mabi}) -target_link_libraries (dyninstAPI_RT_m32 ${CMAKE_DL_LIBS}) -add_library (dyninstAPI_RT_m32_static STATIC ${SRC_LIST_mabi} ${RT_STATIC_ONLY_SRC_LIST_mabi}) - -set_target_properties (dyninstAPI_RT_m32 - PROPERTIES - COMPILE_FLAGS "-DMUTATEE_32 -m32" - LINK_FLAGS "-m32" - OUTPUT_NAME dyninstAPI_RT_m32 - SOVERSION ${SOVERSION} - VERSION ${LIBVERSION}) - -set_target_properties (dyninstAPI_RT_m32_static - PROPERTIES - OUTPUT_NAME dyninstAPI_RT_m32 - COMPILE_FLAGS "-DMUTATEE_32 -m32" - LINK_FLAGS "-m32" - COMPILE_DEFINITIONS DYNINST_RT_STATIC_LIB) - -set_target_properties (dyninstAPI_RT_m32 PROPERTIES CLEAN_DIRECT_OUTPUT 1) -set_target_properties (dyninstAPI_RT_m32_static PROPERTIES CLEAN_DIRECT_OUTPUT 1) - -INSTALL (TARGETS dyninstAPI_RT_m32 dyninstAPI_RT_m32_static - EXPORT DyninstTargets - RUNTIME DESTINATION ${INSTALL_LIB_DIR} - LIBRARY DESTINATION ${INSTALL_LIB_DIR} - ARCHIVE DESTINATION ${INSTALL_LIB_DIR} - PUBLIC_HEADER DESTINATION ${INSTALL_INCLUDE_DIR}) - -install (EXPORT DyninstTargets - DESTINATION "${INSTALL_CMAKE_DIR}") - -endif() +# cmake-format: off +dyninst_library( + dyninstAPI_RT + PUBLIC_HEADER_FILES ${_public_headers} + PRIVATE_HEADER_FILES ${_private_headers} + SOURCE_FILES ${_sources} + DYNINST_DEPS common + PRIVATE_DEPS Threads::Threads + FORCE_STATIC +) +# cmake-format: on + +foreach(t ${dyninstAPI_RT_TARGETS}) + if(DYNINST_OS_UNIX) + target_link_libraries(${t} PRIVATE ${CMAKE_DL_LIBS}) + elseif(DYNINST_OS_Windows) + target_link_libraries(${t} PRIVATE ws2_32 dbghelp psapi) + endif() + + if(${t} MATCHES "static") + target_sources(${t} PRIVATE ${_static_sources}) + target_compile_definitions(${t} PRIVATE DYNINST_RT_STATIC_LIB) + endif() + + # Both shared and static should be named 'dyninstAPI_RT'- only extension differs + set_property(TARGET ${t} PROPERTY OUTPUT_NAME dyninstAPI_RT) +endforeach() + +if(BUILD_RTLIB_32) + include(CheckCCompilerFlag) + + # '-m32' is really a linker option, but CMAKE_REQUIRED_LINK_OPTIONS isn't available until + # cmake-3.14.0, so hijack the libraries argument instead. + set(_m ${CMAKE_REQUIRED_LIBRARIES}) + list(APPEND CMAKE_REQUIRED_LIBRARIES "-m32") + check_c_compiler_flag("-m32" _has_mabi) + set(CMAKE_REQUIRED_LIBRARIES ${_m}) + unset(_m) + + if(NOT _has_mabi) + message(FATAL_ERROR "BUILD_RTLIB_32 enabled, but compiler doesn't support '-m32'") + endif() + + if(NOT DYNINST_OS_UNIX) + message(FATAL_ERROR "32-bit runtime is only supported on Unixes") + endif() + + if(NOT DYNINST_ARCH_x86_64 AND NOT DYNINST_ARCH_i386) + message(FATAL_ERROR "32-bit runtime is only supported on i386 and x86_64") + endif() + + if(DYNINST_ARCH_x86_64) + # We're cross-compiling, so remove the x86_64 thread stuff + list(FILTER _sources EXCLUDE REGEX "RTthread-x86-64") + endif() + + # cmake-format: off + # The headers are all listed as PRIVATE so that they do not get copied into the install + # tree twice (they already get copied in by the creation of the shared library targets) + dyninst_library( + dyninstAPI_RT_m32 + PRIVATE_HEADER_FILES ${_public_headers} ${_private_headers} + SOURCE_FILES ${_sources} src/RTthread-x86.c src/RTtlsgetaddr-x86.S + DEFINES "MUTATEE_32" + PRIVATE_DEPS Threads::Threads + ) + # cmake-format: on + + foreach(t ${dyninstAPI_RT_m32_TARGETS}) + target_compile_options(${t} PRIVATE "-m32") + target_link_options(${t} PRIVATE "-m32") + + target_include_directories( + ${t} BEFORE PRIVATE "$") + + if(DYNINST_OS_UNIX) + target_link_libraries(${t} PRIVATE ${CMAKE_DL_LIBS}) + elseif(DYNINST_OS_Windows) + target_link_libraries(${t} PRIVATE ws2_32 dbghelp psapi) + endif() + + if(${t} MATCHES "static") + target_sources(${t} PRIVATE ${static_sources} src/RTstatic_ctors_dtors-x86.c) + target_compile_definitions(${t} PRIVATE DYNINST_RT_STATIC_LIB) + endif() + endforeach() endif() diff --git a/dyninstAPI_RT/h/dyninstAPI_RT.h b/dyninstAPI_RT/h/dyninstAPI_RT.h index 0c14df3c92..f7c3117ff2 100644 --- a/dyninstAPI_RT/h/dyninstAPI_RT.h +++ b/dyninstAPI_RT/h/dyninstAPI_RT.h @@ -54,8 +54,9 @@ #define DYNINST_BREAKPOINT_SIGNUM (SIGRTMIN+4) #include +#include #include "dyninstRTExport.h" -#include "common/src/Types.h" +#include "common/h/compiler_diagnostics.h" /* If we must make up a boolean type, we should make it unique */ typedef unsigned char RT_Boolean; @@ -166,15 +167,10 @@ typedef struct { #define TRAP_HEADER_SIG 0x759191D6 #define DT_DYNINST 0x6D191957 -#if defined(_MSC_VER) -#pragma warning(disable:4200) -#endif -#if defined(__GNUC__) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -// Disable warning about flexible array members in C++ -// FIXME: Flexible array member, traps[], in structure below -#endif +// Suppress warning about flexible array members not valid in C++ +// FIXME: invalid flexible array member, traps[], in structure below +DYNINST_DIAGNOSTIC_BEGIN_SUPPRESS_FLEX_ARRAY + struct trap_mapping_header { uint32_t signature; uint32_t num_entries; @@ -184,9 +180,8 @@ struct trap_mapping_header { uint64_t high_entry; trapMapping_t traps[]; //Don't change this to a pointer, despite any compiler warnings }; -#if defined(__GNUC__) -#pragma GCC diagnostic pop -#endif + +DYNINST_DIAGNOSTIC_END_SUPPRESS_FLEX_ARRAY #define MAX_MEMORY_MAPPER_ELEMENTS 1024 @@ -244,7 +239,5 @@ struct MemoryMapper64 { DLLEXPORT extern struct MemoryMapper RTmemoryMapper; -extern int RTuntranslatedEntryCounter; - #include "dyninstRTExport.h" #endif /* _DYNINSTAPI_RT_H */ diff --git a/dyninstAPI_RT/h/dyninstRTExport.h b/dyninstAPI_RT/h/dyninstRTExport.h index ed9f9c3016..c65b37702a 100644 --- a/dyninstAPI_RT/h/dyninstRTExport.h +++ b/dyninstAPI_RT/h/dyninstRTExport.h @@ -35,6 +35,8 @@ libraries. */ +#include + #if !defined(DLLEXPORT) #if defined (_MSC_VER) /* If we're on Windows, we need to explicetely export these functions: */ @@ -60,7 +62,7 @@ DLLEXPORT int DYNINSTuserMessage(void *msg, unsigned int msg_size); /* Returns the number of threads DYNINST currently knows about. (Which may differ at certain times from the number of threads actually present.) */ -DLLEXPORT int DYNINSTthreadCount(); +DLLEXPORT int DYNINSTthreadCount(void); /** * These function implement a locking mechanism that can be used by @@ -97,14 +99,11 @@ DLLEXPORT void dyninst_unlock(dyninst_lock_t *lock); * Internal functions that we export to ensure they show up. **/ -DLLEXPORT void DYNINSTsafeBreakPoint(); -DLLEXPORT void DYNINSTinit(); -DLLEXPORT void DYNINST_snippetBreakpoint(); +DLLEXPORT void DYNINSTsafeBreakPoint(void); +DLLEXPORT void DYNINSTinit(void); +DLLEXPORT void DYNINST_snippetBreakpoint(void); DLLEXPORT void DYNINST_stopThread(void *, void *, void *, void *); DLLEXPORT void DYNINST_stopInterProc(void *, void *, void *, void *, void *, void *); -DLLEXPORT void RThandleShadow(void *, void *, void *, void *, void *); -DLLEXPORT unsigned long RTtranslateMemory(unsigned long, unsigned long, unsigned long); -DLLEXPORT unsigned long RTtranslateMemoryShift(unsigned long, unsigned long, unsigned long); DLLEXPORT void *DYNINSTos_malloc(size_t, void *, void *); DLLEXPORT int DYNINSTloadLibrary(char *); diff --git a/dyninstAPI_RT/src/RTcommon.c b/dyninstAPI_RT/src/RTcommon.c index 7454d5821f..f27cd56ece 100644 --- a/dyninstAPI_RT/src/RTcommon.c +++ b/dyninstAPI_RT/src/RTcommon.c @@ -134,13 +134,13 @@ int fakeTickCount; // https://sourceware.org/bugzilla/show_bug.cgi?id=14898 static TLS_VAR short DYNINST_tls_tramp_guard = 1; -DLLEXPORT int DYNINST_lock_tramp_guard() +DLLEXPORT int DYNINST_lock_tramp_guard(void) { if(!DYNINST_tls_tramp_guard) return 0; DYNINST_tls_tramp_guard = 0; return 1; } -DLLEXPORT void DYNINST_unlock_tramp_guard() +DLLEXPORT void DYNINST_unlock_tramp_guard(void) { DYNINST_tls_tramp_guard = 1; } @@ -154,7 +154,7 @@ DECLARE_DYNINST_LOCK(DYNINST_trace_lock); * in initFPU **/ double DYNINSTdummydouble = 4321.71; -static void initFPU() +static void initFPU(void) { double x = 17.1234; DYNINSTdummydouble *= x; @@ -164,15 +164,13 @@ static void initFPU() * This function is called in both static and dynamic rewriting, on * all platforms that support binary rewriting, but before DYNINSTinit **/ -void DYNINSTBaseInit() +void DYNINSTBaseInit(void) { #if defined(cap_mutatee_traps) DYNINSTinitializeTrapHandler(); #endif DYNINST_unlock_tramp_guard(); DYNINSThasInitialized = 1; - - RTuntranslatedEntryCounter = 0; } /** @@ -187,7 +185,7 @@ void DYNINSTBaseInit() * This is only called in the Dynamic instrumentation case. Static * libraries don't call this. **/ -void DYNINSTinit() +void DYNINSTinit(void) { rtdebug_printf("%s[%d]: DYNINSTinit: welcome to DYNINSTinit()\n", __FILE__, __LINE__); initFPU(); @@ -217,13 +215,13 @@ void DYNINSTinit() * Does what it's called. Used by the paradyn daemon as a default in certain * cases (MT in particular) **/ -int DYNINSTreturnZero() +int DYNINSTreturnZero(void) { return 0; } /* Used to by dyninst breakpoint snippet */ -void DYNINST_snippetBreakpoint() { +void DYNINST_snippetBreakpoint(void) { tc_lock_lock(&DYNINST_trace_lock); /* Set the state so the mutator knows what's up */ @@ -238,7 +236,7 @@ void DYNINST_snippetBreakpoint() { } /* Used to instrument (and report) the entry of fork */ -DLLEXPORT void DYNINST_instForkEntry() { +DLLEXPORT void DYNINST_instForkEntry(void) { tc_lock_lock(&DYNINST_trace_lock); /* Set the state so the mutator knows what's up */ @@ -742,7 +740,7 @@ void* dyninstTrapTranslate(void *source, return target; } -DLLEXPORT void DYNINSTtrapFunction(){ +DLLEXPORT void DYNINSTtrapFunction(void){ __asm__ __volatile__( "nop\n" :::); diff --git a/dyninstAPI_RT/src/RTcommon.h b/dyninstAPI_RT/src/RTcommon.h index 398173b961..7314b7e1b8 100644 --- a/dyninstAPI_RT/src/RTcommon.h +++ b/dyninstAPI_RT/src/RTcommon.h @@ -33,19 +33,20 @@ #include "dyninstAPI_RT/h/dyninstAPI_RT.h" #include "RTthread.h" +#include #include #include "common/h/compiler_annotations.h" -void DYNINSTtrapFunction(); -void DYNINSTbreakPoint(); +void DYNINSTtrapFunction(void); +void DYNINSTbreakPoint(void); /* Use a signal that is safe if we're not attached. */ -void DYNINSTsafeBreakPoint(); -void DYNINSTinit(); -int DYNINSTreturnZero(); +void DYNINSTsafeBreakPoint(void); +void DYNINSTinit(void); +int DYNINSTreturnZero(void); int DYNINSTwriteEvent(void *ev, size_t sz); int DYNINSTasyncConnect(int pid); -int DYNINSTinitializeTrapHandler(); +int DYNINSTinitializeTrapHandler(void); void* dyninstTrapTranslate(void *source, volatile unsigned long *table_used, volatile unsigned long *table_version, diff --git a/dyninstAPI_RT/src/RTfreebsd.c b/dyninstAPI_RT/src/RTfreebsd.c index 17ce671c40..92ef807012 100644 --- a/dyninstAPI_RT/src/RTfreebsd.c +++ b/dyninstAPI_RT/src/RTfreebsd.c @@ -399,7 +399,7 @@ static struct link_map *getLinkMap() { // Rewind the current link map pointer to find the // start of the list - struct link_map *last_map; + struct link_map *last_map = NULL; while( map != NULL ) { last_map = map; map = map->l_prev; diff --git a/dyninstAPI_RT/src/RTheap-linux.c b/dyninstAPI_RT/src/RTheap-linux.c index 64cfb06bfb..2fcb1aa026 100644 --- a/dyninstAPI_RT/src/RTheap-linux.c +++ b/dyninstAPI_RT/src/RTheap-linux.c @@ -31,6 +31,8 @@ /* $Id: RTheap-linux.c,v 1.9 2008/01/31 18:01:54 legendre Exp $ */ /* RTheap-linux.c: Linux-specific heap components */ +#define _GNU_SOURCE + #include #include #include /* str* */ @@ -42,6 +44,7 @@ #include /* sbrk(), read(), mmap */ #include /* mmap() */ #include "RTheap.h" +#include "dyntypes.h" #if 1 //defined(MUTATEE64) diff --git a/dyninstAPI_RT/src/RTheap.c b/dyninstAPI_RT/src/RTheap.c index 33195e06e3..17b0f66cc3 100644 --- a/dyninstAPI_RT/src/RTheap.c +++ b/dyninstAPI_RT/src/RTheap.c @@ -31,6 +31,8 @@ /* $Id: RTheap.c,v 1.25 2006/05/03 00:31:25 jodom Exp $ */ /* RTheap.c: platform-generic heap management */ +#define _GNU_SOURCE + #include #include #if !defined(os_windows) /* ccw 15 may 2000 : 29 mar 2001 */ @@ -49,6 +51,7 @@ extern int getpagesize(); #include "dyninstAPI_RT/src/RTheap.h" #include "dyninstAPI_RT/src/RTcommon.h" +#include "unaligned_memory_access.h" typedef enum { @@ -140,7 +143,7 @@ void *DYNINSTos_malloc(size_t nbytes, void *lo_addr, void *hi_addr) } /* define new heap */ - node = (heapList_t*) (ret_heap + size); + node = CAST_WITHOUT_ALIGNMENT_WARNING(heapList_t*, (ret_heap + size)); node->heap.ret_addr = (void *)ret_heap; node->heap.addr = heap; node->heap.len = size_heap; @@ -153,7 +156,7 @@ void *DYNINSTos_malloc(size_t nbytes, void *lo_addr, void *hi_addr) heap = (char*)trymmap(size + sizeof(struct heapList_t), lo, hi, psize, -1); if(!heap) return NULL; - node = (heapList_t*) (heap + size); + node = CAST_WITHOUT_ALIGNMENT_WARNING(heapList_t*, (heap + size)); /* define new heap */ node->heap.addr = heap; diff --git a/dyninstAPI_RT/src/RTheap.h b/dyninstAPI_RT/src/RTheap.h index 1fb6703248..60bf63d316 100644 --- a/dyninstAPI_RT/src/RTheap.h +++ b/dyninstAPI_RT/src/RTheap.h @@ -34,6 +34,7 @@ #define _RT_HEAP_H #include "dyninstAPI_RT/h/dyninstAPI_RT.h" /* RT_Boolean, Address */ +#include "dyntypes.h" #if defined(os_linux) || defined(os_freebsd) @@ -68,7 +69,7 @@ extern int DYNINSTheap_mmapFlags; */ RT_Boolean DYNINSTheap_useMalloc(void *lo, void *hi); -int DYNINSTheap_mmapFdOpen(); +int DYNINSTheap_mmapFdOpen(void); void DYNINSTheap_mmapFdClose(int fd); int DYNINSTheap_getMemoryMap(unsigned *, dyninstmm_t **mmap); diff --git a/dyninstAPI_RT/src/RTlinux.c b/dyninstAPI_RT/src/RTlinux.c index 44ac47d146..dde8c31531 100644 --- a/dyninstAPI_RT/src/RTlinux.c +++ b/dyninstAPI_RT/src/RTlinux.c @@ -33,9 +33,12 @@ * RTlinux.c: mutatee-side library function specific to Linux ************************************************************************/ +#define _GNU_SOURCE + #include "dyninstAPI_RT/h/dyninstAPI_RT.h" #include "dyninstAPI_RT/src/RTthread.h" #include "dyninstAPI_RT/src/RTcommon.h" +#include "unaligned_memory_access.h" #include #include #include @@ -103,7 +106,7 @@ int t_kill(int pid, int sig) { return (result == 0); } -void DYNINSTbreakPoint() +void DYNINSTbreakPoint(void) { if (DYNINSTstaticMode) return; @@ -119,7 +122,7 @@ void uncaught_breakpoint(int sig) failed_breakpoint = 1; } -void DYNINSTsafeBreakPoint() +void DYNINSTsafeBreakPoint(void) { if (DYNINSTstaticMode) return; @@ -129,7 +132,7 @@ void DYNINSTsafeBreakPoint() kill(dyn_lwp_self(), SIGSTOP); } -void mark_heaps_exec() { +void mark_heaps_exec(void) { /* Grab the page size, to align the heap pointer. */ long int pageSize = sysconf( _SC_PAGESIZE ); if( pageSize == 0 || pageSize == - 1 ) { @@ -186,7 +189,7 @@ typedef struct dlopen_args { void *(*DYNINST_do_dlopen)(dlopen_args_t *) = NULL; -static int get_dlopen_error() { +static int get_dlopen_error(void) { char *err_str; err_str = dlerror(); if (err_str) { @@ -255,7 +258,7 @@ int DYNINSTloadLibrary(char *libname) #endif -int dyn_lwp_self() +int dyn_lwp_self(void) { static int gettid_not_valid = 0; int result; @@ -272,14 +275,14 @@ int dyn_lwp_self() return result; } -int dyn_pid_self() +int dyn_pid_self(void) { return getpid(); } dyntid_t (*DYNINST_pthread_self)(void); -dyntid_t dyn_pthread_self() +dyntid_t dyn_pthread_self(void) { dyntid_t me; if (DYNINSTstaticMode) { @@ -331,8 +334,6 @@ int DYNINST_am_initial_thread( dyntid_t tid ) { #elif defined(arch_power) #if defined(arch_64bit) #define UC_PC(x) x->uc_mcontext.regs->nip - #else // 32-bit - #define UC_PC(x) x->uc_mcontext.uc_regs->gregs[32] #endif // power #elif defined(arch_aarch64) //#warning "UC_PC: in aarch64, pc is not directly accessable." @@ -387,7 +388,7 @@ void dyninstTrapHandler(int sig, siginfo_t *sg, ucontext_t *context) assert(hdr); volatile trapMapping_t *mapping = &(hdr->traps[0]); trap_to = dyninstTrapTranslate(orig_ip, - (unsigned long *) &hdr->num_entries, + CAST_WITHOUT_ALIGNMENT_WARNING(unsigned long *, &hdr->num_entries), &zero, &mapping, &one); @@ -406,10 +407,9 @@ void dyninstTrapHandler(int sig, siginfo_t *sg, ucontext_t *context) #if defined(cap_binary_rewriter) extern struct r_debug _r_debug; -DLLEXPORT struct r_debug _r_debug __attribute__ ((weak)); /* Verify that the r_debug variable is visible */ -void r_debugCheck() { assert(_r_debug.r_map); } +void r_debugCheck(void) { assert(_r_debug.r_map); } #define NUM_LIBRARIES 512 //Important, max number of rewritten libraries @@ -429,9 +429,9 @@ struct trap_mapping_header *getStaticTrapMap(unsigned long addr); static unsigned all_headers_current[NUM_LIBRARIES_BITMASK_SIZE]; static unsigned all_headers_last[NUM_LIBRARIES_BITMASK_SIZE]; -static int parse_libs(); +static int parse_libs(void); static int parse_link_map(struct link_map *l); -static void clear_unloaded_libs(); +static void clear_unloaded_libs(void); static void set_bit(unsigned *bit_mask, int bit, char value); //static char get_bit(unsigned *bit_mask, int bit); @@ -477,7 +477,7 @@ static struct trap_mapping_header *getStaticTrapMap(unsigned long addr) } #if !defined (arch_aarch64) -static int parse_libs() +static int parse_libs(void) { struct link_map *l_current; @@ -552,7 +552,7 @@ static int parse_link_map(struct link_map *l) return PARSED; } -static void clear_unloaded_libs() +static void clear_unloaded_libs(void) { unsigned i; for (i = 0; i -#include -#include -#include - -#if defined (__GNUC__) -#include -#define FAST_CALL __attribute__((fastcall)) -#elif defined (os_windows) -#define FAST_CALL __fastcall -#endif - -/* Code to assist in remapping memory operations that were affected - * by our instrumentation */ - -extern void DYNINST_stopThread(void *, void *, void *, void *); - -#if _MSC_VER -struct MemoryMapper RTmemoryMapper = {0, 0, 0, 0 }; -#else -struct MemoryMapper RTmemoryMapper = {0, 0, 0, 0, {{0}} }; -#endif -extern FILE *stOut; - -//#define DEBUG_MEM_EM - -unsigned long RTtranslateMemory(unsigned long input, unsigned long origAddr, unsigned long currAddr) { - /* Standard nonblocking synchronization construct */ - int index; - int min; - int max; - volatile int guard2; - (void)origAddr; /* unused parameter */ - (void)currAddr; /* unused parameter */ - - do { - guard2 = RTmemoryMapper.guard2; - min = 0; - max = (RTmemoryMapper.size - 1); - do { - index = min + ((max - min) / 2); - if (input >= RTmemoryMapper.elements[index].lo) { - /* Either correct or too low */ - if (input < RTmemoryMapper.elements[index].hi) { - break; - } - else { - min = index + 1; - } - } - else { - /* Too high */ - max = index - 1; - } - } while (min <= max); - } while (guard2 != RTmemoryMapper.guard1); - - if (min <= max) { - if (RTmemoryMapper.elements[index].shift == -1) { - return 0; - } - else { - return input + RTmemoryMapper.elements[index].shift; - } - } - else { - return input; - } - return 0; -} - -unsigned long RTtranslateMemoryShift(unsigned long input, unsigned long origAddr, unsigned long currAddr) { - /* Standard nonblocking synchronization construct */ - int index; - int min; - int max; - volatile int guard2; - (void)origAddr; /* unused parameter */ - (void)currAddr; /* unused parameter */ - - do { - guard2 = RTmemoryMapper.guard2; - min = 0; - max = (RTmemoryMapper.size - 1); - do { - index = min + ((max - min) / 2); - if (input >= RTmemoryMapper.elements[index].lo) { - /* Either correct or too low */ - if (input < RTmemoryMapper.elements[index].hi) { - break; - } - else { - min = index + 1; - } - } - else { - /* Too high */ - max = index - 1; - } - } while (min <= max); - } while (guard2 != RTmemoryMapper.guard1); - - if (min <= max) { - if (RTmemoryMapper.elements[index].shift == -1) { - fflush(stOut); - return -1 * input; - } - else { - return RTmemoryMapper.elements[index].shift; - } - } - else { - return 0; - } - return 0; -} - -int RTuntranslatedEntryCounter; -extern void DYNINST_stopThread (void * pointAddr, void *callBackID, void *flags, void *calculation); - -void RThandleShadow(void *direction, void *pointAddr, void *callbackID, void *flags, void *calculation) { - (void)calculation; /* unused parameter */ - if ((int)((long) direction) == 1) { - if (RTuntranslatedEntryCounter == 0) { - // Entering a system call... - DYNINST_stopThread(pointAddr, callbackID, flags, (void *)1); - } - RTuntranslatedEntryCounter++; - } - else { - if (RTuntranslatedEntryCounter > 0) { - RTuntranslatedEntryCounter--; - } - if (RTuntranslatedEntryCounter == 0) { - DYNINST_stopThread(pointAddr, callbackID, flags, (void *)0); - } - } -} diff --git a/dyninstAPI_RT/src/RTposix.c b/dyninstAPI_RT/src/RTposix.c index 8277c3d09a..4e28afea75 100644 --- a/dyninstAPI_RT/src/RTposix.c +++ b/dyninstAPI_RT/src/RTposix.c @@ -33,6 +33,8 @@ * RTposix.c: runtime instrumentation functions for generic posix. ************************************************************************/ +#define _GNU_SOURCE + #include #include #include @@ -55,7 +57,7 @@ #define SOCKLEN_T socklen_t #if !(defined(arch_power) && defined(os_linux)) -void RTmutatedBinary_init() +void RTmutatedBinary_init(void) { return; } @@ -77,7 +79,7 @@ void libdyninstAPI_RT_init(void) __attribute__ ((constructor)); struct passwd *passwd_info = NULL; #endif -void libdyninstAPI_RT_init() +void libdyninstAPI_RT_init(void) { static int initCalledOnce = 0; @@ -189,7 +191,7 @@ int DYNINSTasyncConnect(int pid) #endif } -int DYNINSTasyncDisconnect() +int DYNINSTasyncDisconnect(void) { if (DYNINSTstaticMode) return 0; @@ -264,7 +266,7 @@ int unmap_region(void *addr, int len) { #if defined(cap_mutatee_traps) extern void dyninstTrapHandler(int sig, siginfo_t *info, void *context); -int DYNINSTinitializeTrapHandler() +int DYNINSTinitializeTrapHandler(void) { int result; struct sigaction new_handler; diff --git a/dyninstAPI_RT/src/RTsignal.c b/dyninstAPI_RT/src/RTsignal.c index 1aab0ee3d0..69c0339965 100644 --- a/dyninstAPI_RT/src/RTsignal.c +++ b/dyninstAPI_RT/src/RTsignal.c @@ -30,7 +30,9 @@ /************************************************************************ * RTsignal.c: C-language signal handling code -************************************************************************/ + ************************************************************************/ + +#define _GNU_SOURCE #include #include diff --git a/dyninstAPI_RT/src/RTstatic_ctors_dtors-ppc32.c b/dyninstAPI_RT/src/RTstatic_ctors_dtors-ppc32.c deleted file mode 100644 index 3c3265b832..0000000000 --- a/dyninstAPI_RT/src/RTstatic_ctors_dtors-ppc32.c +++ /dev/null @@ -1,94 +0,0 @@ -/* - * See the dyninst/COPYRIGHT file for copyright information. - * - * We provide the Paradyn Tools (below described as "Paradyn") - * on an AS IS basis, and do not warrant its validity or performance. - * We reserve the right to update, modify, or discontinue this - * software at any time. We shall have no obligation to supply such - * updates or modifications or any other form of support to you. - * - * By your use of Paradyn, you understand and agree that we (or any - * other person or entity with proprietary rights in Paradyn) are - * under no obligation to provide either maintenance services, - * update services, notices of latent defects, or correction of - * defects for Paradyn. - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#if defined(DYNINST_RT_STATIC_LIB) -void (*DYNINSTctors_addr)(void); -void (*DYNINSTdtors_addr)(void); - -#if defined(MUTATEE64) -static const unsigned long long CTOR_LIST_TERM = 0x0000000000000000ULL; -static const unsigned long long CTOR_LIST_START = 0xffffffffffffffffULL; -static const unsigned long long DTOR_LIST_TERM = 0x0000000000000000ULL; -static const unsigned long long DTOR_LIST_START = 0xffffffffffffffffULL; -#else -static const unsigned CTOR_LIST_TERM = 0x00000000; -static const unsigned CTOR_LIST_START = 0xffffffff; -static const unsigned DTOR_LIST_TERM = 0x00000000; -static const unsigned DTOR_LIST_START = 0xffffffff; -#endif - -extern void DYNINSTBaseInit(); - -/* - * When rewritting a static binary, .ctors and .dtors sections of - * instrumentation code needs to be combined with the existing .ctors - * and .dtors sections of the static binary. - * - * The following functions process the .ctors and .dtors sections - * that have been rewritten. The rewriter will relocate the - * address of DYNINSTctors_addr and DYNINSTdtors_addr to point to - * new .ctors and .dtors sections. - */ - -void DYNINSTglobal_ctors_handler() { - void (**ctors_array)(void) = &DYNINSTctors_addr; - - // Find end of function pointer list - void (**tmp_ptr)(void) = ctors_array; - unsigned size = 0; - while( *tmp_ptr != ( (void(*)(void))CTOR_LIST_TERM ) ) { - size++; - tmp_ptr++; - } - - // Constructors are called in the reverse order that they are listed - tmp_ptr = &ctors_array[size-1]; // skip list end - while( *tmp_ptr != ( (void(*)(void))CTOR_LIST_START ) ) { - (*tmp_ptr)(); - tmp_ptr--; - } - - // This ensures that instrumentation cannot execute until all global - // constructors have run - DYNINSTBaseInit(); -} - -void DYNINSTglobal_dtors_handler() { - void (**dtors_array)(void) = &DYNINSTdtors_addr; - - // Destructors are called in the forward order that they are listed - void (**tmp_ptr)(void) = &dtors_array[1]; // skip list start - while( *tmp_ptr != ( (void(*)(void))DTOR_LIST_TERM ) ) { - (*tmp_ptr)(); - tmp_ptr++; - } -} - -#endif diff --git a/dyninstAPI_RT/src/RTstatic_ctors_dtors-x86.c b/dyninstAPI_RT/src/RTstatic_ctors_dtors-x86.c index d603c01a41..3f7f03b04c 100644 --- a/dyninstAPI_RT/src/RTstatic_ctors_dtors-x86.c +++ b/dyninstAPI_RT/src/RTstatic_ctors_dtors-x86.c @@ -38,7 +38,7 @@ extern void (*DYNINSTdtors_begin)(void); extern void (*DYNINSTctors_end)(void); extern void (*DYNINSTdtors_end)(void); -extern void DYNINSTBaseInit(); +extern void DYNINSTBaseInit(void); typedef struct { long *offset; @@ -62,7 +62,7 @@ typedef struct { * new .ctors and .dtors sections. */ -void DYNINSTglobal_ctors_handler() { +void DYNINSTglobal_ctors_handler(void) { void (**ctor)(void) = &DYNINSTctors_begin; while( ctor != ( &DYNINSTctors_end )) { @@ -76,7 +76,7 @@ void DYNINSTglobal_ctors_handler() { DYNINSTBaseInit(); } -void DYNINSTglobal_dtors_handler() { +void DYNINSTglobal_dtors_handler(void) { void (**dtor)(void) = &DYNINSTdtors_begin; // Destructors are called in the forward order that they are listed @@ -87,7 +87,7 @@ void DYNINSTglobal_dtors_handler() { } } -void DYNINSTglobal_irel_handler() { +void DYNINSTglobal_irel_handler(void) { if (sizeof(long) == 8) { rela_t *rel = 0; for (rel = (rela_t *)(&DYNINSTirel_start); rel != (rela_t *)(&DYNINSTirel_end); ++rel) { diff --git a/dyninstAPI_RT/src/RTthread-powerpc-asm.S b/dyninstAPI_RT/src/RTthread-powerpc-asm.S index fd59bdcd27..818c61a3d0 100644 --- a/dyninstAPI_RT/src/RTthread-powerpc-asm.S +++ b/dyninstAPI_RT/src/RTthread-powerpc-asm.S @@ -1,8 +1,6 @@ .file "RTthread-powerpc-asm.S" .machine "push" -#if defined(arch_ppc_little_endian) .abiversion 2 -#endif #ifndef __clang__ # if defined(arch_64bit) @@ -23,7 +21,6 @@ # /* Return 1 if such an atomic update occurred; */ # /* return 0 otherwise. */ # /* ------------------------------------------- */ -#if defined(arch_ppc_little_endian) .section ".toc", "aw" .section ".text" .align 2 @@ -31,23 +28,6 @@ .globl atomic_set .type atomic_set, @function atomic_set: -#elif defined(arch_64bit) - .globl atomic_set - .section ".opd", "aw" - .align 3 -atomic_set: - .quad .atomic_set, .TOC.@tocbase, 0 - .size atomic_set, 24 - - .previous - .globl .atomic_set - .type .atomic_set, @function -.atomic_set: -#else - .globl atomic_set - .type atomic_set, @function -atomic_set: -#endif addi 4,0,1 # r4 = 1 # Attempt atomic memory swap lwarx 5,0,3 # r5 = *int_ptr (load reserve indexed) @@ -64,13 +44,7 @@ atomic_set_return_0: addi 3,0,0 # function return value = r3 = 0 blr # branch via link register (function return) -#if defined(arch_ppc_little_endian) .size atomic_set, . - atomic_set -#elif defined(arch_64bit) - .size .atomic_set, . - .atomic_set -#else - .size atomic_set, . - atomic_set -#endif .machine "pop" diff --git a/dyninstAPI_RT/src/RTthread.h b/dyninstAPI_RT/src/RTthread.h index e78e0d3cb8..5be5acb6d8 100644 --- a/dyninstAPI_RT/src/RTthread.h +++ b/dyninstAPI_RT/src/RTthread.h @@ -34,9 +34,9 @@ #include "dyninstAPI_RT/h/dyninstAPI_RT.h" #include "dyninstAPI_RT/h/dyninstRTExport.h" -DLLEXPORT dyntid_t dyn_pthread_self(); /*Thread library identifier*/ -int dyn_lwp_self(); /*LWP used by the kernel identifier*/ -int dyn_pid_self(); /*PID identifier representing the containing process*/ +DLLEXPORT dyntid_t dyn_pthread_self(void); /*Thread library identifier*/ +int dyn_lwp_self(void); /*LWP used by the kernel identifier*/ +int dyn_pid_self(void); /*PID identifier representing the containing process*/ extern int DYNINST_multithread_capable; diff --git a/dyninstAPI_RT/src/RTwinnt.c b/dyninstAPI_RT/src/RTwinnt.c index 2bb0da55e3..1790f0a57d 100644 --- a/dyninstAPI_RT/src/RTwinnt.c +++ b/dyninstAPI_RT/src/RTwinnt.c @@ -232,7 +232,7 @@ void printSysError(unsigned errNo) { MAKELANGID(LANG_NEUTRAL, SUBLANG_DEFAULT), buf, 1000, NULL); - fprintf(stderr, "*** System error [%d]: %s\n", errNo, buf); + fprintf(stderr, "*** System error [%u]: %s\n", errNo, buf); fflush(stderr); } @@ -243,7 +243,7 @@ int DYNINSTwriteEvent(void *ev, size_t sz) if (send((SOCKET)async_socket, ev, sz, 0) != sz) { printSysError(WSAGetLastError()); - printf("DYNINSTwriteTrace: send error %d, %d %d\n", + printf("DYNINSTwriteTrace: send error %d, %zu %d\n", WSAGetLastError(), sz, async_socket); if (async_socket == -1) @@ -475,14 +475,14 @@ DWORD __stdcall DYNINST_FakeTickCount() fakeTickCount = fakeTickCount + 2; // fakeTickCount = fakeTickCount + (tmp - fakeTickCount)/1000 + 1; } - fprintf(stOut,"0x%lx = DYNINST_FakeTickCount()\n",fakeTickCount); + fprintf(stOut,"0x%x = DYNINST_FakeTickCount()\n",fakeTickCount); return (DWORD) fakeTickCount; } BOOL __stdcall DYNINST_FakeBlockInput(BOOL blockit) { BOOL ret = RT_TRUE; - fprintf(stOut,"0x%lx = DYNINST_FakeBlockInput(%d)\n",ret,blockit); + fprintf(stOut,"0x%x = DYNINST_FakeBlockInput(%d)\n",ret,blockit); return ret; } diff --git a/elf/CMakeLists.txt b/elf/CMakeLists.txt index 4f80f46170..98a633134d 100644 --- a/elf/CMakeLists.txt +++ b/elf/CMakeLists.txt @@ -1,27 +1,25 @@ -# CMake configuration for dynElf (elf) directory +include_guard(GLOBAL) -if (NOT UNIX) - return() -endif() - -include_directories ( - src - h - ) +include(DyninstLibrary) -set (SRC_LIST - src/Elf_X.C - ) - -dyninst_library(dynElf ${LibElf_LIBRARIES}) -if(TARGET TBB) - add_dependencies(dynElf TBB) +if(NOT DYNINST_OS_UNIX) + if(NOT TARGET dynElf) + add_library(dynElf INTERFACE) + endif() + return() endif() -add_dependencies(dynElf ElfUtils) -target_link_private_libraries(dynElf ${ElfUtils_LIBRARIES}) -if (ENABLE_DEBUGINFOD AND LibDebuginfod_FOUND) - add_definitions(-DDEBUGINFOD_LIB) -endif() +set(_public_headers h/Elf_X.h) +set(_sources src/Elf_X.C) -add_definitions(-DDYNELF_LIB) +# cmake-format: off +dyninst_library( + dynElf + PUBLIC_HEADER_FILES ${_public_headers} + SOURCE_FILES ${_sources} + DEFINES DYNELF_LIB + DYNINST_DEPS common + PRIVATE_DEPS + PUBLIC_DEPS Dyninst::ElfUtils +) +# cmake-format: on diff --git a/elf/h/Elf_X.h b/elf/h/Elf_X.h index 601c42f4b5..06c94026fe 100644 --- a/elf/h/Elf_X.h +++ b/elf/h/Elf_X.h @@ -32,11 +32,13 @@ #define __ELF_X_H__ #include "libelf.h" +#include +#include #include #include #include #include "util.h" -#include "dyn_regs.h" +#include "Architecture.h" #ifndef EM_CUDA #define EM_CUDA 190 /* NVIDIA CUDA */ @@ -46,6 +48,10 @@ #define EM_INTEL_GEN9 182 /* INTEL GEN9 */ #endif +#ifndef EM_INTELGT +#define EM_INTELGT 205 /* INTEL Graphics Technology */ +#endif + namespace Dyninst { // Forward declarations @@ -129,24 +135,24 @@ class DYNELF_EXPORT Elf_X { Dyninst::Architecture getArch() const; protected: - Elf *elf; - Elf32_Ehdr *ehdr32; - Elf64_Ehdr *ehdr64; - Elf32_Phdr *phdr32; - Elf64_Phdr *phdr64; - int filedes; - bool is64; - bool isArchive; - bool isBigEndian; + Elf *elf{}; + Elf32_Ehdr *ehdr32{}; + Elf64_Ehdr *ehdr64{}; + Elf32_Phdr *phdr32{}; + Elf64_Phdr *phdr64{}; + int filedes{}; + bool is64{}; + bool isArchive{}; + bool isBigEndian{}; std::vector shdrs; std::vector phdrs; - unsigned int ref_count; + unsigned int ref_count{}; std::string filename; - char *cached_debug_buffer; - unsigned long cached_debug_size; + char *cached_debug_buffer{}; + unsigned long cached_debug_size{}; std::string cached_debug_name; - bool cached_debug; + bool cached_debug{}; Elf_X(); Elf_X(int input, Elf_Cmd cmd, Elf_X *ref = NULL); diff --git a/elf/src/Elf_X.C b/elf/src/Elf_X.C index 404926a733..1fd222c5e1 100644 --- a/elf/src/Elf_X.C +++ b/elf/src/Elf_X.C @@ -28,6 +28,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include #include #include @@ -35,12 +36,13 @@ #include #include -#include -#include -#include -#include +#include +#include +#include +#include #include "common/src/headers.h" +#include "unaligned_memory_access.h" #include "Elf_X.h" #include #include @@ -52,8 +54,8 @@ #endif using namespace std; -using boost::crc_32_type; -using namespace boost::assign; +using dyncompat::crc_32_type; +using namespace dyncompat::assign; using namespace Dyninst; @@ -1730,7 +1732,7 @@ bool Elf_X::findDebugFile(std::string origfilename, string &output_name, char* & if (!result) continue; - boost::crc_32_type crcComputer; + dyncompat::crc_32_type crcComputer; crcComputer.process_bytes(output_buffer, output_buffer_size); if(crcComputer.checksum() != debugFileCrc) { munmap(output_buffer, output_buffer_size); @@ -1763,15 +1765,15 @@ bool Elf_X::findDebugFile(std::string origfilename, string &output_name, char* & if (client == NULL) return false; - char *filename; + char *path; int fd = debuginfod_find_debuginfo(client, (const unsigned char *)buildid.c_str(), - 0, &filename); + 0, &path); debuginfod_end(client); if (fd >= 0) { - string fname = string(filename); - free(filename); + string fname = string(path); + free(path); close(fd); bool result = loadDebugFileFromDisk(fname, @@ -1819,6 +1821,8 @@ Dyninst::Architecture Elf_X::getArch() const return Dyninst::Arch_cuda; case EM_INTEL_GEN9: return Dyninst::Arch_intelGen9; + case EM_INTELGT: + return Dyninst::Arch_intelGen9; case EM_ARM: return Dyninst::Arch_aarch32; case EM_AARCH64: @@ -1829,17 +1833,20 @@ Dyninst::Architecture Elf_X::getArch() const unsigned int ef_amdgpu_mach = 0x000000ff & e_flags(); //cerr << " dealing with amd gpu , mach = " << std::hex << ef_amdgpu_mach << endl; switch(ef_amdgpu_mach){ - case 0x33: case 0x34: case 0x35: case 0x36: case 0x37: case 0x38: - return Dyninst::Arch_amdgpu_rdna; - assert( 0 && "rdna not supported yet " ); - case 0x28: case 0x29: case 0x2a: case 0x2b: case 0x2c: case 0x2d: case 0x2e: case 0x2f: case 0x30: case 0x31: - return Dyninst::Arch_amdgpu_vega; + case 0x40: + return Dyninst::Arch_amdgpu_gfx940; + case 0x3f: + return Dyninst::Arch_amdgpu_gfx90a; + case 0x30: + case 0x28: case 0x29: case 0x2a: case 0x2b: case 0x2c: case 0x2d: case 0x2e: case 0x2f: case 0x31: + return Dyninst::Arch_amdgpu_gfx908; case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17: case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f: assert(0 && "reserved for r600 architecture"); case 0x27: case 0x32 : case 0x39: assert(0 && "reserved"); default: + //cerr << "unsupported amdgpu architecture , value = " << ef_amdgpu_mach << endl; assert(0 && "probabily won't be supported"); } @@ -1867,7 +1874,7 @@ Elf_X_Nhdr::Elf_X_Nhdr(Elf_Data *data_, size_t offset) size_t size = data->d_size - offset; if (sizeof(*nhdr) <= size) { size -= sizeof(*nhdr); - nhdr = (Elf32_Nhdr *)((char *)data->d_buf + offset); + nhdr = alignas_cast((char *)data->d_buf + offset); if (n_namesz() > size || n_descsz() > size - n_namesz()) nhdr = NULL; } diff --git a/external/inttypes-win.h b/external/inttypes-win.h deleted file mode 100644 index cd530cf719..0000000000 --- a/external/inttypes-win.h +++ /dev/null @@ -1,311 +0,0 @@ -// ISO C9x compliant inttypes.h for Microsoft Visual Studio -// Based on ISO/IEC 9899:TC2 Committee draft (May 6, 2005) WG14/N1124 -// -// Copyright (c) 2006 Alexander Chemeris -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// 1. Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// -// 2. Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the distribution. -// -// 3. The name of the author may be used to endorse or promote products -// derived from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED -// WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO -// EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; -// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR -// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF -// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -/////////////////////////////////////////////////////////////////////////////// - -#ifndef _MSC_VER // [ -#error "Use this header only with Microsoft Visual C++ compilers!" -#endif // _MSC_VER ] - -// Modern Visual Studio has sane inttypes.h -#if _MSC_VER >= 1900 -#include -#define _MSC_INTTYPES_H_ -#endif - -#ifndef _MSC_INTTYPES_H_ // [ -#define _MSC_INTTYPES_H_ - -#if _MSC_VER > 1000 -#pragma once -#endif - -#include "stdint-win.h" - -// 7.8 Format conversion of integer types - -typedef struct { - intmax_t quot; - intmax_t rem; -} imaxdiv_t; - -// 7.8.1 Macros for format specifiers - -#if !defined(__cplusplus) || defined(__STDC_FORMAT_MACROS) // [ See footnote 185 at page 198 - -// The fprintf macros for signed integers are: -#define PRId8 "d" -#define PRIi8 "i" -#define PRIdLEAST8 "d" -#define PRIiLEAST8 "i" -#define PRIdFAST8 "d" -#define PRIiFAST8 "i" - -#define PRId16 "hd" -#define PRIi16 "hi" -#define PRIdLEAST16 "hd" -#define PRIiLEAST16 "hi" -#define PRIdFAST16 "hd" -#define PRIiFAST16 "hi" - -#define PRId32 "I32d" -#define PRIi32 "I32i" -#define PRIdLEAST32 "I32d" -#define PRIiLEAST32 "I32i" -#define PRIdFAST32 "I32d" -#define PRIiFAST32 "I32i" - -#define PRId64 "I64d" -#define PRIi64 "I64i" -#define PRIdLEAST64 "I64d" -#define PRIiLEAST64 "I64i" -#define PRIdFAST64 "I64d" -#define PRIiFAST64 "I64i" - -#define PRIdMAX "I64d" -#define PRIiMAX "I64i" - -#define PRIdPTR "Id" -#define PRIiPTR "Ii" - -// The fprintf macros for unsigned integers are: -#define PRIo8 "o" -#define PRIu8 "u" -#define PRIx8 "x" -#define PRIX8 "X" -#define PRIoLEAST8 "o" -#define PRIuLEAST8 "u" -#define PRIxLEAST8 "x" -#define PRIXLEAST8 "X" -#define PRIoFAST8 "o" -#define PRIuFAST8 "u" -#define PRIxFAST8 "x" -#define PRIXFAST8 "X" - -#define PRIo16 "ho" -#define PRIu16 "hu" -#define PRIx16 "hx" -#define PRIX16 "hX" -#define PRIoLEAST16 "ho" -#define PRIuLEAST16 "hu" -#define PRIxLEAST16 "hx" -#define PRIXLEAST16 "hX" -#define PRIoFAST16 "ho" -#define PRIuFAST16 "hu" -#define PRIxFAST16 "hx" -#define PRIXFAST16 "hX" - -#define PRIo32 "I32o" -#define PRIu32 "I32u" -#define PRIx32 "I32x" -#define PRIX32 "I32X" -#define PRIoLEAST32 "I32o" -#define PRIuLEAST32 "I32u" -#define PRIxLEAST32 "I32x" -#define PRIXLEAST32 "I32X" -#define PRIoFAST32 "I32o" -#define PRIuFAST32 "I32u" -#define PRIxFAST32 "I32x" -#define PRIXFAST32 "I32X" - -#define PRIo64 "I64o" -#define PRIu64 "I64u" -#define PRIx64 "I64x" -#define PRIX64 "I64X" -#define PRIoLEAST64 "I64o" -#define PRIuLEAST64 "I64u" -#define PRIxLEAST64 "I64x" -#define PRIXLEAST64 "I64X" -#define PRIoFAST64 "I64o" -#define PRIuFAST64 "I64u" -#define PRIxFAST64 "I64x" -#define PRIXFAST64 "I64X" - -#define PRIoMAX "I64o" -#define PRIuMAX "I64u" -#define PRIxMAX "I64x" -#define PRIXMAX "I64X" - -#define PRIoPTR "Io" -#define PRIuPTR "Iu" -#define PRIxPTR "Ix" -#define PRIXPTR "IX" - -// The fscanf macros for signed integers are: -#define SCNd8 "d" -#define SCNi8 "i" -#define SCNdLEAST8 "d" -#define SCNiLEAST8 "i" -#define SCNdFAST8 "d" -#define SCNiFAST8 "i" - -#define SCNd16 "hd" -#define SCNi16 "hi" -#define SCNdLEAST16 "hd" -#define SCNiLEAST16 "hi" -#define SCNdFAST16 "hd" -#define SCNiFAST16 "hi" - -#define SCNd32 "ld" -#define SCNi32 "li" -#define SCNdLEAST32 "ld" -#define SCNiLEAST32 "li" -#define SCNdFAST32 "ld" -#define SCNiFAST32 "li" - -#define SCNd64 "I64d" -#define SCNi64 "I64i" -#define SCNdLEAST64 "I64d" -#define SCNiLEAST64 "I64i" -#define SCNdFAST64 "I64d" -#define SCNiFAST64 "I64i" - -#define SCNdMAX "I64d" -#define SCNiMAX "I64i" - -#ifdef _WIN64 // [ -# define SCNdPTR "I64d" -# define SCNiPTR "I64i" -#else // _WIN64 ][ -# define SCNdPTR "ld" -# define SCNiPTR "li" -#endif // _WIN64 ] - -// The fscanf macros for unsigned integers are: -#define SCNo8 "o" -#define SCNu8 "u" -#define SCNx8 "x" -#define SCNX8 "X" -#define SCNoLEAST8 "o" -#define SCNuLEAST8 "u" -#define SCNxLEAST8 "x" -#define SCNXLEAST8 "X" -#define SCNoFAST8 "o" -#define SCNuFAST8 "u" -#define SCNxFAST8 "x" -#define SCNXFAST8 "X" - -#define SCNo16 "ho" -#define SCNu16 "hu" -#define SCNx16 "hx" -#define SCNX16 "hX" -#define SCNoLEAST16 "ho" -#define SCNuLEAST16 "hu" -#define SCNxLEAST16 "hx" -#define SCNXLEAST16 "hX" -#define SCNoFAST16 "ho" -#define SCNuFAST16 "hu" -#define SCNxFAST16 "hx" -#define SCNXFAST16 "hX" - -#define SCNo32 "lo" -#define SCNu32 "lu" -#define SCNx32 "lx" -#define SCNX32 "lX" -#define SCNoLEAST32 "lo" -#define SCNuLEAST32 "lu" -#define SCNxLEAST32 "lx" -#define SCNXLEAST32 "lX" -#define SCNoFAST32 "lo" -#define SCNuFAST32 "lu" -#define SCNxFAST32 "lx" -#define SCNXFAST32 "lX" - -#define SCNo64 "I64o" -#define SCNu64 "I64u" -#define SCNx64 "I64x" -#define SCNX64 "I64X" -#define SCNoLEAST64 "I64o" -#define SCNuLEAST64 "I64u" -#define SCNxLEAST64 "I64x" -#define SCNXLEAST64 "I64X" -#define SCNoFAST64 "I64o" -#define SCNuFAST64 "I64u" -#define SCNxFAST64 "I64x" -#define SCNXFAST64 "I64X" - -#define SCNoMAX "I64o" -#define SCNuMAX "I64u" -#define SCNxMAX "I64x" -#define SCNXMAX "I64X" - -#ifdef _WIN64 // [ -# define SCNoPTR "I64o" -# define SCNuPTR "I64u" -# define SCNxPTR "I64x" -# define SCNXPTR "I64X" -#else // _WIN64 ][ -# define SCNoPTR "lo" -# define SCNuPTR "lu" -# define SCNxPTR "lx" -# define SCNXPTR "lX" -#endif // _WIN64 ] - -#endif // __STDC_FORMAT_MACROS ] - -// 7.8.2 Functions for greatest-width integer types - -// 7.8.2.1 The imaxabs function -#define imaxabs _abs64 - -// 7.8.2.2 The imaxdiv function - -// This is modified version of div() function from Microsoft's div.c found -// in %MSVC.NET%\crt\src\div.c -#ifdef STATIC_IMAXDIV // [ -static -#else // STATIC_IMAXDIV ][ -_inline -#endif // STATIC_IMAXDIV ] -imaxdiv_t __cdecl imaxdiv(intmax_t numer, intmax_t denom) -{ - imaxdiv_t result; - - result.quot = numer / denom; - result.rem = numer % denom; - - if (numer < 0 && result.rem > 0) { - // did division wrong; must fix up - ++result.quot; - result.rem -= denom; - } - - return result; -} - -// 7.8.2.3 The strtoimax and strtoumax functions -#define strtoimax _strtoi64 -#define strtoumax _strtoui64 - -// 7.8.2.4 The wcstoimax and wcstoumax functions -#define wcstoimax _wcstoi64 -#define wcstoumax _wcstoui64 - - -#endif // _MSC_INTTYPES_H_ ] diff --git a/external/rose/amdgpuInstructionEnum.h b/external/rose/amdgpuInstructionEnum.h index b46545fa08..e5d7801aa5 100644 --- a/external/rose/amdgpuInstructionEnum.h +++ b/external/rose/amdgpuInstructionEnum.h @@ -5,15 +5,7 @@ enum AMDGPURegisterClass{ amdgpu_regclass_pc, amdgpu_regclass_ttmp_sgpr, amdgpu_regclass_sgpr, - amdgpu_regclass_sgpr_vec2, - amdgpu_regclass_sgpr_vec4, - amdgpu_regclass_sgpr_vec8, - amdgpu_regclass_sgpr_vec16, amdgpu_regclass_vgpr, - amdgpu_regclass_vgpr_vec2, - amdgpu_regclass_vgpr_vec4, - amdgpu_regclass_vgpr_vec8, - amdgpu_regclass_vgpr_vec16 }; enum AMDGPUHardwareRegister{ amdgpu_address_mode_32, @@ -151,103 +143,6 @@ enum AMDGPUScalarGeneralPurposeRegister{ amdgpu_sgpr102, amdgpu_sgpr103 }; -enum AMDGPUScalarGeneralPurposeRegisterVector2{ - amdgpu_sgpr_vec2_0, - amdgpu_sgpr_vec2_2, - amdgpu_sgpr_vec2_4, - amdgpu_sgpr_vec2_6, - amdgpu_sgpr_vec2_8, - amdgpu_sgpr_vec2_10, - amdgpu_sgpr_vec2_12, - amdgpu_sgpr_vec2_14, - amdgpu_sgpr_vec2_16, - amdgpu_sgpr_vec2_18, - amdgpu_sgpr_vec2_20, - amdgpu_sgpr_vec2_22, - amdgpu_sgpr_vec2_24, - amdgpu_sgpr_vec2_26, - amdgpu_sgpr_vec2_28, - amdgpu_sgpr_vec2_30, - amdgpu_sgpr_vec2_32, - amdgpu_sgpr_vec2_34, - amdgpu_sgpr_vec2_36, - amdgpu_sgpr_vec2_38, - amdgpu_sgpr_vec2_40, - amdgpu_sgpr_vec2_42, - amdgpu_sgpr_vec2_44, - amdgpu_sgpr_vec2_46, - amdgpu_sgpr_vec2_48, - amdgpu_sgpr_vec2_50, - amdgpu_sgpr_vec2_52, - amdgpu_sgpr_vec2_54, - amdgpu_sgpr_vec2_56, - amdgpu_sgpr_vec2_58, - amdgpu_sgpr_vec2_60, - amdgpu_sgpr_vec2_62, - amdgpu_sgpr_vec2_64, - amdgpu_sgpr_vec2_66, - amdgpu_sgpr_vec2_68, - amdgpu_sgpr_vec2_70, - amdgpu_sgpr_vec2_72, - amdgpu_sgpr_vec2_74, - amdgpu_sgpr_vec2_76, - amdgpu_sgpr_vec2_78, - amdgpu_sgpr_vec2_80, - amdgpu_sgpr_vec2_82, - amdgpu_sgpr_vec2_84, - amdgpu_sgpr_vec2_86, - amdgpu_sgpr_vec2_88, - amdgpu_sgpr_vec2_90, - amdgpu_sgpr_vec2_92, - amdgpu_sgpr_vec2_94, - amdgpu_sgpr_vec2_96, - amdgpu_sgpr_vec2_98, - amdgpu_sgpr_vec2_100, - amdgpu_sgpr_vec2_102 -}; -enum AMDGPUScalarGeneralPurposeRegisterVector4{ - amdgpu_sgpr_vec4_0, - amdgpu_sgpr_vec4_4, - amdgpu_sgpr_vec4_8, - amdgpu_sgpr_vec4_12, - amdgpu_sgpr_vec4_16, - amdgpu_sgpr_vec4_20, - amdgpu_sgpr_vec4_24, - amdgpu_sgpr_vec4_28, - amdgpu_sgpr_vec4_32, - amdgpu_sgpr_vec4_36, - amdgpu_sgpr_vec4_40, - amdgpu_sgpr_vec4_44, - amdgpu_sgpr_vec4_48, - amdgpu_sgpr_vec4_52, - amdgpu_sgpr_vec4_56, - amdgpu_sgpr_vec4_60, - amdgpu_sgpr_vec4_64, - amdgpu_sgpr_vec4_68, - amdgpu_sgpr_vec4_72, - amdgpu_sgpr_vec4_76, - amdgpu_sgpr_vec4_80, - amdgpu_sgpr_vec4_84, - amdgpu_sgpr_vec4_88, - amdgpu_sgpr_vec4_92, - amdgpu_sgpr_vec4_96, - amdgpu_sgpr_vec4_100 -}; -enum AMDGPUScalarGeneralPurposeRegisterVector8{ - amdgpu_sgpr_vec8_0, - amdgpu_sgpr_vec8_8, - amdgpu_sgpr_vec8_16, - amdgpu_sgpr_vec8_24, - amdgpu_sgpr_vec8_32, - amdgpu_sgpr_vec8_40, - amdgpu_sgpr_vec8_48, - amdgpu_sgpr_vec8_56, - amdgpu_sgpr_vec8_64, - amdgpu_sgpr_vec8_72, - amdgpu_sgpr_vec8_80, - amdgpu_sgpr_vec8_88, - amdgpu_sgpr_vec8_96 -}; enum AMDGPUVectorGeneralPurposeRegister{ amdgpu_vgpr0, amdgpu_vgpr1, @@ -506,770 +401,7 @@ enum AMDGPUVectorGeneralPurposeRegister{ amdgpu_vgpr254, amdgpu_vgpr255 }; -enum AMDGPUVectorGeneralPurposeRegisterVector2{ - amdgpu_vgpr_vec2_0, - amdgpu_vgpr_vec2_1, - amdgpu_vgpr_vec2_2, - amdgpu_vgpr_vec2_3, - amdgpu_vgpr_vec2_4, - amdgpu_vgpr_vec2_5, - amdgpu_vgpr_vec2_6, - amdgpu_vgpr_vec2_7, - amdgpu_vgpr_vec2_8, - amdgpu_vgpr_vec2_9, - amdgpu_vgpr_vec2_10, - amdgpu_vgpr_vec2_11, - amdgpu_vgpr_vec2_12, - amdgpu_vgpr_vec2_13, - amdgpu_vgpr_vec2_14, - amdgpu_vgpr_vec2_15, - amdgpu_vgpr_vec2_16, - amdgpu_vgpr_vec2_17, - amdgpu_vgpr_vec2_18, - amdgpu_vgpr_vec2_19, - amdgpu_vgpr_vec2_20, - amdgpu_vgpr_vec2_21, - amdgpu_vgpr_vec2_22, - amdgpu_vgpr_vec2_23, - amdgpu_vgpr_vec2_24, - amdgpu_vgpr_vec2_25, - amdgpu_vgpr_vec2_26, - amdgpu_vgpr_vec2_27, - amdgpu_vgpr_vec2_28, - amdgpu_vgpr_vec2_29, - amdgpu_vgpr_vec2_30, - amdgpu_vgpr_vec2_31, - amdgpu_vgpr_vec2_32, - amdgpu_vgpr_vec2_33, - amdgpu_vgpr_vec2_34, - amdgpu_vgpr_vec2_35, - amdgpu_vgpr_vec2_36, - amdgpu_vgpr_vec2_37, - amdgpu_vgpr_vec2_38, - amdgpu_vgpr_vec2_39, - amdgpu_vgpr_vec2_40, - amdgpu_vgpr_vec2_41, - amdgpu_vgpr_vec2_42, - amdgpu_vgpr_vec2_43, - amdgpu_vgpr_vec2_44, - amdgpu_vgpr_vec2_45, - amdgpu_vgpr_vec2_46, - amdgpu_vgpr_vec2_47, - amdgpu_vgpr_vec2_48, - amdgpu_vgpr_vec2_49, - amdgpu_vgpr_vec2_50, - amdgpu_vgpr_vec2_51, - amdgpu_vgpr_vec2_52, - amdgpu_vgpr_vec2_53, - amdgpu_vgpr_vec2_54, - amdgpu_vgpr_vec2_55, - amdgpu_vgpr_vec2_56, - amdgpu_vgpr_vec2_57, - amdgpu_vgpr_vec2_58, - amdgpu_vgpr_vec2_59, - amdgpu_vgpr_vec2_60, - amdgpu_vgpr_vec2_61, - amdgpu_vgpr_vec2_62, - amdgpu_vgpr_vec2_63, - amdgpu_vgpr_vec2_64, - amdgpu_vgpr_vec2_65, - amdgpu_vgpr_vec2_66, - amdgpu_vgpr_vec2_67, - amdgpu_vgpr_vec2_68, - amdgpu_vgpr_vec2_69, - amdgpu_vgpr_vec2_70, - amdgpu_vgpr_vec2_71, - amdgpu_vgpr_vec2_72, - amdgpu_vgpr_vec2_73, - amdgpu_vgpr_vec2_74, - amdgpu_vgpr_vec2_75, - amdgpu_vgpr_vec2_76, - amdgpu_vgpr_vec2_77, - amdgpu_vgpr_vec2_78, - amdgpu_vgpr_vec2_79, - amdgpu_vgpr_vec2_80, - amdgpu_vgpr_vec2_81, - amdgpu_vgpr_vec2_82, - amdgpu_vgpr_vec2_83, - amdgpu_vgpr_vec2_84, - amdgpu_vgpr_vec2_85, - amdgpu_vgpr_vec2_86, - amdgpu_vgpr_vec2_87, - amdgpu_vgpr_vec2_88, - amdgpu_vgpr_vec2_89, - amdgpu_vgpr_vec2_90, - amdgpu_vgpr_vec2_91, - amdgpu_vgpr_vec2_92, - amdgpu_vgpr_vec2_93, - amdgpu_vgpr_vec2_94, - amdgpu_vgpr_vec2_95, - amdgpu_vgpr_vec2_96, - amdgpu_vgpr_vec2_97, - amdgpu_vgpr_vec2_98, - amdgpu_vgpr_vec2_99, - amdgpu_vgpr_vec2_100, - amdgpu_vgpr_vec2_101, - amdgpu_vgpr_vec2_102, - amdgpu_vgpr_vec2_103, - amdgpu_vgpr_vec2_104, - amdgpu_vgpr_vec2_105, - amdgpu_vgpr_vec2_106, - amdgpu_vgpr_vec2_107, - amdgpu_vgpr_vec2_108, - amdgpu_vgpr_vec2_109, - amdgpu_vgpr_vec2_110, - amdgpu_vgpr_vec2_111, - amdgpu_vgpr_vec2_112, - amdgpu_vgpr_vec2_113, - amdgpu_vgpr_vec2_114, - amdgpu_vgpr_vec2_115, - amdgpu_vgpr_vec2_116, - amdgpu_vgpr_vec2_117, - amdgpu_vgpr_vec2_118, - amdgpu_vgpr_vec2_119, - amdgpu_vgpr_vec2_120, - amdgpu_vgpr_vec2_121, - amdgpu_vgpr_vec2_122, - amdgpu_vgpr_vec2_123, - amdgpu_vgpr_vec2_124, - amdgpu_vgpr_vec2_125, - amdgpu_vgpr_vec2_126, - amdgpu_vgpr_vec2_127, - amdgpu_vgpr_vec2_128, - amdgpu_vgpr_vec2_129, - amdgpu_vgpr_vec2_130, - amdgpu_vgpr_vec2_131, - amdgpu_vgpr_vec2_132, - amdgpu_vgpr_vec2_133, - amdgpu_vgpr_vec2_134, - amdgpu_vgpr_vec2_135, - amdgpu_vgpr_vec2_136, - amdgpu_vgpr_vec2_137, - amdgpu_vgpr_vec2_138, - amdgpu_vgpr_vec2_139, - amdgpu_vgpr_vec2_140, - amdgpu_vgpr_vec2_141, - amdgpu_vgpr_vec2_142, - amdgpu_vgpr_vec2_143, - amdgpu_vgpr_vec2_144, - amdgpu_vgpr_vec2_145, - amdgpu_vgpr_vec2_146, - amdgpu_vgpr_vec2_147, - amdgpu_vgpr_vec2_148, - amdgpu_vgpr_vec2_149, - amdgpu_vgpr_vec2_150, - amdgpu_vgpr_vec2_151, - amdgpu_vgpr_vec2_152, - amdgpu_vgpr_vec2_153, - amdgpu_vgpr_vec2_154, - amdgpu_vgpr_vec2_155, - amdgpu_vgpr_vec2_156, - amdgpu_vgpr_vec2_157, - amdgpu_vgpr_vec2_158, - amdgpu_vgpr_vec2_159, - amdgpu_vgpr_vec2_160, - amdgpu_vgpr_vec2_161, - amdgpu_vgpr_vec2_162, - amdgpu_vgpr_vec2_163, - amdgpu_vgpr_vec2_164, - amdgpu_vgpr_vec2_165, - amdgpu_vgpr_vec2_166, - amdgpu_vgpr_vec2_167, - amdgpu_vgpr_vec2_168, - amdgpu_vgpr_vec2_169, - amdgpu_vgpr_vec2_170, - amdgpu_vgpr_vec2_171, - amdgpu_vgpr_vec2_172, - amdgpu_vgpr_vec2_173, - amdgpu_vgpr_vec2_174, - amdgpu_vgpr_vec2_175, - amdgpu_vgpr_vec2_176, - amdgpu_vgpr_vec2_177, - amdgpu_vgpr_vec2_178, - amdgpu_vgpr_vec2_179, - amdgpu_vgpr_vec2_180, - amdgpu_vgpr_vec2_181, - amdgpu_vgpr_vec2_182, - amdgpu_vgpr_vec2_183, - amdgpu_vgpr_vec2_184, - amdgpu_vgpr_vec2_185, - amdgpu_vgpr_vec2_186, - amdgpu_vgpr_vec2_187, - amdgpu_vgpr_vec2_188, - amdgpu_vgpr_vec2_189, - amdgpu_vgpr_vec2_190, - amdgpu_vgpr_vec2_191, - amdgpu_vgpr_vec2_192, - amdgpu_vgpr_vec2_193, - amdgpu_vgpr_vec2_194, - amdgpu_vgpr_vec2_195, - amdgpu_vgpr_vec2_196, - amdgpu_vgpr_vec2_197, - amdgpu_vgpr_vec2_198, - amdgpu_vgpr_vec2_199, - amdgpu_vgpr_vec2_200, - amdgpu_vgpr_vec2_201, - amdgpu_vgpr_vec2_202, - amdgpu_vgpr_vec2_203, - amdgpu_vgpr_vec2_204, - amdgpu_vgpr_vec2_205, - amdgpu_vgpr_vec2_206, - amdgpu_vgpr_vec2_207, - amdgpu_vgpr_vec2_208, - amdgpu_vgpr_vec2_209, - amdgpu_vgpr_vec2_210, - amdgpu_vgpr_vec2_211, - amdgpu_vgpr_vec2_212, - amdgpu_vgpr_vec2_213, - amdgpu_vgpr_vec2_214, - amdgpu_vgpr_vec2_215, - amdgpu_vgpr_vec2_216, - amdgpu_vgpr_vec2_217, - amdgpu_vgpr_vec2_218, - amdgpu_vgpr_vec2_219, - amdgpu_vgpr_vec2_220, - amdgpu_vgpr_vec2_221, - amdgpu_vgpr_vec2_222, - amdgpu_vgpr_vec2_223, - amdgpu_vgpr_vec2_224, - amdgpu_vgpr_vec2_225, - amdgpu_vgpr_vec2_226, - amdgpu_vgpr_vec2_227, - amdgpu_vgpr_vec2_228, - amdgpu_vgpr_vec2_229, - amdgpu_vgpr_vec2_230, - amdgpu_vgpr_vec2_231, - amdgpu_vgpr_vec2_232, - amdgpu_vgpr_vec2_233, - amdgpu_vgpr_vec2_234, - amdgpu_vgpr_vec2_235, - amdgpu_vgpr_vec2_236, - amdgpu_vgpr_vec2_237, - amdgpu_vgpr_vec2_238, - amdgpu_vgpr_vec2_239, - amdgpu_vgpr_vec2_240, - amdgpu_vgpr_vec2_241, - amdgpu_vgpr_vec2_242, - amdgpu_vgpr_vec2_243, - amdgpu_vgpr_vec2_244, - amdgpu_vgpr_vec2_245, - amdgpu_vgpr_vec2_246, - amdgpu_vgpr_vec2_247, - amdgpu_vgpr_vec2_248, - amdgpu_vgpr_vec2_249, - amdgpu_vgpr_vec2_250, - amdgpu_vgpr_vec2_251, - amdgpu_vgpr_vec2_252, - amdgpu_vgpr_vec2_253, - amdgpu_vgpr_vec2_254 -}; -enum AMDGPUVectorGeneralPurposeRegisterVector4{ - amdgpu_vgpr_vec4_0, - amdgpu_vgpr_vec4_1, - amdgpu_vgpr_vec4_2, - amdgpu_vgpr_vec4_3, - amdgpu_vgpr_vec4_4, - amdgpu_vgpr_vec4_5, - amdgpu_vgpr_vec4_6, - amdgpu_vgpr_vec4_7, - amdgpu_vgpr_vec4_8, - amdgpu_vgpr_vec4_9, - amdgpu_vgpr_vec4_10, - amdgpu_vgpr_vec4_11, - amdgpu_vgpr_vec4_12, - amdgpu_vgpr_vec4_13, - amdgpu_vgpr_vec4_14, - amdgpu_vgpr_vec4_15, - amdgpu_vgpr_vec4_16, - amdgpu_vgpr_vec4_17, - amdgpu_vgpr_vec4_18, - amdgpu_vgpr_vec4_19, - amdgpu_vgpr_vec4_20, - amdgpu_vgpr_vec4_21, - amdgpu_vgpr_vec4_22, - amdgpu_vgpr_vec4_23, - amdgpu_vgpr_vec4_24, - amdgpu_vgpr_vec4_25, - amdgpu_vgpr_vec4_26, - amdgpu_vgpr_vec4_27, - amdgpu_vgpr_vec4_28, - amdgpu_vgpr_vec4_29, - amdgpu_vgpr_vec4_30, - amdgpu_vgpr_vec4_31, - amdgpu_vgpr_vec4_32, - amdgpu_vgpr_vec4_33, - amdgpu_vgpr_vec4_34, - amdgpu_vgpr_vec4_35, - amdgpu_vgpr_vec4_36, - amdgpu_vgpr_vec4_37, - amdgpu_vgpr_vec4_38, - amdgpu_vgpr_vec4_39, - amdgpu_vgpr_vec4_40, - amdgpu_vgpr_vec4_41, - amdgpu_vgpr_vec4_42, - amdgpu_vgpr_vec4_43, - amdgpu_vgpr_vec4_44, - amdgpu_vgpr_vec4_45, - amdgpu_vgpr_vec4_46, - amdgpu_vgpr_vec4_47, - amdgpu_vgpr_vec4_48, - amdgpu_vgpr_vec4_49, - amdgpu_vgpr_vec4_50, - amdgpu_vgpr_vec4_51, - amdgpu_vgpr_vec4_52, - amdgpu_vgpr_vec4_53, - amdgpu_vgpr_vec4_54, - amdgpu_vgpr_vec4_55, - amdgpu_vgpr_vec4_56, - amdgpu_vgpr_vec4_57, - amdgpu_vgpr_vec4_58, - amdgpu_vgpr_vec4_59, - amdgpu_vgpr_vec4_60, - amdgpu_vgpr_vec4_61, - amdgpu_vgpr_vec4_62, - amdgpu_vgpr_vec4_63, - amdgpu_vgpr_vec4_64, - amdgpu_vgpr_vec4_65, - amdgpu_vgpr_vec4_66, - amdgpu_vgpr_vec4_67, - amdgpu_vgpr_vec4_68, - amdgpu_vgpr_vec4_69, - amdgpu_vgpr_vec4_70, - amdgpu_vgpr_vec4_71, - amdgpu_vgpr_vec4_72, - amdgpu_vgpr_vec4_73, - amdgpu_vgpr_vec4_74, - amdgpu_vgpr_vec4_75, - amdgpu_vgpr_vec4_76, - amdgpu_vgpr_vec4_77, - amdgpu_vgpr_vec4_78, - amdgpu_vgpr_vec4_79, - amdgpu_vgpr_vec4_80, - amdgpu_vgpr_vec4_81, - amdgpu_vgpr_vec4_82, - amdgpu_vgpr_vec4_83, - amdgpu_vgpr_vec4_84, - amdgpu_vgpr_vec4_85, - amdgpu_vgpr_vec4_86, - amdgpu_vgpr_vec4_87, - amdgpu_vgpr_vec4_88, - amdgpu_vgpr_vec4_89, - amdgpu_vgpr_vec4_90, - amdgpu_vgpr_vec4_91, - amdgpu_vgpr_vec4_92, - amdgpu_vgpr_vec4_93, - amdgpu_vgpr_vec4_94, - amdgpu_vgpr_vec4_95, - amdgpu_vgpr_vec4_96, - amdgpu_vgpr_vec4_97, - amdgpu_vgpr_vec4_98, - amdgpu_vgpr_vec4_99, - amdgpu_vgpr_vec4_100, - amdgpu_vgpr_vec4_101, - amdgpu_vgpr_vec4_102, - amdgpu_vgpr_vec4_103, - amdgpu_vgpr_vec4_104, - amdgpu_vgpr_vec4_105, - amdgpu_vgpr_vec4_106, - amdgpu_vgpr_vec4_107, - amdgpu_vgpr_vec4_108, - amdgpu_vgpr_vec4_109, - amdgpu_vgpr_vec4_110, - amdgpu_vgpr_vec4_111, - amdgpu_vgpr_vec4_112, - amdgpu_vgpr_vec4_113, - amdgpu_vgpr_vec4_114, - amdgpu_vgpr_vec4_115, - amdgpu_vgpr_vec4_116, - amdgpu_vgpr_vec4_117, - amdgpu_vgpr_vec4_118, - amdgpu_vgpr_vec4_119, - amdgpu_vgpr_vec4_120, - amdgpu_vgpr_vec4_121, - amdgpu_vgpr_vec4_122, - amdgpu_vgpr_vec4_123, - amdgpu_vgpr_vec4_124, - amdgpu_vgpr_vec4_125, - amdgpu_vgpr_vec4_126, - amdgpu_vgpr_vec4_127, - amdgpu_vgpr_vec4_128, - amdgpu_vgpr_vec4_129, - amdgpu_vgpr_vec4_130, - amdgpu_vgpr_vec4_131, - amdgpu_vgpr_vec4_132, - amdgpu_vgpr_vec4_133, - amdgpu_vgpr_vec4_134, - amdgpu_vgpr_vec4_135, - amdgpu_vgpr_vec4_136, - amdgpu_vgpr_vec4_137, - amdgpu_vgpr_vec4_138, - amdgpu_vgpr_vec4_139, - amdgpu_vgpr_vec4_140, - amdgpu_vgpr_vec4_141, - amdgpu_vgpr_vec4_142, - amdgpu_vgpr_vec4_143, - amdgpu_vgpr_vec4_144, - amdgpu_vgpr_vec4_145, - amdgpu_vgpr_vec4_146, - amdgpu_vgpr_vec4_147, - amdgpu_vgpr_vec4_148, - amdgpu_vgpr_vec4_149, - amdgpu_vgpr_vec4_150, - amdgpu_vgpr_vec4_151, - amdgpu_vgpr_vec4_152, - amdgpu_vgpr_vec4_153, - amdgpu_vgpr_vec4_154, - amdgpu_vgpr_vec4_155, - amdgpu_vgpr_vec4_156, - amdgpu_vgpr_vec4_157, - amdgpu_vgpr_vec4_158, - amdgpu_vgpr_vec4_159, - amdgpu_vgpr_vec4_160, - amdgpu_vgpr_vec4_161, - amdgpu_vgpr_vec4_162, - amdgpu_vgpr_vec4_163, - amdgpu_vgpr_vec4_164, - amdgpu_vgpr_vec4_165, - amdgpu_vgpr_vec4_166, - amdgpu_vgpr_vec4_167, - amdgpu_vgpr_vec4_168, - amdgpu_vgpr_vec4_169, - amdgpu_vgpr_vec4_170, - amdgpu_vgpr_vec4_171, - amdgpu_vgpr_vec4_172, - amdgpu_vgpr_vec4_173, - amdgpu_vgpr_vec4_174, - amdgpu_vgpr_vec4_175, - amdgpu_vgpr_vec4_176, - amdgpu_vgpr_vec4_177, - amdgpu_vgpr_vec4_178, - amdgpu_vgpr_vec4_179, - amdgpu_vgpr_vec4_180, - amdgpu_vgpr_vec4_181, - amdgpu_vgpr_vec4_182, - amdgpu_vgpr_vec4_183, - amdgpu_vgpr_vec4_184, - amdgpu_vgpr_vec4_185, - amdgpu_vgpr_vec4_186, - amdgpu_vgpr_vec4_187, - amdgpu_vgpr_vec4_188, - amdgpu_vgpr_vec4_189, - amdgpu_vgpr_vec4_190, - amdgpu_vgpr_vec4_191, - amdgpu_vgpr_vec4_192, - amdgpu_vgpr_vec4_193, - amdgpu_vgpr_vec4_194, - amdgpu_vgpr_vec4_195, - amdgpu_vgpr_vec4_196, - amdgpu_vgpr_vec4_197, - amdgpu_vgpr_vec4_198, - amdgpu_vgpr_vec4_199, - amdgpu_vgpr_vec4_200, - amdgpu_vgpr_vec4_201, - amdgpu_vgpr_vec4_202, - amdgpu_vgpr_vec4_203, - amdgpu_vgpr_vec4_204, - amdgpu_vgpr_vec4_205, - amdgpu_vgpr_vec4_206, - amdgpu_vgpr_vec4_207, - amdgpu_vgpr_vec4_208, - amdgpu_vgpr_vec4_209, - amdgpu_vgpr_vec4_210, - amdgpu_vgpr_vec4_211, - amdgpu_vgpr_vec4_212, - amdgpu_vgpr_vec4_213, - amdgpu_vgpr_vec4_214, - amdgpu_vgpr_vec4_215, - amdgpu_vgpr_vec4_216, - amdgpu_vgpr_vec4_217, - amdgpu_vgpr_vec4_218, - amdgpu_vgpr_vec4_219, - amdgpu_vgpr_vec4_220, - amdgpu_vgpr_vec4_221, - amdgpu_vgpr_vec4_222, - amdgpu_vgpr_vec4_223, - amdgpu_vgpr_vec4_224, - amdgpu_vgpr_vec4_225, - amdgpu_vgpr_vec4_226, - amdgpu_vgpr_vec4_227, - amdgpu_vgpr_vec4_228, - amdgpu_vgpr_vec4_229, - amdgpu_vgpr_vec4_230, - amdgpu_vgpr_vec4_231, - amdgpu_vgpr_vec4_232, - amdgpu_vgpr_vec4_233, - amdgpu_vgpr_vec4_234, - amdgpu_vgpr_vec4_235, - amdgpu_vgpr_vec4_236, - amdgpu_vgpr_vec4_237, - amdgpu_vgpr_vec4_238, - amdgpu_vgpr_vec4_239, - amdgpu_vgpr_vec4_240, - amdgpu_vgpr_vec4_241, - amdgpu_vgpr_vec4_242, - amdgpu_vgpr_vec4_243, - amdgpu_vgpr_vec4_244, - amdgpu_vgpr_vec4_245, - amdgpu_vgpr_vec4_246, - amdgpu_vgpr_vec4_247, - amdgpu_vgpr_vec4_248, - amdgpu_vgpr_vec4_249, - amdgpu_vgpr_vec4_250, - amdgpu_vgpr_vec4_251, - amdgpu_vgpr_vec4_252 -}; -enum AMDGPUVectorGeneralPurposeRegisterVector8{ - amdgpu_vgpr_vec8_0, - amdgpu_vgpr_vec8_1, - amdgpu_vgpr_vec8_2, - amdgpu_vgpr_vec8_3, - amdgpu_vgpr_vec8_4, - amdgpu_vgpr_vec8_5, - amdgpu_vgpr_vec8_6, - amdgpu_vgpr_vec8_7, - amdgpu_vgpr_vec8_8, - amdgpu_vgpr_vec8_9, - amdgpu_vgpr_vec8_10, - amdgpu_vgpr_vec8_11, - amdgpu_vgpr_vec8_12, - amdgpu_vgpr_vec8_13, - amdgpu_vgpr_vec8_14, - amdgpu_vgpr_vec8_15, - amdgpu_vgpr_vec8_16, - amdgpu_vgpr_vec8_17, - amdgpu_vgpr_vec8_18, - amdgpu_vgpr_vec8_19, - amdgpu_vgpr_vec8_20, - amdgpu_vgpr_vec8_21, - amdgpu_vgpr_vec8_22, - amdgpu_vgpr_vec8_23, - amdgpu_vgpr_vec8_24, - amdgpu_vgpr_vec8_25, - amdgpu_vgpr_vec8_26, - amdgpu_vgpr_vec8_27, - amdgpu_vgpr_vec8_28, - amdgpu_vgpr_vec8_29, - amdgpu_vgpr_vec8_30, - amdgpu_vgpr_vec8_31, - amdgpu_vgpr_vec8_32, - amdgpu_vgpr_vec8_33, - amdgpu_vgpr_vec8_34, - amdgpu_vgpr_vec8_35, - amdgpu_vgpr_vec8_36, - amdgpu_vgpr_vec8_37, - amdgpu_vgpr_vec8_38, - amdgpu_vgpr_vec8_39, - amdgpu_vgpr_vec8_40, - amdgpu_vgpr_vec8_41, - amdgpu_vgpr_vec8_42, - amdgpu_vgpr_vec8_43, - amdgpu_vgpr_vec8_44, - amdgpu_vgpr_vec8_45, - amdgpu_vgpr_vec8_46, - amdgpu_vgpr_vec8_47, - amdgpu_vgpr_vec8_48, - amdgpu_vgpr_vec8_49, - amdgpu_vgpr_vec8_50, - amdgpu_vgpr_vec8_51, - amdgpu_vgpr_vec8_52, - amdgpu_vgpr_vec8_53, - amdgpu_vgpr_vec8_54, - amdgpu_vgpr_vec8_55, - amdgpu_vgpr_vec8_56, - amdgpu_vgpr_vec8_57, - amdgpu_vgpr_vec8_58, - amdgpu_vgpr_vec8_59, - amdgpu_vgpr_vec8_60, - amdgpu_vgpr_vec8_61, - amdgpu_vgpr_vec8_62, - amdgpu_vgpr_vec8_63, - amdgpu_vgpr_vec8_64, - amdgpu_vgpr_vec8_65, - amdgpu_vgpr_vec8_66, - amdgpu_vgpr_vec8_67, - amdgpu_vgpr_vec8_68, - amdgpu_vgpr_vec8_69, - amdgpu_vgpr_vec8_70, - amdgpu_vgpr_vec8_71, - amdgpu_vgpr_vec8_72, - amdgpu_vgpr_vec8_73, - amdgpu_vgpr_vec8_74, - amdgpu_vgpr_vec8_75, - amdgpu_vgpr_vec8_76, - amdgpu_vgpr_vec8_77, - amdgpu_vgpr_vec8_78, - amdgpu_vgpr_vec8_79, - amdgpu_vgpr_vec8_80, - amdgpu_vgpr_vec8_81, - amdgpu_vgpr_vec8_82, - amdgpu_vgpr_vec8_83, - amdgpu_vgpr_vec8_84, - amdgpu_vgpr_vec8_85, - amdgpu_vgpr_vec8_86, - amdgpu_vgpr_vec8_87, - amdgpu_vgpr_vec8_88, - amdgpu_vgpr_vec8_89, - amdgpu_vgpr_vec8_90, - amdgpu_vgpr_vec8_91, - amdgpu_vgpr_vec8_92, - amdgpu_vgpr_vec8_93, - amdgpu_vgpr_vec8_94, - amdgpu_vgpr_vec8_95, - amdgpu_vgpr_vec8_96, - amdgpu_vgpr_vec8_97, - amdgpu_vgpr_vec8_98, - amdgpu_vgpr_vec8_99, - amdgpu_vgpr_vec8_100, - amdgpu_vgpr_vec8_101, - amdgpu_vgpr_vec8_102, - amdgpu_vgpr_vec8_103, - amdgpu_vgpr_vec8_104, - amdgpu_vgpr_vec8_105, - amdgpu_vgpr_vec8_106, - amdgpu_vgpr_vec8_107, - amdgpu_vgpr_vec8_108, - amdgpu_vgpr_vec8_109, - amdgpu_vgpr_vec8_110, - amdgpu_vgpr_vec8_111, - amdgpu_vgpr_vec8_112, - amdgpu_vgpr_vec8_113, - amdgpu_vgpr_vec8_114, - amdgpu_vgpr_vec8_115, - amdgpu_vgpr_vec8_116, - amdgpu_vgpr_vec8_117, - amdgpu_vgpr_vec8_118, - amdgpu_vgpr_vec8_119, - amdgpu_vgpr_vec8_120, - amdgpu_vgpr_vec8_121, - amdgpu_vgpr_vec8_122, - amdgpu_vgpr_vec8_123, - amdgpu_vgpr_vec8_124, - amdgpu_vgpr_vec8_125, - amdgpu_vgpr_vec8_126, - amdgpu_vgpr_vec8_127, - amdgpu_vgpr_vec8_128, - amdgpu_vgpr_vec8_129, - amdgpu_vgpr_vec8_130, - amdgpu_vgpr_vec8_131, - amdgpu_vgpr_vec8_132, - amdgpu_vgpr_vec8_133, - amdgpu_vgpr_vec8_134, - amdgpu_vgpr_vec8_135, - amdgpu_vgpr_vec8_136, - amdgpu_vgpr_vec8_137, - amdgpu_vgpr_vec8_138, - amdgpu_vgpr_vec8_139, - amdgpu_vgpr_vec8_140, - amdgpu_vgpr_vec8_141, - amdgpu_vgpr_vec8_142, - amdgpu_vgpr_vec8_143, - amdgpu_vgpr_vec8_144, - amdgpu_vgpr_vec8_145, - amdgpu_vgpr_vec8_146, - amdgpu_vgpr_vec8_147, - amdgpu_vgpr_vec8_148, - amdgpu_vgpr_vec8_149, - amdgpu_vgpr_vec8_150, - amdgpu_vgpr_vec8_151, - amdgpu_vgpr_vec8_152, - amdgpu_vgpr_vec8_153, - amdgpu_vgpr_vec8_154, - amdgpu_vgpr_vec8_155, - amdgpu_vgpr_vec8_156, - amdgpu_vgpr_vec8_157, - amdgpu_vgpr_vec8_158, - amdgpu_vgpr_vec8_159, - amdgpu_vgpr_vec8_160, - amdgpu_vgpr_vec8_161, - amdgpu_vgpr_vec8_162, - amdgpu_vgpr_vec8_163, - amdgpu_vgpr_vec8_164, - amdgpu_vgpr_vec8_165, - amdgpu_vgpr_vec8_166, - amdgpu_vgpr_vec8_167, - amdgpu_vgpr_vec8_168, - amdgpu_vgpr_vec8_169, - amdgpu_vgpr_vec8_170, - amdgpu_vgpr_vec8_171, - amdgpu_vgpr_vec8_172, - amdgpu_vgpr_vec8_173, - amdgpu_vgpr_vec8_174, - amdgpu_vgpr_vec8_175, - amdgpu_vgpr_vec8_176, - amdgpu_vgpr_vec8_177, - amdgpu_vgpr_vec8_178, - amdgpu_vgpr_vec8_179, - amdgpu_vgpr_vec8_180, - amdgpu_vgpr_vec8_181, - amdgpu_vgpr_vec8_182, - amdgpu_vgpr_vec8_183, - amdgpu_vgpr_vec8_184, - amdgpu_vgpr_vec8_185, - amdgpu_vgpr_vec8_186, - amdgpu_vgpr_vec8_187, - amdgpu_vgpr_vec8_188, - amdgpu_vgpr_vec8_189, - amdgpu_vgpr_vec8_190, - amdgpu_vgpr_vec8_191, - amdgpu_vgpr_vec8_192, - amdgpu_vgpr_vec8_193, - amdgpu_vgpr_vec8_194, - amdgpu_vgpr_vec8_195, - amdgpu_vgpr_vec8_196, - amdgpu_vgpr_vec8_197, - amdgpu_vgpr_vec8_198, - amdgpu_vgpr_vec8_199, - amdgpu_vgpr_vec8_200, - amdgpu_vgpr_vec8_201, - amdgpu_vgpr_vec8_202, - amdgpu_vgpr_vec8_203, - amdgpu_vgpr_vec8_204, - amdgpu_vgpr_vec8_205, - amdgpu_vgpr_vec8_206, - amdgpu_vgpr_vec8_207, - amdgpu_vgpr_vec8_208, - amdgpu_vgpr_vec8_209, - amdgpu_vgpr_vec8_210, - amdgpu_vgpr_vec8_211, - amdgpu_vgpr_vec8_212, - amdgpu_vgpr_vec8_213, - amdgpu_vgpr_vec8_214, - amdgpu_vgpr_vec8_215, - amdgpu_vgpr_vec8_216, - amdgpu_vgpr_vec8_217, - amdgpu_vgpr_vec8_218, - amdgpu_vgpr_vec8_219, - amdgpu_vgpr_vec8_220, - amdgpu_vgpr_vec8_221, - amdgpu_vgpr_vec8_222, - amdgpu_vgpr_vec8_223, - amdgpu_vgpr_vec8_224, - amdgpu_vgpr_vec8_225, - amdgpu_vgpr_vec8_226, - amdgpu_vgpr_vec8_227, - amdgpu_vgpr_vec8_228, - amdgpu_vgpr_vec8_229, - amdgpu_vgpr_vec8_230, - amdgpu_vgpr_vec8_231, - amdgpu_vgpr_vec8_232, - amdgpu_vgpr_vec8_233, - amdgpu_vgpr_vec8_234, - amdgpu_vgpr_vec8_235, - amdgpu_vgpr_vec8_236, - amdgpu_vgpr_vec8_237, - amdgpu_vgpr_vec8_238, - amdgpu_vgpr_vec8_239, - amdgpu_vgpr_vec8_240, - amdgpu_vgpr_vec8_241, - amdgpu_vgpr_vec8_242, - amdgpu_vgpr_vec8_243, - amdgpu_vgpr_vec8_244, - amdgpu_vgpr_vec8_245, - amdgpu_vgpr_vec8_246, - amdgpu_vgpr_vec8_247, - amdgpu_vgpr_vec8_248 -}; -enum AmdgpuVegaInstructionKind{ +enum AMDGPUInstructionKind{ rose_amdgpu_op_INVALID =0, rose_amdgpu_op_s_cmp_ge_eq_i32, rose_amdgpu_op_s_cmp_ge_eq_u32, @@ -1595,4 +727,4 @@ enum AmdgpuVegaInstructionKind{ rose_amdgpu_op_v_cvt_off_f32_i4, rose_amdgpu_op_v_pk_mad_i16 }; -#endif \ No newline at end of file +#endif diff --git a/external/rose/rose-compat.h b/external/rose/rose-compat.h index f59f1fdef2..443e86b7a3 100644 --- a/external/rose/rose-compat.h +++ b/external/rose/rose-compat.h @@ -844,7 +844,7 @@ enum VariantT { V_SgAsmFieldDeclaration = 932, V_SgAsmDataStructureDeclaration = 933, V_SgAsmPEImportILTEntryList = 934, - V_SgAsmAmdgpuVegaInstruction = 935, + V_SgAsmAMDGPUInstruction = 935, }; enum X86SegmentRegister { // These must match numbering in object code diff --git a/external/stdint-win.h b/external/stdint-win.h deleted file mode 100644 index 9d0d6f9eb1..0000000000 --- a/external/stdint-win.h +++ /dev/null @@ -1,245 +0,0 @@ -// ISO C9x compliant stdint.h for Microsoft Visual Studio -// Based on ISO/IEC 9899:TC2 Committee draft (May 6, 2005) WG14/N1124 -// -// Copyright (c) 2006-2008 Alexander Chemeris -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// 1. Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// -// 2. Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the distribution. -// -// 3. The name of the author may be used to endorse or promote products -// derived from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED -// WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO -// EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; -// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR -// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF -// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -/////////////////////////////////////////////////////////////////////////////// - -#ifndef _MSC_VER // [ -#error "Use this header only with Microsoft Visual C++ compilers!" -#endif // _MSC_VER ] - -// Modern Visual Studio has sane stdint.h -#if _MSC_VER >= 1900 -#include -#define _MSC_STDINT_H_ -#endif - -#ifndef _MSC_STDINT_H_ // [ -#define _MSC_STDINT_H_ - -#if _MSC_VER > 1000 -#pragma once -#endif - -#include - -// For Visual Studio 6 in C++ mode and for many Visual Studio versions when -// compiling for ARM we should wrap include with 'extern "C++" {}' -// or compiler give many errors like this: -// error C2733: second C linkage of overloaded function 'wmemchr' not allowed -#ifdef __cplusplus -extern "C" { -#endif -# include -#ifdef __cplusplus -} -#endif - -// Define _W64 macros to mark types changing their size, like intptr_t. -#ifndef _W64 -# if !defined(__midl) && (defined(_X86_) || defined(_M_IX86)) && _MSC_VER >= 1300 -# define _W64 __w64 -# else -# define _W64 -# endif -#endif - - -// 7.18.1 Integer types - -// 7.18.1.1 Exact-width integer types - -// Visual Studio 6 and Embedded Visual C++ 4 doesn't -// realize that, e.g. char has the same size as __int8 -// so we give up on __intX for them. -#if (_MSC_VER < 1300) - typedef signed char int8_t; - typedef signed short int16_t; - typedef signed int int32_t; - typedef unsigned char uint8_t; - typedef unsigned short uint16_t; - typedef unsigned int uint32_t; -#else - typedef signed __int8 int8_t; - typedef signed __int16 int16_t; - typedef signed __int32 int32_t; - typedef unsigned __int8 uint8_t; - typedef unsigned __int16 uint16_t; - typedef unsigned __int32 uint32_t; -#endif -typedef signed __int64 int64_t; -typedef unsigned __int64 uint64_t; - - -// 7.18.1.2 Minimum-width integer types -typedef int8_t int_least8_t; -typedef int16_t int_least16_t; -typedef int32_t int_least32_t; -typedef int64_t int_least64_t; -typedef uint8_t uint_least8_t; -typedef uint16_t uint_least16_t; -typedef uint32_t uint_least32_t; -typedef uint64_t uint_least64_t; - -// 7.18.1.3 Fastest minimum-width integer types - -// 7.18.1.4 Integer types capable of holding object pointers -#ifdef _WIN64 // [ - typedef signed __int64 intptr_t; - typedef unsigned __int64 uintptr_t; -#else // _WIN64 ][ - typedef _W64 signed int intptr_t; - typedef _W64 unsigned int uintptr_t; -#endif // _WIN64 ] - -// 7.18.1.5 Greatest-width integer types -typedef int64_t intmax_t; -typedef uint64_t uintmax_t; - - -// 7.18.2 Limits of specified-width integer types - -#if !defined(__cplusplus) || defined(__STDC_LIMIT_MACROS) // [ See footnote 220 at page 257 and footnote 221 at page 259 - -// 7.18.2.1 Limits of exact-width integer types -#define INT8_MIN ((int8_t)_I8_MIN) -#define INT8_MAX _I8_MAX -#define INT16_MIN ((int16_t)_I16_MIN) -#define INT16_MAX _I16_MAX -#define INT32_MIN ((int32_t)_I32_MIN) -#define INT32_MAX _I32_MAX -#define INT64_MIN ((int64_t)_I64_MIN) -#define INT64_MAX _I64_MAX -#define UINT8_MAX _UI8_MAX -#define UINT16_MAX _UI16_MAX -#define UINT32_MAX _UI32_MAX -#define UINT64_MAX _UI64_MAX - -// 7.18.2.2 Limits of minimum-width integer types -#define INT_LEAST8_MIN INT8_MIN -#define INT_LEAST8_MAX INT8_MAX -#define INT_LEAST16_MIN INT16_MIN -#define INT_LEAST16_MAX INT16_MAX -#define INT_LEAST32_MIN INT32_MIN -#define INT_LEAST32_MAX INT32_MAX -#define INT_LEAST64_MIN INT64_MIN -#define INT_LEAST64_MAX INT64_MAX -#define UINT_LEAST8_MAX UINT8_MAX -#define UINT_LEAST16_MAX UINT16_MAX -#define UINT_LEAST32_MAX UINT32_MAX -#define UINT_LEAST64_MAX UINT64_MAX - -// 7.18.2.3 Limits of fastest minimum-width integer types -#define INT_FAST8_MIN INT8_MIN -#define INT_FAST8_MAX INT8_MAX -#define INT_FAST16_MIN INT16_MIN -#define INT_FAST16_MAX INT16_MAX -#define INT_FAST32_MIN INT32_MIN -#define INT_FAST32_MAX INT32_MAX -#define INT_FAST64_MIN INT64_MIN -#define INT_FAST64_MAX INT64_MAX -#define UINT_FAST8_MAX UINT8_MAX -#define UINT_FAST16_MAX UINT16_MAX -#define UINT_FAST32_MAX UINT32_MAX -#define UINT_FAST64_MAX UINT64_MAX - -// 7.18.2.4 Limits of integer types capable of holding object pointers -#ifdef _WIN64 // [ -# define INTPTR_MIN INT64_MIN -# define INTPTR_MAX INT64_MAX -# define UINTPTR_MAX UINT64_MAX -#else // _WIN64 ][ -# define INTPTR_MIN INT32_MIN -# define INTPTR_MAX INT32_MAX -# define UINTPTR_MAX UINT32_MAX -#endif // _WIN64 ] - -// 7.18.2.5 Limits of greatest-width integer types -#define INTMAX_MIN INT64_MIN -#define INTMAX_MAX INT64_MAX -#define UINTMAX_MAX UINT64_MAX - -// 7.18.3 Limits of other integer types - -#ifdef _WIN64 // [ -# define PTRDIFF_MIN _I64_MIN -# define PTRDIFF_MAX _I64_MAX -#else // _WIN64 ][ -# define PTRDIFF_MIN _I32_MIN -# define PTRDIFF_MAX _I32_MAX -#endif // _WIN64 ] - -#define SIG_ATOMIC_MIN INT_MIN -#define SIG_ATOMIC_MAX INT_MAX - -#ifndef SIZE_MAX // [ -# ifdef _WIN64 // [ -# define SIZE_MAX _UI64_MAX -# else // _WIN64 ][ -# define SIZE_MAX _UI32_MAX -# endif // _WIN64 ] -#endif // SIZE_MAX ] - -// WCHAR_MIN and WCHAR_MAX are also defined in -#ifndef WCHAR_MIN // [ -# define WCHAR_MIN 0 -#endif // WCHAR_MIN ] -#ifndef WCHAR_MAX // [ -# define WCHAR_MAX _UI16_MAX -#endif // WCHAR_MAX ] - -#define WINT_MIN 0 -#define WINT_MAX _UI16_MAX - -#endif // __STDC_LIMIT_MACROS ] - - -// 7.18.4 Limits of other integer types - -#if !defined(__cplusplus) || defined(__STDC_CONSTANT_MACROS) && (_MSC_VER < 1600) // [ See footnote 224 at page 260 - -// 7.18.4.1 Macros for minimum-width integer constants - -#define INT8_C(val) val##i8 -#define INT16_C(val) val##i16 -#define INT32_C(val) val##i32 -#define INT64_C(val) val##i64 - -#define UINT8_C(val) val##ui8 -#define UINT16_C(val) val##ui16 -#define UINT32_C(val) val##ui32 -#define UINT64_C(val) val##ui64 - -// 7.18.4.2 Macros for greatest-width integer constants -#define INTMAX_C INT64_C -#define UINTMAX_C UINT64_C - -#endif // __STDC_CONSTANT_MACROS ] - - -#endif // _MSC_STDINT_H_ ] diff --git a/instructionAPI/CMakeLists.txt b/instructionAPI/CMakeLists.txt index b55de862ff..72cc9276e1 100644 --- a/instructionAPI/CMakeLists.txt +++ b/instructionAPI/CMakeLists.txt @@ -1,62 +1,150 @@ -# CMake configuration for instructionAPI directory - -include_directories ( - ${PROJECT_SOURCE_DIR}/instructionAPI/src - ) - - -set (SRC_LIST - src/Instruction.C - src/InstructionAST.C - src/Operation.C - src/Operand.C - src/Register.C - src/Ternary.C - src/Expression.C - src/BinaryFunction.C - src/InstructionCategories.C - src/ArchSpecificFormatters.C - src/Immediate.C - src/InstructionDecoder.C - src/InstructionDecoder-x86.C - src/InstructionDecoder-power.C - src/InstructionDecoder-aarch64.C - src/InstructionDecoder-amdgpu-vega.C - src/InstructionDecoderImpl.C - ) -SET_SOURCE_FILES_PROPERTIES(${SRC_LIST} PROPERTIES LANGUAGE CXX) +include_guard(GLOBAL) + +include(DyninstLibrary) + +set(_sources + src/debug.C + src/Instruction.C + src/InstructionAST.C + src/Operation.C + src/Operand.C + src/Register.C + src/Ternary.C + src/Expression.C + src/BinaryFunction.C + src/InstructionCategories.C + src/ArchSpecificFormatters.C + src/Immediate.C + src/InstructionDecoder.C + src/InstructionDecoder-x86.C + src/InstructionDecoder-power.C + src/InstructionDecoder-aarch64.C + src/AMDGPU/gfx908/decodeOperands.C + src/AMDGPU/gfx908/appendOperands.C + src/AMDGPU/gfx908/finalizeOperands.C + src/AMDGPU/gfx908/amdgpu_gfx908_decoder_impl.C + src/AMDGPU/gfx908/InstructionDecoder-amdgpu-gfx908.C + src/AMDGPU/gfx90a/decodeOperands.C + src/AMDGPU/gfx90a/appendOperands.C + src/AMDGPU/gfx90a/finalizeOperands.C + src/AMDGPU/gfx90a/amdgpu_gfx90a_decoder_impl.C + src/AMDGPU/gfx90a/InstructionDecoder-amdgpu-gfx90a.C + src/AMDGPU/gfx940/decodeOperands.C + src/AMDGPU/gfx940/appendOperands.C + src/AMDGPU/gfx940/finalizeOperands.C + src/AMDGPU/gfx940/amdgpu_gfx940_decoder_impl.C + src/AMDGPU/gfx940/InstructionDecoder-amdgpu-gfx940.C + src/InstructionDecoderImpl.C + src/syscalls.C + src/interrupts.C) + +set(_public_headers + h/ArchSpecificFormatters.h + h/BinaryFunction.h + h/Dereference.h + h/Expression.h + h/Immediate.h + h/InstructionAST.h + h/InstructionCategories.h + h/InstructionDecoder.h + h/Instruction.h + h/Operand.h + h/Operation_impl.h + h/Register.h + h/Result.h + h/Ternary.h + h/Visitor.h) + +set(_private_headers + src/debug.h + src/amdgpu_branchinsn_table.h + src/AMDGPU/gfx940/InstructionDecoder-amdgpu-gfx940.h + src/AMDGPU/gfx90a/InstructionDecoder-amdgpu-gfx90a.h + src/AMDGPU/gfx908/InstructionDecoder-amdgpu-gfx908.h + src/InstructionDecoder-aarch64.h + src/InstructionDecoderImpl.h + src/InstructionDecoder-power.h + src/InstructionDecoder-x86.h + h/syscalls.h + h/interrupts.h) set(instructionDecoderPowerExtraFlags "") -if (${CMAKE_CXX_COMPILER_ID} MATCHES "GNU") - if (${CMAKE_CXX_COMPILER_VERSION} MATCHES "^([1-9]|1[01])(\.|$)") - # Disable var-tracking-assignments for InstructionDecoder-power.C for - # all known versions of gcc.. The default max size is too small so it - # fails, and adjusting it using - # - # PROPERTIES COMPILE_FLAGS "--param=max-vartrack-size=900000000" - # - # succeeds, but the object file produced is >1GB, so disable it. - string(APPEND instructionDecoderPowerExtraFlags "-fno-var-tracking-assignments") - endif() +if(${CMAKE_CXX_COMPILER_ID} MATCHES "GNU") + if(${CMAKE_CXX_COMPILER_VERSION} MATCHES "^([1-9]|1[01])(\.|$)") + # Disable var-tracking-assignments for InstructionDecoder-power.C for all known + # versions of gcc.. The default max size is too small so it fails, and adjusting + # it using + # + # PROPERTIES COMPILE_FLAGS "--param=max-vartrack-size=900000000" + # + # succeeds, but the object file produced is >1GB, so disable it. + string(APPEND instructionDecoderPowerExtraFlags "-fno-var-tracking-assignments") + endif() endif() # adjust warning threshold if set in cmake/warnings.cmake -if (debugMaxFrameSizeOverridePowerOpcodeTable) - string(APPEND instructionDecoderPowerExtraFlags - " $<$:-Wframe-larger-than=${debugMaxFrameSizeOverridePowerOpcodeTable}>") +if(debugMaxFrameSizeOverridePowerOpcodeTable) + string( + APPEND instructionDecoderPowerExtraFlags + " $<$:-Wframe-larger-than=${debugMaxFrameSizeOverridePowerOpcodeTable}>" + ) +endif() +if(nonDebugMaxFrameSizeOverridePowerOpcodeTable) + string( + APPEND + instructionDecoderPowerExtraFlags + " $<$>:-Wframe-larger-than=${nonDebugMaxFrameSizeOverridePowerOpcodeTable}>" + ) +endif() + +if(NOT instructionDecoderPowerExtraFlags STREQUAL "") + set_source_files_properties( + src/InstructionDecoder-power.C PROPERTIES COMPILE_FLAGS + "${instructionDecoderPowerExtraFlags}") +endif() + +set(finalizeOperandsExtraFlags "") +if(debugMaxFrameSizeOverrideFinalizeOperands) + string( + APPEND finalizeOperandsExtraFlags + " $<$:-Wframe-larger-than=${debugMaxFrameSizeOverrideFinalizeOperands}>" + ) endif() -if (nonDebugMaxFrameSizeOverridePowerOpcodeTable) - string(APPEND instructionDecoderPowerExtraFlags - " $<$>:-Wframe-larger-than=${nonDebugMaxFrameSizeOverridePowerOpcodeTable}>") +if(nonDebugMaxFrameSizeOverrideFinalizeOperands) + string( + APPEND + finalizeOperandsExtraFlags + " $<$>:-Wframe-larger-than=${nonDebugMaxFrameSizeOverrideFinalizeOperands}>" + ) endif() -if (NOT instructionDecoderPowerExtraFlags STREQUAL "") - SET_SOURCE_FILES_PROPERTIES(src/InstructionDecoder-power.C - PROPERTIES COMPILE_FLAGS "${instructionDecoderPowerExtraFlags}") +if(NOT finalizeOperandsExtraFlags STREQUAL "") + set_source_files_properties(src/AMDGPU/gfx940/InstructionDecoder-amdgpu-gfx940.C + PROPERTIES COMPILE_FLAGS "${finalizeOperandsExtraFlags}") + set_source_files_properties(src/AMDGPU/gfx90a/InstructionDecoder-amdgpu-gfx90a.C + PROPERTIES COMPILE_FLAGS "${finalizeOperandsExtraFlags}") + set_source_files_properties(src/AMDGPU/gfx908/InstructionDecoder-amdgpu-gfx908.C + PROPERTIES COMPILE_FLAGS "${finalizeOperandsExtraFlags}") endif() -ADD_DEFINITIONS(-DINSTRUCTION_LIB) +# cmake-format: off +dyninst_library( + instructionAPI + PUBLIC_HEADER_FILES ${_public_headers} + PRIVATE_HEADER_FILES ${_private_headers} + SOURCE_FILES ${_sources} + DEFINES INSTRUCTION_LIB + DYNINST_DEPS common + PUBLIC_DEPS +) +# cmake-format: on -dyninst_library(instructionAPI common) +set(_inc_dirs + ${CMAKE_CURRENT_SOURCE_DIR}/src/AMDGPU/gfx940 + ${CMAKE_CURRENT_SOURCE_DIR}/src/AMDGPU/gfx90a + ${CMAKE_CURRENT_SOURCE_DIR}/src/AMDGPU/gfx908) -target_link_private_libraries(instructionAPI ${Boost_LIBRARIES} ${TBB_LIBRARIES} tbbmalloc) +foreach(t ${instructionAPI_TARGETS}) + target_include_directories(${t} PUBLIC "$") +endforeach() +unset(_inc_dirs) diff --git a/instructionAPI/ISA_ps/encodingindex b/instructionAPI/ISA_ps/encodingindex deleted file mode 100644 index e69de29bb2..0000000000 diff --git a/instructionAPI/ISA_ps/enumerated-symbol-accounts b/instructionAPI/ISA_ps/enumerated-symbol-accounts deleted file mode 100644 index e69de29bb2..0000000000 diff --git a/instructionAPI/ISA_ps/fpsimdindex b/instructionAPI/ISA_ps/fpsimdindex deleted file mode 100644 index e69de29bb2..0000000000 diff --git a/instructionAPI/ISA_ps/index b/instructionAPI/ISA_ps/index deleted file mode 100644 index e69de29bb2..0000000000 diff --git a/instructionAPI/ISA_ps/permindex b/instructionAPI/ISA_ps/permindex deleted file mode 100644 index e69de29bb2..0000000000 diff --git a/instructionAPI/ISA_ps/shared_pseudocode b/instructionAPI/ISA_ps/shared_pseudocode deleted file mode 100644 index e69de29bb2..0000000000 diff --git a/instructionAPI/capstone/aarch64.py b/instructionAPI/capstone/aarch64.py new file mode 100644 index 0000000000..f86441f294 --- /dev/null +++ b/instructionAPI/capstone/aarch64.py @@ -0,0 +1,7 @@ +class aarch64: + + def __init__(self): + self.aliasMap = {} + self.capstone_prefix = "ARM64" + self.dyninst_prefix = "aarch64_op" + self.dyninst_register_prefix="aarch64" diff --git a/instructionAPI/capstone/capstone.py b/instructionAPI/capstone/capstone.py new file mode 100644 index 0000000000..9e9da4c1f9 --- /dev/null +++ b/instructionAPI/capstone/capstone.py @@ -0,0 +1,12 @@ +import re + +def read_mnemonics(file:str): + # Format is ' "name", // X86_INS_NAME' + reg = re.compile(r'\s+\"(.+)?\", \/\/') + mnemonics = [] + with open(file, "r") as f: + for line in f: + matches = reg.search(line) + if matches: + mnemonics.append(matches.group(1)) + return sorted(mnemonics) diff --git a/instructionAPI/capstone/import.py b/instructionAPI/capstone/import.py new file mode 100644 index 0000000000..5ad6defd5d --- /dev/null +++ b/instructionAPI/capstone/import.py @@ -0,0 +1,56 @@ +import argparse +import capstone +import x86 + +""" + Process and import Capstone instruction mnemonics + + Each architecture is in a separate module and implements things like mnemonic prefixes and + instruction aliases. The latter must be manually updated as more instructions are added to + the ISAs. + + Usage: + The mnemonics are stored in the output file 'mnemonics'. This can be directly copied to + the appropriate architecture file in Dyninst (e.g., common/mnemonics/x86_entryIDs.h). + Examining changes is then most easily done using git. +""" + +if __name__ == "__main__": + parser = argparse.ArgumentParser( + description="Translate Capstone instruction data structures to Dyninst instruction data structures" + ) + parser.add_argument( + "--capstone", + type=str, + required=True, + help="Capstone header (e.g., /capstone-engine/capstone/arch/X86/X86MappingInsnName.inc)" + ) + + parser.add_argument("--arch", type=str, choices=["x86"], default="x86") + args = parser.parse_args() + + if args.arch == "x86": + translator = x86.x86() + + with open("mnemonics", "w") as f: + for p in translator.pseudo: + f.write("{0:s}_{1:s}, /* pseudo mnemonic */\n".format(translator.dyninst_prefix, p)) + + mnemonics = capstone.read_mnemonics(args.capstone) + mnemonics.extend(translator.missing) + mnemonics.sort() + + # Remove already-printed names + mnemonics = [m for m in mnemonics if m not in translator.pseudo] + + for m in mnemonics: + if m not in translator.aliases: + f.write("{0:s}_{1:s},\n".format(translator.dyninst_prefix, m)) + continue + + if not translator.aliases[m]["seen"]: + f.write("{0:s}_{1:s},\n".format(translator.dyninst_prefix, m)) + translator.aliases[m]["seen"] = True + for a in translator.aliases[m]["values"]: + f.write("{0:s}_{1:s} = {0:s}_{2:s},\n".format(translator.dyninst_prefix, a, m)) + translator.aliases[a]["seen"] = True diff --git a/instructionAPI/capstone/ppc.py b/instructionAPI/capstone/ppc.py new file mode 100644 index 0000000000..06f0309519 --- /dev/null +++ b/instructionAPI/capstone/ppc.py @@ -0,0 +1,8 @@ +class ppc: + + def __init__(self): + self.aliasMap = {} + + self.capstone_prefix = "PPC" + self.dyninst_prefix = "power_op" + self.dyninst_regiseter_prefix="ppc64" diff --git a/instructionAPI/capstone/x86.py b/instructionAPI/capstone/x86.py new file mode 100644 index 0000000000..eface662be --- /dev/null +++ b/instructionAPI/capstone/x86.py @@ -0,0 +1,183 @@ +class x86: + + def __init__(self): + self.capstone_prefix = "X86" + self.dyninst_prefix = "e" + self.dyninst_register_prefix = "x86_64" + + # Mnemonics missing in Capstone + self.missing = [ "faddp" ] + + # Pseudo-mnemonics used in Dyninst and Capstone + # The ones from Capstone are used for GNU assembler (gas) compatibility + self.pseudo = [ + "No_Entry", # needs to be first + "3dnow_generic", + "fp_generic", + "int80", + "jb_jnaej_j", + "jcxz_jec", + "jnb_jae_j", + "movlps_movhlps", + "movhps_movlhps", + "movsd_sse", + "pextrd_pextrq", + "pinsrd_pinsrq", + "prefetch_w", + "ud2grp10 ", + "ret_far", + "ret_near", + "lcall", # From Capstone + "clzero" # From Capstone + ] + + # x86 has a great many aliased opcodes. This table represents the mappings between + # the various mnemonics associated with those opcodes. There are also opcodes with + # distinct values that map to the same mnemonic (e.g., 0x14 and 0x15 are "ADC"). + # Those are left to Capstone to figure out. We just represent the single mnemonic + # as defined in the SDM. + # + # AT&T aliases (e.g., call vs callq) are not included. + # + # Aliases that come from the LLVM tablegen files are marked as such. Otherwise, + # they come from the Volume 2 Instruction Set Referece in the Intel 64 and IA-32 + # Architectures Software Developer’s Manual (SDM) June 2021 edition with a heading like + # X/Y (e.g., CBW/CWDE/CDQE). + # + # All conditional operations are included. + # Aliases for the FCMOVcc or LOOPcc mnemonics do not exist. We also ignore jcxz b/c as it's + # a 16-bit instruction. + + self.aliases = { + "bndcu" : { "seen" : False, "values" : ["bndcn"] }, + "bndcn" : { "seen" : False, "values" : ["bndcu"] }, + + "cbw" : { "seen" : False, "values" : ["cdqe",] }, + "cdqe" : { "seen" : False, "values" : ["cbw",] }, + + "cdq" : { "seen" : False, "values" : ["cwd", "cqo",] }, + "cqo" : { "seen" : False, "values" : ["cwd", "cdq",] }, + "cwd" : { "seen" : False, "values" : ["cdq", "cqo",] }, + + "cmovb" : { "seen" : False, "values" : ["cmovc", "cmovnae",] }, + "cmovc" : { "seen" : False, "values" : ["cmovb", "cmovnae",] }, + "cmovnae" : { "seen" : False, "values" : ["cmovb", "cmovc",] }, + "cmovae" : { "seen" : False, "values" : ["cmovnb", "cmovnc",] }, + "cmovnb" : { "seen" : False, "values" : ["cmovae", "cmovnc",] }, + "cmovnc" : { "seen" : False, "values" : ["cmovae", "cmovnb",] }, + "cmove" : { "seen" : False, "values" : ["cmovz",] }, + "cmovz" : { "seen" : False, "values" : ["cmove",] }, + "cmovne" : { "seen" : False, "values" : ["cmovnz",] }, + "cmovnz" : { "seen" : False, "values" : ["cmovne",] }, + "cmovbe" : { "seen" : False, "values" : ["cmovna",] }, + "cmovna" : { "seen" : False, "values" : ["cmovbe",] }, + "cmova" : { "seen" : False, "values" : ["cmovnbe",] }, + "cmovnbe" : { "seen" : False, "values" : ["cmova",] }, + "cmovp" : { "seen" : False, "values" : ["cmovpe",] }, + "cmovpe" : { "seen" : False, "values" : ["cmovp",] }, + "cmovnp" : { "seen" : False, "values" : ["cmovpo",] }, + "cmovpo" : { "seen" : False, "values" : ["cmovnp",] }, + "cmovl" : { "seen" : False, "values" : ["cmovnge",] }, + "cmovnge" : { "seen" : False, "values" : ["cmovl",] }, + "cmovge" : { "seen" : False, "values" : ["cmovnl",] }, + "cmovnl" : { "seen" : False, "values" : ["cmovge",] }, + "cmovle" : { "seen" : False, "values" : ["cmovng",] }, + "cmovng" : { "seen" : False, "values" : ["cmovle",] }, + "cmovg" : { "seen" : False, "values" : ["cmovnle",] }, + "cmovnle" : { "seen" : False, "values" : ["cmovg",] }, + "fcompi" : { "seen" : False, "values" : ["fcomip",] }, # From LLVM, but present in bddisasm, binutils, and xed + "fcomip" : { "seen" : False, "values" : ["fcompi",] }, + "fucomip" : { "seen" : False, "values" : ["fucompi",] }, + "fucompi" : { "seen" : False, "values" : ["fucomip",] }, # From LLVM + "iret" : { "seen" : False, "values" : ["iretd", "iretq",] }, + "iretd" : { "seen" : False, "values" : ["iret", "iretq",] }, + "iretq" : { "seen" : False, "values" : ["iret", "iretd",] }, + "jb" : { "seen" : False, "values" : ["jc", "jnae",] }, + "jc" : { "seen" : False, "values" : ["jb", "jnae",] }, + "jnae" : { "seen" : False, "values" : ["jb", "jc",] }, + "jae" : { "seen" : False, "values" : ["jnb", "jnc",] }, + "jnb" : { "seen" : False, "values" : ["jae", "jnc",] }, + "jnc" : { "seen" : False, "values" : ["jae", "jnb",] }, + "je" : { "seen" : False, "values" : ["jz",] }, + "jz" : { "seen" : False, "values" : ["je",] }, + "jne" : { "seen" : False, "values" : ["jnz",] }, + "jnz" : { "seen" : False, "values" : ["jne",] }, + "jbe" : { "seen" : False, "values" : ["jna",] }, + "jna" : { "seen" : False, "values" : ["jbe",] }, + "ja" : { "seen" : False, "values" : ["jnbe",] }, + "jnbe" : { "seen" : False, "values" : ["ja",] }, + "js" : { "seen" : False, "values" : [] }, + "jns" : { "seen" : False, "values" : [] }, + "jp" : { "seen" : False, "values" : ["jpe",] }, + "jpe" : { "seen" : False, "values" : ["jp",] }, + "jnp" : { "seen" : False, "values" : ["jpo",] }, + "jpo" : { "seen" : False, "values" : ["jnp",] }, + "jl" : { "seen" : False, "values" : ["jnge",] }, + "jnge" : { "seen" : False, "values" : ["jl",] }, + "jge" : { "seen" : False, "values" : ["jnl",] }, + "jnl" : { "seen" : False, "values" : ["jge",] }, + "jle" : { "seen" : False, "values" : ["jng",] }, + "jng" : { "seen" : False, "values" : ["jle",] }, + "jg" : { "seen" : False, "values" : ["jnle",] }, + "jnle" : { "seen" : False, "values" : ["jg",] }, + "jcxz" : { "seen" : False, "values" : ["jecxz", "jrcxz",] }, + "jecxz" : { "seen" : False, "values" : ["jcxz", "jrcxz",] }, + "jrcxz" : { "seen" : False, "values" : ["jcxz", "jecxz",] }, + "lods" : { "seen" : False, "values" : ["lodsb",] }, # LLVM, bddisasm, binutils, and xed all agree + "lodsb" : { "seen" : False, "values" : ["lods",] }, + "loope" : { "seen" : False, "values" : ["loopz",] }, # LLVM + "loopz" : { "seen" : False, "values" : ["loope",] }, + "loopne" : { "seen" : False, "values" : ["loopnz",] }, + "loopnz" : { "seen" : False, "values" : ["loopne",] }, # Not a valid mnemonic for 0xE0, but used in LLVM, bddisasm, and binutils + "monitor" : { "seen" : False, "values" : ["monitorx"] }, + "monitorx" : { "seen" : False, "values" : ["monitor"] }, + "mwait" : { "seen" : False, "values" : ["mwaitx"] }, + "mwaitx" : { "seen" : False, "values" : ["mwait"] }, + # Capstone uses popal, but everyone else uses popa. popal isn't in the SDM. + "popa" : { "seen" : False, "values" : ["popal",] }, + "popal" : { "seen" : False, "values" : ["popa",] }, + # Capstone uses popaw, but everyone else uses popad. popaw isn't in the SDM. + "popad" : { "seen" : False, "values" : ["popaw",] }, + "popaw" : { "seen" : False, "values" : ["popad",] }, + # Capstone treats POP{F,D,Q} as separate mnemonics, even though they share an opcode (0x9D) + # Capstone uses non-standard pusha{l,w}. + "pusha" : { "seen" : False, "values" : ["pushad", "pushal", "pushaw",] }, + "pushad" : { "seen" : False, "values" : ["pusha", "pushal", "pushaw",] }, + "pushal" : { "seen" : False, "values" : ["pusha", "pushad", "pushaw",] }, + "pushaw" : { "seen" : False, "values" : ["pusha", "pushad", "pushal",] }, + "pushf" : { "seen" : False, "values" : ["pushfd", "pushfq",] }, + "pushfd" : { "seen" : False, "values" : ["pushf", "pushfq",] }, + "pushfq" : { "seen" : False, "values" : ["pushf", "pushfd",] }, + "retfq" : { "seen" : False, "values" : ["retf",] }, + "retf" : { "seen" : False, "values" : ["retfq",] }, + "setb" : { "seen" : False, "values" : ["setc", "setnae",] }, + "setc" : { "seen" : False, "values" : ["setb", "setnae",] }, + "setnae" : { "seen" : False, "values" : ["setb", "setc",] }, + "setae" : { "seen" : False, "values" : ["setnb", "setnc",] }, + "setnb" : { "seen" : False, "values" : ["setae", "setnc",] }, + "setnc" : { "seen" : False, "values" : ["setae", "setnb",] }, + "sete" : { "seen" : False, "values" : ["setz",] }, + "setz" : { "seen" : False, "values" : ["sete",] }, + "setne" : { "seen" : False, "values" : ["setnz",] }, + "setnz" : { "seen" : False, "values" : ["setne",] }, + "setbe" : { "seen" : False, "values" : ["setna",] }, + "setna" : { "seen" : False, "values" : ["setbe",] }, + "seta" : { "seen" : False, "values" : ["setnbe",] }, + "setnbe" : { "seen" : False, "values" : ["seta",] }, + "setp" : { "seen" : False, "values" : ["setpe",] }, + "setpe" : { "seen" : False, "values" : ["setp",] }, + "setnp" : { "seen" : False, "values" : ["setpo",] }, + "setpo" : { "seen" : False, "values" : ["setnp",] }, + "setl" : { "seen" : False, "values" : ["setnge",] }, + "setnge" : { "seen" : False, "values" : ["setl",] }, + "setge" : { "seen" : False, "values" : ["setnl",] }, + "setnl" : { "seen" : False, "values" : ["setge",] }, + "setle" : { "seen" : False, "values" : ["setng",] }, + "setng" : { "seen" : False, "values" : ["setle",] }, + "setg" : { "seen" : False, "values" : ["setnle",] }, + "setnle" : { "seen" : False, "values" : ["setg",] }, + "wait" : { "seen" : False, "values" : ["fwait",] }, + "fwait" : { "seen" : False, "values" : ["wait",] }, + "xlat" : { "seen" : False, "values" : ["xlatb",] }, + "xlatb" : { "seen" : False, "values" : ["xlat",] } + } diff --git a/instructionAPI/doc/instructionAPI.pdf b/instructionAPI/doc/instructionAPI.pdf index 712c01d11e..04e7e858e6 100644 Binary files a/instructionAPI/doc/instructionAPI.pdf and b/instructionAPI/doc/instructionAPI.pdf differ diff --git a/instructionAPI/h/ArchSpecificFormatters.h b/instructionAPI/h/ArchSpecificFormatters.h index d0d740a853..0509a16d7d 100644 --- a/instructionAPI/h/ArchSpecificFormatters.h +++ b/instructionAPI/h/ArchSpecificFormatters.h @@ -33,21 +33,24 @@ #include #include +#include #include -#include "dyn_regs.h" +#include "Architecture.h" +#include "registers/MachRegister.h" namespace Dyninst { namespace InstructionAPI { class ArchSpecificFormatter { public: - virtual std::string getInstructionString(std::vector ) = 0; - virtual std::string formatImmediate(std::string) = 0; - virtual std::string formatDeref(std::string) = 0; - virtual std::string formatRegister(std::string) = 0; - virtual std::string formatBinaryFunc(std::string, std::string, std::string); + virtual std::string getInstructionString(const std::vector &) const; + virtual std::string formatImmediate(const std::string&) const = 0; + virtual std::string formatDeref(const std::string&) const= 0; + virtual std::string formatRegister(const std::string&) const= 0; + virtual std::string formatBinaryFunc(const std::string&, const std::string&, const std::string&) const; + virtual bool operandPrintOrderReversed() const; virtual ~ArchSpecificFormatter() = default; - ArchSpecificFormatter& operator=(const ArchSpecificFormatter&) = default; + ArchSpecificFormatter& operator=(const ArchSpecificFormatter&) = default; static INSTRUCTION_EXPORT ArchSpecificFormatter& getFormatter(Dyninst::Architecture a); }; @@ -56,11 +59,10 @@ namespace Dyninst { public: PPCFormatter(); - virtual std::string getInstructionString(std::vector ); - virtual std::string formatImmediate(std::string); - virtual std::string formatDeref(std::string); - virtual std::string formatRegister(std::string); - virtual std::string formatBinaryFunc(std::string, std::string, std::string); + std::string formatImmediate(const std::string&) const override; + std::string formatDeref(const std::string&) const override; + std::string formatRegister(const std::string&) const override; + std::string formatBinaryFunc(const std::string&, const std::string&, const std::string&) const override; }; @@ -68,11 +70,10 @@ namespace Dyninst { public: ArmFormatter(); - virtual std::string getInstructionString(std::vector ); - virtual std::string formatImmediate(std::string); - virtual std::string formatDeref(std::string); - virtual std::string formatRegister(std::string); - virtual std::string formatBinaryFunc(std::string, std::string, std::string); + std::string formatImmediate(const std::string&) const override; + std::string formatDeref(const std::string&) const override; + std::string formatRegister(const std::string&) const override; + std::string formatBinaryFunc(const std::string&, const std::string&, const std::string&) const override; private: std::map binaryFuncModifier; @@ -82,12 +83,13 @@ namespace Dyninst { public: AmdgpuFormatter(); - virtual std::string getInstructionString(std::vector ); - virtual std::string formatImmediate(std::string); - virtual std::string formatDeref(std::string); - virtual std::string formatRegister(std::string); - virtual std::string formatBinaryFunc(std::string, std::string, std::string); - + std::string formatImmediate(const std::string&) const override; + std::string formatDeref(const std::string&) const override; + std::string formatRegister(const std::string&) const override; + std::string formatBinaryFunc(const std::string&, const std::string&, const std::string&) const override; + // Helper function for formatting consecutive registers that are displayed as a single operand + // Called when architecture is passed to Instruction.format. + static std::string formatRegister(MachRegister m_Reg, uint32_t num_elements, unsigned m_Low , unsigned m_High ); private: std::map binaryFuncModifier; }; @@ -97,11 +99,12 @@ namespace Dyninst { public: x86Formatter(); - virtual std::string getInstructionString(std::vector ); - virtual std::string formatImmediate(std::string); - virtual std::string formatDeref(std::string); - virtual std::string formatRegister(std::string); - virtual std::string formatBinaryFunc(std::string, std::string, std::string); + std::string getInstructionString(const std::vector &) const override; + std::string formatImmediate(const std::string&) const override; + std::string formatDeref(const std::string&) const override; + std::string formatRegister(const std::string&) const override; + std::string formatBinaryFunc(const std::string&, const std::string&, const std::string&) const override; + bool operandPrintOrderReversed() const override; }; } diff --git a/instructionAPI/h/BinaryFunction.h b/instructionAPI/h/BinaryFunction.h index 9b15def92f..0b0d9598d3 100644 --- a/instructionAPI/h/BinaryFunction.h +++ b/instructionAPI/h/BinaryFunction.h @@ -35,12 +35,12 @@ #include "Register.h" #include "Result.h" #include "ArchSpecificFormatters.h" +#include +#include +#include +#include #include -#if defined(_MSC_VER) -#pragma warning(disable:4251) -#endif - namespace Dyninst { namespace InstructionAPI @@ -73,7 +73,7 @@ namespace Dyninst return m_name; } - typedef boost::shared_ptr Ptr; + typedef dyncompat::shared_ptr Ptr; private: std::string m_name; @@ -263,7 +263,7 @@ namespace Dyninst } Result one(u64, 1); - Result rot = arg1 & (Result(u64, (1< +#include +#include namespace Dyninst { diff --git a/instructionAPI/h/Expression.h b/instructionAPI/h/Expression.h index d69986ab24..f3f124bff8 100644 --- a/instructionAPI/h/Expression.h +++ b/instructionAPI/h/Expression.h @@ -35,6 +35,7 @@ #include "InstructionAST.h" #include "Result.h" +#include #include #include @@ -120,13 +121,13 @@ namespace Dyninst { public: /// \brief A type definition for a reference counted pointer to a %Expression. - typedef boost::shared_ptr Ptr; - friend class Operation_impl; + typedef dyncompat::shared_ptr Ptr; protected: Expression(Result_Type t); Expression(MachRegister r); public: virtual ~Expression(); + Expression(const Expression&) = default; /// \brief If the %Expression can be evaluated, returns a %Result containing its value. /// Otherwise returns an undefined %Result. diff --git a/instructionAPI/h/Immediate.h b/instructionAPI/h/Immediate.h index 6ad770035d..e1e59e6f7b 100644 --- a/instructionAPI/h/Immediate.h +++ b/instructionAPI/h/Immediate.h @@ -32,6 +32,8 @@ #define IMMEDIATE_H #include "Expression.h" +#include +#include #include namespace Dyninst @@ -72,6 +74,20 @@ namespace Dyninst virtual bool isStrictEqual(const InstructionAST& rhs) const; }; + class INSTRUCTION_EXPORT NamedImmediate : public Immediate + { + public: + NamedImmediate(std::string name, const Result &val); + + static NamedImmediate::Ptr makeNamedImmediate(std::string name, const Result &val); + virtual std::string format(Architecture, formatStyle) const; + virtual std::string format(formatStyle) const; + + private: + std::string name_; + }; + + class INSTRUCTION_EXPORT ArmConditionImmediate : public Immediate { public: diff --git a/instructionAPI/h/Instruction.h b/instructionAPI/h/Instruction.h index 2119eb3ca1..8a35b9226c 100644 --- a/instructionAPI/h/Instruction.h +++ b/instructionAPI/h/Instruction.h @@ -32,6 +32,9 @@ #define INSTRUCTION_H +#include +#include +#include #include #include #include @@ -91,7 +94,9 @@ namespace Dyninst friend class InstructionDecoder_x86; friend class InstructionDecoder_power; friend class InstructionDecoder_aarch64; - friend class InstructionDecoder_amdgpu_vega; + friend class InstructionDecoder_amdgpu_gfx908; + friend class InstructionDecoder_amdgpu_gfx90a; + friend class InstructionDecoder_amdgpu_gfx940; struct CFT { @@ -140,6 +145,9 @@ namespace Dyninst /// in the same order that they were decoded. INSTRUCTION_EXPORT void getOperands(std::vector& operands) const; + /// Returns a vector of non-implicit operands in printed order + INSTRUCTION_EXPORT std::vector getDisplayOrderedOperands() const; + /// The \c getOperand method returns the operand at position \c index, or /// an empty operand if \c index does not correspond to a valid operand in this /// instruction. @@ -292,19 +300,18 @@ namespace Dyninst } return memcmp(m_RawInsn.large_insn, rhs.m_RawInsn.large_insn, m_size) == 0; } + INSTRUCTION_EXPORT void updateMnemonic(std::string new_mnemonic) { + m_InsnOp.updateMnemonic(new_mnemonic); + } - typedef boost::shared_ptr Ptr; - public: - //Should be private, but we're working around some compilers mis-using the 'friend' declaration. - INSTRUCTION_EXPORT void appendOperand(Expression::Ptr e, bool isRead, bool isWritten) const; - INSTRUCTION_EXPORT void appendOperand(Expression::Ptr e, bool isRead, bool isWritten, bool isImplicit) const; - INSTRUCTION_EXPORT void appendOperand(Expression::Ptr e, bool isRead, bool isWritten, bool isImplicit, bool trueP, bool falseP) const; + typedef dyncompat::shared_ptr Ptr; private: void updateSize(const unsigned int new_size) {m_size = new_size;} void decodeOperands() const; - void addSuccessor(Expression::Ptr e, bool isCall, bool isIndirect, bool isConditional, bool isFallthrough) const; + void addSuccessor(Expression::Ptr e, bool isCall, bool isIndirect, bool isConditional, bool isFallthrough, bool isImplicit = false) const; + void appendOperand(Expression::Ptr e, bool isRead, bool isWritten, bool isImplicit = false, bool trueP = false, bool falseP = false) const; void copyRaw(size_t size, const unsigned char* raw); Expression::Ptr makeReturnExpression() const; mutable std::list m_Operands; @@ -315,7 +322,8 @@ namespace Dyninst Architecture arch_decoded_from; mutable std::list m_Successors; static int numInsnsAllocated; - ArchSpecificFormatter& formatter; + // formatter is a non-owning pointer to a singleton object + ArchSpecificFormatter* formatter; }; } } diff --git a/instructionAPI/h/InstructionAST.h b/instructionAPI/h/InstructionAST.h index 93a7b63b05..63212ebc75 100644 --- a/instructionAPI/h/InstructionAST.h +++ b/instructionAPI/h/InstructionAST.h @@ -31,20 +31,15 @@ #if !defined(INSTRUCTIONAST_H) #define INSTRUCTIONAST_H -#if defined(_MSC_VER) -// Exported class inheriting from non-exported class. This is by design; don't -// use the shared_from_this externally! -#pragma warning(push) -#pragma warning(disable:4251) -#endif #include "util.h" +#include #include #include #include #include "Result.h" #include "ArchSpecificFormatters.h" -#include "boost/enable_shared_from_this.hpp" +#include "dyncompat/enable_shared_from_this.hpp" namespace Dyninst { @@ -72,12 +67,13 @@ namespace Dyninst /// - They are of the same type /// - If leaf nodes, they represent the same immediate value or the same register /// - If non-leaf nodes, they represent the same operation and their corresponding children are equal - class INSTRUCTION_EXPORT InstructionAST : public boost::enable_shared_from_this + class INSTRUCTION_EXPORT InstructionAST : public dyncompat::enable_shared_from_this { public: - typedef boost::shared_ptr Ptr; + typedef dyncompat::shared_ptr Ptr; InstructionAST(); + InstructionAST(const InstructionAST&) = default; virtual ~InstructionAST(); /// Compare two AST nodes for equality. @@ -126,9 +122,6 @@ namespace Dyninst }; } } -#if defined(_MSC_VER) -#pragma warning(pop) -#endif #endif //!defined(INSTRUCTIONAST_H) diff --git a/instructionAPI/h/InstructionDecoder.h b/instructionAPI/h/InstructionDecoder.h index 7dc4b93bd4..7e901941dc 100644 --- a/instructionAPI/h/InstructionDecoder.h +++ b/instructionAPI/h/InstructionDecoder.h @@ -32,10 +32,7 @@ #define INSTRUCTION_DECODER_H #include "Instruction.h" - -#if defined(_MSC_VER) -#pragma warning(disable:4251) -#endif +#include namespace Dyninst { @@ -86,9 +83,20 @@ namespace Dyninst start(b), end(e) {} }; + // This interface allows registering a callback function to be invoked + // when the InstructionDecoder encounters a byte sequence it is not able + // to successfully convert into a known instruction + struct unknown_instruction { + using callback_t = Instruction(*)(buffer); + static void register_callback(callback_t); + static callback_t unregister_callback(); + unknown_instruction() = delete; + ~unknown_instruction() = delete; + }; + private: buffer m_buf; - boost::shared_ptr m_Impl; + dyncompat::shared_ptr m_Impl; }; } diff --git a/instructionAPI/h/Operand.h b/instructionAPI/h/Operand.h index 6752f51e1c..b680e4d7bc 100644 --- a/instructionAPI/h/Operand.h +++ b/instructionAPI/h/Operand.h @@ -59,46 +59,17 @@ namespace Dyninst class Operand { public: - typedef boost::shared_ptr Ptr; - Operand() : m_isRead(false), m_isWritten(false), m_isImplicit(false), m_isTruePredicate(false), m_isFalsePredicate(false) {} + typedef dyncompat::shared_ptr Ptr; /// \brief Create an operand from a %Expression and flags describing whether the %ValueComputation /// is read, written or both. /// \param val Reference-counted pointer to the %Expression that will be contained in the %Operand being constructed /// \param read True if this operand is read /// \param written True if this operand is written - Operand(Expression::Ptr val, bool read, bool written) : - op_value(val), m_isRead(read), m_isWritten(written), m_isImplicit(false), m_isTruePredicate(false), m_isFalsePredicate(false) {} - Operand(Expression::Ptr val, bool read, bool written, bool implicit) : - op_value(val), m_isRead(read), m_isWritten(written), m_isImplicit(implicit), m_isTruePredicate(false), m_isFalsePredicate(false) {} // An instruction can be true predicated, false predicated, or not predicated at all - Operand(Expression::Ptr val, bool read, bool written, bool implicit, - bool trueP, bool falseP): + explicit Operand(Expression::Ptr val = {}, bool read = false, bool written = false, bool implicit = false, + bool trueP = false, bool falseP = false) noexcept : op_value(val), m_isRead(read), m_isWritten(written), m_isImplicit(implicit), m_isTruePredicate(trueP), m_isFalsePredicate(falseP) {} - virtual ~Operand() - { - op_value.reset(); - } - - Operand(const Operand& o) noexcept : - op_value(o.op_value), m_isRead(o.m_isRead), - m_isWritten(o.m_isWritten), m_isImplicit(o.m_isImplicit), - m_isTruePredicate(o.m_isTruePredicate), m_isFalsePredicate(o.m_isFalsePredicate) - { - } - - const Operand& operator=(const Operand& rhs) - { - op_value = rhs.op_value; - m_isRead = rhs.m_isRead; - m_isWritten = rhs.m_isWritten; - m_isImplicit = rhs.m_isImplicit; - m_isTruePredicate = rhs.m_isTruePredicate; - m_isFalsePredicate = rhs.m_isFalsePredicate; - return *this; - } - - /// \brief Get the registers read by this operand /// \param regsRead Has the registers read inserted into it INSTRUCTION_EXPORT void getReadSet(std::set& regsRead) const; @@ -142,14 +113,14 @@ namespace Dyninst INSTRUCTION_EXPORT Expression::Ptr getValue() const; private: - Expression::Ptr op_value; - bool m_isRead; - bool m_isWritten; - bool m_isImplicit; + Expression::Ptr op_value{}; + bool m_isRead{}; + bool m_isWritten{}; + bool m_isImplicit{}; // Used for GPU instructions with predicates - bool m_isTruePredicate; - bool m_isFalsePredicate; + bool m_isTruePredicate{}; + bool m_isFalsePredicate{}; }; } } diff --git a/instructionAPI/h/Operation_impl.h b/instructionAPI/h/Operation_impl.h index 7cc6f20471..cdedc41a66 100644 --- a/instructionAPI/h/Operation_impl.h +++ b/instructionAPI/h/Operation_impl.h @@ -35,13 +35,15 @@ #include "Expression.h" #include "entryIDs.h" #include "Result.h" +#include +#include #include #include #include "util.h" -#include -#include -#include +#include +#include +#include // OpCode = operation + encoding // contents: @@ -94,23 +96,26 @@ namespace Dyninst /// %Operations are constructed by the %InstructionDecoder as part of the process /// of constructing an %Instruction. - class Operation_impl : public boost::lockable_adapter + class Operation : public dyncompat::lockable_adapter { public: typedef std::set registerSet; typedef std::set VCSet; friend class InstructionDecoder_power; // for editing mnemonics after creation friend class InstructionDecoder_aarch64; - friend class InstructionDecoder_amdgpu_vega; + friend class InstructionDecoder_amdgpu_gfx908; + friend class InstructionDecoder_amdgpu_gfx90a; + friend class InstructionDecoder_amdgpu_gfx940; + friend class Instruction; // to make use of the update size function public: - INSTRUCTION_EXPORT Operation_impl(NS_x86::ia32_entry* e, NS_x86::ia32_prefixes* p = NULL, ia32_locations* l = NULL, + INSTRUCTION_EXPORT Operation(NS_x86::ia32_entry* e, NS_x86::ia32_prefixes* p = NULL, ia32_locations* l = NULL, Architecture arch = Arch_none); - INSTRUCTION_EXPORT Operation_impl(const Operation_impl& o); - INSTRUCTION_EXPORT Operation_impl(); - INSTRUCTION_EXPORT Operation_impl(entryID id, std::string m, Architecture arch); - - INSTRUCTION_EXPORT const Operation_impl& operator=(const Operation_impl& o); + INSTRUCTION_EXPORT Operation(const Operation& o); + INSTRUCTION_EXPORT Operation(); + INSTRUCTION_EXPORT Operation(entryID id, std::string m, Architecture arch); + + INSTRUCTION_EXPORT const Operation& operator=(const Operation& o); /// Returns the set of registers implicitly read (i.e. those not included in the operands, but read anyway) INSTRUCTION_EXPORT const registerSet& implicitReads() ; @@ -134,20 +139,12 @@ namespace Dyninst INSTRUCTION_EXPORT const VCSet& getImplicitMemReads() ; /// Returns the set of memory locations implicitly written. INSTRUCTION_EXPORT const VCSet& getImplicitMemWrites() ; - friend std::size_t hash_value(Operation_impl const& op) - { - size_t seed = 0; - boost::hash_combine(seed, op.operationID); - boost::hash_combine(seed, op.prefixID); - boost::hash_combine(seed, op.archDecodedFrom); - boost::hash_combine(seed, op.addrWidth); - boost::hash_combine(seed, op.segPrefix); - boost::hash_combine(seed, op.isVectorInsn); - return seed; - } - bool operator==(const Operation_impl& rhs) const { - return hash_value(*this) == hash_value(rhs); + + void updateMnemonic(std::string new_mnemonic){ + mnemonic = new_mnemonic; } + + INSTRUCTION_EXPORT const VCSet& getImplicitMemWrites() const; bool isVectorInsn; @@ -170,13 +167,6 @@ namespace Dyninst }; - struct Operation: public Operation_impl { - Operation(entryID id, std::string m, Architecture arch) - : Operation_impl(id, m, arch) {} - Operation(NS_x86::ia32_entry* e, NS_x86::ia32_prefixes* p = NULL, ia32_locations* l = NULL, - Architecture arch = Arch_none) : Operation_impl(e, p, l, arch) {} - Operation() : Operation_impl() {} - }; } } diff --git a/instructionAPI/h/Register.h b/instructionAPI/h/Register.h index 4b2bc7806c..ee2f16c47b 100644 --- a/instructionAPI/h/Register.h +++ b/instructionAPI/h/Register.h @@ -32,11 +32,14 @@ #define REGISTER_H #include "Expression.h" +#include +#include #include #include #include -#include "dyn_regs.h" +#include "registers/MachRegister.h" +#include "Architecture.h" namespace Dyninst { @@ -52,14 +55,15 @@ namespace Dyninst { public: /// \brief A type definition for a reference-counted pointer to a %RegisterAST. - typedef boost::shared_ptr Ptr; + typedef dyncompat::shared_ptr Ptr; /// Construct a register, assigning it the ID \c id. - RegisterAST(MachRegister r); - RegisterAST(MachRegister r, unsigned int lowbit, unsigned int highbit); - RegisterAST(MachRegister r, unsigned int lowbit, unsigned int highbit, Result_Type regType); + RegisterAST(MachRegister r, uint32_t num_elements = 1 ); + RegisterAST(MachRegister r, unsigned int lowbit, unsigned int highbit, uint32_t num_elements = 1); + RegisterAST(MachRegister r, unsigned int lowbit, unsigned int highbit, Result_Type regType, uint32_t num_elements = 1); virtual ~RegisterAST(); + RegisterAST(const RegisterAST&) = default; /// By definition, a %RegisterAST object has no children. /// \param children Since a %RegisterAST has no children, the \c children parameter is unchanged by this method. @@ -113,6 +117,7 @@ namespace Dyninst MachRegister m_Reg; unsigned int m_Low; unsigned int m_High; + unsigned int m_num_elements; }; /** diff --git a/instructionAPI/h/RegisterIDs.h b/instructionAPI/h/RegisterIDs.h deleted file mode 100644 index e7ffea32dc..0000000000 --- a/instructionAPI/h/RegisterIDs.h +++ /dev/null @@ -1,130 +0,0 @@ -/* - * See the dyninst/COPYRIGHT file for copyright information. - * - * We provide the Paradyn Tools (below described as "Paradyn") - * on an AS IS basis, and do not warrant its validity or performance. - * We reserve the right to update, modify, or discontinue this - * software at any time. We shall have no obligation to supply such - * updates or modifications or any other form of support to you. - * - * By your use of Paradyn, you understand and agree that we (or any - * other person or entity with proprietary rights in Paradyn) are - * under no obligation to provide either maintenance services, - * update services, notices of latent defects, or correction of - * defects for Paradyn. - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#if !defined(REGISTER_IDS_X86_H) -#define REGISTER_IDS_X86_H - -#include -#include -#include "util.h" -#include "Result.h" -#include "dyntypes.h" -namespace Dyninst -{ - namespace InstructionAPI - { - /// \enum Dyninst::InstructionAPI::IA32Regs - /// \brief Registers for IA32 and AMD64 processors. - /// - // We REALLY REALLY NEED these definitions to stay aligned as given, - // so (e.g.) (r_EAX - r_AH) == (r_EDX - r_DH). We use that later - // for upconverting overlapping/aliased registers. - enum IA32Regs : unsigned int { r_AH=0, r_BH, r_CH, r_DH, - r_AL=10, r_BL, r_CL, r_DL, - r_AX=20, r_BX, r_CX, r_DX, r_SI, r_DI, - r_eAX=30, r_eBX, r_eCX, r_eDX, r_eSI, r_eDI, - r_EAX=40, r_EBX, r_ECX, r_EDX, r_ESI, r_EDI, - r_eSP=50, r_eBP, - r_ESP=60, r_EBP, - r_EDXEAX=70, r_ECXEBX, //133 - r_EFLAGS=100, - r_CS=110, r_DS, r_ES, r_FS, r_GS, r_SS, - r_EIP=120, - // flags need to be separate registers for proper liveness analysis - r_DummyFPR=130, r_Reserved, - // and we have a dummy register to make liveness consistent since floating point saves are all/none at present - r_rAX=140, r_rBX, r_rCX, r_rDX, r_rSI, r_rDI, - r_RAX=150, r_RBX, r_RCX, r_RDX, r_RSI, r_RDI, - r_rSP=160, r_rBP, - r_RSP=170, r_RBP, - r_R8=180, r_R9, r_R10, r_R11, r_R12, r_R13, r_R14, r_R15, - // AMD64 GPRs - r_RIP=190, - r_XMM0=200, r_XMM1, r_XMM2, r_XMM3, r_XMM4, r_XMM5, r_XMM6, r_XMM7, - r_MM0, r_MM1, r_MM2, r_MM3, r_MM4, r_MM5, r_MM6, r_MM7, - r_CR0, r_CR1, r_CR2, r_CR3, r_CR4, r_CR5, r_CR6, r_CR7, - r_DR0, r_DR1, r_DR2, r_DR3, r_DR4, r_DR5, r_DR6, r_DR7, - r_TR0, r_TR1, r_TR2, r_TR3, r_TR4, r_TR5, r_TR6, r_TR7, - r_SPL, r_BPL, r_SIL, r_DIL, - // FP Stack - r_ST0, r_ST1, r_ST2, r_ST3, r_ST4, r_ST5, r_ST6, r_ST7, - r_ALLGPRS, - r_OF=11, r_SF=7, r_ZF=6, r_AF=4, r_PF=2, r_CF=0, r_TF=8, r_IF=9, r_DF=10, r_NT=14, r_RF=16, - // NOTE: 11 of these! - - }; - - /// The %RegInfo struct associates a register ID with its size and name. - struct RegInfo - { - RegInfo(Result_Type t, std::string n) : - regSize(t), regName(n) - { - } - RegInfo() : - regSize(u8), regName("*** UNDEFINED REGISTER ***") - { - } - - Result_Type regSize; - std::string regName; - }; - } -} - - -namespace Dyninst -{ - namespace InstructionAPI - { - typedef dyn_hash_map RegTable; - /// \brief Register names for disassembly and debugging - struct IA32RegTable - { - IA32RegTable() {} - RegTable IA32_register_names; - Result_Type getSize(int id) - { - RegTable::const_iterator found = IA32_register_names.find((IA32Regs)(id)); - if(found != IA32_register_names.end()) { - return found->second.regSize; - } - // Sane default - return u32; - } - - }; - - } -} - - - -#endif //!defined(REGISTER_IDS_X86_H) diff --git a/instructionAPI/h/Result.h b/instructionAPI/h/Result.h index 772b0ca7d7..5ce2c36edb 100644 --- a/instructionAPI/h/Result.h +++ b/instructionAPI/h/Result.h @@ -31,576 +31,759 @@ #if !defined(RESULT_H) #define RESULT_H -#include #include // memcmp -#if !defined(_MSC_VER) -#include -#else - typedef __int64 int64_t; - typedef __int32 int32_t; - typedef __int16 int16_t; - typedef unsigned __int64 uint64_t; - typedef unsigned __int32 uint32_t; - typedef unsigned __int16 uint16_t; -#endif -#include +#include +#include #include - +#include "util.h" namespace Dyninst { - namespace InstructionAPI - { - union Result_Value - { - unsigned char bitval : 1; - unsigned char u8val; - char s8val; - uint16_t u16val; - int16_t s16val; - uint32_t u24val:24; - uint32_t u32val; - int32_t s32val; - uint64_t u64val; - int64_t s64val; - float floatval; - double dblval; - uint64_t u48val : 48; - int64_t s48val : 48; - void * m14val; - void * m96val; - void * dbl128val; - void * m192val; - void * m256val; - void * m384val; - void * m512val; - }; - enum Result_Type - { - bit_flag = 0, - s8, - u8, - s16, - u16, - u24, - s32, - u32, - s48, - u48, - s64, - u64, - sp_float, - dp_float, - // 48-bit pointers...yay Intel - m14, - m96, - dbl128, - m192, - m256, - m384, - m512, - invalid_type - }; - - template < Result_Type t > struct Result_type2type - { - typedef void* type; - }; - template < > struct Result_type2type - { - typedef char type; - }; - template < > struct Result_type2type - { - typedef unsigned char type; - }; - template < > struct Result_type2type - { - typedef int16_t type; - }; - template < > struct Result_type2type - { - typedef uint16_t type; - }; - template < > struct Result_type2type - { - typedef uint32_t type; - }; - template < > struct Result_type2type - { - typedef int32_t type; - }; - template < > struct Result_type2type - { - typedef uint32_t type; - }; - template < > struct Result_type2type - { - typedef int64_t type; - }; - template < > struct Result_type2type - { - typedef uint64_t type; - }; - template < > struct Result_type2type - { - typedef int64_t type; - }; - template < > struct Result_type2type - { - typedef uint64_t type; - }; - template < > struct Result_type2type - { - typedef float type; - }; - template < > struct Result_type2type - { - typedef double type; - }; - template < > struct Result_type2type - { - typedef unsigned char type; - }; - /// A %Result object represents a value computed by a %Expression AST. - /// - /// The %Result class is a tagged-union representation of the results that - /// %Expressions can produce. It includes 8, 16, 32, 48, and 64 bit integers - /// (signed and unsigned), bit values, and single and double precision floating point values. - /// For each of these types, the value of a %Result may be undefined, or it may be a value within - /// the range of the type. - /// - /// The \c type field is an enum that may contain any of the following values: - /// - \c u8: an unsigned 8-bit integer - /// - \c s8: a signed 8-bit integer - /// - \c u16: an unsigned 16-bit integer - /// - \c s16: a signed 16-bit integer - /// - \c u32: an unsigned 32-bit integer - /// - \c s32: a signed 32-bit integer - /// - \c u48: an unsigned 48-bit integer (IA32 pointers) - /// - \c s48: a signed 48-bit integer (IA32 pointers) - /// - \c u64: an unsigned 64-bit integer - /// - \c s64: a signed 64-bit integer - /// - \c sp_float: a single-precision float - /// - \c dp_float: a double-precision float - /// - \c bit_flag: a single bit (individual flags) - /// - \c m512: a 512-bit memory value - /// - \c dbl128: a 128-bit integer, which often contains packed floating point values - /// - \c m14: a 14 byte memory value - /// - // The %Instruction API's model of %Results is a simple one, and may seem overly aggressive about - // making an %Expression's %Result undefined. It follows the same basic rule as the rest of the API: - // a decoded %Instruction object represents only the information that may be obtained from the machine - // instruction that was decoded. As discussed in the Expression section, the \c setValue - // and \c eval interface allows you to determine the possible %Results of an %Expression when evaluated over various - // machine states. From this, you may construct abstractions to represent the set of possible results. - // Alternately, you may use instrumentation to determine the exact machine state at the time an - // instruction executes, which will allow you to evaluate the %Result of an %Expression in its actual context. - class INSTRUCTION_EXPORT Result + namespace InstructionAPI { - public: - Result_Value val; - Result_Type type; - bool defined; + union Result_Value + { + unsigned char bitval : 1; + unsigned char u8val; + /* char can be signed or unsigned, must be signed for s8val */ + signed char s8val; + uint16_t u16val; + int16_t s16val; + uint32_t u24val:24; + uint32_t u32val; + int32_t s32val; + uint64_t u48val : 48; + int64_t s48val : 48; + uint64_t u64val; + int64_t s64val; + float floatval; + double dblval; + void * dbl128val; + void * m14val; + void * m32val; + void * m64val; + void * m80val; + void * m96val; + void * m128val; + void * m160val; + void * m192val; + void * m224val; + void * m256val; + void * m288val; + void * m320val; + void * m352val; + void * m384val; + void * m416val; + void * m448val; + void * m480val; + void * m512val; + }; - Result() : - type(u32), defined(false) - { - val.u32val = 0; - } - Result(const Result& o) : - val(o.val), type(o.type), defined(o.defined) - { - } + // The order of these enumerations is important. + // See 'operator==' and arithmetic operators. + enum Result_Type + { + bit_flag = 0, + s8, + u8, + s16, + u16, + u24, + s32, + u32, + s48, + u48, + s64, + u64, + sp_float, + dp_float, + m14, // For historical reason m14 means 14 bytes. All other mX means X bits + dbl128, + m32, + m64, + m80, + m96, + m128, + m160, + m192, + m224, + m256, + m288, + m320, + m352, + m384, + m416, + m448, + m480, + m512, + invalid_type + }; - const Result& operator=(const Result& rhs) - { - val = rhs.val; - type = rhs.type; - defined = rhs.defined; - return *this; - } + template < Result_Type t > struct Result_type2type + { + typedef void* type; + }; + template < > struct Result_type2type + { + typedef signed char type; + }; + template < > struct Result_type2type + { + typedef unsigned char type; + }; + template < > struct Result_type2type + { + typedef int16_t type; + }; + template < > struct Result_type2type + { + typedef uint16_t type; + }; + template < > struct Result_type2type + { + typedef uint32_t type; + }; + template < > struct Result_type2type + { + typedef int32_t type; + }; + template < > struct Result_type2type + { + typedef uint32_t type; + }; + template < > struct Result_type2type + { + typedef int64_t type; + }; + template < > struct Result_type2type + { + typedef uint64_t type; + }; + template < > struct Result_type2type + { + typedef int64_t type; + }; + template < > struct Result_type2type + { + typedef uint64_t type; + }; + template < > struct Result_type2type + { + typedef float type; + }; + template < > struct Result_type2type + { + typedef double type; + }; + template < > struct Result_type2type + { + typedef unsigned char type; + }; - /// A %Result may be constructed from a type without providing a value. - /// This constructor creates a %Result of type \c t with undefined contents. - Result(Result_Type t) : - type(t), defined(false) - { - val.u32val = 0; - } + /// A %Result object represents a value computed by a %Expression AST. + /// + /// The %Result class is a tagged-union representation of the results that + /// %Expressions can produce. It includes 8, 16, 32, 48, and 64 bit integers + /// (signed and unsigned), bit values, and single and double precision floating point values. + /// For each of these types, the value of a %Result may be undefined, or it may be a value within + /// the range of the type. + /// + /// The \c type field is an enum that may contain any of the following values: + /// - \c bit_flag: a single bit (individual flags) + /// - \c u8: an unsigned 8-bit integer + /// - \c s8: a signed 8-bit integer + /// - \c u16: an unsigned 16-bit integer + /// - \c s16: a signed 16-bit integer + /// - \c u24: an unsigned 24-bit integer + /// - \c u32: an unsigned 32-bit integer + /// - \c s32: a signed 32-bit integer + /// - \c u48: an unsigned 48-bit integer + /// - \c s48: a signed 48-bit integer + /// - \c u64: an unsigned 64-bit integer + /// - \c s64: a signed 64-bit integer + /// - \c sp_float: a single-precision float + /// - \c dp_float: a double-precision float + /// - \c dbl128: a 128-bit integer, which often contains packed floating point values + /// - \c m14: a 14 byte memory value + /// - \c m32: a 32-bit memory value + /// - \c m64: a 64-bit memory value + /// - \c m80: an 80-bit memory value + /// - \c m96: a 96-bit memory value + /// - \c m128: a 128-bit memory value + /// - \c m160: a 160-bit memory value + /// - \c m192: a 192-bit memory value + /// - \c m224: a 224-bit memory value + /// - \c m256: a 256-bit memory value + /// - \c m288: a 288-bit memory value + /// - \c m320: a 320-bit memory value + /// - \c m352: a 352-bit memory value + /// - \c m384: a 384-bit memory value + /// - \c m416: a 416-bit memory value + /// - \c m448: a 448-bit memory value + /// - \c m480: a 480-bit memory value + /// - \c m512: a 512-bit memory value - /// A %Result may be constructed from a type and any value convertible to the type that the - /// tag represents. - /// This constructor creates a %Result of type \c t and contents \c v for any \c v that is implicitly - /// convertible to type \c t. Attempting to construct a %Result with a value that is incompatible with - /// its type will result in a compile-time error. - template - Result(Result_Type t, T v) : - type(t), defined(true) - { - switch(type) - { - case u8: - val.u8val = (unsigned char)(v); - break; - case s8: - val.s8val = (char)(v); - break; - case u16: - val.u16val = (uint16_t)(v); - break; - case s16: - val.s16val = (int16_t)(v); - break; - case u24: - val.u24val = (uint32_t)(v & 0xFFFFFF); - break; - case u32: - val.u32val = (uint32_t)(v ); - break; - case s32: - val.s32val = (int32_t)(v); - break; - case u64: - val.u64val = (uint64_t)(v); - break; - case s64: - val.s64val = (int64_t)(v); - break; - case bit_flag: - val.bitval = (v != 0) ? 1 : 0; - break; - case u48: - val.u48val = (uint64_t)(v & 0x0000FFFFFFFFFFFFLL); - break; - case s48: - val.s48val = (int64_t)(v & 0x0000FFFFFFFFFFFFLL); - break; - case m512: - val.m512val = (void *)(intptr_t) v; - break; - case dbl128: - val.dbl128val = (void*)(intptr_t) v; - break; - case m14: - val.m14val = (void*)(intptr_t) v; - break; - case m96: - val.m96val = (void *)(intptr_t) v; - break; - case m192: - val.m192val = (void *)(intptr_t) v; - break; - case m256: - val.m256val = (void *)(intptr_t) v; - break; - case m384: - val.m384val = (void *)(intptr_t) v; - break; - // Floats should be constructed with float types - default: - case sp_float: - case dp_float: - assert(!"Invalid type!"); - break; - } - } - Result(Result_Type t, float v) : - type(t), defined(true) - { - assert(t == sp_float || t == dp_float); - val.dblval = v; - } - Result(Result_Type t, double v) : - type(t), defined(true) - { - assert(t == sp_float || t == dp_float); - val.dblval = v; - } - ~Result() - { - } + // The %Instruction API's model of %Results is a simple one, and may seem overly aggressive about + // making an %Expression's %Result undefined. It follows the same basic rule as the rest of the API: + // a decoded %Instruction object represents only the information that may be obtained from the machine + // instruction that was decoded. As discussed in the Expression section, the \c setValue + // and \c eval interface allows you to determine the possible %Results of an %Expression when evaluated over various + // machine states. From this, you may construct abstractions to represent the set of possible results. + // Alternately, you may use instrumentation to determine the exact machine state at the time an + // instruction executes, which will allow you to evaluate the %Result of an %Expression in its actual context. + class INSTRUCTION_EXPORT Result + { + public: + Result_Value val; + Result_Type type; + bool defined; - bool operator<(const Result& o) const - { - if(type < o.type) return true; - if(!defined) return false; - if(!o.defined) return true; + Result() : + type(u32), defined(false) + { + val.u32val = 0; + } + Result(const Result& o) : + val(o.val), type(o.type), defined(o.defined) + { + } + const Result& operator=(const Result& rhs) + { + val = rhs.val; + type = rhs.type; + defined = rhs.defined; + return *this; + } - switch(type) - { - case u8: - return val.u8val < o.val.u8val; - break; - case s8: - return val.s8val < o.val.s8val; - break; - case u16: - return val.u16val < o.val.u16val; - break; - case s16: - return val.s16val < o.val.s16val; - break; - case u24: - return val.u24val < o.val.u24val; - break; - case u32: - return val.u32val < o.val.u32val; - break; - case s32: - return val.s32val < o.val.s32val; - break; - case u64: - return val.u64val < o.val.u64val; - break; - case s64: - return val.s64val < o.val.s64val; - break; - case sp_float: - return val.floatval < o.val.floatval; - break; - case dp_float: - return val.dblval < o.val.dblval; - break; - case bit_flag: - return val.bitval < o.val.bitval; - break; - case u48: - return val.u48val < o.val.u48val; - break; - case s48: - return val.s48val < o.val.s48val; - break; - case m512: - return memcmp(val.m512val, o.val.m512val, 512) < 0; - break; - case dbl128: - return memcmp(val.dbl128val, o.val.dbl128val, 128 / 8) < 0; - break; - case m14: - return memcmp(val.m14val, o.val.m14val, 14) < 0; - break; - case m96: - return memcmp(val.m96val, o.val.m96val, 96) < 0; - break; - case m192: - return memcmp(val.m192val, o.val.m192val, 192) < 0; - break; - case m256: - return memcmp(val.m256val, o.val.m256val, 256) < 0; - break; - case m384: - return memcmp(val.m384val, o.val.m384val, 384) < 0; - break; - default: - assert(!"Invalid type!"); - break; - } - return false; - } + /// A %Result may be constructed from a type without providing a value. + /// This constructor creates a %Result of type \c t with undefined contents. + Result(Result_Type t) : + type(t), defined(false) + { + val.u32val = 0; + } - /// Two %Results are equal if any of the following hold: - /// - Both %Results are of the same type and undefined - /// - Both %Results are of the same type, defined, and have the same value - /// - /// Otherwise, they are unequal (due to having different types, an undefined %Result compared to a defined %Result, - /// or different values). + /// A %Result may be constructed from a type and any value convertible to the type that the + /// tag represents. + /// This constructor creates a %Result of type \c t and contents \c v for any \c v that is implicitly + /// convertible to type \c t. Attempting to construct a %Result with a value that is incompatible with + /// its type will result in a compile-time error. + template + Result(Result_Type t, T v) : + type(t), defined(true) + { + switch(type) + { + case bit_flag: + val.bitval = (v != 0) ? 1 : 0; + break; + case u8: + val.u8val = (unsigned char)(v); + break; + case s8: + val.s8val = (signed char)(v); + break; + case u16: + val.u16val = (uint16_t)(v); + break; + case s16: + val.s16val = (int16_t)(v); + break; + case u24: + val.u24val = (uint32_t)(v & 0xFFFFFF); + break; + case u32: + val.u32val = (uint32_t)(v ); + break; + case s32: + val.s32val = (int32_t)(v); + break; + case u48: + val.u48val = (uint64_t)(v & 0x0000FFFFFFFFFFFFLL); + break; + case s48: + val.s48val = (int64_t)(v & 0x0000FFFFFFFFFFFFLL); + break; + case u64: + val.u64val = (uint64_t)(v); + break; + case s64: + val.s64val = (int64_t)(v); + break; + case dbl128: + val.dbl128val = (void*)(intptr_t) v; + break; + case m14: + val.m14val = (void*)(intptr_t) v; + break; + case m32: + val.m32val = (void *)(intptr_t) v; + break; + case m64: + val.m64val = (void *)(intptr_t) v; + break; + case m80: + val.m80val = (void *)(intptr_t) v; + break; + case m96: + val.m96val = (void *)(intptr_t) v; + break; + case m128: + val.m128val = (void *)(intptr_t) v; + break; + case m160: + val.m160val = (void *)(intptr_t) v; + break; + case m192: + val.m192val = (void *)(intptr_t) v; + break; + case m224: + val.m224val = (void *)(intptr_t) v; + break; + case m256: + val.m256val = (void *)(intptr_t) v; + break; + case m288: + val.m288val = (void *)(intptr_t) v; + break; + case m320: + val.m320val = (void *)(intptr_t) v; + break; + case m352: + val.m352val = (void *)(intptr_t) v; + break; + case m384: + val.m384val = (void *)(intptr_t) v; + break; + case m416: + val.m416val = (void *)(intptr_t) v; + break; + case m448: + val.m448val = (void *)(intptr_t) v; + break; + case m480: + val.m480val = (void *)(intptr_t) v; + break; + case m512: + val.m512val = (void *)(intptr_t) v; + break; + default: + // Floats should be constructed with float types + case sp_float: + case dp_float: + assert(!"Invalid type!"); + break; + } + } + Result(Result_Type t, float v) : + type(t), defined(true) + { + assert(t == sp_float || t == dp_float); + val.dblval = (double)v; + } + Result(Result_Type t, double v) : + type(t), defined(true) + { + assert(t == sp_float || t == dp_float); + val.dblval = v; + } + ~Result() + { + } + bool operator<(const Result& o) const + { + if(type < o.type) return true; + if(!defined) return false; + if(!o.defined) return true; - bool operator==(const Result& o) const - { - return !((*this < o) || (o < *this)); + switch(type) + { + case bit_flag: + return val.bitval < o.val.bitval; + break; + case u8: + return val.u8val < o.val.u8val; + break; + case s8: + return val.s8val < o.val.s8val; + break; + case u16: + return val.u16val < o.val.u16val; + break; + case s16: + return val.s16val < o.val.s16val; + break; + case u24: + return val.u24val < o.val.u24val; + break; + case u32: + return val.u32val < o.val.u32val; + break; + case s32: + return val.s32val < o.val.s32val; + break; + case u48: + return val.u48val < o.val.u48val; + break; + case s48: + return val.s48val < o.val.s48val; + break; + case u64: + return val.u64val < o.val.u64val; + break; + case s64: + return val.s64val < o.val.s64val; + break; + case sp_float: + return val.floatval < o.val.floatval; + break; + case dp_float: + return val.dblval < o.val.dblval; + break; + case dbl128: + return memcmp(val.dbl128val, o.val.dbl128val, 16) < 0; + break; + case m14: + return memcmp(val.m14val, o.val.m14val, 14) < 0; + break; + case m32: + return memcmp(val.m32val, o.val.m32val, 4) < 0; + break; + case m64: + return memcmp(val.m64val, o.val.m64val, 8) < 0; + break; + case m80: + return memcmp(val.m80val, o.val.m80val, 10) < 0; + break; + case m96: + return memcmp(val.m96val, o.val.m96val, 12) < 0; + break; + case m128: + return memcmp(val.m128val, o.val.m128val, 16) < 0; + break; + case m160: + return memcmp(val.m160val, o.val.m160val, 20) < 0; + break; + case m192: + return memcmp(val.m192val, o.val.m192val, 24) < 0; + break; + case m224: + return memcmp(val.m224val, o.val.m224val, 28) < 0; + break; + case m256: + return memcmp(val.m256val, o.val.m256val, 32) < 0; + break; + case m288: + return memcmp(val.m288val, o.val.m288val, 36) < 0; + break; + case m320: + return memcmp(val.m320val, o.val.m320val, 40) < 0; + break; + case m352: + return memcmp(val.m352val, o.val.m352val, 44) < 0; + break; + case m384: + return memcmp(val.m384val, o.val.m384val, 48) < 0; + break; + case m416: + return memcmp(val.m416val, o.val.m416val, 52) < 0; + break; + case m448: + return memcmp(val.m448val, o.val.m448val, 56) < 0; + break; + case m480: + return memcmp(val.m480val, o.val.m480val, 60) < 0; + break; + case m512: + return memcmp(val.m512val, o.val.m512val, 64) < 0; + break; + default: + assert(!"Invalid type!"); + break; + } + return false; + } + /// Two %Results are equal if any of the following hold: + /// - Both %Results are of the same type and undefined + /// - Both %Results are of the same type, defined, and have the same value + /// + /// Otherwise, they are unequal (due to having different types, an undefined %Result compared to a defined %Result, + /// or different values). + bool operator==(const Result& o) const + { + return !((*this < o) || (o < *this)); + } - } - /// %Results are formatted as strings containing their contents, represented as hexadecimal. - /// The type of the %Result is not included in the output. - std::string format() const - { - if(!defined) - { - return "[empty]"; - } - else - { - char hex[20]; - switch(type) - { - case u8: - snprintf(hex, 20, "%x", val.u8val); - break; - case s8: - snprintf(hex, 20, "%x", (unsigned int)val.s8val); - break; - case u16: - snprintf(hex, 20, "%x", val.u16val); - break; - case s16: - snprintf(hex, 20, "%x", (unsigned int)val.s16val); - break; - case u24: - snprintf(hex, 20, "%x", (unsigned int)val.u24val); - break; - case u32: - snprintf(hex, 20, "%x", val.u32val); - break; - case s32: - snprintf(hex, 20, "%x", (unsigned int)val.s32val); - break; - case u64: - return std::to_string(val.u64val); - case s64: - return std::to_string(val.s64val); - break; - case sp_float: - snprintf(hex, 20, "%f", (double)val.floatval); - break; - case dp_float: - snprintf(hex, 20, "%lf", val.dblval); - break; - case bit_flag: - snprintf(hex, 20, "%x", (unsigned int)val.bitval); - break; - case u48: - return std::to_string(val.s48val); - break; - case s48: - return std::to_string(val.s48val); - break; - case m512: - snprintf(hex, 20, "%p", val.m512val); - break; - case m14: - snprintf(hex, 20, "%p", val.m14val); - break; - case m96: - snprintf(hex, 20, "%p", val.m96val); - break; - case dbl128: - snprintf(hex, 20, "%p", val.dbl128val); - break; - case m192: - snprintf(hex, 20, "%p", val.m192val); - break; - case m256: - snprintf(hex, 20, "%p", val.m256val); - break; - case m384: - snprintf(hex, 20, "%p", val.m384val); - break; - default: - snprintf(hex, 20, "[invalid type]"); - break; - }; - return std::string(hex); - } - } + /// %Results are formatted as strings containing their contents, represented as hexadecimal. + /// The type of the %Result is not included in the output. + std::string format() const + { + if(!defined) + { + return "[empty]"; + } + else + { + char hex[20]; + switch(type) + { + case bit_flag: + snprintf(hex, 20, "%x", (unsigned int)val.bitval); + break; + case u8: + snprintf(hex, 20, "%x", val.u8val); + break; + case s8: + snprintf(hex, 20, "%x", (unsigned int)val.s8val); + break; + case u16: + snprintf(hex, 20, "%x", val.u16val); + break; + case s16: + snprintf(hex, 20, "%x", (unsigned int)val.s16val); + break; + case u24: + snprintf(hex, 20, "%x", (unsigned int)val.u24val); + break; + case u32: + snprintf(hex, 20, "%x", val.u32val); + break; + case s32: + snprintf(hex, 20, "%x", (unsigned int)val.s32val); + break; + case u48: + snprintf(hex, 20, "%lx", val.u48val); + break; + case s48: + snprintf(hex, 20, "%lx", (uint64_t ) val.s48val); + break; + case u64: + snprintf(hex, 20, "%lx", val.u64val); + break; + case s64: + snprintf(hex, 20, "%lx", (uint64_t) val.s64val); + break; + case sp_float: + snprintf(hex, 20, "%f", (double)val.floatval); + break; + case dp_float: + snprintf(hex, 20, "%lf", val.dblval); + break; + case dbl128: + snprintf(hex, 20, "%p", val.dbl128val); + break; + case m14: + snprintf(hex, 20, "%p", val.m14val); + break; + case m32: + snprintf(hex, 20, "%p", val.m32val); + break; + case m64: + snprintf(hex, 20, "%p", val.m64val); + break; + case m80: + snprintf(hex, 20, "%p", val.m80val); + break; + case m96: + snprintf(hex, 20, "%p", val.m96val); + break; + case m128: + snprintf(hex, 20, "%p", val.m128val); + break; + case m160: + snprintf(hex, 20, "%p", val.m160val); + break; + case m192: + snprintf(hex, 20, "%p", val.m192val); + break; + case m224: + snprintf(hex, 20, "%p", val.m224val); + break; + case m256: + snprintf(hex, 20, "%p", val.m256val); + break; + case m288: + snprintf(hex, 20, "%p", val.m288val); + break; + case m320: + snprintf(hex, 20, "%p", val.m320val); + break; + case m352: + snprintf(hex, 20, "%p", val.m352val); + break; + case m384: + snprintf(hex, 20, "%p", val.m384val); + break; + case m416: + snprintf(hex, 20, "%p", val.m416val); + break; + case m448: + snprintf(hex, 20, "%p", val.m448val); + break; + case m480: + snprintf(hex, 20, "%p", val.m480val); + break; + case m512: + snprintf(hex, 20, "%p", val.m512val); + break; + default: + snprintf(hex, 20, "[invalid type]"); + break; + }; + return hex; + } + } - template< typename to_type > - to_type convert() const - { - switch(type) - { - case s8: - return to_type(val.s8val); - case u8: - return to_type(val.u8val); - case s16: - return to_type(val.s16val); - case u16: - return to_type(val.u16val); - case u24: - return to_type(val.u24val); - case s32: - return to_type(val.s32val); - case u32: - return to_type(val.u32val); - case s48: - return to_type(val.s48val); - case u48: - return to_type(val.u48val); - case s64: - return to_type(val.s64val); - case u64: - return to_type(val.u64val); - case sp_float: - return to_type(val.floatval); - case dp_float: - return to_type(val.dblval); - case bit_flag: - return to_type(val.bitval); - case m512: - case dbl128: - case m192: - case m256: - case m384: - case m96: - assert(!"M512 and DBL128 types cannot be converted yet"); - return to_type(0); - default: - assert(!"Invalid type in result!"); - return to_type(0); - } - } + template< typename to_type > + to_type convert() const + { + switch(type) + { + case s8: + return to_type(val.s8val); + case u8: + return to_type(val.u8val); + case s16: + return to_type(val.s16val); + case u16: + return to_type(val.u16val); + case u24: + return to_type(val.u24val); + case s32: + return to_type(val.s32val); + case u32: + return to_type(val.u32val); + case s48: + return to_type(val.s48val); + case u48: + return to_type(val.u48val); + case s64: + return to_type(val.s64val); + case u64: + return to_type(val.u64val); + case sp_float: + return to_type(val.floatval); + case dp_float: + return to_type(val.dblval); + case bit_flag: + return to_type(val.bitval); + case dbl128: + case m14: + case m32: + case m64: + case m80: + case m96: + case m128: + case m160: + case m192: + case m224: + case m256: + case m288: + case m320: + case m352: + case m384: + case m416: + case m448: + case m480: + case m512: + assert(!"Memory types cannot be converted yet"); + return to_type(0); + default: + assert(!"Invalid type in result!"); + return to_type(0); + } + } - /// Returns the size of the contained type, in bytes - int size() const - { - switch(type) - { - case u8: - case s8: - return 1; - case u16: - case s16: - return 2; - case u24: - return 3; - case u32: - case s32: - return 4; - case u64: - case s64: - return 8; - case u48: - case s48: - return 6; - case sp_float: - return sizeof(float); - case dp_float: - return sizeof(double); - case bit_flag: - return 1; - case m512: - return 64; - case dbl128: - return 16; - case m192: - return 24; - case m256: - return 32; - default: - // In probabilistic gap parsing, - // we could start to decode at any byte and reach here. - // It is a sign for junk bytes - return 0; - }; - } - }; + /// Returns the size of the contained type, in bytes + int size() const + { + switch(type) + { + case bit_flag: + return 1; + case u8: + case s8: + return 1; + case u16: + case s16: + return 2; + case u24: + return 3; + case u32: + case s32: + return 4; + case u48: + case s48: + return 6; + case u64: + case s64: + return 8; + case sp_float: + return sizeof(float); + case dp_float: + return sizeof(double); + case dbl128: + return 16; + case m14: + return 14; + case m32: + return 4; + case m64: + return 8; + case m80: + return 10; + case m96: + return 12; + case m128: + return 16; + case m160: + return 20; + case m192: + return 24; + case m224: + return 28; + case m256: + return 32; + case m288: + return 36; + case m320: + return 40; + case m352: + return 44; + case m384: + return 48; + case m416: + return 52; + case m448: + return 56; + case m480: + return 60; + case m512: + return 64; + default: + // In probabilistic gap parsing, + // we could start to decode at any byte and reach here. + // It is a sign for junk bytes + return 0; + }; + } + }; - INSTRUCTION_EXPORT Result operator+(const Result& arg1, const Result& arg2); - INSTRUCTION_EXPORT Result operator*(const Result& arg1, const Result& arg2); - INSTRUCTION_EXPORT Result operator<<(const Result& arg1, const Result& arg2); - INSTRUCTION_EXPORT Result operator>>(const Result& arg1, const Result& arg2); - INSTRUCTION_EXPORT Result operator&(const Result& arg1, const Result& arg2); - INSTRUCTION_EXPORT Result operator|(const Result& arg1, const Result& arg2); + INSTRUCTION_EXPORT Result operator+(const Result& arg1, const Result& arg2); + INSTRUCTION_EXPORT Result operator*(const Result& arg1, const Result& arg2); + INSTRUCTION_EXPORT Result operator<<(const Result& arg1, const Result& arg2); + INSTRUCTION_EXPORT Result operator>>(const Result& arg1, const Result& arg2); + INSTRUCTION_EXPORT Result operator&(const Result& arg1, const Result& arg2); + INSTRUCTION_EXPORT Result operator|(const Result& arg1, const Result& arg2); - } + } } diff --git a/instructionAPI/h/Ternary.h b/instructionAPI/h/Ternary.h index cbaf63dcf3..94fb5151cf 100644 --- a/instructionAPI/h/Ternary.h +++ b/instructionAPI/h/Ternary.h @@ -32,11 +32,12 @@ #define TERNARY_H #include "Expression.h" +#include #include #include #include -#include "dyn_regs.h" +#include "Architecture.h" namespace Dyninst { @@ -52,7 +53,7 @@ namespace Dyninst { public: /// \brief A type definition for a reference-counted pointer to a %TernaryAST. - typedef boost::shared_ptr Ptr; + typedef dyncompat::shared_ptr Ptr; /// Construct a register, assigning it the ID \c id. TernaryAST(Expression::Ptr cond , Expression::Ptr first , Expression::Ptr second, Result_Type result_type); @@ -90,7 +91,7 @@ namespace Dyninst Expression::Ptr cond; Expression::Ptr first; Expression::Ptr second; - Result_Type result_type; + Result_Type result_type{}; protected: virtual bool isStrictEqual(const InstructionAST& rhs) const; diff --git a/instructionAPI/h/Visitor.h b/instructionAPI/h/Visitor.h index 4e5e5f7963..714e6376f3 100644 --- a/instructionAPI/h/Visitor.h +++ b/instructionAPI/h/Visitor.h @@ -52,8 +52,8 @@ namespace InstructionAPI /// should not be invoked by user code ordinarily. public: - Visitor() {} - virtual ~Visitor() {} + virtual ~Visitor() = default; + Visitor& operator=(const Visitor&) = default; virtual void visit(BinaryFunction* b) = 0; virtual void visit(Immediate* i) = 0; virtual void visit(RegisterAST* r) = 0; diff --git a/common/src/std_namesp.h b/instructionAPI/h/interrupts.h similarity index 82% rename from common/src/std_namesp.h rename to instructionAPI/h/interrupts.h index 77e78456b6..98378daad4 100644 --- a/common/src/std_namesp.h +++ b/instructionAPI/h/interrupts.h @@ -1,46 +1,44 @@ /* * See the dyninst/COPYRIGHT file for copyright information. - * + * * We provide the Paradyn Tools (below described as "Paradyn") * on an AS IS basis, and do not warrant its validity or performance. * We reserve the right to update, modify, or discontinue this * software at any time. We shall have no obligation to supply such * updates or modifications or any other form of support to you. - * + * * By your use of Paradyn, you understand and agree that we (or any * other person or entity with proprietary rights in Paradyn) are * under no obligation to provide either maintenance services, * update services, notices of latent defects, or correction of * defects for Paradyn. - * + * * This library is free software; you can redistribute it and/or * modify it under the terms of the GNU Lesser General Public * License as published by the Free Software Foundation; either * version 2.1 of the License, or (at your option) any later version. - * + * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU * Lesser General Public License for more details. - * + * * You should have received a copy of the GNU Lesser General Public * License along with this library; if not, write to the Free Software * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ -// $Id: namesp.h,v +#ifndef INSTRUCTIONAPI_INTERRUPTS_H +#define INSTRUCTIONAPI_INTERRUPTS_H -#ifndef __STD_NAMESP__ -#define __STD_NAMESP__ +#include "Instruction.h" +#include "util.h" -#include +namespace Dyninst { namespace InstructionAPI { -// Let's try to keep the symbols that are pulled into the global namespace -// to those that are ubiquitous. -using std::ostream; -using std::cout; -using std::cerr; -using std::endl; +// Checks if instruction is a software interrupt +bool INSTRUCTION_EXPORT isSoftwareInterrupt(Instruction const& ins); -#endif +}} +#endif diff --git a/common/src/Singleton.h b/instructionAPI/h/syscalls.h similarity index 75% rename from common/src/Singleton.h rename to instructionAPI/h/syscalls.h index 03889ac68e..4c1753f5fe 100644 --- a/common/src/Singleton.h +++ b/instructionAPI/h/syscalls.h @@ -1,49 +1,49 @@ /* * See the dyninst/COPYRIGHT file for copyright information. - * + * * We provide the Paradyn Tools (below described as "Paradyn") * on an AS IS basis, and do not warrant its validity or performance. * We reserve the right to update, modify, or discontinue this * software at any time. We shall have no obligation to supply such * updates or modifications or any other form of support to you. - * + * * By your use of Paradyn, you understand and agree that we (or any * other person or entity with proprietary rights in Paradyn) are * under no obligation to provide either maintenance services, * update services, notices of latent defects, or correction of * defects for Paradyn. - * + * * This library is free software; you can redistribute it and/or * modify it under the terms of the GNU Lesser General Public * License as published by the Free Software Foundation; either * version 2.1 of the License, or (at your option) any later version. - * + * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU * Lesser General Public License for more details. - * + * * You should have received a copy of the GNU Lesser General Public * License along with this library; if not, write to the Free Software * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ -#if !defined(SINGLETON_H) -#define SINGLETON_H +#ifndef INSTRUCTIONAPI_SYSCALLS_H +#define INSTRUCTIONAPI_SYSCALLS_H -#if !defined(__cplusplus) -#error "Singleton class is C++-only" -#endif //!defined(__cplusplus) +#include "Instruction.h" +#include "util.h" -template < class T > -class Singleton -{ -public: - static T& getInstance() - { - static T theInstance; - return theInstance; - } -}; +namespace Dyninst { namespace InstructionAPI { -#endif //!defined(SINGLETON_H) + /* Checks if instruction is a system call + * + * System calls can be implemented by the hardware as instructions + * as well as by idioms. This checks for both for all supported + * platforms. + */ +bool INSTRUCTION_EXPORT isSystemCall(Instruction const& ins); + +}} + +#endif diff --git a/instructionAPI/src/AMDGPU/gfx908/InstructionDecoder-amdgpu-gfx908.C b/instructionAPI/src/AMDGPU/gfx908/InstructionDecoder-amdgpu-gfx908.C new file mode 100644 index 0000000000..8154234990 --- /dev/null +++ b/instructionAPI/src/AMDGPU/gfx908/InstructionDecoder-amdgpu-gfx908.C @@ -0,0 +1,247 @@ +/* + * See the dyninst/COPYRIGHT file for copyright information. + * + * We provide the Paradyn Tools (below described as "Paradyn") + * on an AS IS basis, and do not warrant its validity or performance. + * We reserve the right to update, modify, or discontinue this + * software at any time. We shall have no obligation to supply such + * updates or modifications or any other form of support to you. + * + * By your use of Paradyn, you understand and agree that we (or any + * other person or entity with proprietary rights in Paradyn) are + * under no obligation to provide either maintenance services, + * update services, notices of latent defects, or correction of + * defects for Paradyn. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "Ternary.h" +#include "InstructionDecoder-amdgpu-gfx908.h" +#include +#include "registers/AMDGPU/amdgpu_gfx908_regs.h" + +namespace Dyninst { + namespace InstructionAPI { + typedef void (InstructionDecoder_amdgpu_gfx908::*operandFactory)(); + + typedef amdgpu_gfx908_insn_entry amdgpu_gfx908_insn_table[]; + + const std::array InstructionDecoder_amdgpu_gfx908::condNames = { { + "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", "hi", "ls", "ge", + "lt", "gt", "le", "al", "nv", + } }; + + const char* InstructionDecoder_amdgpu_gfx908::bitfieldInsnAliasMap(entryID) { + assert(!"no alias for entryID"); + return nullptr; + } + const char* InstructionDecoder_amdgpu_gfx908::condInsnAliasMap(entryID) { + assert(!"no alias for entryID"); + return nullptr; + } + + + using namespace std; + + Result_Type InstructionDecoder_amdgpu_gfx908::makeSizeType(unsigned int) { + assert(0); //not implemented + return u32; + } + + // **************** + // decoding opcodes + // **************** + + MachRegister InstructionDecoder_amdgpu_gfx908::makeAmdgpuRegID(MachRegister base, unsigned int encoding , unsigned int) { + return MachRegister(base.val() + encoding); + + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx908::makePCExpr() { + MachRegister baseReg = amdgpu_gfx908::pc_all; + return makeRegisterExpression(baseReg); + } + + void InstructionDecoder_amdgpu_gfx908::makeBranchTarget(bool branchIsCall, bool bIsConditional, int immVal, + int immLen_ ) { + Expression::Ptr lhs = makeAddExpression(makePCExpr(),Immediate::makeImmediate(Result(s48,4)),s48); + // immVal * 4 => 2 more bits + int64_t offset = sign_extend64(immLen_+2, immVal * 4); + + Expression::Ptr rhs = Immediate::makeImmediate(Result(s64, offset)); + + insn_in_progress->addSuccessor(makeAddExpression(lhs, rhs, s64), branchIsCall, false, bIsConditional, + false); + if (bIsConditional || branchIsCall) { + insn_in_progress->addSuccessor(makeFallThroughExpr(), false, false, false, true); + } + + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx908::makeFallThroughExpr() { + // TODO: while s_call_B64 is always 4 bytes, it is not clear whether all instructions that has a fall through branch are 4 bytes long + return makeAddExpression(makePCExpr(), Immediate::makeImmediate(Result(u64, unsign_extend64(3, 4))), u64); + } + + + bool InstructionDecoder_amdgpu_gfx908::decodeOperands(const Instruction *) { + assert(0 && "decodeOperands deprecated for amdgpu"); + return true; + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeSGPRorM0(unsigned int offset){ + if( offset <= 104) + return makeRegisterExpression(makeAmdgpuRegID(amdgpu_gfx908::s0,offset)); + if (offset == 124) + return makeRegisterExpression(amdgpu_gfx908::m0); + cerr << " unknown offset in sgpr or m0 " << offset << endl; + assert(0 && "shouldn't reach here"); + return {}; + } + + void InstructionDecoder_amdgpu_gfx908::processOPR_SMEM_OFFSET(layout_ENC_SMEM & layout){ + if (layout.IMM ==0 ){ + if( layout.SOFFSET_EN ==0 ) { + insn_in_progress-> appendOperand( decodeSGPRorM0(layout.OFFSET), true , false ); + }else{ + insn_in_progress-> appendOperand( decodeSGPRorM0(layout.SOFFSET), true , false ); + } + }else{ + if( layout.SOFFSET_EN ==0 ) { + insn_in_progress->appendOperand(Immediate::makeImmediate(Result(s64,layout.OFFSET)),false ,false); + }else{ + insn_in_progress->appendOperand(Immediate::makeImmediate(Result(s64,layout.OFFSET)),false,false); + insn_in_progress-> appendOperand( decodeSGPRorM0(layout.SOFFSET),true ,false); + } + } + } + + uint32_t InstructionDecoder_amdgpu_gfx908::decodeOPR_LITERAL(){ + useImm = true; + immLen = 4; + if(insn_size == 4) + immLiteral = imm_at_32; + else if(insn_size ==8) + immLiteral = imm_at_64; + else + assert(0 && "unsupported instruction size"); + + return immLiteral; + } + Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SDWA(){ + useImm = true; + immLen = 4; + if(insn_size == 4) + immLiteral = imm_at_32; + else if(insn_size ==8) + immLiteral = imm_at_64; + else + assert(0 && "unsupported instruction size"); + uint8_t reg_idx = immLiteral & 0xff; + extension = std::string("_SDWA"); + return makeRegisterExpression(makeAmdgpuRegID(amdgpu_gfx908::v0,reg_idx)); + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_LABEL(uint64_t input){ + Expression::Ptr lhs = makeAddExpression(makePCExpr(),Immediate::makeImmediate(Result(s48,4)),s48); + // 16 bits * 4 => 18 bits + int64_t offset = sign_extend64(18, input * 4); + Expression::Ptr rhs = Immediate::makeImmediate(Result(s64, offset)); + return makeAddExpression(lhs, rhs, s64); + + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx908::makeRegisterExpression(MachRegister registerID, uint32_t num_elements){ + if(registerID == amdgpu_gfx908::src_literal){ + return Immediate::makeImmediate(Result(u32,decodeOPR_LITERAL())); + } + return InstructionDecoderImpl::makeRegisterExpression(registerID,num_elements); + } + Expression::Ptr InstructionDecoder_amdgpu_gfx908::makeRegisterExpression(MachRegister registerID, uint32_t low, uint32_t high ){ + if(registerID == amdgpu_gfx908::src_literal){ + return Immediate::makeImmediate(Result(u32,decodeOPR_LITERAL())); + } + return InstructionDecoderImpl::makeRegisterExpression(registerID, low, high ); + } + + + + inline unsigned int InstructionDecoder_amdgpu_gfx908::get32bit(InstructionDecoder::buffer &b,unsigned int offset ){ + assert(offset %4 ==0 ); + if(b.start + offset + 4 <= b.end) + return b.start[offset+3] << 24 | b.start[offset + 2] << 16 | b.start[offset +1 ] << 8 | b.start [offset]; + return 0; + } + + + void InstructionDecoder_amdgpu_gfx908::reset(){ + immLen = 0; + insn_size = 0; + isBranch = false; + isConditional = false; + isModifyPC =false; + insn = insn_high = insn_long = 0; + useImm = false; + isCall = false; + extension = std::string(""); + } + // here we assemble the first 64 bit (if available) as an instruction + + void InstructionDecoder_amdgpu_gfx908::setupInsnWord(InstructionDecoder::buffer &b) { + reset(); + + + insn = get32bit(b,0); + + imm_at_32 = insn_high = get32bit(b,4); + imm_at_64 = get32bit(b,8); + + insn_long = ( ((uint64_t) insn_high) << 32) | insn; + + + } + void InstructionDecoder_amdgpu_gfx908::decodeOpcode(InstructionDecoder::buffer &b) { + setupInsnWord(b); + mainDecode(); + b.start += insn_in_progress->size(); + } + + void InstructionDecoder_amdgpu_gfx908::debug_instr(){ + cout << "decoded instruction " << insn_in_progress->getOperation().mnemonic << " " << std::hex << insn_long << " insn_family = " << instr_family + << " length = " << insn_in_progress->size()<< endl << endl; + + } + + Instruction InstructionDecoder_amdgpu_gfx908::decode(InstructionDecoder::buffer &b) { + setupInsnWord(b); + mainDecode(); + b.start += insn_in_progress->size(); + return *insn_in_progress; + } + + void InstructionDecoder_amdgpu_gfx908::doDelayedDecode(const Instruction *insn_to_complete) { + + InstructionDecoder::buffer b(insn_to_complete->ptr(), insn_to_complete->size()); + setupInsnWord(b); + mainDecode(); + Instruction* iptr = const_cast(insn_to_complete); + *iptr = *(insn_in_progress.get()); + } + } +} + + + diff --git a/instructionAPI/src/AMDGPU/gfx908/InstructionDecoder-amdgpu-gfx908.h b/instructionAPI/src/AMDGPU/gfx908/InstructionDecoder-amdgpu-gfx908.h new file mode 100644 index 0000000000..aa64797959 --- /dev/null +++ b/instructionAPI/src/AMDGPU/gfx908/InstructionDecoder-amdgpu-gfx908.h @@ -0,0 +1,3784 @@ +/* + * See the dyninst/COPYRIGHT file for copyright information. + * + * We provide the Paradyn Tools (below described as "Paradyn") + * on an AS IS basis, and do not warrant its validity or performance. + * We reserve the right to update, modify, or discontinue this + * software at any time. We shall have no obligation to supply such + * updates or modifications or any other form of support to you. + * + * By your use of Paradyn, you understand and agree that we (or any + * other person or entity with proprietary rights in Paradyn) are + * under no obligation to provide either maintenance services, + * update services, notices of latent defects, or correction of + * defects for Paradyn. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ +#ifndef INSTRUCTION_DECODER_GFX908_H +#define INSTRUCTION_DECODER_GFX908_H +#include +#include +#include +#include +#include "InstructionDecoderImpl.h" +#include +#include "Immediate.h" +#include "Architecture.h" +#include + +namespace Dyninst { + namespace InstructionAPI { + +#define insn_printf(format, ...) \ + do{ \ + printf("[%s:%u]insn_debug " format, FILE__, __LINE__, ## __VA_ARGS__); \ + }while(0) + + struct amdgpu_gfx908_insn_entry; + + class InstructionDecoder_amdgpu_gfx908 : public InstructionDecoderImpl { + friend struct amdgpu_gfx908_insn_entry; + friend struct amdgpu_mask_entry; + + public: + InstructionDecoder_amdgpu_gfx908(Architecture a) : InstructionDecoderImpl(a) {} + + virtual ~InstructionDecoder_amdgpu_gfx908() = default; + + virtual void decodeOpcode(InstructionDecoder::buffer &b); + + // decode one instruction starting from b.start + // will advance b.start whenver a instruction is successfully decoded + virtual Instruction decode(InstructionDecoder::buffer &b); + + virtual void setMode(bool) { } + + virtual bool decodeOperands(const Instruction *insn_to_complete); + + bool decodeOperands(const amdgpu_gfx908_insn_entry & insn_entry); + + virtual void doDelayedDecode(const Instruction *insn_to_complete); + + static const std::array condNames; + static MachRegister sysRegMap(unsigned int); + static const char* bitfieldInsnAliasMap(entryID); + static const char* condInsnAliasMap(entryID); + + + //Check if the index (2nd arg) is valid for the array (1st arg) + template + constexpr bool isArrayIndexValid(ArrayType (&)[n], const IndexType& i) const { + return 0 <= i && i < n; + } + + + private: + virtual Result_Type makeSizeType(unsigned int opType); + + bool is64Bit{}; + + unsigned int insn_size{}; // size of the instruction that we are currently working on + unsigned int insn{}; // the first 32 bit + unsigned int insn_high{}; // the second 32 bit + unsigned long long int insn_long{}; // the combined 64 bit: insn_high << 32 | insn + + // the main process of decoding an instruciton, won't advance buffer + void mainDecode(); + + void mainDecodeOpcode(); + + + void setupInsnWord(InstructionDecoder::buffer &b); + // pointer to the instruction that we are currently working on + dyncompat::shared_ptr insn_in_progress; + + template + int field(unsigned int raw) { +#if defined DEBUG_FIELD + std::cerr << start << "-" << end << ":" << std::dec << (raw >> (start) & + (0xFFFFFFFF >> (31 - (end - start)))) << " "; +#endif + return (raw >> (start) & (0xFFFFFFFF >> (31 - (end - start)))); + } + + template + int longfield(unsigned long long int raw) { +#if defined DEBUG_FIELD + std::cerr << start << "-" << end << ":" << std::dec << (raw >> (start) & + (0xFFFFFFFFFFFFFFFF >> (63 - (end - start)))) << " "; +#endif + return ( (raw >> (start)) & (0xFFFFFFFFFFFFFFFF >> (63 - (end - start)))); + } + + int32_t sign_extend32(int size_, int in) { + int32_t val = 0 | in; + + return (val << (32 - size_)) >> (32 - size_); + } + + int64_t sign_extend64(int size_, int in) { + int64_t val = 0 | in; + + return (val << (64 - size_)) >> (64 - size_); + } + + uint32_t unsign_extend32(int size_, int in) { + uint32_t mask = ~0; + + return (mask >> (32 - size_)) & in; + } + + uint64_t unsign_extend64(int size_, int in) { + uint64_t mask = ~0; + + return (mask >> (64 - size_)) & in; + } + + int highest_set_bit(int32_t val) { + for (int bit_index = 31; bit_index >= 0; bit_index--) + if (((static_cast(val) >> bit_index) & 0x1) == 0x1) + return bit_index + 1; + + return -1; + } + + int lowest_set_bit(int32_t val) { + for (int bit_index = 0; bit_index <= 31; bit_index++) + if (((static_cast(val) >> bit_index) & 0x1) == 0x1) + return bit_index + 1; + + return -1; + } + + std::string extension; + bool hasHw{}; + int hwField{}; + + void processHwFieldInsn(int, int); + + bool hasShift{}; + int shiftField{}; + + void makeBranchTarget(bool, bool, int, int immLen = 16); + + Expression::Ptr makeFallThroughExpr(); + + int _szField{}, size{}; + int _typeField{}; + int cmode{}; + int op{}; + int simdAlphabetImm{}; + + void processAlphabetImm(); + + void NOTHING(); + bool fix_bitfieldinsn_alias(int, int); + void fix_condinsn_alias_and_cond(int &); + void modify_mnemonic_simd_upperhalf_insns(); + + MachRegister makeAmdgpuRegID(MachRegister, unsigned int, unsigned int len = 1); + + MachRegister getLoadStoreSimdRegister(int encoding); + + Expression::Ptr makePCExpr(); + + + template + Expression::Ptr makeLogicalImm(int immr, int imms, int immsLen, Result_Type rT); + + + //for load store + void insnSize(unsigned int insn_size ); + + Expression::Ptr decodeSSRC(unsigned int index); + Expression::Ptr decodeVSRC(unsigned int index); + Expression::Ptr decodeVDST(unsigned int index); + + Expression::Ptr decodeSGPRorM0(unsigned int offset); + + + bool useImm{}; + uint32_t immLen{}; // extra 4 bytes included for decoding instruction + uint32_t immLiteral{}; + uint32_t imm_at_32{}; + uint32_t imm_at_64{}; + uint32_t imm_at_96{}; + + bool isBranch{}; // this is set for all branch instructions, + bool isConditional{}; // this is set for all conditional branch instruction, will set branchCond + bool isCall{}; // this is a call function + + + + // this is set for instructions that directly modify pc + // namely s_setpc and s_swappc + bool isModifyPC{}; + + // reset the decoder internal state for decoding the next instruction + void reset(); + + Expression::Ptr branchCond; + Expression::Ptr branchTarget; + + void setBranch() { + isBranch = true; + } + + void setConditionalBranch() { + isConditional = true; + // TODO : set conditional branch + } + void setModifyPC() { + isModifyPC = true; + } + + void setCall() { + isCall = true; + } + + inline unsigned int get32bit(InstructionDecoder::buffer &b,unsigned int offset ); + + template + void setUseImm(InstructionDecoder::buffer & b, unsigned int offset) + { + if (longfield(insn_long) == candidate) { + useImm = true; + immLen = 4; + immLiteral = get32bit(b,offset); + } + + } + + typedef struct buffer_resource_desc{ + unsigned long long base_address; + unsigned stride; + unsigned cache_swizzle; + unsigned swizzle_enable; + unsigned num_records; + unsigned dst_sel_x; + unsigned dst_sel_y; + unsigned dst_sel_z; + unsigned dst_sel_w; + unsigned num_format; + unsigned data_format; + unsigned user_vm_enable; + unsigned user_vm_mode; + unsigned index_stride; + unsigned add_tid_enable; + unsigned non_volatile; + unsigned type; + }buffer_resource_desc; + + void debug_instr(); + + uint32_t decodeOPR_LITERAL(); + Expression::Ptr decodeOPR_SDWA(); + Expression::Ptr decodeOPR_LABEL(uint64_t input); + using InstructionDecoderImpl::makeRegisterExpression; + Expression::Ptr makeRegisterExpression(MachRegister registerID, uint32_t num_elements = 1); + Expression::Ptr makeRegisterExpression(MachRegister registerID, uint32_t low , uint32_t high ); + void specialHandle(); + + static bool IS_ENC_SOP1(uint64_t I); + static bool IS_ENC_SOPC(uint64_t I); + static bool IS_ENC_SOPP(uint64_t I); + static bool IS_ENC_SOPK(uint64_t I); + static bool IS_ENC_SOP2(uint64_t I); + static bool IS_ENC_SMEM(uint64_t I); + static bool IS_ENC_VOP1(uint64_t I); + static bool IS_ENC_VOPC(uint64_t I); + static bool IS_ENC_VOP2(uint64_t I); + static bool IS_ENC_VINTRP(uint64_t I); + static bool IS_ENC_VOP3P(uint64_t I); + static bool IS_ENC_VOP3(uint64_t I); + static bool IS_ENC_DS(uint64_t I); + static bool IS_ENC_MUBUF(uint64_t I); + static bool IS_ENC_MTBUF(uint64_t I); + static bool IS_ENC_MIMG(uint64_t I); + static bool IS_ENC_EXP(uint64_t I); + static bool IS_ENC_FLAT(uint64_t I); + static bool IS_ENC_FLAT_GLBL(uint64_t I); + static bool IS_ENC_FLAT_SCRATCH(uint64_t I); + static bool IS_SOPK_INST_LITERAL_(uint64_t I); + static bool IS_ENC_VOP2_LITERAL(uint64_t I); + static bool IS_ENC_VOP3B(uint64_t I); + static bool IS_ENC_VOP3P_MFMA(uint64_t I); + enum InstructionFamily + { + ENC_SOP1 = -1, + ENC_SOPC = 0, + ENC_SOPP = 1, + ENC_SOPK = 2, + ENC_SOP2 = 3, + ENC_SMEM = 4, + ENC_VOP1 = 5, + ENC_VOPC = 6, + ENC_VOP2 = 7, + ENC_VINTRP = 8, + ENC_VOP3P = 9, + ENC_VOP3 = 10, + ENC_DS = 11, + ENC_MUBUF = 12, + ENC_MTBUF = 13, + ENC_MIMG = 14, + ENC_EXP = 15, + ENC_FLAT = 16, + ENC_FLAT_GLBL = 17, + ENC_FLAT_SCRATCH = 18, + SOPK_INST_LITERAL_ = 19, + ENC_VOP2_LITERAL = 20, + ENC_VOP3B = 21, + ENC_VOP3P_MFMA = 22, + }; + InstructionFamily instr_family; + struct layout_ENC_SOP1 { + uint16_t ENCODING : 9; + uint8_t OP : 8; + uint8_t SDST : 7; + uint8_t SSRC0 : 8; + }; + struct layout_ENC_SOPC { + uint16_t ENCODING : 9; + uint8_t OP : 7; + uint8_t SSRC0 : 8; + uint8_t SSRC1 : 8; + }; + struct layout_ENC_SOPP { + uint16_t ENCODING : 9; + uint8_t OP : 7; + uint16_t SIMM16 : 16; + }; + struct layout_ENC_SOPK { + uint8_t ENCODING : 4; + uint8_t OP : 5; + uint8_t SDST : 7; + uint16_t SIMM16 : 16; + }; + struct layout_ENC_SOP2 { + uint8_t ENCODING : 2; + uint8_t OP : 7; + uint8_t SDST : 7; + uint8_t SSRC0 : 8; + uint8_t SSRC1 : 8; + }; + struct layout_ENC_SMEM { + uint8_t ENCODING : 6; + uint8_t GLC : 1; + uint8_t IMM : 1; + uint8_t NV : 1; + uint32_t OFFSET : 21; + uint8_t OP : 8; + uint8_t SBASE : 7; + uint8_t SDATA : 7; + uint8_t SOFFSET : 7; + uint8_t SOFFSET_EN : 1; + }; + struct layout_ENC_VOP1 { + uint8_t ENCODING : 7; + uint8_t OP : 8; + uint16_t SRC0 : 9; + uint8_t VDST : 8; + }; + struct layout_ENC_VOPC { + uint8_t ENCODING : 7; + uint8_t OP : 8; + uint16_t SRC0 : 9; + uint8_t VSRC1 : 8; + }; + struct layout_ENC_VOP2 { + uint8_t ENCODING : 1; + uint8_t OP : 6; + uint16_t SRC0 : 9; + uint8_t VDST : 8; + uint8_t VSRC1 : 8; + }; + struct layout_ENC_VINTRP { + uint8_t ATTR : 6; + uint8_t ATTRCHAN : 2; + uint8_t ENCODING : 6; + uint8_t OP : 2; + uint8_t VDST : 8; + uint8_t VSRC : 8; + }; + struct layout_ENC_VOP3P { + uint8_t CLAMP : 1; + uint16_t ENCODING : 9; + uint8_t NEG : 3; + uint8_t NEG_HI : 3; + uint8_t OP : 7; + uint8_t OP_SEL : 3; + uint8_t OP_SEL_HI : 2; + uint8_t OP_SEL_HI_2 : 1; + uint16_t SRC0 : 9; + uint16_t SRC1 : 9; + uint16_t SRC2 : 9; + uint8_t VDST : 8; + }; + struct layout_ENC_VOP3 { + uint8_t ABS : 3; + uint8_t CLAMP : 1; + uint8_t ENCODING : 6; + uint8_t NEG : 3; + uint8_t OMOD : 2; + uint16_t OP : 10; + uint8_t OP_SEL : 4; + uint16_t SRC0 : 9; + uint16_t SRC1 : 9; + uint16_t SRC2 : 9; + uint8_t VDST : 8; + }; + struct layout_ENC_DS { + uint8_t ADDR : 8; + uint8_t DATA0 : 8; + uint8_t DATA1 : 8; + uint8_t ENCODING : 6; + uint8_t GDS : 1; + uint8_t OFFSET0 : 8; + uint8_t OFFSET1 : 8; + uint8_t OP : 8; + uint8_t VDST : 8; + }; + struct layout_ENC_MUBUF { + uint8_t ENCODING : 6; + uint8_t GLC : 1; + uint8_t IDXEN : 1; + uint8_t LDS : 1; + uint8_t OFFEN : 1; + uint16_t OFFSET : 12; + uint8_t OP : 7; + uint8_t SLC : 1; + uint8_t SOFFSET : 8; + uint8_t SRSRC : 7; + uint8_t TFE : 1; + uint8_t VADDR : 8; + uint8_t VDATA : 8; + }; + struct layout_ENC_MTBUF { + uint8_t DFMT : 4; + uint8_t ENCODING : 6; + uint8_t GLC : 1; + uint8_t IDXEN : 1; + uint8_t NFMT : 3; + uint8_t OFFEN : 1; + uint16_t OFFSET : 12; + uint8_t OP : 4; + uint8_t SLC : 1; + uint8_t SOFFSET : 8; + uint8_t SRSRC : 7; + uint8_t TFE : 1; + uint8_t VADDR : 8; + uint8_t VDATA : 8; + }; + struct layout_ENC_MIMG { + uint8_t A16 : 1; + uint8_t D16 : 1; + uint8_t DA : 1; + uint8_t DMASK : 4; + uint8_t ENCODING : 6; + uint8_t GLC : 1; + uint8_t LWE : 1; + uint8_t OP : 7; + uint8_t OPM : 1; + uint8_t SLC : 1; + uint8_t SRSRC : 7; + uint8_t SSAMP : 7; + uint8_t TFE : 1; + uint8_t UNORM : 1; + uint8_t VADDR : 8; + uint8_t VDATA : 8; + }; + struct layout_ENC_EXP { + uint8_t COMPR : 1; + uint8_t DONE : 1; + uint8_t EN : 4; + uint8_t ENCODING : 6; + uint8_t TGT : 6; + uint8_t VM : 1; + uint8_t VSRC0 : 8; + uint8_t VSRC1 : 8; + uint8_t VSRC2 : 8; + uint8_t VSRC3 : 8; + }; + struct layout_ENC_FLAT { + uint8_t ADDR : 8; + uint8_t DATA : 8; + uint8_t ENCODING : 6; + uint8_t GLC : 1; + uint8_t LDS : 1; + uint8_t NV : 1; + uint16_t OFFSET : 12; + uint8_t OP : 7; + uint8_t SADDR : 7; + uint8_t SEG : 2; + uint8_t SLC : 1; + uint8_t VDST : 8; + }; + struct layout_ENC_FLAT_GLBL { + uint8_t ADDR : 8; + uint8_t DATA : 8; + uint8_t ENCODING : 6; + uint8_t GLC : 1; + uint8_t LDS : 1; + uint8_t NV : 1; + uint16_t OFFSET : 13; + uint8_t OP : 7; + uint8_t SADDR : 7; + uint8_t SEG : 2; + uint8_t SLC : 1; + uint8_t VDST : 8; + }; + struct layout_ENC_FLAT_SCRATCH { + uint8_t ADDR : 8; + uint8_t DATA : 8; + uint8_t ENCODING : 6; + uint8_t GLC : 1; + uint8_t LDS : 1; + uint8_t NV : 1; + uint16_t OFFSET : 13; + uint8_t OP : 7; + uint8_t SADDR : 7; + uint8_t SEG : 2; + uint8_t SLC : 1; + uint8_t VDST : 8; + }; + struct layout_SOPK_INST_LITERAL_ { + uint8_t ENCODING : 4; + uint8_t OP : 5; + uint8_t SDST : 7; + uint16_t SIMM16 : 16; + uint32_t SIMM32 : 32; + }; + struct layout_ENC_VOP2_LITERAL { + uint8_t ENCODING : 1; + uint8_t OP : 6; + uint32_t SIMM32 : 32; + uint16_t SRC0 : 9; + uint8_t VDST : 8; + uint8_t VSRC1 : 8; + }; + struct layout_ENC_VOP3B { + uint8_t CLAMP : 1; + uint8_t ENCODING : 6; + uint8_t NEG : 3; + uint8_t OMOD : 2; + uint16_t OP : 10; + uint8_t SDST : 7; + uint16_t SRC0 : 9; + uint16_t SRC1 : 9; + uint16_t SRC2 : 9; + uint8_t VDST : 8; + }; + struct layout_ENC_VOP3P_MFMA { + uint8_t ABID : 4; + uint8_t ACC : 2; + uint8_t BLGP : 3; + uint8_t CBSZ : 3; + uint16_t ENCODING : 9; + uint8_t OP : 7; + uint16_t SRC0 : 9; + uint16_t SRC1 : 9; + uint16_t SRC2 : 9; + uint8_t VDST : 8; + }; + union insn_layout{ + + layout_ENC_SOP1 ENC_SOP1; + layout_ENC_SOPC ENC_SOPC; + layout_ENC_SOPP ENC_SOPP; + layout_ENC_SOPK ENC_SOPK; + layout_ENC_SOP2 ENC_SOP2; + layout_ENC_SMEM ENC_SMEM; + layout_ENC_VOP1 ENC_VOP1; + layout_ENC_VOPC ENC_VOPC; + layout_ENC_VOP2 ENC_VOP2; + layout_ENC_VINTRP ENC_VINTRP; + layout_ENC_VOP3P ENC_VOP3P; + layout_ENC_VOP3 ENC_VOP3; + layout_ENC_DS ENC_DS; + layout_ENC_MUBUF ENC_MUBUF; + layout_ENC_MTBUF ENC_MTBUF; + layout_ENC_MIMG ENC_MIMG; + layout_ENC_EXP ENC_EXP; + layout_ENC_FLAT ENC_FLAT; + layout_ENC_FLAT_GLBL ENC_FLAT_GLBL; + layout_ENC_FLAT_SCRATCH ENC_FLAT_SCRATCH; + layout_SOPK_INST_LITERAL_ SOPK_INST_LITERAL_; + layout_ENC_VOP2_LITERAL ENC_VOP2_LITERAL; + layout_ENC_VOP3B ENC_VOP3B; + layout_ENC_VOP3P_MFMA ENC_VOP3P_MFMA; + }insn_layout; + void decodeENC_SOP1(); + void finalizeENC_SOP1Operands(); + void decodeENC_SOPC(); + void finalizeENC_SOPCOperands(); + void decodeENC_SOPP(); + void finalizeENC_SOPPOperands(); + void decodeENC_SOPK(); + void finalizeENC_SOPKOperands(); + void decodeENC_SOP2(); + void finalizeENC_SOP2Operands(); + void decodeENC_SMEM(); + void finalizeENC_SMEMOperands(); + void decodeENC_VOP1(); + void finalizeENC_VOP1Operands(); + void decodeENC_VOPC(); + void finalizeENC_VOPCOperands(); + void decodeENC_VOP2(); + void finalizeENC_VOP2Operands(); + void decodeENC_VINTRP(); + void finalizeENC_VINTRPOperands(); + void decodeENC_VOP3P(); + void finalizeENC_VOP3POperands(); + void decodeENC_VOP3(); + void finalizeENC_VOP3Operands(); + void decodeENC_DS(); + void finalizeENC_DSOperands(); + void decodeENC_MUBUF(); + void finalizeENC_MUBUFOperands(); + void decodeENC_MTBUF(); + void finalizeENC_MTBUFOperands(); + void decodeENC_MIMG(); + void finalizeENC_MIMGOperands(); + void decodeENC_EXP(); + void finalizeENC_EXPOperands(); + void decodeENC_FLAT(); + void finalizeENC_FLATOperands(); + void decodeENC_FLAT_GLBL(); + void finalizeENC_FLAT_GLBLOperands(); + void decodeENC_FLAT_SCRATCH(); + void finalizeENC_FLAT_SCRATCHOperands(); + void decodeSOPK_INST_LITERAL_(); + void finalizeSOPK_INST_LITERAL_Operands(); + void decodeENC_VOP2_LITERAL(); + void finalizeENC_VOP2_LITERALOperands(); + void decodeENC_VOP3B(); + void finalizeENC_VOP3BOperands(); + void decodeENC_VOP3P_MFMA(); + void finalizeENC_VOP3P_MFMAOperands(); + + + Expression::Ptr decodeOPR_ACCVGPR(uint64_t input, uint32_t output_vec_len = 1 ); + Expression::Ptr decodeOPR_ATTR(uint64_t input, uint32_t output_vec_len = 1 ); + Expression::Ptr decodeOPR_DSMEM(uint64_t input, uint32_t output_vec_len = 1 ); + Expression::Ptr decodeOPR_FLAT_SCRATCH(uint64_t input, uint32_t output_vec_len = 1 ); + Expression::Ptr decodeOPR_PARAM(uint64_t input, uint32_t output_vec_len = 1 ); + Expression::Ptr decodeOPR_PC(uint64_t input, uint32_t output_vec_len = 1 ); + Expression::Ptr decodeOPR_SDST(uint64_t input, uint32_t output_vec_len = 1 ); + Expression::Ptr decodeOPR_SDST_EXEC(uint64_t input, uint32_t output_vec_len = 1 ); + Expression::Ptr decodeOPR_SDST_M0(uint64_t input, uint32_t output_vec_len = 1 ); + Expression::Ptr decodeOPR_SRC(uint64_t input, uint32_t output_vec_len = 1 ); + Expression::Ptr decodeOPR_SRC_ACCVGPR(uint64_t input, uint32_t output_vec_len = 1 ); + Expression::Ptr decodeOPR_SRC_ACCVGPR_OR_CONST(uint64_t input, uint32_t output_vec_len = 1 ); + Expression::Ptr decodeOPR_SRC_NOLDS(uint64_t input, uint32_t output_vec_len = 1 ); + Expression::Ptr decodeOPR_SRC_NOLIT(uint64_t input, uint32_t output_vec_len = 1 ); + Expression::Ptr decodeOPR_SRC_SIMPLE(uint64_t input, uint32_t output_vec_len = 1 ); + Expression::Ptr decodeOPR_SRC_VGPR(uint64_t input, uint32_t output_vec_len = 1 ); + Expression::Ptr decodeOPR_SRC_VGPR_OR_ACCVGPR(uint64_t input, uint32_t output_vec_len = 1 ); + Expression::Ptr decodeOPR_SREG(uint64_t input, uint32_t output_vec_len = 1 ); + Expression::Ptr decodeOPR_SREG_NOVCC(uint64_t input, uint32_t output_vec_len = 1 ); + Expression::Ptr decodeOPR_SSRC(uint64_t input, uint32_t output_vec_len = 1 ); + Expression::Ptr decodeOPR_SSRC_LANESEL(uint64_t input, uint32_t output_vec_len = 1 ); + Expression::Ptr decodeOPR_SSRC_NOLIT(uint64_t input, uint32_t output_vec_len = 1 ); + Expression::Ptr decodeOPR_SSRC_SPECIAL_SCC(uint64_t input, uint32_t output_vec_len = 1 ); + Expression::Ptr decodeOPR_TGT(uint64_t input, uint32_t output_vec_len = 1 ); + Expression::Ptr decodeOPR_VCC(uint64_t input, uint32_t output_vec_len = 1 ); + Expression::Ptr decodeOPR_VGPR(uint64_t input, uint32_t output_vec_len = 1 ); + Expression::Ptr decodeOPR_VGPR_OR_LDS(uint64_t input, uint32_t output_vec_len = 1 ); + + + void appendOPR_SIMM4(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_SIMM8(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_SIMM16(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_SIMM32(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_WAITCNT(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_ACCVGPR(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_ATTR(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_DSMEM(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_FLAT_SCRATCH(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_PARAM(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_PC(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_SDST(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_SDST_EXEC(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_SDST_M0(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void processOPR_SMEM_OFFSET(layout_ENC_SMEM & layout ); + + void appendOPR_SRC(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_SRC_ACCVGPR(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_SRC_ACCVGPR_OR_CONST(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_SRC_NOLDS(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_SRC_NOLIT(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_SRC_SIMPLE(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_SRC_VGPR(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_SRC_VGPR_OR_ACCVGPR(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_SREG(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_SREG_NOVCC(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_SSRC(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_SSRC_LANESEL(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_SSRC_NOLIT(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_SSRC_SPECIAL_SCC(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_TGT(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_VCC(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_VGPR(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_VGPR_OR_LDS(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + + + struct amdgpu_gfx908_insn_entry { + entryID op; + const char *mnemonic; + }; + + + const amdgpu_gfx908_insn_entry ENC_DS_insn_table[256] = + { + {amdgpu_gfx908_op_DS_ADD_U32,"DS_ADD_U32"}, // 0 + {amdgpu_gfx908_op_DS_SUB_U32,"DS_SUB_U32"}, // 1 + {amdgpu_gfx908_op_DS_RSUB_U32,"DS_RSUB_U32"}, // 2 + {amdgpu_gfx908_op_DS_INC_U32,"DS_INC_U32"}, // 3 + {amdgpu_gfx908_op_DS_DEC_U32,"DS_DEC_U32"}, // 4 + {amdgpu_gfx908_op_DS_MIN_I32,"DS_MIN_I32"}, // 5 + {amdgpu_gfx908_op_DS_MAX_I32,"DS_MAX_I32"}, // 6 + {amdgpu_gfx908_op_DS_MIN_U32,"DS_MIN_U32"}, // 7 + {amdgpu_gfx908_op_DS_MAX_U32,"DS_MAX_U32"}, // 8 + {amdgpu_gfx908_op_DS_AND_B32,"DS_AND_B32"}, // 9 + {amdgpu_gfx908_op_DS_OR_B32,"DS_OR_B32"}, // 10 + {amdgpu_gfx908_op_DS_XOR_B32,"DS_XOR_B32"}, // 11 + {amdgpu_gfx908_op_DS_MSKOR_B32,"DS_MSKOR_B32"}, // 12 + {amdgpu_gfx908_op_DS_WRITE_B32,"DS_WRITE_B32"}, // 13 + {amdgpu_gfx908_op_DS_WRITE2_B32,"DS_WRITE2_B32"}, // 14 + {amdgpu_gfx908_op_DS_WRITE2ST64_B32,"DS_WRITE2ST64_B32"}, // 15 + {amdgpu_gfx908_op_DS_CMPST_B32,"DS_CMPST_B32"}, // 16 + {amdgpu_gfx908_op_DS_CMPST_F32,"DS_CMPST_F32"}, // 17 + {amdgpu_gfx908_op_DS_MIN_F32,"DS_MIN_F32"}, // 18 + {amdgpu_gfx908_op_DS_MAX_F32,"DS_MAX_F32"}, // 19 + {amdgpu_gfx908_op_DS_NOP,"DS_NOP"}, // 20 + {amdgpu_gfx908_op_DS_ADD_F32,"DS_ADD_F32"}, // 21 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 22 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 23 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 24 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 25 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 26 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 27 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 28 + {amdgpu_gfx908_op_DS_WRITE_ADDTID_B32,"DS_WRITE_ADDTID_B32"}, // 29 + {amdgpu_gfx908_op_DS_WRITE_B8,"DS_WRITE_B8"}, // 30 + {amdgpu_gfx908_op_DS_WRITE_B16,"DS_WRITE_B16"}, // 31 + {amdgpu_gfx908_op_DS_ADD_RTN_U32,"DS_ADD_RTN_U32"}, // 32 + {amdgpu_gfx908_op_DS_SUB_RTN_U32,"DS_SUB_RTN_U32"}, // 33 + {amdgpu_gfx908_op_DS_RSUB_RTN_U32,"DS_RSUB_RTN_U32"}, // 34 + {amdgpu_gfx908_op_DS_INC_RTN_U32,"DS_INC_RTN_U32"}, // 35 + {amdgpu_gfx908_op_DS_DEC_RTN_U32,"DS_DEC_RTN_U32"}, // 36 + {amdgpu_gfx908_op_DS_MIN_RTN_I32,"DS_MIN_RTN_I32"}, // 37 + {amdgpu_gfx908_op_DS_MAX_RTN_I32,"DS_MAX_RTN_I32"}, // 38 + {amdgpu_gfx908_op_DS_MIN_RTN_U32,"DS_MIN_RTN_U32"}, // 39 + {amdgpu_gfx908_op_DS_MAX_RTN_U32,"DS_MAX_RTN_U32"}, // 40 + {amdgpu_gfx908_op_DS_AND_RTN_B32,"DS_AND_RTN_B32"}, // 41 + {amdgpu_gfx908_op_DS_OR_RTN_B32,"DS_OR_RTN_B32"}, // 42 + {amdgpu_gfx908_op_DS_XOR_RTN_B32,"DS_XOR_RTN_B32"}, // 43 + {amdgpu_gfx908_op_DS_MSKOR_RTN_B32,"DS_MSKOR_RTN_B32"}, // 44 + {amdgpu_gfx908_op_DS_WRXCHG_RTN_B32,"DS_WRXCHG_RTN_B32"}, // 45 + {amdgpu_gfx908_op_DS_WRXCHG2_RTN_B32,"DS_WRXCHG2_RTN_B32"}, // 46 + {amdgpu_gfx908_op_DS_WRXCHG2ST64_RTN_B32,"DS_WRXCHG2ST64_RTN_B32"}, // 47 + {amdgpu_gfx908_op_DS_CMPST_RTN_B32,"DS_CMPST_RTN_B32"}, // 48 + {amdgpu_gfx908_op_DS_CMPST_RTN_F32,"DS_CMPST_RTN_F32"}, // 49 + {amdgpu_gfx908_op_DS_MIN_RTN_F32,"DS_MIN_RTN_F32"}, // 50 + {amdgpu_gfx908_op_DS_MAX_RTN_F32,"DS_MAX_RTN_F32"}, // 51 + {amdgpu_gfx908_op_DS_WRAP_RTN_B32,"DS_WRAP_RTN_B32"}, // 52 + {amdgpu_gfx908_op_DS_ADD_RTN_F32,"DS_ADD_RTN_F32"}, // 53 + {amdgpu_gfx908_op_DS_READ_B32,"DS_READ_B32"}, // 54 + {amdgpu_gfx908_op_DS_READ2_B32,"DS_READ2_B32"}, // 55 + {amdgpu_gfx908_op_DS_READ2ST64_B32,"DS_READ2ST64_B32"}, // 56 + {amdgpu_gfx908_op_DS_READ_I8,"DS_READ_I8"}, // 57 + {amdgpu_gfx908_op_DS_READ_U8,"DS_READ_U8"}, // 58 + {amdgpu_gfx908_op_DS_READ_I16,"DS_READ_I16"}, // 59 + {amdgpu_gfx908_op_DS_READ_U16,"DS_READ_U16"}, // 60 + {amdgpu_gfx908_op_DS_SWIZZLE_B32,"DS_SWIZZLE_B32"}, // 61 + {amdgpu_gfx908_op_DS_PERMUTE_B32,"DS_PERMUTE_B32"}, // 62 + {amdgpu_gfx908_op_DS_BPERMUTE_B32,"DS_BPERMUTE_B32"}, // 63 + {amdgpu_gfx908_op_DS_ADD_U64,"DS_ADD_U64"}, // 64 + {amdgpu_gfx908_op_DS_SUB_U64,"DS_SUB_U64"}, // 65 + {amdgpu_gfx908_op_DS_RSUB_U64,"DS_RSUB_U64"}, // 66 + {amdgpu_gfx908_op_DS_INC_U64,"DS_INC_U64"}, // 67 + {amdgpu_gfx908_op_DS_DEC_U64,"DS_DEC_U64"}, // 68 + {amdgpu_gfx908_op_DS_MIN_I64,"DS_MIN_I64"}, // 69 + {amdgpu_gfx908_op_DS_MAX_I64,"DS_MAX_I64"}, // 70 + {amdgpu_gfx908_op_DS_MIN_U64,"DS_MIN_U64"}, // 71 + {amdgpu_gfx908_op_DS_MAX_U64,"DS_MAX_U64"}, // 72 + {amdgpu_gfx908_op_DS_AND_B64,"DS_AND_B64"}, // 73 + {amdgpu_gfx908_op_DS_OR_B64,"DS_OR_B64"}, // 74 + {amdgpu_gfx908_op_DS_XOR_B64,"DS_XOR_B64"}, // 75 + {amdgpu_gfx908_op_DS_MSKOR_B64,"DS_MSKOR_B64"}, // 76 + {amdgpu_gfx908_op_DS_WRITE_B64,"DS_WRITE_B64"}, // 77 + {amdgpu_gfx908_op_DS_WRITE2_B64,"DS_WRITE2_B64"}, // 78 + {amdgpu_gfx908_op_DS_WRITE2ST64_B64,"DS_WRITE2ST64_B64"}, // 79 + {amdgpu_gfx908_op_DS_CMPST_B64,"DS_CMPST_B64"}, // 80 + {amdgpu_gfx908_op_DS_CMPST_F64,"DS_CMPST_F64"}, // 81 + {amdgpu_gfx908_op_DS_MIN_F64,"DS_MIN_F64"}, // 82 + {amdgpu_gfx908_op_DS_MAX_F64,"DS_MAX_F64"}, // 83 + {amdgpu_gfx908_op_DS_WRITE_B8_D16_HI,"DS_WRITE_B8_D16_HI"}, // 84 + {amdgpu_gfx908_op_DS_WRITE_B16_D16_HI,"DS_WRITE_B16_D16_HI"}, // 85 + {amdgpu_gfx908_op_DS_READ_U8_D16,"DS_READ_U8_D16"}, // 86 + {amdgpu_gfx908_op_DS_READ_U8_D16_HI,"DS_READ_U8_D16_HI"}, // 87 + {amdgpu_gfx908_op_DS_READ_I8_D16,"DS_READ_I8_D16"}, // 88 + {amdgpu_gfx908_op_DS_READ_I8_D16_HI,"DS_READ_I8_D16_HI"}, // 89 + {amdgpu_gfx908_op_DS_READ_U16_D16,"DS_READ_U16_D16"}, // 90 + {amdgpu_gfx908_op_DS_READ_U16_D16_HI,"DS_READ_U16_D16_HI"}, // 91 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 92 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 93 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 94 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 95 + {amdgpu_gfx908_op_DS_ADD_RTN_U64,"DS_ADD_RTN_U64"}, // 96 + {amdgpu_gfx908_op_DS_SUB_RTN_U64,"DS_SUB_RTN_U64"}, // 97 + {amdgpu_gfx908_op_DS_RSUB_RTN_U64,"DS_RSUB_RTN_U64"}, // 98 + {amdgpu_gfx908_op_DS_INC_RTN_U64,"DS_INC_RTN_U64"}, // 99 + {amdgpu_gfx908_op_DS_DEC_RTN_U64,"DS_DEC_RTN_U64"}, // 100 + {amdgpu_gfx908_op_DS_MIN_RTN_I64,"DS_MIN_RTN_I64"}, // 101 + {amdgpu_gfx908_op_DS_MAX_RTN_I64,"DS_MAX_RTN_I64"}, // 102 + {amdgpu_gfx908_op_DS_MIN_RTN_U64,"DS_MIN_RTN_U64"}, // 103 + {amdgpu_gfx908_op_DS_MAX_RTN_U64,"DS_MAX_RTN_U64"}, // 104 + {amdgpu_gfx908_op_DS_AND_RTN_B64,"DS_AND_RTN_B64"}, // 105 + {amdgpu_gfx908_op_DS_OR_RTN_B64,"DS_OR_RTN_B64"}, // 106 + {amdgpu_gfx908_op_DS_XOR_RTN_B64,"DS_XOR_RTN_B64"}, // 107 + {amdgpu_gfx908_op_DS_MSKOR_RTN_B64,"DS_MSKOR_RTN_B64"}, // 108 + {amdgpu_gfx908_op_DS_WRXCHG_RTN_B64,"DS_WRXCHG_RTN_B64"}, // 109 + {amdgpu_gfx908_op_DS_WRXCHG2_RTN_B64,"DS_WRXCHG2_RTN_B64"}, // 110 + {amdgpu_gfx908_op_DS_WRXCHG2ST64_RTN_B64,"DS_WRXCHG2ST64_RTN_B64"}, // 111 + {amdgpu_gfx908_op_DS_CMPST_RTN_B64,"DS_CMPST_RTN_B64"}, // 112 + {amdgpu_gfx908_op_DS_CMPST_RTN_F64,"DS_CMPST_RTN_F64"}, // 113 + {amdgpu_gfx908_op_DS_MIN_RTN_F64,"DS_MIN_RTN_F64"}, // 114 + {amdgpu_gfx908_op_DS_MAX_RTN_F64,"DS_MAX_RTN_F64"}, // 115 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 116 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 117 + {amdgpu_gfx908_op_DS_READ_B64,"DS_READ_B64"}, // 118 + {amdgpu_gfx908_op_DS_READ2_B64,"DS_READ2_B64"}, // 119 + {amdgpu_gfx908_op_DS_READ2ST64_B64,"DS_READ2ST64_B64"}, // 120 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 121 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 122 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 123 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 124 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 125 + {amdgpu_gfx908_op_DS_CONDXCHG32_RTN_B64,"DS_CONDXCHG32_RTN_B64"}, // 126 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 127 + {amdgpu_gfx908_op_DS_ADD_SRC2_U32,"DS_ADD_SRC2_U32"}, // 128 + {amdgpu_gfx908_op_DS_SUB_SRC2_U32,"DS_SUB_SRC2_U32"}, // 129 + {amdgpu_gfx908_op_DS_RSUB_SRC2_U32,"DS_RSUB_SRC2_U32"}, // 130 + {amdgpu_gfx908_op_DS_INC_SRC2_U32,"DS_INC_SRC2_U32"}, // 131 + {amdgpu_gfx908_op_DS_DEC_SRC2_U32,"DS_DEC_SRC2_U32"}, // 132 + {amdgpu_gfx908_op_DS_MIN_SRC2_I32,"DS_MIN_SRC2_I32"}, // 133 + {amdgpu_gfx908_op_DS_MAX_SRC2_I32,"DS_MAX_SRC2_I32"}, // 134 + {amdgpu_gfx908_op_DS_MIN_SRC2_U32,"DS_MIN_SRC2_U32"}, // 135 + {amdgpu_gfx908_op_DS_MAX_SRC2_U32,"DS_MAX_SRC2_U32"}, // 136 + {amdgpu_gfx908_op_DS_AND_SRC2_B32,"DS_AND_SRC2_B32"}, // 137 + {amdgpu_gfx908_op_DS_OR_SRC2_B32,"DS_OR_SRC2_B32"}, // 138 + {amdgpu_gfx908_op_DS_XOR_SRC2_B32,"DS_XOR_SRC2_B32"}, // 139 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 140 + {amdgpu_gfx908_op_DS_WRITE_SRC2_B32,"DS_WRITE_SRC2_B32"}, // 141 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 142 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 143 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 144 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 145 + {amdgpu_gfx908_op_DS_MIN_SRC2_F32,"DS_MIN_SRC2_F32"}, // 146 + {amdgpu_gfx908_op_DS_MAX_SRC2_F32,"DS_MAX_SRC2_F32"}, // 147 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 148 + {amdgpu_gfx908_op_DS_ADD_SRC2_F32,"DS_ADD_SRC2_F32"}, // 149 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 150 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 151 + {amdgpu_gfx908_op_DS_GWS_SEMA_RELEASE_ALL,"DS_GWS_SEMA_RELEASE_ALL"}, // 152 + {amdgpu_gfx908_op_DS_GWS_INIT,"DS_GWS_INIT"}, // 153 + {amdgpu_gfx908_op_DS_GWS_SEMA_V,"DS_GWS_SEMA_V"}, // 154 + {amdgpu_gfx908_op_DS_GWS_SEMA_BR,"DS_GWS_SEMA_BR"}, // 155 + {amdgpu_gfx908_op_DS_GWS_SEMA_P,"DS_GWS_SEMA_P"}, // 156 + {amdgpu_gfx908_op_DS_GWS_BARRIER,"DS_GWS_BARRIER"}, // 157 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 158 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 159 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 160 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 161 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 162 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 163 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 164 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 165 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 166 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 167 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 168 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 169 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 170 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 171 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 172 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 173 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 174 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 175 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 176 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 177 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 178 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 179 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 180 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 181 + {amdgpu_gfx908_op_DS_READ_ADDTID_B32,"DS_READ_ADDTID_B32"}, // 182 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 183 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 184 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 185 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 186 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 187 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 188 + {amdgpu_gfx908_op_DS_CONSUME,"DS_CONSUME"}, // 189 + {amdgpu_gfx908_op_DS_APPEND,"DS_APPEND"}, // 190 + {amdgpu_gfx908_op_DS_ORDERED_COUNT,"DS_ORDERED_COUNT"}, // 191 + {amdgpu_gfx908_op_DS_ADD_SRC2_U64,"DS_ADD_SRC2_U64"}, // 192 + {amdgpu_gfx908_op_DS_SUB_SRC2_U64,"DS_SUB_SRC2_U64"}, // 193 + {amdgpu_gfx908_op_DS_RSUB_SRC2_U64,"DS_RSUB_SRC2_U64"}, // 194 + {amdgpu_gfx908_op_DS_INC_SRC2_U64,"DS_INC_SRC2_U64"}, // 195 + {amdgpu_gfx908_op_DS_DEC_SRC2_U64,"DS_DEC_SRC2_U64"}, // 196 + {amdgpu_gfx908_op_DS_MIN_SRC2_I64,"DS_MIN_SRC2_I64"}, // 197 + {amdgpu_gfx908_op_DS_MAX_SRC2_I64,"DS_MAX_SRC2_I64"}, // 198 + {amdgpu_gfx908_op_DS_MIN_SRC2_U64,"DS_MIN_SRC2_U64"}, // 199 + {amdgpu_gfx908_op_DS_MAX_SRC2_U64,"DS_MAX_SRC2_U64"}, // 200 + {amdgpu_gfx908_op_DS_AND_SRC2_B64,"DS_AND_SRC2_B64"}, // 201 + {amdgpu_gfx908_op_DS_OR_SRC2_B64,"DS_OR_SRC2_B64"}, // 202 + {amdgpu_gfx908_op_DS_XOR_SRC2_B64,"DS_XOR_SRC2_B64"}, // 203 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 204 + {amdgpu_gfx908_op_DS_WRITE_SRC2_B64,"DS_WRITE_SRC2_B64"}, // 205 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 206 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 207 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 208 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 209 + {amdgpu_gfx908_op_DS_MIN_SRC2_F64,"DS_MIN_SRC2_F64"}, // 210 + {amdgpu_gfx908_op_DS_MAX_SRC2_F64,"DS_MAX_SRC2_F64"}, // 211 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 212 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 213 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 214 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 215 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 216 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 217 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 218 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 219 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 220 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 221 + {amdgpu_gfx908_op_DS_WRITE_B96,"DS_WRITE_B96"}, // 222 + {amdgpu_gfx908_op_DS_WRITE_B128,"DS_WRITE_B128"}, // 223 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 224 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 225 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 226 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 227 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 228 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 229 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 230 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 231 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 232 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 233 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 234 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 235 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 236 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 237 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 238 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 239 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 240 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 241 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 242 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 243 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 244 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 245 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 246 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 247 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 248 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 249 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 250 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 251 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 252 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 253 + {amdgpu_gfx908_op_DS_READ_B96,"DS_READ_B96"}, // 254 + {amdgpu_gfx908_op_DS_READ_B128,"DS_READ_B128"}, // 255 + }; // end ENC_DS_insn_table + const amdgpu_gfx908_insn_entry ENC_EXP_insn_table[1] = + { + {amdgpu_gfx908_op_EXP,"EXP"}, // 0 + }; // end ENC_EXP_insn_table + const amdgpu_gfx908_insn_entry ENC_FLAT_insn_table[109] = + { + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 0 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 1 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 2 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 3 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 4 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 5 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 6 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 7 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 8 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 9 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 10 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 11 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 12 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 13 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 14 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 15 + {amdgpu_gfx908_op_FLAT_LOAD_UBYTE,"FLAT_LOAD_UBYTE"}, // 16 + {amdgpu_gfx908_op_FLAT_LOAD_SBYTE,"FLAT_LOAD_SBYTE"}, // 17 + {amdgpu_gfx908_op_FLAT_LOAD_USHORT,"FLAT_LOAD_USHORT"}, // 18 + {amdgpu_gfx908_op_FLAT_LOAD_SSHORT,"FLAT_LOAD_SSHORT"}, // 19 + {amdgpu_gfx908_op_FLAT_LOAD_DWORD,"FLAT_LOAD_DWORD"}, // 20 + {amdgpu_gfx908_op_FLAT_LOAD_DWORDX2,"FLAT_LOAD_DWORDX2"}, // 21 + {amdgpu_gfx908_op_FLAT_LOAD_DWORDX3,"FLAT_LOAD_DWORDX3"}, // 22 + {amdgpu_gfx908_op_FLAT_LOAD_DWORDX4,"FLAT_LOAD_DWORDX4"}, // 23 + {amdgpu_gfx908_op_FLAT_STORE_BYTE,"FLAT_STORE_BYTE"}, // 24 + {amdgpu_gfx908_op_FLAT_STORE_BYTE_D16_HI,"FLAT_STORE_BYTE_D16_HI"}, // 25 + {amdgpu_gfx908_op_FLAT_STORE_SHORT,"FLAT_STORE_SHORT"}, // 26 + {amdgpu_gfx908_op_FLAT_STORE_SHORT_D16_HI,"FLAT_STORE_SHORT_D16_HI"}, // 27 + {amdgpu_gfx908_op_FLAT_STORE_DWORD,"FLAT_STORE_DWORD"}, // 28 + {amdgpu_gfx908_op_FLAT_STORE_DWORDX2,"FLAT_STORE_DWORDX2"}, // 29 + {amdgpu_gfx908_op_FLAT_STORE_DWORDX3,"FLAT_STORE_DWORDX3"}, // 30 + {amdgpu_gfx908_op_FLAT_STORE_DWORDX4,"FLAT_STORE_DWORDX4"}, // 31 + {amdgpu_gfx908_op_FLAT_LOAD_UBYTE_D16,"FLAT_LOAD_UBYTE_D16"}, // 32 + {amdgpu_gfx908_op_FLAT_LOAD_UBYTE_D16_HI,"FLAT_LOAD_UBYTE_D16_HI"}, // 33 + {amdgpu_gfx908_op_FLAT_LOAD_SBYTE_D16,"FLAT_LOAD_SBYTE_D16"}, // 34 + {amdgpu_gfx908_op_FLAT_LOAD_SBYTE_D16_HI,"FLAT_LOAD_SBYTE_D16_HI"}, // 35 + {amdgpu_gfx908_op_FLAT_LOAD_SHORT_D16,"FLAT_LOAD_SHORT_D16"}, // 36 + {amdgpu_gfx908_op_FLAT_LOAD_SHORT_D16_HI,"FLAT_LOAD_SHORT_D16_HI"}, // 37 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 38 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 39 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 40 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 41 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 42 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 43 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 44 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 45 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 46 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 47 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 48 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 49 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 50 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 51 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 52 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 53 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 54 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 55 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 56 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 57 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 58 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 59 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 60 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 61 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 62 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 63 + {amdgpu_gfx908_op_FLAT_ATOMIC_SWAP,"FLAT_ATOMIC_SWAP"}, // 64 + {amdgpu_gfx908_op_FLAT_ATOMIC_CMPSWAP,"FLAT_ATOMIC_CMPSWAP"}, // 65 + {amdgpu_gfx908_op_FLAT_ATOMIC_ADD,"FLAT_ATOMIC_ADD"}, // 66 + {amdgpu_gfx908_op_FLAT_ATOMIC_SUB,"FLAT_ATOMIC_SUB"}, // 67 + {amdgpu_gfx908_op_FLAT_ATOMIC_SMIN,"FLAT_ATOMIC_SMIN"}, // 68 + {amdgpu_gfx908_op_FLAT_ATOMIC_UMIN,"FLAT_ATOMIC_UMIN"}, // 69 + {amdgpu_gfx908_op_FLAT_ATOMIC_SMAX,"FLAT_ATOMIC_SMAX"}, // 70 + {amdgpu_gfx908_op_FLAT_ATOMIC_UMAX,"FLAT_ATOMIC_UMAX"}, // 71 + {amdgpu_gfx908_op_FLAT_ATOMIC_AND,"FLAT_ATOMIC_AND"}, // 72 + {amdgpu_gfx908_op_FLAT_ATOMIC_OR,"FLAT_ATOMIC_OR"}, // 73 + {amdgpu_gfx908_op_FLAT_ATOMIC_XOR,"FLAT_ATOMIC_XOR"}, // 74 + {amdgpu_gfx908_op_FLAT_ATOMIC_INC,"FLAT_ATOMIC_INC"}, // 75 + {amdgpu_gfx908_op_FLAT_ATOMIC_DEC,"FLAT_ATOMIC_DEC"}, // 76 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 77 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 78 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 79 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 80 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 81 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 82 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 83 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 84 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 85 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 86 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 87 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 88 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 89 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 90 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 91 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 92 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 93 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 94 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 95 + {amdgpu_gfx908_op_FLAT_ATOMIC_SWAP_X2,"FLAT_ATOMIC_SWAP_X2"}, // 96 + {amdgpu_gfx908_op_FLAT_ATOMIC_CMPSWAP_X2,"FLAT_ATOMIC_CMPSWAP_X2"}, // 97 + {amdgpu_gfx908_op_FLAT_ATOMIC_ADD_X2,"FLAT_ATOMIC_ADD_X2"}, // 98 + {amdgpu_gfx908_op_FLAT_ATOMIC_SUB_X2,"FLAT_ATOMIC_SUB_X2"}, // 99 + {amdgpu_gfx908_op_FLAT_ATOMIC_SMIN_X2,"FLAT_ATOMIC_SMIN_X2"}, // 100 + {amdgpu_gfx908_op_FLAT_ATOMIC_UMIN_X2,"FLAT_ATOMIC_UMIN_X2"}, // 101 + {amdgpu_gfx908_op_FLAT_ATOMIC_SMAX_X2,"FLAT_ATOMIC_SMAX_X2"}, // 102 + {amdgpu_gfx908_op_FLAT_ATOMIC_UMAX_X2,"FLAT_ATOMIC_UMAX_X2"}, // 103 + {amdgpu_gfx908_op_FLAT_ATOMIC_AND_X2,"FLAT_ATOMIC_AND_X2"}, // 104 + {amdgpu_gfx908_op_FLAT_ATOMIC_OR_X2,"FLAT_ATOMIC_OR_X2"}, // 105 + {amdgpu_gfx908_op_FLAT_ATOMIC_XOR_X2,"FLAT_ATOMIC_XOR_X2"}, // 106 + {amdgpu_gfx908_op_FLAT_ATOMIC_INC_X2,"FLAT_ATOMIC_INC_X2"}, // 107 + {amdgpu_gfx908_op_FLAT_ATOMIC_DEC_X2,"FLAT_ATOMIC_DEC_X2"}, // 108 + }; // end ENC_FLAT_insn_table + const amdgpu_gfx908_insn_entry ENC_FLAT_GLBL_insn_table[109] = + { + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 0 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 1 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 2 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 3 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 4 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 5 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 6 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 7 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 8 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 9 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 10 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 11 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 12 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 13 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 14 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 15 + {amdgpu_gfx908_op_GLOBAL_LOAD_UBYTE,"GLOBAL_LOAD_UBYTE"}, // 16 + {amdgpu_gfx908_op_GLOBAL_LOAD_SBYTE,"GLOBAL_LOAD_SBYTE"}, // 17 + {amdgpu_gfx908_op_GLOBAL_LOAD_USHORT,"GLOBAL_LOAD_USHORT"}, // 18 + {amdgpu_gfx908_op_GLOBAL_LOAD_SSHORT,"GLOBAL_LOAD_SSHORT"}, // 19 + {amdgpu_gfx908_op_GLOBAL_LOAD_DWORD,"GLOBAL_LOAD_DWORD"}, // 20 + {amdgpu_gfx908_op_GLOBAL_LOAD_DWORDX2,"GLOBAL_LOAD_DWORDX2"}, // 21 + {amdgpu_gfx908_op_GLOBAL_LOAD_DWORDX3,"GLOBAL_LOAD_DWORDX3"}, // 22 + {amdgpu_gfx908_op_GLOBAL_LOAD_DWORDX4,"GLOBAL_LOAD_DWORDX4"}, // 23 + {amdgpu_gfx908_op_GLOBAL_STORE_BYTE,"GLOBAL_STORE_BYTE"}, // 24 + {amdgpu_gfx908_op_GLOBAL_STORE_BYTE_D16_HI,"GLOBAL_STORE_BYTE_D16_HI"}, // 25 + {amdgpu_gfx908_op_GLOBAL_STORE_SHORT,"GLOBAL_STORE_SHORT"}, // 26 + {amdgpu_gfx908_op_GLOBAL_STORE_SHORT_D16_HI,"GLOBAL_STORE_SHORT_D16_HI"}, // 27 + {amdgpu_gfx908_op_GLOBAL_STORE_DWORD,"GLOBAL_STORE_DWORD"}, // 28 + {amdgpu_gfx908_op_GLOBAL_STORE_DWORDX2,"GLOBAL_STORE_DWORDX2"}, // 29 + {amdgpu_gfx908_op_GLOBAL_STORE_DWORDX3,"GLOBAL_STORE_DWORDX3"}, // 30 + {amdgpu_gfx908_op_GLOBAL_STORE_DWORDX4,"GLOBAL_STORE_DWORDX4"}, // 31 + {amdgpu_gfx908_op_GLOBAL_LOAD_UBYTE_D16,"GLOBAL_LOAD_UBYTE_D16"}, // 32 + {amdgpu_gfx908_op_GLOBAL_LOAD_UBYTE_D16_HI,"GLOBAL_LOAD_UBYTE_D16_HI"}, // 33 + {amdgpu_gfx908_op_GLOBAL_LOAD_SBYTE_D16,"GLOBAL_LOAD_SBYTE_D16"}, // 34 + {amdgpu_gfx908_op_GLOBAL_LOAD_SBYTE_D16_HI,"GLOBAL_LOAD_SBYTE_D16_HI"}, // 35 + {amdgpu_gfx908_op_GLOBAL_LOAD_SHORT_D16,"GLOBAL_LOAD_SHORT_D16"}, // 36 + {amdgpu_gfx908_op_GLOBAL_LOAD_SHORT_D16_HI,"GLOBAL_LOAD_SHORT_D16_HI"}, // 37 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 38 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 39 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 40 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 41 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 42 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 43 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 44 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 45 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 46 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 47 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 48 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 49 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 50 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 51 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 52 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 53 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 54 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 55 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 56 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 57 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 58 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 59 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 60 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 61 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 62 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 63 + {amdgpu_gfx908_op_GLOBAL_ATOMIC_SWAP,"GLOBAL_ATOMIC_SWAP"}, // 64 + {amdgpu_gfx908_op_GLOBAL_ATOMIC_CMPSWAP,"GLOBAL_ATOMIC_CMPSWAP"}, // 65 + {amdgpu_gfx908_op_GLOBAL_ATOMIC_ADD,"GLOBAL_ATOMIC_ADD"}, // 66 + {amdgpu_gfx908_op_GLOBAL_ATOMIC_SUB,"GLOBAL_ATOMIC_SUB"}, // 67 + {amdgpu_gfx908_op_GLOBAL_ATOMIC_SMIN,"GLOBAL_ATOMIC_SMIN"}, // 68 + {amdgpu_gfx908_op_GLOBAL_ATOMIC_UMIN,"GLOBAL_ATOMIC_UMIN"}, // 69 + {amdgpu_gfx908_op_GLOBAL_ATOMIC_SMAX,"GLOBAL_ATOMIC_SMAX"}, // 70 + {amdgpu_gfx908_op_GLOBAL_ATOMIC_UMAX,"GLOBAL_ATOMIC_UMAX"}, // 71 + {amdgpu_gfx908_op_GLOBAL_ATOMIC_AND,"GLOBAL_ATOMIC_AND"}, // 72 + {amdgpu_gfx908_op_GLOBAL_ATOMIC_OR,"GLOBAL_ATOMIC_OR"}, // 73 + {amdgpu_gfx908_op_GLOBAL_ATOMIC_XOR,"GLOBAL_ATOMIC_XOR"}, // 74 + {amdgpu_gfx908_op_GLOBAL_ATOMIC_INC,"GLOBAL_ATOMIC_INC"}, // 75 + {amdgpu_gfx908_op_GLOBAL_ATOMIC_DEC,"GLOBAL_ATOMIC_DEC"}, // 76 + {amdgpu_gfx908_op_GLOBAL_ATOMIC_ADD_F32,"GLOBAL_ATOMIC_ADD_F32"}, // 77 + {amdgpu_gfx908_op_GLOBAL_ATOMIC_PK_ADD_F16,"GLOBAL_ATOMIC_PK_ADD_F16"}, // 78 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 79 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 80 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 81 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 82 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 83 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 84 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 85 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 86 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 87 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 88 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 89 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 90 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 91 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 92 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 93 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 94 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 95 + {amdgpu_gfx908_op_GLOBAL_ATOMIC_SWAP_X2,"GLOBAL_ATOMIC_SWAP_X2"}, // 96 + {amdgpu_gfx908_op_GLOBAL_ATOMIC_CMPSWAP_X2,"GLOBAL_ATOMIC_CMPSWAP_X2"}, // 97 + {amdgpu_gfx908_op_GLOBAL_ATOMIC_ADD_X2,"GLOBAL_ATOMIC_ADD_X2"}, // 98 + {amdgpu_gfx908_op_GLOBAL_ATOMIC_SUB_X2,"GLOBAL_ATOMIC_SUB_X2"}, // 99 + {amdgpu_gfx908_op_GLOBAL_ATOMIC_SMIN_X2,"GLOBAL_ATOMIC_SMIN_X2"}, // 100 + {amdgpu_gfx908_op_GLOBAL_ATOMIC_UMIN_X2,"GLOBAL_ATOMIC_UMIN_X2"}, // 101 + {amdgpu_gfx908_op_GLOBAL_ATOMIC_SMAX_X2,"GLOBAL_ATOMIC_SMAX_X2"}, // 102 + {amdgpu_gfx908_op_GLOBAL_ATOMIC_UMAX_X2,"GLOBAL_ATOMIC_UMAX_X2"}, // 103 + {amdgpu_gfx908_op_GLOBAL_ATOMIC_AND_X2,"GLOBAL_ATOMIC_AND_X2"}, // 104 + {amdgpu_gfx908_op_GLOBAL_ATOMIC_OR_X2,"GLOBAL_ATOMIC_OR_X2"}, // 105 + {amdgpu_gfx908_op_GLOBAL_ATOMIC_XOR_X2,"GLOBAL_ATOMIC_XOR_X2"}, // 106 + {amdgpu_gfx908_op_GLOBAL_ATOMIC_INC_X2,"GLOBAL_ATOMIC_INC_X2"}, // 107 + {amdgpu_gfx908_op_GLOBAL_ATOMIC_DEC_X2,"GLOBAL_ATOMIC_DEC_X2"}, // 108 + }; // end ENC_FLAT_GLBL_insn_table + const amdgpu_gfx908_insn_entry ENC_FLAT_SCRATCH_insn_table[38] = + { + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 0 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 1 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 2 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 3 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 4 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 5 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 6 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 7 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 8 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 9 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 10 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 11 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 12 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 13 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 14 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 15 + {amdgpu_gfx908_op_SCRATCH_LOAD_UBYTE,"SCRATCH_LOAD_UBYTE"}, // 16 + {amdgpu_gfx908_op_SCRATCH_LOAD_SBYTE,"SCRATCH_LOAD_SBYTE"}, // 17 + {amdgpu_gfx908_op_SCRATCH_LOAD_USHORT,"SCRATCH_LOAD_USHORT"}, // 18 + {amdgpu_gfx908_op_SCRATCH_LOAD_SSHORT,"SCRATCH_LOAD_SSHORT"}, // 19 + {amdgpu_gfx908_op_SCRATCH_LOAD_DWORD,"SCRATCH_LOAD_DWORD"}, // 20 + {amdgpu_gfx908_op_SCRATCH_LOAD_DWORDX2,"SCRATCH_LOAD_DWORDX2"}, // 21 + {amdgpu_gfx908_op_SCRATCH_LOAD_DWORDX3,"SCRATCH_LOAD_DWORDX3"}, // 22 + {amdgpu_gfx908_op_SCRATCH_LOAD_DWORDX4,"SCRATCH_LOAD_DWORDX4"}, // 23 + {amdgpu_gfx908_op_SCRATCH_STORE_BYTE,"SCRATCH_STORE_BYTE"}, // 24 + {amdgpu_gfx908_op_SCRATCH_STORE_BYTE_D16_HI,"SCRATCH_STORE_BYTE_D16_HI"}, // 25 + {amdgpu_gfx908_op_SCRATCH_STORE_SHORT,"SCRATCH_STORE_SHORT"}, // 26 + {amdgpu_gfx908_op_SCRATCH_STORE_SHORT_D16_HI,"SCRATCH_STORE_SHORT_D16_HI"}, // 27 + {amdgpu_gfx908_op_SCRATCH_STORE_DWORD,"SCRATCH_STORE_DWORD"}, // 28 + {amdgpu_gfx908_op_SCRATCH_STORE_DWORDX2,"SCRATCH_STORE_DWORDX2"}, // 29 + {amdgpu_gfx908_op_SCRATCH_STORE_DWORDX3,"SCRATCH_STORE_DWORDX3"}, // 30 + {amdgpu_gfx908_op_SCRATCH_STORE_DWORDX4,"SCRATCH_STORE_DWORDX4"}, // 31 + {amdgpu_gfx908_op_SCRATCH_LOAD_UBYTE_D16,"SCRATCH_LOAD_UBYTE_D16"}, // 32 + {amdgpu_gfx908_op_SCRATCH_LOAD_UBYTE_D16_HI,"SCRATCH_LOAD_UBYTE_D16_HI"}, // 33 + {amdgpu_gfx908_op_SCRATCH_LOAD_SBYTE_D16,"SCRATCH_LOAD_SBYTE_D16"}, // 34 + {amdgpu_gfx908_op_SCRATCH_LOAD_SBYTE_D16_HI,"SCRATCH_LOAD_SBYTE_D16_HI"}, // 35 + {amdgpu_gfx908_op_SCRATCH_LOAD_SHORT_D16,"SCRATCH_LOAD_SHORT_D16"}, // 36 + {amdgpu_gfx908_op_SCRATCH_LOAD_SHORT_D16_HI,"SCRATCH_LOAD_SHORT_D16_HI"}, // 37 + }; // end ENC_FLAT_SCRATCH_insn_table + const amdgpu_gfx908_insn_entry ENC_MIMG_insn_table[112] = + { + {amdgpu_gfx908_op_IMAGE_LOAD,"IMAGE_LOAD"}, // 0 + {amdgpu_gfx908_op_IMAGE_LOAD_MIP,"IMAGE_LOAD_MIP"}, // 1 + {amdgpu_gfx908_op_IMAGE_LOAD_PCK,"IMAGE_LOAD_PCK"}, // 2 + {amdgpu_gfx908_op_IMAGE_LOAD_PCK_SGN,"IMAGE_LOAD_PCK_SGN"}, // 3 + {amdgpu_gfx908_op_IMAGE_LOAD_MIP_PCK,"IMAGE_LOAD_MIP_PCK"}, // 4 + {amdgpu_gfx908_op_IMAGE_LOAD_MIP_PCK_SGN,"IMAGE_LOAD_MIP_PCK_SGN"}, // 5 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 6 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 7 + {amdgpu_gfx908_op_IMAGE_STORE,"IMAGE_STORE"}, // 8 + {amdgpu_gfx908_op_IMAGE_STORE_MIP,"IMAGE_STORE_MIP"}, // 9 + {amdgpu_gfx908_op_IMAGE_STORE_PCK,"IMAGE_STORE_PCK"}, // 10 + {amdgpu_gfx908_op_IMAGE_STORE_MIP_PCK,"IMAGE_STORE_MIP_PCK"}, // 11 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 12 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 13 + {amdgpu_gfx908_op_IMAGE_GET_RESINFO,"IMAGE_GET_RESINFO"}, // 14 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 15 + {amdgpu_gfx908_op_IMAGE_ATOMIC_SWAP,"IMAGE_ATOMIC_SWAP"}, // 16 + {amdgpu_gfx908_op_IMAGE_ATOMIC_CMPSWAP,"IMAGE_ATOMIC_CMPSWAP"}, // 17 + {amdgpu_gfx908_op_IMAGE_ATOMIC_ADD,"IMAGE_ATOMIC_ADD"}, // 18 + {amdgpu_gfx908_op_IMAGE_ATOMIC_SUB,"IMAGE_ATOMIC_SUB"}, // 19 + {amdgpu_gfx908_op_IMAGE_ATOMIC_SMIN,"IMAGE_ATOMIC_SMIN"}, // 20 + {amdgpu_gfx908_op_IMAGE_ATOMIC_UMIN,"IMAGE_ATOMIC_UMIN"}, // 21 + {amdgpu_gfx908_op_IMAGE_ATOMIC_SMAX,"IMAGE_ATOMIC_SMAX"}, // 22 + {amdgpu_gfx908_op_IMAGE_ATOMIC_UMAX,"IMAGE_ATOMIC_UMAX"}, // 23 + {amdgpu_gfx908_op_IMAGE_ATOMIC_AND,"IMAGE_ATOMIC_AND"}, // 24 + {amdgpu_gfx908_op_IMAGE_ATOMIC_OR,"IMAGE_ATOMIC_OR"}, // 25 + {amdgpu_gfx908_op_IMAGE_ATOMIC_XOR,"IMAGE_ATOMIC_XOR"}, // 26 + {amdgpu_gfx908_op_IMAGE_ATOMIC_INC,"IMAGE_ATOMIC_INC"}, // 27 + {amdgpu_gfx908_op_IMAGE_ATOMIC_DEC,"IMAGE_ATOMIC_DEC"}, // 28 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 29 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 30 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 31 + {amdgpu_gfx908_op_IMAGE_SAMPLE,"IMAGE_SAMPLE"}, // 32 + {amdgpu_gfx908_op_IMAGE_SAMPLE_CL,"IMAGE_SAMPLE_CL"}, // 33 + {amdgpu_gfx908_op_IMAGE_SAMPLE_D,"IMAGE_SAMPLE_D"}, // 34 + {amdgpu_gfx908_op_IMAGE_SAMPLE_D_CL,"IMAGE_SAMPLE_D_CL"}, // 35 + {amdgpu_gfx908_op_IMAGE_SAMPLE_L,"IMAGE_SAMPLE_L"}, // 36 + {amdgpu_gfx908_op_IMAGE_SAMPLE_B,"IMAGE_SAMPLE_B"}, // 37 + {amdgpu_gfx908_op_IMAGE_SAMPLE_B_CL,"IMAGE_SAMPLE_B_CL"}, // 38 + {amdgpu_gfx908_op_IMAGE_SAMPLE_LZ,"IMAGE_SAMPLE_LZ"}, // 39 + {amdgpu_gfx908_op_IMAGE_SAMPLE_C,"IMAGE_SAMPLE_C"}, // 40 + {amdgpu_gfx908_op_IMAGE_SAMPLE_C_CL,"IMAGE_SAMPLE_C_CL"}, // 41 + {amdgpu_gfx908_op_IMAGE_SAMPLE_C_D,"IMAGE_SAMPLE_C_D"}, // 42 + {amdgpu_gfx908_op_IMAGE_SAMPLE_C_D_CL,"IMAGE_SAMPLE_C_D_CL"}, // 43 + {amdgpu_gfx908_op_IMAGE_SAMPLE_C_L,"IMAGE_SAMPLE_C_L"}, // 44 + {amdgpu_gfx908_op_IMAGE_SAMPLE_C_B,"IMAGE_SAMPLE_C_B"}, // 45 + {amdgpu_gfx908_op_IMAGE_SAMPLE_C_B_CL,"IMAGE_SAMPLE_C_B_CL"}, // 46 + {amdgpu_gfx908_op_IMAGE_SAMPLE_C_LZ,"IMAGE_SAMPLE_C_LZ"}, // 47 + {amdgpu_gfx908_op_IMAGE_SAMPLE_O,"IMAGE_SAMPLE_O"}, // 48 + {amdgpu_gfx908_op_IMAGE_SAMPLE_CL_O,"IMAGE_SAMPLE_CL_O"}, // 49 + {amdgpu_gfx908_op_IMAGE_SAMPLE_D_O,"IMAGE_SAMPLE_D_O"}, // 50 + {amdgpu_gfx908_op_IMAGE_SAMPLE_D_CL_O,"IMAGE_SAMPLE_D_CL_O"}, // 51 + {amdgpu_gfx908_op_IMAGE_SAMPLE_L_O,"IMAGE_SAMPLE_L_O"}, // 52 + {amdgpu_gfx908_op_IMAGE_SAMPLE_B_O,"IMAGE_SAMPLE_B_O"}, // 53 + {amdgpu_gfx908_op_IMAGE_SAMPLE_B_CL_O,"IMAGE_SAMPLE_B_CL_O"}, // 54 + {amdgpu_gfx908_op_IMAGE_SAMPLE_LZ_O,"IMAGE_SAMPLE_LZ_O"}, // 55 + {amdgpu_gfx908_op_IMAGE_SAMPLE_C_O,"IMAGE_SAMPLE_C_O"}, // 56 + {amdgpu_gfx908_op_IMAGE_SAMPLE_C_CL_O,"IMAGE_SAMPLE_C_CL_O"}, // 57 + {amdgpu_gfx908_op_IMAGE_SAMPLE_C_D_O,"IMAGE_SAMPLE_C_D_O"}, // 58 + {amdgpu_gfx908_op_IMAGE_SAMPLE_C_D_CL_O,"IMAGE_SAMPLE_C_D_CL_O"}, // 59 + {amdgpu_gfx908_op_IMAGE_SAMPLE_C_L_O,"IMAGE_SAMPLE_C_L_O"}, // 60 + {amdgpu_gfx908_op_IMAGE_SAMPLE_C_B_O,"IMAGE_SAMPLE_C_B_O"}, // 61 + {amdgpu_gfx908_op_IMAGE_SAMPLE_C_B_CL_O,"IMAGE_SAMPLE_C_B_CL_O"}, // 62 + {amdgpu_gfx908_op_IMAGE_SAMPLE_C_LZ_O,"IMAGE_SAMPLE_C_LZ_O"}, // 63 + {amdgpu_gfx908_op_IMAGE_GATHER4,"IMAGE_GATHER4"}, // 64 + {amdgpu_gfx908_op_IMAGE_GATHER4_CL,"IMAGE_GATHER4_CL"}, // 65 + {amdgpu_gfx908_op_IMAGE_GATHER4H,"IMAGE_GATHER4H"}, // 66 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 67 + {amdgpu_gfx908_op_IMAGE_GATHER4_L,"IMAGE_GATHER4_L"}, // 68 + {amdgpu_gfx908_op_IMAGE_GATHER4_B,"IMAGE_GATHER4_B"}, // 69 + {amdgpu_gfx908_op_IMAGE_GATHER4_B_CL,"IMAGE_GATHER4_B_CL"}, // 70 + {amdgpu_gfx908_op_IMAGE_GATHER4_LZ,"IMAGE_GATHER4_LZ"}, // 71 + {amdgpu_gfx908_op_IMAGE_GATHER4_C,"IMAGE_GATHER4_C"}, // 72 + {amdgpu_gfx908_op_IMAGE_GATHER4_C_CL,"IMAGE_GATHER4_C_CL"}, // 73 + {amdgpu_gfx908_op_IMAGE_GATHER4H_PCK,"IMAGE_GATHER4H_PCK"}, // 74 + {amdgpu_gfx908_op_IMAGE_GATHER8H_PCK,"IMAGE_GATHER8H_PCK"}, // 75 + {amdgpu_gfx908_op_IMAGE_GATHER4_C_L,"IMAGE_GATHER4_C_L"}, // 76 + {amdgpu_gfx908_op_IMAGE_GATHER4_C_B,"IMAGE_GATHER4_C_B"}, // 77 + {amdgpu_gfx908_op_IMAGE_GATHER4_C_B_CL,"IMAGE_GATHER4_C_B_CL"}, // 78 + {amdgpu_gfx908_op_IMAGE_GATHER4_C_LZ,"IMAGE_GATHER4_C_LZ"}, // 79 + {amdgpu_gfx908_op_IMAGE_GATHER4_O,"IMAGE_GATHER4_O"}, // 80 + {amdgpu_gfx908_op_IMAGE_GATHER4_CL_O,"IMAGE_GATHER4_CL_O"}, // 81 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 82 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 83 + {amdgpu_gfx908_op_IMAGE_GATHER4_L_O,"IMAGE_GATHER4_L_O"}, // 84 + {amdgpu_gfx908_op_IMAGE_GATHER4_B_O,"IMAGE_GATHER4_B_O"}, // 85 + {amdgpu_gfx908_op_IMAGE_GATHER4_B_CL_O,"IMAGE_GATHER4_B_CL_O"}, // 86 + {amdgpu_gfx908_op_IMAGE_GATHER4_LZ_O,"IMAGE_GATHER4_LZ_O"}, // 87 + {amdgpu_gfx908_op_IMAGE_GATHER4_C_O,"IMAGE_GATHER4_C_O"}, // 88 + {amdgpu_gfx908_op_IMAGE_GATHER4_C_CL_O,"IMAGE_GATHER4_C_CL_O"}, // 89 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 90 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 91 + {amdgpu_gfx908_op_IMAGE_GATHER4_C_L_O,"IMAGE_GATHER4_C_L_O"}, // 92 + {amdgpu_gfx908_op_IMAGE_GATHER4_C_B_O,"IMAGE_GATHER4_C_B_O"}, // 93 + {amdgpu_gfx908_op_IMAGE_GATHER4_C_B_CL_O,"IMAGE_GATHER4_C_B_CL_O"}, // 94 + {amdgpu_gfx908_op_IMAGE_GATHER4_C_LZ_O,"IMAGE_GATHER4_C_LZ_O"}, // 95 + {amdgpu_gfx908_op_IMAGE_GET_LOD,"IMAGE_GET_LOD"}, // 96 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 97 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 98 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 99 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 100 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 101 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 102 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 103 + {amdgpu_gfx908_op_IMAGE_SAMPLE_CD,"IMAGE_SAMPLE_CD"}, // 104 + {amdgpu_gfx908_op_IMAGE_SAMPLE_CD_CL,"IMAGE_SAMPLE_CD_CL"}, // 105 + {amdgpu_gfx908_op_IMAGE_SAMPLE_C_CD,"IMAGE_SAMPLE_C_CD"}, // 106 + {amdgpu_gfx908_op_IMAGE_SAMPLE_C_CD_CL,"IMAGE_SAMPLE_C_CD_CL"}, // 107 + {amdgpu_gfx908_op_IMAGE_SAMPLE_CD_O,"IMAGE_SAMPLE_CD_O"}, // 108 + {amdgpu_gfx908_op_IMAGE_SAMPLE_CD_CL_O,"IMAGE_SAMPLE_CD_CL_O"}, // 109 + {amdgpu_gfx908_op_IMAGE_SAMPLE_C_CD_O,"IMAGE_SAMPLE_C_CD_O"}, // 110 + {amdgpu_gfx908_op_IMAGE_SAMPLE_C_CD_CL_O,"IMAGE_SAMPLE_C_CD_CL_O"}, // 111 + }; // end ENC_MIMG_insn_table + const amdgpu_gfx908_insn_entry ENC_MTBUF_insn_table[16] = + { + {amdgpu_gfx908_op_TBUFFER_LOAD_FORMAT_X,"TBUFFER_LOAD_FORMAT_X"}, // 0 + {amdgpu_gfx908_op_TBUFFER_LOAD_FORMAT_XY,"TBUFFER_LOAD_FORMAT_XY"}, // 1 + {amdgpu_gfx908_op_TBUFFER_LOAD_FORMAT_XYZ,"TBUFFER_LOAD_FORMAT_XYZ"}, // 2 + {amdgpu_gfx908_op_TBUFFER_LOAD_FORMAT_XYZW,"TBUFFER_LOAD_FORMAT_XYZW"}, // 3 + {amdgpu_gfx908_op_TBUFFER_STORE_FORMAT_X,"TBUFFER_STORE_FORMAT_X"}, // 4 + {amdgpu_gfx908_op_TBUFFER_STORE_FORMAT_XY,"TBUFFER_STORE_FORMAT_XY"}, // 5 + {amdgpu_gfx908_op_TBUFFER_STORE_FORMAT_XYZ,"TBUFFER_STORE_FORMAT_XYZ"}, // 6 + {amdgpu_gfx908_op_TBUFFER_STORE_FORMAT_XYZW,"TBUFFER_STORE_FORMAT_XYZW"}, // 7 + {amdgpu_gfx908_op_TBUFFER_LOAD_FORMAT_D16_X,"TBUFFER_LOAD_FORMAT_D16_X"}, // 8 + {amdgpu_gfx908_op_TBUFFER_LOAD_FORMAT_D16_XY,"TBUFFER_LOAD_FORMAT_D16_XY"}, // 9 + {amdgpu_gfx908_op_TBUFFER_LOAD_FORMAT_D16_XYZ,"TBUFFER_LOAD_FORMAT_D16_XYZ"}, // 10 + {amdgpu_gfx908_op_TBUFFER_LOAD_FORMAT_D16_XYZW,"TBUFFER_LOAD_FORMAT_D16_XYZW"}, // 11 + {amdgpu_gfx908_op_TBUFFER_STORE_FORMAT_D16_X,"TBUFFER_STORE_FORMAT_D16_X"}, // 12 + {amdgpu_gfx908_op_TBUFFER_STORE_FORMAT_D16_XY,"TBUFFER_STORE_FORMAT_D16_XY"}, // 13 + {amdgpu_gfx908_op_TBUFFER_STORE_FORMAT_D16_XYZ,"TBUFFER_STORE_FORMAT_D16_XYZ"}, // 14 + {amdgpu_gfx908_op_TBUFFER_STORE_FORMAT_D16_XYZW,"TBUFFER_STORE_FORMAT_D16_XYZW"}, // 15 + }; // end ENC_MTBUF_insn_table + const amdgpu_gfx908_insn_entry ENC_MUBUF_insn_table[109] = + { + {amdgpu_gfx908_op_BUFFER_LOAD_FORMAT_X,"BUFFER_LOAD_FORMAT_X"}, // 0 + {amdgpu_gfx908_op_BUFFER_LOAD_FORMAT_XY,"BUFFER_LOAD_FORMAT_XY"}, // 1 + {amdgpu_gfx908_op_BUFFER_LOAD_FORMAT_XYZ,"BUFFER_LOAD_FORMAT_XYZ"}, // 2 + {amdgpu_gfx908_op_BUFFER_LOAD_FORMAT_XYZW,"BUFFER_LOAD_FORMAT_XYZW"}, // 3 + {amdgpu_gfx908_op_BUFFER_STORE_FORMAT_X,"BUFFER_STORE_FORMAT_X"}, // 4 + {amdgpu_gfx908_op_BUFFER_STORE_FORMAT_XY,"BUFFER_STORE_FORMAT_XY"}, // 5 + {amdgpu_gfx908_op_BUFFER_STORE_FORMAT_XYZ,"BUFFER_STORE_FORMAT_XYZ"}, // 6 + {amdgpu_gfx908_op_BUFFER_STORE_FORMAT_XYZW,"BUFFER_STORE_FORMAT_XYZW"}, // 7 + {amdgpu_gfx908_op_BUFFER_LOAD_FORMAT_D16_X,"BUFFER_LOAD_FORMAT_D16_X"}, // 8 + {amdgpu_gfx908_op_BUFFER_LOAD_FORMAT_D16_XY,"BUFFER_LOAD_FORMAT_D16_XY"}, // 9 + {amdgpu_gfx908_op_BUFFER_LOAD_FORMAT_D16_XYZ,"BUFFER_LOAD_FORMAT_D16_XYZ"}, // 10 + {amdgpu_gfx908_op_BUFFER_LOAD_FORMAT_D16_XYZW,"BUFFER_LOAD_FORMAT_D16_XYZW"}, // 11 + {amdgpu_gfx908_op_BUFFER_STORE_FORMAT_D16_X,"BUFFER_STORE_FORMAT_D16_X"}, // 12 + {amdgpu_gfx908_op_BUFFER_STORE_FORMAT_D16_XY,"BUFFER_STORE_FORMAT_D16_XY"}, // 13 + {amdgpu_gfx908_op_BUFFER_STORE_FORMAT_D16_XYZ,"BUFFER_STORE_FORMAT_D16_XYZ"}, // 14 + {amdgpu_gfx908_op_BUFFER_STORE_FORMAT_D16_XYZW,"BUFFER_STORE_FORMAT_D16_XYZW"}, // 15 + {amdgpu_gfx908_op_BUFFER_LOAD_UBYTE,"BUFFER_LOAD_UBYTE"}, // 16 + {amdgpu_gfx908_op_BUFFER_LOAD_SBYTE,"BUFFER_LOAD_SBYTE"}, // 17 + {amdgpu_gfx908_op_BUFFER_LOAD_USHORT,"BUFFER_LOAD_USHORT"}, // 18 + {amdgpu_gfx908_op_BUFFER_LOAD_SSHORT,"BUFFER_LOAD_SSHORT"}, // 19 + {amdgpu_gfx908_op_BUFFER_LOAD_DWORD,"BUFFER_LOAD_DWORD"}, // 20 + {amdgpu_gfx908_op_BUFFER_LOAD_DWORDX2,"BUFFER_LOAD_DWORDX2"}, // 21 + {amdgpu_gfx908_op_BUFFER_LOAD_DWORDX3,"BUFFER_LOAD_DWORDX3"}, // 22 + {amdgpu_gfx908_op_BUFFER_LOAD_DWORDX4,"BUFFER_LOAD_DWORDX4"}, // 23 + {amdgpu_gfx908_op_BUFFER_STORE_BYTE,"BUFFER_STORE_BYTE"}, // 24 + {amdgpu_gfx908_op_BUFFER_STORE_BYTE_D16_HI,"BUFFER_STORE_BYTE_D16_HI"}, // 25 + {amdgpu_gfx908_op_BUFFER_STORE_SHORT,"BUFFER_STORE_SHORT"}, // 26 + {amdgpu_gfx908_op_BUFFER_STORE_SHORT_D16_HI,"BUFFER_STORE_SHORT_D16_HI"}, // 27 + {amdgpu_gfx908_op_BUFFER_STORE_DWORD,"BUFFER_STORE_DWORD"}, // 28 + {amdgpu_gfx908_op_BUFFER_STORE_DWORDX2,"BUFFER_STORE_DWORDX2"}, // 29 + {amdgpu_gfx908_op_BUFFER_STORE_DWORDX3,"BUFFER_STORE_DWORDX3"}, // 30 + {amdgpu_gfx908_op_BUFFER_STORE_DWORDX4,"BUFFER_STORE_DWORDX4"}, // 31 + {amdgpu_gfx908_op_BUFFER_LOAD_UBYTE_D16,"BUFFER_LOAD_UBYTE_D16"}, // 32 + {amdgpu_gfx908_op_BUFFER_LOAD_UBYTE_D16_HI,"BUFFER_LOAD_UBYTE_D16_HI"}, // 33 + {amdgpu_gfx908_op_BUFFER_LOAD_SBYTE_D16,"BUFFER_LOAD_SBYTE_D16"}, // 34 + {amdgpu_gfx908_op_BUFFER_LOAD_SBYTE_D16_HI,"BUFFER_LOAD_SBYTE_D16_HI"}, // 35 + {amdgpu_gfx908_op_BUFFER_LOAD_SHORT_D16,"BUFFER_LOAD_SHORT_D16"}, // 36 + {amdgpu_gfx908_op_BUFFER_LOAD_SHORT_D16_HI,"BUFFER_LOAD_SHORT_D16_HI"}, // 37 + {amdgpu_gfx908_op_BUFFER_LOAD_FORMAT_D16_HI_X,"BUFFER_LOAD_FORMAT_D16_HI_X"}, // 38 + {amdgpu_gfx908_op_BUFFER_STORE_FORMAT_D16_HI_X,"BUFFER_STORE_FORMAT_D16_HI_X"}, // 39 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 40 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 41 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 42 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 43 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 44 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 45 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 46 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 47 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 48 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 49 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 50 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 51 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 52 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 53 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 54 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 55 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 56 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 57 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 58 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 59 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 60 + {amdgpu_gfx908_op_BUFFER_STORE_LDS_DWORD,"BUFFER_STORE_LDS_DWORD"}, // 61 + {amdgpu_gfx908_op_BUFFER_WBINVL1,"BUFFER_WBINVL1"}, // 62 + {amdgpu_gfx908_op_BUFFER_WBINVL1_VOL,"BUFFER_WBINVL1_VOL"}, // 63 + {amdgpu_gfx908_op_BUFFER_ATOMIC_SWAP,"BUFFER_ATOMIC_SWAP"}, // 64 + {amdgpu_gfx908_op_BUFFER_ATOMIC_CMPSWAP,"BUFFER_ATOMIC_CMPSWAP"}, // 65 + {amdgpu_gfx908_op_BUFFER_ATOMIC_ADD,"BUFFER_ATOMIC_ADD"}, // 66 + {amdgpu_gfx908_op_BUFFER_ATOMIC_SUB,"BUFFER_ATOMIC_SUB"}, // 67 + {amdgpu_gfx908_op_BUFFER_ATOMIC_SMIN,"BUFFER_ATOMIC_SMIN"}, // 68 + {amdgpu_gfx908_op_BUFFER_ATOMIC_UMIN,"BUFFER_ATOMIC_UMIN"}, // 69 + {amdgpu_gfx908_op_BUFFER_ATOMIC_SMAX,"BUFFER_ATOMIC_SMAX"}, // 70 + {amdgpu_gfx908_op_BUFFER_ATOMIC_UMAX,"BUFFER_ATOMIC_UMAX"}, // 71 + {amdgpu_gfx908_op_BUFFER_ATOMIC_AND,"BUFFER_ATOMIC_AND"}, // 72 + {amdgpu_gfx908_op_BUFFER_ATOMIC_OR,"BUFFER_ATOMIC_OR"}, // 73 + {amdgpu_gfx908_op_BUFFER_ATOMIC_XOR,"BUFFER_ATOMIC_XOR"}, // 74 + {amdgpu_gfx908_op_BUFFER_ATOMIC_INC,"BUFFER_ATOMIC_INC"}, // 75 + {amdgpu_gfx908_op_BUFFER_ATOMIC_DEC,"BUFFER_ATOMIC_DEC"}, // 76 + {amdgpu_gfx908_op_BUFFER_ATOMIC_ADD_F32,"BUFFER_ATOMIC_ADD_F32"}, // 77 + {amdgpu_gfx908_op_BUFFER_ATOMIC_PK_ADD_F16,"BUFFER_ATOMIC_PK_ADD_F16"}, // 78 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 79 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 80 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 81 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 82 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 83 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 84 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 85 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 86 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 87 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 88 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 89 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 90 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 91 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 92 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 93 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 94 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 95 + {amdgpu_gfx908_op_BUFFER_ATOMIC_SWAP_X2,"BUFFER_ATOMIC_SWAP_X2"}, // 96 + {amdgpu_gfx908_op_BUFFER_ATOMIC_CMPSWAP_X2,"BUFFER_ATOMIC_CMPSWAP_X2"}, // 97 + {amdgpu_gfx908_op_BUFFER_ATOMIC_ADD_X2,"BUFFER_ATOMIC_ADD_X2"}, // 98 + {amdgpu_gfx908_op_BUFFER_ATOMIC_SUB_X2,"BUFFER_ATOMIC_SUB_X2"}, // 99 + {amdgpu_gfx908_op_BUFFER_ATOMIC_SMIN_X2,"BUFFER_ATOMIC_SMIN_X2"}, // 100 + {amdgpu_gfx908_op_BUFFER_ATOMIC_UMIN_X2,"BUFFER_ATOMIC_UMIN_X2"}, // 101 + {amdgpu_gfx908_op_BUFFER_ATOMIC_SMAX_X2,"BUFFER_ATOMIC_SMAX_X2"}, // 102 + {amdgpu_gfx908_op_BUFFER_ATOMIC_UMAX_X2,"BUFFER_ATOMIC_UMAX_X2"}, // 103 + {amdgpu_gfx908_op_BUFFER_ATOMIC_AND_X2,"BUFFER_ATOMIC_AND_X2"}, // 104 + {amdgpu_gfx908_op_BUFFER_ATOMIC_OR_X2,"BUFFER_ATOMIC_OR_X2"}, // 105 + {amdgpu_gfx908_op_BUFFER_ATOMIC_XOR_X2,"BUFFER_ATOMIC_XOR_X2"}, // 106 + {amdgpu_gfx908_op_BUFFER_ATOMIC_INC_X2,"BUFFER_ATOMIC_INC_X2"}, // 107 + {amdgpu_gfx908_op_BUFFER_ATOMIC_DEC_X2,"BUFFER_ATOMIC_DEC_X2"}, // 108 + }; // end ENC_MUBUF_insn_table + const amdgpu_gfx908_insn_entry ENC_SMEM_insn_table[173] = + { + {amdgpu_gfx908_op_S_LOAD_DWORD,"S_LOAD_DWORD"}, // 0 + {amdgpu_gfx908_op_S_LOAD_DWORDX2,"S_LOAD_DWORDX2"}, // 1 + {amdgpu_gfx908_op_S_LOAD_DWORDX4,"S_LOAD_DWORDX4"}, // 2 + {amdgpu_gfx908_op_S_LOAD_DWORDX8,"S_LOAD_DWORDX8"}, // 3 + {amdgpu_gfx908_op_S_LOAD_DWORDX16,"S_LOAD_DWORDX16"}, // 4 + {amdgpu_gfx908_op_S_SCRATCH_LOAD_DWORD,"S_SCRATCH_LOAD_DWORD"}, // 5 + {amdgpu_gfx908_op_S_SCRATCH_LOAD_DWORDX2,"S_SCRATCH_LOAD_DWORDX2"}, // 6 + {amdgpu_gfx908_op_S_SCRATCH_LOAD_DWORDX4,"S_SCRATCH_LOAD_DWORDX4"}, // 7 + {amdgpu_gfx908_op_S_BUFFER_LOAD_DWORD,"S_BUFFER_LOAD_DWORD"}, // 8 + {amdgpu_gfx908_op_S_BUFFER_LOAD_DWORDX2,"S_BUFFER_LOAD_DWORDX2"}, // 9 + {amdgpu_gfx908_op_S_BUFFER_LOAD_DWORDX4,"S_BUFFER_LOAD_DWORDX4"}, // 10 + {amdgpu_gfx908_op_S_BUFFER_LOAD_DWORDX8,"S_BUFFER_LOAD_DWORDX8"}, // 11 + {amdgpu_gfx908_op_S_BUFFER_LOAD_DWORDX16,"S_BUFFER_LOAD_DWORDX16"}, // 12 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 13 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 14 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 15 + {amdgpu_gfx908_op_S_STORE_DWORD,"S_STORE_DWORD"}, // 16 + {amdgpu_gfx908_op_S_STORE_DWORDX2,"S_STORE_DWORDX2"}, // 17 + {amdgpu_gfx908_op_S_STORE_DWORDX4,"S_STORE_DWORDX4"}, // 18 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 19 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 20 + {amdgpu_gfx908_op_S_SCRATCH_STORE_DWORD,"S_SCRATCH_STORE_DWORD"}, // 21 + {amdgpu_gfx908_op_S_SCRATCH_STORE_DWORDX2,"S_SCRATCH_STORE_DWORDX2"}, // 22 + {amdgpu_gfx908_op_S_SCRATCH_STORE_DWORDX4,"S_SCRATCH_STORE_DWORDX4"}, // 23 + {amdgpu_gfx908_op_S_BUFFER_STORE_DWORD,"S_BUFFER_STORE_DWORD"}, // 24 + {amdgpu_gfx908_op_S_BUFFER_STORE_DWORDX2,"S_BUFFER_STORE_DWORDX2"}, // 25 + {amdgpu_gfx908_op_S_BUFFER_STORE_DWORDX4,"S_BUFFER_STORE_DWORDX4"}, // 26 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 27 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 28 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 29 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 30 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 31 + {amdgpu_gfx908_op_S_DCACHE_INV,"S_DCACHE_INV"}, // 32 + {amdgpu_gfx908_op_S_DCACHE_WB,"S_DCACHE_WB"}, // 33 + {amdgpu_gfx908_op_S_DCACHE_INV_VOL,"S_DCACHE_INV_VOL"}, // 34 + {amdgpu_gfx908_op_S_DCACHE_WB_VOL,"S_DCACHE_WB_VOL"}, // 35 + {amdgpu_gfx908_op_S_MEMTIME,"S_MEMTIME"}, // 36 + {amdgpu_gfx908_op_S_MEMREALTIME,"S_MEMREALTIME"}, // 37 + {amdgpu_gfx908_op_S_ATC_PROBE,"S_ATC_PROBE"}, // 38 + {amdgpu_gfx908_op_S_ATC_PROBE_BUFFER,"S_ATC_PROBE_BUFFER"}, // 39 + {amdgpu_gfx908_op_S_DCACHE_DISCARD,"S_DCACHE_DISCARD"}, // 40 + {amdgpu_gfx908_op_S_DCACHE_DISCARD_X2,"S_DCACHE_DISCARD_X2"}, // 41 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 42 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 43 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 44 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 45 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 46 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 47 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 48 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 49 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 50 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 51 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 52 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 53 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 54 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 55 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 56 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 57 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 58 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 59 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 60 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 61 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 62 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 63 + {amdgpu_gfx908_op_S_BUFFER_ATOMIC_SWAP,"S_BUFFER_ATOMIC_SWAP"}, // 64 + {amdgpu_gfx908_op_S_BUFFER_ATOMIC_CMPSWAP,"S_BUFFER_ATOMIC_CMPSWAP"}, // 65 + {amdgpu_gfx908_op_S_BUFFER_ATOMIC_ADD,"S_BUFFER_ATOMIC_ADD"}, // 66 + {amdgpu_gfx908_op_S_BUFFER_ATOMIC_SUB,"S_BUFFER_ATOMIC_SUB"}, // 67 + {amdgpu_gfx908_op_S_BUFFER_ATOMIC_SMIN,"S_BUFFER_ATOMIC_SMIN"}, // 68 + {amdgpu_gfx908_op_S_BUFFER_ATOMIC_UMIN,"S_BUFFER_ATOMIC_UMIN"}, // 69 + {amdgpu_gfx908_op_S_BUFFER_ATOMIC_SMAX,"S_BUFFER_ATOMIC_SMAX"}, // 70 + {amdgpu_gfx908_op_S_BUFFER_ATOMIC_UMAX,"S_BUFFER_ATOMIC_UMAX"}, // 71 + {amdgpu_gfx908_op_S_BUFFER_ATOMIC_AND,"S_BUFFER_ATOMIC_AND"}, // 72 + {amdgpu_gfx908_op_S_BUFFER_ATOMIC_OR,"S_BUFFER_ATOMIC_OR"}, // 73 + {amdgpu_gfx908_op_S_BUFFER_ATOMIC_XOR,"S_BUFFER_ATOMIC_XOR"}, // 74 + {amdgpu_gfx908_op_S_BUFFER_ATOMIC_INC,"S_BUFFER_ATOMIC_INC"}, // 75 + {amdgpu_gfx908_op_S_BUFFER_ATOMIC_DEC,"S_BUFFER_ATOMIC_DEC"}, // 76 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 77 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 78 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 79 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 80 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 81 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 82 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 83 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 84 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 85 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 86 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 87 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 88 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 89 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 90 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 91 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 92 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 93 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 94 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 95 + {amdgpu_gfx908_op_S_BUFFER_ATOMIC_SWAP_X2,"S_BUFFER_ATOMIC_SWAP_X2"}, // 96 + {amdgpu_gfx908_op_S_BUFFER_ATOMIC_CMPSWAP_X2,"S_BUFFER_ATOMIC_CMPSWAP_X2"}, // 97 + {amdgpu_gfx908_op_S_BUFFER_ATOMIC_ADD_X2,"S_BUFFER_ATOMIC_ADD_X2"}, // 98 + {amdgpu_gfx908_op_S_BUFFER_ATOMIC_SUB_X2,"S_BUFFER_ATOMIC_SUB_X2"}, // 99 + {amdgpu_gfx908_op_S_BUFFER_ATOMIC_SMIN_X2,"S_BUFFER_ATOMIC_SMIN_X2"}, // 100 + {amdgpu_gfx908_op_S_BUFFER_ATOMIC_UMIN_X2,"S_BUFFER_ATOMIC_UMIN_X2"}, // 101 + {amdgpu_gfx908_op_S_BUFFER_ATOMIC_SMAX_X2,"S_BUFFER_ATOMIC_SMAX_X2"}, // 102 + {amdgpu_gfx908_op_S_BUFFER_ATOMIC_UMAX_X2,"S_BUFFER_ATOMIC_UMAX_X2"}, // 103 + {amdgpu_gfx908_op_S_BUFFER_ATOMIC_AND_X2,"S_BUFFER_ATOMIC_AND_X2"}, // 104 + {amdgpu_gfx908_op_S_BUFFER_ATOMIC_OR_X2,"S_BUFFER_ATOMIC_OR_X2"}, // 105 + {amdgpu_gfx908_op_S_BUFFER_ATOMIC_XOR_X2,"S_BUFFER_ATOMIC_XOR_X2"}, // 106 + {amdgpu_gfx908_op_S_BUFFER_ATOMIC_INC_X2,"S_BUFFER_ATOMIC_INC_X2"}, // 107 + {amdgpu_gfx908_op_S_BUFFER_ATOMIC_DEC_X2,"S_BUFFER_ATOMIC_DEC_X2"}, // 108 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 109 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 110 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 111 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 112 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 113 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 114 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 115 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 116 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 117 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 118 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 119 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 120 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 121 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 122 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 123 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 124 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 125 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 126 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 127 + {amdgpu_gfx908_op_S_ATOMIC_SWAP,"S_ATOMIC_SWAP"}, // 128 + {amdgpu_gfx908_op_S_ATOMIC_CMPSWAP,"S_ATOMIC_CMPSWAP"}, // 129 + {amdgpu_gfx908_op_S_ATOMIC_ADD,"S_ATOMIC_ADD"}, // 130 + {amdgpu_gfx908_op_S_ATOMIC_SUB,"S_ATOMIC_SUB"}, // 131 + {amdgpu_gfx908_op_S_ATOMIC_SMIN,"S_ATOMIC_SMIN"}, // 132 + {amdgpu_gfx908_op_S_ATOMIC_UMIN,"S_ATOMIC_UMIN"}, // 133 + {amdgpu_gfx908_op_S_ATOMIC_SMAX,"S_ATOMIC_SMAX"}, // 134 + {amdgpu_gfx908_op_S_ATOMIC_UMAX,"S_ATOMIC_UMAX"}, // 135 + {amdgpu_gfx908_op_S_ATOMIC_AND,"S_ATOMIC_AND"}, // 136 + {amdgpu_gfx908_op_S_ATOMIC_OR,"S_ATOMIC_OR"}, // 137 + {amdgpu_gfx908_op_S_ATOMIC_XOR,"S_ATOMIC_XOR"}, // 138 + {amdgpu_gfx908_op_S_ATOMIC_INC,"S_ATOMIC_INC"}, // 139 + {amdgpu_gfx908_op_S_ATOMIC_DEC,"S_ATOMIC_DEC"}, // 140 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 141 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 142 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 143 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 144 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 145 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 146 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 147 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 148 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 149 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 150 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 151 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 152 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 153 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 154 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 155 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 156 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 157 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 158 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 159 + {amdgpu_gfx908_op_S_ATOMIC_SWAP_X2,"S_ATOMIC_SWAP_X2"}, // 160 + {amdgpu_gfx908_op_S_ATOMIC_CMPSWAP_X2,"S_ATOMIC_CMPSWAP_X2"}, // 161 + {amdgpu_gfx908_op_S_ATOMIC_ADD_X2,"S_ATOMIC_ADD_X2"}, // 162 + {amdgpu_gfx908_op_S_ATOMIC_SUB_X2,"S_ATOMIC_SUB_X2"}, // 163 + {amdgpu_gfx908_op_S_ATOMIC_SMIN_X2,"S_ATOMIC_SMIN_X2"}, // 164 + {amdgpu_gfx908_op_S_ATOMIC_UMIN_X2,"S_ATOMIC_UMIN_X2"}, // 165 + {amdgpu_gfx908_op_S_ATOMIC_SMAX_X2,"S_ATOMIC_SMAX_X2"}, // 166 + {amdgpu_gfx908_op_S_ATOMIC_UMAX_X2,"S_ATOMIC_UMAX_X2"}, // 167 + {amdgpu_gfx908_op_S_ATOMIC_AND_X2,"S_ATOMIC_AND_X2"}, // 168 + {amdgpu_gfx908_op_S_ATOMIC_OR_X2,"S_ATOMIC_OR_X2"}, // 169 + {amdgpu_gfx908_op_S_ATOMIC_XOR_X2,"S_ATOMIC_XOR_X2"}, // 170 + {amdgpu_gfx908_op_S_ATOMIC_INC_X2,"S_ATOMIC_INC_X2"}, // 171 + {amdgpu_gfx908_op_S_ATOMIC_DEC_X2,"S_ATOMIC_DEC_X2"}, // 172 + }; // end ENC_SMEM_insn_table + const amdgpu_gfx908_insn_entry ENC_SOP1_insn_table[56] = + { + {amdgpu_gfx908_op_S_MOV_B32,"S_MOV_B32"}, // 0 + {amdgpu_gfx908_op_S_MOV_B64,"S_MOV_B64"}, // 1 + {amdgpu_gfx908_op_S_CMOV_B32,"S_CMOV_B32"}, // 2 + {amdgpu_gfx908_op_S_CMOV_B64,"S_CMOV_B64"}, // 3 + {amdgpu_gfx908_op_S_NOT_B32,"S_NOT_B32"}, // 4 + {amdgpu_gfx908_op_S_NOT_B64,"S_NOT_B64"}, // 5 + {amdgpu_gfx908_op_S_WQM_B32,"S_WQM_B32"}, // 6 + {amdgpu_gfx908_op_S_WQM_B64,"S_WQM_B64"}, // 7 + {amdgpu_gfx908_op_S_BREV_B32,"S_BREV_B32"}, // 8 + {amdgpu_gfx908_op_S_BREV_B64,"S_BREV_B64"}, // 9 + {amdgpu_gfx908_op_S_BCNT0_I32_B32,"S_BCNT0_I32_B32"}, // 10 + {amdgpu_gfx908_op_S_BCNT0_I32_B64,"S_BCNT0_I32_B64"}, // 11 + {amdgpu_gfx908_op_S_BCNT1_I32_B32,"S_BCNT1_I32_B32"}, // 12 + {amdgpu_gfx908_op_S_BCNT1_I32_B64,"S_BCNT1_I32_B64"}, // 13 + {amdgpu_gfx908_op_S_FF0_I32_B32,"S_FF0_I32_B32"}, // 14 + {amdgpu_gfx908_op_S_FF0_I32_B64,"S_FF0_I32_B64"}, // 15 + {amdgpu_gfx908_op_S_FF1_I32_B32,"S_FF1_I32_B32"}, // 16 + {amdgpu_gfx908_op_S_FF1_I32_B64,"S_FF1_I32_B64"}, // 17 + {amdgpu_gfx908_op_S_FLBIT_I32_B32,"S_FLBIT_I32_B32"}, // 18 + {amdgpu_gfx908_op_S_FLBIT_I32_B64,"S_FLBIT_I32_B64"}, // 19 + {amdgpu_gfx908_op_S_FLBIT_I32,"S_FLBIT_I32"}, // 20 + {amdgpu_gfx908_op_S_FLBIT_I32_I64,"S_FLBIT_I32_I64"}, // 21 + {amdgpu_gfx908_op_S_SEXT_I32_I8,"S_SEXT_I32_I8"}, // 22 + {amdgpu_gfx908_op_S_SEXT_I32_I16,"S_SEXT_I32_I16"}, // 23 + {amdgpu_gfx908_op_S_BITSET0_B32,"S_BITSET0_B32"}, // 24 + {amdgpu_gfx908_op_S_BITSET0_B64,"S_BITSET0_B64"}, // 25 + {amdgpu_gfx908_op_S_BITSET1_B32,"S_BITSET1_B32"}, // 26 + {amdgpu_gfx908_op_S_BITSET1_B64,"S_BITSET1_B64"}, // 27 + {amdgpu_gfx908_op_S_GETPC_B64,"S_GETPC_B64"}, // 28 + {amdgpu_gfx908_op_S_SETPC_B64,"S_SETPC_B64"}, // 29 + {amdgpu_gfx908_op_S_SWAPPC_B64,"S_SWAPPC_B64"}, // 30 + {amdgpu_gfx908_op_S_RFE_B64,"S_RFE_B64"}, // 31 + {amdgpu_gfx908_op_S_AND_SAVEEXEC_B64,"S_AND_SAVEEXEC_B64"}, // 32 + {amdgpu_gfx908_op_S_OR_SAVEEXEC_B64,"S_OR_SAVEEXEC_B64"}, // 33 + {amdgpu_gfx908_op_S_XOR_SAVEEXEC_B64,"S_XOR_SAVEEXEC_B64"}, // 34 + {amdgpu_gfx908_op_S_ANDN2_SAVEEXEC_B64,"S_ANDN2_SAVEEXEC_B64"}, // 35 + {amdgpu_gfx908_op_S_ORN2_SAVEEXEC_B64,"S_ORN2_SAVEEXEC_B64"}, // 36 + {amdgpu_gfx908_op_S_NAND_SAVEEXEC_B64,"S_NAND_SAVEEXEC_B64"}, // 37 + {amdgpu_gfx908_op_S_NOR_SAVEEXEC_B64,"S_NOR_SAVEEXEC_B64"}, // 38 + {amdgpu_gfx908_op_S_XNOR_SAVEEXEC_B64,"S_XNOR_SAVEEXEC_B64"}, // 39 + {amdgpu_gfx908_op_S_QUADMASK_B32,"S_QUADMASK_B32"}, // 40 + {amdgpu_gfx908_op_S_QUADMASK_B64,"S_QUADMASK_B64"}, // 41 + {amdgpu_gfx908_op_S_MOVRELS_B32,"S_MOVRELS_B32"}, // 42 + {amdgpu_gfx908_op_S_MOVRELS_B64,"S_MOVRELS_B64"}, // 43 + {amdgpu_gfx908_op_S_MOVRELD_B32,"S_MOVRELD_B32"}, // 44 + {amdgpu_gfx908_op_S_MOVRELD_B64,"S_MOVRELD_B64"}, // 45 + {amdgpu_gfx908_op_S_CBRANCH_JOIN,"S_CBRANCH_JOIN"}, // 46 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 47 + {amdgpu_gfx908_op_S_ABS_I32,"S_ABS_I32"}, // 48 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 49 + {amdgpu_gfx908_op_S_SET_GPR_IDX_IDX,"S_SET_GPR_IDX_IDX"}, // 50 + {amdgpu_gfx908_op_S_ANDN1_SAVEEXEC_B64,"S_ANDN1_SAVEEXEC_B64"}, // 51 + {amdgpu_gfx908_op_S_ORN1_SAVEEXEC_B64,"S_ORN1_SAVEEXEC_B64"}, // 52 + {amdgpu_gfx908_op_S_ANDN1_WREXEC_B64,"S_ANDN1_WREXEC_B64"}, // 53 + {amdgpu_gfx908_op_S_ANDN2_WREXEC_B64,"S_ANDN2_WREXEC_B64"}, // 54 + {amdgpu_gfx908_op_S_BITREPLICATE_B64_B32,"S_BITREPLICATE_B64_B32"}, // 55 + }; // end ENC_SOP1_insn_table + const amdgpu_gfx908_insn_entry ENC_SOP2_insn_table[53] = + { + {amdgpu_gfx908_op_S_ADD_U32,"S_ADD_U32"}, // 0 + {amdgpu_gfx908_op_S_SUB_U32,"S_SUB_U32"}, // 1 + {amdgpu_gfx908_op_S_ADD_I32,"S_ADD_I32"}, // 2 + {amdgpu_gfx908_op_S_SUB_I32,"S_SUB_I32"}, // 3 + {amdgpu_gfx908_op_S_ADDC_U32,"S_ADDC_U32"}, // 4 + {amdgpu_gfx908_op_S_SUBB_U32,"S_SUBB_U32"}, // 5 + {amdgpu_gfx908_op_S_MIN_I32,"S_MIN_I32"}, // 6 + {amdgpu_gfx908_op_S_MIN_U32,"S_MIN_U32"}, // 7 + {amdgpu_gfx908_op_S_MAX_I32,"S_MAX_I32"}, // 8 + {amdgpu_gfx908_op_S_MAX_U32,"S_MAX_U32"}, // 9 + {amdgpu_gfx908_op_S_CSELECT_B32,"S_CSELECT_B32"}, // 10 + {amdgpu_gfx908_op_S_CSELECT_B64,"S_CSELECT_B64"}, // 11 + {amdgpu_gfx908_op_S_AND_B32,"S_AND_B32"}, // 12 + {amdgpu_gfx908_op_S_AND_B64,"S_AND_B64"}, // 13 + {amdgpu_gfx908_op_S_OR_B32,"S_OR_B32"}, // 14 + {amdgpu_gfx908_op_S_OR_B64,"S_OR_B64"}, // 15 + {amdgpu_gfx908_op_S_XOR_B32,"S_XOR_B32"}, // 16 + {amdgpu_gfx908_op_S_XOR_B64,"S_XOR_B64"}, // 17 + {amdgpu_gfx908_op_S_ANDN2_B32,"S_ANDN2_B32"}, // 18 + {amdgpu_gfx908_op_S_ANDN2_B64,"S_ANDN2_B64"}, // 19 + {amdgpu_gfx908_op_S_ORN2_B32,"S_ORN2_B32"}, // 20 + {amdgpu_gfx908_op_S_ORN2_B64,"S_ORN2_B64"}, // 21 + {amdgpu_gfx908_op_S_NAND_B32,"S_NAND_B32"}, // 22 + {amdgpu_gfx908_op_S_NAND_B64,"S_NAND_B64"}, // 23 + {amdgpu_gfx908_op_S_NOR_B32,"S_NOR_B32"}, // 24 + {amdgpu_gfx908_op_S_NOR_B64,"S_NOR_B64"}, // 25 + {amdgpu_gfx908_op_S_XNOR_B32,"S_XNOR_B32"}, // 26 + {amdgpu_gfx908_op_S_XNOR_B64,"S_XNOR_B64"}, // 27 + {amdgpu_gfx908_op_S_LSHL_B32,"S_LSHL_B32"}, // 28 + {amdgpu_gfx908_op_S_LSHL_B64,"S_LSHL_B64"}, // 29 + {amdgpu_gfx908_op_S_LSHR_B32,"S_LSHR_B32"}, // 30 + {amdgpu_gfx908_op_S_LSHR_B64,"S_LSHR_B64"}, // 31 + {amdgpu_gfx908_op_S_ASHR_I32,"S_ASHR_I32"}, // 32 + {amdgpu_gfx908_op_S_ASHR_I64,"S_ASHR_I64"}, // 33 + {amdgpu_gfx908_op_S_BFM_B32,"S_BFM_B32"}, // 34 + {amdgpu_gfx908_op_S_BFM_B64,"S_BFM_B64"}, // 35 + {amdgpu_gfx908_op_S_MUL_I32,"S_MUL_I32"}, // 36 + {amdgpu_gfx908_op_S_BFE_U32,"S_BFE_U32"}, // 37 + {amdgpu_gfx908_op_S_BFE_I32,"S_BFE_I32"}, // 38 + {amdgpu_gfx908_op_S_BFE_U64,"S_BFE_U64"}, // 39 + {amdgpu_gfx908_op_S_BFE_I64,"S_BFE_I64"}, // 40 + {amdgpu_gfx908_op_S_CBRANCH_G_FORK,"S_CBRANCH_G_FORK"}, // 41 + {amdgpu_gfx908_op_S_ABSDIFF_I32,"S_ABSDIFF_I32"}, // 42 + {amdgpu_gfx908_op_S_RFE_RESTORE_B64,"S_RFE_RESTORE_B64"}, // 43 + {amdgpu_gfx908_op_S_MUL_HI_U32,"S_MUL_HI_U32"}, // 44 + {amdgpu_gfx908_op_S_MUL_HI_I32,"S_MUL_HI_I32"}, // 45 + {amdgpu_gfx908_op_S_LSHL1_ADD_U32,"S_LSHL1_ADD_U32"}, // 46 + {amdgpu_gfx908_op_S_LSHL2_ADD_U32,"S_LSHL2_ADD_U32"}, // 47 + {amdgpu_gfx908_op_S_LSHL3_ADD_U32,"S_LSHL3_ADD_U32"}, // 48 + {amdgpu_gfx908_op_S_LSHL4_ADD_U32,"S_LSHL4_ADD_U32"}, // 49 + {amdgpu_gfx908_op_S_PACK_LL_B32_B16,"S_PACK_LL_B32_B16"}, // 50 + {amdgpu_gfx908_op_S_PACK_LH_B32_B16,"S_PACK_LH_B32_B16"}, // 51 + {amdgpu_gfx908_op_S_PACK_HH_B32_B16,"S_PACK_HH_B32_B16"}, // 52 + }; // end ENC_SOP2_insn_table + const amdgpu_gfx908_insn_entry ENC_SOPC_insn_table[20] = + { + {amdgpu_gfx908_op_S_CMP_EQ_I32,"S_CMP_EQ_I32"}, // 0 + {amdgpu_gfx908_op_S_CMP_LG_I32,"S_CMP_LG_I32"}, // 1 + {amdgpu_gfx908_op_S_CMP_GT_I32,"S_CMP_GT_I32"}, // 2 + {amdgpu_gfx908_op_S_CMP_GE_I32,"S_CMP_GE_I32"}, // 3 + {amdgpu_gfx908_op_S_CMP_LT_I32,"S_CMP_LT_I32"}, // 4 + {amdgpu_gfx908_op_S_CMP_LE_I32,"S_CMP_LE_I32"}, // 5 + {amdgpu_gfx908_op_S_CMP_EQ_U32,"S_CMP_EQ_U32"}, // 6 + {amdgpu_gfx908_op_S_CMP_LG_U32,"S_CMP_LG_U32"}, // 7 + {amdgpu_gfx908_op_S_CMP_GT_U32,"S_CMP_GT_U32"}, // 8 + {amdgpu_gfx908_op_S_CMP_GE_U32,"S_CMP_GE_U32"}, // 9 + {amdgpu_gfx908_op_S_CMP_LT_U32,"S_CMP_LT_U32"}, // 10 + {amdgpu_gfx908_op_S_CMP_LE_U32,"S_CMP_LE_U32"}, // 11 + {amdgpu_gfx908_op_S_BITCMP0_B32,"S_BITCMP0_B32"}, // 12 + {amdgpu_gfx908_op_S_BITCMP1_B32,"S_BITCMP1_B32"}, // 13 + {amdgpu_gfx908_op_S_BITCMP0_B64,"S_BITCMP0_B64"}, // 14 + {amdgpu_gfx908_op_S_BITCMP1_B64,"S_BITCMP1_B64"}, // 15 + {amdgpu_gfx908_op_S_SETVSKIP,"S_SETVSKIP"}, // 16 + {amdgpu_gfx908_op_S_SET_GPR_IDX_ON,"S_SET_GPR_IDX_ON"}, // 17 + {amdgpu_gfx908_op_S_CMP_EQ_U64,"S_CMP_EQ_U64"}, // 18 + {amdgpu_gfx908_op_S_CMP_LG_U64,"S_CMP_LG_U64"}, // 19 + }; // end ENC_SOPC_insn_table + const amdgpu_gfx908_insn_entry ENC_SOPK_insn_table[22] = + { + {amdgpu_gfx908_op_S_MOVK_I32,"S_MOVK_I32"}, // 0 + {amdgpu_gfx908_op_S_CMOVK_I32,"S_CMOVK_I32"}, // 1 + {amdgpu_gfx908_op_S_CMPK_EQ_I32,"S_CMPK_EQ_I32"}, // 2 + {amdgpu_gfx908_op_S_CMPK_LG_I32,"S_CMPK_LG_I32"}, // 3 + {amdgpu_gfx908_op_S_CMPK_GT_I32,"S_CMPK_GT_I32"}, // 4 + {amdgpu_gfx908_op_S_CMPK_GE_I32,"S_CMPK_GE_I32"}, // 5 + {amdgpu_gfx908_op_S_CMPK_LT_I32,"S_CMPK_LT_I32"}, // 6 + {amdgpu_gfx908_op_S_CMPK_LE_I32,"S_CMPK_LE_I32"}, // 7 + {amdgpu_gfx908_op_S_CMPK_EQ_U32,"S_CMPK_EQ_U32"}, // 8 + {amdgpu_gfx908_op_S_CMPK_LG_U32,"S_CMPK_LG_U32"}, // 9 + {amdgpu_gfx908_op_S_CMPK_GT_U32,"S_CMPK_GT_U32"}, // 10 + {amdgpu_gfx908_op_S_CMPK_GE_U32,"S_CMPK_GE_U32"}, // 11 + {amdgpu_gfx908_op_S_CMPK_LT_U32,"S_CMPK_LT_U32"}, // 12 + {amdgpu_gfx908_op_S_CMPK_LE_U32,"S_CMPK_LE_U32"}, // 13 + {amdgpu_gfx908_op_S_ADDK_I32,"S_ADDK_I32"}, // 14 + {amdgpu_gfx908_op_S_MULK_I32,"S_MULK_I32"}, // 15 + {amdgpu_gfx908_op_S_CBRANCH_I_FORK,"S_CBRANCH_I_FORK"}, // 16 + {amdgpu_gfx908_op_S_GETREG_B32,"S_GETREG_B32"}, // 17 + {amdgpu_gfx908_op_S_SETREG_B32,"S_SETREG_B32"}, // 18 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 19 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 20 + {amdgpu_gfx908_op_S_CALL_B64,"S_CALL_B64"}, // 21 + }; // end ENC_SOPK_insn_table + const amdgpu_gfx908_insn_entry SOPK_INST_LITERAL__insn_table[21] = + { + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 0 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 1 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 2 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 3 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 4 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 5 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 6 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 7 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 8 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 9 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 10 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 11 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 12 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 13 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 14 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 15 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 16 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 17 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 18 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 19 + {amdgpu_gfx908_op_S_SETREG_IMM32_B32,"S_SETREG_IMM32_B32"}, // 20 + }; // end SOPK_INST_LITERAL__insn_table + const amdgpu_gfx908_insn_entry ENC_SOPP_insn_table[31] = + { + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 0 + {amdgpu_gfx908_op_S_ENDPGM,"S_ENDPGM"}, // 1 + {amdgpu_gfx908_op_S_BRANCH,"S_BRANCH"}, // 2 + {amdgpu_gfx908_op_S_WAKEUP,"S_WAKEUP"}, // 3 + {amdgpu_gfx908_op_S_CBRANCH_SCC0,"S_CBRANCH_SCC0"}, // 4 + {amdgpu_gfx908_op_S_CBRANCH_SCC1,"S_CBRANCH_SCC1"}, // 5 + {amdgpu_gfx908_op_S_CBRANCH_VCCZ,"S_CBRANCH_VCCZ"}, // 6 + {amdgpu_gfx908_op_S_CBRANCH_VCCNZ,"S_CBRANCH_VCCNZ"}, // 7 + {amdgpu_gfx908_op_S_CBRANCH_EXECZ,"S_CBRANCH_EXECZ"}, // 8 + {amdgpu_gfx908_op_S_CBRANCH_EXECNZ,"S_CBRANCH_EXECNZ"}, // 9 + {amdgpu_gfx908_op_S_BARRIER,"S_BARRIER"}, // 10 + {amdgpu_gfx908_op_S_SETKILL,"S_SETKILL"}, // 11 + {amdgpu_gfx908_op_S_WAITCNT,"S_WAITCNT"}, // 12 + {amdgpu_gfx908_op_S_SETHALT,"S_SETHALT"}, // 13 + {amdgpu_gfx908_op_S_SLEEP,"S_SLEEP"}, // 14 + {amdgpu_gfx908_op_S_SETPRIO,"S_SETPRIO"}, // 15 + {amdgpu_gfx908_op_S_SENDMSG,"S_SENDMSG"}, // 16 + {amdgpu_gfx908_op_S_SENDMSGHALT,"S_SENDMSGHALT"}, // 17 + {amdgpu_gfx908_op_S_TRAP,"S_TRAP"}, // 18 + {amdgpu_gfx908_op_S_ICACHE_INV,"S_ICACHE_INV"}, // 19 + {amdgpu_gfx908_op_S_INCPERFLEVEL,"S_INCPERFLEVEL"}, // 20 + {amdgpu_gfx908_op_S_DECPERFLEVEL,"S_DECPERFLEVEL"}, // 21 + {amdgpu_gfx908_op_S_TTRACEDATA,"S_TTRACEDATA"}, // 22 + {amdgpu_gfx908_op_S_CBRANCH_CDBGSYS,"S_CBRANCH_CDBGSYS"}, // 23 + {amdgpu_gfx908_op_S_CBRANCH_CDBGUSER,"S_CBRANCH_CDBGUSER"}, // 24 + {amdgpu_gfx908_op_S_CBRANCH_CDBGSYS_OR_USER,"S_CBRANCH_CDBGSYS_OR_USER"}, // 25 + {amdgpu_gfx908_op_S_CBRANCH_CDBGSYS_AND_USER,"S_CBRANCH_CDBGSYS_AND_USER"}, // 26 + {amdgpu_gfx908_op_S_ENDPGM_SAVED,"S_ENDPGM_SAVED"}, // 27 + {amdgpu_gfx908_op_S_SET_GPR_IDX_OFF,"S_SET_GPR_IDX_OFF"}, // 28 + {amdgpu_gfx908_op_S_SET_GPR_IDX_MODE,"S_SET_GPR_IDX_MODE"}, // 29 + {amdgpu_gfx908_op_S_ENDPGM_ORDERED_PS_DONE,"S_ENDPGM_ORDERED_PS_DONE"}, // 30 + }; // end ENC_SOPP_insn_table + const amdgpu_gfx908_insn_entry ENC_VINTRP_insn_table[3] = + { + {amdgpu_gfx908_op_V_INTERP_P1_F32,"V_INTERP_P1_F32"}, // 0 + {amdgpu_gfx908_op_V_INTERP_P2_F32,"V_INTERP_P2_F32"}, // 1 + {amdgpu_gfx908_op_V_INTERP_MOV_F32,"V_INTERP_MOV_F32"}, // 2 + }; // end ENC_VINTRP_insn_table + const amdgpu_gfx908_insn_entry ENC_VOP3_insn_table[673] = + { + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 0 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 1 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 2 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 3 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 4 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 5 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 6 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 7 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 8 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 9 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 10 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 11 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 12 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 13 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 14 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 15 + {amdgpu_gfx908_op_V_CMP_CLASS_F32,"V_CMP_CLASS_F32"}, // 16 + {amdgpu_gfx908_op_V_CMPX_CLASS_F32,"V_CMPX_CLASS_F32"}, // 17 + {amdgpu_gfx908_op_V_CMP_CLASS_F64,"V_CMP_CLASS_F64"}, // 18 + {amdgpu_gfx908_op_V_CMPX_CLASS_F64,"V_CMPX_CLASS_F64"}, // 19 + {amdgpu_gfx908_op_V_CMP_CLASS_F16,"V_CMP_CLASS_F16"}, // 20 + {amdgpu_gfx908_op_V_CMPX_CLASS_F16,"V_CMPX_CLASS_F16"}, // 21 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 22 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 23 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 24 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 25 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 26 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 27 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 28 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 29 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 30 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 31 + {amdgpu_gfx908_op_V_CMP_F_F16,"V_CMP_F_F16"}, // 32 + {amdgpu_gfx908_op_V_CMP_LT_F16,"V_CMP_LT_F16"}, // 33 + {amdgpu_gfx908_op_V_CMP_EQ_F16,"V_CMP_EQ_F16"}, // 34 + {amdgpu_gfx908_op_V_CMP_LE_F16,"V_CMP_LE_F16"}, // 35 + {amdgpu_gfx908_op_V_CMP_GT_F16,"V_CMP_GT_F16"}, // 36 + {amdgpu_gfx908_op_V_CMP_LG_F16,"V_CMP_LG_F16"}, // 37 + {amdgpu_gfx908_op_V_CMP_GE_F16,"V_CMP_GE_F16"}, // 38 + {amdgpu_gfx908_op_V_CMP_O_F16,"V_CMP_O_F16"}, // 39 + {amdgpu_gfx908_op_V_CMP_U_F16,"V_CMP_U_F16"}, // 40 + {amdgpu_gfx908_op_V_CMP_NGE_F16,"V_CMP_NGE_F16"}, // 41 + {amdgpu_gfx908_op_V_CMP_NLG_F16,"V_CMP_NLG_F16"}, // 42 + {amdgpu_gfx908_op_V_CMP_NGT_F16,"V_CMP_NGT_F16"}, // 43 + {amdgpu_gfx908_op_V_CMP_NLE_F16,"V_CMP_NLE_F16"}, // 44 + {amdgpu_gfx908_op_V_CMP_NEQ_F16,"V_CMP_NEQ_F16"}, // 45 + {amdgpu_gfx908_op_V_CMP_NLT_F16,"V_CMP_NLT_F16"}, // 46 + {amdgpu_gfx908_op_V_CMP_TRU_F16,"V_CMP_TRU_F16"}, // 47 + {amdgpu_gfx908_op_V_CMPX_F_F16,"V_CMPX_F_F16"}, // 48 + {amdgpu_gfx908_op_V_CMPX_LT_F16,"V_CMPX_LT_F16"}, // 49 + {amdgpu_gfx908_op_V_CMPX_EQ_F16,"V_CMPX_EQ_F16"}, // 50 + {amdgpu_gfx908_op_V_CMPX_LE_F16,"V_CMPX_LE_F16"}, // 51 + {amdgpu_gfx908_op_V_CMPX_GT_F16,"V_CMPX_GT_F16"}, // 52 + {amdgpu_gfx908_op_V_CMPX_LG_F16,"V_CMPX_LG_F16"}, // 53 + {amdgpu_gfx908_op_V_CMPX_GE_F16,"V_CMPX_GE_F16"}, // 54 + {amdgpu_gfx908_op_V_CMPX_O_F16,"V_CMPX_O_F16"}, // 55 + {amdgpu_gfx908_op_V_CMPX_U_F16,"V_CMPX_U_F16"}, // 56 + {amdgpu_gfx908_op_V_CMPX_NGE_F16,"V_CMPX_NGE_F16"}, // 57 + {amdgpu_gfx908_op_V_CMPX_NLG_F16,"V_CMPX_NLG_F16"}, // 58 + {amdgpu_gfx908_op_V_CMPX_NGT_F16,"V_CMPX_NGT_F16"}, // 59 + {amdgpu_gfx908_op_V_CMPX_NLE_F16,"V_CMPX_NLE_F16"}, // 60 + {amdgpu_gfx908_op_V_CMPX_NEQ_F16,"V_CMPX_NEQ_F16"}, // 61 + {amdgpu_gfx908_op_V_CMPX_NLT_F16,"V_CMPX_NLT_F16"}, // 62 + {amdgpu_gfx908_op_V_CMPX_TRU_F16,"V_CMPX_TRU_F16"}, // 63 + {amdgpu_gfx908_op_V_CMP_F_F32,"V_CMP_F_F32"}, // 64 + {amdgpu_gfx908_op_V_CMP_LT_F32,"V_CMP_LT_F32"}, // 65 + {amdgpu_gfx908_op_V_CMP_EQ_F32,"V_CMP_EQ_F32"}, // 66 + {amdgpu_gfx908_op_V_CMP_LE_F32,"V_CMP_LE_F32"}, // 67 + {amdgpu_gfx908_op_V_CMP_GT_F32,"V_CMP_GT_F32"}, // 68 + {amdgpu_gfx908_op_V_CMP_LG_F32,"V_CMP_LG_F32"}, // 69 + {amdgpu_gfx908_op_V_CMP_GE_F32,"V_CMP_GE_F32"}, // 70 + {amdgpu_gfx908_op_V_CMP_O_F32,"V_CMP_O_F32"}, // 71 + {amdgpu_gfx908_op_V_CMP_U_F32,"V_CMP_U_F32"}, // 72 + {amdgpu_gfx908_op_V_CMP_NGE_F32,"V_CMP_NGE_F32"}, // 73 + {amdgpu_gfx908_op_V_CMP_NLG_F32,"V_CMP_NLG_F32"}, // 74 + {amdgpu_gfx908_op_V_CMP_NGT_F32,"V_CMP_NGT_F32"}, // 75 + {amdgpu_gfx908_op_V_CMP_NLE_F32,"V_CMP_NLE_F32"}, // 76 + {amdgpu_gfx908_op_V_CMP_NEQ_F32,"V_CMP_NEQ_F32"}, // 77 + {amdgpu_gfx908_op_V_CMP_NLT_F32,"V_CMP_NLT_F32"}, // 78 + {amdgpu_gfx908_op_V_CMP_TRU_F32,"V_CMP_TRU_F32"}, // 79 + {amdgpu_gfx908_op_V_CMPX_F_F32,"V_CMPX_F_F32"}, // 80 + {amdgpu_gfx908_op_V_CMPX_LT_F32,"V_CMPX_LT_F32"}, // 81 + {amdgpu_gfx908_op_V_CMPX_EQ_F32,"V_CMPX_EQ_F32"}, // 82 + {amdgpu_gfx908_op_V_CMPX_LE_F32,"V_CMPX_LE_F32"}, // 83 + {amdgpu_gfx908_op_V_CMPX_GT_F32,"V_CMPX_GT_F32"}, // 84 + {amdgpu_gfx908_op_V_CMPX_LG_F32,"V_CMPX_LG_F32"}, // 85 + {amdgpu_gfx908_op_V_CMPX_GE_F32,"V_CMPX_GE_F32"}, // 86 + {amdgpu_gfx908_op_V_CMPX_O_F32,"V_CMPX_O_F32"}, // 87 + {amdgpu_gfx908_op_V_CMPX_U_F32,"V_CMPX_U_F32"}, // 88 + {amdgpu_gfx908_op_V_CMPX_NGE_F32,"V_CMPX_NGE_F32"}, // 89 + {amdgpu_gfx908_op_V_CMPX_NLG_F32,"V_CMPX_NLG_F32"}, // 90 + {amdgpu_gfx908_op_V_CMPX_NGT_F32,"V_CMPX_NGT_F32"}, // 91 + {amdgpu_gfx908_op_V_CMPX_NLE_F32,"V_CMPX_NLE_F32"}, // 92 + {amdgpu_gfx908_op_V_CMPX_NEQ_F32,"V_CMPX_NEQ_F32"}, // 93 + {amdgpu_gfx908_op_V_CMPX_NLT_F32,"V_CMPX_NLT_F32"}, // 94 + {amdgpu_gfx908_op_V_CMPX_TRU_F32,"V_CMPX_TRU_F32"}, // 95 + {amdgpu_gfx908_op_V_CMP_F_F64,"V_CMP_F_F64"}, // 96 + {amdgpu_gfx908_op_V_CMP_LT_F64,"V_CMP_LT_F64"}, // 97 + {amdgpu_gfx908_op_V_CMP_EQ_F64,"V_CMP_EQ_F64"}, // 98 + {amdgpu_gfx908_op_V_CMP_LE_F64,"V_CMP_LE_F64"}, // 99 + {amdgpu_gfx908_op_V_CMP_GT_F64,"V_CMP_GT_F64"}, // 100 + {amdgpu_gfx908_op_V_CMP_LG_F64,"V_CMP_LG_F64"}, // 101 + {amdgpu_gfx908_op_V_CMP_GE_F64,"V_CMP_GE_F64"}, // 102 + {amdgpu_gfx908_op_V_CMP_O_F64,"V_CMP_O_F64"}, // 103 + {amdgpu_gfx908_op_V_CMP_U_F64,"V_CMP_U_F64"}, // 104 + {amdgpu_gfx908_op_V_CMP_NGE_F64,"V_CMP_NGE_F64"}, // 105 + {amdgpu_gfx908_op_V_CMP_NLG_F64,"V_CMP_NLG_F64"}, // 106 + {amdgpu_gfx908_op_V_CMP_NGT_F64,"V_CMP_NGT_F64"}, // 107 + {amdgpu_gfx908_op_V_CMP_NLE_F64,"V_CMP_NLE_F64"}, // 108 + {amdgpu_gfx908_op_V_CMP_NEQ_F64,"V_CMP_NEQ_F64"}, // 109 + {amdgpu_gfx908_op_V_CMP_NLT_F64,"V_CMP_NLT_F64"}, // 110 + {amdgpu_gfx908_op_V_CMP_TRU_F64,"V_CMP_TRU_F64"}, // 111 + {amdgpu_gfx908_op_V_CMPX_F_F64,"V_CMPX_F_F64"}, // 112 + {amdgpu_gfx908_op_V_CMPX_LT_F64,"V_CMPX_LT_F64"}, // 113 + {amdgpu_gfx908_op_V_CMPX_EQ_F64,"V_CMPX_EQ_F64"}, // 114 + {amdgpu_gfx908_op_V_CMPX_LE_F64,"V_CMPX_LE_F64"}, // 115 + {amdgpu_gfx908_op_V_CMPX_GT_F64,"V_CMPX_GT_F64"}, // 116 + {amdgpu_gfx908_op_V_CMPX_LG_F64,"V_CMPX_LG_F64"}, // 117 + {amdgpu_gfx908_op_V_CMPX_GE_F64,"V_CMPX_GE_F64"}, // 118 + {amdgpu_gfx908_op_V_CMPX_O_F64,"V_CMPX_O_F64"}, // 119 + {amdgpu_gfx908_op_V_CMPX_U_F64,"V_CMPX_U_F64"}, // 120 + {amdgpu_gfx908_op_V_CMPX_NGE_F64,"V_CMPX_NGE_F64"}, // 121 + {amdgpu_gfx908_op_V_CMPX_NLG_F64,"V_CMPX_NLG_F64"}, // 122 + {amdgpu_gfx908_op_V_CMPX_NGT_F64,"V_CMPX_NGT_F64"}, // 123 + {amdgpu_gfx908_op_V_CMPX_NLE_F64,"V_CMPX_NLE_F64"}, // 124 + {amdgpu_gfx908_op_V_CMPX_NEQ_F64,"V_CMPX_NEQ_F64"}, // 125 + {amdgpu_gfx908_op_V_CMPX_NLT_F64,"V_CMPX_NLT_F64"}, // 126 + {amdgpu_gfx908_op_V_CMPX_TRU_F64,"V_CMPX_TRU_F64"}, // 127 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 128 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 129 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 130 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 131 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 132 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 133 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 134 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 135 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 136 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 137 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 138 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 139 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 140 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 141 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 142 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 143 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 144 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 145 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 146 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 147 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 148 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 149 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 150 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 151 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 152 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 153 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 154 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 155 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 156 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 157 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 158 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 159 + {amdgpu_gfx908_op_V_CMP_F_I16,"V_CMP_F_I16"}, // 160 + {amdgpu_gfx908_op_V_CMP_LT_I16,"V_CMP_LT_I16"}, // 161 + {amdgpu_gfx908_op_V_CMP_EQ_I16,"V_CMP_EQ_I16"}, // 162 + {amdgpu_gfx908_op_V_CMP_LE_I16,"V_CMP_LE_I16"}, // 163 + {amdgpu_gfx908_op_V_CMP_GT_I16,"V_CMP_GT_I16"}, // 164 + {amdgpu_gfx908_op_V_CMP_NE_I16,"V_CMP_NE_I16"}, // 165 + {amdgpu_gfx908_op_V_CMP_GE_I16,"V_CMP_GE_I16"}, // 166 + {amdgpu_gfx908_op_V_CMP_T_I16,"V_CMP_T_I16"}, // 167 + {amdgpu_gfx908_op_V_CMP_F_U16,"V_CMP_F_U16"}, // 168 + {amdgpu_gfx908_op_V_CMP_LT_U16,"V_CMP_LT_U16"}, // 169 + {amdgpu_gfx908_op_V_CMP_EQ_U16,"V_CMP_EQ_U16"}, // 170 + {amdgpu_gfx908_op_V_CMP_LE_U16,"V_CMP_LE_U16"}, // 171 + {amdgpu_gfx908_op_V_CMP_GT_U16,"V_CMP_GT_U16"}, // 172 + {amdgpu_gfx908_op_V_CMP_NE_U16,"V_CMP_NE_U16"}, // 173 + {amdgpu_gfx908_op_V_CMP_GE_U16,"V_CMP_GE_U16"}, // 174 + {amdgpu_gfx908_op_V_CMP_T_U16,"V_CMP_T_U16"}, // 175 + {amdgpu_gfx908_op_V_CMPX_F_I16,"V_CMPX_F_I16"}, // 176 + {amdgpu_gfx908_op_V_CMPX_LT_I16,"V_CMPX_LT_I16"}, // 177 + {amdgpu_gfx908_op_V_CMPX_EQ_I16,"V_CMPX_EQ_I16"}, // 178 + {amdgpu_gfx908_op_V_CMPX_LE_I16,"V_CMPX_LE_I16"}, // 179 + {amdgpu_gfx908_op_V_CMPX_GT_I16,"V_CMPX_GT_I16"}, // 180 + {amdgpu_gfx908_op_V_CMPX_NE_I16,"V_CMPX_NE_I16"}, // 181 + {amdgpu_gfx908_op_V_CMPX_GE_I16,"V_CMPX_GE_I16"}, // 182 + {amdgpu_gfx908_op_V_CMPX_T_I16,"V_CMPX_T_I16"}, // 183 + {amdgpu_gfx908_op_V_CMPX_F_U16,"V_CMPX_F_U16"}, // 184 + {amdgpu_gfx908_op_V_CMPX_LT_U16,"V_CMPX_LT_U16"}, // 185 + {amdgpu_gfx908_op_V_CMPX_EQ_U16,"V_CMPX_EQ_U16"}, // 186 + {amdgpu_gfx908_op_V_CMPX_LE_U16,"V_CMPX_LE_U16"}, // 187 + {amdgpu_gfx908_op_V_CMPX_GT_U16,"V_CMPX_GT_U16"}, // 188 + {amdgpu_gfx908_op_V_CMPX_NE_U16,"V_CMPX_NE_U16"}, // 189 + {amdgpu_gfx908_op_V_CMPX_GE_U16,"V_CMPX_GE_U16"}, // 190 + {amdgpu_gfx908_op_V_CMPX_T_U16,"V_CMPX_T_U16"}, // 191 + {amdgpu_gfx908_op_V_CMP_F_I32,"V_CMP_F_I32"}, // 192 + {amdgpu_gfx908_op_V_CMP_LT_I32,"V_CMP_LT_I32"}, // 193 + {amdgpu_gfx908_op_V_CMP_EQ_I32,"V_CMP_EQ_I32"}, // 194 + {amdgpu_gfx908_op_V_CMP_LE_I32,"V_CMP_LE_I32"}, // 195 + {amdgpu_gfx908_op_V_CMP_GT_I32,"V_CMP_GT_I32"}, // 196 + {amdgpu_gfx908_op_V_CMP_NE_I32,"V_CMP_NE_I32"}, // 197 + {amdgpu_gfx908_op_V_CMP_GE_I32,"V_CMP_GE_I32"}, // 198 + {amdgpu_gfx908_op_V_CMP_T_I32,"V_CMP_T_I32"}, // 199 + {amdgpu_gfx908_op_V_CMP_F_U32,"V_CMP_F_U32"}, // 200 + {amdgpu_gfx908_op_V_CMP_LT_U32,"V_CMP_LT_U32"}, // 201 + {amdgpu_gfx908_op_V_CMP_EQ_U32,"V_CMP_EQ_U32"}, // 202 + {amdgpu_gfx908_op_V_CMP_LE_U32,"V_CMP_LE_U32"}, // 203 + {amdgpu_gfx908_op_V_CMP_GT_U32,"V_CMP_GT_U32"}, // 204 + {amdgpu_gfx908_op_V_CMP_NE_U32,"V_CMP_NE_U32"}, // 205 + {amdgpu_gfx908_op_V_CMP_GE_U32,"V_CMP_GE_U32"}, // 206 + {amdgpu_gfx908_op_V_CMP_T_U32,"V_CMP_T_U32"}, // 207 + {amdgpu_gfx908_op_V_CMPX_F_I32,"V_CMPX_F_I32"}, // 208 + {amdgpu_gfx908_op_V_CMPX_LT_I32,"V_CMPX_LT_I32"}, // 209 + {amdgpu_gfx908_op_V_CMPX_EQ_I32,"V_CMPX_EQ_I32"}, // 210 + {amdgpu_gfx908_op_V_CMPX_LE_I32,"V_CMPX_LE_I32"}, // 211 + {amdgpu_gfx908_op_V_CMPX_GT_I32,"V_CMPX_GT_I32"}, // 212 + {amdgpu_gfx908_op_V_CMPX_NE_I32,"V_CMPX_NE_I32"}, // 213 + {amdgpu_gfx908_op_V_CMPX_GE_I32,"V_CMPX_GE_I32"}, // 214 + {amdgpu_gfx908_op_V_CMPX_T_I32,"V_CMPX_T_I32"}, // 215 + {amdgpu_gfx908_op_V_CMPX_F_U32,"V_CMPX_F_U32"}, // 216 + {amdgpu_gfx908_op_V_CMPX_LT_U32,"V_CMPX_LT_U32"}, // 217 + {amdgpu_gfx908_op_V_CMPX_EQ_U32,"V_CMPX_EQ_U32"}, // 218 + {amdgpu_gfx908_op_V_CMPX_LE_U32,"V_CMPX_LE_U32"}, // 219 + {amdgpu_gfx908_op_V_CMPX_GT_U32,"V_CMPX_GT_U32"}, // 220 + {amdgpu_gfx908_op_V_CMPX_NE_U32,"V_CMPX_NE_U32"}, // 221 + {amdgpu_gfx908_op_V_CMPX_GE_U32,"V_CMPX_GE_U32"}, // 222 + {amdgpu_gfx908_op_V_CMPX_T_U32,"V_CMPX_T_U32"}, // 223 + {amdgpu_gfx908_op_V_CMP_F_I64,"V_CMP_F_I64"}, // 224 + {amdgpu_gfx908_op_V_CMP_LT_I64,"V_CMP_LT_I64"}, // 225 + {amdgpu_gfx908_op_V_CMP_EQ_I64,"V_CMP_EQ_I64"}, // 226 + {amdgpu_gfx908_op_V_CMP_LE_I64,"V_CMP_LE_I64"}, // 227 + {amdgpu_gfx908_op_V_CMP_GT_I64,"V_CMP_GT_I64"}, // 228 + {amdgpu_gfx908_op_V_CMP_NE_I64,"V_CMP_NE_I64"}, // 229 + {amdgpu_gfx908_op_V_CMP_GE_I64,"V_CMP_GE_I64"}, // 230 + {amdgpu_gfx908_op_V_CMP_T_I64,"V_CMP_T_I64"}, // 231 + {amdgpu_gfx908_op_V_CMP_F_U64,"V_CMP_F_U64"}, // 232 + {amdgpu_gfx908_op_V_CMP_LT_U64,"V_CMP_LT_U64"}, // 233 + {amdgpu_gfx908_op_V_CMP_EQ_U64,"V_CMP_EQ_U64"}, // 234 + {amdgpu_gfx908_op_V_CMP_LE_U64,"V_CMP_LE_U64"}, // 235 + {amdgpu_gfx908_op_V_CMP_GT_U64,"V_CMP_GT_U64"}, // 236 + {amdgpu_gfx908_op_V_CMP_NE_U64,"V_CMP_NE_U64"}, // 237 + {amdgpu_gfx908_op_V_CMP_GE_U64,"V_CMP_GE_U64"}, // 238 + {amdgpu_gfx908_op_V_CMP_T_U64,"V_CMP_T_U64"}, // 239 + {amdgpu_gfx908_op_V_CMPX_F_I64,"V_CMPX_F_I64"}, // 240 + {amdgpu_gfx908_op_V_CMPX_LT_I64,"V_CMPX_LT_I64"}, // 241 + {amdgpu_gfx908_op_V_CMPX_EQ_I64,"V_CMPX_EQ_I64"}, // 242 + {amdgpu_gfx908_op_V_CMPX_LE_I64,"V_CMPX_LE_I64"}, // 243 + {amdgpu_gfx908_op_V_CMPX_GT_I64,"V_CMPX_GT_I64"}, // 244 + {amdgpu_gfx908_op_V_CMPX_NE_I64,"V_CMPX_NE_I64"}, // 245 + {amdgpu_gfx908_op_V_CMPX_GE_I64,"V_CMPX_GE_I64"}, // 246 + {amdgpu_gfx908_op_V_CMPX_T_I64,"V_CMPX_T_I64"}, // 247 + {amdgpu_gfx908_op_V_CMPX_F_U64,"V_CMPX_F_U64"}, // 248 + {amdgpu_gfx908_op_V_CMPX_LT_U64,"V_CMPX_LT_U64"}, // 249 + {amdgpu_gfx908_op_V_CMPX_EQ_U64,"V_CMPX_EQ_U64"}, // 250 + {amdgpu_gfx908_op_V_CMPX_LE_U64,"V_CMPX_LE_U64"}, // 251 + {amdgpu_gfx908_op_V_CMPX_GT_U64,"V_CMPX_GT_U64"}, // 252 + {amdgpu_gfx908_op_V_CMPX_NE_U64,"V_CMPX_NE_U64"}, // 253 + {amdgpu_gfx908_op_V_CMPX_GE_U64,"V_CMPX_GE_U64"}, // 254 + {amdgpu_gfx908_op_V_CMPX_T_U64,"V_CMPX_T_U64"}, // 255 + {amdgpu_gfx908_op_V_CNDMASK_B32,"V_CNDMASK_B32"}, // 256 + {amdgpu_gfx908_op_V_ADD_F32,"V_ADD_F32"}, // 257 + {amdgpu_gfx908_op_V_SUB_F32,"V_SUB_F32"}, // 258 + {amdgpu_gfx908_op_V_SUBREV_F32,"V_SUBREV_F32"}, // 259 + {amdgpu_gfx908_op_V_MUL_LEGACY_F32,"V_MUL_LEGACY_F32"}, // 260 + {amdgpu_gfx908_op_V_MUL_F32,"V_MUL_F32"}, // 261 + {amdgpu_gfx908_op_V_MUL_I32_I24,"V_MUL_I32_I24"}, // 262 + {amdgpu_gfx908_op_V_MUL_HI_I32_I24,"V_MUL_HI_I32_I24"}, // 263 + {amdgpu_gfx908_op_V_MUL_U32_U24,"V_MUL_U32_U24"}, // 264 + {amdgpu_gfx908_op_V_MUL_HI_U32_U24,"V_MUL_HI_U32_U24"}, // 265 + {amdgpu_gfx908_op_V_MIN_F32,"V_MIN_F32"}, // 266 + {amdgpu_gfx908_op_V_MAX_F32,"V_MAX_F32"}, // 267 + {amdgpu_gfx908_op_V_MIN_I32,"V_MIN_I32"}, // 268 + {amdgpu_gfx908_op_V_MAX_I32,"V_MAX_I32"}, // 269 + {amdgpu_gfx908_op_V_MIN_U32,"V_MIN_U32"}, // 270 + {amdgpu_gfx908_op_V_MAX_U32,"V_MAX_U32"}, // 271 + {amdgpu_gfx908_op_V_LSHRREV_B32,"V_LSHRREV_B32"}, // 272 + {amdgpu_gfx908_op_V_ASHRREV_I32,"V_ASHRREV_I32"}, // 273 + {amdgpu_gfx908_op_V_LSHLREV_B32,"V_LSHLREV_B32"}, // 274 + {amdgpu_gfx908_op_V_AND_B32,"V_AND_B32"}, // 275 + {amdgpu_gfx908_op_V_OR_B32,"V_OR_B32"}, // 276 + {amdgpu_gfx908_op_V_XOR_B32,"V_XOR_B32"}, // 277 + {amdgpu_gfx908_op_V_MAC_F32,"V_MAC_F32"}, // 278 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 279 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 280 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 281 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 282 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 283 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 284 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 285 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 286 + {amdgpu_gfx908_op_V_ADD_F16,"V_ADD_F16"}, // 287 + {amdgpu_gfx908_op_V_SUB_F16,"V_SUB_F16"}, // 288 + {amdgpu_gfx908_op_V_SUBREV_F16,"V_SUBREV_F16"}, // 289 + {amdgpu_gfx908_op_V_MUL_F16,"V_MUL_F16"}, // 290 + {amdgpu_gfx908_op_V_MAC_F16,"V_MAC_F16"}, // 291 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 292 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 293 + {amdgpu_gfx908_op_V_ADD_U16,"V_ADD_U16"}, // 294 + {amdgpu_gfx908_op_V_SUB_U16,"V_SUB_U16"}, // 295 + {amdgpu_gfx908_op_V_SUBREV_U16,"V_SUBREV_U16"}, // 296 + {amdgpu_gfx908_op_V_MUL_LO_U16,"V_MUL_LO_U16"}, // 297 + {amdgpu_gfx908_op_V_LSHLREV_B16,"V_LSHLREV_B16"}, // 298 + {amdgpu_gfx908_op_V_LSHRREV_B16,"V_LSHRREV_B16"}, // 299 + {amdgpu_gfx908_op_V_ASHRREV_I16,"V_ASHRREV_I16"}, // 300 + {amdgpu_gfx908_op_V_MAX_F16,"V_MAX_F16"}, // 301 + {amdgpu_gfx908_op_V_MIN_F16,"V_MIN_F16"}, // 302 + {amdgpu_gfx908_op_V_MAX_U16,"V_MAX_U16"}, // 303 + {amdgpu_gfx908_op_V_MAX_I16,"V_MAX_I16"}, // 304 + {amdgpu_gfx908_op_V_MIN_U16,"V_MIN_U16"}, // 305 + {amdgpu_gfx908_op_V_MIN_I16,"V_MIN_I16"}, // 306 + {amdgpu_gfx908_op_V_LDEXP_F16,"V_LDEXP_F16"}, // 307 + {amdgpu_gfx908_op_V_ADD_U32,"V_ADD_U32"}, // 308 + {amdgpu_gfx908_op_V_SUB_U32,"V_SUB_U32"}, // 309 + {amdgpu_gfx908_op_V_SUBREV_U32,"V_SUBREV_U32"}, // 310 + {amdgpu_gfx908_op_V_DOT2C_F32_F16,"V_DOT2C_F32_F16"}, // 311 + {amdgpu_gfx908_op_V_DOT2C_I32_I16,"V_DOT2C_I32_I16"}, // 312 + {amdgpu_gfx908_op_V_DOT4C_I32_I8,"V_DOT4C_I32_I8"}, // 313 + {amdgpu_gfx908_op_V_DOT8C_I32_I4,"V_DOT8C_I32_I4"}, // 314 + {amdgpu_gfx908_op_V_FMAC_F32,"V_FMAC_F32"}, // 315 + {amdgpu_gfx908_op_V_PK_FMAC_F16,"V_PK_FMAC_F16"}, // 316 + {amdgpu_gfx908_op_V_XNOR_B32,"V_XNOR_B32"}, // 317 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 318 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 319 + {amdgpu_gfx908_op_V_NOP,"V_NOP"}, // 320 + {amdgpu_gfx908_op_V_MOV_B32,"V_MOV_B32"}, // 321 + {amdgpu_gfx908_op_V_READFIRSTLANE_B32,"V_READFIRSTLANE_B32"}, // 322 + {amdgpu_gfx908_op_V_CVT_I32_F64,"V_CVT_I32_F64"}, // 323 + {amdgpu_gfx908_op_V_CVT_F64_I32,"V_CVT_F64_I32"}, // 324 + {amdgpu_gfx908_op_V_CVT_F32_I32,"V_CVT_F32_I32"}, // 325 + {amdgpu_gfx908_op_V_CVT_F32_U32,"V_CVT_F32_U32"}, // 326 + {amdgpu_gfx908_op_V_CVT_U32_F32,"V_CVT_U32_F32"}, // 327 + {amdgpu_gfx908_op_V_CVT_I32_F32,"V_CVT_I32_F32"}, // 328 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 329 + {amdgpu_gfx908_op_V_CVT_F16_F32,"V_CVT_F16_F32"}, // 330 + {amdgpu_gfx908_op_V_CVT_F32_F16,"V_CVT_F32_F16"}, // 331 + {amdgpu_gfx908_op_V_CVT_RPI_I32_F32,"V_CVT_RPI_I32_F32"}, // 332 + {amdgpu_gfx908_op_V_CVT_FLR_I32_F32,"V_CVT_FLR_I32_F32"}, // 333 + {amdgpu_gfx908_op_V_CVT_OFF_F32_I4,"V_CVT_OFF_F32_I4"}, // 334 + {amdgpu_gfx908_op_V_CVT_F32_F64,"V_CVT_F32_F64"}, // 335 + {amdgpu_gfx908_op_V_CVT_F64_F32,"V_CVT_F64_F32"}, // 336 + {amdgpu_gfx908_op_V_CVT_F32_UBYTE0,"V_CVT_F32_UBYTE0"}, // 337 + {amdgpu_gfx908_op_V_CVT_F32_UBYTE1,"V_CVT_F32_UBYTE1"}, // 338 + {amdgpu_gfx908_op_V_CVT_F32_UBYTE2,"V_CVT_F32_UBYTE2"}, // 339 + {amdgpu_gfx908_op_V_CVT_F32_UBYTE3,"V_CVT_F32_UBYTE3"}, // 340 + {amdgpu_gfx908_op_V_CVT_U32_F64,"V_CVT_U32_F64"}, // 341 + {amdgpu_gfx908_op_V_CVT_F64_U32,"V_CVT_F64_U32"}, // 342 + {amdgpu_gfx908_op_V_TRUNC_F64,"V_TRUNC_F64"}, // 343 + {amdgpu_gfx908_op_V_CEIL_F64,"V_CEIL_F64"}, // 344 + {amdgpu_gfx908_op_V_RNDNE_F64,"V_RNDNE_F64"}, // 345 + {amdgpu_gfx908_op_V_FLOOR_F64,"V_FLOOR_F64"}, // 346 + {amdgpu_gfx908_op_V_FRACT_F32,"V_FRACT_F32"}, // 347 + {amdgpu_gfx908_op_V_TRUNC_F32,"V_TRUNC_F32"}, // 348 + {amdgpu_gfx908_op_V_CEIL_F32,"V_CEIL_F32"}, // 349 + {amdgpu_gfx908_op_V_RNDNE_F32,"V_RNDNE_F32"}, // 350 + {amdgpu_gfx908_op_V_FLOOR_F32,"V_FLOOR_F32"}, // 351 + {amdgpu_gfx908_op_V_EXP_F32,"V_EXP_F32"}, // 352 + {amdgpu_gfx908_op_V_LOG_F32,"V_LOG_F32"}, // 353 + {amdgpu_gfx908_op_V_RCP_F32,"V_RCP_F32"}, // 354 + {amdgpu_gfx908_op_V_RCP_IFLAG_F32,"V_RCP_IFLAG_F32"}, // 355 + {amdgpu_gfx908_op_V_RSQ_F32,"V_RSQ_F32"}, // 356 + {amdgpu_gfx908_op_V_RCP_F64,"V_RCP_F64"}, // 357 + {amdgpu_gfx908_op_V_RSQ_F64,"V_RSQ_F64"}, // 358 + {amdgpu_gfx908_op_V_SQRT_F32,"V_SQRT_F32"}, // 359 + {amdgpu_gfx908_op_V_SQRT_F64,"V_SQRT_F64"}, // 360 + {amdgpu_gfx908_op_V_SIN_F32,"V_SIN_F32"}, // 361 + {amdgpu_gfx908_op_V_COS_F32,"V_COS_F32"}, // 362 + {amdgpu_gfx908_op_V_NOT_B32,"V_NOT_B32"}, // 363 + {amdgpu_gfx908_op_V_BFREV_B32,"V_BFREV_B32"}, // 364 + {amdgpu_gfx908_op_V_FFBH_U32,"V_FFBH_U32"}, // 365 + {amdgpu_gfx908_op_V_FFBL_B32,"V_FFBL_B32"}, // 366 + {amdgpu_gfx908_op_V_FFBH_I32,"V_FFBH_I32"}, // 367 + {amdgpu_gfx908_op_V_FREXP_EXP_I32_F64,"V_FREXP_EXP_I32_F64"}, // 368 + {amdgpu_gfx908_op_V_FREXP_MANT_F64,"V_FREXP_MANT_F64"}, // 369 + {amdgpu_gfx908_op_V_FRACT_F64,"V_FRACT_F64"}, // 370 + {amdgpu_gfx908_op_V_FREXP_EXP_I32_F32,"V_FREXP_EXP_I32_F32"}, // 371 + {amdgpu_gfx908_op_V_FREXP_MANT_F32,"V_FREXP_MANT_F32"}, // 372 + {amdgpu_gfx908_op_V_CLREXCP,"V_CLREXCP"}, // 373 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 374 + {amdgpu_gfx908_op_V_SCREEN_PARTITION_4SE_B32,"V_SCREEN_PARTITION_4SE_B32"}, // 375 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 376 + {amdgpu_gfx908_op_V_CVT_F16_U16,"V_CVT_F16_U16"}, // 377 + {amdgpu_gfx908_op_V_CVT_F16_I16,"V_CVT_F16_I16"}, // 378 + {amdgpu_gfx908_op_V_CVT_U16_F16,"V_CVT_U16_F16"}, // 379 + {amdgpu_gfx908_op_V_CVT_I16_F16,"V_CVT_I16_F16"}, // 380 + {amdgpu_gfx908_op_V_RCP_F16,"V_RCP_F16"}, // 381 + {amdgpu_gfx908_op_V_SQRT_F16,"V_SQRT_F16"}, // 382 + {amdgpu_gfx908_op_V_RSQ_F16,"V_RSQ_F16"}, // 383 + {amdgpu_gfx908_op_V_LOG_F16,"V_LOG_F16"}, // 384 + {amdgpu_gfx908_op_V_EXP_F16,"V_EXP_F16"}, // 385 + {amdgpu_gfx908_op_V_FREXP_MANT_F16,"V_FREXP_MANT_F16"}, // 386 + {amdgpu_gfx908_op_V_FREXP_EXP_I16_F16,"V_FREXP_EXP_I16_F16"}, // 387 + {amdgpu_gfx908_op_V_FLOOR_F16,"V_FLOOR_F16"}, // 388 + {amdgpu_gfx908_op_V_CEIL_F16,"V_CEIL_F16"}, // 389 + {amdgpu_gfx908_op_V_TRUNC_F16,"V_TRUNC_F16"}, // 390 + {amdgpu_gfx908_op_V_RNDNE_F16,"V_RNDNE_F16"}, // 391 + {amdgpu_gfx908_op_V_FRACT_F16,"V_FRACT_F16"}, // 392 + {amdgpu_gfx908_op_V_SIN_F16,"V_SIN_F16"}, // 393 + {amdgpu_gfx908_op_V_COS_F16,"V_COS_F16"}, // 394 + {amdgpu_gfx908_op_V_EXP_LEGACY_F32,"V_EXP_LEGACY_F32"}, // 395 + {amdgpu_gfx908_op_V_LOG_LEGACY_F32,"V_LOG_LEGACY_F32"}, // 396 + {amdgpu_gfx908_op_V_CVT_NORM_I16_F16,"V_CVT_NORM_I16_F16"}, // 397 + {amdgpu_gfx908_op_V_CVT_NORM_U16_F16,"V_CVT_NORM_U16_F16"}, // 398 + {amdgpu_gfx908_op_V_SAT_PK_U8_I16,"V_SAT_PK_U8_I16"}, // 399 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 400 + {amdgpu_gfx908_op_V_SWAP_B32,"V_SWAP_B32"}, // 401 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 402 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 403 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 404 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 405 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 406 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 407 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 408 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 409 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 410 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 411 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 412 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 413 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 414 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 415 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 416 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 417 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 418 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 419 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 420 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 421 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 422 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 423 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 424 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 425 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 426 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 427 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 428 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 429 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 430 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 431 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 432 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 433 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 434 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 435 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 436 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 437 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 438 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 439 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 440 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 441 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 442 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 443 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 444 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 445 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 446 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 447 + {amdgpu_gfx908_op_V_MAD_LEGACY_F32,"V_MAD_LEGACY_F32"}, // 448 + {amdgpu_gfx908_op_V_MAD_F32,"V_MAD_F32"}, // 449 + {amdgpu_gfx908_op_V_MAD_I32_I24,"V_MAD_I32_I24"}, // 450 + {amdgpu_gfx908_op_V_MAD_U32_U24,"V_MAD_U32_U24"}, // 451 + {amdgpu_gfx908_op_V_CUBEID_F32,"V_CUBEID_F32"}, // 452 + {amdgpu_gfx908_op_V_CUBESC_F32,"V_CUBESC_F32"}, // 453 + {amdgpu_gfx908_op_V_CUBETC_F32,"V_CUBETC_F32"}, // 454 + {amdgpu_gfx908_op_V_CUBEMA_F32,"V_CUBEMA_F32"}, // 455 + {amdgpu_gfx908_op_V_BFE_U32,"V_BFE_U32"}, // 456 + {amdgpu_gfx908_op_V_BFE_I32,"V_BFE_I32"}, // 457 + {amdgpu_gfx908_op_V_BFI_B32,"V_BFI_B32"}, // 458 + {amdgpu_gfx908_op_V_FMA_F32,"V_FMA_F32"}, // 459 + {amdgpu_gfx908_op_V_FMA_F64,"V_FMA_F64"}, // 460 + {amdgpu_gfx908_op_V_LERP_U8,"V_LERP_U8"}, // 461 + {amdgpu_gfx908_op_V_ALIGNBIT_B32,"V_ALIGNBIT_B32"}, // 462 + {amdgpu_gfx908_op_V_ALIGNBYTE_B32,"V_ALIGNBYTE_B32"}, // 463 + {amdgpu_gfx908_op_V_MIN3_F32,"V_MIN3_F32"}, // 464 + {amdgpu_gfx908_op_V_MIN3_I32,"V_MIN3_I32"}, // 465 + {amdgpu_gfx908_op_V_MIN3_U32,"V_MIN3_U32"}, // 466 + {amdgpu_gfx908_op_V_MAX3_F32,"V_MAX3_F32"}, // 467 + {amdgpu_gfx908_op_V_MAX3_I32,"V_MAX3_I32"}, // 468 + {amdgpu_gfx908_op_V_MAX3_U32,"V_MAX3_U32"}, // 469 + {amdgpu_gfx908_op_V_MED3_F32,"V_MED3_F32"}, // 470 + {amdgpu_gfx908_op_V_MED3_I32,"V_MED3_I32"}, // 471 + {amdgpu_gfx908_op_V_MED3_U32,"V_MED3_U32"}, // 472 + {amdgpu_gfx908_op_V_SAD_U8,"V_SAD_U8"}, // 473 + {amdgpu_gfx908_op_V_SAD_HI_U8,"V_SAD_HI_U8"}, // 474 + {amdgpu_gfx908_op_V_SAD_U16,"V_SAD_U16"}, // 475 + {amdgpu_gfx908_op_V_SAD_U32,"V_SAD_U32"}, // 476 + {amdgpu_gfx908_op_V_CVT_PK_U8_F32,"V_CVT_PK_U8_F32"}, // 477 + {amdgpu_gfx908_op_V_DIV_FIXUP_F32,"V_DIV_FIXUP_F32"}, // 478 + {amdgpu_gfx908_op_V_DIV_FIXUP_F64,"V_DIV_FIXUP_F64"}, // 479 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 480 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 481 + {amdgpu_gfx908_op_V_DIV_FMAS_F32,"V_DIV_FMAS_F32"}, // 482 + {amdgpu_gfx908_op_V_DIV_FMAS_F64,"V_DIV_FMAS_F64"}, // 483 + {amdgpu_gfx908_op_V_MSAD_U8,"V_MSAD_U8"}, // 484 + {amdgpu_gfx908_op_V_QSAD_PK_U16_U8,"V_QSAD_PK_U16_U8"}, // 485 + {amdgpu_gfx908_op_V_MQSAD_PK_U16_U8,"V_MQSAD_PK_U16_U8"}, // 486 + {amdgpu_gfx908_op_V_MQSAD_U32_U8,"V_MQSAD_U32_U8"}, // 487 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 488 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 489 + {amdgpu_gfx908_op_V_MAD_LEGACY_F16,"V_MAD_LEGACY_F16"}, // 490 + {amdgpu_gfx908_op_V_MAD_LEGACY_U16,"V_MAD_LEGACY_U16"}, // 491 + {amdgpu_gfx908_op_V_MAD_LEGACY_I16,"V_MAD_LEGACY_I16"}, // 492 + {amdgpu_gfx908_op_V_PERM_B32,"V_PERM_B32"}, // 493 + {amdgpu_gfx908_op_V_FMA_LEGACY_F16,"V_FMA_LEGACY_F16"}, // 494 + {amdgpu_gfx908_op_V_DIV_FIXUP_LEGACY_F16,"V_DIV_FIXUP_LEGACY_F16"}, // 495 + {amdgpu_gfx908_op_V_CVT_PKACCUM_U8_F32,"V_CVT_PKACCUM_U8_F32"}, // 496 + {amdgpu_gfx908_op_V_MAD_U32_U16,"V_MAD_U32_U16"}, // 497 + {amdgpu_gfx908_op_V_MAD_I32_I16,"V_MAD_I32_I16"}, // 498 + {amdgpu_gfx908_op_V_XAD_U32,"V_XAD_U32"}, // 499 + {amdgpu_gfx908_op_V_MIN3_F16,"V_MIN3_F16"}, // 500 + {amdgpu_gfx908_op_V_MIN3_I16,"V_MIN3_I16"}, // 501 + {amdgpu_gfx908_op_V_MIN3_U16,"V_MIN3_U16"}, // 502 + {amdgpu_gfx908_op_V_MAX3_F16,"V_MAX3_F16"}, // 503 + {amdgpu_gfx908_op_V_MAX3_I16,"V_MAX3_I16"}, // 504 + {amdgpu_gfx908_op_V_MAX3_U16,"V_MAX3_U16"}, // 505 + {amdgpu_gfx908_op_V_MED3_F16,"V_MED3_F16"}, // 506 + {amdgpu_gfx908_op_V_MED3_I16,"V_MED3_I16"}, // 507 + {amdgpu_gfx908_op_V_MED3_U16,"V_MED3_U16"}, // 508 + {amdgpu_gfx908_op_V_LSHL_ADD_U32,"V_LSHL_ADD_U32"}, // 509 + {amdgpu_gfx908_op_V_ADD_LSHL_U32,"V_ADD_LSHL_U32"}, // 510 + {amdgpu_gfx908_op_V_ADD3_U32,"V_ADD3_U32"}, // 511 + {amdgpu_gfx908_op_V_LSHL_OR_B32,"V_LSHL_OR_B32"}, // 512 + {amdgpu_gfx908_op_V_AND_OR_B32,"V_AND_OR_B32"}, // 513 + {amdgpu_gfx908_op_V_OR3_B32,"V_OR3_B32"}, // 514 + {amdgpu_gfx908_op_V_MAD_F16,"V_MAD_F16"}, // 515 + {amdgpu_gfx908_op_V_MAD_U16,"V_MAD_U16"}, // 516 + {amdgpu_gfx908_op_V_MAD_I16,"V_MAD_I16"}, // 517 + {amdgpu_gfx908_op_V_FMA_F16,"V_FMA_F16"}, // 518 + {amdgpu_gfx908_op_V_DIV_FIXUP_F16,"V_DIV_FIXUP_F16"}, // 519 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 520 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 521 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 522 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 523 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 524 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 525 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 526 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 527 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 528 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 529 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 530 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 531 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 532 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 533 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 534 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 535 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 536 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 537 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 538 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 539 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 540 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 541 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 542 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 543 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 544 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 545 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 546 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 547 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 548 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 549 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 550 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 551 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 552 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 553 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 554 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 555 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 556 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 557 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 558 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 559 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 560 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 561 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 562 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 563 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 564 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 565 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 566 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 567 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 568 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 569 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 570 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 571 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 572 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 573 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 574 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 575 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 576 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 577 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 578 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 579 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 580 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 581 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 582 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 583 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 584 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 585 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 586 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 587 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 588 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 589 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 590 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 591 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 592 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 593 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 594 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 595 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 596 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 597 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 598 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 599 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 600 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 601 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 602 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 603 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 604 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 605 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 606 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 607 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 608 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 609 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 610 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 611 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 612 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 613 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 614 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 615 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 616 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 617 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 618 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 619 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 620 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 621 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 622 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 623 + {amdgpu_gfx908_op_V_INTERP_P1_F32,"V_INTERP_P1_F32"}, // 624 + {amdgpu_gfx908_op_V_INTERP_P2_F32,"V_INTERP_P2_F32"}, // 625 + {amdgpu_gfx908_op_V_INTERP_MOV_F32,"V_INTERP_MOV_F32"}, // 626 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 627 + {amdgpu_gfx908_op_V_INTERP_P1LL_F16,"V_INTERP_P1LL_F16"}, // 628 + {amdgpu_gfx908_op_V_INTERP_P1LV_F16,"V_INTERP_P1LV_F16"}, // 629 + {amdgpu_gfx908_op_V_INTERP_P2_LEGACY_F16,"V_INTERP_P2_LEGACY_F16"}, // 630 + {amdgpu_gfx908_op_V_INTERP_P2_F16,"V_INTERP_P2_F16"}, // 631 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 632 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 633 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 634 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 635 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 636 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 637 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 638 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 639 + {amdgpu_gfx908_op_V_ADD_F64,"V_ADD_F64"}, // 640 + {amdgpu_gfx908_op_V_MUL_F64,"V_MUL_F64"}, // 641 + {amdgpu_gfx908_op_V_MIN_F64,"V_MIN_F64"}, // 642 + {amdgpu_gfx908_op_V_MAX_F64,"V_MAX_F64"}, // 643 + {amdgpu_gfx908_op_V_LDEXP_F64,"V_LDEXP_F64"}, // 644 + {amdgpu_gfx908_op_V_MUL_LO_U32,"V_MUL_LO_U32"}, // 645 + {amdgpu_gfx908_op_V_MUL_HI_U32,"V_MUL_HI_U32"}, // 646 + {amdgpu_gfx908_op_V_MUL_HI_I32,"V_MUL_HI_I32"}, // 647 + {amdgpu_gfx908_op_V_LDEXP_F32,"V_LDEXP_F32"}, // 648 + {amdgpu_gfx908_op_V_READLANE_B32,"V_READLANE_B32"}, // 649 + {amdgpu_gfx908_op_V_WRITELANE_B32,"V_WRITELANE_B32"}, // 650 + {amdgpu_gfx908_op_V_BCNT_U32_B32,"V_BCNT_U32_B32"}, // 651 + {amdgpu_gfx908_op_V_MBCNT_LO_U32_B32,"V_MBCNT_LO_U32_B32"}, // 652 + {amdgpu_gfx908_op_V_MBCNT_HI_U32_B32,"V_MBCNT_HI_U32_B32"}, // 653 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 654 + {amdgpu_gfx908_op_V_LSHLREV_B64,"V_LSHLREV_B64"}, // 655 + {amdgpu_gfx908_op_V_LSHRREV_B64,"V_LSHRREV_B64"}, // 656 + {amdgpu_gfx908_op_V_ASHRREV_I64,"V_ASHRREV_I64"}, // 657 + {amdgpu_gfx908_op_V_TRIG_PREOP_F64,"V_TRIG_PREOP_F64"}, // 658 + {amdgpu_gfx908_op_V_BFM_B32,"V_BFM_B32"}, // 659 + {amdgpu_gfx908_op_V_CVT_PKNORM_I16_F32,"V_CVT_PKNORM_I16_F32"}, // 660 + {amdgpu_gfx908_op_V_CVT_PKNORM_U16_F32,"V_CVT_PKNORM_U16_F32"}, // 661 + {amdgpu_gfx908_op_V_CVT_PKRTZ_F16_F32,"V_CVT_PKRTZ_F16_F32"}, // 662 + {amdgpu_gfx908_op_V_CVT_PK_U16_U32,"V_CVT_PK_U16_U32"}, // 663 + {amdgpu_gfx908_op_V_CVT_PK_I16_I32,"V_CVT_PK_I16_I32"}, // 664 + {amdgpu_gfx908_op_V_CVT_PKNORM_I16_F16,"V_CVT_PKNORM_I16_F16"}, // 665 + {amdgpu_gfx908_op_V_CVT_PKNORM_U16_F16,"V_CVT_PKNORM_U16_F16"}, // 666 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 667 + {amdgpu_gfx908_op_V_ADD_I32,"V_ADD_I32"}, // 668 + {amdgpu_gfx908_op_V_SUB_I32,"V_SUB_I32"}, // 669 + {amdgpu_gfx908_op_V_ADD_I16,"V_ADD_I16"}, // 670 + {amdgpu_gfx908_op_V_SUB_I16,"V_SUB_I16"}, // 671 + {amdgpu_gfx908_op_V_PACK_B32_F16,"V_PACK_B32_F16"}, // 672 + }; // end ENC_VOP3_insn_table + const amdgpu_gfx908_insn_entry ENC_VOP1_insn_table[82] = + { + {amdgpu_gfx908_op_V_NOP,"V_NOP"}, // 0 + {amdgpu_gfx908_op_V_MOV_B32,"V_MOV_B32"}, // 1 + {amdgpu_gfx908_op_V_READFIRSTLANE_B32,"V_READFIRSTLANE_B32"}, // 2 + {amdgpu_gfx908_op_V_CVT_I32_F64,"V_CVT_I32_F64"}, // 3 + {amdgpu_gfx908_op_V_CVT_F64_I32,"V_CVT_F64_I32"}, // 4 + {amdgpu_gfx908_op_V_CVT_F32_I32,"V_CVT_F32_I32"}, // 5 + {amdgpu_gfx908_op_V_CVT_F32_U32,"V_CVT_F32_U32"}, // 6 + {amdgpu_gfx908_op_V_CVT_U32_F32,"V_CVT_U32_F32"}, // 7 + {amdgpu_gfx908_op_V_CVT_I32_F32,"V_CVT_I32_F32"}, // 8 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 9 + {amdgpu_gfx908_op_V_CVT_F16_F32,"V_CVT_F16_F32"}, // 10 + {amdgpu_gfx908_op_V_CVT_F32_F16,"V_CVT_F32_F16"}, // 11 + {amdgpu_gfx908_op_V_CVT_RPI_I32_F32,"V_CVT_RPI_I32_F32"}, // 12 + {amdgpu_gfx908_op_V_CVT_FLR_I32_F32,"V_CVT_FLR_I32_F32"}, // 13 + {amdgpu_gfx908_op_V_CVT_OFF_F32_I4,"V_CVT_OFF_F32_I4"}, // 14 + {amdgpu_gfx908_op_V_CVT_F32_F64,"V_CVT_F32_F64"}, // 15 + {amdgpu_gfx908_op_V_CVT_F64_F32,"V_CVT_F64_F32"}, // 16 + {amdgpu_gfx908_op_V_CVT_F32_UBYTE0,"V_CVT_F32_UBYTE0"}, // 17 + {amdgpu_gfx908_op_V_CVT_F32_UBYTE1,"V_CVT_F32_UBYTE1"}, // 18 + {amdgpu_gfx908_op_V_CVT_F32_UBYTE2,"V_CVT_F32_UBYTE2"}, // 19 + {amdgpu_gfx908_op_V_CVT_F32_UBYTE3,"V_CVT_F32_UBYTE3"}, // 20 + {amdgpu_gfx908_op_V_CVT_U32_F64,"V_CVT_U32_F64"}, // 21 + {amdgpu_gfx908_op_V_CVT_F64_U32,"V_CVT_F64_U32"}, // 22 + {amdgpu_gfx908_op_V_TRUNC_F64,"V_TRUNC_F64"}, // 23 + {amdgpu_gfx908_op_V_CEIL_F64,"V_CEIL_F64"}, // 24 + {amdgpu_gfx908_op_V_RNDNE_F64,"V_RNDNE_F64"}, // 25 + {amdgpu_gfx908_op_V_FLOOR_F64,"V_FLOOR_F64"}, // 26 + {amdgpu_gfx908_op_V_FRACT_F32,"V_FRACT_F32"}, // 27 + {amdgpu_gfx908_op_V_TRUNC_F32,"V_TRUNC_F32"}, // 28 + {amdgpu_gfx908_op_V_CEIL_F32,"V_CEIL_F32"}, // 29 + {amdgpu_gfx908_op_V_RNDNE_F32,"V_RNDNE_F32"}, // 30 + {amdgpu_gfx908_op_V_FLOOR_F32,"V_FLOOR_F32"}, // 31 + {amdgpu_gfx908_op_V_EXP_F32,"V_EXP_F32"}, // 32 + {amdgpu_gfx908_op_V_LOG_F32,"V_LOG_F32"}, // 33 + {amdgpu_gfx908_op_V_RCP_F32,"V_RCP_F32"}, // 34 + {amdgpu_gfx908_op_V_RCP_IFLAG_F32,"V_RCP_IFLAG_F32"}, // 35 + {amdgpu_gfx908_op_V_RSQ_F32,"V_RSQ_F32"}, // 36 + {amdgpu_gfx908_op_V_RCP_F64,"V_RCP_F64"}, // 37 + {amdgpu_gfx908_op_V_RSQ_F64,"V_RSQ_F64"}, // 38 + {amdgpu_gfx908_op_V_SQRT_F32,"V_SQRT_F32"}, // 39 + {amdgpu_gfx908_op_V_SQRT_F64,"V_SQRT_F64"}, // 40 + {amdgpu_gfx908_op_V_SIN_F32,"V_SIN_F32"}, // 41 + {amdgpu_gfx908_op_V_COS_F32,"V_COS_F32"}, // 42 + {amdgpu_gfx908_op_V_NOT_B32,"V_NOT_B32"}, // 43 + {amdgpu_gfx908_op_V_BFREV_B32,"V_BFREV_B32"}, // 44 + {amdgpu_gfx908_op_V_FFBH_U32,"V_FFBH_U32"}, // 45 + {amdgpu_gfx908_op_V_FFBL_B32,"V_FFBL_B32"}, // 46 + {amdgpu_gfx908_op_V_FFBH_I32,"V_FFBH_I32"}, // 47 + {amdgpu_gfx908_op_V_FREXP_EXP_I32_F64,"V_FREXP_EXP_I32_F64"}, // 48 + {amdgpu_gfx908_op_V_FREXP_MANT_F64,"V_FREXP_MANT_F64"}, // 49 + {amdgpu_gfx908_op_V_FRACT_F64,"V_FRACT_F64"}, // 50 + {amdgpu_gfx908_op_V_FREXP_EXP_I32_F32,"V_FREXP_EXP_I32_F32"}, // 51 + {amdgpu_gfx908_op_V_FREXP_MANT_F32,"V_FREXP_MANT_F32"}, // 52 + {amdgpu_gfx908_op_V_CLREXCP,"V_CLREXCP"}, // 53 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 54 + {amdgpu_gfx908_op_V_SCREEN_PARTITION_4SE_B32,"V_SCREEN_PARTITION_4SE_B32"}, // 55 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 56 + {amdgpu_gfx908_op_V_CVT_F16_U16,"V_CVT_F16_U16"}, // 57 + {amdgpu_gfx908_op_V_CVT_F16_I16,"V_CVT_F16_I16"}, // 58 + {amdgpu_gfx908_op_V_CVT_U16_F16,"V_CVT_U16_F16"}, // 59 + {amdgpu_gfx908_op_V_CVT_I16_F16,"V_CVT_I16_F16"}, // 60 + {amdgpu_gfx908_op_V_RCP_F16,"V_RCP_F16"}, // 61 + {amdgpu_gfx908_op_V_SQRT_F16,"V_SQRT_F16"}, // 62 + {amdgpu_gfx908_op_V_RSQ_F16,"V_RSQ_F16"}, // 63 + {amdgpu_gfx908_op_V_LOG_F16,"V_LOG_F16"}, // 64 + {amdgpu_gfx908_op_V_EXP_F16,"V_EXP_F16"}, // 65 + {amdgpu_gfx908_op_V_FREXP_MANT_F16,"V_FREXP_MANT_F16"}, // 66 + {amdgpu_gfx908_op_V_FREXP_EXP_I16_F16,"V_FREXP_EXP_I16_F16"}, // 67 + {amdgpu_gfx908_op_V_FLOOR_F16,"V_FLOOR_F16"}, // 68 + {amdgpu_gfx908_op_V_CEIL_F16,"V_CEIL_F16"}, // 69 + {amdgpu_gfx908_op_V_TRUNC_F16,"V_TRUNC_F16"}, // 70 + {amdgpu_gfx908_op_V_RNDNE_F16,"V_RNDNE_F16"}, // 71 + {amdgpu_gfx908_op_V_FRACT_F16,"V_FRACT_F16"}, // 72 + {amdgpu_gfx908_op_V_SIN_F16,"V_SIN_F16"}, // 73 + {amdgpu_gfx908_op_V_COS_F16,"V_COS_F16"}, // 74 + {amdgpu_gfx908_op_V_EXP_LEGACY_F32,"V_EXP_LEGACY_F32"}, // 75 + {amdgpu_gfx908_op_V_LOG_LEGACY_F32,"V_LOG_LEGACY_F32"}, // 76 + {amdgpu_gfx908_op_V_CVT_NORM_I16_F16,"V_CVT_NORM_I16_F16"}, // 77 + {amdgpu_gfx908_op_V_CVT_NORM_U16_F16,"V_CVT_NORM_U16_F16"}, // 78 + {amdgpu_gfx908_op_V_SAT_PK_U8_I16,"V_SAT_PK_U8_I16"}, // 79 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 80 + {amdgpu_gfx908_op_V_SWAP_B32,"V_SWAP_B32"}, // 81 + }; // end ENC_VOP1_insn_table + const amdgpu_gfx908_insn_entry ENC_VOP2_insn_table[62] = + { + {amdgpu_gfx908_op_V_CNDMASK_B32,"V_CNDMASK_B32"}, // 0 + {amdgpu_gfx908_op_V_ADD_F32,"V_ADD_F32"}, // 1 + {amdgpu_gfx908_op_V_SUB_F32,"V_SUB_F32"}, // 2 + {amdgpu_gfx908_op_V_SUBREV_F32,"V_SUBREV_F32"}, // 3 + {amdgpu_gfx908_op_V_MUL_LEGACY_F32,"V_MUL_LEGACY_F32"}, // 4 + {amdgpu_gfx908_op_V_MUL_F32,"V_MUL_F32"}, // 5 + {amdgpu_gfx908_op_V_MUL_I32_I24,"V_MUL_I32_I24"}, // 6 + {amdgpu_gfx908_op_V_MUL_HI_I32_I24,"V_MUL_HI_I32_I24"}, // 7 + {amdgpu_gfx908_op_V_MUL_U32_U24,"V_MUL_U32_U24"}, // 8 + {amdgpu_gfx908_op_V_MUL_HI_U32_U24,"V_MUL_HI_U32_U24"}, // 9 + {amdgpu_gfx908_op_V_MIN_F32,"V_MIN_F32"}, // 10 + {amdgpu_gfx908_op_V_MAX_F32,"V_MAX_F32"}, // 11 + {amdgpu_gfx908_op_V_MIN_I32,"V_MIN_I32"}, // 12 + {amdgpu_gfx908_op_V_MAX_I32,"V_MAX_I32"}, // 13 + {amdgpu_gfx908_op_V_MIN_U32,"V_MIN_U32"}, // 14 + {amdgpu_gfx908_op_V_MAX_U32,"V_MAX_U32"}, // 15 + {amdgpu_gfx908_op_V_LSHRREV_B32,"V_LSHRREV_B32"}, // 16 + {amdgpu_gfx908_op_V_ASHRREV_I32,"V_ASHRREV_I32"}, // 17 + {amdgpu_gfx908_op_V_LSHLREV_B32,"V_LSHLREV_B32"}, // 18 + {amdgpu_gfx908_op_V_AND_B32,"V_AND_B32"}, // 19 + {amdgpu_gfx908_op_V_OR_B32,"V_OR_B32"}, // 20 + {amdgpu_gfx908_op_V_XOR_B32,"V_XOR_B32"}, // 21 + {amdgpu_gfx908_op_V_MAC_F32,"V_MAC_F32"}, // 22 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 23 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 24 + {amdgpu_gfx908_op_V_ADD_CO_U32,"V_ADD_CO_U32"}, // 25 + {amdgpu_gfx908_op_V_SUB_CO_U32,"V_SUB_CO_U32"}, // 26 + {amdgpu_gfx908_op_V_SUBREV_CO_U32,"V_SUBREV_CO_U32"}, // 27 + {amdgpu_gfx908_op_V_ADDC_CO_U32,"V_ADDC_CO_U32"}, // 28 + {amdgpu_gfx908_op_V_SUBB_CO_U32,"V_SUBB_CO_U32"}, // 29 + {amdgpu_gfx908_op_V_SUBBREV_CO_U32,"V_SUBBREV_CO_U32"}, // 30 + {amdgpu_gfx908_op_V_ADD_F16,"V_ADD_F16"}, // 31 + {amdgpu_gfx908_op_V_SUB_F16,"V_SUB_F16"}, // 32 + {amdgpu_gfx908_op_V_SUBREV_F16,"V_SUBREV_F16"}, // 33 + {amdgpu_gfx908_op_V_MUL_F16,"V_MUL_F16"}, // 34 + {amdgpu_gfx908_op_V_MAC_F16,"V_MAC_F16"}, // 35 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 36 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 37 + {amdgpu_gfx908_op_V_ADD_U16,"V_ADD_U16"}, // 38 + {amdgpu_gfx908_op_V_SUB_U16,"V_SUB_U16"}, // 39 + {amdgpu_gfx908_op_V_SUBREV_U16,"V_SUBREV_U16"}, // 40 + {amdgpu_gfx908_op_V_MUL_LO_U16,"V_MUL_LO_U16"}, // 41 + {amdgpu_gfx908_op_V_LSHLREV_B16,"V_LSHLREV_B16"}, // 42 + {amdgpu_gfx908_op_V_LSHRREV_B16,"V_LSHRREV_B16"}, // 43 + {amdgpu_gfx908_op_V_ASHRREV_I16,"V_ASHRREV_I16"}, // 44 + {amdgpu_gfx908_op_V_MAX_F16,"V_MAX_F16"}, // 45 + {amdgpu_gfx908_op_V_MIN_F16,"V_MIN_F16"}, // 46 + {amdgpu_gfx908_op_V_MAX_U16,"V_MAX_U16"}, // 47 + {amdgpu_gfx908_op_V_MAX_I16,"V_MAX_I16"}, // 48 + {amdgpu_gfx908_op_V_MIN_U16,"V_MIN_U16"}, // 49 + {amdgpu_gfx908_op_V_MIN_I16,"V_MIN_I16"}, // 50 + {amdgpu_gfx908_op_V_LDEXP_F16,"V_LDEXP_F16"}, // 51 + {amdgpu_gfx908_op_V_ADD_U32,"V_ADD_U32"}, // 52 + {amdgpu_gfx908_op_V_SUB_U32,"V_SUB_U32"}, // 53 + {amdgpu_gfx908_op_V_SUBREV_U32,"V_SUBREV_U32"}, // 54 + {amdgpu_gfx908_op_V_DOT2C_F32_F16,"V_DOT2C_F32_F16"}, // 55 + {amdgpu_gfx908_op_V_DOT2C_I32_I16,"V_DOT2C_I32_I16"}, // 56 + {amdgpu_gfx908_op_V_DOT4C_I32_I8,"V_DOT4C_I32_I8"}, // 57 + {amdgpu_gfx908_op_V_DOT8C_I32_I4,"V_DOT8C_I32_I4"}, // 58 + {amdgpu_gfx908_op_V_FMAC_F32,"V_FMAC_F32"}, // 59 + {amdgpu_gfx908_op_V_PK_FMAC_F16,"V_PK_FMAC_F16"}, // 60 + {amdgpu_gfx908_op_V_XNOR_B32,"V_XNOR_B32"}, // 61 + }; // end ENC_VOP2_insn_table + const amdgpu_gfx908_insn_entry ENC_VOP2_LITERAL_insn_table[38] = + { + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 0 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 1 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 2 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 3 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 4 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 5 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 6 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 7 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 8 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 9 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 10 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 11 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 12 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 13 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 14 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 15 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 16 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 17 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 18 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 19 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 20 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 21 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 22 + {amdgpu_gfx908_op_V_MADMK_F32,"V_MADMK_F32"}, // 23 + {amdgpu_gfx908_op_V_MADAK_F32,"V_MADAK_F32"}, // 24 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 25 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 26 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 27 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 28 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 29 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 30 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 31 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 32 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 33 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 34 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 35 + {amdgpu_gfx908_op_V_MADMK_F16,"V_MADMK_F16"}, // 36 + {amdgpu_gfx908_op_V_MADAK_F16,"V_MADAK_F16"}, // 37 + }; // end ENC_VOP2_LITERAL_insn_table + const amdgpu_gfx908_insn_entry ENC_VOP3B_insn_table[490] = + { + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 0 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 1 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 2 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 3 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 4 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 5 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 6 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 7 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 8 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 9 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 10 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 11 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 12 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 13 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 14 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 15 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 16 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 17 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 18 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 19 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 20 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 21 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 22 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 23 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 24 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 25 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 26 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 27 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 28 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 29 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 30 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 31 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 32 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 33 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 34 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 35 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 36 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 37 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 38 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 39 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 40 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 41 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 42 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 43 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 44 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 45 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 46 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 47 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 48 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 49 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 50 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 51 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 52 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 53 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 54 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 55 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 56 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 57 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 58 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 59 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 60 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 61 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 62 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 63 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 64 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 65 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 66 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 67 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 68 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 69 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 70 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 71 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 72 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 73 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 74 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 75 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 76 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 77 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 78 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 79 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 80 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 81 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 82 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 83 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 84 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 85 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 86 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 87 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 88 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 89 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 90 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 91 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 92 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 93 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 94 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 95 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 96 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 97 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 98 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 99 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 100 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 101 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 102 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 103 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 104 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 105 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 106 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 107 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 108 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 109 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 110 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 111 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 112 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 113 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 114 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 115 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 116 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 117 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 118 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 119 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 120 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 121 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 122 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 123 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 124 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 125 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 126 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 127 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 128 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 129 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 130 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 131 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 132 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 133 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 134 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 135 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 136 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 137 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 138 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 139 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 140 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 141 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 142 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 143 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 144 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 145 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 146 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 147 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 148 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 149 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 150 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 151 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 152 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 153 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 154 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 155 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 156 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 157 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 158 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 159 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 160 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 161 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 162 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 163 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 164 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 165 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 166 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 167 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 168 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 169 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 170 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 171 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 172 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 173 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 174 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 175 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 176 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 177 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 178 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 179 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 180 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 181 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 182 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 183 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 184 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 185 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 186 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 187 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 188 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 189 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 190 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 191 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 192 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 193 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 194 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 195 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 196 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 197 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 198 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 199 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 200 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 201 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 202 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 203 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 204 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 205 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 206 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 207 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 208 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 209 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 210 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 211 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 212 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 213 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 214 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 215 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 216 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 217 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 218 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 219 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 220 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 221 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 222 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 223 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 224 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 225 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 226 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 227 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 228 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 229 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 230 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 231 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 232 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 233 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 234 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 235 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 236 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 237 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 238 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 239 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 240 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 241 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 242 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 243 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 244 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 245 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 246 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 247 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 248 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 249 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 250 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 251 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 252 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 253 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 254 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 255 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 256 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 257 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 258 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 259 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 260 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 261 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 262 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 263 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 264 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 265 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 266 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 267 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 268 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 269 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 270 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 271 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 272 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 273 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 274 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 275 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 276 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 277 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 278 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 279 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 280 + {amdgpu_gfx908_op_V_ADD_CO_U32,"V_ADD_CO_U32"}, // 281 + {amdgpu_gfx908_op_V_SUB_CO_U32,"V_SUB_CO_U32"}, // 282 + {amdgpu_gfx908_op_V_SUBREV_CO_U32,"V_SUBREV_CO_U32"}, // 283 + {amdgpu_gfx908_op_V_ADDC_CO_U32,"V_ADDC_CO_U32"}, // 284 + {amdgpu_gfx908_op_V_SUBB_CO_U32,"V_SUBB_CO_U32"}, // 285 + {amdgpu_gfx908_op_V_SUBBREV_CO_U32,"V_SUBBREV_CO_U32"}, // 286 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 287 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 288 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 289 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 290 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 291 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 292 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 293 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 294 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 295 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 296 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 297 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 298 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 299 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 300 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 301 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 302 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 303 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 304 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 305 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 306 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 307 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 308 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 309 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 310 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 311 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 312 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 313 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 314 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 315 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 316 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 317 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 318 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 319 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 320 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 321 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 322 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 323 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 324 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 325 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 326 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 327 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 328 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 329 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 330 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 331 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 332 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 333 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 334 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 335 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 336 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 337 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 338 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 339 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 340 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 341 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 342 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 343 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 344 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 345 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 346 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 347 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 348 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 349 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 350 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 351 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 352 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 353 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 354 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 355 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 356 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 357 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 358 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 359 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 360 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 361 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 362 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 363 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 364 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 365 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 366 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 367 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 368 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 369 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 370 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 371 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 372 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 373 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 374 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 375 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 376 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 377 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 378 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 379 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 380 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 381 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 382 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 383 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 384 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 385 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 386 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 387 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 388 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 389 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 390 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 391 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 392 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 393 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 394 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 395 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 396 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 397 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 398 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 399 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 400 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 401 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 402 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 403 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 404 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 405 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 406 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 407 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 408 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 409 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 410 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 411 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 412 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 413 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 414 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 415 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 416 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 417 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 418 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 419 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 420 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 421 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 422 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 423 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 424 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 425 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 426 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 427 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 428 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 429 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 430 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 431 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 432 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 433 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 434 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 435 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 436 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 437 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 438 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 439 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 440 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 441 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 442 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 443 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 444 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 445 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 446 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 447 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 448 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 449 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 450 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 451 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 452 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 453 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 454 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 455 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 456 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 457 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 458 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 459 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 460 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 461 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 462 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 463 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 464 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 465 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 466 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 467 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 468 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 469 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 470 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 471 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 472 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 473 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 474 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 475 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 476 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 477 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 478 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 479 + {amdgpu_gfx908_op_V_DIV_SCALE_F32,"V_DIV_SCALE_F32"}, // 480 + {amdgpu_gfx908_op_V_DIV_SCALE_F64,"V_DIV_SCALE_F64"}, // 481 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 482 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 483 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 484 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 485 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 486 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 487 + {amdgpu_gfx908_op_V_MAD_U64_U32,"V_MAD_U64_U32"}, // 488 + {amdgpu_gfx908_op_V_MAD_I64_I32,"V_MAD_I64_I32"}, // 489 + }; // end ENC_VOP3B_insn_table + const amdgpu_gfx908_insn_entry ENC_VOP3P_insn_table[90] = + { + {amdgpu_gfx908_op_V_PK_MAD_I16,"V_PK_MAD_I16"}, // 0 + {amdgpu_gfx908_op_V_PK_MUL_LO_U16,"V_PK_MUL_LO_U16"}, // 1 + {amdgpu_gfx908_op_V_PK_ADD_I16,"V_PK_ADD_I16"}, // 2 + {amdgpu_gfx908_op_V_PK_SUB_I16,"V_PK_SUB_I16"}, // 3 + {amdgpu_gfx908_op_V_PK_LSHLREV_B16,"V_PK_LSHLREV_B16"}, // 4 + {amdgpu_gfx908_op_V_PK_LSHRREV_B16,"V_PK_LSHRREV_B16"}, // 5 + {amdgpu_gfx908_op_V_PK_ASHRREV_I16,"V_PK_ASHRREV_I16"}, // 6 + {amdgpu_gfx908_op_V_PK_MAX_I16,"V_PK_MAX_I16"}, // 7 + {amdgpu_gfx908_op_V_PK_MIN_I16,"V_PK_MIN_I16"}, // 8 + {amdgpu_gfx908_op_V_PK_MAD_U16,"V_PK_MAD_U16"}, // 9 + {amdgpu_gfx908_op_V_PK_ADD_U16,"V_PK_ADD_U16"}, // 10 + {amdgpu_gfx908_op_V_PK_SUB_U16,"V_PK_SUB_U16"}, // 11 + {amdgpu_gfx908_op_V_PK_MAX_U16,"V_PK_MAX_U16"}, // 12 + {amdgpu_gfx908_op_V_PK_MIN_U16,"V_PK_MIN_U16"}, // 13 + {amdgpu_gfx908_op_V_PK_FMA_F16,"V_PK_FMA_F16"}, // 14 + {amdgpu_gfx908_op_V_PK_ADD_F16,"V_PK_ADD_F16"}, // 15 + {amdgpu_gfx908_op_V_PK_MUL_F16,"V_PK_MUL_F16"}, // 16 + {amdgpu_gfx908_op_V_PK_MIN_F16,"V_PK_MIN_F16"}, // 17 + {amdgpu_gfx908_op_V_PK_MAX_F16,"V_PK_MAX_F16"}, // 18 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 19 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 20 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 21 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 22 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 23 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 24 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 25 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 26 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 27 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 28 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 29 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 30 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 31 + {amdgpu_gfx908_op_V_MAD_MIX_F32,"V_MAD_MIX_F32"}, // 32 + {amdgpu_gfx908_op_V_MAD_MIXLO_F16,"V_MAD_MIXLO_F16"}, // 33 + {amdgpu_gfx908_op_V_MAD_MIXHI_F16,"V_MAD_MIXHI_F16"}, // 34 + {amdgpu_gfx908_op_V_DOT2_F32_F16,"V_DOT2_F32_F16"}, // 35 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 36 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 37 + {amdgpu_gfx908_op_V_DOT2_I32_I16,"V_DOT2_I32_I16"}, // 38 + {amdgpu_gfx908_op_V_DOT2_U32_U16,"V_DOT2_U32_U16"}, // 39 + {amdgpu_gfx908_op_V_DOT4_I32_I8,"V_DOT4_I32_I8"}, // 40 + {amdgpu_gfx908_op_V_DOT4_U32_U8,"V_DOT4_U32_U8"}, // 41 + {amdgpu_gfx908_op_V_DOT8_I32_I4,"V_DOT8_I32_I4"}, // 42 + {amdgpu_gfx908_op_V_DOT8_U32_U4,"V_DOT8_U32_U4"}, // 43 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 44 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 45 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 46 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 47 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 48 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 49 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 50 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 51 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 52 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 53 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 54 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 55 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 56 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 57 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 58 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 59 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 60 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 61 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 62 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 63 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 64 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 65 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 66 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 67 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 68 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 69 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 70 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 71 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 72 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 73 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 74 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 75 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 76 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 77 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 78 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 79 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 80 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 81 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 82 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 83 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 84 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 85 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 86 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 87 + {amdgpu_gfx908_op_V_ACCVGPR_READ,"V_ACCVGPR_READ"}, // 88 + {amdgpu_gfx908_op_V_ACCVGPR_WRITE,"V_ACCVGPR_WRITE"}, // 89 + }; // end ENC_VOP3P_insn_table + const amdgpu_gfx908_insn_entry ENC_VOP3P_MFMA_insn_table[110] = + { + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 0 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 1 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 2 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 3 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 4 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 5 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 6 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 7 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 8 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 9 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 10 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 11 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 12 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 13 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 14 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 15 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 16 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 17 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 18 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 19 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 20 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 21 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 22 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 23 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 24 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 25 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 26 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 27 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 28 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 29 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 30 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 31 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 32 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 33 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 34 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 35 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 36 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 37 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 38 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 39 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 40 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 41 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 42 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 43 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 44 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 45 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 46 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 47 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 48 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 49 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 50 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 51 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 52 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 53 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 54 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 55 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 56 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 57 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 58 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 59 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 60 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 61 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 62 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 63 + {amdgpu_gfx908_op_V_MFMA_F32_32X32X1F32,"V_MFMA_F32_32X32X1F32"}, // 64 + {amdgpu_gfx908_op_V_MFMA_F32_16X16X1F32,"V_MFMA_F32_16X16X1F32"}, // 65 + {amdgpu_gfx908_op_V_MFMA_F32_4X4X1F32,"V_MFMA_F32_4X4X1F32"}, // 66 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 67 + {amdgpu_gfx908_op_V_MFMA_F32_32X32X2F32,"V_MFMA_F32_32X32X2F32"}, // 68 + {amdgpu_gfx908_op_V_MFMA_F32_16X16X4F32,"V_MFMA_F32_16X16X4F32"}, // 69 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 70 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 71 + {amdgpu_gfx908_op_V_MFMA_F32_32X32X4F16,"V_MFMA_F32_32X32X4F16"}, // 72 + {amdgpu_gfx908_op_V_MFMA_F32_16X16X4F16,"V_MFMA_F32_16X16X4F16"}, // 73 + {amdgpu_gfx908_op_V_MFMA_F32_4X4X4F16,"V_MFMA_F32_4X4X4F16"}, // 74 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 75 + {amdgpu_gfx908_op_V_MFMA_F32_32X32X8F16,"V_MFMA_F32_32X32X8F16"}, // 76 + {amdgpu_gfx908_op_V_MFMA_F32_16X16X16F16,"V_MFMA_F32_16X16X16F16"}, // 77 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 78 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 79 + {amdgpu_gfx908_op_V_MFMA_I32_32X32X4I8,"V_MFMA_I32_32X32X4I8"}, // 80 + {amdgpu_gfx908_op_V_MFMA_I32_16X16X4I8,"V_MFMA_I32_16X16X4I8"}, // 81 + {amdgpu_gfx908_op_V_MFMA_I32_4X4X4I8,"V_MFMA_I32_4X4X4I8"}, // 82 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 83 + {amdgpu_gfx908_op_V_MFMA_I32_32X32X8I8,"V_MFMA_I32_32X32X8I8"}, // 84 + {amdgpu_gfx908_op_V_MFMA_I32_16X16X16I8,"V_MFMA_I32_16X16X16I8"}, // 85 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 86 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 87 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 88 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 89 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 90 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 91 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 92 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 93 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 94 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 95 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 96 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 97 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 98 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 99 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 100 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 101 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 102 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 103 + {amdgpu_gfx908_op_V_MFMA_F32_32X32X2BF16,"V_MFMA_F32_32X32X2BF16"}, // 104 + {amdgpu_gfx908_op_V_MFMA_F32_16X16X2BF16,"V_MFMA_F32_16X16X2BF16"}, // 105 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 106 + {amdgpu_gfx908_op_V_MFMA_F32_4X4X2BF16,"V_MFMA_F32_4X4X2BF16"}, // 107 + {amdgpu_gfx908_op_V_MFMA_F32_32X32X4BF16,"V_MFMA_F32_32X32X4BF16"}, // 108 + {amdgpu_gfx908_op_V_MFMA_F32_16X16X8BF16,"V_MFMA_F32_16X16X8BF16"}, // 109 + }; // end ENC_VOP3P_MFMA_insn_table + const amdgpu_gfx908_insn_entry ENC_VOPC_insn_table[256] = + { + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 0 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 1 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 2 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 3 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 4 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 5 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 6 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 7 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 8 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 9 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 10 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 11 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 12 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 13 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 14 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 15 + {amdgpu_gfx908_op_V_CMP_CLASS_F32,"V_CMP_CLASS_F32"}, // 16 + {amdgpu_gfx908_op_V_CMPX_CLASS_F32,"V_CMPX_CLASS_F32"}, // 17 + {amdgpu_gfx908_op_V_CMP_CLASS_F64,"V_CMP_CLASS_F64"}, // 18 + {amdgpu_gfx908_op_V_CMPX_CLASS_F64,"V_CMPX_CLASS_F64"}, // 19 + {amdgpu_gfx908_op_V_CMP_CLASS_F16,"V_CMP_CLASS_F16"}, // 20 + {amdgpu_gfx908_op_V_CMPX_CLASS_F16,"V_CMPX_CLASS_F16"}, // 21 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 22 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 23 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 24 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 25 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 26 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 27 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 28 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 29 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 30 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 31 + {amdgpu_gfx908_op_V_CMP_F_F16,"V_CMP_F_F16"}, // 32 + {amdgpu_gfx908_op_V_CMP_LT_F16,"V_CMP_LT_F16"}, // 33 + {amdgpu_gfx908_op_V_CMP_EQ_F16,"V_CMP_EQ_F16"}, // 34 + {amdgpu_gfx908_op_V_CMP_LE_F16,"V_CMP_LE_F16"}, // 35 + {amdgpu_gfx908_op_V_CMP_GT_F16,"V_CMP_GT_F16"}, // 36 + {amdgpu_gfx908_op_V_CMP_LG_F16,"V_CMP_LG_F16"}, // 37 + {amdgpu_gfx908_op_V_CMP_GE_F16,"V_CMP_GE_F16"}, // 38 + {amdgpu_gfx908_op_V_CMP_O_F16,"V_CMP_O_F16"}, // 39 + {amdgpu_gfx908_op_V_CMP_U_F16,"V_CMP_U_F16"}, // 40 + {amdgpu_gfx908_op_V_CMP_NGE_F16,"V_CMP_NGE_F16"}, // 41 + {amdgpu_gfx908_op_V_CMP_NLG_F16,"V_CMP_NLG_F16"}, // 42 + {amdgpu_gfx908_op_V_CMP_NGT_F16,"V_CMP_NGT_F16"}, // 43 + {amdgpu_gfx908_op_V_CMP_NLE_F16,"V_CMP_NLE_F16"}, // 44 + {amdgpu_gfx908_op_V_CMP_NEQ_F16,"V_CMP_NEQ_F16"}, // 45 + {amdgpu_gfx908_op_V_CMP_NLT_F16,"V_CMP_NLT_F16"}, // 46 + {amdgpu_gfx908_op_V_CMP_TRU_F16,"V_CMP_TRU_F16"}, // 47 + {amdgpu_gfx908_op_V_CMPX_F_F16,"V_CMPX_F_F16"}, // 48 + {amdgpu_gfx908_op_V_CMPX_LT_F16,"V_CMPX_LT_F16"}, // 49 + {amdgpu_gfx908_op_V_CMPX_EQ_F16,"V_CMPX_EQ_F16"}, // 50 + {amdgpu_gfx908_op_V_CMPX_LE_F16,"V_CMPX_LE_F16"}, // 51 + {amdgpu_gfx908_op_V_CMPX_GT_F16,"V_CMPX_GT_F16"}, // 52 + {amdgpu_gfx908_op_V_CMPX_LG_F16,"V_CMPX_LG_F16"}, // 53 + {amdgpu_gfx908_op_V_CMPX_GE_F16,"V_CMPX_GE_F16"}, // 54 + {amdgpu_gfx908_op_V_CMPX_O_F16,"V_CMPX_O_F16"}, // 55 + {amdgpu_gfx908_op_V_CMPX_U_F16,"V_CMPX_U_F16"}, // 56 + {amdgpu_gfx908_op_V_CMPX_NGE_F16,"V_CMPX_NGE_F16"}, // 57 + {amdgpu_gfx908_op_V_CMPX_NLG_F16,"V_CMPX_NLG_F16"}, // 58 + {amdgpu_gfx908_op_V_CMPX_NGT_F16,"V_CMPX_NGT_F16"}, // 59 + {amdgpu_gfx908_op_V_CMPX_NLE_F16,"V_CMPX_NLE_F16"}, // 60 + {amdgpu_gfx908_op_V_CMPX_NEQ_F16,"V_CMPX_NEQ_F16"}, // 61 + {amdgpu_gfx908_op_V_CMPX_NLT_F16,"V_CMPX_NLT_F16"}, // 62 + {amdgpu_gfx908_op_V_CMPX_TRU_F16,"V_CMPX_TRU_F16"}, // 63 + {amdgpu_gfx908_op_V_CMP_F_F32,"V_CMP_F_F32"}, // 64 + {amdgpu_gfx908_op_V_CMP_LT_F32,"V_CMP_LT_F32"}, // 65 + {amdgpu_gfx908_op_V_CMP_EQ_F32,"V_CMP_EQ_F32"}, // 66 + {amdgpu_gfx908_op_V_CMP_LE_F32,"V_CMP_LE_F32"}, // 67 + {amdgpu_gfx908_op_V_CMP_GT_F32,"V_CMP_GT_F32"}, // 68 + {amdgpu_gfx908_op_V_CMP_LG_F32,"V_CMP_LG_F32"}, // 69 + {amdgpu_gfx908_op_V_CMP_GE_F32,"V_CMP_GE_F32"}, // 70 + {amdgpu_gfx908_op_V_CMP_O_F32,"V_CMP_O_F32"}, // 71 + {amdgpu_gfx908_op_V_CMP_U_F32,"V_CMP_U_F32"}, // 72 + {amdgpu_gfx908_op_V_CMP_NGE_F32,"V_CMP_NGE_F32"}, // 73 + {amdgpu_gfx908_op_V_CMP_NLG_F32,"V_CMP_NLG_F32"}, // 74 + {amdgpu_gfx908_op_V_CMP_NGT_F32,"V_CMP_NGT_F32"}, // 75 + {amdgpu_gfx908_op_V_CMP_NLE_F32,"V_CMP_NLE_F32"}, // 76 + {amdgpu_gfx908_op_V_CMP_NEQ_F32,"V_CMP_NEQ_F32"}, // 77 + {amdgpu_gfx908_op_V_CMP_NLT_F32,"V_CMP_NLT_F32"}, // 78 + {amdgpu_gfx908_op_V_CMP_TRU_F32,"V_CMP_TRU_F32"}, // 79 + {amdgpu_gfx908_op_V_CMPX_F_F32,"V_CMPX_F_F32"}, // 80 + {amdgpu_gfx908_op_V_CMPX_LT_F32,"V_CMPX_LT_F32"}, // 81 + {amdgpu_gfx908_op_V_CMPX_EQ_F32,"V_CMPX_EQ_F32"}, // 82 + {amdgpu_gfx908_op_V_CMPX_LE_F32,"V_CMPX_LE_F32"}, // 83 + {amdgpu_gfx908_op_V_CMPX_GT_F32,"V_CMPX_GT_F32"}, // 84 + {amdgpu_gfx908_op_V_CMPX_LG_F32,"V_CMPX_LG_F32"}, // 85 + {amdgpu_gfx908_op_V_CMPX_GE_F32,"V_CMPX_GE_F32"}, // 86 + {amdgpu_gfx908_op_V_CMPX_O_F32,"V_CMPX_O_F32"}, // 87 + {amdgpu_gfx908_op_V_CMPX_U_F32,"V_CMPX_U_F32"}, // 88 + {amdgpu_gfx908_op_V_CMPX_NGE_F32,"V_CMPX_NGE_F32"}, // 89 + {amdgpu_gfx908_op_V_CMPX_NLG_F32,"V_CMPX_NLG_F32"}, // 90 + {amdgpu_gfx908_op_V_CMPX_NGT_F32,"V_CMPX_NGT_F32"}, // 91 + {amdgpu_gfx908_op_V_CMPX_NLE_F32,"V_CMPX_NLE_F32"}, // 92 + {amdgpu_gfx908_op_V_CMPX_NEQ_F32,"V_CMPX_NEQ_F32"}, // 93 + {amdgpu_gfx908_op_V_CMPX_NLT_F32,"V_CMPX_NLT_F32"}, // 94 + {amdgpu_gfx908_op_V_CMPX_TRU_F32,"V_CMPX_TRU_F32"}, // 95 + {amdgpu_gfx908_op_V_CMP_F_F64,"V_CMP_F_F64"}, // 96 + {amdgpu_gfx908_op_V_CMP_LT_F64,"V_CMP_LT_F64"}, // 97 + {amdgpu_gfx908_op_V_CMP_EQ_F64,"V_CMP_EQ_F64"}, // 98 + {amdgpu_gfx908_op_V_CMP_LE_F64,"V_CMP_LE_F64"}, // 99 + {amdgpu_gfx908_op_V_CMP_GT_F64,"V_CMP_GT_F64"}, // 100 + {amdgpu_gfx908_op_V_CMP_LG_F64,"V_CMP_LG_F64"}, // 101 + {amdgpu_gfx908_op_V_CMP_GE_F64,"V_CMP_GE_F64"}, // 102 + {amdgpu_gfx908_op_V_CMP_O_F64,"V_CMP_O_F64"}, // 103 + {amdgpu_gfx908_op_V_CMP_U_F64,"V_CMP_U_F64"}, // 104 + {amdgpu_gfx908_op_V_CMP_NGE_F64,"V_CMP_NGE_F64"}, // 105 + {amdgpu_gfx908_op_V_CMP_NLG_F64,"V_CMP_NLG_F64"}, // 106 + {amdgpu_gfx908_op_V_CMP_NGT_F64,"V_CMP_NGT_F64"}, // 107 + {amdgpu_gfx908_op_V_CMP_NLE_F64,"V_CMP_NLE_F64"}, // 108 + {amdgpu_gfx908_op_V_CMP_NEQ_F64,"V_CMP_NEQ_F64"}, // 109 + {amdgpu_gfx908_op_V_CMP_NLT_F64,"V_CMP_NLT_F64"}, // 110 + {amdgpu_gfx908_op_V_CMP_TRU_F64,"V_CMP_TRU_F64"}, // 111 + {amdgpu_gfx908_op_V_CMPX_F_F64,"V_CMPX_F_F64"}, // 112 + {amdgpu_gfx908_op_V_CMPX_LT_F64,"V_CMPX_LT_F64"}, // 113 + {amdgpu_gfx908_op_V_CMPX_EQ_F64,"V_CMPX_EQ_F64"}, // 114 + {amdgpu_gfx908_op_V_CMPX_LE_F64,"V_CMPX_LE_F64"}, // 115 + {amdgpu_gfx908_op_V_CMPX_GT_F64,"V_CMPX_GT_F64"}, // 116 + {amdgpu_gfx908_op_V_CMPX_LG_F64,"V_CMPX_LG_F64"}, // 117 + {amdgpu_gfx908_op_V_CMPX_GE_F64,"V_CMPX_GE_F64"}, // 118 + {amdgpu_gfx908_op_V_CMPX_O_F64,"V_CMPX_O_F64"}, // 119 + {amdgpu_gfx908_op_V_CMPX_U_F64,"V_CMPX_U_F64"}, // 120 + {amdgpu_gfx908_op_V_CMPX_NGE_F64,"V_CMPX_NGE_F64"}, // 121 + {amdgpu_gfx908_op_V_CMPX_NLG_F64,"V_CMPX_NLG_F64"}, // 122 + {amdgpu_gfx908_op_V_CMPX_NGT_F64,"V_CMPX_NGT_F64"}, // 123 + {amdgpu_gfx908_op_V_CMPX_NLE_F64,"V_CMPX_NLE_F64"}, // 124 + {amdgpu_gfx908_op_V_CMPX_NEQ_F64,"V_CMPX_NEQ_F64"}, // 125 + {amdgpu_gfx908_op_V_CMPX_NLT_F64,"V_CMPX_NLT_F64"}, // 126 + {amdgpu_gfx908_op_V_CMPX_TRU_F64,"V_CMPX_TRU_F64"}, // 127 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 128 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 129 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 130 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 131 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 132 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 133 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 134 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 135 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 136 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 137 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 138 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 139 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 140 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 141 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 142 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 143 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 144 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 145 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 146 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 147 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 148 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 149 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 150 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 151 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 152 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 153 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 154 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 155 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 156 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 157 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 158 + {amdgpu_gfx908_op_S_NOP,"S_NOP"}, // 159 + {amdgpu_gfx908_op_V_CMP_F_I16,"V_CMP_F_I16"}, // 160 + {amdgpu_gfx908_op_V_CMP_LT_I16,"V_CMP_LT_I16"}, // 161 + {amdgpu_gfx908_op_V_CMP_EQ_I16,"V_CMP_EQ_I16"}, // 162 + {amdgpu_gfx908_op_V_CMP_LE_I16,"V_CMP_LE_I16"}, // 163 + {amdgpu_gfx908_op_V_CMP_GT_I16,"V_CMP_GT_I16"}, // 164 + {amdgpu_gfx908_op_V_CMP_NE_I16,"V_CMP_NE_I16"}, // 165 + {amdgpu_gfx908_op_V_CMP_GE_I16,"V_CMP_GE_I16"}, // 166 + {amdgpu_gfx908_op_V_CMP_T_I16,"V_CMP_T_I16"}, // 167 + {amdgpu_gfx908_op_V_CMP_F_U16,"V_CMP_F_U16"}, // 168 + {amdgpu_gfx908_op_V_CMP_LT_U16,"V_CMP_LT_U16"}, // 169 + {amdgpu_gfx908_op_V_CMP_EQ_U16,"V_CMP_EQ_U16"}, // 170 + {amdgpu_gfx908_op_V_CMP_LE_U16,"V_CMP_LE_U16"}, // 171 + {amdgpu_gfx908_op_V_CMP_GT_U16,"V_CMP_GT_U16"}, // 172 + {amdgpu_gfx908_op_V_CMP_NE_U16,"V_CMP_NE_U16"}, // 173 + {amdgpu_gfx908_op_V_CMP_GE_U16,"V_CMP_GE_U16"}, // 174 + {amdgpu_gfx908_op_V_CMP_T_U16,"V_CMP_T_U16"}, // 175 + {amdgpu_gfx908_op_V_CMPX_F_I16,"V_CMPX_F_I16"}, // 176 + {amdgpu_gfx908_op_V_CMPX_LT_I16,"V_CMPX_LT_I16"}, // 177 + {amdgpu_gfx908_op_V_CMPX_EQ_I16,"V_CMPX_EQ_I16"}, // 178 + {amdgpu_gfx908_op_V_CMPX_LE_I16,"V_CMPX_LE_I16"}, // 179 + {amdgpu_gfx908_op_V_CMPX_GT_I16,"V_CMPX_GT_I16"}, // 180 + {amdgpu_gfx908_op_V_CMPX_NE_I16,"V_CMPX_NE_I16"}, // 181 + {amdgpu_gfx908_op_V_CMPX_GE_I16,"V_CMPX_GE_I16"}, // 182 + {amdgpu_gfx908_op_V_CMPX_T_I16,"V_CMPX_T_I16"}, // 183 + {amdgpu_gfx908_op_V_CMPX_F_U16,"V_CMPX_F_U16"}, // 184 + {amdgpu_gfx908_op_V_CMPX_LT_U16,"V_CMPX_LT_U16"}, // 185 + {amdgpu_gfx908_op_V_CMPX_EQ_U16,"V_CMPX_EQ_U16"}, // 186 + {amdgpu_gfx908_op_V_CMPX_LE_U16,"V_CMPX_LE_U16"}, // 187 + {amdgpu_gfx908_op_V_CMPX_GT_U16,"V_CMPX_GT_U16"}, // 188 + {amdgpu_gfx908_op_V_CMPX_NE_U16,"V_CMPX_NE_U16"}, // 189 + {amdgpu_gfx908_op_V_CMPX_GE_U16,"V_CMPX_GE_U16"}, // 190 + {amdgpu_gfx908_op_V_CMPX_T_U16,"V_CMPX_T_U16"}, // 191 + {amdgpu_gfx908_op_V_CMP_F_I32,"V_CMP_F_I32"}, // 192 + {amdgpu_gfx908_op_V_CMP_LT_I32,"V_CMP_LT_I32"}, // 193 + {amdgpu_gfx908_op_V_CMP_EQ_I32,"V_CMP_EQ_I32"}, // 194 + {amdgpu_gfx908_op_V_CMP_LE_I32,"V_CMP_LE_I32"}, // 195 + {amdgpu_gfx908_op_V_CMP_GT_I32,"V_CMP_GT_I32"}, // 196 + {amdgpu_gfx908_op_V_CMP_NE_I32,"V_CMP_NE_I32"}, // 197 + {amdgpu_gfx908_op_V_CMP_GE_I32,"V_CMP_GE_I32"}, // 198 + {amdgpu_gfx908_op_V_CMP_T_I32,"V_CMP_T_I32"}, // 199 + {amdgpu_gfx908_op_V_CMP_F_U32,"V_CMP_F_U32"}, // 200 + {amdgpu_gfx908_op_V_CMP_LT_U32,"V_CMP_LT_U32"}, // 201 + {amdgpu_gfx908_op_V_CMP_EQ_U32,"V_CMP_EQ_U32"}, // 202 + {amdgpu_gfx908_op_V_CMP_LE_U32,"V_CMP_LE_U32"}, // 203 + {amdgpu_gfx908_op_V_CMP_GT_U32,"V_CMP_GT_U32"}, // 204 + {amdgpu_gfx908_op_V_CMP_NE_U32,"V_CMP_NE_U32"}, // 205 + {amdgpu_gfx908_op_V_CMP_GE_U32,"V_CMP_GE_U32"}, // 206 + {amdgpu_gfx908_op_V_CMP_T_U32,"V_CMP_T_U32"}, // 207 + {amdgpu_gfx908_op_V_CMPX_F_I32,"V_CMPX_F_I32"}, // 208 + {amdgpu_gfx908_op_V_CMPX_LT_I32,"V_CMPX_LT_I32"}, // 209 + {amdgpu_gfx908_op_V_CMPX_EQ_I32,"V_CMPX_EQ_I32"}, // 210 + {amdgpu_gfx908_op_V_CMPX_LE_I32,"V_CMPX_LE_I32"}, // 211 + {amdgpu_gfx908_op_V_CMPX_GT_I32,"V_CMPX_GT_I32"}, // 212 + {amdgpu_gfx908_op_V_CMPX_NE_I32,"V_CMPX_NE_I32"}, // 213 + {amdgpu_gfx908_op_V_CMPX_GE_I32,"V_CMPX_GE_I32"}, // 214 + {amdgpu_gfx908_op_V_CMPX_T_I32,"V_CMPX_T_I32"}, // 215 + {amdgpu_gfx908_op_V_CMPX_F_U32,"V_CMPX_F_U32"}, // 216 + {amdgpu_gfx908_op_V_CMPX_LT_U32,"V_CMPX_LT_U32"}, // 217 + {amdgpu_gfx908_op_V_CMPX_EQ_U32,"V_CMPX_EQ_U32"}, // 218 + {amdgpu_gfx908_op_V_CMPX_LE_U32,"V_CMPX_LE_U32"}, // 219 + {amdgpu_gfx908_op_V_CMPX_GT_U32,"V_CMPX_GT_U32"}, // 220 + {amdgpu_gfx908_op_V_CMPX_NE_U32,"V_CMPX_NE_U32"}, // 221 + {amdgpu_gfx908_op_V_CMPX_GE_U32,"V_CMPX_GE_U32"}, // 222 + {amdgpu_gfx908_op_V_CMPX_T_U32,"V_CMPX_T_U32"}, // 223 + {amdgpu_gfx908_op_V_CMP_F_I64,"V_CMP_F_I64"}, // 224 + {amdgpu_gfx908_op_V_CMP_LT_I64,"V_CMP_LT_I64"}, // 225 + {amdgpu_gfx908_op_V_CMP_EQ_I64,"V_CMP_EQ_I64"}, // 226 + {amdgpu_gfx908_op_V_CMP_LE_I64,"V_CMP_LE_I64"}, // 227 + {amdgpu_gfx908_op_V_CMP_GT_I64,"V_CMP_GT_I64"}, // 228 + {amdgpu_gfx908_op_V_CMP_NE_I64,"V_CMP_NE_I64"}, // 229 + {amdgpu_gfx908_op_V_CMP_GE_I64,"V_CMP_GE_I64"}, // 230 + {amdgpu_gfx908_op_V_CMP_T_I64,"V_CMP_T_I64"}, // 231 + {amdgpu_gfx908_op_V_CMP_F_U64,"V_CMP_F_U64"}, // 232 + {amdgpu_gfx908_op_V_CMP_LT_U64,"V_CMP_LT_U64"}, // 233 + {amdgpu_gfx908_op_V_CMP_EQ_U64,"V_CMP_EQ_U64"}, // 234 + {amdgpu_gfx908_op_V_CMP_LE_U64,"V_CMP_LE_U64"}, // 235 + {amdgpu_gfx908_op_V_CMP_GT_U64,"V_CMP_GT_U64"}, // 236 + {amdgpu_gfx908_op_V_CMP_NE_U64,"V_CMP_NE_U64"}, // 237 + {amdgpu_gfx908_op_V_CMP_GE_U64,"V_CMP_GE_U64"}, // 238 + {amdgpu_gfx908_op_V_CMP_T_U64,"V_CMP_T_U64"}, // 239 + {amdgpu_gfx908_op_V_CMPX_F_I64,"V_CMPX_F_I64"}, // 240 + {amdgpu_gfx908_op_V_CMPX_LT_I64,"V_CMPX_LT_I64"}, // 241 + {amdgpu_gfx908_op_V_CMPX_EQ_I64,"V_CMPX_EQ_I64"}, // 242 + {amdgpu_gfx908_op_V_CMPX_LE_I64,"V_CMPX_LE_I64"}, // 243 + {amdgpu_gfx908_op_V_CMPX_GT_I64,"V_CMPX_GT_I64"}, // 244 + {amdgpu_gfx908_op_V_CMPX_NE_I64,"V_CMPX_NE_I64"}, // 245 + {amdgpu_gfx908_op_V_CMPX_GE_I64,"V_CMPX_GE_I64"}, // 246 + {amdgpu_gfx908_op_V_CMPX_T_I64,"V_CMPX_T_I64"}, // 247 + {amdgpu_gfx908_op_V_CMPX_F_U64,"V_CMPX_F_U64"}, // 248 + {amdgpu_gfx908_op_V_CMPX_LT_U64,"V_CMPX_LT_U64"}, // 249 + {amdgpu_gfx908_op_V_CMPX_EQ_U64,"V_CMPX_EQ_U64"}, // 250 + {amdgpu_gfx908_op_V_CMPX_LE_U64,"V_CMPX_LE_U64"}, // 251 + {amdgpu_gfx908_op_V_CMPX_GT_U64,"V_CMPX_GT_U64"}, // 252 + {amdgpu_gfx908_op_V_CMPX_NE_U64,"V_CMPX_NE_U64"}, // 253 + {amdgpu_gfx908_op_V_CMPX_GE_U64,"V_CMPX_GE_U64"}, // 254 + {amdgpu_gfx908_op_V_CMPX_T_U64,"V_CMPX_T_U64"}, // 255 + }; // end ENC_VOPC_insn_table + + + }; + + } +} +#endif //INSTRUCTION_DECODER_GFX908_H diff --git a/instructionAPI/src/AMDGPU/gfx908/amdgpu_gfx908_decoder_impl.C b/instructionAPI/src/AMDGPU/gfx908/amdgpu_gfx908_decoder_impl.C new file mode 100644 index 0000000000..3cf637d0c1 --- /dev/null +++ b/instructionAPI/src/AMDGPU/gfx908/amdgpu_gfx908_decoder_impl.C @@ -0,0 +1,1383 @@ +#include "registers/AMDGPU/amdgpu_gfx908_regs.h" +#include "InstructionDecoder-amdgpu-gfx908.h" + +namespace Dyninst { +namespace InstructionAPI { + bool InstructionDecoder_amdgpu_gfx908::IS_ENC_SOP1(uint64_t I) + { + switch ( I & 0xff80ff00 ) { + case 0xbe800000: case 0xbe800100: case 0xbe800200: case 0xbe800300: + case 0xbe800400: case 0xbe800500: case 0xbe800600: case 0xbe800700: + case 0xbe800800: case 0xbe800900: case 0xbe800a00: case 0xbe800b00: + case 0xbe800c00: case 0xbe800d00: case 0xbe800e00: case 0xbe800f00: + case 0xbe801000: case 0xbe801100: case 0xbe801200: case 0xbe801300: + case 0xbe801400: case 0xbe801500: case 0xbe801600: case 0xbe801700: + case 0xbe801800: case 0xbe801900: case 0xbe801a00: case 0xbe801b00: + case 0xbe801c00: case 0xbe801d00: case 0xbe801e00: case 0xbe801f00: + case 0xbe802000: case 0xbe802100: case 0xbe802200: case 0xbe802300: + case 0xbe802400: case 0xbe802500: case 0xbe802600: case 0xbe802700: + case 0xbe802800: case 0xbe802900: case 0xbe802a00: case 0xbe802b00: + case 0xbe802c00: case 0xbe802d00: case 0xbe802e00: case 0xbe803000: + case 0xbe803200: case 0xbe803300: case 0xbe803400: case 0xbe803500: + case 0xbe803600: case 0xbe803700: + return true; + + default: + return false; + } + } + + bool InstructionDecoder_amdgpu_gfx908::IS_ENC_SOPC(uint64_t I) + { + switch ( I & 0xffff0000 ) { + case 0xbf000000: case 0xbf010000: case 0xbf020000: case 0xbf030000: + case 0xbf040000: case 0xbf050000: case 0xbf060000: case 0xbf070000: + case 0xbf080000: case 0xbf090000: case 0xbf0a0000: case 0xbf0b0000: + case 0xbf0c0000: case 0xbf0d0000: case 0xbf0e0000: case 0xbf0f0000: + case 0xbf100000: case 0xbf110000: case 0xbf120000: case 0xbf130000: + return true; + + default: + return false; + } + } + + bool InstructionDecoder_amdgpu_gfx908::IS_ENC_SOPP(uint64_t I) + { + switch ( I & 0xffff0000 ) { + case 0xbf800000: case 0xbf810000: case 0xbf820000: case 0xbf830000: + case 0xbf840000: case 0xbf850000: case 0xbf860000: case 0xbf870000: + case 0xbf880000: case 0xbf890000: case 0xbf8a0000: case 0xbf8b0000: + case 0xbf8c0000: case 0xbf8d0000: case 0xbf8e0000: case 0xbf8f0000: + case 0xbf900000: case 0xbf910000: case 0xbf920000: case 0xbf930000: + case 0xbf940000: case 0xbf950000: case 0xbf960000: case 0xbf970000: + case 0xbf980000: case 0xbf990000: case 0xbf9a0000: case 0xbf9b0000: + case 0xbf9c0000: case 0xbf9d0000: case 0xbf9e0000: + return true; + + default: + return false; + } + } + + bool InstructionDecoder_amdgpu_gfx908::IS_ENC_SOPK(uint64_t I) + { + switch ( I & 0xff800000 ) { + case 0xb0000000: case 0xb0800000: case 0xb1000000: case 0xb1800000: + case 0xb2000000: case 0xb2800000: case 0xb3000000: case 0xb3800000: + case 0xb4000000: case 0xb4800000: case 0xb5000000: case 0xb5800000: + case 0xb6000000: case 0xb6800000: case 0xb7000000: case 0xb7800000: + case 0xb8000000: case 0xb8800000: case 0xb9000000: case 0xba800000: + return true; + + default: + return false; + } + } + + bool InstructionDecoder_amdgpu_gfx908::IS_ENC_SOP2(uint64_t I) + { + switch ( I & 0xff800000 ) { + case 0x80000000: case 0x80800000: case 0x81000000: case 0x81800000: + case 0x82000000: case 0x82800000: case 0x83000000: case 0x83800000: + case 0x84000000: case 0x84800000: case 0x85000000: case 0x85800000: + case 0x86000000: case 0x86800000: case 0x87000000: case 0x87800000: + case 0x88000000: case 0x88800000: case 0x89000000: case 0x89800000: + case 0x8a000000: case 0x8a800000: case 0x8b000000: case 0x8b800000: + case 0x8c000000: case 0x8c800000: case 0x8d000000: case 0x8d800000: + case 0x8e000000: case 0x8e800000: case 0x8f000000: case 0x8f800000: + case 0x90000000: case 0x90800000: case 0x91000000: case 0x91800000: + case 0x92000000: case 0x92800000: case 0x93000000: case 0x93800000: + case 0x94000000: case 0x94800000: case 0x95000000: case 0x95800000: + case 0x96000000: case 0x96800000: case 0x97000000: case 0x97800000: + case 0x98000000: case 0x98800000: case 0x99000000: case 0x99800000: + case 0x9a000000: + return true; + + default: + return false; + } + } + + bool InstructionDecoder_amdgpu_gfx908::IS_ENC_SMEM(uint64_t I) + { + switch ( I & 0xfffc0000 ) { + case 0xc0000000: case 0xc0040000: case 0xc0080000: case 0xc00c0000: + case 0xc0100000: case 0xc0140000: case 0xc0180000: case 0xc01c0000: + case 0xc0200000: case 0xc0240000: case 0xc0280000: case 0xc02c0000: + case 0xc0300000: case 0xc0400000: case 0xc0440000: case 0xc0480000: + case 0xc0540000: case 0xc0580000: case 0xc05c0000: case 0xc0600000: + case 0xc0640000: case 0xc0680000: case 0xc0800000: case 0xc0840000: + case 0xc0880000: case 0xc08c0000: case 0xc0900000: case 0xc0940000: + case 0xc0980000: case 0xc09c0000: case 0xc0a00000: case 0xc0a40000: + case 0xc1000000: case 0xc1040000: case 0xc1080000: case 0xc10c0000: + case 0xc1100000: case 0xc1140000: case 0xc1180000: case 0xc11c0000: + case 0xc1200000: case 0xc1240000: case 0xc1280000: case 0xc12c0000: + case 0xc1300000: case 0xc1800000: case 0xc1840000: case 0xc1880000: + case 0xc18c0000: case 0xc1900000: case 0xc1940000: case 0xc1980000: + case 0xc19c0000: case 0xc1a00000: case 0xc1a40000: case 0xc1a80000: + case 0xc1ac0000: case 0xc1b00000: case 0xc2000000: case 0xc2040000: + case 0xc2080000: case 0xc20c0000: case 0xc2100000: case 0xc2140000: + case 0xc2180000: case 0xc21c0000: case 0xc2200000: case 0xc2240000: + case 0xc2280000: case 0xc22c0000: case 0xc2300000: case 0xc2800000: + case 0xc2840000: case 0xc2880000: case 0xc28c0000: case 0xc2900000: + case 0xc2940000: case 0xc2980000: case 0xc29c0000: case 0xc2a00000: + case 0xc2a40000: case 0xc2a80000: case 0xc2ac0000: case 0xc2b00000: + return true; + + default: + return false; + } + } + + bool InstructionDecoder_amdgpu_gfx908::IS_ENC_VOP1(uint64_t I) + { + switch ( I & 0xfe01fe00 ) { + case 0x7e000000: case 0x7e000200: case 0x7e000400: case 0x7e000600: + case 0x7e000800: case 0x7e000a00: case 0x7e000c00: case 0x7e000e00: + case 0x7e001000: case 0x7e001400: case 0x7e001600: case 0x7e001800: + case 0x7e001a00: case 0x7e001c00: case 0x7e001e00: case 0x7e002000: + case 0x7e002200: case 0x7e002400: case 0x7e002600: case 0x7e002800: + case 0x7e002a00: case 0x7e002c00: case 0x7e002e00: case 0x7e003000: + case 0x7e003200: case 0x7e003400: case 0x7e003600: case 0x7e003800: + case 0x7e003a00: case 0x7e003c00: case 0x7e003e00: case 0x7e004000: + case 0x7e004200: case 0x7e004400: case 0x7e004600: case 0x7e004800: + case 0x7e004a00: case 0x7e004c00: case 0x7e004e00: case 0x7e005000: + case 0x7e005200: case 0x7e005400: case 0x7e005600: case 0x7e005800: + case 0x7e005a00: case 0x7e005c00: case 0x7e005e00: case 0x7e006000: + case 0x7e006200: case 0x7e006400: case 0x7e006600: case 0x7e006800: + case 0x7e006a00: case 0x7e006e00: case 0x7e007200: case 0x7e007400: + case 0x7e007600: case 0x7e007800: case 0x7e007a00: case 0x7e007c00: + case 0x7e007e00: case 0x7e008000: case 0x7e008200: case 0x7e008400: + case 0x7e008600: case 0x7e008800: case 0x7e008a00: case 0x7e008c00: + case 0x7e008e00: case 0x7e009000: case 0x7e009200: case 0x7e009400: + case 0x7e009600: case 0x7e009800: case 0x7e009a00: case 0x7e009c00: + case 0x7e009e00: case 0x7e00a200: + return true; + + default: + return false; + } + } + + bool InstructionDecoder_amdgpu_gfx908::IS_ENC_VOPC(uint64_t I) + { + switch ( I & 0xfffe0000 ) { + case 0x7c200000: case 0x7c220000: case 0x7c240000: case 0x7c260000: + case 0x7c280000: case 0x7c2a0000: case 0x7c400000: case 0x7c420000: + case 0x7c440000: case 0x7c460000: case 0x7c480000: case 0x7c4a0000: + case 0x7c4c0000: case 0x7c4e0000: case 0x7c500000: case 0x7c520000: + case 0x7c540000: case 0x7c560000: case 0x7c580000: case 0x7c5a0000: + case 0x7c5c0000: case 0x7c5e0000: case 0x7c600000: case 0x7c620000: + case 0x7c640000: case 0x7c660000: case 0x7c680000: case 0x7c6a0000: + case 0x7c6c0000: case 0x7c6e0000: case 0x7c700000: case 0x7c720000: + case 0x7c740000: case 0x7c760000: case 0x7c780000: case 0x7c7a0000: + case 0x7c7c0000: case 0x7c7e0000: case 0x7c800000: case 0x7c820000: + case 0x7c840000: case 0x7c860000: case 0x7c880000: case 0x7c8a0000: + case 0x7c8c0000: case 0x7c8e0000: case 0x7c900000: case 0x7c920000: + case 0x7c940000: case 0x7c960000: case 0x7c980000: case 0x7c9a0000: + case 0x7c9c0000: case 0x7c9e0000: case 0x7ca00000: case 0x7ca20000: + case 0x7ca40000: case 0x7ca60000: case 0x7ca80000: case 0x7caa0000: + case 0x7cac0000: case 0x7cae0000: case 0x7cb00000: case 0x7cb20000: + case 0x7cb40000: case 0x7cb60000: case 0x7cb80000: case 0x7cba0000: + case 0x7cbc0000: case 0x7cbe0000: case 0x7cc00000: case 0x7cc20000: + case 0x7cc40000: case 0x7cc60000: case 0x7cc80000: case 0x7cca0000: + case 0x7ccc0000: case 0x7cce0000: case 0x7cd00000: case 0x7cd20000: + case 0x7cd40000: case 0x7cd60000: case 0x7cd80000: case 0x7cda0000: + case 0x7cdc0000: case 0x7cde0000: case 0x7ce00000: case 0x7ce20000: + case 0x7ce40000: case 0x7ce60000: case 0x7ce80000: case 0x7cea0000: + case 0x7cec0000: case 0x7cee0000: case 0x7cf00000: case 0x7cf20000: + case 0x7cf40000: case 0x7cf60000: case 0x7cf80000: case 0x7cfa0000: + case 0x7cfc0000: case 0x7cfe0000: case 0x7d400000: case 0x7d420000: + case 0x7d440000: case 0x7d460000: case 0x7d480000: case 0x7d4a0000: + case 0x7d4c0000: case 0x7d4e0000: case 0x7d500000: case 0x7d520000: + case 0x7d540000: case 0x7d560000: case 0x7d580000: case 0x7d5a0000: + case 0x7d5c0000: case 0x7d5e0000: case 0x7d600000: case 0x7d620000: + case 0x7d640000: case 0x7d660000: case 0x7d680000: case 0x7d6a0000: + case 0x7d6c0000: case 0x7d6e0000: case 0x7d700000: case 0x7d720000: + case 0x7d740000: case 0x7d760000: case 0x7d780000: case 0x7d7a0000: + case 0x7d7c0000: case 0x7d7e0000: case 0x7d800000: case 0x7d820000: + case 0x7d840000: case 0x7d860000: case 0x7d880000: case 0x7d8a0000: + case 0x7d8c0000: case 0x7d8e0000: case 0x7d900000: case 0x7d920000: + case 0x7d940000: case 0x7d960000: case 0x7d980000: case 0x7d9a0000: + case 0x7d9c0000: case 0x7d9e0000: case 0x7da00000: case 0x7da20000: + case 0x7da40000: case 0x7da60000: case 0x7da80000: case 0x7daa0000: + case 0x7dac0000: case 0x7dae0000: case 0x7db00000: case 0x7db20000: + case 0x7db40000: case 0x7db60000: case 0x7db80000: case 0x7dba0000: + case 0x7dbc0000: case 0x7dbe0000: case 0x7dc00000: case 0x7dc20000: + case 0x7dc40000: case 0x7dc60000: case 0x7dc80000: case 0x7dca0000: + case 0x7dcc0000: case 0x7dce0000: case 0x7dd00000: case 0x7dd20000: + case 0x7dd40000: case 0x7dd60000: case 0x7dd80000: case 0x7dda0000: + case 0x7ddc0000: case 0x7dde0000: case 0x7de00000: case 0x7de20000: + case 0x7de40000: case 0x7de60000: case 0x7de80000: case 0x7dea0000: + case 0x7dec0000: case 0x7dee0000: case 0x7df00000: case 0x7df20000: + case 0x7df40000: case 0x7df60000: case 0x7df80000: case 0x7dfa0000: + case 0x7dfc0000: case 0x7dfe0000: + return true; + + default: + return false; + } + } + + bool InstructionDecoder_amdgpu_gfx908::IS_ENC_VOP2(uint64_t I) + { + switch ( I & 0xfe000000 ) { + case 0x0: case 0x2000000: case 0x4000000: case 0x6000000: + case 0x8000000: case 0xa000000: case 0xc000000: case 0xe000000: + case 0x10000000: case 0x12000000: case 0x14000000: case 0x16000000: + case 0x18000000: case 0x1a000000: case 0x1c000000: case 0x1e000000: + case 0x20000000: case 0x22000000: case 0x24000000: case 0x26000000: + case 0x28000000: case 0x2a000000: case 0x2c000000: case 0x32000000: + case 0x34000000: case 0x36000000: case 0x38000000: case 0x3a000000: + case 0x3c000000: case 0x3e000000: case 0x40000000: case 0x42000000: + case 0x44000000: case 0x46000000: case 0x4c000000: case 0x4e000000: + case 0x50000000: case 0x52000000: case 0x54000000: case 0x56000000: + case 0x58000000: case 0x5a000000: case 0x5c000000: case 0x5e000000: + case 0x60000000: case 0x62000000: case 0x64000000: case 0x66000000: + case 0x68000000: case 0x6a000000: case 0x6c000000: case 0x6e000000: + case 0x70000000: case 0x72000000: case 0x74000000: case 0x76000000: + case 0x78000000: case 0x7a000000: + return true; + + default: + return false; + } + } + + bool InstructionDecoder_amdgpu_gfx908::IS_ENC_VINTRP(uint64_t I) + { + switch ( I & 0xfc030000 ) { + case 0xd4000000: case 0xd4010000: case 0xd4020000: + return true; + + default: + return false; + } + } + + bool InstructionDecoder_amdgpu_gfx908::IS_ENC_VOP3P(uint64_t I) + { + switch ( I & 0xffff0000 ) { + case 0xd3800000: case 0xd3810000: case 0xd3820000: case 0xd3830000: + case 0xd3840000: case 0xd3850000: case 0xd3860000: case 0xd3870000: + case 0xd3880000: case 0xd3890000: case 0xd38a0000: case 0xd38b0000: + case 0xd38c0000: case 0xd38d0000: case 0xd38e0000: case 0xd38f0000: + case 0xd3900000: case 0xd3910000: case 0xd3920000: case 0xd3a00000: + case 0xd3a10000: case 0xd3a20000: case 0xd3a30000: case 0xd3a60000: + case 0xd3a70000: case 0xd3a80000: case 0xd3a90000: case 0xd3aa0000: + case 0xd3ab0000: case 0xd3d80000: case 0xd3d90000: + return true; + + default: + return false; + } + } + + bool InstructionDecoder_amdgpu_gfx908::IS_ENC_VOP3(uint64_t I) + { + switch ( I & 0xffff0000 ) { + case 0xd2700000: case 0xd2710000: case 0xd2720000: case 0xd1400000: + case 0xd1410000: case 0xd1420000: case 0xd1430000: case 0xd1440000: + case 0xd1450000: case 0xd1460000: case 0xd1470000: case 0xd1480000: + case 0xd14a0000: case 0xd14b0000: case 0xd14c0000: case 0xd14d0000: + case 0xd14e0000: case 0xd14f0000: case 0xd1500000: case 0xd1510000: + case 0xd1520000: case 0xd1530000: case 0xd1540000: case 0xd1550000: + case 0xd1560000: case 0xd1570000: case 0xd1580000: case 0xd1590000: + case 0xd15a0000: case 0xd15b0000: case 0xd15c0000: case 0xd15d0000: + case 0xd15e0000: case 0xd15f0000: case 0xd1600000: case 0xd1610000: + case 0xd1620000: case 0xd1630000: case 0xd1640000: case 0xd1650000: + case 0xd1660000: case 0xd1670000: case 0xd1680000: case 0xd1690000: + case 0xd16a0000: case 0xd16b0000: case 0xd16c0000: case 0xd16d0000: + case 0xd16e0000: case 0xd16f0000: case 0xd1700000: case 0xd1710000: + case 0xd1720000: case 0xd1730000: case 0xd1740000: case 0xd1750000: + case 0xd1770000: case 0xd1790000: case 0xd17a0000: case 0xd17b0000: + case 0xd17c0000: case 0xd17d0000: case 0xd17e0000: case 0xd17f0000: + case 0xd1800000: case 0xd1810000: case 0xd1820000: case 0xd1830000: + case 0xd1840000: case 0xd1850000: case 0xd1860000: case 0xd1870000: + case 0xd1880000: case 0xd1890000: case 0xd18a0000: case 0xd18b0000: + case 0xd18c0000: case 0xd18d0000: case 0xd18e0000: case 0xd18f0000: + case 0xd1910000: case 0xd1000000: case 0xd1010000: case 0xd1020000: + case 0xd1030000: case 0xd1040000: case 0xd1050000: case 0xd1060000: + case 0xd1070000: case 0xd1080000: case 0xd1090000: case 0xd10a0000: + case 0xd10b0000: case 0xd10c0000: case 0xd10d0000: case 0xd10e0000: + case 0xd10f0000: case 0xd1100000: case 0xd1110000: case 0xd1120000: + case 0xd1130000: case 0xd1140000: case 0xd1150000: case 0xd1160000: + case 0xd11f0000: case 0xd1200000: case 0xd1210000: case 0xd1220000: + case 0xd1230000: case 0xd1260000: case 0xd1270000: case 0xd1280000: + case 0xd1290000: case 0xd12a0000: case 0xd12b0000: case 0xd12c0000: + case 0xd12d0000: case 0xd12e0000: case 0xd12f0000: case 0xd1300000: + case 0xd1310000: case 0xd1320000: case 0xd1330000: case 0xd1340000: + case 0xd1350000: case 0xd1360000: case 0xd1370000: case 0xd1380000: + case 0xd1390000: case 0xd13a0000: case 0xd13b0000: case 0xd13c0000: + case 0xd13d0000: case 0xd1c00000: case 0xd1c10000: case 0xd1c20000: + case 0xd1c30000: case 0xd1c40000: case 0xd1c50000: case 0xd1c60000: + case 0xd1c70000: case 0xd1c80000: case 0xd1c90000: case 0xd1ca0000: + case 0xd1cb0000: case 0xd1cc0000: case 0xd1cd0000: case 0xd1ce0000: + case 0xd1cf0000: case 0xd1d00000: case 0xd1d10000: case 0xd1d20000: + case 0xd1d30000: case 0xd1d40000: case 0xd1d50000: case 0xd1d60000: + case 0xd1d70000: case 0xd1d80000: case 0xd1d90000: case 0xd1da0000: + case 0xd1db0000: case 0xd1dc0000: case 0xd1dd0000: case 0xd1de0000: + case 0xd1df0000: case 0xd1e20000: case 0xd1e30000: case 0xd1e40000: + case 0xd1e50000: case 0xd1e60000: case 0xd1e70000: case 0xd1ea0000: + case 0xd1eb0000: case 0xd1ec0000: case 0xd1ed0000: case 0xd1ee0000: + case 0xd1ef0000: case 0xd1f00000: case 0xd1f10000: case 0xd1f20000: + case 0xd1f30000: case 0xd1f40000: case 0xd1f50000: case 0xd1f60000: + case 0xd1f70000: case 0xd1f80000: case 0xd1f90000: case 0xd1fa0000: + case 0xd1fb0000: case 0xd1fc0000: case 0xd1fd0000: case 0xd1fe0000: + case 0xd1ff0000: case 0xd2000000: case 0xd2010000: case 0xd2020000: + case 0xd2030000: case 0xd2040000: case 0xd2050000: case 0xd2060000: + case 0xd2070000: case 0xd2740000: case 0xd2750000: case 0xd2760000: + case 0xd2770000: case 0xd2800000: case 0xd2810000: case 0xd2820000: + case 0xd2830000: case 0xd2840000: case 0xd2850000: case 0xd2860000: + case 0xd2870000: case 0xd2880000: case 0xd2890000: case 0xd28a0000: + case 0xd28b0000: case 0xd28c0000: case 0xd28d0000: case 0xd28f0000: + case 0xd2900000: case 0xd2910000: case 0xd2920000: case 0xd2930000: + case 0xd2940000: case 0xd2950000: case 0xd2960000: case 0xd2970000: + case 0xd2980000: case 0xd2990000: case 0xd29a0000: case 0xd29c0000: + case 0xd29d0000: case 0xd29e0000: case 0xd29f0000: case 0xd2a00000: + case 0xd0100000: case 0xd0110000: case 0xd0120000: case 0xd0130000: + case 0xd0140000: case 0xd0150000: case 0xd0200000: case 0xd0210000: + case 0xd0220000: case 0xd0230000: case 0xd0240000: case 0xd0250000: + case 0xd0260000: case 0xd0270000: case 0xd0280000: case 0xd0290000: + case 0xd02a0000: case 0xd02b0000: case 0xd02c0000: case 0xd02d0000: + case 0xd02e0000: case 0xd02f0000: case 0xd0300000: case 0xd0310000: + case 0xd0320000: case 0xd0330000: case 0xd0340000: case 0xd0350000: + case 0xd0360000: case 0xd0370000: case 0xd0380000: case 0xd0390000: + case 0xd03a0000: case 0xd03b0000: case 0xd03c0000: case 0xd03d0000: + case 0xd03e0000: case 0xd03f0000: case 0xd0400000: case 0xd0410000: + case 0xd0420000: case 0xd0430000: case 0xd0440000: case 0xd0450000: + case 0xd0460000: case 0xd0470000: case 0xd0480000: case 0xd0490000: + case 0xd04a0000: case 0xd04b0000: case 0xd04c0000: case 0xd04d0000: + case 0xd04e0000: case 0xd04f0000: case 0xd0500000: case 0xd0510000: + case 0xd0520000: case 0xd0530000: case 0xd0540000: case 0xd0550000: + case 0xd0560000: case 0xd0570000: case 0xd0580000: case 0xd0590000: + case 0xd05a0000: case 0xd05b0000: case 0xd05c0000: case 0xd05d0000: + case 0xd05e0000: case 0xd05f0000: case 0xd0600000: case 0xd0610000: + case 0xd0620000: case 0xd0630000: case 0xd0640000: case 0xd0650000: + case 0xd0660000: case 0xd0670000: case 0xd0680000: case 0xd0690000: + case 0xd06a0000: case 0xd06b0000: case 0xd06c0000: case 0xd06d0000: + case 0xd06e0000: case 0xd06f0000: case 0xd0700000: case 0xd0710000: + case 0xd0720000: case 0xd0730000: case 0xd0740000: case 0xd0750000: + case 0xd0760000: case 0xd0770000: case 0xd0780000: case 0xd0790000: + case 0xd07a0000: case 0xd07b0000: case 0xd07c0000: case 0xd07d0000: + case 0xd07e0000: case 0xd07f0000: case 0xd0a00000: case 0xd0a10000: + case 0xd0a20000: case 0xd0a30000: case 0xd0a40000: case 0xd0a50000: + case 0xd0a60000: case 0xd0a70000: case 0xd0a80000: case 0xd0a90000: + case 0xd0aa0000: case 0xd0ab0000: case 0xd0ac0000: case 0xd0ad0000: + case 0xd0ae0000: case 0xd0af0000: case 0xd0b00000: case 0xd0b10000: + case 0xd0b20000: case 0xd0b30000: case 0xd0b40000: case 0xd0b50000: + case 0xd0b60000: case 0xd0b70000: case 0xd0b80000: case 0xd0b90000: + case 0xd0ba0000: case 0xd0bb0000: case 0xd0bc0000: case 0xd0bd0000: + case 0xd0be0000: case 0xd0bf0000: case 0xd0c00000: case 0xd0c10000: + case 0xd0c20000: case 0xd0c30000: case 0xd0c40000: case 0xd0c50000: + case 0xd0c60000: case 0xd0c70000: case 0xd0c80000: case 0xd0c90000: + case 0xd0ca0000: case 0xd0cb0000: case 0xd0cc0000: case 0xd0cd0000: + case 0xd0ce0000: case 0xd0cf0000: case 0xd0d00000: case 0xd0d10000: + case 0xd0d20000: case 0xd0d30000: case 0xd0d40000: case 0xd0d50000: + case 0xd0d60000: case 0xd0d70000: case 0xd0d80000: case 0xd0d90000: + case 0xd0da0000: case 0xd0db0000: case 0xd0dc0000: case 0xd0dd0000: + case 0xd0de0000: case 0xd0df0000: case 0xd0e00000: case 0xd0e10000: + case 0xd0e20000: case 0xd0e30000: case 0xd0e40000: case 0xd0e50000: + case 0xd0e60000: case 0xd0e70000: case 0xd0e80000: case 0xd0e90000: + case 0xd0ea0000: case 0xd0eb0000: case 0xd0ec0000: case 0xd0ed0000: + case 0xd0ee0000: case 0xd0ef0000: case 0xd0f00000: case 0xd0f10000: + case 0xd0f20000: case 0xd0f30000: case 0xd0f40000: case 0xd0f50000: + case 0xd0f60000: case 0xd0f70000: case 0xd0f80000: case 0xd0f90000: + case 0xd0fa0000: case 0xd0fb0000: case 0xd0fc0000: case 0xd0fd0000: + case 0xd0fe0000: case 0xd0ff0000: + return true; + + default: + return false; + } + } + + bool InstructionDecoder_amdgpu_gfx908::IS_ENC_DS(uint64_t I) + { + switch ( I & 0xfdfe0000 ) { + case 0xd8000000: case 0xd8020000: case 0xd8040000: case 0xd8060000: + case 0xd8080000: case 0xd80a0000: case 0xd80c0000: case 0xd80e0000: + case 0xd8100000: case 0xd8120000: case 0xd8140000: case 0xd8160000: + case 0xd8180000: case 0xd81a0000: case 0xd81c0000: case 0xd81e0000: + case 0xd8200000: case 0xd8220000: case 0xd8240000: case 0xd8260000: + case 0xd8280000: case 0xd82a0000: case 0xd83a0000: case 0xd83c0000: + case 0xd83e0000: case 0xd8400000: case 0xd8420000: case 0xd8440000: + case 0xd8460000: case 0xd8480000: case 0xd84a0000: case 0xd84c0000: + case 0xd84e0000: case 0xd8500000: case 0xd8520000: case 0xd8540000: + case 0xd8560000: case 0xd8580000: case 0xd85a0000: case 0xd85c0000: + case 0xd85e0000: case 0xd8600000: case 0xd8620000: case 0xd8640000: + case 0xd8660000: case 0xd8680000: case 0xd86a0000: case 0xd86c0000: + case 0xd86e0000: case 0xd8700000: case 0xd8720000: case 0xd8740000: + case 0xd8760000: case 0xd8780000: case 0xd87a0000: case 0xd87c0000: + case 0xd87e0000: case 0xd8800000: case 0xd8820000: case 0xd8840000: + case 0xd8860000: case 0xd8880000: case 0xd88a0000: case 0xd88c0000: + case 0xd88e0000: case 0xd8900000: case 0xd8920000: case 0xd8940000: + case 0xd8960000: case 0xd8980000: case 0xd89a0000: case 0xd89c0000: + case 0xd89e0000: case 0xd8a00000: case 0xd8a20000: case 0xd8a40000: + case 0xd8a60000: case 0xd8a80000: case 0xd8aa0000: case 0xd8ac0000: + case 0xd8ae0000: case 0xd8b00000: case 0xd8b20000: case 0xd8b40000: + case 0xd8b60000: case 0xd8c00000: case 0xd8c20000: case 0xd8c40000: + case 0xd8c60000: case 0xd8c80000: case 0xd8ca0000: case 0xd8cc0000: + case 0xd8ce0000: case 0xd8d00000: case 0xd8d20000: case 0xd8d40000: + case 0xd8d60000: case 0xd8d80000: case 0xd8da0000: case 0xd8dc0000: + case 0xd8de0000: case 0xd8e00000: case 0xd8e20000: case 0xd8e40000: + case 0xd8e60000: case 0xd8ec0000: case 0xd8ee0000: case 0xd8f00000: + case 0xd8fc0000: case 0xd9000000: case 0xd9020000: case 0xd9040000: + case 0xd9060000: case 0xd9080000: case 0xd90a0000: case 0xd90c0000: + case 0xd90e0000: case 0xd9100000: case 0xd9120000: case 0xd9140000: + case 0xd9160000: case 0xd91a0000: case 0xd9240000: case 0xd9260000: + case 0xd92a0000: case 0xd9300000: case 0xd9320000: case 0xd9340000: + case 0xd9360000: case 0xd9380000: case 0xd93a0000: case 0xd96c0000: + case 0xd97a0000: case 0xd97c0000: case 0xd97e0000: case 0xd9800000: + case 0xd9820000: case 0xd9840000: case 0xd9860000: case 0xd9880000: + case 0xd98a0000: case 0xd98c0000: case 0xd98e0000: case 0xd9900000: + case 0xd9920000: case 0xd9940000: case 0xd9960000: case 0xd99a0000: + case 0xd9a40000: case 0xd9a60000: case 0xd9bc0000: case 0xd9be0000: + case 0xd9fc0000: case 0xd9fe0000: + return true; + + default: + return false; + } + } + + bool InstructionDecoder_amdgpu_gfx908::IS_ENC_MUBUF(uint64_t I) + { + switch ( I & 0xfdfc0000 ) { + case 0xe0000000: case 0xe0040000: case 0xe0080000: case 0xe00c0000: + case 0xe0100000: case 0xe0140000: case 0xe0180000: case 0xe01c0000: + case 0xe0200000: case 0xe0240000: case 0xe0280000: case 0xe02c0000: + case 0xe0300000: case 0xe0340000: case 0xe0380000: case 0xe03c0000: + case 0xe0400000: case 0xe0440000: case 0xe0480000: case 0xe04c0000: + case 0xe0500000: case 0xe0540000: case 0xe0580000: case 0xe05c0000: + case 0xe0600000: case 0xe0640000: case 0xe0680000: case 0xe06c0000: + case 0xe0700000: case 0xe0740000: case 0xe0780000: case 0xe07c0000: + case 0xe0800000: case 0xe0840000: case 0xe0880000: case 0xe08c0000: + case 0xe0900000: case 0xe0940000: case 0xe0980000: case 0xe09c0000: + case 0xe0f40000: case 0xe0f80000: case 0xe0fc0000: case 0xe1000000: + case 0xe1040000: case 0xe1080000: case 0xe10c0000: case 0xe1100000: + case 0xe1140000: case 0xe1180000: case 0xe11c0000: case 0xe1200000: + case 0xe1240000: case 0xe1280000: case 0xe12c0000: case 0xe1300000: + case 0xe1340000: case 0xe1380000: case 0xe1800000: case 0xe1840000: + case 0xe1880000: case 0xe18c0000: case 0xe1900000: case 0xe1940000: + case 0xe1980000: case 0xe19c0000: case 0xe1a00000: case 0xe1a40000: + case 0xe1a80000: case 0xe1ac0000: case 0xe1b00000: + return true; + + default: + return false; + } + } + + bool InstructionDecoder_amdgpu_gfx908::IS_ENC_MTBUF(uint64_t I) + { + switch ( I & 0xfc078000 ) { + case 0xe8000000: case 0xe8008000: case 0xe8010000: case 0xe8018000: + case 0xe8020000: case 0xe8028000: case 0xe8030000: case 0xe8038000: + case 0xe8040000: case 0xe8048000: case 0xe8050000: case 0xe8058000: + case 0xe8060000: case 0xe8068000: case 0xe8070000: case 0xe8078000: + return true; + + default: + return false; + } + } + + bool InstructionDecoder_amdgpu_gfx908::IS_ENC_MIMG(uint64_t I) + { + switch ( I & 0xfdfc0000 ) { + case 0xf0000000: case 0xf0040000: case 0xf0080000: case 0xf00c0000: + case 0xf0100000: case 0xf0140000: case 0xf0200000: case 0xf0240000: + case 0xf0280000: case 0xf02c0000: case 0xf0380000: case 0xf0400000: + case 0xf0440000: case 0xf0480000: case 0xf04c0000: case 0xf0500000: + case 0xf0540000: case 0xf0580000: case 0xf05c0000: case 0xf0600000: + case 0xf0640000: case 0xf0680000: case 0xf06c0000: case 0xf0700000: + case 0xf0800000: case 0xf0840000: case 0xf0880000: case 0xf08c0000: + case 0xf0900000: case 0xf0940000: case 0xf0980000: case 0xf09c0000: + case 0xf0a00000: case 0xf0a40000: case 0xf0a80000: case 0xf0ac0000: + case 0xf0b00000: case 0xf0b40000: case 0xf0b80000: case 0xf0bc0000: + case 0xf0c00000: case 0xf0c40000: case 0xf0c80000: case 0xf0cc0000: + case 0xf0d00000: case 0xf0d40000: case 0xf0d80000: case 0xf0dc0000: + case 0xf0e00000: case 0xf0e40000: case 0xf0e80000: case 0xf0ec0000: + case 0xf0f00000: case 0xf0f40000: case 0xf0f80000: case 0xf0fc0000: + case 0xf1000000: case 0xf1040000: case 0xf1080000: case 0xf1100000: + case 0xf1140000: case 0xf1180000: case 0xf11c0000: case 0xf1200000: + case 0xf1240000: case 0xf1280000: case 0xf12c0000: case 0xf1300000: + case 0xf1340000: case 0xf1380000: case 0xf13c0000: case 0xf1400000: + case 0xf1440000: case 0xf1500000: case 0xf1540000: case 0xf1580000: + case 0xf15c0000: case 0xf1600000: case 0xf1640000: case 0xf1700000: + case 0xf1740000: case 0xf1780000: case 0xf17c0000: case 0xf1800000: + case 0xf1a00000: case 0xf1a40000: case 0xf1a80000: case 0xf1ac0000: + case 0xf1b00000: case 0xf1b40000: case 0xf1b80000: case 0xf1bc0000: + return true; + + default: + return false; + } + } + + bool InstructionDecoder_amdgpu_gfx908::IS_ENC_EXP(uint64_t I) + { + switch ( I & 0xfc000000 ) { + case 0xc4000000: + return true; + + default: + return false; + } + } + + bool InstructionDecoder_amdgpu_gfx908::IS_ENC_FLAT(uint64_t I) + { + switch ( I & 0xfdfcc000 ) { + case 0xdc400000: case 0xdc440000: case 0xdc480000: case 0xdc4c0000: + case 0xdc500000: case 0xdc540000: case 0xdc580000: case 0xdc5c0000: + case 0xdc600000: case 0xdc640000: case 0xdc680000: case 0xdc6c0000: + case 0xdc700000: case 0xdc740000: case 0xdc780000: case 0xdc7c0000: + case 0xdc800000: case 0xdc840000: case 0xdc880000: case 0xdc8c0000: + case 0xdc900000: case 0xdc940000: case 0xdd000000: case 0xdd040000: + case 0xdd080000: case 0xdd0c0000: case 0xdd100000: case 0xdd140000: + case 0xdd180000: case 0xdd1c0000: case 0xdd200000: case 0xdd240000: + case 0xdd280000: case 0xdd2c0000: case 0xdd300000: case 0xdd800000: + case 0xdd840000: case 0xdd880000: case 0xdd8c0000: case 0xdd900000: + case 0xdd940000: case 0xdd980000: case 0xdd9c0000: case 0xdda00000: + case 0xdda40000: case 0xdda80000: case 0xddac0000: case 0xddb00000: + return true; + + default: + return false; + } + } + + bool InstructionDecoder_amdgpu_gfx908::IS_ENC_FLAT_GLBL(uint64_t I) + { + switch ( I & 0xfdfcc000 ) { + case 0xdc408000: case 0xdc448000: case 0xdc488000: case 0xdc4c8000: + case 0xdc508000: case 0xdc548000: case 0xdc588000: case 0xdc5c8000: + case 0xdc608000: case 0xdc648000: case 0xdc688000: case 0xdc6c8000: + case 0xdc708000: case 0xdc748000: case 0xdc788000: case 0xdc7c8000: + case 0xdc808000: case 0xdc848000: case 0xdc888000: case 0xdc8c8000: + case 0xdc908000: case 0xdc948000: case 0xdd008000: case 0xdd048000: + case 0xdd088000: case 0xdd0c8000: case 0xdd108000: case 0xdd148000: + case 0xdd188000: case 0xdd1c8000: case 0xdd208000: case 0xdd248000: + case 0xdd288000: case 0xdd2c8000: case 0xdd308000: case 0xdd348000: + case 0xdd388000: case 0xdd808000: case 0xdd848000: case 0xdd888000: + case 0xdd8c8000: case 0xdd908000: case 0xdd948000: case 0xdd988000: + case 0xdd9c8000: case 0xdda08000: case 0xdda48000: case 0xdda88000: + case 0xddac8000: case 0xddb08000: + return true; + + default: + return false; + } + } + + bool InstructionDecoder_amdgpu_gfx908::IS_ENC_FLAT_SCRATCH(uint64_t I) + { + switch ( I & 0xfdfcc000 ) { + case 0xdc404000: case 0xdc444000: case 0xdc484000: case 0xdc4c4000: + case 0xdc504000: case 0xdc544000: case 0xdc584000: case 0xdc5c4000: + case 0xdc604000: case 0xdc644000: case 0xdc684000: case 0xdc6c4000: + case 0xdc704000: case 0xdc744000: case 0xdc784000: case 0xdc7c4000: + case 0xdc804000: case 0xdc844000: case 0xdc884000: case 0xdc8c4000: + case 0xdc904000: case 0xdc944000: + return true; + + default: + return false; + } + } + + bool InstructionDecoder_amdgpu_gfx908::IS_SOPK_INST_LITERAL_(uint64_t I) + { + switch ( I & 0xff800000 ) { + case 0xba000000: + return true; + + default: + return false; + } + } + + bool InstructionDecoder_amdgpu_gfx908::IS_ENC_VOP2_LITERAL(uint64_t I) + { + switch ( I & 0xfe000000 ) { + case 0x2e000000: case 0x30000000: case 0x48000000: case 0x4a000000: + return true; + + default: + return false; + } + } + + bool InstructionDecoder_amdgpu_gfx908::IS_ENC_VOP3B(uint64_t I) + { + switch ( I & 0xffff0000 ) { + case 0xd1190000: case 0xd11a0000: case 0xd11b0000: case 0xd11c0000: + case 0xd11d0000: case 0xd11e0000: case 0xd1e00000: case 0xd1e10000: + case 0xd1e80000: case 0xd1e90000: + return true; + + default: + return false; + } + } + + bool InstructionDecoder_amdgpu_gfx908::IS_ENC_VOP3P_MFMA(uint64_t I) + { + switch ( I & 0xffff0000 ) { + case 0xd3c00000: case 0xd3c10000: case 0xd3c20000: case 0xd3c40000: + case 0xd3c50000: case 0xd3c80000: case 0xd3c90000: case 0xd3ca0000: + case 0xd3cc0000: case 0xd3cd0000: case 0xd3d00000: case 0xd3d10000: + case 0xd3d20000: case 0xd3d40000: case 0xd3d50000: case 0xd3e80000: + case 0xd3e90000: case 0xd3eb0000: case 0xd3ec0000: case 0xd3ed0000: + return true; + + default: + return false; + } + } + + void InstructionDecoder_amdgpu_gfx908::decodeENC_SOP1() + { + insn_size = 4; + layout_ENC_SOP1 & layout = insn_layout.ENC_SOP1; + layout.ENCODING = longfield<23,31>(insn_long); + layout.OP = longfield<8,15>(insn_long); + layout.SDST = longfield<16,22>(insn_long); + layout.SSRC0 = longfield<0,7>(insn_long); + assert(isArrayIndexValid(ENC_SOP1_insn_table, layout.OP) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = ENC_SOP1_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_SOP1Operands(); + this->insn_in_progress->updateSize(insn_size + immLen); + this->insn_in_progress->updateMnemonic(std::string(insn_entry.mnemonic) + extension); + } + + void InstructionDecoder_amdgpu_gfx908::decodeENC_SOPC() + { + insn_size = 4; + layout_ENC_SOPC & layout = insn_layout.ENC_SOPC; + layout.ENCODING = longfield<23,31>(insn_long); + layout.OP = longfield<16,22>(insn_long); + layout.SSRC0 = longfield<0,7>(insn_long); + layout.SSRC1 = longfield<8,15>(insn_long); + assert(isArrayIndexValid(ENC_SOPC_insn_table, layout.OP) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = ENC_SOPC_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_SOPCOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); + this->insn_in_progress->updateMnemonic(std::string(insn_entry.mnemonic) + extension); + } + + void InstructionDecoder_amdgpu_gfx908::decodeENC_SOPP() + { + insn_size = 4; + layout_ENC_SOPP & layout = insn_layout.ENC_SOPP; + layout.ENCODING = longfield<23,31>(insn_long); + layout.OP = longfield<16,22>(insn_long); + layout.SIMM16 = longfield<0,15>(insn_long); + assert(isArrayIndexValid(ENC_SOPP_insn_table, layout.OP) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = ENC_SOPP_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_SOPPOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); + this->insn_in_progress->updateMnemonic(std::string(insn_entry.mnemonic) + extension); + } + + void InstructionDecoder_amdgpu_gfx908::decodeENC_SOPK() + { + insn_size = 4; + layout_ENC_SOPK & layout = insn_layout.ENC_SOPK; + layout.ENCODING = longfield<28,31>(insn_long); + layout.OP = longfield<23,27>(insn_long); + layout.SDST = longfield<16,22>(insn_long); + layout.SIMM16 = longfield<0,15>(insn_long); + assert(isArrayIndexValid(ENC_SOPK_insn_table, layout.OP) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = ENC_SOPK_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_SOPKOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); + this->insn_in_progress->updateMnemonic(std::string(insn_entry.mnemonic) + extension); + } + + void InstructionDecoder_amdgpu_gfx908::decodeENC_SOP2() + { + insn_size = 4; + layout_ENC_SOP2 & layout = insn_layout.ENC_SOP2; + layout.ENCODING = longfield<30,31>(insn_long); + layout.OP = longfield<23,29>(insn_long); + layout.SDST = longfield<16,22>(insn_long); + layout.SSRC0 = longfield<0,7>(insn_long); + layout.SSRC1 = longfield<8,15>(insn_long); + assert(isArrayIndexValid(ENC_SOP2_insn_table, layout.OP) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = ENC_SOP2_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_SOP2Operands(); + this->insn_in_progress->updateSize(insn_size + immLen); + this->insn_in_progress->updateMnemonic(std::string(insn_entry.mnemonic) + extension); + } + + void InstructionDecoder_amdgpu_gfx908::decodeENC_SMEM() + { + insn_size = 8; + layout_ENC_SMEM & layout = insn_layout.ENC_SMEM; + layout.ENCODING = longfield<26,31>(insn_long); + layout.GLC = longfield<16,16>(insn_long); + layout.IMM = longfield<17,17>(insn_long); + layout.NV = longfield<15,15>(insn_long); + layout.OFFSET = longfield<32,52>(insn_long); + layout.OP = longfield<18,25>(insn_long); + layout.SBASE = (longfield<0,5>(insn_long) << 1 ) | 0 ; + layout.SDATA = longfield<6,12>(insn_long); + layout.SOFFSET = longfield<57,63>(insn_long); + layout.SOFFSET_EN = longfield<14,14>(insn_long); + assert(isArrayIndexValid(ENC_SMEM_insn_table, layout.OP) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = ENC_SMEM_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_SMEMOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); + this->insn_in_progress->updateMnemonic(std::string(insn_entry.mnemonic) + extension); + } + + void InstructionDecoder_amdgpu_gfx908::decodeENC_VOP1() + { + insn_size = 4; + layout_ENC_VOP1 & layout = insn_layout.ENC_VOP1; + layout.ENCODING = longfield<25,31>(insn_long); + layout.OP = longfield<9,16>(insn_long); + layout.SRC0 = longfield<0,8>(insn_long); + layout.VDST = longfield<17,24>(insn_long); + assert(isArrayIndexValid(ENC_VOP1_insn_table, layout.OP) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = ENC_VOP1_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_VOP1Operands(); + this->insn_in_progress->updateSize(insn_size + immLen); + this->insn_in_progress->updateMnemonic(std::string(insn_entry.mnemonic) + extension); + } + + void InstructionDecoder_amdgpu_gfx908::decodeENC_VOPC() + { + insn_size = 4; + layout_ENC_VOPC & layout = insn_layout.ENC_VOPC; + layout.ENCODING = longfield<25,31>(insn_long); + layout.OP = longfield<17,24>(insn_long); + layout.SRC0 = longfield<0,8>(insn_long); + layout.VSRC1 = longfield<9,16>(insn_long); + assert(isArrayIndexValid(ENC_VOPC_insn_table, layout.OP) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = ENC_VOPC_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_VOPCOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); + this->insn_in_progress->updateMnemonic(std::string(insn_entry.mnemonic) + extension); + } + + void InstructionDecoder_amdgpu_gfx908::decodeENC_VOP2() + { + insn_size = 4; + layout_ENC_VOP2 & layout = insn_layout.ENC_VOP2; + layout.ENCODING = longfield<31,31>(insn_long); + layout.OP = longfield<25,30>(insn_long); + layout.SRC0 = longfield<0,8>(insn_long); + layout.VDST = longfield<17,24>(insn_long); + layout.VSRC1 = longfield<9,16>(insn_long); + assert(isArrayIndexValid(ENC_VOP2_insn_table, layout.OP) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = ENC_VOP2_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_VOP2Operands(); + this->insn_in_progress->updateSize(insn_size + immLen); + this->insn_in_progress->updateMnemonic(std::string(insn_entry.mnemonic) + extension); + } + + void InstructionDecoder_amdgpu_gfx908::decodeENC_VINTRP() + { + insn_size = 4; + layout_ENC_VINTRP & layout = insn_layout.ENC_VINTRP; + layout.ATTR = longfield<10,15>(insn_long); + layout.ATTRCHAN = longfield<8,9>(insn_long); + layout.ENCODING = longfield<26,31>(insn_long); + layout.OP = longfield<16,17>(insn_long); + layout.VDST = longfield<18,25>(insn_long); + layout.VSRC = longfield<0,7>(insn_long); + assert(isArrayIndexValid(ENC_VINTRP_insn_table, layout.OP) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = ENC_VINTRP_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_VINTRPOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); + this->insn_in_progress->updateMnemonic(std::string(insn_entry.mnemonic) + extension); + } + + void InstructionDecoder_amdgpu_gfx908::decodeENC_VOP3P() + { + insn_size = 8; + layout_ENC_VOP3P & layout = insn_layout.ENC_VOP3P; + layout.CLAMP = longfield<15,15>(insn_long); + layout.ENCODING = longfield<23,31>(insn_long); + layout.NEG = longfield<61,63>(insn_long); + layout.NEG_HI = longfield<8,10>(insn_long); + layout.OP = longfield<16,22>(insn_long); + layout.OP_SEL = longfield<11,13>(insn_long); + layout.OP_SEL_HI = longfield<59,60>(insn_long); + layout.OP_SEL_HI_2 = longfield<14,14>(insn_long); + layout.SRC0 = longfield<32,40>(insn_long); + layout.SRC1 = longfield<41,49>(insn_long); + layout.SRC2 = longfield<50,58>(insn_long); + layout.VDST = longfield<0,7>(insn_long); + assert(isArrayIndexValid(ENC_VOP3P_insn_table, layout.OP) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = ENC_VOP3P_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_VOP3POperands(); + this->insn_in_progress->updateSize(insn_size + immLen); + this->insn_in_progress->updateMnemonic(std::string(insn_entry.mnemonic) + extension); + } + + void InstructionDecoder_amdgpu_gfx908::decodeENC_VOP3() + { + insn_size = 8; + layout_ENC_VOP3 & layout = insn_layout.ENC_VOP3; + layout.ABS = longfield<8,10>(insn_long); + layout.CLAMP = longfield<15,15>(insn_long); + layout.ENCODING = longfield<26,31>(insn_long); + layout.NEG = longfield<61,63>(insn_long); + layout.OMOD = longfield<59,60>(insn_long); + layout.OP = longfield<16,25>(insn_long); + layout.OP_SEL = longfield<11,14>(insn_long); + layout.SRC0 = longfield<32,40>(insn_long); + layout.SRC1 = longfield<41,49>(insn_long); + layout.SRC2 = longfield<50,58>(insn_long); + layout.VDST = longfield<0,7>(insn_long); + assert(isArrayIndexValid(ENC_VOP3_insn_table, layout.OP) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = ENC_VOP3_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_VOP3Operands(); + this->insn_in_progress->updateSize(insn_size + immLen); + this->insn_in_progress->updateMnemonic(std::string(insn_entry.mnemonic) + extension); + } + + void InstructionDecoder_amdgpu_gfx908::decodeENC_DS() + { + insn_size = 8; + layout_ENC_DS & layout = insn_layout.ENC_DS; + layout.ADDR = longfield<32,39>(insn_long); + layout.DATA0 = longfield<40,47>(insn_long); + layout.DATA1 = longfield<48,55>(insn_long); + layout.ENCODING = longfield<26,31>(insn_long); + layout.GDS = longfield<16,16>(insn_long); + layout.OFFSET0 = longfield<0,7>(insn_long); + layout.OFFSET1 = longfield<8,15>(insn_long); + layout.OP = longfield<17,24>(insn_long); + layout.VDST = longfield<56,63>(insn_long); + assert(isArrayIndexValid(ENC_DS_insn_table, layout.OP) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = ENC_DS_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_DSOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); + this->insn_in_progress->updateMnemonic(std::string(insn_entry.mnemonic) + extension); + } + + void InstructionDecoder_amdgpu_gfx908::decodeENC_MUBUF() + { + insn_size = 8; + layout_ENC_MUBUF & layout = insn_layout.ENC_MUBUF; + layout.ENCODING = longfield<26,31>(insn_long); + layout.GLC = longfield<14,14>(insn_long); + layout.IDXEN = longfield<13,13>(insn_long); + layout.LDS = longfield<16,16>(insn_long); + layout.OFFEN = longfield<12,12>(insn_long); + layout.OFFSET = longfield<0,11>(insn_long); + layout.OP = longfield<18,24>(insn_long); + layout.SLC = longfield<17,17>(insn_long); + layout.SOFFSET = longfield<56,63>(insn_long); + layout.SRSRC = (longfield<48,52>(insn_long) << 2 ) | 0 ; + layout.TFE = longfield<55,55>(insn_long); + layout.VADDR = longfield<32,39>(insn_long); + layout.VDATA = longfield<40,47>(insn_long); + assert(isArrayIndexValid(ENC_MUBUF_insn_table, layout.OP) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = ENC_MUBUF_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_MUBUFOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); + this->insn_in_progress->updateMnemonic(std::string(insn_entry.mnemonic) + extension); + } + + void InstructionDecoder_amdgpu_gfx908::decodeENC_MTBUF() + { + insn_size = 8; + layout_ENC_MTBUF & layout = insn_layout.ENC_MTBUF; + layout.DFMT = longfield<19,22>(insn_long); + layout.ENCODING = longfield<26,31>(insn_long); + layout.GLC = longfield<14,14>(insn_long); + layout.IDXEN = longfield<13,13>(insn_long); + layout.NFMT = longfield<23,25>(insn_long); + layout.OFFEN = longfield<12,12>(insn_long); + layout.OFFSET = longfield<0,11>(insn_long); + layout.OP = longfield<15,18>(insn_long); + layout.SLC = longfield<54,54>(insn_long); + layout.SOFFSET = longfield<56,63>(insn_long); + layout.SRSRC = (longfield<48,52>(insn_long) << 2 ) | 0 ; + layout.TFE = longfield<55,55>(insn_long); + layout.VADDR = longfield<32,39>(insn_long); + layout.VDATA = longfield<40,47>(insn_long); + assert(isArrayIndexValid(ENC_MTBUF_insn_table, layout.OP) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = ENC_MTBUF_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_MTBUFOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); + this->insn_in_progress->updateMnemonic(std::string(insn_entry.mnemonic) + extension); + } + + void InstructionDecoder_amdgpu_gfx908::decodeENC_MIMG() + { + insn_size = 8; + layout_ENC_MIMG & layout = insn_layout.ENC_MIMG; + layout.A16 = longfield<15,15>(insn_long); + layout.D16 = longfield<63,63>(insn_long); + layout.DA = longfield<14,14>(insn_long); + layout.DMASK = longfield<8,11>(insn_long); + layout.ENCODING = longfield<26,31>(insn_long); + layout.GLC = longfield<13,13>(insn_long); + layout.LWE = longfield<17,17>(insn_long); + layout.OP = longfield<18,24>(insn_long); + layout.OPM = longfield<0,0>(insn_long); + layout.SLC = longfield<25,25>(insn_long); + layout.SRSRC = (longfield<48,52>(insn_long) << 2 ) | 0 ; + layout.SSAMP = (longfield<53,57>(insn_long) << 2 ) | 0 ; + layout.TFE = longfield<16,16>(insn_long); + layout.UNORM = longfield<12,12>(insn_long); + layout.VADDR = longfield<32,39>(insn_long); + layout.VDATA = longfield<40,47>(insn_long); + assert(isArrayIndexValid(ENC_MIMG_insn_table, layout.OP) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = ENC_MIMG_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_MIMGOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); + this->insn_in_progress->updateMnemonic(std::string(insn_entry.mnemonic) + extension); + } + + void InstructionDecoder_amdgpu_gfx908::decodeENC_EXP() + { + insn_size = 8; + } + + void InstructionDecoder_amdgpu_gfx908::decodeENC_FLAT() + { + insn_size = 8; + layout_ENC_FLAT & layout = insn_layout.ENC_FLAT; + layout.ADDR = longfield<32,39>(insn_long); + layout.DATA = longfield<40,47>(insn_long); + layout.ENCODING = longfield<26,31>(insn_long); + layout.GLC = longfield<16,16>(insn_long); + layout.LDS = longfield<13,13>(insn_long); + layout.NV = longfield<55,55>(insn_long); + layout.OFFSET = longfield<0,11>(insn_long); + layout.OP = longfield<18,24>(insn_long); + layout.SADDR = longfield<48,54>(insn_long); + layout.SEG = longfield<14,15>(insn_long); + layout.SLC = longfield<17,17>(insn_long); + layout.VDST = longfield<56,63>(insn_long); + assert(isArrayIndexValid(ENC_FLAT_insn_table, layout.OP) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = ENC_FLAT_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_FLATOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); + this->insn_in_progress->updateMnemonic(std::string(insn_entry.mnemonic) + extension); + } + + void InstructionDecoder_amdgpu_gfx908::decodeENC_FLAT_GLBL() + { + insn_size = 8; + layout_ENC_FLAT_GLBL & layout = insn_layout.ENC_FLAT_GLBL; + layout.ADDR = longfield<32,39>(insn_long); + layout.DATA = longfield<40,47>(insn_long); + layout.ENCODING = longfield<26,31>(insn_long); + layout.GLC = longfield<16,16>(insn_long); + layout.LDS = longfield<13,13>(insn_long); + layout.NV = longfield<55,55>(insn_long); + layout.OFFSET = longfield<0,12>(insn_long); + layout.OP = longfield<18,24>(insn_long); + layout.SADDR = longfield<48,54>(insn_long); + layout.SEG = longfield<14,15>(insn_long); + layout.SLC = longfield<17,17>(insn_long); + layout.VDST = longfield<56,63>(insn_long); + assert(isArrayIndexValid(ENC_FLAT_GLBL_insn_table, layout.OP) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = ENC_FLAT_GLBL_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_FLAT_GLBLOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); + this->insn_in_progress->updateMnemonic(std::string(insn_entry.mnemonic) + extension); + } + + void InstructionDecoder_amdgpu_gfx908::decodeENC_FLAT_SCRATCH() + { + insn_size = 8; + layout_ENC_FLAT_SCRATCH & layout = insn_layout.ENC_FLAT_SCRATCH; + layout.ADDR = longfield<32,39>(insn_long); + layout.DATA = longfield<40,47>(insn_long); + layout.ENCODING = longfield<26,31>(insn_long); + layout.GLC = longfield<16,16>(insn_long); + layout.LDS = longfield<13,13>(insn_long); + layout.NV = longfield<55,55>(insn_long); + layout.OFFSET = longfield<0,12>(insn_long); + layout.OP = longfield<18,24>(insn_long); + layout.SADDR = longfield<48,54>(insn_long); + layout.SEG = longfield<14,15>(insn_long); + layout.SLC = longfield<17,17>(insn_long); + layout.VDST = longfield<56,63>(insn_long); + assert(isArrayIndexValid(ENC_FLAT_SCRATCH_insn_table, layout.OP) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = ENC_FLAT_SCRATCH_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_FLAT_SCRATCHOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); + this->insn_in_progress->updateMnemonic(std::string(insn_entry.mnemonic) + extension); + } + + void InstructionDecoder_amdgpu_gfx908::decodeSOPK_INST_LITERAL_() + { + insn_size = 8; + layout_SOPK_INST_LITERAL_ & layout = insn_layout.SOPK_INST_LITERAL_; + layout.ENCODING = longfield<28,31>(insn_long); + layout.OP = longfield<23,27>(insn_long); + layout.SDST = longfield<16,22>(insn_long); + layout.SIMM16 = longfield<0,15>(insn_long); + layout.SIMM32 = longfield<32,63>(insn_long); + assert(isArrayIndexValid(SOPK_INST_LITERAL__insn_table, layout.OP) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = SOPK_INST_LITERAL__insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeSOPK_INST_LITERAL_Operands(); + this->insn_in_progress->updateSize(insn_size + immLen); + this->insn_in_progress->updateMnemonic(std::string(insn_entry.mnemonic) + extension); + } + + void InstructionDecoder_amdgpu_gfx908::decodeENC_VOP2_LITERAL() + { + insn_size = 8; + layout_ENC_VOP2_LITERAL & layout = insn_layout.ENC_VOP2_LITERAL; + layout.ENCODING = longfield<31,31>(insn_long); + layout.OP = longfield<25,30>(insn_long); + layout.SIMM32 = longfield<32,63>(insn_long); + layout.SRC0 = longfield<0,8>(insn_long); + layout.VDST = longfield<17,24>(insn_long); + layout.VSRC1 = longfield<9,16>(insn_long); + assert(isArrayIndexValid(ENC_VOP2_LITERAL_insn_table, layout.OP) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = ENC_VOP2_LITERAL_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_VOP2_LITERALOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); + this->insn_in_progress->updateMnemonic(std::string(insn_entry.mnemonic) + extension); + } + + void InstructionDecoder_amdgpu_gfx908::decodeENC_VOP3B() + { + insn_size = 8; + layout_ENC_VOP3B & layout = insn_layout.ENC_VOP3B; + layout.CLAMP = longfield<15,15>(insn_long); + layout.ENCODING = longfield<26,31>(insn_long); + layout.NEG = longfield<61,63>(insn_long); + layout.OMOD = longfield<59,60>(insn_long); + layout.OP = longfield<16,25>(insn_long); + layout.SDST = longfield<8,14>(insn_long); + layout.SRC0 = longfield<32,40>(insn_long); + layout.SRC1 = longfield<41,49>(insn_long); + layout.SRC2 = longfield<50,58>(insn_long); + layout.VDST = longfield<0,7>(insn_long); + assert(isArrayIndexValid(ENC_VOP3B_insn_table, layout.OP) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = ENC_VOP3B_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_VOP3BOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); + this->insn_in_progress->updateMnemonic(std::string(insn_entry.mnemonic) + extension); + } + + void InstructionDecoder_amdgpu_gfx908::decodeENC_VOP3P_MFMA() + { + insn_size = 8; + layout_ENC_VOP3P_MFMA & layout = insn_layout.ENC_VOP3P_MFMA; + layout.ABID = longfield<11,14>(insn_long); + layout.ACC = longfield<59,60>(insn_long); + layout.BLGP = longfield<61,63>(insn_long); + layout.CBSZ = longfield<8,10>(insn_long); + layout.ENCODING = longfield<23,31>(insn_long); + layout.OP = longfield<16,22>(insn_long); + layout.SRC0 = longfield<32,40>(insn_long); + layout.SRC1 = longfield<41,49>(insn_long); + layout.SRC2 = longfield<50,58>(insn_long); + layout.VDST = longfield<0,7>(insn_long); + assert(isArrayIndexValid(ENC_VOP3P_MFMA_insn_table, layout.OP) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = ENC_VOP3P_MFMA_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_VOP3P_MFMAOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); + this->insn_in_progress->updateMnemonic(std::string(insn_entry.mnemonic) + extension); + } + + void InstructionDecoder_amdgpu_gfx908::mainDecodeOpcode() + { + if (IS_ENC_SOP1(insn_long)) { + insn_size = 4; + uint32_t op_value = longfield<8,15>(insn_long); + assert(isArrayIndexValid(ENC_SOP1_insn_table, op_value) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = ENC_SOP1_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_SOP1; + } + else if (IS_ENC_SOPC(insn_long)) { + insn_size = 4; + uint32_t op_value = longfield<16,22>(insn_long); + assert(isArrayIndexValid(ENC_SOPC_insn_table, op_value) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = ENC_SOPC_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_SOPC; + } + else if (IS_ENC_SOPP(insn_long)) { + insn_size = 4; + uint32_t op_value = longfield<16,22>(insn_long); + assert(isArrayIndexValid(ENC_SOPP_insn_table, op_value) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = ENC_SOPP_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_SOPP; + } + else if (IS_ENC_SOPK(insn_long)) { + insn_size = 4; + uint32_t op_value = longfield<23,27>(insn_long); + assert(isArrayIndexValid(ENC_SOPK_insn_table, op_value) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = ENC_SOPK_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_SOPK; + } + else if (IS_ENC_SOP2(insn_long)) { + insn_size = 4; + uint32_t op_value = longfield<23,29>(insn_long); + assert(isArrayIndexValid(ENC_SOP2_insn_table, op_value) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = ENC_SOP2_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_SOP2; + } + else if (IS_ENC_SMEM(insn_long)) { + insn_size = 8; + uint32_t op_value = longfield<18,25>(insn_long); + assert(isArrayIndexValid(ENC_SMEM_insn_table, op_value) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = ENC_SMEM_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_SMEM; + } + else if (IS_ENC_VOP1(insn_long)) { + insn_size = 4; + uint32_t op_value = longfield<9,16>(insn_long); + assert(isArrayIndexValid(ENC_VOP1_insn_table, op_value) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = ENC_VOP1_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_VOP1; + } + else if (IS_ENC_VOPC(insn_long)) { + insn_size = 4; + uint32_t op_value = longfield<17,24>(insn_long); + assert(isArrayIndexValid(ENC_VOPC_insn_table, op_value) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = ENC_VOPC_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_VOPC; + } + else if (IS_ENC_VOP2(insn_long)) { + insn_size = 4; + uint32_t op_value = longfield<25,30>(insn_long); + assert(isArrayIndexValid(ENC_VOP2_insn_table, op_value) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = ENC_VOP2_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_VOP2; + } + else if (IS_ENC_VINTRP(insn_long)) { + insn_size = 4; + uint32_t op_value = longfield<16,17>(insn_long); + assert(isArrayIndexValid(ENC_VINTRP_insn_table, op_value) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = ENC_VINTRP_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_VINTRP; + } + else if (IS_ENC_VOP3P(insn_long)) { + insn_size = 8; + uint32_t op_value = longfield<16,22>(insn_long); + assert(isArrayIndexValid(ENC_VOP3P_insn_table, op_value) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = ENC_VOP3P_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_VOP3P; + } + else if (IS_ENC_VOP3(insn_long)) { + insn_size = 8; + uint32_t op_value = longfield<16,25>(insn_long); + assert(isArrayIndexValid(ENC_VOP3_insn_table, op_value) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = ENC_VOP3_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_VOP3; + } + else if (IS_ENC_DS(insn_long)) { + insn_size = 8; + uint32_t op_value = longfield<17,24>(insn_long); + assert(isArrayIndexValid(ENC_DS_insn_table, op_value) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = ENC_DS_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_DS; + } + else if (IS_ENC_MUBUF(insn_long)) { + insn_size = 8; + uint32_t op_value = longfield<18,24>(insn_long); + assert(isArrayIndexValid(ENC_MUBUF_insn_table, op_value) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = ENC_MUBUF_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_MUBUF; + } + else if (IS_ENC_MTBUF(insn_long)) { + insn_size = 8; + uint32_t op_value = longfield<15,18>(insn_long); + assert(isArrayIndexValid(ENC_MTBUF_insn_table, op_value) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = ENC_MTBUF_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_MTBUF; + } + else if (IS_ENC_MIMG(insn_long)) { + insn_size = 8; + uint32_t op_value = longfield<18,24>(insn_long); + assert(isArrayIndexValid(ENC_MIMG_insn_table, op_value) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = ENC_MIMG_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_MIMG; + } + else if (IS_ENC_EXP(insn_long)) { + insn_size = 8; + instr_family = ENC_EXP; + } + else if (IS_ENC_FLAT(insn_long)) { + insn_size = 8; + uint32_t op_value = longfield<18,24>(insn_long); + assert(isArrayIndexValid(ENC_FLAT_insn_table, op_value) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = ENC_FLAT_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_FLAT; + } + else if (IS_ENC_FLAT_GLBL(insn_long)) { + insn_size = 8; + uint32_t op_value = longfield<18,24>(insn_long); + assert(isArrayIndexValid(ENC_FLAT_GLBL_insn_table, op_value) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = ENC_FLAT_GLBL_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_FLAT_GLBL; + } + else if (IS_ENC_FLAT_SCRATCH(insn_long)) { + insn_size = 8; + uint32_t op_value = longfield<18,24>(insn_long); + assert(isArrayIndexValid(ENC_FLAT_SCRATCH_insn_table, op_value) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = ENC_FLAT_SCRATCH_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_FLAT_SCRATCH; + } + else if (IS_SOPK_INST_LITERAL_(insn_long)) { + insn_size = 8; + uint32_t op_value = longfield<23,27>(insn_long); + assert(isArrayIndexValid(SOPK_INST_LITERAL__insn_table, op_value) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = SOPK_INST_LITERAL__insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = SOPK_INST_LITERAL_; + } + else if (IS_ENC_VOP2_LITERAL(insn_long)) { + insn_size = 8; + uint32_t op_value = longfield<25,30>(insn_long); + assert(isArrayIndexValid(ENC_VOP2_LITERAL_insn_table, op_value) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = ENC_VOP2_LITERAL_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_VOP2_LITERAL; + } + else if (IS_ENC_VOP3B(insn_long)) { + insn_size = 8; + uint32_t op_value = longfield<16,25>(insn_long); + assert(isArrayIndexValid(ENC_VOP3B_insn_table, op_value) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = ENC_VOP3B_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_VOP3B; + } + else if (IS_ENC_VOP3P_MFMA(insn_long)) { + insn_size = 8; + uint32_t op_value = longfield<16,22>(insn_long); + assert(isArrayIndexValid(ENC_VOP3P_MFMA_insn_table, op_value) && "Opcode over or underflow"); + const amdgpu_gfx908_insn_entry &insn_entry = ENC_VOP3P_MFMA_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_VOP3P_MFMA; + } + } + + void InstructionDecoder_amdgpu_gfx908::mainDecode() + { + if (IS_ENC_SOP1(insn_long)) { + decodeENC_SOP1(); + } + else if (IS_ENC_SOPC(insn_long)) { + decodeENC_SOPC(); + } + else if (IS_ENC_SOPP(insn_long)) { + decodeENC_SOPP(); + } + else if (IS_ENC_SOPK(insn_long)) { + decodeENC_SOPK(); + } + else if (IS_ENC_SOP2(insn_long)) { + decodeENC_SOP2(); + } + else if (IS_ENC_SMEM(insn_long)) { + decodeENC_SMEM(); + } + else if (IS_ENC_VOP1(insn_long)) { + decodeENC_VOP1(); + } + else if (IS_ENC_VOPC(insn_long)) { + decodeENC_VOPC(); + } + else if (IS_ENC_VOP2(insn_long)) { + decodeENC_VOP2(); + } + else if (IS_ENC_VINTRP(insn_long)) { + decodeENC_VINTRP(); + } + else if (IS_ENC_VOP3P(insn_long)) { + decodeENC_VOP3P(); + } + else if (IS_ENC_VOP3(insn_long)) { + decodeENC_VOP3(); + } + else if (IS_ENC_DS(insn_long)) { + decodeENC_DS(); + } + else if (IS_ENC_MUBUF(insn_long)) { + decodeENC_MUBUF(); + } + else if (IS_ENC_MTBUF(insn_long)) { + decodeENC_MTBUF(); + } + else if (IS_ENC_MIMG(insn_long)) { + decodeENC_MIMG(); + } + else if (IS_ENC_EXP(insn_long)) { + decodeENC_EXP(); + } + else if (IS_ENC_FLAT(insn_long)) { + decodeENC_FLAT(); + } + else if (IS_ENC_FLAT_GLBL(insn_long)) { + decodeENC_FLAT_GLBL(); + } + else if (IS_ENC_FLAT_SCRATCH(insn_long)) { + decodeENC_FLAT_SCRATCH(); + } + else if (IS_SOPK_INST_LITERAL_(insn_long)) { + decodeSOPK_INST_LITERAL_(); + } + else if (IS_ENC_VOP2_LITERAL(insn_long)) { + decodeENC_VOP2_LITERAL(); + } + else if (IS_ENC_VOP3B(insn_long)) { + decodeENC_VOP3B(); + } + else if (IS_ENC_VOP3P_MFMA(insn_long)) { + decodeENC_VOP3P_MFMA(); + } + } + +} +} diff --git a/instructionAPI/src/AMDGPU/gfx908/amdgpu_gfx908_insn_entry.h b/instructionAPI/src/AMDGPU/gfx908/amdgpu_gfx908_insn_entry.h new file mode 100644 index 0000000000..eabf4aff66 --- /dev/null +++ b/instructionAPI/src/AMDGPU/gfx908/amdgpu_gfx908_insn_entry.h @@ -0,0 +1,34 @@ +#include + +struct amdgpu_gfx908_insn_entry { + entryID op; + const char *mnemonic; + std::size_t operandCnt; + const operandFactory *operands; + static const amdgpu_gfx908_insn_table main_insn_table ; + static const operandFactory operandTable[] ; + static const amdgpu_gfx908_insn_table ENC_DS_insn_table ; + static const amdgpu_gfx908_insn_table ENC_EXP_insn_table ; + static const amdgpu_gfx908_insn_table ENC_FLAT_insn_table ; + static const amdgpu_gfx908_insn_table ENC_FLAT_GLBL_insn_table ; + static const amdgpu_gfx908_insn_table ENC_FLAT_SCRATCH_insn_table ; + static const amdgpu_gfx908_insn_table ENC_MIMG_insn_table ; + static const amdgpu_gfx908_insn_table ENC_MTBUF_insn_table ; + static const amdgpu_gfx908_insn_table ENC_MUBUF_insn_table ; + static const amdgpu_gfx908_insn_table ENC_SMEM_insn_table ; + static const amdgpu_gfx908_insn_table ENC_SOP1_insn_table ; + static const amdgpu_gfx908_insn_table ENC_SOP2_insn_table ; + static const amdgpu_gfx908_insn_table ENC_SOPC_insn_table ; + static const amdgpu_gfx908_insn_table ENC_SOPK_insn_table ; + static const amdgpu_gfx908_insn_table SOPK_INST_LITERAL__insn_table ; + static const amdgpu_gfx908_insn_table ENC_SOPP_insn_table ; + static const amdgpu_gfx908_insn_table ENC_VINTRP_insn_table ; + static const amdgpu_gfx908_insn_table ENC_VOP3_insn_table ; + static const amdgpu_gfx908_insn_table ENC_VOP1_insn_table ; + static const amdgpu_gfx908_insn_table ENC_VOP2_insn_table ; + static const amdgpu_gfx908_insn_table ENC_VOP2_LITERAL_insn_table ; + static const amdgpu_gfx908_insn_table ENC_VOP3B_insn_table ; + static const amdgpu_gfx908_insn_table ENC_VOP3P_insn_table ; + static const amdgpu_gfx908_insn_table ENC_VOP3P_MFMA_insn_table ; + static const amdgpu_gfx908_insn_table ENC_VOPC_insn_table ; +}; diff --git a/instructionAPI/src/AMDGPU/gfx908/appendOperands.C b/instructionAPI/src/AMDGPU/gfx908/appendOperands.C new file mode 100644 index 0000000000..c3efe98039 --- /dev/null +++ b/instructionAPI/src/AMDGPU/gfx908/appendOperands.C @@ -0,0 +1,383 @@ +#include +#include "InstructionDecoder-amdgpu-gfx908.h" + +namespace Dyninst { +namespace InstructionAPI { + void InstructionDecoder_amdgpu_gfx908::appendOPR_SIMM4(uint64_t input, bool isRead, bool isWritten, uint32_t /*_num_elements = 1*/ , bool isImplicit /*= false*/) + { + insn_in_progress->appendOperand(Immediate::makeImmediate(Result(s8, input)),isRead,isWritten,isImplicit); + } + + void InstructionDecoder_amdgpu_gfx908::appendOPR_SIMM8(uint64_t input, bool isRead, bool isWritten, uint32_t /*_num_elements = 1*/ , bool isImplicit /*= false*/) + { + insn_in_progress->appendOperand(Immediate::makeImmediate(Result(s8, input)),isRead,isWritten,isImplicit); + } + + void InstructionDecoder_amdgpu_gfx908::appendOPR_SIMM16(uint64_t input, bool isRead, bool isWritten, uint32_t /*_num_elements = 1*/ , bool isImplicit /*= false*/) + { + insn_in_progress->appendOperand(Immediate::makeImmediate(Result(s16, input)),isRead,isWritten,isImplicit); + } + + void InstructionDecoder_amdgpu_gfx908::appendOPR_SIMM32(uint64_t input, bool isRead, bool isWritten, uint32_t /*_num_elements = 1*/ , bool isImplicit /*= false*/) + { + insn_in_progress->appendOperand(Immediate::makeImmediate(Result(s32, input)),isRead,isWritten,isImplicit); + } + + void InstructionDecoder_amdgpu_gfx908::appendOPR_WAITCNT(uint64_t input, bool isRead, bool isWritten, uint32_t /*_num_elements = 1*/ , bool isImplicit /*= false*/) + { + insn_in_progress->appendOperand(Immediate::makeImmediate(Result(s16, input)),isRead,isWritten,isImplicit); + } + + void InstructionDecoder_amdgpu_gfx908::appendOPR_ACCVGPR(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_ACCVGPR(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_ACCVGPR(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + + void InstructionDecoder_amdgpu_gfx908::appendOPR_ATTR(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_ATTR(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_ATTR(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + + void InstructionDecoder_amdgpu_gfx908::appendOPR_DSMEM(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_DSMEM(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_DSMEM(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + + void InstructionDecoder_amdgpu_gfx908::appendOPR_FLAT_SCRATCH(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_FLAT_SCRATCH(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + + void InstructionDecoder_amdgpu_gfx908::appendOPR_PARAM(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_PARAM(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_PARAM(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + + void InstructionDecoder_amdgpu_gfx908::appendOPR_PC(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_PC(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_PC(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + + void InstructionDecoder_amdgpu_gfx908::appendOPR_SDST(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_SDST(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_SDST(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + + void InstructionDecoder_amdgpu_gfx908::appendOPR_SDST_EXEC(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_SDST_EXEC(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + + void InstructionDecoder_amdgpu_gfx908::appendOPR_SDST_M0(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_SDST_M0(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_SDST_M0(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + + void InstructionDecoder_amdgpu_gfx908::appendOPR_SRC(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_SRC(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_SRC(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + + void InstructionDecoder_amdgpu_gfx908::appendOPR_SRC_ACCVGPR(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_SRC_ACCVGPR(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_SRC_ACCVGPR(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + + void InstructionDecoder_amdgpu_gfx908::appendOPR_SRC_ACCVGPR_OR_CONST(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_SRC_ACCVGPR_OR_CONST(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_SRC_ACCVGPR_OR_CONST(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + + void InstructionDecoder_amdgpu_gfx908::appendOPR_SRC_NOLDS(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_SRC_NOLDS(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_SRC_NOLDS(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + + void InstructionDecoder_amdgpu_gfx908::appendOPR_SRC_NOLIT(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_SRC_NOLIT(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + + void InstructionDecoder_amdgpu_gfx908::appendOPR_SRC_SIMPLE(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_SRC_SIMPLE(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + + void InstructionDecoder_amdgpu_gfx908::appendOPR_SRC_VGPR(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_SRC_VGPR(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_SRC_VGPR(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + + void InstructionDecoder_amdgpu_gfx908::appendOPR_SRC_VGPR_OR_ACCVGPR(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_SRC_VGPR_OR_ACCVGPR(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + + void InstructionDecoder_amdgpu_gfx908::appendOPR_SREG(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_SREG(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_SREG(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + + void InstructionDecoder_amdgpu_gfx908::appendOPR_SREG_NOVCC(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_SREG_NOVCC(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_SREG_NOVCC(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + + void InstructionDecoder_amdgpu_gfx908::appendOPR_SSRC(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_SSRC(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_SSRC(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + + void InstructionDecoder_amdgpu_gfx908::appendOPR_SSRC_LANESEL(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_SSRC_LANESEL(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_SSRC_LANESEL(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + + void InstructionDecoder_amdgpu_gfx908::appendOPR_SSRC_NOLIT(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_SSRC_NOLIT(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + + void InstructionDecoder_amdgpu_gfx908::appendOPR_SSRC_SPECIAL_SCC(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_SSRC_SPECIAL_SCC(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + + void InstructionDecoder_amdgpu_gfx908::appendOPR_TGT(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_TGT(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_TGT(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + + void InstructionDecoder_amdgpu_gfx908::appendOPR_VCC(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_VCC(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_VCC(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + + void InstructionDecoder_amdgpu_gfx908::appendOPR_VGPR(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_VGPR(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_VGPR(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + + void InstructionDecoder_amdgpu_gfx908::appendOPR_VGPR_OR_LDS(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_VGPR_OR_LDS(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_VGPR_OR_LDS(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + +} +} diff --git a/instructionAPI/src/AMDGPU/gfx908/decodeOperands.C b/instructionAPI/src/AMDGPU/gfx908/decodeOperands.C new file mode 100644 index 0000000000..ed00727810 --- /dev/null +++ b/instructionAPI/src/AMDGPU/gfx908/decodeOperands.C @@ -0,0 +1,6137 @@ +#include "registers/AMDGPU/amdgpu_gfx908_regs.h" +#include "InstructionDecoder-amdgpu-gfx908.h" + +namespace Dyninst { +namespace InstructionAPI { + Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_ACCVGPR(uint64_t input, uint32_t output_vec_len) + { + switch (input) { + case 0: return makeRegisterExpression(amdgpu_gfx908::acc0, output_vec_len ); + case 1: return makeRegisterExpression(amdgpu_gfx908::acc1, output_vec_len ); + case 2: return makeRegisterExpression(amdgpu_gfx908::acc2, output_vec_len ); + case 3: return makeRegisterExpression(amdgpu_gfx908::acc3, output_vec_len ); + case 4: return makeRegisterExpression(amdgpu_gfx908::acc4, output_vec_len ); + case 5: return makeRegisterExpression(amdgpu_gfx908::acc5, output_vec_len ); + case 6: return makeRegisterExpression(amdgpu_gfx908::acc6, output_vec_len ); + case 7: return makeRegisterExpression(amdgpu_gfx908::acc7, output_vec_len ); + case 8: return makeRegisterExpression(amdgpu_gfx908::acc8, output_vec_len ); + case 9: return makeRegisterExpression(amdgpu_gfx908::acc9, output_vec_len ); + case 10: return makeRegisterExpression(amdgpu_gfx908::acc10, output_vec_len ); + case 11: return makeRegisterExpression(amdgpu_gfx908::acc11, output_vec_len ); + case 12: return makeRegisterExpression(amdgpu_gfx908::acc12, output_vec_len ); + case 13: return makeRegisterExpression(amdgpu_gfx908::acc13, output_vec_len ); + case 14: return makeRegisterExpression(amdgpu_gfx908::acc14, output_vec_len ); + case 15: return makeRegisterExpression(amdgpu_gfx908::acc15, output_vec_len ); + case 16: return makeRegisterExpression(amdgpu_gfx908::acc16, output_vec_len ); + case 17: return makeRegisterExpression(amdgpu_gfx908::acc17, output_vec_len ); + case 18: return makeRegisterExpression(amdgpu_gfx908::acc18, output_vec_len ); + case 19: return makeRegisterExpression(amdgpu_gfx908::acc19, output_vec_len ); + case 20: return makeRegisterExpression(amdgpu_gfx908::acc20, output_vec_len ); + case 21: return makeRegisterExpression(amdgpu_gfx908::acc21, output_vec_len ); + case 22: return makeRegisterExpression(amdgpu_gfx908::acc22, output_vec_len ); + case 23: return makeRegisterExpression(amdgpu_gfx908::acc23, output_vec_len ); + case 24: return makeRegisterExpression(amdgpu_gfx908::acc24, output_vec_len ); + case 25: return makeRegisterExpression(amdgpu_gfx908::acc25, output_vec_len ); + case 26: return makeRegisterExpression(amdgpu_gfx908::acc26, output_vec_len ); + case 27: return makeRegisterExpression(amdgpu_gfx908::acc27, output_vec_len ); + case 28: return makeRegisterExpression(amdgpu_gfx908::acc28, output_vec_len ); + case 29: return makeRegisterExpression(amdgpu_gfx908::acc29, output_vec_len ); + case 30: return makeRegisterExpression(amdgpu_gfx908::acc30, output_vec_len ); + case 31: return makeRegisterExpression(amdgpu_gfx908::acc31, output_vec_len ); + case 32: return makeRegisterExpression(amdgpu_gfx908::acc32, output_vec_len ); + case 33: return makeRegisterExpression(amdgpu_gfx908::acc33, output_vec_len ); + case 34: return makeRegisterExpression(amdgpu_gfx908::acc34, output_vec_len ); + case 35: return makeRegisterExpression(amdgpu_gfx908::acc35, output_vec_len ); + case 36: return makeRegisterExpression(amdgpu_gfx908::acc36, output_vec_len ); + case 37: return makeRegisterExpression(amdgpu_gfx908::acc37, output_vec_len ); + case 38: return makeRegisterExpression(amdgpu_gfx908::acc38, output_vec_len ); + case 39: return makeRegisterExpression(amdgpu_gfx908::acc39, output_vec_len ); + case 40: return makeRegisterExpression(amdgpu_gfx908::acc40, output_vec_len ); + case 41: return makeRegisterExpression(amdgpu_gfx908::acc41, output_vec_len ); + case 42: return makeRegisterExpression(amdgpu_gfx908::acc42, output_vec_len ); + case 43: return makeRegisterExpression(amdgpu_gfx908::acc43, output_vec_len ); + case 44: return makeRegisterExpression(amdgpu_gfx908::acc44, output_vec_len ); + case 45: return makeRegisterExpression(amdgpu_gfx908::acc45, output_vec_len ); + case 46: return makeRegisterExpression(amdgpu_gfx908::acc46, output_vec_len ); + case 47: return makeRegisterExpression(amdgpu_gfx908::acc47, output_vec_len ); + case 48: return makeRegisterExpression(amdgpu_gfx908::acc48, output_vec_len ); + case 49: return makeRegisterExpression(amdgpu_gfx908::acc49, output_vec_len ); + case 50: return makeRegisterExpression(amdgpu_gfx908::acc50, output_vec_len ); + case 51: return makeRegisterExpression(amdgpu_gfx908::acc51, output_vec_len ); + case 52: return makeRegisterExpression(amdgpu_gfx908::acc52, output_vec_len ); + case 53: return makeRegisterExpression(amdgpu_gfx908::acc53, output_vec_len ); + case 54: return makeRegisterExpression(amdgpu_gfx908::acc54, output_vec_len ); + case 55: return makeRegisterExpression(amdgpu_gfx908::acc55, output_vec_len ); + case 56: return makeRegisterExpression(amdgpu_gfx908::acc56, output_vec_len ); + case 57: return makeRegisterExpression(amdgpu_gfx908::acc57, output_vec_len ); + case 58: return makeRegisterExpression(amdgpu_gfx908::acc58, output_vec_len ); + case 59: return makeRegisterExpression(amdgpu_gfx908::acc59, output_vec_len ); + case 60: return makeRegisterExpression(amdgpu_gfx908::acc60, output_vec_len ); + case 61: return makeRegisterExpression(amdgpu_gfx908::acc61, output_vec_len ); + case 62: return makeRegisterExpression(amdgpu_gfx908::acc62, output_vec_len ); + case 63: return makeRegisterExpression(amdgpu_gfx908::acc63, output_vec_len ); + case 64: return makeRegisterExpression(amdgpu_gfx908::acc64, output_vec_len ); + case 65: return makeRegisterExpression(amdgpu_gfx908::acc65, output_vec_len ); + case 66: return makeRegisterExpression(amdgpu_gfx908::acc66, output_vec_len ); + case 67: return makeRegisterExpression(amdgpu_gfx908::acc67, output_vec_len ); + case 68: return makeRegisterExpression(amdgpu_gfx908::acc68, output_vec_len ); + case 69: return makeRegisterExpression(amdgpu_gfx908::acc69, output_vec_len ); + case 70: return makeRegisterExpression(amdgpu_gfx908::acc70, output_vec_len ); + case 71: return makeRegisterExpression(amdgpu_gfx908::acc71, output_vec_len ); + case 72: return makeRegisterExpression(amdgpu_gfx908::acc72, output_vec_len ); + case 73: return makeRegisterExpression(amdgpu_gfx908::acc73, output_vec_len ); + case 74: return makeRegisterExpression(amdgpu_gfx908::acc74, output_vec_len ); + case 75: return makeRegisterExpression(amdgpu_gfx908::acc75, output_vec_len ); + case 76: return makeRegisterExpression(amdgpu_gfx908::acc76, output_vec_len ); + case 77: return makeRegisterExpression(amdgpu_gfx908::acc77, output_vec_len ); + case 78: return makeRegisterExpression(amdgpu_gfx908::acc78, output_vec_len ); + case 79: return makeRegisterExpression(amdgpu_gfx908::acc79, output_vec_len ); + case 80: return makeRegisterExpression(amdgpu_gfx908::acc80, output_vec_len ); + case 81: return makeRegisterExpression(amdgpu_gfx908::acc81, output_vec_len ); + case 82: return makeRegisterExpression(amdgpu_gfx908::acc82, output_vec_len ); + case 83: return makeRegisterExpression(amdgpu_gfx908::acc83, output_vec_len ); + case 84: return makeRegisterExpression(amdgpu_gfx908::acc84, output_vec_len ); + case 85: return makeRegisterExpression(amdgpu_gfx908::acc85, output_vec_len ); + case 86: return makeRegisterExpression(amdgpu_gfx908::acc86, output_vec_len ); + case 87: return makeRegisterExpression(amdgpu_gfx908::acc87, output_vec_len ); + case 88: return makeRegisterExpression(amdgpu_gfx908::acc88, output_vec_len ); + case 89: return makeRegisterExpression(amdgpu_gfx908::acc89, output_vec_len ); + case 90: return makeRegisterExpression(amdgpu_gfx908::acc90, output_vec_len ); + case 91: return makeRegisterExpression(amdgpu_gfx908::acc91, output_vec_len ); + case 92: return makeRegisterExpression(amdgpu_gfx908::acc92, output_vec_len ); + case 93: return makeRegisterExpression(amdgpu_gfx908::acc93, output_vec_len ); + case 94: return makeRegisterExpression(amdgpu_gfx908::acc94, output_vec_len ); + case 95: return makeRegisterExpression(amdgpu_gfx908::acc95, output_vec_len ); + case 96: return makeRegisterExpression(amdgpu_gfx908::acc96, output_vec_len ); + case 97: return makeRegisterExpression(amdgpu_gfx908::acc97, output_vec_len ); + case 98: return makeRegisterExpression(amdgpu_gfx908::acc98, output_vec_len ); + case 99: return makeRegisterExpression(amdgpu_gfx908::acc99, output_vec_len ); + case 100: return makeRegisterExpression(amdgpu_gfx908::acc100, output_vec_len ); + case 101: return makeRegisterExpression(amdgpu_gfx908::acc101, output_vec_len ); + case 102: return makeRegisterExpression(amdgpu_gfx908::acc102, output_vec_len ); + case 103: return makeRegisterExpression(amdgpu_gfx908::acc103, output_vec_len ); + case 104: return makeRegisterExpression(amdgpu_gfx908::acc104, output_vec_len ); + case 105: return makeRegisterExpression(amdgpu_gfx908::acc105, output_vec_len ); + case 106: return makeRegisterExpression(amdgpu_gfx908::acc106, output_vec_len ); + case 107: return makeRegisterExpression(amdgpu_gfx908::acc107, output_vec_len ); + case 108: return makeRegisterExpression(amdgpu_gfx908::acc108, output_vec_len ); + case 109: return makeRegisterExpression(amdgpu_gfx908::acc109, output_vec_len ); + case 110: return makeRegisterExpression(amdgpu_gfx908::acc110, output_vec_len ); + case 111: return makeRegisterExpression(amdgpu_gfx908::acc111, output_vec_len ); + case 112: return makeRegisterExpression(amdgpu_gfx908::acc112, output_vec_len ); + case 113: return makeRegisterExpression(amdgpu_gfx908::acc113, output_vec_len ); + case 114: return makeRegisterExpression(amdgpu_gfx908::acc114, output_vec_len ); + case 115: return makeRegisterExpression(amdgpu_gfx908::acc115, output_vec_len ); + case 116: return makeRegisterExpression(amdgpu_gfx908::acc116, output_vec_len ); + case 117: return makeRegisterExpression(amdgpu_gfx908::acc117, output_vec_len ); + case 118: return makeRegisterExpression(amdgpu_gfx908::acc118, output_vec_len ); + case 119: return makeRegisterExpression(amdgpu_gfx908::acc119, output_vec_len ); + case 120: return makeRegisterExpression(amdgpu_gfx908::acc120, output_vec_len ); + case 121: return makeRegisterExpression(amdgpu_gfx908::acc121, output_vec_len ); + case 122: return makeRegisterExpression(amdgpu_gfx908::acc122, output_vec_len ); + case 123: return makeRegisterExpression(amdgpu_gfx908::acc123, output_vec_len ); + case 124: return makeRegisterExpression(amdgpu_gfx908::acc124, output_vec_len ); + case 125: return makeRegisterExpression(amdgpu_gfx908::acc125, output_vec_len ); + case 126: return makeRegisterExpression(amdgpu_gfx908::acc126, output_vec_len ); + case 127: return makeRegisterExpression(amdgpu_gfx908::acc127, output_vec_len ); + case 128: return makeRegisterExpression(amdgpu_gfx908::acc128, output_vec_len ); + case 129: return makeRegisterExpression(amdgpu_gfx908::acc129, output_vec_len ); + case 130: return makeRegisterExpression(amdgpu_gfx908::acc130, output_vec_len ); + case 131: return makeRegisterExpression(amdgpu_gfx908::acc131, output_vec_len ); + case 132: return makeRegisterExpression(amdgpu_gfx908::acc132, output_vec_len ); + case 133: return makeRegisterExpression(amdgpu_gfx908::acc133, output_vec_len ); + case 134: return makeRegisterExpression(amdgpu_gfx908::acc134, output_vec_len ); + case 135: return makeRegisterExpression(amdgpu_gfx908::acc135, output_vec_len ); + case 136: return makeRegisterExpression(amdgpu_gfx908::acc136, output_vec_len ); + case 137: return makeRegisterExpression(amdgpu_gfx908::acc137, output_vec_len ); + case 138: return makeRegisterExpression(amdgpu_gfx908::acc138, output_vec_len ); + case 139: return makeRegisterExpression(amdgpu_gfx908::acc139, output_vec_len ); + case 140: return makeRegisterExpression(amdgpu_gfx908::acc140, output_vec_len ); + case 141: return makeRegisterExpression(amdgpu_gfx908::acc141, output_vec_len ); + case 142: return makeRegisterExpression(amdgpu_gfx908::acc142, output_vec_len ); + case 143: return makeRegisterExpression(amdgpu_gfx908::acc143, output_vec_len ); + case 144: return makeRegisterExpression(amdgpu_gfx908::acc144, output_vec_len ); + case 145: return makeRegisterExpression(amdgpu_gfx908::acc145, output_vec_len ); + case 146: return makeRegisterExpression(amdgpu_gfx908::acc146, output_vec_len ); + case 147: return makeRegisterExpression(amdgpu_gfx908::acc147, output_vec_len ); + case 148: return makeRegisterExpression(amdgpu_gfx908::acc148, output_vec_len ); + case 149: return makeRegisterExpression(amdgpu_gfx908::acc149, output_vec_len ); + case 150: return makeRegisterExpression(amdgpu_gfx908::acc150, output_vec_len ); + case 151: return makeRegisterExpression(amdgpu_gfx908::acc151, output_vec_len ); + case 152: return makeRegisterExpression(amdgpu_gfx908::acc152, output_vec_len ); + case 153: return makeRegisterExpression(amdgpu_gfx908::acc153, output_vec_len ); + case 154: return makeRegisterExpression(amdgpu_gfx908::acc154, output_vec_len ); + case 155: return makeRegisterExpression(amdgpu_gfx908::acc155, output_vec_len ); + case 156: return makeRegisterExpression(amdgpu_gfx908::acc156, output_vec_len ); + case 157: return makeRegisterExpression(amdgpu_gfx908::acc157, output_vec_len ); + case 158: return makeRegisterExpression(amdgpu_gfx908::acc158, output_vec_len ); + case 159: return makeRegisterExpression(amdgpu_gfx908::acc159, output_vec_len ); + case 160: return makeRegisterExpression(amdgpu_gfx908::acc160, output_vec_len ); + case 161: return makeRegisterExpression(amdgpu_gfx908::acc161, output_vec_len ); + case 162: return makeRegisterExpression(amdgpu_gfx908::acc162, output_vec_len ); + case 163: return makeRegisterExpression(amdgpu_gfx908::acc163, output_vec_len ); + case 164: return makeRegisterExpression(amdgpu_gfx908::acc164, output_vec_len ); + case 165: return makeRegisterExpression(amdgpu_gfx908::acc165, output_vec_len ); + case 166: return makeRegisterExpression(amdgpu_gfx908::acc166, output_vec_len ); + case 167: return makeRegisterExpression(amdgpu_gfx908::acc167, output_vec_len ); + case 168: return makeRegisterExpression(amdgpu_gfx908::acc168, output_vec_len ); + case 169: return makeRegisterExpression(amdgpu_gfx908::acc169, output_vec_len ); + case 170: return makeRegisterExpression(amdgpu_gfx908::acc170, output_vec_len ); + case 171: return makeRegisterExpression(amdgpu_gfx908::acc171, output_vec_len ); + case 172: return makeRegisterExpression(amdgpu_gfx908::acc172, output_vec_len ); + case 173: return makeRegisterExpression(amdgpu_gfx908::acc173, output_vec_len ); + case 174: return makeRegisterExpression(amdgpu_gfx908::acc174, output_vec_len ); + case 175: return makeRegisterExpression(amdgpu_gfx908::acc175, output_vec_len ); + case 176: return makeRegisterExpression(amdgpu_gfx908::acc176, output_vec_len ); + case 177: return makeRegisterExpression(amdgpu_gfx908::acc177, output_vec_len ); + case 178: return makeRegisterExpression(amdgpu_gfx908::acc178, output_vec_len ); + case 179: return makeRegisterExpression(amdgpu_gfx908::acc179, output_vec_len ); + case 180: return makeRegisterExpression(amdgpu_gfx908::acc180, output_vec_len ); + case 181: return makeRegisterExpression(amdgpu_gfx908::acc181, output_vec_len ); + case 182: return makeRegisterExpression(amdgpu_gfx908::acc182, output_vec_len ); + case 183: return makeRegisterExpression(amdgpu_gfx908::acc183, output_vec_len ); + case 184: return makeRegisterExpression(amdgpu_gfx908::acc184, output_vec_len ); + case 185: return makeRegisterExpression(amdgpu_gfx908::acc185, output_vec_len ); + case 186: return makeRegisterExpression(amdgpu_gfx908::acc186, output_vec_len ); + case 187: return makeRegisterExpression(amdgpu_gfx908::acc187, output_vec_len ); + case 188: return makeRegisterExpression(amdgpu_gfx908::acc188, output_vec_len ); + case 189: return makeRegisterExpression(amdgpu_gfx908::acc189, output_vec_len ); + case 190: return makeRegisterExpression(amdgpu_gfx908::acc190, output_vec_len ); + case 191: return makeRegisterExpression(amdgpu_gfx908::acc191, output_vec_len ); + case 192: return makeRegisterExpression(amdgpu_gfx908::acc192, output_vec_len ); + case 193: return makeRegisterExpression(amdgpu_gfx908::acc193, output_vec_len ); + case 194: return makeRegisterExpression(amdgpu_gfx908::acc194, output_vec_len ); + case 195: return makeRegisterExpression(amdgpu_gfx908::acc195, output_vec_len ); + case 196: return makeRegisterExpression(amdgpu_gfx908::acc196, output_vec_len ); + case 197: return makeRegisterExpression(amdgpu_gfx908::acc197, output_vec_len ); + case 198: return makeRegisterExpression(amdgpu_gfx908::acc198, output_vec_len ); + case 199: return makeRegisterExpression(amdgpu_gfx908::acc199, output_vec_len ); + case 200: return makeRegisterExpression(amdgpu_gfx908::acc200, output_vec_len ); + case 201: return makeRegisterExpression(amdgpu_gfx908::acc201, output_vec_len ); + case 202: return makeRegisterExpression(amdgpu_gfx908::acc202, output_vec_len ); + case 203: return makeRegisterExpression(amdgpu_gfx908::acc203, output_vec_len ); + case 204: return makeRegisterExpression(amdgpu_gfx908::acc204, output_vec_len ); + case 205: return makeRegisterExpression(amdgpu_gfx908::acc205, output_vec_len ); + case 206: return makeRegisterExpression(amdgpu_gfx908::acc206, output_vec_len ); + case 207: return makeRegisterExpression(amdgpu_gfx908::acc207, output_vec_len ); + case 208: return makeRegisterExpression(amdgpu_gfx908::acc208, output_vec_len ); + case 209: return makeRegisterExpression(amdgpu_gfx908::acc209, output_vec_len ); + case 210: return makeRegisterExpression(amdgpu_gfx908::acc210, output_vec_len ); + case 211: return makeRegisterExpression(amdgpu_gfx908::acc211, output_vec_len ); + case 212: return makeRegisterExpression(amdgpu_gfx908::acc212, output_vec_len ); + case 213: return makeRegisterExpression(amdgpu_gfx908::acc213, output_vec_len ); + case 214: return makeRegisterExpression(amdgpu_gfx908::acc214, output_vec_len ); + case 215: return makeRegisterExpression(amdgpu_gfx908::acc215, output_vec_len ); + case 216: return makeRegisterExpression(amdgpu_gfx908::acc216, output_vec_len ); + case 217: return makeRegisterExpression(amdgpu_gfx908::acc217, output_vec_len ); + case 218: return makeRegisterExpression(amdgpu_gfx908::acc218, output_vec_len ); + case 219: return makeRegisterExpression(amdgpu_gfx908::acc219, output_vec_len ); + case 220: return makeRegisterExpression(amdgpu_gfx908::acc220, output_vec_len ); + case 221: return makeRegisterExpression(amdgpu_gfx908::acc221, output_vec_len ); + case 222: return makeRegisterExpression(amdgpu_gfx908::acc222, output_vec_len ); + case 223: return makeRegisterExpression(amdgpu_gfx908::acc223, output_vec_len ); + case 224: return makeRegisterExpression(amdgpu_gfx908::acc224, output_vec_len ); + case 225: return makeRegisterExpression(amdgpu_gfx908::acc225, output_vec_len ); + case 226: return makeRegisterExpression(amdgpu_gfx908::acc226, output_vec_len ); + case 227: return makeRegisterExpression(amdgpu_gfx908::acc227, output_vec_len ); + case 228: return makeRegisterExpression(amdgpu_gfx908::acc228, output_vec_len ); + case 229: return makeRegisterExpression(amdgpu_gfx908::acc229, output_vec_len ); + case 230: return makeRegisterExpression(amdgpu_gfx908::acc230, output_vec_len ); + case 231: return makeRegisterExpression(amdgpu_gfx908::acc231, output_vec_len ); + case 232: return makeRegisterExpression(amdgpu_gfx908::acc232, output_vec_len ); + case 233: return makeRegisterExpression(amdgpu_gfx908::acc233, output_vec_len ); + case 234: return makeRegisterExpression(amdgpu_gfx908::acc234, output_vec_len ); + case 235: return makeRegisterExpression(amdgpu_gfx908::acc235, output_vec_len ); + case 236: return makeRegisterExpression(amdgpu_gfx908::acc236, output_vec_len ); + case 237: return makeRegisterExpression(amdgpu_gfx908::acc237, output_vec_len ); + case 238: return makeRegisterExpression(amdgpu_gfx908::acc238, output_vec_len ); + case 239: return makeRegisterExpression(amdgpu_gfx908::acc239, output_vec_len ); + case 240: return makeRegisterExpression(amdgpu_gfx908::acc240, output_vec_len ); + case 241: return makeRegisterExpression(amdgpu_gfx908::acc241, output_vec_len ); + case 242: return makeRegisterExpression(amdgpu_gfx908::acc242, output_vec_len ); + case 243: return makeRegisterExpression(amdgpu_gfx908::acc243, output_vec_len ); + case 244: return makeRegisterExpression(amdgpu_gfx908::acc244, output_vec_len ); + case 245: return makeRegisterExpression(amdgpu_gfx908::acc245, output_vec_len ); + case 246: return makeRegisterExpression(amdgpu_gfx908::acc246, output_vec_len ); + case 247: return makeRegisterExpression(amdgpu_gfx908::acc247, output_vec_len ); + case 248: return makeRegisterExpression(amdgpu_gfx908::acc248, output_vec_len ); + case 249: return makeRegisterExpression(amdgpu_gfx908::acc249, output_vec_len ); + case 250: return makeRegisterExpression(amdgpu_gfx908::acc250, output_vec_len ); + case 251: return makeRegisterExpression(amdgpu_gfx908::acc251, output_vec_len ); + case 252: return makeRegisterExpression(amdgpu_gfx908::acc252, output_vec_len ); + case 253: return makeRegisterExpression(amdgpu_gfx908::acc253, output_vec_len ); + case 254: return makeRegisterExpression(amdgpu_gfx908::acc254, output_vec_len ); + case 255: return makeRegisterExpression(amdgpu_gfx908::acc255, output_vec_len ); + case 768: return makeRegisterExpression(amdgpu_gfx908::acc0, output_vec_len ); + case 769: return makeRegisterExpression(amdgpu_gfx908::acc1, output_vec_len ); + case 770: return makeRegisterExpression(amdgpu_gfx908::acc2, output_vec_len ); + case 771: return makeRegisterExpression(amdgpu_gfx908::acc3, output_vec_len ); + case 772: return makeRegisterExpression(amdgpu_gfx908::acc4, output_vec_len ); + case 773: return makeRegisterExpression(amdgpu_gfx908::acc5, output_vec_len ); + case 774: return makeRegisterExpression(amdgpu_gfx908::acc6, output_vec_len ); + case 775: return makeRegisterExpression(amdgpu_gfx908::acc7, output_vec_len ); + case 776: return makeRegisterExpression(amdgpu_gfx908::acc8, output_vec_len ); + case 777: return makeRegisterExpression(amdgpu_gfx908::acc9, output_vec_len ); + case 778: return makeRegisterExpression(amdgpu_gfx908::acc10, output_vec_len ); + case 779: return makeRegisterExpression(amdgpu_gfx908::acc11, output_vec_len ); + case 780: return makeRegisterExpression(amdgpu_gfx908::acc12, output_vec_len ); + case 781: return makeRegisterExpression(amdgpu_gfx908::acc13, output_vec_len ); + case 782: return makeRegisterExpression(amdgpu_gfx908::acc14, output_vec_len ); + case 783: return makeRegisterExpression(amdgpu_gfx908::acc15, output_vec_len ); + case 784: return makeRegisterExpression(amdgpu_gfx908::acc16, output_vec_len ); + case 785: return makeRegisterExpression(amdgpu_gfx908::acc17, output_vec_len ); + case 786: return makeRegisterExpression(amdgpu_gfx908::acc18, output_vec_len ); + case 787: return makeRegisterExpression(amdgpu_gfx908::acc19, output_vec_len ); + case 788: return makeRegisterExpression(amdgpu_gfx908::acc20, output_vec_len ); + case 789: return makeRegisterExpression(amdgpu_gfx908::acc21, output_vec_len ); + case 790: return makeRegisterExpression(amdgpu_gfx908::acc22, output_vec_len ); + case 791: return makeRegisterExpression(amdgpu_gfx908::acc23, output_vec_len ); + case 792: return makeRegisterExpression(amdgpu_gfx908::acc24, output_vec_len ); + case 793: return makeRegisterExpression(amdgpu_gfx908::acc25, output_vec_len ); + case 794: return makeRegisterExpression(amdgpu_gfx908::acc26, output_vec_len ); + case 795: return makeRegisterExpression(amdgpu_gfx908::acc27, output_vec_len ); + case 796: return makeRegisterExpression(amdgpu_gfx908::acc28, output_vec_len ); + case 797: return makeRegisterExpression(amdgpu_gfx908::acc29, output_vec_len ); + case 798: return makeRegisterExpression(amdgpu_gfx908::acc30, output_vec_len ); + case 799: return makeRegisterExpression(amdgpu_gfx908::acc31, output_vec_len ); + case 800: return makeRegisterExpression(amdgpu_gfx908::acc32, output_vec_len ); + case 801: return makeRegisterExpression(amdgpu_gfx908::acc33, output_vec_len ); + case 802: return makeRegisterExpression(amdgpu_gfx908::acc34, output_vec_len ); + case 803: return makeRegisterExpression(amdgpu_gfx908::acc35, output_vec_len ); + case 804: return makeRegisterExpression(amdgpu_gfx908::acc36, output_vec_len ); + case 805: return makeRegisterExpression(amdgpu_gfx908::acc37, output_vec_len ); + case 806: return makeRegisterExpression(amdgpu_gfx908::acc38, output_vec_len ); + case 807: return makeRegisterExpression(amdgpu_gfx908::acc39, output_vec_len ); + case 808: return makeRegisterExpression(amdgpu_gfx908::acc40, output_vec_len ); + case 809: return makeRegisterExpression(amdgpu_gfx908::acc41, output_vec_len ); + case 810: return makeRegisterExpression(amdgpu_gfx908::acc42, output_vec_len ); + case 811: return makeRegisterExpression(amdgpu_gfx908::acc43, output_vec_len ); + case 812: return makeRegisterExpression(amdgpu_gfx908::acc44, output_vec_len ); + case 813: return makeRegisterExpression(amdgpu_gfx908::acc45, output_vec_len ); + case 814: return makeRegisterExpression(amdgpu_gfx908::acc46, output_vec_len ); + case 815: return makeRegisterExpression(amdgpu_gfx908::acc47, output_vec_len ); + case 816: return makeRegisterExpression(amdgpu_gfx908::acc48, output_vec_len ); + case 817: return makeRegisterExpression(amdgpu_gfx908::acc49, output_vec_len ); + case 818: return makeRegisterExpression(amdgpu_gfx908::acc50, output_vec_len ); + case 819: return makeRegisterExpression(amdgpu_gfx908::acc51, output_vec_len ); + case 820: return makeRegisterExpression(amdgpu_gfx908::acc52, output_vec_len ); + case 821: return makeRegisterExpression(amdgpu_gfx908::acc53, output_vec_len ); + case 822: return makeRegisterExpression(amdgpu_gfx908::acc54, output_vec_len ); + case 823: return makeRegisterExpression(amdgpu_gfx908::acc55, output_vec_len ); + case 824: return makeRegisterExpression(amdgpu_gfx908::acc56, output_vec_len ); + case 825: return makeRegisterExpression(amdgpu_gfx908::acc57, output_vec_len ); + case 826: return makeRegisterExpression(amdgpu_gfx908::acc58, output_vec_len ); + case 827: return makeRegisterExpression(amdgpu_gfx908::acc59, output_vec_len ); + case 828: return makeRegisterExpression(amdgpu_gfx908::acc60, output_vec_len ); + case 829: return makeRegisterExpression(amdgpu_gfx908::acc61, output_vec_len ); + case 830: return makeRegisterExpression(amdgpu_gfx908::acc62, output_vec_len ); + case 831: return makeRegisterExpression(amdgpu_gfx908::acc63, output_vec_len ); + case 832: return makeRegisterExpression(amdgpu_gfx908::acc64, output_vec_len ); + case 833: return makeRegisterExpression(amdgpu_gfx908::acc65, output_vec_len ); + case 834: return makeRegisterExpression(amdgpu_gfx908::acc66, output_vec_len ); + case 835: return makeRegisterExpression(amdgpu_gfx908::acc67, output_vec_len ); + case 836: return makeRegisterExpression(amdgpu_gfx908::acc68, output_vec_len ); + case 837: return makeRegisterExpression(amdgpu_gfx908::acc69, output_vec_len ); + case 838: return makeRegisterExpression(amdgpu_gfx908::acc70, output_vec_len ); + case 839: return makeRegisterExpression(amdgpu_gfx908::acc71, output_vec_len ); + case 840: return makeRegisterExpression(amdgpu_gfx908::acc72, output_vec_len ); + case 841: return makeRegisterExpression(amdgpu_gfx908::acc73, output_vec_len ); + case 842: return makeRegisterExpression(amdgpu_gfx908::acc74, output_vec_len ); + case 843: return makeRegisterExpression(amdgpu_gfx908::acc75, output_vec_len ); + case 844: return makeRegisterExpression(amdgpu_gfx908::acc76, output_vec_len ); + case 845: return makeRegisterExpression(amdgpu_gfx908::acc77, output_vec_len ); + case 846: return makeRegisterExpression(amdgpu_gfx908::acc78, output_vec_len ); + case 847: return makeRegisterExpression(amdgpu_gfx908::acc79, output_vec_len ); + case 848: return makeRegisterExpression(amdgpu_gfx908::acc80, output_vec_len ); + case 849: return makeRegisterExpression(amdgpu_gfx908::acc81, output_vec_len ); + case 850: return makeRegisterExpression(amdgpu_gfx908::acc82, output_vec_len ); + case 851: return makeRegisterExpression(amdgpu_gfx908::acc83, output_vec_len ); + case 852: return makeRegisterExpression(amdgpu_gfx908::acc84, output_vec_len ); + case 853: return makeRegisterExpression(amdgpu_gfx908::acc85, output_vec_len ); + case 854: return makeRegisterExpression(amdgpu_gfx908::acc86, output_vec_len ); + case 855: return makeRegisterExpression(amdgpu_gfx908::acc87, output_vec_len ); + case 856: return makeRegisterExpression(amdgpu_gfx908::acc88, output_vec_len ); + case 857: return makeRegisterExpression(amdgpu_gfx908::acc89, output_vec_len ); + case 858: return makeRegisterExpression(amdgpu_gfx908::acc90, output_vec_len ); + case 859: return makeRegisterExpression(amdgpu_gfx908::acc91, output_vec_len ); + case 860: return makeRegisterExpression(amdgpu_gfx908::acc92, output_vec_len ); + case 861: return makeRegisterExpression(amdgpu_gfx908::acc93, output_vec_len ); + case 862: return makeRegisterExpression(amdgpu_gfx908::acc94, output_vec_len ); + case 863: return makeRegisterExpression(amdgpu_gfx908::acc95, output_vec_len ); + case 864: return makeRegisterExpression(amdgpu_gfx908::acc96, output_vec_len ); + case 865: return makeRegisterExpression(amdgpu_gfx908::acc97, output_vec_len ); + case 866: return makeRegisterExpression(amdgpu_gfx908::acc98, output_vec_len ); + case 867: return makeRegisterExpression(amdgpu_gfx908::acc99, output_vec_len ); + case 868: return makeRegisterExpression(amdgpu_gfx908::acc100, output_vec_len ); + case 869: return makeRegisterExpression(amdgpu_gfx908::acc101, output_vec_len ); + case 870: return makeRegisterExpression(amdgpu_gfx908::acc102, output_vec_len ); + case 871: return makeRegisterExpression(amdgpu_gfx908::acc103, output_vec_len ); + case 872: return makeRegisterExpression(amdgpu_gfx908::acc104, output_vec_len ); + case 873: return makeRegisterExpression(amdgpu_gfx908::acc105, output_vec_len ); + case 874: return makeRegisterExpression(amdgpu_gfx908::acc106, output_vec_len ); + case 875: return makeRegisterExpression(amdgpu_gfx908::acc107, output_vec_len ); + case 876: return makeRegisterExpression(amdgpu_gfx908::acc108, output_vec_len ); + case 877: return makeRegisterExpression(amdgpu_gfx908::acc109, output_vec_len ); + case 878: return makeRegisterExpression(amdgpu_gfx908::acc110, output_vec_len ); + case 879: return makeRegisterExpression(amdgpu_gfx908::acc111, output_vec_len ); + case 880: return makeRegisterExpression(amdgpu_gfx908::acc112, output_vec_len ); + case 881: return makeRegisterExpression(amdgpu_gfx908::acc113, output_vec_len ); + case 882: return makeRegisterExpression(amdgpu_gfx908::acc114, output_vec_len ); + case 883: return makeRegisterExpression(amdgpu_gfx908::acc115, output_vec_len ); + case 884: return makeRegisterExpression(amdgpu_gfx908::acc116, output_vec_len ); + case 885: return makeRegisterExpression(amdgpu_gfx908::acc117, output_vec_len ); + case 886: return makeRegisterExpression(amdgpu_gfx908::acc118, output_vec_len ); + case 887: return makeRegisterExpression(amdgpu_gfx908::acc119, output_vec_len ); + case 888: return makeRegisterExpression(amdgpu_gfx908::acc120, output_vec_len ); + case 889: return makeRegisterExpression(amdgpu_gfx908::acc121, output_vec_len ); + case 890: return makeRegisterExpression(amdgpu_gfx908::acc122, output_vec_len ); + case 891: return makeRegisterExpression(amdgpu_gfx908::acc123, output_vec_len ); + case 892: return makeRegisterExpression(amdgpu_gfx908::acc124, output_vec_len ); + case 893: return makeRegisterExpression(amdgpu_gfx908::acc125, output_vec_len ); + case 894: return makeRegisterExpression(amdgpu_gfx908::acc126, output_vec_len ); + case 895: return makeRegisterExpression(amdgpu_gfx908::acc127, output_vec_len ); + case 896: return makeRegisterExpression(amdgpu_gfx908::acc128, output_vec_len ); + case 897: return makeRegisterExpression(amdgpu_gfx908::acc129, output_vec_len ); + case 898: return makeRegisterExpression(amdgpu_gfx908::acc130, output_vec_len ); + case 899: return makeRegisterExpression(amdgpu_gfx908::acc131, output_vec_len ); + case 900: return makeRegisterExpression(amdgpu_gfx908::acc132, output_vec_len ); + case 901: return makeRegisterExpression(amdgpu_gfx908::acc133, output_vec_len ); + case 902: return makeRegisterExpression(amdgpu_gfx908::acc134, output_vec_len ); + case 903: return makeRegisterExpression(amdgpu_gfx908::acc135, output_vec_len ); + case 904: return makeRegisterExpression(amdgpu_gfx908::acc136, output_vec_len ); + case 905: return makeRegisterExpression(amdgpu_gfx908::acc137, output_vec_len ); + case 906: return makeRegisterExpression(amdgpu_gfx908::acc138, output_vec_len ); + case 907: return makeRegisterExpression(amdgpu_gfx908::acc139, output_vec_len ); + case 908: return makeRegisterExpression(amdgpu_gfx908::acc140, output_vec_len ); + case 909: return makeRegisterExpression(amdgpu_gfx908::acc141, output_vec_len ); + case 910: return makeRegisterExpression(amdgpu_gfx908::acc142, output_vec_len ); + case 911: return makeRegisterExpression(amdgpu_gfx908::acc143, output_vec_len ); + case 912: return makeRegisterExpression(amdgpu_gfx908::acc144, output_vec_len ); + case 913: return makeRegisterExpression(amdgpu_gfx908::acc145, output_vec_len ); + case 914: return makeRegisterExpression(amdgpu_gfx908::acc146, output_vec_len ); + case 915: return makeRegisterExpression(amdgpu_gfx908::acc147, output_vec_len ); + case 916: return makeRegisterExpression(amdgpu_gfx908::acc148, output_vec_len ); + case 917: return makeRegisterExpression(amdgpu_gfx908::acc149, output_vec_len ); + case 918: return makeRegisterExpression(amdgpu_gfx908::acc150, output_vec_len ); + case 919: return makeRegisterExpression(amdgpu_gfx908::acc151, output_vec_len ); + case 920: return makeRegisterExpression(amdgpu_gfx908::acc152, output_vec_len ); + case 921: return makeRegisterExpression(amdgpu_gfx908::acc153, output_vec_len ); + case 922: return makeRegisterExpression(amdgpu_gfx908::acc154, output_vec_len ); + case 923: return makeRegisterExpression(amdgpu_gfx908::acc155, output_vec_len ); + case 924: return makeRegisterExpression(amdgpu_gfx908::acc156, output_vec_len ); + case 925: return makeRegisterExpression(amdgpu_gfx908::acc157, output_vec_len ); + case 926: return makeRegisterExpression(amdgpu_gfx908::acc158, output_vec_len ); + case 927: return makeRegisterExpression(amdgpu_gfx908::acc159, output_vec_len ); + case 928: return makeRegisterExpression(amdgpu_gfx908::acc160, output_vec_len ); + case 929: return makeRegisterExpression(amdgpu_gfx908::acc161, output_vec_len ); + case 930: return makeRegisterExpression(amdgpu_gfx908::acc162, output_vec_len ); + case 931: return makeRegisterExpression(amdgpu_gfx908::acc163, output_vec_len ); + case 932: return makeRegisterExpression(amdgpu_gfx908::acc164, output_vec_len ); + case 933: return makeRegisterExpression(amdgpu_gfx908::acc165, output_vec_len ); + case 934: return makeRegisterExpression(amdgpu_gfx908::acc166, output_vec_len ); + case 935: return makeRegisterExpression(amdgpu_gfx908::acc167, output_vec_len ); + case 936: return makeRegisterExpression(amdgpu_gfx908::acc168, output_vec_len ); + case 937: return makeRegisterExpression(amdgpu_gfx908::acc169, output_vec_len ); + case 938: return makeRegisterExpression(amdgpu_gfx908::acc170, output_vec_len ); + case 939: return makeRegisterExpression(amdgpu_gfx908::acc171, output_vec_len ); + case 940: return makeRegisterExpression(amdgpu_gfx908::acc172, output_vec_len ); + case 941: return makeRegisterExpression(amdgpu_gfx908::acc173, output_vec_len ); + case 942: return makeRegisterExpression(amdgpu_gfx908::acc174, output_vec_len ); + case 943: return makeRegisterExpression(amdgpu_gfx908::acc175, output_vec_len ); + case 944: return makeRegisterExpression(amdgpu_gfx908::acc176, output_vec_len ); + case 945: return makeRegisterExpression(amdgpu_gfx908::acc177, output_vec_len ); + case 946: return makeRegisterExpression(amdgpu_gfx908::acc178, output_vec_len ); + case 947: return makeRegisterExpression(amdgpu_gfx908::acc179, output_vec_len ); + case 948: return makeRegisterExpression(amdgpu_gfx908::acc180, output_vec_len ); + case 949: return makeRegisterExpression(amdgpu_gfx908::acc181, output_vec_len ); + case 950: return makeRegisterExpression(amdgpu_gfx908::acc182, output_vec_len ); + case 951: return makeRegisterExpression(amdgpu_gfx908::acc183, output_vec_len ); + case 952: return makeRegisterExpression(amdgpu_gfx908::acc184, output_vec_len ); + case 953: return makeRegisterExpression(amdgpu_gfx908::acc185, output_vec_len ); + case 954: return makeRegisterExpression(amdgpu_gfx908::acc186, output_vec_len ); + case 955: return makeRegisterExpression(amdgpu_gfx908::acc187, output_vec_len ); + case 956: return makeRegisterExpression(amdgpu_gfx908::acc188, output_vec_len ); + case 957: return makeRegisterExpression(amdgpu_gfx908::acc189, output_vec_len ); + case 958: return makeRegisterExpression(amdgpu_gfx908::acc190, output_vec_len ); + case 959: return makeRegisterExpression(amdgpu_gfx908::acc191, output_vec_len ); + case 960: return makeRegisterExpression(amdgpu_gfx908::acc192, output_vec_len ); + case 961: return makeRegisterExpression(amdgpu_gfx908::acc193, output_vec_len ); + case 962: return makeRegisterExpression(amdgpu_gfx908::acc194, output_vec_len ); + case 963: return makeRegisterExpression(amdgpu_gfx908::acc195, output_vec_len ); + case 964: return makeRegisterExpression(amdgpu_gfx908::acc196, output_vec_len ); + case 965: return makeRegisterExpression(amdgpu_gfx908::acc197, output_vec_len ); + case 966: return makeRegisterExpression(amdgpu_gfx908::acc198, output_vec_len ); + case 967: return makeRegisterExpression(amdgpu_gfx908::acc199, output_vec_len ); + case 968: return makeRegisterExpression(amdgpu_gfx908::acc200, output_vec_len ); + case 969: return makeRegisterExpression(amdgpu_gfx908::acc201, output_vec_len ); + case 970: return makeRegisterExpression(amdgpu_gfx908::acc202, output_vec_len ); + case 971: return makeRegisterExpression(amdgpu_gfx908::acc203, output_vec_len ); + case 972: return makeRegisterExpression(amdgpu_gfx908::acc204, output_vec_len ); + case 973: return makeRegisterExpression(amdgpu_gfx908::acc205, output_vec_len ); + case 974: return makeRegisterExpression(amdgpu_gfx908::acc206, output_vec_len ); + case 975: return makeRegisterExpression(amdgpu_gfx908::acc207, output_vec_len ); + case 976: return makeRegisterExpression(amdgpu_gfx908::acc208, output_vec_len ); + case 977: return makeRegisterExpression(amdgpu_gfx908::acc209, output_vec_len ); + case 978: return makeRegisterExpression(amdgpu_gfx908::acc210, output_vec_len ); + case 979: return makeRegisterExpression(amdgpu_gfx908::acc211, output_vec_len ); + case 980: return makeRegisterExpression(amdgpu_gfx908::acc212, output_vec_len ); + case 981: return makeRegisterExpression(amdgpu_gfx908::acc213, output_vec_len ); + case 982: return makeRegisterExpression(amdgpu_gfx908::acc214, output_vec_len ); + case 983: return makeRegisterExpression(amdgpu_gfx908::acc215, output_vec_len ); + case 984: return makeRegisterExpression(amdgpu_gfx908::acc216, output_vec_len ); + case 985: return makeRegisterExpression(amdgpu_gfx908::acc217, output_vec_len ); + case 986: return makeRegisterExpression(amdgpu_gfx908::acc218, output_vec_len ); + case 987: return makeRegisterExpression(amdgpu_gfx908::acc219, output_vec_len ); + case 988: return makeRegisterExpression(amdgpu_gfx908::acc220, output_vec_len ); + case 989: return makeRegisterExpression(amdgpu_gfx908::acc221, output_vec_len ); + case 990: return makeRegisterExpression(amdgpu_gfx908::acc222, output_vec_len ); + case 991: return makeRegisterExpression(amdgpu_gfx908::acc223, output_vec_len ); + case 992: return makeRegisterExpression(amdgpu_gfx908::acc224, output_vec_len ); + case 993: return makeRegisterExpression(amdgpu_gfx908::acc225, output_vec_len ); + case 994: return makeRegisterExpression(amdgpu_gfx908::acc226, output_vec_len ); + case 995: return makeRegisterExpression(amdgpu_gfx908::acc227, output_vec_len ); + case 996: return makeRegisterExpression(amdgpu_gfx908::acc228, output_vec_len ); + case 997: return makeRegisterExpression(amdgpu_gfx908::acc229, output_vec_len ); + case 998: return makeRegisterExpression(amdgpu_gfx908::acc230, output_vec_len ); + case 999: return makeRegisterExpression(amdgpu_gfx908::acc231, output_vec_len ); + case 1000: return makeRegisterExpression(amdgpu_gfx908::acc232, output_vec_len ); + case 1001: return makeRegisterExpression(amdgpu_gfx908::acc233, output_vec_len ); + case 1002: return makeRegisterExpression(amdgpu_gfx908::acc234, output_vec_len ); + case 1003: return makeRegisterExpression(amdgpu_gfx908::acc235, output_vec_len ); + case 1004: return makeRegisterExpression(amdgpu_gfx908::acc236, output_vec_len ); + case 1005: return makeRegisterExpression(amdgpu_gfx908::acc237, output_vec_len ); + case 1006: return makeRegisterExpression(amdgpu_gfx908::acc238, output_vec_len ); + case 1007: return makeRegisterExpression(amdgpu_gfx908::acc239, output_vec_len ); + case 1008: return makeRegisterExpression(amdgpu_gfx908::acc240, output_vec_len ); + case 1009: return makeRegisterExpression(amdgpu_gfx908::acc241, output_vec_len ); + case 1010: return makeRegisterExpression(amdgpu_gfx908::acc242, output_vec_len ); + case 1011: return makeRegisterExpression(amdgpu_gfx908::acc243, output_vec_len ); + case 1012: return makeRegisterExpression(amdgpu_gfx908::acc244, output_vec_len ); + case 1013: return makeRegisterExpression(amdgpu_gfx908::acc245, output_vec_len ); + case 1014: return makeRegisterExpression(amdgpu_gfx908::acc246, output_vec_len ); + case 1015: return makeRegisterExpression(amdgpu_gfx908::acc247, output_vec_len ); + case 1016: return makeRegisterExpression(amdgpu_gfx908::acc248, output_vec_len ); + case 1017: return makeRegisterExpression(amdgpu_gfx908::acc249, output_vec_len ); + case 1018: return makeRegisterExpression(amdgpu_gfx908::acc250, output_vec_len ); + case 1019: return makeRegisterExpression(amdgpu_gfx908::acc251, output_vec_len ); + case 1020: return makeRegisterExpression(amdgpu_gfx908::acc252, output_vec_len ); + case 1021: return makeRegisterExpression(amdgpu_gfx908::acc253, output_vec_len ); + case 1022: return makeRegisterExpression(amdgpu_gfx908::acc254, output_vec_len ); + case 1023: return makeRegisterExpression(amdgpu_gfx908::acc255, output_vec_len ); + default: return makeRegisterExpression(amdgpu_gfx908::invalid); + } + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_ATTR(uint64_t input, uint32_t output_vec_len) + { + switch (input) { + case 0: return makeRegisterExpression(amdgpu_gfx908::attr0, output_vec_len ); + case 1: return makeRegisterExpression(amdgpu_gfx908::attr1, output_vec_len ); + case 2: return makeRegisterExpression(amdgpu_gfx908::attr2, output_vec_len ); + case 3: return makeRegisterExpression(amdgpu_gfx908::attr3, output_vec_len ); + case 4: return makeRegisterExpression(amdgpu_gfx908::attr4, output_vec_len ); + case 5: return makeRegisterExpression(amdgpu_gfx908::attr5, output_vec_len ); + case 6: return makeRegisterExpression(amdgpu_gfx908::attr6, output_vec_len ); + case 7: return makeRegisterExpression(amdgpu_gfx908::attr7, output_vec_len ); + case 8: return makeRegisterExpression(amdgpu_gfx908::attr8, output_vec_len ); + case 9: return makeRegisterExpression(amdgpu_gfx908::attr9, output_vec_len ); + case 10: return makeRegisterExpression(amdgpu_gfx908::attr10, output_vec_len ); + case 11: return makeRegisterExpression(amdgpu_gfx908::attr11, output_vec_len ); + case 12: return makeRegisterExpression(amdgpu_gfx908::attr12, output_vec_len ); + case 13: return makeRegisterExpression(amdgpu_gfx908::attr13, output_vec_len ); + case 14: return makeRegisterExpression(amdgpu_gfx908::attr14, output_vec_len ); + case 15: return makeRegisterExpression(amdgpu_gfx908::attr15, output_vec_len ); + case 16: return makeRegisterExpression(amdgpu_gfx908::attr16, output_vec_len ); + case 17: return makeRegisterExpression(amdgpu_gfx908::attr17, output_vec_len ); + case 18: return makeRegisterExpression(amdgpu_gfx908::attr18, output_vec_len ); + case 19: return makeRegisterExpression(amdgpu_gfx908::attr19, output_vec_len ); + case 20: return makeRegisterExpression(amdgpu_gfx908::attr20, output_vec_len ); + case 21: return makeRegisterExpression(amdgpu_gfx908::attr21, output_vec_len ); + case 22: return makeRegisterExpression(amdgpu_gfx908::attr22, output_vec_len ); + case 23: return makeRegisterExpression(amdgpu_gfx908::attr23, output_vec_len ); + case 24: return makeRegisterExpression(amdgpu_gfx908::attr24, output_vec_len ); + case 25: return makeRegisterExpression(amdgpu_gfx908::attr25, output_vec_len ); + case 26: return makeRegisterExpression(amdgpu_gfx908::attr26, output_vec_len ); + case 27: return makeRegisterExpression(amdgpu_gfx908::attr27, output_vec_len ); + case 28: return makeRegisterExpression(amdgpu_gfx908::attr28, output_vec_len ); + case 29: return makeRegisterExpression(amdgpu_gfx908::attr29, output_vec_len ); + case 30: return makeRegisterExpression(amdgpu_gfx908::attr30, output_vec_len ); + case 31: return makeRegisterExpression(amdgpu_gfx908::attr31, output_vec_len ); + case 32: return makeRegisterExpression(amdgpu_gfx908::attr32, output_vec_len ); + default: return makeRegisterExpression(amdgpu_gfx908::invalid); + } + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_DSMEM(uint64_t input, uint32_t output_vec_len) + { + switch (input) { + case 0: return makeRegisterExpression(amdgpu_gfx908::dsmem, output_vec_len ); + default: return makeRegisterExpression(amdgpu_gfx908::invalid); + } + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_FLAT_SCRATCH(uint64_t input, uint32_t output_vec_len) + { + switch (input) { + case 0: return makeRegisterExpression(amdgpu_gfx908::flat_scratch_all, output_vec_len ); + default: return makeRegisterExpression(amdgpu_gfx908::invalid); + } + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_PARAM(uint64_t input, uint32_t output_vec_len) + { + switch (input) { + case 0: return makeRegisterExpression(amdgpu_gfx908::p10, output_vec_len ); + case 1: return makeRegisterExpression(amdgpu_gfx908::p20, output_vec_len ); + case 2: return makeRegisterExpression(amdgpu_gfx908::p0, output_vec_len ); + default: return makeRegisterExpression(amdgpu_gfx908::invalid); + } + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_PC(uint64_t input, uint32_t ) + { + switch (input) { + case 0: return makeRegisterExpression(amdgpu_gfx908::pc_all); + default: return makeRegisterExpression(amdgpu_gfx908::invalid); + } + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SDST(uint64_t input, uint32_t output_vec_len) + { + switch (input) { + case 0: return makeRegisterExpression(amdgpu_gfx908::s0, output_vec_len ); + case 1: return makeRegisterExpression(amdgpu_gfx908::s1, output_vec_len ); + case 2: return makeRegisterExpression(amdgpu_gfx908::s2, output_vec_len ); + case 3: return makeRegisterExpression(amdgpu_gfx908::s3, output_vec_len ); + case 4: return makeRegisterExpression(amdgpu_gfx908::s4, output_vec_len ); + case 5: return makeRegisterExpression(amdgpu_gfx908::s5, output_vec_len ); + case 6: return makeRegisterExpression(amdgpu_gfx908::s6, output_vec_len ); + case 7: return makeRegisterExpression(amdgpu_gfx908::s7, output_vec_len ); + case 8: return makeRegisterExpression(amdgpu_gfx908::s8, output_vec_len ); + case 9: return makeRegisterExpression(amdgpu_gfx908::s9, output_vec_len ); + case 10: return makeRegisterExpression(amdgpu_gfx908::s10, output_vec_len ); + case 11: return makeRegisterExpression(amdgpu_gfx908::s11, output_vec_len ); + case 12: return makeRegisterExpression(amdgpu_gfx908::s12, output_vec_len ); + case 13: return makeRegisterExpression(amdgpu_gfx908::s13, output_vec_len ); + case 14: return makeRegisterExpression(amdgpu_gfx908::s14, output_vec_len ); + case 15: return makeRegisterExpression(amdgpu_gfx908::s15, output_vec_len ); + case 16: return makeRegisterExpression(amdgpu_gfx908::s16, output_vec_len ); + case 17: return makeRegisterExpression(amdgpu_gfx908::s17, output_vec_len ); + case 18: return makeRegisterExpression(amdgpu_gfx908::s18, output_vec_len ); + case 19: return makeRegisterExpression(amdgpu_gfx908::s19, output_vec_len ); + case 20: return makeRegisterExpression(amdgpu_gfx908::s20, output_vec_len ); + case 21: return makeRegisterExpression(amdgpu_gfx908::s21, output_vec_len ); + case 22: return makeRegisterExpression(amdgpu_gfx908::s22, output_vec_len ); + case 23: return makeRegisterExpression(amdgpu_gfx908::s23, output_vec_len ); + case 24: return makeRegisterExpression(amdgpu_gfx908::s24, output_vec_len ); + case 25: return makeRegisterExpression(amdgpu_gfx908::s25, output_vec_len ); + case 26: return makeRegisterExpression(amdgpu_gfx908::s26, output_vec_len ); + case 27: return makeRegisterExpression(amdgpu_gfx908::s27, output_vec_len ); + case 28: return makeRegisterExpression(amdgpu_gfx908::s28, output_vec_len ); + case 29: return makeRegisterExpression(amdgpu_gfx908::s29, output_vec_len ); + case 30: return makeRegisterExpression(amdgpu_gfx908::s30, output_vec_len ); + case 31: return makeRegisterExpression(amdgpu_gfx908::s31, output_vec_len ); + case 32: return makeRegisterExpression(amdgpu_gfx908::s32, output_vec_len ); + case 33: return makeRegisterExpression(amdgpu_gfx908::s33, output_vec_len ); + case 34: return makeRegisterExpression(amdgpu_gfx908::s34, output_vec_len ); + case 35: return makeRegisterExpression(amdgpu_gfx908::s35, output_vec_len ); + case 36: return makeRegisterExpression(amdgpu_gfx908::s36, output_vec_len ); + case 37: return makeRegisterExpression(amdgpu_gfx908::s37, output_vec_len ); + case 38: return makeRegisterExpression(amdgpu_gfx908::s38, output_vec_len ); + case 39: return makeRegisterExpression(amdgpu_gfx908::s39, output_vec_len ); + case 40: return makeRegisterExpression(amdgpu_gfx908::s40, output_vec_len ); + case 41: return makeRegisterExpression(amdgpu_gfx908::s41, output_vec_len ); + case 42: return makeRegisterExpression(amdgpu_gfx908::s42, output_vec_len ); + case 43: return makeRegisterExpression(amdgpu_gfx908::s43, output_vec_len ); + case 44: return makeRegisterExpression(amdgpu_gfx908::s44, output_vec_len ); + case 45: return makeRegisterExpression(amdgpu_gfx908::s45, output_vec_len ); + case 46: return makeRegisterExpression(amdgpu_gfx908::s46, output_vec_len ); + case 47: return makeRegisterExpression(amdgpu_gfx908::s47, output_vec_len ); + case 48: return makeRegisterExpression(amdgpu_gfx908::s48, output_vec_len ); + case 49: return makeRegisterExpression(amdgpu_gfx908::s49, output_vec_len ); + case 50: return makeRegisterExpression(amdgpu_gfx908::s50, output_vec_len ); + case 51: return makeRegisterExpression(amdgpu_gfx908::s51, output_vec_len ); + case 52: return makeRegisterExpression(amdgpu_gfx908::s52, output_vec_len ); + case 53: return makeRegisterExpression(amdgpu_gfx908::s53, output_vec_len ); + case 54: return makeRegisterExpression(amdgpu_gfx908::s54, output_vec_len ); + case 55: return makeRegisterExpression(amdgpu_gfx908::s55, output_vec_len ); + case 56: return makeRegisterExpression(amdgpu_gfx908::s56, output_vec_len ); + case 57: return makeRegisterExpression(amdgpu_gfx908::s57, output_vec_len ); + case 58: return makeRegisterExpression(amdgpu_gfx908::s58, output_vec_len ); + case 59: return makeRegisterExpression(amdgpu_gfx908::s59, output_vec_len ); + case 60: return makeRegisterExpression(amdgpu_gfx908::s60, output_vec_len ); + case 61: return makeRegisterExpression(amdgpu_gfx908::s61, output_vec_len ); + case 62: return makeRegisterExpression(amdgpu_gfx908::s62, output_vec_len ); + case 63: return makeRegisterExpression(amdgpu_gfx908::s63, output_vec_len ); + case 64: return makeRegisterExpression(amdgpu_gfx908::s64, output_vec_len ); + case 65: return makeRegisterExpression(amdgpu_gfx908::s65, output_vec_len ); + case 66: return makeRegisterExpression(amdgpu_gfx908::s66, output_vec_len ); + case 67: return makeRegisterExpression(amdgpu_gfx908::s67, output_vec_len ); + case 68: return makeRegisterExpression(amdgpu_gfx908::s68, output_vec_len ); + case 69: return makeRegisterExpression(amdgpu_gfx908::s69, output_vec_len ); + case 70: return makeRegisterExpression(amdgpu_gfx908::s70, output_vec_len ); + case 71: return makeRegisterExpression(amdgpu_gfx908::s71, output_vec_len ); + case 72: return makeRegisterExpression(amdgpu_gfx908::s72, output_vec_len ); + case 73: return makeRegisterExpression(amdgpu_gfx908::s73, output_vec_len ); + case 74: return makeRegisterExpression(amdgpu_gfx908::s74, output_vec_len ); + case 75: return makeRegisterExpression(amdgpu_gfx908::s75, output_vec_len ); + case 76: return makeRegisterExpression(amdgpu_gfx908::s76, output_vec_len ); + case 77: return makeRegisterExpression(amdgpu_gfx908::s77, output_vec_len ); + case 78: return makeRegisterExpression(amdgpu_gfx908::s78, output_vec_len ); + case 79: return makeRegisterExpression(amdgpu_gfx908::s79, output_vec_len ); + case 80: return makeRegisterExpression(amdgpu_gfx908::s80, output_vec_len ); + case 81: return makeRegisterExpression(amdgpu_gfx908::s81, output_vec_len ); + case 82: return makeRegisterExpression(amdgpu_gfx908::s82, output_vec_len ); + case 83: return makeRegisterExpression(amdgpu_gfx908::s83, output_vec_len ); + case 84: return makeRegisterExpression(amdgpu_gfx908::s84, output_vec_len ); + case 85: return makeRegisterExpression(amdgpu_gfx908::s85, output_vec_len ); + case 86: return makeRegisterExpression(amdgpu_gfx908::s86, output_vec_len ); + case 87: return makeRegisterExpression(amdgpu_gfx908::s87, output_vec_len ); + case 88: return makeRegisterExpression(amdgpu_gfx908::s88, output_vec_len ); + case 89: return makeRegisterExpression(amdgpu_gfx908::s89, output_vec_len ); + case 90: return makeRegisterExpression(amdgpu_gfx908::s90, output_vec_len ); + case 91: return makeRegisterExpression(amdgpu_gfx908::s91, output_vec_len ); + case 92: return makeRegisterExpression(amdgpu_gfx908::s92, output_vec_len ); + case 93: return makeRegisterExpression(amdgpu_gfx908::s93, output_vec_len ); + case 94: return makeRegisterExpression(amdgpu_gfx908::s94, output_vec_len ); + case 95: return makeRegisterExpression(amdgpu_gfx908::s95, output_vec_len ); + case 96: return makeRegisterExpression(amdgpu_gfx908::s96, output_vec_len ); + case 97: return makeRegisterExpression(amdgpu_gfx908::s97, output_vec_len ); + case 98: return makeRegisterExpression(amdgpu_gfx908::s98, output_vec_len ); + case 99: return makeRegisterExpression(amdgpu_gfx908::s99, output_vec_len ); + case 100: return makeRegisterExpression(amdgpu_gfx908::s100, output_vec_len ); + case 101: return makeRegisterExpression(amdgpu_gfx908::s101, output_vec_len ); + case 104: return makeRegisterExpression(amdgpu_gfx908::xnack_mask_lo, output_vec_len ); + case 105: return makeRegisterExpression(amdgpu_gfx908::xnack_mask_hi, output_vec_len ); + case 102: return makeRegisterExpression(amdgpu_gfx908::flat_scratch_lo, output_vec_len ); + case 103: return makeRegisterExpression(amdgpu_gfx908::flat_scratch_hi, output_vec_len ); + case 108: return makeRegisterExpression(amdgpu_gfx908::ttmp0, output_vec_len ); + case 109: return makeRegisterExpression(amdgpu_gfx908::ttmp1, output_vec_len ); + case 110: return makeRegisterExpression(amdgpu_gfx908::ttmp2, output_vec_len ); + case 111: return makeRegisterExpression(amdgpu_gfx908::ttmp3, output_vec_len ); + case 112: return makeRegisterExpression(amdgpu_gfx908::ttmp4, output_vec_len ); + case 113: return makeRegisterExpression(amdgpu_gfx908::ttmp5, output_vec_len ); + case 114: return makeRegisterExpression(amdgpu_gfx908::ttmp6, output_vec_len ); + case 115: return makeRegisterExpression(amdgpu_gfx908::ttmp7, output_vec_len ); + case 116: return makeRegisterExpression(amdgpu_gfx908::ttmp8, output_vec_len ); + case 117: return makeRegisterExpression(amdgpu_gfx908::ttmp9, output_vec_len ); + case 118: return makeRegisterExpression(amdgpu_gfx908::ttmp10, output_vec_len ); + case 119: return makeRegisterExpression(amdgpu_gfx908::ttmp11, output_vec_len ); + case 120: return makeRegisterExpression(amdgpu_gfx908::ttmp12, output_vec_len ); + case 121: return makeRegisterExpression(amdgpu_gfx908::ttmp13, output_vec_len ); + case 122: return makeRegisterExpression(amdgpu_gfx908::ttmp14, output_vec_len ); + case 123: return makeRegisterExpression(amdgpu_gfx908::ttmp15, output_vec_len ); + case 106: return makeRegisterExpression(amdgpu_gfx908::vcc_lo, output_vec_len ); + case 107: return makeRegisterExpression(amdgpu_gfx908::vcc_hi, output_vec_len ); + case 124: return makeRegisterExpression(amdgpu_gfx908::m0, output_vec_len ); + case 126: return makeRegisterExpression(amdgpu_gfx908::exec_lo, output_vec_len ); + case 127: return makeRegisterExpression(amdgpu_gfx908::exec_hi, output_vec_len ); + default: return makeRegisterExpression(amdgpu_gfx908::invalid); + } + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SDST_EXEC(uint64_t input, uint32_t output_vec_len) + { + switch (input) { + case 126: return makeRegisterExpression(amdgpu_gfx908::exec_lo, output_vec_len ); + case 127: return makeRegisterExpression(amdgpu_gfx908::exec_hi, output_vec_len ); + default: return makeRegisterExpression(amdgpu_gfx908::invalid); + } + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SDST_M0(uint64_t input, uint32_t output_vec_len) + { + switch (input) { + case 124: return makeRegisterExpression(amdgpu_gfx908::m0, output_vec_len ); + default: return makeRegisterExpression(amdgpu_gfx908::invalid); + } + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SRC(uint64_t input, uint32_t output_vec_len) + { + switch (input) { + case 0: return makeRegisterExpression(amdgpu_gfx908::s0, output_vec_len ); + case 1: return makeRegisterExpression(amdgpu_gfx908::s1, output_vec_len ); + case 2: return makeRegisterExpression(amdgpu_gfx908::s2, output_vec_len ); + case 3: return makeRegisterExpression(amdgpu_gfx908::s3, output_vec_len ); + case 4: return makeRegisterExpression(amdgpu_gfx908::s4, output_vec_len ); + case 5: return makeRegisterExpression(amdgpu_gfx908::s5, output_vec_len ); + case 6: return makeRegisterExpression(amdgpu_gfx908::s6, output_vec_len ); + case 7: return makeRegisterExpression(amdgpu_gfx908::s7, output_vec_len ); + case 8: return makeRegisterExpression(amdgpu_gfx908::s8, output_vec_len ); + case 9: return makeRegisterExpression(amdgpu_gfx908::s9, output_vec_len ); + case 10: return makeRegisterExpression(amdgpu_gfx908::s10, output_vec_len ); + case 11: return makeRegisterExpression(amdgpu_gfx908::s11, output_vec_len ); + case 12: return makeRegisterExpression(amdgpu_gfx908::s12, output_vec_len ); + case 13: return makeRegisterExpression(amdgpu_gfx908::s13, output_vec_len ); + case 14: return makeRegisterExpression(amdgpu_gfx908::s14, output_vec_len ); + case 15: return makeRegisterExpression(amdgpu_gfx908::s15, output_vec_len ); + case 16: return makeRegisterExpression(amdgpu_gfx908::s16, output_vec_len ); + case 17: return makeRegisterExpression(amdgpu_gfx908::s17, output_vec_len ); + case 18: return makeRegisterExpression(amdgpu_gfx908::s18, output_vec_len ); + case 19: return makeRegisterExpression(amdgpu_gfx908::s19, output_vec_len ); + case 20: return makeRegisterExpression(amdgpu_gfx908::s20, output_vec_len ); + case 21: return makeRegisterExpression(amdgpu_gfx908::s21, output_vec_len ); + case 22: return makeRegisterExpression(amdgpu_gfx908::s22, output_vec_len ); + case 23: return makeRegisterExpression(amdgpu_gfx908::s23, output_vec_len ); + case 24: return makeRegisterExpression(amdgpu_gfx908::s24, output_vec_len ); + case 25: return makeRegisterExpression(amdgpu_gfx908::s25, output_vec_len ); + case 26: return makeRegisterExpression(amdgpu_gfx908::s26, output_vec_len ); + case 27: return makeRegisterExpression(amdgpu_gfx908::s27, output_vec_len ); + case 28: return makeRegisterExpression(amdgpu_gfx908::s28, output_vec_len ); + case 29: return makeRegisterExpression(amdgpu_gfx908::s29, output_vec_len ); + case 30: return makeRegisterExpression(amdgpu_gfx908::s30, output_vec_len ); + case 31: return makeRegisterExpression(amdgpu_gfx908::s31, output_vec_len ); + case 32: return makeRegisterExpression(amdgpu_gfx908::s32, output_vec_len ); + case 33: return makeRegisterExpression(amdgpu_gfx908::s33, output_vec_len ); + case 34: return makeRegisterExpression(amdgpu_gfx908::s34, output_vec_len ); + case 35: return makeRegisterExpression(amdgpu_gfx908::s35, output_vec_len ); + case 36: return makeRegisterExpression(amdgpu_gfx908::s36, output_vec_len ); + case 37: return makeRegisterExpression(amdgpu_gfx908::s37, output_vec_len ); + case 38: return makeRegisterExpression(amdgpu_gfx908::s38, output_vec_len ); + case 39: return makeRegisterExpression(amdgpu_gfx908::s39, output_vec_len ); + case 40: return makeRegisterExpression(amdgpu_gfx908::s40, output_vec_len ); + case 41: return makeRegisterExpression(amdgpu_gfx908::s41, output_vec_len ); + case 42: return makeRegisterExpression(amdgpu_gfx908::s42, output_vec_len ); + case 43: return makeRegisterExpression(amdgpu_gfx908::s43, output_vec_len ); + case 44: return makeRegisterExpression(amdgpu_gfx908::s44, output_vec_len ); + case 45: return makeRegisterExpression(amdgpu_gfx908::s45, output_vec_len ); + case 46: return makeRegisterExpression(amdgpu_gfx908::s46, output_vec_len ); + case 47: return makeRegisterExpression(amdgpu_gfx908::s47, output_vec_len ); + case 48: return makeRegisterExpression(amdgpu_gfx908::s48, output_vec_len ); + case 49: return makeRegisterExpression(amdgpu_gfx908::s49, output_vec_len ); + case 50: return makeRegisterExpression(amdgpu_gfx908::s50, output_vec_len ); + case 51: return makeRegisterExpression(amdgpu_gfx908::s51, output_vec_len ); + case 52: return makeRegisterExpression(amdgpu_gfx908::s52, output_vec_len ); + case 53: return makeRegisterExpression(amdgpu_gfx908::s53, output_vec_len ); + case 54: return makeRegisterExpression(amdgpu_gfx908::s54, output_vec_len ); + case 55: return makeRegisterExpression(amdgpu_gfx908::s55, output_vec_len ); + case 56: return makeRegisterExpression(amdgpu_gfx908::s56, output_vec_len ); + case 57: return makeRegisterExpression(amdgpu_gfx908::s57, output_vec_len ); + case 58: return makeRegisterExpression(amdgpu_gfx908::s58, output_vec_len ); + case 59: return makeRegisterExpression(amdgpu_gfx908::s59, output_vec_len ); + case 60: return makeRegisterExpression(amdgpu_gfx908::s60, output_vec_len ); + case 61: return makeRegisterExpression(amdgpu_gfx908::s61, output_vec_len ); + case 62: return makeRegisterExpression(amdgpu_gfx908::s62, output_vec_len ); + case 63: return makeRegisterExpression(amdgpu_gfx908::s63, output_vec_len ); + case 64: return makeRegisterExpression(amdgpu_gfx908::s64, output_vec_len ); + case 65: return makeRegisterExpression(amdgpu_gfx908::s65, output_vec_len ); + case 66: return makeRegisterExpression(amdgpu_gfx908::s66, output_vec_len ); + case 67: return makeRegisterExpression(amdgpu_gfx908::s67, output_vec_len ); + case 68: return makeRegisterExpression(amdgpu_gfx908::s68, output_vec_len ); + case 69: return makeRegisterExpression(amdgpu_gfx908::s69, output_vec_len ); + case 70: return makeRegisterExpression(amdgpu_gfx908::s70, output_vec_len ); + case 71: return makeRegisterExpression(amdgpu_gfx908::s71, output_vec_len ); + case 72: return makeRegisterExpression(amdgpu_gfx908::s72, output_vec_len ); + case 73: return makeRegisterExpression(amdgpu_gfx908::s73, output_vec_len ); + case 74: return makeRegisterExpression(amdgpu_gfx908::s74, output_vec_len ); + case 75: return makeRegisterExpression(amdgpu_gfx908::s75, output_vec_len ); + case 76: return makeRegisterExpression(amdgpu_gfx908::s76, output_vec_len ); + case 77: return makeRegisterExpression(amdgpu_gfx908::s77, output_vec_len ); + case 78: return makeRegisterExpression(amdgpu_gfx908::s78, output_vec_len ); + case 79: return makeRegisterExpression(amdgpu_gfx908::s79, output_vec_len ); + case 80: return makeRegisterExpression(amdgpu_gfx908::s80, output_vec_len ); + case 81: return makeRegisterExpression(amdgpu_gfx908::s81, output_vec_len ); + case 82: return makeRegisterExpression(amdgpu_gfx908::s82, output_vec_len ); + case 83: return makeRegisterExpression(amdgpu_gfx908::s83, output_vec_len ); + case 84: return makeRegisterExpression(amdgpu_gfx908::s84, output_vec_len ); + case 85: return makeRegisterExpression(amdgpu_gfx908::s85, output_vec_len ); + case 86: return makeRegisterExpression(amdgpu_gfx908::s86, output_vec_len ); + case 87: return makeRegisterExpression(amdgpu_gfx908::s87, output_vec_len ); + case 88: return makeRegisterExpression(amdgpu_gfx908::s88, output_vec_len ); + case 89: return makeRegisterExpression(amdgpu_gfx908::s89, output_vec_len ); + case 90: return makeRegisterExpression(amdgpu_gfx908::s90, output_vec_len ); + case 91: return makeRegisterExpression(amdgpu_gfx908::s91, output_vec_len ); + case 92: return makeRegisterExpression(amdgpu_gfx908::s92, output_vec_len ); + case 93: return makeRegisterExpression(amdgpu_gfx908::s93, output_vec_len ); + case 94: return makeRegisterExpression(amdgpu_gfx908::s94, output_vec_len ); + case 95: return makeRegisterExpression(amdgpu_gfx908::s95, output_vec_len ); + case 96: return makeRegisterExpression(amdgpu_gfx908::s96, output_vec_len ); + case 97: return makeRegisterExpression(amdgpu_gfx908::s97, output_vec_len ); + case 98: return makeRegisterExpression(amdgpu_gfx908::s98, output_vec_len ); + case 99: return makeRegisterExpression(amdgpu_gfx908::s99, output_vec_len ); + case 100: return makeRegisterExpression(amdgpu_gfx908::s100, output_vec_len ); + case 101: return makeRegisterExpression(amdgpu_gfx908::s101, output_vec_len ); + case 104: return makeRegisterExpression(amdgpu_gfx908::xnack_mask_lo, output_vec_len ); + case 105: return makeRegisterExpression(amdgpu_gfx908::xnack_mask_hi, output_vec_len ); + case 102: return makeRegisterExpression(amdgpu_gfx908::flat_scratch_lo, output_vec_len ); + case 103: return makeRegisterExpression(amdgpu_gfx908::flat_scratch_hi, output_vec_len ); + case 108: return makeRegisterExpression(amdgpu_gfx908::ttmp0, output_vec_len ); + case 109: return makeRegisterExpression(amdgpu_gfx908::ttmp1, output_vec_len ); + case 110: return makeRegisterExpression(amdgpu_gfx908::ttmp2, output_vec_len ); + case 111: return makeRegisterExpression(amdgpu_gfx908::ttmp3, output_vec_len ); + case 112: return makeRegisterExpression(amdgpu_gfx908::ttmp4, output_vec_len ); + case 113: return makeRegisterExpression(amdgpu_gfx908::ttmp5, output_vec_len ); + case 114: return makeRegisterExpression(amdgpu_gfx908::ttmp6, output_vec_len ); + case 115: return makeRegisterExpression(amdgpu_gfx908::ttmp7, output_vec_len ); + case 116: return makeRegisterExpression(amdgpu_gfx908::ttmp8, output_vec_len ); + case 117: return makeRegisterExpression(amdgpu_gfx908::ttmp9, output_vec_len ); + case 118: return makeRegisterExpression(amdgpu_gfx908::ttmp10, output_vec_len ); + case 119: return makeRegisterExpression(amdgpu_gfx908::ttmp11, output_vec_len ); + case 120: return makeRegisterExpression(amdgpu_gfx908::ttmp12, output_vec_len ); + case 121: return makeRegisterExpression(amdgpu_gfx908::ttmp13, output_vec_len ); + case 122: return makeRegisterExpression(amdgpu_gfx908::ttmp14, output_vec_len ); + case 123: return makeRegisterExpression(amdgpu_gfx908::ttmp15, output_vec_len ); + case 106: return makeRegisterExpression(amdgpu_gfx908::vcc_lo, output_vec_len ); + case 107: return makeRegisterExpression(amdgpu_gfx908::vcc_hi, output_vec_len ); + case 124: return makeRegisterExpression(amdgpu_gfx908::m0, output_vec_len ); + case 126: return makeRegisterExpression(amdgpu_gfx908::exec_lo, output_vec_len ); + case 127: return makeRegisterExpression(amdgpu_gfx908::exec_hi, output_vec_len ); + case 128: return Immediate::makeImmediate(Result(u32, 0)); + case 129: return Immediate::makeImmediate(Result(u32, 1)); + case 130: return Immediate::makeImmediate(Result(u32, 2)); + case 131: return Immediate::makeImmediate(Result(u32, 3)); + case 132: return Immediate::makeImmediate(Result(u32, 4)); + case 133: return Immediate::makeImmediate(Result(u32, 5)); + case 134: return Immediate::makeImmediate(Result(u32, 6)); + case 135: return Immediate::makeImmediate(Result(u32, 7)); + case 136: return Immediate::makeImmediate(Result(u32, 8)); + case 137: return Immediate::makeImmediate(Result(u32, 9)); + case 138: return Immediate::makeImmediate(Result(u32, 10)); + case 139: return Immediate::makeImmediate(Result(u32, 11)); + case 140: return Immediate::makeImmediate(Result(u32, 12)); + case 141: return Immediate::makeImmediate(Result(u32, 13)); + case 142: return Immediate::makeImmediate(Result(u32, 14)); + case 143: return Immediate::makeImmediate(Result(u32, 15)); + case 144: return Immediate::makeImmediate(Result(u32, 16)); + case 145: return Immediate::makeImmediate(Result(u32, 17)); + case 146: return Immediate::makeImmediate(Result(u32, 18)); + case 147: return Immediate::makeImmediate(Result(u32, 19)); + case 148: return Immediate::makeImmediate(Result(u32, 20)); + case 149: return Immediate::makeImmediate(Result(u32, 21)); + case 150: return Immediate::makeImmediate(Result(u32, 22)); + case 151: return Immediate::makeImmediate(Result(u32, 23)); + case 152: return Immediate::makeImmediate(Result(u32, 24)); + case 153: return Immediate::makeImmediate(Result(u32, 25)); + case 154: return Immediate::makeImmediate(Result(u32, 26)); + case 155: return Immediate::makeImmediate(Result(u32, 27)); + case 156: return Immediate::makeImmediate(Result(u32, 28)); + case 157: return Immediate::makeImmediate(Result(u32, 29)); + case 158: return Immediate::makeImmediate(Result(u32, 30)); + case 159: return Immediate::makeImmediate(Result(u32, 31)); + case 160: return Immediate::makeImmediate(Result(u32, 32)); + case 161: return Immediate::makeImmediate(Result(u32, 33)); + case 162: return Immediate::makeImmediate(Result(u32, 34)); + case 163: return Immediate::makeImmediate(Result(u32, 35)); + case 164: return Immediate::makeImmediate(Result(u32, 36)); + case 165: return Immediate::makeImmediate(Result(u32, 37)); + case 166: return Immediate::makeImmediate(Result(u32, 38)); + case 167: return Immediate::makeImmediate(Result(u32, 39)); + case 168: return Immediate::makeImmediate(Result(u32, 40)); + case 169: return Immediate::makeImmediate(Result(u32, 41)); + case 170: return Immediate::makeImmediate(Result(u32, 42)); + case 171: return Immediate::makeImmediate(Result(u32, 43)); + case 172: return Immediate::makeImmediate(Result(u32, 44)); + case 173: return Immediate::makeImmediate(Result(u32, 45)); + case 174: return Immediate::makeImmediate(Result(u32, 46)); + case 175: return Immediate::makeImmediate(Result(u32, 47)); + case 176: return Immediate::makeImmediate(Result(u32, 48)); + case 177: return Immediate::makeImmediate(Result(u32, 49)); + case 178: return Immediate::makeImmediate(Result(u32, 50)); + case 179: return Immediate::makeImmediate(Result(u32, 51)); + case 180: return Immediate::makeImmediate(Result(u32, 52)); + case 181: return Immediate::makeImmediate(Result(u32, 53)); + case 182: return Immediate::makeImmediate(Result(u32, 54)); + case 183: return Immediate::makeImmediate(Result(u32, 55)); + case 184: return Immediate::makeImmediate(Result(u32, 56)); + case 185: return Immediate::makeImmediate(Result(u32, 57)); + case 186: return Immediate::makeImmediate(Result(u32, 58)); + case 187: return Immediate::makeImmediate(Result(u32, 59)); + case 188: return Immediate::makeImmediate(Result(u32, 60)); + case 189: return Immediate::makeImmediate(Result(u32, 61)); + case 190: return Immediate::makeImmediate(Result(u32, 62)); + case 191: return Immediate::makeImmediate(Result(u32, 63)); + case 192: return Immediate::makeImmediate(Result(u32, 64)); + case 193: return Immediate::makeImmediate(Result(u32, -1)); + case 194: return Immediate::makeImmediate(Result(u32, -2)); + case 195: return Immediate::makeImmediate(Result(u32, -3)); + case 196: return Immediate::makeImmediate(Result(u32, -4)); + case 197: return Immediate::makeImmediate(Result(u32, -5)); + case 198: return Immediate::makeImmediate(Result(u32, -6)); + case 199: return Immediate::makeImmediate(Result(u32, -7)); + case 200: return Immediate::makeImmediate(Result(u32, -8)); + case 201: return Immediate::makeImmediate(Result(u32, -9)); + case 202: return Immediate::makeImmediate(Result(u32, -10)); + case 203: return Immediate::makeImmediate(Result(u32, -11)); + case 204: return Immediate::makeImmediate(Result(u32, -12)); + case 205: return Immediate::makeImmediate(Result(u32, -13)); + case 206: return Immediate::makeImmediate(Result(u32, -14)); + case 207: return Immediate::makeImmediate(Result(u32, -15)); + case 208: return Immediate::makeImmediate(Result(u32, -16)); + case 240: return Immediate::makeImmediate(Result(sp_float, 0.5)); + case 241: return Immediate::makeImmediate(Result(sp_float, -0.5)); + case 242: return Immediate::makeImmediate(Result(sp_float, 1.0)); + case 243: return Immediate::makeImmediate(Result(sp_float, -1.0)); + case 244: return Immediate::makeImmediate(Result(sp_float, 2.0)); + case 245: return Immediate::makeImmediate(Result(sp_float, -2.0)); + case 246: return Immediate::makeImmediate(Result(sp_float, 4.0)); + case 247: return Immediate::makeImmediate(Result(sp_float, -4.0)); + case 248: return Immediate::makeImmediate(Result(sp_float, 0.15915494)); + case 251: return makeRegisterExpression(amdgpu_gfx908::src_vccz, output_vec_len ); + case 252: return makeRegisterExpression(amdgpu_gfx908::src_execz, output_vec_len ); + case 253: return makeRegisterExpression(amdgpu_gfx908::src_scc, output_vec_len ); + case 235: return makeRegisterExpression(amdgpu_gfx908::src_shared_base, output_vec_len ); + case 236: return makeRegisterExpression(amdgpu_gfx908::src_shared_limit, output_vec_len ); + case 237: return makeRegisterExpression(amdgpu_gfx908::src_private_base, output_vec_len ); + case 238: return makeRegisterExpression(amdgpu_gfx908::src_private_limit, output_vec_len ); + case 239: return makeRegisterExpression(amdgpu_gfx908::src_pops_exiting_wave_id, output_vec_len ); + case 256: return makeRegisterExpression(amdgpu_gfx908::v0, output_vec_len ); + case 257: return makeRegisterExpression(amdgpu_gfx908::v1, output_vec_len ); + case 258: return makeRegisterExpression(amdgpu_gfx908::v2, output_vec_len ); + case 259: return makeRegisterExpression(amdgpu_gfx908::v3, output_vec_len ); + case 260: return makeRegisterExpression(amdgpu_gfx908::v4, output_vec_len ); + case 261: return makeRegisterExpression(amdgpu_gfx908::v5, output_vec_len ); + case 262: return makeRegisterExpression(amdgpu_gfx908::v6, output_vec_len ); + case 263: return makeRegisterExpression(amdgpu_gfx908::v7, output_vec_len ); + case 264: return makeRegisterExpression(amdgpu_gfx908::v8, output_vec_len ); + case 265: return makeRegisterExpression(amdgpu_gfx908::v9, output_vec_len ); + case 266: return makeRegisterExpression(amdgpu_gfx908::v10, output_vec_len ); + case 267: return makeRegisterExpression(amdgpu_gfx908::v11, output_vec_len ); + case 268: return makeRegisterExpression(amdgpu_gfx908::v12, output_vec_len ); + case 269: return makeRegisterExpression(amdgpu_gfx908::v13, output_vec_len ); + case 270: return makeRegisterExpression(amdgpu_gfx908::v14, output_vec_len ); + case 271: return makeRegisterExpression(amdgpu_gfx908::v15, output_vec_len ); + case 272: return makeRegisterExpression(amdgpu_gfx908::v16, output_vec_len ); + case 273: return makeRegisterExpression(amdgpu_gfx908::v17, output_vec_len ); + case 274: return makeRegisterExpression(amdgpu_gfx908::v18, output_vec_len ); + case 275: return makeRegisterExpression(amdgpu_gfx908::v19, output_vec_len ); + case 276: return makeRegisterExpression(amdgpu_gfx908::v20, output_vec_len ); + case 277: return makeRegisterExpression(amdgpu_gfx908::v21, output_vec_len ); + case 278: return makeRegisterExpression(amdgpu_gfx908::v22, output_vec_len ); + case 279: return makeRegisterExpression(amdgpu_gfx908::v23, output_vec_len ); + case 280: return makeRegisterExpression(amdgpu_gfx908::v24, output_vec_len ); + case 281: return makeRegisterExpression(amdgpu_gfx908::v25, output_vec_len ); + case 282: return makeRegisterExpression(amdgpu_gfx908::v26, output_vec_len ); + case 283: return makeRegisterExpression(amdgpu_gfx908::v27, output_vec_len ); + case 284: return makeRegisterExpression(amdgpu_gfx908::v28, output_vec_len ); + case 285: return makeRegisterExpression(amdgpu_gfx908::v29, output_vec_len ); + case 286: return makeRegisterExpression(amdgpu_gfx908::v30, output_vec_len ); + case 287: return makeRegisterExpression(amdgpu_gfx908::v31, output_vec_len ); + case 288: return makeRegisterExpression(amdgpu_gfx908::v32, output_vec_len ); + case 289: return makeRegisterExpression(amdgpu_gfx908::v33, output_vec_len ); + case 290: return makeRegisterExpression(amdgpu_gfx908::v34, output_vec_len ); + case 291: return makeRegisterExpression(amdgpu_gfx908::v35, output_vec_len ); + case 292: return makeRegisterExpression(amdgpu_gfx908::v36, output_vec_len ); + case 293: return makeRegisterExpression(amdgpu_gfx908::v37, output_vec_len ); + case 294: return makeRegisterExpression(amdgpu_gfx908::v38, output_vec_len ); + case 295: return makeRegisterExpression(amdgpu_gfx908::v39, output_vec_len ); + case 296: return makeRegisterExpression(amdgpu_gfx908::v40, output_vec_len ); + case 297: return makeRegisterExpression(amdgpu_gfx908::v41, output_vec_len ); + case 298: return makeRegisterExpression(amdgpu_gfx908::v42, output_vec_len ); + case 299: return makeRegisterExpression(amdgpu_gfx908::v43, output_vec_len ); + case 300: return makeRegisterExpression(amdgpu_gfx908::v44, output_vec_len ); + case 301: return makeRegisterExpression(amdgpu_gfx908::v45, output_vec_len ); + case 302: return makeRegisterExpression(amdgpu_gfx908::v46, output_vec_len ); + case 303: return makeRegisterExpression(amdgpu_gfx908::v47, output_vec_len ); + case 304: return makeRegisterExpression(amdgpu_gfx908::v48, output_vec_len ); + case 305: return makeRegisterExpression(amdgpu_gfx908::v49, output_vec_len ); + case 306: return makeRegisterExpression(amdgpu_gfx908::v50, output_vec_len ); + case 307: return makeRegisterExpression(amdgpu_gfx908::v51, output_vec_len ); + case 308: return makeRegisterExpression(amdgpu_gfx908::v52, output_vec_len ); + case 309: return makeRegisterExpression(amdgpu_gfx908::v53, output_vec_len ); + case 310: return makeRegisterExpression(amdgpu_gfx908::v54, output_vec_len ); + case 311: return makeRegisterExpression(amdgpu_gfx908::v55, output_vec_len ); + case 312: return makeRegisterExpression(amdgpu_gfx908::v56, output_vec_len ); + case 313: return makeRegisterExpression(amdgpu_gfx908::v57, output_vec_len ); + case 314: return makeRegisterExpression(amdgpu_gfx908::v58, output_vec_len ); + case 315: return makeRegisterExpression(amdgpu_gfx908::v59, output_vec_len ); + case 316: return makeRegisterExpression(amdgpu_gfx908::v60, output_vec_len ); + case 317: return makeRegisterExpression(amdgpu_gfx908::v61, output_vec_len ); + case 318: return makeRegisterExpression(amdgpu_gfx908::v62, output_vec_len ); + case 319: return makeRegisterExpression(amdgpu_gfx908::v63, output_vec_len ); + case 320: return makeRegisterExpression(amdgpu_gfx908::v64, output_vec_len ); + case 321: return makeRegisterExpression(amdgpu_gfx908::v65, output_vec_len ); + case 322: return makeRegisterExpression(amdgpu_gfx908::v66, output_vec_len ); + case 323: return makeRegisterExpression(amdgpu_gfx908::v67, output_vec_len ); + case 324: return makeRegisterExpression(amdgpu_gfx908::v68, output_vec_len ); + case 325: return makeRegisterExpression(amdgpu_gfx908::v69, output_vec_len ); + case 326: return makeRegisterExpression(amdgpu_gfx908::v70, output_vec_len ); + case 327: return makeRegisterExpression(amdgpu_gfx908::v71, output_vec_len ); + case 328: return makeRegisterExpression(amdgpu_gfx908::v72, output_vec_len ); + case 329: return makeRegisterExpression(amdgpu_gfx908::v73, output_vec_len ); + case 330: return makeRegisterExpression(amdgpu_gfx908::v74, output_vec_len ); + case 331: return makeRegisterExpression(amdgpu_gfx908::v75, output_vec_len ); + case 332: return makeRegisterExpression(amdgpu_gfx908::v76, output_vec_len ); + case 333: return makeRegisterExpression(amdgpu_gfx908::v77, output_vec_len ); + case 334: return makeRegisterExpression(amdgpu_gfx908::v78, output_vec_len ); + case 335: return makeRegisterExpression(amdgpu_gfx908::v79, output_vec_len ); + case 336: return makeRegisterExpression(amdgpu_gfx908::v80, output_vec_len ); + case 337: return makeRegisterExpression(amdgpu_gfx908::v81, output_vec_len ); + case 338: return makeRegisterExpression(amdgpu_gfx908::v82, output_vec_len ); + case 339: return makeRegisterExpression(amdgpu_gfx908::v83, output_vec_len ); + case 340: return makeRegisterExpression(amdgpu_gfx908::v84, output_vec_len ); + case 341: return makeRegisterExpression(amdgpu_gfx908::v85, output_vec_len ); + case 342: return makeRegisterExpression(amdgpu_gfx908::v86, output_vec_len ); + case 343: return makeRegisterExpression(amdgpu_gfx908::v87, output_vec_len ); + case 344: return makeRegisterExpression(amdgpu_gfx908::v88, output_vec_len ); + case 345: return makeRegisterExpression(amdgpu_gfx908::v89, output_vec_len ); + case 346: return makeRegisterExpression(amdgpu_gfx908::v90, output_vec_len ); + case 347: return makeRegisterExpression(amdgpu_gfx908::v91, output_vec_len ); + case 348: return makeRegisterExpression(amdgpu_gfx908::v92, output_vec_len ); + case 349: return makeRegisterExpression(amdgpu_gfx908::v93, output_vec_len ); + case 350: return makeRegisterExpression(amdgpu_gfx908::v94, output_vec_len ); + case 351: return makeRegisterExpression(amdgpu_gfx908::v95, output_vec_len ); + case 352: return makeRegisterExpression(amdgpu_gfx908::v96, output_vec_len ); + case 353: return makeRegisterExpression(amdgpu_gfx908::v97, output_vec_len ); + case 354: return makeRegisterExpression(amdgpu_gfx908::v98, output_vec_len ); + case 355: return makeRegisterExpression(amdgpu_gfx908::v99, output_vec_len ); + case 356: return makeRegisterExpression(amdgpu_gfx908::v100, output_vec_len ); + case 357: return makeRegisterExpression(amdgpu_gfx908::v101, output_vec_len ); + case 358: return makeRegisterExpression(amdgpu_gfx908::v102, output_vec_len ); + case 359: return makeRegisterExpression(amdgpu_gfx908::v103, output_vec_len ); + case 360: return makeRegisterExpression(amdgpu_gfx908::v104, output_vec_len ); + case 361: return makeRegisterExpression(amdgpu_gfx908::v105, output_vec_len ); + case 362: return makeRegisterExpression(amdgpu_gfx908::v106, output_vec_len ); + case 363: return makeRegisterExpression(amdgpu_gfx908::v107, output_vec_len ); + case 364: return makeRegisterExpression(amdgpu_gfx908::v108, output_vec_len ); + case 365: return makeRegisterExpression(amdgpu_gfx908::v109, output_vec_len ); + case 366: return makeRegisterExpression(amdgpu_gfx908::v110, output_vec_len ); + case 367: return makeRegisterExpression(amdgpu_gfx908::v111, output_vec_len ); + case 368: return makeRegisterExpression(amdgpu_gfx908::v112, output_vec_len ); + case 369: return makeRegisterExpression(amdgpu_gfx908::v113, output_vec_len ); + case 370: return makeRegisterExpression(amdgpu_gfx908::v114, output_vec_len ); + case 371: return makeRegisterExpression(amdgpu_gfx908::v115, output_vec_len ); + case 372: return makeRegisterExpression(amdgpu_gfx908::v116, output_vec_len ); + case 373: return makeRegisterExpression(amdgpu_gfx908::v117, output_vec_len ); + case 374: return makeRegisterExpression(amdgpu_gfx908::v118, output_vec_len ); + case 375: return makeRegisterExpression(amdgpu_gfx908::v119, output_vec_len ); + case 376: return makeRegisterExpression(amdgpu_gfx908::v120, output_vec_len ); + case 377: return makeRegisterExpression(amdgpu_gfx908::v121, output_vec_len ); + case 378: return makeRegisterExpression(amdgpu_gfx908::v122, output_vec_len ); + case 379: return makeRegisterExpression(amdgpu_gfx908::v123, output_vec_len ); + case 380: return makeRegisterExpression(amdgpu_gfx908::v124, output_vec_len ); + case 381: return makeRegisterExpression(amdgpu_gfx908::v125, output_vec_len ); + case 382: return makeRegisterExpression(amdgpu_gfx908::v126, output_vec_len ); + case 383: return makeRegisterExpression(amdgpu_gfx908::v127, output_vec_len ); + case 384: return makeRegisterExpression(amdgpu_gfx908::v128, output_vec_len ); + case 385: return makeRegisterExpression(amdgpu_gfx908::v129, output_vec_len ); + case 386: return makeRegisterExpression(amdgpu_gfx908::v130, output_vec_len ); + case 387: return makeRegisterExpression(amdgpu_gfx908::v131, output_vec_len ); + case 388: return makeRegisterExpression(amdgpu_gfx908::v132, output_vec_len ); + case 389: return makeRegisterExpression(amdgpu_gfx908::v133, output_vec_len ); + case 390: return makeRegisterExpression(amdgpu_gfx908::v134, output_vec_len ); + case 391: return makeRegisterExpression(amdgpu_gfx908::v135, output_vec_len ); + case 392: return makeRegisterExpression(amdgpu_gfx908::v136, output_vec_len ); + case 393: return makeRegisterExpression(amdgpu_gfx908::v137, output_vec_len ); + case 394: return makeRegisterExpression(amdgpu_gfx908::v138, output_vec_len ); + case 395: return makeRegisterExpression(amdgpu_gfx908::v139, output_vec_len ); + case 396: return makeRegisterExpression(amdgpu_gfx908::v140, output_vec_len ); + case 397: return makeRegisterExpression(amdgpu_gfx908::v141, output_vec_len ); + case 398: return makeRegisterExpression(amdgpu_gfx908::v142, output_vec_len ); + case 399: return makeRegisterExpression(amdgpu_gfx908::v143, output_vec_len ); + case 400: return makeRegisterExpression(amdgpu_gfx908::v144, output_vec_len ); + case 401: return makeRegisterExpression(amdgpu_gfx908::v145, output_vec_len ); + case 402: return makeRegisterExpression(amdgpu_gfx908::v146, output_vec_len ); + case 403: return makeRegisterExpression(amdgpu_gfx908::v147, output_vec_len ); + case 404: return makeRegisterExpression(amdgpu_gfx908::v148, output_vec_len ); + case 405: return makeRegisterExpression(amdgpu_gfx908::v149, output_vec_len ); + case 406: return makeRegisterExpression(amdgpu_gfx908::v150, output_vec_len ); + case 407: return makeRegisterExpression(amdgpu_gfx908::v151, output_vec_len ); + case 408: return makeRegisterExpression(amdgpu_gfx908::v152, output_vec_len ); + case 409: return makeRegisterExpression(amdgpu_gfx908::v153, output_vec_len ); + case 410: return makeRegisterExpression(amdgpu_gfx908::v154, output_vec_len ); + case 411: return makeRegisterExpression(amdgpu_gfx908::v155, output_vec_len ); + case 412: return makeRegisterExpression(amdgpu_gfx908::v156, output_vec_len ); + case 413: return makeRegisterExpression(amdgpu_gfx908::v157, output_vec_len ); + case 414: return makeRegisterExpression(amdgpu_gfx908::v158, output_vec_len ); + case 415: return makeRegisterExpression(amdgpu_gfx908::v159, output_vec_len ); + case 416: return makeRegisterExpression(amdgpu_gfx908::v160, output_vec_len ); + case 417: return makeRegisterExpression(amdgpu_gfx908::v161, output_vec_len ); + case 418: return makeRegisterExpression(amdgpu_gfx908::v162, output_vec_len ); + case 419: return makeRegisterExpression(amdgpu_gfx908::v163, output_vec_len ); + case 420: return makeRegisterExpression(amdgpu_gfx908::v164, output_vec_len ); + case 421: return makeRegisterExpression(amdgpu_gfx908::v165, output_vec_len ); + case 422: return makeRegisterExpression(amdgpu_gfx908::v166, output_vec_len ); + case 423: return makeRegisterExpression(amdgpu_gfx908::v167, output_vec_len ); + case 424: return makeRegisterExpression(amdgpu_gfx908::v168, output_vec_len ); + case 425: return makeRegisterExpression(amdgpu_gfx908::v169, output_vec_len ); + case 426: return makeRegisterExpression(amdgpu_gfx908::v170, output_vec_len ); + case 427: return makeRegisterExpression(amdgpu_gfx908::v171, output_vec_len ); + case 428: return makeRegisterExpression(amdgpu_gfx908::v172, output_vec_len ); + case 429: return makeRegisterExpression(amdgpu_gfx908::v173, output_vec_len ); + case 430: return makeRegisterExpression(amdgpu_gfx908::v174, output_vec_len ); + case 431: return makeRegisterExpression(amdgpu_gfx908::v175, output_vec_len ); + case 432: return makeRegisterExpression(amdgpu_gfx908::v176, output_vec_len ); + case 433: return makeRegisterExpression(amdgpu_gfx908::v177, output_vec_len ); + case 434: return makeRegisterExpression(amdgpu_gfx908::v178, output_vec_len ); + case 435: return makeRegisterExpression(amdgpu_gfx908::v179, output_vec_len ); + case 436: return makeRegisterExpression(amdgpu_gfx908::v180, output_vec_len ); + case 437: return makeRegisterExpression(amdgpu_gfx908::v181, output_vec_len ); + case 438: return makeRegisterExpression(amdgpu_gfx908::v182, output_vec_len ); + case 439: return makeRegisterExpression(amdgpu_gfx908::v183, output_vec_len ); + case 440: return makeRegisterExpression(amdgpu_gfx908::v184, output_vec_len ); + case 441: return makeRegisterExpression(amdgpu_gfx908::v185, output_vec_len ); + case 442: return makeRegisterExpression(amdgpu_gfx908::v186, output_vec_len ); + case 443: return makeRegisterExpression(amdgpu_gfx908::v187, output_vec_len ); + case 444: return makeRegisterExpression(amdgpu_gfx908::v188, output_vec_len ); + case 445: return makeRegisterExpression(amdgpu_gfx908::v189, output_vec_len ); + case 446: return makeRegisterExpression(amdgpu_gfx908::v190, output_vec_len ); + case 447: return makeRegisterExpression(amdgpu_gfx908::v191, output_vec_len ); + case 448: return makeRegisterExpression(amdgpu_gfx908::v192, output_vec_len ); + case 449: return makeRegisterExpression(amdgpu_gfx908::v193, output_vec_len ); + case 450: return makeRegisterExpression(amdgpu_gfx908::v194, output_vec_len ); + case 451: return makeRegisterExpression(amdgpu_gfx908::v195, output_vec_len ); + case 452: return makeRegisterExpression(amdgpu_gfx908::v196, output_vec_len ); + case 453: return makeRegisterExpression(amdgpu_gfx908::v197, output_vec_len ); + case 454: return makeRegisterExpression(amdgpu_gfx908::v198, output_vec_len ); + case 455: return makeRegisterExpression(amdgpu_gfx908::v199, output_vec_len ); + case 456: return makeRegisterExpression(amdgpu_gfx908::v200, output_vec_len ); + case 457: return makeRegisterExpression(amdgpu_gfx908::v201, output_vec_len ); + case 458: return makeRegisterExpression(amdgpu_gfx908::v202, output_vec_len ); + case 459: return makeRegisterExpression(amdgpu_gfx908::v203, output_vec_len ); + case 460: return makeRegisterExpression(amdgpu_gfx908::v204, output_vec_len ); + case 461: return makeRegisterExpression(amdgpu_gfx908::v205, output_vec_len ); + case 462: return makeRegisterExpression(amdgpu_gfx908::v206, output_vec_len ); + case 463: return makeRegisterExpression(amdgpu_gfx908::v207, output_vec_len ); + case 464: return makeRegisterExpression(amdgpu_gfx908::v208, output_vec_len ); + case 465: return makeRegisterExpression(amdgpu_gfx908::v209, output_vec_len ); + case 466: return makeRegisterExpression(amdgpu_gfx908::v210, output_vec_len ); + case 467: return makeRegisterExpression(amdgpu_gfx908::v211, output_vec_len ); + case 468: return makeRegisterExpression(amdgpu_gfx908::v212, output_vec_len ); + case 469: return makeRegisterExpression(amdgpu_gfx908::v213, output_vec_len ); + case 470: return makeRegisterExpression(amdgpu_gfx908::v214, output_vec_len ); + case 471: return makeRegisterExpression(amdgpu_gfx908::v215, output_vec_len ); + case 472: return makeRegisterExpression(amdgpu_gfx908::v216, output_vec_len ); + case 473: return makeRegisterExpression(amdgpu_gfx908::v217, output_vec_len ); + case 474: return makeRegisterExpression(amdgpu_gfx908::v218, output_vec_len ); + case 475: return makeRegisterExpression(amdgpu_gfx908::v219, output_vec_len ); + case 476: return makeRegisterExpression(amdgpu_gfx908::v220, output_vec_len ); + case 477: return makeRegisterExpression(amdgpu_gfx908::v221, output_vec_len ); + case 478: return makeRegisterExpression(amdgpu_gfx908::v222, output_vec_len ); + case 479: return makeRegisterExpression(amdgpu_gfx908::v223, output_vec_len ); + case 480: return makeRegisterExpression(amdgpu_gfx908::v224, output_vec_len ); + case 481: return makeRegisterExpression(amdgpu_gfx908::v225, output_vec_len ); + case 482: return makeRegisterExpression(amdgpu_gfx908::v226, output_vec_len ); + case 483: return makeRegisterExpression(amdgpu_gfx908::v227, output_vec_len ); + case 484: return makeRegisterExpression(amdgpu_gfx908::v228, output_vec_len ); + case 485: return makeRegisterExpression(amdgpu_gfx908::v229, output_vec_len ); + case 486: return makeRegisterExpression(amdgpu_gfx908::v230, output_vec_len ); + case 487: return makeRegisterExpression(amdgpu_gfx908::v231, output_vec_len ); + case 488: return makeRegisterExpression(amdgpu_gfx908::v232, output_vec_len ); + case 489: return makeRegisterExpression(amdgpu_gfx908::v233, output_vec_len ); + case 490: return makeRegisterExpression(amdgpu_gfx908::v234, output_vec_len ); + case 491: return makeRegisterExpression(amdgpu_gfx908::v235, output_vec_len ); + case 492: return makeRegisterExpression(amdgpu_gfx908::v236, output_vec_len ); + case 493: return makeRegisterExpression(amdgpu_gfx908::v237, output_vec_len ); + case 494: return makeRegisterExpression(amdgpu_gfx908::v238, output_vec_len ); + case 495: return makeRegisterExpression(amdgpu_gfx908::v239, output_vec_len ); + case 496: return makeRegisterExpression(amdgpu_gfx908::v240, output_vec_len ); + case 497: return makeRegisterExpression(amdgpu_gfx908::v241, output_vec_len ); + case 498: return makeRegisterExpression(amdgpu_gfx908::v242, output_vec_len ); + case 499: return makeRegisterExpression(amdgpu_gfx908::v243, output_vec_len ); + case 500: return makeRegisterExpression(amdgpu_gfx908::v244, output_vec_len ); + case 501: return makeRegisterExpression(amdgpu_gfx908::v245, output_vec_len ); + case 502: return makeRegisterExpression(amdgpu_gfx908::v246, output_vec_len ); + case 503: return makeRegisterExpression(amdgpu_gfx908::v247, output_vec_len ); + case 504: return makeRegisterExpression(amdgpu_gfx908::v248, output_vec_len ); + case 505: return makeRegisterExpression(amdgpu_gfx908::v249, output_vec_len ); + case 506: return makeRegisterExpression(amdgpu_gfx908::v250, output_vec_len ); + case 507: return makeRegisterExpression(amdgpu_gfx908::v251, output_vec_len ); + case 508: return makeRegisterExpression(amdgpu_gfx908::v252, output_vec_len ); + case 509: return makeRegisterExpression(amdgpu_gfx908::v253, output_vec_len ); + case 510: return makeRegisterExpression(amdgpu_gfx908::v254, output_vec_len ); + case 511: return makeRegisterExpression(amdgpu_gfx908::v255, output_vec_len ); + case 254: return makeRegisterExpression(amdgpu_gfx908::src_lds_direct, output_vec_len ); + case 255: return Immediate::makeImmediate(Result(u32,decodeOPR_LITERAL())); + case 249 : return decodeOPR_SDWA(); + default: return makeRegisterExpression(amdgpu_gfx908::invalid); + } + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SRC_ACCVGPR(uint64_t input, uint32_t output_vec_len) + { + switch (input) { + case 256: return makeRegisterExpression(amdgpu_gfx908::acc0, output_vec_len ); + case 257: return makeRegisterExpression(amdgpu_gfx908::acc1, output_vec_len ); + case 258: return makeRegisterExpression(amdgpu_gfx908::acc2, output_vec_len ); + case 259: return makeRegisterExpression(amdgpu_gfx908::acc3, output_vec_len ); + case 260: return makeRegisterExpression(amdgpu_gfx908::acc4, output_vec_len ); + case 261: return makeRegisterExpression(amdgpu_gfx908::acc5, output_vec_len ); + case 262: return makeRegisterExpression(amdgpu_gfx908::acc6, output_vec_len ); + case 263: return makeRegisterExpression(amdgpu_gfx908::acc7, output_vec_len ); + case 264: return makeRegisterExpression(amdgpu_gfx908::acc8, output_vec_len ); + case 265: return makeRegisterExpression(amdgpu_gfx908::acc9, output_vec_len ); + case 266: return makeRegisterExpression(amdgpu_gfx908::acc10, output_vec_len ); + case 267: return makeRegisterExpression(amdgpu_gfx908::acc11, output_vec_len ); + case 268: return makeRegisterExpression(amdgpu_gfx908::acc12, output_vec_len ); + case 269: return makeRegisterExpression(amdgpu_gfx908::acc13, output_vec_len ); + case 270: return makeRegisterExpression(amdgpu_gfx908::acc14, output_vec_len ); + case 271: return makeRegisterExpression(amdgpu_gfx908::acc15, output_vec_len ); + case 272: return makeRegisterExpression(amdgpu_gfx908::acc16, output_vec_len ); + case 273: return makeRegisterExpression(amdgpu_gfx908::acc17, output_vec_len ); + case 274: return makeRegisterExpression(amdgpu_gfx908::acc18, output_vec_len ); + case 275: return makeRegisterExpression(amdgpu_gfx908::acc19, output_vec_len ); + case 276: return makeRegisterExpression(amdgpu_gfx908::acc20, output_vec_len ); + case 277: return makeRegisterExpression(amdgpu_gfx908::acc21, output_vec_len ); + case 278: return makeRegisterExpression(amdgpu_gfx908::acc22, output_vec_len ); + case 279: return makeRegisterExpression(amdgpu_gfx908::acc23, output_vec_len ); + case 280: return makeRegisterExpression(amdgpu_gfx908::acc24, output_vec_len ); + case 281: return makeRegisterExpression(amdgpu_gfx908::acc25, output_vec_len ); + case 282: return makeRegisterExpression(amdgpu_gfx908::acc26, output_vec_len ); + case 283: return makeRegisterExpression(amdgpu_gfx908::acc27, output_vec_len ); + case 284: return makeRegisterExpression(amdgpu_gfx908::acc28, output_vec_len ); + case 285: return makeRegisterExpression(amdgpu_gfx908::acc29, output_vec_len ); + case 286: return makeRegisterExpression(amdgpu_gfx908::acc30, output_vec_len ); + case 287: return makeRegisterExpression(amdgpu_gfx908::acc31, output_vec_len ); + case 288: return makeRegisterExpression(amdgpu_gfx908::acc32, output_vec_len ); + case 289: return makeRegisterExpression(amdgpu_gfx908::acc33, output_vec_len ); + case 290: return makeRegisterExpression(amdgpu_gfx908::acc34, output_vec_len ); + case 291: return makeRegisterExpression(amdgpu_gfx908::acc35, output_vec_len ); + case 292: return makeRegisterExpression(amdgpu_gfx908::acc36, output_vec_len ); + case 293: return makeRegisterExpression(amdgpu_gfx908::acc37, output_vec_len ); + case 294: return makeRegisterExpression(amdgpu_gfx908::acc38, output_vec_len ); + case 295: return makeRegisterExpression(amdgpu_gfx908::acc39, output_vec_len ); + case 296: return makeRegisterExpression(amdgpu_gfx908::acc40, output_vec_len ); + case 297: return makeRegisterExpression(amdgpu_gfx908::acc41, output_vec_len ); + case 298: return makeRegisterExpression(amdgpu_gfx908::acc42, output_vec_len ); + case 299: return makeRegisterExpression(amdgpu_gfx908::acc43, output_vec_len ); + case 300: return makeRegisterExpression(amdgpu_gfx908::acc44, output_vec_len ); + case 301: return makeRegisterExpression(amdgpu_gfx908::acc45, output_vec_len ); + case 302: return makeRegisterExpression(amdgpu_gfx908::acc46, output_vec_len ); + case 303: return makeRegisterExpression(amdgpu_gfx908::acc47, output_vec_len ); + case 304: return makeRegisterExpression(amdgpu_gfx908::acc48, output_vec_len ); + case 305: return makeRegisterExpression(amdgpu_gfx908::acc49, output_vec_len ); + case 306: return makeRegisterExpression(amdgpu_gfx908::acc50, output_vec_len ); + case 307: return makeRegisterExpression(amdgpu_gfx908::acc51, output_vec_len ); + case 308: return makeRegisterExpression(amdgpu_gfx908::acc52, output_vec_len ); + case 309: return makeRegisterExpression(amdgpu_gfx908::acc53, output_vec_len ); + case 310: return makeRegisterExpression(amdgpu_gfx908::acc54, output_vec_len ); + case 311: return makeRegisterExpression(amdgpu_gfx908::acc55, output_vec_len ); + case 312: return makeRegisterExpression(amdgpu_gfx908::acc56, output_vec_len ); + case 313: return makeRegisterExpression(amdgpu_gfx908::acc57, output_vec_len ); + case 314: return makeRegisterExpression(amdgpu_gfx908::acc58, output_vec_len ); + case 315: return makeRegisterExpression(amdgpu_gfx908::acc59, output_vec_len ); + case 316: return makeRegisterExpression(amdgpu_gfx908::acc60, output_vec_len ); + case 317: return makeRegisterExpression(amdgpu_gfx908::acc61, output_vec_len ); + case 318: return makeRegisterExpression(amdgpu_gfx908::acc62, output_vec_len ); + case 319: return makeRegisterExpression(amdgpu_gfx908::acc63, output_vec_len ); + case 320: return makeRegisterExpression(amdgpu_gfx908::acc64, output_vec_len ); + case 321: return makeRegisterExpression(amdgpu_gfx908::acc65, output_vec_len ); + case 322: return makeRegisterExpression(amdgpu_gfx908::acc66, output_vec_len ); + case 323: return makeRegisterExpression(amdgpu_gfx908::acc67, output_vec_len ); + case 324: return makeRegisterExpression(amdgpu_gfx908::acc68, output_vec_len ); + case 325: return makeRegisterExpression(amdgpu_gfx908::acc69, output_vec_len ); + case 326: return makeRegisterExpression(amdgpu_gfx908::acc70, output_vec_len ); + case 327: return makeRegisterExpression(amdgpu_gfx908::acc71, output_vec_len ); + case 328: return makeRegisterExpression(amdgpu_gfx908::acc72, output_vec_len ); + case 329: return makeRegisterExpression(amdgpu_gfx908::acc73, output_vec_len ); + case 330: return makeRegisterExpression(amdgpu_gfx908::acc74, output_vec_len ); + case 331: return makeRegisterExpression(amdgpu_gfx908::acc75, output_vec_len ); + case 332: return makeRegisterExpression(amdgpu_gfx908::acc76, output_vec_len ); + case 333: return makeRegisterExpression(amdgpu_gfx908::acc77, output_vec_len ); + case 334: return makeRegisterExpression(amdgpu_gfx908::acc78, output_vec_len ); + case 335: return makeRegisterExpression(amdgpu_gfx908::acc79, output_vec_len ); + case 336: return makeRegisterExpression(amdgpu_gfx908::acc80, output_vec_len ); + case 337: return makeRegisterExpression(amdgpu_gfx908::acc81, output_vec_len ); + case 338: return makeRegisterExpression(amdgpu_gfx908::acc82, output_vec_len ); + case 339: return makeRegisterExpression(amdgpu_gfx908::acc83, output_vec_len ); + case 340: return makeRegisterExpression(amdgpu_gfx908::acc84, output_vec_len ); + case 341: return makeRegisterExpression(amdgpu_gfx908::acc85, output_vec_len ); + case 342: return makeRegisterExpression(amdgpu_gfx908::acc86, output_vec_len ); + case 343: return makeRegisterExpression(amdgpu_gfx908::acc87, output_vec_len ); + case 344: return makeRegisterExpression(amdgpu_gfx908::acc88, output_vec_len ); + case 345: return makeRegisterExpression(amdgpu_gfx908::acc89, output_vec_len ); + case 346: return makeRegisterExpression(amdgpu_gfx908::acc90, output_vec_len ); + case 347: return makeRegisterExpression(amdgpu_gfx908::acc91, output_vec_len ); + case 348: return makeRegisterExpression(amdgpu_gfx908::acc92, output_vec_len ); + case 349: return makeRegisterExpression(amdgpu_gfx908::acc93, output_vec_len ); + case 350: return makeRegisterExpression(amdgpu_gfx908::acc94, output_vec_len ); + case 351: return makeRegisterExpression(amdgpu_gfx908::acc95, output_vec_len ); + case 352: return makeRegisterExpression(amdgpu_gfx908::acc96, output_vec_len ); + case 353: return makeRegisterExpression(amdgpu_gfx908::acc97, output_vec_len ); + case 354: return makeRegisterExpression(amdgpu_gfx908::acc98, output_vec_len ); + case 355: return makeRegisterExpression(amdgpu_gfx908::acc99, output_vec_len ); + case 356: return makeRegisterExpression(amdgpu_gfx908::acc100, output_vec_len ); + case 357: return makeRegisterExpression(amdgpu_gfx908::acc101, output_vec_len ); + case 358: return makeRegisterExpression(amdgpu_gfx908::acc102, output_vec_len ); + case 359: return makeRegisterExpression(amdgpu_gfx908::acc103, output_vec_len ); + case 360: return makeRegisterExpression(amdgpu_gfx908::acc104, output_vec_len ); + case 361: return makeRegisterExpression(amdgpu_gfx908::acc105, output_vec_len ); + case 362: return makeRegisterExpression(amdgpu_gfx908::acc106, output_vec_len ); + case 363: return makeRegisterExpression(amdgpu_gfx908::acc107, output_vec_len ); + case 364: return makeRegisterExpression(amdgpu_gfx908::acc108, output_vec_len ); + case 365: return makeRegisterExpression(amdgpu_gfx908::acc109, output_vec_len ); + case 366: return makeRegisterExpression(amdgpu_gfx908::acc110, output_vec_len ); + case 367: return makeRegisterExpression(amdgpu_gfx908::acc111, output_vec_len ); + case 368: return makeRegisterExpression(amdgpu_gfx908::acc112, output_vec_len ); + case 369: return makeRegisterExpression(amdgpu_gfx908::acc113, output_vec_len ); + case 370: return makeRegisterExpression(amdgpu_gfx908::acc114, output_vec_len ); + case 371: return makeRegisterExpression(amdgpu_gfx908::acc115, output_vec_len ); + case 372: return makeRegisterExpression(amdgpu_gfx908::acc116, output_vec_len ); + case 373: return makeRegisterExpression(amdgpu_gfx908::acc117, output_vec_len ); + case 374: return makeRegisterExpression(amdgpu_gfx908::acc118, output_vec_len ); + case 375: return makeRegisterExpression(amdgpu_gfx908::acc119, output_vec_len ); + case 376: return makeRegisterExpression(amdgpu_gfx908::acc120, output_vec_len ); + case 377: return makeRegisterExpression(amdgpu_gfx908::acc121, output_vec_len ); + case 378: return makeRegisterExpression(amdgpu_gfx908::acc122, output_vec_len ); + case 379: return makeRegisterExpression(amdgpu_gfx908::acc123, output_vec_len ); + case 380: return makeRegisterExpression(amdgpu_gfx908::acc124, output_vec_len ); + case 381: return makeRegisterExpression(amdgpu_gfx908::acc125, output_vec_len ); + case 382: return makeRegisterExpression(amdgpu_gfx908::acc126, output_vec_len ); + case 383: return makeRegisterExpression(amdgpu_gfx908::acc127, output_vec_len ); + case 384: return makeRegisterExpression(amdgpu_gfx908::acc128, output_vec_len ); + case 385: return makeRegisterExpression(amdgpu_gfx908::acc129, output_vec_len ); + case 386: return makeRegisterExpression(amdgpu_gfx908::acc130, output_vec_len ); + case 387: return makeRegisterExpression(amdgpu_gfx908::acc131, output_vec_len ); + case 388: return makeRegisterExpression(amdgpu_gfx908::acc132, output_vec_len ); + case 389: return makeRegisterExpression(amdgpu_gfx908::acc133, output_vec_len ); + case 390: return makeRegisterExpression(amdgpu_gfx908::acc134, output_vec_len ); + case 391: return makeRegisterExpression(amdgpu_gfx908::acc135, output_vec_len ); + case 392: return makeRegisterExpression(amdgpu_gfx908::acc136, output_vec_len ); + case 393: return makeRegisterExpression(amdgpu_gfx908::acc137, output_vec_len ); + case 394: return makeRegisterExpression(amdgpu_gfx908::acc138, output_vec_len ); + case 395: return makeRegisterExpression(amdgpu_gfx908::acc139, output_vec_len ); + case 396: return makeRegisterExpression(amdgpu_gfx908::acc140, output_vec_len ); + case 397: return makeRegisterExpression(amdgpu_gfx908::acc141, output_vec_len ); + case 398: return makeRegisterExpression(amdgpu_gfx908::acc142, output_vec_len ); + case 399: return makeRegisterExpression(amdgpu_gfx908::acc143, output_vec_len ); + case 400: return makeRegisterExpression(amdgpu_gfx908::acc144, output_vec_len ); + case 401: return makeRegisterExpression(amdgpu_gfx908::acc145, output_vec_len ); + case 402: return makeRegisterExpression(amdgpu_gfx908::acc146, output_vec_len ); + case 403: return makeRegisterExpression(amdgpu_gfx908::acc147, output_vec_len ); + case 404: return makeRegisterExpression(amdgpu_gfx908::acc148, output_vec_len ); + case 405: return makeRegisterExpression(amdgpu_gfx908::acc149, output_vec_len ); + case 406: return makeRegisterExpression(amdgpu_gfx908::acc150, output_vec_len ); + case 407: return makeRegisterExpression(amdgpu_gfx908::acc151, output_vec_len ); + case 408: return makeRegisterExpression(amdgpu_gfx908::acc152, output_vec_len ); + case 409: return makeRegisterExpression(amdgpu_gfx908::acc153, output_vec_len ); + case 410: return makeRegisterExpression(amdgpu_gfx908::acc154, output_vec_len ); + case 411: return makeRegisterExpression(amdgpu_gfx908::acc155, output_vec_len ); + case 412: return makeRegisterExpression(amdgpu_gfx908::acc156, output_vec_len ); + case 413: return makeRegisterExpression(amdgpu_gfx908::acc157, output_vec_len ); + case 414: return makeRegisterExpression(amdgpu_gfx908::acc158, output_vec_len ); + case 415: return makeRegisterExpression(amdgpu_gfx908::acc159, output_vec_len ); + case 416: return makeRegisterExpression(amdgpu_gfx908::acc160, output_vec_len ); + case 417: return makeRegisterExpression(amdgpu_gfx908::acc161, output_vec_len ); + case 418: return makeRegisterExpression(amdgpu_gfx908::acc162, output_vec_len ); + case 419: return makeRegisterExpression(amdgpu_gfx908::acc163, output_vec_len ); + case 420: return makeRegisterExpression(amdgpu_gfx908::acc164, output_vec_len ); + case 421: return makeRegisterExpression(amdgpu_gfx908::acc165, output_vec_len ); + case 422: return makeRegisterExpression(amdgpu_gfx908::acc166, output_vec_len ); + case 423: return makeRegisterExpression(amdgpu_gfx908::acc167, output_vec_len ); + case 424: return makeRegisterExpression(amdgpu_gfx908::acc168, output_vec_len ); + case 425: return makeRegisterExpression(amdgpu_gfx908::acc169, output_vec_len ); + case 426: return makeRegisterExpression(amdgpu_gfx908::acc170, output_vec_len ); + case 427: return makeRegisterExpression(amdgpu_gfx908::acc171, output_vec_len ); + case 428: return makeRegisterExpression(amdgpu_gfx908::acc172, output_vec_len ); + case 429: return makeRegisterExpression(amdgpu_gfx908::acc173, output_vec_len ); + case 430: return makeRegisterExpression(amdgpu_gfx908::acc174, output_vec_len ); + case 431: return makeRegisterExpression(amdgpu_gfx908::acc175, output_vec_len ); + case 432: return makeRegisterExpression(amdgpu_gfx908::acc176, output_vec_len ); + case 433: return makeRegisterExpression(amdgpu_gfx908::acc177, output_vec_len ); + case 434: return makeRegisterExpression(amdgpu_gfx908::acc178, output_vec_len ); + case 435: return makeRegisterExpression(amdgpu_gfx908::acc179, output_vec_len ); + case 436: return makeRegisterExpression(amdgpu_gfx908::acc180, output_vec_len ); + case 437: return makeRegisterExpression(amdgpu_gfx908::acc181, output_vec_len ); + case 438: return makeRegisterExpression(amdgpu_gfx908::acc182, output_vec_len ); + case 439: return makeRegisterExpression(amdgpu_gfx908::acc183, output_vec_len ); + case 440: return makeRegisterExpression(amdgpu_gfx908::acc184, output_vec_len ); + case 441: return makeRegisterExpression(amdgpu_gfx908::acc185, output_vec_len ); + case 442: return makeRegisterExpression(amdgpu_gfx908::acc186, output_vec_len ); + case 443: return makeRegisterExpression(amdgpu_gfx908::acc187, output_vec_len ); + case 444: return makeRegisterExpression(amdgpu_gfx908::acc188, output_vec_len ); + case 445: return makeRegisterExpression(amdgpu_gfx908::acc189, output_vec_len ); + case 446: return makeRegisterExpression(amdgpu_gfx908::acc190, output_vec_len ); + case 447: return makeRegisterExpression(amdgpu_gfx908::acc191, output_vec_len ); + case 448: return makeRegisterExpression(amdgpu_gfx908::acc192, output_vec_len ); + case 449: return makeRegisterExpression(amdgpu_gfx908::acc193, output_vec_len ); + case 450: return makeRegisterExpression(amdgpu_gfx908::acc194, output_vec_len ); + case 451: return makeRegisterExpression(amdgpu_gfx908::acc195, output_vec_len ); + case 452: return makeRegisterExpression(amdgpu_gfx908::acc196, output_vec_len ); + case 453: return makeRegisterExpression(amdgpu_gfx908::acc197, output_vec_len ); + case 454: return makeRegisterExpression(amdgpu_gfx908::acc198, output_vec_len ); + case 455: return makeRegisterExpression(amdgpu_gfx908::acc199, output_vec_len ); + case 456: return makeRegisterExpression(amdgpu_gfx908::acc200, output_vec_len ); + case 457: return makeRegisterExpression(amdgpu_gfx908::acc201, output_vec_len ); + case 458: return makeRegisterExpression(amdgpu_gfx908::acc202, output_vec_len ); + case 459: return makeRegisterExpression(amdgpu_gfx908::acc203, output_vec_len ); + case 460: return makeRegisterExpression(amdgpu_gfx908::acc204, output_vec_len ); + case 461: return makeRegisterExpression(amdgpu_gfx908::acc205, output_vec_len ); + case 462: return makeRegisterExpression(amdgpu_gfx908::acc206, output_vec_len ); + case 463: return makeRegisterExpression(amdgpu_gfx908::acc207, output_vec_len ); + case 464: return makeRegisterExpression(amdgpu_gfx908::acc208, output_vec_len ); + case 465: return makeRegisterExpression(amdgpu_gfx908::acc209, output_vec_len ); + case 466: return makeRegisterExpression(amdgpu_gfx908::acc210, output_vec_len ); + case 467: return makeRegisterExpression(amdgpu_gfx908::acc211, output_vec_len ); + case 468: return makeRegisterExpression(amdgpu_gfx908::acc212, output_vec_len ); + case 469: return makeRegisterExpression(amdgpu_gfx908::acc213, output_vec_len ); + case 470: return makeRegisterExpression(amdgpu_gfx908::acc214, output_vec_len ); + case 471: return makeRegisterExpression(amdgpu_gfx908::acc215, output_vec_len ); + case 472: return makeRegisterExpression(amdgpu_gfx908::acc216, output_vec_len ); + case 473: return makeRegisterExpression(amdgpu_gfx908::acc217, output_vec_len ); + case 474: return makeRegisterExpression(amdgpu_gfx908::acc218, output_vec_len ); + case 475: return makeRegisterExpression(amdgpu_gfx908::acc219, output_vec_len ); + case 476: return makeRegisterExpression(amdgpu_gfx908::acc220, output_vec_len ); + case 477: return makeRegisterExpression(amdgpu_gfx908::acc221, output_vec_len ); + case 478: return makeRegisterExpression(amdgpu_gfx908::acc222, output_vec_len ); + case 479: return makeRegisterExpression(amdgpu_gfx908::acc223, output_vec_len ); + case 480: return makeRegisterExpression(amdgpu_gfx908::acc224, output_vec_len ); + case 481: return makeRegisterExpression(amdgpu_gfx908::acc225, output_vec_len ); + case 482: return makeRegisterExpression(amdgpu_gfx908::acc226, output_vec_len ); + case 483: return makeRegisterExpression(amdgpu_gfx908::acc227, output_vec_len ); + case 484: return makeRegisterExpression(amdgpu_gfx908::acc228, output_vec_len ); + case 485: return makeRegisterExpression(amdgpu_gfx908::acc229, output_vec_len ); + case 486: return makeRegisterExpression(amdgpu_gfx908::acc230, output_vec_len ); + case 487: return makeRegisterExpression(amdgpu_gfx908::acc231, output_vec_len ); + case 488: return makeRegisterExpression(amdgpu_gfx908::acc232, output_vec_len ); + case 489: return makeRegisterExpression(amdgpu_gfx908::acc233, output_vec_len ); + case 490: return makeRegisterExpression(amdgpu_gfx908::acc234, output_vec_len ); + case 491: return makeRegisterExpression(amdgpu_gfx908::acc235, output_vec_len ); + case 492: return makeRegisterExpression(amdgpu_gfx908::acc236, output_vec_len ); + case 493: return makeRegisterExpression(amdgpu_gfx908::acc237, output_vec_len ); + case 494: return makeRegisterExpression(amdgpu_gfx908::acc238, output_vec_len ); + case 495: return makeRegisterExpression(amdgpu_gfx908::acc239, output_vec_len ); + case 496: return makeRegisterExpression(amdgpu_gfx908::acc240, output_vec_len ); + case 497: return makeRegisterExpression(amdgpu_gfx908::acc241, output_vec_len ); + case 498: return makeRegisterExpression(amdgpu_gfx908::acc242, output_vec_len ); + case 499: return makeRegisterExpression(amdgpu_gfx908::acc243, output_vec_len ); + case 500: return makeRegisterExpression(amdgpu_gfx908::acc244, output_vec_len ); + case 501: return makeRegisterExpression(amdgpu_gfx908::acc245, output_vec_len ); + case 502: return makeRegisterExpression(amdgpu_gfx908::acc246, output_vec_len ); + case 503: return makeRegisterExpression(amdgpu_gfx908::acc247, output_vec_len ); + case 504: return makeRegisterExpression(amdgpu_gfx908::acc248, output_vec_len ); + case 505: return makeRegisterExpression(amdgpu_gfx908::acc249, output_vec_len ); + case 506: return makeRegisterExpression(amdgpu_gfx908::acc250, output_vec_len ); + case 507: return makeRegisterExpression(amdgpu_gfx908::acc251, output_vec_len ); + case 508: return makeRegisterExpression(amdgpu_gfx908::acc252, output_vec_len ); + case 509: return makeRegisterExpression(amdgpu_gfx908::acc253, output_vec_len ); + case 510: return makeRegisterExpression(amdgpu_gfx908::acc254, output_vec_len ); + case 511: return makeRegisterExpression(amdgpu_gfx908::acc255, output_vec_len ); + case 768: return makeRegisterExpression(amdgpu_gfx908::acc0, output_vec_len ); + case 769: return makeRegisterExpression(amdgpu_gfx908::acc1, output_vec_len ); + case 770: return makeRegisterExpression(amdgpu_gfx908::acc2, output_vec_len ); + case 771: return makeRegisterExpression(amdgpu_gfx908::acc3, output_vec_len ); + case 772: return makeRegisterExpression(amdgpu_gfx908::acc4, output_vec_len ); + case 773: return makeRegisterExpression(amdgpu_gfx908::acc5, output_vec_len ); + case 774: return makeRegisterExpression(amdgpu_gfx908::acc6, output_vec_len ); + case 775: return makeRegisterExpression(amdgpu_gfx908::acc7, output_vec_len ); + case 776: return makeRegisterExpression(amdgpu_gfx908::acc8, output_vec_len ); + case 777: return makeRegisterExpression(amdgpu_gfx908::acc9, output_vec_len ); + case 778: return makeRegisterExpression(amdgpu_gfx908::acc10, output_vec_len ); + case 779: return makeRegisterExpression(amdgpu_gfx908::acc11, output_vec_len ); + case 780: return makeRegisterExpression(amdgpu_gfx908::acc12, output_vec_len ); + case 781: return makeRegisterExpression(amdgpu_gfx908::acc13, output_vec_len ); + case 782: return makeRegisterExpression(amdgpu_gfx908::acc14, output_vec_len ); + case 783: return makeRegisterExpression(amdgpu_gfx908::acc15, output_vec_len ); + case 784: return makeRegisterExpression(amdgpu_gfx908::acc16, output_vec_len ); + case 785: return makeRegisterExpression(amdgpu_gfx908::acc17, output_vec_len ); + case 786: return makeRegisterExpression(amdgpu_gfx908::acc18, output_vec_len ); + case 787: return makeRegisterExpression(amdgpu_gfx908::acc19, output_vec_len ); + case 788: return makeRegisterExpression(amdgpu_gfx908::acc20, output_vec_len ); + case 789: return makeRegisterExpression(amdgpu_gfx908::acc21, output_vec_len ); + case 790: return makeRegisterExpression(amdgpu_gfx908::acc22, output_vec_len ); + case 791: return makeRegisterExpression(amdgpu_gfx908::acc23, output_vec_len ); + case 792: return makeRegisterExpression(amdgpu_gfx908::acc24, output_vec_len ); + case 793: return makeRegisterExpression(amdgpu_gfx908::acc25, output_vec_len ); + case 794: return makeRegisterExpression(amdgpu_gfx908::acc26, output_vec_len ); + case 795: return makeRegisterExpression(amdgpu_gfx908::acc27, output_vec_len ); + case 796: return makeRegisterExpression(amdgpu_gfx908::acc28, output_vec_len ); + case 797: return makeRegisterExpression(amdgpu_gfx908::acc29, output_vec_len ); + case 798: return makeRegisterExpression(amdgpu_gfx908::acc30, output_vec_len ); + case 799: return makeRegisterExpression(amdgpu_gfx908::acc31, output_vec_len ); + case 800: return makeRegisterExpression(amdgpu_gfx908::acc32, output_vec_len ); + case 801: return makeRegisterExpression(amdgpu_gfx908::acc33, output_vec_len ); + case 802: return makeRegisterExpression(amdgpu_gfx908::acc34, output_vec_len ); + case 803: return makeRegisterExpression(amdgpu_gfx908::acc35, output_vec_len ); + case 804: return makeRegisterExpression(amdgpu_gfx908::acc36, output_vec_len ); + case 805: return makeRegisterExpression(amdgpu_gfx908::acc37, output_vec_len ); + case 806: return makeRegisterExpression(amdgpu_gfx908::acc38, output_vec_len ); + case 807: return makeRegisterExpression(amdgpu_gfx908::acc39, output_vec_len ); + case 808: return makeRegisterExpression(amdgpu_gfx908::acc40, output_vec_len ); + case 809: return makeRegisterExpression(amdgpu_gfx908::acc41, output_vec_len ); + case 810: return makeRegisterExpression(amdgpu_gfx908::acc42, output_vec_len ); + case 811: return makeRegisterExpression(amdgpu_gfx908::acc43, output_vec_len ); + case 812: return makeRegisterExpression(amdgpu_gfx908::acc44, output_vec_len ); + case 813: return makeRegisterExpression(amdgpu_gfx908::acc45, output_vec_len ); + case 814: return makeRegisterExpression(amdgpu_gfx908::acc46, output_vec_len ); + case 815: return makeRegisterExpression(amdgpu_gfx908::acc47, output_vec_len ); + case 816: return makeRegisterExpression(amdgpu_gfx908::acc48, output_vec_len ); + case 817: return makeRegisterExpression(amdgpu_gfx908::acc49, output_vec_len ); + case 818: return makeRegisterExpression(amdgpu_gfx908::acc50, output_vec_len ); + case 819: return makeRegisterExpression(amdgpu_gfx908::acc51, output_vec_len ); + case 820: return makeRegisterExpression(amdgpu_gfx908::acc52, output_vec_len ); + case 821: return makeRegisterExpression(amdgpu_gfx908::acc53, output_vec_len ); + case 822: return makeRegisterExpression(amdgpu_gfx908::acc54, output_vec_len ); + case 823: return makeRegisterExpression(amdgpu_gfx908::acc55, output_vec_len ); + case 824: return makeRegisterExpression(amdgpu_gfx908::acc56, output_vec_len ); + case 825: return makeRegisterExpression(amdgpu_gfx908::acc57, output_vec_len ); + case 826: return makeRegisterExpression(amdgpu_gfx908::acc58, output_vec_len ); + case 827: return makeRegisterExpression(amdgpu_gfx908::acc59, output_vec_len ); + case 828: return makeRegisterExpression(amdgpu_gfx908::acc60, output_vec_len ); + case 829: return makeRegisterExpression(amdgpu_gfx908::acc61, output_vec_len ); + case 830: return makeRegisterExpression(amdgpu_gfx908::acc62, output_vec_len ); + case 831: return makeRegisterExpression(amdgpu_gfx908::acc63, output_vec_len ); + case 832: return makeRegisterExpression(amdgpu_gfx908::acc64, output_vec_len ); + case 833: return makeRegisterExpression(amdgpu_gfx908::acc65, output_vec_len ); + case 834: return makeRegisterExpression(amdgpu_gfx908::acc66, output_vec_len ); + case 835: return makeRegisterExpression(amdgpu_gfx908::acc67, output_vec_len ); + case 836: return makeRegisterExpression(amdgpu_gfx908::acc68, output_vec_len ); + case 837: return makeRegisterExpression(amdgpu_gfx908::acc69, output_vec_len ); + case 838: return makeRegisterExpression(amdgpu_gfx908::acc70, output_vec_len ); + case 839: return makeRegisterExpression(amdgpu_gfx908::acc71, output_vec_len ); + case 840: return makeRegisterExpression(amdgpu_gfx908::acc72, output_vec_len ); + case 841: return makeRegisterExpression(amdgpu_gfx908::acc73, output_vec_len ); + case 842: return makeRegisterExpression(amdgpu_gfx908::acc74, output_vec_len ); + case 843: return makeRegisterExpression(amdgpu_gfx908::acc75, output_vec_len ); + case 844: return makeRegisterExpression(amdgpu_gfx908::acc76, output_vec_len ); + case 845: return makeRegisterExpression(amdgpu_gfx908::acc77, output_vec_len ); + case 846: return makeRegisterExpression(amdgpu_gfx908::acc78, output_vec_len ); + case 847: return makeRegisterExpression(amdgpu_gfx908::acc79, output_vec_len ); + case 848: return makeRegisterExpression(amdgpu_gfx908::acc80, output_vec_len ); + case 849: return makeRegisterExpression(amdgpu_gfx908::acc81, output_vec_len ); + case 850: return makeRegisterExpression(amdgpu_gfx908::acc82, output_vec_len ); + case 851: return makeRegisterExpression(amdgpu_gfx908::acc83, output_vec_len ); + case 852: return makeRegisterExpression(amdgpu_gfx908::acc84, output_vec_len ); + case 853: return makeRegisterExpression(amdgpu_gfx908::acc85, output_vec_len ); + case 854: return makeRegisterExpression(amdgpu_gfx908::acc86, output_vec_len ); + case 855: return makeRegisterExpression(amdgpu_gfx908::acc87, output_vec_len ); + case 856: return makeRegisterExpression(amdgpu_gfx908::acc88, output_vec_len ); + case 857: return makeRegisterExpression(amdgpu_gfx908::acc89, output_vec_len ); + case 858: return makeRegisterExpression(amdgpu_gfx908::acc90, output_vec_len ); + case 859: return makeRegisterExpression(amdgpu_gfx908::acc91, output_vec_len ); + case 860: return makeRegisterExpression(amdgpu_gfx908::acc92, output_vec_len ); + case 861: return makeRegisterExpression(amdgpu_gfx908::acc93, output_vec_len ); + case 862: return makeRegisterExpression(amdgpu_gfx908::acc94, output_vec_len ); + case 863: return makeRegisterExpression(amdgpu_gfx908::acc95, output_vec_len ); + case 864: return makeRegisterExpression(amdgpu_gfx908::acc96, output_vec_len ); + case 865: return makeRegisterExpression(amdgpu_gfx908::acc97, output_vec_len ); + case 866: return makeRegisterExpression(amdgpu_gfx908::acc98, output_vec_len ); + case 867: return makeRegisterExpression(amdgpu_gfx908::acc99, output_vec_len ); + case 868: return makeRegisterExpression(amdgpu_gfx908::acc100, output_vec_len ); + case 869: return makeRegisterExpression(amdgpu_gfx908::acc101, output_vec_len ); + case 870: return makeRegisterExpression(amdgpu_gfx908::acc102, output_vec_len ); + case 871: return makeRegisterExpression(amdgpu_gfx908::acc103, output_vec_len ); + case 872: return makeRegisterExpression(amdgpu_gfx908::acc104, output_vec_len ); + case 873: return makeRegisterExpression(amdgpu_gfx908::acc105, output_vec_len ); + case 874: return makeRegisterExpression(amdgpu_gfx908::acc106, output_vec_len ); + case 875: return makeRegisterExpression(amdgpu_gfx908::acc107, output_vec_len ); + case 876: return makeRegisterExpression(amdgpu_gfx908::acc108, output_vec_len ); + case 877: return makeRegisterExpression(amdgpu_gfx908::acc109, output_vec_len ); + case 878: return makeRegisterExpression(amdgpu_gfx908::acc110, output_vec_len ); + case 879: return makeRegisterExpression(amdgpu_gfx908::acc111, output_vec_len ); + case 880: return makeRegisterExpression(amdgpu_gfx908::acc112, output_vec_len ); + case 881: return makeRegisterExpression(amdgpu_gfx908::acc113, output_vec_len ); + case 882: return makeRegisterExpression(amdgpu_gfx908::acc114, output_vec_len ); + case 883: return makeRegisterExpression(amdgpu_gfx908::acc115, output_vec_len ); + case 884: return makeRegisterExpression(amdgpu_gfx908::acc116, output_vec_len ); + case 885: return makeRegisterExpression(amdgpu_gfx908::acc117, output_vec_len ); + case 886: return makeRegisterExpression(amdgpu_gfx908::acc118, output_vec_len ); + case 887: return makeRegisterExpression(amdgpu_gfx908::acc119, output_vec_len ); + case 888: return makeRegisterExpression(amdgpu_gfx908::acc120, output_vec_len ); + case 889: return makeRegisterExpression(amdgpu_gfx908::acc121, output_vec_len ); + case 890: return makeRegisterExpression(amdgpu_gfx908::acc122, output_vec_len ); + case 891: return makeRegisterExpression(amdgpu_gfx908::acc123, output_vec_len ); + case 892: return makeRegisterExpression(amdgpu_gfx908::acc124, output_vec_len ); + case 893: return makeRegisterExpression(amdgpu_gfx908::acc125, output_vec_len ); + case 894: return makeRegisterExpression(amdgpu_gfx908::acc126, output_vec_len ); + case 895: return makeRegisterExpression(amdgpu_gfx908::acc127, output_vec_len ); + case 896: return makeRegisterExpression(amdgpu_gfx908::acc128, output_vec_len ); + case 897: return makeRegisterExpression(amdgpu_gfx908::acc129, output_vec_len ); + case 898: return makeRegisterExpression(amdgpu_gfx908::acc130, output_vec_len ); + case 899: return makeRegisterExpression(amdgpu_gfx908::acc131, output_vec_len ); + case 900: return makeRegisterExpression(amdgpu_gfx908::acc132, output_vec_len ); + case 901: return makeRegisterExpression(amdgpu_gfx908::acc133, output_vec_len ); + case 902: return makeRegisterExpression(amdgpu_gfx908::acc134, output_vec_len ); + case 903: return makeRegisterExpression(amdgpu_gfx908::acc135, output_vec_len ); + case 904: return makeRegisterExpression(amdgpu_gfx908::acc136, output_vec_len ); + case 905: return makeRegisterExpression(amdgpu_gfx908::acc137, output_vec_len ); + case 906: return makeRegisterExpression(amdgpu_gfx908::acc138, output_vec_len ); + case 907: return makeRegisterExpression(amdgpu_gfx908::acc139, output_vec_len ); + case 908: return makeRegisterExpression(amdgpu_gfx908::acc140, output_vec_len ); + case 909: return makeRegisterExpression(amdgpu_gfx908::acc141, output_vec_len ); + case 910: return makeRegisterExpression(amdgpu_gfx908::acc142, output_vec_len ); + case 911: return makeRegisterExpression(amdgpu_gfx908::acc143, output_vec_len ); + case 912: return makeRegisterExpression(amdgpu_gfx908::acc144, output_vec_len ); + case 913: return makeRegisterExpression(amdgpu_gfx908::acc145, output_vec_len ); + case 914: return makeRegisterExpression(amdgpu_gfx908::acc146, output_vec_len ); + case 915: return makeRegisterExpression(amdgpu_gfx908::acc147, output_vec_len ); + case 916: return makeRegisterExpression(amdgpu_gfx908::acc148, output_vec_len ); + case 917: return makeRegisterExpression(amdgpu_gfx908::acc149, output_vec_len ); + case 918: return makeRegisterExpression(amdgpu_gfx908::acc150, output_vec_len ); + case 919: return makeRegisterExpression(amdgpu_gfx908::acc151, output_vec_len ); + case 920: return makeRegisterExpression(amdgpu_gfx908::acc152, output_vec_len ); + case 921: return makeRegisterExpression(amdgpu_gfx908::acc153, output_vec_len ); + case 922: return makeRegisterExpression(amdgpu_gfx908::acc154, output_vec_len ); + case 923: return makeRegisterExpression(amdgpu_gfx908::acc155, output_vec_len ); + case 924: return makeRegisterExpression(amdgpu_gfx908::acc156, output_vec_len ); + case 925: return makeRegisterExpression(amdgpu_gfx908::acc157, output_vec_len ); + case 926: return makeRegisterExpression(amdgpu_gfx908::acc158, output_vec_len ); + case 927: return makeRegisterExpression(amdgpu_gfx908::acc159, output_vec_len ); + case 928: return makeRegisterExpression(amdgpu_gfx908::acc160, output_vec_len ); + case 929: return makeRegisterExpression(amdgpu_gfx908::acc161, output_vec_len ); + case 930: return makeRegisterExpression(amdgpu_gfx908::acc162, output_vec_len ); + case 931: return makeRegisterExpression(amdgpu_gfx908::acc163, output_vec_len ); + case 932: return makeRegisterExpression(amdgpu_gfx908::acc164, output_vec_len ); + case 933: return makeRegisterExpression(amdgpu_gfx908::acc165, output_vec_len ); + case 934: return makeRegisterExpression(amdgpu_gfx908::acc166, output_vec_len ); + case 935: return makeRegisterExpression(amdgpu_gfx908::acc167, output_vec_len ); + case 936: return makeRegisterExpression(amdgpu_gfx908::acc168, output_vec_len ); + case 937: return makeRegisterExpression(amdgpu_gfx908::acc169, output_vec_len ); + case 938: return makeRegisterExpression(amdgpu_gfx908::acc170, output_vec_len ); + case 939: return makeRegisterExpression(amdgpu_gfx908::acc171, output_vec_len ); + case 940: return makeRegisterExpression(amdgpu_gfx908::acc172, output_vec_len ); + case 941: return makeRegisterExpression(amdgpu_gfx908::acc173, output_vec_len ); + case 942: return makeRegisterExpression(amdgpu_gfx908::acc174, output_vec_len ); + case 943: return makeRegisterExpression(amdgpu_gfx908::acc175, output_vec_len ); + case 944: return makeRegisterExpression(amdgpu_gfx908::acc176, output_vec_len ); + case 945: return makeRegisterExpression(amdgpu_gfx908::acc177, output_vec_len ); + case 946: return makeRegisterExpression(amdgpu_gfx908::acc178, output_vec_len ); + case 947: return makeRegisterExpression(amdgpu_gfx908::acc179, output_vec_len ); + case 948: return makeRegisterExpression(amdgpu_gfx908::acc180, output_vec_len ); + case 949: return makeRegisterExpression(amdgpu_gfx908::acc181, output_vec_len ); + case 950: return makeRegisterExpression(amdgpu_gfx908::acc182, output_vec_len ); + case 951: return makeRegisterExpression(amdgpu_gfx908::acc183, output_vec_len ); + case 952: return makeRegisterExpression(amdgpu_gfx908::acc184, output_vec_len ); + case 953: return makeRegisterExpression(amdgpu_gfx908::acc185, output_vec_len ); + case 954: return makeRegisterExpression(amdgpu_gfx908::acc186, output_vec_len ); + case 955: return makeRegisterExpression(amdgpu_gfx908::acc187, output_vec_len ); + case 956: return makeRegisterExpression(amdgpu_gfx908::acc188, output_vec_len ); + case 957: return makeRegisterExpression(amdgpu_gfx908::acc189, output_vec_len ); + case 958: return makeRegisterExpression(amdgpu_gfx908::acc190, output_vec_len ); + case 959: return makeRegisterExpression(amdgpu_gfx908::acc191, output_vec_len ); + case 960: return makeRegisterExpression(amdgpu_gfx908::acc192, output_vec_len ); + case 961: return makeRegisterExpression(amdgpu_gfx908::acc193, output_vec_len ); + case 962: return makeRegisterExpression(amdgpu_gfx908::acc194, output_vec_len ); + case 963: return makeRegisterExpression(amdgpu_gfx908::acc195, output_vec_len ); + case 964: return makeRegisterExpression(amdgpu_gfx908::acc196, output_vec_len ); + case 965: return makeRegisterExpression(amdgpu_gfx908::acc197, output_vec_len ); + case 966: return makeRegisterExpression(amdgpu_gfx908::acc198, output_vec_len ); + case 967: return makeRegisterExpression(amdgpu_gfx908::acc199, output_vec_len ); + case 968: return makeRegisterExpression(amdgpu_gfx908::acc200, output_vec_len ); + case 969: return makeRegisterExpression(amdgpu_gfx908::acc201, output_vec_len ); + case 970: return makeRegisterExpression(amdgpu_gfx908::acc202, output_vec_len ); + case 971: return makeRegisterExpression(amdgpu_gfx908::acc203, output_vec_len ); + case 972: return makeRegisterExpression(amdgpu_gfx908::acc204, output_vec_len ); + case 973: return makeRegisterExpression(amdgpu_gfx908::acc205, output_vec_len ); + case 974: return makeRegisterExpression(amdgpu_gfx908::acc206, output_vec_len ); + case 975: return makeRegisterExpression(amdgpu_gfx908::acc207, output_vec_len ); + case 976: return makeRegisterExpression(amdgpu_gfx908::acc208, output_vec_len ); + case 977: return makeRegisterExpression(amdgpu_gfx908::acc209, output_vec_len ); + case 978: return makeRegisterExpression(amdgpu_gfx908::acc210, output_vec_len ); + case 979: return makeRegisterExpression(amdgpu_gfx908::acc211, output_vec_len ); + case 980: return makeRegisterExpression(amdgpu_gfx908::acc212, output_vec_len ); + case 981: return makeRegisterExpression(amdgpu_gfx908::acc213, output_vec_len ); + case 982: return makeRegisterExpression(amdgpu_gfx908::acc214, output_vec_len ); + case 983: return makeRegisterExpression(amdgpu_gfx908::acc215, output_vec_len ); + case 984: return makeRegisterExpression(amdgpu_gfx908::acc216, output_vec_len ); + case 985: return makeRegisterExpression(amdgpu_gfx908::acc217, output_vec_len ); + case 986: return makeRegisterExpression(amdgpu_gfx908::acc218, output_vec_len ); + case 987: return makeRegisterExpression(amdgpu_gfx908::acc219, output_vec_len ); + case 988: return makeRegisterExpression(amdgpu_gfx908::acc220, output_vec_len ); + case 989: return makeRegisterExpression(amdgpu_gfx908::acc221, output_vec_len ); + case 990: return makeRegisterExpression(amdgpu_gfx908::acc222, output_vec_len ); + case 991: return makeRegisterExpression(amdgpu_gfx908::acc223, output_vec_len ); + case 992: return makeRegisterExpression(amdgpu_gfx908::acc224, output_vec_len ); + case 993: return makeRegisterExpression(amdgpu_gfx908::acc225, output_vec_len ); + case 994: return makeRegisterExpression(amdgpu_gfx908::acc226, output_vec_len ); + case 995: return makeRegisterExpression(amdgpu_gfx908::acc227, output_vec_len ); + case 996: return makeRegisterExpression(amdgpu_gfx908::acc228, output_vec_len ); + case 997: return makeRegisterExpression(amdgpu_gfx908::acc229, output_vec_len ); + case 998: return makeRegisterExpression(amdgpu_gfx908::acc230, output_vec_len ); + case 999: return makeRegisterExpression(amdgpu_gfx908::acc231, output_vec_len ); + case 1000: return makeRegisterExpression(amdgpu_gfx908::acc232, output_vec_len ); + case 1001: return makeRegisterExpression(amdgpu_gfx908::acc233, output_vec_len ); + case 1002: return makeRegisterExpression(amdgpu_gfx908::acc234, output_vec_len ); + case 1003: return makeRegisterExpression(amdgpu_gfx908::acc235, output_vec_len ); + case 1004: return makeRegisterExpression(amdgpu_gfx908::acc236, output_vec_len ); + case 1005: return makeRegisterExpression(amdgpu_gfx908::acc237, output_vec_len ); + case 1006: return makeRegisterExpression(amdgpu_gfx908::acc238, output_vec_len ); + case 1007: return makeRegisterExpression(amdgpu_gfx908::acc239, output_vec_len ); + case 1008: return makeRegisterExpression(amdgpu_gfx908::acc240, output_vec_len ); + case 1009: return makeRegisterExpression(amdgpu_gfx908::acc241, output_vec_len ); + case 1010: return makeRegisterExpression(amdgpu_gfx908::acc242, output_vec_len ); + case 1011: return makeRegisterExpression(amdgpu_gfx908::acc243, output_vec_len ); + case 1012: return makeRegisterExpression(amdgpu_gfx908::acc244, output_vec_len ); + case 1013: return makeRegisterExpression(amdgpu_gfx908::acc245, output_vec_len ); + case 1014: return makeRegisterExpression(amdgpu_gfx908::acc246, output_vec_len ); + case 1015: return makeRegisterExpression(amdgpu_gfx908::acc247, output_vec_len ); + case 1016: return makeRegisterExpression(amdgpu_gfx908::acc248, output_vec_len ); + case 1017: return makeRegisterExpression(amdgpu_gfx908::acc249, output_vec_len ); + case 1018: return makeRegisterExpression(amdgpu_gfx908::acc250, output_vec_len ); + case 1019: return makeRegisterExpression(amdgpu_gfx908::acc251, output_vec_len ); + case 1020: return makeRegisterExpression(amdgpu_gfx908::acc252, output_vec_len ); + case 1021: return makeRegisterExpression(amdgpu_gfx908::acc253, output_vec_len ); + case 1022: return makeRegisterExpression(amdgpu_gfx908::acc254, output_vec_len ); + case 1023: return makeRegisterExpression(amdgpu_gfx908::acc255, output_vec_len ); + default: return makeRegisterExpression(amdgpu_gfx908::invalid); + } + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SRC_ACCVGPR_OR_CONST(uint64_t input, uint32_t output_vec_len) + { + switch (input) { + case 256: return makeRegisterExpression(amdgpu_gfx908::acc0, output_vec_len ); + case 257: return makeRegisterExpression(amdgpu_gfx908::acc1, output_vec_len ); + case 258: return makeRegisterExpression(amdgpu_gfx908::acc2, output_vec_len ); + case 259: return makeRegisterExpression(amdgpu_gfx908::acc3, output_vec_len ); + case 260: return makeRegisterExpression(amdgpu_gfx908::acc4, output_vec_len ); + case 261: return makeRegisterExpression(amdgpu_gfx908::acc5, output_vec_len ); + case 262: return makeRegisterExpression(amdgpu_gfx908::acc6, output_vec_len ); + case 263: return makeRegisterExpression(amdgpu_gfx908::acc7, output_vec_len ); + case 264: return makeRegisterExpression(amdgpu_gfx908::acc8, output_vec_len ); + case 265: return makeRegisterExpression(amdgpu_gfx908::acc9, output_vec_len ); + case 266: return makeRegisterExpression(amdgpu_gfx908::acc10, output_vec_len ); + case 267: return makeRegisterExpression(amdgpu_gfx908::acc11, output_vec_len ); + case 268: return makeRegisterExpression(amdgpu_gfx908::acc12, output_vec_len ); + case 269: return makeRegisterExpression(amdgpu_gfx908::acc13, output_vec_len ); + case 270: return makeRegisterExpression(amdgpu_gfx908::acc14, output_vec_len ); + case 271: return makeRegisterExpression(amdgpu_gfx908::acc15, output_vec_len ); + case 272: return makeRegisterExpression(amdgpu_gfx908::acc16, output_vec_len ); + case 273: return makeRegisterExpression(amdgpu_gfx908::acc17, output_vec_len ); + case 274: return makeRegisterExpression(amdgpu_gfx908::acc18, output_vec_len ); + case 275: return makeRegisterExpression(amdgpu_gfx908::acc19, output_vec_len ); + case 276: return makeRegisterExpression(amdgpu_gfx908::acc20, output_vec_len ); + case 277: return makeRegisterExpression(amdgpu_gfx908::acc21, output_vec_len ); + case 278: return makeRegisterExpression(amdgpu_gfx908::acc22, output_vec_len ); + case 279: return makeRegisterExpression(amdgpu_gfx908::acc23, output_vec_len ); + case 280: return makeRegisterExpression(amdgpu_gfx908::acc24, output_vec_len ); + case 281: return makeRegisterExpression(amdgpu_gfx908::acc25, output_vec_len ); + case 282: return makeRegisterExpression(amdgpu_gfx908::acc26, output_vec_len ); + case 283: return makeRegisterExpression(amdgpu_gfx908::acc27, output_vec_len ); + case 284: return makeRegisterExpression(amdgpu_gfx908::acc28, output_vec_len ); + case 285: return makeRegisterExpression(amdgpu_gfx908::acc29, output_vec_len ); + case 286: return makeRegisterExpression(amdgpu_gfx908::acc30, output_vec_len ); + case 287: return makeRegisterExpression(amdgpu_gfx908::acc31, output_vec_len ); + case 288: return makeRegisterExpression(amdgpu_gfx908::acc32, output_vec_len ); + case 289: return makeRegisterExpression(amdgpu_gfx908::acc33, output_vec_len ); + case 290: return makeRegisterExpression(amdgpu_gfx908::acc34, output_vec_len ); + case 291: return makeRegisterExpression(amdgpu_gfx908::acc35, output_vec_len ); + case 292: return makeRegisterExpression(amdgpu_gfx908::acc36, output_vec_len ); + case 293: return makeRegisterExpression(amdgpu_gfx908::acc37, output_vec_len ); + case 294: return makeRegisterExpression(amdgpu_gfx908::acc38, output_vec_len ); + case 295: return makeRegisterExpression(amdgpu_gfx908::acc39, output_vec_len ); + case 296: return makeRegisterExpression(amdgpu_gfx908::acc40, output_vec_len ); + case 297: return makeRegisterExpression(amdgpu_gfx908::acc41, output_vec_len ); + case 298: return makeRegisterExpression(amdgpu_gfx908::acc42, output_vec_len ); + case 299: return makeRegisterExpression(amdgpu_gfx908::acc43, output_vec_len ); + case 300: return makeRegisterExpression(amdgpu_gfx908::acc44, output_vec_len ); + case 301: return makeRegisterExpression(amdgpu_gfx908::acc45, output_vec_len ); + case 302: return makeRegisterExpression(amdgpu_gfx908::acc46, output_vec_len ); + case 303: return makeRegisterExpression(amdgpu_gfx908::acc47, output_vec_len ); + case 304: return makeRegisterExpression(amdgpu_gfx908::acc48, output_vec_len ); + case 305: return makeRegisterExpression(amdgpu_gfx908::acc49, output_vec_len ); + case 306: return makeRegisterExpression(amdgpu_gfx908::acc50, output_vec_len ); + case 307: return makeRegisterExpression(amdgpu_gfx908::acc51, output_vec_len ); + case 308: return makeRegisterExpression(amdgpu_gfx908::acc52, output_vec_len ); + case 309: return makeRegisterExpression(amdgpu_gfx908::acc53, output_vec_len ); + case 310: return makeRegisterExpression(amdgpu_gfx908::acc54, output_vec_len ); + case 311: return makeRegisterExpression(amdgpu_gfx908::acc55, output_vec_len ); + case 312: return makeRegisterExpression(amdgpu_gfx908::acc56, output_vec_len ); + case 313: return makeRegisterExpression(amdgpu_gfx908::acc57, output_vec_len ); + case 314: return makeRegisterExpression(amdgpu_gfx908::acc58, output_vec_len ); + case 315: return makeRegisterExpression(amdgpu_gfx908::acc59, output_vec_len ); + case 316: return makeRegisterExpression(amdgpu_gfx908::acc60, output_vec_len ); + case 317: return makeRegisterExpression(amdgpu_gfx908::acc61, output_vec_len ); + case 318: return makeRegisterExpression(amdgpu_gfx908::acc62, output_vec_len ); + case 319: return makeRegisterExpression(amdgpu_gfx908::acc63, output_vec_len ); + case 320: return makeRegisterExpression(amdgpu_gfx908::acc64, output_vec_len ); + case 321: return makeRegisterExpression(amdgpu_gfx908::acc65, output_vec_len ); + case 322: return makeRegisterExpression(amdgpu_gfx908::acc66, output_vec_len ); + case 323: return makeRegisterExpression(amdgpu_gfx908::acc67, output_vec_len ); + case 324: return makeRegisterExpression(amdgpu_gfx908::acc68, output_vec_len ); + case 325: return makeRegisterExpression(amdgpu_gfx908::acc69, output_vec_len ); + case 326: return makeRegisterExpression(amdgpu_gfx908::acc70, output_vec_len ); + case 327: return makeRegisterExpression(amdgpu_gfx908::acc71, output_vec_len ); + case 328: return makeRegisterExpression(amdgpu_gfx908::acc72, output_vec_len ); + case 329: return makeRegisterExpression(amdgpu_gfx908::acc73, output_vec_len ); + case 330: return makeRegisterExpression(amdgpu_gfx908::acc74, output_vec_len ); + case 331: return makeRegisterExpression(amdgpu_gfx908::acc75, output_vec_len ); + case 332: return makeRegisterExpression(amdgpu_gfx908::acc76, output_vec_len ); + case 333: return makeRegisterExpression(amdgpu_gfx908::acc77, output_vec_len ); + case 334: return makeRegisterExpression(amdgpu_gfx908::acc78, output_vec_len ); + case 335: return makeRegisterExpression(amdgpu_gfx908::acc79, output_vec_len ); + case 336: return makeRegisterExpression(amdgpu_gfx908::acc80, output_vec_len ); + case 337: return makeRegisterExpression(amdgpu_gfx908::acc81, output_vec_len ); + case 338: return makeRegisterExpression(amdgpu_gfx908::acc82, output_vec_len ); + case 339: return makeRegisterExpression(amdgpu_gfx908::acc83, output_vec_len ); + case 340: return makeRegisterExpression(amdgpu_gfx908::acc84, output_vec_len ); + case 341: return makeRegisterExpression(amdgpu_gfx908::acc85, output_vec_len ); + case 342: return makeRegisterExpression(amdgpu_gfx908::acc86, output_vec_len ); + case 343: return makeRegisterExpression(amdgpu_gfx908::acc87, output_vec_len ); + case 344: return makeRegisterExpression(amdgpu_gfx908::acc88, output_vec_len ); + case 345: return makeRegisterExpression(amdgpu_gfx908::acc89, output_vec_len ); + case 346: return makeRegisterExpression(amdgpu_gfx908::acc90, output_vec_len ); + case 347: return makeRegisterExpression(amdgpu_gfx908::acc91, output_vec_len ); + case 348: return makeRegisterExpression(amdgpu_gfx908::acc92, output_vec_len ); + case 349: return makeRegisterExpression(amdgpu_gfx908::acc93, output_vec_len ); + case 350: return makeRegisterExpression(amdgpu_gfx908::acc94, output_vec_len ); + case 351: return makeRegisterExpression(amdgpu_gfx908::acc95, output_vec_len ); + case 352: return makeRegisterExpression(amdgpu_gfx908::acc96, output_vec_len ); + case 353: return makeRegisterExpression(amdgpu_gfx908::acc97, output_vec_len ); + case 354: return makeRegisterExpression(amdgpu_gfx908::acc98, output_vec_len ); + case 355: return makeRegisterExpression(amdgpu_gfx908::acc99, output_vec_len ); + case 356: return makeRegisterExpression(amdgpu_gfx908::acc100, output_vec_len ); + case 357: return makeRegisterExpression(amdgpu_gfx908::acc101, output_vec_len ); + case 358: return makeRegisterExpression(amdgpu_gfx908::acc102, output_vec_len ); + case 359: return makeRegisterExpression(amdgpu_gfx908::acc103, output_vec_len ); + case 360: return makeRegisterExpression(amdgpu_gfx908::acc104, output_vec_len ); + case 361: return makeRegisterExpression(amdgpu_gfx908::acc105, output_vec_len ); + case 362: return makeRegisterExpression(amdgpu_gfx908::acc106, output_vec_len ); + case 363: return makeRegisterExpression(amdgpu_gfx908::acc107, output_vec_len ); + case 364: return makeRegisterExpression(amdgpu_gfx908::acc108, output_vec_len ); + case 365: return makeRegisterExpression(amdgpu_gfx908::acc109, output_vec_len ); + case 366: return makeRegisterExpression(amdgpu_gfx908::acc110, output_vec_len ); + case 367: return makeRegisterExpression(amdgpu_gfx908::acc111, output_vec_len ); + case 368: return makeRegisterExpression(amdgpu_gfx908::acc112, output_vec_len ); + case 369: return makeRegisterExpression(amdgpu_gfx908::acc113, output_vec_len ); + case 370: return makeRegisterExpression(amdgpu_gfx908::acc114, output_vec_len ); + case 371: return makeRegisterExpression(amdgpu_gfx908::acc115, output_vec_len ); + case 372: return makeRegisterExpression(amdgpu_gfx908::acc116, output_vec_len ); + case 373: return makeRegisterExpression(amdgpu_gfx908::acc117, output_vec_len ); + case 374: return makeRegisterExpression(amdgpu_gfx908::acc118, output_vec_len ); + case 375: return makeRegisterExpression(amdgpu_gfx908::acc119, output_vec_len ); + case 376: return makeRegisterExpression(amdgpu_gfx908::acc120, output_vec_len ); + case 377: return makeRegisterExpression(amdgpu_gfx908::acc121, output_vec_len ); + case 378: return makeRegisterExpression(amdgpu_gfx908::acc122, output_vec_len ); + case 379: return makeRegisterExpression(amdgpu_gfx908::acc123, output_vec_len ); + case 380: return makeRegisterExpression(amdgpu_gfx908::acc124, output_vec_len ); + case 381: return makeRegisterExpression(amdgpu_gfx908::acc125, output_vec_len ); + case 382: return makeRegisterExpression(amdgpu_gfx908::acc126, output_vec_len ); + case 383: return makeRegisterExpression(amdgpu_gfx908::acc127, output_vec_len ); + case 384: return makeRegisterExpression(amdgpu_gfx908::acc128, output_vec_len ); + case 385: return makeRegisterExpression(amdgpu_gfx908::acc129, output_vec_len ); + case 386: return makeRegisterExpression(amdgpu_gfx908::acc130, output_vec_len ); + case 387: return makeRegisterExpression(amdgpu_gfx908::acc131, output_vec_len ); + case 388: return makeRegisterExpression(amdgpu_gfx908::acc132, output_vec_len ); + case 389: return makeRegisterExpression(amdgpu_gfx908::acc133, output_vec_len ); + case 390: return makeRegisterExpression(amdgpu_gfx908::acc134, output_vec_len ); + case 391: return makeRegisterExpression(amdgpu_gfx908::acc135, output_vec_len ); + case 392: return makeRegisterExpression(amdgpu_gfx908::acc136, output_vec_len ); + case 393: return makeRegisterExpression(amdgpu_gfx908::acc137, output_vec_len ); + case 394: return makeRegisterExpression(amdgpu_gfx908::acc138, output_vec_len ); + case 395: return makeRegisterExpression(amdgpu_gfx908::acc139, output_vec_len ); + case 396: return makeRegisterExpression(amdgpu_gfx908::acc140, output_vec_len ); + case 397: return makeRegisterExpression(amdgpu_gfx908::acc141, output_vec_len ); + case 398: return makeRegisterExpression(amdgpu_gfx908::acc142, output_vec_len ); + case 399: return makeRegisterExpression(amdgpu_gfx908::acc143, output_vec_len ); + case 400: return makeRegisterExpression(amdgpu_gfx908::acc144, output_vec_len ); + case 401: return makeRegisterExpression(amdgpu_gfx908::acc145, output_vec_len ); + case 402: return makeRegisterExpression(amdgpu_gfx908::acc146, output_vec_len ); + case 403: return makeRegisterExpression(amdgpu_gfx908::acc147, output_vec_len ); + case 404: return makeRegisterExpression(amdgpu_gfx908::acc148, output_vec_len ); + case 405: return makeRegisterExpression(amdgpu_gfx908::acc149, output_vec_len ); + case 406: return makeRegisterExpression(amdgpu_gfx908::acc150, output_vec_len ); + case 407: return makeRegisterExpression(amdgpu_gfx908::acc151, output_vec_len ); + case 408: return makeRegisterExpression(amdgpu_gfx908::acc152, output_vec_len ); + case 409: return makeRegisterExpression(amdgpu_gfx908::acc153, output_vec_len ); + case 410: return makeRegisterExpression(amdgpu_gfx908::acc154, output_vec_len ); + case 411: return makeRegisterExpression(amdgpu_gfx908::acc155, output_vec_len ); + case 412: return makeRegisterExpression(amdgpu_gfx908::acc156, output_vec_len ); + case 413: return makeRegisterExpression(amdgpu_gfx908::acc157, output_vec_len ); + case 414: return makeRegisterExpression(amdgpu_gfx908::acc158, output_vec_len ); + case 415: return makeRegisterExpression(amdgpu_gfx908::acc159, output_vec_len ); + case 416: return makeRegisterExpression(amdgpu_gfx908::acc160, output_vec_len ); + case 417: return makeRegisterExpression(amdgpu_gfx908::acc161, output_vec_len ); + case 418: return makeRegisterExpression(amdgpu_gfx908::acc162, output_vec_len ); + case 419: return makeRegisterExpression(amdgpu_gfx908::acc163, output_vec_len ); + case 420: return makeRegisterExpression(amdgpu_gfx908::acc164, output_vec_len ); + case 421: return makeRegisterExpression(amdgpu_gfx908::acc165, output_vec_len ); + case 422: return makeRegisterExpression(amdgpu_gfx908::acc166, output_vec_len ); + case 423: return makeRegisterExpression(amdgpu_gfx908::acc167, output_vec_len ); + case 424: return makeRegisterExpression(amdgpu_gfx908::acc168, output_vec_len ); + case 425: return makeRegisterExpression(amdgpu_gfx908::acc169, output_vec_len ); + case 426: return makeRegisterExpression(amdgpu_gfx908::acc170, output_vec_len ); + case 427: return makeRegisterExpression(amdgpu_gfx908::acc171, output_vec_len ); + case 428: return makeRegisterExpression(amdgpu_gfx908::acc172, output_vec_len ); + case 429: return makeRegisterExpression(amdgpu_gfx908::acc173, output_vec_len ); + case 430: return makeRegisterExpression(amdgpu_gfx908::acc174, output_vec_len ); + case 431: return makeRegisterExpression(amdgpu_gfx908::acc175, output_vec_len ); + case 432: return makeRegisterExpression(amdgpu_gfx908::acc176, output_vec_len ); + case 433: return makeRegisterExpression(amdgpu_gfx908::acc177, output_vec_len ); + case 434: return makeRegisterExpression(amdgpu_gfx908::acc178, output_vec_len ); + case 435: return makeRegisterExpression(amdgpu_gfx908::acc179, output_vec_len ); + case 436: return makeRegisterExpression(amdgpu_gfx908::acc180, output_vec_len ); + case 437: return makeRegisterExpression(amdgpu_gfx908::acc181, output_vec_len ); + case 438: return makeRegisterExpression(amdgpu_gfx908::acc182, output_vec_len ); + case 439: return makeRegisterExpression(amdgpu_gfx908::acc183, output_vec_len ); + case 440: return makeRegisterExpression(amdgpu_gfx908::acc184, output_vec_len ); + case 441: return makeRegisterExpression(amdgpu_gfx908::acc185, output_vec_len ); + case 442: return makeRegisterExpression(amdgpu_gfx908::acc186, output_vec_len ); + case 443: return makeRegisterExpression(amdgpu_gfx908::acc187, output_vec_len ); + case 444: return makeRegisterExpression(amdgpu_gfx908::acc188, output_vec_len ); + case 445: return makeRegisterExpression(amdgpu_gfx908::acc189, output_vec_len ); + case 446: return makeRegisterExpression(amdgpu_gfx908::acc190, output_vec_len ); + case 447: return makeRegisterExpression(amdgpu_gfx908::acc191, output_vec_len ); + case 448: return makeRegisterExpression(amdgpu_gfx908::acc192, output_vec_len ); + case 449: return makeRegisterExpression(amdgpu_gfx908::acc193, output_vec_len ); + case 450: return makeRegisterExpression(amdgpu_gfx908::acc194, output_vec_len ); + case 451: return makeRegisterExpression(amdgpu_gfx908::acc195, output_vec_len ); + case 452: return makeRegisterExpression(amdgpu_gfx908::acc196, output_vec_len ); + case 453: return makeRegisterExpression(amdgpu_gfx908::acc197, output_vec_len ); + case 454: return makeRegisterExpression(amdgpu_gfx908::acc198, output_vec_len ); + case 455: return makeRegisterExpression(amdgpu_gfx908::acc199, output_vec_len ); + case 456: return makeRegisterExpression(amdgpu_gfx908::acc200, output_vec_len ); + case 457: return makeRegisterExpression(amdgpu_gfx908::acc201, output_vec_len ); + case 458: return makeRegisterExpression(amdgpu_gfx908::acc202, output_vec_len ); + case 459: return makeRegisterExpression(amdgpu_gfx908::acc203, output_vec_len ); + case 460: return makeRegisterExpression(amdgpu_gfx908::acc204, output_vec_len ); + case 461: return makeRegisterExpression(amdgpu_gfx908::acc205, output_vec_len ); + case 462: return makeRegisterExpression(amdgpu_gfx908::acc206, output_vec_len ); + case 463: return makeRegisterExpression(amdgpu_gfx908::acc207, output_vec_len ); + case 464: return makeRegisterExpression(amdgpu_gfx908::acc208, output_vec_len ); + case 465: return makeRegisterExpression(amdgpu_gfx908::acc209, output_vec_len ); + case 466: return makeRegisterExpression(amdgpu_gfx908::acc210, output_vec_len ); + case 467: return makeRegisterExpression(amdgpu_gfx908::acc211, output_vec_len ); + case 468: return makeRegisterExpression(amdgpu_gfx908::acc212, output_vec_len ); + case 469: return makeRegisterExpression(amdgpu_gfx908::acc213, output_vec_len ); + case 470: return makeRegisterExpression(amdgpu_gfx908::acc214, output_vec_len ); + case 471: return makeRegisterExpression(amdgpu_gfx908::acc215, output_vec_len ); + case 472: return makeRegisterExpression(amdgpu_gfx908::acc216, output_vec_len ); + case 473: return makeRegisterExpression(amdgpu_gfx908::acc217, output_vec_len ); + case 474: return makeRegisterExpression(amdgpu_gfx908::acc218, output_vec_len ); + case 475: return makeRegisterExpression(amdgpu_gfx908::acc219, output_vec_len ); + case 476: return makeRegisterExpression(amdgpu_gfx908::acc220, output_vec_len ); + case 477: return makeRegisterExpression(amdgpu_gfx908::acc221, output_vec_len ); + case 478: return makeRegisterExpression(amdgpu_gfx908::acc222, output_vec_len ); + case 479: return makeRegisterExpression(amdgpu_gfx908::acc223, output_vec_len ); + case 480: return makeRegisterExpression(amdgpu_gfx908::acc224, output_vec_len ); + case 481: return makeRegisterExpression(amdgpu_gfx908::acc225, output_vec_len ); + case 482: return makeRegisterExpression(amdgpu_gfx908::acc226, output_vec_len ); + case 483: return makeRegisterExpression(amdgpu_gfx908::acc227, output_vec_len ); + case 484: return makeRegisterExpression(amdgpu_gfx908::acc228, output_vec_len ); + case 485: return makeRegisterExpression(amdgpu_gfx908::acc229, output_vec_len ); + case 486: return makeRegisterExpression(amdgpu_gfx908::acc230, output_vec_len ); + case 487: return makeRegisterExpression(amdgpu_gfx908::acc231, output_vec_len ); + case 488: return makeRegisterExpression(amdgpu_gfx908::acc232, output_vec_len ); + case 489: return makeRegisterExpression(amdgpu_gfx908::acc233, output_vec_len ); + case 490: return makeRegisterExpression(amdgpu_gfx908::acc234, output_vec_len ); + case 491: return makeRegisterExpression(amdgpu_gfx908::acc235, output_vec_len ); + case 492: return makeRegisterExpression(amdgpu_gfx908::acc236, output_vec_len ); + case 493: return makeRegisterExpression(amdgpu_gfx908::acc237, output_vec_len ); + case 494: return makeRegisterExpression(amdgpu_gfx908::acc238, output_vec_len ); + case 495: return makeRegisterExpression(amdgpu_gfx908::acc239, output_vec_len ); + case 496: return makeRegisterExpression(amdgpu_gfx908::acc240, output_vec_len ); + case 497: return makeRegisterExpression(amdgpu_gfx908::acc241, output_vec_len ); + case 498: return makeRegisterExpression(amdgpu_gfx908::acc242, output_vec_len ); + case 499: return makeRegisterExpression(amdgpu_gfx908::acc243, output_vec_len ); + case 500: return makeRegisterExpression(amdgpu_gfx908::acc244, output_vec_len ); + case 501: return makeRegisterExpression(amdgpu_gfx908::acc245, output_vec_len ); + case 502: return makeRegisterExpression(amdgpu_gfx908::acc246, output_vec_len ); + case 503: return makeRegisterExpression(amdgpu_gfx908::acc247, output_vec_len ); + case 504: return makeRegisterExpression(amdgpu_gfx908::acc248, output_vec_len ); + case 505: return makeRegisterExpression(amdgpu_gfx908::acc249, output_vec_len ); + case 506: return makeRegisterExpression(amdgpu_gfx908::acc250, output_vec_len ); + case 507: return makeRegisterExpression(amdgpu_gfx908::acc251, output_vec_len ); + case 508: return makeRegisterExpression(amdgpu_gfx908::acc252, output_vec_len ); + case 509: return makeRegisterExpression(amdgpu_gfx908::acc253, output_vec_len ); + case 510: return makeRegisterExpression(amdgpu_gfx908::acc254, output_vec_len ); + case 511: return makeRegisterExpression(amdgpu_gfx908::acc255, output_vec_len ); + case 768: return makeRegisterExpression(amdgpu_gfx908::acc0, output_vec_len ); + case 769: return makeRegisterExpression(amdgpu_gfx908::acc1, output_vec_len ); + case 770: return makeRegisterExpression(amdgpu_gfx908::acc2, output_vec_len ); + case 771: return makeRegisterExpression(amdgpu_gfx908::acc3, output_vec_len ); + case 772: return makeRegisterExpression(amdgpu_gfx908::acc4, output_vec_len ); + case 773: return makeRegisterExpression(amdgpu_gfx908::acc5, output_vec_len ); + case 774: return makeRegisterExpression(amdgpu_gfx908::acc6, output_vec_len ); + case 775: return makeRegisterExpression(amdgpu_gfx908::acc7, output_vec_len ); + case 776: return makeRegisterExpression(amdgpu_gfx908::acc8, output_vec_len ); + case 777: return makeRegisterExpression(amdgpu_gfx908::acc9, output_vec_len ); + case 778: return makeRegisterExpression(amdgpu_gfx908::acc10, output_vec_len ); + case 779: return makeRegisterExpression(amdgpu_gfx908::acc11, output_vec_len ); + case 780: return makeRegisterExpression(amdgpu_gfx908::acc12, output_vec_len ); + case 781: return makeRegisterExpression(amdgpu_gfx908::acc13, output_vec_len ); + case 782: return makeRegisterExpression(amdgpu_gfx908::acc14, output_vec_len ); + case 783: return makeRegisterExpression(amdgpu_gfx908::acc15, output_vec_len ); + case 784: return makeRegisterExpression(amdgpu_gfx908::acc16, output_vec_len ); + case 785: return makeRegisterExpression(amdgpu_gfx908::acc17, output_vec_len ); + case 786: return makeRegisterExpression(amdgpu_gfx908::acc18, output_vec_len ); + case 787: return makeRegisterExpression(amdgpu_gfx908::acc19, output_vec_len ); + case 788: return makeRegisterExpression(amdgpu_gfx908::acc20, output_vec_len ); + case 789: return makeRegisterExpression(amdgpu_gfx908::acc21, output_vec_len ); + case 790: return makeRegisterExpression(amdgpu_gfx908::acc22, output_vec_len ); + case 791: return makeRegisterExpression(amdgpu_gfx908::acc23, output_vec_len ); + case 792: return makeRegisterExpression(amdgpu_gfx908::acc24, output_vec_len ); + case 793: return makeRegisterExpression(amdgpu_gfx908::acc25, output_vec_len ); + case 794: return makeRegisterExpression(amdgpu_gfx908::acc26, output_vec_len ); + case 795: return makeRegisterExpression(amdgpu_gfx908::acc27, output_vec_len ); + case 796: return makeRegisterExpression(amdgpu_gfx908::acc28, output_vec_len ); + case 797: return makeRegisterExpression(amdgpu_gfx908::acc29, output_vec_len ); + case 798: return makeRegisterExpression(amdgpu_gfx908::acc30, output_vec_len ); + case 799: return makeRegisterExpression(amdgpu_gfx908::acc31, output_vec_len ); + case 800: return makeRegisterExpression(amdgpu_gfx908::acc32, output_vec_len ); + case 801: return makeRegisterExpression(amdgpu_gfx908::acc33, output_vec_len ); + case 802: return makeRegisterExpression(amdgpu_gfx908::acc34, output_vec_len ); + case 803: return makeRegisterExpression(amdgpu_gfx908::acc35, output_vec_len ); + case 804: return makeRegisterExpression(amdgpu_gfx908::acc36, output_vec_len ); + case 805: return makeRegisterExpression(amdgpu_gfx908::acc37, output_vec_len ); + case 806: return makeRegisterExpression(amdgpu_gfx908::acc38, output_vec_len ); + case 807: return makeRegisterExpression(amdgpu_gfx908::acc39, output_vec_len ); + case 808: return makeRegisterExpression(amdgpu_gfx908::acc40, output_vec_len ); + case 809: return makeRegisterExpression(amdgpu_gfx908::acc41, output_vec_len ); + case 810: return makeRegisterExpression(amdgpu_gfx908::acc42, output_vec_len ); + case 811: return makeRegisterExpression(amdgpu_gfx908::acc43, output_vec_len ); + case 812: return makeRegisterExpression(amdgpu_gfx908::acc44, output_vec_len ); + case 813: return makeRegisterExpression(amdgpu_gfx908::acc45, output_vec_len ); + case 814: return makeRegisterExpression(amdgpu_gfx908::acc46, output_vec_len ); + case 815: return makeRegisterExpression(amdgpu_gfx908::acc47, output_vec_len ); + case 816: return makeRegisterExpression(amdgpu_gfx908::acc48, output_vec_len ); + case 817: return makeRegisterExpression(amdgpu_gfx908::acc49, output_vec_len ); + case 818: return makeRegisterExpression(amdgpu_gfx908::acc50, output_vec_len ); + case 819: return makeRegisterExpression(amdgpu_gfx908::acc51, output_vec_len ); + case 820: return makeRegisterExpression(amdgpu_gfx908::acc52, output_vec_len ); + case 821: return makeRegisterExpression(amdgpu_gfx908::acc53, output_vec_len ); + case 822: return makeRegisterExpression(amdgpu_gfx908::acc54, output_vec_len ); + case 823: return makeRegisterExpression(amdgpu_gfx908::acc55, output_vec_len ); + case 824: return makeRegisterExpression(amdgpu_gfx908::acc56, output_vec_len ); + case 825: return makeRegisterExpression(amdgpu_gfx908::acc57, output_vec_len ); + case 826: return makeRegisterExpression(amdgpu_gfx908::acc58, output_vec_len ); + case 827: return makeRegisterExpression(amdgpu_gfx908::acc59, output_vec_len ); + case 828: return makeRegisterExpression(amdgpu_gfx908::acc60, output_vec_len ); + case 829: return makeRegisterExpression(amdgpu_gfx908::acc61, output_vec_len ); + case 830: return makeRegisterExpression(amdgpu_gfx908::acc62, output_vec_len ); + case 831: return makeRegisterExpression(amdgpu_gfx908::acc63, output_vec_len ); + case 832: return makeRegisterExpression(amdgpu_gfx908::acc64, output_vec_len ); + case 833: return makeRegisterExpression(amdgpu_gfx908::acc65, output_vec_len ); + case 834: return makeRegisterExpression(amdgpu_gfx908::acc66, output_vec_len ); + case 835: return makeRegisterExpression(amdgpu_gfx908::acc67, output_vec_len ); + case 836: return makeRegisterExpression(amdgpu_gfx908::acc68, output_vec_len ); + case 837: return makeRegisterExpression(amdgpu_gfx908::acc69, output_vec_len ); + case 838: return makeRegisterExpression(amdgpu_gfx908::acc70, output_vec_len ); + case 839: return makeRegisterExpression(amdgpu_gfx908::acc71, output_vec_len ); + case 840: return makeRegisterExpression(amdgpu_gfx908::acc72, output_vec_len ); + case 841: return makeRegisterExpression(amdgpu_gfx908::acc73, output_vec_len ); + case 842: return makeRegisterExpression(amdgpu_gfx908::acc74, output_vec_len ); + case 843: return makeRegisterExpression(amdgpu_gfx908::acc75, output_vec_len ); + case 844: return makeRegisterExpression(amdgpu_gfx908::acc76, output_vec_len ); + case 845: return makeRegisterExpression(amdgpu_gfx908::acc77, output_vec_len ); + case 846: return makeRegisterExpression(amdgpu_gfx908::acc78, output_vec_len ); + case 847: return makeRegisterExpression(amdgpu_gfx908::acc79, output_vec_len ); + case 848: return makeRegisterExpression(amdgpu_gfx908::acc80, output_vec_len ); + case 849: return makeRegisterExpression(amdgpu_gfx908::acc81, output_vec_len ); + case 850: return makeRegisterExpression(amdgpu_gfx908::acc82, output_vec_len ); + case 851: return makeRegisterExpression(amdgpu_gfx908::acc83, output_vec_len ); + case 852: return makeRegisterExpression(amdgpu_gfx908::acc84, output_vec_len ); + case 853: return makeRegisterExpression(amdgpu_gfx908::acc85, output_vec_len ); + case 854: return makeRegisterExpression(amdgpu_gfx908::acc86, output_vec_len ); + case 855: return makeRegisterExpression(amdgpu_gfx908::acc87, output_vec_len ); + case 856: return makeRegisterExpression(amdgpu_gfx908::acc88, output_vec_len ); + case 857: return makeRegisterExpression(amdgpu_gfx908::acc89, output_vec_len ); + case 858: return makeRegisterExpression(amdgpu_gfx908::acc90, output_vec_len ); + case 859: return makeRegisterExpression(amdgpu_gfx908::acc91, output_vec_len ); + case 860: return makeRegisterExpression(amdgpu_gfx908::acc92, output_vec_len ); + case 861: return makeRegisterExpression(amdgpu_gfx908::acc93, output_vec_len ); + case 862: return makeRegisterExpression(amdgpu_gfx908::acc94, output_vec_len ); + case 863: return makeRegisterExpression(amdgpu_gfx908::acc95, output_vec_len ); + case 864: return makeRegisterExpression(amdgpu_gfx908::acc96, output_vec_len ); + case 865: return makeRegisterExpression(amdgpu_gfx908::acc97, output_vec_len ); + case 866: return makeRegisterExpression(amdgpu_gfx908::acc98, output_vec_len ); + case 867: return makeRegisterExpression(amdgpu_gfx908::acc99, output_vec_len ); + case 868: return makeRegisterExpression(amdgpu_gfx908::acc100, output_vec_len ); + case 869: return makeRegisterExpression(amdgpu_gfx908::acc101, output_vec_len ); + case 870: return makeRegisterExpression(amdgpu_gfx908::acc102, output_vec_len ); + case 871: return makeRegisterExpression(amdgpu_gfx908::acc103, output_vec_len ); + case 872: return makeRegisterExpression(amdgpu_gfx908::acc104, output_vec_len ); + case 873: return makeRegisterExpression(amdgpu_gfx908::acc105, output_vec_len ); + case 874: return makeRegisterExpression(amdgpu_gfx908::acc106, output_vec_len ); + case 875: return makeRegisterExpression(amdgpu_gfx908::acc107, output_vec_len ); + case 876: return makeRegisterExpression(amdgpu_gfx908::acc108, output_vec_len ); + case 877: return makeRegisterExpression(amdgpu_gfx908::acc109, output_vec_len ); + case 878: return makeRegisterExpression(amdgpu_gfx908::acc110, output_vec_len ); + case 879: return makeRegisterExpression(amdgpu_gfx908::acc111, output_vec_len ); + case 880: return makeRegisterExpression(amdgpu_gfx908::acc112, output_vec_len ); + case 881: return makeRegisterExpression(amdgpu_gfx908::acc113, output_vec_len ); + case 882: return makeRegisterExpression(amdgpu_gfx908::acc114, output_vec_len ); + case 883: return makeRegisterExpression(amdgpu_gfx908::acc115, output_vec_len ); + case 884: return makeRegisterExpression(amdgpu_gfx908::acc116, output_vec_len ); + case 885: return makeRegisterExpression(amdgpu_gfx908::acc117, output_vec_len ); + case 886: return makeRegisterExpression(amdgpu_gfx908::acc118, output_vec_len ); + case 887: return makeRegisterExpression(amdgpu_gfx908::acc119, output_vec_len ); + case 888: return makeRegisterExpression(amdgpu_gfx908::acc120, output_vec_len ); + case 889: return makeRegisterExpression(amdgpu_gfx908::acc121, output_vec_len ); + case 890: return makeRegisterExpression(amdgpu_gfx908::acc122, output_vec_len ); + case 891: return makeRegisterExpression(amdgpu_gfx908::acc123, output_vec_len ); + case 892: return makeRegisterExpression(amdgpu_gfx908::acc124, output_vec_len ); + case 893: return makeRegisterExpression(amdgpu_gfx908::acc125, output_vec_len ); + case 894: return makeRegisterExpression(amdgpu_gfx908::acc126, output_vec_len ); + case 895: return makeRegisterExpression(amdgpu_gfx908::acc127, output_vec_len ); + case 896: return makeRegisterExpression(amdgpu_gfx908::acc128, output_vec_len ); + case 897: return makeRegisterExpression(amdgpu_gfx908::acc129, output_vec_len ); + case 898: return makeRegisterExpression(amdgpu_gfx908::acc130, output_vec_len ); + case 899: return makeRegisterExpression(amdgpu_gfx908::acc131, output_vec_len ); + case 900: return makeRegisterExpression(amdgpu_gfx908::acc132, output_vec_len ); + case 901: return makeRegisterExpression(amdgpu_gfx908::acc133, output_vec_len ); + case 902: return makeRegisterExpression(amdgpu_gfx908::acc134, output_vec_len ); + case 903: return makeRegisterExpression(amdgpu_gfx908::acc135, output_vec_len ); + case 904: return makeRegisterExpression(amdgpu_gfx908::acc136, output_vec_len ); + case 905: return makeRegisterExpression(amdgpu_gfx908::acc137, output_vec_len ); + case 906: return makeRegisterExpression(amdgpu_gfx908::acc138, output_vec_len ); + case 907: return makeRegisterExpression(amdgpu_gfx908::acc139, output_vec_len ); + case 908: return makeRegisterExpression(amdgpu_gfx908::acc140, output_vec_len ); + case 909: return makeRegisterExpression(amdgpu_gfx908::acc141, output_vec_len ); + case 910: return makeRegisterExpression(amdgpu_gfx908::acc142, output_vec_len ); + case 911: return makeRegisterExpression(amdgpu_gfx908::acc143, output_vec_len ); + case 912: return makeRegisterExpression(amdgpu_gfx908::acc144, output_vec_len ); + case 913: return makeRegisterExpression(amdgpu_gfx908::acc145, output_vec_len ); + case 914: return makeRegisterExpression(amdgpu_gfx908::acc146, output_vec_len ); + case 915: return makeRegisterExpression(amdgpu_gfx908::acc147, output_vec_len ); + case 916: return makeRegisterExpression(amdgpu_gfx908::acc148, output_vec_len ); + case 917: return makeRegisterExpression(amdgpu_gfx908::acc149, output_vec_len ); + case 918: return makeRegisterExpression(amdgpu_gfx908::acc150, output_vec_len ); + case 919: return makeRegisterExpression(amdgpu_gfx908::acc151, output_vec_len ); + case 920: return makeRegisterExpression(amdgpu_gfx908::acc152, output_vec_len ); + case 921: return makeRegisterExpression(amdgpu_gfx908::acc153, output_vec_len ); + case 922: return makeRegisterExpression(amdgpu_gfx908::acc154, output_vec_len ); + case 923: return makeRegisterExpression(amdgpu_gfx908::acc155, output_vec_len ); + case 924: return makeRegisterExpression(amdgpu_gfx908::acc156, output_vec_len ); + case 925: return makeRegisterExpression(amdgpu_gfx908::acc157, output_vec_len ); + case 926: return makeRegisterExpression(amdgpu_gfx908::acc158, output_vec_len ); + case 927: return makeRegisterExpression(amdgpu_gfx908::acc159, output_vec_len ); + case 928: return makeRegisterExpression(amdgpu_gfx908::acc160, output_vec_len ); + case 929: return makeRegisterExpression(amdgpu_gfx908::acc161, output_vec_len ); + case 930: return makeRegisterExpression(amdgpu_gfx908::acc162, output_vec_len ); + case 931: return makeRegisterExpression(amdgpu_gfx908::acc163, output_vec_len ); + case 932: return makeRegisterExpression(amdgpu_gfx908::acc164, output_vec_len ); + case 933: return makeRegisterExpression(amdgpu_gfx908::acc165, output_vec_len ); + case 934: return makeRegisterExpression(amdgpu_gfx908::acc166, output_vec_len ); + case 935: return makeRegisterExpression(amdgpu_gfx908::acc167, output_vec_len ); + case 936: return makeRegisterExpression(amdgpu_gfx908::acc168, output_vec_len ); + case 937: return makeRegisterExpression(amdgpu_gfx908::acc169, output_vec_len ); + case 938: return makeRegisterExpression(amdgpu_gfx908::acc170, output_vec_len ); + case 939: return makeRegisterExpression(amdgpu_gfx908::acc171, output_vec_len ); + case 940: return makeRegisterExpression(amdgpu_gfx908::acc172, output_vec_len ); + case 941: return makeRegisterExpression(amdgpu_gfx908::acc173, output_vec_len ); + case 942: return makeRegisterExpression(amdgpu_gfx908::acc174, output_vec_len ); + case 943: return makeRegisterExpression(amdgpu_gfx908::acc175, output_vec_len ); + case 944: return makeRegisterExpression(amdgpu_gfx908::acc176, output_vec_len ); + case 945: return makeRegisterExpression(amdgpu_gfx908::acc177, output_vec_len ); + case 946: return makeRegisterExpression(amdgpu_gfx908::acc178, output_vec_len ); + case 947: return makeRegisterExpression(amdgpu_gfx908::acc179, output_vec_len ); + case 948: return makeRegisterExpression(amdgpu_gfx908::acc180, output_vec_len ); + case 949: return makeRegisterExpression(amdgpu_gfx908::acc181, output_vec_len ); + case 950: return makeRegisterExpression(amdgpu_gfx908::acc182, output_vec_len ); + case 951: return makeRegisterExpression(amdgpu_gfx908::acc183, output_vec_len ); + case 952: return makeRegisterExpression(amdgpu_gfx908::acc184, output_vec_len ); + case 953: return makeRegisterExpression(amdgpu_gfx908::acc185, output_vec_len ); + case 954: return makeRegisterExpression(amdgpu_gfx908::acc186, output_vec_len ); + case 955: return makeRegisterExpression(amdgpu_gfx908::acc187, output_vec_len ); + case 956: return makeRegisterExpression(amdgpu_gfx908::acc188, output_vec_len ); + case 957: return makeRegisterExpression(amdgpu_gfx908::acc189, output_vec_len ); + case 958: return makeRegisterExpression(amdgpu_gfx908::acc190, output_vec_len ); + case 959: return makeRegisterExpression(amdgpu_gfx908::acc191, output_vec_len ); + case 960: return makeRegisterExpression(amdgpu_gfx908::acc192, output_vec_len ); + case 961: return makeRegisterExpression(amdgpu_gfx908::acc193, output_vec_len ); + case 962: return makeRegisterExpression(amdgpu_gfx908::acc194, output_vec_len ); + case 963: return makeRegisterExpression(amdgpu_gfx908::acc195, output_vec_len ); + case 964: return makeRegisterExpression(amdgpu_gfx908::acc196, output_vec_len ); + case 965: return makeRegisterExpression(amdgpu_gfx908::acc197, output_vec_len ); + case 966: return makeRegisterExpression(amdgpu_gfx908::acc198, output_vec_len ); + case 967: return makeRegisterExpression(amdgpu_gfx908::acc199, output_vec_len ); + case 968: return makeRegisterExpression(amdgpu_gfx908::acc200, output_vec_len ); + case 969: return makeRegisterExpression(amdgpu_gfx908::acc201, output_vec_len ); + case 970: return makeRegisterExpression(amdgpu_gfx908::acc202, output_vec_len ); + case 971: return makeRegisterExpression(amdgpu_gfx908::acc203, output_vec_len ); + case 972: return makeRegisterExpression(amdgpu_gfx908::acc204, output_vec_len ); + case 973: return makeRegisterExpression(amdgpu_gfx908::acc205, output_vec_len ); + case 974: return makeRegisterExpression(amdgpu_gfx908::acc206, output_vec_len ); + case 975: return makeRegisterExpression(amdgpu_gfx908::acc207, output_vec_len ); + case 976: return makeRegisterExpression(amdgpu_gfx908::acc208, output_vec_len ); + case 977: return makeRegisterExpression(amdgpu_gfx908::acc209, output_vec_len ); + case 978: return makeRegisterExpression(amdgpu_gfx908::acc210, output_vec_len ); + case 979: return makeRegisterExpression(amdgpu_gfx908::acc211, output_vec_len ); + case 980: return makeRegisterExpression(amdgpu_gfx908::acc212, output_vec_len ); + case 981: return makeRegisterExpression(amdgpu_gfx908::acc213, output_vec_len ); + case 982: return makeRegisterExpression(amdgpu_gfx908::acc214, output_vec_len ); + case 983: return makeRegisterExpression(amdgpu_gfx908::acc215, output_vec_len ); + case 984: return makeRegisterExpression(amdgpu_gfx908::acc216, output_vec_len ); + case 985: return makeRegisterExpression(amdgpu_gfx908::acc217, output_vec_len ); + case 986: return makeRegisterExpression(amdgpu_gfx908::acc218, output_vec_len ); + case 987: return makeRegisterExpression(amdgpu_gfx908::acc219, output_vec_len ); + case 988: return makeRegisterExpression(amdgpu_gfx908::acc220, output_vec_len ); + case 989: return makeRegisterExpression(amdgpu_gfx908::acc221, output_vec_len ); + case 990: return makeRegisterExpression(amdgpu_gfx908::acc222, output_vec_len ); + case 991: return makeRegisterExpression(amdgpu_gfx908::acc223, output_vec_len ); + case 992: return makeRegisterExpression(amdgpu_gfx908::acc224, output_vec_len ); + case 993: return makeRegisterExpression(amdgpu_gfx908::acc225, output_vec_len ); + case 994: return makeRegisterExpression(amdgpu_gfx908::acc226, output_vec_len ); + case 995: return makeRegisterExpression(amdgpu_gfx908::acc227, output_vec_len ); + case 996: return makeRegisterExpression(amdgpu_gfx908::acc228, output_vec_len ); + case 997: return makeRegisterExpression(amdgpu_gfx908::acc229, output_vec_len ); + case 998: return makeRegisterExpression(amdgpu_gfx908::acc230, output_vec_len ); + case 999: return makeRegisterExpression(amdgpu_gfx908::acc231, output_vec_len ); + case 1000: return makeRegisterExpression(amdgpu_gfx908::acc232, output_vec_len ); + case 1001: return makeRegisterExpression(amdgpu_gfx908::acc233, output_vec_len ); + case 1002: return makeRegisterExpression(amdgpu_gfx908::acc234, output_vec_len ); + case 1003: return makeRegisterExpression(amdgpu_gfx908::acc235, output_vec_len ); + case 1004: return makeRegisterExpression(amdgpu_gfx908::acc236, output_vec_len ); + case 1005: return makeRegisterExpression(amdgpu_gfx908::acc237, output_vec_len ); + case 1006: return makeRegisterExpression(amdgpu_gfx908::acc238, output_vec_len ); + case 1007: return makeRegisterExpression(amdgpu_gfx908::acc239, output_vec_len ); + case 1008: return makeRegisterExpression(amdgpu_gfx908::acc240, output_vec_len ); + case 1009: return makeRegisterExpression(amdgpu_gfx908::acc241, output_vec_len ); + case 1010: return makeRegisterExpression(amdgpu_gfx908::acc242, output_vec_len ); + case 1011: return makeRegisterExpression(amdgpu_gfx908::acc243, output_vec_len ); + case 1012: return makeRegisterExpression(amdgpu_gfx908::acc244, output_vec_len ); + case 1013: return makeRegisterExpression(amdgpu_gfx908::acc245, output_vec_len ); + case 1014: return makeRegisterExpression(amdgpu_gfx908::acc246, output_vec_len ); + case 1015: return makeRegisterExpression(amdgpu_gfx908::acc247, output_vec_len ); + case 1016: return makeRegisterExpression(amdgpu_gfx908::acc248, output_vec_len ); + case 1017: return makeRegisterExpression(amdgpu_gfx908::acc249, output_vec_len ); + case 1018: return makeRegisterExpression(amdgpu_gfx908::acc250, output_vec_len ); + case 1019: return makeRegisterExpression(amdgpu_gfx908::acc251, output_vec_len ); + case 1020: return makeRegisterExpression(amdgpu_gfx908::acc252, output_vec_len ); + case 1021: return makeRegisterExpression(amdgpu_gfx908::acc253, output_vec_len ); + case 1022: return makeRegisterExpression(amdgpu_gfx908::acc254, output_vec_len ); + case 1023: return makeRegisterExpression(amdgpu_gfx908::acc255, output_vec_len ); + case 128: return Immediate::makeImmediate(Result(u32, 0)); + case 129: return Immediate::makeImmediate(Result(u32, 1)); + case 130: return Immediate::makeImmediate(Result(u32, 2)); + case 131: return Immediate::makeImmediate(Result(u32, 3)); + case 132: return Immediate::makeImmediate(Result(u32, 4)); + case 133: return Immediate::makeImmediate(Result(u32, 5)); + case 134: return Immediate::makeImmediate(Result(u32, 6)); + case 135: return Immediate::makeImmediate(Result(u32, 7)); + case 136: return Immediate::makeImmediate(Result(u32, 8)); + case 137: return Immediate::makeImmediate(Result(u32, 9)); + case 138: return Immediate::makeImmediate(Result(u32, 10)); + case 139: return Immediate::makeImmediate(Result(u32, 11)); + case 140: return Immediate::makeImmediate(Result(u32, 12)); + case 141: return Immediate::makeImmediate(Result(u32, 13)); + case 142: return Immediate::makeImmediate(Result(u32, 14)); + case 143: return Immediate::makeImmediate(Result(u32, 15)); + case 144: return Immediate::makeImmediate(Result(u32, 16)); + case 145: return Immediate::makeImmediate(Result(u32, 17)); + case 146: return Immediate::makeImmediate(Result(u32, 18)); + case 147: return Immediate::makeImmediate(Result(u32, 19)); + case 148: return Immediate::makeImmediate(Result(u32, 20)); + case 149: return Immediate::makeImmediate(Result(u32, 21)); + case 150: return Immediate::makeImmediate(Result(u32, 22)); + case 151: return Immediate::makeImmediate(Result(u32, 23)); + case 152: return Immediate::makeImmediate(Result(u32, 24)); + case 153: return Immediate::makeImmediate(Result(u32, 25)); + case 154: return Immediate::makeImmediate(Result(u32, 26)); + case 155: return Immediate::makeImmediate(Result(u32, 27)); + case 156: return Immediate::makeImmediate(Result(u32, 28)); + case 157: return Immediate::makeImmediate(Result(u32, 29)); + case 158: return Immediate::makeImmediate(Result(u32, 30)); + case 159: return Immediate::makeImmediate(Result(u32, 31)); + case 160: return Immediate::makeImmediate(Result(u32, 32)); + case 161: return Immediate::makeImmediate(Result(u32, 33)); + case 162: return Immediate::makeImmediate(Result(u32, 34)); + case 163: return Immediate::makeImmediate(Result(u32, 35)); + case 164: return Immediate::makeImmediate(Result(u32, 36)); + case 165: return Immediate::makeImmediate(Result(u32, 37)); + case 166: return Immediate::makeImmediate(Result(u32, 38)); + case 167: return Immediate::makeImmediate(Result(u32, 39)); + case 168: return Immediate::makeImmediate(Result(u32, 40)); + case 169: return Immediate::makeImmediate(Result(u32, 41)); + case 170: return Immediate::makeImmediate(Result(u32, 42)); + case 171: return Immediate::makeImmediate(Result(u32, 43)); + case 172: return Immediate::makeImmediate(Result(u32, 44)); + case 173: return Immediate::makeImmediate(Result(u32, 45)); + case 174: return Immediate::makeImmediate(Result(u32, 46)); + case 175: return Immediate::makeImmediate(Result(u32, 47)); + case 176: return Immediate::makeImmediate(Result(u32, 48)); + case 177: return Immediate::makeImmediate(Result(u32, 49)); + case 178: return Immediate::makeImmediate(Result(u32, 50)); + case 179: return Immediate::makeImmediate(Result(u32, 51)); + case 180: return Immediate::makeImmediate(Result(u32, 52)); + case 181: return Immediate::makeImmediate(Result(u32, 53)); + case 182: return Immediate::makeImmediate(Result(u32, 54)); + case 183: return Immediate::makeImmediate(Result(u32, 55)); + case 184: return Immediate::makeImmediate(Result(u32, 56)); + case 185: return Immediate::makeImmediate(Result(u32, 57)); + case 186: return Immediate::makeImmediate(Result(u32, 58)); + case 187: return Immediate::makeImmediate(Result(u32, 59)); + case 188: return Immediate::makeImmediate(Result(u32, 60)); + case 189: return Immediate::makeImmediate(Result(u32, 61)); + case 190: return Immediate::makeImmediate(Result(u32, 62)); + case 191: return Immediate::makeImmediate(Result(u32, 63)); + case 192: return Immediate::makeImmediate(Result(u32, 64)); + case 193: return Immediate::makeImmediate(Result(u32, -1)); + case 194: return Immediate::makeImmediate(Result(u32, -2)); + case 195: return Immediate::makeImmediate(Result(u32, -3)); + case 196: return Immediate::makeImmediate(Result(u32, -4)); + case 197: return Immediate::makeImmediate(Result(u32, -5)); + case 198: return Immediate::makeImmediate(Result(u32, -6)); + case 199: return Immediate::makeImmediate(Result(u32, -7)); + case 200: return Immediate::makeImmediate(Result(u32, -8)); + case 201: return Immediate::makeImmediate(Result(u32, -9)); + case 202: return Immediate::makeImmediate(Result(u32, -10)); + case 203: return Immediate::makeImmediate(Result(u32, -11)); + case 204: return Immediate::makeImmediate(Result(u32, -12)); + case 205: return Immediate::makeImmediate(Result(u32, -13)); + case 206: return Immediate::makeImmediate(Result(u32, -14)); + case 207: return Immediate::makeImmediate(Result(u32, -15)); + case 208: return Immediate::makeImmediate(Result(u32, -16)); + case 240: return Immediate::makeImmediate(Result(sp_float, 0.5)); + case 241: return Immediate::makeImmediate(Result(sp_float, -0.5)); + case 242: return Immediate::makeImmediate(Result(sp_float, 1.0)); + case 243: return Immediate::makeImmediate(Result(sp_float, -1.0)); + case 244: return Immediate::makeImmediate(Result(sp_float, 2.0)); + case 245: return Immediate::makeImmediate(Result(sp_float, -2.0)); + case 246: return Immediate::makeImmediate(Result(sp_float, 4.0)); + case 247: return Immediate::makeImmediate(Result(sp_float, -4.0)); + case 248: return Immediate::makeImmediate(Result(sp_float, 0.15915494)); + default: return makeRegisterExpression(amdgpu_gfx908::invalid); + } + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SRC_NOLDS(uint64_t input, uint32_t output_vec_len) + { + switch (input) { + case 0: return makeRegisterExpression(amdgpu_gfx908::s0, output_vec_len ); + case 1: return makeRegisterExpression(amdgpu_gfx908::s1, output_vec_len ); + case 2: return makeRegisterExpression(amdgpu_gfx908::s2, output_vec_len ); + case 3: return makeRegisterExpression(amdgpu_gfx908::s3, output_vec_len ); + case 4: return makeRegisterExpression(amdgpu_gfx908::s4, output_vec_len ); + case 5: return makeRegisterExpression(amdgpu_gfx908::s5, output_vec_len ); + case 6: return makeRegisterExpression(amdgpu_gfx908::s6, output_vec_len ); + case 7: return makeRegisterExpression(amdgpu_gfx908::s7, output_vec_len ); + case 8: return makeRegisterExpression(amdgpu_gfx908::s8, output_vec_len ); + case 9: return makeRegisterExpression(amdgpu_gfx908::s9, output_vec_len ); + case 10: return makeRegisterExpression(amdgpu_gfx908::s10, output_vec_len ); + case 11: return makeRegisterExpression(amdgpu_gfx908::s11, output_vec_len ); + case 12: return makeRegisterExpression(amdgpu_gfx908::s12, output_vec_len ); + case 13: return makeRegisterExpression(amdgpu_gfx908::s13, output_vec_len ); + case 14: return makeRegisterExpression(amdgpu_gfx908::s14, output_vec_len ); + case 15: return makeRegisterExpression(amdgpu_gfx908::s15, output_vec_len ); + case 16: return makeRegisterExpression(amdgpu_gfx908::s16, output_vec_len ); + case 17: return makeRegisterExpression(amdgpu_gfx908::s17, output_vec_len ); + case 18: return makeRegisterExpression(amdgpu_gfx908::s18, output_vec_len ); + case 19: return makeRegisterExpression(amdgpu_gfx908::s19, output_vec_len ); + case 20: return makeRegisterExpression(amdgpu_gfx908::s20, output_vec_len ); + case 21: return makeRegisterExpression(amdgpu_gfx908::s21, output_vec_len ); + case 22: return makeRegisterExpression(amdgpu_gfx908::s22, output_vec_len ); + case 23: return makeRegisterExpression(amdgpu_gfx908::s23, output_vec_len ); + case 24: return makeRegisterExpression(amdgpu_gfx908::s24, output_vec_len ); + case 25: return makeRegisterExpression(amdgpu_gfx908::s25, output_vec_len ); + case 26: return makeRegisterExpression(amdgpu_gfx908::s26, output_vec_len ); + case 27: return makeRegisterExpression(amdgpu_gfx908::s27, output_vec_len ); + case 28: return makeRegisterExpression(amdgpu_gfx908::s28, output_vec_len ); + case 29: return makeRegisterExpression(amdgpu_gfx908::s29, output_vec_len ); + case 30: return makeRegisterExpression(amdgpu_gfx908::s30, output_vec_len ); + case 31: return makeRegisterExpression(amdgpu_gfx908::s31, output_vec_len ); + case 32: return makeRegisterExpression(amdgpu_gfx908::s32, output_vec_len ); + case 33: return makeRegisterExpression(amdgpu_gfx908::s33, output_vec_len ); + case 34: return makeRegisterExpression(amdgpu_gfx908::s34, output_vec_len ); + case 35: return makeRegisterExpression(amdgpu_gfx908::s35, output_vec_len ); + case 36: return makeRegisterExpression(amdgpu_gfx908::s36, output_vec_len ); + case 37: return makeRegisterExpression(amdgpu_gfx908::s37, output_vec_len ); + case 38: return makeRegisterExpression(amdgpu_gfx908::s38, output_vec_len ); + case 39: return makeRegisterExpression(amdgpu_gfx908::s39, output_vec_len ); + case 40: return makeRegisterExpression(amdgpu_gfx908::s40, output_vec_len ); + case 41: return makeRegisterExpression(amdgpu_gfx908::s41, output_vec_len ); + case 42: return makeRegisterExpression(amdgpu_gfx908::s42, output_vec_len ); + case 43: return makeRegisterExpression(amdgpu_gfx908::s43, output_vec_len ); + case 44: return makeRegisterExpression(amdgpu_gfx908::s44, output_vec_len ); + case 45: return makeRegisterExpression(amdgpu_gfx908::s45, output_vec_len ); + case 46: return makeRegisterExpression(amdgpu_gfx908::s46, output_vec_len ); + case 47: return makeRegisterExpression(amdgpu_gfx908::s47, output_vec_len ); + case 48: return makeRegisterExpression(amdgpu_gfx908::s48, output_vec_len ); + case 49: return makeRegisterExpression(amdgpu_gfx908::s49, output_vec_len ); + case 50: return makeRegisterExpression(amdgpu_gfx908::s50, output_vec_len ); + case 51: return makeRegisterExpression(amdgpu_gfx908::s51, output_vec_len ); + case 52: return makeRegisterExpression(amdgpu_gfx908::s52, output_vec_len ); + case 53: return makeRegisterExpression(amdgpu_gfx908::s53, output_vec_len ); + case 54: return makeRegisterExpression(amdgpu_gfx908::s54, output_vec_len ); + case 55: return makeRegisterExpression(amdgpu_gfx908::s55, output_vec_len ); + case 56: return makeRegisterExpression(amdgpu_gfx908::s56, output_vec_len ); + case 57: return makeRegisterExpression(amdgpu_gfx908::s57, output_vec_len ); + case 58: return makeRegisterExpression(amdgpu_gfx908::s58, output_vec_len ); + case 59: return makeRegisterExpression(amdgpu_gfx908::s59, output_vec_len ); + case 60: return makeRegisterExpression(amdgpu_gfx908::s60, output_vec_len ); + case 61: return makeRegisterExpression(amdgpu_gfx908::s61, output_vec_len ); + case 62: return makeRegisterExpression(amdgpu_gfx908::s62, output_vec_len ); + case 63: return makeRegisterExpression(amdgpu_gfx908::s63, output_vec_len ); + case 64: return makeRegisterExpression(amdgpu_gfx908::s64, output_vec_len ); + case 65: return makeRegisterExpression(amdgpu_gfx908::s65, output_vec_len ); + case 66: return makeRegisterExpression(amdgpu_gfx908::s66, output_vec_len ); + case 67: return makeRegisterExpression(amdgpu_gfx908::s67, output_vec_len ); + case 68: return makeRegisterExpression(amdgpu_gfx908::s68, output_vec_len ); + case 69: return makeRegisterExpression(amdgpu_gfx908::s69, output_vec_len ); + case 70: return makeRegisterExpression(amdgpu_gfx908::s70, output_vec_len ); + case 71: return makeRegisterExpression(amdgpu_gfx908::s71, output_vec_len ); + case 72: return makeRegisterExpression(amdgpu_gfx908::s72, output_vec_len ); + case 73: return makeRegisterExpression(amdgpu_gfx908::s73, output_vec_len ); + case 74: return makeRegisterExpression(amdgpu_gfx908::s74, output_vec_len ); + case 75: return makeRegisterExpression(amdgpu_gfx908::s75, output_vec_len ); + case 76: return makeRegisterExpression(amdgpu_gfx908::s76, output_vec_len ); + case 77: return makeRegisterExpression(amdgpu_gfx908::s77, output_vec_len ); + case 78: return makeRegisterExpression(amdgpu_gfx908::s78, output_vec_len ); + case 79: return makeRegisterExpression(amdgpu_gfx908::s79, output_vec_len ); + case 80: return makeRegisterExpression(amdgpu_gfx908::s80, output_vec_len ); + case 81: return makeRegisterExpression(amdgpu_gfx908::s81, output_vec_len ); + case 82: return makeRegisterExpression(amdgpu_gfx908::s82, output_vec_len ); + case 83: return makeRegisterExpression(amdgpu_gfx908::s83, output_vec_len ); + case 84: return makeRegisterExpression(amdgpu_gfx908::s84, output_vec_len ); + case 85: return makeRegisterExpression(amdgpu_gfx908::s85, output_vec_len ); + case 86: return makeRegisterExpression(amdgpu_gfx908::s86, output_vec_len ); + case 87: return makeRegisterExpression(amdgpu_gfx908::s87, output_vec_len ); + case 88: return makeRegisterExpression(amdgpu_gfx908::s88, output_vec_len ); + case 89: return makeRegisterExpression(amdgpu_gfx908::s89, output_vec_len ); + case 90: return makeRegisterExpression(amdgpu_gfx908::s90, output_vec_len ); + case 91: return makeRegisterExpression(amdgpu_gfx908::s91, output_vec_len ); + case 92: return makeRegisterExpression(amdgpu_gfx908::s92, output_vec_len ); + case 93: return makeRegisterExpression(amdgpu_gfx908::s93, output_vec_len ); + case 94: return makeRegisterExpression(amdgpu_gfx908::s94, output_vec_len ); + case 95: return makeRegisterExpression(amdgpu_gfx908::s95, output_vec_len ); + case 96: return makeRegisterExpression(amdgpu_gfx908::s96, output_vec_len ); + case 97: return makeRegisterExpression(amdgpu_gfx908::s97, output_vec_len ); + case 98: return makeRegisterExpression(amdgpu_gfx908::s98, output_vec_len ); + case 99: return makeRegisterExpression(amdgpu_gfx908::s99, output_vec_len ); + case 100: return makeRegisterExpression(amdgpu_gfx908::s100, output_vec_len ); + case 101: return makeRegisterExpression(amdgpu_gfx908::s101, output_vec_len ); + case 104: return makeRegisterExpression(amdgpu_gfx908::xnack_mask_lo, output_vec_len ); + case 105: return makeRegisterExpression(amdgpu_gfx908::xnack_mask_hi, output_vec_len ); + case 102: return makeRegisterExpression(amdgpu_gfx908::flat_scratch_lo, output_vec_len ); + case 103: return makeRegisterExpression(amdgpu_gfx908::flat_scratch_hi, output_vec_len ); + case 108: return makeRegisterExpression(amdgpu_gfx908::ttmp0, output_vec_len ); + case 109: return makeRegisterExpression(amdgpu_gfx908::ttmp1, output_vec_len ); + case 110: return makeRegisterExpression(amdgpu_gfx908::ttmp2, output_vec_len ); + case 111: return makeRegisterExpression(amdgpu_gfx908::ttmp3, output_vec_len ); + case 112: return makeRegisterExpression(amdgpu_gfx908::ttmp4, output_vec_len ); + case 113: return makeRegisterExpression(amdgpu_gfx908::ttmp5, output_vec_len ); + case 114: return makeRegisterExpression(amdgpu_gfx908::ttmp6, output_vec_len ); + case 115: return makeRegisterExpression(amdgpu_gfx908::ttmp7, output_vec_len ); + case 116: return makeRegisterExpression(amdgpu_gfx908::ttmp8, output_vec_len ); + case 117: return makeRegisterExpression(amdgpu_gfx908::ttmp9, output_vec_len ); + case 118: return makeRegisterExpression(amdgpu_gfx908::ttmp10, output_vec_len ); + case 119: return makeRegisterExpression(amdgpu_gfx908::ttmp11, output_vec_len ); + case 120: return makeRegisterExpression(amdgpu_gfx908::ttmp12, output_vec_len ); + case 121: return makeRegisterExpression(amdgpu_gfx908::ttmp13, output_vec_len ); + case 122: return makeRegisterExpression(amdgpu_gfx908::ttmp14, output_vec_len ); + case 123: return makeRegisterExpression(amdgpu_gfx908::ttmp15, output_vec_len ); + case 106: return makeRegisterExpression(amdgpu_gfx908::vcc_lo, output_vec_len ); + case 107: return makeRegisterExpression(amdgpu_gfx908::vcc_hi, output_vec_len ); + case 124: return makeRegisterExpression(amdgpu_gfx908::m0, output_vec_len ); + case 126: return makeRegisterExpression(amdgpu_gfx908::exec_lo, output_vec_len ); + case 127: return makeRegisterExpression(amdgpu_gfx908::exec_hi, output_vec_len ); + case 128: return Immediate::makeImmediate(Result(u32, 0)); + case 129: return Immediate::makeImmediate(Result(u32, 1)); + case 130: return Immediate::makeImmediate(Result(u32, 2)); + case 131: return Immediate::makeImmediate(Result(u32, 3)); + case 132: return Immediate::makeImmediate(Result(u32, 4)); + case 133: return Immediate::makeImmediate(Result(u32, 5)); + case 134: return Immediate::makeImmediate(Result(u32, 6)); + case 135: return Immediate::makeImmediate(Result(u32, 7)); + case 136: return Immediate::makeImmediate(Result(u32, 8)); + case 137: return Immediate::makeImmediate(Result(u32, 9)); + case 138: return Immediate::makeImmediate(Result(u32, 10)); + case 139: return Immediate::makeImmediate(Result(u32, 11)); + case 140: return Immediate::makeImmediate(Result(u32, 12)); + case 141: return Immediate::makeImmediate(Result(u32, 13)); + case 142: return Immediate::makeImmediate(Result(u32, 14)); + case 143: return Immediate::makeImmediate(Result(u32, 15)); + case 144: return Immediate::makeImmediate(Result(u32, 16)); + case 145: return Immediate::makeImmediate(Result(u32, 17)); + case 146: return Immediate::makeImmediate(Result(u32, 18)); + case 147: return Immediate::makeImmediate(Result(u32, 19)); + case 148: return Immediate::makeImmediate(Result(u32, 20)); + case 149: return Immediate::makeImmediate(Result(u32, 21)); + case 150: return Immediate::makeImmediate(Result(u32, 22)); + case 151: return Immediate::makeImmediate(Result(u32, 23)); + case 152: return Immediate::makeImmediate(Result(u32, 24)); + case 153: return Immediate::makeImmediate(Result(u32, 25)); + case 154: return Immediate::makeImmediate(Result(u32, 26)); + case 155: return Immediate::makeImmediate(Result(u32, 27)); + case 156: return Immediate::makeImmediate(Result(u32, 28)); + case 157: return Immediate::makeImmediate(Result(u32, 29)); + case 158: return Immediate::makeImmediate(Result(u32, 30)); + case 159: return Immediate::makeImmediate(Result(u32, 31)); + case 160: return Immediate::makeImmediate(Result(u32, 32)); + case 161: return Immediate::makeImmediate(Result(u32, 33)); + case 162: return Immediate::makeImmediate(Result(u32, 34)); + case 163: return Immediate::makeImmediate(Result(u32, 35)); + case 164: return Immediate::makeImmediate(Result(u32, 36)); + case 165: return Immediate::makeImmediate(Result(u32, 37)); + case 166: return Immediate::makeImmediate(Result(u32, 38)); + case 167: return Immediate::makeImmediate(Result(u32, 39)); + case 168: return Immediate::makeImmediate(Result(u32, 40)); + case 169: return Immediate::makeImmediate(Result(u32, 41)); + case 170: return Immediate::makeImmediate(Result(u32, 42)); + case 171: return Immediate::makeImmediate(Result(u32, 43)); + case 172: return Immediate::makeImmediate(Result(u32, 44)); + case 173: return Immediate::makeImmediate(Result(u32, 45)); + case 174: return Immediate::makeImmediate(Result(u32, 46)); + case 175: return Immediate::makeImmediate(Result(u32, 47)); + case 176: return Immediate::makeImmediate(Result(u32, 48)); + case 177: return Immediate::makeImmediate(Result(u32, 49)); + case 178: return Immediate::makeImmediate(Result(u32, 50)); + case 179: return Immediate::makeImmediate(Result(u32, 51)); + case 180: return Immediate::makeImmediate(Result(u32, 52)); + case 181: return Immediate::makeImmediate(Result(u32, 53)); + case 182: return Immediate::makeImmediate(Result(u32, 54)); + case 183: return Immediate::makeImmediate(Result(u32, 55)); + case 184: return Immediate::makeImmediate(Result(u32, 56)); + case 185: return Immediate::makeImmediate(Result(u32, 57)); + case 186: return Immediate::makeImmediate(Result(u32, 58)); + case 187: return Immediate::makeImmediate(Result(u32, 59)); + case 188: return Immediate::makeImmediate(Result(u32, 60)); + case 189: return Immediate::makeImmediate(Result(u32, 61)); + case 190: return Immediate::makeImmediate(Result(u32, 62)); + case 191: return Immediate::makeImmediate(Result(u32, 63)); + case 192: return Immediate::makeImmediate(Result(u32, 64)); + case 193: return Immediate::makeImmediate(Result(u32, -1)); + case 194: return Immediate::makeImmediate(Result(u32, -2)); + case 195: return Immediate::makeImmediate(Result(u32, -3)); + case 196: return Immediate::makeImmediate(Result(u32, -4)); + case 197: return Immediate::makeImmediate(Result(u32, -5)); + case 198: return Immediate::makeImmediate(Result(u32, -6)); + case 199: return Immediate::makeImmediate(Result(u32, -7)); + case 200: return Immediate::makeImmediate(Result(u32, -8)); + case 201: return Immediate::makeImmediate(Result(u32, -9)); + case 202: return Immediate::makeImmediate(Result(u32, -10)); + case 203: return Immediate::makeImmediate(Result(u32, -11)); + case 204: return Immediate::makeImmediate(Result(u32, -12)); + case 205: return Immediate::makeImmediate(Result(u32, -13)); + case 206: return Immediate::makeImmediate(Result(u32, -14)); + case 207: return Immediate::makeImmediate(Result(u32, -15)); + case 208: return Immediate::makeImmediate(Result(u32, -16)); + case 240: return Immediate::makeImmediate(Result(sp_float, 0.5)); + case 241: return Immediate::makeImmediate(Result(sp_float, -0.5)); + case 242: return Immediate::makeImmediate(Result(sp_float, 1.0)); + case 243: return Immediate::makeImmediate(Result(sp_float, -1.0)); + case 244: return Immediate::makeImmediate(Result(sp_float, 2.0)); + case 245: return Immediate::makeImmediate(Result(sp_float, -2.0)); + case 246: return Immediate::makeImmediate(Result(sp_float, 4.0)); + case 247: return Immediate::makeImmediate(Result(sp_float, -4.0)); + case 248: return Immediate::makeImmediate(Result(sp_float, 0.15915494)); + case 251: return makeRegisterExpression(amdgpu_gfx908::src_vccz, output_vec_len ); + case 252: return makeRegisterExpression(amdgpu_gfx908::src_execz, output_vec_len ); + case 253: return makeRegisterExpression(amdgpu_gfx908::src_scc, output_vec_len ); + case 235: return makeRegisterExpression(amdgpu_gfx908::src_shared_base, output_vec_len ); + case 236: return makeRegisterExpression(amdgpu_gfx908::src_shared_limit, output_vec_len ); + case 237: return makeRegisterExpression(amdgpu_gfx908::src_private_base, output_vec_len ); + case 238: return makeRegisterExpression(amdgpu_gfx908::src_private_limit, output_vec_len ); + case 239: return makeRegisterExpression(amdgpu_gfx908::src_pops_exiting_wave_id, output_vec_len ); + case 256: return makeRegisterExpression(amdgpu_gfx908::v0, output_vec_len ); + case 257: return makeRegisterExpression(amdgpu_gfx908::v1, output_vec_len ); + case 258: return makeRegisterExpression(amdgpu_gfx908::v2, output_vec_len ); + case 259: return makeRegisterExpression(amdgpu_gfx908::v3, output_vec_len ); + case 260: return makeRegisterExpression(amdgpu_gfx908::v4, output_vec_len ); + case 261: return makeRegisterExpression(amdgpu_gfx908::v5, output_vec_len ); + case 262: return makeRegisterExpression(amdgpu_gfx908::v6, output_vec_len ); + case 263: return makeRegisterExpression(amdgpu_gfx908::v7, output_vec_len ); + case 264: return makeRegisterExpression(amdgpu_gfx908::v8, output_vec_len ); + case 265: return makeRegisterExpression(amdgpu_gfx908::v9, output_vec_len ); + case 266: return makeRegisterExpression(amdgpu_gfx908::v10, output_vec_len ); + case 267: return makeRegisterExpression(amdgpu_gfx908::v11, output_vec_len ); + case 268: return makeRegisterExpression(amdgpu_gfx908::v12, output_vec_len ); + case 269: return makeRegisterExpression(amdgpu_gfx908::v13, output_vec_len ); + case 270: return makeRegisterExpression(amdgpu_gfx908::v14, output_vec_len ); + case 271: return makeRegisterExpression(amdgpu_gfx908::v15, output_vec_len ); + case 272: return makeRegisterExpression(amdgpu_gfx908::v16, output_vec_len ); + case 273: return makeRegisterExpression(amdgpu_gfx908::v17, output_vec_len ); + case 274: return makeRegisterExpression(amdgpu_gfx908::v18, output_vec_len ); + case 275: return makeRegisterExpression(amdgpu_gfx908::v19, output_vec_len ); + case 276: return makeRegisterExpression(amdgpu_gfx908::v20, output_vec_len ); + case 277: return makeRegisterExpression(amdgpu_gfx908::v21, output_vec_len ); + case 278: return makeRegisterExpression(amdgpu_gfx908::v22, output_vec_len ); + case 279: return makeRegisterExpression(amdgpu_gfx908::v23, output_vec_len ); + case 280: return makeRegisterExpression(amdgpu_gfx908::v24, output_vec_len ); + case 281: return makeRegisterExpression(amdgpu_gfx908::v25, output_vec_len ); + case 282: return makeRegisterExpression(amdgpu_gfx908::v26, output_vec_len ); + case 283: return makeRegisterExpression(amdgpu_gfx908::v27, output_vec_len ); + case 284: return makeRegisterExpression(amdgpu_gfx908::v28, output_vec_len ); + case 285: return makeRegisterExpression(amdgpu_gfx908::v29, output_vec_len ); + case 286: return makeRegisterExpression(amdgpu_gfx908::v30, output_vec_len ); + case 287: return makeRegisterExpression(amdgpu_gfx908::v31, output_vec_len ); + case 288: return makeRegisterExpression(amdgpu_gfx908::v32, output_vec_len ); + case 289: return makeRegisterExpression(amdgpu_gfx908::v33, output_vec_len ); + case 290: return makeRegisterExpression(amdgpu_gfx908::v34, output_vec_len ); + case 291: return makeRegisterExpression(amdgpu_gfx908::v35, output_vec_len ); + case 292: return makeRegisterExpression(amdgpu_gfx908::v36, output_vec_len ); + case 293: return makeRegisterExpression(amdgpu_gfx908::v37, output_vec_len ); + case 294: return makeRegisterExpression(amdgpu_gfx908::v38, output_vec_len ); + case 295: return makeRegisterExpression(amdgpu_gfx908::v39, output_vec_len ); + case 296: return makeRegisterExpression(amdgpu_gfx908::v40, output_vec_len ); + case 297: return makeRegisterExpression(amdgpu_gfx908::v41, output_vec_len ); + case 298: return makeRegisterExpression(amdgpu_gfx908::v42, output_vec_len ); + case 299: return makeRegisterExpression(amdgpu_gfx908::v43, output_vec_len ); + case 300: return makeRegisterExpression(amdgpu_gfx908::v44, output_vec_len ); + case 301: return makeRegisterExpression(amdgpu_gfx908::v45, output_vec_len ); + case 302: return makeRegisterExpression(amdgpu_gfx908::v46, output_vec_len ); + case 303: return makeRegisterExpression(amdgpu_gfx908::v47, output_vec_len ); + case 304: return makeRegisterExpression(amdgpu_gfx908::v48, output_vec_len ); + case 305: return makeRegisterExpression(amdgpu_gfx908::v49, output_vec_len ); + case 306: return makeRegisterExpression(amdgpu_gfx908::v50, output_vec_len ); + case 307: return makeRegisterExpression(amdgpu_gfx908::v51, output_vec_len ); + case 308: return makeRegisterExpression(amdgpu_gfx908::v52, output_vec_len ); + case 309: return makeRegisterExpression(amdgpu_gfx908::v53, output_vec_len ); + case 310: return makeRegisterExpression(amdgpu_gfx908::v54, output_vec_len ); + case 311: return makeRegisterExpression(amdgpu_gfx908::v55, output_vec_len ); + case 312: return makeRegisterExpression(amdgpu_gfx908::v56, output_vec_len ); + case 313: return makeRegisterExpression(amdgpu_gfx908::v57, output_vec_len ); + case 314: return makeRegisterExpression(amdgpu_gfx908::v58, output_vec_len ); + case 315: return makeRegisterExpression(amdgpu_gfx908::v59, output_vec_len ); + case 316: return makeRegisterExpression(amdgpu_gfx908::v60, output_vec_len ); + case 317: return makeRegisterExpression(amdgpu_gfx908::v61, output_vec_len ); + case 318: return makeRegisterExpression(amdgpu_gfx908::v62, output_vec_len ); + case 319: return makeRegisterExpression(amdgpu_gfx908::v63, output_vec_len ); + case 320: return makeRegisterExpression(amdgpu_gfx908::v64, output_vec_len ); + case 321: return makeRegisterExpression(amdgpu_gfx908::v65, output_vec_len ); + case 322: return makeRegisterExpression(amdgpu_gfx908::v66, output_vec_len ); + case 323: return makeRegisterExpression(amdgpu_gfx908::v67, output_vec_len ); + case 324: return makeRegisterExpression(amdgpu_gfx908::v68, output_vec_len ); + case 325: return makeRegisterExpression(amdgpu_gfx908::v69, output_vec_len ); + case 326: return makeRegisterExpression(amdgpu_gfx908::v70, output_vec_len ); + case 327: return makeRegisterExpression(amdgpu_gfx908::v71, output_vec_len ); + case 328: return makeRegisterExpression(amdgpu_gfx908::v72, output_vec_len ); + case 329: return makeRegisterExpression(amdgpu_gfx908::v73, output_vec_len ); + case 330: return makeRegisterExpression(amdgpu_gfx908::v74, output_vec_len ); + case 331: return makeRegisterExpression(amdgpu_gfx908::v75, output_vec_len ); + case 332: return makeRegisterExpression(amdgpu_gfx908::v76, output_vec_len ); + case 333: return makeRegisterExpression(amdgpu_gfx908::v77, output_vec_len ); + case 334: return makeRegisterExpression(amdgpu_gfx908::v78, output_vec_len ); + case 335: return makeRegisterExpression(amdgpu_gfx908::v79, output_vec_len ); + case 336: return makeRegisterExpression(amdgpu_gfx908::v80, output_vec_len ); + case 337: return makeRegisterExpression(amdgpu_gfx908::v81, output_vec_len ); + case 338: return makeRegisterExpression(amdgpu_gfx908::v82, output_vec_len ); + case 339: return makeRegisterExpression(amdgpu_gfx908::v83, output_vec_len ); + case 340: return makeRegisterExpression(amdgpu_gfx908::v84, output_vec_len ); + case 341: return makeRegisterExpression(amdgpu_gfx908::v85, output_vec_len ); + case 342: return makeRegisterExpression(amdgpu_gfx908::v86, output_vec_len ); + case 343: return makeRegisterExpression(amdgpu_gfx908::v87, output_vec_len ); + case 344: return makeRegisterExpression(amdgpu_gfx908::v88, output_vec_len ); + case 345: return makeRegisterExpression(amdgpu_gfx908::v89, output_vec_len ); + case 346: return makeRegisterExpression(amdgpu_gfx908::v90, output_vec_len ); + case 347: return makeRegisterExpression(amdgpu_gfx908::v91, output_vec_len ); + case 348: return makeRegisterExpression(amdgpu_gfx908::v92, output_vec_len ); + case 349: return makeRegisterExpression(amdgpu_gfx908::v93, output_vec_len ); + case 350: return makeRegisterExpression(amdgpu_gfx908::v94, output_vec_len ); + case 351: return makeRegisterExpression(amdgpu_gfx908::v95, output_vec_len ); + case 352: return makeRegisterExpression(amdgpu_gfx908::v96, output_vec_len ); + case 353: return makeRegisterExpression(amdgpu_gfx908::v97, output_vec_len ); + case 354: return makeRegisterExpression(amdgpu_gfx908::v98, output_vec_len ); + case 355: return makeRegisterExpression(amdgpu_gfx908::v99, output_vec_len ); + case 356: return makeRegisterExpression(amdgpu_gfx908::v100, output_vec_len ); + case 357: return makeRegisterExpression(amdgpu_gfx908::v101, output_vec_len ); + case 358: return makeRegisterExpression(amdgpu_gfx908::v102, output_vec_len ); + case 359: return makeRegisterExpression(amdgpu_gfx908::v103, output_vec_len ); + case 360: return makeRegisterExpression(amdgpu_gfx908::v104, output_vec_len ); + case 361: return makeRegisterExpression(amdgpu_gfx908::v105, output_vec_len ); + case 362: return makeRegisterExpression(amdgpu_gfx908::v106, output_vec_len ); + case 363: return makeRegisterExpression(amdgpu_gfx908::v107, output_vec_len ); + case 364: return makeRegisterExpression(amdgpu_gfx908::v108, output_vec_len ); + case 365: return makeRegisterExpression(amdgpu_gfx908::v109, output_vec_len ); + case 366: return makeRegisterExpression(amdgpu_gfx908::v110, output_vec_len ); + case 367: return makeRegisterExpression(amdgpu_gfx908::v111, output_vec_len ); + case 368: return makeRegisterExpression(amdgpu_gfx908::v112, output_vec_len ); + case 369: return makeRegisterExpression(amdgpu_gfx908::v113, output_vec_len ); + case 370: return makeRegisterExpression(amdgpu_gfx908::v114, output_vec_len ); + case 371: return makeRegisterExpression(amdgpu_gfx908::v115, output_vec_len ); + case 372: return makeRegisterExpression(amdgpu_gfx908::v116, output_vec_len ); + case 373: return makeRegisterExpression(amdgpu_gfx908::v117, output_vec_len ); + case 374: return makeRegisterExpression(amdgpu_gfx908::v118, output_vec_len ); + case 375: return makeRegisterExpression(amdgpu_gfx908::v119, output_vec_len ); + case 376: return makeRegisterExpression(amdgpu_gfx908::v120, output_vec_len ); + case 377: return makeRegisterExpression(amdgpu_gfx908::v121, output_vec_len ); + case 378: return makeRegisterExpression(amdgpu_gfx908::v122, output_vec_len ); + case 379: return makeRegisterExpression(amdgpu_gfx908::v123, output_vec_len ); + case 380: return makeRegisterExpression(amdgpu_gfx908::v124, output_vec_len ); + case 381: return makeRegisterExpression(amdgpu_gfx908::v125, output_vec_len ); + case 382: return makeRegisterExpression(amdgpu_gfx908::v126, output_vec_len ); + case 383: return makeRegisterExpression(amdgpu_gfx908::v127, output_vec_len ); + case 384: return makeRegisterExpression(amdgpu_gfx908::v128, output_vec_len ); + case 385: return makeRegisterExpression(amdgpu_gfx908::v129, output_vec_len ); + case 386: return makeRegisterExpression(amdgpu_gfx908::v130, output_vec_len ); + case 387: return makeRegisterExpression(amdgpu_gfx908::v131, output_vec_len ); + case 388: return makeRegisterExpression(amdgpu_gfx908::v132, output_vec_len ); + case 389: return makeRegisterExpression(amdgpu_gfx908::v133, output_vec_len ); + case 390: return makeRegisterExpression(amdgpu_gfx908::v134, output_vec_len ); + case 391: return makeRegisterExpression(amdgpu_gfx908::v135, output_vec_len ); + case 392: return makeRegisterExpression(amdgpu_gfx908::v136, output_vec_len ); + case 393: return makeRegisterExpression(amdgpu_gfx908::v137, output_vec_len ); + case 394: return makeRegisterExpression(amdgpu_gfx908::v138, output_vec_len ); + case 395: return makeRegisterExpression(amdgpu_gfx908::v139, output_vec_len ); + case 396: return makeRegisterExpression(amdgpu_gfx908::v140, output_vec_len ); + case 397: return makeRegisterExpression(amdgpu_gfx908::v141, output_vec_len ); + case 398: return makeRegisterExpression(amdgpu_gfx908::v142, output_vec_len ); + case 399: return makeRegisterExpression(amdgpu_gfx908::v143, output_vec_len ); + case 400: return makeRegisterExpression(amdgpu_gfx908::v144, output_vec_len ); + case 401: return makeRegisterExpression(amdgpu_gfx908::v145, output_vec_len ); + case 402: return makeRegisterExpression(amdgpu_gfx908::v146, output_vec_len ); + case 403: return makeRegisterExpression(amdgpu_gfx908::v147, output_vec_len ); + case 404: return makeRegisterExpression(amdgpu_gfx908::v148, output_vec_len ); + case 405: return makeRegisterExpression(amdgpu_gfx908::v149, output_vec_len ); + case 406: return makeRegisterExpression(amdgpu_gfx908::v150, output_vec_len ); + case 407: return makeRegisterExpression(amdgpu_gfx908::v151, output_vec_len ); + case 408: return makeRegisterExpression(amdgpu_gfx908::v152, output_vec_len ); + case 409: return makeRegisterExpression(amdgpu_gfx908::v153, output_vec_len ); + case 410: return makeRegisterExpression(amdgpu_gfx908::v154, output_vec_len ); + case 411: return makeRegisterExpression(amdgpu_gfx908::v155, output_vec_len ); + case 412: return makeRegisterExpression(amdgpu_gfx908::v156, output_vec_len ); + case 413: return makeRegisterExpression(amdgpu_gfx908::v157, output_vec_len ); + case 414: return makeRegisterExpression(amdgpu_gfx908::v158, output_vec_len ); + case 415: return makeRegisterExpression(amdgpu_gfx908::v159, output_vec_len ); + case 416: return makeRegisterExpression(amdgpu_gfx908::v160, output_vec_len ); + case 417: return makeRegisterExpression(amdgpu_gfx908::v161, output_vec_len ); + case 418: return makeRegisterExpression(amdgpu_gfx908::v162, output_vec_len ); + case 419: return makeRegisterExpression(amdgpu_gfx908::v163, output_vec_len ); + case 420: return makeRegisterExpression(amdgpu_gfx908::v164, output_vec_len ); + case 421: return makeRegisterExpression(amdgpu_gfx908::v165, output_vec_len ); + case 422: return makeRegisterExpression(amdgpu_gfx908::v166, output_vec_len ); + case 423: return makeRegisterExpression(amdgpu_gfx908::v167, output_vec_len ); + case 424: return makeRegisterExpression(amdgpu_gfx908::v168, output_vec_len ); + case 425: return makeRegisterExpression(amdgpu_gfx908::v169, output_vec_len ); + case 426: return makeRegisterExpression(amdgpu_gfx908::v170, output_vec_len ); + case 427: return makeRegisterExpression(amdgpu_gfx908::v171, output_vec_len ); + case 428: return makeRegisterExpression(amdgpu_gfx908::v172, output_vec_len ); + case 429: return makeRegisterExpression(amdgpu_gfx908::v173, output_vec_len ); + case 430: return makeRegisterExpression(amdgpu_gfx908::v174, output_vec_len ); + case 431: return makeRegisterExpression(amdgpu_gfx908::v175, output_vec_len ); + case 432: return makeRegisterExpression(amdgpu_gfx908::v176, output_vec_len ); + case 433: return makeRegisterExpression(amdgpu_gfx908::v177, output_vec_len ); + case 434: return makeRegisterExpression(amdgpu_gfx908::v178, output_vec_len ); + case 435: return makeRegisterExpression(amdgpu_gfx908::v179, output_vec_len ); + case 436: return makeRegisterExpression(amdgpu_gfx908::v180, output_vec_len ); + case 437: return makeRegisterExpression(amdgpu_gfx908::v181, output_vec_len ); + case 438: return makeRegisterExpression(amdgpu_gfx908::v182, output_vec_len ); + case 439: return makeRegisterExpression(amdgpu_gfx908::v183, output_vec_len ); + case 440: return makeRegisterExpression(amdgpu_gfx908::v184, output_vec_len ); + case 441: return makeRegisterExpression(amdgpu_gfx908::v185, output_vec_len ); + case 442: return makeRegisterExpression(amdgpu_gfx908::v186, output_vec_len ); + case 443: return makeRegisterExpression(amdgpu_gfx908::v187, output_vec_len ); + case 444: return makeRegisterExpression(amdgpu_gfx908::v188, output_vec_len ); + case 445: return makeRegisterExpression(amdgpu_gfx908::v189, output_vec_len ); + case 446: return makeRegisterExpression(amdgpu_gfx908::v190, output_vec_len ); + case 447: return makeRegisterExpression(amdgpu_gfx908::v191, output_vec_len ); + case 448: return makeRegisterExpression(amdgpu_gfx908::v192, output_vec_len ); + case 449: return makeRegisterExpression(amdgpu_gfx908::v193, output_vec_len ); + case 450: return makeRegisterExpression(amdgpu_gfx908::v194, output_vec_len ); + case 451: return makeRegisterExpression(amdgpu_gfx908::v195, output_vec_len ); + case 452: return makeRegisterExpression(amdgpu_gfx908::v196, output_vec_len ); + case 453: return makeRegisterExpression(amdgpu_gfx908::v197, output_vec_len ); + case 454: return makeRegisterExpression(amdgpu_gfx908::v198, output_vec_len ); + case 455: return makeRegisterExpression(amdgpu_gfx908::v199, output_vec_len ); + case 456: return makeRegisterExpression(amdgpu_gfx908::v200, output_vec_len ); + case 457: return makeRegisterExpression(amdgpu_gfx908::v201, output_vec_len ); + case 458: return makeRegisterExpression(amdgpu_gfx908::v202, output_vec_len ); + case 459: return makeRegisterExpression(amdgpu_gfx908::v203, output_vec_len ); + case 460: return makeRegisterExpression(amdgpu_gfx908::v204, output_vec_len ); + case 461: return makeRegisterExpression(amdgpu_gfx908::v205, output_vec_len ); + case 462: return makeRegisterExpression(amdgpu_gfx908::v206, output_vec_len ); + case 463: return makeRegisterExpression(amdgpu_gfx908::v207, output_vec_len ); + case 464: return makeRegisterExpression(amdgpu_gfx908::v208, output_vec_len ); + case 465: return makeRegisterExpression(amdgpu_gfx908::v209, output_vec_len ); + case 466: return makeRegisterExpression(amdgpu_gfx908::v210, output_vec_len ); + case 467: return makeRegisterExpression(amdgpu_gfx908::v211, output_vec_len ); + case 468: return makeRegisterExpression(amdgpu_gfx908::v212, output_vec_len ); + case 469: return makeRegisterExpression(amdgpu_gfx908::v213, output_vec_len ); + case 470: return makeRegisterExpression(amdgpu_gfx908::v214, output_vec_len ); + case 471: return makeRegisterExpression(amdgpu_gfx908::v215, output_vec_len ); + case 472: return makeRegisterExpression(amdgpu_gfx908::v216, output_vec_len ); + case 473: return makeRegisterExpression(amdgpu_gfx908::v217, output_vec_len ); + case 474: return makeRegisterExpression(amdgpu_gfx908::v218, output_vec_len ); + case 475: return makeRegisterExpression(amdgpu_gfx908::v219, output_vec_len ); + case 476: return makeRegisterExpression(amdgpu_gfx908::v220, output_vec_len ); + case 477: return makeRegisterExpression(amdgpu_gfx908::v221, output_vec_len ); + case 478: return makeRegisterExpression(amdgpu_gfx908::v222, output_vec_len ); + case 479: return makeRegisterExpression(amdgpu_gfx908::v223, output_vec_len ); + case 480: return makeRegisterExpression(amdgpu_gfx908::v224, output_vec_len ); + case 481: return makeRegisterExpression(amdgpu_gfx908::v225, output_vec_len ); + case 482: return makeRegisterExpression(amdgpu_gfx908::v226, output_vec_len ); + case 483: return makeRegisterExpression(amdgpu_gfx908::v227, output_vec_len ); + case 484: return makeRegisterExpression(amdgpu_gfx908::v228, output_vec_len ); + case 485: return makeRegisterExpression(amdgpu_gfx908::v229, output_vec_len ); + case 486: return makeRegisterExpression(amdgpu_gfx908::v230, output_vec_len ); + case 487: return makeRegisterExpression(amdgpu_gfx908::v231, output_vec_len ); + case 488: return makeRegisterExpression(amdgpu_gfx908::v232, output_vec_len ); + case 489: return makeRegisterExpression(amdgpu_gfx908::v233, output_vec_len ); + case 490: return makeRegisterExpression(amdgpu_gfx908::v234, output_vec_len ); + case 491: return makeRegisterExpression(amdgpu_gfx908::v235, output_vec_len ); + case 492: return makeRegisterExpression(amdgpu_gfx908::v236, output_vec_len ); + case 493: return makeRegisterExpression(amdgpu_gfx908::v237, output_vec_len ); + case 494: return makeRegisterExpression(amdgpu_gfx908::v238, output_vec_len ); + case 495: return makeRegisterExpression(amdgpu_gfx908::v239, output_vec_len ); + case 496: return makeRegisterExpression(amdgpu_gfx908::v240, output_vec_len ); + case 497: return makeRegisterExpression(amdgpu_gfx908::v241, output_vec_len ); + case 498: return makeRegisterExpression(amdgpu_gfx908::v242, output_vec_len ); + case 499: return makeRegisterExpression(amdgpu_gfx908::v243, output_vec_len ); + case 500: return makeRegisterExpression(amdgpu_gfx908::v244, output_vec_len ); + case 501: return makeRegisterExpression(amdgpu_gfx908::v245, output_vec_len ); + case 502: return makeRegisterExpression(amdgpu_gfx908::v246, output_vec_len ); + case 503: return makeRegisterExpression(amdgpu_gfx908::v247, output_vec_len ); + case 504: return makeRegisterExpression(amdgpu_gfx908::v248, output_vec_len ); + case 505: return makeRegisterExpression(amdgpu_gfx908::v249, output_vec_len ); + case 506: return makeRegisterExpression(amdgpu_gfx908::v250, output_vec_len ); + case 507: return makeRegisterExpression(amdgpu_gfx908::v251, output_vec_len ); + case 508: return makeRegisterExpression(amdgpu_gfx908::v252, output_vec_len ); + case 509: return makeRegisterExpression(amdgpu_gfx908::v253, output_vec_len ); + case 510: return makeRegisterExpression(amdgpu_gfx908::v254, output_vec_len ); + case 511: return makeRegisterExpression(amdgpu_gfx908::v255, output_vec_len ); + case 255: return Immediate::makeImmediate(Result(u32,decodeOPR_LITERAL())); + case 249 : return decodeOPR_SDWA(); + default: return makeRegisterExpression(amdgpu_gfx908::invalid); + } + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SRC_NOLIT(uint64_t input, uint32_t output_vec_len) + { + switch (input) { + case 0: return makeRegisterExpression(amdgpu_gfx908::s0, output_vec_len ); + case 1: return makeRegisterExpression(amdgpu_gfx908::s1, output_vec_len ); + case 2: return makeRegisterExpression(amdgpu_gfx908::s2, output_vec_len ); + case 3: return makeRegisterExpression(amdgpu_gfx908::s3, output_vec_len ); + case 4: return makeRegisterExpression(amdgpu_gfx908::s4, output_vec_len ); + case 5: return makeRegisterExpression(amdgpu_gfx908::s5, output_vec_len ); + case 6: return makeRegisterExpression(amdgpu_gfx908::s6, output_vec_len ); + case 7: return makeRegisterExpression(amdgpu_gfx908::s7, output_vec_len ); + case 8: return makeRegisterExpression(amdgpu_gfx908::s8, output_vec_len ); + case 9: return makeRegisterExpression(amdgpu_gfx908::s9, output_vec_len ); + case 10: return makeRegisterExpression(amdgpu_gfx908::s10, output_vec_len ); + case 11: return makeRegisterExpression(amdgpu_gfx908::s11, output_vec_len ); + case 12: return makeRegisterExpression(amdgpu_gfx908::s12, output_vec_len ); + case 13: return makeRegisterExpression(amdgpu_gfx908::s13, output_vec_len ); + case 14: return makeRegisterExpression(amdgpu_gfx908::s14, output_vec_len ); + case 15: return makeRegisterExpression(amdgpu_gfx908::s15, output_vec_len ); + case 16: return makeRegisterExpression(amdgpu_gfx908::s16, output_vec_len ); + case 17: return makeRegisterExpression(amdgpu_gfx908::s17, output_vec_len ); + case 18: return makeRegisterExpression(amdgpu_gfx908::s18, output_vec_len ); + case 19: return makeRegisterExpression(amdgpu_gfx908::s19, output_vec_len ); + case 20: return makeRegisterExpression(amdgpu_gfx908::s20, output_vec_len ); + case 21: return makeRegisterExpression(amdgpu_gfx908::s21, output_vec_len ); + case 22: return makeRegisterExpression(amdgpu_gfx908::s22, output_vec_len ); + case 23: return makeRegisterExpression(amdgpu_gfx908::s23, output_vec_len ); + case 24: return makeRegisterExpression(amdgpu_gfx908::s24, output_vec_len ); + case 25: return makeRegisterExpression(amdgpu_gfx908::s25, output_vec_len ); + case 26: return makeRegisterExpression(amdgpu_gfx908::s26, output_vec_len ); + case 27: return makeRegisterExpression(amdgpu_gfx908::s27, output_vec_len ); + case 28: return makeRegisterExpression(amdgpu_gfx908::s28, output_vec_len ); + case 29: return makeRegisterExpression(amdgpu_gfx908::s29, output_vec_len ); + case 30: return makeRegisterExpression(amdgpu_gfx908::s30, output_vec_len ); + case 31: return makeRegisterExpression(amdgpu_gfx908::s31, output_vec_len ); + case 32: return makeRegisterExpression(amdgpu_gfx908::s32, output_vec_len ); + case 33: return makeRegisterExpression(amdgpu_gfx908::s33, output_vec_len ); + case 34: return makeRegisterExpression(amdgpu_gfx908::s34, output_vec_len ); + case 35: return makeRegisterExpression(amdgpu_gfx908::s35, output_vec_len ); + case 36: return makeRegisterExpression(amdgpu_gfx908::s36, output_vec_len ); + case 37: return makeRegisterExpression(amdgpu_gfx908::s37, output_vec_len ); + case 38: return makeRegisterExpression(amdgpu_gfx908::s38, output_vec_len ); + case 39: return makeRegisterExpression(amdgpu_gfx908::s39, output_vec_len ); + case 40: return makeRegisterExpression(amdgpu_gfx908::s40, output_vec_len ); + case 41: return makeRegisterExpression(amdgpu_gfx908::s41, output_vec_len ); + case 42: return makeRegisterExpression(amdgpu_gfx908::s42, output_vec_len ); + case 43: return makeRegisterExpression(amdgpu_gfx908::s43, output_vec_len ); + case 44: return makeRegisterExpression(amdgpu_gfx908::s44, output_vec_len ); + case 45: return makeRegisterExpression(amdgpu_gfx908::s45, output_vec_len ); + case 46: return makeRegisterExpression(amdgpu_gfx908::s46, output_vec_len ); + case 47: return makeRegisterExpression(amdgpu_gfx908::s47, output_vec_len ); + case 48: return makeRegisterExpression(amdgpu_gfx908::s48, output_vec_len ); + case 49: return makeRegisterExpression(amdgpu_gfx908::s49, output_vec_len ); + case 50: return makeRegisterExpression(amdgpu_gfx908::s50, output_vec_len ); + case 51: return makeRegisterExpression(amdgpu_gfx908::s51, output_vec_len ); + case 52: return makeRegisterExpression(amdgpu_gfx908::s52, output_vec_len ); + case 53: return makeRegisterExpression(amdgpu_gfx908::s53, output_vec_len ); + case 54: return makeRegisterExpression(amdgpu_gfx908::s54, output_vec_len ); + case 55: return makeRegisterExpression(amdgpu_gfx908::s55, output_vec_len ); + case 56: return makeRegisterExpression(amdgpu_gfx908::s56, output_vec_len ); + case 57: return makeRegisterExpression(amdgpu_gfx908::s57, output_vec_len ); + case 58: return makeRegisterExpression(amdgpu_gfx908::s58, output_vec_len ); + case 59: return makeRegisterExpression(amdgpu_gfx908::s59, output_vec_len ); + case 60: return makeRegisterExpression(amdgpu_gfx908::s60, output_vec_len ); + case 61: return makeRegisterExpression(amdgpu_gfx908::s61, output_vec_len ); + case 62: return makeRegisterExpression(amdgpu_gfx908::s62, output_vec_len ); + case 63: return makeRegisterExpression(amdgpu_gfx908::s63, output_vec_len ); + case 64: return makeRegisterExpression(amdgpu_gfx908::s64, output_vec_len ); + case 65: return makeRegisterExpression(amdgpu_gfx908::s65, output_vec_len ); + case 66: return makeRegisterExpression(amdgpu_gfx908::s66, output_vec_len ); + case 67: return makeRegisterExpression(amdgpu_gfx908::s67, output_vec_len ); + case 68: return makeRegisterExpression(amdgpu_gfx908::s68, output_vec_len ); + case 69: return makeRegisterExpression(amdgpu_gfx908::s69, output_vec_len ); + case 70: return makeRegisterExpression(amdgpu_gfx908::s70, output_vec_len ); + case 71: return makeRegisterExpression(amdgpu_gfx908::s71, output_vec_len ); + case 72: return makeRegisterExpression(amdgpu_gfx908::s72, output_vec_len ); + case 73: return makeRegisterExpression(amdgpu_gfx908::s73, output_vec_len ); + case 74: return makeRegisterExpression(amdgpu_gfx908::s74, output_vec_len ); + case 75: return makeRegisterExpression(amdgpu_gfx908::s75, output_vec_len ); + case 76: return makeRegisterExpression(amdgpu_gfx908::s76, output_vec_len ); + case 77: return makeRegisterExpression(amdgpu_gfx908::s77, output_vec_len ); + case 78: return makeRegisterExpression(amdgpu_gfx908::s78, output_vec_len ); + case 79: return makeRegisterExpression(amdgpu_gfx908::s79, output_vec_len ); + case 80: return makeRegisterExpression(amdgpu_gfx908::s80, output_vec_len ); + case 81: return makeRegisterExpression(amdgpu_gfx908::s81, output_vec_len ); + case 82: return makeRegisterExpression(amdgpu_gfx908::s82, output_vec_len ); + case 83: return makeRegisterExpression(amdgpu_gfx908::s83, output_vec_len ); + case 84: return makeRegisterExpression(amdgpu_gfx908::s84, output_vec_len ); + case 85: return makeRegisterExpression(amdgpu_gfx908::s85, output_vec_len ); + case 86: return makeRegisterExpression(amdgpu_gfx908::s86, output_vec_len ); + case 87: return makeRegisterExpression(amdgpu_gfx908::s87, output_vec_len ); + case 88: return makeRegisterExpression(amdgpu_gfx908::s88, output_vec_len ); + case 89: return makeRegisterExpression(amdgpu_gfx908::s89, output_vec_len ); + case 90: return makeRegisterExpression(amdgpu_gfx908::s90, output_vec_len ); + case 91: return makeRegisterExpression(amdgpu_gfx908::s91, output_vec_len ); + case 92: return makeRegisterExpression(amdgpu_gfx908::s92, output_vec_len ); + case 93: return makeRegisterExpression(amdgpu_gfx908::s93, output_vec_len ); + case 94: return makeRegisterExpression(amdgpu_gfx908::s94, output_vec_len ); + case 95: return makeRegisterExpression(amdgpu_gfx908::s95, output_vec_len ); + case 96: return makeRegisterExpression(amdgpu_gfx908::s96, output_vec_len ); + case 97: return makeRegisterExpression(amdgpu_gfx908::s97, output_vec_len ); + case 98: return makeRegisterExpression(amdgpu_gfx908::s98, output_vec_len ); + case 99: return makeRegisterExpression(amdgpu_gfx908::s99, output_vec_len ); + case 100: return makeRegisterExpression(amdgpu_gfx908::s100, output_vec_len ); + case 101: return makeRegisterExpression(amdgpu_gfx908::s101, output_vec_len ); + case 104: return makeRegisterExpression(amdgpu_gfx908::xnack_mask_lo, output_vec_len ); + case 105: return makeRegisterExpression(amdgpu_gfx908::xnack_mask_hi, output_vec_len ); + case 102: return makeRegisterExpression(amdgpu_gfx908::flat_scratch_lo, output_vec_len ); + case 103: return makeRegisterExpression(amdgpu_gfx908::flat_scratch_hi, output_vec_len ); + case 108: return makeRegisterExpression(amdgpu_gfx908::ttmp0, output_vec_len ); + case 109: return makeRegisterExpression(amdgpu_gfx908::ttmp1, output_vec_len ); + case 110: return makeRegisterExpression(amdgpu_gfx908::ttmp2, output_vec_len ); + case 111: return makeRegisterExpression(amdgpu_gfx908::ttmp3, output_vec_len ); + case 112: return makeRegisterExpression(amdgpu_gfx908::ttmp4, output_vec_len ); + case 113: return makeRegisterExpression(amdgpu_gfx908::ttmp5, output_vec_len ); + case 114: return makeRegisterExpression(amdgpu_gfx908::ttmp6, output_vec_len ); + case 115: return makeRegisterExpression(amdgpu_gfx908::ttmp7, output_vec_len ); + case 116: return makeRegisterExpression(amdgpu_gfx908::ttmp8, output_vec_len ); + case 117: return makeRegisterExpression(amdgpu_gfx908::ttmp9, output_vec_len ); + case 118: return makeRegisterExpression(amdgpu_gfx908::ttmp10, output_vec_len ); + case 119: return makeRegisterExpression(amdgpu_gfx908::ttmp11, output_vec_len ); + case 120: return makeRegisterExpression(amdgpu_gfx908::ttmp12, output_vec_len ); + case 121: return makeRegisterExpression(amdgpu_gfx908::ttmp13, output_vec_len ); + case 122: return makeRegisterExpression(amdgpu_gfx908::ttmp14, output_vec_len ); + case 123: return makeRegisterExpression(amdgpu_gfx908::ttmp15, output_vec_len ); + case 106: return makeRegisterExpression(amdgpu_gfx908::vcc_lo, output_vec_len ); + case 107: return makeRegisterExpression(amdgpu_gfx908::vcc_hi, output_vec_len ); + case 124: return makeRegisterExpression(amdgpu_gfx908::m0, output_vec_len ); + case 126: return makeRegisterExpression(amdgpu_gfx908::exec_lo, output_vec_len ); + case 127: return makeRegisterExpression(amdgpu_gfx908::exec_hi, output_vec_len ); + case 128: return Immediate::makeImmediate(Result(u32, 0)); + case 129: return Immediate::makeImmediate(Result(u32, 1)); + case 130: return Immediate::makeImmediate(Result(u32, 2)); + case 131: return Immediate::makeImmediate(Result(u32, 3)); + case 132: return Immediate::makeImmediate(Result(u32, 4)); + case 133: return Immediate::makeImmediate(Result(u32, 5)); + case 134: return Immediate::makeImmediate(Result(u32, 6)); + case 135: return Immediate::makeImmediate(Result(u32, 7)); + case 136: return Immediate::makeImmediate(Result(u32, 8)); + case 137: return Immediate::makeImmediate(Result(u32, 9)); + case 138: return Immediate::makeImmediate(Result(u32, 10)); + case 139: return Immediate::makeImmediate(Result(u32, 11)); + case 140: return Immediate::makeImmediate(Result(u32, 12)); + case 141: return Immediate::makeImmediate(Result(u32, 13)); + case 142: return Immediate::makeImmediate(Result(u32, 14)); + case 143: return Immediate::makeImmediate(Result(u32, 15)); + case 144: return Immediate::makeImmediate(Result(u32, 16)); + case 145: return Immediate::makeImmediate(Result(u32, 17)); + case 146: return Immediate::makeImmediate(Result(u32, 18)); + case 147: return Immediate::makeImmediate(Result(u32, 19)); + case 148: return Immediate::makeImmediate(Result(u32, 20)); + case 149: return Immediate::makeImmediate(Result(u32, 21)); + case 150: return Immediate::makeImmediate(Result(u32, 22)); + case 151: return Immediate::makeImmediate(Result(u32, 23)); + case 152: return Immediate::makeImmediate(Result(u32, 24)); + case 153: return Immediate::makeImmediate(Result(u32, 25)); + case 154: return Immediate::makeImmediate(Result(u32, 26)); + case 155: return Immediate::makeImmediate(Result(u32, 27)); + case 156: return Immediate::makeImmediate(Result(u32, 28)); + case 157: return Immediate::makeImmediate(Result(u32, 29)); + case 158: return Immediate::makeImmediate(Result(u32, 30)); + case 159: return Immediate::makeImmediate(Result(u32, 31)); + case 160: return Immediate::makeImmediate(Result(u32, 32)); + case 161: return Immediate::makeImmediate(Result(u32, 33)); + case 162: return Immediate::makeImmediate(Result(u32, 34)); + case 163: return Immediate::makeImmediate(Result(u32, 35)); + case 164: return Immediate::makeImmediate(Result(u32, 36)); + case 165: return Immediate::makeImmediate(Result(u32, 37)); + case 166: return Immediate::makeImmediate(Result(u32, 38)); + case 167: return Immediate::makeImmediate(Result(u32, 39)); + case 168: return Immediate::makeImmediate(Result(u32, 40)); + case 169: return Immediate::makeImmediate(Result(u32, 41)); + case 170: return Immediate::makeImmediate(Result(u32, 42)); + case 171: return Immediate::makeImmediate(Result(u32, 43)); + case 172: return Immediate::makeImmediate(Result(u32, 44)); + case 173: return Immediate::makeImmediate(Result(u32, 45)); + case 174: return Immediate::makeImmediate(Result(u32, 46)); + case 175: return Immediate::makeImmediate(Result(u32, 47)); + case 176: return Immediate::makeImmediate(Result(u32, 48)); + case 177: return Immediate::makeImmediate(Result(u32, 49)); + case 178: return Immediate::makeImmediate(Result(u32, 50)); + case 179: return Immediate::makeImmediate(Result(u32, 51)); + case 180: return Immediate::makeImmediate(Result(u32, 52)); + case 181: return Immediate::makeImmediate(Result(u32, 53)); + case 182: return Immediate::makeImmediate(Result(u32, 54)); + case 183: return Immediate::makeImmediate(Result(u32, 55)); + case 184: return Immediate::makeImmediate(Result(u32, 56)); + case 185: return Immediate::makeImmediate(Result(u32, 57)); + case 186: return Immediate::makeImmediate(Result(u32, 58)); + case 187: return Immediate::makeImmediate(Result(u32, 59)); + case 188: return Immediate::makeImmediate(Result(u32, 60)); + case 189: return Immediate::makeImmediate(Result(u32, 61)); + case 190: return Immediate::makeImmediate(Result(u32, 62)); + case 191: return Immediate::makeImmediate(Result(u32, 63)); + case 192: return Immediate::makeImmediate(Result(u32, 64)); + case 193: return Immediate::makeImmediate(Result(u32, -1)); + case 194: return Immediate::makeImmediate(Result(u32, -2)); + case 195: return Immediate::makeImmediate(Result(u32, -3)); + case 196: return Immediate::makeImmediate(Result(u32, -4)); + case 197: return Immediate::makeImmediate(Result(u32, -5)); + case 198: return Immediate::makeImmediate(Result(u32, -6)); + case 199: return Immediate::makeImmediate(Result(u32, -7)); + case 200: return Immediate::makeImmediate(Result(u32, -8)); + case 201: return Immediate::makeImmediate(Result(u32, -9)); + case 202: return Immediate::makeImmediate(Result(u32, -10)); + case 203: return Immediate::makeImmediate(Result(u32, -11)); + case 204: return Immediate::makeImmediate(Result(u32, -12)); + case 205: return Immediate::makeImmediate(Result(u32, -13)); + case 206: return Immediate::makeImmediate(Result(u32, -14)); + case 207: return Immediate::makeImmediate(Result(u32, -15)); + case 208: return Immediate::makeImmediate(Result(u32, -16)); + case 240: return Immediate::makeImmediate(Result(sp_float, 0.5)); + case 241: return Immediate::makeImmediate(Result(sp_float, -0.5)); + case 242: return Immediate::makeImmediate(Result(sp_float, 1.0)); + case 243: return Immediate::makeImmediate(Result(sp_float, -1.0)); + case 244: return Immediate::makeImmediate(Result(sp_float, 2.0)); + case 245: return Immediate::makeImmediate(Result(sp_float, -2.0)); + case 246: return Immediate::makeImmediate(Result(sp_float, 4.0)); + case 247: return Immediate::makeImmediate(Result(sp_float, -4.0)); + case 248: return Immediate::makeImmediate(Result(sp_float, 0.15915494)); + case 251: return makeRegisterExpression(amdgpu_gfx908::src_vccz, output_vec_len ); + case 252: return makeRegisterExpression(amdgpu_gfx908::src_execz, output_vec_len ); + case 253: return makeRegisterExpression(amdgpu_gfx908::src_scc, output_vec_len ); + case 235: return makeRegisterExpression(amdgpu_gfx908::src_shared_base, output_vec_len ); + case 236: return makeRegisterExpression(amdgpu_gfx908::src_shared_limit, output_vec_len ); + case 237: return makeRegisterExpression(amdgpu_gfx908::src_private_base, output_vec_len ); + case 238: return makeRegisterExpression(amdgpu_gfx908::src_private_limit, output_vec_len ); + case 239: return makeRegisterExpression(amdgpu_gfx908::src_pops_exiting_wave_id, output_vec_len ); + case 256: return makeRegisterExpression(amdgpu_gfx908::v0, output_vec_len ); + case 257: return makeRegisterExpression(amdgpu_gfx908::v1, output_vec_len ); + case 258: return makeRegisterExpression(amdgpu_gfx908::v2, output_vec_len ); + case 259: return makeRegisterExpression(amdgpu_gfx908::v3, output_vec_len ); + case 260: return makeRegisterExpression(amdgpu_gfx908::v4, output_vec_len ); + case 261: return makeRegisterExpression(amdgpu_gfx908::v5, output_vec_len ); + case 262: return makeRegisterExpression(amdgpu_gfx908::v6, output_vec_len ); + case 263: return makeRegisterExpression(amdgpu_gfx908::v7, output_vec_len ); + case 264: return makeRegisterExpression(amdgpu_gfx908::v8, output_vec_len ); + case 265: return makeRegisterExpression(amdgpu_gfx908::v9, output_vec_len ); + case 266: return makeRegisterExpression(amdgpu_gfx908::v10, output_vec_len ); + case 267: return makeRegisterExpression(amdgpu_gfx908::v11, output_vec_len ); + case 268: return makeRegisterExpression(amdgpu_gfx908::v12, output_vec_len ); + case 269: return makeRegisterExpression(amdgpu_gfx908::v13, output_vec_len ); + case 270: return makeRegisterExpression(amdgpu_gfx908::v14, output_vec_len ); + case 271: return makeRegisterExpression(amdgpu_gfx908::v15, output_vec_len ); + case 272: return makeRegisterExpression(amdgpu_gfx908::v16, output_vec_len ); + case 273: return makeRegisterExpression(amdgpu_gfx908::v17, output_vec_len ); + case 274: return makeRegisterExpression(amdgpu_gfx908::v18, output_vec_len ); + case 275: return makeRegisterExpression(amdgpu_gfx908::v19, output_vec_len ); + case 276: return makeRegisterExpression(amdgpu_gfx908::v20, output_vec_len ); + case 277: return makeRegisterExpression(amdgpu_gfx908::v21, output_vec_len ); + case 278: return makeRegisterExpression(amdgpu_gfx908::v22, output_vec_len ); + case 279: return makeRegisterExpression(amdgpu_gfx908::v23, output_vec_len ); + case 280: return makeRegisterExpression(amdgpu_gfx908::v24, output_vec_len ); + case 281: return makeRegisterExpression(amdgpu_gfx908::v25, output_vec_len ); + case 282: return makeRegisterExpression(amdgpu_gfx908::v26, output_vec_len ); + case 283: return makeRegisterExpression(amdgpu_gfx908::v27, output_vec_len ); + case 284: return makeRegisterExpression(amdgpu_gfx908::v28, output_vec_len ); + case 285: return makeRegisterExpression(amdgpu_gfx908::v29, output_vec_len ); + case 286: return makeRegisterExpression(amdgpu_gfx908::v30, output_vec_len ); + case 287: return makeRegisterExpression(amdgpu_gfx908::v31, output_vec_len ); + case 288: return makeRegisterExpression(amdgpu_gfx908::v32, output_vec_len ); + case 289: return makeRegisterExpression(amdgpu_gfx908::v33, output_vec_len ); + case 290: return makeRegisterExpression(amdgpu_gfx908::v34, output_vec_len ); + case 291: return makeRegisterExpression(amdgpu_gfx908::v35, output_vec_len ); + case 292: return makeRegisterExpression(amdgpu_gfx908::v36, output_vec_len ); + case 293: return makeRegisterExpression(amdgpu_gfx908::v37, output_vec_len ); + case 294: return makeRegisterExpression(amdgpu_gfx908::v38, output_vec_len ); + case 295: return makeRegisterExpression(amdgpu_gfx908::v39, output_vec_len ); + case 296: return makeRegisterExpression(amdgpu_gfx908::v40, output_vec_len ); + case 297: return makeRegisterExpression(amdgpu_gfx908::v41, output_vec_len ); + case 298: return makeRegisterExpression(amdgpu_gfx908::v42, output_vec_len ); + case 299: return makeRegisterExpression(amdgpu_gfx908::v43, output_vec_len ); + case 300: return makeRegisterExpression(amdgpu_gfx908::v44, output_vec_len ); + case 301: return makeRegisterExpression(amdgpu_gfx908::v45, output_vec_len ); + case 302: return makeRegisterExpression(amdgpu_gfx908::v46, output_vec_len ); + case 303: return makeRegisterExpression(amdgpu_gfx908::v47, output_vec_len ); + case 304: return makeRegisterExpression(amdgpu_gfx908::v48, output_vec_len ); + case 305: return makeRegisterExpression(amdgpu_gfx908::v49, output_vec_len ); + case 306: return makeRegisterExpression(amdgpu_gfx908::v50, output_vec_len ); + case 307: return makeRegisterExpression(amdgpu_gfx908::v51, output_vec_len ); + case 308: return makeRegisterExpression(amdgpu_gfx908::v52, output_vec_len ); + case 309: return makeRegisterExpression(amdgpu_gfx908::v53, output_vec_len ); + case 310: return makeRegisterExpression(amdgpu_gfx908::v54, output_vec_len ); + case 311: return makeRegisterExpression(amdgpu_gfx908::v55, output_vec_len ); + case 312: return makeRegisterExpression(amdgpu_gfx908::v56, output_vec_len ); + case 313: return makeRegisterExpression(amdgpu_gfx908::v57, output_vec_len ); + case 314: return makeRegisterExpression(amdgpu_gfx908::v58, output_vec_len ); + case 315: return makeRegisterExpression(amdgpu_gfx908::v59, output_vec_len ); + case 316: return makeRegisterExpression(amdgpu_gfx908::v60, output_vec_len ); + case 317: return makeRegisterExpression(amdgpu_gfx908::v61, output_vec_len ); + case 318: return makeRegisterExpression(amdgpu_gfx908::v62, output_vec_len ); + case 319: return makeRegisterExpression(amdgpu_gfx908::v63, output_vec_len ); + case 320: return makeRegisterExpression(amdgpu_gfx908::v64, output_vec_len ); + case 321: return makeRegisterExpression(amdgpu_gfx908::v65, output_vec_len ); + case 322: return makeRegisterExpression(amdgpu_gfx908::v66, output_vec_len ); + case 323: return makeRegisterExpression(amdgpu_gfx908::v67, output_vec_len ); + case 324: return makeRegisterExpression(amdgpu_gfx908::v68, output_vec_len ); + case 325: return makeRegisterExpression(amdgpu_gfx908::v69, output_vec_len ); + case 326: return makeRegisterExpression(amdgpu_gfx908::v70, output_vec_len ); + case 327: return makeRegisterExpression(amdgpu_gfx908::v71, output_vec_len ); + case 328: return makeRegisterExpression(amdgpu_gfx908::v72, output_vec_len ); + case 329: return makeRegisterExpression(amdgpu_gfx908::v73, output_vec_len ); + case 330: return makeRegisterExpression(amdgpu_gfx908::v74, output_vec_len ); + case 331: return makeRegisterExpression(amdgpu_gfx908::v75, output_vec_len ); + case 332: return makeRegisterExpression(amdgpu_gfx908::v76, output_vec_len ); + case 333: return makeRegisterExpression(amdgpu_gfx908::v77, output_vec_len ); + case 334: return makeRegisterExpression(amdgpu_gfx908::v78, output_vec_len ); + case 335: return makeRegisterExpression(amdgpu_gfx908::v79, output_vec_len ); + case 336: return makeRegisterExpression(amdgpu_gfx908::v80, output_vec_len ); + case 337: return makeRegisterExpression(amdgpu_gfx908::v81, output_vec_len ); + case 338: return makeRegisterExpression(amdgpu_gfx908::v82, output_vec_len ); + case 339: return makeRegisterExpression(amdgpu_gfx908::v83, output_vec_len ); + case 340: return makeRegisterExpression(amdgpu_gfx908::v84, output_vec_len ); + case 341: return makeRegisterExpression(amdgpu_gfx908::v85, output_vec_len ); + case 342: return makeRegisterExpression(amdgpu_gfx908::v86, output_vec_len ); + case 343: return makeRegisterExpression(amdgpu_gfx908::v87, output_vec_len ); + case 344: return makeRegisterExpression(amdgpu_gfx908::v88, output_vec_len ); + case 345: return makeRegisterExpression(amdgpu_gfx908::v89, output_vec_len ); + case 346: return makeRegisterExpression(amdgpu_gfx908::v90, output_vec_len ); + case 347: return makeRegisterExpression(amdgpu_gfx908::v91, output_vec_len ); + case 348: return makeRegisterExpression(amdgpu_gfx908::v92, output_vec_len ); + case 349: return makeRegisterExpression(amdgpu_gfx908::v93, output_vec_len ); + case 350: return makeRegisterExpression(amdgpu_gfx908::v94, output_vec_len ); + case 351: return makeRegisterExpression(amdgpu_gfx908::v95, output_vec_len ); + case 352: return makeRegisterExpression(amdgpu_gfx908::v96, output_vec_len ); + case 353: return makeRegisterExpression(amdgpu_gfx908::v97, output_vec_len ); + case 354: return makeRegisterExpression(amdgpu_gfx908::v98, output_vec_len ); + case 355: return makeRegisterExpression(amdgpu_gfx908::v99, output_vec_len ); + case 356: return makeRegisterExpression(amdgpu_gfx908::v100, output_vec_len ); + case 357: return makeRegisterExpression(amdgpu_gfx908::v101, output_vec_len ); + case 358: return makeRegisterExpression(amdgpu_gfx908::v102, output_vec_len ); + case 359: return makeRegisterExpression(amdgpu_gfx908::v103, output_vec_len ); + case 360: return makeRegisterExpression(amdgpu_gfx908::v104, output_vec_len ); + case 361: return makeRegisterExpression(amdgpu_gfx908::v105, output_vec_len ); + case 362: return makeRegisterExpression(amdgpu_gfx908::v106, output_vec_len ); + case 363: return makeRegisterExpression(amdgpu_gfx908::v107, output_vec_len ); + case 364: return makeRegisterExpression(amdgpu_gfx908::v108, output_vec_len ); + case 365: return makeRegisterExpression(amdgpu_gfx908::v109, output_vec_len ); + case 366: return makeRegisterExpression(amdgpu_gfx908::v110, output_vec_len ); + case 367: return makeRegisterExpression(amdgpu_gfx908::v111, output_vec_len ); + case 368: return makeRegisterExpression(amdgpu_gfx908::v112, output_vec_len ); + case 369: return makeRegisterExpression(amdgpu_gfx908::v113, output_vec_len ); + case 370: return makeRegisterExpression(amdgpu_gfx908::v114, output_vec_len ); + case 371: return makeRegisterExpression(amdgpu_gfx908::v115, output_vec_len ); + case 372: return makeRegisterExpression(amdgpu_gfx908::v116, output_vec_len ); + case 373: return makeRegisterExpression(amdgpu_gfx908::v117, output_vec_len ); + case 374: return makeRegisterExpression(amdgpu_gfx908::v118, output_vec_len ); + case 375: return makeRegisterExpression(amdgpu_gfx908::v119, output_vec_len ); + case 376: return makeRegisterExpression(amdgpu_gfx908::v120, output_vec_len ); + case 377: return makeRegisterExpression(amdgpu_gfx908::v121, output_vec_len ); + case 378: return makeRegisterExpression(amdgpu_gfx908::v122, output_vec_len ); + case 379: return makeRegisterExpression(amdgpu_gfx908::v123, output_vec_len ); + case 380: return makeRegisterExpression(amdgpu_gfx908::v124, output_vec_len ); + case 381: return makeRegisterExpression(amdgpu_gfx908::v125, output_vec_len ); + case 382: return makeRegisterExpression(amdgpu_gfx908::v126, output_vec_len ); + case 383: return makeRegisterExpression(amdgpu_gfx908::v127, output_vec_len ); + case 384: return makeRegisterExpression(amdgpu_gfx908::v128, output_vec_len ); + case 385: return makeRegisterExpression(amdgpu_gfx908::v129, output_vec_len ); + case 386: return makeRegisterExpression(amdgpu_gfx908::v130, output_vec_len ); + case 387: return makeRegisterExpression(amdgpu_gfx908::v131, output_vec_len ); + case 388: return makeRegisterExpression(amdgpu_gfx908::v132, output_vec_len ); + case 389: return makeRegisterExpression(amdgpu_gfx908::v133, output_vec_len ); + case 390: return makeRegisterExpression(amdgpu_gfx908::v134, output_vec_len ); + case 391: return makeRegisterExpression(amdgpu_gfx908::v135, output_vec_len ); + case 392: return makeRegisterExpression(amdgpu_gfx908::v136, output_vec_len ); + case 393: return makeRegisterExpression(amdgpu_gfx908::v137, output_vec_len ); + case 394: return makeRegisterExpression(amdgpu_gfx908::v138, output_vec_len ); + case 395: return makeRegisterExpression(amdgpu_gfx908::v139, output_vec_len ); + case 396: return makeRegisterExpression(amdgpu_gfx908::v140, output_vec_len ); + case 397: return makeRegisterExpression(amdgpu_gfx908::v141, output_vec_len ); + case 398: return makeRegisterExpression(amdgpu_gfx908::v142, output_vec_len ); + case 399: return makeRegisterExpression(amdgpu_gfx908::v143, output_vec_len ); + case 400: return makeRegisterExpression(amdgpu_gfx908::v144, output_vec_len ); + case 401: return makeRegisterExpression(amdgpu_gfx908::v145, output_vec_len ); + case 402: return makeRegisterExpression(amdgpu_gfx908::v146, output_vec_len ); + case 403: return makeRegisterExpression(amdgpu_gfx908::v147, output_vec_len ); + case 404: return makeRegisterExpression(amdgpu_gfx908::v148, output_vec_len ); + case 405: return makeRegisterExpression(amdgpu_gfx908::v149, output_vec_len ); + case 406: return makeRegisterExpression(amdgpu_gfx908::v150, output_vec_len ); + case 407: return makeRegisterExpression(amdgpu_gfx908::v151, output_vec_len ); + case 408: return makeRegisterExpression(amdgpu_gfx908::v152, output_vec_len ); + case 409: return makeRegisterExpression(amdgpu_gfx908::v153, output_vec_len ); + case 410: return makeRegisterExpression(amdgpu_gfx908::v154, output_vec_len ); + case 411: return makeRegisterExpression(amdgpu_gfx908::v155, output_vec_len ); + case 412: return makeRegisterExpression(amdgpu_gfx908::v156, output_vec_len ); + case 413: return makeRegisterExpression(amdgpu_gfx908::v157, output_vec_len ); + case 414: return makeRegisterExpression(amdgpu_gfx908::v158, output_vec_len ); + case 415: return makeRegisterExpression(amdgpu_gfx908::v159, output_vec_len ); + case 416: return makeRegisterExpression(amdgpu_gfx908::v160, output_vec_len ); + case 417: return makeRegisterExpression(amdgpu_gfx908::v161, output_vec_len ); + case 418: return makeRegisterExpression(amdgpu_gfx908::v162, output_vec_len ); + case 419: return makeRegisterExpression(amdgpu_gfx908::v163, output_vec_len ); + case 420: return makeRegisterExpression(amdgpu_gfx908::v164, output_vec_len ); + case 421: return makeRegisterExpression(amdgpu_gfx908::v165, output_vec_len ); + case 422: return makeRegisterExpression(amdgpu_gfx908::v166, output_vec_len ); + case 423: return makeRegisterExpression(amdgpu_gfx908::v167, output_vec_len ); + case 424: return makeRegisterExpression(amdgpu_gfx908::v168, output_vec_len ); + case 425: return makeRegisterExpression(amdgpu_gfx908::v169, output_vec_len ); + case 426: return makeRegisterExpression(amdgpu_gfx908::v170, output_vec_len ); + case 427: return makeRegisterExpression(amdgpu_gfx908::v171, output_vec_len ); + case 428: return makeRegisterExpression(amdgpu_gfx908::v172, output_vec_len ); + case 429: return makeRegisterExpression(amdgpu_gfx908::v173, output_vec_len ); + case 430: return makeRegisterExpression(amdgpu_gfx908::v174, output_vec_len ); + case 431: return makeRegisterExpression(amdgpu_gfx908::v175, output_vec_len ); + case 432: return makeRegisterExpression(amdgpu_gfx908::v176, output_vec_len ); + case 433: return makeRegisterExpression(amdgpu_gfx908::v177, output_vec_len ); + case 434: return makeRegisterExpression(amdgpu_gfx908::v178, output_vec_len ); + case 435: return makeRegisterExpression(amdgpu_gfx908::v179, output_vec_len ); + case 436: return makeRegisterExpression(amdgpu_gfx908::v180, output_vec_len ); + case 437: return makeRegisterExpression(amdgpu_gfx908::v181, output_vec_len ); + case 438: return makeRegisterExpression(amdgpu_gfx908::v182, output_vec_len ); + case 439: return makeRegisterExpression(amdgpu_gfx908::v183, output_vec_len ); + case 440: return makeRegisterExpression(amdgpu_gfx908::v184, output_vec_len ); + case 441: return makeRegisterExpression(amdgpu_gfx908::v185, output_vec_len ); + case 442: return makeRegisterExpression(amdgpu_gfx908::v186, output_vec_len ); + case 443: return makeRegisterExpression(amdgpu_gfx908::v187, output_vec_len ); + case 444: return makeRegisterExpression(amdgpu_gfx908::v188, output_vec_len ); + case 445: return makeRegisterExpression(amdgpu_gfx908::v189, output_vec_len ); + case 446: return makeRegisterExpression(amdgpu_gfx908::v190, output_vec_len ); + case 447: return makeRegisterExpression(amdgpu_gfx908::v191, output_vec_len ); + case 448: return makeRegisterExpression(amdgpu_gfx908::v192, output_vec_len ); + case 449: return makeRegisterExpression(amdgpu_gfx908::v193, output_vec_len ); + case 450: return makeRegisterExpression(amdgpu_gfx908::v194, output_vec_len ); + case 451: return makeRegisterExpression(amdgpu_gfx908::v195, output_vec_len ); + case 452: return makeRegisterExpression(amdgpu_gfx908::v196, output_vec_len ); + case 453: return makeRegisterExpression(amdgpu_gfx908::v197, output_vec_len ); + case 454: return makeRegisterExpression(amdgpu_gfx908::v198, output_vec_len ); + case 455: return makeRegisterExpression(amdgpu_gfx908::v199, output_vec_len ); + case 456: return makeRegisterExpression(amdgpu_gfx908::v200, output_vec_len ); + case 457: return makeRegisterExpression(amdgpu_gfx908::v201, output_vec_len ); + case 458: return makeRegisterExpression(amdgpu_gfx908::v202, output_vec_len ); + case 459: return makeRegisterExpression(amdgpu_gfx908::v203, output_vec_len ); + case 460: return makeRegisterExpression(amdgpu_gfx908::v204, output_vec_len ); + case 461: return makeRegisterExpression(amdgpu_gfx908::v205, output_vec_len ); + case 462: return makeRegisterExpression(amdgpu_gfx908::v206, output_vec_len ); + case 463: return makeRegisterExpression(amdgpu_gfx908::v207, output_vec_len ); + case 464: return makeRegisterExpression(amdgpu_gfx908::v208, output_vec_len ); + case 465: return makeRegisterExpression(amdgpu_gfx908::v209, output_vec_len ); + case 466: return makeRegisterExpression(amdgpu_gfx908::v210, output_vec_len ); + case 467: return makeRegisterExpression(amdgpu_gfx908::v211, output_vec_len ); + case 468: return makeRegisterExpression(amdgpu_gfx908::v212, output_vec_len ); + case 469: return makeRegisterExpression(amdgpu_gfx908::v213, output_vec_len ); + case 470: return makeRegisterExpression(amdgpu_gfx908::v214, output_vec_len ); + case 471: return makeRegisterExpression(amdgpu_gfx908::v215, output_vec_len ); + case 472: return makeRegisterExpression(amdgpu_gfx908::v216, output_vec_len ); + case 473: return makeRegisterExpression(amdgpu_gfx908::v217, output_vec_len ); + case 474: return makeRegisterExpression(amdgpu_gfx908::v218, output_vec_len ); + case 475: return makeRegisterExpression(amdgpu_gfx908::v219, output_vec_len ); + case 476: return makeRegisterExpression(amdgpu_gfx908::v220, output_vec_len ); + case 477: return makeRegisterExpression(amdgpu_gfx908::v221, output_vec_len ); + case 478: return makeRegisterExpression(amdgpu_gfx908::v222, output_vec_len ); + case 479: return makeRegisterExpression(amdgpu_gfx908::v223, output_vec_len ); + case 480: return makeRegisterExpression(amdgpu_gfx908::v224, output_vec_len ); + case 481: return makeRegisterExpression(amdgpu_gfx908::v225, output_vec_len ); + case 482: return makeRegisterExpression(amdgpu_gfx908::v226, output_vec_len ); + case 483: return makeRegisterExpression(amdgpu_gfx908::v227, output_vec_len ); + case 484: return makeRegisterExpression(amdgpu_gfx908::v228, output_vec_len ); + case 485: return makeRegisterExpression(amdgpu_gfx908::v229, output_vec_len ); + case 486: return makeRegisterExpression(amdgpu_gfx908::v230, output_vec_len ); + case 487: return makeRegisterExpression(amdgpu_gfx908::v231, output_vec_len ); + case 488: return makeRegisterExpression(amdgpu_gfx908::v232, output_vec_len ); + case 489: return makeRegisterExpression(amdgpu_gfx908::v233, output_vec_len ); + case 490: return makeRegisterExpression(amdgpu_gfx908::v234, output_vec_len ); + case 491: return makeRegisterExpression(amdgpu_gfx908::v235, output_vec_len ); + case 492: return makeRegisterExpression(amdgpu_gfx908::v236, output_vec_len ); + case 493: return makeRegisterExpression(amdgpu_gfx908::v237, output_vec_len ); + case 494: return makeRegisterExpression(amdgpu_gfx908::v238, output_vec_len ); + case 495: return makeRegisterExpression(amdgpu_gfx908::v239, output_vec_len ); + case 496: return makeRegisterExpression(amdgpu_gfx908::v240, output_vec_len ); + case 497: return makeRegisterExpression(amdgpu_gfx908::v241, output_vec_len ); + case 498: return makeRegisterExpression(amdgpu_gfx908::v242, output_vec_len ); + case 499: return makeRegisterExpression(amdgpu_gfx908::v243, output_vec_len ); + case 500: return makeRegisterExpression(amdgpu_gfx908::v244, output_vec_len ); + case 501: return makeRegisterExpression(amdgpu_gfx908::v245, output_vec_len ); + case 502: return makeRegisterExpression(amdgpu_gfx908::v246, output_vec_len ); + case 503: return makeRegisterExpression(amdgpu_gfx908::v247, output_vec_len ); + case 504: return makeRegisterExpression(amdgpu_gfx908::v248, output_vec_len ); + case 505: return makeRegisterExpression(amdgpu_gfx908::v249, output_vec_len ); + case 506: return makeRegisterExpression(amdgpu_gfx908::v250, output_vec_len ); + case 507: return makeRegisterExpression(amdgpu_gfx908::v251, output_vec_len ); + case 508: return makeRegisterExpression(amdgpu_gfx908::v252, output_vec_len ); + case 509: return makeRegisterExpression(amdgpu_gfx908::v253, output_vec_len ); + case 510: return makeRegisterExpression(amdgpu_gfx908::v254, output_vec_len ); + case 511: return makeRegisterExpression(amdgpu_gfx908::v255, output_vec_len ); + case 254: return makeRegisterExpression(amdgpu_gfx908::src_lds_direct, output_vec_len ); + default: return makeRegisterExpression(amdgpu_gfx908::invalid); + } + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SRC_SIMPLE(uint64_t input, uint32_t output_vec_len) + { + switch (input) { + case 0: return makeRegisterExpression(amdgpu_gfx908::s0, output_vec_len ); + case 1: return makeRegisterExpression(amdgpu_gfx908::s1, output_vec_len ); + case 2: return makeRegisterExpression(amdgpu_gfx908::s2, output_vec_len ); + case 3: return makeRegisterExpression(amdgpu_gfx908::s3, output_vec_len ); + case 4: return makeRegisterExpression(amdgpu_gfx908::s4, output_vec_len ); + case 5: return makeRegisterExpression(amdgpu_gfx908::s5, output_vec_len ); + case 6: return makeRegisterExpression(amdgpu_gfx908::s6, output_vec_len ); + case 7: return makeRegisterExpression(amdgpu_gfx908::s7, output_vec_len ); + case 8: return makeRegisterExpression(amdgpu_gfx908::s8, output_vec_len ); + case 9: return makeRegisterExpression(amdgpu_gfx908::s9, output_vec_len ); + case 10: return makeRegisterExpression(amdgpu_gfx908::s10, output_vec_len ); + case 11: return makeRegisterExpression(amdgpu_gfx908::s11, output_vec_len ); + case 12: return makeRegisterExpression(amdgpu_gfx908::s12, output_vec_len ); + case 13: return makeRegisterExpression(amdgpu_gfx908::s13, output_vec_len ); + case 14: return makeRegisterExpression(amdgpu_gfx908::s14, output_vec_len ); + case 15: return makeRegisterExpression(amdgpu_gfx908::s15, output_vec_len ); + case 16: return makeRegisterExpression(amdgpu_gfx908::s16, output_vec_len ); + case 17: return makeRegisterExpression(amdgpu_gfx908::s17, output_vec_len ); + case 18: return makeRegisterExpression(amdgpu_gfx908::s18, output_vec_len ); + case 19: return makeRegisterExpression(amdgpu_gfx908::s19, output_vec_len ); + case 20: return makeRegisterExpression(amdgpu_gfx908::s20, output_vec_len ); + case 21: return makeRegisterExpression(amdgpu_gfx908::s21, output_vec_len ); + case 22: return makeRegisterExpression(amdgpu_gfx908::s22, output_vec_len ); + case 23: return makeRegisterExpression(amdgpu_gfx908::s23, output_vec_len ); + case 24: return makeRegisterExpression(amdgpu_gfx908::s24, output_vec_len ); + case 25: return makeRegisterExpression(amdgpu_gfx908::s25, output_vec_len ); + case 26: return makeRegisterExpression(amdgpu_gfx908::s26, output_vec_len ); + case 27: return makeRegisterExpression(amdgpu_gfx908::s27, output_vec_len ); + case 28: return makeRegisterExpression(amdgpu_gfx908::s28, output_vec_len ); + case 29: return makeRegisterExpression(amdgpu_gfx908::s29, output_vec_len ); + case 30: return makeRegisterExpression(amdgpu_gfx908::s30, output_vec_len ); + case 31: return makeRegisterExpression(amdgpu_gfx908::s31, output_vec_len ); + case 32: return makeRegisterExpression(amdgpu_gfx908::s32, output_vec_len ); + case 33: return makeRegisterExpression(amdgpu_gfx908::s33, output_vec_len ); + case 34: return makeRegisterExpression(amdgpu_gfx908::s34, output_vec_len ); + case 35: return makeRegisterExpression(amdgpu_gfx908::s35, output_vec_len ); + case 36: return makeRegisterExpression(amdgpu_gfx908::s36, output_vec_len ); + case 37: return makeRegisterExpression(amdgpu_gfx908::s37, output_vec_len ); + case 38: return makeRegisterExpression(amdgpu_gfx908::s38, output_vec_len ); + case 39: return makeRegisterExpression(amdgpu_gfx908::s39, output_vec_len ); + case 40: return makeRegisterExpression(amdgpu_gfx908::s40, output_vec_len ); + case 41: return makeRegisterExpression(amdgpu_gfx908::s41, output_vec_len ); + case 42: return makeRegisterExpression(amdgpu_gfx908::s42, output_vec_len ); + case 43: return makeRegisterExpression(amdgpu_gfx908::s43, output_vec_len ); + case 44: return makeRegisterExpression(amdgpu_gfx908::s44, output_vec_len ); + case 45: return makeRegisterExpression(amdgpu_gfx908::s45, output_vec_len ); + case 46: return makeRegisterExpression(amdgpu_gfx908::s46, output_vec_len ); + case 47: return makeRegisterExpression(amdgpu_gfx908::s47, output_vec_len ); + case 48: return makeRegisterExpression(amdgpu_gfx908::s48, output_vec_len ); + case 49: return makeRegisterExpression(amdgpu_gfx908::s49, output_vec_len ); + case 50: return makeRegisterExpression(amdgpu_gfx908::s50, output_vec_len ); + case 51: return makeRegisterExpression(amdgpu_gfx908::s51, output_vec_len ); + case 52: return makeRegisterExpression(amdgpu_gfx908::s52, output_vec_len ); + case 53: return makeRegisterExpression(amdgpu_gfx908::s53, output_vec_len ); + case 54: return makeRegisterExpression(amdgpu_gfx908::s54, output_vec_len ); + case 55: return makeRegisterExpression(amdgpu_gfx908::s55, output_vec_len ); + case 56: return makeRegisterExpression(amdgpu_gfx908::s56, output_vec_len ); + case 57: return makeRegisterExpression(amdgpu_gfx908::s57, output_vec_len ); + case 58: return makeRegisterExpression(amdgpu_gfx908::s58, output_vec_len ); + case 59: return makeRegisterExpression(amdgpu_gfx908::s59, output_vec_len ); + case 60: return makeRegisterExpression(amdgpu_gfx908::s60, output_vec_len ); + case 61: return makeRegisterExpression(amdgpu_gfx908::s61, output_vec_len ); + case 62: return makeRegisterExpression(amdgpu_gfx908::s62, output_vec_len ); + case 63: return makeRegisterExpression(amdgpu_gfx908::s63, output_vec_len ); + case 64: return makeRegisterExpression(amdgpu_gfx908::s64, output_vec_len ); + case 65: return makeRegisterExpression(amdgpu_gfx908::s65, output_vec_len ); + case 66: return makeRegisterExpression(amdgpu_gfx908::s66, output_vec_len ); + case 67: return makeRegisterExpression(amdgpu_gfx908::s67, output_vec_len ); + case 68: return makeRegisterExpression(amdgpu_gfx908::s68, output_vec_len ); + case 69: return makeRegisterExpression(amdgpu_gfx908::s69, output_vec_len ); + case 70: return makeRegisterExpression(amdgpu_gfx908::s70, output_vec_len ); + case 71: return makeRegisterExpression(amdgpu_gfx908::s71, output_vec_len ); + case 72: return makeRegisterExpression(amdgpu_gfx908::s72, output_vec_len ); + case 73: return makeRegisterExpression(amdgpu_gfx908::s73, output_vec_len ); + case 74: return makeRegisterExpression(amdgpu_gfx908::s74, output_vec_len ); + case 75: return makeRegisterExpression(amdgpu_gfx908::s75, output_vec_len ); + case 76: return makeRegisterExpression(amdgpu_gfx908::s76, output_vec_len ); + case 77: return makeRegisterExpression(amdgpu_gfx908::s77, output_vec_len ); + case 78: return makeRegisterExpression(amdgpu_gfx908::s78, output_vec_len ); + case 79: return makeRegisterExpression(amdgpu_gfx908::s79, output_vec_len ); + case 80: return makeRegisterExpression(amdgpu_gfx908::s80, output_vec_len ); + case 81: return makeRegisterExpression(amdgpu_gfx908::s81, output_vec_len ); + case 82: return makeRegisterExpression(amdgpu_gfx908::s82, output_vec_len ); + case 83: return makeRegisterExpression(amdgpu_gfx908::s83, output_vec_len ); + case 84: return makeRegisterExpression(amdgpu_gfx908::s84, output_vec_len ); + case 85: return makeRegisterExpression(amdgpu_gfx908::s85, output_vec_len ); + case 86: return makeRegisterExpression(amdgpu_gfx908::s86, output_vec_len ); + case 87: return makeRegisterExpression(amdgpu_gfx908::s87, output_vec_len ); + case 88: return makeRegisterExpression(amdgpu_gfx908::s88, output_vec_len ); + case 89: return makeRegisterExpression(amdgpu_gfx908::s89, output_vec_len ); + case 90: return makeRegisterExpression(amdgpu_gfx908::s90, output_vec_len ); + case 91: return makeRegisterExpression(amdgpu_gfx908::s91, output_vec_len ); + case 92: return makeRegisterExpression(amdgpu_gfx908::s92, output_vec_len ); + case 93: return makeRegisterExpression(amdgpu_gfx908::s93, output_vec_len ); + case 94: return makeRegisterExpression(amdgpu_gfx908::s94, output_vec_len ); + case 95: return makeRegisterExpression(amdgpu_gfx908::s95, output_vec_len ); + case 96: return makeRegisterExpression(amdgpu_gfx908::s96, output_vec_len ); + case 97: return makeRegisterExpression(amdgpu_gfx908::s97, output_vec_len ); + case 98: return makeRegisterExpression(amdgpu_gfx908::s98, output_vec_len ); + case 99: return makeRegisterExpression(amdgpu_gfx908::s99, output_vec_len ); + case 100: return makeRegisterExpression(amdgpu_gfx908::s100, output_vec_len ); + case 101: return makeRegisterExpression(amdgpu_gfx908::s101, output_vec_len ); + case 104: return makeRegisterExpression(amdgpu_gfx908::xnack_mask_lo, output_vec_len ); + case 105: return makeRegisterExpression(amdgpu_gfx908::xnack_mask_hi, output_vec_len ); + case 102: return makeRegisterExpression(amdgpu_gfx908::flat_scratch_lo, output_vec_len ); + case 103: return makeRegisterExpression(amdgpu_gfx908::flat_scratch_hi, output_vec_len ); + case 108: return makeRegisterExpression(amdgpu_gfx908::ttmp0, output_vec_len ); + case 109: return makeRegisterExpression(amdgpu_gfx908::ttmp1, output_vec_len ); + case 110: return makeRegisterExpression(amdgpu_gfx908::ttmp2, output_vec_len ); + case 111: return makeRegisterExpression(amdgpu_gfx908::ttmp3, output_vec_len ); + case 112: return makeRegisterExpression(amdgpu_gfx908::ttmp4, output_vec_len ); + case 113: return makeRegisterExpression(amdgpu_gfx908::ttmp5, output_vec_len ); + case 114: return makeRegisterExpression(amdgpu_gfx908::ttmp6, output_vec_len ); + case 115: return makeRegisterExpression(amdgpu_gfx908::ttmp7, output_vec_len ); + case 116: return makeRegisterExpression(amdgpu_gfx908::ttmp8, output_vec_len ); + case 117: return makeRegisterExpression(amdgpu_gfx908::ttmp9, output_vec_len ); + case 118: return makeRegisterExpression(amdgpu_gfx908::ttmp10, output_vec_len ); + case 119: return makeRegisterExpression(amdgpu_gfx908::ttmp11, output_vec_len ); + case 120: return makeRegisterExpression(amdgpu_gfx908::ttmp12, output_vec_len ); + case 121: return makeRegisterExpression(amdgpu_gfx908::ttmp13, output_vec_len ); + case 122: return makeRegisterExpression(amdgpu_gfx908::ttmp14, output_vec_len ); + case 123: return makeRegisterExpression(amdgpu_gfx908::ttmp15, output_vec_len ); + case 106: return makeRegisterExpression(amdgpu_gfx908::vcc_lo, output_vec_len ); + case 107: return makeRegisterExpression(amdgpu_gfx908::vcc_hi, output_vec_len ); + case 124: return makeRegisterExpression(amdgpu_gfx908::m0, output_vec_len ); + case 126: return makeRegisterExpression(amdgpu_gfx908::exec_lo, output_vec_len ); + case 127: return makeRegisterExpression(amdgpu_gfx908::exec_hi, output_vec_len ); + case 128: return Immediate::makeImmediate(Result(u32, 0)); + case 129: return Immediate::makeImmediate(Result(u32, 1)); + case 130: return Immediate::makeImmediate(Result(u32, 2)); + case 131: return Immediate::makeImmediate(Result(u32, 3)); + case 132: return Immediate::makeImmediate(Result(u32, 4)); + case 133: return Immediate::makeImmediate(Result(u32, 5)); + case 134: return Immediate::makeImmediate(Result(u32, 6)); + case 135: return Immediate::makeImmediate(Result(u32, 7)); + case 136: return Immediate::makeImmediate(Result(u32, 8)); + case 137: return Immediate::makeImmediate(Result(u32, 9)); + case 138: return Immediate::makeImmediate(Result(u32, 10)); + case 139: return Immediate::makeImmediate(Result(u32, 11)); + case 140: return Immediate::makeImmediate(Result(u32, 12)); + case 141: return Immediate::makeImmediate(Result(u32, 13)); + case 142: return Immediate::makeImmediate(Result(u32, 14)); + case 143: return Immediate::makeImmediate(Result(u32, 15)); + case 144: return Immediate::makeImmediate(Result(u32, 16)); + case 145: return Immediate::makeImmediate(Result(u32, 17)); + case 146: return Immediate::makeImmediate(Result(u32, 18)); + case 147: return Immediate::makeImmediate(Result(u32, 19)); + case 148: return Immediate::makeImmediate(Result(u32, 20)); + case 149: return Immediate::makeImmediate(Result(u32, 21)); + case 150: return Immediate::makeImmediate(Result(u32, 22)); + case 151: return Immediate::makeImmediate(Result(u32, 23)); + case 152: return Immediate::makeImmediate(Result(u32, 24)); + case 153: return Immediate::makeImmediate(Result(u32, 25)); + case 154: return Immediate::makeImmediate(Result(u32, 26)); + case 155: return Immediate::makeImmediate(Result(u32, 27)); + case 156: return Immediate::makeImmediate(Result(u32, 28)); + case 157: return Immediate::makeImmediate(Result(u32, 29)); + case 158: return Immediate::makeImmediate(Result(u32, 30)); + case 159: return Immediate::makeImmediate(Result(u32, 31)); + case 160: return Immediate::makeImmediate(Result(u32, 32)); + case 161: return Immediate::makeImmediate(Result(u32, 33)); + case 162: return Immediate::makeImmediate(Result(u32, 34)); + case 163: return Immediate::makeImmediate(Result(u32, 35)); + case 164: return Immediate::makeImmediate(Result(u32, 36)); + case 165: return Immediate::makeImmediate(Result(u32, 37)); + case 166: return Immediate::makeImmediate(Result(u32, 38)); + case 167: return Immediate::makeImmediate(Result(u32, 39)); + case 168: return Immediate::makeImmediate(Result(u32, 40)); + case 169: return Immediate::makeImmediate(Result(u32, 41)); + case 170: return Immediate::makeImmediate(Result(u32, 42)); + case 171: return Immediate::makeImmediate(Result(u32, 43)); + case 172: return Immediate::makeImmediate(Result(u32, 44)); + case 173: return Immediate::makeImmediate(Result(u32, 45)); + case 174: return Immediate::makeImmediate(Result(u32, 46)); + case 175: return Immediate::makeImmediate(Result(u32, 47)); + case 176: return Immediate::makeImmediate(Result(u32, 48)); + case 177: return Immediate::makeImmediate(Result(u32, 49)); + case 178: return Immediate::makeImmediate(Result(u32, 50)); + case 179: return Immediate::makeImmediate(Result(u32, 51)); + case 180: return Immediate::makeImmediate(Result(u32, 52)); + case 181: return Immediate::makeImmediate(Result(u32, 53)); + case 182: return Immediate::makeImmediate(Result(u32, 54)); + case 183: return Immediate::makeImmediate(Result(u32, 55)); + case 184: return Immediate::makeImmediate(Result(u32, 56)); + case 185: return Immediate::makeImmediate(Result(u32, 57)); + case 186: return Immediate::makeImmediate(Result(u32, 58)); + case 187: return Immediate::makeImmediate(Result(u32, 59)); + case 188: return Immediate::makeImmediate(Result(u32, 60)); + case 189: return Immediate::makeImmediate(Result(u32, 61)); + case 190: return Immediate::makeImmediate(Result(u32, 62)); + case 191: return Immediate::makeImmediate(Result(u32, 63)); + case 192: return Immediate::makeImmediate(Result(u32, 64)); + case 193: return Immediate::makeImmediate(Result(u32, -1)); + case 194: return Immediate::makeImmediate(Result(u32, -2)); + case 195: return Immediate::makeImmediate(Result(u32, -3)); + case 196: return Immediate::makeImmediate(Result(u32, -4)); + case 197: return Immediate::makeImmediate(Result(u32, -5)); + case 198: return Immediate::makeImmediate(Result(u32, -6)); + case 199: return Immediate::makeImmediate(Result(u32, -7)); + case 200: return Immediate::makeImmediate(Result(u32, -8)); + case 201: return Immediate::makeImmediate(Result(u32, -9)); + case 202: return Immediate::makeImmediate(Result(u32, -10)); + case 203: return Immediate::makeImmediate(Result(u32, -11)); + case 204: return Immediate::makeImmediate(Result(u32, -12)); + case 205: return Immediate::makeImmediate(Result(u32, -13)); + case 206: return Immediate::makeImmediate(Result(u32, -14)); + case 207: return Immediate::makeImmediate(Result(u32, -15)); + case 208: return Immediate::makeImmediate(Result(u32, -16)); + case 240: return Immediate::makeImmediate(Result(sp_float, 0.5)); + case 241: return Immediate::makeImmediate(Result(sp_float, -0.5)); + case 242: return Immediate::makeImmediate(Result(sp_float, 1.0)); + case 243: return Immediate::makeImmediate(Result(sp_float, -1.0)); + case 244: return Immediate::makeImmediate(Result(sp_float, 2.0)); + case 245: return Immediate::makeImmediate(Result(sp_float, -2.0)); + case 246: return Immediate::makeImmediate(Result(sp_float, 4.0)); + case 247: return Immediate::makeImmediate(Result(sp_float, -4.0)); + case 248: return Immediate::makeImmediate(Result(sp_float, 0.15915494)); + case 251: return makeRegisterExpression(amdgpu_gfx908::src_vccz, output_vec_len ); + case 252: return makeRegisterExpression(amdgpu_gfx908::src_execz, output_vec_len ); + case 253: return makeRegisterExpression(amdgpu_gfx908::src_scc, output_vec_len ); + case 235: return makeRegisterExpression(amdgpu_gfx908::src_shared_base, output_vec_len ); + case 236: return makeRegisterExpression(amdgpu_gfx908::src_shared_limit, output_vec_len ); + case 237: return makeRegisterExpression(amdgpu_gfx908::src_private_base, output_vec_len ); + case 238: return makeRegisterExpression(amdgpu_gfx908::src_private_limit, output_vec_len ); + case 239: return makeRegisterExpression(amdgpu_gfx908::src_pops_exiting_wave_id, output_vec_len ); + case 256: return makeRegisterExpression(amdgpu_gfx908::v0, output_vec_len ); + case 257: return makeRegisterExpression(amdgpu_gfx908::v1, output_vec_len ); + case 258: return makeRegisterExpression(amdgpu_gfx908::v2, output_vec_len ); + case 259: return makeRegisterExpression(amdgpu_gfx908::v3, output_vec_len ); + case 260: return makeRegisterExpression(amdgpu_gfx908::v4, output_vec_len ); + case 261: return makeRegisterExpression(amdgpu_gfx908::v5, output_vec_len ); + case 262: return makeRegisterExpression(amdgpu_gfx908::v6, output_vec_len ); + case 263: return makeRegisterExpression(amdgpu_gfx908::v7, output_vec_len ); + case 264: return makeRegisterExpression(amdgpu_gfx908::v8, output_vec_len ); + case 265: return makeRegisterExpression(amdgpu_gfx908::v9, output_vec_len ); + case 266: return makeRegisterExpression(amdgpu_gfx908::v10, output_vec_len ); + case 267: return makeRegisterExpression(amdgpu_gfx908::v11, output_vec_len ); + case 268: return makeRegisterExpression(amdgpu_gfx908::v12, output_vec_len ); + case 269: return makeRegisterExpression(amdgpu_gfx908::v13, output_vec_len ); + case 270: return makeRegisterExpression(amdgpu_gfx908::v14, output_vec_len ); + case 271: return makeRegisterExpression(amdgpu_gfx908::v15, output_vec_len ); + case 272: return makeRegisterExpression(amdgpu_gfx908::v16, output_vec_len ); + case 273: return makeRegisterExpression(amdgpu_gfx908::v17, output_vec_len ); + case 274: return makeRegisterExpression(amdgpu_gfx908::v18, output_vec_len ); + case 275: return makeRegisterExpression(amdgpu_gfx908::v19, output_vec_len ); + case 276: return makeRegisterExpression(amdgpu_gfx908::v20, output_vec_len ); + case 277: return makeRegisterExpression(amdgpu_gfx908::v21, output_vec_len ); + case 278: return makeRegisterExpression(amdgpu_gfx908::v22, output_vec_len ); + case 279: return makeRegisterExpression(amdgpu_gfx908::v23, output_vec_len ); + case 280: return makeRegisterExpression(amdgpu_gfx908::v24, output_vec_len ); + case 281: return makeRegisterExpression(amdgpu_gfx908::v25, output_vec_len ); + case 282: return makeRegisterExpression(amdgpu_gfx908::v26, output_vec_len ); + case 283: return makeRegisterExpression(amdgpu_gfx908::v27, output_vec_len ); + case 284: return makeRegisterExpression(amdgpu_gfx908::v28, output_vec_len ); + case 285: return makeRegisterExpression(amdgpu_gfx908::v29, output_vec_len ); + case 286: return makeRegisterExpression(amdgpu_gfx908::v30, output_vec_len ); + case 287: return makeRegisterExpression(amdgpu_gfx908::v31, output_vec_len ); + case 288: return makeRegisterExpression(amdgpu_gfx908::v32, output_vec_len ); + case 289: return makeRegisterExpression(amdgpu_gfx908::v33, output_vec_len ); + case 290: return makeRegisterExpression(amdgpu_gfx908::v34, output_vec_len ); + case 291: return makeRegisterExpression(amdgpu_gfx908::v35, output_vec_len ); + case 292: return makeRegisterExpression(amdgpu_gfx908::v36, output_vec_len ); + case 293: return makeRegisterExpression(amdgpu_gfx908::v37, output_vec_len ); + case 294: return makeRegisterExpression(amdgpu_gfx908::v38, output_vec_len ); + case 295: return makeRegisterExpression(amdgpu_gfx908::v39, output_vec_len ); + case 296: return makeRegisterExpression(amdgpu_gfx908::v40, output_vec_len ); + case 297: return makeRegisterExpression(amdgpu_gfx908::v41, output_vec_len ); + case 298: return makeRegisterExpression(amdgpu_gfx908::v42, output_vec_len ); + case 299: return makeRegisterExpression(amdgpu_gfx908::v43, output_vec_len ); + case 300: return makeRegisterExpression(amdgpu_gfx908::v44, output_vec_len ); + case 301: return makeRegisterExpression(amdgpu_gfx908::v45, output_vec_len ); + case 302: return makeRegisterExpression(amdgpu_gfx908::v46, output_vec_len ); + case 303: return makeRegisterExpression(amdgpu_gfx908::v47, output_vec_len ); + case 304: return makeRegisterExpression(amdgpu_gfx908::v48, output_vec_len ); + case 305: return makeRegisterExpression(amdgpu_gfx908::v49, output_vec_len ); + case 306: return makeRegisterExpression(amdgpu_gfx908::v50, output_vec_len ); + case 307: return makeRegisterExpression(amdgpu_gfx908::v51, output_vec_len ); + case 308: return makeRegisterExpression(amdgpu_gfx908::v52, output_vec_len ); + case 309: return makeRegisterExpression(amdgpu_gfx908::v53, output_vec_len ); + case 310: return makeRegisterExpression(amdgpu_gfx908::v54, output_vec_len ); + case 311: return makeRegisterExpression(amdgpu_gfx908::v55, output_vec_len ); + case 312: return makeRegisterExpression(amdgpu_gfx908::v56, output_vec_len ); + case 313: return makeRegisterExpression(amdgpu_gfx908::v57, output_vec_len ); + case 314: return makeRegisterExpression(amdgpu_gfx908::v58, output_vec_len ); + case 315: return makeRegisterExpression(amdgpu_gfx908::v59, output_vec_len ); + case 316: return makeRegisterExpression(amdgpu_gfx908::v60, output_vec_len ); + case 317: return makeRegisterExpression(amdgpu_gfx908::v61, output_vec_len ); + case 318: return makeRegisterExpression(amdgpu_gfx908::v62, output_vec_len ); + case 319: return makeRegisterExpression(amdgpu_gfx908::v63, output_vec_len ); + case 320: return makeRegisterExpression(amdgpu_gfx908::v64, output_vec_len ); + case 321: return makeRegisterExpression(amdgpu_gfx908::v65, output_vec_len ); + case 322: return makeRegisterExpression(amdgpu_gfx908::v66, output_vec_len ); + case 323: return makeRegisterExpression(amdgpu_gfx908::v67, output_vec_len ); + case 324: return makeRegisterExpression(amdgpu_gfx908::v68, output_vec_len ); + case 325: return makeRegisterExpression(amdgpu_gfx908::v69, output_vec_len ); + case 326: return makeRegisterExpression(amdgpu_gfx908::v70, output_vec_len ); + case 327: return makeRegisterExpression(amdgpu_gfx908::v71, output_vec_len ); + case 328: return makeRegisterExpression(amdgpu_gfx908::v72, output_vec_len ); + case 329: return makeRegisterExpression(amdgpu_gfx908::v73, output_vec_len ); + case 330: return makeRegisterExpression(amdgpu_gfx908::v74, output_vec_len ); + case 331: return makeRegisterExpression(amdgpu_gfx908::v75, output_vec_len ); + case 332: return makeRegisterExpression(amdgpu_gfx908::v76, output_vec_len ); + case 333: return makeRegisterExpression(amdgpu_gfx908::v77, output_vec_len ); + case 334: return makeRegisterExpression(amdgpu_gfx908::v78, output_vec_len ); + case 335: return makeRegisterExpression(amdgpu_gfx908::v79, output_vec_len ); + case 336: return makeRegisterExpression(amdgpu_gfx908::v80, output_vec_len ); + case 337: return makeRegisterExpression(amdgpu_gfx908::v81, output_vec_len ); + case 338: return makeRegisterExpression(amdgpu_gfx908::v82, output_vec_len ); + case 339: return makeRegisterExpression(amdgpu_gfx908::v83, output_vec_len ); + case 340: return makeRegisterExpression(amdgpu_gfx908::v84, output_vec_len ); + case 341: return makeRegisterExpression(amdgpu_gfx908::v85, output_vec_len ); + case 342: return makeRegisterExpression(amdgpu_gfx908::v86, output_vec_len ); + case 343: return makeRegisterExpression(amdgpu_gfx908::v87, output_vec_len ); + case 344: return makeRegisterExpression(amdgpu_gfx908::v88, output_vec_len ); + case 345: return makeRegisterExpression(amdgpu_gfx908::v89, output_vec_len ); + case 346: return makeRegisterExpression(amdgpu_gfx908::v90, output_vec_len ); + case 347: return makeRegisterExpression(amdgpu_gfx908::v91, output_vec_len ); + case 348: return makeRegisterExpression(amdgpu_gfx908::v92, output_vec_len ); + case 349: return makeRegisterExpression(amdgpu_gfx908::v93, output_vec_len ); + case 350: return makeRegisterExpression(amdgpu_gfx908::v94, output_vec_len ); + case 351: return makeRegisterExpression(amdgpu_gfx908::v95, output_vec_len ); + case 352: return makeRegisterExpression(amdgpu_gfx908::v96, output_vec_len ); + case 353: return makeRegisterExpression(amdgpu_gfx908::v97, output_vec_len ); + case 354: return makeRegisterExpression(amdgpu_gfx908::v98, output_vec_len ); + case 355: return makeRegisterExpression(amdgpu_gfx908::v99, output_vec_len ); + case 356: return makeRegisterExpression(amdgpu_gfx908::v100, output_vec_len ); + case 357: return makeRegisterExpression(amdgpu_gfx908::v101, output_vec_len ); + case 358: return makeRegisterExpression(amdgpu_gfx908::v102, output_vec_len ); + case 359: return makeRegisterExpression(amdgpu_gfx908::v103, output_vec_len ); + case 360: return makeRegisterExpression(amdgpu_gfx908::v104, output_vec_len ); + case 361: return makeRegisterExpression(amdgpu_gfx908::v105, output_vec_len ); + case 362: return makeRegisterExpression(amdgpu_gfx908::v106, output_vec_len ); + case 363: return makeRegisterExpression(amdgpu_gfx908::v107, output_vec_len ); + case 364: return makeRegisterExpression(amdgpu_gfx908::v108, output_vec_len ); + case 365: return makeRegisterExpression(amdgpu_gfx908::v109, output_vec_len ); + case 366: return makeRegisterExpression(amdgpu_gfx908::v110, output_vec_len ); + case 367: return makeRegisterExpression(amdgpu_gfx908::v111, output_vec_len ); + case 368: return makeRegisterExpression(amdgpu_gfx908::v112, output_vec_len ); + case 369: return makeRegisterExpression(amdgpu_gfx908::v113, output_vec_len ); + case 370: return makeRegisterExpression(amdgpu_gfx908::v114, output_vec_len ); + case 371: return makeRegisterExpression(amdgpu_gfx908::v115, output_vec_len ); + case 372: return makeRegisterExpression(amdgpu_gfx908::v116, output_vec_len ); + case 373: return makeRegisterExpression(amdgpu_gfx908::v117, output_vec_len ); + case 374: return makeRegisterExpression(amdgpu_gfx908::v118, output_vec_len ); + case 375: return makeRegisterExpression(amdgpu_gfx908::v119, output_vec_len ); + case 376: return makeRegisterExpression(amdgpu_gfx908::v120, output_vec_len ); + case 377: return makeRegisterExpression(amdgpu_gfx908::v121, output_vec_len ); + case 378: return makeRegisterExpression(amdgpu_gfx908::v122, output_vec_len ); + case 379: return makeRegisterExpression(amdgpu_gfx908::v123, output_vec_len ); + case 380: return makeRegisterExpression(amdgpu_gfx908::v124, output_vec_len ); + case 381: return makeRegisterExpression(amdgpu_gfx908::v125, output_vec_len ); + case 382: return makeRegisterExpression(amdgpu_gfx908::v126, output_vec_len ); + case 383: return makeRegisterExpression(amdgpu_gfx908::v127, output_vec_len ); + case 384: return makeRegisterExpression(amdgpu_gfx908::v128, output_vec_len ); + case 385: return makeRegisterExpression(amdgpu_gfx908::v129, output_vec_len ); + case 386: return makeRegisterExpression(amdgpu_gfx908::v130, output_vec_len ); + case 387: return makeRegisterExpression(amdgpu_gfx908::v131, output_vec_len ); + case 388: return makeRegisterExpression(amdgpu_gfx908::v132, output_vec_len ); + case 389: return makeRegisterExpression(amdgpu_gfx908::v133, output_vec_len ); + case 390: return makeRegisterExpression(amdgpu_gfx908::v134, output_vec_len ); + case 391: return makeRegisterExpression(amdgpu_gfx908::v135, output_vec_len ); + case 392: return makeRegisterExpression(amdgpu_gfx908::v136, output_vec_len ); + case 393: return makeRegisterExpression(amdgpu_gfx908::v137, output_vec_len ); + case 394: return makeRegisterExpression(amdgpu_gfx908::v138, output_vec_len ); + case 395: return makeRegisterExpression(amdgpu_gfx908::v139, output_vec_len ); + case 396: return makeRegisterExpression(amdgpu_gfx908::v140, output_vec_len ); + case 397: return makeRegisterExpression(amdgpu_gfx908::v141, output_vec_len ); + case 398: return makeRegisterExpression(amdgpu_gfx908::v142, output_vec_len ); + case 399: return makeRegisterExpression(amdgpu_gfx908::v143, output_vec_len ); + case 400: return makeRegisterExpression(amdgpu_gfx908::v144, output_vec_len ); + case 401: return makeRegisterExpression(amdgpu_gfx908::v145, output_vec_len ); + case 402: return makeRegisterExpression(amdgpu_gfx908::v146, output_vec_len ); + case 403: return makeRegisterExpression(amdgpu_gfx908::v147, output_vec_len ); + case 404: return makeRegisterExpression(amdgpu_gfx908::v148, output_vec_len ); + case 405: return makeRegisterExpression(amdgpu_gfx908::v149, output_vec_len ); + case 406: return makeRegisterExpression(amdgpu_gfx908::v150, output_vec_len ); + case 407: return makeRegisterExpression(amdgpu_gfx908::v151, output_vec_len ); + case 408: return makeRegisterExpression(amdgpu_gfx908::v152, output_vec_len ); + case 409: return makeRegisterExpression(amdgpu_gfx908::v153, output_vec_len ); + case 410: return makeRegisterExpression(amdgpu_gfx908::v154, output_vec_len ); + case 411: return makeRegisterExpression(amdgpu_gfx908::v155, output_vec_len ); + case 412: return makeRegisterExpression(amdgpu_gfx908::v156, output_vec_len ); + case 413: return makeRegisterExpression(amdgpu_gfx908::v157, output_vec_len ); + case 414: return makeRegisterExpression(amdgpu_gfx908::v158, output_vec_len ); + case 415: return makeRegisterExpression(amdgpu_gfx908::v159, output_vec_len ); + case 416: return makeRegisterExpression(amdgpu_gfx908::v160, output_vec_len ); + case 417: return makeRegisterExpression(amdgpu_gfx908::v161, output_vec_len ); + case 418: return makeRegisterExpression(amdgpu_gfx908::v162, output_vec_len ); + case 419: return makeRegisterExpression(amdgpu_gfx908::v163, output_vec_len ); + case 420: return makeRegisterExpression(amdgpu_gfx908::v164, output_vec_len ); + case 421: return makeRegisterExpression(amdgpu_gfx908::v165, output_vec_len ); + case 422: return makeRegisterExpression(amdgpu_gfx908::v166, output_vec_len ); + case 423: return makeRegisterExpression(amdgpu_gfx908::v167, output_vec_len ); + case 424: return makeRegisterExpression(amdgpu_gfx908::v168, output_vec_len ); + case 425: return makeRegisterExpression(amdgpu_gfx908::v169, output_vec_len ); + case 426: return makeRegisterExpression(amdgpu_gfx908::v170, output_vec_len ); + case 427: return makeRegisterExpression(amdgpu_gfx908::v171, output_vec_len ); + case 428: return makeRegisterExpression(amdgpu_gfx908::v172, output_vec_len ); + case 429: return makeRegisterExpression(amdgpu_gfx908::v173, output_vec_len ); + case 430: return makeRegisterExpression(amdgpu_gfx908::v174, output_vec_len ); + case 431: return makeRegisterExpression(amdgpu_gfx908::v175, output_vec_len ); + case 432: return makeRegisterExpression(amdgpu_gfx908::v176, output_vec_len ); + case 433: return makeRegisterExpression(amdgpu_gfx908::v177, output_vec_len ); + case 434: return makeRegisterExpression(amdgpu_gfx908::v178, output_vec_len ); + case 435: return makeRegisterExpression(amdgpu_gfx908::v179, output_vec_len ); + case 436: return makeRegisterExpression(amdgpu_gfx908::v180, output_vec_len ); + case 437: return makeRegisterExpression(amdgpu_gfx908::v181, output_vec_len ); + case 438: return makeRegisterExpression(amdgpu_gfx908::v182, output_vec_len ); + case 439: return makeRegisterExpression(amdgpu_gfx908::v183, output_vec_len ); + case 440: return makeRegisterExpression(amdgpu_gfx908::v184, output_vec_len ); + case 441: return makeRegisterExpression(amdgpu_gfx908::v185, output_vec_len ); + case 442: return makeRegisterExpression(amdgpu_gfx908::v186, output_vec_len ); + case 443: return makeRegisterExpression(amdgpu_gfx908::v187, output_vec_len ); + case 444: return makeRegisterExpression(amdgpu_gfx908::v188, output_vec_len ); + case 445: return makeRegisterExpression(amdgpu_gfx908::v189, output_vec_len ); + case 446: return makeRegisterExpression(amdgpu_gfx908::v190, output_vec_len ); + case 447: return makeRegisterExpression(amdgpu_gfx908::v191, output_vec_len ); + case 448: return makeRegisterExpression(amdgpu_gfx908::v192, output_vec_len ); + case 449: return makeRegisterExpression(amdgpu_gfx908::v193, output_vec_len ); + case 450: return makeRegisterExpression(amdgpu_gfx908::v194, output_vec_len ); + case 451: return makeRegisterExpression(amdgpu_gfx908::v195, output_vec_len ); + case 452: return makeRegisterExpression(amdgpu_gfx908::v196, output_vec_len ); + case 453: return makeRegisterExpression(amdgpu_gfx908::v197, output_vec_len ); + case 454: return makeRegisterExpression(amdgpu_gfx908::v198, output_vec_len ); + case 455: return makeRegisterExpression(amdgpu_gfx908::v199, output_vec_len ); + case 456: return makeRegisterExpression(amdgpu_gfx908::v200, output_vec_len ); + case 457: return makeRegisterExpression(amdgpu_gfx908::v201, output_vec_len ); + case 458: return makeRegisterExpression(amdgpu_gfx908::v202, output_vec_len ); + case 459: return makeRegisterExpression(amdgpu_gfx908::v203, output_vec_len ); + case 460: return makeRegisterExpression(amdgpu_gfx908::v204, output_vec_len ); + case 461: return makeRegisterExpression(amdgpu_gfx908::v205, output_vec_len ); + case 462: return makeRegisterExpression(amdgpu_gfx908::v206, output_vec_len ); + case 463: return makeRegisterExpression(amdgpu_gfx908::v207, output_vec_len ); + case 464: return makeRegisterExpression(amdgpu_gfx908::v208, output_vec_len ); + case 465: return makeRegisterExpression(amdgpu_gfx908::v209, output_vec_len ); + case 466: return makeRegisterExpression(amdgpu_gfx908::v210, output_vec_len ); + case 467: return makeRegisterExpression(amdgpu_gfx908::v211, output_vec_len ); + case 468: return makeRegisterExpression(amdgpu_gfx908::v212, output_vec_len ); + case 469: return makeRegisterExpression(amdgpu_gfx908::v213, output_vec_len ); + case 470: return makeRegisterExpression(amdgpu_gfx908::v214, output_vec_len ); + case 471: return makeRegisterExpression(amdgpu_gfx908::v215, output_vec_len ); + case 472: return makeRegisterExpression(amdgpu_gfx908::v216, output_vec_len ); + case 473: return makeRegisterExpression(amdgpu_gfx908::v217, output_vec_len ); + case 474: return makeRegisterExpression(amdgpu_gfx908::v218, output_vec_len ); + case 475: return makeRegisterExpression(amdgpu_gfx908::v219, output_vec_len ); + case 476: return makeRegisterExpression(amdgpu_gfx908::v220, output_vec_len ); + case 477: return makeRegisterExpression(amdgpu_gfx908::v221, output_vec_len ); + case 478: return makeRegisterExpression(amdgpu_gfx908::v222, output_vec_len ); + case 479: return makeRegisterExpression(amdgpu_gfx908::v223, output_vec_len ); + case 480: return makeRegisterExpression(amdgpu_gfx908::v224, output_vec_len ); + case 481: return makeRegisterExpression(amdgpu_gfx908::v225, output_vec_len ); + case 482: return makeRegisterExpression(amdgpu_gfx908::v226, output_vec_len ); + case 483: return makeRegisterExpression(amdgpu_gfx908::v227, output_vec_len ); + case 484: return makeRegisterExpression(amdgpu_gfx908::v228, output_vec_len ); + case 485: return makeRegisterExpression(amdgpu_gfx908::v229, output_vec_len ); + case 486: return makeRegisterExpression(amdgpu_gfx908::v230, output_vec_len ); + case 487: return makeRegisterExpression(amdgpu_gfx908::v231, output_vec_len ); + case 488: return makeRegisterExpression(amdgpu_gfx908::v232, output_vec_len ); + case 489: return makeRegisterExpression(amdgpu_gfx908::v233, output_vec_len ); + case 490: return makeRegisterExpression(amdgpu_gfx908::v234, output_vec_len ); + case 491: return makeRegisterExpression(amdgpu_gfx908::v235, output_vec_len ); + case 492: return makeRegisterExpression(amdgpu_gfx908::v236, output_vec_len ); + case 493: return makeRegisterExpression(amdgpu_gfx908::v237, output_vec_len ); + case 494: return makeRegisterExpression(amdgpu_gfx908::v238, output_vec_len ); + case 495: return makeRegisterExpression(amdgpu_gfx908::v239, output_vec_len ); + case 496: return makeRegisterExpression(amdgpu_gfx908::v240, output_vec_len ); + case 497: return makeRegisterExpression(amdgpu_gfx908::v241, output_vec_len ); + case 498: return makeRegisterExpression(amdgpu_gfx908::v242, output_vec_len ); + case 499: return makeRegisterExpression(amdgpu_gfx908::v243, output_vec_len ); + case 500: return makeRegisterExpression(amdgpu_gfx908::v244, output_vec_len ); + case 501: return makeRegisterExpression(amdgpu_gfx908::v245, output_vec_len ); + case 502: return makeRegisterExpression(amdgpu_gfx908::v246, output_vec_len ); + case 503: return makeRegisterExpression(amdgpu_gfx908::v247, output_vec_len ); + case 504: return makeRegisterExpression(amdgpu_gfx908::v248, output_vec_len ); + case 505: return makeRegisterExpression(amdgpu_gfx908::v249, output_vec_len ); + case 506: return makeRegisterExpression(amdgpu_gfx908::v250, output_vec_len ); + case 507: return makeRegisterExpression(amdgpu_gfx908::v251, output_vec_len ); + case 508: return makeRegisterExpression(amdgpu_gfx908::v252, output_vec_len ); + case 509: return makeRegisterExpression(amdgpu_gfx908::v253, output_vec_len ); + case 510: return makeRegisterExpression(amdgpu_gfx908::v254, output_vec_len ); + case 511: return makeRegisterExpression(amdgpu_gfx908::v255, output_vec_len ); + default: return makeRegisterExpression(amdgpu_gfx908::invalid); + } + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SRC_VGPR(uint64_t input, uint32_t output_vec_len) + { + switch (input) { + case 256: return makeRegisterExpression(amdgpu_gfx908::v0, output_vec_len ); + case 257: return makeRegisterExpression(amdgpu_gfx908::v1, output_vec_len ); + case 258: return makeRegisterExpression(amdgpu_gfx908::v2, output_vec_len ); + case 259: return makeRegisterExpression(amdgpu_gfx908::v3, output_vec_len ); + case 260: return makeRegisterExpression(amdgpu_gfx908::v4, output_vec_len ); + case 261: return makeRegisterExpression(amdgpu_gfx908::v5, output_vec_len ); + case 262: return makeRegisterExpression(amdgpu_gfx908::v6, output_vec_len ); + case 263: return makeRegisterExpression(amdgpu_gfx908::v7, output_vec_len ); + case 264: return makeRegisterExpression(amdgpu_gfx908::v8, output_vec_len ); + case 265: return makeRegisterExpression(amdgpu_gfx908::v9, output_vec_len ); + case 266: return makeRegisterExpression(amdgpu_gfx908::v10, output_vec_len ); + case 267: return makeRegisterExpression(amdgpu_gfx908::v11, output_vec_len ); + case 268: return makeRegisterExpression(amdgpu_gfx908::v12, output_vec_len ); + case 269: return makeRegisterExpression(amdgpu_gfx908::v13, output_vec_len ); + case 270: return makeRegisterExpression(amdgpu_gfx908::v14, output_vec_len ); + case 271: return makeRegisterExpression(amdgpu_gfx908::v15, output_vec_len ); + case 272: return makeRegisterExpression(amdgpu_gfx908::v16, output_vec_len ); + case 273: return makeRegisterExpression(amdgpu_gfx908::v17, output_vec_len ); + case 274: return makeRegisterExpression(amdgpu_gfx908::v18, output_vec_len ); + case 275: return makeRegisterExpression(amdgpu_gfx908::v19, output_vec_len ); + case 276: return makeRegisterExpression(amdgpu_gfx908::v20, output_vec_len ); + case 277: return makeRegisterExpression(amdgpu_gfx908::v21, output_vec_len ); + case 278: return makeRegisterExpression(amdgpu_gfx908::v22, output_vec_len ); + case 279: return makeRegisterExpression(amdgpu_gfx908::v23, output_vec_len ); + case 280: return makeRegisterExpression(amdgpu_gfx908::v24, output_vec_len ); + case 281: return makeRegisterExpression(amdgpu_gfx908::v25, output_vec_len ); + case 282: return makeRegisterExpression(amdgpu_gfx908::v26, output_vec_len ); + case 283: return makeRegisterExpression(amdgpu_gfx908::v27, output_vec_len ); + case 284: return makeRegisterExpression(amdgpu_gfx908::v28, output_vec_len ); + case 285: return makeRegisterExpression(amdgpu_gfx908::v29, output_vec_len ); + case 286: return makeRegisterExpression(amdgpu_gfx908::v30, output_vec_len ); + case 287: return makeRegisterExpression(amdgpu_gfx908::v31, output_vec_len ); + case 288: return makeRegisterExpression(amdgpu_gfx908::v32, output_vec_len ); + case 289: return makeRegisterExpression(amdgpu_gfx908::v33, output_vec_len ); + case 290: return makeRegisterExpression(amdgpu_gfx908::v34, output_vec_len ); + case 291: return makeRegisterExpression(amdgpu_gfx908::v35, output_vec_len ); + case 292: return makeRegisterExpression(amdgpu_gfx908::v36, output_vec_len ); + case 293: return makeRegisterExpression(amdgpu_gfx908::v37, output_vec_len ); + case 294: return makeRegisterExpression(amdgpu_gfx908::v38, output_vec_len ); + case 295: return makeRegisterExpression(amdgpu_gfx908::v39, output_vec_len ); + case 296: return makeRegisterExpression(amdgpu_gfx908::v40, output_vec_len ); + case 297: return makeRegisterExpression(amdgpu_gfx908::v41, output_vec_len ); + case 298: return makeRegisterExpression(amdgpu_gfx908::v42, output_vec_len ); + case 299: return makeRegisterExpression(amdgpu_gfx908::v43, output_vec_len ); + case 300: return makeRegisterExpression(amdgpu_gfx908::v44, output_vec_len ); + case 301: return makeRegisterExpression(amdgpu_gfx908::v45, output_vec_len ); + case 302: return makeRegisterExpression(amdgpu_gfx908::v46, output_vec_len ); + case 303: return makeRegisterExpression(amdgpu_gfx908::v47, output_vec_len ); + case 304: return makeRegisterExpression(amdgpu_gfx908::v48, output_vec_len ); + case 305: return makeRegisterExpression(amdgpu_gfx908::v49, output_vec_len ); + case 306: return makeRegisterExpression(amdgpu_gfx908::v50, output_vec_len ); + case 307: return makeRegisterExpression(amdgpu_gfx908::v51, output_vec_len ); + case 308: return makeRegisterExpression(amdgpu_gfx908::v52, output_vec_len ); + case 309: return makeRegisterExpression(amdgpu_gfx908::v53, output_vec_len ); + case 310: return makeRegisterExpression(amdgpu_gfx908::v54, output_vec_len ); + case 311: return makeRegisterExpression(amdgpu_gfx908::v55, output_vec_len ); + case 312: return makeRegisterExpression(amdgpu_gfx908::v56, output_vec_len ); + case 313: return makeRegisterExpression(amdgpu_gfx908::v57, output_vec_len ); + case 314: return makeRegisterExpression(amdgpu_gfx908::v58, output_vec_len ); + case 315: return makeRegisterExpression(amdgpu_gfx908::v59, output_vec_len ); + case 316: return makeRegisterExpression(amdgpu_gfx908::v60, output_vec_len ); + case 317: return makeRegisterExpression(amdgpu_gfx908::v61, output_vec_len ); + case 318: return makeRegisterExpression(amdgpu_gfx908::v62, output_vec_len ); + case 319: return makeRegisterExpression(amdgpu_gfx908::v63, output_vec_len ); + case 320: return makeRegisterExpression(amdgpu_gfx908::v64, output_vec_len ); + case 321: return makeRegisterExpression(amdgpu_gfx908::v65, output_vec_len ); + case 322: return makeRegisterExpression(amdgpu_gfx908::v66, output_vec_len ); + case 323: return makeRegisterExpression(amdgpu_gfx908::v67, output_vec_len ); + case 324: return makeRegisterExpression(amdgpu_gfx908::v68, output_vec_len ); + case 325: return makeRegisterExpression(amdgpu_gfx908::v69, output_vec_len ); + case 326: return makeRegisterExpression(amdgpu_gfx908::v70, output_vec_len ); + case 327: return makeRegisterExpression(amdgpu_gfx908::v71, output_vec_len ); + case 328: return makeRegisterExpression(amdgpu_gfx908::v72, output_vec_len ); + case 329: return makeRegisterExpression(amdgpu_gfx908::v73, output_vec_len ); + case 330: return makeRegisterExpression(amdgpu_gfx908::v74, output_vec_len ); + case 331: return makeRegisterExpression(amdgpu_gfx908::v75, output_vec_len ); + case 332: return makeRegisterExpression(amdgpu_gfx908::v76, output_vec_len ); + case 333: return makeRegisterExpression(amdgpu_gfx908::v77, output_vec_len ); + case 334: return makeRegisterExpression(amdgpu_gfx908::v78, output_vec_len ); + case 335: return makeRegisterExpression(amdgpu_gfx908::v79, output_vec_len ); + case 336: return makeRegisterExpression(amdgpu_gfx908::v80, output_vec_len ); + case 337: return makeRegisterExpression(amdgpu_gfx908::v81, output_vec_len ); + case 338: return makeRegisterExpression(amdgpu_gfx908::v82, output_vec_len ); + case 339: return makeRegisterExpression(amdgpu_gfx908::v83, output_vec_len ); + case 340: return makeRegisterExpression(amdgpu_gfx908::v84, output_vec_len ); + case 341: return makeRegisterExpression(amdgpu_gfx908::v85, output_vec_len ); + case 342: return makeRegisterExpression(amdgpu_gfx908::v86, output_vec_len ); + case 343: return makeRegisterExpression(amdgpu_gfx908::v87, output_vec_len ); + case 344: return makeRegisterExpression(amdgpu_gfx908::v88, output_vec_len ); + case 345: return makeRegisterExpression(amdgpu_gfx908::v89, output_vec_len ); + case 346: return makeRegisterExpression(amdgpu_gfx908::v90, output_vec_len ); + case 347: return makeRegisterExpression(amdgpu_gfx908::v91, output_vec_len ); + case 348: return makeRegisterExpression(amdgpu_gfx908::v92, output_vec_len ); + case 349: return makeRegisterExpression(amdgpu_gfx908::v93, output_vec_len ); + case 350: return makeRegisterExpression(amdgpu_gfx908::v94, output_vec_len ); + case 351: return makeRegisterExpression(amdgpu_gfx908::v95, output_vec_len ); + case 352: return makeRegisterExpression(amdgpu_gfx908::v96, output_vec_len ); + case 353: return makeRegisterExpression(amdgpu_gfx908::v97, output_vec_len ); + case 354: return makeRegisterExpression(amdgpu_gfx908::v98, output_vec_len ); + case 355: return makeRegisterExpression(amdgpu_gfx908::v99, output_vec_len ); + case 356: return makeRegisterExpression(amdgpu_gfx908::v100, output_vec_len ); + case 357: return makeRegisterExpression(amdgpu_gfx908::v101, output_vec_len ); + case 358: return makeRegisterExpression(amdgpu_gfx908::v102, output_vec_len ); + case 359: return makeRegisterExpression(amdgpu_gfx908::v103, output_vec_len ); + case 360: return makeRegisterExpression(amdgpu_gfx908::v104, output_vec_len ); + case 361: return makeRegisterExpression(amdgpu_gfx908::v105, output_vec_len ); + case 362: return makeRegisterExpression(amdgpu_gfx908::v106, output_vec_len ); + case 363: return makeRegisterExpression(amdgpu_gfx908::v107, output_vec_len ); + case 364: return makeRegisterExpression(amdgpu_gfx908::v108, output_vec_len ); + case 365: return makeRegisterExpression(amdgpu_gfx908::v109, output_vec_len ); + case 366: return makeRegisterExpression(amdgpu_gfx908::v110, output_vec_len ); + case 367: return makeRegisterExpression(amdgpu_gfx908::v111, output_vec_len ); + case 368: return makeRegisterExpression(amdgpu_gfx908::v112, output_vec_len ); + case 369: return makeRegisterExpression(amdgpu_gfx908::v113, output_vec_len ); + case 370: return makeRegisterExpression(amdgpu_gfx908::v114, output_vec_len ); + case 371: return makeRegisterExpression(amdgpu_gfx908::v115, output_vec_len ); + case 372: return makeRegisterExpression(amdgpu_gfx908::v116, output_vec_len ); + case 373: return makeRegisterExpression(amdgpu_gfx908::v117, output_vec_len ); + case 374: return makeRegisterExpression(amdgpu_gfx908::v118, output_vec_len ); + case 375: return makeRegisterExpression(amdgpu_gfx908::v119, output_vec_len ); + case 376: return makeRegisterExpression(amdgpu_gfx908::v120, output_vec_len ); + case 377: return makeRegisterExpression(amdgpu_gfx908::v121, output_vec_len ); + case 378: return makeRegisterExpression(amdgpu_gfx908::v122, output_vec_len ); + case 379: return makeRegisterExpression(amdgpu_gfx908::v123, output_vec_len ); + case 380: return makeRegisterExpression(amdgpu_gfx908::v124, output_vec_len ); + case 381: return makeRegisterExpression(amdgpu_gfx908::v125, output_vec_len ); + case 382: return makeRegisterExpression(amdgpu_gfx908::v126, output_vec_len ); + case 383: return makeRegisterExpression(amdgpu_gfx908::v127, output_vec_len ); + case 384: return makeRegisterExpression(amdgpu_gfx908::v128, output_vec_len ); + case 385: return makeRegisterExpression(amdgpu_gfx908::v129, output_vec_len ); + case 386: return makeRegisterExpression(amdgpu_gfx908::v130, output_vec_len ); + case 387: return makeRegisterExpression(amdgpu_gfx908::v131, output_vec_len ); + case 388: return makeRegisterExpression(amdgpu_gfx908::v132, output_vec_len ); + case 389: return makeRegisterExpression(amdgpu_gfx908::v133, output_vec_len ); + case 390: return makeRegisterExpression(amdgpu_gfx908::v134, output_vec_len ); + case 391: return makeRegisterExpression(amdgpu_gfx908::v135, output_vec_len ); + case 392: return makeRegisterExpression(amdgpu_gfx908::v136, output_vec_len ); + case 393: return makeRegisterExpression(amdgpu_gfx908::v137, output_vec_len ); + case 394: return makeRegisterExpression(amdgpu_gfx908::v138, output_vec_len ); + case 395: return makeRegisterExpression(amdgpu_gfx908::v139, output_vec_len ); + case 396: return makeRegisterExpression(amdgpu_gfx908::v140, output_vec_len ); + case 397: return makeRegisterExpression(amdgpu_gfx908::v141, output_vec_len ); + case 398: return makeRegisterExpression(amdgpu_gfx908::v142, output_vec_len ); + case 399: return makeRegisterExpression(amdgpu_gfx908::v143, output_vec_len ); + case 400: return makeRegisterExpression(amdgpu_gfx908::v144, output_vec_len ); + case 401: return makeRegisterExpression(amdgpu_gfx908::v145, output_vec_len ); + case 402: return makeRegisterExpression(amdgpu_gfx908::v146, output_vec_len ); + case 403: return makeRegisterExpression(amdgpu_gfx908::v147, output_vec_len ); + case 404: return makeRegisterExpression(amdgpu_gfx908::v148, output_vec_len ); + case 405: return makeRegisterExpression(amdgpu_gfx908::v149, output_vec_len ); + case 406: return makeRegisterExpression(amdgpu_gfx908::v150, output_vec_len ); + case 407: return makeRegisterExpression(amdgpu_gfx908::v151, output_vec_len ); + case 408: return makeRegisterExpression(amdgpu_gfx908::v152, output_vec_len ); + case 409: return makeRegisterExpression(amdgpu_gfx908::v153, output_vec_len ); + case 410: return makeRegisterExpression(amdgpu_gfx908::v154, output_vec_len ); + case 411: return makeRegisterExpression(amdgpu_gfx908::v155, output_vec_len ); + case 412: return makeRegisterExpression(amdgpu_gfx908::v156, output_vec_len ); + case 413: return makeRegisterExpression(amdgpu_gfx908::v157, output_vec_len ); + case 414: return makeRegisterExpression(amdgpu_gfx908::v158, output_vec_len ); + case 415: return makeRegisterExpression(amdgpu_gfx908::v159, output_vec_len ); + case 416: return makeRegisterExpression(amdgpu_gfx908::v160, output_vec_len ); + case 417: return makeRegisterExpression(amdgpu_gfx908::v161, output_vec_len ); + case 418: return makeRegisterExpression(amdgpu_gfx908::v162, output_vec_len ); + case 419: return makeRegisterExpression(amdgpu_gfx908::v163, output_vec_len ); + case 420: return makeRegisterExpression(amdgpu_gfx908::v164, output_vec_len ); + case 421: return makeRegisterExpression(amdgpu_gfx908::v165, output_vec_len ); + case 422: return makeRegisterExpression(amdgpu_gfx908::v166, output_vec_len ); + case 423: return makeRegisterExpression(amdgpu_gfx908::v167, output_vec_len ); + case 424: return makeRegisterExpression(amdgpu_gfx908::v168, output_vec_len ); + case 425: return makeRegisterExpression(amdgpu_gfx908::v169, output_vec_len ); + case 426: return makeRegisterExpression(amdgpu_gfx908::v170, output_vec_len ); + case 427: return makeRegisterExpression(amdgpu_gfx908::v171, output_vec_len ); + case 428: return makeRegisterExpression(amdgpu_gfx908::v172, output_vec_len ); + case 429: return makeRegisterExpression(amdgpu_gfx908::v173, output_vec_len ); + case 430: return makeRegisterExpression(amdgpu_gfx908::v174, output_vec_len ); + case 431: return makeRegisterExpression(amdgpu_gfx908::v175, output_vec_len ); + case 432: return makeRegisterExpression(amdgpu_gfx908::v176, output_vec_len ); + case 433: return makeRegisterExpression(amdgpu_gfx908::v177, output_vec_len ); + case 434: return makeRegisterExpression(amdgpu_gfx908::v178, output_vec_len ); + case 435: return makeRegisterExpression(amdgpu_gfx908::v179, output_vec_len ); + case 436: return makeRegisterExpression(amdgpu_gfx908::v180, output_vec_len ); + case 437: return makeRegisterExpression(amdgpu_gfx908::v181, output_vec_len ); + case 438: return makeRegisterExpression(amdgpu_gfx908::v182, output_vec_len ); + case 439: return makeRegisterExpression(amdgpu_gfx908::v183, output_vec_len ); + case 440: return makeRegisterExpression(amdgpu_gfx908::v184, output_vec_len ); + case 441: return makeRegisterExpression(amdgpu_gfx908::v185, output_vec_len ); + case 442: return makeRegisterExpression(amdgpu_gfx908::v186, output_vec_len ); + case 443: return makeRegisterExpression(amdgpu_gfx908::v187, output_vec_len ); + case 444: return makeRegisterExpression(amdgpu_gfx908::v188, output_vec_len ); + case 445: return makeRegisterExpression(amdgpu_gfx908::v189, output_vec_len ); + case 446: return makeRegisterExpression(amdgpu_gfx908::v190, output_vec_len ); + case 447: return makeRegisterExpression(amdgpu_gfx908::v191, output_vec_len ); + case 448: return makeRegisterExpression(amdgpu_gfx908::v192, output_vec_len ); + case 449: return makeRegisterExpression(amdgpu_gfx908::v193, output_vec_len ); + case 450: return makeRegisterExpression(amdgpu_gfx908::v194, output_vec_len ); + case 451: return makeRegisterExpression(amdgpu_gfx908::v195, output_vec_len ); + case 452: return makeRegisterExpression(amdgpu_gfx908::v196, output_vec_len ); + case 453: return makeRegisterExpression(amdgpu_gfx908::v197, output_vec_len ); + case 454: return makeRegisterExpression(amdgpu_gfx908::v198, output_vec_len ); + case 455: return makeRegisterExpression(amdgpu_gfx908::v199, output_vec_len ); + case 456: return makeRegisterExpression(amdgpu_gfx908::v200, output_vec_len ); + case 457: return makeRegisterExpression(amdgpu_gfx908::v201, output_vec_len ); + case 458: return makeRegisterExpression(amdgpu_gfx908::v202, output_vec_len ); + case 459: return makeRegisterExpression(amdgpu_gfx908::v203, output_vec_len ); + case 460: return makeRegisterExpression(amdgpu_gfx908::v204, output_vec_len ); + case 461: return makeRegisterExpression(amdgpu_gfx908::v205, output_vec_len ); + case 462: return makeRegisterExpression(amdgpu_gfx908::v206, output_vec_len ); + case 463: return makeRegisterExpression(amdgpu_gfx908::v207, output_vec_len ); + case 464: return makeRegisterExpression(amdgpu_gfx908::v208, output_vec_len ); + case 465: return makeRegisterExpression(amdgpu_gfx908::v209, output_vec_len ); + case 466: return makeRegisterExpression(amdgpu_gfx908::v210, output_vec_len ); + case 467: return makeRegisterExpression(amdgpu_gfx908::v211, output_vec_len ); + case 468: return makeRegisterExpression(amdgpu_gfx908::v212, output_vec_len ); + case 469: return makeRegisterExpression(amdgpu_gfx908::v213, output_vec_len ); + case 470: return makeRegisterExpression(amdgpu_gfx908::v214, output_vec_len ); + case 471: return makeRegisterExpression(amdgpu_gfx908::v215, output_vec_len ); + case 472: return makeRegisterExpression(amdgpu_gfx908::v216, output_vec_len ); + case 473: return makeRegisterExpression(amdgpu_gfx908::v217, output_vec_len ); + case 474: return makeRegisterExpression(amdgpu_gfx908::v218, output_vec_len ); + case 475: return makeRegisterExpression(amdgpu_gfx908::v219, output_vec_len ); + case 476: return makeRegisterExpression(amdgpu_gfx908::v220, output_vec_len ); + case 477: return makeRegisterExpression(amdgpu_gfx908::v221, output_vec_len ); + case 478: return makeRegisterExpression(amdgpu_gfx908::v222, output_vec_len ); + case 479: return makeRegisterExpression(amdgpu_gfx908::v223, output_vec_len ); + case 480: return makeRegisterExpression(amdgpu_gfx908::v224, output_vec_len ); + case 481: return makeRegisterExpression(amdgpu_gfx908::v225, output_vec_len ); + case 482: return makeRegisterExpression(amdgpu_gfx908::v226, output_vec_len ); + case 483: return makeRegisterExpression(amdgpu_gfx908::v227, output_vec_len ); + case 484: return makeRegisterExpression(amdgpu_gfx908::v228, output_vec_len ); + case 485: return makeRegisterExpression(amdgpu_gfx908::v229, output_vec_len ); + case 486: return makeRegisterExpression(amdgpu_gfx908::v230, output_vec_len ); + case 487: return makeRegisterExpression(amdgpu_gfx908::v231, output_vec_len ); + case 488: return makeRegisterExpression(amdgpu_gfx908::v232, output_vec_len ); + case 489: return makeRegisterExpression(amdgpu_gfx908::v233, output_vec_len ); + case 490: return makeRegisterExpression(amdgpu_gfx908::v234, output_vec_len ); + case 491: return makeRegisterExpression(amdgpu_gfx908::v235, output_vec_len ); + case 492: return makeRegisterExpression(amdgpu_gfx908::v236, output_vec_len ); + case 493: return makeRegisterExpression(amdgpu_gfx908::v237, output_vec_len ); + case 494: return makeRegisterExpression(amdgpu_gfx908::v238, output_vec_len ); + case 495: return makeRegisterExpression(amdgpu_gfx908::v239, output_vec_len ); + case 496: return makeRegisterExpression(amdgpu_gfx908::v240, output_vec_len ); + case 497: return makeRegisterExpression(amdgpu_gfx908::v241, output_vec_len ); + case 498: return makeRegisterExpression(amdgpu_gfx908::v242, output_vec_len ); + case 499: return makeRegisterExpression(amdgpu_gfx908::v243, output_vec_len ); + case 500: return makeRegisterExpression(amdgpu_gfx908::v244, output_vec_len ); + case 501: return makeRegisterExpression(amdgpu_gfx908::v245, output_vec_len ); + case 502: return makeRegisterExpression(amdgpu_gfx908::v246, output_vec_len ); + case 503: return makeRegisterExpression(amdgpu_gfx908::v247, output_vec_len ); + case 504: return makeRegisterExpression(amdgpu_gfx908::v248, output_vec_len ); + case 505: return makeRegisterExpression(amdgpu_gfx908::v249, output_vec_len ); + case 506: return makeRegisterExpression(amdgpu_gfx908::v250, output_vec_len ); + case 507: return makeRegisterExpression(amdgpu_gfx908::v251, output_vec_len ); + case 508: return makeRegisterExpression(amdgpu_gfx908::v252, output_vec_len ); + case 509: return makeRegisterExpression(amdgpu_gfx908::v253, output_vec_len ); + case 510: return makeRegisterExpression(amdgpu_gfx908::v254, output_vec_len ); + case 511: return makeRegisterExpression(amdgpu_gfx908::v255, output_vec_len ); + default: return makeRegisterExpression(amdgpu_gfx908::invalid); + } + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SRC_VGPR_OR_ACCVGPR(uint64_t input, uint32_t output_vec_len) + { + switch (input) { + case 256: return makeRegisterExpression(amdgpu_gfx908::v0, output_vec_len ); + case 257: return makeRegisterExpression(amdgpu_gfx908::v1, output_vec_len ); + case 258: return makeRegisterExpression(amdgpu_gfx908::v2, output_vec_len ); + case 259: return makeRegisterExpression(amdgpu_gfx908::v3, output_vec_len ); + case 260: return makeRegisterExpression(amdgpu_gfx908::v4, output_vec_len ); + case 261: return makeRegisterExpression(amdgpu_gfx908::v5, output_vec_len ); + case 262: return makeRegisterExpression(amdgpu_gfx908::v6, output_vec_len ); + case 263: return makeRegisterExpression(amdgpu_gfx908::v7, output_vec_len ); + case 264: return makeRegisterExpression(amdgpu_gfx908::v8, output_vec_len ); + case 265: return makeRegisterExpression(amdgpu_gfx908::v9, output_vec_len ); + case 266: return makeRegisterExpression(amdgpu_gfx908::v10, output_vec_len ); + case 267: return makeRegisterExpression(amdgpu_gfx908::v11, output_vec_len ); + case 268: return makeRegisterExpression(amdgpu_gfx908::v12, output_vec_len ); + case 269: return makeRegisterExpression(amdgpu_gfx908::v13, output_vec_len ); + case 270: return makeRegisterExpression(amdgpu_gfx908::v14, output_vec_len ); + case 271: return makeRegisterExpression(amdgpu_gfx908::v15, output_vec_len ); + case 272: return makeRegisterExpression(amdgpu_gfx908::v16, output_vec_len ); + case 273: return makeRegisterExpression(amdgpu_gfx908::v17, output_vec_len ); + case 274: return makeRegisterExpression(amdgpu_gfx908::v18, output_vec_len ); + case 275: return makeRegisterExpression(amdgpu_gfx908::v19, output_vec_len ); + case 276: return makeRegisterExpression(amdgpu_gfx908::v20, output_vec_len ); + case 277: return makeRegisterExpression(amdgpu_gfx908::v21, output_vec_len ); + case 278: return makeRegisterExpression(amdgpu_gfx908::v22, output_vec_len ); + case 279: return makeRegisterExpression(amdgpu_gfx908::v23, output_vec_len ); + case 280: return makeRegisterExpression(amdgpu_gfx908::v24, output_vec_len ); + case 281: return makeRegisterExpression(amdgpu_gfx908::v25, output_vec_len ); + case 282: return makeRegisterExpression(amdgpu_gfx908::v26, output_vec_len ); + case 283: return makeRegisterExpression(amdgpu_gfx908::v27, output_vec_len ); + case 284: return makeRegisterExpression(amdgpu_gfx908::v28, output_vec_len ); + case 285: return makeRegisterExpression(amdgpu_gfx908::v29, output_vec_len ); + case 286: return makeRegisterExpression(amdgpu_gfx908::v30, output_vec_len ); + case 287: return makeRegisterExpression(amdgpu_gfx908::v31, output_vec_len ); + case 288: return makeRegisterExpression(amdgpu_gfx908::v32, output_vec_len ); + case 289: return makeRegisterExpression(amdgpu_gfx908::v33, output_vec_len ); + case 290: return makeRegisterExpression(amdgpu_gfx908::v34, output_vec_len ); + case 291: return makeRegisterExpression(amdgpu_gfx908::v35, output_vec_len ); + case 292: return makeRegisterExpression(amdgpu_gfx908::v36, output_vec_len ); + case 293: return makeRegisterExpression(amdgpu_gfx908::v37, output_vec_len ); + case 294: return makeRegisterExpression(amdgpu_gfx908::v38, output_vec_len ); + case 295: return makeRegisterExpression(amdgpu_gfx908::v39, output_vec_len ); + case 296: return makeRegisterExpression(amdgpu_gfx908::v40, output_vec_len ); + case 297: return makeRegisterExpression(amdgpu_gfx908::v41, output_vec_len ); + case 298: return makeRegisterExpression(amdgpu_gfx908::v42, output_vec_len ); + case 299: return makeRegisterExpression(amdgpu_gfx908::v43, output_vec_len ); + case 300: return makeRegisterExpression(amdgpu_gfx908::v44, output_vec_len ); + case 301: return makeRegisterExpression(amdgpu_gfx908::v45, output_vec_len ); + case 302: return makeRegisterExpression(amdgpu_gfx908::v46, output_vec_len ); + case 303: return makeRegisterExpression(amdgpu_gfx908::v47, output_vec_len ); + case 304: return makeRegisterExpression(amdgpu_gfx908::v48, output_vec_len ); + case 305: return makeRegisterExpression(amdgpu_gfx908::v49, output_vec_len ); + case 306: return makeRegisterExpression(amdgpu_gfx908::v50, output_vec_len ); + case 307: return makeRegisterExpression(amdgpu_gfx908::v51, output_vec_len ); + case 308: return makeRegisterExpression(amdgpu_gfx908::v52, output_vec_len ); + case 309: return makeRegisterExpression(amdgpu_gfx908::v53, output_vec_len ); + case 310: return makeRegisterExpression(amdgpu_gfx908::v54, output_vec_len ); + case 311: return makeRegisterExpression(amdgpu_gfx908::v55, output_vec_len ); + case 312: return makeRegisterExpression(amdgpu_gfx908::v56, output_vec_len ); + case 313: return makeRegisterExpression(amdgpu_gfx908::v57, output_vec_len ); + case 314: return makeRegisterExpression(amdgpu_gfx908::v58, output_vec_len ); + case 315: return makeRegisterExpression(amdgpu_gfx908::v59, output_vec_len ); + case 316: return makeRegisterExpression(amdgpu_gfx908::v60, output_vec_len ); + case 317: return makeRegisterExpression(amdgpu_gfx908::v61, output_vec_len ); + case 318: return makeRegisterExpression(amdgpu_gfx908::v62, output_vec_len ); + case 319: return makeRegisterExpression(amdgpu_gfx908::v63, output_vec_len ); + case 320: return makeRegisterExpression(amdgpu_gfx908::v64, output_vec_len ); + case 321: return makeRegisterExpression(amdgpu_gfx908::v65, output_vec_len ); + case 322: return makeRegisterExpression(amdgpu_gfx908::v66, output_vec_len ); + case 323: return makeRegisterExpression(amdgpu_gfx908::v67, output_vec_len ); + case 324: return makeRegisterExpression(amdgpu_gfx908::v68, output_vec_len ); + case 325: return makeRegisterExpression(amdgpu_gfx908::v69, output_vec_len ); + case 326: return makeRegisterExpression(amdgpu_gfx908::v70, output_vec_len ); + case 327: return makeRegisterExpression(amdgpu_gfx908::v71, output_vec_len ); + case 328: return makeRegisterExpression(amdgpu_gfx908::v72, output_vec_len ); + case 329: return makeRegisterExpression(amdgpu_gfx908::v73, output_vec_len ); + case 330: return makeRegisterExpression(amdgpu_gfx908::v74, output_vec_len ); + case 331: return makeRegisterExpression(amdgpu_gfx908::v75, output_vec_len ); + case 332: return makeRegisterExpression(amdgpu_gfx908::v76, output_vec_len ); + case 333: return makeRegisterExpression(amdgpu_gfx908::v77, output_vec_len ); + case 334: return makeRegisterExpression(amdgpu_gfx908::v78, output_vec_len ); + case 335: return makeRegisterExpression(amdgpu_gfx908::v79, output_vec_len ); + case 336: return makeRegisterExpression(amdgpu_gfx908::v80, output_vec_len ); + case 337: return makeRegisterExpression(amdgpu_gfx908::v81, output_vec_len ); + case 338: return makeRegisterExpression(amdgpu_gfx908::v82, output_vec_len ); + case 339: return makeRegisterExpression(amdgpu_gfx908::v83, output_vec_len ); + case 340: return makeRegisterExpression(amdgpu_gfx908::v84, output_vec_len ); + case 341: return makeRegisterExpression(amdgpu_gfx908::v85, output_vec_len ); + case 342: return makeRegisterExpression(amdgpu_gfx908::v86, output_vec_len ); + case 343: return makeRegisterExpression(amdgpu_gfx908::v87, output_vec_len ); + case 344: return makeRegisterExpression(amdgpu_gfx908::v88, output_vec_len ); + case 345: return makeRegisterExpression(amdgpu_gfx908::v89, output_vec_len ); + case 346: return makeRegisterExpression(amdgpu_gfx908::v90, output_vec_len ); + case 347: return makeRegisterExpression(amdgpu_gfx908::v91, output_vec_len ); + case 348: return makeRegisterExpression(amdgpu_gfx908::v92, output_vec_len ); + case 349: return makeRegisterExpression(amdgpu_gfx908::v93, output_vec_len ); + case 350: return makeRegisterExpression(amdgpu_gfx908::v94, output_vec_len ); + case 351: return makeRegisterExpression(amdgpu_gfx908::v95, output_vec_len ); + case 352: return makeRegisterExpression(amdgpu_gfx908::v96, output_vec_len ); + case 353: return makeRegisterExpression(amdgpu_gfx908::v97, output_vec_len ); + case 354: return makeRegisterExpression(amdgpu_gfx908::v98, output_vec_len ); + case 355: return makeRegisterExpression(amdgpu_gfx908::v99, output_vec_len ); + case 356: return makeRegisterExpression(amdgpu_gfx908::v100, output_vec_len ); + case 357: return makeRegisterExpression(amdgpu_gfx908::v101, output_vec_len ); + case 358: return makeRegisterExpression(amdgpu_gfx908::v102, output_vec_len ); + case 359: return makeRegisterExpression(amdgpu_gfx908::v103, output_vec_len ); + case 360: return makeRegisterExpression(amdgpu_gfx908::v104, output_vec_len ); + case 361: return makeRegisterExpression(amdgpu_gfx908::v105, output_vec_len ); + case 362: return makeRegisterExpression(amdgpu_gfx908::v106, output_vec_len ); + case 363: return makeRegisterExpression(amdgpu_gfx908::v107, output_vec_len ); + case 364: return makeRegisterExpression(amdgpu_gfx908::v108, output_vec_len ); + case 365: return makeRegisterExpression(amdgpu_gfx908::v109, output_vec_len ); + case 366: return makeRegisterExpression(amdgpu_gfx908::v110, output_vec_len ); + case 367: return makeRegisterExpression(amdgpu_gfx908::v111, output_vec_len ); + case 368: return makeRegisterExpression(amdgpu_gfx908::v112, output_vec_len ); + case 369: return makeRegisterExpression(amdgpu_gfx908::v113, output_vec_len ); + case 370: return makeRegisterExpression(amdgpu_gfx908::v114, output_vec_len ); + case 371: return makeRegisterExpression(amdgpu_gfx908::v115, output_vec_len ); + case 372: return makeRegisterExpression(amdgpu_gfx908::v116, output_vec_len ); + case 373: return makeRegisterExpression(amdgpu_gfx908::v117, output_vec_len ); + case 374: return makeRegisterExpression(amdgpu_gfx908::v118, output_vec_len ); + case 375: return makeRegisterExpression(amdgpu_gfx908::v119, output_vec_len ); + case 376: return makeRegisterExpression(amdgpu_gfx908::v120, output_vec_len ); + case 377: return makeRegisterExpression(amdgpu_gfx908::v121, output_vec_len ); + case 378: return makeRegisterExpression(amdgpu_gfx908::v122, output_vec_len ); + case 379: return makeRegisterExpression(amdgpu_gfx908::v123, output_vec_len ); + case 380: return makeRegisterExpression(amdgpu_gfx908::v124, output_vec_len ); + case 381: return makeRegisterExpression(amdgpu_gfx908::v125, output_vec_len ); + case 382: return makeRegisterExpression(amdgpu_gfx908::v126, output_vec_len ); + case 383: return makeRegisterExpression(amdgpu_gfx908::v127, output_vec_len ); + case 384: return makeRegisterExpression(amdgpu_gfx908::v128, output_vec_len ); + case 385: return makeRegisterExpression(amdgpu_gfx908::v129, output_vec_len ); + case 386: return makeRegisterExpression(amdgpu_gfx908::v130, output_vec_len ); + case 387: return makeRegisterExpression(amdgpu_gfx908::v131, output_vec_len ); + case 388: return makeRegisterExpression(amdgpu_gfx908::v132, output_vec_len ); + case 389: return makeRegisterExpression(amdgpu_gfx908::v133, output_vec_len ); + case 390: return makeRegisterExpression(amdgpu_gfx908::v134, output_vec_len ); + case 391: return makeRegisterExpression(amdgpu_gfx908::v135, output_vec_len ); + case 392: return makeRegisterExpression(amdgpu_gfx908::v136, output_vec_len ); + case 393: return makeRegisterExpression(amdgpu_gfx908::v137, output_vec_len ); + case 394: return makeRegisterExpression(amdgpu_gfx908::v138, output_vec_len ); + case 395: return makeRegisterExpression(amdgpu_gfx908::v139, output_vec_len ); + case 396: return makeRegisterExpression(amdgpu_gfx908::v140, output_vec_len ); + case 397: return makeRegisterExpression(amdgpu_gfx908::v141, output_vec_len ); + case 398: return makeRegisterExpression(amdgpu_gfx908::v142, output_vec_len ); + case 399: return makeRegisterExpression(amdgpu_gfx908::v143, output_vec_len ); + case 400: return makeRegisterExpression(amdgpu_gfx908::v144, output_vec_len ); + case 401: return makeRegisterExpression(amdgpu_gfx908::v145, output_vec_len ); + case 402: return makeRegisterExpression(amdgpu_gfx908::v146, output_vec_len ); + case 403: return makeRegisterExpression(amdgpu_gfx908::v147, output_vec_len ); + case 404: return makeRegisterExpression(amdgpu_gfx908::v148, output_vec_len ); + case 405: return makeRegisterExpression(amdgpu_gfx908::v149, output_vec_len ); + case 406: return makeRegisterExpression(amdgpu_gfx908::v150, output_vec_len ); + case 407: return makeRegisterExpression(amdgpu_gfx908::v151, output_vec_len ); + case 408: return makeRegisterExpression(amdgpu_gfx908::v152, output_vec_len ); + case 409: return makeRegisterExpression(amdgpu_gfx908::v153, output_vec_len ); + case 410: return makeRegisterExpression(amdgpu_gfx908::v154, output_vec_len ); + case 411: return makeRegisterExpression(amdgpu_gfx908::v155, output_vec_len ); + case 412: return makeRegisterExpression(amdgpu_gfx908::v156, output_vec_len ); + case 413: return makeRegisterExpression(amdgpu_gfx908::v157, output_vec_len ); + case 414: return makeRegisterExpression(amdgpu_gfx908::v158, output_vec_len ); + case 415: return makeRegisterExpression(amdgpu_gfx908::v159, output_vec_len ); + case 416: return makeRegisterExpression(amdgpu_gfx908::v160, output_vec_len ); + case 417: return makeRegisterExpression(amdgpu_gfx908::v161, output_vec_len ); + case 418: return makeRegisterExpression(amdgpu_gfx908::v162, output_vec_len ); + case 419: return makeRegisterExpression(amdgpu_gfx908::v163, output_vec_len ); + case 420: return makeRegisterExpression(amdgpu_gfx908::v164, output_vec_len ); + case 421: return makeRegisterExpression(amdgpu_gfx908::v165, output_vec_len ); + case 422: return makeRegisterExpression(amdgpu_gfx908::v166, output_vec_len ); + case 423: return makeRegisterExpression(amdgpu_gfx908::v167, output_vec_len ); + case 424: return makeRegisterExpression(amdgpu_gfx908::v168, output_vec_len ); + case 425: return makeRegisterExpression(amdgpu_gfx908::v169, output_vec_len ); + case 426: return makeRegisterExpression(amdgpu_gfx908::v170, output_vec_len ); + case 427: return makeRegisterExpression(amdgpu_gfx908::v171, output_vec_len ); + case 428: return makeRegisterExpression(amdgpu_gfx908::v172, output_vec_len ); + case 429: return makeRegisterExpression(amdgpu_gfx908::v173, output_vec_len ); + case 430: return makeRegisterExpression(amdgpu_gfx908::v174, output_vec_len ); + case 431: return makeRegisterExpression(amdgpu_gfx908::v175, output_vec_len ); + case 432: return makeRegisterExpression(amdgpu_gfx908::v176, output_vec_len ); + case 433: return makeRegisterExpression(amdgpu_gfx908::v177, output_vec_len ); + case 434: return makeRegisterExpression(amdgpu_gfx908::v178, output_vec_len ); + case 435: return makeRegisterExpression(amdgpu_gfx908::v179, output_vec_len ); + case 436: return makeRegisterExpression(amdgpu_gfx908::v180, output_vec_len ); + case 437: return makeRegisterExpression(amdgpu_gfx908::v181, output_vec_len ); + case 438: return makeRegisterExpression(amdgpu_gfx908::v182, output_vec_len ); + case 439: return makeRegisterExpression(amdgpu_gfx908::v183, output_vec_len ); + case 440: return makeRegisterExpression(amdgpu_gfx908::v184, output_vec_len ); + case 441: return makeRegisterExpression(amdgpu_gfx908::v185, output_vec_len ); + case 442: return makeRegisterExpression(amdgpu_gfx908::v186, output_vec_len ); + case 443: return makeRegisterExpression(amdgpu_gfx908::v187, output_vec_len ); + case 444: return makeRegisterExpression(amdgpu_gfx908::v188, output_vec_len ); + case 445: return makeRegisterExpression(amdgpu_gfx908::v189, output_vec_len ); + case 446: return makeRegisterExpression(amdgpu_gfx908::v190, output_vec_len ); + case 447: return makeRegisterExpression(amdgpu_gfx908::v191, output_vec_len ); + case 448: return makeRegisterExpression(amdgpu_gfx908::v192, output_vec_len ); + case 449: return makeRegisterExpression(amdgpu_gfx908::v193, output_vec_len ); + case 450: return makeRegisterExpression(amdgpu_gfx908::v194, output_vec_len ); + case 451: return makeRegisterExpression(amdgpu_gfx908::v195, output_vec_len ); + case 452: return makeRegisterExpression(amdgpu_gfx908::v196, output_vec_len ); + case 453: return makeRegisterExpression(amdgpu_gfx908::v197, output_vec_len ); + case 454: return makeRegisterExpression(amdgpu_gfx908::v198, output_vec_len ); + case 455: return makeRegisterExpression(amdgpu_gfx908::v199, output_vec_len ); + case 456: return makeRegisterExpression(amdgpu_gfx908::v200, output_vec_len ); + case 457: return makeRegisterExpression(amdgpu_gfx908::v201, output_vec_len ); + case 458: return makeRegisterExpression(amdgpu_gfx908::v202, output_vec_len ); + case 459: return makeRegisterExpression(amdgpu_gfx908::v203, output_vec_len ); + case 460: return makeRegisterExpression(amdgpu_gfx908::v204, output_vec_len ); + case 461: return makeRegisterExpression(amdgpu_gfx908::v205, output_vec_len ); + case 462: return makeRegisterExpression(amdgpu_gfx908::v206, output_vec_len ); + case 463: return makeRegisterExpression(amdgpu_gfx908::v207, output_vec_len ); + case 464: return makeRegisterExpression(amdgpu_gfx908::v208, output_vec_len ); + case 465: return makeRegisterExpression(amdgpu_gfx908::v209, output_vec_len ); + case 466: return makeRegisterExpression(amdgpu_gfx908::v210, output_vec_len ); + case 467: return makeRegisterExpression(amdgpu_gfx908::v211, output_vec_len ); + case 468: return makeRegisterExpression(amdgpu_gfx908::v212, output_vec_len ); + case 469: return makeRegisterExpression(amdgpu_gfx908::v213, output_vec_len ); + case 470: return makeRegisterExpression(amdgpu_gfx908::v214, output_vec_len ); + case 471: return makeRegisterExpression(amdgpu_gfx908::v215, output_vec_len ); + case 472: return makeRegisterExpression(amdgpu_gfx908::v216, output_vec_len ); + case 473: return makeRegisterExpression(amdgpu_gfx908::v217, output_vec_len ); + case 474: return makeRegisterExpression(amdgpu_gfx908::v218, output_vec_len ); + case 475: return makeRegisterExpression(amdgpu_gfx908::v219, output_vec_len ); + case 476: return makeRegisterExpression(amdgpu_gfx908::v220, output_vec_len ); + case 477: return makeRegisterExpression(amdgpu_gfx908::v221, output_vec_len ); + case 478: return makeRegisterExpression(amdgpu_gfx908::v222, output_vec_len ); + case 479: return makeRegisterExpression(amdgpu_gfx908::v223, output_vec_len ); + case 480: return makeRegisterExpression(amdgpu_gfx908::v224, output_vec_len ); + case 481: return makeRegisterExpression(amdgpu_gfx908::v225, output_vec_len ); + case 482: return makeRegisterExpression(amdgpu_gfx908::v226, output_vec_len ); + case 483: return makeRegisterExpression(amdgpu_gfx908::v227, output_vec_len ); + case 484: return makeRegisterExpression(amdgpu_gfx908::v228, output_vec_len ); + case 485: return makeRegisterExpression(amdgpu_gfx908::v229, output_vec_len ); + case 486: return makeRegisterExpression(amdgpu_gfx908::v230, output_vec_len ); + case 487: return makeRegisterExpression(amdgpu_gfx908::v231, output_vec_len ); + case 488: return makeRegisterExpression(amdgpu_gfx908::v232, output_vec_len ); + case 489: return makeRegisterExpression(amdgpu_gfx908::v233, output_vec_len ); + case 490: return makeRegisterExpression(amdgpu_gfx908::v234, output_vec_len ); + case 491: return makeRegisterExpression(amdgpu_gfx908::v235, output_vec_len ); + case 492: return makeRegisterExpression(amdgpu_gfx908::v236, output_vec_len ); + case 493: return makeRegisterExpression(amdgpu_gfx908::v237, output_vec_len ); + case 494: return makeRegisterExpression(amdgpu_gfx908::v238, output_vec_len ); + case 495: return makeRegisterExpression(amdgpu_gfx908::v239, output_vec_len ); + case 496: return makeRegisterExpression(amdgpu_gfx908::v240, output_vec_len ); + case 497: return makeRegisterExpression(amdgpu_gfx908::v241, output_vec_len ); + case 498: return makeRegisterExpression(amdgpu_gfx908::v242, output_vec_len ); + case 499: return makeRegisterExpression(amdgpu_gfx908::v243, output_vec_len ); + case 500: return makeRegisterExpression(amdgpu_gfx908::v244, output_vec_len ); + case 501: return makeRegisterExpression(amdgpu_gfx908::v245, output_vec_len ); + case 502: return makeRegisterExpression(amdgpu_gfx908::v246, output_vec_len ); + case 503: return makeRegisterExpression(amdgpu_gfx908::v247, output_vec_len ); + case 504: return makeRegisterExpression(amdgpu_gfx908::v248, output_vec_len ); + case 505: return makeRegisterExpression(amdgpu_gfx908::v249, output_vec_len ); + case 506: return makeRegisterExpression(amdgpu_gfx908::v250, output_vec_len ); + case 507: return makeRegisterExpression(amdgpu_gfx908::v251, output_vec_len ); + case 508: return makeRegisterExpression(amdgpu_gfx908::v252, output_vec_len ); + case 509: return makeRegisterExpression(amdgpu_gfx908::v253, output_vec_len ); + case 510: return makeRegisterExpression(amdgpu_gfx908::v254, output_vec_len ); + case 511: return makeRegisterExpression(amdgpu_gfx908::v255, output_vec_len ); + case 768: return makeRegisterExpression(amdgpu_gfx908::acc0, output_vec_len ); + case 769: return makeRegisterExpression(amdgpu_gfx908::acc1, output_vec_len ); + case 770: return makeRegisterExpression(amdgpu_gfx908::acc2, output_vec_len ); + case 771: return makeRegisterExpression(amdgpu_gfx908::acc3, output_vec_len ); + case 772: return makeRegisterExpression(amdgpu_gfx908::acc4, output_vec_len ); + case 773: return makeRegisterExpression(amdgpu_gfx908::acc5, output_vec_len ); + case 774: return makeRegisterExpression(amdgpu_gfx908::acc6, output_vec_len ); + case 775: return makeRegisterExpression(amdgpu_gfx908::acc7, output_vec_len ); + case 776: return makeRegisterExpression(amdgpu_gfx908::acc8, output_vec_len ); + case 777: return makeRegisterExpression(amdgpu_gfx908::acc9, output_vec_len ); + case 778: return makeRegisterExpression(amdgpu_gfx908::acc10, output_vec_len ); + case 779: return makeRegisterExpression(amdgpu_gfx908::acc11, output_vec_len ); + case 780: return makeRegisterExpression(amdgpu_gfx908::acc12, output_vec_len ); + case 781: return makeRegisterExpression(amdgpu_gfx908::acc13, output_vec_len ); + case 782: return makeRegisterExpression(amdgpu_gfx908::acc14, output_vec_len ); + case 783: return makeRegisterExpression(amdgpu_gfx908::acc15, output_vec_len ); + case 784: return makeRegisterExpression(amdgpu_gfx908::acc16, output_vec_len ); + case 785: return makeRegisterExpression(amdgpu_gfx908::acc17, output_vec_len ); + case 786: return makeRegisterExpression(amdgpu_gfx908::acc18, output_vec_len ); + case 787: return makeRegisterExpression(amdgpu_gfx908::acc19, output_vec_len ); + case 788: return makeRegisterExpression(amdgpu_gfx908::acc20, output_vec_len ); + case 789: return makeRegisterExpression(amdgpu_gfx908::acc21, output_vec_len ); + case 790: return makeRegisterExpression(amdgpu_gfx908::acc22, output_vec_len ); + case 791: return makeRegisterExpression(amdgpu_gfx908::acc23, output_vec_len ); + case 792: return makeRegisterExpression(amdgpu_gfx908::acc24, output_vec_len ); + case 793: return makeRegisterExpression(amdgpu_gfx908::acc25, output_vec_len ); + case 794: return makeRegisterExpression(amdgpu_gfx908::acc26, output_vec_len ); + case 795: return makeRegisterExpression(amdgpu_gfx908::acc27, output_vec_len ); + case 796: return makeRegisterExpression(amdgpu_gfx908::acc28, output_vec_len ); + case 797: return makeRegisterExpression(amdgpu_gfx908::acc29, output_vec_len ); + case 798: return makeRegisterExpression(amdgpu_gfx908::acc30, output_vec_len ); + case 799: return makeRegisterExpression(amdgpu_gfx908::acc31, output_vec_len ); + case 800: return makeRegisterExpression(amdgpu_gfx908::acc32, output_vec_len ); + case 801: return makeRegisterExpression(amdgpu_gfx908::acc33, output_vec_len ); + case 802: return makeRegisterExpression(amdgpu_gfx908::acc34, output_vec_len ); + case 803: return makeRegisterExpression(amdgpu_gfx908::acc35, output_vec_len ); + case 804: return makeRegisterExpression(amdgpu_gfx908::acc36, output_vec_len ); + case 805: return makeRegisterExpression(amdgpu_gfx908::acc37, output_vec_len ); + case 806: return makeRegisterExpression(amdgpu_gfx908::acc38, output_vec_len ); + case 807: return makeRegisterExpression(amdgpu_gfx908::acc39, output_vec_len ); + case 808: return makeRegisterExpression(amdgpu_gfx908::acc40, output_vec_len ); + case 809: return makeRegisterExpression(amdgpu_gfx908::acc41, output_vec_len ); + case 810: return makeRegisterExpression(amdgpu_gfx908::acc42, output_vec_len ); + case 811: return makeRegisterExpression(amdgpu_gfx908::acc43, output_vec_len ); + case 812: return makeRegisterExpression(amdgpu_gfx908::acc44, output_vec_len ); + case 813: return makeRegisterExpression(amdgpu_gfx908::acc45, output_vec_len ); + case 814: return makeRegisterExpression(amdgpu_gfx908::acc46, output_vec_len ); + case 815: return makeRegisterExpression(amdgpu_gfx908::acc47, output_vec_len ); + case 816: return makeRegisterExpression(amdgpu_gfx908::acc48, output_vec_len ); + case 817: return makeRegisterExpression(amdgpu_gfx908::acc49, output_vec_len ); + case 818: return makeRegisterExpression(amdgpu_gfx908::acc50, output_vec_len ); + case 819: return makeRegisterExpression(amdgpu_gfx908::acc51, output_vec_len ); + case 820: return makeRegisterExpression(amdgpu_gfx908::acc52, output_vec_len ); + case 821: return makeRegisterExpression(amdgpu_gfx908::acc53, output_vec_len ); + case 822: return makeRegisterExpression(amdgpu_gfx908::acc54, output_vec_len ); + case 823: return makeRegisterExpression(amdgpu_gfx908::acc55, output_vec_len ); + case 824: return makeRegisterExpression(amdgpu_gfx908::acc56, output_vec_len ); + case 825: return makeRegisterExpression(amdgpu_gfx908::acc57, output_vec_len ); + case 826: return makeRegisterExpression(amdgpu_gfx908::acc58, output_vec_len ); + case 827: return makeRegisterExpression(amdgpu_gfx908::acc59, output_vec_len ); + case 828: return makeRegisterExpression(amdgpu_gfx908::acc60, output_vec_len ); + case 829: return makeRegisterExpression(amdgpu_gfx908::acc61, output_vec_len ); + case 830: return makeRegisterExpression(amdgpu_gfx908::acc62, output_vec_len ); + case 831: return makeRegisterExpression(amdgpu_gfx908::acc63, output_vec_len ); + case 832: return makeRegisterExpression(amdgpu_gfx908::acc64, output_vec_len ); + case 833: return makeRegisterExpression(amdgpu_gfx908::acc65, output_vec_len ); + case 834: return makeRegisterExpression(amdgpu_gfx908::acc66, output_vec_len ); + case 835: return makeRegisterExpression(amdgpu_gfx908::acc67, output_vec_len ); + case 836: return makeRegisterExpression(amdgpu_gfx908::acc68, output_vec_len ); + case 837: return makeRegisterExpression(amdgpu_gfx908::acc69, output_vec_len ); + case 838: return makeRegisterExpression(amdgpu_gfx908::acc70, output_vec_len ); + case 839: return makeRegisterExpression(amdgpu_gfx908::acc71, output_vec_len ); + case 840: return makeRegisterExpression(amdgpu_gfx908::acc72, output_vec_len ); + case 841: return makeRegisterExpression(amdgpu_gfx908::acc73, output_vec_len ); + case 842: return makeRegisterExpression(amdgpu_gfx908::acc74, output_vec_len ); + case 843: return makeRegisterExpression(amdgpu_gfx908::acc75, output_vec_len ); + case 844: return makeRegisterExpression(amdgpu_gfx908::acc76, output_vec_len ); + case 845: return makeRegisterExpression(amdgpu_gfx908::acc77, output_vec_len ); + case 846: return makeRegisterExpression(amdgpu_gfx908::acc78, output_vec_len ); + case 847: return makeRegisterExpression(amdgpu_gfx908::acc79, output_vec_len ); + case 848: return makeRegisterExpression(amdgpu_gfx908::acc80, output_vec_len ); + case 849: return makeRegisterExpression(amdgpu_gfx908::acc81, output_vec_len ); + case 850: return makeRegisterExpression(amdgpu_gfx908::acc82, output_vec_len ); + case 851: return makeRegisterExpression(amdgpu_gfx908::acc83, output_vec_len ); + case 852: return makeRegisterExpression(amdgpu_gfx908::acc84, output_vec_len ); + case 853: return makeRegisterExpression(amdgpu_gfx908::acc85, output_vec_len ); + case 854: return makeRegisterExpression(amdgpu_gfx908::acc86, output_vec_len ); + case 855: return makeRegisterExpression(amdgpu_gfx908::acc87, output_vec_len ); + case 856: return makeRegisterExpression(amdgpu_gfx908::acc88, output_vec_len ); + case 857: return makeRegisterExpression(amdgpu_gfx908::acc89, output_vec_len ); + case 858: return makeRegisterExpression(amdgpu_gfx908::acc90, output_vec_len ); + case 859: return makeRegisterExpression(amdgpu_gfx908::acc91, output_vec_len ); + case 860: return makeRegisterExpression(amdgpu_gfx908::acc92, output_vec_len ); + case 861: return makeRegisterExpression(amdgpu_gfx908::acc93, output_vec_len ); + case 862: return makeRegisterExpression(amdgpu_gfx908::acc94, output_vec_len ); + case 863: return makeRegisterExpression(amdgpu_gfx908::acc95, output_vec_len ); + case 864: return makeRegisterExpression(amdgpu_gfx908::acc96, output_vec_len ); + case 865: return makeRegisterExpression(amdgpu_gfx908::acc97, output_vec_len ); + case 866: return makeRegisterExpression(amdgpu_gfx908::acc98, output_vec_len ); + case 867: return makeRegisterExpression(amdgpu_gfx908::acc99, output_vec_len ); + case 868: return makeRegisterExpression(amdgpu_gfx908::acc100, output_vec_len ); + case 869: return makeRegisterExpression(amdgpu_gfx908::acc101, output_vec_len ); + case 870: return makeRegisterExpression(amdgpu_gfx908::acc102, output_vec_len ); + case 871: return makeRegisterExpression(amdgpu_gfx908::acc103, output_vec_len ); + case 872: return makeRegisterExpression(amdgpu_gfx908::acc104, output_vec_len ); + case 873: return makeRegisterExpression(amdgpu_gfx908::acc105, output_vec_len ); + case 874: return makeRegisterExpression(amdgpu_gfx908::acc106, output_vec_len ); + case 875: return makeRegisterExpression(amdgpu_gfx908::acc107, output_vec_len ); + case 876: return makeRegisterExpression(amdgpu_gfx908::acc108, output_vec_len ); + case 877: return makeRegisterExpression(amdgpu_gfx908::acc109, output_vec_len ); + case 878: return makeRegisterExpression(amdgpu_gfx908::acc110, output_vec_len ); + case 879: return makeRegisterExpression(amdgpu_gfx908::acc111, output_vec_len ); + case 880: return makeRegisterExpression(amdgpu_gfx908::acc112, output_vec_len ); + case 881: return makeRegisterExpression(amdgpu_gfx908::acc113, output_vec_len ); + case 882: return makeRegisterExpression(amdgpu_gfx908::acc114, output_vec_len ); + case 883: return makeRegisterExpression(amdgpu_gfx908::acc115, output_vec_len ); + case 884: return makeRegisterExpression(amdgpu_gfx908::acc116, output_vec_len ); + case 885: return makeRegisterExpression(amdgpu_gfx908::acc117, output_vec_len ); + case 886: return makeRegisterExpression(amdgpu_gfx908::acc118, output_vec_len ); + case 887: return makeRegisterExpression(amdgpu_gfx908::acc119, output_vec_len ); + case 888: return makeRegisterExpression(amdgpu_gfx908::acc120, output_vec_len ); + case 889: return makeRegisterExpression(amdgpu_gfx908::acc121, output_vec_len ); + case 890: return makeRegisterExpression(amdgpu_gfx908::acc122, output_vec_len ); + case 891: return makeRegisterExpression(amdgpu_gfx908::acc123, output_vec_len ); + case 892: return makeRegisterExpression(amdgpu_gfx908::acc124, output_vec_len ); + case 893: return makeRegisterExpression(amdgpu_gfx908::acc125, output_vec_len ); + case 894: return makeRegisterExpression(amdgpu_gfx908::acc126, output_vec_len ); + case 895: return makeRegisterExpression(amdgpu_gfx908::acc127, output_vec_len ); + case 896: return makeRegisterExpression(amdgpu_gfx908::acc128, output_vec_len ); + case 897: return makeRegisterExpression(amdgpu_gfx908::acc129, output_vec_len ); + case 898: return makeRegisterExpression(amdgpu_gfx908::acc130, output_vec_len ); + case 899: return makeRegisterExpression(amdgpu_gfx908::acc131, output_vec_len ); + case 900: return makeRegisterExpression(amdgpu_gfx908::acc132, output_vec_len ); + case 901: return makeRegisterExpression(amdgpu_gfx908::acc133, output_vec_len ); + case 902: return makeRegisterExpression(amdgpu_gfx908::acc134, output_vec_len ); + case 903: return makeRegisterExpression(amdgpu_gfx908::acc135, output_vec_len ); + case 904: return makeRegisterExpression(amdgpu_gfx908::acc136, output_vec_len ); + case 905: return makeRegisterExpression(amdgpu_gfx908::acc137, output_vec_len ); + case 906: return makeRegisterExpression(amdgpu_gfx908::acc138, output_vec_len ); + case 907: return makeRegisterExpression(amdgpu_gfx908::acc139, output_vec_len ); + case 908: return makeRegisterExpression(amdgpu_gfx908::acc140, output_vec_len ); + case 909: return makeRegisterExpression(amdgpu_gfx908::acc141, output_vec_len ); + case 910: return makeRegisterExpression(amdgpu_gfx908::acc142, output_vec_len ); + case 911: return makeRegisterExpression(amdgpu_gfx908::acc143, output_vec_len ); + case 912: return makeRegisterExpression(amdgpu_gfx908::acc144, output_vec_len ); + case 913: return makeRegisterExpression(amdgpu_gfx908::acc145, output_vec_len ); + case 914: return makeRegisterExpression(amdgpu_gfx908::acc146, output_vec_len ); + case 915: return makeRegisterExpression(amdgpu_gfx908::acc147, output_vec_len ); + case 916: return makeRegisterExpression(amdgpu_gfx908::acc148, output_vec_len ); + case 917: return makeRegisterExpression(amdgpu_gfx908::acc149, output_vec_len ); + case 918: return makeRegisterExpression(amdgpu_gfx908::acc150, output_vec_len ); + case 919: return makeRegisterExpression(amdgpu_gfx908::acc151, output_vec_len ); + case 920: return makeRegisterExpression(amdgpu_gfx908::acc152, output_vec_len ); + case 921: return makeRegisterExpression(amdgpu_gfx908::acc153, output_vec_len ); + case 922: return makeRegisterExpression(amdgpu_gfx908::acc154, output_vec_len ); + case 923: return makeRegisterExpression(amdgpu_gfx908::acc155, output_vec_len ); + case 924: return makeRegisterExpression(amdgpu_gfx908::acc156, output_vec_len ); + case 925: return makeRegisterExpression(amdgpu_gfx908::acc157, output_vec_len ); + case 926: return makeRegisterExpression(amdgpu_gfx908::acc158, output_vec_len ); + case 927: return makeRegisterExpression(amdgpu_gfx908::acc159, output_vec_len ); + case 928: return makeRegisterExpression(amdgpu_gfx908::acc160, output_vec_len ); + case 929: return makeRegisterExpression(amdgpu_gfx908::acc161, output_vec_len ); + case 930: return makeRegisterExpression(amdgpu_gfx908::acc162, output_vec_len ); + case 931: return makeRegisterExpression(amdgpu_gfx908::acc163, output_vec_len ); + case 932: return makeRegisterExpression(amdgpu_gfx908::acc164, output_vec_len ); + case 933: return makeRegisterExpression(amdgpu_gfx908::acc165, output_vec_len ); + case 934: return makeRegisterExpression(amdgpu_gfx908::acc166, output_vec_len ); + case 935: return makeRegisterExpression(amdgpu_gfx908::acc167, output_vec_len ); + case 936: return makeRegisterExpression(amdgpu_gfx908::acc168, output_vec_len ); + case 937: return makeRegisterExpression(amdgpu_gfx908::acc169, output_vec_len ); + case 938: return makeRegisterExpression(amdgpu_gfx908::acc170, output_vec_len ); + case 939: return makeRegisterExpression(amdgpu_gfx908::acc171, output_vec_len ); + case 940: return makeRegisterExpression(amdgpu_gfx908::acc172, output_vec_len ); + case 941: return makeRegisterExpression(amdgpu_gfx908::acc173, output_vec_len ); + case 942: return makeRegisterExpression(amdgpu_gfx908::acc174, output_vec_len ); + case 943: return makeRegisterExpression(amdgpu_gfx908::acc175, output_vec_len ); + case 944: return makeRegisterExpression(amdgpu_gfx908::acc176, output_vec_len ); + case 945: return makeRegisterExpression(amdgpu_gfx908::acc177, output_vec_len ); + case 946: return makeRegisterExpression(amdgpu_gfx908::acc178, output_vec_len ); + case 947: return makeRegisterExpression(amdgpu_gfx908::acc179, output_vec_len ); + case 948: return makeRegisterExpression(amdgpu_gfx908::acc180, output_vec_len ); + case 949: return makeRegisterExpression(amdgpu_gfx908::acc181, output_vec_len ); + case 950: return makeRegisterExpression(amdgpu_gfx908::acc182, output_vec_len ); + case 951: return makeRegisterExpression(amdgpu_gfx908::acc183, output_vec_len ); + case 952: return makeRegisterExpression(amdgpu_gfx908::acc184, output_vec_len ); + case 953: return makeRegisterExpression(amdgpu_gfx908::acc185, output_vec_len ); + case 954: return makeRegisterExpression(amdgpu_gfx908::acc186, output_vec_len ); + case 955: return makeRegisterExpression(amdgpu_gfx908::acc187, output_vec_len ); + case 956: return makeRegisterExpression(amdgpu_gfx908::acc188, output_vec_len ); + case 957: return makeRegisterExpression(amdgpu_gfx908::acc189, output_vec_len ); + case 958: return makeRegisterExpression(amdgpu_gfx908::acc190, output_vec_len ); + case 959: return makeRegisterExpression(amdgpu_gfx908::acc191, output_vec_len ); + case 960: return makeRegisterExpression(amdgpu_gfx908::acc192, output_vec_len ); + case 961: return makeRegisterExpression(amdgpu_gfx908::acc193, output_vec_len ); + case 962: return makeRegisterExpression(amdgpu_gfx908::acc194, output_vec_len ); + case 963: return makeRegisterExpression(amdgpu_gfx908::acc195, output_vec_len ); + case 964: return makeRegisterExpression(amdgpu_gfx908::acc196, output_vec_len ); + case 965: return makeRegisterExpression(amdgpu_gfx908::acc197, output_vec_len ); + case 966: return makeRegisterExpression(amdgpu_gfx908::acc198, output_vec_len ); + case 967: return makeRegisterExpression(amdgpu_gfx908::acc199, output_vec_len ); + case 968: return makeRegisterExpression(amdgpu_gfx908::acc200, output_vec_len ); + case 969: return makeRegisterExpression(amdgpu_gfx908::acc201, output_vec_len ); + case 970: return makeRegisterExpression(amdgpu_gfx908::acc202, output_vec_len ); + case 971: return makeRegisterExpression(amdgpu_gfx908::acc203, output_vec_len ); + case 972: return makeRegisterExpression(amdgpu_gfx908::acc204, output_vec_len ); + case 973: return makeRegisterExpression(amdgpu_gfx908::acc205, output_vec_len ); + case 974: return makeRegisterExpression(amdgpu_gfx908::acc206, output_vec_len ); + case 975: return makeRegisterExpression(amdgpu_gfx908::acc207, output_vec_len ); + case 976: return makeRegisterExpression(amdgpu_gfx908::acc208, output_vec_len ); + case 977: return makeRegisterExpression(amdgpu_gfx908::acc209, output_vec_len ); + case 978: return makeRegisterExpression(amdgpu_gfx908::acc210, output_vec_len ); + case 979: return makeRegisterExpression(amdgpu_gfx908::acc211, output_vec_len ); + case 980: return makeRegisterExpression(amdgpu_gfx908::acc212, output_vec_len ); + case 981: return makeRegisterExpression(amdgpu_gfx908::acc213, output_vec_len ); + case 982: return makeRegisterExpression(amdgpu_gfx908::acc214, output_vec_len ); + case 983: return makeRegisterExpression(amdgpu_gfx908::acc215, output_vec_len ); + case 984: return makeRegisterExpression(amdgpu_gfx908::acc216, output_vec_len ); + case 985: return makeRegisterExpression(amdgpu_gfx908::acc217, output_vec_len ); + case 986: return makeRegisterExpression(amdgpu_gfx908::acc218, output_vec_len ); + case 987: return makeRegisterExpression(amdgpu_gfx908::acc219, output_vec_len ); + case 988: return makeRegisterExpression(amdgpu_gfx908::acc220, output_vec_len ); + case 989: return makeRegisterExpression(amdgpu_gfx908::acc221, output_vec_len ); + case 990: return makeRegisterExpression(amdgpu_gfx908::acc222, output_vec_len ); + case 991: return makeRegisterExpression(amdgpu_gfx908::acc223, output_vec_len ); + case 992: return makeRegisterExpression(amdgpu_gfx908::acc224, output_vec_len ); + case 993: return makeRegisterExpression(amdgpu_gfx908::acc225, output_vec_len ); + case 994: return makeRegisterExpression(amdgpu_gfx908::acc226, output_vec_len ); + case 995: return makeRegisterExpression(amdgpu_gfx908::acc227, output_vec_len ); + case 996: return makeRegisterExpression(amdgpu_gfx908::acc228, output_vec_len ); + case 997: return makeRegisterExpression(amdgpu_gfx908::acc229, output_vec_len ); + case 998: return makeRegisterExpression(amdgpu_gfx908::acc230, output_vec_len ); + case 999: return makeRegisterExpression(amdgpu_gfx908::acc231, output_vec_len ); + case 1000: return makeRegisterExpression(amdgpu_gfx908::acc232, output_vec_len ); + case 1001: return makeRegisterExpression(amdgpu_gfx908::acc233, output_vec_len ); + case 1002: return makeRegisterExpression(amdgpu_gfx908::acc234, output_vec_len ); + case 1003: return makeRegisterExpression(amdgpu_gfx908::acc235, output_vec_len ); + case 1004: return makeRegisterExpression(amdgpu_gfx908::acc236, output_vec_len ); + case 1005: return makeRegisterExpression(amdgpu_gfx908::acc237, output_vec_len ); + case 1006: return makeRegisterExpression(amdgpu_gfx908::acc238, output_vec_len ); + case 1007: return makeRegisterExpression(amdgpu_gfx908::acc239, output_vec_len ); + case 1008: return makeRegisterExpression(amdgpu_gfx908::acc240, output_vec_len ); + case 1009: return makeRegisterExpression(amdgpu_gfx908::acc241, output_vec_len ); + case 1010: return makeRegisterExpression(amdgpu_gfx908::acc242, output_vec_len ); + case 1011: return makeRegisterExpression(amdgpu_gfx908::acc243, output_vec_len ); + case 1012: return makeRegisterExpression(amdgpu_gfx908::acc244, output_vec_len ); + case 1013: return makeRegisterExpression(amdgpu_gfx908::acc245, output_vec_len ); + case 1014: return makeRegisterExpression(amdgpu_gfx908::acc246, output_vec_len ); + case 1015: return makeRegisterExpression(amdgpu_gfx908::acc247, output_vec_len ); + case 1016: return makeRegisterExpression(amdgpu_gfx908::acc248, output_vec_len ); + case 1017: return makeRegisterExpression(amdgpu_gfx908::acc249, output_vec_len ); + case 1018: return makeRegisterExpression(amdgpu_gfx908::acc250, output_vec_len ); + case 1019: return makeRegisterExpression(amdgpu_gfx908::acc251, output_vec_len ); + case 1020: return makeRegisterExpression(amdgpu_gfx908::acc252, output_vec_len ); + case 1021: return makeRegisterExpression(amdgpu_gfx908::acc253, output_vec_len ); + case 1022: return makeRegisterExpression(amdgpu_gfx908::acc254, output_vec_len ); + case 1023: return makeRegisterExpression(amdgpu_gfx908::acc255, output_vec_len ); + default: return makeRegisterExpression(amdgpu_gfx908::invalid); + } + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SREG(uint64_t input, uint32_t output_vec_len) + { + switch (input) { + case 0: return makeRegisterExpression(amdgpu_gfx908::s0, output_vec_len ); + case 1: return makeRegisterExpression(amdgpu_gfx908::s1, output_vec_len ); + case 2: return makeRegisterExpression(amdgpu_gfx908::s2, output_vec_len ); + case 3: return makeRegisterExpression(amdgpu_gfx908::s3, output_vec_len ); + case 4: return makeRegisterExpression(amdgpu_gfx908::s4, output_vec_len ); + case 5: return makeRegisterExpression(amdgpu_gfx908::s5, output_vec_len ); + case 6: return makeRegisterExpression(amdgpu_gfx908::s6, output_vec_len ); + case 7: return makeRegisterExpression(amdgpu_gfx908::s7, output_vec_len ); + case 8: return makeRegisterExpression(amdgpu_gfx908::s8, output_vec_len ); + case 9: return makeRegisterExpression(amdgpu_gfx908::s9, output_vec_len ); + case 10: return makeRegisterExpression(amdgpu_gfx908::s10, output_vec_len ); + case 11: return makeRegisterExpression(amdgpu_gfx908::s11, output_vec_len ); + case 12: return makeRegisterExpression(amdgpu_gfx908::s12, output_vec_len ); + case 13: return makeRegisterExpression(amdgpu_gfx908::s13, output_vec_len ); + case 14: return makeRegisterExpression(amdgpu_gfx908::s14, output_vec_len ); + case 15: return makeRegisterExpression(amdgpu_gfx908::s15, output_vec_len ); + case 16: return makeRegisterExpression(amdgpu_gfx908::s16, output_vec_len ); + case 17: return makeRegisterExpression(amdgpu_gfx908::s17, output_vec_len ); + case 18: return makeRegisterExpression(amdgpu_gfx908::s18, output_vec_len ); + case 19: return makeRegisterExpression(amdgpu_gfx908::s19, output_vec_len ); + case 20: return makeRegisterExpression(amdgpu_gfx908::s20, output_vec_len ); + case 21: return makeRegisterExpression(amdgpu_gfx908::s21, output_vec_len ); + case 22: return makeRegisterExpression(amdgpu_gfx908::s22, output_vec_len ); + case 23: return makeRegisterExpression(amdgpu_gfx908::s23, output_vec_len ); + case 24: return makeRegisterExpression(amdgpu_gfx908::s24, output_vec_len ); + case 25: return makeRegisterExpression(amdgpu_gfx908::s25, output_vec_len ); + case 26: return makeRegisterExpression(amdgpu_gfx908::s26, output_vec_len ); + case 27: return makeRegisterExpression(amdgpu_gfx908::s27, output_vec_len ); + case 28: return makeRegisterExpression(amdgpu_gfx908::s28, output_vec_len ); + case 29: return makeRegisterExpression(amdgpu_gfx908::s29, output_vec_len ); + case 30: return makeRegisterExpression(amdgpu_gfx908::s30, output_vec_len ); + case 31: return makeRegisterExpression(amdgpu_gfx908::s31, output_vec_len ); + case 32: return makeRegisterExpression(amdgpu_gfx908::s32, output_vec_len ); + case 33: return makeRegisterExpression(amdgpu_gfx908::s33, output_vec_len ); + case 34: return makeRegisterExpression(amdgpu_gfx908::s34, output_vec_len ); + case 35: return makeRegisterExpression(amdgpu_gfx908::s35, output_vec_len ); + case 36: return makeRegisterExpression(amdgpu_gfx908::s36, output_vec_len ); + case 37: return makeRegisterExpression(amdgpu_gfx908::s37, output_vec_len ); + case 38: return makeRegisterExpression(amdgpu_gfx908::s38, output_vec_len ); + case 39: return makeRegisterExpression(amdgpu_gfx908::s39, output_vec_len ); + case 40: return makeRegisterExpression(amdgpu_gfx908::s40, output_vec_len ); + case 41: return makeRegisterExpression(amdgpu_gfx908::s41, output_vec_len ); + case 42: return makeRegisterExpression(amdgpu_gfx908::s42, output_vec_len ); + case 43: return makeRegisterExpression(amdgpu_gfx908::s43, output_vec_len ); + case 44: return makeRegisterExpression(amdgpu_gfx908::s44, output_vec_len ); + case 45: return makeRegisterExpression(amdgpu_gfx908::s45, output_vec_len ); + case 46: return makeRegisterExpression(amdgpu_gfx908::s46, output_vec_len ); + case 47: return makeRegisterExpression(amdgpu_gfx908::s47, output_vec_len ); + case 48: return makeRegisterExpression(amdgpu_gfx908::s48, output_vec_len ); + case 49: return makeRegisterExpression(amdgpu_gfx908::s49, output_vec_len ); + case 50: return makeRegisterExpression(amdgpu_gfx908::s50, output_vec_len ); + case 51: return makeRegisterExpression(amdgpu_gfx908::s51, output_vec_len ); + case 52: return makeRegisterExpression(amdgpu_gfx908::s52, output_vec_len ); + case 53: return makeRegisterExpression(amdgpu_gfx908::s53, output_vec_len ); + case 54: return makeRegisterExpression(amdgpu_gfx908::s54, output_vec_len ); + case 55: return makeRegisterExpression(amdgpu_gfx908::s55, output_vec_len ); + case 56: return makeRegisterExpression(amdgpu_gfx908::s56, output_vec_len ); + case 57: return makeRegisterExpression(amdgpu_gfx908::s57, output_vec_len ); + case 58: return makeRegisterExpression(amdgpu_gfx908::s58, output_vec_len ); + case 59: return makeRegisterExpression(amdgpu_gfx908::s59, output_vec_len ); + case 60: return makeRegisterExpression(amdgpu_gfx908::s60, output_vec_len ); + case 61: return makeRegisterExpression(amdgpu_gfx908::s61, output_vec_len ); + case 62: return makeRegisterExpression(amdgpu_gfx908::s62, output_vec_len ); + case 63: return makeRegisterExpression(amdgpu_gfx908::s63, output_vec_len ); + case 64: return makeRegisterExpression(amdgpu_gfx908::s64, output_vec_len ); + case 65: return makeRegisterExpression(amdgpu_gfx908::s65, output_vec_len ); + case 66: return makeRegisterExpression(amdgpu_gfx908::s66, output_vec_len ); + case 67: return makeRegisterExpression(amdgpu_gfx908::s67, output_vec_len ); + case 68: return makeRegisterExpression(amdgpu_gfx908::s68, output_vec_len ); + case 69: return makeRegisterExpression(amdgpu_gfx908::s69, output_vec_len ); + case 70: return makeRegisterExpression(amdgpu_gfx908::s70, output_vec_len ); + case 71: return makeRegisterExpression(amdgpu_gfx908::s71, output_vec_len ); + case 72: return makeRegisterExpression(amdgpu_gfx908::s72, output_vec_len ); + case 73: return makeRegisterExpression(amdgpu_gfx908::s73, output_vec_len ); + case 74: return makeRegisterExpression(amdgpu_gfx908::s74, output_vec_len ); + case 75: return makeRegisterExpression(amdgpu_gfx908::s75, output_vec_len ); + case 76: return makeRegisterExpression(amdgpu_gfx908::s76, output_vec_len ); + case 77: return makeRegisterExpression(amdgpu_gfx908::s77, output_vec_len ); + case 78: return makeRegisterExpression(amdgpu_gfx908::s78, output_vec_len ); + case 79: return makeRegisterExpression(amdgpu_gfx908::s79, output_vec_len ); + case 80: return makeRegisterExpression(amdgpu_gfx908::s80, output_vec_len ); + case 81: return makeRegisterExpression(amdgpu_gfx908::s81, output_vec_len ); + case 82: return makeRegisterExpression(amdgpu_gfx908::s82, output_vec_len ); + case 83: return makeRegisterExpression(amdgpu_gfx908::s83, output_vec_len ); + case 84: return makeRegisterExpression(amdgpu_gfx908::s84, output_vec_len ); + case 85: return makeRegisterExpression(amdgpu_gfx908::s85, output_vec_len ); + case 86: return makeRegisterExpression(amdgpu_gfx908::s86, output_vec_len ); + case 87: return makeRegisterExpression(amdgpu_gfx908::s87, output_vec_len ); + case 88: return makeRegisterExpression(amdgpu_gfx908::s88, output_vec_len ); + case 89: return makeRegisterExpression(amdgpu_gfx908::s89, output_vec_len ); + case 90: return makeRegisterExpression(amdgpu_gfx908::s90, output_vec_len ); + case 91: return makeRegisterExpression(amdgpu_gfx908::s91, output_vec_len ); + case 92: return makeRegisterExpression(amdgpu_gfx908::s92, output_vec_len ); + case 93: return makeRegisterExpression(amdgpu_gfx908::s93, output_vec_len ); + case 94: return makeRegisterExpression(amdgpu_gfx908::s94, output_vec_len ); + case 95: return makeRegisterExpression(amdgpu_gfx908::s95, output_vec_len ); + case 96: return makeRegisterExpression(amdgpu_gfx908::s96, output_vec_len ); + case 97: return makeRegisterExpression(amdgpu_gfx908::s97, output_vec_len ); + case 98: return makeRegisterExpression(amdgpu_gfx908::s98, output_vec_len ); + case 99: return makeRegisterExpression(amdgpu_gfx908::s99, output_vec_len ); + case 100: return makeRegisterExpression(amdgpu_gfx908::s100, output_vec_len ); + case 101: return makeRegisterExpression(amdgpu_gfx908::s101, output_vec_len ); + case 104: return makeRegisterExpression(amdgpu_gfx908::xnack_mask_lo, output_vec_len ); + case 105: return makeRegisterExpression(amdgpu_gfx908::xnack_mask_hi, output_vec_len ); + case 102: return makeRegisterExpression(amdgpu_gfx908::flat_scratch_lo, output_vec_len ); + case 103: return makeRegisterExpression(amdgpu_gfx908::flat_scratch_hi, output_vec_len ); + case 108: return makeRegisterExpression(amdgpu_gfx908::ttmp0, output_vec_len ); + case 109: return makeRegisterExpression(amdgpu_gfx908::ttmp1, output_vec_len ); + case 110: return makeRegisterExpression(amdgpu_gfx908::ttmp2, output_vec_len ); + case 111: return makeRegisterExpression(amdgpu_gfx908::ttmp3, output_vec_len ); + case 112: return makeRegisterExpression(amdgpu_gfx908::ttmp4, output_vec_len ); + case 113: return makeRegisterExpression(amdgpu_gfx908::ttmp5, output_vec_len ); + case 114: return makeRegisterExpression(amdgpu_gfx908::ttmp6, output_vec_len ); + case 115: return makeRegisterExpression(amdgpu_gfx908::ttmp7, output_vec_len ); + case 116: return makeRegisterExpression(amdgpu_gfx908::ttmp8, output_vec_len ); + case 117: return makeRegisterExpression(amdgpu_gfx908::ttmp9, output_vec_len ); + case 118: return makeRegisterExpression(amdgpu_gfx908::ttmp10, output_vec_len ); + case 119: return makeRegisterExpression(amdgpu_gfx908::ttmp11, output_vec_len ); + case 120: return makeRegisterExpression(amdgpu_gfx908::ttmp12, output_vec_len ); + case 121: return makeRegisterExpression(amdgpu_gfx908::ttmp13, output_vec_len ); + case 122: return makeRegisterExpression(amdgpu_gfx908::ttmp14, output_vec_len ); + case 123: return makeRegisterExpression(amdgpu_gfx908::ttmp15, output_vec_len ); + case 106: return makeRegisterExpression(amdgpu_gfx908::vcc_lo, output_vec_len ); + case 107: return makeRegisterExpression(amdgpu_gfx908::vcc_hi, output_vec_len ); + default: return makeRegisterExpression(amdgpu_gfx908::invalid); + } + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SREG_NOVCC(uint64_t input, uint32_t output_vec_len) + { + switch (input) { + case 0: return makeRegisterExpression(amdgpu_gfx908::s0, output_vec_len ); + case 1: return makeRegisterExpression(amdgpu_gfx908::s1, output_vec_len ); + case 2: return makeRegisterExpression(amdgpu_gfx908::s2, output_vec_len ); + case 3: return makeRegisterExpression(amdgpu_gfx908::s3, output_vec_len ); + case 4: return makeRegisterExpression(amdgpu_gfx908::s4, output_vec_len ); + case 5: return makeRegisterExpression(amdgpu_gfx908::s5, output_vec_len ); + case 6: return makeRegisterExpression(amdgpu_gfx908::s6, output_vec_len ); + case 7: return makeRegisterExpression(amdgpu_gfx908::s7, output_vec_len ); + case 8: return makeRegisterExpression(amdgpu_gfx908::s8, output_vec_len ); + case 9: return makeRegisterExpression(amdgpu_gfx908::s9, output_vec_len ); + case 10: return makeRegisterExpression(amdgpu_gfx908::s10, output_vec_len ); + case 11: return makeRegisterExpression(amdgpu_gfx908::s11, output_vec_len ); + case 12: return makeRegisterExpression(amdgpu_gfx908::s12, output_vec_len ); + case 13: return makeRegisterExpression(amdgpu_gfx908::s13, output_vec_len ); + case 14: return makeRegisterExpression(amdgpu_gfx908::s14, output_vec_len ); + case 15: return makeRegisterExpression(amdgpu_gfx908::s15, output_vec_len ); + case 16: return makeRegisterExpression(amdgpu_gfx908::s16, output_vec_len ); + case 17: return makeRegisterExpression(amdgpu_gfx908::s17, output_vec_len ); + case 18: return makeRegisterExpression(amdgpu_gfx908::s18, output_vec_len ); + case 19: return makeRegisterExpression(amdgpu_gfx908::s19, output_vec_len ); + case 20: return makeRegisterExpression(amdgpu_gfx908::s20, output_vec_len ); + case 21: return makeRegisterExpression(amdgpu_gfx908::s21, output_vec_len ); + case 22: return makeRegisterExpression(amdgpu_gfx908::s22, output_vec_len ); + case 23: return makeRegisterExpression(amdgpu_gfx908::s23, output_vec_len ); + case 24: return makeRegisterExpression(amdgpu_gfx908::s24, output_vec_len ); + case 25: return makeRegisterExpression(amdgpu_gfx908::s25, output_vec_len ); + case 26: return makeRegisterExpression(amdgpu_gfx908::s26, output_vec_len ); + case 27: return makeRegisterExpression(amdgpu_gfx908::s27, output_vec_len ); + case 28: return makeRegisterExpression(amdgpu_gfx908::s28, output_vec_len ); + case 29: return makeRegisterExpression(amdgpu_gfx908::s29, output_vec_len ); + case 30: return makeRegisterExpression(amdgpu_gfx908::s30, output_vec_len ); + case 31: return makeRegisterExpression(amdgpu_gfx908::s31, output_vec_len ); + case 32: return makeRegisterExpression(amdgpu_gfx908::s32, output_vec_len ); + case 33: return makeRegisterExpression(amdgpu_gfx908::s33, output_vec_len ); + case 34: return makeRegisterExpression(amdgpu_gfx908::s34, output_vec_len ); + case 35: return makeRegisterExpression(amdgpu_gfx908::s35, output_vec_len ); + case 36: return makeRegisterExpression(amdgpu_gfx908::s36, output_vec_len ); + case 37: return makeRegisterExpression(amdgpu_gfx908::s37, output_vec_len ); + case 38: return makeRegisterExpression(amdgpu_gfx908::s38, output_vec_len ); + case 39: return makeRegisterExpression(amdgpu_gfx908::s39, output_vec_len ); + case 40: return makeRegisterExpression(amdgpu_gfx908::s40, output_vec_len ); + case 41: return makeRegisterExpression(amdgpu_gfx908::s41, output_vec_len ); + case 42: return makeRegisterExpression(amdgpu_gfx908::s42, output_vec_len ); + case 43: return makeRegisterExpression(amdgpu_gfx908::s43, output_vec_len ); + case 44: return makeRegisterExpression(amdgpu_gfx908::s44, output_vec_len ); + case 45: return makeRegisterExpression(amdgpu_gfx908::s45, output_vec_len ); + case 46: return makeRegisterExpression(amdgpu_gfx908::s46, output_vec_len ); + case 47: return makeRegisterExpression(amdgpu_gfx908::s47, output_vec_len ); + case 48: return makeRegisterExpression(amdgpu_gfx908::s48, output_vec_len ); + case 49: return makeRegisterExpression(amdgpu_gfx908::s49, output_vec_len ); + case 50: return makeRegisterExpression(amdgpu_gfx908::s50, output_vec_len ); + case 51: return makeRegisterExpression(amdgpu_gfx908::s51, output_vec_len ); + case 52: return makeRegisterExpression(amdgpu_gfx908::s52, output_vec_len ); + case 53: return makeRegisterExpression(amdgpu_gfx908::s53, output_vec_len ); + case 54: return makeRegisterExpression(amdgpu_gfx908::s54, output_vec_len ); + case 55: return makeRegisterExpression(amdgpu_gfx908::s55, output_vec_len ); + case 56: return makeRegisterExpression(amdgpu_gfx908::s56, output_vec_len ); + case 57: return makeRegisterExpression(amdgpu_gfx908::s57, output_vec_len ); + case 58: return makeRegisterExpression(amdgpu_gfx908::s58, output_vec_len ); + case 59: return makeRegisterExpression(amdgpu_gfx908::s59, output_vec_len ); + case 60: return makeRegisterExpression(amdgpu_gfx908::s60, output_vec_len ); + case 61: return makeRegisterExpression(amdgpu_gfx908::s61, output_vec_len ); + case 62: return makeRegisterExpression(amdgpu_gfx908::s62, output_vec_len ); + case 63: return makeRegisterExpression(amdgpu_gfx908::s63, output_vec_len ); + case 64: return makeRegisterExpression(amdgpu_gfx908::s64, output_vec_len ); + case 65: return makeRegisterExpression(amdgpu_gfx908::s65, output_vec_len ); + case 66: return makeRegisterExpression(amdgpu_gfx908::s66, output_vec_len ); + case 67: return makeRegisterExpression(amdgpu_gfx908::s67, output_vec_len ); + case 68: return makeRegisterExpression(amdgpu_gfx908::s68, output_vec_len ); + case 69: return makeRegisterExpression(amdgpu_gfx908::s69, output_vec_len ); + case 70: return makeRegisterExpression(amdgpu_gfx908::s70, output_vec_len ); + case 71: return makeRegisterExpression(amdgpu_gfx908::s71, output_vec_len ); + case 72: return makeRegisterExpression(amdgpu_gfx908::s72, output_vec_len ); + case 73: return makeRegisterExpression(amdgpu_gfx908::s73, output_vec_len ); + case 74: return makeRegisterExpression(amdgpu_gfx908::s74, output_vec_len ); + case 75: return makeRegisterExpression(amdgpu_gfx908::s75, output_vec_len ); + case 76: return makeRegisterExpression(amdgpu_gfx908::s76, output_vec_len ); + case 77: return makeRegisterExpression(amdgpu_gfx908::s77, output_vec_len ); + case 78: return makeRegisterExpression(amdgpu_gfx908::s78, output_vec_len ); + case 79: return makeRegisterExpression(amdgpu_gfx908::s79, output_vec_len ); + case 80: return makeRegisterExpression(amdgpu_gfx908::s80, output_vec_len ); + case 81: return makeRegisterExpression(amdgpu_gfx908::s81, output_vec_len ); + case 82: return makeRegisterExpression(amdgpu_gfx908::s82, output_vec_len ); + case 83: return makeRegisterExpression(amdgpu_gfx908::s83, output_vec_len ); + case 84: return makeRegisterExpression(amdgpu_gfx908::s84, output_vec_len ); + case 85: return makeRegisterExpression(amdgpu_gfx908::s85, output_vec_len ); + case 86: return makeRegisterExpression(amdgpu_gfx908::s86, output_vec_len ); + case 87: return makeRegisterExpression(amdgpu_gfx908::s87, output_vec_len ); + case 88: return makeRegisterExpression(amdgpu_gfx908::s88, output_vec_len ); + case 89: return makeRegisterExpression(amdgpu_gfx908::s89, output_vec_len ); + case 90: return makeRegisterExpression(amdgpu_gfx908::s90, output_vec_len ); + case 91: return makeRegisterExpression(amdgpu_gfx908::s91, output_vec_len ); + case 92: return makeRegisterExpression(amdgpu_gfx908::s92, output_vec_len ); + case 93: return makeRegisterExpression(amdgpu_gfx908::s93, output_vec_len ); + case 94: return makeRegisterExpression(amdgpu_gfx908::s94, output_vec_len ); + case 95: return makeRegisterExpression(amdgpu_gfx908::s95, output_vec_len ); + case 96: return makeRegisterExpression(amdgpu_gfx908::s96, output_vec_len ); + case 97: return makeRegisterExpression(amdgpu_gfx908::s97, output_vec_len ); + case 98: return makeRegisterExpression(amdgpu_gfx908::s98, output_vec_len ); + case 99: return makeRegisterExpression(amdgpu_gfx908::s99, output_vec_len ); + case 100: return makeRegisterExpression(amdgpu_gfx908::s100, output_vec_len ); + case 101: return makeRegisterExpression(amdgpu_gfx908::s101, output_vec_len ); + case 104: return makeRegisterExpression(amdgpu_gfx908::xnack_mask_lo, output_vec_len ); + case 105: return makeRegisterExpression(amdgpu_gfx908::xnack_mask_hi, output_vec_len ); + case 102: return makeRegisterExpression(amdgpu_gfx908::flat_scratch_lo, output_vec_len ); + case 103: return makeRegisterExpression(amdgpu_gfx908::flat_scratch_hi, output_vec_len ); + case 108: return makeRegisterExpression(amdgpu_gfx908::ttmp0, output_vec_len ); + case 109: return makeRegisterExpression(amdgpu_gfx908::ttmp1, output_vec_len ); + case 110: return makeRegisterExpression(amdgpu_gfx908::ttmp2, output_vec_len ); + case 111: return makeRegisterExpression(amdgpu_gfx908::ttmp3, output_vec_len ); + case 112: return makeRegisterExpression(amdgpu_gfx908::ttmp4, output_vec_len ); + case 113: return makeRegisterExpression(amdgpu_gfx908::ttmp5, output_vec_len ); + case 114: return makeRegisterExpression(amdgpu_gfx908::ttmp6, output_vec_len ); + case 115: return makeRegisterExpression(amdgpu_gfx908::ttmp7, output_vec_len ); + case 116: return makeRegisterExpression(amdgpu_gfx908::ttmp8, output_vec_len ); + case 117: return makeRegisterExpression(amdgpu_gfx908::ttmp9, output_vec_len ); + case 118: return makeRegisterExpression(amdgpu_gfx908::ttmp10, output_vec_len ); + case 119: return makeRegisterExpression(amdgpu_gfx908::ttmp11, output_vec_len ); + case 120: return makeRegisterExpression(amdgpu_gfx908::ttmp12, output_vec_len ); + case 121: return makeRegisterExpression(amdgpu_gfx908::ttmp13, output_vec_len ); + case 122: return makeRegisterExpression(amdgpu_gfx908::ttmp14, output_vec_len ); + case 123: return makeRegisterExpression(amdgpu_gfx908::ttmp15, output_vec_len ); + default: return makeRegisterExpression(amdgpu_gfx908::invalid); + } + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SSRC(uint64_t input, uint32_t output_vec_len) + { + switch (input) { + case 0: return makeRegisterExpression(amdgpu_gfx908::s0, output_vec_len ); + case 1: return makeRegisterExpression(amdgpu_gfx908::s1, output_vec_len ); + case 2: return makeRegisterExpression(amdgpu_gfx908::s2, output_vec_len ); + case 3: return makeRegisterExpression(amdgpu_gfx908::s3, output_vec_len ); + case 4: return makeRegisterExpression(amdgpu_gfx908::s4, output_vec_len ); + case 5: return makeRegisterExpression(amdgpu_gfx908::s5, output_vec_len ); + case 6: return makeRegisterExpression(amdgpu_gfx908::s6, output_vec_len ); + case 7: return makeRegisterExpression(amdgpu_gfx908::s7, output_vec_len ); + case 8: return makeRegisterExpression(amdgpu_gfx908::s8, output_vec_len ); + case 9: return makeRegisterExpression(amdgpu_gfx908::s9, output_vec_len ); + case 10: return makeRegisterExpression(amdgpu_gfx908::s10, output_vec_len ); + case 11: return makeRegisterExpression(amdgpu_gfx908::s11, output_vec_len ); + case 12: return makeRegisterExpression(amdgpu_gfx908::s12, output_vec_len ); + case 13: return makeRegisterExpression(amdgpu_gfx908::s13, output_vec_len ); + case 14: return makeRegisterExpression(amdgpu_gfx908::s14, output_vec_len ); + case 15: return makeRegisterExpression(amdgpu_gfx908::s15, output_vec_len ); + case 16: return makeRegisterExpression(amdgpu_gfx908::s16, output_vec_len ); + case 17: return makeRegisterExpression(amdgpu_gfx908::s17, output_vec_len ); + case 18: return makeRegisterExpression(amdgpu_gfx908::s18, output_vec_len ); + case 19: return makeRegisterExpression(amdgpu_gfx908::s19, output_vec_len ); + case 20: return makeRegisterExpression(amdgpu_gfx908::s20, output_vec_len ); + case 21: return makeRegisterExpression(amdgpu_gfx908::s21, output_vec_len ); + case 22: return makeRegisterExpression(amdgpu_gfx908::s22, output_vec_len ); + case 23: return makeRegisterExpression(amdgpu_gfx908::s23, output_vec_len ); + case 24: return makeRegisterExpression(amdgpu_gfx908::s24, output_vec_len ); + case 25: return makeRegisterExpression(amdgpu_gfx908::s25, output_vec_len ); + case 26: return makeRegisterExpression(amdgpu_gfx908::s26, output_vec_len ); + case 27: return makeRegisterExpression(amdgpu_gfx908::s27, output_vec_len ); + case 28: return makeRegisterExpression(amdgpu_gfx908::s28, output_vec_len ); + case 29: return makeRegisterExpression(amdgpu_gfx908::s29, output_vec_len ); + case 30: return makeRegisterExpression(amdgpu_gfx908::s30, output_vec_len ); + case 31: return makeRegisterExpression(amdgpu_gfx908::s31, output_vec_len ); + case 32: return makeRegisterExpression(amdgpu_gfx908::s32, output_vec_len ); + case 33: return makeRegisterExpression(amdgpu_gfx908::s33, output_vec_len ); + case 34: return makeRegisterExpression(amdgpu_gfx908::s34, output_vec_len ); + case 35: return makeRegisterExpression(amdgpu_gfx908::s35, output_vec_len ); + case 36: return makeRegisterExpression(amdgpu_gfx908::s36, output_vec_len ); + case 37: return makeRegisterExpression(amdgpu_gfx908::s37, output_vec_len ); + case 38: return makeRegisterExpression(amdgpu_gfx908::s38, output_vec_len ); + case 39: return makeRegisterExpression(amdgpu_gfx908::s39, output_vec_len ); + case 40: return makeRegisterExpression(amdgpu_gfx908::s40, output_vec_len ); + case 41: return makeRegisterExpression(amdgpu_gfx908::s41, output_vec_len ); + case 42: return makeRegisterExpression(amdgpu_gfx908::s42, output_vec_len ); + case 43: return makeRegisterExpression(amdgpu_gfx908::s43, output_vec_len ); + case 44: return makeRegisterExpression(amdgpu_gfx908::s44, output_vec_len ); + case 45: return makeRegisterExpression(amdgpu_gfx908::s45, output_vec_len ); + case 46: return makeRegisterExpression(amdgpu_gfx908::s46, output_vec_len ); + case 47: return makeRegisterExpression(amdgpu_gfx908::s47, output_vec_len ); + case 48: return makeRegisterExpression(amdgpu_gfx908::s48, output_vec_len ); + case 49: return makeRegisterExpression(amdgpu_gfx908::s49, output_vec_len ); + case 50: return makeRegisterExpression(amdgpu_gfx908::s50, output_vec_len ); + case 51: return makeRegisterExpression(amdgpu_gfx908::s51, output_vec_len ); + case 52: return makeRegisterExpression(amdgpu_gfx908::s52, output_vec_len ); + case 53: return makeRegisterExpression(amdgpu_gfx908::s53, output_vec_len ); + case 54: return makeRegisterExpression(amdgpu_gfx908::s54, output_vec_len ); + case 55: return makeRegisterExpression(amdgpu_gfx908::s55, output_vec_len ); + case 56: return makeRegisterExpression(amdgpu_gfx908::s56, output_vec_len ); + case 57: return makeRegisterExpression(amdgpu_gfx908::s57, output_vec_len ); + case 58: return makeRegisterExpression(amdgpu_gfx908::s58, output_vec_len ); + case 59: return makeRegisterExpression(amdgpu_gfx908::s59, output_vec_len ); + case 60: return makeRegisterExpression(amdgpu_gfx908::s60, output_vec_len ); + case 61: return makeRegisterExpression(amdgpu_gfx908::s61, output_vec_len ); + case 62: return makeRegisterExpression(amdgpu_gfx908::s62, output_vec_len ); + case 63: return makeRegisterExpression(amdgpu_gfx908::s63, output_vec_len ); + case 64: return makeRegisterExpression(amdgpu_gfx908::s64, output_vec_len ); + case 65: return makeRegisterExpression(amdgpu_gfx908::s65, output_vec_len ); + case 66: return makeRegisterExpression(amdgpu_gfx908::s66, output_vec_len ); + case 67: return makeRegisterExpression(amdgpu_gfx908::s67, output_vec_len ); + case 68: return makeRegisterExpression(amdgpu_gfx908::s68, output_vec_len ); + case 69: return makeRegisterExpression(amdgpu_gfx908::s69, output_vec_len ); + case 70: return makeRegisterExpression(amdgpu_gfx908::s70, output_vec_len ); + case 71: return makeRegisterExpression(amdgpu_gfx908::s71, output_vec_len ); + case 72: return makeRegisterExpression(amdgpu_gfx908::s72, output_vec_len ); + case 73: return makeRegisterExpression(amdgpu_gfx908::s73, output_vec_len ); + case 74: return makeRegisterExpression(amdgpu_gfx908::s74, output_vec_len ); + case 75: return makeRegisterExpression(amdgpu_gfx908::s75, output_vec_len ); + case 76: return makeRegisterExpression(amdgpu_gfx908::s76, output_vec_len ); + case 77: return makeRegisterExpression(amdgpu_gfx908::s77, output_vec_len ); + case 78: return makeRegisterExpression(amdgpu_gfx908::s78, output_vec_len ); + case 79: return makeRegisterExpression(amdgpu_gfx908::s79, output_vec_len ); + case 80: return makeRegisterExpression(amdgpu_gfx908::s80, output_vec_len ); + case 81: return makeRegisterExpression(amdgpu_gfx908::s81, output_vec_len ); + case 82: return makeRegisterExpression(amdgpu_gfx908::s82, output_vec_len ); + case 83: return makeRegisterExpression(amdgpu_gfx908::s83, output_vec_len ); + case 84: return makeRegisterExpression(amdgpu_gfx908::s84, output_vec_len ); + case 85: return makeRegisterExpression(amdgpu_gfx908::s85, output_vec_len ); + case 86: return makeRegisterExpression(amdgpu_gfx908::s86, output_vec_len ); + case 87: return makeRegisterExpression(amdgpu_gfx908::s87, output_vec_len ); + case 88: return makeRegisterExpression(amdgpu_gfx908::s88, output_vec_len ); + case 89: return makeRegisterExpression(amdgpu_gfx908::s89, output_vec_len ); + case 90: return makeRegisterExpression(amdgpu_gfx908::s90, output_vec_len ); + case 91: return makeRegisterExpression(amdgpu_gfx908::s91, output_vec_len ); + case 92: return makeRegisterExpression(amdgpu_gfx908::s92, output_vec_len ); + case 93: return makeRegisterExpression(amdgpu_gfx908::s93, output_vec_len ); + case 94: return makeRegisterExpression(amdgpu_gfx908::s94, output_vec_len ); + case 95: return makeRegisterExpression(amdgpu_gfx908::s95, output_vec_len ); + case 96: return makeRegisterExpression(amdgpu_gfx908::s96, output_vec_len ); + case 97: return makeRegisterExpression(amdgpu_gfx908::s97, output_vec_len ); + case 98: return makeRegisterExpression(amdgpu_gfx908::s98, output_vec_len ); + case 99: return makeRegisterExpression(amdgpu_gfx908::s99, output_vec_len ); + case 100: return makeRegisterExpression(amdgpu_gfx908::s100, output_vec_len ); + case 101: return makeRegisterExpression(amdgpu_gfx908::s101, output_vec_len ); + case 104: return makeRegisterExpression(amdgpu_gfx908::xnack_mask_lo, output_vec_len ); + case 105: return makeRegisterExpression(amdgpu_gfx908::xnack_mask_hi, output_vec_len ); + case 102: return makeRegisterExpression(amdgpu_gfx908::flat_scratch_lo, output_vec_len ); + case 103: return makeRegisterExpression(amdgpu_gfx908::flat_scratch_hi, output_vec_len ); + case 108: return makeRegisterExpression(amdgpu_gfx908::ttmp0, output_vec_len ); + case 109: return makeRegisterExpression(amdgpu_gfx908::ttmp1, output_vec_len ); + case 110: return makeRegisterExpression(amdgpu_gfx908::ttmp2, output_vec_len ); + case 111: return makeRegisterExpression(amdgpu_gfx908::ttmp3, output_vec_len ); + case 112: return makeRegisterExpression(amdgpu_gfx908::ttmp4, output_vec_len ); + case 113: return makeRegisterExpression(amdgpu_gfx908::ttmp5, output_vec_len ); + case 114: return makeRegisterExpression(amdgpu_gfx908::ttmp6, output_vec_len ); + case 115: return makeRegisterExpression(amdgpu_gfx908::ttmp7, output_vec_len ); + case 116: return makeRegisterExpression(amdgpu_gfx908::ttmp8, output_vec_len ); + case 117: return makeRegisterExpression(amdgpu_gfx908::ttmp9, output_vec_len ); + case 118: return makeRegisterExpression(amdgpu_gfx908::ttmp10, output_vec_len ); + case 119: return makeRegisterExpression(amdgpu_gfx908::ttmp11, output_vec_len ); + case 120: return makeRegisterExpression(amdgpu_gfx908::ttmp12, output_vec_len ); + case 121: return makeRegisterExpression(amdgpu_gfx908::ttmp13, output_vec_len ); + case 122: return makeRegisterExpression(amdgpu_gfx908::ttmp14, output_vec_len ); + case 123: return makeRegisterExpression(amdgpu_gfx908::ttmp15, output_vec_len ); + case 106: return makeRegisterExpression(amdgpu_gfx908::vcc_lo, output_vec_len ); + case 107: return makeRegisterExpression(amdgpu_gfx908::vcc_hi, output_vec_len ); + case 124: return makeRegisterExpression(amdgpu_gfx908::m0, output_vec_len ); + case 126: return makeRegisterExpression(amdgpu_gfx908::exec_lo, output_vec_len ); + case 127: return makeRegisterExpression(amdgpu_gfx908::exec_hi, output_vec_len ); + case 128: return Immediate::makeImmediate(Result(u32, 0)); + case 129: return Immediate::makeImmediate(Result(u32, 1)); + case 130: return Immediate::makeImmediate(Result(u32, 2)); + case 131: return Immediate::makeImmediate(Result(u32, 3)); + case 132: return Immediate::makeImmediate(Result(u32, 4)); + case 133: return Immediate::makeImmediate(Result(u32, 5)); + case 134: return Immediate::makeImmediate(Result(u32, 6)); + case 135: return Immediate::makeImmediate(Result(u32, 7)); + case 136: return Immediate::makeImmediate(Result(u32, 8)); + case 137: return Immediate::makeImmediate(Result(u32, 9)); + case 138: return Immediate::makeImmediate(Result(u32, 10)); + case 139: return Immediate::makeImmediate(Result(u32, 11)); + case 140: return Immediate::makeImmediate(Result(u32, 12)); + case 141: return Immediate::makeImmediate(Result(u32, 13)); + case 142: return Immediate::makeImmediate(Result(u32, 14)); + case 143: return Immediate::makeImmediate(Result(u32, 15)); + case 144: return Immediate::makeImmediate(Result(u32, 16)); + case 145: return Immediate::makeImmediate(Result(u32, 17)); + case 146: return Immediate::makeImmediate(Result(u32, 18)); + case 147: return Immediate::makeImmediate(Result(u32, 19)); + case 148: return Immediate::makeImmediate(Result(u32, 20)); + case 149: return Immediate::makeImmediate(Result(u32, 21)); + case 150: return Immediate::makeImmediate(Result(u32, 22)); + case 151: return Immediate::makeImmediate(Result(u32, 23)); + case 152: return Immediate::makeImmediate(Result(u32, 24)); + case 153: return Immediate::makeImmediate(Result(u32, 25)); + case 154: return Immediate::makeImmediate(Result(u32, 26)); + case 155: return Immediate::makeImmediate(Result(u32, 27)); + case 156: return Immediate::makeImmediate(Result(u32, 28)); + case 157: return Immediate::makeImmediate(Result(u32, 29)); + case 158: return Immediate::makeImmediate(Result(u32, 30)); + case 159: return Immediate::makeImmediate(Result(u32, 31)); + case 160: return Immediate::makeImmediate(Result(u32, 32)); + case 161: return Immediate::makeImmediate(Result(u32, 33)); + case 162: return Immediate::makeImmediate(Result(u32, 34)); + case 163: return Immediate::makeImmediate(Result(u32, 35)); + case 164: return Immediate::makeImmediate(Result(u32, 36)); + case 165: return Immediate::makeImmediate(Result(u32, 37)); + case 166: return Immediate::makeImmediate(Result(u32, 38)); + case 167: return Immediate::makeImmediate(Result(u32, 39)); + case 168: return Immediate::makeImmediate(Result(u32, 40)); + case 169: return Immediate::makeImmediate(Result(u32, 41)); + case 170: return Immediate::makeImmediate(Result(u32, 42)); + case 171: return Immediate::makeImmediate(Result(u32, 43)); + case 172: return Immediate::makeImmediate(Result(u32, 44)); + case 173: return Immediate::makeImmediate(Result(u32, 45)); + case 174: return Immediate::makeImmediate(Result(u32, 46)); + case 175: return Immediate::makeImmediate(Result(u32, 47)); + case 176: return Immediate::makeImmediate(Result(u32, 48)); + case 177: return Immediate::makeImmediate(Result(u32, 49)); + case 178: return Immediate::makeImmediate(Result(u32, 50)); + case 179: return Immediate::makeImmediate(Result(u32, 51)); + case 180: return Immediate::makeImmediate(Result(u32, 52)); + case 181: return Immediate::makeImmediate(Result(u32, 53)); + case 182: return Immediate::makeImmediate(Result(u32, 54)); + case 183: return Immediate::makeImmediate(Result(u32, 55)); + case 184: return Immediate::makeImmediate(Result(u32, 56)); + case 185: return Immediate::makeImmediate(Result(u32, 57)); + case 186: return Immediate::makeImmediate(Result(u32, 58)); + case 187: return Immediate::makeImmediate(Result(u32, 59)); + case 188: return Immediate::makeImmediate(Result(u32, 60)); + case 189: return Immediate::makeImmediate(Result(u32, 61)); + case 190: return Immediate::makeImmediate(Result(u32, 62)); + case 191: return Immediate::makeImmediate(Result(u32, 63)); + case 192: return Immediate::makeImmediate(Result(u32, 64)); + case 193: return Immediate::makeImmediate(Result(u32, -1)); + case 194: return Immediate::makeImmediate(Result(u32, -2)); + case 195: return Immediate::makeImmediate(Result(u32, -3)); + case 196: return Immediate::makeImmediate(Result(u32, -4)); + case 197: return Immediate::makeImmediate(Result(u32, -5)); + case 198: return Immediate::makeImmediate(Result(u32, -6)); + case 199: return Immediate::makeImmediate(Result(u32, -7)); + case 200: return Immediate::makeImmediate(Result(u32, -8)); + case 201: return Immediate::makeImmediate(Result(u32, -9)); + case 202: return Immediate::makeImmediate(Result(u32, -10)); + case 203: return Immediate::makeImmediate(Result(u32, -11)); + case 204: return Immediate::makeImmediate(Result(u32, -12)); + case 205: return Immediate::makeImmediate(Result(u32, -13)); + case 206: return Immediate::makeImmediate(Result(u32, -14)); + case 207: return Immediate::makeImmediate(Result(u32, -15)); + case 208: return Immediate::makeImmediate(Result(u32, -16)); + case 240: return Immediate::makeImmediate(Result(sp_float, 0.5)); + case 241: return Immediate::makeImmediate(Result(sp_float, -0.5)); + case 242: return Immediate::makeImmediate(Result(sp_float, 1.0)); + case 243: return Immediate::makeImmediate(Result(sp_float, -1.0)); + case 244: return Immediate::makeImmediate(Result(sp_float, 2.0)); + case 245: return Immediate::makeImmediate(Result(sp_float, -2.0)); + case 246: return Immediate::makeImmediate(Result(sp_float, 4.0)); + case 247: return Immediate::makeImmediate(Result(sp_float, -4.0)); + case 248: return Immediate::makeImmediate(Result(sp_float, 0.15915494)); + case 251: return makeRegisterExpression(amdgpu_gfx908::src_vccz, output_vec_len ); + case 252: return makeRegisterExpression(amdgpu_gfx908::src_execz, output_vec_len ); + case 253: return makeRegisterExpression(amdgpu_gfx908::src_scc, output_vec_len ); + case 235: return makeRegisterExpression(amdgpu_gfx908::src_shared_base, output_vec_len ); + case 236: return makeRegisterExpression(amdgpu_gfx908::src_shared_limit, output_vec_len ); + case 237: return makeRegisterExpression(amdgpu_gfx908::src_private_base, output_vec_len ); + case 238: return makeRegisterExpression(amdgpu_gfx908::src_private_limit, output_vec_len ); + case 239: return makeRegisterExpression(amdgpu_gfx908::src_pops_exiting_wave_id, output_vec_len ); + case 255: return Immediate::makeImmediate(Result(u32,decodeOPR_LITERAL())); + case 249 : return decodeOPR_SDWA(); + default: return makeRegisterExpression(amdgpu_gfx908::invalid); + } + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SSRC_LANESEL(uint64_t input, uint32_t output_vec_len) + { + switch (input) { + case 0: return makeRegisterExpression(amdgpu_gfx908::s0, output_vec_len ); + case 1: return makeRegisterExpression(amdgpu_gfx908::s1, output_vec_len ); + case 2: return makeRegisterExpression(amdgpu_gfx908::s2, output_vec_len ); + case 3: return makeRegisterExpression(amdgpu_gfx908::s3, output_vec_len ); + case 4: return makeRegisterExpression(amdgpu_gfx908::s4, output_vec_len ); + case 5: return makeRegisterExpression(amdgpu_gfx908::s5, output_vec_len ); + case 6: return makeRegisterExpression(amdgpu_gfx908::s6, output_vec_len ); + case 7: return makeRegisterExpression(amdgpu_gfx908::s7, output_vec_len ); + case 8: return makeRegisterExpression(amdgpu_gfx908::s8, output_vec_len ); + case 9: return makeRegisterExpression(amdgpu_gfx908::s9, output_vec_len ); + case 10: return makeRegisterExpression(amdgpu_gfx908::s10, output_vec_len ); + case 11: return makeRegisterExpression(amdgpu_gfx908::s11, output_vec_len ); + case 12: return makeRegisterExpression(amdgpu_gfx908::s12, output_vec_len ); + case 13: return makeRegisterExpression(amdgpu_gfx908::s13, output_vec_len ); + case 14: return makeRegisterExpression(amdgpu_gfx908::s14, output_vec_len ); + case 15: return makeRegisterExpression(amdgpu_gfx908::s15, output_vec_len ); + case 16: return makeRegisterExpression(amdgpu_gfx908::s16, output_vec_len ); + case 17: return makeRegisterExpression(amdgpu_gfx908::s17, output_vec_len ); + case 18: return makeRegisterExpression(amdgpu_gfx908::s18, output_vec_len ); + case 19: return makeRegisterExpression(amdgpu_gfx908::s19, output_vec_len ); + case 20: return makeRegisterExpression(amdgpu_gfx908::s20, output_vec_len ); + case 21: return makeRegisterExpression(amdgpu_gfx908::s21, output_vec_len ); + case 22: return makeRegisterExpression(amdgpu_gfx908::s22, output_vec_len ); + case 23: return makeRegisterExpression(amdgpu_gfx908::s23, output_vec_len ); + case 24: return makeRegisterExpression(amdgpu_gfx908::s24, output_vec_len ); + case 25: return makeRegisterExpression(amdgpu_gfx908::s25, output_vec_len ); + case 26: return makeRegisterExpression(amdgpu_gfx908::s26, output_vec_len ); + case 27: return makeRegisterExpression(amdgpu_gfx908::s27, output_vec_len ); + case 28: return makeRegisterExpression(amdgpu_gfx908::s28, output_vec_len ); + case 29: return makeRegisterExpression(amdgpu_gfx908::s29, output_vec_len ); + case 30: return makeRegisterExpression(amdgpu_gfx908::s30, output_vec_len ); + case 31: return makeRegisterExpression(amdgpu_gfx908::s31, output_vec_len ); + case 32: return makeRegisterExpression(amdgpu_gfx908::s32, output_vec_len ); + case 33: return makeRegisterExpression(amdgpu_gfx908::s33, output_vec_len ); + case 34: return makeRegisterExpression(amdgpu_gfx908::s34, output_vec_len ); + case 35: return makeRegisterExpression(amdgpu_gfx908::s35, output_vec_len ); + case 36: return makeRegisterExpression(amdgpu_gfx908::s36, output_vec_len ); + case 37: return makeRegisterExpression(amdgpu_gfx908::s37, output_vec_len ); + case 38: return makeRegisterExpression(amdgpu_gfx908::s38, output_vec_len ); + case 39: return makeRegisterExpression(amdgpu_gfx908::s39, output_vec_len ); + case 40: return makeRegisterExpression(amdgpu_gfx908::s40, output_vec_len ); + case 41: return makeRegisterExpression(amdgpu_gfx908::s41, output_vec_len ); + case 42: return makeRegisterExpression(amdgpu_gfx908::s42, output_vec_len ); + case 43: return makeRegisterExpression(amdgpu_gfx908::s43, output_vec_len ); + case 44: return makeRegisterExpression(amdgpu_gfx908::s44, output_vec_len ); + case 45: return makeRegisterExpression(amdgpu_gfx908::s45, output_vec_len ); + case 46: return makeRegisterExpression(amdgpu_gfx908::s46, output_vec_len ); + case 47: return makeRegisterExpression(amdgpu_gfx908::s47, output_vec_len ); + case 48: return makeRegisterExpression(amdgpu_gfx908::s48, output_vec_len ); + case 49: return makeRegisterExpression(amdgpu_gfx908::s49, output_vec_len ); + case 50: return makeRegisterExpression(amdgpu_gfx908::s50, output_vec_len ); + case 51: return makeRegisterExpression(amdgpu_gfx908::s51, output_vec_len ); + case 52: return makeRegisterExpression(amdgpu_gfx908::s52, output_vec_len ); + case 53: return makeRegisterExpression(amdgpu_gfx908::s53, output_vec_len ); + case 54: return makeRegisterExpression(amdgpu_gfx908::s54, output_vec_len ); + case 55: return makeRegisterExpression(amdgpu_gfx908::s55, output_vec_len ); + case 56: return makeRegisterExpression(amdgpu_gfx908::s56, output_vec_len ); + case 57: return makeRegisterExpression(amdgpu_gfx908::s57, output_vec_len ); + case 58: return makeRegisterExpression(amdgpu_gfx908::s58, output_vec_len ); + case 59: return makeRegisterExpression(amdgpu_gfx908::s59, output_vec_len ); + case 60: return makeRegisterExpression(amdgpu_gfx908::s60, output_vec_len ); + case 61: return makeRegisterExpression(amdgpu_gfx908::s61, output_vec_len ); + case 62: return makeRegisterExpression(amdgpu_gfx908::s62, output_vec_len ); + case 63: return makeRegisterExpression(amdgpu_gfx908::s63, output_vec_len ); + case 64: return makeRegisterExpression(amdgpu_gfx908::s64, output_vec_len ); + case 65: return makeRegisterExpression(amdgpu_gfx908::s65, output_vec_len ); + case 66: return makeRegisterExpression(amdgpu_gfx908::s66, output_vec_len ); + case 67: return makeRegisterExpression(amdgpu_gfx908::s67, output_vec_len ); + case 68: return makeRegisterExpression(amdgpu_gfx908::s68, output_vec_len ); + case 69: return makeRegisterExpression(amdgpu_gfx908::s69, output_vec_len ); + case 70: return makeRegisterExpression(amdgpu_gfx908::s70, output_vec_len ); + case 71: return makeRegisterExpression(amdgpu_gfx908::s71, output_vec_len ); + case 72: return makeRegisterExpression(amdgpu_gfx908::s72, output_vec_len ); + case 73: return makeRegisterExpression(amdgpu_gfx908::s73, output_vec_len ); + case 74: return makeRegisterExpression(amdgpu_gfx908::s74, output_vec_len ); + case 75: return makeRegisterExpression(amdgpu_gfx908::s75, output_vec_len ); + case 76: return makeRegisterExpression(amdgpu_gfx908::s76, output_vec_len ); + case 77: return makeRegisterExpression(amdgpu_gfx908::s77, output_vec_len ); + case 78: return makeRegisterExpression(amdgpu_gfx908::s78, output_vec_len ); + case 79: return makeRegisterExpression(amdgpu_gfx908::s79, output_vec_len ); + case 80: return makeRegisterExpression(amdgpu_gfx908::s80, output_vec_len ); + case 81: return makeRegisterExpression(amdgpu_gfx908::s81, output_vec_len ); + case 82: return makeRegisterExpression(amdgpu_gfx908::s82, output_vec_len ); + case 83: return makeRegisterExpression(amdgpu_gfx908::s83, output_vec_len ); + case 84: return makeRegisterExpression(amdgpu_gfx908::s84, output_vec_len ); + case 85: return makeRegisterExpression(amdgpu_gfx908::s85, output_vec_len ); + case 86: return makeRegisterExpression(amdgpu_gfx908::s86, output_vec_len ); + case 87: return makeRegisterExpression(amdgpu_gfx908::s87, output_vec_len ); + case 88: return makeRegisterExpression(amdgpu_gfx908::s88, output_vec_len ); + case 89: return makeRegisterExpression(amdgpu_gfx908::s89, output_vec_len ); + case 90: return makeRegisterExpression(amdgpu_gfx908::s90, output_vec_len ); + case 91: return makeRegisterExpression(amdgpu_gfx908::s91, output_vec_len ); + case 92: return makeRegisterExpression(amdgpu_gfx908::s92, output_vec_len ); + case 93: return makeRegisterExpression(amdgpu_gfx908::s93, output_vec_len ); + case 94: return makeRegisterExpression(amdgpu_gfx908::s94, output_vec_len ); + case 95: return makeRegisterExpression(amdgpu_gfx908::s95, output_vec_len ); + case 96: return makeRegisterExpression(amdgpu_gfx908::s96, output_vec_len ); + case 97: return makeRegisterExpression(amdgpu_gfx908::s97, output_vec_len ); + case 98: return makeRegisterExpression(amdgpu_gfx908::s98, output_vec_len ); + case 99: return makeRegisterExpression(amdgpu_gfx908::s99, output_vec_len ); + case 100: return makeRegisterExpression(amdgpu_gfx908::s100, output_vec_len ); + case 101: return makeRegisterExpression(amdgpu_gfx908::s101, output_vec_len ); + case 104: return makeRegisterExpression(amdgpu_gfx908::xnack_mask_lo, output_vec_len ); + case 105: return makeRegisterExpression(amdgpu_gfx908::xnack_mask_hi, output_vec_len ); + case 102: return makeRegisterExpression(amdgpu_gfx908::flat_scratch_lo, output_vec_len ); + case 103: return makeRegisterExpression(amdgpu_gfx908::flat_scratch_hi, output_vec_len ); + case 108: return makeRegisterExpression(amdgpu_gfx908::ttmp0, output_vec_len ); + case 109: return makeRegisterExpression(amdgpu_gfx908::ttmp1, output_vec_len ); + case 110: return makeRegisterExpression(amdgpu_gfx908::ttmp2, output_vec_len ); + case 111: return makeRegisterExpression(amdgpu_gfx908::ttmp3, output_vec_len ); + case 112: return makeRegisterExpression(amdgpu_gfx908::ttmp4, output_vec_len ); + case 113: return makeRegisterExpression(amdgpu_gfx908::ttmp5, output_vec_len ); + case 114: return makeRegisterExpression(amdgpu_gfx908::ttmp6, output_vec_len ); + case 115: return makeRegisterExpression(amdgpu_gfx908::ttmp7, output_vec_len ); + case 116: return makeRegisterExpression(amdgpu_gfx908::ttmp8, output_vec_len ); + case 117: return makeRegisterExpression(amdgpu_gfx908::ttmp9, output_vec_len ); + case 118: return makeRegisterExpression(amdgpu_gfx908::ttmp10, output_vec_len ); + case 119: return makeRegisterExpression(amdgpu_gfx908::ttmp11, output_vec_len ); + case 120: return makeRegisterExpression(amdgpu_gfx908::ttmp12, output_vec_len ); + case 121: return makeRegisterExpression(amdgpu_gfx908::ttmp13, output_vec_len ); + case 122: return makeRegisterExpression(amdgpu_gfx908::ttmp14, output_vec_len ); + case 123: return makeRegisterExpression(amdgpu_gfx908::ttmp15, output_vec_len ); + case 106: return makeRegisterExpression(amdgpu_gfx908::vcc_lo, output_vec_len ); + case 107: return makeRegisterExpression(amdgpu_gfx908::vcc_hi, output_vec_len ); + case 124: return makeRegisterExpression(amdgpu_gfx908::m0, output_vec_len ); + case 128: return Immediate::makeImmediate(Result(u32, 0)); + case 129: return Immediate::makeImmediate(Result(u32, 1)); + case 130: return Immediate::makeImmediate(Result(u32, 2)); + case 131: return Immediate::makeImmediate(Result(u32, 3)); + case 132: return Immediate::makeImmediate(Result(u32, 4)); + case 133: return Immediate::makeImmediate(Result(u32, 5)); + case 134: return Immediate::makeImmediate(Result(u32, 6)); + case 135: return Immediate::makeImmediate(Result(u32, 7)); + case 136: return Immediate::makeImmediate(Result(u32, 8)); + case 137: return Immediate::makeImmediate(Result(u32, 9)); + case 138: return Immediate::makeImmediate(Result(u32, 10)); + case 139: return Immediate::makeImmediate(Result(u32, 11)); + case 140: return Immediate::makeImmediate(Result(u32, 12)); + case 141: return Immediate::makeImmediate(Result(u32, 13)); + case 142: return Immediate::makeImmediate(Result(u32, 14)); + case 143: return Immediate::makeImmediate(Result(u32, 15)); + case 144: return Immediate::makeImmediate(Result(u32, 16)); + case 145: return Immediate::makeImmediate(Result(u32, 17)); + case 146: return Immediate::makeImmediate(Result(u32, 18)); + case 147: return Immediate::makeImmediate(Result(u32, 19)); + case 148: return Immediate::makeImmediate(Result(u32, 20)); + case 149: return Immediate::makeImmediate(Result(u32, 21)); + case 150: return Immediate::makeImmediate(Result(u32, 22)); + case 151: return Immediate::makeImmediate(Result(u32, 23)); + case 152: return Immediate::makeImmediate(Result(u32, 24)); + case 153: return Immediate::makeImmediate(Result(u32, 25)); + case 154: return Immediate::makeImmediate(Result(u32, 26)); + case 155: return Immediate::makeImmediate(Result(u32, 27)); + case 156: return Immediate::makeImmediate(Result(u32, 28)); + case 157: return Immediate::makeImmediate(Result(u32, 29)); + case 158: return Immediate::makeImmediate(Result(u32, 30)); + case 159: return Immediate::makeImmediate(Result(u32, 31)); + case 160: return Immediate::makeImmediate(Result(u32, 32)); + case 161: return Immediate::makeImmediate(Result(u32, 33)); + case 162: return Immediate::makeImmediate(Result(u32, 34)); + case 163: return Immediate::makeImmediate(Result(u32, 35)); + case 164: return Immediate::makeImmediate(Result(u32, 36)); + case 165: return Immediate::makeImmediate(Result(u32, 37)); + case 166: return Immediate::makeImmediate(Result(u32, 38)); + case 167: return Immediate::makeImmediate(Result(u32, 39)); + case 168: return Immediate::makeImmediate(Result(u32, 40)); + case 169: return Immediate::makeImmediate(Result(u32, 41)); + case 170: return Immediate::makeImmediate(Result(u32, 42)); + case 171: return Immediate::makeImmediate(Result(u32, 43)); + case 172: return Immediate::makeImmediate(Result(u32, 44)); + case 173: return Immediate::makeImmediate(Result(u32, 45)); + case 174: return Immediate::makeImmediate(Result(u32, 46)); + case 175: return Immediate::makeImmediate(Result(u32, 47)); + case 176: return Immediate::makeImmediate(Result(u32, 48)); + case 177: return Immediate::makeImmediate(Result(u32, 49)); + case 178: return Immediate::makeImmediate(Result(u32, 50)); + case 179: return Immediate::makeImmediate(Result(u32, 51)); + case 180: return Immediate::makeImmediate(Result(u32, 52)); + case 181: return Immediate::makeImmediate(Result(u32, 53)); + case 182: return Immediate::makeImmediate(Result(u32, 54)); + case 183: return Immediate::makeImmediate(Result(u32, 55)); + case 184: return Immediate::makeImmediate(Result(u32, 56)); + case 185: return Immediate::makeImmediate(Result(u32, 57)); + case 186: return Immediate::makeImmediate(Result(u32, 58)); + case 187: return Immediate::makeImmediate(Result(u32, 59)); + case 188: return Immediate::makeImmediate(Result(u32, 60)); + case 189: return Immediate::makeImmediate(Result(u32, 61)); + case 190: return Immediate::makeImmediate(Result(u32, 62)); + case 191: return Immediate::makeImmediate(Result(u32, 63)); + default: return makeRegisterExpression(amdgpu_gfx908::invalid); + } + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SSRC_NOLIT(uint64_t input, uint32_t output_vec_len) + { + switch (input) { + case 0: return makeRegisterExpression(amdgpu_gfx908::s0, output_vec_len ); + case 1: return makeRegisterExpression(amdgpu_gfx908::s1, output_vec_len ); + case 2: return makeRegisterExpression(amdgpu_gfx908::s2, output_vec_len ); + case 3: return makeRegisterExpression(amdgpu_gfx908::s3, output_vec_len ); + case 4: return makeRegisterExpression(amdgpu_gfx908::s4, output_vec_len ); + case 5: return makeRegisterExpression(amdgpu_gfx908::s5, output_vec_len ); + case 6: return makeRegisterExpression(amdgpu_gfx908::s6, output_vec_len ); + case 7: return makeRegisterExpression(amdgpu_gfx908::s7, output_vec_len ); + case 8: return makeRegisterExpression(amdgpu_gfx908::s8, output_vec_len ); + case 9: return makeRegisterExpression(amdgpu_gfx908::s9, output_vec_len ); + case 10: return makeRegisterExpression(amdgpu_gfx908::s10, output_vec_len ); + case 11: return makeRegisterExpression(amdgpu_gfx908::s11, output_vec_len ); + case 12: return makeRegisterExpression(amdgpu_gfx908::s12, output_vec_len ); + case 13: return makeRegisterExpression(amdgpu_gfx908::s13, output_vec_len ); + case 14: return makeRegisterExpression(amdgpu_gfx908::s14, output_vec_len ); + case 15: return makeRegisterExpression(amdgpu_gfx908::s15, output_vec_len ); + case 16: return makeRegisterExpression(amdgpu_gfx908::s16, output_vec_len ); + case 17: return makeRegisterExpression(amdgpu_gfx908::s17, output_vec_len ); + case 18: return makeRegisterExpression(amdgpu_gfx908::s18, output_vec_len ); + case 19: return makeRegisterExpression(amdgpu_gfx908::s19, output_vec_len ); + case 20: return makeRegisterExpression(amdgpu_gfx908::s20, output_vec_len ); + case 21: return makeRegisterExpression(amdgpu_gfx908::s21, output_vec_len ); + case 22: return makeRegisterExpression(amdgpu_gfx908::s22, output_vec_len ); + case 23: return makeRegisterExpression(amdgpu_gfx908::s23, output_vec_len ); + case 24: return makeRegisterExpression(amdgpu_gfx908::s24, output_vec_len ); + case 25: return makeRegisterExpression(amdgpu_gfx908::s25, output_vec_len ); + case 26: return makeRegisterExpression(amdgpu_gfx908::s26, output_vec_len ); + case 27: return makeRegisterExpression(amdgpu_gfx908::s27, output_vec_len ); + case 28: return makeRegisterExpression(amdgpu_gfx908::s28, output_vec_len ); + case 29: return makeRegisterExpression(amdgpu_gfx908::s29, output_vec_len ); + case 30: return makeRegisterExpression(amdgpu_gfx908::s30, output_vec_len ); + case 31: return makeRegisterExpression(amdgpu_gfx908::s31, output_vec_len ); + case 32: return makeRegisterExpression(amdgpu_gfx908::s32, output_vec_len ); + case 33: return makeRegisterExpression(amdgpu_gfx908::s33, output_vec_len ); + case 34: return makeRegisterExpression(amdgpu_gfx908::s34, output_vec_len ); + case 35: return makeRegisterExpression(amdgpu_gfx908::s35, output_vec_len ); + case 36: return makeRegisterExpression(amdgpu_gfx908::s36, output_vec_len ); + case 37: return makeRegisterExpression(amdgpu_gfx908::s37, output_vec_len ); + case 38: return makeRegisterExpression(amdgpu_gfx908::s38, output_vec_len ); + case 39: return makeRegisterExpression(amdgpu_gfx908::s39, output_vec_len ); + case 40: return makeRegisterExpression(amdgpu_gfx908::s40, output_vec_len ); + case 41: return makeRegisterExpression(amdgpu_gfx908::s41, output_vec_len ); + case 42: return makeRegisterExpression(amdgpu_gfx908::s42, output_vec_len ); + case 43: return makeRegisterExpression(amdgpu_gfx908::s43, output_vec_len ); + case 44: return makeRegisterExpression(amdgpu_gfx908::s44, output_vec_len ); + case 45: return makeRegisterExpression(amdgpu_gfx908::s45, output_vec_len ); + case 46: return makeRegisterExpression(amdgpu_gfx908::s46, output_vec_len ); + case 47: return makeRegisterExpression(amdgpu_gfx908::s47, output_vec_len ); + case 48: return makeRegisterExpression(amdgpu_gfx908::s48, output_vec_len ); + case 49: return makeRegisterExpression(amdgpu_gfx908::s49, output_vec_len ); + case 50: return makeRegisterExpression(amdgpu_gfx908::s50, output_vec_len ); + case 51: return makeRegisterExpression(amdgpu_gfx908::s51, output_vec_len ); + case 52: return makeRegisterExpression(amdgpu_gfx908::s52, output_vec_len ); + case 53: return makeRegisterExpression(amdgpu_gfx908::s53, output_vec_len ); + case 54: return makeRegisterExpression(amdgpu_gfx908::s54, output_vec_len ); + case 55: return makeRegisterExpression(amdgpu_gfx908::s55, output_vec_len ); + case 56: return makeRegisterExpression(amdgpu_gfx908::s56, output_vec_len ); + case 57: return makeRegisterExpression(amdgpu_gfx908::s57, output_vec_len ); + case 58: return makeRegisterExpression(amdgpu_gfx908::s58, output_vec_len ); + case 59: return makeRegisterExpression(amdgpu_gfx908::s59, output_vec_len ); + case 60: return makeRegisterExpression(amdgpu_gfx908::s60, output_vec_len ); + case 61: return makeRegisterExpression(amdgpu_gfx908::s61, output_vec_len ); + case 62: return makeRegisterExpression(amdgpu_gfx908::s62, output_vec_len ); + case 63: return makeRegisterExpression(amdgpu_gfx908::s63, output_vec_len ); + case 64: return makeRegisterExpression(amdgpu_gfx908::s64, output_vec_len ); + case 65: return makeRegisterExpression(amdgpu_gfx908::s65, output_vec_len ); + case 66: return makeRegisterExpression(amdgpu_gfx908::s66, output_vec_len ); + case 67: return makeRegisterExpression(amdgpu_gfx908::s67, output_vec_len ); + case 68: return makeRegisterExpression(amdgpu_gfx908::s68, output_vec_len ); + case 69: return makeRegisterExpression(amdgpu_gfx908::s69, output_vec_len ); + case 70: return makeRegisterExpression(amdgpu_gfx908::s70, output_vec_len ); + case 71: return makeRegisterExpression(amdgpu_gfx908::s71, output_vec_len ); + case 72: return makeRegisterExpression(amdgpu_gfx908::s72, output_vec_len ); + case 73: return makeRegisterExpression(amdgpu_gfx908::s73, output_vec_len ); + case 74: return makeRegisterExpression(amdgpu_gfx908::s74, output_vec_len ); + case 75: return makeRegisterExpression(amdgpu_gfx908::s75, output_vec_len ); + case 76: return makeRegisterExpression(amdgpu_gfx908::s76, output_vec_len ); + case 77: return makeRegisterExpression(amdgpu_gfx908::s77, output_vec_len ); + case 78: return makeRegisterExpression(amdgpu_gfx908::s78, output_vec_len ); + case 79: return makeRegisterExpression(amdgpu_gfx908::s79, output_vec_len ); + case 80: return makeRegisterExpression(amdgpu_gfx908::s80, output_vec_len ); + case 81: return makeRegisterExpression(amdgpu_gfx908::s81, output_vec_len ); + case 82: return makeRegisterExpression(amdgpu_gfx908::s82, output_vec_len ); + case 83: return makeRegisterExpression(amdgpu_gfx908::s83, output_vec_len ); + case 84: return makeRegisterExpression(amdgpu_gfx908::s84, output_vec_len ); + case 85: return makeRegisterExpression(amdgpu_gfx908::s85, output_vec_len ); + case 86: return makeRegisterExpression(amdgpu_gfx908::s86, output_vec_len ); + case 87: return makeRegisterExpression(amdgpu_gfx908::s87, output_vec_len ); + case 88: return makeRegisterExpression(amdgpu_gfx908::s88, output_vec_len ); + case 89: return makeRegisterExpression(amdgpu_gfx908::s89, output_vec_len ); + case 90: return makeRegisterExpression(amdgpu_gfx908::s90, output_vec_len ); + case 91: return makeRegisterExpression(amdgpu_gfx908::s91, output_vec_len ); + case 92: return makeRegisterExpression(amdgpu_gfx908::s92, output_vec_len ); + case 93: return makeRegisterExpression(amdgpu_gfx908::s93, output_vec_len ); + case 94: return makeRegisterExpression(amdgpu_gfx908::s94, output_vec_len ); + case 95: return makeRegisterExpression(amdgpu_gfx908::s95, output_vec_len ); + case 96: return makeRegisterExpression(amdgpu_gfx908::s96, output_vec_len ); + case 97: return makeRegisterExpression(amdgpu_gfx908::s97, output_vec_len ); + case 98: return makeRegisterExpression(amdgpu_gfx908::s98, output_vec_len ); + case 99: return makeRegisterExpression(amdgpu_gfx908::s99, output_vec_len ); + case 100: return makeRegisterExpression(amdgpu_gfx908::s100, output_vec_len ); + case 101: return makeRegisterExpression(amdgpu_gfx908::s101, output_vec_len ); + case 104: return makeRegisterExpression(amdgpu_gfx908::xnack_mask_lo, output_vec_len ); + case 105: return makeRegisterExpression(amdgpu_gfx908::xnack_mask_hi, output_vec_len ); + case 102: return makeRegisterExpression(amdgpu_gfx908::flat_scratch_lo, output_vec_len ); + case 103: return makeRegisterExpression(amdgpu_gfx908::flat_scratch_hi, output_vec_len ); + case 108: return makeRegisterExpression(amdgpu_gfx908::ttmp0, output_vec_len ); + case 109: return makeRegisterExpression(amdgpu_gfx908::ttmp1, output_vec_len ); + case 110: return makeRegisterExpression(amdgpu_gfx908::ttmp2, output_vec_len ); + case 111: return makeRegisterExpression(amdgpu_gfx908::ttmp3, output_vec_len ); + case 112: return makeRegisterExpression(amdgpu_gfx908::ttmp4, output_vec_len ); + case 113: return makeRegisterExpression(amdgpu_gfx908::ttmp5, output_vec_len ); + case 114: return makeRegisterExpression(amdgpu_gfx908::ttmp6, output_vec_len ); + case 115: return makeRegisterExpression(amdgpu_gfx908::ttmp7, output_vec_len ); + case 116: return makeRegisterExpression(amdgpu_gfx908::ttmp8, output_vec_len ); + case 117: return makeRegisterExpression(amdgpu_gfx908::ttmp9, output_vec_len ); + case 118: return makeRegisterExpression(amdgpu_gfx908::ttmp10, output_vec_len ); + case 119: return makeRegisterExpression(amdgpu_gfx908::ttmp11, output_vec_len ); + case 120: return makeRegisterExpression(amdgpu_gfx908::ttmp12, output_vec_len ); + case 121: return makeRegisterExpression(amdgpu_gfx908::ttmp13, output_vec_len ); + case 122: return makeRegisterExpression(amdgpu_gfx908::ttmp14, output_vec_len ); + case 123: return makeRegisterExpression(amdgpu_gfx908::ttmp15, output_vec_len ); + case 106: return makeRegisterExpression(amdgpu_gfx908::vcc_lo, output_vec_len ); + case 107: return makeRegisterExpression(amdgpu_gfx908::vcc_hi, output_vec_len ); + case 124: return makeRegisterExpression(amdgpu_gfx908::m0, output_vec_len ); + case 126: return makeRegisterExpression(amdgpu_gfx908::exec_lo, output_vec_len ); + case 127: return makeRegisterExpression(amdgpu_gfx908::exec_hi, output_vec_len ); + case 128: return Immediate::makeImmediate(Result(u32, 0)); + case 129: return Immediate::makeImmediate(Result(u32, 1)); + case 130: return Immediate::makeImmediate(Result(u32, 2)); + case 131: return Immediate::makeImmediate(Result(u32, 3)); + case 132: return Immediate::makeImmediate(Result(u32, 4)); + case 133: return Immediate::makeImmediate(Result(u32, 5)); + case 134: return Immediate::makeImmediate(Result(u32, 6)); + case 135: return Immediate::makeImmediate(Result(u32, 7)); + case 136: return Immediate::makeImmediate(Result(u32, 8)); + case 137: return Immediate::makeImmediate(Result(u32, 9)); + case 138: return Immediate::makeImmediate(Result(u32, 10)); + case 139: return Immediate::makeImmediate(Result(u32, 11)); + case 140: return Immediate::makeImmediate(Result(u32, 12)); + case 141: return Immediate::makeImmediate(Result(u32, 13)); + case 142: return Immediate::makeImmediate(Result(u32, 14)); + case 143: return Immediate::makeImmediate(Result(u32, 15)); + case 144: return Immediate::makeImmediate(Result(u32, 16)); + case 145: return Immediate::makeImmediate(Result(u32, 17)); + case 146: return Immediate::makeImmediate(Result(u32, 18)); + case 147: return Immediate::makeImmediate(Result(u32, 19)); + case 148: return Immediate::makeImmediate(Result(u32, 20)); + case 149: return Immediate::makeImmediate(Result(u32, 21)); + case 150: return Immediate::makeImmediate(Result(u32, 22)); + case 151: return Immediate::makeImmediate(Result(u32, 23)); + case 152: return Immediate::makeImmediate(Result(u32, 24)); + case 153: return Immediate::makeImmediate(Result(u32, 25)); + case 154: return Immediate::makeImmediate(Result(u32, 26)); + case 155: return Immediate::makeImmediate(Result(u32, 27)); + case 156: return Immediate::makeImmediate(Result(u32, 28)); + case 157: return Immediate::makeImmediate(Result(u32, 29)); + case 158: return Immediate::makeImmediate(Result(u32, 30)); + case 159: return Immediate::makeImmediate(Result(u32, 31)); + case 160: return Immediate::makeImmediate(Result(u32, 32)); + case 161: return Immediate::makeImmediate(Result(u32, 33)); + case 162: return Immediate::makeImmediate(Result(u32, 34)); + case 163: return Immediate::makeImmediate(Result(u32, 35)); + case 164: return Immediate::makeImmediate(Result(u32, 36)); + case 165: return Immediate::makeImmediate(Result(u32, 37)); + case 166: return Immediate::makeImmediate(Result(u32, 38)); + case 167: return Immediate::makeImmediate(Result(u32, 39)); + case 168: return Immediate::makeImmediate(Result(u32, 40)); + case 169: return Immediate::makeImmediate(Result(u32, 41)); + case 170: return Immediate::makeImmediate(Result(u32, 42)); + case 171: return Immediate::makeImmediate(Result(u32, 43)); + case 172: return Immediate::makeImmediate(Result(u32, 44)); + case 173: return Immediate::makeImmediate(Result(u32, 45)); + case 174: return Immediate::makeImmediate(Result(u32, 46)); + case 175: return Immediate::makeImmediate(Result(u32, 47)); + case 176: return Immediate::makeImmediate(Result(u32, 48)); + case 177: return Immediate::makeImmediate(Result(u32, 49)); + case 178: return Immediate::makeImmediate(Result(u32, 50)); + case 179: return Immediate::makeImmediate(Result(u32, 51)); + case 180: return Immediate::makeImmediate(Result(u32, 52)); + case 181: return Immediate::makeImmediate(Result(u32, 53)); + case 182: return Immediate::makeImmediate(Result(u32, 54)); + case 183: return Immediate::makeImmediate(Result(u32, 55)); + case 184: return Immediate::makeImmediate(Result(u32, 56)); + case 185: return Immediate::makeImmediate(Result(u32, 57)); + case 186: return Immediate::makeImmediate(Result(u32, 58)); + case 187: return Immediate::makeImmediate(Result(u32, 59)); + case 188: return Immediate::makeImmediate(Result(u32, 60)); + case 189: return Immediate::makeImmediate(Result(u32, 61)); + case 190: return Immediate::makeImmediate(Result(u32, 62)); + case 191: return Immediate::makeImmediate(Result(u32, 63)); + case 192: return Immediate::makeImmediate(Result(u32, 64)); + case 193: return Immediate::makeImmediate(Result(u32, -1)); + case 194: return Immediate::makeImmediate(Result(u32, -2)); + case 195: return Immediate::makeImmediate(Result(u32, -3)); + case 196: return Immediate::makeImmediate(Result(u32, -4)); + case 197: return Immediate::makeImmediate(Result(u32, -5)); + case 198: return Immediate::makeImmediate(Result(u32, -6)); + case 199: return Immediate::makeImmediate(Result(u32, -7)); + case 200: return Immediate::makeImmediate(Result(u32, -8)); + case 201: return Immediate::makeImmediate(Result(u32, -9)); + case 202: return Immediate::makeImmediate(Result(u32, -10)); + case 203: return Immediate::makeImmediate(Result(u32, -11)); + case 204: return Immediate::makeImmediate(Result(u32, -12)); + case 205: return Immediate::makeImmediate(Result(u32, -13)); + case 206: return Immediate::makeImmediate(Result(u32, -14)); + case 207: return Immediate::makeImmediate(Result(u32, -15)); + case 208: return Immediate::makeImmediate(Result(u32, -16)); + case 240: return Immediate::makeImmediate(Result(sp_float, 0.5)); + case 241: return Immediate::makeImmediate(Result(sp_float, -0.5)); + case 242: return Immediate::makeImmediate(Result(sp_float, 1.0)); + case 243: return Immediate::makeImmediate(Result(sp_float, -1.0)); + case 244: return Immediate::makeImmediate(Result(sp_float, 2.0)); + case 245: return Immediate::makeImmediate(Result(sp_float, -2.0)); + case 246: return Immediate::makeImmediate(Result(sp_float, 4.0)); + case 247: return Immediate::makeImmediate(Result(sp_float, -4.0)); + case 248: return Immediate::makeImmediate(Result(sp_float, 0.15915494)); + case 251: return makeRegisterExpression(amdgpu_gfx908::src_vccz, output_vec_len ); + case 252: return makeRegisterExpression(amdgpu_gfx908::src_execz, output_vec_len ); + case 253: return makeRegisterExpression(amdgpu_gfx908::src_scc, output_vec_len ); + case 235: return makeRegisterExpression(amdgpu_gfx908::src_shared_base, output_vec_len ); + case 236: return makeRegisterExpression(amdgpu_gfx908::src_shared_limit, output_vec_len ); + case 237: return makeRegisterExpression(amdgpu_gfx908::src_private_base, output_vec_len ); + case 238: return makeRegisterExpression(amdgpu_gfx908::src_private_limit, output_vec_len ); + case 239: return makeRegisterExpression(amdgpu_gfx908::src_pops_exiting_wave_id, output_vec_len ); + default: return makeRegisterExpression(amdgpu_gfx908::invalid); + } + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_SSRC_SPECIAL_SCC(uint64_t input, uint32_t output_vec_len) + { + switch (input) { + case 253: return makeRegisterExpression(amdgpu_gfx908::src_scc, output_vec_len ); + default: return makeRegisterExpression(amdgpu_gfx908::invalid); + } + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_TGT(uint64_t input, uint32_t output_vec_len) + { + switch (input) { + case 0: return makeRegisterExpression(amdgpu_gfx908::mrt0, output_vec_len ); + case 1: return makeRegisterExpression(amdgpu_gfx908::mrt1, output_vec_len ); + case 2: return makeRegisterExpression(amdgpu_gfx908::mrt2, output_vec_len ); + case 3: return makeRegisterExpression(amdgpu_gfx908::mrt3, output_vec_len ); + case 4: return makeRegisterExpression(amdgpu_gfx908::mrt4, output_vec_len ); + case 5: return makeRegisterExpression(amdgpu_gfx908::mrt5, output_vec_len ); + case 6: return makeRegisterExpression(amdgpu_gfx908::mrt6, output_vec_len ); + case 7: return makeRegisterExpression(amdgpu_gfx908::mrt7, output_vec_len ); + case 8: return makeRegisterExpression(amdgpu_gfx908::mrtz, output_vec_len ); + case 9: return makeRegisterExpression(amdgpu_gfx908::null, output_vec_len ); + case 12: return makeRegisterExpression(amdgpu_gfx908::pos0, output_vec_len ); + case 13: return makeRegisterExpression(amdgpu_gfx908::pos1, output_vec_len ); + case 14: return makeRegisterExpression(amdgpu_gfx908::pos2, output_vec_len ); + case 15: return makeRegisterExpression(amdgpu_gfx908::pos3, output_vec_len ); + case 32: return makeRegisterExpression(amdgpu_gfx908::param0, output_vec_len ); + case 33: return makeRegisterExpression(amdgpu_gfx908::param1, output_vec_len ); + case 34: return makeRegisterExpression(amdgpu_gfx908::param2, output_vec_len ); + case 35: return makeRegisterExpression(amdgpu_gfx908::param3, output_vec_len ); + case 36: return makeRegisterExpression(amdgpu_gfx908::param4, output_vec_len ); + case 37: return makeRegisterExpression(amdgpu_gfx908::param5, output_vec_len ); + case 38: return makeRegisterExpression(amdgpu_gfx908::param6, output_vec_len ); + case 39: return makeRegisterExpression(amdgpu_gfx908::param7, output_vec_len ); + case 40: return makeRegisterExpression(amdgpu_gfx908::param8, output_vec_len ); + case 41: return makeRegisterExpression(amdgpu_gfx908::param9, output_vec_len ); + case 42: return makeRegisterExpression(amdgpu_gfx908::param10, output_vec_len ); + case 43: return makeRegisterExpression(amdgpu_gfx908::param11, output_vec_len ); + case 44: return makeRegisterExpression(amdgpu_gfx908::param12, output_vec_len ); + case 45: return makeRegisterExpression(amdgpu_gfx908::param13, output_vec_len ); + case 46: return makeRegisterExpression(amdgpu_gfx908::param14, output_vec_len ); + case 47: return makeRegisterExpression(amdgpu_gfx908::param15, output_vec_len ); + case 48: return makeRegisterExpression(amdgpu_gfx908::param16, output_vec_len ); + case 49: return makeRegisterExpression(amdgpu_gfx908::param17, output_vec_len ); + case 50: return makeRegisterExpression(amdgpu_gfx908::param18, output_vec_len ); + case 51: return makeRegisterExpression(amdgpu_gfx908::param19, output_vec_len ); + case 52: return makeRegisterExpression(amdgpu_gfx908::param20, output_vec_len ); + case 53: return makeRegisterExpression(amdgpu_gfx908::param21, output_vec_len ); + case 54: return makeRegisterExpression(amdgpu_gfx908::param22, output_vec_len ); + case 55: return makeRegisterExpression(amdgpu_gfx908::param23, output_vec_len ); + case 56: return makeRegisterExpression(amdgpu_gfx908::param24, output_vec_len ); + case 57: return makeRegisterExpression(amdgpu_gfx908::param25, output_vec_len ); + case 58: return makeRegisterExpression(amdgpu_gfx908::param26, output_vec_len ); + case 59: return makeRegisterExpression(amdgpu_gfx908::param27, output_vec_len ); + case 60: return makeRegisterExpression(amdgpu_gfx908::param28, output_vec_len ); + case 61: return makeRegisterExpression(amdgpu_gfx908::param29, output_vec_len ); + case 62: return makeRegisterExpression(amdgpu_gfx908::param30, output_vec_len ); + case 63: return makeRegisterExpression(amdgpu_gfx908::param31, output_vec_len ); + default: return makeRegisterExpression(amdgpu_gfx908::invalid); + } + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_VCC(uint64_t input, uint32_t ) + { + switch (input) { + case 0: return makeRegisterExpression(amdgpu_gfx908::vcc); + default: return makeRegisterExpression(amdgpu_gfx908::invalid); + } + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_VGPR(uint64_t input, uint32_t output_vec_len) + { + switch (input) { + case 0: return makeRegisterExpression(amdgpu_gfx908::v0, output_vec_len ); + case 1: return makeRegisterExpression(amdgpu_gfx908::v1, output_vec_len ); + case 2: return makeRegisterExpression(amdgpu_gfx908::v2, output_vec_len ); + case 3: return makeRegisterExpression(amdgpu_gfx908::v3, output_vec_len ); + case 4: return makeRegisterExpression(amdgpu_gfx908::v4, output_vec_len ); + case 5: return makeRegisterExpression(amdgpu_gfx908::v5, output_vec_len ); + case 6: return makeRegisterExpression(amdgpu_gfx908::v6, output_vec_len ); + case 7: return makeRegisterExpression(amdgpu_gfx908::v7, output_vec_len ); + case 8: return makeRegisterExpression(amdgpu_gfx908::v8, output_vec_len ); + case 9: return makeRegisterExpression(amdgpu_gfx908::v9, output_vec_len ); + case 10: return makeRegisterExpression(amdgpu_gfx908::v10, output_vec_len ); + case 11: return makeRegisterExpression(amdgpu_gfx908::v11, output_vec_len ); + case 12: return makeRegisterExpression(amdgpu_gfx908::v12, output_vec_len ); + case 13: return makeRegisterExpression(amdgpu_gfx908::v13, output_vec_len ); + case 14: return makeRegisterExpression(amdgpu_gfx908::v14, output_vec_len ); + case 15: return makeRegisterExpression(amdgpu_gfx908::v15, output_vec_len ); + case 16: return makeRegisterExpression(amdgpu_gfx908::v16, output_vec_len ); + case 17: return makeRegisterExpression(amdgpu_gfx908::v17, output_vec_len ); + case 18: return makeRegisterExpression(amdgpu_gfx908::v18, output_vec_len ); + case 19: return makeRegisterExpression(amdgpu_gfx908::v19, output_vec_len ); + case 20: return makeRegisterExpression(amdgpu_gfx908::v20, output_vec_len ); + case 21: return makeRegisterExpression(amdgpu_gfx908::v21, output_vec_len ); + case 22: return makeRegisterExpression(amdgpu_gfx908::v22, output_vec_len ); + case 23: return makeRegisterExpression(amdgpu_gfx908::v23, output_vec_len ); + case 24: return makeRegisterExpression(amdgpu_gfx908::v24, output_vec_len ); + case 25: return makeRegisterExpression(amdgpu_gfx908::v25, output_vec_len ); + case 26: return makeRegisterExpression(amdgpu_gfx908::v26, output_vec_len ); + case 27: return makeRegisterExpression(amdgpu_gfx908::v27, output_vec_len ); + case 28: return makeRegisterExpression(amdgpu_gfx908::v28, output_vec_len ); + case 29: return makeRegisterExpression(amdgpu_gfx908::v29, output_vec_len ); + case 30: return makeRegisterExpression(amdgpu_gfx908::v30, output_vec_len ); + case 31: return makeRegisterExpression(amdgpu_gfx908::v31, output_vec_len ); + case 32: return makeRegisterExpression(amdgpu_gfx908::v32, output_vec_len ); + case 33: return makeRegisterExpression(amdgpu_gfx908::v33, output_vec_len ); + case 34: return makeRegisterExpression(amdgpu_gfx908::v34, output_vec_len ); + case 35: return makeRegisterExpression(amdgpu_gfx908::v35, output_vec_len ); + case 36: return makeRegisterExpression(amdgpu_gfx908::v36, output_vec_len ); + case 37: return makeRegisterExpression(amdgpu_gfx908::v37, output_vec_len ); + case 38: return makeRegisterExpression(amdgpu_gfx908::v38, output_vec_len ); + case 39: return makeRegisterExpression(amdgpu_gfx908::v39, output_vec_len ); + case 40: return makeRegisterExpression(amdgpu_gfx908::v40, output_vec_len ); + case 41: return makeRegisterExpression(amdgpu_gfx908::v41, output_vec_len ); + case 42: return makeRegisterExpression(amdgpu_gfx908::v42, output_vec_len ); + case 43: return makeRegisterExpression(amdgpu_gfx908::v43, output_vec_len ); + case 44: return makeRegisterExpression(amdgpu_gfx908::v44, output_vec_len ); + case 45: return makeRegisterExpression(amdgpu_gfx908::v45, output_vec_len ); + case 46: return makeRegisterExpression(amdgpu_gfx908::v46, output_vec_len ); + case 47: return makeRegisterExpression(amdgpu_gfx908::v47, output_vec_len ); + case 48: return makeRegisterExpression(amdgpu_gfx908::v48, output_vec_len ); + case 49: return makeRegisterExpression(amdgpu_gfx908::v49, output_vec_len ); + case 50: return makeRegisterExpression(amdgpu_gfx908::v50, output_vec_len ); + case 51: return makeRegisterExpression(amdgpu_gfx908::v51, output_vec_len ); + case 52: return makeRegisterExpression(amdgpu_gfx908::v52, output_vec_len ); + case 53: return makeRegisterExpression(amdgpu_gfx908::v53, output_vec_len ); + case 54: return makeRegisterExpression(amdgpu_gfx908::v54, output_vec_len ); + case 55: return makeRegisterExpression(amdgpu_gfx908::v55, output_vec_len ); + case 56: return makeRegisterExpression(amdgpu_gfx908::v56, output_vec_len ); + case 57: return makeRegisterExpression(amdgpu_gfx908::v57, output_vec_len ); + case 58: return makeRegisterExpression(amdgpu_gfx908::v58, output_vec_len ); + case 59: return makeRegisterExpression(amdgpu_gfx908::v59, output_vec_len ); + case 60: return makeRegisterExpression(amdgpu_gfx908::v60, output_vec_len ); + case 61: return makeRegisterExpression(amdgpu_gfx908::v61, output_vec_len ); + case 62: return makeRegisterExpression(amdgpu_gfx908::v62, output_vec_len ); + case 63: return makeRegisterExpression(amdgpu_gfx908::v63, output_vec_len ); + case 64: return makeRegisterExpression(amdgpu_gfx908::v64, output_vec_len ); + case 65: return makeRegisterExpression(amdgpu_gfx908::v65, output_vec_len ); + case 66: return makeRegisterExpression(amdgpu_gfx908::v66, output_vec_len ); + case 67: return makeRegisterExpression(amdgpu_gfx908::v67, output_vec_len ); + case 68: return makeRegisterExpression(amdgpu_gfx908::v68, output_vec_len ); + case 69: return makeRegisterExpression(amdgpu_gfx908::v69, output_vec_len ); + case 70: return makeRegisterExpression(amdgpu_gfx908::v70, output_vec_len ); + case 71: return makeRegisterExpression(amdgpu_gfx908::v71, output_vec_len ); + case 72: return makeRegisterExpression(amdgpu_gfx908::v72, output_vec_len ); + case 73: return makeRegisterExpression(amdgpu_gfx908::v73, output_vec_len ); + case 74: return makeRegisterExpression(amdgpu_gfx908::v74, output_vec_len ); + case 75: return makeRegisterExpression(amdgpu_gfx908::v75, output_vec_len ); + case 76: return makeRegisterExpression(amdgpu_gfx908::v76, output_vec_len ); + case 77: return makeRegisterExpression(amdgpu_gfx908::v77, output_vec_len ); + case 78: return makeRegisterExpression(amdgpu_gfx908::v78, output_vec_len ); + case 79: return makeRegisterExpression(amdgpu_gfx908::v79, output_vec_len ); + case 80: return makeRegisterExpression(amdgpu_gfx908::v80, output_vec_len ); + case 81: return makeRegisterExpression(amdgpu_gfx908::v81, output_vec_len ); + case 82: return makeRegisterExpression(amdgpu_gfx908::v82, output_vec_len ); + case 83: return makeRegisterExpression(amdgpu_gfx908::v83, output_vec_len ); + case 84: return makeRegisterExpression(amdgpu_gfx908::v84, output_vec_len ); + case 85: return makeRegisterExpression(amdgpu_gfx908::v85, output_vec_len ); + case 86: return makeRegisterExpression(amdgpu_gfx908::v86, output_vec_len ); + case 87: return makeRegisterExpression(amdgpu_gfx908::v87, output_vec_len ); + case 88: return makeRegisterExpression(amdgpu_gfx908::v88, output_vec_len ); + case 89: return makeRegisterExpression(amdgpu_gfx908::v89, output_vec_len ); + case 90: return makeRegisterExpression(amdgpu_gfx908::v90, output_vec_len ); + case 91: return makeRegisterExpression(amdgpu_gfx908::v91, output_vec_len ); + case 92: return makeRegisterExpression(amdgpu_gfx908::v92, output_vec_len ); + case 93: return makeRegisterExpression(amdgpu_gfx908::v93, output_vec_len ); + case 94: return makeRegisterExpression(amdgpu_gfx908::v94, output_vec_len ); + case 95: return makeRegisterExpression(amdgpu_gfx908::v95, output_vec_len ); + case 96: return makeRegisterExpression(amdgpu_gfx908::v96, output_vec_len ); + case 97: return makeRegisterExpression(amdgpu_gfx908::v97, output_vec_len ); + case 98: return makeRegisterExpression(amdgpu_gfx908::v98, output_vec_len ); + case 99: return makeRegisterExpression(amdgpu_gfx908::v99, output_vec_len ); + case 100: return makeRegisterExpression(amdgpu_gfx908::v100, output_vec_len ); + case 101: return makeRegisterExpression(amdgpu_gfx908::v101, output_vec_len ); + case 102: return makeRegisterExpression(amdgpu_gfx908::v102, output_vec_len ); + case 103: return makeRegisterExpression(amdgpu_gfx908::v103, output_vec_len ); + case 104: return makeRegisterExpression(amdgpu_gfx908::v104, output_vec_len ); + case 105: return makeRegisterExpression(amdgpu_gfx908::v105, output_vec_len ); + case 106: return makeRegisterExpression(amdgpu_gfx908::v106, output_vec_len ); + case 107: return makeRegisterExpression(amdgpu_gfx908::v107, output_vec_len ); + case 108: return makeRegisterExpression(amdgpu_gfx908::v108, output_vec_len ); + case 109: return makeRegisterExpression(amdgpu_gfx908::v109, output_vec_len ); + case 110: return makeRegisterExpression(amdgpu_gfx908::v110, output_vec_len ); + case 111: return makeRegisterExpression(amdgpu_gfx908::v111, output_vec_len ); + case 112: return makeRegisterExpression(amdgpu_gfx908::v112, output_vec_len ); + case 113: return makeRegisterExpression(amdgpu_gfx908::v113, output_vec_len ); + case 114: return makeRegisterExpression(amdgpu_gfx908::v114, output_vec_len ); + case 115: return makeRegisterExpression(amdgpu_gfx908::v115, output_vec_len ); + case 116: return makeRegisterExpression(amdgpu_gfx908::v116, output_vec_len ); + case 117: return makeRegisterExpression(amdgpu_gfx908::v117, output_vec_len ); + case 118: return makeRegisterExpression(amdgpu_gfx908::v118, output_vec_len ); + case 119: return makeRegisterExpression(amdgpu_gfx908::v119, output_vec_len ); + case 120: return makeRegisterExpression(amdgpu_gfx908::v120, output_vec_len ); + case 121: return makeRegisterExpression(amdgpu_gfx908::v121, output_vec_len ); + case 122: return makeRegisterExpression(amdgpu_gfx908::v122, output_vec_len ); + case 123: return makeRegisterExpression(amdgpu_gfx908::v123, output_vec_len ); + case 124: return makeRegisterExpression(amdgpu_gfx908::v124, output_vec_len ); + case 125: return makeRegisterExpression(amdgpu_gfx908::v125, output_vec_len ); + case 126: return makeRegisterExpression(amdgpu_gfx908::v126, output_vec_len ); + case 127: return makeRegisterExpression(amdgpu_gfx908::v127, output_vec_len ); + case 128: return makeRegisterExpression(amdgpu_gfx908::v128, output_vec_len ); + case 129: return makeRegisterExpression(amdgpu_gfx908::v129, output_vec_len ); + case 130: return makeRegisterExpression(amdgpu_gfx908::v130, output_vec_len ); + case 131: return makeRegisterExpression(amdgpu_gfx908::v131, output_vec_len ); + case 132: return makeRegisterExpression(amdgpu_gfx908::v132, output_vec_len ); + case 133: return makeRegisterExpression(amdgpu_gfx908::v133, output_vec_len ); + case 134: return makeRegisterExpression(amdgpu_gfx908::v134, output_vec_len ); + case 135: return makeRegisterExpression(amdgpu_gfx908::v135, output_vec_len ); + case 136: return makeRegisterExpression(amdgpu_gfx908::v136, output_vec_len ); + case 137: return makeRegisterExpression(amdgpu_gfx908::v137, output_vec_len ); + case 138: return makeRegisterExpression(amdgpu_gfx908::v138, output_vec_len ); + case 139: return makeRegisterExpression(amdgpu_gfx908::v139, output_vec_len ); + case 140: return makeRegisterExpression(amdgpu_gfx908::v140, output_vec_len ); + case 141: return makeRegisterExpression(amdgpu_gfx908::v141, output_vec_len ); + case 142: return makeRegisterExpression(amdgpu_gfx908::v142, output_vec_len ); + case 143: return makeRegisterExpression(amdgpu_gfx908::v143, output_vec_len ); + case 144: return makeRegisterExpression(amdgpu_gfx908::v144, output_vec_len ); + case 145: return makeRegisterExpression(amdgpu_gfx908::v145, output_vec_len ); + case 146: return makeRegisterExpression(amdgpu_gfx908::v146, output_vec_len ); + case 147: return makeRegisterExpression(amdgpu_gfx908::v147, output_vec_len ); + case 148: return makeRegisterExpression(amdgpu_gfx908::v148, output_vec_len ); + case 149: return makeRegisterExpression(amdgpu_gfx908::v149, output_vec_len ); + case 150: return makeRegisterExpression(amdgpu_gfx908::v150, output_vec_len ); + case 151: return makeRegisterExpression(amdgpu_gfx908::v151, output_vec_len ); + case 152: return makeRegisterExpression(amdgpu_gfx908::v152, output_vec_len ); + case 153: return makeRegisterExpression(amdgpu_gfx908::v153, output_vec_len ); + case 154: return makeRegisterExpression(amdgpu_gfx908::v154, output_vec_len ); + case 155: return makeRegisterExpression(amdgpu_gfx908::v155, output_vec_len ); + case 156: return makeRegisterExpression(amdgpu_gfx908::v156, output_vec_len ); + case 157: return makeRegisterExpression(amdgpu_gfx908::v157, output_vec_len ); + case 158: return makeRegisterExpression(amdgpu_gfx908::v158, output_vec_len ); + case 159: return makeRegisterExpression(amdgpu_gfx908::v159, output_vec_len ); + case 160: return makeRegisterExpression(amdgpu_gfx908::v160, output_vec_len ); + case 161: return makeRegisterExpression(amdgpu_gfx908::v161, output_vec_len ); + case 162: return makeRegisterExpression(amdgpu_gfx908::v162, output_vec_len ); + case 163: return makeRegisterExpression(amdgpu_gfx908::v163, output_vec_len ); + case 164: return makeRegisterExpression(amdgpu_gfx908::v164, output_vec_len ); + case 165: return makeRegisterExpression(amdgpu_gfx908::v165, output_vec_len ); + case 166: return makeRegisterExpression(amdgpu_gfx908::v166, output_vec_len ); + case 167: return makeRegisterExpression(amdgpu_gfx908::v167, output_vec_len ); + case 168: return makeRegisterExpression(amdgpu_gfx908::v168, output_vec_len ); + case 169: return makeRegisterExpression(amdgpu_gfx908::v169, output_vec_len ); + case 170: return makeRegisterExpression(amdgpu_gfx908::v170, output_vec_len ); + case 171: return makeRegisterExpression(amdgpu_gfx908::v171, output_vec_len ); + case 172: return makeRegisterExpression(amdgpu_gfx908::v172, output_vec_len ); + case 173: return makeRegisterExpression(amdgpu_gfx908::v173, output_vec_len ); + case 174: return makeRegisterExpression(amdgpu_gfx908::v174, output_vec_len ); + case 175: return makeRegisterExpression(amdgpu_gfx908::v175, output_vec_len ); + case 176: return makeRegisterExpression(amdgpu_gfx908::v176, output_vec_len ); + case 177: return makeRegisterExpression(amdgpu_gfx908::v177, output_vec_len ); + case 178: return makeRegisterExpression(amdgpu_gfx908::v178, output_vec_len ); + case 179: return makeRegisterExpression(amdgpu_gfx908::v179, output_vec_len ); + case 180: return makeRegisterExpression(amdgpu_gfx908::v180, output_vec_len ); + case 181: return makeRegisterExpression(amdgpu_gfx908::v181, output_vec_len ); + case 182: return makeRegisterExpression(amdgpu_gfx908::v182, output_vec_len ); + case 183: return makeRegisterExpression(amdgpu_gfx908::v183, output_vec_len ); + case 184: return makeRegisterExpression(amdgpu_gfx908::v184, output_vec_len ); + case 185: return makeRegisterExpression(amdgpu_gfx908::v185, output_vec_len ); + case 186: return makeRegisterExpression(amdgpu_gfx908::v186, output_vec_len ); + case 187: return makeRegisterExpression(amdgpu_gfx908::v187, output_vec_len ); + case 188: return makeRegisterExpression(amdgpu_gfx908::v188, output_vec_len ); + case 189: return makeRegisterExpression(amdgpu_gfx908::v189, output_vec_len ); + case 190: return makeRegisterExpression(amdgpu_gfx908::v190, output_vec_len ); + case 191: return makeRegisterExpression(amdgpu_gfx908::v191, output_vec_len ); + case 192: return makeRegisterExpression(amdgpu_gfx908::v192, output_vec_len ); + case 193: return makeRegisterExpression(amdgpu_gfx908::v193, output_vec_len ); + case 194: return makeRegisterExpression(amdgpu_gfx908::v194, output_vec_len ); + case 195: return makeRegisterExpression(amdgpu_gfx908::v195, output_vec_len ); + case 196: return makeRegisterExpression(amdgpu_gfx908::v196, output_vec_len ); + case 197: return makeRegisterExpression(amdgpu_gfx908::v197, output_vec_len ); + case 198: return makeRegisterExpression(amdgpu_gfx908::v198, output_vec_len ); + case 199: return makeRegisterExpression(amdgpu_gfx908::v199, output_vec_len ); + case 200: return makeRegisterExpression(amdgpu_gfx908::v200, output_vec_len ); + case 201: return makeRegisterExpression(amdgpu_gfx908::v201, output_vec_len ); + case 202: return makeRegisterExpression(amdgpu_gfx908::v202, output_vec_len ); + case 203: return makeRegisterExpression(amdgpu_gfx908::v203, output_vec_len ); + case 204: return makeRegisterExpression(amdgpu_gfx908::v204, output_vec_len ); + case 205: return makeRegisterExpression(amdgpu_gfx908::v205, output_vec_len ); + case 206: return makeRegisterExpression(amdgpu_gfx908::v206, output_vec_len ); + case 207: return makeRegisterExpression(amdgpu_gfx908::v207, output_vec_len ); + case 208: return makeRegisterExpression(amdgpu_gfx908::v208, output_vec_len ); + case 209: return makeRegisterExpression(amdgpu_gfx908::v209, output_vec_len ); + case 210: return makeRegisterExpression(amdgpu_gfx908::v210, output_vec_len ); + case 211: return makeRegisterExpression(amdgpu_gfx908::v211, output_vec_len ); + case 212: return makeRegisterExpression(amdgpu_gfx908::v212, output_vec_len ); + case 213: return makeRegisterExpression(amdgpu_gfx908::v213, output_vec_len ); + case 214: return makeRegisterExpression(amdgpu_gfx908::v214, output_vec_len ); + case 215: return makeRegisterExpression(amdgpu_gfx908::v215, output_vec_len ); + case 216: return makeRegisterExpression(amdgpu_gfx908::v216, output_vec_len ); + case 217: return makeRegisterExpression(amdgpu_gfx908::v217, output_vec_len ); + case 218: return makeRegisterExpression(amdgpu_gfx908::v218, output_vec_len ); + case 219: return makeRegisterExpression(amdgpu_gfx908::v219, output_vec_len ); + case 220: return makeRegisterExpression(amdgpu_gfx908::v220, output_vec_len ); + case 221: return makeRegisterExpression(amdgpu_gfx908::v221, output_vec_len ); + case 222: return makeRegisterExpression(amdgpu_gfx908::v222, output_vec_len ); + case 223: return makeRegisterExpression(amdgpu_gfx908::v223, output_vec_len ); + case 224: return makeRegisterExpression(amdgpu_gfx908::v224, output_vec_len ); + case 225: return makeRegisterExpression(amdgpu_gfx908::v225, output_vec_len ); + case 226: return makeRegisterExpression(amdgpu_gfx908::v226, output_vec_len ); + case 227: return makeRegisterExpression(amdgpu_gfx908::v227, output_vec_len ); + case 228: return makeRegisterExpression(amdgpu_gfx908::v228, output_vec_len ); + case 229: return makeRegisterExpression(amdgpu_gfx908::v229, output_vec_len ); + case 230: return makeRegisterExpression(amdgpu_gfx908::v230, output_vec_len ); + case 231: return makeRegisterExpression(amdgpu_gfx908::v231, output_vec_len ); + case 232: return makeRegisterExpression(amdgpu_gfx908::v232, output_vec_len ); + case 233: return makeRegisterExpression(amdgpu_gfx908::v233, output_vec_len ); + case 234: return makeRegisterExpression(amdgpu_gfx908::v234, output_vec_len ); + case 235: return makeRegisterExpression(amdgpu_gfx908::v235, output_vec_len ); + case 236: return makeRegisterExpression(amdgpu_gfx908::v236, output_vec_len ); + case 237: return makeRegisterExpression(amdgpu_gfx908::v237, output_vec_len ); + case 238: return makeRegisterExpression(amdgpu_gfx908::v238, output_vec_len ); + case 239: return makeRegisterExpression(amdgpu_gfx908::v239, output_vec_len ); + case 240: return makeRegisterExpression(amdgpu_gfx908::v240, output_vec_len ); + case 241: return makeRegisterExpression(amdgpu_gfx908::v241, output_vec_len ); + case 242: return makeRegisterExpression(amdgpu_gfx908::v242, output_vec_len ); + case 243: return makeRegisterExpression(amdgpu_gfx908::v243, output_vec_len ); + case 244: return makeRegisterExpression(amdgpu_gfx908::v244, output_vec_len ); + case 245: return makeRegisterExpression(amdgpu_gfx908::v245, output_vec_len ); + case 246: return makeRegisterExpression(amdgpu_gfx908::v246, output_vec_len ); + case 247: return makeRegisterExpression(amdgpu_gfx908::v247, output_vec_len ); + case 248: return makeRegisterExpression(amdgpu_gfx908::v248, output_vec_len ); + case 249: return makeRegisterExpression(amdgpu_gfx908::v249, output_vec_len ); + case 250: return makeRegisterExpression(amdgpu_gfx908::v250, output_vec_len ); + case 251: return makeRegisterExpression(amdgpu_gfx908::v251, output_vec_len ); + case 252: return makeRegisterExpression(amdgpu_gfx908::v252, output_vec_len ); + case 253: return makeRegisterExpression(amdgpu_gfx908::v253, output_vec_len ); + case 254: return makeRegisterExpression(amdgpu_gfx908::v254, output_vec_len ); + case 255: return makeRegisterExpression(amdgpu_gfx908::v255, output_vec_len ); + default: return makeRegisterExpression(amdgpu_gfx908::invalid); + } + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_VGPR_OR_LDS(uint64_t input, uint32_t output_vec_len) + { + switch (input) { + case 254: return makeRegisterExpression(amdgpu_gfx908::src_lds_direct, output_vec_len ); + case 256: return makeRegisterExpression(amdgpu_gfx908::v0, output_vec_len ); + case 257: return makeRegisterExpression(amdgpu_gfx908::v1, output_vec_len ); + case 258: return makeRegisterExpression(amdgpu_gfx908::v2, output_vec_len ); + case 259: return makeRegisterExpression(amdgpu_gfx908::v3, output_vec_len ); + case 260: return makeRegisterExpression(amdgpu_gfx908::v4, output_vec_len ); + case 261: return makeRegisterExpression(amdgpu_gfx908::v5, output_vec_len ); + case 262: return makeRegisterExpression(amdgpu_gfx908::v6, output_vec_len ); + case 263: return makeRegisterExpression(amdgpu_gfx908::v7, output_vec_len ); + case 264: return makeRegisterExpression(amdgpu_gfx908::v8, output_vec_len ); + case 265: return makeRegisterExpression(amdgpu_gfx908::v9, output_vec_len ); + case 266: return makeRegisterExpression(amdgpu_gfx908::v10, output_vec_len ); + case 267: return makeRegisterExpression(amdgpu_gfx908::v11, output_vec_len ); + case 268: return makeRegisterExpression(amdgpu_gfx908::v12, output_vec_len ); + case 269: return makeRegisterExpression(amdgpu_gfx908::v13, output_vec_len ); + case 270: return makeRegisterExpression(amdgpu_gfx908::v14, output_vec_len ); + case 271: return makeRegisterExpression(amdgpu_gfx908::v15, output_vec_len ); + case 272: return makeRegisterExpression(amdgpu_gfx908::v16, output_vec_len ); + case 273: return makeRegisterExpression(amdgpu_gfx908::v17, output_vec_len ); + case 274: return makeRegisterExpression(amdgpu_gfx908::v18, output_vec_len ); + case 275: return makeRegisterExpression(amdgpu_gfx908::v19, output_vec_len ); + case 276: return makeRegisterExpression(amdgpu_gfx908::v20, output_vec_len ); + case 277: return makeRegisterExpression(amdgpu_gfx908::v21, output_vec_len ); + case 278: return makeRegisterExpression(amdgpu_gfx908::v22, output_vec_len ); + case 279: return makeRegisterExpression(amdgpu_gfx908::v23, output_vec_len ); + case 280: return makeRegisterExpression(amdgpu_gfx908::v24, output_vec_len ); + case 281: return makeRegisterExpression(amdgpu_gfx908::v25, output_vec_len ); + case 282: return makeRegisterExpression(amdgpu_gfx908::v26, output_vec_len ); + case 283: return makeRegisterExpression(amdgpu_gfx908::v27, output_vec_len ); + case 284: return makeRegisterExpression(amdgpu_gfx908::v28, output_vec_len ); + case 285: return makeRegisterExpression(amdgpu_gfx908::v29, output_vec_len ); + case 286: return makeRegisterExpression(amdgpu_gfx908::v30, output_vec_len ); + case 287: return makeRegisterExpression(amdgpu_gfx908::v31, output_vec_len ); + case 288: return makeRegisterExpression(amdgpu_gfx908::v32, output_vec_len ); + case 289: return makeRegisterExpression(amdgpu_gfx908::v33, output_vec_len ); + case 290: return makeRegisterExpression(amdgpu_gfx908::v34, output_vec_len ); + case 291: return makeRegisterExpression(amdgpu_gfx908::v35, output_vec_len ); + case 292: return makeRegisterExpression(amdgpu_gfx908::v36, output_vec_len ); + case 293: return makeRegisterExpression(amdgpu_gfx908::v37, output_vec_len ); + case 294: return makeRegisterExpression(amdgpu_gfx908::v38, output_vec_len ); + case 295: return makeRegisterExpression(amdgpu_gfx908::v39, output_vec_len ); + case 296: return makeRegisterExpression(amdgpu_gfx908::v40, output_vec_len ); + case 297: return makeRegisterExpression(amdgpu_gfx908::v41, output_vec_len ); + case 298: return makeRegisterExpression(amdgpu_gfx908::v42, output_vec_len ); + case 299: return makeRegisterExpression(amdgpu_gfx908::v43, output_vec_len ); + case 300: return makeRegisterExpression(amdgpu_gfx908::v44, output_vec_len ); + case 301: return makeRegisterExpression(amdgpu_gfx908::v45, output_vec_len ); + case 302: return makeRegisterExpression(amdgpu_gfx908::v46, output_vec_len ); + case 303: return makeRegisterExpression(amdgpu_gfx908::v47, output_vec_len ); + case 304: return makeRegisterExpression(amdgpu_gfx908::v48, output_vec_len ); + case 305: return makeRegisterExpression(amdgpu_gfx908::v49, output_vec_len ); + case 306: return makeRegisterExpression(amdgpu_gfx908::v50, output_vec_len ); + case 307: return makeRegisterExpression(amdgpu_gfx908::v51, output_vec_len ); + case 308: return makeRegisterExpression(amdgpu_gfx908::v52, output_vec_len ); + case 309: return makeRegisterExpression(amdgpu_gfx908::v53, output_vec_len ); + case 310: return makeRegisterExpression(amdgpu_gfx908::v54, output_vec_len ); + case 311: return makeRegisterExpression(amdgpu_gfx908::v55, output_vec_len ); + case 312: return makeRegisterExpression(amdgpu_gfx908::v56, output_vec_len ); + case 313: return makeRegisterExpression(amdgpu_gfx908::v57, output_vec_len ); + case 314: return makeRegisterExpression(amdgpu_gfx908::v58, output_vec_len ); + case 315: return makeRegisterExpression(amdgpu_gfx908::v59, output_vec_len ); + case 316: return makeRegisterExpression(amdgpu_gfx908::v60, output_vec_len ); + case 317: return makeRegisterExpression(amdgpu_gfx908::v61, output_vec_len ); + case 318: return makeRegisterExpression(amdgpu_gfx908::v62, output_vec_len ); + case 319: return makeRegisterExpression(amdgpu_gfx908::v63, output_vec_len ); + case 320: return makeRegisterExpression(amdgpu_gfx908::v64, output_vec_len ); + case 321: return makeRegisterExpression(amdgpu_gfx908::v65, output_vec_len ); + case 322: return makeRegisterExpression(amdgpu_gfx908::v66, output_vec_len ); + case 323: return makeRegisterExpression(amdgpu_gfx908::v67, output_vec_len ); + case 324: return makeRegisterExpression(amdgpu_gfx908::v68, output_vec_len ); + case 325: return makeRegisterExpression(amdgpu_gfx908::v69, output_vec_len ); + case 326: return makeRegisterExpression(amdgpu_gfx908::v70, output_vec_len ); + case 327: return makeRegisterExpression(amdgpu_gfx908::v71, output_vec_len ); + case 328: return makeRegisterExpression(amdgpu_gfx908::v72, output_vec_len ); + case 329: return makeRegisterExpression(amdgpu_gfx908::v73, output_vec_len ); + case 330: return makeRegisterExpression(amdgpu_gfx908::v74, output_vec_len ); + case 331: return makeRegisterExpression(amdgpu_gfx908::v75, output_vec_len ); + case 332: return makeRegisterExpression(amdgpu_gfx908::v76, output_vec_len ); + case 333: return makeRegisterExpression(amdgpu_gfx908::v77, output_vec_len ); + case 334: return makeRegisterExpression(amdgpu_gfx908::v78, output_vec_len ); + case 335: return makeRegisterExpression(amdgpu_gfx908::v79, output_vec_len ); + case 336: return makeRegisterExpression(amdgpu_gfx908::v80, output_vec_len ); + case 337: return makeRegisterExpression(amdgpu_gfx908::v81, output_vec_len ); + case 338: return makeRegisterExpression(amdgpu_gfx908::v82, output_vec_len ); + case 339: return makeRegisterExpression(amdgpu_gfx908::v83, output_vec_len ); + case 340: return makeRegisterExpression(amdgpu_gfx908::v84, output_vec_len ); + case 341: return makeRegisterExpression(amdgpu_gfx908::v85, output_vec_len ); + case 342: return makeRegisterExpression(amdgpu_gfx908::v86, output_vec_len ); + case 343: return makeRegisterExpression(amdgpu_gfx908::v87, output_vec_len ); + case 344: return makeRegisterExpression(amdgpu_gfx908::v88, output_vec_len ); + case 345: return makeRegisterExpression(amdgpu_gfx908::v89, output_vec_len ); + case 346: return makeRegisterExpression(amdgpu_gfx908::v90, output_vec_len ); + case 347: return makeRegisterExpression(amdgpu_gfx908::v91, output_vec_len ); + case 348: return makeRegisterExpression(amdgpu_gfx908::v92, output_vec_len ); + case 349: return makeRegisterExpression(amdgpu_gfx908::v93, output_vec_len ); + case 350: return makeRegisterExpression(amdgpu_gfx908::v94, output_vec_len ); + case 351: return makeRegisterExpression(amdgpu_gfx908::v95, output_vec_len ); + case 352: return makeRegisterExpression(amdgpu_gfx908::v96, output_vec_len ); + case 353: return makeRegisterExpression(amdgpu_gfx908::v97, output_vec_len ); + case 354: return makeRegisterExpression(amdgpu_gfx908::v98, output_vec_len ); + case 355: return makeRegisterExpression(amdgpu_gfx908::v99, output_vec_len ); + case 356: return makeRegisterExpression(amdgpu_gfx908::v100, output_vec_len ); + case 357: return makeRegisterExpression(amdgpu_gfx908::v101, output_vec_len ); + case 358: return makeRegisterExpression(amdgpu_gfx908::v102, output_vec_len ); + case 359: return makeRegisterExpression(amdgpu_gfx908::v103, output_vec_len ); + case 360: return makeRegisterExpression(amdgpu_gfx908::v104, output_vec_len ); + case 361: return makeRegisterExpression(amdgpu_gfx908::v105, output_vec_len ); + case 362: return makeRegisterExpression(amdgpu_gfx908::v106, output_vec_len ); + case 363: return makeRegisterExpression(amdgpu_gfx908::v107, output_vec_len ); + case 364: return makeRegisterExpression(amdgpu_gfx908::v108, output_vec_len ); + case 365: return makeRegisterExpression(amdgpu_gfx908::v109, output_vec_len ); + case 366: return makeRegisterExpression(amdgpu_gfx908::v110, output_vec_len ); + case 367: return makeRegisterExpression(amdgpu_gfx908::v111, output_vec_len ); + case 368: return makeRegisterExpression(amdgpu_gfx908::v112, output_vec_len ); + case 369: return makeRegisterExpression(amdgpu_gfx908::v113, output_vec_len ); + case 370: return makeRegisterExpression(amdgpu_gfx908::v114, output_vec_len ); + case 371: return makeRegisterExpression(amdgpu_gfx908::v115, output_vec_len ); + case 372: return makeRegisterExpression(amdgpu_gfx908::v116, output_vec_len ); + case 373: return makeRegisterExpression(amdgpu_gfx908::v117, output_vec_len ); + case 374: return makeRegisterExpression(amdgpu_gfx908::v118, output_vec_len ); + case 375: return makeRegisterExpression(amdgpu_gfx908::v119, output_vec_len ); + case 376: return makeRegisterExpression(amdgpu_gfx908::v120, output_vec_len ); + case 377: return makeRegisterExpression(amdgpu_gfx908::v121, output_vec_len ); + case 378: return makeRegisterExpression(amdgpu_gfx908::v122, output_vec_len ); + case 379: return makeRegisterExpression(amdgpu_gfx908::v123, output_vec_len ); + case 380: return makeRegisterExpression(amdgpu_gfx908::v124, output_vec_len ); + case 381: return makeRegisterExpression(amdgpu_gfx908::v125, output_vec_len ); + case 382: return makeRegisterExpression(amdgpu_gfx908::v126, output_vec_len ); + case 383: return makeRegisterExpression(amdgpu_gfx908::v127, output_vec_len ); + case 384: return makeRegisterExpression(amdgpu_gfx908::v128, output_vec_len ); + case 385: return makeRegisterExpression(amdgpu_gfx908::v129, output_vec_len ); + case 386: return makeRegisterExpression(amdgpu_gfx908::v130, output_vec_len ); + case 387: return makeRegisterExpression(amdgpu_gfx908::v131, output_vec_len ); + case 388: return makeRegisterExpression(amdgpu_gfx908::v132, output_vec_len ); + case 389: return makeRegisterExpression(amdgpu_gfx908::v133, output_vec_len ); + case 390: return makeRegisterExpression(amdgpu_gfx908::v134, output_vec_len ); + case 391: return makeRegisterExpression(amdgpu_gfx908::v135, output_vec_len ); + case 392: return makeRegisterExpression(amdgpu_gfx908::v136, output_vec_len ); + case 393: return makeRegisterExpression(amdgpu_gfx908::v137, output_vec_len ); + case 394: return makeRegisterExpression(amdgpu_gfx908::v138, output_vec_len ); + case 395: return makeRegisterExpression(amdgpu_gfx908::v139, output_vec_len ); + case 396: return makeRegisterExpression(amdgpu_gfx908::v140, output_vec_len ); + case 397: return makeRegisterExpression(amdgpu_gfx908::v141, output_vec_len ); + case 398: return makeRegisterExpression(amdgpu_gfx908::v142, output_vec_len ); + case 399: return makeRegisterExpression(amdgpu_gfx908::v143, output_vec_len ); + case 400: return makeRegisterExpression(amdgpu_gfx908::v144, output_vec_len ); + case 401: return makeRegisterExpression(amdgpu_gfx908::v145, output_vec_len ); + case 402: return makeRegisterExpression(amdgpu_gfx908::v146, output_vec_len ); + case 403: return makeRegisterExpression(amdgpu_gfx908::v147, output_vec_len ); + case 404: return makeRegisterExpression(amdgpu_gfx908::v148, output_vec_len ); + case 405: return makeRegisterExpression(amdgpu_gfx908::v149, output_vec_len ); + case 406: return makeRegisterExpression(amdgpu_gfx908::v150, output_vec_len ); + case 407: return makeRegisterExpression(amdgpu_gfx908::v151, output_vec_len ); + case 408: return makeRegisterExpression(amdgpu_gfx908::v152, output_vec_len ); + case 409: return makeRegisterExpression(amdgpu_gfx908::v153, output_vec_len ); + case 410: return makeRegisterExpression(amdgpu_gfx908::v154, output_vec_len ); + case 411: return makeRegisterExpression(amdgpu_gfx908::v155, output_vec_len ); + case 412: return makeRegisterExpression(amdgpu_gfx908::v156, output_vec_len ); + case 413: return makeRegisterExpression(amdgpu_gfx908::v157, output_vec_len ); + case 414: return makeRegisterExpression(amdgpu_gfx908::v158, output_vec_len ); + case 415: return makeRegisterExpression(amdgpu_gfx908::v159, output_vec_len ); + case 416: return makeRegisterExpression(amdgpu_gfx908::v160, output_vec_len ); + case 417: return makeRegisterExpression(amdgpu_gfx908::v161, output_vec_len ); + case 418: return makeRegisterExpression(amdgpu_gfx908::v162, output_vec_len ); + case 419: return makeRegisterExpression(amdgpu_gfx908::v163, output_vec_len ); + case 420: return makeRegisterExpression(amdgpu_gfx908::v164, output_vec_len ); + case 421: return makeRegisterExpression(amdgpu_gfx908::v165, output_vec_len ); + case 422: return makeRegisterExpression(amdgpu_gfx908::v166, output_vec_len ); + case 423: return makeRegisterExpression(amdgpu_gfx908::v167, output_vec_len ); + case 424: return makeRegisterExpression(amdgpu_gfx908::v168, output_vec_len ); + case 425: return makeRegisterExpression(amdgpu_gfx908::v169, output_vec_len ); + case 426: return makeRegisterExpression(amdgpu_gfx908::v170, output_vec_len ); + case 427: return makeRegisterExpression(amdgpu_gfx908::v171, output_vec_len ); + case 428: return makeRegisterExpression(amdgpu_gfx908::v172, output_vec_len ); + case 429: return makeRegisterExpression(amdgpu_gfx908::v173, output_vec_len ); + case 430: return makeRegisterExpression(amdgpu_gfx908::v174, output_vec_len ); + case 431: return makeRegisterExpression(amdgpu_gfx908::v175, output_vec_len ); + case 432: return makeRegisterExpression(amdgpu_gfx908::v176, output_vec_len ); + case 433: return makeRegisterExpression(amdgpu_gfx908::v177, output_vec_len ); + case 434: return makeRegisterExpression(amdgpu_gfx908::v178, output_vec_len ); + case 435: return makeRegisterExpression(amdgpu_gfx908::v179, output_vec_len ); + case 436: return makeRegisterExpression(amdgpu_gfx908::v180, output_vec_len ); + case 437: return makeRegisterExpression(amdgpu_gfx908::v181, output_vec_len ); + case 438: return makeRegisterExpression(amdgpu_gfx908::v182, output_vec_len ); + case 439: return makeRegisterExpression(amdgpu_gfx908::v183, output_vec_len ); + case 440: return makeRegisterExpression(amdgpu_gfx908::v184, output_vec_len ); + case 441: return makeRegisterExpression(amdgpu_gfx908::v185, output_vec_len ); + case 442: return makeRegisterExpression(amdgpu_gfx908::v186, output_vec_len ); + case 443: return makeRegisterExpression(amdgpu_gfx908::v187, output_vec_len ); + case 444: return makeRegisterExpression(amdgpu_gfx908::v188, output_vec_len ); + case 445: return makeRegisterExpression(amdgpu_gfx908::v189, output_vec_len ); + case 446: return makeRegisterExpression(amdgpu_gfx908::v190, output_vec_len ); + case 447: return makeRegisterExpression(amdgpu_gfx908::v191, output_vec_len ); + case 448: return makeRegisterExpression(amdgpu_gfx908::v192, output_vec_len ); + case 449: return makeRegisterExpression(amdgpu_gfx908::v193, output_vec_len ); + case 450: return makeRegisterExpression(amdgpu_gfx908::v194, output_vec_len ); + case 451: return makeRegisterExpression(amdgpu_gfx908::v195, output_vec_len ); + case 452: return makeRegisterExpression(amdgpu_gfx908::v196, output_vec_len ); + case 453: return makeRegisterExpression(amdgpu_gfx908::v197, output_vec_len ); + case 454: return makeRegisterExpression(amdgpu_gfx908::v198, output_vec_len ); + case 455: return makeRegisterExpression(amdgpu_gfx908::v199, output_vec_len ); + case 456: return makeRegisterExpression(amdgpu_gfx908::v200, output_vec_len ); + case 457: return makeRegisterExpression(amdgpu_gfx908::v201, output_vec_len ); + case 458: return makeRegisterExpression(amdgpu_gfx908::v202, output_vec_len ); + case 459: return makeRegisterExpression(amdgpu_gfx908::v203, output_vec_len ); + case 460: return makeRegisterExpression(amdgpu_gfx908::v204, output_vec_len ); + case 461: return makeRegisterExpression(amdgpu_gfx908::v205, output_vec_len ); + case 462: return makeRegisterExpression(amdgpu_gfx908::v206, output_vec_len ); + case 463: return makeRegisterExpression(amdgpu_gfx908::v207, output_vec_len ); + case 464: return makeRegisterExpression(amdgpu_gfx908::v208, output_vec_len ); + case 465: return makeRegisterExpression(amdgpu_gfx908::v209, output_vec_len ); + case 466: return makeRegisterExpression(amdgpu_gfx908::v210, output_vec_len ); + case 467: return makeRegisterExpression(amdgpu_gfx908::v211, output_vec_len ); + case 468: return makeRegisterExpression(amdgpu_gfx908::v212, output_vec_len ); + case 469: return makeRegisterExpression(amdgpu_gfx908::v213, output_vec_len ); + case 470: return makeRegisterExpression(amdgpu_gfx908::v214, output_vec_len ); + case 471: return makeRegisterExpression(amdgpu_gfx908::v215, output_vec_len ); + case 472: return makeRegisterExpression(amdgpu_gfx908::v216, output_vec_len ); + case 473: return makeRegisterExpression(amdgpu_gfx908::v217, output_vec_len ); + case 474: return makeRegisterExpression(amdgpu_gfx908::v218, output_vec_len ); + case 475: return makeRegisterExpression(amdgpu_gfx908::v219, output_vec_len ); + case 476: return makeRegisterExpression(amdgpu_gfx908::v220, output_vec_len ); + case 477: return makeRegisterExpression(amdgpu_gfx908::v221, output_vec_len ); + case 478: return makeRegisterExpression(amdgpu_gfx908::v222, output_vec_len ); + case 479: return makeRegisterExpression(amdgpu_gfx908::v223, output_vec_len ); + case 480: return makeRegisterExpression(amdgpu_gfx908::v224, output_vec_len ); + case 481: return makeRegisterExpression(amdgpu_gfx908::v225, output_vec_len ); + case 482: return makeRegisterExpression(amdgpu_gfx908::v226, output_vec_len ); + case 483: return makeRegisterExpression(amdgpu_gfx908::v227, output_vec_len ); + case 484: return makeRegisterExpression(amdgpu_gfx908::v228, output_vec_len ); + case 485: return makeRegisterExpression(amdgpu_gfx908::v229, output_vec_len ); + case 486: return makeRegisterExpression(amdgpu_gfx908::v230, output_vec_len ); + case 487: return makeRegisterExpression(amdgpu_gfx908::v231, output_vec_len ); + case 488: return makeRegisterExpression(amdgpu_gfx908::v232, output_vec_len ); + case 489: return makeRegisterExpression(amdgpu_gfx908::v233, output_vec_len ); + case 490: return makeRegisterExpression(amdgpu_gfx908::v234, output_vec_len ); + case 491: return makeRegisterExpression(amdgpu_gfx908::v235, output_vec_len ); + case 492: return makeRegisterExpression(amdgpu_gfx908::v236, output_vec_len ); + case 493: return makeRegisterExpression(amdgpu_gfx908::v237, output_vec_len ); + case 494: return makeRegisterExpression(amdgpu_gfx908::v238, output_vec_len ); + case 495: return makeRegisterExpression(amdgpu_gfx908::v239, output_vec_len ); + case 496: return makeRegisterExpression(amdgpu_gfx908::v240, output_vec_len ); + case 497: return makeRegisterExpression(amdgpu_gfx908::v241, output_vec_len ); + case 498: return makeRegisterExpression(amdgpu_gfx908::v242, output_vec_len ); + case 499: return makeRegisterExpression(amdgpu_gfx908::v243, output_vec_len ); + case 500: return makeRegisterExpression(amdgpu_gfx908::v244, output_vec_len ); + case 501: return makeRegisterExpression(amdgpu_gfx908::v245, output_vec_len ); + case 502: return makeRegisterExpression(amdgpu_gfx908::v246, output_vec_len ); + case 503: return makeRegisterExpression(amdgpu_gfx908::v247, output_vec_len ); + case 504: return makeRegisterExpression(amdgpu_gfx908::v248, output_vec_len ); + case 505: return makeRegisterExpression(amdgpu_gfx908::v249, output_vec_len ); + case 506: return makeRegisterExpression(amdgpu_gfx908::v250, output_vec_len ); + case 507: return makeRegisterExpression(amdgpu_gfx908::v251, output_vec_len ); + case 508: return makeRegisterExpression(amdgpu_gfx908::v252, output_vec_len ); + case 509: return makeRegisterExpression(amdgpu_gfx908::v253, output_vec_len ); + case 510: return makeRegisterExpression(amdgpu_gfx908::v254, output_vec_len ); + case 511: return makeRegisterExpression(amdgpu_gfx908::v255, output_vec_len ); + default: return makeRegisterExpression(amdgpu_gfx908::invalid); + } + } + +} +} diff --git a/instructionAPI/src/AMDGPU/gfx908/finalizeOperands.C b/instructionAPI/src/AMDGPU/gfx908/finalizeOperands.C new file mode 100644 index 0000000000..0dc3399b06 --- /dev/null +++ b/instructionAPI/src/AMDGPU/gfx908/finalizeOperands.C @@ -0,0 +1,2339 @@ +#include "registers/AMDGPU/amdgpu_gfx908_regs.h" +#include "InstructionDecoder-amdgpu-gfx908.h" + +namespace Dyninst { +namespace InstructionAPI { + void InstructionDecoder_amdgpu_gfx908::finalizeENC_DSOperands() + { + layout_ENC_DS & layout = insn_layout.ENC_DS; + switch (layout.OP) { + case 0: case 1: case 2: case 3: case 4: // DS_ADD_U32,DS_SUB_U32,DS_RSUB_U32,DS_INC_U32,DS_DEC_U32, + case 5: case 6: case 7: case 8: case 9: // DS_MIN_I32,DS_MAX_I32,DS_MIN_U32,DS_MAX_U32,DS_AND_B32, + case 10: case 11: case 13: case 18: case 19: // DS_OR_B32,DS_XOR_B32,DS_WRITE_B32,DS_MIN_F32,DS_MAX_F32, + case 21: case 30: case 31: case 84: // DS_ADD_F32,DS_WRITE_B8,DS_WRITE_B16,DS_WRITE_B8_D16_HI, + case 85: // DS_WRITE_B16_D16_HI, + appendOPR_VGPR(layout.ADDR,true,false); + appendOPR_VGPR(layout.DATA0,true,false); + appendOPR_DSMEM(0,true,false,1,true); + if (layout.OFFSET0 || layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,(layout.OFFSET1 << 8) + layout.OFFSET0)),true,false,false); + } + break; + case 12: case 16: case 17: // DS_MSKOR_B32,DS_CMPST_B32,DS_CMPST_F32, + appendOPR_VGPR(layout.ADDR,true,false); + appendOPR_VGPR(layout.DATA0,true,false); + appendOPR_VGPR(layout.DATA1,true,false); + appendOPR_DSMEM(0,true,false,1,true); + if (layout.OFFSET0 || layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,(layout.OFFSET1 << 8) + layout.OFFSET0)),true,false,false); + } + break; + case 14: case 15: // DS_WRITE2_B32,DS_WRITE2ST64_B32, + appendOPR_VGPR(layout.ADDR,true,false); + appendOPR_VGPR(layout.DATA0,true,false); + appendOPR_VGPR(layout.DATA1,true,false); + appendOPR_DSMEM(0,true,false,1,true); + if (layout.OFFSET0) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset0"),Result(u8,layout.OFFSET0)),true,false,false); + } + if (layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset1"),Result(u8,layout.OFFSET1)),true,false,false); + } + break; + case 20: // DS_NOP, + if (layout.OFFSET0 || layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,(layout.OFFSET1 << 8) + layout.OFFSET0)),true,false,false); + } + break; + case 29: // DS_WRITE_ADDTID_B32, + appendOPR_VGPR(layout.DATA0,true,false); + appendOPR_DSMEM(0,true,false,1,true); + appendOPR_SDST_M0(124,true,false,1,true); + if (layout.OFFSET0 || layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,(layout.OFFSET1 << 8) + layout.OFFSET0)),true,false,false); + } + break; + case 32: case 33: case 34: case 35: // DS_ADD_RTN_U32,DS_SUB_RTN_U32,DS_RSUB_RTN_U32,DS_INC_RTN_U32, + case 36: case 37: case 38: case 39: // DS_DEC_RTN_U32,DS_MIN_RTN_I32,DS_MAX_RTN_I32,DS_MIN_RTN_U32, + case 40: case 41: case 42: case 43: // DS_MAX_RTN_U32,DS_AND_RTN_B32,DS_OR_RTN_B32,DS_XOR_RTN_B32, + case 45: case 50: case 51: case 53: // DS_WRXCHG_RTN_B32,DS_MIN_RTN_F32,DS_MAX_RTN_F32,DS_ADD_RTN_F32, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_VGPR(layout.ADDR,true,false); + appendOPR_VGPR(layout.DATA0,true,false); + appendOPR_DSMEM(0,true,false,1,true); + if (layout.OFFSET0 || layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,(layout.OFFSET1 << 8) + layout.OFFSET0)),true,false,false); + } + break; + case 44: case 48: case 49: case 52: // DS_MSKOR_RTN_B32,DS_CMPST_RTN_B32,DS_CMPST_RTN_F32,DS_WRAP_RTN_B32, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_VGPR(layout.ADDR,true,false); + appendOPR_VGPR(layout.DATA0,true,false); + appendOPR_VGPR(layout.DATA1,true,false); + appendOPR_DSMEM(0,true,false,1,true); + if (layout.OFFSET0 || layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,(layout.OFFSET1 << 8) + layout.OFFSET0)),true,false,false); + } + break; + case 46: case 47: // DS_WRXCHG2_RTN_B32,DS_WRXCHG2ST64_RTN_B32, + appendOPR_VGPR(layout.VDST,false,true,2); + appendOPR_VGPR(layout.ADDR,true,false); + appendOPR_VGPR(layout.DATA0,true,false); + appendOPR_VGPR(layout.DATA1,true,false); + appendOPR_DSMEM(0,true,false,1,true); + if (layout.OFFSET0 || layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,(layout.OFFSET1 << 8) + layout.OFFSET0)),true,false,false); + } + break; + case 54: case 57: case 58: case 59: case 60: // DS_READ_B32,DS_READ_I8,DS_READ_U8,DS_READ_I16,DS_READ_U16, + case 86: case 87: case 88: case 89: // DS_READ_U8_D16,DS_READ_U8_D16_HI,DS_READ_I8_D16,DS_READ_I8_D16_HI, + case 90: case 91: // DS_READ_U16_D16,DS_READ_U16_D16_HI, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_VGPR(layout.ADDR,true,false); + appendOPR_DSMEM(0,true,false,1,true); + if (layout.OFFSET0 || layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,(layout.OFFSET1 << 8) + layout.OFFSET0)),true,false,false); + } + break; + case 55: case 56: // DS_READ2_B32,DS_READ2ST64_B32, + appendOPR_VGPR(layout.VDST,false,true,2); + appendOPR_VGPR(layout.ADDR,true,false); + appendOPR_DSMEM(0,true,false,1,true); + if (layout.OFFSET0) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset0"),Result(u8,layout.OFFSET0)),true,false,false); + } + if (layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset1"),Result(u8,layout.OFFSET1)),true,false,false); + } + break; + case 61: // DS_SWIZZLE_B32, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_VGPR(layout.ADDR,true,false); + if (layout.OFFSET0 || layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,(layout.OFFSET1 << 8) + layout.OFFSET0)),true,false,false); + } + break; + case 62: case 63: // DS_PERMUTE_B32,DS_BPERMUTE_B32, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_VGPR(layout.ADDR,true,false); + appendOPR_VGPR(layout.DATA0,true,false); + if (layout.OFFSET0 || layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,(layout.OFFSET1 << 8) + layout.OFFSET0)),true,false,false); + } + break; + case 64: case 65: case 66: case 67: case 68: // DS_ADD_U64,DS_SUB_U64,DS_RSUB_U64,DS_INC_U64,DS_DEC_U64, + case 69: case 70: case 71: case 72: case 73: // DS_MIN_I64,DS_MAX_I64,DS_MIN_U64,DS_MAX_U64,DS_AND_B64, + case 74: case 75: case 77: case 82: case 83: // DS_OR_B64,DS_XOR_B64,DS_WRITE_B64,DS_MIN_F64,DS_MAX_F64, + appendOPR_VGPR(layout.ADDR,true,false); + appendOPR_VGPR(layout.DATA0,true,false,2); + appendOPR_DSMEM(0,true,false,1,true); + if (layout.OFFSET0 || layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,(layout.OFFSET1 << 8) + layout.OFFSET0)),true,false,false); + } + break; + case 76: case 80: case 81: // DS_MSKOR_B64,DS_CMPST_B64,DS_CMPST_F64, + appendOPR_VGPR(layout.ADDR,true,false); + appendOPR_VGPR(layout.DATA0,true,false,2); + appendOPR_VGPR(layout.DATA1,true,false,2); + appendOPR_DSMEM(0,true,false,1,true); + if (layout.OFFSET0 || layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,(layout.OFFSET1 << 8) + layout.OFFSET0)),true,false,false); + } + break; + case 78: case 79: // DS_WRITE2_B64,DS_WRITE2ST64_B64, + appendOPR_VGPR(layout.ADDR,true,false); + appendOPR_VGPR(layout.DATA0,true,false,2); + appendOPR_VGPR(layout.DATA1,true,false,2); + appendOPR_DSMEM(0,true,false,1,true); + if (layout.OFFSET0) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset0"),Result(u8,layout.OFFSET0)),true,false,false); + } + if (layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset1"),Result(u8,layout.OFFSET1)),true,false,false); + } + break; + case 96: case 97: case 98: case 99: // DS_ADD_RTN_U64,DS_SUB_RTN_U64,DS_RSUB_RTN_U64,DS_INC_RTN_U64, + case 100: case 101: case 102: case 103: // DS_DEC_RTN_U64,DS_MIN_RTN_I64,DS_MAX_RTN_I64,DS_MIN_RTN_U64, + case 104: case 105: case 106: case 107: // DS_MAX_RTN_U64,DS_AND_RTN_B64,DS_OR_RTN_B64,DS_XOR_RTN_B64, + case 109: case 114: case 115: case 126: // DS_WRXCHG_RTN_B64,DS_MIN_RTN_F64,DS_MAX_RTN_F64,DS_CONDXCHG32_RTN_B64, + appendOPR_VGPR(layout.VDST,false,true,2); + appendOPR_VGPR(layout.ADDR,true,false); + appendOPR_VGPR(layout.DATA0,true,false,2); + appendOPR_DSMEM(0,true,false,1,true); + if (layout.OFFSET0 || layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,(layout.OFFSET1 << 8) + layout.OFFSET0)),true,false,false); + } + break; + case 108: case 112: case 113: // DS_MSKOR_RTN_B64,DS_CMPST_RTN_B64,DS_CMPST_RTN_F64, + appendOPR_VGPR(layout.VDST,false,true,2); + appendOPR_VGPR(layout.ADDR,true,false); + appendOPR_VGPR(layout.DATA0,true,false,2); + appendOPR_VGPR(layout.DATA1,true,false,2); + appendOPR_DSMEM(0,true,false,1,true); + if (layout.OFFSET0 || layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,(layout.OFFSET1 << 8) + layout.OFFSET0)),true,false,false); + } + break; + case 110: case 111: // DS_WRXCHG2_RTN_B64,DS_WRXCHG2ST64_RTN_B64, + appendOPR_VGPR(layout.VDST,false,true,4); + appendOPR_VGPR(layout.ADDR,true,false); + appendOPR_VGPR(layout.DATA0,true,false,2); + appendOPR_VGPR(layout.DATA1,true,false,2); + appendOPR_DSMEM(0,true,false,1,true); + if (layout.OFFSET0 || layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,(layout.OFFSET1 << 8) + layout.OFFSET0)),true,false,false); + } + break; + case 118: // DS_READ_B64, + appendOPR_VGPR(layout.VDST,false,true,2); + appendOPR_VGPR(layout.ADDR,true,false); + appendOPR_DSMEM(0,true,false,1,true); + if (layout.OFFSET0 || layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,(layout.OFFSET1 << 8) + layout.OFFSET0)),true,false,false); + } + break; + case 119: case 120: // DS_READ2_B64,DS_READ2ST64_B64, + appendOPR_VGPR(layout.VDST,false,true,4); + appendOPR_VGPR(layout.ADDR,true,false); + appendOPR_DSMEM(0,true,false,1,true); + if (layout.OFFSET0) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset0"),Result(u8,layout.OFFSET0)),true,false,false); + } + if (layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset1"),Result(u8,layout.OFFSET1)),true,false,false); + } + break; + case 128: case 129: case 130: case 131: // DS_ADD_SRC2_U32,DS_SUB_SRC2_U32,DS_RSUB_SRC2_U32,DS_INC_SRC2_U32, + case 132: case 133: case 134: case 135: // DS_DEC_SRC2_U32,DS_MIN_SRC2_I32,DS_MAX_SRC2_I32,DS_MIN_SRC2_U32, + case 136: case 137: case 138: case 139: // DS_MAX_SRC2_U32,DS_AND_SRC2_B32,DS_OR_SRC2_B32,DS_XOR_SRC2_B32, + case 141: case 146: case 147: case 149: // DS_WRITE_SRC2_B32,DS_MIN_SRC2_F32,DS_MAX_SRC2_F32,DS_ADD_SRC2_F32, + case 192: case 193: case 194: case 195: // DS_ADD_SRC2_U64,DS_SUB_SRC2_U64,DS_RSUB_SRC2_U64,DS_INC_SRC2_U64, + case 196: case 197: case 198: case 199: // DS_DEC_SRC2_U64,DS_MIN_SRC2_I64,DS_MAX_SRC2_I64,DS_MIN_SRC2_U64, + case 200: case 201: case 202: case 203: // DS_MAX_SRC2_U64,DS_AND_SRC2_B64,DS_OR_SRC2_B64,DS_XOR_SRC2_B64, + case 205: case 210: case 211: // DS_WRITE_SRC2_B64,DS_MIN_SRC2_F64,DS_MAX_SRC2_F64, + appendOPR_VGPR(layout.ADDR,true,false); + appendOPR_DSMEM(0,true,false,1,true); + if (layout.OFFSET0 || layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,(layout.OFFSET1 << 8) + layout.OFFSET0)),true,false,false); + } + break; + case 152: case 154: case 156: // DS_GWS_SEMA_RELEASE_ALL,DS_GWS_SEMA_V,DS_GWS_SEMA_P, + appendOPR_SDST_M0(124,true,false,1,true); + if (layout.OFFSET0 || layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,(layout.OFFSET1 << 8) + layout.OFFSET0)),true,false,false); + } + break; + case 153: case 155: case 157: // DS_GWS_INIT,DS_GWS_SEMA_BR,DS_GWS_BARRIER, + appendOPR_VGPR(layout.DATA0,true,false); + appendOPR_SDST_M0(124,true,false,1,true); + if (layout.OFFSET0 || layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,(layout.OFFSET1 << 8) + layout.OFFSET0)),true,false,false); + } + break; + case 182: case 189: case 190: // DS_READ_ADDTID_B32,DS_CONSUME,DS_APPEND, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_DSMEM(0,true,false,1,true); + appendOPR_SDST_M0(124,true,false,1,true); + if (layout.OFFSET0 || layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,(layout.OFFSET1 << 8) + layout.OFFSET0)),true,false,false); + } + break; + case 191: // DS_ORDERED_COUNT, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_VGPR(layout.ADDR,true,false); + appendOPR_SDST_M0(124,true,false,1,true); + if (layout.OFFSET0 || layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,(layout.OFFSET1 << 8) + layout.OFFSET0)),true,false,false); + } + break; + case 222: // DS_WRITE_B96, + appendOPR_VGPR(layout.ADDR,true,false); + appendOPR_VGPR(layout.DATA0,true,false,3); + appendOPR_DSMEM(0,true,false,1,true); + if (layout.OFFSET0 || layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,(layout.OFFSET1 << 8) + layout.OFFSET0)),true,false,false); + } + break; + case 223: // DS_WRITE_B128, + appendOPR_VGPR(layout.ADDR,true,false); + appendOPR_VGPR(layout.DATA0,true,false,4); + appendOPR_DSMEM(0,true,false,1,true); + if (layout.OFFSET0 || layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,(layout.OFFSET1 << 8) + layout.OFFSET0)),true,false,false); + } + break; + case 254: // DS_READ_B96, + appendOPR_VGPR(layout.VDST,false,true,3); + appendOPR_VGPR(layout.ADDR,true,false); + appendOPR_DSMEM(0,true,false,1,true); + if (layout.OFFSET0 || layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,(layout.OFFSET1 << 8) + layout.OFFSET0)),true,false,false); + } + break; + case 255: // DS_READ_B128, + appendOPR_VGPR(layout.VDST,false,true,4); + appendOPR_VGPR(layout.ADDR,true,false); + appendOPR_DSMEM(0,true,false,1,true); + if (layout.OFFSET0 || layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,(layout.OFFSET1 << 8) + layout.OFFSET0)),true,false,false); + } + break; + } + } + + void InstructionDecoder_amdgpu_gfx908::finalizeENC_FLATOperands() + { + layout_ENC_FLAT & layout = insn_layout.ENC_FLAT; + switch (layout.OP) { + case 16: case 17: case 18: case 19: // FLAT_LOAD_UBYTE,FLAT_LOAD_SBYTE,FLAT_LOAD_USHORT,FLAT_LOAD_SSHORT, + case 20: case 32: case 33: // FLAT_LOAD_DWORD,FLAT_LOAD_UBYTE_D16,FLAT_LOAD_UBYTE_D16_HI, + case 34: case 35: case 36: // FLAT_LOAD_SBYTE_D16,FLAT_LOAD_SBYTE_D16_HI,FLAT_LOAD_SHORT_D16, + case 37: // FLAT_LOAD_SHORT_D16_HI, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_VGPR(layout.ADDR,true,false,2); + appendOPR_FLAT_SCRATCH(0,true,false,1,true); + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); + break; + case 21: // FLAT_LOAD_DWORDX2, + appendOPR_VGPR(layout.VDST,false,true,2); + appendOPR_VGPR(layout.ADDR,true,false,2); + appendOPR_FLAT_SCRATCH(0,true,false,1,true); + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); + break; + case 22: // FLAT_LOAD_DWORDX3, + appendOPR_VGPR(layout.VDST,false,true,3); + appendOPR_VGPR(layout.ADDR,true,false,2); + appendOPR_FLAT_SCRATCH(0,true,false,1,true); + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); + break; + case 23: // FLAT_LOAD_DWORDX4, + appendOPR_VGPR(layout.VDST,false,true,4); + appendOPR_VGPR(layout.ADDR,true,false,2); + appendOPR_FLAT_SCRATCH(0,true,false,1,true); + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); + break; + case 24: case 25: case 26: // FLAT_STORE_BYTE,FLAT_STORE_BYTE_D16_HI,FLAT_STORE_SHORT, + case 27: case 28: // FLAT_STORE_SHORT_D16_HI,FLAT_STORE_DWORD, + appendOPR_VGPR(layout.ADDR,true,false,2); + appendOPR_VGPR(layout.DATA,true,false); + appendOPR_FLAT_SCRATCH(0,true,false,1,true); + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); + break; + case 29: // FLAT_STORE_DWORDX2, + appendOPR_VGPR(layout.ADDR,true,false,2); + appendOPR_VGPR(layout.DATA,true,false,2); + appendOPR_FLAT_SCRATCH(0,true,false,1,true); + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); + break; + case 30: // FLAT_STORE_DWORDX3, + appendOPR_VGPR(layout.ADDR,true,false,2); + appendOPR_VGPR(layout.DATA,true,false,3); + appendOPR_FLAT_SCRATCH(0,true,false,1,true); + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); + break; + case 31: // FLAT_STORE_DWORDX4, + appendOPR_VGPR(layout.ADDR,true,false,2); + appendOPR_VGPR(layout.DATA,true,false,4); + appendOPR_FLAT_SCRATCH(0,true,false,1,true); + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); + break; + case 64: case 66: case 67: case 68: // FLAT_ATOMIC_SWAP,FLAT_ATOMIC_ADD,FLAT_ATOMIC_SUB,FLAT_ATOMIC_SMIN, + case 69: case 70: case 71: case 72: // FLAT_ATOMIC_UMIN,FLAT_ATOMIC_SMAX,FLAT_ATOMIC_UMAX,FLAT_ATOMIC_AND, + case 73: case 74: case 75: case 76: // FLAT_ATOMIC_OR,FLAT_ATOMIC_XOR,FLAT_ATOMIC_INC,FLAT_ATOMIC_DEC, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_VGPR(layout.ADDR,true,false,2); + appendOPR_VGPR(layout.DATA,true,false); + appendOPR_FLAT_SCRATCH(0,true,false,1,true); + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); + break; + case 65: case 96: case 98: case 99: // FLAT_ATOMIC_CMPSWAP,FLAT_ATOMIC_SWAP_X2,FLAT_ATOMIC_ADD_X2,FLAT_ATOMIC_SUB_X2, + case 100: case 101: case 102: // FLAT_ATOMIC_SMIN_X2,FLAT_ATOMIC_UMIN_X2,FLAT_ATOMIC_SMAX_X2, + case 103: case 104: case 105: // FLAT_ATOMIC_UMAX_X2,FLAT_ATOMIC_AND_X2,FLAT_ATOMIC_OR_X2, + case 106: case 107: case 108: // FLAT_ATOMIC_XOR_X2,FLAT_ATOMIC_INC_X2,FLAT_ATOMIC_DEC_X2, + appendOPR_VGPR(layout.VDST,false,true,2); + appendOPR_VGPR(layout.ADDR,true,false,2); + appendOPR_VGPR(layout.DATA,true,false,2); + appendOPR_FLAT_SCRATCH(0,true,false,1,true); + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); + break; + case 97: // FLAT_ATOMIC_CMPSWAP_X2, + appendOPR_VGPR(layout.VDST,false,true,4); + appendOPR_VGPR(layout.ADDR,true,false,2); + appendOPR_VGPR(layout.DATA,true,false,4); + appendOPR_FLAT_SCRATCH(0,true,false,1,true); + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); + break; + } + } + + void InstructionDecoder_amdgpu_gfx908::finalizeENC_FLAT_GLBLOperands() + { + layout_ENC_FLAT_GLBL & layout = insn_layout.ENC_FLAT_GLBL; + switch (layout.OP) { + case 16: case 17: case 18: case 19: // GLOBAL_LOAD_UBYTE,GLOBAL_LOAD_SBYTE,GLOBAL_LOAD_USHORT,GLOBAL_LOAD_SSHORT, + case 20: case 32: case 33: // GLOBAL_LOAD_DWORD,GLOBAL_LOAD_UBYTE_D16,GLOBAL_LOAD_UBYTE_D16_HI, + case 34: case 35: case 36: // GLOBAL_LOAD_SBYTE_D16,GLOBAL_LOAD_SBYTE_D16_HI,GLOBAL_LOAD_SHORT_D16, + case 37: // GLOBAL_LOAD_SHORT_D16_HI, + appendOPR_VGPR(layout.VDST,false,true); + if (layout.SADDR == 0x7f) { + appendOPR_VGPR(layout.ADDR,true,false,2); + } else { + appendOPR_VGPR(layout.ADDR,true,false); + } + if (layout.SADDR != 0x7f) { + appendOPR_SREG(layout.SADDR,true,false,2); + } + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); + break; + case 21: // GLOBAL_LOAD_DWORDX2, + appendOPR_VGPR(layout.VDST,false,true,2); + if (layout.SADDR == 0x7f) { + appendOPR_VGPR(layout.ADDR,true,false,2); + } else { + appendOPR_VGPR(layout.ADDR,true,false); + } + if (layout.SADDR != 0x7f) { + appendOPR_SREG(layout.SADDR,true,false,2); + } + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); + break; + case 22: // GLOBAL_LOAD_DWORDX3, + appendOPR_VGPR(layout.VDST,false,true,3); + if (layout.SADDR == 0x7f) { + appendOPR_VGPR(layout.ADDR,true,false,2); + } else { + appendOPR_VGPR(layout.ADDR,true,false); + } + if (layout.SADDR != 0x7f) { + appendOPR_SREG(layout.SADDR,true,false,2); + } + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); + break; + case 23: // GLOBAL_LOAD_DWORDX4, + appendOPR_VGPR(layout.VDST,false,true,4); + if (layout.SADDR == 0x7f) { + appendOPR_VGPR(layout.ADDR,true,false,2); + } else { + appendOPR_VGPR(layout.ADDR,true,false); + } + if (layout.SADDR != 0x7f) { + appendOPR_SREG(layout.SADDR,true,false,2); + } + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); + break; + case 24: case 25: case 26: // GLOBAL_STORE_BYTE,GLOBAL_STORE_BYTE_D16_HI,GLOBAL_STORE_SHORT, + case 27: case 28: // GLOBAL_STORE_SHORT_D16_HI,GLOBAL_STORE_DWORD, + if (layout.SADDR == 0x7f) { + appendOPR_VGPR(layout.ADDR,true,false,2); + } else { + appendOPR_VGPR(layout.ADDR,true,false); + } + appendOPR_VGPR(layout.DATA,true,false); + if (layout.SADDR != 0x7f) { + appendOPR_SREG(layout.SADDR,true,false,2); + } + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); + break; + case 29: // GLOBAL_STORE_DWORDX2, + if (layout.SADDR == 0x7f) { + appendOPR_VGPR(layout.ADDR,true,false,2); + } else { + appendOPR_VGPR(layout.ADDR,true,false); + } + appendOPR_VGPR(layout.DATA,true,false,2); + if (layout.SADDR != 0x7f) { + appendOPR_SREG(layout.SADDR,true,false,2); + } + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); + break; + case 30: // GLOBAL_STORE_DWORDX3, + if (layout.SADDR == 0x7f) { + appendOPR_VGPR(layout.ADDR,true,false,2); + } else { + appendOPR_VGPR(layout.ADDR,true,false); + } + appendOPR_VGPR(layout.DATA,true,false,3); + if (layout.SADDR != 0x7f) { + appendOPR_SREG(layout.SADDR,true,false,2); + } + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); + break; + case 31: // GLOBAL_STORE_DWORDX4, + if (layout.SADDR == 0x7f) { + appendOPR_VGPR(layout.ADDR,true,false,2); + } else { + appendOPR_VGPR(layout.ADDR,true,false); + } + appendOPR_VGPR(layout.DATA,true,false,4); + if (layout.SADDR != 0x7f) { + appendOPR_SREG(layout.SADDR,true,false,2); + } + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); + break; + case 64: case 66: case 67: case 68: // GLOBAL_ATOMIC_SWAP,GLOBAL_ATOMIC_ADD,GLOBAL_ATOMIC_SUB,GLOBAL_ATOMIC_SMIN, + case 69: case 70: case 71: case 72: // GLOBAL_ATOMIC_UMIN,GLOBAL_ATOMIC_SMAX,GLOBAL_ATOMIC_UMAX,GLOBAL_ATOMIC_AND, + case 73: case 74: case 75: case 76: // GLOBAL_ATOMIC_OR,GLOBAL_ATOMIC_XOR,GLOBAL_ATOMIC_INC,GLOBAL_ATOMIC_DEC, + case 77: case 78: // GLOBAL_ATOMIC_ADD_F32,GLOBAL_ATOMIC_PK_ADD_F16, + appendOPR_VGPR(layout.VDST,false,true); + if (layout.SADDR == 0x7f) { + appendOPR_VGPR(layout.ADDR,true,false,2); + } else { + appendOPR_VGPR(layout.ADDR,true,false); + } + appendOPR_VGPR(layout.DATA,true,false); + if (layout.SADDR != 0x7f) { + appendOPR_SREG(layout.SADDR,true,false,2); + } + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); + break; + case 65: case 96: case 98: // GLOBAL_ATOMIC_CMPSWAP,GLOBAL_ATOMIC_SWAP_X2,GLOBAL_ATOMIC_ADD_X2, + case 99: case 100: case 101: // GLOBAL_ATOMIC_SUB_X2,GLOBAL_ATOMIC_SMIN_X2,GLOBAL_ATOMIC_UMIN_X2, + case 102: case 103: case 104: // GLOBAL_ATOMIC_SMAX_X2,GLOBAL_ATOMIC_UMAX_X2,GLOBAL_ATOMIC_AND_X2, + case 105: case 106: case 107: // GLOBAL_ATOMIC_OR_X2,GLOBAL_ATOMIC_XOR_X2,GLOBAL_ATOMIC_INC_X2, + case 108: // GLOBAL_ATOMIC_DEC_X2, + appendOPR_VGPR(layout.VDST,false,true,2); + if (layout.SADDR == 0x7f) { + appendOPR_VGPR(layout.ADDR,true,false,2); + } else { + appendOPR_VGPR(layout.ADDR,true,false); + } + appendOPR_VGPR(layout.DATA,true,false,2); + if (layout.SADDR != 0x7f) { + appendOPR_SREG(layout.SADDR,true,false,2); + } + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); + break; + case 97: // GLOBAL_ATOMIC_CMPSWAP_X2, + appendOPR_VGPR(layout.VDST,false,true,4); + if (layout.SADDR == 0x7f) { + appendOPR_VGPR(layout.ADDR,true,false,2); + } else { + appendOPR_VGPR(layout.ADDR,true,false); + } + appendOPR_VGPR(layout.DATA,true,false,4); + if (layout.SADDR != 0x7f) { + appendOPR_SREG(layout.SADDR,true,false,2); + } + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); + break; + } + } + + void InstructionDecoder_amdgpu_gfx908::finalizeENC_FLAT_SCRATCHOperands() + { + layout_ENC_FLAT_SCRATCH & layout = insn_layout.ENC_FLAT_SCRATCH; + switch (layout.OP) { + case 16: case 17: case 18: case 19: // SCRATCH_LOAD_UBYTE,SCRATCH_LOAD_SBYTE,SCRATCH_LOAD_USHORT,SCRATCH_LOAD_SSHORT, + case 20: case 32: case 33: // SCRATCH_LOAD_DWORD,SCRATCH_LOAD_UBYTE_D16,SCRATCH_LOAD_UBYTE_D16_HI, + case 34: case 35: case 36: // SCRATCH_LOAD_SBYTE_D16,SCRATCH_LOAD_SBYTE_D16_HI,SCRATCH_LOAD_SHORT_D16, + case 37: // SCRATCH_LOAD_SHORT_D16_HI, + appendOPR_VGPR(layout.VDST,false,true); + if (layout.SADDR == 0x7f) { + appendOPR_VGPR(layout.ADDR,true,false,2); + } else { + appendOPR_VGPR(layout.ADDR,true,false); + } + if (layout.SADDR != 0x7f) { + appendOPR_SREG(layout.SADDR,true,false,2); + } + appendOPR_FLAT_SCRATCH(0,true,false,1,true); + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); + break; + case 21: // SCRATCH_LOAD_DWORDX2, + appendOPR_VGPR(layout.VDST,false,true,2); + if (layout.SADDR == 0x7f) { + appendOPR_VGPR(layout.ADDR,true,false,2); + } else { + appendOPR_VGPR(layout.ADDR,true,false); + } + if (layout.SADDR != 0x7f) { + appendOPR_SREG(layout.SADDR,true,false,2); + } + appendOPR_FLAT_SCRATCH(0,true,false,1,true); + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); + break; + case 22: // SCRATCH_LOAD_DWORDX3, + appendOPR_VGPR(layout.VDST,false,true,3); + if (layout.SADDR == 0x7f) { + appendOPR_VGPR(layout.ADDR,true,false,2); + } else { + appendOPR_VGPR(layout.ADDR,true,false); + } + if (layout.SADDR != 0x7f) { + appendOPR_SREG(layout.SADDR,true,false,2); + } + appendOPR_FLAT_SCRATCH(0,true,false,1,true); + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); + break; + case 23: // SCRATCH_LOAD_DWORDX4, + appendOPR_VGPR(layout.VDST,false,true,4); + if (layout.SADDR == 0x7f) { + appendOPR_VGPR(layout.ADDR,true,false,2); + } else { + appendOPR_VGPR(layout.ADDR,true,false); + } + if (layout.SADDR != 0x7f) { + appendOPR_SREG(layout.SADDR,true,false,2); + } + appendOPR_FLAT_SCRATCH(0,true,false,1,true); + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); + break; + case 24: case 25: case 26: // SCRATCH_STORE_BYTE,SCRATCH_STORE_BYTE_D16_HI,SCRATCH_STORE_SHORT, + case 27: case 28: // SCRATCH_STORE_SHORT_D16_HI,SCRATCH_STORE_DWORD, + if (layout.SADDR == 0x7f) { + appendOPR_VGPR(layout.ADDR,true,false,2); + } else { + appendOPR_VGPR(layout.ADDR,true,false); + } + appendOPR_VGPR(layout.DATA,true,false); + if (layout.SADDR != 0x7f) { + appendOPR_SREG(layout.SADDR,true,false,2); + } + appendOPR_FLAT_SCRATCH(0,true,false,1,true); + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); + break; + case 29: // SCRATCH_STORE_DWORDX2, + if (layout.SADDR == 0x7f) { + appendOPR_VGPR(layout.ADDR,true,false,2); + } else { + appendOPR_VGPR(layout.ADDR,true,false); + } + appendOPR_VGPR(layout.DATA,true,false,2); + if (layout.SADDR != 0x7f) { + appendOPR_SREG(layout.SADDR,true,false,2); + } + appendOPR_FLAT_SCRATCH(0,true,false,1,true); + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); + break; + case 30: // SCRATCH_STORE_DWORDX3, + if (layout.SADDR == 0x7f) { + appendOPR_VGPR(layout.ADDR,true,false,2); + } else { + appendOPR_VGPR(layout.ADDR,true,false); + } + appendOPR_VGPR(layout.DATA,true,false,3); + if (layout.SADDR != 0x7f) { + appendOPR_SREG(layout.SADDR,true,false,2); + } + appendOPR_FLAT_SCRATCH(0,true,false,1,true); + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); + break; + case 31: // SCRATCH_STORE_DWORDX4, + if (layout.SADDR == 0x7f) { + appendOPR_VGPR(layout.ADDR,true,false,2); + } else { + appendOPR_VGPR(layout.ADDR,true,false); + } + appendOPR_VGPR(layout.DATA,true,false,4); + if (layout.SADDR != 0x7f) { + appendOPR_SREG(layout.SADDR,true,false,2); + } + appendOPR_FLAT_SCRATCH(0,true,false,1,true); + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); + break; + } + } + + void InstructionDecoder_amdgpu_gfx908::finalizeENC_MIMGOperands() + { + layout_ENC_MIMG & layout = insn_layout.ENC_MIMG; + switch (layout.OP) { + case 0: case 1: case 2: case 3: // IMAGE_LOAD,IMAGE_LOAD_MIP,IMAGE_LOAD_PCK,IMAGE_LOAD_PCK_SGN, + case 4: case 5: // IMAGE_LOAD_MIP_PCK,IMAGE_LOAD_MIP_PCK_SGN, + appendOPR_VGPR(layout.VDATA,false,true,4); + appendOPR_VGPR(layout.VADDR,true,false,4); + appendOPR_SREG(layout.SRSRC,true,false,8); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); + break; + case 8: case 9: case 10: case 11: // IMAGE_STORE,IMAGE_STORE_MIP,IMAGE_STORE_PCK,IMAGE_STORE_MIP_PCK, + appendOPR_VGPR(layout.VDATA,true,false,4); + appendOPR_VGPR(layout.VADDR,true,false,4); + appendOPR_SREG(layout.SRSRC,true,false,8); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); + break; + case 14: // IMAGE_GET_RESINFO, + appendOPR_VGPR(layout.VDATA,false,true,4); + appendOPR_VGPR(layout.VADDR,true,false); + appendOPR_SREG(layout.SRSRC,true,false,8); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); + break; + case 16: case 17: case 18: case 19: // IMAGE_ATOMIC_SWAP,IMAGE_ATOMIC_CMPSWAP,IMAGE_ATOMIC_ADD,IMAGE_ATOMIC_SUB, + case 20: case 21: case 22: case 23: // IMAGE_ATOMIC_SMIN,IMAGE_ATOMIC_UMIN,IMAGE_ATOMIC_SMAX,IMAGE_ATOMIC_UMAX, + case 24: case 25: case 26: case 27: // IMAGE_ATOMIC_AND,IMAGE_ATOMIC_OR,IMAGE_ATOMIC_XOR,IMAGE_ATOMIC_INC, + case 28: // IMAGE_ATOMIC_DEC, + appendOPR_VGPR(layout.VDATA,true,true,4); + appendOPR_VGPR(layout.VADDR,true,false,4); + appendOPR_SREG(layout.SRSRC,true,false,8); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); + break; + case 32: case 39: case 64: case 66: // IMAGE_SAMPLE,IMAGE_SAMPLE_LZ,IMAGE_GATHER4,IMAGE_GATHER4H, + case 71: case 74: case 75: case 96: // IMAGE_GATHER4_LZ,IMAGE_GATHER4H_PCK,IMAGE_GATHER8H_PCK,IMAGE_GET_LOD, + appendOPR_VGPR(layout.VDATA,false,true,4); + appendOPR_VGPR(layout.VADDR,true,false,3); + appendOPR_SREG(layout.SRSRC,true,false,8); + appendOPR_SREG(layout.SSAMP,true,false,4); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); + break; + case 33: case 36: case 37: case 40: // IMAGE_SAMPLE_CL,IMAGE_SAMPLE_L,IMAGE_SAMPLE_B,IMAGE_SAMPLE_C, + case 47: case 48: case 55: case 65: // IMAGE_SAMPLE_C_LZ,IMAGE_SAMPLE_O,IMAGE_SAMPLE_LZ_O,IMAGE_GATHER4_CL, + case 68: case 69: case 72: case 79: // IMAGE_GATHER4_L,IMAGE_GATHER4_B,IMAGE_GATHER4_C,IMAGE_GATHER4_C_LZ, + case 80: case 87: // IMAGE_GATHER4_O,IMAGE_GATHER4_LZ_O, + appendOPR_VGPR(layout.VDATA,false,true,4); + appendOPR_VGPR(layout.VADDR,true,false,4); + appendOPR_SREG(layout.SRSRC,true,false,8); + appendOPR_SREG(layout.SSAMP,true,false,4); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); + break; + case 34: case 104: // IMAGE_SAMPLE_D,IMAGE_SAMPLE_CD, + appendOPR_VGPR(layout.VDATA,false,true,4); + appendOPR_VGPR(layout.VADDR,true,false,9); + appendOPR_SREG(layout.SRSRC,true,false,8); + appendOPR_SREG(layout.SSAMP,true,false,4); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); + break; + case 35: case 42: case 50: case 105: // IMAGE_SAMPLE_D_CL,IMAGE_SAMPLE_C_D,IMAGE_SAMPLE_D_O,IMAGE_SAMPLE_CD_CL, + case 106: case 108: // IMAGE_SAMPLE_C_CD,IMAGE_SAMPLE_CD_O, + appendOPR_VGPR(layout.VDATA,false,true,4); + appendOPR_VGPR(layout.VADDR,true,false,10); + appendOPR_SREG(layout.SRSRC,true,false,8); + appendOPR_SREG(layout.SSAMP,true,false,4); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); + break; + case 38: case 41: case 44: case 45: // IMAGE_SAMPLE_B_CL,IMAGE_SAMPLE_C_CL,IMAGE_SAMPLE_C_L,IMAGE_SAMPLE_C_B, + case 49: case 52: case 53: case 56: // IMAGE_SAMPLE_CL_O,IMAGE_SAMPLE_L_O,IMAGE_SAMPLE_B_O,IMAGE_SAMPLE_C_O, + case 63: case 70: case 73: case 76: // IMAGE_SAMPLE_C_LZ_O,IMAGE_GATHER4_B_CL,IMAGE_GATHER4_C_CL,IMAGE_GATHER4_C_L, + case 77: case 81: case 84: case 85: // IMAGE_GATHER4_C_B,IMAGE_GATHER4_CL_O,IMAGE_GATHER4_L_O,IMAGE_GATHER4_B_O, + case 88: case 95: // IMAGE_GATHER4_C_O,IMAGE_GATHER4_C_LZ_O, + appendOPR_VGPR(layout.VDATA,false,true,4); + appendOPR_VGPR(layout.VADDR,true,false,5); + appendOPR_SREG(layout.SRSRC,true,false,8); + appendOPR_SREG(layout.SSAMP,true,false,4); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); + break; + case 43: case 51: case 58: // IMAGE_SAMPLE_C_D_CL,IMAGE_SAMPLE_D_CL_O,IMAGE_SAMPLE_C_D_O, + case 107: case 109: case 110: // IMAGE_SAMPLE_C_CD_CL,IMAGE_SAMPLE_CD_CL_O,IMAGE_SAMPLE_C_CD_O, + appendOPR_VGPR(layout.VDATA,false,true,4); + appendOPR_VGPR(layout.VADDR,true,false,11); + appendOPR_SREG(layout.SRSRC,true,false,8); + appendOPR_SREG(layout.SSAMP,true,false,4); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); + break; + case 46: case 54: case 57: // IMAGE_SAMPLE_C_B_CL,IMAGE_SAMPLE_B_CL_O,IMAGE_SAMPLE_C_CL_O, + case 60: case 61: case 78: // IMAGE_SAMPLE_C_L_O,IMAGE_SAMPLE_C_B_O,IMAGE_GATHER4_C_B_CL, + case 86: case 89: case 92: // IMAGE_GATHER4_B_CL_O,IMAGE_GATHER4_C_CL_O,IMAGE_GATHER4_C_L_O, + case 93: // IMAGE_GATHER4_C_B_O, + appendOPR_VGPR(layout.VDATA,false,true,4); + appendOPR_VGPR(layout.VADDR,true,false,6); + appendOPR_SREG(layout.SRSRC,true,false,8); + appendOPR_SREG(layout.SSAMP,true,false,4); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); + break; + case 59: case 111: // IMAGE_SAMPLE_C_D_CL_O,IMAGE_SAMPLE_C_CD_CL_O, + appendOPR_VGPR(layout.VDATA,false,true,4); + appendOPR_VGPR(layout.VADDR,true,false,12); + appendOPR_SREG(layout.SRSRC,true,false,8); + appendOPR_SREG(layout.SSAMP,true,false,4); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); + break; + case 62: case 94: // IMAGE_SAMPLE_C_B_CL_O,IMAGE_GATHER4_C_B_CL_O, + appendOPR_VGPR(layout.VDATA,false,true,4); + appendOPR_VGPR(layout.VADDR,true,false,7); + appendOPR_SREG(layout.SRSRC,true,false,8); + appendOPR_SREG(layout.SSAMP,true,false,4); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); + break; + } + } + + void InstructionDecoder_amdgpu_gfx908::finalizeENC_MTBUFOperands() + { + layout_ENC_MTBUF & layout = insn_layout.ENC_MTBUF; + switch (layout.OP) { + case 0: case 8: case 9: // TBUFFER_LOAD_FORMAT_X,TBUFFER_LOAD_FORMAT_D16_X,TBUFFER_LOAD_FORMAT_D16_XY, + appendOPR_VGPR(layout.VDATA,false,true); + appendOPR_VGPR(layout.VADDR,true,false,2); + appendOPR_SREG(layout.SRSRC,true,false,4); + appendOPR_SSRC_NOLIT(layout.SOFFSET,true,false); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); + break; + case 1: case 10: case 11: // TBUFFER_LOAD_FORMAT_XY,TBUFFER_LOAD_FORMAT_D16_XYZ,TBUFFER_LOAD_FORMAT_D16_XYZW, + appendOPR_VGPR(layout.VDATA,false,true,2); + appendOPR_VGPR(layout.VADDR,true,false,2); + appendOPR_SREG(layout.SRSRC,true,false,4); + appendOPR_SSRC_NOLIT(layout.SOFFSET,true,false); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); + break; + case 2: // TBUFFER_LOAD_FORMAT_XYZ, + appendOPR_VGPR(layout.VDATA,false,true,3); + appendOPR_VGPR(layout.VADDR,true,false,2); + appendOPR_SREG(layout.SRSRC,true,false,4); + appendOPR_SSRC_NOLIT(layout.SOFFSET,true,false); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); + break; + case 3: // TBUFFER_LOAD_FORMAT_XYZW, + appendOPR_VGPR(layout.VDATA,false,true,4); + appendOPR_VGPR(layout.VADDR,true,false,2); + appendOPR_SREG(layout.SRSRC,true,false,4); + appendOPR_SSRC_NOLIT(layout.SOFFSET,true,false); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); + break; + case 4: case 12: case 13: // TBUFFER_STORE_FORMAT_X,TBUFFER_STORE_FORMAT_D16_X,TBUFFER_STORE_FORMAT_D16_XY, + appendOPR_VGPR(layout.VDATA,true,false); + appendOPR_VGPR(layout.VADDR,true,false,2); + appendOPR_SREG(layout.SRSRC,true,false,4); + appendOPR_SSRC_NOLIT(layout.SOFFSET,true,false); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); + break; + case 5: case 14: case 15: // TBUFFER_STORE_FORMAT_XY,TBUFFER_STORE_FORMAT_D16_XYZ,TBUFFER_STORE_FORMAT_D16_XYZW, + appendOPR_VGPR(layout.VDATA,true,false,2); + appendOPR_VGPR(layout.VADDR,true,false,2); + appendOPR_SREG(layout.SRSRC,true,false,4); + appendOPR_SSRC_NOLIT(layout.SOFFSET,true,false); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); + break; + case 6: // TBUFFER_STORE_FORMAT_XYZ, + appendOPR_VGPR(layout.VDATA,true,false,3); + appendOPR_VGPR(layout.VADDR,true,false,2); + appendOPR_SREG(layout.SRSRC,true,false,4); + appendOPR_SSRC_NOLIT(layout.SOFFSET,true,false); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); + break; + case 7: // TBUFFER_STORE_FORMAT_XYZW, + appendOPR_VGPR(layout.VDATA,true,false,4); + appendOPR_VGPR(layout.VADDR,true,false,2); + appendOPR_SREG(layout.SRSRC,true,false,4); + appendOPR_SSRC_NOLIT(layout.SOFFSET,true,false); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); + break; + } + } + + void InstructionDecoder_amdgpu_gfx908::finalizeENC_MUBUFOperands() + { + layout_ENC_MUBUF & layout = insn_layout.ENC_MUBUF; + switch (layout.OP) { + case 0: case 8: case 9: // BUFFER_LOAD_FORMAT_X,BUFFER_LOAD_FORMAT_D16_X,BUFFER_LOAD_FORMAT_D16_XY, + case 16: case 17: case 18: case 19: // BUFFER_LOAD_UBYTE,BUFFER_LOAD_SBYTE,BUFFER_LOAD_USHORT,BUFFER_LOAD_SSHORT, + case 20: case 32: case 33: // BUFFER_LOAD_DWORD,BUFFER_LOAD_UBYTE_D16,BUFFER_LOAD_UBYTE_D16_HI, + case 34: case 35: case 36: // BUFFER_LOAD_SBYTE_D16,BUFFER_LOAD_SBYTE_D16_HI,BUFFER_LOAD_SHORT_D16, + case 37: case 38: // BUFFER_LOAD_SHORT_D16_HI,BUFFER_LOAD_FORMAT_D16_HI_X, + appendOPR_VGPR(layout.VDATA,false,true); + if (layout.IDXEN || layout.OFFEN) { + appendOPR_VGPR(layout.VADDR,true,false); + } else if (layout.OFFSET) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::off,1),false,false,false); + } + if (layout.IDXEN && layout.OFFEN) { + appendOPR_VGPR(layout.VADDR+1,true,false); + } + appendOPR_SREG(layout.SRSRC,true,false,4); + appendOPR_SSRC_NOLIT(layout.SOFFSET,true,false); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); + if (layout.IDXEN) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::idxen,1),false,false,false); + } + if (layout.OFFEN) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::offen,1),false,false,false); + } + if (layout.OFFSET) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,layout.OFFSET)),true,false,false); + } + break; + case 1: case 10: case 11: // BUFFER_LOAD_FORMAT_XY,BUFFER_LOAD_FORMAT_D16_XYZ,BUFFER_LOAD_FORMAT_D16_XYZW, + case 21: // BUFFER_LOAD_DWORDX2, + appendOPR_VGPR(layout.VDATA,false,true,2); + if (layout.IDXEN || layout.OFFEN) { + appendOPR_VGPR(layout.VADDR,true,false); + } else if (layout.OFFSET) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::off,1),false,false,false); + } + if (layout.IDXEN && layout.OFFEN) { + appendOPR_VGPR(layout.VADDR+1,true,false); + } + appendOPR_SREG(layout.SRSRC,true,false,4); + appendOPR_SSRC_NOLIT(layout.SOFFSET,true,false); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); + if (layout.IDXEN) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::idxen,1),false,false,false); + } + if (layout.OFFEN) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::offen,1),false,false,false); + } + if (layout.OFFSET) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,layout.OFFSET)),true,false,false); + } + break; + case 2: case 22: // BUFFER_LOAD_FORMAT_XYZ,BUFFER_LOAD_DWORDX3, + appendOPR_VGPR(layout.VDATA,false,true,3); + if (layout.IDXEN || layout.OFFEN) { + appendOPR_VGPR(layout.VADDR,true,false); + } else if (layout.OFFSET) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::off,1),false,false,false); + } + if (layout.IDXEN && layout.OFFEN) { + appendOPR_VGPR(layout.VADDR+1,true,false); + } + appendOPR_SREG(layout.SRSRC,true,false,4); + appendOPR_SSRC_NOLIT(layout.SOFFSET,true,false); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); + if (layout.IDXEN) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::idxen,1),false,false,false); + } + if (layout.OFFEN) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::offen,1),false,false,false); + } + if (layout.OFFSET) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,layout.OFFSET)),true,false,false); + } + break; + case 3: case 23: // BUFFER_LOAD_FORMAT_XYZW,BUFFER_LOAD_DWORDX4, + appendOPR_VGPR(layout.VDATA,false,true,4); + if (layout.IDXEN || layout.OFFEN) { + appendOPR_VGPR(layout.VADDR,true,false); + } else if (layout.OFFSET) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::off,1),false,false,false); + } + if (layout.IDXEN && layout.OFFEN) { + appendOPR_VGPR(layout.VADDR+1,true,false); + } + appendOPR_SREG(layout.SRSRC,true,false,4); + appendOPR_SSRC_NOLIT(layout.SOFFSET,true,false); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); + if (layout.IDXEN) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::idxen,1),false,false,false); + } + if (layout.OFFEN) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::offen,1),false,false,false); + } + if (layout.OFFSET) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,layout.OFFSET)),true,false,false); + } + break; + case 4: case 12: case 13: // BUFFER_STORE_FORMAT_X,BUFFER_STORE_FORMAT_D16_X,BUFFER_STORE_FORMAT_D16_XY, + case 24: case 25: case 26: // BUFFER_STORE_BYTE,BUFFER_STORE_BYTE_D16_HI,BUFFER_STORE_SHORT, + case 27: case 28: case 39: // BUFFER_STORE_SHORT_D16_HI,BUFFER_STORE_DWORD,BUFFER_STORE_FORMAT_D16_HI_X, + appendOPR_VGPR(layout.VDATA,true,false); + if (layout.IDXEN || layout.OFFEN) { + appendOPR_VGPR(layout.VADDR,true,false); + } else if (layout.OFFSET) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::off,1),false,false,false); + } + if (layout.IDXEN && layout.OFFEN) { + appendOPR_VGPR(layout.VADDR+1,true,false); + } + appendOPR_SREG(layout.SRSRC,true,false,4); + appendOPR_SSRC_NOLIT(layout.SOFFSET,true,false); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); + if (layout.IDXEN) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::idxen,1),false,false,false); + } + if (layout.OFFEN) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::offen,1),false,false,false); + } + if (layout.OFFSET) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,layout.OFFSET)),true,false,false); + } + break; + case 5: case 14: case 15: // BUFFER_STORE_FORMAT_XY,BUFFER_STORE_FORMAT_D16_XYZ,BUFFER_STORE_FORMAT_D16_XYZW, + case 29: // BUFFER_STORE_DWORDX2, + appendOPR_VGPR(layout.VDATA,true,false,2); + if (layout.IDXEN || layout.OFFEN) { + appendOPR_VGPR(layout.VADDR,true,false); + } else if (layout.OFFSET) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::off,1),false,false,false); + } + if (layout.IDXEN && layout.OFFEN) { + appendOPR_VGPR(layout.VADDR+1,true,false); + } + appendOPR_SREG(layout.SRSRC,true,false,4); + appendOPR_SSRC_NOLIT(layout.SOFFSET,true,false); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); + if (layout.IDXEN) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::idxen,1),false,false,false); + } + if (layout.OFFEN) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::offen,1),false,false,false); + } + if (layout.OFFSET) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,layout.OFFSET)),true,false,false); + } + break; + case 6: case 30: // BUFFER_STORE_FORMAT_XYZ,BUFFER_STORE_DWORDX3, + appendOPR_VGPR(layout.VDATA,true,false,3); + if (layout.IDXEN || layout.OFFEN) { + appendOPR_VGPR(layout.VADDR,true,false); + } else if (layout.OFFSET) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::off,1),false,false,false); + } + if (layout.IDXEN && layout.OFFEN) { + appendOPR_VGPR(layout.VADDR+1,true,false); + } + appendOPR_SREG(layout.SRSRC,true,false,4); + appendOPR_SSRC_NOLIT(layout.SOFFSET,true,false); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); + if (layout.IDXEN) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::idxen,1),false,false,false); + } + if (layout.OFFEN) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::offen,1),false,false,false); + } + if (layout.OFFSET) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,layout.OFFSET)),true,false,false); + } + break; + case 7: case 31: // BUFFER_STORE_FORMAT_XYZW,BUFFER_STORE_DWORDX4, + appendOPR_VGPR(layout.VDATA,true,false,4); + if (layout.IDXEN || layout.OFFEN) { + appendOPR_VGPR(layout.VADDR,true,false); + } else if (layout.OFFSET) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::off,1),false,false,false); + } + if (layout.IDXEN && layout.OFFEN) { + appendOPR_VGPR(layout.VADDR+1,true,false); + } + appendOPR_SREG(layout.SRSRC,true,false,4); + appendOPR_SSRC_NOLIT(layout.SOFFSET,true,false); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); + if (layout.IDXEN) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::idxen,1),false,false,false); + } + if (layout.OFFEN) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::offen,1),false,false,false); + } + if (layout.OFFSET) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,layout.OFFSET)),true,false,false); + } + break; + case 61: // BUFFER_STORE_LDS_DWORD, + appendOPR_SREG(layout.SRSRC,true,false,4); + appendOPR_SSRC_NOLIT(layout.SOFFSET,true,false); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); + if (layout.IDXEN) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::idxen,1),false,false,false); + } + if (layout.OFFEN) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::offen,1),false,false,false); + } + if (layout.OFFSET) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,layout.OFFSET)),true,false,false); + } + break; + case 62: case 63: // BUFFER_WBINVL1,BUFFER_WBINVL1_VOL, + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); + if (layout.IDXEN) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::idxen,1),false,false,false); + } + if (layout.OFFEN) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::offen,1),false,false,false); + } + if (layout.OFFSET) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,layout.OFFSET)),true,false,false); + } + break; + case 64: case 66: case 67: case 68: // BUFFER_ATOMIC_SWAP,BUFFER_ATOMIC_ADD,BUFFER_ATOMIC_SUB,BUFFER_ATOMIC_SMIN, + case 69: case 70: case 71: case 72: // BUFFER_ATOMIC_UMIN,BUFFER_ATOMIC_SMAX,BUFFER_ATOMIC_UMAX,BUFFER_ATOMIC_AND, + case 73: case 74: case 75: case 76: // BUFFER_ATOMIC_OR,BUFFER_ATOMIC_XOR,BUFFER_ATOMIC_INC,BUFFER_ATOMIC_DEC, + case 77: case 78: // BUFFER_ATOMIC_ADD_F32,BUFFER_ATOMIC_PK_ADD_F16, + appendOPR_VGPR(layout.VDATA,true,true); + if (layout.IDXEN || layout.OFFEN) { + appendOPR_VGPR(layout.VADDR,true,false); + } else if (layout.OFFSET) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::off,1),false,false,false); + } + if (layout.IDXEN && layout.OFFEN) { + appendOPR_VGPR(layout.VADDR+1,true,false); + } + appendOPR_SREG(layout.SRSRC,true,false,4); + appendOPR_SSRC_NOLIT(layout.SOFFSET,true,false); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); + if (layout.IDXEN) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::idxen,1),false,false,false); + } + if (layout.OFFEN) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::offen,1),false,false,false); + } + if (layout.OFFSET) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,layout.OFFSET)),true,false,false); + } + break; + case 65: case 96: case 98: // BUFFER_ATOMIC_CMPSWAP,BUFFER_ATOMIC_SWAP_X2,BUFFER_ATOMIC_ADD_X2, + case 99: case 100: case 101: // BUFFER_ATOMIC_SUB_X2,BUFFER_ATOMIC_SMIN_X2,BUFFER_ATOMIC_UMIN_X2, + case 102: case 103: case 104: // BUFFER_ATOMIC_SMAX_X2,BUFFER_ATOMIC_UMAX_X2,BUFFER_ATOMIC_AND_X2, + case 105: case 106: case 107: // BUFFER_ATOMIC_OR_X2,BUFFER_ATOMIC_XOR_X2,BUFFER_ATOMIC_INC_X2, + case 108: // BUFFER_ATOMIC_DEC_X2, + appendOPR_VGPR(layout.VDATA,true,true,2); + if (layout.IDXEN || layout.OFFEN) { + appendOPR_VGPR(layout.VADDR,true,false); + } else if (layout.OFFSET) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::off,1),false,false,false); + } + if (layout.IDXEN && layout.OFFEN) { + appendOPR_VGPR(layout.VADDR+1,true,false); + } + appendOPR_SREG(layout.SRSRC,true,false,4); + appendOPR_SSRC_NOLIT(layout.SOFFSET,true,false); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); + if (layout.IDXEN) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::idxen,1),false,false,false); + } + if (layout.OFFEN) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::offen,1),false,false,false); + } + if (layout.OFFSET) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,layout.OFFSET)),true,false,false); + } + break; + case 97: // BUFFER_ATOMIC_CMPSWAP_X2, + appendOPR_VGPR(layout.VDATA,true,true,4); + if (layout.IDXEN || layout.OFFEN) { + appendOPR_VGPR(layout.VADDR,true,false); + } else if (layout.OFFSET) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::off,1),false,false,false); + } + if (layout.IDXEN && layout.OFFEN) { + appendOPR_VGPR(layout.VADDR+1,true,false); + } + appendOPR_SREG(layout.SRSRC,true,false,4); + appendOPR_SSRC_NOLIT(layout.SOFFSET,true,false); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,36),true,true,true); + if (layout.IDXEN) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::idxen,1),false,false,false); + } + if (layout.OFFEN) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::offen,1),false,false,false); + } + if (layout.OFFSET) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,layout.OFFSET)),true,false,false); + } + break; + } + } + + void InstructionDecoder_amdgpu_gfx908::finalizeENC_SMEMOperands() + { + layout_ENC_SMEM & layout = insn_layout.ENC_SMEM; + switch (layout.OP) { + case 0: case 5: // S_LOAD_DWORD,S_SCRATCH_LOAD_DWORD, + appendOPR_SREG(layout.SDATA,false,true); + appendOPR_SREG(layout.SBASE,true,false,2); + processOPR_SMEM_OFFSET(layout); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); + break; + case 1: case 6: // S_LOAD_DWORDX2,S_SCRATCH_LOAD_DWORDX2, + appendOPR_SREG(layout.SDATA,false,true,2); + appendOPR_SREG(layout.SBASE,true,false,2); + processOPR_SMEM_OFFSET(layout); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); + break; + case 2: case 7: // S_LOAD_DWORDX4,S_SCRATCH_LOAD_DWORDX4, + appendOPR_SREG(layout.SDATA,false,true,4); + appendOPR_SREG(layout.SBASE,true,false,2); + processOPR_SMEM_OFFSET(layout); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); + break; + case 3: // S_LOAD_DWORDX8, + appendOPR_SREG(layout.SDATA,false,true,8); + appendOPR_SREG(layout.SBASE,true,false,2); + processOPR_SMEM_OFFSET(layout); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); + break; + case 4: // S_LOAD_DWORDX16, + appendOPR_SREG(layout.SDATA,false,true,16); + appendOPR_SREG(layout.SBASE,true,false,2); + processOPR_SMEM_OFFSET(layout); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); + break; + case 8: // S_BUFFER_LOAD_DWORD, + appendOPR_SREG(layout.SDATA,false,true); + appendOPR_SREG(layout.SBASE,true,false,4); + processOPR_SMEM_OFFSET(layout); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); + break; + case 9: // S_BUFFER_LOAD_DWORDX2, + appendOPR_SREG(layout.SDATA,false,true,2); + appendOPR_SREG(layout.SBASE,true,false,4); + processOPR_SMEM_OFFSET(layout); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); + break; + case 10: // S_BUFFER_LOAD_DWORDX4, + appendOPR_SREG(layout.SDATA,false,true,4); + appendOPR_SREG(layout.SBASE,true,false,4); + processOPR_SMEM_OFFSET(layout); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); + break; + case 11: // S_BUFFER_LOAD_DWORDX8, + appendOPR_SREG(layout.SDATA,false,true,8); + appendOPR_SREG(layout.SBASE,true,false,4); + processOPR_SMEM_OFFSET(layout); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); + break; + case 12: // S_BUFFER_LOAD_DWORDX16, + appendOPR_SREG(layout.SDATA,false,true,16); + appendOPR_SREG(layout.SBASE,true,false,4); + processOPR_SMEM_OFFSET(layout); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); + break; + case 16: case 21: // S_STORE_DWORD,S_SCRATCH_STORE_DWORD, + appendOPR_SREG(layout.SDATA,true,false); + appendOPR_SREG(layout.SBASE,true,false,2); + processOPR_SMEM_OFFSET(layout); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); + break; + case 17: case 22: // S_STORE_DWORDX2,S_SCRATCH_STORE_DWORDX2, + appendOPR_SREG(layout.SDATA,true,false,2); + appendOPR_SREG(layout.SBASE,true,false,2); + processOPR_SMEM_OFFSET(layout); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); + break; + case 18: case 23: // S_STORE_DWORDX4,S_SCRATCH_STORE_DWORDX4, + appendOPR_SREG(layout.SDATA,true,false,4); + appendOPR_SREG(layout.SBASE,true,false,2); + processOPR_SMEM_OFFSET(layout); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); + break; + case 24: // S_BUFFER_STORE_DWORD, + appendOPR_SREG(layout.SDATA,true,false); + appendOPR_SREG(layout.SBASE,true,false,4); + processOPR_SMEM_OFFSET(layout); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); + break; + case 25: // S_BUFFER_STORE_DWORDX2, + appendOPR_SREG(layout.SDATA,true,false,2); + appendOPR_SREG(layout.SBASE,true,false,4); + processOPR_SMEM_OFFSET(layout); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); + break; + case 26: // S_BUFFER_STORE_DWORDX4, + appendOPR_SREG(layout.SDATA,true,false,4); + appendOPR_SREG(layout.SBASE,true,false,4); + processOPR_SMEM_OFFSET(layout); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); + break; + case 32: case 33: case 34: case 35: // S_DCACHE_INV,S_DCACHE_WB,S_DCACHE_INV_VOL,S_DCACHE_WB_VOL, + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); + break; + case 36: case 37: // S_MEMTIME,S_MEMREALTIME, + appendOPR_SREG(layout.SDATA,false,true,2); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); + break; + case 38: // S_ATC_PROBE, + appendOPR_SIMM8(layout.SDATA,true,false); + appendOPR_SREG(layout.SBASE,true,false,2); + processOPR_SMEM_OFFSET(layout); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); + break; + case 39: // S_ATC_PROBE_BUFFER, + appendOPR_SIMM8(layout.SDATA,true,false); + appendOPR_SREG(layout.SBASE,true,false,4); + processOPR_SMEM_OFFSET(layout); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); + break; + case 40: case 41: // S_DCACHE_DISCARD,S_DCACHE_DISCARD_X2, + appendOPR_SREG(layout.SBASE,true,false,2); + processOPR_SMEM_OFFSET(layout); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); + break; + case 64: case 66: case 67: // S_BUFFER_ATOMIC_SWAP,S_BUFFER_ATOMIC_ADD,S_BUFFER_ATOMIC_SUB, + case 68: case 69: case 70: // S_BUFFER_ATOMIC_SMIN,S_BUFFER_ATOMIC_UMIN,S_BUFFER_ATOMIC_SMAX, + case 71: case 72: case 73: // S_BUFFER_ATOMIC_UMAX,S_BUFFER_ATOMIC_AND,S_BUFFER_ATOMIC_OR, + case 74: case 75: case 76: // S_BUFFER_ATOMIC_XOR,S_BUFFER_ATOMIC_INC,S_BUFFER_ATOMIC_DEC, + appendOPR_SREG(layout.SDATA,true,true); + appendOPR_SREG(layout.SBASE,true,false,4); + processOPR_SMEM_OFFSET(layout); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); + break; + case 65: case 96: case 98: // S_BUFFER_ATOMIC_CMPSWAP,S_BUFFER_ATOMIC_SWAP_X2,S_BUFFER_ATOMIC_ADD_X2, + case 99: case 100: case 101: // S_BUFFER_ATOMIC_SUB_X2,S_BUFFER_ATOMIC_SMIN_X2,S_BUFFER_ATOMIC_UMIN_X2, + case 102: case 103: case 104: // S_BUFFER_ATOMIC_SMAX_X2,S_BUFFER_ATOMIC_UMAX_X2,S_BUFFER_ATOMIC_AND_X2, + case 105: case 106: case 107: // S_BUFFER_ATOMIC_OR_X2,S_BUFFER_ATOMIC_XOR_X2,S_BUFFER_ATOMIC_INC_X2, + case 108: // S_BUFFER_ATOMIC_DEC_X2, + appendOPR_SREG(layout.SDATA,true,true,2); + appendOPR_SREG(layout.SBASE,true,false,4); + processOPR_SMEM_OFFSET(layout); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); + break; + case 97: // S_BUFFER_ATOMIC_CMPSWAP_X2, + appendOPR_SREG(layout.SDATA,true,true,4); + appendOPR_SREG(layout.SBASE,true,false,4); + processOPR_SMEM_OFFSET(layout); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); + break; + case 128: case 130: case 131: case 132: // S_ATOMIC_SWAP,S_ATOMIC_ADD,S_ATOMIC_SUB,S_ATOMIC_SMIN, + case 133: case 134: case 135: case 136: // S_ATOMIC_UMIN,S_ATOMIC_SMAX,S_ATOMIC_UMAX,S_ATOMIC_AND, + case 137: case 138: case 139: case 140: // S_ATOMIC_OR,S_ATOMIC_XOR,S_ATOMIC_INC,S_ATOMIC_DEC, + appendOPR_SREG(layout.SDATA,true,true); + appendOPR_SREG(layout.SBASE,true,false,2); + processOPR_SMEM_OFFSET(layout); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); + break; + case 129: case 160: case 162: case 163: // S_ATOMIC_CMPSWAP,S_ATOMIC_SWAP_X2,S_ATOMIC_ADD_X2,S_ATOMIC_SUB_X2, + case 164: case 165: case 166: case 167: // S_ATOMIC_SMIN_X2,S_ATOMIC_UMIN_X2,S_ATOMIC_SMAX_X2,S_ATOMIC_UMAX_X2, + case 168: case 169: case 170: case 171: // S_ATOMIC_AND_X2,S_ATOMIC_OR_X2,S_ATOMIC_XOR_X2,S_ATOMIC_INC_X2, + case 172: // S_ATOMIC_DEC_X2, + appendOPR_SREG(layout.SDATA,true,true,2); + appendOPR_SREG(layout.SBASE,true,false,2); + processOPR_SMEM_OFFSET(layout); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); + break; + case 161: // S_ATOMIC_CMPSWAP_X2, + appendOPR_SREG(layout.SDATA,true,true,4); + appendOPR_SREG(layout.SBASE,true,false,2); + processOPR_SMEM_OFFSET(layout); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,16),true,true,true); + break; + } + } + + void InstructionDecoder_amdgpu_gfx908::finalizeENC_SOP1Operands() + { + layout_ENC_SOP1 & layout = insn_layout.ENC_SOP1; + switch (layout.OP) { + case 0: case 8: case 14: case 16: case 18: // S_MOV_B32,S_BREV_B32,S_FF0_I32_B32,S_FF1_I32_B32,S_FLBIT_I32_B32, + case 20: case 22: case 23: // S_FLBIT_I32,S_SEXT_I32_I8,S_SEXT_I32_I16, + appendOPR_SDST(layout.SDST,false,true); + appendOPR_SSRC(layout.SSRC0,true,false); + break; + case 1: case 9: // S_MOV_B64,S_BREV_B64, + appendOPR_SDST(layout.SDST,false,true,2); + appendOPR_SSRC(layout.SSRC0,true,false,2); + break; + case 2: // S_CMOV_B32, + appendOPR_SDST(layout.SDST,true,true); + appendOPR_SSRC(layout.SSRC0,true,false); + appendOPR_SSRC_SPECIAL_SCC(253,true,false,1,true); + break; + case 3: // S_CMOV_B64, + appendOPR_SDST(layout.SDST,true,true,2); + appendOPR_SSRC(layout.SSRC0,true,false,2); + appendOPR_SSRC_SPECIAL_SCC(253,true,false,1,true); + break; + case 4: case 6: case 10: case 12: case 40: // S_NOT_B32,S_WQM_B32,S_BCNT0_I32_B32,S_BCNT1_I32_B32,S_QUADMASK_B32, + case 48: // S_ABS_I32, + appendOPR_SDST(layout.SDST,false,true); + appendOPR_SSRC(layout.SSRC0,true,false); + appendOPR_SSRC_SPECIAL_SCC(253,false,true,1,true); + break; + case 5: case 7: case 41: // S_NOT_B64,S_WQM_B64,S_QUADMASK_B64, + appendOPR_SDST(layout.SDST,false,true,2); + appendOPR_SSRC(layout.SSRC0,true,false,2); + appendOPR_SSRC_SPECIAL_SCC(253,false,true,1,true); + break; + case 11: case 13: // S_BCNT0_I32_B64,S_BCNT1_I32_B64, + appendOPR_SDST(layout.SDST,false,true); + appendOPR_SSRC(layout.SSRC0,true,false,2); + appendOPR_SSRC_SPECIAL_SCC(253,false,true,1,true); + break; + case 15: case 17: case 19: case 21: // S_FF0_I32_B64,S_FF1_I32_B64,S_FLBIT_I32_B64,S_FLBIT_I32_I64, + appendOPR_SDST(layout.SDST,false,true); + appendOPR_SSRC(layout.SSRC0,true,false,2); + break; + case 24: case 26: // S_BITSET0_B32,S_BITSET1_B32, + appendOPR_SDST(layout.SDST,true,true); + appendOPR_SSRC(layout.SSRC0,true,false); + break; + case 25: case 27: // S_BITSET0_B64,S_BITSET1_B64, + appendOPR_SDST(layout.SDST,true,true,2); + appendOPR_SSRC(layout.SSRC0,true,false); + break; + case 28: // S_GETPC_B64, + appendOPR_SDST(layout.SDST,false,true,2); + appendOPR_PC(0,true,false,1,true); + break; + case 29: // S_SETPC_B64, + setBranch(); + setModifyPC(); + appendOPR_SREG(layout.SSRC0,true,false,2); + appendOPR_PC(0,false,true,1,true); + break; + case 30: // S_SWAPPC_B64, + setBranch(); + setModifyPC(); + appendOPR_SDST(layout.SDST,false,true,2); + appendOPR_SREG(layout.SSRC0,true,false,2); + appendOPR_PC(0,false,true,1,true); + appendOPR_PC(0,true,false,1,true); + break; + case 31: // S_RFE_B64, + appendOPR_SREG(layout.SSRC0,true,false,2); + appendOPR_PC(0,false,true,1,true); + break; + case 32: case 33: case 34: case 35: // S_AND_SAVEEXEC_B64,S_OR_SAVEEXEC_B64,S_XOR_SAVEEXEC_B64,S_ANDN2_SAVEEXEC_B64, + case 36: case 37: case 38: // S_ORN2_SAVEEXEC_B64,S_NAND_SAVEEXEC_B64,S_NOR_SAVEEXEC_B64, + case 39: case 51: case 52: // S_XNOR_SAVEEXEC_B64,S_ANDN1_SAVEEXEC_B64,S_ORN1_SAVEEXEC_B64, + case 53: case 54: // S_ANDN1_WREXEC_B64,S_ANDN2_WREXEC_B64, + appendOPR_SREG(layout.SDST,false,true,2); + appendOPR_SSRC(layout.SSRC0,true,false,2); + appendOPR_SDST_EXEC(126,false,true,1,true); + appendOPR_SSRC_SPECIAL_SCC(253,false,true,1,true); + appendOPR_SDST_EXEC(126,true,false,1,true); + break; + case 42: // S_MOVRELS_B32, + appendOPR_SDST(layout.SDST,false,true); + appendOPR_SREG(layout.SSRC0,true,false); + appendOPR_SDST_M0(124,true,false,1,true); + break; + case 43: // S_MOVRELS_B64, + appendOPR_SDST(layout.SDST,false,true,2); + appendOPR_SREG(layout.SSRC0,true,false,2); + appendOPR_SDST_M0(124,true,false,1,true); + break; + case 44: // S_MOVRELD_B32, + appendOPR_SREG(layout.SDST,false,true); + appendOPR_SSRC(layout.SSRC0,true,false); + appendOPR_SDST_M0(124,true,false,1,true); + break; + case 45: // S_MOVRELD_B64, + appendOPR_SREG(layout.SDST,false,true,2); + appendOPR_SSRC(layout.SSRC0,true,false,2); + appendOPR_SDST_M0(124,true,false,1,true); + break; + case 46: // S_CBRANCH_JOIN, + appendOPR_SREG(layout.SSRC0,true,false); + appendOPR_SDST_EXEC(126,false,true,1,true); + appendOPR_PC(0,false,true,1,true); + break; + case 50: // S_SET_GPR_IDX_IDX, + appendOPR_SSRC(layout.SSRC0,true,false); + appendOPR_SDST_M0(124,false,true,1,true); + appendOPR_SDST_M0(124,true,false,1,true); + break; + case 55: // S_BITREPLICATE_B64_B32, + appendOPR_SDST(layout.SDST,false,true,2); + appendOPR_SSRC(layout.SSRC0,true,false); + break; + } + } + + void InstructionDecoder_amdgpu_gfx908::finalizeENC_SOP2Operands() + { + layout_ENC_SOP2 & layout = insn_layout.ENC_SOP2; + switch (layout.OP) { + case 0: case 1: case 2: case 3: case 6: case 7: // S_ADD_U32,S_SUB_U32,S_ADD_I32,S_SUB_I32,S_MIN_I32,S_MIN_U32, + case 8: case 9: case 12: case 14: case 16: // S_MAX_I32,S_MAX_U32,S_AND_B32,S_OR_B32,S_XOR_B32, + case 18: case 20: case 22: case 24: case 26: // S_ANDN2_B32,S_ORN2_B32,S_NAND_B32,S_NOR_B32,S_XNOR_B32, + case 28: case 30: case 32: case 37: case 38: // S_LSHL_B32,S_LSHR_B32,S_ASHR_I32,S_BFE_U32,S_BFE_I32, + case 42: case 46: case 47: case 48: // S_ABSDIFF_I32,S_LSHL1_ADD_U32,S_LSHL2_ADD_U32,S_LSHL3_ADD_U32, + case 49: // S_LSHL4_ADD_U32, + appendOPR_SDST(layout.SDST,false,true); + appendOPR_SSRC(layout.SSRC0,true,false); + appendOPR_SSRC(layout.SSRC1,true,false); + appendOPR_SSRC_SPECIAL_SCC(253,false,true,1,true); + break; + case 4: case 5: // S_ADDC_U32,S_SUBB_U32, + appendOPR_SDST(layout.SDST,false,true); + appendOPR_SSRC(layout.SSRC0,true,false); + appendOPR_SSRC(layout.SSRC1,true,false); + appendOPR_SSRC_SPECIAL_SCC(253,false,true,1,true); + appendOPR_SSRC_SPECIAL_SCC(253,true,false,1,true); + break; + case 10: // S_CSELECT_B32, + appendOPR_SDST(layout.SDST,false,true); + appendOPR_SSRC(layout.SSRC0,true,false); + appendOPR_SSRC(layout.SSRC1,true,false); + appendOPR_SSRC_SPECIAL_SCC(253,true,false,1,true); + break; + case 11: // S_CSELECT_B64, + appendOPR_SDST(layout.SDST,false,true,2); + appendOPR_SSRC(layout.SSRC0,true,false,2); + appendOPR_SSRC(layout.SSRC1,true,false,2); + appendOPR_SSRC_SPECIAL_SCC(253,true,false,1,true); + break; + case 13: case 15: case 17: case 19: case 21: // S_AND_B64,S_OR_B64,S_XOR_B64,S_ANDN2_B64,S_ORN2_B64, + case 23: case 25: case 27: // S_NAND_B64,S_NOR_B64,S_XNOR_B64, + appendOPR_SDST(layout.SDST,false,true,2); + appendOPR_SSRC(layout.SSRC0,true,false,2); + appendOPR_SSRC(layout.SSRC1,true,false,2); + appendOPR_SSRC_SPECIAL_SCC(253,false,true,1,true); + break; + case 29: case 31: case 33: case 39: case 40: // S_LSHL_B64,S_LSHR_B64,S_ASHR_I64,S_BFE_U64,S_BFE_I64, + appendOPR_SDST(layout.SDST,false,true,2); + appendOPR_SSRC(layout.SSRC0,true,false,2); + appendOPR_SSRC(layout.SSRC1,true,false); + appendOPR_SSRC_SPECIAL_SCC(253,false,true,1,true); + break; + case 34: case 36: case 44: case 45: case 50: // S_BFM_B32,S_MUL_I32,S_MUL_HI_U32,S_MUL_HI_I32,S_PACK_LL_B32_B16, + case 51: case 52: // S_PACK_LH_B32_B16,S_PACK_HH_B32_B16, + appendOPR_SDST(layout.SDST,false,true); + appendOPR_SSRC(layout.SSRC0,true,false); + appendOPR_SSRC(layout.SSRC1,true,false); + break; + case 35: // S_BFM_B64, + appendOPR_SDST(layout.SDST,false,true,2); + appendOPR_SSRC(layout.SSRC0,true,false); + appendOPR_SSRC(layout.SSRC1,true,false); + break; + case 41: // S_CBRANCH_G_FORK, + appendOPR_SSRC_NOLIT(layout.SSRC0,true,false,2); + appendOPR_SSRC_NOLIT(layout.SSRC1,true,false,2); + appendOPR_PC(0,false,true,1,true); + break; + case 43: // S_RFE_RESTORE_B64, + appendOPR_SSRC(layout.SSRC0,true,false,2); + appendOPR_SSRC(layout.SSRC1,true,false); + appendOPR_PC(0,false,true,1,true); + break; + } + } + + void InstructionDecoder_amdgpu_gfx908::finalizeENC_SOPCOperands() + { + layout_ENC_SOPC & layout = insn_layout.ENC_SOPC; + switch (layout.OP) { + case 0: case 1: case 2: case 3: case 4: // S_CMP_EQ_I32,S_CMP_LG_I32,S_CMP_GT_I32,S_CMP_GE_I32,S_CMP_LT_I32, + case 5: case 6: case 7: case 8: case 9: // S_CMP_LE_I32,S_CMP_EQ_U32,S_CMP_LG_U32,S_CMP_GT_U32,S_CMP_GE_U32, + case 10: case 11: case 12: case 13: // S_CMP_LT_U32,S_CMP_LE_U32,S_BITCMP0_B32,S_BITCMP1_B32, + appendOPR_SSRC(layout.SSRC0,true,false); + appendOPR_SSRC(layout.SSRC1,true,false); + appendOPR_SSRC_SPECIAL_SCC(253,false,true,1,true); + break; + case 14: case 15: // S_BITCMP0_B64,S_BITCMP1_B64, + appendOPR_SSRC(layout.SSRC0,true,false,2); + appendOPR_SSRC(layout.SSRC1,true,false); + appendOPR_SSRC_SPECIAL_SCC(253,false,true,1,true); + break; + case 16: // S_SETVSKIP, + appendOPR_SSRC(layout.SSRC0,true,false); + appendOPR_SSRC(layout.SSRC1,true,false); + break; + case 17: // S_SET_GPR_IDX_ON, + appendOPR_SSRC(layout.SSRC0,true,false); + appendOPR_SIMM4(layout.SSRC1,true,false); + appendOPR_SDST_M0(124,false,true,1,true); + appendOPR_SDST_M0(124,true,false,1,true); + break; + case 18: case 19: // S_CMP_EQ_U64,S_CMP_LG_U64, + appendOPR_SSRC(layout.SSRC0,true,false,2); + appendOPR_SSRC(layout.SSRC1,true,false,2); + appendOPR_SSRC_SPECIAL_SCC(253,false,true,1,true); + break; + } + } + + void InstructionDecoder_amdgpu_gfx908::finalizeENC_SOPKOperands() + { + layout_ENC_SOPK & layout = insn_layout.ENC_SOPK; + switch (layout.OP) { + case 0: case 17: // S_MOVK_I32,S_GETREG_B32, + appendOPR_SDST(layout.SDST,false,true); + appendOPR_SIMM16(layout.SIMM16,true,false); + break; + case 1: // S_CMOVK_I32, + appendOPR_SDST(layout.SDST,true,true); + appendOPR_SIMM16(layout.SIMM16,true,false); + appendOPR_SSRC_SPECIAL_SCC(253,true,false,1,true); + break; + case 2: case 3: case 4: case 5: case 6: // S_CMPK_EQ_I32,S_CMPK_LG_I32,S_CMPK_GT_I32,S_CMPK_GE_I32,S_CMPK_LT_I32, + case 7: case 8: case 9: case 10: case 11: // S_CMPK_LE_I32,S_CMPK_EQ_U32,S_CMPK_LG_U32,S_CMPK_GT_U32,S_CMPK_GE_U32, + case 12: case 13: // S_CMPK_LT_U32,S_CMPK_LE_U32, + appendOPR_SDST(layout.SDST,true,false); + appendOPR_SIMM16(layout.SIMM16,true,false); + appendOPR_SSRC_SPECIAL_SCC(253,false,true,1,true); + break; + case 14: // S_ADDK_I32, + appendOPR_SDST(layout.SDST,true,true); + appendOPR_SIMM16(layout.SIMM16,true,false); + appendOPR_SSRC_SPECIAL_SCC(253,false,true,1,true); + break; + case 15: // S_MULK_I32, + appendOPR_SDST(layout.SDST,true,true); + appendOPR_SIMM16(layout.SIMM16,true,false); + break; + case 16: // S_CBRANCH_I_FORK, + appendOPR_SDST(layout.SDST,true,false,2); + insn_in_progress->appendOperand(decodeOPR_LABEL(layout.SIMM16),true,false); + break; + case 18: // S_SETREG_B32, + appendOPR_SIMM16(layout.SIMM16,false,true); + appendOPR_SDST(layout.SDST,true,false); + break; + case 21: // S_CALL_B64, + appendOPR_SDST(layout.SDST,false,true,2); + insn_in_progress->appendOperand(decodeOPR_LABEL(layout.SIMM16),true,false); + appendOPR_PC(0,false,true,1,true); + appendOPR_PC(0,true,false,1,true); + break; + } + } + + void InstructionDecoder_amdgpu_gfx908::finalizeSOPK_INST_LITERAL_Operands() + { + layout_SOPK_INST_LITERAL_ & layout = insn_layout.SOPK_INST_LITERAL_; + switch (layout.OP) { + case 20: // S_SETREG_IMM32_B32, + appendOPR_SIMM16(layout.SIMM16,false,true); + appendOPR_SIMM32(layout.SIMM32,true,false); + break; + } + } + + void InstructionDecoder_amdgpu_gfx908::finalizeENC_SOPPOperands() + { + layout_ENC_SOPP & layout = insn_layout.ENC_SOPP; + switch (layout.OP) { + case 0: case 11: case 13: case 14: case 15: case 18: // S_NOP,S_SETKILL,S_SETHALT,S_SLEEP,S_SETPRIO,S_TRAP, + case 20: case 21: // S_INCPERFLEVEL,S_DECPERFLEVEL, + appendOPR_SIMM16(layout.SIMM16,true,false); + break; + case 1: case 3: case 10: case 19: case 27: // S_ENDPGM,S_WAKEUP,S_BARRIER,S_ICACHE_INV,S_ENDPGM_SAVED, + case 28: case 30: // S_SET_GPR_IDX_OFF,S_ENDPGM_ORDERED_PS_DONE, + break; + case 2: // S_BRANCH, + setBranch(); + makeBranchTarget(isCall,isConditional,layout.SIMM16); + break; + case 4: case 5: // S_CBRANCH_SCC0,S_CBRANCH_SCC1, + setBranch(); + setConditionalBranch(); + makeBranchTarget(isCall,isConditional,layout.SIMM16); + appendOPR_SSRC_SPECIAL_SCC(253,true,false,1,true); + break; + case 6: case 7: // S_CBRANCH_VCCZ,S_CBRANCH_VCCNZ, + setBranch(); + setConditionalBranch(); + makeBranchTarget(isCall,isConditional,layout.SIMM16); + appendOPR_VCC(0,true,false,1,true); + break; + case 8: case 9: // S_CBRANCH_EXECZ,S_CBRANCH_EXECNZ, + setBranch(); + setConditionalBranch(); + makeBranchTarget(isCall,isConditional,layout.SIMM16); + appendOPR_SDST_EXEC(126,true,false,1,true); + break; + case 12: // S_WAITCNT, + { + uint32_t vmcnt = ((0x3& (layout.SIMM16 >>14))<<4) | (layout.SIMM16 & 0xf); + uint32_t expcnt = ((layout.SIMM16>>4) & 0x7); + uint32_t lgkmcnt = ((layout.SIMM16>>8) & 0xf); + if (vmcnt != 0x3f) + { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::vmcnt,0,32),false,true); + insn_in_progress->appendOperand(Immediate::makeImmediate(Result(u32,vmcnt)),false,false); + } + if (expcnt != 0x7) + { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::expcnt,0,32),false,true); + insn_in_progress->appendOperand(Immediate::makeImmediate(Result(u32,expcnt)),false,false); + } + if (lgkmcnt != 0xf) + { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx908::lgkmcnt,0,32),false,true); + insn_in_progress->appendOperand(Immediate::makeImmediate(Result(u32,lgkmcnt)),false,false); + } + } + break; + case 16: case 17: // S_SENDMSG,S_SENDMSGHALT, + appendOPR_SIMM16(layout.SIMM16,true,false); + appendOPR_SDST_M0(124,true,false,1,true); + break; + case 22: // S_TTRACEDATA, + appendOPR_SDST_M0(124,true,false,1,true); + break; + case 23: case 24: case 25: // S_CBRANCH_CDBGSYS,S_CBRANCH_CDBGUSER,S_CBRANCH_CDBGSYS_OR_USER, + case 26: // S_CBRANCH_CDBGSYS_AND_USER, + insn_in_progress->appendOperand(decodeOPR_LABEL(layout.SIMM16),true,false); + break; + case 29: // S_SET_GPR_IDX_MODE, + appendOPR_SIMM16(layout.SIMM16,true,false); + appendOPR_SDST_M0(124,false,true,1,true); + appendOPR_SDST_M0(124,true,false,1,true); + break; + } + } + + void InstructionDecoder_amdgpu_gfx908::finalizeENC_VINTRPOperands() + { + layout_ENC_VINTRP & layout = insn_layout.ENC_VINTRP; + switch (layout.OP) { + case 0: // V_INTERP_P1_F32, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_VGPR(layout.VSRC,true,false); + appendOPR_ATTR(layout.ATTR,true,false); + appendOPR_SDST_M0(124,true,false,1,true); + break; + case 1: // V_INTERP_P2_F32, + appendOPR_VGPR(layout.VDST,true,true); + appendOPR_VGPR(layout.VSRC,true,false); + appendOPR_ATTR(layout.ATTR,true,false); + appendOPR_SDST_M0(124,true,false,1,true); + break; + case 2: // V_INTERP_MOV_F32, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_PARAM(layout.VSRC,true,false); + appendOPR_ATTR(layout.ATTR,true,false); + appendOPR_SDST_M0(124,true,false,1,true); + break; + } + } + + void InstructionDecoder_amdgpu_gfx908::finalizeENC_VOP3Operands() + { + layout_ENC_VOP3 & layout = insn_layout.ENC_VOP3; + switch (layout.OP) { + case 624: // V_INTERP_P1_F32, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_SRC_VGPR(layout.SRC1,true,false); + appendOPR_ATTR(layout.SRC0,true,false); + appendOPR_SDST_M0(124,true,false,1,true); + break; + case 625: // V_INTERP_P2_F32, + appendOPR_VGPR(layout.VDST,true,true); + appendOPR_SRC_VGPR(layout.SRC1,true,false); + appendOPR_ATTR(layout.SRC0,true,false); + appendOPR_SDST_M0(124,true,false,1,true); + break; + case 626: // V_INTERP_MOV_F32, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_PARAM(layout.SRC1,true,false); + appendOPR_ATTR(layout.SRC0,true,false); + appendOPR_SDST_M0(124,true,false,1,true); + break; + case 320: case 373: // V_NOP,V_CLREXCP, + break; + case 321: case 325: case 326: case 327: // V_MOV_B32,V_CVT_F32_I32,V_CVT_F32_U32,V_CVT_U32_F32, + case 328: case 330: case 331: case 332: // V_CVT_I32_F32,V_CVT_F16_F32,V_CVT_F32_F16,V_CVT_RPI_I32_F32, + case 333: case 334: case 337: case 338: // V_CVT_FLR_I32_F32,V_CVT_OFF_F32_I4,V_CVT_F32_UBYTE0,V_CVT_F32_UBYTE1, + case 339: case 340: case 347: case 348: // V_CVT_F32_UBYTE2,V_CVT_F32_UBYTE3,V_FRACT_F32,V_TRUNC_F32, + case 349: case 350: case 351: case 352: case 353: // V_CEIL_F32,V_RNDNE_F32,V_FLOOR_F32,V_EXP_F32,V_LOG_F32, + case 354: case 355: case 356: case 359: case 361: // V_RCP_F32,V_RCP_IFLAG_F32,V_RSQ_F32,V_SQRT_F32,V_SIN_F32, + case 362: case 363: case 364: case 365: case 366: // V_COS_F32,V_NOT_B32,V_BFREV_B32,V_FFBH_U32,V_FFBL_B32, + case 367: case 371: case 372: // V_FFBH_I32,V_FREXP_EXP_I32_F32,V_FREXP_MANT_F32, + case 375: case 377: case 378: case 379: // V_SCREEN_PARTITION_4SE_B32,V_CVT_F16_U16,V_CVT_F16_I16,V_CVT_U16_F16, + case 380: case 381: case 382: case 383: case 384: // V_CVT_I16_F16,V_RCP_F16,V_SQRT_F16,V_RSQ_F16,V_LOG_F16, + case 385: case 386: case 387: case 388: // V_EXP_F16,V_FREXP_MANT_F16,V_FREXP_EXP_I16_F16,V_FLOOR_F16, + case 389: case 390: case 391: case 392: case 393: // V_CEIL_F16,V_TRUNC_F16,V_RNDNE_F16,V_FRACT_F16,V_SIN_F16, + case 394: case 395: case 396: case 397: // V_COS_F16,V_EXP_LEGACY_F32,V_LOG_LEGACY_F32,V_CVT_NORM_I16_F16, + case 398: case 399: // V_CVT_NORM_U16_F16,V_SAT_PK_U8_I16, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_SRC_NOLIT(layout.SRC0,true,false); + break; + case 322: // V_READFIRSTLANE_B32, + appendOPR_SREG_NOVCC(layout.VDST,false,true); + appendOPR_VGPR_OR_LDS(layout.SRC0,true,false); + break; + case 323: case 335: case 341: case 368: // V_CVT_I32_F64,V_CVT_F32_F64,V_CVT_U32_F64,V_FREXP_EXP_I32_F64, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_SRC_NOLIT(layout.SRC0,true,false,2); + break; + case 324: case 336: case 342: // V_CVT_F64_I32,V_CVT_F64_F32,V_CVT_F64_U32, + appendOPR_VGPR(layout.VDST,false,true,2); + appendOPR_SRC_NOLIT(layout.SRC0,true,false); + break; + case 343: case 344: case 345: case 346: case 357: // V_TRUNC_F64,V_CEIL_F64,V_RNDNE_F64,V_FLOOR_F64,V_RCP_F64, + case 358: case 360: case 369: case 370: // V_RSQ_F64,V_SQRT_F64,V_FREXP_MANT_F64,V_FRACT_F64, + appendOPR_VGPR(layout.VDST,false,true,2); + appendOPR_SRC_NOLIT(layout.SRC0,true,false,2); + break; + case 401: // V_SWAP_B32, + appendOPR_VGPR(layout.VDST,true,true); + appendOPR_SRC_VGPR(layout.SRC0,true,true); + break; + case 256: // V_CNDMASK_B32, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_SRC_NOLIT(layout.SRC0,true,false); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false); + appendOPR_SREG(layout.SRC2,true,false,2); + break; + case 257: case 258: case 259: case 260: case 261: // V_ADD_F32,V_SUB_F32,V_SUBREV_F32,V_MUL_LEGACY_F32,V_MUL_F32, + case 262: case 263: case 264: case 265: // V_MUL_I32_I24,V_MUL_HI_I32_I24,V_MUL_U32_U24,V_MUL_HI_U32_U24, + case 266: case 267: case 268: case 269: case 270: // V_MIN_F32,V_MAX_F32,V_MIN_I32,V_MAX_I32,V_MIN_U32, + case 271: case 275: case 276: case 277: case 287: // V_MAX_U32,V_AND_B32,V_OR_B32,V_XOR_B32,V_ADD_F16, + case 288: case 290: case 294: case 295: case 297: // V_SUB_F16,V_MUL_F16,V_ADD_U16,V_SUB_U16,V_MUL_LO_U16, + case 301: case 302: case 303: case 304: case 305: // V_MAX_F16,V_MIN_F16,V_MAX_U16,V_MAX_I16,V_MIN_U16, + case 306: case 307: case 308: case 309: case 317: // V_MIN_I16,V_LDEXP_F16,V_ADD_U32,V_SUB_U32,V_XNOR_B32, + case 645: case 646: case 647: case 648: // V_MUL_LO_U32,V_MUL_HI_U32,V_MUL_HI_I32,V_LDEXP_F32, + case 651: case 652: case 653: case 659: // V_BCNT_U32_B32,V_MBCNT_LO_U32_B32,V_MBCNT_HI_U32_B32,V_BFM_B32, + case 660: case 661: case 662: // V_CVT_PKNORM_I16_F32,V_CVT_PKNORM_U16_F32,V_CVT_PKRTZ_F16_F32, + case 663: case 664: case 665: // V_CVT_PK_U16_U32,V_CVT_PK_I16_I32,V_CVT_PKNORM_I16_F16, + case 666: case 668: case 669: case 670: case 671: // V_CVT_PKNORM_U16_F16,V_ADD_I32,V_SUB_I32,V_ADD_I16,V_SUB_I16, + case 672: // V_PACK_B32_F16, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_SRC_NOLIT(layout.SRC0,true,false); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false); + break; + case 272: case 273: case 274: case 289: // V_LSHRREV_B32,V_ASHRREV_I32,V_LSHLREV_B32,V_SUBREV_F16, + case 296: case 298: case 299: case 300: // V_SUBREV_U16,V_LSHLREV_B16,V_LSHRREV_B16,V_ASHRREV_I16, + case 310: // V_SUBREV_U32, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_SRC_SIMPLE(layout.SRC0,true,false); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false); + break; + case 278: case 291: case 311: case 312: // V_MAC_F32,V_MAC_F16,V_DOT2C_F32_F16,V_DOT2C_I32_I16, + case 313: case 314: case 315: case 316: // V_DOT4C_I32_I8,V_DOT8C_I32_I4,V_FMAC_F32,V_PK_FMAC_F16, + case 496: // V_CVT_PKACCUM_U8_F32, + appendOPR_VGPR(layout.VDST,true,true); + appendOPR_SRC_NOLIT(layout.SRC0,true,false); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false); + break; + case 448: case 449: case 450: case 451: // V_MAD_LEGACY_F32,V_MAD_F32,V_MAD_I32_I24,V_MAD_U32_U24, + case 452: case 453: case 454: case 455: case 456: // V_CUBEID_F32,V_CUBESC_F32,V_CUBETC_F32,V_CUBEMA_F32,V_BFE_U32, + case 457: case 458: case 459: case 461: case 462: // V_BFE_I32,V_BFI_B32,V_FMA_F32,V_LERP_U8,V_ALIGNBIT_B32, + case 463: case 464: case 465: case 466: case 467: // V_ALIGNBYTE_B32,V_MIN3_F32,V_MIN3_I32,V_MIN3_U32,V_MAX3_F32, + case 468: case 469: case 470: case 471: case 472: // V_MAX3_I32,V_MAX3_U32,V_MED3_F32,V_MED3_I32,V_MED3_U32, + case 473: case 474: case 475: case 476: case 477: // V_SAD_U8,V_SAD_HI_U8,V_SAD_U16,V_SAD_U32,V_CVT_PK_U8_F32, + case 478: case 484: case 490: case 491: // V_DIV_FIXUP_F32,V_MSAD_U8,V_MAD_LEGACY_F16,V_MAD_LEGACY_U16, + case 492: case 493: case 494: case 495: // V_MAD_LEGACY_I16,V_PERM_B32,V_FMA_LEGACY_F16,V_DIV_FIXUP_LEGACY_F16, + case 497: case 498: case 499: case 500: case 501: // V_MAD_U32_U16,V_MAD_I32_I16,V_XAD_U32,V_MIN3_F16,V_MIN3_I16, + case 502: case 503: case 504: case 505: case 506: // V_MIN3_U16,V_MAX3_F16,V_MAX3_I16,V_MAX3_U16,V_MED3_F16, + case 507: case 508: case 509: case 510: case 511: // V_MED3_I16,V_MED3_U16,V_LSHL_ADD_U32,V_ADD_LSHL_U32,V_ADD3_U32, + case 512: case 513: case 514: case 515: case 516: // V_LSHL_OR_B32,V_AND_OR_B32,V_OR3_B32,V_MAD_F16,V_MAD_U16, + case 517: case 518: case 519: // V_MAD_I16,V_FMA_F16,V_DIV_FIXUP_F16, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_SRC_NOLIT(layout.SRC0,true,false); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false); + appendOPR_SRC_SIMPLE(layout.SRC2,true,false); + break; + case 460: case 479: // V_FMA_F64,V_DIV_FIXUP_F64, + appendOPR_VGPR(layout.VDST,false,true,2); + appendOPR_SRC_NOLIT(layout.SRC0,true,false,2); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false,2); + appendOPR_SRC_SIMPLE(layout.SRC2,true,false,2); + break; + case 482: // V_DIV_FMAS_F32, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_SRC_NOLIT(layout.SRC0,true,false); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false); + appendOPR_SRC_SIMPLE(layout.SRC2,true,false); + appendOPR_VCC(0,true,false,1,true); + break; + case 483: // V_DIV_FMAS_F64, + appendOPR_VGPR(layout.VDST,false,true,2); + appendOPR_SRC_NOLIT(layout.SRC0,true,false,2); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false,2); + appendOPR_SRC_SIMPLE(layout.SRC2,true,false,2); + appendOPR_VCC(0,true,false,1,true); + break; + case 485: case 486: // V_QSAD_PK_U16_U8,V_MQSAD_PK_U16_U8, + appendOPR_VGPR(layout.VDST,false,true,2); + appendOPR_SRC_NOLIT(layout.SRC0,true,false,2); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false); + appendOPR_SRC_SIMPLE(layout.SRC2,true,false,2); + break; + case 487: // V_MQSAD_U32_U8, + appendOPR_VGPR(layout.VDST,false,true,4); + appendOPR_SRC_NOLIT(layout.SRC0,true,false,2); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false); + appendOPR_SRC_VGPR(layout.SRC2,true,false,4); + break; + case 628: // V_INTERP_P1LL_F16, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_SRC_VGPR(layout.SRC1,true,false); + appendOPR_ATTR(layout.SRC0,true,false); + break; + case 629: case 630: case 631: // V_INTERP_P1LV_F16,V_INTERP_P2_LEGACY_F16,V_INTERP_P2_F16, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_SRC_VGPR(layout.SRC1,true,false); + appendOPR_ATTR(layout.SRC0,true,false); + appendOPR_SRC_VGPR(layout.SRC2,true,false); + break; + case 640: case 641: case 642: case 643: // V_ADD_F64,V_MUL_F64,V_MIN_F64,V_MAX_F64, + appendOPR_VGPR(layout.VDST,false,true,2); + appendOPR_SRC_NOLIT(layout.SRC0,true,false,2); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false,2); + break; + case 644: case 658: // V_LDEXP_F64,V_TRIG_PREOP_F64, + appendOPR_VGPR(layout.VDST,false,true,2); + appendOPR_SRC_NOLIT(layout.SRC0,true,false,2); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false); + break; + case 649: // V_READLANE_B32, + appendOPR_SREG_NOVCC(layout.VDST,false,true); + appendOPR_VGPR_OR_LDS(layout.SRC0,true,false); + appendOPR_SSRC_LANESEL(layout.SRC1,true,false); + break; + case 650: // V_WRITELANE_B32, + appendOPR_VGPR(layout.VDST,true,true); + appendOPR_SSRC_NOLIT(layout.SRC0,true,false); + appendOPR_SSRC_LANESEL(layout.SRC1,true,false); + break; + case 655: case 656: case 657: // V_LSHLREV_B64,V_LSHRREV_B64,V_ASHRREV_I64, + appendOPR_VGPR(layout.VDST,false,true,2); + appendOPR_SRC_SIMPLE(layout.SRC0,true,false); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false,2); + break; + case 16: case 20: case 32: case 33: // V_CMP_CLASS_F32,V_CMP_CLASS_F16,V_CMP_F_F16,V_CMP_LT_F16, + case 34: case 35: case 36: case 37: case 38: // V_CMP_EQ_F16,V_CMP_LE_F16,V_CMP_GT_F16,V_CMP_LG_F16,V_CMP_GE_F16, + case 39: case 40: case 41: case 42: case 43: // V_CMP_O_F16,V_CMP_U_F16,V_CMP_NGE_F16,V_CMP_NLG_F16,V_CMP_NGT_F16, + case 44: case 45: case 46: case 47: case 64: // V_CMP_NLE_F16,V_CMP_NEQ_F16,V_CMP_NLT_F16,V_CMP_TRU_F16,V_CMP_F_F32, + case 65: case 66: case 67: case 68: case 69: // V_CMP_LT_F32,V_CMP_EQ_F32,V_CMP_LE_F32,V_CMP_GT_F32,V_CMP_LG_F32, + case 70: case 71: case 72: case 73: case 74: // V_CMP_GE_F32,V_CMP_O_F32,V_CMP_U_F32,V_CMP_NGE_F32,V_CMP_NLG_F32, + case 75: case 76: case 77: case 78: // V_CMP_NGT_F32,V_CMP_NLE_F32,V_CMP_NEQ_F32,V_CMP_NLT_F32, + case 79: case 160: case 161: case 162: // V_CMP_TRU_F32,V_CMP_F_I16,V_CMP_LT_I16,V_CMP_EQ_I16, + case 163: case 164: case 165: case 166: // V_CMP_LE_I16,V_CMP_GT_I16,V_CMP_NE_I16,V_CMP_GE_I16, + case 167: case 168: case 169: case 170: case 171: // V_CMP_T_I16,V_CMP_F_U16,V_CMP_LT_U16,V_CMP_EQ_U16,V_CMP_LE_U16, + case 172: case 173: case 174: case 175: case 192: // V_CMP_GT_U16,V_CMP_NE_U16,V_CMP_GE_U16,V_CMP_T_U16,V_CMP_F_I32, + case 193: case 194: case 195: case 196: // V_CMP_LT_I32,V_CMP_EQ_I32,V_CMP_LE_I32,V_CMP_GT_I32, + case 197: case 198: case 199: case 200: case 201: // V_CMP_NE_I32,V_CMP_GE_I32,V_CMP_T_I32,V_CMP_F_U32,V_CMP_LT_U32, + case 202: case 203: case 204: case 205: // V_CMP_EQ_U32,V_CMP_LE_U32,V_CMP_GT_U32,V_CMP_NE_U32, + case 206: case 207: // V_CMP_GE_U32,V_CMP_T_U32, + appendOPR_SREG(layout.VDST,false,true,2); + appendOPR_SRC_NOLIT(layout.SRC0,true,false); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false); + break; + case 17: case 21: case 48: case 49: // V_CMPX_CLASS_F32,V_CMPX_CLASS_F16,V_CMPX_F_F16,V_CMPX_LT_F16, + case 50: case 51: case 52: case 53: // V_CMPX_EQ_F16,V_CMPX_LE_F16,V_CMPX_GT_F16,V_CMPX_LG_F16, + case 54: case 55: case 56: case 57: // V_CMPX_GE_F16,V_CMPX_O_F16,V_CMPX_U_F16,V_CMPX_NGE_F16, + case 58: case 59: case 60: case 61: // V_CMPX_NLG_F16,V_CMPX_NGT_F16,V_CMPX_NLE_F16,V_CMPX_NEQ_F16, + case 62: case 63: case 80: case 81: // V_CMPX_NLT_F16,V_CMPX_TRU_F16,V_CMPX_F_F32,V_CMPX_LT_F32, + case 82: case 83: case 84: case 85: // V_CMPX_EQ_F32,V_CMPX_LE_F32,V_CMPX_GT_F32,V_CMPX_LG_F32, + case 86: case 87: case 88: case 89: // V_CMPX_GE_F32,V_CMPX_O_F32,V_CMPX_U_F32,V_CMPX_NGE_F32, + case 90: case 91: case 92: case 93: // V_CMPX_NLG_F32,V_CMPX_NGT_F32,V_CMPX_NLE_F32,V_CMPX_NEQ_F32, + case 94: case 95: case 176: case 177: // V_CMPX_NLT_F32,V_CMPX_TRU_F32,V_CMPX_F_I16,V_CMPX_LT_I16, + case 178: case 179: case 180: case 181: // V_CMPX_EQ_I16,V_CMPX_LE_I16,V_CMPX_GT_I16,V_CMPX_NE_I16, + case 182: case 183: case 184: case 185: // V_CMPX_GE_I16,V_CMPX_T_I16,V_CMPX_F_U16,V_CMPX_LT_U16, + case 186: case 187: case 188: case 189: // V_CMPX_EQ_U16,V_CMPX_LE_U16,V_CMPX_GT_U16,V_CMPX_NE_U16, + case 190: case 191: case 208: case 209: // V_CMPX_GE_U16,V_CMPX_T_U16,V_CMPX_F_I32,V_CMPX_LT_I32, + case 210: case 211: case 212: case 213: // V_CMPX_EQ_I32,V_CMPX_LE_I32,V_CMPX_GT_I32,V_CMPX_NE_I32, + case 214: case 215: case 216: case 217: // V_CMPX_GE_I32,V_CMPX_T_I32,V_CMPX_F_U32,V_CMPX_LT_U32, + case 218: case 219: case 220: case 221: // V_CMPX_EQ_U32,V_CMPX_LE_U32,V_CMPX_GT_U32,V_CMPX_NE_U32, + case 222: case 223: // V_CMPX_GE_U32,V_CMPX_T_U32, + appendOPR_SDST(layout.VDST,false,true,2); + appendOPR_SRC_NOLIT(layout.SRC0,true,false); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false); + appendOPR_SDST_EXEC(126,false,true,1,true); + break; + case 18: // V_CMP_CLASS_F64, + appendOPR_SREG(layout.VDST,false,true,2); + appendOPR_SRC_NOLIT(layout.SRC0,true,false,2); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false); + break; + case 19: // V_CMPX_CLASS_F64, + appendOPR_SDST(layout.VDST,false,true,2); + appendOPR_SRC_NOLIT(layout.SRC0,true,false,2); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false); + appendOPR_SDST_EXEC(126,false,true,1,true); + break; + case 96: case 97: case 98: case 99: case 100: // V_CMP_F_F64,V_CMP_LT_F64,V_CMP_EQ_F64,V_CMP_LE_F64,V_CMP_GT_F64, + case 101: case 102: case 103: case 104: // V_CMP_LG_F64,V_CMP_GE_F64,V_CMP_O_F64,V_CMP_U_F64, + case 105: case 106: case 107: case 108: // V_CMP_NGE_F64,V_CMP_NLG_F64,V_CMP_NGT_F64,V_CMP_NLE_F64, + case 109: case 110: case 111: case 224: // V_CMP_NEQ_F64,V_CMP_NLT_F64,V_CMP_TRU_F64,V_CMP_F_I64, + case 225: case 226: case 227: case 228: // V_CMP_LT_I64,V_CMP_EQ_I64,V_CMP_LE_I64,V_CMP_GT_I64, + case 229: case 230: case 231: case 232: case 233: // V_CMP_NE_I64,V_CMP_GE_I64,V_CMP_T_I64,V_CMP_F_U64,V_CMP_LT_U64, + case 234: case 235: case 236: case 237: // V_CMP_EQ_U64,V_CMP_LE_U64,V_CMP_GT_U64,V_CMP_NE_U64, + case 238: case 239: // V_CMP_GE_U64,V_CMP_T_U64, + appendOPR_SREG(layout.VDST,false,true,2); + appendOPR_SRC_NOLIT(layout.SRC0,true,false,2); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false,2); + break; + case 112: case 113: case 114: case 115: // V_CMPX_F_F64,V_CMPX_LT_F64,V_CMPX_EQ_F64,V_CMPX_LE_F64, + case 116: case 117: case 118: case 119: // V_CMPX_GT_F64,V_CMPX_LG_F64,V_CMPX_GE_F64,V_CMPX_O_F64, + case 120: case 121: case 122: case 123: // V_CMPX_U_F64,V_CMPX_NGE_F64,V_CMPX_NLG_F64,V_CMPX_NGT_F64, + case 124: case 125: case 126: case 127: // V_CMPX_NLE_F64,V_CMPX_NEQ_F64,V_CMPX_NLT_F64,V_CMPX_TRU_F64, + case 240: case 241: case 242: case 243: // V_CMPX_F_I64,V_CMPX_LT_I64,V_CMPX_EQ_I64,V_CMPX_LE_I64, + case 244: case 245: case 246: case 247: // V_CMPX_GT_I64,V_CMPX_NE_I64,V_CMPX_GE_I64,V_CMPX_T_I64, + case 248: case 249: case 250: case 251: // V_CMPX_F_U64,V_CMPX_LT_U64,V_CMPX_EQ_U64,V_CMPX_LE_U64, + case 252: case 253: case 254: case 255: // V_CMPX_GT_U64,V_CMPX_NE_U64,V_CMPX_GE_U64,V_CMPX_T_U64, + appendOPR_SDST(layout.VDST,false,true,2); + appendOPR_SRC_NOLIT(layout.SRC0,true,false,2); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false,2); + appendOPR_SDST_EXEC(126,false,true,1,true); + break; + } + } + + void InstructionDecoder_amdgpu_gfx908::finalizeENC_VOP1Operands() + { + layout_ENC_VOP1 & layout = insn_layout.ENC_VOP1; + switch (layout.OP) { + case 0: case 53: // V_NOP,V_CLREXCP, + break; + case 1: case 5: case 6: case 7: case 8: // V_MOV_B32,V_CVT_F32_I32,V_CVT_F32_U32,V_CVT_U32_F32,V_CVT_I32_F32, + case 10: case 11: case 12: case 13: // V_CVT_F16_F32,V_CVT_F32_F16,V_CVT_RPI_I32_F32,V_CVT_FLR_I32_F32, + case 14: case 17: case 18: case 19: // V_CVT_OFF_F32_I4,V_CVT_F32_UBYTE0,V_CVT_F32_UBYTE1,V_CVT_F32_UBYTE2, + case 20: case 27: case 28: case 29: case 30: // V_CVT_F32_UBYTE3,V_FRACT_F32,V_TRUNC_F32,V_CEIL_F32,V_RNDNE_F32, + case 31: case 32: case 33: case 34: case 35: // V_FLOOR_F32,V_EXP_F32,V_LOG_F32,V_RCP_F32,V_RCP_IFLAG_F32, + case 36: case 39: case 41: case 42: case 43: // V_RSQ_F32,V_SQRT_F32,V_SIN_F32,V_COS_F32,V_NOT_B32, + case 44: case 45: case 46: case 47: case 51: // V_BFREV_B32,V_FFBH_U32,V_FFBL_B32,V_FFBH_I32,V_FREXP_EXP_I32_F32, + case 52: case 55: case 57: case 58: // V_FREXP_MANT_F32,V_SCREEN_PARTITION_4SE_B32,V_CVT_F16_U16,V_CVT_F16_I16, + case 59: case 60: case 61: case 62: case 63: // V_CVT_U16_F16,V_CVT_I16_F16,V_RCP_F16,V_SQRT_F16,V_RSQ_F16, + case 64: case 65: case 66: case 67: // V_LOG_F16,V_EXP_F16,V_FREXP_MANT_F16,V_FREXP_EXP_I16_F16, + case 68: case 69: case 70: case 71: case 72: // V_FLOOR_F16,V_CEIL_F16,V_TRUNC_F16,V_RNDNE_F16,V_FRACT_F16, + case 73: case 74: case 75: case 76: // V_SIN_F16,V_COS_F16,V_EXP_LEGACY_F32,V_LOG_LEGACY_F32, + case 77: case 78: case 79: // V_CVT_NORM_I16_F16,V_CVT_NORM_U16_F16,V_SAT_PK_U8_I16, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_SRC(layout.SRC0,true,false); + break; + case 2: // V_READFIRSTLANE_B32, + appendOPR_SREG_NOVCC(layout.VDST,false,true); + appendOPR_VGPR_OR_LDS(layout.SRC0,true,false); + break; + case 3: case 15: case 21: case 48: // V_CVT_I32_F64,V_CVT_F32_F64,V_CVT_U32_F64,V_FREXP_EXP_I32_F64, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_SRC(layout.SRC0,true,false,2); + break; + case 4: case 16: case 22: // V_CVT_F64_I32,V_CVT_F64_F32,V_CVT_F64_U32, + appendOPR_VGPR(layout.VDST,false,true,2); + appendOPR_SRC(layout.SRC0,true,false); + break; + case 23: case 24: case 25: case 26: case 37: // V_TRUNC_F64,V_CEIL_F64,V_RNDNE_F64,V_FLOOR_F64,V_RCP_F64, + case 38: case 40: case 49: case 50: // V_RSQ_F64,V_SQRT_F64,V_FREXP_MANT_F64,V_FRACT_F64, + appendOPR_VGPR(layout.VDST,false,true,2); + appendOPR_SRC(layout.SRC0,true,false,2); + break; + case 81: // V_SWAP_B32, + appendOPR_VGPR(layout.VDST,true,true); + appendOPR_SRC_VGPR(layout.SRC0,true,true); + break; + } + } + + void InstructionDecoder_amdgpu_gfx908::finalizeENC_VOP2Operands() + { + layout_ENC_VOP2 & layout = insn_layout.ENC_VOP2; + switch (layout.OP) { + case 0: // V_CNDMASK_B32, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_SRC(layout.SRC0,true,false); + appendOPR_VGPR(layout.VSRC1,true,false); + appendOPR_VCC(0,true,false,2); + break; + case 1: case 2: case 3: case 4: case 5: // V_ADD_F32,V_SUB_F32,V_SUBREV_F32,V_MUL_LEGACY_F32,V_MUL_F32, + case 6: case 7: case 8: case 9: case 10: // V_MUL_I32_I24,V_MUL_HI_I32_I24,V_MUL_U32_U24,V_MUL_HI_U32_U24,V_MIN_F32, + case 11: case 12: case 13: case 14: case 15: // V_MAX_F32,V_MIN_I32,V_MAX_I32,V_MIN_U32,V_MAX_U32, + case 19: case 20: case 21: case 31: case 32: // V_AND_B32,V_OR_B32,V_XOR_B32,V_ADD_F16,V_SUB_F16, + case 34: case 38: case 39: case 41: case 45: // V_MUL_F16,V_ADD_U16,V_SUB_U16,V_MUL_LO_U16,V_MAX_F16, + case 46: case 47: case 48: case 49: case 50: // V_MIN_F16,V_MAX_U16,V_MAX_I16,V_MIN_U16,V_MIN_I16, + case 51: case 52: case 53: case 61: // V_LDEXP_F16,V_ADD_U32,V_SUB_U32,V_XNOR_B32, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_SRC(layout.SRC0,true,false); + appendOPR_VGPR(layout.VSRC1,true,false); + break; + case 16: case 17: case 18: case 33: case 40: // V_LSHRREV_B32,V_ASHRREV_I32,V_LSHLREV_B32,V_SUBREV_F16,V_SUBREV_U16, + case 42: case 43: case 44: case 54: // V_LSHLREV_B16,V_LSHRREV_B16,V_ASHRREV_I16,V_SUBREV_U32, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_SRC_NOLDS(layout.SRC0,true,false); + appendOPR_VGPR(layout.VSRC1,true,false); + break; + case 22: case 35: case 55: case 56: case 57: // V_MAC_F32,V_MAC_F16,V_DOT2C_F32_F16,V_DOT2C_I32_I16,V_DOT4C_I32_I8, + case 58: case 59: case 60: // V_DOT8C_I32_I4,V_FMAC_F32,V_PK_FMAC_F16, + appendOPR_VGPR(layout.VDST,true,true); + appendOPR_SRC(layout.SRC0,true,false); + appendOPR_VGPR(layout.VSRC1,true,false); + break; + case 25: case 26: // V_ADD_CO_U32,V_SUB_CO_U32, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_VCC(0,false,true,2); + appendOPR_SRC(layout.SRC0,true,false); + appendOPR_VGPR(layout.VSRC1,true,false); + break; + case 27: // V_SUBREV_CO_U32, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_VCC(0,false,true,2); + appendOPR_SRC_NOLDS(layout.SRC0,true,false); + appendOPR_VGPR(layout.VSRC1,true,false); + break; + case 28: case 29: // V_ADDC_CO_U32,V_SUBB_CO_U32, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_VCC(0,false,true,2); + appendOPR_SRC(layout.SRC0,true,false); + appendOPR_VGPR(layout.VSRC1,true,false); + appendOPR_VCC(0,true,false,2); + break; + case 30: // V_SUBBREV_CO_U32, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_VCC(0,false,true,2); + appendOPR_SRC_NOLDS(layout.SRC0,true,false); + appendOPR_VGPR(layout.VSRC1,true,false); + appendOPR_VCC(0,true,false,2); + break; + } + } + + void InstructionDecoder_amdgpu_gfx908::finalizeENC_VOP2_LITERALOperands() + { + layout_ENC_VOP2_LITERAL & layout = insn_layout.ENC_VOP2_LITERAL; + switch (layout.OP) { + case 23: case 36: // V_MADMK_F32,V_MADMK_F16, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_SRC(layout.SRC0,true,false); + appendOPR_SIMM32(layout.SIMM32,true,false); + appendOPR_VGPR(layout.VSRC1,true,false); + break; + case 24: case 37: // V_MADAK_F32,V_MADAK_F16, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_SRC(layout.SRC0,true,false); + appendOPR_VGPR(layout.VSRC1,true,false); + appendOPR_SIMM32(layout.SIMM32,true,false); + break; + } + } + + void InstructionDecoder_amdgpu_gfx908::finalizeENC_VOP3BOperands() + { + layout_ENC_VOP3B & layout = insn_layout.ENC_VOP3B; + switch (layout.OP) { + case 281: case 282: // V_ADD_CO_U32,V_SUB_CO_U32, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_SREG(layout.SDST,false,true,2); + appendOPR_SRC_NOLIT(layout.SRC0,true,false); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false); + break; + case 283: // V_SUBREV_CO_U32, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_SREG(layout.SDST,false,true,2); + appendOPR_SRC_SIMPLE(layout.SRC0,true,false); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false); + break; + case 284: case 285: // V_ADDC_CO_U32,V_SUBB_CO_U32, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_SREG(layout.SDST,false,true,2); + appendOPR_SRC_NOLIT(layout.SRC0,true,false); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false); + appendOPR_SREG(layout.SRC2,true,false,2); + break; + case 286: // V_SUBBREV_CO_U32, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_SREG(layout.SDST,false,true,2); + appendOPR_SRC_SIMPLE(layout.SRC0,true,false); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false); + appendOPR_SREG(layout.SRC2,true,false,2); + break; + case 480: // V_DIV_SCALE_F32, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_VCC(layout.SDST,false,true,2); + appendOPR_SRC_NOLIT(layout.SRC0,true,false); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false); + appendOPR_SRC_SIMPLE(layout.SRC2,true,false); + break; + case 481: // V_DIV_SCALE_F64, + appendOPR_VGPR(layout.VDST,false,true,2); + appendOPR_VCC(layout.SDST,false,true,2); + appendOPR_SRC_NOLIT(layout.SRC0,true,false,2); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false,2); + appendOPR_SRC_SIMPLE(layout.SRC2,true,false,2); + break; + case 488: case 489: // V_MAD_U64_U32,V_MAD_I64_I32, + appendOPR_VGPR(layout.VDST,false,true,2); + appendOPR_SREG(layout.SDST,false,true,2); + appendOPR_SRC_NOLIT(layout.SRC0,true,false); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false); + appendOPR_SRC_SIMPLE(layout.SRC2,true,false,2); + break; + } + } + + void InstructionDecoder_amdgpu_gfx908::finalizeENC_VOP3POperands() + { + layout_ENC_VOP3P & layout = insn_layout.ENC_VOP3P; + switch (layout.OP) { + case 0: case 9: case 14: case 32: case 33: // V_PK_MAD_I16,V_PK_MAD_U16,V_PK_FMA_F16,V_MAD_MIX_F32,V_MAD_MIXLO_F16, + case 34: case 35: case 38: case 39: // V_MAD_MIXHI_F16,V_DOT2_F32_F16,V_DOT2_I32_I16,V_DOT2_U32_U16, + case 40: case 41: case 42: case 43: // V_DOT4_I32_I8,V_DOT4_U32_U8,V_DOT8_I32_I4,V_DOT8_U32_U4, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_SRC_NOLIT(layout.SRC0,true,false); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false); + appendOPR_SRC_SIMPLE(layout.SRC2,true,false); + break; + case 1: case 2: case 3: case 7: case 8: // V_PK_MUL_LO_U16,V_PK_ADD_I16,V_PK_SUB_I16,V_PK_MAX_I16,V_PK_MIN_I16, + case 10: case 11: case 12: case 13: case 15: // V_PK_ADD_U16,V_PK_SUB_U16,V_PK_MAX_U16,V_PK_MIN_U16,V_PK_ADD_F16, + case 16: case 17: case 18: // V_PK_MUL_F16,V_PK_MIN_F16,V_PK_MAX_F16, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_SRC_NOLIT(layout.SRC0,true,false); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false); + break; + case 4: case 5: case 6: // V_PK_LSHLREV_B16,V_PK_LSHRREV_B16,V_PK_ASHRREV_I16, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_SRC_SIMPLE(layout.SRC0,true,false); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false); + break; + case 88: // V_ACCVGPR_READ, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_SRC_ACCVGPR(layout.SRC0,true,false); + break; + case 89: // V_ACCVGPR_WRITE, + appendOPR_ACCVGPR(layout.VDST,false,true); + appendOPR_SRC_NOLIT(layout.SRC0,true,false); + break; + } + } + + void InstructionDecoder_amdgpu_gfx908::finalizeENC_VOP3P_MFMAOperands() + { + layout_ENC_VOP3P_MFMA & layout = insn_layout.ENC_VOP3P_MFMA; + switch (layout.OP) { + case 64: case 80: case 104: // V_MFMA_F32_32X32X1F32,V_MFMA_I32_32X32X4I8,V_MFMA_F32_32X32X2BF16, + appendOPR_ACCVGPR(layout.VDST,false,true,32); + appendOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,true,false); + appendOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,true,false); + appendOPR_SRC_ACCVGPR_OR_CONST(layout.SRC2,true,false,32); + break; + case 65: case 68: case 81: // V_MFMA_F32_16X16X1F32,V_MFMA_F32_32X32X2F32,V_MFMA_I32_16X16X4I8, + case 84: case 105: case 108: // V_MFMA_I32_32X32X8I8,V_MFMA_F32_16X16X2BF16,V_MFMA_F32_32X32X4BF16, + appendOPR_ACCVGPR(layout.VDST,false,true,16); + appendOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,true,false); + appendOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,true,false); + appendOPR_SRC_ACCVGPR_OR_CONST(layout.SRC2,true,false,16); + break; + case 66: case 69: case 82: // V_MFMA_F32_4X4X1F32,V_MFMA_F32_16X16X4F32,V_MFMA_I32_4X4X4I8, + case 85: case 107: case 109: // V_MFMA_I32_16X16X16I8,V_MFMA_F32_4X4X2BF16,V_MFMA_F32_16X16X8BF16, + appendOPR_ACCVGPR(layout.VDST,false,true,4); + appendOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,true,false); + appendOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,true,false); + appendOPR_SRC_ACCVGPR_OR_CONST(layout.SRC2,true,false,4); + break; + case 72: // V_MFMA_F32_32X32X4F16, + appendOPR_ACCVGPR(layout.VDST,false,true,32); + appendOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,true,false,2); + appendOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,true,false,2); + appendOPR_SRC_ACCVGPR_OR_CONST(layout.SRC2,true,false,32); + break; + case 73: case 76: // V_MFMA_F32_16X16X4F16,V_MFMA_F32_32X32X8F16, + appendOPR_ACCVGPR(layout.VDST,false,true,16); + appendOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,true,false,2); + appendOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,true,false,2); + appendOPR_SRC_ACCVGPR_OR_CONST(layout.SRC2,true,false,16); + break; + case 74: case 77: // V_MFMA_F32_4X4X4F16,V_MFMA_F32_16X16X16F16, + appendOPR_ACCVGPR(layout.VDST,false,true,4); + appendOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,true,false,2); + appendOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,true,false,2); + appendOPR_SRC_ACCVGPR_OR_CONST(layout.SRC2,true,false,4); + break; + } + } + + void InstructionDecoder_amdgpu_gfx908::finalizeENC_VOPCOperands() + { + layout_ENC_VOPC & layout = insn_layout.ENC_VOPC; + switch (layout.OP) { + case 16: case 20: case 32: case 33: // V_CMP_CLASS_F32,V_CMP_CLASS_F16,V_CMP_F_F16,V_CMP_LT_F16, + case 34: case 35: case 36: case 37: case 38: // V_CMP_EQ_F16,V_CMP_LE_F16,V_CMP_GT_F16,V_CMP_LG_F16,V_CMP_GE_F16, + case 39: case 40: case 41: case 42: case 43: // V_CMP_O_F16,V_CMP_U_F16,V_CMP_NGE_F16,V_CMP_NLG_F16,V_CMP_NGT_F16, + case 44: case 45: case 46: case 47: case 64: // V_CMP_NLE_F16,V_CMP_NEQ_F16,V_CMP_NLT_F16,V_CMP_TRU_F16,V_CMP_F_F32, + case 65: case 66: case 67: case 68: case 69: // V_CMP_LT_F32,V_CMP_EQ_F32,V_CMP_LE_F32,V_CMP_GT_F32,V_CMP_LG_F32, + case 70: case 71: case 72: case 73: case 74: // V_CMP_GE_F32,V_CMP_O_F32,V_CMP_U_F32,V_CMP_NGE_F32,V_CMP_NLG_F32, + case 75: case 76: case 77: case 78: // V_CMP_NGT_F32,V_CMP_NLE_F32,V_CMP_NEQ_F32,V_CMP_NLT_F32, + case 79: case 160: case 161: case 162: // V_CMP_TRU_F32,V_CMP_F_I16,V_CMP_LT_I16,V_CMP_EQ_I16, + case 163: case 164: case 165: case 166: // V_CMP_LE_I16,V_CMP_GT_I16,V_CMP_NE_I16,V_CMP_GE_I16, + case 167: case 168: case 169: case 170: case 171: // V_CMP_T_I16,V_CMP_F_U16,V_CMP_LT_U16,V_CMP_EQ_U16,V_CMP_LE_U16, + case 172: case 173: case 174: case 175: case 192: // V_CMP_GT_U16,V_CMP_NE_U16,V_CMP_GE_U16,V_CMP_T_U16,V_CMP_F_I32, + case 193: case 194: case 195: case 196: // V_CMP_LT_I32,V_CMP_EQ_I32,V_CMP_LE_I32,V_CMP_GT_I32, + case 197: case 198: case 199: case 200: case 201: // V_CMP_NE_I32,V_CMP_GE_I32,V_CMP_T_I32,V_CMP_F_U32,V_CMP_LT_U32, + case 202: case 203: case 204: case 205: // V_CMP_EQ_U32,V_CMP_LE_U32,V_CMP_GT_U32,V_CMP_NE_U32, + case 206: case 207: // V_CMP_GE_U32,V_CMP_T_U32, + appendOPR_VCC(0,false,true,2); + appendOPR_SRC(layout.SRC0,true,false); + appendOPR_VGPR(layout.VSRC1,true,false); + break; + case 17: case 21: case 48: case 49: // V_CMPX_CLASS_F32,V_CMPX_CLASS_F16,V_CMPX_F_F16,V_CMPX_LT_F16, + case 50: case 51: case 52: case 53: // V_CMPX_EQ_F16,V_CMPX_LE_F16,V_CMPX_GT_F16,V_CMPX_LG_F16, + case 54: case 55: case 56: case 57: // V_CMPX_GE_F16,V_CMPX_O_F16,V_CMPX_U_F16,V_CMPX_NGE_F16, + case 58: case 59: case 60: case 61: // V_CMPX_NLG_F16,V_CMPX_NGT_F16,V_CMPX_NLE_F16,V_CMPX_NEQ_F16, + case 62: case 63: case 80: case 81: // V_CMPX_NLT_F16,V_CMPX_TRU_F16,V_CMPX_F_F32,V_CMPX_LT_F32, + case 82: case 83: case 84: case 85: // V_CMPX_EQ_F32,V_CMPX_LE_F32,V_CMPX_GT_F32,V_CMPX_LG_F32, + case 86: case 87: case 88: case 89: // V_CMPX_GE_F32,V_CMPX_O_F32,V_CMPX_U_F32,V_CMPX_NGE_F32, + case 90: case 91: case 92: case 93: // V_CMPX_NLG_F32,V_CMPX_NGT_F32,V_CMPX_NLE_F32,V_CMPX_NEQ_F32, + case 94: case 95: case 176: case 177: // V_CMPX_NLT_F32,V_CMPX_TRU_F32,V_CMPX_F_I16,V_CMPX_LT_I16, + case 178: case 179: case 180: case 181: // V_CMPX_EQ_I16,V_CMPX_LE_I16,V_CMPX_GT_I16,V_CMPX_NE_I16, + case 182: case 183: case 184: case 185: // V_CMPX_GE_I16,V_CMPX_T_I16,V_CMPX_F_U16,V_CMPX_LT_U16, + case 186: case 187: case 188: case 189: // V_CMPX_EQ_U16,V_CMPX_LE_U16,V_CMPX_GT_U16,V_CMPX_NE_U16, + case 190: case 191: case 208: case 209: // V_CMPX_GE_U16,V_CMPX_T_U16,V_CMPX_F_I32,V_CMPX_LT_I32, + case 210: case 211: case 212: case 213: // V_CMPX_EQ_I32,V_CMPX_LE_I32,V_CMPX_GT_I32,V_CMPX_NE_I32, + case 214: case 215: case 216: case 217: // V_CMPX_GE_I32,V_CMPX_T_I32,V_CMPX_F_U32,V_CMPX_LT_U32, + case 218: case 219: case 220: case 221: // V_CMPX_EQ_U32,V_CMPX_LE_U32,V_CMPX_GT_U32,V_CMPX_NE_U32, + case 222: case 223: // V_CMPX_GE_U32,V_CMPX_T_U32, + appendOPR_VCC(0,false,true,2); + appendOPR_SRC(layout.SRC0,true,false); + appendOPR_VGPR(layout.VSRC1,true,false); + appendOPR_SDST_EXEC(126,false,true,1,true); + break; + case 18: // V_CMP_CLASS_F64, + appendOPR_VCC(0,false,true,2); + appendOPR_SRC(layout.SRC0,true,false,2); + appendOPR_VGPR(layout.VSRC1,true,false); + break; + case 19: // V_CMPX_CLASS_F64, + appendOPR_VCC(0,false,true,2); + appendOPR_SRC(layout.SRC0,true,false,2); + appendOPR_VGPR(layout.VSRC1,true,false); + appendOPR_SDST_EXEC(126,false,true,1,true); + break; + case 96: case 97: case 98: case 99: case 100: // V_CMP_F_F64,V_CMP_LT_F64,V_CMP_EQ_F64,V_CMP_LE_F64,V_CMP_GT_F64, + case 101: case 102: case 103: case 104: // V_CMP_LG_F64,V_CMP_GE_F64,V_CMP_O_F64,V_CMP_U_F64, + case 105: case 106: case 107: case 108: // V_CMP_NGE_F64,V_CMP_NLG_F64,V_CMP_NGT_F64,V_CMP_NLE_F64, + case 109: case 110: case 111: case 224: // V_CMP_NEQ_F64,V_CMP_NLT_F64,V_CMP_TRU_F64,V_CMP_F_I64, + case 225: case 226: case 227: case 228: // V_CMP_LT_I64,V_CMP_EQ_I64,V_CMP_LE_I64,V_CMP_GT_I64, + case 229: case 230: case 231: case 232: case 233: // V_CMP_NE_I64,V_CMP_GE_I64,V_CMP_T_I64,V_CMP_F_U64,V_CMP_LT_U64, + case 234: case 235: case 236: case 237: // V_CMP_EQ_U64,V_CMP_LE_U64,V_CMP_GT_U64,V_CMP_NE_U64, + case 238: case 239: // V_CMP_GE_U64,V_CMP_T_U64, + appendOPR_VCC(0,false,true,2); + appendOPR_SRC(layout.SRC0,true,false,2); + appendOPR_VGPR(layout.VSRC1,true,false,2); + break; + case 112: case 113: case 114: case 115: // V_CMPX_F_F64,V_CMPX_LT_F64,V_CMPX_EQ_F64,V_CMPX_LE_F64, + case 116: case 117: case 118: case 119: // V_CMPX_GT_F64,V_CMPX_LG_F64,V_CMPX_GE_F64,V_CMPX_O_F64, + case 120: case 121: case 122: case 123: // V_CMPX_U_F64,V_CMPX_NGE_F64,V_CMPX_NLG_F64,V_CMPX_NGT_F64, + case 124: case 125: case 126: case 127: // V_CMPX_NLE_F64,V_CMPX_NEQ_F64,V_CMPX_NLT_F64,V_CMPX_TRU_F64, + case 240: case 241: case 242: case 243: // V_CMPX_F_I64,V_CMPX_LT_I64,V_CMPX_EQ_I64,V_CMPX_LE_I64, + case 244: case 245: case 246: case 247: // V_CMPX_GT_I64,V_CMPX_NE_I64,V_CMPX_GE_I64,V_CMPX_T_I64, + case 248: case 249: case 250: case 251: // V_CMPX_F_U64,V_CMPX_LT_U64,V_CMPX_EQ_U64,V_CMPX_LE_U64, + case 252: case 253: case 254: case 255: // V_CMPX_GT_U64,V_CMPX_NE_U64,V_CMPX_GE_U64,V_CMPX_T_U64, + appendOPR_VCC(0,false,true,2); + appendOPR_SRC(layout.SRC0,true,false,2); + appendOPR_VGPR(layout.VSRC1,true,false,2); + appendOPR_SDST_EXEC(126,false,true,1,true); + break; + } + } + +} +} diff --git a/instructionAPI/src/AMDGPU/gfx90a/InstructionDecoder-amdgpu-gfx90a.C b/instructionAPI/src/AMDGPU/gfx90a/InstructionDecoder-amdgpu-gfx90a.C new file mode 100644 index 0000000000..a2fcba1397 --- /dev/null +++ b/instructionAPI/src/AMDGPU/gfx90a/InstructionDecoder-amdgpu-gfx90a.C @@ -0,0 +1,243 @@ +/* + * See the dyninst/COPYRIGHT file for copyright information. + * + * We provide the Paradyn Tools (below described as "Paradyn") + * on an AS IS basis, and do not warrant its validity or performance. + * We reserve the right to update, modify, or discontinue this + * software at any time. We shall have no obligation to supply such + * updates or modifications or any other form of support to you. + * + * By your use of Paradyn, you understand and agree that we (or any + * other person or entity with proprietary rights in Paradyn) are + * under no obligation to provide either maintenance services, + * update services, notices of latent defects, or correction of + * defects for Paradyn. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "Ternary.h" +#include "InstructionDecoder-amdgpu-gfx90a.h" +#include +#include "registers/AMDGPU/amdgpu_gfx90a_regs.h" + +namespace Dyninst { + namespace InstructionAPI { + typedef void (InstructionDecoder_amdgpu_gfx90a::*operandFactory)(); + + typedef amdgpu_gfx90a_insn_entry amdgpu_gfx90a_insn_table[]; + + const std::array InstructionDecoder_amdgpu_gfx90a::condNames = { { + "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", "hi", "ls", "ge", + "lt", "gt", "le", "al", "nv", + } }; + + const char* InstructionDecoder_amdgpu_gfx90a::bitfieldInsnAliasMap(entryID) { + assert(!"no alias for entryID"); + return nullptr; + } + const char* InstructionDecoder_amdgpu_gfx90a::condInsnAliasMap(entryID) { + assert(!"no alias for entryID"); + return nullptr; + } + + using namespace std; + Result_Type InstructionDecoder_amdgpu_gfx90a::makeSizeType(unsigned int) { + assert(0); //not implemented + return u32; + } + + // **************** + // decoding opcodes + // **************** + + MachRegister InstructionDecoder_amdgpu_gfx90a::makeAmdgpuRegID(MachRegister base, unsigned int encoding , unsigned int) { + return MachRegister(base.val() + encoding); + + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx90a::makePCExpr() { + MachRegister baseReg = amdgpu_gfx90a::pc_all; + return makeRegisterExpression(baseReg); + } + + void InstructionDecoder_amdgpu_gfx90a::makeBranchTarget(bool branchIsCall, bool bIsConditional, int immVal, + int immLen_ ) { + Expression::Ptr lhs = makeAddExpression(makePCExpr(),Immediate::makeImmediate(Result(s48,4)),s48); + // * 4 => 2 more bits + int64_t offset = sign_extend64(immLen_+2, immVal * 4); + + Expression::Ptr rhs = Immediate::makeImmediate(Result(s64, offset)); + + insn_in_progress->addSuccessor(makeAddExpression(lhs, rhs, s64), branchIsCall, false, bIsConditional, + false); + if (bIsConditional || branchIsCall) { + insn_in_progress->addSuccessor(makeFallThroughExpr(), false, false, false, true); + } + + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx90a::makeFallThroughExpr() { + // TODO: while s_call_B64 is always 4 bytes, it is not clear whether all instructions that has a fall through branch are 4 bytes long + return makeAddExpression(makePCExpr(), Immediate::makeImmediate(Result(u64, unsign_extend64(3, 4))), u64); + } + + + bool InstructionDecoder_amdgpu_gfx90a::decodeOperands(const Instruction *) { + assert(0 && "decodeOperands deprecated for amdgpu"); + return true; + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx90a::decodeSGPRorM0(unsigned int offset){ + if( offset <= 104) + return makeRegisterExpression(makeAmdgpuRegID(amdgpu_gfx90a::s0,offset)); + if (offset == 124) + return makeRegisterExpression(amdgpu_gfx90a::m0); + cerr << " unknown offset in sgpr or m0 " << offset << endl; + assert(0 && "shouldn't reach here"); + return {}; + } + + + + void InstructionDecoder_amdgpu_gfx90a::processOPR_SMEM_OFFSET(layout_ENC_SMEM & layout){ + if (layout.IMM ==0 ){ + if( layout.SOFFSET_EN ==0 ) { + insn_in_progress-> appendOperand( decodeSGPRorM0(layout.OFFSET), true , false ); + }else{ + insn_in_progress-> appendOperand( decodeSGPRorM0(layout.SOFFSET), true , false ); + } + }else{ + if( layout.SOFFSET_EN ==0 ) { + insn_in_progress->appendOperand(Immediate::makeImmediate(Result(s64,layout.OFFSET)),false ,false); + }else{ + insn_in_progress->appendOperand(Immediate::makeImmediate(Result(s64,layout.OFFSET)),false,false); + insn_in_progress-> appendOperand( decodeSGPRorM0(layout.SOFFSET),true ,false); + } + } + } + uint32_t InstructionDecoder_amdgpu_gfx90a::decodeOPR_LITERAL(){ + useImm = true; + immLen = 4; + if(insn_size == 4) + immLiteral = imm_at_32; + else if(insn_size ==8) + immLiteral = imm_at_64; + else + assert(0 && "unsupported instruction size"); + + return immLiteral; + } + Expression::Ptr InstructionDecoder_amdgpu_gfx90a::decodeOPR_SDWA(){ + useImm = true; + immLen = 4; + if(insn_size == 4) + immLiteral = imm_at_32; + else if(insn_size ==8) + immLiteral = imm_at_64; + else + assert(0 && "unsupported instruction size"); + extension = std::string("_SDWA"); + uint8_t reg_idx = immLiteral & 0xff; + + return makeRegisterExpression(makeAmdgpuRegID(amdgpu_gfx90a::v0,reg_idx),1); + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx90a::decodeOPR_LABEL(uint64_t input){ + Expression::Ptr lhs = makeAddExpression(makePCExpr(),Immediate::makeImmediate(Result(s48,4)),s48); + // 16 bits immediate * 4 => 18 bits + int64_t offset = sign_extend64(18, input * 4); + Expression::Ptr rhs = Immediate::makeImmediate(Result(s64, offset)); + return makeAddExpression(lhs, rhs, s64); + + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx90a::makeRegisterExpression(MachRegister registerID, uint32_t num_elements){ + if(registerID == amdgpu_gfx90a::src_literal){ + return Immediate::makeImmediate(Result(u32,decodeOPR_LITERAL())); + } + return InstructionDecoderImpl::makeRegisterExpression(registerID,num_elements); + } + Expression::Ptr InstructionDecoder_amdgpu_gfx90a::makeRegisterExpression(MachRegister registerID, uint32_t low, uint32_t high ){ + if(registerID == amdgpu_gfx90a::src_literal){ + return Immediate::makeImmediate(Result(u32,decodeOPR_LITERAL())); + } + return InstructionDecoderImpl::makeRegisterExpression(registerID, low, high ); + } + + + + inline unsigned int InstructionDecoder_amdgpu_gfx90a::get32bit(InstructionDecoder::buffer &b,unsigned int offset ){ + assert(offset %4 ==0 ); + if(b.start + offset + 4 <= b.end) + return b.start[offset+3] << 24 | b.start[offset + 2] << 16 | b.start[offset +1 ] << 8 | b.start [offset]; + return 0; + } + + + void InstructionDecoder_amdgpu_gfx90a::reset(){ + immLen = 0; + insn_size = 0; + isBranch = false; + isConditional = false; + isModifyPC =false; + insn = insn_high = insn_long = 0; + useImm = false; + isCall = false; + extension = std::string(""); + } + // here we assemble the first 64 bit (if available) as an instruction + + void InstructionDecoder_amdgpu_gfx90a::setupInsnWord(InstructionDecoder::buffer &b) { + reset(); + if (b.start > b.end) + return; + insn = get32bit(b,0); + + imm_at_32 = insn_high = get32bit(b,4); + imm_at_64 = get32bit(b,8); + + insn_long = ( ((uint64_t) insn_high) << 32) | insn; + } + void InstructionDecoder_amdgpu_gfx90a::decodeOpcode(InstructionDecoder::buffer &b) { + setupInsnWord(b); + mainDecode(); + b.start += insn_in_progress->size(); + } + + void InstructionDecoder_amdgpu_gfx90a::debug_instr(){ + // cout << "decoded instruction " << insn_in_progress->getOperation().mnemonic << " " << std::hex << insn_long << " insn_family = " << instr_family << " length = " << insn_in_progress->size()<< endl << endl; + } + + Instruction InstructionDecoder_amdgpu_gfx90a::decode(InstructionDecoder::buffer &b) { + setupInsnWord(b); + mainDecode(); + b.start += insn_in_progress->size(); + return *insn_in_progress; + } + + void InstructionDecoder_amdgpu_gfx90a::doDelayedDecode(const Instruction *insn_to_complete) { + + InstructionDecoder::buffer b(insn_to_complete->ptr(), insn_to_complete->size()); + setupInsnWord(b); + mainDecode(); + Instruction* iptr = const_cast(insn_to_complete); + *iptr = *(insn_in_progress.get()); + } + } +} + + + diff --git a/instructionAPI/src/AMDGPU/gfx90a/InstructionDecoder-amdgpu-gfx90a.h b/instructionAPI/src/AMDGPU/gfx90a/InstructionDecoder-amdgpu-gfx90a.h new file mode 100644 index 0000000000..00cdcc9b54 --- /dev/null +++ b/instructionAPI/src/AMDGPU/gfx90a/InstructionDecoder-amdgpu-gfx90a.h @@ -0,0 +1,3688 @@ +/* + * See the dyninst/COPYRIGHT file for copyright information. + * + * We provide the Paradyn Tools (below described as "Paradyn") + * on an AS IS basis, and do not warrant its validity or performance. + * We reserve the right to update, modify, or discontinue this + * software at any time. We shall have no obligation to supply such + * updates or modifications or any other form of support to you. + * + * By your use of Paradyn, you understand and agree that we (or any + * other person or entity with proprietary rights in Paradyn) are + * under no obligation to provide either maintenance services, + * update services, notices of latent defects, or correction of + * defects for Paradyn. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ +#ifndef INSTRUCTION_DECODER_GFX90A_H +#define INSTRUCTION_DECODER_GFX90A_H +#include +#include +#include +#include +#include "InstructionDecoderImpl.h" +#include +#include "Immediate.h" +#include "Architecture.h" +#include + +namespace Dyninst { + namespace InstructionAPI { + +#define insn_printf(format, ...) \ + do{ \ + printf("[%s:%u]insn_debug " format, FILE__, __LINE__, ## __VA_ARGS__); \ + }while(0) + + struct amdgpu_gfx90a_insn_entry; + + class InstructionDecoder_amdgpu_gfx90a : public InstructionDecoderImpl { + friend struct amdgpu_gfx90a_insn_entry; + friend struct amdgpu_mask_entry; + + public: + InstructionDecoder_amdgpu_gfx90a(Architecture a) : InstructionDecoderImpl(a) {} + + virtual ~InstructionDecoder_amdgpu_gfx90a() = default; + + virtual void decodeOpcode(InstructionDecoder::buffer &b); + + // decode one instruction starting from b.start + // will advance b.start whenver a instruction is successfully decoded + virtual Instruction decode(InstructionDecoder::buffer &b); + + virtual void setMode(bool) { } + + virtual bool decodeOperands(const Instruction *insn_to_complete); + + bool decodeOperands(const amdgpu_gfx90a_insn_entry & insn_entry); + + virtual void doDelayedDecode(const Instruction *insn_to_complete); + + static const std::array condNames; + static MachRegister sysRegMap(unsigned int); + static const char* bitfieldInsnAliasMap(entryID); + static const char* condInsnAliasMap(entryID); + + + //Check if the index (2nd arg) is valid for the array (1st arg) + template + constexpr bool isArrayIndexValid(ArrayType (&)[n], const IndexType& i) const { + return 0 <= i && i < n; + } + + + private: + virtual Result_Type makeSizeType(unsigned int opType); + + bool is64Bit{}; + + unsigned int insn_size{}; // size of the instruction that we are currently working on + unsigned int insn{}; // the first 32 bit + unsigned int insn_high{}; // the second 32 bit + unsigned long long int insn_long{}; // the combined 64 bit: insn_high << 32 | insn + + // the main process of decoding an instruciton, won't advance buffer + void mainDecode(); + + void mainDecodeOpcode(); + + + void setupInsnWord(InstructionDecoder::buffer &b); + // pointer to the instruction that we are currently working on + dyncompat::shared_ptr insn_in_progress; + + template + int field(unsigned int raw) { +#if defined DEBUG_FIELD + std::cerr << start << "-" << end << ":" << std::dec << (raw >> (start) & + (0xFFFFFFFF >> (31 - (end - start)))) << " "; +#endif + return (raw >> (start) & (0xFFFFFFFF >> (31 - (end - start)))); + } + + template + int longfield(unsigned long long int raw) { +#if defined DEBUG_FIELD + std::cerr << start << "-" << end << ":" << std::dec << (raw >> (start) & + (0xFFFFFFFFFFFFFFFF >> (63 - (end - start)))) << " "; +#endif + return ( (raw >> (start)) & (0xFFFFFFFFFFFFFFFF >> (63 - (end - start)))); + } + + int32_t sign_extend32(int size_, int in) { + int32_t val = 0 | in; + + return (val << (32 - size_)) >> (32 - size_); + } + + int64_t sign_extend64(int size_, int in) { + int64_t val = 0 | in; + + return (val << (64 - size_)) >> (64 - size_); + } + + uint32_t unsign_extend32(int size_, int in) { + uint32_t mask = ~0; + + return (mask >> (32 - size_)) & in; + } + + uint64_t unsign_extend64(int size_, int in) { + uint64_t mask = ~0; + + return (mask >> (64 - size_)) & in; + } + + int highest_set_bit(int32_t val) { + for (int bit_index = 31; bit_index >= 0; bit_index--) + if (((static_cast(val) >> bit_index) & 0x1) == 0x1) + return bit_index + 1; + + return -1; + } + + int lowest_set_bit(int32_t val) { + for (int bit_index = 0; bit_index <= 31; bit_index++) + if (((static_cast(val) >> bit_index) & 0x1) == 0x1) + return bit_index + 1; + + return -1; + } + + std::string extension; + bool hasHw{}; + int hwField{}; + + void processHwFieldInsn(int, int); + + bool hasShift{}; + int shiftField{}; + + void makeBranchTarget(bool, bool, int, int immLen = 16); + + Expression::Ptr makeFallThroughExpr(); + + int _szField{}, size{}; + int _typeField{}; + int cmode{}; + int op{}; + int simdAlphabetImm{}; + + void processAlphabetImm(); + + void NOTHING(); + bool fix_bitfieldinsn_alias(int, int); + void fix_condinsn_alias_and_cond(int &); + void modify_mnemonic_simd_upperhalf_insns(); + + MachRegister makeAmdgpuRegID(MachRegister, unsigned int, unsigned int len = 1); + + MachRegister getLoadStoreSimdRegister(int encoding); + + Expression::Ptr makePCExpr(); + + + template + Expression::Ptr makeLogicalImm(int immr, int imms, int immsLen, Result_Type rT); + + + //for load store + void insnSize(unsigned int insn_size ); + + Expression::Ptr decodeSSRC(unsigned int index); + Expression::Ptr decodeVSRC(unsigned int index); + Expression::Ptr decodeVDST(unsigned int index); + + Expression::Ptr decodeSGPRorM0(unsigned int offset); + + + bool useImm{}; + uint32_t immLen{}; // extra 4 bytes included for decoding instruction + uint32_t immLiteral{}; + uint32_t imm_at_32{}; + uint32_t imm_at_64{}; + uint32_t imm_at_96{}; + + bool isBranch{}; // this is set for all branch instructions, + bool isConditional{}; // this is set for all conditional branch instruction, will set branchCond + bool isCall{}; // this is a call function + + + + // this is set for instructions that directly modify pc + // namely s_setpc and s_swappc + bool isModifyPC{}; + + // reset the decoder internal state for decoding the next instruction + void reset(); + + Expression::Ptr branchCond; + Expression::Ptr branchTarget; + + void setBranch() { + isBranch = true; + } + + void setConditionalBranch() { + isConditional = true; + // TODO : set conditional branch + } + void setModifyPC() { + isModifyPC = true; + } + + void setCall() { + isCall = true; + } + + inline unsigned int get32bit(InstructionDecoder::buffer &b,unsigned int offset ); + + template + void setUseImm(InstructionDecoder::buffer & b, unsigned int offset) + { + if (longfield(insn_long) == candidate) { + useImm = true; + immLen = 4; + immLiteral = get32bit(b,offset); + } + + } + + typedef struct buffer_resource_desc{ + unsigned long long base_address; + unsigned stride; + unsigned cache_swizzle; + unsigned swizzle_enable; + unsigned num_records; + unsigned dst_sel_x; + unsigned dst_sel_y; + unsigned dst_sel_z; + unsigned dst_sel_w; + unsigned num_format; + unsigned data_format; + unsigned user_vm_enable; + unsigned user_vm_mode; + unsigned index_stride; + unsigned add_tid_enable; + unsigned non_volatile; + unsigned type; + }buffer_resource_desc; + + void debug_instr(); + + uint32_t decodeOPR_LITERAL(); + Expression::Ptr decodeOPR_SDWA(); + Expression::Ptr decodeOPR_LABEL(uint64_t input); + using InstructionDecoderImpl::makeRegisterExpression; + Expression::Ptr makeRegisterExpression(MachRegister registerID, uint32_t num_elements = 1); + Expression::Ptr makeRegisterExpression(MachRegister registerID, uint32_t low , uint32_t high ); + void specialHandle(); + + static bool IS_ENC_SOP1(uint64_t I); + static bool IS_ENC_SOPC(uint64_t I); + static bool IS_ENC_SOPP(uint64_t I); + static bool IS_ENC_SOPK(uint64_t I); + static bool IS_ENC_SOP2(uint64_t I); + static bool IS_ENC_SMEM(uint64_t I); + static bool IS_ENC_VOP1(uint64_t I); + static bool IS_ENC_VOPC(uint64_t I); + static bool IS_ENC_VOP2(uint64_t I); + static bool IS_ENC_VINTRP(uint64_t I); + static bool IS_ENC_VOP3P(uint64_t I); + static bool IS_ENC_VOP3(uint64_t I); + static bool IS_ENC_DS(uint64_t I); + static bool IS_ENC_MUBUF(uint64_t I); + static bool IS_ENC_MTBUF(uint64_t I); + static bool IS_ENC_MIMG(uint64_t I); + static bool IS_ENC_FLAT(uint64_t I); + static bool IS_ENC_FLAT_GLBL(uint64_t I); + static bool IS_ENC_FLAT_SCRATCH(uint64_t I); + static bool IS_SOPK_INST_LITERAL_(uint64_t I); + static bool IS_ENC_VOP2_LITERAL(uint64_t I); + static bool IS_ENC_VOP3B(uint64_t I); + static bool IS_ENC_VOP3P_MFMA(uint64_t I); + enum InstructionFamily + { + ENC_SOP1 = -1, + ENC_SOPC = 0, + ENC_SOPP = 1, + ENC_SOPK = 2, + ENC_SOP2 = 3, + ENC_SMEM = 4, + ENC_VOP1 = 5, + ENC_VOPC = 6, + ENC_VOP2 = 7, + ENC_VINTRP = 8, + ENC_VOP3P = 9, + ENC_VOP3 = 10, + ENC_DS = 11, + ENC_MUBUF = 12, + ENC_MTBUF = 13, + ENC_MIMG = 14, + ENC_FLAT = 16, + ENC_FLAT_GLBL = 17, + ENC_FLAT_SCRATCH = 18, + SOPK_INST_LITERAL_ = 19, + ENC_VOP2_LITERAL = 20, + ENC_VOP3B = 21, + ENC_VOP3P_MFMA = 22, + }; + InstructionFamily instr_family; + struct layout_ENC_SOP1 { + uint16_t ENCODING : 9; + uint8_t OP : 8; + uint8_t SDST : 7; + uint8_t SSRC0 : 8; + }; + struct layout_ENC_SOPC { + uint16_t ENCODING : 9; + uint8_t OP : 7; + uint8_t SSRC0 : 8; + uint8_t SSRC1 : 8; + }; + struct layout_ENC_SOPP { + uint16_t ENCODING : 9; + uint8_t OP : 7; + uint16_t SIMM16 : 16; + }; + struct layout_ENC_SOPK { + uint8_t ENCODING : 4; + uint8_t OP : 5; + uint8_t SDST : 7; + uint16_t SIMM16 : 16; + }; + struct layout_ENC_SOP2 { + uint8_t ENCODING : 2; + uint8_t OP : 7; + uint8_t SDST : 7; + uint8_t SSRC0 : 8; + uint8_t SSRC1 : 8; + }; + struct layout_ENC_SMEM { + uint8_t ENCODING : 6; + uint8_t GLC : 1; + uint8_t IMM : 1; + uint8_t NV : 1; + uint32_t OFFSET : 21; + uint8_t OP : 8; + uint8_t SBASE : 7; + uint8_t SDATA : 7; + uint8_t SOFFSET : 7; + uint8_t SOFFSET_EN : 1; + }; + struct layout_ENC_VOP1 { + uint8_t ENCODING : 7; + uint8_t OP : 8; + uint16_t SRC0 : 9; + uint8_t VDST : 8; + }; + struct layout_ENC_VOPC { + uint8_t ENCODING : 7; + uint8_t OP : 8; + uint16_t SRC0 : 9; + uint8_t VSRC1 : 8; + }; + struct layout_ENC_VOP2 { + uint8_t ENCODING : 1; + uint8_t OP : 6; + uint16_t SRC0 : 9; + uint8_t VDST : 8; + uint8_t VSRC1 : 8; + }; + struct layout_ENC_VINTRP { + uint8_t ATTR : 6; + uint8_t ATTRCHAN : 2; + uint8_t ENCODING : 6; + uint8_t OP : 2; + uint8_t VDST : 8; + uint8_t VSRC : 8; + }; + struct layout_ENC_VOP3P { + uint8_t CLAMP : 1; + uint16_t ENCODING : 9; + uint8_t NEG : 3; + uint8_t NEG_HI : 3; + uint8_t OP : 7; + uint8_t OP_SEL : 3; + uint8_t OP_SEL_HI : 2; + uint8_t OP_SEL_HI_2 : 1; + uint16_t SRC0 : 9; + uint16_t SRC1 : 9; + uint16_t SRC2 : 9; + uint8_t VDST : 8; + }; + struct layout_ENC_VOP3 { + uint8_t ABS : 3; + uint8_t CLAMP : 1; + uint8_t ENCODING : 6; + uint8_t NEG : 3; + uint8_t OMOD : 2; + uint16_t OP : 10; + uint8_t OP_SEL : 4; + uint16_t SRC0 : 9; + uint16_t SRC1 : 9; + uint16_t SRC2 : 9; + uint8_t VDST : 8; + }; + struct layout_ENC_DS { + uint8_t ACC : 1; + uint8_t ADDR : 8; + uint8_t DATA0 : 8; + uint8_t DATA1 : 8; + uint8_t ENCODING : 6; + uint8_t GDS : 1; + uint8_t OFFSET0 : 8; + uint8_t OFFSET1 : 8; + uint8_t OP : 8; + uint8_t VDST : 8; + }; + struct layout_ENC_MUBUF { + uint8_t ACC : 1; + uint8_t ENCODING : 6; + uint8_t GLC : 1; + uint8_t IDXEN : 1; + uint8_t LDS : 1; + uint8_t OFFEN : 1; + uint16_t OFFSET : 12; + uint8_t OP : 7; + uint8_t SCC : 1; + uint8_t SLC : 1; + uint8_t SOFFSET : 8; + uint8_t SRSRC : 7; + uint8_t VADDR : 8; + uint8_t VDATA : 8; + }; + struct layout_ENC_MTBUF { + uint8_t ACC : 1; + uint8_t DFMT : 4; + uint8_t ENCODING : 6; + uint8_t GLC : 1; + uint8_t IDXEN : 1; + uint8_t NFMT : 3; + uint8_t OFFEN : 1; + uint16_t OFFSET : 12; + uint8_t OP : 4; + uint8_t SCC : 1; + uint8_t SLC : 1; + uint8_t SOFFSET : 8; + uint8_t SRSRC : 7; + uint8_t VADDR : 8; + uint8_t VDATA : 8; + }; + struct layout_ENC_MIMG { + uint8_t A16 : 1; + uint8_t ACC : 1; + uint8_t D16 : 1; + uint8_t DA : 1; + uint8_t DMASK : 4; + uint8_t ENCODING : 6; + uint8_t GLC : 1; + uint8_t LWE : 1; + uint8_t OP : 7; + uint8_t OPM : 1; + uint8_t SCC : 1; + uint8_t SLC : 1; + uint8_t SRSRC : 7; + uint8_t SSAMP : 7; + uint8_t UNORM : 1; + uint8_t VADDR : 8; + uint8_t VDATA : 8; + }; + struct layout_ENC_FLAT { + uint8_t ACC : 1; + uint8_t ADDR : 8; + uint8_t DATA : 8; + uint8_t ENCODING : 6; + uint8_t GLC : 1; + uint8_t LDS : 1; + uint16_t OFFSET : 12; + uint8_t OP : 7; + uint8_t SADDR : 7; + uint8_t SCC : 1; + uint8_t SEG : 2; + uint8_t SLC : 1; + uint8_t VDST : 8; + }; + struct layout_ENC_FLAT_GLBL { + uint8_t ACC : 1; + uint8_t ADDR : 8; + uint8_t DATA : 8; + uint8_t ENCODING : 6; + uint8_t GLC : 1; + uint8_t LDS : 1; + uint16_t OFFSET : 13; + uint8_t OP : 7; + uint8_t SADDR : 7; + uint8_t SCC : 1; + uint8_t SEG : 2; + uint8_t SLC : 1; + uint8_t VDST : 8; + }; + struct layout_ENC_FLAT_SCRATCH { + uint8_t ACC : 1; + uint8_t ADDR : 8; + uint8_t DATA : 8; + uint8_t ENCODING : 6; + uint8_t GLC : 1; + uint8_t LDS : 1; + uint16_t OFFSET : 13; + uint8_t OP : 7; + uint8_t SADDR : 7; + uint8_t SCC : 1; + uint8_t SEG : 2; + uint8_t SLC : 1; + uint8_t VDST : 8; + }; + struct layout_SOPK_INST_LITERAL_ { + uint8_t ENCODING : 4; + uint8_t OP : 5; + uint8_t SDST : 7; + uint16_t SIMM16 : 16; + uint32_t SIMM32 : 32; + }; + struct layout_ENC_VOP2_LITERAL { + uint8_t ENCODING : 1; + uint8_t OP : 6; + uint32_t SIMM32 : 32; + uint16_t SRC0 : 9; + uint8_t VDST : 8; + uint8_t VSRC1 : 8; + }; + struct layout_ENC_VOP3B { + uint8_t CLAMP : 1; + uint8_t ENCODING : 6; + uint8_t NEG : 3; + uint8_t OMOD : 2; + uint16_t OP : 10; + uint8_t SDST : 7; + uint16_t SRC0 : 9; + uint16_t SRC1 : 9; + uint16_t SRC2 : 9; + uint8_t VDST : 8; + }; + struct layout_ENC_VOP3P_MFMA { + uint8_t ABID : 4; + uint8_t ACC : 2; + uint8_t ACC_CD : 1; + uint8_t BLGP : 3; + uint8_t CBSZ : 3; + uint16_t ENCODING : 9; + uint8_t OP : 7; + uint16_t SRC0 : 9; + uint16_t SRC1 : 9; + uint16_t SRC2 : 9; + uint8_t VDST : 8; + }; + union insn_layout{ + + layout_ENC_SOP1 ENC_SOP1; + layout_ENC_SOPC ENC_SOPC; + layout_ENC_SOPP ENC_SOPP; + layout_ENC_SOPK ENC_SOPK; + layout_ENC_SOP2 ENC_SOP2; + layout_ENC_SMEM ENC_SMEM; + layout_ENC_VOP1 ENC_VOP1; + layout_ENC_VOPC ENC_VOPC; + layout_ENC_VOP2 ENC_VOP2; + layout_ENC_VINTRP ENC_VINTRP; + layout_ENC_VOP3P ENC_VOP3P; + layout_ENC_VOP3 ENC_VOP3; + layout_ENC_DS ENC_DS; + layout_ENC_MUBUF ENC_MUBUF; + layout_ENC_MTBUF ENC_MTBUF; + layout_ENC_MIMG ENC_MIMG; + layout_ENC_FLAT ENC_FLAT; + layout_ENC_FLAT_GLBL ENC_FLAT_GLBL; + layout_ENC_FLAT_SCRATCH ENC_FLAT_SCRATCH; + layout_SOPK_INST_LITERAL_ SOPK_INST_LITERAL_; + layout_ENC_VOP2_LITERAL ENC_VOP2_LITERAL; + layout_ENC_VOP3B ENC_VOP3B; + layout_ENC_VOP3P_MFMA ENC_VOP3P_MFMA; + }insn_layout; + void decodeENC_SOP1(); + void finalizeENC_SOP1Operands(); + void decodeENC_SOPC(); + void finalizeENC_SOPCOperands(); + void decodeENC_SOPP(); + void finalizeENC_SOPPOperands(); + void decodeENC_SOPK(); + void finalizeENC_SOPKOperands(); + void decodeENC_SOP2(); + void finalizeENC_SOP2Operands(); + void decodeENC_SMEM(); + void finalizeENC_SMEMOperands(); + void decodeENC_VOP1(); + void finalizeENC_VOP1Operands(); + void decodeENC_VOPC(); + void finalizeENC_VOPCOperands(); + void decodeENC_VOP2(); + void finalizeENC_VOP2Operands(); + void decodeENC_VINTRP(); + void finalizeENC_VINTRPOperands(); + void decodeENC_VOP3P(); + void finalizeENC_VOP3POperands(); + void decodeENC_VOP3(); + void finalizeENC_VOP3Operands(); + void decodeENC_DS(); + void finalizeENC_DSOperands(); + void decodeENC_MUBUF(); + void finalizeENC_MUBUFOperands(); + void decodeENC_MTBUF(); + void finalizeENC_MTBUFOperands(); + void decodeENC_MIMG(); + void finalizeENC_MIMGOperands(); + void decodeENC_FLAT(); + void finalizeENC_FLATOperands(); + void decodeENC_FLAT_GLBL(); + void finalizeENC_FLAT_GLBLOperands(); + void decodeENC_FLAT_SCRATCH(); + void finalizeENC_FLAT_SCRATCHOperands(); + void decodeSOPK_INST_LITERAL_(); + void finalizeSOPK_INST_LITERAL_Operands(); + void decodeENC_VOP2_LITERAL(); + void finalizeENC_VOP2_LITERALOperands(); + void decodeENC_VOP3B(); + void finalizeENC_VOP3BOperands(); + void decodeENC_VOP3P_MFMA(); + void finalizeENC_VOP3P_MFMAOperands(); + + + Expression::Ptr decodeOPR_ACCVGPR(uint64_t input, uint32_t output_vec_len = 1 ); + Expression::Ptr decodeOPR_DSMEM(uint64_t input, uint32_t output_vec_len = 1 ); + Expression::Ptr decodeOPR_FLAT_SCRATCH(uint64_t input, uint32_t output_vec_len = 1 ); + Expression::Ptr decodeOPR_PC(uint64_t input, uint32_t output_vec_len = 1 ); + Expression::Ptr decodeOPR_SDST(uint64_t input, uint32_t output_vec_len = 1 ); + Expression::Ptr decodeOPR_SDST_EXEC(uint64_t input, uint32_t output_vec_len = 1 ); + Expression::Ptr decodeOPR_SDST_M0(uint64_t input, uint32_t output_vec_len = 1 ); + Expression::Ptr decodeOPR_SRC(uint64_t input, uint32_t output_vec_len = 1 ); + Expression::Ptr decodeOPR_SRC_ACCVGPR(uint64_t input, uint32_t output_vec_len = 1 ); + Expression::Ptr decodeOPR_SRC_NOLDS(uint64_t input, uint32_t output_vec_len = 1 ); + Expression::Ptr decodeOPR_SRC_NOLIT(uint64_t input, uint32_t output_vec_len = 1 ); + Expression::Ptr decodeOPR_SRC_SIMPLE(uint64_t input, uint32_t output_vec_len = 1 ); + Expression::Ptr decodeOPR_SRC_VGPR(uint64_t input, uint32_t output_vec_len = 1 ); + Expression::Ptr decodeOPR_SRC_VGPR_OR_ACCVGPR(uint64_t input, uint32_t output_vec_len = 1 ); + Expression::Ptr decodeOPR_SRC_VGPR_OR_ACCVGPR_OR_CONST(uint64_t input, uint32_t output_vec_len = 1 ); + Expression::Ptr decodeOPR_SREG(uint64_t input, uint32_t output_vec_len = 1 ); + Expression::Ptr decodeOPR_SREG_NOVCC(uint64_t input, uint32_t output_vec_len = 1 ); + Expression::Ptr decodeOPR_SSRC(uint64_t input, uint32_t output_vec_len = 1 ); + Expression::Ptr decodeOPR_SSRC_LANESEL(uint64_t input, uint32_t output_vec_len = 1 ); + Expression::Ptr decodeOPR_SSRC_NOLIT(uint64_t input, uint32_t output_vec_len = 1 ); + Expression::Ptr decodeOPR_SSRC_SPECIAL_SCC(uint64_t input, uint32_t output_vec_len = 1 ); + Expression::Ptr decodeOPR_VCC(uint64_t input, uint32_t output_vec_len = 1 ); + Expression::Ptr decodeOPR_VGPR(uint64_t input, uint32_t output_vec_len = 1 ); + Expression::Ptr decodeOPR_VGPR_OR_ACCVGPR(uint64_t input, uint32_t output_vec_len = 1 ); + Expression::Ptr decodeOPR_VGPR_OR_LDS(uint64_t input, uint32_t output_vec_len = 1 ); + + + void appendOPR_SIMM4(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_SIMM8(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_SIMM16(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_SIMM32(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_WAITCNT(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_ACCVGPR(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_DSMEM(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_FLAT_SCRATCH(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_PC(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_SDST(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_SDST_EXEC(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_SDST_M0(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void processOPR_SMEM_OFFSET(layout_ENC_SMEM & layout ); + + void appendOPR_SRC(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_SRC_ACCVGPR(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_SRC_NOLDS(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_SRC_NOLIT(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_SRC_SIMPLE(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_SRC_VGPR(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_SRC_VGPR_OR_ACCVGPR(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_SRC_VGPR_OR_ACCVGPR_OR_CONST(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_SREG(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_SREG_NOVCC(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_SSRC(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_SSRC_LANESEL(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_SSRC_NOLIT(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_SSRC_SPECIAL_SCC(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_VCC(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_VGPR(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_VGPR_OR_ACCVGPR(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_VGPR_OR_LDS(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + + + struct amdgpu_gfx90a_insn_entry { + entryID op; + const char *mnemonic; + }; + + + const amdgpu_gfx90a_insn_entry ENC_DS_insn_table[256] = + { + {amdgpu_gfx90a_op_DS_ADD_U32,"DS_ADD_U32"}, // 0 + {amdgpu_gfx90a_op_DS_SUB_U32,"DS_SUB_U32"}, // 1 + {amdgpu_gfx90a_op_DS_RSUB_U32,"DS_RSUB_U32"}, // 2 + {amdgpu_gfx90a_op_DS_INC_U32,"DS_INC_U32"}, // 3 + {amdgpu_gfx90a_op_DS_DEC_U32,"DS_DEC_U32"}, // 4 + {amdgpu_gfx90a_op_DS_MIN_I32,"DS_MIN_I32"}, // 5 + {amdgpu_gfx90a_op_DS_MAX_I32,"DS_MAX_I32"}, // 6 + {amdgpu_gfx90a_op_DS_MIN_U32,"DS_MIN_U32"}, // 7 + {amdgpu_gfx90a_op_DS_MAX_U32,"DS_MAX_U32"}, // 8 + {amdgpu_gfx90a_op_DS_AND_B32,"DS_AND_B32"}, // 9 + {amdgpu_gfx90a_op_DS_OR_B32,"DS_OR_B32"}, // 10 + {amdgpu_gfx90a_op_DS_XOR_B32,"DS_XOR_B32"}, // 11 + {amdgpu_gfx90a_op_DS_MSKOR_B32,"DS_MSKOR_B32"}, // 12 + {amdgpu_gfx90a_op_DS_WRITE_B32,"DS_WRITE_B32"}, // 13 + {amdgpu_gfx90a_op_DS_WRITE2_B32,"DS_WRITE2_B32"}, // 14 + {amdgpu_gfx90a_op_DS_WRITE2ST64_B32,"DS_WRITE2ST64_B32"}, // 15 + {amdgpu_gfx90a_op_DS_CMPST_B32,"DS_CMPST_B32"}, // 16 + {amdgpu_gfx90a_op_DS_CMPST_F32,"DS_CMPST_F32"}, // 17 + {amdgpu_gfx90a_op_DS_MIN_F32,"DS_MIN_F32"}, // 18 + {amdgpu_gfx90a_op_DS_MAX_F32,"DS_MAX_F32"}, // 19 + {amdgpu_gfx90a_op_DS_NOP,"DS_NOP"}, // 20 + {amdgpu_gfx90a_op_DS_ADD_F32,"DS_ADD_F32"}, // 21 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 22 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 23 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 24 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 25 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 26 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 27 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 28 + {amdgpu_gfx90a_op_DS_WRITE_ADDTID_B32,"DS_WRITE_ADDTID_B32"}, // 29 + {amdgpu_gfx90a_op_DS_WRITE_B8,"DS_WRITE_B8"}, // 30 + {amdgpu_gfx90a_op_DS_WRITE_B16,"DS_WRITE_B16"}, // 31 + {amdgpu_gfx90a_op_DS_ADD_RTN_U32,"DS_ADD_RTN_U32"}, // 32 + {amdgpu_gfx90a_op_DS_SUB_RTN_U32,"DS_SUB_RTN_U32"}, // 33 + {amdgpu_gfx90a_op_DS_RSUB_RTN_U32,"DS_RSUB_RTN_U32"}, // 34 + {amdgpu_gfx90a_op_DS_INC_RTN_U32,"DS_INC_RTN_U32"}, // 35 + {amdgpu_gfx90a_op_DS_DEC_RTN_U32,"DS_DEC_RTN_U32"}, // 36 + {amdgpu_gfx90a_op_DS_MIN_RTN_I32,"DS_MIN_RTN_I32"}, // 37 + {amdgpu_gfx90a_op_DS_MAX_RTN_I32,"DS_MAX_RTN_I32"}, // 38 + {amdgpu_gfx90a_op_DS_MIN_RTN_U32,"DS_MIN_RTN_U32"}, // 39 + {amdgpu_gfx90a_op_DS_MAX_RTN_U32,"DS_MAX_RTN_U32"}, // 40 + {amdgpu_gfx90a_op_DS_AND_RTN_B32,"DS_AND_RTN_B32"}, // 41 + {amdgpu_gfx90a_op_DS_OR_RTN_B32,"DS_OR_RTN_B32"}, // 42 + {amdgpu_gfx90a_op_DS_XOR_RTN_B32,"DS_XOR_RTN_B32"}, // 43 + {amdgpu_gfx90a_op_DS_MSKOR_RTN_B32,"DS_MSKOR_RTN_B32"}, // 44 + {amdgpu_gfx90a_op_DS_WRXCHG_RTN_B32,"DS_WRXCHG_RTN_B32"}, // 45 + {amdgpu_gfx90a_op_DS_WRXCHG2_RTN_B32,"DS_WRXCHG2_RTN_B32"}, // 46 + {amdgpu_gfx90a_op_DS_WRXCHG2ST64_RTN_B32,"DS_WRXCHG2ST64_RTN_B32"}, // 47 + {amdgpu_gfx90a_op_DS_CMPST_RTN_B32,"DS_CMPST_RTN_B32"}, // 48 + {amdgpu_gfx90a_op_DS_CMPST_RTN_F32,"DS_CMPST_RTN_F32"}, // 49 + {amdgpu_gfx90a_op_DS_MIN_RTN_F32,"DS_MIN_RTN_F32"}, // 50 + {amdgpu_gfx90a_op_DS_MAX_RTN_F32,"DS_MAX_RTN_F32"}, // 51 + {amdgpu_gfx90a_op_DS_WRAP_RTN_B32,"DS_WRAP_RTN_B32"}, // 52 + {amdgpu_gfx90a_op_DS_ADD_RTN_F32,"DS_ADD_RTN_F32"}, // 53 + {amdgpu_gfx90a_op_DS_READ_B32,"DS_READ_B32"}, // 54 + {amdgpu_gfx90a_op_DS_READ2_B32,"DS_READ2_B32"}, // 55 + {amdgpu_gfx90a_op_DS_READ2ST64_B32,"DS_READ2ST64_B32"}, // 56 + {amdgpu_gfx90a_op_DS_READ_I8,"DS_READ_I8"}, // 57 + {amdgpu_gfx90a_op_DS_READ_U8,"DS_READ_U8"}, // 58 + {amdgpu_gfx90a_op_DS_READ_I16,"DS_READ_I16"}, // 59 + {amdgpu_gfx90a_op_DS_READ_U16,"DS_READ_U16"}, // 60 + {amdgpu_gfx90a_op_DS_SWIZZLE_B32,"DS_SWIZZLE_B32"}, // 61 + {amdgpu_gfx90a_op_DS_PERMUTE_B32,"DS_PERMUTE_B32"}, // 62 + {amdgpu_gfx90a_op_DS_BPERMUTE_B32,"DS_BPERMUTE_B32"}, // 63 + {amdgpu_gfx90a_op_DS_ADD_U64,"DS_ADD_U64"}, // 64 + {amdgpu_gfx90a_op_DS_SUB_U64,"DS_SUB_U64"}, // 65 + {amdgpu_gfx90a_op_DS_RSUB_U64,"DS_RSUB_U64"}, // 66 + {amdgpu_gfx90a_op_DS_INC_U64,"DS_INC_U64"}, // 67 + {amdgpu_gfx90a_op_DS_DEC_U64,"DS_DEC_U64"}, // 68 + {amdgpu_gfx90a_op_DS_MIN_I64,"DS_MIN_I64"}, // 69 + {amdgpu_gfx90a_op_DS_MAX_I64,"DS_MAX_I64"}, // 70 + {amdgpu_gfx90a_op_DS_MIN_U64,"DS_MIN_U64"}, // 71 + {amdgpu_gfx90a_op_DS_MAX_U64,"DS_MAX_U64"}, // 72 + {amdgpu_gfx90a_op_DS_AND_B64,"DS_AND_B64"}, // 73 + {amdgpu_gfx90a_op_DS_OR_B64,"DS_OR_B64"}, // 74 + {amdgpu_gfx90a_op_DS_XOR_B64,"DS_XOR_B64"}, // 75 + {amdgpu_gfx90a_op_DS_MSKOR_B64,"DS_MSKOR_B64"}, // 76 + {amdgpu_gfx90a_op_DS_WRITE_B64,"DS_WRITE_B64"}, // 77 + {amdgpu_gfx90a_op_DS_WRITE2_B64,"DS_WRITE2_B64"}, // 78 + {amdgpu_gfx90a_op_DS_WRITE2ST64_B64,"DS_WRITE2ST64_B64"}, // 79 + {amdgpu_gfx90a_op_DS_CMPST_B64,"DS_CMPST_B64"}, // 80 + {amdgpu_gfx90a_op_DS_CMPST_F64,"DS_CMPST_F64"}, // 81 + {amdgpu_gfx90a_op_DS_MIN_F64,"DS_MIN_F64"}, // 82 + {amdgpu_gfx90a_op_DS_MAX_F64,"DS_MAX_F64"}, // 83 + {amdgpu_gfx90a_op_DS_WRITE_B8_D16_HI,"DS_WRITE_B8_D16_HI"}, // 84 + {amdgpu_gfx90a_op_DS_WRITE_B16_D16_HI,"DS_WRITE_B16_D16_HI"}, // 85 + {amdgpu_gfx90a_op_DS_READ_U8_D16,"DS_READ_U8_D16"}, // 86 + {amdgpu_gfx90a_op_DS_READ_U8_D16_HI,"DS_READ_U8_D16_HI"}, // 87 + {amdgpu_gfx90a_op_DS_READ_I8_D16,"DS_READ_I8_D16"}, // 88 + {amdgpu_gfx90a_op_DS_READ_I8_D16_HI,"DS_READ_I8_D16_HI"}, // 89 + {amdgpu_gfx90a_op_DS_READ_U16_D16,"DS_READ_U16_D16"}, // 90 + {amdgpu_gfx90a_op_DS_READ_U16_D16_HI,"DS_READ_U16_D16_HI"}, // 91 + {amdgpu_gfx90a_op_DS_ADD_F64,"DS_ADD_F64"}, // 92 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 93 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 94 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 95 + {amdgpu_gfx90a_op_DS_ADD_RTN_U64,"DS_ADD_RTN_U64"}, // 96 + {amdgpu_gfx90a_op_DS_SUB_RTN_U64,"DS_SUB_RTN_U64"}, // 97 + {amdgpu_gfx90a_op_DS_RSUB_RTN_U64,"DS_RSUB_RTN_U64"}, // 98 + {amdgpu_gfx90a_op_DS_INC_RTN_U64,"DS_INC_RTN_U64"}, // 99 + {amdgpu_gfx90a_op_DS_DEC_RTN_U64,"DS_DEC_RTN_U64"}, // 100 + {amdgpu_gfx90a_op_DS_MIN_RTN_I64,"DS_MIN_RTN_I64"}, // 101 + {amdgpu_gfx90a_op_DS_MAX_RTN_I64,"DS_MAX_RTN_I64"}, // 102 + {amdgpu_gfx90a_op_DS_MIN_RTN_U64,"DS_MIN_RTN_U64"}, // 103 + {amdgpu_gfx90a_op_DS_MAX_RTN_U64,"DS_MAX_RTN_U64"}, // 104 + {amdgpu_gfx90a_op_DS_AND_RTN_B64,"DS_AND_RTN_B64"}, // 105 + {amdgpu_gfx90a_op_DS_OR_RTN_B64,"DS_OR_RTN_B64"}, // 106 + {amdgpu_gfx90a_op_DS_XOR_RTN_B64,"DS_XOR_RTN_B64"}, // 107 + {amdgpu_gfx90a_op_DS_MSKOR_RTN_B64,"DS_MSKOR_RTN_B64"}, // 108 + {amdgpu_gfx90a_op_DS_WRXCHG_RTN_B64,"DS_WRXCHG_RTN_B64"}, // 109 + {amdgpu_gfx90a_op_DS_WRXCHG2_RTN_B64,"DS_WRXCHG2_RTN_B64"}, // 110 + {amdgpu_gfx90a_op_DS_WRXCHG2ST64_RTN_B64,"DS_WRXCHG2ST64_RTN_B64"}, // 111 + {amdgpu_gfx90a_op_DS_CMPST_RTN_B64,"DS_CMPST_RTN_B64"}, // 112 + {amdgpu_gfx90a_op_DS_CMPST_RTN_F64,"DS_CMPST_RTN_F64"}, // 113 + {amdgpu_gfx90a_op_DS_MIN_RTN_F64,"DS_MIN_RTN_F64"}, // 114 + {amdgpu_gfx90a_op_DS_MAX_RTN_F64,"DS_MAX_RTN_F64"}, // 115 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 116 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 117 + {amdgpu_gfx90a_op_DS_READ_B64,"DS_READ_B64"}, // 118 + {amdgpu_gfx90a_op_DS_READ2_B64,"DS_READ2_B64"}, // 119 + {amdgpu_gfx90a_op_DS_READ2ST64_B64,"DS_READ2ST64_B64"}, // 120 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 121 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 122 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 123 + {amdgpu_gfx90a_op_DS_ADD_RTN_F64,"DS_ADD_RTN_F64"}, // 124 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 125 + {amdgpu_gfx90a_op_DS_CONDXCHG32_RTN_B64,"DS_CONDXCHG32_RTN_B64"}, // 126 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 127 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 128 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 129 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 130 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 131 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 132 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 133 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 134 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 135 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 136 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 137 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 138 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 139 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 140 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 141 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 142 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 143 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 144 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 145 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 146 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 147 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 148 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 149 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 150 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 151 + {amdgpu_gfx90a_op_DS_GWS_SEMA_RELEASE_ALL,"DS_GWS_SEMA_RELEASE_ALL"}, // 152 + {amdgpu_gfx90a_op_DS_GWS_INIT,"DS_GWS_INIT"}, // 153 + {amdgpu_gfx90a_op_DS_GWS_SEMA_V,"DS_GWS_SEMA_V"}, // 154 + {amdgpu_gfx90a_op_DS_GWS_SEMA_BR,"DS_GWS_SEMA_BR"}, // 155 + {amdgpu_gfx90a_op_DS_GWS_SEMA_P,"DS_GWS_SEMA_P"}, // 156 + {amdgpu_gfx90a_op_DS_GWS_BARRIER,"DS_GWS_BARRIER"}, // 157 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 158 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 159 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 160 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 161 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 162 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 163 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 164 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 165 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 166 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 167 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 168 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 169 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 170 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 171 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 172 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 173 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 174 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 175 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 176 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 177 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 178 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 179 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 180 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 181 + {amdgpu_gfx90a_op_DS_READ_ADDTID_B32,"DS_READ_ADDTID_B32"}, // 182 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 183 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 184 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 185 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 186 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 187 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 188 + {amdgpu_gfx90a_op_DS_CONSUME,"DS_CONSUME"}, // 189 + {amdgpu_gfx90a_op_DS_APPEND,"DS_APPEND"}, // 190 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 191 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 192 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 193 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 194 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 195 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 196 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 197 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 198 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 199 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 200 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 201 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 202 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 203 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 204 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 205 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 206 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 207 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 208 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 209 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 210 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 211 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 212 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 213 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 214 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 215 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 216 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 217 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 218 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 219 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 220 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 221 + {amdgpu_gfx90a_op_DS_WRITE_B96,"DS_WRITE_B96"}, // 222 + {amdgpu_gfx90a_op_DS_WRITE_B128,"DS_WRITE_B128"}, // 223 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 224 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 225 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 226 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 227 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 228 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 229 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 230 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 231 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 232 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 233 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 234 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 235 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 236 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 237 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 238 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 239 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 240 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 241 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 242 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 243 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 244 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 245 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 246 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 247 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 248 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 249 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 250 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 251 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 252 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 253 + {amdgpu_gfx90a_op_DS_READ_B96,"DS_READ_B96"}, // 254 + {amdgpu_gfx90a_op_DS_READ_B128,"DS_READ_B128"}, // 255 + }; // end ENC_DS_insn_table + const amdgpu_gfx90a_insn_entry ENC_FLAT_insn_table[109] = + { + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 0 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 1 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 2 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 3 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 4 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 5 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 6 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 7 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 8 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 9 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 10 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 11 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 12 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 13 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 14 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 15 + {amdgpu_gfx90a_op_FLAT_LOAD_UBYTE,"FLAT_LOAD_UBYTE"}, // 16 + {amdgpu_gfx90a_op_FLAT_LOAD_SBYTE,"FLAT_LOAD_SBYTE"}, // 17 + {amdgpu_gfx90a_op_FLAT_LOAD_USHORT,"FLAT_LOAD_USHORT"}, // 18 + {amdgpu_gfx90a_op_FLAT_LOAD_SSHORT,"FLAT_LOAD_SSHORT"}, // 19 + {amdgpu_gfx90a_op_FLAT_LOAD_DWORD,"FLAT_LOAD_DWORD"}, // 20 + {amdgpu_gfx90a_op_FLAT_LOAD_DWORDX2,"FLAT_LOAD_DWORDX2"}, // 21 + {amdgpu_gfx90a_op_FLAT_LOAD_DWORDX3,"FLAT_LOAD_DWORDX3"}, // 22 + {amdgpu_gfx90a_op_FLAT_LOAD_DWORDX4,"FLAT_LOAD_DWORDX4"}, // 23 + {amdgpu_gfx90a_op_FLAT_STORE_BYTE,"FLAT_STORE_BYTE"}, // 24 + {amdgpu_gfx90a_op_FLAT_STORE_BYTE_D16_HI,"FLAT_STORE_BYTE_D16_HI"}, // 25 + {amdgpu_gfx90a_op_FLAT_STORE_SHORT,"FLAT_STORE_SHORT"}, // 26 + {amdgpu_gfx90a_op_FLAT_STORE_SHORT_D16_HI,"FLAT_STORE_SHORT_D16_HI"}, // 27 + {amdgpu_gfx90a_op_FLAT_STORE_DWORD,"FLAT_STORE_DWORD"}, // 28 + {amdgpu_gfx90a_op_FLAT_STORE_DWORDX2,"FLAT_STORE_DWORDX2"}, // 29 + {amdgpu_gfx90a_op_FLAT_STORE_DWORDX3,"FLAT_STORE_DWORDX3"}, // 30 + {amdgpu_gfx90a_op_FLAT_STORE_DWORDX4,"FLAT_STORE_DWORDX4"}, // 31 + {amdgpu_gfx90a_op_FLAT_LOAD_UBYTE_D16,"FLAT_LOAD_UBYTE_D16"}, // 32 + {amdgpu_gfx90a_op_FLAT_LOAD_UBYTE_D16_HI,"FLAT_LOAD_UBYTE_D16_HI"}, // 33 + {amdgpu_gfx90a_op_FLAT_LOAD_SBYTE_D16,"FLAT_LOAD_SBYTE_D16"}, // 34 + {amdgpu_gfx90a_op_FLAT_LOAD_SBYTE_D16_HI,"FLAT_LOAD_SBYTE_D16_HI"}, // 35 + {amdgpu_gfx90a_op_FLAT_LOAD_SHORT_D16,"FLAT_LOAD_SHORT_D16"}, // 36 + {amdgpu_gfx90a_op_FLAT_LOAD_SHORT_D16_HI,"FLAT_LOAD_SHORT_D16_HI"}, // 37 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 38 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 39 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 40 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 41 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 42 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 43 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 44 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 45 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 46 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 47 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 48 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 49 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 50 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 51 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 52 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 53 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 54 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 55 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 56 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 57 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 58 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 59 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 60 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 61 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 62 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 63 + {amdgpu_gfx90a_op_FLAT_ATOMIC_SWAP,"FLAT_ATOMIC_SWAP"}, // 64 + {amdgpu_gfx90a_op_FLAT_ATOMIC_CMPSWAP,"FLAT_ATOMIC_CMPSWAP"}, // 65 + {amdgpu_gfx90a_op_FLAT_ATOMIC_ADD,"FLAT_ATOMIC_ADD"}, // 66 + {amdgpu_gfx90a_op_FLAT_ATOMIC_SUB,"FLAT_ATOMIC_SUB"}, // 67 + {amdgpu_gfx90a_op_FLAT_ATOMIC_SMIN,"FLAT_ATOMIC_SMIN"}, // 68 + {amdgpu_gfx90a_op_FLAT_ATOMIC_UMIN,"FLAT_ATOMIC_UMIN"}, // 69 + {amdgpu_gfx90a_op_FLAT_ATOMIC_SMAX,"FLAT_ATOMIC_SMAX"}, // 70 + {amdgpu_gfx90a_op_FLAT_ATOMIC_UMAX,"FLAT_ATOMIC_UMAX"}, // 71 + {amdgpu_gfx90a_op_FLAT_ATOMIC_AND,"FLAT_ATOMIC_AND"}, // 72 + {amdgpu_gfx90a_op_FLAT_ATOMIC_OR,"FLAT_ATOMIC_OR"}, // 73 + {amdgpu_gfx90a_op_FLAT_ATOMIC_XOR,"FLAT_ATOMIC_XOR"}, // 74 + {amdgpu_gfx90a_op_FLAT_ATOMIC_INC,"FLAT_ATOMIC_INC"}, // 75 + {amdgpu_gfx90a_op_FLAT_ATOMIC_DEC,"FLAT_ATOMIC_DEC"}, // 76 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 77 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 78 + {amdgpu_gfx90a_op_FLAT_ATOMIC_ADD_F64,"FLAT_ATOMIC_ADD_F64"}, // 79 + {amdgpu_gfx90a_op_FLAT_ATOMIC_MIN_F64,"FLAT_ATOMIC_MIN_F64"}, // 80 + {amdgpu_gfx90a_op_FLAT_ATOMIC_MAX_F64,"FLAT_ATOMIC_MAX_F64"}, // 81 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 82 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 83 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 84 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 85 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 86 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 87 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 88 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 89 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 90 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 91 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 92 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 93 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 94 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 95 + {amdgpu_gfx90a_op_FLAT_ATOMIC_SWAP_X2,"FLAT_ATOMIC_SWAP_X2"}, // 96 + {amdgpu_gfx90a_op_FLAT_ATOMIC_CMPSWAP_X2,"FLAT_ATOMIC_CMPSWAP_X2"}, // 97 + {amdgpu_gfx90a_op_FLAT_ATOMIC_ADD_X2,"FLAT_ATOMIC_ADD_X2"}, // 98 + {amdgpu_gfx90a_op_FLAT_ATOMIC_SUB_X2,"FLAT_ATOMIC_SUB_X2"}, // 99 + {amdgpu_gfx90a_op_FLAT_ATOMIC_SMIN_X2,"FLAT_ATOMIC_SMIN_X2"}, // 100 + {amdgpu_gfx90a_op_FLAT_ATOMIC_UMIN_X2,"FLAT_ATOMIC_UMIN_X2"}, // 101 + {amdgpu_gfx90a_op_FLAT_ATOMIC_SMAX_X2,"FLAT_ATOMIC_SMAX_X2"}, // 102 + {amdgpu_gfx90a_op_FLAT_ATOMIC_UMAX_X2,"FLAT_ATOMIC_UMAX_X2"}, // 103 + {amdgpu_gfx90a_op_FLAT_ATOMIC_AND_X2,"FLAT_ATOMIC_AND_X2"}, // 104 + {amdgpu_gfx90a_op_FLAT_ATOMIC_OR_X2,"FLAT_ATOMIC_OR_X2"}, // 105 + {amdgpu_gfx90a_op_FLAT_ATOMIC_XOR_X2,"FLAT_ATOMIC_XOR_X2"}, // 106 + {amdgpu_gfx90a_op_FLAT_ATOMIC_INC_X2,"FLAT_ATOMIC_INC_X2"}, // 107 + {amdgpu_gfx90a_op_FLAT_ATOMIC_DEC_X2,"FLAT_ATOMIC_DEC_X2"}, // 108 + }; // end ENC_FLAT_insn_table + const amdgpu_gfx90a_insn_entry ENC_FLAT_GLBL_insn_table[109] = + { + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 0 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 1 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 2 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 3 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 4 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 5 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 6 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 7 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 8 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 9 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 10 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 11 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 12 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 13 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 14 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 15 + {amdgpu_gfx90a_op_GLOBAL_LOAD_UBYTE,"GLOBAL_LOAD_UBYTE"}, // 16 + {amdgpu_gfx90a_op_GLOBAL_LOAD_SBYTE,"GLOBAL_LOAD_SBYTE"}, // 17 + {amdgpu_gfx90a_op_GLOBAL_LOAD_USHORT,"GLOBAL_LOAD_USHORT"}, // 18 + {amdgpu_gfx90a_op_GLOBAL_LOAD_SSHORT,"GLOBAL_LOAD_SSHORT"}, // 19 + {amdgpu_gfx90a_op_GLOBAL_LOAD_DWORD,"GLOBAL_LOAD_DWORD"}, // 20 + {amdgpu_gfx90a_op_GLOBAL_LOAD_DWORDX2,"GLOBAL_LOAD_DWORDX2"}, // 21 + {amdgpu_gfx90a_op_GLOBAL_LOAD_DWORDX3,"GLOBAL_LOAD_DWORDX3"}, // 22 + {amdgpu_gfx90a_op_GLOBAL_LOAD_DWORDX4,"GLOBAL_LOAD_DWORDX4"}, // 23 + {amdgpu_gfx90a_op_GLOBAL_STORE_BYTE,"GLOBAL_STORE_BYTE"}, // 24 + {amdgpu_gfx90a_op_GLOBAL_STORE_BYTE_D16_HI,"GLOBAL_STORE_BYTE_D16_HI"}, // 25 + {amdgpu_gfx90a_op_GLOBAL_STORE_SHORT,"GLOBAL_STORE_SHORT"}, // 26 + {amdgpu_gfx90a_op_GLOBAL_STORE_SHORT_D16_HI,"GLOBAL_STORE_SHORT_D16_HI"}, // 27 + {amdgpu_gfx90a_op_GLOBAL_STORE_DWORD,"GLOBAL_STORE_DWORD"}, // 28 + {amdgpu_gfx90a_op_GLOBAL_STORE_DWORDX2,"GLOBAL_STORE_DWORDX2"}, // 29 + {amdgpu_gfx90a_op_GLOBAL_STORE_DWORDX3,"GLOBAL_STORE_DWORDX3"}, // 30 + {amdgpu_gfx90a_op_GLOBAL_STORE_DWORDX4,"GLOBAL_STORE_DWORDX4"}, // 31 + {amdgpu_gfx90a_op_GLOBAL_LOAD_UBYTE_D16,"GLOBAL_LOAD_UBYTE_D16"}, // 32 + {amdgpu_gfx90a_op_GLOBAL_LOAD_UBYTE_D16_HI,"GLOBAL_LOAD_UBYTE_D16_HI"}, // 33 + {amdgpu_gfx90a_op_GLOBAL_LOAD_SBYTE_D16,"GLOBAL_LOAD_SBYTE_D16"}, // 34 + {amdgpu_gfx90a_op_GLOBAL_LOAD_SBYTE_D16_HI,"GLOBAL_LOAD_SBYTE_D16_HI"}, // 35 + {amdgpu_gfx90a_op_GLOBAL_LOAD_SHORT_D16,"GLOBAL_LOAD_SHORT_D16"}, // 36 + {amdgpu_gfx90a_op_GLOBAL_LOAD_SHORT_D16_HI,"GLOBAL_LOAD_SHORT_D16_HI"}, // 37 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 38 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 39 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 40 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 41 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 42 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 43 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 44 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 45 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 46 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 47 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 48 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 49 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 50 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 51 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 52 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 53 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 54 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 55 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 56 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 57 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 58 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 59 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 60 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 61 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 62 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 63 + {amdgpu_gfx90a_op_GLOBAL_ATOMIC_SWAP,"GLOBAL_ATOMIC_SWAP"}, // 64 + {amdgpu_gfx90a_op_GLOBAL_ATOMIC_CMPSWAP,"GLOBAL_ATOMIC_CMPSWAP"}, // 65 + {amdgpu_gfx90a_op_GLOBAL_ATOMIC_ADD,"GLOBAL_ATOMIC_ADD"}, // 66 + {amdgpu_gfx90a_op_GLOBAL_ATOMIC_SUB,"GLOBAL_ATOMIC_SUB"}, // 67 + {amdgpu_gfx90a_op_GLOBAL_ATOMIC_SMIN,"GLOBAL_ATOMIC_SMIN"}, // 68 + {amdgpu_gfx90a_op_GLOBAL_ATOMIC_UMIN,"GLOBAL_ATOMIC_UMIN"}, // 69 + {amdgpu_gfx90a_op_GLOBAL_ATOMIC_SMAX,"GLOBAL_ATOMIC_SMAX"}, // 70 + {amdgpu_gfx90a_op_GLOBAL_ATOMIC_UMAX,"GLOBAL_ATOMIC_UMAX"}, // 71 + {amdgpu_gfx90a_op_GLOBAL_ATOMIC_AND,"GLOBAL_ATOMIC_AND"}, // 72 + {amdgpu_gfx90a_op_GLOBAL_ATOMIC_OR,"GLOBAL_ATOMIC_OR"}, // 73 + {amdgpu_gfx90a_op_GLOBAL_ATOMIC_XOR,"GLOBAL_ATOMIC_XOR"}, // 74 + {amdgpu_gfx90a_op_GLOBAL_ATOMIC_INC,"GLOBAL_ATOMIC_INC"}, // 75 + {amdgpu_gfx90a_op_GLOBAL_ATOMIC_DEC,"GLOBAL_ATOMIC_DEC"}, // 76 + {amdgpu_gfx90a_op_GLOBAL_ATOMIC_ADD_F32,"GLOBAL_ATOMIC_ADD_F32"}, // 77 + {amdgpu_gfx90a_op_GLOBAL_ATOMIC_PK_ADD_F16,"GLOBAL_ATOMIC_PK_ADD_F16"}, // 78 + {amdgpu_gfx90a_op_GLOBAL_ATOMIC_ADD_F64,"GLOBAL_ATOMIC_ADD_F64"}, // 79 + {amdgpu_gfx90a_op_GLOBAL_ATOMIC_MIN_F64,"GLOBAL_ATOMIC_MIN_F64"}, // 80 + {amdgpu_gfx90a_op_GLOBAL_ATOMIC_MAX_F64,"GLOBAL_ATOMIC_MAX_F64"}, // 81 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 82 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 83 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 84 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 85 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 86 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 87 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 88 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 89 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 90 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 91 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 92 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 93 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 94 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 95 + {amdgpu_gfx90a_op_GLOBAL_ATOMIC_SWAP_X2,"GLOBAL_ATOMIC_SWAP_X2"}, // 96 + {amdgpu_gfx90a_op_GLOBAL_ATOMIC_CMPSWAP_X2,"GLOBAL_ATOMIC_CMPSWAP_X2"}, // 97 + {amdgpu_gfx90a_op_GLOBAL_ATOMIC_ADD_X2,"GLOBAL_ATOMIC_ADD_X2"}, // 98 + {amdgpu_gfx90a_op_GLOBAL_ATOMIC_SUB_X2,"GLOBAL_ATOMIC_SUB_X2"}, // 99 + {amdgpu_gfx90a_op_GLOBAL_ATOMIC_SMIN_X2,"GLOBAL_ATOMIC_SMIN_X2"}, // 100 + {amdgpu_gfx90a_op_GLOBAL_ATOMIC_UMIN_X2,"GLOBAL_ATOMIC_UMIN_X2"}, // 101 + {amdgpu_gfx90a_op_GLOBAL_ATOMIC_SMAX_X2,"GLOBAL_ATOMIC_SMAX_X2"}, // 102 + {amdgpu_gfx90a_op_GLOBAL_ATOMIC_UMAX_X2,"GLOBAL_ATOMIC_UMAX_X2"}, // 103 + {amdgpu_gfx90a_op_GLOBAL_ATOMIC_AND_X2,"GLOBAL_ATOMIC_AND_X2"}, // 104 + {amdgpu_gfx90a_op_GLOBAL_ATOMIC_OR_X2,"GLOBAL_ATOMIC_OR_X2"}, // 105 + {amdgpu_gfx90a_op_GLOBAL_ATOMIC_XOR_X2,"GLOBAL_ATOMIC_XOR_X2"}, // 106 + {amdgpu_gfx90a_op_GLOBAL_ATOMIC_INC_X2,"GLOBAL_ATOMIC_INC_X2"}, // 107 + {amdgpu_gfx90a_op_GLOBAL_ATOMIC_DEC_X2,"GLOBAL_ATOMIC_DEC_X2"}, // 108 + }; // end ENC_FLAT_GLBL_insn_table + const amdgpu_gfx90a_insn_entry ENC_FLAT_SCRATCH_insn_table[38] = + { + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 0 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 1 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 2 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 3 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 4 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 5 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 6 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 7 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 8 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 9 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 10 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 11 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 12 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 13 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 14 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 15 + {amdgpu_gfx90a_op_SCRATCH_LOAD_UBYTE,"SCRATCH_LOAD_UBYTE"}, // 16 + {amdgpu_gfx90a_op_SCRATCH_LOAD_SBYTE,"SCRATCH_LOAD_SBYTE"}, // 17 + {amdgpu_gfx90a_op_SCRATCH_LOAD_USHORT,"SCRATCH_LOAD_USHORT"}, // 18 + {amdgpu_gfx90a_op_SCRATCH_LOAD_SSHORT,"SCRATCH_LOAD_SSHORT"}, // 19 + {amdgpu_gfx90a_op_SCRATCH_LOAD_DWORD,"SCRATCH_LOAD_DWORD"}, // 20 + {amdgpu_gfx90a_op_SCRATCH_LOAD_DWORDX2,"SCRATCH_LOAD_DWORDX2"}, // 21 + {amdgpu_gfx90a_op_SCRATCH_LOAD_DWORDX3,"SCRATCH_LOAD_DWORDX3"}, // 22 + {amdgpu_gfx90a_op_SCRATCH_LOAD_DWORDX4,"SCRATCH_LOAD_DWORDX4"}, // 23 + {amdgpu_gfx90a_op_SCRATCH_STORE_BYTE,"SCRATCH_STORE_BYTE"}, // 24 + {amdgpu_gfx90a_op_SCRATCH_STORE_BYTE_D16_HI,"SCRATCH_STORE_BYTE_D16_HI"}, // 25 + {amdgpu_gfx90a_op_SCRATCH_STORE_SHORT,"SCRATCH_STORE_SHORT"}, // 26 + {amdgpu_gfx90a_op_SCRATCH_STORE_SHORT_D16_HI,"SCRATCH_STORE_SHORT_D16_HI"}, // 27 + {amdgpu_gfx90a_op_SCRATCH_STORE_DWORD,"SCRATCH_STORE_DWORD"}, // 28 + {amdgpu_gfx90a_op_SCRATCH_STORE_DWORDX2,"SCRATCH_STORE_DWORDX2"}, // 29 + {amdgpu_gfx90a_op_SCRATCH_STORE_DWORDX3,"SCRATCH_STORE_DWORDX3"}, // 30 + {amdgpu_gfx90a_op_SCRATCH_STORE_DWORDX4,"SCRATCH_STORE_DWORDX4"}, // 31 + {amdgpu_gfx90a_op_SCRATCH_LOAD_UBYTE_D16,"SCRATCH_LOAD_UBYTE_D16"}, // 32 + {amdgpu_gfx90a_op_SCRATCH_LOAD_UBYTE_D16_HI,"SCRATCH_LOAD_UBYTE_D16_HI"}, // 33 + {amdgpu_gfx90a_op_SCRATCH_LOAD_SBYTE_D16,"SCRATCH_LOAD_SBYTE_D16"}, // 34 + {amdgpu_gfx90a_op_SCRATCH_LOAD_SBYTE_D16_HI,"SCRATCH_LOAD_SBYTE_D16_HI"}, // 35 + {amdgpu_gfx90a_op_SCRATCH_LOAD_SHORT_D16,"SCRATCH_LOAD_SHORT_D16"}, // 36 + {amdgpu_gfx90a_op_SCRATCH_LOAD_SHORT_D16_HI,"SCRATCH_LOAD_SHORT_D16_HI"}, // 37 + }; // end ENC_FLAT_SCRATCH_insn_table + const amdgpu_gfx90a_insn_entry ENC_MIMG_insn_table[33] = + { + {amdgpu_gfx90a_op_IMAGE_LOAD,"IMAGE_LOAD"}, // 0 + {amdgpu_gfx90a_op_IMAGE_LOAD_MIP,"IMAGE_LOAD_MIP"}, // 1 + {amdgpu_gfx90a_op_IMAGE_LOAD_PCK,"IMAGE_LOAD_PCK"}, // 2 + {amdgpu_gfx90a_op_IMAGE_LOAD_PCK_SGN,"IMAGE_LOAD_PCK_SGN"}, // 3 + {amdgpu_gfx90a_op_IMAGE_LOAD_MIP_PCK,"IMAGE_LOAD_MIP_PCK"}, // 4 + {amdgpu_gfx90a_op_IMAGE_LOAD_MIP_PCK_SGN,"IMAGE_LOAD_MIP_PCK_SGN"}, // 5 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 6 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 7 + {amdgpu_gfx90a_op_IMAGE_STORE,"IMAGE_STORE"}, // 8 + {amdgpu_gfx90a_op_IMAGE_STORE_MIP,"IMAGE_STORE_MIP"}, // 9 + {amdgpu_gfx90a_op_IMAGE_STORE_PCK,"IMAGE_STORE_PCK"}, // 10 + {amdgpu_gfx90a_op_IMAGE_STORE_MIP_PCK,"IMAGE_STORE_MIP_PCK"}, // 11 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 12 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 13 + {amdgpu_gfx90a_op_IMAGE_GET_RESINFO,"IMAGE_GET_RESINFO"}, // 14 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 15 + {amdgpu_gfx90a_op_IMAGE_ATOMIC_SWAP,"IMAGE_ATOMIC_SWAP"}, // 16 + {amdgpu_gfx90a_op_IMAGE_ATOMIC_CMPSWAP,"IMAGE_ATOMIC_CMPSWAP"}, // 17 + {amdgpu_gfx90a_op_IMAGE_ATOMIC_ADD,"IMAGE_ATOMIC_ADD"}, // 18 + {amdgpu_gfx90a_op_IMAGE_ATOMIC_SUB,"IMAGE_ATOMIC_SUB"}, // 19 + {amdgpu_gfx90a_op_IMAGE_ATOMIC_SMIN,"IMAGE_ATOMIC_SMIN"}, // 20 + {amdgpu_gfx90a_op_IMAGE_ATOMIC_UMIN,"IMAGE_ATOMIC_UMIN"}, // 21 + {amdgpu_gfx90a_op_IMAGE_ATOMIC_SMAX,"IMAGE_ATOMIC_SMAX"}, // 22 + {amdgpu_gfx90a_op_IMAGE_ATOMIC_UMAX,"IMAGE_ATOMIC_UMAX"}, // 23 + {amdgpu_gfx90a_op_IMAGE_ATOMIC_AND,"IMAGE_ATOMIC_AND"}, // 24 + {amdgpu_gfx90a_op_IMAGE_ATOMIC_OR,"IMAGE_ATOMIC_OR"}, // 25 + {amdgpu_gfx90a_op_IMAGE_ATOMIC_XOR,"IMAGE_ATOMIC_XOR"}, // 26 + {amdgpu_gfx90a_op_IMAGE_ATOMIC_INC,"IMAGE_ATOMIC_INC"}, // 27 + {amdgpu_gfx90a_op_IMAGE_ATOMIC_DEC,"IMAGE_ATOMIC_DEC"}, // 28 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 29 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 30 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 31 + {amdgpu_gfx90a_op_IMAGE_SAMPLE,"IMAGE_SAMPLE"}, // 32 + }; // end ENC_MIMG_insn_table + const amdgpu_gfx90a_insn_entry ENC_MTBUF_insn_table[16] = + { + {amdgpu_gfx90a_op_TBUFFER_LOAD_FORMAT_X,"TBUFFER_LOAD_FORMAT_X"}, // 0 + {amdgpu_gfx90a_op_TBUFFER_LOAD_FORMAT_XY,"TBUFFER_LOAD_FORMAT_XY"}, // 1 + {amdgpu_gfx90a_op_TBUFFER_LOAD_FORMAT_XYZ,"TBUFFER_LOAD_FORMAT_XYZ"}, // 2 + {amdgpu_gfx90a_op_TBUFFER_LOAD_FORMAT_XYZW,"TBUFFER_LOAD_FORMAT_XYZW"}, // 3 + {amdgpu_gfx90a_op_TBUFFER_STORE_FORMAT_X,"TBUFFER_STORE_FORMAT_X"}, // 4 + {amdgpu_gfx90a_op_TBUFFER_STORE_FORMAT_XY,"TBUFFER_STORE_FORMAT_XY"}, // 5 + {amdgpu_gfx90a_op_TBUFFER_STORE_FORMAT_XYZ,"TBUFFER_STORE_FORMAT_XYZ"}, // 6 + {amdgpu_gfx90a_op_TBUFFER_STORE_FORMAT_XYZW,"TBUFFER_STORE_FORMAT_XYZW"}, // 7 + {amdgpu_gfx90a_op_TBUFFER_LOAD_FORMAT_D16_X,"TBUFFER_LOAD_FORMAT_D16_X"}, // 8 + {amdgpu_gfx90a_op_TBUFFER_LOAD_FORMAT_D16_XY,"TBUFFER_LOAD_FORMAT_D16_XY"}, // 9 + {amdgpu_gfx90a_op_TBUFFER_LOAD_FORMAT_D16_XYZ,"TBUFFER_LOAD_FORMAT_D16_XYZ"}, // 10 + {amdgpu_gfx90a_op_TBUFFER_LOAD_FORMAT_D16_XYZW,"TBUFFER_LOAD_FORMAT_D16_XYZW"}, // 11 + {amdgpu_gfx90a_op_TBUFFER_STORE_FORMAT_D16_X,"TBUFFER_STORE_FORMAT_D16_X"}, // 12 + {amdgpu_gfx90a_op_TBUFFER_STORE_FORMAT_D16_XY,"TBUFFER_STORE_FORMAT_D16_XY"}, // 13 + {amdgpu_gfx90a_op_TBUFFER_STORE_FORMAT_D16_XYZ,"TBUFFER_STORE_FORMAT_D16_XYZ"}, // 14 + {amdgpu_gfx90a_op_TBUFFER_STORE_FORMAT_D16_XYZW,"TBUFFER_STORE_FORMAT_D16_XYZW"}, // 15 + }; // end ENC_MTBUF_insn_table + const amdgpu_gfx90a_insn_entry ENC_MUBUF_insn_table[109] = + { + {amdgpu_gfx90a_op_BUFFER_LOAD_FORMAT_X,"BUFFER_LOAD_FORMAT_X"}, // 0 + {amdgpu_gfx90a_op_BUFFER_LOAD_FORMAT_XY,"BUFFER_LOAD_FORMAT_XY"}, // 1 + {amdgpu_gfx90a_op_BUFFER_LOAD_FORMAT_XYZ,"BUFFER_LOAD_FORMAT_XYZ"}, // 2 + {amdgpu_gfx90a_op_BUFFER_LOAD_FORMAT_XYZW,"BUFFER_LOAD_FORMAT_XYZW"}, // 3 + {amdgpu_gfx90a_op_BUFFER_STORE_FORMAT_X,"BUFFER_STORE_FORMAT_X"}, // 4 + {amdgpu_gfx90a_op_BUFFER_STORE_FORMAT_XY,"BUFFER_STORE_FORMAT_XY"}, // 5 + {amdgpu_gfx90a_op_BUFFER_STORE_FORMAT_XYZ,"BUFFER_STORE_FORMAT_XYZ"}, // 6 + {amdgpu_gfx90a_op_BUFFER_STORE_FORMAT_XYZW,"BUFFER_STORE_FORMAT_XYZW"}, // 7 + {amdgpu_gfx90a_op_BUFFER_LOAD_FORMAT_D16_X,"BUFFER_LOAD_FORMAT_D16_X"}, // 8 + {amdgpu_gfx90a_op_BUFFER_LOAD_FORMAT_D16_XY,"BUFFER_LOAD_FORMAT_D16_XY"}, // 9 + {amdgpu_gfx90a_op_BUFFER_LOAD_FORMAT_D16_XYZ,"BUFFER_LOAD_FORMAT_D16_XYZ"}, // 10 + {amdgpu_gfx90a_op_BUFFER_LOAD_FORMAT_D16_XYZW,"BUFFER_LOAD_FORMAT_D16_XYZW"}, // 11 + {amdgpu_gfx90a_op_BUFFER_STORE_FORMAT_D16_X,"BUFFER_STORE_FORMAT_D16_X"}, // 12 + {amdgpu_gfx90a_op_BUFFER_STORE_FORMAT_D16_XY,"BUFFER_STORE_FORMAT_D16_XY"}, // 13 + {amdgpu_gfx90a_op_BUFFER_STORE_FORMAT_D16_XYZ,"BUFFER_STORE_FORMAT_D16_XYZ"}, // 14 + {amdgpu_gfx90a_op_BUFFER_STORE_FORMAT_D16_XYZW,"BUFFER_STORE_FORMAT_D16_XYZW"}, // 15 + {amdgpu_gfx90a_op_BUFFER_LOAD_UBYTE,"BUFFER_LOAD_UBYTE"}, // 16 + {amdgpu_gfx90a_op_BUFFER_LOAD_SBYTE,"BUFFER_LOAD_SBYTE"}, // 17 + {amdgpu_gfx90a_op_BUFFER_LOAD_USHORT,"BUFFER_LOAD_USHORT"}, // 18 + {amdgpu_gfx90a_op_BUFFER_LOAD_SSHORT,"BUFFER_LOAD_SSHORT"}, // 19 + {amdgpu_gfx90a_op_BUFFER_LOAD_DWORD,"BUFFER_LOAD_DWORD"}, // 20 + {amdgpu_gfx90a_op_BUFFER_LOAD_DWORDX2,"BUFFER_LOAD_DWORDX2"}, // 21 + {amdgpu_gfx90a_op_BUFFER_LOAD_DWORDX3,"BUFFER_LOAD_DWORDX3"}, // 22 + {amdgpu_gfx90a_op_BUFFER_LOAD_DWORDX4,"BUFFER_LOAD_DWORDX4"}, // 23 + {amdgpu_gfx90a_op_BUFFER_STORE_BYTE,"BUFFER_STORE_BYTE"}, // 24 + {amdgpu_gfx90a_op_BUFFER_STORE_BYTE_D16_HI,"BUFFER_STORE_BYTE_D16_HI"}, // 25 + {amdgpu_gfx90a_op_BUFFER_STORE_SHORT,"BUFFER_STORE_SHORT"}, // 26 + {amdgpu_gfx90a_op_BUFFER_STORE_SHORT_D16_HI,"BUFFER_STORE_SHORT_D16_HI"}, // 27 + {amdgpu_gfx90a_op_BUFFER_STORE_DWORD,"BUFFER_STORE_DWORD"}, // 28 + {amdgpu_gfx90a_op_BUFFER_STORE_DWORDX2,"BUFFER_STORE_DWORDX2"}, // 29 + {amdgpu_gfx90a_op_BUFFER_STORE_DWORDX3,"BUFFER_STORE_DWORDX3"}, // 30 + {amdgpu_gfx90a_op_BUFFER_STORE_DWORDX4,"BUFFER_STORE_DWORDX4"}, // 31 + {amdgpu_gfx90a_op_BUFFER_LOAD_UBYTE_D16,"BUFFER_LOAD_UBYTE_D16"}, // 32 + {amdgpu_gfx90a_op_BUFFER_LOAD_UBYTE_D16_HI,"BUFFER_LOAD_UBYTE_D16_HI"}, // 33 + {amdgpu_gfx90a_op_BUFFER_LOAD_SBYTE_D16,"BUFFER_LOAD_SBYTE_D16"}, // 34 + {amdgpu_gfx90a_op_BUFFER_LOAD_SBYTE_D16_HI,"BUFFER_LOAD_SBYTE_D16_HI"}, // 35 + {amdgpu_gfx90a_op_BUFFER_LOAD_SHORT_D16,"BUFFER_LOAD_SHORT_D16"}, // 36 + {amdgpu_gfx90a_op_BUFFER_LOAD_SHORT_D16_HI,"BUFFER_LOAD_SHORT_D16_HI"}, // 37 + {amdgpu_gfx90a_op_BUFFER_LOAD_FORMAT_D16_HI_X,"BUFFER_LOAD_FORMAT_D16_HI_X"}, // 38 + {amdgpu_gfx90a_op_BUFFER_STORE_FORMAT_D16_HI_X,"BUFFER_STORE_FORMAT_D16_HI_X"}, // 39 + {amdgpu_gfx90a_op_BUFFER_WBL2,"BUFFER_WBL2"}, // 40 + {amdgpu_gfx90a_op_BUFFER_INVL2,"BUFFER_INVL2"}, // 41 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 42 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 43 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 44 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 45 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 46 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 47 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 48 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 49 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 50 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 51 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 52 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 53 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 54 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 55 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 56 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 57 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 58 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 59 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 60 + {amdgpu_gfx90a_op_BUFFER_STORE_LDS_DWORD,"BUFFER_STORE_LDS_DWORD"}, // 61 + {amdgpu_gfx90a_op_BUFFER_WBINVL1,"BUFFER_WBINVL1"}, // 62 + {amdgpu_gfx90a_op_BUFFER_WBINVL1_VOL,"BUFFER_WBINVL1_VOL"}, // 63 + {amdgpu_gfx90a_op_BUFFER_ATOMIC_SWAP,"BUFFER_ATOMIC_SWAP"}, // 64 + {amdgpu_gfx90a_op_BUFFER_ATOMIC_CMPSWAP,"BUFFER_ATOMIC_CMPSWAP"}, // 65 + {amdgpu_gfx90a_op_BUFFER_ATOMIC_ADD,"BUFFER_ATOMIC_ADD"}, // 66 + {amdgpu_gfx90a_op_BUFFER_ATOMIC_SUB,"BUFFER_ATOMIC_SUB"}, // 67 + {amdgpu_gfx90a_op_BUFFER_ATOMIC_SMIN,"BUFFER_ATOMIC_SMIN"}, // 68 + {amdgpu_gfx90a_op_BUFFER_ATOMIC_UMIN,"BUFFER_ATOMIC_UMIN"}, // 69 + {amdgpu_gfx90a_op_BUFFER_ATOMIC_SMAX,"BUFFER_ATOMIC_SMAX"}, // 70 + {amdgpu_gfx90a_op_BUFFER_ATOMIC_UMAX,"BUFFER_ATOMIC_UMAX"}, // 71 + {amdgpu_gfx90a_op_BUFFER_ATOMIC_AND,"BUFFER_ATOMIC_AND"}, // 72 + {amdgpu_gfx90a_op_BUFFER_ATOMIC_OR,"BUFFER_ATOMIC_OR"}, // 73 + {amdgpu_gfx90a_op_BUFFER_ATOMIC_XOR,"BUFFER_ATOMIC_XOR"}, // 74 + {amdgpu_gfx90a_op_BUFFER_ATOMIC_INC,"BUFFER_ATOMIC_INC"}, // 75 + {amdgpu_gfx90a_op_BUFFER_ATOMIC_DEC,"BUFFER_ATOMIC_DEC"}, // 76 + {amdgpu_gfx90a_op_BUFFER_ATOMIC_ADD_F32,"BUFFER_ATOMIC_ADD_F32"}, // 77 + {amdgpu_gfx90a_op_BUFFER_ATOMIC_PK_ADD_F16,"BUFFER_ATOMIC_PK_ADD_F16"}, // 78 + {amdgpu_gfx90a_op_BUFFER_ATOMIC_ADD_F64,"BUFFER_ATOMIC_ADD_F64"}, // 79 + {amdgpu_gfx90a_op_BUFFER_ATOMIC_MIN_F64,"BUFFER_ATOMIC_MIN_F64"}, // 80 + {amdgpu_gfx90a_op_BUFFER_ATOMIC_MAX_F64,"BUFFER_ATOMIC_MAX_F64"}, // 81 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 82 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 83 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 84 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 85 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 86 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 87 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 88 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 89 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 90 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 91 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 92 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 93 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 94 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 95 + {amdgpu_gfx90a_op_BUFFER_ATOMIC_SWAP_X2,"BUFFER_ATOMIC_SWAP_X2"}, // 96 + {amdgpu_gfx90a_op_BUFFER_ATOMIC_CMPSWAP_X2,"BUFFER_ATOMIC_CMPSWAP_X2"}, // 97 + {amdgpu_gfx90a_op_BUFFER_ATOMIC_ADD_X2,"BUFFER_ATOMIC_ADD_X2"}, // 98 + {amdgpu_gfx90a_op_BUFFER_ATOMIC_SUB_X2,"BUFFER_ATOMIC_SUB_X2"}, // 99 + {amdgpu_gfx90a_op_BUFFER_ATOMIC_SMIN_X2,"BUFFER_ATOMIC_SMIN_X2"}, // 100 + {amdgpu_gfx90a_op_BUFFER_ATOMIC_UMIN_X2,"BUFFER_ATOMIC_UMIN_X2"}, // 101 + {amdgpu_gfx90a_op_BUFFER_ATOMIC_SMAX_X2,"BUFFER_ATOMIC_SMAX_X2"}, // 102 + {amdgpu_gfx90a_op_BUFFER_ATOMIC_UMAX_X2,"BUFFER_ATOMIC_UMAX_X2"}, // 103 + {amdgpu_gfx90a_op_BUFFER_ATOMIC_AND_X2,"BUFFER_ATOMIC_AND_X2"}, // 104 + {amdgpu_gfx90a_op_BUFFER_ATOMIC_OR_X2,"BUFFER_ATOMIC_OR_X2"}, // 105 + {amdgpu_gfx90a_op_BUFFER_ATOMIC_XOR_X2,"BUFFER_ATOMIC_XOR_X2"}, // 106 + {amdgpu_gfx90a_op_BUFFER_ATOMIC_INC_X2,"BUFFER_ATOMIC_INC_X2"}, // 107 + {amdgpu_gfx90a_op_BUFFER_ATOMIC_DEC_X2,"BUFFER_ATOMIC_DEC_X2"}, // 108 + }; // end ENC_MUBUF_insn_table + const amdgpu_gfx90a_insn_entry ENC_SMEM_insn_table[173] = + { + {amdgpu_gfx90a_op_S_LOAD_DWORD,"S_LOAD_DWORD"}, // 0 + {amdgpu_gfx90a_op_S_LOAD_DWORDX2,"S_LOAD_DWORDX2"}, // 1 + {amdgpu_gfx90a_op_S_LOAD_DWORDX4,"S_LOAD_DWORDX4"}, // 2 + {amdgpu_gfx90a_op_S_LOAD_DWORDX8,"S_LOAD_DWORDX8"}, // 3 + {amdgpu_gfx90a_op_S_LOAD_DWORDX16,"S_LOAD_DWORDX16"}, // 4 + {amdgpu_gfx90a_op_S_SCRATCH_LOAD_DWORD,"S_SCRATCH_LOAD_DWORD"}, // 5 + {amdgpu_gfx90a_op_S_SCRATCH_LOAD_DWORDX2,"S_SCRATCH_LOAD_DWORDX2"}, // 6 + {amdgpu_gfx90a_op_S_SCRATCH_LOAD_DWORDX4,"S_SCRATCH_LOAD_DWORDX4"}, // 7 + {amdgpu_gfx90a_op_S_BUFFER_LOAD_DWORD,"S_BUFFER_LOAD_DWORD"}, // 8 + {amdgpu_gfx90a_op_S_BUFFER_LOAD_DWORDX2,"S_BUFFER_LOAD_DWORDX2"}, // 9 + {amdgpu_gfx90a_op_S_BUFFER_LOAD_DWORDX4,"S_BUFFER_LOAD_DWORDX4"}, // 10 + {amdgpu_gfx90a_op_S_BUFFER_LOAD_DWORDX8,"S_BUFFER_LOAD_DWORDX8"}, // 11 + {amdgpu_gfx90a_op_S_BUFFER_LOAD_DWORDX16,"S_BUFFER_LOAD_DWORDX16"}, // 12 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 13 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 14 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 15 + {amdgpu_gfx90a_op_S_STORE_DWORD,"S_STORE_DWORD"}, // 16 + {amdgpu_gfx90a_op_S_STORE_DWORDX2,"S_STORE_DWORDX2"}, // 17 + {amdgpu_gfx90a_op_S_STORE_DWORDX4,"S_STORE_DWORDX4"}, // 18 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 19 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 20 + {amdgpu_gfx90a_op_S_SCRATCH_STORE_DWORD,"S_SCRATCH_STORE_DWORD"}, // 21 + {amdgpu_gfx90a_op_S_SCRATCH_STORE_DWORDX2,"S_SCRATCH_STORE_DWORDX2"}, // 22 + {amdgpu_gfx90a_op_S_SCRATCH_STORE_DWORDX4,"S_SCRATCH_STORE_DWORDX4"}, // 23 + {amdgpu_gfx90a_op_S_BUFFER_STORE_DWORD,"S_BUFFER_STORE_DWORD"}, // 24 + {amdgpu_gfx90a_op_S_BUFFER_STORE_DWORDX2,"S_BUFFER_STORE_DWORDX2"}, // 25 + {amdgpu_gfx90a_op_S_BUFFER_STORE_DWORDX4,"S_BUFFER_STORE_DWORDX4"}, // 26 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 27 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 28 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 29 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 30 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 31 + {amdgpu_gfx90a_op_S_DCACHE_INV,"S_DCACHE_INV"}, // 32 + {amdgpu_gfx90a_op_S_DCACHE_WB,"S_DCACHE_WB"}, // 33 + {amdgpu_gfx90a_op_S_DCACHE_INV_VOL,"S_DCACHE_INV_VOL"}, // 34 + {amdgpu_gfx90a_op_S_DCACHE_WB_VOL,"S_DCACHE_WB_VOL"}, // 35 + {amdgpu_gfx90a_op_S_MEMTIME,"S_MEMTIME"}, // 36 + {amdgpu_gfx90a_op_S_MEMREALTIME,"S_MEMREALTIME"}, // 37 + {amdgpu_gfx90a_op_S_ATC_PROBE,"S_ATC_PROBE"}, // 38 + {amdgpu_gfx90a_op_S_ATC_PROBE_BUFFER,"S_ATC_PROBE_BUFFER"}, // 39 + {amdgpu_gfx90a_op_S_DCACHE_DISCARD,"S_DCACHE_DISCARD"}, // 40 + {amdgpu_gfx90a_op_S_DCACHE_DISCARD_X2,"S_DCACHE_DISCARD_X2"}, // 41 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 42 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 43 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 44 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 45 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 46 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 47 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 48 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 49 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 50 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 51 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 52 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 53 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 54 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 55 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 56 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 57 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 58 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 59 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 60 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 61 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 62 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 63 + {amdgpu_gfx90a_op_S_BUFFER_ATOMIC_SWAP,"S_BUFFER_ATOMIC_SWAP"}, // 64 + {amdgpu_gfx90a_op_S_BUFFER_ATOMIC_CMPSWAP,"S_BUFFER_ATOMIC_CMPSWAP"}, // 65 + {amdgpu_gfx90a_op_S_BUFFER_ATOMIC_ADD,"S_BUFFER_ATOMIC_ADD"}, // 66 + {amdgpu_gfx90a_op_S_BUFFER_ATOMIC_SUB,"S_BUFFER_ATOMIC_SUB"}, // 67 + {amdgpu_gfx90a_op_S_BUFFER_ATOMIC_SMIN,"S_BUFFER_ATOMIC_SMIN"}, // 68 + {amdgpu_gfx90a_op_S_BUFFER_ATOMIC_UMIN,"S_BUFFER_ATOMIC_UMIN"}, // 69 + {amdgpu_gfx90a_op_S_BUFFER_ATOMIC_SMAX,"S_BUFFER_ATOMIC_SMAX"}, // 70 + {amdgpu_gfx90a_op_S_BUFFER_ATOMIC_UMAX,"S_BUFFER_ATOMIC_UMAX"}, // 71 + {amdgpu_gfx90a_op_S_BUFFER_ATOMIC_AND,"S_BUFFER_ATOMIC_AND"}, // 72 + {amdgpu_gfx90a_op_S_BUFFER_ATOMIC_OR,"S_BUFFER_ATOMIC_OR"}, // 73 + {amdgpu_gfx90a_op_S_BUFFER_ATOMIC_XOR,"S_BUFFER_ATOMIC_XOR"}, // 74 + {amdgpu_gfx90a_op_S_BUFFER_ATOMIC_INC,"S_BUFFER_ATOMIC_INC"}, // 75 + {amdgpu_gfx90a_op_S_BUFFER_ATOMIC_DEC,"S_BUFFER_ATOMIC_DEC"}, // 76 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 77 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 78 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 79 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 80 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 81 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 82 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 83 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 84 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 85 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 86 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 87 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 88 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 89 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 90 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 91 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 92 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 93 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 94 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 95 + {amdgpu_gfx90a_op_S_BUFFER_ATOMIC_SWAP_X2,"S_BUFFER_ATOMIC_SWAP_X2"}, // 96 + {amdgpu_gfx90a_op_S_BUFFER_ATOMIC_CMPSWAP_X2,"S_BUFFER_ATOMIC_CMPSWAP_X2"}, // 97 + {amdgpu_gfx90a_op_S_BUFFER_ATOMIC_ADD_X2,"S_BUFFER_ATOMIC_ADD_X2"}, // 98 + {amdgpu_gfx90a_op_S_BUFFER_ATOMIC_SUB_X2,"S_BUFFER_ATOMIC_SUB_X2"}, // 99 + {amdgpu_gfx90a_op_S_BUFFER_ATOMIC_SMIN_X2,"S_BUFFER_ATOMIC_SMIN_X2"}, // 100 + {amdgpu_gfx90a_op_S_BUFFER_ATOMIC_UMIN_X2,"S_BUFFER_ATOMIC_UMIN_X2"}, // 101 + {amdgpu_gfx90a_op_S_BUFFER_ATOMIC_SMAX_X2,"S_BUFFER_ATOMIC_SMAX_X2"}, // 102 + {amdgpu_gfx90a_op_S_BUFFER_ATOMIC_UMAX_X2,"S_BUFFER_ATOMIC_UMAX_X2"}, // 103 + {amdgpu_gfx90a_op_S_BUFFER_ATOMIC_AND_X2,"S_BUFFER_ATOMIC_AND_X2"}, // 104 + {amdgpu_gfx90a_op_S_BUFFER_ATOMIC_OR_X2,"S_BUFFER_ATOMIC_OR_X2"}, // 105 + {amdgpu_gfx90a_op_S_BUFFER_ATOMIC_XOR_X2,"S_BUFFER_ATOMIC_XOR_X2"}, // 106 + {amdgpu_gfx90a_op_S_BUFFER_ATOMIC_INC_X2,"S_BUFFER_ATOMIC_INC_X2"}, // 107 + {amdgpu_gfx90a_op_S_BUFFER_ATOMIC_DEC_X2,"S_BUFFER_ATOMIC_DEC_X2"}, // 108 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 109 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 110 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 111 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 112 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 113 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 114 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 115 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 116 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 117 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 118 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 119 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 120 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 121 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 122 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 123 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 124 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 125 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 126 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 127 + {amdgpu_gfx90a_op_S_ATOMIC_SWAP,"S_ATOMIC_SWAP"}, // 128 + {amdgpu_gfx90a_op_S_ATOMIC_CMPSWAP,"S_ATOMIC_CMPSWAP"}, // 129 + {amdgpu_gfx90a_op_S_ATOMIC_ADD,"S_ATOMIC_ADD"}, // 130 + {amdgpu_gfx90a_op_S_ATOMIC_SUB,"S_ATOMIC_SUB"}, // 131 + {amdgpu_gfx90a_op_S_ATOMIC_SMIN,"S_ATOMIC_SMIN"}, // 132 + {amdgpu_gfx90a_op_S_ATOMIC_UMIN,"S_ATOMIC_UMIN"}, // 133 + {amdgpu_gfx90a_op_S_ATOMIC_SMAX,"S_ATOMIC_SMAX"}, // 134 + {amdgpu_gfx90a_op_S_ATOMIC_UMAX,"S_ATOMIC_UMAX"}, // 135 + {amdgpu_gfx90a_op_S_ATOMIC_AND,"S_ATOMIC_AND"}, // 136 + {amdgpu_gfx90a_op_S_ATOMIC_OR,"S_ATOMIC_OR"}, // 137 + {amdgpu_gfx90a_op_S_ATOMIC_XOR,"S_ATOMIC_XOR"}, // 138 + {amdgpu_gfx90a_op_S_ATOMIC_INC,"S_ATOMIC_INC"}, // 139 + {amdgpu_gfx90a_op_S_ATOMIC_DEC,"S_ATOMIC_DEC"}, // 140 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 141 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 142 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 143 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 144 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 145 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 146 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 147 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 148 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 149 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 150 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 151 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 152 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 153 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 154 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 155 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 156 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 157 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 158 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 159 + {amdgpu_gfx90a_op_S_ATOMIC_SWAP_X2,"S_ATOMIC_SWAP_X2"}, // 160 + {amdgpu_gfx90a_op_S_ATOMIC_CMPSWAP_X2,"S_ATOMIC_CMPSWAP_X2"}, // 161 + {amdgpu_gfx90a_op_S_ATOMIC_ADD_X2,"S_ATOMIC_ADD_X2"}, // 162 + {amdgpu_gfx90a_op_S_ATOMIC_SUB_X2,"S_ATOMIC_SUB_X2"}, // 163 + {amdgpu_gfx90a_op_S_ATOMIC_SMIN_X2,"S_ATOMIC_SMIN_X2"}, // 164 + {amdgpu_gfx90a_op_S_ATOMIC_UMIN_X2,"S_ATOMIC_UMIN_X2"}, // 165 + {amdgpu_gfx90a_op_S_ATOMIC_SMAX_X2,"S_ATOMIC_SMAX_X2"}, // 166 + {amdgpu_gfx90a_op_S_ATOMIC_UMAX_X2,"S_ATOMIC_UMAX_X2"}, // 167 + {amdgpu_gfx90a_op_S_ATOMIC_AND_X2,"S_ATOMIC_AND_X2"}, // 168 + {amdgpu_gfx90a_op_S_ATOMIC_OR_X2,"S_ATOMIC_OR_X2"}, // 169 + {amdgpu_gfx90a_op_S_ATOMIC_XOR_X2,"S_ATOMIC_XOR_X2"}, // 170 + {amdgpu_gfx90a_op_S_ATOMIC_INC_X2,"S_ATOMIC_INC_X2"}, // 171 + {amdgpu_gfx90a_op_S_ATOMIC_DEC_X2,"S_ATOMIC_DEC_X2"}, // 172 + }; // end ENC_SMEM_insn_table + const amdgpu_gfx90a_insn_entry ENC_SOP1_insn_table[56] = + { + {amdgpu_gfx90a_op_S_MOV_B32,"S_MOV_B32"}, // 0 + {amdgpu_gfx90a_op_S_MOV_B64,"S_MOV_B64"}, // 1 + {amdgpu_gfx90a_op_S_CMOV_B32,"S_CMOV_B32"}, // 2 + {amdgpu_gfx90a_op_S_CMOV_B64,"S_CMOV_B64"}, // 3 + {amdgpu_gfx90a_op_S_NOT_B32,"S_NOT_B32"}, // 4 + {amdgpu_gfx90a_op_S_NOT_B64,"S_NOT_B64"}, // 5 + {amdgpu_gfx90a_op_S_WQM_B32,"S_WQM_B32"}, // 6 + {amdgpu_gfx90a_op_S_WQM_B64,"S_WQM_B64"}, // 7 + {amdgpu_gfx90a_op_S_BREV_B32,"S_BREV_B32"}, // 8 + {amdgpu_gfx90a_op_S_BREV_B64,"S_BREV_B64"}, // 9 + {amdgpu_gfx90a_op_S_BCNT0_I32_B32,"S_BCNT0_I32_B32"}, // 10 + {amdgpu_gfx90a_op_S_BCNT0_I32_B64,"S_BCNT0_I32_B64"}, // 11 + {amdgpu_gfx90a_op_S_BCNT1_I32_B32,"S_BCNT1_I32_B32"}, // 12 + {amdgpu_gfx90a_op_S_BCNT1_I32_B64,"S_BCNT1_I32_B64"}, // 13 + {amdgpu_gfx90a_op_S_FF0_I32_B32,"S_FF0_I32_B32"}, // 14 + {amdgpu_gfx90a_op_S_FF0_I32_B64,"S_FF0_I32_B64"}, // 15 + {amdgpu_gfx90a_op_S_FF1_I32_B32,"S_FF1_I32_B32"}, // 16 + {amdgpu_gfx90a_op_S_FF1_I32_B64,"S_FF1_I32_B64"}, // 17 + {amdgpu_gfx90a_op_S_FLBIT_I32_B32,"S_FLBIT_I32_B32"}, // 18 + {amdgpu_gfx90a_op_S_FLBIT_I32_B64,"S_FLBIT_I32_B64"}, // 19 + {amdgpu_gfx90a_op_S_FLBIT_I32,"S_FLBIT_I32"}, // 20 + {amdgpu_gfx90a_op_S_FLBIT_I32_I64,"S_FLBIT_I32_I64"}, // 21 + {amdgpu_gfx90a_op_S_SEXT_I32_I8,"S_SEXT_I32_I8"}, // 22 + {amdgpu_gfx90a_op_S_SEXT_I32_I16,"S_SEXT_I32_I16"}, // 23 + {amdgpu_gfx90a_op_S_BITSET0_B32,"S_BITSET0_B32"}, // 24 + {amdgpu_gfx90a_op_S_BITSET0_B64,"S_BITSET0_B64"}, // 25 + {amdgpu_gfx90a_op_S_BITSET1_B32,"S_BITSET1_B32"}, // 26 + {amdgpu_gfx90a_op_S_BITSET1_B64,"S_BITSET1_B64"}, // 27 + {amdgpu_gfx90a_op_S_GETPC_B64,"S_GETPC_B64"}, // 28 + {amdgpu_gfx90a_op_S_SETPC_B64,"S_SETPC_B64"}, // 29 + {amdgpu_gfx90a_op_S_SWAPPC_B64,"S_SWAPPC_B64"}, // 30 + {amdgpu_gfx90a_op_S_RFE_B64,"S_RFE_B64"}, // 31 + {amdgpu_gfx90a_op_S_AND_SAVEEXEC_B64,"S_AND_SAVEEXEC_B64"}, // 32 + {amdgpu_gfx90a_op_S_OR_SAVEEXEC_B64,"S_OR_SAVEEXEC_B64"}, // 33 + {amdgpu_gfx90a_op_S_XOR_SAVEEXEC_B64,"S_XOR_SAVEEXEC_B64"}, // 34 + {amdgpu_gfx90a_op_S_ANDN2_SAVEEXEC_B64,"S_ANDN2_SAVEEXEC_B64"}, // 35 + {amdgpu_gfx90a_op_S_ORN2_SAVEEXEC_B64,"S_ORN2_SAVEEXEC_B64"}, // 36 + {amdgpu_gfx90a_op_S_NAND_SAVEEXEC_B64,"S_NAND_SAVEEXEC_B64"}, // 37 + {amdgpu_gfx90a_op_S_NOR_SAVEEXEC_B64,"S_NOR_SAVEEXEC_B64"}, // 38 + {amdgpu_gfx90a_op_S_XNOR_SAVEEXEC_B64,"S_XNOR_SAVEEXEC_B64"}, // 39 + {amdgpu_gfx90a_op_S_QUADMASK_B32,"S_QUADMASK_B32"}, // 40 + {amdgpu_gfx90a_op_S_QUADMASK_B64,"S_QUADMASK_B64"}, // 41 + {amdgpu_gfx90a_op_S_MOVRELS_B32,"S_MOVRELS_B32"}, // 42 + {amdgpu_gfx90a_op_S_MOVRELS_B64,"S_MOVRELS_B64"}, // 43 + {amdgpu_gfx90a_op_S_MOVRELD_B32,"S_MOVRELD_B32"}, // 44 + {amdgpu_gfx90a_op_S_MOVRELD_B64,"S_MOVRELD_B64"}, // 45 + {amdgpu_gfx90a_op_S_CBRANCH_JOIN,"S_CBRANCH_JOIN"}, // 46 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 47 + {amdgpu_gfx90a_op_S_ABS_I32,"S_ABS_I32"}, // 48 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 49 + {amdgpu_gfx90a_op_S_SET_GPR_IDX_IDX,"S_SET_GPR_IDX_IDX"}, // 50 + {amdgpu_gfx90a_op_S_ANDN1_SAVEEXEC_B64,"S_ANDN1_SAVEEXEC_B64"}, // 51 + {amdgpu_gfx90a_op_S_ORN1_SAVEEXEC_B64,"S_ORN1_SAVEEXEC_B64"}, // 52 + {amdgpu_gfx90a_op_S_ANDN1_WREXEC_B64,"S_ANDN1_WREXEC_B64"}, // 53 + {amdgpu_gfx90a_op_S_ANDN2_WREXEC_B64,"S_ANDN2_WREXEC_B64"}, // 54 + {amdgpu_gfx90a_op_S_BITREPLICATE_B64_B32,"S_BITREPLICATE_B64_B32"}, // 55 + }; // end ENC_SOP1_insn_table + const amdgpu_gfx90a_insn_entry ENC_SOP2_insn_table[53] = + { + {amdgpu_gfx90a_op_S_ADD_U32,"S_ADD_U32"}, // 0 + {amdgpu_gfx90a_op_S_SUB_U32,"S_SUB_U32"}, // 1 + {amdgpu_gfx90a_op_S_ADD_I32,"S_ADD_I32"}, // 2 + {amdgpu_gfx90a_op_S_SUB_I32,"S_SUB_I32"}, // 3 + {amdgpu_gfx90a_op_S_ADDC_U32,"S_ADDC_U32"}, // 4 + {amdgpu_gfx90a_op_S_SUBB_U32,"S_SUBB_U32"}, // 5 + {amdgpu_gfx90a_op_S_MIN_I32,"S_MIN_I32"}, // 6 + {amdgpu_gfx90a_op_S_MIN_U32,"S_MIN_U32"}, // 7 + {amdgpu_gfx90a_op_S_MAX_I32,"S_MAX_I32"}, // 8 + {amdgpu_gfx90a_op_S_MAX_U32,"S_MAX_U32"}, // 9 + {amdgpu_gfx90a_op_S_CSELECT_B32,"S_CSELECT_B32"}, // 10 + {amdgpu_gfx90a_op_S_CSELECT_B64,"S_CSELECT_B64"}, // 11 + {amdgpu_gfx90a_op_S_AND_B32,"S_AND_B32"}, // 12 + {amdgpu_gfx90a_op_S_AND_B64,"S_AND_B64"}, // 13 + {amdgpu_gfx90a_op_S_OR_B32,"S_OR_B32"}, // 14 + {amdgpu_gfx90a_op_S_OR_B64,"S_OR_B64"}, // 15 + {amdgpu_gfx90a_op_S_XOR_B32,"S_XOR_B32"}, // 16 + {amdgpu_gfx90a_op_S_XOR_B64,"S_XOR_B64"}, // 17 + {amdgpu_gfx90a_op_S_ANDN2_B32,"S_ANDN2_B32"}, // 18 + {amdgpu_gfx90a_op_S_ANDN2_B64,"S_ANDN2_B64"}, // 19 + {amdgpu_gfx90a_op_S_ORN2_B32,"S_ORN2_B32"}, // 20 + {amdgpu_gfx90a_op_S_ORN2_B64,"S_ORN2_B64"}, // 21 + {amdgpu_gfx90a_op_S_NAND_B32,"S_NAND_B32"}, // 22 + {amdgpu_gfx90a_op_S_NAND_B64,"S_NAND_B64"}, // 23 + {amdgpu_gfx90a_op_S_NOR_B32,"S_NOR_B32"}, // 24 + {amdgpu_gfx90a_op_S_NOR_B64,"S_NOR_B64"}, // 25 + {amdgpu_gfx90a_op_S_XNOR_B32,"S_XNOR_B32"}, // 26 + {amdgpu_gfx90a_op_S_XNOR_B64,"S_XNOR_B64"}, // 27 + {amdgpu_gfx90a_op_S_LSHL_B32,"S_LSHL_B32"}, // 28 + {amdgpu_gfx90a_op_S_LSHL_B64,"S_LSHL_B64"}, // 29 + {amdgpu_gfx90a_op_S_LSHR_B32,"S_LSHR_B32"}, // 30 + {amdgpu_gfx90a_op_S_LSHR_B64,"S_LSHR_B64"}, // 31 + {amdgpu_gfx90a_op_S_ASHR_I32,"S_ASHR_I32"}, // 32 + {amdgpu_gfx90a_op_S_ASHR_I64,"S_ASHR_I64"}, // 33 + {amdgpu_gfx90a_op_S_BFM_B32,"S_BFM_B32"}, // 34 + {amdgpu_gfx90a_op_S_BFM_B64,"S_BFM_B64"}, // 35 + {amdgpu_gfx90a_op_S_MUL_I32,"S_MUL_I32"}, // 36 + {amdgpu_gfx90a_op_S_BFE_U32,"S_BFE_U32"}, // 37 + {amdgpu_gfx90a_op_S_BFE_I32,"S_BFE_I32"}, // 38 + {amdgpu_gfx90a_op_S_BFE_U64,"S_BFE_U64"}, // 39 + {amdgpu_gfx90a_op_S_BFE_I64,"S_BFE_I64"}, // 40 + {amdgpu_gfx90a_op_S_CBRANCH_G_FORK,"S_CBRANCH_G_FORK"}, // 41 + {amdgpu_gfx90a_op_S_ABSDIFF_I32,"S_ABSDIFF_I32"}, // 42 + {amdgpu_gfx90a_op_S_RFE_RESTORE_B64,"S_RFE_RESTORE_B64"}, // 43 + {amdgpu_gfx90a_op_S_MUL_HI_U32,"S_MUL_HI_U32"}, // 44 + {amdgpu_gfx90a_op_S_MUL_HI_I32,"S_MUL_HI_I32"}, // 45 + {amdgpu_gfx90a_op_S_LSHL1_ADD_U32,"S_LSHL1_ADD_U32"}, // 46 + {amdgpu_gfx90a_op_S_LSHL2_ADD_U32,"S_LSHL2_ADD_U32"}, // 47 + {amdgpu_gfx90a_op_S_LSHL3_ADD_U32,"S_LSHL3_ADD_U32"}, // 48 + {amdgpu_gfx90a_op_S_LSHL4_ADD_U32,"S_LSHL4_ADD_U32"}, // 49 + {amdgpu_gfx90a_op_S_PACK_LL_B32_B16,"S_PACK_LL_B32_B16"}, // 50 + {amdgpu_gfx90a_op_S_PACK_LH_B32_B16,"S_PACK_LH_B32_B16"}, // 51 + {amdgpu_gfx90a_op_S_PACK_HH_B32_B16,"S_PACK_HH_B32_B16"}, // 52 + }; // end ENC_SOP2_insn_table + const amdgpu_gfx90a_insn_entry ENC_SOPC_insn_table[20] = + { + {amdgpu_gfx90a_op_S_CMP_EQ_I32,"S_CMP_EQ_I32"}, // 0 + {amdgpu_gfx90a_op_S_CMP_LG_I32,"S_CMP_LG_I32"}, // 1 + {amdgpu_gfx90a_op_S_CMP_GT_I32,"S_CMP_GT_I32"}, // 2 + {amdgpu_gfx90a_op_S_CMP_GE_I32,"S_CMP_GE_I32"}, // 3 + {amdgpu_gfx90a_op_S_CMP_LT_I32,"S_CMP_LT_I32"}, // 4 + {amdgpu_gfx90a_op_S_CMP_LE_I32,"S_CMP_LE_I32"}, // 5 + {amdgpu_gfx90a_op_S_CMP_EQ_U32,"S_CMP_EQ_U32"}, // 6 + {amdgpu_gfx90a_op_S_CMP_LG_U32,"S_CMP_LG_U32"}, // 7 + {amdgpu_gfx90a_op_S_CMP_GT_U32,"S_CMP_GT_U32"}, // 8 + {amdgpu_gfx90a_op_S_CMP_GE_U32,"S_CMP_GE_U32"}, // 9 + {amdgpu_gfx90a_op_S_CMP_LT_U32,"S_CMP_LT_U32"}, // 10 + {amdgpu_gfx90a_op_S_CMP_LE_U32,"S_CMP_LE_U32"}, // 11 + {amdgpu_gfx90a_op_S_BITCMP0_B32,"S_BITCMP0_B32"}, // 12 + {amdgpu_gfx90a_op_S_BITCMP1_B32,"S_BITCMP1_B32"}, // 13 + {amdgpu_gfx90a_op_S_BITCMP0_B64,"S_BITCMP0_B64"}, // 14 + {amdgpu_gfx90a_op_S_BITCMP1_B64,"S_BITCMP1_B64"}, // 15 + {amdgpu_gfx90a_op_S_SETVSKIP,"S_SETVSKIP"}, // 16 + {amdgpu_gfx90a_op_S_SET_GPR_IDX_ON,"S_SET_GPR_IDX_ON"}, // 17 + {amdgpu_gfx90a_op_S_CMP_EQ_U64,"S_CMP_EQ_U64"}, // 18 + {amdgpu_gfx90a_op_S_CMP_LG_U64,"S_CMP_LG_U64"}, // 19 + }; // end ENC_SOPC_insn_table + const amdgpu_gfx90a_insn_entry ENC_SOPK_insn_table[22] = + { + {amdgpu_gfx90a_op_S_MOVK_I32,"S_MOVK_I32"}, // 0 + {amdgpu_gfx90a_op_S_CMOVK_I32,"S_CMOVK_I32"}, // 1 + {amdgpu_gfx90a_op_S_CMPK_EQ_I32,"S_CMPK_EQ_I32"}, // 2 + {amdgpu_gfx90a_op_S_CMPK_LG_I32,"S_CMPK_LG_I32"}, // 3 + {amdgpu_gfx90a_op_S_CMPK_GT_I32,"S_CMPK_GT_I32"}, // 4 + {amdgpu_gfx90a_op_S_CMPK_GE_I32,"S_CMPK_GE_I32"}, // 5 + {amdgpu_gfx90a_op_S_CMPK_LT_I32,"S_CMPK_LT_I32"}, // 6 + {amdgpu_gfx90a_op_S_CMPK_LE_I32,"S_CMPK_LE_I32"}, // 7 + {amdgpu_gfx90a_op_S_CMPK_EQ_U32,"S_CMPK_EQ_U32"}, // 8 + {amdgpu_gfx90a_op_S_CMPK_LG_U32,"S_CMPK_LG_U32"}, // 9 + {amdgpu_gfx90a_op_S_CMPK_GT_U32,"S_CMPK_GT_U32"}, // 10 + {amdgpu_gfx90a_op_S_CMPK_GE_U32,"S_CMPK_GE_U32"}, // 11 + {amdgpu_gfx90a_op_S_CMPK_LT_U32,"S_CMPK_LT_U32"}, // 12 + {amdgpu_gfx90a_op_S_CMPK_LE_U32,"S_CMPK_LE_U32"}, // 13 + {amdgpu_gfx90a_op_S_ADDK_I32,"S_ADDK_I32"}, // 14 + {amdgpu_gfx90a_op_S_MULK_I32,"S_MULK_I32"}, // 15 + {amdgpu_gfx90a_op_S_CBRANCH_I_FORK,"S_CBRANCH_I_FORK"}, // 16 + {amdgpu_gfx90a_op_S_GETREG_B32,"S_GETREG_B32"}, // 17 + {amdgpu_gfx90a_op_S_SETREG_B32,"S_SETREG_B32"}, // 18 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 19 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 20 + {amdgpu_gfx90a_op_S_CALL_B64,"S_CALL_B64"}, // 21 + }; // end ENC_SOPK_insn_table + const amdgpu_gfx90a_insn_entry SOPK_INST_LITERAL__insn_table[21] = + { + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 0 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 1 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 2 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 3 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 4 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 5 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 6 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 7 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 8 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 9 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 10 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 11 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 12 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 13 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 14 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 15 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 16 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 17 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 18 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 19 + {amdgpu_gfx90a_op_S_SETREG_IMM32_B32,"S_SETREG_IMM32_B32"}, // 20 + }; // end SOPK_INST_LITERAL__insn_table + const amdgpu_gfx90a_insn_entry ENC_SOPP_insn_table[31] = + { + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 0 + {amdgpu_gfx90a_op_S_ENDPGM,"S_ENDPGM"}, // 1 + {amdgpu_gfx90a_op_S_BRANCH,"S_BRANCH"}, // 2 + {amdgpu_gfx90a_op_S_WAKEUP,"S_WAKEUP"}, // 3 + {amdgpu_gfx90a_op_S_CBRANCH_SCC0,"S_CBRANCH_SCC0"}, // 4 + {amdgpu_gfx90a_op_S_CBRANCH_SCC1,"S_CBRANCH_SCC1"}, // 5 + {amdgpu_gfx90a_op_S_CBRANCH_VCCZ,"S_CBRANCH_VCCZ"}, // 6 + {amdgpu_gfx90a_op_S_CBRANCH_VCCNZ,"S_CBRANCH_VCCNZ"}, // 7 + {amdgpu_gfx90a_op_S_CBRANCH_EXECZ,"S_CBRANCH_EXECZ"}, // 8 + {amdgpu_gfx90a_op_S_CBRANCH_EXECNZ,"S_CBRANCH_EXECNZ"}, // 9 + {amdgpu_gfx90a_op_S_BARRIER,"S_BARRIER"}, // 10 + {amdgpu_gfx90a_op_S_SETKILL,"S_SETKILL"}, // 11 + {amdgpu_gfx90a_op_S_WAITCNT,"S_WAITCNT"}, // 12 + {amdgpu_gfx90a_op_S_SETHALT,"S_SETHALT"}, // 13 + {amdgpu_gfx90a_op_S_SLEEP,"S_SLEEP"}, // 14 + {amdgpu_gfx90a_op_S_SETPRIO,"S_SETPRIO"}, // 15 + {amdgpu_gfx90a_op_S_SENDMSG,"S_SENDMSG"}, // 16 + {amdgpu_gfx90a_op_S_SENDMSGHALT,"S_SENDMSGHALT"}, // 17 + {amdgpu_gfx90a_op_S_TRAP,"S_TRAP"}, // 18 + {amdgpu_gfx90a_op_S_ICACHE_INV,"S_ICACHE_INV"}, // 19 + {amdgpu_gfx90a_op_S_INCPERFLEVEL,"S_INCPERFLEVEL"}, // 20 + {amdgpu_gfx90a_op_S_DECPERFLEVEL,"S_DECPERFLEVEL"}, // 21 + {amdgpu_gfx90a_op_S_TTRACEDATA,"S_TTRACEDATA"}, // 22 + {amdgpu_gfx90a_op_S_CBRANCH_CDBGSYS,"S_CBRANCH_CDBGSYS"}, // 23 + {amdgpu_gfx90a_op_S_CBRANCH_CDBGUSER,"S_CBRANCH_CDBGUSER"}, // 24 + {amdgpu_gfx90a_op_S_CBRANCH_CDBGSYS_OR_USER,"S_CBRANCH_CDBGSYS_OR_USER"}, // 25 + {amdgpu_gfx90a_op_S_CBRANCH_CDBGSYS_AND_USER,"S_CBRANCH_CDBGSYS_AND_USER"}, // 26 + {amdgpu_gfx90a_op_S_ENDPGM_SAVED,"S_ENDPGM_SAVED"}, // 27 + {amdgpu_gfx90a_op_S_SET_GPR_IDX_OFF,"S_SET_GPR_IDX_OFF"}, // 28 + {amdgpu_gfx90a_op_S_SET_GPR_IDX_MODE,"S_SET_GPR_IDX_MODE"}, // 29 + {amdgpu_gfx90a_op_S_ENDPGM_ORDERED_PS_DONE,"S_ENDPGM_ORDERED_PS_DONE"}, // 30 + }; // end ENC_SOPP_insn_table + const amdgpu_gfx90a_insn_entry ENC_VOP1_insn_table[83] = + { + {amdgpu_gfx90a_op_V_NOP,"V_NOP"}, // 0 + {amdgpu_gfx90a_op_V_MOV_B32,"V_MOV_B32"}, // 1 + {amdgpu_gfx90a_op_V_READFIRSTLANE_B32,"V_READFIRSTLANE_B32"}, // 2 + {amdgpu_gfx90a_op_V_CVT_I32_F64,"V_CVT_I32_F64"}, // 3 + {amdgpu_gfx90a_op_V_CVT_F64_I32,"V_CVT_F64_I32"}, // 4 + {amdgpu_gfx90a_op_V_CVT_F32_I32,"V_CVT_F32_I32"}, // 5 + {amdgpu_gfx90a_op_V_CVT_F32_U32,"V_CVT_F32_U32"}, // 6 + {amdgpu_gfx90a_op_V_CVT_U32_F32,"V_CVT_U32_F32"}, // 7 + {amdgpu_gfx90a_op_V_CVT_I32_F32,"V_CVT_I32_F32"}, // 8 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 9 + {amdgpu_gfx90a_op_V_CVT_F16_F32,"V_CVT_F16_F32"}, // 10 + {amdgpu_gfx90a_op_V_CVT_F32_F16,"V_CVT_F32_F16"}, // 11 + {amdgpu_gfx90a_op_V_CVT_RPI_I32_F32,"V_CVT_RPI_I32_F32"}, // 12 + {amdgpu_gfx90a_op_V_CVT_FLR_I32_F32,"V_CVT_FLR_I32_F32"}, // 13 + {amdgpu_gfx90a_op_V_CVT_OFF_F32_I4,"V_CVT_OFF_F32_I4"}, // 14 + {amdgpu_gfx90a_op_V_CVT_F32_F64,"V_CVT_F32_F64"}, // 15 + {amdgpu_gfx90a_op_V_CVT_F64_F32,"V_CVT_F64_F32"}, // 16 + {amdgpu_gfx90a_op_V_CVT_F32_UBYTE0,"V_CVT_F32_UBYTE0"}, // 17 + {amdgpu_gfx90a_op_V_CVT_F32_UBYTE1,"V_CVT_F32_UBYTE1"}, // 18 + {amdgpu_gfx90a_op_V_CVT_F32_UBYTE2,"V_CVT_F32_UBYTE2"}, // 19 + {amdgpu_gfx90a_op_V_CVT_F32_UBYTE3,"V_CVT_F32_UBYTE3"}, // 20 + {amdgpu_gfx90a_op_V_CVT_U32_F64,"V_CVT_U32_F64"}, // 21 + {amdgpu_gfx90a_op_V_CVT_F64_U32,"V_CVT_F64_U32"}, // 22 + {amdgpu_gfx90a_op_V_TRUNC_F64,"V_TRUNC_F64"}, // 23 + {amdgpu_gfx90a_op_V_CEIL_F64,"V_CEIL_F64"}, // 24 + {amdgpu_gfx90a_op_V_RNDNE_F64,"V_RNDNE_F64"}, // 25 + {amdgpu_gfx90a_op_V_FLOOR_F64,"V_FLOOR_F64"}, // 26 + {amdgpu_gfx90a_op_V_FRACT_F32,"V_FRACT_F32"}, // 27 + {amdgpu_gfx90a_op_V_TRUNC_F32,"V_TRUNC_F32"}, // 28 + {amdgpu_gfx90a_op_V_CEIL_F32,"V_CEIL_F32"}, // 29 + {amdgpu_gfx90a_op_V_RNDNE_F32,"V_RNDNE_F32"}, // 30 + {amdgpu_gfx90a_op_V_FLOOR_F32,"V_FLOOR_F32"}, // 31 + {amdgpu_gfx90a_op_V_EXP_F32,"V_EXP_F32"}, // 32 + {amdgpu_gfx90a_op_V_LOG_F32,"V_LOG_F32"}, // 33 + {amdgpu_gfx90a_op_V_RCP_F32,"V_RCP_F32"}, // 34 + {amdgpu_gfx90a_op_V_RCP_IFLAG_F32,"V_RCP_IFLAG_F32"}, // 35 + {amdgpu_gfx90a_op_V_RSQ_F32,"V_RSQ_F32"}, // 36 + {amdgpu_gfx90a_op_V_RCP_F64,"V_RCP_F64"}, // 37 + {amdgpu_gfx90a_op_V_RSQ_F64,"V_RSQ_F64"}, // 38 + {amdgpu_gfx90a_op_V_SQRT_F32,"V_SQRT_F32"}, // 39 + {amdgpu_gfx90a_op_V_SQRT_F64,"V_SQRT_F64"}, // 40 + {amdgpu_gfx90a_op_V_SIN_F32,"V_SIN_F32"}, // 41 + {amdgpu_gfx90a_op_V_COS_F32,"V_COS_F32"}, // 42 + {amdgpu_gfx90a_op_V_NOT_B32,"V_NOT_B32"}, // 43 + {amdgpu_gfx90a_op_V_BFREV_B32,"V_BFREV_B32"}, // 44 + {amdgpu_gfx90a_op_V_FFBH_U32,"V_FFBH_U32"}, // 45 + {amdgpu_gfx90a_op_V_FFBL_B32,"V_FFBL_B32"}, // 46 + {amdgpu_gfx90a_op_V_FFBH_I32,"V_FFBH_I32"}, // 47 + {amdgpu_gfx90a_op_V_FREXP_EXP_I32_F64,"V_FREXP_EXP_I32_F64"}, // 48 + {amdgpu_gfx90a_op_V_FREXP_MANT_F64,"V_FREXP_MANT_F64"}, // 49 + {amdgpu_gfx90a_op_V_FRACT_F64,"V_FRACT_F64"}, // 50 + {amdgpu_gfx90a_op_V_FREXP_EXP_I32_F32,"V_FREXP_EXP_I32_F32"}, // 51 + {amdgpu_gfx90a_op_V_FREXP_MANT_F32,"V_FREXP_MANT_F32"}, // 52 + {amdgpu_gfx90a_op_V_CLREXCP,"V_CLREXCP"}, // 53 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 54 + {amdgpu_gfx90a_op_V_SCREEN_PARTITION_4SE_B32,"V_SCREEN_PARTITION_4SE_B32"}, // 55 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 56 + {amdgpu_gfx90a_op_V_CVT_F16_U16,"V_CVT_F16_U16"}, // 57 + {amdgpu_gfx90a_op_V_CVT_F16_I16,"V_CVT_F16_I16"}, // 58 + {amdgpu_gfx90a_op_V_CVT_U16_F16,"V_CVT_U16_F16"}, // 59 + {amdgpu_gfx90a_op_V_CVT_I16_F16,"V_CVT_I16_F16"}, // 60 + {amdgpu_gfx90a_op_V_RCP_F16,"V_RCP_F16"}, // 61 + {amdgpu_gfx90a_op_V_SQRT_F16,"V_SQRT_F16"}, // 62 + {amdgpu_gfx90a_op_V_RSQ_F16,"V_RSQ_F16"}, // 63 + {amdgpu_gfx90a_op_V_LOG_F16,"V_LOG_F16"}, // 64 + {amdgpu_gfx90a_op_V_EXP_F16,"V_EXP_F16"}, // 65 + {amdgpu_gfx90a_op_V_FREXP_MANT_F16,"V_FREXP_MANT_F16"}, // 66 + {amdgpu_gfx90a_op_V_FREXP_EXP_I16_F16,"V_FREXP_EXP_I16_F16"}, // 67 + {amdgpu_gfx90a_op_V_FLOOR_F16,"V_FLOOR_F16"}, // 68 + {amdgpu_gfx90a_op_V_CEIL_F16,"V_CEIL_F16"}, // 69 + {amdgpu_gfx90a_op_V_TRUNC_F16,"V_TRUNC_F16"}, // 70 + {amdgpu_gfx90a_op_V_RNDNE_F16,"V_RNDNE_F16"}, // 71 + {amdgpu_gfx90a_op_V_FRACT_F16,"V_FRACT_F16"}, // 72 + {amdgpu_gfx90a_op_V_SIN_F16,"V_SIN_F16"}, // 73 + {amdgpu_gfx90a_op_V_COS_F16,"V_COS_F16"}, // 74 + {amdgpu_gfx90a_op_V_EXP_LEGACY_F32,"V_EXP_LEGACY_F32"}, // 75 + {amdgpu_gfx90a_op_V_LOG_LEGACY_F32,"V_LOG_LEGACY_F32"}, // 76 + {amdgpu_gfx90a_op_V_CVT_NORM_I16_F16,"V_CVT_NORM_I16_F16"}, // 77 + {amdgpu_gfx90a_op_V_CVT_NORM_U16_F16,"V_CVT_NORM_U16_F16"}, // 78 + {amdgpu_gfx90a_op_V_SAT_PK_U8_I16,"V_SAT_PK_U8_I16"}, // 79 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 80 + {amdgpu_gfx90a_op_V_SWAP_B32,"V_SWAP_B32"}, // 81 + {amdgpu_gfx90a_op_V_ACCVGPR_MOV_B32,"V_ACCVGPR_MOV_B32"}, // 82 + }; // end ENC_VOP1_insn_table + const amdgpu_gfx90a_insn_entry ENC_VOP3_insn_table[674] = + { + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 0 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 1 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 2 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 3 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 4 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 5 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 6 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 7 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 8 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 9 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 10 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 11 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 12 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 13 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 14 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 15 + {amdgpu_gfx90a_op_V_CMP_CLASS_F32,"V_CMP_CLASS_F32"}, // 16 + {amdgpu_gfx90a_op_V_CMPX_CLASS_F32,"V_CMPX_CLASS_F32"}, // 17 + {amdgpu_gfx90a_op_V_CMP_CLASS_F64,"V_CMP_CLASS_F64"}, // 18 + {amdgpu_gfx90a_op_V_CMPX_CLASS_F64,"V_CMPX_CLASS_F64"}, // 19 + {amdgpu_gfx90a_op_V_CMP_CLASS_F16,"V_CMP_CLASS_F16"}, // 20 + {amdgpu_gfx90a_op_V_CMPX_CLASS_F16,"V_CMPX_CLASS_F16"}, // 21 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 22 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 23 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 24 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 25 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 26 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 27 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 28 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 29 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 30 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 31 + {amdgpu_gfx90a_op_V_CMP_F_F16,"V_CMP_F_F16"}, // 32 + {amdgpu_gfx90a_op_V_CMP_LT_F16,"V_CMP_LT_F16"}, // 33 + {amdgpu_gfx90a_op_V_CMP_EQ_F16,"V_CMP_EQ_F16"}, // 34 + {amdgpu_gfx90a_op_V_CMP_LE_F16,"V_CMP_LE_F16"}, // 35 + {amdgpu_gfx90a_op_V_CMP_GT_F16,"V_CMP_GT_F16"}, // 36 + {amdgpu_gfx90a_op_V_CMP_LG_F16,"V_CMP_LG_F16"}, // 37 + {amdgpu_gfx90a_op_V_CMP_GE_F16,"V_CMP_GE_F16"}, // 38 + {amdgpu_gfx90a_op_V_CMP_O_F16,"V_CMP_O_F16"}, // 39 + {amdgpu_gfx90a_op_V_CMP_U_F16,"V_CMP_U_F16"}, // 40 + {amdgpu_gfx90a_op_V_CMP_NGE_F16,"V_CMP_NGE_F16"}, // 41 + {amdgpu_gfx90a_op_V_CMP_NLG_F16,"V_CMP_NLG_F16"}, // 42 + {amdgpu_gfx90a_op_V_CMP_NGT_F16,"V_CMP_NGT_F16"}, // 43 + {amdgpu_gfx90a_op_V_CMP_NLE_F16,"V_CMP_NLE_F16"}, // 44 + {amdgpu_gfx90a_op_V_CMP_NEQ_F16,"V_CMP_NEQ_F16"}, // 45 + {amdgpu_gfx90a_op_V_CMP_NLT_F16,"V_CMP_NLT_F16"}, // 46 + {amdgpu_gfx90a_op_V_CMP_TRU_F16,"V_CMP_TRU_F16"}, // 47 + {amdgpu_gfx90a_op_V_CMPX_F_F16,"V_CMPX_F_F16"}, // 48 + {amdgpu_gfx90a_op_V_CMPX_LT_F16,"V_CMPX_LT_F16"}, // 49 + {amdgpu_gfx90a_op_V_CMPX_EQ_F16,"V_CMPX_EQ_F16"}, // 50 + {amdgpu_gfx90a_op_V_CMPX_LE_F16,"V_CMPX_LE_F16"}, // 51 + {amdgpu_gfx90a_op_V_CMPX_GT_F16,"V_CMPX_GT_F16"}, // 52 + {amdgpu_gfx90a_op_V_CMPX_LG_F16,"V_CMPX_LG_F16"}, // 53 + {amdgpu_gfx90a_op_V_CMPX_GE_F16,"V_CMPX_GE_F16"}, // 54 + {amdgpu_gfx90a_op_V_CMPX_O_F16,"V_CMPX_O_F16"}, // 55 + {amdgpu_gfx90a_op_V_CMPX_U_F16,"V_CMPX_U_F16"}, // 56 + {amdgpu_gfx90a_op_V_CMPX_NGE_F16,"V_CMPX_NGE_F16"}, // 57 + {amdgpu_gfx90a_op_V_CMPX_NLG_F16,"V_CMPX_NLG_F16"}, // 58 + {amdgpu_gfx90a_op_V_CMPX_NGT_F16,"V_CMPX_NGT_F16"}, // 59 + {amdgpu_gfx90a_op_V_CMPX_NLE_F16,"V_CMPX_NLE_F16"}, // 60 + {amdgpu_gfx90a_op_V_CMPX_NEQ_F16,"V_CMPX_NEQ_F16"}, // 61 + {amdgpu_gfx90a_op_V_CMPX_NLT_F16,"V_CMPX_NLT_F16"}, // 62 + {amdgpu_gfx90a_op_V_CMPX_TRU_F16,"V_CMPX_TRU_F16"}, // 63 + {amdgpu_gfx90a_op_V_CMP_F_F32,"V_CMP_F_F32"}, // 64 + {amdgpu_gfx90a_op_V_CMP_LT_F32,"V_CMP_LT_F32"}, // 65 + {amdgpu_gfx90a_op_V_CMP_EQ_F32,"V_CMP_EQ_F32"}, // 66 + {amdgpu_gfx90a_op_V_CMP_LE_F32,"V_CMP_LE_F32"}, // 67 + {amdgpu_gfx90a_op_V_CMP_GT_F32,"V_CMP_GT_F32"}, // 68 + {amdgpu_gfx90a_op_V_CMP_LG_F32,"V_CMP_LG_F32"}, // 69 + {amdgpu_gfx90a_op_V_CMP_GE_F32,"V_CMP_GE_F32"}, // 70 + {amdgpu_gfx90a_op_V_CMP_O_F32,"V_CMP_O_F32"}, // 71 + {amdgpu_gfx90a_op_V_CMP_U_F32,"V_CMP_U_F32"}, // 72 + {amdgpu_gfx90a_op_V_CMP_NGE_F32,"V_CMP_NGE_F32"}, // 73 + {amdgpu_gfx90a_op_V_CMP_NLG_F32,"V_CMP_NLG_F32"}, // 74 + {amdgpu_gfx90a_op_V_CMP_NGT_F32,"V_CMP_NGT_F32"}, // 75 + {amdgpu_gfx90a_op_V_CMP_NLE_F32,"V_CMP_NLE_F32"}, // 76 + {amdgpu_gfx90a_op_V_CMP_NEQ_F32,"V_CMP_NEQ_F32"}, // 77 + {amdgpu_gfx90a_op_V_CMP_NLT_F32,"V_CMP_NLT_F32"}, // 78 + {amdgpu_gfx90a_op_V_CMP_TRU_F32,"V_CMP_TRU_F32"}, // 79 + {amdgpu_gfx90a_op_V_CMPX_F_F32,"V_CMPX_F_F32"}, // 80 + {amdgpu_gfx90a_op_V_CMPX_LT_F32,"V_CMPX_LT_F32"}, // 81 + {amdgpu_gfx90a_op_V_CMPX_EQ_F32,"V_CMPX_EQ_F32"}, // 82 + {amdgpu_gfx90a_op_V_CMPX_LE_F32,"V_CMPX_LE_F32"}, // 83 + {amdgpu_gfx90a_op_V_CMPX_GT_F32,"V_CMPX_GT_F32"}, // 84 + {amdgpu_gfx90a_op_V_CMPX_LG_F32,"V_CMPX_LG_F32"}, // 85 + {amdgpu_gfx90a_op_V_CMPX_GE_F32,"V_CMPX_GE_F32"}, // 86 + {amdgpu_gfx90a_op_V_CMPX_O_F32,"V_CMPX_O_F32"}, // 87 + {amdgpu_gfx90a_op_V_CMPX_U_F32,"V_CMPX_U_F32"}, // 88 + {amdgpu_gfx90a_op_V_CMPX_NGE_F32,"V_CMPX_NGE_F32"}, // 89 + {amdgpu_gfx90a_op_V_CMPX_NLG_F32,"V_CMPX_NLG_F32"}, // 90 + {amdgpu_gfx90a_op_V_CMPX_NGT_F32,"V_CMPX_NGT_F32"}, // 91 + {amdgpu_gfx90a_op_V_CMPX_NLE_F32,"V_CMPX_NLE_F32"}, // 92 + {amdgpu_gfx90a_op_V_CMPX_NEQ_F32,"V_CMPX_NEQ_F32"}, // 93 + {amdgpu_gfx90a_op_V_CMPX_NLT_F32,"V_CMPX_NLT_F32"}, // 94 + {amdgpu_gfx90a_op_V_CMPX_TRU_F32,"V_CMPX_TRU_F32"}, // 95 + {amdgpu_gfx90a_op_V_CMP_F_F64,"V_CMP_F_F64"}, // 96 + {amdgpu_gfx90a_op_V_CMP_LT_F64,"V_CMP_LT_F64"}, // 97 + {amdgpu_gfx90a_op_V_CMP_EQ_F64,"V_CMP_EQ_F64"}, // 98 + {amdgpu_gfx90a_op_V_CMP_LE_F64,"V_CMP_LE_F64"}, // 99 + {amdgpu_gfx90a_op_V_CMP_GT_F64,"V_CMP_GT_F64"}, // 100 + {amdgpu_gfx90a_op_V_CMP_LG_F64,"V_CMP_LG_F64"}, // 101 + {amdgpu_gfx90a_op_V_CMP_GE_F64,"V_CMP_GE_F64"}, // 102 + {amdgpu_gfx90a_op_V_CMP_O_F64,"V_CMP_O_F64"}, // 103 + {amdgpu_gfx90a_op_V_CMP_U_F64,"V_CMP_U_F64"}, // 104 + {amdgpu_gfx90a_op_V_CMP_NGE_F64,"V_CMP_NGE_F64"}, // 105 + {amdgpu_gfx90a_op_V_CMP_NLG_F64,"V_CMP_NLG_F64"}, // 106 + {amdgpu_gfx90a_op_V_CMP_NGT_F64,"V_CMP_NGT_F64"}, // 107 + {amdgpu_gfx90a_op_V_CMP_NLE_F64,"V_CMP_NLE_F64"}, // 108 + {amdgpu_gfx90a_op_V_CMP_NEQ_F64,"V_CMP_NEQ_F64"}, // 109 + {amdgpu_gfx90a_op_V_CMP_NLT_F64,"V_CMP_NLT_F64"}, // 110 + {amdgpu_gfx90a_op_V_CMP_TRU_F64,"V_CMP_TRU_F64"}, // 111 + {amdgpu_gfx90a_op_V_CMPX_F_F64,"V_CMPX_F_F64"}, // 112 + {amdgpu_gfx90a_op_V_CMPX_LT_F64,"V_CMPX_LT_F64"}, // 113 + {amdgpu_gfx90a_op_V_CMPX_EQ_F64,"V_CMPX_EQ_F64"}, // 114 + {amdgpu_gfx90a_op_V_CMPX_LE_F64,"V_CMPX_LE_F64"}, // 115 + {amdgpu_gfx90a_op_V_CMPX_GT_F64,"V_CMPX_GT_F64"}, // 116 + {amdgpu_gfx90a_op_V_CMPX_LG_F64,"V_CMPX_LG_F64"}, // 117 + {amdgpu_gfx90a_op_V_CMPX_GE_F64,"V_CMPX_GE_F64"}, // 118 + {amdgpu_gfx90a_op_V_CMPX_O_F64,"V_CMPX_O_F64"}, // 119 + {amdgpu_gfx90a_op_V_CMPX_U_F64,"V_CMPX_U_F64"}, // 120 + {amdgpu_gfx90a_op_V_CMPX_NGE_F64,"V_CMPX_NGE_F64"}, // 121 + {amdgpu_gfx90a_op_V_CMPX_NLG_F64,"V_CMPX_NLG_F64"}, // 122 + {amdgpu_gfx90a_op_V_CMPX_NGT_F64,"V_CMPX_NGT_F64"}, // 123 + {amdgpu_gfx90a_op_V_CMPX_NLE_F64,"V_CMPX_NLE_F64"}, // 124 + {amdgpu_gfx90a_op_V_CMPX_NEQ_F64,"V_CMPX_NEQ_F64"}, // 125 + {amdgpu_gfx90a_op_V_CMPX_NLT_F64,"V_CMPX_NLT_F64"}, // 126 + {amdgpu_gfx90a_op_V_CMPX_TRU_F64,"V_CMPX_TRU_F64"}, // 127 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 128 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 129 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 130 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 131 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 132 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 133 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 134 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 135 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 136 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 137 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 138 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 139 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 140 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 141 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 142 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 143 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 144 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 145 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 146 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 147 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 148 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 149 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 150 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 151 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 152 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 153 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 154 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 155 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 156 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 157 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 158 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 159 + {amdgpu_gfx90a_op_V_CMP_F_I16,"V_CMP_F_I16"}, // 160 + {amdgpu_gfx90a_op_V_CMP_LT_I16,"V_CMP_LT_I16"}, // 161 + {amdgpu_gfx90a_op_V_CMP_EQ_I16,"V_CMP_EQ_I16"}, // 162 + {amdgpu_gfx90a_op_V_CMP_LE_I16,"V_CMP_LE_I16"}, // 163 + {amdgpu_gfx90a_op_V_CMP_GT_I16,"V_CMP_GT_I16"}, // 164 + {amdgpu_gfx90a_op_V_CMP_NE_I16,"V_CMP_NE_I16"}, // 165 + {amdgpu_gfx90a_op_V_CMP_GE_I16,"V_CMP_GE_I16"}, // 166 + {amdgpu_gfx90a_op_V_CMP_T_I16,"V_CMP_T_I16"}, // 167 + {amdgpu_gfx90a_op_V_CMP_F_U16,"V_CMP_F_U16"}, // 168 + {amdgpu_gfx90a_op_V_CMP_LT_U16,"V_CMP_LT_U16"}, // 169 + {amdgpu_gfx90a_op_V_CMP_EQ_U16,"V_CMP_EQ_U16"}, // 170 + {amdgpu_gfx90a_op_V_CMP_LE_U16,"V_CMP_LE_U16"}, // 171 + {amdgpu_gfx90a_op_V_CMP_GT_U16,"V_CMP_GT_U16"}, // 172 + {amdgpu_gfx90a_op_V_CMP_NE_U16,"V_CMP_NE_U16"}, // 173 + {amdgpu_gfx90a_op_V_CMP_GE_U16,"V_CMP_GE_U16"}, // 174 + {amdgpu_gfx90a_op_V_CMP_T_U16,"V_CMP_T_U16"}, // 175 + {amdgpu_gfx90a_op_V_CMPX_F_I16,"V_CMPX_F_I16"}, // 176 + {amdgpu_gfx90a_op_V_CMPX_LT_I16,"V_CMPX_LT_I16"}, // 177 + {amdgpu_gfx90a_op_V_CMPX_EQ_I16,"V_CMPX_EQ_I16"}, // 178 + {amdgpu_gfx90a_op_V_CMPX_LE_I16,"V_CMPX_LE_I16"}, // 179 + {amdgpu_gfx90a_op_V_CMPX_GT_I16,"V_CMPX_GT_I16"}, // 180 + {amdgpu_gfx90a_op_V_CMPX_NE_I16,"V_CMPX_NE_I16"}, // 181 + {amdgpu_gfx90a_op_V_CMPX_GE_I16,"V_CMPX_GE_I16"}, // 182 + {amdgpu_gfx90a_op_V_CMPX_T_I16,"V_CMPX_T_I16"}, // 183 + {amdgpu_gfx90a_op_V_CMPX_F_U16,"V_CMPX_F_U16"}, // 184 + {amdgpu_gfx90a_op_V_CMPX_LT_U16,"V_CMPX_LT_U16"}, // 185 + {amdgpu_gfx90a_op_V_CMPX_EQ_U16,"V_CMPX_EQ_U16"}, // 186 + {amdgpu_gfx90a_op_V_CMPX_LE_U16,"V_CMPX_LE_U16"}, // 187 + {amdgpu_gfx90a_op_V_CMPX_GT_U16,"V_CMPX_GT_U16"}, // 188 + {amdgpu_gfx90a_op_V_CMPX_NE_U16,"V_CMPX_NE_U16"}, // 189 + {amdgpu_gfx90a_op_V_CMPX_GE_U16,"V_CMPX_GE_U16"}, // 190 + {amdgpu_gfx90a_op_V_CMPX_T_U16,"V_CMPX_T_U16"}, // 191 + {amdgpu_gfx90a_op_V_CMP_F_I32,"V_CMP_F_I32"}, // 192 + {amdgpu_gfx90a_op_V_CMP_LT_I32,"V_CMP_LT_I32"}, // 193 + {amdgpu_gfx90a_op_V_CMP_EQ_I32,"V_CMP_EQ_I32"}, // 194 + {amdgpu_gfx90a_op_V_CMP_LE_I32,"V_CMP_LE_I32"}, // 195 + {amdgpu_gfx90a_op_V_CMP_GT_I32,"V_CMP_GT_I32"}, // 196 + {amdgpu_gfx90a_op_V_CMP_NE_I32,"V_CMP_NE_I32"}, // 197 + {amdgpu_gfx90a_op_V_CMP_GE_I32,"V_CMP_GE_I32"}, // 198 + {amdgpu_gfx90a_op_V_CMP_T_I32,"V_CMP_T_I32"}, // 199 + {amdgpu_gfx90a_op_V_CMP_F_U32,"V_CMP_F_U32"}, // 200 + {amdgpu_gfx90a_op_V_CMP_LT_U32,"V_CMP_LT_U32"}, // 201 + {amdgpu_gfx90a_op_V_CMP_EQ_U32,"V_CMP_EQ_U32"}, // 202 + {amdgpu_gfx90a_op_V_CMP_LE_U32,"V_CMP_LE_U32"}, // 203 + {amdgpu_gfx90a_op_V_CMP_GT_U32,"V_CMP_GT_U32"}, // 204 + {amdgpu_gfx90a_op_V_CMP_NE_U32,"V_CMP_NE_U32"}, // 205 + {amdgpu_gfx90a_op_V_CMP_GE_U32,"V_CMP_GE_U32"}, // 206 + {amdgpu_gfx90a_op_V_CMP_T_U32,"V_CMP_T_U32"}, // 207 + {amdgpu_gfx90a_op_V_CMPX_F_I32,"V_CMPX_F_I32"}, // 208 + {amdgpu_gfx90a_op_V_CMPX_LT_I32,"V_CMPX_LT_I32"}, // 209 + {amdgpu_gfx90a_op_V_CMPX_EQ_I32,"V_CMPX_EQ_I32"}, // 210 + {amdgpu_gfx90a_op_V_CMPX_LE_I32,"V_CMPX_LE_I32"}, // 211 + {amdgpu_gfx90a_op_V_CMPX_GT_I32,"V_CMPX_GT_I32"}, // 212 + {amdgpu_gfx90a_op_V_CMPX_NE_I32,"V_CMPX_NE_I32"}, // 213 + {amdgpu_gfx90a_op_V_CMPX_GE_I32,"V_CMPX_GE_I32"}, // 214 + {amdgpu_gfx90a_op_V_CMPX_T_I32,"V_CMPX_T_I32"}, // 215 + {amdgpu_gfx90a_op_V_CMPX_F_U32,"V_CMPX_F_U32"}, // 216 + {amdgpu_gfx90a_op_V_CMPX_LT_U32,"V_CMPX_LT_U32"}, // 217 + {amdgpu_gfx90a_op_V_CMPX_EQ_U32,"V_CMPX_EQ_U32"}, // 218 + {amdgpu_gfx90a_op_V_CMPX_LE_U32,"V_CMPX_LE_U32"}, // 219 + {amdgpu_gfx90a_op_V_CMPX_GT_U32,"V_CMPX_GT_U32"}, // 220 + {amdgpu_gfx90a_op_V_CMPX_NE_U32,"V_CMPX_NE_U32"}, // 221 + {amdgpu_gfx90a_op_V_CMPX_GE_U32,"V_CMPX_GE_U32"}, // 222 + {amdgpu_gfx90a_op_V_CMPX_T_U32,"V_CMPX_T_U32"}, // 223 + {amdgpu_gfx90a_op_V_CMP_F_I64,"V_CMP_F_I64"}, // 224 + {amdgpu_gfx90a_op_V_CMP_LT_I64,"V_CMP_LT_I64"}, // 225 + {amdgpu_gfx90a_op_V_CMP_EQ_I64,"V_CMP_EQ_I64"}, // 226 + {amdgpu_gfx90a_op_V_CMP_LE_I64,"V_CMP_LE_I64"}, // 227 + {amdgpu_gfx90a_op_V_CMP_GT_I64,"V_CMP_GT_I64"}, // 228 + {amdgpu_gfx90a_op_V_CMP_NE_I64,"V_CMP_NE_I64"}, // 229 + {amdgpu_gfx90a_op_V_CMP_GE_I64,"V_CMP_GE_I64"}, // 230 + {amdgpu_gfx90a_op_V_CMP_T_I64,"V_CMP_T_I64"}, // 231 + {amdgpu_gfx90a_op_V_CMP_F_U64,"V_CMP_F_U64"}, // 232 + {amdgpu_gfx90a_op_V_CMP_LT_U64,"V_CMP_LT_U64"}, // 233 + {amdgpu_gfx90a_op_V_CMP_EQ_U64,"V_CMP_EQ_U64"}, // 234 + {amdgpu_gfx90a_op_V_CMP_LE_U64,"V_CMP_LE_U64"}, // 235 + {amdgpu_gfx90a_op_V_CMP_GT_U64,"V_CMP_GT_U64"}, // 236 + {amdgpu_gfx90a_op_V_CMP_NE_U64,"V_CMP_NE_U64"}, // 237 + {amdgpu_gfx90a_op_V_CMP_GE_U64,"V_CMP_GE_U64"}, // 238 + {amdgpu_gfx90a_op_V_CMP_T_U64,"V_CMP_T_U64"}, // 239 + {amdgpu_gfx90a_op_V_CMPX_F_I64,"V_CMPX_F_I64"}, // 240 + {amdgpu_gfx90a_op_V_CMPX_LT_I64,"V_CMPX_LT_I64"}, // 241 + {amdgpu_gfx90a_op_V_CMPX_EQ_I64,"V_CMPX_EQ_I64"}, // 242 + {amdgpu_gfx90a_op_V_CMPX_LE_I64,"V_CMPX_LE_I64"}, // 243 + {amdgpu_gfx90a_op_V_CMPX_GT_I64,"V_CMPX_GT_I64"}, // 244 + {amdgpu_gfx90a_op_V_CMPX_NE_I64,"V_CMPX_NE_I64"}, // 245 + {amdgpu_gfx90a_op_V_CMPX_GE_I64,"V_CMPX_GE_I64"}, // 246 + {amdgpu_gfx90a_op_V_CMPX_T_I64,"V_CMPX_T_I64"}, // 247 + {amdgpu_gfx90a_op_V_CMPX_F_U64,"V_CMPX_F_U64"}, // 248 + {amdgpu_gfx90a_op_V_CMPX_LT_U64,"V_CMPX_LT_U64"}, // 249 + {amdgpu_gfx90a_op_V_CMPX_EQ_U64,"V_CMPX_EQ_U64"}, // 250 + {amdgpu_gfx90a_op_V_CMPX_LE_U64,"V_CMPX_LE_U64"}, // 251 + {amdgpu_gfx90a_op_V_CMPX_GT_U64,"V_CMPX_GT_U64"}, // 252 + {amdgpu_gfx90a_op_V_CMPX_NE_U64,"V_CMPX_NE_U64"}, // 253 + {amdgpu_gfx90a_op_V_CMPX_GE_U64,"V_CMPX_GE_U64"}, // 254 + {amdgpu_gfx90a_op_V_CMPX_T_U64,"V_CMPX_T_U64"}, // 255 + {amdgpu_gfx90a_op_V_CNDMASK_B32,"V_CNDMASK_B32"}, // 256 + {amdgpu_gfx90a_op_V_ADD_F32,"V_ADD_F32"}, // 257 + {amdgpu_gfx90a_op_V_SUB_F32,"V_SUB_F32"}, // 258 + {amdgpu_gfx90a_op_V_SUBREV_F32,"V_SUBREV_F32"}, // 259 + {amdgpu_gfx90a_op_V_FMAC_F64,"V_FMAC_F64"}, // 260 + {amdgpu_gfx90a_op_V_MUL_F32,"V_MUL_F32"}, // 261 + {amdgpu_gfx90a_op_V_MUL_I32_I24,"V_MUL_I32_I24"}, // 262 + {amdgpu_gfx90a_op_V_MUL_HI_I32_I24,"V_MUL_HI_I32_I24"}, // 263 + {amdgpu_gfx90a_op_V_MUL_U32_U24,"V_MUL_U32_U24"}, // 264 + {amdgpu_gfx90a_op_V_MUL_HI_U32_U24,"V_MUL_HI_U32_U24"}, // 265 + {amdgpu_gfx90a_op_V_MIN_F32,"V_MIN_F32"}, // 266 + {amdgpu_gfx90a_op_V_MAX_F32,"V_MAX_F32"}, // 267 + {amdgpu_gfx90a_op_V_MIN_I32,"V_MIN_I32"}, // 268 + {amdgpu_gfx90a_op_V_MAX_I32,"V_MAX_I32"}, // 269 + {amdgpu_gfx90a_op_V_MIN_U32,"V_MIN_U32"}, // 270 + {amdgpu_gfx90a_op_V_MAX_U32,"V_MAX_U32"}, // 271 + {amdgpu_gfx90a_op_V_LSHRREV_B32,"V_LSHRREV_B32"}, // 272 + {amdgpu_gfx90a_op_V_ASHRREV_I32,"V_ASHRREV_I32"}, // 273 + {amdgpu_gfx90a_op_V_LSHLREV_B32,"V_LSHLREV_B32"}, // 274 + {amdgpu_gfx90a_op_V_AND_B32,"V_AND_B32"}, // 275 + {amdgpu_gfx90a_op_V_OR_B32,"V_OR_B32"}, // 276 + {amdgpu_gfx90a_op_V_XOR_B32,"V_XOR_B32"}, // 277 + {amdgpu_gfx90a_op_V_MAC_F32,"V_MAC_F32"}, // 278 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 279 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 280 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 281 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 282 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 283 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 284 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 285 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 286 + {amdgpu_gfx90a_op_V_ADD_F16,"V_ADD_F16"}, // 287 + {amdgpu_gfx90a_op_V_SUB_F16,"V_SUB_F16"}, // 288 + {amdgpu_gfx90a_op_V_SUBREV_F16,"V_SUBREV_F16"}, // 289 + {amdgpu_gfx90a_op_V_MUL_F16,"V_MUL_F16"}, // 290 + {amdgpu_gfx90a_op_V_MAC_F16,"V_MAC_F16"}, // 291 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 292 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 293 + {amdgpu_gfx90a_op_V_ADD_U16,"V_ADD_U16"}, // 294 + {amdgpu_gfx90a_op_V_SUB_U16,"V_SUB_U16"}, // 295 + {amdgpu_gfx90a_op_V_SUBREV_U16,"V_SUBREV_U16"}, // 296 + {amdgpu_gfx90a_op_V_MUL_LO_U16,"V_MUL_LO_U16"}, // 297 + {amdgpu_gfx90a_op_V_LSHLREV_B16,"V_LSHLREV_B16"}, // 298 + {amdgpu_gfx90a_op_V_LSHRREV_B16,"V_LSHRREV_B16"}, // 299 + {amdgpu_gfx90a_op_V_ASHRREV_I16,"V_ASHRREV_I16"}, // 300 + {amdgpu_gfx90a_op_V_MAX_F16,"V_MAX_F16"}, // 301 + {amdgpu_gfx90a_op_V_MIN_F16,"V_MIN_F16"}, // 302 + {amdgpu_gfx90a_op_V_MAX_U16,"V_MAX_U16"}, // 303 + {amdgpu_gfx90a_op_V_MAX_I16,"V_MAX_I16"}, // 304 + {amdgpu_gfx90a_op_V_MIN_U16,"V_MIN_U16"}, // 305 + {amdgpu_gfx90a_op_V_MIN_I16,"V_MIN_I16"}, // 306 + {amdgpu_gfx90a_op_V_LDEXP_F16,"V_LDEXP_F16"}, // 307 + {amdgpu_gfx90a_op_V_ADD_U32,"V_ADD_U32"}, // 308 + {amdgpu_gfx90a_op_V_SUB_U32,"V_SUB_U32"}, // 309 + {amdgpu_gfx90a_op_V_SUBREV_U32,"V_SUBREV_U32"}, // 310 + {amdgpu_gfx90a_op_V_DOT2C_F32_F16,"V_DOT2C_F32_F16"}, // 311 + {amdgpu_gfx90a_op_V_DOT2C_I32_I16,"V_DOT2C_I32_I16"}, // 312 + {amdgpu_gfx90a_op_V_DOT4C_I32_I8,"V_DOT4C_I32_I8"}, // 313 + {amdgpu_gfx90a_op_V_DOT8C_I32_I4,"V_DOT8C_I32_I4"}, // 314 + {amdgpu_gfx90a_op_V_FMAC_F32,"V_FMAC_F32"}, // 315 + {amdgpu_gfx90a_op_V_PK_FMAC_F16,"V_PK_FMAC_F16"}, // 316 + {amdgpu_gfx90a_op_V_XNOR_B32,"V_XNOR_B32"}, // 317 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 318 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 319 + {amdgpu_gfx90a_op_V_NOP,"V_NOP"}, // 320 + {amdgpu_gfx90a_op_V_MOV_B32,"V_MOV_B32"}, // 321 + {amdgpu_gfx90a_op_V_READFIRSTLANE_B32,"V_READFIRSTLANE_B32"}, // 322 + {amdgpu_gfx90a_op_V_CVT_I32_F64,"V_CVT_I32_F64"}, // 323 + {amdgpu_gfx90a_op_V_CVT_F64_I32,"V_CVT_F64_I32"}, // 324 + {amdgpu_gfx90a_op_V_CVT_F32_I32,"V_CVT_F32_I32"}, // 325 + {amdgpu_gfx90a_op_V_CVT_F32_U32,"V_CVT_F32_U32"}, // 326 + {amdgpu_gfx90a_op_V_CVT_U32_F32,"V_CVT_U32_F32"}, // 327 + {amdgpu_gfx90a_op_V_CVT_I32_F32,"V_CVT_I32_F32"}, // 328 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 329 + {amdgpu_gfx90a_op_V_CVT_F16_F32,"V_CVT_F16_F32"}, // 330 + {amdgpu_gfx90a_op_V_CVT_F32_F16,"V_CVT_F32_F16"}, // 331 + {amdgpu_gfx90a_op_V_CVT_RPI_I32_F32,"V_CVT_RPI_I32_F32"}, // 332 + {amdgpu_gfx90a_op_V_CVT_FLR_I32_F32,"V_CVT_FLR_I32_F32"}, // 333 + {amdgpu_gfx90a_op_V_CVT_OFF_F32_I4,"V_CVT_OFF_F32_I4"}, // 334 + {amdgpu_gfx90a_op_V_CVT_F32_F64,"V_CVT_F32_F64"}, // 335 + {amdgpu_gfx90a_op_V_CVT_F64_F32,"V_CVT_F64_F32"}, // 336 + {amdgpu_gfx90a_op_V_CVT_F32_UBYTE0,"V_CVT_F32_UBYTE0"}, // 337 + {amdgpu_gfx90a_op_V_CVT_F32_UBYTE1,"V_CVT_F32_UBYTE1"}, // 338 + {amdgpu_gfx90a_op_V_CVT_F32_UBYTE2,"V_CVT_F32_UBYTE2"}, // 339 + {amdgpu_gfx90a_op_V_CVT_F32_UBYTE3,"V_CVT_F32_UBYTE3"}, // 340 + {amdgpu_gfx90a_op_V_CVT_U32_F64,"V_CVT_U32_F64"}, // 341 + {amdgpu_gfx90a_op_V_CVT_F64_U32,"V_CVT_F64_U32"}, // 342 + {amdgpu_gfx90a_op_V_TRUNC_F64,"V_TRUNC_F64"}, // 343 + {amdgpu_gfx90a_op_V_CEIL_F64,"V_CEIL_F64"}, // 344 + {amdgpu_gfx90a_op_V_RNDNE_F64,"V_RNDNE_F64"}, // 345 + {amdgpu_gfx90a_op_V_FLOOR_F64,"V_FLOOR_F64"}, // 346 + {amdgpu_gfx90a_op_V_FRACT_F32,"V_FRACT_F32"}, // 347 + {amdgpu_gfx90a_op_V_TRUNC_F32,"V_TRUNC_F32"}, // 348 + {amdgpu_gfx90a_op_V_CEIL_F32,"V_CEIL_F32"}, // 349 + {amdgpu_gfx90a_op_V_RNDNE_F32,"V_RNDNE_F32"}, // 350 + {amdgpu_gfx90a_op_V_FLOOR_F32,"V_FLOOR_F32"}, // 351 + {amdgpu_gfx90a_op_V_EXP_F32,"V_EXP_F32"}, // 352 + {amdgpu_gfx90a_op_V_LOG_F32,"V_LOG_F32"}, // 353 + {amdgpu_gfx90a_op_V_RCP_F32,"V_RCP_F32"}, // 354 + {amdgpu_gfx90a_op_V_RCP_IFLAG_F32,"V_RCP_IFLAG_F32"}, // 355 + {amdgpu_gfx90a_op_V_RSQ_F32,"V_RSQ_F32"}, // 356 + {amdgpu_gfx90a_op_V_RCP_F64,"V_RCP_F64"}, // 357 + {amdgpu_gfx90a_op_V_RSQ_F64,"V_RSQ_F64"}, // 358 + {amdgpu_gfx90a_op_V_SQRT_F32,"V_SQRT_F32"}, // 359 + {amdgpu_gfx90a_op_V_SQRT_F64,"V_SQRT_F64"}, // 360 + {amdgpu_gfx90a_op_V_SIN_F32,"V_SIN_F32"}, // 361 + {amdgpu_gfx90a_op_V_COS_F32,"V_COS_F32"}, // 362 + {amdgpu_gfx90a_op_V_NOT_B32,"V_NOT_B32"}, // 363 + {amdgpu_gfx90a_op_V_BFREV_B32,"V_BFREV_B32"}, // 364 + {amdgpu_gfx90a_op_V_FFBH_U32,"V_FFBH_U32"}, // 365 + {amdgpu_gfx90a_op_V_FFBL_B32,"V_FFBL_B32"}, // 366 + {amdgpu_gfx90a_op_V_FFBH_I32,"V_FFBH_I32"}, // 367 + {amdgpu_gfx90a_op_V_FREXP_EXP_I32_F64,"V_FREXP_EXP_I32_F64"}, // 368 + {amdgpu_gfx90a_op_V_FREXP_MANT_F64,"V_FREXP_MANT_F64"}, // 369 + {amdgpu_gfx90a_op_V_FRACT_F64,"V_FRACT_F64"}, // 370 + {amdgpu_gfx90a_op_V_FREXP_EXP_I32_F32,"V_FREXP_EXP_I32_F32"}, // 371 + {amdgpu_gfx90a_op_V_FREXP_MANT_F32,"V_FREXP_MANT_F32"}, // 372 + {amdgpu_gfx90a_op_V_CLREXCP,"V_CLREXCP"}, // 373 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 374 + {amdgpu_gfx90a_op_V_SCREEN_PARTITION_4SE_B32,"V_SCREEN_PARTITION_4SE_B32"}, // 375 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 376 + {amdgpu_gfx90a_op_V_CVT_F16_U16,"V_CVT_F16_U16"}, // 377 + {amdgpu_gfx90a_op_V_CVT_F16_I16,"V_CVT_F16_I16"}, // 378 + {amdgpu_gfx90a_op_V_CVT_U16_F16,"V_CVT_U16_F16"}, // 379 + {amdgpu_gfx90a_op_V_CVT_I16_F16,"V_CVT_I16_F16"}, // 380 + {amdgpu_gfx90a_op_V_RCP_F16,"V_RCP_F16"}, // 381 + {amdgpu_gfx90a_op_V_SQRT_F16,"V_SQRT_F16"}, // 382 + {amdgpu_gfx90a_op_V_RSQ_F16,"V_RSQ_F16"}, // 383 + {amdgpu_gfx90a_op_V_LOG_F16,"V_LOG_F16"}, // 384 + {amdgpu_gfx90a_op_V_EXP_F16,"V_EXP_F16"}, // 385 + {amdgpu_gfx90a_op_V_FREXP_MANT_F16,"V_FREXP_MANT_F16"}, // 386 + {amdgpu_gfx90a_op_V_FREXP_EXP_I16_F16,"V_FREXP_EXP_I16_F16"}, // 387 + {amdgpu_gfx90a_op_V_FLOOR_F16,"V_FLOOR_F16"}, // 388 + {amdgpu_gfx90a_op_V_CEIL_F16,"V_CEIL_F16"}, // 389 + {amdgpu_gfx90a_op_V_TRUNC_F16,"V_TRUNC_F16"}, // 390 + {amdgpu_gfx90a_op_V_RNDNE_F16,"V_RNDNE_F16"}, // 391 + {amdgpu_gfx90a_op_V_FRACT_F16,"V_FRACT_F16"}, // 392 + {amdgpu_gfx90a_op_V_SIN_F16,"V_SIN_F16"}, // 393 + {amdgpu_gfx90a_op_V_COS_F16,"V_COS_F16"}, // 394 + {amdgpu_gfx90a_op_V_EXP_LEGACY_F32,"V_EXP_LEGACY_F32"}, // 395 + {amdgpu_gfx90a_op_V_LOG_LEGACY_F32,"V_LOG_LEGACY_F32"}, // 396 + {amdgpu_gfx90a_op_V_CVT_NORM_I16_F16,"V_CVT_NORM_I16_F16"}, // 397 + {amdgpu_gfx90a_op_V_CVT_NORM_U16_F16,"V_CVT_NORM_U16_F16"}, // 398 + {amdgpu_gfx90a_op_V_SAT_PK_U8_I16,"V_SAT_PK_U8_I16"}, // 399 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 400 + {amdgpu_gfx90a_op_V_SWAP_B32,"V_SWAP_B32"}, // 401 + {amdgpu_gfx90a_op_V_ACCVGPR_MOV_B32,"V_ACCVGPR_MOV_B32"}, // 402 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 403 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 404 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 405 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 406 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 407 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 408 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 409 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 410 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 411 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 412 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 413 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 414 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 415 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 416 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 417 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 418 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 419 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 420 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 421 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 422 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 423 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 424 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 425 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 426 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 427 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 428 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 429 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 430 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 431 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 432 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 433 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 434 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 435 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 436 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 437 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 438 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 439 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 440 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 441 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 442 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 443 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 444 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 445 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 446 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 447 + {amdgpu_gfx90a_op_V_MAD_LEGACY_F32,"V_MAD_LEGACY_F32"}, // 448 + {amdgpu_gfx90a_op_V_MAD_F32,"V_MAD_F32"}, // 449 + {amdgpu_gfx90a_op_V_MAD_I32_I24,"V_MAD_I32_I24"}, // 450 + {amdgpu_gfx90a_op_V_MAD_U32_U24,"V_MAD_U32_U24"}, // 451 + {amdgpu_gfx90a_op_V_CUBEID_F32,"V_CUBEID_F32"}, // 452 + {amdgpu_gfx90a_op_V_CUBESC_F32,"V_CUBESC_F32"}, // 453 + {amdgpu_gfx90a_op_V_CUBETC_F32,"V_CUBETC_F32"}, // 454 + {amdgpu_gfx90a_op_V_CUBEMA_F32,"V_CUBEMA_F32"}, // 455 + {amdgpu_gfx90a_op_V_BFE_U32,"V_BFE_U32"}, // 456 + {amdgpu_gfx90a_op_V_BFE_I32,"V_BFE_I32"}, // 457 + {amdgpu_gfx90a_op_V_BFI_B32,"V_BFI_B32"}, // 458 + {amdgpu_gfx90a_op_V_FMA_F32,"V_FMA_F32"}, // 459 + {amdgpu_gfx90a_op_V_FMA_F64,"V_FMA_F64"}, // 460 + {amdgpu_gfx90a_op_V_LERP_U8,"V_LERP_U8"}, // 461 + {amdgpu_gfx90a_op_V_ALIGNBIT_B32,"V_ALIGNBIT_B32"}, // 462 + {amdgpu_gfx90a_op_V_ALIGNBYTE_B32,"V_ALIGNBYTE_B32"}, // 463 + {amdgpu_gfx90a_op_V_MIN3_F32,"V_MIN3_F32"}, // 464 + {amdgpu_gfx90a_op_V_MIN3_I32,"V_MIN3_I32"}, // 465 + {amdgpu_gfx90a_op_V_MIN3_U32,"V_MIN3_U32"}, // 466 + {amdgpu_gfx90a_op_V_MAX3_F32,"V_MAX3_F32"}, // 467 + {amdgpu_gfx90a_op_V_MAX3_I32,"V_MAX3_I32"}, // 468 + {amdgpu_gfx90a_op_V_MAX3_U32,"V_MAX3_U32"}, // 469 + {amdgpu_gfx90a_op_V_MED3_F32,"V_MED3_F32"}, // 470 + {amdgpu_gfx90a_op_V_MED3_I32,"V_MED3_I32"}, // 471 + {amdgpu_gfx90a_op_V_MED3_U32,"V_MED3_U32"}, // 472 + {amdgpu_gfx90a_op_V_SAD_U8,"V_SAD_U8"}, // 473 + {amdgpu_gfx90a_op_V_SAD_HI_U8,"V_SAD_HI_U8"}, // 474 + {amdgpu_gfx90a_op_V_SAD_U16,"V_SAD_U16"}, // 475 + {amdgpu_gfx90a_op_V_SAD_U32,"V_SAD_U32"}, // 476 + {amdgpu_gfx90a_op_V_CVT_PK_U8_F32,"V_CVT_PK_U8_F32"}, // 477 + {amdgpu_gfx90a_op_V_DIV_FIXUP_F32,"V_DIV_FIXUP_F32"}, // 478 + {amdgpu_gfx90a_op_V_DIV_FIXUP_F64,"V_DIV_FIXUP_F64"}, // 479 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 480 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 481 + {amdgpu_gfx90a_op_V_DIV_FMAS_F32,"V_DIV_FMAS_F32"}, // 482 + {amdgpu_gfx90a_op_V_DIV_FMAS_F64,"V_DIV_FMAS_F64"}, // 483 + {amdgpu_gfx90a_op_V_MSAD_U8,"V_MSAD_U8"}, // 484 + {amdgpu_gfx90a_op_V_QSAD_PK_U16_U8,"V_QSAD_PK_U16_U8"}, // 485 + {amdgpu_gfx90a_op_V_MQSAD_PK_U16_U8,"V_MQSAD_PK_U16_U8"}, // 486 + {amdgpu_gfx90a_op_V_MQSAD_U32_U8,"V_MQSAD_U32_U8"}, // 487 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 488 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 489 + {amdgpu_gfx90a_op_V_MAD_LEGACY_F16,"V_MAD_LEGACY_F16"}, // 490 + {amdgpu_gfx90a_op_V_MAD_LEGACY_U16,"V_MAD_LEGACY_U16"}, // 491 + {amdgpu_gfx90a_op_V_MAD_LEGACY_I16,"V_MAD_LEGACY_I16"}, // 492 + {amdgpu_gfx90a_op_V_PERM_B32,"V_PERM_B32"}, // 493 + {amdgpu_gfx90a_op_V_FMA_LEGACY_F16,"V_FMA_LEGACY_F16"}, // 494 + {amdgpu_gfx90a_op_V_DIV_FIXUP_LEGACY_F16,"V_DIV_FIXUP_LEGACY_F16"}, // 495 + {amdgpu_gfx90a_op_V_CVT_PKACCUM_U8_F32,"V_CVT_PKACCUM_U8_F32"}, // 496 + {amdgpu_gfx90a_op_V_MAD_U32_U16,"V_MAD_U32_U16"}, // 497 + {amdgpu_gfx90a_op_V_MAD_I32_I16,"V_MAD_I32_I16"}, // 498 + {amdgpu_gfx90a_op_V_XAD_U32,"V_XAD_U32"}, // 499 + {amdgpu_gfx90a_op_V_MIN3_F16,"V_MIN3_F16"}, // 500 + {amdgpu_gfx90a_op_V_MIN3_I16,"V_MIN3_I16"}, // 501 + {amdgpu_gfx90a_op_V_MIN3_U16,"V_MIN3_U16"}, // 502 + {amdgpu_gfx90a_op_V_MAX3_F16,"V_MAX3_F16"}, // 503 + {amdgpu_gfx90a_op_V_MAX3_I16,"V_MAX3_I16"}, // 504 + {amdgpu_gfx90a_op_V_MAX3_U16,"V_MAX3_U16"}, // 505 + {amdgpu_gfx90a_op_V_MED3_F16,"V_MED3_F16"}, // 506 + {amdgpu_gfx90a_op_V_MED3_I16,"V_MED3_I16"}, // 507 + {amdgpu_gfx90a_op_V_MED3_U16,"V_MED3_U16"}, // 508 + {amdgpu_gfx90a_op_V_LSHL_ADD_U32,"V_LSHL_ADD_U32"}, // 509 + {amdgpu_gfx90a_op_V_ADD_LSHL_U32,"V_ADD_LSHL_U32"}, // 510 + {amdgpu_gfx90a_op_V_ADD3_U32,"V_ADD3_U32"}, // 511 + {amdgpu_gfx90a_op_V_LSHL_OR_B32,"V_LSHL_OR_B32"}, // 512 + {amdgpu_gfx90a_op_V_AND_OR_B32,"V_AND_OR_B32"}, // 513 + {amdgpu_gfx90a_op_V_OR3_B32,"V_OR3_B32"}, // 514 + {amdgpu_gfx90a_op_V_MAD_F16,"V_MAD_F16"}, // 515 + {amdgpu_gfx90a_op_V_MAD_U16,"V_MAD_U16"}, // 516 + {amdgpu_gfx90a_op_V_MAD_I16,"V_MAD_I16"}, // 517 + {amdgpu_gfx90a_op_V_FMA_F16,"V_FMA_F16"}, // 518 + {amdgpu_gfx90a_op_V_DIV_FIXUP_F16,"V_DIV_FIXUP_F16"}, // 519 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 520 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 521 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 522 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 523 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 524 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 525 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 526 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 527 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 528 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 529 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 530 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 531 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 532 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 533 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 534 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 535 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 536 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 537 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 538 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 539 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 540 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 541 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 542 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 543 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 544 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 545 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 546 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 547 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 548 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 549 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 550 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 551 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 552 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 553 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 554 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 555 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 556 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 557 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 558 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 559 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 560 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 561 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 562 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 563 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 564 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 565 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 566 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 567 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 568 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 569 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 570 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 571 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 572 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 573 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 574 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 575 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 576 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 577 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 578 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 579 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 580 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 581 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 582 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 583 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 584 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 585 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 586 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 587 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 588 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 589 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 590 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 591 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 592 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 593 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 594 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 595 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 596 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 597 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 598 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 599 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 600 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 601 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 602 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 603 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 604 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 605 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 606 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 607 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 608 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 609 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 610 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 611 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 612 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 613 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 614 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 615 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 616 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 617 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 618 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 619 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 620 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 621 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 622 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 623 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 624 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 625 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 626 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 627 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 628 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 629 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 630 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 631 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 632 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 633 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 634 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 635 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 636 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 637 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 638 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 639 + {amdgpu_gfx90a_op_V_ADD_F64,"V_ADD_F64"}, // 640 + {amdgpu_gfx90a_op_V_MUL_F64,"V_MUL_F64"}, // 641 + {amdgpu_gfx90a_op_V_MIN_F64,"V_MIN_F64"}, // 642 + {amdgpu_gfx90a_op_V_MAX_F64,"V_MAX_F64"}, // 643 + {amdgpu_gfx90a_op_V_LDEXP_F64,"V_LDEXP_F64"}, // 644 + {amdgpu_gfx90a_op_V_MUL_LO_U32,"V_MUL_LO_U32"}, // 645 + {amdgpu_gfx90a_op_V_MUL_HI_U32,"V_MUL_HI_U32"}, // 646 + {amdgpu_gfx90a_op_V_MUL_HI_I32,"V_MUL_HI_I32"}, // 647 + {amdgpu_gfx90a_op_V_LDEXP_F32,"V_LDEXP_F32"}, // 648 + {amdgpu_gfx90a_op_V_READLANE_B32,"V_READLANE_B32"}, // 649 + {amdgpu_gfx90a_op_V_WRITELANE_B32,"V_WRITELANE_B32"}, // 650 + {amdgpu_gfx90a_op_V_BCNT_U32_B32,"V_BCNT_U32_B32"}, // 651 + {amdgpu_gfx90a_op_V_MBCNT_LO_U32_B32,"V_MBCNT_LO_U32_B32"}, // 652 + {amdgpu_gfx90a_op_V_MBCNT_HI_U32_B32,"V_MBCNT_HI_U32_B32"}, // 653 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 654 + {amdgpu_gfx90a_op_V_LSHLREV_B64,"V_LSHLREV_B64"}, // 655 + {amdgpu_gfx90a_op_V_LSHRREV_B64,"V_LSHRREV_B64"}, // 656 + {amdgpu_gfx90a_op_V_ASHRREV_I64,"V_ASHRREV_I64"}, // 657 + {amdgpu_gfx90a_op_V_TRIG_PREOP_F64,"V_TRIG_PREOP_F64"}, // 658 + {amdgpu_gfx90a_op_V_BFM_B32,"V_BFM_B32"}, // 659 + {amdgpu_gfx90a_op_V_CVT_PKNORM_I16_F32,"V_CVT_PKNORM_I16_F32"}, // 660 + {amdgpu_gfx90a_op_V_CVT_PKNORM_U16_F32,"V_CVT_PKNORM_U16_F32"}, // 661 + {amdgpu_gfx90a_op_V_CVT_PKRTZ_F16_F32,"V_CVT_PKRTZ_F16_F32"}, // 662 + {amdgpu_gfx90a_op_V_CVT_PK_U16_U32,"V_CVT_PK_U16_U32"}, // 663 + {amdgpu_gfx90a_op_V_CVT_PK_I16_I32,"V_CVT_PK_I16_I32"}, // 664 + {amdgpu_gfx90a_op_V_CVT_PKNORM_I16_F16,"V_CVT_PKNORM_I16_F16"}, // 665 + {amdgpu_gfx90a_op_V_CVT_PKNORM_U16_F16,"V_CVT_PKNORM_U16_F16"}, // 666 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 667 + {amdgpu_gfx90a_op_V_ADD_I32,"V_ADD_I32"}, // 668 + {amdgpu_gfx90a_op_V_SUB_I32,"V_SUB_I32"}, // 669 + {amdgpu_gfx90a_op_V_ADD_I16,"V_ADD_I16"}, // 670 + {amdgpu_gfx90a_op_V_SUB_I16,"V_SUB_I16"}, // 671 + {amdgpu_gfx90a_op_V_PACK_B32_F16,"V_PACK_B32_F16"}, // 672 + {amdgpu_gfx90a_op_V_MUL_LEGACY_F32,"V_MUL_LEGACY_F32"}, // 673 + }; // end ENC_VOP3_insn_table + const amdgpu_gfx90a_insn_entry ENC_VOP2_insn_table[62] = + { + {amdgpu_gfx90a_op_V_CNDMASK_B32,"V_CNDMASK_B32"}, // 0 + {amdgpu_gfx90a_op_V_ADD_F32,"V_ADD_F32"}, // 1 + {amdgpu_gfx90a_op_V_SUB_F32,"V_SUB_F32"}, // 2 + {amdgpu_gfx90a_op_V_SUBREV_F32,"V_SUBREV_F32"}, // 3 + {amdgpu_gfx90a_op_V_FMAC_F64,"V_FMAC_F64"}, // 4 + {amdgpu_gfx90a_op_V_MUL_F32,"V_MUL_F32"}, // 5 + {amdgpu_gfx90a_op_V_MUL_I32_I24,"V_MUL_I32_I24"}, // 6 + {amdgpu_gfx90a_op_V_MUL_HI_I32_I24,"V_MUL_HI_I32_I24"}, // 7 + {amdgpu_gfx90a_op_V_MUL_U32_U24,"V_MUL_U32_U24"}, // 8 + {amdgpu_gfx90a_op_V_MUL_HI_U32_U24,"V_MUL_HI_U32_U24"}, // 9 + {amdgpu_gfx90a_op_V_MIN_F32,"V_MIN_F32"}, // 10 + {amdgpu_gfx90a_op_V_MAX_F32,"V_MAX_F32"}, // 11 + {amdgpu_gfx90a_op_V_MIN_I32,"V_MIN_I32"}, // 12 + {amdgpu_gfx90a_op_V_MAX_I32,"V_MAX_I32"}, // 13 + {amdgpu_gfx90a_op_V_MIN_U32,"V_MIN_U32"}, // 14 + {amdgpu_gfx90a_op_V_MAX_U32,"V_MAX_U32"}, // 15 + {amdgpu_gfx90a_op_V_LSHRREV_B32,"V_LSHRREV_B32"}, // 16 + {amdgpu_gfx90a_op_V_ASHRREV_I32,"V_ASHRREV_I32"}, // 17 + {amdgpu_gfx90a_op_V_LSHLREV_B32,"V_LSHLREV_B32"}, // 18 + {amdgpu_gfx90a_op_V_AND_B32,"V_AND_B32"}, // 19 + {amdgpu_gfx90a_op_V_OR_B32,"V_OR_B32"}, // 20 + {amdgpu_gfx90a_op_V_XOR_B32,"V_XOR_B32"}, // 21 + {amdgpu_gfx90a_op_V_MAC_F32,"V_MAC_F32"}, // 22 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 23 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 24 + {amdgpu_gfx90a_op_V_ADD_CO_U32,"V_ADD_CO_U32"}, // 25 + {amdgpu_gfx90a_op_V_SUB_CO_U32,"V_SUB_CO_U32"}, // 26 + {amdgpu_gfx90a_op_V_SUBREV_CO_U32,"V_SUBREV_CO_U32"}, // 27 + {amdgpu_gfx90a_op_V_ADDC_CO_U32,"V_ADDC_CO_U32"}, // 28 + {amdgpu_gfx90a_op_V_SUBB_CO_U32,"V_SUBB_CO_U32"}, // 29 + {amdgpu_gfx90a_op_V_SUBBREV_CO_U32,"V_SUBBREV_CO_U32"}, // 30 + {amdgpu_gfx90a_op_V_ADD_F16,"V_ADD_F16"}, // 31 + {amdgpu_gfx90a_op_V_SUB_F16,"V_SUB_F16"}, // 32 + {amdgpu_gfx90a_op_V_SUBREV_F16,"V_SUBREV_F16"}, // 33 + {amdgpu_gfx90a_op_V_MUL_F16,"V_MUL_F16"}, // 34 + {amdgpu_gfx90a_op_V_MAC_F16,"V_MAC_F16"}, // 35 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 36 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 37 + {amdgpu_gfx90a_op_V_ADD_U16,"V_ADD_U16"}, // 38 + {amdgpu_gfx90a_op_V_SUB_U16,"V_SUB_U16"}, // 39 + {amdgpu_gfx90a_op_V_SUBREV_U16,"V_SUBREV_U16"}, // 40 + {amdgpu_gfx90a_op_V_MUL_LO_U16,"V_MUL_LO_U16"}, // 41 + {amdgpu_gfx90a_op_V_LSHLREV_B16,"V_LSHLREV_B16"}, // 42 + {amdgpu_gfx90a_op_V_LSHRREV_B16,"V_LSHRREV_B16"}, // 43 + {amdgpu_gfx90a_op_V_ASHRREV_I16,"V_ASHRREV_I16"}, // 44 + {amdgpu_gfx90a_op_V_MAX_F16,"V_MAX_F16"}, // 45 + {amdgpu_gfx90a_op_V_MIN_F16,"V_MIN_F16"}, // 46 + {amdgpu_gfx90a_op_V_MAX_U16,"V_MAX_U16"}, // 47 + {amdgpu_gfx90a_op_V_MAX_I16,"V_MAX_I16"}, // 48 + {amdgpu_gfx90a_op_V_MIN_U16,"V_MIN_U16"}, // 49 + {amdgpu_gfx90a_op_V_MIN_I16,"V_MIN_I16"}, // 50 + {amdgpu_gfx90a_op_V_LDEXP_F16,"V_LDEXP_F16"}, // 51 + {amdgpu_gfx90a_op_V_ADD_U32,"V_ADD_U32"}, // 52 + {amdgpu_gfx90a_op_V_SUB_U32,"V_SUB_U32"}, // 53 + {amdgpu_gfx90a_op_V_SUBREV_U32,"V_SUBREV_U32"}, // 54 + {amdgpu_gfx90a_op_V_DOT2C_F32_F16,"V_DOT2C_F32_F16"}, // 55 + {amdgpu_gfx90a_op_V_DOT2C_I32_I16,"V_DOT2C_I32_I16"}, // 56 + {amdgpu_gfx90a_op_V_DOT4C_I32_I8,"V_DOT4C_I32_I8"}, // 57 + {amdgpu_gfx90a_op_V_DOT8C_I32_I4,"V_DOT8C_I32_I4"}, // 58 + {amdgpu_gfx90a_op_V_FMAC_F32,"V_FMAC_F32"}, // 59 + {amdgpu_gfx90a_op_V_PK_FMAC_F16,"V_PK_FMAC_F16"}, // 60 + {amdgpu_gfx90a_op_V_XNOR_B32,"V_XNOR_B32"}, // 61 + }; // end ENC_VOP2_insn_table + const amdgpu_gfx90a_insn_entry ENC_VOP2_LITERAL_insn_table[38] = + { + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 0 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 1 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 2 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 3 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 4 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 5 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 6 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 7 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 8 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 9 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 10 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 11 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 12 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 13 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 14 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 15 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 16 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 17 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 18 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 19 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 20 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 21 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 22 + {amdgpu_gfx90a_op_V_MADMK_F32,"V_MADMK_F32"}, // 23 + {amdgpu_gfx90a_op_V_MADAK_F32,"V_MADAK_F32"}, // 24 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 25 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 26 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 27 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 28 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 29 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 30 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 31 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 32 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 33 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 34 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 35 + {amdgpu_gfx90a_op_V_MADMK_F16,"V_MADMK_F16"}, // 36 + {amdgpu_gfx90a_op_V_MADAK_F16,"V_MADAK_F16"}, // 37 + }; // end ENC_VOP2_LITERAL_insn_table + const amdgpu_gfx90a_insn_entry ENC_VOP3B_insn_table[490] = + { + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 0 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 1 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 2 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 3 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 4 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 5 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 6 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 7 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 8 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 9 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 10 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 11 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 12 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 13 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 14 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 15 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 16 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 17 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 18 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 19 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 20 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 21 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 22 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 23 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 24 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 25 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 26 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 27 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 28 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 29 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 30 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 31 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 32 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 33 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 34 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 35 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 36 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 37 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 38 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 39 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 40 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 41 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 42 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 43 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 44 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 45 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 46 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 47 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 48 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 49 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 50 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 51 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 52 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 53 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 54 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 55 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 56 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 57 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 58 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 59 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 60 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 61 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 62 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 63 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 64 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 65 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 66 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 67 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 68 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 69 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 70 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 71 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 72 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 73 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 74 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 75 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 76 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 77 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 78 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 79 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 80 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 81 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 82 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 83 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 84 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 85 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 86 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 87 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 88 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 89 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 90 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 91 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 92 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 93 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 94 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 95 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 96 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 97 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 98 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 99 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 100 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 101 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 102 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 103 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 104 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 105 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 106 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 107 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 108 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 109 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 110 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 111 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 112 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 113 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 114 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 115 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 116 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 117 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 118 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 119 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 120 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 121 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 122 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 123 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 124 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 125 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 126 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 127 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 128 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 129 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 130 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 131 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 132 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 133 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 134 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 135 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 136 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 137 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 138 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 139 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 140 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 141 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 142 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 143 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 144 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 145 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 146 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 147 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 148 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 149 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 150 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 151 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 152 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 153 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 154 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 155 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 156 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 157 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 158 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 159 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 160 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 161 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 162 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 163 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 164 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 165 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 166 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 167 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 168 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 169 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 170 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 171 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 172 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 173 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 174 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 175 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 176 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 177 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 178 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 179 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 180 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 181 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 182 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 183 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 184 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 185 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 186 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 187 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 188 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 189 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 190 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 191 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 192 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 193 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 194 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 195 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 196 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 197 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 198 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 199 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 200 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 201 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 202 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 203 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 204 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 205 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 206 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 207 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 208 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 209 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 210 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 211 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 212 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 213 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 214 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 215 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 216 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 217 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 218 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 219 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 220 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 221 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 222 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 223 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 224 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 225 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 226 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 227 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 228 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 229 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 230 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 231 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 232 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 233 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 234 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 235 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 236 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 237 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 238 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 239 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 240 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 241 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 242 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 243 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 244 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 245 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 246 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 247 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 248 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 249 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 250 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 251 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 252 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 253 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 254 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 255 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 256 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 257 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 258 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 259 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 260 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 261 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 262 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 263 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 264 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 265 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 266 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 267 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 268 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 269 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 270 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 271 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 272 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 273 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 274 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 275 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 276 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 277 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 278 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 279 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 280 + {amdgpu_gfx90a_op_V_ADD_CO_U32,"V_ADD_CO_U32"}, // 281 + {amdgpu_gfx90a_op_V_SUB_CO_U32,"V_SUB_CO_U32"}, // 282 + {amdgpu_gfx90a_op_V_SUBREV_CO_U32,"V_SUBREV_CO_U32"}, // 283 + {amdgpu_gfx90a_op_V_ADDC_CO_U32,"V_ADDC_CO_U32"}, // 284 + {amdgpu_gfx90a_op_V_SUBB_CO_U32,"V_SUBB_CO_U32"}, // 285 + {amdgpu_gfx90a_op_V_SUBBREV_CO_U32,"V_SUBBREV_CO_U32"}, // 286 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 287 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 288 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 289 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 290 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 291 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 292 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 293 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 294 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 295 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 296 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 297 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 298 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 299 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 300 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 301 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 302 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 303 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 304 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 305 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 306 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 307 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 308 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 309 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 310 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 311 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 312 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 313 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 314 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 315 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 316 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 317 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 318 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 319 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 320 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 321 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 322 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 323 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 324 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 325 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 326 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 327 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 328 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 329 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 330 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 331 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 332 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 333 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 334 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 335 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 336 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 337 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 338 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 339 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 340 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 341 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 342 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 343 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 344 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 345 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 346 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 347 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 348 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 349 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 350 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 351 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 352 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 353 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 354 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 355 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 356 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 357 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 358 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 359 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 360 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 361 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 362 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 363 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 364 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 365 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 366 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 367 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 368 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 369 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 370 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 371 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 372 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 373 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 374 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 375 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 376 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 377 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 378 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 379 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 380 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 381 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 382 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 383 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 384 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 385 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 386 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 387 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 388 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 389 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 390 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 391 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 392 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 393 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 394 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 395 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 396 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 397 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 398 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 399 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 400 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 401 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 402 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 403 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 404 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 405 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 406 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 407 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 408 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 409 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 410 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 411 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 412 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 413 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 414 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 415 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 416 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 417 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 418 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 419 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 420 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 421 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 422 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 423 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 424 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 425 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 426 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 427 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 428 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 429 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 430 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 431 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 432 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 433 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 434 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 435 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 436 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 437 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 438 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 439 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 440 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 441 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 442 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 443 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 444 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 445 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 446 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 447 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 448 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 449 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 450 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 451 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 452 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 453 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 454 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 455 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 456 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 457 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 458 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 459 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 460 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 461 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 462 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 463 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 464 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 465 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 466 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 467 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 468 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 469 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 470 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 471 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 472 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 473 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 474 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 475 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 476 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 477 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 478 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 479 + {amdgpu_gfx90a_op_V_DIV_SCALE_F32,"V_DIV_SCALE_F32"}, // 480 + {amdgpu_gfx90a_op_V_DIV_SCALE_F64,"V_DIV_SCALE_F64"}, // 481 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 482 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 483 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 484 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 485 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 486 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 487 + {amdgpu_gfx90a_op_V_MAD_U64_U32,"V_MAD_U64_U32"}, // 488 + {amdgpu_gfx90a_op_V_MAD_I64_I32,"V_MAD_I64_I32"}, // 489 + }; // end ENC_VOP3B_insn_table + const amdgpu_gfx90a_insn_entry ENC_VOP3P_insn_table[90] = + { + {amdgpu_gfx90a_op_V_PK_MAD_I16,"V_PK_MAD_I16"}, // 0 + {amdgpu_gfx90a_op_V_PK_MUL_LO_U16,"V_PK_MUL_LO_U16"}, // 1 + {amdgpu_gfx90a_op_V_PK_ADD_I16,"V_PK_ADD_I16"}, // 2 + {amdgpu_gfx90a_op_V_PK_SUB_I16,"V_PK_SUB_I16"}, // 3 + {amdgpu_gfx90a_op_V_PK_LSHLREV_B16,"V_PK_LSHLREV_B16"}, // 4 + {amdgpu_gfx90a_op_V_PK_LSHRREV_B16,"V_PK_LSHRREV_B16"}, // 5 + {amdgpu_gfx90a_op_V_PK_ASHRREV_I16,"V_PK_ASHRREV_I16"}, // 6 + {amdgpu_gfx90a_op_V_PK_MAX_I16,"V_PK_MAX_I16"}, // 7 + {amdgpu_gfx90a_op_V_PK_MIN_I16,"V_PK_MIN_I16"}, // 8 + {amdgpu_gfx90a_op_V_PK_MAD_U16,"V_PK_MAD_U16"}, // 9 + {amdgpu_gfx90a_op_V_PK_ADD_U16,"V_PK_ADD_U16"}, // 10 + {amdgpu_gfx90a_op_V_PK_SUB_U16,"V_PK_SUB_U16"}, // 11 + {amdgpu_gfx90a_op_V_PK_MAX_U16,"V_PK_MAX_U16"}, // 12 + {amdgpu_gfx90a_op_V_PK_MIN_U16,"V_PK_MIN_U16"}, // 13 + {amdgpu_gfx90a_op_V_PK_FMA_F16,"V_PK_FMA_F16"}, // 14 + {amdgpu_gfx90a_op_V_PK_ADD_F16,"V_PK_ADD_F16"}, // 15 + {amdgpu_gfx90a_op_V_PK_MUL_F16,"V_PK_MUL_F16"}, // 16 + {amdgpu_gfx90a_op_V_PK_MIN_F16,"V_PK_MIN_F16"}, // 17 + {amdgpu_gfx90a_op_V_PK_MAX_F16,"V_PK_MAX_F16"}, // 18 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 19 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 20 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 21 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 22 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 23 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 24 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 25 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 26 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 27 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 28 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 29 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 30 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 31 + {amdgpu_gfx90a_op_V_MAD_MIX_F32,"V_MAD_MIX_F32"}, // 32 + {amdgpu_gfx90a_op_V_MAD_MIXLO_F16,"V_MAD_MIXLO_F16"}, // 33 + {amdgpu_gfx90a_op_V_MAD_MIXHI_F16,"V_MAD_MIXHI_F16"}, // 34 + {amdgpu_gfx90a_op_V_DOT2_F32_F16,"V_DOT2_F32_F16"}, // 35 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 36 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 37 + {amdgpu_gfx90a_op_V_DOT2_I32_I16,"V_DOT2_I32_I16"}, // 38 + {amdgpu_gfx90a_op_V_DOT2_U32_U16,"V_DOT2_U32_U16"}, // 39 + {amdgpu_gfx90a_op_V_DOT4_I32_I8,"V_DOT4_I32_I8"}, // 40 + {amdgpu_gfx90a_op_V_DOT4_U32_U8,"V_DOT4_U32_U8"}, // 41 + {amdgpu_gfx90a_op_V_DOT8_I32_I4,"V_DOT8_I32_I4"}, // 42 + {amdgpu_gfx90a_op_V_DOT8_U32_U4,"V_DOT8_U32_U4"}, // 43 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 44 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 45 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 46 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 47 + {amdgpu_gfx90a_op_V_PK_FMA_F32,"V_PK_FMA_F32"}, // 48 + {amdgpu_gfx90a_op_V_PK_MUL_F32,"V_PK_MUL_F32"}, // 49 + {amdgpu_gfx90a_op_V_PK_ADD_F32,"V_PK_ADD_F32"}, // 50 + {amdgpu_gfx90a_op_V_PK_MOV_B32,"V_PK_MOV_B32"}, // 51 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 52 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 53 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 54 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 55 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 56 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 57 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 58 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 59 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 60 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 61 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 62 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 63 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 64 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 65 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 66 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 67 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 68 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 69 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 70 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 71 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 72 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 73 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 74 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 75 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 76 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 77 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 78 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 79 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 80 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 81 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 82 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 83 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 84 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 85 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 86 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 87 + {amdgpu_gfx90a_op_V_ACCVGPR_READ,"V_ACCVGPR_READ"}, // 88 + {amdgpu_gfx90a_op_V_ACCVGPR_WRITE,"V_ACCVGPR_WRITE"}, // 89 + }; // end ENC_VOP3P_insn_table + const amdgpu_gfx90a_insn_entry ENC_VOP3P_MFMA_insn_table[112] = + { + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 0 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 1 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 2 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 3 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 4 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 5 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 6 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 7 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 8 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 9 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 10 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 11 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 12 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 13 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 14 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 15 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 16 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 17 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 18 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 19 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 20 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 21 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 22 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 23 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 24 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 25 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 26 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 27 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 28 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 29 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 30 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 31 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 32 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 33 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 34 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 35 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 36 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 37 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 38 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 39 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 40 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 41 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 42 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 43 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 44 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 45 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 46 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 47 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 48 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 49 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 50 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 51 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 52 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 53 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 54 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 55 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 56 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 57 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 58 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 59 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 60 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 61 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 62 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 63 + {amdgpu_gfx90a_op_V_MFMA_F32_32X32X1F32,"V_MFMA_F32_32X32X1F32"}, // 64 + {amdgpu_gfx90a_op_V_MFMA_F32_16X16X1F32,"V_MFMA_F32_16X16X1F32"}, // 65 + {amdgpu_gfx90a_op_V_MFMA_F32_4X4X1F32,"V_MFMA_F32_4X4X1F32"}, // 66 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 67 + {amdgpu_gfx90a_op_V_MFMA_F32_32X32X2F32,"V_MFMA_F32_32X32X2F32"}, // 68 + {amdgpu_gfx90a_op_V_MFMA_F32_16X16X4F32,"V_MFMA_F32_16X16X4F32"}, // 69 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 70 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 71 + {amdgpu_gfx90a_op_V_MFMA_F32_32X32X4F16,"V_MFMA_F32_32X32X4F16"}, // 72 + {amdgpu_gfx90a_op_V_MFMA_F32_16X16X4F16,"V_MFMA_F32_16X16X4F16"}, // 73 + {amdgpu_gfx90a_op_V_MFMA_F32_4X4X4F16,"V_MFMA_F32_4X4X4F16"}, // 74 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 75 + {amdgpu_gfx90a_op_V_MFMA_F32_32X32X8F16,"V_MFMA_F32_32X32X8F16"}, // 76 + {amdgpu_gfx90a_op_V_MFMA_F32_16X16X16F16,"V_MFMA_F32_16X16X16F16"}, // 77 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 78 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 79 + {amdgpu_gfx90a_op_V_MFMA_I32_32X32X4I8,"V_MFMA_I32_32X32X4I8"}, // 80 + {amdgpu_gfx90a_op_V_MFMA_I32_16X16X4I8,"V_MFMA_I32_16X16X4I8"}, // 81 + {amdgpu_gfx90a_op_V_MFMA_I32_4X4X4I8,"V_MFMA_I32_4X4X4I8"}, // 82 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 83 + {amdgpu_gfx90a_op_V_MFMA_I32_32X32X8I8,"V_MFMA_I32_32X32X8I8"}, // 84 + {amdgpu_gfx90a_op_V_MFMA_I32_16X16X16I8,"V_MFMA_I32_16X16X16I8"}, // 85 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 86 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 87 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 88 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 89 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 90 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 91 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 92 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 93 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 94 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 95 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 96 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 97 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 98 + {amdgpu_gfx90a_op_V_MFMA_F32_32X32X4BF16_1K,"V_MFMA_F32_32X32X4BF16_1K"}, // 99 + {amdgpu_gfx90a_op_V_MFMA_F32_16X16X4BF16_1K,"V_MFMA_F32_16X16X4BF16_1K"}, // 100 + {amdgpu_gfx90a_op_V_MFMA_F32_4X4X4BF16_1K,"V_MFMA_F32_4X4X4BF16_1K"}, // 101 + {amdgpu_gfx90a_op_V_MFMA_F32_32X32X8BF16_1K,"V_MFMA_F32_32X32X8BF16_1K"}, // 102 + {amdgpu_gfx90a_op_V_MFMA_F32_16X16X16BF16_1K,"V_MFMA_F32_16X16X16BF16_1K"}, // 103 + {amdgpu_gfx90a_op_V_MFMA_F32_32X32X2BF16,"V_MFMA_F32_32X32X2BF16"}, // 104 + {amdgpu_gfx90a_op_V_MFMA_F32_16X16X2BF16,"V_MFMA_F32_16X16X2BF16"}, // 105 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 106 + {amdgpu_gfx90a_op_V_MFMA_F32_4X4X2BF16,"V_MFMA_F32_4X4X2BF16"}, // 107 + {amdgpu_gfx90a_op_V_MFMA_F32_32X32X4BF16,"V_MFMA_F32_32X32X4BF16"}, // 108 + {amdgpu_gfx90a_op_V_MFMA_F32_16X16X8BF16,"V_MFMA_F32_16X16X8BF16"}, // 109 + {amdgpu_gfx90a_op_V_MFMA_F64_16X16X4F64,"V_MFMA_F64_16X16X4F64"}, // 110 + {amdgpu_gfx90a_op_V_MFMA_F64_4X4X4F64,"V_MFMA_F64_4X4X4F64"}, // 111 + }; // end ENC_VOP3P_MFMA_insn_table + const amdgpu_gfx90a_insn_entry ENC_VOPC_insn_table[256] = + { + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 0 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 1 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 2 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 3 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 4 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 5 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 6 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 7 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 8 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 9 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 10 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 11 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 12 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 13 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 14 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 15 + {amdgpu_gfx90a_op_V_CMP_CLASS_F32,"V_CMP_CLASS_F32"}, // 16 + {amdgpu_gfx90a_op_V_CMPX_CLASS_F32,"V_CMPX_CLASS_F32"}, // 17 + {amdgpu_gfx90a_op_V_CMP_CLASS_F64,"V_CMP_CLASS_F64"}, // 18 + {amdgpu_gfx90a_op_V_CMPX_CLASS_F64,"V_CMPX_CLASS_F64"}, // 19 + {amdgpu_gfx90a_op_V_CMP_CLASS_F16,"V_CMP_CLASS_F16"}, // 20 + {amdgpu_gfx90a_op_V_CMPX_CLASS_F16,"V_CMPX_CLASS_F16"}, // 21 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 22 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 23 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 24 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 25 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 26 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 27 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 28 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 29 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 30 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 31 + {amdgpu_gfx90a_op_V_CMP_F_F16,"V_CMP_F_F16"}, // 32 + {amdgpu_gfx90a_op_V_CMP_LT_F16,"V_CMP_LT_F16"}, // 33 + {amdgpu_gfx90a_op_V_CMP_EQ_F16,"V_CMP_EQ_F16"}, // 34 + {amdgpu_gfx90a_op_V_CMP_LE_F16,"V_CMP_LE_F16"}, // 35 + {amdgpu_gfx90a_op_V_CMP_GT_F16,"V_CMP_GT_F16"}, // 36 + {amdgpu_gfx90a_op_V_CMP_LG_F16,"V_CMP_LG_F16"}, // 37 + {amdgpu_gfx90a_op_V_CMP_GE_F16,"V_CMP_GE_F16"}, // 38 + {amdgpu_gfx90a_op_V_CMP_O_F16,"V_CMP_O_F16"}, // 39 + {amdgpu_gfx90a_op_V_CMP_U_F16,"V_CMP_U_F16"}, // 40 + {amdgpu_gfx90a_op_V_CMP_NGE_F16,"V_CMP_NGE_F16"}, // 41 + {amdgpu_gfx90a_op_V_CMP_NLG_F16,"V_CMP_NLG_F16"}, // 42 + {amdgpu_gfx90a_op_V_CMP_NGT_F16,"V_CMP_NGT_F16"}, // 43 + {amdgpu_gfx90a_op_V_CMP_NLE_F16,"V_CMP_NLE_F16"}, // 44 + {amdgpu_gfx90a_op_V_CMP_NEQ_F16,"V_CMP_NEQ_F16"}, // 45 + {amdgpu_gfx90a_op_V_CMP_NLT_F16,"V_CMP_NLT_F16"}, // 46 + {amdgpu_gfx90a_op_V_CMP_TRU_F16,"V_CMP_TRU_F16"}, // 47 + {amdgpu_gfx90a_op_V_CMPX_F_F16,"V_CMPX_F_F16"}, // 48 + {amdgpu_gfx90a_op_V_CMPX_LT_F16,"V_CMPX_LT_F16"}, // 49 + {amdgpu_gfx90a_op_V_CMPX_EQ_F16,"V_CMPX_EQ_F16"}, // 50 + {amdgpu_gfx90a_op_V_CMPX_LE_F16,"V_CMPX_LE_F16"}, // 51 + {amdgpu_gfx90a_op_V_CMPX_GT_F16,"V_CMPX_GT_F16"}, // 52 + {amdgpu_gfx90a_op_V_CMPX_LG_F16,"V_CMPX_LG_F16"}, // 53 + {amdgpu_gfx90a_op_V_CMPX_GE_F16,"V_CMPX_GE_F16"}, // 54 + {amdgpu_gfx90a_op_V_CMPX_O_F16,"V_CMPX_O_F16"}, // 55 + {amdgpu_gfx90a_op_V_CMPX_U_F16,"V_CMPX_U_F16"}, // 56 + {amdgpu_gfx90a_op_V_CMPX_NGE_F16,"V_CMPX_NGE_F16"}, // 57 + {amdgpu_gfx90a_op_V_CMPX_NLG_F16,"V_CMPX_NLG_F16"}, // 58 + {amdgpu_gfx90a_op_V_CMPX_NGT_F16,"V_CMPX_NGT_F16"}, // 59 + {amdgpu_gfx90a_op_V_CMPX_NLE_F16,"V_CMPX_NLE_F16"}, // 60 + {amdgpu_gfx90a_op_V_CMPX_NEQ_F16,"V_CMPX_NEQ_F16"}, // 61 + {amdgpu_gfx90a_op_V_CMPX_NLT_F16,"V_CMPX_NLT_F16"}, // 62 + {amdgpu_gfx90a_op_V_CMPX_TRU_F16,"V_CMPX_TRU_F16"}, // 63 + {amdgpu_gfx90a_op_V_CMP_F_F32,"V_CMP_F_F32"}, // 64 + {amdgpu_gfx90a_op_V_CMP_LT_F32,"V_CMP_LT_F32"}, // 65 + {amdgpu_gfx90a_op_V_CMP_EQ_F32,"V_CMP_EQ_F32"}, // 66 + {amdgpu_gfx90a_op_V_CMP_LE_F32,"V_CMP_LE_F32"}, // 67 + {amdgpu_gfx90a_op_V_CMP_GT_F32,"V_CMP_GT_F32"}, // 68 + {amdgpu_gfx90a_op_V_CMP_LG_F32,"V_CMP_LG_F32"}, // 69 + {amdgpu_gfx90a_op_V_CMP_GE_F32,"V_CMP_GE_F32"}, // 70 + {amdgpu_gfx90a_op_V_CMP_O_F32,"V_CMP_O_F32"}, // 71 + {amdgpu_gfx90a_op_V_CMP_U_F32,"V_CMP_U_F32"}, // 72 + {amdgpu_gfx90a_op_V_CMP_NGE_F32,"V_CMP_NGE_F32"}, // 73 + {amdgpu_gfx90a_op_V_CMP_NLG_F32,"V_CMP_NLG_F32"}, // 74 + {amdgpu_gfx90a_op_V_CMP_NGT_F32,"V_CMP_NGT_F32"}, // 75 + {amdgpu_gfx90a_op_V_CMP_NLE_F32,"V_CMP_NLE_F32"}, // 76 + {amdgpu_gfx90a_op_V_CMP_NEQ_F32,"V_CMP_NEQ_F32"}, // 77 + {amdgpu_gfx90a_op_V_CMP_NLT_F32,"V_CMP_NLT_F32"}, // 78 + {amdgpu_gfx90a_op_V_CMP_TRU_F32,"V_CMP_TRU_F32"}, // 79 + {amdgpu_gfx90a_op_V_CMPX_F_F32,"V_CMPX_F_F32"}, // 80 + {amdgpu_gfx90a_op_V_CMPX_LT_F32,"V_CMPX_LT_F32"}, // 81 + {amdgpu_gfx90a_op_V_CMPX_EQ_F32,"V_CMPX_EQ_F32"}, // 82 + {amdgpu_gfx90a_op_V_CMPX_LE_F32,"V_CMPX_LE_F32"}, // 83 + {amdgpu_gfx90a_op_V_CMPX_GT_F32,"V_CMPX_GT_F32"}, // 84 + {amdgpu_gfx90a_op_V_CMPX_LG_F32,"V_CMPX_LG_F32"}, // 85 + {amdgpu_gfx90a_op_V_CMPX_GE_F32,"V_CMPX_GE_F32"}, // 86 + {amdgpu_gfx90a_op_V_CMPX_O_F32,"V_CMPX_O_F32"}, // 87 + {amdgpu_gfx90a_op_V_CMPX_U_F32,"V_CMPX_U_F32"}, // 88 + {amdgpu_gfx90a_op_V_CMPX_NGE_F32,"V_CMPX_NGE_F32"}, // 89 + {amdgpu_gfx90a_op_V_CMPX_NLG_F32,"V_CMPX_NLG_F32"}, // 90 + {amdgpu_gfx90a_op_V_CMPX_NGT_F32,"V_CMPX_NGT_F32"}, // 91 + {amdgpu_gfx90a_op_V_CMPX_NLE_F32,"V_CMPX_NLE_F32"}, // 92 + {amdgpu_gfx90a_op_V_CMPX_NEQ_F32,"V_CMPX_NEQ_F32"}, // 93 + {amdgpu_gfx90a_op_V_CMPX_NLT_F32,"V_CMPX_NLT_F32"}, // 94 + {amdgpu_gfx90a_op_V_CMPX_TRU_F32,"V_CMPX_TRU_F32"}, // 95 + {amdgpu_gfx90a_op_V_CMP_F_F64,"V_CMP_F_F64"}, // 96 + {amdgpu_gfx90a_op_V_CMP_LT_F64,"V_CMP_LT_F64"}, // 97 + {amdgpu_gfx90a_op_V_CMP_EQ_F64,"V_CMP_EQ_F64"}, // 98 + {amdgpu_gfx90a_op_V_CMP_LE_F64,"V_CMP_LE_F64"}, // 99 + {amdgpu_gfx90a_op_V_CMP_GT_F64,"V_CMP_GT_F64"}, // 100 + {amdgpu_gfx90a_op_V_CMP_LG_F64,"V_CMP_LG_F64"}, // 101 + {amdgpu_gfx90a_op_V_CMP_GE_F64,"V_CMP_GE_F64"}, // 102 + {amdgpu_gfx90a_op_V_CMP_O_F64,"V_CMP_O_F64"}, // 103 + {amdgpu_gfx90a_op_V_CMP_U_F64,"V_CMP_U_F64"}, // 104 + {amdgpu_gfx90a_op_V_CMP_NGE_F64,"V_CMP_NGE_F64"}, // 105 + {amdgpu_gfx90a_op_V_CMP_NLG_F64,"V_CMP_NLG_F64"}, // 106 + {amdgpu_gfx90a_op_V_CMP_NGT_F64,"V_CMP_NGT_F64"}, // 107 + {amdgpu_gfx90a_op_V_CMP_NLE_F64,"V_CMP_NLE_F64"}, // 108 + {amdgpu_gfx90a_op_V_CMP_NEQ_F64,"V_CMP_NEQ_F64"}, // 109 + {amdgpu_gfx90a_op_V_CMP_NLT_F64,"V_CMP_NLT_F64"}, // 110 + {amdgpu_gfx90a_op_V_CMP_TRU_F64,"V_CMP_TRU_F64"}, // 111 + {amdgpu_gfx90a_op_V_CMPX_F_F64,"V_CMPX_F_F64"}, // 112 + {amdgpu_gfx90a_op_V_CMPX_LT_F64,"V_CMPX_LT_F64"}, // 113 + {amdgpu_gfx90a_op_V_CMPX_EQ_F64,"V_CMPX_EQ_F64"}, // 114 + {amdgpu_gfx90a_op_V_CMPX_LE_F64,"V_CMPX_LE_F64"}, // 115 + {amdgpu_gfx90a_op_V_CMPX_GT_F64,"V_CMPX_GT_F64"}, // 116 + {amdgpu_gfx90a_op_V_CMPX_LG_F64,"V_CMPX_LG_F64"}, // 117 + {amdgpu_gfx90a_op_V_CMPX_GE_F64,"V_CMPX_GE_F64"}, // 118 + {amdgpu_gfx90a_op_V_CMPX_O_F64,"V_CMPX_O_F64"}, // 119 + {amdgpu_gfx90a_op_V_CMPX_U_F64,"V_CMPX_U_F64"}, // 120 + {amdgpu_gfx90a_op_V_CMPX_NGE_F64,"V_CMPX_NGE_F64"}, // 121 + {amdgpu_gfx90a_op_V_CMPX_NLG_F64,"V_CMPX_NLG_F64"}, // 122 + {amdgpu_gfx90a_op_V_CMPX_NGT_F64,"V_CMPX_NGT_F64"}, // 123 + {amdgpu_gfx90a_op_V_CMPX_NLE_F64,"V_CMPX_NLE_F64"}, // 124 + {amdgpu_gfx90a_op_V_CMPX_NEQ_F64,"V_CMPX_NEQ_F64"}, // 125 + {amdgpu_gfx90a_op_V_CMPX_NLT_F64,"V_CMPX_NLT_F64"}, // 126 + {amdgpu_gfx90a_op_V_CMPX_TRU_F64,"V_CMPX_TRU_F64"}, // 127 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 128 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 129 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 130 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 131 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 132 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 133 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 134 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 135 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 136 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 137 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 138 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 139 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 140 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 141 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 142 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 143 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 144 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 145 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 146 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 147 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 148 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 149 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 150 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 151 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 152 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 153 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 154 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 155 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 156 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 157 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 158 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 159 + {amdgpu_gfx90a_op_V_CMP_F_I16,"V_CMP_F_I16"}, // 160 + {amdgpu_gfx90a_op_V_CMP_LT_I16,"V_CMP_LT_I16"}, // 161 + {amdgpu_gfx90a_op_V_CMP_EQ_I16,"V_CMP_EQ_I16"}, // 162 + {amdgpu_gfx90a_op_V_CMP_LE_I16,"V_CMP_LE_I16"}, // 163 + {amdgpu_gfx90a_op_V_CMP_GT_I16,"V_CMP_GT_I16"}, // 164 + {amdgpu_gfx90a_op_V_CMP_NE_I16,"V_CMP_NE_I16"}, // 165 + {amdgpu_gfx90a_op_V_CMP_GE_I16,"V_CMP_GE_I16"}, // 166 + {amdgpu_gfx90a_op_V_CMP_T_I16,"V_CMP_T_I16"}, // 167 + {amdgpu_gfx90a_op_V_CMP_F_U16,"V_CMP_F_U16"}, // 168 + {amdgpu_gfx90a_op_V_CMP_LT_U16,"V_CMP_LT_U16"}, // 169 + {amdgpu_gfx90a_op_V_CMP_EQ_U16,"V_CMP_EQ_U16"}, // 170 + {amdgpu_gfx90a_op_V_CMP_LE_U16,"V_CMP_LE_U16"}, // 171 + {amdgpu_gfx90a_op_V_CMP_GT_U16,"V_CMP_GT_U16"}, // 172 + {amdgpu_gfx90a_op_V_CMP_NE_U16,"V_CMP_NE_U16"}, // 173 + {amdgpu_gfx90a_op_V_CMP_GE_U16,"V_CMP_GE_U16"}, // 174 + {amdgpu_gfx90a_op_V_CMP_T_U16,"V_CMP_T_U16"}, // 175 + {amdgpu_gfx90a_op_V_CMPX_F_I16,"V_CMPX_F_I16"}, // 176 + {amdgpu_gfx90a_op_V_CMPX_LT_I16,"V_CMPX_LT_I16"}, // 177 + {amdgpu_gfx90a_op_V_CMPX_EQ_I16,"V_CMPX_EQ_I16"}, // 178 + {amdgpu_gfx90a_op_V_CMPX_LE_I16,"V_CMPX_LE_I16"}, // 179 + {amdgpu_gfx90a_op_V_CMPX_GT_I16,"V_CMPX_GT_I16"}, // 180 + {amdgpu_gfx90a_op_V_CMPX_NE_I16,"V_CMPX_NE_I16"}, // 181 + {amdgpu_gfx90a_op_V_CMPX_GE_I16,"V_CMPX_GE_I16"}, // 182 + {amdgpu_gfx90a_op_V_CMPX_T_I16,"V_CMPX_T_I16"}, // 183 + {amdgpu_gfx90a_op_V_CMPX_F_U16,"V_CMPX_F_U16"}, // 184 + {amdgpu_gfx90a_op_V_CMPX_LT_U16,"V_CMPX_LT_U16"}, // 185 + {amdgpu_gfx90a_op_V_CMPX_EQ_U16,"V_CMPX_EQ_U16"}, // 186 + {amdgpu_gfx90a_op_V_CMPX_LE_U16,"V_CMPX_LE_U16"}, // 187 + {amdgpu_gfx90a_op_V_CMPX_GT_U16,"V_CMPX_GT_U16"}, // 188 + {amdgpu_gfx90a_op_V_CMPX_NE_U16,"V_CMPX_NE_U16"}, // 189 + {amdgpu_gfx90a_op_V_CMPX_GE_U16,"V_CMPX_GE_U16"}, // 190 + {amdgpu_gfx90a_op_V_CMPX_T_U16,"V_CMPX_T_U16"}, // 191 + {amdgpu_gfx90a_op_V_CMP_F_I32,"V_CMP_F_I32"}, // 192 + {amdgpu_gfx90a_op_V_CMP_LT_I32,"V_CMP_LT_I32"}, // 193 + {amdgpu_gfx90a_op_V_CMP_EQ_I32,"V_CMP_EQ_I32"}, // 194 + {amdgpu_gfx90a_op_V_CMP_LE_I32,"V_CMP_LE_I32"}, // 195 + {amdgpu_gfx90a_op_V_CMP_GT_I32,"V_CMP_GT_I32"}, // 196 + {amdgpu_gfx90a_op_V_CMP_NE_I32,"V_CMP_NE_I32"}, // 197 + {amdgpu_gfx90a_op_V_CMP_GE_I32,"V_CMP_GE_I32"}, // 198 + {amdgpu_gfx90a_op_V_CMP_T_I32,"V_CMP_T_I32"}, // 199 + {amdgpu_gfx90a_op_V_CMP_F_U32,"V_CMP_F_U32"}, // 200 + {amdgpu_gfx90a_op_V_CMP_LT_U32,"V_CMP_LT_U32"}, // 201 + {amdgpu_gfx90a_op_V_CMP_EQ_U32,"V_CMP_EQ_U32"}, // 202 + {amdgpu_gfx90a_op_V_CMP_LE_U32,"V_CMP_LE_U32"}, // 203 + {amdgpu_gfx90a_op_V_CMP_GT_U32,"V_CMP_GT_U32"}, // 204 + {amdgpu_gfx90a_op_V_CMP_NE_U32,"V_CMP_NE_U32"}, // 205 + {amdgpu_gfx90a_op_V_CMP_GE_U32,"V_CMP_GE_U32"}, // 206 + {amdgpu_gfx90a_op_V_CMP_T_U32,"V_CMP_T_U32"}, // 207 + {amdgpu_gfx90a_op_V_CMPX_F_I32,"V_CMPX_F_I32"}, // 208 + {amdgpu_gfx90a_op_V_CMPX_LT_I32,"V_CMPX_LT_I32"}, // 209 + {amdgpu_gfx90a_op_V_CMPX_EQ_I32,"V_CMPX_EQ_I32"}, // 210 + {amdgpu_gfx90a_op_V_CMPX_LE_I32,"V_CMPX_LE_I32"}, // 211 + {amdgpu_gfx90a_op_V_CMPX_GT_I32,"V_CMPX_GT_I32"}, // 212 + {amdgpu_gfx90a_op_V_CMPX_NE_I32,"V_CMPX_NE_I32"}, // 213 + {amdgpu_gfx90a_op_V_CMPX_GE_I32,"V_CMPX_GE_I32"}, // 214 + {amdgpu_gfx90a_op_V_CMPX_T_I32,"V_CMPX_T_I32"}, // 215 + {amdgpu_gfx90a_op_V_CMPX_F_U32,"V_CMPX_F_U32"}, // 216 + {amdgpu_gfx90a_op_V_CMPX_LT_U32,"V_CMPX_LT_U32"}, // 217 + {amdgpu_gfx90a_op_V_CMPX_EQ_U32,"V_CMPX_EQ_U32"}, // 218 + {amdgpu_gfx90a_op_V_CMPX_LE_U32,"V_CMPX_LE_U32"}, // 219 + {amdgpu_gfx90a_op_V_CMPX_GT_U32,"V_CMPX_GT_U32"}, // 220 + {amdgpu_gfx90a_op_V_CMPX_NE_U32,"V_CMPX_NE_U32"}, // 221 + {amdgpu_gfx90a_op_V_CMPX_GE_U32,"V_CMPX_GE_U32"}, // 222 + {amdgpu_gfx90a_op_V_CMPX_T_U32,"V_CMPX_T_U32"}, // 223 + {amdgpu_gfx90a_op_V_CMP_F_I64,"V_CMP_F_I64"}, // 224 + {amdgpu_gfx90a_op_V_CMP_LT_I64,"V_CMP_LT_I64"}, // 225 + {amdgpu_gfx90a_op_V_CMP_EQ_I64,"V_CMP_EQ_I64"}, // 226 + {amdgpu_gfx90a_op_V_CMP_LE_I64,"V_CMP_LE_I64"}, // 227 + {amdgpu_gfx90a_op_V_CMP_GT_I64,"V_CMP_GT_I64"}, // 228 + {amdgpu_gfx90a_op_V_CMP_NE_I64,"V_CMP_NE_I64"}, // 229 + {amdgpu_gfx90a_op_V_CMP_GE_I64,"V_CMP_GE_I64"}, // 230 + {amdgpu_gfx90a_op_V_CMP_T_I64,"V_CMP_T_I64"}, // 231 + {amdgpu_gfx90a_op_V_CMP_F_U64,"V_CMP_F_U64"}, // 232 + {amdgpu_gfx90a_op_V_CMP_LT_U64,"V_CMP_LT_U64"}, // 233 + {amdgpu_gfx90a_op_V_CMP_EQ_U64,"V_CMP_EQ_U64"}, // 234 + {amdgpu_gfx90a_op_V_CMP_LE_U64,"V_CMP_LE_U64"}, // 235 + {amdgpu_gfx90a_op_V_CMP_GT_U64,"V_CMP_GT_U64"}, // 236 + {amdgpu_gfx90a_op_V_CMP_NE_U64,"V_CMP_NE_U64"}, // 237 + {amdgpu_gfx90a_op_V_CMP_GE_U64,"V_CMP_GE_U64"}, // 238 + {amdgpu_gfx90a_op_V_CMP_T_U64,"V_CMP_T_U64"}, // 239 + {amdgpu_gfx90a_op_V_CMPX_F_I64,"V_CMPX_F_I64"}, // 240 + {amdgpu_gfx90a_op_V_CMPX_LT_I64,"V_CMPX_LT_I64"}, // 241 + {amdgpu_gfx90a_op_V_CMPX_EQ_I64,"V_CMPX_EQ_I64"}, // 242 + {amdgpu_gfx90a_op_V_CMPX_LE_I64,"V_CMPX_LE_I64"}, // 243 + {amdgpu_gfx90a_op_V_CMPX_GT_I64,"V_CMPX_GT_I64"}, // 244 + {amdgpu_gfx90a_op_V_CMPX_NE_I64,"V_CMPX_NE_I64"}, // 245 + {amdgpu_gfx90a_op_V_CMPX_GE_I64,"V_CMPX_GE_I64"}, // 246 + {amdgpu_gfx90a_op_V_CMPX_T_I64,"V_CMPX_T_I64"}, // 247 + {amdgpu_gfx90a_op_V_CMPX_F_U64,"V_CMPX_F_U64"}, // 248 + {amdgpu_gfx90a_op_V_CMPX_LT_U64,"V_CMPX_LT_U64"}, // 249 + {amdgpu_gfx90a_op_V_CMPX_EQ_U64,"V_CMPX_EQ_U64"}, // 250 + {amdgpu_gfx90a_op_V_CMPX_LE_U64,"V_CMPX_LE_U64"}, // 251 + {amdgpu_gfx90a_op_V_CMPX_GT_U64,"V_CMPX_GT_U64"}, // 252 + {amdgpu_gfx90a_op_V_CMPX_NE_U64,"V_CMPX_NE_U64"}, // 253 + {amdgpu_gfx90a_op_V_CMPX_GE_U64,"V_CMPX_GE_U64"}, // 254 + {amdgpu_gfx90a_op_V_CMPX_T_U64,"V_CMPX_T_U64"}, // 255 + }; // end ENC_VOPC_insn_table + const amdgpu_gfx90a_insn_entry ENC_VINTRP_insn_table[1] = + { + {amdgpu_gfx90a_op_S_NOP,"S_NOP"}, // 0 + }; // end ENC_VINTRP_insn_table + + + }; + + } +} +#endif //INSTRUCTION_DECODER_GFX90A_H diff --git a/instructionAPI/src/AMDGPU/gfx90a/amdgpu_gfx90a_decoder_impl.C b/instructionAPI/src/AMDGPU/gfx90a/amdgpu_gfx90a_decoder_impl.C new file mode 100644 index 0000000000..84cd5f4b90 --- /dev/null +++ b/instructionAPI/src/AMDGPU/gfx90a/amdgpu_gfx90a_decoder_impl.C @@ -0,0 +1,1346 @@ +#include "registers/AMDGPU/amdgpu_gfx90a_regs.h" +#include "InstructionDecoder-amdgpu-gfx90a.h" + +namespace Dyninst { +namespace InstructionAPI { + bool InstructionDecoder_amdgpu_gfx90a::IS_ENC_SOP1(uint64_t I) + { + switch ( I & 0xff80ff00 ) { + case 0xbe800000: case 0xbe800100: case 0xbe800200: case 0xbe800300: + case 0xbe800400: case 0xbe800500: case 0xbe800600: case 0xbe800700: + case 0xbe800800: case 0xbe800900: case 0xbe800a00: case 0xbe800b00: + case 0xbe800c00: case 0xbe800d00: case 0xbe800e00: case 0xbe800f00: + case 0xbe801000: case 0xbe801100: case 0xbe801200: case 0xbe801300: + case 0xbe801400: case 0xbe801500: case 0xbe801600: case 0xbe801700: + case 0xbe801800: case 0xbe801900: case 0xbe801a00: case 0xbe801b00: + case 0xbe801c00: case 0xbe801d00: case 0xbe801e00: case 0xbe801f00: + case 0xbe802000: case 0xbe802100: case 0xbe802200: case 0xbe802300: + case 0xbe802400: case 0xbe802500: case 0xbe802600: case 0xbe802700: + case 0xbe802800: case 0xbe802900: case 0xbe802a00: case 0xbe802b00: + case 0xbe802c00: case 0xbe802d00: case 0xbe802e00: case 0xbe803000: + case 0xbe803200: case 0xbe803300: case 0xbe803400: case 0xbe803500: + case 0xbe803600: case 0xbe803700: + return true; + + default: + return false; + } + } + + bool InstructionDecoder_amdgpu_gfx90a::IS_ENC_SOPC(uint64_t I) + { + switch ( I & 0xffff0000 ) { + case 0xbf000000: case 0xbf010000: case 0xbf020000: case 0xbf030000: + case 0xbf040000: case 0xbf050000: case 0xbf060000: case 0xbf070000: + case 0xbf080000: case 0xbf090000: case 0xbf0a0000: case 0xbf0b0000: + case 0xbf0c0000: case 0xbf0d0000: case 0xbf0e0000: case 0xbf0f0000: + case 0xbf100000: case 0xbf110000: case 0xbf120000: case 0xbf130000: + return true; + + default: + return false; + } + } + + bool InstructionDecoder_amdgpu_gfx90a::IS_ENC_SOPP(uint64_t I) + { + switch ( I & 0xffff0000 ) { + case 0xbf800000: case 0xbf810000: case 0xbf820000: case 0xbf830000: + case 0xbf840000: case 0xbf850000: case 0xbf860000: case 0xbf870000: + case 0xbf880000: case 0xbf890000: case 0xbf8a0000: case 0xbf8b0000: + case 0xbf8c0000: case 0xbf8d0000: case 0xbf8e0000: case 0xbf8f0000: + case 0xbf900000: case 0xbf910000: case 0xbf920000: case 0xbf930000: + case 0xbf940000: case 0xbf950000: case 0xbf960000: case 0xbf970000: + case 0xbf980000: case 0xbf990000: case 0xbf9a0000: case 0xbf9b0000: + case 0xbf9c0000: case 0xbf9d0000: case 0xbf9e0000: + return true; + + default: + return false; + } + } + + bool InstructionDecoder_amdgpu_gfx90a::IS_ENC_SOPK(uint64_t I) + { + switch ( I & 0xff800000 ) { + case 0xb0000000: case 0xb0800000: case 0xb1000000: case 0xb1800000: + case 0xb2000000: case 0xb2800000: case 0xb3000000: case 0xb3800000: + case 0xb4000000: case 0xb4800000: case 0xb5000000: case 0xb5800000: + case 0xb6000000: case 0xb6800000: case 0xb7000000: case 0xb7800000: + case 0xb8000000: case 0xb8800000: case 0xb9000000: case 0xba800000: + return true; + + default: + return false; + } + } + + bool InstructionDecoder_amdgpu_gfx90a::IS_ENC_SOP2(uint64_t I) + { + switch ( I & 0xff800000 ) { + case 0x80000000: case 0x80800000: case 0x81000000: case 0x81800000: + case 0x82000000: case 0x82800000: case 0x83000000: case 0x83800000: + case 0x84000000: case 0x84800000: case 0x85000000: case 0x85800000: + case 0x86000000: case 0x86800000: case 0x87000000: case 0x87800000: + case 0x88000000: case 0x88800000: case 0x89000000: case 0x89800000: + case 0x8a000000: case 0x8a800000: case 0x8b000000: case 0x8b800000: + case 0x8c000000: case 0x8c800000: case 0x8d000000: case 0x8d800000: + case 0x8e000000: case 0x8e800000: case 0x8f000000: case 0x8f800000: + case 0x90000000: case 0x90800000: case 0x91000000: case 0x91800000: + case 0x92000000: case 0x92800000: case 0x93000000: case 0x93800000: + case 0x94000000: case 0x94800000: case 0x95000000: case 0x95800000: + case 0x96000000: case 0x96800000: case 0x97000000: case 0x97800000: + case 0x98000000: case 0x98800000: case 0x99000000: case 0x99800000: + case 0x9a000000: + return true; + + default: + return false; + } + } + + bool InstructionDecoder_amdgpu_gfx90a::IS_ENC_SMEM(uint64_t I) + { + switch ( I & 0xfffc0000 ) { + case 0xc0000000: case 0xc0040000: case 0xc0080000: case 0xc00c0000: + case 0xc0100000: case 0xc0140000: case 0xc0180000: case 0xc01c0000: + case 0xc0200000: case 0xc0240000: case 0xc0280000: case 0xc02c0000: + case 0xc0300000: case 0xc0400000: case 0xc0440000: case 0xc0480000: + case 0xc0540000: case 0xc0580000: case 0xc05c0000: case 0xc0600000: + case 0xc0640000: case 0xc0680000: case 0xc0800000: case 0xc0840000: + case 0xc0880000: case 0xc08c0000: case 0xc0900000: case 0xc0940000: + case 0xc0980000: case 0xc09c0000: case 0xc0a00000: case 0xc0a40000: + case 0xc1000000: case 0xc1040000: case 0xc1080000: case 0xc10c0000: + case 0xc1100000: case 0xc1140000: case 0xc1180000: case 0xc11c0000: + case 0xc1200000: case 0xc1240000: case 0xc1280000: case 0xc12c0000: + case 0xc1300000: case 0xc1800000: case 0xc1840000: case 0xc1880000: + case 0xc18c0000: case 0xc1900000: case 0xc1940000: case 0xc1980000: + case 0xc19c0000: case 0xc1a00000: case 0xc1a40000: case 0xc1a80000: + case 0xc1ac0000: case 0xc1b00000: case 0xc2000000: case 0xc2040000: + case 0xc2080000: case 0xc20c0000: case 0xc2100000: case 0xc2140000: + case 0xc2180000: case 0xc21c0000: case 0xc2200000: case 0xc2240000: + case 0xc2280000: case 0xc22c0000: case 0xc2300000: case 0xc2800000: + case 0xc2840000: case 0xc2880000: case 0xc28c0000: case 0xc2900000: + case 0xc2940000: case 0xc2980000: case 0xc29c0000: case 0xc2a00000: + case 0xc2a40000: case 0xc2a80000: case 0xc2ac0000: case 0xc2b00000: + return true; + + default: + return false; + } + } + + bool InstructionDecoder_amdgpu_gfx90a::IS_ENC_VOP1(uint64_t I) + { + switch ( I & 0xfe01fe00 ) { + case 0x7e000000: case 0x7e000200: case 0x7e000400: case 0x7e000600: + case 0x7e000800: case 0x7e000a00: case 0x7e000c00: case 0x7e000e00: + case 0x7e001000: case 0x7e001400: case 0x7e001600: case 0x7e001800: + case 0x7e001a00: case 0x7e001c00: case 0x7e001e00: case 0x7e002000: + case 0x7e002200: case 0x7e002400: case 0x7e002600: case 0x7e002800: + case 0x7e002a00: case 0x7e002c00: case 0x7e002e00: case 0x7e003000: + case 0x7e003200: case 0x7e003400: case 0x7e003600: case 0x7e003800: + case 0x7e003a00: case 0x7e003c00: case 0x7e003e00: case 0x7e004000: + case 0x7e004200: case 0x7e004400: case 0x7e004600: case 0x7e004800: + case 0x7e004a00: case 0x7e004c00: case 0x7e004e00: case 0x7e005000: + case 0x7e005200: case 0x7e005400: case 0x7e005600: case 0x7e005800: + case 0x7e005a00: case 0x7e005c00: case 0x7e005e00: case 0x7e006000: + case 0x7e006200: case 0x7e006400: case 0x7e006600: case 0x7e006800: + case 0x7e006a00: case 0x7e006e00: case 0x7e007200: case 0x7e007400: + case 0x7e007600: case 0x7e007800: case 0x7e007a00: case 0x7e007c00: + case 0x7e007e00: case 0x7e008000: case 0x7e008200: case 0x7e008400: + case 0x7e008600: case 0x7e008800: case 0x7e008a00: case 0x7e008c00: + case 0x7e008e00: case 0x7e009000: case 0x7e009200: case 0x7e009400: + case 0x7e009600: case 0x7e009800: case 0x7e009a00: case 0x7e009c00: + case 0x7e009e00: case 0x7e00a200: case 0x7e00a400: + return true; + + default: + return false; + } + } + + bool InstructionDecoder_amdgpu_gfx90a::IS_ENC_VOPC(uint64_t I) + { + switch ( I & 0xfffe0000 ) { + case 0x7c200000: case 0x7c220000: case 0x7c240000: case 0x7c260000: + case 0x7c280000: case 0x7c2a0000: case 0x7c400000: case 0x7c420000: + case 0x7c440000: case 0x7c460000: case 0x7c480000: case 0x7c4a0000: + case 0x7c4c0000: case 0x7c4e0000: case 0x7c500000: case 0x7c520000: + case 0x7c540000: case 0x7c560000: case 0x7c580000: case 0x7c5a0000: + case 0x7c5c0000: case 0x7c5e0000: case 0x7c600000: case 0x7c620000: + case 0x7c640000: case 0x7c660000: case 0x7c680000: case 0x7c6a0000: + case 0x7c6c0000: case 0x7c6e0000: case 0x7c700000: case 0x7c720000: + case 0x7c740000: case 0x7c760000: case 0x7c780000: case 0x7c7a0000: + case 0x7c7c0000: case 0x7c7e0000: case 0x7c800000: case 0x7c820000: + case 0x7c840000: case 0x7c860000: case 0x7c880000: case 0x7c8a0000: + case 0x7c8c0000: case 0x7c8e0000: case 0x7c900000: case 0x7c920000: + case 0x7c940000: case 0x7c960000: case 0x7c980000: case 0x7c9a0000: + case 0x7c9c0000: case 0x7c9e0000: case 0x7ca00000: case 0x7ca20000: + case 0x7ca40000: case 0x7ca60000: case 0x7ca80000: case 0x7caa0000: + case 0x7cac0000: case 0x7cae0000: case 0x7cb00000: case 0x7cb20000: + case 0x7cb40000: case 0x7cb60000: case 0x7cb80000: case 0x7cba0000: + case 0x7cbc0000: case 0x7cbe0000: case 0x7cc00000: case 0x7cc20000: + case 0x7cc40000: case 0x7cc60000: case 0x7cc80000: case 0x7cca0000: + case 0x7ccc0000: case 0x7cce0000: case 0x7cd00000: case 0x7cd20000: + case 0x7cd40000: case 0x7cd60000: case 0x7cd80000: case 0x7cda0000: + case 0x7cdc0000: case 0x7cde0000: case 0x7ce00000: case 0x7ce20000: + case 0x7ce40000: case 0x7ce60000: case 0x7ce80000: case 0x7cea0000: + case 0x7cec0000: case 0x7cee0000: case 0x7cf00000: case 0x7cf20000: + case 0x7cf40000: case 0x7cf60000: case 0x7cf80000: case 0x7cfa0000: + case 0x7cfc0000: case 0x7cfe0000: case 0x7d400000: case 0x7d420000: + case 0x7d440000: case 0x7d460000: case 0x7d480000: case 0x7d4a0000: + case 0x7d4c0000: case 0x7d4e0000: case 0x7d500000: case 0x7d520000: + case 0x7d540000: case 0x7d560000: case 0x7d580000: case 0x7d5a0000: + case 0x7d5c0000: case 0x7d5e0000: case 0x7d600000: case 0x7d620000: + case 0x7d640000: case 0x7d660000: case 0x7d680000: case 0x7d6a0000: + case 0x7d6c0000: case 0x7d6e0000: case 0x7d700000: case 0x7d720000: + case 0x7d740000: case 0x7d760000: case 0x7d780000: case 0x7d7a0000: + case 0x7d7c0000: case 0x7d7e0000: case 0x7d800000: case 0x7d820000: + case 0x7d840000: case 0x7d860000: case 0x7d880000: case 0x7d8a0000: + case 0x7d8c0000: case 0x7d8e0000: case 0x7d900000: case 0x7d920000: + case 0x7d940000: case 0x7d960000: case 0x7d980000: case 0x7d9a0000: + case 0x7d9c0000: case 0x7d9e0000: case 0x7da00000: case 0x7da20000: + case 0x7da40000: case 0x7da60000: case 0x7da80000: case 0x7daa0000: + case 0x7dac0000: case 0x7dae0000: case 0x7db00000: case 0x7db20000: + case 0x7db40000: case 0x7db60000: case 0x7db80000: case 0x7dba0000: + case 0x7dbc0000: case 0x7dbe0000: case 0x7dc00000: case 0x7dc20000: + case 0x7dc40000: case 0x7dc60000: case 0x7dc80000: case 0x7dca0000: + case 0x7dcc0000: case 0x7dce0000: case 0x7dd00000: case 0x7dd20000: + case 0x7dd40000: case 0x7dd60000: case 0x7dd80000: case 0x7dda0000: + case 0x7ddc0000: case 0x7dde0000: case 0x7de00000: case 0x7de20000: + case 0x7de40000: case 0x7de60000: case 0x7de80000: case 0x7dea0000: + case 0x7dec0000: case 0x7dee0000: case 0x7df00000: case 0x7df20000: + case 0x7df40000: case 0x7df60000: case 0x7df80000: case 0x7dfa0000: + case 0x7dfc0000: case 0x7dfe0000: + return true; + + default: + return false; + } + } + + bool InstructionDecoder_amdgpu_gfx90a::IS_ENC_VOP2(uint64_t I) + { + switch ( I & 0xfe000000 ) { + case 0x0: case 0x2000000: case 0x4000000: case 0x6000000: + case 0x8000000: case 0xa000000: case 0xc000000: case 0xe000000: + case 0x10000000: case 0x12000000: case 0x14000000: case 0x16000000: + case 0x18000000: case 0x1a000000: case 0x1c000000: case 0x1e000000: + case 0x20000000: case 0x22000000: case 0x24000000: case 0x26000000: + case 0x28000000: case 0x2a000000: case 0x2c000000: case 0x32000000: + case 0x34000000: case 0x36000000: case 0x38000000: case 0x3a000000: + case 0x3c000000: case 0x3e000000: case 0x40000000: case 0x42000000: + case 0x44000000: case 0x46000000: case 0x4c000000: case 0x4e000000: + case 0x50000000: case 0x52000000: case 0x54000000: case 0x56000000: + case 0x58000000: case 0x5a000000: case 0x5c000000: case 0x5e000000: + case 0x60000000: case 0x62000000: case 0x64000000: case 0x66000000: + case 0x68000000: case 0x6a000000: case 0x6c000000: case 0x6e000000: + case 0x70000000: case 0x72000000: case 0x74000000: case 0x76000000: + case 0x78000000: case 0x7a000000: + return true; + + default: + return false; + } + } + + bool InstructionDecoder_amdgpu_gfx90a::IS_ENC_VINTRP(uint64_t I) + { + switch ( I & 0xfc000000 ) { + default: + return false; + } + } + + bool InstructionDecoder_amdgpu_gfx90a::IS_ENC_VOP3P(uint64_t I) + { + switch ( I & 0xffff0000 ) { + case 0xd3800000: case 0xd3810000: case 0xd3820000: case 0xd3830000: + case 0xd3840000: case 0xd3850000: case 0xd3860000: case 0xd3870000: + case 0xd3880000: case 0xd3890000: case 0xd38a0000: case 0xd38b0000: + case 0xd38c0000: case 0xd38d0000: case 0xd38e0000: case 0xd38f0000: + case 0xd3900000: case 0xd3910000: case 0xd3920000: case 0xd3a00000: + case 0xd3a10000: case 0xd3a20000: case 0xd3a30000: case 0xd3a60000: + case 0xd3a70000: case 0xd3a80000: case 0xd3a90000: case 0xd3aa0000: + case 0xd3ab0000: case 0xd3b00000: case 0xd3b10000: case 0xd3b20000: + case 0xd3b30000: case 0xd3d80000: case 0xd3d90000: + return true; + + default: + return false; + } + } + + bool InstructionDecoder_amdgpu_gfx90a::IS_ENC_VOP3(uint64_t I) + { + switch ( I & 0xffff0000 ) { + case 0xd1400000: case 0xd1410000: case 0xd1420000: case 0xd1430000: + case 0xd1440000: case 0xd1450000: case 0xd1460000: case 0xd1470000: + case 0xd1480000: case 0xd14a0000: case 0xd14b0000: case 0xd14c0000: + case 0xd14d0000: case 0xd14e0000: case 0xd14f0000: case 0xd1500000: + case 0xd1510000: case 0xd1520000: case 0xd1530000: case 0xd1540000: + case 0xd1550000: case 0xd1560000: case 0xd1570000: case 0xd1580000: + case 0xd1590000: case 0xd15a0000: case 0xd15b0000: case 0xd15c0000: + case 0xd15d0000: case 0xd15e0000: case 0xd15f0000: case 0xd1600000: + case 0xd1610000: case 0xd1620000: case 0xd1630000: case 0xd1640000: + case 0xd1650000: case 0xd1660000: case 0xd1670000: case 0xd1680000: + case 0xd1690000: case 0xd16a0000: case 0xd16b0000: case 0xd16c0000: + case 0xd16d0000: case 0xd16e0000: case 0xd16f0000: case 0xd1700000: + case 0xd1710000: case 0xd1720000: case 0xd1730000: case 0xd1740000: + case 0xd1750000: case 0xd1770000: case 0xd1790000: case 0xd17a0000: + case 0xd17b0000: case 0xd17c0000: case 0xd17d0000: case 0xd17e0000: + case 0xd17f0000: case 0xd1800000: case 0xd1810000: case 0xd1820000: + case 0xd1830000: case 0xd1840000: case 0xd1850000: case 0xd1860000: + case 0xd1870000: case 0xd1880000: case 0xd1890000: case 0xd18a0000: + case 0xd18b0000: case 0xd18c0000: case 0xd18d0000: case 0xd18e0000: + case 0xd18f0000: case 0xd1910000: case 0xd1920000: case 0xd1000000: + case 0xd1010000: case 0xd1020000: case 0xd1030000: case 0xd1040000: + case 0xd1050000: case 0xd1060000: case 0xd1070000: case 0xd1080000: + case 0xd1090000: case 0xd10a0000: case 0xd10b0000: case 0xd10c0000: + case 0xd10d0000: case 0xd10e0000: case 0xd10f0000: case 0xd1100000: + case 0xd1110000: case 0xd1120000: case 0xd1130000: case 0xd1140000: + case 0xd1150000: case 0xd1160000: case 0xd11f0000: case 0xd1200000: + case 0xd1210000: case 0xd1220000: case 0xd1230000: case 0xd1260000: + case 0xd1270000: case 0xd1280000: case 0xd1290000: case 0xd12a0000: + case 0xd12b0000: case 0xd12c0000: case 0xd12d0000: case 0xd12e0000: + case 0xd12f0000: case 0xd1300000: case 0xd1310000: case 0xd1320000: + case 0xd1330000: case 0xd1340000: case 0xd1350000: case 0xd1360000: + case 0xd1370000: case 0xd1380000: case 0xd1390000: case 0xd13a0000: + case 0xd13b0000: case 0xd13c0000: case 0xd13d0000: case 0xd1c00000: + case 0xd1c10000: case 0xd1c20000: case 0xd1c30000: case 0xd1c40000: + case 0xd1c50000: case 0xd1c60000: case 0xd1c70000: case 0xd1c80000: + case 0xd1c90000: case 0xd1ca0000: case 0xd1cb0000: case 0xd1cc0000: + case 0xd1cd0000: case 0xd1ce0000: case 0xd1cf0000: case 0xd1d00000: + case 0xd1d10000: case 0xd1d20000: case 0xd1d30000: case 0xd1d40000: + case 0xd1d50000: case 0xd1d60000: case 0xd1d70000: case 0xd1d80000: + case 0xd1d90000: case 0xd1da0000: case 0xd1db0000: case 0xd1dc0000: + case 0xd1dd0000: case 0xd1de0000: case 0xd1df0000: case 0xd1e20000: + case 0xd1e30000: case 0xd1e40000: case 0xd1e50000: case 0xd1e60000: + case 0xd1e70000: case 0xd1ea0000: case 0xd1eb0000: case 0xd1ec0000: + case 0xd1ed0000: case 0xd1ee0000: case 0xd1ef0000: case 0xd1f00000: + case 0xd1f10000: case 0xd1f20000: case 0xd1f30000: case 0xd1f40000: + case 0xd1f50000: case 0xd1f60000: case 0xd1f70000: case 0xd1f80000: + case 0xd1f90000: case 0xd1fa0000: case 0xd1fb0000: case 0xd1fc0000: + case 0xd1fd0000: case 0xd1fe0000: case 0xd1ff0000: case 0xd2000000: + case 0xd2010000: case 0xd2020000: case 0xd2030000: case 0xd2040000: + case 0xd2050000: case 0xd2060000: case 0xd2070000: case 0xd2800000: + case 0xd2810000: case 0xd2820000: case 0xd2830000: case 0xd2840000: + case 0xd2850000: case 0xd2860000: case 0xd2870000: case 0xd2880000: + case 0xd2890000: case 0xd28a0000: case 0xd28b0000: case 0xd28c0000: + case 0xd28d0000: case 0xd28f0000: case 0xd2900000: case 0xd2910000: + case 0xd2920000: case 0xd2930000: case 0xd2940000: case 0xd2950000: + case 0xd2960000: case 0xd2970000: case 0xd2980000: case 0xd2990000: + case 0xd29a0000: case 0xd29c0000: case 0xd29d0000: case 0xd29e0000: + case 0xd29f0000: case 0xd2a00000: case 0xd2a10000: case 0xd0100000: + case 0xd0110000: case 0xd0120000: case 0xd0130000: case 0xd0140000: + case 0xd0150000: case 0xd0200000: case 0xd0210000: case 0xd0220000: + case 0xd0230000: case 0xd0240000: case 0xd0250000: case 0xd0260000: + case 0xd0270000: case 0xd0280000: case 0xd0290000: case 0xd02a0000: + case 0xd02b0000: case 0xd02c0000: case 0xd02d0000: case 0xd02e0000: + case 0xd02f0000: case 0xd0300000: case 0xd0310000: case 0xd0320000: + case 0xd0330000: case 0xd0340000: case 0xd0350000: case 0xd0360000: + case 0xd0370000: case 0xd0380000: case 0xd0390000: case 0xd03a0000: + case 0xd03b0000: case 0xd03c0000: case 0xd03d0000: case 0xd03e0000: + case 0xd03f0000: case 0xd0400000: case 0xd0410000: case 0xd0420000: + case 0xd0430000: case 0xd0440000: case 0xd0450000: case 0xd0460000: + case 0xd0470000: case 0xd0480000: case 0xd0490000: case 0xd04a0000: + case 0xd04b0000: case 0xd04c0000: case 0xd04d0000: case 0xd04e0000: + case 0xd04f0000: case 0xd0500000: case 0xd0510000: case 0xd0520000: + case 0xd0530000: case 0xd0540000: case 0xd0550000: case 0xd0560000: + case 0xd0570000: case 0xd0580000: case 0xd0590000: case 0xd05a0000: + case 0xd05b0000: case 0xd05c0000: case 0xd05d0000: case 0xd05e0000: + case 0xd05f0000: case 0xd0600000: case 0xd0610000: case 0xd0620000: + case 0xd0630000: case 0xd0640000: case 0xd0650000: case 0xd0660000: + case 0xd0670000: case 0xd0680000: case 0xd0690000: case 0xd06a0000: + case 0xd06b0000: case 0xd06c0000: case 0xd06d0000: case 0xd06e0000: + case 0xd06f0000: case 0xd0700000: case 0xd0710000: case 0xd0720000: + case 0xd0730000: case 0xd0740000: case 0xd0750000: case 0xd0760000: + case 0xd0770000: case 0xd0780000: case 0xd0790000: case 0xd07a0000: + case 0xd07b0000: case 0xd07c0000: case 0xd07d0000: case 0xd07e0000: + case 0xd07f0000: case 0xd0a00000: case 0xd0a10000: case 0xd0a20000: + case 0xd0a30000: case 0xd0a40000: case 0xd0a50000: case 0xd0a60000: + case 0xd0a70000: case 0xd0a80000: case 0xd0a90000: case 0xd0aa0000: + case 0xd0ab0000: case 0xd0ac0000: case 0xd0ad0000: case 0xd0ae0000: + case 0xd0af0000: case 0xd0b00000: case 0xd0b10000: case 0xd0b20000: + case 0xd0b30000: case 0xd0b40000: case 0xd0b50000: case 0xd0b60000: + case 0xd0b70000: case 0xd0b80000: case 0xd0b90000: case 0xd0ba0000: + case 0xd0bb0000: case 0xd0bc0000: case 0xd0bd0000: case 0xd0be0000: + case 0xd0bf0000: case 0xd0c00000: case 0xd0c10000: case 0xd0c20000: + case 0xd0c30000: case 0xd0c40000: case 0xd0c50000: case 0xd0c60000: + case 0xd0c70000: case 0xd0c80000: case 0xd0c90000: case 0xd0ca0000: + case 0xd0cb0000: case 0xd0cc0000: case 0xd0cd0000: case 0xd0ce0000: + case 0xd0cf0000: case 0xd0d00000: case 0xd0d10000: case 0xd0d20000: + case 0xd0d30000: case 0xd0d40000: case 0xd0d50000: case 0xd0d60000: + case 0xd0d70000: case 0xd0d80000: case 0xd0d90000: case 0xd0da0000: + case 0xd0db0000: case 0xd0dc0000: case 0xd0dd0000: case 0xd0de0000: + case 0xd0df0000: case 0xd0e00000: case 0xd0e10000: case 0xd0e20000: + case 0xd0e30000: case 0xd0e40000: case 0xd0e50000: case 0xd0e60000: + case 0xd0e70000: case 0xd0e80000: case 0xd0e90000: case 0xd0ea0000: + case 0xd0eb0000: case 0xd0ec0000: case 0xd0ed0000: case 0xd0ee0000: + case 0xd0ef0000: case 0xd0f00000: case 0xd0f10000: case 0xd0f20000: + case 0xd0f30000: case 0xd0f40000: case 0xd0f50000: case 0xd0f60000: + case 0xd0f70000: case 0xd0f80000: case 0xd0f90000: case 0xd0fa0000: + case 0xd0fb0000: case 0xd0fc0000: case 0xd0fd0000: case 0xd0fe0000: + case 0xd0ff0000: + return true; + + default: + return false; + } + } + + bool InstructionDecoder_amdgpu_gfx90a::IS_ENC_DS(uint64_t I) + { + switch ( I & 0xfdfe0000 ) { + case 0xd8000000: case 0xd8020000: case 0xd8040000: case 0xd8060000: + case 0xd8080000: case 0xd80a0000: case 0xd80c0000: case 0xd80e0000: + case 0xd8100000: case 0xd8120000: case 0xd8140000: case 0xd8160000: + case 0xd8180000: case 0xd81a0000: case 0xd81c0000: case 0xd81e0000: + case 0xd8200000: case 0xd8220000: case 0xd8240000: case 0xd8260000: + case 0xd8280000: case 0xd82a0000: case 0xd83a0000: case 0xd83c0000: + case 0xd83e0000: case 0xd8400000: case 0xd8420000: case 0xd8440000: + case 0xd8460000: case 0xd8480000: case 0xd84a0000: case 0xd84c0000: + case 0xd84e0000: case 0xd8500000: case 0xd8520000: case 0xd8540000: + case 0xd8560000: case 0xd8580000: case 0xd85a0000: case 0xd85c0000: + case 0xd85e0000: case 0xd8600000: case 0xd8620000: case 0xd8640000: + case 0xd8660000: case 0xd8680000: case 0xd86a0000: case 0xd86c0000: + case 0xd86e0000: case 0xd8700000: case 0xd8720000: case 0xd8740000: + case 0xd8760000: case 0xd8780000: case 0xd87a0000: case 0xd87c0000: + case 0xd87e0000: case 0xd8800000: case 0xd8820000: case 0xd8840000: + case 0xd8860000: case 0xd8880000: case 0xd88a0000: case 0xd88c0000: + case 0xd88e0000: case 0xd8900000: case 0xd8920000: case 0xd8940000: + case 0xd8960000: case 0xd8980000: case 0xd89a0000: case 0xd89c0000: + case 0xd89e0000: case 0xd8a00000: case 0xd8a20000: case 0xd8a40000: + case 0xd8a60000: case 0xd8a80000: case 0xd8aa0000: case 0xd8ac0000: + case 0xd8ae0000: case 0xd8b00000: case 0xd8b20000: case 0xd8b40000: + case 0xd8b60000: case 0xd8b80000: case 0xd8c00000: case 0xd8c20000: + case 0xd8c40000: case 0xd8c60000: case 0xd8c80000: case 0xd8ca0000: + case 0xd8cc0000: case 0xd8ce0000: case 0xd8d00000: case 0xd8d20000: + case 0xd8d40000: case 0xd8d60000: case 0xd8d80000: case 0xd8da0000: + case 0xd8dc0000: case 0xd8de0000: case 0xd8e00000: case 0xd8e20000: + case 0xd8e40000: case 0xd8e60000: case 0xd8ec0000: case 0xd8ee0000: + case 0xd8f00000: case 0xd8f80000: case 0xd8fc0000: case 0xd9300000: + case 0xd9320000: case 0xd9340000: case 0xd9360000: case 0xd9380000: + case 0xd93a0000: case 0xd96c0000: case 0xd97a0000: case 0xd97c0000: + case 0xd9bc0000: case 0xd9be0000: case 0xd9fc0000: case 0xd9fe0000: + return true; + + default: + return false; + } + } + + bool InstructionDecoder_amdgpu_gfx90a::IS_ENC_MUBUF(uint64_t I) + { + switch ( I & 0xfdfc0000 ) { + case 0xe0000000: case 0xe0040000: case 0xe0080000: case 0xe00c0000: + case 0xe0100000: case 0xe0140000: case 0xe0180000: case 0xe01c0000: + case 0xe0200000: case 0xe0240000: case 0xe0280000: case 0xe02c0000: + case 0xe0300000: case 0xe0340000: case 0xe0380000: case 0xe03c0000: + case 0xe0400000: case 0xe0440000: case 0xe0480000: case 0xe04c0000: + case 0xe0500000: case 0xe0540000: case 0xe0580000: case 0xe05c0000: + case 0xe0600000: case 0xe0640000: case 0xe0680000: case 0xe06c0000: + case 0xe0700000: case 0xe0740000: case 0xe0780000: case 0xe07c0000: + case 0xe0800000: case 0xe0840000: case 0xe0880000: case 0xe08c0000: + case 0xe0900000: case 0xe0940000: case 0xe0980000: case 0xe09c0000: + case 0xe0a00000: case 0xe0a40000: case 0xe0f40000: case 0xe0f80000: + case 0xe0fc0000: case 0xe1000000: case 0xe1040000: case 0xe1080000: + case 0xe10c0000: case 0xe1100000: case 0xe1140000: case 0xe1180000: + case 0xe11c0000: case 0xe1200000: case 0xe1240000: case 0xe1280000: + case 0xe12c0000: case 0xe1300000: case 0xe1340000: case 0xe1380000: + case 0xe13c0000: case 0xe1400000: case 0xe1440000: case 0xe1800000: + case 0xe1840000: case 0xe1880000: case 0xe18c0000: case 0xe1900000: + case 0xe1940000: case 0xe1980000: case 0xe19c0000: case 0xe1a00000: + case 0xe1a40000: case 0xe1a80000: case 0xe1ac0000: case 0xe1b00000: + return true; + + default: + return false; + } + } + + bool InstructionDecoder_amdgpu_gfx90a::IS_ENC_MTBUF(uint64_t I) + { + switch ( I & 0xfc078000 ) { + case 0xe8000000: case 0xe8008000: case 0xe8010000: case 0xe8018000: + case 0xe8020000: case 0xe8028000: case 0xe8030000: case 0xe8038000: + case 0xe8040000: case 0xe8048000: case 0xe8050000: case 0xe8058000: + case 0xe8060000: case 0xe8068000: case 0xe8070000: case 0xe8078000: + return true; + + default: + return false; + } + } + + bool InstructionDecoder_amdgpu_gfx90a::IS_ENC_MIMG(uint64_t I) + { + switch ( I & 0xfdfc0000 ) { + case 0xf0000000: case 0xf0040000: case 0xf0080000: case 0xf00c0000: + case 0xf0100000: case 0xf0140000: case 0xf0200000: case 0xf0240000: + case 0xf0280000: case 0xf02c0000: case 0xf0380000: case 0xf0400000: + case 0xf0440000: case 0xf0480000: case 0xf04c0000: case 0xf0500000: + case 0xf0540000: case 0xf0580000: case 0xf05c0000: case 0xf0600000: + case 0xf0640000: case 0xf0680000: case 0xf06c0000: case 0xf0700000: + case 0xf0800000: + return true; + + default: + return false; + } + } + + bool InstructionDecoder_amdgpu_gfx90a::IS_ENC_FLAT(uint64_t I) + { + switch ( I & 0xfdfcc000 ) { + case 0xdc400000: case 0xdc440000: case 0xdc480000: case 0xdc4c0000: + case 0xdc500000: case 0xdc540000: case 0xdc580000: case 0xdc5c0000: + case 0xdc600000: case 0xdc640000: case 0xdc680000: case 0xdc6c0000: + case 0xdc700000: case 0xdc740000: case 0xdc780000: case 0xdc7c0000: + case 0xdc800000: case 0xdc840000: case 0xdc880000: case 0xdc8c0000: + case 0xdc900000: case 0xdc940000: case 0xdd000000: case 0xdd040000: + case 0xdd080000: case 0xdd0c0000: case 0xdd100000: case 0xdd140000: + case 0xdd180000: case 0xdd1c0000: case 0xdd200000: case 0xdd240000: + case 0xdd280000: case 0xdd2c0000: case 0xdd300000: case 0xdd3c0000: + case 0xdd400000: case 0xdd440000: case 0xdd800000: case 0xdd840000: + case 0xdd880000: case 0xdd8c0000: case 0xdd900000: case 0xdd940000: + case 0xdd980000: case 0xdd9c0000: case 0xdda00000: case 0xdda40000: + case 0xdda80000: case 0xddac0000: case 0xddb00000: + return true; + + default: + return false; + } + } + + bool InstructionDecoder_amdgpu_gfx90a::IS_ENC_FLAT_GLBL(uint64_t I) + { + switch ( I & 0xfdfcc000 ) { + case 0xdc408000: case 0xdc448000: case 0xdc488000: case 0xdc4c8000: + case 0xdc508000: case 0xdc548000: case 0xdc588000: case 0xdc5c8000: + case 0xdc608000: case 0xdc648000: case 0xdc688000: case 0xdc6c8000: + case 0xdc708000: case 0xdc748000: case 0xdc788000: case 0xdc7c8000: + case 0xdc808000: case 0xdc848000: case 0xdc888000: case 0xdc8c8000: + case 0xdc908000: case 0xdc948000: case 0xdd008000: case 0xdd048000: + case 0xdd088000: case 0xdd0c8000: case 0xdd108000: case 0xdd148000: + case 0xdd188000: case 0xdd1c8000: case 0xdd208000: case 0xdd248000: + case 0xdd288000: case 0xdd2c8000: case 0xdd308000: case 0xdd348000: + case 0xdd388000: case 0xdd3c8000: case 0xdd408000: case 0xdd448000: + case 0xdd808000: case 0xdd848000: case 0xdd888000: case 0xdd8c8000: + case 0xdd908000: case 0xdd948000: case 0xdd988000: case 0xdd9c8000: + case 0xdda08000: case 0xdda48000: case 0xdda88000: case 0xddac8000: + case 0xddb08000: + return true; + + default: + return false; + } + } + + bool InstructionDecoder_amdgpu_gfx90a::IS_ENC_FLAT_SCRATCH(uint64_t I) + { + switch ( I & 0xfdfcc000 ) { + case 0xdc404000: case 0xdc444000: case 0xdc484000: case 0xdc4c4000: + case 0xdc504000: case 0xdc544000: case 0xdc584000: case 0xdc5c4000: + case 0xdc604000: case 0xdc644000: case 0xdc684000: case 0xdc6c4000: + case 0xdc704000: case 0xdc744000: case 0xdc784000: case 0xdc7c4000: + case 0xdc804000: case 0xdc844000: case 0xdc884000: case 0xdc8c4000: + case 0xdc904000: case 0xdc944000: + return true; + + default: + return false; + } + } + + bool InstructionDecoder_amdgpu_gfx90a::IS_SOPK_INST_LITERAL_(uint64_t I) + { + switch ( I & 0xff800000 ) { + case 0xba000000: + return true; + + default: + return false; + } + } + + bool InstructionDecoder_amdgpu_gfx90a::IS_ENC_VOP2_LITERAL(uint64_t I) + { + switch ( I & 0xfe000000 ) { + case 0x2e000000: case 0x30000000: case 0x48000000: case 0x4a000000: + return true; + + default: + return false; + } + } + + bool InstructionDecoder_amdgpu_gfx90a::IS_ENC_VOP3B(uint64_t I) + { + switch ( I & 0xffff0000 ) { + case 0xd1190000: case 0xd11a0000: case 0xd11b0000: case 0xd11c0000: + case 0xd11d0000: case 0xd11e0000: case 0xd1e00000: case 0xd1e10000: + case 0xd1e80000: case 0xd1e90000: + return true; + + default: + return false; + } + } + + bool InstructionDecoder_amdgpu_gfx90a::IS_ENC_VOP3P_MFMA(uint64_t I) + { + switch ( I & 0xffff0000 ) { + case 0xd3c00000: case 0xd3c10000: case 0xd3c20000: case 0xd3c40000: + case 0xd3c50000: case 0xd3c80000: case 0xd3c90000: case 0xd3ca0000: + case 0xd3cc0000: case 0xd3cd0000: case 0xd3d00000: case 0xd3d10000: + case 0xd3d20000: case 0xd3d40000: case 0xd3d50000: case 0xd3e30000: + case 0xd3e40000: case 0xd3e50000: case 0xd3e60000: case 0xd3e70000: + case 0xd3e80000: case 0xd3e90000: case 0xd3eb0000: case 0xd3ec0000: + case 0xd3ed0000: case 0xd3ee0000: case 0xd3ef0000: + return true; + + default: + return false; + } + } + + void InstructionDecoder_amdgpu_gfx90a::decodeENC_SOP1() + { + insn_size = 4; + layout_ENC_SOP1 & layout = insn_layout.ENC_SOP1; + layout.ENCODING = longfield<23,31>(insn_long); + layout.OP = longfield<8,15>(insn_long); + layout.SDST = longfield<16,22>(insn_long); + layout.SSRC0 = longfield<0,7>(insn_long); + assert(isArrayIndexValid(ENC_SOP1_insn_table, layout.OP) && "Opcode over or underflow"); + const amdgpu_gfx90a_insn_entry &insn_entry = ENC_SOP1_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_SOP1Operands(); + this->insn_in_progress->updateSize(insn_size + immLen); + this->insn_in_progress->updateMnemonic(std::string(insn_entry.mnemonic) + extension); + } + + void InstructionDecoder_amdgpu_gfx90a::decodeENC_SOPC() + { + insn_size = 4; + layout_ENC_SOPC & layout = insn_layout.ENC_SOPC; + layout.ENCODING = longfield<23,31>(insn_long); + layout.OP = longfield<16,22>(insn_long); + layout.SSRC0 = longfield<0,7>(insn_long); + layout.SSRC1 = longfield<8,15>(insn_long); + assert(isArrayIndexValid(ENC_SOPC_insn_table, layout.OP) && "Opcode over or underflow"); + const amdgpu_gfx90a_insn_entry &insn_entry = ENC_SOPC_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_SOPCOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); + this->insn_in_progress->updateMnemonic(std::string(insn_entry.mnemonic) + extension); + } + + void InstructionDecoder_amdgpu_gfx90a::decodeENC_SOPP() + { + insn_size = 4; + layout_ENC_SOPP & layout = insn_layout.ENC_SOPP; + layout.ENCODING = longfield<23,31>(insn_long); + layout.OP = longfield<16,22>(insn_long); + layout.SIMM16 = longfield<0,15>(insn_long); + assert(isArrayIndexValid(ENC_SOPP_insn_table, layout.OP) && "Opcode over or underflow"); + const amdgpu_gfx90a_insn_entry &insn_entry = ENC_SOPP_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_SOPPOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); + this->insn_in_progress->updateMnemonic(std::string(insn_entry.mnemonic) + extension); + } + + void InstructionDecoder_amdgpu_gfx90a::decodeENC_SOPK() + { + insn_size = 4; + layout_ENC_SOPK & layout = insn_layout.ENC_SOPK; + layout.ENCODING = longfield<28,31>(insn_long); + layout.OP = longfield<23,27>(insn_long); + layout.SDST = longfield<16,22>(insn_long); + layout.SIMM16 = longfield<0,15>(insn_long); + assert(isArrayIndexValid(ENC_SOPK_insn_table, layout.OP) && "Opcode over or underflow"); + const amdgpu_gfx90a_insn_entry &insn_entry = ENC_SOPK_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_SOPKOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); + this->insn_in_progress->updateMnemonic(std::string(insn_entry.mnemonic) + extension); + } + + void InstructionDecoder_amdgpu_gfx90a::decodeENC_SOP2() + { + insn_size = 4; + layout_ENC_SOP2 & layout = insn_layout.ENC_SOP2; + layout.ENCODING = longfield<30,31>(insn_long); + layout.OP = longfield<23,29>(insn_long); + layout.SDST = longfield<16,22>(insn_long); + layout.SSRC0 = longfield<0,7>(insn_long); + layout.SSRC1 = longfield<8,15>(insn_long); + assert(isArrayIndexValid(ENC_SOP2_insn_table, layout.OP) && "Opcode over or underflow"); + const amdgpu_gfx90a_insn_entry &insn_entry = ENC_SOP2_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_SOP2Operands(); + this->insn_in_progress->updateSize(insn_size + immLen); + this->insn_in_progress->updateMnemonic(std::string(insn_entry.mnemonic) + extension); + } + + void InstructionDecoder_amdgpu_gfx90a::decodeENC_SMEM() + { + insn_size = 8; + layout_ENC_SMEM & layout = insn_layout.ENC_SMEM; + layout.ENCODING = longfield<26,31>(insn_long); + layout.GLC = longfield<16,16>(insn_long); + layout.IMM = longfield<17,17>(insn_long); + layout.NV = longfield<15,15>(insn_long); + layout.OFFSET = longfield<32,52>(insn_long); + layout.OP = longfield<18,25>(insn_long); + layout.SBASE = (longfield<0,5>(insn_long) << 1 ) | 0 ; + layout.SDATA = longfield<6,12>(insn_long); + layout.SOFFSET = longfield<57,63>(insn_long); + layout.SOFFSET_EN = longfield<14,14>(insn_long); + assert(isArrayIndexValid(ENC_SMEM_insn_table, layout.OP) && "Opcode over or underflow"); + const amdgpu_gfx90a_insn_entry &insn_entry = ENC_SMEM_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_SMEMOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); + this->insn_in_progress->updateMnemonic(std::string(insn_entry.mnemonic) + extension); + } + + void InstructionDecoder_amdgpu_gfx90a::decodeENC_VOP1() + { + insn_size = 4; + layout_ENC_VOP1 & layout = insn_layout.ENC_VOP1; + layout.ENCODING = longfield<25,31>(insn_long); + layout.OP = longfield<9,16>(insn_long); + layout.SRC0 = longfield<0,8>(insn_long); + layout.VDST = longfield<17,24>(insn_long); + assert(isArrayIndexValid(ENC_VOP1_insn_table, layout.OP) && "Opcode over or underflow"); + const amdgpu_gfx90a_insn_entry &insn_entry = ENC_VOP1_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_VOP1Operands(); + this->insn_in_progress->updateSize(insn_size + immLen); + this->insn_in_progress->updateMnemonic(std::string(insn_entry.mnemonic) + extension); + } + + void InstructionDecoder_amdgpu_gfx90a::decodeENC_VOPC() + { + insn_size = 4; + layout_ENC_VOPC & layout = insn_layout.ENC_VOPC; + layout.ENCODING = longfield<25,31>(insn_long); + layout.OP = longfield<17,24>(insn_long); + layout.SRC0 = longfield<0,8>(insn_long); + layout.VSRC1 = longfield<9,16>(insn_long); + assert(isArrayIndexValid(ENC_VOPC_insn_table, layout.OP) && "Opcode over or underflow"); + const amdgpu_gfx90a_insn_entry &insn_entry = ENC_VOPC_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_VOPCOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); + this->insn_in_progress->updateMnemonic(std::string(insn_entry.mnemonic) + extension); + } + + void InstructionDecoder_amdgpu_gfx90a::decodeENC_VOP2() + { + insn_size = 4; + layout_ENC_VOP2 & layout = insn_layout.ENC_VOP2; + layout.ENCODING = longfield<31,31>(insn_long); + layout.OP = longfield<25,30>(insn_long); + layout.SRC0 = longfield<0,8>(insn_long); + layout.VDST = longfield<17,24>(insn_long); + layout.VSRC1 = longfield<9,16>(insn_long); + assert(isArrayIndexValid(ENC_VOP2_insn_table, layout.OP) && "Opcode over or underflow"); + const amdgpu_gfx90a_insn_entry &insn_entry = ENC_VOP2_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_VOP2Operands(); + this->insn_in_progress->updateSize(insn_size + immLen); + this->insn_in_progress->updateMnemonic(std::string(insn_entry.mnemonic) + extension); + } + + void InstructionDecoder_amdgpu_gfx90a::decodeENC_VINTRP() + { + insn_size = 4; + layout_ENC_VINTRP & layout = insn_layout.ENC_VINTRP; + layout.ATTR = longfield<10,15>(insn_long); + layout.ATTRCHAN = longfield<8,9>(insn_long); + layout.ENCODING = longfield<26,31>(insn_long); + layout.OP = longfield<16,17>(insn_long); + layout.VDST = longfield<18,25>(insn_long); + layout.VSRC = longfield<0,7>(insn_long); + assert(isArrayIndexValid(ENC_VINTRP_insn_table, layout.OP) && "Opcode over or underflow"); + const amdgpu_gfx90a_insn_entry &insn_entry = ENC_VINTRP_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_VINTRPOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); + this->insn_in_progress->updateMnemonic(std::string(insn_entry.mnemonic) + extension); + } + + void InstructionDecoder_amdgpu_gfx90a::decodeENC_VOP3P() + { + insn_size = 8; + layout_ENC_VOP3P & layout = insn_layout.ENC_VOP3P; + layout.CLAMP = longfield<15,15>(insn_long); + layout.ENCODING = longfield<23,31>(insn_long); + layout.NEG = longfield<61,63>(insn_long); + layout.NEG_HI = longfield<8,10>(insn_long); + layout.OP = longfield<16,22>(insn_long); + layout.OP_SEL = longfield<11,13>(insn_long); + layout.OP_SEL_HI = longfield<59,60>(insn_long); + layout.OP_SEL_HI_2 = longfield<14,14>(insn_long); + layout.SRC0 = longfield<32,40>(insn_long); + layout.SRC1 = longfield<41,49>(insn_long); + layout.SRC2 = longfield<50,58>(insn_long); + layout.VDST = longfield<0,7>(insn_long); + assert(isArrayIndexValid(ENC_VOP3P_insn_table, layout.OP) && "Opcode over or underflow"); + const amdgpu_gfx90a_insn_entry &insn_entry = ENC_VOP3P_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_VOP3POperands(); + this->insn_in_progress->updateSize(insn_size + immLen); + this->insn_in_progress->updateMnemonic(std::string(insn_entry.mnemonic) + extension); + } + + void InstructionDecoder_amdgpu_gfx90a::decodeENC_VOP3() + { + insn_size = 8; + layout_ENC_VOP3 & layout = insn_layout.ENC_VOP3; + layout.ABS = longfield<8,10>(insn_long); + layout.CLAMP = longfield<15,15>(insn_long); + layout.ENCODING = longfield<26,31>(insn_long); + layout.NEG = longfield<61,63>(insn_long); + layout.OMOD = longfield<59,60>(insn_long); + layout.OP = longfield<16,25>(insn_long); + layout.OP_SEL = longfield<11,14>(insn_long); + layout.SRC0 = longfield<32,40>(insn_long); + layout.SRC1 = longfield<41,49>(insn_long); + layout.SRC2 = longfield<50,58>(insn_long); + layout.VDST = longfield<0,7>(insn_long); + assert(isArrayIndexValid(ENC_VOP3_insn_table, layout.OP) && "Opcode over or underflow"); + const amdgpu_gfx90a_insn_entry &insn_entry = ENC_VOP3_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_VOP3Operands(); + this->insn_in_progress->updateSize(insn_size + immLen); + this->insn_in_progress->updateMnemonic(std::string(insn_entry.mnemonic) + extension); + } + + void InstructionDecoder_amdgpu_gfx90a::decodeENC_DS() + { + insn_size = 8; + layout_ENC_DS & layout = insn_layout.ENC_DS; + layout.ACC = longfield<25,25>(insn_long); + layout.ADDR = longfield<32,39>(insn_long); + layout.DATA0 = longfield<40,47>(insn_long); + layout.DATA1 = longfield<48,55>(insn_long); + layout.ENCODING = longfield<26,31>(insn_long); + layout.GDS = longfield<16,16>(insn_long); + layout.OFFSET0 = longfield<0,7>(insn_long); + layout.OFFSET1 = longfield<8,15>(insn_long); + layout.OP = longfield<17,24>(insn_long); + layout.VDST = longfield<56,63>(insn_long); + assert(isArrayIndexValid(ENC_DS_insn_table, layout.OP) && "Opcode over or underflow"); + const amdgpu_gfx90a_insn_entry &insn_entry = ENC_DS_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_DSOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); + this->insn_in_progress->updateMnemonic(std::string(insn_entry.mnemonic) + extension); + } + + void InstructionDecoder_amdgpu_gfx90a::decodeENC_MUBUF() + { + insn_size = 8; + layout_ENC_MUBUF & layout = insn_layout.ENC_MUBUF; + layout.ACC = longfield<55,55>(insn_long); + layout.ENCODING = longfield<26,31>(insn_long); + layout.GLC = longfield<14,14>(insn_long); + layout.IDXEN = longfield<13,13>(insn_long); + layout.LDS = longfield<16,16>(insn_long); + layout.OFFEN = longfield<12,12>(insn_long); + layout.OFFSET = longfield<0,11>(insn_long); + layout.OP = longfield<18,24>(insn_long); + layout.SCC = longfield<15,15>(insn_long); + layout.SLC = longfield<17,17>(insn_long); + layout.SOFFSET = longfield<56,63>(insn_long); + layout.SRSRC = (longfield<48,52>(insn_long) << 2 ) | 0 ; + layout.VADDR = longfield<32,39>(insn_long); + layout.VDATA = longfield<40,47>(insn_long); + assert(isArrayIndexValid(ENC_MUBUF_insn_table, layout.OP) && "Opcode over or underflow"); + const amdgpu_gfx90a_insn_entry &insn_entry = ENC_MUBUF_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_MUBUFOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); + this->insn_in_progress->updateMnemonic(std::string(insn_entry.mnemonic) + extension); + } + + void InstructionDecoder_amdgpu_gfx90a::decodeENC_MTBUF() + { + insn_size = 8; + layout_ENC_MTBUF & layout = insn_layout.ENC_MTBUF; + layout.ACC = longfield<55,55>(insn_long); + layout.DFMT = longfield<19,22>(insn_long); + layout.ENCODING = longfield<26,31>(insn_long); + layout.GLC = longfield<14,14>(insn_long); + layout.IDXEN = longfield<13,13>(insn_long); + layout.NFMT = longfield<23,25>(insn_long); + layout.OFFEN = longfield<12,12>(insn_long); + layout.OFFSET = longfield<0,11>(insn_long); + layout.OP = longfield<15,18>(insn_long); + layout.SCC = longfield<53,53>(insn_long); + layout.SLC = longfield<54,54>(insn_long); + layout.SOFFSET = longfield<56,63>(insn_long); + layout.SRSRC = (longfield<48,52>(insn_long) << 2 ) | 0 ; + layout.VADDR = longfield<32,39>(insn_long); + layout.VDATA = longfield<40,47>(insn_long); + assert(isArrayIndexValid(ENC_MTBUF_insn_table, layout.OP) && "Opcode over or underflow"); + const amdgpu_gfx90a_insn_entry &insn_entry = ENC_MTBUF_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_MTBUFOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); + this->insn_in_progress->updateMnemonic(std::string(insn_entry.mnemonic) + extension); + } + + void InstructionDecoder_amdgpu_gfx90a::decodeENC_MIMG() + { + insn_size = 8; + layout_ENC_MIMG & layout = insn_layout.ENC_MIMG; + layout.A16 = longfield<15,15>(insn_long); + layout.ACC = longfield<16,16>(insn_long); + layout.D16 = longfield<63,63>(insn_long); + layout.DA = longfield<14,14>(insn_long); + layout.DMASK = longfield<8,11>(insn_long); + layout.ENCODING = longfield<26,31>(insn_long); + layout.GLC = longfield<13,13>(insn_long); + layout.LWE = longfield<17,17>(insn_long); + layout.OP = longfield<18,24>(insn_long); + layout.OPM = longfield<0,0>(insn_long); + layout.SCC = longfield<7,7>(insn_long); + layout.SLC = longfield<25,25>(insn_long); + layout.SRSRC = (longfield<48,52>(insn_long) << 2 ) | 0 ; + layout.SSAMP = (longfield<53,57>(insn_long) << 2 ) | 0 ; + layout.UNORM = longfield<12,12>(insn_long); + layout.VADDR = longfield<32,39>(insn_long); + layout.VDATA = longfield<40,47>(insn_long); + assert(isArrayIndexValid(ENC_MIMG_insn_table, layout.OP) && "Opcode over or underflow"); + const amdgpu_gfx90a_insn_entry &insn_entry = ENC_MIMG_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_MIMGOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); + this->insn_in_progress->updateMnemonic(std::string(insn_entry.mnemonic) + extension); + } + + void InstructionDecoder_amdgpu_gfx90a::decodeENC_FLAT() + { + insn_size = 8; + layout_ENC_FLAT & layout = insn_layout.ENC_FLAT; + layout.ACC = longfield<55,55>(insn_long); + layout.ADDR = longfield<32,39>(insn_long); + layout.DATA = longfield<40,47>(insn_long); + layout.ENCODING = longfield<26,31>(insn_long); + layout.GLC = longfield<16,16>(insn_long); + layout.LDS = longfield<13,13>(insn_long); + layout.OFFSET = longfield<0,11>(insn_long); + layout.OP = longfield<18,24>(insn_long); + layout.SADDR = longfield<48,54>(insn_long); + layout.SCC = longfield<25,25>(insn_long); + layout.SEG = longfield<14,15>(insn_long); + layout.SLC = longfield<17,17>(insn_long); + layout.VDST = longfield<56,63>(insn_long); + assert(isArrayIndexValid(ENC_FLAT_insn_table, layout.OP) && "Opcode over or underflow"); + const amdgpu_gfx90a_insn_entry &insn_entry = ENC_FLAT_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_FLATOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); + this->insn_in_progress->updateMnemonic(std::string(insn_entry.mnemonic) + extension); + } + + void InstructionDecoder_amdgpu_gfx90a::decodeENC_FLAT_GLBL() + { + insn_size = 8; + layout_ENC_FLAT_GLBL & layout = insn_layout.ENC_FLAT_GLBL; + layout.ACC = longfield<55,55>(insn_long); + layout.ADDR = longfield<32,39>(insn_long); + layout.DATA = longfield<40,47>(insn_long); + layout.ENCODING = longfield<26,31>(insn_long); + layout.GLC = longfield<16,16>(insn_long); + layout.LDS = longfield<13,13>(insn_long); + layout.OFFSET = longfield<0,12>(insn_long); + layout.OP = longfield<18,24>(insn_long); + layout.SADDR = longfield<48,54>(insn_long); + layout.SCC = longfield<25,25>(insn_long); + layout.SEG = longfield<14,15>(insn_long); + layout.SLC = longfield<17,17>(insn_long); + layout.VDST = longfield<56,63>(insn_long); + assert(isArrayIndexValid(ENC_FLAT_GLBL_insn_table, layout.OP) && "Opcode over or underflow"); + const amdgpu_gfx90a_insn_entry &insn_entry = ENC_FLAT_GLBL_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_FLAT_GLBLOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); + this->insn_in_progress->updateMnemonic(std::string(insn_entry.mnemonic) + extension); + } + + void InstructionDecoder_amdgpu_gfx90a::decodeENC_FLAT_SCRATCH() + { + insn_size = 8; + layout_ENC_FLAT_SCRATCH & layout = insn_layout.ENC_FLAT_SCRATCH; + layout.ACC = longfield<55,55>(insn_long); + layout.ADDR = longfield<32,39>(insn_long); + layout.DATA = longfield<40,47>(insn_long); + layout.ENCODING = longfield<26,31>(insn_long); + layout.GLC = longfield<16,16>(insn_long); + layout.LDS = longfield<13,13>(insn_long); + layout.OFFSET = longfield<0,12>(insn_long); + layout.OP = longfield<18,24>(insn_long); + layout.SADDR = longfield<48,54>(insn_long); + layout.SCC = longfield<25,25>(insn_long); + layout.SEG = longfield<14,15>(insn_long); + layout.SLC = longfield<17,17>(insn_long); + layout.VDST = longfield<56,63>(insn_long); + assert(isArrayIndexValid(ENC_FLAT_SCRATCH_insn_table, layout.OP) && "Opcode over or underflow"); + const amdgpu_gfx90a_insn_entry &insn_entry = ENC_FLAT_SCRATCH_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_FLAT_SCRATCHOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); + this->insn_in_progress->updateMnemonic(std::string(insn_entry.mnemonic) + extension); + } + + void InstructionDecoder_amdgpu_gfx90a::decodeSOPK_INST_LITERAL_() + { + insn_size = 8; + layout_SOPK_INST_LITERAL_ & layout = insn_layout.SOPK_INST_LITERAL_; + layout.ENCODING = longfield<28,31>(insn_long); + layout.OP = longfield<23,27>(insn_long); + layout.SDST = longfield<16,22>(insn_long); + layout.SIMM16 = longfield<0,15>(insn_long); + layout.SIMM32 = longfield<32,63>(insn_long); + assert(isArrayIndexValid(SOPK_INST_LITERAL__insn_table, layout.OP) && "Opcode over or underflow"); + const amdgpu_gfx90a_insn_entry &insn_entry = SOPK_INST_LITERAL__insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeSOPK_INST_LITERAL_Operands(); + this->insn_in_progress->updateSize(insn_size + immLen); + this->insn_in_progress->updateMnemonic(std::string(insn_entry.mnemonic) + extension); + } + + void InstructionDecoder_amdgpu_gfx90a::decodeENC_VOP2_LITERAL() + { + insn_size = 8; + layout_ENC_VOP2_LITERAL & layout = insn_layout.ENC_VOP2_LITERAL; + layout.ENCODING = longfield<31,31>(insn_long); + layout.OP = longfield<25,30>(insn_long); + layout.SIMM32 = longfield<32,63>(insn_long); + layout.SRC0 = longfield<0,8>(insn_long); + layout.VDST = longfield<17,24>(insn_long); + layout.VSRC1 = longfield<9,16>(insn_long); + assert(isArrayIndexValid(ENC_VOP2_LITERAL_insn_table, layout.OP) && "Opcode over or underflow"); + const amdgpu_gfx90a_insn_entry &insn_entry = ENC_VOP2_LITERAL_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_VOP2_LITERALOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); + this->insn_in_progress->updateMnemonic(std::string(insn_entry.mnemonic) + extension); + } + + void InstructionDecoder_amdgpu_gfx90a::decodeENC_VOP3B() + { + insn_size = 8; + layout_ENC_VOP3B & layout = insn_layout.ENC_VOP3B; + layout.CLAMP = longfield<15,15>(insn_long); + layout.ENCODING = longfield<26,31>(insn_long); + layout.NEG = longfield<61,63>(insn_long); + layout.OMOD = longfield<59,60>(insn_long); + layout.OP = longfield<16,25>(insn_long); + layout.SDST = longfield<8,14>(insn_long); + layout.SRC0 = longfield<32,40>(insn_long); + layout.SRC1 = longfield<41,49>(insn_long); + layout.SRC2 = longfield<50,58>(insn_long); + layout.VDST = longfield<0,7>(insn_long); + assert(isArrayIndexValid(ENC_VOP3B_insn_table, layout.OP) && "Opcode over or underflow"); + const amdgpu_gfx90a_insn_entry &insn_entry = ENC_VOP3B_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_VOP3BOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); + this->insn_in_progress->updateMnemonic(std::string(insn_entry.mnemonic) + extension); + } + + void InstructionDecoder_amdgpu_gfx90a::decodeENC_VOP3P_MFMA() + { + insn_size = 8; + layout_ENC_VOP3P_MFMA & layout = insn_layout.ENC_VOP3P_MFMA; + layout.ABID = longfield<11,14>(insn_long); + layout.ACC = longfield<59,60>(insn_long); + layout.ACC_CD = longfield<15,15>(insn_long); + layout.BLGP = longfield<61,63>(insn_long); + layout.CBSZ = longfield<8,10>(insn_long); + layout.ENCODING = longfield<23,31>(insn_long); + layout.OP = longfield<16,22>(insn_long); + layout.SRC0 = longfield<32,40>(insn_long); + layout.SRC1 = longfield<41,49>(insn_long); + layout.SRC2 = longfield<50,58>(insn_long); + layout.VDST = longfield<0,7>(insn_long); + assert(isArrayIndexValid(ENC_VOP3P_MFMA_insn_table, layout.OP) && "Opcode over or underflow"); + const amdgpu_gfx90a_insn_entry &insn_entry = ENC_VOP3P_MFMA_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_VOP3P_MFMAOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); + this->insn_in_progress->updateMnemonic(std::string(insn_entry.mnemonic) + extension); + } + + void InstructionDecoder_amdgpu_gfx90a::mainDecodeOpcode() + { + if (IS_ENC_SOP1(insn_long)) { + insn_size = 4; + uint32_t op_value = longfield<8,15>(insn_long); + assert(isArrayIndexValid(ENC_SOP1_insn_table, op_value) && "Opcode over or underflow"); + const amdgpu_gfx90a_insn_entry &insn_entry = ENC_SOP1_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_SOP1; + } + else if (IS_ENC_SOPC(insn_long)) { + insn_size = 4; + uint32_t op_value = longfield<16,22>(insn_long); + assert(isArrayIndexValid(ENC_SOPC_insn_table, op_value) && "Opcode over or underflow"); + const amdgpu_gfx90a_insn_entry &insn_entry = ENC_SOPC_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_SOPC; + } + else if (IS_ENC_SOPP(insn_long)) { + insn_size = 4; + uint32_t op_value = longfield<16,22>(insn_long); + assert(isArrayIndexValid(ENC_SOPP_insn_table, op_value) && "Opcode over or underflow"); + const amdgpu_gfx90a_insn_entry &insn_entry = ENC_SOPP_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_SOPP; + } + else if (IS_ENC_SOPK(insn_long)) { + insn_size = 4; + uint32_t op_value = longfield<23,27>(insn_long); + assert(isArrayIndexValid(ENC_SOPK_insn_table, op_value) && "Opcode over or underflow"); + const amdgpu_gfx90a_insn_entry &insn_entry = ENC_SOPK_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_SOPK; + } + else if (IS_ENC_SOP2(insn_long)) { + insn_size = 4; + uint32_t op_value = longfield<23,29>(insn_long); + assert(isArrayIndexValid(ENC_SOP2_insn_table, op_value) && "Opcode over or underflow"); + const amdgpu_gfx90a_insn_entry &insn_entry = ENC_SOP2_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_SOP2; + } + else if (IS_ENC_SMEM(insn_long)) { + insn_size = 8; + uint32_t op_value = longfield<18,25>(insn_long); + assert(isArrayIndexValid(ENC_SMEM_insn_table, op_value) && "Opcode over or underflow"); + const amdgpu_gfx90a_insn_entry &insn_entry = ENC_SMEM_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_SMEM; + } + else if (IS_ENC_VOP1(insn_long)) { + insn_size = 4; + uint32_t op_value = longfield<9,16>(insn_long); + assert(isArrayIndexValid(ENC_VOP1_insn_table, op_value) && "Opcode over or underflow"); + const amdgpu_gfx90a_insn_entry &insn_entry = ENC_VOP1_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_VOP1; + } + else if (IS_ENC_VOPC(insn_long)) { + insn_size = 4; + uint32_t op_value = longfield<17,24>(insn_long); + assert(isArrayIndexValid(ENC_VOPC_insn_table, op_value) && "Opcode over or underflow"); + const amdgpu_gfx90a_insn_entry &insn_entry = ENC_VOPC_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_VOPC; + } + else if (IS_ENC_VOP2(insn_long)) { + insn_size = 4; + uint32_t op_value = longfield<25,30>(insn_long); + assert(isArrayIndexValid(ENC_VOP2_insn_table, op_value) && "Opcode over or underflow"); + const amdgpu_gfx90a_insn_entry &insn_entry = ENC_VOP2_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_VOP2; + } + else if (IS_ENC_VINTRP(insn_long)) { + insn_size = 4; + uint32_t op_value = longfield<16,17>(insn_long); + assert(isArrayIndexValid(ENC_VINTRP_insn_table, op_value) && "Opcode over or underflow"); + const amdgpu_gfx90a_insn_entry &insn_entry = ENC_VINTRP_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_VINTRP; + } + else if (IS_ENC_VOP3P(insn_long)) { + insn_size = 8; + uint32_t op_value = longfield<16,22>(insn_long); + assert(isArrayIndexValid(ENC_VOP3P_insn_table, op_value) && "Opcode over or underflow"); + const amdgpu_gfx90a_insn_entry &insn_entry = ENC_VOP3P_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_VOP3P; + } + else if (IS_ENC_VOP3(insn_long)) { + insn_size = 8; + uint32_t op_value = longfield<16,25>(insn_long); + assert(isArrayIndexValid(ENC_VOP3_insn_table, op_value) && "Opcode over or underflow"); + const amdgpu_gfx90a_insn_entry &insn_entry = ENC_VOP3_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_VOP3; + } + else if (IS_ENC_DS(insn_long)) { + insn_size = 8; + uint32_t op_value = longfield<17,24>(insn_long); + assert(isArrayIndexValid(ENC_DS_insn_table, op_value) && "Opcode over or underflow"); + const amdgpu_gfx90a_insn_entry &insn_entry = ENC_DS_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_DS; + } + else if (IS_ENC_MUBUF(insn_long)) { + insn_size = 8; + uint32_t op_value = longfield<18,24>(insn_long); + assert(isArrayIndexValid(ENC_MUBUF_insn_table, op_value) && "Opcode over or underflow"); + const amdgpu_gfx90a_insn_entry &insn_entry = ENC_MUBUF_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_MUBUF; + } + else if (IS_ENC_MTBUF(insn_long)) { + insn_size = 8; + uint32_t op_value = longfield<15,18>(insn_long); + assert(isArrayIndexValid(ENC_MTBUF_insn_table, op_value) && "Opcode over or underflow"); + const amdgpu_gfx90a_insn_entry &insn_entry = ENC_MTBUF_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_MTBUF; + } + else if (IS_ENC_MIMG(insn_long)) { + insn_size = 8; + uint32_t op_value = longfield<18,24>(insn_long); + assert(isArrayIndexValid(ENC_MIMG_insn_table, op_value) && "Opcode over or underflow"); + const amdgpu_gfx90a_insn_entry &insn_entry = ENC_MIMG_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_MIMG; + } + else if (IS_ENC_FLAT(insn_long)) { + insn_size = 8; + uint32_t op_value = longfield<18,24>(insn_long); + assert(isArrayIndexValid(ENC_FLAT_insn_table, op_value) && "Opcode over or underflow"); + const amdgpu_gfx90a_insn_entry &insn_entry = ENC_FLAT_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_FLAT; + } + else if (IS_ENC_FLAT_GLBL(insn_long)) { + insn_size = 8; + uint32_t op_value = longfield<18,24>(insn_long); + assert(isArrayIndexValid(ENC_FLAT_GLBL_insn_table, op_value) && "Opcode over or underflow"); + const amdgpu_gfx90a_insn_entry &insn_entry = ENC_FLAT_GLBL_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_FLAT_GLBL; + } + else if (IS_ENC_FLAT_SCRATCH(insn_long)) { + insn_size = 8; + uint32_t op_value = longfield<18,24>(insn_long); + assert(isArrayIndexValid(ENC_FLAT_SCRATCH_insn_table, op_value) && "Opcode over or underflow"); + const amdgpu_gfx90a_insn_entry &insn_entry = ENC_FLAT_SCRATCH_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_FLAT_SCRATCH; + } + else if (IS_SOPK_INST_LITERAL_(insn_long)) { + insn_size = 8; + uint32_t op_value = longfield<23,27>(insn_long); + assert(isArrayIndexValid(SOPK_INST_LITERAL__insn_table, op_value) && "Opcode over or underflow"); + const amdgpu_gfx90a_insn_entry &insn_entry = SOPK_INST_LITERAL__insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = SOPK_INST_LITERAL_; + } + else if (IS_ENC_VOP2_LITERAL(insn_long)) { + insn_size = 8; + uint32_t op_value = longfield<25,30>(insn_long); + assert(isArrayIndexValid(ENC_VOP2_LITERAL_insn_table, op_value) && "Opcode over or underflow"); + const amdgpu_gfx90a_insn_entry &insn_entry = ENC_VOP2_LITERAL_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_VOP2_LITERAL; + } + else if (IS_ENC_VOP3B(insn_long)) { + insn_size = 8; + uint32_t op_value = longfield<16,25>(insn_long); + assert(isArrayIndexValid(ENC_VOP3B_insn_table, op_value) && "Opcode over or underflow"); + const amdgpu_gfx90a_insn_entry &insn_entry = ENC_VOP3B_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_VOP3B; + } + else if (IS_ENC_VOP3P_MFMA(insn_long)) { + insn_size = 8; + uint32_t op_value = longfield<16,22>(insn_long); + assert(isArrayIndexValid(ENC_VOP3P_MFMA_insn_table, op_value) && "Opcode over or underflow"); + const amdgpu_gfx90a_insn_entry &insn_entry = ENC_VOP3P_MFMA_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_VOP3P_MFMA; + } + } + + void InstructionDecoder_amdgpu_gfx90a::mainDecode() + { + if (IS_ENC_SOP1(insn_long)) { + decodeENC_SOP1(); + } + else if (IS_ENC_SOPC(insn_long)) { + decodeENC_SOPC(); + } + else if (IS_ENC_SOPP(insn_long)) { + decodeENC_SOPP(); + } + else if (IS_ENC_SOPK(insn_long)) { + decodeENC_SOPK(); + } + else if (IS_ENC_SOP2(insn_long)) { + decodeENC_SOP2(); + } + else if (IS_ENC_SMEM(insn_long)) { + decodeENC_SMEM(); + } + else if (IS_ENC_VOP1(insn_long)) { + decodeENC_VOP1(); + } + else if (IS_ENC_VOPC(insn_long)) { + decodeENC_VOPC(); + } + else if (IS_ENC_VOP2(insn_long)) { + decodeENC_VOP2(); + } + else if (IS_ENC_VINTRP(insn_long)) { + decodeENC_VINTRP(); + } + else if (IS_ENC_VOP3P(insn_long)) { + decodeENC_VOP3P(); + } + else if (IS_ENC_VOP3(insn_long)) { + decodeENC_VOP3(); + } + else if (IS_ENC_DS(insn_long)) { + decodeENC_DS(); + } + else if (IS_ENC_MUBUF(insn_long)) { + decodeENC_MUBUF(); + } + else if (IS_ENC_MTBUF(insn_long)) { + decodeENC_MTBUF(); + } + else if (IS_ENC_MIMG(insn_long)) { + decodeENC_MIMG(); + } + else if (IS_ENC_FLAT(insn_long)) { + decodeENC_FLAT(); + } + else if (IS_ENC_FLAT_GLBL(insn_long)) { + decodeENC_FLAT_GLBL(); + } + else if (IS_ENC_FLAT_SCRATCH(insn_long)) { + decodeENC_FLAT_SCRATCH(); + } + else if (IS_SOPK_INST_LITERAL_(insn_long)) { + decodeSOPK_INST_LITERAL_(); + } + else if (IS_ENC_VOP2_LITERAL(insn_long)) { + decodeENC_VOP2_LITERAL(); + } + else if (IS_ENC_VOP3B(insn_long)) { + decodeENC_VOP3B(); + } + else if (IS_ENC_VOP3P_MFMA(insn_long)) { + decodeENC_VOP3P_MFMA(); + } + } + +} +} diff --git a/instructionAPI/src/AMDGPU/gfx90a/amdgpu_gfx90a_insn_entry.h b/instructionAPI/src/AMDGPU/gfx90a/amdgpu_gfx90a_insn_entry.h new file mode 100644 index 0000000000..5d09c8fa50 --- /dev/null +++ b/instructionAPI/src/AMDGPU/gfx90a/amdgpu_gfx90a_insn_entry.h @@ -0,0 +1,33 @@ +#include + +struct amdgpu_gfx90a_insn_entry { + entryID op; + const char *mnemonic; + std::size_t operandCnt; + const operandFactory *operands; + static const amdgpu_gfx90a_insn_table main_insn_table ; + static const operandFactory operandTable[] ; + static const amdgpu_gfx90a_insn_table ENC_DS_insn_table ; + static const amdgpu_gfx90a_insn_table ENC_FLAT_insn_table ; + static const amdgpu_gfx90a_insn_table ENC_FLAT_GLBL_insn_table ; + static const amdgpu_gfx90a_insn_table ENC_FLAT_SCRATCH_insn_table ; + static const amdgpu_gfx90a_insn_table ENC_MIMG_insn_table ; + static const amdgpu_gfx90a_insn_table ENC_MTBUF_insn_table ; + static const amdgpu_gfx90a_insn_table ENC_MUBUF_insn_table ; + static const amdgpu_gfx90a_insn_table ENC_SMEM_insn_table ; + static const amdgpu_gfx90a_insn_table ENC_SOP1_insn_table ; + static const amdgpu_gfx90a_insn_table ENC_SOP2_insn_table ; + static const amdgpu_gfx90a_insn_table ENC_SOPC_insn_table ; + static const amdgpu_gfx90a_insn_table ENC_SOPK_insn_table ; + static const amdgpu_gfx90a_insn_table SOPK_INST_LITERAL__insn_table ; + static const amdgpu_gfx90a_insn_table ENC_SOPP_insn_table ; + static const amdgpu_gfx90a_insn_table ENC_VOP1_insn_table ; + static const amdgpu_gfx90a_insn_table ENC_VOP3_insn_table ; + static const amdgpu_gfx90a_insn_table ENC_VOP2_insn_table ; + static const amdgpu_gfx90a_insn_table ENC_VOP2_LITERAL_insn_table ; + static const amdgpu_gfx90a_insn_table ENC_VOP3B_insn_table ; + static const amdgpu_gfx90a_insn_table ENC_VOP3P_insn_table ; + static const amdgpu_gfx90a_insn_table ENC_VOP3P_MFMA_insn_table ; + static const amdgpu_gfx90a_insn_table ENC_VOPC_insn_table ; + static const amdgpu_gfx90a_insn_table ENC_VINTRP_insn_table ; +}; diff --git a/instructionAPI/src/AMDGPU/gfx90a/amdgpu_gfx90a_opcode_tables.C b/instructionAPI/src/AMDGPU/gfx90a/amdgpu_gfx90a_opcode_tables.C new file mode 100644 index 0000000000..a92d73016b --- /dev/null +++ b/instructionAPI/src/AMDGPU/gfx90a/amdgpu_gfx90a_opcode_tables.C @@ -0,0 +1,2921 @@ + const amdgpu_gfx90a_insn_entry ENC_DS_insn_table [256] = + { + {amdgpu_gfx90a_op_DS_ADD_U32,"DS_ADD_U32"} ,//0 + {amdgpu_gfx90a_op_DS_SUB_U32,"DS_SUB_U32"} ,//1 + {amdgpu_gfx90a_op_DS_RSUB_U32,"DS_RSUB_U32"} ,//2 + {amdgpu_gfx90a_op_DS_INC_U32,"DS_INC_U32"} ,//3 + {amdgpu_gfx90a_op_DS_DEC_U32,"DS_DEC_U32"} ,//4 + {amdgpu_gfx90a_op_DS_MIN_I32,"DS_MIN_I32"} ,//5 + {amdgpu_gfx90a_op_DS_MAX_I32,"DS_MAX_I32"} ,//6 + {amdgpu_gfx90a_op_DS_MIN_U32,"DS_MIN_U32"} ,//7 + {amdgpu_gfx90a_op_DS_MAX_U32,"DS_MAX_U32"} ,//8 + {amdgpu_gfx90a_op_DS_AND_B32,"DS_AND_B32"} ,//9 + {amdgpu_gfx90a_op_DS_OR_B32,"DS_OR_B32"} ,//10 + {amdgpu_gfx90a_op_DS_XOR_B32,"DS_XOR_B32"} ,//11 + {amdgpu_gfx90a_op_DS_MSKOR_B32,"DS_MSKOR_B32"} ,//12 + {amdgpu_gfx90a_op_DS_WRITE_B32,"DS_WRITE_B32"} ,//13 + {amdgpu_gfx90a_op_DS_WRITE2_B32,"DS_WRITE2_B32"} ,//14 + {amdgpu_gfx90a_op_DS_WRITE2ST64_B32,"DS_WRITE2ST64_B32"} ,//15 + {amdgpu_gfx90a_op_DS_CMPST_B32,"DS_CMPST_B32"} ,//16 + {amdgpu_gfx90a_op_DS_CMPST_F32,"DS_CMPST_F32"} ,//17 + {amdgpu_gfx90a_op_DS_MIN_F32,"DS_MIN_F32"} ,//18 + {amdgpu_gfx90a_op_DS_MAX_F32,"DS_MAX_F32"} ,//19 + {amdgpu_gfx90a_op_DS_NOP,"DS_NOP"} ,//20 + {amdgpu_gfx90a_op_DS_ADD_F32,"DS_ADD_F32"} ,//21 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//22 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//23 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//24 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//25 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//26 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//27 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//28 + {amdgpu_gfx90a_op_DS_WRITE_ADDTID_B32,"DS_WRITE_ADDTID_B32"} ,//29 + {amdgpu_gfx90a_op_DS_WRITE_B8,"DS_WRITE_B8"} ,//30 + {amdgpu_gfx90a_op_DS_WRITE_B16,"DS_WRITE_B16"} ,//31 + {amdgpu_gfx90a_op_DS_ADD_RTN_U32,"DS_ADD_RTN_U32"} ,//32 + {amdgpu_gfx90a_op_DS_SUB_RTN_U32,"DS_SUB_RTN_U32"} ,//33 + {amdgpu_gfx90a_op_DS_RSUB_RTN_U32,"DS_RSUB_RTN_U32"} ,//34 + {amdgpu_gfx90a_op_DS_INC_RTN_U32,"DS_INC_RTN_U32"} ,//35 + {amdgpu_gfx90a_op_DS_DEC_RTN_U32,"DS_DEC_RTN_U32"} ,//36 + {amdgpu_gfx90a_op_DS_MIN_RTN_I32,"DS_MIN_RTN_I32"} ,//37 + {amdgpu_gfx90a_op_DS_MAX_RTN_I32,"DS_MAX_RTN_I32"} ,//38 + {amdgpu_gfx90a_op_DS_MIN_RTN_U32,"DS_MIN_RTN_U32"} ,//39 + {amdgpu_gfx90a_op_DS_MAX_RTN_U32,"DS_MAX_RTN_U32"} ,//40 + {amdgpu_gfx90a_op_DS_AND_RTN_B32,"DS_AND_RTN_B32"} ,//41 + {amdgpu_gfx90a_op_DS_OR_RTN_B32,"DS_OR_RTN_B32"} ,//42 + {amdgpu_gfx90a_op_DS_XOR_RTN_B32,"DS_XOR_RTN_B32"} ,//43 + {amdgpu_gfx90a_op_DS_MSKOR_RTN_B32,"DS_MSKOR_RTN_B32"} ,//44 + {amdgpu_gfx90a_op_DS_WRXCHG_RTN_B32,"DS_WRXCHG_RTN_B32"} ,//45 + {amdgpu_gfx90a_op_DS_WRXCHG2_RTN_B32,"DS_WRXCHG2_RTN_B32"} ,//46 + {amdgpu_gfx90a_op_DS_WRXCHG2ST64_RTN_B32,"DS_WRXCHG2ST64_RTN_B32"} ,//47 + {amdgpu_gfx90a_op_DS_CMPST_RTN_B32,"DS_CMPST_RTN_B32"} ,//48 + {amdgpu_gfx90a_op_DS_CMPST_RTN_F32,"DS_CMPST_RTN_F32"} ,//49 + {amdgpu_gfx90a_op_DS_MIN_RTN_F32,"DS_MIN_RTN_F32"} ,//50 + {amdgpu_gfx90a_op_DS_MAX_RTN_F32,"DS_MAX_RTN_F32"} ,//51 + {amdgpu_gfx90a_op_DS_WRAP_RTN_B32,"DS_WRAP_RTN_B32"} ,//52 + {amdgpu_gfx90a_op_DS_ADD_RTN_F32,"DS_ADD_RTN_F32"} ,//53 + {amdgpu_gfx90a_op_DS_READ_B32,"DS_READ_B32"} ,//54 + {amdgpu_gfx90a_op_DS_READ2_B32,"DS_READ2_B32"} ,//55 + {amdgpu_gfx90a_op_DS_READ2ST64_B32,"DS_READ2ST64_B32"} ,//56 + {amdgpu_gfx90a_op_DS_READ_I8,"DS_READ_I8"} ,//57 + {amdgpu_gfx90a_op_DS_READ_U8,"DS_READ_U8"} ,//58 + {amdgpu_gfx90a_op_DS_READ_I16,"DS_READ_I16"} ,//59 + {amdgpu_gfx90a_op_DS_READ_U16,"DS_READ_U16"} ,//60 + {amdgpu_gfx90a_op_DS_SWIZZLE_B32,"DS_SWIZZLE_B32"} ,//61 + {amdgpu_gfx90a_op_DS_PERMUTE_B32,"DS_PERMUTE_B32"} ,//62 + {amdgpu_gfx90a_op_DS_BPERMUTE_B32,"DS_BPERMUTE_B32"} ,//63 + {amdgpu_gfx90a_op_DS_ADD_U64,"DS_ADD_U64"} ,//64 + {amdgpu_gfx90a_op_DS_SUB_U64,"DS_SUB_U64"} ,//65 + {amdgpu_gfx90a_op_DS_RSUB_U64,"DS_RSUB_U64"} ,//66 + {amdgpu_gfx90a_op_DS_INC_U64,"DS_INC_U64"} ,//67 + {amdgpu_gfx90a_op_DS_DEC_U64,"DS_DEC_U64"} ,//68 + {amdgpu_gfx90a_op_DS_MIN_I64,"DS_MIN_I64"} ,//69 + {amdgpu_gfx90a_op_DS_MAX_I64,"DS_MAX_I64"} ,//70 + {amdgpu_gfx90a_op_DS_MIN_U64,"DS_MIN_U64"} ,//71 + {amdgpu_gfx90a_op_DS_MAX_U64,"DS_MAX_U64"} ,//72 + {amdgpu_gfx90a_op_DS_AND_B64,"DS_AND_B64"} ,//73 + {amdgpu_gfx90a_op_DS_OR_B64,"DS_OR_B64"} ,//74 + {amdgpu_gfx90a_op_DS_XOR_B64,"DS_XOR_B64"} ,//75 + {amdgpu_gfx90a_op_DS_MSKOR_B64,"DS_MSKOR_B64"} ,//76 + {amdgpu_gfx90a_op_DS_WRITE_B64,"DS_WRITE_B64"} ,//77 + {amdgpu_gfx90a_op_DS_WRITE2_B64,"DS_WRITE2_B64"} ,//78 + {amdgpu_gfx90a_op_DS_WRITE2ST64_B64,"DS_WRITE2ST64_B64"} ,//79 + {amdgpu_gfx90a_op_DS_CMPST_B64,"DS_CMPST_B64"} ,//80 + {amdgpu_gfx90a_op_DS_CMPST_F64,"DS_CMPST_F64"} ,//81 + {amdgpu_gfx90a_op_DS_MIN_F64,"DS_MIN_F64"} ,//82 + {amdgpu_gfx90a_op_DS_MAX_F64,"DS_MAX_F64"} ,//83 + {amdgpu_gfx90a_op_DS_WRITE_B8_D16_HI,"DS_WRITE_B8_D16_HI"} ,//84 + {amdgpu_gfx90a_op_DS_WRITE_B16_D16_HI,"DS_WRITE_B16_D16_HI"} ,//85 + {amdgpu_gfx90a_op_DS_READ_U8_D16,"DS_READ_U8_D16"} ,//86 + {amdgpu_gfx90a_op_DS_READ_U8_D16_HI,"DS_READ_U8_D16_HI"} ,//87 + {amdgpu_gfx90a_op_DS_READ_I8_D16,"DS_READ_I8_D16"} ,//88 + {amdgpu_gfx90a_op_DS_READ_I8_D16_HI,"DS_READ_I8_D16_HI"} ,//89 + {amdgpu_gfx90a_op_DS_READ_U16_D16,"DS_READ_U16_D16"} ,//90 + {amdgpu_gfx90a_op_DS_READ_U16_D16_HI,"DS_READ_U16_D16_HI"} ,//91 + {amdgpu_gfx90a_op_DS_ADD_F64,"DS_ADD_F64"} ,//92 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//93 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//94 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//95 + {amdgpu_gfx90a_op_DS_ADD_RTN_U64,"DS_ADD_RTN_U64"} ,//96 + {amdgpu_gfx90a_op_DS_SUB_RTN_U64,"DS_SUB_RTN_U64"} ,//97 + {amdgpu_gfx90a_op_DS_RSUB_RTN_U64,"DS_RSUB_RTN_U64"} ,//98 + {amdgpu_gfx90a_op_DS_INC_RTN_U64,"DS_INC_RTN_U64"} ,//99 + {amdgpu_gfx90a_op_DS_DEC_RTN_U64,"DS_DEC_RTN_U64"} ,//100 + {amdgpu_gfx90a_op_DS_MIN_RTN_I64,"DS_MIN_RTN_I64"} ,//101 + {amdgpu_gfx90a_op_DS_MAX_RTN_I64,"DS_MAX_RTN_I64"} ,//102 + {amdgpu_gfx90a_op_DS_MIN_RTN_U64,"DS_MIN_RTN_U64"} ,//103 + {amdgpu_gfx90a_op_DS_MAX_RTN_U64,"DS_MAX_RTN_U64"} ,//104 + {amdgpu_gfx90a_op_DS_AND_RTN_B64,"DS_AND_RTN_B64"} ,//105 + {amdgpu_gfx90a_op_DS_OR_RTN_B64,"DS_OR_RTN_B64"} ,//106 + {amdgpu_gfx90a_op_DS_XOR_RTN_B64,"DS_XOR_RTN_B64"} ,//107 + {amdgpu_gfx90a_op_DS_MSKOR_RTN_B64,"DS_MSKOR_RTN_B64"} ,//108 + {amdgpu_gfx90a_op_DS_WRXCHG_RTN_B64,"DS_WRXCHG_RTN_B64"} ,//109 + {amdgpu_gfx90a_op_DS_WRXCHG2_RTN_B64,"DS_WRXCHG2_RTN_B64"} ,//110 + {amdgpu_gfx90a_op_DS_WRXCHG2ST64_RTN_B64,"DS_WRXCHG2ST64_RTN_B64"} ,//111 + {amdgpu_gfx90a_op_DS_CMPST_RTN_B64,"DS_CMPST_RTN_B64"} ,//112 + {amdgpu_gfx90a_op_DS_CMPST_RTN_F64,"DS_CMPST_RTN_F64"} ,//113 + {amdgpu_gfx90a_op_DS_MIN_RTN_F64,"DS_MIN_RTN_F64"} ,//114 + {amdgpu_gfx90a_op_DS_MAX_RTN_F64,"DS_MAX_RTN_F64"} ,//115 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//116 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//117 + {amdgpu_gfx90a_op_DS_READ_B64,"DS_READ_B64"} ,//118 + {amdgpu_gfx90a_op_DS_READ2_B64,"DS_READ2_B64"} ,//119 + {amdgpu_gfx90a_op_DS_READ2ST64_B64,"DS_READ2ST64_B64"} ,//120 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//121 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//122 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//123 + {amdgpu_gfx90a_op_DS_ADD_RTN_F64,"DS_ADD_RTN_F64"} ,//124 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//125 + {amdgpu_gfx90a_op_DS_CONDXCHG32_RTN_B64,"DS_CONDXCHG32_RTN_B64"} ,//126 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//127 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//128 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//129 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//130 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//131 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//132 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//133 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//134 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//135 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//136 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//137 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//138 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//139 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//140 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//141 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//142 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//143 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//144 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//145 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//146 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//147 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//148 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//149 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//150 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//151 + {amdgpu_gfx90a_op_DS_GWS_SEMA_RELEASE_ALL,"DS_GWS_SEMA_RELEASE_ALL"} ,//152 + {amdgpu_gfx90a_op_DS_GWS_INIT,"DS_GWS_INIT"} ,//153 + {amdgpu_gfx90a_op_DS_GWS_SEMA_V,"DS_GWS_SEMA_V"} ,//154 + {amdgpu_gfx90a_op_DS_GWS_SEMA_BR,"DS_GWS_SEMA_BR"} ,//155 + {amdgpu_gfx90a_op_DS_GWS_SEMA_P,"DS_GWS_SEMA_P"} ,//156 + {amdgpu_gfx90a_op_DS_GWS_BARRIER,"DS_GWS_BARRIER"} ,//157 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//158 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//159 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//160 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//161 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//162 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//163 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//164 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//165 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//166 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//167 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//168 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//169 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//170 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//171 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//172 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//173 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//174 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//175 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//176 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//177 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//178 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//179 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//180 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//181 + {amdgpu_gfx90a_op_DS_READ_ADDTID_B32,"DS_READ_ADDTID_B32"} ,//182 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//183 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//184 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//185 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//186 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//187 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//188 + {amdgpu_gfx90a_op_DS_CONSUME,"DS_CONSUME"} ,//189 + {amdgpu_gfx90a_op_DS_APPEND,"DS_APPEND"} ,//190 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//191 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//192 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//193 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//194 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//195 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//196 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//197 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//198 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//199 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//200 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//201 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//202 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//203 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//204 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//205 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//206 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//207 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//208 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//209 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//210 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//211 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//212 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//213 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//214 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//215 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//216 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//217 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//218 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//219 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//220 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//221 + {amdgpu_gfx90a_op_DS_WRITE_B96,"DS_WRITE_B96"} ,//222 + {amdgpu_gfx90a_op_DS_WRITE_B128,"DS_WRITE_B128"} ,//223 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//224 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//225 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//226 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//227 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//228 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//229 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//230 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//231 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//232 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//233 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//234 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//235 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//236 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//237 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//238 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//239 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//240 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//241 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//242 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//243 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//244 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//245 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//246 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//247 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//248 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//249 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//250 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//251 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//252 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//253 + {amdgpu_gfx90a_op_DS_READ_B96,"DS_READ_B96"} ,//254 + {amdgpu_gfx90a_op_DS_READ_B128,"DS_READ_B128"} ,//255 + }; // end ENC_DS_insn_table + const amdgpu_gfx90a_insn_entry ENC_FLAT_insn_table [109] = + { + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//0 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//1 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//2 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//3 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//4 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//5 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//6 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//7 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//8 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//9 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//10 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//11 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//12 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//13 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//14 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//15 + {amdgpu_gfx90a_op_FLAT_LOAD_UBYTE,"FLAT_LOAD_UBYTE"} ,//16 + {amdgpu_gfx90a_op_FLAT_LOAD_SBYTE,"FLAT_LOAD_SBYTE"} ,//17 + {amdgpu_gfx90a_op_FLAT_LOAD_USHORT,"FLAT_LOAD_USHORT"} ,//18 + {amdgpu_gfx90a_op_FLAT_LOAD_SSHORT,"FLAT_LOAD_SSHORT"} ,//19 + {amdgpu_gfx90a_op_FLAT_LOAD_DWORD,"FLAT_LOAD_DWORD"} ,//20 + {amdgpu_gfx90a_op_FLAT_LOAD_DWORDX2,"FLAT_LOAD_DWORDX2"} ,//21 + {amdgpu_gfx90a_op_FLAT_LOAD_DWORDX3,"FLAT_LOAD_DWORDX3"} ,//22 + {amdgpu_gfx90a_op_FLAT_LOAD_DWORDX4,"FLAT_LOAD_DWORDX4"} ,//23 + {amdgpu_gfx90a_op_FLAT_STORE_BYTE,"FLAT_STORE_BYTE"} ,//24 + {amdgpu_gfx90a_op_FLAT_STORE_BYTE_D16_HI,"FLAT_STORE_BYTE_D16_HI"} ,//25 + {amdgpu_gfx90a_op_FLAT_STORE_SHORT,"FLAT_STORE_SHORT"} ,//26 + {amdgpu_gfx90a_op_FLAT_STORE_SHORT_D16_HI,"FLAT_STORE_SHORT_D16_HI"} ,//27 + {amdgpu_gfx90a_op_FLAT_STORE_DWORD,"FLAT_STORE_DWORD"} ,//28 + {amdgpu_gfx90a_op_FLAT_STORE_DWORDX2,"FLAT_STORE_DWORDX2"} ,//29 + {amdgpu_gfx90a_op_FLAT_STORE_DWORDX3,"FLAT_STORE_DWORDX3"} ,//30 + {amdgpu_gfx90a_op_FLAT_STORE_DWORDX4,"FLAT_STORE_DWORDX4"} ,//31 + {amdgpu_gfx90a_op_FLAT_LOAD_UBYTE_D16,"FLAT_LOAD_UBYTE_D16"} ,//32 + {amdgpu_gfx90a_op_FLAT_LOAD_UBYTE_D16_HI,"FLAT_LOAD_UBYTE_D16_HI"} ,//33 + {amdgpu_gfx90a_op_FLAT_LOAD_SBYTE_D16,"FLAT_LOAD_SBYTE_D16"} ,//34 + {amdgpu_gfx90a_op_FLAT_LOAD_SBYTE_D16_HI,"FLAT_LOAD_SBYTE_D16_HI"} ,//35 + {amdgpu_gfx90a_op_FLAT_LOAD_SHORT_D16,"FLAT_LOAD_SHORT_D16"} ,//36 + {amdgpu_gfx90a_op_FLAT_LOAD_SHORT_D16_HI,"FLAT_LOAD_SHORT_D16_HI"} ,//37 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//38 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//39 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//40 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//41 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//42 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//43 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//44 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//45 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//46 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//47 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//48 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//49 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//50 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//51 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//52 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//53 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//54 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//55 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//56 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//57 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//58 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//59 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//60 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//61 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//62 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//63 + {amdgpu_gfx90a_op_FLAT_ATOMIC_SWAP,"FLAT_ATOMIC_SWAP"} ,//64 + {amdgpu_gfx90a_op_FLAT_ATOMIC_CMPSWAP,"FLAT_ATOMIC_CMPSWAP"} ,//65 + {amdgpu_gfx90a_op_FLAT_ATOMIC_ADD,"FLAT_ATOMIC_ADD"} ,//66 + {amdgpu_gfx90a_op_FLAT_ATOMIC_SUB,"FLAT_ATOMIC_SUB"} ,//67 + {amdgpu_gfx90a_op_FLAT_ATOMIC_SMIN,"FLAT_ATOMIC_SMIN"} ,//68 + {amdgpu_gfx90a_op_FLAT_ATOMIC_UMIN,"FLAT_ATOMIC_UMIN"} ,//69 + {amdgpu_gfx90a_op_FLAT_ATOMIC_SMAX,"FLAT_ATOMIC_SMAX"} ,//70 + {amdgpu_gfx90a_op_FLAT_ATOMIC_UMAX,"FLAT_ATOMIC_UMAX"} ,//71 + {amdgpu_gfx90a_op_FLAT_ATOMIC_AND,"FLAT_ATOMIC_AND"} ,//72 + {amdgpu_gfx90a_op_FLAT_ATOMIC_OR,"FLAT_ATOMIC_OR"} ,//73 + {amdgpu_gfx90a_op_FLAT_ATOMIC_XOR,"FLAT_ATOMIC_XOR"} ,//74 + {amdgpu_gfx90a_op_FLAT_ATOMIC_INC,"FLAT_ATOMIC_INC"} ,//75 + {amdgpu_gfx90a_op_FLAT_ATOMIC_DEC,"FLAT_ATOMIC_DEC"} ,//76 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//77 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//78 + {amdgpu_gfx90a_op_FLAT_ATOMIC_ADD_F64,"FLAT_ATOMIC_ADD_F64"} ,//79 + {amdgpu_gfx90a_op_FLAT_ATOMIC_MIN_F64,"FLAT_ATOMIC_MIN_F64"} ,//80 + {amdgpu_gfx90a_op_FLAT_ATOMIC_MAX_F64,"FLAT_ATOMIC_MAX_F64"} ,//81 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//82 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//83 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//84 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//85 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//86 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//87 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//88 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//89 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//90 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//91 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//92 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//93 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//94 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//95 + {amdgpu_gfx90a_op_FLAT_ATOMIC_SWAP_X2,"FLAT_ATOMIC_SWAP_X2"} ,//96 + {amdgpu_gfx90a_op_FLAT_ATOMIC_CMPSWAP_X2,"FLAT_ATOMIC_CMPSWAP_X2"} ,//97 + {amdgpu_gfx90a_op_FLAT_ATOMIC_ADD_X2,"FLAT_ATOMIC_ADD_X2"} ,//98 + {amdgpu_gfx90a_op_FLAT_ATOMIC_SUB_X2,"FLAT_ATOMIC_SUB_X2"} ,//99 + {amdgpu_gfx90a_op_FLAT_ATOMIC_SMIN_X2,"FLAT_ATOMIC_SMIN_X2"} ,//100 + {amdgpu_gfx90a_op_FLAT_ATOMIC_UMIN_X2,"FLAT_ATOMIC_UMIN_X2"} ,//101 + {amdgpu_gfx90a_op_FLAT_ATOMIC_SMAX_X2,"FLAT_ATOMIC_SMAX_X2"} ,//102 + {amdgpu_gfx90a_op_FLAT_ATOMIC_UMAX_X2,"FLAT_ATOMIC_UMAX_X2"} ,//103 + {amdgpu_gfx90a_op_FLAT_ATOMIC_AND_X2,"FLAT_ATOMIC_AND_X2"} ,//104 + {amdgpu_gfx90a_op_FLAT_ATOMIC_OR_X2,"FLAT_ATOMIC_OR_X2"} ,//105 + {amdgpu_gfx90a_op_FLAT_ATOMIC_XOR_X2,"FLAT_ATOMIC_XOR_X2"} ,//106 + {amdgpu_gfx90a_op_FLAT_ATOMIC_INC_X2,"FLAT_ATOMIC_INC_X2"} ,//107 + {amdgpu_gfx90a_op_FLAT_ATOMIC_DEC_X2,"FLAT_ATOMIC_DEC_X2"} ,//108 + }; // end ENC_FLAT_insn_table + const amdgpu_gfx90a_insn_entry ENC_FLAT_GLBL_insn_table [109] = + { + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//0 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//1 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//2 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//3 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//4 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//5 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//6 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//7 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//8 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//9 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//10 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//11 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//12 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//13 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//14 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//15 + {amdgpu_gfx90a_op_GLOBAL_LOAD_UBYTE,"GLOBAL_LOAD_UBYTE"} ,//16 + {amdgpu_gfx90a_op_GLOBAL_LOAD_SBYTE,"GLOBAL_LOAD_SBYTE"} ,//17 + {amdgpu_gfx90a_op_GLOBAL_LOAD_USHORT,"GLOBAL_LOAD_USHORT"} ,//18 + {amdgpu_gfx90a_op_GLOBAL_LOAD_SSHORT,"GLOBAL_LOAD_SSHORT"} ,//19 + {amdgpu_gfx90a_op_GLOBAL_LOAD_DWORD,"GLOBAL_LOAD_DWORD"} ,//20 + {amdgpu_gfx90a_op_GLOBAL_LOAD_DWORDX2,"GLOBAL_LOAD_DWORDX2"} ,//21 + {amdgpu_gfx90a_op_GLOBAL_LOAD_DWORDX3,"GLOBAL_LOAD_DWORDX3"} ,//22 + {amdgpu_gfx90a_op_GLOBAL_LOAD_DWORDX4,"GLOBAL_LOAD_DWORDX4"} ,//23 + {amdgpu_gfx90a_op_GLOBAL_STORE_BYTE,"GLOBAL_STORE_BYTE"} ,//24 + {amdgpu_gfx90a_op_GLOBAL_STORE_BYTE_D16_HI,"GLOBAL_STORE_BYTE_D16_HI"} ,//25 + {amdgpu_gfx90a_op_GLOBAL_STORE_SHORT,"GLOBAL_STORE_SHORT"} ,//26 + {amdgpu_gfx90a_op_GLOBAL_STORE_SHORT_D16_HI,"GLOBAL_STORE_SHORT_D16_HI"} ,//27 + {amdgpu_gfx90a_op_GLOBAL_STORE_DWORD,"GLOBAL_STORE_DWORD"} ,//28 + {amdgpu_gfx90a_op_GLOBAL_STORE_DWORDX2,"GLOBAL_STORE_DWORDX2"} ,//29 + {amdgpu_gfx90a_op_GLOBAL_STORE_DWORDX3,"GLOBAL_STORE_DWORDX3"} ,//30 + {amdgpu_gfx90a_op_GLOBAL_STORE_DWORDX4,"GLOBAL_STORE_DWORDX4"} ,//31 + {amdgpu_gfx90a_op_GLOBAL_LOAD_UBYTE_D16,"GLOBAL_LOAD_UBYTE_D16"} ,//32 + {amdgpu_gfx90a_op_GLOBAL_LOAD_UBYTE_D16_HI,"GLOBAL_LOAD_UBYTE_D16_HI"} ,//33 + {amdgpu_gfx90a_op_GLOBAL_LOAD_SBYTE_D16,"GLOBAL_LOAD_SBYTE_D16"} ,//34 + {amdgpu_gfx90a_op_GLOBAL_LOAD_SBYTE_D16_HI,"GLOBAL_LOAD_SBYTE_D16_HI"} ,//35 + {amdgpu_gfx90a_op_GLOBAL_LOAD_SHORT_D16,"GLOBAL_LOAD_SHORT_D16"} ,//36 + {amdgpu_gfx90a_op_GLOBAL_LOAD_SHORT_D16_HI,"GLOBAL_LOAD_SHORT_D16_HI"} ,//37 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//38 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//39 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//40 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//41 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//42 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//43 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//44 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//45 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//46 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//47 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//48 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//49 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//50 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//51 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//52 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//53 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//54 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//55 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//56 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//57 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//58 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//59 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//60 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//61 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//62 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//63 + {amdgpu_gfx90a_op_GLOBAL_ATOMIC_SWAP,"GLOBAL_ATOMIC_SWAP"} ,//64 + {amdgpu_gfx90a_op_GLOBAL_ATOMIC_CMPSWAP,"GLOBAL_ATOMIC_CMPSWAP"} ,//65 + {amdgpu_gfx90a_op_GLOBAL_ATOMIC_ADD,"GLOBAL_ATOMIC_ADD"} ,//66 + {amdgpu_gfx90a_op_GLOBAL_ATOMIC_SUB,"GLOBAL_ATOMIC_SUB"} ,//67 + {amdgpu_gfx90a_op_GLOBAL_ATOMIC_SMIN,"GLOBAL_ATOMIC_SMIN"} ,//68 + {amdgpu_gfx90a_op_GLOBAL_ATOMIC_UMIN,"GLOBAL_ATOMIC_UMIN"} ,//69 + {amdgpu_gfx90a_op_GLOBAL_ATOMIC_SMAX,"GLOBAL_ATOMIC_SMAX"} ,//70 + {amdgpu_gfx90a_op_GLOBAL_ATOMIC_UMAX,"GLOBAL_ATOMIC_UMAX"} ,//71 + {amdgpu_gfx90a_op_GLOBAL_ATOMIC_AND,"GLOBAL_ATOMIC_AND"} ,//72 + {amdgpu_gfx90a_op_GLOBAL_ATOMIC_OR,"GLOBAL_ATOMIC_OR"} ,//73 + {amdgpu_gfx90a_op_GLOBAL_ATOMIC_XOR,"GLOBAL_ATOMIC_XOR"} ,//74 + {amdgpu_gfx90a_op_GLOBAL_ATOMIC_INC,"GLOBAL_ATOMIC_INC"} ,//75 + {amdgpu_gfx90a_op_GLOBAL_ATOMIC_DEC,"GLOBAL_ATOMIC_DEC"} ,//76 + {amdgpu_gfx90a_op_GLOBAL_ATOMIC_ADD_F32,"GLOBAL_ATOMIC_ADD_F32"} ,//77 + {amdgpu_gfx90a_op_GLOBAL_ATOMIC_PK_ADD_F16,"GLOBAL_ATOMIC_PK_ADD_F16"} ,//78 + {amdgpu_gfx90a_op_GLOBAL_ATOMIC_ADD_F64,"GLOBAL_ATOMIC_ADD_F64"} ,//79 + {amdgpu_gfx90a_op_GLOBAL_ATOMIC_MIN_F64,"GLOBAL_ATOMIC_MIN_F64"} ,//80 + {amdgpu_gfx90a_op_GLOBAL_ATOMIC_MAX_F64,"GLOBAL_ATOMIC_MAX_F64"} ,//81 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//82 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//83 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//84 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//85 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//86 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//87 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//88 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//89 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//90 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//91 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//92 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//93 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//94 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//95 + {amdgpu_gfx90a_op_GLOBAL_ATOMIC_SWAP_X2,"GLOBAL_ATOMIC_SWAP_X2"} ,//96 + {amdgpu_gfx90a_op_GLOBAL_ATOMIC_CMPSWAP_X2,"GLOBAL_ATOMIC_CMPSWAP_X2"} ,//97 + {amdgpu_gfx90a_op_GLOBAL_ATOMIC_ADD_X2,"GLOBAL_ATOMIC_ADD_X2"} ,//98 + {amdgpu_gfx90a_op_GLOBAL_ATOMIC_SUB_X2,"GLOBAL_ATOMIC_SUB_X2"} ,//99 + {amdgpu_gfx90a_op_GLOBAL_ATOMIC_SMIN_X2,"GLOBAL_ATOMIC_SMIN_X2"} ,//100 + {amdgpu_gfx90a_op_GLOBAL_ATOMIC_UMIN_X2,"GLOBAL_ATOMIC_UMIN_X2"} ,//101 + {amdgpu_gfx90a_op_GLOBAL_ATOMIC_SMAX_X2,"GLOBAL_ATOMIC_SMAX_X2"} ,//102 + {amdgpu_gfx90a_op_GLOBAL_ATOMIC_UMAX_X2,"GLOBAL_ATOMIC_UMAX_X2"} ,//103 + {amdgpu_gfx90a_op_GLOBAL_ATOMIC_AND_X2,"GLOBAL_ATOMIC_AND_X2"} ,//104 + {amdgpu_gfx90a_op_GLOBAL_ATOMIC_OR_X2,"GLOBAL_ATOMIC_OR_X2"} ,//105 + {amdgpu_gfx90a_op_GLOBAL_ATOMIC_XOR_X2,"GLOBAL_ATOMIC_XOR_X2"} ,//106 + {amdgpu_gfx90a_op_GLOBAL_ATOMIC_INC_X2,"GLOBAL_ATOMIC_INC_X2"} ,//107 + {amdgpu_gfx90a_op_GLOBAL_ATOMIC_DEC_X2,"GLOBAL_ATOMIC_DEC_X2"} ,//108 + }; // end ENC_FLAT_GLBL_insn_table + const amdgpu_gfx90a_insn_entry ENC_FLAT_SCRATCH_insn_table [38] = + { + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//0 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//1 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//2 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//3 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//4 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//5 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//6 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//7 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//8 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//9 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//10 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//11 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//12 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//13 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//14 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//15 + {amdgpu_gfx90a_op_SCRATCH_LOAD_UBYTE,"SCRATCH_LOAD_UBYTE"} ,//16 + {amdgpu_gfx90a_op_SCRATCH_LOAD_SBYTE,"SCRATCH_LOAD_SBYTE"} ,//17 + {amdgpu_gfx90a_op_SCRATCH_LOAD_USHORT,"SCRATCH_LOAD_USHORT"} ,//18 + {amdgpu_gfx90a_op_SCRATCH_LOAD_SSHORT,"SCRATCH_LOAD_SSHORT"} ,//19 + {amdgpu_gfx90a_op_SCRATCH_LOAD_DWORD,"SCRATCH_LOAD_DWORD"} ,//20 + {amdgpu_gfx90a_op_SCRATCH_LOAD_DWORDX2,"SCRATCH_LOAD_DWORDX2"} ,//21 + {amdgpu_gfx90a_op_SCRATCH_LOAD_DWORDX3,"SCRATCH_LOAD_DWORDX3"} ,//22 + {amdgpu_gfx90a_op_SCRATCH_LOAD_DWORDX4,"SCRATCH_LOAD_DWORDX4"} ,//23 + {amdgpu_gfx90a_op_SCRATCH_STORE_BYTE,"SCRATCH_STORE_BYTE"} ,//24 + {amdgpu_gfx90a_op_SCRATCH_STORE_BYTE_D16_HI,"SCRATCH_STORE_BYTE_D16_HI"} ,//25 + {amdgpu_gfx90a_op_SCRATCH_STORE_SHORT,"SCRATCH_STORE_SHORT"} ,//26 + {amdgpu_gfx90a_op_SCRATCH_STORE_SHORT_D16_HI,"SCRATCH_STORE_SHORT_D16_HI"} ,//27 + {amdgpu_gfx90a_op_SCRATCH_STORE_DWORD,"SCRATCH_STORE_DWORD"} ,//28 + {amdgpu_gfx90a_op_SCRATCH_STORE_DWORDX2,"SCRATCH_STORE_DWORDX2"} ,//29 + {amdgpu_gfx90a_op_SCRATCH_STORE_DWORDX3,"SCRATCH_STORE_DWORDX3"} ,//30 + {amdgpu_gfx90a_op_SCRATCH_STORE_DWORDX4,"SCRATCH_STORE_DWORDX4"} ,//31 + {amdgpu_gfx90a_op_SCRATCH_LOAD_UBYTE_D16,"SCRATCH_LOAD_UBYTE_D16"} ,//32 + {amdgpu_gfx90a_op_SCRATCH_LOAD_UBYTE_D16_HI,"SCRATCH_LOAD_UBYTE_D16_HI"} ,//33 + {amdgpu_gfx90a_op_SCRATCH_LOAD_SBYTE_D16,"SCRATCH_LOAD_SBYTE_D16"} ,//34 + {amdgpu_gfx90a_op_SCRATCH_LOAD_SBYTE_D16_HI,"SCRATCH_LOAD_SBYTE_D16_HI"} ,//35 + {amdgpu_gfx90a_op_SCRATCH_LOAD_SHORT_D16,"SCRATCH_LOAD_SHORT_D16"} ,//36 + {amdgpu_gfx90a_op_SCRATCH_LOAD_SHORT_D16_HI,"SCRATCH_LOAD_SHORT_D16_HI"} ,//37 + }; // end ENC_FLAT_SCRATCH_insn_table + const amdgpu_gfx90a_insn_entry ENC_MIMG_insn_table [33] = + { + {amdgpu_gfx90a_op_IMAGE_LOAD,"IMAGE_LOAD"} ,//0 + {amdgpu_gfx90a_op_IMAGE_LOAD_MIP,"IMAGE_LOAD_MIP"} ,//1 + {amdgpu_gfx90a_op_IMAGE_LOAD_PCK,"IMAGE_LOAD_PCK"} ,//2 + {amdgpu_gfx90a_op_IMAGE_LOAD_PCK_SGN,"IMAGE_LOAD_PCK_SGN"} ,//3 + {amdgpu_gfx90a_op_IMAGE_LOAD_MIP_PCK,"IMAGE_LOAD_MIP_PCK"} ,//4 + {amdgpu_gfx90a_op_IMAGE_LOAD_MIP_PCK_SGN,"IMAGE_LOAD_MIP_PCK_SGN"} ,//5 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//6 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//7 + {amdgpu_gfx90a_op_IMAGE_STORE,"IMAGE_STORE"} ,//8 + {amdgpu_gfx90a_op_IMAGE_STORE_MIP,"IMAGE_STORE_MIP"} ,//9 + {amdgpu_gfx90a_op_IMAGE_STORE_PCK,"IMAGE_STORE_PCK"} ,//10 + {amdgpu_gfx90a_op_IMAGE_STORE_MIP_PCK,"IMAGE_STORE_MIP_PCK"} ,//11 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//12 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//13 + {amdgpu_gfx90a_op_IMAGE_GET_RESINFO,"IMAGE_GET_RESINFO"} ,//14 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//15 + {amdgpu_gfx90a_op_IMAGE_ATOMIC_SWAP,"IMAGE_ATOMIC_SWAP"} ,//16 + {amdgpu_gfx90a_op_IMAGE_ATOMIC_CMPSWAP,"IMAGE_ATOMIC_CMPSWAP"} ,//17 + {amdgpu_gfx90a_op_IMAGE_ATOMIC_ADD,"IMAGE_ATOMIC_ADD"} ,//18 + {amdgpu_gfx90a_op_IMAGE_ATOMIC_SUB,"IMAGE_ATOMIC_SUB"} ,//19 + {amdgpu_gfx90a_op_IMAGE_ATOMIC_SMIN,"IMAGE_ATOMIC_SMIN"} ,//20 + {amdgpu_gfx90a_op_IMAGE_ATOMIC_UMIN,"IMAGE_ATOMIC_UMIN"} ,//21 + {amdgpu_gfx90a_op_IMAGE_ATOMIC_SMAX,"IMAGE_ATOMIC_SMAX"} ,//22 + {amdgpu_gfx90a_op_IMAGE_ATOMIC_UMAX,"IMAGE_ATOMIC_UMAX"} ,//23 + {amdgpu_gfx90a_op_IMAGE_ATOMIC_AND,"IMAGE_ATOMIC_AND"} ,//24 + {amdgpu_gfx90a_op_IMAGE_ATOMIC_OR,"IMAGE_ATOMIC_OR"} ,//25 + {amdgpu_gfx90a_op_IMAGE_ATOMIC_XOR,"IMAGE_ATOMIC_XOR"} ,//26 + {amdgpu_gfx90a_op_IMAGE_ATOMIC_INC,"IMAGE_ATOMIC_INC"} ,//27 + {amdgpu_gfx90a_op_IMAGE_ATOMIC_DEC,"IMAGE_ATOMIC_DEC"} ,//28 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//29 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//30 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//31 + {amdgpu_gfx90a_op_IMAGE_SAMPLE,"IMAGE_SAMPLE"} ,//32 + }; // end ENC_MIMG_insn_table + const amdgpu_gfx90a_insn_entry ENC_MTBUF_insn_table [16] = + { + {amdgpu_gfx90a_op_TBUFFER_LOAD_FORMAT_X,"TBUFFER_LOAD_FORMAT_X"} ,//0 + {amdgpu_gfx90a_op_TBUFFER_LOAD_FORMAT_XY,"TBUFFER_LOAD_FORMAT_XY"} ,//1 + {amdgpu_gfx90a_op_TBUFFER_LOAD_FORMAT_XYZ,"TBUFFER_LOAD_FORMAT_XYZ"} ,//2 + {amdgpu_gfx90a_op_TBUFFER_LOAD_FORMAT_XYZW,"TBUFFER_LOAD_FORMAT_XYZW"} ,//3 + {amdgpu_gfx90a_op_TBUFFER_STORE_FORMAT_X,"TBUFFER_STORE_FORMAT_X"} ,//4 + {amdgpu_gfx90a_op_TBUFFER_STORE_FORMAT_XY,"TBUFFER_STORE_FORMAT_XY"} ,//5 + {amdgpu_gfx90a_op_TBUFFER_STORE_FORMAT_XYZ,"TBUFFER_STORE_FORMAT_XYZ"} ,//6 + {amdgpu_gfx90a_op_TBUFFER_STORE_FORMAT_XYZW,"TBUFFER_STORE_FORMAT_XYZW"} ,//7 + {amdgpu_gfx90a_op_TBUFFER_LOAD_FORMAT_D16_X,"TBUFFER_LOAD_FORMAT_D16_X"} ,//8 + {amdgpu_gfx90a_op_TBUFFER_LOAD_FORMAT_D16_XY,"TBUFFER_LOAD_FORMAT_D16_XY"} ,//9 + {amdgpu_gfx90a_op_TBUFFER_LOAD_FORMAT_D16_XYZ,"TBUFFER_LOAD_FORMAT_D16_XYZ"} ,//10 + {amdgpu_gfx90a_op_TBUFFER_LOAD_FORMAT_D16_XYZW,"TBUFFER_LOAD_FORMAT_D16_XYZW"} ,//11 + {amdgpu_gfx90a_op_TBUFFER_STORE_FORMAT_D16_X,"TBUFFER_STORE_FORMAT_D16_X"} ,//12 + {amdgpu_gfx90a_op_TBUFFER_STORE_FORMAT_D16_XY,"TBUFFER_STORE_FORMAT_D16_XY"} ,//13 + {amdgpu_gfx90a_op_TBUFFER_STORE_FORMAT_D16_XYZ,"TBUFFER_STORE_FORMAT_D16_XYZ"} ,//14 + {amdgpu_gfx90a_op_TBUFFER_STORE_FORMAT_D16_XYZW,"TBUFFER_STORE_FORMAT_D16_XYZW"} ,//15 + }; // end ENC_MTBUF_insn_table + const amdgpu_gfx90a_insn_entry ENC_MUBUF_insn_table [109] = + { + {amdgpu_gfx90a_op_BUFFER_LOAD_FORMAT_X,"BUFFER_LOAD_FORMAT_X"} ,//0 + {amdgpu_gfx90a_op_BUFFER_LOAD_FORMAT_XY,"BUFFER_LOAD_FORMAT_XY"} ,//1 + {amdgpu_gfx90a_op_BUFFER_LOAD_FORMAT_XYZ,"BUFFER_LOAD_FORMAT_XYZ"} ,//2 + {amdgpu_gfx90a_op_BUFFER_LOAD_FORMAT_XYZW,"BUFFER_LOAD_FORMAT_XYZW"} ,//3 + {amdgpu_gfx90a_op_BUFFER_STORE_FORMAT_X,"BUFFER_STORE_FORMAT_X"} ,//4 + {amdgpu_gfx90a_op_BUFFER_STORE_FORMAT_XY,"BUFFER_STORE_FORMAT_XY"} ,//5 + {amdgpu_gfx90a_op_BUFFER_STORE_FORMAT_XYZ,"BUFFER_STORE_FORMAT_XYZ"} ,//6 + {amdgpu_gfx90a_op_BUFFER_STORE_FORMAT_XYZW,"BUFFER_STORE_FORMAT_XYZW"} ,//7 + {amdgpu_gfx90a_op_BUFFER_LOAD_FORMAT_D16_X,"BUFFER_LOAD_FORMAT_D16_X"} ,//8 + {amdgpu_gfx90a_op_BUFFER_LOAD_FORMAT_D16_XY,"BUFFER_LOAD_FORMAT_D16_XY"} ,//9 + {amdgpu_gfx90a_op_BUFFER_LOAD_FORMAT_D16_XYZ,"BUFFER_LOAD_FORMAT_D16_XYZ"} ,//10 + {amdgpu_gfx90a_op_BUFFER_LOAD_FORMAT_D16_XYZW,"BUFFER_LOAD_FORMAT_D16_XYZW"} ,//11 + {amdgpu_gfx90a_op_BUFFER_STORE_FORMAT_D16_X,"BUFFER_STORE_FORMAT_D16_X"} ,//12 + {amdgpu_gfx90a_op_BUFFER_STORE_FORMAT_D16_XY,"BUFFER_STORE_FORMAT_D16_XY"} ,//13 + {amdgpu_gfx90a_op_BUFFER_STORE_FORMAT_D16_XYZ,"BUFFER_STORE_FORMAT_D16_XYZ"} ,//14 + {amdgpu_gfx90a_op_BUFFER_STORE_FORMAT_D16_XYZW,"BUFFER_STORE_FORMAT_D16_XYZW"} ,//15 + {amdgpu_gfx90a_op_BUFFER_LOAD_UBYTE,"BUFFER_LOAD_UBYTE"} ,//16 + {amdgpu_gfx90a_op_BUFFER_LOAD_SBYTE,"BUFFER_LOAD_SBYTE"} ,//17 + {amdgpu_gfx90a_op_BUFFER_LOAD_USHORT,"BUFFER_LOAD_USHORT"} ,//18 + {amdgpu_gfx90a_op_BUFFER_LOAD_SSHORT,"BUFFER_LOAD_SSHORT"} ,//19 + {amdgpu_gfx90a_op_BUFFER_LOAD_DWORD,"BUFFER_LOAD_DWORD"} ,//20 + {amdgpu_gfx90a_op_BUFFER_LOAD_DWORDX2,"BUFFER_LOAD_DWORDX2"} ,//21 + {amdgpu_gfx90a_op_BUFFER_LOAD_DWORDX3,"BUFFER_LOAD_DWORDX3"} ,//22 + {amdgpu_gfx90a_op_BUFFER_LOAD_DWORDX4,"BUFFER_LOAD_DWORDX4"} ,//23 + {amdgpu_gfx90a_op_BUFFER_STORE_BYTE,"BUFFER_STORE_BYTE"} ,//24 + {amdgpu_gfx90a_op_BUFFER_STORE_BYTE_D16_HI,"BUFFER_STORE_BYTE_D16_HI"} ,//25 + {amdgpu_gfx90a_op_BUFFER_STORE_SHORT,"BUFFER_STORE_SHORT"} ,//26 + {amdgpu_gfx90a_op_BUFFER_STORE_SHORT_D16_HI,"BUFFER_STORE_SHORT_D16_HI"} ,//27 + {amdgpu_gfx90a_op_BUFFER_STORE_DWORD,"BUFFER_STORE_DWORD"} ,//28 + {amdgpu_gfx90a_op_BUFFER_STORE_DWORDX2,"BUFFER_STORE_DWORDX2"} ,//29 + {amdgpu_gfx90a_op_BUFFER_STORE_DWORDX3,"BUFFER_STORE_DWORDX3"} ,//30 + {amdgpu_gfx90a_op_BUFFER_STORE_DWORDX4,"BUFFER_STORE_DWORDX4"} ,//31 + {amdgpu_gfx90a_op_BUFFER_LOAD_UBYTE_D16,"BUFFER_LOAD_UBYTE_D16"} ,//32 + {amdgpu_gfx90a_op_BUFFER_LOAD_UBYTE_D16_HI,"BUFFER_LOAD_UBYTE_D16_HI"} ,//33 + {amdgpu_gfx90a_op_BUFFER_LOAD_SBYTE_D16,"BUFFER_LOAD_SBYTE_D16"} ,//34 + {amdgpu_gfx90a_op_BUFFER_LOAD_SBYTE_D16_HI,"BUFFER_LOAD_SBYTE_D16_HI"} ,//35 + {amdgpu_gfx90a_op_BUFFER_LOAD_SHORT_D16,"BUFFER_LOAD_SHORT_D16"} ,//36 + {amdgpu_gfx90a_op_BUFFER_LOAD_SHORT_D16_HI,"BUFFER_LOAD_SHORT_D16_HI"} ,//37 + {amdgpu_gfx90a_op_BUFFER_LOAD_FORMAT_D16_HI_X,"BUFFER_LOAD_FORMAT_D16_HI_X"} ,//38 + {amdgpu_gfx90a_op_BUFFER_STORE_FORMAT_D16_HI_X,"BUFFER_STORE_FORMAT_D16_HI_X"} ,//39 + {amdgpu_gfx90a_op_BUFFER_WBL2,"BUFFER_WBL2"} ,//40 + {amdgpu_gfx90a_op_BUFFER_INVL2,"BUFFER_INVL2"} ,//41 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//42 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//43 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//44 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//45 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//46 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//47 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//48 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//49 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//50 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//51 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//52 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//53 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//54 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//55 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//56 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//57 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//58 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//59 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//60 + {amdgpu_gfx90a_op_BUFFER_STORE_LDS_DWORD,"BUFFER_STORE_LDS_DWORD"} ,//61 + {amdgpu_gfx90a_op_BUFFER_WBINVL1,"BUFFER_WBINVL1"} ,//62 + {amdgpu_gfx90a_op_BUFFER_WBINVL1_VOL,"BUFFER_WBINVL1_VOL"} ,//63 + {amdgpu_gfx90a_op_BUFFER_ATOMIC_SWAP,"BUFFER_ATOMIC_SWAP"} ,//64 + {amdgpu_gfx90a_op_BUFFER_ATOMIC_CMPSWAP,"BUFFER_ATOMIC_CMPSWAP"} ,//65 + {amdgpu_gfx90a_op_BUFFER_ATOMIC_ADD,"BUFFER_ATOMIC_ADD"} ,//66 + {amdgpu_gfx90a_op_BUFFER_ATOMIC_SUB,"BUFFER_ATOMIC_SUB"} ,//67 + {amdgpu_gfx90a_op_BUFFER_ATOMIC_SMIN,"BUFFER_ATOMIC_SMIN"} ,//68 + {amdgpu_gfx90a_op_BUFFER_ATOMIC_UMIN,"BUFFER_ATOMIC_UMIN"} ,//69 + {amdgpu_gfx90a_op_BUFFER_ATOMIC_SMAX,"BUFFER_ATOMIC_SMAX"} ,//70 + {amdgpu_gfx90a_op_BUFFER_ATOMIC_UMAX,"BUFFER_ATOMIC_UMAX"} ,//71 + {amdgpu_gfx90a_op_BUFFER_ATOMIC_AND,"BUFFER_ATOMIC_AND"} ,//72 + {amdgpu_gfx90a_op_BUFFER_ATOMIC_OR,"BUFFER_ATOMIC_OR"} ,//73 + {amdgpu_gfx90a_op_BUFFER_ATOMIC_XOR,"BUFFER_ATOMIC_XOR"} ,//74 + {amdgpu_gfx90a_op_BUFFER_ATOMIC_INC,"BUFFER_ATOMIC_INC"} ,//75 + {amdgpu_gfx90a_op_BUFFER_ATOMIC_DEC,"BUFFER_ATOMIC_DEC"} ,//76 + {amdgpu_gfx90a_op_BUFFER_ATOMIC_ADD_F32,"BUFFER_ATOMIC_ADD_F32"} ,//77 + {amdgpu_gfx90a_op_BUFFER_ATOMIC_PK_ADD_F16,"BUFFER_ATOMIC_PK_ADD_F16"} ,//78 + {amdgpu_gfx90a_op_BUFFER_ATOMIC_ADD_F64,"BUFFER_ATOMIC_ADD_F64"} ,//79 + {amdgpu_gfx90a_op_BUFFER_ATOMIC_MIN_F64,"BUFFER_ATOMIC_MIN_F64"} ,//80 + {amdgpu_gfx90a_op_BUFFER_ATOMIC_MAX_F64,"BUFFER_ATOMIC_MAX_F64"} ,//81 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//82 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//83 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//84 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//85 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//86 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//87 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//88 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//89 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//90 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//91 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//92 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//93 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//94 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//95 + {amdgpu_gfx90a_op_BUFFER_ATOMIC_SWAP_X2,"BUFFER_ATOMIC_SWAP_X2"} ,//96 + {amdgpu_gfx90a_op_BUFFER_ATOMIC_CMPSWAP_X2,"BUFFER_ATOMIC_CMPSWAP_X2"} ,//97 + {amdgpu_gfx90a_op_BUFFER_ATOMIC_ADD_X2,"BUFFER_ATOMIC_ADD_X2"} ,//98 + {amdgpu_gfx90a_op_BUFFER_ATOMIC_SUB_X2,"BUFFER_ATOMIC_SUB_X2"} ,//99 + {amdgpu_gfx90a_op_BUFFER_ATOMIC_SMIN_X2,"BUFFER_ATOMIC_SMIN_X2"} ,//100 + {amdgpu_gfx90a_op_BUFFER_ATOMIC_UMIN_X2,"BUFFER_ATOMIC_UMIN_X2"} ,//101 + {amdgpu_gfx90a_op_BUFFER_ATOMIC_SMAX_X2,"BUFFER_ATOMIC_SMAX_X2"} ,//102 + {amdgpu_gfx90a_op_BUFFER_ATOMIC_UMAX_X2,"BUFFER_ATOMIC_UMAX_X2"} ,//103 + {amdgpu_gfx90a_op_BUFFER_ATOMIC_AND_X2,"BUFFER_ATOMIC_AND_X2"} ,//104 + {amdgpu_gfx90a_op_BUFFER_ATOMIC_OR_X2,"BUFFER_ATOMIC_OR_X2"} ,//105 + {amdgpu_gfx90a_op_BUFFER_ATOMIC_XOR_X2,"BUFFER_ATOMIC_XOR_X2"} ,//106 + {amdgpu_gfx90a_op_BUFFER_ATOMIC_INC_X2,"BUFFER_ATOMIC_INC_X2"} ,//107 + {amdgpu_gfx90a_op_BUFFER_ATOMIC_DEC_X2,"BUFFER_ATOMIC_DEC_X2"} ,//108 + }; // end ENC_MUBUF_insn_table + const amdgpu_gfx90a_insn_entry ENC_SMEM_insn_table [173] = + { + {amdgpu_gfx90a_op_S_LOAD_DWORD,"S_LOAD_DWORD"} ,//0 + {amdgpu_gfx90a_op_S_LOAD_DWORDX2,"S_LOAD_DWORDX2"} ,//1 + {amdgpu_gfx90a_op_S_LOAD_DWORDX4,"S_LOAD_DWORDX4"} ,//2 + {amdgpu_gfx90a_op_S_LOAD_DWORDX8,"S_LOAD_DWORDX8"} ,//3 + {amdgpu_gfx90a_op_S_LOAD_DWORDX16,"S_LOAD_DWORDX16"} ,//4 + {amdgpu_gfx90a_op_S_SCRATCH_LOAD_DWORD,"S_SCRATCH_LOAD_DWORD"} ,//5 + {amdgpu_gfx90a_op_S_SCRATCH_LOAD_DWORDX2,"S_SCRATCH_LOAD_DWORDX2"} ,//6 + {amdgpu_gfx90a_op_S_SCRATCH_LOAD_DWORDX4,"S_SCRATCH_LOAD_DWORDX4"} ,//7 + {amdgpu_gfx90a_op_S_BUFFER_LOAD_DWORD,"S_BUFFER_LOAD_DWORD"} ,//8 + {amdgpu_gfx90a_op_S_BUFFER_LOAD_DWORDX2,"S_BUFFER_LOAD_DWORDX2"} ,//9 + {amdgpu_gfx90a_op_S_BUFFER_LOAD_DWORDX4,"S_BUFFER_LOAD_DWORDX4"} ,//10 + {amdgpu_gfx90a_op_S_BUFFER_LOAD_DWORDX8,"S_BUFFER_LOAD_DWORDX8"} ,//11 + {amdgpu_gfx90a_op_S_BUFFER_LOAD_DWORDX16,"S_BUFFER_LOAD_DWORDX16"} ,//12 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//13 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//14 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//15 + {amdgpu_gfx90a_op_S_STORE_DWORD,"S_STORE_DWORD"} ,//16 + {amdgpu_gfx90a_op_S_STORE_DWORDX2,"S_STORE_DWORDX2"} ,//17 + {amdgpu_gfx90a_op_S_STORE_DWORDX4,"S_STORE_DWORDX4"} ,//18 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//19 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//20 + {amdgpu_gfx90a_op_S_SCRATCH_STORE_DWORD,"S_SCRATCH_STORE_DWORD"} ,//21 + {amdgpu_gfx90a_op_S_SCRATCH_STORE_DWORDX2,"S_SCRATCH_STORE_DWORDX2"} ,//22 + {amdgpu_gfx90a_op_S_SCRATCH_STORE_DWORDX4,"S_SCRATCH_STORE_DWORDX4"} ,//23 + {amdgpu_gfx90a_op_S_BUFFER_STORE_DWORD,"S_BUFFER_STORE_DWORD"} ,//24 + {amdgpu_gfx90a_op_S_BUFFER_STORE_DWORDX2,"S_BUFFER_STORE_DWORDX2"} ,//25 + {amdgpu_gfx90a_op_S_BUFFER_STORE_DWORDX4,"S_BUFFER_STORE_DWORDX4"} ,//26 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//27 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//28 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//29 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//30 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//31 + {amdgpu_gfx90a_op_S_DCACHE_INV,"S_DCACHE_INV"} ,//32 + {amdgpu_gfx90a_op_S_DCACHE_WB,"S_DCACHE_WB"} ,//33 + {amdgpu_gfx90a_op_S_DCACHE_INV_VOL,"S_DCACHE_INV_VOL"} ,//34 + {amdgpu_gfx90a_op_S_DCACHE_WB_VOL,"S_DCACHE_WB_VOL"} ,//35 + {amdgpu_gfx90a_op_S_MEMTIME,"S_MEMTIME"} ,//36 + {amdgpu_gfx90a_op_S_MEMREALTIME,"S_MEMREALTIME"} ,//37 + {amdgpu_gfx90a_op_S_ATC_PROBE,"S_ATC_PROBE"} ,//38 + {amdgpu_gfx90a_op_S_ATC_PROBE_BUFFER,"S_ATC_PROBE_BUFFER"} ,//39 + {amdgpu_gfx90a_op_S_DCACHE_DISCARD,"S_DCACHE_DISCARD"} ,//40 + {amdgpu_gfx90a_op_S_DCACHE_DISCARD_X2,"S_DCACHE_DISCARD_X2"} ,//41 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//42 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//43 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//44 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//45 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//46 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//47 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//48 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//49 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//50 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//51 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//52 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//53 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//54 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//55 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//56 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//57 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//58 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//59 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//60 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//61 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//62 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//63 + {amdgpu_gfx90a_op_S_BUFFER_ATOMIC_SWAP,"S_BUFFER_ATOMIC_SWAP"} ,//64 + {amdgpu_gfx90a_op_S_BUFFER_ATOMIC_CMPSWAP,"S_BUFFER_ATOMIC_CMPSWAP"} ,//65 + {amdgpu_gfx90a_op_S_BUFFER_ATOMIC_ADD,"S_BUFFER_ATOMIC_ADD"} ,//66 + {amdgpu_gfx90a_op_S_BUFFER_ATOMIC_SUB,"S_BUFFER_ATOMIC_SUB"} ,//67 + {amdgpu_gfx90a_op_S_BUFFER_ATOMIC_SMIN,"S_BUFFER_ATOMIC_SMIN"} ,//68 + {amdgpu_gfx90a_op_S_BUFFER_ATOMIC_UMIN,"S_BUFFER_ATOMIC_UMIN"} ,//69 + {amdgpu_gfx90a_op_S_BUFFER_ATOMIC_SMAX,"S_BUFFER_ATOMIC_SMAX"} ,//70 + {amdgpu_gfx90a_op_S_BUFFER_ATOMIC_UMAX,"S_BUFFER_ATOMIC_UMAX"} ,//71 + {amdgpu_gfx90a_op_S_BUFFER_ATOMIC_AND,"S_BUFFER_ATOMIC_AND"} ,//72 + {amdgpu_gfx90a_op_S_BUFFER_ATOMIC_OR,"S_BUFFER_ATOMIC_OR"} ,//73 + {amdgpu_gfx90a_op_S_BUFFER_ATOMIC_XOR,"S_BUFFER_ATOMIC_XOR"} ,//74 + {amdgpu_gfx90a_op_S_BUFFER_ATOMIC_INC,"S_BUFFER_ATOMIC_INC"} ,//75 + {amdgpu_gfx90a_op_S_BUFFER_ATOMIC_DEC,"S_BUFFER_ATOMIC_DEC"} ,//76 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//77 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//78 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//79 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//80 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//81 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//82 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//83 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//84 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//85 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//86 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//87 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//88 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//89 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//90 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//91 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//92 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//93 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//94 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//95 + {amdgpu_gfx90a_op_S_BUFFER_ATOMIC_SWAP_X2,"S_BUFFER_ATOMIC_SWAP_X2"} ,//96 + {amdgpu_gfx90a_op_S_BUFFER_ATOMIC_CMPSWAP_X2,"S_BUFFER_ATOMIC_CMPSWAP_X2"} ,//97 + {amdgpu_gfx90a_op_S_BUFFER_ATOMIC_ADD_X2,"S_BUFFER_ATOMIC_ADD_X2"} ,//98 + {amdgpu_gfx90a_op_S_BUFFER_ATOMIC_SUB_X2,"S_BUFFER_ATOMIC_SUB_X2"} ,//99 + {amdgpu_gfx90a_op_S_BUFFER_ATOMIC_SMIN_X2,"S_BUFFER_ATOMIC_SMIN_X2"} ,//100 + {amdgpu_gfx90a_op_S_BUFFER_ATOMIC_UMIN_X2,"S_BUFFER_ATOMIC_UMIN_X2"} ,//101 + {amdgpu_gfx90a_op_S_BUFFER_ATOMIC_SMAX_X2,"S_BUFFER_ATOMIC_SMAX_X2"} ,//102 + {amdgpu_gfx90a_op_S_BUFFER_ATOMIC_UMAX_X2,"S_BUFFER_ATOMIC_UMAX_X2"} ,//103 + {amdgpu_gfx90a_op_S_BUFFER_ATOMIC_AND_X2,"S_BUFFER_ATOMIC_AND_X2"} ,//104 + {amdgpu_gfx90a_op_S_BUFFER_ATOMIC_OR_X2,"S_BUFFER_ATOMIC_OR_X2"} ,//105 + {amdgpu_gfx90a_op_S_BUFFER_ATOMIC_XOR_X2,"S_BUFFER_ATOMIC_XOR_X2"} ,//106 + {amdgpu_gfx90a_op_S_BUFFER_ATOMIC_INC_X2,"S_BUFFER_ATOMIC_INC_X2"} ,//107 + {amdgpu_gfx90a_op_S_BUFFER_ATOMIC_DEC_X2,"S_BUFFER_ATOMIC_DEC_X2"} ,//108 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//109 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//110 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//111 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//112 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//113 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//114 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//115 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//116 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//117 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//118 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//119 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//120 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//121 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//122 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//123 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//124 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//125 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//126 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//127 + {amdgpu_gfx90a_op_S_ATOMIC_SWAP,"S_ATOMIC_SWAP"} ,//128 + {amdgpu_gfx90a_op_S_ATOMIC_CMPSWAP,"S_ATOMIC_CMPSWAP"} ,//129 + {amdgpu_gfx90a_op_S_ATOMIC_ADD,"S_ATOMIC_ADD"} ,//130 + {amdgpu_gfx90a_op_S_ATOMIC_SUB,"S_ATOMIC_SUB"} ,//131 + {amdgpu_gfx90a_op_S_ATOMIC_SMIN,"S_ATOMIC_SMIN"} ,//132 + {amdgpu_gfx90a_op_S_ATOMIC_UMIN,"S_ATOMIC_UMIN"} ,//133 + {amdgpu_gfx90a_op_S_ATOMIC_SMAX,"S_ATOMIC_SMAX"} ,//134 + {amdgpu_gfx90a_op_S_ATOMIC_UMAX,"S_ATOMIC_UMAX"} ,//135 + {amdgpu_gfx90a_op_S_ATOMIC_AND,"S_ATOMIC_AND"} ,//136 + {amdgpu_gfx90a_op_S_ATOMIC_OR,"S_ATOMIC_OR"} ,//137 + {amdgpu_gfx90a_op_S_ATOMIC_XOR,"S_ATOMIC_XOR"} ,//138 + {amdgpu_gfx90a_op_S_ATOMIC_INC,"S_ATOMIC_INC"} ,//139 + {amdgpu_gfx90a_op_S_ATOMIC_DEC,"S_ATOMIC_DEC"} ,//140 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//141 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//142 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//143 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//144 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//145 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//146 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//147 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//148 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//149 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//150 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//151 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//152 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//153 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//154 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//155 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//156 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//157 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//158 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//159 + {amdgpu_gfx90a_op_S_ATOMIC_SWAP_X2,"S_ATOMIC_SWAP_X2"} ,//160 + {amdgpu_gfx90a_op_S_ATOMIC_CMPSWAP_X2,"S_ATOMIC_CMPSWAP_X2"} ,//161 + {amdgpu_gfx90a_op_S_ATOMIC_ADD_X2,"S_ATOMIC_ADD_X2"} ,//162 + {amdgpu_gfx90a_op_S_ATOMIC_SUB_X2,"S_ATOMIC_SUB_X2"} ,//163 + {amdgpu_gfx90a_op_S_ATOMIC_SMIN_X2,"S_ATOMIC_SMIN_X2"} ,//164 + {amdgpu_gfx90a_op_S_ATOMIC_UMIN_X2,"S_ATOMIC_UMIN_X2"} ,//165 + {amdgpu_gfx90a_op_S_ATOMIC_SMAX_X2,"S_ATOMIC_SMAX_X2"} ,//166 + {amdgpu_gfx90a_op_S_ATOMIC_UMAX_X2,"S_ATOMIC_UMAX_X2"} ,//167 + {amdgpu_gfx90a_op_S_ATOMIC_AND_X2,"S_ATOMIC_AND_X2"} ,//168 + {amdgpu_gfx90a_op_S_ATOMIC_OR_X2,"S_ATOMIC_OR_X2"} ,//169 + {amdgpu_gfx90a_op_S_ATOMIC_XOR_X2,"S_ATOMIC_XOR_X2"} ,//170 + {amdgpu_gfx90a_op_S_ATOMIC_INC_X2,"S_ATOMIC_INC_X2"} ,//171 + {amdgpu_gfx90a_op_S_ATOMIC_DEC_X2,"S_ATOMIC_DEC_X2"} ,//172 + }; // end ENC_SMEM_insn_table + const amdgpu_gfx90a_insn_entry ENC_SOP1_insn_table [56] = + { + {amdgpu_gfx90a_op_S_MOV_B32,"S_MOV_B32"} ,//0 + {amdgpu_gfx90a_op_S_MOV_B64,"S_MOV_B64"} ,//1 + {amdgpu_gfx90a_op_S_CMOV_B32,"S_CMOV_B32"} ,//2 + {amdgpu_gfx90a_op_S_CMOV_B64,"S_CMOV_B64"} ,//3 + {amdgpu_gfx90a_op_S_NOT_B32,"S_NOT_B32"} ,//4 + {amdgpu_gfx90a_op_S_NOT_B64,"S_NOT_B64"} ,//5 + {amdgpu_gfx90a_op_S_WQM_B32,"S_WQM_B32"} ,//6 + {amdgpu_gfx90a_op_S_WQM_B64,"S_WQM_B64"} ,//7 + {amdgpu_gfx90a_op_S_BREV_B32,"S_BREV_B32"} ,//8 + {amdgpu_gfx90a_op_S_BREV_B64,"S_BREV_B64"} ,//9 + {amdgpu_gfx90a_op_S_BCNT0_I32_B32,"S_BCNT0_I32_B32"} ,//10 + {amdgpu_gfx90a_op_S_BCNT0_I32_B64,"S_BCNT0_I32_B64"} ,//11 + {amdgpu_gfx90a_op_S_BCNT1_I32_B32,"S_BCNT1_I32_B32"} ,//12 + {amdgpu_gfx90a_op_S_BCNT1_I32_B64,"S_BCNT1_I32_B64"} ,//13 + {amdgpu_gfx90a_op_S_FF0_I32_B32,"S_FF0_I32_B32"} ,//14 + {amdgpu_gfx90a_op_S_FF0_I32_B64,"S_FF0_I32_B64"} ,//15 + {amdgpu_gfx90a_op_S_FF1_I32_B32,"S_FF1_I32_B32"} ,//16 + {amdgpu_gfx90a_op_S_FF1_I32_B64,"S_FF1_I32_B64"} ,//17 + {amdgpu_gfx90a_op_S_FLBIT_I32_B32,"S_FLBIT_I32_B32"} ,//18 + {amdgpu_gfx90a_op_S_FLBIT_I32_B64,"S_FLBIT_I32_B64"} ,//19 + {amdgpu_gfx90a_op_S_FLBIT_I32,"S_FLBIT_I32"} ,//20 + {amdgpu_gfx90a_op_S_FLBIT_I32_I64,"S_FLBIT_I32_I64"} ,//21 + {amdgpu_gfx90a_op_S_SEXT_I32_I8,"S_SEXT_I32_I8"} ,//22 + {amdgpu_gfx90a_op_S_SEXT_I32_I16,"S_SEXT_I32_I16"} ,//23 + {amdgpu_gfx90a_op_S_BITSET0_B32,"S_BITSET0_B32"} ,//24 + {amdgpu_gfx90a_op_S_BITSET0_B64,"S_BITSET0_B64"} ,//25 + {amdgpu_gfx90a_op_S_BITSET1_B32,"S_BITSET1_B32"} ,//26 + {amdgpu_gfx90a_op_S_BITSET1_B64,"S_BITSET1_B64"} ,//27 + {amdgpu_gfx90a_op_S_GETPC_B64,"S_GETPC_B64"} ,//28 + {amdgpu_gfx90a_op_S_SETPC_B64,"S_SETPC_B64"} ,//29 + {amdgpu_gfx90a_op_S_SWAPPC_B64,"S_SWAPPC_B64"} ,//30 + {amdgpu_gfx90a_op_S_RFE_B64,"S_RFE_B64"} ,//31 + {amdgpu_gfx90a_op_S_AND_SAVEEXEC_B64,"S_AND_SAVEEXEC_B64"} ,//32 + {amdgpu_gfx90a_op_S_OR_SAVEEXEC_B64,"S_OR_SAVEEXEC_B64"} ,//33 + {amdgpu_gfx90a_op_S_XOR_SAVEEXEC_B64,"S_XOR_SAVEEXEC_B64"} ,//34 + {amdgpu_gfx90a_op_S_ANDN2_SAVEEXEC_B64,"S_ANDN2_SAVEEXEC_B64"} ,//35 + {amdgpu_gfx90a_op_S_ORN2_SAVEEXEC_B64,"S_ORN2_SAVEEXEC_B64"} ,//36 + {amdgpu_gfx90a_op_S_NAND_SAVEEXEC_B64,"S_NAND_SAVEEXEC_B64"} ,//37 + {amdgpu_gfx90a_op_S_NOR_SAVEEXEC_B64,"S_NOR_SAVEEXEC_B64"} ,//38 + {amdgpu_gfx90a_op_S_XNOR_SAVEEXEC_B64,"S_XNOR_SAVEEXEC_B64"} ,//39 + {amdgpu_gfx90a_op_S_QUADMASK_B32,"S_QUADMASK_B32"} ,//40 + {amdgpu_gfx90a_op_S_QUADMASK_B64,"S_QUADMASK_B64"} ,//41 + {amdgpu_gfx90a_op_S_MOVRELS_B32,"S_MOVRELS_B32"} ,//42 + {amdgpu_gfx90a_op_S_MOVRELS_B64,"S_MOVRELS_B64"} ,//43 + {amdgpu_gfx90a_op_S_MOVRELD_B32,"S_MOVRELD_B32"} ,//44 + {amdgpu_gfx90a_op_S_MOVRELD_B64,"S_MOVRELD_B64"} ,//45 + {amdgpu_gfx90a_op_S_CBRANCH_JOIN,"S_CBRANCH_JOIN"} ,//46 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//47 + {amdgpu_gfx90a_op_S_ABS_I32,"S_ABS_I32"} ,//48 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//49 + {amdgpu_gfx90a_op_S_SET_GPR_IDX_IDX,"S_SET_GPR_IDX_IDX"} ,//50 + {amdgpu_gfx90a_op_S_ANDN1_SAVEEXEC_B64,"S_ANDN1_SAVEEXEC_B64"} ,//51 + {amdgpu_gfx90a_op_S_ORN1_SAVEEXEC_B64,"S_ORN1_SAVEEXEC_B64"} ,//52 + {amdgpu_gfx90a_op_S_ANDN1_WREXEC_B64,"S_ANDN1_WREXEC_B64"} ,//53 + {amdgpu_gfx90a_op_S_ANDN2_WREXEC_B64,"S_ANDN2_WREXEC_B64"} ,//54 + {amdgpu_gfx90a_op_S_BITREPLICATE_B64_B32,"S_BITREPLICATE_B64_B32"} ,//55 + }; // end ENC_SOP1_insn_table + const amdgpu_gfx90a_insn_entry ENC_SOP2_insn_table [53] = + { + {amdgpu_gfx90a_op_S_ADD_U32,"S_ADD_U32"} ,//0 + {amdgpu_gfx90a_op_S_SUB_U32,"S_SUB_U32"} ,//1 + {amdgpu_gfx90a_op_S_ADD_I32,"S_ADD_I32"} ,//2 + {amdgpu_gfx90a_op_S_SUB_I32,"S_SUB_I32"} ,//3 + {amdgpu_gfx90a_op_S_ADDC_U32,"S_ADDC_U32"} ,//4 + {amdgpu_gfx90a_op_S_SUBB_U32,"S_SUBB_U32"} ,//5 + {amdgpu_gfx90a_op_S_MIN_I32,"S_MIN_I32"} ,//6 + {amdgpu_gfx90a_op_S_MIN_U32,"S_MIN_U32"} ,//7 + {amdgpu_gfx90a_op_S_MAX_I32,"S_MAX_I32"} ,//8 + {amdgpu_gfx90a_op_S_MAX_U32,"S_MAX_U32"} ,//9 + {amdgpu_gfx90a_op_S_CSELECT_B32,"S_CSELECT_B32"} ,//10 + {amdgpu_gfx90a_op_S_CSELECT_B64,"S_CSELECT_B64"} ,//11 + {amdgpu_gfx90a_op_S_AND_B32,"S_AND_B32"} ,//12 + {amdgpu_gfx90a_op_S_AND_B64,"S_AND_B64"} ,//13 + {amdgpu_gfx90a_op_S_OR_B32,"S_OR_B32"} ,//14 + {amdgpu_gfx90a_op_S_OR_B64,"S_OR_B64"} ,//15 + {amdgpu_gfx90a_op_S_XOR_B32,"S_XOR_B32"} ,//16 + {amdgpu_gfx90a_op_S_XOR_B64,"S_XOR_B64"} ,//17 + {amdgpu_gfx90a_op_S_ANDN2_B32,"S_ANDN2_B32"} ,//18 + {amdgpu_gfx90a_op_S_ANDN2_B64,"S_ANDN2_B64"} ,//19 + {amdgpu_gfx90a_op_S_ORN2_B32,"S_ORN2_B32"} ,//20 + {amdgpu_gfx90a_op_S_ORN2_B64,"S_ORN2_B64"} ,//21 + {amdgpu_gfx90a_op_S_NAND_B32,"S_NAND_B32"} ,//22 + {amdgpu_gfx90a_op_S_NAND_B64,"S_NAND_B64"} ,//23 + {amdgpu_gfx90a_op_S_NOR_B32,"S_NOR_B32"} ,//24 + {amdgpu_gfx90a_op_S_NOR_B64,"S_NOR_B64"} ,//25 + {amdgpu_gfx90a_op_S_XNOR_B32,"S_XNOR_B32"} ,//26 + {amdgpu_gfx90a_op_S_XNOR_B64,"S_XNOR_B64"} ,//27 + {amdgpu_gfx90a_op_S_LSHL_B32,"S_LSHL_B32"} ,//28 + {amdgpu_gfx90a_op_S_LSHL_B64,"S_LSHL_B64"} ,//29 + {amdgpu_gfx90a_op_S_LSHR_B32,"S_LSHR_B32"} ,//30 + {amdgpu_gfx90a_op_S_LSHR_B64,"S_LSHR_B64"} ,//31 + {amdgpu_gfx90a_op_S_ASHR_I32,"S_ASHR_I32"} ,//32 + {amdgpu_gfx90a_op_S_ASHR_I64,"S_ASHR_I64"} ,//33 + {amdgpu_gfx90a_op_S_BFM_B32,"S_BFM_B32"} ,//34 + {amdgpu_gfx90a_op_S_BFM_B64,"S_BFM_B64"} ,//35 + {amdgpu_gfx90a_op_S_MUL_I32,"S_MUL_I32"} ,//36 + {amdgpu_gfx90a_op_S_BFE_U32,"S_BFE_U32"} ,//37 + {amdgpu_gfx90a_op_S_BFE_I32,"S_BFE_I32"} ,//38 + {amdgpu_gfx90a_op_S_BFE_U64,"S_BFE_U64"} ,//39 + {amdgpu_gfx90a_op_S_BFE_I64,"S_BFE_I64"} ,//40 + {amdgpu_gfx90a_op_S_CBRANCH_G_FORK,"S_CBRANCH_G_FORK"} ,//41 + {amdgpu_gfx90a_op_S_ABSDIFF_I32,"S_ABSDIFF_I32"} ,//42 + {amdgpu_gfx90a_op_S_RFE_RESTORE_B64,"S_RFE_RESTORE_B64"} ,//43 + {amdgpu_gfx90a_op_S_MUL_HI_U32,"S_MUL_HI_U32"} ,//44 + {amdgpu_gfx90a_op_S_MUL_HI_I32,"S_MUL_HI_I32"} ,//45 + {amdgpu_gfx90a_op_S_LSHL1_ADD_U32,"S_LSHL1_ADD_U32"} ,//46 + {amdgpu_gfx90a_op_S_LSHL2_ADD_U32,"S_LSHL2_ADD_U32"} ,//47 + {amdgpu_gfx90a_op_S_LSHL3_ADD_U32,"S_LSHL3_ADD_U32"} ,//48 + {amdgpu_gfx90a_op_S_LSHL4_ADD_U32,"S_LSHL4_ADD_U32"} ,//49 + {amdgpu_gfx90a_op_S_PACK_LL_B32_B16,"S_PACK_LL_B32_B16"} ,//50 + {amdgpu_gfx90a_op_S_PACK_LH_B32_B16,"S_PACK_LH_B32_B16"} ,//51 + {amdgpu_gfx90a_op_S_PACK_HH_B32_B16,"S_PACK_HH_B32_B16"} ,//52 + }; // end ENC_SOP2_insn_table + const amdgpu_gfx90a_insn_entry ENC_SOPC_insn_table [20] = + { + {amdgpu_gfx90a_op_S_CMP_EQ_I32,"S_CMP_EQ_I32"} ,//0 + {amdgpu_gfx90a_op_S_CMP_LG_I32,"S_CMP_LG_I32"} ,//1 + {amdgpu_gfx90a_op_S_CMP_GT_I32,"S_CMP_GT_I32"} ,//2 + {amdgpu_gfx90a_op_S_CMP_GE_I32,"S_CMP_GE_I32"} ,//3 + {amdgpu_gfx90a_op_S_CMP_LT_I32,"S_CMP_LT_I32"} ,//4 + {amdgpu_gfx90a_op_S_CMP_LE_I32,"S_CMP_LE_I32"} ,//5 + {amdgpu_gfx90a_op_S_CMP_EQ_U32,"S_CMP_EQ_U32"} ,//6 + {amdgpu_gfx90a_op_S_CMP_LG_U32,"S_CMP_LG_U32"} ,//7 + {amdgpu_gfx90a_op_S_CMP_GT_U32,"S_CMP_GT_U32"} ,//8 + {amdgpu_gfx90a_op_S_CMP_GE_U32,"S_CMP_GE_U32"} ,//9 + {amdgpu_gfx90a_op_S_CMP_LT_U32,"S_CMP_LT_U32"} ,//10 + {amdgpu_gfx90a_op_S_CMP_LE_U32,"S_CMP_LE_U32"} ,//11 + {amdgpu_gfx90a_op_S_BITCMP0_B32,"S_BITCMP0_B32"} ,//12 + {amdgpu_gfx90a_op_S_BITCMP1_B32,"S_BITCMP1_B32"} ,//13 + {amdgpu_gfx90a_op_S_BITCMP0_B64,"S_BITCMP0_B64"} ,//14 + {amdgpu_gfx90a_op_S_BITCMP1_B64,"S_BITCMP1_B64"} ,//15 + {amdgpu_gfx90a_op_S_SETVSKIP,"S_SETVSKIP"} ,//16 + {amdgpu_gfx90a_op_S_SET_GPR_IDX_ON,"S_SET_GPR_IDX_ON"} ,//17 + {amdgpu_gfx90a_op_S_CMP_EQ_U64,"S_CMP_EQ_U64"} ,//18 + {amdgpu_gfx90a_op_S_CMP_LG_U64,"S_CMP_LG_U64"} ,//19 + }; // end ENC_SOPC_insn_table + const amdgpu_gfx90a_insn_entry ENC_SOPK_insn_table [22] = + { + {amdgpu_gfx90a_op_S_MOVK_I32,"S_MOVK_I32"} ,//0 + {amdgpu_gfx90a_op_S_CMOVK_I32,"S_CMOVK_I32"} ,//1 + {amdgpu_gfx90a_op_S_CMPK_EQ_I32,"S_CMPK_EQ_I32"} ,//2 + {amdgpu_gfx90a_op_S_CMPK_LG_I32,"S_CMPK_LG_I32"} ,//3 + {amdgpu_gfx90a_op_S_CMPK_GT_I32,"S_CMPK_GT_I32"} ,//4 + {amdgpu_gfx90a_op_S_CMPK_GE_I32,"S_CMPK_GE_I32"} ,//5 + {amdgpu_gfx90a_op_S_CMPK_LT_I32,"S_CMPK_LT_I32"} ,//6 + {amdgpu_gfx90a_op_S_CMPK_LE_I32,"S_CMPK_LE_I32"} ,//7 + {amdgpu_gfx90a_op_S_CMPK_EQ_U32,"S_CMPK_EQ_U32"} ,//8 + {amdgpu_gfx90a_op_S_CMPK_LG_U32,"S_CMPK_LG_U32"} ,//9 + {amdgpu_gfx90a_op_S_CMPK_GT_U32,"S_CMPK_GT_U32"} ,//10 + {amdgpu_gfx90a_op_S_CMPK_GE_U32,"S_CMPK_GE_U32"} ,//11 + {amdgpu_gfx90a_op_S_CMPK_LT_U32,"S_CMPK_LT_U32"} ,//12 + {amdgpu_gfx90a_op_S_CMPK_LE_U32,"S_CMPK_LE_U32"} ,//13 + {amdgpu_gfx90a_op_S_ADDK_I32,"S_ADDK_I32"} ,//14 + {amdgpu_gfx90a_op_S_MULK_I32,"S_MULK_I32"} ,//15 + {amdgpu_gfx90a_op_S_CBRANCH_I_FORK,"S_CBRANCH_I_FORK"} ,//16 + {amdgpu_gfx90a_op_S_GETREG_B32,"S_GETREG_B32"} ,//17 + {amdgpu_gfx90a_op_S_SETREG_B32,"S_SETREG_B32"} ,//18 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//19 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//20 + {amdgpu_gfx90a_op_S_CALL_B64,"S_CALL_B64"} ,//21 + }; // end ENC_SOPK_insn_table + const amdgpu_gfx90a_insn_entry SOPK_INST_LITERAL__insn_table [21] = + { + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//0 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//1 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//2 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//3 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//4 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//5 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//6 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//7 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//8 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//9 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//10 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//11 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//12 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//13 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//14 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//15 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//16 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//17 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//18 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//19 + {amdgpu_gfx90a_op_S_SETREG_IMM32_B32,"S_SETREG_IMM32_B32"} ,//20 + }; // end SOPK_INST_LITERAL__insn_table + const amdgpu_gfx90a_insn_entry ENC_SOPP_insn_table [31] = + { + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//0 + {amdgpu_gfx90a_op_S_ENDPGM,"S_ENDPGM"} ,//1 + {amdgpu_gfx90a_op_S_BRANCH,"S_BRANCH"} ,//2 + {amdgpu_gfx90a_op_S_WAKEUP,"S_WAKEUP"} ,//3 + {amdgpu_gfx90a_op_S_CBRANCH_SCC0,"S_CBRANCH_SCC0"} ,//4 + {amdgpu_gfx90a_op_S_CBRANCH_SCC1,"S_CBRANCH_SCC1"} ,//5 + {amdgpu_gfx90a_op_S_CBRANCH_VCCZ,"S_CBRANCH_VCCZ"} ,//6 + {amdgpu_gfx90a_op_S_CBRANCH_VCCNZ,"S_CBRANCH_VCCNZ"} ,//7 + {amdgpu_gfx90a_op_S_CBRANCH_EXECZ,"S_CBRANCH_EXECZ"} ,//8 + {amdgpu_gfx90a_op_S_CBRANCH_EXECNZ,"S_CBRANCH_EXECNZ"} ,//9 + {amdgpu_gfx90a_op_S_BARRIER,"S_BARRIER"} ,//10 + {amdgpu_gfx90a_op_S_SETKILL,"S_SETKILL"} ,//11 + {amdgpu_gfx90a_op_S_WAITCNT,"S_WAITCNT"} ,//12 + {amdgpu_gfx90a_op_S_SETHALT,"S_SETHALT"} ,//13 + {amdgpu_gfx90a_op_S_SLEEP,"S_SLEEP"} ,//14 + {amdgpu_gfx90a_op_S_SETPRIO,"S_SETPRIO"} ,//15 + {amdgpu_gfx90a_op_S_SENDMSG,"S_SENDMSG"} ,//16 + {amdgpu_gfx90a_op_S_SENDMSGHALT,"S_SENDMSGHALT"} ,//17 + {amdgpu_gfx90a_op_S_TRAP,"S_TRAP"} ,//18 + {amdgpu_gfx90a_op_S_ICACHE_INV,"S_ICACHE_INV"} ,//19 + {amdgpu_gfx90a_op_S_INCPERFLEVEL,"S_INCPERFLEVEL"} ,//20 + {amdgpu_gfx90a_op_S_DECPERFLEVEL,"S_DECPERFLEVEL"} ,//21 + {amdgpu_gfx90a_op_S_TTRACEDATA,"S_TTRACEDATA"} ,//22 + {amdgpu_gfx90a_op_S_CBRANCH_CDBGSYS,"S_CBRANCH_CDBGSYS"} ,//23 + {amdgpu_gfx90a_op_S_CBRANCH_CDBGUSER,"S_CBRANCH_CDBGUSER"} ,//24 + {amdgpu_gfx90a_op_S_CBRANCH_CDBGSYS_OR_USER,"S_CBRANCH_CDBGSYS_OR_USER"} ,//25 + {amdgpu_gfx90a_op_S_CBRANCH_CDBGSYS_AND_USER,"S_CBRANCH_CDBGSYS_AND_USER"} ,//26 + {amdgpu_gfx90a_op_S_ENDPGM_SAVED,"S_ENDPGM_SAVED"} ,//27 + {amdgpu_gfx90a_op_S_SET_GPR_IDX_OFF,"S_SET_GPR_IDX_OFF"} ,//28 + {amdgpu_gfx90a_op_S_SET_GPR_IDX_MODE,"S_SET_GPR_IDX_MODE"} ,//29 + {amdgpu_gfx90a_op_S_ENDPGM_ORDERED_PS_DONE,"S_ENDPGM_ORDERED_PS_DONE"} ,//30 + }; // end ENC_SOPP_insn_table + const amdgpu_gfx90a_insn_entry ENC_VOP1_insn_table [83] = + { + {amdgpu_gfx90a_op_V_NOP,"V_NOP"} ,//0 + {amdgpu_gfx90a_op_V_MOV_B32,"V_MOV_B32"} ,//1 + {amdgpu_gfx90a_op_V_READFIRSTLANE_B32,"V_READFIRSTLANE_B32"} ,//2 + {amdgpu_gfx90a_op_V_CVT_I32_F64,"V_CVT_I32_F64"} ,//3 + {amdgpu_gfx90a_op_V_CVT_F64_I32,"V_CVT_F64_I32"} ,//4 + {amdgpu_gfx90a_op_V_CVT_F32_I32,"V_CVT_F32_I32"} ,//5 + {amdgpu_gfx90a_op_V_CVT_F32_U32,"V_CVT_F32_U32"} ,//6 + {amdgpu_gfx90a_op_V_CVT_U32_F32,"V_CVT_U32_F32"} ,//7 + {amdgpu_gfx90a_op_V_CVT_I32_F32,"V_CVT_I32_F32"} ,//8 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//9 + {amdgpu_gfx90a_op_V_CVT_F16_F32,"V_CVT_F16_F32"} ,//10 + {amdgpu_gfx90a_op_V_CVT_F32_F16,"V_CVT_F32_F16"} ,//11 + {amdgpu_gfx90a_op_V_CVT_RPI_I32_F32,"V_CVT_RPI_I32_F32"} ,//12 + {amdgpu_gfx90a_op_V_CVT_FLR_I32_F32,"V_CVT_FLR_I32_F32"} ,//13 + {amdgpu_gfx90a_op_V_CVT_OFF_F32_I4,"V_CVT_OFF_F32_I4"} ,//14 + {amdgpu_gfx90a_op_V_CVT_F32_F64,"V_CVT_F32_F64"} ,//15 + {amdgpu_gfx90a_op_V_CVT_F64_F32,"V_CVT_F64_F32"} ,//16 + {amdgpu_gfx90a_op_V_CVT_F32_UBYTE0,"V_CVT_F32_UBYTE0"} ,//17 + {amdgpu_gfx90a_op_V_CVT_F32_UBYTE1,"V_CVT_F32_UBYTE1"} ,//18 + {amdgpu_gfx90a_op_V_CVT_F32_UBYTE2,"V_CVT_F32_UBYTE2"} ,//19 + {amdgpu_gfx90a_op_V_CVT_F32_UBYTE3,"V_CVT_F32_UBYTE3"} ,//20 + {amdgpu_gfx90a_op_V_CVT_U32_F64,"V_CVT_U32_F64"} ,//21 + {amdgpu_gfx90a_op_V_CVT_F64_U32,"V_CVT_F64_U32"} ,//22 + {amdgpu_gfx90a_op_V_TRUNC_F64,"V_TRUNC_F64"} ,//23 + {amdgpu_gfx90a_op_V_CEIL_F64,"V_CEIL_F64"} ,//24 + {amdgpu_gfx90a_op_V_RNDNE_F64,"V_RNDNE_F64"} ,//25 + {amdgpu_gfx90a_op_V_FLOOR_F64,"V_FLOOR_F64"} ,//26 + {amdgpu_gfx90a_op_V_FRACT_F32,"V_FRACT_F32"} ,//27 + {amdgpu_gfx90a_op_V_TRUNC_F32,"V_TRUNC_F32"} ,//28 + {amdgpu_gfx90a_op_V_CEIL_F32,"V_CEIL_F32"} ,//29 + {amdgpu_gfx90a_op_V_RNDNE_F32,"V_RNDNE_F32"} ,//30 + {amdgpu_gfx90a_op_V_FLOOR_F32,"V_FLOOR_F32"} ,//31 + {amdgpu_gfx90a_op_V_EXP_F32,"V_EXP_F32"} ,//32 + {amdgpu_gfx90a_op_V_LOG_F32,"V_LOG_F32"} ,//33 + {amdgpu_gfx90a_op_V_RCP_F32,"V_RCP_F32"} ,//34 + {amdgpu_gfx90a_op_V_RCP_IFLAG_F32,"V_RCP_IFLAG_F32"} ,//35 + {amdgpu_gfx90a_op_V_RSQ_F32,"V_RSQ_F32"} ,//36 + {amdgpu_gfx90a_op_V_RCP_F64,"V_RCP_F64"} ,//37 + {amdgpu_gfx90a_op_V_RSQ_F64,"V_RSQ_F64"} ,//38 + {amdgpu_gfx90a_op_V_SQRT_F32,"V_SQRT_F32"} ,//39 + {amdgpu_gfx90a_op_V_SQRT_F64,"V_SQRT_F64"} ,//40 + {amdgpu_gfx90a_op_V_SIN_F32,"V_SIN_F32"} ,//41 + {amdgpu_gfx90a_op_V_COS_F32,"V_COS_F32"} ,//42 + {amdgpu_gfx90a_op_V_NOT_B32,"V_NOT_B32"} ,//43 + {amdgpu_gfx90a_op_V_BFREV_B32,"V_BFREV_B32"} ,//44 + {amdgpu_gfx90a_op_V_FFBH_U32,"V_FFBH_U32"} ,//45 + {amdgpu_gfx90a_op_V_FFBL_B32,"V_FFBL_B32"} ,//46 + {amdgpu_gfx90a_op_V_FFBH_I32,"V_FFBH_I32"} ,//47 + {amdgpu_gfx90a_op_V_FREXP_EXP_I32_F64,"V_FREXP_EXP_I32_F64"} ,//48 + {amdgpu_gfx90a_op_V_FREXP_MANT_F64,"V_FREXP_MANT_F64"} ,//49 + {amdgpu_gfx90a_op_V_FRACT_F64,"V_FRACT_F64"} ,//50 + {amdgpu_gfx90a_op_V_FREXP_EXP_I32_F32,"V_FREXP_EXP_I32_F32"} ,//51 + {amdgpu_gfx90a_op_V_FREXP_MANT_F32,"V_FREXP_MANT_F32"} ,//52 + {amdgpu_gfx90a_op_V_CLREXCP,"V_CLREXCP"} ,//53 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//54 + {amdgpu_gfx90a_op_V_SCREEN_PARTITION_4SE_B32,"V_SCREEN_PARTITION_4SE_B32"} ,//55 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//56 + {amdgpu_gfx90a_op_V_CVT_F16_U16,"V_CVT_F16_U16"} ,//57 + {amdgpu_gfx90a_op_V_CVT_F16_I16,"V_CVT_F16_I16"} ,//58 + {amdgpu_gfx90a_op_V_CVT_U16_F16,"V_CVT_U16_F16"} ,//59 + {amdgpu_gfx90a_op_V_CVT_I16_F16,"V_CVT_I16_F16"} ,//60 + {amdgpu_gfx90a_op_V_RCP_F16,"V_RCP_F16"} ,//61 + {amdgpu_gfx90a_op_V_SQRT_F16,"V_SQRT_F16"} ,//62 + {amdgpu_gfx90a_op_V_RSQ_F16,"V_RSQ_F16"} ,//63 + {amdgpu_gfx90a_op_V_LOG_F16,"V_LOG_F16"} ,//64 + {amdgpu_gfx90a_op_V_EXP_F16,"V_EXP_F16"} ,//65 + {amdgpu_gfx90a_op_V_FREXP_MANT_F16,"V_FREXP_MANT_F16"} ,//66 + {amdgpu_gfx90a_op_V_FREXP_EXP_I16_F16,"V_FREXP_EXP_I16_F16"} ,//67 + {amdgpu_gfx90a_op_V_FLOOR_F16,"V_FLOOR_F16"} ,//68 + {amdgpu_gfx90a_op_V_CEIL_F16,"V_CEIL_F16"} ,//69 + {amdgpu_gfx90a_op_V_TRUNC_F16,"V_TRUNC_F16"} ,//70 + {amdgpu_gfx90a_op_V_RNDNE_F16,"V_RNDNE_F16"} ,//71 + {amdgpu_gfx90a_op_V_FRACT_F16,"V_FRACT_F16"} ,//72 + {amdgpu_gfx90a_op_V_SIN_F16,"V_SIN_F16"} ,//73 + {amdgpu_gfx90a_op_V_COS_F16,"V_COS_F16"} ,//74 + {amdgpu_gfx90a_op_V_EXP_LEGACY_F32,"V_EXP_LEGACY_F32"} ,//75 + {amdgpu_gfx90a_op_V_LOG_LEGACY_F32,"V_LOG_LEGACY_F32"} ,//76 + {amdgpu_gfx90a_op_V_CVT_NORM_I16_F16,"V_CVT_NORM_I16_F16"} ,//77 + {amdgpu_gfx90a_op_V_CVT_NORM_U16_F16,"V_CVT_NORM_U16_F16"} ,//78 + {amdgpu_gfx90a_op_V_SAT_PK_U8_I16,"V_SAT_PK_U8_I16"} ,//79 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//80 + {amdgpu_gfx90a_op_V_SWAP_B32,"V_SWAP_B32"} ,//81 + {amdgpu_gfx90a_op_V_ACCVGPR_MOV_B32,"V_ACCVGPR_MOV_B32"} ,//82 + }; // end ENC_VOP1_insn_table + const amdgpu_gfx90a_insn_entry ENC_VOP3_insn_table [674] = + { + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//0 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//1 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//2 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//3 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//4 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//5 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//6 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//7 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//8 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//9 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//10 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//11 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//12 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//13 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//14 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//15 + {amdgpu_gfx90a_op_V_CMP_CLASS_F32,"V_CMP_CLASS_F32"} ,//16 + {amdgpu_gfx90a_op_V_CMPX_CLASS_F32,"V_CMPX_CLASS_F32"} ,//17 + {amdgpu_gfx90a_op_V_CMP_CLASS_F64,"V_CMP_CLASS_F64"} ,//18 + {amdgpu_gfx90a_op_V_CMPX_CLASS_F64,"V_CMPX_CLASS_F64"} ,//19 + {amdgpu_gfx90a_op_V_CMP_CLASS_F16,"V_CMP_CLASS_F16"} ,//20 + {amdgpu_gfx90a_op_V_CMPX_CLASS_F16,"V_CMPX_CLASS_F16"} ,//21 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//22 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//23 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//24 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//25 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//26 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//27 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//28 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//29 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//30 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//31 + {amdgpu_gfx90a_op_V_CMP_F_F16,"V_CMP_F_F16"} ,//32 + {amdgpu_gfx90a_op_V_CMP_LT_F16,"V_CMP_LT_F16"} ,//33 + {amdgpu_gfx90a_op_V_CMP_EQ_F16,"V_CMP_EQ_F16"} ,//34 + {amdgpu_gfx90a_op_V_CMP_LE_F16,"V_CMP_LE_F16"} ,//35 + {amdgpu_gfx90a_op_V_CMP_GT_F16,"V_CMP_GT_F16"} ,//36 + {amdgpu_gfx90a_op_V_CMP_LG_F16,"V_CMP_LG_F16"} ,//37 + {amdgpu_gfx90a_op_V_CMP_GE_F16,"V_CMP_GE_F16"} ,//38 + {amdgpu_gfx90a_op_V_CMP_O_F16,"V_CMP_O_F16"} ,//39 + {amdgpu_gfx90a_op_V_CMP_U_F16,"V_CMP_U_F16"} ,//40 + {amdgpu_gfx90a_op_V_CMP_NGE_F16,"V_CMP_NGE_F16"} ,//41 + {amdgpu_gfx90a_op_V_CMP_NLG_F16,"V_CMP_NLG_F16"} ,//42 + {amdgpu_gfx90a_op_V_CMP_NGT_F16,"V_CMP_NGT_F16"} ,//43 + {amdgpu_gfx90a_op_V_CMP_NLE_F16,"V_CMP_NLE_F16"} ,//44 + {amdgpu_gfx90a_op_V_CMP_NEQ_F16,"V_CMP_NEQ_F16"} ,//45 + {amdgpu_gfx90a_op_V_CMP_NLT_F16,"V_CMP_NLT_F16"} ,//46 + {amdgpu_gfx90a_op_V_CMP_TRU_F16,"V_CMP_TRU_F16"} ,//47 + {amdgpu_gfx90a_op_V_CMPX_F_F16,"V_CMPX_F_F16"} ,//48 + {amdgpu_gfx90a_op_V_CMPX_LT_F16,"V_CMPX_LT_F16"} ,//49 + {amdgpu_gfx90a_op_V_CMPX_EQ_F16,"V_CMPX_EQ_F16"} ,//50 + {amdgpu_gfx90a_op_V_CMPX_LE_F16,"V_CMPX_LE_F16"} ,//51 + {amdgpu_gfx90a_op_V_CMPX_GT_F16,"V_CMPX_GT_F16"} ,//52 + {amdgpu_gfx90a_op_V_CMPX_LG_F16,"V_CMPX_LG_F16"} ,//53 + {amdgpu_gfx90a_op_V_CMPX_GE_F16,"V_CMPX_GE_F16"} ,//54 + {amdgpu_gfx90a_op_V_CMPX_O_F16,"V_CMPX_O_F16"} ,//55 + {amdgpu_gfx90a_op_V_CMPX_U_F16,"V_CMPX_U_F16"} ,//56 + {amdgpu_gfx90a_op_V_CMPX_NGE_F16,"V_CMPX_NGE_F16"} ,//57 + {amdgpu_gfx90a_op_V_CMPX_NLG_F16,"V_CMPX_NLG_F16"} ,//58 + {amdgpu_gfx90a_op_V_CMPX_NGT_F16,"V_CMPX_NGT_F16"} ,//59 + {amdgpu_gfx90a_op_V_CMPX_NLE_F16,"V_CMPX_NLE_F16"} ,//60 + {amdgpu_gfx90a_op_V_CMPX_NEQ_F16,"V_CMPX_NEQ_F16"} ,//61 + {amdgpu_gfx90a_op_V_CMPX_NLT_F16,"V_CMPX_NLT_F16"} ,//62 + {amdgpu_gfx90a_op_V_CMPX_TRU_F16,"V_CMPX_TRU_F16"} ,//63 + {amdgpu_gfx90a_op_V_CMP_F_F32,"V_CMP_F_F32"} ,//64 + {amdgpu_gfx90a_op_V_CMP_LT_F32,"V_CMP_LT_F32"} ,//65 + {amdgpu_gfx90a_op_V_CMP_EQ_F32,"V_CMP_EQ_F32"} ,//66 + {amdgpu_gfx90a_op_V_CMP_LE_F32,"V_CMP_LE_F32"} ,//67 + {amdgpu_gfx90a_op_V_CMP_GT_F32,"V_CMP_GT_F32"} ,//68 + {amdgpu_gfx90a_op_V_CMP_LG_F32,"V_CMP_LG_F32"} ,//69 + {amdgpu_gfx90a_op_V_CMP_GE_F32,"V_CMP_GE_F32"} ,//70 + {amdgpu_gfx90a_op_V_CMP_O_F32,"V_CMP_O_F32"} ,//71 + {amdgpu_gfx90a_op_V_CMP_U_F32,"V_CMP_U_F32"} ,//72 + {amdgpu_gfx90a_op_V_CMP_NGE_F32,"V_CMP_NGE_F32"} ,//73 + {amdgpu_gfx90a_op_V_CMP_NLG_F32,"V_CMP_NLG_F32"} ,//74 + {amdgpu_gfx90a_op_V_CMP_NGT_F32,"V_CMP_NGT_F32"} ,//75 + {amdgpu_gfx90a_op_V_CMP_NLE_F32,"V_CMP_NLE_F32"} ,//76 + {amdgpu_gfx90a_op_V_CMP_NEQ_F32,"V_CMP_NEQ_F32"} ,//77 + {amdgpu_gfx90a_op_V_CMP_NLT_F32,"V_CMP_NLT_F32"} ,//78 + {amdgpu_gfx90a_op_V_CMP_TRU_F32,"V_CMP_TRU_F32"} ,//79 + {amdgpu_gfx90a_op_V_CMPX_F_F32,"V_CMPX_F_F32"} ,//80 + {amdgpu_gfx90a_op_V_CMPX_LT_F32,"V_CMPX_LT_F32"} ,//81 + {amdgpu_gfx90a_op_V_CMPX_EQ_F32,"V_CMPX_EQ_F32"} ,//82 + {amdgpu_gfx90a_op_V_CMPX_LE_F32,"V_CMPX_LE_F32"} ,//83 + {amdgpu_gfx90a_op_V_CMPX_GT_F32,"V_CMPX_GT_F32"} ,//84 + {amdgpu_gfx90a_op_V_CMPX_LG_F32,"V_CMPX_LG_F32"} ,//85 + {amdgpu_gfx90a_op_V_CMPX_GE_F32,"V_CMPX_GE_F32"} ,//86 + {amdgpu_gfx90a_op_V_CMPX_O_F32,"V_CMPX_O_F32"} ,//87 + {amdgpu_gfx90a_op_V_CMPX_U_F32,"V_CMPX_U_F32"} ,//88 + {amdgpu_gfx90a_op_V_CMPX_NGE_F32,"V_CMPX_NGE_F32"} ,//89 + {amdgpu_gfx90a_op_V_CMPX_NLG_F32,"V_CMPX_NLG_F32"} ,//90 + {amdgpu_gfx90a_op_V_CMPX_NGT_F32,"V_CMPX_NGT_F32"} ,//91 + {amdgpu_gfx90a_op_V_CMPX_NLE_F32,"V_CMPX_NLE_F32"} ,//92 + {amdgpu_gfx90a_op_V_CMPX_NEQ_F32,"V_CMPX_NEQ_F32"} ,//93 + {amdgpu_gfx90a_op_V_CMPX_NLT_F32,"V_CMPX_NLT_F32"} ,//94 + {amdgpu_gfx90a_op_V_CMPX_TRU_F32,"V_CMPX_TRU_F32"} ,//95 + {amdgpu_gfx90a_op_V_CMP_F_F64,"V_CMP_F_F64"} ,//96 + {amdgpu_gfx90a_op_V_CMP_LT_F64,"V_CMP_LT_F64"} ,//97 + {amdgpu_gfx90a_op_V_CMP_EQ_F64,"V_CMP_EQ_F64"} ,//98 + {amdgpu_gfx90a_op_V_CMP_LE_F64,"V_CMP_LE_F64"} ,//99 + {amdgpu_gfx90a_op_V_CMP_GT_F64,"V_CMP_GT_F64"} ,//100 + {amdgpu_gfx90a_op_V_CMP_LG_F64,"V_CMP_LG_F64"} ,//101 + {amdgpu_gfx90a_op_V_CMP_GE_F64,"V_CMP_GE_F64"} ,//102 + {amdgpu_gfx90a_op_V_CMP_O_F64,"V_CMP_O_F64"} ,//103 + {amdgpu_gfx90a_op_V_CMP_U_F64,"V_CMP_U_F64"} ,//104 + {amdgpu_gfx90a_op_V_CMP_NGE_F64,"V_CMP_NGE_F64"} ,//105 + {amdgpu_gfx90a_op_V_CMP_NLG_F64,"V_CMP_NLG_F64"} ,//106 + {amdgpu_gfx90a_op_V_CMP_NGT_F64,"V_CMP_NGT_F64"} ,//107 + {amdgpu_gfx90a_op_V_CMP_NLE_F64,"V_CMP_NLE_F64"} ,//108 + {amdgpu_gfx90a_op_V_CMP_NEQ_F64,"V_CMP_NEQ_F64"} ,//109 + {amdgpu_gfx90a_op_V_CMP_NLT_F64,"V_CMP_NLT_F64"} ,//110 + {amdgpu_gfx90a_op_V_CMP_TRU_F64,"V_CMP_TRU_F64"} ,//111 + {amdgpu_gfx90a_op_V_CMPX_F_F64,"V_CMPX_F_F64"} ,//112 + {amdgpu_gfx90a_op_V_CMPX_LT_F64,"V_CMPX_LT_F64"} ,//113 + {amdgpu_gfx90a_op_V_CMPX_EQ_F64,"V_CMPX_EQ_F64"} ,//114 + {amdgpu_gfx90a_op_V_CMPX_LE_F64,"V_CMPX_LE_F64"} ,//115 + {amdgpu_gfx90a_op_V_CMPX_GT_F64,"V_CMPX_GT_F64"} ,//116 + {amdgpu_gfx90a_op_V_CMPX_LG_F64,"V_CMPX_LG_F64"} ,//117 + {amdgpu_gfx90a_op_V_CMPX_GE_F64,"V_CMPX_GE_F64"} ,//118 + {amdgpu_gfx90a_op_V_CMPX_O_F64,"V_CMPX_O_F64"} ,//119 + {amdgpu_gfx90a_op_V_CMPX_U_F64,"V_CMPX_U_F64"} ,//120 + {amdgpu_gfx90a_op_V_CMPX_NGE_F64,"V_CMPX_NGE_F64"} ,//121 + {amdgpu_gfx90a_op_V_CMPX_NLG_F64,"V_CMPX_NLG_F64"} ,//122 + {amdgpu_gfx90a_op_V_CMPX_NGT_F64,"V_CMPX_NGT_F64"} ,//123 + {amdgpu_gfx90a_op_V_CMPX_NLE_F64,"V_CMPX_NLE_F64"} ,//124 + {amdgpu_gfx90a_op_V_CMPX_NEQ_F64,"V_CMPX_NEQ_F64"} ,//125 + {amdgpu_gfx90a_op_V_CMPX_NLT_F64,"V_CMPX_NLT_F64"} ,//126 + {amdgpu_gfx90a_op_V_CMPX_TRU_F64,"V_CMPX_TRU_F64"} ,//127 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//128 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//129 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//130 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//131 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//132 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//133 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//134 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//135 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//136 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//137 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//138 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//139 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//140 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//141 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//142 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//143 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//144 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//145 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//146 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//147 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//148 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//149 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//150 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//151 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//152 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//153 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//154 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//155 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//156 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//157 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//158 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//159 + {amdgpu_gfx90a_op_V_CMP_F_I16,"V_CMP_F_I16"} ,//160 + {amdgpu_gfx90a_op_V_CMP_LT_I16,"V_CMP_LT_I16"} ,//161 + {amdgpu_gfx90a_op_V_CMP_EQ_I16,"V_CMP_EQ_I16"} ,//162 + {amdgpu_gfx90a_op_V_CMP_LE_I16,"V_CMP_LE_I16"} ,//163 + {amdgpu_gfx90a_op_V_CMP_GT_I16,"V_CMP_GT_I16"} ,//164 + {amdgpu_gfx90a_op_V_CMP_NE_I16,"V_CMP_NE_I16"} ,//165 + {amdgpu_gfx90a_op_V_CMP_GE_I16,"V_CMP_GE_I16"} ,//166 + {amdgpu_gfx90a_op_V_CMP_T_I16,"V_CMP_T_I16"} ,//167 + {amdgpu_gfx90a_op_V_CMP_F_U16,"V_CMP_F_U16"} ,//168 + {amdgpu_gfx90a_op_V_CMP_LT_U16,"V_CMP_LT_U16"} ,//169 + {amdgpu_gfx90a_op_V_CMP_EQ_U16,"V_CMP_EQ_U16"} ,//170 + {amdgpu_gfx90a_op_V_CMP_LE_U16,"V_CMP_LE_U16"} ,//171 + {amdgpu_gfx90a_op_V_CMP_GT_U16,"V_CMP_GT_U16"} ,//172 + {amdgpu_gfx90a_op_V_CMP_NE_U16,"V_CMP_NE_U16"} ,//173 + {amdgpu_gfx90a_op_V_CMP_GE_U16,"V_CMP_GE_U16"} ,//174 + {amdgpu_gfx90a_op_V_CMP_T_U16,"V_CMP_T_U16"} ,//175 + {amdgpu_gfx90a_op_V_CMPX_F_I16,"V_CMPX_F_I16"} ,//176 + {amdgpu_gfx90a_op_V_CMPX_LT_I16,"V_CMPX_LT_I16"} ,//177 + {amdgpu_gfx90a_op_V_CMPX_EQ_I16,"V_CMPX_EQ_I16"} ,//178 + {amdgpu_gfx90a_op_V_CMPX_LE_I16,"V_CMPX_LE_I16"} ,//179 + {amdgpu_gfx90a_op_V_CMPX_GT_I16,"V_CMPX_GT_I16"} ,//180 + {amdgpu_gfx90a_op_V_CMPX_NE_I16,"V_CMPX_NE_I16"} ,//181 + {amdgpu_gfx90a_op_V_CMPX_GE_I16,"V_CMPX_GE_I16"} ,//182 + {amdgpu_gfx90a_op_V_CMPX_T_I16,"V_CMPX_T_I16"} ,//183 + {amdgpu_gfx90a_op_V_CMPX_F_U16,"V_CMPX_F_U16"} ,//184 + {amdgpu_gfx90a_op_V_CMPX_LT_U16,"V_CMPX_LT_U16"} ,//185 + {amdgpu_gfx90a_op_V_CMPX_EQ_U16,"V_CMPX_EQ_U16"} ,//186 + {amdgpu_gfx90a_op_V_CMPX_LE_U16,"V_CMPX_LE_U16"} ,//187 + {amdgpu_gfx90a_op_V_CMPX_GT_U16,"V_CMPX_GT_U16"} ,//188 + {amdgpu_gfx90a_op_V_CMPX_NE_U16,"V_CMPX_NE_U16"} ,//189 + {amdgpu_gfx90a_op_V_CMPX_GE_U16,"V_CMPX_GE_U16"} ,//190 + {amdgpu_gfx90a_op_V_CMPX_T_U16,"V_CMPX_T_U16"} ,//191 + {amdgpu_gfx90a_op_V_CMP_F_I32,"V_CMP_F_I32"} ,//192 + {amdgpu_gfx90a_op_V_CMP_LT_I32,"V_CMP_LT_I32"} ,//193 + {amdgpu_gfx90a_op_V_CMP_EQ_I32,"V_CMP_EQ_I32"} ,//194 + {amdgpu_gfx90a_op_V_CMP_LE_I32,"V_CMP_LE_I32"} ,//195 + {amdgpu_gfx90a_op_V_CMP_GT_I32,"V_CMP_GT_I32"} ,//196 + {amdgpu_gfx90a_op_V_CMP_NE_I32,"V_CMP_NE_I32"} ,//197 + {amdgpu_gfx90a_op_V_CMP_GE_I32,"V_CMP_GE_I32"} ,//198 + {amdgpu_gfx90a_op_V_CMP_T_I32,"V_CMP_T_I32"} ,//199 + {amdgpu_gfx90a_op_V_CMP_F_U32,"V_CMP_F_U32"} ,//200 + {amdgpu_gfx90a_op_V_CMP_LT_U32,"V_CMP_LT_U32"} ,//201 + {amdgpu_gfx90a_op_V_CMP_EQ_U32,"V_CMP_EQ_U32"} ,//202 + {amdgpu_gfx90a_op_V_CMP_LE_U32,"V_CMP_LE_U32"} ,//203 + {amdgpu_gfx90a_op_V_CMP_GT_U32,"V_CMP_GT_U32"} ,//204 + {amdgpu_gfx90a_op_V_CMP_NE_U32,"V_CMP_NE_U32"} ,//205 + {amdgpu_gfx90a_op_V_CMP_GE_U32,"V_CMP_GE_U32"} ,//206 + {amdgpu_gfx90a_op_V_CMP_T_U32,"V_CMP_T_U32"} ,//207 + {amdgpu_gfx90a_op_V_CMPX_F_I32,"V_CMPX_F_I32"} ,//208 + {amdgpu_gfx90a_op_V_CMPX_LT_I32,"V_CMPX_LT_I32"} ,//209 + {amdgpu_gfx90a_op_V_CMPX_EQ_I32,"V_CMPX_EQ_I32"} ,//210 + {amdgpu_gfx90a_op_V_CMPX_LE_I32,"V_CMPX_LE_I32"} ,//211 + {amdgpu_gfx90a_op_V_CMPX_GT_I32,"V_CMPX_GT_I32"} ,//212 + {amdgpu_gfx90a_op_V_CMPX_NE_I32,"V_CMPX_NE_I32"} ,//213 + {amdgpu_gfx90a_op_V_CMPX_GE_I32,"V_CMPX_GE_I32"} ,//214 + {amdgpu_gfx90a_op_V_CMPX_T_I32,"V_CMPX_T_I32"} ,//215 + {amdgpu_gfx90a_op_V_CMPX_F_U32,"V_CMPX_F_U32"} ,//216 + {amdgpu_gfx90a_op_V_CMPX_LT_U32,"V_CMPX_LT_U32"} ,//217 + {amdgpu_gfx90a_op_V_CMPX_EQ_U32,"V_CMPX_EQ_U32"} ,//218 + {amdgpu_gfx90a_op_V_CMPX_LE_U32,"V_CMPX_LE_U32"} ,//219 + {amdgpu_gfx90a_op_V_CMPX_GT_U32,"V_CMPX_GT_U32"} ,//220 + {amdgpu_gfx90a_op_V_CMPX_NE_U32,"V_CMPX_NE_U32"} ,//221 + {amdgpu_gfx90a_op_V_CMPX_GE_U32,"V_CMPX_GE_U32"} ,//222 + {amdgpu_gfx90a_op_V_CMPX_T_U32,"V_CMPX_T_U32"} ,//223 + {amdgpu_gfx90a_op_V_CMP_F_I64,"V_CMP_F_I64"} ,//224 + {amdgpu_gfx90a_op_V_CMP_LT_I64,"V_CMP_LT_I64"} ,//225 + {amdgpu_gfx90a_op_V_CMP_EQ_I64,"V_CMP_EQ_I64"} ,//226 + {amdgpu_gfx90a_op_V_CMP_LE_I64,"V_CMP_LE_I64"} ,//227 + {amdgpu_gfx90a_op_V_CMP_GT_I64,"V_CMP_GT_I64"} ,//228 + {amdgpu_gfx90a_op_V_CMP_NE_I64,"V_CMP_NE_I64"} ,//229 + {amdgpu_gfx90a_op_V_CMP_GE_I64,"V_CMP_GE_I64"} ,//230 + {amdgpu_gfx90a_op_V_CMP_T_I64,"V_CMP_T_I64"} ,//231 + {amdgpu_gfx90a_op_V_CMP_F_U64,"V_CMP_F_U64"} ,//232 + {amdgpu_gfx90a_op_V_CMP_LT_U64,"V_CMP_LT_U64"} ,//233 + {amdgpu_gfx90a_op_V_CMP_EQ_U64,"V_CMP_EQ_U64"} ,//234 + {amdgpu_gfx90a_op_V_CMP_LE_U64,"V_CMP_LE_U64"} ,//235 + {amdgpu_gfx90a_op_V_CMP_GT_U64,"V_CMP_GT_U64"} ,//236 + {amdgpu_gfx90a_op_V_CMP_NE_U64,"V_CMP_NE_U64"} ,//237 + {amdgpu_gfx90a_op_V_CMP_GE_U64,"V_CMP_GE_U64"} ,//238 + {amdgpu_gfx90a_op_V_CMP_T_U64,"V_CMP_T_U64"} ,//239 + {amdgpu_gfx90a_op_V_CMPX_F_I64,"V_CMPX_F_I64"} ,//240 + {amdgpu_gfx90a_op_V_CMPX_LT_I64,"V_CMPX_LT_I64"} ,//241 + {amdgpu_gfx90a_op_V_CMPX_EQ_I64,"V_CMPX_EQ_I64"} ,//242 + {amdgpu_gfx90a_op_V_CMPX_LE_I64,"V_CMPX_LE_I64"} ,//243 + {amdgpu_gfx90a_op_V_CMPX_GT_I64,"V_CMPX_GT_I64"} ,//244 + {amdgpu_gfx90a_op_V_CMPX_NE_I64,"V_CMPX_NE_I64"} ,//245 + {amdgpu_gfx90a_op_V_CMPX_GE_I64,"V_CMPX_GE_I64"} ,//246 + {amdgpu_gfx90a_op_V_CMPX_T_I64,"V_CMPX_T_I64"} ,//247 + {amdgpu_gfx90a_op_V_CMPX_F_U64,"V_CMPX_F_U64"} ,//248 + {amdgpu_gfx90a_op_V_CMPX_LT_U64,"V_CMPX_LT_U64"} ,//249 + {amdgpu_gfx90a_op_V_CMPX_EQ_U64,"V_CMPX_EQ_U64"} ,//250 + {amdgpu_gfx90a_op_V_CMPX_LE_U64,"V_CMPX_LE_U64"} ,//251 + {amdgpu_gfx90a_op_V_CMPX_GT_U64,"V_CMPX_GT_U64"} ,//252 + {amdgpu_gfx90a_op_V_CMPX_NE_U64,"V_CMPX_NE_U64"} ,//253 + {amdgpu_gfx90a_op_V_CMPX_GE_U64,"V_CMPX_GE_U64"} ,//254 + {amdgpu_gfx90a_op_V_CMPX_T_U64,"V_CMPX_T_U64"} ,//255 + {amdgpu_gfx90a_op_V_CNDMASK_B32,"V_CNDMASK_B32"} ,//256 + {amdgpu_gfx90a_op_V_ADD_F32,"V_ADD_F32"} ,//257 + {amdgpu_gfx90a_op_V_SUB_F32,"V_SUB_F32"} ,//258 + {amdgpu_gfx90a_op_V_SUBREV_F32,"V_SUBREV_F32"} ,//259 + {amdgpu_gfx90a_op_V_FMAC_F64,"V_FMAC_F64"} ,//260 + {amdgpu_gfx90a_op_V_MUL_F32,"V_MUL_F32"} ,//261 + {amdgpu_gfx90a_op_V_MUL_I32_I24,"V_MUL_I32_I24"} ,//262 + {amdgpu_gfx90a_op_V_MUL_HI_I32_I24,"V_MUL_HI_I32_I24"} ,//263 + {amdgpu_gfx90a_op_V_MUL_U32_U24,"V_MUL_U32_U24"} ,//264 + {amdgpu_gfx90a_op_V_MUL_HI_U32_U24,"V_MUL_HI_U32_U24"} ,//265 + {amdgpu_gfx90a_op_V_MIN_F32,"V_MIN_F32"} ,//266 + {amdgpu_gfx90a_op_V_MAX_F32,"V_MAX_F32"} ,//267 + {amdgpu_gfx90a_op_V_MIN_I32,"V_MIN_I32"} ,//268 + {amdgpu_gfx90a_op_V_MAX_I32,"V_MAX_I32"} ,//269 + {amdgpu_gfx90a_op_V_MIN_U32,"V_MIN_U32"} ,//270 + {amdgpu_gfx90a_op_V_MAX_U32,"V_MAX_U32"} ,//271 + {amdgpu_gfx90a_op_V_LSHRREV_B32,"V_LSHRREV_B32"} ,//272 + {amdgpu_gfx90a_op_V_ASHRREV_I32,"V_ASHRREV_I32"} ,//273 + {amdgpu_gfx90a_op_V_LSHLREV_B32,"V_LSHLREV_B32"} ,//274 + {amdgpu_gfx90a_op_V_AND_B32,"V_AND_B32"} ,//275 + {amdgpu_gfx90a_op_V_OR_B32,"V_OR_B32"} ,//276 + {amdgpu_gfx90a_op_V_XOR_B32,"V_XOR_B32"} ,//277 + {amdgpu_gfx90a_op_V_MAC_F32,"V_MAC_F32"} ,//278 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//279 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//280 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//281 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//282 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//283 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//284 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//285 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//286 + {amdgpu_gfx90a_op_V_ADD_F16,"V_ADD_F16"} ,//287 + {amdgpu_gfx90a_op_V_SUB_F16,"V_SUB_F16"} ,//288 + {amdgpu_gfx90a_op_V_SUBREV_F16,"V_SUBREV_F16"} ,//289 + {amdgpu_gfx90a_op_V_MUL_F16,"V_MUL_F16"} ,//290 + {amdgpu_gfx90a_op_V_MAC_F16,"V_MAC_F16"} ,//291 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//292 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//293 + {amdgpu_gfx90a_op_V_ADD_U16,"V_ADD_U16"} ,//294 + {amdgpu_gfx90a_op_V_SUB_U16,"V_SUB_U16"} ,//295 + {amdgpu_gfx90a_op_V_SUBREV_U16,"V_SUBREV_U16"} ,//296 + {amdgpu_gfx90a_op_V_MUL_LO_U16,"V_MUL_LO_U16"} ,//297 + {amdgpu_gfx90a_op_V_LSHLREV_B16,"V_LSHLREV_B16"} ,//298 + {amdgpu_gfx90a_op_V_LSHRREV_B16,"V_LSHRREV_B16"} ,//299 + {amdgpu_gfx90a_op_V_ASHRREV_I16,"V_ASHRREV_I16"} ,//300 + {amdgpu_gfx90a_op_V_MAX_F16,"V_MAX_F16"} ,//301 + {amdgpu_gfx90a_op_V_MIN_F16,"V_MIN_F16"} ,//302 + {amdgpu_gfx90a_op_V_MAX_U16,"V_MAX_U16"} ,//303 + {amdgpu_gfx90a_op_V_MAX_I16,"V_MAX_I16"} ,//304 + {amdgpu_gfx90a_op_V_MIN_U16,"V_MIN_U16"} ,//305 + {amdgpu_gfx90a_op_V_MIN_I16,"V_MIN_I16"} ,//306 + {amdgpu_gfx90a_op_V_LDEXP_F16,"V_LDEXP_F16"} ,//307 + {amdgpu_gfx90a_op_V_ADD_U32,"V_ADD_U32"} ,//308 + {amdgpu_gfx90a_op_V_SUB_U32,"V_SUB_U32"} ,//309 + {amdgpu_gfx90a_op_V_SUBREV_U32,"V_SUBREV_U32"} ,//310 + {amdgpu_gfx90a_op_V_DOT2C_F32_F16,"V_DOT2C_F32_F16"} ,//311 + {amdgpu_gfx90a_op_V_DOT2C_I32_I16,"V_DOT2C_I32_I16"} ,//312 + {amdgpu_gfx90a_op_V_DOT4C_I32_I8,"V_DOT4C_I32_I8"} ,//313 + {amdgpu_gfx90a_op_V_DOT8C_I32_I4,"V_DOT8C_I32_I4"} ,//314 + {amdgpu_gfx90a_op_V_FMAC_F32,"V_FMAC_F32"} ,//315 + {amdgpu_gfx90a_op_V_PK_FMAC_F16,"V_PK_FMAC_F16"} ,//316 + {amdgpu_gfx90a_op_V_XNOR_B32,"V_XNOR_B32"} ,//317 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//318 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//319 + {amdgpu_gfx90a_op_V_NOP,"V_NOP"} ,//320 + {amdgpu_gfx90a_op_V_MOV_B32,"V_MOV_B32"} ,//321 + {amdgpu_gfx90a_op_V_READFIRSTLANE_B32,"V_READFIRSTLANE_B32"} ,//322 + {amdgpu_gfx90a_op_V_CVT_I32_F64,"V_CVT_I32_F64"} ,//323 + {amdgpu_gfx90a_op_V_CVT_F64_I32,"V_CVT_F64_I32"} ,//324 + {amdgpu_gfx90a_op_V_CVT_F32_I32,"V_CVT_F32_I32"} ,//325 + {amdgpu_gfx90a_op_V_CVT_F32_U32,"V_CVT_F32_U32"} ,//326 + {amdgpu_gfx90a_op_V_CVT_U32_F32,"V_CVT_U32_F32"} ,//327 + {amdgpu_gfx90a_op_V_CVT_I32_F32,"V_CVT_I32_F32"} ,//328 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//329 + {amdgpu_gfx90a_op_V_CVT_F16_F32,"V_CVT_F16_F32"} ,//330 + {amdgpu_gfx90a_op_V_CVT_F32_F16,"V_CVT_F32_F16"} ,//331 + {amdgpu_gfx90a_op_V_CVT_RPI_I32_F32,"V_CVT_RPI_I32_F32"} ,//332 + {amdgpu_gfx90a_op_V_CVT_FLR_I32_F32,"V_CVT_FLR_I32_F32"} ,//333 + {amdgpu_gfx90a_op_V_CVT_OFF_F32_I4,"V_CVT_OFF_F32_I4"} ,//334 + {amdgpu_gfx90a_op_V_CVT_F32_F64,"V_CVT_F32_F64"} ,//335 + {amdgpu_gfx90a_op_V_CVT_F64_F32,"V_CVT_F64_F32"} ,//336 + {amdgpu_gfx90a_op_V_CVT_F32_UBYTE0,"V_CVT_F32_UBYTE0"} ,//337 + {amdgpu_gfx90a_op_V_CVT_F32_UBYTE1,"V_CVT_F32_UBYTE1"} ,//338 + {amdgpu_gfx90a_op_V_CVT_F32_UBYTE2,"V_CVT_F32_UBYTE2"} ,//339 + {amdgpu_gfx90a_op_V_CVT_F32_UBYTE3,"V_CVT_F32_UBYTE3"} ,//340 + {amdgpu_gfx90a_op_V_CVT_U32_F64,"V_CVT_U32_F64"} ,//341 + {amdgpu_gfx90a_op_V_CVT_F64_U32,"V_CVT_F64_U32"} ,//342 + {amdgpu_gfx90a_op_V_TRUNC_F64,"V_TRUNC_F64"} ,//343 + {amdgpu_gfx90a_op_V_CEIL_F64,"V_CEIL_F64"} ,//344 + {amdgpu_gfx90a_op_V_RNDNE_F64,"V_RNDNE_F64"} ,//345 + {amdgpu_gfx90a_op_V_FLOOR_F64,"V_FLOOR_F64"} ,//346 + {amdgpu_gfx90a_op_V_FRACT_F32,"V_FRACT_F32"} ,//347 + {amdgpu_gfx90a_op_V_TRUNC_F32,"V_TRUNC_F32"} ,//348 + {amdgpu_gfx90a_op_V_CEIL_F32,"V_CEIL_F32"} ,//349 + {amdgpu_gfx90a_op_V_RNDNE_F32,"V_RNDNE_F32"} ,//350 + {amdgpu_gfx90a_op_V_FLOOR_F32,"V_FLOOR_F32"} ,//351 + {amdgpu_gfx90a_op_V_EXP_F32,"V_EXP_F32"} ,//352 + {amdgpu_gfx90a_op_V_LOG_F32,"V_LOG_F32"} ,//353 + {amdgpu_gfx90a_op_V_RCP_F32,"V_RCP_F32"} ,//354 + {amdgpu_gfx90a_op_V_RCP_IFLAG_F32,"V_RCP_IFLAG_F32"} ,//355 + {amdgpu_gfx90a_op_V_RSQ_F32,"V_RSQ_F32"} ,//356 + {amdgpu_gfx90a_op_V_RCP_F64,"V_RCP_F64"} ,//357 + {amdgpu_gfx90a_op_V_RSQ_F64,"V_RSQ_F64"} ,//358 + {amdgpu_gfx90a_op_V_SQRT_F32,"V_SQRT_F32"} ,//359 + {amdgpu_gfx90a_op_V_SQRT_F64,"V_SQRT_F64"} ,//360 + {amdgpu_gfx90a_op_V_SIN_F32,"V_SIN_F32"} ,//361 + {amdgpu_gfx90a_op_V_COS_F32,"V_COS_F32"} ,//362 + {amdgpu_gfx90a_op_V_NOT_B32,"V_NOT_B32"} ,//363 + {amdgpu_gfx90a_op_V_BFREV_B32,"V_BFREV_B32"} ,//364 + {amdgpu_gfx90a_op_V_FFBH_U32,"V_FFBH_U32"} ,//365 + {amdgpu_gfx90a_op_V_FFBL_B32,"V_FFBL_B32"} ,//366 + {amdgpu_gfx90a_op_V_FFBH_I32,"V_FFBH_I32"} ,//367 + {amdgpu_gfx90a_op_V_FREXP_EXP_I32_F64,"V_FREXP_EXP_I32_F64"} ,//368 + {amdgpu_gfx90a_op_V_FREXP_MANT_F64,"V_FREXP_MANT_F64"} ,//369 + {amdgpu_gfx90a_op_V_FRACT_F64,"V_FRACT_F64"} ,//370 + {amdgpu_gfx90a_op_V_FREXP_EXP_I32_F32,"V_FREXP_EXP_I32_F32"} ,//371 + {amdgpu_gfx90a_op_V_FREXP_MANT_F32,"V_FREXP_MANT_F32"} ,//372 + {amdgpu_gfx90a_op_V_CLREXCP,"V_CLREXCP"} ,//373 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//374 + {amdgpu_gfx90a_op_V_SCREEN_PARTITION_4SE_B32,"V_SCREEN_PARTITION_4SE_B32"} ,//375 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//376 + {amdgpu_gfx90a_op_V_CVT_F16_U16,"V_CVT_F16_U16"} ,//377 + {amdgpu_gfx90a_op_V_CVT_F16_I16,"V_CVT_F16_I16"} ,//378 + {amdgpu_gfx90a_op_V_CVT_U16_F16,"V_CVT_U16_F16"} ,//379 + {amdgpu_gfx90a_op_V_CVT_I16_F16,"V_CVT_I16_F16"} ,//380 + {amdgpu_gfx90a_op_V_RCP_F16,"V_RCP_F16"} ,//381 + {amdgpu_gfx90a_op_V_SQRT_F16,"V_SQRT_F16"} ,//382 + {amdgpu_gfx90a_op_V_RSQ_F16,"V_RSQ_F16"} ,//383 + {amdgpu_gfx90a_op_V_LOG_F16,"V_LOG_F16"} ,//384 + {amdgpu_gfx90a_op_V_EXP_F16,"V_EXP_F16"} ,//385 + {amdgpu_gfx90a_op_V_FREXP_MANT_F16,"V_FREXP_MANT_F16"} ,//386 + {amdgpu_gfx90a_op_V_FREXP_EXP_I16_F16,"V_FREXP_EXP_I16_F16"} ,//387 + {amdgpu_gfx90a_op_V_FLOOR_F16,"V_FLOOR_F16"} ,//388 + {amdgpu_gfx90a_op_V_CEIL_F16,"V_CEIL_F16"} ,//389 + {amdgpu_gfx90a_op_V_TRUNC_F16,"V_TRUNC_F16"} ,//390 + {amdgpu_gfx90a_op_V_RNDNE_F16,"V_RNDNE_F16"} ,//391 + {amdgpu_gfx90a_op_V_FRACT_F16,"V_FRACT_F16"} ,//392 + {amdgpu_gfx90a_op_V_SIN_F16,"V_SIN_F16"} ,//393 + {amdgpu_gfx90a_op_V_COS_F16,"V_COS_F16"} ,//394 + {amdgpu_gfx90a_op_V_EXP_LEGACY_F32,"V_EXP_LEGACY_F32"} ,//395 + {amdgpu_gfx90a_op_V_LOG_LEGACY_F32,"V_LOG_LEGACY_F32"} ,//396 + {amdgpu_gfx90a_op_V_CVT_NORM_I16_F16,"V_CVT_NORM_I16_F16"} ,//397 + {amdgpu_gfx90a_op_V_CVT_NORM_U16_F16,"V_CVT_NORM_U16_F16"} ,//398 + {amdgpu_gfx90a_op_V_SAT_PK_U8_I16,"V_SAT_PK_U8_I16"} ,//399 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//400 + {amdgpu_gfx90a_op_V_SWAP_B32,"V_SWAP_B32"} ,//401 + {amdgpu_gfx90a_op_V_ACCVGPR_MOV_B32,"V_ACCVGPR_MOV_B32"} ,//402 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//403 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//404 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//405 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//406 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//407 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//408 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//409 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//410 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//411 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//412 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//413 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//414 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//415 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//416 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//417 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//418 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//419 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//420 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//421 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//422 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//423 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//424 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//425 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//426 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//427 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//428 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//429 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//430 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//431 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//432 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//433 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//434 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//435 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//436 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//437 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//438 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//439 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//440 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//441 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//442 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//443 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//444 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//445 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//446 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//447 + {amdgpu_gfx90a_op_V_MAD_LEGACY_F32,"V_MAD_LEGACY_F32"} ,//448 + {amdgpu_gfx90a_op_V_MAD_F32,"V_MAD_F32"} ,//449 + {amdgpu_gfx90a_op_V_MAD_I32_I24,"V_MAD_I32_I24"} ,//450 + {amdgpu_gfx90a_op_V_MAD_U32_U24,"V_MAD_U32_U24"} ,//451 + {amdgpu_gfx90a_op_V_CUBEID_F32,"V_CUBEID_F32"} ,//452 + {amdgpu_gfx90a_op_V_CUBESC_F32,"V_CUBESC_F32"} ,//453 + {amdgpu_gfx90a_op_V_CUBETC_F32,"V_CUBETC_F32"} ,//454 + {amdgpu_gfx90a_op_V_CUBEMA_F32,"V_CUBEMA_F32"} ,//455 + {amdgpu_gfx90a_op_V_BFE_U32,"V_BFE_U32"} ,//456 + {amdgpu_gfx90a_op_V_BFE_I32,"V_BFE_I32"} ,//457 + {amdgpu_gfx90a_op_V_BFI_B32,"V_BFI_B32"} ,//458 + {amdgpu_gfx90a_op_V_FMA_F32,"V_FMA_F32"} ,//459 + {amdgpu_gfx90a_op_V_FMA_F64,"V_FMA_F64"} ,//460 + {amdgpu_gfx90a_op_V_LERP_U8,"V_LERP_U8"} ,//461 + {amdgpu_gfx90a_op_V_ALIGNBIT_B32,"V_ALIGNBIT_B32"} ,//462 + {amdgpu_gfx90a_op_V_ALIGNBYTE_B32,"V_ALIGNBYTE_B32"} ,//463 + {amdgpu_gfx90a_op_V_MIN3_F32,"V_MIN3_F32"} ,//464 + {amdgpu_gfx90a_op_V_MIN3_I32,"V_MIN3_I32"} ,//465 + {amdgpu_gfx90a_op_V_MIN3_U32,"V_MIN3_U32"} ,//466 + {amdgpu_gfx90a_op_V_MAX3_F32,"V_MAX3_F32"} ,//467 + {amdgpu_gfx90a_op_V_MAX3_I32,"V_MAX3_I32"} ,//468 + {amdgpu_gfx90a_op_V_MAX3_U32,"V_MAX3_U32"} ,//469 + {amdgpu_gfx90a_op_V_MED3_F32,"V_MED3_F32"} ,//470 + {amdgpu_gfx90a_op_V_MED3_I32,"V_MED3_I32"} ,//471 + {amdgpu_gfx90a_op_V_MED3_U32,"V_MED3_U32"} ,//472 + {amdgpu_gfx90a_op_V_SAD_U8,"V_SAD_U8"} ,//473 + {amdgpu_gfx90a_op_V_SAD_HI_U8,"V_SAD_HI_U8"} ,//474 + {amdgpu_gfx90a_op_V_SAD_U16,"V_SAD_U16"} ,//475 + {amdgpu_gfx90a_op_V_SAD_U32,"V_SAD_U32"} ,//476 + {amdgpu_gfx90a_op_V_CVT_PK_U8_F32,"V_CVT_PK_U8_F32"} ,//477 + {amdgpu_gfx90a_op_V_DIV_FIXUP_F32,"V_DIV_FIXUP_F32"} ,//478 + {amdgpu_gfx90a_op_V_DIV_FIXUP_F64,"V_DIV_FIXUP_F64"} ,//479 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//480 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//481 + {amdgpu_gfx90a_op_V_DIV_FMAS_F32,"V_DIV_FMAS_F32"} ,//482 + {amdgpu_gfx90a_op_V_DIV_FMAS_F64,"V_DIV_FMAS_F64"} ,//483 + {amdgpu_gfx90a_op_V_MSAD_U8,"V_MSAD_U8"} ,//484 + {amdgpu_gfx90a_op_V_QSAD_PK_U16_U8,"V_QSAD_PK_U16_U8"} ,//485 + {amdgpu_gfx90a_op_V_MQSAD_PK_U16_U8,"V_MQSAD_PK_U16_U8"} ,//486 + {amdgpu_gfx90a_op_V_MQSAD_U32_U8,"V_MQSAD_U32_U8"} ,//487 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//488 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//489 + {amdgpu_gfx90a_op_V_MAD_LEGACY_F16,"V_MAD_LEGACY_F16"} ,//490 + {amdgpu_gfx90a_op_V_MAD_LEGACY_U16,"V_MAD_LEGACY_U16"} ,//491 + {amdgpu_gfx90a_op_V_MAD_LEGACY_I16,"V_MAD_LEGACY_I16"} ,//492 + {amdgpu_gfx90a_op_V_PERM_B32,"V_PERM_B32"} ,//493 + {amdgpu_gfx90a_op_V_FMA_LEGACY_F16,"V_FMA_LEGACY_F16"} ,//494 + {amdgpu_gfx90a_op_V_DIV_FIXUP_LEGACY_F16,"V_DIV_FIXUP_LEGACY_F16"} ,//495 + {amdgpu_gfx90a_op_V_CVT_PKACCUM_U8_F32,"V_CVT_PKACCUM_U8_F32"} ,//496 + {amdgpu_gfx90a_op_V_MAD_U32_U16,"V_MAD_U32_U16"} ,//497 + {amdgpu_gfx90a_op_V_MAD_I32_I16,"V_MAD_I32_I16"} ,//498 + {amdgpu_gfx90a_op_V_XAD_U32,"V_XAD_U32"} ,//499 + {amdgpu_gfx90a_op_V_MIN3_F16,"V_MIN3_F16"} ,//500 + {amdgpu_gfx90a_op_V_MIN3_I16,"V_MIN3_I16"} ,//501 + {amdgpu_gfx90a_op_V_MIN3_U16,"V_MIN3_U16"} ,//502 + {amdgpu_gfx90a_op_V_MAX3_F16,"V_MAX3_F16"} ,//503 + {amdgpu_gfx90a_op_V_MAX3_I16,"V_MAX3_I16"} ,//504 + {amdgpu_gfx90a_op_V_MAX3_U16,"V_MAX3_U16"} ,//505 + {amdgpu_gfx90a_op_V_MED3_F16,"V_MED3_F16"} ,//506 + {amdgpu_gfx90a_op_V_MED3_I16,"V_MED3_I16"} ,//507 + {amdgpu_gfx90a_op_V_MED3_U16,"V_MED3_U16"} ,//508 + {amdgpu_gfx90a_op_V_LSHL_ADD_U32,"V_LSHL_ADD_U32"} ,//509 + {amdgpu_gfx90a_op_V_ADD_LSHL_U32,"V_ADD_LSHL_U32"} ,//510 + {amdgpu_gfx90a_op_V_ADD3_U32,"V_ADD3_U32"} ,//511 + {amdgpu_gfx90a_op_V_LSHL_OR_B32,"V_LSHL_OR_B32"} ,//512 + {amdgpu_gfx90a_op_V_AND_OR_B32,"V_AND_OR_B32"} ,//513 + {amdgpu_gfx90a_op_V_OR3_B32,"V_OR3_B32"} ,//514 + {amdgpu_gfx90a_op_V_MAD_F16,"V_MAD_F16"} ,//515 + {amdgpu_gfx90a_op_V_MAD_U16,"V_MAD_U16"} ,//516 + {amdgpu_gfx90a_op_V_MAD_I16,"V_MAD_I16"} ,//517 + {amdgpu_gfx90a_op_V_FMA_F16,"V_FMA_F16"} ,//518 + {amdgpu_gfx90a_op_V_DIV_FIXUP_F16,"V_DIV_FIXUP_F16"} ,//519 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//520 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//521 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//522 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//523 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//524 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//525 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//526 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//527 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//528 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//529 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//530 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//531 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//532 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//533 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//534 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//535 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//536 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//537 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//538 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//539 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//540 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//541 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//542 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//543 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//544 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//545 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//546 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//547 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//548 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//549 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//550 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//551 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//552 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//553 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//554 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//555 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//556 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//557 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//558 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//559 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//560 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//561 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//562 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//563 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//564 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//565 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//566 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//567 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//568 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//569 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//570 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//571 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//572 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//573 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//574 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//575 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//576 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//577 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//578 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//579 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//580 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//581 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//582 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//583 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//584 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//585 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//586 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//587 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//588 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//589 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//590 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//591 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//592 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//593 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//594 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//595 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//596 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//597 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//598 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//599 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//600 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//601 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//602 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//603 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//604 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//605 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//606 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//607 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//608 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//609 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//610 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//611 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//612 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//613 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//614 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//615 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//616 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//617 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//618 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//619 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//620 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//621 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//622 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//623 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//624 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//625 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//626 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//627 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//628 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//629 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//630 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//631 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//632 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//633 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//634 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//635 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//636 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//637 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//638 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//639 + {amdgpu_gfx90a_op_V_ADD_F64,"V_ADD_F64"} ,//640 + {amdgpu_gfx90a_op_V_MUL_F64,"V_MUL_F64"} ,//641 + {amdgpu_gfx90a_op_V_MIN_F64,"V_MIN_F64"} ,//642 + {amdgpu_gfx90a_op_V_MAX_F64,"V_MAX_F64"} ,//643 + {amdgpu_gfx90a_op_V_LDEXP_F64,"V_LDEXP_F64"} ,//644 + {amdgpu_gfx90a_op_V_MUL_LO_U32,"V_MUL_LO_U32"} ,//645 + {amdgpu_gfx90a_op_V_MUL_HI_U32,"V_MUL_HI_U32"} ,//646 + {amdgpu_gfx90a_op_V_MUL_HI_I32,"V_MUL_HI_I32"} ,//647 + {amdgpu_gfx90a_op_V_LDEXP_F32,"V_LDEXP_F32"} ,//648 + {amdgpu_gfx90a_op_V_READLANE_B32,"V_READLANE_B32"} ,//649 + {amdgpu_gfx90a_op_V_WRITELANE_B32,"V_WRITELANE_B32"} ,//650 + {amdgpu_gfx90a_op_V_BCNT_U32_B32,"V_BCNT_U32_B32"} ,//651 + {amdgpu_gfx90a_op_V_MBCNT_LO_U32_B32,"V_MBCNT_LO_U32_B32"} ,//652 + {amdgpu_gfx90a_op_V_MBCNT_HI_U32_B32,"V_MBCNT_HI_U32_B32"} ,//653 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//654 + {amdgpu_gfx90a_op_V_LSHLREV_B64,"V_LSHLREV_B64"} ,//655 + {amdgpu_gfx90a_op_V_LSHRREV_B64,"V_LSHRREV_B64"} ,//656 + {amdgpu_gfx90a_op_V_ASHRREV_I64,"V_ASHRREV_I64"} ,//657 + {amdgpu_gfx90a_op_V_TRIG_PREOP_F64,"V_TRIG_PREOP_F64"} ,//658 + {amdgpu_gfx90a_op_V_BFM_B32,"V_BFM_B32"} ,//659 + {amdgpu_gfx90a_op_V_CVT_PKNORM_I16_F32,"V_CVT_PKNORM_I16_F32"} ,//660 + {amdgpu_gfx90a_op_V_CVT_PKNORM_U16_F32,"V_CVT_PKNORM_U16_F32"} ,//661 + {amdgpu_gfx90a_op_V_CVT_PKRTZ_F16_F32,"V_CVT_PKRTZ_F16_F32"} ,//662 + {amdgpu_gfx90a_op_V_CVT_PK_U16_U32,"V_CVT_PK_U16_U32"} ,//663 + {amdgpu_gfx90a_op_V_CVT_PK_I16_I32,"V_CVT_PK_I16_I32"} ,//664 + {amdgpu_gfx90a_op_V_CVT_PKNORM_I16_F16,"V_CVT_PKNORM_I16_F16"} ,//665 + {amdgpu_gfx90a_op_V_CVT_PKNORM_U16_F16,"V_CVT_PKNORM_U16_F16"} ,//666 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//667 + {amdgpu_gfx90a_op_V_ADD_I32,"V_ADD_I32"} ,//668 + {amdgpu_gfx90a_op_V_SUB_I32,"V_SUB_I32"} ,//669 + {amdgpu_gfx90a_op_V_ADD_I16,"V_ADD_I16"} ,//670 + {amdgpu_gfx90a_op_V_SUB_I16,"V_SUB_I16"} ,//671 + {amdgpu_gfx90a_op_V_PACK_B32_F16,"V_PACK_B32_F16"} ,//672 + {amdgpu_gfx90a_op_V_MUL_LEGACY_F32,"V_MUL_LEGACY_F32"} ,//673 + }; // end ENC_VOP3_insn_table + const amdgpu_gfx90a_insn_entry ENC_VOP2_insn_table [62] = + { + {amdgpu_gfx90a_op_V_CNDMASK_B32,"V_CNDMASK_B32"} ,//0 + {amdgpu_gfx90a_op_V_ADD_F32,"V_ADD_F32"} ,//1 + {amdgpu_gfx90a_op_V_SUB_F32,"V_SUB_F32"} ,//2 + {amdgpu_gfx90a_op_V_SUBREV_F32,"V_SUBREV_F32"} ,//3 + {amdgpu_gfx90a_op_V_FMAC_F64,"V_FMAC_F64"} ,//4 + {amdgpu_gfx90a_op_V_MUL_F32,"V_MUL_F32"} ,//5 + {amdgpu_gfx90a_op_V_MUL_I32_I24,"V_MUL_I32_I24"} ,//6 + {amdgpu_gfx90a_op_V_MUL_HI_I32_I24,"V_MUL_HI_I32_I24"} ,//7 + {amdgpu_gfx90a_op_V_MUL_U32_U24,"V_MUL_U32_U24"} ,//8 + {amdgpu_gfx90a_op_V_MUL_HI_U32_U24,"V_MUL_HI_U32_U24"} ,//9 + {amdgpu_gfx90a_op_V_MIN_F32,"V_MIN_F32"} ,//10 + {amdgpu_gfx90a_op_V_MAX_F32,"V_MAX_F32"} ,//11 + {amdgpu_gfx90a_op_V_MIN_I32,"V_MIN_I32"} ,//12 + {amdgpu_gfx90a_op_V_MAX_I32,"V_MAX_I32"} ,//13 + {amdgpu_gfx90a_op_V_MIN_U32,"V_MIN_U32"} ,//14 + {amdgpu_gfx90a_op_V_MAX_U32,"V_MAX_U32"} ,//15 + {amdgpu_gfx90a_op_V_LSHRREV_B32,"V_LSHRREV_B32"} ,//16 + {amdgpu_gfx90a_op_V_ASHRREV_I32,"V_ASHRREV_I32"} ,//17 + {amdgpu_gfx90a_op_V_LSHLREV_B32,"V_LSHLREV_B32"} ,//18 + {amdgpu_gfx90a_op_V_AND_B32,"V_AND_B32"} ,//19 + {amdgpu_gfx90a_op_V_OR_B32,"V_OR_B32"} ,//20 + {amdgpu_gfx90a_op_V_XOR_B32,"V_XOR_B32"} ,//21 + {amdgpu_gfx90a_op_V_MAC_F32,"V_MAC_F32"} ,//22 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//23 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//24 + {amdgpu_gfx90a_op_V_ADD_CO_U32,"V_ADD_CO_U32"} ,//25 + {amdgpu_gfx90a_op_V_SUB_CO_U32,"V_SUB_CO_U32"} ,//26 + {amdgpu_gfx90a_op_V_SUBREV_CO_U32,"V_SUBREV_CO_U32"} ,//27 + {amdgpu_gfx90a_op_V_ADDC_CO_U32,"V_ADDC_CO_U32"} ,//28 + {amdgpu_gfx90a_op_V_SUBB_CO_U32,"V_SUBB_CO_U32"} ,//29 + {amdgpu_gfx90a_op_V_SUBBREV_CO_U32,"V_SUBBREV_CO_U32"} ,//30 + {amdgpu_gfx90a_op_V_ADD_F16,"V_ADD_F16"} ,//31 + {amdgpu_gfx90a_op_V_SUB_F16,"V_SUB_F16"} ,//32 + {amdgpu_gfx90a_op_V_SUBREV_F16,"V_SUBREV_F16"} ,//33 + {amdgpu_gfx90a_op_V_MUL_F16,"V_MUL_F16"} ,//34 + {amdgpu_gfx90a_op_V_MAC_F16,"V_MAC_F16"} ,//35 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//36 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//37 + {amdgpu_gfx90a_op_V_ADD_U16,"V_ADD_U16"} ,//38 + {amdgpu_gfx90a_op_V_SUB_U16,"V_SUB_U16"} ,//39 + {amdgpu_gfx90a_op_V_SUBREV_U16,"V_SUBREV_U16"} ,//40 + {amdgpu_gfx90a_op_V_MUL_LO_U16,"V_MUL_LO_U16"} ,//41 + {amdgpu_gfx90a_op_V_LSHLREV_B16,"V_LSHLREV_B16"} ,//42 + {amdgpu_gfx90a_op_V_LSHRREV_B16,"V_LSHRREV_B16"} ,//43 + {amdgpu_gfx90a_op_V_ASHRREV_I16,"V_ASHRREV_I16"} ,//44 + {amdgpu_gfx90a_op_V_MAX_F16,"V_MAX_F16"} ,//45 + {amdgpu_gfx90a_op_V_MIN_F16,"V_MIN_F16"} ,//46 + {amdgpu_gfx90a_op_V_MAX_U16,"V_MAX_U16"} ,//47 + {amdgpu_gfx90a_op_V_MAX_I16,"V_MAX_I16"} ,//48 + {amdgpu_gfx90a_op_V_MIN_U16,"V_MIN_U16"} ,//49 + {amdgpu_gfx90a_op_V_MIN_I16,"V_MIN_I16"} ,//50 + {amdgpu_gfx90a_op_V_LDEXP_F16,"V_LDEXP_F16"} ,//51 + {amdgpu_gfx90a_op_V_ADD_U32,"V_ADD_U32"} ,//52 + {amdgpu_gfx90a_op_V_SUB_U32,"V_SUB_U32"} ,//53 + {amdgpu_gfx90a_op_V_SUBREV_U32,"V_SUBREV_U32"} ,//54 + {amdgpu_gfx90a_op_V_DOT2C_F32_F16,"V_DOT2C_F32_F16"} ,//55 + {amdgpu_gfx90a_op_V_DOT2C_I32_I16,"V_DOT2C_I32_I16"} ,//56 + {amdgpu_gfx90a_op_V_DOT4C_I32_I8,"V_DOT4C_I32_I8"} ,//57 + {amdgpu_gfx90a_op_V_DOT8C_I32_I4,"V_DOT8C_I32_I4"} ,//58 + {amdgpu_gfx90a_op_V_FMAC_F32,"V_FMAC_F32"} ,//59 + {amdgpu_gfx90a_op_V_PK_FMAC_F16,"V_PK_FMAC_F16"} ,//60 + {amdgpu_gfx90a_op_V_XNOR_B32,"V_XNOR_B32"} ,//61 + }; // end ENC_VOP2_insn_table + const amdgpu_gfx90a_insn_entry ENC_VOP2_LITERAL_insn_table [38] = + { + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//0 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//1 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//2 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//3 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//4 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//5 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//6 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//7 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//8 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//9 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//10 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//11 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//12 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//13 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//14 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//15 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//16 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//17 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//18 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//19 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//20 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//21 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//22 + {amdgpu_gfx90a_op_V_MADMK_F32,"V_MADMK_F32"} ,//23 + {amdgpu_gfx90a_op_V_MADAK_F32,"V_MADAK_F32"} ,//24 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//25 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//26 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//27 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//28 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//29 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//30 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//31 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//32 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//33 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//34 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//35 + {amdgpu_gfx90a_op_V_MADMK_F16,"V_MADMK_F16"} ,//36 + {amdgpu_gfx90a_op_V_MADAK_F16,"V_MADAK_F16"} ,//37 + }; // end ENC_VOP2_LITERAL_insn_table + const amdgpu_gfx90a_insn_entry ENC_VOP3B_insn_table [490] = + { + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//0 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//1 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//2 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//3 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//4 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//5 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//6 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//7 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//8 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//9 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//10 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//11 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//12 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//13 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//14 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//15 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//16 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//17 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//18 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//19 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//20 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//21 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//22 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//23 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//24 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//25 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//26 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//27 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//28 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//29 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//30 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//31 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//32 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//33 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//34 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//35 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//36 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//37 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//38 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//39 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//40 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//41 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//42 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//43 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//44 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//45 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//46 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//47 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//48 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//49 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//50 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//51 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//52 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//53 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//54 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//55 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//56 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//57 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//58 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//59 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//60 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//61 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//62 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//63 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//64 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//65 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//66 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//67 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//68 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//69 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//70 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//71 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//72 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//73 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//74 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//75 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//76 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//77 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//78 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//79 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//80 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//81 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//82 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//83 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//84 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//85 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//86 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//87 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//88 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//89 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//90 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//91 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//92 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//93 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//94 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//95 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//96 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//97 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//98 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//99 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//100 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//101 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//102 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//103 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//104 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//105 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//106 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//107 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//108 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//109 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//110 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//111 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//112 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//113 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//114 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//115 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//116 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//117 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//118 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//119 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//120 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//121 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//122 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//123 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//124 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//125 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//126 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//127 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//128 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//129 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//130 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//131 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//132 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//133 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//134 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//135 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//136 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//137 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//138 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//139 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//140 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//141 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//142 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//143 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//144 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//145 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//146 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//147 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//148 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//149 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//150 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//151 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//152 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//153 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//154 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//155 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//156 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//157 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//158 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//159 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//160 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//161 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//162 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//163 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//164 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//165 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//166 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//167 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//168 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//169 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//170 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//171 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//172 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//173 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//174 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//175 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//176 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//177 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//178 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//179 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//180 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//181 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//182 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//183 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//184 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//185 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//186 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//187 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//188 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//189 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//190 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//191 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//192 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//193 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//194 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//195 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//196 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//197 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//198 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//199 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//200 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//201 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//202 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//203 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//204 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//205 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//206 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//207 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//208 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//209 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//210 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//211 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//212 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//213 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//214 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//215 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//216 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//217 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//218 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//219 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//220 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//221 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//222 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//223 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//224 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//225 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//226 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//227 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//228 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//229 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//230 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//231 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//232 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//233 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//234 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//235 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//236 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//237 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//238 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//239 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//240 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//241 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//242 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//243 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//244 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//245 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//246 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//247 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//248 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//249 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//250 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//251 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//252 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//253 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//254 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//255 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//256 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//257 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//258 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//259 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//260 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//261 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//262 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//263 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//264 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//265 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//266 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//267 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//268 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//269 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//270 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//271 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//272 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//273 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//274 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//275 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//276 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//277 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//278 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//279 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//280 + {amdgpu_gfx90a_op_V_ADD_CO_U32,"V_ADD_CO_U32"} ,//281 + {amdgpu_gfx90a_op_V_SUB_CO_U32,"V_SUB_CO_U32"} ,//282 + {amdgpu_gfx90a_op_V_SUBREV_CO_U32,"V_SUBREV_CO_U32"} ,//283 + {amdgpu_gfx90a_op_V_ADDC_CO_U32,"V_ADDC_CO_U32"} ,//284 + {amdgpu_gfx90a_op_V_SUBB_CO_U32,"V_SUBB_CO_U32"} ,//285 + {amdgpu_gfx90a_op_V_SUBBREV_CO_U32,"V_SUBBREV_CO_U32"} ,//286 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//287 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//288 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//289 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//290 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//291 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//292 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//293 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//294 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//295 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//296 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//297 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//298 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//299 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//300 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//301 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//302 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//303 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//304 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//305 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//306 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//307 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//308 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//309 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//310 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//311 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//312 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//313 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//314 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//315 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//316 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//317 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//318 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//319 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//320 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//321 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//322 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//323 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//324 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//325 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//326 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//327 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//328 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//329 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//330 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//331 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//332 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//333 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//334 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//335 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//336 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//337 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//338 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//339 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//340 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//341 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//342 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//343 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//344 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//345 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//346 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//347 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//348 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//349 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//350 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//351 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//352 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//353 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//354 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//355 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//356 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//357 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//358 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//359 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//360 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//361 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//362 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//363 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//364 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//365 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//366 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//367 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//368 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//369 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//370 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//371 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//372 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//373 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//374 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//375 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//376 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//377 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//378 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//379 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//380 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//381 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//382 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//383 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//384 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//385 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//386 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//387 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//388 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//389 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//390 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//391 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//392 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//393 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//394 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//395 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//396 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//397 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//398 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//399 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//400 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//401 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//402 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//403 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//404 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//405 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//406 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//407 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//408 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//409 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//410 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//411 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//412 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//413 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//414 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//415 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//416 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//417 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//418 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//419 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//420 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//421 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//422 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//423 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//424 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//425 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//426 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//427 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//428 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//429 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//430 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//431 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//432 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//433 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//434 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//435 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//436 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//437 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//438 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//439 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//440 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//441 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//442 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//443 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//444 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//445 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//446 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//447 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//448 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//449 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//450 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//451 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//452 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//453 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//454 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//455 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//456 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//457 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//458 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//459 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//460 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//461 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//462 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//463 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//464 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//465 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//466 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//467 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//468 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//469 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//470 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//471 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//472 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//473 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//474 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//475 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//476 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//477 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//478 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//479 + {amdgpu_gfx90a_op_V_DIV_SCALE_F32,"V_DIV_SCALE_F32"} ,//480 + {amdgpu_gfx90a_op_V_DIV_SCALE_F64,"V_DIV_SCALE_F64"} ,//481 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//482 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//483 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//484 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//485 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//486 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//487 + {amdgpu_gfx90a_op_V_MAD_U64_U32,"V_MAD_U64_U32"} ,//488 + {amdgpu_gfx90a_op_V_MAD_I64_I32,"V_MAD_I64_I32"} ,//489 + }; // end ENC_VOP3B_insn_table + const amdgpu_gfx90a_insn_entry ENC_VOP3P_insn_table [90] = + { + {amdgpu_gfx90a_op_V_PK_MAD_I16,"V_PK_MAD_I16"} ,//0 + {amdgpu_gfx90a_op_V_PK_MUL_LO_U16,"V_PK_MUL_LO_U16"} ,//1 + {amdgpu_gfx90a_op_V_PK_ADD_I16,"V_PK_ADD_I16"} ,//2 + {amdgpu_gfx90a_op_V_PK_SUB_I16,"V_PK_SUB_I16"} ,//3 + {amdgpu_gfx90a_op_V_PK_LSHLREV_B16,"V_PK_LSHLREV_B16"} ,//4 + {amdgpu_gfx90a_op_V_PK_LSHRREV_B16,"V_PK_LSHRREV_B16"} ,//5 + {amdgpu_gfx90a_op_V_PK_ASHRREV_I16,"V_PK_ASHRREV_I16"} ,//6 + {amdgpu_gfx90a_op_V_PK_MAX_I16,"V_PK_MAX_I16"} ,//7 + {amdgpu_gfx90a_op_V_PK_MIN_I16,"V_PK_MIN_I16"} ,//8 + {amdgpu_gfx90a_op_V_PK_MAD_U16,"V_PK_MAD_U16"} ,//9 + {amdgpu_gfx90a_op_V_PK_ADD_U16,"V_PK_ADD_U16"} ,//10 + {amdgpu_gfx90a_op_V_PK_SUB_U16,"V_PK_SUB_U16"} ,//11 + {amdgpu_gfx90a_op_V_PK_MAX_U16,"V_PK_MAX_U16"} ,//12 + {amdgpu_gfx90a_op_V_PK_MIN_U16,"V_PK_MIN_U16"} ,//13 + {amdgpu_gfx90a_op_V_PK_FMA_F16,"V_PK_FMA_F16"} ,//14 + {amdgpu_gfx90a_op_V_PK_ADD_F16,"V_PK_ADD_F16"} ,//15 + {amdgpu_gfx90a_op_V_PK_MUL_F16,"V_PK_MUL_F16"} ,//16 + {amdgpu_gfx90a_op_V_PK_MIN_F16,"V_PK_MIN_F16"} ,//17 + {amdgpu_gfx90a_op_V_PK_MAX_F16,"V_PK_MAX_F16"} ,//18 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//19 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//20 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//21 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//22 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//23 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//24 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//25 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//26 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//27 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//28 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//29 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//30 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//31 + {amdgpu_gfx90a_op_V_MAD_MIX_F32,"V_MAD_MIX_F32"} ,//32 + {amdgpu_gfx90a_op_V_MAD_MIXLO_F16,"V_MAD_MIXLO_F16"} ,//33 + {amdgpu_gfx90a_op_V_MAD_MIXHI_F16,"V_MAD_MIXHI_F16"} ,//34 + {amdgpu_gfx90a_op_V_DOT2_F32_F16,"V_DOT2_F32_F16"} ,//35 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//36 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//37 + {amdgpu_gfx90a_op_V_DOT2_I32_I16,"V_DOT2_I32_I16"} ,//38 + {amdgpu_gfx90a_op_V_DOT2_U32_U16,"V_DOT2_U32_U16"} ,//39 + {amdgpu_gfx90a_op_V_DOT4_I32_I8,"V_DOT4_I32_I8"} ,//40 + {amdgpu_gfx90a_op_V_DOT4_U32_U8,"V_DOT4_U32_U8"} ,//41 + {amdgpu_gfx90a_op_V_DOT8_I32_I4,"V_DOT8_I32_I4"} ,//42 + {amdgpu_gfx90a_op_V_DOT8_U32_U4,"V_DOT8_U32_U4"} ,//43 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//44 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//45 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//46 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//47 + {amdgpu_gfx90a_op_V_PK_FMA_F32,"V_PK_FMA_F32"} ,//48 + {amdgpu_gfx90a_op_V_PK_MUL_F32,"V_PK_MUL_F32"} ,//49 + {amdgpu_gfx90a_op_V_PK_ADD_F32,"V_PK_ADD_F32"} ,//50 + {amdgpu_gfx90a_op_V_PK_MOV_B32,"V_PK_MOV_B32"} ,//51 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//52 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//53 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//54 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//55 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//56 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//57 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//58 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//59 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//60 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//61 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//62 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//63 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//64 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//65 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//66 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//67 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//68 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//69 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//70 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//71 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//72 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//73 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//74 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//75 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//76 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//77 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//78 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//79 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//80 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//81 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//82 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//83 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//84 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//85 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//86 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//87 + {amdgpu_gfx90a_op_V_ACCVGPR_READ,"V_ACCVGPR_READ"} ,//88 + {amdgpu_gfx90a_op_V_ACCVGPR_WRITE,"V_ACCVGPR_WRITE"} ,//89 + }; // end ENC_VOP3P_insn_table + const amdgpu_gfx90a_insn_entry ENC_VOP3P_MFMA_insn_table [112] = + { + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//0 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//1 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//2 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//3 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//4 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//5 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//6 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//7 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//8 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//9 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//10 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//11 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//12 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//13 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//14 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//15 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//16 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//17 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//18 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//19 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//20 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//21 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//22 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//23 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//24 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//25 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//26 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//27 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//28 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//29 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//30 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//31 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//32 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//33 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//34 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//35 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//36 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//37 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//38 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//39 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//40 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//41 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//42 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//43 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//44 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//45 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//46 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//47 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//48 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//49 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//50 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//51 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//52 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//53 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//54 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//55 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//56 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//57 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//58 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//59 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//60 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//61 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//62 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//63 + {amdgpu_gfx90a_op_V_MFMA_F32_32X32X1F32,"V_MFMA_F32_32X32X1F32"} ,//64 + {amdgpu_gfx90a_op_V_MFMA_F32_16X16X1F32,"V_MFMA_F32_16X16X1F32"} ,//65 + {amdgpu_gfx90a_op_V_MFMA_F32_4X4X1F32,"V_MFMA_F32_4X4X1F32"} ,//66 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//67 + {amdgpu_gfx90a_op_V_MFMA_F32_32X32X2F32,"V_MFMA_F32_32X32X2F32"} ,//68 + {amdgpu_gfx90a_op_V_MFMA_F32_16X16X4F32,"V_MFMA_F32_16X16X4F32"} ,//69 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//70 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//71 + {amdgpu_gfx90a_op_V_MFMA_F32_32X32X4F16,"V_MFMA_F32_32X32X4F16"} ,//72 + {amdgpu_gfx90a_op_V_MFMA_F32_16X16X4F16,"V_MFMA_F32_16X16X4F16"} ,//73 + {amdgpu_gfx90a_op_V_MFMA_F32_4X4X4F16,"V_MFMA_F32_4X4X4F16"} ,//74 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//75 + {amdgpu_gfx90a_op_V_MFMA_F32_32X32X8F16,"V_MFMA_F32_32X32X8F16"} ,//76 + {amdgpu_gfx90a_op_V_MFMA_F32_16X16X16F16,"V_MFMA_F32_16X16X16F16"} ,//77 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//78 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//79 + {amdgpu_gfx90a_op_V_MFMA_I32_32X32X4I8,"V_MFMA_I32_32X32X4I8"} ,//80 + {amdgpu_gfx90a_op_V_MFMA_I32_16X16X4I8,"V_MFMA_I32_16X16X4I8"} ,//81 + {amdgpu_gfx90a_op_V_MFMA_I32_4X4X4I8,"V_MFMA_I32_4X4X4I8"} ,//82 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//83 + {amdgpu_gfx90a_op_V_MFMA_I32_32X32X8I8,"V_MFMA_I32_32X32X8I8"} ,//84 + {amdgpu_gfx90a_op_V_MFMA_I32_16X16X16I8,"V_MFMA_I32_16X16X16I8"} ,//85 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//86 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//87 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//88 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//89 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//90 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//91 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//92 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//93 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//94 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//95 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//96 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//97 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//98 + {amdgpu_gfx90a_op_V_MFMA_F32_32X32X4BF16_1K,"V_MFMA_F32_32X32X4BF16_1K"} ,//99 + {amdgpu_gfx90a_op_V_MFMA_F32_16X16X4BF16_1K,"V_MFMA_F32_16X16X4BF16_1K"} ,//100 + {amdgpu_gfx90a_op_V_MFMA_F32_4X4X4BF16_1K,"V_MFMA_F32_4X4X4BF16_1K"} ,//101 + {amdgpu_gfx90a_op_V_MFMA_F32_32X32X8BF16_1K,"V_MFMA_F32_32X32X8BF16_1K"} ,//102 + {amdgpu_gfx90a_op_V_MFMA_F32_16X16X16BF16_1K,"V_MFMA_F32_16X16X16BF16_1K"} ,//103 + {amdgpu_gfx90a_op_V_MFMA_F32_32X32X2BF16,"V_MFMA_F32_32X32X2BF16"} ,//104 + {amdgpu_gfx90a_op_V_MFMA_F32_16X16X2BF16,"V_MFMA_F32_16X16X2BF16"} ,//105 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//106 + {amdgpu_gfx90a_op_V_MFMA_F32_4X4X2BF16,"V_MFMA_F32_4X4X2BF16"} ,//107 + {amdgpu_gfx90a_op_V_MFMA_F32_32X32X4BF16,"V_MFMA_F32_32X32X4BF16"} ,//108 + {amdgpu_gfx90a_op_V_MFMA_F32_16X16X8BF16,"V_MFMA_F32_16X16X8BF16"} ,//109 + {amdgpu_gfx90a_op_V_MFMA_F64_16X16X4F64,"V_MFMA_F64_16X16X4F64"} ,//110 + {amdgpu_gfx90a_op_V_MFMA_F64_4X4X4F64,"V_MFMA_F64_4X4X4F64"} ,//111 + }; // end ENC_VOP3P_MFMA_insn_table + const amdgpu_gfx90a_insn_entry ENC_VOPC_insn_table [256] = + { + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//0 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//1 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//2 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//3 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//4 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//5 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//6 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//7 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//8 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//9 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//10 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//11 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//12 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//13 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//14 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//15 + {amdgpu_gfx90a_op_V_CMP_CLASS_F32,"V_CMP_CLASS_F32"} ,//16 + {amdgpu_gfx90a_op_V_CMPX_CLASS_F32,"V_CMPX_CLASS_F32"} ,//17 + {amdgpu_gfx90a_op_V_CMP_CLASS_F64,"V_CMP_CLASS_F64"} ,//18 + {amdgpu_gfx90a_op_V_CMPX_CLASS_F64,"V_CMPX_CLASS_F64"} ,//19 + {amdgpu_gfx90a_op_V_CMP_CLASS_F16,"V_CMP_CLASS_F16"} ,//20 + {amdgpu_gfx90a_op_V_CMPX_CLASS_F16,"V_CMPX_CLASS_F16"} ,//21 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//22 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//23 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//24 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//25 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//26 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//27 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//28 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//29 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//30 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//31 + {amdgpu_gfx90a_op_V_CMP_F_F16,"V_CMP_F_F16"} ,//32 + {amdgpu_gfx90a_op_V_CMP_LT_F16,"V_CMP_LT_F16"} ,//33 + {amdgpu_gfx90a_op_V_CMP_EQ_F16,"V_CMP_EQ_F16"} ,//34 + {amdgpu_gfx90a_op_V_CMP_LE_F16,"V_CMP_LE_F16"} ,//35 + {amdgpu_gfx90a_op_V_CMP_GT_F16,"V_CMP_GT_F16"} ,//36 + {amdgpu_gfx90a_op_V_CMP_LG_F16,"V_CMP_LG_F16"} ,//37 + {amdgpu_gfx90a_op_V_CMP_GE_F16,"V_CMP_GE_F16"} ,//38 + {amdgpu_gfx90a_op_V_CMP_O_F16,"V_CMP_O_F16"} ,//39 + {amdgpu_gfx90a_op_V_CMP_U_F16,"V_CMP_U_F16"} ,//40 + {amdgpu_gfx90a_op_V_CMP_NGE_F16,"V_CMP_NGE_F16"} ,//41 + {amdgpu_gfx90a_op_V_CMP_NLG_F16,"V_CMP_NLG_F16"} ,//42 + {amdgpu_gfx90a_op_V_CMP_NGT_F16,"V_CMP_NGT_F16"} ,//43 + {amdgpu_gfx90a_op_V_CMP_NLE_F16,"V_CMP_NLE_F16"} ,//44 + {amdgpu_gfx90a_op_V_CMP_NEQ_F16,"V_CMP_NEQ_F16"} ,//45 + {amdgpu_gfx90a_op_V_CMP_NLT_F16,"V_CMP_NLT_F16"} ,//46 + {amdgpu_gfx90a_op_V_CMP_TRU_F16,"V_CMP_TRU_F16"} ,//47 + {amdgpu_gfx90a_op_V_CMPX_F_F16,"V_CMPX_F_F16"} ,//48 + {amdgpu_gfx90a_op_V_CMPX_LT_F16,"V_CMPX_LT_F16"} ,//49 + {amdgpu_gfx90a_op_V_CMPX_EQ_F16,"V_CMPX_EQ_F16"} ,//50 + {amdgpu_gfx90a_op_V_CMPX_LE_F16,"V_CMPX_LE_F16"} ,//51 + {amdgpu_gfx90a_op_V_CMPX_GT_F16,"V_CMPX_GT_F16"} ,//52 + {amdgpu_gfx90a_op_V_CMPX_LG_F16,"V_CMPX_LG_F16"} ,//53 + {amdgpu_gfx90a_op_V_CMPX_GE_F16,"V_CMPX_GE_F16"} ,//54 + {amdgpu_gfx90a_op_V_CMPX_O_F16,"V_CMPX_O_F16"} ,//55 + {amdgpu_gfx90a_op_V_CMPX_U_F16,"V_CMPX_U_F16"} ,//56 + {amdgpu_gfx90a_op_V_CMPX_NGE_F16,"V_CMPX_NGE_F16"} ,//57 + {amdgpu_gfx90a_op_V_CMPX_NLG_F16,"V_CMPX_NLG_F16"} ,//58 + {amdgpu_gfx90a_op_V_CMPX_NGT_F16,"V_CMPX_NGT_F16"} ,//59 + {amdgpu_gfx90a_op_V_CMPX_NLE_F16,"V_CMPX_NLE_F16"} ,//60 + {amdgpu_gfx90a_op_V_CMPX_NEQ_F16,"V_CMPX_NEQ_F16"} ,//61 + {amdgpu_gfx90a_op_V_CMPX_NLT_F16,"V_CMPX_NLT_F16"} ,//62 + {amdgpu_gfx90a_op_V_CMPX_TRU_F16,"V_CMPX_TRU_F16"} ,//63 + {amdgpu_gfx90a_op_V_CMP_F_F32,"V_CMP_F_F32"} ,//64 + {amdgpu_gfx90a_op_V_CMP_LT_F32,"V_CMP_LT_F32"} ,//65 + {amdgpu_gfx90a_op_V_CMP_EQ_F32,"V_CMP_EQ_F32"} ,//66 + {amdgpu_gfx90a_op_V_CMP_LE_F32,"V_CMP_LE_F32"} ,//67 + {amdgpu_gfx90a_op_V_CMP_GT_F32,"V_CMP_GT_F32"} ,//68 + {amdgpu_gfx90a_op_V_CMP_LG_F32,"V_CMP_LG_F32"} ,//69 + {amdgpu_gfx90a_op_V_CMP_GE_F32,"V_CMP_GE_F32"} ,//70 + {amdgpu_gfx90a_op_V_CMP_O_F32,"V_CMP_O_F32"} ,//71 + {amdgpu_gfx90a_op_V_CMP_U_F32,"V_CMP_U_F32"} ,//72 + {amdgpu_gfx90a_op_V_CMP_NGE_F32,"V_CMP_NGE_F32"} ,//73 + {amdgpu_gfx90a_op_V_CMP_NLG_F32,"V_CMP_NLG_F32"} ,//74 + {amdgpu_gfx90a_op_V_CMP_NGT_F32,"V_CMP_NGT_F32"} ,//75 + {amdgpu_gfx90a_op_V_CMP_NLE_F32,"V_CMP_NLE_F32"} ,//76 + {amdgpu_gfx90a_op_V_CMP_NEQ_F32,"V_CMP_NEQ_F32"} ,//77 + {amdgpu_gfx90a_op_V_CMP_NLT_F32,"V_CMP_NLT_F32"} ,//78 + {amdgpu_gfx90a_op_V_CMP_TRU_F32,"V_CMP_TRU_F32"} ,//79 + {amdgpu_gfx90a_op_V_CMPX_F_F32,"V_CMPX_F_F32"} ,//80 + {amdgpu_gfx90a_op_V_CMPX_LT_F32,"V_CMPX_LT_F32"} ,//81 + {amdgpu_gfx90a_op_V_CMPX_EQ_F32,"V_CMPX_EQ_F32"} ,//82 + {amdgpu_gfx90a_op_V_CMPX_LE_F32,"V_CMPX_LE_F32"} ,//83 + {amdgpu_gfx90a_op_V_CMPX_GT_F32,"V_CMPX_GT_F32"} ,//84 + {amdgpu_gfx90a_op_V_CMPX_LG_F32,"V_CMPX_LG_F32"} ,//85 + {amdgpu_gfx90a_op_V_CMPX_GE_F32,"V_CMPX_GE_F32"} ,//86 + {amdgpu_gfx90a_op_V_CMPX_O_F32,"V_CMPX_O_F32"} ,//87 + {amdgpu_gfx90a_op_V_CMPX_U_F32,"V_CMPX_U_F32"} ,//88 + {amdgpu_gfx90a_op_V_CMPX_NGE_F32,"V_CMPX_NGE_F32"} ,//89 + {amdgpu_gfx90a_op_V_CMPX_NLG_F32,"V_CMPX_NLG_F32"} ,//90 + {amdgpu_gfx90a_op_V_CMPX_NGT_F32,"V_CMPX_NGT_F32"} ,//91 + {amdgpu_gfx90a_op_V_CMPX_NLE_F32,"V_CMPX_NLE_F32"} ,//92 + {amdgpu_gfx90a_op_V_CMPX_NEQ_F32,"V_CMPX_NEQ_F32"} ,//93 + {amdgpu_gfx90a_op_V_CMPX_NLT_F32,"V_CMPX_NLT_F32"} ,//94 + {amdgpu_gfx90a_op_V_CMPX_TRU_F32,"V_CMPX_TRU_F32"} ,//95 + {amdgpu_gfx90a_op_V_CMP_F_F64,"V_CMP_F_F64"} ,//96 + {amdgpu_gfx90a_op_V_CMP_LT_F64,"V_CMP_LT_F64"} ,//97 + {amdgpu_gfx90a_op_V_CMP_EQ_F64,"V_CMP_EQ_F64"} ,//98 + {amdgpu_gfx90a_op_V_CMP_LE_F64,"V_CMP_LE_F64"} ,//99 + {amdgpu_gfx90a_op_V_CMP_GT_F64,"V_CMP_GT_F64"} ,//100 + {amdgpu_gfx90a_op_V_CMP_LG_F64,"V_CMP_LG_F64"} ,//101 + {amdgpu_gfx90a_op_V_CMP_GE_F64,"V_CMP_GE_F64"} ,//102 + {amdgpu_gfx90a_op_V_CMP_O_F64,"V_CMP_O_F64"} ,//103 + {amdgpu_gfx90a_op_V_CMP_U_F64,"V_CMP_U_F64"} ,//104 + {amdgpu_gfx90a_op_V_CMP_NGE_F64,"V_CMP_NGE_F64"} ,//105 + {amdgpu_gfx90a_op_V_CMP_NLG_F64,"V_CMP_NLG_F64"} ,//106 + {amdgpu_gfx90a_op_V_CMP_NGT_F64,"V_CMP_NGT_F64"} ,//107 + {amdgpu_gfx90a_op_V_CMP_NLE_F64,"V_CMP_NLE_F64"} ,//108 + {amdgpu_gfx90a_op_V_CMP_NEQ_F64,"V_CMP_NEQ_F64"} ,//109 + {amdgpu_gfx90a_op_V_CMP_NLT_F64,"V_CMP_NLT_F64"} ,//110 + {amdgpu_gfx90a_op_V_CMP_TRU_F64,"V_CMP_TRU_F64"} ,//111 + {amdgpu_gfx90a_op_V_CMPX_F_F64,"V_CMPX_F_F64"} ,//112 + {amdgpu_gfx90a_op_V_CMPX_LT_F64,"V_CMPX_LT_F64"} ,//113 + {amdgpu_gfx90a_op_V_CMPX_EQ_F64,"V_CMPX_EQ_F64"} ,//114 + {amdgpu_gfx90a_op_V_CMPX_LE_F64,"V_CMPX_LE_F64"} ,//115 + {amdgpu_gfx90a_op_V_CMPX_GT_F64,"V_CMPX_GT_F64"} ,//116 + {amdgpu_gfx90a_op_V_CMPX_LG_F64,"V_CMPX_LG_F64"} ,//117 + {amdgpu_gfx90a_op_V_CMPX_GE_F64,"V_CMPX_GE_F64"} ,//118 + {amdgpu_gfx90a_op_V_CMPX_O_F64,"V_CMPX_O_F64"} ,//119 + {amdgpu_gfx90a_op_V_CMPX_U_F64,"V_CMPX_U_F64"} ,//120 + {amdgpu_gfx90a_op_V_CMPX_NGE_F64,"V_CMPX_NGE_F64"} ,//121 + {amdgpu_gfx90a_op_V_CMPX_NLG_F64,"V_CMPX_NLG_F64"} ,//122 + {amdgpu_gfx90a_op_V_CMPX_NGT_F64,"V_CMPX_NGT_F64"} ,//123 + {amdgpu_gfx90a_op_V_CMPX_NLE_F64,"V_CMPX_NLE_F64"} ,//124 + {amdgpu_gfx90a_op_V_CMPX_NEQ_F64,"V_CMPX_NEQ_F64"} ,//125 + {amdgpu_gfx90a_op_V_CMPX_NLT_F64,"V_CMPX_NLT_F64"} ,//126 + {amdgpu_gfx90a_op_V_CMPX_TRU_F64,"V_CMPX_TRU_F64"} ,//127 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//128 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//129 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//130 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//131 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//132 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//133 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//134 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//135 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//136 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//137 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//138 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//139 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//140 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//141 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//142 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//143 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//144 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//145 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//146 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//147 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//148 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//149 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//150 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//151 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//152 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//153 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//154 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//155 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//156 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//157 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//158 + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//159 + {amdgpu_gfx90a_op_V_CMP_F_I16,"V_CMP_F_I16"} ,//160 + {amdgpu_gfx90a_op_V_CMP_LT_I16,"V_CMP_LT_I16"} ,//161 + {amdgpu_gfx90a_op_V_CMP_EQ_I16,"V_CMP_EQ_I16"} ,//162 + {amdgpu_gfx90a_op_V_CMP_LE_I16,"V_CMP_LE_I16"} ,//163 + {amdgpu_gfx90a_op_V_CMP_GT_I16,"V_CMP_GT_I16"} ,//164 + {amdgpu_gfx90a_op_V_CMP_NE_I16,"V_CMP_NE_I16"} ,//165 + {amdgpu_gfx90a_op_V_CMP_GE_I16,"V_CMP_GE_I16"} ,//166 + {amdgpu_gfx90a_op_V_CMP_T_I16,"V_CMP_T_I16"} ,//167 + {amdgpu_gfx90a_op_V_CMP_F_U16,"V_CMP_F_U16"} ,//168 + {amdgpu_gfx90a_op_V_CMP_LT_U16,"V_CMP_LT_U16"} ,//169 + {amdgpu_gfx90a_op_V_CMP_EQ_U16,"V_CMP_EQ_U16"} ,//170 + {amdgpu_gfx90a_op_V_CMP_LE_U16,"V_CMP_LE_U16"} ,//171 + {amdgpu_gfx90a_op_V_CMP_GT_U16,"V_CMP_GT_U16"} ,//172 + {amdgpu_gfx90a_op_V_CMP_NE_U16,"V_CMP_NE_U16"} ,//173 + {amdgpu_gfx90a_op_V_CMP_GE_U16,"V_CMP_GE_U16"} ,//174 + {amdgpu_gfx90a_op_V_CMP_T_U16,"V_CMP_T_U16"} ,//175 + {amdgpu_gfx90a_op_V_CMPX_F_I16,"V_CMPX_F_I16"} ,//176 + {amdgpu_gfx90a_op_V_CMPX_LT_I16,"V_CMPX_LT_I16"} ,//177 + {amdgpu_gfx90a_op_V_CMPX_EQ_I16,"V_CMPX_EQ_I16"} ,//178 + {amdgpu_gfx90a_op_V_CMPX_LE_I16,"V_CMPX_LE_I16"} ,//179 + {amdgpu_gfx90a_op_V_CMPX_GT_I16,"V_CMPX_GT_I16"} ,//180 + {amdgpu_gfx90a_op_V_CMPX_NE_I16,"V_CMPX_NE_I16"} ,//181 + {amdgpu_gfx90a_op_V_CMPX_GE_I16,"V_CMPX_GE_I16"} ,//182 + {amdgpu_gfx90a_op_V_CMPX_T_I16,"V_CMPX_T_I16"} ,//183 + {amdgpu_gfx90a_op_V_CMPX_F_U16,"V_CMPX_F_U16"} ,//184 + {amdgpu_gfx90a_op_V_CMPX_LT_U16,"V_CMPX_LT_U16"} ,//185 + {amdgpu_gfx90a_op_V_CMPX_EQ_U16,"V_CMPX_EQ_U16"} ,//186 + {amdgpu_gfx90a_op_V_CMPX_LE_U16,"V_CMPX_LE_U16"} ,//187 + {amdgpu_gfx90a_op_V_CMPX_GT_U16,"V_CMPX_GT_U16"} ,//188 + {amdgpu_gfx90a_op_V_CMPX_NE_U16,"V_CMPX_NE_U16"} ,//189 + {amdgpu_gfx90a_op_V_CMPX_GE_U16,"V_CMPX_GE_U16"} ,//190 + {amdgpu_gfx90a_op_V_CMPX_T_U16,"V_CMPX_T_U16"} ,//191 + {amdgpu_gfx90a_op_V_CMP_F_I32,"V_CMP_F_I32"} ,//192 + {amdgpu_gfx90a_op_V_CMP_LT_I32,"V_CMP_LT_I32"} ,//193 + {amdgpu_gfx90a_op_V_CMP_EQ_I32,"V_CMP_EQ_I32"} ,//194 + {amdgpu_gfx90a_op_V_CMP_LE_I32,"V_CMP_LE_I32"} ,//195 + {amdgpu_gfx90a_op_V_CMP_GT_I32,"V_CMP_GT_I32"} ,//196 + {amdgpu_gfx90a_op_V_CMP_NE_I32,"V_CMP_NE_I32"} ,//197 + {amdgpu_gfx90a_op_V_CMP_GE_I32,"V_CMP_GE_I32"} ,//198 + {amdgpu_gfx90a_op_V_CMP_T_I32,"V_CMP_T_I32"} ,//199 + {amdgpu_gfx90a_op_V_CMP_F_U32,"V_CMP_F_U32"} ,//200 + {amdgpu_gfx90a_op_V_CMP_LT_U32,"V_CMP_LT_U32"} ,//201 + {amdgpu_gfx90a_op_V_CMP_EQ_U32,"V_CMP_EQ_U32"} ,//202 + {amdgpu_gfx90a_op_V_CMP_LE_U32,"V_CMP_LE_U32"} ,//203 + {amdgpu_gfx90a_op_V_CMP_GT_U32,"V_CMP_GT_U32"} ,//204 + {amdgpu_gfx90a_op_V_CMP_NE_U32,"V_CMP_NE_U32"} ,//205 + {amdgpu_gfx90a_op_V_CMP_GE_U32,"V_CMP_GE_U32"} ,//206 + {amdgpu_gfx90a_op_V_CMP_T_U32,"V_CMP_T_U32"} ,//207 + {amdgpu_gfx90a_op_V_CMPX_F_I32,"V_CMPX_F_I32"} ,//208 + {amdgpu_gfx90a_op_V_CMPX_LT_I32,"V_CMPX_LT_I32"} ,//209 + {amdgpu_gfx90a_op_V_CMPX_EQ_I32,"V_CMPX_EQ_I32"} ,//210 + {amdgpu_gfx90a_op_V_CMPX_LE_I32,"V_CMPX_LE_I32"} ,//211 + {amdgpu_gfx90a_op_V_CMPX_GT_I32,"V_CMPX_GT_I32"} ,//212 + {amdgpu_gfx90a_op_V_CMPX_NE_I32,"V_CMPX_NE_I32"} ,//213 + {amdgpu_gfx90a_op_V_CMPX_GE_I32,"V_CMPX_GE_I32"} ,//214 + {amdgpu_gfx90a_op_V_CMPX_T_I32,"V_CMPX_T_I32"} ,//215 + {amdgpu_gfx90a_op_V_CMPX_F_U32,"V_CMPX_F_U32"} ,//216 + {amdgpu_gfx90a_op_V_CMPX_LT_U32,"V_CMPX_LT_U32"} ,//217 + {amdgpu_gfx90a_op_V_CMPX_EQ_U32,"V_CMPX_EQ_U32"} ,//218 + {amdgpu_gfx90a_op_V_CMPX_LE_U32,"V_CMPX_LE_U32"} ,//219 + {amdgpu_gfx90a_op_V_CMPX_GT_U32,"V_CMPX_GT_U32"} ,//220 + {amdgpu_gfx90a_op_V_CMPX_NE_U32,"V_CMPX_NE_U32"} ,//221 + {amdgpu_gfx90a_op_V_CMPX_GE_U32,"V_CMPX_GE_U32"} ,//222 + {amdgpu_gfx90a_op_V_CMPX_T_U32,"V_CMPX_T_U32"} ,//223 + {amdgpu_gfx90a_op_V_CMP_F_I64,"V_CMP_F_I64"} ,//224 + {amdgpu_gfx90a_op_V_CMP_LT_I64,"V_CMP_LT_I64"} ,//225 + {amdgpu_gfx90a_op_V_CMP_EQ_I64,"V_CMP_EQ_I64"} ,//226 + {amdgpu_gfx90a_op_V_CMP_LE_I64,"V_CMP_LE_I64"} ,//227 + {amdgpu_gfx90a_op_V_CMP_GT_I64,"V_CMP_GT_I64"} ,//228 + {amdgpu_gfx90a_op_V_CMP_NE_I64,"V_CMP_NE_I64"} ,//229 + {amdgpu_gfx90a_op_V_CMP_GE_I64,"V_CMP_GE_I64"} ,//230 + {amdgpu_gfx90a_op_V_CMP_T_I64,"V_CMP_T_I64"} ,//231 + {amdgpu_gfx90a_op_V_CMP_F_U64,"V_CMP_F_U64"} ,//232 + {amdgpu_gfx90a_op_V_CMP_LT_U64,"V_CMP_LT_U64"} ,//233 + {amdgpu_gfx90a_op_V_CMP_EQ_U64,"V_CMP_EQ_U64"} ,//234 + {amdgpu_gfx90a_op_V_CMP_LE_U64,"V_CMP_LE_U64"} ,//235 + {amdgpu_gfx90a_op_V_CMP_GT_U64,"V_CMP_GT_U64"} ,//236 + {amdgpu_gfx90a_op_V_CMP_NE_U64,"V_CMP_NE_U64"} ,//237 + {amdgpu_gfx90a_op_V_CMP_GE_U64,"V_CMP_GE_U64"} ,//238 + {amdgpu_gfx90a_op_V_CMP_T_U64,"V_CMP_T_U64"} ,//239 + {amdgpu_gfx90a_op_V_CMPX_F_I64,"V_CMPX_F_I64"} ,//240 + {amdgpu_gfx90a_op_V_CMPX_LT_I64,"V_CMPX_LT_I64"} ,//241 + {amdgpu_gfx90a_op_V_CMPX_EQ_I64,"V_CMPX_EQ_I64"} ,//242 + {amdgpu_gfx90a_op_V_CMPX_LE_I64,"V_CMPX_LE_I64"} ,//243 + {amdgpu_gfx90a_op_V_CMPX_GT_I64,"V_CMPX_GT_I64"} ,//244 + {amdgpu_gfx90a_op_V_CMPX_NE_I64,"V_CMPX_NE_I64"} ,//245 + {amdgpu_gfx90a_op_V_CMPX_GE_I64,"V_CMPX_GE_I64"} ,//246 + {amdgpu_gfx90a_op_V_CMPX_T_I64,"V_CMPX_T_I64"} ,//247 + {amdgpu_gfx90a_op_V_CMPX_F_U64,"V_CMPX_F_U64"} ,//248 + {amdgpu_gfx90a_op_V_CMPX_LT_U64,"V_CMPX_LT_U64"} ,//249 + {amdgpu_gfx90a_op_V_CMPX_EQ_U64,"V_CMPX_EQ_U64"} ,//250 + {amdgpu_gfx90a_op_V_CMPX_LE_U64,"V_CMPX_LE_U64"} ,//251 + {amdgpu_gfx90a_op_V_CMPX_GT_U64,"V_CMPX_GT_U64"} ,//252 + {amdgpu_gfx90a_op_V_CMPX_NE_U64,"V_CMPX_NE_U64"} ,//253 + {amdgpu_gfx90a_op_V_CMPX_GE_U64,"V_CMPX_GE_U64"} ,//254 + {amdgpu_gfx90a_op_V_CMPX_T_U64,"V_CMPX_T_U64"} ,//255 + }; // end ENC_VOPC_insn_table + const amdgpu_gfx90a_insn_entry ENC_VINTRP_insn_table [1] = + { + {amdgpu_gfx90a_op_S_NOP,"S_NOP"} ,//0 + }; // end ENC_VINTRP_insn_table diff --git a/instructionAPI/src/AMDGPU/gfx90a/appendOperands.C b/instructionAPI/src/AMDGPU/gfx90a/appendOperands.C new file mode 100644 index 0000000000..9ba795007b --- /dev/null +++ b/instructionAPI/src/AMDGPU/gfx90a/appendOperands.C @@ -0,0 +1,357 @@ +#include +#include "InstructionDecoder-amdgpu-gfx90a.h" + +namespace Dyninst { +namespace InstructionAPI { + void InstructionDecoder_amdgpu_gfx90a::appendOPR_SIMM4(uint64_t input, bool isRead, bool isWritten, uint32_t /*_num_elements = 1*/ , bool isImplicit /*= false*/) + { + insn_in_progress->appendOperand(Immediate::makeImmediate(Result(s8, input)),isRead,isWritten,isImplicit); + } + + void InstructionDecoder_amdgpu_gfx90a::appendOPR_SIMM8(uint64_t input, bool isRead, bool isWritten, uint32_t /*_num_elements = 1*/ , bool isImplicit /*= false*/) + { + insn_in_progress->appendOperand(Immediate::makeImmediate(Result(s8, input)),isRead,isWritten,isImplicit); + } + + void InstructionDecoder_amdgpu_gfx90a::appendOPR_SIMM16(uint64_t input, bool isRead, bool isWritten, uint32_t /*_num_elements = 1*/ , bool isImplicit /*= false*/) + { + insn_in_progress->appendOperand(Immediate::makeImmediate(Result(s16, input)),isRead,isWritten,isImplicit); + } + + void InstructionDecoder_amdgpu_gfx90a::appendOPR_SIMM32(uint64_t input, bool isRead, bool isWritten, uint32_t /*_num_elements = 1*/ , bool isImplicit /*= false*/) + { + insn_in_progress->appendOperand(Immediate::makeImmediate(Result(s32, input)),isRead,isWritten,isImplicit); + } + + void InstructionDecoder_amdgpu_gfx90a::appendOPR_WAITCNT(uint64_t input, bool isRead, bool isWritten, uint32_t /*_num_elements = 1*/ , bool isImplicit /*= false*/) + { + insn_in_progress->appendOperand(Immediate::makeImmediate(Result(s16, input)),isRead,isWritten,isImplicit); + } + + void InstructionDecoder_amdgpu_gfx90a::appendOPR_ACCVGPR(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_ACCVGPR(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_ACCVGPR(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + + void InstructionDecoder_amdgpu_gfx90a::appendOPR_DSMEM(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_DSMEM(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_DSMEM(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + + void InstructionDecoder_amdgpu_gfx90a::appendOPR_FLAT_SCRATCH(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_FLAT_SCRATCH(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + + void InstructionDecoder_amdgpu_gfx90a::appendOPR_PC(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_PC(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_PC(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + + void InstructionDecoder_amdgpu_gfx90a::appendOPR_SDST(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_SDST(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_SDST(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + + void InstructionDecoder_amdgpu_gfx90a::appendOPR_SDST_EXEC(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_SDST_EXEC(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + + void InstructionDecoder_amdgpu_gfx90a::appendOPR_SDST_M0(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_SDST_M0(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_SDST_M0(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + + void InstructionDecoder_amdgpu_gfx90a::appendOPR_SRC(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_SRC(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_SRC(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + + void InstructionDecoder_amdgpu_gfx90a::appendOPR_SRC_ACCVGPR(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_SRC_ACCVGPR(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_SRC_ACCVGPR(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + + void InstructionDecoder_amdgpu_gfx90a::appendOPR_SRC_NOLDS(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_SRC_NOLDS(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_SRC_NOLDS(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + + void InstructionDecoder_amdgpu_gfx90a::appendOPR_SRC_NOLIT(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_SRC_NOLIT(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + + void InstructionDecoder_amdgpu_gfx90a::appendOPR_SRC_SIMPLE(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_SRC_SIMPLE(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + + void InstructionDecoder_amdgpu_gfx90a::appendOPR_SRC_VGPR(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_SRC_VGPR(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_SRC_VGPR(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + + void InstructionDecoder_amdgpu_gfx90a::appendOPR_SRC_VGPR_OR_ACCVGPR(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_SRC_VGPR_OR_ACCVGPR(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + + void InstructionDecoder_amdgpu_gfx90a::appendOPR_SRC_VGPR_OR_ACCVGPR_OR_CONST(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_SRC_VGPR_OR_ACCVGPR_OR_CONST(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR_OR_CONST(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + + void InstructionDecoder_amdgpu_gfx90a::appendOPR_SREG(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_SREG(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_SREG(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + + void InstructionDecoder_amdgpu_gfx90a::appendOPR_SREG_NOVCC(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_SREG_NOVCC(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_SREG_NOVCC(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + + void InstructionDecoder_amdgpu_gfx90a::appendOPR_SSRC(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_SSRC(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_SSRC(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + + void InstructionDecoder_amdgpu_gfx90a::appendOPR_SSRC_LANESEL(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_SSRC_LANESEL(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_SSRC_LANESEL(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + + void InstructionDecoder_amdgpu_gfx90a::appendOPR_SSRC_NOLIT(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_SSRC_NOLIT(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + + void InstructionDecoder_amdgpu_gfx90a::appendOPR_SSRC_SPECIAL_SCC(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_SSRC_SPECIAL_SCC(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + + void InstructionDecoder_amdgpu_gfx90a::appendOPR_VCC(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_VCC(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_VCC(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + + void InstructionDecoder_amdgpu_gfx90a::appendOPR_VGPR(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_VGPR(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_VGPR(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + + void InstructionDecoder_amdgpu_gfx90a::appendOPR_VGPR_OR_ACCVGPR(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_VGPR_OR_ACCVGPR(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + + void InstructionDecoder_amdgpu_gfx90a::appendOPR_VGPR_OR_LDS(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_VGPR_OR_LDS(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_VGPR_OR_LDS(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + +} +} diff --git a/instructionAPI/src/AMDGPU/gfx90a/decodeOperands.C b/instructionAPI/src/AMDGPU/gfx90a/decodeOperands.C new file mode 100644 index 0000000000..b853107f5c --- /dev/null +++ b/instructionAPI/src/AMDGPU/gfx90a/decodeOperands.C @@ -0,0 +1,6550 @@ +#include "registers/AMDGPU/amdgpu_gfx90a_regs.h" +#include "InstructionDecoder-amdgpu-gfx90a.h" + +namespace Dyninst { +namespace InstructionAPI { + Expression::Ptr InstructionDecoder_amdgpu_gfx90a::decodeOPR_ACCVGPR(uint64_t input, uint32_t output_vec_len) + { + switch (input) { + case 0: return makeRegisterExpression(amdgpu_gfx90a::acc0, output_vec_len ); + case 1: return makeRegisterExpression(amdgpu_gfx90a::acc1, output_vec_len ); + case 2: return makeRegisterExpression(amdgpu_gfx90a::acc2, output_vec_len ); + case 3: return makeRegisterExpression(amdgpu_gfx90a::acc3, output_vec_len ); + case 4: return makeRegisterExpression(amdgpu_gfx90a::acc4, output_vec_len ); + case 5: return makeRegisterExpression(amdgpu_gfx90a::acc5, output_vec_len ); + case 6: return makeRegisterExpression(amdgpu_gfx90a::acc6, output_vec_len ); + case 7: return makeRegisterExpression(amdgpu_gfx90a::acc7, output_vec_len ); + case 8: return makeRegisterExpression(amdgpu_gfx90a::acc8, output_vec_len ); + case 9: return makeRegisterExpression(amdgpu_gfx90a::acc9, output_vec_len ); + case 10: return makeRegisterExpression(amdgpu_gfx90a::acc10, output_vec_len ); + case 11: return makeRegisterExpression(amdgpu_gfx90a::acc11, output_vec_len ); + case 12: return makeRegisterExpression(amdgpu_gfx90a::acc12, output_vec_len ); + case 13: return makeRegisterExpression(amdgpu_gfx90a::acc13, output_vec_len ); + case 14: return makeRegisterExpression(amdgpu_gfx90a::acc14, output_vec_len ); + case 15: return makeRegisterExpression(amdgpu_gfx90a::acc15, output_vec_len ); + case 16: return makeRegisterExpression(amdgpu_gfx90a::acc16, output_vec_len ); + case 17: return makeRegisterExpression(amdgpu_gfx90a::acc17, output_vec_len ); + case 18: return makeRegisterExpression(amdgpu_gfx90a::acc18, output_vec_len ); + case 19: return makeRegisterExpression(amdgpu_gfx90a::acc19, output_vec_len ); + case 20: return makeRegisterExpression(amdgpu_gfx90a::acc20, output_vec_len ); + case 21: return makeRegisterExpression(amdgpu_gfx90a::acc21, output_vec_len ); + case 22: return makeRegisterExpression(amdgpu_gfx90a::acc22, output_vec_len ); + case 23: return makeRegisterExpression(amdgpu_gfx90a::acc23, output_vec_len ); + case 24: return makeRegisterExpression(amdgpu_gfx90a::acc24, output_vec_len ); + case 25: return makeRegisterExpression(amdgpu_gfx90a::acc25, output_vec_len ); + case 26: return makeRegisterExpression(amdgpu_gfx90a::acc26, output_vec_len ); + case 27: return makeRegisterExpression(amdgpu_gfx90a::acc27, output_vec_len ); + case 28: return makeRegisterExpression(amdgpu_gfx90a::acc28, output_vec_len ); + case 29: return makeRegisterExpression(amdgpu_gfx90a::acc29, output_vec_len ); + case 30: return makeRegisterExpression(amdgpu_gfx90a::acc30, output_vec_len ); + case 31: return makeRegisterExpression(amdgpu_gfx90a::acc31, output_vec_len ); + case 32: return makeRegisterExpression(amdgpu_gfx90a::acc32, output_vec_len ); + case 33: return makeRegisterExpression(amdgpu_gfx90a::acc33, output_vec_len ); + case 34: return makeRegisterExpression(amdgpu_gfx90a::acc34, output_vec_len ); + case 35: return makeRegisterExpression(amdgpu_gfx90a::acc35, output_vec_len ); + case 36: return makeRegisterExpression(amdgpu_gfx90a::acc36, output_vec_len ); + case 37: return makeRegisterExpression(amdgpu_gfx90a::acc37, output_vec_len ); + case 38: return makeRegisterExpression(amdgpu_gfx90a::acc38, output_vec_len ); + case 39: return makeRegisterExpression(amdgpu_gfx90a::acc39, output_vec_len ); + case 40: return makeRegisterExpression(amdgpu_gfx90a::acc40, output_vec_len ); + case 41: return makeRegisterExpression(amdgpu_gfx90a::acc41, output_vec_len ); + case 42: return makeRegisterExpression(amdgpu_gfx90a::acc42, output_vec_len ); + case 43: return makeRegisterExpression(amdgpu_gfx90a::acc43, output_vec_len ); + case 44: return makeRegisterExpression(amdgpu_gfx90a::acc44, output_vec_len ); + case 45: return makeRegisterExpression(amdgpu_gfx90a::acc45, output_vec_len ); + case 46: return makeRegisterExpression(amdgpu_gfx90a::acc46, output_vec_len ); + case 47: return makeRegisterExpression(amdgpu_gfx90a::acc47, output_vec_len ); + case 48: return makeRegisterExpression(amdgpu_gfx90a::acc48, output_vec_len ); + case 49: return makeRegisterExpression(amdgpu_gfx90a::acc49, output_vec_len ); + case 50: return makeRegisterExpression(amdgpu_gfx90a::acc50, output_vec_len ); + case 51: return makeRegisterExpression(amdgpu_gfx90a::acc51, output_vec_len ); + case 52: return makeRegisterExpression(amdgpu_gfx90a::acc52, output_vec_len ); + case 53: return makeRegisterExpression(amdgpu_gfx90a::acc53, output_vec_len ); + case 54: return makeRegisterExpression(amdgpu_gfx90a::acc54, output_vec_len ); + case 55: return makeRegisterExpression(amdgpu_gfx90a::acc55, output_vec_len ); + case 56: return makeRegisterExpression(amdgpu_gfx90a::acc56, output_vec_len ); + case 57: return makeRegisterExpression(amdgpu_gfx90a::acc57, output_vec_len ); + case 58: return makeRegisterExpression(amdgpu_gfx90a::acc58, output_vec_len ); + case 59: return makeRegisterExpression(amdgpu_gfx90a::acc59, output_vec_len ); + case 60: return makeRegisterExpression(amdgpu_gfx90a::acc60, output_vec_len ); + case 61: return makeRegisterExpression(amdgpu_gfx90a::acc61, output_vec_len ); + case 62: return makeRegisterExpression(amdgpu_gfx90a::acc62, output_vec_len ); + case 63: return makeRegisterExpression(amdgpu_gfx90a::acc63, output_vec_len ); + case 64: return makeRegisterExpression(amdgpu_gfx90a::acc64, output_vec_len ); + case 65: return makeRegisterExpression(amdgpu_gfx90a::acc65, output_vec_len ); + case 66: return makeRegisterExpression(amdgpu_gfx90a::acc66, output_vec_len ); + case 67: return makeRegisterExpression(amdgpu_gfx90a::acc67, output_vec_len ); + case 68: return makeRegisterExpression(amdgpu_gfx90a::acc68, output_vec_len ); + case 69: return makeRegisterExpression(amdgpu_gfx90a::acc69, output_vec_len ); + case 70: return makeRegisterExpression(amdgpu_gfx90a::acc70, output_vec_len ); + case 71: return makeRegisterExpression(amdgpu_gfx90a::acc71, output_vec_len ); + case 72: return makeRegisterExpression(amdgpu_gfx90a::acc72, output_vec_len ); + case 73: return makeRegisterExpression(amdgpu_gfx90a::acc73, output_vec_len ); + case 74: return makeRegisterExpression(amdgpu_gfx90a::acc74, output_vec_len ); + case 75: return makeRegisterExpression(amdgpu_gfx90a::acc75, output_vec_len ); + case 76: return makeRegisterExpression(amdgpu_gfx90a::acc76, output_vec_len ); + case 77: return makeRegisterExpression(amdgpu_gfx90a::acc77, output_vec_len ); + case 78: return makeRegisterExpression(amdgpu_gfx90a::acc78, output_vec_len ); + case 79: return makeRegisterExpression(amdgpu_gfx90a::acc79, output_vec_len ); + case 80: return makeRegisterExpression(amdgpu_gfx90a::acc80, output_vec_len ); + case 81: return makeRegisterExpression(amdgpu_gfx90a::acc81, output_vec_len ); + case 82: return makeRegisterExpression(amdgpu_gfx90a::acc82, output_vec_len ); + case 83: return makeRegisterExpression(amdgpu_gfx90a::acc83, output_vec_len ); + case 84: return makeRegisterExpression(amdgpu_gfx90a::acc84, output_vec_len ); + case 85: return makeRegisterExpression(amdgpu_gfx90a::acc85, output_vec_len ); + case 86: return makeRegisterExpression(amdgpu_gfx90a::acc86, output_vec_len ); + case 87: return makeRegisterExpression(amdgpu_gfx90a::acc87, output_vec_len ); + case 88: return makeRegisterExpression(amdgpu_gfx90a::acc88, output_vec_len ); + case 89: return makeRegisterExpression(amdgpu_gfx90a::acc89, output_vec_len ); + case 90: return makeRegisterExpression(amdgpu_gfx90a::acc90, output_vec_len ); + case 91: return makeRegisterExpression(amdgpu_gfx90a::acc91, output_vec_len ); + case 92: return makeRegisterExpression(amdgpu_gfx90a::acc92, output_vec_len ); + case 93: return makeRegisterExpression(amdgpu_gfx90a::acc93, output_vec_len ); + case 94: return makeRegisterExpression(amdgpu_gfx90a::acc94, output_vec_len ); + case 95: return makeRegisterExpression(amdgpu_gfx90a::acc95, output_vec_len ); + case 96: return makeRegisterExpression(amdgpu_gfx90a::acc96, output_vec_len ); + case 97: return makeRegisterExpression(amdgpu_gfx90a::acc97, output_vec_len ); + case 98: return makeRegisterExpression(amdgpu_gfx90a::acc98, output_vec_len ); + case 99: return makeRegisterExpression(amdgpu_gfx90a::acc99, output_vec_len ); + case 100: return makeRegisterExpression(amdgpu_gfx90a::acc100, output_vec_len ); + case 101: return makeRegisterExpression(amdgpu_gfx90a::acc101, output_vec_len ); + case 102: return makeRegisterExpression(amdgpu_gfx90a::acc102, output_vec_len ); + case 103: return makeRegisterExpression(amdgpu_gfx90a::acc103, output_vec_len ); + case 104: return makeRegisterExpression(amdgpu_gfx90a::acc104, output_vec_len ); + case 105: return makeRegisterExpression(amdgpu_gfx90a::acc105, output_vec_len ); + case 106: return makeRegisterExpression(amdgpu_gfx90a::acc106, output_vec_len ); + case 107: return makeRegisterExpression(amdgpu_gfx90a::acc107, output_vec_len ); + case 108: return makeRegisterExpression(amdgpu_gfx90a::acc108, output_vec_len ); + case 109: return makeRegisterExpression(amdgpu_gfx90a::acc109, output_vec_len ); + case 110: return makeRegisterExpression(amdgpu_gfx90a::acc110, output_vec_len ); + case 111: return makeRegisterExpression(amdgpu_gfx90a::acc111, output_vec_len ); + case 112: return makeRegisterExpression(amdgpu_gfx90a::acc112, output_vec_len ); + case 113: return makeRegisterExpression(amdgpu_gfx90a::acc113, output_vec_len ); + case 114: return makeRegisterExpression(amdgpu_gfx90a::acc114, output_vec_len ); + case 115: return makeRegisterExpression(amdgpu_gfx90a::acc115, output_vec_len ); + case 116: return makeRegisterExpression(amdgpu_gfx90a::acc116, output_vec_len ); + case 117: return makeRegisterExpression(amdgpu_gfx90a::acc117, output_vec_len ); + case 118: return makeRegisterExpression(amdgpu_gfx90a::acc118, output_vec_len ); + case 119: return makeRegisterExpression(amdgpu_gfx90a::acc119, output_vec_len ); + case 120: return makeRegisterExpression(amdgpu_gfx90a::acc120, output_vec_len ); + case 121: return makeRegisterExpression(amdgpu_gfx90a::acc121, output_vec_len ); + case 122: return makeRegisterExpression(amdgpu_gfx90a::acc122, output_vec_len ); + case 123: return makeRegisterExpression(amdgpu_gfx90a::acc123, output_vec_len ); + case 124: return makeRegisterExpression(amdgpu_gfx90a::acc124, output_vec_len ); + case 125: return makeRegisterExpression(amdgpu_gfx90a::acc125, output_vec_len ); + case 126: return makeRegisterExpression(amdgpu_gfx90a::acc126, output_vec_len ); + case 127: return makeRegisterExpression(amdgpu_gfx90a::acc127, output_vec_len ); + case 128: return makeRegisterExpression(amdgpu_gfx90a::acc128, output_vec_len ); + case 129: return makeRegisterExpression(amdgpu_gfx90a::acc129, output_vec_len ); + case 130: return makeRegisterExpression(amdgpu_gfx90a::acc130, output_vec_len ); + case 131: return makeRegisterExpression(amdgpu_gfx90a::acc131, output_vec_len ); + case 132: return makeRegisterExpression(amdgpu_gfx90a::acc132, output_vec_len ); + case 133: return makeRegisterExpression(amdgpu_gfx90a::acc133, output_vec_len ); + case 134: return makeRegisterExpression(amdgpu_gfx90a::acc134, output_vec_len ); + case 135: return makeRegisterExpression(amdgpu_gfx90a::acc135, output_vec_len ); + case 136: return makeRegisterExpression(amdgpu_gfx90a::acc136, output_vec_len ); + case 137: return makeRegisterExpression(amdgpu_gfx90a::acc137, output_vec_len ); + case 138: return makeRegisterExpression(amdgpu_gfx90a::acc138, output_vec_len ); + case 139: return makeRegisterExpression(amdgpu_gfx90a::acc139, output_vec_len ); + case 140: return makeRegisterExpression(amdgpu_gfx90a::acc140, output_vec_len ); + case 141: return makeRegisterExpression(amdgpu_gfx90a::acc141, output_vec_len ); + case 142: return makeRegisterExpression(amdgpu_gfx90a::acc142, output_vec_len ); + case 143: return makeRegisterExpression(amdgpu_gfx90a::acc143, output_vec_len ); + case 144: return makeRegisterExpression(amdgpu_gfx90a::acc144, output_vec_len ); + case 145: return makeRegisterExpression(amdgpu_gfx90a::acc145, output_vec_len ); + case 146: return makeRegisterExpression(amdgpu_gfx90a::acc146, output_vec_len ); + case 147: return makeRegisterExpression(amdgpu_gfx90a::acc147, output_vec_len ); + case 148: return makeRegisterExpression(amdgpu_gfx90a::acc148, output_vec_len ); + case 149: return makeRegisterExpression(amdgpu_gfx90a::acc149, output_vec_len ); + case 150: return makeRegisterExpression(amdgpu_gfx90a::acc150, output_vec_len ); + case 151: return makeRegisterExpression(amdgpu_gfx90a::acc151, output_vec_len ); + case 152: return makeRegisterExpression(amdgpu_gfx90a::acc152, output_vec_len ); + case 153: return makeRegisterExpression(amdgpu_gfx90a::acc153, output_vec_len ); + case 154: return makeRegisterExpression(amdgpu_gfx90a::acc154, output_vec_len ); + case 155: return makeRegisterExpression(amdgpu_gfx90a::acc155, output_vec_len ); + case 156: return makeRegisterExpression(amdgpu_gfx90a::acc156, output_vec_len ); + case 157: return makeRegisterExpression(amdgpu_gfx90a::acc157, output_vec_len ); + case 158: return makeRegisterExpression(amdgpu_gfx90a::acc158, output_vec_len ); + case 159: return makeRegisterExpression(amdgpu_gfx90a::acc159, output_vec_len ); + case 160: return makeRegisterExpression(amdgpu_gfx90a::acc160, output_vec_len ); + case 161: return makeRegisterExpression(amdgpu_gfx90a::acc161, output_vec_len ); + case 162: return makeRegisterExpression(amdgpu_gfx90a::acc162, output_vec_len ); + case 163: return makeRegisterExpression(amdgpu_gfx90a::acc163, output_vec_len ); + case 164: return makeRegisterExpression(amdgpu_gfx90a::acc164, output_vec_len ); + case 165: return makeRegisterExpression(amdgpu_gfx90a::acc165, output_vec_len ); + case 166: return makeRegisterExpression(amdgpu_gfx90a::acc166, output_vec_len ); + case 167: return makeRegisterExpression(amdgpu_gfx90a::acc167, output_vec_len ); + case 168: return makeRegisterExpression(amdgpu_gfx90a::acc168, output_vec_len ); + case 169: return makeRegisterExpression(amdgpu_gfx90a::acc169, output_vec_len ); + case 170: return makeRegisterExpression(amdgpu_gfx90a::acc170, output_vec_len ); + case 171: return makeRegisterExpression(amdgpu_gfx90a::acc171, output_vec_len ); + case 172: return makeRegisterExpression(amdgpu_gfx90a::acc172, output_vec_len ); + case 173: return makeRegisterExpression(amdgpu_gfx90a::acc173, output_vec_len ); + case 174: return makeRegisterExpression(amdgpu_gfx90a::acc174, output_vec_len ); + case 175: return makeRegisterExpression(amdgpu_gfx90a::acc175, output_vec_len ); + case 176: return makeRegisterExpression(amdgpu_gfx90a::acc176, output_vec_len ); + case 177: return makeRegisterExpression(amdgpu_gfx90a::acc177, output_vec_len ); + case 178: return makeRegisterExpression(amdgpu_gfx90a::acc178, output_vec_len ); + case 179: return makeRegisterExpression(amdgpu_gfx90a::acc179, output_vec_len ); + case 180: return makeRegisterExpression(amdgpu_gfx90a::acc180, output_vec_len ); + case 181: return makeRegisterExpression(amdgpu_gfx90a::acc181, output_vec_len ); + case 182: return makeRegisterExpression(amdgpu_gfx90a::acc182, output_vec_len ); + case 183: return makeRegisterExpression(amdgpu_gfx90a::acc183, output_vec_len ); + case 184: return makeRegisterExpression(amdgpu_gfx90a::acc184, output_vec_len ); + case 185: return makeRegisterExpression(amdgpu_gfx90a::acc185, output_vec_len ); + case 186: return makeRegisterExpression(amdgpu_gfx90a::acc186, output_vec_len ); + case 187: return makeRegisterExpression(amdgpu_gfx90a::acc187, output_vec_len ); + case 188: return makeRegisterExpression(amdgpu_gfx90a::acc188, output_vec_len ); + case 189: return makeRegisterExpression(amdgpu_gfx90a::acc189, output_vec_len ); + case 190: return makeRegisterExpression(amdgpu_gfx90a::acc190, output_vec_len ); + case 191: return makeRegisterExpression(amdgpu_gfx90a::acc191, output_vec_len ); + case 192: return makeRegisterExpression(amdgpu_gfx90a::acc192, output_vec_len ); + case 193: return makeRegisterExpression(amdgpu_gfx90a::acc193, output_vec_len ); + case 194: return makeRegisterExpression(amdgpu_gfx90a::acc194, output_vec_len ); + case 195: return makeRegisterExpression(amdgpu_gfx90a::acc195, output_vec_len ); + case 196: return makeRegisterExpression(amdgpu_gfx90a::acc196, output_vec_len ); + case 197: return makeRegisterExpression(amdgpu_gfx90a::acc197, output_vec_len ); + case 198: return makeRegisterExpression(amdgpu_gfx90a::acc198, output_vec_len ); + case 199: return makeRegisterExpression(amdgpu_gfx90a::acc199, output_vec_len ); + case 200: return makeRegisterExpression(amdgpu_gfx90a::acc200, output_vec_len ); + case 201: return makeRegisterExpression(amdgpu_gfx90a::acc201, output_vec_len ); + case 202: return makeRegisterExpression(amdgpu_gfx90a::acc202, output_vec_len ); + case 203: return makeRegisterExpression(amdgpu_gfx90a::acc203, output_vec_len ); + case 204: return makeRegisterExpression(amdgpu_gfx90a::acc204, output_vec_len ); + case 205: return makeRegisterExpression(amdgpu_gfx90a::acc205, output_vec_len ); + case 206: return makeRegisterExpression(amdgpu_gfx90a::acc206, output_vec_len ); + case 207: return makeRegisterExpression(amdgpu_gfx90a::acc207, output_vec_len ); + case 208: return makeRegisterExpression(amdgpu_gfx90a::acc208, output_vec_len ); + case 209: return makeRegisterExpression(amdgpu_gfx90a::acc209, output_vec_len ); + case 210: return makeRegisterExpression(amdgpu_gfx90a::acc210, output_vec_len ); + case 211: return makeRegisterExpression(amdgpu_gfx90a::acc211, output_vec_len ); + case 212: return makeRegisterExpression(amdgpu_gfx90a::acc212, output_vec_len ); + case 213: return makeRegisterExpression(amdgpu_gfx90a::acc213, output_vec_len ); + case 214: return makeRegisterExpression(amdgpu_gfx90a::acc214, output_vec_len ); + case 215: return makeRegisterExpression(amdgpu_gfx90a::acc215, output_vec_len ); + case 216: return makeRegisterExpression(amdgpu_gfx90a::acc216, output_vec_len ); + case 217: return makeRegisterExpression(amdgpu_gfx90a::acc217, output_vec_len ); + case 218: return makeRegisterExpression(amdgpu_gfx90a::acc218, output_vec_len ); + case 219: return makeRegisterExpression(amdgpu_gfx90a::acc219, output_vec_len ); + case 220: return makeRegisterExpression(amdgpu_gfx90a::acc220, output_vec_len ); + case 221: return makeRegisterExpression(amdgpu_gfx90a::acc221, output_vec_len ); + case 222: return makeRegisterExpression(amdgpu_gfx90a::acc222, output_vec_len ); + case 223: return makeRegisterExpression(amdgpu_gfx90a::acc223, output_vec_len ); + case 224: return makeRegisterExpression(amdgpu_gfx90a::acc224, output_vec_len ); + case 225: return makeRegisterExpression(amdgpu_gfx90a::acc225, output_vec_len ); + case 226: return makeRegisterExpression(amdgpu_gfx90a::acc226, output_vec_len ); + case 227: return makeRegisterExpression(amdgpu_gfx90a::acc227, output_vec_len ); + case 228: return makeRegisterExpression(amdgpu_gfx90a::acc228, output_vec_len ); + case 229: return makeRegisterExpression(amdgpu_gfx90a::acc229, output_vec_len ); + case 230: return makeRegisterExpression(amdgpu_gfx90a::acc230, output_vec_len ); + case 231: return makeRegisterExpression(amdgpu_gfx90a::acc231, output_vec_len ); + case 232: return makeRegisterExpression(amdgpu_gfx90a::acc232, output_vec_len ); + case 233: return makeRegisterExpression(amdgpu_gfx90a::acc233, output_vec_len ); + case 234: return makeRegisterExpression(amdgpu_gfx90a::acc234, output_vec_len ); + case 235: return makeRegisterExpression(amdgpu_gfx90a::acc235, output_vec_len ); + case 236: return makeRegisterExpression(amdgpu_gfx90a::acc236, output_vec_len ); + case 237: return makeRegisterExpression(amdgpu_gfx90a::acc237, output_vec_len ); + case 238: return makeRegisterExpression(amdgpu_gfx90a::acc238, output_vec_len ); + case 239: return makeRegisterExpression(amdgpu_gfx90a::acc239, output_vec_len ); + case 240: return makeRegisterExpression(amdgpu_gfx90a::acc240, output_vec_len ); + case 241: return makeRegisterExpression(amdgpu_gfx90a::acc241, output_vec_len ); + case 242: return makeRegisterExpression(amdgpu_gfx90a::acc242, output_vec_len ); + case 243: return makeRegisterExpression(amdgpu_gfx90a::acc243, output_vec_len ); + case 244: return makeRegisterExpression(amdgpu_gfx90a::acc244, output_vec_len ); + case 245: return makeRegisterExpression(amdgpu_gfx90a::acc245, output_vec_len ); + case 246: return makeRegisterExpression(amdgpu_gfx90a::acc246, output_vec_len ); + case 247: return makeRegisterExpression(amdgpu_gfx90a::acc247, output_vec_len ); + case 248: return makeRegisterExpression(amdgpu_gfx90a::acc248, output_vec_len ); + case 249: return makeRegisterExpression(amdgpu_gfx90a::acc249, output_vec_len ); + case 250: return makeRegisterExpression(amdgpu_gfx90a::acc250, output_vec_len ); + case 251: return makeRegisterExpression(amdgpu_gfx90a::acc251, output_vec_len ); + case 252: return makeRegisterExpression(amdgpu_gfx90a::acc252, output_vec_len ); + case 253: return makeRegisterExpression(amdgpu_gfx90a::acc253, output_vec_len ); + case 254: return makeRegisterExpression(amdgpu_gfx90a::acc254, output_vec_len ); + case 255: return makeRegisterExpression(amdgpu_gfx90a::acc255, output_vec_len ); + case 512: return makeRegisterExpression(amdgpu_gfx90a::acc0, output_vec_len ); + case 513: return makeRegisterExpression(amdgpu_gfx90a::acc1, output_vec_len ); + case 514: return makeRegisterExpression(amdgpu_gfx90a::acc2, output_vec_len ); + case 515: return makeRegisterExpression(amdgpu_gfx90a::acc3, output_vec_len ); + case 516: return makeRegisterExpression(amdgpu_gfx90a::acc4, output_vec_len ); + case 517: return makeRegisterExpression(amdgpu_gfx90a::acc5, output_vec_len ); + case 518: return makeRegisterExpression(amdgpu_gfx90a::acc6, output_vec_len ); + case 519: return makeRegisterExpression(amdgpu_gfx90a::acc7, output_vec_len ); + case 520: return makeRegisterExpression(amdgpu_gfx90a::acc8, output_vec_len ); + case 521: return makeRegisterExpression(amdgpu_gfx90a::acc9, output_vec_len ); + case 522: return makeRegisterExpression(amdgpu_gfx90a::acc10, output_vec_len ); + case 523: return makeRegisterExpression(amdgpu_gfx90a::acc11, output_vec_len ); + case 524: return makeRegisterExpression(amdgpu_gfx90a::acc12, output_vec_len ); + case 525: return makeRegisterExpression(amdgpu_gfx90a::acc13, output_vec_len ); + case 526: return makeRegisterExpression(amdgpu_gfx90a::acc14, output_vec_len ); + case 527: return makeRegisterExpression(amdgpu_gfx90a::acc15, output_vec_len ); + case 528: return makeRegisterExpression(amdgpu_gfx90a::acc16, output_vec_len ); + case 529: return makeRegisterExpression(amdgpu_gfx90a::acc17, output_vec_len ); + case 530: return makeRegisterExpression(amdgpu_gfx90a::acc18, output_vec_len ); + case 531: return makeRegisterExpression(amdgpu_gfx90a::acc19, output_vec_len ); + case 532: return makeRegisterExpression(amdgpu_gfx90a::acc20, output_vec_len ); + case 533: return makeRegisterExpression(amdgpu_gfx90a::acc21, output_vec_len ); + case 534: return makeRegisterExpression(amdgpu_gfx90a::acc22, output_vec_len ); + case 535: return makeRegisterExpression(amdgpu_gfx90a::acc23, output_vec_len ); + case 536: return makeRegisterExpression(amdgpu_gfx90a::acc24, output_vec_len ); + case 537: return makeRegisterExpression(amdgpu_gfx90a::acc25, output_vec_len ); + case 538: return makeRegisterExpression(amdgpu_gfx90a::acc26, output_vec_len ); + case 539: return makeRegisterExpression(amdgpu_gfx90a::acc27, output_vec_len ); + case 540: return makeRegisterExpression(amdgpu_gfx90a::acc28, output_vec_len ); + case 541: return makeRegisterExpression(amdgpu_gfx90a::acc29, output_vec_len ); + case 542: return makeRegisterExpression(amdgpu_gfx90a::acc30, output_vec_len ); + case 543: return makeRegisterExpression(amdgpu_gfx90a::acc31, output_vec_len ); + case 544: return makeRegisterExpression(amdgpu_gfx90a::acc32, output_vec_len ); + case 545: return makeRegisterExpression(amdgpu_gfx90a::acc33, output_vec_len ); + case 546: return makeRegisterExpression(amdgpu_gfx90a::acc34, output_vec_len ); + case 547: return makeRegisterExpression(amdgpu_gfx90a::acc35, output_vec_len ); + case 548: return makeRegisterExpression(amdgpu_gfx90a::acc36, output_vec_len ); + case 549: return makeRegisterExpression(amdgpu_gfx90a::acc37, output_vec_len ); + case 550: return makeRegisterExpression(amdgpu_gfx90a::acc38, output_vec_len ); + case 551: return makeRegisterExpression(amdgpu_gfx90a::acc39, output_vec_len ); + case 552: return makeRegisterExpression(amdgpu_gfx90a::acc40, output_vec_len ); + case 553: return makeRegisterExpression(amdgpu_gfx90a::acc41, output_vec_len ); + case 554: return makeRegisterExpression(amdgpu_gfx90a::acc42, output_vec_len ); + case 555: return makeRegisterExpression(amdgpu_gfx90a::acc43, output_vec_len ); + case 556: return makeRegisterExpression(amdgpu_gfx90a::acc44, output_vec_len ); + case 557: return makeRegisterExpression(amdgpu_gfx90a::acc45, output_vec_len ); + case 558: return makeRegisterExpression(amdgpu_gfx90a::acc46, output_vec_len ); + case 559: return makeRegisterExpression(amdgpu_gfx90a::acc47, output_vec_len ); + case 560: return makeRegisterExpression(amdgpu_gfx90a::acc48, output_vec_len ); + case 561: return makeRegisterExpression(amdgpu_gfx90a::acc49, output_vec_len ); + case 562: return makeRegisterExpression(amdgpu_gfx90a::acc50, output_vec_len ); + case 563: return makeRegisterExpression(amdgpu_gfx90a::acc51, output_vec_len ); + case 564: return makeRegisterExpression(amdgpu_gfx90a::acc52, output_vec_len ); + case 565: return makeRegisterExpression(amdgpu_gfx90a::acc53, output_vec_len ); + case 566: return makeRegisterExpression(amdgpu_gfx90a::acc54, output_vec_len ); + case 567: return makeRegisterExpression(amdgpu_gfx90a::acc55, output_vec_len ); + case 568: return makeRegisterExpression(amdgpu_gfx90a::acc56, output_vec_len ); + case 569: return makeRegisterExpression(amdgpu_gfx90a::acc57, output_vec_len ); + case 570: return makeRegisterExpression(amdgpu_gfx90a::acc58, output_vec_len ); + case 571: return makeRegisterExpression(amdgpu_gfx90a::acc59, output_vec_len ); + case 572: return makeRegisterExpression(amdgpu_gfx90a::acc60, output_vec_len ); + case 573: return makeRegisterExpression(amdgpu_gfx90a::acc61, output_vec_len ); + case 574: return makeRegisterExpression(amdgpu_gfx90a::acc62, output_vec_len ); + case 575: return makeRegisterExpression(amdgpu_gfx90a::acc63, output_vec_len ); + case 576: return makeRegisterExpression(amdgpu_gfx90a::acc64, output_vec_len ); + case 577: return makeRegisterExpression(amdgpu_gfx90a::acc65, output_vec_len ); + case 578: return makeRegisterExpression(amdgpu_gfx90a::acc66, output_vec_len ); + case 579: return makeRegisterExpression(amdgpu_gfx90a::acc67, output_vec_len ); + case 580: return makeRegisterExpression(amdgpu_gfx90a::acc68, output_vec_len ); + case 581: return makeRegisterExpression(amdgpu_gfx90a::acc69, output_vec_len ); + case 582: return makeRegisterExpression(amdgpu_gfx90a::acc70, output_vec_len ); + case 583: return makeRegisterExpression(amdgpu_gfx90a::acc71, output_vec_len ); + case 584: return makeRegisterExpression(amdgpu_gfx90a::acc72, output_vec_len ); + case 585: return makeRegisterExpression(amdgpu_gfx90a::acc73, output_vec_len ); + case 586: return makeRegisterExpression(amdgpu_gfx90a::acc74, output_vec_len ); + case 587: return makeRegisterExpression(amdgpu_gfx90a::acc75, output_vec_len ); + case 588: return makeRegisterExpression(amdgpu_gfx90a::acc76, output_vec_len ); + case 589: return makeRegisterExpression(amdgpu_gfx90a::acc77, output_vec_len ); + case 590: return makeRegisterExpression(amdgpu_gfx90a::acc78, output_vec_len ); + case 591: return makeRegisterExpression(amdgpu_gfx90a::acc79, output_vec_len ); + case 592: return makeRegisterExpression(amdgpu_gfx90a::acc80, output_vec_len ); + case 593: return makeRegisterExpression(amdgpu_gfx90a::acc81, output_vec_len ); + case 594: return makeRegisterExpression(amdgpu_gfx90a::acc82, output_vec_len ); + case 595: return makeRegisterExpression(amdgpu_gfx90a::acc83, output_vec_len ); + case 596: return makeRegisterExpression(amdgpu_gfx90a::acc84, output_vec_len ); + case 597: return makeRegisterExpression(amdgpu_gfx90a::acc85, output_vec_len ); + case 598: return makeRegisterExpression(amdgpu_gfx90a::acc86, output_vec_len ); + case 599: return makeRegisterExpression(amdgpu_gfx90a::acc87, output_vec_len ); + case 600: return makeRegisterExpression(amdgpu_gfx90a::acc88, output_vec_len ); + case 601: return makeRegisterExpression(amdgpu_gfx90a::acc89, output_vec_len ); + case 602: return makeRegisterExpression(amdgpu_gfx90a::acc90, output_vec_len ); + case 603: return makeRegisterExpression(amdgpu_gfx90a::acc91, output_vec_len ); + case 604: return makeRegisterExpression(amdgpu_gfx90a::acc92, output_vec_len ); + case 605: return makeRegisterExpression(amdgpu_gfx90a::acc93, output_vec_len ); + case 606: return makeRegisterExpression(amdgpu_gfx90a::acc94, output_vec_len ); + case 607: return makeRegisterExpression(amdgpu_gfx90a::acc95, output_vec_len ); + case 608: return makeRegisterExpression(amdgpu_gfx90a::acc96, output_vec_len ); + case 609: return makeRegisterExpression(amdgpu_gfx90a::acc97, output_vec_len ); + case 610: return makeRegisterExpression(amdgpu_gfx90a::acc98, output_vec_len ); + case 611: return makeRegisterExpression(amdgpu_gfx90a::acc99, output_vec_len ); + case 612: return makeRegisterExpression(amdgpu_gfx90a::acc100, output_vec_len ); + case 613: return makeRegisterExpression(amdgpu_gfx90a::acc101, output_vec_len ); + case 614: return makeRegisterExpression(amdgpu_gfx90a::acc102, output_vec_len ); + case 615: return makeRegisterExpression(amdgpu_gfx90a::acc103, output_vec_len ); + case 616: return makeRegisterExpression(amdgpu_gfx90a::acc104, output_vec_len ); + case 617: return makeRegisterExpression(amdgpu_gfx90a::acc105, output_vec_len ); + case 618: return makeRegisterExpression(amdgpu_gfx90a::acc106, output_vec_len ); + case 619: return makeRegisterExpression(amdgpu_gfx90a::acc107, output_vec_len ); + case 620: return makeRegisterExpression(amdgpu_gfx90a::acc108, output_vec_len ); + case 621: return makeRegisterExpression(amdgpu_gfx90a::acc109, output_vec_len ); + case 622: return makeRegisterExpression(amdgpu_gfx90a::acc110, output_vec_len ); + case 623: return makeRegisterExpression(amdgpu_gfx90a::acc111, output_vec_len ); + case 624: return makeRegisterExpression(amdgpu_gfx90a::acc112, output_vec_len ); + case 625: return makeRegisterExpression(amdgpu_gfx90a::acc113, output_vec_len ); + case 626: return makeRegisterExpression(amdgpu_gfx90a::acc114, output_vec_len ); + case 627: return makeRegisterExpression(amdgpu_gfx90a::acc115, output_vec_len ); + case 628: return makeRegisterExpression(amdgpu_gfx90a::acc116, output_vec_len ); + case 629: return makeRegisterExpression(amdgpu_gfx90a::acc117, output_vec_len ); + case 630: return makeRegisterExpression(amdgpu_gfx90a::acc118, output_vec_len ); + case 631: return makeRegisterExpression(amdgpu_gfx90a::acc119, output_vec_len ); + case 632: return makeRegisterExpression(amdgpu_gfx90a::acc120, output_vec_len ); + case 633: return makeRegisterExpression(amdgpu_gfx90a::acc121, output_vec_len ); + case 634: return makeRegisterExpression(amdgpu_gfx90a::acc122, output_vec_len ); + case 635: return makeRegisterExpression(amdgpu_gfx90a::acc123, output_vec_len ); + case 636: return makeRegisterExpression(amdgpu_gfx90a::acc124, output_vec_len ); + case 637: return makeRegisterExpression(amdgpu_gfx90a::acc125, output_vec_len ); + case 638: return makeRegisterExpression(amdgpu_gfx90a::acc126, output_vec_len ); + case 639: return makeRegisterExpression(amdgpu_gfx90a::acc127, output_vec_len ); + case 640: return makeRegisterExpression(amdgpu_gfx90a::acc128, output_vec_len ); + case 641: return makeRegisterExpression(amdgpu_gfx90a::acc129, output_vec_len ); + case 642: return makeRegisterExpression(amdgpu_gfx90a::acc130, output_vec_len ); + case 643: return makeRegisterExpression(amdgpu_gfx90a::acc131, output_vec_len ); + case 644: return makeRegisterExpression(amdgpu_gfx90a::acc132, output_vec_len ); + case 645: return makeRegisterExpression(amdgpu_gfx90a::acc133, output_vec_len ); + case 646: return makeRegisterExpression(amdgpu_gfx90a::acc134, output_vec_len ); + case 647: return makeRegisterExpression(amdgpu_gfx90a::acc135, output_vec_len ); + case 648: return makeRegisterExpression(amdgpu_gfx90a::acc136, output_vec_len ); + case 649: return makeRegisterExpression(amdgpu_gfx90a::acc137, output_vec_len ); + case 650: return makeRegisterExpression(amdgpu_gfx90a::acc138, output_vec_len ); + case 651: return makeRegisterExpression(amdgpu_gfx90a::acc139, output_vec_len ); + case 652: return makeRegisterExpression(amdgpu_gfx90a::acc140, output_vec_len ); + case 653: return makeRegisterExpression(amdgpu_gfx90a::acc141, output_vec_len ); + case 654: return makeRegisterExpression(amdgpu_gfx90a::acc142, output_vec_len ); + case 655: return makeRegisterExpression(amdgpu_gfx90a::acc143, output_vec_len ); + case 656: return makeRegisterExpression(amdgpu_gfx90a::acc144, output_vec_len ); + case 657: return makeRegisterExpression(amdgpu_gfx90a::acc145, output_vec_len ); + case 658: return makeRegisterExpression(amdgpu_gfx90a::acc146, output_vec_len ); + case 659: return makeRegisterExpression(amdgpu_gfx90a::acc147, output_vec_len ); + case 660: return makeRegisterExpression(amdgpu_gfx90a::acc148, output_vec_len ); + case 661: return makeRegisterExpression(amdgpu_gfx90a::acc149, output_vec_len ); + case 662: return makeRegisterExpression(amdgpu_gfx90a::acc150, output_vec_len ); + case 663: return makeRegisterExpression(amdgpu_gfx90a::acc151, output_vec_len ); + case 664: return makeRegisterExpression(amdgpu_gfx90a::acc152, output_vec_len ); + case 665: return makeRegisterExpression(amdgpu_gfx90a::acc153, output_vec_len ); + case 666: return makeRegisterExpression(amdgpu_gfx90a::acc154, output_vec_len ); + case 667: return makeRegisterExpression(amdgpu_gfx90a::acc155, output_vec_len ); + case 668: return makeRegisterExpression(amdgpu_gfx90a::acc156, output_vec_len ); + case 669: return makeRegisterExpression(amdgpu_gfx90a::acc157, output_vec_len ); + case 670: return makeRegisterExpression(amdgpu_gfx90a::acc158, output_vec_len ); + case 671: return makeRegisterExpression(amdgpu_gfx90a::acc159, output_vec_len ); + case 672: return makeRegisterExpression(amdgpu_gfx90a::acc160, output_vec_len ); + case 673: return makeRegisterExpression(amdgpu_gfx90a::acc161, output_vec_len ); + case 674: return makeRegisterExpression(amdgpu_gfx90a::acc162, output_vec_len ); + case 675: return makeRegisterExpression(amdgpu_gfx90a::acc163, output_vec_len ); + case 676: return makeRegisterExpression(amdgpu_gfx90a::acc164, output_vec_len ); + case 677: return makeRegisterExpression(amdgpu_gfx90a::acc165, output_vec_len ); + case 678: return makeRegisterExpression(amdgpu_gfx90a::acc166, output_vec_len ); + case 679: return makeRegisterExpression(amdgpu_gfx90a::acc167, output_vec_len ); + case 680: return makeRegisterExpression(amdgpu_gfx90a::acc168, output_vec_len ); + case 681: return makeRegisterExpression(amdgpu_gfx90a::acc169, output_vec_len ); + case 682: return makeRegisterExpression(amdgpu_gfx90a::acc170, output_vec_len ); + case 683: return makeRegisterExpression(amdgpu_gfx90a::acc171, output_vec_len ); + case 684: return makeRegisterExpression(amdgpu_gfx90a::acc172, output_vec_len ); + case 685: return makeRegisterExpression(amdgpu_gfx90a::acc173, output_vec_len ); + case 686: return makeRegisterExpression(amdgpu_gfx90a::acc174, output_vec_len ); + case 687: return makeRegisterExpression(amdgpu_gfx90a::acc175, output_vec_len ); + case 688: return makeRegisterExpression(amdgpu_gfx90a::acc176, output_vec_len ); + case 689: return makeRegisterExpression(amdgpu_gfx90a::acc177, output_vec_len ); + case 690: return makeRegisterExpression(amdgpu_gfx90a::acc178, output_vec_len ); + case 691: return makeRegisterExpression(amdgpu_gfx90a::acc179, output_vec_len ); + case 692: return makeRegisterExpression(amdgpu_gfx90a::acc180, output_vec_len ); + case 693: return makeRegisterExpression(amdgpu_gfx90a::acc181, output_vec_len ); + case 694: return makeRegisterExpression(amdgpu_gfx90a::acc182, output_vec_len ); + case 695: return makeRegisterExpression(amdgpu_gfx90a::acc183, output_vec_len ); + case 696: return makeRegisterExpression(amdgpu_gfx90a::acc184, output_vec_len ); + case 697: return makeRegisterExpression(amdgpu_gfx90a::acc185, output_vec_len ); + case 698: return makeRegisterExpression(amdgpu_gfx90a::acc186, output_vec_len ); + case 699: return makeRegisterExpression(amdgpu_gfx90a::acc187, output_vec_len ); + case 700: return makeRegisterExpression(amdgpu_gfx90a::acc188, output_vec_len ); + case 701: return makeRegisterExpression(amdgpu_gfx90a::acc189, output_vec_len ); + case 702: return makeRegisterExpression(amdgpu_gfx90a::acc190, output_vec_len ); + case 703: return makeRegisterExpression(amdgpu_gfx90a::acc191, output_vec_len ); + case 704: return makeRegisterExpression(amdgpu_gfx90a::acc192, output_vec_len ); + case 705: return makeRegisterExpression(amdgpu_gfx90a::acc193, output_vec_len ); + case 706: return makeRegisterExpression(amdgpu_gfx90a::acc194, output_vec_len ); + case 707: return makeRegisterExpression(amdgpu_gfx90a::acc195, output_vec_len ); + case 708: return makeRegisterExpression(amdgpu_gfx90a::acc196, output_vec_len ); + case 709: return makeRegisterExpression(amdgpu_gfx90a::acc197, output_vec_len ); + case 710: return makeRegisterExpression(amdgpu_gfx90a::acc198, output_vec_len ); + case 711: return makeRegisterExpression(amdgpu_gfx90a::acc199, output_vec_len ); + case 712: return makeRegisterExpression(amdgpu_gfx90a::acc200, output_vec_len ); + case 713: return makeRegisterExpression(amdgpu_gfx90a::acc201, output_vec_len ); + case 714: return makeRegisterExpression(amdgpu_gfx90a::acc202, output_vec_len ); + case 715: return makeRegisterExpression(amdgpu_gfx90a::acc203, output_vec_len ); + case 716: return makeRegisterExpression(amdgpu_gfx90a::acc204, output_vec_len ); + case 717: return makeRegisterExpression(amdgpu_gfx90a::acc205, output_vec_len ); + case 718: return makeRegisterExpression(amdgpu_gfx90a::acc206, output_vec_len ); + case 719: return makeRegisterExpression(amdgpu_gfx90a::acc207, output_vec_len ); + case 720: return makeRegisterExpression(amdgpu_gfx90a::acc208, output_vec_len ); + case 721: return makeRegisterExpression(amdgpu_gfx90a::acc209, output_vec_len ); + case 722: return makeRegisterExpression(amdgpu_gfx90a::acc210, output_vec_len ); + case 723: return makeRegisterExpression(amdgpu_gfx90a::acc211, output_vec_len ); + case 724: return makeRegisterExpression(amdgpu_gfx90a::acc212, output_vec_len ); + case 725: return makeRegisterExpression(amdgpu_gfx90a::acc213, output_vec_len ); + case 726: return makeRegisterExpression(amdgpu_gfx90a::acc214, output_vec_len ); + case 727: return makeRegisterExpression(amdgpu_gfx90a::acc215, output_vec_len ); + case 728: return makeRegisterExpression(amdgpu_gfx90a::acc216, output_vec_len ); + case 729: return makeRegisterExpression(amdgpu_gfx90a::acc217, output_vec_len ); + case 730: return makeRegisterExpression(amdgpu_gfx90a::acc218, output_vec_len ); + case 731: return makeRegisterExpression(amdgpu_gfx90a::acc219, output_vec_len ); + case 732: return makeRegisterExpression(amdgpu_gfx90a::acc220, output_vec_len ); + case 733: return makeRegisterExpression(amdgpu_gfx90a::acc221, output_vec_len ); + case 734: return makeRegisterExpression(amdgpu_gfx90a::acc222, output_vec_len ); + case 735: return makeRegisterExpression(amdgpu_gfx90a::acc223, output_vec_len ); + case 736: return makeRegisterExpression(amdgpu_gfx90a::acc224, output_vec_len ); + case 737: return makeRegisterExpression(amdgpu_gfx90a::acc225, output_vec_len ); + case 738: return makeRegisterExpression(amdgpu_gfx90a::acc226, output_vec_len ); + case 739: return makeRegisterExpression(amdgpu_gfx90a::acc227, output_vec_len ); + case 740: return makeRegisterExpression(amdgpu_gfx90a::acc228, output_vec_len ); + case 741: return makeRegisterExpression(amdgpu_gfx90a::acc229, output_vec_len ); + case 742: return makeRegisterExpression(amdgpu_gfx90a::acc230, output_vec_len ); + case 743: return makeRegisterExpression(amdgpu_gfx90a::acc231, output_vec_len ); + case 744: return makeRegisterExpression(amdgpu_gfx90a::acc232, output_vec_len ); + case 745: return makeRegisterExpression(amdgpu_gfx90a::acc233, output_vec_len ); + case 746: return makeRegisterExpression(amdgpu_gfx90a::acc234, output_vec_len ); + case 747: return makeRegisterExpression(amdgpu_gfx90a::acc235, output_vec_len ); + case 748: return makeRegisterExpression(amdgpu_gfx90a::acc236, output_vec_len ); + case 749: return makeRegisterExpression(amdgpu_gfx90a::acc237, output_vec_len ); + case 750: return makeRegisterExpression(amdgpu_gfx90a::acc238, output_vec_len ); + case 751: return makeRegisterExpression(amdgpu_gfx90a::acc239, output_vec_len ); + case 752: return makeRegisterExpression(amdgpu_gfx90a::acc240, output_vec_len ); + case 753: return makeRegisterExpression(amdgpu_gfx90a::acc241, output_vec_len ); + case 754: return makeRegisterExpression(amdgpu_gfx90a::acc242, output_vec_len ); + case 755: return makeRegisterExpression(amdgpu_gfx90a::acc243, output_vec_len ); + case 756: return makeRegisterExpression(amdgpu_gfx90a::acc244, output_vec_len ); + case 757: return makeRegisterExpression(amdgpu_gfx90a::acc245, output_vec_len ); + case 758: return makeRegisterExpression(amdgpu_gfx90a::acc246, output_vec_len ); + case 759: return makeRegisterExpression(amdgpu_gfx90a::acc247, output_vec_len ); + case 760: return makeRegisterExpression(amdgpu_gfx90a::acc248, output_vec_len ); + case 761: return makeRegisterExpression(amdgpu_gfx90a::acc249, output_vec_len ); + case 762: return makeRegisterExpression(amdgpu_gfx90a::acc250, output_vec_len ); + case 763: return makeRegisterExpression(amdgpu_gfx90a::acc251, output_vec_len ); + case 764: return makeRegisterExpression(amdgpu_gfx90a::acc252, output_vec_len ); + case 765: return makeRegisterExpression(amdgpu_gfx90a::acc253, output_vec_len ); + case 766: return makeRegisterExpression(amdgpu_gfx90a::acc254, output_vec_len ); + case 767: return makeRegisterExpression(amdgpu_gfx90a::acc255, output_vec_len ); + default: return makeRegisterExpression(amdgpu_gfx90a::invalid); + } + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx90a::decodeOPR_DSMEM(uint64_t input, uint32_t output_vec_len) + { + switch (input) { + case 0: return makeRegisterExpression(amdgpu_gfx90a::dsmem, output_vec_len ); + default: return makeRegisterExpression(amdgpu_gfx90a::invalid); + } + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx90a::decodeOPR_FLAT_SCRATCH(uint64_t input, uint32_t output_vec_len) + { + switch (input) { + case 0: return makeRegisterExpression(amdgpu_gfx90a::flat_scratch_all, output_vec_len ); + default: return makeRegisterExpression(amdgpu_gfx90a::invalid); + } + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx90a::decodeOPR_PC(uint64_t input, uint32_t ) + { + switch (input) { + case 0: return makeRegisterExpression(amdgpu_gfx90a::pc_all); + default: return makeRegisterExpression(amdgpu_gfx90a::invalid); + } + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx90a::decodeOPR_SDST(uint64_t input, uint32_t output_vec_len) + { + switch (input) { + case 0: return makeRegisterExpression(amdgpu_gfx90a::s0, output_vec_len ); + case 1: return makeRegisterExpression(amdgpu_gfx90a::s1, output_vec_len ); + case 2: return makeRegisterExpression(amdgpu_gfx90a::s2, output_vec_len ); + case 3: return makeRegisterExpression(amdgpu_gfx90a::s3, output_vec_len ); + case 4: return makeRegisterExpression(amdgpu_gfx90a::s4, output_vec_len ); + case 5: return makeRegisterExpression(amdgpu_gfx90a::s5, output_vec_len ); + case 6: return makeRegisterExpression(amdgpu_gfx90a::s6, output_vec_len ); + case 7: return makeRegisterExpression(amdgpu_gfx90a::s7, output_vec_len ); + case 8: return makeRegisterExpression(amdgpu_gfx90a::s8, output_vec_len ); + case 9: return makeRegisterExpression(amdgpu_gfx90a::s9, output_vec_len ); + case 10: return makeRegisterExpression(amdgpu_gfx90a::s10, output_vec_len ); + case 11: return makeRegisterExpression(amdgpu_gfx90a::s11, output_vec_len ); + case 12: return makeRegisterExpression(amdgpu_gfx90a::s12, output_vec_len ); + case 13: return makeRegisterExpression(amdgpu_gfx90a::s13, output_vec_len ); + case 14: return makeRegisterExpression(amdgpu_gfx90a::s14, output_vec_len ); + case 15: return makeRegisterExpression(amdgpu_gfx90a::s15, output_vec_len ); + case 16: return makeRegisterExpression(amdgpu_gfx90a::s16, output_vec_len ); + case 17: return makeRegisterExpression(amdgpu_gfx90a::s17, output_vec_len ); + case 18: return makeRegisterExpression(amdgpu_gfx90a::s18, output_vec_len ); + case 19: return makeRegisterExpression(amdgpu_gfx90a::s19, output_vec_len ); + case 20: return makeRegisterExpression(amdgpu_gfx90a::s20, output_vec_len ); + case 21: return makeRegisterExpression(amdgpu_gfx90a::s21, output_vec_len ); + case 22: return makeRegisterExpression(amdgpu_gfx90a::s22, output_vec_len ); + case 23: return makeRegisterExpression(amdgpu_gfx90a::s23, output_vec_len ); + case 24: return makeRegisterExpression(amdgpu_gfx90a::s24, output_vec_len ); + case 25: return makeRegisterExpression(amdgpu_gfx90a::s25, output_vec_len ); + case 26: return makeRegisterExpression(amdgpu_gfx90a::s26, output_vec_len ); + case 27: return makeRegisterExpression(amdgpu_gfx90a::s27, output_vec_len ); + case 28: return makeRegisterExpression(amdgpu_gfx90a::s28, output_vec_len ); + case 29: return makeRegisterExpression(amdgpu_gfx90a::s29, output_vec_len ); + case 30: return makeRegisterExpression(amdgpu_gfx90a::s30, output_vec_len ); + case 31: return makeRegisterExpression(amdgpu_gfx90a::s31, output_vec_len ); + case 32: return makeRegisterExpression(amdgpu_gfx90a::s32, output_vec_len ); + case 33: return makeRegisterExpression(amdgpu_gfx90a::s33, output_vec_len ); + case 34: return makeRegisterExpression(amdgpu_gfx90a::s34, output_vec_len ); + case 35: return makeRegisterExpression(amdgpu_gfx90a::s35, output_vec_len ); + case 36: return makeRegisterExpression(amdgpu_gfx90a::s36, output_vec_len ); + case 37: return makeRegisterExpression(amdgpu_gfx90a::s37, output_vec_len ); + case 38: return makeRegisterExpression(amdgpu_gfx90a::s38, output_vec_len ); + case 39: return makeRegisterExpression(amdgpu_gfx90a::s39, output_vec_len ); + case 40: return makeRegisterExpression(amdgpu_gfx90a::s40, output_vec_len ); + case 41: return makeRegisterExpression(amdgpu_gfx90a::s41, output_vec_len ); + case 42: return makeRegisterExpression(amdgpu_gfx90a::s42, output_vec_len ); + case 43: return makeRegisterExpression(amdgpu_gfx90a::s43, output_vec_len ); + case 44: return makeRegisterExpression(amdgpu_gfx90a::s44, output_vec_len ); + case 45: return makeRegisterExpression(amdgpu_gfx90a::s45, output_vec_len ); + case 46: return makeRegisterExpression(amdgpu_gfx90a::s46, output_vec_len ); + case 47: return makeRegisterExpression(amdgpu_gfx90a::s47, output_vec_len ); + case 48: return makeRegisterExpression(amdgpu_gfx90a::s48, output_vec_len ); + case 49: return makeRegisterExpression(amdgpu_gfx90a::s49, output_vec_len ); + case 50: return makeRegisterExpression(amdgpu_gfx90a::s50, output_vec_len ); + case 51: return makeRegisterExpression(amdgpu_gfx90a::s51, output_vec_len ); + case 52: return makeRegisterExpression(amdgpu_gfx90a::s52, output_vec_len ); + case 53: return makeRegisterExpression(amdgpu_gfx90a::s53, output_vec_len ); + case 54: return makeRegisterExpression(amdgpu_gfx90a::s54, output_vec_len ); + case 55: return makeRegisterExpression(amdgpu_gfx90a::s55, output_vec_len ); + case 56: return makeRegisterExpression(amdgpu_gfx90a::s56, output_vec_len ); + case 57: return makeRegisterExpression(amdgpu_gfx90a::s57, output_vec_len ); + case 58: return makeRegisterExpression(amdgpu_gfx90a::s58, output_vec_len ); + case 59: return makeRegisterExpression(amdgpu_gfx90a::s59, output_vec_len ); + case 60: return makeRegisterExpression(amdgpu_gfx90a::s60, output_vec_len ); + case 61: return makeRegisterExpression(amdgpu_gfx90a::s61, output_vec_len ); + case 62: return makeRegisterExpression(amdgpu_gfx90a::s62, output_vec_len ); + case 63: return makeRegisterExpression(amdgpu_gfx90a::s63, output_vec_len ); + case 64: return makeRegisterExpression(amdgpu_gfx90a::s64, output_vec_len ); + case 65: return makeRegisterExpression(amdgpu_gfx90a::s65, output_vec_len ); + case 66: return makeRegisterExpression(amdgpu_gfx90a::s66, output_vec_len ); + case 67: return makeRegisterExpression(amdgpu_gfx90a::s67, output_vec_len ); + case 68: return makeRegisterExpression(amdgpu_gfx90a::s68, output_vec_len ); + case 69: return makeRegisterExpression(amdgpu_gfx90a::s69, output_vec_len ); + case 70: return makeRegisterExpression(amdgpu_gfx90a::s70, output_vec_len ); + case 71: return makeRegisterExpression(amdgpu_gfx90a::s71, output_vec_len ); + case 72: return makeRegisterExpression(amdgpu_gfx90a::s72, output_vec_len ); + case 73: return makeRegisterExpression(amdgpu_gfx90a::s73, output_vec_len ); + case 74: return makeRegisterExpression(amdgpu_gfx90a::s74, output_vec_len ); + case 75: return makeRegisterExpression(amdgpu_gfx90a::s75, output_vec_len ); + case 76: return makeRegisterExpression(amdgpu_gfx90a::s76, output_vec_len ); + case 77: return makeRegisterExpression(amdgpu_gfx90a::s77, output_vec_len ); + case 78: return makeRegisterExpression(amdgpu_gfx90a::s78, output_vec_len ); + case 79: return makeRegisterExpression(amdgpu_gfx90a::s79, output_vec_len ); + case 80: return makeRegisterExpression(amdgpu_gfx90a::s80, output_vec_len ); + case 81: return makeRegisterExpression(amdgpu_gfx90a::s81, output_vec_len ); + case 82: return makeRegisterExpression(amdgpu_gfx90a::s82, output_vec_len ); + case 83: return makeRegisterExpression(amdgpu_gfx90a::s83, output_vec_len ); + case 84: return makeRegisterExpression(amdgpu_gfx90a::s84, output_vec_len ); + case 85: return makeRegisterExpression(amdgpu_gfx90a::s85, output_vec_len ); + case 86: return makeRegisterExpression(amdgpu_gfx90a::s86, output_vec_len ); + case 87: return makeRegisterExpression(amdgpu_gfx90a::s87, output_vec_len ); + case 88: return makeRegisterExpression(amdgpu_gfx90a::s88, output_vec_len ); + case 89: return makeRegisterExpression(amdgpu_gfx90a::s89, output_vec_len ); + case 90: return makeRegisterExpression(amdgpu_gfx90a::s90, output_vec_len ); + case 91: return makeRegisterExpression(amdgpu_gfx90a::s91, output_vec_len ); + case 92: return makeRegisterExpression(amdgpu_gfx90a::s92, output_vec_len ); + case 93: return makeRegisterExpression(amdgpu_gfx90a::s93, output_vec_len ); + case 94: return makeRegisterExpression(amdgpu_gfx90a::s94, output_vec_len ); + case 95: return makeRegisterExpression(amdgpu_gfx90a::s95, output_vec_len ); + case 96: return makeRegisterExpression(amdgpu_gfx90a::s96, output_vec_len ); + case 97: return makeRegisterExpression(amdgpu_gfx90a::s97, output_vec_len ); + case 98: return makeRegisterExpression(amdgpu_gfx90a::s98, output_vec_len ); + case 99: return makeRegisterExpression(amdgpu_gfx90a::s99, output_vec_len ); + case 100: return makeRegisterExpression(amdgpu_gfx90a::s100, output_vec_len ); + case 101: return makeRegisterExpression(amdgpu_gfx90a::s101, output_vec_len ); + case 104: return makeRegisterExpression(amdgpu_gfx90a::xnack_mask_lo, output_vec_len ); + case 105: return makeRegisterExpression(amdgpu_gfx90a::xnack_mask_hi, output_vec_len ); + case 102: return makeRegisterExpression(amdgpu_gfx90a::flat_scratch_lo, output_vec_len ); + case 103: return makeRegisterExpression(amdgpu_gfx90a::flat_scratch_hi, output_vec_len ); + case 108: return makeRegisterExpression(amdgpu_gfx90a::ttmp0, output_vec_len ); + case 109: return makeRegisterExpression(amdgpu_gfx90a::ttmp1, output_vec_len ); + case 110: return makeRegisterExpression(amdgpu_gfx90a::ttmp2, output_vec_len ); + case 111: return makeRegisterExpression(amdgpu_gfx90a::ttmp3, output_vec_len ); + case 112: return makeRegisterExpression(amdgpu_gfx90a::ttmp4, output_vec_len ); + case 113: return makeRegisterExpression(amdgpu_gfx90a::ttmp5, output_vec_len ); + case 114: return makeRegisterExpression(amdgpu_gfx90a::ttmp6, output_vec_len ); + case 115: return makeRegisterExpression(amdgpu_gfx90a::ttmp7, output_vec_len ); + case 116: return makeRegisterExpression(amdgpu_gfx90a::ttmp8, output_vec_len ); + case 117: return makeRegisterExpression(amdgpu_gfx90a::ttmp9, output_vec_len ); + case 118: return makeRegisterExpression(amdgpu_gfx90a::ttmp10, output_vec_len ); + case 119: return makeRegisterExpression(amdgpu_gfx90a::ttmp11, output_vec_len ); + case 120: return makeRegisterExpression(amdgpu_gfx90a::ttmp12, output_vec_len ); + case 121: return makeRegisterExpression(amdgpu_gfx90a::ttmp13, output_vec_len ); + case 122: return makeRegisterExpression(amdgpu_gfx90a::ttmp14, output_vec_len ); + case 123: return makeRegisterExpression(amdgpu_gfx90a::ttmp15, output_vec_len ); + case 106: return makeRegisterExpression(amdgpu_gfx90a::vcc_lo, output_vec_len ); + case 107: return makeRegisterExpression(amdgpu_gfx90a::vcc_hi, output_vec_len ); + case 124: return makeRegisterExpression(amdgpu_gfx90a::m0, output_vec_len ); + case 126: return makeRegisterExpression(amdgpu_gfx90a::exec_lo, output_vec_len ); + case 127: return makeRegisterExpression(amdgpu_gfx90a::exec_hi, output_vec_len ); + default: return makeRegisterExpression(amdgpu_gfx90a::invalid); + } + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx90a::decodeOPR_SDST_EXEC(uint64_t input, uint32_t output_vec_len) + { + switch (input) { + case 126: return makeRegisterExpression(amdgpu_gfx90a::exec_lo, output_vec_len ); + case 127: return makeRegisterExpression(amdgpu_gfx90a::exec_hi, output_vec_len ); + default: return makeRegisterExpression(amdgpu_gfx90a::invalid); + } + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx90a::decodeOPR_SDST_M0(uint64_t input, uint32_t output_vec_len) + { + switch (input) { + case 124: return makeRegisterExpression(amdgpu_gfx90a::m0, output_vec_len ); + default: return makeRegisterExpression(amdgpu_gfx90a::invalid); + } + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx90a::decodeOPR_SRC(uint64_t input, uint32_t output_vec_len) + { + switch (input) { + case 0: return makeRegisterExpression(amdgpu_gfx90a::s0, output_vec_len ); + case 1: return makeRegisterExpression(amdgpu_gfx90a::s1, output_vec_len ); + case 2: return makeRegisterExpression(amdgpu_gfx90a::s2, output_vec_len ); + case 3: return makeRegisterExpression(amdgpu_gfx90a::s3, output_vec_len ); + case 4: return makeRegisterExpression(amdgpu_gfx90a::s4, output_vec_len ); + case 5: return makeRegisterExpression(amdgpu_gfx90a::s5, output_vec_len ); + case 6: return makeRegisterExpression(amdgpu_gfx90a::s6, output_vec_len ); + case 7: return makeRegisterExpression(amdgpu_gfx90a::s7, output_vec_len ); + case 8: return makeRegisterExpression(amdgpu_gfx90a::s8, output_vec_len ); + case 9: return makeRegisterExpression(amdgpu_gfx90a::s9, output_vec_len ); + case 10: return makeRegisterExpression(amdgpu_gfx90a::s10, output_vec_len ); + case 11: return makeRegisterExpression(amdgpu_gfx90a::s11, output_vec_len ); + case 12: return makeRegisterExpression(amdgpu_gfx90a::s12, output_vec_len ); + case 13: return makeRegisterExpression(amdgpu_gfx90a::s13, output_vec_len ); + case 14: return makeRegisterExpression(amdgpu_gfx90a::s14, output_vec_len ); + case 15: return makeRegisterExpression(amdgpu_gfx90a::s15, output_vec_len ); + case 16: return makeRegisterExpression(amdgpu_gfx90a::s16, output_vec_len ); + case 17: return makeRegisterExpression(amdgpu_gfx90a::s17, output_vec_len ); + case 18: return makeRegisterExpression(amdgpu_gfx90a::s18, output_vec_len ); + case 19: return makeRegisterExpression(amdgpu_gfx90a::s19, output_vec_len ); + case 20: return makeRegisterExpression(amdgpu_gfx90a::s20, output_vec_len ); + case 21: return makeRegisterExpression(amdgpu_gfx90a::s21, output_vec_len ); + case 22: return makeRegisterExpression(amdgpu_gfx90a::s22, output_vec_len ); + case 23: return makeRegisterExpression(amdgpu_gfx90a::s23, output_vec_len ); + case 24: return makeRegisterExpression(amdgpu_gfx90a::s24, output_vec_len ); + case 25: return makeRegisterExpression(amdgpu_gfx90a::s25, output_vec_len ); + case 26: return makeRegisterExpression(amdgpu_gfx90a::s26, output_vec_len ); + case 27: return makeRegisterExpression(amdgpu_gfx90a::s27, output_vec_len ); + case 28: return makeRegisterExpression(amdgpu_gfx90a::s28, output_vec_len ); + case 29: return makeRegisterExpression(amdgpu_gfx90a::s29, output_vec_len ); + case 30: return makeRegisterExpression(amdgpu_gfx90a::s30, output_vec_len ); + case 31: return makeRegisterExpression(amdgpu_gfx90a::s31, output_vec_len ); + case 32: return makeRegisterExpression(amdgpu_gfx90a::s32, output_vec_len ); + case 33: return makeRegisterExpression(amdgpu_gfx90a::s33, output_vec_len ); + case 34: return makeRegisterExpression(amdgpu_gfx90a::s34, output_vec_len ); + case 35: return makeRegisterExpression(amdgpu_gfx90a::s35, output_vec_len ); + case 36: return makeRegisterExpression(amdgpu_gfx90a::s36, output_vec_len ); + case 37: return makeRegisterExpression(amdgpu_gfx90a::s37, output_vec_len ); + case 38: return makeRegisterExpression(amdgpu_gfx90a::s38, output_vec_len ); + case 39: return makeRegisterExpression(amdgpu_gfx90a::s39, output_vec_len ); + case 40: return makeRegisterExpression(amdgpu_gfx90a::s40, output_vec_len ); + case 41: return makeRegisterExpression(amdgpu_gfx90a::s41, output_vec_len ); + case 42: return makeRegisterExpression(amdgpu_gfx90a::s42, output_vec_len ); + case 43: return makeRegisterExpression(amdgpu_gfx90a::s43, output_vec_len ); + case 44: return makeRegisterExpression(amdgpu_gfx90a::s44, output_vec_len ); + case 45: return makeRegisterExpression(amdgpu_gfx90a::s45, output_vec_len ); + case 46: return makeRegisterExpression(amdgpu_gfx90a::s46, output_vec_len ); + case 47: return makeRegisterExpression(amdgpu_gfx90a::s47, output_vec_len ); + case 48: return makeRegisterExpression(amdgpu_gfx90a::s48, output_vec_len ); + case 49: return makeRegisterExpression(amdgpu_gfx90a::s49, output_vec_len ); + case 50: return makeRegisterExpression(amdgpu_gfx90a::s50, output_vec_len ); + case 51: return makeRegisterExpression(amdgpu_gfx90a::s51, output_vec_len ); + case 52: return makeRegisterExpression(amdgpu_gfx90a::s52, output_vec_len ); + case 53: return makeRegisterExpression(amdgpu_gfx90a::s53, output_vec_len ); + case 54: return makeRegisterExpression(amdgpu_gfx90a::s54, output_vec_len ); + case 55: return makeRegisterExpression(amdgpu_gfx90a::s55, output_vec_len ); + case 56: return makeRegisterExpression(amdgpu_gfx90a::s56, output_vec_len ); + case 57: return makeRegisterExpression(amdgpu_gfx90a::s57, output_vec_len ); + case 58: return makeRegisterExpression(amdgpu_gfx90a::s58, output_vec_len ); + case 59: return makeRegisterExpression(amdgpu_gfx90a::s59, output_vec_len ); + case 60: return makeRegisterExpression(amdgpu_gfx90a::s60, output_vec_len ); + case 61: return makeRegisterExpression(amdgpu_gfx90a::s61, output_vec_len ); + case 62: return makeRegisterExpression(amdgpu_gfx90a::s62, output_vec_len ); + case 63: return makeRegisterExpression(amdgpu_gfx90a::s63, output_vec_len ); + case 64: return makeRegisterExpression(amdgpu_gfx90a::s64, output_vec_len ); + case 65: return makeRegisterExpression(amdgpu_gfx90a::s65, output_vec_len ); + case 66: return makeRegisterExpression(amdgpu_gfx90a::s66, output_vec_len ); + case 67: return makeRegisterExpression(amdgpu_gfx90a::s67, output_vec_len ); + case 68: return makeRegisterExpression(amdgpu_gfx90a::s68, output_vec_len ); + case 69: return makeRegisterExpression(amdgpu_gfx90a::s69, output_vec_len ); + case 70: return makeRegisterExpression(amdgpu_gfx90a::s70, output_vec_len ); + case 71: return makeRegisterExpression(amdgpu_gfx90a::s71, output_vec_len ); + case 72: return makeRegisterExpression(amdgpu_gfx90a::s72, output_vec_len ); + case 73: return makeRegisterExpression(amdgpu_gfx90a::s73, output_vec_len ); + case 74: return makeRegisterExpression(amdgpu_gfx90a::s74, output_vec_len ); + case 75: return makeRegisterExpression(amdgpu_gfx90a::s75, output_vec_len ); + case 76: return makeRegisterExpression(amdgpu_gfx90a::s76, output_vec_len ); + case 77: return makeRegisterExpression(amdgpu_gfx90a::s77, output_vec_len ); + case 78: return makeRegisterExpression(amdgpu_gfx90a::s78, output_vec_len ); + case 79: return makeRegisterExpression(amdgpu_gfx90a::s79, output_vec_len ); + case 80: return makeRegisterExpression(amdgpu_gfx90a::s80, output_vec_len ); + case 81: return makeRegisterExpression(amdgpu_gfx90a::s81, output_vec_len ); + case 82: return makeRegisterExpression(amdgpu_gfx90a::s82, output_vec_len ); + case 83: return makeRegisterExpression(amdgpu_gfx90a::s83, output_vec_len ); + case 84: return makeRegisterExpression(amdgpu_gfx90a::s84, output_vec_len ); + case 85: return makeRegisterExpression(amdgpu_gfx90a::s85, output_vec_len ); + case 86: return makeRegisterExpression(amdgpu_gfx90a::s86, output_vec_len ); + case 87: return makeRegisterExpression(amdgpu_gfx90a::s87, output_vec_len ); + case 88: return makeRegisterExpression(amdgpu_gfx90a::s88, output_vec_len ); + case 89: return makeRegisterExpression(amdgpu_gfx90a::s89, output_vec_len ); + case 90: return makeRegisterExpression(amdgpu_gfx90a::s90, output_vec_len ); + case 91: return makeRegisterExpression(amdgpu_gfx90a::s91, output_vec_len ); + case 92: return makeRegisterExpression(amdgpu_gfx90a::s92, output_vec_len ); + case 93: return makeRegisterExpression(amdgpu_gfx90a::s93, output_vec_len ); + case 94: return makeRegisterExpression(amdgpu_gfx90a::s94, output_vec_len ); + case 95: return makeRegisterExpression(amdgpu_gfx90a::s95, output_vec_len ); + case 96: return makeRegisterExpression(amdgpu_gfx90a::s96, output_vec_len ); + case 97: return makeRegisterExpression(amdgpu_gfx90a::s97, output_vec_len ); + case 98: return makeRegisterExpression(amdgpu_gfx90a::s98, output_vec_len ); + case 99: return makeRegisterExpression(amdgpu_gfx90a::s99, output_vec_len ); + case 100: return makeRegisterExpression(amdgpu_gfx90a::s100, output_vec_len ); + case 101: return makeRegisterExpression(amdgpu_gfx90a::s101, output_vec_len ); + case 104: return makeRegisterExpression(amdgpu_gfx90a::xnack_mask_lo, output_vec_len ); + case 105: return makeRegisterExpression(amdgpu_gfx90a::xnack_mask_hi, output_vec_len ); + case 102: return makeRegisterExpression(amdgpu_gfx90a::flat_scratch_lo, output_vec_len ); + case 103: return makeRegisterExpression(amdgpu_gfx90a::flat_scratch_hi, output_vec_len ); + case 108: return makeRegisterExpression(amdgpu_gfx90a::ttmp0, output_vec_len ); + case 109: return makeRegisterExpression(amdgpu_gfx90a::ttmp1, output_vec_len ); + case 110: return makeRegisterExpression(amdgpu_gfx90a::ttmp2, output_vec_len ); + case 111: return makeRegisterExpression(amdgpu_gfx90a::ttmp3, output_vec_len ); + case 112: return makeRegisterExpression(amdgpu_gfx90a::ttmp4, output_vec_len ); + case 113: return makeRegisterExpression(amdgpu_gfx90a::ttmp5, output_vec_len ); + case 114: return makeRegisterExpression(amdgpu_gfx90a::ttmp6, output_vec_len ); + case 115: return makeRegisterExpression(amdgpu_gfx90a::ttmp7, output_vec_len ); + case 116: return makeRegisterExpression(amdgpu_gfx90a::ttmp8, output_vec_len ); + case 117: return makeRegisterExpression(amdgpu_gfx90a::ttmp9, output_vec_len ); + case 118: return makeRegisterExpression(amdgpu_gfx90a::ttmp10, output_vec_len ); + case 119: return makeRegisterExpression(amdgpu_gfx90a::ttmp11, output_vec_len ); + case 120: return makeRegisterExpression(amdgpu_gfx90a::ttmp12, output_vec_len ); + case 121: return makeRegisterExpression(amdgpu_gfx90a::ttmp13, output_vec_len ); + case 122: return makeRegisterExpression(amdgpu_gfx90a::ttmp14, output_vec_len ); + case 123: return makeRegisterExpression(amdgpu_gfx90a::ttmp15, output_vec_len ); + case 106: return makeRegisterExpression(amdgpu_gfx90a::vcc_lo, output_vec_len ); + case 107: return makeRegisterExpression(amdgpu_gfx90a::vcc_hi, output_vec_len ); + case 124: return makeRegisterExpression(amdgpu_gfx90a::m0, output_vec_len ); + case 126: return makeRegisterExpression(amdgpu_gfx90a::exec_lo, output_vec_len ); + case 127: return makeRegisterExpression(amdgpu_gfx90a::exec_hi, output_vec_len ); + case 128: return Immediate::makeImmediate(Result(u32, 0)); + case 129: return Immediate::makeImmediate(Result(u32, 1)); + case 130: return Immediate::makeImmediate(Result(u32, 2)); + case 131: return Immediate::makeImmediate(Result(u32, 3)); + case 132: return Immediate::makeImmediate(Result(u32, 4)); + case 133: return Immediate::makeImmediate(Result(u32, 5)); + case 134: return Immediate::makeImmediate(Result(u32, 6)); + case 135: return Immediate::makeImmediate(Result(u32, 7)); + case 136: return Immediate::makeImmediate(Result(u32, 8)); + case 137: return Immediate::makeImmediate(Result(u32, 9)); + case 138: return Immediate::makeImmediate(Result(u32, 10)); + case 139: return Immediate::makeImmediate(Result(u32, 11)); + case 140: return Immediate::makeImmediate(Result(u32, 12)); + case 141: return Immediate::makeImmediate(Result(u32, 13)); + case 142: return Immediate::makeImmediate(Result(u32, 14)); + case 143: return Immediate::makeImmediate(Result(u32, 15)); + case 144: return Immediate::makeImmediate(Result(u32, 16)); + case 145: return Immediate::makeImmediate(Result(u32, 17)); + case 146: return Immediate::makeImmediate(Result(u32, 18)); + case 147: return Immediate::makeImmediate(Result(u32, 19)); + case 148: return Immediate::makeImmediate(Result(u32, 20)); + case 149: return Immediate::makeImmediate(Result(u32, 21)); + case 150: return Immediate::makeImmediate(Result(u32, 22)); + case 151: return Immediate::makeImmediate(Result(u32, 23)); + case 152: return Immediate::makeImmediate(Result(u32, 24)); + case 153: return Immediate::makeImmediate(Result(u32, 25)); + case 154: return Immediate::makeImmediate(Result(u32, 26)); + case 155: return Immediate::makeImmediate(Result(u32, 27)); + case 156: return Immediate::makeImmediate(Result(u32, 28)); + case 157: return Immediate::makeImmediate(Result(u32, 29)); + case 158: return Immediate::makeImmediate(Result(u32, 30)); + case 159: return Immediate::makeImmediate(Result(u32, 31)); + case 160: return Immediate::makeImmediate(Result(u32, 32)); + case 161: return Immediate::makeImmediate(Result(u32, 33)); + case 162: return Immediate::makeImmediate(Result(u32, 34)); + case 163: return Immediate::makeImmediate(Result(u32, 35)); + case 164: return Immediate::makeImmediate(Result(u32, 36)); + case 165: return Immediate::makeImmediate(Result(u32, 37)); + case 166: return Immediate::makeImmediate(Result(u32, 38)); + case 167: return Immediate::makeImmediate(Result(u32, 39)); + case 168: return Immediate::makeImmediate(Result(u32, 40)); + case 169: return Immediate::makeImmediate(Result(u32, 41)); + case 170: return Immediate::makeImmediate(Result(u32, 42)); + case 171: return Immediate::makeImmediate(Result(u32, 43)); + case 172: return Immediate::makeImmediate(Result(u32, 44)); + case 173: return Immediate::makeImmediate(Result(u32, 45)); + case 174: return Immediate::makeImmediate(Result(u32, 46)); + case 175: return Immediate::makeImmediate(Result(u32, 47)); + case 176: return Immediate::makeImmediate(Result(u32, 48)); + case 177: return Immediate::makeImmediate(Result(u32, 49)); + case 178: return Immediate::makeImmediate(Result(u32, 50)); + case 179: return Immediate::makeImmediate(Result(u32, 51)); + case 180: return Immediate::makeImmediate(Result(u32, 52)); + case 181: return Immediate::makeImmediate(Result(u32, 53)); + case 182: return Immediate::makeImmediate(Result(u32, 54)); + case 183: return Immediate::makeImmediate(Result(u32, 55)); + case 184: return Immediate::makeImmediate(Result(u32, 56)); + case 185: return Immediate::makeImmediate(Result(u32, 57)); + case 186: return Immediate::makeImmediate(Result(u32, 58)); + case 187: return Immediate::makeImmediate(Result(u32, 59)); + case 188: return Immediate::makeImmediate(Result(u32, 60)); + case 189: return Immediate::makeImmediate(Result(u32, 61)); + case 190: return Immediate::makeImmediate(Result(u32, 62)); + case 191: return Immediate::makeImmediate(Result(u32, 63)); + case 192: return Immediate::makeImmediate(Result(u32, 64)); + case 193: return Immediate::makeImmediate(Result(u32, -1)); + case 194: return Immediate::makeImmediate(Result(u32, -2)); + case 195: return Immediate::makeImmediate(Result(u32, -3)); + case 196: return Immediate::makeImmediate(Result(u32, -4)); + case 197: return Immediate::makeImmediate(Result(u32, -5)); + case 198: return Immediate::makeImmediate(Result(u32, -6)); + case 199: return Immediate::makeImmediate(Result(u32, -7)); + case 200: return Immediate::makeImmediate(Result(u32, -8)); + case 201: return Immediate::makeImmediate(Result(u32, -9)); + case 202: return Immediate::makeImmediate(Result(u32, -10)); + case 203: return Immediate::makeImmediate(Result(u32, -11)); + case 204: return Immediate::makeImmediate(Result(u32, -12)); + case 205: return Immediate::makeImmediate(Result(u32, -13)); + case 206: return Immediate::makeImmediate(Result(u32, -14)); + case 207: return Immediate::makeImmediate(Result(u32, -15)); + case 208: return Immediate::makeImmediate(Result(u32, -16)); + case 240: return Immediate::makeImmediate(Result(sp_float, 0.5)); + case 241: return Immediate::makeImmediate(Result(sp_float, -0.5)); + case 242: return Immediate::makeImmediate(Result(sp_float, 1.0)); + case 243: return Immediate::makeImmediate(Result(sp_float, -1.0)); + case 244: return Immediate::makeImmediate(Result(sp_float, 2.0)); + case 245: return Immediate::makeImmediate(Result(sp_float, -2.0)); + case 246: return Immediate::makeImmediate(Result(sp_float, 4.0)); + case 247: return Immediate::makeImmediate(Result(sp_float, -4.0)); + case 248: return Immediate::makeImmediate(Result(sp_float, 0.15915494)); + case 251: return makeRegisterExpression(amdgpu_gfx90a::src_vccz, output_vec_len ); + case 252: return makeRegisterExpression(amdgpu_gfx90a::src_execz, output_vec_len ); + case 253: return makeRegisterExpression(amdgpu_gfx90a::src_scc, output_vec_len ); + case 235: return makeRegisterExpression(amdgpu_gfx90a::src_shared_base, output_vec_len ); + case 236: return makeRegisterExpression(amdgpu_gfx90a::src_shared_limit, output_vec_len ); + case 237: return makeRegisterExpression(amdgpu_gfx90a::src_private_base, output_vec_len ); + case 238: return makeRegisterExpression(amdgpu_gfx90a::src_private_limit, output_vec_len ); + case 239: return makeRegisterExpression(amdgpu_gfx90a::src_pops_exiting_wave_id, output_vec_len ); + case 256: return makeRegisterExpression(amdgpu_gfx90a::v0, output_vec_len ); + case 257: return makeRegisterExpression(amdgpu_gfx90a::v1, output_vec_len ); + case 258: return makeRegisterExpression(amdgpu_gfx90a::v2, output_vec_len ); + case 259: return makeRegisterExpression(amdgpu_gfx90a::v3, output_vec_len ); + case 260: return makeRegisterExpression(amdgpu_gfx90a::v4, output_vec_len ); + case 261: return makeRegisterExpression(amdgpu_gfx90a::v5, output_vec_len ); + case 262: return makeRegisterExpression(amdgpu_gfx90a::v6, output_vec_len ); + case 263: return makeRegisterExpression(amdgpu_gfx90a::v7, output_vec_len ); + case 264: return makeRegisterExpression(amdgpu_gfx90a::v8, output_vec_len ); + case 265: return makeRegisterExpression(amdgpu_gfx90a::v9, output_vec_len ); + case 266: return makeRegisterExpression(amdgpu_gfx90a::v10, output_vec_len ); + case 267: return makeRegisterExpression(amdgpu_gfx90a::v11, output_vec_len ); + case 268: return makeRegisterExpression(amdgpu_gfx90a::v12, output_vec_len ); + case 269: return makeRegisterExpression(amdgpu_gfx90a::v13, output_vec_len ); + case 270: return makeRegisterExpression(amdgpu_gfx90a::v14, output_vec_len ); + case 271: return makeRegisterExpression(amdgpu_gfx90a::v15, output_vec_len ); + case 272: return makeRegisterExpression(amdgpu_gfx90a::v16, output_vec_len ); + case 273: return makeRegisterExpression(amdgpu_gfx90a::v17, output_vec_len ); + case 274: return makeRegisterExpression(amdgpu_gfx90a::v18, output_vec_len ); + case 275: return makeRegisterExpression(amdgpu_gfx90a::v19, output_vec_len ); + case 276: return makeRegisterExpression(amdgpu_gfx90a::v20, output_vec_len ); + case 277: return makeRegisterExpression(amdgpu_gfx90a::v21, output_vec_len ); + case 278: return makeRegisterExpression(amdgpu_gfx90a::v22, output_vec_len ); + case 279: return makeRegisterExpression(amdgpu_gfx90a::v23, output_vec_len ); + case 280: return makeRegisterExpression(amdgpu_gfx90a::v24, output_vec_len ); + case 281: return makeRegisterExpression(amdgpu_gfx90a::v25, output_vec_len ); + case 282: return makeRegisterExpression(amdgpu_gfx90a::v26, output_vec_len ); + case 283: return makeRegisterExpression(amdgpu_gfx90a::v27, output_vec_len ); + case 284: return makeRegisterExpression(amdgpu_gfx90a::v28, output_vec_len ); + case 285: return makeRegisterExpression(amdgpu_gfx90a::v29, output_vec_len ); + case 286: return makeRegisterExpression(amdgpu_gfx90a::v30, output_vec_len ); + case 287: return makeRegisterExpression(amdgpu_gfx90a::v31, output_vec_len ); + case 288: return makeRegisterExpression(amdgpu_gfx90a::v32, output_vec_len ); + case 289: return makeRegisterExpression(amdgpu_gfx90a::v33, output_vec_len ); + case 290: return makeRegisterExpression(amdgpu_gfx90a::v34, output_vec_len ); + case 291: return makeRegisterExpression(amdgpu_gfx90a::v35, output_vec_len ); + case 292: return makeRegisterExpression(amdgpu_gfx90a::v36, output_vec_len ); + case 293: return makeRegisterExpression(amdgpu_gfx90a::v37, output_vec_len ); + case 294: return makeRegisterExpression(amdgpu_gfx90a::v38, output_vec_len ); + case 295: return makeRegisterExpression(amdgpu_gfx90a::v39, output_vec_len ); + case 296: return makeRegisterExpression(amdgpu_gfx90a::v40, output_vec_len ); + case 297: return makeRegisterExpression(amdgpu_gfx90a::v41, output_vec_len ); + case 298: return makeRegisterExpression(amdgpu_gfx90a::v42, output_vec_len ); + case 299: return makeRegisterExpression(amdgpu_gfx90a::v43, output_vec_len ); + case 300: return makeRegisterExpression(amdgpu_gfx90a::v44, output_vec_len ); + case 301: return makeRegisterExpression(amdgpu_gfx90a::v45, output_vec_len ); + case 302: return makeRegisterExpression(amdgpu_gfx90a::v46, output_vec_len ); + case 303: return makeRegisterExpression(amdgpu_gfx90a::v47, output_vec_len ); + case 304: return makeRegisterExpression(amdgpu_gfx90a::v48, output_vec_len ); + case 305: return makeRegisterExpression(amdgpu_gfx90a::v49, output_vec_len ); + case 306: return makeRegisterExpression(amdgpu_gfx90a::v50, output_vec_len ); + case 307: return makeRegisterExpression(amdgpu_gfx90a::v51, output_vec_len ); + case 308: return makeRegisterExpression(amdgpu_gfx90a::v52, output_vec_len ); + case 309: return makeRegisterExpression(amdgpu_gfx90a::v53, output_vec_len ); + case 310: return makeRegisterExpression(amdgpu_gfx90a::v54, output_vec_len ); + case 311: return makeRegisterExpression(amdgpu_gfx90a::v55, output_vec_len ); + case 312: return makeRegisterExpression(amdgpu_gfx90a::v56, output_vec_len ); + case 313: return makeRegisterExpression(amdgpu_gfx90a::v57, output_vec_len ); + case 314: return makeRegisterExpression(amdgpu_gfx90a::v58, output_vec_len ); + case 315: return makeRegisterExpression(amdgpu_gfx90a::v59, output_vec_len ); + case 316: return makeRegisterExpression(amdgpu_gfx90a::v60, output_vec_len ); + case 317: return makeRegisterExpression(amdgpu_gfx90a::v61, output_vec_len ); + case 318: return makeRegisterExpression(amdgpu_gfx90a::v62, output_vec_len ); + case 319: return makeRegisterExpression(amdgpu_gfx90a::v63, output_vec_len ); + case 320: return makeRegisterExpression(amdgpu_gfx90a::v64, output_vec_len ); + case 321: return makeRegisterExpression(amdgpu_gfx90a::v65, output_vec_len ); + case 322: return makeRegisterExpression(amdgpu_gfx90a::v66, output_vec_len ); + case 323: return makeRegisterExpression(amdgpu_gfx90a::v67, output_vec_len ); + case 324: return makeRegisterExpression(amdgpu_gfx90a::v68, output_vec_len ); + case 325: return makeRegisterExpression(amdgpu_gfx90a::v69, output_vec_len ); + case 326: return makeRegisterExpression(amdgpu_gfx90a::v70, output_vec_len ); + case 327: return makeRegisterExpression(amdgpu_gfx90a::v71, output_vec_len ); + case 328: return makeRegisterExpression(amdgpu_gfx90a::v72, output_vec_len ); + case 329: return makeRegisterExpression(amdgpu_gfx90a::v73, output_vec_len ); + case 330: return makeRegisterExpression(amdgpu_gfx90a::v74, output_vec_len ); + case 331: return makeRegisterExpression(amdgpu_gfx90a::v75, output_vec_len ); + case 332: return makeRegisterExpression(amdgpu_gfx90a::v76, output_vec_len ); + case 333: return makeRegisterExpression(amdgpu_gfx90a::v77, output_vec_len ); + case 334: return makeRegisterExpression(amdgpu_gfx90a::v78, output_vec_len ); + case 335: return makeRegisterExpression(amdgpu_gfx90a::v79, output_vec_len ); + case 336: return makeRegisterExpression(amdgpu_gfx90a::v80, output_vec_len ); + case 337: return makeRegisterExpression(amdgpu_gfx90a::v81, output_vec_len ); + case 338: return makeRegisterExpression(amdgpu_gfx90a::v82, output_vec_len ); + case 339: return makeRegisterExpression(amdgpu_gfx90a::v83, output_vec_len ); + case 340: return makeRegisterExpression(amdgpu_gfx90a::v84, output_vec_len ); + case 341: return makeRegisterExpression(amdgpu_gfx90a::v85, output_vec_len ); + case 342: return makeRegisterExpression(amdgpu_gfx90a::v86, output_vec_len ); + case 343: return makeRegisterExpression(amdgpu_gfx90a::v87, output_vec_len ); + case 344: return makeRegisterExpression(amdgpu_gfx90a::v88, output_vec_len ); + case 345: return makeRegisterExpression(amdgpu_gfx90a::v89, output_vec_len ); + case 346: return makeRegisterExpression(amdgpu_gfx90a::v90, output_vec_len ); + case 347: return makeRegisterExpression(amdgpu_gfx90a::v91, output_vec_len ); + case 348: return makeRegisterExpression(amdgpu_gfx90a::v92, output_vec_len ); + case 349: return makeRegisterExpression(amdgpu_gfx90a::v93, output_vec_len ); + case 350: return makeRegisterExpression(amdgpu_gfx90a::v94, output_vec_len ); + case 351: return makeRegisterExpression(amdgpu_gfx90a::v95, output_vec_len ); + case 352: return makeRegisterExpression(amdgpu_gfx90a::v96, output_vec_len ); + case 353: return makeRegisterExpression(amdgpu_gfx90a::v97, output_vec_len ); + case 354: return makeRegisterExpression(amdgpu_gfx90a::v98, output_vec_len ); + case 355: return makeRegisterExpression(amdgpu_gfx90a::v99, output_vec_len ); + case 356: return makeRegisterExpression(amdgpu_gfx90a::v100, output_vec_len ); + case 357: return makeRegisterExpression(amdgpu_gfx90a::v101, output_vec_len ); + case 358: return makeRegisterExpression(amdgpu_gfx90a::v102, output_vec_len ); + case 359: return makeRegisterExpression(amdgpu_gfx90a::v103, output_vec_len ); + case 360: return makeRegisterExpression(amdgpu_gfx90a::v104, output_vec_len ); + case 361: return makeRegisterExpression(amdgpu_gfx90a::v105, output_vec_len ); + case 362: return makeRegisterExpression(amdgpu_gfx90a::v106, output_vec_len ); + case 363: return makeRegisterExpression(amdgpu_gfx90a::v107, output_vec_len ); + case 364: return makeRegisterExpression(amdgpu_gfx90a::v108, output_vec_len ); + case 365: return makeRegisterExpression(amdgpu_gfx90a::v109, output_vec_len ); + case 366: return makeRegisterExpression(amdgpu_gfx90a::v110, output_vec_len ); + case 367: return makeRegisterExpression(amdgpu_gfx90a::v111, output_vec_len ); + case 368: return makeRegisterExpression(amdgpu_gfx90a::v112, output_vec_len ); + case 369: return makeRegisterExpression(amdgpu_gfx90a::v113, output_vec_len ); + case 370: return makeRegisterExpression(amdgpu_gfx90a::v114, output_vec_len ); + case 371: return makeRegisterExpression(amdgpu_gfx90a::v115, output_vec_len ); + case 372: return makeRegisterExpression(amdgpu_gfx90a::v116, output_vec_len ); + case 373: return makeRegisterExpression(amdgpu_gfx90a::v117, output_vec_len ); + case 374: return makeRegisterExpression(amdgpu_gfx90a::v118, output_vec_len ); + case 375: return makeRegisterExpression(amdgpu_gfx90a::v119, output_vec_len ); + case 376: return makeRegisterExpression(amdgpu_gfx90a::v120, output_vec_len ); + case 377: return makeRegisterExpression(amdgpu_gfx90a::v121, output_vec_len ); + case 378: return makeRegisterExpression(amdgpu_gfx90a::v122, output_vec_len ); + case 379: return makeRegisterExpression(amdgpu_gfx90a::v123, output_vec_len ); + case 380: return makeRegisterExpression(amdgpu_gfx90a::v124, output_vec_len ); + case 381: return makeRegisterExpression(amdgpu_gfx90a::v125, output_vec_len ); + case 382: return makeRegisterExpression(amdgpu_gfx90a::v126, output_vec_len ); + case 383: return makeRegisterExpression(amdgpu_gfx90a::v127, output_vec_len ); + case 384: return makeRegisterExpression(amdgpu_gfx90a::v128, output_vec_len ); + case 385: return makeRegisterExpression(amdgpu_gfx90a::v129, output_vec_len ); + case 386: return makeRegisterExpression(amdgpu_gfx90a::v130, output_vec_len ); + case 387: return makeRegisterExpression(amdgpu_gfx90a::v131, output_vec_len ); + case 388: return makeRegisterExpression(amdgpu_gfx90a::v132, output_vec_len ); + case 389: return makeRegisterExpression(amdgpu_gfx90a::v133, output_vec_len ); + case 390: return makeRegisterExpression(amdgpu_gfx90a::v134, output_vec_len ); + case 391: return makeRegisterExpression(amdgpu_gfx90a::v135, output_vec_len ); + case 392: return makeRegisterExpression(amdgpu_gfx90a::v136, output_vec_len ); + case 393: return makeRegisterExpression(amdgpu_gfx90a::v137, output_vec_len ); + case 394: return makeRegisterExpression(amdgpu_gfx90a::v138, output_vec_len ); + case 395: return makeRegisterExpression(amdgpu_gfx90a::v139, output_vec_len ); + case 396: return makeRegisterExpression(amdgpu_gfx90a::v140, output_vec_len ); + case 397: return makeRegisterExpression(amdgpu_gfx90a::v141, output_vec_len ); + case 398: return makeRegisterExpression(amdgpu_gfx90a::v142, output_vec_len ); + case 399: return makeRegisterExpression(amdgpu_gfx90a::v143, output_vec_len ); + case 400: return makeRegisterExpression(amdgpu_gfx90a::v144, output_vec_len ); + case 401: return makeRegisterExpression(amdgpu_gfx90a::v145, output_vec_len ); + case 402: return makeRegisterExpression(amdgpu_gfx90a::v146, output_vec_len ); + case 403: return makeRegisterExpression(amdgpu_gfx90a::v147, output_vec_len ); + case 404: return makeRegisterExpression(amdgpu_gfx90a::v148, output_vec_len ); + case 405: return makeRegisterExpression(amdgpu_gfx90a::v149, output_vec_len ); + case 406: return makeRegisterExpression(amdgpu_gfx90a::v150, output_vec_len ); + case 407: return makeRegisterExpression(amdgpu_gfx90a::v151, output_vec_len ); + case 408: return makeRegisterExpression(amdgpu_gfx90a::v152, output_vec_len ); + case 409: return makeRegisterExpression(amdgpu_gfx90a::v153, output_vec_len ); + case 410: return makeRegisterExpression(amdgpu_gfx90a::v154, output_vec_len ); + case 411: return makeRegisterExpression(amdgpu_gfx90a::v155, output_vec_len ); + case 412: return makeRegisterExpression(amdgpu_gfx90a::v156, output_vec_len ); + case 413: return makeRegisterExpression(amdgpu_gfx90a::v157, output_vec_len ); + case 414: return makeRegisterExpression(amdgpu_gfx90a::v158, output_vec_len ); + case 415: return makeRegisterExpression(amdgpu_gfx90a::v159, output_vec_len ); + case 416: return makeRegisterExpression(amdgpu_gfx90a::v160, output_vec_len ); + case 417: return makeRegisterExpression(amdgpu_gfx90a::v161, output_vec_len ); + case 418: return makeRegisterExpression(amdgpu_gfx90a::v162, output_vec_len ); + case 419: return makeRegisterExpression(amdgpu_gfx90a::v163, output_vec_len ); + case 420: return makeRegisterExpression(amdgpu_gfx90a::v164, output_vec_len ); + case 421: return makeRegisterExpression(amdgpu_gfx90a::v165, output_vec_len ); + case 422: return makeRegisterExpression(amdgpu_gfx90a::v166, output_vec_len ); + case 423: return makeRegisterExpression(amdgpu_gfx90a::v167, output_vec_len ); + case 424: return makeRegisterExpression(amdgpu_gfx90a::v168, output_vec_len ); + case 425: return makeRegisterExpression(amdgpu_gfx90a::v169, output_vec_len ); + case 426: return makeRegisterExpression(amdgpu_gfx90a::v170, output_vec_len ); + case 427: return makeRegisterExpression(amdgpu_gfx90a::v171, output_vec_len ); + case 428: return makeRegisterExpression(amdgpu_gfx90a::v172, output_vec_len ); + case 429: return makeRegisterExpression(amdgpu_gfx90a::v173, output_vec_len ); + case 430: return makeRegisterExpression(amdgpu_gfx90a::v174, output_vec_len ); + case 431: return makeRegisterExpression(amdgpu_gfx90a::v175, output_vec_len ); + case 432: return makeRegisterExpression(amdgpu_gfx90a::v176, output_vec_len ); + case 433: return makeRegisterExpression(amdgpu_gfx90a::v177, output_vec_len ); + case 434: return makeRegisterExpression(amdgpu_gfx90a::v178, output_vec_len ); + case 435: return makeRegisterExpression(amdgpu_gfx90a::v179, output_vec_len ); + case 436: return makeRegisterExpression(amdgpu_gfx90a::v180, output_vec_len ); + case 437: return makeRegisterExpression(amdgpu_gfx90a::v181, output_vec_len ); + case 438: return makeRegisterExpression(amdgpu_gfx90a::v182, output_vec_len ); + case 439: return makeRegisterExpression(amdgpu_gfx90a::v183, output_vec_len ); + case 440: return makeRegisterExpression(amdgpu_gfx90a::v184, output_vec_len ); + case 441: return makeRegisterExpression(amdgpu_gfx90a::v185, output_vec_len ); + case 442: return makeRegisterExpression(amdgpu_gfx90a::v186, output_vec_len ); + case 443: return makeRegisterExpression(amdgpu_gfx90a::v187, output_vec_len ); + case 444: return makeRegisterExpression(amdgpu_gfx90a::v188, output_vec_len ); + case 445: return makeRegisterExpression(amdgpu_gfx90a::v189, output_vec_len ); + case 446: return makeRegisterExpression(amdgpu_gfx90a::v190, output_vec_len ); + case 447: return makeRegisterExpression(amdgpu_gfx90a::v191, output_vec_len ); + case 448: return makeRegisterExpression(amdgpu_gfx90a::v192, output_vec_len ); + case 449: return makeRegisterExpression(amdgpu_gfx90a::v193, output_vec_len ); + case 450: return makeRegisterExpression(amdgpu_gfx90a::v194, output_vec_len ); + case 451: return makeRegisterExpression(amdgpu_gfx90a::v195, output_vec_len ); + case 452: return makeRegisterExpression(amdgpu_gfx90a::v196, output_vec_len ); + case 453: return makeRegisterExpression(amdgpu_gfx90a::v197, output_vec_len ); + case 454: return makeRegisterExpression(amdgpu_gfx90a::v198, output_vec_len ); + case 455: return makeRegisterExpression(amdgpu_gfx90a::v199, output_vec_len ); + case 456: return makeRegisterExpression(amdgpu_gfx90a::v200, output_vec_len ); + case 457: return makeRegisterExpression(amdgpu_gfx90a::v201, output_vec_len ); + case 458: return makeRegisterExpression(amdgpu_gfx90a::v202, output_vec_len ); + case 459: return makeRegisterExpression(amdgpu_gfx90a::v203, output_vec_len ); + case 460: return makeRegisterExpression(amdgpu_gfx90a::v204, output_vec_len ); + case 461: return makeRegisterExpression(amdgpu_gfx90a::v205, output_vec_len ); + case 462: return makeRegisterExpression(amdgpu_gfx90a::v206, output_vec_len ); + case 463: return makeRegisterExpression(amdgpu_gfx90a::v207, output_vec_len ); + case 464: return makeRegisterExpression(amdgpu_gfx90a::v208, output_vec_len ); + case 465: return makeRegisterExpression(amdgpu_gfx90a::v209, output_vec_len ); + case 466: return makeRegisterExpression(amdgpu_gfx90a::v210, output_vec_len ); + case 467: return makeRegisterExpression(amdgpu_gfx90a::v211, output_vec_len ); + case 468: return makeRegisterExpression(amdgpu_gfx90a::v212, output_vec_len ); + case 469: return makeRegisterExpression(amdgpu_gfx90a::v213, output_vec_len ); + case 470: return makeRegisterExpression(amdgpu_gfx90a::v214, output_vec_len ); + case 471: return makeRegisterExpression(amdgpu_gfx90a::v215, output_vec_len ); + case 472: return makeRegisterExpression(amdgpu_gfx90a::v216, output_vec_len ); + case 473: return makeRegisterExpression(amdgpu_gfx90a::v217, output_vec_len ); + case 474: return makeRegisterExpression(amdgpu_gfx90a::v218, output_vec_len ); + case 475: return makeRegisterExpression(amdgpu_gfx90a::v219, output_vec_len ); + case 476: return makeRegisterExpression(amdgpu_gfx90a::v220, output_vec_len ); + case 477: return makeRegisterExpression(amdgpu_gfx90a::v221, output_vec_len ); + case 478: return makeRegisterExpression(amdgpu_gfx90a::v222, output_vec_len ); + case 479: return makeRegisterExpression(amdgpu_gfx90a::v223, output_vec_len ); + case 480: return makeRegisterExpression(amdgpu_gfx90a::v224, output_vec_len ); + case 481: return makeRegisterExpression(amdgpu_gfx90a::v225, output_vec_len ); + case 482: return makeRegisterExpression(amdgpu_gfx90a::v226, output_vec_len ); + case 483: return makeRegisterExpression(amdgpu_gfx90a::v227, output_vec_len ); + case 484: return makeRegisterExpression(amdgpu_gfx90a::v228, output_vec_len ); + case 485: return makeRegisterExpression(amdgpu_gfx90a::v229, output_vec_len ); + case 486: return makeRegisterExpression(amdgpu_gfx90a::v230, output_vec_len ); + case 487: return makeRegisterExpression(amdgpu_gfx90a::v231, output_vec_len ); + case 488: return makeRegisterExpression(amdgpu_gfx90a::v232, output_vec_len ); + case 489: return makeRegisterExpression(amdgpu_gfx90a::v233, output_vec_len ); + case 490: return makeRegisterExpression(amdgpu_gfx90a::v234, output_vec_len ); + case 491: return makeRegisterExpression(amdgpu_gfx90a::v235, output_vec_len ); + case 492: return makeRegisterExpression(amdgpu_gfx90a::v236, output_vec_len ); + case 493: return makeRegisterExpression(amdgpu_gfx90a::v237, output_vec_len ); + case 494: return makeRegisterExpression(amdgpu_gfx90a::v238, output_vec_len ); + case 495: return makeRegisterExpression(amdgpu_gfx90a::v239, output_vec_len ); + case 496: return makeRegisterExpression(amdgpu_gfx90a::v240, output_vec_len ); + case 497: return makeRegisterExpression(amdgpu_gfx90a::v241, output_vec_len ); + case 498: return makeRegisterExpression(amdgpu_gfx90a::v242, output_vec_len ); + case 499: return makeRegisterExpression(amdgpu_gfx90a::v243, output_vec_len ); + case 500: return makeRegisterExpression(amdgpu_gfx90a::v244, output_vec_len ); + case 501: return makeRegisterExpression(amdgpu_gfx90a::v245, output_vec_len ); + case 502: return makeRegisterExpression(amdgpu_gfx90a::v246, output_vec_len ); + case 503: return makeRegisterExpression(amdgpu_gfx90a::v247, output_vec_len ); + case 504: return makeRegisterExpression(amdgpu_gfx90a::v248, output_vec_len ); + case 505: return makeRegisterExpression(amdgpu_gfx90a::v249, output_vec_len ); + case 506: return makeRegisterExpression(amdgpu_gfx90a::v250, output_vec_len ); + case 507: return makeRegisterExpression(amdgpu_gfx90a::v251, output_vec_len ); + case 508: return makeRegisterExpression(amdgpu_gfx90a::v252, output_vec_len ); + case 509: return makeRegisterExpression(amdgpu_gfx90a::v253, output_vec_len ); + case 510: return makeRegisterExpression(amdgpu_gfx90a::v254, output_vec_len ); + case 511: return makeRegisterExpression(amdgpu_gfx90a::v255, output_vec_len ); + case 255: return Immediate::makeImmediate(Result(u32,decodeOPR_LITERAL())); + case 249 : return decodeOPR_SDWA(); + default: return makeRegisterExpression(amdgpu_gfx90a::invalid); + } + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx90a::decodeOPR_SRC_ACCVGPR(uint64_t input, uint32_t output_vec_len) + { + switch (input) { + case 256: return makeRegisterExpression(amdgpu_gfx90a::acc0, output_vec_len ); + case 257: return makeRegisterExpression(amdgpu_gfx90a::acc1, output_vec_len ); + case 258: return makeRegisterExpression(amdgpu_gfx90a::acc2, output_vec_len ); + case 259: return makeRegisterExpression(amdgpu_gfx90a::acc3, output_vec_len ); + case 260: return makeRegisterExpression(amdgpu_gfx90a::acc4, output_vec_len ); + case 261: return makeRegisterExpression(amdgpu_gfx90a::acc5, output_vec_len ); + case 262: return makeRegisterExpression(amdgpu_gfx90a::acc6, output_vec_len ); + case 263: return makeRegisterExpression(amdgpu_gfx90a::acc7, output_vec_len ); + case 264: return makeRegisterExpression(amdgpu_gfx90a::acc8, output_vec_len ); + case 265: return makeRegisterExpression(amdgpu_gfx90a::acc9, output_vec_len ); + case 266: return makeRegisterExpression(amdgpu_gfx90a::acc10, output_vec_len ); + case 267: return makeRegisterExpression(amdgpu_gfx90a::acc11, output_vec_len ); + case 268: return makeRegisterExpression(amdgpu_gfx90a::acc12, output_vec_len ); + case 269: return makeRegisterExpression(amdgpu_gfx90a::acc13, output_vec_len ); + case 270: return makeRegisterExpression(amdgpu_gfx90a::acc14, output_vec_len ); + case 271: return makeRegisterExpression(amdgpu_gfx90a::acc15, output_vec_len ); + case 272: return makeRegisterExpression(amdgpu_gfx90a::acc16, output_vec_len ); + case 273: return makeRegisterExpression(amdgpu_gfx90a::acc17, output_vec_len ); + case 274: return makeRegisterExpression(amdgpu_gfx90a::acc18, output_vec_len ); + case 275: return makeRegisterExpression(amdgpu_gfx90a::acc19, output_vec_len ); + case 276: return makeRegisterExpression(amdgpu_gfx90a::acc20, output_vec_len ); + case 277: return makeRegisterExpression(amdgpu_gfx90a::acc21, output_vec_len ); + case 278: return makeRegisterExpression(amdgpu_gfx90a::acc22, output_vec_len ); + case 279: return makeRegisterExpression(amdgpu_gfx90a::acc23, output_vec_len ); + case 280: return makeRegisterExpression(amdgpu_gfx90a::acc24, output_vec_len ); + case 281: return makeRegisterExpression(amdgpu_gfx90a::acc25, output_vec_len ); + case 282: return makeRegisterExpression(amdgpu_gfx90a::acc26, output_vec_len ); + case 283: return makeRegisterExpression(amdgpu_gfx90a::acc27, output_vec_len ); + case 284: return makeRegisterExpression(amdgpu_gfx90a::acc28, output_vec_len ); + case 285: return makeRegisterExpression(amdgpu_gfx90a::acc29, output_vec_len ); + case 286: return makeRegisterExpression(amdgpu_gfx90a::acc30, output_vec_len ); + case 287: return makeRegisterExpression(amdgpu_gfx90a::acc31, output_vec_len ); + case 288: return makeRegisterExpression(amdgpu_gfx90a::acc32, output_vec_len ); + case 289: return makeRegisterExpression(amdgpu_gfx90a::acc33, output_vec_len ); + case 290: return makeRegisterExpression(amdgpu_gfx90a::acc34, output_vec_len ); + case 291: return makeRegisterExpression(amdgpu_gfx90a::acc35, output_vec_len ); + case 292: return makeRegisterExpression(amdgpu_gfx90a::acc36, output_vec_len ); + case 293: return makeRegisterExpression(amdgpu_gfx90a::acc37, output_vec_len ); + case 294: return makeRegisterExpression(amdgpu_gfx90a::acc38, output_vec_len ); + case 295: return makeRegisterExpression(amdgpu_gfx90a::acc39, output_vec_len ); + case 296: return makeRegisterExpression(amdgpu_gfx90a::acc40, output_vec_len ); + case 297: return makeRegisterExpression(amdgpu_gfx90a::acc41, output_vec_len ); + case 298: return makeRegisterExpression(amdgpu_gfx90a::acc42, output_vec_len ); + case 299: return makeRegisterExpression(amdgpu_gfx90a::acc43, output_vec_len ); + case 300: return makeRegisterExpression(amdgpu_gfx90a::acc44, output_vec_len ); + case 301: return makeRegisterExpression(amdgpu_gfx90a::acc45, output_vec_len ); + case 302: return makeRegisterExpression(amdgpu_gfx90a::acc46, output_vec_len ); + case 303: return makeRegisterExpression(amdgpu_gfx90a::acc47, output_vec_len ); + case 304: return makeRegisterExpression(amdgpu_gfx90a::acc48, output_vec_len ); + case 305: return makeRegisterExpression(amdgpu_gfx90a::acc49, output_vec_len ); + case 306: return makeRegisterExpression(amdgpu_gfx90a::acc50, output_vec_len ); + case 307: return makeRegisterExpression(amdgpu_gfx90a::acc51, output_vec_len ); + case 308: return makeRegisterExpression(amdgpu_gfx90a::acc52, output_vec_len ); + case 309: return makeRegisterExpression(amdgpu_gfx90a::acc53, output_vec_len ); + case 310: return makeRegisterExpression(amdgpu_gfx90a::acc54, output_vec_len ); + case 311: return makeRegisterExpression(amdgpu_gfx90a::acc55, output_vec_len ); + case 312: return makeRegisterExpression(amdgpu_gfx90a::acc56, output_vec_len ); + case 313: return makeRegisterExpression(amdgpu_gfx90a::acc57, output_vec_len ); + case 314: return makeRegisterExpression(amdgpu_gfx90a::acc58, output_vec_len ); + case 315: return makeRegisterExpression(amdgpu_gfx90a::acc59, output_vec_len ); + case 316: return makeRegisterExpression(amdgpu_gfx90a::acc60, output_vec_len ); + case 317: return makeRegisterExpression(amdgpu_gfx90a::acc61, output_vec_len ); + case 318: return makeRegisterExpression(amdgpu_gfx90a::acc62, output_vec_len ); + case 319: return makeRegisterExpression(amdgpu_gfx90a::acc63, output_vec_len ); + case 320: return makeRegisterExpression(amdgpu_gfx90a::acc64, output_vec_len ); + case 321: return makeRegisterExpression(amdgpu_gfx90a::acc65, output_vec_len ); + case 322: return makeRegisterExpression(amdgpu_gfx90a::acc66, output_vec_len ); + case 323: return makeRegisterExpression(amdgpu_gfx90a::acc67, output_vec_len ); + case 324: return makeRegisterExpression(amdgpu_gfx90a::acc68, output_vec_len ); + case 325: return makeRegisterExpression(amdgpu_gfx90a::acc69, output_vec_len ); + case 326: return makeRegisterExpression(amdgpu_gfx90a::acc70, output_vec_len ); + case 327: return makeRegisterExpression(amdgpu_gfx90a::acc71, output_vec_len ); + case 328: return makeRegisterExpression(amdgpu_gfx90a::acc72, output_vec_len ); + case 329: return makeRegisterExpression(amdgpu_gfx90a::acc73, output_vec_len ); + case 330: return makeRegisterExpression(amdgpu_gfx90a::acc74, output_vec_len ); + case 331: return makeRegisterExpression(amdgpu_gfx90a::acc75, output_vec_len ); + case 332: return makeRegisterExpression(amdgpu_gfx90a::acc76, output_vec_len ); + case 333: return makeRegisterExpression(amdgpu_gfx90a::acc77, output_vec_len ); + case 334: return makeRegisterExpression(amdgpu_gfx90a::acc78, output_vec_len ); + case 335: return makeRegisterExpression(amdgpu_gfx90a::acc79, output_vec_len ); + case 336: return makeRegisterExpression(amdgpu_gfx90a::acc80, output_vec_len ); + case 337: return makeRegisterExpression(amdgpu_gfx90a::acc81, output_vec_len ); + case 338: return makeRegisterExpression(amdgpu_gfx90a::acc82, output_vec_len ); + case 339: return makeRegisterExpression(amdgpu_gfx90a::acc83, output_vec_len ); + case 340: return makeRegisterExpression(amdgpu_gfx90a::acc84, output_vec_len ); + case 341: return makeRegisterExpression(amdgpu_gfx90a::acc85, output_vec_len ); + case 342: return makeRegisterExpression(amdgpu_gfx90a::acc86, output_vec_len ); + case 343: return makeRegisterExpression(amdgpu_gfx90a::acc87, output_vec_len ); + case 344: return makeRegisterExpression(amdgpu_gfx90a::acc88, output_vec_len ); + case 345: return makeRegisterExpression(amdgpu_gfx90a::acc89, output_vec_len ); + case 346: return makeRegisterExpression(amdgpu_gfx90a::acc90, output_vec_len ); + case 347: return makeRegisterExpression(amdgpu_gfx90a::acc91, output_vec_len ); + case 348: return makeRegisterExpression(amdgpu_gfx90a::acc92, output_vec_len ); + case 349: return makeRegisterExpression(amdgpu_gfx90a::acc93, output_vec_len ); + case 350: return makeRegisterExpression(amdgpu_gfx90a::acc94, output_vec_len ); + case 351: return makeRegisterExpression(amdgpu_gfx90a::acc95, output_vec_len ); + case 352: return makeRegisterExpression(amdgpu_gfx90a::acc96, output_vec_len ); + case 353: return makeRegisterExpression(amdgpu_gfx90a::acc97, output_vec_len ); + case 354: return makeRegisterExpression(amdgpu_gfx90a::acc98, output_vec_len ); + case 355: return makeRegisterExpression(amdgpu_gfx90a::acc99, output_vec_len ); + case 356: return makeRegisterExpression(amdgpu_gfx90a::acc100, output_vec_len ); + case 357: return makeRegisterExpression(amdgpu_gfx90a::acc101, output_vec_len ); + case 358: return makeRegisterExpression(amdgpu_gfx90a::acc102, output_vec_len ); + case 359: return makeRegisterExpression(amdgpu_gfx90a::acc103, output_vec_len ); + case 360: return makeRegisterExpression(amdgpu_gfx90a::acc104, output_vec_len ); + case 361: return makeRegisterExpression(amdgpu_gfx90a::acc105, output_vec_len ); + case 362: return makeRegisterExpression(amdgpu_gfx90a::acc106, output_vec_len ); + case 363: return makeRegisterExpression(amdgpu_gfx90a::acc107, output_vec_len ); + case 364: return makeRegisterExpression(amdgpu_gfx90a::acc108, output_vec_len ); + case 365: return makeRegisterExpression(amdgpu_gfx90a::acc109, output_vec_len ); + case 366: return makeRegisterExpression(amdgpu_gfx90a::acc110, output_vec_len ); + case 367: return makeRegisterExpression(amdgpu_gfx90a::acc111, output_vec_len ); + case 368: return makeRegisterExpression(amdgpu_gfx90a::acc112, output_vec_len ); + case 369: return makeRegisterExpression(amdgpu_gfx90a::acc113, output_vec_len ); + case 370: return makeRegisterExpression(amdgpu_gfx90a::acc114, output_vec_len ); + case 371: return makeRegisterExpression(amdgpu_gfx90a::acc115, output_vec_len ); + case 372: return makeRegisterExpression(amdgpu_gfx90a::acc116, output_vec_len ); + case 373: return makeRegisterExpression(amdgpu_gfx90a::acc117, output_vec_len ); + case 374: return makeRegisterExpression(amdgpu_gfx90a::acc118, output_vec_len ); + case 375: return makeRegisterExpression(amdgpu_gfx90a::acc119, output_vec_len ); + case 376: return makeRegisterExpression(amdgpu_gfx90a::acc120, output_vec_len ); + case 377: return makeRegisterExpression(amdgpu_gfx90a::acc121, output_vec_len ); + case 378: return makeRegisterExpression(amdgpu_gfx90a::acc122, output_vec_len ); + case 379: return makeRegisterExpression(amdgpu_gfx90a::acc123, output_vec_len ); + case 380: return makeRegisterExpression(amdgpu_gfx90a::acc124, output_vec_len ); + case 381: return makeRegisterExpression(amdgpu_gfx90a::acc125, output_vec_len ); + case 382: return makeRegisterExpression(amdgpu_gfx90a::acc126, output_vec_len ); + case 383: return makeRegisterExpression(amdgpu_gfx90a::acc127, output_vec_len ); + case 384: return makeRegisterExpression(amdgpu_gfx90a::acc128, output_vec_len ); + case 385: return makeRegisterExpression(amdgpu_gfx90a::acc129, output_vec_len ); + case 386: return makeRegisterExpression(amdgpu_gfx90a::acc130, output_vec_len ); + case 387: return makeRegisterExpression(amdgpu_gfx90a::acc131, output_vec_len ); + case 388: return makeRegisterExpression(amdgpu_gfx90a::acc132, output_vec_len ); + case 389: return makeRegisterExpression(amdgpu_gfx90a::acc133, output_vec_len ); + case 390: return makeRegisterExpression(amdgpu_gfx90a::acc134, output_vec_len ); + case 391: return makeRegisterExpression(amdgpu_gfx90a::acc135, output_vec_len ); + case 392: return makeRegisterExpression(amdgpu_gfx90a::acc136, output_vec_len ); + case 393: return makeRegisterExpression(amdgpu_gfx90a::acc137, output_vec_len ); + case 394: return makeRegisterExpression(amdgpu_gfx90a::acc138, output_vec_len ); + case 395: return makeRegisterExpression(amdgpu_gfx90a::acc139, output_vec_len ); + case 396: return makeRegisterExpression(amdgpu_gfx90a::acc140, output_vec_len ); + case 397: return makeRegisterExpression(amdgpu_gfx90a::acc141, output_vec_len ); + case 398: return makeRegisterExpression(amdgpu_gfx90a::acc142, output_vec_len ); + case 399: return makeRegisterExpression(amdgpu_gfx90a::acc143, output_vec_len ); + case 400: return makeRegisterExpression(amdgpu_gfx90a::acc144, output_vec_len ); + case 401: return makeRegisterExpression(amdgpu_gfx90a::acc145, output_vec_len ); + case 402: return makeRegisterExpression(amdgpu_gfx90a::acc146, output_vec_len ); + case 403: return makeRegisterExpression(amdgpu_gfx90a::acc147, output_vec_len ); + case 404: return makeRegisterExpression(amdgpu_gfx90a::acc148, output_vec_len ); + case 405: return makeRegisterExpression(amdgpu_gfx90a::acc149, output_vec_len ); + case 406: return makeRegisterExpression(amdgpu_gfx90a::acc150, output_vec_len ); + case 407: return makeRegisterExpression(amdgpu_gfx90a::acc151, output_vec_len ); + case 408: return makeRegisterExpression(amdgpu_gfx90a::acc152, output_vec_len ); + case 409: return makeRegisterExpression(amdgpu_gfx90a::acc153, output_vec_len ); + case 410: return makeRegisterExpression(amdgpu_gfx90a::acc154, output_vec_len ); + case 411: return makeRegisterExpression(amdgpu_gfx90a::acc155, output_vec_len ); + case 412: return makeRegisterExpression(amdgpu_gfx90a::acc156, output_vec_len ); + case 413: return makeRegisterExpression(amdgpu_gfx90a::acc157, output_vec_len ); + case 414: return makeRegisterExpression(amdgpu_gfx90a::acc158, output_vec_len ); + case 415: return makeRegisterExpression(amdgpu_gfx90a::acc159, output_vec_len ); + case 416: return makeRegisterExpression(amdgpu_gfx90a::acc160, output_vec_len ); + case 417: return makeRegisterExpression(amdgpu_gfx90a::acc161, output_vec_len ); + case 418: return makeRegisterExpression(amdgpu_gfx90a::acc162, output_vec_len ); + case 419: return makeRegisterExpression(amdgpu_gfx90a::acc163, output_vec_len ); + case 420: return makeRegisterExpression(amdgpu_gfx90a::acc164, output_vec_len ); + case 421: return makeRegisterExpression(amdgpu_gfx90a::acc165, output_vec_len ); + case 422: return makeRegisterExpression(amdgpu_gfx90a::acc166, output_vec_len ); + case 423: return makeRegisterExpression(amdgpu_gfx90a::acc167, output_vec_len ); + case 424: return makeRegisterExpression(amdgpu_gfx90a::acc168, output_vec_len ); + case 425: return makeRegisterExpression(amdgpu_gfx90a::acc169, output_vec_len ); + case 426: return makeRegisterExpression(amdgpu_gfx90a::acc170, output_vec_len ); + case 427: return makeRegisterExpression(amdgpu_gfx90a::acc171, output_vec_len ); + case 428: return makeRegisterExpression(amdgpu_gfx90a::acc172, output_vec_len ); + case 429: return makeRegisterExpression(amdgpu_gfx90a::acc173, output_vec_len ); + case 430: return makeRegisterExpression(amdgpu_gfx90a::acc174, output_vec_len ); + case 431: return makeRegisterExpression(amdgpu_gfx90a::acc175, output_vec_len ); + case 432: return makeRegisterExpression(amdgpu_gfx90a::acc176, output_vec_len ); + case 433: return makeRegisterExpression(amdgpu_gfx90a::acc177, output_vec_len ); + case 434: return makeRegisterExpression(amdgpu_gfx90a::acc178, output_vec_len ); + case 435: return makeRegisterExpression(amdgpu_gfx90a::acc179, output_vec_len ); + case 436: return makeRegisterExpression(amdgpu_gfx90a::acc180, output_vec_len ); + case 437: return makeRegisterExpression(amdgpu_gfx90a::acc181, output_vec_len ); + case 438: return makeRegisterExpression(amdgpu_gfx90a::acc182, output_vec_len ); + case 439: return makeRegisterExpression(amdgpu_gfx90a::acc183, output_vec_len ); + case 440: return makeRegisterExpression(amdgpu_gfx90a::acc184, output_vec_len ); + case 441: return makeRegisterExpression(amdgpu_gfx90a::acc185, output_vec_len ); + case 442: return makeRegisterExpression(amdgpu_gfx90a::acc186, output_vec_len ); + case 443: return makeRegisterExpression(amdgpu_gfx90a::acc187, output_vec_len ); + case 444: return makeRegisterExpression(amdgpu_gfx90a::acc188, output_vec_len ); + case 445: return makeRegisterExpression(amdgpu_gfx90a::acc189, output_vec_len ); + case 446: return makeRegisterExpression(amdgpu_gfx90a::acc190, output_vec_len ); + case 447: return makeRegisterExpression(amdgpu_gfx90a::acc191, output_vec_len ); + case 448: return makeRegisterExpression(amdgpu_gfx90a::acc192, output_vec_len ); + case 449: return makeRegisterExpression(amdgpu_gfx90a::acc193, output_vec_len ); + case 450: return makeRegisterExpression(amdgpu_gfx90a::acc194, output_vec_len ); + case 451: return makeRegisterExpression(amdgpu_gfx90a::acc195, output_vec_len ); + case 452: return makeRegisterExpression(amdgpu_gfx90a::acc196, output_vec_len ); + case 453: return makeRegisterExpression(amdgpu_gfx90a::acc197, output_vec_len ); + case 454: return makeRegisterExpression(amdgpu_gfx90a::acc198, output_vec_len ); + case 455: return makeRegisterExpression(amdgpu_gfx90a::acc199, output_vec_len ); + case 456: return makeRegisterExpression(amdgpu_gfx90a::acc200, output_vec_len ); + case 457: return makeRegisterExpression(amdgpu_gfx90a::acc201, output_vec_len ); + case 458: return makeRegisterExpression(amdgpu_gfx90a::acc202, output_vec_len ); + case 459: return makeRegisterExpression(amdgpu_gfx90a::acc203, output_vec_len ); + case 460: return makeRegisterExpression(amdgpu_gfx90a::acc204, output_vec_len ); + case 461: return makeRegisterExpression(amdgpu_gfx90a::acc205, output_vec_len ); + case 462: return makeRegisterExpression(amdgpu_gfx90a::acc206, output_vec_len ); + case 463: return makeRegisterExpression(amdgpu_gfx90a::acc207, output_vec_len ); + case 464: return makeRegisterExpression(amdgpu_gfx90a::acc208, output_vec_len ); + case 465: return makeRegisterExpression(amdgpu_gfx90a::acc209, output_vec_len ); + case 466: return makeRegisterExpression(amdgpu_gfx90a::acc210, output_vec_len ); + case 467: return makeRegisterExpression(amdgpu_gfx90a::acc211, output_vec_len ); + case 468: return makeRegisterExpression(amdgpu_gfx90a::acc212, output_vec_len ); + case 469: return makeRegisterExpression(amdgpu_gfx90a::acc213, output_vec_len ); + case 470: return makeRegisterExpression(amdgpu_gfx90a::acc214, output_vec_len ); + case 471: return makeRegisterExpression(amdgpu_gfx90a::acc215, output_vec_len ); + case 472: return makeRegisterExpression(amdgpu_gfx90a::acc216, output_vec_len ); + case 473: return makeRegisterExpression(amdgpu_gfx90a::acc217, output_vec_len ); + case 474: return makeRegisterExpression(amdgpu_gfx90a::acc218, output_vec_len ); + case 475: return makeRegisterExpression(amdgpu_gfx90a::acc219, output_vec_len ); + case 476: return makeRegisterExpression(amdgpu_gfx90a::acc220, output_vec_len ); + case 477: return makeRegisterExpression(amdgpu_gfx90a::acc221, output_vec_len ); + case 478: return makeRegisterExpression(amdgpu_gfx90a::acc222, output_vec_len ); + case 479: return makeRegisterExpression(amdgpu_gfx90a::acc223, output_vec_len ); + case 480: return makeRegisterExpression(amdgpu_gfx90a::acc224, output_vec_len ); + case 481: return makeRegisterExpression(amdgpu_gfx90a::acc225, output_vec_len ); + case 482: return makeRegisterExpression(amdgpu_gfx90a::acc226, output_vec_len ); + case 483: return makeRegisterExpression(amdgpu_gfx90a::acc227, output_vec_len ); + case 484: return makeRegisterExpression(amdgpu_gfx90a::acc228, output_vec_len ); + case 485: return makeRegisterExpression(amdgpu_gfx90a::acc229, output_vec_len ); + case 486: return makeRegisterExpression(amdgpu_gfx90a::acc230, output_vec_len ); + case 487: return makeRegisterExpression(amdgpu_gfx90a::acc231, output_vec_len ); + case 488: return makeRegisterExpression(amdgpu_gfx90a::acc232, output_vec_len ); + case 489: return makeRegisterExpression(amdgpu_gfx90a::acc233, output_vec_len ); + case 490: return makeRegisterExpression(amdgpu_gfx90a::acc234, output_vec_len ); + case 491: return makeRegisterExpression(amdgpu_gfx90a::acc235, output_vec_len ); + case 492: return makeRegisterExpression(amdgpu_gfx90a::acc236, output_vec_len ); + case 493: return makeRegisterExpression(amdgpu_gfx90a::acc237, output_vec_len ); + case 494: return makeRegisterExpression(amdgpu_gfx90a::acc238, output_vec_len ); + case 495: return makeRegisterExpression(amdgpu_gfx90a::acc239, output_vec_len ); + case 496: return makeRegisterExpression(amdgpu_gfx90a::acc240, output_vec_len ); + case 497: return makeRegisterExpression(amdgpu_gfx90a::acc241, output_vec_len ); + case 498: return makeRegisterExpression(amdgpu_gfx90a::acc242, output_vec_len ); + case 499: return makeRegisterExpression(amdgpu_gfx90a::acc243, output_vec_len ); + case 500: return makeRegisterExpression(amdgpu_gfx90a::acc244, output_vec_len ); + case 501: return makeRegisterExpression(amdgpu_gfx90a::acc245, output_vec_len ); + case 502: return makeRegisterExpression(amdgpu_gfx90a::acc246, output_vec_len ); + case 503: return makeRegisterExpression(amdgpu_gfx90a::acc247, output_vec_len ); + case 504: return makeRegisterExpression(amdgpu_gfx90a::acc248, output_vec_len ); + case 505: return makeRegisterExpression(amdgpu_gfx90a::acc249, output_vec_len ); + case 506: return makeRegisterExpression(amdgpu_gfx90a::acc250, output_vec_len ); + case 507: return makeRegisterExpression(amdgpu_gfx90a::acc251, output_vec_len ); + case 508: return makeRegisterExpression(amdgpu_gfx90a::acc252, output_vec_len ); + case 509: return makeRegisterExpression(amdgpu_gfx90a::acc253, output_vec_len ); + case 510: return makeRegisterExpression(amdgpu_gfx90a::acc254, output_vec_len ); + case 511: return makeRegisterExpression(amdgpu_gfx90a::acc255, output_vec_len ); + case 768: return makeRegisterExpression(amdgpu_gfx90a::acc0, output_vec_len ); + case 769: return makeRegisterExpression(amdgpu_gfx90a::acc1, output_vec_len ); + case 770: return makeRegisterExpression(amdgpu_gfx90a::acc2, output_vec_len ); + case 771: return makeRegisterExpression(amdgpu_gfx90a::acc3, output_vec_len ); + case 772: return makeRegisterExpression(amdgpu_gfx90a::acc4, output_vec_len ); + case 773: return makeRegisterExpression(amdgpu_gfx90a::acc5, output_vec_len ); + case 774: return makeRegisterExpression(amdgpu_gfx90a::acc6, output_vec_len ); + case 775: return makeRegisterExpression(amdgpu_gfx90a::acc7, output_vec_len ); + case 776: return makeRegisterExpression(amdgpu_gfx90a::acc8, output_vec_len ); + case 777: return makeRegisterExpression(amdgpu_gfx90a::acc9, output_vec_len ); + case 778: return makeRegisterExpression(amdgpu_gfx90a::acc10, output_vec_len ); + case 779: return makeRegisterExpression(amdgpu_gfx90a::acc11, output_vec_len ); + case 780: return makeRegisterExpression(amdgpu_gfx90a::acc12, output_vec_len ); + case 781: return makeRegisterExpression(amdgpu_gfx90a::acc13, output_vec_len ); + case 782: return makeRegisterExpression(amdgpu_gfx90a::acc14, output_vec_len ); + case 783: return makeRegisterExpression(amdgpu_gfx90a::acc15, output_vec_len ); + case 784: return makeRegisterExpression(amdgpu_gfx90a::acc16, output_vec_len ); + case 785: return makeRegisterExpression(amdgpu_gfx90a::acc17, output_vec_len ); + case 786: return makeRegisterExpression(amdgpu_gfx90a::acc18, output_vec_len ); + case 787: return makeRegisterExpression(amdgpu_gfx90a::acc19, output_vec_len ); + case 788: return makeRegisterExpression(amdgpu_gfx90a::acc20, output_vec_len ); + case 789: return makeRegisterExpression(amdgpu_gfx90a::acc21, output_vec_len ); + case 790: return makeRegisterExpression(amdgpu_gfx90a::acc22, output_vec_len ); + case 791: return makeRegisterExpression(amdgpu_gfx90a::acc23, output_vec_len ); + case 792: return makeRegisterExpression(amdgpu_gfx90a::acc24, output_vec_len ); + case 793: return makeRegisterExpression(amdgpu_gfx90a::acc25, output_vec_len ); + case 794: return makeRegisterExpression(amdgpu_gfx90a::acc26, output_vec_len ); + case 795: return makeRegisterExpression(amdgpu_gfx90a::acc27, output_vec_len ); + case 796: return makeRegisterExpression(amdgpu_gfx90a::acc28, output_vec_len ); + case 797: return makeRegisterExpression(amdgpu_gfx90a::acc29, output_vec_len ); + case 798: return makeRegisterExpression(amdgpu_gfx90a::acc30, output_vec_len ); + case 799: return makeRegisterExpression(amdgpu_gfx90a::acc31, output_vec_len ); + case 800: return makeRegisterExpression(amdgpu_gfx90a::acc32, output_vec_len ); + case 801: return makeRegisterExpression(amdgpu_gfx90a::acc33, output_vec_len ); + case 802: return makeRegisterExpression(amdgpu_gfx90a::acc34, output_vec_len ); + case 803: return makeRegisterExpression(amdgpu_gfx90a::acc35, output_vec_len ); + case 804: return makeRegisterExpression(amdgpu_gfx90a::acc36, output_vec_len ); + case 805: return makeRegisterExpression(amdgpu_gfx90a::acc37, output_vec_len ); + case 806: return makeRegisterExpression(amdgpu_gfx90a::acc38, output_vec_len ); + case 807: return makeRegisterExpression(amdgpu_gfx90a::acc39, output_vec_len ); + case 808: return makeRegisterExpression(amdgpu_gfx90a::acc40, output_vec_len ); + case 809: return makeRegisterExpression(amdgpu_gfx90a::acc41, output_vec_len ); + case 810: return makeRegisterExpression(amdgpu_gfx90a::acc42, output_vec_len ); + case 811: return makeRegisterExpression(amdgpu_gfx90a::acc43, output_vec_len ); + case 812: return makeRegisterExpression(amdgpu_gfx90a::acc44, output_vec_len ); + case 813: return makeRegisterExpression(amdgpu_gfx90a::acc45, output_vec_len ); + case 814: return makeRegisterExpression(amdgpu_gfx90a::acc46, output_vec_len ); + case 815: return makeRegisterExpression(amdgpu_gfx90a::acc47, output_vec_len ); + case 816: return makeRegisterExpression(amdgpu_gfx90a::acc48, output_vec_len ); + case 817: return makeRegisterExpression(amdgpu_gfx90a::acc49, output_vec_len ); + case 818: return makeRegisterExpression(amdgpu_gfx90a::acc50, output_vec_len ); + case 819: return makeRegisterExpression(amdgpu_gfx90a::acc51, output_vec_len ); + case 820: return makeRegisterExpression(amdgpu_gfx90a::acc52, output_vec_len ); + case 821: return makeRegisterExpression(amdgpu_gfx90a::acc53, output_vec_len ); + case 822: return makeRegisterExpression(amdgpu_gfx90a::acc54, output_vec_len ); + case 823: return makeRegisterExpression(amdgpu_gfx90a::acc55, output_vec_len ); + case 824: return makeRegisterExpression(amdgpu_gfx90a::acc56, output_vec_len ); + case 825: return makeRegisterExpression(amdgpu_gfx90a::acc57, output_vec_len ); + case 826: return makeRegisterExpression(amdgpu_gfx90a::acc58, output_vec_len ); + case 827: return makeRegisterExpression(amdgpu_gfx90a::acc59, output_vec_len ); + case 828: return makeRegisterExpression(amdgpu_gfx90a::acc60, output_vec_len ); + case 829: return makeRegisterExpression(amdgpu_gfx90a::acc61, output_vec_len ); + case 830: return makeRegisterExpression(amdgpu_gfx90a::acc62, output_vec_len ); + case 831: return makeRegisterExpression(amdgpu_gfx90a::acc63, output_vec_len ); + case 832: return makeRegisterExpression(amdgpu_gfx90a::acc64, output_vec_len ); + case 833: return makeRegisterExpression(amdgpu_gfx90a::acc65, output_vec_len ); + case 834: return makeRegisterExpression(amdgpu_gfx90a::acc66, output_vec_len ); + case 835: return makeRegisterExpression(amdgpu_gfx90a::acc67, output_vec_len ); + case 836: return makeRegisterExpression(amdgpu_gfx90a::acc68, output_vec_len ); + case 837: return makeRegisterExpression(amdgpu_gfx90a::acc69, output_vec_len ); + case 838: return makeRegisterExpression(amdgpu_gfx90a::acc70, output_vec_len ); + case 839: return makeRegisterExpression(amdgpu_gfx90a::acc71, output_vec_len ); + case 840: return makeRegisterExpression(amdgpu_gfx90a::acc72, output_vec_len ); + case 841: return makeRegisterExpression(amdgpu_gfx90a::acc73, output_vec_len ); + case 842: return makeRegisterExpression(amdgpu_gfx90a::acc74, output_vec_len ); + case 843: return makeRegisterExpression(amdgpu_gfx90a::acc75, output_vec_len ); + case 844: return makeRegisterExpression(amdgpu_gfx90a::acc76, output_vec_len ); + case 845: return makeRegisterExpression(amdgpu_gfx90a::acc77, output_vec_len ); + case 846: return makeRegisterExpression(amdgpu_gfx90a::acc78, output_vec_len ); + case 847: return makeRegisterExpression(amdgpu_gfx90a::acc79, output_vec_len ); + case 848: return makeRegisterExpression(amdgpu_gfx90a::acc80, output_vec_len ); + case 849: return makeRegisterExpression(amdgpu_gfx90a::acc81, output_vec_len ); + case 850: return makeRegisterExpression(amdgpu_gfx90a::acc82, output_vec_len ); + case 851: return makeRegisterExpression(amdgpu_gfx90a::acc83, output_vec_len ); + case 852: return makeRegisterExpression(amdgpu_gfx90a::acc84, output_vec_len ); + case 853: return makeRegisterExpression(amdgpu_gfx90a::acc85, output_vec_len ); + case 854: return makeRegisterExpression(amdgpu_gfx90a::acc86, output_vec_len ); + case 855: return makeRegisterExpression(amdgpu_gfx90a::acc87, output_vec_len ); + case 856: return makeRegisterExpression(amdgpu_gfx90a::acc88, output_vec_len ); + case 857: return makeRegisterExpression(amdgpu_gfx90a::acc89, output_vec_len ); + case 858: return makeRegisterExpression(amdgpu_gfx90a::acc90, output_vec_len ); + case 859: return makeRegisterExpression(amdgpu_gfx90a::acc91, output_vec_len ); + case 860: return makeRegisterExpression(amdgpu_gfx90a::acc92, output_vec_len ); + case 861: return makeRegisterExpression(amdgpu_gfx90a::acc93, output_vec_len ); + case 862: return makeRegisterExpression(amdgpu_gfx90a::acc94, output_vec_len ); + case 863: return makeRegisterExpression(amdgpu_gfx90a::acc95, output_vec_len ); + case 864: return makeRegisterExpression(amdgpu_gfx90a::acc96, output_vec_len ); + case 865: return makeRegisterExpression(amdgpu_gfx90a::acc97, output_vec_len ); + case 866: return makeRegisterExpression(amdgpu_gfx90a::acc98, output_vec_len ); + case 867: return makeRegisterExpression(amdgpu_gfx90a::acc99, output_vec_len ); + case 868: return makeRegisterExpression(amdgpu_gfx90a::acc100, output_vec_len ); + case 869: return makeRegisterExpression(amdgpu_gfx90a::acc101, output_vec_len ); + case 870: return makeRegisterExpression(amdgpu_gfx90a::acc102, output_vec_len ); + case 871: return makeRegisterExpression(amdgpu_gfx90a::acc103, output_vec_len ); + case 872: return makeRegisterExpression(amdgpu_gfx90a::acc104, output_vec_len ); + case 873: return makeRegisterExpression(amdgpu_gfx90a::acc105, output_vec_len ); + case 874: return makeRegisterExpression(amdgpu_gfx90a::acc106, output_vec_len ); + case 875: return makeRegisterExpression(amdgpu_gfx90a::acc107, output_vec_len ); + case 876: return makeRegisterExpression(amdgpu_gfx90a::acc108, output_vec_len ); + case 877: return makeRegisterExpression(amdgpu_gfx90a::acc109, output_vec_len ); + case 878: return makeRegisterExpression(amdgpu_gfx90a::acc110, output_vec_len ); + case 879: return makeRegisterExpression(amdgpu_gfx90a::acc111, output_vec_len ); + case 880: return makeRegisterExpression(amdgpu_gfx90a::acc112, output_vec_len ); + case 881: return makeRegisterExpression(amdgpu_gfx90a::acc113, output_vec_len ); + case 882: return makeRegisterExpression(amdgpu_gfx90a::acc114, output_vec_len ); + case 883: return makeRegisterExpression(amdgpu_gfx90a::acc115, output_vec_len ); + case 884: return makeRegisterExpression(amdgpu_gfx90a::acc116, output_vec_len ); + case 885: return makeRegisterExpression(amdgpu_gfx90a::acc117, output_vec_len ); + case 886: return makeRegisterExpression(amdgpu_gfx90a::acc118, output_vec_len ); + case 887: return makeRegisterExpression(amdgpu_gfx90a::acc119, output_vec_len ); + case 888: return makeRegisterExpression(amdgpu_gfx90a::acc120, output_vec_len ); + case 889: return makeRegisterExpression(amdgpu_gfx90a::acc121, output_vec_len ); + case 890: return makeRegisterExpression(amdgpu_gfx90a::acc122, output_vec_len ); + case 891: return makeRegisterExpression(amdgpu_gfx90a::acc123, output_vec_len ); + case 892: return makeRegisterExpression(amdgpu_gfx90a::acc124, output_vec_len ); + case 893: return makeRegisterExpression(amdgpu_gfx90a::acc125, output_vec_len ); + case 894: return makeRegisterExpression(amdgpu_gfx90a::acc126, output_vec_len ); + case 895: return makeRegisterExpression(amdgpu_gfx90a::acc127, output_vec_len ); + case 896: return makeRegisterExpression(amdgpu_gfx90a::acc128, output_vec_len ); + case 897: return makeRegisterExpression(amdgpu_gfx90a::acc129, output_vec_len ); + case 898: return makeRegisterExpression(amdgpu_gfx90a::acc130, output_vec_len ); + case 899: return makeRegisterExpression(amdgpu_gfx90a::acc131, output_vec_len ); + case 900: return makeRegisterExpression(amdgpu_gfx90a::acc132, output_vec_len ); + case 901: return makeRegisterExpression(amdgpu_gfx90a::acc133, output_vec_len ); + case 902: return makeRegisterExpression(amdgpu_gfx90a::acc134, output_vec_len ); + case 903: return makeRegisterExpression(amdgpu_gfx90a::acc135, output_vec_len ); + case 904: return makeRegisterExpression(amdgpu_gfx90a::acc136, output_vec_len ); + case 905: return makeRegisterExpression(amdgpu_gfx90a::acc137, output_vec_len ); + case 906: return makeRegisterExpression(amdgpu_gfx90a::acc138, output_vec_len ); + case 907: return makeRegisterExpression(amdgpu_gfx90a::acc139, output_vec_len ); + case 908: return makeRegisterExpression(amdgpu_gfx90a::acc140, output_vec_len ); + case 909: return makeRegisterExpression(amdgpu_gfx90a::acc141, output_vec_len ); + case 910: return makeRegisterExpression(amdgpu_gfx90a::acc142, output_vec_len ); + case 911: return makeRegisterExpression(amdgpu_gfx90a::acc143, output_vec_len ); + case 912: return makeRegisterExpression(amdgpu_gfx90a::acc144, output_vec_len ); + case 913: return makeRegisterExpression(amdgpu_gfx90a::acc145, output_vec_len ); + case 914: return makeRegisterExpression(amdgpu_gfx90a::acc146, output_vec_len ); + case 915: return makeRegisterExpression(amdgpu_gfx90a::acc147, output_vec_len ); + case 916: return makeRegisterExpression(amdgpu_gfx90a::acc148, output_vec_len ); + case 917: return makeRegisterExpression(amdgpu_gfx90a::acc149, output_vec_len ); + case 918: return makeRegisterExpression(amdgpu_gfx90a::acc150, output_vec_len ); + case 919: return makeRegisterExpression(amdgpu_gfx90a::acc151, output_vec_len ); + case 920: return makeRegisterExpression(amdgpu_gfx90a::acc152, output_vec_len ); + case 921: return makeRegisterExpression(amdgpu_gfx90a::acc153, output_vec_len ); + case 922: return makeRegisterExpression(amdgpu_gfx90a::acc154, output_vec_len ); + case 923: return makeRegisterExpression(amdgpu_gfx90a::acc155, output_vec_len ); + case 924: return makeRegisterExpression(amdgpu_gfx90a::acc156, output_vec_len ); + case 925: return makeRegisterExpression(amdgpu_gfx90a::acc157, output_vec_len ); + case 926: return makeRegisterExpression(amdgpu_gfx90a::acc158, output_vec_len ); + case 927: return makeRegisterExpression(amdgpu_gfx90a::acc159, output_vec_len ); + case 928: return makeRegisterExpression(amdgpu_gfx90a::acc160, output_vec_len ); + case 929: return makeRegisterExpression(amdgpu_gfx90a::acc161, output_vec_len ); + case 930: return makeRegisterExpression(amdgpu_gfx90a::acc162, output_vec_len ); + case 931: return makeRegisterExpression(amdgpu_gfx90a::acc163, output_vec_len ); + case 932: return makeRegisterExpression(amdgpu_gfx90a::acc164, output_vec_len ); + case 933: return makeRegisterExpression(amdgpu_gfx90a::acc165, output_vec_len ); + case 934: return makeRegisterExpression(amdgpu_gfx90a::acc166, output_vec_len ); + case 935: return makeRegisterExpression(amdgpu_gfx90a::acc167, output_vec_len ); + case 936: return makeRegisterExpression(amdgpu_gfx90a::acc168, output_vec_len ); + case 937: return makeRegisterExpression(amdgpu_gfx90a::acc169, output_vec_len ); + case 938: return makeRegisterExpression(amdgpu_gfx90a::acc170, output_vec_len ); + case 939: return makeRegisterExpression(amdgpu_gfx90a::acc171, output_vec_len ); + case 940: return makeRegisterExpression(amdgpu_gfx90a::acc172, output_vec_len ); + case 941: return makeRegisterExpression(amdgpu_gfx90a::acc173, output_vec_len ); + case 942: return makeRegisterExpression(amdgpu_gfx90a::acc174, output_vec_len ); + case 943: return makeRegisterExpression(amdgpu_gfx90a::acc175, output_vec_len ); + case 944: return makeRegisterExpression(amdgpu_gfx90a::acc176, output_vec_len ); + case 945: return makeRegisterExpression(amdgpu_gfx90a::acc177, output_vec_len ); + case 946: return makeRegisterExpression(amdgpu_gfx90a::acc178, output_vec_len ); + case 947: return makeRegisterExpression(amdgpu_gfx90a::acc179, output_vec_len ); + case 948: return makeRegisterExpression(amdgpu_gfx90a::acc180, output_vec_len ); + case 949: return makeRegisterExpression(amdgpu_gfx90a::acc181, output_vec_len ); + case 950: return makeRegisterExpression(amdgpu_gfx90a::acc182, output_vec_len ); + case 951: return makeRegisterExpression(amdgpu_gfx90a::acc183, output_vec_len ); + case 952: return makeRegisterExpression(amdgpu_gfx90a::acc184, output_vec_len ); + case 953: return makeRegisterExpression(amdgpu_gfx90a::acc185, output_vec_len ); + case 954: return makeRegisterExpression(amdgpu_gfx90a::acc186, output_vec_len ); + case 955: return makeRegisterExpression(amdgpu_gfx90a::acc187, output_vec_len ); + case 956: return makeRegisterExpression(amdgpu_gfx90a::acc188, output_vec_len ); + case 957: return makeRegisterExpression(amdgpu_gfx90a::acc189, output_vec_len ); + case 958: return makeRegisterExpression(amdgpu_gfx90a::acc190, output_vec_len ); + case 959: return makeRegisterExpression(amdgpu_gfx90a::acc191, output_vec_len ); + case 960: return makeRegisterExpression(amdgpu_gfx90a::acc192, output_vec_len ); + case 961: return makeRegisterExpression(amdgpu_gfx90a::acc193, output_vec_len ); + case 962: return makeRegisterExpression(amdgpu_gfx90a::acc194, output_vec_len ); + case 963: return makeRegisterExpression(amdgpu_gfx90a::acc195, output_vec_len ); + case 964: return makeRegisterExpression(amdgpu_gfx90a::acc196, output_vec_len ); + case 965: return makeRegisterExpression(amdgpu_gfx90a::acc197, output_vec_len ); + case 966: return makeRegisterExpression(amdgpu_gfx90a::acc198, output_vec_len ); + case 967: return makeRegisterExpression(amdgpu_gfx90a::acc199, output_vec_len ); + case 968: return makeRegisterExpression(amdgpu_gfx90a::acc200, output_vec_len ); + case 969: return makeRegisterExpression(amdgpu_gfx90a::acc201, output_vec_len ); + case 970: return makeRegisterExpression(amdgpu_gfx90a::acc202, output_vec_len ); + case 971: return makeRegisterExpression(amdgpu_gfx90a::acc203, output_vec_len ); + case 972: return makeRegisterExpression(amdgpu_gfx90a::acc204, output_vec_len ); + case 973: return makeRegisterExpression(amdgpu_gfx90a::acc205, output_vec_len ); + case 974: return makeRegisterExpression(amdgpu_gfx90a::acc206, output_vec_len ); + case 975: return makeRegisterExpression(amdgpu_gfx90a::acc207, output_vec_len ); + case 976: return makeRegisterExpression(amdgpu_gfx90a::acc208, output_vec_len ); + case 977: return makeRegisterExpression(amdgpu_gfx90a::acc209, output_vec_len ); + case 978: return makeRegisterExpression(amdgpu_gfx90a::acc210, output_vec_len ); + case 979: return makeRegisterExpression(amdgpu_gfx90a::acc211, output_vec_len ); + case 980: return makeRegisterExpression(amdgpu_gfx90a::acc212, output_vec_len ); + case 981: return makeRegisterExpression(amdgpu_gfx90a::acc213, output_vec_len ); + case 982: return makeRegisterExpression(amdgpu_gfx90a::acc214, output_vec_len ); + case 983: return makeRegisterExpression(amdgpu_gfx90a::acc215, output_vec_len ); + case 984: return makeRegisterExpression(amdgpu_gfx90a::acc216, output_vec_len ); + case 985: return makeRegisterExpression(amdgpu_gfx90a::acc217, output_vec_len ); + case 986: return makeRegisterExpression(amdgpu_gfx90a::acc218, output_vec_len ); + case 987: return makeRegisterExpression(amdgpu_gfx90a::acc219, output_vec_len ); + case 988: return makeRegisterExpression(amdgpu_gfx90a::acc220, output_vec_len ); + case 989: return makeRegisterExpression(amdgpu_gfx90a::acc221, output_vec_len ); + case 990: return makeRegisterExpression(amdgpu_gfx90a::acc222, output_vec_len ); + case 991: return makeRegisterExpression(amdgpu_gfx90a::acc223, output_vec_len ); + case 992: return makeRegisterExpression(amdgpu_gfx90a::acc224, output_vec_len ); + case 993: return makeRegisterExpression(amdgpu_gfx90a::acc225, output_vec_len ); + case 994: return makeRegisterExpression(amdgpu_gfx90a::acc226, output_vec_len ); + case 995: return makeRegisterExpression(amdgpu_gfx90a::acc227, output_vec_len ); + case 996: return makeRegisterExpression(amdgpu_gfx90a::acc228, output_vec_len ); + case 997: return makeRegisterExpression(amdgpu_gfx90a::acc229, output_vec_len ); + case 998: return makeRegisterExpression(amdgpu_gfx90a::acc230, output_vec_len ); + case 999: return makeRegisterExpression(amdgpu_gfx90a::acc231, output_vec_len ); + case 1000: return makeRegisterExpression(amdgpu_gfx90a::acc232, output_vec_len ); + case 1001: return makeRegisterExpression(amdgpu_gfx90a::acc233, output_vec_len ); + case 1002: return makeRegisterExpression(amdgpu_gfx90a::acc234, output_vec_len ); + case 1003: return makeRegisterExpression(amdgpu_gfx90a::acc235, output_vec_len ); + case 1004: return makeRegisterExpression(amdgpu_gfx90a::acc236, output_vec_len ); + case 1005: return makeRegisterExpression(amdgpu_gfx90a::acc237, output_vec_len ); + case 1006: return makeRegisterExpression(amdgpu_gfx90a::acc238, output_vec_len ); + case 1007: return makeRegisterExpression(amdgpu_gfx90a::acc239, output_vec_len ); + case 1008: return makeRegisterExpression(amdgpu_gfx90a::acc240, output_vec_len ); + case 1009: return makeRegisterExpression(amdgpu_gfx90a::acc241, output_vec_len ); + case 1010: return makeRegisterExpression(amdgpu_gfx90a::acc242, output_vec_len ); + case 1011: return makeRegisterExpression(amdgpu_gfx90a::acc243, output_vec_len ); + case 1012: return makeRegisterExpression(amdgpu_gfx90a::acc244, output_vec_len ); + case 1013: return makeRegisterExpression(amdgpu_gfx90a::acc245, output_vec_len ); + case 1014: return makeRegisterExpression(amdgpu_gfx90a::acc246, output_vec_len ); + case 1015: return makeRegisterExpression(amdgpu_gfx90a::acc247, output_vec_len ); + case 1016: return makeRegisterExpression(amdgpu_gfx90a::acc248, output_vec_len ); + case 1017: return makeRegisterExpression(amdgpu_gfx90a::acc249, output_vec_len ); + case 1018: return makeRegisterExpression(amdgpu_gfx90a::acc250, output_vec_len ); + case 1019: return makeRegisterExpression(amdgpu_gfx90a::acc251, output_vec_len ); + case 1020: return makeRegisterExpression(amdgpu_gfx90a::acc252, output_vec_len ); + case 1021: return makeRegisterExpression(amdgpu_gfx90a::acc253, output_vec_len ); + case 1022: return makeRegisterExpression(amdgpu_gfx90a::acc254, output_vec_len ); + case 1023: return makeRegisterExpression(amdgpu_gfx90a::acc255, output_vec_len ); + default: return makeRegisterExpression(amdgpu_gfx90a::invalid); + } + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx90a::decodeOPR_SRC_NOLDS(uint64_t input, uint32_t output_vec_len) + { + switch (input) { + case 0: return makeRegisterExpression(amdgpu_gfx90a::s0, output_vec_len ); + case 1: return makeRegisterExpression(amdgpu_gfx90a::s1, output_vec_len ); + case 2: return makeRegisterExpression(amdgpu_gfx90a::s2, output_vec_len ); + case 3: return makeRegisterExpression(amdgpu_gfx90a::s3, output_vec_len ); + case 4: return makeRegisterExpression(amdgpu_gfx90a::s4, output_vec_len ); + case 5: return makeRegisterExpression(amdgpu_gfx90a::s5, output_vec_len ); + case 6: return makeRegisterExpression(amdgpu_gfx90a::s6, output_vec_len ); + case 7: return makeRegisterExpression(amdgpu_gfx90a::s7, output_vec_len ); + case 8: return makeRegisterExpression(amdgpu_gfx90a::s8, output_vec_len ); + case 9: return makeRegisterExpression(amdgpu_gfx90a::s9, output_vec_len ); + case 10: return makeRegisterExpression(amdgpu_gfx90a::s10, output_vec_len ); + case 11: return makeRegisterExpression(amdgpu_gfx90a::s11, output_vec_len ); + case 12: return makeRegisterExpression(amdgpu_gfx90a::s12, output_vec_len ); + case 13: return makeRegisterExpression(amdgpu_gfx90a::s13, output_vec_len ); + case 14: return makeRegisterExpression(amdgpu_gfx90a::s14, output_vec_len ); + case 15: return makeRegisterExpression(amdgpu_gfx90a::s15, output_vec_len ); + case 16: return makeRegisterExpression(amdgpu_gfx90a::s16, output_vec_len ); + case 17: return makeRegisterExpression(amdgpu_gfx90a::s17, output_vec_len ); + case 18: return makeRegisterExpression(amdgpu_gfx90a::s18, output_vec_len ); + case 19: return makeRegisterExpression(amdgpu_gfx90a::s19, output_vec_len ); + case 20: return makeRegisterExpression(amdgpu_gfx90a::s20, output_vec_len ); + case 21: return makeRegisterExpression(amdgpu_gfx90a::s21, output_vec_len ); + case 22: return makeRegisterExpression(amdgpu_gfx90a::s22, output_vec_len ); + case 23: return makeRegisterExpression(amdgpu_gfx90a::s23, output_vec_len ); + case 24: return makeRegisterExpression(amdgpu_gfx90a::s24, output_vec_len ); + case 25: return makeRegisterExpression(amdgpu_gfx90a::s25, output_vec_len ); + case 26: return makeRegisterExpression(amdgpu_gfx90a::s26, output_vec_len ); + case 27: return makeRegisterExpression(amdgpu_gfx90a::s27, output_vec_len ); + case 28: return makeRegisterExpression(amdgpu_gfx90a::s28, output_vec_len ); + case 29: return makeRegisterExpression(amdgpu_gfx90a::s29, output_vec_len ); + case 30: return makeRegisterExpression(amdgpu_gfx90a::s30, output_vec_len ); + case 31: return makeRegisterExpression(amdgpu_gfx90a::s31, output_vec_len ); + case 32: return makeRegisterExpression(amdgpu_gfx90a::s32, output_vec_len ); + case 33: return makeRegisterExpression(amdgpu_gfx90a::s33, output_vec_len ); + case 34: return makeRegisterExpression(amdgpu_gfx90a::s34, output_vec_len ); + case 35: return makeRegisterExpression(amdgpu_gfx90a::s35, output_vec_len ); + case 36: return makeRegisterExpression(amdgpu_gfx90a::s36, output_vec_len ); + case 37: return makeRegisterExpression(amdgpu_gfx90a::s37, output_vec_len ); + case 38: return makeRegisterExpression(amdgpu_gfx90a::s38, output_vec_len ); + case 39: return makeRegisterExpression(amdgpu_gfx90a::s39, output_vec_len ); + case 40: return makeRegisterExpression(amdgpu_gfx90a::s40, output_vec_len ); + case 41: return makeRegisterExpression(amdgpu_gfx90a::s41, output_vec_len ); + case 42: return makeRegisterExpression(amdgpu_gfx90a::s42, output_vec_len ); + case 43: return makeRegisterExpression(amdgpu_gfx90a::s43, output_vec_len ); + case 44: return makeRegisterExpression(amdgpu_gfx90a::s44, output_vec_len ); + case 45: return makeRegisterExpression(amdgpu_gfx90a::s45, output_vec_len ); + case 46: return makeRegisterExpression(amdgpu_gfx90a::s46, output_vec_len ); + case 47: return makeRegisterExpression(amdgpu_gfx90a::s47, output_vec_len ); + case 48: return makeRegisterExpression(amdgpu_gfx90a::s48, output_vec_len ); + case 49: return makeRegisterExpression(amdgpu_gfx90a::s49, output_vec_len ); + case 50: return makeRegisterExpression(amdgpu_gfx90a::s50, output_vec_len ); + case 51: return makeRegisterExpression(amdgpu_gfx90a::s51, output_vec_len ); + case 52: return makeRegisterExpression(amdgpu_gfx90a::s52, output_vec_len ); + case 53: return makeRegisterExpression(amdgpu_gfx90a::s53, output_vec_len ); + case 54: return makeRegisterExpression(amdgpu_gfx90a::s54, output_vec_len ); + case 55: return makeRegisterExpression(amdgpu_gfx90a::s55, output_vec_len ); + case 56: return makeRegisterExpression(amdgpu_gfx90a::s56, output_vec_len ); + case 57: return makeRegisterExpression(amdgpu_gfx90a::s57, output_vec_len ); + case 58: return makeRegisterExpression(amdgpu_gfx90a::s58, output_vec_len ); + case 59: return makeRegisterExpression(amdgpu_gfx90a::s59, output_vec_len ); + case 60: return makeRegisterExpression(amdgpu_gfx90a::s60, output_vec_len ); + case 61: return makeRegisterExpression(amdgpu_gfx90a::s61, output_vec_len ); + case 62: return makeRegisterExpression(amdgpu_gfx90a::s62, output_vec_len ); + case 63: return makeRegisterExpression(amdgpu_gfx90a::s63, output_vec_len ); + case 64: return makeRegisterExpression(amdgpu_gfx90a::s64, output_vec_len ); + case 65: return makeRegisterExpression(amdgpu_gfx90a::s65, output_vec_len ); + case 66: return makeRegisterExpression(amdgpu_gfx90a::s66, output_vec_len ); + case 67: return makeRegisterExpression(amdgpu_gfx90a::s67, output_vec_len ); + case 68: return makeRegisterExpression(amdgpu_gfx90a::s68, output_vec_len ); + case 69: return makeRegisterExpression(amdgpu_gfx90a::s69, output_vec_len ); + case 70: return makeRegisterExpression(amdgpu_gfx90a::s70, output_vec_len ); + case 71: return makeRegisterExpression(amdgpu_gfx90a::s71, output_vec_len ); + case 72: return makeRegisterExpression(amdgpu_gfx90a::s72, output_vec_len ); + case 73: return makeRegisterExpression(amdgpu_gfx90a::s73, output_vec_len ); + case 74: return makeRegisterExpression(amdgpu_gfx90a::s74, output_vec_len ); + case 75: return makeRegisterExpression(amdgpu_gfx90a::s75, output_vec_len ); + case 76: return makeRegisterExpression(amdgpu_gfx90a::s76, output_vec_len ); + case 77: return makeRegisterExpression(amdgpu_gfx90a::s77, output_vec_len ); + case 78: return makeRegisterExpression(amdgpu_gfx90a::s78, output_vec_len ); + case 79: return makeRegisterExpression(amdgpu_gfx90a::s79, output_vec_len ); + case 80: return makeRegisterExpression(amdgpu_gfx90a::s80, output_vec_len ); + case 81: return makeRegisterExpression(amdgpu_gfx90a::s81, output_vec_len ); + case 82: return makeRegisterExpression(amdgpu_gfx90a::s82, output_vec_len ); + case 83: return makeRegisterExpression(amdgpu_gfx90a::s83, output_vec_len ); + case 84: return makeRegisterExpression(amdgpu_gfx90a::s84, output_vec_len ); + case 85: return makeRegisterExpression(amdgpu_gfx90a::s85, output_vec_len ); + case 86: return makeRegisterExpression(amdgpu_gfx90a::s86, output_vec_len ); + case 87: return makeRegisterExpression(amdgpu_gfx90a::s87, output_vec_len ); + case 88: return makeRegisterExpression(amdgpu_gfx90a::s88, output_vec_len ); + case 89: return makeRegisterExpression(amdgpu_gfx90a::s89, output_vec_len ); + case 90: return makeRegisterExpression(amdgpu_gfx90a::s90, output_vec_len ); + case 91: return makeRegisterExpression(amdgpu_gfx90a::s91, output_vec_len ); + case 92: return makeRegisterExpression(amdgpu_gfx90a::s92, output_vec_len ); + case 93: return makeRegisterExpression(amdgpu_gfx90a::s93, output_vec_len ); + case 94: return makeRegisterExpression(amdgpu_gfx90a::s94, output_vec_len ); + case 95: return makeRegisterExpression(amdgpu_gfx90a::s95, output_vec_len ); + case 96: return makeRegisterExpression(amdgpu_gfx90a::s96, output_vec_len ); + case 97: return makeRegisterExpression(amdgpu_gfx90a::s97, output_vec_len ); + case 98: return makeRegisterExpression(amdgpu_gfx90a::s98, output_vec_len ); + case 99: return makeRegisterExpression(amdgpu_gfx90a::s99, output_vec_len ); + case 100: return makeRegisterExpression(amdgpu_gfx90a::s100, output_vec_len ); + case 101: return makeRegisterExpression(amdgpu_gfx90a::s101, output_vec_len ); + case 104: return makeRegisterExpression(amdgpu_gfx90a::xnack_mask_lo, output_vec_len ); + case 105: return makeRegisterExpression(amdgpu_gfx90a::xnack_mask_hi, output_vec_len ); + case 102: return makeRegisterExpression(amdgpu_gfx90a::flat_scratch_lo, output_vec_len ); + case 103: return makeRegisterExpression(amdgpu_gfx90a::flat_scratch_hi, output_vec_len ); + case 108: return makeRegisterExpression(amdgpu_gfx90a::ttmp0, output_vec_len ); + case 109: return makeRegisterExpression(amdgpu_gfx90a::ttmp1, output_vec_len ); + case 110: return makeRegisterExpression(amdgpu_gfx90a::ttmp2, output_vec_len ); + case 111: return makeRegisterExpression(amdgpu_gfx90a::ttmp3, output_vec_len ); + case 112: return makeRegisterExpression(amdgpu_gfx90a::ttmp4, output_vec_len ); + case 113: return makeRegisterExpression(amdgpu_gfx90a::ttmp5, output_vec_len ); + case 114: return makeRegisterExpression(amdgpu_gfx90a::ttmp6, output_vec_len ); + case 115: return makeRegisterExpression(amdgpu_gfx90a::ttmp7, output_vec_len ); + case 116: return makeRegisterExpression(amdgpu_gfx90a::ttmp8, output_vec_len ); + case 117: return makeRegisterExpression(amdgpu_gfx90a::ttmp9, output_vec_len ); + case 118: return makeRegisterExpression(amdgpu_gfx90a::ttmp10, output_vec_len ); + case 119: return makeRegisterExpression(amdgpu_gfx90a::ttmp11, output_vec_len ); + case 120: return makeRegisterExpression(amdgpu_gfx90a::ttmp12, output_vec_len ); + case 121: return makeRegisterExpression(amdgpu_gfx90a::ttmp13, output_vec_len ); + case 122: return makeRegisterExpression(amdgpu_gfx90a::ttmp14, output_vec_len ); + case 123: return makeRegisterExpression(amdgpu_gfx90a::ttmp15, output_vec_len ); + case 106: return makeRegisterExpression(amdgpu_gfx90a::vcc_lo, output_vec_len ); + case 107: return makeRegisterExpression(amdgpu_gfx90a::vcc_hi, output_vec_len ); + case 124: return makeRegisterExpression(amdgpu_gfx90a::m0, output_vec_len ); + case 126: return makeRegisterExpression(amdgpu_gfx90a::exec_lo, output_vec_len ); + case 127: return makeRegisterExpression(amdgpu_gfx90a::exec_hi, output_vec_len ); + case 128: return Immediate::makeImmediate(Result(u32, 0)); + case 129: return Immediate::makeImmediate(Result(u32, 1)); + case 130: return Immediate::makeImmediate(Result(u32, 2)); + case 131: return Immediate::makeImmediate(Result(u32, 3)); + case 132: return Immediate::makeImmediate(Result(u32, 4)); + case 133: return Immediate::makeImmediate(Result(u32, 5)); + case 134: return Immediate::makeImmediate(Result(u32, 6)); + case 135: return Immediate::makeImmediate(Result(u32, 7)); + case 136: return Immediate::makeImmediate(Result(u32, 8)); + case 137: return Immediate::makeImmediate(Result(u32, 9)); + case 138: return Immediate::makeImmediate(Result(u32, 10)); + case 139: return Immediate::makeImmediate(Result(u32, 11)); + case 140: return Immediate::makeImmediate(Result(u32, 12)); + case 141: return Immediate::makeImmediate(Result(u32, 13)); + case 142: return Immediate::makeImmediate(Result(u32, 14)); + case 143: return Immediate::makeImmediate(Result(u32, 15)); + case 144: return Immediate::makeImmediate(Result(u32, 16)); + case 145: return Immediate::makeImmediate(Result(u32, 17)); + case 146: return Immediate::makeImmediate(Result(u32, 18)); + case 147: return Immediate::makeImmediate(Result(u32, 19)); + case 148: return Immediate::makeImmediate(Result(u32, 20)); + case 149: return Immediate::makeImmediate(Result(u32, 21)); + case 150: return Immediate::makeImmediate(Result(u32, 22)); + case 151: return Immediate::makeImmediate(Result(u32, 23)); + case 152: return Immediate::makeImmediate(Result(u32, 24)); + case 153: return Immediate::makeImmediate(Result(u32, 25)); + case 154: return Immediate::makeImmediate(Result(u32, 26)); + case 155: return Immediate::makeImmediate(Result(u32, 27)); + case 156: return Immediate::makeImmediate(Result(u32, 28)); + case 157: return Immediate::makeImmediate(Result(u32, 29)); + case 158: return Immediate::makeImmediate(Result(u32, 30)); + case 159: return Immediate::makeImmediate(Result(u32, 31)); + case 160: return Immediate::makeImmediate(Result(u32, 32)); + case 161: return Immediate::makeImmediate(Result(u32, 33)); + case 162: return Immediate::makeImmediate(Result(u32, 34)); + case 163: return Immediate::makeImmediate(Result(u32, 35)); + case 164: return Immediate::makeImmediate(Result(u32, 36)); + case 165: return Immediate::makeImmediate(Result(u32, 37)); + case 166: return Immediate::makeImmediate(Result(u32, 38)); + case 167: return Immediate::makeImmediate(Result(u32, 39)); + case 168: return Immediate::makeImmediate(Result(u32, 40)); + case 169: return Immediate::makeImmediate(Result(u32, 41)); + case 170: return Immediate::makeImmediate(Result(u32, 42)); + case 171: return Immediate::makeImmediate(Result(u32, 43)); + case 172: return Immediate::makeImmediate(Result(u32, 44)); + case 173: return Immediate::makeImmediate(Result(u32, 45)); + case 174: return Immediate::makeImmediate(Result(u32, 46)); + case 175: return Immediate::makeImmediate(Result(u32, 47)); + case 176: return Immediate::makeImmediate(Result(u32, 48)); + case 177: return Immediate::makeImmediate(Result(u32, 49)); + case 178: return Immediate::makeImmediate(Result(u32, 50)); + case 179: return Immediate::makeImmediate(Result(u32, 51)); + case 180: return Immediate::makeImmediate(Result(u32, 52)); + case 181: return Immediate::makeImmediate(Result(u32, 53)); + case 182: return Immediate::makeImmediate(Result(u32, 54)); + case 183: return Immediate::makeImmediate(Result(u32, 55)); + case 184: return Immediate::makeImmediate(Result(u32, 56)); + case 185: return Immediate::makeImmediate(Result(u32, 57)); + case 186: return Immediate::makeImmediate(Result(u32, 58)); + case 187: return Immediate::makeImmediate(Result(u32, 59)); + case 188: return Immediate::makeImmediate(Result(u32, 60)); + case 189: return Immediate::makeImmediate(Result(u32, 61)); + case 190: return Immediate::makeImmediate(Result(u32, 62)); + case 191: return Immediate::makeImmediate(Result(u32, 63)); + case 192: return Immediate::makeImmediate(Result(u32, 64)); + case 193: return Immediate::makeImmediate(Result(u32, -1)); + case 194: return Immediate::makeImmediate(Result(u32, -2)); + case 195: return Immediate::makeImmediate(Result(u32, -3)); + case 196: return Immediate::makeImmediate(Result(u32, -4)); + case 197: return Immediate::makeImmediate(Result(u32, -5)); + case 198: return Immediate::makeImmediate(Result(u32, -6)); + case 199: return Immediate::makeImmediate(Result(u32, -7)); + case 200: return Immediate::makeImmediate(Result(u32, -8)); + case 201: return Immediate::makeImmediate(Result(u32, -9)); + case 202: return Immediate::makeImmediate(Result(u32, -10)); + case 203: return Immediate::makeImmediate(Result(u32, -11)); + case 204: return Immediate::makeImmediate(Result(u32, -12)); + case 205: return Immediate::makeImmediate(Result(u32, -13)); + case 206: return Immediate::makeImmediate(Result(u32, -14)); + case 207: return Immediate::makeImmediate(Result(u32, -15)); + case 208: return Immediate::makeImmediate(Result(u32, -16)); + case 240: return Immediate::makeImmediate(Result(sp_float, 0.5)); + case 241: return Immediate::makeImmediate(Result(sp_float, -0.5)); + case 242: return Immediate::makeImmediate(Result(sp_float, 1.0)); + case 243: return Immediate::makeImmediate(Result(sp_float, -1.0)); + case 244: return Immediate::makeImmediate(Result(sp_float, 2.0)); + case 245: return Immediate::makeImmediate(Result(sp_float, -2.0)); + case 246: return Immediate::makeImmediate(Result(sp_float, 4.0)); + case 247: return Immediate::makeImmediate(Result(sp_float, -4.0)); + case 248: return Immediate::makeImmediate(Result(sp_float, 0.15915494)); + case 251: return makeRegisterExpression(amdgpu_gfx90a::src_vccz, output_vec_len ); + case 252: return makeRegisterExpression(amdgpu_gfx90a::src_execz, output_vec_len ); + case 253: return makeRegisterExpression(amdgpu_gfx90a::src_scc, output_vec_len ); + case 235: return makeRegisterExpression(amdgpu_gfx90a::src_shared_base, output_vec_len ); + case 236: return makeRegisterExpression(amdgpu_gfx90a::src_shared_limit, output_vec_len ); + case 237: return makeRegisterExpression(amdgpu_gfx90a::src_private_base, output_vec_len ); + case 238: return makeRegisterExpression(amdgpu_gfx90a::src_private_limit, output_vec_len ); + case 239: return makeRegisterExpression(amdgpu_gfx90a::src_pops_exiting_wave_id, output_vec_len ); + case 256: return makeRegisterExpression(amdgpu_gfx90a::v0, output_vec_len ); + case 257: return makeRegisterExpression(amdgpu_gfx90a::v1, output_vec_len ); + case 258: return makeRegisterExpression(amdgpu_gfx90a::v2, output_vec_len ); + case 259: return makeRegisterExpression(amdgpu_gfx90a::v3, output_vec_len ); + case 260: return makeRegisterExpression(amdgpu_gfx90a::v4, output_vec_len ); + case 261: return makeRegisterExpression(amdgpu_gfx90a::v5, output_vec_len ); + case 262: return makeRegisterExpression(amdgpu_gfx90a::v6, output_vec_len ); + case 263: return makeRegisterExpression(amdgpu_gfx90a::v7, output_vec_len ); + case 264: return makeRegisterExpression(amdgpu_gfx90a::v8, output_vec_len ); + case 265: return makeRegisterExpression(amdgpu_gfx90a::v9, output_vec_len ); + case 266: return makeRegisterExpression(amdgpu_gfx90a::v10, output_vec_len ); + case 267: return makeRegisterExpression(amdgpu_gfx90a::v11, output_vec_len ); + case 268: return makeRegisterExpression(amdgpu_gfx90a::v12, output_vec_len ); + case 269: return makeRegisterExpression(amdgpu_gfx90a::v13, output_vec_len ); + case 270: return makeRegisterExpression(amdgpu_gfx90a::v14, output_vec_len ); + case 271: return makeRegisterExpression(amdgpu_gfx90a::v15, output_vec_len ); + case 272: return makeRegisterExpression(amdgpu_gfx90a::v16, output_vec_len ); + case 273: return makeRegisterExpression(amdgpu_gfx90a::v17, output_vec_len ); + case 274: return makeRegisterExpression(amdgpu_gfx90a::v18, output_vec_len ); + case 275: return makeRegisterExpression(amdgpu_gfx90a::v19, output_vec_len ); + case 276: return makeRegisterExpression(amdgpu_gfx90a::v20, output_vec_len ); + case 277: return makeRegisterExpression(amdgpu_gfx90a::v21, output_vec_len ); + case 278: return makeRegisterExpression(amdgpu_gfx90a::v22, output_vec_len ); + case 279: return makeRegisterExpression(amdgpu_gfx90a::v23, output_vec_len ); + case 280: return makeRegisterExpression(amdgpu_gfx90a::v24, output_vec_len ); + case 281: return makeRegisterExpression(amdgpu_gfx90a::v25, output_vec_len ); + case 282: return makeRegisterExpression(amdgpu_gfx90a::v26, output_vec_len ); + case 283: return makeRegisterExpression(amdgpu_gfx90a::v27, output_vec_len ); + case 284: return makeRegisterExpression(amdgpu_gfx90a::v28, output_vec_len ); + case 285: return makeRegisterExpression(amdgpu_gfx90a::v29, output_vec_len ); + case 286: return makeRegisterExpression(amdgpu_gfx90a::v30, output_vec_len ); + case 287: return makeRegisterExpression(amdgpu_gfx90a::v31, output_vec_len ); + case 288: return makeRegisterExpression(amdgpu_gfx90a::v32, output_vec_len ); + case 289: return makeRegisterExpression(amdgpu_gfx90a::v33, output_vec_len ); + case 290: return makeRegisterExpression(amdgpu_gfx90a::v34, output_vec_len ); + case 291: return makeRegisterExpression(amdgpu_gfx90a::v35, output_vec_len ); + case 292: return makeRegisterExpression(amdgpu_gfx90a::v36, output_vec_len ); + case 293: return makeRegisterExpression(amdgpu_gfx90a::v37, output_vec_len ); + case 294: return makeRegisterExpression(amdgpu_gfx90a::v38, output_vec_len ); + case 295: return makeRegisterExpression(amdgpu_gfx90a::v39, output_vec_len ); + case 296: return makeRegisterExpression(amdgpu_gfx90a::v40, output_vec_len ); + case 297: return makeRegisterExpression(amdgpu_gfx90a::v41, output_vec_len ); + case 298: return makeRegisterExpression(amdgpu_gfx90a::v42, output_vec_len ); + case 299: return makeRegisterExpression(amdgpu_gfx90a::v43, output_vec_len ); + case 300: return makeRegisterExpression(amdgpu_gfx90a::v44, output_vec_len ); + case 301: return makeRegisterExpression(amdgpu_gfx90a::v45, output_vec_len ); + case 302: return makeRegisterExpression(amdgpu_gfx90a::v46, output_vec_len ); + case 303: return makeRegisterExpression(amdgpu_gfx90a::v47, output_vec_len ); + case 304: return makeRegisterExpression(amdgpu_gfx90a::v48, output_vec_len ); + case 305: return makeRegisterExpression(amdgpu_gfx90a::v49, output_vec_len ); + case 306: return makeRegisterExpression(amdgpu_gfx90a::v50, output_vec_len ); + case 307: return makeRegisterExpression(amdgpu_gfx90a::v51, output_vec_len ); + case 308: return makeRegisterExpression(amdgpu_gfx90a::v52, output_vec_len ); + case 309: return makeRegisterExpression(amdgpu_gfx90a::v53, output_vec_len ); + case 310: return makeRegisterExpression(amdgpu_gfx90a::v54, output_vec_len ); + case 311: return makeRegisterExpression(amdgpu_gfx90a::v55, output_vec_len ); + case 312: return makeRegisterExpression(amdgpu_gfx90a::v56, output_vec_len ); + case 313: return makeRegisterExpression(amdgpu_gfx90a::v57, output_vec_len ); + case 314: return makeRegisterExpression(amdgpu_gfx90a::v58, output_vec_len ); + case 315: return makeRegisterExpression(amdgpu_gfx90a::v59, output_vec_len ); + case 316: return makeRegisterExpression(amdgpu_gfx90a::v60, output_vec_len ); + case 317: return makeRegisterExpression(amdgpu_gfx90a::v61, output_vec_len ); + case 318: return makeRegisterExpression(amdgpu_gfx90a::v62, output_vec_len ); + case 319: return makeRegisterExpression(amdgpu_gfx90a::v63, output_vec_len ); + case 320: return makeRegisterExpression(amdgpu_gfx90a::v64, output_vec_len ); + case 321: return makeRegisterExpression(amdgpu_gfx90a::v65, output_vec_len ); + case 322: return makeRegisterExpression(amdgpu_gfx90a::v66, output_vec_len ); + case 323: return makeRegisterExpression(amdgpu_gfx90a::v67, output_vec_len ); + case 324: return makeRegisterExpression(amdgpu_gfx90a::v68, output_vec_len ); + case 325: return makeRegisterExpression(amdgpu_gfx90a::v69, output_vec_len ); + case 326: return makeRegisterExpression(amdgpu_gfx90a::v70, output_vec_len ); + case 327: return makeRegisterExpression(amdgpu_gfx90a::v71, output_vec_len ); + case 328: return makeRegisterExpression(amdgpu_gfx90a::v72, output_vec_len ); + case 329: return makeRegisterExpression(amdgpu_gfx90a::v73, output_vec_len ); + case 330: return makeRegisterExpression(amdgpu_gfx90a::v74, output_vec_len ); + case 331: return makeRegisterExpression(amdgpu_gfx90a::v75, output_vec_len ); + case 332: return makeRegisterExpression(amdgpu_gfx90a::v76, output_vec_len ); + case 333: return makeRegisterExpression(amdgpu_gfx90a::v77, output_vec_len ); + case 334: return makeRegisterExpression(amdgpu_gfx90a::v78, output_vec_len ); + case 335: return makeRegisterExpression(amdgpu_gfx90a::v79, output_vec_len ); + case 336: return makeRegisterExpression(amdgpu_gfx90a::v80, output_vec_len ); + case 337: return makeRegisterExpression(amdgpu_gfx90a::v81, output_vec_len ); + case 338: return makeRegisterExpression(amdgpu_gfx90a::v82, output_vec_len ); + case 339: return makeRegisterExpression(amdgpu_gfx90a::v83, output_vec_len ); + case 340: return makeRegisterExpression(amdgpu_gfx90a::v84, output_vec_len ); + case 341: return makeRegisterExpression(amdgpu_gfx90a::v85, output_vec_len ); + case 342: return makeRegisterExpression(amdgpu_gfx90a::v86, output_vec_len ); + case 343: return makeRegisterExpression(amdgpu_gfx90a::v87, output_vec_len ); + case 344: return makeRegisterExpression(amdgpu_gfx90a::v88, output_vec_len ); + case 345: return makeRegisterExpression(amdgpu_gfx90a::v89, output_vec_len ); + case 346: return makeRegisterExpression(amdgpu_gfx90a::v90, output_vec_len ); + case 347: return makeRegisterExpression(amdgpu_gfx90a::v91, output_vec_len ); + case 348: return makeRegisterExpression(amdgpu_gfx90a::v92, output_vec_len ); + case 349: return makeRegisterExpression(amdgpu_gfx90a::v93, output_vec_len ); + case 350: return makeRegisterExpression(amdgpu_gfx90a::v94, output_vec_len ); + case 351: return makeRegisterExpression(amdgpu_gfx90a::v95, output_vec_len ); + case 352: return makeRegisterExpression(amdgpu_gfx90a::v96, output_vec_len ); + case 353: return makeRegisterExpression(amdgpu_gfx90a::v97, output_vec_len ); + case 354: return makeRegisterExpression(amdgpu_gfx90a::v98, output_vec_len ); + case 355: return makeRegisterExpression(amdgpu_gfx90a::v99, output_vec_len ); + case 356: return makeRegisterExpression(amdgpu_gfx90a::v100, output_vec_len ); + case 357: return makeRegisterExpression(amdgpu_gfx90a::v101, output_vec_len ); + case 358: return makeRegisterExpression(amdgpu_gfx90a::v102, output_vec_len ); + case 359: return makeRegisterExpression(amdgpu_gfx90a::v103, output_vec_len ); + case 360: return makeRegisterExpression(amdgpu_gfx90a::v104, output_vec_len ); + case 361: return makeRegisterExpression(amdgpu_gfx90a::v105, output_vec_len ); + case 362: return makeRegisterExpression(amdgpu_gfx90a::v106, output_vec_len ); + case 363: return makeRegisterExpression(amdgpu_gfx90a::v107, output_vec_len ); + case 364: return makeRegisterExpression(amdgpu_gfx90a::v108, output_vec_len ); + case 365: return makeRegisterExpression(amdgpu_gfx90a::v109, output_vec_len ); + case 366: return makeRegisterExpression(amdgpu_gfx90a::v110, output_vec_len ); + case 367: return makeRegisterExpression(amdgpu_gfx90a::v111, output_vec_len ); + case 368: return makeRegisterExpression(amdgpu_gfx90a::v112, output_vec_len ); + case 369: return makeRegisterExpression(amdgpu_gfx90a::v113, output_vec_len ); + case 370: return makeRegisterExpression(amdgpu_gfx90a::v114, output_vec_len ); + case 371: return makeRegisterExpression(amdgpu_gfx90a::v115, output_vec_len ); + case 372: return makeRegisterExpression(amdgpu_gfx90a::v116, output_vec_len ); + case 373: return makeRegisterExpression(amdgpu_gfx90a::v117, output_vec_len ); + case 374: return makeRegisterExpression(amdgpu_gfx90a::v118, output_vec_len ); + case 375: return makeRegisterExpression(amdgpu_gfx90a::v119, output_vec_len ); + case 376: return makeRegisterExpression(amdgpu_gfx90a::v120, output_vec_len ); + case 377: return makeRegisterExpression(amdgpu_gfx90a::v121, output_vec_len ); + case 378: return makeRegisterExpression(amdgpu_gfx90a::v122, output_vec_len ); + case 379: return makeRegisterExpression(amdgpu_gfx90a::v123, output_vec_len ); + case 380: return makeRegisterExpression(amdgpu_gfx90a::v124, output_vec_len ); + case 381: return makeRegisterExpression(amdgpu_gfx90a::v125, output_vec_len ); + case 382: return makeRegisterExpression(amdgpu_gfx90a::v126, output_vec_len ); + case 383: return makeRegisterExpression(amdgpu_gfx90a::v127, output_vec_len ); + case 384: return makeRegisterExpression(amdgpu_gfx90a::v128, output_vec_len ); + case 385: return makeRegisterExpression(amdgpu_gfx90a::v129, output_vec_len ); + case 386: return makeRegisterExpression(amdgpu_gfx90a::v130, output_vec_len ); + case 387: return makeRegisterExpression(amdgpu_gfx90a::v131, output_vec_len ); + case 388: return makeRegisterExpression(amdgpu_gfx90a::v132, output_vec_len ); + case 389: return makeRegisterExpression(amdgpu_gfx90a::v133, output_vec_len ); + case 390: return makeRegisterExpression(amdgpu_gfx90a::v134, output_vec_len ); + case 391: return makeRegisterExpression(amdgpu_gfx90a::v135, output_vec_len ); + case 392: return makeRegisterExpression(amdgpu_gfx90a::v136, output_vec_len ); + case 393: return makeRegisterExpression(amdgpu_gfx90a::v137, output_vec_len ); + case 394: return makeRegisterExpression(amdgpu_gfx90a::v138, output_vec_len ); + case 395: return makeRegisterExpression(amdgpu_gfx90a::v139, output_vec_len ); + case 396: return makeRegisterExpression(amdgpu_gfx90a::v140, output_vec_len ); + case 397: return makeRegisterExpression(amdgpu_gfx90a::v141, output_vec_len ); + case 398: return makeRegisterExpression(amdgpu_gfx90a::v142, output_vec_len ); + case 399: return makeRegisterExpression(amdgpu_gfx90a::v143, output_vec_len ); + case 400: return makeRegisterExpression(amdgpu_gfx90a::v144, output_vec_len ); + case 401: return makeRegisterExpression(amdgpu_gfx90a::v145, output_vec_len ); + case 402: return makeRegisterExpression(amdgpu_gfx90a::v146, output_vec_len ); + case 403: return makeRegisterExpression(amdgpu_gfx90a::v147, output_vec_len ); + case 404: return makeRegisterExpression(amdgpu_gfx90a::v148, output_vec_len ); + case 405: return makeRegisterExpression(amdgpu_gfx90a::v149, output_vec_len ); + case 406: return makeRegisterExpression(amdgpu_gfx90a::v150, output_vec_len ); + case 407: return makeRegisterExpression(amdgpu_gfx90a::v151, output_vec_len ); + case 408: return makeRegisterExpression(amdgpu_gfx90a::v152, output_vec_len ); + case 409: return makeRegisterExpression(amdgpu_gfx90a::v153, output_vec_len ); + case 410: return makeRegisterExpression(amdgpu_gfx90a::v154, output_vec_len ); + case 411: return makeRegisterExpression(amdgpu_gfx90a::v155, output_vec_len ); + case 412: return makeRegisterExpression(amdgpu_gfx90a::v156, output_vec_len ); + case 413: return makeRegisterExpression(amdgpu_gfx90a::v157, output_vec_len ); + case 414: return makeRegisterExpression(amdgpu_gfx90a::v158, output_vec_len ); + case 415: return makeRegisterExpression(amdgpu_gfx90a::v159, output_vec_len ); + case 416: return makeRegisterExpression(amdgpu_gfx90a::v160, output_vec_len ); + case 417: return makeRegisterExpression(amdgpu_gfx90a::v161, output_vec_len ); + case 418: return makeRegisterExpression(amdgpu_gfx90a::v162, output_vec_len ); + case 419: return makeRegisterExpression(amdgpu_gfx90a::v163, output_vec_len ); + case 420: return makeRegisterExpression(amdgpu_gfx90a::v164, output_vec_len ); + case 421: return makeRegisterExpression(amdgpu_gfx90a::v165, output_vec_len ); + case 422: return makeRegisterExpression(amdgpu_gfx90a::v166, output_vec_len ); + case 423: return makeRegisterExpression(amdgpu_gfx90a::v167, output_vec_len ); + case 424: return makeRegisterExpression(amdgpu_gfx90a::v168, output_vec_len ); + case 425: return makeRegisterExpression(amdgpu_gfx90a::v169, output_vec_len ); + case 426: return makeRegisterExpression(amdgpu_gfx90a::v170, output_vec_len ); + case 427: return makeRegisterExpression(amdgpu_gfx90a::v171, output_vec_len ); + case 428: return makeRegisterExpression(amdgpu_gfx90a::v172, output_vec_len ); + case 429: return makeRegisterExpression(amdgpu_gfx90a::v173, output_vec_len ); + case 430: return makeRegisterExpression(amdgpu_gfx90a::v174, output_vec_len ); + case 431: return makeRegisterExpression(amdgpu_gfx90a::v175, output_vec_len ); + case 432: return makeRegisterExpression(amdgpu_gfx90a::v176, output_vec_len ); + case 433: return makeRegisterExpression(amdgpu_gfx90a::v177, output_vec_len ); + case 434: return makeRegisterExpression(amdgpu_gfx90a::v178, output_vec_len ); + case 435: return makeRegisterExpression(amdgpu_gfx90a::v179, output_vec_len ); + case 436: return makeRegisterExpression(amdgpu_gfx90a::v180, output_vec_len ); + case 437: return makeRegisterExpression(amdgpu_gfx90a::v181, output_vec_len ); + case 438: return makeRegisterExpression(amdgpu_gfx90a::v182, output_vec_len ); + case 439: return makeRegisterExpression(amdgpu_gfx90a::v183, output_vec_len ); + case 440: return makeRegisterExpression(amdgpu_gfx90a::v184, output_vec_len ); + case 441: return makeRegisterExpression(amdgpu_gfx90a::v185, output_vec_len ); + case 442: return makeRegisterExpression(amdgpu_gfx90a::v186, output_vec_len ); + case 443: return makeRegisterExpression(amdgpu_gfx90a::v187, output_vec_len ); + case 444: return makeRegisterExpression(amdgpu_gfx90a::v188, output_vec_len ); + case 445: return makeRegisterExpression(amdgpu_gfx90a::v189, output_vec_len ); + case 446: return makeRegisterExpression(amdgpu_gfx90a::v190, output_vec_len ); + case 447: return makeRegisterExpression(amdgpu_gfx90a::v191, output_vec_len ); + case 448: return makeRegisterExpression(amdgpu_gfx90a::v192, output_vec_len ); + case 449: return makeRegisterExpression(amdgpu_gfx90a::v193, output_vec_len ); + case 450: return makeRegisterExpression(amdgpu_gfx90a::v194, output_vec_len ); + case 451: return makeRegisterExpression(amdgpu_gfx90a::v195, output_vec_len ); + case 452: return makeRegisterExpression(amdgpu_gfx90a::v196, output_vec_len ); + case 453: return makeRegisterExpression(amdgpu_gfx90a::v197, output_vec_len ); + case 454: return makeRegisterExpression(amdgpu_gfx90a::v198, output_vec_len ); + case 455: return makeRegisterExpression(amdgpu_gfx90a::v199, output_vec_len ); + case 456: return makeRegisterExpression(amdgpu_gfx90a::v200, output_vec_len ); + case 457: return makeRegisterExpression(amdgpu_gfx90a::v201, output_vec_len ); + case 458: return makeRegisterExpression(amdgpu_gfx90a::v202, output_vec_len ); + case 459: return makeRegisterExpression(amdgpu_gfx90a::v203, output_vec_len ); + case 460: return makeRegisterExpression(amdgpu_gfx90a::v204, output_vec_len ); + case 461: return makeRegisterExpression(amdgpu_gfx90a::v205, output_vec_len ); + case 462: return makeRegisterExpression(amdgpu_gfx90a::v206, output_vec_len ); + case 463: return makeRegisterExpression(amdgpu_gfx90a::v207, output_vec_len ); + case 464: return makeRegisterExpression(amdgpu_gfx90a::v208, output_vec_len ); + case 465: return makeRegisterExpression(amdgpu_gfx90a::v209, output_vec_len ); + case 466: return makeRegisterExpression(amdgpu_gfx90a::v210, output_vec_len ); + case 467: return makeRegisterExpression(amdgpu_gfx90a::v211, output_vec_len ); + case 468: return makeRegisterExpression(amdgpu_gfx90a::v212, output_vec_len ); + case 469: return makeRegisterExpression(amdgpu_gfx90a::v213, output_vec_len ); + case 470: return makeRegisterExpression(amdgpu_gfx90a::v214, output_vec_len ); + case 471: return makeRegisterExpression(amdgpu_gfx90a::v215, output_vec_len ); + case 472: return makeRegisterExpression(amdgpu_gfx90a::v216, output_vec_len ); + case 473: return makeRegisterExpression(amdgpu_gfx90a::v217, output_vec_len ); + case 474: return makeRegisterExpression(amdgpu_gfx90a::v218, output_vec_len ); + case 475: return makeRegisterExpression(amdgpu_gfx90a::v219, output_vec_len ); + case 476: return makeRegisterExpression(amdgpu_gfx90a::v220, output_vec_len ); + case 477: return makeRegisterExpression(amdgpu_gfx90a::v221, output_vec_len ); + case 478: return makeRegisterExpression(amdgpu_gfx90a::v222, output_vec_len ); + case 479: return makeRegisterExpression(amdgpu_gfx90a::v223, output_vec_len ); + case 480: return makeRegisterExpression(amdgpu_gfx90a::v224, output_vec_len ); + case 481: return makeRegisterExpression(amdgpu_gfx90a::v225, output_vec_len ); + case 482: return makeRegisterExpression(amdgpu_gfx90a::v226, output_vec_len ); + case 483: return makeRegisterExpression(amdgpu_gfx90a::v227, output_vec_len ); + case 484: return makeRegisterExpression(amdgpu_gfx90a::v228, output_vec_len ); + case 485: return makeRegisterExpression(amdgpu_gfx90a::v229, output_vec_len ); + case 486: return makeRegisterExpression(amdgpu_gfx90a::v230, output_vec_len ); + case 487: return makeRegisterExpression(amdgpu_gfx90a::v231, output_vec_len ); + case 488: return makeRegisterExpression(amdgpu_gfx90a::v232, output_vec_len ); + case 489: return makeRegisterExpression(amdgpu_gfx90a::v233, output_vec_len ); + case 490: return makeRegisterExpression(amdgpu_gfx90a::v234, output_vec_len ); + case 491: return makeRegisterExpression(amdgpu_gfx90a::v235, output_vec_len ); + case 492: return makeRegisterExpression(amdgpu_gfx90a::v236, output_vec_len ); + case 493: return makeRegisterExpression(amdgpu_gfx90a::v237, output_vec_len ); + case 494: return makeRegisterExpression(amdgpu_gfx90a::v238, output_vec_len ); + case 495: return makeRegisterExpression(amdgpu_gfx90a::v239, output_vec_len ); + case 496: return makeRegisterExpression(amdgpu_gfx90a::v240, output_vec_len ); + case 497: return makeRegisterExpression(amdgpu_gfx90a::v241, output_vec_len ); + case 498: return makeRegisterExpression(amdgpu_gfx90a::v242, output_vec_len ); + case 499: return makeRegisterExpression(amdgpu_gfx90a::v243, output_vec_len ); + case 500: return makeRegisterExpression(amdgpu_gfx90a::v244, output_vec_len ); + case 501: return makeRegisterExpression(amdgpu_gfx90a::v245, output_vec_len ); + case 502: return makeRegisterExpression(amdgpu_gfx90a::v246, output_vec_len ); + case 503: return makeRegisterExpression(amdgpu_gfx90a::v247, output_vec_len ); + case 504: return makeRegisterExpression(amdgpu_gfx90a::v248, output_vec_len ); + case 505: return makeRegisterExpression(amdgpu_gfx90a::v249, output_vec_len ); + case 506: return makeRegisterExpression(amdgpu_gfx90a::v250, output_vec_len ); + case 507: return makeRegisterExpression(amdgpu_gfx90a::v251, output_vec_len ); + case 508: return makeRegisterExpression(amdgpu_gfx90a::v252, output_vec_len ); + case 509: return makeRegisterExpression(amdgpu_gfx90a::v253, output_vec_len ); + case 510: return makeRegisterExpression(amdgpu_gfx90a::v254, output_vec_len ); + case 511: return makeRegisterExpression(amdgpu_gfx90a::v255, output_vec_len ); + case 255: return Immediate::makeImmediate(Result(u32,decodeOPR_LITERAL())); + case 249 : return decodeOPR_SDWA(); + default: return makeRegisterExpression(amdgpu_gfx90a::invalid); + } + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx90a::decodeOPR_SRC_NOLIT(uint64_t input, uint32_t output_vec_len) + { + switch (input) { + case 0: return makeRegisterExpression(amdgpu_gfx90a::s0, output_vec_len ); + case 1: return makeRegisterExpression(amdgpu_gfx90a::s1, output_vec_len ); + case 2: return makeRegisterExpression(amdgpu_gfx90a::s2, output_vec_len ); + case 3: return makeRegisterExpression(amdgpu_gfx90a::s3, output_vec_len ); + case 4: return makeRegisterExpression(amdgpu_gfx90a::s4, output_vec_len ); + case 5: return makeRegisterExpression(amdgpu_gfx90a::s5, output_vec_len ); + case 6: return makeRegisterExpression(amdgpu_gfx90a::s6, output_vec_len ); + case 7: return makeRegisterExpression(amdgpu_gfx90a::s7, output_vec_len ); + case 8: return makeRegisterExpression(amdgpu_gfx90a::s8, output_vec_len ); + case 9: return makeRegisterExpression(amdgpu_gfx90a::s9, output_vec_len ); + case 10: return makeRegisterExpression(amdgpu_gfx90a::s10, output_vec_len ); + case 11: return makeRegisterExpression(amdgpu_gfx90a::s11, output_vec_len ); + case 12: return makeRegisterExpression(amdgpu_gfx90a::s12, output_vec_len ); + case 13: return makeRegisterExpression(amdgpu_gfx90a::s13, output_vec_len ); + case 14: return makeRegisterExpression(amdgpu_gfx90a::s14, output_vec_len ); + case 15: return makeRegisterExpression(amdgpu_gfx90a::s15, output_vec_len ); + case 16: return makeRegisterExpression(amdgpu_gfx90a::s16, output_vec_len ); + case 17: return makeRegisterExpression(amdgpu_gfx90a::s17, output_vec_len ); + case 18: return makeRegisterExpression(amdgpu_gfx90a::s18, output_vec_len ); + case 19: return makeRegisterExpression(amdgpu_gfx90a::s19, output_vec_len ); + case 20: return makeRegisterExpression(amdgpu_gfx90a::s20, output_vec_len ); + case 21: return makeRegisterExpression(amdgpu_gfx90a::s21, output_vec_len ); + case 22: return makeRegisterExpression(amdgpu_gfx90a::s22, output_vec_len ); + case 23: return makeRegisterExpression(amdgpu_gfx90a::s23, output_vec_len ); + case 24: return makeRegisterExpression(amdgpu_gfx90a::s24, output_vec_len ); + case 25: return makeRegisterExpression(amdgpu_gfx90a::s25, output_vec_len ); + case 26: return makeRegisterExpression(amdgpu_gfx90a::s26, output_vec_len ); + case 27: return makeRegisterExpression(amdgpu_gfx90a::s27, output_vec_len ); + case 28: return makeRegisterExpression(amdgpu_gfx90a::s28, output_vec_len ); + case 29: return makeRegisterExpression(amdgpu_gfx90a::s29, output_vec_len ); + case 30: return makeRegisterExpression(amdgpu_gfx90a::s30, output_vec_len ); + case 31: return makeRegisterExpression(amdgpu_gfx90a::s31, output_vec_len ); + case 32: return makeRegisterExpression(amdgpu_gfx90a::s32, output_vec_len ); + case 33: return makeRegisterExpression(amdgpu_gfx90a::s33, output_vec_len ); + case 34: return makeRegisterExpression(amdgpu_gfx90a::s34, output_vec_len ); + case 35: return makeRegisterExpression(amdgpu_gfx90a::s35, output_vec_len ); + case 36: return makeRegisterExpression(amdgpu_gfx90a::s36, output_vec_len ); + case 37: return makeRegisterExpression(amdgpu_gfx90a::s37, output_vec_len ); + case 38: return makeRegisterExpression(amdgpu_gfx90a::s38, output_vec_len ); + case 39: return makeRegisterExpression(amdgpu_gfx90a::s39, output_vec_len ); + case 40: return makeRegisterExpression(amdgpu_gfx90a::s40, output_vec_len ); + case 41: return makeRegisterExpression(amdgpu_gfx90a::s41, output_vec_len ); + case 42: return makeRegisterExpression(amdgpu_gfx90a::s42, output_vec_len ); + case 43: return makeRegisterExpression(amdgpu_gfx90a::s43, output_vec_len ); + case 44: return makeRegisterExpression(amdgpu_gfx90a::s44, output_vec_len ); + case 45: return makeRegisterExpression(amdgpu_gfx90a::s45, output_vec_len ); + case 46: return makeRegisterExpression(amdgpu_gfx90a::s46, output_vec_len ); + case 47: return makeRegisterExpression(amdgpu_gfx90a::s47, output_vec_len ); + case 48: return makeRegisterExpression(amdgpu_gfx90a::s48, output_vec_len ); + case 49: return makeRegisterExpression(amdgpu_gfx90a::s49, output_vec_len ); + case 50: return makeRegisterExpression(amdgpu_gfx90a::s50, output_vec_len ); + case 51: return makeRegisterExpression(amdgpu_gfx90a::s51, output_vec_len ); + case 52: return makeRegisterExpression(amdgpu_gfx90a::s52, output_vec_len ); + case 53: return makeRegisterExpression(amdgpu_gfx90a::s53, output_vec_len ); + case 54: return makeRegisterExpression(amdgpu_gfx90a::s54, output_vec_len ); + case 55: return makeRegisterExpression(amdgpu_gfx90a::s55, output_vec_len ); + case 56: return makeRegisterExpression(amdgpu_gfx90a::s56, output_vec_len ); + case 57: return makeRegisterExpression(amdgpu_gfx90a::s57, output_vec_len ); + case 58: return makeRegisterExpression(amdgpu_gfx90a::s58, output_vec_len ); + case 59: return makeRegisterExpression(amdgpu_gfx90a::s59, output_vec_len ); + case 60: return makeRegisterExpression(amdgpu_gfx90a::s60, output_vec_len ); + case 61: return makeRegisterExpression(amdgpu_gfx90a::s61, output_vec_len ); + case 62: return makeRegisterExpression(amdgpu_gfx90a::s62, output_vec_len ); + case 63: return makeRegisterExpression(amdgpu_gfx90a::s63, output_vec_len ); + case 64: return makeRegisterExpression(amdgpu_gfx90a::s64, output_vec_len ); + case 65: return makeRegisterExpression(amdgpu_gfx90a::s65, output_vec_len ); + case 66: return makeRegisterExpression(amdgpu_gfx90a::s66, output_vec_len ); + case 67: return makeRegisterExpression(amdgpu_gfx90a::s67, output_vec_len ); + case 68: return makeRegisterExpression(amdgpu_gfx90a::s68, output_vec_len ); + case 69: return makeRegisterExpression(amdgpu_gfx90a::s69, output_vec_len ); + case 70: return makeRegisterExpression(amdgpu_gfx90a::s70, output_vec_len ); + case 71: return makeRegisterExpression(amdgpu_gfx90a::s71, output_vec_len ); + case 72: return makeRegisterExpression(amdgpu_gfx90a::s72, output_vec_len ); + case 73: return makeRegisterExpression(amdgpu_gfx90a::s73, output_vec_len ); + case 74: return makeRegisterExpression(amdgpu_gfx90a::s74, output_vec_len ); + case 75: return makeRegisterExpression(amdgpu_gfx90a::s75, output_vec_len ); + case 76: return makeRegisterExpression(amdgpu_gfx90a::s76, output_vec_len ); + case 77: return makeRegisterExpression(amdgpu_gfx90a::s77, output_vec_len ); + case 78: return makeRegisterExpression(amdgpu_gfx90a::s78, output_vec_len ); + case 79: return makeRegisterExpression(amdgpu_gfx90a::s79, output_vec_len ); + case 80: return makeRegisterExpression(amdgpu_gfx90a::s80, output_vec_len ); + case 81: return makeRegisterExpression(amdgpu_gfx90a::s81, output_vec_len ); + case 82: return makeRegisterExpression(amdgpu_gfx90a::s82, output_vec_len ); + case 83: return makeRegisterExpression(amdgpu_gfx90a::s83, output_vec_len ); + case 84: return makeRegisterExpression(amdgpu_gfx90a::s84, output_vec_len ); + case 85: return makeRegisterExpression(amdgpu_gfx90a::s85, output_vec_len ); + case 86: return makeRegisterExpression(amdgpu_gfx90a::s86, output_vec_len ); + case 87: return makeRegisterExpression(amdgpu_gfx90a::s87, output_vec_len ); + case 88: return makeRegisterExpression(amdgpu_gfx90a::s88, output_vec_len ); + case 89: return makeRegisterExpression(amdgpu_gfx90a::s89, output_vec_len ); + case 90: return makeRegisterExpression(amdgpu_gfx90a::s90, output_vec_len ); + case 91: return makeRegisterExpression(amdgpu_gfx90a::s91, output_vec_len ); + case 92: return makeRegisterExpression(amdgpu_gfx90a::s92, output_vec_len ); + case 93: return makeRegisterExpression(amdgpu_gfx90a::s93, output_vec_len ); + case 94: return makeRegisterExpression(amdgpu_gfx90a::s94, output_vec_len ); + case 95: return makeRegisterExpression(amdgpu_gfx90a::s95, output_vec_len ); + case 96: return makeRegisterExpression(amdgpu_gfx90a::s96, output_vec_len ); + case 97: return makeRegisterExpression(amdgpu_gfx90a::s97, output_vec_len ); + case 98: return makeRegisterExpression(amdgpu_gfx90a::s98, output_vec_len ); + case 99: return makeRegisterExpression(amdgpu_gfx90a::s99, output_vec_len ); + case 100: return makeRegisterExpression(amdgpu_gfx90a::s100, output_vec_len ); + case 101: return makeRegisterExpression(amdgpu_gfx90a::s101, output_vec_len ); + case 104: return makeRegisterExpression(amdgpu_gfx90a::xnack_mask_lo, output_vec_len ); + case 105: return makeRegisterExpression(amdgpu_gfx90a::xnack_mask_hi, output_vec_len ); + case 102: return makeRegisterExpression(amdgpu_gfx90a::flat_scratch_lo, output_vec_len ); + case 103: return makeRegisterExpression(amdgpu_gfx90a::flat_scratch_hi, output_vec_len ); + case 108: return makeRegisterExpression(amdgpu_gfx90a::ttmp0, output_vec_len ); + case 109: return makeRegisterExpression(amdgpu_gfx90a::ttmp1, output_vec_len ); + case 110: return makeRegisterExpression(amdgpu_gfx90a::ttmp2, output_vec_len ); + case 111: return makeRegisterExpression(amdgpu_gfx90a::ttmp3, output_vec_len ); + case 112: return makeRegisterExpression(amdgpu_gfx90a::ttmp4, output_vec_len ); + case 113: return makeRegisterExpression(amdgpu_gfx90a::ttmp5, output_vec_len ); + case 114: return makeRegisterExpression(amdgpu_gfx90a::ttmp6, output_vec_len ); + case 115: return makeRegisterExpression(amdgpu_gfx90a::ttmp7, output_vec_len ); + case 116: return makeRegisterExpression(amdgpu_gfx90a::ttmp8, output_vec_len ); + case 117: return makeRegisterExpression(amdgpu_gfx90a::ttmp9, output_vec_len ); + case 118: return makeRegisterExpression(amdgpu_gfx90a::ttmp10, output_vec_len ); + case 119: return makeRegisterExpression(amdgpu_gfx90a::ttmp11, output_vec_len ); + case 120: return makeRegisterExpression(amdgpu_gfx90a::ttmp12, output_vec_len ); + case 121: return makeRegisterExpression(amdgpu_gfx90a::ttmp13, output_vec_len ); + case 122: return makeRegisterExpression(amdgpu_gfx90a::ttmp14, output_vec_len ); + case 123: return makeRegisterExpression(amdgpu_gfx90a::ttmp15, output_vec_len ); + case 106: return makeRegisterExpression(amdgpu_gfx90a::vcc_lo, output_vec_len ); + case 107: return makeRegisterExpression(amdgpu_gfx90a::vcc_hi, output_vec_len ); + case 124: return makeRegisterExpression(amdgpu_gfx90a::m0, output_vec_len ); + case 126: return makeRegisterExpression(amdgpu_gfx90a::exec_lo, output_vec_len ); + case 127: return makeRegisterExpression(amdgpu_gfx90a::exec_hi, output_vec_len ); + case 128: return Immediate::makeImmediate(Result(u32, 0)); + case 129: return Immediate::makeImmediate(Result(u32, 1)); + case 130: return Immediate::makeImmediate(Result(u32, 2)); + case 131: return Immediate::makeImmediate(Result(u32, 3)); + case 132: return Immediate::makeImmediate(Result(u32, 4)); + case 133: return Immediate::makeImmediate(Result(u32, 5)); + case 134: return Immediate::makeImmediate(Result(u32, 6)); + case 135: return Immediate::makeImmediate(Result(u32, 7)); + case 136: return Immediate::makeImmediate(Result(u32, 8)); + case 137: return Immediate::makeImmediate(Result(u32, 9)); + case 138: return Immediate::makeImmediate(Result(u32, 10)); + case 139: return Immediate::makeImmediate(Result(u32, 11)); + case 140: return Immediate::makeImmediate(Result(u32, 12)); + case 141: return Immediate::makeImmediate(Result(u32, 13)); + case 142: return Immediate::makeImmediate(Result(u32, 14)); + case 143: return Immediate::makeImmediate(Result(u32, 15)); + case 144: return Immediate::makeImmediate(Result(u32, 16)); + case 145: return Immediate::makeImmediate(Result(u32, 17)); + case 146: return Immediate::makeImmediate(Result(u32, 18)); + case 147: return Immediate::makeImmediate(Result(u32, 19)); + case 148: return Immediate::makeImmediate(Result(u32, 20)); + case 149: return Immediate::makeImmediate(Result(u32, 21)); + case 150: return Immediate::makeImmediate(Result(u32, 22)); + case 151: return Immediate::makeImmediate(Result(u32, 23)); + case 152: return Immediate::makeImmediate(Result(u32, 24)); + case 153: return Immediate::makeImmediate(Result(u32, 25)); + case 154: return Immediate::makeImmediate(Result(u32, 26)); + case 155: return Immediate::makeImmediate(Result(u32, 27)); + case 156: return Immediate::makeImmediate(Result(u32, 28)); + case 157: return Immediate::makeImmediate(Result(u32, 29)); + case 158: return Immediate::makeImmediate(Result(u32, 30)); + case 159: return Immediate::makeImmediate(Result(u32, 31)); + case 160: return Immediate::makeImmediate(Result(u32, 32)); + case 161: return Immediate::makeImmediate(Result(u32, 33)); + case 162: return Immediate::makeImmediate(Result(u32, 34)); + case 163: return Immediate::makeImmediate(Result(u32, 35)); + case 164: return Immediate::makeImmediate(Result(u32, 36)); + case 165: return Immediate::makeImmediate(Result(u32, 37)); + case 166: return Immediate::makeImmediate(Result(u32, 38)); + case 167: return Immediate::makeImmediate(Result(u32, 39)); + case 168: return Immediate::makeImmediate(Result(u32, 40)); + case 169: return Immediate::makeImmediate(Result(u32, 41)); + case 170: return Immediate::makeImmediate(Result(u32, 42)); + case 171: return Immediate::makeImmediate(Result(u32, 43)); + case 172: return Immediate::makeImmediate(Result(u32, 44)); + case 173: return Immediate::makeImmediate(Result(u32, 45)); + case 174: return Immediate::makeImmediate(Result(u32, 46)); + case 175: return Immediate::makeImmediate(Result(u32, 47)); + case 176: return Immediate::makeImmediate(Result(u32, 48)); + case 177: return Immediate::makeImmediate(Result(u32, 49)); + case 178: return Immediate::makeImmediate(Result(u32, 50)); + case 179: return Immediate::makeImmediate(Result(u32, 51)); + case 180: return Immediate::makeImmediate(Result(u32, 52)); + case 181: return Immediate::makeImmediate(Result(u32, 53)); + case 182: return Immediate::makeImmediate(Result(u32, 54)); + case 183: return Immediate::makeImmediate(Result(u32, 55)); + case 184: return Immediate::makeImmediate(Result(u32, 56)); + case 185: return Immediate::makeImmediate(Result(u32, 57)); + case 186: return Immediate::makeImmediate(Result(u32, 58)); + case 187: return Immediate::makeImmediate(Result(u32, 59)); + case 188: return Immediate::makeImmediate(Result(u32, 60)); + case 189: return Immediate::makeImmediate(Result(u32, 61)); + case 190: return Immediate::makeImmediate(Result(u32, 62)); + case 191: return Immediate::makeImmediate(Result(u32, 63)); + case 192: return Immediate::makeImmediate(Result(u32, 64)); + case 193: return Immediate::makeImmediate(Result(u32, -1)); + case 194: return Immediate::makeImmediate(Result(u32, -2)); + case 195: return Immediate::makeImmediate(Result(u32, -3)); + case 196: return Immediate::makeImmediate(Result(u32, -4)); + case 197: return Immediate::makeImmediate(Result(u32, -5)); + case 198: return Immediate::makeImmediate(Result(u32, -6)); + case 199: return Immediate::makeImmediate(Result(u32, -7)); + case 200: return Immediate::makeImmediate(Result(u32, -8)); + case 201: return Immediate::makeImmediate(Result(u32, -9)); + case 202: return Immediate::makeImmediate(Result(u32, -10)); + case 203: return Immediate::makeImmediate(Result(u32, -11)); + case 204: return Immediate::makeImmediate(Result(u32, -12)); + case 205: return Immediate::makeImmediate(Result(u32, -13)); + case 206: return Immediate::makeImmediate(Result(u32, -14)); + case 207: return Immediate::makeImmediate(Result(u32, -15)); + case 208: return Immediate::makeImmediate(Result(u32, -16)); + case 240: return Immediate::makeImmediate(Result(sp_float, 0.5)); + case 241: return Immediate::makeImmediate(Result(sp_float, -0.5)); + case 242: return Immediate::makeImmediate(Result(sp_float, 1.0)); + case 243: return Immediate::makeImmediate(Result(sp_float, -1.0)); + case 244: return Immediate::makeImmediate(Result(sp_float, 2.0)); + case 245: return Immediate::makeImmediate(Result(sp_float, -2.0)); + case 246: return Immediate::makeImmediate(Result(sp_float, 4.0)); + case 247: return Immediate::makeImmediate(Result(sp_float, -4.0)); + case 248: return Immediate::makeImmediate(Result(sp_float, 0.15915494)); + case 251: return makeRegisterExpression(amdgpu_gfx90a::src_vccz, output_vec_len ); + case 252: return makeRegisterExpression(amdgpu_gfx90a::src_execz, output_vec_len ); + case 253: return makeRegisterExpression(amdgpu_gfx90a::src_scc, output_vec_len ); + case 235: return makeRegisterExpression(amdgpu_gfx90a::src_shared_base, output_vec_len ); + case 236: return makeRegisterExpression(amdgpu_gfx90a::src_shared_limit, output_vec_len ); + case 237: return makeRegisterExpression(amdgpu_gfx90a::src_private_base, output_vec_len ); + case 238: return makeRegisterExpression(amdgpu_gfx90a::src_private_limit, output_vec_len ); + case 239: return makeRegisterExpression(amdgpu_gfx90a::src_pops_exiting_wave_id, output_vec_len ); + case 256: return makeRegisterExpression(amdgpu_gfx90a::v0, output_vec_len ); + case 257: return makeRegisterExpression(amdgpu_gfx90a::v1, output_vec_len ); + case 258: return makeRegisterExpression(amdgpu_gfx90a::v2, output_vec_len ); + case 259: return makeRegisterExpression(amdgpu_gfx90a::v3, output_vec_len ); + case 260: return makeRegisterExpression(amdgpu_gfx90a::v4, output_vec_len ); + case 261: return makeRegisterExpression(amdgpu_gfx90a::v5, output_vec_len ); + case 262: return makeRegisterExpression(amdgpu_gfx90a::v6, output_vec_len ); + case 263: return makeRegisterExpression(amdgpu_gfx90a::v7, output_vec_len ); + case 264: return makeRegisterExpression(amdgpu_gfx90a::v8, output_vec_len ); + case 265: return makeRegisterExpression(amdgpu_gfx90a::v9, output_vec_len ); + case 266: return makeRegisterExpression(amdgpu_gfx90a::v10, output_vec_len ); + case 267: return makeRegisterExpression(amdgpu_gfx90a::v11, output_vec_len ); + case 268: return makeRegisterExpression(amdgpu_gfx90a::v12, output_vec_len ); + case 269: return makeRegisterExpression(amdgpu_gfx90a::v13, output_vec_len ); + case 270: return makeRegisterExpression(amdgpu_gfx90a::v14, output_vec_len ); + case 271: return makeRegisterExpression(amdgpu_gfx90a::v15, output_vec_len ); + case 272: return makeRegisterExpression(amdgpu_gfx90a::v16, output_vec_len ); + case 273: return makeRegisterExpression(amdgpu_gfx90a::v17, output_vec_len ); + case 274: return makeRegisterExpression(amdgpu_gfx90a::v18, output_vec_len ); + case 275: return makeRegisterExpression(amdgpu_gfx90a::v19, output_vec_len ); + case 276: return makeRegisterExpression(amdgpu_gfx90a::v20, output_vec_len ); + case 277: return makeRegisterExpression(amdgpu_gfx90a::v21, output_vec_len ); + case 278: return makeRegisterExpression(amdgpu_gfx90a::v22, output_vec_len ); + case 279: return makeRegisterExpression(amdgpu_gfx90a::v23, output_vec_len ); + case 280: return makeRegisterExpression(amdgpu_gfx90a::v24, output_vec_len ); + case 281: return makeRegisterExpression(amdgpu_gfx90a::v25, output_vec_len ); + case 282: return makeRegisterExpression(amdgpu_gfx90a::v26, output_vec_len ); + case 283: return makeRegisterExpression(amdgpu_gfx90a::v27, output_vec_len ); + case 284: return makeRegisterExpression(amdgpu_gfx90a::v28, output_vec_len ); + case 285: return makeRegisterExpression(amdgpu_gfx90a::v29, output_vec_len ); + case 286: return makeRegisterExpression(amdgpu_gfx90a::v30, output_vec_len ); + case 287: return makeRegisterExpression(amdgpu_gfx90a::v31, output_vec_len ); + case 288: return makeRegisterExpression(amdgpu_gfx90a::v32, output_vec_len ); + case 289: return makeRegisterExpression(amdgpu_gfx90a::v33, output_vec_len ); + case 290: return makeRegisterExpression(amdgpu_gfx90a::v34, output_vec_len ); + case 291: return makeRegisterExpression(amdgpu_gfx90a::v35, output_vec_len ); + case 292: return makeRegisterExpression(amdgpu_gfx90a::v36, output_vec_len ); + case 293: return makeRegisterExpression(amdgpu_gfx90a::v37, output_vec_len ); + case 294: return makeRegisterExpression(amdgpu_gfx90a::v38, output_vec_len ); + case 295: return makeRegisterExpression(amdgpu_gfx90a::v39, output_vec_len ); + case 296: return makeRegisterExpression(amdgpu_gfx90a::v40, output_vec_len ); + case 297: return makeRegisterExpression(amdgpu_gfx90a::v41, output_vec_len ); + case 298: return makeRegisterExpression(amdgpu_gfx90a::v42, output_vec_len ); + case 299: return makeRegisterExpression(amdgpu_gfx90a::v43, output_vec_len ); + case 300: return makeRegisterExpression(amdgpu_gfx90a::v44, output_vec_len ); + case 301: return makeRegisterExpression(amdgpu_gfx90a::v45, output_vec_len ); + case 302: return makeRegisterExpression(amdgpu_gfx90a::v46, output_vec_len ); + case 303: return makeRegisterExpression(amdgpu_gfx90a::v47, output_vec_len ); + case 304: return makeRegisterExpression(amdgpu_gfx90a::v48, output_vec_len ); + case 305: return makeRegisterExpression(amdgpu_gfx90a::v49, output_vec_len ); + case 306: return makeRegisterExpression(amdgpu_gfx90a::v50, output_vec_len ); + case 307: return makeRegisterExpression(amdgpu_gfx90a::v51, output_vec_len ); + case 308: return makeRegisterExpression(amdgpu_gfx90a::v52, output_vec_len ); + case 309: return makeRegisterExpression(amdgpu_gfx90a::v53, output_vec_len ); + case 310: return makeRegisterExpression(amdgpu_gfx90a::v54, output_vec_len ); + case 311: return makeRegisterExpression(amdgpu_gfx90a::v55, output_vec_len ); + case 312: return makeRegisterExpression(amdgpu_gfx90a::v56, output_vec_len ); + case 313: return makeRegisterExpression(amdgpu_gfx90a::v57, output_vec_len ); + case 314: return makeRegisterExpression(amdgpu_gfx90a::v58, output_vec_len ); + case 315: return makeRegisterExpression(amdgpu_gfx90a::v59, output_vec_len ); + case 316: return makeRegisterExpression(amdgpu_gfx90a::v60, output_vec_len ); + case 317: return makeRegisterExpression(amdgpu_gfx90a::v61, output_vec_len ); + case 318: return makeRegisterExpression(amdgpu_gfx90a::v62, output_vec_len ); + case 319: return makeRegisterExpression(amdgpu_gfx90a::v63, output_vec_len ); + case 320: return makeRegisterExpression(amdgpu_gfx90a::v64, output_vec_len ); + case 321: return makeRegisterExpression(amdgpu_gfx90a::v65, output_vec_len ); + case 322: return makeRegisterExpression(amdgpu_gfx90a::v66, output_vec_len ); + case 323: return makeRegisterExpression(amdgpu_gfx90a::v67, output_vec_len ); + case 324: return makeRegisterExpression(amdgpu_gfx90a::v68, output_vec_len ); + case 325: return makeRegisterExpression(amdgpu_gfx90a::v69, output_vec_len ); + case 326: return makeRegisterExpression(amdgpu_gfx90a::v70, output_vec_len ); + case 327: return makeRegisterExpression(amdgpu_gfx90a::v71, output_vec_len ); + case 328: return makeRegisterExpression(amdgpu_gfx90a::v72, output_vec_len ); + case 329: return makeRegisterExpression(amdgpu_gfx90a::v73, output_vec_len ); + case 330: return makeRegisterExpression(amdgpu_gfx90a::v74, output_vec_len ); + case 331: return makeRegisterExpression(amdgpu_gfx90a::v75, output_vec_len ); + case 332: return makeRegisterExpression(amdgpu_gfx90a::v76, output_vec_len ); + case 333: return makeRegisterExpression(amdgpu_gfx90a::v77, output_vec_len ); + case 334: return makeRegisterExpression(amdgpu_gfx90a::v78, output_vec_len ); + case 335: return makeRegisterExpression(amdgpu_gfx90a::v79, output_vec_len ); + case 336: return makeRegisterExpression(amdgpu_gfx90a::v80, output_vec_len ); + case 337: return makeRegisterExpression(amdgpu_gfx90a::v81, output_vec_len ); + case 338: return makeRegisterExpression(amdgpu_gfx90a::v82, output_vec_len ); + case 339: return makeRegisterExpression(amdgpu_gfx90a::v83, output_vec_len ); + case 340: return makeRegisterExpression(amdgpu_gfx90a::v84, output_vec_len ); + case 341: return makeRegisterExpression(amdgpu_gfx90a::v85, output_vec_len ); + case 342: return makeRegisterExpression(amdgpu_gfx90a::v86, output_vec_len ); + case 343: return makeRegisterExpression(amdgpu_gfx90a::v87, output_vec_len ); + case 344: return makeRegisterExpression(amdgpu_gfx90a::v88, output_vec_len ); + case 345: return makeRegisterExpression(amdgpu_gfx90a::v89, output_vec_len ); + case 346: return makeRegisterExpression(amdgpu_gfx90a::v90, output_vec_len ); + case 347: return makeRegisterExpression(amdgpu_gfx90a::v91, output_vec_len ); + case 348: return makeRegisterExpression(amdgpu_gfx90a::v92, output_vec_len ); + case 349: return makeRegisterExpression(amdgpu_gfx90a::v93, output_vec_len ); + case 350: return makeRegisterExpression(amdgpu_gfx90a::v94, output_vec_len ); + case 351: return makeRegisterExpression(amdgpu_gfx90a::v95, output_vec_len ); + case 352: return makeRegisterExpression(amdgpu_gfx90a::v96, output_vec_len ); + case 353: return makeRegisterExpression(amdgpu_gfx90a::v97, output_vec_len ); + case 354: return makeRegisterExpression(amdgpu_gfx90a::v98, output_vec_len ); + case 355: return makeRegisterExpression(amdgpu_gfx90a::v99, output_vec_len ); + case 356: return makeRegisterExpression(amdgpu_gfx90a::v100, output_vec_len ); + case 357: return makeRegisterExpression(amdgpu_gfx90a::v101, output_vec_len ); + case 358: return makeRegisterExpression(amdgpu_gfx90a::v102, output_vec_len ); + case 359: return makeRegisterExpression(amdgpu_gfx90a::v103, output_vec_len ); + case 360: return makeRegisterExpression(amdgpu_gfx90a::v104, output_vec_len ); + case 361: return makeRegisterExpression(amdgpu_gfx90a::v105, output_vec_len ); + case 362: return makeRegisterExpression(amdgpu_gfx90a::v106, output_vec_len ); + case 363: return makeRegisterExpression(amdgpu_gfx90a::v107, output_vec_len ); + case 364: return makeRegisterExpression(amdgpu_gfx90a::v108, output_vec_len ); + case 365: return makeRegisterExpression(amdgpu_gfx90a::v109, output_vec_len ); + case 366: return makeRegisterExpression(amdgpu_gfx90a::v110, output_vec_len ); + case 367: return makeRegisterExpression(amdgpu_gfx90a::v111, output_vec_len ); + case 368: return makeRegisterExpression(amdgpu_gfx90a::v112, output_vec_len ); + case 369: return makeRegisterExpression(amdgpu_gfx90a::v113, output_vec_len ); + case 370: return makeRegisterExpression(amdgpu_gfx90a::v114, output_vec_len ); + case 371: return makeRegisterExpression(amdgpu_gfx90a::v115, output_vec_len ); + case 372: return makeRegisterExpression(amdgpu_gfx90a::v116, output_vec_len ); + case 373: return makeRegisterExpression(amdgpu_gfx90a::v117, output_vec_len ); + case 374: return makeRegisterExpression(amdgpu_gfx90a::v118, output_vec_len ); + case 375: return makeRegisterExpression(amdgpu_gfx90a::v119, output_vec_len ); + case 376: return makeRegisterExpression(amdgpu_gfx90a::v120, output_vec_len ); + case 377: return makeRegisterExpression(amdgpu_gfx90a::v121, output_vec_len ); + case 378: return makeRegisterExpression(amdgpu_gfx90a::v122, output_vec_len ); + case 379: return makeRegisterExpression(amdgpu_gfx90a::v123, output_vec_len ); + case 380: return makeRegisterExpression(amdgpu_gfx90a::v124, output_vec_len ); + case 381: return makeRegisterExpression(amdgpu_gfx90a::v125, output_vec_len ); + case 382: return makeRegisterExpression(amdgpu_gfx90a::v126, output_vec_len ); + case 383: return makeRegisterExpression(amdgpu_gfx90a::v127, output_vec_len ); + case 384: return makeRegisterExpression(amdgpu_gfx90a::v128, output_vec_len ); + case 385: return makeRegisterExpression(amdgpu_gfx90a::v129, output_vec_len ); + case 386: return makeRegisterExpression(amdgpu_gfx90a::v130, output_vec_len ); + case 387: return makeRegisterExpression(amdgpu_gfx90a::v131, output_vec_len ); + case 388: return makeRegisterExpression(amdgpu_gfx90a::v132, output_vec_len ); + case 389: return makeRegisterExpression(amdgpu_gfx90a::v133, output_vec_len ); + case 390: return makeRegisterExpression(amdgpu_gfx90a::v134, output_vec_len ); + case 391: return makeRegisterExpression(amdgpu_gfx90a::v135, output_vec_len ); + case 392: return makeRegisterExpression(amdgpu_gfx90a::v136, output_vec_len ); + case 393: return makeRegisterExpression(amdgpu_gfx90a::v137, output_vec_len ); + case 394: return makeRegisterExpression(amdgpu_gfx90a::v138, output_vec_len ); + case 395: return makeRegisterExpression(amdgpu_gfx90a::v139, output_vec_len ); + case 396: return makeRegisterExpression(amdgpu_gfx90a::v140, output_vec_len ); + case 397: return makeRegisterExpression(amdgpu_gfx90a::v141, output_vec_len ); + case 398: return makeRegisterExpression(amdgpu_gfx90a::v142, output_vec_len ); + case 399: return makeRegisterExpression(amdgpu_gfx90a::v143, output_vec_len ); + case 400: return makeRegisterExpression(amdgpu_gfx90a::v144, output_vec_len ); + case 401: return makeRegisterExpression(amdgpu_gfx90a::v145, output_vec_len ); + case 402: return makeRegisterExpression(amdgpu_gfx90a::v146, output_vec_len ); + case 403: return makeRegisterExpression(amdgpu_gfx90a::v147, output_vec_len ); + case 404: return makeRegisterExpression(amdgpu_gfx90a::v148, output_vec_len ); + case 405: return makeRegisterExpression(amdgpu_gfx90a::v149, output_vec_len ); + case 406: return makeRegisterExpression(amdgpu_gfx90a::v150, output_vec_len ); + case 407: return makeRegisterExpression(amdgpu_gfx90a::v151, output_vec_len ); + case 408: return makeRegisterExpression(amdgpu_gfx90a::v152, output_vec_len ); + case 409: return makeRegisterExpression(amdgpu_gfx90a::v153, output_vec_len ); + case 410: return makeRegisterExpression(amdgpu_gfx90a::v154, output_vec_len ); + case 411: return makeRegisterExpression(amdgpu_gfx90a::v155, output_vec_len ); + case 412: return makeRegisterExpression(amdgpu_gfx90a::v156, output_vec_len ); + case 413: return makeRegisterExpression(amdgpu_gfx90a::v157, output_vec_len ); + case 414: return makeRegisterExpression(amdgpu_gfx90a::v158, output_vec_len ); + case 415: return makeRegisterExpression(amdgpu_gfx90a::v159, output_vec_len ); + case 416: return makeRegisterExpression(amdgpu_gfx90a::v160, output_vec_len ); + case 417: return makeRegisterExpression(amdgpu_gfx90a::v161, output_vec_len ); + case 418: return makeRegisterExpression(amdgpu_gfx90a::v162, output_vec_len ); + case 419: return makeRegisterExpression(amdgpu_gfx90a::v163, output_vec_len ); + case 420: return makeRegisterExpression(amdgpu_gfx90a::v164, output_vec_len ); + case 421: return makeRegisterExpression(amdgpu_gfx90a::v165, output_vec_len ); + case 422: return makeRegisterExpression(amdgpu_gfx90a::v166, output_vec_len ); + case 423: return makeRegisterExpression(amdgpu_gfx90a::v167, output_vec_len ); + case 424: return makeRegisterExpression(amdgpu_gfx90a::v168, output_vec_len ); + case 425: return makeRegisterExpression(amdgpu_gfx90a::v169, output_vec_len ); + case 426: return makeRegisterExpression(amdgpu_gfx90a::v170, output_vec_len ); + case 427: return makeRegisterExpression(amdgpu_gfx90a::v171, output_vec_len ); + case 428: return makeRegisterExpression(amdgpu_gfx90a::v172, output_vec_len ); + case 429: return makeRegisterExpression(amdgpu_gfx90a::v173, output_vec_len ); + case 430: return makeRegisterExpression(amdgpu_gfx90a::v174, output_vec_len ); + case 431: return makeRegisterExpression(amdgpu_gfx90a::v175, output_vec_len ); + case 432: return makeRegisterExpression(amdgpu_gfx90a::v176, output_vec_len ); + case 433: return makeRegisterExpression(amdgpu_gfx90a::v177, output_vec_len ); + case 434: return makeRegisterExpression(amdgpu_gfx90a::v178, output_vec_len ); + case 435: return makeRegisterExpression(amdgpu_gfx90a::v179, output_vec_len ); + case 436: return makeRegisterExpression(amdgpu_gfx90a::v180, output_vec_len ); + case 437: return makeRegisterExpression(amdgpu_gfx90a::v181, output_vec_len ); + case 438: return makeRegisterExpression(amdgpu_gfx90a::v182, output_vec_len ); + case 439: return makeRegisterExpression(amdgpu_gfx90a::v183, output_vec_len ); + case 440: return makeRegisterExpression(amdgpu_gfx90a::v184, output_vec_len ); + case 441: return makeRegisterExpression(amdgpu_gfx90a::v185, output_vec_len ); + case 442: return makeRegisterExpression(amdgpu_gfx90a::v186, output_vec_len ); + case 443: return makeRegisterExpression(amdgpu_gfx90a::v187, output_vec_len ); + case 444: return makeRegisterExpression(amdgpu_gfx90a::v188, output_vec_len ); + case 445: return makeRegisterExpression(amdgpu_gfx90a::v189, output_vec_len ); + case 446: return makeRegisterExpression(amdgpu_gfx90a::v190, output_vec_len ); + case 447: return makeRegisterExpression(amdgpu_gfx90a::v191, output_vec_len ); + case 448: return makeRegisterExpression(amdgpu_gfx90a::v192, output_vec_len ); + case 449: return makeRegisterExpression(amdgpu_gfx90a::v193, output_vec_len ); + case 450: return makeRegisterExpression(amdgpu_gfx90a::v194, output_vec_len ); + case 451: return makeRegisterExpression(amdgpu_gfx90a::v195, output_vec_len ); + case 452: return makeRegisterExpression(amdgpu_gfx90a::v196, output_vec_len ); + case 453: return makeRegisterExpression(amdgpu_gfx90a::v197, output_vec_len ); + case 454: return makeRegisterExpression(amdgpu_gfx90a::v198, output_vec_len ); + case 455: return makeRegisterExpression(amdgpu_gfx90a::v199, output_vec_len ); + case 456: return makeRegisterExpression(amdgpu_gfx90a::v200, output_vec_len ); + case 457: return makeRegisterExpression(amdgpu_gfx90a::v201, output_vec_len ); + case 458: return makeRegisterExpression(amdgpu_gfx90a::v202, output_vec_len ); + case 459: return makeRegisterExpression(amdgpu_gfx90a::v203, output_vec_len ); + case 460: return makeRegisterExpression(amdgpu_gfx90a::v204, output_vec_len ); + case 461: return makeRegisterExpression(amdgpu_gfx90a::v205, output_vec_len ); + case 462: return makeRegisterExpression(amdgpu_gfx90a::v206, output_vec_len ); + case 463: return makeRegisterExpression(amdgpu_gfx90a::v207, output_vec_len ); + case 464: return makeRegisterExpression(amdgpu_gfx90a::v208, output_vec_len ); + case 465: return makeRegisterExpression(amdgpu_gfx90a::v209, output_vec_len ); + case 466: return makeRegisterExpression(amdgpu_gfx90a::v210, output_vec_len ); + case 467: return makeRegisterExpression(amdgpu_gfx90a::v211, output_vec_len ); + case 468: return makeRegisterExpression(amdgpu_gfx90a::v212, output_vec_len ); + case 469: return makeRegisterExpression(amdgpu_gfx90a::v213, output_vec_len ); + case 470: return makeRegisterExpression(amdgpu_gfx90a::v214, output_vec_len ); + case 471: return makeRegisterExpression(amdgpu_gfx90a::v215, output_vec_len ); + case 472: return makeRegisterExpression(amdgpu_gfx90a::v216, output_vec_len ); + case 473: return makeRegisterExpression(amdgpu_gfx90a::v217, output_vec_len ); + case 474: return makeRegisterExpression(amdgpu_gfx90a::v218, output_vec_len ); + case 475: return makeRegisterExpression(amdgpu_gfx90a::v219, output_vec_len ); + case 476: return makeRegisterExpression(amdgpu_gfx90a::v220, output_vec_len ); + case 477: return makeRegisterExpression(amdgpu_gfx90a::v221, output_vec_len ); + case 478: return makeRegisterExpression(amdgpu_gfx90a::v222, output_vec_len ); + case 479: return makeRegisterExpression(amdgpu_gfx90a::v223, output_vec_len ); + case 480: return makeRegisterExpression(amdgpu_gfx90a::v224, output_vec_len ); + case 481: return makeRegisterExpression(amdgpu_gfx90a::v225, output_vec_len ); + case 482: return makeRegisterExpression(amdgpu_gfx90a::v226, output_vec_len ); + case 483: return makeRegisterExpression(amdgpu_gfx90a::v227, output_vec_len ); + case 484: return makeRegisterExpression(amdgpu_gfx90a::v228, output_vec_len ); + case 485: return makeRegisterExpression(amdgpu_gfx90a::v229, output_vec_len ); + case 486: return makeRegisterExpression(amdgpu_gfx90a::v230, output_vec_len ); + case 487: return makeRegisterExpression(amdgpu_gfx90a::v231, output_vec_len ); + case 488: return makeRegisterExpression(amdgpu_gfx90a::v232, output_vec_len ); + case 489: return makeRegisterExpression(amdgpu_gfx90a::v233, output_vec_len ); + case 490: return makeRegisterExpression(amdgpu_gfx90a::v234, output_vec_len ); + case 491: return makeRegisterExpression(amdgpu_gfx90a::v235, output_vec_len ); + case 492: return makeRegisterExpression(amdgpu_gfx90a::v236, output_vec_len ); + case 493: return makeRegisterExpression(amdgpu_gfx90a::v237, output_vec_len ); + case 494: return makeRegisterExpression(amdgpu_gfx90a::v238, output_vec_len ); + case 495: return makeRegisterExpression(amdgpu_gfx90a::v239, output_vec_len ); + case 496: return makeRegisterExpression(amdgpu_gfx90a::v240, output_vec_len ); + case 497: return makeRegisterExpression(amdgpu_gfx90a::v241, output_vec_len ); + case 498: return makeRegisterExpression(amdgpu_gfx90a::v242, output_vec_len ); + case 499: return makeRegisterExpression(amdgpu_gfx90a::v243, output_vec_len ); + case 500: return makeRegisterExpression(amdgpu_gfx90a::v244, output_vec_len ); + case 501: return makeRegisterExpression(amdgpu_gfx90a::v245, output_vec_len ); + case 502: return makeRegisterExpression(amdgpu_gfx90a::v246, output_vec_len ); + case 503: return makeRegisterExpression(amdgpu_gfx90a::v247, output_vec_len ); + case 504: return makeRegisterExpression(amdgpu_gfx90a::v248, output_vec_len ); + case 505: return makeRegisterExpression(amdgpu_gfx90a::v249, output_vec_len ); + case 506: return makeRegisterExpression(amdgpu_gfx90a::v250, output_vec_len ); + case 507: return makeRegisterExpression(amdgpu_gfx90a::v251, output_vec_len ); + case 508: return makeRegisterExpression(amdgpu_gfx90a::v252, output_vec_len ); + case 509: return makeRegisterExpression(amdgpu_gfx90a::v253, output_vec_len ); + case 510: return makeRegisterExpression(amdgpu_gfx90a::v254, output_vec_len ); + case 511: return makeRegisterExpression(amdgpu_gfx90a::v255, output_vec_len ); + default: return makeRegisterExpression(amdgpu_gfx90a::invalid); + } + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx90a::decodeOPR_SRC_SIMPLE(uint64_t input, uint32_t output_vec_len) + { + switch (input) { + case 0: return makeRegisterExpression(amdgpu_gfx90a::s0, output_vec_len ); + case 1: return makeRegisterExpression(amdgpu_gfx90a::s1, output_vec_len ); + case 2: return makeRegisterExpression(amdgpu_gfx90a::s2, output_vec_len ); + case 3: return makeRegisterExpression(amdgpu_gfx90a::s3, output_vec_len ); + case 4: return makeRegisterExpression(amdgpu_gfx90a::s4, output_vec_len ); + case 5: return makeRegisterExpression(amdgpu_gfx90a::s5, output_vec_len ); + case 6: return makeRegisterExpression(amdgpu_gfx90a::s6, output_vec_len ); + case 7: return makeRegisterExpression(amdgpu_gfx90a::s7, output_vec_len ); + case 8: return makeRegisterExpression(amdgpu_gfx90a::s8, output_vec_len ); + case 9: return makeRegisterExpression(amdgpu_gfx90a::s9, output_vec_len ); + case 10: return makeRegisterExpression(amdgpu_gfx90a::s10, output_vec_len ); + case 11: return makeRegisterExpression(amdgpu_gfx90a::s11, output_vec_len ); + case 12: return makeRegisterExpression(amdgpu_gfx90a::s12, output_vec_len ); + case 13: return makeRegisterExpression(amdgpu_gfx90a::s13, output_vec_len ); + case 14: return makeRegisterExpression(amdgpu_gfx90a::s14, output_vec_len ); + case 15: return makeRegisterExpression(amdgpu_gfx90a::s15, output_vec_len ); + case 16: return makeRegisterExpression(amdgpu_gfx90a::s16, output_vec_len ); + case 17: return makeRegisterExpression(amdgpu_gfx90a::s17, output_vec_len ); + case 18: return makeRegisterExpression(amdgpu_gfx90a::s18, output_vec_len ); + case 19: return makeRegisterExpression(amdgpu_gfx90a::s19, output_vec_len ); + case 20: return makeRegisterExpression(amdgpu_gfx90a::s20, output_vec_len ); + case 21: return makeRegisterExpression(amdgpu_gfx90a::s21, output_vec_len ); + case 22: return makeRegisterExpression(amdgpu_gfx90a::s22, output_vec_len ); + case 23: return makeRegisterExpression(amdgpu_gfx90a::s23, output_vec_len ); + case 24: return makeRegisterExpression(amdgpu_gfx90a::s24, output_vec_len ); + case 25: return makeRegisterExpression(amdgpu_gfx90a::s25, output_vec_len ); + case 26: return makeRegisterExpression(amdgpu_gfx90a::s26, output_vec_len ); + case 27: return makeRegisterExpression(amdgpu_gfx90a::s27, output_vec_len ); + case 28: return makeRegisterExpression(amdgpu_gfx90a::s28, output_vec_len ); + case 29: return makeRegisterExpression(amdgpu_gfx90a::s29, output_vec_len ); + case 30: return makeRegisterExpression(amdgpu_gfx90a::s30, output_vec_len ); + case 31: return makeRegisterExpression(amdgpu_gfx90a::s31, output_vec_len ); + case 32: return makeRegisterExpression(amdgpu_gfx90a::s32, output_vec_len ); + case 33: return makeRegisterExpression(amdgpu_gfx90a::s33, output_vec_len ); + case 34: return makeRegisterExpression(amdgpu_gfx90a::s34, output_vec_len ); + case 35: return makeRegisterExpression(amdgpu_gfx90a::s35, output_vec_len ); + case 36: return makeRegisterExpression(amdgpu_gfx90a::s36, output_vec_len ); + case 37: return makeRegisterExpression(amdgpu_gfx90a::s37, output_vec_len ); + case 38: return makeRegisterExpression(amdgpu_gfx90a::s38, output_vec_len ); + case 39: return makeRegisterExpression(amdgpu_gfx90a::s39, output_vec_len ); + case 40: return makeRegisterExpression(amdgpu_gfx90a::s40, output_vec_len ); + case 41: return makeRegisterExpression(amdgpu_gfx90a::s41, output_vec_len ); + case 42: return makeRegisterExpression(amdgpu_gfx90a::s42, output_vec_len ); + case 43: return makeRegisterExpression(amdgpu_gfx90a::s43, output_vec_len ); + case 44: return makeRegisterExpression(amdgpu_gfx90a::s44, output_vec_len ); + case 45: return makeRegisterExpression(amdgpu_gfx90a::s45, output_vec_len ); + case 46: return makeRegisterExpression(amdgpu_gfx90a::s46, output_vec_len ); + case 47: return makeRegisterExpression(amdgpu_gfx90a::s47, output_vec_len ); + case 48: return makeRegisterExpression(amdgpu_gfx90a::s48, output_vec_len ); + case 49: return makeRegisterExpression(amdgpu_gfx90a::s49, output_vec_len ); + case 50: return makeRegisterExpression(amdgpu_gfx90a::s50, output_vec_len ); + case 51: return makeRegisterExpression(amdgpu_gfx90a::s51, output_vec_len ); + case 52: return makeRegisterExpression(amdgpu_gfx90a::s52, output_vec_len ); + case 53: return makeRegisterExpression(amdgpu_gfx90a::s53, output_vec_len ); + case 54: return makeRegisterExpression(amdgpu_gfx90a::s54, output_vec_len ); + case 55: return makeRegisterExpression(amdgpu_gfx90a::s55, output_vec_len ); + case 56: return makeRegisterExpression(amdgpu_gfx90a::s56, output_vec_len ); + case 57: return makeRegisterExpression(amdgpu_gfx90a::s57, output_vec_len ); + case 58: return makeRegisterExpression(amdgpu_gfx90a::s58, output_vec_len ); + case 59: return makeRegisterExpression(amdgpu_gfx90a::s59, output_vec_len ); + case 60: return makeRegisterExpression(amdgpu_gfx90a::s60, output_vec_len ); + case 61: return makeRegisterExpression(amdgpu_gfx90a::s61, output_vec_len ); + case 62: return makeRegisterExpression(amdgpu_gfx90a::s62, output_vec_len ); + case 63: return makeRegisterExpression(amdgpu_gfx90a::s63, output_vec_len ); + case 64: return makeRegisterExpression(amdgpu_gfx90a::s64, output_vec_len ); + case 65: return makeRegisterExpression(amdgpu_gfx90a::s65, output_vec_len ); + case 66: return makeRegisterExpression(amdgpu_gfx90a::s66, output_vec_len ); + case 67: return makeRegisterExpression(amdgpu_gfx90a::s67, output_vec_len ); + case 68: return makeRegisterExpression(amdgpu_gfx90a::s68, output_vec_len ); + case 69: return makeRegisterExpression(amdgpu_gfx90a::s69, output_vec_len ); + case 70: return makeRegisterExpression(amdgpu_gfx90a::s70, output_vec_len ); + case 71: return makeRegisterExpression(amdgpu_gfx90a::s71, output_vec_len ); + case 72: return makeRegisterExpression(amdgpu_gfx90a::s72, output_vec_len ); + case 73: return makeRegisterExpression(amdgpu_gfx90a::s73, output_vec_len ); + case 74: return makeRegisterExpression(amdgpu_gfx90a::s74, output_vec_len ); + case 75: return makeRegisterExpression(amdgpu_gfx90a::s75, output_vec_len ); + case 76: return makeRegisterExpression(amdgpu_gfx90a::s76, output_vec_len ); + case 77: return makeRegisterExpression(amdgpu_gfx90a::s77, output_vec_len ); + case 78: return makeRegisterExpression(amdgpu_gfx90a::s78, output_vec_len ); + case 79: return makeRegisterExpression(amdgpu_gfx90a::s79, output_vec_len ); + case 80: return makeRegisterExpression(amdgpu_gfx90a::s80, output_vec_len ); + case 81: return makeRegisterExpression(amdgpu_gfx90a::s81, output_vec_len ); + case 82: return makeRegisterExpression(amdgpu_gfx90a::s82, output_vec_len ); + case 83: return makeRegisterExpression(amdgpu_gfx90a::s83, output_vec_len ); + case 84: return makeRegisterExpression(amdgpu_gfx90a::s84, output_vec_len ); + case 85: return makeRegisterExpression(amdgpu_gfx90a::s85, output_vec_len ); + case 86: return makeRegisterExpression(amdgpu_gfx90a::s86, output_vec_len ); + case 87: return makeRegisterExpression(amdgpu_gfx90a::s87, output_vec_len ); + case 88: return makeRegisterExpression(amdgpu_gfx90a::s88, output_vec_len ); + case 89: return makeRegisterExpression(amdgpu_gfx90a::s89, output_vec_len ); + case 90: return makeRegisterExpression(amdgpu_gfx90a::s90, output_vec_len ); + case 91: return makeRegisterExpression(amdgpu_gfx90a::s91, output_vec_len ); + case 92: return makeRegisterExpression(amdgpu_gfx90a::s92, output_vec_len ); + case 93: return makeRegisterExpression(amdgpu_gfx90a::s93, output_vec_len ); + case 94: return makeRegisterExpression(amdgpu_gfx90a::s94, output_vec_len ); + case 95: return makeRegisterExpression(amdgpu_gfx90a::s95, output_vec_len ); + case 96: return makeRegisterExpression(amdgpu_gfx90a::s96, output_vec_len ); + case 97: return makeRegisterExpression(amdgpu_gfx90a::s97, output_vec_len ); + case 98: return makeRegisterExpression(amdgpu_gfx90a::s98, output_vec_len ); + case 99: return makeRegisterExpression(amdgpu_gfx90a::s99, output_vec_len ); + case 100: return makeRegisterExpression(amdgpu_gfx90a::s100, output_vec_len ); + case 101: return makeRegisterExpression(amdgpu_gfx90a::s101, output_vec_len ); + case 104: return makeRegisterExpression(amdgpu_gfx90a::xnack_mask_lo, output_vec_len ); + case 105: return makeRegisterExpression(amdgpu_gfx90a::xnack_mask_hi, output_vec_len ); + case 102: return makeRegisterExpression(amdgpu_gfx90a::flat_scratch_lo, output_vec_len ); + case 103: return makeRegisterExpression(amdgpu_gfx90a::flat_scratch_hi, output_vec_len ); + case 108: return makeRegisterExpression(amdgpu_gfx90a::ttmp0, output_vec_len ); + case 109: return makeRegisterExpression(amdgpu_gfx90a::ttmp1, output_vec_len ); + case 110: return makeRegisterExpression(amdgpu_gfx90a::ttmp2, output_vec_len ); + case 111: return makeRegisterExpression(amdgpu_gfx90a::ttmp3, output_vec_len ); + case 112: return makeRegisterExpression(amdgpu_gfx90a::ttmp4, output_vec_len ); + case 113: return makeRegisterExpression(amdgpu_gfx90a::ttmp5, output_vec_len ); + case 114: return makeRegisterExpression(amdgpu_gfx90a::ttmp6, output_vec_len ); + case 115: return makeRegisterExpression(amdgpu_gfx90a::ttmp7, output_vec_len ); + case 116: return makeRegisterExpression(amdgpu_gfx90a::ttmp8, output_vec_len ); + case 117: return makeRegisterExpression(amdgpu_gfx90a::ttmp9, output_vec_len ); + case 118: return makeRegisterExpression(amdgpu_gfx90a::ttmp10, output_vec_len ); + case 119: return makeRegisterExpression(amdgpu_gfx90a::ttmp11, output_vec_len ); + case 120: return makeRegisterExpression(amdgpu_gfx90a::ttmp12, output_vec_len ); + case 121: return makeRegisterExpression(amdgpu_gfx90a::ttmp13, output_vec_len ); + case 122: return makeRegisterExpression(amdgpu_gfx90a::ttmp14, output_vec_len ); + case 123: return makeRegisterExpression(amdgpu_gfx90a::ttmp15, output_vec_len ); + case 106: return makeRegisterExpression(amdgpu_gfx90a::vcc_lo, output_vec_len ); + case 107: return makeRegisterExpression(amdgpu_gfx90a::vcc_hi, output_vec_len ); + case 124: return makeRegisterExpression(amdgpu_gfx90a::m0, output_vec_len ); + case 126: return makeRegisterExpression(amdgpu_gfx90a::exec_lo, output_vec_len ); + case 127: return makeRegisterExpression(amdgpu_gfx90a::exec_hi, output_vec_len ); + case 128: return Immediate::makeImmediate(Result(u32, 0)); + case 129: return Immediate::makeImmediate(Result(u32, 1)); + case 130: return Immediate::makeImmediate(Result(u32, 2)); + case 131: return Immediate::makeImmediate(Result(u32, 3)); + case 132: return Immediate::makeImmediate(Result(u32, 4)); + case 133: return Immediate::makeImmediate(Result(u32, 5)); + case 134: return Immediate::makeImmediate(Result(u32, 6)); + case 135: return Immediate::makeImmediate(Result(u32, 7)); + case 136: return Immediate::makeImmediate(Result(u32, 8)); + case 137: return Immediate::makeImmediate(Result(u32, 9)); + case 138: return Immediate::makeImmediate(Result(u32, 10)); + case 139: return Immediate::makeImmediate(Result(u32, 11)); + case 140: return Immediate::makeImmediate(Result(u32, 12)); + case 141: return Immediate::makeImmediate(Result(u32, 13)); + case 142: return Immediate::makeImmediate(Result(u32, 14)); + case 143: return Immediate::makeImmediate(Result(u32, 15)); + case 144: return Immediate::makeImmediate(Result(u32, 16)); + case 145: return Immediate::makeImmediate(Result(u32, 17)); + case 146: return Immediate::makeImmediate(Result(u32, 18)); + case 147: return Immediate::makeImmediate(Result(u32, 19)); + case 148: return Immediate::makeImmediate(Result(u32, 20)); + case 149: return Immediate::makeImmediate(Result(u32, 21)); + case 150: return Immediate::makeImmediate(Result(u32, 22)); + case 151: return Immediate::makeImmediate(Result(u32, 23)); + case 152: return Immediate::makeImmediate(Result(u32, 24)); + case 153: return Immediate::makeImmediate(Result(u32, 25)); + case 154: return Immediate::makeImmediate(Result(u32, 26)); + case 155: return Immediate::makeImmediate(Result(u32, 27)); + case 156: return Immediate::makeImmediate(Result(u32, 28)); + case 157: return Immediate::makeImmediate(Result(u32, 29)); + case 158: return Immediate::makeImmediate(Result(u32, 30)); + case 159: return Immediate::makeImmediate(Result(u32, 31)); + case 160: return Immediate::makeImmediate(Result(u32, 32)); + case 161: return Immediate::makeImmediate(Result(u32, 33)); + case 162: return Immediate::makeImmediate(Result(u32, 34)); + case 163: return Immediate::makeImmediate(Result(u32, 35)); + case 164: return Immediate::makeImmediate(Result(u32, 36)); + case 165: return Immediate::makeImmediate(Result(u32, 37)); + case 166: return Immediate::makeImmediate(Result(u32, 38)); + case 167: return Immediate::makeImmediate(Result(u32, 39)); + case 168: return Immediate::makeImmediate(Result(u32, 40)); + case 169: return Immediate::makeImmediate(Result(u32, 41)); + case 170: return Immediate::makeImmediate(Result(u32, 42)); + case 171: return Immediate::makeImmediate(Result(u32, 43)); + case 172: return Immediate::makeImmediate(Result(u32, 44)); + case 173: return Immediate::makeImmediate(Result(u32, 45)); + case 174: return Immediate::makeImmediate(Result(u32, 46)); + case 175: return Immediate::makeImmediate(Result(u32, 47)); + case 176: return Immediate::makeImmediate(Result(u32, 48)); + case 177: return Immediate::makeImmediate(Result(u32, 49)); + case 178: return Immediate::makeImmediate(Result(u32, 50)); + case 179: return Immediate::makeImmediate(Result(u32, 51)); + case 180: return Immediate::makeImmediate(Result(u32, 52)); + case 181: return Immediate::makeImmediate(Result(u32, 53)); + case 182: return Immediate::makeImmediate(Result(u32, 54)); + case 183: return Immediate::makeImmediate(Result(u32, 55)); + case 184: return Immediate::makeImmediate(Result(u32, 56)); + case 185: return Immediate::makeImmediate(Result(u32, 57)); + case 186: return Immediate::makeImmediate(Result(u32, 58)); + case 187: return Immediate::makeImmediate(Result(u32, 59)); + case 188: return Immediate::makeImmediate(Result(u32, 60)); + case 189: return Immediate::makeImmediate(Result(u32, 61)); + case 190: return Immediate::makeImmediate(Result(u32, 62)); + case 191: return Immediate::makeImmediate(Result(u32, 63)); + case 192: return Immediate::makeImmediate(Result(u32, 64)); + case 193: return Immediate::makeImmediate(Result(u32, -1)); + case 194: return Immediate::makeImmediate(Result(u32, -2)); + case 195: return Immediate::makeImmediate(Result(u32, -3)); + case 196: return Immediate::makeImmediate(Result(u32, -4)); + case 197: return Immediate::makeImmediate(Result(u32, -5)); + case 198: return Immediate::makeImmediate(Result(u32, -6)); + case 199: return Immediate::makeImmediate(Result(u32, -7)); + case 200: return Immediate::makeImmediate(Result(u32, -8)); + case 201: return Immediate::makeImmediate(Result(u32, -9)); + case 202: return Immediate::makeImmediate(Result(u32, -10)); + case 203: return Immediate::makeImmediate(Result(u32, -11)); + case 204: return Immediate::makeImmediate(Result(u32, -12)); + case 205: return Immediate::makeImmediate(Result(u32, -13)); + case 206: return Immediate::makeImmediate(Result(u32, -14)); + case 207: return Immediate::makeImmediate(Result(u32, -15)); + case 208: return Immediate::makeImmediate(Result(u32, -16)); + case 240: return Immediate::makeImmediate(Result(sp_float, 0.5)); + case 241: return Immediate::makeImmediate(Result(sp_float, -0.5)); + case 242: return Immediate::makeImmediate(Result(sp_float, 1.0)); + case 243: return Immediate::makeImmediate(Result(sp_float, -1.0)); + case 244: return Immediate::makeImmediate(Result(sp_float, 2.0)); + case 245: return Immediate::makeImmediate(Result(sp_float, -2.0)); + case 246: return Immediate::makeImmediate(Result(sp_float, 4.0)); + case 247: return Immediate::makeImmediate(Result(sp_float, -4.0)); + case 248: return Immediate::makeImmediate(Result(sp_float, 0.15915494)); + case 251: return makeRegisterExpression(amdgpu_gfx90a::src_vccz, output_vec_len ); + case 252: return makeRegisterExpression(amdgpu_gfx90a::src_execz, output_vec_len ); + case 253: return makeRegisterExpression(amdgpu_gfx90a::src_scc, output_vec_len ); + case 235: return makeRegisterExpression(amdgpu_gfx90a::src_shared_base, output_vec_len ); + case 236: return makeRegisterExpression(amdgpu_gfx90a::src_shared_limit, output_vec_len ); + case 237: return makeRegisterExpression(amdgpu_gfx90a::src_private_base, output_vec_len ); + case 238: return makeRegisterExpression(amdgpu_gfx90a::src_private_limit, output_vec_len ); + case 239: return makeRegisterExpression(amdgpu_gfx90a::src_pops_exiting_wave_id, output_vec_len ); + case 256: return makeRegisterExpression(amdgpu_gfx90a::v0, output_vec_len ); + case 257: return makeRegisterExpression(amdgpu_gfx90a::v1, output_vec_len ); + case 258: return makeRegisterExpression(amdgpu_gfx90a::v2, output_vec_len ); + case 259: return makeRegisterExpression(amdgpu_gfx90a::v3, output_vec_len ); + case 260: return makeRegisterExpression(amdgpu_gfx90a::v4, output_vec_len ); + case 261: return makeRegisterExpression(amdgpu_gfx90a::v5, output_vec_len ); + case 262: return makeRegisterExpression(amdgpu_gfx90a::v6, output_vec_len ); + case 263: return makeRegisterExpression(amdgpu_gfx90a::v7, output_vec_len ); + case 264: return makeRegisterExpression(amdgpu_gfx90a::v8, output_vec_len ); + case 265: return makeRegisterExpression(amdgpu_gfx90a::v9, output_vec_len ); + case 266: return makeRegisterExpression(amdgpu_gfx90a::v10, output_vec_len ); + case 267: return makeRegisterExpression(amdgpu_gfx90a::v11, output_vec_len ); + case 268: return makeRegisterExpression(amdgpu_gfx90a::v12, output_vec_len ); + case 269: return makeRegisterExpression(amdgpu_gfx90a::v13, output_vec_len ); + case 270: return makeRegisterExpression(amdgpu_gfx90a::v14, output_vec_len ); + case 271: return makeRegisterExpression(amdgpu_gfx90a::v15, output_vec_len ); + case 272: return makeRegisterExpression(amdgpu_gfx90a::v16, output_vec_len ); + case 273: return makeRegisterExpression(amdgpu_gfx90a::v17, output_vec_len ); + case 274: return makeRegisterExpression(amdgpu_gfx90a::v18, output_vec_len ); + case 275: return makeRegisterExpression(amdgpu_gfx90a::v19, output_vec_len ); + case 276: return makeRegisterExpression(amdgpu_gfx90a::v20, output_vec_len ); + case 277: return makeRegisterExpression(amdgpu_gfx90a::v21, output_vec_len ); + case 278: return makeRegisterExpression(amdgpu_gfx90a::v22, output_vec_len ); + case 279: return makeRegisterExpression(amdgpu_gfx90a::v23, output_vec_len ); + case 280: return makeRegisterExpression(amdgpu_gfx90a::v24, output_vec_len ); + case 281: return makeRegisterExpression(amdgpu_gfx90a::v25, output_vec_len ); + case 282: return makeRegisterExpression(amdgpu_gfx90a::v26, output_vec_len ); + case 283: return makeRegisterExpression(amdgpu_gfx90a::v27, output_vec_len ); + case 284: return makeRegisterExpression(amdgpu_gfx90a::v28, output_vec_len ); + case 285: return makeRegisterExpression(amdgpu_gfx90a::v29, output_vec_len ); + case 286: return makeRegisterExpression(amdgpu_gfx90a::v30, output_vec_len ); + case 287: return makeRegisterExpression(amdgpu_gfx90a::v31, output_vec_len ); + case 288: return makeRegisterExpression(amdgpu_gfx90a::v32, output_vec_len ); + case 289: return makeRegisterExpression(amdgpu_gfx90a::v33, output_vec_len ); + case 290: return makeRegisterExpression(amdgpu_gfx90a::v34, output_vec_len ); + case 291: return makeRegisterExpression(amdgpu_gfx90a::v35, output_vec_len ); + case 292: return makeRegisterExpression(amdgpu_gfx90a::v36, output_vec_len ); + case 293: return makeRegisterExpression(amdgpu_gfx90a::v37, output_vec_len ); + case 294: return makeRegisterExpression(amdgpu_gfx90a::v38, output_vec_len ); + case 295: return makeRegisterExpression(amdgpu_gfx90a::v39, output_vec_len ); + case 296: return makeRegisterExpression(amdgpu_gfx90a::v40, output_vec_len ); + case 297: return makeRegisterExpression(amdgpu_gfx90a::v41, output_vec_len ); + case 298: return makeRegisterExpression(amdgpu_gfx90a::v42, output_vec_len ); + case 299: return makeRegisterExpression(amdgpu_gfx90a::v43, output_vec_len ); + case 300: return makeRegisterExpression(amdgpu_gfx90a::v44, output_vec_len ); + case 301: return makeRegisterExpression(amdgpu_gfx90a::v45, output_vec_len ); + case 302: return makeRegisterExpression(amdgpu_gfx90a::v46, output_vec_len ); + case 303: return makeRegisterExpression(amdgpu_gfx90a::v47, output_vec_len ); + case 304: return makeRegisterExpression(amdgpu_gfx90a::v48, output_vec_len ); + case 305: return makeRegisterExpression(amdgpu_gfx90a::v49, output_vec_len ); + case 306: return makeRegisterExpression(amdgpu_gfx90a::v50, output_vec_len ); + case 307: return makeRegisterExpression(amdgpu_gfx90a::v51, output_vec_len ); + case 308: return makeRegisterExpression(amdgpu_gfx90a::v52, output_vec_len ); + case 309: return makeRegisterExpression(amdgpu_gfx90a::v53, output_vec_len ); + case 310: return makeRegisterExpression(amdgpu_gfx90a::v54, output_vec_len ); + case 311: return makeRegisterExpression(amdgpu_gfx90a::v55, output_vec_len ); + case 312: return makeRegisterExpression(amdgpu_gfx90a::v56, output_vec_len ); + case 313: return makeRegisterExpression(amdgpu_gfx90a::v57, output_vec_len ); + case 314: return makeRegisterExpression(amdgpu_gfx90a::v58, output_vec_len ); + case 315: return makeRegisterExpression(amdgpu_gfx90a::v59, output_vec_len ); + case 316: return makeRegisterExpression(amdgpu_gfx90a::v60, output_vec_len ); + case 317: return makeRegisterExpression(amdgpu_gfx90a::v61, output_vec_len ); + case 318: return makeRegisterExpression(amdgpu_gfx90a::v62, output_vec_len ); + case 319: return makeRegisterExpression(amdgpu_gfx90a::v63, output_vec_len ); + case 320: return makeRegisterExpression(amdgpu_gfx90a::v64, output_vec_len ); + case 321: return makeRegisterExpression(amdgpu_gfx90a::v65, output_vec_len ); + case 322: return makeRegisterExpression(amdgpu_gfx90a::v66, output_vec_len ); + case 323: return makeRegisterExpression(amdgpu_gfx90a::v67, output_vec_len ); + case 324: return makeRegisterExpression(amdgpu_gfx90a::v68, output_vec_len ); + case 325: return makeRegisterExpression(amdgpu_gfx90a::v69, output_vec_len ); + case 326: return makeRegisterExpression(amdgpu_gfx90a::v70, output_vec_len ); + case 327: return makeRegisterExpression(amdgpu_gfx90a::v71, output_vec_len ); + case 328: return makeRegisterExpression(amdgpu_gfx90a::v72, output_vec_len ); + case 329: return makeRegisterExpression(amdgpu_gfx90a::v73, output_vec_len ); + case 330: return makeRegisterExpression(amdgpu_gfx90a::v74, output_vec_len ); + case 331: return makeRegisterExpression(amdgpu_gfx90a::v75, output_vec_len ); + case 332: return makeRegisterExpression(amdgpu_gfx90a::v76, output_vec_len ); + case 333: return makeRegisterExpression(amdgpu_gfx90a::v77, output_vec_len ); + case 334: return makeRegisterExpression(amdgpu_gfx90a::v78, output_vec_len ); + case 335: return makeRegisterExpression(amdgpu_gfx90a::v79, output_vec_len ); + case 336: return makeRegisterExpression(amdgpu_gfx90a::v80, output_vec_len ); + case 337: return makeRegisterExpression(amdgpu_gfx90a::v81, output_vec_len ); + case 338: return makeRegisterExpression(amdgpu_gfx90a::v82, output_vec_len ); + case 339: return makeRegisterExpression(amdgpu_gfx90a::v83, output_vec_len ); + case 340: return makeRegisterExpression(amdgpu_gfx90a::v84, output_vec_len ); + case 341: return makeRegisterExpression(amdgpu_gfx90a::v85, output_vec_len ); + case 342: return makeRegisterExpression(amdgpu_gfx90a::v86, output_vec_len ); + case 343: return makeRegisterExpression(amdgpu_gfx90a::v87, output_vec_len ); + case 344: return makeRegisterExpression(amdgpu_gfx90a::v88, output_vec_len ); + case 345: return makeRegisterExpression(amdgpu_gfx90a::v89, output_vec_len ); + case 346: return makeRegisterExpression(amdgpu_gfx90a::v90, output_vec_len ); + case 347: return makeRegisterExpression(amdgpu_gfx90a::v91, output_vec_len ); + case 348: return makeRegisterExpression(amdgpu_gfx90a::v92, output_vec_len ); + case 349: return makeRegisterExpression(amdgpu_gfx90a::v93, output_vec_len ); + case 350: return makeRegisterExpression(amdgpu_gfx90a::v94, output_vec_len ); + case 351: return makeRegisterExpression(amdgpu_gfx90a::v95, output_vec_len ); + case 352: return makeRegisterExpression(amdgpu_gfx90a::v96, output_vec_len ); + case 353: return makeRegisterExpression(amdgpu_gfx90a::v97, output_vec_len ); + case 354: return makeRegisterExpression(amdgpu_gfx90a::v98, output_vec_len ); + case 355: return makeRegisterExpression(amdgpu_gfx90a::v99, output_vec_len ); + case 356: return makeRegisterExpression(amdgpu_gfx90a::v100, output_vec_len ); + case 357: return makeRegisterExpression(amdgpu_gfx90a::v101, output_vec_len ); + case 358: return makeRegisterExpression(amdgpu_gfx90a::v102, output_vec_len ); + case 359: return makeRegisterExpression(amdgpu_gfx90a::v103, output_vec_len ); + case 360: return makeRegisterExpression(amdgpu_gfx90a::v104, output_vec_len ); + case 361: return makeRegisterExpression(amdgpu_gfx90a::v105, output_vec_len ); + case 362: return makeRegisterExpression(amdgpu_gfx90a::v106, output_vec_len ); + case 363: return makeRegisterExpression(amdgpu_gfx90a::v107, output_vec_len ); + case 364: return makeRegisterExpression(amdgpu_gfx90a::v108, output_vec_len ); + case 365: return makeRegisterExpression(amdgpu_gfx90a::v109, output_vec_len ); + case 366: return makeRegisterExpression(amdgpu_gfx90a::v110, output_vec_len ); + case 367: return makeRegisterExpression(amdgpu_gfx90a::v111, output_vec_len ); + case 368: return makeRegisterExpression(amdgpu_gfx90a::v112, output_vec_len ); + case 369: return makeRegisterExpression(amdgpu_gfx90a::v113, output_vec_len ); + case 370: return makeRegisterExpression(amdgpu_gfx90a::v114, output_vec_len ); + case 371: return makeRegisterExpression(amdgpu_gfx90a::v115, output_vec_len ); + case 372: return makeRegisterExpression(amdgpu_gfx90a::v116, output_vec_len ); + case 373: return makeRegisterExpression(amdgpu_gfx90a::v117, output_vec_len ); + case 374: return makeRegisterExpression(amdgpu_gfx90a::v118, output_vec_len ); + case 375: return makeRegisterExpression(amdgpu_gfx90a::v119, output_vec_len ); + case 376: return makeRegisterExpression(amdgpu_gfx90a::v120, output_vec_len ); + case 377: return makeRegisterExpression(amdgpu_gfx90a::v121, output_vec_len ); + case 378: return makeRegisterExpression(amdgpu_gfx90a::v122, output_vec_len ); + case 379: return makeRegisterExpression(amdgpu_gfx90a::v123, output_vec_len ); + case 380: return makeRegisterExpression(amdgpu_gfx90a::v124, output_vec_len ); + case 381: return makeRegisterExpression(amdgpu_gfx90a::v125, output_vec_len ); + case 382: return makeRegisterExpression(amdgpu_gfx90a::v126, output_vec_len ); + case 383: return makeRegisterExpression(amdgpu_gfx90a::v127, output_vec_len ); + case 384: return makeRegisterExpression(amdgpu_gfx90a::v128, output_vec_len ); + case 385: return makeRegisterExpression(amdgpu_gfx90a::v129, output_vec_len ); + case 386: return makeRegisterExpression(amdgpu_gfx90a::v130, output_vec_len ); + case 387: return makeRegisterExpression(amdgpu_gfx90a::v131, output_vec_len ); + case 388: return makeRegisterExpression(amdgpu_gfx90a::v132, output_vec_len ); + case 389: return makeRegisterExpression(amdgpu_gfx90a::v133, output_vec_len ); + case 390: return makeRegisterExpression(amdgpu_gfx90a::v134, output_vec_len ); + case 391: return makeRegisterExpression(amdgpu_gfx90a::v135, output_vec_len ); + case 392: return makeRegisterExpression(amdgpu_gfx90a::v136, output_vec_len ); + case 393: return makeRegisterExpression(amdgpu_gfx90a::v137, output_vec_len ); + case 394: return makeRegisterExpression(amdgpu_gfx90a::v138, output_vec_len ); + case 395: return makeRegisterExpression(amdgpu_gfx90a::v139, output_vec_len ); + case 396: return makeRegisterExpression(amdgpu_gfx90a::v140, output_vec_len ); + case 397: return makeRegisterExpression(amdgpu_gfx90a::v141, output_vec_len ); + case 398: return makeRegisterExpression(amdgpu_gfx90a::v142, output_vec_len ); + case 399: return makeRegisterExpression(amdgpu_gfx90a::v143, output_vec_len ); + case 400: return makeRegisterExpression(amdgpu_gfx90a::v144, output_vec_len ); + case 401: return makeRegisterExpression(amdgpu_gfx90a::v145, output_vec_len ); + case 402: return makeRegisterExpression(amdgpu_gfx90a::v146, output_vec_len ); + case 403: return makeRegisterExpression(amdgpu_gfx90a::v147, output_vec_len ); + case 404: return makeRegisterExpression(amdgpu_gfx90a::v148, output_vec_len ); + case 405: return makeRegisterExpression(amdgpu_gfx90a::v149, output_vec_len ); + case 406: return makeRegisterExpression(amdgpu_gfx90a::v150, output_vec_len ); + case 407: return makeRegisterExpression(amdgpu_gfx90a::v151, output_vec_len ); + case 408: return makeRegisterExpression(amdgpu_gfx90a::v152, output_vec_len ); + case 409: return makeRegisterExpression(amdgpu_gfx90a::v153, output_vec_len ); + case 410: return makeRegisterExpression(amdgpu_gfx90a::v154, output_vec_len ); + case 411: return makeRegisterExpression(amdgpu_gfx90a::v155, output_vec_len ); + case 412: return makeRegisterExpression(amdgpu_gfx90a::v156, output_vec_len ); + case 413: return makeRegisterExpression(amdgpu_gfx90a::v157, output_vec_len ); + case 414: return makeRegisterExpression(amdgpu_gfx90a::v158, output_vec_len ); + case 415: return makeRegisterExpression(amdgpu_gfx90a::v159, output_vec_len ); + case 416: return makeRegisterExpression(amdgpu_gfx90a::v160, output_vec_len ); + case 417: return makeRegisterExpression(amdgpu_gfx90a::v161, output_vec_len ); + case 418: return makeRegisterExpression(amdgpu_gfx90a::v162, output_vec_len ); + case 419: return makeRegisterExpression(amdgpu_gfx90a::v163, output_vec_len ); + case 420: return makeRegisterExpression(amdgpu_gfx90a::v164, output_vec_len ); + case 421: return makeRegisterExpression(amdgpu_gfx90a::v165, output_vec_len ); + case 422: return makeRegisterExpression(amdgpu_gfx90a::v166, output_vec_len ); + case 423: return makeRegisterExpression(amdgpu_gfx90a::v167, output_vec_len ); + case 424: return makeRegisterExpression(amdgpu_gfx90a::v168, output_vec_len ); + case 425: return makeRegisterExpression(amdgpu_gfx90a::v169, output_vec_len ); + case 426: return makeRegisterExpression(amdgpu_gfx90a::v170, output_vec_len ); + case 427: return makeRegisterExpression(amdgpu_gfx90a::v171, output_vec_len ); + case 428: return makeRegisterExpression(amdgpu_gfx90a::v172, output_vec_len ); + case 429: return makeRegisterExpression(amdgpu_gfx90a::v173, output_vec_len ); + case 430: return makeRegisterExpression(amdgpu_gfx90a::v174, output_vec_len ); + case 431: return makeRegisterExpression(amdgpu_gfx90a::v175, output_vec_len ); + case 432: return makeRegisterExpression(amdgpu_gfx90a::v176, output_vec_len ); + case 433: return makeRegisterExpression(amdgpu_gfx90a::v177, output_vec_len ); + case 434: return makeRegisterExpression(amdgpu_gfx90a::v178, output_vec_len ); + case 435: return makeRegisterExpression(amdgpu_gfx90a::v179, output_vec_len ); + case 436: return makeRegisterExpression(amdgpu_gfx90a::v180, output_vec_len ); + case 437: return makeRegisterExpression(amdgpu_gfx90a::v181, output_vec_len ); + case 438: return makeRegisterExpression(amdgpu_gfx90a::v182, output_vec_len ); + case 439: return makeRegisterExpression(amdgpu_gfx90a::v183, output_vec_len ); + case 440: return makeRegisterExpression(amdgpu_gfx90a::v184, output_vec_len ); + case 441: return makeRegisterExpression(amdgpu_gfx90a::v185, output_vec_len ); + case 442: return makeRegisterExpression(amdgpu_gfx90a::v186, output_vec_len ); + case 443: return makeRegisterExpression(amdgpu_gfx90a::v187, output_vec_len ); + case 444: return makeRegisterExpression(amdgpu_gfx90a::v188, output_vec_len ); + case 445: return makeRegisterExpression(amdgpu_gfx90a::v189, output_vec_len ); + case 446: return makeRegisterExpression(amdgpu_gfx90a::v190, output_vec_len ); + case 447: return makeRegisterExpression(amdgpu_gfx90a::v191, output_vec_len ); + case 448: return makeRegisterExpression(amdgpu_gfx90a::v192, output_vec_len ); + case 449: return makeRegisterExpression(amdgpu_gfx90a::v193, output_vec_len ); + case 450: return makeRegisterExpression(amdgpu_gfx90a::v194, output_vec_len ); + case 451: return makeRegisterExpression(amdgpu_gfx90a::v195, output_vec_len ); + case 452: return makeRegisterExpression(amdgpu_gfx90a::v196, output_vec_len ); + case 453: return makeRegisterExpression(amdgpu_gfx90a::v197, output_vec_len ); + case 454: return makeRegisterExpression(amdgpu_gfx90a::v198, output_vec_len ); + case 455: return makeRegisterExpression(amdgpu_gfx90a::v199, output_vec_len ); + case 456: return makeRegisterExpression(amdgpu_gfx90a::v200, output_vec_len ); + case 457: return makeRegisterExpression(amdgpu_gfx90a::v201, output_vec_len ); + case 458: return makeRegisterExpression(amdgpu_gfx90a::v202, output_vec_len ); + case 459: return makeRegisterExpression(amdgpu_gfx90a::v203, output_vec_len ); + case 460: return makeRegisterExpression(amdgpu_gfx90a::v204, output_vec_len ); + case 461: return makeRegisterExpression(amdgpu_gfx90a::v205, output_vec_len ); + case 462: return makeRegisterExpression(amdgpu_gfx90a::v206, output_vec_len ); + case 463: return makeRegisterExpression(amdgpu_gfx90a::v207, output_vec_len ); + case 464: return makeRegisterExpression(amdgpu_gfx90a::v208, output_vec_len ); + case 465: return makeRegisterExpression(amdgpu_gfx90a::v209, output_vec_len ); + case 466: return makeRegisterExpression(amdgpu_gfx90a::v210, output_vec_len ); + case 467: return makeRegisterExpression(amdgpu_gfx90a::v211, output_vec_len ); + case 468: return makeRegisterExpression(amdgpu_gfx90a::v212, output_vec_len ); + case 469: return makeRegisterExpression(amdgpu_gfx90a::v213, output_vec_len ); + case 470: return makeRegisterExpression(amdgpu_gfx90a::v214, output_vec_len ); + case 471: return makeRegisterExpression(amdgpu_gfx90a::v215, output_vec_len ); + case 472: return makeRegisterExpression(amdgpu_gfx90a::v216, output_vec_len ); + case 473: return makeRegisterExpression(amdgpu_gfx90a::v217, output_vec_len ); + case 474: return makeRegisterExpression(amdgpu_gfx90a::v218, output_vec_len ); + case 475: return makeRegisterExpression(amdgpu_gfx90a::v219, output_vec_len ); + case 476: return makeRegisterExpression(amdgpu_gfx90a::v220, output_vec_len ); + case 477: return makeRegisterExpression(amdgpu_gfx90a::v221, output_vec_len ); + case 478: return makeRegisterExpression(amdgpu_gfx90a::v222, output_vec_len ); + case 479: return makeRegisterExpression(amdgpu_gfx90a::v223, output_vec_len ); + case 480: return makeRegisterExpression(amdgpu_gfx90a::v224, output_vec_len ); + case 481: return makeRegisterExpression(amdgpu_gfx90a::v225, output_vec_len ); + case 482: return makeRegisterExpression(amdgpu_gfx90a::v226, output_vec_len ); + case 483: return makeRegisterExpression(amdgpu_gfx90a::v227, output_vec_len ); + case 484: return makeRegisterExpression(amdgpu_gfx90a::v228, output_vec_len ); + case 485: return makeRegisterExpression(amdgpu_gfx90a::v229, output_vec_len ); + case 486: return makeRegisterExpression(amdgpu_gfx90a::v230, output_vec_len ); + case 487: return makeRegisterExpression(amdgpu_gfx90a::v231, output_vec_len ); + case 488: return makeRegisterExpression(amdgpu_gfx90a::v232, output_vec_len ); + case 489: return makeRegisterExpression(amdgpu_gfx90a::v233, output_vec_len ); + case 490: return makeRegisterExpression(amdgpu_gfx90a::v234, output_vec_len ); + case 491: return makeRegisterExpression(amdgpu_gfx90a::v235, output_vec_len ); + case 492: return makeRegisterExpression(amdgpu_gfx90a::v236, output_vec_len ); + case 493: return makeRegisterExpression(amdgpu_gfx90a::v237, output_vec_len ); + case 494: return makeRegisterExpression(amdgpu_gfx90a::v238, output_vec_len ); + case 495: return makeRegisterExpression(amdgpu_gfx90a::v239, output_vec_len ); + case 496: return makeRegisterExpression(amdgpu_gfx90a::v240, output_vec_len ); + case 497: return makeRegisterExpression(amdgpu_gfx90a::v241, output_vec_len ); + case 498: return makeRegisterExpression(amdgpu_gfx90a::v242, output_vec_len ); + case 499: return makeRegisterExpression(amdgpu_gfx90a::v243, output_vec_len ); + case 500: return makeRegisterExpression(amdgpu_gfx90a::v244, output_vec_len ); + case 501: return makeRegisterExpression(amdgpu_gfx90a::v245, output_vec_len ); + case 502: return makeRegisterExpression(amdgpu_gfx90a::v246, output_vec_len ); + case 503: return makeRegisterExpression(amdgpu_gfx90a::v247, output_vec_len ); + case 504: return makeRegisterExpression(amdgpu_gfx90a::v248, output_vec_len ); + case 505: return makeRegisterExpression(amdgpu_gfx90a::v249, output_vec_len ); + case 506: return makeRegisterExpression(amdgpu_gfx90a::v250, output_vec_len ); + case 507: return makeRegisterExpression(amdgpu_gfx90a::v251, output_vec_len ); + case 508: return makeRegisterExpression(amdgpu_gfx90a::v252, output_vec_len ); + case 509: return makeRegisterExpression(amdgpu_gfx90a::v253, output_vec_len ); + case 510: return makeRegisterExpression(amdgpu_gfx90a::v254, output_vec_len ); + case 511: return makeRegisterExpression(amdgpu_gfx90a::v255, output_vec_len ); + default: return makeRegisterExpression(amdgpu_gfx90a::invalid); + } + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx90a::decodeOPR_SRC_VGPR(uint64_t input, uint32_t output_vec_len) + { + switch (input) { + case 256: return makeRegisterExpression(amdgpu_gfx90a::v0, output_vec_len ); + case 257: return makeRegisterExpression(amdgpu_gfx90a::v1, output_vec_len ); + case 258: return makeRegisterExpression(amdgpu_gfx90a::v2, output_vec_len ); + case 259: return makeRegisterExpression(amdgpu_gfx90a::v3, output_vec_len ); + case 260: return makeRegisterExpression(amdgpu_gfx90a::v4, output_vec_len ); + case 261: return makeRegisterExpression(amdgpu_gfx90a::v5, output_vec_len ); + case 262: return makeRegisterExpression(amdgpu_gfx90a::v6, output_vec_len ); + case 263: return makeRegisterExpression(amdgpu_gfx90a::v7, output_vec_len ); + case 264: return makeRegisterExpression(amdgpu_gfx90a::v8, output_vec_len ); + case 265: return makeRegisterExpression(amdgpu_gfx90a::v9, output_vec_len ); + case 266: return makeRegisterExpression(amdgpu_gfx90a::v10, output_vec_len ); + case 267: return makeRegisterExpression(amdgpu_gfx90a::v11, output_vec_len ); + case 268: return makeRegisterExpression(amdgpu_gfx90a::v12, output_vec_len ); + case 269: return makeRegisterExpression(amdgpu_gfx90a::v13, output_vec_len ); + case 270: return makeRegisterExpression(amdgpu_gfx90a::v14, output_vec_len ); + case 271: return makeRegisterExpression(amdgpu_gfx90a::v15, output_vec_len ); + case 272: return makeRegisterExpression(amdgpu_gfx90a::v16, output_vec_len ); + case 273: return makeRegisterExpression(amdgpu_gfx90a::v17, output_vec_len ); + case 274: return makeRegisterExpression(amdgpu_gfx90a::v18, output_vec_len ); + case 275: return makeRegisterExpression(amdgpu_gfx90a::v19, output_vec_len ); + case 276: return makeRegisterExpression(amdgpu_gfx90a::v20, output_vec_len ); + case 277: return makeRegisterExpression(amdgpu_gfx90a::v21, output_vec_len ); + case 278: return makeRegisterExpression(amdgpu_gfx90a::v22, output_vec_len ); + case 279: return makeRegisterExpression(amdgpu_gfx90a::v23, output_vec_len ); + case 280: return makeRegisterExpression(amdgpu_gfx90a::v24, output_vec_len ); + case 281: return makeRegisterExpression(amdgpu_gfx90a::v25, output_vec_len ); + case 282: return makeRegisterExpression(amdgpu_gfx90a::v26, output_vec_len ); + case 283: return makeRegisterExpression(amdgpu_gfx90a::v27, output_vec_len ); + case 284: return makeRegisterExpression(amdgpu_gfx90a::v28, output_vec_len ); + case 285: return makeRegisterExpression(amdgpu_gfx90a::v29, output_vec_len ); + case 286: return makeRegisterExpression(amdgpu_gfx90a::v30, output_vec_len ); + case 287: return makeRegisterExpression(amdgpu_gfx90a::v31, output_vec_len ); + case 288: return makeRegisterExpression(amdgpu_gfx90a::v32, output_vec_len ); + case 289: return makeRegisterExpression(amdgpu_gfx90a::v33, output_vec_len ); + case 290: return makeRegisterExpression(amdgpu_gfx90a::v34, output_vec_len ); + case 291: return makeRegisterExpression(amdgpu_gfx90a::v35, output_vec_len ); + case 292: return makeRegisterExpression(amdgpu_gfx90a::v36, output_vec_len ); + case 293: return makeRegisterExpression(amdgpu_gfx90a::v37, output_vec_len ); + case 294: return makeRegisterExpression(amdgpu_gfx90a::v38, output_vec_len ); + case 295: return makeRegisterExpression(amdgpu_gfx90a::v39, output_vec_len ); + case 296: return makeRegisterExpression(amdgpu_gfx90a::v40, output_vec_len ); + case 297: return makeRegisterExpression(amdgpu_gfx90a::v41, output_vec_len ); + case 298: return makeRegisterExpression(amdgpu_gfx90a::v42, output_vec_len ); + case 299: return makeRegisterExpression(amdgpu_gfx90a::v43, output_vec_len ); + case 300: return makeRegisterExpression(amdgpu_gfx90a::v44, output_vec_len ); + case 301: return makeRegisterExpression(amdgpu_gfx90a::v45, output_vec_len ); + case 302: return makeRegisterExpression(amdgpu_gfx90a::v46, output_vec_len ); + case 303: return makeRegisterExpression(amdgpu_gfx90a::v47, output_vec_len ); + case 304: return makeRegisterExpression(amdgpu_gfx90a::v48, output_vec_len ); + case 305: return makeRegisterExpression(amdgpu_gfx90a::v49, output_vec_len ); + case 306: return makeRegisterExpression(amdgpu_gfx90a::v50, output_vec_len ); + case 307: return makeRegisterExpression(amdgpu_gfx90a::v51, output_vec_len ); + case 308: return makeRegisterExpression(amdgpu_gfx90a::v52, output_vec_len ); + case 309: return makeRegisterExpression(amdgpu_gfx90a::v53, output_vec_len ); + case 310: return makeRegisterExpression(amdgpu_gfx90a::v54, output_vec_len ); + case 311: return makeRegisterExpression(amdgpu_gfx90a::v55, output_vec_len ); + case 312: return makeRegisterExpression(amdgpu_gfx90a::v56, output_vec_len ); + case 313: return makeRegisterExpression(amdgpu_gfx90a::v57, output_vec_len ); + case 314: return makeRegisterExpression(amdgpu_gfx90a::v58, output_vec_len ); + case 315: return makeRegisterExpression(amdgpu_gfx90a::v59, output_vec_len ); + case 316: return makeRegisterExpression(amdgpu_gfx90a::v60, output_vec_len ); + case 317: return makeRegisterExpression(amdgpu_gfx90a::v61, output_vec_len ); + case 318: return makeRegisterExpression(amdgpu_gfx90a::v62, output_vec_len ); + case 319: return makeRegisterExpression(amdgpu_gfx90a::v63, output_vec_len ); + case 320: return makeRegisterExpression(amdgpu_gfx90a::v64, output_vec_len ); + case 321: return makeRegisterExpression(amdgpu_gfx90a::v65, output_vec_len ); + case 322: return makeRegisterExpression(amdgpu_gfx90a::v66, output_vec_len ); + case 323: return makeRegisterExpression(amdgpu_gfx90a::v67, output_vec_len ); + case 324: return makeRegisterExpression(amdgpu_gfx90a::v68, output_vec_len ); + case 325: return makeRegisterExpression(amdgpu_gfx90a::v69, output_vec_len ); + case 326: return makeRegisterExpression(amdgpu_gfx90a::v70, output_vec_len ); + case 327: return makeRegisterExpression(amdgpu_gfx90a::v71, output_vec_len ); + case 328: return makeRegisterExpression(amdgpu_gfx90a::v72, output_vec_len ); + case 329: return makeRegisterExpression(amdgpu_gfx90a::v73, output_vec_len ); + case 330: return makeRegisterExpression(amdgpu_gfx90a::v74, output_vec_len ); + case 331: return makeRegisterExpression(amdgpu_gfx90a::v75, output_vec_len ); + case 332: return makeRegisterExpression(amdgpu_gfx90a::v76, output_vec_len ); + case 333: return makeRegisterExpression(amdgpu_gfx90a::v77, output_vec_len ); + case 334: return makeRegisterExpression(amdgpu_gfx90a::v78, output_vec_len ); + case 335: return makeRegisterExpression(amdgpu_gfx90a::v79, output_vec_len ); + case 336: return makeRegisterExpression(amdgpu_gfx90a::v80, output_vec_len ); + case 337: return makeRegisterExpression(amdgpu_gfx90a::v81, output_vec_len ); + case 338: return makeRegisterExpression(amdgpu_gfx90a::v82, output_vec_len ); + case 339: return makeRegisterExpression(amdgpu_gfx90a::v83, output_vec_len ); + case 340: return makeRegisterExpression(amdgpu_gfx90a::v84, output_vec_len ); + case 341: return makeRegisterExpression(amdgpu_gfx90a::v85, output_vec_len ); + case 342: return makeRegisterExpression(amdgpu_gfx90a::v86, output_vec_len ); + case 343: return makeRegisterExpression(amdgpu_gfx90a::v87, output_vec_len ); + case 344: return makeRegisterExpression(amdgpu_gfx90a::v88, output_vec_len ); + case 345: return makeRegisterExpression(amdgpu_gfx90a::v89, output_vec_len ); + case 346: return makeRegisterExpression(amdgpu_gfx90a::v90, output_vec_len ); + case 347: return makeRegisterExpression(amdgpu_gfx90a::v91, output_vec_len ); + case 348: return makeRegisterExpression(amdgpu_gfx90a::v92, output_vec_len ); + case 349: return makeRegisterExpression(amdgpu_gfx90a::v93, output_vec_len ); + case 350: return makeRegisterExpression(amdgpu_gfx90a::v94, output_vec_len ); + case 351: return makeRegisterExpression(amdgpu_gfx90a::v95, output_vec_len ); + case 352: return makeRegisterExpression(amdgpu_gfx90a::v96, output_vec_len ); + case 353: return makeRegisterExpression(amdgpu_gfx90a::v97, output_vec_len ); + case 354: return makeRegisterExpression(amdgpu_gfx90a::v98, output_vec_len ); + case 355: return makeRegisterExpression(amdgpu_gfx90a::v99, output_vec_len ); + case 356: return makeRegisterExpression(amdgpu_gfx90a::v100, output_vec_len ); + case 357: return makeRegisterExpression(amdgpu_gfx90a::v101, output_vec_len ); + case 358: return makeRegisterExpression(amdgpu_gfx90a::v102, output_vec_len ); + case 359: return makeRegisterExpression(amdgpu_gfx90a::v103, output_vec_len ); + case 360: return makeRegisterExpression(amdgpu_gfx90a::v104, output_vec_len ); + case 361: return makeRegisterExpression(amdgpu_gfx90a::v105, output_vec_len ); + case 362: return makeRegisterExpression(amdgpu_gfx90a::v106, output_vec_len ); + case 363: return makeRegisterExpression(amdgpu_gfx90a::v107, output_vec_len ); + case 364: return makeRegisterExpression(amdgpu_gfx90a::v108, output_vec_len ); + case 365: return makeRegisterExpression(amdgpu_gfx90a::v109, output_vec_len ); + case 366: return makeRegisterExpression(amdgpu_gfx90a::v110, output_vec_len ); + case 367: return makeRegisterExpression(amdgpu_gfx90a::v111, output_vec_len ); + case 368: return makeRegisterExpression(amdgpu_gfx90a::v112, output_vec_len ); + case 369: return makeRegisterExpression(amdgpu_gfx90a::v113, output_vec_len ); + case 370: return makeRegisterExpression(amdgpu_gfx90a::v114, output_vec_len ); + case 371: return makeRegisterExpression(amdgpu_gfx90a::v115, output_vec_len ); + case 372: return makeRegisterExpression(amdgpu_gfx90a::v116, output_vec_len ); + case 373: return makeRegisterExpression(amdgpu_gfx90a::v117, output_vec_len ); + case 374: return makeRegisterExpression(amdgpu_gfx90a::v118, output_vec_len ); + case 375: return makeRegisterExpression(amdgpu_gfx90a::v119, output_vec_len ); + case 376: return makeRegisterExpression(amdgpu_gfx90a::v120, output_vec_len ); + case 377: return makeRegisterExpression(amdgpu_gfx90a::v121, output_vec_len ); + case 378: return makeRegisterExpression(amdgpu_gfx90a::v122, output_vec_len ); + case 379: return makeRegisterExpression(amdgpu_gfx90a::v123, output_vec_len ); + case 380: return makeRegisterExpression(amdgpu_gfx90a::v124, output_vec_len ); + case 381: return makeRegisterExpression(amdgpu_gfx90a::v125, output_vec_len ); + case 382: return makeRegisterExpression(amdgpu_gfx90a::v126, output_vec_len ); + case 383: return makeRegisterExpression(amdgpu_gfx90a::v127, output_vec_len ); + case 384: return makeRegisterExpression(amdgpu_gfx90a::v128, output_vec_len ); + case 385: return makeRegisterExpression(amdgpu_gfx90a::v129, output_vec_len ); + case 386: return makeRegisterExpression(amdgpu_gfx90a::v130, output_vec_len ); + case 387: return makeRegisterExpression(amdgpu_gfx90a::v131, output_vec_len ); + case 388: return makeRegisterExpression(amdgpu_gfx90a::v132, output_vec_len ); + case 389: return makeRegisterExpression(amdgpu_gfx90a::v133, output_vec_len ); + case 390: return makeRegisterExpression(amdgpu_gfx90a::v134, output_vec_len ); + case 391: return makeRegisterExpression(amdgpu_gfx90a::v135, output_vec_len ); + case 392: return makeRegisterExpression(amdgpu_gfx90a::v136, output_vec_len ); + case 393: return makeRegisterExpression(amdgpu_gfx90a::v137, output_vec_len ); + case 394: return makeRegisterExpression(amdgpu_gfx90a::v138, output_vec_len ); + case 395: return makeRegisterExpression(amdgpu_gfx90a::v139, output_vec_len ); + case 396: return makeRegisterExpression(amdgpu_gfx90a::v140, output_vec_len ); + case 397: return makeRegisterExpression(amdgpu_gfx90a::v141, output_vec_len ); + case 398: return makeRegisterExpression(amdgpu_gfx90a::v142, output_vec_len ); + case 399: return makeRegisterExpression(amdgpu_gfx90a::v143, output_vec_len ); + case 400: return makeRegisterExpression(amdgpu_gfx90a::v144, output_vec_len ); + case 401: return makeRegisterExpression(amdgpu_gfx90a::v145, output_vec_len ); + case 402: return makeRegisterExpression(amdgpu_gfx90a::v146, output_vec_len ); + case 403: return makeRegisterExpression(amdgpu_gfx90a::v147, output_vec_len ); + case 404: return makeRegisterExpression(amdgpu_gfx90a::v148, output_vec_len ); + case 405: return makeRegisterExpression(amdgpu_gfx90a::v149, output_vec_len ); + case 406: return makeRegisterExpression(amdgpu_gfx90a::v150, output_vec_len ); + case 407: return makeRegisterExpression(amdgpu_gfx90a::v151, output_vec_len ); + case 408: return makeRegisterExpression(amdgpu_gfx90a::v152, output_vec_len ); + case 409: return makeRegisterExpression(amdgpu_gfx90a::v153, output_vec_len ); + case 410: return makeRegisterExpression(amdgpu_gfx90a::v154, output_vec_len ); + case 411: return makeRegisterExpression(amdgpu_gfx90a::v155, output_vec_len ); + case 412: return makeRegisterExpression(amdgpu_gfx90a::v156, output_vec_len ); + case 413: return makeRegisterExpression(amdgpu_gfx90a::v157, output_vec_len ); + case 414: return makeRegisterExpression(amdgpu_gfx90a::v158, output_vec_len ); + case 415: return makeRegisterExpression(amdgpu_gfx90a::v159, output_vec_len ); + case 416: return makeRegisterExpression(amdgpu_gfx90a::v160, output_vec_len ); + case 417: return makeRegisterExpression(amdgpu_gfx90a::v161, output_vec_len ); + case 418: return makeRegisterExpression(amdgpu_gfx90a::v162, output_vec_len ); + case 419: return makeRegisterExpression(amdgpu_gfx90a::v163, output_vec_len ); + case 420: return makeRegisterExpression(amdgpu_gfx90a::v164, output_vec_len ); + case 421: return makeRegisterExpression(amdgpu_gfx90a::v165, output_vec_len ); + case 422: return makeRegisterExpression(amdgpu_gfx90a::v166, output_vec_len ); + case 423: return makeRegisterExpression(amdgpu_gfx90a::v167, output_vec_len ); + case 424: return makeRegisterExpression(amdgpu_gfx90a::v168, output_vec_len ); + case 425: return makeRegisterExpression(amdgpu_gfx90a::v169, output_vec_len ); + case 426: return makeRegisterExpression(amdgpu_gfx90a::v170, output_vec_len ); + case 427: return makeRegisterExpression(amdgpu_gfx90a::v171, output_vec_len ); + case 428: return makeRegisterExpression(amdgpu_gfx90a::v172, output_vec_len ); + case 429: return makeRegisterExpression(amdgpu_gfx90a::v173, output_vec_len ); + case 430: return makeRegisterExpression(amdgpu_gfx90a::v174, output_vec_len ); + case 431: return makeRegisterExpression(amdgpu_gfx90a::v175, output_vec_len ); + case 432: return makeRegisterExpression(amdgpu_gfx90a::v176, output_vec_len ); + case 433: return makeRegisterExpression(amdgpu_gfx90a::v177, output_vec_len ); + case 434: return makeRegisterExpression(amdgpu_gfx90a::v178, output_vec_len ); + case 435: return makeRegisterExpression(amdgpu_gfx90a::v179, output_vec_len ); + case 436: return makeRegisterExpression(amdgpu_gfx90a::v180, output_vec_len ); + case 437: return makeRegisterExpression(amdgpu_gfx90a::v181, output_vec_len ); + case 438: return makeRegisterExpression(amdgpu_gfx90a::v182, output_vec_len ); + case 439: return makeRegisterExpression(amdgpu_gfx90a::v183, output_vec_len ); + case 440: return makeRegisterExpression(amdgpu_gfx90a::v184, output_vec_len ); + case 441: return makeRegisterExpression(amdgpu_gfx90a::v185, output_vec_len ); + case 442: return makeRegisterExpression(amdgpu_gfx90a::v186, output_vec_len ); + case 443: return makeRegisterExpression(amdgpu_gfx90a::v187, output_vec_len ); + case 444: return makeRegisterExpression(amdgpu_gfx90a::v188, output_vec_len ); + case 445: return makeRegisterExpression(amdgpu_gfx90a::v189, output_vec_len ); + case 446: return makeRegisterExpression(amdgpu_gfx90a::v190, output_vec_len ); + case 447: return makeRegisterExpression(amdgpu_gfx90a::v191, output_vec_len ); + case 448: return makeRegisterExpression(amdgpu_gfx90a::v192, output_vec_len ); + case 449: return makeRegisterExpression(amdgpu_gfx90a::v193, output_vec_len ); + case 450: return makeRegisterExpression(amdgpu_gfx90a::v194, output_vec_len ); + case 451: return makeRegisterExpression(amdgpu_gfx90a::v195, output_vec_len ); + case 452: return makeRegisterExpression(amdgpu_gfx90a::v196, output_vec_len ); + case 453: return makeRegisterExpression(amdgpu_gfx90a::v197, output_vec_len ); + case 454: return makeRegisterExpression(amdgpu_gfx90a::v198, output_vec_len ); + case 455: return makeRegisterExpression(amdgpu_gfx90a::v199, output_vec_len ); + case 456: return makeRegisterExpression(amdgpu_gfx90a::v200, output_vec_len ); + case 457: return makeRegisterExpression(amdgpu_gfx90a::v201, output_vec_len ); + case 458: return makeRegisterExpression(amdgpu_gfx90a::v202, output_vec_len ); + case 459: return makeRegisterExpression(amdgpu_gfx90a::v203, output_vec_len ); + case 460: return makeRegisterExpression(amdgpu_gfx90a::v204, output_vec_len ); + case 461: return makeRegisterExpression(amdgpu_gfx90a::v205, output_vec_len ); + case 462: return makeRegisterExpression(amdgpu_gfx90a::v206, output_vec_len ); + case 463: return makeRegisterExpression(amdgpu_gfx90a::v207, output_vec_len ); + case 464: return makeRegisterExpression(amdgpu_gfx90a::v208, output_vec_len ); + case 465: return makeRegisterExpression(amdgpu_gfx90a::v209, output_vec_len ); + case 466: return makeRegisterExpression(amdgpu_gfx90a::v210, output_vec_len ); + case 467: return makeRegisterExpression(amdgpu_gfx90a::v211, output_vec_len ); + case 468: return makeRegisterExpression(amdgpu_gfx90a::v212, output_vec_len ); + case 469: return makeRegisterExpression(amdgpu_gfx90a::v213, output_vec_len ); + case 470: return makeRegisterExpression(amdgpu_gfx90a::v214, output_vec_len ); + case 471: return makeRegisterExpression(amdgpu_gfx90a::v215, output_vec_len ); + case 472: return makeRegisterExpression(amdgpu_gfx90a::v216, output_vec_len ); + case 473: return makeRegisterExpression(amdgpu_gfx90a::v217, output_vec_len ); + case 474: return makeRegisterExpression(amdgpu_gfx90a::v218, output_vec_len ); + case 475: return makeRegisterExpression(amdgpu_gfx90a::v219, output_vec_len ); + case 476: return makeRegisterExpression(amdgpu_gfx90a::v220, output_vec_len ); + case 477: return makeRegisterExpression(amdgpu_gfx90a::v221, output_vec_len ); + case 478: return makeRegisterExpression(amdgpu_gfx90a::v222, output_vec_len ); + case 479: return makeRegisterExpression(amdgpu_gfx90a::v223, output_vec_len ); + case 480: return makeRegisterExpression(amdgpu_gfx90a::v224, output_vec_len ); + case 481: return makeRegisterExpression(amdgpu_gfx90a::v225, output_vec_len ); + case 482: return makeRegisterExpression(amdgpu_gfx90a::v226, output_vec_len ); + case 483: return makeRegisterExpression(amdgpu_gfx90a::v227, output_vec_len ); + case 484: return makeRegisterExpression(amdgpu_gfx90a::v228, output_vec_len ); + case 485: return makeRegisterExpression(amdgpu_gfx90a::v229, output_vec_len ); + case 486: return makeRegisterExpression(amdgpu_gfx90a::v230, output_vec_len ); + case 487: return makeRegisterExpression(amdgpu_gfx90a::v231, output_vec_len ); + case 488: return makeRegisterExpression(amdgpu_gfx90a::v232, output_vec_len ); + case 489: return makeRegisterExpression(amdgpu_gfx90a::v233, output_vec_len ); + case 490: return makeRegisterExpression(amdgpu_gfx90a::v234, output_vec_len ); + case 491: return makeRegisterExpression(amdgpu_gfx90a::v235, output_vec_len ); + case 492: return makeRegisterExpression(amdgpu_gfx90a::v236, output_vec_len ); + case 493: return makeRegisterExpression(amdgpu_gfx90a::v237, output_vec_len ); + case 494: return makeRegisterExpression(amdgpu_gfx90a::v238, output_vec_len ); + case 495: return makeRegisterExpression(amdgpu_gfx90a::v239, output_vec_len ); + case 496: return makeRegisterExpression(amdgpu_gfx90a::v240, output_vec_len ); + case 497: return makeRegisterExpression(amdgpu_gfx90a::v241, output_vec_len ); + case 498: return makeRegisterExpression(amdgpu_gfx90a::v242, output_vec_len ); + case 499: return makeRegisterExpression(amdgpu_gfx90a::v243, output_vec_len ); + case 500: return makeRegisterExpression(amdgpu_gfx90a::v244, output_vec_len ); + case 501: return makeRegisterExpression(amdgpu_gfx90a::v245, output_vec_len ); + case 502: return makeRegisterExpression(amdgpu_gfx90a::v246, output_vec_len ); + case 503: return makeRegisterExpression(amdgpu_gfx90a::v247, output_vec_len ); + case 504: return makeRegisterExpression(amdgpu_gfx90a::v248, output_vec_len ); + case 505: return makeRegisterExpression(amdgpu_gfx90a::v249, output_vec_len ); + case 506: return makeRegisterExpression(amdgpu_gfx90a::v250, output_vec_len ); + case 507: return makeRegisterExpression(amdgpu_gfx90a::v251, output_vec_len ); + case 508: return makeRegisterExpression(amdgpu_gfx90a::v252, output_vec_len ); + case 509: return makeRegisterExpression(amdgpu_gfx90a::v253, output_vec_len ); + case 510: return makeRegisterExpression(amdgpu_gfx90a::v254, output_vec_len ); + case 511: return makeRegisterExpression(amdgpu_gfx90a::v255, output_vec_len ); + default: return makeRegisterExpression(amdgpu_gfx90a::invalid); + } + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx90a::decodeOPR_SRC_VGPR_OR_ACCVGPR(uint64_t input, uint32_t output_vec_len) + { + switch (input) { + case 256: return makeRegisterExpression(amdgpu_gfx90a::v0, output_vec_len ); + case 257: return makeRegisterExpression(amdgpu_gfx90a::v1, output_vec_len ); + case 258: return makeRegisterExpression(amdgpu_gfx90a::v2, output_vec_len ); + case 259: return makeRegisterExpression(amdgpu_gfx90a::v3, output_vec_len ); + case 260: return makeRegisterExpression(amdgpu_gfx90a::v4, output_vec_len ); + case 261: return makeRegisterExpression(amdgpu_gfx90a::v5, output_vec_len ); + case 262: return makeRegisterExpression(amdgpu_gfx90a::v6, output_vec_len ); + case 263: return makeRegisterExpression(amdgpu_gfx90a::v7, output_vec_len ); + case 264: return makeRegisterExpression(amdgpu_gfx90a::v8, output_vec_len ); + case 265: return makeRegisterExpression(amdgpu_gfx90a::v9, output_vec_len ); + case 266: return makeRegisterExpression(amdgpu_gfx90a::v10, output_vec_len ); + case 267: return makeRegisterExpression(amdgpu_gfx90a::v11, output_vec_len ); + case 268: return makeRegisterExpression(amdgpu_gfx90a::v12, output_vec_len ); + case 269: return makeRegisterExpression(amdgpu_gfx90a::v13, output_vec_len ); + case 270: return makeRegisterExpression(amdgpu_gfx90a::v14, output_vec_len ); + case 271: return makeRegisterExpression(amdgpu_gfx90a::v15, output_vec_len ); + case 272: return makeRegisterExpression(amdgpu_gfx90a::v16, output_vec_len ); + case 273: return makeRegisterExpression(amdgpu_gfx90a::v17, output_vec_len ); + case 274: return makeRegisterExpression(amdgpu_gfx90a::v18, output_vec_len ); + case 275: return makeRegisterExpression(amdgpu_gfx90a::v19, output_vec_len ); + case 276: return makeRegisterExpression(amdgpu_gfx90a::v20, output_vec_len ); + case 277: return makeRegisterExpression(amdgpu_gfx90a::v21, output_vec_len ); + case 278: return makeRegisterExpression(amdgpu_gfx90a::v22, output_vec_len ); + case 279: return makeRegisterExpression(amdgpu_gfx90a::v23, output_vec_len ); + case 280: return makeRegisterExpression(amdgpu_gfx90a::v24, output_vec_len ); + case 281: return makeRegisterExpression(amdgpu_gfx90a::v25, output_vec_len ); + case 282: return makeRegisterExpression(amdgpu_gfx90a::v26, output_vec_len ); + case 283: return makeRegisterExpression(amdgpu_gfx90a::v27, output_vec_len ); + case 284: return makeRegisterExpression(amdgpu_gfx90a::v28, output_vec_len ); + case 285: return makeRegisterExpression(amdgpu_gfx90a::v29, output_vec_len ); + case 286: return makeRegisterExpression(amdgpu_gfx90a::v30, output_vec_len ); + case 287: return makeRegisterExpression(amdgpu_gfx90a::v31, output_vec_len ); + case 288: return makeRegisterExpression(amdgpu_gfx90a::v32, output_vec_len ); + case 289: return makeRegisterExpression(amdgpu_gfx90a::v33, output_vec_len ); + case 290: return makeRegisterExpression(amdgpu_gfx90a::v34, output_vec_len ); + case 291: return makeRegisterExpression(amdgpu_gfx90a::v35, output_vec_len ); + case 292: return makeRegisterExpression(amdgpu_gfx90a::v36, output_vec_len ); + case 293: return makeRegisterExpression(amdgpu_gfx90a::v37, output_vec_len ); + case 294: return makeRegisterExpression(amdgpu_gfx90a::v38, output_vec_len ); + case 295: return makeRegisterExpression(amdgpu_gfx90a::v39, output_vec_len ); + case 296: return makeRegisterExpression(amdgpu_gfx90a::v40, output_vec_len ); + case 297: return makeRegisterExpression(amdgpu_gfx90a::v41, output_vec_len ); + case 298: return makeRegisterExpression(amdgpu_gfx90a::v42, output_vec_len ); + case 299: return makeRegisterExpression(amdgpu_gfx90a::v43, output_vec_len ); + case 300: return makeRegisterExpression(amdgpu_gfx90a::v44, output_vec_len ); + case 301: return makeRegisterExpression(amdgpu_gfx90a::v45, output_vec_len ); + case 302: return makeRegisterExpression(amdgpu_gfx90a::v46, output_vec_len ); + case 303: return makeRegisterExpression(amdgpu_gfx90a::v47, output_vec_len ); + case 304: return makeRegisterExpression(amdgpu_gfx90a::v48, output_vec_len ); + case 305: return makeRegisterExpression(amdgpu_gfx90a::v49, output_vec_len ); + case 306: return makeRegisterExpression(amdgpu_gfx90a::v50, output_vec_len ); + case 307: return makeRegisterExpression(amdgpu_gfx90a::v51, output_vec_len ); + case 308: return makeRegisterExpression(amdgpu_gfx90a::v52, output_vec_len ); + case 309: return makeRegisterExpression(amdgpu_gfx90a::v53, output_vec_len ); + case 310: return makeRegisterExpression(amdgpu_gfx90a::v54, output_vec_len ); + case 311: return makeRegisterExpression(amdgpu_gfx90a::v55, output_vec_len ); + case 312: return makeRegisterExpression(amdgpu_gfx90a::v56, output_vec_len ); + case 313: return makeRegisterExpression(amdgpu_gfx90a::v57, output_vec_len ); + case 314: return makeRegisterExpression(amdgpu_gfx90a::v58, output_vec_len ); + case 315: return makeRegisterExpression(amdgpu_gfx90a::v59, output_vec_len ); + case 316: return makeRegisterExpression(amdgpu_gfx90a::v60, output_vec_len ); + case 317: return makeRegisterExpression(amdgpu_gfx90a::v61, output_vec_len ); + case 318: return makeRegisterExpression(amdgpu_gfx90a::v62, output_vec_len ); + case 319: return makeRegisterExpression(amdgpu_gfx90a::v63, output_vec_len ); + case 320: return makeRegisterExpression(amdgpu_gfx90a::v64, output_vec_len ); + case 321: return makeRegisterExpression(amdgpu_gfx90a::v65, output_vec_len ); + case 322: return makeRegisterExpression(amdgpu_gfx90a::v66, output_vec_len ); + case 323: return makeRegisterExpression(amdgpu_gfx90a::v67, output_vec_len ); + case 324: return makeRegisterExpression(amdgpu_gfx90a::v68, output_vec_len ); + case 325: return makeRegisterExpression(amdgpu_gfx90a::v69, output_vec_len ); + case 326: return makeRegisterExpression(amdgpu_gfx90a::v70, output_vec_len ); + case 327: return makeRegisterExpression(amdgpu_gfx90a::v71, output_vec_len ); + case 328: return makeRegisterExpression(amdgpu_gfx90a::v72, output_vec_len ); + case 329: return makeRegisterExpression(amdgpu_gfx90a::v73, output_vec_len ); + case 330: return makeRegisterExpression(amdgpu_gfx90a::v74, output_vec_len ); + case 331: return makeRegisterExpression(amdgpu_gfx90a::v75, output_vec_len ); + case 332: return makeRegisterExpression(amdgpu_gfx90a::v76, output_vec_len ); + case 333: return makeRegisterExpression(amdgpu_gfx90a::v77, output_vec_len ); + case 334: return makeRegisterExpression(amdgpu_gfx90a::v78, output_vec_len ); + case 335: return makeRegisterExpression(amdgpu_gfx90a::v79, output_vec_len ); + case 336: return makeRegisterExpression(amdgpu_gfx90a::v80, output_vec_len ); + case 337: return makeRegisterExpression(amdgpu_gfx90a::v81, output_vec_len ); + case 338: return makeRegisterExpression(amdgpu_gfx90a::v82, output_vec_len ); + case 339: return makeRegisterExpression(amdgpu_gfx90a::v83, output_vec_len ); + case 340: return makeRegisterExpression(amdgpu_gfx90a::v84, output_vec_len ); + case 341: return makeRegisterExpression(amdgpu_gfx90a::v85, output_vec_len ); + case 342: return makeRegisterExpression(amdgpu_gfx90a::v86, output_vec_len ); + case 343: return makeRegisterExpression(amdgpu_gfx90a::v87, output_vec_len ); + case 344: return makeRegisterExpression(amdgpu_gfx90a::v88, output_vec_len ); + case 345: return makeRegisterExpression(amdgpu_gfx90a::v89, output_vec_len ); + case 346: return makeRegisterExpression(amdgpu_gfx90a::v90, output_vec_len ); + case 347: return makeRegisterExpression(amdgpu_gfx90a::v91, output_vec_len ); + case 348: return makeRegisterExpression(amdgpu_gfx90a::v92, output_vec_len ); + case 349: return makeRegisterExpression(amdgpu_gfx90a::v93, output_vec_len ); + case 350: return makeRegisterExpression(amdgpu_gfx90a::v94, output_vec_len ); + case 351: return makeRegisterExpression(amdgpu_gfx90a::v95, output_vec_len ); + case 352: return makeRegisterExpression(amdgpu_gfx90a::v96, output_vec_len ); + case 353: return makeRegisterExpression(amdgpu_gfx90a::v97, output_vec_len ); + case 354: return makeRegisterExpression(amdgpu_gfx90a::v98, output_vec_len ); + case 355: return makeRegisterExpression(amdgpu_gfx90a::v99, output_vec_len ); + case 356: return makeRegisterExpression(amdgpu_gfx90a::v100, output_vec_len ); + case 357: return makeRegisterExpression(amdgpu_gfx90a::v101, output_vec_len ); + case 358: return makeRegisterExpression(amdgpu_gfx90a::v102, output_vec_len ); + case 359: return makeRegisterExpression(amdgpu_gfx90a::v103, output_vec_len ); + case 360: return makeRegisterExpression(amdgpu_gfx90a::v104, output_vec_len ); + case 361: return makeRegisterExpression(amdgpu_gfx90a::v105, output_vec_len ); + case 362: return makeRegisterExpression(amdgpu_gfx90a::v106, output_vec_len ); + case 363: return makeRegisterExpression(amdgpu_gfx90a::v107, output_vec_len ); + case 364: return makeRegisterExpression(amdgpu_gfx90a::v108, output_vec_len ); + case 365: return makeRegisterExpression(amdgpu_gfx90a::v109, output_vec_len ); + case 366: return makeRegisterExpression(amdgpu_gfx90a::v110, output_vec_len ); + case 367: return makeRegisterExpression(amdgpu_gfx90a::v111, output_vec_len ); + case 368: return makeRegisterExpression(amdgpu_gfx90a::v112, output_vec_len ); + case 369: return makeRegisterExpression(amdgpu_gfx90a::v113, output_vec_len ); + case 370: return makeRegisterExpression(amdgpu_gfx90a::v114, output_vec_len ); + case 371: return makeRegisterExpression(amdgpu_gfx90a::v115, output_vec_len ); + case 372: return makeRegisterExpression(amdgpu_gfx90a::v116, output_vec_len ); + case 373: return makeRegisterExpression(amdgpu_gfx90a::v117, output_vec_len ); + case 374: return makeRegisterExpression(amdgpu_gfx90a::v118, output_vec_len ); + case 375: return makeRegisterExpression(amdgpu_gfx90a::v119, output_vec_len ); + case 376: return makeRegisterExpression(amdgpu_gfx90a::v120, output_vec_len ); + case 377: return makeRegisterExpression(amdgpu_gfx90a::v121, output_vec_len ); + case 378: return makeRegisterExpression(amdgpu_gfx90a::v122, output_vec_len ); + case 379: return makeRegisterExpression(amdgpu_gfx90a::v123, output_vec_len ); + case 380: return makeRegisterExpression(amdgpu_gfx90a::v124, output_vec_len ); + case 381: return makeRegisterExpression(amdgpu_gfx90a::v125, output_vec_len ); + case 382: return makeRegisterExpression(amdgpu_gfx90a::v126, output_vec_len ); + case 383: return makeRegisterExpression(amdgpu_gfx90a::v127, output_vec_len ); + case 384: return makeRegisterExpression(amdgpu_gfx90a::v128, output_vec_len ); + case 385: return makeRegisterExpression(amdgpu_gfx90a::v129, output_vec_len ); + case 386: return makeRegisterExpression(amdgpu_gfx90a::v130, output_vec_len ); + case 387: return makeRegisterExpression(amdgpu_gfx90a::v131, output_vec_len ); + case 388: return makeRegisterExpression(amdgpu_gfx90a::v132, output_vec_len ); + case 389: return makeRegisterExpression(amdgpu_gfx90a::v133, output_vec_len ); + case 390: return makeRegisterExpression(amdgpu_gfx90a::v134, output_vec_len ); + case 391: return makeRegisterExpression(amdgpu_gfx90a::v135, output_vec_len ); + case 392: return makeRegisterExpression(amdgpu_gfx90a::v136, output_vec_len ); + case 393: return makeRegisterExpression(amdgpu_gfx90a::v137, output_vec_len ); + case 394: return makeRegisterExpression(amdgpu_gfx90a::v138, output_vec_len ); + case 395: return makeRegisterExpression(amdgpu_gfx90a::v139, output_vec_len ); + case 396: return makeRegisterExpression(amdgpu_gfx90a::v140, output_vec_len ); + case 397: return makeRegisterExpression(amdgpu_gfx90a::v141, output_vec_len ); + case 398: return makeRegisterExpression(amdgpu_gfx90a::v142, output_vec_len ); + case 399: return makeRegisterExpression(amdgpu_gfx90a::v143, output_vec_len ); + case 400: return makeRegisterExpression(amdgpu_gfx90a::v144, output_vec_len ); + case 401: return makeRegisterExpression(amdgpu_gfx90a::v145, output_vec_len ); + case 402: return makeRegisterExpression(amdgpu_gfx90a::v146, output_vec_len ); + case 403: return makeRegisterExpression(amdgpu_gfx90a::v147, output_vec_len ); + case 404: return makeRegisterExpression(amdgpu_gfx90a::v148, output_vec_len ); + case 405: return makeRegisterExpression(amdgpu_gfx90a::v149, output_vec_len ); + case 406: return makeRegisterExpression(amdgpu_gfx90a::v150, output_vec_len ); + case 407: return makeRegisterExpression(amdgpu_gfx90a::v151, output_vec_len ); + case 408: return makeRegisterExpression(amdgpu_gfx90a::v152, output_vec_len ); + case 409: return makeRegisterExpression(amdgpu_gfx90a::v153, output_vec_len ); + case 410: return makeRegisterExpression(amdgpu_gfx90a::v154, output_vec_len ); + case 411: return makeRegisterExpression(amdgpu_gfx90a::v155, output_vec_len ); + case 412: return makeRegisterExpression(amdgpu_gfx90a::v156, output_vec_len ); + case 413: return makeRegisterExpression(amdgpu_gfx90a::v157, output_vec_len ); + case 414: return makeRegisterExpression(amdgpu_gfx90a::v158, output_vec_len ); + case 415: return makeRegisterExpression(amdgpu_gfx90a::v159, output_vec_len ); + case 416: return makeRegisterExpression(amdgpu_gfx90a::v160, output_vec_len ); + case 417: return makeRegisterExpression(amdgpu_gfx90a::v161, output_vec_len ); + case 418: return makeRegisterExpression(amdgpu_gfx90a::v162, output_vec_len ); + case 419: return makeRegisterExpression(amdgpu_gfx90a::v163, output_vec_len ); + case 420: return makeRegisterExpression(amdgpu_gfx90a::v164, output_vec_len ); + case 421: return makeRegisterExpression(amdgpu_gfx90a::v165, output_vec_len ); + case 422: return makeRegisterExpression(amdgpu_gfx90a::v166, output_vec_len ); + case 423: return makeRegisterExpression(amdgpu_gfx90a::v167, output_vec_len ); + case 424: return makeRegisterExpression(amdgpu_gfx90a::v168, output_vec_len ); + case 425: return makeRegisterExpression(amdgpu_gfx90a::v169, output_vec_len ); + case 426: return makeRegisterExpression(amdgpu_gfx90a::v170, output_vec_len ); + case 427: return makeRegisterExpression(amdgpu_gfx90a::v171, output_vec_len ); + case 428: return makeRegisterExpression(amdgpu_gfx90a::v172, output_vec_len ); + case 429: return makeRegisterExpression(amdgpu_gfx90a::v173, output_vec_len ); + case 430: return makeRegisterExpression(amdgpu_gfx90a::v174, output_vec_len ); + case 431: return makeRegisterExpression(amdgpu_gfx90a::v175, output_vec_len ); + case 432: return makeRegisterExpression(amdgpu_gfx90a::v176, output_vec_len ); + case 433: return makeRegisterExpression(amdgpu_gfx90a::v177, output_vec_len ); + case 434: return makeRegisterExpression(amdgpu_gfx90a::v178, output_vec_len ); + case 435: return makeRegisterExpression(amdgpu_gfx90a::v179, output_vec_len ); + case 436: return makeRegisterExpression(amdgpu_gfx90a::v180, output_vec_len ); + case 437: return makeRegisterExpression(amdgpu_gfx90a::v181, output_vec_len ); + case 438: return makeRegisterExpression(amdgpu_gfx90a::v182, output_vec_len ); + case 439: return makeRegisterExpression(amdgpu_gfx90a::v183, output_vec_len ); + case 440: return makeRegisterExpression(amdgpu_gfx90a::v184, output_vec_len ); + case 441: return makeRegisterExpression(amdgpu_gfx90a::v185, output_vec_len ); + case 442: return makeRegisterExpression(amdgpu_gfx90a::v186, output_vec_len ); + case 443: return makeRegisterExpression(amdgpu_gfx90a::v187, output_vec_len ); + case 444: return makeRegisterExpression(amdgpu_gfx90a::v188, output_vec_len ); + case 445: return makeRegisterExpression(amdgpu_gfx90a::v189, output_vec_len ); + case 446: return makeRegisterExpression(amdgpu_gfx90a::v190, output_vec_len ); + case 447: return makeRegisterExpression(amdgpu_gfx90a::v191, output_vec_len ); + case 448: return makeRegisterExpression(amdgpu_gfx90a::v192, output_vec_len ); + case 449: return makeRegisterExpression(amdgpu_gfx90a::v193, output_vec_len ); + case 450: return makeRegisterExpression(amdgpu_gfx90a::v194, output_vec_len ); + case 451: return makeRegisterExpression(amdgpu_gfx90a::v195, output_vec_len ); + case 452: return makeRegisterExpression(amdgpu_gfx90a::v196, output_vec_len ); + case 453: return makeRegisterExpression(amdgpu_gfx90a::v197, output_vec_len ); + case 454: return makeRegisterExpression(amdgpu_gfx90a::v198, output_vec_len ); + case 455: return makeRegisterExpression(amdgpu_gfx90a::v199, output_vec_len ); + case 456: return makeRegisterExpression(amdgpu_gfx90a::v200, output_vec_len ); + case 457: return makeRegisterExpression(amdgpu_gfx90a::v201, output_vec_len ); + case 458: return makeRegisterExpression(amdgpu_gfx90a::v202, output_vec_len ); + case 459: return makeRegisterExpression(amdgpu_gfx90a::v203, output_vec_len ); + case 460: return makeRegisterExpression(amdgpu_gfx90a::v204, output_vec_len ); + case 461: return makeRegisterExpression(amdgpu_gfx90a::v205, output_vec_len ); + case 462: return makeRegisterExpression(amdgpu_gfx90a::v206, output_vec_len ); + case 463: return makeRegisterExpression(amdgpu_gfx90a::v207, output_vec_len ); + case 464: return makeRegisterExpression(amdgpu_gfx90a::v208, output_vec_len ); + case 465: return makeRegisterExpression(amdgpu_gfx90a::v209, output_vec_len ); + case 466: return makeRegisterExpression(amdgpu_gfx90a::v210, output_vec_len ); + case 467: return makeRegisterExpression(amdgpu_gfx90a::v211, output_vec_len ); + case 468: return makeRegisterExpression(amdgpu_gfx90a::v212, output_vec_len ); + case 469: return makeRegisterExpression(amdgpu_gfx90a::v213, output_vec_len ); + case 470: return makeRegisterExpression(amdgpu_gfx90a::v214, output_vec_len ); + case 471: return makeRegisterExpression(amdgpu_gfx90a::v215, output_vec_len ); + case 472: return makeRegisterExpression(amdgpu_gfx90a::v216, output_vec_len ); + case 473: return makeRegisterExpression(amdgpu_gfx90a::v217, output_vec_len ); + case 474: return makeRegisterExpression(amdgpu_gfx90a::v218, output_vec_len ); + case 475: return makeRegisterExpression(amdgpu_gfx90a::v219, output_vec_len ); + case 476: return makeRegisterExpression(amdgpu_gfx90a::v220, output_vec_len ); + case 477: return makeRegisterExpression(amdgpu_gfx90a::v221, output_vec_len ); + case 478: return makeRegisterExpression(amdgpu_gfx90a::v222, output_vec_len ); + case 479: return makeRegisterExpression(amdgpu_gfx90a::v223, output_vec_len ); + case 480: return makeRegisterExpression(amdgpu_gfx90a::v224, output_vec_len ); + case 481: return makeRegisterExpression(amdgpu_gfx90a::v225, output_vec_len ); + case 482: return makeRegisterExpression(amdgpu_gfx90a::v226, output_vec_len ); + case 483: return makeRegisterExpression(amdgpu_gfx90a::v227, output_vec_len ); + case 484: return makeRegisterExpression(amdgpu_gfx90a::v228, output_vec_len ); + case 485: return makeRegisterExpression(amdgpu_gfx90a::v229, output_vec_len ); + case 486: return makeRegisterExpression(amdgpu_gfx90a::v230, output_vec_len ); + case 487: return makeRegisterExpression(amdgpu_gfx90a::v231, output_vec_len ); + case 488: return makeRegisterExpression(amdgpu_gfx90a::v232, output_vec_len ); + case 489: return makeRegisterExpression(amdgpu_gfx90a::v233, output_vec_len ); + case 490: return makeRegisterExpression(amdgpu_gfx90a::v234, output_vec_len ); + case 491: return makeRegisterExpression(amdgpu_gfx90a::v235, output_vec_len ); + case 492: return makeRegisterExpression(amdgpu_gfx90a::v236, output_vec_len ); + case 493: return makeRegisterExpression(amdgpu_gfx90a::v237, output_vec_len ); + case 494: return makeRegisterExpression(amdgpu_gfx90a::v238, output_vec_len ); + case 495: return makeRegisterExpression(amdgpu_gfx90a::v239, output_vec_len ); + case 496: return makeRegisterExpression(amdgpu_gfx90a::v240, output_vec_len ); + case 497: return makeRegisterExpression(amdgpu_gfx90a::v241, output_vec_len ); + case 498: return makeRegisterExpression(amdgpu_gfx90a::v242, output_vec_len ); + case 499: return makeRegisterExpression(amdgpu_gfx90a::v243, output_vec_len ); + case 500: return makeRegisterExpression(amdgpu_gfx90a::v244, output_vec_len ); + case 501: return makeRegisterExpression(amdgpu_gfx90a::v245, output_vec_len ); + case 502: return makeRegisterExpression(amdgpu_gfx90a::v246, output_vec_len ); + case 503: return makeRegisterExpression(amdgpu_gfx90a::v247, output_vec_len ); + case 504: return makeRegisterExpression(amdgpu_gfx90a::v248, output_vec_len ); + case 505: return makeRegisterExpression(amdgpu_gfx90a::v249, output_vec_len ); + case 506: return makeRegisterExpression(amdgpu_gfx90a::v250, output_vec_len ); + case 507: return makeRegisterExpression(amdgpu_gfx90a::v251, output_vec_len ); + case 508: return makeRegisterExpression(amdgpu_gfx90a::v252, output_vec_len ); + case 509: return makeRegisterExpression(amdgpu_gfx90a::v253, output_vec_len ); + case 510: return makeRegisterExpression(amdgpu_gfx90a::v254, output_vec_len ); + case 511: return makeRegisterExpression(amdgpu_gfx90a::v255, output_vec_len ); + case 768: return makeRegisterExpression(amdgpu_gfx90a::acc0, output_vec_len ); + case 769: return makeRegisterExpression(amdgpu_gfx90a::acc1, output_vec_len ); + case 770: return makeRegisterExpression(amdgpu_gfx90a::acc2, output_vec_len ); + case 771: return makeRegisterExpression(amdgpu_gfx90a::acc3, output_vec_len ); + case 772: return makeRegisterExpression(amdgpu_gfx90a::acc4, output_vec_len ); + case 773: return makeRegisterExpression(amdgpu_gfx90a::acc5, output_vec_len ); + case 774: return makeRegisterExpression(amdgpu_gfx90a::acc6, output_vec_len ); + case 775: return makeRegisterExpression(amdgpu_gfx90a::acc7, output_vec_len ); + case 776: return makeRegisterExpression(amdgpu_gfx90a::acc8, output_vec_len ); + case 777: return makeRegisterExpression(amdgpu_gfx90a::acc9, output_vec_len ); + case 778: return makeRegisterExpression(amdgpu_gfx90a::acc10, output_vec_len ); + case 779: return makeRegisterExpression(amdgpu_gfx90a::acc11, output_vec_len ); + case 780: return makeRegisterExpression(amdgpu_gfx90a::acc12, output_vec_len ); + case 781: return makeRegisterExpression(amdgpu_gfx90a::acc13, output_vec_len ); + case 782: return makeRegisterExpression(amdgpu_gfx90a::acc14, output_vec_len ); + case 783: return makeRegisterExpression(amdgpu_gfx90a::acc15, output_vec_len ); + case 784: return makeRegisterExpression(amdgpu_gfx90a::acc16, output_vec_len ); + case 785: return makeRegisterExpression(amdgpu_gfx90a::acc17, output_vec_len ); + case 786: return makeRegisterExpression(amdgpu_gfx90a::acc18, output_vec_len ); + case 787: return makeRegisterExpression(amdgpu_gfx90a::acc19, output_vec_len ); + case 788: return makeRegisterExpression(amdgpu_gfx90a::acc20, output_vec_len ); + case 789: return makeRegisterExpression(amdgpu_gfx90a::acc21, output_vec_len ); + case 790: return makeRegisterExpression(amdgpu_gfx90a::acc22, output_vec_len ); + case 791: return makeRegisterExpression(amdgpu_gfx90a::acc23, output_vec_len ); + case 792: return makeRegisterExpression(amdgpu_gfx90a::acc24, output_vec_len ); + case 793: return makeRegisterExpression(amdgpu_gfx90a::acc25, output_vec_len ); + case 794: return makeRegisterExpression(amdgpu_gfx90a::acc26, output_vec_len ); + case 795: return makeRegisterExpression(amdgpu_gfx90a::acc27, output_vec_len ); + case 796: return makeRegisterExpression(amdgpu_gfx90a::acc28, output_vec_len ); + case 797: return makeRegisterExpression(amdgpu_gfx90a::acc29, output_vec_len ); + case 798: return makeRegisterExpression(amdgpu_gfx90a::acc30, output_vec_len ); + case 799: return makeRegisterExpression(amdgpu_gfx90a::acc31, output_vec_len ); + case 800: return makeRegisterExpression(amdgpu_gfx90a::acc32, output_vec_len ); + case 801: return makeRegisterExpression(amdgpu_gfx90a::acc33, output_vec_len ); + case 802: return makeRegisterExpression(amdgpu_gfx90a::acc34, output_vec_len ); + case 803: return makeRegisterExpression(amdgpu_gfx90a::acc35, output_vec_len ); + case 804: return makeRegisterExpression(amdgpu_gfx90a::acc36, output_vec_len ); + case 805: return makeRegisterExpression(amdgpu_gfx90a::acc37, output_vec_len ); + case 806: return makeRegisterExpression(amdgpu_gfx90a::acc38, output_vec_len ); + case 807: return makeRegisterExpression(amdgpu_gfx90a::acc39, output_vec_len ); + case 808: return makeRegisterExpression(amdgpu_gfx90a::acc40, output_vec_len ); + case 809: return makeRegisterExpression(amdgpu_gfx90a::acc41, output_vec_len ); + case 810: return makeRegisterExpression(amdgpu_gfx90a::acc42, output_vec_len ); + case 811: return makeRegisterExpression(amdgpu_gfx90a::acc43, output_vec_len ); + case 812: return makeRegisterExpression(amdgpu_gfx90a::acc44, output_vec_len ); + case 813: return makeRegisterExpression(amdgpu_gfx90a::acc45, output_vec_len ); + case 814: return makeRegisterExpression(amdgpu_gfx90a::acc46, output_vec_len ); + case 815: return makeRegisterExpression(amdgpu_gfx90a::acc47, output_vec_len ); + case 816: return makeRegisterExpression(amdgpu_gfx90a::acc48, output_vec_len ); + case 817: return makeRegisterExpression(amdgpu_gfx90a::acc49, output_vec_len ); + case 818: return makeRegisterExpression(amdgpu_gfx90a::acc50, output_vec_len ); + case 819: return makeRegisterExpression(amdgpu_gfx90a::acc51, output_vec_len ); + case 820: return makeRegisterExpression(amdgpu_gfx90a::acc52, output_vec_len ); + case 821: return makeRegisterExpression(amdgpu_gfx90a::acc53, output_vec_len ); + case 822: return makeRegisterExpression(amdgpu_gfx90a::acc54, output_vec_len ); + case 823: return makeRegisterExpression(amdgpu_gfx90a::acc55, output_vec_len ); + case 824: return makeRegisterExpression(amdgpu_gfx90a::acc56, output_vec_len ); + case 825: return makeRegisterExpression(amdgpu_gfx90a::acc57, output_vec_len ); + case 826: return makeRegisterExpression(amdgpu_gfx90a::acc58, output_vec_len ); + case 827: return makeRegisterExpression(amdgpu_gfx90a::acc59, output_vec_len ); + case 828: return makeRegisterExpression(amdgpu_gfx90a::acc60, output_vec_len ); + case 829: return makeRegisterExpression(amdgpu_gfx90a::acc61, output_vec_len ); + case 830: return makeRegisterExpression(amdgpu_gfx90a::acc62, output_vec_len ); + case 831: return makeRegisterExpression(amdgpu_gfx90a::acc63, output_vec_len ); + case 832: return makeRegisterExpression(amdgpu_gfx90a::acc64, output_vec_len ); + case 833: return makeRegisterExpression(amdgpu_gfx90a::acc65, output_vec_len ); + case 834: return makeRegisterExpression(amdgpu_gfx90a::acc66, output_vec_len ); + case 835: return makeRegisterExpression(amdgpu_gfx90a::acc67, output_vec_len ); + case 836: return makeRegisterExpression(amdgpu_gfx90a::acc68, output_vec_len ); + case 837: return makeRegisterExpression(amdgpu_gfx90a::acc69, output_vec_len ); + case 838: return makeRegisterExpression(amdgpu_gfx90a::acc70, output_vec_len ); + case 839: return makeRegisterExpression(amdgpu_gfx90a::acc71, output_vec_len ); + case 840: return makeRegisterExpression(amdgpu_gfx90a::acc72, output_vec_len ); + case 841: return makeRegisterExpression(amdgpu_gfx90a::acc73, output_vec_len ); + case 842: return makeRegisterExpression(amdgpu_gfx90a::acc74, output_vec_len ); + case 843: return makeRegisterExpression(amdgpu_gfx90a::acc75, output_vec_len ); + case 844: return makeRegisterExpression(amdgpu_gfx90a::acc76, output_vec_len ); + case 845: return makeRegisterExpression(amdgpu_gfx90a::acc77, output_vec_len ); + case 846: return makeRegisterExpression(amdgpu_gfx90a::acc78, output_vec_len ); + case 847: return makeRegisterExpression(amdgpu_gfx90a::acc79, output_vec_len ); + case 848: return makeRegisterExpression(amdgpu_gfx90a::acc80, output_vec_len ); + case 849: return makeRegisterExpression(amdgpu_gfx90a::acc81, output_vec_len ); + case 850: return makeRegisterExpression(amdgpu_gfx90a::acc82, output_vec_len ); + case 851: return makeRegisterExpression(amdgpu_gfx90a::acc83, output_vec_len ); + case 852: return makeRegisterExpression(amdgpu_gfx90a::acc84, output_vec_len ); + case 853: return makeRegisterExpression(amdgpu_gfx90a::acc85, output_vec_len ); + case 854: return makeRegisterExpression(amdgpu_gfx90a::acc86, output_vec_len ); + case 855: return makeRegisterExpression(amdgpu_gfx90a::acc87, output_vec_len ); + case 856: return makeRegisterExpression(amdgpu_gfx90a::acc88, output_vec_len ); + case 857: return makeRegisterExpression(amdgpu_gfx90a::acc89, output_vec_len ); + case 858: return makeRegisterExpression(amdgpu_gfx90a::acc90, output_vec_len ); + case 859: return makeRegisterExpression(amdgpu_gfx90a::acc91, output_vec_len ); + case 860: return makeRegisterExpression(amdgpu_gfx90a::acc92, output_vec_len ); + case 861: return makeRegisterExpression(amdgpu_gfx90a::acc93, output_vec_len ); + case 862: return makeRegisterExpression(amdgpu_gfx90a::acc94, output_vec_len ); + case 863: return makeRegisterExpression(amdgpu_gfx90a::acc95, output_vec_len ); + case 864: return makeRegisterExpression(amdgpu_gfx90a::acc96, output_vec_len ); + case 865: return makeRegisterExpression(amdgpu_gfx90a::acc97, output_vec_len ); + case 866: return makeRegisterExpression(amdgpu_gfx90a::acc98, output_vec_len ); + case 867: return makeRegisterExpression(amdgpu_gfx90a::acc99, output_vec_len ); + case 868: return makeRegisterExpression(amdgpu_gfx90a::acc100, output_vec_len ); + case 869: return makeRegisterExpression(amdgpu_gfx90a::acc101, output_vec_len ); + case 870: return makeRegisterExpression(amdgpu_gfx90a::acc102, output_vec_len ); + case 871: return makeRegisterExpression(amdgpu_gfx90a::acc103, output_vec_len ); + case 872: return makeRegisterExpression(amdgpu_gfx90a::acc104, output_vec_len ); + case 873: return makeRegisterExpression(amdgpu_gfx90a::acc105, output_vec_len ); + case 874: return makeRegisterExpression(amdgpu_gfx90a::acc106, output_vec_len ); + case 875: return makeRegisterExpression(amdgpu_gfx90a::acc107, output_vec_len ); + case 876: return makeRegisterExpression(amdgpu_gfx90a::acc108, output_vec_len ); + case 877: return makeRegisterExpression(amdgpu_gfx90a::acc109, output_vec_len ); + case 878: return makeRegisterExpression(amdgpu_gfx90a::acc110, output_vec_len ); + case 879: return makeRegisterExpression(amdgpu_gfx90a::acc111, output_vec_len ); + case 880: return makeRegisterExpression(amdgpu_gfx90a::acc112, output_vec_len ); + case 881: return makeRegisterExpression(amdgpu_gfx90a::acc113, output_vec_len ); + case 882: return makeRegisterExpression(amdgpu_gfx90a::acc114, output_vec_len ); + case 883: return makeRegisterExpression(amdgpu_gfx90a::acc115, output_vec_len ); + case 884: return makeRegisterExpression(amdgpu_gfx90a::acc116, output_vec_len ); + case 885: return makeRegisterExpression(amdgpu_gfx90a::acc117, output_vec_len ); + case 886: return makeRegisterExpression(amdgpu_gfx90a::acc118, output_vec_len ); + case 887: return makeRegisterExpression(amdgpu_gfx90a::acc119, output_vec_len ); + case 888: return makeRegisterExpression(amdgpu_gfx90a::acc120, output_vec_len ); + case 889: return makeRegisterExpression(amdgpu_gfx90a::acc121, output_vec_len ); + case 890: return makeRegisterExpression(amdgpu_gfx90a::acc122, output_vec_len ); + case 891: return makeRegisterExpression(amdgpu_gfx90a::acc123, output_vec_len ); + case 892: return makeRegisterExpression(amdgpu_gfx90a::acc124, output_vec_len ); + case 893: return makeRegisterExpression(amdgpu_gfx90a::acc125, output_vec_len ); + case 894: return makeRegisterExpression(amdgpu_gfx90a::acc126, output_vec_len ); + case 895: return makeRegisterExpression(amdgpu_gfx90a::acc127, output_vec_len ); + case 896: return makeRegisterExpression(amdgpu_gfx90a::acc128, output_vec_len ); + case 897: return makeRegisterExpression(amdgpu_gfx90a::acc129, output_vec_len ); + case 898: return makeRegisterExpression(amdgpu_gfx90a::acc130, output_vec_len ); + case 899: return makeRegisterExpression(amdgpu_gfx90a::acc131, output_vec_len ); + case 900: return makeRegisterExpression(amdgpu_gfx90a::acc132, output_vec_len ); + case 901: return makeRegisterExpression(amdgpu_gfx90a::acc133, output_vec_len ); + case 902: return makeRegisterExpression(amdgpu_gfx90a::acc134, output_vec_len ); + case 903: return makeRegisterExpression(amdgpu_gfx90a::acc135, output_vec_len ); + case 904: return makeRegisterExpression(amdgpu_gfx90a::acc136, output_vec_len ); + case 905: return makeRegisterExpression(amdgpu_gfx90a::acc137, output_vec_len ); + case 906: return makeRegisterExpression(amdgpu_gfx90a::acc138, output_vec_len ); + case 907: return makeRegisterExpression(amdgpu_gfx90a::acc139, output_vec_len ); + case 908: return makeRegisterExpression(amdgpu_gfx90a::acc140, output_vec_len ); + case 909: return makeRegisterExpression(amdgpu_gfx90a::acc141, output_vec_len ); + case 910: return makeRegisterExpression(amdgpu_gfx90a::acc142, output_vec_len ); + case 911: return makeRegisterExpression(amdgpu_gfx90a::acc143, output_vec_len ); + case 912: return makeRegisterExpression(amdgpu_gfx90a::acc144, output_vec_len ); + case 913: return makeRegisterExpression(amdgpu_gfx90a::acc145, output_vec_len ); + case 914: return makeRegisterExpression(amdgpu_gfx90a::acc146, output_vec_len ); + case 915: return makeRegisterExpression(amdgpu_gfx90a::acc147, output_vec_len ); + case 916: return makeRegisterExpression(amdgpu_gfx90a::acc148, output_vec_len ); + case 917: return makeRegisterExpression(amdgpu_gfx90a::acc149, output_vec_len ); + case 918: return makeRegisterExpression(amdgpu_gfx90a::acc150, output_vec_len ); + case 919: return makeRegisterExpression(amdgpu_gfx90a::acc151, output_vec_len ); + case 920: return makeRegisterExpression(amdgpu_gfx90a::acc152, output_vec_len ); + case 921: return makeRegisterExpression(amdgpu_gfx90a::acc153, output_vec_len ); + case 922: return makeRegisterExpression(amdgpu_gfx90a::acc154, output_vec_len ); + case 923: return makeRegisterExpression(amdgpu_gfx90a::acc155, output_vec_len ); + case 924: return makeRegisterExpression(amdgpu_gfx90a::acc156, output_vec_len ); + case 925: return makeRegisterExpression(amdgpu_gfx90a::acc157, output_vec_len ); + case 926: return makeRegisterExpression(amdgpu_gfx90a::acc158, output_vec_len ); + case 927: return makeRegisterExpression(amdgpu_gfx90a::acc159, output_vec_len ); + case 928: return makeRegisterExpression(amdgpu_gfx90a::acc160, output_vec_len ); + case 929: return makeRegisterExpression(amdgpu_gfx90a::acc161, output_vec_len ); + case 930: return makeRegisterExpression(amdgpu_gfx90a::acc162, output_vec_len ); + case 931: return makeRegisterExpression(amdgpu_gfx90a::acc163, output_vec_len ); + case 932: return makeRegisterExpression(amdgpu_gfx90a::acc164, output_vec_len ); + case 933: return makeRegisterExpression(amdgpu_gfx90a::acc165, output_vec_len ); + case 934: return makeRegisterExpression(amdgpu_gfx90a::acc166, output_vec_len ); + case 935: return makeRegisterExpression(amdgpu_gfx90a::acc167, output_vec_len ); + case 936: return makeRegisterExpression(amdgpu_gfx90a::acc168, output_vec_len ); + case 937: return makeRegisterExpression(amdgpu_gfx90a::acc169, output_vec_len ); + case 938: return makeRegisterExpression(amdgpu_gfx90a::acc170, output_vec_len ); + case 939: return makeRegisterExpression(amdgpu_gfx90a::acc171, output_vec_len ); + case 940: return makeRegisterExpression(amdgpu_gfx90a::acc172, output_vec_len ); + case 941: return makeRegisterExpression(amdgpu_gfx90a::acc173, output_vec_len ); + case 942: return makeRegisterExpression(amdgpu_gfx90a::acc174, output_vec_len ); + case 943: return makeRegisterExpression(amdgpu_gfx90a::acc175, output_vec_len ); + case 944: return makeRegisterExpression(amdgpu_gfx90a::acc176, output_vec_len ); + case 945: return makeRegisterExpression(amdgpu_gfx90a::acc177, output_vec_len ); + case 946: return makeRegisterExpression(amdgpu_gfx90a::acc178, output_vec_len ); + case 947: return makeRegisterExpression(amdgpu_gfx90a::acc179, output_vec_len ); + case 948: return makeRegisterExpression(amdgpu_gfx90a::acc180, output_vec_len ); + case 949: return makeRegisterExpression(amdgpu_gfx90a::acc181, output_vec_len ); + case 950: return makeRegisterExpression(amdgpu_gfx90a::acc182, output_vec_len ); + case 951: return makeRegisterExpression(amdgpu_gfx90a::acc183, output_vec_len ); + case 952: return makeRegisterExpression(amdgpu_gfx90a::acc184, output_vec_len ); + case 953: return makeRegisterExpression(amdgpu_gfx90a::acc185, output_vec_len ); + case 954: return makeRegisterExpression(amdgpu_gfx90a::acc186, output_vec_len ); + case 955: return makeRegisterExpression(amdgpu_gfx90a::acc187, output_vec_len ); + case 956: return makeRegisterExpression(amdgpu_gfx90a::acc188, output_vec_len ); + case 957: return makeRegisterExpression(amdgpu_gfx90a::acc189, output_vec_len ); + case 958: return makeRegisterExpression(amdgpu_gfx90a::acc190, output_vec_len ); + case 959: return makeRegisterExpression(amdgpu_gfx90a::acc191, output_vec_len ); + case 960: return makeRegisterExpression(amdgpu_gfx90a::acc192, output_vec_len ); + case 961: return makeRegisterExpression(amdgpu_gfx90a::acc193, output_vec_len ); + case 962: return makeRegisterExpression(amdgpu_gfx90a::acc194, output_vec_len ); + case 963: return makeRegisterExpression(amdgpu_gfx90a::acc195, output_vec_len ); + case 964: return makeRegisterExpression(amdgpu_gfx90a::acc196, output_vec_len ); + case 965: return makeRegisterExpression(amdgpu_gfx90a::acc197, output_vec_len ); + case 966: return makeRegisterExpression(amdgpu_gfx90a::acc198, output_vec_len ); + case 967: return makeRegisterExpression(amdgpu_gfx90a::acc199, output_vec_len ); + case 968: return makeRegisterExpression(amdgpu_gfx90a::acc200, output_vec_len ); + case 969: return makeRegisterExpression(amdgpu_gfx90a::acc201, output_vec_len ); + case 970: return makeRegisterExpression(amdgpu_gfx90a::acc202, output_vec_len ); + case 971: return makeRegisterExpression(amdgpu_gfx90a::acc203, output_vec_len ); + case 972: return makeRegisterExpression(amdgpu_gfx90a::acc204, output_vec_len ); + case 973: return makeRegisterExpression(amdgpu_gfx90a::acc205, output_vec_len ); + case 974: return makeRegisterExpression(amdgpu_gfx90a::acc206, output_vec_len ); + case 975: return makeRegisterExpression(amdgpu_gfx90a::acc207, output_vec_len ); + case 976: return makeRegisterExpression(amdgpu_gfx90a::acc208, output_vec_len ); + case 977: return makeRegisterExpression(amdgpu_gfx90a::acc209, output_vec_len ); + case 978: return makeRegisterExpression(amdgpu_gfx90a::acc210, output_vec_len ); + case 979: return makeRegisterExpression(amdgpu_gfx90a::acc211, output_vec_len ); + case 980: return makeRegisterExpression(amdgpu_gfx90a::acc212, output_vec_len ); + case 981: return makeRegisterExpression(amdgpu_gfx90a::acc213, output_vec_len ); + case 982: return makeRegisterExpression(amdgpu_gfx90a::acc214, output_vec_len ); + case 983: return makeRegisterExpression(amdgpu_gfx90a::acc215, output_vec_len ); + case 984: return makeRegisterExpression(amdgpu_gfx90a::acc216, output_vec_len ); + case 985: return makeRegisterExpression(amdgpu_gfx90a::acc217, output_vec_len ); + case 986: return makeRegisterExpression(amdgpu_gfx90a::acc218, output_vec_len ); + case 987: return makeRegisterExpression(amdgpu_gfx90a::acc219, output_vec_len ); + case 988: return makeRegisterExpression(amdgpu_gfx90a::acc220, output_vec_len ); + case 989: return makeRegisterExpression(amdgpu_gfx90a::acc221, output_vec_len ); + case 990: return makeRegisterExpression(amdgpu_gfx90a::acc222, output_vec_len ); + case 991: return makeRegisterExpression(amdgpu_gfx90a::acc223, output_vec_len ); + case 992: return makeRegisterExpression(amdgpu_gfx90a::acc224, output_vec_len ); + case 993: return makeRegisterExpression(amdgpu_gfx90a::acc225, output_vec_len ); + case 994: return makeRegisterExpression(amdgpu_gfx90a::acc226, output_vec_len ); + case 995: return makeRegisterExpression(amdgpu_gfx90a::acc227, output_vec_len ); + case 996: return makeRegisterExpression(amdgpu_gfx90a::acc228, output_vec_len ); + case 997: return makeRegisterExpression(amdgpu_gfx90a::acc229, output_vec_len ); + case 998: return makeRegisterExpression(amdgpu_gfx90a::acc230, output_vec_len ); + case 999: return makeRegisterExpression(amdgpu_gfx90a::acc231, output_vec_len ); + case 1000: return makeRegisterExpression(amdgpu_gfx90a::acc232, output_vec_len ); + case 1001: return makeRegisterExpression(amdgpu_gfx90a::acc233, output_vec_len ); + case 1002: return makeRegisterExpression(amdgpu_gfx90a::acc234, output_vec_len ); + case 1003: return makeRegisterExpression(amdgpu_gfx90a::acc235, output_vec_len ); + case 1004: return makeRegisterExpression(amdgpu_gfx90a::acc236, output_vec_len ); + case 1005: return makeRegisterExpression(amdgpu_gfx90a::acc237, output_vec_len ); + case 1006: return makeRegisterExpression(amdgpu_gfx90a::acc238, output_vec_len ); + case 1007: return makeRegisterExpression(amdgpu_gfx90a::acc239, output_vec_len ); + case 1008: return makeRegisterExpression(amdgpu_gfx90a::acc240, output_vec_len ); + case 1009: return makeRegisterExpression(amdgpu_gfx90a::acc241, output_vec_len ); + case 1010: return makeRegisterExpression(amdgpu_gfx90a::acc242, output_vec_len ); + case 1011: return makeRegisterExpression(amdgpu_gfx90a::acc243, output_vec_len ); + case 1012: return makeRegisterExpression(amdgpu_gfx90a::acc244, output_vec_len ); + case 1013: return makeRegisterExpression(amdgpu_gfx90a::acc245, output_vec_len ); + case 1014: return makeRegisterExpression(amdgpu_gfx90a::acc246, output_vec_len ); + case 1015: return makeRegisterExpression(amdgpu_gfx90a::acc247, output_vec_len ); + case 1016: return makeRegisterExpression(amdgpu_gfx90a::acc248, output_vec_len ); + case 1017: return makeRegisterExpression(amdgpu_gfx90a::acc249, output_vec_len ); + case 1018: return makeRegisterExpression(amdgpu_gfx90a::acc250, output_vec_len ); + case 1019: return makeRegisterExpression(amdgpu_gfx90a::acc251, output_vec_len ); + case 1020: return makeRegisterExpression(amdgpu_gfx90a::acc252, output_vec_len ); + case 1021: return makeRegisterExpression(amdgpu_gfx90a::acc253, output_vec_len ); + case 1022: return makeRegisterExpression(amdgpu_gfx90a::acc254, output_vec_len ); + case 1023: return makeRegisterExpression(amdgpu_gfx90a::acc255, output_vec_len ); + default: return makeRegisterExpression(amdgpu_gfx90a::invalid); + } + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx90a::decodeOPR_SRC_VGPR_OR_ACCVGPR_OR_CONST(uint64_t input, uint32_t output_vec_len) + { + switch (input) { + case 256: return makeRegisterExpression(amdgpu_gfx90a::v0, output_vec_len ); + case 257: return makeRegisterExpression(amdgpu_gfx90a::v1, output_vec_len ); + case 258: return makeRegisterExpression(amdgpu_gfx90a::v2, output_vec_len ); + case 259: return makeRegisterExpression(amdgpu_gfx90a::v3, output_vec_len ); + case 260: return makeRegisterExpression(amdgpu_gfx90a::v4, output_vec_len ); + case 261: return makeRegisterExpression(amdgpu_gfx90a::v5, output_vec_len ); + case 262: return makeRegisterExpression(amdgpu_gfx90a::v6, output_vec_len ); + case 263: return makeRegisterExpression(amdgpu_gfx90a::v7, output_vec_len ); + case 264: return makeRegisterExpression(amdgpu_gfx90a::v8, output_vec_len ); + case 265: return makeRegisterExpression(amdgpu_gfx90a::v9, output_vec_len ); + case 266: return makeRegisterExpression(amdgpu_gfx90a::v10, output_vec_len ); + case 267: return makeRegisterExpression(amdgpu_gfx90a::v11, output_vec_len ); + case 268: return makeRegisterExpression(amdgpu_gfx90a::v12, output_vec_len ); + case 269: return makeRegisterExpression(amdgpu_gfx90a::v13, output_vec_len ); + case 270: return makeRegisterExpression(amdgpu_gfx90a::v14, output_vec_len ); + case 271: return makeRegisterExpression(amdgpu_gfx90a::v15, output_vec_len ); + case 272: return makeRegisterExpression(amdgpu_gfx90a::v16, output_vec_len ); + case 273: return makeRegisterExpression(amdgpu_gfx90a::v17, output_vec_len ); + case 274: return makeRegisterExpression(amdgpu_gfx90a::v18, output_vec_len ); + case 275: return makeRegisterExpression(amdgpu_gfx90a::v19, output_vec_len ); + case 276: return makeRegisterExpression(amdgpu_gfx90a::v20, output_vec_len ); + case 277: return makeRegisterExpression(amdgpu_gfx90a::v21, output_vec_len ); + case 278: return makeRegisterExpression(amdgpu_gfx90a::v22, output_vec_len ); + case 279: return makeRegisterExpression(amdgpu_gfx90a::v23, output_vec_len ); + case 280: return makeRegisterExpression(amdgpu_gfx90a::v24, output_vec_len ); + case 281: return makeRegisterExpression(amdgpu_gfx90a::v25, output_vec_len ); + case 282: return makeRegisterExpression(amdgpu_gfx90a::v26, output_vec_len ); + case 283: return makeRegisterExpression(amdgpu_gfx90a::v27, output_vec_len ); + case 284: return makeRegisterExpression(amdgpu_gfx90a::v28, output_vec_len ); + case 285: return makeRegisterExpression(amdgpu_gfx90a::v29, output_vec_len ); + case 286: return makeRegisterExpression(amdgpu_gfx90a::v30, output_vec_len ); + case 287: return makeRegisterExpression(amdgpu_gfx90a::v31, output_vec_len ); + case 288: return makeRegisterExpression(amdgpu_gfx90a::v32, output_vec_len ); + case 289: return makeRegisterExpression(amdgpu_gfx90a::v33, output_vec_len ); + case 290: return makeRegisterExpression(amdgpu_gfx90a::v34, output_vec_len ); + case 291: return makeRegisterExpression(amdgpu_gfx90a::v35, output_vec_len ); + case 292: return makeRegisterExpression(amdgpu_gfx90a::v36, output_vec_len ); + case 293: return makeRegisterExpression(amdgpu_gfx90a::v37, output_vec_len ); + case 294: return makeRegisterExpression(amdgpu_gfx90a::v38, output_vec_len ); + case 295: return makeRegisterExpression(amdgpu_gfx90a::v39, output_vec_len ); + case 296: return makeRegisterExpression(amdgpu_gfx90a::v40, output_vec_len ); + case 297: return makeRegisterExpression(amdgpu_gfx90a::v41, output_vec_len ); + case 298: return makeRegisterExpression(amdgpu_gfx90a::v42, output_vec_len ); + case 299: return makeRegisterExpression(amdgpu_gfx90a::v43, output_vec_len ); + case 300: return makeRegisterExpression(amdgpu_gfx90a::v44, output_vec_len ); + case 301: return makeRegisterExpression(amdgpu_gfx90a::v45, output_vec_len ); + case 302: return makeRegisterExpression(amdgpu_gfx90a::v46, output_vec_len ); + case 303: return makeRegisterExpression(amdgpu_gfx90a::v47, output_vec_len ); + case 304: return makeRegisterExpression(amdgpu_gfx90a::v48, output_vec_len ); + case 305: return makeRegisterExpression(amdgpu_gfx90a::v49, output_vec_len ); + case 306: return makeRegisterExpression(amdgpu_gfx90a::v50, output_vec_len ); + case 307: return makeRegisterExpression(amdgpu_gfx90a::v51, output_vec_len ); + case 308: return makeRegisterExpression(amdgpu_gfx90a::v52, output_vec_len ); + case 309: return makeRegisterExpression(amdgpu_gfx90a::v53, output_vec_len ); + case 310: return makeRegisterExpression(amdgpu_gfx90a::v54, output_vec_len ); + case 311: return makeRegisterExpression(amdgpu_gfx90a::v55, output_vec_len ); + case 312: return makeRegisterExpression(amdgpu_gfx90a::v56, output_vec_len ); + case 313: return makeRegisterExpression(amdgpu_gfx90a::v57, output_vec_len ); + case 314: return makeRegisterExpression(amdgpu_gfx90a::v58, output_vec_len ); + case 315: return makeRegisterExpression(amdgpu_gfx90a::v59, output_vec_len ); + case 316: return makeRegisterExpression(amdgpu_gfx90a::v60, output_vec_len ); + case 317: return makeRegisterExpression(amdgpu_gfx90a::v61, output_vec_len ); + case 318: return makeRegisterExpression(amdgpu_gfx90a::v62, output_vec_len ); + case 319: return makeRegisterExpression(amdgpu_gfx90a::v63, output_vec_len ); + case 320: return makeRegisterExpression(amdgpu_gfx90a::v64, output_vec_len ); + case 321: return makeRegisterExpression(amdgpu_gfx90a::v65, output_vec_len ); + case 322: return makeRegisterExpression(amdgpu_gfx90a::v66, output_vec_len ); + case 323: return makeRegisterExpression(amdgpu_gfx90a::v67, output_vec_len ); + case 324: return makeRegisterExpression(amdgpu_gfx90a::v68, output_vec_len ); + case 325: return makeRegisterExpression(amdgpu_gfx90a::v69, output_vec_len ); + case 326: return makeRegisterExpression(amdgpu_gfx90a::v70, output_vec_len ); + case 327: return makeRegisterExpression(amdgpu_gfx90a::v71, output_vec_len ); + case 328: return makeRegisterExpression(amdgpu_gfx90a::v72, output_vec_len ); + case 329: return makeRegisterExpression(amdgpu_gfx90a::v73, output_vec_len ); + case 330: return makeRegisterExpression(amdgpu_gfx90a::v74, output_vec_len ); + case 331: return makeRegisterExpression(amdgpu_gfx90a::v75, output_vec_len ); + case 332: return makeRegisterExpression(amdgpu_gfx90a::v76, output_vec_len ); + case 333: return makeRegisterExpression(amdgpu_gfx90a::v77, output_vec_len ); + case 334: return makeRegisterExpression(amdgpu_gfx90a::v78, output_vec_len ); + case 335: return makeRegisterExpression(amdgpu_gfx90a::v79, output_vec_len ); + case 336: return makeRegisterExpression(amdgpu_gfx90a::v80, output_vec_len ); + case 337: return makeRegisterExpression(amdgpu_gfx90a::v81, output_vec_len ); + case 338: return makeRegisterExpression(amdgpu_gfx90a::v82, output_vec_len ); + case 339: return makeRegisterExpression(amdgpu_gfx90a::v83, output_vec_len ); + case 340: return makeRegisterExpression(amdgpu_gfx90a::v84, output_vec_len ); + case 341: return makeRegisterExpression(amdgpu_gfx90a::v85, output_vec_len ); + case 342: return makeRegisterExpression(amdgpu_gfx90a::v86, output_vec_len ); + case 343: return makeRegisterExpression(amdgpu_gfx90a::v87, output_vec_len ); + case 344: return makeRegisterExpression(amdgpu_gfx90a::v88, output_vec_len ); + case 345: return makeRegisterExpression(amdgpu_gfx90a::v89, output_vec_len ); + case 346: return makeRegisterExpression(amdgpu_gfx90a::v90, output_vec_len ); + case 347: return makeRegisterExpression(amdgpu_gfx90a::v91, output_vec_len ); + case 348: return makeRegisterExpression(amdgpu_gfx90a::v92, output_vec_len ); + case 349: return makeRegisterExpression(amdgpu_gfx90a::v93, output_vec_len ); + case 350: return makeRegisterExpression(amdgpu_gfx90a::v94, output_vec_len ); + case 351: return makeRegisterExpression(amdgpu_gfx90a::v95, output_vec_len ); + case 352: return makeRegisterExpression(amdgpu_gfx90a::v96, output_vec_len ); + case 353: return makeRegisterExpression(amdgpu_gfx90a::v97, output_vec_len ); + case 354: return makeRegisterExpression(amdgpu_gfx90a::v98, output_vec_len ); + case 355: return makeRegisterExpression(amdgpu_gfx90a::v99, output_vec_len ); + case 356: return makeRegisterExpression(amdgpu_gfx90a::v100, output_vec_len ); + case 357: return makeRegisterExpression(amdgpu_gfx90a::v101, output_vec_len ); + case 358: return makeRegisterExpression(amdgpu_gfx90a::v102, output_vec_len ); + case 359: return makeRegisterExpression(amdgpu_gfx90a::v103, output_vec_len ); + case 360: return makeRegisterExpression(amdgpu_gfx90a::v104, output_vec_len ); + case 361: return makeRegisterExpression(amdgpu_gfx90a::v105, output_vec_len ); + case 362: return makeRegisterExpression(amdgpu_gfx90a::v106, output_vec_len ); + case 363: return makeRegisterExpression(amdgpu_gfx90a::v107, output_vec_len ); + case 364: return makeRegisterExpression(amdgpu_gfx90a::v108, output_vec_len ); + case 365: return makeRegisterExpression(amdgpu_gfx90a::v109, output_vec_len ); + case 366: return makeRegisterExpression(amdgpu_gfx90a::v110, output_vec_len ); + case 367: return makeRegisterExpression(amdgpu_gfx90a::v111, output_vec_len ); + case 368: return makeRegisterExpression(amdgpu_gfx90a::v112, output_vec_len ); + case 369: return makeRegisterExpression(amdgpu_gfx90a::v113, output_vec_len ); + case 370: return makeRegisterExpression(amdgpu_gfx90a::v114, output_vec_len ); + case 371: return makeRegisterExpression(amdgpu_gfx90a::v115, output_vec_len ); + case 372: return makeRegisterExpression(amdgpu_gfx90a::v116, output_vec_len ); + case 373: return makeRegisterExpression(amdgpu_gfx90a::v117, output_vec_len ); + case 374: return makeRegisterExpression(amdgpu_gfx90a::v118, output_vec_len ); + case 375: return makeRegisterExpression(amdgpu_gfx90a::v119, output_vec_len ); + case 376: return makeRegisterExpression(amdgpu_gfx90a::v120, output_vec_len ); + case 377: return makeRegisterExpression(amdgpu_gfx90a::v121, output_vec_len ); + case 378: return makeRegisterExpression(amdgpu_gfx90a::v122, output_vec_len ); + case 379: return makeRegisterExpression(amdgpu_gfx90a::v123, output_vec_len ); + case 380: return makeRegisterExpression(amdgpu_gfx90a::v124, output_vec_len ); + case 381: return makeRegisterExpression(amdgpu_gfx90a::v125, output_vec_len ); + case 382: return makeRegisterExpression(amdgpu_gfx90a::v126, output_vec_len ); + case 383: return makeRegisterExpression(amdgpu_gfx90a::v127, output_vec_len ); + case 384: return makeRegisterExpression(amdgpu_gfx90a::v128, output_vec_len ); + case 385: return makeRegisterExpression(amdgpu_gfx90a::v129, output_vec_len ); + case 386: return makeRegisterExpression(amdgpu_gfx90a::v130, output_vec_len ); + case 387: return makeRegisterExpression(amdgpu_gfx90a::v131, output_vec_len ); + case 388: return makeRegisterExpression(amdgpu_gfx90a::v132, output_vec_len ); + case 389: return makeRegisterExpression(amdgpu_gfx90a::v133, output_vec_len ); + case 390: return makeRegisterExpression(amdgpu_gfx90a::v134, output_vec_len ); + case 391: return makeRegisterExpression(amdgpu_gfx90a::v135, output_vec_len ); + case 392: return makeRegisterExpression(amdgpu_gfx90a::v136, output_vec_len ); + case 393: return makeRegisterExpression(amdgpu_gfx90a::v137, output_vec_len ); + case 394: return makeRegisterExpression(amdgpu_gfx90a::v138, output_vec_len ); + case 395: return makeRegisterExpression(amdgpu_gfx90a::v139, output_vec_len ); + case 396: return makeRegisterExpression(amdgpu_gfx90a::v140, output_vec_len ); + case 397: return makeRegisterExpression(amdgpu_gfx90a::v141, output_vec_len ); + case 398: return makeRegisterExpression(amdgpu_gfx90a::v142, output_vec_len ); + case 399: return makeRegisterExpression(amdgpu_gfx90a::v143, output_vec_len ); + case 400: return makeRegisterExpression(amdgpu_gfx90a::v144, output_vec_len ); + case 401: return makeRegisterExpression(amdgpu_gfx90a::v145, output_vec_len ); + case 402: return makeRegisterExpression(amdgpu_gfx90a::v146, output_vec_len ); + case 403: return makeRegisterExpression(amdgpu_gfx90a::v147, output_vec_len ); + case 404: return makeRegisterExpression(amdgpu_gfx90a::v148, output_vec_len ); + case 405: return makeRegisterExpression(amdgpu_gfx90a::v149, output_vec_len ); + case 406: return makeRegisterExpression(amdgpu_gfx90a::v150, output_vec_len ); + case 407: return makeRegisterExpression(amdgpu_gfx90a::v151, output_vec_len ); + case 408: return makeRegisterExpression(amdgpu_gfx90a::v152, output_vec_len ); + case 409: return makeRegisterExpression(amdgpu_gfx90a::v153, output_vec_len ); + case 410: return makeRegisterExpression(amdgpu_gfx90a::v154, output_vec_len ); + case 411: return makeRegisterExpression(amdgpu_gfx90a::v155, output_vec_len ); + case 412: return makeRegisterExpression(amdgpu_gfx90a::v156, output_vec_len ); + case 413: return makeRegisterExpression(amdgpu_gfx90a::v157, output_vec_len ); + case 414: return makeRegisterExpression(amdgpu_gfx90a::v158, output_vec_len ); + case 415: return makeRegisterExpression(amdgpu_gfx90a::v159, output_vec_len ); + case 416: return makeRegisterExpression(amdgpu_gfx90a::v160, output_vec_len ); + case 417: return makeRegisterExpression(amdgpu_gfx90a::v161, output_vec_len ); + case 418: return makeRegisterExpression(amdgpu_gfx90a::v162, output_vec_len ); + case 419: return makeRegisterExpression(amdgpu_gfx90a::v163, output_vec_len ); + case 420: return makeRegisterExpression(amdgpu_gfx90a::v164, output_vec_len ); + case 421: return makeRegisterExpression(amdgpu_gfx90a::v165, output_vec_len ); + case 422: return makeRegisterExpression(amdgpu_gfx90a::v166, output_vec_len ); + case 423: return makeRegisterExpression(amdgpu_gfx90a::v167, output_vec_len ); + case 424: return makeRegisterExpression(amdgpu_gfx90a::v168, output_vec_len ); + case 425: return makeRegisterExpression(amdgpu_gfx90a::v169, output_vec_len ); + case 426: return makeRegisterExpression(amdgpu_gfx90a::v170, output_vec_len ); + case 427: return makeRegisterExpression(amdgpu_gfx90a::v171, output_vec_len ); + case 428: return makeRegisterExpression(amdgpu_gfx90a::v172, output_vec_len ); + case 429: return makeRegisterExpression(amdgpu_gfx90a::v173, output_vec_len ); + case 430: return makeRegisterExpression(amdgpu_gfx90a::v174, output_vec_len ); + case 431: return makeRegisterExpression(amdgpu_gfx90a::v175, output_vec_len ); + case 432: return makeRegisterExpression(amdgpu_gfx90a::v176, output_vec_len ); + case 433: return makeRegisterExpression(amdgpu_gfx90a::v177, output_vec_len ); + case 434: return makeRegisterExpression(amdgpu_gfx90a::v178, output_vec_len ); + case 435: return makeRegisterExpression(amdgpu_gfx90a::v179, output_vec_len ); + case 436: return makeRegisterExpression(amdgpu_gfx90a::v180, output_vec_len ); + case 437: return makeRegisterExpression(amdgpu_gfx90a::v181, output_vec_len ); + case 438: return makeRegisterExpression(amdgpu_gfx90a::v182, output_vec_len ); + case 439: return makeRegisterExpression(amdgpu_gfx90a::v183, output_vec_len ); + case 440: return makeRegisterExpression(amdgpu_gfx90a::v184, output_vec_len ); + case 441: return makeRegisterExpression(amdgpu_gfx90a::v185, output_vec_len ); + case 442: return makeRegisterExpression(amdgpu_gfx90a::v186, output_vec_len ); + case 443: return makeRegisterExpression(amdgpu_gfx90a::v187, output_vec_len ); + case 444: return makeRegisterExpression(amdgpu_gfx90a::v188, output_vec_len ); + case 445: return makeRegisterExpression(amdgpu_gfx90a::v189, output_vec_len ); + case 446: return makeRegisterExpression(amdgpu_gfx90a::v190, output_vec_len ); + case 447: return makeRegisterExpression(amdgpu_gfx90a::v191, output_vec_len ); + case 448: return makeRegisterExpression(amdgpu_gfx90a::v192, output_vec_len ); + case 449: return makeRegisterExpression(amdgpu_gfx90a::v193, output_vec_len ); + case 450: return makeRegisterExpression(amdgpu_gfx90a::v194, output_vec_len ); + case 451: return makeRegisterExpression(amdgpu_gfx90a::v195, output_vec_len ); + case 452: return makeRegisterExpression(amdgpu_gfx90a::v196, output_vec_len ); + case 453: return makeRegisterExpression(amdgpu_gfx90a::v197, output_vec_len ); + case 454: return makeRegisterExpression(amdgpu_gfx90a::v198, output_vec_len ); + case 455: return makeRegisterExpression(amdgpu_gfx90a::v199, output_vec_len ); + case 456: return makeRegisterExpression(amdgpu_gfx90a::v200, output_vec_len ); + case 457: return makeRegisterExpression(amdgpu_gfx90a::v201, output_vec_len ); + case 458: return makeRegisterExpression(amdgpu_gfx90a::v202, output_vec_len ); + case 459: return makeRegisterExpression(amdgpu_gfx90a::v203, output_vec_len ); + case 460: return makeRegisterExpression(amdgpu_gfx90a::v204, output_vec_len ); + case 461: return makeRegisterExpression(amdgpu_gfx90a::v205, output_vec_len ); + case 462: return makeRegisterExpression(amdgpu_gfx90a::v206, output_vec_len ); + case 463: return makeRegisterExpression(amdgpu_gfx90a::v207, output_vec_len ); + case 464: return makeRegisterExpression(amdgpu_gfx90a::v208, output_vec_len ); + case 465: return makeRegisterExpression(amdgpu_gfx90a::v209, output_vec_len ); + case 466: return makeRegisterExpression(amdgpu_gfx90a::v210, output_vec_len ); + case 467: return makeRegisterExpression(amdgpu_gfx90a::v211, output_vec_len ); + case 468: return makeRegisterExpression(amdgpu_gfx90a::v212, output_vec_len ); + case 469: return makeRegisterExpression(amdgpu_gfx90a::v213, output_vec_len ); + case 470: return makeRegisterExpression(amdgpu_gfx90a::v214, output_vec_len ); + case 471: return makeRegisterExpression(amdgpu_gfx90a::v215, output_vec_len ); + case 472: return makeRegisterExpression(amdgpu_gfx90a::v216, output_vec_len ); + case 473: return makeRegisterExpression(amdgpu_gfx90a::v217, output_vec_len ); + case 474: return makeRegisterExpression(amdgpu_gfx90a::v218, output_vec_len ); + case 475: return makeRegisterExpression(amdgpu_gfx90a::v219, output_vec_len ); + case 476: return makeRegisterExpression(amdgpu_gfx90a::v220, output_vec_len ); + case 477: return makeRegisterExpression(amdgpu_gfx90a::v221, output_vec_len ); + case 478: return makeRegisterExpression(amdgpu_gfx90a::v222, output_vec_len ); + case 479: return makeRegisterExpression(amdgpu_gfx90a::v223, output_vec_len ); + case 480: return makeRegisterExpression(amdgpu_gfx90a::v224, output_vec_len ); + case 481: return makeRegisterExpression(amdgpu_gfx90a::v225, output_vec_len ); + case 482: return makeRegisterExpression(amdgpu_gfx90a::v226, output_vec_len ); + case 483: return makeRegisterExpression(amdgpu_gfx90a::v227, output_vec_len ); + case 484: return makeRegisterExpression(amdgpu_gfx90a::v228, output_vec_len ); + case 485: return makeRegisterExpression(amdgpu_gfx90a::v229, output_vec_len ); + case 486: return makeRegisterExpression(amdgpu_gfx90a::v230, output_vec_len ); + case 487: return makeRegisterExpression(amdgpu_gfx90a::v231, output_vec_len ); + case 488: return makeRegisterExpression(amdgpu_gfx90a::v232, output_vec_len ); + case 489: return makeRegisterExpression(amdgpu_gfx90a::v233, output_vec_len ); + case 490: return makeRegisterExpression(amdgpu_gfx90a::v234, output_vec_len ); + case 491: return makeRegisterExpression(amdgpu_gfx90a::v235, output_vec_len ); + case 492: return makeRegisterExpression(amdgpu_gfx90a::v236, output_vec_len ); + case 493: return makeRegisterExpression(amdgpu_gfx90a::v237, output_vec_len ); + case 494: return makeRegisterExpression(amdgpu_gfx90a::v238, output_vec_len ); + case 495: return makeRegisterExpression(amdgpu_gfx90a::v239, output_vec_len ); + case 496: return makeRegisterExpression(amdgpu_gfx90a::v240, output_vec_len ); + case 497: return makeRegisterExpression(amdgpu_gfx90a::v241, output_vec_len ); + case 498: return makeRegisterExpression(amdgpu_gfx90a::v242, output_vec_len ); + case 499: return makeRegisterExpression(amdgpu_gfx90a::v243, output_vec_len ); + case 500: return makeRegisterExpression(amdgpu_gfx90a::v244, output_vec_len ); + case 501: return makeRegisterExpression(amdgpu_gfx90a::v245, output_vec_len ); + case 502: return makeRegisterExpression(amdgpu_gfx90a::v246, output_vec_len ); + case 503: return makeRegisterExpression(amdgpu_gfx90a::v247, output_vec_len ); + case 504: return makeRegisterExpression(amdgpu_gfx90a::v248, output_vec_len ); + case 505: return makeRegisterExpression(amdgpu_gfx90a::v249, output_vec_len ); + case 506: return makeRegisterExpression(amdgpu_gfx90a::v250, output_vec_len ); + case 507: return makeRegisterExpression(amdgpu_gfx90a::v251, output_vec_len ); + case 508: return makeRegisterExpression(amdgpu_gfx90a::v252, output_vec_len ); + case 509: return makeRegisterExpression(amdgpu_gfx90a::v253, output_vec_len ); + case 510: return makeRegisterExpression(amdgpu_gfx90a::v254, output_vec_len ); + case 511: return makeRegisterExpression(amdgpu_gfx90a::v255, output_vec_len ); + case 768: return makeRegisterExpression(amdgpu_gfx90a::acc0, output_vec_len ); + case 769: return makeRegisterExpression(amdgpu_gfx90a::acc1, output_vec_len ); + case 770: return makeRegisterExpression(amdgpu_gfx90a::acc2, output_vec_len ); + case 771: return makeRegisterExpression(amdgpu_gfx90a::acc3, output_vec_len ); + case 772: return makeRegisterExpression(amdgpu_gfx90a::acc4, output_vec_len ); + case 773: return makeRegisterExpression(amdgpu_gfx90a::acc5, output_vec_len ); + case 774: return makeRegisterExpression(amdgpu_gfx90a::acc6, output_vec_len ); + case 775: return makeRegisterExpression(amdgpu_gfx90a::acc7, output_vec_len ); + case 776: return makeRegisterExpression(amdgpu_gfx90a::acc8, output_vec_len ); + case 777: return makeRegisterExpression(amdgpu_gfx90a::acc9, output_vec_len ); + case 778: return makeRegisterExpression(amdgpu_gfx90a::acc10, output_vec_len ); + case 779: return makeRegisterExpression(amdgpu_gfx90a::acc11, output_vec_len ); + case 780: return makeRegisterExpression(amdgpu_gfx90a::acc12, output_vec_len ); + case 781: return makeRegisterExpression(amdgpu_gfx90a::acc13, output_vec_len ); + case 782: return makeRegisterExpression(amdgpu_gfx90a::acc14, output_vec_len ); + case 783: return makeRegisterExpression(amdgpu_gfx90a::acc15, output_vec_len ); + case 784: return makeRegisterExpression(amdgpu_gfx90a::acc16, output_vec_len ); + case 785: return makeRegisterExpression(amdgpu_gfx90a::acc17, output_vec_len ); + case 786: return makeRegisterExpression(amdgpu_gfx90a::acc18, output_vec_len ); + case 787: return makeRegisterExpression(amdgpu_gfx90a::acc19, output_vec_len ); + case 788: return makeRegisterExpression(amdgpu_gfx90a::acc20, output_vec_len ); + case 789: return makeRegisterExpression(amdgpu_gfx90a::acc21, output_vec_len ); + case 790: return makeRegisterExpression(amdgpu_gfx90a::acc22, output_vec_len ); + case 791: return makeRegisterExpression(amdgpu_gfx90a::acc23, output_vec_len ); + case 792: return makeRegisterExpression(amdgpu_gfx90a::acc24, output_vec_len ); + case 793: return makeRegisterExpression(amdgpu_gfx90a::acc25, output_vec_len ); + case 794: return makeRegisterExpression(amdgpu_gfx90a::acc26, output_vec_len ); + case 795: return makeRegisterExpression(amdgpu_gfx90a::acc27, output_vec_len ); + case 796: return makeRegisterExpression(amdgpu_gfx90a::acc28, output_vec_len ); + case 797: return makeRegisterExpression(amdgpu_gfx90a::acc29, output_vec_len ); + case 798: return makeRegisterExpression(amdgpu_gfx90a::acc30, output_vec_len ); + case 799: return makeRegisterExpression(amdgpu_gfx90a::acc31, output_vec_len ); + case 800: return makeRegisterExpression(amdgpu_gfx90a::acc32, output_vec_len ); + case 801: return makeRegisterExpression(amdgpu_gfx90a::acc33, output_vec_len ); + case 802: return makeRegisterExpression(amdgpu_gfx90a::acc34, output_vec_len ); + case 803: return makeRegisterExpression(amdgpu_gfx90a::acc35, output_vec_len ); + case 804: return makeRegisterExpression(amdgpu_gfx90a::acc36, output_vec_len ); + case 805: return makeRegisterExpression(amdgpu_gfx90a::acc37, output_vec_len ); + case 806: return makeRegisterExpression(amdgpu_gfx90a::acc38, output_vec_len ); + case 807: return makeRegisterExpression(amdgpu_gfx90a::acc39, output_vec_len ); + case 808: return makeRegisterExpression(amdgpu_gfx90a::acc40, output_vec_len ); + case 809: return makeRegisterExpression(amdgpu_gfx90a::acc41, output_vec_len ); + case 810: return makeRegisterExpression(amdgpu_gfx90a::acc42, output_vec_len ); + case 811: return makeRegisterExpression(amdgpu_gfx90a::acc43, output_vec_len ); + case 812: return makeRegisterExpression(amdgpu_gfx90a::acc44, output_vec_len ); + case 813: return makeRegisterExpression(amdgpu_gfx90a::acc45, output_vec_len ); + case 814: return makeRegisterExpression(amdgpu_gfx90a::acc46, output_vec_len ); + case 815: return makeRegisterExpression(amdgpu_gfx90a::acc47, output_vec_len ); + case 816: return makeRegisterExpression(amdgpu_gfx90a::acc48, output_vec_len ); + case 817: return makeRegisterExpression(amdgpu_gfx90a::acc49, output_vec_len ); + case 818: return makeRegisterExpression(amdgpu_gfx90a::acc50, output_vec_len ); + case 819: return makeRegisterExpression(amdgpu_gfx90a::acc51, output_vec_len ); + case 820: return makeRegisterExpression(amdgpu_gfx90a::acc52, output_vec_len ); + case 821: return makeRegisterExpression(amdgpu_gfx90a::acc53, output_vec_len ); + case 822: return makeRegisterExpression(amdgpu_gfx90a::acc54, output_vec_len ); + case 823: return makeRegisterExpression(amdgpu_gfx90a::acc55, output_vec_len ); + case 824: return makeRegisterExpression(amdgpu_gfx90a::acc56, output_vec_len ); + case 825: return makeRegisterExpression(amdgpu_gfx90a::acc57, output_vec_len ); + case 826: return makeRegisterExpression(amdgpu_gfx90a::acc58, output_vec_len ); + case 827: return makeRegisterExpression(amdgpu_gfx90a::acc59, output_vec_len ); + case 828: return makeRegisterExpression(amdgpu_gfx90a::acc60, output_vec_len ); + case 829: return makeRegisterExpression(amdgpu_gfx90a::acc61, output_vec_len ); + case 830: return makeRegisterExpression(amdgpu_gfx90a::acc62, output_vec_len ); + case 831: return makeRegisterExpression(amdgpu_gfx90a::acc63, output_vec_len ); + case 832: return makeRegisterExpression(amdgpu_gfx90a::acc64, output_vec_len ); + case 833: return makeRegisterExpression(amdgpu_gfx90a::acc65, output_vec_len ); + case 834: return makeRegisterExpression(amdgpu_gfx90a::acc66, output_vec_len ); + case 835: return makeRegisterExpression(amdgpu_gfx90a::acc67, output_vec_len ); + case 836: return makeRegisterExpression(amdgpu_gfx90a::acc68, output_vec_len ); + case 837: return makeRegisterExpression(amdgpu_gfx90a::acc69, output_vec_len ); + case 838: return makeRegisterExpression(amdgpu_gfx90a::acc70, output_vec_len ); + case 839: return makeRegisterExpression(amdgpu_gfx90a::acc71, output_vec_len ); + case 840: return makeRegisterExpression(amdgpu_gfx90a::acc72, output_vec_len ); + case 841: return makeRegisterExpression(amdgpu_gfx90a::acc73, output_vec_len ); + case 842: return makeRegisterExpression(amdgpu_gfx90a::acc74, output_vec_len ); + case 843: return makeRegisterExpression(amdgpu_gfx90a::acc75, output_vec_len ); + case 844: return makeRegisterExpression(amdgpu_gfx90a::acc76, output_vec_len ); + case 845: return makeRegisterExpression(amdgpu_gfx90a::acc77, output_vec_len ); + case 846: return makeRegisterExpression(amdgpu_gfx90a::acc78, output_vec_len ); + case 847: return makeRegisterExpression(amdgpu_gfx90a::acc79, output_vec_len ); + case 848: return makeRegisterExpression(amdgpu_gfx90a::acc80, output_vec_len ); + case 849: return makeRegisterExpression(amdgpu_gfx90a::acc81, output_vec_len ); + case 850: return makeRegisterExpression(amdgpu_gfx90a::acc82, output_vec_len ); + case 851: return makeRegisterExpression(amdgpu_gfx90a::acc83, output_vec_len ); + case 852: return makeRegisterExpression(amdgpu_gfx90a::acc84, output_vec_len ); + case 853: return makeRegisterExpression(amdgpu_gfx90a::acc85, output_vec_len ); + case 854: return makeRegisterExpression(amdgpu_gfx90a::acc86, output_vec_len ); + case 855: return makeRegisterExpression(amdgpu_gfx90a::acc87, output_vec_len ); + case 856: return makeRegisterExpression(amdgpu_gfx90a::acc88, output_vec_len ); + case 857: return makeRegisterExpression(amdgpu_gfx90a::acc89, output_vec_len ); + case 858: return makeRegisterExpression(amdgpu_gfx90a::acc90, output_vec_len ); + case 859: return makeRegisterExpression(amdgpu_gfx90a::acc91, output_vec_len ); + case 860: return makeRegisterExpression(amdgpu_gfx90a::acc92, output_vec_len ); + case 861: return makeRegisterExpression(amdgpu_gfx90a::acc93, output_vec_len ); + case 862: return makeRegisterExpression(amdgpu_gfx90a::acc94, output_vec_len ); + case 863: return makeRegisterExpression(amdgpu_gfx90a::acc95, output_vec_len ); + case 864: return makeRegisterExpression(amdgpu_gfx90a::acc96, output_vec_len ); + case 865: return makeRegisterExpression(amdgpu_gfx90a::acc97, output_vec_len ); + case 866: return makeRegisterExpression(amdgpu_gfx90a::acc98, output_vec_len ); + case 867: return makeRegisterExpression(amdgpu_gfx90a::acc99, output_vec_len ); + case 868: return makeRegisterExpression(amdgpu_gfx90a::acc100, output_vec_len ); + case 869: return makeRegisterExpression(amdgpu_gfx90a::acc101, output_vec_len ); + case 870: return makeRegisterExpression(amdgpu_gfx90a::acc102, output_vec_len ); + case 871: return makeRegisterExpression(amdgpu_gfx90a::acc103, output_vec_len ); + case 872: return makeRegisterExpression(amdgpu_gfx90a::acc104, output_vec_len ); + case 873: return makeRegisterExpression(amdgpu_gfx90a::acc105, output_vec_len ); + case 874: return makeRegisterExpression(amdgpu_gfx90a::acc106, output_vec_len ); + case 875: return makeRegisterExpression(amdgpu_gfx90a::acc107, output_vec_len ); + case 876: return makeRegisterExpression(amdgpu_gfx90a::acc108, output_vec_len ); + case 877: return makeRegisterExpression(amdgpu_gfx90a::acc109, output_vec_len ); + case 878: return makeRegisterExpression(amdgpu_gfx90a::acc110, output_vec_len ); + case 879: return makeRegisterExpression(amdgpu_gfx90a::acc111, output_vec_len ); + case 880: return makeRegisterExpression(amdgpu_gfx90a::acc112, output_vec_len ); + case 881: return makeRegisterExpression(amdgpu_gfx90a::acc113, output_vec_len ); + case 882: return makeRegisterExpression(amdgpu_gfx90a::acc114, output_vec_len ); + case 883: return makeRegisterExpression(amdgpu_gfx90a::acc115, output_vec_len ); + case 884: return makeRegisterExpression(amdgpu_gfx90a::acc116, output_vec_len ); + case 885: return makeRegisterExpression(amdgpu_gfx90a::acc117, output_vec_len ); + case 886: return makeRegisterExpression(amdgpu_gfx90a::acc118, output_vec_len ); + case 887: return makeRegisterExpression(amdgpu_gfx90a::acc119, output_vec_len ); + case 888: return makeRegisterExpression(amdgpu_gfx90a::acc120, output_vec_len ); + case 889: return makeRegisterExpression(amdgpu_gfx90a::acc121, output_vec_len ); + case 890: return makeRegisterExpression(amdgpu_gfx90a::acc122, output_vec_len ); + case 891: return makeRegisterExpression(amdgpu_gfx90a::acc123, output_vec_len ); + case 892: return makeRegisterExpression(amdgpu_gfx90a::acc124, output_vec_len ); + case 893: return makeRegisterExpression(amdgpu_gfx90a::acc125, output_vec_len ); + case 894: return makeRegisterExpression(amdgpu_gfx90a::acc126, output_vec_len ); + case 895: return makeRegisterExpression(amdgpu_gfx90a::acc127, output_vec_len ); + case 896: return makeRegisterExpression(amdgpu_gfx90a::acc128, output_vec_len ); + case 897: return makeRegisterExpression(amdgpu_gfx90a::acc129, output_vec_len ); + case 898: return makeRegisterExpression(amdgpu_gfx90a::acc130, output_vec_len ); + case 899: return makeRegisterExpression(amdgpu_gfx90a::acc131, output_vec_len ); + case 900: return makeRegisterExpression(amdgpu_gfx90a::acc132, output_vec_len ); + case 901: return makeRegisterExpression(amdgpu_gfx90a::acc133, output_vec_len ); + case 902: return makeRegisterExpression(amdgpu_gfx90a::acc134, output_vec_len ); + case 903: return makeRegisterExpression(amdgpu_gfx90a::acc135, output_vec_len ); + case 904: return makeRegisterExpression(amdgpu_gfx90a::acc136, output_vec_len ); + case 905: return makeRegisterExpression(amdgpu_gfx90a::acc137, output_vec_len ); + case 906: return makeRegisterExpression(amdgpu_gfx90a::acc138, output_vec_len ); + case 907: return makeRegisterExpression(amdgpu_gfx90a::acc139, output_vec_len ); + case 908: return makeRegisterExpression(amdgpu_gfx90a::acc140, output_vec_len ); + case 909: return makeRegisterExpression(amdgpu_gfx90a::acc141, output_vec_len ); + case 910: return makeRegisterExpression(amdgpu_gfx90a::acc142, output_vec_len ); + case 911: return makeRegisterExpression(amdgpu_gfx90a::acc143, output_vec_len ); + case 912: return makeRegisterExpression(amdgpu_gfx90a::acc144, output_vec_len ); + case 913: return makeRegisterExpression(amdgpu_gfx90a::acc145, output_vec_len ); + case 914: return makeRegisterExpression(amdgpu_gfx90a::acc146, output_vec_len ); + case 915: return makeRegisterExpression(amdgpu_gfx90a::acc147, output_vec_len ); + case 916: return makeRegisterExpression(amdgpu_gfx90a::acc148, output_vec_len ); + case 917: return makeRegisterExpression(amdgpu_gfx90a::acc149, output_vec_len ); + case 918: return makeRegisterExpression(amdgpu_gfx90a::acc150, output_vec_len ); + case 919: return makeRegisterExpression(amdgpu_gfx90a::acc151, output_vec_len ); + case 920: return makeRegisterExpression(amdgpu_gfx90a::acc152, output_vec_len ); + case 921: return makeRegisterExpression(amdgpu_gfx90a::acc153, output_vec_len ); + case 922: return makeRegisterExpression(amdgpu_gfx90a::acc154, output_vec_len ); + case 923: return makeRegisterExpression(amdgpu_gfx90a::acc155, output_vec_len ); + case 924: return makeRegisterExpression(amdgpu_gfx90a::acc156, output_vec_len ); + case 925: return makeRegisterExpression(amdgpu_gfx90a::acc157, output_vec_len ); + case 926: return makeRegisterExpression(amdgpu_gfx90a::acc158, output_vec_len ); + case 927: return makeRegisterExpression(amdgpu_gfx90a::acc159, output_vec_len ); + case 928: return makeRegisterExpression(amdgpu_gfx90a::acc160, output_vec_len ); + case 929: return makeRegisterExpression(amdgpu_gfx90a::acc161, output_vec_len ); + case 930: return makeRegisterExpression(amdgpu_gfx90a::acc162, output_vec_len ); + case 931: return makeRegisterExpression(amdgpu_gfx90a::acc163, output_vec_len ); + case 932: return makeRegisterExpression(amdgpu_gfx90a::acc164, output_vec_len ); + case 933: return makeRegisterExpression(amdgpu_gfx90a::acc165, output_vec_len ); + case 934: return makeRegisterExpression(amdgpu_gfx90a::acc166, output_vec_len ); + case 935: return makeRegisterExpression(amdgpu_gfx90a::acc167, output_vec_len ); + case 936: return makeRegisterExpression(amdgpu_gfx90a::acc168, output_vec_len ); + case 937: return makeRegisterExpression(amdgpu_gfx90a::acc169, output_vec_len ); + case 938: return makeRegisterExpression(amdgpu_gfx90a::acc170, output_vec_len ); + case 939: return makeRegisterExpression(amdgpu_gfx90a::acc171, output_vec_len ); + case 940: return makeRegisterExpression(amdgpu_gfx90a::acc172, output_vec_len ); + case 941: return makeRegisterExpression(amdgpu_gfx90a::acc173, output_vec_len ); + case 942: return makeRegisterExpression(amdgpu_gfx90a::acc174, output_vec_len ); + case 943: return makeRegisterExpression(amdgpu_gfx90a::acc175, output_vec_len ); + case 944: return makeRegisterExpression(amdgpu_gfx90a::acc176, output_vec_len ); + case 945: return makeRegisterExpression(amdgpu_gfx90a::acc177, output_vec_len ); + case 946: return makeRegisterExpression(amdgpu_gfx90a::acc178, output_vec_len ); + case 947: return makeRegisterExpression(amdgpu_gfx90a::acc179, output_vec_len ); + case 948: return makeRegisterExpression(amdgpu_gfx90a::acc180, output_vec_len ); + case 949: return makeRegisterExpression(amdgpu_gfx90a::acc181, output_vec_len ); + case 950: return makeRegisterExpression(amdgpu_gfx90a::acc182, output_vec_len ); + case 951: return makeRegisterExpression(amdgpu_gfx90a::acc183, output_vec_len ); + case 952: return makeRegisterExpression(amdgpu_gfx90a::acc184, output_vec_len ); + case 953: return makeRegisterExpression(amdgpu_gfx90a::acc185, output_vec_len ); + case 954: return makeRegisterExpression(amdgpu_gfx90a::acc186, output_vec_len ); + case 955: return makeRegisterExpression(amdgpu_gfx90a::acc187, output_vec_len ); + case 956: return makeRegisterExpression(amdgpu_gfx90a::acc188, output_vec_len ); + case 957: return makeRegisterExpression(amdgpu_gfx90a::acc189, output_vec_len ); + case 958: return makeRegisterExpression(amdgpu_gfx90a::acc190, output_vec_len ); + case 959: return makeRegisterExpression(amdgpu_gfx90a::acc191, output_vec_len ); + case 960: return makeRegisterExpression(amdgpu_gfx90a::acc192, output_vec_len ); + case 961: return makeRegisterExpression(amdgpu_gfx90a::acc193, output_vec_len ); + case 962: return makeRegisterExpression(amdgpu_gfx90a::acc194, output_vec_len ); + case 963: return makeRegisterExpression(amdgpu_gfx90a::acc195, output_vec_len ); + case 964: return makeRegisterExpression(amdgpu_gfx90a::acc196, output_vec_len ); + case 965: return makeRegisterExpression(amdgpu_gfx90a::acc197, output_vec_len ); + case 966: return makeRegisterExpression(amdgpu_gfx90a::acc198, output_vec_len ); + case 967: return makeRegisterExpression(amdgpu_gfx90a::acc199, output_vec_len ); + case 968: return makeRegisterExpression(amdgpu_gfx90a::acc200, output_vec_len ); + case 969: return makeRegisterExpression(amdgpu_gfx90a::acc201, output_vec_len ); + case 970: return makeRegisterExpression(amdgpu_gfx90a::acc202, output_vec_len ); + case 971: return makeRegisterExpression(amdgpu_gfx90a::acc203, output_vec_len ); + case 972: return makeRegisterExpression(amdgpu_gfx90a::acc204, output_vec_len ); + case 973: return makeRegisterExpression(amdgpu_gfx90a::acc205, output_vec_len ); + case 974: return makeRegisterExpression(amdgpu_gfx90a::acc206, output_vec_len ); + case 975: return makeRegisterExpression(amdgpu_gfx90a::acc207, output_vec_len ); + case 976: return makeRegisterExpression(amdgpu_gfx90a::acc208, output_vec_len ); + case 977: return makeRegisterExpression(amdgpu_gfx90a::acc209, output_vec_len ); + case 978: return makeRegisterExpression(amdgpu_gfx90a::acc210, output_vec_len ); + case 979: return makeRegisterExpression(amdgpu_gfx90a::acc211, output_vec_len ); + case 980: return makeRegisterExpression(amdgpu_gfx90a::acc212, output_vec_len ); + case 981: return makeRegisterExpression(amdgpu_gfx90a::acc213, output_vec_len ); + case 982: return makeRegisterExpression(amdgpu_gfx90a::acc214, output_vec_len ); + case 983: return makeRegisterExpression(amdgpu_gfx90a::acc215, output_vec_len ); + case 984: return makeRegisterExpression(amdgpu_gfx90a::acc216, output_vec_len ); + case 985: return makeRegisterExpression(amdgpu_gfx90a::acc217, output_vec_len ); + case 986: return makeRegisterExpression(amdgpu_gfx90a::acc218, output_vec_len ); + case 987: return makeRegisterExpression(amdgpu_gfx90a::acc219, output_vec_len ); + case 988: return makeRegisterExpression(amdgpu_gfx90a::acc220, output_vec_len ); + case 989: return makeRegisterExpression(amdgpu_gfx90a::acc221, output_vec_len ); + case 990: return makeRegisterExpression(amdgpu_gfx90a::acc222, output_vec_len ); + case 991: return makeRegisterExpression(amdgpu_gfx90a::acc223, output_vec_len ); + case 992: return makeRegisterExpression(amdgpu_gfx90a::acc224, output_vec_len ); + case 993: return makeRegisterExpression(amdgpu_gfx90a::acc225, output_vec_len ); + case 994: return makeRegisterExpression(amdgpu_gfx90a::acc226, output_vec_len ); + case 995: return makeRegisterExpression(amdgpu_gfx90a::acc227, output_vec_len ); + case 996: return makeRegisterExpression(amdgpu_gfx90a::acc228, output_vec_len ); + case 997: return makeRegisterExpression(amdgpu_gfx90a::acc229, output_vec_len ); + case 998: return makeRegisterExpression(amdgpu_gfx90a::acc230, output_vec_len ); + case 999: return makeRegisterExpression(amdgpu_gfx90a::acc231, output_vec_len ); + case 1000: return makeRegisterExpression(amdgpu_gfx90a::acc232, output_vec_len ); + case 1001: return makeRegisterExpression(amdgpu_gfx90a::acc233, output_vec_len ); + case 1002: return makeRegisterExpression(amdgpu_gfx90a::acc234, output_vec_len ); + case 1003: return makeRegisterExpression(amdgpu_gfx90a::acc235, output_vec_len ); + case 1004: return makeRegisterExpression(amdgpu_gfx90a::acc236, output_vec_len ); + case 1005: return makeRegisterExpression(amdgpu_gfx90a::acc237, output_vec_len ); + case 1006: return makeRegisterExpression(amdgpu_gfx90a::acc238, output_vec_len ); + case 1007: return makeRegisterExpression(amdgpu_gfx90a::acc239, output_vec_len ); + case 1008: return makeRegisterExpression(amdgpu_gfx90a::acc240, output_vec_len ); + case 1009: return makeRegisterExpression(amdgpu_gfx90a::acc241, output_vec_len ); + case 1010: return makeRegisterExpression(amdgpu_gfx90a::acc242, output_vec_len ); + case 1011: return makeRegisterExpression(amdgpu_gfx90a::acc243, output_vec_len ); + case 1012: return makeRegisterExpression(amdgpu_gfx90a::acc244, output_vec_len ); + case 1013: return makeRegisterExpression(amdgpu_gfx90a::acc245, output_vec_len ); + case 1014: return makeRegisterExpression(amdgpu_gfx90a::acc246, output_vec_len ); + case 1015: return makeRegisterExpression(amdgpu_gfx90a::acc247, output_vec_len ); + case 1016: return makeRegisterExpression(amdgpu_gfx90a::acc248, output_vec_len ); + case 1017: return makeRegisterExpression(amdgpu_gfx90a::acc249, output_vec_len ); + case 1018: return makeRegisterExpression(amdgpu_gfx90a::acc250, output_vec_len ); + case 1019: return makeRegisterExpression(amdgpu_gfx90a::acc251, output_vec_len ); + case 1020: return makeRegisterExpression(amdgpu_gfx90a::acc252, output_vec_len ); + case 1021: return makeRegisterExpression(amdgpu_gfx90a::acc253, output_vec_len ); + case 1022: return makeRegisterExpression(amdgpu_gfx90a::acc254, output_vec_len ); + case 1023: return makeRegisterExpression(amdgpu_gfx90a::acc255, output_vec_len ); + case 128: return Immediate::makeImmediate(Result(u32, 0)); + case 129: return Immediate::makeImmediate(Result(u32, 1)); + case 130: return Immediate::makeImmediate(Result(u32, 2)); + case 131: return Immediate::makeImmediate(Result(u32, 3)); + case 132: return Immediate::makeImmediate(Result(u32, 4)); + case 133: return Immediate::makeImmediate(Result(u32, 5)); + case 134: return Immediate::makeImmediate(Result(u32, 6)); + case 135: return Immediate::makeImmediate(Result(u32, 7)); + case 136: return Immediate::makeImmediate(Result(u32, 8)); + case 137: return Immediate::makeImmediate(Result(u32, 9)); + case 138: return Immediate::makeImmediate(Result(u32, 10)); + case 139: return Immediate::makeImmediate(Result(u32, 11)); + case 140: return Immediate::makeImmediate(Result(u32, 12)); + case 141: return Immediate::makeImmediate(Result(u32, 13)); + case 142: return Immediate::makeImmediate(Result(u32, 14)); + case 143: return Immediate::makeImmediate(Result(u32, 15)); + case 144: return Immediate::makeImmediate(Result(u32, 16)); + case 145: return Immediate::makeImmediate(Result(u32, 17)); + case 146: return Immediate::makeImmediate(Result(u32, 18)); + case 147: return Immediate::makeImmediate(Result(u32, 19)); + case 148: return Immediate::makeImmediate(Result(u32, 20)); + case 149: return Immediate::makeImmediate(Result(u32, 21)); + case 150: return Immediate::makeImmediate(Result(u32, 22)); + case 151: return Immediate::makeImmediate(Result(u32, 23)); + case 152: return Immediate::makeImmediate(Result(u32, 24)); + case 153: return Immediate::makeImmediate(Result(u32, 25)); + case 154: return Immediate::makeImmediate(Result(u32, 26)); + case 155: return Immediate::makeImmediate(Result(u32, 27)); + case 156: return Immediate::makeImmediate(Result(u32, 28)); + case 157: return Immediate::makeImmediate(Result(u32, 29)); + case 158: return Immediate::makeImmediate(Result(u32, 30)); + case 159: return Immediate::makeImmediate(Result(u32, 31)); + case 160: return Immediate::makeImmediate(Result(u32, 32)); + case 161: return Immediate::makeImmediate(Result(u32, 33)); + case 162: return Immediate::makeImmediate(Result(u32, 34)); + case 163: return Immediate::makeImmediate(Result(u32, 35)); + case 164: return Immediate::makeImmediate(Result(u32, 36)); + case 165: return Immediate::makeImmediate(Result(u32, 37)); + case 166: return Immediate::makeImmediate(Result(u32, 38)); + case 167: return Immediate::makeImmediate(Result(u32, 39)); + case 168: return Immediate::makeImmediate(Result(u32, 40)); + case 169: return Immediate::makeImmediate(Result(u32, 41)); + case 170: return Immediate::makeImmediate(Result(u32, 42)); + case 171: return Immediate::makeImmediate(Result(u32, 43)); + case 172: return Immediate::makeImmediate(Result(u32, 44)); + case 173: return Immediate::makeImmediate(Result(u32, 45)); + case 174: return Immediate::makeImmediate(Result(u32, 46)); + case 175: return Immediate::makeImmediate(Result(u32, 47)); + case 176: return Immediate::makeImmediate(Result(u32, 48)); + case 177: return Immediate::makeImmediate(Result(u32, 49)); + case 178: return Immediate::makeImmediate(Result(u32, 50)); + case 179: return Immediate::makeImmediate(Result(u32, 51)); + case 180: return Immediate::makeImmediate(Result(u32, 52)); + case 181: return Immediate::makeImmediate(Result(u32, 53)); + case 182: return Immediate::makeImmediate(Result(u32, 54)); + case 183: return Immediate::makeImmediate(Result(u32, 55)); + case 184: return Immediate::makeImmediate(Result(u32, 56)); + case 185: return Immediate::makeImmediate(Result(u32, 57)); + case 186: return Immediate::makeImmediate(Result(u32, 58)); + case 187: return Immediate::makeImmediate(Result(u32, 59)); + case 188: return Immediate::makeImmediate(Result(u32, 60)); + case 189: return Immediate::makeImmediate(Result(u32, 61)); + case 190: return Immediate::makeImmediate(Result(u32, 62)); + case 191: return Immediate::makeImmediate(Result(u32, 63)); + case 192: return Immediate::makeImmediate(Result(u32, 64)); + case 193: return Immediate::makeImmediate(Result(u32, -1)); + case 194: return Immediate::makeImmediate(Result(u32, -2)); + case 195: return Immediate::makeImmediate(Result(u32, -3)); + case 196: return Immediate::makeImmediate(Result(u32, -4)); + case 197: return Immediate::makeImmediate(Result(u32, -5)); + case 198: return Immediate::makeImmediate(Result(u32, -6)); + case 199: return Immediate::makeImmediate(Result(u32, -7)); + case 200: return Immediate::makeImmediate(Result(u32, -8)); + case 201: return Immediate::makeImmediate(Result(u32, -9)); + case 202: return Immediate::makeImmediate(Result(u32, -10)); + case 203: return Immediate::makeImmediate(Result(u32, -11)); + case 204: return Immediate::makeImmediate(Result(u32, -12)); + case 205: return Immediate::makeImmediate(Result(u32, -13)); + case 206: return Immediate::makeImmediate(Result(u32, -14)); + case 207: return Immediate::makeImmediate(Result(u32, -15)); + case 208: return Immediate::makeImmediate(Result(u32, -16)); + case 240: return Immediate::makeImmediate(Result(sp_float, 0.5)); + case 241: return Immediate::makeImmediate(Result(sp_float, -0.5)); + case 242: return Immediate::makeImmediate(Result(sp_float, 1.0)); + case 243: return Immediate::makeImmediate(Result(sp_float, -1.0)); + case 244: return Immediate::makeImmediate(Result(sp_float, 2.0)); + case 245: return Immediate::makeImmediate(Result(sp_float, -2.0)); + case 246: return Immediate::makeImmediate(Result(sp_float, 4.0)); + case 247: return Immediate::makeImmediate(Result(sp_float, -4.0)); + case 248: return Immediate::makeImmediate(Result(sp_float, 0.15915494)); + default: return makeRegisterExpression(amdgpu_gfx90a::invalid); + } + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx90a::decodeOPR_SREG(uint64_t input, uint32_t output_vec_len) + { + switch (input) { + case 0: return makeRegisterExpression(amdgpu_gfx90a::s0, output_vec_len ); + case 1: return makeRegisterExpression(amdgpu_gfx90a::s1, output_vec_len ); + case 2: return makeRegisterExpression(amdgpu_gfx90a::s2, output_vec_len ); + case 3: return makeRegisterExpression(amdgpu_gfx90a::s3, output_vec_len ); + case 4: return makeRegisterExpression(amdgpu_gfx90a::s4, output_vec_len ); + case 5: return makeRegisterExpression(amdgpu_gfx90a::s5, output_vec_len ); + case 6: return makeRegisterExpression(amdgpu_gfx90a::s6, output_vec_len ); + case 7: return makeRegisterExpression(amdgpu_gfx90a::s7, output_vec_len ); + case 8: return makeRegisterExpression(amdgpu_gfx90a::s8, output_vec_len ); + case 9: return makeRegisterExpression(amdgpu_gfx90a::s9, output_vec_len ); + case 10: return makeRegisterExpression(amdgpu_gfx90a::s10, output_vec_len ); + case 11: return makeRegisterExpression(amdgpu_gfx90a::s11, output_vec_len ); + case 12: return makeRegisterExpression(amdgpu_gfx90a::s12, output_vec_len ); + case 13: return makeRegisterExpression(amdgpu_gfx90a::s13, output_vec_len ); + case 14: return makeRegisterExpression(amdgpu_gfx90a::s14, output_vec_len ); + case 15: return makeRegisterExpression(amdgpu_gfx90a::s15, output_vec_len ); + case 16: return makeRegisterExpression(amdgpu_gfx90a::s16, output_vec_len ); + case 17: return makeRegisterExpression(amdgpu_gfx90a::s17, output_vec_len ); + case 18: return makeRegisterExpression(amdgpu_gfx90a::s18, output_vec_len ); + case 19: return makeRegisterExpression(amdgpu_gfx90a::s19, output_vec_len ); + case 20: return makeRegisterExpression(amdgpu_gfx90a::s20, output_vec_len ); + case 21: return makeRegisterExpression(amdgpu_gfx90a::s21, output_vec_len ); + case 22: return makeRegisterExpression(amdgpu_gfx90a::s22, output_vec_len ); + case 23: return makeRegisterExpression(amdgpu_gfx90a::s23, output_vec_len ); + case 24: return makeRegisterExpression(amdgpu_gfx90a::s24, output_vec_len ); + case 25: return makeRegisterExpression(amdgpu_gfx90a::s25, output_vec_len ); + case 26: return makeRegisterExpression(amdgpu_gfx90a::s26, output_vec_len ); + case 27: return makeRegisterExpression(amdgpu_gfx90a::s27, output_vec_len ); + case 28: return makeRegisterExpression(amdgpu_gfx90a::s28, output_vec_len ); + case 29: return makeRegisterExpression(amdgpu_gfx90a::s29, output_vec_len ); + case 30: return makeRegisterExpression(amdgpu_gfx90a::s30, output_vec_len ); + case 31: return makeRegisterExpression(amdgpu_gfx90a::s31, output_vec_len ); + case 32: return makeRegisterExpression(amdgpu_gfx90a::s32, output_vec_len ); + case 33: return makeRegisterExpression(amdgpu_gfx90a::s33, output_vec_len ); + case 34: return makeRegisterExpression(amdgpu_gfx90a::s34, output_vec_len ); + case 35: return makeRegisterExpression(amdgpu_gfx90a::s35, output_vec_len ); + case 36: return makeRegisterExpression(amdgpu_gfx90a::s36, output_vec_len ); + case 37: return makeRegisterExpression(amdgpu_gfx90a::s37, output_vec_len ); + case 38: return makeRegisterExpression(amdgpu_gfx90a::s38, output_vec_len ); + case 39: return makeRegisterExpression(amdgpu_gfx90a::s39, output_vec_len ); + case 40: return makeRegisterExpression(amdgpu_gfx90a::s40, output_vec_len ); + case 41: return makeRegisterExpression(amdgpu_gfx90a::s41, output_vec_len ); + case 42: return makeRegisterExpression(amdgpu_gfx90a::s42, output_vec_len ); + case 43: return makeRegisterExpression(amdgpu_gfx90a::s43, output_vec_len ); + case 44: return makeRegisterExpression(amdgpu_gfx90a::s44, output_vec_len ); + case 45: return makeRegisterExpression(amdgpu_gfx90a::s45, output_vec_len ); + case 46: return makeRegisterExpression(amdgpu_gfx90a::s46, output_vec_len ); + case 47: return makeRegisterExpression(amdgpu_gfx90a::s47, output_vec_len ); + case 48: return makeRegisterExpression(amdgpu_gfx90a::s48, output_vec_len ); + case 49: return makeRegisterExpression(amdgpu_gfx90a::s49, output_vec_len ); + case 50: return makeRegisterExpression(amdgpu_gfx90a::s50, output_vec_len ); + case 51: return makeRegisterExpression(amdgpu_gfx90a::s51, output_vec_len ); + case 52: return makeRegisterExpression(amdgpu_gfx90a::s52, output_vec_len ); + case 53: return makeRegisterExpression(amdgpu_gfx90a::s53, output_vec_len ); + case 54: return makeRegisterExpression(amdgpu_gfx90a::s54, output_vec_len ); + case 55: return makeRegisterExpression(amdgpu_gfx90a::s55, output_vec_len ); + case 56: return makeRegisterExpression(amdgpu_gfx90a::s56, output_vec_len ); + case 57: return makeRegisterExpression(amdgpu_gfx90a::s57, output_vec_len ); + case 58: return makeRegisterExpression(amdgpu_gfx90a::s58, output_vec_len ); + case 59: return makeRegisterExpression(amdgpu_gfx90a::s59, output_vec_len ); + case 60: return makeRegisterExpression(amdgpu_gfx90a::s60, output_vec_len ); + case 61: return makeRegisterExpression(amdgpu_gfx90a::s61, output_vec_len ); + case 62: return makeRegisterExpression(amdgpu_gfx90a::s62, output_vec_len ); + case 63: return makeRegisterExpression(amdgpu_gfx90a::s63, output_vec_len ); + case 64: return makeRegisterExpression(amdgpu_gfx90a::s64, output_vec_len ); + case 65: return makeRegisterExpression(amdgpu_gfx90a::s65, output_vec_len ); + case 66: return makeRegisterExpression(amdgpu_gfx90a::s66, output_vec_len ); + case 67: return makeRegisterExpression(amdgpu_gfx90a::s67, output_vec_len ); + case 68: return makeRegisterExpression(amdgpu_gfx90a::s68, output_vec_len ); + case 69: return makeRegisterExpression(amdgpu_gfx90a::s69, output_vec_len ); + case 70: return makeRegisterExpression(amdgpu_gfx90a::s70, output_vec_len ); + case 71: return makeRegisterExpression(amdgpu_gfx90a::s71, output_vec_len ); + case 72: return makeRegisterExpression(amdgpu_gfx90a::s72, output_vec_len ); + case 73: return makeRegisterExpression(amdgpu_gfx90a::s73, output_vec_len ); + case 74: return makeRegisterExpression(amdgpu_gfx90a::s74, output_vec_len ); + case 75: return makeRegisterExpression(amdgpu_gfx90a::s75, output_vec_len ); + case 76: return makeRegisterExpression(amdgpu_gfx90a::s76, output_vec_len ); + case 77: return makeRegisterExpression(amdgpu_gfx90a::s77, output_vec_len ); + case 78: return makeRegisterExpression(amdgpu_gfx90a::s78, output_vec_len ); + case 79: return makeRegisterExpression(amdgpu_gfx90a::s79, output_vec_len ); + case 80: return makeRegisterExpression(amdgpu_gfx90a::s80, output_vec_len ); + case 81: return makeRegisterExpression(amdgpu_gfx90a::s81, output_vec_len ); + case 82: return makeRegisterExpression(amdgpu_gfx90a::s82, output_vec_len ); + case 83: return makeRegisterExpression(amdgpu_gfx90a::s83, output_vec_len ); + case 84: return makeRegisterExpression(amdgpu_gfx90a::s84, output_vec_len ); + case 85: return makeRegisterExpression(amdgpu_gfx90a::s85, output_vec_len ); + case 86: return makeRegisterExpression(amdgpu_gfx90a::s86, output_vec_len ); + case 87: return makeRegisterExpression(amdgpu_gfx90a::s87, output_vec_len ); + case 88: return makeRegisterExpression(amdgpu_gfx90a::s88, output_vec_len ); + case 89: return makeRegisterExpression(amdgpu_gfx90a::s89, output_vec_len ); + case 90: return makeRegisterExpression(amdgpu_gfx90a::s90, output_vec_len ); + case 91: return makeRegisterExpression(amdgpu_gfx90a::s91, output_vec_len ); + case 92: return makeRegisterExpression(amdgpu_gfx90a::s92, output_vec_len ); + case 93: return makeRegisterExpression(amdgpu_gfx90a::s93, output_vec_len ); + case 94: return makeRegisterExpression(amdgpu_gfx90a::s94, output_vec_len ); + case 95: return makeRegisterExpression(amdgpu_gfx90a::s95, output_vec_len ); + case 96: return makeRegisterExpression(amdgpu_gfx90a::s96, output_vec_len ); + case 97: return makeRegisterExpression(amdgpu_gfx90a::s97, output_vec_len ); + case 98: return makeRegisterExpression(amdgpu_gfx90a::s98, output_vec_len ); + case 99: return makeRegisterExpression(amdgpu_gfx90a::s99, output_vec_len ); + case 100: return makeRegisterExpression(amdgpu_gfx90a::s100, output_vec_len ); + case 101: return makeRegisterExpression(amdgpu_gfx90a::s101, output_vec_len ); + case 104: return makeRegisterExpression(amdgpu_gfx90a::xnack_mask_lo, output_vec_len ); + case 105: return makeRegisterExpression(amdgpu_gfx90a::xnack_mask_hi, output_vec_len ); + case 102: return makeRegisterExpression(amdgpu_gfx90a::flat_scratch_lo, output_vec_len ); + case 103: return makeRegisterExpression(amdgpu_gfx90a::flat_scratch_hi, output_vec_len ); + case 108: return makeRegisterExpression(amdgpu_gfx90a::ttmp0, output_vec_len ); + case 109: return makeRegisterExpression(amdgpu_gfx90a::ttmp1, output_vec_len ); + case 110: return makeRegisterExpression(amdgpu_gfx90a::ttmp2, output_vec_len ); + case 111: return makeRegisterExpression(amdgpu_gfx90a::ttmp3, output_vec_len ); + case 112: return makeRegisterExpression(amdgpu_gfx90a::ttmp4, output_vec_len ); + case 113: return makeRegisterExpression(amdgpu_gfx90a::ttmp5, output_vec_len ); + case 114: return makeRegisterExpression(amdgpu_gfx90a::ttmp6, output_vec_len ); + case 115: return makeRegisterExpression(amdgpu_gfx90a::ttmp7, output_vec_len ); + case 116: return makeRegisterExpression(amdgpu_gfx90a::ttmp8, output_vec_len ); + case 117: return makeRegisterExpression(amdgpu_gfx90a::ttmp9, output_vec_len ); + case 118: return makeRegisterExpression(amdgpu_gfx90a::ttmp10, output_vec_len ); + case 119: return makeRegisterExpression(amdgpu_gfx90a::ttmp11, output_vec_len ); + case 120: return makeRegisterExpression(amdgpu_gfx90a::ttmp12, output_vec_len ); + case 121: return makeRegisterExpression(amdgpu_gfx90a::ttmp13, output_vec_len ); + case 122: return makeRegisterExpression(amdgpu_gfx90a::ttmp14, output_vec_len ); + case 123: return makeRegisterExpression(amdgpu_gfx90a::ttmp15, output_vec_len ); + case 106: return makeRegisterExpression(amdgpu_gfx90a::vcc_lo, output_vec_len ); + case 107: return makeRegisterExpression(amdgpu_gfx90a::vcc_hi, output_vec_len ); + default: return makeRegisterExpression(amdgpu_gfx90a::invalid); + } + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx90a::decodeOPR_SREG_NOVCC(uint64_t input, uint32_t output_vec_len) + { + switch (input) { + case 0: return makeRegisterExpression(amdgpu_gfx90a::s0, output_vec_len ); + case 1: return makeRegisterExpression(amdgpu_gfx90a::s1, output_vec_len ); + case 2: return makeRegisterExpression(amdgpu_gfx90a::s2, output_vec_len ); + case 3: return makeRegisterExpression(amdgpu_gfx90a::s3, output_vec_len ); + case 4: return makeRegisterExpression(amdgpu_gfx90a::s4, output_vec_len ); + case 5: return makeRegisterExpression(amdgpu_gfx90a::s5, output_vec_len ); + case 6: return makeRegisterExpression(amdgpu_gfx90a::s6, output_vec_len ); + case 7: return makeRegisterExpression(amdgpu_gfx90a::s7, output_vec_len ); + case 8: return makeRegisterExpression(amdgpu_gfx90a::s8, output_vec_len ); + case 9: return makeRegisterExpression(amdgpu_gfx90a::s9, output_vec_len ); + case 10: return makeRegisterExpression(amdgpu_gfx90a::s10, output_vec_len ); + case 11: return makeRegisterExpression(amdgpu_gfx90a::s11, output_vec_len ); + case 12: return makeRegisterExpression(amdgpu_gfx90a::s12, output_vec_len ); + case 13: return makeRegisterExpression(amdgpu_gfx90a::s13, output_vec_len ); + case 14: return makeRegisterExpression(amdgpu_gfx90a::s14, output_vec_len ); + case 15: return makeRegisterExpression(amdgpu_gfx90a::s15, output_vec_len ); + case 16: return makeRegisterExpression(amdgpu_gfx90a::s16, output_vec_len ); + case 17: return makeRegisterExpression(amdgpu_gfx90a::s17, output_vec_len ); + case 18: return makeRegisterExpression(amdgpu_gfx90a::s18, output_vec_len ); + case 19: return makeRegisterExpression(amdgpu_gfx90a::s19, output_vec_len ); + case 20: return makeRegisterExpression(amdgpu_gfx90a::s20, output_vec_len ); + case 21: return makeRegisterExpression(amdgpu_gfx90a::s21, output_vec_len ); + case 22: return makeRegisterExpression(amdgpu_gfx90a::s22, output_vec_len ); + case 23: return makeRegisterExpression(amdgpu_gfx90a::s23, output_vec_len ); + case 24: return makeRegisterExpression(amdgpu_gfx90a::s24, output_vec_len ); + case 25: return makeRegisterExpression(amdgpu_gfx90a::s25, output_vec_len ); + case 26: return makeRegisterExpression(amdgpu_gfx90a::s26, output_vec_len ); + case 27: return makeRegisterExpression(amdgpu_gfx90a::s27, output_vec_len ); + case 28: return makeRegisterExpression(amdgpu_gfx90a::s28, output_vec_len ); + case 29: return makeRegisterExpression(amdgpu_gfx90a::s29, output_vec_len ); + case 30: return makeRegisterExpression(amdgpu_gfx90a::s30, output_vec_len ); + case 31: return makeRegisterExpression(amdgpu_gfx90a::s31, output_vec_len ); + case 32: return makeRegisterExpression(amdgpu_gfx90a::s32, output_vec_len ); + case 33: return makeRegisterExpression(amdgpu_gfx90a::s33, output_vec_len ); + case 34: return makeRegisterExpression(amdgpu_gfx90a::s34, output_vec_len ); + case 35: return makeRegisterExpression(amdgpu_gfx90a::s35, output_vec_len ); + case 36: return makeRegisterExpression(amdgpu_gfx90a::s36, output_vec_len ); + case 37: return makeRegisterExpression(amdgpu_gfx90a::s37, output_vec_len ); + case 38: return makeRegisterExpression(amdgpu_gfx90a::s38, output_vec_len ); + case 39: return makeRegisterExpression(amdgpu_gfx90a::s39, output_vec_len ); + case 40: return makeRegisterExpression(amdgpu_gfx90a::s40, output_vec_len ); + case 41: return makeRegisterExpression(amdgpu_gfx90a::s41, output_vec_len ); + case 42: return makeRegisterExpression(amdgpu_gfx90a::s42, output_vec_len ); + case 43: return makeRegisterExpression(amdgpu_gfx90a::s43, output_vec_len ); + case 44: return makeRegisterExpression(amdgpu_gfx90a::s44, output_vec_len ); + case 45: return makeRegisterExpression(amdgpu_gfx90a::s45, output_vec_len ); + case 46: return makeRegisterExpression(amdgpu_gfx90a::s46, output_vec_len ); + case 47: return makeRegisterExpression(amdgpu_gfx90a::s47, output_vec_len ); + case 48: return makeRegisterExpression(amdgpu_gfx90a::s48, output_vec_len ); + case 49: return makeRegisterExpression(amdgpu_gfx90a::s49, output_vec_len ); + case 50: return makeRegisterExpression(amdgpu_gfx90a::s50, output_vec_len ); + case 51: return makeRegisterExpression(amdgpu_gfx90a::s51, output_vec_len ); + case 52: return makeRegisterExpression(amdgpu_gfx90a::s52, output_vec_len ); + case 53: return makeRegisterExpression(amdgpu_gfx90a::s53, output_vec_len ); + case 54: return makeRegisterExpression(amdgpu_gfx90a::s54, output_vec_len ); + case 55: return makeRegisterExpression(amdgpu_gfx90a::s55, output_vec_len ); + case 56: return makeRegisterExpression(amdgpu_gfx90a::s56, output_vec_len ); + case 57: return makeRegisterExpression(amdgpu_gfx90a::s57, output_vec_len ); + case 58: return makeRegisterExpression(amdgpu_gfx90a::s58, output_vec_len ); + case 59: return makeRegisterExpression(amdgpu_gfx90a::s59, output_vec_len ); + case 60: return makeRegisterExpression(amdgpu_gfx90a::s60, output_vec_len ); + case 61: return makeRegisterExpression(amdgpu_gfx90a::s61, output_vec_len ); + case 62: return makeRegisterExpression(amdgpu_gfx90a::s62, output_vec_len ); + case 63: return makeRegisterExpression(amdgpu_gfx90a::s63, output_vec_len ); + case 64: return makeRegisterExpression(amdgpu_gfx90a::s64, output_vec_len ); + case 65: return makeRegisterExpression(amdgpu_gfx90a::s65, output_vec_len ); + case 66: return makeRegisterExpression(amdgpu_gfx90a::s66, output_vec_len ); + case 67: return makeRegisterExpression(amdgpu_gfx90a::s67, output_vec_len ); + case 68: return makeRegisterExpression(amdgpu_gfx90a::s68, output_vec_len ); + case 69: return makeRegisterExpression(amdgpu_gfx90a::s69, output_vec_len ); + case 70: return makeRegisterExpression(amdgpu_gfx90a::s70, output_vec_len ); + case 71: return makeRegisterExpression(amdgpu_gfx90a::s71, output_vec_len ); + case 72: return makeRegisterExpression(amdgpu_gfx90a::s72, output_vec_len ); + case 73: return makeRegisterExpression(amdgpu_gfx90a::s73, output_vec_len ); + case 74: return makeRegisterExpression(amdgpu_gfx90a::s74, output_vec_len ); + case 75: return makeRegisterExpression(amdgpu_gfx90a::s75, output_vec_len ); + case 76: return makeRegisterExpression(amdgpu_gfx90a::s76, output_vec_len ); + case 77: return makeRegisterExpression(amdgpu_gfx90a::s77, output_vec_len ); + case 78: return makeRegisterExpression(amdgpu_gfx90a::s78, output_vec_len ); + case 79: return makeRegisterExpression(amdgpu_gfx90a::s79, output_vec_len ); + case 80: return makeRegisterExpression(amdgpu_gfx90a::s80, output_vec_len ); + case 81: return makeRegisterExpression(amdgpu_gfx90a::s81, output_vec_len ); + case 82: return makeRegisterExpression(amdgpu_gfx90a::s82, output_vec_len ); + case 83: return makeRegisterExpression(amdgpu_gfx90a::s83, output_vec_len ); + case 84: return makeRegisterExpression(amdgpu_gfx90a::s84, output_vec_len ); + case 85: return makeRegisterExpression(amdgpu_gfx90a::s85, output_vec_len ); + case 86: return makeRegisterExpression(amdgpu_gfx90a::s86, output_vec_len ); + case 87: return makeRegisterExpression(amdgpu_gfx90a::s87, output_vec_len ); + case 88: return makeRegisterExpression(amdgpu_gfx90a::s88, output_vec_len ); + case 89: return makeRegisterExpression(amdgpu_gfx90a::s89, output_vec_len ); + case 90: return makeRegisterExpression(amdgpu_gfx90a::s90, output_vec_len ); + case 91: return makeRegisterExpression(amdgpu_gfx90a::s91, output_vec_len ); + case 92: return makeRegisterExpression(amdgpu_gfx90a::s92, output_vec_len ); + case 93: return makeRegisterExpression(amdgpu_gfx90a::s93, output_vec_len ); + case 94: return makeRegisterExpression(amdgpu_gfx90a::s94, output_vec_len ); + case 95: return makeRegisterExpression(amdgpu_gfx90a::s95, output_vec_len ); + case 96: return makeRegisterExpression(amdgpu_gfx90a::s96, output_vec_len ); + case 97: return makeRegisterExpression(amdgpu_gfx90a::s97, output_vec_len ); + case 98: return makeRegisterExpression(amdgpu_gfx90a::s98, output_vec_len ); + case 99: return makeRegisterExpression(amdgpu_gfx90a::s99, output_vec_len ); + case 100: return makeRegisterExpression(amdgpu_gfx90a::s100, output_vec_len ); + case 101: return makeRegisterExpression(amdgpu_gfx90a::s101, output_vec_len ); + case 104: return makeRegisterExpression(amdgpu_gfx90a::xnack_mask_lo, output_vec_len ); + case 105: return makeRegisterExpression(amdgpu_gfx90a::xnack_mask_hi, output_vec_len ); + case 102: return makeRegisterExpression(amdgpu_gfx90a::flat_scratch_lo, output_vec_len ); + case 103: return makeRegisterExpression(amdgpu_gfx90a::flat_scratch_hi, output_vec_len ); + case 108: return makeRegisterExpression(amdgpu_gfx90a::ttmp0, output_vec_len ); + case 109: return makeRegisterExpression(amdgpu_gfx90a::ttmp1, output_vec_len ); + case 110: return makeRegisterExpression(amdgpu_gfx90a::ttmp2, output_vec_len ); + case 111: return makeRegisterExpression(amdgpu_gfx90a::ttmp3, output_vec_len ); + case 112: return makeRegisterExpression(amdgpu_gfx90a::ttmp4, output_vec_len ); + case 113: return makeRegisterExpression(amdgpu_gfx90a::ttmp5, output_vec_len ); + case 114: return makeRegisterExpression(amdgpu_gfx90a::ttmp6, output_vec_len ); + case 115: return makeRegisterExpression(amdgpu_gfx90a::ttmp7, output_vec_len ); + case 116: return makeRegisterExpression(amdgpu_gfx90a::ttmp8, output_vec_len ); + case 117: return makeRegisterExpression(amdgpu_gfx90a::ttmp9, output_vec_len ); + case 118: return makeRegisterExpression(amdgpu_gfx90a::ttmp10, output_vec_len ); + case 119: return makeRegisterExpression(amdgpu_gfx90a::ttmp11, output_vec_len ); + case 120: return makeRegisterExpression(amdgpu_gfx90a::ttmp12, output_vec_len ); + case 121: return makeRegisterExpression(amdgpu_gfx90a::ttmp13, output_vec_len ); + case 122: return makeRegisterExpression(amdgpu_gfx90a::ttmp14, output_vec_len ); + case 123: return makeRegisterExpression(amdgpu_gfx90a::ttmp15, output_vec_len ); + default: return makeRegisterExpression(amdgpu_gfx90a::invalid); + } + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx90a::decodeOPR_SSRC(uint64_t input, uint32_t output_vec_len) + { + switch (input) { + case 0: return makeRegisterExpression(amdgpu_gfx90a::s0, output_vec_len ); + case 1: return makeRegisterExpression(amdgpu_gfx90a::s1, output_vec_len ); + case 2: return makeRegisterExpression(amdgpu_gfx90a::s2, output_vec_len ); + case 3: return makeRegisterExpression(amdgpu_gfx90a::s3, output_vec_len ); + case 4: return makeRegisterExpression(amdgpu_gfx90a::s4, output_vec_len ); + case 5: return makeRegisterExpression(amdgpu_gfx90a::s5, output_vec_len ); + case 6: return makeRegisterExpression(amdgpu_gfx90a::s6, output_vec_len ); + case 7: return makeRegisterExpression(amdgpu_gfx90a::s7, output_vec_len ); + case 8: return makeRegisterExpression(amdgpu_gfx90a::s8, output_vec_len ); + case 9: return makeRegisterExpression(amdgpu_gfx90a::s9, output_vec_len ); + case 10: return makeRegisterExpression(amdgpu_gfx90a::s10, output_vec_len ); + case 11: return makeRegisterExpression(amdgpu_gfx90a::s11, output_vec_len ); + case 12: return makeRegisterExpression(amdgpu_gfx90a::s12, output_vec_len ); + case 13: return makeRegisterExpression(amdgpu_gfx90a::s13, output_vec_len ); + case 14: return makeRegisterExpression(amdgpu_gfx90a::s14, output_vec_len ); + case 15: return makeRegisterExpression(amdgpu_gfx90a::s15, output_vec_len ); + case 16: return makeRegisterExpression(amdgpu_gfx90a::s16, output_vec_len ); + case 17: return makeRegisterExpression(amdgpu_gfx90a::s17, output_vec_len ); + case 18: return makeRegisterExpression(amdgpu_gfx90a::s18, output_vec_len ); + case 19: return makeRegisterExpression(amdgpu_gfx90a::s19, output_vec_len ); + case 20: return makeRegisterExpression(amdgpu_gfx90a::s20, output_vec_len ); + case 21: return makeRegisterExpression(amdgpu_gfx90a::s21, output_vec_len ); + case 22: return makeRegisterExpression(amdgpu_gfx90a::s22, output_vec_len ); + case 23: return makeRegisterExpression(amdgpu_gfx90a::s23, output_vec_len ); + case 24: return makeRegisterExpression(amdgpu_gfx90a::s24, output_vec_len ); + case 25: return makeRegisterExpression(amdgpu_gfx90a::s25, output_vec_len ); + case 26: return makeRegisterExpression(amdgpu_gfx90a::s26, output_vec_len ); + case 27: return makeRegisterExpression(amdgpu_gfx90a::s27, output_vec_len ); + case 28: return makeRegisterExpression(amdgpu_gfx90a::s28, output_vec_len ); + case 29: return makeRegisterExpression(amdgpu_gfx90a::s29, output_vec_len ); + case 30: return makeRegisterExpression(amdgpu_gfx90a::s30, output_vec_len ); + case 31: return makeRegisterExpression(amdgpu_gfx90a::s31, output_vec_len ); + case 32: return makeRegisterExpression(amdgpu_gfx90a::s32, output_vec_len ); + case 33: return makeRegisterExpression(amdgpu_gfx90a::s33, output_vec_len ); + case 34: return makeRegisterExpression(amdgpu_gfx90a::s34, output_vec_len ); + case 35: return makeRegisterExpression(amdgpu_gfx90a::s35, output_vec_len ); + case 36: return makeRegisterExpression(amdgpu_gfx90a::s36, output_vec_len ); + case 37: return makeRegisterExpression(amdgpu_gfx90a::s37, output_vec_len ); + case 38: return makeRegisterExpression(amdgpu_gfx90a::s38, output_vec_len ); + case 39: return makeRegisterExpression(amdgpu_gfx90a::s39, output_vec_len ); + case 40: return makeRegisterExpression(amdgpu_gfx90a::s40, output_vec_len ); + case 41: return makeRegisterExpression(amdgpu_gfx90a::s41, output_vec_len ); + case 42: return makeRegisterExpression(amdgpu_gfx90a::s42, output_vec_len ); + case 43: return makeRegisterExpression(amdgpu_gfx90a::s43, output_vec_len ); + case 44: return makeRegisterExpression(amdgpu_gfx90a::s44, output_vec_len ); + case 45: return makeRegisterExpression(amdgpu_gfx90a::s45, output_vec_len ); + case 46: return makeRegisterExpression(amdgpu_gfx90a::s46, output_vec_len ); + case 47: return makeRegisterExpression(amdgpu_gfx90a::s47, output_vec_len ); + case 48: return makeRegisterExpression(amdgpu_gfx90a::s48, output_vec_len ); + case 49: return makeRegisterExpression(amdgpu_gfx90a::s49, output_vec_len ); + case 50: return makeRegisterExpression(amdgpu_gfx90a::s50, output_vec_len ); + case 51: return makeRegisterExpression(amdgpu_gfx90a::s51, output_vec_len ); + case 52: return makeRegisterExpression(amdgpu_gfx90a::s52, output_vec_len ); + case 53: return makeRegisterExpression(amdgpu_gfx90a::s53, output_vec_len ); + case 54: return makeRegisterExpression(amdgpu_gfx90a::s54, output_vec_len ); + case 55: return makeRegisterExpression(amdgpu_gfx90a::s55, output_vec_len ); + case 56: return makeRegisterExpression(amdgpu_gfx90a::s56, output_vec_len ); + case 57: return makeRegisterExpression(amdgpu_gfx90a::s57, output_vec_len ); + case 58: return makeRegisterExpression(amdgpu_gfx90a::s58, output_vec_len ); + case 59: return makeRegisterExpression(amdgpu_gfx90a::s59, output_vec_len ); + case 60: return makeRegisterExpression(amdgpu_gfx90a::s60, output_vec_len ); + case 61: return makeRegisterExpression(amdgpu_gfx90a::s61, output_vec_len ); + case 62: return makeRegisterExpression(amdgpu_gfx90a::s62, output_vec_len ); + case 63: return makeRegisterExpression(amdgpu_gfx90a::s63, output_vec_len ); + case 64: return makeRegisterExpression(amdgpu_gfx90a::s64, output_vec_len ); + case 65: return makeRegisterExpression(amdgpu_gfx90a::s65, output_vec_len ); + case 66: return makeRegisterExpression(amdgpu_gfx90a::s66, output_vec_len ); + case 67: return makeRegisterExpression(amdgpu_gfx90a::s67, output_vec_len ); + case 68: return makeRegisterExpression(amdgpu_gfx90a::s68, output_vec_len ); + case 69: return makeRegisterExpression(amdgpu_gfx90a::s69, output_vec_len ); + case 70: return makeRegisterExpression(amdgpu_gfx90a::s70, output_vec_len ); + case 71: return makeRegisterExpression(amdgpu_gfx90a::s71, output_vec_len ); + case 72: return makeRegisterExpression(amdgpu_gfx90a::s72, output_vec_len ); + case 73: return makeRegisterExpression(amdgpu_gfx90a::s73, output_vec_len ); + case 74: return makeRegisterExpression(amdgpu_gfx90a::s74, output_vec_len ); + case 75: return makeRegisterExpression(amdgpu_gfx90a::s75, output_vec_len ); + case 76: return makeRegisterExpression(amdgpu_gfx90a::s76, output_vec_len ); + case 77: return makeRegisterExpression(amdgpu_gfx90a::s77, output_vec_len ); + case 78: return makeRegisterExpression(amdgpu_gfx90a::s78, output_vec_len ); + case 79: return makeRegisterExpression(amdgpu_gfx90a::s79, output_vec_len ); + case 80: return makeRegisterExpression(amdgpu_gfx90a::s80, output_vec_len ); + case 81: return makeRegisterExpression(amdgpu_gfx90a::s81, output_vec_len ); + case 82: return makeRegisterExpression(amdgpu_gfx90a::s82, output_vec_len ); + case 83: return makeRegisterExpression(amdgpu_gfx90a::s83, output_vec_len ); + case 84: return makeRegisterExpression(amdgpu_gfx90a::s84, output_vec_len ); + case 85: return makeRegisterExpression(amdgpu_gfx90a::s85, output_vec_len ); + case 86: return makeRegisterExpression(amdgpu_gfx90a::s86, output_vec_len ); + case 87: return makeRegisterExpression(amdgpu_gfx90a::s87, output_vec_len ); + case 88: return makeRegisterExpression(amdgpu_gfx90a::s88, output_vec_len ); + case 89: return makeRegisterExpression(amdgpu_gfx90a::s89, output_vec_len ); + case 90: return makeRegisterExpression(amdgpu_gfx90a::s90, output_vec_len ); + case 91: return makeRegisterExpression(amdgpu_gfx90a::s91, output_vec_len ); + case 92: return makeRegisterExpression(amdgpu_gfx90a::s92, output_vec_len ); + case 93: return makeRegisterExpression(amdgpu_gfx90a::s93, output_vec_len ); + case 94: return makeRegisterExpression(amdgpu_gfx90a::s94, output_vec_len ); + case 95: return makeRegisterExpression(amdgpu_gfx90a::s95, output_vec_len ); + case 96: return makeRegisterExpression(amdgpu_gfx90a::s96, output_vec_len ); + case 97: return makeRegisterExpression(amdgpu_gfx90a::s97, output_vec_len ); + case 98: return makeRegisterExpression(amdgpu_gfx90a::s98, output_vec_len ); + case 99: return makeRegisterExpression(amdgpu_gfx90a::s99, output_vec_len ); + case 100: return makeRegisterExpression(amdgpu_gfx90a::s100, output_vec_len ); + case 101: return makeRegisterExpression(amdgpu_gfx90a::s101, output_vec_len ); + case 104: return makeRegisterExpression(amdgpu_gfx90a::xnack_mask_lo, output_vec_len ); + case 105: return makeRegisterExpression(amdgpu_gfx90a::xnack_mask_hi, output_vec_len ); + case 102: return makeRegisterExpression(amdgpu_gfx90a::flat_scratch_lo, output_vec_len ); + case 103: return makeRegisterExpression(amdgpu_gfx90a::flat_scratch_hi, output_vec_len ); + case 108: return makeRegisterExpression(amdgpu_gfx90a::ttmp0, output_vec_len ); + case 109: return makeRegisterExpression(amdgpu_gfx90a::ttmp1, output_vec_len ); + case 110: return makeRegisterExpression(amdgpu_gfx90a::ttmp2, output_vec_len ); + case 111: return makeRegisterExpression(amdgpu_gfx90a::ttmp3, output_vec_len ); + case 112: return makeRegisterExpression(amdgpu_gfx90a::ttmp4, output_vec_len ); + case 113: return makeRegisterExpression(amdgpu_gfx90a::ttmp5, output_vec_len ); + case 114: return makeRegisterExpression(amdgpu_gfx90a::ttmp6, output_vec_len ); + case 115: return makeRegisterExpression(amdgpu_gfx90a::ttmp7, output_vec_len ); + case 116: return makeRegisterExpression(amdgpu_gfx90a::ttmp8, output_vec_len ); + case 117: return makeRegisterExpression(amdgpu_gfx90a::ttmp9, output_vec_len ); + case 118: return makeRegisterExpression(amdgpu_gfx90a::ttmp10, output_vec_len ); + case 119: return makeRegisterExpression(amdgpu_gfx90a::ttmp11, output_vec_len ); + case 120: return makeRegisterExpression(amdgpu_gfx90a::ttmp12, output_vec_len ); + case 121: return makeRegisterExpression(amdgpu_gfx90a::ttmp13, output_vec_len ); + case 122: return makeRegisterExpression(amdgpu_gfx90a::ttmp14, output_vec_len ); + case 123: return makeRegisterExpression(amdgpu_gfx90a::ttmp15, output_vec_len ); + case 106: return makeRegisterExpression(amdgpu_gfx90a::vcc_lo, output_vec_len ); + case 107: return makeRegisterExpression(amdgpu_gfx90a::vcc_hi, output_vec_len ); + case 124: return makeRegisterExpression(amdgpu_gfx90a::m0, output_vec_len ); + case 126: return makeRegisterExpression(amdgpu_gfx90a::exec_lo, output_vec_len ); + case 127: return makeRegisterExpression(amdgpu_gfx90a::exec_hi, output_vec_len ); + case 128: return Immediate::makeImmediate(Result(u32, 0)); + case 129: return Immediate::makeImmediate(Result(u32, 1)); + case 130: return Immediate::makeImmediate(Result(u32, 2)); + case 131: return Immediate::makeImmediate(Result(u32, 3)); + case 132: return Immediate::makeImmediate(Result(u32, 4)); + case 133: return Immediate::makeImmediate(Result(u32, 5)); + case 134: return Immediate::makeImmediate(Result(u32, 6)); + case 135: return Immediate::makeImmediate(Result(u32, 7)); + case 136: return Immediate::makeImmediate(Result(u32, 8)); + case 137: return Immediate::makeImmediate(Result(u32, 9)); + case 138: return Immediate::makeImmediate(Result(u32, 10)); + case 139: return Immediate::makeImmediate(Result(u32, 11)); + case 140: return Immediate::makeImmediate(Result(u32, 12)); + case 141: return Immediate::makeImmediate(Result(u32, 13)); + case 142: return Immediate::makeImmediate(Result(u32, 14)); + case 143: return Immediate::makeImmediate(Result(u32, 15)); + case 144: return Immediate::makeImmediate(Result(u32, 16)); + case 145: return Immediate::makeImmediate(Result(u32, 17)); + case 146: return Immediate::makeImmediate(Result(u32, 18)); + case 147: return Immediate::makeImmediate(Result(u32, 19)); + case 148: return Immediate::makeImmediate(Result(u32, 20)); + case 149: return Immediate::makeImmediate(Result(u32, 21)); + case 150: return Immediate::makeImmediate(Result(u32, 22)); + case 151: return Immediate::makeImmediate(Result(u32, 23)); + case 152: return Immediate::makeImmediate(Result(u32, 24)); + case 153: return Immediate::makeImmediate(Result(u32, 25)); + case 154: return Immediate::makeImmediate(Result(u32, 26)); + case 155: return Immediate::makeImmediate(Result(u32, 27)); + case 156: return Immediate::makeImmediate(Result(u32, 28)); + case 157: return Immediate::makeImmediate(Result(u32, 29)); + case 158: return Immediate::makeImmediate(Result(u32, 30)); + case 159: return Immediate::makeImmediate(Result(u32, 31)); + case 160: return Immediate::makeImmediate(Result(u32, 32)); + case 161: return Immediate::makeImmediate(Result(u32, 33)); + case 162: return Immediate::makeImmediate(Result(u32, 34)); + case 163: return Immediate::makeImmediate(Result(u32, 35)); + case 164: return Immediate::makeImmediate(Result(u32, 36)); + case 165: return Immediate::makeImmediate(Result(u32, 37)); + case 166: return Immediate::makeImmediate(Result(u32, 38)); + case 167: return Immediate::makeImmediate(Result(u32, 39)); + case 168: return Immediate::makeImmediate(Result(u32, 40)); + case 169: return Immediate::makeImmediate(Result(u32, 41)); + case 170: return Immediate::makeImmediate(Result(u32, 42)); + case 171: return Immediate::makeImmediate(Result(u32, 43)); + case 172: return Immediate::makeImmediate(Result(u32, 44)); + case 173: return Immediate::makeImmediate(Result(u32, 45)); + case 174: return Immediate::makeImmediate(Result(u32, 46)); + case 175: return Immediate::makeImmediate(Result(u32, 47)); + case 176: return Immediate::makeImmediate(Result(u32, 48)); + case 177: return Immediate::makeImmediate(Result(u32, 49)); + case 178: return Immediate::makeImmediate(Result(u32, 50)); + case 179: return Immediate::makeImmediate(Result(u32, 51)); + case 180: return Immediate::makeImmediate(Result(u32, 52)); + case 181: return Immediate::makeImmediate(Result(u32, 53)); + case 182: return Immediate::makeImmediate(Result(u32, 54)); + case 183: return Immediate::makeImmediate(Result(u32, 55)); + case 184: return Immediate::makeImmediate(Result(u32, 56)); + case 185: return Immediate::makeImmediate(Result(u32, 57)); + case 186: return Immediate::makeImmediate(Result(u32, 58)); + case 187: return Immediate::makeImmediate(Result(u32, 59)); + case 188: return Immediate::makeImmediate(Result(u32, 60)); + case 189: return Immediate::makeImmediate(Result(u32, 61)); + case 190: return Immediate::makeImmediate(Result(u32, 62)); + case 191: return Immediate::makeImmediate(Result(u32, 63)); + case 192: return Immediate::makeImmediate(Result(u32, 64)); + case 193: return Immediate::makeImmediate(Result(u32, -1)); + case 194: return Immediate::makeImmediate(Result(u32, -2)); + case 195: return Immediate::makeImmediate(Result(u32, -3)); + case 196: return Immediate::makeImmediate(Result(u32, -4)); + case 197: return Immediate::makeImmediate(Result(u32, -5)); + case 198: return Immediate::makeImmediate(Result(u32, -6)); + case 199: return Immediate::makeImmediate(Result(u32, -7)); + case 200: return Immediate::makeImmediate(Result(u32, -8)); + case 201: return Immediate::makeImmediate(Result(u32, -9)); + case 202: return Immediate::makeImmediate(Result(u32, -10)); + case 203: return Immediate::makeImmediate(Result(u32, -11)); + case 204: return Immediate::makeImmediate(Result(u32, -12)); + case 205: return Immediate::makeImmediate(Result(u32, -13)); + case 206: return Immediate::makeImmediate(Result(u32, -14)); + case 207: return Immediate::makeImmediate(Result(u32, -15)); + case 208: return Immediate::makeImmediate(Result(u32, -16)); + case 240: return Immediate::makeImmediate(Result(sp_float, 0.5)); + case 241: return Immediate::makeImmediate(Result(sp_float, -0.5)); + case 242: return Immediate::makeImmediate(Result(sp_float, 1.0)); + case 243: return Immediate::makeImmediate(Result(sp_float, -1.0)); + case 244: return Immediate::makeImmediate(Result(sp_float, 2.0)); + case 245: return Immediate::makeImmediate(Result(sp_float, -2.0)); + case 246: return Immediate::makeImmediate(Result(sp_float, 4.0)); + case 247: return Immediate::makeImmediate(Result(sp_float, -4.0)); + case 248: return Immediate::makeImmediate(Result(sp_float, 0.15915494)); + case 251: return makeRegisterExpression(amdgpu_gfx90a::src_vccz, output_vec_len ); + case 252: return makeRegisterExpression(amdgpu_gfx90a::src_execz, output_vec_len ); + case 253: return makeRegisterExpression(amdgpu_gfx90a::src_scc, output_vec_len ); + case 235: return makeRegisterExpression(amdgpu_gfx90a::src_shared_base, output_vec_len ); + case 236: return makeRegisterExpression(amdgpu_gfx90a::src_shared_limit, output_vec_len ); + case 237: return makeRegisterExpression(amdgpu_gfx90a::src_private_base, output_vec_len ); + case 238: return makeRegisterExpression(amdgpu_gfx90a::src_private_limit, output_vec_len ); + case 239: return makeRegisterExpression(amdgpu_gfx90a::src_pops_exiting_wave_id, output_vec_len ); + case 255: return Immediate::makeImmediate(Result(u32,decodeOPR_LITERAL())); + case 249 : return decodeOPR_SDWA(); + default: return makeRegisterExpression(amdgpu_gfx90a::invalid); + } + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx90a::decodeOPR_SSRC_LANESEL(uint64_t input, uint32_t output_vec_len) + { + switch (input) { + case 0: return makeRegisterExpression(amdgpu_gfx90a::s0, output_vec_len ); + case 1: return makeRegisterExpression(amdgpu_gfx90a::s1, output_vec_len ); + case 2: return makeRegisterExpression(amdgpu_gfx90a::s2, output_vec_len ); + case 3: return makeRegisterExpression(amdgpu_gfx90a::s3, output_vec_len ); + case 4: return makeRegisterExpression(amdgpu_gfx90a::s4, output_vec_len ); + case 5: return makeRegisterExpression(amdgpu_gfx90a::s5, output_vec_len ); + case 6: return makeRegisterExpression(amdgpu_gfx90a::s6, output_vec_len ); + case 7: return makeRegisterExpression(amdgpu_gfx90a::s7, output_vec_len ); + case 8: return makeRegisterExpression(amdgpu_gfx90a::s8, output_vec_len ); + case 9: return makeRegisterExpression(amdgpu_gfx90a::s9, output_vec_len ); + case 10: return makeRegisterExpression(amdgpu_gfx90a::s10, output_vec_len ); + case 11: return makeRegisterExpression(amdgpu_gfx90a::s11, output_vec_len ); + case 12: return makeRegisterExpression(amdgpu_gfx90a::s12, output_vec_len ); + case 13: return makeRegisterExpression(amdgpu_gfx90a::s13, output_vec_len ); + case 14: return makeRegisterExpression(amdgpu_gfx90a::s14, output_vec_len ); + case 15: return makeRegisterExpression(amdgpu_gfx90a::s15, output_vec_len ); + case 16: return makeRegisterExpression(amdgpu_gfx90a::s16, output_vec_len ); + case 17: return makeRegisterExpression(amdgpu_gfx90a::s17, output_vec_len ); + case 18: return makeRegisterExpression(amdgpu_gfx90a::s18, output_vec_len ); + case 19: return makeRegisterExpression(amdgpu_gfx90a::s19, output_vec_len ); + case 20: return makeRegisterExpression(amdgpu_gfx90a::s20, output_vec_len ); + case 21: return makeRegisterExpression(amdgpu_gfx90a::s21, output_vec_len ); + case 22: return makeRegisterExpression(amdgpu_gfx90a::s22, output_vec_len ); + case 23: return makeRegisterExpression(amdgpu_gfx90a::s23, output_vec_len ); + case 24: return makeRegisterExpression(amdgpu_gfx90a::s24, output_vec_len ); + case 25: return makeRegisterExpression(amdgpu_gfx90a::s25, output_vec_len ); + case 26: return makeRegisterExpression(amdgpu_gfx90a::s26, output_vec_len ); + case 27: return makeRegisterExpression(amdgpu_gfx90a::s27, output_vec_len ); + case 28: return makeRegisterExpression(amdgpu_gfx90a::s28, output_vec_len ); + case 29: return makeRegisterExpression(amdgpu_gfx90a::s29, output_vec_len ); + case 30: return makeRegisterExpression(amdgpu_gfx90a::s30, output_vec_len ); + case 31: return makeRegisterExpression(amdgpu_gfx90a::s31, output_vec_len ); + case 32: return makeRegisterExpression(amdgpu_gfx90a::s32, output_vec_len ); + case 33: return makeRegisterExpression(amdgpu_gfx90a::s33, output_vec_len ); + case 34: return makeRegisterExpression(amdgpu_gfx90a::s34, output_vec_len ); + case 35: return makeRegisterExpression(amdgpu_gfx90a::s35, output_vec_len ); + case 36: return makeRegisterExpression(amdgpu_gfx90a::s36, output_vec_len ); + case 37: return makeRegisterExpression(amdgpu_gfx90a::s37, output_vec_len ); + case 38: return makeRegisterExpression(amdgpu_gfx90a::s38, output_vec_len ); + case 39: return makeRegisterExpression(amdgpu_gfx90a::s39, output_vec_len ); + case 40: return makeRegisterExpression(amdgpu_gfx90a::s40, output_vec_len ); + case 41: return makeRegisterExpression(amdgpu_gfx90a::s41, output_vec_len ); + case 42: return makeRegisterExpression(amdgpu_gfx90a::s42, output_vec_len ); + case 43: return makeRegisterExpression(amdgpu_gfx90a::s43, output_vec_len ); + case 44: return makeRegisterExpression(amdgpu_gfx90a::s44, output_vec_len ); + case 45: return makeRegisterExpression(amdgpu_gfx90a::s45, output_vec_len ); + case 46: return makeRegisterExpression(amdgpu_gfx90a::s46, output_vec_len ); + case 47: return makeRegisterExpression(amdgpu_gfx90a::s47, output_vec_len ); + case 48: return makeRegisterExpression(amdgpu_gfx90a::s48, output_vec_len ); + case 49: return makeRegisterExpression(amdgpu_gfx90a::s49, output_vec_len ); + case 50: return makeRegisterExpression(amdgpu_gfx90a::s50, output_vec_len ); + case 51: return makeRegisterExpression(amdgpu_gfx90a::s51, output_vec_len ); + case 52: return makeRegisterExpression(amdgpu_gfx90a::s52, output_vec_len ); + case 53: return makeRegisterExpression(amdgpu_gfx90a::s53, output_vec_len ); + case 54: return makeRegisterExpression(amdgpu_gfx90a::s54, output_vec_len ); + case 55: return makeRegisterExpression(amdgpu_gfx90a::s55, output_vec_len ); + case 56: return makeRegisterExpression(amdgpu_gfx90a::s56, output_vec_len ); + case 57: return makeRegisterExpression(amdgpu_gfx90a::s57, output_vec_len ); + case 58: return makeRegisterExpression(amdgpu_gfx90a::s58, output_vec_len ); + case 59: return makeRegisterExpression(amdgpu_gfx90a::s59, output_vec_len ); + case 60: return makeRegisterExpression(amdgpu_gfx90a::s60, output_vec_len ); + case 61: return makeRegisterExpression(amdgpu_gfx90a::s61, output_vec_len ); + case 62: return makeRegisterExpression(amdgpu_gfx90a::s62, output_vec_len ); + case 63: return makeRegisterExpression(amdgpu_gfx90a::s63, output_vec_len ); + case 64: return makeRegisterExpression(amdgpu_gfx90a::s64, output_vec_len ); + case 65: return makeRegisterExpression(amdgpu_gfx90a::s65, output_vec_len ); + case 66: return makeRegisterExpression(amdgpu_gfx90a::s66, output_vec_len ); + case 67: return makeRegisterExpression(amdgpu_gfx90a::s67, output_vec_len ); + case 68: return makeRegisterExpression(amdgpu_gfx90a::s68, output_vec_len ); + case 69: return makeRegisterExpression(amdgpu_gfx90a::s69, output_vec_len ); + case 70: return makeRegisterExpression(amdgpu_gfx90a::s70, output_vec_len ); + case 71: return makeRegisterExpression(amdgpu_gfx90a::s71, output_vec_len ); + case 72: return makeRegisterExpression(amdgpu_gfx90a::s72, output_vec_len ); + case 73: return makeRegisterExpression(amdgpu_gfx90a::s73, output_vec_len ); + case 74: return makeRegisterExpression(amdgpu_gfx90a::s74, output_vec_len ); + case 75: return makeRegisterExpression(amdgpu_gfx90a::s75, output_vec_len ); + case 76: return makeRegisterExpression(amdgpu_gfx90a::s76, output_vec_len ); + case 77: return makeRegisterExpression(amdgpu_gfx90a::s77, output_vec_len ); + case 78: return makeRegisterExpression(amdgpu_gfx90a::s78, output_vec_len ); + case 79: return makeRegisterExpression(amdgpu_gfx90a::s79, output_vec_len ); + case 80: return makeRegisterExpression(amdgpu_gfx90a::s80, output_vec_len ); + case 81: return makeRegisterExpression(amdgpu_gfx90a::s81, output_vec_len ); + case 82: return makeRegisterExpression(amdgpu_gfx90a::s82, output_vec_len ); + case 83: return makeRegisterExpression(amdgpu_gfx90a::s83, output_vec_len ); + case 84: return makeRegisterExpression(amdgpu_gfx90a::s84, output_vec_len ); + case 85: return makeRegisterExpression(amdgpu_gfx90a::s85, output_vec_len ); + case 86: return makeRegisterExpression(amdgpu_gfx90a::s86, output_vec_len ); + case 87: return makeRegisterExpression(amdgpu_gfx90a::s87, output_vec_len ); + case 88: return makeRegisterExpression(amdgpu_gfx90a::s88, output_vec_len ); + case 89: return makeRegisterExpression(amdgpu_gfx90a::s89, output_vec_len ); + case 90: return makeRegisterExpression(amdgpu_gfx90a::s90, output_vec_len ); + case 91: return makeRegisterExpression(amdgpu_gfx90a::s91, output_vec_len ); + case 92: return makeRegisterExpression(amdgpu_gfx90a::s92, output_vec_len ); + case 93: return makeRegisterExpression(amdgpu_gfx90a::s93, output_vec_len ); + case 94: return makeRegisterExpression(amdgpu_gfx90a::s94, output_vec_len ); + case 95: return makeRegisterExpression(amdgpu_gfx90a::s95, output_vec_len ); + case 96: return makeRegisterExpression(amdgpu_gfx90a::s96, output_vec_len ); + case 97: return makeRegisterExpression(amdgpu_gfx90a::s97, output_vec_len ); + case 98: return makeRegisterExpression(amdgpu_gfx90a::s98, output_vec_len ); + case 99: return makeRegisterExpression(amdgpu_gfx90a::s99, output_vec_len ); + case 100: return makeRegisterExpression(amdgpu_gfx90a::s100, output_vec_len ); + case 101: return makeRegisterExpression(amdgpu_gfx90a::s101, output_vec_len ); + case 104: return makeRegisterExpression(amdgpu_gfx90a::xnack_mask_lo, output_vec_len ); + case 105: return makeRegisterExpression(amdgpu_gfx90a::xnack_mask_hi, output_vec_len ); + case 102: return makeRegisterExpression(amdgpu_gfx90a::flat_scratch_lo, output_vec_len ); + case 103: return makeRegisterExpression(amdgpu_gfx90a::flat_scratch_hi, output_vec_len ); + case 108: return makeRegisterExpression(amdgpu_gfx90a::ttmp0, output_vec_len ); + case 109: return makeRegisterExpression(amdgpu_gfx90a::ttmp1, output_vec_len ); + case 110: return makeRegisterExpression(amdgpu_gfx90a::ttmp2, output_vec_len ); + case 111: return makeRegisterExpression(amdgpu_gfx90a::ttmp3, output_vec_len ); + case 112: return makeRegisterExpression(amdgpu_gfx90a::ttmp4, output_vec_len ); + case 113: return makeRegisterExpression(amdgpu_gfx90a::ttmp5, output_vec_len ); + case 114: return makeRegisterExpression(amdgpu_gfx90a::ttmp6, output_vec_len ); + case 115: return makeRegisterExpression(amdgpu_gfx90a::ttmp7, output_vec_len ); + case 116: return makeRegisterExpression(amdgpu_gfx90a::ttmp8, output_vec_len ); + case 117: return makeRegisterExpression(amdgpu_gfx90a::ttmp9, output_vec_len ); + case 118: return makeRegisterExpression(amdgpu_gfx90a::ttmp10, output_vec_len ); + case 119: return makeRegisterExpression(amdgpu_gfx90a::ttmp11, output_vec_len ); + case 120: return makeRegisterExpression(amdgpu_gfx90a::ttmp12, output_vec_len ); + case 121: return makeRegisterExpression(amdgpu_gfx90a::ttmp13, output_vec_len ); + case 122: return makeRegisterExpression(amdgpu_gfx90a::ttmp14, output_vec_len ); + case 123: return makeRegisterExpression(amdgpu_gfx90a::ttmp15, output_vec_len ); + case 106: return makeRegisterExpression(amdgpu_gfx90a::vcc_lo, output_vec_len ); + case 107: return makeRegisterExpression(amdgpu_gfx90a::vcc_hi, output_vec_len ); + case 124: return makeRegisterExpression(amdgpu_gfx90a::m0, output_vec_len ); + case 128: return Immediate::makeImmediate(Result(u32, 0)); + case 129: return Immediate::makeImmediate(Result(u32, 1)); + case 130: return Immediate::makeImmediate(Result(u32, 2)); + case 131: return Immediate::makeImmediate(Result(u32, 3)); + case 132: return Immediate::makeImmediate(Result(u32, 4)); + case 133: return Immediate::makeImmediate(Result(u32, 5)); + case 134: return Immediate::makeImmediate(Result(u32, 6)); + case 135: return Immediate::makeImmediate(Result(u32, 7)); + case 136: return Immediate::makeImmediate(Result(u32, 8)); + case 137: return Immediate::makeImmediate(Result(u32, 9)); + case 138: return Immediate::makeImmediate(Result(u32, 10)); + case 139: return Immediate::makeImmediate(Result(u32, 11)); + case 140: return Immediate::makeImmediate(Result(u32, 12)); + case 141: return Immediate::makeImmediate(Result(u32, 13)); + case 142: return Immediate::makeImmediate(Result(u32, 14)); + case 143: return Immediate::makeImmediate(Result(u32, 15)); + case 144: return Immediate::makeImmediate(Result(u32, 16)); + case 145: return Immediate::makeImmediate(Result(u32, 17)); + case 146: return Immediate::makeImmediate(Result(u32, 18)); + case 147: return Immediate::makeImmediate(Result(u32, 19)); + case 148: return Immediate::makeImmediate(Result(u32, 20)); + case 149: return Immediate::makeImmediate(Result(u32, 21)); + case 150: return Immediate::makeImmediate(Result(u32, 22)); + case 151: return Immediate::makeImmediate(Result(u32, 23)); + case 152: return Immediate::makeImmediate(Result(u32, 24)); + case 153: return Immediate::makeImmediate(Result(u32, 25)); + case 154: return Immediate::makeImmediate(Result(u32, 26)); + case 155: return Immediate::makeImmediate(Result(u32, 27)); + case 156: return Immediate::makeImmediate(Result(u32, 28)); + case 157: return Immediate::makeImmediate(Result(u32, 29)); + case 158: return Immediate::makeImmediate(Result(u32, 30)); + case 159: return Immediate::makeImmediate(Result(u32, 31)); + case 160: return Immediate::makeImmediate(Result(u32, 32)); + case 161: return Immediate::makeImmediate(Result(u32, 33)); + case 162: return Immediate::makeImmediate(Result(u32, 34)); + case 163: return Immediate::makeImmediate(Result(u32, 35)); + case 164: return Immediate::makeImmediate(Result(u32, 36)); + case 165: return Immediate::makeImmediate(Result(u32, 37)); + case 166: return Immediate::makeImmediate(Result(u32, 38)); + case 167: return Immediate::makeImmediate(Result(u32, 39)); + case 168: return Immediate::makeImmediate(Result(u32, 40)); + case 169: return Immediate::makeImmediate(Result(u32, 41)); + case 170: return Immediate::makeImmediate(Result(u32, 42)); + case 171: return Immediate::makeImmediate(Result(u32, 43)); + case 172: return Immediate::makeImmediate(Result(u32, 44)); + case 173: return Immediate::makeImmediate(Result(u32, 45)); + case 174: return Immediate::makeImmediate(Result(u32, 46)); + case 175: return Immediate::makeImmediate(Result(u32, 47)); + case 176: return Immediate::makeImmediate(Result(u32, 48)); + case 177: return Immediate::makeImmediate(Result(u32, 49)); + case 178: return Immediate::makeImmediate(Result(u32, 50)); + case 179: return Immediate::makeImmediate(Result(u32, 51)); + case 180: return Immediate::makeImmediate(Result(u32, 52)); + case 181: return Immediate::makeImmediate(Result(u32, 53)); + case 182: return Immediate::makeImmediate(Result(u32, 54)); + case 183: return Immediate::makeImmediate(Result(u32, 55)); + case 184: return Immediate::makeImmediate(Result(u32, 56)); + case 185: return Immediate::makeImmediate(Result(u32, 57)); + case 186: return Immediate::makeImmediate(Result(u32, 58)); + case 187: return Immediate::makeImmediate(Result(u32, 59)); + case 188: return Immediate::makeImmediate(Result(u32, 60)); + case 189: return Immediate::makeImmediate(Result(u32, 61)); + case 190: return Immediate::makeImmediate(Result(u32, 62)); + case 191: return Immediate::makeImmediate(Result(u32, 63)); + default: return makeRegisterExpression(amdgpu_gfx90a::invalid); + } + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx90a::decodeOPR_SSRC_NOLIT(uint64_t input, uint32_t output_vec_len) + { + switch (input) { + case 0: return makeRegisterExpression(amdgpu_gfx90a::s0, output_vec_len ); + case 1: return makeRegisterExpression(amdgpu_gfx90a::s1, output_vec_len ); + case 2: return makeRegisterExpression(amdgpu_gfx90a::s2, output_vec_len ); + case 3: return makeRegisterExpression(amdgpu_gfx90a::s3, output_vec_len ); + case 4: return makeRegisterExpression(amdgpu_gfx90a::s4, output_vec_len ); + case 5: return makeRegisterExpression(amdgpu_gfx90a::s5, output_vec_len ); + case 6: return makeRegisterExpression(amdgpu_gfx90a::s6, output_vec_len ); + case 7: return makeRegisterExpression(amdgpu_gfx90a::s7, output_vec_len ); + case 8: return makeRegisterExpression(amdgpu_gfx90a::s8, output_vec_len ); + case 9: return makeRegisterExpression(amdgpu_gfx90a::s9, output_vec_len ); + case 10: return makeRegisterExpression(amdgpu_gfx90a::s10, output_vec_len ); + case 11: return makeRegisterExpression(amdgpu_gfx90a::s11, output_vec_len ); + case 12: return makeRegisterExpression(amdgpu_gfx90a::s12, output_vec_len ); + case 13: return makeRegisterExpression(amdgpu_gfx90a::s13, output_vec_len ); + case 14: return makeRegisterExpression(amdgpu_gfx90a::s14, output_vec_len ); + case 15: return makeRegisterExpression(amdgpu_gfx90a::s15, output_vec_len ); + case 16: return makeRegisterExpression(amdgpu_gfx90a::s16, output_vec_len ); + case 17: return makeRegisterExpression(amdgpu_gfx90a::s17, output_vec_len ); + case 18: return makeRegisterExpression(amdgpu_gfx90a::s18, output_vec_len ); + case 19: return makeRegisterExpression(amdgpu_gfx90a::s19, output_vec_len ); + case 20: return makeRegisterExpression(amdgpu_gfx90a::s20, output_vec_len ); + case 21: return makeRegisterExpression(amdgpu_gfx90a::s21, output_vec_len ); + case 22: return makeRegisterExpression(amdgpu_gfx90a::s22, output_vec_len ); + case 23: return makeRegisterExpression(amdgpu_gfx90a::s23, output_vec_len ); + case 24: return makeRegisterExpression(amdgpu_gfx90a::s24, output_vec_len ); + case 25: return makeRegisterExpression(amdgpu_gfx90a::s25, output_vec_len ); + case 26: return makeRegisterExpression(amdgpu_gfx90a::s26, output_vec_len ); + case 27: return makeRegisterExpression(amdgpu_gfx90a::s27, output_vec_len ); + case 28: return makeRegisterExpression(amdgpu_gfx90a::s28, output_vec_len ); + case 29: return makeRegisterExpression(amdgpu_gfx90a::s29, output_vec_len ); + case 30: return makeRegisterExpression(amdgpu_gfx90a::s30, output_vec_len ); + case 31: return makeRegisterExpression(amdgpu_gfx90a::s31, output_vec_len ); + case 32: return makeRegisterExpression(amdgpu_gfx90a::s32, output_vec_len ); + case 33: return makeRegisterExpression(amdgpu_gfx90a::s33, output_vec_len ); + case 34: return makeRegisterExpression(amdgpu_gfx90a::s34, output_vec_len ); + case 35: return makeRegisterExpression(amdgpu_gfx90a::s35, output_vec_len ); + case 36: return makeRegisterExpression(amdgpu_gfx90a::s36, output_vec_len ); + case 37: return makeRegisterExpression(amdgpu_gfx90a::s37, output_vec_len ); + case 38: return makeRegisterExpression(amdgpu_gfx90a::s38, output_vec_len ); + case 39: return makeRegisterExpression(amdgpu_gfx90a::s39, output_vec_len ); + case 40: return makeRegisterExpression(amdgpu_gfx90a::s40, output_vec_len ); + case 41: return makeRegisterExpression(amdgpu_gfx90a::s41, output_vec_len ); + case 42: return makeRegisterExpression(amdgpu_gfx90a::s42, output_vec_len ); + case 43: return makeRegisterExpression(amdgpu_gfx90a::s43, output_vec_len ); + case 44: return makeRegisterExpression(amdgpu_gfx90a::s44, output_vec_len ); + case 45: return makeRegisterExpression(amdgpu_gfx90a::s45, output_vec_len ); + case 46: return makeRegisterExpression(amdgpu_gfx90a::s46, output_vec_len ); + case 47: return makeRegisterExpression(amdgpu_gfx90a::s47, output_vec_len ); + case 48: return makeRegisterExpression(amdgpu_gfx90a::s48, output_vec_len ); + case 49: return makeRegisterExpression(amdgpu_gfx90a::s49, output_vec_len ); + case 50: return makeRegisterExpression(amdgpu_gfx90a::s50, output_vec_len ); + case 51: return makeRegisterExpression(amdgpu_gfx90a::s51, output_vec_len ); + case 52: return makeRegisterExpression(amdgpu_gfx90a::s52, output_vec_len ); + case 53: return makeRegisterExpression(amdgpu_gfx90a::s53, output_vec_len ); + case 54: return makeRegisterExpression(amdgpu_gfx90a::s54, output_vec_len ); + case 55: return makeRegisterExpression(amdgpu_gfx90a::s55, output_vec_len ); + case 56: return makeRegisterExpression(amdgpu_gfx90a::s56, output_vec_len ); + case 57: return makeRegisterExpression(amdgpu_gfx90a::s57, output_vec_len ); + case 58: return makeRegisterExpression(amdgpu_gfx90a::s58, output_vec_len ); + case 59: return makeRegisterExpression(amdgpu_gfx90a::s59, output_vec_len ); + case 60: return makeRegisterExpression(amdgpu_gfx90a::s60, output_vec_len ); + case 61: return makeRegisterExpression(amdgpu_gfx90a::s61, output_vec_len ); + case 62: return makeRegisterExpression(amdgpu_gfx90a::s62, output_vec_len ); + case 63: return makeRegisterExpression(amdgpu_gfx90a::s63, output_vec_len ); + case 64: return makeRegisterExpression(amdgpu_gfx90a::s64, output_vec_len ); + case 65: return makeRegisterExpression(amdgpu_gfx90a::s65, output_vec_len ); + case 66: return makeRegisterExpression(amdgpu_gfx90a::s66, output_vec_len ); + case 67: return makeRegisterExpression(amdgpu_gfx90a::s67, output_vec_len ); + case 68: return makeRegisterExpression(amdgpu_gfx90a::s68, output_vec_len ); + case 69: return makeRegisterExpression(amdgpu_gfx90a::s69, output_vec_len ); + case 70: return makeRegisterExpression(amdgpu_gfx90a::s70, output_vec_len ); + case 71: return makeRegisterExpression(amdgpu_gfx90a::s71, output_vec_len ); + case 72: return makeRegisterExpression(amdgpu_gfx90a::s72, output_vec_len ); + case 73: return makeRegisterExpression(amdgpu_gfx90a::s73, output_vec_len ); + case 74: return makeRegisterExpression(amdgpu_gfx90a::s74, output_vec_len ); + case 75: return makeRegisterExpression(amdgpu_gfx90a::s75, output_vec_len ); + case 76: return makeRegisterExpression(amdgpu_gfx90a::s76, output_vec_len ); + case 77: return makeRegisterExpression(amdgpu_gfx90a::s77, output_vec_len ); + case 78: return makeRegisterExpression(amdgpu_gfx90a::s78, output_vec_len ); + case 79: return makeRegisterExpression(amdgpu_gfx90a::s79, output_vec_len ); + case 80: return makeRegisterExpression(amdgpu_gfx90a::s80, output_vec_len ); + case 81: return makeRegisterExpression(amdgpu_gfx90a::s81, output_vec_len ); + case 82: return makeRegisterExpression(amdgpu_gfx90a::s82, output_vec_len ); + case 83: return makeRegisterExpression(amdgpu_gfx90a::s83, output_vec_len ); + case 84: return makeRegisterExpression(amdgpu_gfx90a::s84, output_vec_len ); + case 85: return makeRegisterExpression(amdgpu_gfx90a::s85, output_vec_len ); + case 86: return makeRegisterExpression(amdgpu_gfx90a::s86, output_vec_len ); + case 87: return makeRegisterExpression(amdgpu_gfx90a::s87, output_vec_len ); + case 88: return makeRegisterExpression(amdgpu_gfx90a::s88, output_vec_len ); + case 89: return makeRegisterExpression(amdgpu_gfx90a::s89, output_vec_len ); + case 90: return makeRegisterExpression(amdgpu_gfx90a::s90, output_vec_len ); + case 91: return makeRegisterExpression(amdgpu_gfx90a::s91, output_vec_len ); + case 92: return makeRegisterExpression(amdgpu_gfx90a::s92, output_vec_len ); + case 93: return makeRegisterExpression(amdgpu_gfx90a::s93, output_vec_len ); + case 94: return makeRegisterExpression(amdgpu_gfx90a::s94, output_vec_len ); + case 95: return makeRegisterExpression(amdgpu_gfx90a::s95, output_vec_len ); + case 96: return makeRegisterExpression(amdgpu_gfx90a::s96, output_vec_len ); + case 97: return makeRegisterExpression(amdgpu_gfx90a::s97, output_vec_len ); + case 98: return makeRegisterExpression(amdgpu_gfx90a::s98, output_vec_len ); + case 99: return makeRegisterExpression(amdgpu_gfx90a::s99, output_vec_len ); + case 100: return makeRegisterExpression(amdgpu_gfx90a::s100, output_vec_len ); + case 101: return makeRegisterExpression(amdgpu_gfx90a::s101, output_vec_len ); + case 104: return makeRegisterExpression(amdgpu_gfx90a::xnack_mask_lo, output_vec_len ); + case 105: return makeRegisterExpression(amdgpu_gfx90a::xnack_mask_hi, output_vec_len ); + case 102: return makeRegisterExpression(amdgpu_gfx90a::flat_scratch_lo, output_vec_len ); + case 103: return makeRegisterExpression(amdgpu_gfx90a::flat_scratch_hi, output_vec_len ); + case 108: return makeRegisterExpression(amdgpu_gfx90a::ttmp0, output_vec_len ); + case 109: return makeRegisterExpression(amdgpu_gfx90a::ttmp1, output_vec_len ); + case 110: return makeRegisterExpression(amdgpu_gfx90a::ttmp2, output_vec_len ); + case 111: return makeRegisterExpression(amdgpu_gfx90a::ttmp3, output_vec_len ); + case 112: return makeRegisterExpression(amdgpu_gfx90a::ttmp4, output_vec_len ); + case 113: return makeRegisterExpression(amdgpu_gfx90a::ttmp5, output_vec_len ); + case 114: return makeRegisterExpression(amdgpu_gfx90a::ttmp6, output_vec_len ); + case 115: return makeRegisterExpression(amdgpu_gfx90a::ttmp7, output_vec_len ); + case 116: return makeRegisterExpression(amdgpu_gfx90a::ttmp8, output_vec_len ); + case 117: return makeRegisterExpression(amdgpu_gfx90a::ttmp9, output_vec_len ); + case 118: return makeRegisterExpression(amdgpu_gfx90a::ttmp10, output_vec_len ); + case 119: return makeRegisterExpression(amdgpu_gfx90a::ttmp11, output_vec_len ); + case 120: return makeRegisterExpression(amdgpu_gfx90a::ttmp12, output_vec_len ); + case 121: return makeRegisterExpression(amdgpu_gfx90a::ttmp13, output_vec_len ); + case 122: return makeRegisterExpression(amdgpu_gfx90a::ttmp14, output_vec_len ); + case 123: return makeRegisterExpression(amdgpu_gfx90a::ttmp15, output_vec_len ); + case 106: return makeRegisterExpression(amdgpu_gfx90a::vcc_lo, output_vec_len ); + case 107: return makeRegisterExpression(amdgpu_gfx90a::vcc_hi, output_vec_len ); + case 124: return makeRegisterExpression(amdgpu_gfx90a::m0, output_vec_len ); + case 126: return makeRegisterExpression(amdgpu_gfx90a::exec_lo, output_vec_len ); + case 127: return makeRegisterExpression(amdgpu_gfx90a::exec_hi, output_vec_len ); + case 128: return Immediate::makeImmediate(Result(u32, 0)); + case 129: return Immediate::makeImmediate(Result(u32, 1)); + case 130: return Immediate::makeImmediate(Result(u32, 2)); + case 131: return Immediate::makeImmediate(Result(u32, 3)); + case 132: return Immediate::makeImmediate(Result(u32, 4)); + case 133: return Immediate::makeImmediate(Result(u32, 5)); + case 134: return Immediate::makeImmediate(Result(u32, 6)); + case 135: return Immediate::makeImmediate(Result(u32, 7)); + case 136: return Immediate::makeImmediate(Result(u32, 8)); + case 137: return Immediate::makeImmediate(Result(u32, 9)); + case 138: return Immediate::makeImmediate(Result(u32, 10)); + case 139: return Immediate::makeImmediate(Result(u32, 11)); + case 140: return Immediate::makeImmediate(Result(u32, 12)); + case 141: return Immediate::makeImmediate(Result(u32, 13)); + case 142: return Immediate::makeImmediate(Result(u32, 14)); + case 143: return Immediate::makeImmediate(Result(u32, 15)); + case 144: return Immediate::makeImmediate(Result(u32, 16)); + case 145: return Immediate::makeImmediate(Result(u32, 17)); + case 146: return Immediate::makeImmediate(Result(u32, 18)); + case 147: return Immediate::makeImmediate(Result(u32, 19)); + case 148: return Immediate::makeImmediate(Result(u32, 20)); + case 149: return Immediate::makeImmediate(Result(u32, 21)); + case 150: return Immediate::makeImmediate(Result(u32, 22)); + case 151: return Immediate::makeImmediate(Result(u32, 23)); + case 152: return Immediate::makeImmediate(Result(u32, 24)); + case 153: return Immediate::makeImmediate(Result(u32, 25)); + case 154: return Immediate::makeImmediate(Result(u32, 26)); + case 155: return Immediate::makeImmediate(Result(u32, 27)); + case 156: return Immediate::makeImmediate(Result(u32, 28)); + case 157: return Immediate::makeImmediate(Result(u32, 29)); + case 158: return Immediate::makeImmediate(Result(u32, 30)); + case 159: return Immediate::makeImmediate(Result(u32, 31)); + case 160: return Immediate::makeImmediate(Result(u32, 32)); + case 161: return Immediate::makeImmediate(Result(u32, 33)); + case 162: return Immediate::makeImmediate(Result(u32, 34)); + case 163: return Immediate::makeImmediate(Result(u32, 35)); + case 164: return Immediate::makeImmediate(Result(u32, 36)); + case 165: return Immediate::makeImmediate(Result(u32, 37)); + case 166: return Immediate::makeImmediate(Result(u32, 38)); + case 167: return Immediate::makeImmediate(Result(u32, 39)); + case 168: return Immediate::makeImmediate(Result(u32, 40)); + case 169: return Immediate::makeImmediate(Result(u32, 41)); + case 170: return Immediate::makeImmediate(Result(u32, 42)); + case 171: return Immediate::makeImmediate(Result(u32, 43)); + case 172: return Immediate::makeImmediate(Result(u32, 44)); + case 173: return Immediate::makeImmediate(Result(u32, 45)); + case 174: return Immediate::makeImmediate(Result(u32, 46)); + case 175: return Immediate::makeImmediate(Result(u32, 47)); + case 176: return Immediate::makeImmediate(Result(u32, 48)); + case 177: return Immediate::makeImmediate(Result(u32, 49)); + case 178: return Immediate::makeImmediate(Result(u32, 50)); + case 179: return Immediate::makeImmediate(Result(u32, 51)); + case 180: return Immediate::makeImmediate(Result(u32, 52)); + case 181: return Immediate::makeImmediate(Result(u32, 53)); + case 182: return Immediate::makeImmediate(Result(u32, 54)); + case 183: return Immediate::makeImmediate(Result(u32, 55)); + case 184: return Immediate::makeImmediate(Result(u32, 56)); + case 185: return Immediate::makeImmediate(Result(u32, 57)); + case 186: return Immediate::makeImmediate(Result(u32, 58)); + case 187: return Immediate::makeImmediate(Result(u32, 59)); + case 188: return Immediate::makeImmediate(Result(u32, 60)); + case 189: return Immediate::makeImmediate(Result(u32, 61)); + case 190: return Immediate::makeImmediate(Result(u32, 62)); + case 191: return Immediate::makeImmediate(Result(u32, 63)); + case 192: return Immediate::makeImmediate(Result(u32, 64)); + case 193: return Immediate::makeImmediate(Result(u32, -1)); + case 194: return Immediate::makeImmediate(Result(u32, -2)); + case 195: return Immediate::makeImmediate(Result(u32, -3)); + case 196: return Immediate::makeImmediate(Result(u32, -4)); + case 197: return Immediate::makeImmediate(Result(u32, -5)); + case 198: return Immediate::makeImmediate(Result(u32, -6)); + case 199: return Immediate::makeImmediate(Result(u32, -7)); + case 200: return Immediate::makeImmediate(Result(u32, -8)); + case 201: return Immediate::makeImmediate(Result(u32, -9)); + case 202: return Immediate::makeImmediate(Result(u32, -10)); + case 203: return Immediate::makeImmediate(Result(u32, -11)); + case 204: return Immediate::makeImmediate(Result(u32, -12)); + case 205: return Immediate::makeImmediate(Result(u32, -13)); + case 206: return Immediate::makeImmediate(Result(u32, -14)); + case 207: return Immediate::makeImmediate(Result(u32, -15)); + case 208: return Immediate::makeImmediate(Result(u32, -16)); + case 240: return Immediate::makeImmediate(Result(sp_float, 0.5)); + case 241: return Immediate::makeImmediate(Result(sp_float, -0.5)); + case 242: return Immediate::makeImmediate(Result(sp_float, 1.0)); + case 243: return Immediate::makeImmediate(Result(sp_float, -1.0)); + case 244: return Immediate::makeImmediate(Result(sp_float, 2.0)); + case 245: return Immediate::makeImmediate(Result(sp_float, -2.0)); + case 246: return Immediate::makeImmediate(Result(sp_float, 4.0)); + case 247: return Immediate::makeImmediate(Result(sp_float, -4.0)); + case 248: return Immediate::makeImmediate(Result(sp_float, 0.15915494)); + case 251: return makeRegisterExpression(amdgpu_gfx90a::src_vccz, output_vec_len ); + case 252: return makeRegisterExpression(amdgpu_gfx90a::src_execz, output_vec_len ); + case 253: return makeRegisterExpression(amdgpu_gfx90a::src_scc, output_vec_len ); + case 235: return makeRegisterExpression(amdgpu_gfx90a::src_shared_base, output_vec_len ); + case 236: return makeRegisterExpression(amdgpu_gfx90a::src_shared_limit, output_vec_len ); + case 237: return makeRegisterExpression(amdgpu_gfx90a::src_private_base, output_vec_len ); + case 238: return makeRegisterExpression(amdgpu_gfx90a::src_private_limit, output_vec_len ); + case 239: return makeRegisterExpression(amdgpu_gfx90a::src_pops_exiting_wave_id, output_vec_len ); + default: return makeRegisterExpression(amdgpu_gfx90a::invalid); + } + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx90a::decodeOPR_SSRC_SPECIAL_SCC(uint64_t input, uint32_t output_vec_len) + { + switch (input) { + case 253: return makeRegisterExpression(amdgpu_gfx90a::src_scc, output_vec_len ); + default: return makeRegisterExpression(amdgpu_gfx90a::invalid); + } + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx90a::decodeOPR_VCC(uint64_t input, uint32_t ) + { + switch (input) { + case 0: return makeRegisterExpression(amdgpu_gfx90a::vcc); + default: return makeRegisterExpression(amdgpu_gfx90a::invalid); + } + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx90a::decodeOPR_VGPR(uint64_t input, uint32_t output_vec_len) + { + switch (input) { + case 0: return makeRegisterExpression(amdgpu_gfx90a::v0, output_vec_len ); + case 1: return makeRegisterExpression(amdgpu_gfx90a::v1, output_vec_len ); + case 2: return makeRegisterExpression(amdgpu_gfx90a::v2, output_vec_len ); + case 3: return makeRegisterExpression(amdgpu_gfx90a::v3, output_vec_len ); + case 4: return makeRegisterExpression(amdgpu_gfx90a::v4, output_vec_len ); + case 5: return makeRegisterExpression(amdgpu_gfx90a::v5, output_vec_len ); + case 6: return makeRegisterExpression(amdgpu_gfx90a::v6, output_vec_len ); + case 7: return makeRegisterExpression(amdgpu_gfx90a::v7, output_vec_len ); + case 8: return makeRegisterExpression(amdgpu_gfx90a::v8, output_vec_len ); + case 9: return makeRegisterExpression(amdgpu_gfx90a::v9, output_vec_len ); + case 10: return makeRegisterExpression(amdgpu_gfx90a::v10, output_vec_len ); + case 11: return makeRegisterExpression(amdgpu_gfx90a::v11, output_vec_len ); + case 12: return makeRegisterExpression(amdgpu_gfx90a::v12, output_vec_len ); + case 13: return makeRegisterExpression(amdgpu_gfx90a::v13, output_vec_len ); + case 14: return makeRegisterExpression(amdgpu_gfx90a::v14, output_vec_len ); + case 15: return makeRegisterExpression(amdgpu_gfx90a::v15, output_vec_len ); + case 16: return makeRegisterExpression(amdgpu_gfx90a::v16, output_vec_len ); + case 17: return makeRegisterExpression(amdgpu_gfx90a::v17, output_vec_len ); + case 18: return makeRegisterExpression(amdgpu_gfx90a::v18, output_vec_len ); + case 19: return makeRegisterExpression(amdgpu_gfx90a::v19, output_vec_len ); + case 20: return makeRegisterExpression(amdgpu_gfx90a::v20, output_vec_len ); + case 21: return makeRegisterExpression(amdgpu_gfx90a::v21, output_vec_len ); + case 22: return makeRegisterExpression(amdgpu_gfx90a::v22, output_vec_len ); + case 23: return makeRegisterExpression(amdgpu_gfx90a::v23, output_vec_len ); + case 24: return makeRegisterExpression(amdgpu_gfx90a::v24, output_vec_len ); + case 25: return makeRegisterExpression(amdgpu_gfx90a::v25, output_vec_len ); + case 26: return makeRegisterExpression(amdgpu_gfx90a::v26, output_vec_len ); + case 27: return makeRegisterExpression(amdgpu_gfx90a::v27, output_vec_len ); + case 28: return makeRegisterExpression(amdgpu_gfx90a::v28, output_vec_len ); + case 29: return makeRegisterExpression(amdgpu_gfx90a::v29, output_vec_len ); + case 30: return makeRegisterExpression(amdgpu_gfx90a::v30, output_vec_len ); + case 31: return makeRegisterExpression(amdgpu_gfx90a::v31, output_vec_len ); + case 32: return makeRegisterExpression(amdgpu_gfx90a::v32, output_vec_len ); + case 33: return makeRegisterExpression(amdgpu_gfx90a::v33, output_vec_len ); + case 34: return makeRegisterExpression(amdgpu_gfx90a::v34, output_vec_len ); + case 35: return makeRegisterExpression(amdgpu_gfx90a::v35, output_vec_len ); + case 36: return makeRegisterExpression(amdgpu_gfx90a::v36, output_vec_len ); + case 37: return makeRegisterExpression(amdgpu_gfx90a::v37, output_vec_len ); + case 38: return makeRegisterExpression(amdgpu_gfx90a::v38, output_vec_len ); + case 39: return makeRegisterExpression(amdgpu_gfx90a::v39, output_vec_len ); + case 40: return makeRegisterExpression(amdgpu_gfx90a::v40, output_vec_len ); + case 41: return makeRegisterExpression(amdgpu_gfx90a::v41, output_vec_len ); + case 42: return makeRegisterExpression(amdgpu_gfx90a::v42, output_vec_len ); + case 43: return makeRegisterExpression(amdgpu_gfx90a::v43, output_vec_len ); + case 44: return makeRegisterExpression(amdgpu_gfx90a::v44, output_vec_len ); + case 45: return makeRegisterExpression(amdgpu_gfx90a::v45, output_vec_len ); + case 46: return makeRegisterExpression(amdgpu_gfx90a::v46, output_vec_len ); + case 47: return makeRegisterExpression(amdgpu_gfx90a::v47, output_vec_len ); + case 48: return makeRegisterExpression(amdgpu_gfx90a::v48, output_vec_len ); + case 49: return makeRegisterExpression(amdgpu_gfx90a::v49, output_vec_len ); + case 50: return makeRegisterExpression(amdgpu_gfx90a::v50, output_vec_len ); + case 51: return makeRegisterExpression(amdgpu_gfx90a::v51, output_vec_len ); + case 52: return makeRegisterExpression(amdgpu_gfx90a::v52, output_vec_len ); + case 53: return makeRegisterExpression(amdgpu_gfx90a::v53, output_vec_len ); + case 54: return makeRegisterExpression(amdgpu_gfx90a::v54, output_vec_len ); + case 55: return makeRegisterExpression(amdgpu_gfx90a::v55, output_vec_len ); + case 56: return makeRegisterExpression(amdgpu_gfx90a::v56, output_vec_len ); + case 57: return makeRegisterExpression(amdgpu_gfx90a::v57, output_vec_len ); + case 58: return makeRegisterExpression(amdgpu_gfx90a::v58, output_vec_len ); + case 59: return makeRegisterExpression(amdgpu_gfx90a::v59, output_vec_len ); + case 60: return makeRegisterExpression(amdgpu_gfx90a::v60, output_vec_len ); + case 61: return makeRegisterExpression(amdgpu_gfx90a::v61, output_vec_len ); + case 62: return makeRegisterExpression(amdgpu_gfx90a::v62, output_vec_len ); + case 63: return makeRegisterExpression(amdgpu_gfx90a::v63, output_vec_len ); + case 64: return makeRegisterExpression(amdgpu_gfx90a::v64, output_vec_len ); + case 65: return makeRegisterExpression(amdgpu_gfx90a::v65, output_vec_len ); + case 66: return makeRegisterExpression(amdgpu_gfx90a::v66, output_vec_len ); + case 67: return makeRegisterExpression(amdgpu_gfx90a::v67, output_vec_len ); + case 68: return makeRegisterExpression(amdgpu_gfx90a::v68, output_vec_len ); + case 69: return makeRegisterExpression(amdgpu_gfx90a::v69, output_vec_len ); + case 70: return makeRegisterExpression(amdgpu_gfx90a::v70, output_vec_len ); + case 71: return makeRegisterExpression(amdgpu_gfx90a::v71, output_vec_len ); + case 72: return makeRegisterExpression(amdgpu_gfx90a::v72, output_vec_len ); + case 73: return makeRegisterExpression(amdgpu_gfx90a::v73, output_vec_len ); + case 74: return makeRegisterExpression(amdgpu_gfx90a::v74, output_vec_len ); + case 75: return makeRegisterExpression(amdgpu_gfx90a::v75, output_vec_len ); + case 76: return makeRegisterExpression(amdgpu_gfx90a::v76, output_vec_len ); + case 77: return makeRegisterExpression(amdgpu_gfx90a::v77, output_vec_len ); + case 78: return makeRegisterExpression(amdgpu_gfx90a::v78, output_vec_len ); + case 79: return makeRegisterExpression(amdgpu_gfx90a::v79, output_vec_len ); + case 80: return makeRegisterExpression(amdgpu_gfx90a::v80, output_vec_len ); + case 81: return makeRegisterExpression(amdgpu_gfx90a::v81, output_vec_len ); + case 82: return makeRegisterExpression(amdgpu_gfx90a::v82, output_vec_len ); + case 83: return makeRegisterExpression(amdgpu_gfx90a::v83, output_vec_len ); + case 84: return makeRegisterExpression(amdgpu_gfx90a::v84, output_vec_len ); + case 85: return makeRegisterExpression(amdgpu_gfx90a::v85, output_vec_len ); + case 86: return makeRegisterExpression(amdgpu_gfx90a::v86, output_vec_len ); + case 87: return makeRegisterExpression(amdgpu_gfx90a::v87, output_vec_len ); + case 88: return makeRegisterExpression(amdgpu_gfx90a::v88, output_vec_len ); + case 89: return makeRegisterExpression(amdgpu_gfx90a::v89, output_vec_len ); + case 90: return makeRegisterExpression(amdgpu_gfx90a::v90, output_vec_len ); + case 91: return makeRegisterExpression(amdgpu_gfx90a::v91, output_vec_len ); + case 92: return makeRegisterExpression(amdgpu_gfx90a::v92, output_vec_len ); + case 93: return makeRegisterExpression(amdgpu_gfx90a::v93, output_vec_len ); + case 94: return makeRegisterExpression(amdgpu_gfx90a::v94, output_vec_len ); + case 95: return makeRegisterExpression(amdgpu_gfx90a::v95, output_vec_len ); + case 96: return makeRegisterExpression(amdgpu_gfx90a::v96, output_vec_len ); + case 97: return makeRegisterExpression(amdgpu_gfx90a::v97, output_vec_len ); + case 98: return makeRegisterExpression(amdgpu_gfx90a::v98, output_vec_len ); + case 99: return makeRegisterExpression(amdgpu_gfx90a::v99, output_vec_len ); + case 100: return makeRegisterExpression(amdgpu_gfx90a::v100, output_vec_len ); + case 101: return makeRegisterExpression(amdgpu_gfx90a::v101, output_vec_len ); + case 102: return makeRegisterExpression(amdgpu_gfx90a::v102, output_vec_len ); + case 103: return makeRegisterExpression(amdgpu_gfx90a::v103, output_vec_len ); + case 104: return makeRegisterExpression(amdgpu_gfx90a::v104, output_vec_len ); + case 105: return makeRegisterExpression(amdgpu_gfx90a::v105, output_vec_len ); + case 106: return makeRegisterExpression(amdgpu_gfx90a::v106, output_vec_len ); + case 107: return makeRegisterExpression(amdgpu_gfx90a::v107, output_vec_len ); + case 108: return makeRegisterExpression(amdgpu_gfx90a::v108, output_vec_len ); + case 109: return makeRegisterExpression(amdgpu_gfx90a::v109, output_vec_len ); + case 110: return makeRegisterExpression(amdgpu_gfx90a::v110, output_vec_len ); + case 111: return makeRegisterExpression(amdgpu_gfx90a::v111, output_vec_len ); + case 112: return makeRegisterExpression(amdgpu_gfx90a::v112, output_vec_len ); + case 113: return makeRegisterExpression(amdgpu_gfx90a::v113, output_vec_len ); + case 114: return makeRegisterExpression(amdgpu_gfx90a::v114, output_vec_len ); + case 115: return makeRegisterExpression(amdgpu_gfx90a::v115, output_vec_len ); + case 116: return makeRegisterExpression(amdgpu_gfx90a::v116, output_vec_len ); + case 117: return makeRegisterExpression(amdgpu_gfx90a::v117, output_vec_len ); + case 118: return makeRegisterExpression(amdgpu_gfx90a::v118, output_vec_len ); + case 119: return makeRegisterExpression(amdgpu_gfx90a::v119, output_vec_len ); + case 120: return makeRegisterExpression(amdgpu_gfx90a::v120, output_vec_len ); + case 121: return makeRegisterExpression(amdgpu_gfx90a::v121, output_vec_len ); + case 122: return makeRegisterExpression(amdgpu_gfx90a::v122, output_vec_len ); + case 123: return makeRegisterExpression(amdgpu_gfx90a::v123, output_vec_len ); + case 124: return makeRegisterExpression(amdgpu_gfx90a::v124, output_vec_len ); + case 125: return makeRegisterExpression(amdgpu_gfx90a::v125, output_vec_len ); + case 126: return makeRegisterExpression(amdgpu_gfx90a::v126, output_vec_len ); + case 127: return makeRegisterExpression(amdgpu_gfx90a::v127, output_vec_len ); + case 128: return makeRegisterExpression(amdgpu_gfx90a::v128, output_vec_len ); + case 129: return makeRegisterExpression(amdgpu_gfx90a::v129, output_vec_len ); + case 130: return makeRegisterExpression(amdgpu_gfx90a::v130, output_vec_len ); + case 131: return makeRegisterExpression(amdgpu_gfx90a::v131, output_vec_len ); + case 132: return makeRegisterExpression(amdgpu_gfx90a::v132, output_vec_len ); + case 133: return makeRegisterExpression(amdgpu_gfx90a::v133, output_vec_len ); + case 134: return makeRegisterExpression(amdgpu_gfx90a::v134, output_vec_len ); + case 135: return makeRegisterExpression(amdgpu_gfx90a::v135, output_vec_len ); + case 136: return makeRegisterExpression(amdgpu_gfx90a::v136, output_vec_len ); + case 137: return makeRegisterExpression(amdgpu_gfx90a::v137, output_vec_len ); + case 138: return makeRegisterExpression(amdgpu_gfx90a::v138, output_vec_len ); + case 139: return makeRegisterExpression(amdgpu_gfx90a::v139, output_vec_len ); + case 140: return makeRegisterExpression(amdgpu_gfx90a::v140, output_vec_len ); + case 141: return makeRegisterExpression(amdgpu_gfx90a::v141, output_vec_len ); + case 142: return makeRegisterExpression(amdgpu_gfx90a::v142, output_vec_len ); + case 143: return makeRegisterExpression(amdgpu_gfx90a::v143, output_vec_len ); + case 144: return makeRegisterExpression(amdgpu_gfx90a::v144, output_vec_len ); + case 145: return makeRegisterExpression(amdgpu_gfx90a::v145, output_vec_len ); + case 146: return makeRegisterExpression(amdgpu_gfx90a::v146, output_vec_len ); + case 147: return makeRegisterExpression(amdgpu_gfx90a::v147, output_vec_len ); + case 148: return makeRegisterExpression(amdgpu_gfx90a::v148, output_vec_len ); + case 149: return makeRegisterExpression(amdgpu_gfx90a::v149, output_vec_len ); + case 150: return makeRegisterExpression(amdgpu_gfx90a::v150, output_vec_len ); + case 151: return makeRegisterExpression(amdgpu_gfx90a::v151, output_vec_len ); + case 152: return makeRegisterExpression(amdgpu_gfx90a::v152, output_vec_len ); + case 153: return makeRegisterExpression(amdgpu_gfx90a::v153, output_vec_len ); + case 154: return makeRegisterExpression(amdgpu_gfx90a::v154, output_vec_len ); + case 155: return makeRegisterExpression(amdgpu_gfx90a::v155, output_vec_len ); + case 156: return makeRegisterExpression(amdgpu_gfx90a::v156, output_vec_len ); + case 157: return makeRegisterExpression(amdgpu_gfx90a::v157, output_vec_len ); + case 158: return makeRegisterExpression(amdgpu_gfx90a::v158, output_vec_len ); + case 159: return makeRegisterExpression(amdgpu_gfx90a::v159, output_vec_len ); + case 160: return makeRegisterExpression(amdgpu_gfx90a::v160, output_vec_len ); + case 161: return makeRegisterExpression(amdgpu_gfx90a::v161, output_vec_len ); + case 162: return makeRegisterExpression(amdgpu_gfx90a::v162, output_vec_len ); + case 163: return makeRegisterExpression(amdgpu_gfx90a::v163, output_vec_len ); + case 164: return makeRegisterExpression(amdgpu_gfx90a::v164, output_vec_len ); + case 165: return makeRegisterExpression(amdgpu_gfx90a::v165, output_vec_len ); + case 166: return makeRegisterExpression(amdgpu_gfx90a::v166, output_vec_len ); + case 167: return makeRegisterExpression(amdgpu_gfx90a::v167, output_vec_len ); + case 168: return makeRegisterExpression(amdgpu_gfx90a::v168, output_vec_len ); + case 169: return makeRegisterExpression(amdgpu_gfx90a::v169, output_vec_len ); + case 170: return makeRegisterExpression(amdgpu_gfx90a::v170, output_vec_len ); + case 171: return makeRegisterExpression(amdgpu_gfx90a::v171, output_vec_len ); + case 172: return makeRegisterExpression(amdgpu_gfx90a::v172, output_vec_len ); + case 173: return makeRegisterExpression(amdgpu_gfx90a::v173, output_vec_len ); + case 174: return makeRegisterExpression(amdgpu_gfx90a::v174, output_vec_len ); + case 175: return makeRegisterExpression(amdgpu_gfx90a::v175, output_vec_len ); + case 176: return makeRegisterExpression(amdgpu_gfx90a::v176, output_vec_len ); + case 177: return makeRegisterExpression(amdgpu_gfx90a::v177, output_vec_len ); + case 178: return makeRegisterExpression(amdgpu_gfx90a::v178, output_vec_len ); + case 179: return makeRegisterExpression(amdgpu_gfx90a::v179, output_vec_len ); + case 180: return makeRegisterExpression(amdgpu_gfx90a::v180, output_vec_len ); + case 181: return makeRegisterExpression(amdgpu_gfx90a::v181, output_vec_len ); + case 182: return makeRegisterExpression(amdgpu_gfx90a::v182, output_vec_len ); + case 183: return makeRegisterExpression(amdgpu_gfx90a::v183, output_vec_len ); + case 184: return makeRegisterExpression(amdgpu_gfx90a::v184, output_vec_len ); + case 185: return makeRegisterExpression(amdgpu_gfx90a::v185, output_vec_len ); + case 186: return makeRegisterExpression(amdgpu_gfx90a::v186, output_vec_len ); + case 187: return makeRegisterExpression(amdgpu_gfx90a::v187, output_vec_len ); + case 188: return makeRegisterExpression(amdgpu_gfx90a::v188, output_vec_len ); + case 189: return makeRegisterExpression(amdgpu_gfx90a::v189, output_vec_len ); + case 190: return makeRegisterExpression(amdgpu_gfx90a::v190, output_vec_len ); + case 191: return makeRegisterExpression(amdgpu_gfx90a::v191, output_vec_len ); + case 192: return makeRegisterExpression(amdgpu_gfx90a::v192, output_vec_len ); + case 193: return makeRegisterExpression(amdgpu_gfx90a::v193, output_vec_len ); + case 194: return makeRegisterExpression(amdgpu_gfx90a::v194, output_vec_len ); + case 195: return makeRegisterExpression(amdgpu_gfx90a::v195, output_vec_len ); + case 196: return makeRegisterExpression(amdgpu_gfx90a::v196, output_vec_len ); + case 197: return makeRegisterExpression(amdgpu_gfx90a::v197, output_vec_len ); + case 198: return makeRegisterExpression(amdgpu_gfx90a::v198, output_vec_len ); + case 199: return makeRegisterExpression(amdgpu_gfx90a::v199, output_vec_len ); + case 200: return makeRegisterExpression(amdgpu_gfx90a::v200, output_vec_len ); + case 201: return makeRegisterExpression(amdgpu_gfx90a::v201, output_vec_len ); + case 202: return makeRegisterExpression(amdgpu_gfx90a::v202, output_vec_len ); + case 203: return makeRegisterExpression(amdgpu_gfx90a::v203, output_vec_len ); + case 204: return makeRegisterExpression(amdgpu_gfx90a::v204, output_vec_len ); + case 205: return makeRegisterExpression(amdgpu_gfx90a::v205, output_vec_len ); + case 206: return makeRegisterExpression(amdgpu_gfx90a::v206, output_vec_len ); + case 207: return makeRegisterExpression(amdgpu_gfx90a::v207, output_vec_len ); + case 208: return makeRegisterExpression(amdgpu_gfx90a::v208, output_vec_len ); + case 209: return makeRegisterExpression(amdgpu_gfx90a::v209, output_vec_len ); + case 210: return makeRegisterExpression(amdgpu_gfx90a::v210, output_vec_len ); + case 211: return makeRegisterExpression(amdgpu_gfx90a::v211, output_vec_len ); + case 212: return makeRegisterExpression(amdgpu_gfx90a::v212, output_vec_len ); + case 213: return makeRegisterExpression(amdgpu_gfx90a::v213, output_vec_len ); + case 214: return makeRegisterExpression(amdgpu_gfx90a::v214, output_vec_len ); + case 215: return makeRegisterExpression(amdgpu_gfx90a::v215, output_vec_len ); + case 216: return makeRegisterExpression(amdgpu_gfx90a::v216, output_vec_len ); + case 217: return makeRegisterExpression(amdgpu_gfx90a::v217, output_vec_len ); + case 218: return makeRegisterExpression(amdgpu_gfx90a::v218, output_vec_len ); + case 219: return makeRegisterExpression(amdgpu_gfx90a::v219, output_vec_len ); + case 220: return makeRegisterExpression(amdgpu_gfx90a::v220, output_vec_len ); + case 221: return makeRegisterExpression(amdgpu_gfx90a::v221, output_vec_len ); + case 222: return makeRegisterExpression(amdgpu_gfx90a::v222, output_vec_len ); + case 223: return makeRegisterExpression(amdgpu_gfx90a::v223, output_vec_len ); + case 224: return makeRegisterExpression(amdgpu_gfx90a::v224, output_vec_len ); + case 225: return makeRegisterExpression(amdgpu_gfx90a::v225, output_vec_len ); + case 226: return makeRegisterExpression(amdgpu_gfx90a::v226, output_vec_len ); + case 227: return makeRegisterExpression(amdgpu_gfx90a::v227, output_vec_len ); + case 228: return makeRegisterExpression(amdgpu_gfx90a::v228, output_vec_len ); + case 229: return makeRegisterExpression(amdgpu_gfx90a::v229, output_vec_len ); + case 230: return makeRegisterExpression(amdgpu_gfx90a::v230, output_vec_len ); + case 231: return makeRegisterExpression(amdgpu_gfx90a::v231, output_vec_len ); + case 232: return makeRegisterExpression(amdgpu_gfx90a::v232, output_vec_len ); + case 233: return makeRegisterExpression(amdgpu_gfx90a::v233, output_vec_len ); + case 234: return makeRegisterExpression(amdgpu_gfx90a::v234, output_vec_len ); + case 235: return makeRegisterExpression(amdgpu_gfx90a::v235, output_vec_len ); + case 236: return makeRegisterExpression(amdgpu_gfx90a::v236, output_vec_len ); + case 237: return makeRegisterExpression(amdgpu_gfx90a::v237, output_vec_len ); + case 238: return makeRegisterExpression(amdgpu_gfx90a::v238, output_vec_len ); + case 239: return makeRegisterExpression(amdgpu_gfx90a::v239, output_vec_len ); + case 240: return makeRegisterExpression(amdgpu_gfx90a::v240, output_vec_len ); + case 241: return makeRegisterExpression(amdgpu_gfx90a::v241, output_vec_len ); + case 242: return makeRegisterExpression(amdgpu_gfx90a::v242, output_vec_len ); + case 243: return makeRegisterExpression(amdgpu_gfx90a::v243, output_vec_len ); + case 244: return makeRegisterExpression(amdgpu_gfx90a::v244, output_vec_len ); + case 245: return makeRegisterExpression(amdgpu_gfx90a::v245, output_vec_len ); + case 246: return makeRegisterExpression(amdgpu_gfx90a::v246, output_vec_len ); + case 247: return makeRegisterExpression(amdgpu_gfx90a::v247, output_vec_len ); + case 248: return makeRegisterExpression(amdgpu_gfx90a::v248, output_vec_len ); + case 249: return makeRegisterExpression(amdgpu_gfx90a::v249, output_vec_len ); + case 250: return makeRegisterExpression(amdgpu_gfx90a::v250, output_vec_len ); + case 251: return makeRegisterExpression(amdgpu_gfx90a::v251, output_vec_len ); + case 252: return makeRegisterExpression(amdgpu_gfx90a::v252, output_vec_len ); + case 253: return makeRegisterExpression(amdgpu_gfx90a::v253, output_vec_len ); + case 254: return makeRegisterExpression(amdgpu_gfx90a::v254, output_vec_len ); + case 255: return makeRegisterExpression(amdgpu_gfx90a::v255, output_vec_len ); + default: return makeRegisterExpression(amdgpu_gfx90a::invalid); + } + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx90a::decodeOPR_VGPR_OR_ACCVGPR(uint64_t input, uint32_t output_vec_len) + { + switch (input) { + case 0: return makeRegisterExpression(amdgpu_gfx90a::v0, output_vec_len ); + case 1: return makeRegisterExpression(amdgpu_gfx90a::v1, output_vec_len ); + case 2: return makeRegisterExpression(amdgpu_gfx90a::v2, output_vec_len ); + case 3: return makeRegisterExpression(amdgpu_gfx90a::v3, output_vec_len ); + case 4: return makeRegisterExpression(amdgpu_gfx90a::v4, output_vec_len ); + case 5: return makeRegisterExpression(amdgpu_gfx90a::v5, output_vec_len ); + case 6: return makeRegisterExpression(amdgpu_gfx90a::v6, output_vec_len ); + case 7: return makeRegisterExpression(amdgpu_gfx90a::v7, output_vec_len ); + case 8: return makeRegisterExpression(amdgpu_gfx90a::v8, output_vec_len ); + case 9: return makeRegisterExpression(amdgpu_gfx90a::v9, output_vec_len ); + case 10: return makeRegisterExpression(amdgpu_gfx90a::v10, output_vec_len ); + case 11: return makeRegisterExpression(amdgpu_gfx90a::v11, output_vec_len ); + case 12: return makeRegisterExpression(amdgpu_gfx90a::v12, output_vec_len ); + case 13: return makeRegisterExpression(amdgpu_gfx90a::v13, output_vec_len ); + case 14: return makeRegisterExpression(amdgpu_gfx90a::v14, output_vec_len ); + case 15: return makeRegisterExpression(amdgpu_gfx90a::v15, output_vec_len ); + case 16: return makeRegisterExpression(amdgpu_gfx90a::v16, output_vec_len ); + case 17: return makeRegisterExpression(amdgpu_gfx90a::v17, output_vec_len ); + case 18: return makeRegisterExpression(amdgpu_gfx90a::v18, output_vec_len ); + case 19: return makeRegisterExpression(amdgpu_gfx90a::v19, output_vec_len ); + case 20: return makeRegisterExpression(amdgpu_gfx90a::v20, output_vec_len ); + case 21: return makeRegisterExpression(amdgpu_gfx90a::v21, output_vec_len ); + case 22: return makeRegisterExpression(amdgpu_gfx90a::v22, output_vec_len ); + case 23: return makeRegisterExpression(amdgpu_gfx90a::v23, output_vec_len ); + case 24: return makeRegisterExpression(amdgpu_gfx90a::v24, output_vec_len ); + case 25: return makeRegisterExpression(amdgpu_gfx90a::v25, output_vec_len ); + case 26: return makeRegisterExpression(amdgpu_gfx90a::v26, output_vec_len ); + case 27: return makeRegisterExpression(amdgpu_gfx90a::v27, output_vec_len ); + case 28: return makeRegisterExpression(amdgpu_gfx90a::v28, output_vec_len ); + case 29: return makeRegisterExpression(amdgpu_gfx90a::v29, output_vec_len ); + case 30: return makeRegisterExpression(amdgpu_gfx90a::v30, output_vec_len ); + case 31: return makeRegisterExpression(amdgpu_gfx90a::v31, output_vec_len ); + case 32: return makeRegisterExpression(amdgpu_gfx90a::v32, output_vec_len ); + case 33: return makeRegisterExpression(amdgpu_gfx90a::v33, output_vec_len ); + case 34: return makeRegisterExpression(amdgpu_gfx90a::v34, output_vec_len ); + case 35: return makeRegisterExpression(amdgpu_gfx90a::v35, output_vec_len ); + case 36: return makeRegisterExpression(amdgpu_gfx90a::v36, output_vec_len ); + case 37: return makeRegisterExpression(amdgpu_gfx90a::v37, output_vec_len ); + case 38: return makeRegisterExpression(amdgpu_gfx90a::v38, output_vec_len ); + case 39: return makeRegisterExpression(amdgpu_gfx90a::v39, output_vec_len ); + case 40: return makeRegisterExpression(amdgpu_gfx90a::v40, output_vec_len ); + case 41: return makeRegisterExpression(amdgpu_gfx90a::v41, output_vec_len ); + case 42: return makeRegisterExpression(amdgpu_gfx90a::v42, output_vec_len ); + case 43: return makeRegisterExpression(amdgpu_gfx90a::v43, output_vec_len ); + case 44: return makeRegisterExpression(amdgpu_gfx90a::v44, output_vec_len ); + case 45: return makeRegisterExpression(amdgpu_gfx90a::v45, output_vec_len ); + case 46: return makeRegisterExpression(amdgpu_gfx90a::v46, output_vec_len ); + case 47: return makeRegisterExpression(amdgpu_gfx90a::v47, output_vec_len ); + case 48: return makeRegisterExpression(amdgpu_gfx90a::v48, output_vec_len ); + case 49: return makeRegisterExpression(amdgpu_gfx90a::v49, output_vec_len ); + case 50: return makeRegisterExpression(amdgpu_gfx90a::v50, output_vec_len ); + case 51: return makeRegisterExpression(amdgpu_gfx90a::v51, output_vec_len ); + case 52: return makeRegisterExpression(amdgpu_gfx90a::v52, output_vec_len ); + case 53: return makeRegisterExpression(amdgpu_gfx90a::v53, output_vec_len ); + case 54: return makeRegisterExpression(amdgpu_gfx90a::v54, output_vec_len ); + case 55: return makeRegisterExpression(amdgpu_gfx90a::v55, output_vec_len ); + case 56: return makeRegisterExpression(amdgpu_gfx90a::v56, output_vec_len ); + case 57: return makeRegisterExpression(amdgpu_gfx90a::v57, output_vec_len ); + case 58: return makeRegisterExpression(amdgpu_gfx90a::v58, output_vec_len ); + case 59: return makeRegisterExpression(amdgpu_gfx90a::v59, output_vec_len ); + case 60: return makeRegisterExpression(amdgpu_gfx90a::v60, output_vec_len ); + case 61: return makeRegisterExpression(amdgpu_gfx90a::v61, output_vec_len ); + case 62: return makeRegisterExpression(amdgpu_gfx90a::v62, output_vec_len ); + case 63: return makeRegisterExpression(amdgpu_gfx90a::v63, output_vec_len ); + case 64: return makeRegisterExpression(amdgpu_gfx90a::v64, output_vec_len ); + case 65: return makeRegisterExpression(amdgpu_gfx90a::v65, output_vec_len ); + case 66: return makeRegisterExpression(amdgpu_gfx90a::v66, output_vec_len ); + case 67: return makeRegisterExpression(amdgpu_gfx90a::v67, output_vec_len ); + case 68: return makeRegisterExpression(amdgpu_gfx90a::v68, output_vec_len ); + case 69: return makeRegisterExpression(amdgpu_gfx90a::v69, output_vec_len ); + case 70: return makeRegisterExpression(amdgpu_gfx90a::v70, output_vec_len ); + case 71: return makeRegisterExpression(amdgpu_gfx90a::v71, output_vec_len ); + case 72: return makeRegisterExpression(amdgpu_gfx90a::v72, output_vec_len ); + case 73: return makeRegisterExpression(amdgpu_gfx90a::v73, output_vec_len ); + case 74: return makeRegisterExpression(amdgpu_gfx90a::v74, output_vec_len ); + case 75: return makeRegisterExpression(amdgpu_gfx90a::v75, output_vec_len ); + case 76: return makeRegisterExpression(amdgpu_gfx90a::v76, output_vec_len ); + case 77: return makeRegisterExpression(amdgpu_gfx90a::v77, output_vec_len ); + case 78: return makeRegisterExpression(amdgpu_gfx90a::v78, output_vec_len ); + case 79: return makeRegisterExpression(amdgpu_gfx90a::v79, output_vec_len ); + case 80: return makeRegisterExpression(amdgpu_gfx90a::v80, output_vec_len ); + case 81: return makeRegisterExpression(amdgpu_gfx90a::v81, output_vec_len ); + case 82: return makeRegisterExpression(amdgpu_gfx90a::v82, output_vec_len ); + case 83: return makeRegisterExpression(amdgpu_gfx90a::v83, output_vec_len ); + case 84: return makeRegisterExpression(amdgpu_gfx90a::v84, output_vec_len ); + case 85: return makeRegisterExpression(amdgpu_gfx90a::v85, output_vec_len ); + case 86: return makeRegisterExpression(amdgpu_gfx90a::v86, output_vec_len ); + case 87: return makeRegisterExpression(amdgpu_gfx90a::v87, output_vec_len ); + case 88: return makeRegisterExpression(amdgpu_gfx90a::v88, output_vec_len ); + case 89: return makeRegisterExpression(amdgpu_gfx90a::v89, output_vec_len ); + case 90: return makeRegisterExpression(amdgpu_gfx90a::v90, output_vec_len ); + case 91: return makeRegisterExpression(amdgpu_gfx90a::v91, output_vec_len ); + case 92: return makeRegisterExpression(amdgpu_gfx90a::v92, output_vec_len ); + case 93: return makeRegisterExpression(amdgpu_gfx90a::v93, output_vec_len ); + case 94: return makeRegisterExpression(amdgpu_gfx90a::v94, output_vec_len ); + case 95: return makeRegisterExpression(amdgpu_gfx90a::v95, output_vec_len ); + case 96: return makeRegisterExpression(amdgpu_gfx90a::v96, output_vec_len ); + case 97: return makeRegisterExpression(amdgpu_gfx90a::v97, output_vec_len ); + case 98: return makeRegisterExpression(amdgpu_gfx90a::v98, output_vec_len ); + case 99: return makeRegisterExpression(amdgpu_gfx90a::v99, output_vec_len ); + case 100: return makeRegisterExpression(amdgpu_gfx90a::v100, output_vec_len ); + case 101: return makeRegisterExpression(amdgpu_gfx90a::v101, output_vec_len ); + case 102: return makeRegisterExpression(amdgpu_gfx90a::v102, output_vec_len ); + case 103: return makeRegisterExpression(amdgpu_gfx90a::v103, output_vec_len ); + case 104: return makeRegisterExpression(amdgpu_gfx90a::v104, output_vec_len ); + case 105: return makeRegisterExpression(amdgpu_gfx90a::v105, output_vec_len ); + case 106: return makeRegisterExpression(amdgpu_gfx90a::v106, output_vec_len ); + case 107: return makeRegisterExpression(amdgpu_gfx90a::v107, output_vec_len ); + case 108: return makeRegisterExpression(amdgpu_gfx90a::v108, output_vec_len ); + case 109: return makeRegisterExpression(amdgpu_gfx90a::v109, output_vec_len ); + case 110: return makeRegisterExpression(amdgpu_gfx90a::v110, output_vec_len ); + case 111: return makeRegisterExpression(amdgpu_gfx90a::v111, output_vec_len ); + case 112: return makeRegisterExpression(amdgpu_gfx90a::v112, output_vec_len ); + case 113: return makeRegisterExpression(amdgpu_gfx90a::v113, output_vec_len ); + case 114: return makeRegisterExpression(amdgpu_gfx90a::v114, output_vec_len ); + case 115: return makeRegisterExpression(amdgpu_gfx90a::v115, output_vec_len ); + case 116: return makeRegisterExpression(amdgpu_gfx90a::v116, output_vec_len ); + case 117: return makeRegisterExpression(amdgpu_gfx90a::v117, output_vec_len ); + case 118: return makeRegisterExpression(amdgpu_gfx90a::v118, output_vec_len ); + case 119: return makeRegisterExpression(amdgpu_gfx90a::v119, output_vec_len ); + case 120: return makeRegisterExpression(amdgpu_gfx90a::v120, output_vec_len ); + case 121: return makeRegisterExpression(amdgpu_gfx90a::v121, output_vec_len ); + case 122: return makeRegisterExpression(amdgpu_gfx90a::v122, output_vec_len ); + case 123: return makeRegisterExpression(amdgpu_gfx90a::v123, output_vec_len ); + case 124: return makeRegisterExpression(amdgpu_gfx90a::v124, output_vec_len ); + case 125: return makeRegisterExpression(amdgpu_gfx90a::v125, output_vec_len ); + case 126: return makeRegisterExpression(amdgpu_gfx90a::v126, output_vec_len ); + case 127: return makeRegisterExpression(amdgpu_gfx90a::v127, output_vec_len ); + case 128: return makeRegisterExpression(amdgpu_gfx90a::v128, output_vec_len ); + case 129: return makeRegisterExpression(amdgpu_gfx90a::v129, output_vec_len ); + case 130: return makeRegisterExpression(amdgpu_gfx90a::v130, output_vec_len ); + case 131: return makeRegisterExpression(amdgpu_gfx90a::v131, output_vec_len ); + case 132: return makeRegisterExpression(amdgpu_gfx90a::v132, output_vec_len ); + case 133: return makeRegisterExpression(amdgpu_gfx90a::v133, output_vec_len ); + case 134: return makeRegisterExpression(amdgpu_gfx90a::v134, output_vec_len ); + case 135: return makeRegisterExpression(amdgpu_gfx90a::v135, output_vec_len ); + case 136: return makeRegisterExpression(amdgpu_gfx90a::v136, output_vec_len ); + case 137: return makeRegisterExpression(amdgpu_gfx90a::v137, output_vec_len ); + case 138: return makeRegisterExpression(amdgpu_gfx90a::v138, output_vec_len ); + case 139: return makeRegisterExpression(amdgpu_gfx90a::v139, output_vec_len ); + case 140: return makeRegisterExpression(amdgpu_gfx90a::v140, output_vec_len ); + case 141: return makeRegisterExpression(amdgpu_gfx90a::v141, output_vec_len ); + case 142: return makeRegisterExpression(amdgpu_gfx90a::v142, output_vec_len ); + case 143: return makeRegisterExpression(amdgpu_gfx90a::v143, output_vec_len ); + case 144: return makeRegisterExpression(amdgpu_gfx90a::v144, output_vec_len ); + case 145: return makeRegisterExpression(amdgpu_gfx90a::v145, output_vec_len ); + case 146: return makeRegisterExpression(amdgpu_gfx90a::v146, output_vec_len ); + case 147: return makeRegisterExpression(amdgpu_gfx90a::v147, output_vec_len ); + case 148: return makeRegisterExpression(amdgpu_gfx90a::v148, output_vec_len ); + case 149: return makeRegisterExpression(amdgpu_gfx90a::v149, output_vec_len ); + case 150: return makeRegisterExpression(amdgpu_gfx90a::v150, output_vec_len ); + case 151: return makeRegisterExpression(amdgpu_gfx90a::v151, output_vec_len ); + case 152: return makeRegisterExpression(amdgpu_gfx90a::v152, output_vec_len ); + case 153: return makeRegisterExpression(amdgpu_gfx90a::v153, output_vec_len ); + case 154: return makeRegisterExpression(amdgpu_gfx90a::v154, output_vec_len ); + case 155: return makeRegisterExpression(amdgpu_gfx90a::v155, output_vec_len ); + case 156: return makeRegisterExpression(amdgpu_gfx90a::v156, output_vec_len ); + case 157: return makeRegisterExpression(amdgpu_gfx90a::v157, output_vec_len ); + case 158: return makeRegisterExpression(amdgpu_gfx90a::v158, output_vec_len ); + case 159: return makeRegisterExpression(amdgpu_gfx90a::v159, output_vec_len ); + case 160: return makeRegisterExpression(amdgpu_gfx90a::v160, output_vec_len ); + case 161: return makeRegisterExpression(amdgpu_gfx90a::v161, output_vec_len ); + case 162: return makeRegisterExpression(amdgpu_gfx90a::v162, output_vec_len ); + case 163: return makeRegisterExpression(amdgpu_gfx90a::v163, output_vec_len ); + case 164: return makeRegisterExpression(amdgpu_gfx90a::v164, output_vec_len ); + case 165: return makeRegisterExpression(amdgpu_gfx90a::v165, output_vec_len ); + case 166: return makeRegisterExpression(amdgpu_gfx90a::v166, output_vec_len ); + case 167: return makeRegisterExpression(amdgpu_gfx90a::v167, output_vec_len ); + case 168: return makeRegisterExpression(amdgpu_gfx90a::v168, output_vec_len ); + case 169: return makeRegisterExpression(amdgpu_gfx90a::v169, output_vec_len ); + case 170: return makeRegisterExpression(amdgpu_gfx90a::v170, output_vec_len ); + case 171: return makeRegisterExpression(amdgpu_gfx90a::v171, output_vec_len ); + case 172: return makeRegisterExpression(amdgpu_gfx90a::v172, output_vec_len ); + case 173: return makeRegisterExpression(amdgpu_gfx90a::v173, output_vec_len ); + case 174: return makeRegisterExpression(amdgpu_gfx90a::v174, output_vec_len ); + case 175: return makeRegisterExpression(amdgpu_gfx90a::v175, output_vec_len ); + case 176: return makeRegisterExpression(amdgpu_gfx90a::v176, output_vec_len ); + case 177: return makeRegisterExpression(amdgpu_gfx90a::v177, output_vec_len ); + case 178: return makeRegisterExpression(amdgpu_gfx90a::v178, output_vec_len ); + case 179: return makeRegisterExpression(amdgpu_gfx90a::v179, output_vec_len ); + case 180: return makeRegisterExpression(amdgpu_gfx90a::v180, output_vec_len ); + case 181: return makeRegisterExpression(amdgpu_gfx90a::v181, output_vec_len ); + case 182: return makeRegisterExpression(amdgpu_gfx90a::v182, output_vec_len ); + case 183: return makeRegisterExpression(amdgpu_gfx90a::v183, output_vec_len ); + case 184: return makeRegisterExpression(amdgpu_gfx90a::v184, output_vec_len ); + case 185: return makeRegisterExpression(amdgpu_gfx90a::v185, output_vec_len ); + case 186: return makeRegisterExpression(amdgpu_gfx90a::v186, output_vec_len ); + case 187: return makeRegisterExpression(amdgpu_gfx90a::v187, output_vec_len ); + case 188: return makeRegisterExpression(amdgpu_gfx90a::v188, output_vec_len ); + case 189: return makeRegisterExpression(amdgpu_gfx90a::v189, output_vec_len ); + case 190: return makeRegisterExpression(amdgpu_gfx90a::v190, output_vec_len ); + case 191: return makeRegisterExpression(amdgpu_gfx90a::v191, output_vec_len ); + case 192: return makeRegisterExpression(amdgpu_gfx90a::v192, output_vec_len ); + case 193: return makeRegisterExpression(amdgpu_gfx90a::v193, output_vec_len ); + case 194: return makeRegisterExpression(amdgpu_gfx90a::v194, output_vec_len ); + case 195: return makeRegisterExpression(amdgpu_gfx90a::v195, output_vec_len ); + case 196: return makeRegisterExpression(amdgpu_gfx90a::v196, output_vec_len ); + case 197: return makeRegisterExpression(amdgpu_gfx90a::v197, output_vec_len ); + case 198: return makeRegisterExpression(amdgpu_gfx90a::v198, output_vec_len ); + case 199: return makeRegisterExpression(amdgpu_gfx90a::v199, output_vec_len ); + case 200: return makeRegisterExpression(amdgpu_gfx90a::v200, output_vec_len ); + case 201: return makeRegisterExpression(amdgpu_gfx90a::v201, output_vec_len ); + case 202: return makeRegisterExpression(amdgpu_gfx90a::v202, output_vec_len ); + case 203: return makeRegisterExpression(amdgpu_gfx90a::v203, output_vec_len ); + case 204: return makeRegisterExpression(amdgpu_gfx90a::v204, output_vec_len ); + case 205: return makeRegisterExpression(amdgpu_gfx90a::v205, output_vec_len ); + case 206: return makeRegisterExpression(amdgpu_gfx90a::v206, output_vec_len ); + case 207: return makeRegisterExpression(amdgpu_gfx90a::v207, output_vec_len ); + case 208: return makeRegisterExpression(amdgpu_gfx90a::v208, output_vec_len ); + case 209: return makeRegisterExpression(amdgpu_gfx90a::v209, output_vec_len ); + case 210: return makeRegisterExpression(amdgpu_gfx90a::v210, output_vec_len ); + case 211: return makeRegisterExpression(amdgpu_gfx90a::v211, output_vec_len ); + case 212: return makeRegisterExpression(amdgpu_gfx90a::v212, output_vec_len ); + case 213: return makeRegisterExpression(amdgpu_gfx90a::v213, output_vec_len ); + case 214: return makeRegisterExpression(amdgpu_gfx90a::v214, output_vec_len ); + case 215: return makeRegisterExpression(amdgpu_gfx90a::v215, output_vec_len ); + case 216: return makeRegisterExpression(amdgpu_gfx90a::v216, output_vec_len ); + case 217: return makeRegisterExpression(amdgpu_gfx90a::v217, output_vec_len ); + case 218: return makeRegisterExpression(amdgpu_gfx90a::v218, output_vec_len ); + case 219: return makeRegisterExpression(amdgpu_gfx90a::v219, output_vec_len ); + case 220: return makeRegisterExpression(amdgpu_gfx90a::v220, output_vec_len ); + case 221: return makeRegisterExpression(amdgpu_gfx90a::v221, output_vec_len ); + case 222: return makeRegisterExpression(amdgpu_gfx90a::v222, output_vec_len ); + case 223: return makeRegisterExpression(amdgpu_gfx90a::v223, output_vec_len ); + case 224: return makeRegisterExpression(amdgpu_gfx90a::v224, output_vec_len ); + case 225: return makeRegisterExpression(amdgpu_gfx90a::v225, output_vec_len ); + case 226: return makeRegisterExpression(amdgpu_gfx90a::v226, output_vec_len ); + case 227: return makeRegisterExpression(amdgpu_gfx90a::v227, output_vec_len ); + case 228: return makeRegisterExpression(amdgpu_gfx90a::v228, output_vec_len ); + case 229: return makeRegisterExpression(amdgpu_gfx90a::v229, output_vec_len ); + case 230: return makeRegisterExpression(amdgpu_gfx90a::v230, output_vec_len ); + case 231: return makeRegisterExpression(amdgpu_gfx90a::v231, output_vec_len ); + case 232: return makeRegisterExpression(amdgpu_gfx90a::v232, output_vec_len ); + case 233: return makeRegisterExpression(amdgpu_gfx90a::v233, output_vec_len ); + case 234: return makeRegisterExpression(amdgpu_gfx90a::v234, output_vec_len ); + case 235: return makeRegisterExpression(amdgpu_gfx90a::v235, output_vec_len ); + case 236: return makeRegisterExpression(amdgpu_gfx90a::v236, output_vec_len ); + case 237: return makeRegisterExpression(amdgpu_gfx90a::v237, output_vec_len ); + case 238: return makeRegisterExpression(amdgpu_gfx90a::v238, output_vec_len ); + case 239: return makeRegisterExpression(amdgpu_gfx90a::v239, output_vec_len ); + case 240: return makeRegisterExpression(amdgpu_gfx90a::v240, output_vec_len ); + case 241: return makeRegisterExpression(amdgpu_gfx90a::v241, output_vec_len ); + case 242: return makeRegisterExpression(amdgpu_gfx90a::v242, output_vec_len ); + case 243: return makeRegisterExpression(amdgpu_gfx90a::v243, output_vec_len ); + case 244: return makeRegisterExpression(amdgpu_gfx90a::v244, output_vec_len ); + case 245: return makeRegisterExpression(amdgpu_gfx90a::v245, output_vec_len ); + case 246: return makeRegisterExpression(amdgpu_gfx90a::v246, output_vec_len ); + case 247: return makeRegisterExpression(amdgpu_gfx90a::v247, output_vec_len ); + case 248: return makeRegisterExpression(amdgpu_gfx90a::v248, output_vec_len ); + case 249: return makeRegisterExpression(amdgpu_gfx90a::v249, output_vec_len ); + case 250: return makeRegisterExpression(amdgpu_gfx90a::v250, output_vec_len ); + case 251: return makeRegisterExpression(amdgpu_gfx90a::v251, output_vec_len ); + case 252: return makeRegisterExpression(amdgpu_gfx90a::v252, output_vec_len ); + case 253: return makeRegisterExpression(amdgpu_gfx90a::v253, output_vec_len ); + case 254: return makeRegisterExpression(amdgpu_gfx90a::v254, output_vec_len ); + case 255: return makeRegisterExpression(amdgpu_gfx90a::v255, output_vec_len ); + case 512: return makeRegisterExpression(amdgpu_gfx90a::acc0, output_vec_len ); + case 513: return makeRegisterExpression(amdgpu_gfx90a::acc1, output_vec_len ); + case 514: return makeRegisterExpression(amdgpu_gfx90a::acc2, output_vec_len ); + case 515: return makeRegisterExpression(amdgpu_gfx90a::acc3, output_vec_len ); + case 516: return makeRegisterExpression(amdgpu_gfx90a::acc4, output_vec_len ); + case 517: return makeRegisterExpression(amdgpu_gfx90a::acc5, output_vec_len ); + case 518: return makeRegisterExpression(amdgpu_gfx90a::acc6, output_vec_len ); + case 519: return makeRegisterExpression(amdgpu_gfx90a::acc7, output_vec_len ); + case 520: return makeRegisterExpression(amdgpu_gfx90a::acc8, output_vec_len ); + case 521: return makeRegisterExpression(amdgpu_gfx90a::acc9, output_vec_len ); + case 522: return makeRegisterExpression(amdgpu_gfx90a::acc10, output_vec_len ); + case 523: return makeRegisterExpression(amdgpu_gfx90a::acc11, output_vec_len ); + case 524: return makeRegisterExpression(amdgpu_gfx90a::acc12, output_vec_len ); + case 525: return makeRegisterExpression(amdgpu_gfx90a::acc13, output_vec_len ); + case 526: return makeRegisterExpression(amdgpu_gfx90a::acc14, output_vec_len ); + case 527: return makeRegisterExpression(amdgpu_gfx90a::acc15, output_vec_len ); + case 528: return makeRegisterExpression(amdgpu_gfx90a::acc16, output_vec_len ); + case 529: return makeRegisterExpression(amdgpu_gfx90a::acc17, output_vec_len ); + case 530: return makeRegisterExpression(amdgpu_gfx90a::acc18, output_vec_len ); + case 531: return makeRegisterExpression(amdgpu_gfx90a::acc19, output_vec_len ); + case 532: return makeRegisterExpression(amdgpu_gfx90a::acc20, output_vec_len ); + case 533: return makeRegisterExpression(amdgpu_gfx90a::acc21, output_vec_len ); + case 534: return makeRegisterExpression(amdgpu_gfx90a::acc22, output_vec_len ); + case 535: return makeRegisterExpression(amdgpu_gfx90a::acc23, output_vec_len ); + case 536: return makeRegisterExpression(amdgpu_gfx90a::acc24, output_vec_len ); + case 537: return makeRegisterExpression(amdgpu_gfx90a::acc25, output_vec_len ); + case 538: return makeRegisterExpression(amdgpu_gfx90a::acc26, output_vec_len ); + case 539: return makeRegisterExpression(amdgpu_gfx90a::acc27, output_vec_len ); + case 540: return makeRegisterExpression(amdgpu_gfx90a::acc28, output_vec_len ); + case 541: return makeRegisterExpression(amdgpu_gfx90a::acc29, output_vec_len ); + case 542: return makeRegisterExpression(amdgpu_gfx90a::acc30, output_vec_len ); + case 543: return makeRegisterExpression(amdgpu_gfx90a::acc31, output_vec_len ); + case 544: return makeRegisterExpression(amdgpu_gfx90a::acc32, output_vec_len ); + case 545: return makeRegisterExpression(amdgpu_gfx90a::acc33, output_vec_len ); + case 546: return makeRegisterExpression(amdgpu_gfx90a::acc34, output_vec_len ); + case 547: return makeRegisterExpression(amdgpu_gfx90a::acc35, output_vec_len ); + case 548: return makeRegisterExpression(amdgpu_gfx90a::acc36, output_vec_len ); + case 549: return makeRegisterExpression(amdgpu_gfx90a::acc37, output_vec_len ); + case 550: return makeRegisterExpression(amdgpu_gfx90a::acc38, output_vec_len ); + case 551: return makeRegisterExpression(amdgpu_gfx90a::acc39, output_vec_len ); + case 552: return makeRegisterExpression(amdgpu_gfx90a::acc40, output_vec_len ); + case 553: return makeRegisterExpression(amdgpu_gfx90a::acc41, output_vec_len ); + case 554: return makeRegisterExpression(amdgpu_gfx90a::acc42, output_vec_len ); + case 555: return makeRegisterExpression(amdgpu_gfx90a::acc43, output_vec_len ); + case 556: return makeRegisterExpression(amdgpu_gfx90a::acc44, output_vec_len ); + case 557: return makeRegisterExpression(amdgpu_gfx90a::acc45, output_vec_len ); + case 558: return makeRegisterExpression(amdgpu_gfx90a::acc46, output_vec_len ); + case 559: return makeRegisterExpression(amdgpu_gfx90a::acc47, output_vec_len ); + case 560: return makeRegisterExpression(amdgpu_gfx90a::acc48, output_vec_len ); + case 561: return makeRegisterExpression(amdgpu_gfx90a::acc49, output_vec_len ); + case 562: return makeRegisterExpression(amdgpu_gfx90a::acc50, output_vec_len ); + case 563: return makeRegisterExpression(amdgpu_gfx90a::acc51, output_vec_len ); + case 564: return makeRegisterExpression(amdgpu_gfx90a::acc52, output_vec_len ); + case 565: return makeRegisterExpression(amdgpu_gfx90a::acc53, output_vec_len ); + case 566: return makeRegisterExpression(amdgpu_gfx90a::acc54, output_vec_len ); + case 567: return makeRegisterExpression(amdgpu_gfx90a::acc55, output_vec_len ); + case 568: return makeRegisterExpression(amdgpu_gfx90a::acc56, output_vec_len ); + case 569: return makeRegisterExpression(amdgpu_gfx90a::acc57, output_vec_len ); + case 570: return makeRegisterExpression(amdgpu_gfx90a::acc58, output_vec_len ); + case 571: return makeRegisterExpression(amdgpu_gfx90a::acc59, output_vec_len ); + case 572: return makeRegisterExpression(amdgpu_gfx90a::acc60, output_vec_len ); + case 573: return makeRegisterExpression(amdgpu_gfx90a::acc61, output_vec_len ); + case 574: return makeRegisterExpression(amdgpu_gfx90a::acc62, output_vec_len ); + case 575: return makeRegisterExpression(amdgpu_gfx90a::acc63, output_vec_len ); + case 576: return makeRegisterExpression(amdgpu_gfx90a::acc64, output_vec_len ); + case 577: return makeRegisterExpression(amdgpu_gfx90a::acc65, output_vec_len ); + case 578: return makeRegisterExpression(amdgpu_gfx90a::acc66, output_vec_len ); + case 579: return makeRegisterExpression(amdgpu_gfx90a::acc67, output_vec_len ); + case 580: return makeRegisterExpression(amdgpu_gfx90a::acc68, output_vec_len ); + case 581: return makeRegisterExpression(amdgpu_gfx90a::acc69, output_vec_len ); + case 582: return makeRegisterExpression(amdgpu_gfx90a::acc70, output_vec_len ); + case 583: return makeRegisterExpression(amdgpu_gfx90a::acc71, output_vec_len ); + case 584: return makeRegisterExpression(amdgpu_gfx90a::acc72, output_vec_len ); + case 585: return makeRegisterExpression(amdgpu_gfx90a::acc73, output_vec_len ); + case 586: return makeRegisterExpression(amdgpu_gfx90a::acc74, output_vec_len ); + case 587: return makeRegisterExpression(amdgpu_gfx90a::acc75, output_vec_len ); + case 588: return makeRegisterExpression(amdgpu_gfx90a::acc76, output_vec_len ); + case 589: return makeRegisterExpression(amdgpu_gfx90a::acc77, output_vec_len ); + case 590: return makeRegisterExpression(amdgpu_gfx90a::acc78, output_vec_len ); + case 591: return makeRegisterExpression(amdgpu_gfx90a::acc79, output_vec_len ); + case 592: return makeRegisterExpression(amdgpu_gfx90a::acc80, output_vec_len ); + case 593: return makeRegisterExpression(amdgpu_gfx90a::acc81, output_vec_len ); + case 594: return makeRegisterExpression(amdgpu_gfx90a::acc82, output_vec_len ); + case 595: return makeRegisterExpression(amdgpu_gfx90a::acc83, output_vec_len ); + case 596: return makeRegisterExpression(amdgpu_gfx90a::acc84, output_vec_len ); + case 597: return makeRegisterExpression(amdgpu_gfx90a::acc85, output_vec_len ); + case 598: return makeRegisterExpression(amdgpu_gfx90a::acc86, output_vec_len ); + case 599: return makeRegisterExpression(amdgpu_gfx90a::acc87, output_vec_len ); + case 600: return makeRegisterExpression(amdgpu_gfx90a::acc88, output_vec_len ); + case 601: return makeRegisterExpression(amdgpu_gfx90a::acc89, output_vec_len ); + case 602: return makeRegisterExpression(amdgpu_gfx90a::acc90, output_vec_len ); + case 603: return makeRegisterExpression(amdgpu_gfx90a::acc91, output_vec_len ); + case 604: return makeRegisterExpression(amdgpu_gfx90a::acc92, output_vec_len ); + case 605: return makeRegisterExpression(amdgpu_gfx90a::acc93, output_vec_len ); + case 606: return makeRegisterExpression(amdgpu_gfx90a::acc94, output_vec_len ); + case 607: return makeRegisterExpression(amdgpu_gfx90a::acc95, output_vec_len ); + case 608: return makeRegisterExpression(amdgpu_gfx90a::acc96, output_vec_len ); + case 609: return makeRegisterExpression(amdgpu_gfx90a::acc97, output_vec_len ); + case 610: return makeRegisterExpression(amdgpu_gfx90a::acc98, output_vec_len ); + case 611: return makeRegisterExpression(amdgpu_gfx90a::acc99, output_vec_len ); + case 612: return makeRegisterExpression(amdgpu_gfx90a::acc100, output_vec_len ); + case 613: return makeRegisterExpression(amdgpu_gfx90a::acc101, output_vec_len ); + case 614: return makeRegisterExpression(amdgpu_gfx90a::acc102, output_vec_len ); + case 615: return makeRegisterExpression(amdgpu_gfx90a::acc103, output_vec_len ); + case 616: return makeRegisterExpression(amdgpu_gfx90a::acc104, output_vec_len ); + case 617: return makeRegisterExpression(amdgpu_gfx90a::acc105, output_vec_len ); + case 618: return makeRegisterExpression(amdgpu_gfx90a::acc106, output_vec_len ); + case 619: return makeRegisterExpression(amdgpu_gfx90a::acc107, output_vec_len ); + case 620: return makeRegisterExpression(amdgpu_gfx90a::acc108, output_vec_len ); + case 621: return makeRegisterExpression(amdgpu_gfx90a::acc109, output_vec_len ); + case 622: return makeRegisterExpression(amdgpu_gfx90a::acc110, output_vec_len ); + case 623: return makeRegisterExpression(amdgpu_gfx90a::acc111, output_vec_len ); + case 624: return makeRegisterExpression(amdgpu_gfx90a::acc112, output_vec_len ); + case 625: return makeRegisterExpression(amdgpu_gfx90a::acc113, output_vec_len ); + case 626: return makeRegisterExpression(amdgpu_gfx90a::acc114, output_vec_len ); + case 627: return makeRegisterExpression(amdgpu_gfx90a::acc115, output_vec_len ); + case 628: return makeRegisterExpression(amdgpu_gfx90a::acc116, output_vec_len ); + case 629: return makeRegisterExpression(amdgpu_gfx90a::acc117, output_vec_len ); + case 630: return makeRegisterExpression(amdgpu_gfx90a::acc118, output_vec_len ); + case 631: return makeRegisterExpression(amdgpu_gfx90a::acc119, output_vec_len ); + case 632: return makeRegisterExpression(amdgpu_gfx90a::acc120, output_vec_len ); + case 633: return makeRegisterExpression(amdgpu_gfx90a::acc121, output_vec_len ); + case 634: return makeRegisterExpression(amdgpu_gfx90a::acc122, output_vec_len ); + case 635: return makeRegisterExpression(amdgpu_gfx90a::acc123, output_vec_len ); + case 636: return makeRegisterExpression(amdgpu_gfx90a::acc124, output_vec_len ); + case 637: return makeRegisterExpression(amdgpu_gfx90a::acc125, output_vec_len ); + case 638: return makeRegisterExpression(amdgpu_gfx90a::acc126, output_vec_len ); + case 639: return makeRegisterExpression(amdgpu_gfx90a::acc127, output_vec_len ); + case 640: return makeRegisterExpression(amdgpu_gfx90a::acc128, output_vec_len ); + case 641: return makeRegisterExpression(amdgpu_gfx90a::acc129, output_vec_len ); + case 642: return makeRegisterExpression(amdgpu_gfx90a::acc130, output_vec_len ); + case 643: return makeRegisterExpression(amdgpu_gfx90a::acc131, output_vec_len ); + case 644: return makeRegisterExpression(amdgpu_gfx90a::acc132, output_vec_len ); + case 645: return makeRegisterExpression(amdgpu_gfx90a::acc133, output_vec_len ); + case 646: return makeRegisterExpression(amdgpu_gfx90a::acc134, output_vec_len ); + case 647: return makeRegisterExpression(amdgpu_gfx90a::acc135, output_vec_len ); + case 648: return makeRegisterExpression(amdgpu_gfx90a::acc136, output_vec_len ); + case 649: return makeRegisterExpression(amdgpu_gfx90a::acc137, output_vec_len ); + case 650: return makeRegisterExpression(amdgpu_gfx90a::acc138, output_vec_len ); + case 651: return makeRegisterExpression(amdgpu_gfx90a::acc139, output_vec_len ); + case 652: return makeRegisterExpression(amdgpu_gfx90a::acc140, output_vec_len ); + case 653: return makeRegisterExpression(amdgpu_gfx90a::acc141, output_vec_len ); + case 654: return makeRegisterExpression(amdgpu_gfx90a::acc142, output_vec_len ); + case 655: return makeRegisterExpression(amdgpu_gfx90a::acc143, output_vec_len ); + case 656: return makeRegisterExpression(amdgpu_gfx90a::acc144, output_vec_len ); + case 657: return makeRegisterExpression(amdgpu_gfx90a::acc145, output_vec_len ); + case 658: return makeRegisterExpression(amdgpu_gfx90a::acc146, output_vec_len ); + case 659: return makeRegisterExpression(amdgpu_gfx90a::acc147, output_vec_len ); + case 660: return makeRegisterExpression(amdgpu_gfx90a::acc148, output_vec_len ); + case 661: return makeRegisterExpression(amdgpu_gfx90a::acc149, output_vec_len ); + case 662: return makeRegisterExpression(amdgpu_gfx90a::acc150, output_vec_len ); + case 663: return makeRegisterExpression(amdgpu_gfx90a::acc151, output_vec_len ); + case 664: return makeRegisterExpression(amdgpu_gfx90a::acc152, output_vec_len ); + case 665: return makeRegisterExpression(amdgpu_gfx90a::acc153, output_vec_len ); + case 666: return makeRegisterExpression(amdgpu_gfx90a::acc154, output_vec_len ); + case 667: return makeRegisterExpression(amdgpu_gfx90a::acc155, output_vec_len ); + case 668: return makeRegisterExpression(amdgpu_gfx90a::acc156, output_vec_len ); + case 669: return makeRegisterExpression(amdgpu_gfx90a::acc157, output_vec_len ); + case 670: return makeRegisterExpression(amdgpu_gfx90a::acc158, output_vec_len ); + case 671: return makeRegisterExpression(amdgpu_gfx90a::acc159, output_vec_len ); + case 672: return makeRegisterExpression(amdgpu_gfx90a::acc160, output_vec_len ); + case 673: return makeRegisterExpression(amdgpu_gfx90a::acc161, output_vec_len ); + case 674: return makeRegisterExpression(amdgpu_gfx90a::acc162, output_vec_len ); + case 675: return makeRegisterExpression(amdgpu_gfx90a::acc163, output_vec_len ); + case 676: return makeRegisterExpression(amdgpu_gfx90a::acc164, output_vec_len ); + case 677: return makeRegisterExpression(amdgpu_gfx90a::acc165, output_vec_len ); + case 678: return makeRegisterExpression(amdgpu_gfx90a::acc166, output_vec_len ); + case 679: return makeRegisterExpression(amdgpu_gfx90a::acc167, output_vec_len ); + case 680: return makeRegisterExpression(amdgpu_gfx90a::acc168, output_vec_len ); + case 681: return makeRegisterExpression(amdgpu_gfx90a::acc169, output_vec_len ); + case 682: return makeRegisterExpression(amdgpu_gfx90a::acc170, output_vec_len ); + case 683: return makeRegisterExpression(amdgpu_gfx90a::acc171, output_vec_len ); + case 684: return makeRegisterExpression(amdgpu_gfx90a::acc172, output_vec_len ); + case 685: return makeRegisterExpression(amdgpu_gfx90a::acc173, output_vec_len ); + case 686: return makeRegisterExpression(amdgpu_gfx90a::acc174, output_vec_len ); + case 687: return makeRegisterExpression(amdgpu_gfx90a::acc175, output_vec_len ); + case 688: return makeRegisterExpression(amdgpu_gfx90a::acc176, output_vec_len ); + case 689: return makeRegisterExpression(amdgpu_gfx90a::acc177, output_vec_len ); + case 690: return makeRegisterExpression(amdgpu_gfx90a::acc178, output_vec_len ); + case 691: return makeRegisterExpression(amdgpu_gfx90a::acc179, output_vec_len ); + case 692: return makeRegisterExpression(amdgpu_gfx90a::acc180, output_vec_len ); + case 693: return makeRegisterExpression(amdgpu_gfx90a::acc181, output_vec_len ); + case 694: return makeRegisterExpression(amdgpu_gfx90a::acc182, output_vec_len ); + case 695: return makeRegisterExpression(amdgpu_gfx90a::acc183, output_vec_len ); + case 696: return makeRegisterExpression(amdgpu_gfx90a::acc184, output_vec_len ); + case 697: return makeRegisterExpression(amdgpu_gfx90a::acc185, output_vec_len ); + case 698: return makeRegisterExpression(amdgpu_gfx90a::acc186, output_vec_len ); + case 699: return makeRegisterExpression(amdgpu_gfx90a::acc187, output_vec_len ); + case 700: return makeRegisterExpression(amdgpu_gfx90a::acc188, output_vec_len ); + case 701: return makeRegisterExpression(amdgpu_gfx90a::acc189, output_vec_len ); + case 702: return makeRegisterExpression(amdgpu_gfx90a::acc190, output_vec_len ); + case 703: return makeRegisterExpression(amdgpu_gfx90a::acc191, output_vec_len ); + case 704: return makeRegisterExpression(amdgpu_gfx90a::acc192, output_vec_len ); + case 705: return makeRegisterExpression(amdgpu_gfx90a::acc193, output_vec_len ); + case 706: return makeRegisterExpression(amdgpu_gfx90a::acc194, output_vec_len ); + case 707: return makeRegisterExpression(amdgpu_gfx90a::acc195, output_vec_len ); + case 708: return makeRegisterExpression(amdgpu_gfx90a::acc196, output_vec_len ); + case 709: return makeRegisterExpression(amdgpu_gfx90a::acc197, output_vec_len ); + case 710: return makeRegisterExpression(amdgpu_gfx90a::acc198, output_vec_len ); + case 711: return makeRegisterExpression(amdgpu_gfx90a::acc199, output_vec_len ); + case 712: return makeRegisterExpression(amdgpu_gfx90a::acc200, output_vec_len ); + case 713: return makeRegisterExpression(amdgpu_gfx90a::acc201, output_vec_len ); + case 714: return makeRegisterExpression(amdgpu_gfx90a::acc202, output_vec_len ); + case 715: return makeRegisterExpression(amdgpu_gfx90a::acc203, output_vec_len ); + case 716: return makeRegisterExpression(amdgpu_gfx90a::acc204, output_vec_len ); + case 717: return makeRegisterExpression(amdgpu_gfx90a::acc205, output_vec_len ); + case 718: return makeRegisterExpression(amdgpu_gfx90a::acc206, output_vec_len ); + case 719: return makeRegisterExpression(amdgpu_gfx90a::acc207, output_vec_len ); + case 720: return makeRegisterExpression(amdgpu_gfx90a::acc208, output_vec_len ); + case 721: return makeRegisterExpression(amdgpu_gfx90a::acc209, output_vec_len ); + case 722: return makeRegisterExpression(amdgpu_gfx90a::acc210, output_vec_len ); + case 723: return makeRegisterExpression(amdgpu_gfx90a::acc211, output_vec_len ); + case 724: return makeRegisterExpression(amdgpu_gfx90a::acc212, output_vec_len ); + case 725: return makeRegisterExpression(amdgpu_gfx90a::acc213, output_vec_len ); + case 726: return makeRegisterExpression(amdgpu_gfx90a::acc214, output_vec_len ); + case 727: return makeRegisterExpression(amdgpu_gfx90a::acc215, output_vec_len ); + case 728: return makeRegisterExpression(amdgpu_gfx90a::acc216, output_vec_len ); + case 729: return makeRegisterExpression(amdgpu_gfx90a::acc217, output_vec_len ); + case 730: return makeRegisterExpression(amdgpu_gfx90a::acc218, output_vec_len ); + case 731: return makeRegisterExpression(amdgpu_gfx90a::acc219, output_vec_len ); + case 732: return makeRegisterExpression(amdgpu_gfx90a::acc220, output_vec_len ); + case 733: return makeRegisterExpression(amdgpu_gfx90a::acc221, output_vec_len ); + case 734: return makeRegisterExpression(amdgpu_gfx90a::acc222, output_vec_len ); + case 735: return makeRegisterExpression(amdgpu_gfx90a::acc223, output_vec_len ); + case 736: return makeRegisterExpression(amdgpu_gfx90a::acc224, output_vec_len ); + case 737: return makeRegisterExpression(amdgpu_gfx90a::acc225, output_vec_len ); + case 738: return makeRegisterExpression(amdgpu_gfx90a::acc226, output_vec_len ); + case 739: return makeRegisterExpression(amdgpu_gfx90a::acc227, output_vec_len ); + case 740: return makeRegisterExpression(amdgpu_gfx90a::acc228, output_vec_len ); + case 741: return makeRegisterExpression(amdgpu_gfx90a::acc229, output_vec_len ); + case 742: return makeRegisterExpression(amdgpu_gfx90a::acc230, output_vec_len ); + case 743: return makeRegisterExpression(amdgpu_gfx90a::acc231, output_vec_len ); + case 744: return makeRegisterExpression(amdgpu_gfx90a::acc232, output_vec_len ); + case 745: return makeRegisterExpression(amdgpu_gfx90a::acc233, output_vec_len ); + case 746: return makeRegisterExpression(amdgpu_gfx90a::acc234, output_vec_len ); + case 747: return makeRegisterExpression(amdgpu_gfx90a::acc235, output_vec_len ); + case 748: return makeRegisterExpression(amdgpu_gfx90a::acc236, output_vec_len ); + case 749: return makeRegisterExpression(amdgpu_gfx90a::acc237, output_vec_len ); + case 750: return makeRegisterExpression(amdgpu_gfx90a::acc238, output_vec_len ); + case 751: return makeRegisterExpression(amdgpu_gfx90a::acc239, output_vec_len ); + case 752: return makeRegisterExpression(amdgpu_gfx90a::acc240, output_vec_len ); + case 753: return makeRegisterExpression(amdgpu_gfx90a::acc241, output_vec_len ); + case 754: return makeRegisterExpression(amdgpu_gfx90a::acc242, output_vec_len ); + case 755: return makeRegisterExpression(amdgpu_gfx90a::acc243, output_vec_len ); + case 756: return makeRegisterExpression(amdgpu_gfx90a::acc244, output_vec_len ); + case 757: return makeRegisterExpression(amdgpu_gfx90a::acc245, output_vec_len ); + case 758: return makeRegisterExpression(amdgpu_gfx90a::acc246, output_vec_len ); + case 759: return makeRegisterExpression(amdgpu_gfx90a::acc247, output_vec_len ); + case 760: return makeRegisterExpression(amdgpu_gfx90a::acc248, output_vec_len ); + case 761: return makeRegisterExpression(amdgpu_gfx90a::acc249, output_vec_len ); + case 762: return makeRegisterExpression(amdgpu_gfx90a::acc250, output_vec_len ); + case 763: return makeRegisterExpression(amdgpu_gfx90a::acc251, output_vec_len ); + case 764: return makeRegisterExpression(amdgpu_gfx90a::acc252, output_vec_len ); + case 765: return makeRegisterExpression(amdgpu_gfx90a::acc253, output_vec_len ); + case 766: return makeRegisterExpression(amdgpu_gfx90a::acc254, output_vec_len ); + case 767: return makeRegisterExpression(amdgpu_gfx90a::acc255, output_vec_len ); + default: return makeRegisterExpression(amdgpu_gfx90a::invalid); + } + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx90a::decodeOPR_VGPR_OR_LDS(uint64_t input, uint32_t output_vec_len) + { + switch (input) { + case 256: return makeRegisterExpression(amdgpu_gfx90a::v0, output_vec_len ); + case 257: return makeRegisterExpression(amdgpu_gfx90a::v1, output_vec_len ); + case 258: return makeRegisterExpression(amdgpu_gfx90a::v2, output_vec_len ); + case 259: return makeRegisterExpression(amdgpu_gfx90a::v3, output_vec_len ); + case 260: return makeRegisterExpression(amdgpu_gfx90a::v4, output_vec_len ); + case 261: return makeRegisterExpression(amdgpu_gfx90a::v5, output_vec_len ); + case 262: return makeRegisterExpression(amdgpu_gfx90a::v6, output_vec_len ); + case 263: return makeRegisterExpression(amdgpu_gfx90a::v7, output_vec_len ); + case 264: return makeRegisterExpression(amdgpu_gfx90a::v8, output_vec_len ); + case 265: return makeRegisterExpression(amdgpu_gfx90a::v9, output_vec_len ); + case 266: return makeRegisterExpression(amdgpu_gfx90a::v10, output_vec_len ); + case 267: return makeRegisterExpression(amdgpu_gfx90a::v11, output_vec_len ); + case 268: return makeRegisterExpression(amdgpu_gfx90a::v12, output_vec_len ); + case 269: return makeRegisterExpression(amdgpu_gfx90a::v13, output_vec_len ); + case 270: return makeRegisterExpression(amdgpu_gfx90a::v14, output_vec_len ); + case 271: return makeRegisterExpression(amdgpu_gfx90a::v15, output_vec_len ); + case 272: return makeRegisterExpression(amdgpu_gfx90a::v16, output_vec_len ); + case 273: return makeRegisterExpression(amdgpu_gfx90a::v17, output_vec_len ); + case 274: return makeRegisterExpression(amdgpu_gfx90a::v18, output_vec_len ); + case 275: return makeRegisterExpression(amdgpu_gfx90a::v19, output_vec_len ); + case 276: return makeRegisterExpression(amdgpu_gfx90a::v20, output_vec_len ); + case 277: return makeRegisterExpression(amdgpu_gfx90a::v21, output_vec_len ); + case 278: return makeRegisterExpression(amdgpu_gfx90a::v22, output_vec_len ); + case 279: return makeRegisterExpression(amdgpu_gfx90a::v23, output_vec_len ); + case 280: return makeRegisterExpression(amdgpu_gfx90a::v24, output_vec_len ); + case 281: return makeRegisterExpression(amdgpu_gfx90a::v25, output_vec_len ); + case 282: return makeRegisterExpression(amdgpu_gfx90a::v26, output_vec_len ); + case 283: return makeRegisterExpression(amdgpu_gfx90a::v27, output_vec_len ); + case 284: return makeRegisterExpression(amdgpu_gfx90a::v28, output_vec_len ); + case 285: return makeRegisterExpression(amdgpu_gfx90a::v29, output_vec_len ); + case 286: return makeRegisterExpression(amdgpu_gfx90a::v30, output_vec_len ); + case 287: return makeRegisterExpression(amdgpu_gfx90a::v31, output_vec_len ); + case 288: return makeRegisterExpression(amdgpu_gfx90a::v32, output_vec_len ); + case 289: return makeRegisterExpression(amdgpu_gfx90a::v33, output_vec_len ); + case 290: return makeRegisterExpression(amdgpu_gfx90a::v34, output_vec_len ); + case 291: return makeRegisterExpression(amdgpu_gfx90a::v35, output_vec_len ); + case 292: return makeRegisterExpression(amdgpu_gfx90a::v36, output_vec_len ); + case 293: return makeRegisterExpression(amdgpu_gfx90a::v37, output_vec_len ); + case 294: return makeRegisterExpression(amdgpu_gfx90a::v38, output_vec_len ); + case 295: return makeRegisterExpression(amdgpu_gfx90a::v39, output_vec_len ); + case 296: return makeRegisterExpression(amdgpu_gfx90a::v40, output_vec_len ); + case 297: return makeRegisterExpression(amdgpu_gfx90a::v41, output_vec_len ); + case 298: return makeRegisterExpression(amdgpu_gfx90a::v42, output_vec_len ); + case 299: return makeRegisterExpression(amdgpu_gfx90a::v43, output_vec_len ); + case 300: return makeRegisterExpression(amdgpu_gfx90a::v44, output_vec_len ); + case 301: return makeRegisterExpression(amdgpu_gfx90a::v45, output_vec_len ); + case 302: return makeRegisterExpression(amdgpu_gfx90a::v46, output_vec_len ); + case 303: return makeRegisterExpression(amdgpu_gfx90a::v47, output_vec_len ); + case 304: return makeRegisterExpression(amdgpu_gfx90a::v48, output_vec_len ); + case 305: return makeRegisterExpression(amdgpu_gfx90a::v49, output_vec_len ); + case 306: return makeRegisterExpression(amdgpu_gfx90a::v50, output_vec_len ); + case 307: return makeRegisterExpression(amdgpu_gfx90a::v51, output_vec_len ); + case 308: return makeRegisterExpression(amdgpu_gfx90a::v52, output_vec_len ); + case 309: return makeRegisterExpression(amdgpu_gfx90a::v53, output_vec_len ); + case 310: return makeRegisterExpression(amdgpu_gfx90a::v54, output_vec_len ); + case 311: return makeRegisterExpression(amdgpu_gfx90a::v55, output_vec_len ); + case 312: return makeRegisterExpression(amdgpu_gfx90a::v56, output_vec_len ); + case 313: return makeRegisterExpression(amdgpu_gfx90a::v57, output_vec_len ); + case 314: return makeRegisterExpression(amdgpu_gfx90a::v58, output_vec_len ); + case 315: return makeRegisterExpression(amdgpu_gfx90a::v59, output_vec_len ); + case 316: return makeRegisterExpression(amdgpu_gfx90a::v60, output_vec_len ); + case 317: return makeRegisterExpression(amdgpu_gfx90a::v61, output_vec_len ); + case 318: return makeRegisterExpression(amdgpu_gfx90a::v62, output_vec_len ); + case 319: return makeRegisterExpression(amdgpu_gfx90a::v63, output_vec_len ); + case 320: return makeRegisterExpression(amdgpu_gfx90a::v64, output_vec_len ); + case 321: return makeRegisterExpression(amdgpu_gfx90a::v65, output_vec_len ); + case 322: return makeRegisterExpression(amdgpu_gfx90a::v66, output_vec_len ); + case 323: return makeRegisterExpression(amdgpu_gfx90a::v67, output_vec_len ); + case 324: return makeRegisterExpression(amdgpu_gfx90a::v68, output_vec_len ); + case 325: return makeRegisterExpression(amdgpu_gfx90a::v69, output_vec_len ); + case 326: return makeRegisterExpression(amdgpu_gfx90a::v70, output_vec_len ); + case 327: return makeRegisterExpression(amdgpu_gfx90a::v71, output_vec_len ); + case 328: return makeRegisterExpression(amdgpu_gfx90a::v72, output_vec_len ); + case 329: return makeRegisterExpression(amdgpu_gfx90a::v73, output_vec_len ); + case 330: return makeRegisterExpression(amdgpu_gfx90a::v74, output_vec_len ); + case 331: return makeRegisterExpression(amdgpu_gfx90a::v75, output_vec_len ); + case 332: return makeRegisterExpression(amdgpu_gfx90a::v76, output_vec_len ); + case 333: return makeRegisterExpression(amdgpu_gfx90a::v77, output_vec_len ); + case 334: return makeRegisterExpression(amdgpu_gfx90a::v78, output_vec_len ); + case 335: return makeRegisterExpression(amdgpu_gfx90a::v79, output_vec_len ); + case 336: return makeRegisterExpression(amdgpu_gfx90a::v80, output_vec_len ); + case 337: return makeRegisterExpression(amdgpu_gfx90a::v81, output_vec_len ); + case 338: return makeRegisterExpression(amdgpu_gfx90a::v82, output_vec_len ); + case 339: return makeRegisterExpression(amdgpu_gfx90a::v83, output_vec_len ); + case 340: return makeRegisterExpression(amdgpu_gfx90a::v84, output_vec_len ); + case 341: return makeRegisterExpression(amdgpu_gfx90a::v85, output_vec_len ); + case 342: return makeRegisterExpression(amdgpu_gfx90a::v86, output_vec_len ); + case 343: return makeRegisterExpression(amdgpu_gfx90a::v87, output_vec_len ); + case 344: return makeRegisterExpression(amdgpu_gfx90a::v88, output_vec_len ); + case 345: return makeRegisterExpression(amdgpu_gfx90a::v89, output_vec_len ); + case 346: return makeRegisterExpression(amdgpu_gfx90a::v90, output_vec_len ); + case 347: return makeRegisterExpression(amdgpu_gfx90a::v91, output_vec_len ); + case 348: return makeRegisterExpression(amdgpu_gfx90a::v92, output_vec_len ); + case 349: return makeRegisterExpression(amdgpu_gfx90a::v93, output_vec_len ); + case 350: return makeRegisterExpression(amdgpu_gfx90a::v94, output_vec_len ); + case 351: return makeRegisterExpression(amdgpu_gfx90a::v95, output_vec_len ); + case 352: return makeRegisterExpression(amdgpu_gfx90a::v96, output_vec_len ); + case 353: return makeRegisterExpression(amdgpu_gfx90a::v97, output_vec_len ); + case 354: return makeRegisterExpression(amdgpu_gfx90a::v98, output_vec_len ); + case 355: return makeRegisterExpression(amdgpu_gfx90a::v99, output_vec_len ); + case 356: return makeRegisterExpression(amdgpu_gfx90a::v100, output_vec_len ); + case 357: return makeRegisterExpression(amdgpu_gfx90a::v101, output_vec_len ); + case 358: return makeRegisterExpression(amdgpu_gfx90a::v102, output_vec_len ); + case 359: return makeRegisterExpression(amdgpu_gfx90a::v103, output_vec_len ); + case 360: return makeRegisterExpression(amdgpu_gfx90a::v104, output_vec_len ); + case 361: return makeRegisterExpression(amdgpu_gfx90a::v105, output_vec_len ); + case 362: return makeRegisterExpression(amdgpu_gfx90a::v106, output_vec_len ); + case 363: return makeRegisterExpression(amdgpu_gfx90a::v107, output_vec_len ); + case 364: return makeRegisterExpression(amdgpu_gfx90a::v108, output_vec_len ); + case 365: return makeRegisterExpression(amdgpu_gfx90a::v109, output_vec_len ); + case 366: return makeRegisterExpression(amdgpu_gfx90a::v110, output_vec_len ); + case 367: return makeRegisterExpression(amdgpu_gfx90a::v111, output_vec_len ); + case 368: return makeRegisterExpression(amdgpu_gfx90a::v112, output_vec_len ); + case 369: return makeRegisterExpression(amdgpu_gfx90a::v113, output_vec_len ); + case 370: return makeRegisterExpression(amdgpu_gfx90a::v114, output_vec_len ); + case 371: return makeRegisterExpression(amdgpu_gfx90a::v115, output_vec_len ); + case 372: return makeRegisterExpression(amdgpu_gfx90a::v116, output_vec_len ); + case 373: return makeRegisterExpression(amdgpu_gfx90a::v117, output_vec_len ); + case 374: return makeRegisterExpression(amdgpu_gfx90a::v118, output_vec_len ); + case 375: return makeRegisterExpression(amdgpu_gfx90a::v119, output_vec_len ); + case 376: return makeRegisterExpression(amdgpu_gfx90a::v120, output_vec_len ); + case 377: return makeRegisterExpression(amdgpu_gfx90a::v121, output_vec_len ); + case 378: return makeRegisterExpression(amdgpu_gfx90a::v122, output_vec_len ); + case 379: return makeRegisterExpression(amdgpu_gfx90a::v123, output_vec_len ); + case 380: return makeRegisterExpression(amdgpu_gfx90a::v124, output_vec_len ); + case 381: return makeRegisterExpression(amdgpu_gfx90a::v125, output_vec_len ); + case 382: return makeRegisterExpression(amdgpu_gfx90a::v126, output_vec_len ); + case 383: return makeRegisterExpression(amdgpu_gfx90a::v127, output_vec_len ); + case 384: return makeRegisterExpression(amdgpu_gfx90a::v128, output_vec_len ); + case 385: return makeRegisterExpression(amdgpu_gfx90a::v129, output_vec_len ); + case 386: return makeRegisterExpression(amdgpu_gfx90a::v130, output_vec_len ); + case 387: return makeRegisterExpression(amdgpu_gfx90a::v131, output_vec_len ); + case 388: return makeRegisterExpression(amdgpu_gfx90a::v132, output_vec_len ); + case 389: return makeRegisterExpression(amdgpu_gfx90a::v133, output_vec_len ); + case 390: return makeRegisterExpression(amdgpu_gfx90a::v134, output_vec_len ); + case 391: return makeRegisterExpression(amdgpu_gfx90a::v135, output_vec_len ); + case 392: return makeRegisterExpression(amdgpu_gfx90a::v136, output_vec_len ); + case 393: return makeRegisterExpression(amdgpu_gfx90a::v137, output_vec_len ); + case 394: return makeRegisterExpression(amdgpu_gfx90a::v138, output_vec_len ); + case 395: return makeRegisterExpression(amdgpu_gfx90a::v139, output_vec_len ); + case 396: return makeRegisterExpression(amdgpu_gfx90a::v140, output_vec_len ); + case 397: return makeRegisterExpression(amdgpu_gfx90a::v141, output_vec_len ); + case 398: return makeRegisterExpression(amdgpu_gfx90a::v142, output_vec_len ); + case 399: return makeRegisterExpression(amdgpu_gfx90a::v143, output_vec_len ); + case 400: return makeRegisterExpression(amdgpu_gfx90a::v144, output_vec_len ); + case 401: return makeRegisterExpression(amdgpu_gfx90a::v145, output_vec_len ); + case 402: return makeRegisterExpression(amdgpu_gfx90a::v146, output_vec_len ); + case 403: return makeRegisterExpression(amdgpu_gfx90a::v147, output_vec_len ); + case 404: return makeRegisterExpression(amdgpu_gfx90a::v148, output_vec_len ); + case 405: return makeRegisterExpression(amdgpu_gfx90a::v149, output_vec_len ); + case 406: return makeRegisterExpression(amdgpu_gfx90a::v150, output_vec_len ); + case 407: return makeRegisterExpression(amdgpu_gfx90a::v151, output_vec_len ); + case 408: return makeRegisterExpression(amdgpu_gfx90a::v152, output_vec_len ); + case 409: return makeRegisterExpression(amdgpu_gfx90a::v153, output_vec_len ); + case 410: return makeRegisterExpression(amdgpu_gfx90a::v154, output_vec_len ); + case 411: return makeRegisterExpression(amdgpu_gfx90a::v155, output_vec_len ); + case 412: return makeRegisterExpression(amdgpu_gfx90a::v156, output_vec_len ); + case 413: return makeRegisterExpression(amdgpu_gfx90a::v157, output_vec_len ); + case 414: return makeRegisterExpression(amdgpu_gfx90a::v158, output_vec_len ); + case 415: return makeRegisterExpression(amdgpu_gfx90a::v159, output_vec_len ); + case 416: return makeRegisterExpression(amdgpu_gfx90a::v160, output_vec_len ); + case 417: return makeRegisterExpression(amdgpu_gfx90a::v161, output_vec_len ); + case 418: return makeRegisterExpression(amdgpu_gfx90a::v162, output_vec_len ); + case 419: return makeRegisterExpression(amdgpu_gfx90a::v163, output_vec_len ); + case 420: return makeRegisterExpression(amdgpu_gfx90a::v164, output_vec_len ); + case 421: return makeRegisterExpression(amdgpu_gfx90a::v165, output_vec_len ); + case 422: return makeRegisterExpression(amdgpu_gfx90a::v166, output_vec_len ); + case 423: return makeRegisterExpression(amdgpu_gfx90a::v167, output_vec_len ); + case 424: return makeRegisterExpression(amdgpu_gfx90a::v168, output_vec_len ); + case 425: return makeRegisterExpression(amdgpu_gfx90a::v169, output_vec_len ); + case 426: return makeRegisterExpression(amdgpu_gfx90a::v170, output_vec_len ); + case 427: return makeRegisterExpression(amdgpu_gfx90a::v171, output_vec_len ); + case 428: return makeRegisterExpression(amdgpu_gfx90a::v172, output_vec_len ); + case 429: return makeRegisterExpression(amdgpu_gfx90a::v173, output_vec_len ); + case 430: return makeRegisterExpression(amdgpu_gfx90a::v174, output_vec_len ); + case 431: return makeRegisterExpression(amdgpu_gfx90a::v175, output_vec_len ); + case 432: return makeRegisterExpression(amdgpu_gfx90a::v176, output_vec_len ); + case 433: return makeRegisterExpression(amdgpu_gfx90a::v177, output_vec_len ); + case 434: return makeRegisterExpression(amdgpu_gfx90a::v178, output_vec_len ); + case 435: return makeRegisterExpression(amdgpu_gfx90a::v179, output_vec_len ); + case 436: return makeRegisterExpression(amdgpu_gfx90a::v180, output_vec_len ); + case 437: return makeRegisterExpression(amdgpu_gfx90a::v181, output_vec_len ); + case 438: return makeRegisterExpression(amdgpu_gfx90a::v182, output_vec_len ); + case 439: return makeRegisterExpression(amdgpu_gfx90a::v183, output_vec_len ); + case 440: return makeRegisterExpression(amdgpu_gfx90a::v184, output_vec_len ); + case 441: return makeRegisterExpression(amdgpu_gfx90a::v185, output_vec_len ); + case 442: return makeRegisterExpression(amdgpu_gfx90a::v186, output_vec_len ); + case 443: return makeRegisterExpression(amdgpu_gfx90a::v187, output_vec_len ); + case 444: return makeRegisterExpression(amdgpu_gfx90a::v188, output_vec_len ); + case 445: return makeRegisterExpression(amdgpu_gfx90a::v189, output_vec_len ); + case 446: return makeRegisterExpression(amdgpu_gfx90a::v190, output_vec_len ); + case 447: return makeRegisterExpression(amdgpu_gfx90a::v191, output_vec_len ); + case 448: return makeRegisterExpression(amdgpu_gfx90a::v192, output_vec_len ); + case 449: return makeRegisterExpression(amdgpu_gfx90a::v193, output_vec_len ); + case 450: return makeRegisterExpression(amdgpu_gfx90a::v194, output_vec_len ); + case 451: return makeRegisterExpression(amdgpu_gfx90a::v195, output_vec_len ); + case 452: return makeRegisterExpression(amdgpu_gfx90a::v196, output_vec_len ); + case 453: return makeRegisterExpression(amdgpu_gfx90a::v197, output_vec_len ); + case 454: return makeRegisterExpression(amdgpu_gfx90a::v198, output_vec_len ); + case 455: return makeRegisterExpression(amdgpu_gfx90a::v199, output_vec_len ); + case 456: return makeRegisterExpression(amdgpu_gfx90a::v200, output_vec_len ); + case 457: return makeRegisterExpression(amdgpu_gfx90a::v201, output_vec_len ); + case 458: return makeRegisterExpression(amdgpu_gfx90a::v202, output_vec_len ); + case 459: return makeRegisterExpression(amdgpu_gfx90a::v203, output_vec_len ); + case 460: return makeRegisterExpression(amdgpu_gfx90a::v204, output_vec_len ); + case 461: return makeRegisterExpression(amdgpu_gfx90a::v205, output_vec_len ); + case 462: return makeRegisterExpression(amdgpu_gfx90a::v206, output_vec_len ); + case 463: return makeRegisterExpression(amdgpu_gfx90a::v207, output_vec_len ); + case 464: return makeRegisterExpression(amdgpu_gfx90a::v208, output_vec_len ); + case 465: return makeRegisterExpression(amdgpu_gfx90a::v209, output_vec_len ); + case 466: return makeRegisterExpression(amdgpu_gfx90a::v210, output_vec_len ); + case 467: return makeRegisterExpression(amdgpu_gfx90a::v211, output_vec_len ); + case 468: return makeRegisterExpression(amdgpu_gfx90a::v212, output_vec_len ); + case 469: return makeRegisterExpression(amdgpu_gfx90a::v213, output_vec_len ); + case 470: return makeRegisterExpression(amdgpu_gfx90a::v214, output_vec_len ); + case 471: return makeRegisterExpression(amdgpu_gfx90a::v215, output_vec_len ); + case 472: return makeRegisterExpression(amdgpu_gfx90a::v216, output_vec_len ); + case 473: return makeRegisterExpression(amdgpu_gfx90a::v217, output_vec_len ); + case 474: return makeRegisterExpression(amdgpu_gfx90a::v218, output_vec_len ); + case 475: return makeRegisterExpression(amdgpu_gfx90a::v219, output_vec_len ); + case 476: return makeRegisterExpression(amdgpu_gfx90a::v220, output_vec_len ); + case 477: return makeRegisterExpression(amdgpu_gfx90a::v221, output_vec_len ); + case 478: return makeRegisterExpression(amdgpu_gfx90a::v222, output_vec_len ); + case 479: return makeRegisterExpression(amdgpu_gfx90a::v223, output_vec_len ); + case 480: return makeRegisterExpression(amdgpu_gfx90a::v224, output_vec_len ); + case 481: return makeRegisterExpression(amdgpu_gfx90a::v225, output_vec_len ); + case 482: return makeRegisterExpression(amdgpu_gfx90a::v226, output_vec_len ); + case 483: return makeRegisterExpression(amdgpu_gfx90a::v227, output_vec_len ); + case 484: return makeRegisterExpression(amdgpu_gfx90a::v228, output_vec_len ); + case 485: return makeRegisterExpression(amdgpu_gfx90a::v229, output_vec_len ); + case 486: return makeRegisterExpression(amdgpu_gfx90a::v230, output_vec_len ); + case 487: return makeRegisterExpression(amdgpu_gfx90a::v231, output_vec_len ); + case 488: return makeRegisterExpression(amdgpu_gfx90a::v232, output_vec_len ); + case 489: return makeRegisterExpression(amdgpu_gfx90a::v233, output_vec_len ); + case 490: return makeRegisterExpression(amdgpu_gfx90a::v234, output_vec_len ); + case 491: return makeRegisterExpression(amdgpu_gfx90a::v235, output_vec_len ); + case 492: return makeRegisterExpression(amdgpu_gfx90a::v236, output_vec_len ); + case 493: return makeRegisterExpression(amdgpu_gfx90a::v237, output_vec_len ); + case 494: return makeRegisterExpression(amdgpu_gfx90a::v238, output_vec_len ); + case 495: return makeRegisterExpression(amdgpu_gfx90a::v239, output_vec_len ); + case 496: return makeRegisterExpression(amdgpu_gfx90a::v240, output_vec_len ); + case 497: return makeRegisterExpression(amdgpu_gfx90a::v241, output_vec_len ); + case 498: return makeRegisterExpression(amdgpu_gfx90a::v242, output_vec_len ); + case 499: return makeRegisterExpression(amdgpu_gfx90a::v243, output_vec_len ); + case 500: return makeRegisterExpression(amdgpu_gfx90a::v244, output_vec_len ); + case 501: return makeRegisterExpression(amdgpu_gfx90a::v245, output_vec_len ); + case 502: return makeRegisterExpression(amdgpu_gfx90a::v246, output_vec_len ); + case 503: return makeRegisterExpression(amdgpu_gfx90a::v247, output_vec_len ); + case 504: return makeRegisterExpression(amdgpu_gfx90a::v248, output_vec_len ); + case 505: return makeRegisterExpression(amdgpu_gfx90a::v249, output_vec_len ); + case 506: return makeRegisterExpression(amdgpu_gfx90a::v250, output_vec_len ); + case 507: return makeRegisterExpression(amdgpu_gfx90a::v251, output_vec_len ); + case 508: return makeRegisterExpression(amdgpu_gfx90a::v252, output_vec_len ); + case 509: return makeRegisterExpression(amdgpu_gfx90a::v253, output_vec_len ); + case 510: return makeRegisterExpression(amdgpu_gfx90a::v254, output_vec_len ); + case 511: return makeRegisterExpression(amdgpu_gfx90a::v255, output_vec_len ); + default: return makeRegisterExpression(amdgpu_gfx90a::invalid); + } + } + +} +} diff --git a/instructionAPI/src/AMDGPU/gfx90a/finalizeOperands.C b/instructionAPI/src/AMDGPU/gfx90a/finalizeOperands.C new file mode 100644 index 0000000000..1c81518950 --- /dev/null +++ b/instructionAPI/src/AMDGPU/gfx90a/finalizeOperands.C @@ -0,0 +1,2252 @@ +#include "registers/AMDGPU/amdgpu_gfx90a_regs.h" +#include "InstructionDecoder-amdgpu-gfx90a.h" + +namespace Dyninst { +namespace InstructionAPI { + void InstructionDecoder_amdgpu_gfx90a::finalizeENC_DSOperands() + { + layout_ENC_DS & layout = insn_layout.ENC_DS; + switch (layout.OP) { + case 0: case 1: case 2: case 3: case 4: // DS_ADD_U32,DS_SUB_U32,DS_RSUB_U32,DS_INC_U32,DS_DEC_U32, + case 5: case 6: case 7: case 8: case 9: // DS_MIN_I32,DS_MAX_I32,DS_MIN_U32,DS_MAX_U32,DS_AND_B32, + case 10: case 11: case 13: case 18: case 19: // DS_OR_B32,DS_XOR_B32,DS_WRITE_B32,DS_MIN_F32,DS_MAX_F32, + case 21: case 30: case 31: case 84: // DS_ADD_F32,DS_WRITE_B8,DS_WRITE_B16,DS_WRITE_B8_D16_HI, + case 85: // DS_WRITE_B16_D16_HI, + appendOPR_VGPR(layout.ADDR,true,false); + appendOPR_VGPR_OR_ACCVGPR(layout.DATA0,true,false); + appendOPR_DSMEM(0,true,false,1,true); + if (layout.OFFSET0 || layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,(layout.OFFSET1 << 8) + layout.OFFSET0)),true,false,false); + } + break; + case 12: case 16: case 17: // DS_MSKOR_B32,DS_CMPST_B32,DS_CMPST_F32, + appendOPR_VGPR(layout.ADDR,true,false); + appendOPR_VGPR_OR_ACCVGPR(layout.DATA0,true,false); + appendOPR_VGPR_OR_ACCVGPR(layout.DATA1,true,false); + appendOPR_DSMEM(0,true,false,1,true); + if (layout.OFFSET0 || layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,(layout.OFFSET1 << 8) + layout.OFFSET0)),true,false,false); + } + break; + case 14: case 15: // DS_WRITE2_B32,DS_WRITE2ST64_B32, + appendOPR_VGPR(layout.ADDR,true,false); + appendOPR_VGPR_OR_ACCVGPR(layout.DATA0,true,false); + appendOPR_VGPR_OR_ACCVGPR(layout.DATA1,true,false); + appendOPR_DSMEM(0,true,false,1,true); + if (layout.OFFSET0) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset0"),Result(u8,layout.OFFSET0)),true,false,false); + } + if (layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset1"),Result(u8,layout.OFFSET1)),true,false,false); + } + break; + case 20: // DS_NOP, + if (layout.OFFSET0 || layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,(layout.OFFSET1 << 8) + layout.OFFSET0)),true,false,false); + } + break; + case 29: // DS_WRITE_ADDTID_B32, + appendOPR_VGPR_OR_ACCVGPR(layout.DATA0,true,false); + appendOPR_DSMEM(0,true,false,1,true); + appendOPR_SDST_M0(124,true,false,1,true); + if (layout.OFFSET0 || layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,(layout.OFFSET1 << 8) + layout.OFFSET0)),true,false,false); + } + break; + case 32: case 33: case 34: case 35: // DS_ADD_RTN_U32,DS_SUB_RTN_U32,DS_RSUB_RTN_U32,DS_INC_RTN_U32, + case 36: case 37: case 38: case 39: // DS_DEC_RTN_U32,DS_MIN_RTN_I32,DS_MAX_RTN_I32,DS_MIN_RTN_U32, + case 40: case 41: case 42: case 43: // DS_MAX_RTN_U32,DS_AND_RTN_B32,DS_OR_RTN_B32,DS_XOR_RTN_B32, + case 45: case 50: case 51: case 53: // DS_WRXCHG_RTN_B32,DS_MIN_RTN_F32,DS_MAX_RTN_F32,DS_ADD_RTN_F32, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true); + appendOPR_VGPR(layout.ADDR,true,false); + appendOPR_VGPR_OR_ACCVGPR(layout.DATA0,true,false); + appendOPR_DSMEM(0,true,false,1,true); + if (layout.OFFSET0 || layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,(layout.OFFSET1 << 8) + layout.OFFSET0)),true,false,false); + } + break; + case 44: case 48: case 49: case 52: // DS_MSKOR_RTN_B32,DS_CMPST_RTN_B32,DS_CMPST_RTN_F32,DS_WRAP_RTN_B32, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true); + appendOPR_VGPR(layout.ADDR,true,false); + appendOPR_VGPR_OR_ACCVGPR(layout.DATA0,true,false); + appendOPR_VGPR_OR_ACCVGPR(layout.DATA1,true,false); + appendOPR_DSMEM(0,true,false,1,true); + if (layout.OFFSET0 || layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,(layout.OFFSET1 << 8) + layout.OFFSET0)),true,false,false); + } + break; + case 46: case 47: // DS_WRXCHG2_RTN_B32,DS_WRXCHG2ST64_RTN_B32, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true,2); + appendOPR_VGPR(layout.ADDR,true,false); + appendOPR_VGPR_OR_ACCVGPR(layout.DATA0,true,false); + appendOPR_VGPR_OR_ACCVGPR(layout.DATA1,true,false); + appendOPR_DSMEM(0,true,false,1,true); + if (layout.OFFSET0 || layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,(layout.OFFSET1 << 8) + layout.OFFSET0)),true,false,false); + } + break; + case 54: case 57: case 58: case 59: case 60: // DS_READ_B32,DS_READ_I8,DS_READ_U8,DS_READ_I16,DS_READ_U16, + case 86: case 87: case 88: case 89: // DS_READ_U8_D16,DS_READ_U8_D16_HI,DS_READ_I8_D16,DS_READ_I8_D16_HI, + case 90: case 91: // DS_READ_U16_D16,DS_READ_U16_D16_HI, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true); + appendOPR_VGPR(layout.ADDR,true,false); + appendOPR_DSMEM(0,true,false,1,true); + if (layout.OFFSET0 || layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,(layout.OFFSET1 << 8) + layout.OFFSET0)),true,false,false); + } + break; + case 55: case 56: // DS_READ2_B32,DS_READ2ST64_B32, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true,2); + appendOPR_VGPR(layout.ADDR,true,false); + appendOPR_DSMEM(0,true,false,1,true); + if (layout.OFFSET0) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset0"),Result(u8,layout.OFFSET0)),true,false,false); + } + if (layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset1"),Result(u8,layout.OFFSET1)),true,false,false); + } + break; + case 61: // DS_SWIZZLE_B32, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true); + appendOPR_VGPR(layout.ADDR,true,false); + if (layout.OFFSET0 || layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,(layout.OFFSET1 << 8) + layout.OFFSET0)),true,false,false); + } + break; + case 62: case 63: // DS_PERMUTE_B32,DS_BPERMUTE_B32, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true); + appendOPR_VGPR(layout.ADDR,true,false); + appendOPR_VGPR_OR_ACCVGPR(layout.DATA0,true,false); + if (layout.OFFSET0 || layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,(layout.OFFSET1 << 8) + layout.OFFSET0)),true,false,false); + } + break; + case 64: case 65: case 66: case 67: case 68: // DS_ADD_U64,DS_SUB_U64,DS_RSUB_U64,DS_INC_U64,DS_DEC_U64, + case 69: case 70: case 71: case 72: case 73: // DS_MIN_I64,DS_MAX_I64,DS_MIN_U64,DS_MAX_U64,DS_AND_B64, + case 74: case 75: case 77: case 82: case 83: // DS_OR_B64,DS_XOR_B64,DS_WRITE_B64,DS_MIN_F64,DS_MAX_F64, + appendOPR_VGPR(layout.ADDR,true,false); + appendOPR_VGPR_OR_ACCVGPR(layout.DATA0,true,false,2); + appendOPR_DSMEM(0,true,false,1,true); + if (layout.OFFSET0 || layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,(layout.OFFSET1 << 8) + layout.OFFSET0)),true,false,false); + } + break; + case 76: case 80: case 81: // DS_MSKOR_B64,DS_CMPST_B64,DS_CMPST_F64, + appendOPR_VGPR(layout.ADDR,true,false); + appendOPR_VGPR_OR_ACCVGPR(layout.DATA0,true,false,2); + appendOPR_VGPR_OR_ACCVGPR(layout.DATA1,true,false,2); + appendOPR_DSMEM(0,true,false,1,true); + if (layout.OFFSET0 || layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,(layout.OFFSET1 << 8) + layout.OFFSET0)),true,false,false); + } + break; + case 78: case 79: // DS_WRITE2_B64,DS_WRITE2ST64_B64, + appendOPR_VGPR(layout.ADDR,true,false); + appendOPR_VGPR_OR_ACCVGPR(layout.DATA0,true,false,2); + appendOPR_VGPR_OR_ACCVGPR(layout.DATA1,true,false,2); + appendOPR_DSMEM(0,true,false,1,true); + if (layout.OFFSET0) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset0"),Result(u8,layout.OFFSET0)),true,false,false); + } + if (layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset1"),Result(u8,layout.OFFSET1)),true,false,false); + } + break; + case 92: // DS_ADD_F64, + appendOPR_VGPR(layout.ADDR,true,false); + appendOPR_VGPR_OR_ACCVGPR(layout.DATA0,true,false,2); + if (layout.OFFSET0 || layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,(layout.OFFSET1 << 8) + layout.OFFSET0)),true,false,false); + } + break; + case 96: case 97: case 98: case 99: // DS_ADD_RTN_U64,DS_SUB_RTN_U64,DS_RSUB_RTN_U64,DS_INC_RTN_U64, + case 100: case 101: case 102: case 103: // DS_DEC_RTN_U64,DS_MIN_RTN_I64,DS_MAX_RTN_I64,DS_MIN_RTN_U64, + case 104: case 105: case 106: case 107: // DS_MAX_RTN_U64,DS_AND_RTN_B64,DS_OR_RTN_B64,DS_XOR_RTN_B64, + case 109: case 114: case 115: case 126: // DS_WRXCHG_RTN_B64,DS_MIN_RTN_F64,DS_MAX_RTN_F64,DS_CONDXCHG32_RTN_B64, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true,2); + appendOPR_VGPR(layout.ADDR,true,false); + appendOPR_VGPR_OR_ACCVGPR(layout.DATA0,true,false,2); + appendOPR_DSMEM(0,true,false,1,true); + if (layout.OFFSET0 || layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,(layout.OFFSET1 << 8) + layout.OFFSET0)),true,false,false); + } + break; + case 108: case 112: case 113: // DS_MSKOR_RTN_B64,DS_CMPST_RTN_B64,DS_CMPST_RTN_F64, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true,2); + appendOPR_VGPR(layout.ADDR,true,false); + appendOPR_VGPR_OR_ACCVGPR(layout.DATA0,true,false,2); + appendOPR_VGPR_OR_ACCVGPR(layout.DATA1,true,false,2); + appendOPR_DSMEM(0,true,false,1,true); + if (layout.OFFSET0 || layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,(layout.OFFSET1 << 8) + layout.OFFSET0)),true,false,false); + } + break; + case 110: case 111: // DS_WRXCHG2_RTN_B64,DS_WRXCHG2ST64_RTN_B64, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true,4); + appendOPR_VGPR(layout.ADDR,true,false); + appendOPR_VGPR_OR_ACCVGPR(layout.DATA0,true,false,2); + appendOPR_VGPR_OR_ACCVGPR(layout.DATA1,true,false,2); + appendOPR_DSMEM(0,true,false,1,true); + if (layout.OFFSET0 || layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,(layout.OFFSET1 << 8) + layout.OFFSET0)),true,false,false); + } + break; + case 118: // DS_READ_B64, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true,2); + appendOPR_VGPR(layout.ADDR,true,false); + appendOPR_DSMEM(0,true,false,1,true); + if (layout.OFFSET0 || layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,(layout.OFFSET1 << 8) + layout.OFFSET0)),true,false,false); + } + break; + case 119: case 120: // DS_READ2_B64,DS_READ2ST64_B64, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true,4); + appendOPR_VGPR(layout.ADDR,true,false); + appendOPR_DSMEM(0,true,false,1,true); + if (layout.OFFSET0) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset0"),Result(u8,layout.OFFSET0)),true,false,false); + } + if (layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset1"),Result(u8,layout.OFFSET1)),true,false,false); + } + break; + case 124: // DS_ADD_RTN_F64, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true,2); + appendOPR_VGPR(layout.ADDR,true,false); + appendOPR_VGPR_OR_ACCVGPR(layout.DATA0,true,false,2); + if (layout.OFFSET0 || layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,(layout.OFFSET1 << 8) + layout.OFFSET0)),true,false,false); + } + break; + case 152: case 154: case 156: // DS_GWS_SEMA_RELEASE_ALL,DS_GWS_SEMA_V,DS_GWS_SEMA_P, + appendOPR_SDST_M0(124,true,false,1,true); + if (layout.OFFSET0 || layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,(layout.OFFSET1 << 8) + layout.OFFSET0)),true,false,false); + } + break; + case 153: case 155: case 157: // DS_GWS_INIT,DS_GWS_SEMA_BR,DS_GWS_BARRIER, + appendOPR_VGPR_OR_ACCVGPR(layout.DATA0,true,false); + appendOPR_SDST_M0(124,true,false,1,true); + if (layout.OFFSET0 || layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,(layout.OFFSET1 << 8) + layout.OFFSET0)),true,false,false); + } + break; + case 182: case 189: case 190: // DS_READ_ADDTID_B32,DS_CONSUME,DS_APPEND, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true); + appendOPR_DSMEM(0,true,false,1,true); + appendOPR_SDST_M0(124,true,false,1,true); + if (layout.OFFSET0 || layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,(layout.OFFSET1 << 8) + layout.OFFSET0)),true,false,false); + } + break; + case 222: // DS_WRITE_B96, + appendOPR_VGPR(layout.ADDR,true,false); + appendOPR_VGPR_OR_ACCVGPR(layout.DATA0,true,false,3); + appendOPR_DSMEM(0,true,false,1,true); + if (layout.OFFSET0 || layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,(layout.OFFSET1 << 8) + layout.OFFSET0)),true,false,false); + } + break; + case 223: // DS_WRITE_B128, + appendOPR_VGPR(layout.ADDR,true,false); + appendOPR_VGPR_OR_ACCVGPR(layout.DATA0,true,false,4); + appendOPR_DSMEM(0,true,false,1,true); + if (layout.OFFSET0 || layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,(layout.OFFSET1 << 8) + layout.OFFSET0)),true,false,false); + } + break; + case 254: // DS_READ_B96, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true,3); + appendOPR_VGPR(layout.ADDR,true,false); + appendOPR_DSMEM(0,true,false,1,true); + if (layout.OFFSET0 || layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,(layout.OFFSET1 << 8) + layout.OFFSET0)),true,false,false); + } + break; + case 255: // DS_READ_B128, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true,4); + appendOPR_VGPR(layout.ADDR,true,false); + appendOPR_DSMEM(0,true,false,1,true); + if (layout.OFFSET0 || layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,(layout.OFFSET1 << 8) + layout.OFFSET0)),true,false,false); + } + break; + } + } + + void InstructionDecoder_amdgpu_gfx90a::finalizeENC_FLATOperands() + { + layout_ENC_FLAT & layout = insn_layout.ENC_FLAT; + switch (layout.OP) { + case 16: case 17: case 18: case 19: // FLAT_LOAD_UBYTE,FLAT_LOAD_SBYTE,FLAT_LOAD_USHORT,FLAT_LOAD_SSHORT, + case 20: case 32: case 33: // FLAT_LOAD_DWORD,FLAT_LOAD_UBYTE_D16,FLAT_LOAD_UBYTE_D16_HI, + case 34: case 35: case 36: // FLAT_LOAD_SBYTE_D16,FLAT_LOAD_SBYTE_D16_HI,FLAT_LOAD_SHORT_D16, + case 37: // FLAT_LOAD_SHORT_D16_HI, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true); + appendOPR_VGPR(layout.ADDR,true,false,2); + appendOPR_FLAT_SCRATCH(0,true,false,1,true); + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::lgkmcnt,0,16),true,true,true); + break; + case 21: // FLAT_LOAD_DWORDX2, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true,2); + appendOPR_VGPR(layout.ADDR,true,false,2); + appendOPR_FLAT_SCRATCH(0,true,false,1,true); + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::lgkmcnt,0,16),true,true,true); + break; + case 22: // FLAT_LOAD_DWORDX3, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true,3); + appendOPR_VGPR(layout.ADDR,true,false,2); + appendOPR_FLAT_SCRATCH(0,true,false,1,true); + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::lgkmcnt,0,16),true,true,true); + break; + case 23: // FLAT_LOAD_DWORDX4, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true,4); + appendOPR_VGPR(layout.ADDR,true,false,2); + appendOPR_FLAT_SCRATCH(0,true,false,1,true); + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::lgkmcnt,0,16),true,true,true); + break; + case 24: case 25: case 26: // FLAT_STORE_BYTE,FLAT_STORE_BYTE_D16_HI,FLAT_STORE_SHORT, + case 27: case 28: // FLAT_STORE_SHORT_D16_HI,FLAT_STORE_DWORD, + appendOPR_VGPR(layout.ADDR,true,false,2); + appendOPR_VGPR_OR_ACCVGPR(layout.DATA,true,false); + appendOPR_FLAT_SCRATCH(0,true,false,1,true); + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::lgkmcnt,0,16),true,true,true); + break; + case 29: // FLAT_STORE_DWORDX2, + appendOPR_VGPR(layout.ADDR,true,false,2); + appendOPR_VGPR_OR_ACCVGPR(layout.DATA,true,false,2); + appendOPR_FLAT_SCRATCH(0,true,false,1,true); + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::lgkmcnt,0,16),true,true,true); + break; + case 30: // FLAT_STORE_DWORDX3, + appendOPR_VGPR(layout.ADDR,true,false,2); + appendOPR_VGPR_OR_ACCVGPR(layout.DATA,true,false,3); + appendOPR_FLAT_SCRATCH(0,true,false,1,true); + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::lgkmcnt,0,16),true,true,true); + break; + case 31: // FLAT_STORE_DWORDX4, + appendOPR_VGPR(layout.ADDR,true,false,2); + appendOPR_VGPR_OR_ACCVGPR(layout.DATA,true,false,4); + appendOPR_FLAT_SCRATCH(0,true,false,1,true); + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::lgkmcnt,0,16),true,true,true); + break; + case 64: case 66: case 67: case 68: // FLAT_ATOMIC_SWAP,FLAT_ATOMIC_ADD,FLAT_ATOMIC_SUB,FLAT_ATOMIC_SMIN, + case 69: case 70: case 71: case 72: // FLAT_ATOMIC_UMIN,FLAT_ATOMIC_SMAX,FLAT_ATOMIC_UMAX,FLAT_ATOMIC_AND, + case 73: case 74: case 75: case 76: // FLAT_ATOMIC_OR,FLAT_ATOMIC_XOR,FLAT_ATOMIC_INC,FLAT_ATOMIC_DEC, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true); + appendOPR_VGPR(layout.ADDR,true,false,2); + appendOPR_VGPR_OR_ACCVGPR(layout.DATA,true,false); + appendOPR_FLAT_SCRATCH(0,true,false,1,true); + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::lgkmcnt,0,16),true,true,true); + break; + case 65: case 79: case 80: // FLAT_ATOMIC_CMPSWAP,FLAT_ATOMIC_ADD_F64,FLAT_ATOMIC_MIN_F64, + case 81: case 96: case 98: case 99: // FLAT_ATOMIC_MAX_F64,FLAT_ATOMIC_SWAP_X2,FLAT_ATOMIC_ADD_X2,FLAT_ATOMIC_SUB_X2, + case 100: case 101: case 102: // FLAT_ATOMIC_SMIN_X2,FLAT_ATOMIC_UMIN_X2,FLAT_ATOMIC_SMAX_X2, + case 103: case 104: case 105: // FLAT_ATOMIC_UMAX_X2,FLAT_ATOMIC_AND_X2,FLAT_ATOMIC_OR_X2, + case 106: case 107: case 108: // FLAT_ATOMIC_XOR_X2,FLAT_ATOMIC_INC_X2,FLAT_ATOMIC_DEC_X2, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true,2); + appendOPR_VGPR(layout.ADDR,true,false,2); + appendOPR_VGPR_OR_ACCVGPR(layout.DATA,true,false,2); + appendOPR_FLAT_SCRATCH(0,true,false,1,true); + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::lgkmcnt,0,16),true,true,true); + break; + case 97: // FLAT_ATOMIC_CMPSWAP_X2, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true,4); + appendOPR_VGPR(layout.ADDR,true,false,2); + appendOPR_VGPR_OR_ACCVGPR(layout.DATA,true,false,4); + appendOPR_FLAT_SCRATCH(0,true,false,1,true); + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::lgkmcnt,0,16),true,true,true); + break; + } + } + + void InstructionDecoder_amdgpu_gfx90a::finalizeENC_FLAT_GLBLOperands() + { + layout_ENC_FLAT_GLBL & layout = insn_layout.ENC_FLAT_GLBL; + switch (layout.OP) { + case 16: case 17: case 18: case 19: // GLOBAL_LOAD_UBYTE,GLOBAL_LOAD_SBYTE,GLOBAL_LOAD_USHORT,GLOBAL_LOAD_SSHORT, + case 20: case 32: case 33: // GLOBAL_LOAD_DWORD,GLOBAL_LOAD_UBYTE_D16,GLOBAL_LOAD_UBYTE_D16_HI, + case 34: case 35: case 36: // GLOBAL_LOAD_SBYTE_D16,GLOBAL_LOAD_SBYTE_D16_HI,GLOBAL_LOAD_SHORT_D16, + case 37: // GLOBAL_LOAD_SHORT_D16_HI, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true); + if (layout.SADDR == 0x7f) { + appendOPR_VGPR(layout.ADDR,true,false,2); + } else { + appendOPR_VGPR(layout.ADDR,true,false); + } + if (layout.SADDR != 0x7f) { + appendOPR_SREG(layout.SADDR,true,false,2); + } + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::lgkmcnt,0,16),true,true,true); + break; + case 21: // GLOBAL_LOAD_DWORDX2, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true,2); + if (layout.SADDR == 0x7f) { + appendOPR_VGPR(layout.ADDR,true,false,2); + } else { + appendOPR_VGPR(layout.ADDR,true,false); + } + if (layout.SADDR != 0x7f) { + appendOPR_SREG(layout.SADDR,true,false,2); + } + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::lgkmcnt,0,16),true,true,true); + break; + case 22: // GLOBAL_LOAD_DWORDX3, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true,3); + if (layout.SADDR == 0x7f) { + appendOPR_VGPR(layout.ADDR,true,false,2); + } else { + appendOPR_VGPR(layout.ADDR,true,false); + } + if (layout.SADDR != 0x7f) { + appendOPR_SREG(layout.SADDR,true,false,2); + } + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::lgkmcnt,0,16),true,true,true); + break; + case 23: // GLOBAL_LOAD_DWORDX4, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true,4); + if (layout.SADDR == 0x7f) { + appendOPR_VGPR(layout.ADDR,true,false,2); + } else { + appendOPR_VGPR(layout.ADDR,true,false); + } + if (layout.SADDR != 0x7f) { + appendOPR_SREG(layout.SADDR,true,false,2); + } + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::lgkmcnt,0,16),true,true,true); + break; + case 24: case 25: case 26: // GLOBAL_STORE_BYTE,GLOBAL_STORE_BYTE_D16_HI,GLOBAL_STORE_SHORT, + case 27: case 28: // GLOBAL_STORE_SHORT_D16_HI,GLOBAL_STORE_DWORD, + if (layout.SADDR == 0x7f) { + appendOPR_VGPR(layout.ADDR,true,false,2); + } else { + appendOPR_VGPR(layout.ADDR,true,false); + } + appendOPR_VGPR_OR_ACCVGPR(layout.DATA,true,false); + if (layout.SADDR != 0x7f) { + appendOPR_SREG(layout.SADDR,true,false,2); + } + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::lgkmcnt,0,16),true,true,true); + break; + case 29: // GLOBAL_STORE_DWORDX2, + if (layout.SADDR == 0x7f) { + appendOPR_VGPR(layout.ADDR,true,false,2); + } else { + appendOPR_VGPR(layout.ADDR,true,false); + } + appendOPR_VGPR_OR_ACCVGPR(layout.DATA,true,false,2); + if (layout.SADDR != 0x7f) { + appendOPR_SREG(layout.SADDR,true,false,2); + } + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::lgkmcnt,0,16),true,true,true); + break; + case 30: // GLOBAL_STORE_DWORDX3, + if (layout.SADDR == 0x7f) { + appendOPR_VGPR(layout.ADDR,true,false,2); + } else { + appendOPR_VGPR(layout.ADDR,true,false); + } + appendOPR_VGPR_OR_ACCVGPR(layout.DATA,true,false,3); + if (layout.SADDR != 0x7f) { + appendOPR_SREG(layout.SADDR,true,false,2); + } + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::lgkmcnt,0,16),true,true,true); + break; + case 31: // GLOBAL_STORE_DWORDX4, + if (layout.SADDR == 0x7f) { + appendOPR_VGPR(layout.ADDR,true,false,2); + } else { + appendOPR_VGPR(layout.ADDR,true,false); + } + appendOPR_VGPR_OR_ACCVGPR(layout.DATA,true,false,4); + if (layout.SADDR != 0x7f) { + appendOPR_SREG(layout.SADDR,true,false,2); + } + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::lgkmcnt,0,16),true,true,true); + break; + case 64: case 66: case 67: case 68: // GLOBAL_ATOMIC_SWAP,GLOBAL_ATOMIC_ADD,GLOBAL_ATOMIC_SUB,GLOBAL_ATOMIC_SMIN, + case 69: case 70: case 71: case 72: // GLOBAL_ATOMIC_UMIN,GLOBAL_ATOMIC_SMAX,GLOBAL_ATOMIC_UMAX,GLOBAL_ATOMIC_AND, + case 73: case 74: case 75: case 76: // GLOBAL_ATOMIC_OR,GLOBAL_ATOMIC_XOR,GLOBAL_ATOMIC_INC,GLOBAL_ATOMIC_DEC, + case 77: case 78: // GLOBAL_ATOMIC_ADD_F32,GLOBAL_ATOMIC_PK_ADD_F16, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true); + if (layout.SADDR == 0x7f) { + appendOPR_VGPR(layout.ADDR,true,false,2); + } else { + appendOPR_VGPR(layout.ADDR,true,false); + } + appendOPR_VGPR_OR_ACCVGPR(layout.DATA,true,false); + if (layout.SADDR != 0x7f) { + appendOPR_SREG(layout.SADDR,true,false,2); + } + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::lgkmcnt,0,16),true,true,true); + break; + case 65: case 79: case 80: // GLOBAL_ATOMIC_CMPSWAP,GLOBAL_ATOMIC_ADD_F64,GLOBAL_ATOMIC_MIN_F64, + case 81: case 96: case 98: // GLOBAL_ATOMIC_MAX_F64,GLOBAL_ATOMIC_SWAP_X2,GLOBAL_ATOMIC_ADD_X2, + case 99: case 100: case 101: // GLOBAL_ATOMIC_SUB_X2,GLOBAL_ATOMIC_SMIN_X2,GLOBAL_ATOMIC_UMIN_X2, + case 102: case 103: case 104: // GLOBAL_ATOMIC_SMAX_X2,GLOBAL_ATOMIC_UMAX_X2,GLOBAL_ATOMIC_AND_X2, + case 105: case 106: case 107: // GLOBAL_ATOMIC_OR_X2,GLOBAL_ATOMIC_XOR_X2,GLOBAL_ATOMIC_INC_X2, + case 108: // GLOBAL_ATOMIC_DEC_X2, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true,2); + if (layout.SADDR == 0x7f) { + appendOPR_VGPR(layout.ADDR,true,false,2); + } else { + appendOPR_VGPR(layout.ADDR,true,false); + } + appendOPR_VGPR_OR_ACCVGPR(layout.DATA,true,false,2); + if (layout.SADDR != 0x7f) { + appendOPR_SREG(layout.SADDR,true,false,2); + } + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::lgkmcnt,0,16),true,true,true); + break; + case 97: // GLOBAL_ATOMIC_CMPSWAP_X2, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true,4); + if (layout.SADDR == 0x7f) { + appendOPR_VGPR(layout.ADDR,true,false,2); + } else { + appendOPR_VGPR(layout.ADDR,true,false); + } + appendOPR_VGPR_OR_ACCVGPR(layout.DATA,true,false,4); + if (layout.SADDR != 0x7f) { + appendOPR_SREG(layout.SADDR,true,false,2); + } + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::lgkmcnt,0,16),true,true,true); + break; + } + } + + void InstructionDecoder_amdgpu_gfx90a::finalizeENC_FLAT_SCRATCHOperands() + { + layout_ENC_FLAT_SCRATCH & layout = insn_layout.ENC_FLAT_SCRATCH; + switch (layout.OP) { + case 16: case 17: case 18: case 19: // SCRATCH_LOAD_UBYTE,SCRATCH_LOAD_SBYTE,SCRATCH_LOAD_USHORT,SCRATCH_LOAD_SSHORT, + case 20: case 32: case 33: // SCRATCH_LOAD_DWORD,SCRATCH_LOAD_UBYTE_D16,SCRATCH_LOAD_UBYTE_D16_HI, + case 34: case 35: case 36: // SCRATCH_LOAD_SBYTE_D16,SCRATCH_LOAD_SBYTE_D16_HI,SCRATCH_LOAD_SHORT_D16, + case 37: // SCRATCH_LOAD_SHORT_D16_HI, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true); + if (layout.SADDR == 0x7f) { + appendOPR_VGPR(layout.ADDR,true,false,2); + } else { + appendOPR_VGPR(layout.ADDR,true,false); + } + if (layout.SADDR != 0x7f) { + appendOPR_SREG(layout.SADDR,true,false,2); + } + appendOPR_FLAT_SCRATCH(0,true,false,1,true); + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::lgkmcnt,0,16),true,true,true); + break; + case 21: // SCRATCH_LOAD_DWORDX2, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true,2); + if (layout.SADDR == 0x7f) { + appendOPR_VGPR(layout.ADDR,true,false,2); + } else { + appendOPR_VGPR(layout.ADDR,true,false); + } + if (layout.SADDR != 0x7f) { + appendOPR_SREG(layout.SADDR,true,false,2); + } + appendOPR_FLAT_SCRATCH(0,true,false,1,true); + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::lgkmcnt,0,16),true,true,true); + break; + case 22: // SCRATCH_LOAD_DWORDX3, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true,3); + if (layout.SADDR == 0x7f) { + appendOPR_VGPR(layout.ADDR,true,false,2); + } else { + appendOPR_VGPR(layout.ADDR,true,false); + } + if (layout.SADDR != 0x7f) { + appendOPR_SREG(layout.SADDR,true,false,2); + } + appendOPR_FLAT_SCRATCH(0,true,false,1,true); + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::lgkmcnt,0,16),true,true,true); + break; + case 23: // SCRATCH_LOAD_DWORDX4, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true,4); + if (layout.SADDR == 0x7f) { + appendOPR_VGPR(layout.ADDR,true,false,2); + } else { + appendOPR_VGPR(layout.ADDR,true,false); + } + if (layout.SADDR != 0x7f) { + appendOPR_SREG(layout.SADDR,true,false,2); + } + appendOPR_FLAT_SCRATCH(0,true,false,1,true); + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::lgkmcnt,0,16),true,true,true); + break; + case 24: case 25: case 26: // SCRATCH_STORE_BYTE,SCRATCH_STORE_BYTE_D16_HI,SCRATCH_STORE_SHORT, + case 27: case 28: // SCRATCH_STORE_SHORT_D16_HI,SCRATCH_STORE_DWORD, + if (layout.SADDR == 0x7f) { + appendOPR_VGPR(layout.ADDR,true,false,2); + } else { + appendOPR_VGPR(layout.ADDR,true,false); + } + appendOPR_VGPR_OR_ACCVGPR(layout.DATA,true,false); + if (layout.SADDR != 0x7f) { + appendOPR_SREG(layout.SADDR,true,false,2); + } + appendOPR_FLAT_SCRATCH(0,true,false,1,true); + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::lgkmcnt,0,16),true,true,true); + break; + case 29: // SCRATCH_STORE_DWORDX2, + if (layout.SADDR == 0x7f) { + appendOPR_VGPR(layout.ADDR,true,false,2); + } else { + appendOPR_VGPR(layout.ADDR,true,false); + } + appendOPR_VGPR_OR_ACCVGPR(layout.DATA,true,false,2); + if (layout.SADDR != 0x7f) { + appendOPR_SREG(layout.SADDR,true,false,2); + } + appendOPR_FLAT_SCRATCH(0,true,false,1,true); + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::lgkmcnt,0,16),true,true,true); + break; + case 30: // SCRATCH_STORE_DWORDX3, + if (layout.SADDR == 0x7f) { + appendOPR_VGPR(layout.ADDR,true,false,2); + } else { + appendOPR_VGPR(layout.ADDR,true,false); + } + appendOPR_VGPR_OR_ACCVGPR(layout.DATA,true,false,3); + if (layout.SADDR != 0x7f) { + appendOPR_SREG(layout.SADDR,true,false,2); + } + appendOPR_FLAT_SCRATCH(0,true,false,1,true); + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::lgkmcnt,0,16),true,true,true); + break; + case 31: // SCRATCH_STORE_DWORDX4, + if (layout.SADDR == 0x7f) { + appendOPR_VGPR(layout.ADDR,true,false,2); + } else { + appendOPR_VGPR(layout.ADDR,true,false); + } + appendOPR_VGPR_OR_ACCVGPR(layout.DATA,true,false,4); + if (layout.SADDR != 0x7f) { + appendOPR_SREG(layout.SADDR,true,false,2); + } + appendOPR_FLAT_SCRATCH(0,true,false,1,true); + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::lgkmcnt,0,16),true,true,true); + break; + } + } + + void InstructionDecoder_amdgpu_gfx90a::finalizeENC_MIMGOperands() + { + layout_ENC_MIMG & layout = insn_layout.ENC_MIMG; + switch (layout.OP) { + case 0: case 1: case 2: case 3: // IMAGE_LOAD,IMAGE_LOAD_MIP,IMAGE_LOAD_PCK,IMAGE_LOAD_PCK_SGN, + case 4: case 5: // IMAGE_LOAD_MIP_PCK,IMAGE_LOAD_MIP_PCK_SGN, + appendOPR_VGPR_OR_ACCVGPR(layout.VDATA,false,true,4); + appendOPR_VGPR(layout.VADDR,true,false,4); + appendOPR_SREG(layout.SRSRC,true,false,8); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::vmcnt,0,36),true,true,true); + break; + case 8: case 9: case 10: case 11: // IMAGE_STORE,IMAGE_STORE_MIP,IMAGE_STORE_PCK,IMAGE_STORE_MIP_PCK, + appendOPR_VGPR_OR_ACCVGPR(layout.VDATA,true,false,4); + appendOPR_VGPR(layout.VADDR,true,false,4); + appendOPR_SREG(layout.SRSRC,true,false,8); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::vmcnt,0,36),true,true,true); + break; + case 14: // IMAGE_GET_RESINFO, + appendOPR_VGPR_OR_ACCVGPR(layout.VDATA,false,true,4); + appendOPR_VGPR(layout.VADDR,true,false); + appendOPR_SREG(layout.SRSRC,true,false,8); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::vmcnt,0,36),true,true,true); + break; + case 16: case 17: case 18: case 19: // IMAGE_ATOMIC_SWAP,IMAGE_ATOMIC_CMPSWAP,IMAGE_ATOMIC_ADD,IMAGE_ATOMIC_SUB, + case 20: case 21: case 22: case 23: // IMAGE_ATOMIC_SMIN,IMAGE_ATOMIC_UMIN,IMAGE_ATOMIC_SMAX,IMAGE_ATOMIC_UMAX, + case 24: case 25: case 26: case 27: // IMAGE_ATOMIC_AND,IMAGE_ATOMIC_OR,IMAGE_ATOMIC_XOR,IMAGE_ATOMIC_INC, + case 28: // IMAGE_ATOMIC_DEC, + appendOPR_VGPR_OR_ACCVGPR(layout.VDATA,true,true,4); + appendOPR_VGPR(layout.VADDR,true,false,4); + appendOPR_SREG(layout.SRSRC,true,false,8); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::vmcnt,0,36),true,true,true); + break; + case 32: // IMAGE_SAMPLE, + appendOPR_VGPR_OR_ACCVGPR(layout.VDATA,false,true,4); + appendOPR_VGPR(layout.VADDR,true,false,3); + appendOPR_SREG(layout.SRSRC,true,false,8); + appendOPR_SREG(layout.SSAMP,true,false,4); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::vmcnt,0,36),true,true,true); + break; + } + } + + void InstructionDecoder_amdgpu_gfx90a::finalizeENC_MTBUFOperands() + { + layout_ENC_MTBUF & layout = insn_layout.ENC_MTBUF; + switch (layout.OP) { + case 0: case 8: case 9: // TBUFFER_LOAD_FORMAT_X,TBUFFER_LOAD_FORMAT_D16_X,TBUFFER_LOAD_FORMAT_D16_XY, + appendOPR_VGPR_OR_ACCVGPR(layout.VDATA,false,true); + appendOPR_VGPR(layout.VADDR,true,false,2); + appendOPR_SREG(layout.SRSRC,true,false,4); + appendOPR_SSRC_NOLIT(layout.SOFFSET,true,false); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::vmcnt,0,36),true,true,true); + break; + case 1: case 10: case 11: // TBUFFER_LOAD_FORMAT_XY,TBUFFER_LOAD_FORMAT_D16_XYZ,TBUFFER_LOAD_FORMAT_D16_XYZW, + appendOPR_VGPR_OR_ACCVGPR(layout.VDATA,false,true,2); + appendOPR_VGPR(layout.VADDR,true,false,2); + appendOPR_SREG(layout.SRSRC,true,false,4); + appendOPR_SSRC_NOLIT(layout.SOFFSET,true,false); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::vmcnt,0,36),true,true,true); + break; + case 2: // TBUFFER_LOAD_FORMAT_XYZ, + appendOPR_VGPR_OR_ACCVGPR(layout.VDATA,false,true,3); + appendOPR_VGPR(layout.VADDR,true,false,2); + appendOPR_SREG(layout.SRSRC,true,false,4); + appendOPR_SSRC_NOLIT(layout.SOFFSET,true,false); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::vmcnt,0,36),true,true,true); + break; + case 3: // TBUFFER_LOAD_FORMAT_XYZW, + appendOPR_VGPR_OR_ACCVGPR(layout.VDATA,false,true,4); + appendOPR_VGPR(layout.VADDR,true,false,2); + appendOPR_SREG(layout.SRSRC,true,false,4); + appendOPR_SSRC_NOLIT(layout.SOFFSET,true,false); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::vmcnt,0,36),true,true,true); + break; + case 4: case 12: case 13: // TBUFFER_STORE_FORMAT_X,TBUFFER_STORE_FORMAT_D16_X,TBUFFER_STORE_FORMAT_D16_XY, + appendOPR_VGPR_OR_ACCVGPR(layout.VDATA,true,false); + appendOPR_VGPR(layout.VADDR,true,false,2); + appendOPR_SREG(layout.SRSRC,true,false,4); + appendOPR_SSRC_NOLIT(layout.SOFFSET,true,false); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::vmcnt,0,36),true,true,true); + break; + case 5: case 14: case 15: // TBUFFER_STORE_FORMAT_XY,TBUFFER_STORE_FORMAT_D16_XYZ,TBUFFER_STORE_FORMAT_D16_XYZW, + appendOPR_VGPR_OR_ACCVGPR(layout.VDATA,true,false,2); + appendOPR_VGPR(layout.VADDR,true,false,2); + appendOPR_SREG(layout.SRSRC,true,false,4); + appendOPR_SSRC_NOLIT(layout.SOFFSET,true,false); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::vmcnt,0,36),true,true,true); + break; + case 6: // TBUFFER_STORE_FORMAT_XYZ, + appendOPR_VGPR_OR_ACCVGPR(layout.VDATA,true,false,3); + appendOPR_VGPR(layout.VADDR,true,false,2); + appendOPR_SREG(layout.SRSRC,true,false,4); + appendOPR_SSRC_NOLIT(layout.SOFFSET,true,false); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::vmcnt,0,36),true,true,true); + break; + case 7: // TBUFFER_STORE_FORMAT_XYZW, + appendOPR_VGPR_OR_ACCVGPR(layout.VDATA,true,false,4); + appendOPR_VGPR(layout.VADDR,true,false,2); + appendOPR_SREG(layout.SRSRC,true,false,4); + appendOPR_SSRC_NOLIT(layout.SOFFSET,true,false); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::vmcnt,0,36),true,true,true); + break; + } + } + + void InstructionDecoder_amdgpu_gfx90a::finalizeENC_MUBUFOperands() + { + layout_ENC_MUBUF & layout = insn_layout.ENC_MUBUF; + switch (layout.OP) { + case 0: case 8: case 9: // BUFFER_LOAD_FORMAT_X,BUFFER_LOAD_FORMAT_D16_X,BUFFER_LOAD_FORMAT_D16_XY, + case 16: case 17: case 18: case 19: // BUFFER_LOAD_UBYTE,BUFFER_LOAD_SBYTE,BUFFER_LOAD_USHORT,BUFFER_LOAD_SSHORT, + case 20: case 32: case 33: // BUFFER_LOAD_DWORD,BUFFER_LOAD_UBYTE_D16,BUFFER_LOAD_UBYTE_D16_HI, + case 34: case 35: case 36: // BUFFER_LOAD_SBYTE_D16,BUFFER_LOAD_SBYTE_D16_HI,BUFFER_LOAD_SHORT_D16, + case 37: case 38: // BUFFER_LOAD_SHORT_D16_HI,BUFFER_LOAD_FORMAT_D16_HI_X, + appendOPR_VGPR_OR_ACCVGPR(layout.VDATA,false,true); + if (layout.IDXEN || layout.OFFEN) { + appendOPR_VGPR(layout.VADDR,true,false); + } else if (layout.OFFSET) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::off,1),false,false,false); + } + if (layout.IDXEN && layout.OFFEN) { + appendOPR_VGPR(layout.VADDR+1,true,false); + } + appendOPR_SREG(layout.SRSRC,true,false,4); + appendOPR_SSRC_NOLIT(layout.SOFFSET,true,false); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::vmcnt,0,36),true,true,true); + if (layout.IDXEN) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::idxen,1),false,false,false); + } + if (layout.OFFEN) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::offen,1),false,false,false); + } + if (layout.OFFSET) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,layout.OFFSET)),true,false,false); + } + break; + case 1: case 10: case 11: // BUFFER_LOAD_FORMAT_XY,BUFFER_LOAD_FORMAT_D16_XYZ,BUFFER_LOAD_FORMAT_D16_XYZW, + case 21: // BUFFER_LOAD_DWORDX2, + appendOPR_VGPR_OR_ACCVGPR(layout.VDATA,false,true,2); + if (layout.IDXEN || layout.OFFEN) { + appendOPR_VGPR(layout.VADDR,true,false); + } else if (layout.OFFSET) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::off,1),false,false,false); + } + if (layout.IDXEN && layout.OFFEN) { + appendOPR_VGPR(layout.VADDR+1,true,false); + } + appendOPR_SREG(layout.SRSRC,true,false,4); + appendOPR_SSRC_NOLIT(layout.SOFFSET,true,false); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::vmcnt,0,36),true,true,true); + if (layout.IDXEN) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::idxen,1),false,false,false); + } + if (layout.OFFEN) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::offen,1),false,false,false); + } + if (layout.OFFSET) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,layout.OFFSET)),true,false,false); + } + break; + case 2: case 22: // BUFFER_LOAD_FORMAT_XYZ,BUFFER_LOAD_DWORDX3, + appendOPR_VGPR_OR_ACCVGPR(layout.VDATA,false,true,3); + if (layout.IDXEN || layout.OFFEN) { + appendOPR_VGPR(layout.VADDR,true,false); + } else if (layout.OFFSET) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::off,1),false,false,false); + } + if (layout.IDXEN && layout.OFFEN) { + appendOPR_VGPR(layout.VADDR+1,true,false); + } + appendOPR_SREG(layout.SRSRC,true,false,4); + appendOPR_SSRC_NOLIT(layout.SOFFSET,true,false); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::vmcnt,0,36),true,true,true); + if (layout.IDXEN) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::idxen,1),false,false,false); + } + if (layout.OFFEN) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::offen,1),false,false,false); + } + if (layout.OFFSET) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,layout.OFFSET)),true,false,false); + } + break; + case 3: case 23: // BUFFER_LOAD_FORMAT_XYZW,BUFFER_LOAD_DWORDX4, + appendOPR_VGPR_OR_ACCVGPR(layout.VDATA,false,true,4); + if (layout.IDXEN || layout.OFFEN) { + appendOPR_VGPR(layout.VADDR,true,false); + } else if (layout.OFFSET) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::off,1),false,false,false); + } + if (layout.IDXEN && layout.OFFEN) { + appendOPR_VGPR(layout.VADDR+1,true,false); + } + appendOPR_SREG(layout.SRSRC,true,false,4); + appendOPR_SSRC_NOLIT(layout.SOFFSET,true,false); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::vmcnt,0,36),true,true,true); + if (layout.IDXEN) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::idxen,1),false,false,false); + } + if (layout.OFFEN) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::offen,1),false,false,false); + } + if (layout.OFFSET) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,layout.OFFSET)),true,false,false); + } + break; + case 4: case 12: case 13: // BUFFER_STORE_FORMAT_X,BUFFER_STORE_FORMAT_D16_X,BUFFER_STORE_FORMAT_D16_XY, + case 24: case 25: case 26: // BUFFER_STORE_BYTE,BUFFER_STORE_BYTE_D16_HI,BUFFER_STORE_SHORT, + case 27: case 28: case 39: // BUFFER_STORE_SHORT_D16_HI,BUFFER_STORE_DWORD,BUFFER_STORE_FORMAT_D16_HI_X, + appendOPR_VGPR_OR_ACCVGPR(layout.VDATA,true,false); + if (layout.IDXEN || layout.OFFEN) { + appendOPR_VGPR(layout.VADDR,true,false); + } else if (layout.OFFSET) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::off,1),false,false,false); + } + if (layout.IDXEN && layout.OFFEN) { + appendOPR_VGPR(layout.VADDR+1,true,false); + } + appendOPR_SREG(layout.SRSRC,true,false,4); + appendOPR_SSRC_NOLIT(layout.SOFFSET,true,false); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::vmcnt,0,36),true,true,true); + if (layout.IDXEN) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::idxen,1),false,false,false); + } + if (layout.OFFEN) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::offen,1),false,false,false); + } + if (layout.OFFSET) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,layout.OFFSET)),true,false,false); + } + break; + case 5: case 14: case 15: // BUFFER_STORE_FORMAT_XY,BUFFER_STORE_FORMAT_D16_XYZ,BUFFER_STORE_FORMAT_D16_XYZW, + case 29: // BUFFER_STORE_DWORDX2, + appendOPR_VGPR_OR_ACCVGPR(layout.VDATA,true,false,2); + if (layout.IDXEN || layout.OFFEN) { + appendOPR_VGPR(layout.VADDR,true,false); + } else if (layout.OFFSET) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::off,1),false,false,false); + } + if (layout.IDXEN && layout.OFFEN) { + appendOPR_VGPR(layout.VADDR+1,true,false); + } + appendOPR_SREG(layout.SRSRC,true,false,4); + appendOPR_SSRC_NOLIT(layout.SOFFSET,true,false); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::vmcnt,0,36),true,true,true); + if (layout.IDXEN) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::idxen,1),false,false,false); + } + if (layout.OFFEN) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::offen,1),false,false,false); + } + if (layout.OFFSET) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,layout.OFFSET)),true,false,false); + } + break; + case 6: case 30: // BUFFER_STORE_FORMAT_XYZ,BUFFER_STORE_DWORDX3, + appendOPR_VGPR_OR_ACCVGPR(layout.VDATA,true,false,3); + if (layout.IDXEN || layout.OFFEN) { + appendOPR_VGPR(layout.VADDR,true,false); + } else if (layout.OFFSET) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::off,1),false,false,false); + } + if (layout.IDXEN && layout.OFFEN) { + appendOPR_VGPR(layout.VADDR+1,true,false); + } + appendOPR_SREG(layout.SRSRC,true,false,4); + appendOPR_SSRC_NOLIT(layout.SOFFSET,true,false); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::vmcnt,0,36),true,true,true); + if (layout.IDXEN) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::idxen,1),false,false,false); + } + if (layout.OFFEN) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::offen,1),false,false,false); + } + if (layout.OFFSET) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,layout.OFFSET)),true,false,false); + } + break; + case 7: case 31: // BUFFER_STORE_FORMAT_XYZW,BUFFER_STORE_DWORDX4, + appendOPR_VGPR_OR_ACCVGPR(layout.VDATA,true,false,4); + if (layout.IDXEN || layout.OFFEN) { + appendOPR_VGPR(layout.VADDR,true,false); + } else if (layout.OFFSET) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::off,1),false,false,false); + } + if (layout.IDXEN && layout.OFFEN) { + appendOPR_VGPR(layout.VADDR+1,true,false); + } + appendOPR_SREG(layout.SRSRC,true,false,4); + appendOPR_SSRC_NOLIT(layout.SOFFSET,true,false); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::vmcnt,0,36),true,true,true); + if (layout.IDXEN) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::idxen,1),false,false,false); + } + if (layout.OFFEN) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::offen,1),false,false,false); + } + if (layout.OFFSET) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,layout.OFFSET)),true,false,false); + } + break; + case 40: case 41: case 62: case 63: // BUFFER_WBL2,BUFFER_INVL2,BUFFER_WBINVL1,BUFFER_WBINVL1_VOL, + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::vmcnt,0,36),true,true,true); + if (layout.IDXEN) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::idxen,1),false,false,false); + } + if (layout.OFFEN) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::offen,1),false,false,false); + } + if (layout.OFFSET) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,layout.OFFSET)),true,false,false); + } + break; + case 61: // BUFFER_STORE_LDS_DWORD, + appendOPR_SREG(layout.SRSRC,true,false,4); + appendOPR_SSRC_NOLIT(layout.SOFFSET,true,false); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::vmcnt,0,36),true,true,true); + if (layout.IDXEN) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::idxen,1),false,false,false); + } + if (layout.OFFEN) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::offen,1),false,false,false); + } + if (layout.OFFSET) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,layout.OFFSET)),true,false,false); + } + break; + case 64: case 66: case 67: case 68: // BUFFER_ATOMIC_SWAP,BUFFER_ATOMIC_ADD,BUFFER_ATOMIC_SUB,BUFFER_ATOMIC_SMIN, + case 69: case 70: case 71: case 72: // BUFFER_ATOMIC_UMIN,BUFFER_ATOMIC_SMAX,BUFFER_ATOMIC_UMAX,BUFFER_ATOMIC_AND, + case 73: case 74: case 75: case 76: // BUFFER_ATOMIC_OR,BUFFER_ATOMIC_XOR,BUFFER_ATOMIC_INC,BUFFER_ATOMIC_DEC, + case 77: case 78: // BUFFER_ATOMIC_ADD_F32,BUFFER_ATOMIC_PK_ADD_F16, + appendOPR_VGPR_OR_ACCVGPR(layout.VDATA,true,true); + if (layout.IDXEN || layout.OFFEN) { + appendOPR_VGPR(layout.VADDR,true,false); + } else if (layout.OFFSET) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::off,1),false,false,false); + } + if (layout.IDXEN && layout.OFFEN) { + appendOPR_VGPR(layout.VADDR+1,true,false); + } + appendOPR_SREG(layout.SRSRC,true,false,4); + appendOPR_SSRC_NOLIT(layout.SOFFSET,true,false); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::vmcnt,0,36),true,true,true); + if (layout.IDXEN) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::idxen,1),false,false,false); + } + if (layout.OFFEN) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::offen,1),false,false,false); + } + if (layout.OFFSET) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,layout.OFFSET)),true,false,false); + } + break; + case 65: case 79: case 80: // BUFFER_ATOMIC_CMPSWAP,BUFFER_ATOMIC_ADD_F64,BUFFER_ATOMIC_MIN_F64, + case 81: case 96: case 98: // BUFFER_ATOMIC_MAX_F64,BUFFER_ATOMIC_SWAP_X2,BUFFER_ATOMIC_ADD_X2, + case 99: case 100: case 101: // BUFFER_ATOMIC_SUB_X2,BUFFER_ATOMIC_SMIN_X2,BUFFER_ATOMIC_UMIN_X2, + case 102: case 103: case 104: // BUFFER_ATOMIC_SMAX_X2,BUFFER_ATOMIC_UMAX_X2,BUFFER_ATOMIC_AND_X2, + case 105: case 106: case 107: // BUFFER_ATOMIC_OR_X2,BUFFER_ATOMIC_XOR_X2,BUFFER_ATOMIC_INC_X2, + case 108: // BUFFER_ATOMIC_DEC_X2, + appendOPR_VGPR_OR_ACCVGPR(layout.VDATA,true,true,2); + if (layout.IDXEN || layout.OFFEN) { + appendOPR_VGPR(layout.VADDR,true,false); + } else if (layout.OFFSET) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::off,1),false,false,false); + } + if (layout.IDXEN && layout.OFFEN) { + appendOPR_VGPR(layout.VADDR+1,true,false); + } + appendOPR_SREG(layout.SRSRC,true,false,4); + appendOPR_SSRC_NOLIT(layout.SOFFSET,true,false); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::vmcnt,0,36),true,true,true); + if (layout.IDXEN) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::idxen,1),false,false,false); + } + if (layout.OFFEN) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::offen,1),false,false,false); + } + if (layout.OFFSET) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,layout.OFFSET)),true,false,false); + } + break; + case 97: // BUFFER_ATOMIC_CMPSWAP_X2, + appendOPR_VGPR_OR_ACCVGPR(layout.VDATA,true,true,4); + if (layout.IDXEN || layout.OFFEN) { + appendOPR_VGPR(layout.VADDR,true,false); + } else if (layout.OFFSET) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::off,1),false,false,false); + } + if (layout.IDXEN && layout.OFFEN) { + appendOPR_VGPR(layout.VADDR+1,true,false); + } + appendOPR_SREG(layout.SRSRC,true,false,4); + appendOPR_SSRC_NOLIT(layout.SOFFSET,true,false); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::vmcnt,0,36),true,true,true); + if (layout.IDXEN) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::idxen,1),false,false,false); + } + if (layout.OFFEN) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::offen,1),false,false,false); + } + if (layout.OFFSET) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,layout.OFFSET)),true,false,false); + } + break; + } + } + + void InstructionDecoder_amdgpu_gfx90a::finalizeENC_SMEMOperands() + { + layout_ENC_SMEM & layout = insn_layout.ENC_SMEM; + switch (layout.OP) { + case 0: case 5: // S_LOAD_DWORD,S_SCRATCH_LOAD_DWORD, + appendOPR_SREG(layout.SDATA,false,true); + appendOPR_SREG(layout.SBASE,true,false,2); + processOPR_SMEM_OFFSET(layout); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::lgkmcnt,0,16),true,true,true); + break; + case 1: case 6: // S_LOAD_DWORDX2,S_SCRATCH_LOAD_DWORDX2, + appendOPR_SREG(layout.SDATA,false,true,2); + appendOPR_SREG(layout.SBASE,true,false,2); + processOPR_SMEM_OFFSET(layout); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::lgkmcnt,0,16),true,true,true); + break; + case 2: case 7: // S_LOAD_DWORDX4,S_SCRATCH_LOAD_DWORDX4, + appendOPR_SREG(layout.SDATA,false,true,4); + appendOPR_SREG(layout.SBASE,true,false,2); + processOPR_SMEM_OFFSET(layout); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::lgkmcnt,0,16),true,true,true); + break; + case 3: // S_LOAD_DWORDX8, + appendOPR_SREG(layout.SDATA,false,true,8); + appendOPR_SREG(layout.SBASE,true,false,2); + processOPR_SMEM_OFFSET(layout); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::lgkmcnt,0,16),true,true,true); + break; + case 4: // S_LOAD_DWORDX16, + appendOPR_SREG(layout.SDATA,false,true,16); + appendOPR_SREG(layout.SBASE,true,false,2); + processOPR_SMEM_OFFSET(layout); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::lgkmcnt,0,16),true,true,true); + break; + case 8: // S_BUFFER_LOAD_DWORD, + appendOPR_SREG(layout.SDATA,false,true); + appendOPR_SREG(layout.SBASE,true,false,4); + processOPR_SMEM_OFFSET(layout); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::lgkmcnt,0,16),true,true,true); + break; + case 9: // S_BUFFER_LOAD_DWORDX2, + appendOPR_SREG(layout.SDATA,false,true,2); + appendOPR_SREG(layout.SBASE,true,false,4); + processOPR_SMEM_OFFSET(layout); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::lgkmcnt,0,16),true,true,true); + break; + case 10: // S_BUFFER_LOAD_DWORDX4, + appendOPR_SREG(layout.SDATA,false,true,4); + appendOPR_SREG(layout.SBASE,true,false,4); + processOPR_SMEM_OFFSET(layout); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::lgkmcnt,0,16),true,true,true); + break; + case 11: // S_BUFFER_LOAD_DWORDX8, + appendOPR_SREG(layout.SDATA,false,true,8); + appendOPR_SREG(layout.SBASE,true,false,4); + processOPR_SMEM_OFFSET(layout); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::lgkmcnt,0,16),true,true,true); + break; + case 12: // S_BUFFER_LOAD_DWORDX16, + appendOPR_SREG(layout.SDATA,false,true,16); + appendOPR_SREG(layout.SBASE,true,false,4); + processOPR_SMEM_OFFSET(layout); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::lgkmcnt,0,16),true,true,true); + break; + case 16: case 21: // S_STORE_DWORD,S_SCRATCH_STORE_DWORD, + appendOPR_SREG(layout.SDATA,true,false); + appendOPR_SREG(layout.SBASE,true,false,2); + processOPR_SMEM_OFFSET(layout); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::lgkmcnt,0,16),true,true,true); + break; + case 17: case 22: // S_STORE_DWORDX2,S_SCRATCH_STORE_DWORDX2, + appendOPR_SREG(layout.SDATA,true,false,2); + appendOPR_SREG(layout.SBASE,true,false,2); + processOPR_SMEM_OFFSET(layout); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::lgkmcnt,0,16),true,true,true); + break; + case 18: case 23: // S_STORE_DWORDX4,S_SCRATCH_STORE_DWORDX4, + appendOPR_SREG(layout.SDATA,true,false,4); + appendOPR_SREG(layout.SBASE,true,false,2); + processOPR_SMEM_OFFSET(layout); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::lgkmcnt,0,16),true,true,true); + break; + case 24: // S_BUFFER_STORE_DWORD, + appendOPR_SREG(layout.SDATA,true,false); + appendOPR_SREG(layout.SBASE,true,false,4); + processOPR_SMEM_OFFSET(layout); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::lgkmcnt,0,16),true,true,true); + break; + case 25: // S_BUFFER_STORE_DWORDX2, + appendOPR_SREG(layout.SDATA,true,false,2); + appendOPR_SREG(layout.SBASE,true,false,4); + processOPR_SMEM_OFFSET(layout); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::lgkmcnt,0,16),true,true,true); + break; + case 26: // S_BUFFER_STORE_DWORDX4, + appendOPR_SREG(layout.SDATA,true,false,4); + appendOPR_SREG(layout.SBASE,true,false,4); + processOPR_SMEM_OFFSET(layout); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::lgkmcnt,0,16),true,true,true); + break; + case 32: case 33: case 34: case 35: // S_DCACHE_INV,S_DCACHE_WB,S_DCACHE_INV_VOL,S_DCACHE_WB_VOL, + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::lgkmcnt,0,16),true,true,true); + break; + case 36: case 37: // S_MEMTIME,S_MEMREALTIME, + appendOPR_SREG(layout.SDATA,false,true,2); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::lgkmcnt,0,16),true,true,true); + break; + case 38: // S_ATC_PROBE, + appendOPR_SIMM8(layout.SDATA,true,false); + appendOPR_SREG(layout.SBASE,true,false,2); + processOPR_SMEM_OFFSET(layout); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::lgkmcnt,0,16),true,true,true); + break; + case 39: // S_ATC_PROBE_BUFFER, + appendOPR_SIMM8(layout.SDATA,true,false); + appendOPR_SREG(layout.SBASE,true,false,4); + processOPR_SMEM_OFFSET(layout); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::lgkmcnt,0,16),true,true,true); + break; + case 40: case 41: // S_DCACHE_DISCARD,S_DCACHE_DISCARD_X2, + appendOPR_SREG(layout.SBASE,true,false,2); + processOPR_SMEM_OFFSET(layout); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::lgkmcnt,0,16),true,true,true); + break; + case 64: case 66: case 67: // S_BUFFER_ATOMIC_SWAP,S_BUFFER_ATOMIC_ADD,S_BUFFER_ATOMIC_SUB, + case 68: case 69: case 70: // S_BUFFER_ATOMIC_SMIN,S_BUFFER_ATOMIC_UMIN,S_BUFFER_ATOMIC_SMAX, + case 71: case 72: case 73: // S_BUFFER_ATOMIC_UMAX,S_BUFFER_ATOMIC_AND,S_BUFFER_ATOMIC_OR, + case 74: case 75: case 76: // S_BUFFER_ATOMIC_XOR,S_BUFFER_ATOMIC_INC,S_BUFFER_ATOMIC_DEC, + appendOPR_SREG(layout.SDATA,true,true); + appendOPR_SREG(layout.SBASE,true,false,4); + processOPR_SMEM_OFFSET(layout); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::lgkmcnt,0,16),true,true,true); + break; + case 65: case 96: case 98: // S_BUFFER_ATOMIC_CMPSWAP,S_BUFFER_ATOMIC_SWAP_X2,S_BUFFER_ATOMIC_ADD_X2, + case 99: case 100: case 101: // S_BUFFER_ATOMIC_SUB_X2,S_BUFFER_ATOMIC_SMIN_X2,S_BUFFER_ATOMIC_UMIN_X2, + case 102: case 103: case 104: // S_BUFFER_ATOMIC_SMAX_X2,S_BUFFER_ATOMIC_UMAX_X2,S_BUFFER_ATOMIC_AND_X2, + case 105: case 106: case 107: // S_BUFFER_ATOMIC_OR_X2,S_BUFFER_ATOMIC_XOR_X2,S_BUFFER_ATOMIC_INC_X2, + case 108: // S_BUFFER_ATOMIC_DEC_X2, + appendOPR_SREG(layout.SDATA,true,true,2); + appendOPR_SREG(layout.SBASE,true,false,4); + processOPR_SMEM_OFFSET(layout); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::lgkmcnt,0,16),true,true,true); + break; + case 97: // S_BUFFER_ATOMIC_CMPSWAP_X2, + appendOPR_SREG(layout.SDATA,true,true,4); + appendOPR_SREG(layout.SBASE,true,false,4); + processOPR_SMEM_OFFSET(layout); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::lgkmcnt,0,16),true,true,true); + break; + case 128: case 130: case 131: case 132: // S_ATOMIC_SWAP,S_ATOMIC_ADD,S_ATOMIC_SUB,S_ATOMIC_SMIN, + case 133: case 134: case 135: case 136: // S_ATOMIC_UMIN,S_ATOMIC_SMAX,S_ATOMIC_UMAX,S_ATOMIC_AND, + case 137: case 138: case 139: case 140: // S_ATOMIC_OR,S_ATOMIC_XOR,S_ATOMIC_INC,S_ATOMIC_DEC, + appendOPR_SREG(layout.SDATA,true,true); + appendOPR_SREG(layout.SBASE,true,false,2); + processOPR_SMEM_OFFSET(layout); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::lgkmcnt,0,16),true,true,true); + break; + case 129: case 160: case 162: case 163: // S_ATOMIC_CMPSWAP,S_ATOMIC_SWAP_X2,S_ATOMIC_ADD_X2,S_ATOMIC_SUB_X2, + case 164: case 165: case 166: case 167: // S_ATOMIC_SMIN_X2,S_ATOMIC_UMIN_X2,S_ATOMIC_SMAX_X2,S_ATOMIC_UMAX_X2, + case 168: case 169: case 170: case 171: // S_ATOMIC_AND_X2,S_ATOMIC_OR_X2,S_ATOMIC_XOR_X2,S_ATOMIC_INC_X2, + case 172: // S_ATOMIC_DEC_X2, + appendOPR_SREG(layout.SDATA,true,true,2); + appendOPR_SREG(layout.SBASE,true,false,2); + processOPR_SMEM_OFFSET(layout); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::lgkmcnt,0,16),true,true,true); + break; + case 161: // S_ATOMIC_CMPSWAP_X2, + appendOPR_SREG(layout.SDATA,true,true,4); + appendOPR_SREG(layout.SBASE,true,false,2); + processOPR_SMEM_OFFSET(layout); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::lgkmcnt,0,16),true,true,true); + break; + } + } + + void InstructionDecoder_amdgpu_gfx90a::finalizeENC_SOP1Operands() + { + layout_ENC_SOP1 & layout = insn_layout.ENC_SOP1; + switch (layout.OP) { + case 0: case 8: case 14: case 16: case 18: // S_MOV_B32,S_BREV_B32,S_FF0_I32_B32,S_FF1_I32_B32,S_FLBIT_I32_B32, + case 20: case 22: case 23: // S_FLBIT_I32,S_SEXT_I32_I8,S_SEXT_I32_I16, + appendOPR_SDST(layout.SDST,false,true); + appendOPR_SSRC(layout.SSRC0,true,false); + break; + case 1: case 9: // S_MOV_B64,S_BREV_B64, + appendOPR_SDST(layout.SDST,false,true,2); + appendOPR_SSRC(layout.SSRC0,true,false,2); + break; + case 2: // S_CMOV_B32, + appendOPR_SDST(layout.SDST,true,true); + appendOPR_SSRC(layout.SSRC0,true,false); + appendOPR_SSRC_SPECIAL_SCC(253,true,false,1,true); + break; + case 3: // S_CMOV_B64, + appendOPR_SDST(layout.SDST,true,true,2); + appendOPR_SSRC(layout.SSRC0,true,false,2); + appendOPR_SSRC_SPECIAL_SCC(253,true,false,1,true); + break; + case 4: case 6: case 10: case 12: case 40: // S_NOT_B32,S_WQM_B32,S_BCNT0_I32_B32,S_BCNT1_I32_B32,S_QUADMASK_B32, + case 48: // S_ABS_I32, + appendOPR_SDST(layout.SDST,false,true); + appendOPR_SSRC(layout.SSRC0,true,false); + appendOPR_SSRC_SPECIAL_SCC(253,false,true,1,true); + break; + case 5: case 7: case 41: // S_NOT_B64,S_WQM_B64,S_QUADMASK_B64, + appendOPR_SDST(layout.SDST,false,true,2); + appendOPR_SSRC(layout.SSRC0,true,false,2); + appendOPR_SSRC_SPECIAL_SCC(253,false,true,1,true); + break; + case 11: case 13: // S_BCNT0_I32_B64,S_BCNT1_I32_B64, + appendOPR_SDST(layout.SDST,false,true); + appendOPR_SSRC(layout.SSRC0,true,false,2); + appendOPR_SSRC_SPECIAL_SCC(253,false,true,1,true); + break; + case 15: case 17: case 19: case 21: // S_FF0_I32_B64,S_FF1_I32_B64,S_FLBIT_I32_B64,S_FLBIT_I32_I64, + appendOPR_SDST(layout.SDST,false,true); + appendOPR_SSRC(layout.SSRC0,true,false,2); + break; + case 24: case 26: // S_BITSET0_B32,S_BITSET1_B32, + appendOPR_SDST(layout.SDST,true,true); + appendOPR_SSRC(layout.SSRC0,true,false); + break; + case 25: case 27: // S_BITSET0_B64,S_BITSET1_B64, + appendOPR_SDST(layout.SDST,true,true,2); + appendOPR_SSRC(layout.SSRC0,true,false); + break; + case 28: // S_GETPC_B64, + appendOPR_SDST(layout.SDST,false,true,2); + appendOPR_PC(0,true,false,1,true); + break; + case 29: // S_SETPC_B64, + setBranch(); + setModifyPC(); + appendOPR_SREG(layout.SSRC0,true,false,2); + appendOPR_PC(0,false,true,1,true); + break; + case 30: // S_SWAPPC_B64, + setBranch(); + setModifyPC(); + appendOPR_SDST(layout.SDST,false,true,2); + appendOPR_SREG(layout.SSRC0,true,false,2); + appendOPR_PC(0,false,true,1,true); + appendOPR_PC(0,true,false,1,true); + break; + case 31: // S_RFE_B64, + appendOPR_SREG(layout.SSRC0,true,false,2); + appendOPR_PC(0,false,true,1,true); + break; + case 32: case 33: case 34: case 35: // S_AND_SAVEEXEC_B64,S_OR_SAVEEXEC_B64,S_XOR_SAVEEXEC_B64,S_ANDN2_SAVEEXEC_B64, + case 36: case 37: case 38: // S_ORN2_SAVEEXEC_B64,S_NAND_SAVEEXEC_B64,S_NOR_SAVEEXEC_B64, + case 39: case 51: case 52: // S_XNOR_SAVEEXEC_B64,S_ANDN1_SAVEEXEC_B64,S_ORN1_SAVEEXEC_B64, + case 53: case 54: // S_ANDN1_WREXEC_B64,S_ANDN2_WREXEC_B64, + appendOPR_SREG(layout.SDST,false,true,2); + appendOPR_SSRC(layout.SSRC0,true,false,2); + appendOPR_SDST_EXEC(126,false,true,1,true); + appendOPR_SSRC_SPECIAL_SCC(253,false,true,1,true); + appendOPR_SDST_EXEC(126,true,false,1,true); + break; + case 42: // S_MOVRELS_B32, + appendOPR_SDST(layout.SDST,false,true); + appendOPR_SREG(layout.SSRC0,true,false); + appendOPR_SDST_M0(124,true,false,1,true); + break; + case 43: // S_MOVRELS_B64, + appendOPR_SDST(layout.SDST,false,true,2); + appendOPR_SREG(layout.SSRC0,true,false,2); + appendOPR_SDST_M0(124,true,false,1,true); + break; + case 44: // S_MOVRELD_B32, + appendOPR_SREG(layout.SDST,false,true); + appendOPR_SSRC(layout.SSRC0,true,false); + appendOPR_SDST_M0(124,true,false,1,true); + break; + case 45: // S_MOVRELD_B64, + appendOPR_SREG(layout.SDST,false,true,2); + appendOPR_SSRC(layout.SSRC0,true,false,2); + appendOPR_SDST_M0(124,true,false,1,true); + break; + case 46: // S_CBRANCH_JOIN, + appendOPR_SREG(layout.SSRC0,true,false); + appendOPR_SDST_EXEC(126,false,true,1,true); + appendOPR_PC(0,false,true,1,true); + break; + case 50: // S_SET_GPR_IDX_IDX, + appendOPR_SSRC(layout.SSRC0,true,false); + appendOPR_SDST_M0(124,false,true,1,true); + appendOPR_SDST_M0(124,true,false,1,true); + break; + case 55: // S_BITREPLICATE_B64_B32, + appendOPR_SDST(layout.SDST,false,true,2); + appendOPR_SSRC(layout.SSRC0,true,false); + break; + } + } + + void InstructionDecoder_amdgpu_gfx90a::finalizeENC_SOP2Operands() + { + layout_ENC_SOP2 & layout = insn_layout.ENC_SOP2; + switch (layout.OP) { + case 0: case 1: case 2: case 3: case 6: case 7: // S_ADD_U32,S_SUB_U32,S_ADD_I32,S_SUB_I32,S_MIN_I32,S_MIN_U32, + case 8: case 9: case 12: case 14: case 16: // S_MAX_I32,S_MAX_U32,S_AND_B32,S_OR_B32,S_XOR_B32, + case 18: case 20: case 22: case 24: case 26: // S_ANDN2_B32,S_ORN2_B32,S_NAND_B32,S_NOR_B32,S_XNOR_B32, + case 28: case 30: case 32: case 37: case 38: // S_LSHL_B32,S_LSHR_B32,S_ASHR_I32,S_BFE_U32,S_BFE_I32, + case 42: case 46: case 47: case 48: // S_ABSDIFF_I32,S_LSHL1_ADD_U32,S_LSHL2_ADD_U32,S_LSHL3_ADD_U32, + case 49: // S_LSHL4_ADD_U32, + appendOPR_SDST(layout.SDST,false,true); + appendOPR_SSRC(layout.SSRC0,true,false); + appendOPR_SSRC(layout.SSRC1,true,false); + appendOPR_SSRC_SPECIAL_SCC(253,false,true,1,true); + break; + case 4: case 5: // S_ADDC_U32,S_SUBB_U32, + appendOPR_SDST(layout.SDST,false,true); + appendOPR_SSRC(layout.SSRC0,true,false); + appendOPR_SSRC(layout.SSRC1,true,false); + appendOPR_SSRC_SPECIAL_SCC(253,false,true,1,true); + appendOPR_SSRC_SPECIAL_SCC(253,true,false,1,true); + break; + case 10: // S_CSELECT_B32, + appendOPR_SDST(layout.SDST,false,true); + appendOPR_SSRC(layout.SSRC0,true,false); + appendOPR_SSRC(layout.SSRC1,true,false); + appendOPR_SSRC_SPECIAL_SCC(253,true,false,1,true); + break; + case 11: // S_CSELECT_B64, + appendOPR_SDST(layout.SDST,false,true,2); + appendOPR_SSRC(layout.SSRC0,true,false,2); + appendOPR_SSRC(layout.SSRC1,true,false,2); + appendOPR_SSRC_SPECIAL_SCC(253,true,false,1,true); + break; + case 13: case 15: case 17: case 19: case 21: // S_AND_B64,S_OR_B64,S_XOR_B64,S_ANDN2_B64,S_ORN2_B64, + case 23: case 25: case 27: // S_NAND_B64,S_NOR_B64,S_XNOR_B64, + appendOPR_SDST(layout.SDST,false,true,2); + appendOPR_SSRC(layout.SSRC0,true,false,2); + appendOPR_SSRC(layout.SSRC1,true,false,2); + appendOPR_SSRC_SPECIAL_SCC(253,false,true,1,true); + break; + case 29: case 31: case 33: case 39: case 40: // S_LSHL_B64,S_LSHR_B64,S_ASHR_I64,S_BFE_U64,S_BFE_I64, + appendOPR_SDST(layout.SDST,false,true,2); + appendOPR_SSRC(layout.SSRC0,true,false,2); + appendOPR_SSRC(layout.SSRC1,true,false); + appendOPR_SSRC_SPECIAL_SCC(253,false,true,1,true); + break; + case 34: case 36: case 44: case 45: case 50: // S_BFM_B32,S_MUL_I32,S_MUL_HI_U32,S_MUL_HI_I32,S_PACK_LL_B32_B16, + case 51: case 52: // S_PACK_LH_B32_B16,S_PACK_HH_B32_B16, + appendOPR_SDST(layout.SDST,false,true); + appendOPR_SSRC(layout.SSRC0,true,false); + appendOPR_SSRC(layout.SSRC1,true,false); + break; + case 35: // S_BFM_B64, + appendOPR_SDST(layout.SDST,false,true,2); + appendOPR_SSRC(layout.SSRC0,true,false); + appendOPR_SSRC(layout.SSRC1,true,false); + break; + case 41: // S_CBRANCH_G_FORK, + appendOPR_SSRC_NOLIT(layout.SSRC0,true,false,2); + appendOPR_SSRC_NOLIT(layout.SSRC1,true,false,2); + appendOPR_PC(0,false,true,1,true); + break; + case 43: // S_RFE_RESTORE_B64, + appendOPR_SSRC(layout.SSRC0,true,false,2); + appendOPR_SSRC(layout.SSRC1,true,false); + appendOPR_PC(0,false,true,1,true); + break; + } + } + + void InstructionDecoder_amdgpu_gfx90a::finalizeENC_SOPCOperands() + { + layout_ENC_SOPC & layout = insn_layout.ENC_SOPC; + switch (layout.OP) { + case 0: case 1: case 2: case 3: case 4: // S_CMP_EQ_I32,S_CMP_LG_I32,S_CMP_GT_I32,S_CMP_GE_I32,S_CMP_LT_I32, + case 5: case 6: case 7: case 8: case 9: // S_CMP_LE_I32,S_CMP_EQ_U32,S_CMP_LG_U32,S_CMP_GT_U32,S_CMP_GE_U32, + case 10: case 11: case 12: case 13: // S_CMP_LT_U32,S_CMP_LE_U32,S_BITCMP0_B32,S_BITCMP1_B32, + appendOPR_SSRC(layout.SSRC0,true,false); + appendOPR_SSRC(layout.SSRC1,true,false); + appendOPR_SSRC_SPECIAL_SCC(253,false,true,1,true); + break; + case 14: case 15: // S_BITCMP0_B64,S_BITCMP1_B64, + appendOPR_SSRC(layout.SSRC0,true,false,2); + appendOPR_SSRC(layout.SSRC1,true,false); + appendOPR_SSRC_SPECIAL_SCC(253,false,true,1,true); + break; + case 16: // S_SETVSKIP, + appendOPR_SSRC(layout.SSRC0,true,false); + appendOPR_SSRC(layout.SSRC1,true,false); + break; + case 17: // S_SET_GPR_IDX_ON, + appendOPR_SSRC(layout.SSRC0,true,false); + appendOPR_SIMM4(layout.SSRC1,true,false); + appendOPR_SDST_M0(124,false,true,1,true); + appendOPR_SDST_M0(124,true,false,1,true); + break; + case 18: case 19: // S_CMP_EQ_U64,S_CMP_LG_U64, + appendOPR_SSRC(layout.SSRC0,true,false,2); + appendOPR_SSRC(layout.SSRC1,true,false,2); + appendOPR_SSRC_SPECIAL_SCC(253,false,true,1,true); + break; + } + } + + void InstructionDecoder_amdgpu_gfx90a::finalizeENC_SOPKOperands() + { + layout_ENC_SOPK & layout = insn_layout.ENC_SOPK; + switch (layout.OP) { + case 0: case 17: // S_MOVK_I32,S_GETREG_B32, + appendOPR_SDST(layout.SDST,false,true); + appendOPR_SIMM16(layout.SIMM16,true,false); + break; + case 1: // S_CMOVK_I32, + appendOPR_SDST(layout.SDST,true,true); + appendOPR_SIMM16(layout.SIMM16,true,false); + appendOPR_SSRC_SPECIAL_SCC(253,true,false,1,true); + break; + case 2: case 3: case 4: case 5: case 6: // S_CMPK_EQ_I32,S_CMPK_LG_I32,S_CMPK_GT_I32,S_CMPK_GE_I32,S_CMPK_LT_I32, + case 7: case 8: case 9: case 10: case 11: // S_CMPK_LE_I32,S_CMPK_EQ_U32,S_CMPK_LG_U32,S_CMPK_GT_U32,S_CMPK_GE_U32, + case 12: case 13: // S_CMPK_LT_U32,S_CMPK_LE_U32, + appendOPR_SDST(layout.SDST,true,false); + appendOPR_SIMM16(layout.SIMM16,true,false); + appendOPR_SSRC_SPECIAL_SCC(253,false,true,1,true); + break; + case 14: // S_ADDK_I32, + appendOPR_SDST(layout.SDST,true,true); + appendOPR_SIMM16(layout.SIMM16,true,false); + appendOPR_SSRC_SPECIAL_SCC(253,false,true,1,true); + break; + case 15: // S_MULK_I32, + appendOPR_SDST(layout.SDST,true,true); + appendOPR_SIMM16(layout.SIMM16,true,false); + break; + case 16: // S_CBRANCH_I_FORK, + appendOPR_SDST(layout.SDST,true,false,2); + insn_in_progress->appendOperand(decodeOPR_LABEL(layout.SIMM16),true,false); + break; + case 18: // S_SETREG_B32, + appendOPR_SIMM16(layout.SIMM16,false,true); + appendOPR_SDST(layout.SDST,true,false); + break; + case 21: // S_CALL_B64, + appendOPR_SDST(layout.SDST,false,true,2); + insn_in_progress->appendOperand(decodeOPR_LABEL(layout.SIMM16),true,false); + appendOPR_PC(0,false,true,1,true); + appendOPR_PC(0,true,false,1,true); + break; + } + } + + void InstructionDecoder_amdgpu_gfx90a::finalizeSOPK_INST_LITERAL_Operands() + { + layout_SOPK_INST_LITERAL_ & layout = insn_layout.SOPK_INST_LITERAL_; + switch (layout.OP) { + case 20: // S_SETREG_IMM32_B32, + appendOPR_SIMM16(layout.SIMM16,false,true); + appendOPR_SIMM32(layout.SIMM32,true,false); + break; + } + } + + void InstructionDecoder_amdgpu_gfx90a::finalizeENC_SOPPOperands() + { + layout_ENC_SOPP & layout = insn_layout.ENC_SOPP; + switch (layout.OP) { + case 0: case 11: case 13: case 14: case 15: case 18: // S_NOP,S_SETKILL,S_SETHALT,S_SLEEP,S_SETPRIO,S_TRAP, + case 20: case 21: // S_INCPERFLEVEL,S_DECPERFLEVEL, + appendOPR_SIMM16(layout.SIMM16,true,false); + break; + case 1: case 3: case 10: case 19: case 27: // S_ENDPGM,S_WAKEUP,S_BARRIER,S_ICACHE_INV,S_ENDPGM_SAVED, + case 28: case 30: // S_SET_GPR_IDX_OFF,S_ENDPGM_ORDERED_PS_DONE, + break; + case 2: // S_BRANCH, + setBranch(); + makeBranchTarget(isCall,isConditional,layout.SIMM16); + break; + case 4: case 5: // S_CBRANCH_SCC0,S_CBRANCH_SCC1, + setBranch(); + setConditionalBranch(); + makeBranchTarget(isCall,isConditional,layout.SIMM16); + appendOPR_SSRC_SPECIAL_SCC(253,true,false,1,true); + break; + case 6: case 7: // S_CBRANCH_VCCZ,S_CBRANCH_VCCNZ, + setBranch(); + setConditionalBranch(); + makeBranchTarget(isCall,isConditional,layout.SIMM16); + appendOPR_VCC(0,true,false,1,true); + break; + case 8: case 9: // S_CBRANCH_EXECZ,S_CBRANCH_EXECNZ, + setBranch(); + setConditionalBranch(); + makeBranchTarget(isCall,isConditional,layout.SIMM16); + appendOPR_SDST_EXEC(126,true,false,1,true); + break; + case 12: // S_WAITCNT, + { + uint32_t vmcnt = ((0x3& (layout.SIMM16 >>14))<<4) | (layout.SIMM16 & 0xf); + uint32_t expcnt = ((layout.SIMM16>>4) & 0x7); + uint32_t lgkmcnt = ((layout.SIMM16>>8) & 0xf); + if (vmcnt != 0x3f) + { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::vmcnt,0,32),false,true); + insn_in_progress->appendOperand(Immediate::makeImmediate(Result(u32,vmcnt)),false,false); + } + if (expcnt != 0x7) + { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::expcnt,0,32),false,true); + insn_in_progress->appendOperand(Immediate::makeImmediate(Result(u32,expcnt)),false,false); + } + if (lgkmcnt != 0xf) + { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx90a::lgkmcnt,0,32),false,true); + insn_in_progress->appendOperand(Immediate::makeImmediate(Result(u32,lgkmcnt)),false,false); + } + } + break; + case 16: case 17: // S_SENDMSG,S_SENDMSGHALT, + appendOPR_SIMM16(layout.SIMM16,true,false); + appendOPR_SDST_M0(124,true,false,1,true); + break; + case 22: // S_TTRACEDATA, + appendOPR_SDST_M0(124,true,false,1,true); + break; + case 23: case 24: case 25: // S_CBRANCH_CDBGSYS,S_CBRANCH_CDBGUSER,S_CBRANCH_CDBGSYS_OR_USER, + case 26: // S_CBRANCH_CDBGSYS_AND_USER, + insn_in_progress->appendOperand(decodeOPR_LABEL(layout.SIMM16),true,false); + break; + case 29: // S_SET_GPR_IDX_MODE, + appendOPR_SIMM16(layout.SIMM16,true,false); + appendOPR_SDST_M0(124,false,true,1,true); + appendOPR_SDST_M0(124,true,false,1,true); + break; + } + } + + void InstructionDecoder_amdgpu_gfx90a::finalizeENC_VOP1Operands() + { + layout_ENC_VOP1 & layout = insn_layout.ENC_VOP1; + switch (layout.OP) { + case 0: case 53: // V_NOP,V_CLREXCP, + break; + case 1: case 5: case 6: case 7: case 8: // V_MOV_B32,V_CVT_F32_I32,V_CVT_F32_U32,V_CVT_U32_F32,V_CVT_I32_F32, + case 10: case 11: case 12: case 13: // V_CVT_F16_F32,V_CVT_F32_F16,V_CVT_RPI_I32_F32,V_CVT_FLR_I32_F32, + case 14: case 17: case 18: case 19: // V_CVT_OFF_F32_I4,V_CVT_F32_UBYTE0,V_CVT_F32_UBYTE1,V_CVT_F32_UBYTE2, + case 20: case 27: case 28: case 29: case 30: // V_CVT_F32_UBYTE3,V_FRACT_F32,V_TRUNC_F32,V_CEIL_F32,V_RNDNE_F32, + case 31: case 32: case 33: case 34: case 35: // V_FLOOR_F32,V_EXP_F32,V_LOG_F32,V_RCP_F32,V_RCP_IFLAG_F32, + case 36: case 39: case 41: case 42: case 43: // V_RSQ_F32,V_SQRT_F32,V_SIN_F32,V_COS_F32,V_NOT_B32, + case 44: case 45: case 46: case 47: case 51: // V_BFREV_B32,V_FFBH_U32,V_FFBL_B32,V_FFBH_I32,V_FREXP_EXP_I32_F32, + case 52: case 55: case 57: case 58: // V_FREXP_MANT_F32,V_SCREEN_PARTITION_4SE_B32,V_CVT_F16_U16,V_CVT_F16_I16, + case 59: case 60: case 61: case 62: case 63: // V_CVT_U16_F16,V_CVT_I16_F16,V_RCP_F16,V_SQRT_F16,V_RSQ_F16, + case 64: case 65: case 66: case 67: // V_LOG_F16,V_EXP_F16,V_FREXP_MANT_F16,V_FREXP_EXP_I16_F16, + case 68: case 69: case 70: case 71: case 72: // V_FLOOR_F16,V_CEIL_F16,V_TRUNC_F16,V_RNDNE_F16,V_FRACT_F16, + case 73: case 74: case 75: case 76: // V_SIN_F16,V_COS_F16,V_EXP_LEGACY_F32,V_LOG_LEGACY_F32, + case 77: case 78: case 79: // V_CVT_NORM_I16_F16,V_CVT_NORM_U16_F16,V_SAT_PK_U8_I16, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_SRC(layout.SRC0,true,false); + break; + case 2: // V_READFIRSTLANE_B32, + appendOPR_SREG_NOVCC(layout.VDST,false,true); + appendOPR_VGPR_OR_LDS(layout.SRC0,true,false); + break; + case 3: case 15: case 21: case 48: // V_CVT_I32_F64,V_CVT_F32_F64,V_CVT_U32_F64,V_FREXP_EXP_I32_F64, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_SRC(layout.SRC0,true,false,2); + break; + case 4: case 16: case 22: // V_CVT_F64_I32,V_CVT_F64_F32,V_CVT_F64_U32, + appendOPR_VGPR(layout.VDST,false,true,2); + appendOPR_SRC(layout.SRC0,true,false); + break; + case 23: case 24: case 25: case 26: case 37: // V_TRUNC_F64,V_CEIL_F64,V_RNDNE_F64,V_FLOOR_F64,V_RCP_F64, + case 38: case 40: case 49: case 50: // V_RSQ_F64,V_SQRT_F64,V_FREXP_MANT_F64,V_FRACT_F64, + appendOPR_VGPR(layout.VDST,false,true,2); + appendOPR_SRC(layout.SRC0,true,false,2); + break; + case 81: // V_SWAP_B32, + appendOPR_VGPR(layout.VDST,true,true); + appendOPR_SRC_VGPR(layout.SRC0,true,true); + break; + case 82: // V_ACCVGPR_MOV_B32, + appendOPR_ACCVGPR(layout.VDST,false,true); + appendOPR_SRC_ACCVGPR(layout.SRC0,true,false); + break; + } + } + + void InstructionDecoder_amdgpu_gfx90a::finalizeENC_VOP3Operands() + { + layout_ENC_VOP3 & layout = insn_layout.ENC_VOP3; + switch (layout.OP) { + case 320: case 373: // V_NOP,V_CLREXCP, + break; + case 321: case 325: case 326: case 327: // V_MOV_B32,V_CVT_F32_I32,V_CVT_F32_U32,V_CVT_U32_F32, + case 328: case 330: case 331: case 332: // V_CVT_I32_F32,V_CVT_F16_F32,V_CVT_F32_F16,V_CVT_RPI_I32_F32, + case 333: case 334: case 337: case 338: // V_CVT_FLR_I32_F32,V_CVT_OFF_F32_I4,V_CVT_F32_UBYTE0,V_CVT_F32_UBYTE1, + case 339: case 340: case 347: case 348: // V_CVT_F32_UBYTE2,V_CVT_F32_UBYTE3,V_FRACT_F32,V_TRUNC_F32, + case 349: case 350: case 351: case 352: case 353: // V_CEIL_F32,V_RNDNE_F32,V_FLOOR_F32,V_EXP_F32,V_LOG_F32, + case 354: case 355: case 356: case 359: case 361: // V_RCP_F32,V_RCP_IFLAG_F32,V_RSQ_F32,V_SQRT_F32,V_SIN_F32, + case 362: case 363: case 364: case 365: case 366: // V_COS_F32,V_NOT_B32,V_BFREV_B32,V_FFBH_U32,V_FFBL_B32, + case 367: case 371: case 372: // V_FFBH_I32,V_FREXP_EXP_I32_F32,V_FREXP_MANT_F32, + case 375: case 377: case 378: case 379: // V_SCREEN_PARTITION_4SE_B32,V_CVT_F16_U16,V_CVT_F16_I16,V_CVT_U16_F16, + case 380: case 381: case 382: case 383: case 384: // V_CVT_I16_F16,V_RCP_F16,V_SQRT_F16,V_RSQ_F16,V_LOG_F16, + case 385: case 386: case 387: case 388: // V_EXP_F16,V_FREXP_MANT_F16,V_FREXP_EXP_I16_F16,V_FLOOR_F16, + case 389: case 390: case 391: case 392: case 393: // V_CEIL_F16,V_TRUNC_F16,V_RNDNE_F16,V_FRACT_F16,V_SIN_F16, + case 394: case 395: case 396: case 397: // V_COS_F16,V_EXP_LEGACY_F32,V_LOG_LEGACY_F32,V_CVT_NORM_I16_F16, + case 398: case 399: // V_CVT_NORM_U16_F16,V_SAT_PK_U8_I16, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_SRC_NOLIT(layout.SRC0,true,false); + break; + case 322: // V_READFIRSTLANE_B32, + appendOPR_SREG_NOVCC(layout.VDST,false,true); + appendOPR_VGPR_OR_LDS(layout.SRC0,true,false); + break; + case 323: case 335: case 341: case 368: // V_CVT_I32_F64,V_CVT_F32_F64,V_CVT_U32_F64,V_FREXP_EXP_I32_F64, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_SRC_NOLIT(layout.SRC0,true,false,2); + break; + case 324: case 336: case 342: // V_CVT_F64_I32,V_CVT_F64_F32,V_CVT_F64_U32, + appendOPR_VGPR(layout.VDST,false,true,2); + appendOPR_SRC_NOLIT(layout.SRC0,true,false); + break; + case 343: case 344: case 345: case 346: case 357: // V_TRUNC_F64,V_CEIL_F64,V_RNDNE_F64,V_FLOOR_F64,V_RCP_F64, + case 358: case 360: case 369: case 370: // V_RSQ_F64,V_SQRT_F64,V_FREXP_MANT_F64,V_FRACT_F64, + appendOPR_VGPR(layout.VDST,false,true,2); + appendOPR_SRC_NOLIT(layout.SRC0,true,false,2); + break; + case 401: // V_SWAP_B32, + appendOPR_VGPR(layout.VDST,true,true); + appendOPR_SRC_VGPR(layout.SRC0,true,true); + break; + case 402: // V_ACCVGPR_MOV_B32, + appendOPR_ACCVGPR(layout.VDST,false,true); + appendOPR_SRC_ACCVGPR(layout.SRC0,true,false); + break; + case 256: // V_CNDMASK_B32, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_SRC_NOLIT(layout.SRC0,true,false); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false); + appendOPR_SREG(layout.SRC2,true,false,2); + break; + case 257: case 258: case 259: case 261: case 262: // V_ADD_F32,V_SUB_F32,V_SUBREV_F32,V_MUL_F32,V_MUL_I32_I24, + case 263: case 264: case 265: case 266: // V_MUL_HI_I32_I24,V_MUL_U32_U24,V_MUL_HI_U32_U24,V_MIN_F32, + case 267: case 268: case 269: case 270: case 271: // V_MAX_F32,V_MIN_I32,V_MAX_I32,V_MIN_U32,V_MAX_U32, + case 275: case 276: case 277: case 287: case 288: // V_AND_B32,V_OR_B32,V_XOR_B32,V_ADD_F16,V_SUB_F16, + case 290: case 294: case 295: case 297: case 301: // V_MUL_F16,V_ADD_U16,V_SUB_U16,V_MUL_LO_U16,V_MAX_F16, + case 302: case 303: case 304: case 305: case 306: // V_MIN_F16,V_MAX_U16,V_MAX_I16,V_MIN_U16,V_MIN_I16, + case 307: case 308: case 309: case 317: case 645: // V_LDEXP_F16,V_ADD_U32,V_SUB_U32,V_XNOR_B32,V_MUL_LO_U32, + case 646: case 647: case 648: case 651: // V_MUL_HI_U32,V_MUL_HI_I32,V_LDEXP_F32,V_BCNT_U32_B32, + case 652: case 653: case 659: case 660: // V_MBCNT_LO_U32_B32,V_MBCNT_HI_U32_B32,V_BFM_B32,V_CVT_PKNORM_I16_F32, + case 661: case 662: case 663: // V_CVT_PKNORM_U16_F32,V_CVT_PKRTZ_F16_F32,V_CVT_PK_U16_U32, + case 664: case 665: case 666: case 668: // V_CVT_PK_I16_I32,V_CVT_PKNORM_I16_F16,V_CVT_PKNORM_U16_F16,V_ADD_I32, + case 669: case 670: case 671: case 672: case 673: // V_SUB_I32,V_ADD_I16,V_SUB_I16,V_PACK_B32_F16,V_MUL_LEGACY_F32, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_SRC_NOLIT(layout.SRC0,true,false); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false); + break; + case 260: // V_FMAC_F64, + appendOPR_VGPR(layout.VDST,true,true,2); + appendOPR_SRC_NOLIT(layout.SRC0,true,false,2); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false,2); + break; + case 272: case 273: case 274: case 289: // V_LSHRREV_B32,V_ASHRREV_I32,V_LSHLREV_B32,V_SUBREV_F16, + case 296: case 298: case 299: case 300: // V_SUBREV_U16,V_LSHLREV_B16,V_LSHRREV_B16,V_ASHRREV_I16, + case 310: // V_SUBREV_U32, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_SRC_SIMPLE(layout.SRC0,true,false); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false); + break; + case 278: case 291: case 311: case 312: // V_MAC_F32,V_MAC_F16,V_DOT2C_F32_F16,V_DOT2C_I32_I16, + case 313: case 314: case 315: case 316: // V_DOT4C_I32_I8,V_DOT8C_I32_I4,V_FMAC_F32,V_PK_FMAC_F16, + case 496: // V_CVT_PKACCUM_U8_F32, + appendOPR_VGPR(layout.VDST,true,true); + appendOPR_SRC_NOLIT(layout.SRC0,true,false); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false); + break; + case 448: case 449: case 450: case 451: // V_MAD_LEGACY_F32,V_MAD_F32,V_MAD_I32_I24,V_MAD_U32_U24, + case 452: case 453: case 454: case 455: case 456: // V_CUBEID_F32,V_CUBESC_F32,V_CUBETC_F32,V_CUBEMA_F32,V_BFE_U32, + case 457: case 458: case 459: case 461: case 462: // V_BFE_I32,V_BFI_B32,V_FMA_F32,V_LERP_U8,V_ALIGNBIT_B32, + case 463: case 464: case 465: case 466: case 467: // V_ALIGNBYTE_B32,V_MIN3_F32,V_MIN3_I32,V_MIN3_U32,V_MAX3_F32, + case 468: case 469: case 470: case 471: case 472: // V_MAX3_I32,V_MAX3_U32,V_MED3_F32,V_MED3_I32,V_MED3_U32, + case 473: case 474: case 475: case 476: case 477: // V_SAD_U8,V_SAD_HI_U8,V_SAD_U16,V_SAD_U32,V_CVT_PK_U8_F32, + case 478: case 484: case 490: case 491: // V_DIV_FIXUP_F32,V_MSAD_U8,V_MAD_LEGACY_F16,V_MAD_LEGACY_U16, + case 492: case 493: case 494: case 495: // V_MAD_LEGACY_I16,V_PERM_B32,V_FMA_LEGACY_F16,V_DIV_FIXUP_LEGACY_F16, + case 497: case 498: case 499: case 500: case 501: // V_MAD_U32_U16,V_MAD_I32_I16,V_XAD_U32,V_MIN3_F16,V_MIN3_I16, + case 502: case 503: case 504: case 505: case 506: // V_MIN3_U16,V_MAX3_F16,V_MAX3_I16,V_MAX3_U16,V_MED3_F16, + case 507: case 508: case 509: case 510: case 511: // V_MED3_I16,V_MED3_U16,V_LSHL_ADD_U32,V_ADD_LSHL_U32,V_ADD3_U32, + case 512: case 513: case 514: case 515: case 516: // V_LSHL_OR_B32,V_AND_OR_B32,V_OR3_B32,V_MAD_F16,V_MAD_U16, + case 517: case 518: case 519: // V_MAD_I16,V_FMA_F16,V_DIV_FIXUP_F16, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_SRC_NOLIT(layout.SRC0,true,false); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false); + appendOPR_SRC_SIMPLE(layout.SRC2,true,false); + break; + case 460: case 479: // V_FMA_F64,V_DIV_FIXUP_F64, + appendOPR_VGPR(layout.VDST,false,true,2); + appendOPR_SRC_NOLIT(layout.SRC0,true,false,2); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false,2); + appendOPR_SRC_SIMPLE(layout.SRC2,true,false,2); + break; + case 482: // V_DIV_FMAS_F32, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_SRC_NOLIT(layout.SRC0,true,false); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false); + appendOPR_SRC_SIMPLE(layout.SRC2,true,false); + appendOPR_VCC(0,true,false,1,true); + break; + case 483: // V_DIV_FMAS_F64, + appendOPR_VGPR(layout.VDST,false,true,2); + appendOPR_SRC_NOLIT(layout.SRC0,true,false,2); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false,2); + appendOPR_SRC_SIMPLE(layout.SRC2,true,false,2); + appendOPR_VCC(0,true,false,1,true); + break; + case 485: case 486: // V_QSAD_PK_U16_U8,V_MQSAD_PK_U16_U8, + appendOPR_VGPR(layout.VDST,false,true,2); + appendOPR_SRC_NOLIT(layout.SRC0,true,false,2); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false); + appendOPR_SRC_SIMPLE(layout.SRC2,true,false,2); + break; + case 487: // V_MQSAD_U32_U8, + appendOPR_VGPR(layout.VDST,false,true,4); + appendOPR_SRC_NOLIT(layout.SRC0,true,false,2); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false); + appendOPR_SRC_VGPR(layout.SRC2,true,false,4); + break; + case 640: case 641: case 642: case 643: // V_ADD_F64,V_MUL_F64,V_MIN_F64,V_MAX_F64, + appendOPR_VGPR(layout.VDST,false,true,2); + appendOPR_SRC_NOLIT(layout.SRC0,true,false,2); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false,2); + break; + case 644: case 658: // V_LDEXP_F64,V_TRIG_PREOP_F64, + appendOPR_VGPR(layout.VDST,false,true,2); + appendOPR_SRC_NOLIT(layout.SRC0,true,false,2); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false); + break; + case 649: // V_READLANE_B32, + appendOPR_SREG_NOVCC(layout.VDST,false,true); + appendOPR_VGPR_OR_LDS(layout.SRC0,true,false); + appendOPR_SSRC_LANESEL(layout.SRC1,true,false); + break; + case 650: // V_WRITELANE_B32, + appendOPR_VGPR(layout.VDST,true,true); + appendOPR_SSRC_NOLIT(layout.SRC0,true,false); + appendOPR_SSRC_LANESEL(layout.SRC1,true,false); + break; + case 655: case 656: case 657: // V_LSHLREV_B64,V_LSHRREV_B64,V_ASHRREV_I64, + appendOPR_VGPR(layout.VDST,false,true,2); + appendOPR_SRC_SIMPLE(layout.SRC0,true,false); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false,2); + break; + case 16: case 20: case 32: case 33: // V_CMP_CLASS_F32,V_CMP_CLASS_F16,V_CMP_F_F16,V_CMP_LT_F16, + case 34: case 35: case 36: case 37: case 38: // V_CMP_EQ_F16,V_CMP_LE_F16,V_CMP_GT_F16,V_CMP_LG_F16,V_CMP_GE_F16, + case 39: case 40: case 41: case 42: case 43: // V_CMP_O_F16,V_CMP_U_F16,V_CMP_NGE_F16,V_CMP_NLG_F16,V_CMP_NGT_F16, + case 44: case 45: case 46: case 47: case 64: // V_CMP_NLE_F16,V_CMP_NEQ_F16,V_CMP_NLT_F16,V_CMP_TRU_F16,V_CMP_F_F32, + case 65: case 66: case 67: case 68: case 69: // V_CMP_LT_F32,V_CMP_EQ_F32,V_CMP_LE_F32,V_CMP_GT_F32,V_CMP_LG_F32, + case 70: case 71: case 72: case 73: case 74: // V_CMP_GE_F32,V_CMP_O_F32,V_CMP_U_F32,V_CMP_NGE_F32,V_CMP_NLG_F32, + case 75: case 76: case 77: case 78: // V_CMP_NGT_F32,V_CMP_NLE_F32,V_CMP_NEQ_F32,V_CMP_NLT_F32, + case 79: case 160: case 161: case 162: // V_CMP_TRU_F32,V_CMP_F_I16,V_CMP_LT_I16,V_CMP_EQ_I16, + case 163: case 164: case 165: case 166: // V_CMP_LE_I16,V_CMP_GT_I16,V_CMP_NE_I16,V_CMP_GE_I16, + case 167: case 168: case 169: case 170: case 171: // V_CMP_T_I16,V_CMP_F_U16,V_CMP_LT_U16,V_CMP_EQ_U16,V_CMP_LE_U16, + case 172: case 173: case 174: case 175: case 192: // V_CMP_GT_U16,V_CMP_NE_U16,V_CMP_GE_U16,V_CMP_T_U16,V_CMP_F_I32, + case 193: case 194: case 195: case 196: // V_CMP_LT_I32,V_CMP_EQ_I32,V_CMP_LE_I32,V_CMP_GT_I32, + case 197: case 198: case 199: case 200: case 201: // V_CMP_NE_I32,V_CMP_GE_I32,V_CMP_T_I32,V_CMP_F_U32,V_CMP_LT_U32, + case 202: case 203: case 204: case 205: // V_CMP_EQ_U32,V_CMP_LE_U32,V_CMP_GT_U32,V_CMP_NE_U32, + case 206: case 207: // V_CMP_GE_U32,V_CMP_T_U32, + appendOPR_SREG(layout.VDST,false,true,2); + appendOPR_SRC_NOLIT(layout.SRC0,true,false); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false); + break; + case 17: case 21: case 48: case 49: // V_CMPX_CLASS_F32,V_CMPX_CLASS_F16,V_CMPX_F_F16,V_CMPX_LT_F16, + case 50: case 51: case 52: case 53: // V_CMPX_EQ_F16,V_CMPX_LE_F16,V_CMPX_GT_F16,V_CMPX_LG_F16, + case 54: case 55: case 56: case 57: // V_CMPX_GE_F16,V_CMPX_O_F16,V_CMPX_U_F16,V_CMPX_NGE_F16, + case 58: case 59: case 60: case 61: // V_CMPX_NLG_F16,V_CMPX_NGT_F16,V_CMPX_NLE_F16,V_CMPX_NEQ_F16, + case 62: case 63: case 80: case 81: // V_CMPX_NLT_F16,V_CMPX_TRU_F16,V_CMPX_F_F32,V_CMPX_LT_F32, + case 82: case 83: case 84: case 85: // V_CMPX_EQ_F32,V_CMPX_LE_F32,V_CMPX_GT_F32,V_CMPX_LG_F32, + case 86: case 87: case 88: case 89: // V_CMPX_GE_F32,V_CMPX_O_F32,V_CMPX_U_F32,V_CMPX_NGE_F32, + case 90: case 91: case 92: case 93: // V_CMPX_NLG_F32,V_CMPX_NGT_F32,V_CMPX_NLE_F32,V_CMPX_NEQ_F32, + case 94: case 95: case 176: case 177: // V_CMPX_NLT_F32,V_CMPX_TRU_F32,V_CMPX_F_I16,V_CMPX_LT_I16, + case 178: case 179: case 180: case 181: // V_CMPX_EQ_I16,V_CMPX_LE_I16,V_CMPX_GT_I16,V_CMPX_NE_I16, + case 182: case 183: case 184: case 185: // V_CMPX_GE_I16,V_CMPX_T_I16,V_CMPX_F_U16,V_CMPX_LT_U16, + case 186: case 187: case 188: case 189: // V_CMPX_EQ_U16,V_CMPX_LE_U16,V_CMPX_GT_U16,V_CMPX_NE_U16, + case 190: case 191: case 208: case 209: // V_CMPX_GE_U16,V_CMPX_T_U16,V_CMPX_F_I32,V_CMPX_LT_I32, + case 210: case 211: case 212: case 213: // V_CMPX_EQ_I32,V_CMPX_LE_I32,V_CMPX_GT_I32,V_CMPX_NE_I32, + case 214: case 215: case 216: case 217: // V_CMPX_GE_I32,V_CMPX_T_I32,V_CMPX_F_U32,V_CMPX_LT_U32, + case 218: case 219: case 220: case 221: // V_CMPX_EQ_U32,V_CMPX_LE_U32,V_CMPX_GT_U32,V_CMPX_NE_U32, + case 222: case 223: // V_CMPX_GE_U32,V_CMPX_T_U32, + appendOPR_SDST(layout.VDST,false,true,2); + appendOPR_SRC_NOLIT(layout.SRC0,true,false); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false); + appendOPR_SDST_EXEC(126,false,true,1,true); + break; + case 18: // V_CMP_CLASS_F64, + appendOPR_SREG(layout.VDST,false,true,2); + appendOPR_SRC_NOLIT(layout.SRC0,true,false,2); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false); + break; + case 19: // V_CMPX_CLASS_F64, + appendOPR_SDST(layout.VDST,false,true,2); + appendOPR_SRC_NOLIT(layout.SRC0,true,false,2); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false); + appendOPR_SDST_EXEC(126,false,true,1,true); + break; + case 96: case 97: case 98: case 99: case 100: // V_CMP_F_F64,V_CMP_LT_F64,V_CMP_EQ_F64,V_CMP_LE_F64,V_CMP_GT_F64, + case 101: case 102: case 103: case 104: // V_CMP_LG_F64,V_CMP_GE_F64,V_CMP_O_F64,V_CMP_U_F64, + case 105: case 106: case 107: case 108: // V_CMP_NGE_F64,V_CMP_NLG_F64,V_CMP_NGT_F64,V_CMP_NLE_F64, + case 109: case 110: case 111: case 224: // V_CMP_NEQ_F64,V_CMP_NLT_F64,V_CMP_TRU_F64,V_CMP_F_I64, + case 225: case 226: case 227: case 228: // V_CMP_LT_I64,V_CMP_EQ_I64,V_CMP_LE_I64,V_CMP_GT_I64, + case 229: case 230: case 231: case 232: case 233: // V_CMP_NE_I64,V_CMP_GE_I64,V_CMP_T_I64,V_CMP_F_U64,V_CMP_LT_U64, + case 234: case 235: case 236: case 237: // V_CMP_EQ_U64,V_CMP_LE_U64,V_CMP_GT_U64,V_CMP_NE_U64, + case 238: case 239: // V_CMP_GE_U64,V_CMP_T_U64, + appendOPR_SREG(layout.VDST,false,true,2); + appendOPR_SRC_NOLIT(layout.SRC0,true,false,2); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false,2); + break; + case 112: case 113: case 114: case 115: // V_CMPX_F_F64,V_CMPX_LT_F64,V_CMPX_EQ_F64,V_CMPX_LE_F64, + case 116: case 117: case 118: case 119: // V_CMPX_GT_F64,V_CMPX_LG_F64,V_CMPX_GE_F64,V_CMPX_O_F64, + case 120: case 121: case 122: case 123: // V_CMPX_U_F64,V_CMPX_NGE_F64,V_CMPX_NLG_F64,V_CMPX_NGT_F64, + case 124: case 125: case 126: case 127: // V_CMPX_NLE_F64,V_CMPX_NEQ_F64,V_CMPX_NLT_F64,V_CMPX_TRU_F64, + case 240: case 241: case 242: case 243: // V_CMPX_F_I64,V_CMPX_LT_I64,V_CMPX_EQ_I64,V_CMPX_LE_I64, + case 244: case 245: case 246: case 247: // V_CMPX_GT_I64,V_CMPX_NE_I64,V_CMPX_GE_I64,V_CMPX_T_I64, + case 248: case 249: case 250: case 251: // V_CMPX_F_U64,V_CMPX_LT_U64,V_CMPX_EQ_U64,V_CMPX_LE_U64, + case 252: case 253: case 254: case 255: // V_CMPX_GT_U64,V_CMPX_NE_U64,V_CMPX_GE_U64,V_CMPX_T_U64, + appendOPR_SDST(layout.VDST,false,true,2); + appendOPR_SRC_NOLIT(layout.SRC0,true,false,2); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false,2); + appendOPR_SDST_EXEC(126,false,true,1,true); + break; + } + } + + void InstructionDecoder_amdgpu_gfx90a::finalizeENC_VOP2Operands() + { + layout_ENC_VOP2 & layout = insn_layout.ENC_VOP2; + switch (layout.OP) { + case 0: // V_CNDMASK_B32, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_SRC(layout.SRC0,true,false); + appendOPR_VGPR(layout.VSRC1,true,false); + appendOPR_VCC(0,true,false,2); + break; + case 1: case 2: case 3: case 5: case 6: // V_ADD_F32,V_SUB_F32,V_SUBREV_F32,V_MUL_F32,V_MUL_I32_I24, + case 7: case 8: case 9: case 10: case 11: // V_MUL_HI_I32_I24,V_MUL_U32_U24,V_MUL_HI_U32_U24,V_MIN_F32,V_MAX_F32, + case 12: case 13: case 14: case 15: case 19: // V_MIN_I32,V_MAX_I32,V_MIN_U32,V_MAX_U32,V_AND_B32, + case 20: case 21: case 31: case 32: case 34: // V_OR_B32,V_XOR_B32,V_ADD_F16,V_SUB_F16,V_MUL_F16, + case 38: case 39: case 41: case 45: case 46: // V_ADD_U16,V_SUB_U16,V_MUL_LO_U16,V_MAX_F16,V_MIN_F16, + case 47: case 48: case 49: case 50: case 51: // V_MAX_U16,V_MAX_I16,V_MIN_U16,V_MIN_I16,V_LDEXP_F16, + case 52: case 53: case 61: // V_ADD_U32,V_SUB_U32,V_XNOR_B32, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_SRC(layout.SRC0,true,false); + appendOPR_VGPR(layout.VSRC1,true,false); + break; + case 4: // V_FMAC_F64, + appendOPR_VGPR(layout.VDST,true,true,2); + appendOPR_SRC(layout.SRC0,true,false,2); + appendOPR_VGPR(layout.VSRC1,true,false,2); + break; + case 16: case 17: case 18: case 33: case 40: // V_LSHRREV_B32,V_ASHRREV_I32,V_LSHLREV_B32,V_SUBREV_F16,V_SUBREV_U16, + case 42: case 43: case 44: case 54: // V_LSHLREV_B16,V_LSHRREV_B16,V_ASHRREV_I16,V_SUBREV_U32, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_SRC_NOLDS(layout.SRC0,true,false); + appendOPR_VGPR(layout.VSRC1,true,false); + break; + case 22: case 35: case 55: case 56: case 57: // V_MAC_F32,V_MAC_F16,V_DOT2C_F32_F16,V_DOT2C_I32_I16,V_DOT4C_I32_I8, + case 58: case 59: case 60: // V_DOT8C_I32_I4,V_FMAC_F32,V_PK_FMAC_F16, + appendOPR_VGPR(layout.VDST,true,true); + appendOPR_SRC(layout.SRC0,true,false); + appendOPR_VGPR(layout.VSRC1,true,false); + break; + case 25: case 26: // V_ADD_CO_U32,V_SUB_CO_U32, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_VCC(0,false,true,2); + appendOPR_SRC(layout.SRC0,true,false); + appendOPR_VGPR(layout.VSRC1,true,false); + break; + case 27: // V_SUBREV_CO_U32, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_VCC(0,false,true,2); + appendOPR_SRC_NOLDS(layout.SRC0,true,false); + appendOPR_VGPR(layout.VSRC1,true,false); + break; + case 28: case 29: // V_ADDC_CO_U32,V_SUBB_CO_U32, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_VCC(0,false,true,2); + appendOPR_SRC(layout.SRC0,true,false); + appendOPR_VGPR(layout.VSRC1,true,false); + appendOPR_VCC(0,true,false,2); + break; + case 30: // V_SUBBREV_CO_U32, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_VCC(0,false,true,2); + appendOPR_SRC_NOLDS(layout.SRC0,true,false); + appendOPR_VGPR(layout.VSRC1,true,false); + appendOPR_VCC(0,true,false,2); + break; + } + } + + void InstructionDecoder_amdgpu_gfx90a::finalizeENC_VOP2_LITERALOperands() + { + layout_ENC_VOP2_LITERAL & layout = insn_layout.ENC_VOP2_LITERAL; + switch (layout.OP) { + case 23: case 36: // V_MADMK_F32,V_MADMK_F16, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_SRC(layout.SRC0,true,false); + appendOPR_SIMM32(layout.SIMM32,true,false); + appendOPR_VGPR(layout.VSRC1,true,false); + break; + case 24: case 37: // V_MADAK_F32,V_MADAK_F16, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_SRC(layout.SRC0,true,false); + appendOPR_VGPR(layout.VSRC1,true,false); + appendOPR_SIMM32(layout.SIMM32,true,false); + break; + } + } + + void InstructionDecoder_amdgpu_gfx90a::finalizeENC_VOP3BOperands() + { + layout_ENC_VOP3B & layout = insn_layout.ENC_VOP3B; + switch (layout.OP) { + case 281: case 282: // V_ADD_CO_U32,V_SUB_CO_U32, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_SREG(layout.SDST,false,true,2); + appendOPR_SRC_NOLIT(layout.SRC0,true,false); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false); + break; + case 283: // V_SUBREV_CO_U32, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_SREG(layout.SDST,false,true,2); + appendOPR_SRC_SIMPLE(layout.SRC0,true,false); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false); + break; + case 284: case 285: // V_ADDC_CO_U32,V_SUBB_CO_U32, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_SREG(layout.SDST,false,true,2); + appendOPR_SRC_NOLIT(layout.SRC0,true,false); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false); + appendOPR_SREG(layout.SRC2,true,false,2); + break; + case 286: // V_SUBBREV_CO_U32, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_SREG(layout.SDST,false,true,2); + appendOPR_SRC_SIMPLE(layout.SRC0,true,false); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false); + appendOPR_SREG(layout.SRC2,true,false,2); + break; + case 480: // V_DIV_SCALE_F32, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_VCC(layout.SDST,false,true,2); + appendOPR_SRC_NOLIT(layout.SRC0,true,false); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false); + appendOPR_SRC_SIMPLE(layout.SRC2,true,false); + break; + case 481: // V_DIV_SCALE_F64, + appendOPR_VGPR(layout.VDST,false,true,2); + appendOPR_VCC(layout.SDST,false,true,2); + appendOPR_SRC_NOLIT(layout.SRC0,true,false,2); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false,2); + appendOPR_SRC_SIMPLE(layout.SRC2,true,false,2); + break; + case 488: case 489: // V_MAD_U64_U32,V_MAD_I64_I32, + appendOPR_VGPR(layout.VDST,false,true,2); + appendOPR_SREG(layout.SDST,false,true,2); + appendOPR_SRC_NOLIT(layout.SRC0,true,false); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false); + appendOPR_SRC_SIMPLE(layout.SRC2,true,false,2); + break; + } + } + + void InstructionDecoder_amdgpu_gfx90a::finalizeENC_VOP3POperands() + { + layout_ENC_VOP3P & layout = insn_layout.ENC_VOP3P; + switch (layout.OP) { + case 0: case 9: case 14: case 32: case 33: // V_PK_MAD_I16,V_PK_MAD_U16,V_PK_FMA_F16,V_MAD_MIX_F32,V_MAD_MIXLO_F16, + case 34: case 35: case 38: case 39: // V_MAD_MIXHI_F16,V_DOT2_F32_F16,V_DOT2_I32_I16,V_DOT2_U32_U16, + case 40: case 41: case 42: case 43: // V_DOT4_I32_I8,V_DOT4_U32_U8,V_DOT8_I32_I4,V_DOT8_U32_U4, + case 48: // V_PK_FMA_F32, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_SRC_NOLIT(layout.SRC0,true,false); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false); + appendOPR_SRC_SIMPLE(layout.SRC2,true,false); + break; + case 1: case 2: case 3: case 7: case 8: // V_PK_MUL_LO_U16,V_PK_ADD_I16,V_PK_SUB_I16,V_PK_MAX_I16,V_PK_MIN_I16, + case 10: case 11: case 12: case 13: case 15: // V_PK_ADD_U16,V_PK_SUB_U16,V_PK_MAX_U16,V_PK_MIN_U16,V_PK_ADD_F16, + case 16: case 17: case 18: case 49: case 50: // V_PK_MUL_F16,V_PK_MIN_F16,V_PK_MAX_F16,V_PK_MUL_F32,V_PK_ADD_F32, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_SRC_NOLIT(layout.SRC0,true,false); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false); + break; + case 4: case 5: case 6: // V_PK_LSHLREV_B16,V_PK_LSHRREV_B16,V_PK_ASHRREV_I16, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_SRC_SIMPLE(layout.SRC0,true,false); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false); + break; + case 51: // V_PK_MOV_B32, + appendOPR_VGPR(layout.VDST,false,true,2); + appendOPR_SRC_NOLIT(layout.SRC0,true,false,2); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false,2); + break; + case 88: // V_ACCVGPR_READ, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_SRC_ACCVGPR(layout.SRC0,true,false); + break; + case 89: // V_ACCVGPR_WRITE, + appendOPR_ACCVGPR(layout.VDST,false,true); + appendOPR_SRC_NOLIT(layout.SRC0,true,false); + break; + } + } + + void InstructionDecoder_amdgpu_gfx90a::finalizeENC_VOP3P_MFMAOperands() + { + layout_ENC_VOP3P_MFMA & layout = insn_layout.ENC_VOP3P_MFMA; + switch (layout.OP) { + case 64: case 80: case 104: // V_MFMA_F32_32X32X1F32,V_MFMA_I32_32X32X4I8,V_MFMA_F32_32X32X2BF16, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true,32); + appendOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,true,false); + appendOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,true,false); + appendOPR_SRC_VGPR_OR_ACCVGPR_OR_CONST(layout.SRC2,true,false,32); + break; + case 65: case 68: case 81: // V_MFMA_F32_16X16X1F32,V_MFMA_F32_32X32X2F32,V_MFMA_I32_16X16X4I8, + case 84: case 105: case 108: // V_MFMA_I32_32X32X8I8,V_MFMA_F32_16X16X2BF16,V_MFMA_F32_32X32X4BF16, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true,16); + appendOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,true,false); + appendOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,true,false); + appendOPR_SRC_VGPR_OR_ACCVGPR_OR_CONST(layout.SRC2,true,false,16); + break; + case 66: case 69: case 82: // V_MFMA_F32_4X4X1F32,V_MFMA_F32_16X16X4F32,V_MFMA_I32_4X4X4I8, + case 85: case 107: case 109: // V_MFMA_I32_16X16X16I8,V_MFMA_F32_4X4X2BF16,V_MFMA_F32_16X16X8BF16, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true,4); + appendOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,true,false); + appendOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,true,false); + appendOPR_SRC_VGPR_OR_ACCVGPR_OR_CONST(layout.SRC2,true,false,4); + break; + case 72: case 99: // V_MFMA_F32_32X32X4F16,V_MFMA_F32_32X32X4BF16_1K, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true,32); + appendOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,true,false,2); + appendOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,true,false,2); + appendOPR_SRC_VGPR_OR_ACCVGPR_OR_CONST(layout.SRC2,true,false,32); + break; + case 73: case 76: case 100: // V_MFMA_F32_16X16X4F16,V_MFMA_F32_32X32X8F16,V_MFMA_F32_16X16X4BF16_1K, + case 102: // V_MFMA_F32_32X32X8BF16_1K, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true,16); + appendOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,true,false,2); + appendOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,true,false,2); + appendOPR_SRC_VGPR_OR_ACCVGPR_OR_CONST(layout.SRC2,true,false,16); + break; + case 74: case 77: case 101: // V_MFMA_F32_4X4X4F16,V_MFMA_F32_16X16X16F16,V_MFMA_F32_4X4X4BF16_1K, + case 103: // V_MFMA_F32_16X16X16BF16_1K, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true,4); + appendOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,true,false,2); + appendOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,true,false,2); + appendOPR_SRC_VGPR_OR_ACCVGPR_OR_CONST(layout.SRC2,true,false,4); + break; + case 110: // V_MFMA_F64_16X16X4F64, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true,8); + appendOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,true,false,2); + appendOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,true,false,2); + appendOPR_SRC_VGPR_OR_ACCVGPR_OR_CONST(layout.SRC2,true,false,8); + break; + case 111: // V_MFMA_F64_4X4X4F64, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true,2); + appendOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,true,false,2); + appendOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,true,false,2); + appendOPR_SRC_VGPR_OR_ACCVGPR_OR_CONST(layout.SRC2,true,false,2); + break; + } + } + + void InstructionDecoder_amdgpu_gfx90a::finalizeENC_VOPCOperands() + { + layout_ENC_VOPC & layout = insn_layout.ENC_VOPC; + switch (layout.OP) { + case 16: case 20: case 32: case 33: // V_CMP_CLASS_F32,V_CMP_CLASS_F16,V_CMP_F_F16,V_CMP_LT_F16, + case 34: case 35: case 36: case 37: case 38: // V_CMP_EQ_F16,V_CMP_LE_F16,V_CMP_GT_F16,V_CMP_LG_F16,V_CMP_GE_F16, + case 39: case 40: case 41: case 42: case 43: // V_CMP_O_F16,V_CMP_U_F16,V_CMP_NGE_F16,V_CMP_NLG_F16,V_CMP_NGT_F16, + case 44: case 45: case 46: case 47: case 64: // V_CMP_NLE_F16,V_CMP_NEQ_F16,V_CMP_NLT_F16,V_CMP_TRU_F16,V_CMP_F_F32, + case 65: case 66: case 67: case 68: case 69: // V_CMP_LT_F32,V_CMP_EQ_F32,V_CMP_LE_F32,V_CMP_GT_F32,V_CMP_LG_F32, + case 70: case 71: case 72: case 73: case 74: // V_CMP_GE_F32,V_CMP_O_F32,V_CMP_U_F32,V_CMP_NGE_F32,V_CMP_NLG_F32, + case 75: case 76: case 77: case 78: // V_CMP_NGT_F32,V_CMP_NLE_F32,V_CMP_NEQ_F32,V_CMP_NLT_F32, + case 79: case 160: case 161: case 162: // V_CMP_TRU_F32,V_CMP_F_I16,V_CMP_LT_I16,V_CMP_EQ_I16, + case 163: case 164: case 165: case 166: // V_CMP_LE_I16,V_CMP_GT_I16,V_CMP_NE_I16,V_CMP_GE_I16, + case 167: case 168: case 169: case 170: case 171: // V_CMP_T_I16,V_CMP_F_U16,V_CMP_LT_U16,V_CMP_EQ_U16,V_CMP_LE_U16, + case 172: case 173: case 174: case 175: case 192: // V_CMP_GT_U16,V_CMP_NE_U16,V_CMP_GE_U16,V_CMP_T_U16,V_CMP_F_I32, + case 193: case 194: case 195: case 196: // V_CMP_LT_I32,V_CMP_EQ_I32,V_CMP_LE_I32,V_CMP_GT_I32, + case 197: case 198: case 199: case 200: case 201: // V_CMP_NE_I32,V_CMP_GE_I32,V_CMP_T_I32,V_CMP_F_U32,V_CMP_LT_U32, + case 202: case 203: case 204: case 205: // V_CMP_EQ_U32,V_CMP_LE_U32,V_CMP_GT_U32,V_CMP_NE_U32, + case 206: case 207: // V_CMP_GE_U32,V_CMP_T_U32, + appendOPR_VCC(0,false,true,2); + appendOPR_SRC(layout.SRC0,true,false); + appendOPR_VGPR(layout.VSRC1,true,false); + break; + case 17: case 21: case 48: case 49: // V_CMPX_CLASS_F32,V_CMPX_CLASS_F16,V_CMPX_F_F16,V_CMPX_LT_F16, + case 50: case 51: case 52: case 53: // V_CMPX_EQ_F16,V_CMPX_LE_F16,V_CMPX_GT_F16,V_CMPX_LG_F16, + case 54: case 55: case 56: case 57: // V_CMPX_GE_F16,V_CMPX_O_F16,V_CMPX_U_F16,V_CMPX_NGE_F16, + case 58: case 59: case 60: case 61: // V_CMPX_NLG_F16,V_CMPX_NGT_F16,V_CMPX_NLE_F16,V_CMPX_NEQ_F16, + case 62: case 63: case 80: case 81: // V_CMPX_NLT_F16,V_CMPX_TRU_F16,V_CMPX_F_F32,V_CMPX_LT_F32, + case 82: case 83: case 84: case 85: // V_CMPX_EQ_F32,V_CMPX_LE_F32,V_CMPX_GT_F32,V_CMPX_LG_F32, + case 86: case 87: case 88: case 89: // V_CMPX_GE_F32,V_CMPX_O_F32,V_CMPX_U_F32,V_CMPX_NGE_F32, + case 90: case 91: case 92: case 93: // V_CMPX_NLG_F32,V_CMPX_NGT_F32,V_CMPX_NLE_F32,V_CMPX_NEQ_F32, + case 94: case 95: case 176: case 177: // V_CMPX_NLT_F32,V_CMPX_TRU_F32,V_CMPX_F_I16,V_CMPX_LT_I16, + case 178: case 179: case 180: case 181: // V_CMPX_EQ_I16,V_CMPX_LE_I16,V_CMPX_GT_I16,V_CMPX_NE_I16, + case 182: case 183: case 184: case 185: // V_CMPX_GE_I16,V_CMPX_T_I16,V_CMPX_F_U16,V_CMPX_LT_U16, + case 186: case 187: case 188: case 189: // V_CMPX_EQ_U16,V_CMPX_LE_U16,V_CMPX_GT_U16,V_CMPX_NE_U16, + case 190: case 191: case 208: case 209: // V_CMPX_GE_U16,V_CMPX_T_U16,V_CMPX_F_I32,V_CMPX_LT_I32, + case 210: case 211: case 212: case 213: // V_CMPX_EQ_I32,V_CMPX_LE_I32,V_CMPX_GT_I32,V_CMPX_NE_I32, + case 214: case 215: case 216: case 217: // V_CMPX_GE_I32,V_CMPX_T_I32,V_CMPX_F_U32,V_CMPX_LT_U32, + case 218: case 219: case 220: case 221: // V_CMPX_EQ_U32,V_CMPX_LE_U32,V_CMPX_GT_U32,V_CMPX_NE_U32, + case 222: case 223: // V_CMPX_GE_U32,V_CMPX_T_U32, + appendOPR_VCC(0,false,true,2); + appendOPR_SRC(layout.SRC0,true,false); + appendOPR_VGPR(layout.VSRC1,true,false); + appendOPR_SDST_EXEC(126,false,true,1,true); + break; + case 18: // V_CMP_CLASS_F64, + appendOPR_VCC(0,false,true,2); + appendOPR_SRC(layout.SRC0,true,false,2); + appendOPR_VGPR(layout.VSRC1,true,false); + break; + case 19: // V_CMPX_CLASS_F64, + appendOPR_VCC(0,false,true,2); + appendOPR_SRC(layout.SRC0,true,false,2); + appendOPR_VGPR(layout.VSRC1,true,false); + appendOPR_SDST_EXEC(126,false,true,1,true); + break; + case 96: case 97: case 98: case 99: case 100: // V_CMP_F_F64,V_CMP_LT_F64,V_CMP_EQ_F64,V_CMP_LE_F64,V_CMP_GT_F64, + case 101: case 102: case 103: case 104: // V_CMP_LG_F64,V_CMP_GE_F64,V_CMP_O_F64,V_CMP_U_F64, + case 105: case 106: case 107: case 108: // V_CMP_NGE_F64,V_CMP_NLG_F64,V_CMP_NGT_F64,V_CMP_NLE_F64, + case 109: case 110: case 111: case 224: // V_CMP_NEQ_F64,V_CMP_NLT_F64,V_CMP_TRU_F64,V_CMP_F_I64, + case 225: case 226: case 227: case 228: // V_CMP_LT_I64,V_CMP_EQ_I64,V_CMP_LE_I64,V_CMP_GT_I64, + case 229: case 230: case 231: case 232: case 233: // V_CMP_NE_I64,V_CMP_GE_I64,V_CMP_T_I64,V_CMP_F_U64,V_CMP_LT_U64, + case 234: case 235: case 236: case 237: // V_CMP_EQ_U64,V_CMP_LE_U64,V_CMP_GT_U64,V_CMP_NE_U64, + case 238: case 239: // V_CMP_GE_U64,V_CMP_T_U64, + appendOPR_VCC(0,false,true,2); + appendOPR_SRC(layout.SRC0,true,false,2); + appendOPR_VGPR(layout.VSRC1,true,false,2); + break; + case 112: case 113: case 114: case 115: // V_CMPX_F_F64,V_CMPX_LT_F64,V_CMPX_EQ_F64,V_CMPX_LE_F64, + case 116: case 117: case 118: case 119: // V_CMPX_GT_F64,V_CMPX_LG_F64,V_CMPX_GE_F64,V_CMPX_O_F64, + case 120: case 121: case 122: case 123: // V_CMPX_U_F64,V_CMPX_NGE_F64,V_CMPX_NLG_F64,V_CMPX_NGT_F64, + case 124: case 125: case 126: case 127: // V_CMPX_NLE_F64,V_CMPX_NEQ_F64,V_CMPX_NLT_F64,V_CMPX_TRU_F64, + case 240: case 241: case 242: case 243: // V_CMPX_F_I64,V_CMPX_LT_I64,V_CMPX_EQ_I64,V_CMPX_LE_I64, + case 244: case 245: case 246: case 247: // V_CMPX_GT_I64,V_CMPX_NE_I64,V_CMPX_GE_I64,V_CMPX_T_I64, + case 248: case 249: case 250: case 251: // V_CMPX_F_U64,V_CMPX_LT_U64,V_CMPX_EQ_U64,V_CMPX_LE_U64, + case 252: case 253: case 254: case 255: // V_CMPX_GT_U64,V_CMPX_NE_U64,V_CMPX_GE_U64,V_CMPX_T_U64, + appendOPR_VCC(0,false,true,2); + appendOPR_SRC(layout.SRC0,true,false,2); + appendOPR_VGPR(layout.VSRC1,true,false,2); + appendOPR_SDST_EXEC(126,false,true,1,true); + break; + } + } + +void InstructionDecoder_amdgpu_gfx90a::finalizeENC_VINTRPOperands() { +} + +} +} diff --git a/instructionAPI/src/AMDGPU/gfx940/InstructionDecoder-amdgpu-gfx940.C b/instructionAPI/src/AMDGPU/gfx940/InstructionDecoder-amdgpu-gfx940.C new file mode 100644 index 0000000000..bd081bb0c7 --- /dev/null +++ b/instructionAPI/src/AMDGPU/gfx940/InstructionDecoder-amdgpu-gfx940.C @@ -0,0 +1,241 @@ +/* + * See the dyninst/COPYRIGHT file for copyright information. + * + * We provide the Paradyn Tools (below described as "Paradyn") + * on an AS IS basis, and do not warrant its validity or performance. + * We reserve the right to update, modify, or discontinue this + * software at any time. We shall have no obligation to supply such + * updates or modifications or any other form of support to you. + * + * By your use of Paradyn, you understand and agree that we (or any + * other person or entity with proprietary rights in Paradyn) are + * under no obligation to provide either maintenance services, + * update services, notices of latent defects, or correction of + * defects for Paradyn. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "Ternary.h" +#include "InstructionDecoder-amdgpu-gfx940.h" +#include +#include "registers/AMDGPU/amdgpu_gfx940_regs.h" + +namespace Dyninst { + namespace InstructionAPI { + typedef void (InstructionDecoder_amdgpu_gfx940::*operandFactory)(); + + typedef amdgpu_gfx940_insn_entry amdgpu_gfx940_insn_table[]; + + const std::array InstructionDecoder_amdgpu_gfx940::condNames = { { + "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", "hi", "ls", "ge", + "lt", "gt", "le", "al", "nv", + } }; + + const char* InstructionDecoder_amdgpu_gfx940::bitfieldInsnAliasMap(entryID) { + assert(!"no alias for entryID"); + return nullptr; + } + const char* InstructionDecoder_amdgpu_gfx940::condInsnAliasMap(entryID) { + assert(!"no alias for entryID"); + return nullptr; + } + + using namespace std; + Result_Type InstructionDecoder_amdgpu_gfx940::makeSizeType(unsigned int) { + assert(0); //not implemented + return u32; + } + + // **************** + // decoding opcodes + // **************** + + MachRegister InstructionDecoder_amdgpu_gfx940::makeAmdgpuRegID(MachRegister base, unsigned int encoding , unsigned int) { + return MachRegister(base.val() + encoding); + + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx940::makePCExpr() { + MachRegister baseReg = amdgpu_gfx940::pc_all; + return makeRegisterExpression(baseReg); + } + + void InstructionDecoder_amdgpu_gfx940::makeBranchTarget(bool branchIsCall, bool bIsConditional, int immVal, + int immLen_) { + Expression::Ptr lhs = makeAddExpression(makePCExpr(),Immediate::makeImmediate(Result(s48,4)),s48); + // * 4 => 2 more bits + int64_t offset = sign_extend64(immLen_+2, immVal * 4); + + Expression::Ptr rhs = Immediate::makeImmediate(Result(s64, offset)); + + insn_in_progress->addSuccessor(makeAddExpression(lhs, rhs, s64), branchIsCall, false, bIsConditional, + false); + if (bIsConditional || branchIsCall) { + insn_in_progress->addSuccessor(makeFallThroughExpr(), false, false, false, true); + } + + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx940::makeFallThroughExpr() { + // TODO: while s_call_B64 is always 4 bytes, it is not clear whether all instructions that has a fall through branch are 4 bytes long + return makeAddExpression(makePCExpr(), Immediate::makeImmediate(Result(u64, unsign_extend64(3, 4))), u64); + } + + + bool InstructionDecoder_amdgpu_gfx940::decodeOperands(const Instruction *) { + assert(0 && "decodeOperands deprecated for amdgpu"); + return true; + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx940::decodeSGPRorM0(unsigned int offset){ + if( offset <= 104) + return makeRegisterExpression(makeAmdgpuRegID(amdgpu_gfx940::s0,offset)); + if (offset == 124) + return makeRegisterExpression(amdgpu_gfx940::m0); + cerr << " unknown offset in sgpr or m0 " << offset << endl; + assert(0 && "shouldn't reach here"); + return {}; + } + + + + void InstructionDecoder_amdgpu_gfx940::processOPR_SMEM_OFFSET(layout_ENC_SMEM & layout){ + if (layout.IMM ==0 ){ + if( layout.SOFFSET_EN ==0 ) { + insn_in_progress-> appendOperand( decodeSGPRorM0(layout.OFFSET), true , false ); + }else{ + insn_in_progress-> appendOperand( decodeSGPRorM0(layout.SOFFSET), true , false ); + } + }else{ + if( layout.SOFFSET_EN ==0 ) { + insn_in_progress->appendOperand(Immediate::makeImmediate(Result(s64,layout.OFFSET)),false ,false); + }else{ + insn_in_progress->appendOperand(Immediate::makeImmediate(Result(s64,layout.OFFSET)),false,false); + insn_in_progress-> appendOperand( decodeSGPRorM0(layout.SOFFSET),true ,false); + } + } + } + uint32_t InstructionDecoder_amdgpu_gfx940::decodeOPR_LITERAL(){ + useImm = true; + immLen = 4; + if(insn_size == 4) + immLiteral = imm_at_32; + else if(insn_size ==8) + immLiteral = imm_at_64; + else + assert(0 && "unsupported instruction size"); + + return immLiteral; + } + Expression::Ptr InstructionDecoder_amdgpu_gfx940::decodeOPR_SDWA(){ + useImm = true; + immLen = 4; + if(insn_size == 4) + immLiteral = imm_at_32; + else if(insn_size ==8) + immLiteral = imm_at_64; + else + assert(0 && "unsupported instruction size"); + extension = std::string("_SDWA"); + uint8_t reg_idx = immLiteral & 0xff; + + return makeRegisterExpression(makeAmdgpuRegID(amdgpu_gfx940::v0,reg_idx),1); + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx940::decodeOPR_LABEL(uint64_t input){ + Expression::Ptr lhs = makeAddExpression(makePCExpr(),Immediate::makeImmediate(Result(s48,4)),s48); + // 16 bits immediate * 4 => 18 bits + int64_t offset = sign_extend64(18, input * 4); + Expression::Ptr rhs = Immediate::makeImmediate(Result(s64, offset)); + return makeAddExpression(lhs, rhs, s64); + + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx940::makeRegisterExpression(MachRegister registerID, uint32_t num_elements){ + if(registerID == amdgpu_gfx940::src_literal){ + return Immediate::makeImmediate(Result(u32,decodeOPR_LITERAL())); + } + return InstructionDecoderImpl::makeRegisterExpression(registerID,num_elements); + } + Expression::Ptr InstructionDecoder_amdgpu_gfx940::makeRegisterExpression(MachRegister registerID, uint32_t low, uint32_t high ){ + if(registerID == amdgpu_gfx940::src_literal){ + return Immediate::makeImmediate(Result(u32,decodeOPR_LITERAL())); + } + return InstructionDecoderImpl::makeRegisterExpression(registerID, low, high ); + } + + inline unsigned int InstructionDecoder_amdgpu_gfx940::get32bit(InstructionDecoder::buffer &b,unsigned int offset ){ + assert(offset %4 ==0 ); + if(b.start + offset + 4 <= b.end) + return b.start[offset+3] << 24 | b.start[offset + 2] << 16 | b.start[offset +1 ] << 8 | b.start [offset]; + return 0; + } + + + void InstructionDecoder_amdgpu_gfx940::reset(){ + immLen = 0; + insn_size = 0; + isBranch = false; + isConditional = false; + isModifyPC =false; + insn = insn_high = insn_long = 0; + useImm = false; + isCall = false; + extension = std::string(""); + } + // here we assemble the first 64 bit (if available) as an instruction + + void InstructionDecoder_amdgpu_gfx940::setupInsnWord(InstructionDecoder::buffer &b) { + reset(); + if (b.start > b.end) + return; + insn = get32bit(b,0); + + imm_at_32 = insn_high = get32bit(b,4); + imm_at_64 = get32bit(b,8); + + insn_long = ( ((uint64_t) insn_high) << 32) | insn; + } + void InstructionDecoder_amdgpu_gfx940::decodeOpcode(InstructionDecoder::buffer &b) { + setupInsnWord(b); + mainDecode(); + b.start += insn_in_progress->size(); + } + + void InstructionDecoder_amdgpu_gfx940::debug_instr(){ + // cout << "decoded instruction " << insn_in_progress->getOperation().mnemonic << " " << std::hex << insn_long << " insn_family = " << instr_family << " length = " << insn_in_progress->size()<< endl << endl; + } + + Instruction InstructionDecoder_amdgpu_gfx940::decode(InstructionDecoder::buffer &b) { + setupInsnWord(b); + mainDecode(); + b.start += insn_in_progress->size(); + return *insn_in_progress; + } + + void InstructionDecoder_amdgpu_gfx940::doDelayedDecode(const Instruction *insn_to_complete) { + + InstructionDecoder::buffer b(insn_to_complete->ptr(), insn_to_complete->size()); + setupInsnWord(b); + mainDecode(); + Instruction* iptr = const_cast(insn_to_complete); + *iptr = *(insn_in_progress.get()); + } + } +} + + + diff --git a/instructionAPI/src/AMDGPU/gfx940/InstructionDecoder-amdgpu-gfx940.h b/instructionAPI/src/AMDGPU/gfx940/InstructionDecoder-amdgpu-gfx940.h new file mode 100644 index 0000000000..75f5a2893b --- /dev/null +++ b/instructionAPI/src/AMDGPU/gfx940/InstructionDecoder-amdgpu-gfx940.h @@ -0,0 +1,3667 @@ +/* + * See the dyninst/COPYRIGHT file for copyright information. + * + * We provide the Paradyn Tools (below described as "Paradyn") + * on an AS IS basis, and do not warrant its validity or performance. + * We reserve the right to update, modify, or discontinue this + * software at any time. We shall have no obligation to supply such + * updates or modifications or any other form of support to you. + * + * By your use of Paradyn, you understand and agree that we (or any + * other person or entity with proprietary rights in Paradyn) are + * under no obligation to provide either maintenance services, + * update services, notices of latent defects, or correction of + * defects for Paradyn. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ +#ifndef INSTRUCTION_DECODER_GFX940_H +#define INSTRUCTION_DECODER_GFX940_H +#include +#include +#include +#include +#include "InstructionDecoderImpl.h" +#include +#include "Immediate.h" +#include "Architecture.h" +#include + +namespace Dyninst { + namespace InstructionAPI { + +#define insn_printf(format, ...) \ + do{ \ + printf("[%s:%u]insn_debug " format, FILE__, __LINE__, ## __VA_ARGS__); \ + }while(0) + + struct amdgpu_gfx940_insn_entry; + + class InstructionDecoder_amdgpu_gfx940 : public InstructionDecoderImpl { + friend struct amdgpu_gfx940_insn_entry; + friend struct amdgpu_mask_entry; + + public: + InstructionDecoder_amdgpu_gfx940(Architecture a) : InstructionDecoderImpl(a) {} + + virtual ~InstructionDecoder_amdgpu_gfx940() = default; + + virtual void decodeOpcode(InstructionDecoder::buffer &b); + + // decode one instruction starting from b.start + // will advance b.start whenver a instruction is successfully decoded + virtual Instruction decode(InstructionDecoder::buffer &b); + + virtual void setMode(bool) { } + + virtual bool decodeOperands(const Instruction *insn_to_complete); + + bool decodeOperands(const amdgpu_gfx940_insn_entry & insn_entry); + + virtual void doDelayedDecode(const Instruction *insn_to_complete); + + static const std::array condNames; + static MachRegister sysRegMap(unsigned int); + static const char* bitfieldInsnAliasMap(entryID); + static const char* condInsnAliasMap(entryID); + + + //Check if the index (2nd arg) is valid for the array (1st arg) + template + constexpr bool isArrayIndexValid(ArrayType (&)[n], const IndexType& i) const { + return 0 <= i && i < n; + } + + + private: + virtual Result_Type makeSizeType(unsigned int opType); + + bool is64Bit{}; + + unsigned int insn_size{}; // size of the instruction that we are currently working on + unsigned int insn{}; // the first 32 bit + unsigned int insn_high{}; // the second 32 bit + unsigned long long int insn_long{}; // the combined 64 bit: insn_high << 32 | insn + + // the main process of decoding an instruciton, won't advance buffer + void mainDecode(); + + void mainDecodeOpcode(); + + + void setupInsnWord(InstructionDecoder::buffer &b); + // pointer to the instruction that we are currently working on + dyncompat::shared_ptr insn_in_progress; + + template + int field(unsigned int raw) { +#if defined DEBUG_FIELD + std::cerr << start << "-" << end << ":" << std::dec << (raw >> (start) & + (0xFFFFFFFF >> (31 - (end - start)))) << " "; +#endif + return (raw >> (start) & (0xFFFFFFFF >> (31 - (end - start)))); + } + + template + int longfield(unsigned long long int raw) { +#if defined DEBUG_FIELD + std::cerr << start << "-" << end << ":" << std::dec << (raw >> (start) & + (0xFFFFFFFFFFFFFFFF >> (63 - (end - start)))) << " "; +#endif + return ( (raw >> (start)) & (0xFFFFFFFFFFFFFFFF >> (63 - (end - start)))); + } + + int32_t sign_extend32(int size_, int in) { + int32_t val = 0 | in; + + return (val << (32 - size_)) >> (32 - size_); + } + + int64_t sign_extend64(int size_, int in) { + int64_t val = 0 | in; + + return (val << (64 - size_)) >> (64 - size_); + } + + uint32_t unsign_extend32(int size_, int in) { + uint32_t mask = ~0; + + return (mask >> (32 - size_)) & in; + } + + uint64_t unsign_extend64(int size_, int in) { + uint64_t mask = ~0; + + return (mask >> (64 - size_)) & in; + } + + int highest_set_bit(int32_t val) { + for (int bit_index = 31; bit_index >= 0; bit_index--) + if (((static_cast(val) >> bit_index) & 0x1) == 0x1) + return bit_index + 1; + + return -1; + } + + int lowest_set_bit(int32_t val) { + for (int bit_index = 0; bit_index <= 31; bit_index++) + if (((static_cast(val) >> bit_index) & 0x1) == 0x1) + return bit_index + 1; + + return -1; + } + + std::string extension; + bool hasHw{}; + int hwField{}; + + void processHwFieldInsn(int, int); + + bool hasShift{}; + int shiftField{}; + + void makeBranchTarget(bool, bool, int, int immLen = 16); + + Expression::Ptr makeFallThroughExpr(); + + int _szField{}, size{}; + int _typeField{}; + int cmode{}; + int op{}; + int simdAlphabetImm{}; + + void processAlphabetImm(); + + void NOTHING(); + bool fix_bitfieldinsn_alias(int, int); + void fix_condinsn_alias_and_cond(int &); + void modify_mnemonic_simd_upperhalf_insns(); + + MachRegister makeAmdgpuRegID(MachRegister, unsigned int, unsigned int len = 1); + + MachRegister getLoadStoreSimdRegister(int encoding); + + Expression::Ptr makePCExpr(); + + + template + Expression::Ptr makeLogicalImm(int immr, int imms, int immsLen, Result_Type rT); + + + //for load store + void insnSize(unsigned int insn_size ); + + Expression::Ptr decodeSSRC(unsigned int index); + Expression::Ptr decodeVSRC(unsigned int index); + Expression::Ptr decodeVDST(unsigned int index); + + Expression::Ptr decodeSGPRorM0(unsigned int offset); + + + bool useImm{}; + uint32_t immLen{}; // extra 4 bytes included for decoding instruction + uint32_t immLiteral{}; + uint32_t imm_at_32{}; + uint32_t imm_at_64{}; + uint32_t imm_at_96{}; + + bool isBranch{}; // this is set for all branch instructions, + bool isConditional{}; // this is set for all conditional branch instruction, will set branchCond + bool isCall{}; // this is a call function + + + + // this is set for instructions that directly modify pc + // namely s_setpc and s_swappc + bool isModifyPC{}; + + // reset the decoder internal state for decoding the next instruction + void reset(); + + Expression::Ptr branchCond; + Expression::Ptr branchTarget; + + void setBranch() { + isBranch = true; + } + + void setConditionalBranch() { + isConditional = true; + // TODO : set conditional branch + } + void setModifyPC() { + isModifyPC = true; + } + + void setCall() { + isCall = true; + } + + inline unsigned int get32bit(InstructionDecoder::buffer &b,unsigned int offset ); + + template + void setUseImm(InstructionDecoder::buffer & b, unsigned int offset) + { + if (longfield(insn_long) == candidate) { + useImm = true; + immLen = 4; + immLiteral = get32bit(b,offset); + } + + } + + typedef struct buffer_resource_desc{ + unsigned long long base_address; + unsigned stride; + unsigned cache_swizzle; + unsigned swizzle_enable; + unsigned num_records; + unsigned dst_sel_x; + unsigned dst_sel_y; + unsigned dst_sel_z; + unsigned dst_sel_w; + unsigned num_format; + unsigned data_format; + unsigned user_vm_enable; + unsigned user_vm_mode; + unsigned index_stride; + unsigned add_tid_enable; + unsigned non_volatile; + unsigned type; + }buffer_resource_desc; + + void debug_instr(); + + uint32_t decodeOPR_LITERAL(); + Expression::Ptr decodeOPR_SDWA(); + Expression::Ptr decodeOPR_LABEL(uint64_t input); + using InstructionDecoderImpl::makeRegisterExpression; + Expression::Ptr makeRegisterExpression(MachRegister registerID, uint32_t num_elements = 1); + Expression::Ptr makeRegisterExpression(MachRegister registerID, uint32_t low , uint32_t high ); + void specialHandle(); + + static bool IS_ENC_SOP1(uint64_t I); + static bool IS_ENC_SOPC(uint64_t I); + static bool IS_ENC_SOPP(uint64_t I); + static bool IS_ENC_SOPK(uint64_t I); + static bool IS_ENC_SOP2(uint64_t I); + static bool IS_ENC_SMEM(uint64_t I); + static bool IS_ENC_VOP1(uint64_t I); + static bool IS_ENC_VOPC(uint64_t I); + static bool IS_ENC_VOP2(uint64_t I); + static bool IS_ENC_VINTRP(uint64_t I); + static bool IS_ENC_VOP3P(uint64_t I); + static bool IS_ENC_VOP3(uint64_t I); + static bool IS_ENC_DS(uint64_t I); + static bool IS_ENC_MUBUF(uint64_t I); + static bool IS_ENC_MTBUF(uint64_t I); + static bool IS_ENC_MIMG(uint64_t I); + static bool IS_ENC_FLAT(uint64_t I); + static bool IS_ENC_FLAT_GLBL(uint64_t I); + static bool IS_ENC_FLAT_SCRATCH(uint64_t I); + static bool IS_SOPK_INST_LITERAL_(uint64_t I); + static bool IS_ENC_VOP2_LITERAL(uint64_t I); + static bool IS_ENC_VOP3B(uint64_t I); + static bool IS_ENC_VOP3P_MFMA(uint64_t I); + enum InstructionFamily + { + ENC_SOP1 = -1, + ENC_SOPC = 0, + ENC_SOPP = 1, + ENC_SOPK = 2, + ENC_SOP2 = 3, + ENC_SMEM = 4, + ENC_VOP1 = 5, + ENC_VOPC = 6, + ENC_VOP2 = 7, + ENC_VINTRP = 8, + ENC_VOP3P = 9, + ENC_VOP3 = 10, + ENC_DS = 11, + ENC_MUBUF = 12, + ENC_MTBUF = 13, + ENC_MIMG = 14, + ENC_FLAT = 16, + ENC_FLAT_GLBL = 17, + ENC_FLAT_SCRATCH = 18, + SOPK_INST_LITERAL_ = 19, + ENC_VOP2_LITERAL = 20, + ENC_VOP3B = 21, + ENC_VOP3P_MFMA = 22, + }; + InstructionFamily instr_family; + struct layout_ENC_SOP1 { + uint16_t ENCODING : 9; + uint8_t OP : 8; + uint8_t SDST : 7; + uint8_t SSRC0 : 8; + }; + struct layout_ENC_SOPC { + uint16_t ENCODING : 9; + uint8_t OP : 7; + uint8_t SSRC0 : 8; + uint8_t SSRC1 : 8; + }; + struct layout_ENC_SOPP { + uint16_t ENCODING : 9; + uint8_t OP : 7; + uint16_t SIMM16 : 16; + }; + struct layout_ENC_SOPK { + uint8_t ENCODING : 4; + uint8_t OP : 5; + uint8_t SDST : 7; + uint16_t SIMM16 : 16; + }; + struct layout_ENC_SOP2 { + uint8_t ENCODING : 2; + uint8_t OP : 7; + uint8_t SDST : 7; + uint8_t SSRC0 : 8; + uint8_t SSRC1 : 8; + }; + struct layout_ENC_SMEM { + uint8_t ENCODING : 6; + uint8_t GLC : 1; + uint8_t IMM : 1; + uint8_t NV : 1; + uint32_t OFFSET : 21; + uint8_t OP : 8; + uint8_t SBASE : 7; + uint8_t SDATA : 7; + uint8_t SOFFSET : 7; + uint8_t SOFFSET_EN : 1; + }; + struct layout_ENC_VOP1 { + uint8_t ENCODING : 7; + uint8_t OP : 8; + uint16_t SRC0 : 9; + uint8_t VDST : 8; + }; + struct layout_ENC_VOPC { + uint8_t ENCODING : 7; + uint8_t OP : 8; + uint16_t SRC0 : 9; + uint8_t VSRC1 : 8; + }; + struct layout_ENC_VOP2 { + uint8_t ENCODING : 1; + uint8_t OP : 6; + uint16_t SRC0 : 9; + uint8_t VDST : 8; + uint8_t VSRC1 : 8; + }; + struct layout_ENC_VINTRP { + uint8_t ATTR : 6; + uint8_t ATTRCHAN : 2; + uint8_t ENCODING : 6; + uint8_t OP : 2; + uint8_t VDST : 8; + uint8_t VSRC : 8; + }; + struct layout_ENC_VOP3P { + uint8_t CLAMP : 1; + uint16_t ENCODING : 9; + uint8_t NEG : 3; + uint8_t NEG_HI : 3; + uint8_t OP : 7; + uint8_t OP_SEL : 3; + uint8_t OP_SEL_HI : 2; + uint8_t OP_SEL_HI_2 : 1; + uint16_t SRC0 : 9; + uint16_t SRC1 : 9; + uint16_t SRC2 : 9; + uint8_t VDST : 8; + }; + struct layout_ENC_VOP3 { + uint8_t ABS : 3; + uint8_t CLAMP : 1; + uint8_t ENCODING : 6; + uint8_t NEG : 3; + uint8_t OMOD : 2; + uint16_t OP : 10; + uint8_t OP_SEL : 4; + uint16_t SRC0 : 9; + uint16_t SRC1 : 9; + uint16_t SRC2 : 9; + uint8_t VDST : 8; + }; + struct layout_ENC_DS { + uint8_t ACC : 1; + uint8_t ADDR : 8; + uint8_t DATA0 : 8; + uint8_t DATA1 : 8; + uint8_t ENCODING : 6; + uint8_t GDS : 1; + uint8_t OFFSET0 : 8; + uint8_t OFFSET1 : 8; + uint8_t OP : 8; + uint8_t VDST : 8; + }; + struct layout_ENC_MUBUF { + uint8_t ACC : 1; + uint8_t ENCODING : 6; + uint8_t IDXEN : 1; + uint8_t LDS : 1; + uint8_t NT : 1; + uint8_t OFFEN : 1; + uint16_t OFFSET : 12; + uint8_t OP : 7; + uint8_t SC0 : 1; + uint8_t SC1 : 1; + uint8_t SOFFSET : 8; + uint8_t SRSRC : 7; + uint8_t VADDR : 8; + uint8_t VDATA : 8; + }; + struct layout_ENC_MTBUF { + uint8_t ACC : 1; + uint8_t DFMT : 4; + uint8_t ENCODING : 6; + uint8_t IDXEN : 1; + uint8_t NFMT : 3; + uint8_t NT : 1; + uint8_t OFFEN : 1; + uint16_t OFFSET : 12; + uint8_t OP : 4; + uint8_t SC0 : 1; + uint8_t SC1 : 1; + uint8_t SOFFSET : 8; + uint8_t SRSRC : 7; + uint8_t VADDR : 8; + uint8_t VDATA : 8; + }; + struct layout_ENC_MIMG { + uint8_t A16 : 1; + uint8_t ACC : 1; + uint8_t D16 : 1; + uint8_t DA : 1; + uint8_t DMASK : 4; + uint8_t ENCODING : 6; + uint8_t LWE : 1; + uint8_t NT : 1; + uint8_t OP : 7; + uint8_t OPM : 1; + uint8_t SC0 : 1; + uint8_t SC1 : 1; + uint8_t SRSRC : 7; + uint8_t SSAMP : 7; + uint8_t UNORM : 1; + uint8_t VADDR : 8; + uint8_t VDATA : 8; + }; + struct layout_ENC_FLAT { + uint8_t ACC : 1; + uint8_t ADDR : 8; + uint8_t DATA : 8; + uint8_t ENCODING : 6; + uint8_t NT : 1; + uint16_t OFFSET : 12; + uint8_t OP : 7; + uint8_t SADDR : 7; + uint8_t SC0 : 1; + uint8_t SC1 : 1; + uint8_t SEG : 2; + uint8_t SVE : 1; + uint8_t VDST : 8; + }; + struct layout_ENC_FLAT_GLBL { + uint8_t ACC : 1; + uint8_t ADDR : 8; + uint8_t DATA : 8; + uint8_t ENCODING : 6; + uint8_t NT : 1; + uint16_t OFFSET : 13; + uint8_t OP : 7; + uint8_t SADDR : 7; + uint8_t SC0 : 1; + uint8_t SC1 : 1; + uint8_t SEG : 2; + uint8_t SVE : 1; + uint8_t VDST : 8; + }; + struct layout_ENC_FLAT_SCRATCH { + uint8_t ACC : 1; + uint8_t ADDR : 8; + uint8_t DATA : 8; + uint8_t ENCODING : 6; + uint8_t NT : 1; + uint16_t OFFSET : 13; + uint8_t OP : 7; + uint8_t SADDR : 7; + uint8_t SC0 : 1; + uint8_t SC1 : 1; + uint8_t SEG : 2; + uint8_t SVE : 1; + uint8_t VDST : 8; + }; + struct layout_SOPK_INST_LITERAL_ { + uint8_t ENCODING : 4; + uint8_t OP : 5; + uint8_t SDST : 7; + uint16_t SIMM16 : 16; + uint32_t SIMM32 : 32; + }; + struct layout_ENC_VOP2_LITERAL { + uint8_t ENCODING : 1; + uint8_t OP : 6; + uint32_t SIMM32 : 32; + uint16_t SRC0 : 9; + uint8_t VDST : 8; + uint8_t VSRC1 : 8; + }; + struct layout_ENC_VOP3B { + uint8_t CLAMP : 1; + uint8_t ENCODING : 6; + uint8_t NEG : 3; + uint8_t OMOD : 2; + uint16_t OP : 10; + uint8_t SDST : 7; + uint16_t SRC0 : 9; + uint16_t SRC1 : 9; + uint16_t SRC2 : 9; + uint8_t VDST : 8; + }; + struct layout_ENC_VOP3P_MFMA { + uint8_t ABID : 4; + uint8_t ACC : 2; + uint8_t ACC_CD : 1; + uint8_t BLGP : 3; + uint8_t CBSZ : 3; + uint16_t ENCODING : 9; + uint8_t OP : 7; + uint16_t SRC0 : 9; + uint16_t SRC1 : 9; + uint16_t SRC2 : 9; + uint8_t VDST : 8; + }; + union insn_layout{ + + layout_ENC_SOP1 ENC_SOP1; + layout_ENC_SOPC ENC_SOPC; + layout_ENC_SOPP ENC_SOPP; + layout_ENC_SOPK ENC_SOPK; + layout_ENC_SOP2 ENC_SOP2; + layout_ENC_SMEM ENC_SMEM; + layout_ENC_VOP1 ENC_VOP1; + layout_ENC_VOPC ENC_VOPC; + layout_ENC_VOP2 ENC_VOP2; + layout_ENC_VINTRP ENC_VINTRP; + layout_ENC_VOP3P ENC_VOP3P; + layout_ENC_VOP3 ENC_VOP3; + layout_ENC_DS ENC_DS; + layout_ENC_MUBUF ENC_MUBUF; + layout_ENC_MTBUF ENC_MTBUF; + layout_ENC_MIMG ENC_MIMG; + layout_ENC_FLAT ENC_FLAT; + layout_ENC_FLAT_GLBL ENC_FLAT_GLBL; + layout_ENC_FLAT_SCRATCH ENC_FLAT_SCRATCH; + layout_SOPK_INST_LITERAL_ SOPK_INST_LITERAL_; + layout_ENC_VOP2_LITERAL ENC_VOP2_LITERAL; + layout_ENC_VOP3B ENC_VOP3B; + layout_ENC_VOP3P_MFMA ENC_VOP3P_MFMA; + }insn_layout; + void decodeENC_SOP1(); + void finalizeENC_SOP1Operands(); + void decodeENC_SOPC(); + void finalizeENC_SOPCOperands(); + void decodeENC_SOPP(); + void finalizeENC_SOPPOperands(); + void decodeENC_SOPK(); + void finalizeENC_SOPKOperands(); + void decodeENC_SOP2(); + void finalizeENC_SOP2Operands(); + void decodeENC_SMEM(); + void finalizeENC_SMEMOperands(); + void decodeENC_VOP1(); + void finalizeENC_VOP1Operands(); + void decodeENC_VOPC(); + void finalizeENC_VOPCOperands(); + void decodeENC_VOP2(); + void finalizeENC_VOP2Operands(); + void decodeENC_VINTRP(); + void finalizeENC_VINTRPOperands(); + void decodeENC_VOP3P(); + void finalizeENC_VOP3POperands(); + void decodeENC_VOP3(); + void finalizeENC_VOP3Operands(); + void decodeENC_DS(); + void finalizeENC_DSOperands(); + void decodeENC_MUBUF(); + void finalizeENC_MUBUFOperands(); + void decodeENC_MTBUF(); + void finalizeENC_MTBUFOperands(); + void decodeENC_MIMG(); + void finalizeENC_MIMGOperands(); + void decodeENC_FLAT(); + void finalizeENC_FLATOperands(); + void decodeENC_FLAT_GLBL(); + void finalizeENC_FLAT_GLBLOperands(); + void decodeENC_FLAT_SCRATCH(); + void finalizeENC_FLAT_SCRATCHOperands(); + void decodeSOPK_INST_LITERAL_(); + void finalizeSOPK_INST_LITERAL_Operands(); + void decodeENC_VOP2_LITERAL(); + void finalizeENC_VOP2_LITERALOperands(); + void decodeENC_VOP3B(); + void finalizeENC_VOP3BOperands(); + void decodeENC_VOP3P_MFMA(); + void finalizeENC_VOP3P_MFMAOperands(); + + + Expression::Ptr decodeOPR_ACCVGPR(uint64_t input, uint32_t output_vec_len = 1 ); + Expression::Ptr decodeOPR_DSMEM(uint64_t input, uint32_t output_vec_len = 1 ); + Expression::Ptr decodeOPR_FLAT_SCRATCH(uint64_t input, uint32_t output_vec_len = 1 ); + Expression::Ptr decodeOPR_PC(uint64_t input, uint32_t output_vec_len = 1 ); + Expression::Ptr decodeOPR_SDST(uint64_t input, uint32_t output_vec_len = 1 ); + Expression::Ptr decodeOPR_SDST_EXEC(uint64_t input, uint32_t output_vec_len = 1 ); + Expression::Ptr decodeOPR_SDST_M0(uint64_t input, uint32_t output_vec_len = 1 ); + Expression::Ptr decodeOPR_SRC(uint64_t input, uint32_t output_vec_len = 1 ); + Expression::Ptr decodeOPR_SRC_ACCVGPR(uint64_t input, uint32_t output_vec_len = 1 ); + Expression::Ptr decodeOPR_SRC_NOLDS(uint64_t input, uint32_t output_vec_len = 1 ); + Expression::Ptr decodeOPR_SRC_NOLIT(uint64_t input, uint32_t output_vec_len = 1 ); + Expression::Ptr decodeOPR_SRC_SIMPLE(uint64_t input, uint32_t output_vec_len = 1 ); + Expression::Ptr decodeOPR_SRC_VGPR(uint64_t input, uint32_t output_vec_len = 1 ); + Expression::Ptr decodeOPR_SRC_VGPR_OR_ACCVGPR(uint64_t input, uint32_t output_vec_len = 1 ); + Expression::Ptr decodeOPR_SRC_VGPR_OR_ACCVGPR_OR_CONST(uint64_t input, uint32_t output_vec_len = 1 ); + Expression::Ptr decodeOPR_SREG(uint64_t input, uint32_t output_vec_len = 1 ); + Expression::Ptr decodeOPR_SREG_NOVCC(uint64_t input, uint32_t output_vec_len = 1 ); + Expression::Ptr decodeOPR_SSRC(uint64_t input, uint32_t output_vec_len = 1 ); + Expression::Ptr decodeOPR_SSRC_LANESEL(uint64_t input, uint32_t output_vec_len = 1 ); + Expression::Ptr decodeOPR_SSRC_NOLIT(uint64_t input, uint32_t output_vec_len = 1 ); + Expression::Ptr decodeOPR_SSRC_SPECIAL_SCC(uint64_t input, uint32_t output_vec_len = 1 ); + Expression::Ptr decodeOPR_VCC(uint64_t input, uint32_t output_vec_len = 1 ); + Expression::Ptr decodeOPR_VGPR(uint64_t input, uint32_t output_vec_len = 1 ); + Expression::Ptr decodeOPR_VGPR_OR_ACCVGPR(uint64_t input, uint32_t output_vec_len = 1 ); + Expression::Ptr decodeOPR_VGPR_OR_LDS(uint64_t input, uint32_t output_vec_len = 1 ); + + + void appendOPR_SIMM4(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_SIMM8(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_SIMM16(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_SIMM32(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_WAITCNT(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_ACCVGPR(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_DSMEM(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_FLAT_SCRATCH(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_PC(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_SDST(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_SDST_EXEC(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_SDST_M0(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void processOPR_SMEM_OFFSET(layout_ENC_SMEM & layout ); + + void appendOPR_SRC(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_SRC_ACCVGPR(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_SRC_NOLDS(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_SRC_NOLIT(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_SRC_SIMPLE(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_SRC_VGPR(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_SRC_VGPR_OR_ACCVGPR(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_SRC_VGPR_OR_ACCVGPR_OR_CONST(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_SREG(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_SREG_NOVCC(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_SSRC(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_SSRC_LANESEL(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_SSRC_NOLIT(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_SSRC_SPECIAL_SCC(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_VCC(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_VGPR(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_VGPR_OR_ACCVGPR(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + void appendOPR_VGPR_OR_LDS(uint64_t input, bool isRead, bool isWritten, uint32_t _num_elements = 1, bool isImplicit = false); + + + + struct amdgpu_gfx940_insn_entry { + entryID op; + const char *mnemonic; + }; + + + const amdgpu_gfx940_insn_entry ENC_DS_insn_table[256] = + { + {amdgpu_gfx940_op_DS_ADD_U32,"DS_ADD_U32"}, // 0 + {amdgpu_gfx940_op_DS_SUB_U32,"DS_SUB_U32"}, // 1 + {amdgpu_gfx940_op_DS_RSUB_U32,"DS_RSUB_U32"}, // 2 + {amdgpu_gfx940_op_DS_INC_U32,"DS_INC_U32"}, // 3 + {amdgpu_gfx940_op_DS_DEC_U32,"DS_DEC_U32"}, // 4 + {amdgpu_gfx940_op_DS_MIN_I32,"DS_MIN_I32"}, // 5 + {amdgpu_gfx940_op_DS_MAX_I32,"DS_MAX_I32"}, // 6 + {amdgpu_gfx940_op_DS_MIN_U32,"DS_MIN_U32"}, // 7 + {amdgpu_gfx940_op_DS_MAX_U32,"DS_MAX_U32"}, // 8 + {amdgpu_gfx940_op_DS_AND_B32,"DS_AND_B32"}, // 9 + {amdgpu_gfx940_op_DS_OR_B32,"DS_OR_B32"}, // 10 + {amdgpu_gfx940_op_DS_XOR_B32,"DS_XOR_B32"}, // 11 + {amdgpu_gfx940_op_DS_MSKOR_B32,"DS_MSKOR_B32"}, // 12 + {amdgpu_gfx940_op_DS_WRITE_B32,"DS_WRITE_B32"}, // 13 + {amdgpu_gfx940_op_DS_WRITE2_B32,"DS_WRITE2_B32"}, // 14 + {amdgpu_gfx940_op_DS_WRITE2ST64_B32,"DS_WRITE2ST64_B32"}, // 15 + {amdgpu_gfx940_op_DS_CMPST_B32,"DS_CMPST_B32"}, // 16 + {amdgpu_gfx940_op_DS_CMPST_F32,"DS_CMPST_F32"}, // 17 + {amdgpu_gfx940_op_DS_MIN_F32,"DS_MIN_F32"}, // 18 + {amdgpu_gfx940_op_DS_MAX_F32,"DS_MAX_F32"}, // 19 + {amdgpu_gfx940_op_DS_NOP,"DS_NOP"}, // 20 + {amdgpu_gfx940_op_DS_ADD_F32,"DS_ADD_F32"}, // 21 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 22 + {amdgpu_gfx940_op_DS_PK_ADD_F16,"DS_PK_ADD_F16"}, // 23 + {amdgpu_gfx940_op_DS_PK_ADD_BF16,"DS_PK_ADD_BF16"}, // 24 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 25 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 26 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 27 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 28 + {amdgpu_gfx940_op_DS_WRITE_ADDTID_B32,"DS_WRITE_ADDTID_B32"}, // 29 + {amdgpu_gfx940_op_DS_WRITE_B8,"DS_WRITE_B8"}, // 30 + {amdgpu_gfx940_op_DS_WRITE_B16,"DS_WRITE_B16"}, // 31 + {amdgpu_gfx940_op_DS_ADD_RTN_U32,"DS_ADD_RTN_U32"}, // 32 + {amdgpu_gfx940_op_DS_SUB_RTN_U32,"DS_SUB_RTN_U32"}, // 33 + {amdgpu_gfx940_op_DS_RSUB_RTN_U32,"DS_RSUB_RTN_U32"}, // 34 + {amdgpu_gfx940_op_DS_INC_RTN_U32,"DS_INC_RTN_U32"}, // 35 + {amdgpu_gfx940_op_DS_DEC_RTN_U32,"DS_DEC_RTN_U32"}, // 36 + {amdgpu_gfx940_op_DS_MIN_RTN_I32,"DS_MIN_RTN_I32"}, // 37 + {amdgpu_gfx940_op_DS_MAX_RTN_I32,"DS_MAX_RTN_I32"}, // 38 + {amdgpu_gfx940_op_DS_MIN_RTN_U32,"DS_MIN_RTN_U32"}, // 39 + {amdgpu_gfx940_op_DS_MAX_RTN_U32,"DS_MAX_RTN_U32"}, // 40 + {amdgpu_gfx940_op_DS_AND_RTN_B32,"DS_AND_RTN_B32"}, // 41 + {amdgpu_gfx940_op_DS_OR_RTN_B32,"DS_OR_RTN_B32"}, // 42 + {amdgpu_gfx940_op_DS_XOR_RTN_B32,"DS_XOR_RTN_B32"}, // 43 + {amdgpu_gfx940_op_DS_MSKOR_RTN_B32,"DS_MSKOR_RTN_B32"}, // 44 + {amdgpu_gfx940_op_DS_WRXCHG_RTN_B32,"DS_WRXCHG_RTN_B32"}, // 45 + {amdgpu_gfx940_op_DS_WRXCHG2_RTN_B32,"DS_WRXCHG2_RTN_B32"}, // 46 + {amdgpu_gfx940_op_DS_WRXCHG2ST64_RTN_B32,"DS_WRXCHG2ST64_RTN_B32"}, // 47 + {amdgpu_gfx940_op_DS_CMPST_RTN_B32,"DS_CMPST_RTN_B32"}, // 48 + {amdgpu_gfx940_op_DS_CMPST_RTN_F32,"DS_CMPST_RTN_F32"}, // 49 + {amdgpu_gfx940_op_DS_MIN_RTN_F32,"DS_MIN_RTN_F32"}, // 50 + {amdgpu_gfx940_op_DS_MAX_RTN_F32,"DS_MAX_RTN_F32"}, // 51 + {amdgpu_gfx940_op_DS_WRAP_RTN_B32,"DS_WRAP_RTN_B32"}, // 52 + {amdgpu_gfx940_op_DS_ADD_RTN_F32,"DS_ADD_RTN_F32"}, // 53 + {amdgpu_gfx940_op_DS_READ_B32,"DS_READ_B32"}, // 54 + {amdgpu_gfx940_op_DS_READ2_B32,"DS_READ2_B32"}, // 55 + {amdgpu_gfx940_op_DS_READ2ST64_B32,"DS_READ2ST64_B32"}, // 56 + {amdgpu_gfx940_op_DS_READ_I8,"DS_READ_I8"}, // 57 + {amdgpu_gfx940_op_DS_READ_U8,"DS_READ_U8"}, // 58 + {amdgpu_gfx940_op_DS_READ_I16,"DS_READ_I16"}, // 59 + {amdgpu_gfx940_op_DS_READ_U16,"DS_READ_U16"}, // 60 + {amdgpu_gfx940_op_DS_SWIZZLE_B32,"DS_SWIZZLE_B32"}, // 61 + {amdgpu_gfx940_op_DS_PERMUTE_B32,"DS_PERMUTE_B32"}, // 62 + {amdgpu_gfx940_op_DS_BPERMUTE_B32,"DS_BPERMUTE_B32"}, // 63 + {amdgpu_gfx940_op_DS_ADD_U64,"DS_ADD_U64"}, // 64 + {amdgpu_gfx940_op_DS_SUB_U64,"DS_SUB_U64"}, // 65 + {amdgpu_gfx940_op_DS_RSUB_U64,"DS_RSUB_U64"}, // 66 + {amdgpu_gfx940_op_DS_INC_U64,"DS_INC_U64"}, // 67 + {amdgpu_gfx940_op_DS_DEC_U64,"DS_DEC_U64"}, // 68 + {amdgpu_gfx940_op_DS_MIN_I64,"DS_MIN_I64"}, // 69 + {amdgpu_gfx940_op_DS_MAX_I64,"DS_MAX_I64"}, // 70 + {amdgpu_gfx940_op_DS_MIN_U64,"DS_MIN_U64"}, // 71 + {amdgpu_gfx940_op_DS_MAX_U64,"DS_MAX_U64"}, // 72 + {amdgpu_gfx940_op_DS_AND_B64,"DS_AND_B64"}, // 73 + {amdgpu_gfx940_op_DS_OR_B64,"DS_OR_B64"}, // 74 + {amdgpu_gfx940_op_DS_XOR_B64,"DS_XOR_B64"}, // 75 + {amdgpu_gfx940_op_DS_MSKOR_B64,"DS_MSKOR_B64"}, // 76 + {amdgpu_gfx940_op_DS_WRITE_B64,"DS_WRITE_B64"}, // 77 + {amdgpu_gfx940_op_DS_WRITE2_B64,"DS_WRITE2_B64"}, // 78 + {amdgpu_gfx940_op_DS_WRITE2ST64_B64,"DS_WRITE2ST64_B64"}, // 79 + {amdgpu_gfx940_op_DS_CMPST_B64,"DS_CMPST_B64"}, // 80 + {amdgpu_gfx940_op_DS_CMPST_F64,"DS_CMPST_F64"}, // 81 + {amdgpu_gfx940_op_DS_MIN_F64,"DS_MIN_F64"}, // 82 + {amdgpu_gfx940_op_DS_MAX_F64,"DS_MAX_F64"}, // 83 + {amdgpu_gfx940_op_DS_WRITE_B8_D16_HI,"DS_WRITE_B8_D16_HI"}, // 84 + {amdgpu_gfx940_op_DS_WRITE_B16_D16_HI,"DS_WRITE_B16_D16_HI"}, // 85 + {amdgpu_gfx940_op_DS_READ_U8_D16,"DS_READ_U8_D16"}, // 86 + {amdgpu_gfx940_op_DS_READ_U8_D16_HI,"DS_READ_U8_D16_HI"}, // 87 + {amdgpu_gfx940_op_DS_READ_I8_D16,"DS_READ_I8_D16"}, // 88 + {amdgpu_gfx940_op_DS_READ_I8_D16_HI,"DS_READ_I8_D16_HI"}, // 89 + {amdgpu_gfx940_op_DS_READ_U16_D16,"DS_READ_U16_D16"}, // 90 + {amdgpu_gfx940_op_DS_READ_U16_D16_HI,"DS_READ_U16_D16_HI"}, // 91 + {amdgpu_gfx940_op_DS_ADD_F64,"DS_ADD_F64"}, // 92 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 93 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 94 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 95 + {amdgpu_gfx940_op_DS_ADD_RTN_U64,"DS_ADD_RTN_U64"}, // 96 + {amdgpu_gfx940_op_DS_SUB_RTN_U64,"DS_SUB_RTN_U64"}, // 97 + {amdgpu_gfx940_op_DS_RSUB_RTN_U64,"DS_RSUB_RTN_U64"}, // 98 + {amdgpu_gfx940_op_DS_INC_RTN_U64,"DS_INC_RTN_U64"}, // 99 + {amdgpu_gfx940_op_DS_DEC_RTN_U64,"DS_DEC_RTN_U64"}, // 100 + {amdgpu_gfx940_op_DS_MIN_RTN_I64,"DS_MIN_RTN_I64"}, // 101 + {amdgpu_gfx940_op_DS_MAX_RTN_I64,"DS_MAX_RTN_I64"}, // 102 + {amdgpu_gfx940_op_DS_MIN_RTN_U64,"DS_MIN_RTN_U64"}, // 103 + {amdgpu_gfx940_op_DS_MAX_RTN_U64,"DS_MAX_RTN_U64"}, // 104 + {amdgpu_gfx940_op_DS_AND_RTN_B64,"DS_AND_RTN_B64"}, // 105 + {amdgpu_gfx940_op_DS_OR_RTN_B64,"DS_OR_RTN_B64"}, // 106 + {amdgpu_gfx940_op_DS_XOR_RTN_B64,"DS_XOR_RTN_B64"}, // 107 + {amdgpu_gfx940_op_DS_MSKOR_RTN_B64,"DS_MSKOR_RTN_B64"}, // 108 + {amdgpu_gfx940_op_DS_WRXCHG_RTN_B64,"DS_WRXCHG_RTN_B64"}, // 109 + {amdgpu_gfx940_op_DS_WRXCHG2_RTN_B64,"DS_WRXCHG2_RTN_B64"}, // 110 + {amdgpu_gfx940_op_DS_WRXCHG2ST64_RTN_B64,"DS_WRXCHG2ST64_RTN_B64"}, // 111 + {amdgpu_gfx940_op_DS_CMPST_RTN_B64,"DS_CMPST_RTN_B64"}, // 112 + {amdgpu_gfx940_op_DS_CMPST_RTN_F64,"DS_CMPST_RTN_F64"}, // 113 + {amdgpu_gfx940_op_DS_MIN_RTN_F64,"DS_MIN_RTN_F64"}, // 114 + {amdgpu_gfx940_op_DS_MAX_RTN_F64,"DS_MAX_RTN_F64"}, // 115 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 116 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 117 + {amdgpu_gfx940_op_DS_READ_B64,"DS_READ_B64"}, // 118 + {amdgpu_gfx940_op_DS_READ2_B64,"DS_READ2_B64"}, // 119 + {amdgpu_gfx940_op_DS_READ2ST64_B64,"DS_READ2ST64_B64"}, // 120 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 121 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 122 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 123 + {amdgpu_gfx940_op_DS_ADD_RTN_F64,"DS_ADD_RTN_F64"}, // 124 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 125 + {amdgpu_gfx940_op_DS_CONDXCHG32_RTN_B64,"DS_CONDXCHG32_RTN_B64"}, // 126 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 127 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 128 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 129 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 130 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 131 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 132 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 133 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 134 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 135 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 136 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 137 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 138 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 139 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 140 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 141 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 142 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 143 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 144 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 145 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 146 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 147 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 148 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 149 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 150 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 151 + {amdgpu_gfx940_op_DS_GWS_SEMA_RELEASE_ALL,"DS_GWS_SEMA_RELEASE_ALL"}, // 152 + {amdgpu_gfx940_op_DS_GWS_INIT,"DS_GWS_INIT"}, // 153 + {amdgpu_gfx940_op_DS_GWS_SEMA_V,"DS_GWS_SEMA_V"}, // 154 + {amdgpu_gfx940_op_DS_GWS_SEMA_BR,"DS_GWS_SEMA_BR"}, // 155 + {amdgpu_gfx940_op_DS_GWS_SEMA_P,"DS_GWS_SEMA_P"}, // 156 + {amdgpu_gfx940_op_DS_GWS_BARRIER,"DS_GWS_BARRIER"}, // 157 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 158 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 159 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 160 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 161 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 162 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 163 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 164 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 165 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 166 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 167 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 168 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 169 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 170 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 171 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 172 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 173 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 174 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 175 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 176 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 177 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 178 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 179 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 180 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 181 + {amdgpu_gfx940_op_DS_READ_ADDTID_B32,"DS_READ_ADDTID_B32"}, // 182 + {amdgpu_gfx940_op_DS_PK_ADD_RTN_F16,"DS_PK_ADD_RTN_F16"}, // 183 + {amdgpu_gfx940_op_DS_PK_ADD_RTN_BF16,"DS_PK_ADD_RTN_BF16"}, // 184 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 185 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 186 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 187 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 188 + {amdgpu_gfx940_op_DS_CONSUME,"DS_CONSUME"}, // 189 + {amdgpu_gfx940_op_DS_APPEND,"DS_APPEND"}, // 190 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 191 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 192 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 193 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 194 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 195 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 196 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 197 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 198 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 199 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 200 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 201 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 202 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 203 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 204 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 205 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 206 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 207 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 208 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 209 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 210 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 211 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 212 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 213 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 214 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 215 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 216 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 217 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 218 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 219 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 220 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 221 + {amdgpu_gfx940_op_DS_WRITE_B96,"DS_WRITE_B96"}, // 222 + {amdgpu_gfx940_op_DS_WRITE_B128,"DS_WRITE_B128"}, // 223 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 224 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 225 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 226 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 227 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 228 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 229 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 230 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 231 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 232 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 233 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 234 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 235 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 236 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 237 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 238 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 239 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 240 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 241 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 242 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 243 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 244 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 245 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 246 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 247 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 248 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 249 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 250 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 251 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 252 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 253 + {amdgpu_gfx940_op_DS_READ_B96,"DS_READ_B96"}, // 254 + {amdgpu_gfx940_op_DS_READ_B128,"DS_READ_B128"}, // 255 + }; // end ENC_DS_insn_table + const amdgpu_gfx940_insn_entry ENC_FLAT_insn_table[109] = + { + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 0 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 1 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 2 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 3 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 4 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 5 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 6 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 7 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 8 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 9 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 10 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 11 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 12 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 13 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 14 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 15 + {amdgpu_gfx940_op_FLAT_LOAD_UBYTE,"FLAT_LOAD_UBYTE"}, // 16 + {amdgpu_gfx940_op_FLAT_LOAD_SBYTE,"FLAT_LOAD_SBYTE"}, // 17 + {amdgpu_gfx940_op_FLAT_LOAD_USHORT,"FLAT_LOAD_USHORT"}, // 18 + {amdgpu_gfx940_op_FLAT_LOAD_SSHORT,"FLAT_LOAD_SSHORT"}, // 19 + {amdgpu_gfx940_op_FLAT_LOAD_DWORD,"FLAT_LOAD_DWORD"}, // 20 + {amdgpu_gfx940_op_FLAT_LOAD_DWORDX2,"FLAT_LOAD_DWORDX2"}, // 21 + {amdgpu_gfx940_op_FLAT_LOAD_DWORDX3,"FLAT_LOAD_DWORDX3"}, // 22 + {amdgpu_gfx940_op_FLAT_LOAD_DWORDX4,"FLAT_LOAD_DWORDX4"}, // 23 + {amdgpu_gfx940_op_FLAT_STORE_BYTE,"FLAT_STORE_BYTE"}, // 24 + {amdgpu_gfx940_op_FLAT_STORE_BYTE_D16_HI,"FLAT_STORE_BYTE_D16_HI"}, // 25 + {amdgpu_gfx940_op_FLAT_STORE_SHORT,"FLAT_STORE_SHORT"}, // 26 + {amdgpu_gfx940_op_FLAT_STORE_SHORT_D16_HI,"FLAT_STORE_SHORT_D16_HI"}, // 27 + {amdgpu_gfx940_op_FLAT_STORE_DWORD,"FLAT_STORE_DWORD"}, // 28 + {amdgpu_gfx940_op_FLAT_STORE_DWORDX2,"FLAT_STORE_DWORDX2"}, // 29 + {amdgpu_gfx940_op_FLAT_STORE_DWORDX3,"FLAT_STORE_DWORDX3"}, // 30 + {amdgpu_gfx940_op_FLAT_STORE_DWORDX4,"FLAT_STORE_DWORDX4"}, // 31 + {amdgpu_gfx940_op_FLAT_LOAD_UBYTE_D16,"FLAT_LOAD_UBYTE_D16"}, // 32 + {amdgpu_gfx940_op_FLAT_LOAD_UBYTE_D16_HI,"FLAT_LOAD_UBYTE_D16_HI"}, // 33 + {amdgpu_gfx940_op_FLAT_LOAD_SBYTE_D16,"FLAT_LOAD_SBYTE_D16"}, // 34 + {amdgpu_gfx940_op_FLAT_LOAD_SBYTE_D16_HI,"FLAT_LOAD_SBYTE_D16_HI"}, // 35 + {amdgpu_gfx940_op_FLAT_LOAD_SHORT_D16,"FLAT_LOAD_SHORT_D16"}, // 36 + {amdgpu_gfx940_op_FLAT_LOAD_SHORT_D16_HI,"FLAT_LOAD_SHORT_D16_HI"}, // 37 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 38 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 39 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 40 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 41 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 42 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 43 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 44 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 45 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 46 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 47 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 48 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 49 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 50 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 51 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 52 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 53 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 54 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 55 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 56 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 57 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 58 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 59 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 60 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 61 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 62 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 63 + {amdgpu_gfx940_op_FLAT_ATOMIC_SWAP,"FLAT_ATOMIC_SWAP"}, // 64 + {amdgpu_gfx940_op_FLAT_ATOMIC_CMPSWAP,"FLAT_ATOMIC_CMPSWAP"}, // 65 + {amdgpu_gfx940_op_FLAT_ATOMIC_ADD,"FLAT_ATOMIC_ADD"}, // 66 + {amdgpu_gfx940_op_FLAT_ATOMIC_SUB,"FLAT_ATOMIC_SUB"}, // 67 + {amdgpu_gfx940_op_FLAT_ATOMIC_SMIN,"FLAT_ATOMIC_SMIN"}, // 68 + {amdgpu_gfx940_op_FLAT_ATOMIC_UMIN,"FLAT_ATOMIC_UMIN"}, // 69 + {amdgpu_gfx940_op_FLAT_ATOMIC_SMAX,"FLAT_ATOMIC_SMAX"}, // 70 + {amdgpu_gfx940_op_FLAT_ATOMIC_UMAX,"FLAT_ATOMIC_UMAX"}, // 71 + {amdgpu_gfx940_op_FLAT_ATOMIC_AND,"FLAT_ATOMIC_AND"}, // 72 + {amdgpu_gfx940_op_FLAT_ATOMIC_OR,"FLAT_ATOMIC_OR"}, // 73 + {amdgpu_gfx940_op_FLAT_ATOMIC_XOR,"FLAT_ATOMIC_XOR"}, // 74 + {amdgpu_gfx940_op_FLAT_ATOMIC_INC,"FLAT_ATOMIC_INC"}, // 75 + {amdgpu_gfx940_op_FLAT_ATOMIC_DEC,"FLAT_ATOMIC_DEC"}, // 76 + {amdgpu_gfx940_op_FLAT_ATOMIC_ADD_F32,"FLAT_ATOMIC_ADD_F32"}, // 77 + {amdgpu_gfx940_op_FLAT_ATOMIC_PK_ADD_F16,"FLAT_ATOMIC_PK_ADD_F16"}, // 78 + {amdgpu_gfx940_op_FLAT_ATOMIC_ADD_F64,"FLAT_ATOMIC_ADD_F64"}, // 79 + {amdgpu_gfx940_op_FLAT_ATOMIC_MIN_F64,"FLAT_ATOMIC_MIN_F64"}, // 80 + {amdgpu_gfx940_op_FLAT_ATOMIC_MAX_F64,"FLAT_ATOMIC_MAX_F64"}, // 81 + {amdgpu_gfx940_op_FLAT_ATOMIC_PK_ADD_BF16,"FLAT_ATOMIC_PK_ADD_BF16"}, // 82 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 83 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 84 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 85 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 86 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 87 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 88 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 89 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 90 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 91 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 92 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 93 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 94 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 95 + {amdgpu_gfx940_op_FLAT_ATOMIC_SWAP_X2,"FLAT_ATOMIC_SWAP_X2"}, // 96 + {amdgpu_gfx940_op_FLAT_ATOMIC_CMPSWAP_X2,"FLAT_ATOMIC_CMPSWAP_X2"}, // 97 + {amdgpu_gfx940_op_FLAT_ATOMIC_ADD_X2,"FLAT_ATOMIC_ADD_X2"}, // 98 + {amdgpu_gfx940_op_FLAT_ATOMIC_SUB_X2,"FLAT_ATOMIC_SUB_X2"}, // 99 + {amdgpu_gfx940_op_FLAT_ATOMIC_SMIN_X2,"FLAT_ATOMIC_SMIN_X2"}, // 100 + {amdgpu_gfx940_op_FLAT_ATOMIC_UMIN_X2,"FLAT_ATOMIC_UMIN_X2"}, // 101 + {amdgpu_gfx940_op_FLAT_ATOMIC_SMAX_X2,"FLAT_ATOMIC_SMAX_X2"}, // 102 + {amdgpu_gfx940_op_FLAT_ATOMIC_UMAX_X2,"FLAT_ATOMIC_UMAX_X2"}, // 103 + {amdgpu_gfx940_op_FLAT_ATOMIC_AND_X2,"FLAT_ATOMIC_AND_X2"}, // 104 + {amdgpu_gfx940_op_FLAT_ATOMIC_OR_X2,"FLAT_ATOMIC_OR_X2"}, // 105 + {amdgpu_gfx940_op_FLAT_ATOMIC_XOR_X2,"FLAT_ATOMIC_XOR_X2"}, // 106 + {amdgpu_gfx940_op_FLAT_ATOMIC_INC_X2,"FLAT_ATOMIC_INC_X2"}, // 107 + {amdgpu_gfx940_op_FLAT_ATOMIC_DEC_X2,"FLAT_ATOMIC_DEC_X2"}, // 108 + }; // end ENC_FLAT_insn_table + const amdgpu_gfx940_insn_entry ENC_FLAT_GLBL_insn_table[109] = + { + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 0 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 1 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 2 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 3 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 4 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 5 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 6 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 7 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 8 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 9 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 10 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 11 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 12 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 13 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 14 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 15 + {amdgpu_gfx940_op_GLOBAL_LOAD_UBYTE,"GLOBAL_LOAD_UBYTE"}, // 16 + {amdgpu_gfx940_op_GLOBAL_LOAD_SBYTE,"GLOBAL_LOAD_SBYTE"}, // 17 + {amdgpu_gfx940_op_GLOBAL_LOAD_USHORT,"GLOBAL_LOAD_USHORT"}, // 18 + {amdgpu_gfx940_op_GLOBAL_LOAD_SSHORT,"GLOBAL_LOAD_SSHORT"}, // 19 + {amdgpu_gfx940_op_GLOBAL_LOAD_DWORD,"GLOBAL_LOAD_DWORD"}, // 20 + {amdgpu_gfx940_op_GLOBAL_LOAD_DWORDX2,"GLOBAL_LOAD_DWORDX2"}, // 21 + {amdgpu_gfx940_op_GLOBAL_LOAD_DWORDX3,"GLOBAL_LOAD_DWORDX3"}, // 22 + {amdgpu_gfx940_op_GLOBAL_LOAD_DWORDX4,"GLOBAL_LOAD_DWORDX4"}, // 23 + {amdgpu_gfx940_op_GLOBAL_STORE_BYTE,"GLOBAL_STORE_BYTE"}, // 24 + {amdgpu_gfx940_op_GLOBAL_STORE_BYTE_D16_HI,"GLOBAL_STORE_BYTE_D16_HI"}, // 25 + {amdgpu_gfx940_op_GLOBAL_STORE_SHORT,"GLOBAL_STORE_SHORT"}, // 26 + {amdgpu_gfx940_op_GLOBAL_STORE_SHORT_D16_HI,"GLOBAL_STORE_SHORT_D16_HI"}, // 27 + {amdgpu_gfx940_op_GLOBAL_STORE_DWORD,"GLOBAL_STORE_DWORD"}, // 28 + {amdgpu_gfx940_op_GLOBAL_STORE_DWORDX2,"GLOBAL_STORE_DWORDX2"}, // 29 + {amdgpu_gfx940_op_GLOBAL_STORE_DWORDX3,"GLOBAL_STORE_DWORDX3"}, // 30 + {amdgpu_gfx940_op_GLOBAL_STORE_DWORDX4,"GLOBAL_STORE_DWORDX4"}, // 31 + {amdgpu_gfx940_op_GLOBAL_LOAD_UBYTE_D16,"GLOBAL_LOAD_UBYTE_D16"}, // 32 + {amdgpu_gfx940_op_GLOBAL_LOAD_UBYTE_D16_HI,"GLOBAL_LOAD_UBYTE_D16_HI"}, // 33 + {amdgpu_gfx940_op_GLOBAL_LOAD_SBYTE_D16,"GLOBAL_LOAD_SBYTE_D16"}, // 34 + {amdgpu_gfx940_op_GLOBAL_LOAD_SBYTE_D16_HI,"GLOBAL_LOAD_SBYTE_D16_HI"}, // 35 + {amdgpu_gfx940_op_GLOBAL_LOAD_SHORT_D16,"GLOBAL_LOAD_SHORT_D16"}, // 36 + {amdgpu_gfx940_op_GLOBAL_LOAD_SHORT_D16_HI,"GLOBAL_LOAD_SHORT_D16_HI"}, // 37 + {amdgpu_gfx940_op_GLOBAL_LOAD_LDS_UBYTE,"GLOBAL_LOAD_LDS_UBYTE"}, // 38 + {amdgpu_gfx940_op_GLOBAL_LOAD_LDS_SBYTE,"GLOBAL_LOAD_LDS_SBYTE"}, // 39 + {amdgpu_gfx940_op_GLOBAL_LOAD_LDS_USHORT,"GLOBAL_LOAD_LDS_USHORT"}, // 40 + {amdgpu_gfx940_op_GLOBAL_LOAD_LDS_SSHORT,"GLOBAL_LOAD_LDS_SSHORT"}, // 41 + {amdgpu_gfx940_op_GLOBAL_LOAD_LDS_DWORD,"GLOBAL_LOAD_LDS_DWORD"}, // 42 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 43 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 44 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 45 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 46 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 47 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 48 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 49 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 50 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 51 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 52 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 53 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 54 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 55 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 56 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 57 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 58 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 59 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 60 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 61 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 62 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 63 + {amdgpu_gfx940_op_GLOBAL_ATOMIC_SWAP,"GLOBAL_ATOMIC_SWAP"}, // 64 + {amdgpu_gfx940_op_GLOBAL_ATOMIC_CMPSWAP,"GLOBAL_ATOMIC_CMPSWAP"}, // 65 + {amdgpu_gfx940_op_GLOBAL_ATOMIC_ADD,"GLOBAL_ATOMIC_ADD"}, // 66 + {amdgpu_gfx940_op_GLOBAL_ATOMIC_SUB,"GLOBAL_ATOMIC_SUB"}, // 67 + {amdgpu_gfx940_op_GLOBAL_ATOMIC_SMIN,"GLOBAL_ATOMIC_SMIN"}, // 68 + {amdgpu_gfx940_op_GLOBAL_ATOMIC_UMIN,"GLOBAL_ATOMIC_UMIN"}, // 69 + {amdgpu_gfx940_op_GLOBAL_ATOMIC_SMAX,"GLOBAL_ATOMIC_SMAX"}, // 70 + {amdgpu_gfx940_op_GLOBAL_ATOMIC_UMAX,"GLOBAL_ATOMIC_UMAX"}, // 71 + {amdgpu_gfx940_op_GLOBAL_ATOMIC_AND,"GLOBAL_ATOMIC_AND"}, // 72 + {amdgpu_gfx940_op_GLOBAL_ATOMIC_OR,"GLOBAL_ATOMIC_OR"}, // 73 + {amdgpu_gfx940_op_GLOBAL_ATOMIC_XOR,"GLOBAL_ATOMIC_XOR"}, // 74 + {amdgpu_gfx940_op_GLOBAL_ATOMIC_INC,"GLOBAL_ATOMIC_INC"}, // 75 + {amdgpu_gfx940_op_GLOBAL_ATOMIC_DEC,"GLOBAL_ATOMIC_DEC"}, // 76 + {amdgpu_gfx940_op_GLOBAL_ATOMIC_ADD_F32,"GLOBAL_ATOMIC_ADD_F32"}, // 77 + {amdgpu_gfx940_op_GLOBAL_ATOMIC_PK_ADD_F16,"GLOBAL_ATOMIC_PK_ADD_F16"}, // 78 + {amdgpu_gfx940_op_GLOBAL_ATOMIC_ADD_F64,"GLOBAL_ATOMIC_ADD_F64"}, // 79 + {amdgpu_gfx940_op_GLOBAL_ATOMIC_MIN_F64,"GLOBAL_ATOMIC_MIN_F64"}, // 80 + {amdgpu_gfx940_op_GLOBAL_ATOMIC_MAX_F64,"GLOBAL_ATOMIC_MAX_F64"}, // 81 + {amdgpu_gfx940_op_GLOBAL_ATOMIC_PK_ADD_BF16,"GLOBAL_ATOMIC_PK_ADD_BF16"}, // 82 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 83 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 84 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 85 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 86 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 87 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 88 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 89 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 90 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 91 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 92 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 93 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 94 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 95 + {amdgpu_gfx940_op_GLOBAL_ATOMIC_SWAP_X2,"GLOBAL_ATOMIC_SWAP_X2"}, // 96 + {amdgpu_gfx940_op_GLOBAL_ATOMIC_CMPSWAP_X2,"GLOBAL_ATOMIC_CMPSWAP_X2"}, // 97 + {amdgpu_gfx940_op_GLOBAL_ATOMIC_ADD_X2,"GLOBAL_ATOMIC_ADD_X2"}, // 98 + {amdgpu_gfx940_op_GLOBAL_ATOMIC_SUB_X2,"GLOBAL_ATOMIC_SUB_X2"}, // 99 + {amdgpu_gfx940_op_GLOBAL_ATOMIC_SMIN_X2,"GLOBAL_ATOMIC_SMIN_X2"}, // 100 + {amdgpu_gfx940_op_GLOBAL_ATOMIC_UMIN_X2,"GLOBAL_ATOMIC_UMIN_X2"}, // 101 + {amdgpu_gfx940_op_GLOBAL_ATOMIC_SMAX_X2,"GLOBAL_ATOMIC_SMAX_X2"}, // 102 + {amdgpu_gfx940_op_GLOBAL_ATOMIC_UMAX_X2,"GLOBAL_ATOMIC_UMAX_X2"}, // 103 + {amdgpu_gfx940_op_GLOBAL_ATOMIC_AND_X2,"GLOBAL_ATOMIC_AND_X2"}, // 104 + {amdgpu_gfx940_op_GLOBAL_ATOMIC_OR_X2,"GLOBAL_ATOMIC_OR_X2"}, // 105 + {amdgpu_gfx940_op_GLOBAL_ATOMIC_XOR_X2,"GLOBAL_ATOMIC_XOR_X2"}, // 106 + {amdgpu_gfx940_op_GLOBAL_ATOMIC_INC_X2,"GLOBAL_ATOMIC_INC_X2"}, // 107 + {amdgpu_gfx940_op_GLOBAL_ATOMIC_DEC_X2,"GLOBAL_ATOMIC_DEC_X2"}, // 108 + }; // end ENC_FLAT_GLBL_insn_table + const amdgpu_gfx940_insn_entry ENC_FLAT_SCRATCH_insn_table[43] = + { + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 0 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 1 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 2 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 3 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 4 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 5 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 6 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 7 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 8 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 9 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 10 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 11 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 12 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 13 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 14 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 15 + {amdgpu_gfx940_op_SCRATCH_LOAD_UBYTE,"SCRATCH_LOAD_UBYTE"}, // 16 + {amdgpu_gfx940_op_SCRATCH_LOAD_SBYTE,"SCRATCH_LOAD_SBYTE"}, // 17 + {amdgpu_gfx940_op_SCRATCH_LOAD_USHORT,"SCRATCH_LOAD_USHORT"}, // 18 + {amdgpu_gfx940_op_SCRATCH_LOAD_SSHORT,"SCRATCH_LOAD_SSHORT"}, // 19 + {amdgpu_gfx940_op_SCRATCH_LOAD_DWORD,"SCRATCH_LOAD_DWORD"}, // 20 + {amdgpu_gfx940_op_SCRATCH_LOAD_DWORDX2,"SCRATCH_LOAD_DWORDX2"}, // 21 + {amdgpu_gfx940_op_SCRATCH_LOAD_DWORDX3,"SCRATCH_LOAD_DWORDX3"}, // 22 + {amdgpu_gfx940_op_SCRATCH_LOAD_DWORDX4,"SCRATCH_LOAD_DWORDX4"}, // 23 + {amdgpu_gfx940_op_SCRATCH_STORE_BYTE,"SCRATCH_STORE_BYTE"}, // 24 + {amdgpu_gfx940_op_SCRATCH_STORE_BYTE_D16_HI,"SCRATCH_STORE_BYTE_D16_HI"}, // 25 + {amdgpu_gfx940_op_SCRATCH_STORE_SHORT,"SCRATCH_STORE_SHORT"}, // 26 + {amdgpu_gfx940_op_SCRATCH_STORE_SHORT_D16_HI,"SCRATCH_STORE_SHORT_D16_HI"}, // 27 + {amdgpu_gfx940_op_SCRATCH_STORE_DWORD,"SCRATCH_STORE_DWORD"}, // 28 + {amdgpu_gfx940_op_SCRATCH_STORE_DWORDX2,"SCRATCH_STORE_DWORDX2"}, // 29 + {amdgpu_gfx940_op_SCRATCH_STORE_DWORDX3,"SCRATCH_STORE_DWORDX3"}, // 30 + {amdgpu_gfx940_op_SCRATCH_STORE_DWORDX4,"SCRATCH_STORE_DWORDX4"}, // 31 + {amdgpu_gfx940_op_SCRATCH_LOAD_UBYTE_D16,"SCRATCH_LOAD_UBYTE_D16"}, // 32 + {amdgpu_gfx940_op_SCRATCH_LOAD_UBYTE_D16_HI,"SCRATCH_LOAD_UBYTE_D16_HI"}, // 33 + {amdgpu_gfx940_op_SCRATCH_LOAD_SBYTE_D16,"SCRATCH_LOAD_SBYTE_D16"}, // 34 + {amdgpu_gfx940_op_SCRATCH_LOAD_SBYTE_D16_HI,"SCRATCH_LOAD_SBYTE_D16_HI"}, // 35 + {amdgpu_gfx940_op_SCRATCH_LOAD_SHORT_D16,"SCRATCH_LOAD_SHORT_D16"}, // 36 + {amdgpu_gfx940_op_SCRATCH_LOAD_SHORT_D16_HI,"SCRATCH_LOAD_SHORT_D16_HI"}, // 37 + {amdgpu_gfx940_op_SCRATCH_LOAD_LDS_UBYTE,"SCRATCH_LOAD_LDS_UBYTE"}, // 38 + {amdgpu_gfx940_op_SCRATCH_LOAD_LDS_SBYTE,"SCRATCH_LOAD_LDS_SBYTE"}, // 39 + {amdgpu_gfx940_op_SCRATCH_LOAD_LDS_USHORT,"SCRATCH_LOAD_LDS_USHORT"}, // 40 + {amdgpu_gfx940_op_SCRATCH_LOAD_LDS_SSHORT,"SCRATCH_LOAD_LDS_SSHORT"}, // 41 + {amdgpu_gfx940_op_SCRATCH_LOAD_LDS_DWORD,"SCRATCH_LOAD_LDS_DWORD"}, // 42 + }; // end ENC_FLAT_SCRATCH_insn_table + const amdgpu_gfx940_insn_entry ENC_MTBUF_insn_table[16] = + { + {amdgpu_gfx940_op_TBUFFER_LOAD_FORMAT_X,"TBUFFER_LOAD_FORMAT_X"}, // 0 + {amdgpu_gfx940_op_TBUFFER_LOAD_FORMAT_XY,"TBUFFER_LOAD_FORMAT_XY"}, // 1 + {amdgpu_gfx940_op_TBUFFER_LOAD_FORMAT_XYZ,"TBUFFER_LOAD_FORMAT_XYZ"}, // 2 + {amdgpu_gfx940_op_TBUFFER_LOAD_FORMAT_XYZW,"TBUFFER_LOAD_FORMAT_XYZW"}, // 3 + {amdgpu_gfx940_op_TBUFFER_STORE_FORMAT_X,"TBUFFER_STORE_FORMAT_X"}, // 4 + {amdgpu_gfx940_op_TBUFFER_STORE_FORMAT_XY,"TBUFFER_STORE_FORMAT_XY"}, // 5 + {amdgpu_gfx940_op_TBUFFER_STORE_FORMAT_XYZ,"TBUFFER_STORE_FORMAT_XYZ"}, // 6 + {amdgpu_gfx940_op_TBUFFER_STORE_FORMAT_XYZW,"TBUFFER_STORE_FORMAT_XYZW"}, // 7 + {amdgpu_gfx940_op_TBUFFER_LOAD_FORMAT_D16_X,"TBUFFER_LOAD_FORMAT_D16_X"}, // 8 + {amdgpu_gfx940_op_TBUFFER_LOAD_FORMAT_D16_XY,"TBUFFER_LOAD_FORMAT_D16_XY"}, // 9 + {amdgpu_gfx940_op_TBUFFER_LOAD_FORMAT_D16_XYZ,"TBUFFER_LOAD_FORMAT_D16_XYZ"}, // 10 + {amdgpu_gfx940_op_TBUFFER_LOAD_FORMAT_D16_XYZW,"TBUFFER_LOAD_FORMAT_D16_XYZW"}, // 11 + {amdgpu_gfx940_op_TBUFFER_STORE_FORMAT_D16_X,"TBUFFER_STORE_FORMAT_D16_X"}, // 12 + {amdgpu_gfx940_op_TBUFFER_STORE_FORMAT_D16_XY,"TBUFFER_STORE_FORMAT_D16_XY"}, // 13 + {amdgpu_gfx940_op_TBUFFER_STORE_FORMAT_D16_XYZ,"TBUFFER_STORE_FORMAT_D16_XYZ"}, // 14 + {amdgpu_gfx940_op_TBUFFER_STORE_FORMAT_D16_XYZW,"TBUFFER_STORE_FORMAT_D16_XYZW"}, // 15 + }; // end ENC_MTBUF_insn_table + const amdgpu_gfx940_insn_entry ENC_MUBUF_insn_table[109] = + { + {amdgpu_gfx940_op_BUFFER_LOAD_FORMAT_X,"BUFFER_LOAD_FORMAT_X"}, // 0 + {amdgpu_gfx940_op_BUFFER_LOAD_FORMAT_XY,"BUFFER_LOAD_FORMAT_XY"}, // 1 + {amdgpu_gfx940_op_BUFFER_LOAD_FORMAT_XYZ,"BUFFER_LOAD_FORMAT_XYZ"}, // 2 + {amdgpu_gfx940_op_BUFFER_LOAD_FORMAT_XYZW,"BUFFER_LOAD_FORMAT_XYZW"}, // 3 + {amdgpu_gfx940_op_BUFFER_STORE_FORMAT_X,"BUFFER_STORE_FORMAT_X"}, // 4 + {amdgpu_gfx940_op_BUFFER_STORE_FORMAT_XY,"BUFFER_STORE_FORMAT_XY"}, // 5 + {amdgpu_gfx940_op_BUFFER_STORE_FORMAT_XYZ,"BUFFER_STORE_FORMAT_XYZ"}, // 6 + {amdgpu_gfx940_op_BUFFER_STORE_FORMAT_XYZW,"BUFFER_STORE_FORMAT_XYZW"}, // 7 + {amdgpu_gfx940_op_BUFFER_LOAD_FORMAT_D16_X,"BUFFER_LOAD_FORMAT_D16_X"}, // 8 + {amdgpu_gfx940_op_BUFFER_LOAD_FORMAT_D16_XY,"BUFFER_LOAD_FORMAT_D16_XY"}, // 9 + {amdgpu_gfx940_op_BUFFER_LOAD_FORMAT_D16_XYZ,"BUFFER_LOAD_FORMAT_D16_XYZ"}, // 10 + {amdgpu_gfx940_op_BUFFER_LOAD_FORMAT_D16_XYZW,"BUFFER_LOAD_FORMAT_D16_XYZW"}, // 11 + {amdgpu_gfx940_op_BUFFER_STORE_FORMAT_D16_X,"BUFFER_STORE_FORMAT_D16_X"}, // 12 + {amdgpu_gfx940_op_BUFFER_STORE_FORMAT_D16_XY,"BUFFER_STORE_FORMAT_D16_XY"}, // 13 + {amdgpu_gfx940_op_BUFFER_STORE_FORMAT_D16_XYZ,"BUFFER_STORE_FORMAT_D16_XYZ"}, // 14 + {amdgpu_gfx940_op_BUFFER_STORE_FORMAT_D16_XYZW,"BUFFER_STORE_FORMAT_D16_XYZW"}, // 15 + {amdgpu_gfx940_op_BUFFER_LOAD_UBYTE,"BUFFER_LOAD_UBYTE"}, // 16 + {amdgpu_gfx940_op_BUFFER_LOAD_SBYTE,"BUFFER_LOAD_SBYTE"}, // 17 + {amdgpu_gfx940_op_BUFFER_LOAD_USHORT,"BUFFER_LOAD_USHORT"}, // 18 + {amdgpu_gfx940_op_BUFFER_LOAD_SSHORT,"BUFFER_LOAD_SSHORT"}, // 19 + {amdgpu_gfx940_op_BUFFER_LOAD_DWORD,"BUFFER_LOAD_DWORD"}, // 20 + {amdgpu_gfx940_op_BUFFER_LOAD_DWORDX2,"BUFFER_LOAD_DWORDX2"}, // 21 + {amdgpu_gfx940_op_BUFFER_LOAD_DWORDX3,"BUFFER_LOAD_DWORDX3"}, // 22 + {amdgpu_gfx940_op_BUFFER_LOAD_DWORDX4,"BUFFER_LOAD_DWORDX4"}, // 23 + {amdgpu_gfx940_op_BUFFER_STORE_BYTE,"BUFFER_STORE_BYTE"}, // 24 + {amdgpu_gfx940_op_BUFFER_STORE_BYTE_D16_HI,"BUFFER_STORE_BYTE_D16_HI"}, // 25 + {amdgpu_gfx940_op_BUFFER_STORE_SHORT,"BUFFER_STORE_SHORT"}, // 26 + {amdgpu_gfx940_op_BUFFER_STORE_SHORT_D16_HI,"BUFFER_STORE_SHORT_D16_HI"}, // 27 + {amdgpu_gfx940_op_BUFFER_STORE_DWORD,"BUFFER_STORE_DWORD"}, // 28 + {amdgpu_gfx940_op_BUFFER_STORE_DWORDX2,"BUFFER_STORE_DWORDX2"}, // 29 + {amdgpu_gfx940_op_BUFFER_STORE_DWORDX3,"BUFFER_STORE_DWORDX3"}, // 30 + {amdgpu_gfx940_op_BUFFER_STORE_DWORDX4,"BUFFER_STORE_DWORDX4"}, // 31 + {amdgpu_gfx940_op_BUFFER_LOAD_UBYTE_D16,"BUFFER_LOAD_UBYTE_D16"}, // 32 + {amdgpu_gfx940_op_BUFFER_LOAD_UBYTE_D16_HI,"BUFFER_LOAD_UBYTE_D16_HI"}, // 33 + {amdgpu_gfx940_op_BUFFER_LOAD_SBYTE_D16,"BUFFER_LOAD_SBYTE_D16"}, // 34 + {amdgpu_gfx940_op_BUFFER_LOAD_SBYTE_D16_HI,"BUFFER_LOAD_SBYTE_D16_HI"}, // 35 + {amdgpu_gfx940_op_BUFFER_LOAD_SHORT_D16,"BUFFER_LOAD_SHORT_D16"}, // 36 + {amdgpu_gfx940_op_BUFFER_LOAD_SHORT_D16_HI,"BUFFER_LOAD_SHORT_D16_HI"}, // 37 + {amdgpu_gfx940_op_BUFFER_LOAD_FORMAT_D16_HI_X,"BUFFER_LOAD_FORMAT_D16_HI_X"}, // 38 + {amdgpu_gfx940_op_BUFFER_STORE_FORMAT_D16_HI_X,"BUFFER_STORE_FORMAT_D16_HI_X"}, // 39 + {amdgpu_gfx940_op_BUFFER_WBL2,"BUFFER_WBL2"}, // 40 + {amdgpu_gfx940_op_BUFFER_INV,"BUFFER_INV"}, // 41 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 42 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 43 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 44 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 45 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 46 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 47 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 48 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 49 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 50 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 51 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 52 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 53 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 54 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 55 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 56 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 57 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 58 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 59 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 60 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 61 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 62 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 63 + {amdgpu_gfx940_op_BUFFER_ATOMIC_SWAP,"BUFFER_ATOMIC_SWAP"}, // 64 + {amdgpu_gfx940_op_BUFFER_ATOMIC_CMPSWAP,"BUFFER_ATOMIC_CMPSWAP"}, // 65 + {amdgpu_gfx940_op_BUFFER_ATOMIC_ADD,"BUFFER_ATOMIC_ADD"}, // 66 + {amdgpu_gfx940_op_BUFFER_ATOMIC_SUB,"BUFFER_ATOMIC_SUB"}, // 67 + {amdgpu_gfx940_op_BUFFER_ATOMIC_SMIN,"BUFFER_ATOMIC_SMIN"}, // 68 + {amdgpu_gfx940_op_BUFFER_ATOMIC_UMIN,"BUFFER_ATOMIC_UMIN"}, // 69 + {amdgpu_gfx940_op_BUFFER_ATOMIC_SMAX,"BUFFER_ATOMIC_SMAX"}, // 70 + {amdgpu_gfx940_op_BUFFER_ATOMIC_UMAX,"BUFFER_ATOMIC_UMAX"}, // 71 + {amdgpu_gfx940_op_BUFFER_ATOMIC_AND,"BUFFER_ATOMIC_AND"}, // 72 + {amdgpu_gfx940_op_BUFFER_ATOMIC_OR,"BUFFER_ATOMIC_OR"}, // 73 + {amdgpu_gfx940_op_BUFFER_ATOMIC_XOR,"BUFFER_ATOMIC_XOR"}, // 74 + {amdgpu_gfx940_op_BUFFER_ATOMIC_INC,"BUFFER_ATOMIC_INC"}, // 75 + {amdgpu_gfx940_op_BUFFER_ATOMIC_DEC,"BUFFER_ATOMIC_DEC"}, // 76 + {amdgpu_gfx940_op_BUFFER_ATOMIC_ADD_F32,"BUFFER_ATOMIC_ADD_F32"}, // 77 + {amdgpu_gfx940_op_BUFFER_ATOMIC_PK_ADD_F16,"BUFFER_ATOMIC_PK_ADD_F16"}, // 78 + {amdgpu_gfx940_op_BUFFER_ATOMIC_ADD_F64,"BUFFER_ATOMIC_ADD_F64"}, // 79 + {amdgpu_gfx940_op_BUFFER_ATOMIC_MIN_F64,"BUFFER_ATOMIC_MIN_F64"}, // 80 + {amdgpu_gfx940_op_BUFFER_ATOMIC_MAX_F64,"BUFFER_ATOMIC_MAX_F64"}, // 81 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 82 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 83 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 84 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 85 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 86 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 87 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 88 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 89 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 90 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 91 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 92 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 93 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 94 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 95 + {amdgpu_gfx940_op_BUFFER_ATOMIC_SWAP_X2,"BUFFER_ATOMIC_SWAP_X2"}, // 96 + {amdgpu_gfx940_op_BUFFER_ATOMIC_CMPSWAP_X2,"BUFFER_ATOMIC_CMPSWAP_X2"}, // 97 + {amdgpu_gfx940_op_BUFFER_ATOMIC_ADD_X2,"BUFFER_ATOMIC_ADD_X2"}, // 98 + {amdgpu_gfx940_op_BUFFER_ATOMIC_SUB_X2,"BUFFER_ATOMIC_SUB_X2"}, // 99 + {amdgpu_gfx940_op_BUFFER_ATOMIC_SMIN_X2,"BUFFER_ATOMIC_SMIN_X2"}, // 100 + {amdgpu_gfx940_op_BUFFER_ATOMIC_UMIN_X2,"BUFFER_ATOMIC_UMIN_X2"}, // 101 + {amdgpu_gfx940_op_BUFFER_ATOMIC_SMAX_X2,"BUFFER_ATOMIC_SMAX_X2"}, // 102 + {amdgpu_gfx940_op_BUFFER_ATOMIC_UMAX_X2,"BUFFER_ATOMIC_UMAX_X2"}, // 103 + {amdgpu_gfx940_op_BUFFER_ATOMIC_AND_X2,"BUFFER_ATOMIC_AND_X2"}, // 104 + {amdgpu_gfx940_op_BUFFER_ATOMIC_OR_X2,"BUFFER_ATOMIC_OR_X2"}, // 105 + {amdgpu_gfx940_op_BUFFER_ATOMIC_XOR_X2,"BUFFER_ATOMIC_XOR_X2"}, // 106 + {amdgpu_gfx940_op_BUFFER_ATOMIC_INC_X2,"BUFFER_ATOMIC_INC_X2"}, // 107 + {amdgpu_gfx940_op_BUFFER_ATOMIC_DEC_X2,"BUFFER_ATOMIC_DEC_X2"}, // 108 + }; // end ENC_MUBUF_insn_table + const amdgpu_gfx940_insn_entry ENC_SMEM_insn_table[173] = + { + {amdgpu_gfx940_op_S_LOAD_DWORD,"S_LOAD_DWORD"}, // 0 + {amdgpu_gfx940_op_S_LOAD_DWORDX2,"S_LOAD_DWORDX2"}, // 1 + {amdgpu_gfx940_op_S_LOAD_DWORDX4,"S_LOAD_DWORDX4"}, // 2 + {amdgpu_gfx940_op_S_LOAD_DWORDX8,"S_LOAD_DWORDX8"}, // 3 + {amdgpu_gfx940_op_S_LOAD_DWORDX16,"S_LOAD_DWORDX16"}, // 4 + {amdgpu_gfx940_op_S_SCRATCH_LOAD_DWORD,"S_SCRATCH_LOAD_DWORD"}, // 5 + {amdgpu_gfx940_op_S_SCRATCH_LOAD_DWORDX2,"S_SCRATCH_LOAD_DWORDX2"}, // 6 + {amdgpu_gfx940_op_S_SCRATCH_LOAD_DWORDX4,"S_SCRATCH_LOAD_DWORDX4"}, // 7 + {amdgpu_gfx940_op_S_BUFFER_LOAD_DWORD,"S_BUFFER_LOAD_DWORD"}, // 8 + {amdgpu_gfx940_op_S_BUFFER_LOAD_DWORDX2,"S_BUFFER_LOAD_DWORDX2"}, // 9 + {amdgpu_gfx940_op_S_BUFFER_LOAD_DWORDX4,"S_BUFFER_LOAD_DWORDX4"}, // 10 + {amdgpu_gfx940_op_S_BUFFER_LOAD_DWORDX8,"S_BUFFER_LOAD_DWORDX8"}, // 11 + {amdgpu_gfx940_op_S_BUFFER_LOAD_DWORDX16,"S_BUFFER_LOAD_DWORDX16"}, // 12 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 13 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 14 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 15 + {amdgpu_gfx940_op_S_STORE_DWORD,"S_STORE_DWORD"}, // 16 + {amdgpu_gfx940_op_S_STORE_DWORDX2,"S_STORE_DWORDX2"}, // 17 + {amdgpu_gfx940_op_S_STORE_DWORDX4,"S_STORE_DWORDX4"}, // 18 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 19 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 20 + {amdgpu_gfx940_op_S_SCRATCH_STORE_DWORD,"S_SCRATCH_STORE_DWORD"}, // 21 + {amdgpu_gfx940_op_S_SCRATCH_STORE_DWORDX2,"S_SCRATCH_STORE_DWORDX2"}, // 22 + {amdgpu_gfx940_op_S_SCRATCH_STORE_DWORDX4,"S_SCRATCH_STORE_DWORDX4"}, // 23 + {amdgpu_gfx940_op_S_BUFFER_STORE_DWORD,"S_BUFFER_STORE_DWORD"}, // 24 + {amdgpu_gfx940_op_S_BUFFER_STORE_DWORDX2,"S_BUFFER_STORE_DWORDX2"}, // 25 + {amdgpu_gfx940_op_S_BUFFER_STORE_DWORDX4,"S_BUFFER_STORE_DWORDX4"}, // 26 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 27 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 28 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 29 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 30 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 31 + {amdgpu_gfx940_op_S_DCACHE_INV,"S_DCACHE_INV"}, // 32 + {amdgpu_gfx940_op_S_DCACHE_WB,"S_DCACHE_WB"}, // 33 + {amdgpu_gfx940_op_S_DCACHE_INV_VOL,"S_DCACHE_INV_VOL"}, // 34 + {amdgpu_gfx940_op_S_DCACHE_WB_VOL,"S_DCACHE_WB_VOL"}, // 35 + {amdgpu_gfx940_op_S_MEMTIME,"S_MEMTIME"}, // 36 + {amdgpu_gfx940_op_S_MEMREALTIME,"S_MEMREALTIME"}, // 37 + {amdgpu_gfx940_op_S_ATC_PROBE,"S_ATC_PROBE"}, // 38 + {amdgpu_gfx940_op_S_ATC_PROBE_BUFFER,"S_ATC_PROBE_BUFFER"}, // 39 + {amdgpu_gfx940_op_S_DCACHE_DISCARD,"S_DCACHE_DISCARD"}, // 40 + {amdgpu_gfx940_op_S_DCACHE_DISCARD_X2,"S_DCACHE_DISCARD_X2"}, // 41 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 42 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 43 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 44 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 45 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 46 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 47 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 48 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 49 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 50 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 51 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 52 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 53 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 54 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 55 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 56 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 57 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 58 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 59 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 60 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 61 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 62 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 63 + {amdgpu_gfx940_op_S_BUFFER_ATOMIC_SWAP,"S_BUFFER_ATOMIC_SWAP"}, // 64 + {amdgpu_gfx940_op_S_BUFFER_ATOMIC_CMPSWAP,"S_BUFFER_ATOMIC_CMPSWAP"}, // 65 + {amdgpu_gfx940_op_S_BUFFER_ATOMIC_ADD,"S_BUFFER_ATOMIC_ADD"}, // 66 + {amdgpu_gfx940_op_S_BUFFER_ATOMIC_SUB,"S_BUFFER_ATOMIC_SUB"}, // 67 + {amdgpu_gfx940_op_S_BUFFER_ATOMIC_SMIN,"S_BUFFER_ATOMIC_SMIN"}, // 68 + {amdgpu_gfx940_op_S_BUFFER_ATOMIC_UMIN,"S_BUFFER_ATOMIC_UMIN"}, // 69 + {amdgpu_gfx940_op_S_BUFFER_ATOMIC_SMAX,"S_BUFFER_ATOMIC_SMAX"}, // 70 + {amdgpu_gfx940_op_S_BUFFER_ATOMIC_UMAX,"S_BUFFER_ATOMIC_UMAX"}, // 71 + {amdgpu_gfx940_op_S_BUFFER_ATOMIC_AND,"S_BUFFER_ATOMIC_AND"}, // 72 + {amdgpu_gfx940_op_S_BUFFER_ATOMIC_OR,"S_BUFFER_ATOMIC_OR"}, // 73 + {amdgpu_gfx940_op_S_BUFFER_ATOMIC_XOR,"S_BUFFER_ATOMIC_XOR"}, // 74 + {amdgpu_gfx940_op_S_BUFFER_ATOMIC_INC,"S_BUFFER_ATOMIC_INC"}, // 75 + {amdgpu_gfx940_op_S_BUFFER_ATOMIC_DEC,"S_BUFFER_ATOMIC_DEC"}, // 76 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 77 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 78 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 79 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 80 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 81 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 82 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 83 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 84 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 85 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 86 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 87 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 88 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 89 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 90 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 91 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 92 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 93 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 94 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 95 + {amdgpu_gfx940_op_S_BUFFER_ATOMIC_SWAP_X2,"S_BUFFER_ATOMIC_SWAP_X2"}, // 96 + {amdgpu_gfx940_op_S_BUFFER_ATOMIC_CMPSWAP_X2,"S_BUFFER_ATOMIC_CMPSWAP_X2"}, // 97 + {amdgpu_gfx940_op_S_BUFFER_ATOMIC_ADD_X2,"S_BUFFER_ATOMIC_ADD_X2"}, // 98 + {amdgpu_gfx940_op_S_BUFFER_ATOMIC_SUB_X2,"S_BUFFER_ATOMIC_SUB_X2"}, // 99 + {amdgpu_gfx940_op_S_BUFFER_ATOMIC_SMIN_X2,"S_BUFFER_ATOMIC_SMIN_X2"}, // 100 + {amdgpu_gfx940_op_S_BUFFER_ATOMIC_UMIN_X2,"S_BUFFER_ATOMIC_UMIN_X2"}, // 101 + {amdgpu_gfx940_op_S_BUFFER_ATOMIC_SMAX_X2,"S_BUFFER_ATOMIC_SMAX_X2"}, // 102 + {amdgpu_gfx940_op_S_BUFFER_ATOMIC_UMAX_X2,"S_BUFFER_ATOMIC_UMAX_X2"}, // 103 + {amdgpu_gfx940_op_S_BUFFER_ATOMIC_AND_X2,"S_BUFFER_ATOMIC_AND_X2"}, // 104 + {amdgpu_gfx940_op_S_BUFFER_ATOMIC_OR_X2,"S_BUFFER_ATOMIC_OR_X2"}, // 105 + {amdgpu_gfx940_op_S_BUFFER_ATOMIC_XOR_X2,"S_BUFFER_ATOMIC_XOR_X2"}, // 106 + {amdgpu_gfx940_op_S_BUFFER_ATOMIC_INC_X2,"S_BUFFER_ATOMIC_INC_X2"}, // 107 + {amdgpu_gfx940_op_S_BUFFER_ATOMIC_DEC_X2,"S_BUFFER_ATOMIC_DEC_X2"}, // 108 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 109 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 110 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 111 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 112 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 113 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 114 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 115 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 116 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 117 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 118 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 119 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 120 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 121 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 122 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 123 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 124 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 125 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 126 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 127 + {amdgpu_gfx940_op_S_ATOMIC_SWAP,"S_ATOMIC_SWAP"}, // 128 + {amdgpu_gfx940_op_S_ATOMIC_CMPSWAP,"S_ATOMIC_CMPSWAP"}, // 129 + {amdgpu_gfx940_op_S_ATOMIC_ADD,"S_ATOMIC_ADD"}, // 130 + {amdgpu_gfx940_op_S_ATOMIC_SUB,"S_ATOMIC_SUB"}, // 131 + {amdgpu_gfx940_op_S_ATOMIC_SMIN,"S_ATOMIC_SMIN"}, // 132 + {amdgpu_gfx940_op_S_ATOMIC_UMIN,"S_ATOMIC_UMIN"}, // 133 + {amdgpu_gfx940_op_S_ATOMIC_SMAX,"S_ATOMIC_SMAX"}, // 134 + {amdgpu_gfx940_op_S_ATOMIC_UMAX,"S_ATOMIC_UMAX"}, // 135 + {amdgpu_gfx940_op_S_ATOMIC_AND,"S_ATOMIC_AND"}, // 136 + {amdgpu_gfx940_op_S_ATOMIC_OR,"S_ATOMIC_OR"}, // 137 + {amdgpu_gfx940_op_S_ATOMIC_XOR,"S_ATOMIC_XOR"}, // 138 + {amdgpu_gfx940_op_S_ATOMIC_INC,"S_ATOMIC_INC"}, // 139 + {amdgpu_gfx940_op_S_ATOMIC_DEC,"S_ATOMIC_DEC"}, // 140 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 141 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 142 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 143 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 144 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 145 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 146 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 147 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 148 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 149 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 150 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 151 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 152 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 153 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 154 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 155 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 156 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 157 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 158 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 159 + {amdgpu_gfx940_op_S_ATOMIC_SWAP_X2,"S_ATOMIC_SWAP_X2"}, // 160 + {amdgpu_gfx940_op_S_ATOMIC_CMPSWAP_X2,"S_ATOMIC_CMPSWAP_X2"}, // 161 + {amdgpu_gfx940_op_S_ATOMIC_ADD_X2,"S_ATOMIC_ADD_X2"}, // 162 + {amdgpu_gfx940_op_S_ATOMIC_SUB_X2,"S_ATOMIC_SUB_X2"}, // 163 + {amdgpu_gfx940_op_S_ATOMIC_SMIN_X2,"S_ATOMIC_SMIN_X2"}, // 164 + {amdgpu_gfx940_op_S_ATOMIC_UMIN_X2,"S_ATOMIC_UMIN_X2"}, // 165 + {amdgpu_gfx940_op_S_ATOMIC_SMAX_X2,"S_ATOMIC_SMAX_X2"}, // 166 + {amdgpu_gfx940_op_S_ATOMIC_UMAX_X2,"S_ATOMIC_UMAX_X2"}, // 167 + {amdgpu_gfx940_op_S_ATOMIC_AND_X2,"S_ATOMIC_AND_X2"}, // 168 + {amdgpu_gfx940_op_S_ATOMIC_OR_X2,"S_ATOMIC_OR_X2"}, // 169 + {amdgpu_gfx940_op_S_ATOMIC_XOR_X2,"S_ATOMIC_XOR_X2"}, // 170 + {amdgpu_gfx940_op_S_ATOMIC_INC_X2,"S_ATOMIC_INC_X2"}, // 171 + {amdgpu_gfx940_op_S_ATOMIC_DEC_X2,"S_ATOMIC_DEC_X2"}, // 172 + }; // end ENC_SMEM_insn_table + const amdgpu_gfx940_insn_entry ENC_SOP1_insn_table[56] = + { + {amdgpu_gfx940_op_S_MOV_B32,"S_MOV_B32"}, // 0 + {amdgpu_gfx940_op_S_MOV_B64,"S_MOV_B64"}, // 1 + {amdgpu_gfx940_op_S_CMOV_B32,"S_CMOV_B32"}, // 2 + {amdgpu_gfx940_op_S_CMOV_B64,"S_CMOV_B64"}, // 3 + {amdgpu_gfx940_op_S_NOT_B32,"S_NOT_B32"}, // 4 + {amdgpu_gfx940_op_S_NOT_B64,"S_NOT_B64"}, // 5 + {amdgpu_gfx940_op_S_WQM_B32,"S_WQM_B32"}, // 6 + {amdgpu_gfx940_op_S_WQM_B64,"S_WQM_B64"}, // 7 + {amdgpu_gfx940_op_S_BREV_B32,"S_BREV_B32"}, // 8 + {amdgpu_gfx940_op_S_BREV_B64,"S_BREV_B64"}, // 9 + {amdgpu_gfx940_op_S_BCNT0_I32_B32,"S_BCNT0_I32_B32"}, // 10 + {amdgpu_gfx940_op_S_BCNT0_I32_B64,"S_BCNT0_I32_B64"}, // 11 + {amdgpu_gfx940_op_S_BCNT1_I32_B32,"S_BCNT1_I32_B32"}, // 12 + {amdgpu_gfx940_op_S_BCNT1_I32_B64,"S_BCNT1_I32_B64"}, // 13 + {amdgpu_gfx940_op_S_FF0_I32_B32,"S_FF0_I32_B32"}, // 14 + {amdgpu_gfx940_op_S_FF0_I32_B64,"S_FF0_I32_B64"}, // 15 + {amdgpu_gfx940_op_S_FF1_I32_B32,"S_FF1_I32_B32"}, // 16 + {amdgpu_gfx940_op_S_FF1_I32_B64,"S_FF1_I32_B64"}, // 17 + {amdgpu_gfx940_op_S_FLBIT_I32_B32,"S_FLBIT_I32_B32"}, // 18 + {amdgpu_gfx940_op_S_FLBIT_I32_B64,"S_FLBIT_I32_B64"}, // 19 + {amdgpu_gfx940_op_S_FLBIT_I32,"S_FLBIT_I32"}, // 20 + {amdgpu_gfx940_op_S_FLBIT_I32_I64,"S_FLBIT_I32_I64"}, // 21 + {amdgpu_gfx940_op_S_SEXT_I32_I8,"S_SEXT_I32_I8"}, // 22 + {amdgpu_gfx940_op_S_SEXT_I32_I16,"S_SEXT_I32_I16"}, // 23 + {amdgpu_gfx940_op_S_BITSET0_B32,"S_BITSET0_B32"}, // 24 + {amdgpu_gfx940_op_S_BITSET0_B64,"S_BITSET0_B64"}, // 25 + {amdgpu_gfx940_op_S_BITSET1_B32,"S_BITSET1_B32"}, // 26 + {amdgpu_gfx940_op_S_BITSET1_B64,"S_BITSET1_B64"}, // 27 + {amdgpu_gfx940_op_S_GETPC_B64,"S_GETPC_B64"}, // 28 + {amdgpu_gfx940_op_S_SETPC_B64,"S_SETPC_B64"}, // 29 + {amdgpu_gfx940_op_S_SWAPPC_B64,"S_SWAPPC_B64"}, // 30 + {amdgpu_gfx940_op_S_RFE_B64,"S_RFE_B64"}, // 31 + {amdgpu_gfx940_op_S_AND_SAVEEXEC_B64,"S_AND_SAVEEXEC_B64"}, // 32 + {amdgpu_gfx940_op_S_OR_SAVEEXEC_B64,"S_OR_SAVEEXEC_B64"}, // 33 + {amdgpu_gfx940_op_S_XOR_SAVEEXEC_B64,"S_XOR_SAVEEXEC_B64"}, // 34 + {amdgpu_gfx940_op_S_ANDN2_SAVEEXEC_B64,"S_ANDN2_SAVEEXEC_B64"}, // 35 + {amdgpu_gfx940_op_S_ORN2_SAVEEXEC_B64,"S_ORN2_SAVEEXEC_B64"}, // 36 + {amdgpu_gfx940_op_S_NAND_SAVEEXEC_B64,"S_NAND_SAVEEXEC_B64"}, // 37 + {amdgpu_gfx940_op_S_NOR_SAVEEXEC_B64,"S_NOR_SAVEEXEC_B64"}, // 38 + {amdgpu_gfx940_op_S_XNOR_SAVEEXEC_B64,"S_XNOR_SAVEEXEC_B64"}, // 39 + {amdgpu_gfx940_op_S_QUADMASK_B32,"S_QUADMASK_B32"}, // 40 + {amdgpu_gfx940_op_S_QUADMASK_B64,"S_QUADMASK_B64"}, // 41 + {amdgpu_gfx940_op_S_MOVRELS_B32,"S_MOVRELS_B32"}, // 42 + {amdgpu_gfx940_op_S_MOVRELS_B64,"S_MOVRELS_B64"}, // 43 + {amdgpu_gfx940_op_S_MOVRELD_B32,"S_MOVRELD_B32"}, // 44 + {amdgpu_gfx940_op_S_MOVRELD_B64,"S_MOVRELD_B64"}, // 45 + {amdgpu_gfx940_op_S_CBRANCH_JOIN,"S_CBRANCH_JOIN"}, // 46 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 47 + {amdgpu_gfx940_op_S_ABS_I32,"S_ABS_I32"}, // 48 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 49 + {amdgpu_gfx940_op_S_SET_GPR_IDX_IDX,"S_SET_GPR_IDX_IDX"}, // 50 + {amdgpu_gfx940_op_S_ANDN1_SAVEEXEC_B64,"S_ANDN1_SAVEEXEC_B64"}, // 51 + {amdgpu_gfx940_op_S_ORN1_SAVEEXEC_B64,"S_ORN1_SAVEEXEC_B64"}, // 52 + {amdgpu_gfx940_op_S_ANDN1_WREXEC_B64,"S_ANDN1_WREXEC_B64"}, // 53 + {amdgpu_gfx940_op_S_ANDN2_WREXEC_B64,"S_ANDN2_WREXEC_B64"}, // 54 + {amdgpu_gfx940_op_S_BITREPLICATE_B64_B32,"S_BITREPLICATE_B64_B32"}, // 55 + }; // end ENC_SOP1_insn_table + const amdgpu_gfx940_insn_entry ENC_SOP2_insn_table[53] = + { + {amdgpu_gfx940_op_S_ADD_U32,"S_ADD_U32"}, // 0 + {amdgpu_gfx940_op_S_SUB_U32,"S_SUB_U32"}, // 1 + {amdgpu_gfx940_op_S_ADD_I32,"S_ADD_I32"}, // 2 + {amdgpu_gfx940_op_S_SUB_I32,"S_SUB_I32"}, // 3 + {amdgpu_gfx940_op_S_ADDC_U32,"S_ADDC_U32"}, // 4 + {amdgpu_gfx940_op_S_SUBB_U32,"S_SUBB_U32"}, // 5 + {amdgpu_gfx940_op_S_MIN_I32,"S_MIN_I32"}, // 6 + {amdgpu_gfx940_op_S_MIN_U32,"S_MIN_U32"}, // 7 + {amdgpu_gfx940_op_S_MAX_I32,"S_MAX_I32"}, // 8 + {amdgpu_gfx940_op_S_MAX_U32,"S_MAX_U32"}, // 9 + {amdgpu_gfx940_op_S_CSELECT_B32,"S_CSELECT_B32"}, // 10 + {amdgpu_gfx940_op_S_CSELECT_B64,"S_CSELECT_B64"}, // 11 + {amdgpu_gfx940_op_S_AND_B32,"S_AND_B32"}, // 12 + {amdgpu_gfx940_op_S_AND_B64,"S_AND_B64"}, // 13 + {amdgpu_gfx940_op_S_OR_B32,"S_OR_B32"}, // 14 + {amdgpu_gfx940_op_S_OR_B64,"S_OR_B64"}, // 15 + {amdgpu_gfx940_op_S_XOR_B32,"S_XOR_B32"}, // 16 + {amdgpu_gfx940_op_S_XOR_B64,"S_XOR_B64"}, // 17 + {amdgpu_gfx940_op_S_ANDN2_B32,"S_ANDN2_B32"}, // 18 + {amdgpu_gfx940_op_S_ANDN2_B64,"S_ANDN2_B64"}, // 19 + {amdgpu_gfx940_op_S_ORN2_B32,"S_ORN2_B32"}, // 20 + {amdgpu_gfx940_op_S_ORN2_B64,"S_ORN2_B64"}, // 21 + {amdgpu_gfx940_op_S_NAND_B32,"S_NAND_B32"}, // 22 + {amdgpu_gfx940_op_S_NAND_B64,"S_NAND_B64"}, // 23 + {amdgpu_gfx940_op_S_NOR_B32,"S_NOR_B32"}, // 24 + {amdgpu_gfx940_op_S_NOR_B64,"S_NOR_B64"}, // 25 + {amdgpu_gfx940_op_S_XNOR_B32,"S_XNOR_B32"}, // 26 + {amdgpu_gfx940_op_S_XNOR_B64,"S_XNOR_B64"}, // 27 + {amdgpu_gfx940_op_S_LSHL_B32,"S_LSHL_B32"}, // 28 + {amdgpu_gfx940_op_S_LSHL_B64,"S_LSHL_B64"}, // 29 + {amdgpu_gfx940_op_S_LSHR_B32,"S_LSHR_B32"}, // 30 + {amdgpu_gfx940_op_S_LSHR_B64,"S_LSHR_B64"}, // 31 + {amdgpu_gfx940_op_S_ASHR_I32,"S_ASHR_I32"}, // 32 + {amdgpu_gfx940_op_S_ASHR_I64,"S_ASHR_I64"}, // 33 + {amdgpu_gfx940_op_S_BFM_B32,"S_BFM_B32"}, // 34 + {amdgpu_gfx940_op_S_BFM_B64,"S_BFM_B64"}, // 35 + {amdgpu_gfx940_op_S_MUL_I32,"S_MUL_I32"}, // 36 + {amdgpu_gfx940_op_S_BFE_U32,"S_BFE_U32"}, // 37 + {amdgpu_gfx940_op_S_BFE_I32,"S_BFE_I32"}, // 38 + {amdgpu_gfx940_op_S_BFE_U64,"S_BFE_U64"}, // 39 + {amdgpu_gfx940_op_S_BFE_I64,"S_BFE_I64"}, // 40 + {amdgpu_gfx940_op_S_CBRANCH_G_FORK,"S_CBRANCH_G_FORK"}, // 41 + {amdgpu_gfx940_op_S_ABSDIFF_I32,"S_ABSDIFF_I32"}, // 42 + {amdgpu_gfx940_op_S_RFE_RESTORE_B64,"S_RFE_RESTORE_B64"}, // 43 + {amdgpu_gfx940_op_S_MUL_HI_U32,"S_MUL_HI_U32"}, // 44 + {amdgpu_gfx940_op_S_MUL_HI_I32,"S_MUL_HI_I32"}, // 45 + {amdgpu_gfx940_op_S_LSHL1_ADD_U32,"S_LSHL1_ADD_U32"}, // 46 + {amdgpu_gfx940_op_S_LSHL2_ADD_U32,"S_LSHL2_ADD_U32"}, // 47 + {amdgpu_gfx940_op_S_LSHL3_ADD_U32,"S_LSHL3_ADD_U32"}, // 48 + {amdgpu_gfx940_op_S_LSHL4_ADD_U32,"S_LSHL4_ADD_U32"}, // 49 + {amdgpu_gfx940_op_S_PACK_LL_B32_B16,"S_PACK_LL_B32_B16"}, // 50 + {amdgpu_gfx940_op_S_PACK_LH_B32_B16,"S_PACK_LH_B32_B16"}, // 51 + {amdgpu_gfx940_op_S_PACK_HH_B32_B16,"S_PACK_HH_B32_B16"}, // 52 + }; // end ENC_SOP2_insn_table + const amdgpu_gfx940_insn_entry ENC_SOPC_insn_table[20] = + { + {amdgpu_gfx940_op_S_CMP_EQ_I32,"S_CMP_EQ_I32"}, // 0 + {amdgpu_gfx940_op_S_CMP_LG_I32,"S_CMP_LG_I32"}, // 1 + {amdgpu_gfx940_op_S_CMP_GT_I32,"S_CMP_GT_I32"}, // 2 + {amdgpu_gfx940_op_S_CMP_GE_I32,"S_CMP_GE_I32"}, // 3 + {amdgpu_gfx940_op_S_CMP_LT_I32,"S_CMP_LT_I32"}, // 4 + {amdgpu_gfx940_op_S_CMP_LE_I32,"S_CMP_LE_I32"}, // 5 + {amdgpu_gfx940_op_S_CMP_EQ_U32,"S_CMP_EQ_U32"}, // 6 + {amdgpu_gfx940_op_S_CMP_LG_U32,"S_CMP_LG_U32"}, // 7 + {amdgpu_gfx940_op_S_CMP_GT_U32,"S_CMP_GT_U32"}, // 8 + {amdgpu_gfx940_op_S_CMP_GE_U32,"S_CMP_GE_U32"}, // 9 + {amdgpu_gfx940_op_S_CMP_LT_U32,"S_CMP_LT_U32"}, // 10 + {amdgpu_gfx940_op_S_CMP_LE_U32,"S_CMP_LE_U32"}, // 11 + {amdgpu_gfx940_op_S_BITCMP0_B32,"S_BITCMP0_B32"}, // 12 + {amdgpu_gfx940_op_S_BITCMP1_B32,"S_BITCMP1_B32"}, // 13 + {amdgpu_gfx940_op_S_BITCMP0_B64,"S_BITCMP0_B64"}, // 14 + {amdgpu_gfx940_op_S_BITCMP1_B64,"S_BITCMP1_B64"}, // 15 + {amdgpu_gfx940_op_S_SETVSKIP,"S_SETVSKIP"}, // 16 + {amdgpu_gfx940_op_S_SET_GPR_IDX_ON,"S_SET_GPR_IDX_ON"}, // 17 + {amdgpu_gfx940_op_S_CMP_EQ_U64,"S_CMP_EQ_U64"}, // 18 + {amdgpu_gfx940_op_S_CMP_LG_U64,"S_CMP_LG_U64"}, // 19 + }; // end ENC_SOPC_insn_table + const amdgpu_gfx940_insn_entry ENC_SOPK_insn_table[22] = + { + {amdgpu_gfx940_op_S_MOVK_I32,"S_MOVK_I32"}, // 0 + {amdgpu_gfx940_op_S_CMOVK_I32,"S_CMOVK_I32"}, // 1 + {amdgpu_gfx940_op_S_CMPK_EQ_I32,"S_CMPK_EQ_I32"}, // 2 + {amdgpu_gfx940_op_S_CMPK_LG_I32,"S_CMPK_LG_I32"}, // 3 + {amdgpu_gfx940_op_S_CMPK_GT_I32,"S_CMPK_GT_I32"}, // 4 + {amdgpu_gfx940_op_S_CMPK_GE_I32,"S_CMPK_GE_I32"}, // 5 + {amdgpu_gfx940_op_S_CMPK_LT_I32,"S_CMPK_LT_I32"}, // 6 + {amdgpu_gfx940_op_S_CMPK_LE_I32,"S_CMPK_LE_I32"}, // 7 + {amdgpu_gfx940_op_S_CMPK_EQ_U32,"S_CMPK_EQ_U32"}, // 8 + {amdgpu_gfx940_op_S_CMPK_LG_U32,"S_CMPK_LG_U32"}, // 9 + {amdgpu_gfx940_op_S_CMPK_GT_U32,"S_CMPK_GT_U32"}, // 10 + {amdgpu_gfx940_op_S_CMPK_GE_U32,"S_CMPK_GE_U32"}, // 11 + {amdgpu_gfx940_op_S_CMPK_LT_U32,"S_CMPK_LT_U32"}, // 12 + {amdgpu_gfx940_op_S_CMPK_LE_U32,"S_CMPK_LE_U32"}, // 13 + {amdgpu_gfx940_op_S_ADDK_I32,"S_ADDK_I32"}, // 14 + {amdgpu_gfx940_op_S_MULK_I32,"S_MULK_I32"}, // 15 + {amdgpu_gfx940_op_S_CBRANCH_I_FORK,"S_CBRANCH_I_FORK"}, // 16 + {amdgpu_gfx940_op_S_GETREG_B32,"S_GETREG_B32"}, // 17 + {amdgpu_gfx940_op_S_SETREG_B32,"S_SETREG_B32"}, // 18 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 19 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 20 + {amdgpu_gfx940_op_S_CALL_B64,"S_CALL_B64"}, // 21 + }; // end ENC_SOPK_insn_table + const amdgpu_gfx940_insn_entry ENC_SOPP_insn_table[32] = + { + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 0 + {amdgpu_gfx940_op_S_ENDPGM,"S_ENDPGM"}, // 1 + {amdgpu_gfx940_op_S_BRANCH,"S_BRANCH"}, // 2 + {amdgpu_gfx940_op_S_WAKEUP,"S_WAKEUP"}, // 3 + {amdgpu_gfx940_op_S_CBRANCH_SCC0,"S_CBRANCH_SCC0"}, // 4 + {amdgpu_gfx940_op_S_CBRANCH_SCC1,"S_CBRANCH_SCC1"}, // 5 + {amdgpu_gfx940_op_S_CBRANCH_VCCZ,"S_CBRANCH_VCCZ"}, // 6 + {amdgpu_gfx940_op_S_CBRANCH_VCCNZ,"S_CBRANCH_VCCNZ"}, // 7 + {amdgpu_gfx940_op_S_CBRANCH_EXECZ,"S_CBRANCH_EXECZ"}, // 8 + {amdgpu_gfx940_op_S_CBRANCH_EXECNZ,"S_CBRANCH_EXECNZ"}, // 9 + {amdgpu_gfx940_op_S_BARRIER,"S_BARRIER"}, // 10 + {amdgpu_gfx940_op_S_SETKILL,"S_SETKILL"}, // 11 + {amdgpu_gfx940_op_S_WAITCNT,"S_WAITCNT"}, // 12 + {amdgpu_gfx940_op_S_SETHALT,"S_SETHALT"}, // 13 + {amdgpu_gfx940_op_S_SLEEP,"S_SLEEP"}, // 14 + {amdgpu_gfx940_op_S_SETPRIO,"S_SETPRIO"}, // 15 + {amdgpu_gfx940_op_S_SENDMSG,"S_SENDMSG"}, // 16 + {amdgpu_gfx940_op_S_SENDMSGHALT,"S_SENDMSGHALT"}, // 17 + {amdgpu_gfx940_op_S_TRAP,"S_TRAP"}, // 18 + {amdgpu_gfx940_op_S_ICACHE_INV,"S_ICACHE_INV"}, // 19 + {amdgpu_gfx940_op_S_INCPERFLEVEL,"S_INCPERFLEVEL"}, // 20 + {amdgpu_gfx940_op_S_DECPERFLEVEL,"S_DECPERFLEVEL"}, // 21 + {amdgpu_gfx940_op_S_TTRACEDATA,"S_TTRACEDATA"}, // 22 + {amdgpu_gfx940_op_S_CBRANCH_CDBGSYS,"S_CBRANCH_CDBGSYS"}, // 23 + {amdgpu_gfx940_op_S_CBRANCH_CDBGUSER,"S_CBRANCH_CDBGUSER"}, // 24 + {amdgpu_gfx940_op_S_CBRANCH_CDBGSYS_OR_USER,"S_CBRANCH_CDBGSYS_OR_USER"}, // 25 + {amdgpu_gfx940_op_S_CBRANCH_CDBGSYS_AND_USER,"S_CBRANCH_CDBGSYS_AND_USER"}, // 26 + {amdgpu_gfx940_op_S_ENDPGM_SAVED,"S_ENDPGM_SAVED"}, // 27 + {amdgpu_gfx940_op_S_SET_GPR_IDX_OFF,"S_SET_GPR_IDX_OFF"}, // 28 + {amdgpu_gfx940_op_S_SET_GPR_IDX_MODE,"S_SET_GPR_IDX_MODE"}, // 29 + {amdgpu_gfx940_op_S_ENDPGM_ORDERED_PS_DONE,"S_ENDPGM_ORDERED_PS_DONE"}, // 30 + {amdgpu_gfx940_op_S_SET_VALU_COEXEC_MODE,"S_SET_VALU_COEXEC_MODE"}, // 31 + }; // end ENC_SOPP_insn_table + const amdgpu_gfx940_insn_entry ENC_VOP1_insn_table[88] = + { + {amdgpu_gfx940_op_V_NOP,"V_NOP"}, // 0 + {amdgpu_gfx940_op_V_MOV_B32,"V_MOV_B32"}, // 1 + {amdgpu_gfx940_op_V_READFIRSTLANE_B32,"V_READFIRSTLANE_B32"}, // 2 + {amdgpu_gfx940_op_V_CVT_I32_F64,"V_CVT_I32_F64"}, // 3 + {amdgpu_gfx940_op_V_CVT_F64_I32,"V_CVT_F64_I32"}, // 4 + {amdgpu_gfx940_op_V_CVT_F32_I32,"V_CVT_F32_I32"}, // 5 + {amdgpu_gfx940_op_V_CVT_F32_U32,"V_CVT_F32_U32"}, // 6 + {amdgpu_gfx940_op_V_CVT_U32_F32,"V_CVT_U32_F32"}, // 7 + {amdgpu_gfx940_op_V_CVT_I32_F32,"V_CVT_I32_F32"}, // 8 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 9 + {amdgpu_gfx940_op_V_CVT_F16_F32,"V_CVT_F16_F32"}, // 10 + {amdgpu_gfx940_op_V_CVT_F32_F16,"V_CVT_F32_F16"}, // 11 + {amdgpu_gfx940_op_V_CVT_RPI_I32_F32,"V_CVT_RPI_I32_F32"}, // 12 + {amdgpu_gfx940_op_V_CVT_FLR_I32_F32,"V_CVT_FLR_I32_F32"}, // 13 + {amdgpu_gfx940_op_V_CVT_OFF_F32_I4,"V_CVT_OFF_F32_I4"}, // 14 + {amdgpu_gfx940_op_V_CVT_F32_F64,"V_CVT_F32_F64"}, // 15 + {amdgpu_gfx940_op_V_CVT_F64_F32,"V_CVT_F64_F32"}, // 16 + {amdgpu_gfx940_op_V_CVT_F32_UBYTE0,"V_CVT_F32_UBYTE0"}, // 17 + {amdgpu_gfx940_op_V_CVT_F32_UBYTE1,"V_CVT_F32_UBYTE1"}, // 18 + {amdgpu_gfx940_op_V_CVT_F32_UBYTE2,"V_CVT_F32_UBYTE2"}, // 19 + {amdgpu_gfx940_op_V_CVT_F32_UBYTE3,"V_CVT_F32_UBYTE3"}, // 20 + {amdgpu_gfx940_op_V_CVT_U32_F64,"V_CVT_U32_F64"}, // 21 + {amdgpu_gfx940_op_V_CVT_F64_U32,"V_CVT_F64_U32"}, // 22 + {amdgpu_gfx940_op_V_TRUNC_F64,"V_TRUNC_F64"}, // 23 + {amdgpu_gfx940_op_V_CEIL_F64,"V_CEIL_F64"}, // 24 + {amdgpu_gfx940_op_V_RNDNE_F64,"V_RNDNE_F64"}, // 25 + {amdgpu_gfx940_op_V_FLOOR_F64,"V_FLOOR_F64"}, // 26 + {amdgpu_gfx940_op_V_FRACT_F32,"V_FRACT_F32"}, // 27 + {amdgpu_gfx940_op_V_TRUNC_F32,"V_TRUNC_F32"}, // 28 + {amdgpu_gfx940_op_V_CEIL_F32,"V_CEIL_F32"}, // 29 + {amdgpu_gfx940_op_V_RNDNE_F32,"V_RNDNE_F32"}, // 30 + {amdgpu_gfx940_op_V_FLOOR_F32,"V_FLOOR_F32"}, // 31 + {amdgpu_gfx940_op_V_EXP_F32,"V_EXP_F32"}, // 32 + {amdgpu_gfx940_op_V_LOG_F32,"V_LOG_F32"}, // 33 + {amdgpu_gfx940_op_V_RCP_F32,"V_RCP_F32"}, // 34 + {amdgpu_gfx940_op_V_RCP_IFLAG_F32,"V_RCP_IFLAG_F32"}, // 35 + {amdgpu_gfx940_op_V_RSQ_F32,"V_RSQ_F32"}, // 36 + {amdgpu_gfx940_op_V_RCP_F64,"V_RCP_F64"}, // 37 + {amdgpu_gfx940_op_V_RSQ_F64,"V_RSQ_F64"}, // 38 + {amdgpu_gfx940_op_V_SQRT_F32,"V_SQRT_F32"}, // 39 + {amdgpu_gfx940_op_V_SQRT_F64,"V_SQRT_F64"}, // 40 + {amdgpu_gfx940_op_V_SIN_F32,"V_SIN_F32"}, // 41 + {amdgpu_gfx940_op_V_COS_F32,"V_COS_F32"}, // 42 + {amdgpu_gfx940_op_V_NOT_B32,"V_NOT_B32"}, // 43 + {amdgpu_gfx940_op_V_BFREV_B32,"V_BFREV_B32"}, // 44 + {amdgpu_gfx940_op_V_FFBH_U32,"V_FFBH_U32"}, // 45 + {amdgpu_gfx940_op_V_FFBL_B32,"V_FFBL_B32"}, // 46 + {amdgpu_gfx940_op_V_FFBH_I32,"V_FFBH_I32"}, // 47 + {amdgpu_gfx940_op_V_FREXP_EXP_I32_F64,"V_FREXP_EXP_I32_F64"}, // 48 + {amdgpu_gfx940_op_V_FREXP_MANT_F64,"V_FREXP_MANT_F64"}, // 49 + {amdgpu_gfx940_op_V_FRACT_F64,"V_FRACT_F64"}, // 50 + {amdgpu_gfx940_op_V_FREXP_EXP_I32_F32,"V_FREXP_EXP_I32_F32"}, // 51 + {amdgpu_gfx940_op_V_FREXP_MANT_F32,"V_FREXP_MANT_F32"}, // 52 + {amdgpu_gfx940_op_V_CLREXCP,"V_CLREXCP"}, // 53 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 54 + {amdgpu_gfx940_op_V_SCREEN_PARTITION_4SE_B32,"V_SCREEN_PARTITION_4SE_B32"}, // 55 + {amdgpu_gfx940_op_V_MOV_B64,"V_MOV_B64"}, // 56 + {amdgpu_gfx940_op_V_CVT_F16_U16,"V_CVT_F16_U16"}, // 57 + {amdgpu_gfx940_op_V_CVT_F16_I16,"V_CVT_F16_I16"}, // 58 + {amdgpu_gfx940_op_V_CVT_U16_F16,"V_CVT_U16_F16"}, // 59 + {amdgpu_gfx940_op_V_CVT_I16_F16,"V_CVT_I16_F16"}, // 60 + {amdgpu_gfx940_op_V_RCP_F16,"V_RCP_F16"}, // 61 + {amdgpu_gfx940_op_V_SQRT_F16,"V_SQRT_F16"}, // 62 + {amdgpu_gfx940_op_V_RSQ_F16,"V_RSQ_F16"}, // 63 + {amdgpu_gfx940_op_V_LOG_F16,"V_LOG_F16"}, // 64 + {amdgpu_gfx940_op_V_EXP_F16,"V_EXP_F16"}, // 65 + {amdgpu_gfx940_op_V_FREXP_MANT_F16,"V_FREXP_MANT_F16"}, // 66 + {amdgpu_gfx940_op_V_FREXP_EXP_I16_F16,"V_FREXP_EXP_I16_F16"}, // 67 + {amdgpu_gfx940_op_V_FLOOR_F16,"V_FLOOR_F16"}, // 68 + {amdgpu_gfx940_op_V_CEIL_F16,"V_CEIL_F16"}, // 69 + {amdgpu_gfx940_op_V_TRUNC_F16,"V_TRUNC_F16"}, // 70 + {amdgpu_gfx940_op_V_RNDNE_F16,"V_RNDNE_F16"}, // 71 + {amdgpu_gfx940_op_V_FRACT_F16,"V_FRACT_F16"}, // 72 + {amdgpu_gfx940_op_V_SIN_F16,"V_SIN_F16"}, // 73 + {amdgpu_gfx940_op_V_COS_F16,"V_COS_F16"}, // 74 + {amdgpu_gfx940_op_V_EXP_LEGACY_F32,"V_EXP_LEGACY_F32"}, // 75 + {amdgpu_gfx940_op_V_LOG_LEGACY_F32,"V_LOG_LEGACY_F32"}, // 76 + {amdgpu_gfx940_op_V_CVT_NORM_I16_F16,"V_CVT_NORM_I16_F16"}, // 77 + {amdgpu_gfx940_op_V_CVT_NORM_U16_F16,"V_CVT_NORM_U16_F16"}, // 78 + {amdgpu_gfx940_op_V_SAT_PK_U8_I16,"V_SAT_PK_U8_I16"}, // 79 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 80 + {amdgpu_gfx940_op_V_SWAP_B32,"V_SWAP_B32"}, // 81 + {amdgpu_gfx940_op_V_ACCVGPR_MOV_B32,"V_ACCVGPR_MOV_B32"}, // 82 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 83 + {amdgpu_gfx940_op_V_CVT_F32_FP8,"V_CVT_F32_FP8"}, // 84 + {amdgpu_gfx940_op_V_CVT_F32_BF8,"V_CVT_F32_BF8"}, // 85 + {amdgpu_gfx940_op_V_CVT_PK_F32_FP8,"V_CVT_PK_F32_FP8"}, // 86 + {amdgpu_gfx940_op_V_CVT_PK_F32_BF8,"V_CVT_PK_F32_BF8"}, // 87 + }; // end ENC_VOP1_insn_table + const amdgpu_gfx940_insn_entry ENC_VOP3_insn_table[678] = + { + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 0 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 1 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 2 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 3 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 4 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 5 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 6 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 7 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 8 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 9 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 10 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 11 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 12 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 13 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 14 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 15 + {amdgpu_gfx940_op_V_CMP_CLASS_F32,"V_CMP_CLASS_F32"}, // 16 + {amdgpu_gfx940_op_V_CMPX_CLASS_F32,"V_CMPX_CLASS_F32"}, // 17 + {amdgpu_gfx940_op_V_CMP_CLASS_F64,"V_CMP_CLASS_F64"}, // 18 + {amdgpu_gfx940_op_V_CMPX_CLASS_F64,"V_CMPX_CLASS_F64"}, // 19 + {amdgpu_gfx940_op_V_CMP_CLASS_F16,"V_CMP_CLASS_F16"}, // 20 + {amdgpu_gfx940_op_V_CMPX_CLASS_F16,"V_CMPX_CLASS_F16"}, // 21 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 22 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 23 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 24 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 25 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 26 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 27 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 28 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 29 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 30 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 31 + {amdgpu_gfx940_op_V_CMP_F_F16,"V_CMP_F_F16"}, // 32 + {amdgpu_gfx940_op_V_CMP_LT_F16,"V_CMP_LT_F16"}, // 33 + {amdgpu_gfx940_op_V_CMP_EQ_F16,"V_CMP_EQ_F16"}, // 34 + {amdgpu_gfx940_op_V_CMP_LE_F16,"V_CMP_LE_F16"}, // 35 + {amdgpu_gfx940_op_V_CMP_GT_F16,"V_CMP_GT_F16"}, // 36 + {amdgpu_gfx940_op_V_CMP_LG_F16,"V_CMP_LG_F16"}, // 37 + {amdgpu_gfx940_op_V_CMP_GE_F16,"V_CMP_GE_F16"}, // 38 + {amdgpu_gfx940_op_V_CMP_O_F16,"V_CMP_O_F16"}, // 39 + {amdgpu_gfx940_op_V_CMP_U_F16,"V_CMP_U_F16"}, // 40 + {amdgpu_gfx940_op_V_CMP_NGE_F16,"V_CMP_NGE_F16"}, // 41 + {amdgpu_gfx940_op_V_CMP_NLG_F16,"V_CMP_NLG_F16"}, // 42 + {amdgpu_gfx940_op_V_CMP_NGT_F16,"V_CMP_NGT_F16"}, // 43 + {amdgpu_gfx940_op_V_CMP_NLE_F16,"V_CMP_NLE_F16"}, // 44 + {amdgpu_gfx940_op_V_CMP_NEQ_F16,"V_CMP_NEQ_F16"}, // 45 + {amdgpu_gfx940_op_V_CMP_NLT_F16,"V_CMP_NLT_F16"}, // 46 + {amdgpu_gfx940_op_V_CMP_TRU_F16,"V_CMP_TRU_F16"}, // 47 + {amdgpu_gfx940_op_V_CMPX_F_F16,"V_CMPX_F_F16"}, // 48 + {amdgpu_gfx940_op_V_CMPX_LT_F16,"V_CMPX_LT_F16"}, // 49 + {amdgpu_gfx940_op_V_CMPX_EQ_F16,"V_CMPX_EQ_F16"}, // 50 + {amdgpu_gfx940_op_V_CMPX_LE_F16,"V_CMPX_LE_F16"}, // 51 + {amdgpu_gfx940_op_V_CMPX_GT_F16,"V_CMPX_GT_F16"}, // 52 + {amdgpu_gfx940_op_V_CMPX_LG_F16,"V_CMPX_LG_F16"}, // 53 + {amdgpu_gfx940_op_V_CMPX_GE_F16,"V_CMPX_GE_F16"}, // 54 + {amdgpu_gfx940_op_V_CMPX_O_F16,"V_CMPX_O_F16"}, // 55 + {amdgpu_gfx940_op_V_CMPX_U_F16,"V_CMPX_U_F16"}, // 56 + {amdgpu_gfx940_op_V_CMPX_NGE_F16,"V_CMPX_NGE_F16"}, // 57 + {amdgpu_gfx940_op_V_CMPX_NLG_F16,"V_CMPX_NLG_F16"}, // 58 + {amdgpu_gfx940_op_V_CMPX_NGT_F16,"V_CMPX_NGT_F16"}, // 59 + {amdgpu_gfx940_op_V_CMPX_NLE_F16,"V_CMPX_NLE_F16"}, // 60 + {amdgpu_gfx940_op_V_CMPX_NEQ_F16,"V_CMPX_NEQ_F16"}, // 61 + {amdgpu_gfx940_op_V_CMPX_NLT_F16,"V_CMPX_NLT_F16"}, // 62 + {amdgpu_gfx940_op_V_CMPX_TRU_F16,"V_CMPX_TRU_F16"}, // 63 + {amdgpu_gfx940_op_V_CMP_F_F32,"V_CMP_F_F32"}, // 64 + {amdgpu_gfx940_op_V_CMP_LT_F32,"V_CMP_LT_F32"}, // 65 + {amdgpu_gfx940_op_V_CMP_EQ_F32,"V_CMP_EQ_F32"}, // 66 + {amdgpu_gfx940_op_V_CMP_LE_F32,"V_CMP_LE_F32"}, // 67 + {amdgpu_gfx940_op_V_CMP_GT_F32,"V_CMP_GT_F32"}, // 68 + {amdgpu_gfx940_op_V_CMP_LG_F32,"V_CMP_LG_F32"}, // 69 + {amdgpu_gfx940_op_V_CMP_GE_F32,"V_CMP_GE_F32"}, // 70 + {amdgpu_gfx940_op_V_CMP_O_F32,"V_CMP_O_F32"}, // 71 + {amdgpu_gfx940_op_V_CMP_U_F32,"V_CMP_U_F32"}, // 72 + {amdgpu_gfx940_op_V_CMP_NGE_F32,"V_CMP_NGE_F32"}, // 73 + {amdgpu_gfx940_op_V_CMP_NLG_F32,"V_CMP_NLG_F32"}, // 74 + {amdgpu_gfx940_op_V_CMP_NGT_F32,"V_CMP_NGT_F32"}, // 75 + {amdgpu_gfx940_op_V_CMP_NLE_F32,"V_CMP_NLE_F32"}, // 76 + {amdgpu_gfx940_op_V_CMP_NEQ_F32,"V_CMP_NEQ_F32"}, // 77 + {amdgpu_gfx940_op_V_CMP_NLT_F32,"V_CMP_NLT_F32"}, // 78 + {amdgpu_gfx940_op_V_CMP_TRU_F32,"V_CMP_TRU_F32"}, // 79 + {amdgpu_gfx940_op_V_CMPX_F_F32,"V_CMPX_F_F32"}, // 80 + {amdgpu_gfx940_op_V_CMPX_LT_F32,"V_CMPX_LT_F32"}, // 81 + {amdgpu_gfx940_op_V_CMPX_EQ_F32,"V_CMPX_EQ_F32"}, // 82 + {amdgpu_gfx940_op_V_CMPX_LE_F32,"V_CMPX_LE_F32"}, // 83 + {amdgpu_gfx940_op_V_CMPX_GT_F32,"V_CMPX_GT_F32"}, // 84 + {amdgpu_gfx940_op_V_CMPX_LG_F32,"V_CMPX_LG_F32"}, // 85 + {amdgpu_gfx940_op_V_CMPX_GE_F32,"V_CMPX_GE_F32"}, // 86 + {amdgpu_gfx940_op_V_CMPX_O_F32,"V_CMPX_O_F32"}, // 87 + {amdgpu_gfx940_op_V_CMPX_U_F32,"V_CMPX_U_F32"}, // 88 + {amdgpu_gfx940_op_V_CMPX_NGE_F32,"V_CMPX_NGE_F32"}, // 89 + {amdgpu_gfx940_op_V_CMPX_NLG_F32,"V_CMPX_NLG_F32"}, // 90 + {amdgpu_gfx940_op_V_CMPX_NGT_F32,"V_CMPX_NGT_F32"}, // 91 + {amdgpu_gfx940_op_V_CMPX_NLE_F32,"V_CMPX_NLE_F32"}, // 92 + {amdgpu_gfx940_op_V_CMPX_NEQ_F32,"V_CMPX_NEQ_F32"}, // 93 + {amdgpu_gfx940_op_V_CMPX_NLT_F32,"V_CMPX_NLT_F32"}, // 94 + {amdgpu_gfx940_op_V_CMPX_TRU_F32,"V_CMPX_TRU_F32"}, // 95 + {amdgpu_gfx940_op_V_CMP_F_F64,"V_CMP_F_F64"}, // 96 + {amdgpu_gfx940_op_V_CMP_LT_F64,"V_CMP_LT_F64"}, // 97 + {amdgpu_gfx940_op_V_CMP_EQ_F64,"V_CMP_EQ_F64"}, // 98 + {amdgpu_gfx940_op_V_CMP_LE_F64,"V_CMP_LE_F64"}, // 99 + {amdgpu_gfx940_op_V_CMP_GT_F64,"V_CMP_GT_F64"}, // 100 + {amdgpu_gfx940_op_V_CMP_LG_F64,"V_CMP_LG_F64"}, // 101 + {amdgpu_gfx940_op_V_CMP_GE_F64,"V_CMP_GE_F64"}, // 102 + {amdgpu_gfx940_op_V_CMP_O_F64,"V_CMP_O_F64"}, // 103 + {amdgpu_gfx940_op_V_CMP_U_F64,"V_CMP_U_F64"}, // 104 + {amdgpu_gfx940_op_V_CMP_NGE_F64,"V_CMP_NGE_F64"}, // 105 + {amdgpu_gfx940_op_V_CMP_NLG_F64,"V_CMP_NLG_F64"}, // 106 + {amdgpu_gfx940_op_V_CMP_NGT_F64,"V_CMP_NGT_F64"}, // 107 + {amdgpu_gfx940_op_V_CMP_NLE_F64,"V_CMP_NLE_F64"}, // 108 + {amdgpu_gfx940_op_V_CMP_NEQ_F64,"V_CMP_NEQ_F64"}, // 109 + {amdgpu_gfx940_op_V_CMP_NLT_F64,"V_CMP_NLT_F64"}, // 110 + {amdgpu_gfx940_op_V_CMP_TRU_F64,"V_CMP_TRU_F64"}, // 111 + {amdgpu_gfx940_op_V_CMPX_F_F64,"V_CMPX_F_F64"}, // 112 + {amdgpu_gfx940_op_V_CMPX_LT_F64,"V_CMPX_LT_F64"}, // 113 + {amdgpu_gfx940_op_V_CMPX_EQ_F64,"V_CMPX_EQ_F64"}, // 114 + {amdgpu_gfx940_op_V_CMPX_LE_F64,"V_CMPX_LE_F64"}, // 115 + {amdgpu_gfx940_op_V_CMPX_GT_F64,"V_CMPX_GT_F64"}, // 116 + {amdgpu_gfx940_op_V_CMPX_LG_F64,"V_CMPX_LG_F64"}, // 117 + {amdgpu_gfx940_op_V_CMPX_GE_F64,"V_CMPX_GE_F64"}, // 118 + {amdgpu_gfx940_op_V_CMPX_O_F64,"V_CMPX_O_F64"}, // 119 + {amdgpu_gfx940_op_V_CMPX_U_F64,"V_CMPX_U_F64"}, // 120 + {amdgpu_gfx940_op_V_CMPX_NGE_F64,"V_CMPX_NGE_F64"}, // 121 + {amdgpu_gfx940_op_V_CMPX_NLG_F64,"V_CMPX_NLG_F64"}, // 122 + {amdgpu_gfx940_op_V_CMPX_NGT_F64,"V_CMPX_NGT_F64"}, // 123 + {amdgpu_gfx940_op_V_CMPX_NLE_F64,"V_CMPX_NLE_F64"}, // 124 + {amdgpu_gfx940_op_V_CMPX_NEQ_F64,"V_CMPX_NEQ_F64"}, // 125 + {amdgpu_gfx940_op_V_CMPX_NLT_F64,"V_CMPX_NLT_F64"}, // 126 + {amdgpu_gfx940_op_V_CMPX_TRU_F64,"V_CMPX_TRU_F64"}, // 127 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 128 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 129 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 130 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 131 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 132 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 133 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 134 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 135 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 136 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 137 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 138 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 139 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 140 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 141 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 142 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 143 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 144 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 145 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 146 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 147 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 148 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 149 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 150 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 151 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 152 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 153 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 154 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 155 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 156 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 157 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 158 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 159 + {amdgpu_gfx940_op_V_CMP_F_I16,"V_CMP_F_I16"}, // 160 + {amdgpu_gfx940_op_V_CMP_LT_I16,"V_CMP_LT_I16"}, // 161 + {amdgpu_gfx940_op_V_CMP_EQ_I16,"V_CMP_EQ_I16"}, // 162 + {amdgpu_gfx940_op_V_CMP_LE_I16,"V_CMP_LE_I16"}, // 163 + {amdgpu_gfx940_op_V_CMP_GT_I16,"V_CMP_GT_I16"}, // 164 + {amdgpu_gfx940_op_V_CMP_NE_I16,"V_CMP_NE_I16"}, // 165 + {amdgpu_gfx940_op_V_CMP_GE_I16,"V_CMP_GE_I16"}, // 166 + {amdgpu_gfx940_op_V_CMP_T_I16,"V_CMP_T_I16"}, // 167 + {amdgpu_gfx940_op_V_CMP_F_U16,"V_CMP_F_U16"}, // 168 + {amdgpu_gfx940_op_V_CMP_LT_U16,"V_CMP_LT_U16"}, // 169 + {amdgpu_gfx940_op_V_CMP_EQ_U16,"V_CMP_EQ_U16"}, // 170 + {amdgpu_gfx940_op_V_CMP_LE_U16,"V_CMP_LE_U16"}, // 171 + {amdgpu_gfx940_op_V_CMP_GT_U16,"V_CMP_GT_U16"}, // 172 + {amdgpu_gfx940_op_V_CMP_NE_U16,"V_CMP_NE_U16"}, // 173 + {amdgpu_gfx940_op_V_CMP_GE_U16,"V_CMP_GE_U16"}, // 174 + {amdgpu_gfx940_op_V_CMP_T_U16,"V_CMP_T_U16"}, // 175 + {amdgpu_gfx940_op_V_CMPX_F_I16,"V_CMPX_F_I16"}, // 176 + {amdgpu_gfx940_op_V_CMPX_LT_I16,"V_CMPX_LT_I16"}, // 177 + {amdgpu_gfx940_op_V_CMPX_EQ_I16,"V_CMPX_EQ_I16"}, // 178 + {amdgpu_gfx940_op_V_CMPX_LE_I16,"V_CMPX_LE_I16"}, // 179 + {amdgpu_gfx940_op_V_CMPX_GT_I16,"V_CMPX_GT_I16"}, // 180 + {amdgpu_gfx940_op_V_CMPX_NE_I16,"V_CMPX_NE_I16"}, // 181 + {amdgpu_gfx940_op_V_CMPX_GE_I16,"V_CMPX_GE_I16"}, // 182 + {amdgpu_gfx940_op_V_CMPX_T_I16,"V_CMPX_T_I16"}, // 183 + {amdgpu_gfx940_op_V_CMPX_F_U16,"V_CMPX_F_U16"}, // 184 + {amdgpu_gfx940_op_V_CMPX_LT_U16,"V_CMPX_LT_U16"}, // 185 + {amdgpu_gfx940_op_V_CMPX_EQ_U16,"V_CMPX_EQ_U16"}, // 186 + {amdgpu_gfx940_op_V_CMPX_LE_U16,"V_CMPX_LE_U16"}, // 187 + {amdgpu_gfx940_op_V_CMPX_GT_U16,"V_CMPX_GT_U16"}, // 188 + {amdgpu_gfx940_op_V_CMPX_NE_U16,"V_CMPX_NE_U16"}, // 189 + {amdgpu_gfx940_op_V_CMPX_GE_U16,"V_CMPX_GE_U16"}, // 190 + {amdgpu_gfx940_op_V_CMPX_T_U16,"V_CMPX_T_U16"}, // 191 + {amdgpu_gfx940_op_V_CMP_F_I32,"V_CMP_F_I32"}, // 192 + {amdgpu_gfx940_op_V_CMP_LT_I32,"V_CMP_LT_I32"}, // 193 + {amdgpu_gfx940_op_V_CMP_EQ_I32,"V_CMP_EQ_I32"}, // 194 + {amdgpu_gfx940_op_V_CMP_LE_I32,"V_CMP_LE_I32"}, // 195 + {amdgpu_gfx940_op_V_CMP_GT_I32,"V_CMP_GT_I32"}, // 196 + {amdgpu_gfx940_op_V_CMP_NE_I32,"V_CMP_NE_I32"}, // 197 + {amdgpu_gfx940_op_V_CMP_GE_I32,"V_CMP_GE_I32"}, // 198 + {amdgpu_gfx940_op_V_CMP_T_I32,"V_CMP_T_I32"}, // 199 + {amdgpu_gfx940_op_V_CMP_F_U32,"V_CMP_F_U32"}, // 200 + {amdgpu_gfx940_op_V_CMP_LT_U32,"V_CMP_LT_U32"}, // 201 + {amdgpu_gfx940_op_V_CMP_EQ_U32,"V_CMP_EQ_U32"}, // 202 + {amdgpu_gfx940_op_V_CMP_LE_U32,"V_CMP_LE_U32"}, // 203 + {amdgpu_gfx940_op_V_CMP_GT_U32,"V_CMP_GT_U32"}, // 204 + {amdgpu_gfx940_op_V_CMP_NE_U32,"V_CMP_NE_U32"}, // 205 + {amdgpu_gfx940_op_V_CMP_GE_U32,"V_CMP_GE_U32"}, // 206 + {amdgpu_gfx940_op_V_CMP_T_U32,"V_CMP_T_U32"}, // 207 + {amdgpu_gfx940_op_V_CMPX_F_I32,"V_CMPX_F_I32"}, // 208 + {amdgpu_gfx940_op_V_CMPX_LT_I32,"V_CMPX_LT_I32"}, // 209 + {amdgpu_gfx940_op_V_CMPX_EQ_I32,"V_CMPX_EQ_I32"}, // 210 + {amdgpu_gfx940_op_V_CMPX_LE_I32,"V_CMPX_LE_I32"}, // 211 + {amdgpu_gfx940_op_V_CMPX_GT_I32,"V_CMPX_GT_I32"}, // 212 + {amdgpu_gfx940_op_V_CMPX_NE_I32,"V_CMPX_NE_I32"}, // 213 + {amdgpu_gfx940_op_V_CMPX_GE_I32,"V_CMPX_GE_I32"}, // 214 + {amdgpu_gfx940_op_V_CMPX_T_I32,"V_CMPX_T_I32"}, // 215 + {amdgpu_gfx940_op_V_CMPX_F_U32,"V_CMPX_F_U32"}, // 216 + {amdgpu_gfx940_op_V_CMPX_LT_U32,"V_CMPX_LT_U32"}, // 217 + {amdgpu_gfx940_op_V_CMPX_EQ_U32,"V_CMPX_EQ_U32"}, // 218 + {amdgpu_gfx940_op_V_CMPX_LE_U32,"V_CMPX_LE_U32"}, // 219 + {amdgpu_gfx940_op_V_CMPX_GT_U32,"V_CMPX_GT_U32"}, // 220 + {amdgpu_gfx940_op_V_CMPX_NE_U32,"V_CMPX_NE_U32"}, // 221 + {amdgpu_gfx940_op_V_CMPX_GE_U32,"V_CMPX_GE_U32"}, // 222 + {amdgpu_gfx940_op_V_CMPX_T_U32,"V_CMPX_T_U32"}, // 223 + {amdgpu_gfx940_op_V_CMP_F_I64,"V_CMP_F_I64"}, // 224 + {amdgpu_gfx940_op_V_CMP_LT_I64,"V_CMP_LT_I64"}, // 225 + {amdgpu_gfx940_op_V_CMP_EQ_I64,"V_CMP_EQ_I64"}, // 226 + {amdgpu_gfx940_op_V_CMP_LE_I64,"V_CMP_LE_I64"}, // 227 + {amdgpu_gfx940_op_V_CMP_GT_I64,"V_CMP_GT_I64"}, // 228 + {amdgpu_gfx940_op_V_CMP_NE_I64,"V_CMP_NE_I64"}, // 229 + {amdgpu_gfx940_op_V_CMP_GE_I64,"V_CMP_GE_I64"}, // 230 + {amdgpu_gfx940_op_V_CMP_T_I64,"V_CMP_T_I64"}, // 231 + {amdgpu_gfx940_op_V_CMP_F_U64,"V_CMP_F_U64"}, // 232 + {amdgpu_gfx940_op_V_CMP_LT_U64,"V_CMP_LT_U64"}, // 233 + {amdgpu_gfx940_op_V_CMP_EQ_U64,"V_CMP_EQ_U64"}, // 234 + {amdgpu_gfx940_op_V_CMP_LE_U64,"V_CMP_LE_U64"}, // 235 + {amdgpu_gfx940_op_V_CMP_GT_U64,"V_CMP_GT_U64"}, // 236 + {amdgpu_gfx940_op_V_CMP_NE_U64,"V_CMP_NE_U64"}, // 237 + {amdgpu_gfx940_op_V_CMP_GE_U64,"V_CMP_GE_U64"}, // 238 + {amdgpu_gfx940_op_V_CMP_T_U64,"V_CMP_T_U64"}, // 239 + {amdgpu_gfx940_op_V_CMPX_F_I64,"V_CMPX_F_I64"}, // 240 + {amdgpu_gfx940_op_V_CMPX_LT_I64,"V_CMPX_LT_I64"}, // 241 + {amdgpu_gfx940_op_V_CMPX_EQ_I64,"V_CMPX_EQ_I64"}, // 242 + {amdgpu_gfx940_op_V_CMPX_LE_I64,"V_CMPX_LE_I64"}, // 243 + {amdgpu_gfx940_op_V_CMPX_GT_I64,"V_CMPX_GT_I64"}, // 244 + {amdgpu_gfx940_op_V_CMPX_NE_I64,"V_CMPX_NE_I64"}, // 245 + {amdgpu_gfx940_op_V_CMPX_GE_I64,"V_CMPX_GE_I64"}, // 246 + {amdgpu_gfx940_op_V_CMPX_T_I64,"V_CMPX_T_I64"}, // 247 + {amdgpu_gfx940_op_V_CMPX_F_U64,"V_CMPX_F_U64"}, // 248 + {amdgpu_gfx940_op_V_CMPX_LT_U64,"V_CMPX_LT_U64"}, // 249 + {amdgpu_gfx940_op_V_CMPX_EQ_U64,"V_CMPX_EQ_U64"}, // 250 + {amdgpu_gfx940_op_V_CMPX_LE_U64,"V_CMPX_LE_U64"}, // 251 + {amdgpu_gfx940_op_V_CMPX_GT_U64,"V_CMPX_GT_U64"}, // 252 + {amdgpu_gfx940_op_V_CMPX_NE_U64,"V_CMPX_NE_U64"}, // 253 + {amdgpu_gfx940_op_V_CMPX_GE_U64,"V_CMPX_GE_U64"}, // 254 + {amdgpu_gfx940_op_V_CMPX_T_U64,"V_CMPX_T_U64"}, // 255 + {amdgpu_gfx940_op_V_CNDMASK_B32,"V_CNDMASK_B32"}, // 256 + {amdgpu_gfx940_op_V_ADD_F32,"V_ADD_F32"}, // 257 + {amdgpu_gfx940_op_V_SUB_F32,"V_SUB_F32"}, // 258 + {amdgpu_gfx940_op_V_SUBREV_F32,"V_SUBREV_F32"}, // 259 + {amdgpu_gfx940_op_V_FMAC_F64,"V_FMAC_F64"}, // 260 + {amdgpu_gfx940_op_V_MUL_F32,"V_MUL_F32"}, // 261 + {amdgpu_gfx940_op_V_MUL_I32_I24,"V_MUL_I32_I24"}, // 262 + {amdgpu_gfx940_op_V_MUL_HI_I32_I24,"V_MUL_HI_I32_I24"}, // 263 + {amdgpu_gfx940_op_V_MUL_U32_U24,"V_MUL_U32_U24"}, // 264 + {amdgpu_gfx940_op_V_MUL_HI_U32_U24,"V_MUL_HI_U32_U24"}, // 265 + {amdgpu_gfx940_op_V_MIN_F32,"V_MIN_F32"}, // 266 + {amdgpu_gfx940_op_V_MAX_F32,"V_MAX_F32"}, // 267 + {amdgpu_gfx940_op_V_MIN_I32,"V_MIN_I32"}, // 268 + {amdgpu_gfx940_op_V_MAX_I32,"V_MAX_I32"}, // 269 + {amdgpu_gfx940_op_V_MIN_U32,"V_MIN_U32"}, // 270 + {amdgpu_gfx940_op_V_MAX_U32,"V_MAX_U32"}, // 271 + {amdgpu_gfx940_op_V_LSHRREV_B32,"V_LSHRREV_B32"}, // 272 + {amdgpu_gfx940_op_V_ASHRREV_I32,"V_ASHRREV_I32"}, // 273 + {amdgpu_gfx940_op_V_LSHLREV_B32,"V_LSHLREV_B32"}, // 274 + {amdgpu_gfx940_op_V_AND_B32,"V_AND_B32"}, // 275 + {amdgpu_gfx940_op_V_OR_B32,"V_OR_B32"}, // 276 + {amdgpu_gfx940_op_V_XOR_B32,"V_XOR_B32"}, // 277 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 278 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 279 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 280 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 281 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 282 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 283 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 284 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 285 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 286 + {amdgpu_gfx940_op_V_ADD_F16,"V_ADD_F16"}, // 287 + {amdgpu_gfx940_op_V_SUB_F16,"V_SUB_F16"}, // 288 + {amdgpu_gfx940_op_V_SUBREV_F16,"V_SUBREV_F16"}, // 289 + {amdgpu_gfx940_op_V_MUL_F16,"V_MUL_F16"}, // 290 + {amdgpu_gfx940_op_V_MAC_F16,"V_MAC_F16"}, // 291 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 292 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 293 + {amdgpu_gfx940_op_V_ADD_U16,"V_ADD_U16"}, // 294 + {amdgpu_gfx940_op_V_SUB_U16,"V_SUB_U16"}, // 295 + {amdgpu_gfx940_op_V_SUBREV_U16,"V_SUBREV_U16"}, // 296 + {amdgpu_gfx940_op_V_MUL_LO_U16,"V_MUL_LO_U16"}, // 297 + {amdgpu_gfx940_op_V_LSHLREV_B16,"V_LSHLREV_B16"}, // 298 + {amdgpu_gfx940_op_V_LSHRREV_B16,"V_LSHRREV_B16"}, // 299 + {amdgpu_gfx940_op_V_ASHRREV_I16,"V_ASHRREV_I16"}, // 300 + {amdgpu_gfx940_op_V_MAX_F16,"V_MAX_F16"}, // 301 + {amdgpu_gfx940_op_V_MIN_F16,"V_MIN_F16"}, // 302 + {amdgpu_gfx940_op_V_MAX_U16,"V_MAX_U16"}, // 303 + {amdgpu_gfx940_op_V_MAX_I16,"V_MAX_I16"}, // 304 + {amdgpu_gfx940_op_V_MIN_U16,"V_MIN_U16"}, // 305 + {amdgpu_gfx940_op_V_MIN_I16,"V_MIN_I16"}, // 306 + {amdgpu_gfx940_op_V_LDEXP_F16,"V_LDEXP_F16"}, // 307 + {amdgpu_gfx940_op_V_ADD_U32,"V_ADD_U32"}, // 308 + {amdgpu_gfx940_op_V_SUB_U32,"V_SUB_U32"}, // 309 + {amdgpu_gfx940_op_V_SUBREV_U32,"V_SUBREV_U32"}, // 310 + {amdgpu_gfx940_op_V_DOT2C_F32_F16,"V_DOT2C_F32_F16"}, // 311 + {amdgpu_gfx940_op_V_DOT2C_I32_I16,"V_DOT2C_I32_I16"}, // 312 + {amdgpu_gfx940_op_V_DOT4C_I32_I8,"V_DOT4C_I32_I8"}, // 313 + {amdgpu_gfx940_op_V_DOT8C_I32_I4,"V_DOT8C_I32_I4"}, // 314 + {amdgpu_gfx940_op_V_FMAC_F32,"V_FMAC_F32"}, // 315 + {amdgpu_gfx940_op_V_PK_FMAC_F16,"V_PK_FMAC_F16"}, // 316 + {amdgpu_gfx940_op_V_XNOR_B32,"V_XNOR_B32"}, // 317 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 318 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 319 + {amdgpu_gfx940_op_V_NOP,"V_NOP"}, // 320 + {amdgpu_gfx940_op_V_MOV_B32,"V_MOV_B32"}, // 321 + {amdgpu_gfx940_op_V_READFIRSTLANE_B32,"V_READFIRSTLANE_B32"}, // 322 + {amdgpu_gfx940_op_V_CVT_I32_F64,"V_CVT_I32_F64"}, // 323 + {amdgpu_gfx940_op_V_CVT_F64_I32,"V_CVT_F64_I32"}, // 324 + {amdgpu_gfx940_op_V_CVT_F32_I32,"V_CVT_F32_I32"}, // 325 + {amdgpu_gfx940_op_V_CVT_F32_U32,"V_CVT_F32_U32"}, // 326 + {amdgpu_gfx940_op_V_CVT_U32_F32,"V_CVT_U32_F32"}, // 327 + {amdgpu_gfx940_op_V_CVT_I32_F32,"V_CVT_I32_F32"}, // 328 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 329 + {amdgpu_gfx940_op_V_CVT_F16_F32,"V_CVT_F16_F32"}, // 330 + {amdgpu_gfx940_op_V_CVT_F32_F16,"V_CVT_F32_F16"}, // 331 + {amdgpu_gfx940_op_V_CVT_RPI_I32_F32,"V_CVT_RPI_I32_F32"}, // 332 + {amdgpu_gfx940_op_V_CVT_FLR_I32_F32,"V_CVT_FLR_I32_F32"}, // 333 + {amdgpu_gfx940_op_V_CVT_OFF_F32_I4,"V_CVT_OFF_F32_I4"}, // 334 + {amdgpu_gfx940_op_V_CVT_F32_F64,"V_CVT_F32_F64"}, // 335 + {amdgpu_gfx940_op_V_CVT_F64_F32,"V_CVT_F64_F32"}, // 336 + {amdgpu_gfx940_op_V_CVT_F32_UBYTE0,"V_CVT_F32_UBYTE0"}, // 337 + {amdgpu_gfx940_op_V_CVT_F32_UBYTE1,"V_CVT_F32_UBYTE1"}, // 338 + {amdgpu_gfx940_op_V_CVT_F32_UBYTE2,"V_CVT_F32_UBYTE2"}, // 339 + {amdgpu_gfx940_op_V_CVT_F32_UBYTE3,"V_CVT_F32_UBYTE3"}, // 340 + {amdgpu_gfx940_op_V_CVT_U32_F64,"V_CVT_U32_F64"}, // 341 + {amdgpu_gfx940_op_V_CVT_F64_U32,"V_CVT_F64_U32"}, // 342 + {amdgpu_gfx940_op_V_TRUNC_F64,"V_TRUNC_F64"}, // 343 + {amdgpu_gfx940_op_V_CEIL_F64,"V_CEIL_F64"}, // 344 + {amdgpu_gfx940_op_V_RNDNE_F64,"V_RNDNE_F64"}, // 345 + {amdgpu_gfx940_op_V_FLOOR_F64,"V_FLOOR_F64"}, // 346 + {amdgpu_gfx940_op_V_FRACT_F32,"V_FRACT_F32"}, // 347 + {amdgpu_gfx940_op_V_TRUNC_F32,"V_TRUNC_F32"}, // 348 + {amdgpu_gfx940_op_V_CEIL_F32,"V_CEIL_F32"}, // 349 + {amdgpu_gfx940_op_V_RNDNE_F32,"V_RNDNE_F32"}, // 350 + {amdgpu_gfx940_op_V_FLOOR_F32,"V_FLOOR_F32"}, // 351 + {amdgpu_gfx940_op_V_EXP_F32,"V_EXP_F32"}, // 352 + {amdgpu_gfx940_op_V_LOG_F32,"V_LOG_F32"}, // 353 + {amdgpu_gfx940_op_V_RCP_F32,"V_RCP_F32"}, // 354 + {amdgpu_gfx940_op_V_RCP_IFLAG_F32,"V_RCP_IFLAG_F32"}, // 355 + {amdgpu_gfx940_op_V_RSQ_F32,"V_RSQ_F32"}, // 356 + {amdgpu_gfx940_op_V_RCP_F64,"V_RCP_F64"}, // 357 + {amdgpu_gfx940_op_V_RSQ_F64,"V_RSQ_F64"}, // 358 + {amdgpu_gfx940_op_V_SQRT_F32,"V_SQRT_F32"}, // 359 + {amdgpu_gfx940_op_V_SQRT_F64,"V_SQRT_F64"}, // 360 + {amdgpu_gfx940_op_V_SIN_F32,"V_SIN_F32"}, // 361 + {amdgpu_gfx940_op_V_COS_F32,"V_COS_F32"}, // 362 + {amdgpu_gfx940_op_V_NOT_B32,"V_NOT_B32"}, // 363 + {amdgpu_gfx940_op_V_BFREV_B32,"V_BFREV_B32"}, // 364 + {amdgpu_gfx940_op_V_FFBH_U32,"V_FFBH_U32"}, // 365 + {amdgpu_gfx940_op_V_FFBL_B32,"V_FFBL_B32"}, // 366 + {amdgpu_gfx940_op_V_FFBH_I32,"V_FFBH_I32"}, // 367 + {amdgpu_gfx940_op_V_FREXP_EXP_I32_F64,"V_FREXP_EXP_I32_F64"}, // 368 + {amdgpu_gfx940_op_V_FREXP_MANT_F64,"V_FREXP_MANT_F64"}, // 369 + {amdgpu_gfx940_op_V_FRACT_F64,"V_FRACT_F64"}, // 370 + {amdgpu_gfx940_op_V_FREXP_EXP_I32_F32,"V_FREXP_EXP_I32_F32"}, // 371 + {amdgpu_gfx940_op_V_FREXP_MANT_F32,"V_FREXP_MANT_F32"}, // 372 + {amdgpu_gfx940_op_V_CLREXCP,"V_CLREXCP"}, // 373 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 374 + {amdgpu_gfx940_op_V_SCREEN_PARTITION_4SE_B32,"V_SCREEN_PARTITION_4SE_B32"}, // 375 + {amdgpu_gfx940_op_V_MOV_B64,"V_MOV_B64"}, // 376 + {amdgpu_gfx940_op_V_CVT_F16_U16,"V_CVT_F16_U16"}, // 377 + {amdgpu_gfx940_op_V_CVT_F16_I16,"V_CVT_F16_I16"}, // 378 + {amdgpu_gfx940_op_V_CVT_U16_F16,"V_CVT_U16_F16"}, // 379 + {amdgpu_gfx940_op_V_CVT_I16_F16,"V_CVT_I16_F16"}, // 380 + {amdgpu_gfx940_op_V_RCP_F16,"V_RCP_F16"}, // 381 + {amdgpu_gfx940_op_V_SQRT_F16,"V_SQRT_F16"}, // 382 + {amdgpu_gfx940_op_V_RSQ_F16,"V_RSQ_F16"}, // 383 + {amdgpu_gfx940_op_V_LOG_F16,"V_LOG_F16"}, // 384 + {amdgpu_gfx940_op_V_EXP_F16,"V_EXP_F16"}, // 385 + {amdgpu_gfx940_op_V_FREXP_MANT_F16,"V_FREXP_MANT_F16"}, // 386 + {amdgpu_gfx940_op_V_FREXP_EXP_I16_F16,"V_FREXP_EXP_I16_F16"}, // 387 + {amdgpu_gfx940_op_V_FLOOR_F16,"V_FLOOR_F16"}, // 388 + {amdgpu_gfx940_op_V_CEIL_F16,"V_CEIL_F16"}, // 389 + {amdgpu_gfx940_op_V_TRUNC_F16,"V_TRUNC_F16"}, // 390 + {amdgpu_gfx940_op_V_RNDNE_F16,"V_RNDNE_F16"}, // 391 + {amdgpu_gfx940_op_V_FRACT_F16,"V_FRACT_F16"}, // 392 + {amdgpu_gfx940_op_V_SIN_F16,"V_SIN_F16"}, // 393 + {amdgpu_gfx940_op_V_COS_F16,"V_COS_F16"}, // 394 + {amdgpu_gfx940_op_V_EXP_LEGACY_F32,"V_EXP_LEGACY_F32"}, // 395 + {amdgpu_gfx940_op_V_LOG_LEGACY_F32,"V_LOG_LEGACY_F32"}, // 396 + {amdgpu_gfx940_op_V_CVT_NORM_I16_F16,"V_CVT_NORM_I16_F16"}, // 397 + {amdgpu_gfx940_op_V_CVT_NORM_U16_F16,"V_CVT_NORM_U16_F16"}, // 398 + {amdgpu_gfx940_op_V_SAT_PK_U8_I16,"V_SAT_PK_U8_I16"}, // 399 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 400 + {amdgpu_gfx940_op_V_SWAP_B32,"V_SWAP_B32"}, // 401 + {amdgpu_gfx940_op_V_ACCVGPR_MOV_B32,"V_ACCVGPR_MOV_B32"}, // 402 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 403 + {amdgpu_gfx940_op_V_CVT_F32_FP8,"V_CVT_F32_FP8"}, // 404 + {amdgpu_gfx940_op_V_CVT_F32_BF8,"V_CVT_F32_BF8"}, // 405 + {amdgpu_gfx940_op_V_CVT_PK_F32_FP8,"V_CVT_PK_F32_FP8"}, // 406 + {amdgpu_gfx940_op_V_CVT_PK_F32_BF8,"V_CVT_PK_F32_BF8"}, // 407 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 408 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 409 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 410 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 411 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 412 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 413 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 414 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 415 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 416 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 417 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 418 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 419 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 420 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 421 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 422 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 423 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 424 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 425 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 426 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 427 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 428 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 429 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 430 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 431 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 432 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 433 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 434 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 435 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 436 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 437 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 438 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 439 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 440 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 441 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 442 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 443 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 444 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 445 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 446 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 447 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 448 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 449 + {amdgpu_gfx940_op_V_MAD_I32_I24,"V_MAD_I32_I24"}, // 450 + {amdgpu_gfx940_op_V_MAD_U32_U24,"V_MAD_U32_U24"}, // 451 + {amdgpu_gfx940_op_V_CUBEID_F32,"V_CUBEID_F32"}, // 452 + {amdgpu_gfx940_op_V_CUBESC_F32,"V_CUBESC_F32"}, // 453 + {amdgpu_gfx940_op_V_CUBETC_F32,"V_CUBETC_F32"}, // 454 + {amdgpu_gfx940_op_V_CUBEMA_F32,"V_CUBEMA_F32"}, // 455 + {amdgpu_gfx940_op_V_BFE_U32,"V_BFE_U32"}, // 456 + {amdgpu_gfx940_op_V_BFE_I32,"V_BFE_I32"}, // 457 + {amdgpu_gfx940_op_V_BFI_B32,"V_BFI_B32"}, // 458 + {amdgpu_gfx940_op_V_FMA_F32,"V_FMA_F32"}, // 459 + {amdgpu_gfx940_op_V_FMA_F64,"V_FMA_F64"}, // 460 + {amdgpu_gfx940_op_V_LERP_U8,"V_LERP_U8"}, // 461 + {amdgpu_gfx940_op_V_ALIGNBIT_B32,"V_ALIGNBIT_B32"}, // 462 + {amdgpu_gfx940_op_V_ALIGNBYTE_B32,"V_ALIGNBYTE_B32"}, // 463 + {amdgpu_gfx940_op_V_MIN3_F32,"V_MIN3_F32"}, // 464 + {amdgpu_gfx940_op_V_MIN3_I32,"V_MIN3_I32"}, // 465 + {amdgpu_gfx940_op_V_MIN3_U32,"V_MIN3_U32"}, // 466 + {amdgpu_gfx940_op_V_MAX3_F32,"V_MAX3_F32"}, // 467 + {amdgpu_gfx940_op_V_MAX3_I32,"V_MAX3_I32"}, // 468 + {amdgpu_gfx940_op_V_MAX3_U32,"V_MAX3_U32"}, // 469 + {amdgpu_gfx940_op_V_MED3_F32,"V_MED3_F32"}, // 470 + {amdgpu_gfx940_op_V_MED3_I32,"V_MED3_I32"}, // 471 + {amdgpu_gfx940_op_V_MED3_U32,"V_MED3_U32"}, // 472 + {amdgpu_gfx940_op_V_SAD_U8,"V_SAD_U8"}, // 473 + {amdgpu_gfx940_op_V_SAD_HI_U8,"V_SAD_HI_U8"}, // 474 + {amdgpu_gfx940_op_V_SAD_U16,"V_SAD_U16"}, // 475 + {amdgpu_gfx940_op_V_SAD_U32,"V_SAD_U32"}, // 476 + {amdgpu_gfx940_op_V_CVT_PK_U8_F32,"V_CVT_PK_U8_F32"}, // 477 + {amdgpu_gfx940_op_V_DIV_FIXUP_F32,"V_DIV_FIXUP_F32"}, // 478 + {amdgpu_gfx940_op_V_DIV_FIXUP_F64,"V_DIV_FIXUP_F64"}, // 479 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 480 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 481 + {amdgpu_gfx940_op_V_DIV_FMAS_F32,"V_DIV_FMAS_F32"}, // 482 + {amdgpu_gfx940_op_V_DIV_FMAS_F64,"V_DIV_FMAS_F64"}, // 483 + {amdgpu_gfx940_op_V_MSAD_U8,"V_MSAD_U8"}, // 484 + {amdgpu_gfx940_op_V_QSAD_PK_U16_U8,"V_QSAD_PK_U16_U8"}, // 485 + {amdgpu_gfx940_op_V_MQSAD_PK_U16_U8,"V_MQSAD_PK_U16_U8"}, // 486 + {amdgpu_gfx940_op_V_MQSAD_U32_U8,"V_MQSAD_U32_U8"}, // 487 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 488 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 489 + {amdgpu_gfx940_op_V_MAD_LEGACY_F16,"V_MAD_LEGACY_F16"}, // 490 + {amdgpu_gfx940_op_V_MAD_LEGACY_U16,"V_MAD_LEGACY_U16"}, // 491 + {amdgpu_gfx940_op_V_MAD_LEGACY_I16,"V_MAD_LEGACY_I16"}, // 492 + {amdgpu_gfx940_op_V_PERM_B32,"V_PERM_B32"}, // 493 + {amdgpu_gfx940_op_V_FMA_LEGACY_F16,"V_FMA_LEGACY_F16"}, // 494 + {amdgpu_gfx940_op_V_DIV_FIXUP_LEGACY_F16,"V_DIV_FIXUP_LEGACY_F16"}, // 495 + {amdgpu_gfx940_op_V_CVT_PKACCUM_U8_F32,"V_CVT_PKACCUM_U8_F32"}, // 496 + {amdgpu_gfx940_op_V_MAD_U32_U16,"V_MAD_U32_U16"}, // 497 + {amdgpu_gfx940_op_V_MAD_I32_I16,"V_MAD_I32_I16"}, // 498 + {amdgpu_gfx940_op_V_XAD_U32,"V_XAD_U32"}, // 499 + {amdgpu_gfx940_op_V_MIN3_F16,"V_MIN3_F16"}, // 500 + {amdgpu_gfx940_op_V_MIN3_I16,"V_MIN3_I16"}, // 501 + {amdgpu_gfx940_op_V_MIN3_U16,"V_MIN3_U16"}, // 502 + {amdgpu_gfx940_op_V_MAX3_F16,"V_MAX3_F16"}, // 503 + {amdgpu_gfx940_op_V_MAX3_I16,"V_MAX3_I16"}, // 504 + {amdgpu_gfx940_op_V_MAX3_U16,"V_MAX3_U16"}, // 505 + {amdgpu_gfx940_op_V_MED3_F16,"V_MED3_F16"}, // 506 + {amdgpu_gfx940_op_V_MED3_I16,"V_MED3_I16"}, // 507 + {amdgpu_gfx940_op_V_MED3_U16,"V_MED3_U16"}, // 508 + {amdgpu_gfx940_op_V_LSHL_ADD_U32,"V_LSHL_ADD_U32"}, // 509 + {amdgpu_gfx940_op_V_ADD_LSHL_U32,"V_ADD_LSHL_U32"}, // 510 + {amdgpu_gfx940_op_V_ADD3_U32,"V_ADD3_U32"}, // 511 + {amdgpu_gfx940_op_V_LSHL_OR_B32,"V_LSHL_OR_B32"}, // 512 + {amdgpu_gfx940_op_V_AND_OR_B32,"V_AND_OR_B32"}, // 513 + {amdgpu_gfx940_op_V_OR3_B32,"V_OR3_B32"}, // 514 + {amdgpu_gfx940_op_V_MAD_F16,"V_MAD_F16"}, // 515 + {amdgpu_gfx940_op_V_MAD_U16,"V_MAD_U16"}, // 516 + {amdgpu_gfx940_op_V_MAD_I16,"V_MAD_I16"}, // 517 + {amdgpu_gfx940_op_V_FMA_F16,"V_FMA_F16"}, // 518 + {amdgpu_gfx940_op_V_DIV_FIXUP_F16,"V_DIV_FIXUP_F16"}, // 519 + {amdgpu_gfx940_op_V_LSHL_ADD_U64,"V_LSHL_ADD_U64"}, // 520 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 521 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 522 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 523 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 524 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 525 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 526 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 527 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 528 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 529 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 530 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 531 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 532 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 533 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 534 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 535 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 536 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 537 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 538 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 539 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 540 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 541 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 542 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 543 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 544 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 545 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 546 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 547 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 548 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 549 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 550 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 551 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 552 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 553 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 554 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 555 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 556 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 557 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 558 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 559 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 560 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 561 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 562 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 563 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 564 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 565 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 566 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 567 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 568 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 569 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 570 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 571 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 572 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 573 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 574 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 575 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 576 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 577 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 578 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 579 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 580 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 581 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 582 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 583 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 584 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 585 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 586 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 587 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 588 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 589 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 590 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 591 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 592 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 593 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 594 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 595 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 596 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 597 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 598 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 599 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 600 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 601 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 602 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 603 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 604 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 605 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 606 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 607 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 608 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 609 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 610 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 611 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 612 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 613 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 614 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 615 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 616 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 617 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 618 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 619 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 620 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 621 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 622 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 623 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 624 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 625 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 626 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 627 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 628 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 629 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 630 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 631 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 632 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 633 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 634 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 635 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 636 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 637 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 638 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 639 + {amdgpu_gfx940_op_V_ADD_F64,"V_ADD_F64"}, // 640 + {amdgpu_gfx940_op_V_MUL_F64,"V_MUL_F64"}, // 641 + {amdgpu_gfx940_op_V_MIN_F64,"V_MIN_F64"}, // 642 + {amdgpu_gfx940_op_V_MAX_F64,"V_MAX_F64"}, // 643 + {amdgpu_gfx940_op_V_LDEXP_F64,"V_LDEXP_F64"}, // 644 + {amdgpu_gfx940_op_V_MUL_LO_U32,"V_MUL_LO_U32"}, // 645 + {amdgpu_gfx940_op_V_MUL_HI_U32,"V_MUL_HI_U32"}, // 646 + {amdgpu_gfx940_op_V_MUL_HI_I32,"V_MUL_HI_I32"}, // 647 + {amdgpu_gfx940_op_V_LDEXP_F32,"V_LDEXP_F32"}, // 648 + {amdgpu_gfx940_op_V_READLANE_B32,"V_READLANE_B32"}, // 649 + {amdgpu_gfx940_op_V_WRITELANE_B32,"V_WRITELANE_B32"}, // 650 + {amdgpu_gfx940_op_V_BCNT_U32_B32,"V_BCNT_U32_B32"}, // 651 + {amdgpu_gfx940_op_V_MBCNT_LO_U32_B32,"V_MBCNT_LO_U32_B32"}, // 652 + {amdgpu_gfx940_op_V_MBCNT_HI_U32_B32,"V_MBCNT_HI_U32_B32"}, // 653 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 654 + {amdgpu_gfx940_op_V_LSHLREV_B64,"V_LSHLREV_B64"}, // 655 + {amdgpu_gfx940_op_V_LSHRREV_B64,"V_LSHRREV_B64"}, // 656 + {amdgpu_gfx940_op_V_ASHRREV_I64,"V_ASHRREV_I64"}, // 657 + {amdgpu_gfx940_op_V_TRIG_PREOP_F64,"V_TRIG_PREOP_F64"}, // 658 + {amdgpu_gfx940_op_V_BFM_B32,"V_BFM_B32"}, // 659 + {amdgpu_gfx940_op_V_CVT_PKNORM_I16_F32,"V_CVT_PKNORM_I16_F32"}, // 660 + {amdgpu_gfx940_op_V_CVT_PKNORM_U16_F32,"V_CVT_PKNORM_U16_F32"}, // 661 + {amdgpu_gfx940_op_V_CVT_PKRTZ_F16_F32,"V_CVT_PKRTZ_F16_F32"}, // 662 + {amdgpu_gfx940_op_V_CVT_PK_U16_U32,"V_CVT_PK_U16_U32"}, // 663 + {amdgpu_gfx940_op_V_CVT_PK_I16_I32,"V_CVT_PK_I16_I32"}, // 664 + {amdgpu_gfx940_op_V_CVT_PKNORM_I16_F16,"V_CVT_PKNORM_I16_F16"}, // 665 + {amdgpu_gfx940_op_V_CVT_PKNORM_U16_F16,"V_CVT_PKNORM_U16_F16"}, // 666 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 667 + {amdgpu_gfx940_op_V_ADD_I32,"V_ADD_I32"}, // 668 + {amdgpu_gfx940_op_V_SUB_I32,"V_SUB_I32"}, // 669 + {amdgpu_gfx940_op_V_ADD_I16,"V_ADD_I16"}, // 670 + {amdgpu_gfx940_op_V_SUB_I16,"V_SUB_I16"}, // 671 + {amdgpu_gfx940_op_V_PACK_B32_F16,"V_PACK_B32_F16"}, // 672 + {amdgpu_gfx940_op_V_MUL_LEGACY_F32,"V_MUL_LEGACY_F32"}, // 673 + {amdgpu_gfx940_op_V_CVT_PK_FP8_F32,"V_CVT_PK_FP8_F32"}, // 674 + {amdgpu_gfx940_op_V_CVT_PK_BF8_F32,"V_CVT_PK_BF8_F32"}, // 675 + {amdgpu_gfx940_op_V_CVT_SR_FP8_F32,"V_CVT_SR_FP8_F32"}, // 676 + {amdgpu_gfx940_op_V_CVT_SR_BF8_F32,"V_CVT_SR_BF8_F32"}, // 677 + }; // end ENC_VOP3_insn_table + const amdgpu_gfx940_insn_entry ENC_VOP2_insn_table[62] = + { + {amdgpu_gfx940_op_V_CNDMASK_B32,"V_CNDMASK_B32"}, // 0 + {amdgpu_gfx940_op_V_ADD_F32,"V_ADD_F32"}, // 1 + {amdgpu_gfx940_op_V_SUB_F32,"V_SUB_F32"}, // 2 + {amdgpu_gfx940_op_V_SUBREV_F32,"V_SUBREV_F32"}, // 3 + {amdgpu_gfx940_op_V_FMAC_F64,"V_FMAC_F64"}, // 4 + {amdgpu_gfx940_op_V_MUL_F32,"V_MUL_F32"}, // 5 + {amdgpu_gfx940_op_V_MUL_I32_I24,"V_MUL_I32_I24"}, // 6 + {amdgpu_gfx940_op_V_MUL_HI_I32_I24,"V_MUL_HI_I32_I24"}, // 7 + {amdgpu_gfx940_op_V_MUL_U32_U24,"V_MUL_U32_U24"}, // 8 + {amdgpu_gfx940_op_V_MUL_HI_U32_U24,"V_MUL_HI_U32_U24"}, // 9 + {amdgpu_gfx940_op_V_MIN_F32,"V_MIN_F32"}, // 10 + {amdgpu_gfx940_op_V_MAX_F32,"V_MAX_F32"}, // 11 + {amdgpu_gfx940_op_V_MIN_I32,"V_MIN_I32"}, // 12 + {amdgpu_gfx940_op_V_MAX_I32,"V_MAX_I32"}, // 13 + {amdgpu_gfx940_op_V_MIN_U32,"V_MIN_U32"}, // 14 + {amdgpu_gfx940_op_V_MAX_U32,"V_MAX_U32"}, // 15 + {amdgpu_gfx940_op_V_LSHRREV_B32,"V_LSHRREV_B32"}, // 16 + {amdgpu_gfx940_op_V_ASHRREV_I32,"V_ASHRREV_I32"}, // 17 + {amdgpu_gfx940_op_V_LSHLREV_B32,"V_LSHLREV_B32"}, // 18 + {amdgpu_gfx940_op_V_AND_B32,"V_AND_B32"}, // 19 + {amdgpu_gfx940_op_V_OR_B32,"V_OR_B32"}, // 20 + {amdgpu_gfx940_op_V_XOR_B32,"V_XOR_B32"}, // 21 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 22 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 23 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 24 + {amdgpu_gfx940_op_V_ADD_CO_U32,"V_ADD_CO_U32"}, // 25 + {amdgpu_gfx940_op_V_SUB_CO_U32,"V_SUB_CO_U32"}, // 26 + {amdgpu_gfx940_op_V_SUBREV_CO_U32,"V_SUBREV_CO_U32"}, // 27 + {amdgpu_gfx940_op_V_ADDC_CO_U32,"V_ADDC_CO_U32"}, // 28 + {amdgpu_gfx940_op_V_SUBB_CO_U32,"V_SUBB_CO_U32"}, // 29 + {amdgpu_gfx940_op_V_SUBBREV_CO_U32,"V_SUBBREV_CO_U32"}, // 30 + {amdgpu_gfx940_op_V_ADD_F16,"V_ADD_F16"}, // 31 + {amdgpu_gfx940_op_V_SUB_F16,"V_SUB_F16"}, // 32 + {amdgpu_gfx940_op_V_SUBREV_F16,"V_SUBREV_F16"}, // 33 + {amdgpu_gfx940_op_V_MUL_F16,"V_MUL_F16"}, // 34 + {amdgpu_gfx940_op_V_MAC_F16,"V_MAC_F16"}, // 35 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 36 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 37 + {amdgpu_gfx940_op_V_ADD_U16,"V_ADD_U16"}, // 38 + {amdgpu_gfx940_op_V_SUB_U16,"V_SUB_U16"}, // 39 + {amdgpu_gfx940_op_V_SUBREV_U16,"V_SUBREV_U16"}, // 40 + {amdgpu_gfx940_op_V_MUL_LO_U16,"V_MUL_LO_U16"}, // 41 + {amdgpu_gfx940_op_V_LSHLREV_B16,"V_LSHLREV_B16"}, // 42 + {amdgpu_gfx940_op_V_LSHRREV_B16,"V_LSHRREV_B16"}, // 43 + {amdgpu_gfx940_op_V_ASHRREV_I16,"V_ASHRREV_I16"}, // 44 + {amdgpu_gfx940_op_V_MAX_F16,"V_MAX_F16"}, // 45 + {amdgpu_gfx940_op_V_MIN_F16,"V_MIN_F16"}, // 46 + {amdgpu_gfx940_op_V_MAX_U16,"V_MAX_U16"}, // 47 + {amdgpu_gfx940_op_V_MAX_I16,"V_MAX_I16"}, // 48 + {amdgpu_gfx940_op_V_MIN_U16,"V_MIN_U16"}, // 49 + {amdgpu_gfx940_op_V_MIN_I16,"V_MIN_I16"}, // 50 + {amdgpu_gfx940_op_V_LDEXP_F16,"V_LDEXP_F16"}, // 51 + {amdgpu_gfx940_op_V_ADD_U32,"V_ADD_U32"}, // 52 + {amdgpu_gfx940_op_V_SUB_U32,"V_SUB_U32"}, // 53 + {amdgpu_gfx940_op_V_SUBREV_U32,"V_SUBREV_U32"}, // 54 + {amdgpu_gfx940_op_V_DOT2C_F32_F16,"V_DOT2C_F32_F16"}, // 55 + {amdgpu_gfx940_op_V_DOT2C_I32_I16,"V_DOT2C_I32_I16"}, // 56 + {amdgpu_gfx940_op_V_DOT4C_I32_I8,"V_DOT4C_I32_I8"}, // 57 + {amdgpu_gfx940_op_V_DOT8C_I32_I4,"V_DOT8C_I32_I4"}, // 58 + {amdgpu_gfx940_op_V_FMAC_F32,"V_FMAC_F32"}, // 59 + {amdgpu_gfx940_op_V_PK_FMAC_F16,"V_PK_FMAC_F16"}, // 60 + {amdgpu_gfx940_op_V_XNOR_B32,"V_XNOR_B32"}, // 61 + }; // end ENC_VOP2_insn_table + const amdgpu_gfx940_insn_entry ENC_VOP2_LITERAL_insn_table[38] = + { + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 0 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 1 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 2 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 3 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 4 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 5 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 6 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 7 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 8 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 9 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 10 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 11 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 12 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 13 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 14 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 15 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 16 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 17 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 18 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 19 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 20 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 21 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 22 + {amdgpu_gfx940_op_V_FMAMK_F32,"V_FMAMK_F32"}, // 23 + {amdgpu_gfx940_op_V_FMAAK_F32,"V_FMAAK_F32"}, // 24 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 25 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 26 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 27 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 28 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 29 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 30 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 31 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 32 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 33 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 34 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 35 + {amdgpu_gfx940_op_V_MADMK_F16,"V_MADMK_F16"}, // 36 + {amdgpu_gfx940_op_V_MADAK_F16,"V_MADAK_F16"}, // 37 + }; // end ENC_VOP2_LITERAL_insn_table + const amdgpu_gfx940_insn_entry ENC_VOP3B_insn_table[490] = + { + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 0 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 1 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 2 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 3 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 4 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 5 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 6 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 7 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 8 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 9 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 10 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 11 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 12 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 13 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 14 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 15 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 16 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 17 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 18 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 19 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 20 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 21 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 22 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 23 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 24 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 25 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 26 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 27 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 28 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 29 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 30 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 31 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 32 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 33 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 34 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 35 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 36 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 37 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 38 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 39 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 40 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 41 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 42 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 43 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 44 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 45 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 46 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 47 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 48 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 49 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 50 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 51 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 52 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 53 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 54 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 55 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 56 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 57 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 58 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 59 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 60 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 61 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 62 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 63 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 64 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 65 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 66 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 67 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 68 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 69 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 70 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 71 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 72 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 73 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 74 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 75 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 76 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 77 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 78 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 79 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 80 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 81 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 82 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 83 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 84 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 85 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 86 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 87 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 88 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 89 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 90 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 91 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 92 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 93 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 94 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 95 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 96 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 97 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 98 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 99 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 100 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 101 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 102 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 103 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 104 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 105 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 106 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 107 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 108 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 109 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 110 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 111 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 112 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 113 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 114 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 115 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 116 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 117 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 118 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 119 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 120 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 121 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 122 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 123 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 124 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 125 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 126 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 127 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 128 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 129 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 130 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 131 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 132 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 133 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 134 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 135 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 136 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 137 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 138 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 139 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 140 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 141 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 142 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 143 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 144 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 145 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 146 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 147 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 148 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 149 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 150 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 151 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 152 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 153 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 154 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 155 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 156 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 157 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 158 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 159 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 160 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 161 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 162 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 163 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 164 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 165 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 166 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 167 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 168 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 169 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 170 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 171 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 172 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 173 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 174 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 175 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 176 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 177 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 178 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 179 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 180 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 181 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 182 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 183 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 184 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 185 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 186 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 187 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 188 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 189 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 190 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 191 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 192 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 193 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 194 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 195 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 196 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 197 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 198 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 199 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 200 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 201 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 202 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 203 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 204 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 205 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 206 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 207 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 208 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 209 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 210 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 211 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 212 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 213 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 214 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 215 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 216 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 217 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 218 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 219 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 220 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 221 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 222 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 223 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 224 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 225 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 226 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 227 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 228 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 229 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 230 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 231 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 232 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 233 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 234 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 235 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 236 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 237 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 238 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 239 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 240 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 241 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 242 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 243 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 244 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 245 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 246 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 247 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 248 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 249 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 250 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 251 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 252 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 253 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 254 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 255 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 256 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 257 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 258 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 259 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 260 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 261 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 262 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 263 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 264 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 265 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 266 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 267 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 268 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 269 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 270 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 271 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 272 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 273 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 274 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 275 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 276 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 277 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 278 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 279 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 280 + {amdgpu_gfx940_op_V_ADD_CO_U32,"V_ADD_CO_U32"}, // 281 + {amdgpu_gfx940_op_V_SUB_CO_U32,"V_SUB_CO_U32"}, // 282 + {amdgpu_gfx940_op_V_SUBREV_CO_U32,"V_SUBREV_CO_U32"}, // 283 + {amdgpu_gfx940_op_V_ADDC_CO_U32,"V_ADDC_CO_U32"}, // 284 + {amdgpu_gfx940_op_V_SUBB_CO_U32,"V_SUBB_CO_U32"}, // 285 + {amdgpu_gfx940_op_V_SUBBREV_CO_U32,"V_SUBBREV_CO_U32"}, // 286 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 287 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 288 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 289 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 290 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 291 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 292 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 293 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 294 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 295 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 296 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 297 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 298 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 299 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 300 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 301 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 302 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 303 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 304 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 305 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 306 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 307 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 308 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 309 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 310 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 311 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 312 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 313 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 314 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 315 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 316 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 317 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 318 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 319 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 320 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 321 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 322 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 323 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 324 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 325 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 326 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 327 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 328 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 329 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 330 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 331 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 332 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 333 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 334 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 335 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 336 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 337 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 338 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 339 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 340 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 341 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 342 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 343 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 344 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 345 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 346 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 347 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 348 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 349 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 350 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 351 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 352 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 353 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 354 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 355 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 356 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 357 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 358 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 359 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 360 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 361 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 362 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 363 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 364 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 365 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 366 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 367 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 368 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 369 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 370 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 371 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 372 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 373 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 374 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 375 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 376 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 377 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 378 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 379 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 380 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 381 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 382 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 383 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 384 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 385 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 386 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 387 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 388 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 389 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 390 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 391 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 392 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 393 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 394 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 395 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 396 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 397 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 398 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 399 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 400 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 401 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 402 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 403 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 404 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 405 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 406 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 407 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 408 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 409 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 410 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 411 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 412 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 413 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 414 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 415 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 416 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 417 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 418 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 419 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 420 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 421 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 422 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 423 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 424 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 425 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 426 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 427 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 428 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 429 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 430 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 431 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 432 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 433 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 434 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 435 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 436 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 437 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 438 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 439 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 440 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 441 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 442 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 443 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 444 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 445 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 446 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 447 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 448 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 449 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 450 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 451 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 452 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 453 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 454 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 455 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 456 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 457 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 458 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 459 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 460 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 461 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 462 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 463 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 464 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 465 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 466 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 467 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 468 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 469 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 470 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 471 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 472 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 473 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 474 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 475 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 476 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 477 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 478 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 479 + {amdgpu_gfx940_op_V_DIV_SCALE_F32,"V_DIV_SCALE_F32"}, // 480 + {amdgpu_gfx940_op_V_DIV_SCALE_F64,"V_DIV_SCALE_F64"}, // 481 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 482 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 483 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 484 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 485 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 486 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 487 + {amdgpu_gfx940_op_V_MAD_U64_U32,"V_MAD_U64_U32"}, // 488 + {amdgpu_gfx940_op_V_MAD_I64_I32,"V_MAD_I64_I32"}, // 489 + }; // end ENC_VOP3B_insn_table + const amdgpu_gfx940_insn_entry ENC_VOP3P_insn_table[90] = + { + {amdgpu_gfx940_op_V_PK_MAD_I16,"V_PK_MAD_I16"}, // 0 + {amdgpu_gfx940_op_V_PK_MUL_LO_U16,"V_PK_MUL_LO_U16"}, // 1 + {amdgpu_gfx940_op_V_PK_ADD_I16,"V_PK_ADD_I16"}, // 2 + {amdgpu_gfx940_op_V_PK_SUB_I16,"V_PK_SUB_I16"}, // 3 + {amdgpu_gfx940_op_V_PK_LSHLREV_B16,"V_PK_LSHLREV_B16"}, // 4 + {amdgpu_gfx940_op_V_PK_LSHRREV_B16,"V_PK_LSHRREV_B16"}, // 5 + {amdgpu_gfx940_op_V_PK_ASHRREV_I16,"V_PK_ASHRREV_I16"}, // 6 + {amdgpu_gfx940_op_V_PK_MAX_I16,"V_PK_MAX_I16"}, // 7 + {amdgpu_gfx940_op_V_PK_MIN_I16,"V_PK_MIN_I16"}, // 8 + {amdgpu_gfx940_op_V_PK_MAD_U16,"V_PK_MAD_U16"}, // 9 + {amdgpu_gfx940_op_V_PK_ADD_U16,"V_PK_ADD_U16"}, // 10 + {amdgpu_gfx940_op_V_PK_SUB_U16,"V_PK_SUB_U16"}, // 11 + {amdgpu_gfx940_op_V_PK_MAX_U16,"V_PK_MAX_U16"}, // 12 + {amdgpu_gfx940_op_V_PK_MIN_U16,"V_PK_MIN_U16"}, // 13 + {amdgpu_gfx940_op_V_PK_FMA_F16,"V_PK_FMA_F16"}, // 14 + {amdgpu_gfx940_op_V_PK_ADD_F16,"V_PK_ADD_F16"}, // 15 + {amdgpu_gfx940_op_V_PK_MUL_F16,"V_PK_MUL_F16"}, // 16 + {amdgpu_gfx940_op_V_PK_MIN_F16,"V_PK_MIN_F16"}, // 17 + {amdgpu_gfx940_op_V_PK_MAX_F16,"V_PK_MAX_F16"}, // 18 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 19 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 20 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 21 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 22 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 23 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 24 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 25 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 26 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 27 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 28 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 29 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 30 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 31 + {amdgpu_gfx940_op_V_MAD_MIX_F32,"V_MAD_MIX_F32"}, // 32 + {amdgpu_gfx940_op_V_MAD_MIXLO_F16,"V_MAD_MIXLO_F16"}, // 33 + {amdgpu_gfx940_op_V_MAD_MIXHI_F16,"V_MAD_MIXHI_F16"}, // 34 + {amdgpu_gfx940_op_V_DOT2_F32_F16,"V_DOT2_F32_F16"}, // 35 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 36 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 37 + {amdgpu_gfx940_op_V_DOT2_I32_I16,"V_DOT2_I32_I16"}, // 38 + {amdgpu_gfx940_op_V_DOT2_U32_U16,"V_DOT2_U32_U16"}, // 39 + {amdgpu_gfx940_op_V_DOT4_I32_I8,"V_DOT4_I32_I8"}, // 40 + {amdgpu_gfx940_op_V_DOT4_U32_U8,"V_DOT4_U32_U8"}, // 41 + {amdgpu_gfx940_op_V_DOT8_I32_I4,"V_DOT8_I32_I4"}, // 42 + {amdgpu_gfx940_op_V_DOT8_U32_U4,"V_DOT8_U32_U4"}, // 43 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 44 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 45 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 46 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 47 + {amdgpu_gfx940_op_V_PK_FMA_F32,"V_PK_FMA_F32"}, // 48 + {amdgpu_gfx940_op_V_PK_MUL_F32,"V_PK_MUL_F32"}, // 49 + {amdgpu_gfx940_op_V_PK_ADD_F32,"V_PK_ADD_F32"}, // 50 + {amdgpu_gfx940_op_V_PK_MOV_B32,"V_PK_MOV_B32"}, // 51 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 52 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 53 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 54 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 55 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 56 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 57 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 58 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 59 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 60 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 61 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 62 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 63 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 64 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 65 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 66 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 67 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 68 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 69 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 70 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 71 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 72 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 73 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 74 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 75 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 76 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 77 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 78 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 79 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 80 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 81 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 82 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 83 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 84 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 85 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 86 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 87 + {amdgpu_gfx940_op_V_ACCVGPR_READ,"V_ACCVGPR_READ"}, // 88 + {amdgpu_gfx940_op_V_ACCVGPR_WRITE,"V_ACCVGPR_WRITE"}, // 89 + }; // end ENC_VOP3P_insn_table + const amdgpu_gfx940_insn_entry ENC_VOP3P_MFMA_insn_table[128] = + { + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 0 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 1 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 2 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 3 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 4 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 5 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 6 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 7 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 8 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 9 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 10 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 11 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 12 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 13 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 14 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 15 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 16 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 17 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 18 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 19 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 20 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 21 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 22 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 23 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 24 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 25 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 26 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 27 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 28 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 29 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 30 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 31 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 32 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 33 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 34 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 35 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 36 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 37 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 38 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 39 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 40 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 41 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 42 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 43 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 44 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 45 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 46 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 47 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 48 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 49 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 50 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 51 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 52 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 53 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 54 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 55 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 56 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 57 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 58 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 59 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 60 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 61 + {amdgpu_gfx940_op_V_MFMA_F32_16X16X8_XF32,"V_MFMA_F32_16X16X8_XF32"}, // 62 + {amdgpu_gfx940_op_V_MFMA_F32_32X32X4_XF32,"V_MFMA_F32_32X32X4_XF32"}, // 63 + {amdgpu_gfx940_op_V_MFMA_F32_32X32X1_2B_F32,"V_MFMA_F32_32X32X1_2B_F32"}, // 64 + {amdgpu_gfx940_op_V_MFMA_F32_16X16X1_4B_F32,"V_MFMA_F32_16X16X1_4B_F32"}, // 65 + {amdgpu_gfx940_op_V_MFMA_F32_4X4X1_16B_F32,"V_MFMA_F32_4X4X1_16B_F32"}, // 66 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 67 + {amdgpu_gfx940_op_V_MFMA_F32_32X32X2_F32,"V_MFMA_F32_32X32X2_F32"}, // 68 + {amdgpu_gfx940_op_V_MFMA_F32_16X16X4_F32,"V_MFMA_F32_16X16X4_F32"}, // 69 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 70 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 71 + {amdgpu_gfx940_op_V_MFMA_F32_32X32X4_2B_F16,"V_MFMA_F32_32X32X4_2B_F16"}, // 72 + {amdgpu_gfx940_op_V_MFMA_F32_16X16X4_4B_F16,"V_MFMA_F32_16X16X4_4B_F16"}, // 73 + {amdgpu_gfx940_op_V_MFMA_F32_4X4X4_16B_F16,"V_MFMA_F32_4X4X4_16B_F16"}, // 74 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 75 + {amdgpu_gfx940_op_V_MFMA_F32_32X32X8_F16,"V_MFMA_F32_32X32X8_F16"}, // 76 + {amdgpu_gfx940_op_V_MFMA_F32_16X16X16_F16,"V_MFMA_F32_16X16X16_F16"}, // 77 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 78 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 79 + {amdgpu_gfx940_op_V_MFMA_I32_32X32X4_2B_I8,"V_MFMA_I32_32X32X4_2B_I8"}, // 80 + {amdgpu_gfx940_op_V_MFMA_I32_16X16X4_4B_I8,"V_MFMA_I32_16X16X4_4B_I8"}, // 81 + {amdgpu_gfx940_op_V_MFMA_I32_4X4X4_16B_I8,"V_MFMA_I32_4X4X4_16B_I8"}, // 82 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 83 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 84 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 85 + {amdgpu_gfx940_op_V_MFMA_I32_32X32X16_I8,"V_MFMA_I32_32X32X16_I8"}, // 86 + {amdgpu_gfx940_op_V_MFMA_I32_16X16X32_I8,"V_MFMA_I32_16X16X32_I8"}, // 87 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 88 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 89 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 90 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 91 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 92 + {amdgpu_gfx940_op_V_MFMA_F32_32X32X4_2B_BF16,"V_MFMA_F32_32X32X4_2B_BF16"}, // 93 + {amdgpu_gfx940_op_V_MFMA_F32_16X16X4_4B_BF16,"V_MFMA_F32_16X16X4_4B_BF16"}, // 94 + {amdgpu_gfx940_op_V_MFMA_F32_4X4X4_16B_BF16,"V_MFMA_F32_4X4X4_16B_BF16"}, // 95 + {amdgpu_gfx940_op_V_MFMA_F32_32X32X8_BF16,"V_MFMA_F32_32X32X8_BF16"}, // 96 + {amdgpu_gfx940_op_V_MFMA_F32_16X16X16_BF16,"V_MFMA_F32_16X16X16_BF16"}, // 97 + {amdgpu_gfx940_op_V_SMFMAC_F32_16X16X32_F16,"V_SMFMAC_F32_16X16X32_F16"}, // 98 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 99 + {amdgpu_gfx940_op_V_SMFMAC_F32_32X32X16_F16,"V_SMFMAC_F32_32X32X16_F16"}, // 100 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 101 + {amdgpu_gfx940_op_V_SMFMAC_F32_16X16X32_BF16,"V_SMFMAC_F32_16X16X32_BF16"}, // 102 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 103 + {amdgpu_gfx940_op_V_SMFMAC_F32_32X32X16_BF16,"V_SMFMAC_F32_32X32X16_BF16"}, // 104 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 105 + {amdgpu_gfx940_op_V_SMFMAC_I32_16X16X64_I8,"V_SMFMAC_I32_16X16X64_I8"}, // 106 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 107 + {amdgpu_gfx940_op_V_SMFMAC_I32_32X32X32_I8,"V_SMFMAC_I32_32X32X32_I8"}, // 108 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 109 + {amdgpu_gfx940_op_V_MFMA_F64_16X16X4_F64,"V_MFMA_F64_16X16X4_F64"}, // 110 + {amdgpu_gfx940_op_V_MFMA_F64_4X4X4_4B_F64,"V_MFMA_F64_4X4X4_4B_F64"}, // 111 + {amdgpu_gfx940_op_V_MFMA_F32_16X16X32_BF8_BF8,"V_MFMA_F32_16X16X32_BF8_BF8"}, // 112 + {amdgpu_gfx940_op_V_MFMA_F32_16X16X32_BF8_FP8,"V_MFMA_F32_16X16X32_BF8_FP8"}, // 113 + {amdgpu_gfx940_op_V_MFMA_F32_16X16X32_FP8_BF8,"V_MFMA_F32_16X16X32_FP8_BF8"}, // 114 + {amdgpu_gfx940_op_V_MFMA_F32_16X16X32_FP8_FP8,"V_MFMA_F32_16X16X32_FP8_FP8"}, // 115 + {amdgpu_gfx940_op_V_MFMA_F32_32X32X16_BF8_BF8,"V_MFMA_F32_32X32X16_BF8_BF8"}, // 116 + {amdgpu_gfx940_op_V_MFMA_F32_32X32X16_BF8_FP8,"V_MFMA_F32_32X32X16_BF8_FP8"}, // 117 + {amdgpu_gfx940_op_V_MFMA_F32_32X32X16_FP8_BF8,"V_MFMA_F32_32X32X16_FP8_BF8"}, // 118 + {amdgpu_gfx940_op_V_MFMA_F32_32X32X16_FP8_FP8,"V_MFMA_F32_32X32X16_FP8_FP8"}, // 119 + {amdgpu_gfx940_op_V_SMFMAC_F32_16X16X64_BF8_BF8,"V_SMFMAC_F32_16X16X64_BF8_BF8"}, // 120 + {amdgpu_gfx940_op_V_SMFMAC_F32_16X16X64_BF8_FP8,"V_SMFMAC_F32_16X16X64_BF8_FP8"}, // 121 + {amdgpu_gfx940_op_V_SMFMAC_F32_16X16X64_FP8_BF8,"V_SMFMAC_F32_16X16X64_FP8_BF8"}, // 122 + {amdgpu_gfx940_op_V_SMFMAC_F32_16X16X64_FP8_FP8,"V_SMFMAC_F32_16X16X64_FP8_FP8"}, // 123 + {amdgpu_gfx940_op_V_SMFMAC_F32_32X32X32_BF8_BF8,"V_SMFMAC_F32_32X32X32_BF8_BF8"}, // 124 + {amdgpu_gfx940_op_V_SMFMAC_F32_32X32X32_BF8_FP8,"V_SMFMAC_F32_32X32X32_BF8_FP8"}, // 125 + {amdgpu_gfx940_op_V_SMFMAC_F32_32X32X32_FP8_BF8,"V_SMFMAC_F32_32X32X32_FP8_BF8"}, // 126 + {amdgpu_gfx940_op_V_SMFMAC_F32_32X32X32_FP8_FP8,"V_SMFMAC_F32_32X32X32_FP8_FP8"}, // 127 + }; // end ENC_VOP3P_MFMA_insn_table + const amdgpu_gfx940_insn_entry ENC_VOPC_insn_table[256] = + { + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 0 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 1 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 2 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 3 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 4 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 5 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 6 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 7 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 8 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 9 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 10 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 11 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 12 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 13 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 14 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 15 + {amdgpu_gfx940_op_V_CMP_CLASS_F32,"V_CMP_CLASS_F32"}, // 16 + {amdgpu_gfx940_op_V_CMPX_CLASS_F32,"V_CMPX_CLASS_F32"}, // 17 + {amdgpu_gfx940_op_V_CMP_CLASS_F64,"V_CMP_CLASS_F64"}, // 18 + {amdgpu_gfx940_op_V_CMPX_CLASS_F64,"V_CMPX_CLASS_F64"}, // 19 + {amdgpu_gfx940_op_V_CMP_CLASS_F16,"V_CMP_CLASS_F16"}, // 20 + {amdgpu_gfx940_op_V_CMPX_CLASS_F16,"V_CMPX_CLASS_F16"}, // 21 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 22 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 23 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 24 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 25 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 26 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 27 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 28 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 29 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 30 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 31 + {amdgpu_gfx940_op_V_CMP_F_F16,"V_CMP_F_F16"}, // 32 + {amdgpu_gfx940_op_V_CMP_LT_F16,"V_CMP_LT_F16"}, // 33 + {amdgpu_gfx940_op_V_CMP_EQ_F16,"V_CMP_EQ_F16"}, // 34 + {amdgpu_gfx940_op_V_CMP_LE_F16,"V_CMP_LE_F16"}, // 35 + {amdgpu_gfx940_op_V_CMP_GT_F16,"V_CMP_GT_F16"}, // 36 + {amdgpu_gfx940_op_V_CMP_LG_F16,"V_CMP_LG_F16"}, // 37 + {amdgpu_gfx940_op_V_CMP_GE_F16,"V_CMP_GE_F16"}, // 38 + {amdgpu_gfx940_op_V_CMP_O_F16,"V_CMP_O_F16"}, // 39 + {amdgpu_gfx940_op_V_CMP_U_F16,"V_CMP_U_F16"}, // 40 + {amdgpu_gfx940_op_V_CMP_NGE_F16,"V_CMP_NGE_F16"}, // 41 + {amdgpu_gfx940_op_V_CMP_NLG_F16,"V_CMP_NLG_F16"}, // 42 + {amdgpu_gfx940_op_V_CMP_NGT_F16,"V_CMP_NGT_F16"}, // 43 + {amdgpu_gfx940_op_V_CMP_NLE_F16,"V_CMP_NLE_F16"}, // 44 + {amdgpu_gfx940_op_V_CMP_NEQ_F16,"V_CMP_NEQ_F16"}, // 45 + {amdgpu_gfx940_op_V_CMP_NLT_F16,"V_CMP_NLT_F16"}, // 46 + {amdgpu_gfx940_op_V_CMP_TRU_F16,"V_CMP_TRU_F16"}, // 47 + {amdgpu_gfx940_op_V_CMPX_F_F16,"V_CMPX_F_F16"}, // 48 + {amdgpu_gfx940_op_V_CMPX_LT_F16,"V_CMPX_LT_F16"}, // 49 + {amdgpu_gfx940_op_V_CMPX_EQ_F16,"V_CMPX_EQ_F16"}, // 50 + {amdgpu_gfx940_op_V_CMPX_LE_F16,"V_CMPX_LE_F16"}, // 51 + {amdgpu_gfx940_op_V_CMPX_GT_F16,"V_CMPX_GT_F16"}, // 52 + {amdgpu_gfx940_op_V_CMPX_LG_F16,"V_CMPX_LG_F16"}, // 53 + {amdgpu_gfx940_op_V_CMPX_GE_F16,"V_CMPX_GE_F16"}, // 54 + {amdgpu_gfx940_op_V_CMPX_O_F16,"V_CMPX_O_F16"}, // 55 + {amdgpu_gfx940_op_V_CMPX_U_F16,"V_CMPX_U_F16"}, // 56 + {amdgpu_gfx940_op_V_CMPX_NGE_F16,"V_CMPX_NGE_F16"}, // 57 + {amdgpu_gfx940_op_V_CMPX_NLG_F16,"V_CMPX_NLG_F16"}, // 58 + {amdgpu_gfx940_op_V_CMPX_NGT_F16,"V_CMPX_NGT_F16"}, // 59 + {amdgpu_gfx940_op_V_CMPX_NLE_F16,"V_CMPX_NLE_F16"}, // 60 + {amdgpu_gfx940_op_V_CMPX_NEQ_F16,"V_CMPX_NEQ_F16"}, // 61 + {amdgpu_gfx940_op_V_CMPX_NLT_F16,"V_CMPX_NLT_F16"}, // 62 + {amdgpu_gfx940_op_V_CMPX_TRU_F16,"V_CMPX_TRU_F16"}, // 63 + {amdgpu_gfx940_op_V_CMP_F_F32,"V_CMP_F_F32"}, // 64 + {amdgpu_gfx940_op_V_CMP_LT_F32,"V_CMP_LT_F32"}, // 65 + {amdgpu_gfx940_op_V_CMP_EQ_F32,"V_CMP_EQ_F32"}, // 66 + {amdgpu_gfx940_op_V_CMP_LE_F32,"V_CMP_LE_F32"}, // 67 + {amdgpu_gfx940_op_V_CMP_GT_F32,"V_CMP_GT_F32"}, // 68 + {amdgpu_gfx940_op_V_CMP_LG_F32,"V_CMP_LG_F32"}, // 69 + {amdgpu_gfx940_op_V_CMP_GE_F32,"V_CMP_GE_F32"}, // 70 + {amdgpu_gfx940_op_V_CMP_O_F32,"V_CMP_O_F32"}, // 71 + {amdgpu_gfx940_op_V_CMP_U_F32,"V_CMP_U_F32"}, // 72 + {amdgpu_gfx940_op_V_CMP_NGE_F32,"V_CMP_NGE_F32"}, // 73 + {amdgpu_gfx940_op_V_CMP_NLG_F32,"V_CMP_NLG_F32"}, // 74 + {amdgpu_gfx940_op_V_CMP_NGT_F32,"V_CMP_NGT_F32"}, // 75 + {amdgpu_gfx940_op_V_CMP_NLE_F32,"V_CMP_NLE_F32"}, // 76 + {amdgpu_gfx940_op_V_CMP_NEQ_F32,"V_CMP_NEQ_F32"}, // 77 + {amdgpu_gfx940_op_V_CMP_NLT_F32,"V_CMP_NLT_F32"}, // 78 + {amdgpu_gfx940_op_V_CMP_TRU_F32,"V_CMP_TRU_F32"}, // 79 + {amdgpu_gfx940_op_V_CMPX_F_F32,"V_CMPX_F_F32"}, // 80 + {amdgpu_gfx940_op_V_CMPX_LT_F32,"V_CMPX_LT_F32"}, // 81 + {amdgpu_gfx940_op_V_CMPX_EQ_F32,"V_CMPX_EQ_F32"}, // 82 + {amdgpu_gfx940_op_V_CMPX_LE_F32,"V_CMPX_LE_F32"}, // 83 + {amdgpu_gfx940_op_V_CMPX_GT_F32,"V_CMPX_GT_F32"}, // 84 + {amdgpu_gfx940_op_V_CMPX_LG_F32,"V_CMPX_LG_F32"}, // 85 + {amdgpu_gfx940_op_V_CMPX_GE_F32,"V_CMPX_GE_F32"}, // 86 + {amdgpu_gfx940_op_V_CMPX_O_F32,"V_CMPX_O_F32"}, // 87 + {amdgpu_gfx940_op_V_CMPX_U_F32,"V_CMPX_U_F32"}, // 88 + {amdgpu_gfx940_op_V_CMPX_NGE_F32,"V_CMPX_NGE_F32"}, // 89 + {amdgpu_gfx940_op_V_CMPX_NLG_F32,"V_CMPX_NLG_F32"}, // 90 + {amdgpu_gfx940_op_V_CMPX_NGT_F32,"V_CMPX_NGT_F32"}, // 91 + {amdgpu_gfx940_op_V_CMPX_NLE_F32,"V_CMPX_NLE_F32"}, // 92 + {amdgpu_gfx940_op_V_CMPX_NEQ_F32,"V_CMPX_NEQ_F32"}, // 93 + {amdgpu_gfx940_op_V_CMPX_NLT_F32,"V_CMPX_NLT_F32"}, // 94 + {amdgpu_gfx940_op_V_CMPX_TRU_F32,"V_CMPX_TRU_F32"}, // 95 + {amdgpu_gfx940_op_V_CMP_F_F64,"V_CMP_F_F64"}, // 96 + {amdgpu_gfx940_op_V_CMP_LT_F64,"V_CMP_LT_F64"}, // 97 + {amdgpu_gfx940_op_V_CMP_EQ_F64,"V_CMP_EQ_F64"}, // 98 + {amdgpu_gfx940_op_V_CMP_LE_F64,"V_CMP_LE_F64"}, // 99 + {amdgpu_gfx940_op_V_CMP_GT_F64,"V_CMP_GT_F64"}, // 100 + {amdgpu_gfx940_op_V_CMP_LG_F64,"V_CMP_LG_F64"}, // 101 + {amdgpu_gfx940_op_V_CMP_GE_F64,"V_CMP_GE_F64"}, // 102 + {amdgpu_gfx940_op_V_CMP_O_F64,"V_CMP_O_F64"}, // 103 + {amdgpu_gfx940_op_V_CMP_U_F64,"V_CMP_U_F64"}, // 104 + {amdgpu_gfx940_op_V_CMP_NGE_F64,"V_CMP_NGE_F64"}, // 105 + {amdgpu_gfx940_op_V_CMP_NLG_F64,"V_CMP_NLG_F64"}, // 106 + {amdgpu_gfx940_op_V_CMP_NGT_F64,"V_CMP_NGT_F64"}, // 107 + {amdgpu_gfx940_op_V_CMP_NLE_F64,"V_CMP_NLE_F64"}, // 108 + {amdgpu_gfx940_op_V_CMP_NEQ_F64,"V_CMP_NEQ_F64"}, // 109 + {amdgpu_gfx940_op_V_CMP_NLT_F64,"V_CMP_NLT_F64"}, // 110 + {amdgpu_gfx940_op_V_CMP_TRU_F64,"V_CMP_TRU_F64"}, // 111 + {amdgpu_gfx940_op_V_CMPX_F_F64,"V_CMPX_F_F64"}, // 112 + {amdgpu_gfx940_op_V_CMPX_LT_F64,"V_CMPX_LT_F64"}, // 113 + {amdgpu_gfx940_op_V_CMPX_EQ_F64,"V_CMPX_EQ_F64"}, // 114 + {amdgpu_gfx940_op_V_CMPX_LE_F64,"V_CMPX_LE_F64"}, // 115 + {amdgpu_gfx940_op_V_CMPX_GT_F64,"V_CMPX_GT_F64"}, // 116 + {amdgpu_gfx940_op_V_CMPX_LG_F64,"V_CMPX_LG_F64"}, // 117 + {amdgpu_gfx940_op_V_CMPX_GE_F64,"V_CMPX_GE_F64"}, // 118 + {amdgpu_gfx940_op_V_CMPX_O_F64,"V_CMPX_O_F64"}, // 119 + {amdgpu_gfx940_op_V_CMPX_U_F64,"V_CMPX_U_F64"}, // 120 + {amdgpu_gfx940_op_V_CMPX_NGE_F64,"V_CMPX_NGE_F64"}, // 121 + {amdgpu_gfx940_op_V_CMPX_NLG_F64,"V_CMPX_NLG_F64"}, // 122 + {amdgpu_gfx940_op_V_CMPX_NGT_F64,"V_CMPX_NGT_F64"}, // 123 + {amdgpu_gfx940_op_V_CMPX_NLE_F64,"V_CMPX_NLE_F64"}, // 124 + {amdgpu_gfx940_op_V_CMPX_NEQ_F64,"V_CMPX_NEQ_F64"}, // 125 + {amdgpu_gfx940_op_V_CMPX_NLT_F64,"V_CMPX_NLT_F64"}, // 126 + {amdgpu_gfx940_op_V_CMPX_TRU_F64,"V_CMPX_TRU_F64"}, // 127 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 128 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 129 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 130 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 131 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 132 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 133 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 134 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 135 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 136 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 137 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 138 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 139 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 140 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 141 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 142 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 143 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 144 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 145 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 146 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 147 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 148 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 149 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 150 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 151 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 152 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 153 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 154 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 155 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 156 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 157 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 158 + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 159 + {amdgpu_gfx940_op_V_CMP_F_I16,"V_CMP_F_I16"}, // 160 + {amdgpu_gfx940_op_V_CMP_LT_I16,"V_CMP_LT_I16"}, // 161 + {amdgpu_gfx940_op_V_CMP_EQ_I16,"V_CMP_EQ_I16"}, // 162 + {amdgpu_gfx940_op_V_CMP_LE_I16,"V_CMP_LE_I16"}, // 163 + {amdgpu_gfx940_op_V_CMP_GT_I16,"V_CMP_GT_I16"}, // 164 + {amdgpu_gfx940_op_V_CMP_NE_I16,"V_CMP_NE_I16"}, // 165 + {amdgpu_gfx940_op_V_CMP_GE_I16,"V_CMP_GE_I16"}, // 166 + {amdgpu_gfx940_op_V_CMP_T_I16,"V_CMP_T_I16"}, // 167 + {amdgpu_gfx940_op_V_CMP_F_U16,"V_CMP_F_U16"}, // 168 + {amdgpu_gfx940_op_V_CMP_LT_U16,"V_CMP_LT_U16"}, // 169 + {amdgpu_gfx940_op_V_CMP_EQ_U16,"V_CMP_EQ_U16"}, // 170 + {amdgpu_gfx940_op_V_CMP_LE_U16,"V_CMP_LE_U16"}, // 171 + {amdgpu_gfx940_op_V_CMP_GT_U16,"V_CMP_GT_U16"}, // 172 + {amdgpu_gfx940_op_V_CMP_NE_U16,"V_CMP_NE_U16"}, // 173 + {amdgpu_gfx940_op_V_CMP_GE_U16,"V_CMP_GE_U16"}, // 174 + {amdgpu_gfx940_op_V_CMP_T_U16,"V_CMP_T_U16"}, // 175 + {amdgpu_gfx940_op_V_CMPX_F_I16,"V_CMPX_F_I16"}, // 176 + {amdgpu_gfx940_op_V_CMPX_LT_I16,"V_CMPX_LT_I16"}, // 177 + {amdgpu_gfx940_op_V_CMPX_EQ_I16,"V_CMPX_EQ_I16"}, // 178 + {amdgpu_gfx940_op_V_CMPX_LE_I16,"V_CMPX_LE_I16"}, // 179 + {amdgpu_gfx940_op_V_CMPX_GT_I16,"V_CMPX_GT_I16"}, // 180 + {amdgpu_gfx940_op_V_CMPX_NE_I16,"V_CMPX_NE_I16"}, // 181 + {amdgpu_gfx940_op_V_CMPX_GE_I16,"V_CMPX_GE_I16"}, // 182 + {amdgpu_gfx940_op_V_CMPX_T_I16,"V_CMPX_T_I16"}, // 183 + {amdgpu_gfx940_op_V_CMPX_F_U16,"V_CMPX_F_U16"}, // 184 + {amdgpu_gfx940_op_V_CMPX_LT_U16,"V_CMPX_LT_U16"}, // 185 + {amdgpu_gfx940_op_V_CMPX_EQ_U16,"V_CMPX_EQ_U16"}, // 186 + {amdgpu_gfx940_op_V_CMPX_LE_U16,"V_CMPX_LE_U16"}, // 187 + {amdgpu_gfx940_op_V_CMPX_GT_U16,"V_CMPX_GT_U16"}, // 188 + {amdgpu_gfx940_op_V_CMPX_NE_U16,"V_CMPX_NE_U16"}, // 189 + {amdgpu_gfx940_op_V_CMPX_GE_U16,"V_CMPX_GE_U16"}, // 190 + {amdgpu_gfx940_op_V_CMPX_T_U16,"V_CMPX_T_U16"}, // 191 + {amdgpu_gfx940_op_V_CMP_F_I32,"V_CMP_F_I32"}, // 192 + {amdgpu_gfx940_op_V_CMP_LT_I32,"V_CMP_LT_I32"}, // 193 + {amdgpu_gfx940_op_V_CMP_EQ_I32,"V_CMP_EQ_I32"}, // 194 + {amdgpu_gfx940_op_V_CMP_LE_I32,"V_CMP_LE_I32"}, // 195 + {amdgpu_gfx940_op_V_CMP_GT_I32,"V_CMP_GT_I32"}, // 196 + {amdgpu_gfx940_op_V_CMP_NE_I32,"V_CMP_NE_I32"}, // 197 + {amdgpu_gfx940_op_V_CMP_GE_I32,"V_CMP_GE_I32"}, // 198 + {amdgpu_gfx940_op_V_CMP_T_I32,"V_CMP_T_I32"}, // 199 + {amdgpu_gfx940_op_V_CMP_F_U32,"V_CMP_F_U32"}, // 200 + {amdgpu_gfx940_op_V_CMP_LT_U32,"V_CMP_LT_U32"}, // 201 + {amdgpu_gfx940_op_V_CMP_EQ_U32,"V_CMP_EQ_U32"}, // 202 + {amdgpu_gfx940_op_V_CMP_LE_U32,"V_CMP_LE_U32"}, // 203 + {amdgpu_gfx940_op_V_CMP_GT_U32,"V_CMP_GT_U32"}, // 204 + {amdgpu_gfx940_op_V_CMP_NE_U32,"V_CMP_NE_U32"}, // 205 + {amdgpu_gfx940_op_V_CMP_GE_U32,"V_CMP_GE_U32"}, // 206 + {amdgpu_gfx940_op_V_CMP_T_U32,"V_CMP_T_U32"}, // 207 + {amdgpu_gfx940_op_V_CMPX_F_I32,"V_CMPX_F_I32"}, // 208 + {amdgpu_gfx940_op_V_CMPX_LT_I32,"V_CMPX_LT_I32"}, // 209 + {amdgpu_gfx940_op_V_CMPX_EQ_I32,"V_CMPX_EQ_I32"}, // 210 + {amdgpu_gfx940_op_V_CMPX_LE_I32,"V_CMPX_LE_I32"}, // 211 + {amdgpu_gfx940_op_V_CMPX_GT_I32,"V_CMPX_GT_I32"}, // 212 + {amdgpu_gfx940_op_V_CMPX_NE_I32,"V_CMPX_NE_I32"}, // 213 + {amdgpu_gfx940_op_V_CMPX_GE_I32,"V_CMPX_GE_I32"}, // 214 + {amdgpu_gfx940_op_V_CMPX_T_I32,"V_CMPX_T_I32"}, // 215 + {amdgpu_gfx940_op_V_CMPX_F_U32,"V_CMPX_F_U32"}, // 216 + {amdgpu_gfx940_op_V_CMPX_LT_U32,"V_CMPX_LT_U32"}, // 217 + {amdgpu_gfx940_op_V_CMPX_EQ_U32,"V_CMPX_EQ_U32"}, // 218 + {amdgpu_gfx940_op_V_CMPX_LE_U32,"V_CMPX_LE_U32"}, // 219 + {amdgpu_gfx940_op_V_CMPX_GT_U32,"V_CMPX_GT_U32"}, // 220 + {amdgpu_gfx940_op_V_CMPX_NE_U32,"V_CMPX_NE_U32"}, // 221 + {amdgpu_gfx940_op_V_CMPX_GE_U32,"V_CMPX_GE_U32"}, // 222 + {amdgpu_gfx940_op_V_CMPX_T_U32,"V_CMPX_T_U32"}, // 223 + {amdgpu_gfx940_op_V_CMP_F_I64,"V_CMP_F_I64"}, // 224 + {amdgpu_gfx940_op_V_CMP_LT_I64,"V_CMP_LT_I64"}, // 225 + {amdgpu_gfx940_op_V_CMP_EQ_I64,"V_CMP_EQ_I64"}, // 226 + {amdgpu_gfx940_op_V_CMP_LE_I64,"V_CMP_LE_I64"}, // 227 + {amdgpu_gfx940_op_V_CMP_GT_I64,"V_CMP_GT_I64"}, // 228 + {amdgpu_gfx940_op_V_CMP_NE_I64,"V_CMP_NE_I64"}, // 229 + {amdgpu_gfx940_op_V_CMP_GE_I64,"V_CMP_GE_I64"}, // 230 + {amdgpu_gfx940_op_V_CMP_T_I64,"V_CMP_T_I64"}, // 231 + {amdgpu_gfx940_op_V_CMP_F_U64,"V_CMP_F_U64"}, // 232 + {amdgpu_gfx940_op_V_CMP_LT_U64,"V_CMP_LT_U64"}, // 233 + {amdgpu_gfx940_op_V_CMP_EQ_U64,"V_CMP_EQ_U64"}, // 234 + {amdgpu_gfx940_op_V_CMP_LE_U64,"V_CMP_LE_U64"}, // 235 + {amdgpu_gfx940_op_V_CMP_GT_U64,"V_CMP_GT_U64"}, // 236 + {amdgpu_gfx940_op_V_CMP_NE_U64,"V_CMP_NE_U64"}, // 237 + {amdgpu_gfx940_op_V_CMP_GE_U64,"V_CMP_GE_U64"}, // 238 + {amdgpu_gfx940_op_V_CMP_T_U64,"V_CMP_T_U64"}, // 239 + {amdgpu_gfx940_op_V_CMPX_F_I64,"V_CMPX_F_I64"}, // 240 + {amdgpu_gfx940_op_V_CMPX_LT_I64,"V_CMPX_LT_I64"}, // 241 + {amdgpu_gfx940_op_V_CMPX_EQ_I64,"V_CMPX_EQ_I64"}, // 242 + {amdgpu_gfx940_op_V_CMPX_LE_I64,"V_CMPX_LE_I64"}, // 243 + {amdgpu_gfx940_op_V_CMPX_GT_I64,"V_CMPX_GT_I64"}, // 244 + {amdgpu_gfx940_op_V_CMPX_NE_I64,"V_CMPX_NE_I64"}, // 245 + {amdgpu_gfx940_op_V_CMPX_GE_I64,"V_CMPX_GE_I64"}, // 246 + {amdgpu_gfx940_op_V_CMPX_T_I64,"V_CMPX_T_I64"}, // 247 + {amdgpu_gfx940_op_V_CMPX_F_U64,"V_CMPX_F_U64"}, // 248 + {amdgpu_gfx940_op_V_CMPX_LT_U64,"V_CMPX_LT_U64"}, // 249 + {amdgpu_gfx940_op_V_CMPX_EQ_U64,"V_CMPX_EQ_U64"}, // 250 + {amdgpu_gfx940_op_V_CMPX_LE_U64,"V_CMPX_LE_U64"}, // 251 + {amdgpu_gfx940_op_V_CMPX_GT_U64,"V_CMPX_GT_U64"}, // 252 + {amdgpu_gfx940_op_V_CMPX_NE_U64,"V_CMPX_NE_U64"}, // 253 + {amdgpu_gfx940_op_V_CMPX_GE_U64,"V_CMPX_GE_U64"}, // 254 + {amdgpu_gfx940_op_V_CMPX_T_U64,"V_CMPX_T_U64"}, // 255 + }; // end ENC_VOPC_insn_table + const amdgpu_gfx940_insn_entry ENC_VINTRP_insn_table[1] = + { + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 0 + }; // end ENC_VINTRP_insn_table + const amdgpu_gfx940_insn_entry ENC_MIMG_insn_table[1] = + { + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 0 + }; // end ENC_MIMG_insn_table + const amdgpu_gfx940_insn_entry SOPK_INST_LITERAL__insn_table[1] = + { + {amdgpu_gfx940_op_S_NOP,"S_NOP"}, // 0 + }; // end SOPK_INST_LITERAL__insn_table + + + }; + + } +} +#endif //INSTRUCTION_DECODER_GFX940_H diff --git a/instructionAPI/src/AMDGPU/gfx940/amdgpu_gfx940_decoder_impl.C b/instructionAPI/src/AMDGPU/gfx940/amdgpu_gfx940_decoder_impl.C new file mode 100644 index 0000000000..8fb9bfb246 --- /dev/null +++ b/instructionAPI/src/AMDGPU/gfx940/amdgpu_gfx940_decoder_impl.C @@ -0,0 +1,1348 @@ +#include "registers/AMDGPU/amdgpu_gfx940_regs.h" +#include "InstructionDecoder-amdgpu-gfx940.h" + +namespace Dyninst { +namespace InstructionAPI { + bool InstructionDecoder_amdgpu_gfx940::IS_ENC_SOP1(uint64_t I) + { + switch ( I & 0xff80ff00 ) { + case 0xbe800000: case 0xbe800100: case 0xbe800200: case 0xbe800300: + case 0xbe800400: case 0xbe800500: case 0xbe800600: case 0xbe800700: + case 0xbe800800: case 0xbe800900: case 0xbe800a00: case 0xbe800b00: + case 0xbe800c00: case 0xbe800d00: case 0xbe800e00: case 0xbe800f00: + case 0xbe801000: case 0xbe801100: case 0xbe801200: case 0xbe801300: + case 0xbe801400: case 0xbe801500: case 0xbe801600: case 0xbe801700: + case 0xbe801800: case 0xbe801900: case 0xbe801a00: case 0xbe801b00: + case 0xbe801c00: case 0xbe801d00: case 0xbe801e00: case 0xbe801f00: + case 0xbe802000: case 0xbe802100: case 0xbe802200: case 0xbe802300: + case 0xbe802400: case 0xbe802500: case 0xbe802600: case 0xbe802700: + case 0xbe802800: case 0xbe802900: case 0xbe802a00: case 0xbe802b00: + case 0xbe802c00: case 0xbe802d00: case 0xbe802e00: case 0xbe803000: + case 0xbe803200: case 0xbe803300: case 0xbe803400: case 0xbe803500: + case 0xbe803600: case 0xbe803700: + return true; + + default: + return false; + } + } + + bool InstructionDecoder_amdgpu_gfx940::IS_ENC_SOPC(uint64_t I) + { + switch ( I & 0xffff0000 ) { + case 0xbf000000: case 0xbf010000: case 0xbf020000: case 0xbf030000: + case 0xbf040000: case 0xbf050000: case 0xbf060000: case 0xbf070000: + case 0xbf080000: case 0xbf090000: case 0xbf0a0000: case 0xbf0b0000: + case 0xbf0c0000: case 0xbf0d0000: case 0xbf0e0000: case 0xbf0f0000: + case 0xbf100000: case 0xbf110000: case 0xbf120000: case 0xbf130000: + return true; + + default: + return false; + } + } + + bool InstructionDecoder_amdgpu_gfx940::IS_ENC_SOPP(uint64_t I) + { + switch ( I & 0xffff0000 ) { + case 0xbf800000: case 0xbf810000: case 0xbf820000: case 0xbf830000: + case 0xbf840000: case 0xbf850000: case 0xbf860000: case 0xbf870000: + case 0xbf880000: case 0xbf890000: case 0xbf8a0000: case 0xbf8b0000: + case 0xbf8c0000: case 0xbf8d0000: case 0xbf8e0000: case 0xbf8f0000: + case 0xbf900000: case 0xbf910000: case 0xbf920000: case 0xbf930000: + case 0xbf940000: case 0xbf950000: case 0xbf960000: case 0xbf970000: + case 0xbf980000: case 0xbf990000: case 0xbf9a0000: case 0xbf9b0000: + case 0xbf9c0000: case 0xbf9d0000: case 0xbf9e0000: case 0xbf9f0000: + return true; + + default: + return false; + } + } + + bool InstructionDecoder_amdgpu_gfx940::IS_ENC_SOPK(uint64_t I) + { + switch ( I & 0xff800000 ) { + case 0xb0000000: case 0xb0800000: case 0xb1000000: case 0xb1800000: + case 0xb2000000: case 0xb2800000: case 0xb3000000: case 0xb3800000: + case 0xb4000000: case 0xb4800000: case 0xb5000000: case 0xb5800000: + case 0xb6000000: case 0xb6800000: case 0xb7000000: case 0xb7800000: + case 0xb8000000: case 0xb8800000: case 0xb9000000: case 0xba800000: + return true; + + default: + return false; + } + } + + bool InstructionDecoder_amdgpu_gfx940::IS_ENC_SOP2(uint64_t I) + { + switch ( I & 0xff800000 ) { + case 0x80000000: case 0x80800000: case 0x81000000: case 0x81800000: + case 0x82000000: case 0x82800000: case 0x83000000: case 0x83800000: + case 0x84000000: case 0x84800000: case 0x85000000: case 0x85800000: + case 0x86000000: case 0x86800000: case 0x87000000: case 0x87800000: + case 0x88000000: case 0x88800000: case 0x89000000: case 0x89800000: + case 0x8a000000: case 0x8a800000: case 0x8b000000: case 0x8b800000: + case 0x8c000000: case 0x8c800000: case 0x8d000000: case 0x8d800000: + case 0x8e000000: case 0x8e800000: case 0x8f000000: case 0x8f800000: + case 0x90000000: case 0x90800000: case 0x91000000: case 0x91800000: + case 0x92000000: case 0x92800000: case 0x93000000: case 0x93800000: + case 0x94000000: case 0x94800000: case 0x95000000: case 0x95800000: + case 0x96000000: case 0x96800000: case 0x97000000: case 0x97800000: + case 0x98000000: case 0x98800000: case 0x99000000: case 0x99800000: + case 0x9a000000: + return true; + + default: + return false; + } + } + + bool InstructionDecoder_amdgpu_gfx940::IS_ENC_SMEM(uint64_t I) + { + switch ( I & 0xfffc0000 ) { + case 0xc0000000: case 0xc0040000: case 0xc0080000: case 0xc00c0000: + case 0xc0100000: case 0xc0140000: case 0xc0180000: case 0xc01c0000: + case 0xc0200000: case 0xc0240000: case 0xc0280000: case 0xc02c0000: + case 0xc0300000: case 0xc0400000: case 0xc0440000: case 0xc0480000: + case 0xc0540000: case 0xc0580000: case 0xc05c0000: case 0xc0600000: + case 0xc0640000: case 0xc0680000: case 0xc0800000: case 0xc0840000: + case 0xc0880000: case 0xc08c0000: case 0xc0900000: case 0xc0940000: + case 0xc0980000: case 0xc09c0000: case 0xc0a00000: case 0xc0a40000: + case 0xc1000000: case 0xc1040000: case 0xc1080000: case 0xc10c0000: + case 0xc1100000: case 0xc1140000: case 0xc1180000: case 0xc11c0000: + case 0xc1200000: case 0xc1240000: case 0xc1280000: case 0xc12c0000: + case 0xc1300000: case 0xc1800000: case 0xc1840000: case 0xc1880000: + case 0xc18c0000: case 0xc1900000: case 0xc1940000: case 0xc1980000: + case 0xc19c0000: case 0xc1a00000: case 0xc1a40000: case 0xc1a80000: + case 0xc1ac0000: case 0xc1b00000: case 0xc2000000: case 0xc2040000: + case 0xc2080000: case 0xc20c0000: case 0xc2100000: case 0xc2140000: + case 0xc2180000: case 0xc21c0000: case 0xc2200000: case 0xc2240000: + case 0xc2280000: case 0xc22c0000: case 0xc2300000: case 0xc2800000: + case 0xc2840000: case 0xc2880000: case 0xc28c0000: case 0xc2900000: + case 0xc2940000: case 0xc2980000: case 0xc29c0000: case 0xc2a00000: + case 0xc2a40000: case 0xc2a80000: case 0xc2ac0000: case 0xc2b00000: + return true; + + default: + return false; + } + } + + bool InstructionDecoder_amdgpu_gfx940::IS_ENC_VOP1(uint64_t I) + { + switch ( I & 0xfe01fe00 ) { + case 0x7e000000: case 0x7e000200: case 0x7e000400: case 0x7e000600: + case 0x7e000800: case 0x7e000a00: case 0x7e000c00: case 0x7e000e00: + case 0x7e001000: case 0x7e001400: case 0x7e001600: case 0x7e001800: + case 0x7e001a00: case 0x7e001c00: case 0x7e001e00: case 0x7e002000: + case 0x7e002200: case 0x7e002400: case 0x7e002600: case 0x7e002800: + case 0x7e002a00: case 0x7e002c00: case 0x7e002e00: case 0x7e003000: + case 0x7e003200: case 0x7e003400: case 0x7e003600: case 0x7e003800: + case 0x7e003a00: case 0x7e003c00: case 0x7e003e00: case 0x7e004000: + case 0x7e004200: case 0x7e004400: case 0x7e004600: case 0x7e004800: + case 0x7e004a00: case 0x7e004c00: case 0x7e004e00: case 0x7e005000: + case 0x7e005200: case 0x7e005400: case 0x7e005600: case 0x7e005800: + case 0x7e005a00: case 0x7e005c00: case 0x7e005e00: case 0x7e006000: + case 0x7e006200: case 0x7e006400: case 0x7e006600: case 0x7e006800: + case 0x7e006a00: case 0x7e006e00: case 0x7e007000: case 0x7e007200: + case 0x7e007400: case 0x7e007600: case 0x7e007800: case 0x7e007a00: + case 0x7e007c00: case 0x7e007e00: case 0x7e008000: case 0x7e008200: + case 0x7e008400: case 0x7e008600: case 0x7e008800: case 0x7e008a00: + case 0x7e008c00: case 0x7e008e00: case 0x7e009000: case 0x7e009200: + case 0x7e009400: case 0x7e009600: case 0x7e009800: case 0x7e009a00: + case 0x7e009c00: case 0x7e009e00: case 0x7e00a200: case 0x7e00a400: + case 0x7e00a800: case 0x7e00aa00: case 0x7e00ac00: case 0x7e00ae00: + return true; + + default: + return false; + } + } + + bool InstructionDecoder_amdgpu_gfx940::IS_ENC_VOPC(uint64_t I) + { + switch ( I & 0xfffe0000 ) { + case 0x7c200000: case 0x7c220000: case 0x7c240000: case 0x7c260000: + case 0x7c280000: case 0x7c2a0000: case 0x7c400000: case 0x7c420000: + case 0x7c440000: case 0x7c460000: case 0x7c480000: case 0x7c4a0000: + case 0x7c4c0000: case 0x7c4e0000: case 0x7c500000: case 0x7c520000: + case 0x7c540000: case 0x7c560000: case 0x7c580000: case 0x7c5a0000: + case 0x7c5c0000: case 0x7c5e0000: case 0x7c600000: case 0x7c620000: + case 0x7c640000: case 0x7c660000: case 0x7c680000: case 0x7c6a0000: + case 0x7c6c0000: case 0x7c6e0000: case 0x7c700000: case 0x7c720000: + case 0x7c740000: case 0x7c760000: case 0x7c780000: case 0x7c7a0000: + case 0x7c7c0000: case 0x7c7e0000: case 0x7c800000: case 0x7c820000: + case 0x7c840000: case 0x7c860000: case 0x7c880000: case 0x7c8a0000: + case 0x7c8c0000: case 0x7c8e0000: case 0x7c900000: case 0x7c920000: + case 0x7c940000: case 0x7c960000: case 0x7c980000: case 0x7c9a0000: + case 0x7c9c0000: case 0x7c9e0000: case 0x7ca00000: case 0x7ca20000: + case 0x7ca40000: case 0x7ca60000: case 0x7ca80000: case 0x7caa0000: + case 0x7cac0000: case 0x7cae0000: case 0x7cb00000: case 0x7cb20000: + case 0x7cb40000: case 0x7cb60000: case 0x7cb80000: case 0x7cba0000: + case 0x7cbc0000: case 0x7cbe0000: case 0x7cc00000: case 0x7cc20000: + case 0x7cc40000: case 0x7cc60000: case 0x7cc80000: case 0x7cca0000: + case 0x7ccc0000: case 0x7cce0000: case 0x7cd00000: case 0x7cd20000: + case 0x7cd40000: case 0x7cd60000: case 0x7cd80000: case 0x7cda0000: + case 0x7cdc0000: case 0x7cde0000: case 0x7ce00000: case 0x7ce20000: + case 0x7ce40000: case 0x7ce60000: case 0x7ce80000: case 0x7cea0000: + case 0x7cec0000: case 0x7cee0000: case 0x7cf00000: case 0x7cf20000: + case 0x7cf40000: case 0x7cf60000: case 0x7cf80000: case 0x7cfa0000: + case 0x7cfc0000: case 0x7cfe0000: case 0x7d400000: case 0x7d420000: + case 0x7d440000: case 0x7d460000: case 0x7d480000: case 0x7d4a0000: + case 0x7d4c0000: case 0x7d4e0000: case 0x7d500000: case 0x7d520000: + case 0x7d540000: case 0x7d560000: case 0x7d580000: case 0x7d5a0000: + case 0x7d5c0000: case 0x7d5e0000: case 0x7d600000: case 0x7d620000: + case 0x7d640000: case 0x7d660000: case 0x7d680000: case 0x7d6a0000: + case 0x7d6c0000: case 0x7d6e0000: case 0x7d700000: case 0x7d720000: + case 0x7d740000: case 0x7d760000: case 0x7d780000: case 0x7d7a0000: + case 0x7d7c0000: case 0x7d7e0000: case 0x7d800000: case 0x7d820000: + case 0x7d840000: case 0x7d860000: case 0x7d880000: case 0x7d8a0000: + case 0x7d8c0000: case 0x7d8e0000: case 0x7d900000: case 0x7d920000: + case 0x7d940000: case 0x7d960000: case 0x7d980000: case 0x7d9a0000: + case 0x7d9c0000: case 0x7d9e0000: case 0x7da00000: case 0x7da20000: + case 0x7da40000: case 0x7da60000: case 0x7da80000: case 0x7daa0000: + case 0x7dac0000: case 0x7dae0000: case 0x7db00000: case 0x7db20000: + case 0x7db40000: case 0x7db60000: case 0x7db80000: case 0x7dba0000: + case 0x7dbc0000: case 0x7dbe0000: case 0x7dc00000: case 0x7dc20000: + case 0x7dc40000: case 0x7dc60000: case 0x7dc80000: case 0x7dca0000: + case 0x7dcc0000: case 0x7dce0000: case 0x7dd00000: case 0x7dd20000: + case 0x7dd40000: case 0x7dd60000: case 0x7dd80000: case 0x7dda0000: + case 0x7ddc0000: case 0x7dde0000: case 0x7de00000: case 0x7de20000: + case 0x7de40000: case 0x7de60000: case 0x7de80000: case 0x7dea0000: + case 0x7dec0000: case 0x7dee0000: case 0x7df00000: case 0x7df20000: + case 0x7df40000: case 0x7df60000: case 0x7df80000: case 0x7dfa0000: + case 0x7dfc0000: case 0x7dfe0000: + return true; + + default: + return false; + } + } + + bool InstructionDecoder_amdgpu_gfx940::IS_ENC_VOP2(uint64_t I) + { + switch ( I & 0xfe000000 ) { + case 0x0: case 0x2000000: case 0x4000000: case 0x6000000: + case 0x8000000: case 0xa000000: case 0xc000000: case 0xe000000: + case 0x10000000: case 0x12000000: case 0x14000000: case 0x16000000: + case 0x18000000: case 0x1a000000: case 0x1c000000: case 0x1e000000: + case 0x20000000: case 0x22000000: case 0x24000000: case 0x26000000: + case 0x28000000: case 0x2a000000: case 0x32000000: case 0x34000000: + case 0x36000000: case 0x38000000: case 0x3a000000: case 0x3c000000: + case 0x3e000000: case 0x40000000: case 0x42000000: case 0x44000000: + case 0x46000000: case 0x4c000000: case 0x4e000000: case 0x50000000: + case 0x52000000: case 0x54000000: case 0x56000000: case 0x58000000: + case 0x5a000000: case 0x5c000000: case 0x5e000000: case 0x60000000: + case 0x62000000: case 0x64000000: case 0x66000000: case 0x68000000: + case 0x6a000000: case 0x6c000000: case 0x6e000000: case 0x70000000: + case 0x72000000: case 0x74000000: case 0x76000000: case 0x78000000: + case 0x7a000000: + return true; + + default: + return false; + } + } + + bool InstructionDecoder_amdgpu_gfx940::IS_ENC_VINTRP(uint64_t I) + { + switch ( I & 0xfc000000 ) { + default: + return false; + } + } + + bool InstructionDecoder_amdgpu_gfx940::IS_ENC_VOP3P(uint64_t I) + { + switch ( I & 0xffff0000 ) { + case 0xd3800000: case 0xd3810000: case 0xd3820000: case 0xd3830000: + case 0xd3840000: case 0xd3850000: case 0xd3860000: case 0xd3870000: + case 0xd3880000: case 0xd3890000: case 0xd38a0000: case 0xd38b0000: + case 0xd38c0000: case 0xd38d0000: case 0xd38e0000: case 0xd38f0000: + case 0xd3900000: case 0xd3910000: case 0xd3920000: case 0xd3a00000: + case 0xd3a10000: case 0xd3a20000: case 0xd3a30000: case 0xd3a60000: + case 0xd3a70000: case 0xd3a80000: case 0xd3a90000: case 0xd3aa0000: + case 0xd3ab0000: case 0xd3b00000: case 0xd3b10000: case 0xd3b20000: + case 0xd3b30000: case 0xd3d80000: case 0xd3d90000: + return true; + + default: + return false; + } + } + + bool InstructionDecoder_amdgpu_gfx940::IS_ENC_VOP3(uint64_t I) + { + switch ( I & 0xffff0000 ) { + case 0xd1400000: case 0xd1410000: case 0xd1420000: case 0xd1430000: + case 0xd1440000: case 0xd1450000: case 0xd1460000: case 0xd1470000: + case 0xd1480000: case 0xd14a0000: case 0xd14b0000: case 0xd14c0000: + case 0xd14d0000: case 0xd14e0000: case 0xd14f0000: case 0xd1500000: + case 0xd1510000: case 0xd1520000: case 0xd1530000: case 0xd1540000: + case 0xd1550000: case 0xd1560000: case 0xd1570000: case 0xd1580000: + case 0xd1590000: case 0xd15a0000: case 0xd15b0000: case 0xd15c0000: + case 0xd15d0000: case 0xd15e0000: case 0xd15f0000: case 0xd1600000: + case 0xd1610000: case 0xd1620000: case 0xd1630000: case 0xd1640000: + case 0xd1650000: case 0xd1660000: case 0xd1670000: case 0xd1680000: + case 0xd1690000: case 0xd16a0000: case 0xd16b0000: case 0xd16c0000: + case 0xd16d0000: case 0xd16e0000: case 0xd16f0000: case 0xd1700000: + case 0xd1710000: case 0xd1720000: case 0xd1730000: case 0xd1740000: + case 0xd1750000: case 0xd1770000: case 0xd1780000: case 0xd1790000: + case 0xd17a0000: case 0xd17b0000: case 0xd17c0000: case 0xd17d0000: + case 0xd17e0000: case 0xd17f0000: case 0xd1800000: case 0xd1810000: + case 0xd1820000: case 0xd1830000: case 0xd1840000: case 0xd1850000: + case 0xd1860000: case 0xd1870000: case 0xd1880000: case 0xd1890000: + case 0xd18a0000: case 0xd18b0000: case 0xd18c0000: case 0xd18d0000: + case 0xd18e0000: case 0xd18f0000: case 0xd1910000: case 0xd1920000: + case 0xd1940000: case 0xd1950000: case 0xd1960000: case 0xd1970000: + case 0xd1000000: case 0xd1010000: case 0xd1020000: case 0xd1030000: + case 0xd1040000: case 0xd1050000: case 0xd1060000: case 0xd1070000: + case 0xd1080000: case 0xd1090000: case 0xd10a0000: case 0xd10b0000: + case 0xd10c0000: case 0xd10d0000: case 0xd10e0000: case 0xd10f0000: + case 0xd1100000: case 0xd1110000: case 0xd1120000: case 0xd1130000: + case 0xd1140000: case 0xd1150000: case 0xd11f0000: case 0xd1200000: + case 0xd1210000: case 0xd1220000: case 0xd1230000: case 0xd1260000: + case 0xd1270000: case 0xd1280000: case 0xd1290000: case 0xd12a0000: + case 0xd12b0000: case 0xd12c0000: case 0xd12d0000: case 0xd12e0000: + case 0xd12f0000: case 0xd1300000: case 0xd1310000: case 0xd1320000: + case 0xd1330000: case 0xd1340000: case 0xd1350000: case 0xd1360000: + case 0xd1370000: case 0xd1380000: case 0xd1390000: case 0xd13a0000: + case 0xd13b0000: case 0xd13c0000: case 0xd13d0000: case 0xd1c20000: + case 0xd1c30000: case 0xd1c40000: case 0xd1c50000: case 0xd1c60000: + case 0xd1c70000: case 0xd1c80000: case 0xd1c90000: case 0xd1ca0000: + case 0xd1cb0000: case 0xd1cc0000: case 0xd1cd0000: case 0xd1ce0000: + case 0xd1cf0000: case 0xd1d00000: case 0xd1d10000: case 0xd1d20000: + case 0xd1d30000: case 0xd1d40000: case 0xd1d50000: case 0xd1d60000: + case 0xd1d70000: case 0xd1d80000: case 0xd1d90000: case 0xd1da0000: + case 0xd1db0000: case 0xd1dc0000: case 0xd1dd0000: case 0xd1de0000: + case 0xd1df0000: case 0xd1e20000: case 0xd1e30000: case 0xd1e40000: + case 0xd1e50000: case 0xd1e60000: case 0xd1e70000: case 0xd1ea0000: + case 0xd1eb0000: case 0xd1ec0000: case 0xd1ed0000: case 0xd1ee0000: + case 0xd1ef0000: case 0xd1f00000: case 0xd1f10000: case 0xd1f20000: + case 0xd1f30000: case 0xd1f40000: case 0xd1f50000: case 0xd1f60000: + case 0xd1f70000: case 0xd1f80000: case 0xd1f90000: case 0xd1fa0000: + case 0xd1fb0000: case 0xd1fc0000: case 0xd1fd0000: case 0xd1fe0000: + case 0xd1ff0000: case 0xd2000000: case 0xd2010000: case 0xd2020000: + case 0xd2030000: case 0xd2040000: case 0xd2050000: case 0xd2060000: + case 0xd2070000: case 0xd2080000: case 0xd2800000: case 0xd2810000: + case 0xd2820000: case 0xd2830000: case 0xd2840000: case 0xd2850000: + case 0xd2860000: case 0xd2870000: case 0xd2880000: case 0xd2890000: + case 0xd28a0000: case 0xd28b0000: case 0xd28c0000: case 0xd28d0000: + case 0xd28f0000: case 0xd2900000: case 0xd2910000: case 0xd2920000: + case 0xd2930000: case 0xd2940000: case 0xd2950000: case 0xd2960000: + case 0xd2970000: case 0xd2980000: case 0xd2990000: case 0xd29a0000: + case 0xd29c0000: case 0xd29d0000: case 0xd29e0000: case 0xd29f0000: + case 0xd2a00000: case 0xd2a10000: case 0xd2a20000: case 0xd2a30000: + case 0xd2a40000: case 0xd2a50000: case 0xd0100000: case 0xd0110000: + case 0xd0120000: case 0xd0130000: case 0xd0140000: case 0xd0150000: + case 0xd0200000: case 0xd0210000: case 0xd0220000: case 0xd0230000: + case 0xd0240000: case 0xd0250000: case 0xd0260000: case 0xd0270000: + case 0xd0280000: case 0xd0290000: case 0xd02a0000: case 0xd02b0000: + case 0xd02c0000: case 0xd02d0000: case 0xd02e0000: case 0xd02f0000: + case 0xd0300000: case 0xd0310000: case 0xd0320000: case 0xd0330000: + case 0xd0340000: case 0xd0350000: case 0xd0360000: case 0xd0370000: + case 0xd0380000: case 0xd0390000: case 0xd03a0000: case 0xd03b0000: + case 0xd03c0000: case 0xd03d0000: case 0xd03e0000: case 0xd03f0000: + case 0xd0400000: case 0xd0410000: case 0xd0420000: case 0xd0430000: + case 0xd0440000: case 0xd0450000: case 0xd0460000: case 0xd0470000: + case 0xd0480000: case 0xd0490000: case 0xd04a0000: case 0xd04b0000: + case 0xd04c0000: case 0xd04d0000: case 0xd04e0000: case 0xd04f0000: + case 0xd0500000: case 0xd0510000: case 0xd0520000: case 0xd0530000: + case 0xd0540000: case 0xd0550000: case 0xd0560000: case 0xd0570000: + case 0xd0580000: case 0xd0590000: case 0xd05a0000: case 0xd05b0000: + case 0xd05c0000: case 0xd05d0000: case 0xd05e0000: case 0xd05f0000: + case 0xd0600000: case 0xd0610000: case 0xd0620000: case 0xd0630000: + case 0xd0640000: case 0xd0650000: case 0xd0660000: case 0xd0670000: + case 0xd0680000: case 0xd0690000: case 0xd06a0000: case 0xd06b0000: + case 0xd06c0000: case 0xd06d0000: case 0xd06e0000: case 0xd06f0000: + case 0xd0700000: case 0xd0710000: case 0xd0720000: case 0xd0730000: + case 0xd0740000: case 0xd0750000: case 0xd0760000: case 0xd0770000: + case 0xd0780000: case 0xd0790000: case 0xd07a0000: case 0xd07b0000: + case 0xd07c0000: case 0xd07d0000: case 0xd07e0000: case 0xd07f0000: + case 0xd0a00000: case 0xd0a10000: case 0xd0a20000: case 0xd0a30000: + case 0xd0a40000: case 0xd0a50000: case 0xd0a60000: case 0xd0a70000: + case 0xd0a80000: case 0xd0a90000: case 0xd0aa0000: case 0xd0ab0000: + case 0xd0ac0000: case 0xd0ad0000: case 0xd0ae0000: case 0xd0af0000: + case 0xd0b00000: case 0xd0b10000: case 0xd0b20000: case 0xd0b30000: + case 0xd0b40000: case 0xd0b50000: case 0xd0b60000: case 0xd0b70000: + case 0xd0b80000: case 0xd0b90000: case 0xd0ba0000: case 0xd0bb0000: + case 0xd0bc0000: case 0xd0bd0000: case 0xd0be0000: case 0xd0bf0000: + case 0xd0c00000: case 0xd0c10000: case 0xd0c20000: case 0xd0c30000: + case 0xd0c40000: case 0xd0c50000: case 0xd0c60000: case 0xd0c70000: + case 0xd0c80000: case 0xd0c90000: case 0xd0ca0000: case 0xd0cb0000: + case 0xd0cc0000: case 0xd0cd0000: case 0xd0ce0000: case 0xd0cf0000: + case 0xd0d00000: case 0xd0d10000: case 0xd0d20000: case 0xd0d30000: + case 0xd0d40000: case 0xd0d50000: case 0xd0d60000: case 0xd0d70000: + case 0xd0d80000: case 0xd0d90000: case 0xd0da0000: case 0xd0db0000: + case 0xd0dc0000: case 0xd0dd0000: case 0xd0de0000: case 0xd0df0000: + case 0xd0e00000: case 0xd0e10000: case 0xd0e20000: case 0xd0e30000: + case 0xd0e40000: case 0xd0e50000: case 0xd0e60000: case 0xd0e70000: + case 0xd0e80000: case 0xd0e90000: case 0xd0ea0000: case 0xd0eb0000: + case 0xd0ec0000: case 0xd0ed0000: case 0xd0ee0000: case 0xd0ef0000: + case 0xd0f00000: case 0xd0f10000: case 0xd0f20000: case 0xd0f30000: + case 0xd0f40000: case 0xd0f50000: case 0xd0f60000: case 0xd0f70000: + case 0xd0f80000: case 0xd0f90000: case 0xd0fa0000: case 0xd0fb0000: + case 0xd0fc0000: case 0xd0fd0000: case 0xd0fe0000: case 0xd0ff0000: + return true; + + default: + return false; + } + } + + bool InstructionDecoder_amdgpu_gfx940::IS_ENC_DS(uint64_t I) + { + switch ( I & 0xfdfe0000 ) { + case 0xd8000000: case 0xd8020000: case 0xd8040000: case 0xd8060000: + case 0xd8080000: case 0xd80a0000: case 0xd80c0000: case 0xd80e0000: + case 0xd8100000: case 0xd8120000: case 0xd8140000: case 0xd8160000: + case 0xd8180000: case 0xd81a0000: case 0xd81c0000: case 0xd81e0000: + case 0xd8200000: case 0xd8220000: case 0xd8240000: case 0xd8260000: + case 0xd8280000: case 0xd82a0000: case 0xd82e0000: case 0xd8300000: + case 0xd83a0000: case 0xd83c0000: case 0xd83e0000: case 0xd8400000: + case 0xd8420000: case 0xd8440000: case 0xd8460000: case 0xd8480000: + case 0xd84a0000: case 0xd84c0000: case 0xd84e0000: case 0xd8500000: + case 0xd8520000: case 0xd8540000: case 0xd8560000: case 0xd8580000: + case 0xd85a0000: case 0xd85c0000: case 0xd85e0000: case 0xd8600000: + case 0xd8620000: case 0xd8640000: case 0xd8660000: case 0xd8680000: + case 0xd86a0000: case 0xd86c0000: case 0xd86e0000: case 0xd8700000: + case 0xd8720000: case 0xd8740000: case 0xd8760000: case 0xd8780000: + case 0xd87a0000: case 0xd87c0000: case 0xd87e0000: case 0xd8800000: + case 0xd8820000: case 0xd8840000: case 0xd8860000: case 0xd8880000: + case 0xd88a0000: case 0xd88c0000: case 0xd88e0000: case 0xd8900000: + case 0xd8920000: case 0xd8940000: case 0xd8960000: case 0xd8980000: + case 0xd89a0000: case 0xd89c0000: case 0xd89e0000: case 0xd8a00000: + case 0xd8a20000: case 0xd8a40000: case 0xd8a60000: case 0xd8a80000: + case 0xd8aa0000: case 0xd8ac0000: case 0xd8ae0000: case 0xd8b00000: + case 0xd8b20000: case 0xd8b40000: case 0xd8b60000: case 0xd8b80000: + case 0xd8c00000: case 0xd8c20000: case 0xd8c40000: case 0xd8c60000: + case 0xd8c80000: case 0xd8ca0000: case 0xd8cc0000: case 0xd8ce0000: + case 0xd8d00000: case 0xd8d20000: case 0xd8d40000: case 0xd8d60000: + case 0xd8d80000: case 0xd8da0000: case 0xd8dc0000: case 0xd8de0000: + case 0xd8e00000: case 0xd8e20000: case 0xd8e40000: case 0xd8e60000: + case 0xd8ec0000: case 0xd8ee0000: case 0xd8f00000: case 0xd8f80000: + case 0xd8fc0000: case 0xd9300000: case 0xd9320000: case 0xd9340000: + case 0xd9360000: case 0xd9380000: case 0xd93a0000: case 0xd96c0000: + case 0xd96e0000: case 0xd9700000: case 0xd97a0000: case 0xd97c0000: + case 0xd9bc0000: case 0xd9be0000: case 0xd9fc0000: case 0xd9fe0000: + return true; + + default: + return false; + } + } + + bool InstructionDecoder_amdgpu_gfx940::IS_ENC_MUBUF(uint64_t I) + { + switch ( I & 0xfdfc0000 ) { + case 0xe0000000: case 0xe0040000: case 0xe0080000: case 0xe00c0000: + case 0xe0100000: case 0xe0140000: case 0xe0180000: case 0xe01c0000: + case 0xe0200000: case 0xe0240000: case 0xe0280000: case 0xe02c0000: + case 0xe0300000: case 0xe0340000: case 0xe0380000: case 0xe03c0000: + case 0xe0400000: case 0xe0440000: case 0xe0480000: case 0xe04c0000: + case 0xe0500000: case 0xe0540000: case 0xe0580000: case 0xe05c0000: + case 0xe0600000: case 0xe0640000: case 0xe0680000: case 0xe06c0000: + case 0xe0700000: case 0xe0740000: case 0xe0780000: case 0xe07c0000: + case 0xe0800000: case 0xe0840000: case 0xe0880000: case 0xe08c0000: + case 0xe0900000: case 0xe0940000: case 0xe0980000: case 0xe09c0000: + case 0xe0a00000: case 0xe0a40000: case 0xe1000000: case 0xe1040000: + case 0xe1080000: case 0xe10c0000: case 0xe1100000: case 0xe1140000: + case 0xe1180000: case 0xe11c0000: case 0xe1200000: case 0xe1240000: + case 0xe1280000: case 0xe12c0000: case 0xe1300000: case 0xe1340000: + case 0xe1380000: case 0xe13c0000: case 0xe1400000: case 0xe1440000: + case 0xe1800000: case 0xe1840000: case 0xe1880000: case 0xe18c0000: + case 0xe1900000: case 0xe1940000: case 0xe1980000: case 0xe19c0000: + case 0xe1a00000: case 0xe1a40000: case 0xe1a80000: case 0xe1ac0000: + case 0xe1b00000: + return true; + + default: + return false; + } + } + + bool InstructionDecoder_amdgpu_gfx940::IS_ENC_MTBUF(uint64_t I) + { + switch ( I & 0xfc078000 ) { + case 0xe8000000: case 0xe8008000: case 0xe8010000: case 0xe8018000: + case 0xe8020000: case 0xe8028000: case 0xe8030000: case 0xe8038000: + case 0xe8040000: case 0xe8048000: case 0xe8050000: case 0xe8058000: + case 0xe8060000: case 0xe8068000: case 0xe8070000: case 0xe8078000: + return true; + + default: + return false; + } + } + + bool InstructionDecoder_amdgpu_gfx940::IS_ENC_MIMG(uint64_t I) + { + switch ( I & 0xfc000000 ) { + default: + return false; + } + } + + bool InstructionDecoder_amdgpu_gfx940::IS_ENC_FLAT(uint64_t I) + { + switch ( I & 0xfdfcc000 ) { + case 0xdc400000: case 0xdc440000: case 0xdc480000: case 0xdc4c0000: + case 0xdc500000: case 0xdc540000: case 0xdc580000: case 0xdc5c0000: + case 0xdc600000: case 0xdc640000: case 0xdc680000: case 0xdc6c0000: + case 0xdc700000: case 0xdc740000: case 0xdc780000: case 0xdc7c0000: + case 0xdc800000: case 0xdc840000: case 0xdc880000: case 0xdc8c0000: + case 0xdc900000: case 0xdc940000: case 0xdd000000: case 0xdd040000: + case 0xdd080000: case 0xdd0c0000: case 0xdd100000: case 0xdd140000: + case 0xdd180000: case 0xdd1c0000: case 0xdd200000: case 0xdd240000: + case 0xdd280000: case 0xdd2c0000: case 0xdd300000: case 0xdd340000: + case 0xdd380000: case 0xdd3c0000: case 0xdd400000: case 0xdd440000: + case 0xdd480000: case 0xdd800000: case 0xdd840000: case 0xdd880000: + case 0xdd8c0000: case 0xdd900000: case 0xdd940000: case 0xdd980000: + case 0xdd9c0000: case 0xdda00000: case 0xdda40000: case 0xdda80000: + case 0xddac0000: case 0xddb00000: + return true; + + default: + return false; + } + } + + bool InstructionDecoder_amdgpu_gfx940::IS_ENC_FLAT_GLBL(uint64_t I) + { + switch ( I & 0xfdfcc000 ) { + case 0xdc408000: case 0xdc448000: case 0xdc488000: case 0xdc4c8000: + case 0xdc508000: case 0xdc548000: case 0xdc588000: case 0xdc5c8000: + case 0xdc608000: case 0xdc648000: case 0xdc688000: case 0xdc6c8000: + case 0xdc708000: case 0xdc748000: case 0xdc788000: case 0xdc7c8000: + case 0xdc808000: case 0xdc848000: case 0xdc888000: case 0xdc8c8000: + case 0xdc908000: case 0xdc948000: case 0xdc988000: case 0xdc9c8000: + case 0xdca08000: case 0xdca48000: case 0xdca88000: case 0xdd008000: + case 0xdd048000: case 0xdd088000: case 0xdd0c8000: case 0xdd108000: + case 0xdd148000: case 0xdd188000: case 0xdd1c8000: case 0xdd208000: + case 0xdd248000: case 0xdd288000: case 0xdd2c8000: case 0xdd308000: + case 0xdd348000: case 0xdd388000: case 0xdd3c8000: case 0xdd408000: + case 0xdd448000: case 0xdd488000: case 0xdd808000: case 0xdd848000: + case 0xdd888000: case 0xdd8c8000: case 0xdd908000: case 0xdd948000: + case 0xdd988000: case 0xdd9c8000: case 0xdda08000: case 0xdda48000: + case 0xdda88000: case 0xddac8000: case 0xddb08000: + return true; + + default: + return false; + } + } + + bool InstructionDecoder_amdgpu_gfx940::IS_ENC_FLAT_SCRATCH(uint64_t I) + { + switch ( I & 0xfdfcc000 ) { + case 0xdc404000: case 0xdc444000: case 0xdc484000: case 0xdc4c4000: + case 0xdc504000: case 0xdc544000: case 0xdc584000: case 0xdc5c4000: + case 0xdc604000: case 0xdc644000: case 0xdc684000: case 0xdc6c4000: + case 0xdc704000: case 0xdc744000: case 0xdc784000: case 0xdc7c4000: + case 0xdc804000: case 0xdc844000: case 0xdc884000: case 0xdc8c4000: + case 0xdc904000: case 0xdc944000: case 0xdc984000: case 0xdc9c4000: + case 0xdca04000: case 0xdca44000: case 0xdca84000: + return true; + + default: + return false; + } + } + + bool InstructionDecoder_amdgpu_gfx940::IS_SOPK_INST_LITERAL_(uint64_t I) + { + switch ( I & 0xff800000 ) { + case 0xba000000: + return true; + + default: + return false; + } + } + + bool InstructionDecoder_amdgpu_gfx940::IS_ENC_VOP2_LITERAL(uint64_t I) + { + switch ( I & 0xfe000000 ) { + case 0x2e000000: case 0x30000000: case 0x48000000: case 0x4a000000: + return true; + + default: + return false; + } + } + + bool InstructionDecoder_amdgpu_gfx940::IS_ENC_VOP3B(uint64_t I) + { + switch ( I & 0xffff0000 ) { + case 0xd1190000: case 0xd11a0000: case 0xd11b0000: case 0xd11c0000: + case 0xd11d0000: case 0xd11e0000: case 0xd1e00000: case 0xd1e10000: + case 0xd1e80000: case 0xd1e90000: + return true; + + default: + return false; + } + } + + bool InstructionDecoder_amdgpu_gfx940::IS_ENC_VOP3P_MFMA(uint64_t I) + { + switch ( I & 0xffff0000 ) { + case 0xd3be0000: case 0xd3bf0000: case 0xd3c00000: case 0xd3c10000: + case 0xd3c20000: case 0xd3c40000: case 0xd3c50000: case 0xd3c80000: + case 0xd3c90000: case 0xd3ca0000: case 0xd3cc0000: case 0xd3cd0000: + case 0xd3d00000: case 0xd3d10000: case 0xd3d20000: case 0xd3d60000: + case 0xd3d70000: case 0xd3dd0000: case 0xd3de0000: case 0xd3df0000: + case 0xd3e00000: case 0xd3e10000: case 0xd3e20000: case 0xd3e40000: + case 0xd3e60000: case 0xd3e80000: case 0xd3ea0000: case 0xd3ec0000: + case 0xd3ee0000: case 0xd3ef0000: case 0xd3f00000: case 0xd3f10000: + case 0xd3f20000: case 0xd3f30000: case 0xd3f40000: case 0xd3f50000: + case 0xd3f60000: case 0xd3f70000: case 0xd3f80000: case 0xd3f90000: + case 0xd3fa0000: case 0xd3fb0000: case 0xd3fc0000: case 0xd3fd0000: + case 0xd3fe0000: case 0xd3ff0000: + return true; + + default: + return false; + } + } + + void InstructionDecoder_amdgpu_gfx940::decodeENC_SOP1() + { + insn_size = 4; + layout_ENC_SOP1 & layout = insn_layout.ENC_SOP1; + layout.ENCODING = longfield<23,31>(insn_long); + layout.OP = longfield<8,15>(insn_long); + layout.SDST = longfield<16,22>(insn_long); + layout.SSRC0 = longfield<0,7>(insn_long); + assert(isArrayIndexValid(ENC_SOP1_insn_table, layout.OP) && "Opcode over or underflow"); + const amdgpu_gfx940_insn_entry &insn_entry = ENC_SOP1_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_SOP1Operands(); + this->insn_in_progress->updateSize(insn_size + immLen); + this->insn_in_progress->updateMnemonic(std::string(insn_entry.mnemonic) + extension); + } + + void InstructionDecoder_amdgpu_gfx940::decodeENC_SOPC() + { + insn_size = 4; + layout_ENC_SOPC & layout = insn_layout.ENC_SOPC; + layout.ENCODING = longfield<23,31>(insn_long); + layout.OP = longfield<16,22>(insn_long); + layout.SSRC0 = longfield<0,7>(insn_long); + layout.SSRC1 = longfield<8,15>(insn_long); + assert(isArrayIndexValid(ENC_SOPC_insn_table, layout.OP) && "Opcode over or underflow"); + const amdgpu_gfx940_insn_entry &insn_entry = ENC_SOPC_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_SOPCOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); + this->insn_in_progress->updateMnemonic(std::string(insn_entry.mnemonic) + extension); + } + + void InstructionDecoder_amdgpu_gfx940::decodeENC_SOPP() + { + insn_size = 4; + layout_ENC_SOPP & layout = insn_layout.ENC_SOPP; + layout.ENCODING = longfield<23,31>(insn_long); + layout.OP = longfield<16,22>(insn_long); + layout.SIMM16 = longfield<0,15>(insn_long); + assert(isArrayIndexValid(ENC_SOPP_insn_table, layout.OP) && "Opcode over or underflow"); + const amdgpu_gfx940_insn_entry &insn_entry = ENC_SOPP_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_SOPPOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); + this->insn_in_progress->updateMnemonic(std::string(insn_entry.mnemonic) + extension); + } + + void InstructionDecoder_amdgpu_gfx940::decodeENC_SOPK() + { + insn_size = 4; + layout_ENC_SOPK & layout = insn_layout.ENC_SOPK; + layout.ENCODING = longfield<28,31>(insn_long); + layout.OP = longfield<23,27>(insn_long); + layout.SDST = longfield<16,22>(insn_long); + layout.SIMM16 = longfield<0,15>(insn_long); + assert(isArrayIndexValid(ENC_SOPK_insn_table, layout.OP) && "Opcode over or underflow"); + const amdgpu_gfx940_insn_entry &insn_entry = ENC_SOPK_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_SOPKOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); + this->insn_in_progress->updateMnemonic(std::string(insn_entry.mnemonic) + extension); + } + + void InstructionDecoder_amdgpu_gfx940::decodeENC_SOP2() + { + insn_size = 4; + layout_ENC_SOP2 & layout = insn_layout.ENC_SOP2; + layout.ENCODING = longfield<30,31>(insn_long); + layout.OP = longfield<23,29>(insn_long); + layout.SDST = longfield<16,22>(insn_long); + layout.SSRC0 = longfield<0,7>(insn_long); + layout.SSRC1 = longfield<8,15>(insn_long); + assert(isArrayIndexValid(ENC_SOP2_insn_table, layout.OP) && "Opcode over or underflow"); + const amdgpu_gfx940_insn_entry &insn_entry = ENC_SOP2_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_SOP2Operands(); + this->insn_in_progress->updateSize(insn_size + immLen); + this->insn_in_progress->updateMnemonic(std::string(insn_entry.mnemonic) + extension); + } + + void InstructionDecoder_amdgpu_gfx940::decodeENC_SMEM() + { + insn_size = 8; + layout_ENC_SMEM & layout = insn_layout.ENC_SMEM; + layout.ENCODING = longfield<26,31>(insn_long); + layout.GLC = longfield<16,16>(insn_long); + layout.IMM = longfield<17,17>(insn_long); + layout.NV = longfield<15,15>(insn_long); + layout.OFFSET = longfield<32,52>(insn_long); + layout.OP = longfield<18,25>(insn_long); + layout.SBASE = (longfield<0,5>(insn_long) << 1 ) | 0 ; + layout.SDATA = longfield<6,12>(insn_long); + layout.SOFFSET = longfield<57,63>(insn_long); + layout.SOFFSET_EN = longfield<14,14>(insn_long); + assert(isArrayIndexValid(ENC_SMEM_insn_table, layout.OP) && "Opcode over or underflow"); + const amdgpu_gfx940_insn_entry &insn_entry = ENC_SMEM_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_SMEMOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); + this->insn_in_progress->updateMnemonic(std::string(insn_entry.mnemonic) + extension); + } + + void InstructionDecoder_amdgpu_gfx940::decodeENC_VOP1() + { + insn_size = 4; + layout_ENC_VOP1 & layout = insn_layout.ENC_VOP1; + layout.ENCODING = longfield<25,31>(insn_long); + layout.OP = longfield<9,16>(insn_long); + layout.SRC0 = longfield<0,8>(insn_long); + layout.VDST = longfield<17,24>(insn_long); + assert(isArrayIndexValid(ENC_VOP1_insn_table, layout.OP) && "Opcode over or underflow"); + const amdgpu_gfx940_insn_entry &insn_entry = ENC_VOP1_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_VOP1Operands(); + this->insn_in_progress->updateSize(insn_size + immLen); + this->insn_in_progress->updateMnemonic(std::string(insn_entry.mnemonic) + extension); + } + + void InstructionDecoder_amdgpu_gfx940::decodeENC_VOPC() + { + insn_size = 4; + layout_ENC_VOPC & layout = insn_layout.ENC_VOPC; + layout.ENCODING = longfield<25,31>(insn_long); + layout.OP = longfield<17,24>(insn_long); + layout.SRC0 = longfield<0,8>(insn_long); + layout.VSRC1 = longfield<9,16>(insn_long); + assert(isArrayIndexValid(ENC_VOPC_insn_table, layout.OP) && "Opcode over or underflow"); + const amdgpu_gfx940_insn_entry &insn_entry = ENC_VOPC_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_VOPCOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); + this->insn_in_progress->updateMnemonic(std::string(insn_entry.mnemonic) + extension); + } + + void InstructionDecoder_amdgpu_gfx940::decodeENC_VOP2() + { + insn_size = 4; + layout_ENC_VOP2 & layout = insn_layout.ENC_VOP2; + layout.ENCODING = longfield<31,31>(insn_long); + layout.OP = longfield<25,30>(insn_long); + layout.SRC0 = longfield<0,8>(insn_long); + layout.VDST = longfield<17,24>(insn_long); + layout.VSRC1 = longfield<9,16>(insn_long); + assert(isArrayIndexValid(ENC_VOP2_insn_table, layout.OP) && "Opcode over or underflow"); + const amdgpu_gfx940_insn_entry &insn_entry = ENC_VOP2_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_VOP2Operands(); + this->insn_in_progress->updateSize(insn_size + immLen); + this->insn_in_progress->updateMnemonic(std::string(insn_entry.mnemonic) + extension); + } + + void InstructionDecoder_amdgpu_gfx940::decodeENC_VINTRP() + { + insn_size = 4; + layout_ENC_VINTRP & layout = insn_layout.ENC_VINTRP; + layout.ATTR = longfield<10,15>(insn_long); + layout.ATTRCHAN = longfield<8,9>(insn_long); + layout.ENCODING = longfield<26,31>(insn_long); + layout.OP = longfield<16,17>(insn_long); + layout.VDST = longfield<18,25>(insn_long); + layout.VSRC = longfield<0,7>(insn_long); + assert(isArrayIndexValid(ENC_VINTRP_insn_table, layout.OP) && "Opcode over or underflow"); + const amdgpu_gfx940_insn_entry &insn_entry = ENC_VINTRP_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_VINTRPOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); + this->insn_in_progress->updateMnemonic(std::string(insn_entry.mnemonic) + extension); + } + + void InstructionDecoder_amdgpu_gfx940::decodeENC_VOP3P() + { + insn_size = 8; + layout_ENC_VOP3P & layout = insn_layout.ENC_VOP3P; + layout.CLAMP = longfield<15,15>(insn_long); + layout.ENCODING = longfield<23,31>(insn_long); + layout.NEG = longfield<61,63>(insn_long); + layout.NEG_HI = longfield<8,10>(insn_long); + layout.OP = longfield<16,22>(insn_long); + layout.OP_SEL = longfield<11,13>(insn_long); + layout.OP_SEL_HI = longfield<59,60>(insn_long); + layout.OP_SEL_HI_2 = longfield<14,14>(insn_long); + layout.SRC0 = longfield<32,40>(insn_long); + layout.SRC1 = longfield<41,49>(insn_long); + layout.SRC2 = longfield<50,58>(insn_long); + layout.VDST = longfield<0,7>(insn_long); + assert(isArrayIndexValid(ENC_VOP3P_insn_table, layout.OP) && "Opcode over or underflow"); + const amdgpu_gfx940_insn_entry &insn_entry = ENC_VOP3P_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_VOP3POperands(); + this->insn_in_progress->updateSize(insn_size + immLen); + this->insn_in_progress->updateMnemonic(std::string(insn_entry.mnemonic) + extension); + } + + void InstructionDecoder_amdgpu_gfx940::decodeENC_VOP3() + { + insn_size = 8; + layout_ENC_VOP3 & layout = insn_layout.ENC_VOP3; + layout.ABS = longfield<8,10>(insn_long); + layout.CLAMP = longfield<15,15>(insn_long); + layout.ENCODING = longfield<26,31>(insn_long); + layout.NEG = longfield<61,63>(insn_long); + layout.OMOD = longfield<59,60>(insn_long); + layout.OP = longfield<16,25>(insn_long); + layout.OP_SEL = longfield<11,14>(insn_long); + layout.SRC0 = longfield<32,40>(insn_long); + layout.SRC1 = longfield<41,49>(insn_long); + layout.SRC2 = longfield<50,58>(insn_long); + layout.VDST = longfield<0,7>(insn_long); + assert(isArrayIndexValid(ENC_VOP3_insn_table, layout.OP) && "Opcode over or underflow"); + const amdgpu_gfx940_insn_entry &insn_entry = ENC_VOP3_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_VOP3Operands(); + this->insn_in_progress->updateSize(insn_size + immLen); + this->insn_in_progress->updateMnemonic(std::string(insn_entry.mnemonic) + extension); + } + + void InstructionDecoder_amdgpu_gfx940::decodeENC_DS() + { + insn_size = 8; + layout_ENC_DS & layout = insn_layout.ENC_DS; + layout.ACC = longfield<25,25>(insn_long); + layout.ADDR = longfield<32,39>(insn_long); + layout.DATA0 = longfield<40,47>(insn_long); + layout.DATA1 = longfield<48,55>(insn_long); + layout.ENCODING = longfield<26,31>(insn_long); + layout.GDS = longfield<16,16>(insn_long); + layout.OFFSET0 = longfield<0,7>(insn_long); + layout.OFFSET1 = longfield<8,15>(insn_long); + layout.OP = longfield<17,24>(insn_long); + layout.VDST = longfield<56,63>(insn_long); + assert(isArrayIndexValid(ENC_DS_insn_table, layout.OP) && "Opcode over or underflow"); + const amdgpu_gfx940_insn_entry &insn_entry = ENC_DS_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_DSOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); + this->insn_in_progress->updateMnemonic(std::string(insn_entry.mnemonic) + extension); + } + + void InstructionDecoder_amdgpu_gfx940::decodeENC_MUBUF() + { + insn_size = 8; + layout_ENC_MUBUF & layout = insn_layout.ENC_MUBUF; + layout.ACC = longfield<55,55>(insn_long); + layout.ENCODING = longfield<26,31>(insn_long); + layout.IDXEN = longfield<13,13>(insn_long); + layout.LDS = longfield<16,16>(insn_long); + layout.NT = longfield<17,17>(insn_long); + layout.OFFEN = longfield<12,12>(insn_long); + layout.OFFSET = longfield<0,11>(insn_long); + layout.OP = longfield<18,24>(insn_long); + layout.SC0 = longfield<14,14>(insn_long); + layout.SC1 = longfield<15,15>(insn_long); + layout.SOFFSET = longfield<56,63>(insn_long); + layout.SRSRC = (longfield<48,52>(insn_long) << 2 ) | 0 ; + layout.VADDR = longfield<32,39>(insn_long); + layout.VDATA = longfield<40,47>(insn_long); + assert(isArrayIndexValid(ENC_MUBUF_insn_table, layout.OP) && "Opcode over or underflow"); + const amdgpu_gfx940_insn_entry &insn_entry = ENC_MUBUF_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_MUBUFOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); + this->insn_in_progress->updateMnemonic(std::string(insn_entry.mnemonic) + extension); + } + + void InstructionDecoder_amdgpu_gfx940::decodeENC_MTBUF() + { + insn_size = 8; + layout_ENC_MTBUF & layout = insn_layout.ENC_MTBUF; + layout.ACC = longfield<55,55>(insn_long); + layout.DFMT = longfield<19,22>(insn_long); + layout.ENCODING = longfield<26,31>(insn_long); + layout.IDXEN = longfield<13,13>(insn_long); + layout.NFMT = longfield<23,25>(insn_long); + layout.NT = longfield<54,54>(insn_long); + layout.OFFEN = longfield<12,12>(insn_long); + layout.OFFSET = longfield<0,11>(insn_long); + layout.OP = longfield<15,18>(insn_long); + layout.SC0 = longfield<14,14>(insn_long); + layout.SC1 = longfield<53,53>(insn_long); + layout.SOFFSET = longfield<56,63>(insn_long); + layout.SRSRC = (longfield<48,52>(insn_long) << 2 ) | 0 ; + layout.VADDR = longfield<32,39>(insn_long); + layout.VDATA = longfield<40,47>(insn_long); + assert(isArrayIndexValid(ENC_MTBUF_insn_table, layout.OP) && "Opcode over or underflow"); + const amdgpu_gfx940_insn_entry &insn_entry = ENC_MTBUF_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_MTBUFOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); + this->insn_in_progress->updateMnemonic(std::string(insn_entry.mnemonic) + extension); + } + + void InstructionDecoder_amdgpu_gfx940::decodeENC_MIMG() + { + insn_size = 8; + layout_ENC_MIMG & layout = insn_layout.ENC_MIMG; + layout.A16 = longfield<15,15>(insn_long); + layout.ACC = longfield<16,16>(insn_long); + layout.D16 = longfield<63,63>(insn_long); + layout.DA = longfield<14,14>(insn_long); + layout.DMASK = longfield<8,11>(insn_long); + layout.ENCODING = longfield<26,31>(insn_long); + layout.LWE = longfield<17,17>(insn_long); + layout.NT = longfield<25,25>(insn_long); + layout.OP = longfield<18,24>(insn_long); + layout.OPM = longfield<0,0>(insn_long); + layout.SC0 = longfield<13,13>(insn_long); + layout.SC1 = longfield<7,7>(insn_long); + layout.SRSRC = (longfield<48,52>(insn_long) << 2 ) | 0 ; + layout.SSAMP = (longfield<53,57>(insn_long) << 2 ) | 0 ; + layout.UNORM = longfield<12,12>(insn_long); + layout.VADDR = longfield<32,39>(insn_long); + layout.VDATA = longfield<40,47>(insn_long); + assert(isArrayIndexValid(ENC_MIMG_insn_table, layout.OP) && "Opcode over or underflow"); + const amdgpu_gfx940_insn_entry &insn_entry = ENC_MIMG_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_MIMGOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); + this->insn_in_progress->updateMnemonic(std::string(insn_entry.mnemonic) + extension); + } + + void InstructionDecoder_amdgpu_gfx940::decodeENC_FLAT() + { + insn_size = 8; + layout_ENC_FLAT & layout = insn_layout.ENC_FLAT; + layout.ACC = longfield<55,55>(insn_long); + layout.ADDR = longfield<32,39>(insn_long); + layout.DATA = longfield<40,47>(insn_long); + layout.ENCODING = longfield<26,31>(insn_long); + layout.NT = longfield<17,17>(insn_long); + layout.OFFSET = longfield<0,11>(insn_long); + layout.OP = longfield<18,24>(insn_long); + layout.SADDR = longfield<48,54>(insn_long); + layout.SC0 = longfield<16,16>(insn_long); + layout.SC1 = longfield<25,25>(insn_long); + layout.SEG = longfield<14,15>(insn_long); + layout.SVE = longfield<13,13>(insn_long); + layout.VDST = longfield<56,63>(insn_long); + assert(isArrayIndexValid(ENC_FLAT_insn_table, layout.OP) && "Opcode over or underflow"); + const amdgpu_gfx940_insn_entry &insn_entry = ENC_FLAT_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_FLATOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); + this->insn_in_progress->updateMnemonic(std::string(insn_entry.mnemonic) + extension); + } + + void InstructionDecoder_amdgpu_gfx940::decodeENC_FLAT_GLBL() + { + insn_size = 8; + layout_ENC_FLAT_GLBL & layout = insn_layout.ENC_FLAT_GLBL; + layout.ACC = longfield<55,55>(insn_long); + layout.ADDR = longfield<32,39>(insn_long); + layout.DATA = longfield<40,47>(insn_long); + layout.ENCODING = longfield<26,31>(insn_long); + layout.NT = longfield<17,17>(insn_long); + layout.OFFSET = longfield<0,12>(insn_long); + layout.OP = longfield<18,24>(insn_long); + layout.SADDR = longfield<48,54>(insn_long); + layout.SC0 = longfield<16,16>(insn_long); + layout.SC1 = longfield<25,25>(insn_long); + layout.SEG = longfield<14,15>(insn_long); + layout.SVE = longfield<13,13>(insn_long); + layout.VDST = longfield<56,63>(insn_long); + assert(isArrayIndexValid(ENC_FLAT_GLBL_insn_table, layout.OP) && "Opcode over or underflow"); + const amdgpu_gfx940_insn_entry &insn_entry = ENC_FLAT_GLBL_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_FLAT_GLBLOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); + this->insn_in_progress->updateMnemonic(std::string(insn_entry.mnemonic) + extension); + } + + void InstructionDecoder_amdgpu_gfx940::decodeENC_FLAT_SCRATCH() + { + insn_size = 8; + layout_ENC_FLAT_SCRATCH & layout = insn_layout.ENC_FLAT_SCRATCH; + layout.ACC = longfield<55,55>(insn_long); + layout.ADDR = longfield<32,39>(insn_long); + layout.DATA = longfield<40,47>(insn_long); + layout.ENCODING = longfield<26,31>(insn_long); + layout.NT = longfield<17,17>(insn_long); + layout.OFFSET = longfield<0,12>(insn_long); + layout.OP = longfield<18,24>(insn_long); + layout.SADDR = longfield<48,54>(insn_long); + layout.SC0 = longfield<16,16>(insn_long); + layout.SC1 = longfield<25,25>(insn_long); + layout.SEG = longfield<14,15>(insn_long); + layout.SVE = longfield<13,13>(insn_long); + layout.VDST = longfield<56,63>(insn_long); + assert(isArrayIndexValid(ENC_FLAT_SCRATCH_insn_table, layout.OP) && "Opcode over or underflow"); + const amdgpu_gfx940_insn_entry &insn_entry = ENC_FLAT_SCRATCH_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_FLAT_SCRATCHOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); + this->insn_in_progress->updateMnemonic(std::string(insn_entry.mnemonic) + extension); + } + + void InstructionDecoder_amdgpu_gfx940::decodeSOPK_INST_LITERAL_() + { + insn_size = 8; + layout_SOPK_INST_LITERAL_ & layout = insn_layout.SOPK_INST_LITERAL_; + layout.ENCODING = longfield<28,31>(insn_long); + layout.OP = longfield<23,27>(insn_long); + layout.SDST = longfield<16,22>(insn_long); + layout.SIMM16 = longfield<0,15>(insn_long); + layout.SIMM32 = longfield<32,63>(insn_long); + assert(isArrayIndexValid(SOPK_INST_LITERAL__insn_table, layout.OP) && "Opcode over or underflow"); + const amdgpu_gfx940_insn_entry &insn_entry = SOPK_INST_LITERAL__insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeSOPK_INST_LITERAL_Operands(); + this->insn_in_progress->updateSize(insn_size + immLen); + this->insn_in_progress->updateMnemonic(std::string(insn_entry.mnemonic) + extension); + } + + void InstructionDecoder_amdgpu_gfx940::decodeENC_VOP2_LITERAL() + { + insn_size = 8; + layout_ENC_VOP2_LITERAL & layout = insn_layout.ENC_VOP2_LITERAL; + layout.ENCODING = longfield<31,31>(insn_long); + layout.OP = longfield<25,30>(insn_long); + layout.SIMM32 = longfield<32,63>(insn_long); + layout.SRC0 = longfield<0,8>(insn_long); + layout.VDST = longfield<17,24>(insn_long); + layout.VSRC1 = longfield<9,16>(insn_long); + assert(isArrayIndexValid(ENC_VOP2_LITERAL_insn_table, layout.OP) && "Opcode over or underflow"); + const amdgpu_gfx940_insn_entry &insn_entry = ENC_VOP2_LITERAL_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_VOP2_LITERALOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); + this->insn_in_progress->updateMnemonic(std::string(insn_entry.mnemonic) + extension); + } + + void InstructionDecoder_amdgpu_gfx940::decodeENC_VOP3B() + { + insn_size = 8; + layout_ENC_VOP3B & layout = insn_layout.ENC_VOP3B; + layout.CLAMP = longfield<15,15>(insn_long); + layout.ENCODING = longfield<26,31>(insn_long); + layout.NEG = longfield<61,63>(insn_long); + layout.OMOD = longfield<59,60>(insn_long); + layout.OP = longfield<16,25>(insn_long); + layout.SDST = longfield<8,14>(insn_long); + layout.SRC0 = longfield<32,40>(insn_long); + layout.SRC1 = longfield<41,49>(insn_long); + layout.SRC2 = longfield<50,58>(insn_long); + layout.VDST = longfield<0,7>(insn_long); + assert(isArrayIndexValid(ENC_VOP3B_insn_table, layout.OP) && "Opcode over or underflow"); + const amdgpu_gfx940_insn_entry &insn_entry = ENC_VOP3B_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_VOP3BOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); + this->insn_in_progress->updateMnemonic(std::string(insn_entry.mnemonic) + extension); + } + + void InstructionDecoder_amdgpu_gfx940::decodeENC_VOP3P_MFMA() + { + insn_size = 8; + layout_ENC_VOP3P_MFMA & layout = insn_layout.ENC_VOP3P_MFMA; + layout.ABID = longfield<11,14>(insn_long); + layout.ACC = longfield<59,60>(insn_long); + layout.ACC_CD = longfield<15,15>(insn_long); + layout.BLGP = longfield<61,63>(insn_long); + layout.CBSZ = longfield<8,10>(insn_long); + layout.ENCODING = longfield<23,31>(insn_long); + layout.OP = longfield<16,22>(insn_long); + layout.SRC0 = longfield<32,40>(insn_long); + layout.SRC1 = longfield<41,49>(insn_long); + layout.SRC2 = longfield<50,58>(insn_long); + layout.VDST = longfield<0,7>(insn_long); + assert(isArrayIndexValid(ENC_VOP3P_MFMA_insn_table, layout.OP) && "Opcode over or underflow"); + const amdgpu_gfx940_insn_entry &insn_entry = ENC_VOP3P_MFMA_insn_table[layout.OP]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + finalizeENC_VOP3P_MFMAOperands(); + this->insn_in_progress->updateSize(insn_size + immLen); + this->insn_in_progress->updateMnemonic(std::string(insn_entry.mnemonic) + extension); + } + + void InstructionDecoder_amdgpu_gfx940::mainDecodeOpcode() + { + if (IS_ENC_SOP1(insn_long)) { + insn_size = 4; + uint32_t op_value = longfield<8,15>(insn_long); + assert(isArrayIndexValid(ENC_SOP1_insn_table, op_value) && "Opcode over or underflow"); + const amdgpu_gfx940_insn_entry &insn_entry = ENC_SOP1_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_SOP1; + } + else if (IS_ENC_SOPC(insn_long)) { + insn_size = 4; + uint32_t op_value = longfield<16,22>(insn_long); + assert(isArrayIndexValid(ENC_SOPC_insn_table, op_value) && "Opcode over or underflow"); + const amdgpu_gfx940_insn_entry &insn_entry = ENC_SOPC_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_SOPC; + } + else if (IS_ENC_SOPP(insn_long)) { + insn_size = 4; + uint32_t op_value = longfield<16,22>(insn_long); + assert(isArrayIndexValid(ENC_SOPP_insn_table, op_value) && "Opcode over or underflow"); + const amdgpu_gfx940_insn_entry &insn_entry = ENC_SOPP_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_SOPP; + } + else if (IS_ENC_SOPK(insn_long)) { + insn_size = 4; + uint32_t op_value = longfield<23,27>(insn_long); + assert(isArrayIndexValid(ENC_SOPK_insn_table, op_value) && "Opcode over or underflow"); + const amdgpu_gfx940_insn_entry &insn_entry = ENC_SOPK_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_SOPK; + } + else if (IS_ENC_SOP2(insn_long)) { + insn_size = 4; + uint32_t op_value = longfield<23,29>(insn_long); + assert(isArrayIndexValid(ENC_SOP2_insn_table, op_value) && "Opcode over or underflow"); + const amdgpu_gfx940_insn_entry &insn_entry = ENC_SOP2_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_SOP2; + } + else if (IS_ENC_SMEM(insn_long)) { + insn_size = 8; + uint32_t op_value = longfield<18,25>(insn_long); + assert(isArrayIndexValid(ENC_SMEM_insn_table, op_value) && "Opcode over or underflow"); + const amdgpu_gfx940_insn_entry &insn_entry = ENC_SMEM_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_SMEM; + } + else if (IS_ENC_VOP1(insn_long)) { + insn_size = 4; + uint32_t op_value = longfield<9,16>(insn_long); + assert(isArrayIndexValid(ENC_VOP1_insn_table, op_value) && "Opcode over or underflow"); + const amdgpu_gfx940_insn_entry &insn_entry = ENC_VOP1_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_VOP1; + } + else if (IS_ENC_VOPC(insn_long)) { + insn_size = 4; + uint32_t op_value = longfield<17,24>(insn_long); + assert(isArrayIndexValid(ENC_VOPC_insn_table, op_value) && "Opcode over or underflow"); + const amdgpu_gfx940_insn_entry &insn_entry = ENC_VOPC_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_VOPC; + } + else if (IS_ENC_VOP2(insn_long)) { + insn_size = 4; + uint32_t op_value = longfield<25,30>(insn_long); + assert(isArrayIndexValid(ENC_VOP2_insn_table, op_value) && "Opcode over or underflow"); + const amdgpu_gfx940_insn_entry &insn_entry = ENC_VOP2_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_VOP2; + } + else if (IS_ENC_VINTRP(insn_long)) { + insn_size = 4; + uint32_t op_value = longfield<16,17>(insn_long); + assert(isArrayIndexValid(ENC_VINTRP_insn_table, op_value) && "Opcode over or underflow"); + const amdgpu_gfx940_insn_entry &insn_entry = ENC_VINTRP_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_VINTRP; + } + else if (IS_ENC_VOP3P(insn_long)) { + insn_size = 8; + uint32_t op_value = longfield<16,22>(insn_long); + assert(isArrayIndexValid(ENC_VOP3P_insn_table, op_value) && "Opcode over or underflow"); + const amdgpu_gfx940_insn_entry &insn_entry = ENC_VOP3P_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_VOP3P; + } + else if (IS_ENC_VOP3(insn_long)) { + insn_size = 8; + uint32_t op_value = longfield<16,25>(insn_long); + assert(isArrayIndexValid(ENC_VOP3_insn_table, op_value) && "Opcode over or underflow"); + const amdgpu_gfx940_insn_entry &insn_entry = ENC_VOP3_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_VOP3; + } + else if (IS_ENC_DS(insn_long)) { + insn_size = 8; + uint32_t op_value = longfield<17,24>(insn_long); + assert(isArrayIndexValid(ENC_DS_insn_table, op_value) && "Opcode over or underflow"); + const amdgpu_gfx940_insn_entry &insn_entry = ENC_DS_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_DS; + } + else if (IS_ENC_MUBUF(insn_long)) { + insn_size = 8; + uint32_t op_value = longfield<18,24>(insn_long); + assert(isArrayIndexValid(ENC_MUBUF_insn_table, op_value) && "Opcode over or underflow"); + const amdgpu_gfx940_insn_entry &insn_entry = ENC_MUBUF_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_MUBUF; + } + else if (IS_ENC_MTBUF(insn_long)) { + insn_size = 8; + uint32_t op_value = longfield<15,18>(insn_long); + assert(isArrayIndexValid(ENC_MTBUF_insn_table, op_value) && "Opcode over or underflow"); + const amdgpu_gfx940_insn_entry &insn_entry = ENC_MTBUF_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_MTBUF; + } + else if (IS_ENC_MIMG(insn_long)) { + insn_size = 8; + uint32_t op_value = longfield<18,24>(insn_long); + assert(isArrayIndexValid(ENC_MIMG_insn_table, op_value) && "Opcode over or underflow"); + const amdgpu_gfx940_insn_entry &insn_entry = ENC_MIMG_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_MIMG; + } + else if (IS_ENC_FLAT(insn_long)) { + insn_size = 8; + uint32_t op_value = longfield<18,24>(insn_long); + assert(isArrayIndexValid(ENC_FLAT_insn_table, op_value) && "Opcode over or underflow"); + const amdgpu_gfx940_insn_entry &insn_entry = ENC_FLAT_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_FLAT; + } + else if (IS_ENC_FLAT_GLBL(insn_long)) { + insn_size = 8; + uint32_t op_value = longfield<18,24>(insn_long); + assert(isArrayIndexValid(ENC_FLAT_GLBL_insn_table, op_value) && "Opcode over or underflow"); + const amdgpu_gfx940_insn_entry &insn_entry = ENC_FLAT_GLBL_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_FLAT_GLBL; + } + else if (IS_ENC_FLAT_SCRATCH(insn_long)) { + insn_size = 8; + uint32_t op_value = longfield<18,24>(insn_long); + assert(isArrayIndexValid(ENC_FLAT_SCRATCH_insn_table, op_value) && "Opcode over or underflow"); + const amdgpu_gfx940_insn_entry &insn_entry = ENC_FLAT_SCRATCH_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_FLAT_SCRATCH; + } + else if (IS_SOPK_INST_LITERAL_(insn_long)) { + insn_size = 8; + uint32_t op_value = longfield<23,27>(insn_long); + assert(isArrayIndexValid(SOPK_INST_LITERAL__insn_table, op_value) && "Opcode over or underflow"); + const amdgpu_gfx940_insn_entry &insn_entry = SOPK_INST_LITERAL__insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = SOPK_INST_LITERAL_; + } + else if (IS_ENC_VOP2_LITERAL(insn_long)) { + insn_size = 8; + uint32_t op_value = longfield<25,30>(insn_long); + assert(isArrayIndexValid(ENC_VOP2_LITERAL_insn_table, op_value) && "Opcode over or underflow"); + const amdgpu_gfx940_insn_entry &insn_entry = ENC_VOP2_LITERAL_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_VOP2_LITERAL; + } + else if (IS_ENC_VOP3B(insn_long)) { + insn_size = 8; + uint32_t op_value = longfield<16,25>(insn_long); + assert(isArrayIndexValid(ENC_VOP3B_insn_table, op_value) && "Opcode over or underflow"); + const amdgpu_gfx940_insn_entry &insn_entry = ENC_VOP3B_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_VOP3B; + } + else if (IS_ENC_VOP3P_MFMA(insn_long)) { + insn_size = 8; + uint32_t op_value = longfield<16,22>(insn_long); + assert(isArrayIndexValid(ENC_VOP3P_MFMA_insn_table, op_value) && "Opcode over or underflow"); + const amdgpu_gfx940_insn_entry &insn_entry = ENC_VOP3P_MFMA_insn_table[op]; + this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size+immLen,reinterpret_cast(&insn)); + instr_family = ENC_VOP3P_MFMA; + } + } + + void InstructionDecoder_amdgpu_gfx940::mainDecode() + { + if (IS_ENC_SOP1(insn_long)) { + decodeENC_SOP1(); + } + else if (IS_ENC_SOPC(insn_long)) { + decodeENC_SOPC(); + } + else if (IS_ENC_SOPP(insn_long)) { + decodeENC_SOPP(); + } + else if (IS_ENC_SOPK(insn_long)) { + decodeENC_SOPK(); + } + else if (IS_ENC_SOP2(insn_long)) { + decodeENC_SOP2(); + } + else if (IS_ENC_SMEM(insn_long)) { + decodeENC_SMEM(); + } + else if (IS_ENC_VOP1(insn_long)) { + decodeENC_VOP1(); + } + else if (IS_ENC_VOPC(insn_long)) { + decodeENC_VOPC(); + } + else if (IS_ENC_VOP2(insn_long)) { + decodeENC_VOP2(); + } + else if (IS_ENC_VINTRP(insn_long)) { + decodeENC_VINTRP(); + } + else if (IS_ENC_VOP3P(insn_long)) { + decodeENC_VOP3P(); + } + else if (IS_ENC_VOP3(insn_long)) { + decodeENC_VOP3(); + } + else if (IS_ENC_DS(insn_long)) { + decodeENC_DS(); + } + else if (IS_ENC_MUBUF(insn_long)) { + decodeENC_MUBUF(); + } + else if (IS_ENC_MTBUF(insn_long)) { + decodeENC_MTBUF(); + } + else if (IS_ENC_MIMG(insn_long)) { + decodeENC_MIMG(); + } + else if (IS_ENC_FLAT(insn_long)) { + decodeENC_FLAT(); + } + else if (IS_ENC_FLAT_GLBL(insn_long)) { + decodeENC_FLAT_GLBL(); + } + else if (IS_ENC_FLAT_SCRATCH(insn_long)) { + decodeENC_FLAT_SCRATCH(); + } + else if (IS_SOPK_INST_LITERAL_(insn_long)) { + decodeSOPK_INST_LITERAL_(); + } + else if (IS_ENC_VOP2_LITERAL(insn_long)) { + decodeENC_VOP2_LITERAL(); + } + else if (IS_ENC_VOP3B(insn_long)) { + decodeENC_VOP3B(); + } + else if (IS_ENC_VOP3P_MFMA(insn_long)) { + decodeENC_VOP3P_MFMA(); + } + } + +} +} diff --git a/instructionAPI/src/AMDGPU/gfx940/amdgpu_gfx940_opcode_tables.C b/instructionAPI/src/AMDGPU/gfx940/amdgpu_gfx940_opcode_tables.C new file mode 100644 index 0000000000..bc2ca8afc3 --- /dev/null +++ b/instructionAPI/src/AMDGPU/gfx940/amdgpu_gfx940_opcode_tables.C @@ -0,0 +1,2900 @@ + const amdgpu_gfx940_insn_entry ENC_DS_insn_table [256] = + { + {amdgpu_gfx940_op_DS_ADD_U32,"DS_ADD_U32"} ,//0 + {amdgpu_gfx940_op_DS_SUB_U32,"DS_SUB_U32"} ,//1 + {amdgpu_gfx940_op_DS_RSUB_U32,"DS_RSUB_U32"} ,//2 + {amdgpu_gfx940_op_DS_INC_U32,"DS_INC_U32"} ,//3 + {amdgpu_gfx940_op_DS_DEC_U32,"DS_DEC_U32"} ,//4 + {amdgpu_gfx940_op_DS_MIN_I32,"DS_MIN_I32"} ,//5 + {amdgpu_gfx940_op_DS_MAX_I32,"DS_MAX_I32"} ,//6 + {amdgpu_gfx940_op_DS_MIN_U32,"DS_MIN_U32"} ,//7 + {amdgpu_gfx940_op_DS_MAX_U32,"DS_MAX_U32"} ,//8 + {amdgpu_gfx940_op_DS_AND_B32,"DS_AND_B32"} ,//9 + {amdgpu_gfx940_op_DS_OR_B32,"DS_OR_B32"} ,//10 + {amdgpu_gfx940_op_DS_XOR_B32,"DS_XOR_B32"} ,//11 + {amdgpu_gfx940_op_DS_MSKOR_B32,"DS_MSKOR_B32"} ,//12 + {amdgpu_gfx940_op_DS_WRITE_B32,"DS_WRITE_B32"} ,//13 + {amdgpu_gfx940_op_DS_WRITE2_B32,"DS_WRITE2_B32"} ,//14 + {amdgpu_gfx940_op_DS_WRITE2ST64_B32,"DS_WRITE2ST64_B32"} ,//15 + {amdgpu_gfx940_op_DS_CMPST_B32,"DS_CMPST_B32"} ,//16 + {amdgpu_gfx940_op_DS_CMPST_F32,"DS_CMPST_F32"} ,//17 + {amdgpu_gfx940_op_DS_MIN_F32,"DS_MIN_F32"} ,//18 + {amdgpu_gfx940_op_DS_MAX_F32,"DS_MAX_F32"} ,//19 + {amdgpu_gfx940_op_DS_NOP,"DS_NOP"} ,//20 + {amdgpu_gfx940_op_DS_ADD_F32,"DS_ADD_F32"} ,//21 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//22 + {amdgpu_gfx940_op_DS_PK_ADD_F16,"DS_PK_ADD_F16"} ,//23 + {amdgpu_gfx940_op_DS_PK_ADD_BF16,"DS_PK_ADD_BF16"} ,//24 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//25 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//26 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//27 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//28 + {amdgpu_gfx940_op_DS_WRITE_ADDTID_B32,"DS_WRITE_ADDTID_B32"} ,//29 + {amdgpu_gfx940_op_DS_WRITE_B8,"DS_WRITE_B8"} ,//30 + {amdgpu_gfx940_op_DS_WRITE_B16,"DS_WRITE_B16"} ,//31 + {amdgpu_gfx940_op_DS_ADD_RTN_U32,"DS_ADD_RTN_U32"} ,//32 + {amdgpu_gfx940_op_DS_SUB_RTN_U32,"DS_SUB_RTN_U32"} ,//33 + {amdgpu_gfx940_op_DS_RSUB_RTN_U32,"DS_RSUB_RTN_U32"} ,//34 + {amdgpu_gfx940_op_DS_INC_RTN_U32,"DS_INC_RTN_U32"} ,//35 + {amdgpu_gfx940_op_DS_DEC_RTN_U32,"DS_DEC_RTN_U32"} ,//36 + {amdgpu_gfx940_op_DS_MIN_RTN_I32,"DS_MIN_RTN_I32"} ,//37 + {amdgpu_gfx940_op_DS_MAX_RTN_I32,"DS_MAX_RTN_I32"} ,//38 + {amdgpu_gfx940_op_DS_MIN_RTN_U32,"DS_MIN_RTN_U32"} ,//39 + {amdgpu_gfx940_op_DS_MAX_RTN_U32,"DS_MAX_RTN_U32"} ,//40 + {amdgpu_gfx940_op_DS_AND_RTN_B32,"DS_AND_RTN_B32"} ,//41 + {amdgpu_gfx940_op_DS_OR_RTN_B32,"DS_OR_RTN_B32"} ,//42 + {amdgpu_gfx940_op_DS_XOR_RTN_B32,"DS_XOR_RTN_B32"} ,//43 + {amdgpu_gfx940_op_DS_MSKOR_RTN_B32,"DS_MSKOR_RTN_B32"} ,//44 + {amdgpu_gfx940_op_DS_WRXCHG_RTN_B32,"DS_WRXCHG_RTN_B32"} ,//45 + {amdgpu_gfx940_op_DS_WRXCHG2_RTN_B32,"DS_WRXCHG2_RTN_B32"} ,//46 + {amdgpu_gfx940_op_DS_WRXCHG2ST64_RTN_B32,"DS_WRXCHG2ST64_RTN_B32"} ,//47 + {amdgpu_gfx940_op_DS_CMPST_RTN_B32,"DS_CMPST_RTN_B32"} ,//48 + {amdgpu_gfx940_op_DS_CMPST_RTN_F32,"DS_CMPST_RTN_F32"} ,//49 + {amdgpu_gfx940_op_DS_MIN_RTN_F32,"DS_MIN_RTN_F32"} ,//50 + {amdgpu_gfx940_op_DS_MAX_RTN_F32,"DS_MAX_RTN_F32"} ,//51 + {amdgpu_gfx940_op_DS_WRAP_RTN_B32,"DS_WRAP_RTN_B32"} ,//52 + {amdgpu_gfx940_op_DS_ADD_RTN_F32,"DS_ADD_RTN_F32"} ,//53 + {amdgpu_gfx940_op_DS_READ_B32,"DS_READ_B32"} ,//54 + {amdgpu_gfx940_op_DS_READ2_B32,"DS_READ2_B32"} ,//55 + {amdgpu_gfx940_op_DS_READ2ST64_B32,"DS_READ2ST64_B32"} ,//56 + {amdgpu_gfx940_op_DS_READ_I8,"DS_READ_I8"} ,//57 + {amdgpu_gfx940_op_DS_READ_U8,"DS_READ_U8"} ,//58 + {amdgpu_gfx940_op_DS_READ_I16,"DS_READ_I16"} ,//59 + {amdgpu_gfx940_op_DS_READ_U16,"DS_READ_U16"} ,//60 + {amdgpu_gfx940_op_DS_SWIZZLE_B32,"DS_SWIZZLE_B32"} ,//61 + {amdgpu_gfx940_op_DS_PERMUTE_B32,"DS_PERMUTE_B32"} ,//62 + {amdgpu_gfx940_op_DS_BPERMUTE_B32,"DS_BPERMUTE_B32"} ,//63 + {amdgpu_gfx940_op_DS_ADD_U64,"DS_ADD_U64"} ,//64 + {amdgpu_gfx940_op_DS_SUB_U64,"DS_SUB_U64"} ,//65 + {amdgpu_gfx940_op_DS_RSUB_U64,"DS_RSUB_U64"} ,//66 + {amdgpu_gfx940_op_DS_INC_U64,"DS_INC_U64"} ,//67 + {amdgpu_gfx940_op_DS_DEC_U64,"DS_DEC_U64"} ,//68 + {amdgpu_gfx940_op_DS_MIN_I64,"DS_MIN_I64"} ,//69 + {amdgpu_gfx940_op_DS_MAX_I64,"DS_MAX_I64"} ,//70 + {amdgpu_gfx940_op_DS_MIN_U64,"DS_MIN_U64"} ,//71 + {amdgpu_gfx940_op_DS_MAX_U64,"DS_MAX_U64"} ,//72 + {amdgpu_gfx940_op_DS_AND_B64,"DS_AND_B64"} ,//73 + {amdgpu_gfx940_op_DS_OR_B64,"DS_OR_B64"} ,//74 + {amdgpu_gfx940_op_DS_XOR_B64,"DS_XOR_B64"} ,//75 + {amdgpu_gfx940_op_DS_MSKOR_B64,"DS_MSKOR_B64"} ,//76 + {amdgpu_gfx940_op_DS_WRITE_B64,"DS_WRITE_B64"} ,//77 + {amdgpu_gfx940_op_DS_WRITE2_B64,"DS_WRITE2_B64"} ,//78 + {amdgpu_gfx940_op_DS_WRITE2ST64_B64,"DS_WRITE2ST64_B64"} ,//79 + {amdgpu_gfx940_op_DS_CMPST_B64,"DS_CMPST_B64"} ,//80 + {amdgpu_gfx940_op_DS_CMPST_F64,"DS_CMPST_F64"} ,//81 + {amdgpu_gfx940_op_DS_MIN_F64,"DS_MIN_F64"} ,//82 + {amdgpu_gfx940_op_DS_MAX_F64,"DS_MAX_F64"} ,//83 + {amdgpu_gfx940_op_DS_WRITE_B8_D16_HI,"DS_WRITE_B8_D16_HI"} ,//84 + {amdgpu_gfx940_op_DS_WRITE_B16_D16_HI,"DS_WRITE_B16_D16_HI"} ,//85 + {amdgpu_gfx940_op_DS_READ_U8_D16,"DS_READ_U8_D16"} ,//86 + {amdgpu_gfx940_op_DS_READ_U8_D16_HI,"DS_READ_U8_D16_HI"} ,//87 + {amdgpu_gfx940_op_DS_READ_I8_D16,"DS_READ_I8_D16"} ,//88 + {amdgpu_gfx940_op_DS_READ_I8_D16_HI,"DS_READ_I8_D16_HI"} ,//89 + {amdgpu_gfx940_op_DS_READ_U16_D16,"DS_READ_U16_D16"} ,//90 + {amdgpu_gfx940_op_DS_READ_U16_D16_HI,"DS_READ_U16_D16_HI"} ,//91 + {amdgpu_gfx940_op_DS_ADD_F64,"DS_ADD_F64"} ,//92 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//93 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//94 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//95 + {amdgpu_gfx940_op_DS_ADD_RTN_U64,"DS_ADD_RTN_U64"} ,//96 + {amdgpu_gfx940_op_DS_SUB_RTN_U64,"DS_SUB_RTN_U64"} ,//97 + {amdgpu_gfx940_op_DS_RSUB_RTN_U64,"DS_RSUB_RTN_U64"} ,//98 + {amdgpu_gfx940_op_DS_INC_RTN_U64,"DS_INC_RTN_U64"} ,//99 + {amdgpu_gfx940_op_DS_DEC_RTN_U64,"DS_DEC_RTN_U64"} ,//100 + {amdgpu_gfx940_op_DS_MIN_RTN_I64,"DS_MIN_RTN_I64"} ,//101 + {amdgpu_gfx940_op_DS_MAX_RTN_I64,"DS_MAX_RTN_I64"} ,//102 + {amdgpu_gfx940_op_DS_MIN_RTN_U64,"DS_MIN_RTN_U64"} ,//103 + {amdgpu_gfx940_op_DS_MAX_RTN_U64,"DS_MAX_RTN_U64"} ,//104 + {amdgpu_gfx940_op_DS_AND_RTN_B64,"DS_AND_RTN_B64"} ,//105 + {amdgpu_gfx940_op_DS_OR_RTN_B64,"DS_OR_RTN_B64"} ,//106 + {amdgpu_gfx940_op_DS_XOR_RTN_B64,"DS_XOR_RTN_B64"} ,//107 + {amdgpu_gfx940_op_DS_MSKOR_RTN_B64,"DS_MSKOR_RTN_B64"} ,//108 + {amdgpu_gfx940_op_DS_WRXCHG_RTN_B64,"DS_WRXCHG_RTN_B64"} ,//109 + {amdgpu_gfx940_op_DS_WRXCHG2_RTN_B64,"DS_WRXCHG2_RTN_B64"} ,//110 + {amdgpu_gfx940_op_DS_WRXCHG2ST64_RTN_B64,"DS_WRXCHG2ST64_RTN_B64"} ,//111 + {amdgpu_gfx940_op_DS_CMPST_RTN_B64,"DS_CMPST_RTN_B64"} ,//112 + {amdgpu_gfx940_op_DS_CMPST_RTN_F64,"DS_CMPST_RTN_F64"} ,//113 + {amdgpu_gfx940_op_DS_MIN_RTN_F64,"DS_MIN_RTN_F64"} ,//114 + {amdgpu_gfx940_op_DS_MAX_RTN_F64,"DS_MAX_RTN_F64"} ,//115 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//116 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//117 + {amdgpu_gfx940_op_DS_READ_B64,"DS_READ_B64"} ,//118 + {amdgpu_gfx940_op_DS_READ2_B64,"DS_READ2_B64"} ,//119 + {amdgpu_gfx940_op_DS_READ2ST64_B64,"DS_READ2ST64_B64"} ,//120 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//121 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//122 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//123 + {amdgpu_gfx940_op_DS_ADD_RTN_F64,"DS_ADD_RTN_F64"} ,//124 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//125 + {amdgpu_gfx940_op_DS_CONDXCHG32_RTN_B64,"DS_CONDXCHG32_RTN_B64"} ,//126 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//127 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//128 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//129 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//130 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//131 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//132 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//133 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//134 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//135 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//136 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//137 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//138 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//139 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//140 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//141 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//142 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//143 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//144 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//145 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//146 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//147 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//148 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//149 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//150 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//151 + {amdgpu_gfx940_op_DS_GWS_SEMA_RELEASE_ALL,"DS_GWS_SEMA_RELEASE_ALL"} ,//152 + {amdgpu_gfx940_op_DS_GWS_INIT,"DS_GWS_INIT"} ,//153 + {amdgpu_gfx940_op_DS_GWS_SEMA_V,"DS_GWS_SEMA_V"} ,//154 + {amdgpu_gfx940_op_DS_GWS_SEMA_BR,"DS_GWS_SEMA_BR"} ,//155 + {amdgpu_gfx940_op_DS_GWS_SEMA_P,"DS_GWS_SEMA_P"} ,//156 + {amdgpu_gfx940_op_DS_GWS_BARRIER,"DS_GWS_BARRIER"} ,//157 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//158 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//159 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//160 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//161 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//162 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//163 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//164 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//165 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//166 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//167 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//168 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//169 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//170 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//171 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//172 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//173 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//174 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//175 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//176 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//177 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//178 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//179 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//180 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//181 + {amdgpu_gfx940_op_DS_READ_ADDTID_B32,"DS_READ_ADDTID_B32"} ,//182 + {amdgpu_gfx940_op_DS_PK_ADD_RTN_F16,"DS_PK_ADD_RTN_F16"} ,//183 + {amdgpu_gfx940_op_DS_PK_ADD_RTN_BF16,"DS_PK_ADD_RTN_BF16"} ,//184 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//185 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//186 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//187 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//188 + {amdgpu_gfx940_op_DS_CONSUME,"DS_CONSUME"} ,//189 + {amdgpu_gfx940_op_DS_APPEND,"DS_APPEND"} ,//190 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//191 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//192 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//193 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//194 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//195 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//196 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//197 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//198 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//199 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//200 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//201 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//202 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//203 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//204 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//205 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//206 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//207 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//208 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//209 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//210 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//211 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//212 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//213 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//214 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//215 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//216 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//217 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//218 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//219 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//220 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//221 + {amdgpu_gfx940_op_DS_WRITE_B96,"DS_WRITE_B96"} ,//222 + {amdgpu_gfx940_op_DS_WRITE_B128,"DS_WRITE_B128"} ,//223 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//224 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//225 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//226 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//227 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//228 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//229 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//230 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//231 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//232 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//233 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//234 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//235 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//236 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//237 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//238 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//239 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//240 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//241 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//242 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//243 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//244 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//245 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//246 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//247 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//248 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//249 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//250 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//251 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//252 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//253 + {amdgpu_gfx940_op_DS_READ_B96,"DS_READ_B96"} ,//254 + {amdgpu_gfx940_op_DS_READ_B128,"DS_READ_B128"} ,//255 + }; // end ENC_DS_insn_table + const amdgpu_gfx940_insn_entry ENC_FLAT_insn_table [109] = + { + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//0 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//1 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//2 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//3 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//4 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//5 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//6 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//7 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//8 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//9 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//10 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//11 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//12 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//13 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//14 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//15 + {amdgpu_gfx940_op_FLAT_LOAD_UBYTE,"FLAT_LOAD_UBYTE"} ,//16 + {amdgpu_gfx940_op_FLAT_LOAD_SBYTE,"FLAT_LOAD_SBYTE"} ,//17 + {amdgpu_gfx940_op_FLAT_LOAD_USHORT,"FLAT_LOAD_USHORT"} ,//18 + {amdgpu_gfx940_op_FLAT_LOAD_SSHORT,"FLAT_LOAD_SSHORT"} ,//19 + {amdgpu_gfx940_op_FLAT_LOAD_DWORD,"FLAT_LOAD_DWORD"} ,//20 + {amdgpu_gfx940_op_FLAT_LOAD_DWORDX2,"FLAT_LOAD_DWORDX2"} ,//21 + {amdgpu_gfx940_op_FLAT_LOAD_DWORDX3,"FLAT_LOAD_DWORDX3"} ,//22 + {amdgpu_gfx940_op_FLAT_LOAD_DWORDX4,"FLAT_LOAD_DWORDX4"} ,//23 + {amdgpu_gfx940_op_FLAT_STORE_BYTE,"FLAT_STORE_BYTE"} ,//24 + {amdgpu_gfx940_op_FLAT_STORE_BYTE_D16_HI,"FLAT_STORE_BYTE_D16_HI"} ,//25 + {amdgpu_gfx940_op_FLAT_STORE_SHORT,"FLAT_STORE_SHORT"} ,//26 + {amdgpu_gfx940_op_FLAT_STORE_SHORT_D16_HI,"FLAT_STORE_SHORT_D16_HI"} ,//27 + {amdgpu_gfx940_op_FLAT_STORE_DWORD,"FLAT_STORE_DWORD"} ,//28 + {amdgpu_gfx940_op_FLAT_STORE_DWORDX2,"FLAT_STORE_DWORDX2"} ,//29 + {amdgpu_gfx940_op_FLAT_STORE_DWORDX3,"FLAT_STORE_DWORDX3"} ,//30 + {amdgpu_gfx940_op_FLAT_STORE_DWORDX4,"FLAT_STORE_DWORDX4"} ,//31 + {amdgpu_gfx940_op_FLAT_LOAD_UBYTE_D16,"FLAT_LOAD_UBYTE_D16"} ,//32 + {amdgpu_gfx940_op_FLAT_LOAD_UBYTE_D16_HI,"FLAT_LOAD_UBYTE_D16_HI"} ,//33 + {amdgpu_gfx940_op_FLAT_LOAD_SBYTE_D16,"FLAT_LOAD_SBYTE_D16"} ,//34 + {amdgpu_gfx940_op_FLAT_LOAD_SBYTE_D16_HI,"FLAT_LOAD_SBYTE_D16_HI"} ,//35 + {amdgpu_gfx940_op_FLAT_LOAD_SHORT_D16,"FLAT_LOAD_SHORT_D16"} ,//36 + {amdgpu_gfx940_op_FLAT_LOAD_SHORT_D16_HI,"FLAT_LOAD_SHORT_D16_HI"} ,//37 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//38 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//39 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//40 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//41 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//42 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//43 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//44 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//45 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//46 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//47 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//48 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//49 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//50 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//51 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//52 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//53 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//54 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//55 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//56 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//57 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//58 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//59 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//60 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//61 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//62 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//63 + {amdgpu_gfx940_op_FLAT_ATOMIC_SWAP,"FLAT_ATOMIC_SWAP"} ,//64 + {amdgpu_gfx940_op_FLAT_ATOMIC_CMPSWAP,"FLAT_ATOMIC_CMPSWAP"} ,//65 + {amdgpu_gfx940_op_FLAT_ATOMIC_ADD,"FLAT_ATOMIC_ADD"} ,//66 + {amdgpu_gfx940_op_FLAT_ATOMIC_SUB,"FLAT_ATOMIC_SUB"} ,//67 + {amdgpu_gfx940_op_FLAT_ATOMIC_SMIN,"FLAT_ATOMIC_SMIN"} ,//68 + {amdgpu_gfx940_op_FLAT_ATOMIC_UMIN,"FLAT_ATOMIC_UMIN"} ,//69 + {amdgpu_gfx940_op_FLAT_ATOMIC_SMAX,"FLAT_ATOMIC_SMAX"} ,//70 + {amdgpu_gfx940_op_FLAT_ATOMIC_UMAX,"FLAT_ATOMIC_UMAX"} ,//71 + {amdgpu_gfx940_op_FLAT_ATOMIC_AND,"FLAT_ATOMIC_AND"} ,//72 + {amdgpu_gfx940_op_FLAT_ATOMIC_OR,"FLAT_ATOMIC_OR"} ,//73 + {amdgpu_gfx940_op_FLAT_ATOMIC_XOR,"FLAT_ATOMIC_XOR"} ,//74 + {amdgpu_gfx940_op_FLAT_ATOMIC_INC,"FLAT_ATOMIC_INC"} ,//75 + {amdgpu_gfx940_op_FLAT_ATOMIC_DEC,"FLAT_ATOMIC_DEC"} ,//76 + {amdgpu_gfx940_op_FLAT_ATOMIC_ADD_F32,"FLAT_ATOMIC_ADD_F32"} ,//77 + {amdgpu_gfx940_op_FLAT_ATOMIC_PK_ADD_F16,"FLAT_ATOMIC_PK_ADD_F16"} ,//78 + {amdgpu_gfx940_op_FLAT_ATOMIC_ADD_F64,"FLAT_ATOMIC_ADD_F64"} ,//79 + {amdgpu_gfx940_op_FLAT_ATOMIC_MIN_F64,"FLAT_ATOMIC_MIN_F64"} ,//80 + {amdgpu_gfx940_op_FLAT_ATOMIC_MAX_F64,"FLAT_ATOMIC_MAX_F64"} ,//81 + {amdgpu_gfx940_op_FLAT_ATOMIC_PK_ADD_BF16,"FLAT_ATOMIC_PK_ADD_BF16"} ,//82 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//83 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//84 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//85 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//86 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//87 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//88 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//89 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//90 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//91 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//92 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//93 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//94 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//95 + {amdgpu_gfx940_op_FLAT_ATOMIC_SWAP_X2,"FLAT_ATOMIC_SWAP_X2"} ,//96 + {amdgpu_gfx940_op_FLAT_ATOMIC_CMPSWAP_X2,"FLAT_ATOMIC_CMPSWAP_X2"} ,//97 + {amdgpu_gfx940_op_FLAT_ATOMIC_ADD_X2,"FLAT_ATOMIC_ADD_X2"} ,//98 + {amdgpu_gfx940_op_FLAT_ATOMIC_SUB_X2,"FLAT_ATOMIC_SUB_X2"} ,//99 + {amdgpu_gfx940_op_FLAT_ATOMIC_SMIN_X2,"FLAT_ATOMIC_SMIN_X2"} ,//100 + {amdgpu_gfx940_op_FLAT_ATOMIC_UMIN_X2,"FLAT_ATOMIC_UMIN_X2"} ,//101 + {amdgpu_gfx940_op_FLAT_ATOMIC_SMAX_X2,"FLAT_ATOMIC_SMAX_X2"} ,//102 + {amdgpu_gfx940_op_FLAT_ATOMIC_UMAX_X2,"FLAT_ATOMIC_UMAX_X2"} ,//103 + {amdgpu_gfx940_op_FLAT_ATOMIC_AND_X2,"FLAT_ATOMIC_AND_X2"} ,//104 + {amdgpu_gfx940_op_FLAT_ATOMIC_OR_X2,"FLAT_ATOMIC_OR_X2"} ,//105 + {amdgpu_gfx940_op_FLAT_ATOMIC_XOR_X2,"FLAT_ATOMIC_XOR_X2"} ,//106 + {amdgpu_gfx940_op_FLAT_ATOMIC_INC_X2,"FLAT_ATOMIC_INC_X2"} ,//107 + {amdgpu_gfx940_op_FLAT_ATOMIC_DEC_X2,"FLAT_ATOMIC_DEC_X2"} ,//108 + }; // end ENC_FLAT_insn_table + const amdgpu_gfx940_insn_entry ENC_FLAT_GLBL_insn_table [109] = + { + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//0 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//1 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//2 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//3 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//4 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//5 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//6 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//7 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//8 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//9 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//10 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//11 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//12 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//13 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//14 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//15 + {amdgpu_gfx940_op_GLOBAL_LOAD_UBYTE,"GLOBAL_LOAD_UBYTE"} ,//16 + {amdgpu_gfx940_op_GLOBAL_LOAD_SBYTE,"GLOBAL_LOAD_SBYTE"} ,//17 + {amdgpu_gfx940_op_GLOBAL_LOAD_USHORT,"GLOBAL_LOAD_USHORT"} ,//18 + {amdgpu_gfx940_op_GLOBAL_LOAD_SSHORT,"GLOBAL_LOAD_SSHORT"} ,//19 + {amdgpu_gfx940_op_GLOBAL_LOAD_DWORD,"GLOBAL_LOAD_DWORD"} ,//20 + {amdgpu_gfx940_op_GLOBAL_LOAD_DWORDX2,"GLOBAL_LOAD_DWORDX2"} ,//21 + {amdgpu_gfx940_op_GLOBAL_LOAD_DWORDX3,"GLOBAL_LOAD_DWORDX3"} ,//22 + {amdgpu_gfx940_op_GLOBAL_LOAD_DWORDX4,"GLOBAL_LOAD_DWORDX4"} ,//23 + {amdgpu_gfx940_op_GLOBAL_STORE_BYTE,"GLOBAL_STORE_BYTE"} ,//24 + {amdgpu_gfx940_op_GLOBAL_STORE_BYTE_D16_HI,"GLOBAL_STORE_BYTE_D16_HI"} ,//25 + {amdgpu_gfx940_op_GLOBAL_STORE_SHORT,"GLOBAL_STORE_SHORT"} ,//26 + {amdgpu_gfx940_op_GLOBAL_STORE_SHORT_D16_HI,"GLOBAL_STORE_SHORT_D16_HI"} ,//27 + {amdgpu_gfx940_op_GLOBAL_STORE_DWORD,"GLOBAL_STORE_DWORD"} ,//28 + {amdgpu_gfx940_op_GLOBAL_STORE_DWORDX2,"GLOBAL_STORE_DWORDX2"} ,//29 + {amdgpu_gfx940_op_GLOBAL_STORE_DWORDX3,"GLOBAL_STORE_DWORDX3"} ,//30 + {amdgpu_gfx940_op_GLOBAL_STORE_DWORDX4,"GLOBAL_STORE_DWORDX4"} ,//31 + {amdgpu_gfx940_op_GLOBAL_LOAD_UBYTE_D16,"GLOBAL_LOAD_UBYTE_D16"} ,//32 + {amdgpu_gfx940_op_GLOBAL_LOAD_UBYTE_D16_HI,"GLOBAL_LOAD_UBYTE_D16_HI"} ,//33 + {amdgpu_gfx940_op_GLOBAL_LOAD_SBYTE_D16,"GLOBAL_LOAD_SBYTE_D16"} ,//34 + {amdgpu_gfx940_op_GLOBAL_LOAD_SBYTE_D16_HI,"GLOBAL_LOAD_SBYTE_D16_HI"} ,//35 + {amdgpu_gfx940_op_GLOBAL_LOAD_SHORT_D16,"GLOBAL_LOAD_SHORT_D16"} ,//36 + {amdgpu_gfx940_op_GLOBAL_LOAD_SHORT_D16_HI,"GLOBAL_LOAD_SHORT_D16_HI"} ,//37 + {amdgpu_gfx940_op_GLOBAL_LOAD_LDS_UBYTE,"GLOBAL_LOAD_LDS_UBYTE"} ,//38 + {amdgpu_gfx940_op_GLOBAL_LOAD_LDS_SBYTE,"GLOBAL_LOAD_LDS_SBYTE"} ,//39 + {amdgpu_gfx940_op_GLOBAL_LOAD_LDS_USHORT,"GLOBAL_LOAD_LDS_USHORT"} ,//40 + {amdgpu_gfx940_op_GLOBAL_LOAD_LDS_SSHORT,"GLOBAL_LOAD_LDS_SSHORT"} ,//41 + {amdgpu_gfx940_op_GLOBAL_LOAD_LDS_DWORD,"GLOBAL_LOAD_LDS_DWORD"} ,//42 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//43 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//44 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//45 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//46 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//47 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//48 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//49 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//50 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//51 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//52 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//53 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//54 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//55 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//56 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//57 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//58 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//59 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//60 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//61 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//62 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//63 + {amdgpu_gfx940_op_GLOBAL_ATOMIC_SWAP,"GLOBAL_ATOMIC_SWAP"} ,//64 + {amdgpu_gfx940_op_GLOBAL_ATOMIC_CMPSWAP,"GLOBAL_ATOMIC_CMPSWAP"} ,//65 + {amdgpu_gfx940_op_GLOBAL_ATOMIC_ADD,"GLOBAL_ATOMIC_ADD"} ,//66 + {amdgpu_gfx940_op_GLOBAL_ATOMIC_SUB,"GLOBAL_ATOMIC_SUB"} ,//67 + {amdgpu_gfx940_op_GLOBAL_ATOMIC_SMIN,"GLOBAL_ATOMIC_SMIN"} ,//68 + {amdgpu_gfx940_op_GLOBAL_ATOMIC_UMIN,"GLOBAL_ATOMIC_UMIN"} ,//69 + {amdgpu_gfx940_op_GLOBAL_ATOMIC_SMAX,"GLOBAL_ATOMIC_SMAX"} ,//70 + {amdgpu_gfx940_op_GLOBAL_ATOMIC_UMAX,"GLOBAL_ATOMIC_UMAX"} ,//71 + {amdgpu_gfx940_op_GLOBAL_ATOMIC_AND,"GLOBAL_ATOMIC_AND"} ,//72 + {amdgpu_gfx940_op_GLOBAL_ATOMIC_OR,"GLOBAL_ATOMIC_OR"} ,//73 + {amdgpu_gfx940_op_GLOBAL_ATOMIC_XOR,"GLOBAL_ATOMIC_XOR"} ,//74 + {amdgpu_gfx940_op_GLOBAL_ATOMIC_INC,"GLOBAL_ATOMIC_INC"} ,//75 + {amdgpu_gfx940_op_GLOBAL_ATOMIC_DEC,"GLOBAL_ATOMIC_DEC"} ,//76 + {amdgpu_gfx940_op_GLOBAL_ATOMIC_ADD_F32,"GLOBAL_ATOMIC_ADD_F32"} ,//77 + {amdgpu_gfx940_op_GLOBAL_ATOMIC_PK_ADD_F16,"GLOBAL_ATOMIC_PK_ADD_F16"} ,//78 + {amdgpu_gfx940_op_GLOBAL_ATOMIC_ADD_F64,"GLOBAL_ATOMIC_ADD_F64"} ,//79 + {amdgpu_gfx940_op_GLOBAL_ATOMIC_MIN_F64,"GLOBAL_ATOMIC_MIN_F64"} ,//80 + {amdgpu_gfx940_op_GLOBAL_ATOMIC_MAX_F64,"GLOBAL_ATOMIC_MAX_F64"} ,//81 + {amdgpu_gfx940_op_GLOBAL_ATOMIC_PK_ADD_BF16,"GLOBAL_ATOMIC_PK_ADD_BF16"} ,//82 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//83 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//84 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//85 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//86 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//87 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//88 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//89 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//90 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//91 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//92 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//93 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//94 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//95 + {amdgpu_gfx940_op_GLOBAL_ATOMIC_SWAP_X2,"GLOBAL_ATOMIC_SWAP_X2"} ,//96 + {amdgpu_gfx940_op_GLOBAL_ATOMIC_CMPSWAP_X2,"GLOBAL_ATOMIC_CMPSWAP_X2"} ,//97 + {amdgpu_gfx940_op_GLOBAL_ATOMIC_ADD_X2,"GLOBAL_ATOMIC_ADD_X2"} ,//98 + {amdgpu_gfx940_op_GLOBAL_ATOMIC_SUB_X2,"GLOBAL_ATOMIC_SUB_X2"} ,//99 + {amdgpu_gfx940_op_GLOBAL_ATOMIC_SMIN_X2,"GLOBAL_ATOMIC_SMIN_X2"} ,//100 + {amdgpu_gfx940_op_GLOBAL_ATOMIC_UMIN_X2,"GLOBAL_ATOMIC_UMIN_X2"} ,//101 + {amdgpu_gfx940_op_GLOBAL_ATOMIC_SMAX_X2,"GLOBAL_ATOMIC_SMAX_X2"} ,//102 + {amdgpu_gfx940_op_GLOBAL_ATOMIC_UMAX_X2,"GLOBAL_ATOMIC_UMAX_X2"} ,//103 + {amdgpu_gfx940_op_GLOBAL_ATOMIC_AND_X2,"GLOBAL_ATOMIC_AND_X2"} ,//104 + {amdgpu_gfx940_op_GLOBAL_ATOMIC_OR_X2,"GLOBAL_ATOMIC_OR_X2"} ,//105 + {amdgpu_gfx940_op_GLOBAL_ATOMIC_XOR_X2,"GLOBAL_ATOMIC_XOR_X2"} ,//106 + {amdgpu_gfx940_op_GLOBAL_ATOMIC_INC_X2,"GLOBAL_ATOMIC_INC_X2"} ,//107 + {amdgpu_gfx940_op_GLOBAL_ATOMIC_DEC_X2,"GLOBAL_ATOMIC_DEC_X2"} ,//108 + }; // end ENC_FLAT_GLBL_insn_table + const amdgpu_gfx940_insn_entry ENC_FLAT_SCRATCH_insn_table [43] = + { + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//0 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//1 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//2 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//3 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//4 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//5 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//6 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//7 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//8 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//9 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//10 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//11 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//12 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//13 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//14 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//15 + {amdgpu_gfx940_op_SCRATCH_LOAD_UBYTE,"SCRATCH_LOAD_UBYTE"} ,//16 + {amdgpu_gfx940_op_SCRATCH_LOAD_SBYTE,"SCRATCH_LOAD_SBYTE"} ,//17 + {amdgpu_gfx940_op_SCRATCH_LOAD_USHORT,"SCRATCH_LOAD_USHORT"} ,//18 + {amdgpu_gfx940_op_SCRATCH_LOAD_SSHORT,"SCRATCH_LOAD_SSHORT"} ,//19 + {amdgpu_gfx940_op_SCRATCH_LOAD_DWORD,"SCRATCH_LOAD_DWORD"} ,//20 + {amdgpu_gfx940_op_SCRATCH_LOAD_DWORDX2,"SCRATCH_LOAD_DWORDX2"} ,//21 + {amdgpu_gfx940_op_SCRATCH_LOAD_DWORDX3,"SCRATCH_LOAD_DWORDX3"} ,//22 + {amdgpu_gfx940_op_SCRATCH_LOAD_DWORDX4,"SCRATCH_LOAD_DWORDX4"} ,//23 + {amdgpu_gfx940_op_SCRATCH_STORE_BYTE,"SCRATCH_STORE_BYTE"} ,//24 + {amdgpu_gfx940_op_SCRATCH_STORE_BYTE_D16_HI,"SCRATCH_STORE_BYTE_D16_HI"} ,//25 + {amdgpu_gfx940_op_SCRATCH_STORE_SHORT,"SCRATCH_STORE_SHORT"} ,//26 + {amdgpu_gfx940_op_SCRATCH_STORE_SHORT_D16_HI,"SCRATCH_STORE_SHORT_D16_HI"} ,//27 + {amdgpu_gfx940_op_SCRATCH_STORE_DWORD,"SCRATCH_STORE_DWORD"} ,//28 + {amdgpu_gfx940_op_SCRATCH_STORE_DWORDX2,"SCRATCH_STORE_DWORDX2"} ,//29 + {amdgpu_gfx940_op_SCRATCH_STORE_DWORDX3,"SCRATCH_STORE_DWORDX3"} ,//30 + {amdgpu_gfx940_op_SCRATCH_STORE_DWORDX4,"SCRATCH_STORE_DWORDX4"} ,//31 + {amdgpu_gfx940_op_SCRATCH_LOAD_UBYTE_D16,"SCRATCH_LOAD_UBYTE_D16"} ,//32 + {amdgpu_gfx940_op_SCRATCH_LOAD_UBYTE_D16_HI,"SCRATCH_LOAD_UBYTE_D16_HI"} ,//33 + {amdgpu_gfx940_op_SCRATCH_LOAD_SBYTE_D16,"SCRATCH_LOAD_SBYTE_D16"} ,//34 + {amdgpu_gfx940_op_SCRATCH_LOAD_SBYTE_D16_HI,"SCRATCH_LOAD_SBYTE_D16_HI"} ,//35 + {amdgpu_gfx940_op_SCRATCH_LOAD_SHORT_D16,"SCRATCH_LOAD_SHORT_D16"} ,//36 + {amdgpu_gfx940_op_SCRATCH_LOAD_SHORT_D16_HI,"SCRATCH_LOAD_SHORT_D16_HI"} ,//37 + {amdgpu_gfx940_op_SCRATCH_LOAD_LDS_UBYTE,"SCRATCH_LOAD_LDS_UBYTE"} ,//38 + {amdgpu_gfx940_op_SCRATCH_LOAD_LDS_SBYTE,"SCRATCH_LOAD_LDS_SBYTE"} ,//39 + {amdgpu_gfx940_op_SCRATCH_LOAD_LDS_USHORT,"SCRATCH_LOAD_LDS_USHORT"} ,//40 + {amdgpu_gfx940_op_SCRATCH_LOAD_LDS_SSHORT,"SCRATCH_LOAD_LDS_SSHORT"} ,//41 + {amdgpu_gfx940_op_SCRATCH_LOAD_LDS_DWORD,"SCRATCH_LOAD_LDS_DWORD"} ,//42 + }; // end ENC_FLAT_SCRATCH_insn_table + const amdgpu_gfx940_insn_entry ENC_MTBUF_insn_table [16] = + { + {amdgpu_gfx940_op_TBUFFER_LOAD_FORMAT_X,"TBUFFER_LOAD_FORMAT_X"} ,//0 + {amdgpu_gfx940_op_TBUFFER_LOAD_FORMAT_XY,"TBUFFER_LOAD_FORMAT_XY"} ,//1 + {amdgpu_gfx940_op_TBUFFER_LOAD_FORMAT_XYZ,"TBUFFER_LOAD_FORMAT_XYZ"} ,//2 + {amdgpu_gfx940_op_TBUFFER_LOAD_FORMAT_XYZW,"TBUFFER_LOAD_FORMAT_XYZW"} ,//3 + {amdgpu_gfx940_op_TBUFFER_STORE_FORMAT_X,"TBUFFER_STORE_FORMAT_X"} ,//4 + {amdgpu_gfx940_op_TBUFFER_STORE_FORMAT_XY,"TBUFFER_STORE_FORMAT_XY"} ,//5 + {amdgpu_gfx940_op_TBUFFER_STORE_FORMAT_XYZ,"TBUFFER_STORE_FORMAT_XYZ"} ,//6 + {amdgpu_gfx940_op_TBUFFER_STORE_FORMAT_XYZW,"TBUFFER_STORE_FORMAT_XYZW"} ,//7 + {amdgpu_gfx940_op_TBUFFER_LOAD_FORMAT_D16_X,"TBUFFER_LOAD_FORMAT_D16_X"} ,//8 + {amdgpu_gfx940_op_TBUFFER_LOAD_FORMAT_D16_XY,"TBUFFER_LOAD_FORMAT_D16_XY"} ,//9 + {amdgpu_gfx940_op_TBUFFER_LOAD_FORMAT_D16_XYZ,"TBUFFER_LOAD_FORMAT_D16_XYZ"} ,//10 + {amdgpu_gfx940_op_TBUFFER_LOAD_FORMAT_D16_XYZW,"TBUFFER_LOAD_FORMAT_D16_XYZW"} ,//11 + {amdgpu_gfx940_op_TBUFFER_STORE_FORMAT_D16_X,"TBUFFER_STORE_FORMAT_D16_X"} ,//12 + {amdgpu_gfx940_op_TBUFFER_STORE_FORMAT_D16_XY,"TBUFFER_STORE_FORMAT_D16_XY"} ,//13 + {amdgpu_gfx940_op_TBUFFER_STORE_FORMAT_D16_XYZ,"TBUFFER_STORE_FORMAT_D16_XYZ"} ,//14 + {amdgpu_gfx940_op_TBUFFER_STORE_FORMAT_D16_XYZW,"TBUFFER_STORE_FORMAT_D16_XYZW"} ,//15 + }; // end ENC_MTBUF_insn_table + const amdgpu_gfx940_insn_entry ENC_MUBUF_insn_table [109] = + { + {amdgpu_gfx940_op_BUFFER_LOAD_FORMAT_X,"BUFFER_LOAD_FORMAT_X"} ,//0 + {amdgpu_gfx940_op_BUFFER_LOAD_FORMAT_XY,"BUFFER_LOAD_FORMAT_XY"} ,//1 + {amdgpu_gfx940_op_BUFFER_LOAD_FORMAT_XYZ,"BUFFER_LOAD_FORMAT_XYZ"} ,//2 + {amdgpu_gfx940_op_BUFFER_LOAD_FORMAT_XYZW,"BUFFER_LOAD_FORMAT_XYZW"} ,//3 + {amdgpu_gfx940_op_BUFFER_STORE_FORMAT_X,"BUFFER_STORE_FORMAT_X"} ,//4 + {amdgpu_gfx940_op_BUFFER_STORE_FORMAT_XY,"BUFFER_STORE_FORMAT_XY"} ,//5 + {amdgpu_gfx940_op_BUFFER_STORE_FORMAT_XYZ,"BUFFER_STORE_FORMAT_XYZ"} ,//6 + {amdgpu_gfx940_op_BUFFER_STORE_FORMAT_XYZW,"BUFFER_STORE_FORMAT_XYZW"} ,//7 + {amdgpu_gfx940_op_BUFFER_LOAD_FORMAT_D16_X,"BUFFER_LOAD_FORMAT_D16_X"} ,//8 + {amdgpu_gfx940_op_BUFFER_LOAD_FORMAT_D16_XY,"BUFFER_LOAD_FORMAT_D16_XY"} ,//9 + {amdgpu_gfx940_op_BUFFER_LOAD_FORMAT_D16_XYZ,"BUFFER_LOAD_FORMAT_D16_XYZ"} ,//10 + {amdgpu_gfx940_op_BUFFER_LOAD_FORMAT_D16_XYZW,"BUFFER_LOAD_FORMAT_D16_XYZW"} ,//11 + {amdgpu_gfx940_op_BUFFER_STORE_FORMAT_D16_X,"BUFFER_STORE_FORMAT_D16_X"} ,//12 + {amdgpu_gfx940_op_BUFFER_STORE_FORMAT_D16_XY,"BUFFER_STORE_FORMAT_D16_XY"} ,//13 + {amdgpu_gfx940_op_BUFFER_STORE_FORMAT_D16_XYZ,"BUFFER_STORE_FORMAT_D16_XYZ"} ,//14 + {amdgpu_gfx940_op_BUFFER_STORE_FORMAT_D16_XYZW,"BUFFER_STORE_FORMAT_D16_XYZW"} ,//15 + {amdgpu_gfx940_op_BUFFER_LOAD_UBYTE,"BUFFER_LOAD_UBYTE"} ,//16 + {amdgpu_gfx940_op_BUFFER_LOAD_SBYTE,"BUFFER_LOAD_SBYTE"} ,//17 + {amdgpu_gfx940_op_BUFFER_LOAD_USHORT,"BUFFER_LOAD_USHORT"} ,//18 + {amdgpu_gfx940_op_BUFFER_LOAD_SSHORT,"BUFFER_LOAD_SSHORT"} ,//19 + {amdgpu_gfx940_op_BUFFER_LOAD_DWORD,"BUFFER_LOAD_DWORD"} ,//20 + {amdgpu_gfx940_op_BUFFER_LOAD_DWORDX2,"BUFFER_LOAD_DWORDX2"} ,//21 + {amdgpu_gfx940_op_BUFFER_LOAD_DWORDX3,"BUFFER_LOAD_DWORDX3"} ,//22 + {amdgpu_gfx940_op_BUFFER_LOAD_DWORDX4,"BUFFER_LOAD_DWORDX4"} ,//23 + {amdgpu_gfx940_op_BUFFER_STORE_BYTE,"BUFFER_STORE_BYTE"} ,//24 + {amdgpu_gfx940_op_BUFFER_STORE_BYTE_D16_HI,"BUFFER_STORE_BYTE_D16_HI"} ,//25 + {amdgpu_gfx940_op_BUFFER_STORE_SHORT,"BUFFER_STORE_SHORT"} ,//26 + {amdgpu_gfx940_op_BUFFER_STORE_SHORT_D16_HI,"BUFFER_STORE_SHORT_D16_HI"} ,//27 + {amdgpu_gfx940_op_BUFFER_STORE_DWORD,"BUFFER_STORE_DWORD"} ,//28 + {amdgpu_gfx940_op_BUFFER_STORE_DWORDX2,"BUFFER_STORE_DWORDX2"} ,//29 + {amdgpu_gfx940_op_BUFFER_STORE_DWORDX3,"BUFFER_STORE_DWORDX3"} ,//30 + {amdgpu_gfx940_op_BUFFER_STORE_DWORDX4,"BUFFER_STORE_DWORDX4"} ,//31 + {amdgpu_gfx940_op_BUFFER_LOAD_UBYTE_D16,"BUFFER_LOAD_UBYTE_D16"} ,//32 + {amdgpu_gfx940_op_BUFFER_LOAD_UBYTE_D16_HI,"BUFFER_LOAD_UBYTE_D16_HI"} ,//33 + {amdgpu_gfx940_op_BUFFER_LOAD_SBYTE_D16,"BUFFER_LOAD_SBYTE_D16"} ,//34 + {amdgpu_gfx940_op_BUFFER_LOAD_SBYTE_D16_HI,"BUFFER_LOAD_SBYTE_D16_HI"} ,//35 + {amdgpu_gfx940_op_BUFFER_LOAD_SHORT_D16,"BUFFER_LOAD_SHORT_D16"} ,//36 + {amdgpu_gfx940_op_BUFFER_LOAD_SHORT_D16_HI,"BUFFER_LOAD_SHORT_D16_HI"} ,//37 + {amdgpu_gfx940_op_BUFFER_LOAD_FORMAT_D16_HI_X,"BUFFER_LOAD_FORMAT_D16_HI_X"} ,//38 + {amdgpu_gfx940_op_BUFFER_STORE_FORMAT_D16_HI_X,"BUFFER_STORE_FORMAT_D16_HI_X"} ,//39 + {amdgpu_gfx940_op_BUFFER_WBL2,"BUFFER_WBL2"} ,//40 + {amdgpu_gfx940_op_BUFFER_INV,"BUFFER_INV"} ,//41 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//42 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//43 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//44 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//45 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//46 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//47 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//48 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//49 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//50 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//51 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//52 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//53 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//54 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//55 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//56 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//57 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//58 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//59 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//60 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//61 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//62 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//63 + {amdgpu_gfx940_op_BUFFER_ATOMIC_SWAP,"BUFFER_ATOMIC_SWAP"} ,//64 + {amdgpu_gfx940_op_BUFFER_ATOMIC_CMPSWAP,"BUFFER_ATOMIC_CMPSWAP"} ,//65 + {amdgpu_gfx940_op_BUFFER_ATOMIC_ADD,"BUFFER_ATOMIC_ADD"} ,//66 + {amdgpu_gfx940_op_BUFFER_ATOMIC_SUB,"BUFFER_ATOMIC_SUB"} ,//67 + {amdgpu_gfx940_op_BUFFER_ATOMIC_SMIN,"BUFFER_ATOMIC_SMIN"} ,//68 + {amdgpu_gfx940_op_BUFFER_ATOMIC_UMIN,"BUFFER_ATOMIC_UMIN"} ,//69 + {amdgpu_gfx940_op_BUFFER_ATOMIC_SMAX,"BUFFER_ATOMIC_SMAX"} ,//70 + {amdgpu_gfx940_op_BUFFER_ATOMIC_UMAX,"BUFFER_ATOMIC_UMAX"} ,//71 + {amdgpu_gfx940_op_BUFFER_ATOMIC_AND,"BUFFER_ATOMIC_AND"} ,//72 + {amdgpu_gfx940_op_BUFFER_ATOMIC_OR,"BUFFER_ATOMIC_OR"} ,//73 + {amdgpu_gfx940_op_BUFFER_ATOMIC_XOR,"BUFFER_ATOMIC_XOR"} ,//74 + {amdgpu_gfx940_op_BUFFER_ATOMIC_INC,"BUFFER_ATOMIC_INC"} ,//75 + {amdgpu_gfx940_op_BUFFER_ATOMIC_DEC,"BUFFER_ATOMIC_DEC"} ,//76 + {amdgpu_gfx940_op_BUFFER_ATOMIC_ADD_F32,"BUFFER_ATOMIC_ADD_F32"} ,//77 + {amdgpu_gfx940_op_BUFFER_ATOMIC_PK_ADD_F16,"BUFFER_ATOMIC_PK_ADD_F16"} ,//78 + {amdgpu_gfx940_op_BUFFER_ATOMIC_ADD_F64,"BUFFER_ATOMIC_ADD_F64"} ,//79 + {amdgpu_gfx940_op_BUFFER_ATOMIC_MIN_F64,"BUFFER_ATOMIC_MIN_F64"} ,//80 + {amdgpu_gfx940_op_BUFFER_ATOMIC_MAX_F64,"BUFFER_ATOMIC_MAX_F64"} ,//81 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//82 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//83 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//84 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//85 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//86 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//87 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//88 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//89 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//90 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//91 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//92 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//93 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//94 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//95 + {amdgpu_gfx940_op_BUFFER_ATOMIC_SWAP_X2,"BUFFER_ATOMIC_SWAP_X2"} ,//96 + {amdgpu_gfx940_op_BUFFER_ATOMIC_CMPSWAP_X2,"BUFFER_ATOMIC_CMPSWAP_X2"} ,//97 + {amdgpu_gfx940_op_BUFFER_ATOMIC_ADD_X2,"BUFFER_ATOMIC_ADD_X2"} ,//98 + {amdgpu_gfx940_op_BUFFER_ATOMIC_SUB_X2,"BUFFER_ATOMIC_SUB_X2"} ,//99 + {amdgpu_gfx940_op_BUFFER_ATOMIC_SMIN_X2,"BUFFER_ATOMIC_SMIN_X2"} ,//100 + {amdgpu_gfx940_op_BUFFER_ATOMIC_UMIN_X2,"BUFFER_ATOMIC_UMIN_X2"} ,//101 + {amdgpu_gfx940_op_BUFFER_ATOMIC_SMAX_X2,"BUFFER_ATOMIC_SMAX_X2"} ,//102 + {amdgpu_gfx940_op_BUFFER_ATOMIC_UMAX_X2,"BUFFER_ATOMIC_UMAX_X2"} ,//103 + {amdgpu_gfx940_op_BUFFER_ATOMIC_AND_X2,"BUFFER_ATOMIC_AND_X2"} ,//104 + {amdgpu_gfx940_op_BUFFER_ATOMIC_OR_X2,"BUFFER_ATOMIC_OR_X2"} ,//105 + {amdgpu_gfx940_op_BUFFER_ATOMIC_XOR_X2,"BUFFER_ATOMIC_XOR_X2"} ,//106 + {amdgpu_gfx940_op_BUFFER_ATOMIC_INC_X2,"BUFFER_ATOMIC_INC_X2"} ,//107 + {amdgpu_gfx940_op_BUFFER_ATOMIC_DEC_X2,"BUFFER_ATOMIC_DEC_X2"} ,//108 + }; // end ENC_MUBUF_insn_table + const amdgpu_gfx940_insn_entry ENC_SMEM_insn_table [173] = + { + {amdgpu_gfx940_op_S_LOAD_DWORD,"S_LOAD_DWORD"} ,//0 + {amdgpu_gfx940_op_S_LOAD_DWORDX2,"S_LOAD_DWORDX2"} ,//1 + {amdgpu_gfx940_op_S_LOAD_DWORDX4,"S_LOAD_DWORDX4"} ,//2 + {amdgpu_gfx940_op_S_LOAD_DWORDX8,"S_LOAD_DWORDX8"} ,//3 + {amdgpu_gfx940_op_S_LOAD_DWORDX16,"S_LOAD_DWORDX16"} ,//4 + {amdgpu_gfx940_op_S_SCRATCH_LOAD_DWORD,"S_SCRATCH_LOAD_DWORD"} ,//5 + {amdgpu_gfx940_op_S_SCRATCH_LOAD_DWORDX2,"S_SCRATCH_LOAD_DWORDX2"} ,//6 + {amdgpu_gfx940_op_S_SCRATCH_LOAD_DWORDX4,"S_SCRATCH_LOAD_DWORDX4"} ,//7 + {amdgpu_gfx940_op_S_BUFFER_LOAD_DWORD,"S_BUFFER_LOAD_DWORD"} ,//8 + {amdgpu_gfx940_op_S_BUFFER_LOAD_DWORDX2,"S_BUFFER_LOAD_DWORDX2"} ,//9 + {amdgpu_gfx940_op_S_BUFFER_LOAD_DWORDX4,"S_BUFFER_LOAD_DWORDX4"} ,//10 + {amdgpu_gfx940_op_S_BUFFER_LOAD_DWORDX8,"S_BUFFER_LOAD_DWORDX8"} ,//11 + {amdgpu_gfx940_op_S_BUFFER_LOAD_DWORDX16,"S_BUFFER_LOAD_DWORDX16"} ,//12 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//13 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//14 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//15 + {amdgpu_gfx940_op_S_STORE_DWORD,"S_STORE_DWORD"} ,//16 + {amdgpu_gfx940_op_S_STORE_DWORDX2,"S_STORE_DWORDX2"} ,//17 + {amdgpu_gfx940_op_S_STORE_DWORDX4,"S_STORE_DWORDX4"} ,//18 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//19 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//20 + {amdgpu_gfx940_op_S_SCRATCH_STORE_DWORD,"S_SCRATCH_STORE_DWORD"} ,//21 + {amdgpu_gfx940_op_S_SCRATCH_STORE_DWORDX2,"S_SCRATCH_STORE_DWORDX2"} ,//22 + {amdgpu_gfx940_op_S_SCRATCH_STORE_DWORDX4,"S_SCRATCH_STORE_DWORDX4"} ,//23 + {amdgpu_gfx940_op_S_BUFFER_STORE_DWORD,"S_BUFFER_STORE_DWORD"} ,//24 + {amdgpu_gfx940_op_S_BUFFER_STORE_DWORDX2,"S_BUFFER_STORE_DWORDX2"} ,//25 + {amdgpu_gfx940_op_S_BUFFER_STORE_DWORDX4,"S_BUFFER_STORE_DWORDX4"} ,//26 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//27 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//28 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//29 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//30 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//31 + {amdgpu_gfx940_op_S_DCACHE_INV,"S_DCACHE_INV"} ,//32 + {amdgpu_gfx940_op_S_DCACHE_WB,"S_DCACHE_WB"} ,//33 + {amdgpu_gfx940_op_S_DCACHE_INV_VOL,"S_DCACHE_INV_VOL"} ,//34 + {amdgpu_gfx940_op_S_DCACHE_WB_VOL,"S_DCACHE_WB_VOL"} ,//35 + {amdgpu_gfx940_op_S_MEMTIME,"S_MEMTIME"} ,//36 + {amdgpu_gfx940_op_S_MEMREALTIME,"S_MEMREALTIME"} ,//37 + {amdgpu_gfx940_op_S_ATC_PROBE,"S_ATC_PROBE"} ,//38 + {amdgpu_gfx940_op_S_ATC_PROBE_BUFFER,"S_ATC_PROBE_BUFFER"} ,//39 + {amdgpu_gfx940_op_S_DCACHE_DISCARD,"S_DCACHE_DISCARD"} ,//40 + {amdgpu_gfx940_op_S_DCACHE_DISCARD_X2,"S_DCACHE_DISCARD_X2"} ,//41 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//42 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//43 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//44 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//45 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//46 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//47 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//48 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//49 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//50 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//51 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//52 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//53 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//54 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//55 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//56 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//57 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//58 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//59 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//60 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//61 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//62 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//63 + {amdgpu_gfx940_op_S_BUFFER_ATOMIC_SWAP,"S_BUFFER_ATOMIC_SWAP"} ,//64 + {amdgpu_gfx940_op_S_BUFFER_ATOMIC_CMPSWAP,"S_BUFFER_ATOMIC_CMPSWAP"} ,//65 + {amdgpu_gfx940_op_S_BUFFER_ATOMIC_ADD,"S_BUFFER_ATOMIC_ADD"} ,//66 + {amdgpu_gfx940_op_S_BUFFER_ATOMIC_SUB,"S_BUFFER_ATOMIC_SUB"} ,//67 + {amdgpu_gfx940_op_S_BUFFER_ATOMIC_SMIN,"S_BUFFER_ATOMIC_SMIN"} ,//68 + {amdgpu_gfx940_op_S_BUFFER_ATOMIC_UMIN,"S_BUFFER_ATOMIC_UMIN"} ,//69 + {amdgpu_gfx940_op_S_BUFFER_ATOMIC_SMAX,"S_BUFFER_ATOMIC_SMAX"} ,//70 + {amdgpu_gfx940_op_S_BUFFER_ATOMIC_UMAX,"S_BUFFER_ATOMIC_UMAX"} ,//71 + {amdgpu_gfx940_op_S_BUFFER_ATOMIC_AND,"S_BUFFER_ATOMIC_AND"} ,//72 + {amdgpu_gfx940_op_S_BUFFER_ATOMIC_OR,"S_BUFFER_ATOMIC_OR"} ,//73 + {amdgpu_gfx940_op_S_BUFFER_ATOMIC_XOR,"S_BUFFER_ATOMIC_XOR"} ,//74 + {amdgpu_gfx940_op_S_BUFFER_ATOMIC_INC,"S_BUFFER_ATOMIC_INC"} ,//75 + {amdgpu_gfx940_op_S_BUFFER_ATOMIC_DEC,"S_BUFFER_ATOMIC_DEC"} ,//76 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//77 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//78 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//79 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//80 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//81 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//82 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//83 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//84 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//85 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//86 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//87 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//88 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//89 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//90 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//91 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//92 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//93 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//94 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//95 + {amdgpu_gfx940_op_S_BUFFER_ATOMIC_SWAP_X2,"S_BUFFER_ATOMIC_SWAP_X2"} ,//96 + {amdgpu_gfx940_op_S_BUFFER_ATOMIC_CMPSWAP_X2,"S_BUFFER_ATOMIC_CMPSWAP_X2"} ,//97 + {amdgpu_gfx940_op_S_BUFFER_ATOMIC_ADD_X2,"S_BUFFER_ATOMIC_ADD_X2"} ,//98 + {amdgpu_gfx940_op_S_BUFFER_ATOMIC_SUB_X2,"S_BUFFER_ATOMIC_SUB_X2"} ,//99 + {amdgpu_gfx940_op_S_BUFFER_ATOMIC_SMIN_X2,"S_BUFFER_ATOMIC_SMIN_X2"} ,//100 + {amdgpu_gfx940_op_S_BUFFER_ATOMIC_UMIN_X2,"S_BUFFER_ATOMIC_UMIN_X2"} ,//101 + {amdgpu_gfx940_op_S_BUFFER_ATOMIC_SMAX_X2,"S_BUFFER_ATOMIC_SMAX_X2"} ,//102 + {amdgpu_gfx940_op_S_BUFFER_ATOMIC_UMAX_X2,"S_BUFFER_ATOMIC_UMAX_X2"} ,//103 + {amdgpu_gfx940_op_S_BUFFER_ATOMIC_AND_X2,"S_BUFFER_ATOMIC_AND_X2"} ,//104 + {amdgpu_gfx940_op_S_BUFFER_ATOMIC_OR_X2,"S_BUFFER_ATOMIC_OR_X2"} ,//105 + {amdgpu_gfx940_op_S_BUFFER_ATOMIC_XOR_X2,"S_BUFFER_ATOMIC_XOR_X2"} ,//106 + {amdgpu_gfx940_op_S_BUFFER_ATOMIC_INC_X2,"S_BUFFER_ATOMIC_INC_X2"} ,//107 + {amdgpu_gfx940_op_S_BUFFER_ATOMIC_DEC_X2,"S_BUFFER_ATOMIC_DEC_X2"} ,//108 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//109 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//110 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//111 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//112 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//113 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//114 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//115 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//116 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//117 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//118 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//119 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//120 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//121 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//122 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//123 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//124 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//125 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//126 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//127 + {amdgpu_gfx940_op_S_ATOMIC_SWAP,"S_ATOMIC_SWAP"} ,//128 + {amdgpu_gfx940_op_S_ATOMIC_CMPSWAP,"S_ATOMIC_CMPSWAP"} ,//129 + {amdgpu_gfx940_op_S_ATOMIC_ADD,"S_ATOMIC_ADD"} ,//130 + {amdgpu_gfx940_op_S_ATOMIC_SUB,"S_ATOMIC_SUB"} ,//131 + {amdgpu_gfx940_op_S_ATOMIC_SMIN,"S_ATOMIC_SMIN"} ,//132 + {amdgpu_gfx940_op_S_ATOMIC_UMIN,"S_ATOMIC_UMIN"} ,//133 + {amdgpu_gfx940_op_S_ATOMIC_SMAX,"S_ATOMIC_SMAX"} ,//134 + {amdgpu_gfx940_op_S_ATOMIC_UMAX,"S_ATOMIC_UMAX"} ,//135 + {amdgpu_gfx940_op_S_ATOMIC_AND,"S_ATOMIC_AND"} ,//136 + {amdgpu_gfx940_op_S_ATOMIC_OR,"S_ATOMIC_OR"} ,//137 + {amdgpu_gfx940_op_S_ATOMIC_XOR,"S_ATOMIC_XOR"} ,//138 + {amdgpu_gfx940_op_S_ATOMIC_INC,"S_ATOMIC_INC"} ,//139 + {amdgpu_gfx940_op_S_ATOMIC_DEC,"S_ATOMIC_DEC"} ,//140 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//141 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//142 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//143 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//144 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//145 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//146 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//147 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//148 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//149 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//150 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//151 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//152 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//153 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//154 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//155 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//156 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//157 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//158 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//159 + {amdgpu_gfx940_op_S_ATOMIC_SWAP_X2,"S_ATOMIC_SWAP_X2"} ,//160 + {amdgpu_gfx940_op_S_ATOMIC_CMPSWAP_X2,"S_ATOMIC_CMPSWAP_X2"} ,//161 + {amdgpu_gfx940_op_S_ATOMIC_ADD_X2,"S_ATOMIC_ADD_X2"} ,//162 + {amdgpu_gfx940_op_S_ATOMIC_SUB_X2,"S_ATOMIC_SUB_X2"} ,//163 + {amdgpu_gfx940_op_S_ATOMIC_SMIN_X2,"S_ATOMIC_SMIN_X2"} ,//164 + {amdgpu_gfx940_op_S_ATOMIC_UMIN_X2,"S_ATOMIC_UMIN_X2"} ,//165 + {amdgpu_gfx940_op_S_ATOMIC_SMAX_X2,"S_ATOMIC_SMAX_X2"} ,//166 + {amdgpu_gfx940_op_S_ATOMIC_UMAX_X2,"S_ATOMIC_UMAX_X2"} ,//167 + {amdgpu_gfx940_op_S_ATOMIC_AND_X2,"S_ATOMIC_AND_X2"} ,//168 + {amdgpu_gfx940_op_S_ATOMIC_OR_X2,"S_ATOMIC_OR_X2"} ,//169 + {amdgpu_gfx940_op_S_ATOMIC_XOR_X2,"S_ATOMIC_XOR_X2"} ,//170 + {amdgpu_gfx940_op_S_ATOMIC_INC_X2,"S_ATOMIC_INC_X2"} ,//171 + {amdgpu_gfx940_op_S_ATOMIC_DEC_X2,"S_ATOMIC_DEC_X2"} ,//172 + }; // end ENC_SMEM_insn_table + const amdgpu_gfx940_insn_entry ENC_SOP1_insn_table [56] = + { + {amdgpu_gfx940_op_S_MOV_B32,"S_MOV_B32"} ,//0 + {amdgpu_gfx940_op_S_MOV_B64,"S_MOV_B64"} ,//1 + {amdgpu_gfx940_op_S_CMOV_B32,"S_CMOV_B32"} ,//2 + {amdgpu_gfx940_op_S_CMOV_B64,"S_CMOV_B64"} ,//3 + {amdgpu_gfx940_op_S_NOT_B32,"S_NOT_B32"} ,//4 + {amdgpu_gfx940_op_S_NOT_B64,"S_NOT_B64"} ,//5 + {amdgpu_gfx940_op_S_WQM_B32,"S_WQM_B32"} ,//6 + {amdgpu_gfx940_op_S_WQM_B64,"S_WQM_B64"} ,//7 + {amdgpu_gfx940_op_S_BREV_B32,"S_BREV_B32"} ,//8 + {amdgpu_gfx940_op_S_BREV_B64,"S_BREV_B64"} ,//9 + {amdgpu_gfx940_op_S_BCNT0_I32_B32,"S_BCNT0_I32_B32"} ,//10 + {amdgpu_gfx940_op_S_BCNT0_I32_B64,"S_BCNT0_I32_B64"} ,//11 + {amdgpu_gfx940_op_S_BCNT1_I32_B32,"S_BCNT1_I32_B32"} ,//12 + {amdgpu_gfx940_op_S_BCNT1_I32_B64,"S_BCNT1_I32_B64"} ,//13 + {amdgpu_gfx940_op_S_FF0_I32_B32,"S_FF0_I32_B32"} ,//14 + {amdgpu_gfx940_op_S_FF0_I32_B64,"S_FF0_I32_B64"} ,//15 + {amdgpu_gfx940_op_S_FF1_I32_B32,"S_FF1_I32_B32"} ,//16 + {amdgpu_gfx940_op_S_FF1_I32_B64,"S_FF1_I32_B64"} ,//17 + {amdgpu_gfx940_op_S_FLBIT_I32_B32,"S_FLBIT_I32_B32"} ,//18 + {amdgpu_gfx940_op_S_FLBIT_I32_B64,"S_FLBIT_I32_B64"} ,//19 + {amdgpu_gfx940_op_S_FLBIT_I32,"S_FLBIT_I32"} ,//20 + {amdgpu_gfx940_op_S_FLBIT_I32_I64,"S_FLBIT_I32_I64"} ,//21 + {amdgpu_gfx940_op_S_SEXT_I32_I8,"S_SEXT_I32_I8"} ,//22 + {amdgpu_gfx940_op_S_SEXT_I32_I16,"S_SEXT_I32_I16"} ,//23 + {amdgpu_gfx940_op_S_BITSET0_B32,"S_BITSET0_B32"} ,//24 + {amdgpu_gfx940_op_S_BITSET0_B64,"S_BITSET0_B64"} ,//25 + {amdgpu_gfx940_op_S_BITSET1_B32,"S_BITSET1_B32"} ,//26 + {amdgpu_gfx940_op_S_BITSET1_B64,"S_BITSET1_B64"} ,//27 + {amdgpu_gfx940_op_S_GETPC_B64,"S_GETPC_B64"} ,//28 + {amdgpu_gfx940_op_S_SETPC_B64,"S_SETPC_B64"} ,//29 + {amdgpu_gfx940_op_S_SWAPPC_B64,"S_SWAPPC_B64"} ,//30 + {amdgpu_gfx940_op_S_RFE_B64,"S_RFE_B64"} ,//31 + {amdgpu_gfx940_op_S_AND_SAVEEXEC_B64,"S_AND_SAVEEXEC_B64"} ,//32 + {amdgpu_gfx940_op_S_OR_SAVEEXEC_B64,"S_OR_SAVEEXEC_B64"} ,//33 + {amdgpu_gfx940_op_S_XOR_SAVEEXEC_B64,"S_XOR_SAVEEXEC_B64"} ,//34 + {amdgpu_gfx940_op_S_ANDN2_SAVEEXEC_B64,"S_ANDN2_SAVEEXEC_B64"} ,//35 + {amdgpu_gfx940_op_S_ORN2_SAVEEXEC_B64,"S_ORN2_SAVEEXEC_B64"} ,//36 + {amdgpu_gfx940_op_S_NAND_SAVEEXEC_B64,"S_NAND_SAVEEXEC_B64"} ,//37 + {amdgpu_gfx940_op_S_NOR_SAVEEXEC_B64,"S_NOR_SAVEEXEC_B64"} ,//38 + {amdgpu_gfx940_op_S_XNOR_SAVEEXEC_B64,"S_XNOR_SAVEEXEC_B64"} ,//39 + {amdgpu_gfx940_op_S_QUADMASK_B32,"S_QUADMASK_B32"} ,//40 + {amdgpu_gfx940_op_S_QUADMASK_B64,"S_QUADMASK_B64"} ,//41 + {amdgpu_gfx940_op_S_MOVRELS_B32,"S_MOVRELS_B32"} ,//42 + {amdgpu_gfx940_op_S_MOVRELS_B64,"S_MOVRELS_B64"} ,//43 + {amdgpu_gfx940_op_S_MOVRELD_B32,"S_MOVRELD_B32"} ,//44 + {amdgpu_gfx940_op_S_MOVRELD_B64,"S_MOVRELD_B64"} ,//45 + {amdgpu_gfx940_op_S_CBRANCH_JOIN,"S_CBRANCH_JOIN"} ,//46 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//47 + {amdgpu_gfx940_op_S_ABS_I32,"S_ABS_I32"} ,//48 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//49 + {amdgpu_gfx940_op_S_SET_GPR_IDX_IDX,"S_SET_GPR_IDX_IDX"} ,//50 + {amdgpu_gfx940_op_S_ANDN1_SAVEEXEC_B64,"S_ANDN1_SAVEEXEC_B64"} ,//51 + {amdgpu_gfx940_op_S_ORN1_SAVEEXEC_B64,"S_ORN1_SAVEEXEC_B64"} ,//52 + {amdgpu_gfx940_op_S_ANDN1_WREXEC_B64,"S_ANDN1_WREXEC_B64"} ,//53 + {amdgpu_gfx940_op_S_ANDN2_WREXEC_B64,"S_ANDN2_WREXEC_B64"} ,//54 + {amdgpu_gfx940_op_S_BITREPLICATE_B64_B32,"S_BITREPLICATE_B64_B32"} ,//55 + }; // end ENC_SOP1_insn_table + const amdgpu_gfx940_insn_entry ENC_SOP2_insn_table [53] = + { + {amdgpu_gfx940_op_S_ADD_U32,"S_ADD_U32"} ,//0 + {amdgpu_gfx940_op_S_SUB_U32,"S_SUB_U32"} ,//1 + {amdgpu_gfx940_op_S_ADD_I32,"S_ADD_I32"} ,//2 + {amdgpu_gfx940_op_S_SUB_I32,"S_SUB_I32"} ,//3 + {amdgpu_gfx940_op_S_ADDC_U32,"S_ADDC_U32"} ,//4 + {amdgpu_gfx940_op_S_SUBB_U32,"S_SUBB_U32"} ,//5 + {amdgpu_gfx940_op_S_MIN_I32,"S_MIN_I32"} ,//6 + {amdgpu_gfx940_op_S_MIN_U32,"S_MIN_U32"} ,//7 + {amdgpu_gfx940_op_S_MAX_I32,"S_MAX_I32"} ,//8 + {amdgpu_gfx940_op_S_MAX_U32,"S_MAX_U32"} ,//9 + {amdgpu_gfx940_op_S_CSELECT_B32,"S_CSELECT_B32"} ,//10 + {amdgpu_gfx940_op_S_CSELECT_B64,"S_CSELECT_B64"} ,//11 + {amdgpu_gfx940_op_S_AND_B32,"S_AND_B32"} ,//12 + {amdgpu_gfx940_op_S_AND_B64,"S_AND_B64"} ,//13 + {amdgpu_gfx940_op_S_OR_B32,"S_OR_B32"} ,//14 + {amdgpu_gfx940_op_S_OR_B64,"S_OR_B64"} ,//15 + {amdgpu_gfx940_op_S_XOR_B32,"S_XOR_B32"} ,//16 + {amdgpu_gfx940_op_S_XOR_B64,"S_XOR_B64"} ,//17 + {amdgpu_gfx940_op_S_ANDN2_B32,"S_ANDN2_B32"} ,//18 + {amdgpu_gfx940_op_S_ANDN2_B64,"S_ANDN2_B64"} ,//19 + {amdgpu_gfx940_op_S_ORN2_B32,"S_ORN2_B32"} ,//20 + {amdgpu_gfx940_op_S_ORN2_B64,"S_ORN2_B64"} ,//21 + {amdgpu_gfx940_op_S_NAND_B32,"S_NAND_B32"} ,//22 + {amdgpu_gfx940_op_S_NAND_B64,"S_NAND_B64"} ,//23 + {amdgpu_gfx940_op_S_NOR_B32,"S_NOR_B32"} ,//24 + {amdgpu_gfx940_op_S_NOR_B64,"S_NOR_B64"} ,//25 + {amdgpu_gfx940_op_S_XNOR_B32,"S_XNOR_B32"} ,//26 + {amdgpu_gfx940_op_S_XNOR_B64,"S_XNOR_B64"} ,//27 + {amdgpu_gfx940_op_S_LSHL_B32,"S_LSHL_B32"} ,//28 + {amdgpu_gfx940_op_S_LSHL_B64,"S_LSHL_B64"} ,//29 + {amdgpu_gfx940_op_S_LSHR_B32,"S_LSHR_B32"} ,//30 + {amdgpu_gfx940_op_S_LSHR_B64,"S_LSHR_B64"} ,//31 + {amdgpu_gfx940_op_S_ASHR_I32,"S_ASHR_I32"} ,//32 + {amdgpu_gfx940_op_S_ASHR_I64,"S_ASHR_I64"} ,//33 + {amdgpu_gfx940_op_S_BFM_B32,"S_BFM_B32"} ,//34 + {amdgpu_gfx940_op_S_BFM_B64,"S_BFM_B64"} ,//35 + {amdgpu_gfx940_op_S_MUL_I32,"S_MUL_I32"} ,//36 + {amdgpu_gfx940_op_S_BFE_U32,"S_BFE_U32"} ,//37 + {amdgpu_gfx940_op_S_BFE_I32,"S_BFE_I32"} ,//38 + {amdgpu_gfx940_op_S_BFE_U64,"S_BFE_U64"} ,//39 + {amdgpu_gfx940_op_S_BFE_I64,"S_BFE_I64"} ,//40 + {amdgpu_gfx940_op_S_CBRANCH_G_FORK,"S_CBRANCH_G_FORK"} ,//41 + {amdgpu_gfx940_op_S_ABSDIFF_I32,"S_ABSDIFF_I32"} ,//42 + {amdgpu_gfx940_op_S_RFE_RESTORE_B64,"S_RFE_RESTORE_B64"} ,//43 + {amdgpu_gfx940_op_S_MUL_HI_U32,"S_MUL_HI_U32"} ,//44 + {amdgpu_gfx940_op_S_MUL_HI_I32,"S_MUL_HI_I32"} ,//45 + {amdgpu_gfx940_op_S_LSHL1_ADD_U32,"S_LSHL1_ADD_U32"} ,//46 + {amdgpu_gfx940_op_S_LSHL2_ADD_U32,"S_LSHL2_ADD_U32"} ,//47 + {amdgpu_gfx940_op_S_LSHL3_ADD_U32,"S_LSHL3_ADD_U32"} ,//48 + {amdgpu_gfx940_op_S_LSHL4_ADD_U32,"S_LSHL4_ADD_U32"} ,//49 + {amdgpu_gfx940_op_S_PACK_LL_B32_B16,"S_PACK_LL_B32_B16"} ,//50 + {amdgpu_gfx940_op_S_PACK_LH_B32_B16,"S_PACK_LH_B32_B16"} ,//51 + {amdgpu_gfx940_op_S_PACK_HH_B32_B16,"S_PACK_HH_B32_B16"} ,//52 + }; // end ENC_SOP2_insn_table + const amdgpu_gfx940_insn_entry ENC_SOPC_insn_table [20] = + { + {amdgpu_gfx940_op_S_CMP_EQ_I32,"S_CMP_EQ_I32"} ,//0 + {amdgpu_gfx940_op_S_CMP_LG_I32,"S_CMP_LG_I32"} ,//1 + {amdgpu_gfx940_op_S_CMP_GT_I32,"S_CMP_GT_I32"} ,//2 + {amdgpu_gfx940_op_S_CMP_GE_I32,"S_CMP_GE_I32"} ,//3 + {amdgpu_gfx940_op_S_CMP_LT_I32,"S_CMP_LT_I32"} ,//4 + {amdgpu_gfx940_op_S_CMP_LE_I32,"S_CMP_LE_I32"} ,//5 + {amdgpu_gfx940_op_S_CMP_EQ_U32,"S_CMP_EQ_U32"} ,//6 + {amdgpu_gfx940_op_S_CMP_LG_U32,"S_CMP_LG_U32"} ,//7 + {amdgpu_gfx940_op_S_CMP_GT_U32,"S_CMP_GT_U32"} ,//8 + {amdgpu_gfx940_op_S_CMP_GE_U32,"S_CMP_GE_U32"} ,//9 + {amdgpu_gfx940_op_S_CMP_LT_U32,"S_CMP_LT_U32"} ,//10 + {amdgpu_gfx940_op_S_CMP_LE_U32,"S_CMP_LE_U32"} ,//11 + {amdgpu_gfx940_op_S_BITCMP0_B32,"S_BITCMP0_B32"} ,//12 + {amdgpu_gfx940_op_S_BITCMP1_B32,"S_BITCMP1_B32"} ,//13 + {amdgpu_gfx940_op_S_BITCMP0_B64,"S_BITCMP0_B64"} ,//14 + {amdgpu_gfx940_op_S_BITCMP1_B64,"S_BITCMP1_B64"} ,//15 + {amdgpu_gfx940_op_S_SETVSKIP,"S_SETVSKIP"} ,//16 + {amdgpu_gfx940_op_S_SET_GPR_IDX_ON,"S_SET_GPR_IDX_ON"} ,//17 + {amdgpu_gfx940_op_S_CMP_EQ_U64,"S_CMP_EQ_U64"} ,//18 + {amdgpu_gfx940_op_S_CMP_LG_U64,"S_CMP_LG_U64"} ,//19 + }; // end ENC_SOPC_insn_table + const amdgpu_gfx940_insn_entry ENC_SOPK_insn_table [22] = + { + {amdgpu_gfx940_op_S_MOVK_I32,"S_MOVK_I32"} ,//0 + {amdgpu_gfx940_op_S_CMOVK_I32,"S_CMOVK_I32"} ,//1 + {amdgpu_gfx940_op_S_CMPK_EQ_I32,"S_CMPK_EQ_I32"} ,//2 + {amdgpu_gfx940_op_S_CMPK_LG_I32,"S_CMPK_LG_I32"} ,//3 + {amdgpu_gfx940_op_S_CMPK_GT_I32,"S_CMPK_GT_I32"} ,//4 + {amdgpu_gfx940_op_S_CMPK_GE_I32,"S_CMPK_GE_I32"} ,//5 + {amdgpu_gfx940_op_S_CMPK_LT_I32,"S_CMPK_LT_I32"} ,//6 + {amdgpu_gfx940_op_S_CMPK_LE_I32,"S_CMPK_LE_I32"} ,//7 + {amdgpu_gfx940_op_S_CMPK_EQ_U32,"S_CMPK_EQ_U32"} ,//8 + {amdgpu_gfx940_op_S_CMPK_LG_U32,"S_CMPK_LG_U32"} ,//9 + {amdgpu_gfx940_op_S_CMPK_GT_U32,"S_CMPK_GT_U32"} ,//10 + {amdgpu_gfx940_op_S_CMPK_GE_U32,"S_CMPK_GE_U32"} ,//11 + {amdgpu_gfx940_op_S_CMPK_LT_U32,"S_CMPK_LT_U32"} ,//12 + {amdgpu_gfx940_op_S_CMPK_LE_U32,"S_CMPK_LE_U32"} ,//13 + {amdgpu_gfx940_op_S_ADDK_I32,"S_ADDK_I32"} ,//14 + {amdgpu_gfx940_op_S_MULK_I32,"S_MULK_I32"} ,//15 + {amdgpu_gfx940_op_S_CBRANCH_I_FORK,"S_CBRANCH_I_FORK"} ,//16 + {amdgpu_gfx940_op_S_GETREG_B32,"S_GETREG_B32"} ,//17 + {amdgpu_gfx940_op_S_SETREG_B32,"S_SETREG_B32"} ,//18 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//19 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//20 + {amdgpu_gfx940_op_S_CALL_B64,"S_CALL_B64"} ,//21 + }; // end ENC_SOPK_insn_table + const amdgpu_gfx940_insn_entry ENC_SOPP_insn_table [32] = + { + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//0 + {amdgpu_gfx940_op_S_ENDPGM,"S_ENDPGM"} ,//1 + {amdgpu_gfx940_op_S_BRANCH,"S_BRANCH"} ,//2 + {amdgpu_gfx940_op_S_WAKEUP,"S_WAKEUP"} ,//3 + {amdgpu_gfx940_op_S_CBRANCH_SCC0,"S_CBRANCH_SCC0"} ,//4 + {amdgpu_gfx940_op_S_CBRANCH_SCC1,"S_CBRANCH_SCC1"} ,//5 + {amdgpu_gfx940_op_S_CBRANCH_VCCZ,"S_CBRANCH_VCCZ"} ,//6 + {amdgpu_gfx940_op_S_CBRANCH_VCCNZ,"S_CBRANCH_VCCNZ"} ,//7 + {amdgpu_gfx940_op_S_CBRANCH_EXECZ,"S_CBRANCH_EXECZ"} ,//8 + {amdgpu_gfx940_op_S_CBRANCH_EXECNZ,"S_CBRANCH_EXECNZ"} ,//9 + {amdgpu_gfx940_op_S_BARRIER,"S_BARRIER"} ,//10 + {amdgpu_gfx940_op_S_SETKILL,"S_SETKILL"} ,//11 + {amdgpu_gfx940_op_S_WAITCNT,"S_WAITCNT"} ,//12 + {amdgpu_gfx940_op_S_SETHALT,"S_SETHALT"} ,//13 + {amdgpu_gfx940_op_S_SLEEP,"S_SLEEP"} ,//14 + {amdgpu_gfx940_op_S_SETPRIO,"S_SETPRIO"} ,//15 + {amdgpu_gfx940_op_S_SENDMSG,"S_SENDMSG"} ,//16 + {amdgpu_gfx940_op_S_SENDMSGHALT,"S_SENDMSGHALT"} ,//17 + {amdgpu_gfx940_op_S_TRAP,"S_TRAP"} ,//18 + {amdgpu_gfx940_op_S_ICACHE_INV,"S_ICACHE_INV"} ,//19 + {amdgpu_gfx940_op_S_INCPERFLEVEL,"S_INCPERFLEVEL"} ,//20 + {amdgpu_gfx940_op_S_DECPERFLEVEL,"S_DECPERFLEVEL"} ,//21 + {amdgpu_gfx940_op_S_TTRACEDATA,"S_TTRACEDATA"} ,//22 + {amdgpu_gfx940_op_S_CBRANCH_CDBGSYS,"S_CBRANCH_CDBGSYS"} ,//23 + {amdgpu_gfx940_op_S_CBRANCH_CDBGUSER,"S_CBRANCH_CDBGUSER"} ,//24 + {amdgpu_gfx940_op_S_CBRANCH_CDBGSYS_OR_USER,"S_CBRANCH_CDBGSYS_OR_USER"} ,//25 + {amdgpu_gfx940_op_S_CBRANCH_CDBGSYS_AND_USER,"S_CBRANCH_CDBGSYS_AND_USER"} ,//26 + {amdgpu_gfx940_op_S_ENDPGM_SAVED,"S_ENDPGM_SAVED"} ,//27 + {amdgpu_gfx940_op_S_SET_GPR_IDX_OFF,"S_SET_GPR_IDX_OFF"} ,//28 + {amdgpu_gfx940_op_S_SET_GPR_IDX_MODE,"S_SET_GPR_IDX_MODE"} ,//29 + {amdgpu_gfx940_op_S_ENDPGM_ORDERED_PS_DONE,"S_ENDPGM_ORDERED_PS_DONE"} ,//30 + {amdgpu_gfx940_op_S_SET_VALU_COEXEC_MODE,"S_SET_VALU_COEXEC_MODE"} ,//31 + }; // end ENC_SOPP_insn_table + const amdgpu_gfx940_insn_entry ENC_VOP1_insn_table [88] = + { + {amdgpu_gfx940_op_V_NOP,"V_NOP"} ,//0 + {amdgpu_gfx940_op_V_MOV_B32,"V_MOV_B32"} ,//1 + {amdgpu_gfx940_op_V_READFIRSTLANE_B32,"V_READFIRSTLANE_B32"} ,//2 + {amdgpu_gfx940_op_V_CVT_I32_F64,"V_CVT_I32_F64"} ,//3 + {amdgpu_gfx940_op_V_CVT_F64_I32,"V_CVT_F64_I32"} ,//4 + {amdgpu_gfx940_op_V_CVT_F32_I32,"V_CVT_F32_I32"} ,//5 + {amdgpu_gfx940_op_V_CVT_F32_U32,"V_CVT_F32_U32"} ,//6 + {amdgpu_gfx940_op_V_CVT_U32_F32,"V_CVT_U32_F32"} ,//7 + {amdgpu_gfx940_op_V_CVT_I32_F32,"V_CVT_I32_F32"} ,//8 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//9 + {amdgpu_gfx940_op_V_CVT_F16_F32,"V_CVT_F16_F32"} ,//10 + {amdgpu_gfx940_op_V_CVT_F32_F16,"V_CVT_F32_F16"} ,//11 + {amdgpu_gfx940_op_V_CVT_RPI_I32_F32,"V_CVT_RPI_I32_F32"} ,//12 + {amdgpu_gfx940_op_V_CVT_FLR_I32_F32,"V_CVT_FLR_I32_F32"} ,//13 + {amdgpu_gfx940_op_V_CVT_OFF_F32_I4,"V_CVT_OFF_F32_I4"} ,//14 + {amdgpu_gfx940_op_V_CVT_F32_F64,"V_CVT_F32_F64"} ,//15 + {amdgpu_gfx940_op_V_CVT_F64_F32,"V_CVT_F64_F32"} ,//16 + {amdgpu_gfx940_op_V_CVT_F32_UBYTE0,"V_CVT_F32_UBYTE0"} ,//17 + {amdgpu_gfx940_op_V_CVT_F32_UBYTE1,"V_CVT_F32_UBYTE1"} ,//18 + {amdgpu_gfx940_op_V_CVT_F32_UBYTE2,"V_CVT_F32_UBYTE2"} ,//19 + {amdgpu_gfx940_op_V_CVT_F32_UBYTE3,"V_CVT_F32_UBYTE3"} ,//20 + {amdgpu_gfx940_op_V_CVT_U32_F64,"V_CVT_U32_F64"} ,//21 + {amdgpu_gfx940_op_V_CVT_F64_U32,"V_CVT_F64_U32"} ,//22 + {amdgpu_gfx940_op_V_TRUNC_F64,"V_TRUNC_F64"} ,//23 + {amdgpu_gfx940_op_V_CEIL_F64,"V_CEIL_F64"} ,//24 + {amdgpu_gfx940_op_V_RNDNE_F64,"V_RNDNE_F64"} ,//25 + {amdgpu_gfx940_op_V_FLOOR_F64,"V_FLOOR_F64"} ,//26 + {amdgpu_gfx940_op_V_FRACT_F32,"V_FRACT_F32"} ,//27 + {amdgpu_gfx940_op_V_TRUNC_F32,"V_TRUNC_F32"} ,//28 + {amdgpu_gfx940_op_V_CEIL_F32,"V_CEIL_F32"} ,//29 + {amdgpu_gfx940_op_V_RNDNE_F32,"V_RNDNE_F32"} ,//30 + {amdgpu_gfx940_op_V_FLOOR_F32,"V_FLOOR_F32"} ,//31 + {amdgpu_gfx940_op_V_EXP_F32,"V_EXP_F32"} ,//32 + {amdgpu_gfx940_op_V_LOG_F32,"V_LOG_F32"} ,//33 + {amdgpu_gfx940_op_V_RCP_F32,"V_RCP_F32"} ,//34 + {amdgpu_gfx940_op_V_RCP_IFLAG_F32,"V_RCP_IFLAG_F32"} ,//35 + {amdgpu_gfx940_op_V_RSQ_F32,"V_RSQ_F32"} ,//36 + {amdgpu_gfx940_op_V_RCP_F64,"V_RCP_F64"} ,//37 + {amdgpu_gfx940_op_V_RSQ_F64,"V_RSQ_F64"} ,//38 + {amdgpu_gfx940_op_V_SQRT_F32,"V_SQRT_F32"} ,//39 + {amdgpu_gfx940_op_V_SQRT_F64,"V_SQRT_F64"} ,//40 + {amdgpu_gfx940_op_V_SIN_F32,"V_SIN_F32"} ,//41 + {amdgpu_gfx940_op_V_COS_F32,"V_COS_F32"} ,//42 + {amdgpu_gfx940_op_V_NOT_B32,"V_NOT_B32"} ,//43 + {amdgpu_gfx940_op_V_BFREV_B32,"V_BFREV_B32"} ,//44 + {amdgpu_gfx940_op_V_FFBH_U32,"V_FFBH_U32"} ,//45 + {amdgpu_gfx940_op_V_FFBL_B32,"V_FFBL_B32"} ,//46 + {amdgpu_gfx940_op_V_FFBH_I32,"V_FFBH_I32"} ,//47 + {amdgpu_gfx940_op_V_FREXP_EXP_I32_F64,"V_FREXP_EXP_I32_F64"} ,//48 + {amdgpu_gfx940_op_V_FREXP_MANT_F64,"V_FREXP_MANT_F64"} ,//49 + {amdgpu_gfx940_op_V_FRACT_F64,"V_FRACT_F64"} ,//50 + {amdgpu_gfx940_op_V_FREXP_EXP_I32_F32,"V_FREXP_EXP_I32_F32"} ,//51 + {amdgpu_gfx940_op_V_FREXP_MANT_F32,"V_FREXP_MANT_F32"} ,//52 + {amdgpu_gfx940_op_V_CLREXCP,"V_CLREXCP"} ,//53 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//54 + {amdgpu_gfx940_op_V_SCREEN_PARTITION_4SE_B32,"V_SCREEN_PARTITION_4SE_B32"} ,//55 + {amdgpu_gfx940_op_V_MOV_B64,"V_MOV_B64"} ,//56 + {amdgpu_gfx940_op_V_CVT_F16_U16,"V_CVT_F16_U16"} ,//57 + {amdgpu_gfx940_op_V_CVT_F16_I16,"V_CVT_F16_I16"} ,//58 + {amdgpu_gfx940_op_V_CVT_U16_F16,"V_CVT_U16_F16"} ,//59 + {amdgpu_gfx940_op_V_CVT_I16_F16,"V_CVT_I16_F16"} ,//60 + {amdgpu_gfx940_op_V_RCP_F16,"V_RCP_F16"} ,//61 + {amdgpu_gfx940_op_V_SQRT_F16,"V_SQRT_F16"} ,//62 + {amdgpu_gfx940_op_V_RSQ_F16,"V_RSQ_F16"} ,//63 + {amdgpu_gfx940_op_V_LOG_F16,"V_LOG_F16"} ,//64 + {amdgpu_gfx940_op_V_EXP_F16,"V_EXP_F16"} ,//65 + {amdgpu_gfx940_op_V_FREXP_MANT_F16,"V_FREXP_MANT_F16"} ,//66 + {amdgpu_gfx940_op_V_FREXP_EXP_I16_F16,"V_FREXP_EXP_I16_F16"} ,//67 + {amdgpu_gfx940_op_V_FLOOR_F16,"V_FLOOR_F16"} ,//68 + {amdgpu_gfx940_op_V_CEIL_F16,"V_CEIL_F16"} ,//69 + {amdgpu_gfx940_op_V_TRUNC_F16,"V_TRUNC_F16"} ,//70 + {amdgpu_gfx940_op_V_RNDNE_F16,"V_RNDNE_F16"} ,//71 + {amdgpu_gfx940_op_V_FRACT_F16,"V_FRACT_F16"} ,//72 + {amdgpu_gfx940_op_V_SIN_F16,"V_SIN_F16"} ,//73 + {amdgpu_gfx940_op_V_COS_F16,"V_COS_F16"} ,//74 + {amdgpu_gfx940_op_V_EXP_LEGACY_F32,"V_EXP_LEGACY_F32"} ,//75 + {amdgpu_gfx940_op_V_LOG_LEGACY_F32,"V_LOG_LEGACY_F32"} ,//76 + {amdgpu_gfx940_op_V_CVT_NORM_I16_F16,"V_CVT_NORM_I16_F16"} ,//77 + {amdgpu_gfx940_op_V_CVT_NORM_U16_F16,"V_CVT_NORM_U16_F16"} ,//78 + {amdgpu_gfx940_op_V_SAT_PK_U8_I16,"V_SAT_PK_U8_I16"} ,//79 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//80 + {amdgpu_gfx940_op_V_SWAP_B32,"V_SWAP_B32"} ,//81 + {amdgpu_gfx940_op_V_ACCVGPR_MOV_B32,"V_ACCVGPR_MOV_B32"} ,//82 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//83 + {amdgpu_gfx940_op_V_CVT_F32_FP8,"V_CVT_F32_FP8"} ,//84 + {amdgpu_gfx940_op_V_CVT_F32_BF8,"V_CVT_F32_BF8"} ,//85 + {amdgpu_gfx940_op_V_CVT_PK_F32_FP8,"V_CVT_PK_F32_FP8"} ,//86 + {amdgpu_gfx940_op_V_CVT_PK_F32_BF8,"V_CVT_PK_F32_BF8"} ,//87 + }; // end ENC_VOP1_insn_table + const amdgpu_gfx940_insn_entry ENC_VOP3_insn_table [678] = + { + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//0 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//1 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//2 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//3 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//4 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//5 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//6 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//7 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//8 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//9 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//10 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//11 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//12 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//13 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//14 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//15 + {amdgpu_gfx940_op_V_CMP_CLASS_F32,"V_CMP_CLASS_F32"} ,//16 + {amdgpu_gfx940_op_V_CMPX_CLASS_F32,"V_CMPX_CLASS_F32"} ,//17 + {amdgpu_gfx940_op_V_CMP_CLASS_F64,"V_CMP_CLASS_F64"} ,//18 + {amdgpu_gfx940_op_V_CMPX_CLASS_F64,"V_CMPX_CLASS_F64"} ,//19 + {amdgpu_gfx940_op_V_CMP_CLASS_F16,"V_CMP_CLASS_F16"} ,//20 + {amdgpu_gfx940_op_V_CMPX_CLASS_F16,"V_CMPX_CLASS_F16"} ,//21 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//22 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//23 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//24 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//25 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//26 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//27 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//28 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//29 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//30 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//31 + {amdgpu_gfx940_op_V_CMP_F_F16,"V_CMP_F_F16"} ,//32 + {amdgpu_gfx940_op_V_CMP_LT_F16,"V_CMP_LT_F16"} ,//33 + {amdgpu_gfx940_op_V_CMP_EQ_F16,"V_CMP_EQ_F16"} ,//34 + {amdgpu_gfx940_op_V_CMP_LE_F16,"V_CMP_LE_F16"} ,//35 + {amdgpu_gfx940_op_V_CMP_GT_F16,"V_CMP_GT_F16"} ,//36 + {amdgpu_gfx940_op_V_CMP_LG_F16,"V_CMP_LG_F16"} ,//37 + {amdgpu_gfx940_op_V_CMP_GE_F16,"V_CMP_GE_F16"} ,//38 + {amdgpu_gfx940_op_V_CMP_O_F16,"V_CMP_O_F16"} ,//39 + {amdgpu_gfx940_op_V_CMP_U_F16,"V_CMP_U_F16"} ,//40 + {amdgpu_gfx940_op_V_CMP_NGE_F16,"V_CMP_NGE_F16"} ,//41 + {amdgpu_gfx940_op_V_CMP_NLG_F16,"V_CMP_NLG_F16"} ,//42 + {amdgpu_gfx940_op_V_CMP_NGT_F16,"V_CMP_NGT_F16"} ,//43 + {amdgpu_gfx940_op_V_CMP_NLE_F16,"V_CMP_NLE_F16"} ,//44 + {amdgpu_gfx940_op_V_CMP_NEQ_F16,"V_CMP_NEQ_F16"} ,//45 + {amdgpu_gfx940_op_V_CMP_NLT_F16,"V_CMP_NLT_F16"} ,//46 + {amdgpu_gfx940_op_V_CMP_TRU_F16,"V_CMP_TRU_F16"} ,//47 + {amdgpu_gfx940_op_V_CMPX_F_F16,"V_CMPX_F_F16"} ,//48 + {amdgpu_gfx940_op_V_CMPX_LT_F16,"V_CMPX_LT_F16"} ,//49 + {amdgpu_gfx940_op_V_CMPX_EQ_F16,"V_CMPX_EQ_F16"} ,//50 + {amdgpu_gfx940_op_V_CMPX_LE_F16,"V_CMPX_LE_F16"} ,//51 + {amdgpu_gfx940_op_V_CMPX_GT_F16,"V_CMPX_GT_F16"} ,//52 + {amdgpu_gfx940_op_V_CMPX_LG_F16,"V_CMPX_LG_F16"} ,//53 + {amdgpu_gfx940_op_V_CMPX_GE_F16,"V_CMPX_GE_F16"} ,//54 + {amdgpu_gfx940_op_V_CMPX_O_F16,"V_CMPX_O_F16"} ,//55 + {amdgpu_gfx940_op_V_CMPX_U_F16,"V_CMPX_U_F16"} ,//56 + {amdgpu_gfx940_op_V_CMPX_NGE_F16,"V_CMPX_NGE_F16"} ,//57 + {amdgpu_gfx940_op_V_CMPX_NLG_F16,"V_CMPX_NLG_F16"} ,//58 + {amdgpu_gfx940_op_V_CMPX_NGT_F16,"V_CMPX_NGT_F16"} ,//59 + {amdgpu_gfx940_op_V_CMPX_NLE_F16,"V_CMPX_NLE_F16"} ,//60 + {amdgpu_gfx940_op_V_CMPX_NEQ_F16,"V_CMPX_NEQ_F16"} ,//61 + {amdgpu_gfx940_op_V_CMPX_NLT_F16,"V_CMPX_NLT_F16"} ,//62 + {amdgpu_gfx940_op_V_CMPX_TRU_F16,"V_CMPX_TRU_F16"} ,//63 + {amdgpu_gfx940_op_V_CMP_F_F32,"V_CMP_F_F32"} ,//64 + {amdgpu_gfx940_op_V_CMP_LT_F32,"V_CMP_LT_F32"} ,//65 + {amdgpu_gfx940_op_V_CMP_EQ_F32,"V_CMP_EQ_F32"} ,//66 + {amdgpu_gfx940_op_V_CMP_LE_F32,"V_CMP_LE_F32"} ,//67 + {amdgpu_gfx940_op_V_CMP_GT_F32,"V_CMP_GT_F32"} ,//68 + {amdgpu_gfx940_op_V_CMP_LG_F32,"V_CMP_LG_F32"} ,//69 + {amdgpu_gfx940_op_V_CMP_GE_F32,"V_CMP_GE_F32"} ,//70 + {amdgpu_gfx940_op_V_CMP_O_F32,"V_CMP_O_F32"} ,//71 + {amdgpu_gfx940_op_V_CMP_U_F32,"V_CMP_U_F32"} ,//72 + {amdgpu_gfx940_op_V_CMP_NGE_F32,"V_CMP_NGE_F32"} ,//73 + {amdgpu_gfx940_op_V_CMP_NLG_F32,"V_CMP_NLG_F32"} ,//74 + {amdgpu_gfx940_op_V_CMP_NGT_F32,"V_CMP_NGT_F32"} ,//75 + {amdgpu_gfx940_op_V_CMP_NLE_F32,"V_CMP_NLE_F32"} ,//76 + {amdgpu_gfx940_op_V_CMP_NEQ_F32,"V_CMP_NEQ_F32"} ,//77 + {amdgpu_gfx940_op_V_CMP_NLT_F32,"V_CMP_NLT_F32"} ,//78 + {amdgpu_gfx940_op_V_CMP_TRU_F32,"V_CMP_TRU_F32"} ,//79 + {amdgpu_gfx940_op_V_CMPX_F_F32,"V_CMPX_F_F32"} ,//80 + {amdgpu_gfx940_op_V_CMPX_LT_F32,"V_CMPX_LT_F32"} ,//81 + {amdgpu_gfx940_op_V_CMPX_EQ_F32,"V_CMPX_EQ_F32"} ,//82 + {amdgpu_gfx940_op_V_CMPX_LE_F32,"V_CMPX_LE_F32"} ,//83 + {amdgpu_gfx940_op_V_CMPX_GT_F32,"V_CMPX_GT_F32"} ,//84 + {amdgpu_gfx940_op_V_CMPX_LG_F32,"V_CMPX_LG_F32"} ,//85 + {amdgpu_gfx940_op_V_CMPX_GE_F32,"V_CMPX_GE_F32"} ,//86 + {amdgpu_gfx940_op_V_CMPX_O_F32,"V_CMPX_O_F32"} ,//87 + {amdgpu_gfx940_op_V_CMPX_U_F32,"V_CMPX_U_F32"} ,//88 + {amdgpu_gfx940_op_V_CMPX_NGE_F32,"V_CMPX_NGE_F32"} ,//89 + {amdgpu_gfx940_op_V_CMPX_NLG_F32,"V_CMPX_NLG_F32"} ,//90 + {amdgpu_gfx940_op_V_CMPX_NGT_F32,"V_CMPX_NGT_F32"} ,//91 + {amdgpu_gfx940_op_V_CMPX_NLE_F32,"V_CMPX_NLE_F32"} ,//92 + {amdgpu_gfx940_op_V_CMPX_NEQ_F32,"V_CMPX_NEQ_F32"} ,//93 + {amdgpu_gfx940_op_V_CMPX_NLT_F32,"V_CMPX_NLT_F32"} ,//94 + {amdgpu_gfx940_op_V_CMPX_TRU_F32,"V_CMPX_TRU_F32"} ,//95 + {amdgpu_gfx940_op_V_CMP_F_F64,"V_CMP_F_F64"} ,//96 + {amdgpu_gfx940_op_V_CMP_LT_F64,"V_CMP_LT_F64"} ,//97 + {amdgpu_gfx940_op_V_CMP_EQ_F64,"V_CMP_EQ_F64"} ,//98 + {amdgpu_gfx940_op_V_CMP_LE_F64,"V_CMP_LE_F64"} ,//99 + {amdgpu_gfx940_op_V_CMP_GT_F64,"V_CMP_GT_F64"} ,//100 + {amdgpu_gfx940_op_V_CMP_LG_F64,"V_CMP_LG_F64"} ,//101 + {amdgpu_gfx940_op_V_CMP_GE_F64,"V_CMP_GE_F64"} ,//102 + {amdgpu_gfx940_op_V_CMP_O_F64,"V_CMP_O_F64"} ,//103 + {amdgpu_gfx940_op_V_CMP_U_F64,"V_CMP_U_F64"} ,//104 + {amdgpu_gfx940_op_V_CMP_NGE_F64,"V_CMP_NGE_F64"} ,//105 + {amdgpu_gfx940_op_V_CMP_NLG_F64,"V_CMP_NLG_F64"} ,//106 + {amdgpu_gfx940_op_V_CMP_NGT_F64,"V_CMP_NGT_F64"} ,//107 + {amdgpu_gfx940_op_V_CMP_NLE_F64,"V_CMP_NLE_F64"} ,//108 + {amdgpu_gfx940_op_V_CMP_NEQ_F64,"V_CMP_NEQ_F64"} ,//109 + {amdgpu_gfx940_op_V_CMP_NLT_F64,"V_CMP_NLT_F64"} ,//110 + {amdgpu_gfx940_op_V_CMP_TRU_F64,"V_CMP_TRU_F64"} ,//111 + {amdgpu_gfx940_op_V_CMPX_F_F64,"V_CMPX_F_F64"} ,//112 + {amdgpu_gfx940_op_V_CMPX_LT_F64,"V_CMPX_LT_F64"} ,//113 + {amdgpu_gfx940_op_V_CMPX_EQ_F64,"V_CMPX_EQ_F64"} ,//114 + {amdgpu_gfx940_op_V_CMPX_LE_F64,"V_CMPX_LE_F64"} ,//115 + {amdgpu_gfx940_op_V_CMPX_GT_F64,"V_CMPX_GT_F64"} ,//116 + {amdgpu_gfx940_op_V_CMPX_LG_F64,"V_CMPX_LG_F64"} ,//117 + {amdgpu_gfx940_op_V_CMPX_GE_F64,"V_CMPX_GE_F64"} ,//118 + {amdgpu_gfx940_op_V_CMPX_O_F64,"V_CMPX_O_F64"} ,//119 + {amdgpu_gfx940_op_V_CMPX_U_F64,"V_CMPX_U_F64"} ,//120 + {amdgpu_gfx940_op_V_CMPX_NGE_F64,"V_CMPX_NGE_F64"} ,//121 + {amdgpu_gfx940_op_V_CMPX_NLG_F64,"V_CMPX_NLG_F64"} ,//122 + {amdgpu_gfx940_op_V_CMPX_NGT_F64,"V_CMPX_NGT_F64"} ,//123 + {amdgpu_gfx940_op_V_CMPX_NLE_F64,"V_CMPX_NLE_F64"} ,//124 + {amdgpu_gfx940_op_V_CMPX_NEQ_F64,"V_CMPX_NEQ_F64"} ,//125 + {amdgpu_gfx940_op_V_CMPX_NLT_F64,"V_CMPX_NLT_F64"} ,//126 + {amdgpu_gfx940_op_V_CMPX_TRU_F64,"V_CMPX_TRU_F64"} ,//127 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//128 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//129 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//130 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//131 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//132 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//133 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//134 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//135 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//136 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//137 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//138 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//139 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//140 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//141 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//142 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//143 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//144 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//145 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//146 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//147 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//148 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//149 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//150 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//151 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//152 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//153 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//154 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//155 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//156 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//157 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//158 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//159 + {amdgpu_gfx940_op_V_CMP_F_I16,"V_CMP_F_I16"} ,//160 + {amdgpu_gfx940_op_V_CMP_LT_I16,"V_CMP_LT_I16"} ,//161 + {amdgpu_gfx940_op_V_CMP_EQ_I16,"V_CMP_EQ_I16"} ,//162 + {amdgpu_gfx940_op_V_CMP_LE_I16,"V_CMP_LE_I16"} ,//163 + {amdgpu_gfx940_op_V_CMP_GT_I16,"V_CMP_GT_I16"} ,//164 + {amdgpu_gfx940_op_V_CMP_NE_I16,"V_CMP_NE_I16"} ,//165 + {amdgpu_gfx940_op_V_CMP_GE_I16,"V_CMP_GE_I16"} ,//166 + {amdgpu_gfx940_op_V_CMP_T_I16,"V_CMP_T_I16"} ,//167 + {amdgpu_gfx940_op_V_CMP_F_U16,"V_CMP_F_U16"} ,//168 + {amdgpu_gfx940_op_V_CMP_LT_U16,"V_CMP_LT_U16"} ,//169 + {amdgpu_gfx940_op_V_CMP_EQ_U16,"V_CMP_EQ_U16"} ,//170 + {amdgpu_gfx940_op_V_CMP_LE_U16,"V_CMP_LE_U16"} ,//171 + {amdgpu_gfx940_op_V_CMP_GT_U16,"V_CMP_GT_U16"} ,//172 + {amdgpu_gfx940_op_V_CMP_NE_U16,"V_CMP_NE_U16"} ,//173 + {amdgpu_gfx940_op_V_CMP_GE_U16,"V_CMP_GE_U16"} ,//174 + {amdgpu_gfx940_op_V_CMP_T_U16,"V_CMP_T_U16"} ,//175 + {amdgpu_gfx940_op_V_CMPX_F_I16,"V_CMPX_F_I16"} ,//176 + {amdgpu_gfx940_op_V_CMPX_LT_I16,"V_CMPX_LT_I16"} ,//177 + {amdgpu_gfx940_op_V_CMPX_EQ_I16,"V_CMPX_EQ_I16"} ,//178 + {amdgpu_gfx940_op_V_CMPX_LE_I16,"V_CMPX_LE_I16"} ,//179 + {amdgpu_gfx940_op_V_CMPX_GT_I16,"V_CMPX_GT_I16"} ,//180 + {amdgpu_gfx940_op_V_CMPX_NE_I16,"V_CMPX_NE_I16"} ,//181 + {amdgpu_gfx940_op_V_CMPX_GE_I16,"V_CMPX_GE_I16"} ,//182 + {amdgpu_gfx940_op_V_CMPX_T_I16,"V_CMPX_T_I16"} ,//183 + {amdgpu_gfx940_op_V_CMPX_F_U16,"V_CMPX_F_U16"} ,//184 + {amdgpu_gfx940_op_V_CMPX_LT_U16,"V_CMPX_LT_U16"} ,//185 + {amdgpu_gfx940_op_V_CMPX_EQ_U16,"V_CMPX_EQ_U16"} ,//186 + {amdgpu_gfx940_op_V_CMPX_LE_U16,"V_CMPX_LE_U16"} ,//187 + {amdgpu_gfx940_op_V_CMPX_GT_U16,"V_CMPX_GT_U16"} ,//188 + {amdgpu_gfx940_op_V_CMPX_NE_U16,"V_CMPX_NE_U16"} ,//189 + {amdgpu_gfx940_op_V_CMPX_GE_U16,"V_CMPX_GE_U16"} ,//190 + {amdgpu_gfx940_op_V_CMPX_T_U16,"V_CMPX_T_U16"} ,//191 + {amdgpu_gfx940_op_V_CMP_F_I32,"V_CMP_F_I32"} ,//192 + {amdgpu_gfx940_op_V_CMP_LT_I32,"V_CMP_LT_I32"} ,//193 + {amdgpu_gfx940_op_V_CMP_EQ_I32,"V_CMP_EQ_I32"} ,//194 + {amdgpu_gfx940_op_V_CMP_LE_I32,"V_CMP_LE_I32"} ,//195 + {amdgpu_gfx940_op_V_CMP_GT_I32,"V_CMP_GT_I32"} ,//196 + {amdgpu_gfx940_op_V_CMP_NE_I32,"V_CMP_NE_I32"} ,//197 + {amdgpu_gfx940_op_V_CMP_GE_I32,"V_CMP_GE_I32"} ,//198 + {amdgpu_gfx940_op_V_CMP_T_I32,"V_CMP_T_I32"} ,//199 + {amdgpu_gfx940_op_V_CMP_F_U32,"V_CMP_F_U32"} ,//200 + {amdgpu_gfx940_op_V_CMP_LT_U32,"V_CMP_LT_U32"} ,//201 + {amdgpu_gfx940_op_V_CMP_EQ_U32,"V_CMP_EQ_U32"} ,//202 + {amdgpu_gfx940_op_V_CMP_LE_U32,"V_CMP_LE_U32"} ,//203 + {amdgpu_gfx940_op_V_CMP_GT_U32,"V_CMP_GT_U32"} ,//204 + {amdgpu_gfx940_op_V_CMP_NE_U32,"V_CMP_NE_U32"} ,//205 + {amdgpu_gfx940_op_V_CMP_GE_U32,"V_CMP_GE_U32"} ,//206 + {amdgpu_gfx940_op_V_CMP_T_U32,"V_CMP_T_U32"} ,//207 + {amdgpu_gfx940_op_V_CMPX_F_I32,"V_CMPX_F_I32"} ,//208 + {amdgpu_gfx940_op_V_CMPX_LT_I32,"V_CMPX_LT_I32"} ,//209 + {amdgpu_gfx940_op_V_CMPX_EQ_I32,"V_CMPX_EQ_I32"} ,//210 + {amdgpu_gfx940_op_V_CMPX_LE_I32,"V_CMPX_LE_I32"} ,//211 + {amdgpu_gfx940_op_V_CMPX_GT_I32,"V_CMPX_GT_I32"} ,//212 + {amdgpu_gfx940_op_V_CMPX_NE_I32,"V_CMPX_NE_I32"} ,//213 + {amdgpu_gfx940_op_V_CMPX_GE_I32,"V_CMPX_GE_I32"} ,//214 + {amdgpu_gfx940_op_V_CMPX_T_I32,"V_CMPX_T_I32"} ,//215 + {amdgpu_gfx940_op_V_CMPX_F_U32,"V_CMPX_F_U32"} ,//216 + {amdgpu_gfx940_op_V_CMPX_LT_U32,"V_CMPX_LT_U32"} ,//217 + {amdgpu_gfx940_op_V_CMPX_EQ_U32,"V_CMPX_EQ_U32"} ,//218 + {amdgpu_gfx940_op_V_CMPX_LE_U32,"V_CMPX_LE_U32"} ,//219 + {amdgpu_gfx940_op_V_CMPX_GT_U32,"V_CMPX_GT_U32"} ,//220 + {amdgpu_gfx940_op_V_CMPX_NE_U32,"V_CMPX_NE_U32"} ,//221 + {amdgpu_gfx940_op_V_CMPX_GE_U32,"V_CMPX_GE_U32"} ,//222 + {amdgpu_gfx940_op_V_CMPX_T_U32,"V_CMPX_T_U32"} ,//223 + {amdgpu_gfx940_op_V_CMP_F_I64,"V_CMP_F_I64"} ,//224 + {amdgpu_gfx940_op_V_CMP_LT_I64,"V_CMP_LT_I64"} ,//225 + {amdgpu_gfx940_op_V_CMP_EQ_I64,"V_CMP_EQ_I64"} ,//226 + {amdgpu_gfx940_op_V_CMP_LE_I64,"V_CMP_LE_I64"} ,//227 + {amdgpu_gfx940_op_V_CMP_GT_I64,"V_CMP_GT_I64"} ,//228 + {amdgpu_gfx940_op_V_CMP_NE_I64,"V_CMP_NE_I64"} ,//229 + {amdgpu_gfx940_op_V_CMP_GE_I64,"V_CMP_GE_I64"} ,//230 + {amdgpu_gfx940_op_V_CMP_T_I64,"V_CMP_T_I64"} ,//231 + {amdgpu_gfx940_op_V_CMP_F_U64,"V_CMP_F_U64"} ,//232 + {amdgpu_gfx940_op_V_CMP_LT_U64,"V_CMP_LT_U64"} ,//233 + {amdgpu_gfx940_op_V_CMP_EQ_U64,"V_CMP_EQ_U64"} ,//234 + {amdgpu_gfx940_op_V_CMP_LE_U64,"V_CMP_LE_U64"} ,//235 + {amdgpu_gfx940_op_V_CMP_GT_U64,"V_CMP_GT_U64"} ,//236 + {amdgpu_gfx940_op_V_CMP_NE_U64,"V_CMP_NE_U64"} ,//237 + {amdgpu_gfx940_op_V_CMP_GE_U64,"V_CMP_GE_U64"} ,//238 + {amdgpu_gfx940_op_V_CMP_T_U64,"V_CMP_T_U64"} ,//239 + {amdgpu_gfx940_op_V_CMPX_F_I64,"V_CMPX_F_I64"} ,//240 + {amdgpu_gfx940_op_V_CMPX_LT_I64,"V_CMPX_LT_I64"} ,//241 + {amdgpu_gfx940_op_V_CMPX_EQ_I64,"V_CMPX_EQ_I64"} ,//242 + {amdgpu_gfx940_op_V_CMPX_LE_I64,"V_CMPX_LE_I64"} ,//243 + {amdgpu_gfx940_op_V_CMPX_GT_I64,"V_CMPX_GT_I64"} ,//244 + {amdgpu_gfx940_op_V_CMPX_NE_I64,"V_CMPX_NE_I64"} ,//245 + {amdgpu_gfx940_op_V_CMPX_GE_I64,"V_CMPX_GE_I64"} ,//246 + {amdgpu_gfx940_op_V_CMPX_T_I64,"V_CMPX_T_I64"} ,//247 + {amdgpu_gfx940_op_V_CMPX_F_U64,"V_CMPX_F_U64"} ,//248 + {amdgpu_gfx940_op_V_CMPX_LT_U64,"V_CMPX_LT_U64"} ,//249 + {amdgpu_gfx940_op_V_CMPX_EQ_U64,"V_CMPX_EQ_U64"} ,//250 + {amdgpu_gfx940_op_V_CMPX_LE_U64,"V_CMPX_LE_U64"} ,//251 + {amdgpu_gfx940_op_V_CMPX_GT_U64,"V_CMPX_GT_U64"} ,//252 + {amdgpu_gfx940_op_V_CMPX_NE_U64,"V_CMPX_NE_U64"} ,//253 + {amdgpu_gfx940_op_V_CMPX_GE_U64,"V_CMPX_GE_U64"} ,//254 + {amdgpu_gfx940_op_V_CMPX_T_U64,"V_CMPX_T_U64"} ,//255 + {amdgpu_gfx940_op_V_CNDMASK_B32,"V_CNDMASK_B32"} ,//256 + {amdgpu_gfx940_op_V_ADD_F32,"V_ADD_F32"} ,//257 + {amdgpu_gfx940_op_V_SUB_F32,"V_SUB_F32"} ,//258 + {amdgpu_gfx940_op_V_SUBREV_F32,"V_SUBREV_F32"} ,//259 + {amdgpu_gfx940_op_V_FMAC_F64,"V_FMAC_F64"} ,//260 + {amdgpu_gfx940_op_V_MUL_F32,"V_MUL_F32"} ,//261 + {amdgpu_gfx940_op_V_MUL_I32_I24,"V_MUL_I32_I24"} ,//262 + {amdgpu_gfx940_op_V_MUL_HI_I32_I24,"V_MUL_HI_I32_I24"} ,//263 + {amdgpu_gfx940_op_V_MUL_U32_U24,"V_MUL_U32_U24"} ,//264 + {amdgpu_gfx940_op_V_MUL_HI_U32_U24,"V_MUL_HI_U32_U24"} ,//265 + {amdgpu_gfx940_op_V_MIN_F32,"V_MIN_F32"} ,//266 + {amdgpu_gfx940_op_V_MAX_F32,"V_MAX_F32"} ,//267 + {amdgpu_gfx940_op_V_MIN_I32,"V_MIN_I32"} ,//268 + {amdgpu_gfx940_op_V_MAX_I32,"V_MAX_I32"} ,//269 + {amdgpu_gfx940_op_V_MIN_U32,"V_MIN_U32"} ,//270 + {amdgpu_gfx940_op_V_MAX_U32,"V_MAX_U32"} ,//271 + {amdgpu_gfx940_op_V_LSHRREV_B32,"V_LSHRREV_B32"} ,//272 + {amdgpu_gfx940_op_V_ASHRREV_I32,"V_ASHRREV_I32"} ,//273 + {amdgpu_gfx940_op_V_LSHLREV_B32,"V_LSHLREV_B32"} ,//274 + {amdgpu_gfx940_op_V_AND_B32,"V_AND_B32"} ,//275 + {amdgpu_gfx940_op_V_OR_B32,"V_OR_B32"} ,//276 + {amdgpu_gfx940_op_V_XOR_B32,"V_XOR_B32"} ,//277 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//278 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//279 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//280 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//281 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//282 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//283 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//284 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//285 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//286 + {amdgpu_gfx940_op_V_ADD_F16,"V_ADD_F16"} ,//287 + {amdgpu_gfx940_op_V_SUB_F16,"V_SUB_F16"} ,//288 + {amdgpu_gfx940_op_V_SUBREV_F16,"V_SUBREV_F16"} ,//289 + {amdgpu_gfx940_op_V_MUL_F16,"V_MUL_F16"} ,//290 + {amdgpu_gfx940_op_V_MAC_F16,"V_MAC_F16"} ,//291 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//292 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//293 + {amdgpu_gfx940_op_V_ADD_U16,"V_ADD_U16"} ,//294 + {amdgpu_gfx940_op_V_SUB_U16,"V_SUB_U16"} ,//295 + {amdgpu_gfx940_op_V_SUBREV_U16,"V_SUBREV_U16"} ,//296 + {amdgpu_gfx940_op_V_MUL_LO_U16,"V_MUL_LO_U16"} ,//297 + {amdgpu_gfx940_op_V_LSHLREV_B16,"V_LSHLREV_B16"} ,//298 + {amdgpu_gfx940_op_V_LSHRREV_B16,"V_LSHRREV_B16"} ,//299 + {amdgpu_gfx940_op_V_ASHRREV_I16,"V_ASHRREV_I16"} ,//300 + {amdgpu_gfx940_op_V_MAX_F16,"V_MAX_F16"} ,//301 + {amdgpu_gfx940_op_V_MIN_F16,"V_MIN_F16"} ,//302 + {amdgpu_gfx940_op_V_MAX_U16,"V_MAX_U16"} ,//303 + {amdgpu_gfx940_op_V_MAX_I16,"V_MAX_I16"} ,//304 + {amdgpu_gfx940_op_V_MIN_U16,"V_MIN_U16"} ,//305 + {amdgpu_gfx940_op_V_MIN_I16,"V_MIN_I16"} ,//306 + {amdgpu_gfx940_op_V_LDEXP_F16,"V_LDEXP_F16"} ,//307 + {amdgpu_gfx940_op_V_ADD_U32,"V_ADD_U32"} ,//308 + {amdgpu_gfx940_op_V_SUB_U32,"V_SUB_U32"} ,//309 + {amdgpu_gfx940_op_V_SUBREV_U32,"V_SUBREV_U32"} ,//310 + {amdgpu_gfx940_op_V_DOT2C_F32_F16,"V_DOT2C_F32_F16"} ,//311 + {amdgpu_gfx940_op_V_DOT2C_I32_I16,"V_DOT2C_I32_I16"} ,//312 + {amdgpu_gfx940_op_V_DOT4C_I32_I8,"V_DOT4C_I32_I8"} ,//313 + {amdgpu_gfx940_op_V_DOT8C_I32_I4,"V_DOT8C_I32_I4"} ,//314 + {amdgpu_gfx940_op_V_FMAC_F32,"V_FMAC_F32"} ,//315 + {amdgpu_gfx940_op_V_PK_FMAC_F16,"V_PK_FMAC_F16"} ,//316 + {amdgpu_gfx940_op_V_XNOR_B32,"V_XNOR_B32"} ,//317 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//318 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//319 + {amdgpu_gfx940_op_V_NOP,"V_NOP"} ,//320 + {amdgpu_gfx940_op_V_MOV_B32,"V_MOV_B32"} ,//321 + {amdgpu_gfx940_op_V_READFIRSTLANE_B32,"V_READFIRSTLANE_B32"} ,//322 + {amdgpu_gfx940_op_V_CVT_I32_F64,"V_CVT_I32_F64"} ,//323 + {amdgpu_gfx940_op_V_CVT_F64_I32,"V_CVT_F64_I32"} ,//324 + {amdgpu_gfx940_op_V_CVT_F32_I32,"V_CVT_F32_I32"} ,//325 + {amdgpu_gfx940_op_V_CVT_F32_U32,"V_CVT_F32_U32"} ,//326 + {amdgpu_gfx940_op_V_CVT_U32_F32,"V_CVT_U32_F32"} ,//327 + {amdgpu_gfx940_op_V_CVT_I32_F32,"V_CVT_I32_F32"} ,//328 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//329 + {amdgpu_gfx940_op_V_CVT_F16_F32,"V_CVT_F16_F32"} ,//330 + {amdgpu_gfx940_op_V_CVT_F32_F16,"V_CVT_F32_F16"} ,//331 + {amdgpu_gfx940_op_V_CVT_RPI_I32_F32,"V_CVT_RPI_I32_F32"} ,//332 + {amdgpu_gfx940_op_V_CVT_FLR_I32_F32,"V_CVT_FLR_I32_F32"} ,//333 + {amdgpu_gfx940_op_V_CVT_OFF_F32_I4,"V_CVT_OFF_F32_I4"} ,//334 + {amdgpu_gfx940_op_V_CVT_F32_F64,"V_CVT_F32_F64"} ,//335 + {amdgpu_gfx940_op_V_CVT_F64_F32,"V_CVT_F64_F32"} ,//336 + {amdgpu_gfx940_op_V_CVT_F32_UBYTE0,"V_CVT_F32_UBYTE0"} ,//337 + {amdgpu_gfx940_op_V_CVT_F32_UBYTE1,"V_CVT_F32_UBYTE1"} ,//338 + {amdgpu_gfx940_op_V_CVT_F32_UBYTE2,"V_CVT_F32_UBYTE2"} ,//339 + {amdgpu_gfx940_op_V_CVT_F32_UBYTE3,"V_CVT_F32_UBYTE3"} ,//340 + {amdgpu_gfx940_op_V_CVT_U32_F64,"V_CVT_U32_F64"} ,//341 + {amdgpu_gfx940_op_V_CVT_F64_U32,"V_CVT_F64_U32"} ,//342 + {amdgpu_gfx940_op_V_TRUNC_F64,"V_TRUNC_F64"} ,//343 + {amdgpu_gfx940_op_V_CEIL_F64,"V_CEIL_F64"} ,//344 + {amdgpu_gfx940_op_V_RNDNE_F64,"V_RNDNE_F64"} ,//345 + {amdgpu_gfx940_op_V_FLOOR_F64,"V_FLOOR_F64"} ,//346 + {amdgpu_gfx940_op_V_FRACT_F32,"V_FRACT_F32"} ,//347 + {amdgpu_gfx940_op_V_TRUNC_F32,"V_TRUNC_F32"} ,//348 + {amdgpu_gfx940_op_V_CEIL_F32,"V_CEIL_F32"} ,//349 + {amdgpu_gfx940_op_V_RNDNE_F32,"V_RNDNE_F32"} ,//350 + {amdgpu_gfx940_op_V_FLOOR_F32,"V_FLOOR_F32"} ,//351 + {amdgpu_gfx940_op_V_EXP_F32,"V_EXP_F32"} ,//352 + {amdgpu_gfx940_op_V_LOG_F32,"V_LOG_F32"} ,//353 + {amdgpu_gfx940_op_V_RCP_F32,"V_RCP_F32"} ,//354 + {amdgpu_gfx940_op_V_RCP_IFLAG_F32,"V_RCP_IFLAG_F32"} ,//355 + {amdgpu_gfx940_op_V_RSQ_F32,"V_RSQ_F32"} ,//356 + {amdgpu_gfx940_op_V_RCP_F64,"V_RCP_F64"} ,//357 + {amdgpu_gfx940_op_V_RSQ_F64,"V_RSQ_F64"} ,//358 + {amdgpu_gfx940_op_V_SQRT_F32,"V_SQRT_F32"} ,//359 + {amdgpu_gfx940_op_V_SQRT_F64,"V_SQRT_F64"} ,//360 + {amdgpu_gfx940_op_V_SIN_F32,"V_SIN_F32"} ,//361 + {amdgpu_gfx940_op_V_COS_F32,"V_COS_F32"} ,//362 + {amdgpu_gfx940_op_V_NOT_B32,"V_NOT_B32"} ,//363 + {amdgpu_gfx940_op_V_BFREV_B32,"V_BFREV_B32"} ,//364 + {amdgpu_gfx940_op_V_FFBH_U32,"V_FFBH_U32"} ,//365 + {amdgpu_gfx940_op_V_FFBL_B32,"V_FFBL_B32"} ,//366 + {amdgpu_gfx940_op_V_FFBH_I32,"V_FFBH_I32"} ,//367 + {amdgpu_gfx940_op_V_FREXP_EXP_I32_F64,"V_FREXP_EXP_I32_F64"} ,//368 + {amdgpu_gfx940_op_V_FREXP_MANT_F64,"V_FREXP_MANT_F64"} ,//369 + {amdgpu_gfx940_op_V_FRACT_F64,"V_FRACT_F64"} ,//370 + {amdgpu_gfx940_op_V_FREXP_EXP_I32_F32,"V_FREXP_EXP_I32_F32"} ,//371 + {amdgpu_gfx940_op_V_FREXP_MANT_F32,"V_FREXP_MANT_F32"} ,//372 + {amdgpu_gfx940_op_V_CLREXCP,"V_CLREXCP"} ,//373 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//374 + {amdgpu_gfx940_op_V_SCREEN_PARTITION_4SE_B32,"V_SCREEN_PARTITION_4SE_B32"} ,//375 + {amdgpu_gfx940_op_V_MOV_B64,"V_MOV_B64"} ,//376 + {amdgpu_gfx940_op_V_CVT_F16_U16,"V_CVT_F16_U16"} ,//377 + {amdgpu_gfx940_op_V_CVT_F16_I16,"V_CVT_F16_I16"} ,//378 + {amdgpu_gfx940_op_V_CVT_U16_F16,"V_CVT_U16_F16"} ,//379 + {amdgpu_gfx940_op_V_CVT_I16_F16,"V_CVT_I16_F16"} ,//380 + {amdgpu_gfx940_op_V_RCP_F16,"V_RCP_F16"} ,//381 + {amdgpu_gfx940_op_V_SQRT_F16,"V_SQRT_F16"} ,//382 + {amdgpu_gfx940_op_V_RSQ_F16,"V_RSQ_F16"} ,//383 + {amdgpu_gfx940_op_V_LOG_F16,"V_LOG_F16"} ,//384 + {amdgpu_gfx940_op_V_EXP_F16,"V_EXP_F16"} ,//385 + {amdgpu_gfx940_op_V_FREXP_MANT_F16,"V_FREXP_MANT_F16"} ,//386 + {amdgpu_gfx940_op_V_FREXP_EXP_I16_F16,"V_FREXP_EXP_I16_F16"} ,//387 + {amdgpu_gfx940_op_V_FLOOR_F16,"V_FLOOR_F16"} ,//388 + {amdgpu_gfx940_op_V_CEIL_F16,"V_CEIL_F16"} ,//389 + {amdgpu_gfx940_op_V_TRUNC_F16,"V_TRUNC_F16"} ,//390 + {amdgpu_gfx940_op_V_RNDNE_F16,"V_RNDNE_F16"} ,//391 + {amdgpu_gfx940_op_V_FRACT_F16,"V_FRACT_F16"} ,//392 + {amdgpu_gfx940_op_V_SIN_F16,"V_SIN_F16"} ,//393 + {amdgpu_gfx940_op_V_COS_F16,"V_COS_F16"} ,//394 + {amdgpu_gfx940_op_V_EXP_LEGACY_F32,"V_EXP_LEGACY_F32"} ,//395 + {amdgpu_gfx940_op_V_LOG_LEGACY_F32,"V_LOG_LEGACY_F32"} ,//396 + {amdgpu_gfx940_op_V_CVT_NORM_I16_F16,"V_CVT_NORM_I16_F16"} ,//397 + {amdgpu_gfx940_op_V_CVT_NORM_U16_F16,"V_CVT_NORM_U16_F16"} ,//398 + {amdgpu_gfx940_op_V_SAT_PK_U8_I16,"V_SAT_PK_U8_I16"} ,//399 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//400 + {amdgpu_gfx940_op_V_SWAP_B32,"V_SWAP_B32"} ,//401 + {amdgpu_gfx940_op_V_ACCVGPR_MOV_B32,"V_ACCVGPR_MOV_B32"} ,//402 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//403 + {amdgpu_gfx940_op_V_CVT_F32_FP8,"V_CVT_F32_FP8"} ,//404 + {amdgpu_gfx940_op_V_CVT_F32_BF8,"V_CVT_F32_BF8"} ,//405 + {amdgpu_gfx940_op_V_CVT_PK_F32_FP8,"V_CVT_PK_F32_FP8"} ,//406 + {amdgpu_gfx940_op_V_CVT_PK_F32_BF8,"V_CVT_PK_F32_BF8"} ,//407 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//408 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//409 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//410 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//411 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//412 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//413 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//414 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//415 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//416 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//417 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//418 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//419 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//420 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//421 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//422 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//423 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//424 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//425 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//426 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//427 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//428 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//429 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//430 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//431 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//432 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//433 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//434 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//435 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//436 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//437 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//438 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//439 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//440 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//441 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//442 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//443 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//444 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//445 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//446 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//447 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//448 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//449 + {amdgpu_gfx940_op_V_MAD_I32_I24,"V_MAD_I32_I24"} ,//450 + {amdgpu_gfx940_op_V_MAD_U32_U24,"V_MAD_U32_U24"} ,//451 + {amdgpu_gfx940_op_V_CUBEID_F32,"V_CUBEID_F32"} ,//452 + {amdgpu_gfx940_op_V_CUBESC_F32,"V_CUBESC_F32"} ,//453 + {amdgpu_gfx940_op_V_CUBETC_F32,"V_CUBETC_F32"} ,//454 + {amdgpu_gfx940_op_V_CUBEMA_F32,"V_CUBEMA_F32"} ,//455 + {amdgpu_gfx940_op_V_BFE_U32,"V_BFE_U32"} ,//456 + {amdgpu_gfx940_op_V_BFE_I32,"V_BFE_I32"} ,//457 + {amdgpu_gfx940_op_V_BFI_B32,"V_BFI_B32"} ,//458 + {amdgpu_gfx940_op_V_FMA_F32,"V_FMA_F32"} ,//459 + {amdgpu_gfx940_op_V_FMA_F64,"V_FMA_F64"} ,//460 + {amdgpu_gfx940_op_V_LERP_U8,"V_LERP_U8"} ,//461 + {amdgpu_gfx940_op_V_ALIGNBIT_B32,"V_ALIGNBIT_B32"} ,//462 + {amdgpu_gfx940_op_V_ALIGNBYTE_B32,"V_ALIGNBYTE_B32"} ,//463 + {amdgpu_gfx940_op_V_MIN3_F32,"V_MIN3_F32"} ,//464 + {amdgpu_gfx940_op_V_MIN3_I32,"V_MIN3_I32"} ,//465 + {amdgpu_gfx940_op_V_MIN3_U32,"V_MIN3_U32"} ,//466 + {amdgpu_gfx940_op_V_MAX3_F32,"V_MAX3_F32"} ,//467 + {amdgpu_gfx940_op_V_MAX3_I32,"V_MAX3_I32"} ,//468 + {amdgpu_gfx940_op_V_MAX3_U32,"V_MAX3_U32"} ,//469 + {amdgpu_gfx940_op_V_MED3_F32,"V_MED3_F32"} ,//470 + {amdgpu_gfx940_op_V_MED3_I32,"V_MED3_I32"} ,//471 + {amdgpu_gfx940_op_V_MED3_U32,"V_MED3_U32"} ,//472 + {amdgpu_gfx940_op_V_SAD_U8,"V_SAD_U8"} ,//473 + {amdgpu_gfx940_op_V_SAD_HI_U8,"V_SAD_HI_U8"} ,//474 + {amdgpu_gfx940_op_V_SAD_U16,"V_SAD_U16"} ,//475 + {amdgpu_gfx940_op_V_SAD_U32,"V_SAD_U32"} ,//476 + {amdgpu_gfx940_op_V_CVT_PK_U8_F32,"V_CVT_PK_U8_F32"} ,//477 + {amdgpu_gfx940_op_V_DIV_FIXUP_F32,"V_DIV_FIXUP_F32"} ,//478 + {amdgpu_gfx940_op_V_DIV_FIXUP_F64,"V_DIV_FIXUP_F64"} ,//479 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//480 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//481 + {amdgpu_gfx940_op_V_DIV_FMAS_F32,"V_DIV_FMAS_F32"} ,//482 + {amdgpu_gfx940_op_V_DIV_FMAS_F64,"V_DIV_FMAS_F64"} ,//483 + {amdgpu_gfx940_op_V_MSAD_U8,"V_MSAD_U8"} ,//484 + {amdgpu_gfx940_op_V_QSAD_PK_U16_U8,"V_QSAD_PK_U16_U8"} ,//485 + {amdgpu_gfx940_op_V_MQSAD_PK_U16_U8,"V_MQSAD_PK_U16_U8"} ,//486 + {amdgpu_gfx940_op_V_MQSAD_U32_U8,"V_MQSAD_U32_U8"} ,//487 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//488 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//489 + {amdgpu_gfx940_op_V_MAD_LEGACY_F16,"V_MAD_LEGACY_F16"} ,//490 + {amdgpu_gfx940_op_V_MAD_LEGACY_U16,"V_MAD_LEGACY_U16"} ,//491 + {amdgpu_gfx940_op_V_MAD_LEGACY_I16,"V_MAD_LEGACY_I16"} ,//492 + {amdgpu_gfx940_op_V_PERM_B32,"V_PERM_B32"} ,//493 + {amdgpu_gfx940_op_V_FMA_LEGACY_F16,"V_FMA_LEGACY_F16"} ,//494 + {amdgpu_gfx940_op_V_DIV_FIXUP_LEGACY_F16,"V_DIV_FIXUP_LEGACY_F16"} ,//495 + {amdgpu_gfx940_op_V_CVT_PKACCUM_U8_F32,"V_CVT_PKACCUM_U8_F32"} ,//496 + {amdgpu_gfx940_op_V_MAD_U32_U16,"V_MAD_U32_U16"} ,//497 + {amdgpu_gfx940_op_V_MAD_I32_I16,"V_MAD_I32_I16"} ,//498 + {amdgpu_gfx940_op_V_XAD_U32,"V_XAD_U32"} ,//499 + {amdgpu_gfx940_op_V_MIN3_F16,"V_MIN3_F16"} ,//500 + {amdgpu_gfx940_op_V_MIN3_I16,"V_MIN3_I16"} ,//501 + {amdgpu_gfx940_op_V_MIN3_U16,"V_MIN3_U16"} ,//502 + {amdgpu_gfx940_op_V_MAX3_F16,"V_MAX3_F16"} ,//503 + {amdgpu_gfx940_op_V_MAX3_I16,"V_MAX3_I16"} ,//504 + {amdgpu_gfx940_op_V_MAX3_U16,"V_MAX3_U16"} ,//505 + {amdgpu_gfx940_op_V_MED3_F16,"V_MED3_F16"} ,//506 + {amdgpu_gfx940_op_V_MED3_I16,"V_MED3_I16"} ,//507 + {amdgpu_gfx940_op_V_MED3_U16,"V_MED3_U16"} ,//508 + {amdgpu_gfx940_op_V_LSHL_ADD_U32,"V_LSHL_ADD_U32"} ,//509 + {amdgpu_gfx940_op_V_ADD_LSHL_U32,"V_ADD_LSHL_U32"} ,//510 + {amdgpu_gfx940_op_V_ADD3_U32,"V_ADD3_U32"} ,//511 + {amdgpu_gfx940_op_V_LSHL_OR_B32,"V_LSHL_OR_B32"} ,//512 + {amdgpu_gfx940_op_V_AND_OR_B32,"V_AND_OR_B32"} ,//513 + {amdgpu_gfx940_op_V_OR3_B32,"V_OR3_B32"} ,//514 + {amdgpu_gfx940_op_V_MAD_F16,"V_MAD_F16"} ,//515 + {amdgpu_gfx940_op_V_MAD_U16,"V_MAD_U16"} ,//516 + {amdgpu_gfx940_op_V_MAD_I16,"V_MAD_I16"} ,//517 + {amdgpu_gfx940_op_V_FMA_F16,"V_FMA_F16"} ,//518 + {amdgpu_gfx940_op_V_DIV_FIXUP_F16,"V_DIV_FIXUP_F16"} ,//519 + {amdgpu_gfx940_op_V_LSHL_ADD_U64,"V_LSHL_ADD_U64"} ,//520 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//521 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//522 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//523 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//524 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//525 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//526 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//527 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//528 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//529 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//530 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//531 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//532 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//533 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//534 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//535 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//536 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//537 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//538 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//539 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//540 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//541 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//542 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//543 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//544 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//545 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//546 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//547 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//548 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//549 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//550 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//551 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//552 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//553 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//554 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//555 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//556 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//557 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//558 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//559 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//560 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//561 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//562 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//563 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//564 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//565 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//566 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//567 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//568 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//569 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//570 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//571 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//572 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//573 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//574 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//575 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//576 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//577 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//578 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//579 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//580 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//581 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//582 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//583 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//584 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//585 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//586 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//587 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//588 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//589 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//590 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//591 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//592 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//593 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//594 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//595 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//596 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//597 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//598 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//599 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//600 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//601 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//602 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//603 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//604 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//605 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//606 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//607 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//608 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//609 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//610 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//611 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//612 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//613 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//614 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//615 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//616 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//617 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//618 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//619 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//620 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//621 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//622 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//623 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//624 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//625 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//626 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//627 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//628 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//629 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//630 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//631 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//632 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//633 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//634 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//635 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//636 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//637 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//638 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//639 + {amdgpu_gfx940_op_V_ADD_F64,"V_ADD_F64"} ,//640 + {amdgpu_gfx940_op_V_MUL_F64,"V_MUL_F64"} ,//641 + {amdgpu_gfx940_op_V_MIN_F64,"V_MIN_F64"} ,//642 + {amdgpu_gfx940_op_V_MAX_F64,"V_MAX_F64"} ,//643 + {amdgpu_gfx940_op_V_LDEXP_F64,"V_LDEXP_F64"} ,//644 + {amdgpu_gfx940_op_V_MUL_LO_U32,"V_MUL_LO_U32"} ,//645 + {amdgpu_gfx940_op_V_MUL_HI_U32,"V_MUL_HI_U32"} ,//646 + {amdgpu_gfx940_op_V_MUL_HI_I32,"V_MUL_HI_I32"} ,//647 + {amdgpu_gfx940_op_V_LDEXP_F32,"V_LDEXP_F32"} ,//648 + {amdgpu_gfx940_op_V_READLANE_B32,"V_READLANE_B32"} ,//649 + {amdgpu_gfx940_op_V_WRITELANE_B32,"V_WRITELANE_B32"} ,//650 + {amdgpu_gfx940_op_V_BCNT_U32_B32,"V_BCNT_U32_B32"} ,//651 + {amdgpu_gfx940_op_V_MBCNT_LO_U32_B32,"V_MBCNT_LO_U32_B32"} ,//652 + {amdgpu_gfx940_op_V_MBCNT_HI_U32_B32,"V_MBCNT_HI_U32_B32"} ,//653 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//654 + {amdgpu_gfx940_op_V_LSHLREV_B64,"V_LSHLREV_B64"} ,//655 + {amdgpu_gfx940_op_V_LSHRREV_B64,"V_LSHRREV_B64"} ,//656 + {amdgpu_gfx940_op_V_ASHRREV_I64,"V_ASHRREV_I64"} ,//657 + {amdgpu_gfx940_op_V_TRIG_PREOP_F64,"V_TRIG_PREOP_F64"} ,//658 + {amdgpu_gfx940_op_V_BFM_B32,"V_BFM_B32"} ,//659 + {amdgpu_gfx940_op_V_CVT_PKNORM_I16_F32,"V_CVT_PKNORM_I16_F32"} ,//660 + {amdgpu_gfx940_op_V_CVT_PKNORM_U16_F32,"V_CVT_PKNORM_U16_F32"} ,//661 + {amdgpu_gfx940_op_V_CVT_PKRTZ_F16_F32,"V_CVT_PKRTZ_F16_F32"} ,//662 + {amdgpu_gfx940_op_V_CVT_PK_U16_U32,"V_CVT_PK_U16_U32"} ,//663 + {amdgpu_gfx940_op_V_CVT_PK_I16_I32,"V_CVT_PK_I16_I32"} ,//664 + {amdgpu_gfx940_op_V_CVT_PKNORM_I16_F16,"V_CVT_PKNORM_I16_F16"} ,//665 + {amdgpu_gfx940_op_V_CVT_PKNORM_U16_F16,"V_CVT_PKNORM_U16_F16"} ,//666 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//667 + {amdgpu_gfx940_op_V_ADD_I32,"V_ADD_I32"} ,//668 + {amdgpu_gfx940_op_V_SUB_I32,"V_SUB_I32"} ,//669 + {amdgpu_gfx940_op_V_ADD_I16,"V_ADD_I16"} ,//670 + {amdgpu_gfx940_op_V_SUB_I16,"V_SUB_I16"} ,//671 + {amdgpu_gfx940_op_V_PACK_B32_F16,"V_PACK_B32_F16"} ,//672 + {amdgpu_gfx940_op_V_MUL_LEGACY_F32,"V_MUL_LEGACY_F32"} ,//673 + {amdgpu_gfx940_op_V_CVT_PK_FP8_F32,"V_CVT_PK_FP8_F32"} ,//674 + {amdgpu_gfx940_op_V_CVT_PK_BF8_F32,"V_CVT_PK_BF8_F32"} ,//675 + {amdgpu_gfx940_op_V_CVT_SR_FP8_F32,"V_CVT_SR_FP8_F32"} ,//676 + {amdgpu_gfx940_op_V_CVT_SR_BF8_F32,"V_CVT_SR_BF8_F32"} ,//677 + }; // end ENC_VOP3_insn_table + const amdgpu_gfx940_insn_entry ENC_VOP2_insn_table [62] = + { + {amdgpu_gfx940_op_V_CNDMASK_B32,"V_CNDMASK_B32"} ,//0 + {amdgpu_gfx940_op_V_ADD_F32,"V_ADD_F32"} ,//1 + {amdgpu_gfx940_op_V_SUB_F32,"V_SUB_F32"} ,//2 + {amdgpu_gfx940_op_V_SUBREV_F32,"V_SUBREV_F32"} ,//3 + {amdgpu_gfx940_op_V_FMAC_F64,"V_FMAC_F64"} ,//4 + {amdgpu_gfx940_op_V_MUL_F32,"V_MUL_F32"} ,//5 + {amdgpu_gfx940_op_V_MUL_I32_I24,"V_MUL_I32_I24"} ,//6 + {amdgpu_gfx940_op_V_MUL_HI_I32_I24,"V_MUL_HI_I32_I24"} ,//7 + {amdgpu_gfx940_op_V_MUL_U32_U24,"V_MUL_U32_U24"} ,//8 + {amdgpu_gfx940_op_V_MUL_HI_U32_U24,"V_MUL_HI_U32_U24"} ,//9 + {amdgpu_gfx940_op_V_MIN_F32,"V_MIN_F32"} ,//10 + {amdgpu_gfx940_op_V_MAX_F32,"V_MAX_F32"} ,//11 + {amdgpu_gfx940_op_V_MIN_I32,"V_MIN_I32"} ,//12 + {amdgpu_gfx940_op_V_MAX_I32,"V_MAX_I32"} ,//13 + {amdgpu_gfx940_op_V_MIN_U32,"V_MIN_U32"} ,//14 + {amdgpu_gfx940_op_V_MAX_U32,"V_MAX_U32"} ,//15 + {amdgpu_gfx940_op_V_LSHRREV_B32,"V_LSHRREV_B32"} ,//16 + {amdgpu_gfx940_op_V_ASHRREV_I32,"V_ASHRREV_I32"} ,//17 + {amdgpu_gfx940_op_V_LSHLREV_B32,"V_LSHLREV_B32"} ,//18 + {amdgpu_gfx940_op_V_AND_B32,"V_AND_B32"} ,//19 + {amdgpu_gfx940_op_V_OR_B32,"V_OR_B32"} ,//20 + {amdgpu_gfx940_op_V_XOR_B32,"V_XOR_B32"} ,//21 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//22 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//23 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//24 + {amdgpu_gfx940_op_V_ADD_CO_U32,"V_ADD_CO_U32"} ,//25 + {amdgpu_gfx940_op_V_SUB_CO_U32,"V_SUB_CO_U32"} ,//26 + {amdgpu_gfx940_op_V_SUBREV_CO_U32,"V_SUBREV_CO_U32"} ,//27 + {amdgpu_gfx940_op_V_ADDC_CO_U32,"V_ADDC_CO_U32"} ,//28 + {amdgpu_gfx940_op_V_SUBB_CO_U32,"V_SUBB_CO_U32"} ,//29 + {amdgpu_gfx940_op_V_SUBBREV_CO_U32,"V_SUBBREV_CO_U32"} ,//30 + {amdgpu_gfx940_op_V_ADD_F16,"V_ADD_F16"} ,//31 + {amdgpu_gfx940_op_V_SUB_F16,"V_SUB_F16"} ,//32 + {amdgpu_gfx940_op_V_SUBREV_F16,"V_SUBREV_F16"} ,//33 + {amdgpu_gfx940_op_V_MUL_F16,"V_MUL_F16"} ,//34 + {amdgpu_gfx940_op_V_MAC_F16,"V_MAC_F16"} ,//35 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//36 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//37 + {amdgpu_gfx940_op_V_ADD_U16,"V_ADD_U16"} ,//38 + {amdgpu_gfx940_op_V_SUB_U16,"V_SUB_U16"} ,//39 + {amdgpu_gfx940_op_V_SUBREV_U16,"V_SUBREV_U16"} ,//40 + {amdgpu_gfx940_op_V_MUL_LO_U16,"V_MUL_LO_U16"} ,//41 + {amdgpu_gfx940_op_V_LSHLREV_B16,"V_LSHLREV_B16"} ,//42 + {amdgpu_gfx940_op_V_LSHRREV_B16,"V_LSHRREV_B16"} ,//43 + {amdgpu_gfx940_op_V_ASHRREV_I16,"V_ASHRREV_I16"} ,//44 + {amdgpu_gfx940_op_V_MAX_F16,"V_MAX_F16"} ,//45 + {amdgpu_gfx940_op_V_MIN_F16,"V_MIN_F16"} ,//46 + {amdgpu_gfx940_op_V_MAX_U16,"V_MAX_U16"} ,//47 + {amdgpu_gfx940_op_V_MAX_I16,"V_MAX_I16"} ,//48 + {amdgpu_gfx940_op_V_MIN_U16,"V_MIN_U16"} ,//49 + {amdgpu_gfx940_op_V_MIN_I16,"V_MIN_I16"} ,//50 + {amdgpu_gfx940_op_V_LDEXP_F16,"V_LDEXP_F16"} ,//51 + {amdgpu_gfx940_op_V_ADD_U32,"V_ADD_U32"} ,//52 + {amdgpu_gfx940_op_V_SUB_U32,"V_SUB_U32"} ,//53 + {amdgpu_gfx940_op_V_SUBREV_U32,"V_SUBREV_U32"} ,//54 + {amdgpu_gfx940_op_V_DOT2C_F32_F16,"V_DOT2C_F32_F16"} ,//55 + {amdgpu_gfx940_op_V_DOT2C_I32_I16,"V_DOT2C_I32_I16"} ,//56 + {amdgpu_gfx940_op_V_DOT4C_I32_I8,"V_DOT4C_I32_I8"} ,//57 + {amdgpu_gfx940_op_V_DOT8C_I32_I4,"V_DOT8C_I32_I4"} ,//58 + {amdgpu_gfx940_op_V_FMAC_F32,"V_FMAC_F32"} ,//59 + {amdgpu_gfx940_op_V_PK_FMAC_F16,"V_PK_FMAC_F16"} ,//60 + {amdgpu_gfx940_op_V_XNOR_B32,"V_XNOR_B32"} ,//61 + }; // end ENC_VOP2_insn_table + const amdgpu_gfx940_insn_entry ENC_VOP2_LITERAL_insn_table [38] = + { + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//0 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//1 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//2 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//3 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//4 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//5 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//6 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//7 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//8 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//9 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//10 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//11 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//12 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//13 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//14 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//15 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//16 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//17 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//18 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//19 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//20 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//21 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//22 + {amdgpu_gfx940_op_V_FMAMK_F32,"V_FMAMK_F32"} ,//23 + {amdgpu_gfx940_op_V_FMAAK_F32,"V_FMAAK_F32"} ,//24 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//25 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//26 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//27 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//28 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//29 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//30 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//31 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//32 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//33 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//34 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//35 + {amdgpu_gfx940_op_V_MADMK_F16,"V_MADMK_F16"} ,//36 + {amdgpu_gfx940_op_V_MADAK_F16,"V_MADAK_F16"} ,//37 + }; // end ENC_VOP2_LITERAL_insn_table + const amdgpu_gfx940_insn_entry ENC_VOP3B_insn_table [490] = + { + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//0 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//1 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//2 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//3 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//4 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//5 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//6 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//7 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//8 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//9 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//10 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//11 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//12 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//13 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//14 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//15 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//16 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//17 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//18 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//19 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//20 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//21 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//22 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//23 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//24 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//25 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//26 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//27 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//28 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//29 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//30 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//31 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//32 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//33 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//34 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//35 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//36 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//37 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//38 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//39 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//40 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//41 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//42 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//43 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//44 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//45 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//46 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//47 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//48 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//49 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//50 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//51 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//52 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//53 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//54 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//55 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//56 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//57 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//58 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//59 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//60 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//61 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//62 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//63 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//64 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//65 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//66 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//67 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//68 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//69 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//70 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//71 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//72 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//73 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//74 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//75 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//76 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//77 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//78 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//79 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//80 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//81 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//82 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//83 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//84 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//85 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//86 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//87 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//88 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//89 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//90 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//91 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//92 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//93 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//94 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//95 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//96 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//97 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//98 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//99 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//100 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//101 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//102 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//103 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//104 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//105 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//106 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//107 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//108 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//109 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//110 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//111 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//112 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//113 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//114 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//115 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//116 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//117 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//118 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//119 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//120 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//121 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//122 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//123 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//124 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//125 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//126 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//127 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//128 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//129 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//130 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//131 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//132 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//133 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//134 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//135 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//136 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//137 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//138 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//139 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//140 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//141 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//142 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//143 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//144 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//145 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//146 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//147 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//148 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//149 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//150 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//151 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//152 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//153 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//154 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//155 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//156 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//157 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//158 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//159 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//160 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//161 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//162 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//163 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//164 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//165 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//166 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//167 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//168 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//169 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//170 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//171 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//172 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//173 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//174 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//175 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//176 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//177 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//178 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//179 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//180 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//181 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//182 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//183 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//184 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//185 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//186 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//187 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//188 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//189 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//190 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//191 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//192 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//193 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//194 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//195 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//196 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//197 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//198 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//199 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//200 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//201 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//202 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//203 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//204 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//205 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//206 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//207 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//208 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//209 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//210 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//211 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//212 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//213 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//214 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//215 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//216 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//217 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//218 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//219 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//220 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//221 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//222 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//223 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//224 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//225 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//226 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//227 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//228 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//229 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//230 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//231 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//232 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//233 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//234 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//235 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//236 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//237 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//238 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//239 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//240 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//241 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//242 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//243 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//244 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//245 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//246 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//247 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//248 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//249 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//250 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//251 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//252 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//253 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//254 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//255 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//256 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//257 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//258 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//259 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//260 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//261 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//262 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//263 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//264 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//265 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//266 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//267 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//268 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//269 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//270 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//271 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//272 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//273 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//274 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//275 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//276 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//277 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//278 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//279 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//280 + {amdgpu_gfx940_op_V_ADD_CO_U32,"V_ADD_CO_U32"} ,//281 + {amdgpu_gfx940_op_V_SUB_CO_U32,"V_SUB_CO_U32"} ,//282 + {amdgpu_gfx940_op_V_SUBREV_CO_U32,"V_SUBREV_CO_U32"} ,//283 + {amdgpu_gfx940_op_V_ADDC_CO_U32,"V_ADDC_CO_U32"} ,//284 + {amdgpu_gfx940_op_V_SUBB_CO_U32,"V_SUBB_CO_U32"} ,//285 + {amdgpu_gfx940_op_V_SUBBREV_CO_U32,"V_SUBBREV_CO_U32"} ,//286 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//287 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//288 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//289 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//290 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//291 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//292 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//293 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//294 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//295 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//296 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//297 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//298 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//299 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//300 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//301 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//302 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//303 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//304 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//305 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//306 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//307 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//308 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//309 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//310 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//311 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//312 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//313 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//314 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//315 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//316 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//317 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//318 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//319 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//320 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//321 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//322 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//323 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//324 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//325 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//326 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//327 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//328 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//329 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//330 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//331 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//332 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//333 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//334 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//335 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//336 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//337 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//338 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//339 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//340 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//341 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//342 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//343 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//344 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//345 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//346 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//347 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//348 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//349 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//350 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//351 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//352 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//353 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//354 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//355 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//356 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//357 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//358 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//359 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//360 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//361 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//362 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//363 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//364 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//365 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//366 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//367 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//368 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//369 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//370 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//371 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//372 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//373 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//374 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//375 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//376 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//377 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//378 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//379 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//380 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//381 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//382 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//383 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//384 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//385 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//386 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//387 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//388 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//389 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//390 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//391 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//392 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//393 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//394 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//395 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//396 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//397 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//398 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//399 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//400 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//401 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//402 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//403 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//404 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//405 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//406 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//407 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//408 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//409 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//410 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//411 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//412 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//413 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//414 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//415 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//416 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//417 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//418 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//419 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//420 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//421 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//422 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//423 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//424 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//425 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//426 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//427 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//428 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//429 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//430 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//431 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//432 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//433 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//434 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//435 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//436 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//437 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//438 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//439 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//440 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//441 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//442 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//443 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//444 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//445 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//446 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//447 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//448 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//449 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//450 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//451 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//452 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//453 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//454 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//455 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//456 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//457 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//458 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//459 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//460 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//461 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//462 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//463 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//464 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//465 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//466 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//467 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//468 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//469 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//470 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//471 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//472 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//473 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//474 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//475 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//476 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//477 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//478 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//479 + {amdgpu_gfx940_op_V_DIV_SCALE_F32,"V_DIV_SCALE_F32"} ,//480 + {amdgpu_gfx940_op_V_DIV_SCALE_F64,"V_DIV_SCALE_F64"} ,//481 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//482 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//483 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//484 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//485 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//486 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//487 + {amdgpu_gfx940_op_V_MAD_U64_U32,"V_MAD_U64_U32"} ,//488 + {amdgpu_gfx940_op_V_MAD_I64_I32,"V_MAD_I64_I32"} ,//489 + }; // end ENC_VOP3B_insn_table + const amdgpu_gfx940_insn_entry ENC_VOP3P_insn_table [90] = + { + {amdgpu_gfx940_op_V_PK_MAD_I16,"V_PK_MAD_I16"} ,//0 + {amdgpu_gfx940_op_V_PK_MUL_LO_U16,"V_PK_MUL_LO_U16"} ,//1 + {amdgpu_gfx940_op_V_PK_ADD_I16,"V_PK_ADD_I16"} ,//2 + {amdgpu_gfx940_op_V_PK_SUB_I16,"V_PK_SUB_I16"} ,//3 + {amdgpu_gfx940_op_V_PK_LSHLREV_B16,"V_PK_LSHLREV_B16"} ,//4 + {amdgpu_gfx940_op_V_PK_LSHRREV_B16,"V_PK_LSHRREV_B16"} ,//5 + {amdgpu_gfx940_op_V_PK_ASHRREV_I16,"V_PK_ASHRREV_I16"} ,//6 + {amdgpu_gfx940_op_V_PK_MAX_I16,"V_PK_MAX_I16"} ,//7 + {amdgpu_gfx940_op_V_PK_MIN_I16,"V_PK_MIN_I16"} ,//8 + {amdgpu_gfx940_op_V_PK_MAD_U16,"V_PK_MAD_U16"} ,//9 + {amdgpu_gfx940_op_V_PK_ADD_U16,"V_PK_ADD_U16"} ,//10 + {amdgpu_gfx940_op_V_PK_SUB_U16,"V_PK_SUB_U16"} ,//11 + {amdgpu_gfx940_op_V_PK_MAX_U16,"V_PK_MAX_U16"} ,//12 + {amdgpu_gfx940_op_V_PK_MIN_U16,"V_PK_MIN_U16"} ,//13 + {amdgpu_gfx940_op_V_PK_FMA_F16,"V_PK_FMA_F16"} ,//14 + {amdgpu_gfx940_op_V_PK_ADD_F16,"V_PK_ADD_F16"} ,//15 + {amdgpu_gfx940_op_V_PK_MUL_F16,"V_PK_MUL_F16"} ,//16 + {amdgpu_gfx940_op_V_PK_MIN_F16,"V_PK_MIN_F16"} ,//17 + {amdgpu_gfx940_op_V_PK_MAX_F16,"V_PK_MAX_F16"} ,//18 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//19 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//20 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//21 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//22 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//23 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//24 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//25 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//26 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//27 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//28 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//29 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//30 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//31 + {amdgpu_gfx940_op_V_MAD_MIX_F32,"V_MAD_MIX_F32"} ,//32 + {amdgpu_gfx940_op_V_MAD_MIXLO_F16,"V_MAD_MIXLO_F16"} ,//33 + {amdgpu_gfx940_op_V_MAD_MIXHI_F16,"V_MAD_MIXHI_F16"} ,//34 + {amdgpu_gfx940_op_V_DOT2_F32_F16,"V_DOT2_F32_F16"} ,//35 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//36 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//37 + {amdgpu_gfx940_op_V_DOT2_I32_I16,"V_DOT2_I32_I16"} ,//38 + {amdgpu_gfx940_op_V_DOT2_U32_U16,"V_DOT2_U32_U16"} ,//39 + {amdgpu_gfx940_op_V_DOT4_I32_I8,"V_DOT4_I32_I8"} ,//40 + {amdgpu_gfx940_op_V_DOT4_U32_U8,"V_DOT4_U32_U8"} ,//41 + {amdgpu_gfx940_op_V_DOT8_I32_I4,"V_DOT8_I32_I4"} ,//42 + {amdgpu_gfx940_op_V_DOT8_U32_U4,"V_DOT8_U32_U4"} ,//43 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//44 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//45 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//46 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//47 + {amdgpu_gfx940_op_V_PK_FMA_F32,"V_PK_FMA_F32"} ,//48 + {amdgpu_gfx940_op_V_PK_MUL_F32,"V_PK_MUL_F32"} ,//49 + {amdgpu_gfx940_op_V_PK_ADD_F32,"V_PK_ADD_F32"} ,//50 + {amdgpu_gfx940_op_V_PK_MOV_B32,"V_PK_MOV_B32"} ,//51 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//52 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//53 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//54 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//55 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//56 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//57 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//58 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//59 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//60 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//61 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//62 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//63 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//64 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//65 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//66 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//67 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//68 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//69 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//70 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//71 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//72 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//73 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//74 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//75 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//76 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//77 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//78 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//79 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//80 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//81 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//82 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//83 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//84 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//85 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//86 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//87 + {amdgpu_gfx940_op_V_ACCVGPR_READ,"V_ACCVGPR_READ"} ,//88 + {amdgpu_gfx940_op_V_ACCVGPR_WRITE,"V_ACCVGPR_WRITE"} ,//89 + }; // end ENC_VOP3P_insn_table + const amdgpu_gfx940_insn_entry ENC_VOP3P_MFMA_insn_table [128] = + { + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//0 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//1 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//2 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//3 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//4 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//5 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//6 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//7 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//8 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//9 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//10 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//11 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//12 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//13 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//14 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//15 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//16 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//17 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//18 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//19 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//20 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//21 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//22 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//23 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//24 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//25 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//26 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//27 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//28 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//29 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//30 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//31 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//32 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//33 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//34 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//35 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//36 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//37 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//38 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//39 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//40 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//41 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//42 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//43 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//44 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//45 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//46 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//47 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//48 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//49 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//50 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//51 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//52 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//53 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//54 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//55 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//56 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//57 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//58 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//59 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//60 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//61 + {amdgpu_gfx940_op_V_MFMA_F32_16X16X8_XF32,"V_MFMA_F32_16X16X8_XF32"} ,//62 + {amdgpu_gfx940_op_V_MFMA_F32_32X32X4_XF32,"V_MFMA_F32_32X32X4_XF32"} ,//63 + {amdgpu_gfx940_op_V_MFMA_F32_32X32X1_2B_F32,"V_MFMA_F32_32X32X1_2B_F32"} ,//64 + {amdgpu_gfx940_op_V_MFMA_F32_16X16X1_4B_F32,"V_MFMA_F32_16X16X1_4B_F32"} ,//65 + {amdgpu_gfx940_op_V_MFMA_F32_4X4X1_16B_F32,"V_MFMA_F32_4X4X1_16B_F32"} ,//66 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//67 + {amdgpu_gfx940_op_V_MFMA_F32_32X32X2_F32,"V_MFMA_F32_32X32X2_F32"} ,//68 + {amdgpu_gfx940_op_V_MFMA_F32_16X16X4_F32,"V_MFMA_F32_16X16X4_F32"} ,//69 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//70 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//71 + {amdgpu_gfx940_op_V_MFMA_F32_32X32X4_2B_F16,"V_MFMA_F32_32X32X4_2B_F16"} ,//72 + {amdgpu_gfx940_op_V_MFMA_F32_16X16X4_4B_F16,"V_MFMA_F32_16X16X4_4B_F16"} ,//73 + {amdgpu_gfx940_op_V_MFMA_F32_4X4X4_16B_F16,"V_MFMA_F32_4X4X4_16B_F16"} ,//74 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//75 + {amdgpu_gfx940_op_V_MFMA_F32_32X32X8_F16,"V_MFMA_F32_32X32X8_F16"} ,//76 + {amdgpu_gfx940_op_V_MFMA_F32_16X16X16_F16,"V_MFMA_F32_16X16X16_F16"} ,//77 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//78 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//79 + {amdgpu_gfx940_op_V_MFMA_I32_32X32X4_2B_I8,"V_MFMA_I32_32X32X4_2B_I8"} ,//80 + {amdgpu_gfx940_op_V_MFMA_I32_16X16X4_4B_I8,"V_MFMA_I32_16X16X4_4B_I8"} ,//81 + {amdgpu_gfx940_op_V_MFMA_I32_4X4X4_16B_I8,"V_MFMA_I32_4X4X4_16B_I8"} ,//82 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//83 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//84 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//85 + {amdgpu_gfx940_op_V_MFMA_I32_32X32X16_I8,"V_MFMA_I32_32X32X16_I8"} ,//86 + {amdgpu_gfx940_op_V_MFMA_I32_16X16X32_I8,"V_MFMA_I32_16X16X32_I8"} ,//87 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//88 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//89 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//90 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//91 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//92 + {amdgpu_gfx940_op_V_MFMA_F32_32X32X4_2B_BF16,"V_MFMA_F32_32X32X4_2B_BF16"} ,//93 + {amdgpu_gfx940_op_V_MFMA_F32_16X16X4_4B_BF16,"V_MFMA_F32_16X16X4_4B_BF16"} ,//94 + {amdgpu_gfx940_op_V_MFMA_F32_4X4X4_16B_BF16,"V_MFMA_F32_4X4X4_16B_BF16"} ,//95 + {amdgpu_gfx940_op_V_MFMA_F32_32X32X8_BF16,"V_MFMA_F32_32X32X8_BF16"} ,//96 + {amdgpu_gfx940_op_V_MFMA_F32_16X16X16_BF16,"V_MFMA_F32_16X16X16_BF16"} ,//97 + {amdgpu_gfx940_op_V_SMFMAC_F32_16X16X32_F16,"V_SMFMAC_F32_16X16X32_F16"} ,//98 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//99 + {amdgpu_gfx940_op_V_SMFMAC_F32_32X32X16_F16,"V_SMFMAC_F32_32X32X16_F16"} ,//100 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//101 + {amdgpu_gfx940_op_V_SMFMAC_F32_16X16X32_BF16,"V_SMFMAC_F32_16X16X32_BF16"} ,//102 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//103 + {amdgpu_gfx940_op_V_SMFMAC_F32_32X32X16_BF16,"V_SMFMAC_F32_32X32X16_BF16"} ,//104 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//105 + {amdgpu_gfx940_op_V_SMFMAC_I32_16X16X64_I8,"V_SMFMAC_I32_16X16X64_I8"} ,//106 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//107 + {amdgpu_gfx940_op_V_SMFMAC_I32_32X32X32_I8,"V_SMFMAC_I32_32X32X32_I8"} ,//108 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//109 + {amdgpu_gfx940_op_V_MFMA_F64_16X16X4_F64,"V_MFMA_F64_16X16X4_F64"} ,//110 + {amdgpu_gfx940_op_V_MFMA_F64_4X4X4_4B_F64,"V_MFMA_F64_4X4X4_4B_F64"} ,//111 + {amdgpu_gfx940_op_V_MFMA_F32_16X16X32_BF8_BF8,"V_MFMA_F32_16X16X32_BF8_BF8"} ,//112 + {amdgpu_gfx940_op_V_MFMA_F32_16X16X32_BF8_FP8,"V_MFMA_F32_16X16X32_BF8_FP8"} ,//113 + {amdgpu_gfx940_op_V_MFMA_F32_16X16X32_FP8_BF8,"V_MFMA_F32_16X16X32_FP8_BF8"} ,//114 + {amdgpu_gfx940_op_V_MFMA_F32_16X16X32_FP8_FP8,"V_MFMA_F32_16X16X32_FP8_FP8"} ,//115 + {amdgpu_gfx940_op_V_MFMA_F32_32X32X16_BF8_BF8,"V_MFMA_F32_32X32X16_BF8_BF8"} ,//116 + {amdgpu_gfx940_op_V_MFMA_F32_32X32X16_BF8_FP8,"V_MFMA_F32_32X32X16_BF8_FP8"} ,//117 + {amdgpu_gfx940_op_V_MFMA_F32_32X32X16_FP8_BF8,"V_MFMA_F32_32X32X16_FP8_BF8"} ,//118 + {amdgpu_gfx940_op_V_MFMA_F32_32X32X16_FP8_FP8,"V_MFMA_F32_32X32X16_FP8_FP8"} ,//119 + {amdgpu_gfx940_op_V_SMFMAC_F32_16X16X64_BF8_BF8,"V_SMFMAC_F32_16X16X64_BF8_BF8"} ,//120 + {amdgpu_gfx940_op_V_SMFMAC_F32_16X16X64_BF8_FP8,"V_SMFMAC_F32_16X16X64_BF8_FP8"} ,//121 + {amdgpu_gfx940_op_V_SMFMAC_F32_16X16X64_FP8_BF8,"V_SMFMAC_F32_16X16X64_FP8_BF8"} ,//122 + {amdgpu_gfx940_op_V_SMFMAC_F32_16X16X64_FP8_FP8,"V_SMFMAC_F32_16X16X64_FP8_FP8"} ,//123 + {amdgpu_gfx940_op_V_SMFMAC_F32_32X32X32_BF8_BF8,"V_SMFMAC_F32_32X32X32_BF8_BF8"} ,//124 + {amdgpu_gfx940_op_V_SMFMAC_F32_32X32X32_BF8_FP8,"V_SMFMAC_F32_32X32X32_BF8_FP8"} ,//125 + {amdgpu_gfx940_op_V_SMFMAC_F32_32X32X32_FP8_BF8,"V_SMFMAC_F32_32X32X32_FP8_BF8"} ,//126 + {amdgpu_gfx940_op_V_SMFMAC_F32_32X32X32_FP8_FP8,"V_SMFMAC_F32_32X32X32_FP8_FP8"} ,//127 + }; // end ENC_VOP3P_MFMA_insn_table + const amdgpu_gfx940_insn_entry ENC_VOPC_insn_table [256] = + { + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//0 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//1 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//2 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//3 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//4 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//5 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//6 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//7 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//8 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//9 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//10 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//11 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//12 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//13 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//14 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//15 + {amdgpu_gfx940_op_V_CMP_CLASS_F32,"V_CMP_CLASS_F32"} ,//16 + {amdgpu_gfx940_op_V_CMPX_CLASS_F32,"V_CMPX_CLASS_F32"} ,//17 + {amdgpu_gfx940_op_V_CMP_CLASS_F64,"V_CMP_CLASS_F64"} ,//18 + {amdgpu_gfx940_op_V_CMPX_CLASS_F64,"V_CMPX_CLASS_F64"} ,//19 + {amdgpu_gfx940_op_V_CMP_CLASS_F16,"V_CMP_CLASS_F16"} ,//20 + {amdgpu_gfx940_op_V_CMPX_CLASS_F16,"V_CMPX_CLASS_F16"} ,//21 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//22 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//23 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//24 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//25 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//26 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//27 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//28 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//29 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//30 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//31 + {amdgpu_gfx940_op_V_CMP_F_F16,"V_CMP_F_F16"} ,//32 + {amdgpu_gfx940_op_V_CMP_LT_F16,"V_CMP_LT_F16"} ,//33 + {amdgpu_gfx940_op_V_CMP_EQ_F16,"V_CMP_EQ_F16"} ,//34 + {amdgpu_gfx940_op_V_CMP_LE_F16,"V_CMP_LE_F16"} ,//35 + {amdgpu_gfx940_op_V_CMP_GT_F16,"V_CMP_GT_F16"} ,//36 + {amdgpu_gfx940_op_V_CMP_LG_F16,"V_CMP_LG_F16"} ,//37 + {amdgpu_gfx940_op_V_CMP_GE_F16,"V_CMP_GE_F16"} ,//38 + {amdgpu_gfx940_op_V_CMP_O_F16,"V_CMP_O_F16"} ,//39 + {amdgpu_gfx940_op_V_CMP_U_F16,"V_CMP_U_F16"} ,//40 + {amdgpu_gfx940_op_V_CMP_NGE_F16,"V_CMP_NGE_F16"} ,//41 + {amdgpu_gfx940_op_V_CMP_NLG_F16,"V_CMP_NLG_F16"} ,//42 + {amdgpu_gfx940_op_V_CMP_NGT_F16,"V_CMP_NGT_F16"} ,//43 + {amdgpu_gfx940_op_V_CMP_NLE_F16,"V_CMP_NLE_F16"} ,//44 + {amdgpu_gfx940_op_V_CMP_NEQ_F16,"V_CMP_NEQ_F16"} ,//45 + {amdgpu_gfx940_op_V_CMP_NLT_F16,"V_CMP_NLT_F16"} ,//46 + {amdgpu_gfx940_op_V_CMP_TRU_F16,"V_CMP_TRU_F16"} ,//47 + {amdgpu_gfx940_op_V_CMPX_F_F16,"V_CMPX_F_F16"} ,//48 + {amdgpu_gfx940_op_V_CMPX_LT_F16,"V_CMPX_LT_F16"} ,//49 + {amdgpu_gfx940_op_V_CMPX_EQ_F16,"V_CMPX_EQ_F16"} ,//50 + {amdgpu_gfx940_op_V_CMPX_LE_F16,"V_CMPX_LE_F16"} ,//51 + {amdgpu_gfx940_op_V_CMPX_GT_F16,"V_CMPX_GT_F16"} ,//52 + {amdgpu_gfx940_op_V_CMPX_LG_F16,"V_CMPX_LG_F16"} ,//53 + {amdgpu_gfx940_op_V_CMPX_GE_F16,"V_CMPX_GE_F16"} ,//54 + {amdgpu_gfx940_op_V_CMPX_O_F16,"V_CMPX_O_F16"} ,//55 + {amdgpu_gfx940_op_V_CMPX_U_F16,"V_CMPX_U_F16"} ,//56 + {amdgpu_gfx940_op_V_CMPX_NGE_F16,"V_CMPX_NGE_F16"} ,//57 + {amdgpu_gfx940_op_V_CMPX_NLG_F16,"V_CMPX_NLG_F16"} ,//58 + {amdgpu_gfx940_op_V_CMPX_NGT_F16,"V_CMPX_NGT_F16"} ,//59 + {amdgpu_gfx940_op_V_CMPX_NLE_F16,"V_CMPX_NLE_F16"} ,//60 + {amdgpu_gfx940_op_V_CMPX_NEQ_F16,"V_CMPX_NEQ_F16"} ,//61 + {amdgpu_gfx940_op_V_CMPX_NLT_F16,"V_CMPX_NLT_F16"} ,//62 + {amdgpu_gfx940_op_V_CMPX_TRU_F16,"V_CMPX_TRU_F16"} ,//63 + {amdgpu_gfx940_op_V_CMP_F_F32,"V_CMP_F_F32"} ,//64 + {amdgpu_gfx940_op_V_CMP_LT_F32,"V_CMP_LT_F32"} ,//65 + {amdgpu_gfx940_op_V_CMP_EQ_F32,"V_CMP_EQ_F32"} ,//66 + {amdgpu_gfx940_op_V_CMP_LE_F32,"V_CMP_LE_F32"} ,//67 + {amdgpu_gfx940_op_V_CMP_GT_F32,"V_CMP_GT_F32"} ,//68 + {amdgpu_gfx940_op_V_CMP_LG_F32,"V_CMP_LG_F32"} ,//69 + {amdgpu_gfx940_op_V_CMP_GE_F32,"V_CMP_GE_F32"} ,//70 + {amdgpu_gfx940_op_V_CMP_O_F32,"V_CMP_O_F32"} ,//71 + {amdgpu_gfx940_op_V_CMP_U_F32,"V_CMP_U_F32"} ,//72 + {amdgpu_gfx940_op_V_CMP_NGE_F32,"V_CMP_NGE_F32"} ,//73 + {amdgpu_gfx940_op_V_CMP_NLG_F32,"V_CMP_NLG_F32"} ,//74 + {amdgpu_gfx940_op_V_CMP_NGT_F32,"V_CMP_NGT_F32"} ,//75 + {amdgpu_gfx940_op_V_CMP_NLE_F32,"V_CMP_NLE_F32"} ,//76 + {amdgpu_gfx940_op_V_CMP_NEQ_F32,"V_CMP_NEQ_F32"} ,//77 + {amdgpu_gfx940_op_V_CMP_NLT_F32,"V_CMP_NLT_F32"} ,//78 + {amdgpu_gfx940_op_V_CMP_TRU_F32,"V_CMP_TRU_F32"} ,//79 + {amdgpu_gfx940_op_V_CMPX_F_F32,"V_CMPX_F_F32"} ,//80 + {amdgpu_gfx940_op_V_CMPX_LT_F32,"V_CMPX_LT_F32"} ,//81 + {amdgpu_gfx940_op_V_CMPX_EQ_F32,"V_CMPX_EQ_F32"} ,//82 + {amdgpu_gfx940_op_V_CMPX_LE_F32,"V_CMPX_LE_F32"} ,//83 + {amdgpu_gfx940_op_V_CMPX_GT_F32,"V_CMPX_GT_F32"} ,//84 + {amdgpu_gfx940_op_V_CMPX_LG_F32,"V_CMPX_LG_F32"} ,//85 + {amdgpu_gfx940_op_V_CMPX_GE_F32,"V_CMPX_GE_F32"} ,//86 + {amdgpu_gfx940_op_V_CMPX_O_F32,"V_CMPX_O_F32"} ,//87 + {amdgpu_gfx940_op_V_CMPX_U_F32,"V_CMPX_U_F32"} ,//88 + {amdgpu_gfx940_op_V_CMPX_NGE_F32,"V_CMPX_NGE_F32"} ,//89 + {amdgpu_gfx940_op_V_CMPX_NLG_F32,"V_CMPX_NLG_F32"} ,//90 + {amdgpu_gfx940_op_V_CMPX_NGT_F32,"V_CMPX_NGT_F32"} ,//91 + {amdgpu_gfx940_op_V_CMPX_NLE_F32,"V_CMPX_NLE_F32"} ,//92 + {amdgpu_gfx940_op_V_CMPX_NEQ_F32,"V_CMPX_NEQ_F32"} ,//93 + {amdgpu_gfx940_op_V_CMPX_NLT_F32,"V_CMPX_NLT_F32"} ,//94 + {amdgpu_gfx940_op_V_CMPX_TRU_F32,"V_CMPX_TRU_F32"} ,//95 + {amdgpu_gfx940_op_V_CMP_F_F64,"V_CMP_F_F64"} ,//96 + {amdgpu_gfx940_op_V_CMP_LT_F64,"V_CMP_LT_F64"} ,//97 + {amdgpu_gfx940_op_V_CMP_EQ_F64,"V_CMP_EQ_F64"} ,//98 + {amdgpu_gfx940_op_V_CMP_LE_F64,"V_CMP_LE_F64"} ,//99 + {amdgpu_gfx940_op_V_CMP_GT_F64,"V_CMP_GT_F64"} ,//100 + {amdgpu_gfx940_op_V_CMP_LG_F64,"V_CMP_LG_F64"} ,//101 + {amdgpu_gfx940_op_V_CMP_GE_F64,"V_CMP_GE_F64"} ,//102 + {amdgpu_gfx940_op_V_CMP_O_F64,"V_CMP_O_F64"} ,//103 + {amdgpu_gfx940_op_V_CMP_U_F64,"V_CMP_U_F64"} ,//104 + {amdgpu_gfx940_op_V_CMP_NGE_F64,"V_CMP_NGE_F64"} ,//105 + {amdgpu_gfx940_op_V_CMP_NLG_F64,"V_CMP_NLG_F64"} ,//106 + {amdgpu_gfx940_op_V_CMP_NGT_F64,"V_CMP_NGT_F64"} ,//107 + {amdgpu_gfx940_op_V_CMP_NLE_F64,"V_CMP_NLE_F64"} ,//108 + {amdgpu_gfx940_op_V_CMP_NEQ_F64,"V_CMP_NEQ_F64"} ,//109 + {amdgpu_gfx940_op_V_CMP_NLT_F64,"V_CMP_NLT_F64"} ,//110 + {amdgpu_gfx940_op_V_CMP_TRU_F64,"V_CMP_TRU_F64"} ,//111 + {amdgpu_gfx940_op_V_CMPX_F_F64,"V_CMPX_F_F64"} ,//112 + {amdgpu_gfx940_op_V_CMPX_LT_F64,"V_CMPX_LT_F64"} ,//113 + {amdgpu_gfx940_op_V_CMPX_EQ_F64,"V_CMPX_EQ_F64"} ,//114 + {amdgpu_gfx940_op_V_CMPX_LE_F64,"V_CMPX_LE_F64"} ,//115 + {amdgpu_gfx940_op_V_CMPX_GT_F64,"V_CMPX_GT_F64"} ,//116 + {amdgpu_gfx940_op_V_CMPX_LG_F64,"V_CMPX_LG_F64"} ,//117 + {amdgpu_gfx940_op_V_CMPX_GE_F64,"V_CMPX_GE_F64"} ,//118 + {amdgpu_gfx940_op_V_CMPX_O_F64,"V_CMPX_O_F64"} ,//119 + {amdgpu_gfx940_op_V_CMPX_U_F64,"V_CMPX_U_F64"} ,//120 + {amdgpu_gfx940_op_V_CMPX_NGE_F64,"V_CMPX_NGE_F64"} ,//121 + {amdgpu_gfx940_op_V_CMPX_NLG_F64,"V_CMPX_NLG_F64"} ,//122 + {amdgpu_gfx940_op_V_CMPX_NGT_F64,"V_CMPX_NGT_F64"} ,//123 + {amdgpu_gfx940_op_V_CMPX_NLE_F64,"V_CMPX_NLE_F64"} ,//124 + {amdgpu_gfx940_op_V_CMPX_NEQ_F64,"V_CMPX_NEQ_F64"} ,//125 + {amdgpu_gfx940_op_V_CMPX_NLT_F64,"V_CMPX_NLT_F64"} ,//126 + {amdgpu_gfx940_op_V_CMPX_TRU_F64,"V_CMPX_TRU_F64"} ,//127 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//128 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//129 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//130 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//131 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//132 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//133 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//134 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//135 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//136 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//137 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//138 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//139 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//140 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//141 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//142 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//143 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//144 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//145 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//146 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//147 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//148 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//149 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//150 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//151 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//152 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//153 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//154 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//155 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//156 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//157 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//158 + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//159 + {amdgpu_gfx940_op_V_CMP_F_I16,"V_CMP_F_I16"} ,//160 + {amdgpu_gfx940_op_V_CMP_LT_I16,"V_CMP_LT_I16"} ,//161 + {amdgpu_gfx940_op_V_CMP_EQ_I16,"V_CMP_EQ_I16"} ,//162 + {amdgpu_gfx940_op_V_CMP_LE_I16,"V_CMP_LE_I16"} ,//163 + {amdgpu_gfx940_op_V_CMP_GT_I16,"V_CMP_GT_I16"} ,//164 + {amdgpu_gfx940_op_V_CMP_NE_I16,"V_CMP_NE_I16"} ,//165 + {amdgpu_gfx940_op_V_CMP_GE_I16,"V_CMP_GE_I16"} ,//166 + {amdgpu_gfx940_op_V_CMP_T_I16,"V_CMP_T_I16"} ,//167 + {amdgpu_gfx940_op_V_CMP_F_U16,"V_CMP_F_U16"} ,//168 + {amdgpu_gfx940_op_V_CMP_LT_U16,"V_CMP_LT_U16"} ,//169 + {amdgpu_gfx940_op_V_CMP_EQ_U16,"V_CMP_EQ_U16"} ,//170 + {amdgpu_gfx940_op_V_CMP_LE_U16,"V_CMP_LE_U16"} ,//171 + {amdgpu_gfx940_op_V_CMP_GT_U16,"V_CMP_GT_U16"} ,//172 + {amdgpu_gfx940_op_V_CMP_NE_U16,"V_CMP_NE_U16"} ,//173 + {amdgpu_gfx940_op_V_CMP_GE_U16,"V_CMP_GE_U16"} ,//174 + {amdgpu_gfx940_op_V_CMP_T_U16,"V_CMP_T_U16"} ,//175 + {amdgpu_gfx940_op_V_CMPX_F_I16,"V_CMPX_F_I16"} ,//176 + {amdgpu_gfx940_op_V_CMPX_LT_I16,"V_CMPX_LT_I16"} ,//177 + {amdgpu_gfx940_op_V_CMPX_EQ_I16,"V_CMPX_EQ_I16"} ,//178 + {amdgpu_gfx940_op_V_CMPX_LE_I16,"V_CMPX_LE_I16"} ,//179 + {amdgpu_gfx940_op_V_CMPX_GT_I16,"V_CMPX_GT_I16"} ,//180 + {amdgpu_gfx940_op_V_CMPX_NE_I16,"V_CMPX_NE_I16"} ,//181 + {amdgpu_gfx940_op_V_CMPX_GE_I16,"V_CMPX_GE_I16"} ,//182 + {amdgpu_gfx940_op_V_CMPX_T_I16,"V_CMPX_T_I16"} ,//183 + {amdgpu_gfx940_op_V_CMPX_F_U16,"V_CMPX_F_U16"} ,//184 + {amdgpu_gfx940_op_V_CMPX_LT_U16,"V_CMPX_LT_U16"} ,//185 + {amdgpu_gfx940_op_V_CMPX_EQ_U16,"V_CMPX_EQ_U16"} ,//186 + {amdgpu_gfx940_op_V_CMPX_LE_U16,"V_CMPX_LE_U16"} ,//187 + {amdgpu_gfx940_op_V_CMPX_GT_U16,"V_CMPX_GT_U16"} ,//188 + {amdgpu_gfx940_op_V_CMPX_NE_U16,"V_CMPX_NE_U16"} ,//189 + {amdgpu_gfx940_op_V_CMPX_GE_U16,"V_CMPX_GE_U16"} ,//190 + {amdgpu_gfx940_op_V_CMPX_T_U16,"V_CMPX_T_U16"} ,//191 + {amdgpu_gfx940_op_V_CMP_F_I32,"V_CMP_F_I32"} ,//192 + {amdgpu_gfx940_op_V_CMP_LT_I32,"V_CMP_LT_I32"} ,//193 + {amdgpu_gfx940_op_V_CMP_EQ_I32,"V_CMP_EQ_I32"} ,//194 + {amdgpu_gfx940_op_V_CMP_LE_I32,"V_CMP_LE_I32"} ,//195 + {amdgpu_gfx940_op_V_CMP_GT_I32,"V_CMP_GT_I32"} ,//196 + {amdgpu_gfx940_op_V_CMP_NE_I32,"V_CMP_NE_I32"} ,//197 + {amdgpu_gfx940_op_V_CMP_GE_I32,"V_CMP_GE_I32"} ,//198 + {amdgpu_gfx940_op_V_CMP_T_I32,"V_CMP_T_I32"} ,//199 + {amdgpu_gfx940_op_V_CMP_F_U32,"V_CMP_F_U32"} ,//200 + {amdgpu_gfx940_op_V_CMP_LT_U32,"V_CMP_LT_U32"} ,//201 + {amdgpu_gfx940_op_V_CMP_EQ_U32,"V_CMP_EQ_U32"} ,//202 + {amdgpu_gfx940_op_V_CMP_LE_U32,"V_CMP_LE_U32"} ,//203 + {amdgpu_gfx940_op_V_CMP_GT_U32,"V_CMP_GT_U32"} ,//204 + {amdgpu_gfx940_op_V_CMP_NE_U32,"V_CMP_NE_U32"} ,//205 + {amdgpu_gfx940_op_V_CMP_GE_U32,"V_CMP_GE_U32"} ,//206 + {amdgpu_gfx940_op_V_CMP_T_U32,"V_CMP_T_U32"} ,//207 + {amdgpu_gfx940_op_V_CMPX_F_I32,"V_CMPX_F_I32"} ,//208 + {amdgpu_gfx940_op_V_CMPX_LT_I32,"V_CMPX_LT_I32"} ,//209 + {amdgpu_gfx940_op_V_CMPX_EQ_I32,"V_CMPX_EQ_I32"} ,//210 + {amdgpu_gfx940_op_V_CMPX_LE_I32,"V_CMPX_LE_I32"} ,//211 + {amdgpu_gfx940_op_V_CMPX_GT_I32,"V_CMPX_GT_I32"} ,//212 + {amdgpu_gfx940_op_V_CMPX_NE_I32,"V_CMPX_NE_I32"} ,//213 + {amdgpu_gfx940_op_V_CMPX_GE_I32,"V_CMPX_GE_I32"} ,//214 + {amdgpu_gfx940_op_V_CMPX_T_I32,"V_CMPX_T_I32"} ,//215 + {amdgpu_gfx940_op_V_CMPX_F_U32,"V_CMPX_F_U32"} ,//216 + {amdgpu_gfx940_op_V_CMPX_LT_U32,"V_CMPX_LT_U32"} ,//217 + {amdgpu_gfx940_op_V_CMPX_EQ_U32,"V_CMPX_EQ_U32"} ,//218 + {amdgpu_gfx940_op_V_CMPX_LE_U32,"V_CMPX_LE_U32"} ,//219 + {amdgpu_gfx940_op_V_CMPX_GT_U32,"V_CMPX_GT_U32"} ,//220 + {amdgpu_gfx940_op_V_CMPX_NE_U32,"V_CMPX_NE_U32"} ,//221 + {amdgpu_gfx940_op_V_CMPX_GE_U32,"V_CMPX_GE_U32"} ,//222 + {amdgpu_gfx940_op_V_CMPX_T_U32,"V_CMPX_T_U32"} ,//223 + {amdgpu_gfx940_op_V_CMP_F_I64,"V_CMP_F_I64"} ,//224 + {amdgpu_gfx940_op_V_CMP_LT_I64,"V_CMP_LT_I64"} ,//225 + {amdgpu_gfx940_op_V_CMP_EQ_I64,"V_CMP_EQ_I64"} ,//226 + {amdgpu_gfx940_op_V_CMP_LE_I64,"V_CMP_LE_I64"} ,//227 + {amdgpu_gfx940_op_V_CMP_GT_I64,"V_CMP_GT_I64"} ,//228 + {amdgpu_gfx940_op_V_CMP_NE_I64,"V_CMP_NE_I64"} ,//229 + {amdgpu_gfx940_op_V_CMP_GE_I64,"V_CMP_GE_I64"} ,//230 + {amdgpu_gfx940_op_V_CMP_T_I64,"V_CMP_T_I64"} ,//231 + {amdgpu_gfx940_op_V_CMP_F_U64,"V_CMP_F_U64"} ,//232 + {amdgpu_gfx940_op_V_CMP_LT_U64,"V_CMP_LT_U64"} ,//233 + {amdgpu_gfx940_op_V_CMP_EQ_U64,"V_CMP_EQ_U64"} ,//234 + {amdgpu_gfx940_op_V_CMP_LE_U64,"V_CMP_LE_U64"} ,//235 + {amdgpu_gfx940_op_V_CMP_GT_U64,"V_CMP_GT_U64"} ,//236 + {amdgpu_gfx940_op_V_CMP_NE_U64,"V_CMP_NE_U64"} ,//237 + {amdgpu_gfx940_op_V_CMP_GE_U64,"V_CMP_GE_U64"} ,//238 + {amdgpu_gfx940_op_V_CMP_T_U64,"V_CMP_T_U64"} ,//239 + {amdgpu_gfx940_op_V_CMPX_F_I64,"V_CMPX_F_I64"} ,//240 + {amdgpu_gfx940_op_V_CMPX_LT_I64,"V_CMPX_LT_I64"} ,//241 + {amdgpu_gfx940_op_V_CMPX_EQ_I64,"V_CMPX_EQ_I64"} ,//242 + {amdgpu_gfx940_op_V_CMPX_LE_I64,"V_CMPX_LE_I64"} ,//243 + {amdgpu_gfx940_op_V_CMPX_GT_I64,"V_CMPX_GT_I64"} ,//244 + {amdgpu_gfx940_op_V_CMPX_NE_I64,"V_CMPX_NE_I64"} ,//245 + {amdgpu_gfx940_op_V_CMPX_GE_I64,"V_CMPX_GE_I64"} ,//246 + {amdgpu_gfx940_op_V_CMPX_T_I64,"V_CMPX_T_I64"} ,//247 + {amdgpu_gfx940_op_V_CMPX_F_U64,"V_CMPX_F_U64"} ,//248 + {amdgpu_gfx940_op_V_CMPX_LT_U64,"V_CMPX_LT_U64"} ,//249 + {amdgpu_gfx940_op_V_CMPX_EQ_U64,"V_CMPX_EQ_U64"} ,//250 + {amdgpu_gfx940_op_V_CMPX_LE_U64,"V_CMPX_LE_U64"} ,//251 + {amdgpu_gfx940_op_V_CMPX_GT_U64,"V_CMPX_GT_U64"} ,//252 + {amdgpu_gfx940_op_V_CMPX_NE_U64,"V_CMPX_NE_U64"} ,//253 + {amdgpu_gfx940_op_V_CMPX_GE_U64,"V_CMPX_GE_U64"} ,//254 + {amdgpu_gfx940_op_V_CMPX_T_U64,"V_CMPX_T_U64"} ,//255 + }; // end ENC_VOPC_insn_table + const amdgpu_gfx940_insn_entry ENC_VINTRP_insn_table [1] = + { + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//0 + }; // end ENC_VINTRP_insn_table + const amdgpu_gfx940_insn_entry ENC_MIMG_insn_table [1] = + { + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//0 + }; // end ENC_MIMG_insn_table + const amdgpu_gfx940_insn_entry SOPK_INST_LITERAL__insn_table [1] = + { + {amdgpu_gfx940_op_S_NOP,"S_NOP"} ,//0 + }; // end SOPK_INST_LITERAL__insn_table diff --git a/instructionAPI/src/AMDGPU/gfx940/appendOperands.C b/instructionAPI/src/AMDGPU/gfx940/appendOperands.C new file mode 100644 index 0000000000..6f3a6ca294 --- /dev/null +++ b/instructionAPI/src/AMDGPU/gfx940/appendOperands.C @@ -0,0 +1,357 @@ +#include +#include "InstructionDecoder-amdgpu-gfx940.h" + +namespace Dyninst { +namespace InstructionAPI { + void InstructionDecoder_amdgpu_gfx940::appendOPR_SIMM4(uint64_t input, bool isRead, bool isWritten, uint32_t /*_num_elements = 1*/ , bool isImplicit /*= false*/) + { + insn_in_progress->appendOperand(Immediate::makeImmediate(Result(s8, input)),isRead,isWritten,isImplicit); + } + + void InstructionDecoder_amdgpu_gfx940::appendOPR_SIMM8(uint64_t input, bool isRead, bool isWritten, uint32_t /*_num_elements = 1*/ , bool isImplicit /*= false*/) + { + insn_in_progress->appendOperand(Immediate::makeImmediate(Result(s8, input)),isRead,isWritten,isImplicit); + } + + void InstructionDecoder_amdgpu_gfx940::appendOPR_SIMM16(uint64_t input, bool isRead, bool isWritten, uint32_t /*_num_elements = 1*/ , bool isImplicit /*= false*/) + { + insn_in_progress->appendOperand(Immediate::makeImmediate(Result(s16, input)),isRead,isWritten,isImplicit); + } + + void InstructionDecoder_amdgpu_gfx940::appendOPR_SIMM32(uint64_t input, bool isRead, bool isWritten, uint32_t /*_num_elements = 1*/ , bool isImplicit /*= false*/) + { + insn_in_progress->appendOperand(Immediate::makeImmediate(Result(s32, input)),isRead,isWritten,isImplicit); + } + + void InstructionDecoder_amdgpu_gfx940::appendOPR_WAITCNT(uint64_t input, bool isRead, bool isWritten, uint32_t /*_num_elements = 1*/ , bool isImplicit /*= false*/) + { + insn_in_progress->appendOperand(Immediate::makeImmediate(Result(s16, input)),isRead,isWritten,isImplicit); + } + + void InstructionDecoder_amdgpu_gfx940::appendOPR_ACCVGPR(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_ACCVGPR(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_ACCVGPR(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + + void InstructionDecoder_amdgpu_gfx940::appendOPR_DSMEM(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_DSMEM(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_DSMEM(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + + void InstructionDecoder_amdgpu_gfx940::appendOPR_FLAT_SCRATCH(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_FLAT_SCRATCH(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_FLAT_SCRATCH(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + + void InstructionDecoder_amdgpu_gfx940::appendOPR_PC(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_PC(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_PC(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + + void InstructionDecoder_amdgpu_gfx940::appendOPR_SDST(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_SDST(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_SDST(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + + void InstructionDecoder_amdgpu_gfx940::appendOPR_SDST_EXEC(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_SDST_EXEC(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_SDST_EXEC(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + + void InstructionDecoder_amdgpu_gfx940::appendOPR_SDST_M0(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_SDST_M0(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_SDST_M0(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + + void InstructionDecoder_amdgpu_gfx940::appendOPR_SRC(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_SRC(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_SRC(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + + void InstructionDecoder_amdgpu_gfx940::appendOPR_SRC_ACCVGPR(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_SRC_ACCVGPR(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_SRC_ACCVGPR(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + + void InstructionDecoder_amdgpu_gfx940::appendOPR_SRC_NOLDS(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_SRC_NOLDS(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_SRC_NOLDS(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + + void InstructionDecoder_amdgpu_gfx940::appendOPR_SRC_NOLIT(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_SRC_NOLIT(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_SRC_NOLIT(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + + void InstructionDecoder_amdgpu_gfx940::appendOPR_SRC_SIMPLE(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_SRC_SIMPLE(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_SRC_SIMPLE(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + + void InstructionDecoder_amdgpu_gfx940::appendOPR_SRC_VGPR(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_SRC_VGPR(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_SRC_VGPR(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + + void InstructionDecoder_amdgpu_gfx940::appendOPR_SRC_VGPR_OR_ACCVGPR(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_SRC_VGPR_OR_ACCVGPR(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + + void InstructionDecoder_amdgpu_gfx940::appendOPR_SRC_VGPR_OR_ACCVGPR_OR_CONST(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_SRC_VGPR_OR_ACCVGPR_OR_CONST(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_SRC_VGPR_OR_ACCVGPR_OR_CONST(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + + void InstructionDecoder_amdgpu_gfx940::appendOPR_SREG(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_SREG(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_SREG(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + + void InstructionDecoder_amdgpu_gfx940::appendOPR_SREG_NOVCC(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_SREG_NOVCC(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_SREG_NOVCC(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + + void InstructionDecoder_amdgpu_gfx940::appendOPR_SSRC(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_SSRC(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_SSRC(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + + void InstructionDecoder_amdgpu_gfx940::appendOPR_SSRC_LANESEL(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_SSRC_LANESEL(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_SSRC_LANESEL(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + + void InstructionDecoder_amdgpu_gfx940::appendOPR_SSRC_NOLIT(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_SSRC_NOLIT(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_SSRC_NOLIT(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + + void InstructionDecoder_amdgpu_gfx940::appendOPR_SSRC_SPECIAL_SCC(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_SSRC_SPECIAL_SCC(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_SSRC_SPECIAL_SCC(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + + void InstructionDecoder_amdgpu_gfx940::appendOPR_VCC(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_VCC(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_VCC(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + + void InstructionDecoder_amdgpu_gfx940::appendOPR_VGPR(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_VGPR(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_VGPR(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + + void InstructionDecoder_amdgpu_gfx940::appendOPR_VGPR_OR_ACCVGPR(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_VGPR_OR_ACCVGPR(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_VGPR_OR_ACCVGPR(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + + void InstructionDecoder_amdgpu_gfx940::appendOPR_VGPR_OR_LDS(uint64_t input, bool isRead, bool isWritten, uint32_t vec_len /*= 1*/ , bool isImplicit /*= false*/) + { + Expression::Ptr first = decodeOPR_VGPR_OR_LDS(input,vec_len); + insn_in_progress->appendOperand(first,isRead,isWritten,isImplicit); + if (dyncompat::dynamic_pointer_cast(first) != NULL) + { + for (uint32_t vec_id = 1; vec_id < vec_len; vec_id++) + { + insn_in_progress->appendOperand(decodeOPR_VGPR_OR_LDS(input+vec_id,0),isRead,isWritten,isImplicit); + } + } + } + +} +} diff --git a/instructionAPI/src/AMDGPU/gfx940/decodeOperands.C b/instructionAPI/src/AMDGPU/gfx940/decodeOperands.C new file mode 100644 index 0000000000..7ecf1a7da7 --- /dev/null +++ b/instructionAPI/src/AMDGPU/gfx940/decodeOperands.C @@ -0,0 +1,6550 @@ +#include "registers/AMDGPU/amdgpu_gfx940_regs.h" +#include "InstructionDecoder-amdgpu-gfx940.h" + +namespace Dyninst { +namespace InstructionAPI { + Expression::Ptr InstructionDecoder_amdgpu_gfx940::decodeOPR_ACCVGPR(uint64_t input, uint32_t output_vec_len) + { + switch (input) { + case 0: return makeRegisterExpression(amdgpu_gfx940::acc0, output_vec_len ); + case 1: return makeRegisterExpression(amdgpu_gfx940::acc1, output_vec_len ); + case 2: return makeRegisterExpression(amdgpu_gfx940::acc2, output_vec_len ); + case 3: return makeRegisterExpression(amdgpu_gfx940::acc3, output_vec_len ); + case 4: return makeRegisterExpression(amdgpu_gfx940::acc4, output_vec_len ); + case 5: return makeRegisterExpression(amdgpu_gfx940::acc5, output_vec_len ); + case 6: return makeRegisterExpression(amdgpu_gfx940::acc6, output_vec_len ); + case 7: return makeRegisterExpression(amdgpu_gfx940::acc7, output_vec_len ); + case 8: return makeRegisterExpression(amdgpu_gfx940::acc8, output_vec_len ); + case 9: return makeRegisterExpression(amdgpu_gfx940::acc9, output_vec_len ); + case 10: return makeRegisterExpression(amdgpu_gfx940::acc10, output_vec_len ); + case 11: return makeRegisterExpression(amdgpu_gfx940::acc11, output_vec_len ); + case 12: return makeRegisterExpression(amdgpu_gfx940::acc12, output_vec_len ); + case 13: return makeRegisterExpression(amdgpu_gfx940::acc13, output_vec_len ); + case 14: return makeRegisterExpression(amdgpu_gfx940::acc14, output_vec_len ); + case 15: return makeRegisterExpression(amdgpu_gfx940::acc15, output_vec_len ); + case 16: return makeRegisterExpression(amdgpu_gfx940::acc16, output_vec_len ); + case 17: return makeRegisterExpression(amdgpu_gfx940::acc17, output_vec_len ); + case 18: return makeRegisterExpression(amdgpu_gfx940::acc18, output_vec_len ); + case 19: return makeRegisterExpression(amdgpu_gfx940::acc19, output_vec_len ); + case 20: return makeRegisterExpression(amdgpu_gfx940::acc20, output_vec_len ); + case 21: return makeRegisterExpression(amdgpu_gfx940::acc21, output_vec_len ); + case 22: return makeRegisterExpression(amdgpu_gfx940::acc22, output_vec_len ); + case 23: return makeRegisterExpression(amdgpu_gfx940::acc23, output_vec_len ); + case 24: return makeRegisterExpression(amdgpu_gfx940::acc24, output_vec_len ); + case 25: return makeRegisterExpression(amdgpu_gfx940::acc25, output_vec_len ); + case 26: return makeRegisterExpression(amdgpu_gfx940::acc26, output_vec_len ); + case 27: return makeRegisterExpression(amdgpu_gfx940::acc27, output_vec_len ); + case 28: return makeRegisterExpression(amdgpu_gfx940::acc28, output_vec_len ); + case 29: return makeRegisterExpression(amdgpu_gfx940::acc29, output_vec_len ); + case 30: return makeRegisterExpression(amdgpu_gfx940::acc30, output_vec_len ); + case 31: return makeRegisterExpression(amdgpu_gfx940::acc31, output_vec_len ); + case 32: return makeRegisterExpression(amdgpu_gfx940::acc32, output_vec_len ); + case 33: return makeRegisterExpression(amdgpu_gfx940::acc33, output_vec_len ); + case 34: return makeRegisterExpression(amdgpu_gfx940::acc34, output_vec_len ); + case 35: return makeRegisterExpression(amdgpu_gfx940::acc35, output_vec_len ); + case 36: return makeRegisterExpression(amdgpu_gfx940::acc36, output_vec_len ); + case 37: return makeRegisterExpression(amdgpu_gfx940::acc37, output_vec_len ); + case 38: return makeRegisterExpression(amdgpu_gfx940::acc38, output_vec_len ); + case 39: return makeRegisterExpression(amdgpu_gfx940::acc39, output_vec_len ); + case 40: return makeRegisterExpression(amdgpu_gfx940::acc40, output_vec_len ); + case 41: return makeRegisterExpression(amdgpu_gfx940::acc41, output_vec_len ); + case 42: return makeRegisterExpression(amdgpu_gfx940::acc42, output_vec_len ); + case 43: return makeRegisterExpression(amdgpu_gfx940::acc43, output_vec_len ); + case 44: return makeRegisterExpression(amdgpu_gfx940::acc44, output_vec_len ); + case 45: return makeRegisterExpression(amdgpu_gfx940::acc45, output_vec_len ); + case 46: return makeRegisterExpression(amdgpu_gfx940::acc46, output_vec_len ); + case 47: return makeRegisterExpression(amdgpu_gfx940::acc47, output_vec_len ); + case 48: return makeRegisterExpression(amdgpu_gfx940::acc48, output_vec_len ); + case 49: return makeRegisterExpression(amdgpu_gfx940::acc49, output_vec_len ); + case 50: return makeRegisterExpression(amdgpu_gfx940::acc50, output_vec_len ); + case 51: return makeRegisterExpression(amdgpu_gfx940::acc51, output_vec_len ); + case 52: return makeRegisterExpression(amdgpu_gfx940::acc52, output_vec_len ); + case 53: return makeRegisterExpression(amdgpu_gfx940::acc53, output_vec_len ); + case 54: return makeRegisterExpression(amdgpu_gfx940::acc54, output_vec_len ); + case 55: return makeRegisterExpression(amdgpu_gfx940::acc55, output_vec_len ); + case 56: return makeRegisterExpression(amdgpu_gfx940::acc56, output_vec_len ); + case 57: return makeRegisterExpression(amdgpu_gfx940::acc57, output_vec_len ); + case 58: return makeRegisterExpression(amdgpu_gfx940::acc58, output_vec_len ); + case 59: return makeRegisterExpression(amdgpu_gfx940::acc59, output_vec_len ); + case 60: return makeRegisterExpression(amdgpu_gfx940::acc60, output_vec_len ); + case 61: return makeRegisterExpression(amdgpu_gfx940::acc61, output_vec_len ); + case 62: return makeRegisterExpression(amdgpu_gfx940::acc62, output_vec_len ); + case 63: return makeRegisterExpression(amdgpu_gfx940::acc63, output_vec_len ); + case 64: return makeRegisterExpression(amdgpu_gfx940::acc64, output_vec_len ); + case 65: return makeRegisterExpression(amdgpu_gfx940::acc65, output_vec_len ); + case 66: return makeRegisterExpression(amdgpu_gfx940::acc66, output_vec_len ); + case 67: return makeRegisterExpression(amdgpu_gfx940::acc67, output_vec_len ); + case 68: return makeRegisterExpression(amdgpu_gfx940::acc68, output_vec_len ); + case 69: return makeRegisterExpression(amdgpu_gfx940::acc69, output_vec_len ); + case 70: return makeRegisterExpression(amdgpu_gfx940::acc70, output_vec_len ); + case 71: return makeRegisterExpression(amdgpu_gfx940::acc71, output_vec_len ); + case 72: return makeRegisterExpression(amdgpu_gfx940::acc72, output_vec_len ); + case 73: return makeRegisterExpression(amdgpu_gfx940::acc73, output_vec_len ); + case 74: return makeRegisterExpression(amdgpu_gfx940::acc74, output_vec_len ); + case 75: return makeRegisterExpression(amdgpu_gfx940::acc75, output_vec_len ); + case 76: return makeRegisterExpression(amdgpu_gfx940::acc76, output_vec_len ); + case 77: return makeRegisterExpression(amdgpu_gfx940::acc77, output_vec_len ); + case 78: return makeRegisterExpression(amdgpu_gfx940::acc78, output_vec_len ); + case 79: return makeRegisterExpression(amdgpu_gfx940::acc79, output_vec_len ); + case 80: return makeRegisterExpression(amdgpu_gfx940::acc80, output_vec_len ); + case 81: return makeRegisterExpression(amdgpu_gfx940::acc81, output_vec_len ); + case 82: return makeRegisterExpression(amdgpu_gfx940::acc82, output_vec_len ); + case 83: return makeRegisterExpression(amdgpu_gfx940::acc83, output_vec_len ); + case 84: return makeRegisterExpression(amdgpu_gfx940::acc84, output_vec_len ); + case 85: return makeRegisterExpression(amdgpu_gfx940::acc85, output_vec_len ); + case 86: return makeRegisterExpression(amdgpu_gfx940::acc86, output_vec_len ); + case 87: return makeRegisterExpression(amdgpu_gfx940::acc87, output_vec_len ); + case 88: return makeRegisterExpression(amdgpu_gfx940::acc88, output_vec_len ); + case 89: return makeRegisterExpression(amdgpu_gfx940::acc89, output_vec_len ); + case 90: return makeRegisterExpression(amdgpu_gfx940::acc90, output_vec_len ); + case 91: return makeRegisterExpression(amdgpu_gfx940::acc91, output_vec_len ); + case 92: return makeRegisterExpression(amdgpu_gfx940::acc92, output_vec_len ); + case 93: return makeRegisterExpression(amdgpu_gfx940::acc93, output_vec_len ); + case 94: return makeRegisterExpression(amdgpu_gfx940::acc94, output_vec_len ); + case 95: return makeRegisterExpression(amdgpu_gfx940::acc95, output_vec_len ); + case 96: return makeRegisterExpression(amdgpu_gfx940::acc96, output_vec_len ); + case 97: return makeRegisterExpression(amdgpu_gfx940::acc97, output_vec_len ); + case 98: return makeRegisterExpression(amdgpu_gfx940::acc98, output_vec_len ); + case 99: return makeRegisterExpression(amdgpu_gfx940::acc99, output_vec_len ); + case 100: return makeRegisterExpression(amdgpu_gfx940::acc100, output_vec_len ); + case 101: return makeRegisterExpression(amdgpu_gfx940::acc101, output_vec_len ); + case 102: return makeRegisterExpression(amdgpu_gfx940::acc102, output_vec_len ); + case 103: return makeRegisterExpression(amdgpu_gfx940::acc103, output_vec_len ); + case 104: return makeRegisterExpression(amdgpu_gfx940::acc104, output_vec_len ); + case 105: return makeRegisterExpression(amdgpu_gfx940::acc105, output_vec_len ); + case 106: return makeRegisterExpression(amdgpu_gfx940::acc106, output_vec_len ); + case 107: return makeRegisterExpression(amdgpu_gfx940::acc107, output_vec_len ); + case 108: return makeRegisterExpression(amdgpu_gfx940::acc108, output_vec_len ); + case 109: return makeRegisterExpression(amdgpu_gfx940::acc109, output_vec_len ); + case 110: return makeRegisterExpression(amdgpu_gfx940::acc110, output_vec_len ); + case 111: return makeRegisterExpression(amdgpu_gfx940::acc111, output_vec_len ); + case 112: return makeRegisterExpression(amdgpu_gfx940::acc112, output_vec_len ); + case 113: return makeRegisterExpression(amdgpu_gfx940::acc113, output_vec_len ); + case 114: return makeRegisterExpression(amdgpu_gfx940::acc114, output_vec_len ); + case 115: return makeRegisterExpression(amdgpu_gfx940::acc115, output_vec_len ); + case 116: return makeRegisterExpression(amdgpu_gfx940::acc116, output_vec_len ); + case 117: return makeRegisterExpression(amdgpu_gfx940::acc117, output_vec_len ); + case 118: return makeRegisterExpression(amdgpu_gfx940::acc118, output_vec_len ); + case 119: return makeRegisterExpression(amdgpu_gfx940::acc119, output_vec_len ); + case 120: return makeRegisterExpression(amdgpu_gfx940::acc120, output_vec_len ); + case 121: return makeRegisterExpression(amdgpu_gfx940::acc121, output_vec_len ); + case 122: return makeRegisterExpression(amdgpu_gfx940::acc122, output_vec_len ); + case 123: return makeRegisterExpression(amdgpu_gfx940::acc123, output_vec_len ); + case 124: return makeRegisterExpression(amdgpu_gfx940::acc124, output_vec_len ); + case 125: return makeRegisterExpression(amdgpu_gfx940::acc125, output_vec_len ); + case 126: return makeRegisterExpression(amdgpu_gfx940::acc126, output_vec_len ); + case 127: return makeRegisterExpression(amdgpu_gfx940::acc127, output_vec_len ); + case 128: return makeRegisterExpression(amdgpu_gfx940::acc128, output_vec_len ); + case 129: return makeRegisterExpression(amdgpu_gfx940::acc129, output_vec_len ); + case 130: return makeRegisterExpression(amdgpu_gfx940::acc130, output_vec_len ); + case 131: return makeRegisterExpression(amdgpu_gfx940::acc131, output_vec_len ); + case 132: return makeRegisterExpression(amdgpu_gfx940::acc132, output_vec_len ); + case 133: return makeRegisterExpression(amdgpu_gfx940::acc133, output_vec_len ); + case 134: return makeRegisterExpression(amdgpu_gfx940::acc134, output_vec_len ); + case 135: return makeRegisterExpression(amdgpu_gfx940::acc135, output_vec_len ); + case 136: return makeRegisterExpression(amdgpu_gfx940::acc136, output_vec_len ); + case 137: return makeRegisterExpression(amdgpu_gfx940::acc137, output_vec_len ); + case 138: return makeRegisterExpression(amdgpu_gfx940::acc138, output_vec_len ); + case 139: return makeRegisterExpression(amdgpu_gfx940::acc139, output_vec_len ); + case 140: return makeRegisterExpression(amdgpu_gfx940::acc140, output_vec_len ); + case 141: return makeRegisterExpression(amdgpu_gfx940::acc141, output_vec_len ); + case 142: return makeRegisterExpression(amdgpu_gfx940::acc142, output_vec_len ); + case 143: return makeRegisterExpression(amdgpu_gfx940::acc143, output_vec_len ); + case 144: return makeRegisterExpression(amdgpu_gfx940::acc144, output_vec_len ); + case 145: return makeRegisterExpression(amdgpu_gfx940::acc145, output_vec_len ); + case 146: return makeRegisterExpression(amdgpu_gfx940::acc146, output_vec_len ); + case 147: return makeRegisterExpression(amdgpu_gfx940::acc147, output_vec_len ); + case 148: return makeRegisterExpression(amdgpu_gfx940::acc148, output_vec_len ); + case 149: return makeRegisterExpression(amdgpu_gfx940::acc149, output_vec_len ); + case 150: return makeRegisterExpression(amdgpu_gfx940::acc150, output_vec_len ); + case 151: return makeRegisterExpression(amdgpu_gfx940::acc151, output_vec_len ); + case 152: return makeRegisterExpression(amdgpu_gfx940::acc152, output_vec_len ); + case 153: return makeRegisterExpression(amdgpu_gfx940::acc153, output_vec_len ); + case 154: return makeRegisterExpression(amdgpu_gfx940::acc154, output_vec_len ); + case 155: return makeRegisterExpression(amdgpu_gfx940::acc155, output_vec_len ); + case 156: return makeRegisterExpression(amdgpu_gfx940::acc156, output_vec_len ); + case 157: return makeRegisterExpression(amdgpu_gfx940::acc157, output_vec_len ); + case 158: return makeRegisterExpression(amdgpu_gfx940::acc158, output_vec_len ); + case 159: return makeRegisterExpression(amdgpu_gfx940::acc159, output_vec_len ); + case 160: return makeRegisterExpression(amdgpu_gfx940::acc160, output_vec_len ); + case 161: return makeRegisterExpression(amdgpu_gfx940::acc161, output_vec_len ); + case 162: return makeRegisterExpression(amdgpu_gfx940::acc162, output_vec_len ); + case 163: return makeRegisterExpression(amdgpu_gfx940::acc163, output_vec_len ); + case 164: return makeRegisterExpression(amdgpu_gfx940::acc164, output_vec_len ); + case 165: return makeRegisterExpression(amdgpu_gfx940::acc165, output_vec_len ); + case 166: return makeRegisterExpression(amdgpu_gfx940::acc166, output_vec_len ); + case 167: return makeRegisterExpression(amdgpu_gfx940::acc167, output_vec_len ); + case 168: return makeRegisterExpression(amdgpu_gfx940::acc168, output_vec_len ); + case 169: return makeRegisterExpression(amdgpu_gfx940::acc169, output_vec_len ); + case 170: return makeRegisterExpression(amdgpu_gfx940::acc170, output_vec_len ); + case 171: return makeRegisterExpression(amdgpu_gfx940::acc171, output_vec_len ); + case 172: return makeRegisterExpression(amdgpu_gfx940::acc172, output_vec_len ); + case 173: return makeRegisterExpression(amdgpu_gfx940::acc173, output_vec_len ); + case 174: return makeRegisterExpression(amdgpu_gfx940::acc174, output_vec_len ); + case 175: return makeRegisterExpression(amdgpu_gfx940::acc175, output_vec_len ); + case 176: return makeRegisterExpression(amdgpu_gfx940::acc176, output_vec_len ); + case 177: return makeRegisterExpression(amdgpu_gfx940::acc177, output_vec_len ); + case 178: return makeRegisterExpression(amdgpu_gfx940::acc178, output_vec_len ); + case 179: return makeRegisterExpression(amdgpu_gfx940::acc179, output_vec_len ); + case 180: return makeRegisterExpression(amdgpu_gfx940::acc180, output_vec_len ); + case 181: return makeRegisterExpression(amdgpu_gfx940::acc181, output_vec_len ); + case 182: return makeRegisterExpression(amdgpu_gfx940::acc182, output_vec_len ); + case 183: return makeRegisterExpression(amdgpu_gfx940::acc183, output_vec_len ); + case 184: return makeRegisterExpression(amdgpu_gfx940::acc184, output_vec_len ); + case 185: return makeRegisterExpression(amdgpu_gfx940::acc185, output_vec_len ); + case 186: return makeRegisterExpression(amdgpu_gfx940::acc186, output_vec_len ); + case 187: return makeRegisterExpression(amdgpu_gfx940::acc187, output_vec_len ); + case 188: return makeRegisterExpression(amdgpu_gfx940::acc188, output_vec_len ); + case 189: return makeRegisterExpression(amdgpu_gfx940::acc189, output_vec_len ); + case 190: return makeRegisterExpression(amdgpu_gfx940::acc190, output_vec_len ); + case 191: return makeRegisterExpression(amdgpu_gfx940::acc191, output_vec_len ); + case 192: return makeRegisterExpression(amdgpu_gfx940::acc192, output_vec_len ); + case 193: return makeRegisterExpression(amdgpu_gfx940::acc193, output_vec_len ); + case 194: return makeRegisterExpression(amdgpu_gfx940::acc194, output_vec_len ); + case 195: return makeRegisterExpression(amdgpu_gfx940::acc195, output_vec_len ); + case 196: return makeRegisterExpression(amdgpu_gfx940::acc196, output_vec_len ); + case 197: return makeRegisterExpression(amdgpu_gfx940::acc197, output_vec_len ); + case 198: return makeRegisterExpression(amdgpu_gfx940::acc198, output_vec_len ); + case 199: return makeRegisterExpression(amdgpu_gfx940::acc199, output_vec_len ); + case 200: return makeRegisterExpression(amdgpu_gfx940::acc200, output_vec_len ); + case 201: return makeRegisterExpression(amdgpu_gfx940::acc201, output_vec_len ); + case 202: return makeRegisterExpression(amdgpu_gfx940::acc202, output_vec_len ); + case 203: return makeRegisterExpression(amdgpu_gfx940::acc203, output_vec_len ); + case 204: return makeRegisterExpression(amdgpu_gfx940::acc204, output_vec_len ); + case 205: return makeRegisterExpression(amdgpu_gfx940::acc205, output_vec_len ); + case 206: return makeRegisterExpression(amdgpu_gfx940::acc206, output_vec_len ); + case 207: return makeRegisterExpression(amdgpu_gfx940::acc207, output_vec_len ); + case 208: return makeRegisterExpression(amdgpu_gfx940::acc208, output_vec_len ); + case 209: return makeRegisterExpression(amdgpu_gfx940::acc209, output_vec_len ); + case 210: return makeRegisterExpression(amdgpu_gfx940::acc210, output_vec_len ); + case 211: return makeRegisterExpression(amdgpu_gfx940::acc211, output_vec_len ); + case 212: return makeRegisterExpression(amdgpu_gfx940::acc212, output_vec_len ); + case 213: return makeRegisterExpression(amdgpu_gfx940::acc213, output_vec_len ); + case 214: return makeRegisterExpression(amdgpu_gfx940::acc214, output_vec_len ); + case 215: return makeRegisterExpression(amdgpu_gfx940::acc215, output_vec_len ); + case 216: return makeRegisterExpression(amdgpu_gfx940::acc216, output_vec_len ); + case 217: return makeRegisterExpression(amdgpu_gfx940::acc217, output_vec_len ); + case 218: return makeRegisterExpression(amdgpu_gfx940::acc218, output_vec_len ); + case 219: return makeRegisterExpression(amdgpu_gfx940::acc219, output_vec_len ); + case 220: return makeRegisterExpression(amdgpu_gfx940::acc220, output_vec_len ); + case 221: return makeRegisterExpression(amdgpu_gfx940::acc221, output_vec_len ); + case 222: return makeRegisterExpression(amdgpu_gfx940::acc222, output_vec_len ); + case 223: return makeRegisterExpression(amdgpu_gfx940::acc223, output_vec_len ); + case 224: return makeRegisterExpression(amdgpu_gfx940::acc224, output_vec_len ); + case 225: return makeRegisterExpression(amdgpu_gfx940::acc225, output_vec_len ); + case 226: return makeRegisterExpression(amdgpu_gfx940::acc226, output_vec_len ); + case 227: return makeRegisterExpression(amdgpu_gfx940::acc227, output_vec_len ); + case 228: return makeRegisterExpression(amdgpu_gfx940::acc228, output_vec_len ); + case 229: return makeRegisterExpression(amdgpu_gfx940::acc229, output_vec_len ); + case 230: return makeRegisterExpression(amdgpu_gfx940::acc230, output_vec_len ); + case 231: return makeRegisterExpression(amdgpu_gfx940::acc231, output_vec_len ); + case 232: return makeRegisterExpression(amdgpu_gfx940::acc232, output_vec_len ); + case 233: return makeRegisterExpression(amdgpu_gfx940::acc233, output_vec_len ); + case 234: return makeRegisterExpression(amdgpu_gfx940::acc234, output_vec_len ); + case 235: return makeRegisterExpression(amdgpu_gfx940::acc235, output_vec_len ); + case 236: return makeRegisterExpression(amdgpu_gfx940::acc236, output_vec_len ); + case 237: return makeRegisterExpression(amdgpu_gfx940::acc237, output_vec_len ); + case 238: return makeRegisterExpression(amdgpu_gfx940::acc238, output_vec_len ); + case 239: return makeRegisterExpression(amdgpu_gfx940::acc239, output_vec_len ); + case 240: return makeRegisterExpression(amdgpu_gfx940::acc240, output_vec_len ); + case 241: return makeRegisterExpression(amdgpu_gfx940::acc241, output_vec_len ); + case 242: return makeRegisterExpression(amdgpu_gfx940::acc242, output_vec_len ); + case 243: return makeRegisterExpression(amdgpu_gfx940::acc243, output_vec_len ); + case 244: return makeRegisterExpression(amdgpu_gfx940::acc244, output_vec_len ); + case 245: return makeRegisterExpression(amdgpu_gfx940::acc245, output_vec_len ); + case 246: return makeRegisterExpression(amdgpu_gfx940::acc246, output_vec_len ); + case 247: return makeRegisterExpression(amdgpu_gfx940::acc247, output_vec_len ); + case 248: return makeRegisterExpression(amdgpu_gfx940::acc248, output_vec_len ); + case 249: return makeRegisterExpression(amdgpu_gfx940::acc249, output_vec_len ); + case 250: return makeRegisterExpression(amdgpu_gfx940::acc250, output_vec_len ); + case 251: return makeRegisterExpression(amdgpu_gfx940::acc251, output_vec_len ); + case 252: return makeRegisterExpression(amdgpu_gfx940::acc252, output_vec_len ); + case 253: return makeRegisterExpression(amdgpu_gfx940::acc253, output_vec_len ); + case 254: return makeRegisterExpression(amdgpu_gfx940::acc254, output_vec_len ); + case 255: return makeRegisterExpression(amdgpu_gfx940::acc255, output_vec_len ); + case 512: return makeRegisterExpression(amdgpu_gfx940::acc0, output_vec_len ); + case 513: return makeRegisterExpression(amdgpu_gfx940::acc1, output_vec_len ); + case 514: return makeRegisterExpression(amdgpu_gfx940::acc2, output_vec_len ); + case 515: return makeRegisterExpression(amdgpu_gfx940::acc3, output_vec_len ); + case 516: return makeRegisterExpression(amdgpu_gfx940::acc4, output_vec_len ); + case 517: return makeRegisterExpression(amdgpu_gfx940::acc5, output_vec_len ); + case 518: return makeRegisterExpression(amdgpu_gfx940::acc6, output_vec_len ); + case 519: return makeRegisterExpression(amdgpu_gfx940::acc7, output_vec_len ); + case 520: return makeRegisterExpression(amdgpu_gfx940::acc8, output_vec_len ); + case 521: return makeRegisterExpression(amdgpu_gfx940::acc9, output_vec_len ); + case 522: return makeRegisterExpression(amdgpu_gfx940::acc10, output_vec_len ); + case 523: return makeRegisterExpression(amdgpu_gfx940::acc11, output_vec_len ); + case 524: return makeRegisterExpression(amdgpu_gfx940::acc12, output_vec_len ); + case 525: return makeRegisterExpression(amdgpu_gfx940::acc13, output_vec_len ); + case 526: return makeRegisterExpression(amdgpu_gfx940::acc14, output_vec_len ); + case 527: return makeRegisterExpression(amdgpu_gfx940::acc15, output_vec_len ); + case 528: return makeRegisterExpression(amdgpu_gfx940::acc16, output_vec_len ); + case 529: return makeRegisterExpression(amdgpu_gfx940::acc17, output_vec_len ); + case 530: return makeRegisterExpression(amdgpu_gfx940::acc18, output_vec_len ); + case 531: return makeRegisterExpression(amdgpu_gfx940::acc19, output_vec_len ); + case 532: return makeRegisterExpression(amdgpu_gfx940::acc20, output_vec_len ); + case 533: return makeRegisterExpression(amdgpu_gfx940::acc21, output_vec_len ); + case 534: return makeRegisterExpression(amdgpu_gfx940::acc22, output_vec_len ); + case 535: return makeRegisterExpression(amdgpu_gfx940::acc23, output_vec_len ); + case 536: return makeRegisterExpression(amdgpu_gfx940::acc24, output_vec_len ); + case 537: return makeRegisterExpression(amdgpu_gfx940::acc25, output_vec_len ); + case 538: return makeRegisterExpression(amdgpu_gfx940::acc26, output_vec_len ); + case 539: return makeRegisterExpression(amdgpu_gfx940::acc27, output_vec_len ); + case 540: return makeRegisterExpression(amdgpu_gfx940::acc28, output_vec_len ); + case 541: return makeRegisterExpression(amdgpu_gfx940::acc29, output_vec_len ); + case 542: return makeRegisterExpression(amdgpu_gfx940::acc30, output_vec_len ); + case 543: return makeRegisterExpression(amdgpu_gfx940::acc31, output_vec_len ); + case 544: return makeRegisterExpression(amdgpu_gfx940::acc32, output_vec_len ); + case 545: return makeRegisterExpression(amdgpu_gfx940::acc33, output_vec_len ); + case 546: return makeRegisterExpression(amdgpu_gfx940::acc34, output_vec_len ); + case 547: return makeRegisterExpression(amdgpu_gfx940::acc35, output_vec_len ); + case 548: return makeRegisterExpression(amdgpu_gfx940::acc36, output_vec_len ); + case 549: return makeRegisterExpression(amdgpu_gfx940::acc37, output_vec_len ); + case 550: return makeRegisterExpression(amdgpu_gfx940::acc38, output_vec_len ); + case 551: return makeRegisterExpression(amdgpu_gfx940::acc39, output_vec_len ); + case 552: return makeRegisterExpression(amdgpu_gfx940::acc40, output_vec_len ); + case 553: return makeRegisterExpression(amdgpu_gfx940::acc41, output_vec_len ); + case 554: return makeRegisterExpression(amdgpu_gfx940::acc42, output_vec_len ); + case 555: return makeRegisterExpression(amdgpu_gfx940::acc43, output_vec_len ); + case 556: return makeRegisterExpression(amdgpu_gfx940::acc44, output_vec_len ); + case 557: return makeRegisterExpression(amdgpu_gfx940::acc45, output_vec_len ); + case 558: return makeRegisterExpression(amdgpu_gfx940::acc46, output_vec_len ); + case 559: return makeRegisterExpression(amdgpu_gfx940::acc47, output_vec_len ); + case 560: return makeRegisterExpression(amdgpu_gfx940::acc48, output_vec_len ); + case 561: return makeRegisterExpression(amdgpu_gfx940::acc49, output_vec_len ); + case 562: return makeRegisterExpression(amdgpu_gfx940::acc50, output_vec_len ); + case 563: return makeRegisterExpression(amdgpu_gfx940::acc51, output_vec_len ); + case 564: return makeRegisterExpression(amdgpu_gfx940::acc52, output_vec_len ); + case 565: return makeRegisterExpression(amdgpu_gfx940::acc53, output_vec_len ); + case 566: return makeRegisterExpression(amdgpu_gfx940::acc54, output_vec_len ); + case 567: return makeRegisterExpression(amdgpu_gfx940::acc55, output_vec_len ); + case 568: return makeRegisterExpression(amdgpu_gfx940::acc56, output_vec_len ); + case 569: return makeRegisterExpression(amdgpu_gfx940::acc57, output_vec_len ); + case 570: return makeRegisterExpression(amdgpu_gfx940::acc58, output_vec_len ); + case 571: return makeRegisterExpression(amdgpu_gfx940::acc59, output_vec_len ); + case 572: return makeRegisterExpression(amdgpu_gfx940::acc60, output_vec_len ); + case 573: return makeRegisterExpression(amdgpu_gfx940::acc61, output_vec_len ); + case 574: return makeRegisterExpression(amdgpu_gfx940::acc62, output_vec_len ); + case 575: return makeRegisterExpression(amdgpu_gfx940::acc63, output_vec_len ); + case 576: return makeRegisterExpression(amdgpu_gfx940::acc64, output_vec_len ); + case 577: return makeRegisterExpression(amdgpu_gfx940::acc65, output_vec_len ); + case 578: return makeRegisterExpression(amdgpu_gfx940::acc66, output_vec_len ); + case 579: return makeRegisterExpression(amdgpu_gfx940::acc67, output_vec_len ); + case 580: return makeRegisterExpression(amdgpu_gfx940::acc68, output_vec_len ); + case 581: return makeRegisterExpression(amdgpu_gfx940::acc69, output_vec_len ); + case 582: return makeRegisterExpression(amdgpu_gfx940::acc70, output_vec_len ); + case 583: return makeRegisterExpression(amdgpu_gfx940::acc71, output_vec_len ); + case 584: return makeRegisterExpression(amdgpu_gfx940::acc72, output_vec_len ); + case 585: return makeRegisterExpression(amdgpu_gfx940::acc73, output_vec_len ); + case 586: return makeRegisterExpression(amdgpu_gfx940::acc74, output_vec_len ); + case 587: return makeRegisterExpression(amdgpu_gfx940::acc75, output_vec_len ); + case 588: return makeRegisterExpression(amdgpu_gfx940::acc76, output_vec_len ); + case 589: return makeRegisterExpression(amdgpu_gfx940::acc77, output_vec_len ); + case 590: return makeRegisterExpression(amdgpu_gfx940::acc78, output_vec_len ); + case 591: return makeRegisterExpression(amdgpu_gfx940::acc79, output_vec_len ); + case 592: return makeRegisterExpression(amdgpu_gfx940::acc80, output_vec_len ); + case 593: return makeRegisterExpression(amdgpu_gfx940::acc81, output_vec_len ); + case 594: return makeRegisterExpression(amdgpu_gfx940::acc82, output_vec_len ); + case 595: return makeRegisterExpression(amdgpu_gfx940::acc83, output_vec_len ); + case 596: return makeRegisterExpression(amdgpu_gfx940::acc84, output_vec_len ); + case 597: return makeRegisterExpression(amdgpu_gfx940::acc85, output_vec_len ); + case 598: return makeRegisterExpression(amdgpu_gfx940::acc86, output_vec_len ); + case 599: return makeRegisterExpression(amdgpu_gfx940::acc87, output_vec_len ); + case 600: return makeRegisterExpression(amdgpu_gfx940::acc88, output_vec_len ); + case 601: return makeRegisterExpression(amdgpu_gfx940::acc89, output_vec_len ); + case 602: return makeRegisterExpression(amdgpu_gfx940::acc90, output_vec_len ); + case 603: return makeRegisterExpression(amdgpu_gfx940::acc91, output_vec_len ); + case 604: return makeRegisterExpression(amdgpu_gfx940::acc92, output_vec_len ); + case 605: return makeRegisterExpression(amdgpu_gfx940::acc93, output_vec_len ); + case 606: return makeRegisterExpression(amdgpu_gfx940::acc94, output_vec_len ); + case 607: return makeRegisterExpression(amdgpu_gfx940::acc95, output_vec_len ); + case 608: return makeRegisterExpression(amdgpu_gfx940::acc96, output_vec_len ); + case 609: return makeRegisterExpression(amdgpu_gfx940::acc97, output_vec_len ); + case 610: return makeRegisterExpression(amdgpu_gfx940::acc98, output_vec_len ); + case 611: return makeRegisterExpression(amdgpu_gfx940::acc99, output_vec_len ); + case 612: return makeRegisterExpression(amdgpu_gfx940::acc100, output_vec_len ); + case 613: return makeRegisterExpression(amdgpu_gfx940::acc101, output_vec_len ); + case 614: return makeRegisterExpression(amdgpu_gfx940::acc102, output_vec_len ); + case 615: return makeRegisterExpression(amdgpu_gfx940::acc103, output_vec_len ); + case 616: return makeRegisterExpression(amdgpu_gfx940::acc104, output_vec_len ); + case 617: return makeRegisterExpression(amdgpu_gfx940::acc105, output_vec_len ); + case 618: return makeRegisterExpression(amdgpu_gfx940::acc106, output_vec_len ); + case 619: return makeRegisterExpression(amdgpu_gfx940::acc107, output_vec_len ); + case 620: return makeRegisterExpression(amdgpu_gfx940::acc108, output_vec_len ); + case 621: return makeRegisterExpression(amdgpu_gfx940::acc109, output_vec_len ); + case 622: return makeRegisterExpression(amdgpu_gfx940::acc110, output_vec_len ); + case 623: return makeRegisterExpression(amdgpu_gfx940::acc111, output_vec_len ); + case 624: return makeRegisterExpression(amdgpu_gfx940::acc112, output_vec_len ); + case 625: return makeRegisterExpression(amdgpu_gfx940::acc113, output_vec_len ); + case 626: return makeRegisterExpression(amdgpu_gfx940::acc114, output_vec_len ); + case 627: return makeRegisterExpression(amdgpu_gfx940::acc115, output_vec_len ); + case 628: return makeRegisterExpression(amdgpu_gfx940::acc116, output_vec_len ); + case 629: return makeRegisterExpression(amdgpu_gfx940::acc117, output_vec_len ); + case 630: return makeRegisterExpression(amdgpu_gfx940::acc118, output_vec_len ); + case 631: return makeRegisterExpression(amdgpu_gfx940::acc119, output_vec_len ); + case 632: return makeRegisterExpression(amdgpu_gfx940::acc120, output_vec_len ); + case 633: return makeRegisterExpression(amdgpu_gfx940::acc121, output_vec_len ); + case 634: return makeRegisterExpression(amdgpu_gfx940::acc122, output_vec_len ); + case 635: return makeRegisterExpression(amdgpu_gfx940::acc123, output_vec_len ); + case 636: return makeRegisterExpression(amdgpu_gfx940::acc124, output_vec_len ); + case 637: return makeRegisterExpression(amdgpu_gfx940::acc125, output_vec_len ); + case 638: return makeRegisterExpression(amdgpu_gfx940::acc126, output_vec_len ); + case 639: return makeRegisterExpression(amdgpu_gfx940::acc127, output_vec_len ); + case 640: return makeRegisterExpression(amdgpu_gfx940::acc128, output_vec_len ); + case 641: return makeRegisterExpression(amdgpu_gfx940::acc129, output_vec_len ); + case 642: return makeRegisterExpression(amdgpu_gfx940::acc130, output_vec_len ); + case 643: return makeRegisterExpression(amdgpu_gfx940::acc131, output_vec_len ); + case 644: return makeRegisterExpression(amdgpu_gfx940::acc132, output_vec_len ); + case 645: return makeRegisterExpression(amdgpu_gfx940::acc133, output_vec_len ); + case 646: return makeRegisterExpression(amdgpu_gfx940::acc134, output_vec_len ); + case 647: return makeRegisterExpression(amdgpu_gfx940::acc135, output_vec_len ); + case 648: return makeRegisterExpression(amdgpu_gfx940::acc136, output_vec_len ); + case 649: return makeRegisterExpression(amdgpu_gfx940::acc137, output_vec_len ); + case 650: return makeRegisterExpression(amdgpu_gfx940::acc138, output_vec_len ); + case 651: return makeRegisterExpression(amdgpu_gfx940::acc139, output_vec_len ); + case 652: return makeRegisterExpression(amdgpu_gfx940::acc140, output_vec_len ); + case 653: return makeRegisterExpression(amdgpu_gfx940::acc141, output_vec_len ); + case 654: return makeRegisterExpression(amdgpu_gfx940::acc142, output_vec_len ); + case 655: return makeRegisterExpression(amdgpu_gfx940::acc143, output_vec_len ); + case 656: return makeRegisterExpression(amdgpu_gfx940::acc144, output_vec_len ); + case 657: return makeRegisterExpression(amdgpu_gfx940::acc145, output_vec_len ); + case 658: return makeRegisterExpression(amdgpu_gfx940::acc146, output_vec_len ); + case 659: return makeRegisterExpression(amdgpu_gfx940::acc147, output_vec_len ); + case 660: return makeRegisterExpression(amdgpu_gfx940::acc148, output_vec_len ); + case 661: return makeRegisterExpression(amdgpu_gfx940::acc149, output_vec_len ); + case 662: return makeRegisterExpression(amdgpu_gfx940::acc150, output_vec_len ); + case 663: return makeRegisterExpression(amdgpu_gfx940::acc151, output_vec_len ); + case 664: return makeRegisterExpression(amdgpu_gfx940::acc152, output_vec_len ); + case 665: return makeRegisterExpression(amdgpu_gfx940::acc153, output_vec_len ); + case 666: return makeRegisterExpression(amdgpu_gfx940::acc154, output_vec_len ); + case 667: return makeRegisterExpression(amdgpu_gfx940::acc155, output_vec_len ); + case 668: return makeRegisterExpression(amdgpu_gfx940::acc156, output_vec_len ); + case 669: return makeRegisterExpression(amdgpu_gfx940::acc157, output_vec_len ); + case 670: return makeRegisterExpression(amdgpu_gfx940::acc158, output_vec_len ); + case 671: return makeRegisterExpression(amdgpu_gfx940::acc159, output_vec_len ); + case 672: return makeRegisterExpression(amdgpu_gfx940::acc160, output_vec_len ); + case 673: return makeRegisterExpression(amdgpu_gfx940::acc161, output_vec_len ); + case 674: return makeRegisterExpression(amdgpu_gfx940::acc162, output_vec_len ); + case 675: return makeRegisterExpression(amdgpu_gfx940::acc163, output_vec_len ); + case 676: return makeRegisterExpression(amdgpu_gfx940::acc164, output_vec_len ); + case 677: return makeRegisterExpression(amdgpu_gfx940::acc165, output_vec_len ); + case 678: return makeRegisterExpression(amdgpu_gfx940::acc166, output_vec_len ); + case 679: return makeRegisterExpression(amdgpu_gfx940::acc167, output_vec_len ); + case 680: return makeRegisterExpression(amdgpu_gfx940::acc168, output_vec_len ); + case 681: return makeRegisterExpression(amdgpu_gfx940::acc169, output_vec_len ); + case 682: return makeRegisterExpression(amdgpu_gfx940::acc170, output_vec_len ); + case 683: return makeRegisterExpression(amdgpu_gfx940::acc171, output_vec_len ); + case 684: return makeRegisterExpression(amdgpu_gfx940::acc172, output_vec_len ); + case 685: return makeRegisterExpression(amdgpu_gfx940::acc173, output_vec_len ); + case 686: return makeRegisterExpression(amdgpu_gfx940::acc174, output_vec_len ); + case 687: return makeRegisterExpression(amdgpu_gfx940::acc175, output_vec_len ); + case 688: return makeRegisterExpression(amdgpu_gfx940::acc176, output_vec_len ); + case 689: return makeRegisterExpression(amdgpu_gfx940::acc177, output_vec_len ); + case 690: return makeRegisterExpression(amdgpu_gfx940::acc178, output_vec_len ); + case 691: return makeRegisterExpression(amdgpu_gfx940::acc179, output_vec_len ); + case 692: return makeRegisterExpression(amdgpu_gfx940::acc180, output_vec_len ); + case 693: return makeRegisterExpression(amdgpu_gfx940::acc181, output_vec_len ); + case 694: return makeRegisterExpression(amdgpu_gfx940::acc182, output_vec_len ); + case 695: return makeRegisterExpression(amdgpu_gfx940::acc183, output_vec_len ); + case 696: return makeRegisterExpression(amdgpu_gfx940::acc184, output_vec_len ); + case 697: return makeRegisterExpression(amdgpu_gfx940::acc185, output_vec_len ); + case 698: return makeRegisterExpression(amdgpu_gfx940::acc186, output_vec_len ); + case 699: return makeRegisterExpression(amdgpu_gfx940::acc187, output_vec_len ); + case 700: return makeRegisterExpression(amdgpu_gfx940::acc188, output_vec_len ); + case 701: return makeRegisterExpression(amdgpu_gfx940::acc189, output_vec_len ); + case 702: return makeRegisterExpression(amdgpu_gfx940::acc190, output_vec_len ); + case 703: return makeRegisterExpression(amdgpu_gfx940::acc191, output_vec_len ); + case 704: return makeRegisterExpression(amdgpu_gfx940::acc192, output_vec_len ); + case 705: return makeRegisterExpression(amdgpu_gfx940::acc193, output_vec_len ); + case 706: return makeRegisterExpression(amdgpu_gfx940::acc194, output_vec_len ); + case 707: return makeRegisterExpression(amdgpu_gfx940::acc195, output_vec_len ); + case 708: return makeRegisterExpression(amdgpu_gfx940::acc196, output_vec_len ); + case 709: return makeRegisterExpression(amdgpu_gfx940::acc197, output_vec_len ); + case 710: return makeRegisterExpression(amdgpu_gfx940::acc198, output_vec_len ); + case 711: return makeRegisterExpression(amdgpu_gfx940::acc199, output_vec_len ); + case 712: return makeRegisterExpression(amdgpu_gfx940::acc200, output_vec_len ); + case 713: return makeRegisterExpression(amdgpu_gfx940::acc201, output_vec_len ); + case 714: return makeRegisterExpression(amdgpu_gfx940::acc202, output_vec_len ); + case 715: return makeRegisterExpression(amdgpu_gfx940::acc203, output_vec_len ); + case 716: return makeRegisterExpression(amdgpu_gfx940::acc204, output_vec_len ); + case 717: return makeRegisterExpression(amdgpu_gfx940::acc205, output_vec_len ); + case 718: return makeRegisterExpression(amdgpu_gfx940::acc206, output_vec_len ); + case 719: return makeRegisterExpression(amdgpu_gfx940::acc207, output_vec_len ); + case 720: return makeRegisterExpression(amdgpu_gfx940::acc208, output_vec_len ); + case 721: return makeRegisterExpression(amdgpu_gfx940::acc209, output_vec_len ); + case 722: return makeRegisterExpression(amdgpu_gfx940::acc210, output_vec_len ); + case 723: return makeRegisterExpression(amdgpu_gfx940::acc211, output_vec_len ); + case 724: return makeRegisterExpression(amdgpu_gfx940::acc212, output_vec_len ); + case 725: return makeRegisterExpression(amdgpu_gfx940::acc213, output_vec_len ); + case 726: return makeRegisterExpression(amdgpu_gfx940::acc214, output_vec_len ); + case 727: return makeRegisterExpression(amdgpu_gfx940::acc215, output_vec_len ); + case 728: return makeRegisterExpression(amdgpu_gfx940::acc216, output_vec_len ); + case 729: return makeRegisterExpression(amdgpu_gfx940::acc217, output_vec_len ); + case 730: return makeRegisterExpression(amdgpu_gfx940::acc218, output_vec_len ); + case 731: return makeRegisterExpression(amdgpu_gfx940::acc219, output_vec_len ); + case 732: return makeRegisterExpression(amdgpu_gfx940::acc220, output_vec_len ); + case 733: return makeRegisterExpression(amdgpu_gfx940::acc221, output_vec_len ); + case 734: return makeRegisterExpression(amdgpu_gfx940::acc222, output_vec_len ); + case 735: return makeRegisterExpression(amdgpu_gfx940::acc223, output_vec_len ); + case 736: return makeRegisterExpression(amdgpu_gfx940::acc224, output_vec_len ); + case 737: return makeRegisterExpression(amdgpu_gfx940::acc225, output_vec_len ); + case 738: return makeRegisterExpression(amdgpu_gfx940::acc226, output_vec_len ); + case 739: return makeRegisterExpression(amdgpu_gfx940::acc227, output_vec_len ); + case 740: return makeRegisterExpression(amdgpu_gfx940::acc228, output_vec_len ); + case 741: return makeRegisterExpression(amdgpu_gfx940::acc229, output_vec_len ); + case 742: return makeRegisterExpression(amdgpu_gfx940::acc230, output_vec_len ); + case 743: return makeRegisterExpression(amdgpu_gfx940::acc231, output_vec_len ); + case 744: return makeRegisterExpression(amdgpu_gfx940::acc232, output_vec_len ); + case 745: return makeRegisterExpression(amdgpu_gfx940::acc233, output_vec_len ); + case 746: return makeRegisterExpression(amdgpu_gfx940::acc234, output_vec_len ); + case 747: return makeRegisterExpression(amdgpu_gfx940::acc235, output_vec_len ); + case 748: return makeRegisterExpression(amdgpu_gfx940::acc236, output_vec_len ); + case 749: return makeRegisterExpression(amdgpu_gfx940::acc237, output_vec_len ); + case 750: return makeRegisterExpression(amdgpu_gfx940::acc238, output_vec_len ); + case 751: return makeRegisterExpression(amdgpu_gfx940::acc239, output_vec_len ); + case 752: return makeRegisterExpression(amdgpu_gfx940::acc240, output_vec_len ); + case 753: return makeRegisterExpression(amdgpu_gfx940::acc241, output_vec_len ); + case 754: return makeRegisterExpression(amdgpu_gfx940::acc242, output_vec_len ); + case 755: return makeRegisterExpression(amdgpu_gfx940::acc243, output_vec_len ); + case 756: return makeRegisterExpression(amdgpu_gfx940::acc244, output_vec_len ); + case 757: return makeRegisterExpression(amdgpu_gfx940::acc245, output_vec_len ); + case 758: return makeRegisterExpression(amdgpu_gfx940::acc246, output_vec_len ); + case 759: return makeRegisterExpression(amdgpu_gfx940::acc247, output_vec_len ); + case 760: return makeRegisterExpression(amdgpu_gfx940::acc248, output_vec_len ); + case 761: return makeRegisterExpression(amdgpu_gfx940::acc249, output_vec_len ); + case 762: return makeRegisterExpression(amdgpu_gfx940::acc250, output_vec_len ); + case 763: return makeRegisterExpression(amdgpu_gfx940::acc251, output_vec_len ); + case 764: return makeRegisterExpression(amdgpu_gfx940::acc252, output_vec_len ); + case 765: return makeRegisterExpression(amdgpu_gfx940::acc253, output_vec_len ); + case 766: return makeRegisterExpression(amdgpu_gfx940::acc254, output_vec_len ); + case 767: return makeRegisterExpression(amdgpu_gfx940::acc255, output_vec_len ); + default: return makeRegisterExpression(amdgpu_gfx940::invalid); + } + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx940::decodeOPR_DSMEM(uint64_t input, uint32_t output_vec_len) + { + switch (input) { + case 0: return makeRegisterExpression(amdgpu_gfx940::dsmem, output_vec_len ); + default: return makeRegisterExpression(amdgpu_gfx940::invalid); + } + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx940::decodeOPR_FLAT_SCRATCH(uint64_t input, uint32_t output_vec_len) + { + switch (input) { + case 0: return makeRegisterExpression(amdgpu_gfx940::flat_scratch_all, output_vec_len ); + default: return makeRegisterExpression(amdgpu_gfx940::invalid); + } + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx940::decodeOPR_PC(uint64_t input, uint32_t ) + { + switch (input) { + case 0: return makeRegisterExpression(amdgpu_gfx940::pc_all); + default: return makeRegisterExpression(amdgpu_gfx940::invalid); + } + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx940::decodeOPR_SDST(uint64_t input, uint32_t output_vec_len) + { + switch (input) { + case 0: return makeRegisterExpression(amdgpu_gfx940::s0, output_vec_len ); + case 1: return makeRegisterExpression(amdgpu_gfx940::s1, output_vec_len ); + case 2: return makeRegisterExpression(amdgpu_gfx940::s2, output_vec_len ); + case 3: return makeRegisterExpression(amdgpu_gfx940::s3, output_vec_len ); + case 4: return makeRegisterExpression(amdgpu_gfx940::s4, output_vec_len ); + case 5: return makeRegisterExpression(amdgpu_gfx940::s5, output_vec_len ); + case 6: return makeRegisterExpression(amdgpu_gfx940::s6, output_vec_len ); + case 7: return makeRegisterExpression(amdgpu_gfx940::s7, output_vec_len ); + case 8: return makeRegisterExpression(amdgpu_gfx940::s8, output_vec_len ); + case 9: return makeRegisterExpression(amdgpu_gfx940::s9, output_vec_len ); + case 10: return makeRegisterExpression(amdgpu_gfx940::s10, output_vec_len ); + case 11: return makeRegisterExpression(amdgpu_gfx940::s11, output_vec_len ); + case 12: return makeRegisterExpression(amdgpu_gfx940::s12, output_vec_len ); + case 13: return makeRegisterExpression(amdgpu_gfx940::s13, output_vec_len ); + case 14: return makeRegisterExpression(amdgpu_gfx940::s14, output_vec_len ); + case 15: return makeRegisterExpression(amdgpu_gfx940::s15, output_vec_len ); + case 16: return makeRegisterExpression(amdgpu_gfx940::s16, output_vec_len ); + case 17: return makeRegisterExpression(amdgpu_gfx940::s17, output_vec_len ); + case 18: return makeRegisterExpression(amdgpu_gfx940::s18, output_vec_len ); + case 19: return makeRegisterExpression(amdgpu_gfx940::s19, output_vec_len ); + case 20: return makeRegisterExpression(amdgpu_gfx940::s20, output_vec_len ); + case 21: return makeRegisterExpression(amdgpu_gfx940::s21, output_vec_len ); + case 22: return makeRegisterExpression(amdgpu_gfx940::s22, output_vec_len ); + case 23: return makeRegisterExpression(amdgpu_gfx940::s23, output_vec_len ); + case 24: return makeRegisterExpression(amdgpu_gfx940::s24, output_vec_len ); + case 25: return makeRegisterExpression(amdgpu_gfx940::s25, output_vec_len ); + case 26: return makeRegisterExpression(amdgpu_gfx940::s26, output_vec_len ); + case 27: return makeRegisterExpression(amdgpu_gfx940::s27, output_vec_len ); + case 28: return makeRegisterExpression(amdgpu_gfx940::s28, output_vec_len ); + case 29: return makeRegisterExpression(amdgpu_gfx940::s29, output_vec_len ); + case 30: return makeRegisterExpression(amdgpu_gfx940::s30, output_vec_len ); + case 31: return makeRegisterExpression(amdgpu_gfx940::s31, output_vec_len ); + case 32: return makeRegisterExpression(amdgpu_gfx940::s32, output_vec_len ); + case 33: return makeRegisterExpression(amdgpu_gfx940::s33, output_vec_len ); + case 34: return makeRegisterExpression(amdgpu_gfx940::s34, output_vec_len ); + case 35: return makeRegisterExpression(amdgpu_gfx940::s35, output_vec_len ); + case 36: return makeRegisterExpression(amdgpu_gfx940::s36, output_vec_len ); + case 37: return makeRegisterExpression(amdgpu_gfx940::s37, output_vec_len ); + case 38: return makeRegisterExpression(amdgpu_gfx940::s38, output_vec_len ); + case 39: return makeRegisterExpression(amdgpu_gfx940::s39, output_vec_len ); + case 40: return makeRegisterExpression(amdgpu_gfx940::s40, output_vec_len ); + case 41: return makeRegisterExpression(amdgpu_gfx940::s41, output_vec_len ); + case 42: return makeRegisterExpression(amdgpu_gfx940::s42, output_vec_len ); + case 43: return makeRegisterExpression(amdgpu_gfx940::s43, output_vec_len ); + case 44: return makeRegisterExpression(amdgpu_gfx940::s44, output_vec_len ); + case 45: return makeRegisterExpression(amdgpu_gfx940::s45, output_vec_len ); + case 46: return makeRegisterExpression(amdgpu_gfx940::s46, output_vec_len ); + case 47: return makeRegisterExpression(amdgpu_gfx940::s47, output_vec_len ); + case 48: return makeRegisterExpression(amdgpu_gfx940::s48, output_vec_len ); + case 49: return makeRegisterExpression(amdgpu_gfx940::s49, output_vec_len ); + case 50: return makeRegisterExpression(amdgpu_gfx940::s50, output_vec_len ); + case 51: return makeRegisterExpression(amdgpu_gfx940::s51, output_vec_len ); + case 52: return makeRegisterExpression(amdgpu_gfx940::s52, output_vec_len ); + case 53: return makeRegisterExpression(amdgpu_gfx940::s53, output_vec_len ); + case 54: return makeRegisterExpression(amdgpu_gfx940::s54, output_vec_len ); + case 55: return makeRegisterExpression(amdgpu_gfx940::s55, output_vec_len ); + case 56: return makeRegisterExpression(amdgpu_gfx940::s56, output_vec_len ); + case 57: return makeRegisterExpression(amdgpu_gfx940::s57, output_vec_len ); + case 58: return makeRegisterExpression(amdgpu_gfx940::s58, output_vec_len ); + case 59: return makeRegisterExpression(amdgpu_gfx940::s59, output_vec_len ); + case 60: return makeRegisterExpression(amdgpu_gfx940::s60, output_vec_len ); + case 61: return makeRegisterExpression(amdgpu_gfx940::s61, output_vec_len ); + case 62: return makeRegisterExpression(amdgpu_gfx940::s62, output_vec_len ); + case 63: return makeRegisterExpression(amdgpu_gfx940::s63, output_vec_len ); + case 64: return makeRegisterExpression(amdgpu_gfx940::s64, output_vec_len ); + case 65: return makeRegisterExpression(amdgpu_gfx940::s65, output_vec_len ); + case 66: return makeRegisterExpression(amdgpu_gfx940::s66, output_vec_len ); + case 67: return makeRegisterExpression(amdgpu_gfx940::s67, output_vec_len ); + case 68: return makeRegisterExpression(amdgpu_gfx940::s68, output_vec_len ); + case 69: return makeRegisterExpression(amdgpu_gfx940::s69, output_vec_len ); + case 70: return makeRegisterExpression(amdgpu_gfx940::s70, output_vec_len ); + case 71: return makeRegisterExpression(amdgpu_gfx940::s71, output_vec_len ); + case 72: return makeRegisterExpression(amdgpu_gfx940::s72, output_vec_len ); + case 73: return makeRegisterExpression(amdgpu_gfx940::s73, output_vec_len ); + case 74: return makeRegisterExpression(amdgpu_gfx940::s74, output_vec_len ); + case 75: return makeRegisterExpression(amdgpu_gfx940::s75, output_vec_len ); + case 76: return makeRegisterExpression(amdgpu_gfx940::s76, output_vec_len ); + case 77: return makeRegisterExpression(amdgpu_gfx940::s77, output_vec_len ); + case 78: return makeRegisterExpression(amdgpu_gfx940::s78, output_vec_len ); + case 79: return makeRegisterExpression(amdgpu_gfx940::s79, output_vec_len ); + case 80: return makeRegisterExpression(amdgpu_gfx940::s80, output_vec_len ); + case 81: return makeRegisterExpression(amdgpu_gfx940::s81, output_vec_len ); + case 82: return makeRegisterExpression(amdgpu_gfx940::s82, output_vec_len ); + case 83: return makeRegisterExpression(amdgpu_gfx940::s83, output_vec_len ); + case 84: return makeRegisterExpression(amdgpu_gfx940::s84, output_vec_len ); + case 85: return makeRegisterExpression(amdgpu_gfx940::s85, output_vec_len ); + case 86: return makeRegisterExpression(amdgpu_gfx940::s86, output_vec_len ); + case 87: return makeRegisterExpression(amdgpu_gfx940::s87, output_vec_len ); + case 88: return makeRegisterExpression(amdgpu_gfx940::s88, output_vec_len ); + case 89: return makeRegisterExpression(amdgpu_gfx940::s89, output_vec_len ); + case 90: return makeRegisterExpression(amdgpu_gfx940::s90, output_vec_len ); + case 91: return makeRegisterExpression(amdgpu_gfx940::s91, output_vec_len ); + case 92: return makeRegisterExpression(amdgpu_gfx940::s92, output_vec_len ); + case 93: return makeRegisterExpression(amdgpu_gfx940::s93, output_vec_len ); + case 94: return makeRegisterExpression(amdgpu_gfx940::s94, output_vec_len ); + case 95: return makeRegisterExpression(amdgpu_gfx940::s95, output_vec_len ); + case 96: return makeRegisterExpression(amdgpu_gfx940::s96, output_vec_len ); + case 97: return makeRegisterExpression(amdgpu_gfx940::s97, output_vec_len ); + case 98: return makeRegisterExpression(amdgpu_gfx940::s98, output_vec_len ); + case 99: return makeRegisterExpression(amdgpu_gfx940::s99, output_vec_len ); + case 100: return makeRegisterExpression(amdgpu_gfx940::s100, output_vec_len ); + case 101: return makeRegisterExpression(amdgpu_gfx940::s101, output_vec_len ); + case 104: return makeRegisterExpression(amdgpu_gfx940::xnack_mask_lo, output_vec_len ); + case 105: return makeRegisterExpression(amdgpu_gfx940::xnack_mask_hi, output_vec_len ); + case 102: return makeRegisterExpression(amdgpu_gfx940::flat_scratch_lo, output_vec_len ); + case 103: return makeRegisterExpression(amdgpu_gfx940::flat_scratch_hi, output_vec_len ); + case 108: return makeRegisterExpression(amdgpu_gfx940::ttmp0, output_vec_len ); + case 109: return makeRegisterExpression(amdgpu_gfx940::ttmp1, output_vec_len ); + case 110: return makeRegisterExpression(amdgpu_gfx940::ttmp2, output_vec_len ); + case 111: return makeRegisterExpression(amdgpu_gfx940::ttmp3, output_vec_len ); + case 112: return makeRegisterExpression(amdgpu_gfx940::ttmp4, output_vec_len ); + case 113: return makeRegisterExpression(amdgpu_gfx940::ttmp5, output_vec_len ); + case 114: return makeRegisterExpression(amdgpu_gfx940::ttmp6, output_vec_len ); + case 115: return makeRegisterExpression(amdgpu_gfx940::ttmp7, output_vec_len ); + case 116: return makeRegisterExpression(amdgpu_gfx940::ttmp8, output_vec_len ); + case 117: return makeRegisterExpression(amdgpu_gfx940::ttmp9, output_vec_len ); + case 118: return makeRegisterExpression(amdgpu_gfx940::ttmp10, output_vec_len ); + case 119: return makeRegisterExpression(amdgpu_gfx940::ttmp11, output_vec_len ); + case 120: return makeRegisterExpression(amdgpu_gfx940::ttmp12, output_vec_len ); + case 121: return makeRegisterExpression(amdgpu_gfx940::ttmp13, output_vec_len ); + case 122: return makeRegisterExpression(amdgpu_gfx940::ttmp14, output_vec_len ); + case 123: return makeRegisterExpression(amdgpu_gfx940::ttmp15, output_vec_len ); + case 106: return makeRegisterExpression(amdgpu_gfx940::vcc_lo, output_vec_len ); + case 107: return makeRegisterExpression(amdgpu_gfx940::vcc_hi, output_vec_len ); + case 124: return makeRegisterExpression(amdgpu_gfx940::m0, output_vec_len ); + case 126: return makeRegisterExpression(amdgpu_gfx940::exec_lo, output_vec_len ); + case 127: return makeRegisterExpression(amdgpu_gfx940::exec_hi, output_vec_len ); + default: return makeRegisterExpression(amdgpu_gfx940::invalid); + } + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx940::decodeOPR_SDST_EXEC(uint64_t input, uint32_t output_vec_len) + { + switch (input) { + case 126: return makeRegisterExpression(amdgpu_gfx940::exec_lo, output_vec_len ); + case 127: return makeRegisterExpression(amdgpu_gfx940::exec_hi, output_vec_len ); + default: return makeRegisterExpression(amdgpu_gfx940::invalid); + } + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx940::decodeOPR_SDST_M0(uint64_t input, uint32_t output_vec_len) + { + switch (input) { + case 124: return makeRegisterExpression(amdgpu_gfx940::m0, output_vec_len ); + default: return makeRegisterExpression(amdgpu_gfx940::invalid); + } + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx940::decodeOPR_SRC(uint64_t input, uint32_t output_vec_len) + { + switch (input) { + case 0: return makeRegisterExpression(amdgpu_gfx940::s0, output_vec_len ); + case 1: return makeRegisterExpression(amdgpu_gfx940::s1, output_vec_len ); + case 2: return makeRegisterExpression(amdgpu_gfx940::s2, output_vec_len ); + case 3: return makeRegisterExpression(amdgpu_gfx940::s3, output_vec_len ); + case 4: return makeRegisterExpression(amdgpu_gfx940::s4, output_vec_len ); + case 5: return makeRegisterExpression(amdgpu_gfx940::s5, output_vec_len ); + case 6: return makeRegisterExpression(amdgpu_gfx940::s6, output_vec_len ); + case 7: return makeRegisterExpression(amdgpu_gfx940::s7, output_vec_len ); + case 8: return makeRegisterExpression(amdgpu_gfx940::s8, output_vec_len ); + case 9: return makeRegisterExpression(amdgpu_gfx940::s9, output_vec_len ); + case 10: return makeRegisterExpression(amdgpu_gfx940::s10, output_vec_len ); + case 11: return makeRegisterExpression(amdgpu_gfx940::s11, output_vec_len ); + case 12: return makeRegisterExpression(amdgpu_gfx940::s12, output_vec_len ); + case 13: return makeRegisterExpression(amdgpu_gfx940::s13, output_vec_len ); + case 14: return makeRegisterExpression(amdgpu_gfx940::s14, output_vec_len ); + case 15: return makeRegisterExpression(amdgpu_gfx940::s15, output_vec_len ); + case 16: return makeRegisterExpression(amdgpu_gfx940::s16, output_vec_len ); + case 17: return makeRegisterExpression(amdgpu_gfx940::s17, output_vec_len ); + case 18: return makeRegisterExpression(amdgpu_gfx940::s18, output_vec_len ); + case 19: return makeRegisterExpression(amdgpu_gfx940::s19, output_vec_len ); + case 20: return makeRegisterExpression(amdgpu_gfx940::s20, output_vec_len ); + case 21: return makeRegisterExpression(amdgpu_gfx940::s21, output_vec_len ); + case 22: return makeRegisterExpression(amdgpu_gfx940::s22, output_vec_len ); + case 23: return makeRegisterExpression(amdgpu_gfx940::s23, output_vec_len ); + case 24: return makeRegisterExpression(amdgpu_gfx940::s24, output_vec_len ); + case 25: return makeRegisterExpression(amdgpu_gfx940::s25, output_vec_len ); + case 26: return makeRegisterExpression(amdgpu_gfx940::s26, output_vec_len ); + case 27: return makeRegisterExpression(amdgpu_gfx940::s27, output_vec_len ); + case 28: return makeRegisterExpression(amdgpu_gfx940::s28, output_vec_len ); + case 29: return makeRegisterExpression(amdgpu_gfx940::s29, output_vec_len ); + case 30: return makeRegisterExpression(amdgpu_gfx940::s30, output_vec_len ); + case 31: return makeRegisterExpression(amdgpu_gfx940::s31, output_vec_len ); + case 32: return makeRegisterExpression(amdgpu_gfx940::s32, output_vec_len ); + case 33: return makeRegisterExpression(amdgpu_gfx940::s33, output_vec_len ); + case 34: return makeRegisterExpression(amdgpu_gfx940::s34, output_vec_len ); + case 35: return makeRegisterExpression(amdgpu_gfx940::s35, output_vec_len ); + case 36: return makeRegisterExpression(amdgpu_gfx940::s36, output_vec_len ); + case 37: return makeRegisterExpression(amdgpu_gfx940::s37, output_vec_len ); + case 38: return makeRegisterExpression(amdgpu_gfx940::s38, output_vec_len ); + case 39: return makeRegisterExpression(amdgpu_gfx940::s39, output_vec_len ); + case 40: return makeRegisterExpression(amdgpu_gfx940::s40, output_vec_len ); + case 41: return makeRegisterExpression(amdgpu_gfx940::s41, output_vec_len ); + case 42: return makeRegisterExpression(amdgpu_gfx940::s42, output_vec_len ); + case 43: return makeRegisterExpression(amdgpu_gfx940::s43, output_vec_len ); + case 44: return makeRegisterExpression(amdgpu_gfx940::s44, output_vec_len ); + case 45: return makeRegisterExpression(amdgpu_gfx940::s45, output_vec_len ); + case 46: return makeRegisterExpression(amdgpu_gfx940::s46, output_vec_len ); + case 47: return makeRegisterExpression(amdgpu_gfx940::s47, output_vec_len ); + case 48: return makeRegisterExpression(amdgpu_gfx940::s48, output_vec_len ); + case 49: return makeRegisterExpression(amdgpu_gfx940::s49, output_vec_len ); + case 50: return makeRegisterExpression(amdgpu_gfx940::s50, output_vec_len ); + case 51: return makeRegisterExpression(amdgpu_gfx940::s51, output_vec_len ); + case 52: return makeRegisterExpression(amdgpu_gfx940::s52, output_vec_len ); + case 53: return makeRegisterExpression(amdgpu_gfx940::s53, output_vec_len ); + case 54: return makeRegisterExpression(amdgpu_gfx940::s54, output_vec_len ); + case 55: return makeRegisterExpression(amdgpu_gfx940::s55, output_vec_len ); + case 56: return makeRegisterExpression(amdgpu_gfx940::s56, output_vec_len ); + case 57: return makeRegisterExpression(amdgpu_gfx940::s57, output_vec_len ); + case 58: return makeRegisterExpression(amdgpu_gfx940::s58, output_vec_len ); + case 59: return makeRegisterExpression(amdgpu_gfx940::s59, output_vec_len ); + case 60: return makeRegisterExpression(amdgpu_gfx940::s60, output_vec_len ); + case 61: return makeRegisterExpression(amdgpu_gfx940::s61, output_vec_len ); + case 62: return makeRegisterExpression(amdgpu_gfx940::s62, output_vec_len ); + case 63: return makeRegisterExpression(amdgpu_gfx940::s63, output_vec_len ); + case 64: return makeRegisterExpression(amdgpu_gfx940::s64, output_vec_len ); + case 65: return makeRegisterExpression(amdgpu_gfx940::s65, output_vec_len ); + case 66: return makeRegisterExpression(amdgpu_gfx940::s66, output_vec_len ); + case 67: return makeRegisterExpression(amdgpu_gfx940::s67, output_vec_len ); + case 68: return makeRegisterExpression(amdgpu_gfx940::s68, output_vec_len ); + case 69: return makeRegisterExpression(amdgpu_gfx940::s69, output_vec_len ); + case 70: return makeRegisterExpression(amdgpu_gfx940::s70, output_vec_len ); + case 71: return makeRegisterExpression(amdgpu_gfx940::s71, output_vec_len ); + case 72: return makeRegisterExpression(amdgpu_gfx940::s72, output_vec_len ); + case 73: return makeRegisterExpression(amdgpu_gfx940::s73, output_vec_len ); + case 74: return makeRegisterExpression(amdgpu_gfx940::s74, output_vec_len ); + case 75: return makeRegisterExpression(amdgpu_gfx940::s75, output_vec_len ); + case 76: return makeRegisterExpression(amdgpu_gfx940::s76, output_vec_len ); + case 77: return makeRegisterExpression(amdgpu_gfx940::s77, output_vec_len ); + case 78: return makeRegisterExpression(amdgpu_gfx940::s78, output_vec_len ); + case 79: return makeRegisterExpression(amdgpu_gfx940::s79, output_vec_len ); + case 80: return makeRegisterExpression(amdgpu_gfx940::s80, output_vec_len ); + case 81: return makeRegisterExpression(amdgpu_gfx940::s81, output_vec_len ); + case 82: return makeRegisterExpression(amdgpu_gfx940::s82, output_vec_len ); + case 83: return makeRegisterExpression(amdgpu_gfx940::s83, output_vec_len ); + case 84: return makeRegisterExpression(amdgpu_gfx940::s84, output_vec_len ); + case 85: return makeRegisterExpression(amdgpu_gfx940::s85, output_vec_len ); + case 86: return makeRegisterExpression(amdgpu_gfx940::s86, output_vec_len ); + case 87: return makeRegisterExpression(amdgpu_gfx940::s87, output_vec_len ); + case 88: return makeRegisterExpression(amdgpu_gfx940::s88, output_vec_len ); + case 89: return makeRegisterExpression(amdgpu_gfx940::s89, output_vec_len ); + case 90: return makeRegisterExpression(amdgpu_gfx940::s90, output_vec_len ); + case 91: return makeRegisterExpression(amdgpu_gfx940::s91, output_vec_len ); + case 92: return makeRegisterExpression(amdgpu_gfx940::s92, output_vec_len ); + case 93: return makeRegisterExpression(amdgpu_gfx940::s93, output_vec_len ); + case 94: return makeRegisterExpression(amdgpu_gfx940::s94, output_vec_len ); + case 95: return makeRegisterExpression(amdgpu_gfx940::s95, output_vec_len ); + case 96: return makeRegisterExpression(amdgpu_gfx940::s96, output_vec_len ); + case 97: return makeRegisterExpression(amdgpu_gfx940::s97, output_vec_len ); + case 98: return makeRegisterExpression(amdgpu_gfx940::s98, output_vec_len ); + case 99: return makeRegisterExpression(amdgpu_gfx940::s99, output_vec_len ); + case 100: return makeRegisterExpression(amdgpu_gfx940::s100, output_vec_len ); + case 101: return makeRegisterExpression(amdgpu_gfx940::s101, output_vec_len ); + case 104: return makeRegisterExpression(amdgpu_gfx940::xnack_mask_lo, output_vec_len ); + case 105: return makeRegisterExpression(amdgpu_gfx940::xnack_mask_hi, output_vec_len ); + case 102: return makeRegisterExpression(amdgpu_gfx940::flat_scratch_lo, output_vec_len ); + case 103: return makeRegisterExpression(amdgpu_gfx940::flat_scratch_hi, output_vec_len ); + case 108: return makeRegisterExpression(amdgpu_gfx940::ttmp0, output_vec_len ); + case 109: return makeRegisterExpression(amdgpu_gfx940::ttmp1, output_vec_len ); + case 110: return makeRegisterExpression(amdgpu_gfx940::ttmp2, output_vec_len ); + case 111: return makeRegisterExpression(amdgpu_gfx940::ttmp3, output_vec_len ); + case 112: return makeRegisterExpression(amdgpu_gfx940::ttmp4, output_vec_len ); + case 113: return makeRegisterExpression(amdgpu_gfx940::ttmp5, output_vec_len ); + case 114: return makeRegisterExpression(amdgpu_gfx940::ttmp6, output_vec_len ); + case 115: return makeRegisterExpression(amdgpu_gfx940::ttmp7, output_vec_len ); + case 116: return makeRegisterExpression(amdgpu_gfx940::ttmp8, output_vec_len ); + case 117: return makeRegisterExpression(amdgpu_gfx940::ttmp9, output_vec_len ); + case 118: return makeRegisterExpression(amdgpu_gfx940::ttmp10, output_vec_len ); + case 119: return makeRegisterExpression(amdgpu_gfx940::ttmp11, output_vec_len ); + case 120: return makeRegisterExpression(amdgpu_gfx940::ttmp12, output_vec_len ); + case 121: return makeRegisterExpression(amdgpu_gfx940::ttmp13, output_vec_len ); + case 122: return makeRegisterExpression(amdgpu_gfx940::ttmp14, output_vec_len ); + case 123: return makeRegisterExpression(amdgpu_gfx940::ttmp15, output_vec_len ); + case 106: return makeRegisterExpression(amdgpu_gfx940::vcc_lo, output_vec_len ); + case 107: return makeRegisterExpression(amdgpu_gfx940::vcc_hi, output_vec_len ); + case 124: return makeRegisterExpression(amdgpu_gfx940::m0, output_vec_len ); + case 126: return makeRegisterExpression(amdgpu_gfx940::exec_lo, output_vec_len ); + case 127: return makeRegisterExpression(amdgpu_gfx940::exec_hi, output_vec_len ); + case 128: return Immediate::makeImmediate(Result(u32, 0)); + case 129: return Immediate::makeImmediate(Result(u32, 1)); + case 130: return Immediate::makeImmediate(Result(u32, 2)); + case 131: return Immediate::makeImmediate(Result(u32, 3)); + case 132: return Immediate::makeImmediate(Result(u32, 4)); + case 133: return Immediate::makeImmediate(Result(u32, 5)); + case 134: return Immediate::makeImmediate(Result(u32, 6)); + case 135: return Immediate::makeImmediate(Result(u32, 7)); + case 136: return Immediate::makeImmediate(Result(u32, 8)); + case 137: return Immediate::makeImmediate(Result(u32, 9)); + case 138: return Immediate::makeImmediate(Result(u32, 10)); + case 139: return Immediate::makeImmediate(Result(u32, 11)); + case 140: return Immediate::makeImmediate(Result(u32, 12)); + case 141: return Immediate::makeImmediate(Result(u32, 13)); + case 142: return Immediate::makeImmediate(Result(u32, 14)); + case 143: return Immediate::makeImmediate(Result(u32, 15)); + case 144: return Immediate::makeImmediate(Result(u32, 16)); + case 145: return Immediate::makeImmediate(Result(u32, 17)); + case 146: return Immediate::makeImmediate(Result(u32, 18)); + case 147: return Immediate::makeImmediate(Result(u32, 19)); + case 148: return Immediate::makeImmediate(Result(u32, 20)); + case 149: return Immediate::makeImmediate(Result(u32, 21)); + case 150: return Immediate::makeImmediate(Result(u32, 22)); + case 151: return Immediate::makeImmediate(Result(u32, 23)); + case 152: return Immediate::makeImmediate(Result(u32, 24)); + case 153: return Immediate::makeImmediate(Result(u32, 25)); + case 154: return Immediate::makeImmediate(Result(u32, 26)); + case 155: return Immediate::makeImmediate(Result(u32, 27)); + case 156: return Immediate::makeImmediate(Result(u32, 28)); + case 157: return Immediate::makeImmediate(Result(u32, 29)); + case 158: return Immediate::makeImmediate(Result(u32, 30)); + case 159: return Immediate::makeImmediate(Result(u32, 31)); + case 160: return Immediate::makeImmediate(Result(u32, 32)); + case 161: return Immediate::makeImmediate(Result(u32, 33)); + case 162: return Immediate::makeImmediate(Result(u32, 34)); + case 163: return Immediate::makeImmediate(Result(u32, 35)); + case 164: return Immediate::makeImmediate(Result(u32, 36)); + case 165: return Immediate::makeImmediate(Result(u32, 37)); + case 166: return Immediate::makeImmediate(Result(u32, 38)); + case 167: return Immediate::makeImmediate(Result(u32, 39)); + case 168: return Immediate::makeImmediate(Result(u32, 40)); + case 169: return Immediate::makeImmediate(Result(u32, 41)); + case 170: return Immediate::makeImmediate(Result(u32, 42)); + case 171: return Immediate::makeImmediate(Result(u32, 43)); + case 172: return Immediate::makeImmediate(Result(u32, 44)); + case 173: return Immediate::makeImmediate(Result(u32, 45)); + case 174: return Immediate::makeImmediate(Result(u32, 46)); + case 175: return Immediate::makeImmediate(Result(u32, 47)); + case 176: return Immediate::makeImmediate(Result(u32, 48)); + case 177: return Immediate::makeImmediate(Result(u32, 49)); + case 178: return Immediate::makeImmediate(Result(u32, 50)); + case 179: return Immediate::makeImmediate(Result(u32, 51)); + case 180: return Immediate::makeImmediate(Result(u32, 52)); + case 181: return Immediate::makeImmediate(Result(u32, 53)); + case 182: return Immediate::makeImmediate(Result(u32, 54)); + case 183: return Immediate::makeImmediate(Result(u32, 55)); + case 184: return Immediate::makeImmediate(Result(u32, 56)); + case 185: return Immediate::makeImmediate(Result(u32, 57)); + case 186: return Immediate::makeImmediate(Result(u32, 58)); + case 187: return Immediate::makeImmediate(Result(u32, 59)); + case 188: return Immediate::makeImmediate(Result(u32, 60)); + case 189: return Immediate::makeImmediate(Result(u32, 61)); + case 190: return Immediate::makeImmediate(Result(u32, 62)); + case 191: return Immediate::makeImmediate(Result(u32, 63)); + case 192: return Immediate::makeImmediate(Result(u32, 64)); + case 193: return Immediate::makeImmediate(Result(u32, -1)); + case 194: return Immediate::makeImmediate(Result(u32, -2)); + case 195: return Immediate::makeImmediate(Result(u32, -3)); + case 196: return Immediate::makeImmediate(Result(u32, -4)); + case 197: return Immediate::makeImmediate(Result(u32, -5)); + case 198: return Immediate::makeImmediate(Result(u32, -6)); + case 199: return Immediate::makeImmediate(Result(u32, -7)); + case 200: return Immediate::makeImmediate(Result(u32, -8)); + case 201: return Immediate::makeImmediate(Result(u32, -9)); + case 202: return Immediate::makeImmediate(Result(u32, -10)); + case 203: return Immediate::makeImmediate(Result(u32, -11)); + case 204: return Immediate::makeImmediate(Result(u32, -12)); + case 205: return Immediate::makeImmediate(Result(u32, -13)); + case 206: return Immediate::makeImmediate(Result(u32, -14)); + case 207: return Immediate::makeImmediate(Result(u32, -15)); + case 208: return Immediate::makeImmediate(Result(u32, -16)); + case 240: return Immediate::makeImmediate(Result(sp_float, 0.5)); + case 241: return Immediate::makeImmediate(Result(sp_float, -0.5)); + case 242: return Immediate::makeImmediate(Result(sp_float, 1.0)); + case 243: return Immediate::makeImmediate(Result(sp_float, -1.0)); + case 244: return Immediate::makeImmediate(Result(sp_float, 2.0)); + case 245: return Immediate::makeImmediate(Result(sp_float, -2.0)); + case 246: return Immediate::makeImmediate(Result(sp_float, 4.0)); + case 247: return Immediate::makeImmediate(Result(sp_float, -4.0)); + case 248: return Immediate::makeImmediate(Result(sp_float, 0.15915494)); + case 251: return makeRegisterExpression(amdgpu_gfx940::src_vccz, output_vec_len ); + case 252: return makeRegisterExpression(amdgpu_gfx940::src_execz, output_vec_len ); + case 253: return makeRegisterExpression(amdgpu_gfx940::src_scc, output_vec_len ); + case 235: return makeRegisterExpression(amdgpu_gfx940::src_shared_base, output_vec_len ); + case 236: return makeRegisterExpression(amdgpu_gfx940::src_shared_limit, output_vec_len ); + case 237: return makeRegisterExpression(amdgpu_gfx940::src_private_base, output_vec_len ); + case 238: return makeRegisterExpression(amdgpu_gfx940::src_private_limit, output_vec_len ); + case 239: return makeRegisterExpression(amdgpu_gfx940::src_pops_exiting_wave_id, output_vec_len ); + case 256: return makeRegisterExpression(amdgpu_gfx940::v0, output_vec_len ); + case 257: return makeRegisterExpression(amdgpu_gfx940::v1, output_vec_len ); + case 258: return makeRegisterExpression(amdgpu_gfx940::v2, output_vec_len ); + case 259: return makeRegisterExpression(amdgpu_gfx940::v3, output_vec_len ); + case 260: return makeRegisterExpression(amdgpu_gfx940::v4, output_vec_len ); + case 261: return makeRegisterExpression(amdgpu_gfx940::v5, output_vec_len ); + case 262: return makeRegisterExpression(amdgpu_gfx940::v6, output_vec_len ); + case 263: return makeRegisterExpression(amdgpu_gfx940::v7, output_vec_len ); + case 264: return makeRegisterExpression(amdgpu_gfx940::v8, output_vec_len ); + case 265: return makeRegisterExpression(amdgpu_gfx940::v9, output_vec_len ); + case 266: return makeRegisterExpression(amdgpu_gfx940::v10, output_vec_len ); + case 267: return makeRegisterExpression(amdgpu_gfx940::v11, output_vec_len ); + case 268: return makeRegisterExpression(amdgpu_gfx940::v12, output_vec_len ); + case 269: return makeRegisterExpression(amdgpu_gfx940::v13, output_vec_len ); + case 270: return makeRegisterExpression(amdgpu_gfx940::v14, output_vec_len ); + case 271: return makeRegisterExpression(amdgpu_gfx940::v15, output_vec_len ); + case 272: return makeRegisterExpression(amdgpu_gfx940::v16, output_vec_len ); + case 273: return makeRegisterExpression(amdgpu_gfx940::v17, output_vec_len ); + case 274: return makeRegisterExpression(amdgpu_gfx940::v18, output_vec_len ); + case 275: return makeRegisterExpression(amdgpu_gfx940::v19, output_vec_len ); + case 276: return makeRegisterExpression(amdgpu_gfx940::v20, output_vec_len ); + case 277: return makeRegisterExpression(amdgpu_gfx940::v21, output_vec_len ); + case 278: return makeRegisterExpression(amdgpu_gfx940::v22, output_vec_len ); + case 279: return makeRegisterExpression(amdgpu_gfx940::v23, output_vec_len ); + case 280: return makeRegisterExpression(amdgpu_gfx940::v24, output_vec_len ); + case 281: return makeRegisterExpression(amdgpu_gfx940::v25, output_vec_len ); + case 282: return makeRegisterExpression(amdgpu_gfx940::v26, output_vec_len ); + case 283: return makeRegisterExpression(amdgpu_gfx940::v27, output_vec_len ); + case 284: return makeRegisterExpression(amdgpu_gfx940::v28, output_vec_len ); + case 285: return makeRegisterExpression(amdgpu_gfx940::v29, output_vec_len ); + case 286: return makeRegisterExpression(amdgpu_gfx940::v30, output_vec_len ); + case 287: return makeRegisterExpression(amdgpu_gfx940::v31, output_vec_len ); + case 288: return makeRegisterExpression(amdgpu_gfx940::v32, output_vec_len ); + case 289: return makeRegisterExpression(amdgpu_gfx940::v33, output_vec_len ); + case 290: return makeRegisterExpression(amdgpu_gfx940::v34, output_vec_len ); + case 291: return makeRegisterExpression(amdgpu_gfx940::v35, output_vec_len ); + case 292: return makeRegisterExpression(amdgpu_gfx940::v36, output_vec_len ); + case 293: return makeRegisterExpression(amdgpu_gfx940::v37, output_vec_len ); + case 294: return makeRegisterExpression(amdgpu_gfx940::v38, output_vec_len ); + case 295: return makeRegisterExpression(amdgpu_gfx940::v39, output_vec_len ); + case 296: return makeRegisterExpression(amdgpu_gfx940::v40, output_vec_len ); + case 297: return makeRegisterExpression(amdgpu_gfx940::v41, output_vec_len ); + case 298: return makeRegisterExpression(amdgpu_gfx940::v42, output_vec_len ); + case 299: return makeRegisterExpression(amdgpu_gfx940::v43, output_vec_len ); + case 300: return makeRegisterExpression(amdgpu_gfx940::v44, output_vec_len ); + case 301: return makeRegisterExpression(amdgpu_gfx940::v45, output_vec_len ); + case 302: return makeRegisterExpression(amdgpu_gfx940::v46, output_vec_len ); + case 303: return makeRegisterExpression(amdgpu_gfx940::v47, output_vec_len ); + case 304: return makeRegisterExpression(amdgpu_gfx940::v48, output_vec_len ); + case 305: return makeRegisterExpression(amdgpu_gfx940::v49, output_vec_len ); + case 306: return makeRegisterExpression(amdgpu_gfx940::v50, output_vec_len ); + case 307: return makeRegisterExpression(amdgpu_gfx940::v51, output_vec_len ); + case 308: return makeRegisterExpression(amdgpu_gfx940::v52, output_vec_len ); + case 309: return makeRegisterExpression(amdgpu_gfx940::v53, output_vec_len ); + case 310: return makeRegisterExpression(amdgpu_gfx940::v54, output_vec_len ); + case 311: return makeRegisterExpression(amdgpu_gfx940::v55, output_vec_len ); + case 312: return makeRegisterExpression(amdgpu_gfx940::v56, output_vec_len ); + case 313: return makeRegisterExpression(amdgpu_gfx940::v57, output_vec_len ); + case 314: return makeRegisterExpression(amdgpu_gfx940::v58, output_vec_len ); + case 315: return makeRegisterExpression(amdgpu_gfx940::v59, output_vec_len ); + case 316: return makeRegisterExpression(amdgpu_gfx940::v60, output_vec_len ); + case 317: return makeRegisterExpression(amdgpu_gfx940::v61, output_vec_len ); + case 318: return makeRegisterExpression(amdgpu_gfx940::v62, output_vec_len ); + case 319: return makeRegisterExpression(amdgpu_gfx940::v63, output_vec_len ); + case 320: return makeRegisterExpression(amdgpu_gfx940::v64, output_vec_len ); + case 321: return makeRegisterExpression(amdgpu_gfx940::v65, output_vec_len ); + case 322: return makeRegisterExpression(amdgpu_gfx940::v66, output_vec_len ); + case 323: return makeRegisterExpression(amdgpu_gfx940::v67, output_vec_len ); + case 324: return makeRegisterExpression(amdgpu_gfx940::v68, output_vec_len ); + case 325: return makeRegisterExpression(amdgpu_gfx940::v69, output_vec_len ); + case 326: return makeRegisterExpression(amdgpu_gfx940::v70, output_vec_len ); + case 327: return makeRegisterExpression(amdgpu_gfx940::v71, output_vec_len ); + case 328: return makeRegisterExpression(amdgpu_gfx940::v72, output_vec_len ); + case 329: return makeRegisterExpression(amdgpu_gfx940::v73, output_vec_len ); + case 330: return makeRegisterExpression(amdgpu_gfx940::v74, output_vec_len ); + case 331: return makeRegisterExpression(amdgpu_gfx940::v75, output_vec_len ); + case 332: return makeRegisterExpression(amdgpu_gfx940::v76, output_vec_len ); + case 333: return makeRegisterExpression(amdgpu_gfx940::v77, output_vec_len ); + case 334: return makeRegisterExpression(amdgpu_gfx940::v78, output_vec_len ); + case 335: return makeRegisterExpression(amdgpu_gfx940::v79, output_vec_len ); + case 336: return makeRegisterExpression(amdgpu_gfx940::v80, output_vec_len ); + case 337: return makeRegisterExpression(amdgpu_gfx940::v81, output_vec_len ); + case 338: return makeRegisterExpression(amdgpu_gfx940::v82, output_vec_len ); + case 339: return makeRegisterExpression(amdgpu_gfx940::v83, output_vec_len ); + case 340: return makeRegisterExpression(amdgpu_gfx940::v84, output_vec_len ); + case 341: return makeRegisterExpression(amdgpu_gfx940::v85, output_vec_len ); + case 342: return makeRegisterExpression(amdgpu_gfx940::v86, output_vec_len ); + case 343: return makeRegisterExpression(amdgpu_gfx940::v87, output_vec_len ); + case 344: return makeRegisterExpression(amdgpu_gfx940::v88, output_vec_len ); + case 345: return makeRegisterExpression(amdgpu_gfx940::v89, output_vec_len ); + case 346: return makeRegisterExpression(amdgpu_gfx940::v90, output_vec_len ); + case 347: return makeRegisterExpression(amdgpu_gfx940::v91, output_vec_len ); + case 348: return makeRegisterExpression(amdgpu_gfx940::v92, output_vec_len ); + case 349: return makeRegisterExpression(amdgpu_gfx940::v93, output_vec_len ); + case 350: return makeRegisterExpression(amdgpu_gfx940::v94, output_vec_len ); + case 351: return makeRegisterExpression(amdgpu_gfx940::v95, output_vec_len ); + case 352: return makeRegisterExpression(amdgpu_gfx940::v96, output_vec_len ); + case 353: return makeRegisterExpression(amdgpu_gfx940::v97, output_vec_len ); + case 354: return makeRegisterExpression(amdgpu_gfx940::v98, output_vec_len ); + case 355: return makeRegisterExpression(amdgpu_gfx940::v99, output_vec_len ); + case 356: return makeRegisterExpression(amdgpu_gfx940::v100, output_vec_len ); + case 357: return makeRegisterExpression(amdgpu_gfx940::v101, output_vec_len ); + case 358: return makeRegisterExpression(amdgpu_gfx940::v102, output_vec_len ); + case 359: return makeRegisterExpression(amdgpu_gfx940::v103, output_vec_len ); + case 360: return makeRegisterExpression(amdgpu_gfx940::v104, output_vec_len ); + case 361: return makeRegisterExpression(amdgpu_gfx940::v105, output_vec_len ); + case 362: return makeRegisterExpression(amdgpu_gfx940::v106, output_vec_len ); + case 363: return makeRegisterExpression(amdgpu_gfx940::v107, output_vec_len ); + case 364: return makeRegisterExpression(amdgpu_gfx940::v108, output_vec_len ); + case 365: return makeRegisterExpression(amdgpu_gfx940::v109, output_vec_len ); + case 366: return makeRegisterExpression(amdgpu_gfx940::v110, output_vec_len ); + case 367: return makeRegisterExpression(amdgpu_gfx940::v111, output_vec_len ); + case 368: return makeRegisterExpression(amdgpu_gfx940::v112, output_vec_len ); + case 369: return makeRegisterExpression(amdgpu_gfx940::v113, output_vec_len ); + case 370: return makeRegisterExpression(amdgpu_gfx940::v114, output_vec_len ); + case 371: return makeRegisterExpression(amdgpu_gfx940::v115, output_vec_len ); + case 372: return makeRegisterExpression(amdgpu_gfx940::v116, output_vec_len ); + case 373: return makeRegisterExpression(amdgpu_gfx940::v117, output_vec_len ); + case 374: return makeRegisterExpression(amdgpu_gfx940::v118, output_vec_len ); + case 375: return makeRegisterExpression(amdgpu_gfx940::v119, output_vec_len ); + case 376: return makeRegisterExpression(amdgpu_gfx940::v120, output_vec_len ); + case 377: return makeRegisterExpression(amdgpu_gfx940::v121, output_vec_len ); + case 378: return makeRegisterExpression(amdgpu_gfx940::v122, output_vec_len ); + case 379: return makeRegisterExpression(amdgpu_gfx940::v123, output_vec_len ); + case 380: return makeRegisterExpression(amdgpu_gfx940::v124, output_vec_len ); + case 381: return makeRegisterExpression(amdgpu_gfx940::v125, output_vec_len ); + case 382: return makeRegisterExpression(amdgpu_gfx940::v126, output_vec_len ); + case 383: return makeRegisterExpression(amdgpu_gfx940::v127, output_vec_len ); + case 384: return makeRegisterExpression(amdgpu_gfx940::v128, output_vec_len ); + case 385: return makeRegisterExpression(amdgpu_gfx940::v129, output_vec_len ); + case 386: return makeRegisterExpression(amdgpu_gfx940::v130, output_vec_len ); + case 387: return makeRegisterExpression(amdgpu_gfx940::v131, output_vec_len ); + case 388: return makeRegisterExpression(amdgpu_gfx940::v132, output_vec_len ); + case 389: return makeRegisterExpression(amdgpu_gfx940::v133, output_vec_len ); + case 390: return makeRegisterExpression(amdgpu_gfx940::v134, output_vec_len ); + case 391: return makeRegisterExpression(amdgpu_gfx940::v135, output_vec_len ); + case 392: return makeRegisterExpression(amdgpu_gfx940::v136, output_vec_len ); + case 393: return makeRegisterExpression(amdgpu_gfx940::v137, output_vec_len ); + case 394: return makeRegisterExpression(amdgpu_gfx940::v138, output_vec_len ); + case 395: return makeRegisterExpression(amdgpu_gfx940::v139, output_vec_len ); + case 396: return makeRegisterExpression(amdgpu_gfx940::v140, output_vec_len ); + case 397: return makeRegisterExpression(amdgpu_gfx940::v141, output_vec_len ); + case 398: return makeRegisterExpression(amdgpu_gfx940::v142, output_vec_len ); + case 399: return makeRegisterExpression(amdgpu_gfx940::v143, output_vec_len ); + case 400: return makeRegisterExpression(amdgpu_gfx940::v144, output_vec_len ); + case 401: return makeRegisterExpression(amdgpu_gfx940::v145, output_vec_len ); + case 402: return makeRegisterExpression(amdgpu_gfx940::v146, output_vec_len ); + case 403: return makeRegisterExpression(amdgpu_gfx940::v147, output_vec_len ); + case 404: return makeRegisterExpression(amdgpu_gfx940::v148, output_vec_len ); + case 405: return makeRegisterExpression(amdgpu_gfx940::v149, output_vec_len ); + case 406: return makeRegisterExpression(amdgpu_gfx940::v150, output_vec_len ); + case 407: return makeRegisterExpression(amdgpu_gfx940::v151, output_vec_len ); + case 408: return makeRegisterExpression(amdgpu_gfx940::v152, output_vec_len ); + case 409: return makeRegisterExpression(amdgpu_gfx940::v153, output_vec_len ); + case 410: return makeRegisterExpression(amdgpu_gfx940::v154, output_vec_len ); + case 411: return makeRegisterExpression(amdgpu_gfx940::v155, output_vec_len ); + case 412: return makeRegisterExpression(amdgpu_gfx940::v156, output_vec_len ); + case 413: return makeRegisterExpression(amdgpu_gfx940::v157, output_vec_len ); + case 414: return makeRegisterExpression(amdgpu_gfx940::v158, output_vec_len ); + case 415: return makeRegisterExpression(amdgpu_gfx940::v159, output_vec_len ); + case 416: return makeRegisterExpression(amdgpu_gfx940::v160, output_vec_len ); + case 417: return makeRegisterExpression(amdgpu_gfx940::v161, output_vec_len ); + case 418: return makeRegisterExpression(amdgpu_gfx940::v162, output_vec_len ); + case 419: return makeRegisterExpression(amdgpu_gfx940::v163, output_vec_len ); + case 420: return makeRegisterExpression(amdgpu_gfx940::v164, output_vec_len ); + case 421: return makeRegisterExpression(amdgpu_gfx940::v165, output_vec_len ); + case 422: return makeRegisterExpression(amdgpu_gfx940::v166, output_vec_len ); + case 423: return makeRegisterExpression(amdgpu_gfx940::v167, output_vec_len ); + case 424: return makeRegisterExpression(amdgpu_gfx940::v168, output_vec_len ); + case 425: return makeRegisterExpression(amdgpu_gfx940::v169, output_vec_len ); + case 426: return makeRegisterExpression(amdgpu_gfx940::v170, output_vec_len ); + case 427: return makeRegisterExpression(amdgpu_gfx940::v171, output_vec_len ); + case 428: return makeRegisterExpression(amdgpu_gfx940::v172, output_vec_len ); + case 429: return makeRegisterExpression(amdgpu_gfx940::v173, output_vec_len ); + case 430: return makeRegisterExpression(amdgpu_gfx940::v174, output_vec_len ); + case 431: return makeRegisterExpression(amdgpu_gfx940::v175, output_vec_len ); + case 432: return makeRegisterExpression(amdgpu_gfx940::v176, output_vec_len ); + case 433: return makeRegisterExpression(amdgpu_gfx940::v177, output_vec_len ); + case 434: return makeRegisterExpression(amdgpu_gfx940::v178, output_vec_len ); + case 435: return makeRegisterExpression(amdgpu_gfx940::v179, output_vec_len ); + case 436: return makeRegisterExpression(amdgpu_gfx940::v180, output_vec_len ); + case 437: return makeRegisterExpression(amdgpu_gfx940::v181, output_vec_len ); + case 438: return makeRegisterExpression(amdgpu_gfx940::v182, output_vec_len ); + case 439: return makeRegisterExpression(amdgpu_gfx940::v183, output_vec_len ); + case 440: return makeRegisterExpression(amdgpu_gfx940::v184, output_vec_len ); + case 441: return makeRegisterExpression(amdgpu_gfx940::v185, output_vec_len ); + case 442: return makeRegisterExpression(amdgpu_gfx940::v186, output_vec_len ); + case 443: return makeRegisterExpression(amdgpu_gfx940::v187, output_vec_len ); + case 444: return makeRegisterExpression(amdgpu_gfx940::v188, output_vec_len ); + case 445: return makeRegisterExpression(amdgpu_gfx940::v189, output_vec_len ); + case 446: return makeRegisterExpression(amdgpu_gfx940::v190, output_vec_len ); + case 447: return makeRegisterExpression(amdgpu_gfx940::v191, output_vec_len ); + case 448: return makeRegisterExpression(amdgpu_gfx940::v192, output_vec_len ); + case 449: return makeRegisterExpression(amdgpu_gfx940::v193, output_vec_len ); + case 450: return makeRegisterExpression(amdgpu_gfx940::v194, output_vec_len ); + case 451: return makeRegisterExpression(amdgpu_gfx940::v195, output_vec_len ); + case 452: return makeRegisterExpression(amdgpu_gfx940::v196, output_vec_len ); + case 453: return makeRegisterExpression(amdgpu_gfx940::v197, output_vec_len ); + case 454: return makeRegisterExpression(amdgpu_gfx940::v198, output_vec_len ); + case 455: return makeRegisterExpression(amdgpu_gfx940::v199, output_vec_len ); + case 456: return makeRegisterExpression(amdgpu_gfx940::v200, output_vec_len ); + case 457: return makeRegisterExpression(amdgpu_gfx940::v201, output_vec_len ); + case 458: return makeRegisterExpression(amdgpu_gfx940::v202, output_vec_len ); + case 459: return makeRegisterExpression(amdgpu_gfx940::v203, output_vec_len ); + case 460: return makeRegisterExpression(amdgpu_gfx940::v204, output_vec_len ); + case 461: return makeRegisterExpression(amdgpu_gfx940::v205, output_vec_len ); + case 462: return makeRegisterExpression(amdgpu_gfx940::v206, output_vec_len ); + case 463: return makeRegisterExpression(amdgpu_gfx940::v207, output_vec_len ); + case 464: return makeRegisterExpression(amdgpu_gfx940::v208, output_vec_len ); + case 465: return makeRegisterExpression(amdgpu_gfx940::v209, output_vec_len ); + case 466: return makeRegisterExpression(amdgpu_gfx940::v210, output_vec_len ); + case 467: return makeRegisterExpression(amdgpu_gfx940::v211, output_vec_len ); + case 468: return makeRegisterExpression(amdgpu_gfx940::v212, output_vec_len ); + case 469: return makeRegisterExpression(amdgpu_gfx940::v213, output_vec_len ); + case 470: return makeRegisterExpression(amdgpu_gfx940::v214, output_vec_len ); + case 471: return makeRegisterExpression(amdgpu_gfx940::v215, output_vec_len ); + case 472: return makeRegisterExpression(amdgpu_gfx940::v216, output_vec_len ); + case 473: return makeRegisterExpression(amdgpu_gfx940::v217, output_vec_len ); + case 474: return makeRegisterExpression(amdgpu_gfx940::v218, output_vec_len ); + case 475: return makeRegisterExpression(amdgpu_gfx940::v219, output_vec_len ); + case 476: return makeRegisterExpression(amdgpu_gfx940::v220, output_vec_len ); + case 477: return makeRegisterExpression(amdgpu_gfx940::v221, output_vec_len ); + case 478: return makeRegisterExpression(amdgpu_gfx940::v222, output_vec_len ); + case 479: return makeRegisterExpression(amdgpu_gfx940::v223, output_vec_len ); + case 480: return makeRegisterExpression(amdgpu_gfx940::v224, output_vec_len ); + case 481: return makeRegisterExpression(amdgpu_gfx940::v225, output_vec_len ); + case 482: return makeRegisterExpression(amdgpu_gfx940::v226, output_vec_len ); + case 483: return makeRegisterExpression(amdgpu_gfx940::v227, output_vec_len ); + case 484: return makeRegisterExpression(amdgpu_gfx940::v228, output_vec_len ); + case 485: return makeRegisterExpression(amdgpu_gfx940::v229, output_vec_len ); + case 486: return makeRegisterExpression(amdgpu_gfx940::v230, output_vec_len ); + case 487: return makeRegisterExpression(amdgpu_gfx940::v231, output_vec_len ); + case 488: return makeRegisterExpression(amdgpu_gfx940::v232, output_vec_len ); + case 489: return makeRegisterExpression(amdgpu_gfx940::v233, output_vec_len ); + case 490: return makeRegisterExpression(amdgpu_gfx940::v234, output_vec_len ); + case 491: return makeRegisterExpression(amdgpu_gfx940::v235, output_vec_len ); + case 492: return makeRegisterExpression(amdgpu_gfx940::v236, output_vec_len ); + case 493: return makeRegisterExpression(amdgpu_gfx940::v237, output_vec_len ); + case 494: return makeRegisterExpression(amdgpu_gfx940::v238, output_vec_len ); + case 495: return makeRegisterExpression(amdgpu_gfx940::v239, output_vec_len ); + case 496: return makeRegisterExpression(amdgpu_gfx940::v240, output_vec_len ); + case 497: return makeRegisterExpression(amdgpu_gfx940::v241, output_vec_len ); + case 498: return makeRegisterExpression(amdgpu_gfx940::v242, output_vec_len ); + case 499: return makeRegisterExpression(amdgpu_gfx940::v243, output_vec_len ); + case 500: return makeRegisterExpression(amdgpu_gfx940::v244, output_vec_len ); + case 501: return makeRegisterExpression(amdgpu_gfx940::v245, output_vec_len ); + case 502: return makeRegisterExpression(amdgpu_gfx940::v246, output_vec_len ); + case 503: return makeRegisterExpression(amdgpu_gfx940::v247, output_vec_len ); + case 504: return makeRegisterExpression(amdgpu_gfx940::v248, output_vec_len ); + case 505: return makeRegisterExpression(amdgpu_gfx940::v249, output_vec_len ); + case 506: return makeRegisterExpression(amdgpu_gfx940::v250, output_vec_len ); + case 507: return makeRegisterExpression(amdgpu_gfx940::v251, output_vec_len ); + case 508: return makeRegisterExpression(amdgpu_gfx940::v252, output_vec_len ); + case 509: return makeRegisterExpression(amdgpu_gfx940::v253, output_vec_len ); + case 510: return makeRegisterExpression(amdgpu_gfx940::v254, output_vec_len ); + case 511: return makeRegisterExpression(amdgpu_gfx940::v255, output_vec_len ); + case 255: return Immediate::makeImmediate(Result(u32,decodeOPR_LITERAL())); + case 249 : return decodeOPR_SDWA(); + default: return makeRegisterExpression(amdgpu_gfx940::invalid); + } + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx940::decodeOPR_SRC_ACCVGPR(uint64_t input, uint32_t output_vec_len) + { + switch (input) { + case 256: return makeRegisterExpression(amdgpu_gfx940::acc0, output_vec_len ); + case 257: return makeRegisterExpression(amdgpu_gfx940::acc1, output_vec_len ); + case 258: return makeRegisterExpression(amdgpu_gfx940::acc2, output_vec_len ); + case 259: return makeRegisterExpression(amdgpu_gfx940::acc3, output_vec_len ); + case 260: return makeRegisterExpression(amdgpu_gfx940::acc4, output_vec_len ); + case 261: return makeRegisterExpression(amdgpu_gfx940::acc5, output_vec_len ); + case 262: return makeRegisterExpression(amdgpu_gfx940::acc6, output_vec_len ); + case 263: return makeRegisterExpression(amdgpu_gfx940::acc7, output_vec_len ); + case 264: return makeRegisterExpression(amdgpu_gfx940::acc8, output_vec_len ); + case 265: return makeRegisterExpression(amdgpu_gfx940::acc9, output_vec_len ); + case 266: return makeRegisterExpression(amdgpu_gfx940::acc10, output_vec_len ); + case 267: return makeRegisterExpression(amdgpu_gfx940::acc11, output_vec_len ); + case 268: return makeRegisterExpression(amdgpu_gfx940::acc12, output_vec_len ); + case 269: return makeRegisterExpression(amdgpu_gfx940::acc13, output_vec_len ); + case 270: return makeRegisterExpression(amdgpu_gfx940::acc14, output_vec_len ); + case 271: return makeRegisterExpression(amdgpu_gfx940::acc15, output_vec_len ); + case 272: return makeRegisterExpression(amdgpu_gfx940::acc16, output_vec_len ); + case 273: return makeRegisterExpression(amdgpu_gfx940::acc17, output_vec_len ); + case 274: return makeRegisterExpression(amdgpu_gfx940::acc18, output_vec_len ); + case 275: return makeRegisterExpression(amdgpu_gfx940::acc19, output_vec_len ); + case 276: return makeRegisterExpression(amdgpu_gfx940::acc20, output_vec_len ); + case 277: return makeRegisterExpression(amdgpu_gfx940::acc21, output_vec_len ); + case 278: return makeRegisterExpression(amdgpu_gfx940::acc22, output_vec_len ); + case 279: return makeRegisterExpression(amdgpu_gfx940::acc23, output_vec_len ); + case 280: return makeRegisterExpression(amdgpu_gfx940::acc24, output_vec_len ); + case 281: return makeRegisterExpression(amdgpu_gfx940::acc25, output_vec_len ); + case 282: return makeRegisterExpression(amdgpu_gfx940::acc26, output_vec_len ); + case 283: return makeRegisterExpression(amdgpu_gfx940::acc27, output_vec_len ); + case 284: return makeRegisterExpression(amdgpu_gfx940::acc28, output_vec_len ); + case 285: return makeRegisterExpression(amdgpu_gfx940::acc29, output_vec_len ); + case 286: return makeRegisterExpression(amdgpu_gfx940::acc30, output_vec_len ); + case 287: return makeRegisterExpression(amdgpu_gfx940::acc31, output_vec_len ); + case 288: return makeRegisterExpression(amdgpu_gfx940::acc32, output_vec_len ); + case 289: return makeRegisterExpression(amdgpu_gfx940::acc33, output_vec_len ); + case 290: return makeRegisterExpression(amdgpu_gfx940::acc34, output_vec_len ); + case 291: return makeRegisterExpression(amdgpu_gfx940::acc35, output_vec_len ); + case 292: return makeRegisterExpression(amdgpu_gfx940::acc36, output_vec_len ); + case 293: return makeRegisterExpression(amdgpu_gfx940::acc37, output_vec_len ); + case 294: return makeRegisterExpression(amdgpu_gfx940::acc38, output_vec_len ); + case 295: return makeRegisterExpression(amdgpu_gfx940::acc39, output_vec_len ); + case 296: return makeRegisterExpression(amdgpu_gfx940::acc40, output_vec_len ); + case 297: return makeRegisterExpression(amdgpu_gfx940::acc41, output_vec_len ); + case 298: return makeRegisterExpression(amdgpu_gfx940::acc42, output_vec_len ); + case 299: return makeRegisterExpression(amdgpu_gfx940::acc43, output_vec_len ); + case 300: return makeRegisterExpression(amdgpu_gfx940::acc44, output_vec_len ); + case 301: return makeRegisterExpression(amdgpu_gfx940::acc45, output_vec_len ); + case 302: return makeRegisterExpression(amdgpu_gfx940::acc46, output_vec_len ); + case 303: return makeRegisterExpression(amdgpu_gfx940::acc47, output_vec_len ); + case 304: return makeRegisterExpression(amdgpu_gfx940::acc48, output_vec_len ); + case 305: return makeRegisterExpression(amdgpu_gfx940::acc49, output_vec_len ); + case 306: return makeRegisterExpression(amdgpu_gfx940::acc50, output_vec_len ); + case 307: return makeRegisterExpression(amdgpu_gfx940::acc51, output_vec_len ); + case 308: return makeRegisterExpression(amdgpu_gfx940::acc52, output_vec_len ); + case 309: return makeRegisterExpression(amdgpu_gfx940::acc53, output_vec_len ); + case 310: return makeRegisterExpression(amdgpu_gfx940::acc54, output_vec_len ); + case 311: return makeRegisterExpression(amdgpu_gfx940::acc55, output_vec_len ); + case 312: return makeRegisterExpression(amdgpu_gfx940::acc56, output_vec_len ); + case 313: return makeRegisterExpression(amdgpu_gfx940::acc57, output_vec_len ); + case 314: return makeRegisterExpression(amdgpu_gfx940::acc58, output_vec_len ); + case 315: return makeRegisterExpression(amdgpu_gfx940::acc59, output_vec_len ); + case 316: return makeRegisterExpression(amdgpu_gfx940::acc60, output_vec_len ); + case 317: return makeRegisterExpression(amdgpu_gfx940::acc61, output_vec_len ); + case 318: return makeRegisterExpression(amdgpu_gfx940::acc62, output_vec_len ); + case 319: return makeRegisterExpression(amdgpu_gfx940::acc63, output_vec_len ); + case 320: return makeRegisterExpression(amdgpu_gfx940::acc64, output_vec_len ); + case 321: return makeRegisterExpression(amdgpu_gfx940::acc65, output_vec_len ); + case 322: return makeRegisterExpression(amdgpu_gfx940::acc66, output_vec_len ); + case 323: return makeRegisterExpression(amdgpu_gfx940::acc67, output_vec_len ); + case 324: return makeRegisterExpression(amdgpu_gfx940::acc68, output_vec_len ); + case 325: return makeRegisterExpression(amdgpu_gfx940::acc69, output_vec_len ); + case 326: return makeRegisterExpression(amdgpu_gfx940::acc70, output_vec_len ); + case 327: return makeRegisterExpression(amdgpu_gfx940::acc71, output_vec_len ); + case 328: return makeRegisterExpression(amdgpu_gfx940::acc72, output_vec_len ); + case 329: return makeRegisterExpression(amdgpu_gfx940::acc73, output_vec_len ); + case 330: return makeRegisterExpression(amdgpu_gfx940::acc74, output_vec_len ); + case 331: return makeRegisterExpression(amdgpu_gfx940::acc75, output_vec_len ); + case 332: return makeRegisterExpression(amdgpu_gfx940::acc76, output_vec_len ); + case 333: return makeRegisterExpression(amdgpu_gfx940::acc77, output_vec_len ); + case 334: return makeRegisterExpression(amdgpu_gfx940::acc78, output_vec_len ); + case 335: return makeRegisterExpression(amdgpu_gfx940::acc79, output_vec_len ); + case 336: return makeRegisterExpression(amdgpu_gfx940::acc80, output_vec_len ); + case 337: return makeRegisterExpression(amdgpu_gfx940::acc81, output_vec_len ); + case 338: return makeRegisterExpression(amdgpu_gfx940::acc82, output_vec_len ); + case 339: return makeRegisterExpression(amdgpu_gfx940::acc83, output_vec_len ); + case 340: return makeRegisterExpression(amdgpu_gfx940::acc84, output_vec_len ); + case 341: return makeRegisterExpression(amdgpu_gfx940::acc85, output_vec_len ); + case 342: return makeRegisterExpression(amdgpu_gfx940::acc86, output_vec_len ); + case 343: return makeRegisterExpression(amdgpu_gfx940::acc87, output_vec_len ); + case 344: return makeRegisterExpression(amdgpu_gfx940::acc88, output_vec_len ); + case 345: return makeRegisterExpression(amdgpu_gfx940::acc89, output_vec_len ); + case 346: return makeRegisterExpression(amdgpu_gfx940::acc90, output_vec_len ); + case 347: return makeRegisterExpression(amdgpu_gfx940::acc91, output_vec_len ); + case 348: return makeRegisterExpression(amdgpu_gfx940::acc92, output_vec_len ); + case 349: return makeRegisterExpression(amdgpu_gfx940::acc93, output_vec_len ); + case 350: return makeRegisterExpression(amdgpu_gfx940::acc94, output_vec_len ); + case 351: return makeRegisterExpression(amdgpu_gfx940::acc95, output_vec_len ); + case 352: return makeRegisterExpression(amdgpu_gfx940::acc96, output_vec_len ); + case 353: return makeRegisterExpression(amdgpu_gfx940::acc97, output_vec_len ); + case 354: return makeRegisterExpression(amdgpu_gfx940::acc98, output_vec_len ); + case 355: return makeRegisterExpression(amdgpu_gfx940::acc99, output_vec_len ); + case 356: return makeRegisterExpression(amdgpu_gfx940::acc100, output_vec_len ); + case 357: return makeRegisterExpression(amdgpu_gfx940::acc101, output_vec_len ); + case 358: return makeRegisterExpression(amdgpu_gfx940::acc102, output_vec_len ); + case 359: return makeRegisterExpression(amdgpu_gfx940::acc103, output_vec_len ); + case 360: return makeRegisterExpression(amdgpu_gfx940::acc104, output_vec_len ); + case 361: return makeRegisterExpression(amdgpu_gfx940::acc105, output_vec_len ); + case 362: return makeRegisterExpression(amdgpu_gfx940::acc106, output_vec_len ); + case 363: return makeRegisterExpression(amdgpu_gfx940::acc107, output_vec_len ); + case 364: return makeRegisterExpression(amdgpu_gfx940::acc108, output_vec_len ); + case 365: return makeRegisterExpression(amdgpu_gfx940::acc109, output_vec_len ); + case 366: return makeRegisterExpression(amdgpu_gfx940::acc110, output_vec_len ); + case 367: return makeRegisterExpression(amdgpu_gfx940::acc111, output_vec_len ); + case 368: return makeRegisterExpression(amdgpu_gfx940::acc112, output_vec_len ); + case 369: return makeRegisterExpression(amdgpu_gfx940::acc113, output_vec_len ); + case 370: return makeRegisterExpression(amdgpu_gfx940::acc114, output_vec_len ); + case 371: return makeRegisterExpression(amdgpu_gfx940::acc115, output_vec_len ); + case 372: return makeRegisterExpression(amdgpu_gfx940::acc116, output_vec_len ); + case 373: return makeRegisterExpression(amdgpu_gfx940::acc117, output_vec_len ); + case 374: return makeRegisterExpression(amdgpu_gfx940::acc118, output_vec_len ); + case 375: return makeRegisterExpression(amdgpu_gfx940::acc119, output_vec_len ); + case 376: return makeRegisterExpression(amdgpu_gfx940::acc120, output_vec_len ); + case 377: return makeRegisterExpression(amdgpu_gfx940::acc121, output_vec_len ); + case 378: return makeRegisterExpression(amdgpu_gfx940::acc122, output_vec_len ); + case 379: return makeRegisterExpression(amdgpu_gfx940::acc123, output_vec_len ); + case 380: return makeRegisterExpression(amdgpu_gfx940::acc124, output_vec_len ); + case 381: return makeRegisterExpression(amdgpu_gfx940::acc125, output_vec_len ); + case 382: return makeRegisterExpression(amdgpu_gfx940::acc126, output_vec_len ); + case 383: return makeRegisterExpression(amdgpu_gfx940::acc127, output_vec_len ); + case 384: return makeRegisterExpression(amdgpu_gfx940::acc128, output_vec_len ); + case 385: return makeRegisterExpression(amdgpu_gfx940::acc129, output_vec_len ); + case 386: return makeRegisterExpression(amdgpu_gfx940::acc130, output_vec_len ); + case 387: return makeRegisterExpression(amdgpu_gfx940::acc131, output_vec_len ); + case 388: return makeRegisterExpression(amdgpu_gfx940::acc132, output_vec_len ); + case 389: return makeRegisterExpression(amdgpu_gfx940::acc133, output_vec_len ); + case 390: return makeRegisterExpression(amdgpu_gfx940::acc134, output_vec_len ); + case 391: return makeRegisterExpression(amdgpu_gfx940::acc135, output_vec_len ); + case 392: return makeRegisterExpression(amdgpu_gfx940::acc136, output_vec_len ); + case 393: return makeRegisterExpression(amdgpu_gfx940::acc137, output_vec_len ); + case 394: return makeRegisterExpression(amdgpu_gfx940::acc138, output_vec_len ); + case 395: return makeRegisterExpression(amdgpu_gfx940::acc139, output_vec_len ); + case 396: return makeRegisterExpression(amdgpu_gfx940::acc140, output_vec_len ); + case 397: return makeRegisterExpression(amdgpu_gfx940::acc141, output_vec_len ); + case 398: return makeRegisterExpression(amdgpu_gfx940::acc142, output_vec_len ); + case 399: return makeRegisterExpression(amdgpu_gfx940::acc143, output_vec_len ); + case 400: return makeRegisterExpression(amdgpu_gfx940::acc144, output_vec_len ); + case 401: return makeRegisterExpression(amdgpu_gfx940::acc145, output_vec_len ); + case 402: return makeRegisterExpression(amdgpu_gfx940::acc146, output_vec_len ); + case 403: return makeRegisterExpression(amdgpu_gfx940::acc147, output_vec_len ); + case 404: return makeRegisterExpression(amdgpu_gfx940::acc148, output_vec_len ); + case 405: return makeRegisterExpression(amdgpu_gfx940::acc149, output_vec_len ); + case 406: return makeRegisterExpression(amdgpu_gfx940::acc150, output_vec_len ); + case 407: return makeRegisterExpression(amdgpu_gfx940::acc151, output_vec_len ); + case 408: return makeRegisterExpression(amdgpu_gfx940::acc152, output_vec_len ); + case 409: return makeRegisterExpression(amdgpu_gfx940::acc153, output_vec_len ); + case 410: return makeRegisterExpression(amdgpu_gfx940::acc154, output_vec_len ); + case 411: return makeRegisterExpression(amdgpu_gfx940::acc155, output_vec_len ); + case 412: return makeRegisterExpression(amdgpu_gfx940::acc156, output_vec_len ); + case 413: return makeRegisterExpression(amdgpu_gfx940::acc157, output_vec_len ); + case 414: return makeRegisterExpression(amdgpu_gfx940::acc158, output_vec_len ); + case 415: return makeRegisterExpression(amdgpu_gfx940::acc159, output_vec_len ); + case 416: return makeRegisterExpression(amdgpu_gfx940::acc160, output_vec_len ); + case 417: return makeRegisterExpression(amdgpu_gfx940::acc161, output_vec_len ); + case 418: return makeRegisterExpression(amdgpu_gfx940::acc162, output_vec_len ); + case 419: return makeRegisterExpression(amdgpu_gfx940::acc163, output_vec_len ); + case 420: return makeRegisterExpression(amdgpu_gfx940::acc164, output_vec_len ); + case 421: return makeRegisterExpression(amdgpu_gfx940::acc165, output_vec_len ); + case 422: return makeRegisterExpression(amdgpu_gfx940::acc166, output_vec_len ); + case 423: return makeRegisterExpression(amdgpu_gfx940::acc167, output_vec_len ); + case 424: return makeRegisterExpression(amdgpu_gfx940::acc168, output_vec_len ); + case 425: return makeRegisterExpression(amdgpu_gfx940::acc169, output_vec_len ); + case 426: return makeRegisterExpression(amdgpu_gfx940::acc170, output_vec_len ); + case 427: return makeRegisterExpression(amdgpu_gfx940::acc171, output_vec_len ); + case 428: return makeRegisterExpression(amdgpu_gfx940::acc172, output_vec_len ); + case 429: return makeRegisterExpression(amdgpu_gfx940::acc173, output_vec_len ); + case 430: return makeRegisterExpression(amdgpu_gfx940::acc174, output_vec_len ); + case 431: return makeRegisterExpression(amdgpu_gfx940::acc175, output_vec_len ); + case 432: return makeRegisterExpression(amdgpu_gfx940::acc176, output_vec_len ); + case 433: return makeRegisterExpression(amdgpu_gfx940::acc177, output_vec_len ); + case 434: return makeRegisterExpression(amdgpu_gfx940::acc178, output_vec_len ); + case 435: return makeRegisterExpression(amdgpu_gfx940::acc179, output_vec_len ); + case 436: return makeRegisterExpression(amdgpu_gfx940::acc180, output_vec_len ); + case 437: return makeRegisterExpression(amdgpu_gfx940::acc181, output_vec_len ); + case 438: return makeRegisterExpression(amdgpu_gfx940::acc182, output_vec_len ); + case 439: return makeRegisterExpression(amdgpu_gfx940::acc183, output_vec_len ); + case 440: return makeRegisterExpression(amdgpu_gfx940::acc184, output_vec_len ); + case 441: return makeRegisterExpression(amdgpu_gfx940::acc185, output_vec_len ); + case 442: return makeRegisterExpression(amdgpu_gfx940::acc186, output_vec_len ); + case 443: return makeRegisterExpression(amdgpu_gfx940::acc187, output_vec_len ); + case 444: return makeRegisterExpression(amdgpu_gfx940::acc188, output_vec_len ); + case 445: return makeRegisterExpression(amdgpu_gfx940::acc189, output_vec_len ); + case 446: return makeRegisterExpression(amdgpu_gfx940::acc190, output_vec_len ); + case 447: return makeRegisterExpression(amdgpu_gfx940::acc191, output_vec_len ); + case 448: return makeRegisterExpression(amdgpu_gfx940::acc192, output_vec_len ); + case 449: return makeRegisterExpression(amdgpu_gfx940::acc193, output_vec_len ); + case 450: return makeRegisterExpression(amdgpu_gfx940::acc194, output_vec_len ); + case 451: return makeRegisterExpression(amdgpu_gfx940::acc195, output_vec_len ); + case 452: return makeRegisterExpression(amdgpu_gfx940::acc196, output_vec_len ); + case 453: return makeRegisterExpression(amdgpu_gfx940::acc197, output_vec_len ); + case 454: return makeRegisterExpression(amdgpu_gfx940::acc198, output_vec_len ); + case 455: return makeRegisterExpression(amdgpu_gfx940::acc199, output_vec_len ); + case 456: return makeRegisterExpression(amdgpu_gfx940::acc200, output_vec_len ); + case 457: return makeRegisterExpression(amdgpu_gfx940::acc201, output_vec_len ); + case 458: return makeRegisterExpression(amdgpu_gfx940::acc202, output_vec_len ); + case 459: return makeRegisterExpression(amdgpu_gfx940::acc203, output_vec_len ); + case 460: return makeRegisterExpression(amdgpu_gfx940::acc204, output_vec_len ); + case 461: return makeRegisterExpression(amdgpu_gfx940::acc205, output_vec_len ); + case 462: return makeRegisterExpression(amdgpu_gfx940::acc206, output_vec_len ); + case 463: return makeRegisterExpression(amdgpu_gfx940::acc207, output_vec_len ); + case 464: return makeRegisterExpression(amdgpu_gfx940::acc208, output_vec_len ); + case 465: return makeRegisterExpression(amdgpu_gfx940::acc209, output_vec_len ); + case 466: return makeRegisterExpression(amdgpu_gfx940::acc210, output_vec_len ); + case 467: return makeRegisterExpression(amdgpu_gfx940::acc211, output_vec_len ); + case 468: return makeRegisterExpression(amdgpu_gfx940::acc212, output_vec_len ); + case 469: return makeRegisterExpression(amdgpu_gfx940::acc213, output_vec_len ); + case 470: return makeRegisterExpression(amdgpu_gfx940::acc214, output_vec_len ); + case 471: return makeRegisterExpression(amdgpu_gfx940::acc215, output_vec_len ); + case 472: return makeRegisterExpression(amdgpu_gfx940::acc216, output_vec_len ); + case 473: return makeRegisterExpression(amdgpu_gfx940::acc217, output_vec_len ); + case 474: return makeRegisterExpression(amdgpu_gfx940::acc218, output_vec_len ); + case 475: return makeRegisterExpression(amdgpu_gfx940::acc219, output_vec_len ); + case 476: return makeRegisterExpression(amdgpu_gfx940::acc220, output_vec_len ); + case 477: return makeRegisterExpression(amdgpu_gfx940::acc221, output_vec_len ); + case 478: return makeRegisterExpression(amdgpu_gfx940::acc222, output_vec_len ); + case 479: return makeRegisterExpression(amdgpu_gfx940::acc223, output_vec_len ); + case 480: return makeRegisterExpression(amdgpu_gfx940::acc224, output_vec_len ); + case 481: return makeRegisterExpression(amdgpu_gfx940::acc225, output_vec_len ); + case 482: return makeRegisterExpression(amdgpu_gfx940::acc226, output_vec_len ); + case 483: return makeRegisterExpression(amdgpu_gfx940::acc227, output_vec_len ); + case 484: return makeRegisterExpression(amdgpu_gfx940::acc228, output_vec_len ); + case 485: return makeRegisterExpression(amdgpu_gfx940::acc229, output_vec_len ); + case 486: return makeRegisterExpression(amdgpu_gfx940::acc230, output_vec_len ); + case 487: return makeRegisterExpression(amdgpu_gfx940::acc231, output_vec_len ); + case 488: return makeRegisterExpression(amdgpu_gfx940::acc232, output_vec_len ); + case 489: return makeRegisterExpression(amdgpu_gfx940::acc233, output_vec_len ); + case 490: return makeRegisterExpression(amdgpu_gfx940::acc234, output_vec_len ); + case 491: return makeRegisterExpression(amdgpu_gfx940::acc235, output_vec_len ); + case 492: return makeRegisterExpression(amdgpu_gfx940::acc236, output_vec_len ); + case 493: return makeRegisterExpression(amdgpu_gfx940::acc237, output_vec_len ); + case 494: return makeRegisterExpression(amdgpu_gfx940::acc238, output_vec_len ); + case 495: return makeRegisterExpression(amdgpu_gfx940::acc239, output_vec_len ); + case 496: return makeRegisterExpression(amdgpu_gfx940::acc240, output_vec_len ); + case 497: return makeRegisterExpression(amdgpu_gfx940::acc241, output_vec_len ); + case 498: return makeRegisterExpression(amdgpu_gfx940::acc242, output_vec_len ); + case 499: return makeRegisterExpression(amdgpu_gfx940::acc243, output_vec_len ); + case 500: return makeRegisterExpression(amdgpu_gfx940::acc244, output_vec_len ); + case 501: return makeRegisterExpression(amdgpu_gfx940::acc245, output_vec_len ); + case 502: return makeRegisterExpression(amdgpu_gfx940::acc246, output_vec_len ); + case 503: return makeRegisterExpression(amdgpu_gfx940::acc247, output_vec_len ); + case 504: return makeRegisterExpression(amdgpu_gfx940::acc248, output_vec_len ); + case 505: return makeRegisterExpression(amdgpu_gfx940::acc249, output_vec_len ); + case 506: return makeRegisterExpression(amdgpu_gfx940::acc250, output_vec_len ); + case 507: return makeRegisterExpression(amdgpu_gfx940::acc251, output_vec_len ); + case 508: return makeRegisterExpression(amdgpu_gfx940::acc252, output_vec_len ); + case 509: return makeRegisterExpression(amdgpu_gfx940::acc253, output_vec_len ); + case 510: return makeRegisterExpression(amdgpu_gfx940::acc254, output_vec_len ); + case 511: return makeRegisterExpression(amdgpu_gfx940::acc255, output_vec_len ); + case 768: return makeRegisterExpression(amdgpu_gfx940::acc0, output_vec_len ); + case 769: return makeRegisterExpression(amdgpu_gfx940::acc1, output_vec_len ); + case 770: return makeRegisterExpression(amdgpu_gfx940::acc2, output_vec_len ); + case 771: return makeRegisterExpression(amdgpu_gfx940::acc3, output_vec_len ); + case 772: return makeRegisterExpression(amdgpu_gfx940::acc4, output_vec_len ); + case 773: return makeRegisterExpression(amdgpu_gfx940::acc5, output_vec_len ); + case 774: return makeRegisterExpression(amdgpu_gfx940::acc6, output_vec_len ); + case 775: return makeRegisterExpression(amdgpu_gfx940::acc7, output_vec_len ); + case 776: return makeRegisterExpression(amdgpu_gfx940::acc8, output_vec_len ); + case 777: return makeRegisterExpression(amdgpu_gfx940::acc9, output_vec_len ); + case 778: return makeRegisterExpression(amdgpu_gfx940::acc10, output_vec_len ); + case 779: return makeRegisterExpression(amdgpu_gfx940::acc11, output_vec_len ); + case 780: return makeRegisterExpression(amdgpu_gfx940::acc12, output_vec_len ); + case 781: return makeRegisterExpression(amdgpu_gfx940::acc13, output_vec_len ); + case 782: return makeRegisterExpression(amdgpu_gfx940::acc14, output_vec_len ); + case 783: return makeRegisterExpression(amdgpu_gfx940::acc15, output_vec_len ); + case 784: return makeRegisterExpression(amdgpu_gfx940::acc16, output_vec_len ); + case 785: return makeRegisterExpression(amdgpu_gfx940::acc17, output_vec_len ); + case 786: return makeRegisterExpression(amdgpu_gfx940::acc18, output_vec_len ); + case 787: return makeRegisterExpression(amdgpu_gfx940::acc19, output_vec_len ); + case 788: return makeRegisterExpression(amdgpu_gfx940::acc20, output_vec_len ); + case 789: return makeRegisterExpression(amdgpu_gfx940::acc21, output_vec_len ); + case 790: return makeRegisterExpression(amdgpu_gfx940::acc22, output_vec_len ); + case 791: return makeRegisterExpression(amdgpu_gfx940::acc23, output_vec_len ); + case 792: return makeRegisterExpression(amdgpu_gfx940::acc24, output_vec_len ); + case 793: return makeRegisterExpression(amdgpu_gfx940::acc25, output_vec_len ); + case 794: return makeRegisterExpression(amdgpu_gfx940::acc26, output_vec_len ); + case 795: return makeRegisterExpression(amdgpu_gfx940::acc27, output_vec_len ); + case 796: return makeRegisterExpression(amdgpu_gfx940::acc28, output_vec_len ); + case 797: return makeRegisterExpression(amdgpu_gfx940::acc29, output_vec_len ); + case 798: return makeRegisterExpression(amdgpu_gfx940::acc30, output_vec_len ); + case 799: return makeRegisterExpression(amdgpu_gfx940::acc31, output_vec_len ); + case 800: return makeRegisterExpression(amdgpu_gfx940::acc32, output_vec_len ); + case 801: return makeRegisterExpression(amdgpu_gfx940::acc33, output_vec_len ); + case 802: return makeRegisterExpression(amdgpu_gfx940::acc34, output_vec_len ); + case 803: return makeRegisterExpression(amdgpu_gfx940::acc35, output_vec_len ); + case 804: return makeRegisterExpression(amdgpu_gfx940::acc36, output_vec_len ); + case 805: return makeRegisterExpression(amdgpu_gfx940::acc37, output_vec_len ); + case 806: return makeRegisterExpression(amdgpu_gfx940::acc38, output_vec_len ); + case 807: return makeRegisterExpression(amdgpu_gfx940::acc39, output_vec_len ); + case 808: return makeRegisterExpression(amdgpu_gfx940::acc40, output_vec_len ); + case 809: return makeRegisterExpression(amdgpu_gfx940::acc41, output_vec_len ); + case 810: return makeRegisterExpression(amdgpu_gfx940::acc42, output_vec_len ); + case 811: return makeRegisterExpression(amdgpu_gfx940::acc43, output_vec_len ); + case 812: return makeRegisterExpression(amdgpu_gfx940::acc44, output_vec_len ); + case 813: return makeRegisterExpression(amdgpu_gfx940::acc45, output_vec_len ); + case 814: return makeRegisterExpression(amdgpu_gfx940::acc46, output_vec_len ); + case 815: return makeRegisterExpression(amdgpu_gfx940::acc47, output_vec_len ); + case 816: return makeRegisterExpression(amdgpu_gfx940::acc48, output_vec_len ); + case 817: return makeRegisterExpression(amdgpu_gfx940::acc49, output_vec_len ); + case 818: return makeRegisterExpression(amdgpu_gfx940::acc50, output_vec_len ); + case 819: return makeRegisterExpression(amdgpu_gfx940::acc51, output_vec_len ); + case 820: return makeRegisterExpression(amdgpu_gfx940::acc52, output_vec_len ); + case 821: return makeRegisterExpression(amdgpu_gfx940::acc53, output_vec_len ); + case 822: return makeRegisterExpression(amdgpu_gfx940::acc54, output_vec_len ); + case 823: return makeRegisterExpression(amdgpu_gfx940::acc55, output_vec_len ); + case 824: return makeRegisterExpression(amdgpu_gfx940::acc56, output_vec_len ); + case 825: return makeRegisterExpression(amdgpu_gfx940::acc57, output_vec_len ); + case 826: return makeRegisterExpression(amdgpu_gfx940::acc58, output_vec_len ); + case 827: return makeRegisterExpression(amdgpu_gfx940::acc59, output_vec_len ); + case 828: return makeRegisterExpression(amdgpu_gfx940::acc60, output_vec_len ); + case 829: return makeRegisterExpression(amdgpu_gfx940::acc61, output_vec_len ); + case 830: return makeRegisterExpression(amdgpu_gfx940::acc62, output_vec_len ); + case 831: return makeRegisterExpression(amdgpu_gfx940::acc63, output_vec_len ); + case 832: return makeRegisterExpression(amdgpu_gfx940::acc64, output_vec_len ); + case 833: return makeRegisterExpression(amdgpu_gfx940::acc65, output_vec_len ); + case 834: return makeRegisterExpression(amdgpu_gfx940::acc66, output_vec_len ); + case 835: return makeRegisterExpression(amdgpu_gfx940::acc67, output_vec_len ); + case 836: return makeRegisterExpression(amdgpu_gfx940::acc68, output_vec_len ); + case 837: return makeRegisterExpression(amdgpu_gfx940::acc69, output_vec_len ); + case 838: return makeRegisterExpression(amdgpu_gfx940::acc70, output_vec_len ); + case 839: return makeRegisterExpression(amdgpu_gfx940::acc71, output_vec_len ); + case 840: return makeRegisterExpression(amdgpu_gfx940::acc72, output_vec_len ); + case 841: return makeRegisterExpression(amdgpu_gfx940::acc73, output_vec_len ); + case 842: return makeRegisterExpression(amdgpu_gfx940::acc74, output_vec_len ); + case 843: return makeRegisterExpression(amdgpu_gfx940::acc75, output_vec_len ); + case 844: return makeRegisterExpression(amdgpu_gfx940::acc76, output_vec_len ); + case 845: return makeRegisterExpression(amdgpu_gfx940::acc77, output_vec_len ); + case 846: return makeRegisterExpression(amdgpu_gfx940::acc78, output_vec_len ); + case 847: return makeRegisterExpression(amdgpu_gfx940::acc79, output_vec_len ); + case 848: return makeRegisterExpression(amdgpu_gfx940::acc80, output_vec_len ); + case 849: return makeRegisterExpression(amdgpu_gfx940::acc81, output_vec_len ); + case 850: return makeRegisterExpression(amdgpu_gfx940::acc82, output_vec_len ); + case 851: return makeRegisterExpression(amdgpu_gfx940::acc83, output_vec_len ); + case 852: return makeRegisterExpression(amdgpu_gfx940::acc84, output_vec_len ); + case 853: return makeRegisterExpression(amdgpu_gfx940::acc85, output_vec_len ); + case 854: return makeRegisterExpression(amdgpu_gfx940::acc86, output_vec_len ); + case 855: return makeRegisterExpression(amdgpu_gfx940::acc87, output_vec_len ); + case 856: return makeRegisterExpression(amdgpu_gfx940::acc88, output_vec_len ); + case 857: return makeRegisterExpression(amdgpu_gfx940::acc89, output_vec_len ); + case 858: return makeRegisterExpression(amdgpu_gfx940::acc90, output_vec_len ); + case 859: return makeRegisterExpression(amdgpu_gfx940::acc91, output_vec_len ); + case 860: return makeRegisterExpression(amdgpu_gfx940::acc92, output_vec_len ); + case 861: return makeRegisterExpression(amdgpu_gfx940::acc93, output_vec_len ); + case 862: return makeRegisterExpression(amdgpu_gfx940::acc94, output_vec_len ); + case 863: return makeRegisterExpression(amdgpu_gfx940::acc95, output_vec_len ); + case 864: return makeRegisterExpression(amdgpu_gfx940::acc96, output_vec_len ); + case 865: return makeRegisterExpression(amdgpu_gfx940::acc97, output_vec_len ); + case 866: return makeRegisterExpression(amdgpu_gfx940::acc98, output_vec_len ); + case 867: return makeRegisterExpression(amdgpu_gfx940::acc99, output_vec_len ); + case 868: return makeRegisterExpression(amdgpu_gfx940::acc100, output_vec_len ); + case 869: return makeRegisterExpression(amdgpu_gfx940::acc101, output_vec_len ); + case 870: return makeRegisterExpression(amdgpu_gfx940::acc102, output_vec_len ); + case 871: return makeRegisterExpression(amdgpu_gfx940::acc103, output_vec_len ); + case 872: return makeRegisterExpression(amdgpu_gfx940::acc104, output_vec_len ); + case 873: return makeRegisterExpression(amdgpu_gfx940::acc105, output_vec_len ); + case 874: return makeRegisterExpression(amdgpu_gfx940::acc106, output_vec_len ); + case 875: return makeRegisterExpression(amdgpu_gfx940::acc107, output_vec_len ); + case 876: return makeRegisterExpression(amdgpu_gfx940::acc108, output_vec_len ); + case 877: return makeRegisterExpression(amdgpu_gfx940::acc109, output_vec_len ); + case 878: return makeRegisterExpression(amdgpu_gfx940::acc110, output_vec_len ); + case 879: return makeRegisterExpression(amdgpu_gfx940::acc111, output_vec_len ); + case 880: return makeRegisterExpression(amdgpu_gfx940::acc112, output_vec_len ); + case 881: return makeRegisterExpression(amdgpu_gfx940::acc113, output_vec_len ); + case 882: return makeRegisterExpression(amdgpu_gfx940::acc114, output_vec_len ); + case 883: return makeRegisterExpression(amdgpu_gfx940::acc115, output_vec_len ); + case 884: return makeRegisterExpression(amdgpu_gfx940::acc116, output_vec_len ); + case 885: return makeRegisterExpression(amdgpu_gfx940::acc117, output_vec_len ); + case 886: return makeRegisterExpression(amdgpu_gfx940::acc118, output_vec_len ); + case 887: return makeRegisterExpression(amdgpu_gfx940::acc119, output_vec_len ); + case 888: return makeRegisterExpression(amdgpu_gfx940::acc120, output_vec_len ); + case 889: return makeRegisterExpression(amdgpu_gfx940::acc121, output_vec_len ); + case 890: return makeRegisterExpression(amdgpu_gfx940::acc122, output_vec_len ); + case 891: return makeRegisterExpression(amdgpu_gfx940::acc123, output_vec_len ); + case 892: return makeRegisterExpression(amdgpu_gfx940::acc124, output_vec_len ); + case 893: return makeRegisterExpression(amdgpu_gfx940::acc125, output_vec_len ); + case 894: return makeRegisterExpression(amdgpu_gfx940::acc126, output_vec_len ); + case 895: return makeRegisterExpression(amdgpu_gfx940::acc127, output_vec_len ); + case 896: return makeRegisterExpression(amdgpu_gfx940::acc128, output_vec_len ); + case 897: return makeRegisterExpression(amdgpu_gfx940::acc129, output_vec_len ); + case 898: return makeRegisterExpression(amdgpu_gfx940::acc130, output_vec_len ); + case 899: return makeRegisterExpression(amdgpu_gfx940::acc131, output_vec_len ); + case 900: return makeRegisterExpression(amdgpu_gfx940::acc132, output_vec_len ); + case 901: return makeRegisterExpression(amdgpu_gfx940::acc133, output_vec_len ); + case 902: return makeRegisterExpression(amdgpu_gfx940::acc134, output_vec_len ); + case 903: return makeRegisterExpression(amdgpu_gfx940::acc135, output_vec_len ); + case 904: return makeRegisterExpression(amdgpu_gfx940::acc136, output_vec_len ); + case 905: return makeRegisterExpression(amdgpu_gfx940::acc137, output_vec_len ); + case 906: return makeRegisterExpression(amdgpu_gfx940::acc138, output_vec_len ); + case 907: return makeRegisterExpression(amdgpu_gfx940::acc139, output_vec_len ); + case 908: return makeRegisterExpression(amdgpu_gfx940::acc140, output_vec_len ); + case 909: return makeRegisterExpression(amdgpu_gfx940::acc141, output_vec_len ); + case 910: return makeRegisterExpression(amdgpu_gfx940::acc142, output_vec_len ); + case 911: return makeRegisterExpression(amdgpu_gfx940::acc143, output_vec_len ); + case 912: return makeRegisterExpression(amdgpu_gfx940::acc144, output_vec_len ); + case 913: return makeRegisterExpression(amdgpu_gfx940::acc145, output_vec_len ); + case 914: return makeRegisterExpression(amdgpu_gfx940::acc146, output_vec_len ); + case 915: return makeRegisterExpression(amdgpu_gfx940::acc147, output_vec_len ); + case 916: return makeRegisterExpression(amdgpu_gfx940::acc148, output_vec_len ); + case 917: return makeRegisterExpression(amdgpu_gfx940::acc149, output_vec_len ); + case 918: return makeRegisterExpression(amdgpu_gfx940::acc150, output_vec_len ); + case 919: return makeRegisterExpression(amdgpu_gfx940::acc151, output_vec_len ); + case 920: return makeRegisterExpression(amdgpu_gfx940::acc152, output_vec_len ); + case 921: return makeRegisterExpression(amdgpu_gfx940::acc153, output_vec_len ); + case 922: return makeRegisterExpression(amdgpu_gfx940::acc154, output_vec_len ); + case 923: return makeRegisterExpression(amdgpu_gfx940::acc155, output_vec_len ); + case 924: return makeRegisterExpression(amdgpu_gfx940::acc156, output_vec_len ); + case 925: return makeRegisterExpression(amdgpu_gfx940::acc157, output_vec_len ); + case 926: return makeRegisterExpression(amdgpu_gfx940::acc158, output_vec_len ); + case 927: return makeRegisterExpression(amdgpu_gfx940::acc159, output_vec_len ); + case 928: return makeRegisterExpression(amdgpu_gfx940::acc160, output_vec_len ); + case 929: return makeRegisterExpression(amdgpu_gfx940::acc161, output_vec_len ); + case 930: return makeRegisterExpression(amdgpu_gfx940::acc162, output_vec_len ); + case 931: return makeRegisterExpression(amdgpu_gfx940::acc163, output_vec_len ); + case 932: return makeRegisterExpression(amdgpu_gfx940::acc164, output_vec_len ); + case 933: return makeRegisterExpression(amdgpu_gfx940::acc165, output_vec_len ); + case 934: return makeRegisterExpression(amdgpu_gfx940::acc166, output_vec_len ); + case 935: return makeRegisterExpression(amdgpu_gfx940::acc167, output_vec_len ); + case 936: return makeRegisterExpression(amdgpu_gfx940::acc168, output_vec_len ); + case 937: return makeRegisterExpression(amdgpu_gfx940::acc169, output_vec_len ); + case 938: return makeRegisterExpression(amdgpu_gfx940::acc170, output_vec_len ); + case 939: return makeRegisterExpression(amdgpu_gfx940::acc171, output_vec_len ); + case 940: return makeRegisterExpression(amdgpu_gfx940::acc172, output_vec_len ); + case 941: return makeRegisterExpression(amdgpu_gfx940::acc173, output_vec_len ); + case 942: return makeRegisterExpression(amdgpu_gfx940::acc174, output_vec_len ); + case 943: return makeRegisterExpression(amdgpu_gfx940::acc175, output_vec_len ); + case 944: return makeRegisterExpression(amdgpu_gfx940::acc176, output_vec_len ); + case 945: return makeRegisterExpression(amdgpu_gfx940::acc177, output_vec_len ); + case 946: return makeRegisterExpression(amdgpu_gfx940::acc178, output_vec_len ); + case 947: return makeRegisterExpression(amdgpu_gfx940::acc179, output_vec_len ); + case 948: return makeRegisterExpression(amdgpu_gfx940::acc180, output_vec_len ); + case 949: return makeRegisterExpression(amdgpu_gfx940::acc181, output_vec_len ); + case 950: return makeRegisterExpression(amdgpu_gfx940::acc182, output_vec_len ); + case 951: return makeRegisterExpression(amdgpu_gfx940::acc183, output_vec_len ); + case 952: return makeRegisterExpression(amdgpu_gfx940::acc184, output_vec_len ); + case 953: return makeRegisterExpression(amdgpu_gfx940::acc185, output_vec_len ); + case 954: return makeRegisterExpression(amdgpu_gfx940::acc186, output_vec_len ); + case 955: return makeRegisterExpression(amdgpu_gfx940::acc187, output_vec_len ); + case 956: return makeRegisterExpression(amdgpu_gfx940::acc188, output_vec_len ); + case 957: return makeRegisterExpression(amdgpu_gfx940::acc189, output_vec_len ); + case 958: return makeRegisterExpression(amdgpu_gfx940::acc190, output_vec_len ); + case 959: return makeRegisterExpression(amdgpu_gfx940::acc191, output_vec_len ); + case 960: return makeRegisterExpression(amdgpu_gfx940::acc192, output_vec_len ); + case 961: return makeRegisterExpression(amdgpu_gfx940::acc193, output_vec_len ); + case 962: return makeRegisterExpression(amdgpu_gfx940::acc194, output_vec_len ); + case 963: return makeRegisterExpression(amdgpu_gfx940::acc195, output_vec_len ); + case 964: return makeRegisterExpression(amdgpu_gfx940::acc196, output_vec_len ); + case 965: return makeRegisterExpression(amdgpu_gfx940::acc197, output_vec_len ); + case 966: return makeRegisterExpression(amdgpu_gfx940::acc198, output_vec_len ); + case 967: return makeRegisterExpression(amdgpu_gfx940::acc199, output_vec_len ); + case 968: return makeRegisterExpression(amdgpu_gfx940::acc200, output_vec_len ); + case 969: return makeRegisterExpression(amdgpu_gfx940::acc201, output_vec_len ); + case 970: return makeRegisterExpression(amdgpu_gfx940::acc202, output_vec_len ); + case 971: return makeRegisterExpression(amdgpu_gfx940::acc203, output_vec_len ); + case 972: return makeRegisterExpression(amdgpu_gfx940::acc204, output_vec_len ); + case 973: return makeRegisterExpression(amdgpu_gfx940::acc205, output_vec_len ); + case 974: return makeRegisterExpression(amdgpu_gfx940::acc206, output_vec_len ); + case 975: return makeRegisterExpression(amdgpu_gfx940::acc207, output_vec_len ); + case 976: return makeRegisterExpression(amdgpu_gfx940::acc208, output_vec_len ); + case 977: return makeRegisterExpression(amdgpu_gfx940::acc209, output_vec_len ); + case 978: return makeRegisterExpression(amdgpu_gfx940::acc210, output_vec_len ); + case 979: return makeRegisterExpression(amdgpu_gfx940::acc211, output_vec_len ); + case 980: return makeRegisterExpression(amdgpu_gfx940::acc212, output_vec_len ); + case 981: return makeRegisterExpression(amdgpu_gfx940::acc213, output_vec_len ); + case 982: return makeRegisterExpression(amdgpu_gfx940::acc214, output_vec_len ); + case 983: return makeRegisterExpression(amdgpu_gfx940::acc215, output_vec_len ); + case 984: return makeRegisterExpression(amdgpu_gfx940::acc216, output_vec_len ); + case 985: return makeRegisterExpression(amdgpu_gfx940::acc217, output_vec_len ); + case 986: return makeRegisterExpression(amdgpu_gfx940::acc218, output_vec_len ); + case 987: return makeRegisterExpression(amdgpu_gfx940::acc219, output_vec_len ); + case 988: return makeRegisterExpression(amdgpu_gfx940::acc220, output_vec_len ); + case 989: return makeRegisterExpression(amdgpu_gfx940::acc221, output_vec_len ); + case 990: return makeRegisterExpression(amdgpu_gfx940::acc222, output_vec_len ); + case 991: return makeRegisterExpression(amdgpu_gfx940::acc223, output_vec_len ); + case 992: return makeRegisterExpression(amdgpu_gfx940::acc224, output_vec_len ); + case 993: return makeRegisterExpression(amdgpu_gfx940::acc225, output_vec_len ); + case 994: return makeRegisterExpression(amdgpu_gfx940::acc226, output_vec_len ); + case 995: return makeRegisterExpression(amdgpu_gfx940::acc227, output_vec_len ); + case 996: return makeRegisterExpression(amdgpu_gfx940::acc228, output_vec_len ); + case 997: return makeRegisterExpression(amdgpu_gfx940::acc229, output_vec_len ); + case 998: return makeRegisterExpression(amdgpu_gfx940::acc230, output_vec_len ); + case 999: return makeRegisterExpression(amdgpu_gfx940::acc231, output_vec_len ); + case 1000: return makeRegisterExpression(amdgpu_gfx940::acc232, output_vec_len ); + case 1001: return makeRegisterExpression(amdgpu_gfx940::acc233, output_vec_len ); + case 1002: return makeRegisterExpression(amdgpu_gfx940::acc234, output_vec_len ); + case 1003: return makeRegisterExpression(amdgpu_gfx940::acc235, output_vec_len ); + case 1004: return makeRegisterExpression(amdgpu_gfx940::acc236, output_vec_len ); + case 1005: return makeRegisterExpression(amdgpu_gfx940::acc237, output_vec_len ); + case 1006: return makeRegisterExpression(amdgpu_gfx940::acc238, output_vec_len ); + case 1007: return makeRegisterExpression(amdgpu_gfx940::acc239, output_vec_len ); + case 1008: return makeRegisterExpression(amdgpu_gfx940::acc240, output_vec_len ); + case 1009: return makeRegisterExpression(amdgpu_gfx940::acc241, output_vec_len ); + case 1010: return makeRegisterExpression(amdgpu_gfx940::acc242, output_vec_len ); + case 1011: return makeRegisterExpression(amdgpu_gfx940::acc243, output_vec_len ); + case 1012: return makeRegisterExpression(amdgpu_gfx940::acc244, output_vec_len ); + case 1013: return makeRegisterExpression(amdgpu_gfx940::acc245, output_vec_len ); + case 1014: return makeRegisterExpression(amdgpu_gfx940::acc246, output_vec_len ); + case 1015: return makeRegisterExpression(amdgpu_gfx940::acc247, output_vec_len ); + case 1016: return makeRegisterExpression(amdgpu_gfx940::acc248, output_vec_len ); + case 1017: return makeRegisterExpression(amdgpu_gfx940::acc249, output_vec_len ); + case 1018: return makeRegisterExpression(amdgpu_gfx940::acc250, output_vec_len ); + case 1019: return makeRegisterExpression(amdgpu_gfx940::acc251, output_vec_len ); + case 1020: return makeRegisterExpression(amdgpu_gfx940::acc252, output_vec_len ); + case 1021: return makeRegisterExpression(amdgpu_gfx940::acc253, output_vec_len ); + case 1022: return makeRegisterExpression(amdgpu_gfx940::acc254, output_vec_len ); + case 1023: return makeRegisterExpression(amdgpu_gfx940::acc255, output_vec_len ); + default: return makeRegisterExpression(amdgpu_gfx940::invalid); + } + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx940::decodeOPR_SRC_NOLDS(uint64_t input, uint32_t output_vec_len) + { + switch (input) { + case 0: return makeRegisterExpression(amdgpu_gfx940::s0, output_vec_len ); + case 1: return makeRegisterExpression(amdgpu_gfx940::s1, output_vec_len ); + case 2: return makeRegisterExpression(amdgpu_gfx940::s2, output_vec_len ); + case 3: return makeRegisterExpression(amdgpu_gfx940::s3, output_vec_len ); + case 4: return makeRegisterExpression(amdgpu_gfx940::s4, output_vec_len ); + case 5: return makeRegisterExpression(amdgpu_gfx940::s5, output_vec_len ); + case 6: return makeRegisterExpression(amdgpu_gfx940::s6, output_vec_len ); + case 7: return makeRegisterExpression(amdgpu_gfx940::s7, output_vec_len ); + case 8: return makeRegisterExpression(amdgpu_gfx940::s8, output_vec_len ); + case 9: return makeRegisterExpression(amdgpu_gfx940::s9, output_vec_len ); + case 10: return makeRegisterExpression(amdgpu_gfx940::s10, output_vec_len ); + case 11: return makeRegisterExpression(amdgpu_gfx940::s11, output_vec_len ); + case 12: return makeRegisterExpression(amdgpu_gfx940::s12, output_vec_len ); + case 13: return makeRegisterExpression(amdgpu_gfx940::s13, output_vec_len ); + case 14: return makeRegisterExpression(amdgpu_gfx940::s14, output_vec_len ); + case 15: return makeRegisterExpression(amdgpu_gfx940::s15, output_vec_len ); + case 16: return makeRegisterExpression(amdgpu_gfx940::s16, output_vec_len ); + case 17: return makeRegisterExpression(amdgpu_gfx940::s17, output_vec_len ); + case 18: return makeRegisterExpression(amdgpu_gfx940::s18, output_vec_len ); + case 19: return makeRegisterExpression(amdgpu_gfx940::s19, output_vec_len ); + case 20: return makeRegisterExpression(amdgpu_gfx940::s20, output_vec_len ); + case 21: return makeRegisterExpression(amdgpu_gfx940::s21, output_vec_len ); + case 22: return makeRegisterExpression(amdgpu_gfx940::s22, output_vec_len ); + case 23: return makeRegisterExpression(amdgpu_gfx940::s23, output_vec_len ); + case 24: return makeRegisterExpression(amdgpu_gfx940::s24, output_vec_len ); + case 25: return makeRegisterExpression(amdgpu_gfx940::s25, output_vec_len ); + case 26: return makeRegisterExpression(amdgpu_gfx940::s26, output_vec_len ); + case 27: return makeRegisterExpression(amdgpu_gfx940::s27, output_vec_len ); + case 28: return makeRegisterExpression(amdgpu_gfx940::s28, output_vec_len ); + case 29: return makeRegisterExpression(amdgpu_gfx940::s29, output_vec_len ); + case 30: return makeRegisterExpression(amdgpu_gfx940::s30, output_vec_len ); + case 31: return makeRegisterExpression(amdgpu_gfx940::s31, output_vec_len ); + case 32: return makeRegisterExpression(amdgpu_gfx940::s32, output_vec_len ); + case 33: return makeRegisterExpression(amdgpu_gfx940::s33, output_vec_len ); + case 34: return makeRegisterExpression(amdgpu_gfx940::s34, output_vec_len ); + case 35: return makeRegisterExpression(amdgpu_gfx940::s35, output_vec_len ); + case 36: return makeRegisterExpression(amdgpu_gfx940::s36, output_vec_len ); + case 37: return makeRegisterExpression(amdgpu_gfx940::s37, output_vec_len ); + case 38: return makeRegisterExpression(amdgpu_gfx940::s38, output_vec_len ); + case 39: return makeRegisterExpression(amdgpu_gfx940::s39, output_vec_len ); + case 40: return makeRegisterExpression(amdgpu_gfx940::s40, output_vec_len ); + case 41: return makeRegisterExpression(amdgpu_gfx940::s41, output_vec_len ); + case 42: return makeRegisterExpression(amdgpu_gfx940::s42, output_vec_len ); + case 43: return makeRegisterExpression(amdgpu_gfx940::s43, output_vec_len ); + case 44: return makeRegisterExpression(amdgpu_gfx940::s44, output_vec_len ); + case 45: return makeRegisterExpression(amdgpu_gfx940::s45, output_vec_len ); + case 46: return makeRegisterExpression(amdgpu_gfx940::s46, output_vec_len ); + case 47: return makeRegisterExpression(amdgpu_gfx940::s47, output_vec_len ); + case 48: return makeRegisterExpression(amdgpu_gfx940::s48, output_vec_len ); + case 49: return makeRegisterExpression(amdgpu_gfx940::s49, output_vec_len ); + case 50: return makeRegisterExpression(amdgpu_gfx940::s50, output_vec_len ); + case 51: return makeRegisterExpression(amdgpu_gfx940::s51, output_vec_len ); + case 52: return makeRegisterExpression(amdgpu_gfx940::s52, output_vec_len ); + case 53: return makeRegisterExpression(amdgpu_gfx940::s53, output_vec_len ); + case 54: return makeRegisterExpression(amdgpu_gfx940::s54, output_vec_len ); + case 55: return makeRegisterExpression(amdgpu_gfx940::s55, output_vec_len ); + case 56: return makeRegisterExpression(amdgpu_gfx940::s56, output_vec_len ); + case 57: return makeRegisterExpression(amdgpu_gfx940::s57, output_vec_len ); + case 58: return makeRegisterExpression(amdgpu_gfx940::s58, output_vec_len ); + case 59: return makeRegisterExpression(amdgpu_gfx940::s59, output_vec_len ); + case 60: return makeRegisterExpression(amdgpu_gfx940::s60, output_vec_len ); + case 61: return makeRegisterExpression(amdgpu_gfx940::s61, output_vec_len ); + case 62: return makeRegisterExpression(amdgpu_gfx940::s62, output_vec_len ); + case 63: return makeRegisterExpression(amdgpu_gfx940::s63, output_vec_len ); + case 64: return makeRegisterExpression(amdgpu_gfx940::s64, output_vec_len ); + case 65: return makeRegisterExpression(amdgpu_gfx940::s65, output_vec_len ); + case 66: return makeRegisterExpression(amdgpu_gfx940::s66, output_vec_len ); + case 67: return makeRegisterExpression(amdgpu_gfx940::s67, output_vec_len ); + case 68: return makeRegisterExpression(amdgpu_gfx940::s68, output_vec_len ); + case 69: return makeRegisterExpression(amdgpu_gfx940::s69, output_vec_len ); + case 70: return makeRegisterExpression(amdgpu_gfx940::s70, output_vec_len ); + case 71: return makeRegisterExpression(amdgpu_gfx940::s71, output_vec_len ); + case 72: return makeRegisterExpression(amdgpu_gfx940::s72, output_vec_len ); + case 73: return makeRegisterExpression(amdgpu_gfx940::s73, output_vec_len ); + case 74: return makeRegisterExpression(amdgpu_gfx940::s74, output_vec_len ); + case 75: return makeRegisterExpression(amdgpu_gfx940::s75, output_vec_len ); + case 76: return makeRegisterExpression(amdgpu_gfx940::s76, output_vec_len ); + case 77: return makeRegisterExpression(amdgpu_gfx940::s77, output_vec_len ); + case 78: return makeRegisterExpression(amdgpu_gfx940::s78, output_vec_len ); + case 79: return makeRegisterExpression(amdgpu_gfx940::s79, output_vec_len ); + case 80: return makeRegisterExpression(amdgpu_gfx940::s80, output_vec_len ); + case 81: return makeRegisterExpression(amdgpu_gfx940::s81, output_vec_len ); + case 82: return makeRegisterExpression(amdgpu_gfx940::s82, output_vec_len ); + case 83: return makeRegisterExpression(amdgpu_gfx940::s83, output_vec_len ); + case 84: return makeRegisterExpression(amdgpu_gfx940::s84, output_vec_len ); + case 85: return makeRegisterExpression(amdgpu_gfx940::s85, output_vec_len ); + case 86: return makeRegisterExpression(amdgpu_gfx940::s86, output_vec_len ); + case 87: return makeRegisterExpression(amdgpu_gfx940::s87, output_vec_len ); + case 88: return makeRegisterExpression(amdgpu_gfx940::s88, output_vec_len ); + case 89: return makeRegisterExpression(amdgpu_gfx940::s89, output_vec_len ); + case 90: return makeRegisterExpression(amdgpu_gfx940::s90, output_vec_len ); + case 91: return makeRegisterExpression(amdgpu_gfx940::s91, output_vec_len ); + case 92: return makeRegisterExpression(amdgpu_gfx940::s92, output_vec_len ); + case 93: return makeRegisterExpression(amdgpu_gfx940::s93, output_vec_len ); + case 94: return makeRegisterExpression(amdgpu_gfx940::s94, output_vec_len ); + case 95: return makeRegisterExpression(amdgpu_gfx940::s95, output_vec_len ); + case 96: return makeRegisterExpression(amdgpu_gfx940::s96, output_vec_len ); + case 97: return makeRegisterExpression(amdgpu_gfx940::s97, output_vec_len ); + case 98: return makeRegisterExpression(amdgpu_gfx940::s98, output_vec_len ); + case 99: return makeRegisterExpression(amdgpu_gfx940::s99, output_vec_len ); + case 100: return makeRegisterExpression(amdgpu_gfx940::s100, output_vec_len ); + case 101: return makeRegisterExpression(amdgpu_gfx940::s101, output_vec_len ); + case 104: return makeRegisterExpression(amdgpu_gfx940::xnack_mask_lo, output_vec_len ); + case 105: return makeRegisterExpression(amdgpu_gfx940::xnack_mask_hi, output_vec_len ); + case 102: return makeRegisterExpression(amdgpu_gfx940::flat_scratch_lo, output_vec_len ); + case 103: return makeRegisterExpression(amdgpu_gfx940::flat_scratch_hi, output_vec_len ); + case 108: return makeRegisterExpression(amdgpu_gfx940::ttmp0, output_vec_len ); + case 109: return makeRegisterExpression(amdgpu_gfx940::ttmp1, output_vec_len ); + case 110: return makeRegisterExpression(amdgpu_gfx940::ttmp2, output_vec_len ); + case 111: return makeRegisterExpression(amdgpu_gfx940::ttmp3, output_vec_len ); + case 112: return makeRegisterExpression(amdgpu_gfx940::ttmp4, output_vec_len ); + case 113: return makeRegisterExpression(amdgpu_gfx940::ttmp5, output_vec_len ); + case 114: return makeRegisterExpression(amdgpu_gfx940::ttmp6, output_vec_len ); + case 115: return makeRegisterExpression(amdgpu_gfx940::ttmp7, output_vec_len ); + case 116: return makeRegisterExpression(amdgpu_gfx940::ttmp8, output_vec_len ); + case 117: return makeRegisterExpression(amdgpu_gfx940::ttmp9, output_vec_len ); + case 118: return makeRegisterExpression(amdgpu_gfx940::ttmp10, output_vec_len ); + case 119: return makeRegisterExpression(amdgpu_gfx940::ttmp11, output_vec_len ); + case 120: return makeRegisterExpression(amdgpu_gfx940::ttmp12, output_vec_len ); + case 121: return makeRegisterExpression(amdgpu_gfx940::ttmp13, output_vec_len ); + case 122: return makeRegisterExpression(amdgpu_gfx940::ttmp14, output_vec_len ); + case 123: return makeRegisterExpression(amdgpu_gfx940::ttmp15, output_vec_len ); + case 106: return makeRegisterExpression(amdgpu_gfx940::vcc_lo, output_vec_len ); + case 107: return makeRegisterExpression(amdgpu_gfx940::vcc_hi, output_vec_len ); + case 124: return makeRegisterExpression(amdgpu_gfx940::m0, output_vec_len ); + case 126: return makeRegisterExpression(amdgpu_gfx940::exec_lo, output_vec_len ); + case 127: return makeRegisterExpression(amdgpu_gfx940::exec_hi, output_vec_len ); + case 128: return Immediate::makeImmediate(Result(u32, 0)); + case 129: return Immediate::makeImmediate(Result(u32, 1)); + case 130: return Immediate::makeImmediate(Result(u32, 2)); + case 131: return Immediate::makeImmediate(Result(u32, 3)); + case 132: return Immediate::makeImmediate(Result(u32, 4)); + case 133: return Immediate::makeImmediate(Result(u32, 5)); + case 134: return Immediate::makeImmediate(Result(u32, 6)); + case 135: return Immediate::makeImmediate(Result(u32, 7)); + case 136: return Immediate::makeImmediate(Result(u32, 8)); + case 137: return Immediate::makeImmediate(Result(u32, 9)); + case 138: return Immediate::makeImmediate(Result(u32, 10)); + case 139: return Immediate::makeImmediate(Result(u32, 11)); + case 140: return Immediate::makeImmediate(Result(u32, 12)); + case 141: return Immediate::makeImmediate(Result(u32, 13)); + case 142: return Immediate::makeImmediate(Result(u32, 14)); + case 143: return Immediate::makeImmediate(Result(u32, 15)); + case 144: return Immediate::makeImmediate(Result(u32, 16)); + case 145: return Immediate::makeImmediate(Result(u32, 17)); + case 146: return Immediate::makeImmediate(Result(u32, 18)); + case 147: return Immediate::makeImmediate(Result(u32, 19)); + case 148: return Immediate::makeImmediate(Result(u32, 20)); + case 149: return Immediate::makeImmediate(Result(u32, 21)); + case 150: return Immediate::makeImmediate(Result(u32, 22)); + case 151: return Immediate::makeImmediate(Result(u32, 23)); + case 152: return Immediate::makeImmediate(Result(u32, 24)); + case 153: return Immediate::makeImmediate(Result(u32, 25)); + case 154: return Immediate::makeImmediate(Result(u32, 26)); + case 155: return Immediate::makeImmediate(Result(u32, 27)); + case 156: return Immediate::makeImmediate(Result(u32, 28)); + case 157: return Immediate::makeImmediate(Result(u32, 29)); + case 158: return Immediate::makeImmediate(Result(u32, 30)); + case 159: return Immediate::makeImmediate(Result(u32, 31)); + case 160: return Immediate::makeImmediate(Result(u32, 32)); + case 161: return Immediate::makeImmediate(Result(u32, 33)); + case 162: return Immediate::makeImmediate(Result(u32, 34)); + case 163: return Immediate::makeImmediate(Result(u32, 35)); + case 164: return Immediate::makeImmediate(Result(u32, 36)); + case 165: return Immediate::makeImmediate(Result(u32, 37)); + case 166: return Immediate::makeImmediate(Result(u32, 38)); + case 167: return Immediate::makeImmediate(Result(u32, 39)); + case 168: return Immediate::makeImmediate(Result(u32, 40)); + case 169: return Immediate::makeImmediate(Result(u32, 41)); + case 170: return Immediate::makeImmediate(Result(u32, 42)); + case 171: return Immediate::makeImmediate(Result(u32, 43)); + case 172: return Immediate::makeImmediate(Result(u32, 44)); + case 173: return Immediate::makeImmediate(Result(u32, 45)); + case 174: return Immediate::makeImmediate(Result(u32, 46)); + case 175: return Immediate::makeImmediate(Result(u32, 47)); + case 176: return Immediate::makeImmediate(Result(u32, 48)); + case 177: return Immediate::makeImmediate(Result(u32, 49)); + case 178: return Immediate::makeImmediate(Result(u32, 50)); + case 179: return Immediate::makeImmediate(Result(u32, 51)); + case 180: return Immediate::makeImmediate(Result(u32, 52)); + case 181: return Immediate::makeImmediate(Result(u32, 53)); + case 182: return Immediate::makeImmediate(Result(u32, 54)); + case 183: return Immediate::makeImmediate(Result(u32, 55)); + case 184: return Immediate::makeImmediate(Result(u32, 56)); + case 185: return Immediate::makeImmediate(Result(u32, 57)); + case 186: return Immediate::makeImmediate(Result(u32, 58)); + case 187: return Immediate::makeImmediate(Result(u32, 59)); + case 188: return Immediate::makeImmediate(Result(u32, 60)); + case 189: return Immediate::makeImmediate(Result(u32, 61)); + case 190: return Immediate::makeImmediate(Result(u32, 62)); + case 191: return Immediate::makeImmediate(Result(u32, 63)); + case 192: return Immediate::makeImmediate(Result(u32, 64)); + case 193: return Immediate::makeImmediate(Result(u32, -1)); + case 194: return Immediate::makeImmediate(Result(u32, -2)); + case 195: return Immediate::makeImmediate(Result(u32, -3)); + case 196: return Immediate::makeImmediate(Result(u32, -4)); + case 197: return Immediate::makeImmediate(Result(u32, -5)); + case 198: return Immediate::makeImmediate(Result(u32, -6)); + case 199: return Immediate::makeImmediate(Result(u32, -7)); + case 200: return Immediate::makeImmediate(Result(u32, -8)); + case 201: return Immediate::makeImmediate(Result(u32, -9)); + case 202: return Immediate::makeImmediate(Result(u32, -10)); + case 203: return Immediate::makeImmediate(Result(u32, -11)); + case 204: return Immediate::makeImmediate(Result(u32, -12)); + case 205: return Immediate::makeImmediate(Result(u32, -13)); + case 206: return Immediate::makeImmediate(Result(u32, -14)); + case 207: return Immediate::makeImmediate(Result(u32, -15)); + case 208: return Immediate::makeImmediate(Result(u32, -16)); + case 240: return Immediate::makeImmediate(Result(sp_float, 0.5)); + case 241: return Immediate::makeImmediate(Result(sp_float, -0.5)); + case 242: return Immediate::makeImmediate(Result(sp_float, 1.0)); + case 243: return Immediate::makeImmediate(Result(sp_float, -1.0)); + case 244: return Immediate::makeImmediate(Result(sp_float, 2.0)); + case 245: return Immediate::makeImmediate(Result(sp_float, -2.0)); + case 246: return Immediate::makeImmediate(Result(sp_float, 4.0)); + case 247: return Immediate::makeImmediate(Result(sp_float, -4.0)); + case 248: return Immediate::makeImmediate(Result(sp_float, 0.15915494)); + case 251: return makeRegisterExpression(amdgpu_gfx940::src_vccz, output_vec_len ); + case 252: return makeRegisterExpression(amdgpu_gfx940::src_execz, output_vec_len ); + case 253: return makeRegisterExpression(amdgpu_gfx940::src_scc, output_vec_len ); + case 235: return makeRegisterExpression(amdgpu_gfx940::src_shared_base, output_vec_len ); + case 236: return makeRegisterExpression(amdgpu_gfx940::src_shared_limit, output_vec_len ); + case 237: return makeRegisterExpression(amdgpu_gfx940::src_private_base, output_vec_len ); + case 238: return makeRegisterExpression(amdgpu_gfx940::src_private_limit, output_vec_len ); + case 239: return makeRegisterExpression(amdgpu_gfx940::src_pops_exiting_wave_id, output_vec_len ); + case 256: return makeRegisterExpression(amdgpu_gfx940::v0, output_vec_len ); + case 257: return makeRegisterExpression(amdgpu_gfx940::v1, output_vec_len ); + case 258: return makeRegisterExpression(amdgpu_gfx940::v2, output_vec_len ); + case 259: return makeRegisterExpression(amdgpu_gfx940::v3, output_vec_len ); + case 260: return makeRegisterExpression(amdgpu_gfx940::v4, output_vec_len ); + case 261: return makeRegisterExpression(amdgpu_gfx940::v5, output_vec_len ); + case 262: return makeRegisterExpression(amdgpu_gfx940::v6, output_vec_len ); + case 263: return makeRegisterExpression(amdgpu_gfx940::v7, output_vec_len ); + case 264: return makeRegisterExpression(amdgpu_gfx940::v8, output_vec_len ); + case 265: return makeRegisterExpression(amdgpu_gfx940::v9, output_vec_len ); + case 266: return makeRegisterExpression(amdgpu_gfx940::v10, output_vec_len ); + case 267: return makeRegisterExpression(amdgpu_gfx940::v11, output_vec_len ); + case 268: return makeRegisterExpression(amdgpu_gfx940::v12, output_vec_len ); + case 269: return makeRegisterExpression(amdgpu_gfx940::v13, output_vec_len ); + case 270: return makeRegisterExpression(amdgpu_gfx940::v14, output_vec_len ); + case 271: return makeRegisterExpression(amdgpu_gfx940::v15, output_vec_len ); + case 272: return makeRegisterExpression(amdgpu_gfx940::v16, output_vec_len ); + case 273: return makeRegisterExpression(amdgpu_gfx940::v17, output_vec_len ); + case 274: return makeRegisterExpression(amdgpu_gfx940::v18, output_vec_len ); + case 275: return makeRegisterExpression(amdgpu_gfx940::v19, output_vec_len ); + case 276: return makeRegisterExpression(amdgpu_gfx940::v20, output_vec_len ); + case 277: return makeRegisterExpression(amdgpu_gfx940::v21, output_vec_len ); + case 278: return makeRegisterExpression(amdgpu_gfx940::v22, output_vec_len ); + case 279: return makeRegisterExpression(amdgpu_gfx940::v23, output_vec_len ); + case 280: return makeRegisterExpression(amdgpu_gfx940::v24, output_vec_len ); + case 281: return makeRegisterExpression(amdgpu_gfx940::v25, output_vec_len ); + case 282: return makeRegisterExpression(amdgpu_gfx940::v26, output_vec_len ); + case 283: return makeRegisterExpression(amdgpu_gfx940::v27, output_vec_len ); + case 284: return makeRegisterExpression(amdgpu_gfx940::v28, output_vec_len ); + case 285: return makeRegisterExpression(amdgpu_gfx940::v29, output_vec_len ); + case 286: return makeRegisterExpression(amdgpu_gfx940::v30, output_vec_len ); + case 287: return makeRegisterExpression(amdgpu_gfx940::v31, output_vec_len ); + case 288: return makeRegisterExpression(amdgpu_gfx940::v32, output_vec_len ); + case 289: return makeRegisterExpression(amdgpu_gfx940::v33, output_vec_len ); + case 290: return makeRegisterExpression(amdgpu_gfx940::v34, output_vec_len ); + case 291: return makeRegisterExpression(amdgpu_gfx940::v35, output_vec_len ); + case 292: return makeRegisterExpression(amdgpu_gfx940::v36, output_vec_len ); + case 293: return makeRegisterExpression(amdgpu_gfx940::v37, output_vec_len ); + case 294: return makeRegisterExpression(amdgpu_gfx940::v38, output_vec_len ); + case 295: return makeRegisterExpression(amdgpu_gfx940::v39, output_vec_len ); + case 296: return makeRegisterExpression(amdgpu_gfx940::v40, output_vec_len ); + case 297: return makeRegisterExpression(amdgpu_gfx940::v41, output_vec_len ); + case 298: return makeRegisterExpression(amdgpu_gfx940::v42, output_vec_len ); + case 299: return makeRegisterExpression(amdgpu_gfx940::v43, output_vec_len ); + case 300: return makeRegisterExpression(amdgpu_gfx940::v44, output_vec_len ); + case 301: return makeRegisterExpression(amdgpu_gfx940::v45, output_vec_len ); + case 302: return makeRegisterExpression(amdgpu_gfx940::v46, output_vec_len ); + case 303: return makeRegisterExpression(amdgpu_gfx940::v47, output_vec_len ); + case 304: return makeRegisterExpression(amdgpu_gfx940::v48, output_vec_len ); + case 305: return makeRegisterExpression(amdgpu_gfx940::v49, output_vec_len ); + case 306: return makeRegisterExpression(amdgpu_gfx940::v50, output_vec_len ); + case 307: return makeRegisterExpression(amdgpu_gfx940::v51, output_vec_len ); + case 308: return makeRegisterExpression(amdgpu_gfx940::v52, output_vec_len ); + case 309: return makeRegisterExpression(amdgpu_gfx940::v53, output_vec_len ); + case 310: return makeRegisterExpression(amdgpu_gfx940::v54, output_vec_len ); + case 311: return makeRegisterExpression(amdgpu_gfx940::v55, output_vec_len ); + case 312: return makeRegisterExpression(amdgpu_gfx940::v56, output_vec_len ); + case 313: return makeRegisterExpression(amdgpu_gfx940::v57, output_vec_len ); + case 314: return makeRegisterExpression(amdgpu_gfx940::v58, output_vec_len ); + case 315: return makeRegisterExpression(amdgpu_gfx940::v59, output_vec_len ); + case 316: return makeRegisterExpression(amdgpu_gfx940::v60, output_vec_len ); + case 317: return makeRegisterExpression(amdgpu_gfx940::v61, output_vec_len ); + case 318: return makeRegisterExpression(amdgpu_gfx940::v62, output_vec_len ); + case 319: return makeRegisterExpression(amdgpu_gfx940::v63, output_vec_len ); + case 320: return makeRegisterExpression(amdgpu_gfx940::v64, output_vec_len ); + case 321: return makeRegisterExpression(amdgpu_gfx940::v65, output_vec_len ); + case 322: return makeRegisterExpression(amdgpu_gfx940::v66, output_vec_len ); + case 323: return makeRegisterExpression(amdgpu_gfx940::v67, output_vec_len ); + case 324: return makeRegisterExpression(amdgpu_gfx940::v68, output_vec_len ); + case 325: return makeRegisterExpression(amdgpu_gfx940::v69, output_vec_len ); + case 326: return makeRegisterExpression(amdgpu_gfx940::v70, output_vec_len ); + case 327: return makeRegisterExpression(amdgpu_gfx940::v71, output_vec_len ); + case 328: return makeRegisterExpression(amdgpu_gfx940::v72, output_vec_len ); + case 329: return makeRegisterExpression(amdgpu_gfx940::v73, output_vec_len ); + case 330: return makeRegisterExpression(amdgpu_gfx940::v74, output_vec_len ); + case 331: return makeRegisterExpression(amdgpu_gfx940::v75, output_vec_len ); + case 332: return makeRegisterExpression(amdgpu_gfx940::v76, output_vec_len ); + case 333: return makeRegisterExpression(amdgpu_gfx940::v77, output_vec_len ); + case 334: return makeRegisterExpression(amdgpu_gfx940::v78, output_vec_len ); + case 335: return makeRegisterExpression(amdgpu_gfx940::v79, output_vec_len ); + case 336: return makeRegisterExpression(amdgpu_gfx940::v80, output_vec_len ); + case 337: return makeRegisterExpression(amdgpu_gfx940::v81, output_vec_len ); + case 338: return makeRegisterExpression(amdgpu_gfx940::v82, output_vec_len ); + case 339: return makeRegisterExpression(amdgpu_gfx940::v83, output_vec_len ); + case 340: return makeRegisterExpression(amdgpu_gfx940::v84, output_vec_len ); + case 341: return makeRegisterExpression(amdgpu_gfx940::v85, output_vec_len ); + case 342: return makeRegisterExpression(amdgpu_gfx940::v86, output_vec_len ); + case 343: return makeRegisterExpression(amdgpu_gfx940::v87, output_vec_len ); + case 344: return makeRegisterExpression(amdgpu_gfx940::v88, output_vec_len ); + case 345: return makeRegisterExpression(amdgpu_gfx940::v89, output_vec_len ); + case 346: return makeRegisterExpression(amdgpu_gfx940::v90, output_vec_len ); + case 347: return makeRegisterExpression(amdgpu_gfx940::v91, output_vec_len ); + case 348: return makeRegisterExpression(amdgpu_gfx940::v92, output_vec_len ); + case 349: return makeRegisterExpression(amdgpu_gfx940::v93, output_vec_len ); + case 350: return makeRegisterExpression(amdgpu_gfx940::v94, output_vec_len ); + case 351: return makeRegisterExpression(amdgpu_gfx940::v95, output_vec_len ); + case 352: return makeRegisterExpression(amdgpu_gfx940::v96, output_vec_len ); + case 353: return makeRegisterExpression(amdgpu_gfx940::v97, output_vec_len ); + case 354: return makeRegisterExpression(amdgpu_gfx940::v98, output_vec_len ); + case 355: return makeRegisterExpression(amdgpu_gfx940::v99, output_vec_len ); + case 356: return makeRegisterExpression(amdgpu_gfx940::v100, output_vec_len ); + case 357: return makeRegisterExpression(amdgpu_gfx940::v101, output_vec_len ); + case 358: return makeRegisterExpression(amdgpu_gfx940::v102, output_vec_len ); + case 359: return makeRegisterExpression(amdgpu_gfx940::v103, output_vec_len ); + case 360: return makeRegisterExpression(amdgpu_gfx940::v104, output_vec_len ); + case 361: return makeRegisterExpression(amdgpu_gfx940::v105, output_vec_len ); + case 362: return makeRegisterExpression(amdgpu_gfx940::v106, output_vec_len ); + case 363: return makeRegisterExpression(amdgpu_gfx940::v107, output_vec_len ); + case 364: return makeRegisterExpression(amdgpu_gfx940::v108, output_vec_len ); + case 365: return makeRegisterExpression(amdgpu_gfx940::v109, output_vec_len ); + case 366: return makeRegisterExpression(amdgpu_gfx940::v110, output_vec_len ); + case 367: return makeRegisterExpression(amdgpu_gfx940::v111, output_vec_len ); + case 368: return makeRegisterExpression(amdgpu_gfx940::v112, output_vec_len ); + case 369: return makeRegisterExpression(amdgpu_gfx940::v113, output_vec_len ); + case 370: return makeRegisterExpression(amdgpu_gfx940::v114, output_vec_len ); + case 371: return makeRegisterExpression(amdgpu_gfx940::v115, output_vec_len ); + case 372: return makeRegisterExpression(amdgpu_gfx940::v116, output_vec_len ); + case 373: return makeRegisterExpression(amdgpu_gfx940::v117, output_vec_len ); + case 374: return makeRegisterExpression(amdgpu_gfx940::v118, output_vec_len ); + case 375: return makeRegisterExpression(amdgpu_gfx940::v119, output_vec_len ); + case 376: return makeRegisterExpression(amdgpu_gfx940::v120, output_vec_len ); + case 377: return makeRegisterExpression(amdgpu_gfx940::v121, output_vec_len ); + case 378: return makeRegisterExpression(amdgpu_gfx940::v122, output_vec_len ); + case 379: return makeRegisterExpression(amdgpu_gfx940::v123, output_vec_len ); + case 380: return makeRegisterExpression(amdgpu_gfx940::v124, output_vec_len ); + case 381: return makeRegisterExpression(amdgpu_gfx940::v125, output_vec_len ); + case 382: return makeRegisterExpression(amdgpu_gfx940::v126, output_vec_len ); + case 383: return makeRegisterExpression(amdgpu_gfx940::v127, output_vec_len ); + case 384: return makeRegisterExpression(amdgpu_gfx940::v128, output_vec_len ); + case 385: return makeRegisterExpression(amdgpu_gfx940::v129, output_vec_len ); + case 386: return makeRegisterExpression(amdgpu_gfx940::v130, output_vec_len ); + case 387: return makeRegisterExpression(amdgpu_gfx940::v131, output_vec_len ); + case 388: return makeRegisterExpression(amdgpu_gfx940::v132, output_vec_len ); + case 389: return makeRegisterExpression(amdgpu_gfx940::v133, output_vec_len ); + case 390: return makeRegisterExpression(amdgpu_gfx940::v134, output_vec_len ); + case 391: return makeRegisterExpression(amdgpu_gfx940::v135, output_vec_len ); + case 392: return makeRegisterExpression(amdgpu_gfx940::v136, output_vec_len ); + case 393: return makeRegisterExpression(amdgpu_gfx940::v137, output_vec_len ); + case 394: return makeRegisterExpression(amdgpu_gfx940::v138, output_vec_len ); + case 395: return makeRegisterExpression(amdgpu_gfx940::v139, output_vec_len ); + case 396: return makeRegisterExpression(amdgpu_gfx940::v140, output_vec_len ); + case 397: return makeRegisterExpression(amdgpu_gfx940::v141, output_vec_len ); + case 398: return makeRegisterExpression(amdgpu_gfx940::v142, output_vec_len ); + case 399: return makeRegisterExpression(amdgpu_gfx940::v143, output_vec_len ); + case 400: return makeRegisterExpression(amdgpu_gfx940::v144, output_vec_len ); + case 401: return makeRegisterExpression(amdgpu_gfx940::v145, output_vec_len ); + case 402: return makeRegisterExpression(amdgpu_gfx940::v146, output_vec_len ); + case 403: return makeRegisterExpression(amdgpu_gfx940::v147, output_vec_len ); + case 404: return makeRegisterExpression(amdgpu_gfx940::v148, output_vec_len ); + case 405: return makeRegisterExpression(amdgpu_gfx940::v149, output_vec_len ); + case 406: return makeRegisterExpression(amdgpu_gfx940::v150, output_vec_len ); + case 407: return makeRegisterExpression(amdgpu_gfx940::v151, output_vec_len ); + case 408: return makeRegisterExpression(amdgpu_gfx940::v152, output_vec_len ); + case 409: return makeRegisterExpression(amdgpu_gfx940::v153, output_vec_len ); + case 410: return makeRegisterExpression(amdgpu_gfx940::v154, output_vec_len ); + case 411: return makeRegisterExpression(amdgpu_gfx940::v155, output_vec_len ); + case 412: return makeRegisterExpression(amdgpu_gfx940::v156, output_vec_len ); + case 413: return makeRegisterExpression(amdgpu_gfx940::v157, output_vec_len ); + case 414: return makeRegisterExpression(amdgpu_gfx940::v158, output_vec_len ); + case 415: return makeRegisterExpression(amdgpu_gfx940::v159, output_vec_len ); + case 416: return makeRegisterExpression(amdgpu_gfx940::v160, output_vec_len ); + case 417: return makeRegisterExpression(amdgpu_gfx940::v161, output_vec_len ); + case 418: return makeRegisterExpression(amdgpu_gfx940::v162, output_vec_len ); + case 419: return makeRegisterExpression(amdgpu_gfx940::v163, output_vec_len ); + case 420: return makeRegisterExpression(amdgpu_gfx940::v164, output_vec_len ); + case 421: return makeRegisterExpression(amdgpu_gfx940::v165, output_vec_len ); + case 422: return makeRegisterExpression(amdgpu_gfx940::v166, output_vec_len ); + case 423: return makeRegisterExpression(amdgpu_gfx940::v167, output_vec_len ); + case 424: return makeRegisterExpression(amdgpu_gfx940::v168, output_vec_len ); + case 425: return makeRegisterExpression(amdgpu_gfx940::v169, output_vec_len ); + case 426: return makeRegisterExpression(amdgpu_gfx940::v170, output_vec_len ); + case 427: return makeRegisterExpression(amdgpu_gfx940::v171, output_vec_len ); + case 428: return makeRegisterExpression(amdgpu_gfx940::v172, output_vec_len ); + case 429: return makeRegisterExpression(amdgpu_gfx940::v173, output_vec_len ); + case 430: return makeRegisterExpression(amdgpu_gfx940::v174, output_vec_len ); + case 431: return makeRegisterExpression(amdgpu_gfx940::v175, output_vec_len ); + case 432: return makeRegisterExpression(amdgpu_gfx940::v176, output_vec_len ); + case 433: return makeRegisterExpression(amdgpu_gfx940::v177, output_vec_len ); + case 434: return makeRegisterExpression(amdgpu_gfx940::v178, output_vec_len ); + case 435: return makeRegisterExpression(amdgpu_gfx940::v179, output_vec_len ); + case 436: return makeRegisterExpression(amdgpu_gfx940::v180, output_vec_len ); + case 437: return makeRegisterExpression(amdgpu_gfx940::v181, output_vec_len ); + case 438: return makeRegisterExpression(amdgpu_gfx940::v182, output_vec_len ); + case 439: return makeRegisterExpression(amdgpu_gfx940::v183, output_vec_len ); + case 440: return makeRegisterExpression(amdgpu_gfx940::v184, output_vec_len ); + case 441: return makeRegisterExpression(amdgpu_gfx940::v185, output_vec_len ); + case 442: return makeRegisterExpression(amdgpu_gfx940::v186, output_vec_len ); + case 443: return makeRegisterExpression(amdgpu_gfx940::v187, output_vec_len ); + case 444: return makeRegisterExpression(amdgpu_gfx940::v188, output_vec_len ); + case 445: return makeRegisterExpression(amdgpu_gfx940::v189, output_vec_len ); + case 446: return makeRegisterExpression(amdgpu_gfx940::v190, output_vec_len ); + case 447: return makeRegisterExpression(amdgpu_gfx940::v191, output_vec_len ); + case 448: return makeRegisterExpression(amdgpu_gfx940::v192, output_vec_len ); + case 449: return makeRegisterExpression(amdgpu_gfx940::v193, output_vec_len ); + case 450: return makeRegisterExpression(amdgpu_gfx940::v194, output_vec_len ); + case 451: return makeRegisterExpression(amdgpu_gfx940::v195, output_vec_len ); + case 452: return makeRegisterExpression(amdgpu_gfx940::v196, output_vec_len ); + case 453: return makeRegisterExpression(amdgpu_gfx940::v197, output_vec_len ); + case 454: return makeRegisterExpression(amdgpu_gfx940::v198, output_vec_len ); + case 455: return makeRegisterExpression(amdgpu_gfx940::v199, output_vec_len ); + case 456: return makeRegisterExpression(amdgpu_gfx940::v200, output_vec_len ); + case 457: return makeRegisterExpression(amdgpu_gfx940::v201, output_vec_len ); + case 458: return makeRegisterExpression(amdgpu_gfx940::v202, output_vec_len ); + case 459: return makeRegisterExpression(amdgpu_gfx940::v203, output_vec_len ); + case 460: return makeRegisterExpression(amdgpu_gfx940::v204, output_vec_len ); + case 461: return makeRegisterExpression(amdgpu_gfx940::v205, output_vec_len ); + case 462: return makeRegisterExpression(amdgpu_gfx940::v206, output_vec_len ); + case 463: return makeRegisterExpression(amdgpu_gfx940::v207, output_vec_len ); + case 464: return makeRegisterExpression(amdgpu_gfx940::v208, output_vec_len ); + case 465: return makeRegisterExpression(amdgpu_gfx940::v209, output_vec_len ); + case 466: return makeRegisterExpression(amdgpu_gfx940::v210, output_vec_len ); + case 467: return makeRegisterExpression(amdgpu_gfx940::v211, output_vec_len ); + case 468: return makeRegisterExpression(amdgpu_gfx940::v212, output_vec_len ); + case 469: return makeRegisterExpression(amdgpu_gfx940::v213, output_vec_len ); + case 470: return makeRegisterExpression(amdgpu_gfx940::v214, output_vec_len ); + case 471: return makeRegisterExpression(amdgpu_gfx940::v215, output_vec_len ); + case 472: return makeRegisterExpression(amdgpu_gfx940::v216, output_vec_len ); + case 473: return makeRegisterExpression(amdgpu_gfx940::v217, output_vec_len ); + case 474: return makeRegisterExpression(amdgpu_gfx940::v218, output_vec_len ); + case 475: return makeRegisterExpression(amdgpu_gfx940::v219, output_vec_len ); + case 476: return makeRegisterExpression(amdgpu_gfx940::v220, output_vec_len ); + case 477: return makeRegisterExpression(amdgpu_gfx940::v221, output_vec_len ); + case 478: return makeRegisterExpression(amdgpu_gfx940::v222, output_vec_len ); + case 479: return makeRegisterExpression(amdgpu_gfx940::v223, output_vec_len ); + case 480: return makeRegisterExpression(amdgpu_gfx940::v224, output_vec_len ); + case 481: return makeRegisterExpression(amdgpu_gfx940::v225, output_vec_len ); + case 482: return makeRegisterExpression(amdgpu_gfx940::v226, output_vec_len ); + case 483: return makeRegisterExpression(amdgpu_gfx940::v227, output_vec_len ); + case 484: return makeRegisterExpression(amdgpu_gfx940::v228, output_vec_len ); + case 485: return makeRegisterExpression(amdgpu_gfx940::v229, output_vec_len ); + case 486: return makeRegisterExpression(amdgpu_gfx940::v230, output_vec_len ); + case 487: return makeRegisterExpression(amdgpu_gfx940::v231, output_vec_len ); + case 488: return makeRegisterExpression(amdgpu_gfx940::v232, output_vec_len ); + case 489: return makeRegisterExpression(amdgpu_gfx940::v233, output_vec_len ); + case 490: return makeRegisterExpression(amdgpu_gfx940::v234, output_vec_len ); + case 491: return makeRegisterExpression(amdgpu_gfx940::v235, output_vec_len ); + case 492: return makeRegisterExpression(amdgpu_gfx940::v236, output_vec_len ); + case 493: return makeRegisterExpression(amdgpu_gfx940::v237, output_vec_len ); + case 494: return makeRegisterExpression(amdgpu_gfx940::v238, output_vec_len ); + case 495: return makeRegisterExpression(amdgpu_gfx940::v239, output_vec_len ); + case 496: return makeRegisterExpression(amdgpu_gfx940::v240, output_vec_len ); + case 497: return makeRegisterExpression(amdgpu_gfx940::v241, output_vec_len ); + case 498: return makeRegisterExpression(amdgpu_gfx940::v242, output_vec_len ); + case 499: return makeRegisterExpression(amdgpu_gfx940::v243, output_vec_len ); + case 500: return makeRegisterExpression(amdgpu_gfx940::v244, output_vec_len ); + case 501: return makeRegisterExpression(amdgpu_gfx940::v245, output_vec_len ); + case 502: return makeRegisterExpression(amdgpu_gfx940::v246, output_vec_len ); + case 503: return makeRegisterExpression(amdgpu_gfx940::v247, output_vec_len ); + case 504: return makeRegisterExpression(amdgpu_gfx940::v248, output_vec_len ); + case 505: return makeRegisterExpression(amdgpu_gfx940::v249, output_vec_len ); + case 506: return makeRegisterExpression(amdgpu_gfx940::v250, output_vec_len ); + case 507: return makeRegisterExpression(amdgpu_gfx940::v251, output_vec_len ); + case 508: return makeRegisterExpression(amdgpu_gfx940::v252, output_vec_len ); + case 509: return makeRegisterExpression(amdgpu_gfx940::v253, output_vec_len ); + case 510: return makeRegisterExpression(amdgpu_gfx940::v254, output_vec_len ); + case 511: return makeRegisterExpression(amdgpu_gfx940::v255, output_vec_len ); + case 255: return Immediate::makeImmediate(Result(u32,decodeOPR_LITERAL())); + case 249 : return decodeOPR_SDWA(); + default: return makeRegisterExpression(amdgpu_gfx940::invalid); + } + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx940::decodeOPR_SRC_NOLIT(uint64_t input, uint32_t output_vec_len) + { + switch (input) { + case 0: return makeRegisterExpression(amdgpu_gfx940::s0, output_vec_len ); + case 1: return makeRegisterExpression(amdgpu_gfx940::s1, output_vec_len ); + case 2: return makeRegisterExpression(amdgpu_gfx940::s2, output_vec_len ); + case 3: return makeRegisterExpression(amdgpu_gfx940::s3, output_vec_len ); + case 4: return makeRegisterExpression(amdgpu_gfx940::s4, output_vec_len ); + case 5: return makeRegisterExpression(amdgpu_gfx940::s5, output_vec_len ); + case 6: return makeRegisterExpression(amdgpu_gfx940::s6, output_vec_len ); + case 7: return makeRegisterExpression(amdgpu_gfx940::s7, output_vec_len ); + case 8: return makeRegisterExpression(amdgpu_gfx940::s8, output_vec_len ); + case 9: return makeRegisterExpression(amdgpu_gfx940::s9, output_vec_len ); + case 10: return makeRegisterExpression(amdgpu_gfx940::s10, output_vec_len ); + case 11: return makeRegisterExpression(amdgpu_gfx940::s11, output_vec_len ); + case 12: return makeRegisterExpression(amdgpu_gfx940::s12, output_vec_len ); + case 13: return makeRegisterExpression(amdgpu_gfx940::s13, output_vec_len ); + case 14: return makeRegisterExpression(amdgpu_gfx940::s14, output_vec_len ); + case 15: return makeRegisterExpression(amdgpu_gfx940::s15, output_vec_len ); + case 16: return makeRegisterExpression(amdgpu_gfx940::s16, output_vec_len ); + case 17: return makeRegisterExpression(amdgpu_gfx940::s17, output_vec_len ); + case 18: return makeRegisterExpression(amdgpu_gfx940::s18, output_vec_len ); + case 19: return makeRegisterExpression(amdgpu_gfx940::s19, output_vec_len ); + case 20: return makeRegisterExpression(amdgpu_gfx940::s20, output_vec_len ); + case 21: return makeRegisterExpression(amdgpu_gfx940::s21, output_vec_len ); + case 22: return makeRegisterExpression(amdgpu_gfx940::s22, output_vec_len ); + case 23: return makeRegisterExpression(amdgpu_gfx940::s23, output_vec_len ); + case 24: return makeRegisterExpression(amdgpu_gfx940::s24, output_vec_len ); + case 25: return makeRegisterExpression(amdgpu_gfx940::s25, output_vec_len ); + case 26: return makeRegisterExpression(amdgpu_gfx940::s26, output_vec_len ); + case 27: return makeRegisterExpression(amdgpu_gfx940::s27, output_vec_len ); + case 28: return makeRegisterExpression(amdgpu_gfx940::s28, output_vec_len ); + case 29: return makeRegisterExpression(amdgpu_gfx940::s29, output_vec_len ); + case 30: return makeRegisterExpression(amdgpu_gfx940::s30, output_vec_len ); + case 31: return makeRegisterExpression(amdgpu_gfx940::s31, output_vec_len ); + case 32: return makeRegisterExpression(amdgpu_gfx940::s32, output_vec_len ); + case 33: return makeRegisterExpression(amdgpu_gfx940::s33, output_vec_len ); + case 34: return makeRegisterExpression(amdgpu_gfx940::s34, output_vec_len ); + case 35: return makeRegisterExpression(amdgpu_gfx940::s35, output_vec_len ); + case 36: return makeRegisterExpression(amdgpu_gfx940::s36, output_vec_len ); + case 37: return makeRegisterExpression(amdgpu_gfx940::s37, output_vec_len ); + case 38: return makeRegisterExpression(amdgpu_gfx940::s38, output_vec_len ); + case 39: return makeRegisterExpression(amdgpu_gfx940::s39, output_vec_len ); + case 40: return makeRegisterExpression(amdgpu_gfx940::s40, output_vec_len ); + case 41: return makeRegisterExpression(amdgpu_gfx940::s41, output_vec_len ); + case 42: return makeRegisterExpression(amdgpu_gfx940::s42, output_vec_len ); + case 43: return makeRegisterExpression(amdgpu_gfx940::s43, output_vec_len ); + case 44: return makeRegisterExpression(amdgpu_gfx940::s44, output_vec_len ); + case 45: return makeRegisterExpression(amdgpu_gfx940::s45, output_vec_len ); + case 46: return makeRegisterExpression(amdgpu_gfx940::s46, output_vec_len ); + case 47: return makeRegisterExpression(amdgpu_gfx940::s47, output_vec_len ); + case 48: return makeRegisterExpression(amdgpu_gfx940::s48, output_vec_len ); + case 49: return makeRegisterExpression(amdgpu_gfx940::s49, output_vec_len ); + case 50: return makeRegisterExpression(amdgpu_gfx940::s50, output_vec_len ); + case 51: return makeRegisterExpression(amdgpu_gfx940::s51, output_vec_len ); + case 52: return makeRegisterExpression(amdgpu_gfx940::s52, output_vec_len ); + case 53: return makeRegisterExpression(amdgpu_gfx940::s53, output_vec_len ); + case 54: return makeRegisterExpression(amdgpu_gfx940::s54, output_vec_len ); + case 55: return makeRegisterExpression(amdgpu_gfx940::s55, output_vec_len ); + case 56: return makeRegisterExpression(amdgpu_gfx940::s56, output_vec_len ); + case 57: return makeRegisterExpression(amdgpu_gfx940::s57, output_vec_len ); + case 58: return makeRegisterExpression(amdgpu_gfx940::s58, output_vec_len ); + case 59: return makeRegisterExpression(amdgpu_gfx940::s59, output_vec_len ); + case 60: return makeRegisterExpression(amdgpu_gfx940::s60, output_vec_len ); + case 61: return makeRegisterExpression(amdgpu_gfx940::s61, output_vec_len ); + case 62: return makeRegisterExpression(amdgpu_gfx940::s62, output_vec_len ); + case 63: return makeRegisterExpression(amdgpu_gfx940::s63, output_vec_len ); + case 64: return makeRegisterExpression(amdgpu_gfx940::s64, output_vec_len ); + case 65: return makeRegisterExpression(amdgpu_gfx940::s65, output_vec_len ); + case 66: return makeRegisterExpression(amdgpu_gfx940::s66, output_vec_len ); + case 67: return makeRegisterExpression(amdgpu_gfx940::s67, output_vec_len ); + case 68: return makeRegisterExpression(amdgpu_gfx940::s68, output_vec_len ); + case 69: return makeRegisterExpression(amdgpu_gfx940::s69, output_vec_len ); + case 70: return makeRegisterExpression(amdgpu_gfx940::s70, output_vec_len ); + case 71: return makeRegisterExpression(amdgpu_gfx940::s71, output_vec_len ); + case 72: return makeRegisterExpression(amdgpu_gfx940::s72, output_vec_len ); + case 73: return makeRegisterExpression(amdgpu_gfx940::s73, output_vec_len ); + case 74: return makeRegisterExpression(amdgpu_gfx940::s74, output_vec_len ); + case 75: return makeRegisterExpression(amdgpu_gfx940::s75, output_vec_len ); + case 76: return makeRegisterExpression(amdgpu_gfx940::s76, output_vec_len ); + case 77: return makeRegisterExpression(amdgpu_gfx940::s77, output_vec_len ); + case 78: return makeRegisterExpression(amdgpu_gfx940::s78, output_vec_len ); + case 79: return makeRegisterExpression(amdgpu_gfx940::s79, output_vec_len ); + case 80: return makeRegisterExpression(amdgpu_gfx940::s80, output_vec_len ); + case 81: return makeRegisterExpression(amdgpu_gfx940::s81, output_vec_len ); + case 82: return makeRegisterExpression(amdgpu_gfx940::s82, output_vec_len ); + case 83: return makeRegisterExpression(amdgpu_gfx940::s83, output_vec_len ); + case 84: return makeRegisterExpression(amdgpu_gfx940::s84, output_vec_len ); + case 85: return makeRegisterExpression(amdgpu_gfx940::s85, output_vec_len ); + case 86: return makeRegisterExpression(amdgpu_gfx940::s86, output_vec_len ); + case 87: return makeRegisterExpression(amdgpu_gfx940::s87, output_vec_len ); + case 88: return makeRegisterExpression(amdgpu_gfx940::s88, output_vec_len ); + case 89: return makeRegisterExpression(amdgpu_gfx940::s89, output_vec_len ); + case 90: return makeRegisterExpression(amdgpu_gfx940::s90, output_vec_len ); + case 91: return makeRegisterExpression(amdgpu_gfx940::s91, output_vec_len ); + case 92: return makeRegisterExpression(amdgpu_gfx940::s92, output_vec_len ); + case 93: return makeRegisterExpression(amdgpu_gfx940::s93, output_vec_len ); + case 94: return makeRegisterExpression(amdgpu_gfx940::s94, output_vec_len ); + case 95: return makeRegisterExpression(amdgpu_gfx940::s95, output_vec_len ); + case 96: return makeRegisterExpression(amdgpu_gfx940::s96, output_vec_len ); + case 97: return makeRegisterExpression(amdgpu_gfx940::s97, output_vec_len ); + case 98: return makeRegisterExpression(amdgpu_gfx940::s98, output_vec_len ); + case 99: return makeRegisterExpression(amdgpu_gfx940::s99, output_vec_len ); + case 100: return makeRegisterExpression(amdgpu_gfx940::s100, output_vec_len ); + case 101: return makeRegisterExpression(amdgpu_gfx940::s101, output_vec_len ); + case 104: return makeRegisterExpression(amdgpu_gfx940::xnack_mask_lo, output_vec_len ); + case 105: return makeRegisterExpression(amdgpu_gfx940::xnack_mask_hi, output_vec_len ); + case 102: return makeRegisterExpression(amdgpu_gfx940::flat_scratch_lo, output_vec_len ); + case 103: return makeRegisterExpression(amdgpu_gfx940::flat_scratch_hi, output_vec_len ); + case 108: return makeRegisterExpression(amdgpu_gfx940::ttmp0, output_vec_len ); + case 109: return makeRegisterExpression(amdgpu_gfx940::ttmp1, output_vec_len ); + case 110: return makeRegisterExpression(amdgpu_gfx940::ttmp2, output_vec_len ); + case 111: return makeRegisterExpression(amdgpu_gfx940::ttmp3, output_vec_len ); + case 112: return makeRegisterExpression(amdgpu_gfx940::ttmp4, output_vec_len ); + case 113: return makeRegisterExpression(amdgpu_gfx940::ttmp5, output_vec_len ); + case 114: return makeRegisterExpression(amdgpu_gfx940::ttmp6, output_vec_len ); + case 115: return makeRegisterExpression(amdgpu_gfx940::ttmp7, output_vec_len ); + case 116: return makeRegisterExpression(amdgpu_gfx940::ttmp8, output_vec_len ); + case 117: return makeRegisterExpression(amdgpu_gfx940::ttmp9, output_vec_len ); + case 118: return makeRegisterExpression(amdgpu_gfx940::ttmp10, output_vec_len ); + case 119: return makeRegisterExpression(amdgpu_gfx940::ttmp11, output_vec_len ); + case 120: return makeRegisterExpression(amdgpu_gfx940::ttmp12, output_vec_len ); + case 121: return makeRegisterExpression(amdgpu_gfx940::ttmp13, output_vec_len ); + case 122: return makeRegisterExpression(amdgpu_gfx940::ttmp14, output_vec_len ); + case 123: return makeRegisterExpression(amdgpu_gfx940::ttmp15, output_vec_len ); + case 106: return makeRegisterExpression(amdgpu_gfx940::vcc_lo, output_vec_len ); + case 107: return makeRegisterExpression(amdgpu_gfx940::vcc_hi, output_vec_len ); + case 124: return makeRegisterExpression(amdgpu_gfx940::m0, output_vec_len ); + case 126: return makeRegisterExpression(amdgpu_gfx940::exec_lo, output_vec_len ); + case 127: return makeRegisterExpression(amdgpu_gfx940::exec_hi, output_vec_len ); + case 128: return Immediate::makeImmediate(Result(u32, 0)); + case 129: return Immediate::makeImmediate(Result(u32, 1)); + case 130: return Immediate::makeImmediate(Result(u32, 2)); + case 131: return Immediate::makeImmediate(Result(u32, 3)); + case 132: return Immediate::makeImmediate(Result(u32, 4)); + case 133: return Immediate::makeImmediate(Result(u32, 5)); + case 134: return Immediate::makeImmediate(Result(u32, 6)); + case 135: return Immediate::makeImmediate(Result(u32, 7)); + case 136: return Immediate::makeImmediate(Result(u32, 8)); + case 137: return Immediate::makeImmediate(Result(u32, 9)); + case 138: return Immediate::makeImmediate(Result(u32, 10)); + case 139: return Immediate::makeImmediate(Result(u32, 11)); + case 140: return Immediate::makeImmediate(Result(u32, 12)); + case 141: return Immediate::makeImmediate(Result(u32, 13)); + case 142: return Immediate::makeImmediate(Result(u32, 14)); + case 143: return Immediate::makeImmediate(Result(u32, 15)); + case 144: return Immediate::makeImmediate(Result(u32, 16)); + case 145: return Immediate::makeImmediate(Result(u32, 17)); + case 146: return Immediate::makeImmediate(Result(u32, 18)); + case 147: return Immediate::makeImmediate(Result(u32, 19)); + case 148: return Immediate::makeImmediate(Result(u32, 20)); + case 149: return Immediate::makeImmediate(Result(u32, 21)); + case 150: return Immediate::makeImmediate(Result(u32, 22)); + case 151: return Immediate::makeImmediate(Result(u32, 23)); + case 152: return Immediate::makeImmediate(Result(u32, 24)); + case 153: return Immediate::makeImmediate(Result(u32, 25)); + case 154: return Immediate::makeImmediate(Result(u32, 26)); + case 155: return Immediate::makeImmediate(Result(u32, 27)); + case 156: return Immediate::makeImmediate(Result(u32, 28)); + case 157: return Immediate::makeImmediate(Result(u32, 29)); + case 158: return Immediate::makeImmediate(Result(u32, 30)); + case 159: return Immediate::makeImmediate(Result(u32, 31)); + case 160: return Immediate::makeImmediate(Result(u32, 32)); + case 161: return Immediate::makeImmediate(Result(u32, 33)); + case 162: return Immediate::makeImmediate(Result(u32, 34)); + case 163: return Immediate::makeImmediate(Result(u32, 35)); + case 164: return Immediate::makeImmediate(Result(u32, 36)); + case 165: return Immediate::makeImmediate(Result(u32, 37)); + case 166: return Immediate::makeImmediate(Result(u32, 38)); + case 167: return Immediate::makeImmediate(Result(u32, 39)); + case 168: return Immediate::makeImmediate(Result(u32, 40)); + case 169: return Immediate::makeImmediate(Result(u32, 41)); + case 170: return Immediate::makeImmediate(Result(u32, 42)); + case 171: return Immediate::makeImmediate(Result(u32, 43)); + case 172: return Immediate::makeImmediate(Result(u32, 44)); + case 173: return Immediate::makeImmediate(Result(u32, 45)); + case 174: return Immediate::makeImmediate(Result(u32, 46)); + case 175: return Immediate::makeImmediate(Result(u32, 47)); + case 176: return Immediate::makeImmediate(Result(u32, 48)); + case 177: return Immediate::makeImmediate(Result(u32, 49)); + case 178: return Immediate::makeImmediate(Result(u32, 50)); + case 179: return Immediate::makeImmediate(Result(u32, 51)); + case 180: return Immediate::makeImmediate(Result(u32, 52)); + case 181: return Immediate::makeImmediate(Result(u32, 53)); + case 182: return Immediate::makeImmediate(Result(u32, 54)); + case 183: return Immediate::makeImmediate(Result(u32, 55)); + case 184: return Immediate::makeImmediate(Result(u32, 56)); + case 185: return Immediate::makeImmediate(Result(u32, 57)); + case 186: return Immediate::makeImmediate(Result(u32, 58)); + case 187: return Immediate::makeImmediate(Result(u32, 59)); + case 188: return Immediate::makeImmediate(Result(u32, 60)); + case 189: return Immediate::makeImmediate(Result(u32, 61)); + case 190: return Immediate::makeImmediate(Result(u32, 62)); + case 191: return Immediate::makeImmediate(Result(u32, 63)); + case 192: return Immediate::makeImmediate(Result(u32, 64)); + case 193: return Immediate::makeImmediate(Result(u32, -1)); + case 194: return Immediate::makeImmediate(Result(u32, -2)); + case 195: return Immediate::makeImmediate(Result(u32, -3)); + case 196: return Immediate::makeImmediate(Result(u32, -4)); + case 197: return Immediate::makeImmediate(Result(u32, -5)); + case 198: return Immediate::makeImmediate(Result(u32, -6)); + case 199: return Immediate::makeImmediate(Result(u32, -7)); + case 200: return Immediate::makeImmediate(Result(u32, -8)); + case 201: return Immediate::makeImmediate(Result(u32, -9)); + case 202: return Immediate::makeImmediate(Result(u32, -10)); + case 203: return Immediate::makeImmediate(Result(u32, -11)); + case 204: return Immediate::makeImmediate(Result(u32, -12)); + case 205: return Immediate::makeImmediate(Result(u32, -13)); + case 206: return Immediate::makeImmediate(Result(u32, -14)); + case 207: return Immediate::makeImmediate(Result(u32, -15)); + case 208: return Immediate::makeImmediate(Result(u32, -16)); + case 240: return Immediate::makeImmediate(Result(sp_float, 0.5)); + case 241: return Immediate::makeImmediate(Result(sp_float, -0.5)); + case 242: return Immediate::makeImmediate(Result(sp_float, 1.0)); + case 243: return Immediate::makeImmediate(Result(sp_float, -1.0)); + case 244: return Immediate::makeImmediate(Result(sp_float, 2.0)); + case 245: return Immediate::makeImmediate(Result(sp_float, -2.0)); + case 246: return Immediate::makeImmediate(Result(sp_float, 4.0)); + case 247: return Immediate::makeImmediate(Result(sp_float, -4.0)); + case 248: return Immediate::makeImmediate(Result(sp_float, 0.15915494)); + case 251: return makeRegisterExpression(amdgpu_gfx940::src_vccz, output_vec_len ); + case 252: return makeRegisterExpression(amdgpu_gfx940::src_execz, output_vec_len ); + case 253: return makeRegisterExpression(amdgpu_gfx940::src_scc, output_vec_len ); + case 235: return makeRegisterExpression(amdgpu_gfx940::src_shared_base, output_vec_len ); + case 236: return makeRegisterExpression(amdgpu_gfx940::src_shared_limit, output_vec_len ); + case 237: return makeRegisterExpression(amdgpu_gfx940::src_private_base, output_vec_len ); + case 238: return makeRegisterExpression(amdgpu_gfx940::src_private_limit, output_vec_len ); + case 239: return makeRegisterExpression(amdgpu_gfx940::src_pops_exiting_wave_id, output_vec_len ); + case 256: return makeRegisterExpression(amdgpu_gfx940::v0, output_vec_len ); + case 257: return makeRegisterExpression(amdgpu_gfx940::v1, output_vec_len ); + case 258: return makeRegisterExpression(amdgpu_gfx940::v2, output_vec_len ); + case 259: return makeRegisterExpression(amdgpu_gfx940::v3, output_vec_len ); + case 260: return makeRegisterExpression(amdgpu_gfx940::v4, output_vec_len ); + case 261: return makeRegisterExpression(amdgpu_gfx940::v5, output_vec_len ); + case 262: return makeRegisterExpression(amdgpu_gfx940::v6, output_vec_len ); + case 263: return makeRegisterExpression(amdgpu_gfx940::v7, output_vec_len ); + case 264: return makeRegisterExpression(amdgpu_gfx940::v8, output_vec_len ); + case 265: return makeRegisterExpression(amdgpu_gfx940::v9, output_vec_len ); + case 266: return makeRegisterExpression(amdgpu_gfx940::v10, output_vec_len ); + case 267: return makeRegisterExpression(amdgpu_gfx940::v11, output_vec_len ); + case 268: return makeRegisterExpression(amdgpu_gfx940::v12, output_vec_len ); + case 269: return makeRegisterExpression(amdgpu_gfx940::v13, output_vec_len ); + case 270: return makeRegisterExpression(amdgpu_gfx940::v14, output_vec_len ); + case 271: return makeRegisterExpression(amdgpu_gfx940::v15, output_vec_len ); + case 272: return makeRegisterExpression(amdgpu_gfx940::v16, output_vec_len ); + case 273: return makeRegisterExpression(amdgpu_gfx940::v17, output_vec_len ); + case 274: return makeRegisterExpression(amdgpu_gfx940::v18, output_vec_len ); + case 275: return makeRegisterExpression(amdgpu_gfx940::v19, output_vec_len ); + case 276: return makeRegisterExpression(amdgpu_gfx940::v20, output_vec_len ); + case 277: return makeRegisterExpression(amdgpu_gfx940::v21, output_vec_len ); + case 278: return makeRegisterExpression(amdgpu_gfx940::v22, output_vec_len ); + case 279: return makeRegisterExpression(amdgpu_gfx940::v23, output_vec_len ); + case 280: return makeRegisterExpression(amdgpu_gfx940::v24, output_vec_len ); + case 281: return makeRegisterExpression(amdgpu_gfx940::v25, output_vec_len ); + case 282: return makeRegisterExpression(amdgpu_gfx940::v26, output_vec_len ); + case 283: return makeRegisterExpression(amdgpu_gfx940::v27, output_vec_len ); + case 284: return makeRegisterExpression(amdgpu_gfx940::v28, output_vec_len ); + case 285: return makeRegisterExpression(amdgpu_gfx940::v29, output_vec_len ); + case 286: return makeRegisterExpression(amdgpu_gfx940::v30, output_vec_len ); + case 287: return makeRegisterExpression(amdgpu_gfx940::v31, output_vec_len ); + case 288: return makeRegisterExpression(amdgpu_gfx940::v32, output_vec_len ); + case 289: return makeRegisterExpression(amdgpu_gfx940::v33, output_vec_len ); + case 290: return makeRegisterExpression(amdgpu_gfx940::v34, output_vec_len ); + case 291: return makeRegisterExpression(amdgpu_gfx940::v35, output_vec_len ); + case 292: return makeRegisterExpression(amdgpu_gfx940::v36, output_vec_len ); + case 293: return makeRegisterExpression(amdgpu_gfx940::v37, output_vec_len ); + case 294: return makeRegisterExpression(amdgpu_gfx940::v38, output_vec_len ); + case 295: return makeRegisterExpression(amdgpu_gfx940::v39, output_vec_len ); + case 296: return makeRegisterExpression(amdgpu_gfx940::v40, output_vec_len ); + case 297: return makeRegisterExpression(amdgpu_gfx940::v41, output_vec_len ); + case 298: return makeRegisterExpression(amdgpu_gfx940::v42, output_vec_len ); + case 299: return makeRegisterExpression(amdgpu_gfx940::v43, output_vec_len ); + case 300: return makeRegisterExpression(amdgpu_gfx940::v44, output_vec_len ); + case 301: return makeRegisterExpression(amdgpu_gfx940::v45, output_vec_len ); + case 302: return makeRegisterExpression(amdgpu_gfx940::v46, output_vec_len ); + case 303: return makeRegisterExpression(amdgpu_gfx940::v47, output_vec_len ); + case 304: return makeRegisterExpression(amdgpu_gfx940::v48, output_vec_len ); + case 305: return makeRegisterExpression(amdgpu_gfx940::v49, output_vec_len ); + case 306: return makeRegisterExpression(amdgpu_gfx940::v50, output_vec_len ); + case 307: return makeRegisterExpression(amdgpu_gfx940::v51, output_vec_len ); + case 308: return makeRegisterExpression(amdgpu_gfx940::v52, output_vec_len ); + case 309: return makeRegisterExpression(amdgpu_gfx940::v53, output_vec_len ); + case 310: return makeRegisterExpression(amdgpu_gfx940::v54, output_vec_len ); + case 311: return makeRegisterExpression(amdgpu_gfx940::v55, output_vec_len ); + case 312: return makeRegisterExpression(amdgpu_gfx940::v56, output_vec_len ); + case 313: return makeRegisterExpression(amdgpu_gfx940::v57, output_vec_len ); + case 314: return makeRegisterExpression(amdgpu_gfx940::v58, output_vec_len ); + case 315: return makeRegisterExpression(amdgpu_gfx940::v59, output_vec_len ); + case 316: return makeRegisterExpression(amdgpu_gfx940::v60, output_vec_len ); + case 317: return makeRegisterExpression(amdgpu_gfx940::v61, output_vec_len ); + case 318: return makeRegisterExpression(amdgpu_gfx940::v62, output_vec_len ); + case 319: return makeRegisterExpression(amdgpu_gfx940::v63, output_vec_len ); + case 320: return makeRegisterExpression(amdgpu_gfx940::v64, output_vec_len ); + case 321: return makeRegisterExpression(amdgpu_gfx940::v65, output_vec_len ); + case 322: return makeRegisterExpression(amdgpu_gfx940::v66, output_vec_len ); + case 323: return makeRegisterExpression(amdgpu_gfx940::v67, output_vec_len ); + case 324: return makeRegisterExpression(amdgpu_gfx940::v68, output_vec_len ); + case 325: return makeRegisterExpression(amdgpu_gfx940::v69, output_vec_len ); + case 326: return makeRegisterExpression(amdgpu_gfx940::v70, output_vec_len ); + case 327: return makeRegisterExpression(amdgpu_gfx940::v71, output_vec_len ); + case 328: return makeRegisterExpression(amdgpu_gfx940::v72, output_vec_len ); + case 329: return makeRegisterExpression(amdgpu_gfx940::v73, output_vec_len ); + case 330: return makeRegisterExpression(amdgpu_gfx940::v74, output_vec_len ); + case 331: return makeRegisterExpression(amdgpu_gfx940::v75, output_vec_len ); + case 332: return makeRegisterExpression(amdgpu_gfx940::v76, output_vec_len ); + case 333: return makeRegisterExpression(amdgpu_gfx940::v77, output_vec_len ); + case 334: return makeRegisterExpression(amdgpu_gfx940::v78, output_vec_len ); + case 335: return makeRegisterExpression(amdgpu_gfx940::v79, output_vec_len ); + case 336: return makeRegisterExpression(amdgpu_gfx940::v80, output_vec_len ); + case 337: return makeRegisterExpression(amdgpu_gfx940::v81, output_vec_len ); + case 338: return makeRegisterExpression(amdgpu_gfx940::v82, output_vec_len ); + case 339: return makeRegisterExpression(amdgpu_gfx940::v83, output_vec_len ); + case 340: return makeRegisterExpression(amdgpu_gfx940::v84, output_vec_len ); + case 341: return makeRegisterExpression(amdgpu_gfx940::v85, output_vec_len ); + case 342: return makeRegisterExpression(amdgpu_gfx940::v86, output_vec_len ); + case 343: return makeRegisterExpression(amdgpu_gfx940::v87, output_vec_len ); + case 344: return makeRegisterExpression(amdgpu_gfx940::v88, output_vec_len ); + case 345: return makeRegisterExpression(amdgpu_gfx940::v89, output_vec_len ); + case 346: return makeRegisterExpression(amdgpu_gfx940::v90, output_vec_len ); + case 347: return makeRegisterExpression(amdgpu_gfx940::v91, output_vec_len ); + case 348: return makeRegisterExpression(amdgpu_gfx940::v92, output_vec_len ); + case 349: return makeRegisterExpression(amdgpu_gfx940::v93, output_vec_len ); + case 350: return makeRegisterExpression(amdgpu_gfx940::v94, output_vec_len ); + case 351: return makeRegisterExpression(amdgpu_gfx940::v95, output_vec_len ); + case 352: return makeRegisterExpression(amdgpu_gfx940::v96, output_vec_len ); + case 353: return makeRegisterExpression(amdgpu_gfx940::v97, output_vec_len ); + case 354: return makeRegisterExpression(amdgpu_gfx940::v98, output_vec_len ); + case 355: return makeRegisterExpression(amdgpu_gfx940::v99, output_vec_len ); + case 356: return makeRegisterExpression(amdgpu_gfx940::v100, output_vec_len ); + case 357: return makeRegisterExpression(amdgpu_gfx940::v101, output_vec_len ); + case 358: return makeRegisterExpression(amdgpu_gfx940::v102, output_vec_len ); + case 359: return makeRegisterExpression(amdgpu_gfx940::v103, output_vec_len ); + case 360: return makeRegisterExpression(amdgpu_gfx940::v104, output_vec_len ); + case 361: return makeRegisterExpression(amdgpu_gfx940::v105, output_vec_len ); + case 362: return makeRegisterExpression(amdgpu_gfx940::v106, output_vec_len ); + case 363: return makeRegisterExpression(amdgpu_gfx940::v107, output_vec_len ); + case 364: return makeRegisterExpression(amdgpu_gfx940::v108, output_vec_len ); + case 365: return makeRegisterExpression(amdgpu_gfx940::v109, output_vec_len ); + case 366: return makeRegisterExpression(amdgpu_gfx940::v110, output_vec_len ); + case 367: return makeRegisterExpression(amdgpu_gfx940::v111, output_vec_len ); + case 368: return makeRegisterExpression(amdgpu_gfx940::v112, output_vec_len ); + case 369: return makeRegisterExpression(amdgpu_gfx940::v113, output_vec_len ); + case 370: return makeRegisterExpression(amdgpu_gfx940::v114, output_vec_len ); + case 371: return makeRegisterExpression(amdgpu_gfx940::v115, output_vec_len ); + case 372: return makeRegisterExpression(amdgpu_gfx940::v116, output_vec_len ); + case 373: return makeRegisterExpression(amdgpu_gfx940::v117, output_vec_len ); + case 374: return makeRegisterExpression(amdgpu_gfx940::v118, output_vec_len ); + case 375: return makeRegisterExpression(amdgpu_gfx940::v119, output_vec_len ); + case 376: return makeRegisterExpression(amdgpu_gfx940::v120, output_vec_len ); + case 377: return makeRegisterExpression(amdgpu_gfx940::v121, output_vec_len ); + case 378: return makeRegisterExpression(amdgpu_gfx940::v122, output_vec_len ); + case 379: return makeRegisterExpression(amdgpu_gfx940::v123, output_vec_len ); + case 380: return makeRegisterExpression(amdgpu_gfx940::v124, output_vec_len ); + case 381: return makeRegisterExpression(amdgpu_gfx940::v125, output_vec_len ); + case 382: return makeRegisterExpression(amdgpu_gfx940::v126, output_vec_len ); + case 383: return makeRegisterExpression(amdgpu_gfx940::v127, output_vec_len ); + case 384: return makeRegisterExpression(amdgpu_gfx940::v128, output_vec_len ); + case 385: return makeRegisterExpression(amdgpu_gfx940::v129, output_vec_len ); + case 386: return makeRegisterExpression(amdgpu_gfx940::v130, output_vec_len ); + case 387: return makeRegisterExpression(amdgpu_gfx940::v131, output_vec_len ); + case 388: return makeRegisterExpression(amdgpu_gfx940::v132, output_vec_len ); + case 389: return makeRegisterExpression(amdgpu_gfx940::v133, output_vec_len ); + case 390: return makeRegisterExpression(amdgpu_gfx940::v134, output_vec_len ); + case 391: return makeRegisterExpression(amdgpu_gfx940::v135, output_vec_len ); + case 392: return makeRegisterExpression(amdgpu_gfx940::v136, output_vec_len ); + case 393: return makeRegisterExpression(amdgpu_gfx940::v137, output_vec_len ); + case 394: return makeRegisterExpression(amdgpu_gfx940::v138, output_vec_len ); + case 395: return makeRegisterExpression(amdgpu_gfx940::v139, output_vec_len ); + case 396: return makeRegisterExpression(amdgpu_gfx940::v140, output_vec_len ); + case 397: return makeRegisterExpression(amdgpu_gfx940::v141, output_vec_len ); + case 398: return makeRegisterExpression(amdgpu_gfx940::v142, output_vec_len ); + case 399: return makeRegisterExpression(amdgpu_gfx940::v143, output_vec_len ); + case 400: return makeRegisterExpression(amdgpu_gfx940::v144, output_vec_len ); + case 401: return makeRegisterExpression(amdgpu_gfx940::v145, output_vec_len ); + case 402: return makeRegisterExpression(amdgpu_gfx940::v146, output_vec_len ); + case 403: return makeRegisterExpression(amdgpu_gfx940::v147, output_vec_len ); + case 404: return makeRegisterExpression(amdgpu_gfx940::v148, output_vec_len ); + case 405: return makeRegisterExpression(amdgpu_gfx940::v149, output_vec_len ); + case 406: return makeRegisterExpression(amdgpu_gfx940::v150, output_vec_len ); + case 407: return makeRegisterExpression(amdgpu_gfx940::v151, output_vec_len ); + case 408: return makeRegisterExpression(amdgpu_gfx940::v152, output_vec_len ); + case 409: return makeRegisterExpression(amdgpu_gfx940::v153, output_vec_len ); + case 410: return makeRegisterExpression(amdgpu_gfx940::v154, output_vec_len ); + case 411: return makeRegisterExpression(amdgpu_gfx940::v155, output_vec_len ); + case 412: return makeRegisterExpression(amdgpu_gfx940::v156, output_vec_len ); + case 413: return makeRegisterExpression(amdgpu_gfx940::v157, output_vec_len ); + case 414: return makeRegisterExpression(amdgpu_gfx940::v158, output_vec_len ); + case 415: return makeRegisterExpression(amdgpu_gfx940::v159, output_vec_len ); + case 416: return makeRegisterExpression(amdgpu_gfx940::v160, output_vec_len ); + case 417: return makeRegisterExpression(amdgpu_gfx940::v161, output_vec_len ); + case 418: return makeRegisterExpression(amdgpu_gfx940::v162, output_vec_len ); + case 419: return makeRegisterExpression(amdgpu_gfx940::v163, output_vec_len ); + case 420: return makeRegisterExpression(amdgpu_gfx940::v164, output_vec_len ); + case 421: return makeRegisterExpression(amdgpu_gfx940::v165, output_vec_len ); + case 422: return makeRegisterExpression(amdgpu_gfx940::v166, output_vec_len ); + case 423: return makeRegisterExpression(amdgpu_gfx940::v167, output_vec_len ); + case 424: return makeRegisterExpression(amdgpu_gfx940::v168, output_vec_len ); + case 425: return makeRegisterExpression(amdgpu_gfx940::v169, output_vec_len ); + case 426: return makeRegisterExpression(amdgpu_gfx940::v170, output_vec_len ); + case 427: return makeRegisterExpression(amdgpu_gfx940::v171, output_vec_len ); + case 428: return makeRegisterExpression(amdgpu_gfx940::v172, output_vec_len ); + case 429: return makeRegisterExpression(amdgpu_gfx940::v173, output_vec_len ); + case 430: return makeRegisterExpression(amdgpu_gfx940::v174, output_vec_len ); + case 431: return makeRegisterExpression(amdgpu_gfx940::v175, output_vec_len ); + case 432: return makeRegisterExpression(amdgpu_gfx940::v176, output_vec_len ); + case 433: return makeRegisterExpression(amdgpu_gfx940::v177, output_vec_len ); + case 434: return makeRegisterExpression(amdgpu_gfx940::v178, output_vec_len ); + case 435: return makeRegisterExpression(amdgpu_gfx940::v179, output_vec_len ); + case 436: return makeRegisterExpression(amdgpu_gfx940::v180, output_vec_len ); + case 437: return makeRegisterExpression(amdgpu_gfx940::v181, output_vec_len ); + case 438: return makeRegisterExpression(amdgpu_gfx940::v182, output_vec_len ); + case 439: return makeRegisterExpression(amdgpu_gfx940::v183, output_vec_len ); + case 440: return makeRegisterExpression(amdgpu_gfx940::v184, output_vec_len ); + case 441: return makeRegisterExpression(amdgpu_gfx940::v185, output_vec_len ); + case 442: return makeRegisterExpression(amdgpu_gfx940::v186, output_vec_len ); + case 443: return makeRegisterExpression(amdgpu_gfx940::v187, output_vec_len ); + case 444: return makeRegisterExpression(amdgpu_gfx940::v188, output_vec_len ); + case 445: return makeRegisterExpression(amdgpu_gfx940::v189, output_vec_len ); + case 446: return makeRegisterExpression(amdgpu_gfx940::v190, output_vec_len ); + case 447: return makeRegisterExpression(amdgpu_gfx940::v191, output_vec_len ); + case 448: return makeRegisterExpression(amdgpu_gfx940::v192, output_vec_len ); + case 449: return makeRegisterExpression(amdgpu_gfx940::v193, output_vec_len ); + case 450: return makeRegisterExpression(amdgpu_gfx940::v194, output_vec_len ); + case 451: return makeRegisterExpression(amdgpu_gfx940::v195, output_vec_len ); + case 452: return makeRegisterExpression(amdgpu_gfx940::v196, output_vec_len ); + case 453: return makeRegisterExpression(amdgpu_gfx940::v197, output_vec_len ); + case 454: return makeRegisterExpression(amdgpu_gfx940::v198, output_vec_len ); + case 455: return makeRegisterExpression(amdgpu_gfx940::v199, output_vec_len ); + case 456: return makeRegisterExpression(amdgpu_gfx940::v200, output_vec_len ); + case 457: return makeRegisterExpression(amdgpu_gfx940::v201, output_vec_len ); + case 458: return makeRegisterExpression(amdgpu_gfx940::v202, output_vec_len ); + case 459: return makeRegisterExpression(amdgpu_gfx940::v203, output_vec_len ); + case 460: return makeRegisterExpression(amdgpu_gfx940::v204, output_vec_len ); + case 461: return makeRegisterExpression(amdgpu_gfx940::v205, output_vec_len ); + case 462: return makeRegisterExpression(amdgpu_gfx940::v206, output_vec_len ); + case 463: return makeRegisterExpression(amdgpu_gfx940::v207, output_vec_len ); + case 464: return makeRegisterExpression(amdgpu_gfx940::v208, output_vec_len ); + case 465: return makeRegisterExpression(amdgpu_gfx940::v209, output_vec_len ); + case 466: return makeRegisterExpression(amdgpu_gfx940::v210, output_vec_len ); + case 467: return makeRegisterExpression(amdgpu_gfx940::v211, output_vec_len ); + case 468: return makeRegisterExpression(amdgpu_gfx940::v212, output_vec_len ); + case 469: return makeRegisterExpression(amdgpu_gfx940::v213, output_vec_len ); + case 470: return makeRegisterExpression(amdgpu_gfx940::v214, output_vec_len ); + case 471: return makeRegisterExpression(amdgpu_gfx940::v215, output_vec_len ); + case 472: return makeRegisterExpression(amdgpu_gfx940::v216, output_vec_len ); + case 473: return makeRegisterExpression(amdgpu_gfx940::v217, output_vec_len ); + case 474: return makeRegisterExpression(amdgpu_gfx940::v218, output_vec_len ); + case 475: return makeRegisterExpression(amdgpu_gfx940::v219, output_vec_len ); + case 476: return makeRegisterExpression(amdgpu_gfx940::v220, output_vec_len ); + case 477: return makeRegisterExpression(amdgpu_gfx940::v221, output_vec_len ); + case 478: return makeRegisterExpression(amdgpu_gfx940::v222, output_vec_len ); + case 479: return makeRegisterExpression(amdgpu_gfx940::v223, output_vec_len ); + case 480: return makeRegisterExpression(amdgpu_gfx940::v224, output_vec_len ); + case 481: return makeRegisterExpression(amdgpu_gfx940::v225, output_vec_len ); + case 482: return makeRegisterExpression(amdgpu_gfx940::v226, output_vec_len ); + case 483: return makeRegisterExpression(amdgpu_gfx940::v227, output_vec_len ); + case 484: return makeRegisterExpression(amdgpu_gfx940::v228, output_vec_len ); + case 485: return makeRegisterExpression(amdgpu_gfx940::v229, output_vec_len ); + case 486: return makeRegisterExpression(amdgpu_gfx940::v230, output_vec_len ); + case 487: return makeRegisterExpression(amdgpu_gfx940::v231, output_vec_len ); + case 488: return makeRegisterExpression(amdgpu_gfx940::v232, output_vec_len ); + case 489: return makeRegisterExpression(amdgpu_gfx940::v233, output_vec_len ); + case 490: return makeRegisterExpression(amdgpu_gfx940::v234, output_vec_len ); + case 491: return makeRegisterExpression(amdgpu_gfx940::v235, output_vec_len ); + case 492: return makeRegisterExpression(amdgpu_gfx940::v236, output_vec_len ); + case 493: return makeRegisterExpression(amdgpu_gfx940::v237, output_vec_len ); + case 494: return makeRegisterExpression(amdgpu_gfx940::v238, output_vec_len ); + case 495: return makeRegisterExpression(amdgpu_gfx940::v239, output_vec_len ); + case 496: return makeRegisterExpression(amdgpu_gfx940::v240, output_vec_len ); + case 497: return makeRegisterExpression(amdgpu_gfx940::v241, output_vec_len ); + case 498: return makeRegisterExpression(amdgpu_gfx940::v242, output_vec_len ); + case 499: return makeRegisterExpression(amdgpu_gfx940::v243, output_vec_len ); + case 500: return makeRegisterExpression(amdgpu_gfx940::v244, output_vec_len ); + case 501: return makeRegisterExpression(amdgpu_gfx940::v245, output_vec_len ); + case 502: return makeRegisterExpression(amdgpu_gfx940::v246, output_vec_len ); + case 503: return makeRegisterExpression(amdgpu_gfx940::v247, output_vec_len ); + case 504: return makeRegisterExpression(amdgpu_gfx940::v248, output_vec_len ); + case 505: return makeRegisterExpression(amdgpu_gfx940::v249, output_vec_len ); + case 506: return makeRegisterExpression(amdgpu_gfx940::v250, output_vec_len ); + case 507: return makeRegisterExpression(amdgpu_gfx940::v251, output_vec_len ); + case 508: return makeRegisterExpression(amdgpu_gfx940::v252, output_vec_len ); + case 509: return makeRegisterExpression(amdgpu_gfx940::v253, output_vec_len ); + case 510: return makeRegisterExpression(amdgpu_gfx940::v254, output_vec_len ); + case 511: return makeRegisterExpression(amdgpu_gfx940::v255, output_vec_len ); + default: return makeRegisterExpression(amdgpu_gfx940::invalid); + } + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx940::decodeOPR_SRC_SIMPLE(uint64_t input, uint32_t output_vec_len) + { + switch (input) { + case 0: return makeRegisterExpression(amdgpu_gfx940::s0, output_vec_len ); + case 1: return makeRegisterExpression(amdgpu_gfx940::s1, output_vec_len ); + case 2: return makeRegisterExpression(amdgpu_gfx940::s2, output_vec_len ); + case 3: return makeRegisterExpression(amdgpu_gfx940::s3, output_vec_len ); + case 4: return makeRegisterExpression(amdgpu_gfx940::s4, output_vec_len ); + case 5: return makeRegisterExpression(amdgpu_gfx940::s5, output_vec_len ); + case 6: return makeRegisterExpression(amdgpu_gfx940::s6, output_vec_len ); + case 7: return makeRegisterExpression(amdgpu_gfx940::s7, output_vec_len ); + case 8: return makeRegisterExpression(amdgpu_gfx940::s8, output_vec_len ); + case 9: return makeRegisterExpression(amdgpu_gfx940::s9, output_vec_len ); + case 10: return makeRegisterExpression(amdgpu_gfx940::s10, output_vec_len ); + case 11: return makeRegisterExpression(amdgpu_gfx940::s11, output_vec_len ); + case 12: return makeRegisterExpression(amdgpu_gfx940::s12, output_vec_len ); + case 13: return makeRegisterExpression(amdgpu_gfx940::s13, output_vec_len ); + case 14: return makeRegisterExpression(amdgpu_gfx940::s14, output_vec_len ); + case 15: return makeRegisterExpression(amdgpu_gfx940::s15, output_vec_len ); + case 16: return makeRegisterExpression(amdgpu_gfx940::s16, output_vec_len ); + case 17: return makeRegisterExpression(amdgpu_gfx940::s17, output_vec_len ); + case 18: return makeRegisterExpression(amdgpu_gfx940::s18, output_vec_len ); + case 19: return makeRegisterExpression(amdgpu_gfx940::s19, output_vec_len ); + case 20: return makeRegisterExpression(amdgpu_gfx940::s20, output_vec_len ); + case 21: return makeRegisterExpression(amdgpu_gfx940::s21, output_vec_len ); + case 22: return makeRegisterExpression(amdgpu_gfx940::s22, output_vec_len ); + case 23: return makeRegisterExpression(amdgpu_gfx940::s23, output_vec_len ); + case 24: return makeRegisterExpression(amdgpu_gfx940::s24, output_vec_len ); + case 25: return makeRegisterExpression(amdgpu_gfx940::s25, output_vec_len ); + case 26: return makeRegisterExpression(amdgpu_gfx940::s26, output_vec_len ); + case 27: return makeRegisterExpression(amdgpu_gfx940::s27, output_vec_len ); + case 28: return makeRegisterExpression(amdgpu_gfx940::s28, output_vec_len ); + case 29: return makeRegisterExpression(amdgpu_gfx940::s29, output_vec_len ); + case 30: return makeRegisterExpression(amdgpu_gfx940::s30, output_vec_len ); + case 31: return makeRegisterExpression(amdgpu_gfx940::s31, output_vec_len ); + case 32: return makeRegisterExpression(amdgpu_gfx940::s32, output_vec_len ); + case 33: return makeRegisterExpression(amdgpu_gfx940::s33, output_vec_len ); + case 34: return makeRegisterExpression(amdgpu_gfx940::s34, output_vec_len ); + case 35: return makeRegisterExpression(amdgpu_gfx940::s35, output_vec_len ); + case 36: return makeRegisterExpression(amdgpu_gfx940::s36, output_vec_len ); + case 37: return makeRegisterExpression(amdgpu_gfx940::s37, output_vec_len ); + case 38: return makeRegisterExpression(amdgpu_gfx940::s38, output_vec_len ); + case 39: return makeRegisterExpression(amdgpu_gfx940::s39, output_vec_len ); + case 40: return makeRegisterExpression(amdgpu_gfx940::s40, output_vec_len ); + case 41: return makeRegisterExpression(amdgpu_gfx940::s41, output_vec_len ); + case 42: return makeRegisterExpression(amdgpu_gfx940::s42, output_vec_len ); + case 43: return makeRegisterExpression(amdgpu_gfx940::s43, output_vec_len ); + case 44: return makeRegisterExpression(amdgpu_gfx940::s44, output_vec_len ); + case 45: return makeRegisterExpression(amdgpu_gfx940::s45, output_vec_len ); + case 46: return makeRegisterExpression(amdgpu_gfx940::s46, output_vec_len ); + case 47: return makeRegisterExpression(amdgpu_gfx940::s47, output_vec_len ); + case 48: return makeRegisterExpression(amdgpu_gfx940::s48, output_vec_len ); + case 49: return makeRegisterExpression(amdgpu_gfx940::s49, output_vec_len ); + case 50: return makeRegisterExpression(amdgpu_gfx940::s50, output_vec_len ); + case 51: return makeRegisterExpression(amdgpu_gfx940::s51, output_vec_len ); + case 52: return makeRegisterExpression(amdgpu_gfx940::s52, output_vec_len ); + case 53: return makeRegisterExpression(amdgpu_gfx940::s53, output_vec_len ); + case 54: return makeRegisterExpression(amdgpu_gfx940::s54, output_vec_len ); + case 55: return makeRegisterExpression(amdgpu_gfx940::s55, output_vec_len ); + case 56: return makeRegisterExpression(amdgpu_gfx940::s56, output_vec_len ); + case 57: return makeRegisterExpression(amdgpu_gfx940::s57, output_vec_len ); + case 58: return makeRegisterExpression(amdgpu_gfx940::s58, output_vec_len ); + case 59: return makeRegisterExpression(amdgpu_gfx940::s59, output_vec_len ); + case 60: return makeRegisterExpression(amdgpu_gfx940::s60, output_vec_len ); + case 61: return makeRegisterExpression(amdgpu_gfx940::s61, output_vec_len ); + case 62: return makeRegisterExpression(amdgpu_gfx940::s62, output_vec_len ); + case 63: return makeRegisterExpression(amdgpu_gfx940::s63, output_vec_len ); + case 64: return makeRegisterExpression(amdgpu_gfx940::s64, output_vec_len ); + case 65: return makeRegisterExpression(amdgpu_gfx940::s65, output_vec_len ); + case 66: return makeRegisterExpression(amdgpu_gfx940::s66, output_vec_len ); + case 67: return makeRegisterExpression(amdgpu_gfx940::s67, output_vec_len ); + case 68: return makeRegisterExpression(amdgpu_gfx940::s68, output_vec_len ); + case 69: return makeRegisterExpression(amdgpu_gfx940::s69, output_vec_len ); + case 70: return makeRegisterExpression(amdgpu_gfx940::s70, output_vec_len ); + case 71: return makeRegisterExpression(amdgpu_gfx940::s71, output_vec_len ); + case 72: return makeRegisterExpression(amdgpu_gfx940::s72, output_vec_len ); + case 73: return makeRegisterExpression(amdgpu_gfx940::s73, output_vec_len ); + case 74: return makeRegisterExpression(amdgpu_gfx940::s74, output_vec_len ); + case 75: return makeRegisterExpression(amdgpu_gfx940::s75, output_vec_len ); + case 76: return makeRegisterExpression(amdgpu_gfx940::s76, output_vec_len ); + case 77: return makeRegisterExpression(amdgpu_gfx940::s77, output_vec_len ); + case 78: return makeRegisterExpression(amdgpu_gfx940::s78, output_vec_len ); + case 79: return makeRegisterExpression(amdgpu_gfx940::s79, output_vec_len ); + case 80: return makeRegisterExpression(amdgpu_gfx940::s80, output_vec_len ); + case 81: return makeRegisterExpression(amdgpu_gfx940::s81, output_vec_len ); + case 82: return makeRegisterExpression(amdgpu_gfx940::s82, output_vec_len ); + case 83: return makeRegisterExpression(amdgpu_gfx940::s83, output_vec_len ); + case 84: return makeRegisterExpression(amdgpu_gfx940::s84, output_vec_len ); + case 85: return makeRegisterExpression(amdgpu_gfx940::s85, output_vec_len ); + case 86: return makeRegisterExpression(amdgpu_gfx940::s86, output_vec_len ); + case 87: return makeRegisterExpression(amdgpu_gfx940::s87, output_vec_len ); + case 88: return makeRegisterExpression(amdgpu_gfx940::s88, output_vec_len ); + case 89: return makeRegisterExpression(amdgpu_gfx940::s89, output_vec_len ); + case 90: return makeRegisterExpression(amdgpu_gfx940::s90, output_vec_len ); + case 91: return makeRegisterExpression(amdgpu_gfx940::s91, output_vec_len ); + case 92: return makeRegisterExpression(amdgpu_gfx940::s92, output_vec_len ); + case 93: return makeRegisterExpression(amdgpu_gfx940::s93, output_vec_len ); + case 94: return makeRegisterExpression(amdgpu_gfx940::s94, output_vec_len ); + case 95: return makeRegisterExpression(amdgpu_gfx940::s95, output_vec_len ); + case 96: return makeRegisterExpression(amdgpu_gfx940::s96, output_vec_len ); + case 97: return makeRegisterExpression(amdgpu_gfx940::s97, output_vec_len ); + case 98: return makeRegisterExpression(amdgpu_gfx940::s98, output_vec_len ); + case 99: return makeRegisterExpression(amdgpu_gfx940::s99, output_vec_len ); + case 100: return makeRegisterExpression(amdgpu_gfx940::s100, output_vec_len ); + case 101: return makeRegisterExpression(amdgpu_gfx940::s101, output_vec_len ); + case 104: return makeRegisterExpression(amdgpu_gfx940::xnack_mask_lo, output_vec_len ); + case 105: return makeRegisterExpression(amdgpu_gfx940::xnack_mask_hi, output_vec_len ); + case 102: return makeRegisterExpression(amdgpu_gfx940::flat_scratch_lo, output_vec_len ); + case 103: return makeRegisterExpression(amdgpu_gfx940::flat_scratch_hi, output_vec_len ); + case 108: return makeRegisterExpression(amdgpu_gfx940::ttmp0, output_vec_len ); + case 109: return makeRegisterExpression(amdgpu_gfx940::ttmp1, output_vec_len ); + case 110: return makeRegisterExpression(amdgpu_gfx940::ttmp2, output_vec_len ); + case 111: return makeRegisterExpression(amdgpu_gfx940::ttmp3, output_vec_len ); + case 112: return makeRegisterExpression(amdgpu_gfx940::ttmp4, output_vec_len ); + case 113: return makeRegisterExpression(amdgpu_gfx940::ttmp5, output_vec_len ); + case 114: return makeRegisterExpression(amdgpu_gfx940::ttmp6, output_vec_len ); + case 115: return makeRegisterExpression(amdgpu_gfx940::ttmp7, output_vec_len ); + case 116: return makeRegisterExpression(amdgpu_gfx940::ttmp8, output_vec_len ); + case 117: return makeRegisterExpression(amdgpu_gfx940::ttmp9, output_vec_len ); + case 118: return makeRegisterExpression(amdgpu_gfx940::ttmp10, output_vec_len ); + case 119: return makeRegisterExpression(amdgpu_gfx940::ttmp11, output_vec_len ); + case 120: return makeRegisterExpression(amdgpu_gfx940::ttmp12, output_vec_len ); + case 121: return makeRegisterExpression(amdgpu_gfx940::ttmp13, output_vec_len ); + case 122: return makeRegisterExpression(amdgpu_gfx940::ttmp14, output_vec_len ); + case 123: return makeRegisterExpression(amdgpu_gfx940::ttmp15, output_vec_len ); + case 106: return makeRegisterExpression(amdgpu_gfx940::vcc_lo, output_vec_len ); + case 107: return makeRegisterExpression(amdgpu_gfx940::vcc_hi, output_vec_len ); + case 124: return makeRegisterExpression(amdgpu_gfx940::m0, output_vec_len ); + case 126: return makeRegisterExpression(amdgpu_gfx940::exec_lo, output_vec_len ); + case 127: return makeRegisterExpression(amdgpu_gfx940::exec_hi, output_vec_len ); + case 128: return Immediate::makeImmediate(Result(u32, 0)); + case 129: return Immediate::makeImmediate(Result(u32, 1)); + case 130: return Immediate::makeImmediate(Result(u32, 2)); + case 131: return Immediate::makeImmediate(Result(u32, 3)); + case 132: return Immediate::makeImmediate(Result(u32, 4)); + case 133: return Immediate::makeImmediate(Result(u32, 5)); + case 134: return Immediate::makeImmediate(Result(u32, 6)); + case 135: return Immediate::makeImmediate(Result(u32, 7)); + case 136: return Immediate::makeImmediate(Result(u32, 8)); + case 137: return Immediate::makeImmediate(Result(u32, 9)); + case 138: return Immediate::makeImmediate(Result(u32, 10)); + case 139: return Immediate::makeImmediate(Result(u32, 11)); + case 140: return Immediate::makeImmediate(Result(u32, 12)); + case 141: return Immediate::makeImmediate(Result(u32, 13)); + case 142: return Immediate::makeImmediate(Result(u32, 14)); + case 143: return Immediate::makeImmediate(Result(u32, 15)); + case 144: return Immediate::makeImmediate(Result(u32, 16)); + case 145: return Immediate::makeImmediate(Result(u32, 17)); + case 146: return Immediate::makeImmediate(Result(u32, 18)); + case 147: return Immediate::makeImmediate(Result(u32, 19)); + case 148: return Immediate::makeImmediate(Result(u32, 20)); + case 149: return Immediate::makeImmediate(Result(u32, 21)); + case 150: return Immediate::makeImmediate(Result(u32, 22)); + case 151: return Immediate::makeImmediate(Result(u32, 23)); + case 152: return Immediate::makeImmediate(Result(u32, 24)); + case 153: return Immediate::makeImmediate(Result(u32, 25)); + case 154: return Immediate::makeImmediate(Result(u32, 26)); + case 155: return Immediate::makeImmediate(Result(u32, 27)); + case 156: return Immediate::makeImmediate(Result(u32, 28)); + case 157: return Immediate::makeImmediate(Result(u32, 29)); + case 158: return Immediate::makeImmediate(Result(u32, 30)); + case 159: return Immediate::makeImmediate(Result(u32, 31)); + case 160: return Immediate::makeImmediate(Result(u32, 32)); + case 161: return Immediate::makeImmediate(Result(u32, 33)); + case 162: return Immediate::makeImmediate(Result(u32, 34)); + case 163: return Immediate::makeImmediate(Result(u32, 35)); + case 164: return Immediate::makeImmediate(Result(u32, 36)); + case 165: return Immediate::makeImmediate(Result(u32, 37)); + case 166: return Immediate::makeImmediate(Result(u32, 38)); + case 167: return Immediate::makeImmediate(Result(u32, 39)); + case 168: return Immediate::makeImmediate(Result(u32, 40)); + case 169: return Immediate::makeImmediate(Result(u32, 41)); + case 170: return Immediate::makeImmediate(Result(u32, 42)); + case 171: return Immediate::makeImmediate(Result(u32, 43)); + case 172: return Immediate::makeImmediate(Result(u32, 44)); + case 173: return Immediate::makeImmediate(Result(u32, 45)); + case 174: return Immediate::makeImmediate(Result(u32, 46)); + case 175: return Immediate::makeImmediate(Result(u32, 47)); + case 176: return Immediate::makeImmediate(Result(u32, 48)); + case 177: return Immediate::makeImmediate(Result(u32, 49)); + case 178: return Immediate::makeImmediate(Result(u32, 50)); + case 179: return Immediate::makeImmediate(Result(u32, 51)); + case 180: return Immediate::makeImmediate(Result(u32, 52)); + case 181: return Immediate::makeImmediate(Result(u32, 53)); + case 182: return Immediate::makeImmediate(Result(u32, 54)); + case 183: return Immediate::makeImmediate(Result(u32, 55)); + case 184: return Immediate::makeImmediate(Result(u32, 56)); + case 185: return Immediate::makeImmediate(Result(u32, 57)); + case 186: return Immediate::makeImmediate(Result(u32, 58)); + case 187: return Immediate::makeImmediate(Result(u32, 59)); + case 188: return Immediate::makeImmediate(Result(u32, 60)); + case 189: return Immediate::makeImmediate(Result(u32, 61)); + case 190: return Immediate::makeImmediate(Result(u32, 62)); + case 191: return Immediate::makeImmediate(Result(u32, 63)); + case 192: return Immediate::makeImmediate(Result(u32, 64)); + case 193: return Immediate::makeImmediate(Result(u32, -1)); + case 194: return Immediate::makeImmediate(Result(u32, -2)); + case 195: return Immediate::makeImmediate(Result(u32, -3)); + case 196: return Immediate::makeImmediate(Result(u32, -4)); + case 197: return Immediate::makeImmediate(Result(u32, -5)); + case 198: return Immediate::makeImmediate(Result(u32, -6)); + case 199: return Immediate::makeImmediate(Result(u32, -7)); + case 200: return Immediate::makeImmediate(Result(u32, -8)); + case 201: return Immediate::makeImmediate(Result(u32, -9)); + case 202: return Immediate::makeImmediate(Result(u32, -10)); + case 203: return Immediate::makeImmediate(Result(u32, -11)); + case 204: return Immediate::makeImmediate(Result(u32, -12)); + case 205: return Immediate::makeImmediate(Result(u32, -13)); + case 206: return Immediate::makeImmediate(Result(u32, -14)); + case 207: return Immediate::makeImmediate(Result(u32, -15)); + case 208: return Immediate::makeImmediate(Result(u32, -16)); + case 240: return Immediate::makeImmediate(Result(sp_float, 0.5)); + case 241: return Immediate::makeImmediate(Result(sp_float, -0.5)); + case 242: return Immediate::makeImmediate(Result(sp_float, 1.0)); + case 243: return Immediate::makeImmediate(Result(sp_float, -1.0)); + case 244: return Immediate::makeImmediate(Result(sp_float, 2.0)); + case 245: return Immediate::makeImmediate(Result(sp_float, -2.0)); + case 246: return Immediate::makeImmediate(Result(sp_float, 4.0)); + case 247: return Immediate::makeImmediate(Result(sp_float, -4.0)); + case 248: return Immediate::makeImmediate(Result(sp_float, 0.15915494)); + case 251: return makeRegisterExpression(amdgpu_gfx940::src_vccz, output_vec_len ); + case 252: return makeRegisterExpression(amdgpu_gfx940::src_execz, output_vec_len ); + case 253: return makeRegisterExpression(amdgpu_gfx940::src_scc, output_vec_len ); + case 235: return makeRegisterExpression(amdgpu_gfx940::src_shared_base, output_vec_len ); + case 236: return makeRegisterExpression(amdgpu_gfx940::src_shared_limit, output_vec_len ); + case 237: return makeRegisterExpression(amdgpu_gfx940::src_private_base, output_vec_len ); + case 238: return makeRegisterExpression(amdgpu_gfx940::src_private_limit, output_vec_len ); + case 239: return makeRegisterExpression(amdgpu_gfx940::src_pops_exiting_wave_id, output_vec_len ); + case 256: return makeRegisterExpression(amdgpu_gfx940::v0, output_vec_len ); + case 257: return makeRegisterExpression(amdgpu_gfx940::v1, output_vec_len ); + case 258: return makeRegisterExpression(amdgpu_gfx940::v2, output_vec_len ); + case 259: return makeRegisterExpression(amdgpu_gfx940::v3, output_vec_len ); + case 260: return makeRegisterExpression(amdgpu_gfx940::v4, output_vec_len ); + case 261: return makeRegisterExpression(amdgpu_gfx940::v5, output_vec_len ); + case 262: return makeRegisterExpression(amdgpu_gfx940::v6, output_vec_len ); + case 263: return makeRegisterExpression(amdgpu_gfx940::v7, output_vec_len ); + case 264: return makeRegisterExpression(amdgpu_gfx940::v8, output_vec_len ); + case 265: return makeRegisterExpression(amdgpu_gfx940::v9, output_vec_len ); + case 266: return makeRegisterExpression(amdgpu_gfx940::v10, output_vec_len ); + case 267: return makeRegisterExpression(amdgpu_gfx940::v11, output_vec_len ); + case 268: return makeRegisterExpression(amdgpu_gfx940::v12, output_vec_len ); + case 269: return makeRegisterExpression(amdgpu_gfx940::v13, output_vec_len ); + case 270: return makeRegisterExpression(amdgpu_gfx940::v14, output_vec_len ); + case 271: return makeRegisterExpression(amdgpu_gfx940::v15, output_vec_len ); + case 272: return makeRegisterExpression(amdgpu_gfx940::v16, output_vec_len ); + case 273: return makeRegisterExpression(amdgpu_gfx940::v17, output_vec_len ); + case 274: return makeRegisterExpression(amdgpu_gfx940::v18, output_vec_len ); + case 275: return makeRegisterExpression(amdgpu_gfx940::v19, output_vec_len ); + case 276: return makeRegisterExpression(amdgpu_gfx940::v20, output_vec_len ); + case 277: return makeRegisterExpression(amdgpu_gfx940::v21, output_vec_len ); + case 278: return makeRegisterExpression(amdgpu_gfx940::v22, output_vec_len ); + case 279: return makeRegisterExpression(amdgpu_gfx940::v23, output_vec_len ); + case 280: return makeRegisterExpression(amdgpu_gfx940::v24, output_vec_len ); + case 281: return makeRegisterExpression(amdgpu_gfx940::v25, output_vec_len ); + case 282: return makeRegisterExpression(amdgpu_gfx940::v26, output_vec_len ); + case 283: return makeRegisterExpression(amdgpu_gfx940::v27, output_vec_len ); + case 284: return makeRegisterExpression(amdgpu_gfx940::v28, output_vec_len ); + case 285: return makeRegisterExpression(amdgpu_gfx940::v29, output_vec_len ); + case 286: return makeRegisterExpression(amdgpu_gfx940::v30, output_vec_len ); + case 287: return makeRegisterExpression(amdgpu_gfx940::v31, output_vec_len ); + case 288: return makeRegisterExpression(amdgpu_gfx940::v32, output_vec_len ); + case 289: return makeRegisterExpression(amdgpu_gfx940::v33, output_vec_len ); + case 290: return makeRegisterExpression(amdgpu_gfx940::v34, output_vec_len ); + case 291: return makeRegisterExpression(amdgpu_gfx940::v35, output_vec_len ); + case 292: return makeRegisterExpression(amdgpu_gfx940::v36, output_vec_len ); + case 293: return makeRegisterExpression(amdgpu_gfx940::v37, output_vec_len ); + case 294: return makeRegisterExpression(amdgpu_gfx940::v38, output_vec_len ); + case 295: return makeRegisterExpression(amdgpu_gfx940::v39, output_vec_len ); + case 296: return makeRegisterExpression(amdgpu_gfx940::v40, output_vec_len ); + case 297: return makeRegisterExpression(amdgpu_gfx940::v41, output_vec_len ); + case 298: return makeRegisterExpression(amdgpu_gfx940::v42, output_vec_len ); + case 299: return makeRegisterExpression(amdgpu_gfx940::v43, output_vec_len ); + case 300: return makeRegisterExpression(amdgpu_gfx940::v44, output_vec_len ); + case 301: return makeRegisterExpression(amdgpu_gfx940::v45, output_vec_len ); + case 302: return makeRegisterExpression(amdgpu_gfx940::v46, output_vec_len ); + case 303: return makeRegisterExpression(amdgpu_gfx940::v47, output_vec_len ); + case 304: return makeRegisterExpression(amdgpu_gfx940::v48, output_vec_len ); + case 305: return makeRegisterExpression(amdgpu_gfx940::v49, output_vec_len ); + case 306: return makeRegisterExpression(amdgpu_gfx940::v50, output_vec_len ); + case 307: return makeRegisterExpression(amdgpu_gfx940::v51, output_vec_len ); + case 308: return makeRegisterExpression(amdgpu_gfx940::v52, output_vec_len ); + case 309: return makeRegisterExpression(amdgpu_gfx940::v53, output_vec_len ); + case 310: return makeRegisterExpression(amdgpu_gfx940::v54, output_vec_len ); + case 311: return makeRegisterExpression(amdgpu_gfx940::v55, output_vec_len ); + case 312: return makeRegisterExpression(amdgpu_gfx940::v56, output_vec_len ); + case 313: return makeRegisterExpression(amdgpu_gfx940::v57, output_vec_len ); + case 314: return makeRegisterExpression(amdgpu_gfx940::v58, output_vec_len ); + case 315: return makeRegisterExpression(amdgpu_gfx940::v59, output_vec_len ); + case 316: return makeRegisterExpression(amdgpu_gfx940::v60, output_vec_len ); + case 317: return makeRegisterExpression(amdgpu_gfx940::v61, output_vec_len ); + case 318: return makeRegisterExpression(amdgpu_gfx940::v62, output_vec_len ); + case 319: return makeRegisterExpression(amdgpu_gfx940::v63, output_vec_len ); + case 320: return makeRegisterExpression(amdgpu_gfx940::v64, output_vec_len ); + case 321: return makeRegisterExpression(amdgpu_gfx940::v65, output_vec_len ); + case 322: return makeRegisterExpression(amdgpu_gfx940::v66, output_vec_len ); + case 323: return makeRegisterExpression(amdgpu_gfx940::v67, output_vec_len ); + case 324: return makeRegisterExpression(amdgpu_gfx940::v68, output_vec_len ); + case 325: return makeRegisterExpression(amdgpu_gfx940::v69, output_vec_len ); + case 326: return makeRegisterExpression(amdgpu_gfx940::v70, output_vec_len ); + case 327: return makeRegisterExpression(amdgpu_gfx940::v71, output_vec_len ); + case 328: return makeRegisterExpression(amdgpu_gfx940::v72, output_vec_len ); + case 329: return makeRegisterExpression(amdgpu_gfx940::v73, output_vec_len ); + case 330: return makeRegisterExpression(amdgpu_gfx940::v74, output_vec_len ); + case 331: return makeRegisterExpression(amdgpu_gfx940::v75, output_vec_len ); + case 332: return makeRegisterExpression(amdgpu_gfx940::v76, output_vec_len ); + case 333: return makeRegisterExpression(amdgpu_gfx940::v77, output_vec_len ); + case 334: return makeRegisterExpression(amdgpu_gfx940::v78, output_vec_len ); + case 335: return makeRegisterExpression(amdgpu_gfx940::v79, output_vec_len ); + case 336: return makeRegisterExpression(amdgpu_gfx940::v80, output_vec_len ); + case 337: return makeRegisterExpression(amdgpu_gfx940::v81, output_vec_len ); + case 338: return makeRegisterExpression(amdgpu_gfx940::v82, output_vec_len ); + case 339: return makeRegisterExpression(amdgpu_gfx940::v83, output_vec_len ); + case 340: return makeRegisterExpression(amdgpu_gfx940::v84, output_vec_len ); + case 341: return makeRegisterExpression(amdgpu_gfx940::v85, output_vec_len ); + case 342: return makeRegisterExpression(amdgpu_gfx940::v86, output_vec_len ); + case 343: return makeRegisterExpression(amdgpu_gfx940::v87, output_vec_len ); + case 344: return makeRegisterExpression(amdgpu_gfx940::v88, output_vec_len ); + case 345: return makeRegisterExpression(amdgpu_gfx940::v89, output_vec_len ); + case 346: return makeRegisterExpression(amdgpu_gfx940::v90, output_vec_len ); + case 347: return makeRegisterExpression(amdgpu_gfx940::v91, output_vec_len ); + case 348: return makeRegisterExpression(amdgpu_gfx940::v92, output_vec_len ); + case 349: return makeRegisterExpression(amdgpu_gfx940::v93, output_vec_len ); + case 350: return makeRegisterExpression(amdgpu_gfx940::v94, output_vec_len ); + case 351: return makeRegisterExpression(amdgpu_gfx940::v95, output_vec_len ); + case 352: return makeRegisterExpression(amdgpu_gfx940::v96, output_vec_len ); + case 353: return makeRegisterExpression(amdgpu_gfx940::v97, output_vec_len ); + case 354: return makeRegisterExpression(amdgpu_gfx940::v98, output_vec_len ); + case 355: return makeRegisterExpression(amdgpu_gfx940::v99, output_vec_len ); + case 356: return makeRegisterExpression(amdgpu_gfx940::v100, output_vec_len ); + case 357: return makeRegisterExpression(amdgpu_gfx940::v101, output_vec_len ); + case 358: return makeRegisterExpression(amdgpu_gfx940::v102, output_vec_len ); + case 359: return makeRegisterExpression(amdgpu_gfx940::v103, output_vec_len ); + case 360: return makeRegisterExpression(amdgpu_gfx940::v104, output_vec_len ); + case 361: return makeRegisterExpression(amdgpu_gfx940::v105, output_vec_len ); + case 362: return makeRegisterExpression(amdgpu_gfx940::v106, output_vec_len ); + case 363: return makeRegisterExpression(amdgpu_gfx940::v107, output_vec_len ); + case 364: return makeRegisterExpression(amdgpu_gfx940::v108, output_vec_len ); + case 365: return makeRegisterExpression(amdgpu_gfx940::v109, output_vec_len ); + case 366: return makeRegisterExpression(amdgpu_gfx940::v110, output_vec_len ); + case 367: return makeRegisterExpression(amdgpu_gfx940::v111, output_vec_len ); + case 368: return makeRegisterExpression(amdgpu_gfx940::v112, output_vec_len ); + case 369: return makeRegisterExpression(amdgpu_gfx940::v113, output_vec_len ); + case 370: return makeRegisterExpression(amdgpu_gfx940::v114, output_vec_len ); + case 371: return makeRegisterExpression(amdgpu_gfx940::v115, output_vec_len ); + case 372: return makeRegisterExpression(amdgpu_gfx940::v116, output_vec_len ); + case 373: return makeRegisterExpression(amdgpu_gfx940::v117, output_vec_len ); + case 374: return makeRegisterExpression(amdgpu_gfx940::v118, output_vec_len ); + case 375: return makeRegisterExpression(amdgpu_gfx940::v119, output_vec_len ); + case 376: return makeRegisterExpression(amdgpu_gfx940::v120, output_vec_len ); + case 377: return makeRegisterExpression(amdgpu_gfx940::v121, output_vec_len ); + case 378: return makeRegisterExpression(amdgpu_gfx940::v122, output_vec_len ); + case 379: return makeRegisterExpression(amdgpu_gfx940::v123, output_vec_len ); + case 380: return makeRegisterExpression(amdgpu_gfx940::v124, output_vec_len ); + case 381: return makeRegisterExpression(amdgpu_gfx940::v125, output_vec_len ); + case 382: return makeRegisterExpression(amdgpu_gfx940::v126, output_vec_len ); + case 383: return makeRegisterExpression(amdgpu_gfx940::v127, output_vec_len ); + case 384: return makeRegisterExpression(amdgpu_gfx940::v128, output_vec_len ); + case 385: return makeRegisterExpression(amdgpu_gfx940::v129, output_vec_len ); + case 386: return makeRegisterExpression(amdgpu_gfx940::v130, output_vec_len ); + case 387: return makeRegisterExpression(amdgpu_gfx940::v131, output_vec_len ); + case 388: return makeRegisterExpression(amdgpu_gfx940::v132, output_vec_len ); + case 389: return makeRegisterExpression(amdgpu_gfx940::v133, output_vec_len ); + case 390: return makeRegisterExpression(amdgpu_gfx940::v134, output_vec_len ); + case 391: return makeRegisterExpression(amdgpu_gfx940::v135, output_vec_len ); + case 392: return makeRegisterExpression(amdgpu_gfx940::v136, output_vec_len ); + case 393: return makeRegisterExpression(amdgpu_gfx940::v137, output_vec_len ); + case 394: return makeRegisterExpression(amdgpu_gfx940::v138, output_vec_len ); + case 395: return makeRegisterExpression(amdgpu_gfx940::v139, output_vec_len ); + case 396: return makeRegisterExpression(amdgpu_gfx940::v140, output_vec_len ); + case 397: return makeRegisterExpression(amdgpu_gfx940::v141, output_vec_len ); + case 398: return makeRegisterExpression(amdgpu_gfx940::v142, output_vec_len ); + case 399: return makeRegisterExpression(amdgpu_gfx940::v143, output_vec_len ); + case 400: return makeRegisterExpression(amdgpu_gfx940::v144, output_vec_len ); + case 401: return makeRegisterExpression(amdgpu_gfx940::v145, output_vec_len ); + case 402: return makeRegisterExpression(amdgpu_gfx940::v146, output_vec_len ); + case 403: return makeRegisterExpression(amdgpu_gfx940::v147, output_vec_len ); + case 404: return makeRegisterExpression(amdgpu_gfx940::v148, output_vec_len ); + case 405: return makeRegisterExpression(amdgpu_gfx940::v149, output_vec_len ); + case 406: return makeRegisterExpression(amdgpu_gfx940::v150, output_vec_len ); + case 407: return makeRegisterExpression(amdgpu_gfx940::v151, output_vec_len ); + case 408: return makeRegisterExpression(amdgpu_gfx940::v152, output_vec_len ); + case 409: return makeRegisterExpression(amdgpu_gfx940::v153, output_vec_len ); + case 410: return makeRegisterExpression(amdgpu_gfx940::v154, output_vec_len ); + case 411: return makeRegisterExpression(amdgpu_gfx940::v155, output_vec_len ); + case 412: return makeRegisterExpression(amdgpu_gfx940::v156, output_vec_len ); + case 413: return makeRegisterExpression(amdgpu_gfx940::v157, output_vec_len ); + case 414: return makeRegisterExpression(amdgpu_gfx940::v158, output_vec_len ); + case 415: return makeRegisterExpression(amdgpu_gfx940::v159, output_vec_len ); + case 416: return makeRegisterExpression(amdgpu_gfx940::v160, output_vec_len ); + case 417: return makeRegisterExpression(amdgpu_gfx940::v161, output_vec_len ); + case 418: return makeRegisterExpression(amdgpu_gfx940::v162, output_vec_len ); + case 419: return makeRegisterExpression(amdgpu_gfx940::v163, output_vec_len ); + case 420: return makeRegisterExpression(amdgpu_gfx940::v164, output_vec_len ); + case 421: return makeRegisterExpression(amdgpu_gfx940::v165, output_vec_len ); + case 422: return makeRegisterExpression(amdgpu_gfx940::v166, output_vec_len ); + case 423: return makeRegisterExpression(amdgpu_gfx940::v167, output_vec_len ); + case 424: return makeRegisterExpression(amdgpu_gfx940::v168, output_vec_len ); + case 425: return makeRegisterExpression(amdgpu_gfx940::v169, output_vec_len ); + case 426: return makeRegisterExpression(amdgpu_gfx940::v170, output_vec_len ); + case 427: return makeRegisterExpression(amdgpu_gfx940::v171, output_vec_len ); + case 428: return makeRegisterExpression(amdgpu_gfx940::v172, output_vec_len ); + case 429: return makeRegisterExpression(amdgpu_gfx940::v173, output_vec_len ); + case 430: return makeRegisterExpression(amdgpu_gfx940::v174, output_vec_len ); + case 431: return makeRegisterExpression(amdgpu_gfx940::v175, output_vec_len ); + case 432: return makeRegisterExpression(amdgpu_gfx940::v176, output_vec_len ); + case 433: return makeRegisterExpression(amdgpu_gfx940::v177, output_vec_len ); + case 434: return makeRegisterExpression(amdgpu_gfx940::v178, output_vec_len ); + case 435: return makeRegisterExpression(amdgpu_gfx940::v179, output_vec_len ); + case 436: return makeRegisterExpression(amdgpu_gfx940::v180, output_vec_len ); + case 437: return makeRegisterExpression(amdgpu_gfx940::v181, output_vec_len ); + case 438: return makeRegisterExpression(amdgpu_gfx940::v182, output_vec_len ); + case 439: return makeRegisterExpression(amdgpu_gfx940::v183, output_vec_len ); + case 440: return makeRegisterExpression(amdgpu_gfx940::v184, output_vec_len ); + case 441: return makeRegisterExpression(amdgpu_gfx940::v185, output_vec_len ); + case 442: return makeRegisterExpression(amdgpu_gfx940::v186, output_vec_len ); + case 443: return makeRegisterExpression(amdgpu_gfx940::v187, output_vec_len ); + case 444: return makeRegisterExpression(amdgpu_gfx940::v188, output_vec_len ); + case 445: return makeRegisterExpression(amdgpu_gfx940::v189, output_vec_len ); + case 446: return makeRegisterExpression(amdgpu_gfx940::v190, output_vec_len ); + case 447: return makeRegisterExpression(amdgpu_gfx940::v191, output_vec_len ); + case 448: return makeRegisterExpression(amdgpu_gfx940::v192, output_vec_len ); + case 449: return makeRegisterExpression(amdgpu_gfx940::v193, output_vec_len ); + case 450: return makeRegisterExpression(amdgpu_gfx940::v194, output_vec_len ); + case 451: return makeRegisterExpression(amdgpu_gfx940::v195, output_vec_len ); + case 452: return makeRegisterExpression(amdgpu_gfx940::v196, output_vec_len ); + case 453: return makeRegisterExpression(amdgpu_gfx940::v197, output_vec_len ); + case 454: return makeRegisterExpression(amdgpu_gfx940::v198, output_vec_len ); + case 455: return makeRegisterExpression(amdgpu_gfx940::v199, output_vec_len ); + case 456: return makeRegisterExpression(amdgpu_gfx940::v200, output_vec_len ); + case 457: return makeRegisterExpression(amdgpu_gfx940::v201, output_vec_len ); + case 458: return makeRegisterExpression(amdgpu_gfx940::v202, output_vec_len ); + case 459: return makeRegisterExpression(amdgpu_gfx940::v203, output_vec_len ); + case 460: return makeRegisterExpression(amdgpu_gfx940::v204, output_vec_len ); + case 461: return makeRegisterExpression(amdgpu_gfx940::v205, output_vec_len ); + case 462: return makeRegisterExpression(amdgpu_gfx940::v206, output_vec_len ); + case 463: return makeRegisterExpression(amdgpu_gfx940::v207, output_vec_len ); + case 464: return makeRegisterExpression(amdgpu_gfx940::v208, output_vec_len ); + case 465: return makeRegisterExpression(amdgpu_gfx940::v209, output_vec_len ); + case 466: return makeRegisterExpression(amdgpu_gfx940::v210, output_vec_len ); + case 467: return makeRegisterExpression(amdgpu_gfx940::v211, output_vec_len ); + case 468: return makeRegisterExpression(amdgpu_gfx940::v212, output_vec_len ); + case 469: return makeRegisterExpression(amdgpu_gfx940::v213, output_vec_len ); + case 470: return makeRegisterExpression(amdgpu_gfx940::v214, output_vec_len ); + case 471: return makeRegisterExpression(amdgpu_gfx940::v215, output_vec_len ); + case 472: return makeRegisterExpression(amdgpu_gfx940::v216, output_vec_len ); + case 473: return makeRegisterExpression(amdgpu_gfx940::v217, output_vec_len ); + case 474: return makeRegisterExpression(amdgpu_gfx940::v218, output_vec_len ); + case 475: return makeRegisterExpression(amdgpu_gfx940::v219, output_vec_len ); + case 476: return makeRegisterExpression(amdgpu_gfx940::v220, output_vec_len ); + case 477: return makeRegisterExpression(amdgpu_gfx940::v221, output_vec_len ); + case 478: return makeRegisterExpression(amdgpu_gfx940::v222, output_vec_len ); + case 479: return makeRegisterExpression(amdgpu_gfx940::v223, output_vec_len ); + case 480: return makeRegisterExpression(amdgpu_gfx940::v224, output_vec_len ); + case 481: return makeRegisterExpression(amdgpu_gfx940::v225, output_vec_len ); + case 482: return makeRegisterExpression(amdgpu_gfx940::v226, output_vec_len ); + case 483: return makeRegisterExpression(amdgpu_gfx940::v227, output_vec_len ); + case 484: return makeRegisterExpression(amdgpu_gfx940::v228, output_vec_len ); + case 485: return makeRegisterExpression(amdgpu_gfx940::v229, output_vec_len ); + case 486: return makeRegisterExpression(amdgpu_gfx940::v230, output_vec_len ); + case 487: return makeRegisterExpression(amdgpu_gfx940::v231, output_vec_len ); + case 488: return makeRegisterExpression(amdgpu_gfx940::v232, output_vec_len ); + case 489: return makeRegisterExpression(amdgpu_gfx940::v233, output_vec_len ); + case 490: return makeRegisterExpression(amdgpu_gfx940::v234, output_vec_len ); + case 491: return makeRegisterExpression(amdgpu_gfx940::v235, output_vec_len ); + case 492: return makeRegisterExpression(amdgpu_gfx940::v236, output_vec_len ); + case 493: return makeRegisterExpression(amdgpu_gfx940::v237, output_vec_len ); + case 494: return makeRegisterExpression(amdgpu_gfx940::v238, output_vec_len ); + case 495: return makeRegisterExpression(amdgpu_gfx940::v239, output_vec_len ); + case 496: return makeRegisterExpression(amdgpu_gfx940::v240, output_vec_len ); + case 497: return makeRegisterExpression(amdgpu_gfx940::v241, output_vec_len ); + case 498: return makeRegisterExpression(amdgpu_gfx940::v242, output_vec_len ); + case 499: return makeRegisterExpression(amdgpu_gfx940::v243, output_vec_len ); + case 500: return makeRegisterExpression(amdgpu_gfx940::v244, output_vec_len ); + case 501: return makeRegisterExpression(amdgpu_gfx940::v245, output_vec_len ); + case 502: return makeRegisterExpression(amdgpu_gfx940::v246, output_vec_len ); + case 503: return makeRegisterExpression(amdgpu_gfx940::v247, output_vec_len ); + case 504: return makeRegisterExpression(amdgpu_gfx940::v248, output_vec_len ); + case 505: return makeRegisterExpression(amdgpu_gfx940::v249, output_vec_len ); + case 506: return makeRegisterExpression(amdgpu_gfx940::v250, output_vec_len ); + case 507: return makeRegisterExpression(amdgpu_gfx940::v251, output_vec_len ); + case 508: return makeRegisterExpression(amdgpu_gfx940::v252, output_vec_len ); + case 509: return makeRegisterExpression(amdgpu_gfx940::v253, output_vec_len ); + case 510: return makeRegisterExpression(amdgpu_gfx940::v254, output_vec_len ); + case 511: return makeRegisterExpression(amdgpu_gfx940::v255, output_vec_len ); + default: return makeRegisterExpression(amdgpu_gfx940::invalid); + } + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx940::decodeOPR_SRC_VGPR(uint64_t input, uint32_t output_vec_len) + { + switch (input) { + case 256: return makeRegisterExpression(amdgpu_gfx940::v0, output_vec_len ); + case 257: return makeRegisterExpression(amdgpu_gfx940::v1, output_vec_len ); + case 258: return makeRegisterExpression(amdgpu_gfx940::v2, output_vec_len ); + case 259: return makeRegisterExpression(amdgpu_gfx940::v3, output_vec_len ); + case 260: return makeRegisterExpression(amdgpu_gfx940::v4, output_vec_len ); + case 261: return makeRegisterExpression(amdgpu_gfx940::v5, output_vec_len ); + case 262: return makeRegisterExpression(amdgpu_gfx940::v6, output_vec_len ); + case 263: return makeRegisterExpression(amdgpu_gfx940::v7, output_vec_len ); + case 264: return makeRegisterExpression(amdgpu_gfx940::v8, output_vec_len ); + case 265: return makeRegisterExpression(amdgpu_gfx940::v9, output_vec_len ); + case 266: return makeRegisterExpression(amdgpu_gfx940::v10, output_vec_len ); + case 267: return makeRegisterExpression(amdgpu_gfx940::v11, output_vec_len ); + case 268: return makeRegisterExpression(amdgpu_gfx940::v12, output_vec_len ); + case 269: return makeRegisterExpression(amdgpu_gfx940::v13, output_vec_len ); + case 270: return makeRegisterExpression(amdgpu_gfx940::v14, output_vec_len ); + case 271: return makeRegisterExpression(amdgpu_gfx940::v15, output_vec_len ); + case 272: return makeRegisterExpression(amdgpu_gfx940::v16, output_vec_len ); + case 273: return makeRegisterExpression(amdgpu_gfx940::v17, output_vec_len ); + case 274: return makeRegisterExpression(amdgpu_gfx940::v18, output_vec_len ); + case 275: return makeRegisterExpression(amdgpu_gfx940::v19, output_vec_len ); + case 276: return makeRegisterExpression(amdgpu_gfx940::v20, output_vec_len ); + case 277: return makeRegisterExpression(amdgpu_gfx940::v21, output_vec_len ); + case 278: return makeRegisterExpression(amdgpu_gfx940::v22, output_vec_len ); + case 279: return makeRegisterExpression(amdgpu_gfx940::v23, output_vec_len ); + case 280: return makeRegisterExpression(amdgpu_gfx940::v24, output_vec_len ); + case 281: return makeRegisterExpression(amdgpu_gfx940::v25, output_vec_len ); + case 282: return makeRegisterExpression(amdgpu_gfx940::v26, output_vec_len ); + case 283: return makeRegisterExpression(amdgpu_gfx940::v27, output_vec_len ); + case 284: return makeRegisterExpression(amdgpu_gfx940::v28, output_vec_len ); + case 285: return makeRegisterExpression(amdgpu_gfx940::v29, output_vec_len ); + case 286: return makeRegisterExpression(amdgpu_gfx940::v30, output_vec_len ); + case 287: return makeRegisterExpression(amdgpu_gfx940::v31, output_vec_len ); + case 288: return makeRegisterExpression(amdgpu_gfx940::v32, output_vec_len ); + case 289: return makeRegisterExpression(amdgpu_gfx940::v33, output_vec_len ); + case 290: return makeRegisterExpression(amdgpu_gfx940::v34, output_vec_len ); + case 291: return makeRegisterExpression(amdgpu_gfx940::v35, output_vec_len ); + case 292: return makeRegisterExpression(amdgpu_gfx940::v36, output_vec_len ); + case 293: return makeRegisterExpression(amdgpu_gfx940::v37, output_vec_len ); + case 294: return makeRegisterExpression(amdgpu_gfx940::v38, output_vec_len ); + case 295: return makeRegisterExpression(amdgpu_gfx940::v39, output_vec_len ); + case 296: return makeRegisterExpression(amdgpu_gfx940::v40, output_vec_len ); + case 297: return makeRegisterExpression(amdgpu_gfx940::v41, output_vec_len ); + case 298: return makeRegisterExpression(amdgpu_gfx940::v42, output_vec_len ); + case 299: return makeRegisterExpression(amdgpu_gfx940::v43, output_vec_len ); + case 300: return makeRegisterExpression(amdgpu_gfx940::v44, output_vec_len ); + case 301: return makeRegisterExpression(amdgpu_gfx940::v45, output_vec_len ); + case 302: return makeRegisterExpression(amdgpu_gfx940::v46, output_vec_len ); + case 303: return makeRegisterExpression(amdgpu_gfx940::v47, output_vec_len ); + case 304: return makeRegisterExpression(amdgpu_gfx940::v48, output_vec_len ); + case 305: return makeRegisterExpression(amdgpu_gfx940::v49, output_vec_len ); + case 306: return makeRegisterExpression(amdgpu_gfx940::v50, output_vec_len ); + case 307: return makeRegisterExpression(amdgpu_gfx940::v51, output_vec_len ); + case 308: return makeRegisterExpression(amdgpu_gfx940::v52, output_vec_len ); + case 309: return makeRegisterExpression(amdgpu_gfx940::v53, output_vec_len ); + case 310: return makeRegisterExpression(amdgpu_gfx940::v54, output_vec_len ); + case 311: return makeRegisterExpression(amdgpu_gfx940::v55, output_vec_len ); + case 312: return makeRegisterExpression(amdgpu_gfx940::v56, output_vec_len ); + case 313: return makeRegisterExpression(amdgpu_gfx940::v57, output_vec_len ); + case 314: return makeRegisterExpression(amdgpu_gfx940::v58, output_vec_len ); + case 315: return makeRegisterExpression(amdgpu_gfx940::v59, output_vec_len ); + case 316: return makeRegisterExpression(amdgpu_gfx940::v60, output_vec_len ); + case 317: return makeRegisterExpression(amdgpu_gfx940::v61, output_vec_len ); + case 318: return makeRegisterExpression(amdgpu_gfx940::v62, output_vec_len ); + case 319: return makeRegisterExpression(amdgpu_gfx940::v63, output_vec_len ); + case 320: return makeRegisterExpression(amdgpu_gfx940::v64, output_vec_len ); + case 321: return makeRegisterExpression(amdgpu_gfx940::v65, output_vec_len ); + case 322: return makeRegisterExpression(amdgpu_gfx940::v66, output_vec_len ); + case 323: return makeRegisterExpression(amdgpu_gfx940::v67, output_vec_len ); + case 324: return makeRegisterExpression(amdgpu_gfx940::v68, output_vec_len ); + case 325: return makeRegisterExpression(amdgpu_gfx940::v69, output_vec_len ); + case 326: return makeRegisterExpression(amdgpu_gfx940::v70, output_vec_len ); + case 327: return makeRegisterExpression(amdgpu_gfx940::v71, output_vec_len ); + case 328: return makeRegisterExpression(amdgpu_gfx940::v72, output_vec_len ); + case 329: return makeRegisterExpression(amdgpu_gfx940::v73, output_vec_len ); + case 330: return makeRegisterExpression(amdgpu_gfx940::v74, output_vec_len ); + case 331: return makeRegisterExpression(amdgpu_gfx940::v75, output_vec_len ); + case 332: return makeRegisterExpression(amdgpu_gfx940::v76, output_vec_len ); + case 333: return makeRegisterExpression(amdgpu_gfx940::v77, output_vec_len ); + case 334: return makeRegisterExpression(amdgpu_gfx940::v78, output_vec_len ); + case 335: return makeRegisterExpression(amdgpu_gfx940::v79, output_vec_len ); + case 336: return makeRegisterExpression(amdgpu_gfx940::v80, output_vec_len ); + case 337: return makeRegisterExpression(amdgpu_gfx940::v81, output_vec_len ); + case 338: return makeRegisterExpression(amdgpu_gfx940::v82, output_vec_len ); + case 339: return makeRegisterExpression(amdgpu_gfx940::v83, output_vec_len ); + case 340: return makeRegisterExpression(amdgpu_gfx940::v84, output_vec_len ); + case 341: return makeRegisterExpression(amdgpu_gfx940::v85, output_vec_len ); + case 342: return makeRegisterExpression(amdgpu_gfx940::v86, output_vec_len ); + case 343: return makeRegisterExpression(amdgpu_gfx940::v87, output_vec_len ); + case 344: return makeRegisterExpression(amdgpu_gfx940::v88, output_vec_len ); + case 345: return makeRegisterExpression(amdgpu_gfx940::v89, output_vec_len ); + case 346: return makeRegisterExpression(amdgpu_gfx940::v90, output_vec_len ); + case 347: return makeRegisterExpression(amdgpu_gfx940::v91, output_vec_len ); + case 348: return makeRegisterExpression(amdgpu_gfx940::v92, output_vec_len ); + case 349: return makeRegisterExpression(amdgpu_gfx940::v93, output_vec_len ); + case 350: return makeRegisterExpression(amdgpu_gfx940::v94, output_vec_len ); + case 351: return makeRegisterExpression(amdgpu_gfx940::v95, output_vec_len ); + case 352: return makeRegisterExpression(amdgpu_gfx940::v96, output_vec_len ); + case 353: return makeRegisterExpression(amdgpu_gfx940::v97, output_vec_len ); + case 354: return makeRegisterExpression(amdgpu_gfx940::v98, output_vec_len ); + case 355: return makeRegisterExpression(amdgpu_gfx940::v99, output_vec_len ); + case 356: return makeRegisterExpression(amdgpu_gfx940::v100, output_vec_len ); + case 357: return makeRegisterExpression(amdgpu_gfx940::v101, output_vec_len ); + case 358: return makeRegisterExpression(amdgpu_gfx940::v102, output_vec_len ); + case 359: return makeRegisterExpression(amdgpu_gfx940::v103, output_vec_len ); + case 360: return makeRegisterExpression(amdgpu_gfx940::v104, output_vec_len ); + case 361: return makeRegisterExpression(amdgpu_gfx940::v105, output_vec_len ); + case 362: return makeRegisterExpression(amdgpu_gfx940::v106, output_vec_len ); + case 363: return makeRegisterExpression(amdgpu_gfx940::v107, output_vec_len ); + case 364: return makeRegisterExpression(amdgpu_gfx940::v108, output_vec_len ); + case 365: return makeRegisterExpression(amdgpu_gfx940::v109, output_vec_len ); + case 366: return makeRegisterExpression(amdgpu_gfx940::v110, output_vec_len ); + case 367: return makeRegisterExpression(amdgpu_gfx940::v111, output_vec_len ); + case 368: return makeRegisterExpression(amdgpu_gfx940::v112, output_vec_len ); + case 369: return makeRegisterExpression(amdgpu_gfx940::v113, output_vec_len ); + case 370: return makeRegisterExpression(amdgpu_gfx940::v114, output_vec_len ); + case 371: return makeRegisterExpression(amdgpu_gfx940::v115, output_vec_len ); + case 372: return makeRegisterExpression(amdgpu_gfx940::v116, output_vec_len ); + case 373: return makeRegisterExpression(amdgpu_gfx940::v117, output_vec_len ); + case 374: return makeRegisterExpression(amdgpu_gfx940::v118, output_vec_len ); + case 375: return makeRegisterExpression(amdgpu_gfx940::v119, output_vec_len ); + case 376: return makeRegisterExpression(amdgpu_gfx940::v120, output_vec_len ); + case 377: return makeRegisterExpression(amdgpu_gfx940::v121, output_vec_len ); + case 378: return makeRegisterExpression(amdgpu_gfx940::v122, output_vec_len ); + case 379: return makeRegisterExpression(amdgpu_gfx940::v123, output_vec_len ); + case 380: return makeRegisterExpression(amdgpu_gfx940::v124, output_vec_len ); + case 381: return makeRegisterExpression(amdgpu_gfx940::v125, output_vec_len ); + case 382: return makeRegisterExpression(amdgpu_gfx940::v126, output_vec_len ); + case 383: return makeRegisterExpression(amdgpu_gfx940::v127, output_vec_len ); + case 384: return makeRegisterExpression(amdgpu_gfx940::v128, output_vec_len ); + case 385: return makeRegisterExpression(amdgpu_gfx940::v129, output_vec_len ); + case 386: return makeRegisterExpression(amdgpu_gfx940::v130, output_vec_len ); + case 387: return makeRegisterExpression(amdgpu_gfx940::v131, output_vec_len ); + case 388: return makeRegisterExpression(amdgpu_gfx940::v132, output_vec_len ); + case 389: return makeRegisterExpression(amdgpu_gfx940::v133, output_vec_len ); + case 390: return makeRegisterExpression(amdgpu_gfx940::v134, output_vec_len ); + case 391: return makeRegisterExpression(amdgpu_gfx940::v135, output_vec_len ); + case 392: return makeRegisterExpression(amdgpu_gfx940::v136, output_vec_len ); + case 393: return makeRegisterExpression(amdgpu_gfx940::v137, output_vec_len ); + case 394: return makeRegisterExpression(amdgpu_gfx940::v138, output_vec_len ); + case 395: return makeRegisterExpression(amdgpu_gfx940::v139, output_vec_len ); + case 396: return makeRegisterExpression(amdgpu_gfx940::v140, output_vec_len ); + case 397: return makeRegisterExpression(amdgpu_gfx940::v141, output_vec_len ); + case 398: return makeRegisterExpression(amdgpu_gfx940::v142, output_vec_len ); + case 399: return makeRegisterExpression(amdgpu_gfx940::v143, output_vec_len ); + case 400: return makeRegisterExpression(amdgpu_gfx940::v144, output_vec_len ); + case 401: return makeRegisterExpression(amdgpu_gfx940::v145, output_vec_len ); + case 402: return makeRegisterExpression(amdgpu_gfx940::v146, output_vec_len ); + case 403: return makeRegisterExpression(amdgpu_gfx940::v147, output_vec_len ); + case 404: return makeRegisterExpression(amdgpu_gfx940::v148, output_vec_len ); + case 405: return makeRegisterExpression(amdgpu_gfx940::v149, output_vec_len ); + case 406: return makeRegisterExpression(amdgpu_gfx940::v150, output_vec_len ); + case 407: return makeRegisterExpression(amdgpu_gfx940::v151, output_vec_len ); + case 408: return makeRegisterExpression(amdgpu_gfx940::v152, output_vec_len ); + case 409: return makeRegisterExpression(amdgpu_gfx940::v153, output_vec_len ); + case 410: return makeRegisterExpression(amdgpu_gfx940::v154, output_vec_len ); + case 411: return makeRegisterExpression(amdgpu_gfx940::v155, output_vec_len ); + case 412: return makeRegisterExpression(amdgpu_gfx940::v156, output_vec_len ); + case 413: return makeRegisterExpression(amdgpu_gfx940::v157, output_vec_len ); + case 414: return makeRegisterExpression(amdgpu_gfx940::v158, output_vec_len ); + case 415: return makeRegisterExpression(amdgpu_gfx940::v159, output_vec_len ); + case 416: return makeRegisterExpression(amdgpu_gfx940::v160, output_vec_len ); + case 417: return makeRegisterExpression(amdgpu_gfx940::v161, output_vec_len ); + case 418: return makeRegisterExpression(amdgpu_gfx940::v162, output_vec_len ); + case 419: return makeRegisterExpression(amdgpu_gfx940::v163, output_vec_len ); + case 420: return makeRegisterExpression(amdgpu_gfx940::v164, output_vec_len ); + case 421: return makeRegisterExpression(amdgpu_gfx940::v165, output_vec_len ); + case 422: return makeRegisterExpression(amdgpu_gfx940::v166, output_vec_len ); + case 423: return makeRegisterExpression(amdgpu_gfx940::v167, output_vec_len ); + case 424: return makeRegisterExpression(amdgpu_gfx940::v168, output_vec_len ); + case 425: return makeRegisterExpression(amdgpu_gfx940::v169, output_vec_len ); + case 426: return makeRegisterExpression(amdgpu_gfx940::v170, output_vec_len ); + case 427: return makeRegisterExpression(amdgpu_gfx940::v171, output_vec_len ); + case 428: return makeRegisterExpression(amdgpu_gfx940::v172, output_vec_len ); + case 429: return makeRegisterExpression(amdgpu_gfx940::v173, output_vec_len ); + case 430: return makeRegisterExpression(amdgpu_gfx940::v174, output_vec_len ); + case 431: return makeRegisterExpression(amdgpu_gfx940::v175, output_vec_len ); + case 432: return makeRegisterExpression(amdgpu_gfx940::v176, output_vec_len ); + case 433: return makeRegisterExpression(amdgpu_gfx940::v177, output_vec_len ); + case 434: return makeRegisterExpression(amdgpu_gfx940::v178, output_vec_len ); + case 435: return makeRegisterExpression(amdgpu_gfx940::v179, output_vec_len ); + case 436: return makeRegisterExpression(amdgpu_gfx940::v180, output_vec_len ); + case 437: return makeRegisterExpression(amdgpu_gfx940::v181, output_vec_len ); + case 438: return makeRegisterExpression(amdgpu_gfx940::v182, output_vec_len ); + case 439: return makeRegisterExpression(amdgpu_gfx940::v183, output_vec_len ); + case 440: return makeRegisterExpression(amdgpu_gfx940::v184, output_vec_len ); + case 441: return makeRegisterExpression(amdgpu_gfx940::v185, output_vec_len ); + case 442: return makeRegisterExpression(amdgpu_gfx940::v186, output_vec_len ); + case 443: return makeRegisterExpression(amdgpu_gfx940::v187, output_vec_len ); + case 444: return makeRegisterExpression(amdgpu_gfx940::v188, output_vec_len ); + case 445: return makeRegisterExpression(amdgpu_gfx940::v189, output_vec_len ); + case 446: return makeRegisterExpression(amdgpu_gfx940::v190, output_vec_len ); + case 447: return makeRegisterExpression(amdgpu_gfx940::v191, output_vec_len ); + case 448: return makeRegisterExpression(amdgpu_gfx940::v192, output_vec_len ); + case 449: return makeRegisterExpression(amdgpu_gfx940::v193, output_vec_len ); + case 450: return makeRegisterExpression(amdgpu_gfx940::v194, output_vec_len ); + case 451: return makeRegisterExpression(amdgpu_gfx940::v195, output_vec_len ); + case 452: return makeRegisterExpression(amdgpu_gfx940::v196, output_vec_len ); + case 453: return makeRegisterExpression(amdgpu_gfx940::v197, output_vec_len ); + case 454: return makeRegisterExpression(amdgpu_gfx940::v198, output_vec_len ); + case 455: return makeRegisterExpression(amdgpu_gfx940::v199, output_vec_len ); + case 456: return makeRegisterExpression(amdgpu_gfx940::v200, output_vec_len ); + case 457: return makeRegisterExpression(amdgpu_gfx940::v201, output_vec_len ); + case 458: return makeRegisterExpression(amdgpu_gfx940::v202, output_vec_len ); + case 459: return makeRegisterExpression(amdgpu_gfx940::v203, output_vec_len ); + case 460: return makeRegisterExpression(amdgpu_gfx940::v204, output_vec_len ); + case 461: return makeRegisterExpression(amdgpu_gfx940::v205, output_vec_len ); + case 462: return makeRegisterExpression(amdgpu_gfx940::v206, output_vec_len ); + case 463: return makeRegisterExpression(amdgpu_gfx940::v207, output_vec_len ); + case 464: return makeRegisterExpression(amdgpu_gfx940::v208, output_vec_len ); + case 465: return makeRegisterExpression(amdgpu_gfx940::v209, output_vec_len ); + case 466: return makeRegisterExpression(amdgpu_gfx940::v210, output_vec_len ); + case 467: return makeRegisterExpression(amdgpu_gfx940::v211, output_vec_len ); + case 468: return makeRegisterExpression(amdgpu_gfx940::v212, output_vec_len ); + case 469: return makeRegisterExpression(amdgpu_gfx940::v213, output_vec_len ); + case 470: return makeRegisterExpression(amdgpu_gfx940::v214, output_vec_len ); + case 471: return makeRegisterExpression(amdgpu_gfx940::v215, output_vec_len ); + case 472: return makeRegisterExpression(amdgpu_gfx940::v216, output_vec_len ); + case 473: return makeRegisterExpression(amdgpu_gfx940::v217, output_vec_len ); + case 474: return makeRegisterExpression(amdgpu_gfx940::v218, output_vec_len ); + case 475: return makeRegisterExpression(amdgpu_gfx940::v219, output_vec_len ); + case 476: return makeRegisterExpression(amdgpu_gfx940::v220, output_vec_len ); + case 477: return makeRegisterExpression(amdgpu_gfx940::v221, output_vec_len ); + case 478: return makeRegisterExpression(amdgpu_gfx940::v222, output_vec_len ); + case 479: return makeRegisterExpression(amdgpu_gfx940::v223, output_vec_len ); + case 480: return makeRegisterExpression(amdgpu_gfx940::v224, output_vec_len ); + case 481: return makeRegisterExpression(amdgpu_gfx940::v225, output_vec_len ); + case 482: return makeRegisterExpression(amdgpu_gfx940::v226, output_vec_len ); + case 483: return makeRegisterExpression(amdgpu_gfx940::v227, output_vec_len ); + case 484: return makeRegisterExpression(amdgpu_gfx940::v228, output_vec_len ); + case 485: return makeRegisterExpression(amdgpu_gfx940::v229, output_vec_len ); + case 486: return makeRegisterExpression(amdgpu_gfx940::v230, output_vec_len ); + case 487: return makeRegisterExpression(amdgpu_gfx940::v231, output_vec_len ); + case 488: return makeRegisterExpression(amdgpu_gfx940::v232, output_vec_len ); + case 489: return makeRegisterExpression(amdgpu_gfx940::v233, output_vec_len ); + case 490: return makeRegisterExpression(amdgpu_gfx940::v234, output_vec_len ); + case 491: return makeRegisterExpression(amdgpu_gfx940::v235, output_vec_len ); + case 492: return makeRegisterExpression(amdgpu_gfx940::v236, output_vec_len ); + case 493: return makeRegisterExpression(amdgpu_gfx940::v237, output_vec_len ); + case 494: return makeRegisterExpression(amdgpu_gfx940::v238, output_vec_len ); + case 495: return makeRegisterExpression(amdgpu_gfx940::v239, output_vec_len ); + case 496: return makeRegisterExpression(amdgpu_gfx940::v240, output_vec_len ); + case 497: return makeRegisterExpression(amdgpu_gfx940::v241, output_vec_len ); + case 498: return makeRegisterExpression(amdgpu_gfx940::v242, output_vec_len ); + case 499: return makeRegisterExpression(amdgpu_gfx940::v243, output_vec_len ); + case 500: return makeRegisterExpression(amdgpu_gfx940::v244, output_vec_len ); + case 501: return makeRegisterExpression(amdgpu_gfx940::v245, output_vec_len ); + case 502: return makeRegisterExpression(amdgpu_gfx940::v246, output_vec_len ); + case 503: return makeRegisterExpression(amdgpu_gfx940::v247, output_vec_len ); + case 504: return makeRegisterExpression(amdgpu_gfx940::v248, output_vec_len ); + case 505: return makeRegisterExpression(amdgpu_gfx940::v249, output_vec_len ); + case 506: return makeRegisterExpression(amdgpu_gfx940::v250, output_vec_len ); + case 507: return makeRegisterExpression(amdgpu_gfx940::v251, output_vec_len ); + case 508: return makeRegisterExpression(amdgpu_gfx940::v252, output_vec_len ); + case 509: return makeRegisterExpression(amdgpu_gfx940::v253, output_vec_len ); + case 510: return makeRegisterExpression(amdgpu_gfx940::v254, output_vec_len ); + case 511: return makeRegisterExpression(amdgpu_gfx940::v255, output_vec_len ); + default: return makeRegisterExpression(amdgpu_gfx940::invalid); + } + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx940::decodeOPR_SRC_VGPR_OR_ACCVGPR(uint64_t input, uint32_t output_vec_len) + { + switch (input) { + case 256: return makeRegisterExpression(amdgpu_gfx940::v0, output_vec_len ); + case 257: return makeRegisterExpression(amdgpu_gfx940::v1, output_vec_len ); + case 258: return makeRegisterExpression(amdgpu_gfx940::v2, output_vec_len ); + case 259: return makeRegisterExpression(amdgpu_gfx940::v3, output_vec_len ); + case 260: return makeRegisterExpression(amdgpu_gfx940::v4, output_vec_len ); + case 261: return makeRegisterExpression(amdgpu_gfx940::v5, output_vec_len ); + case 262: return makeRegisterExpression(amdgpu_gfx940::v6, output_vec_len ); + case 263: return makeRegisterExpression(amdgpu_gfx940::v7, output_vec_len ); + case 264: return makeRegisterExpression(amdgpu_gfx940::v8, output_vec_len ); + case 265: return makeRegisterExpression(amdgpu_gfx940::v9, output_vec_len ); + case 266: return makeRegisterExpression(amdgpu_gfx940::v10, output_vec_len ); + case 267: return makeRegisterExpression(amdgpu_gfx940::v11, output_vec_len ); + case 268: return makeRegisterExpression(amdgpu_gfx940::v12, output_vec_len ); + case 269: return makeRegisterExpression(amdgpu_gfx940::v13, output_vec_len ); + case 270: return makeRegisterExpression(amdgpu_gfx940::v14, output_vec_len ); + case 271: return makeRegisterExpression(amdgpu_gfx940::v15, output_vec_len ); + case 272: return makeRegisterExpression(amdgpu_gfx940::v16, output_vec_len ); + case 273: return makeRegisterExpression(amdgpu_gfx940::v17, output_vec_len ); + case 274: return makeRegisterExpression(amdgpu_gfx940::v18, output_vec_len ); + case 275: return makeRegisterExpression(amdgpu_gfx940::v19, output_vec_len ); + case 276: return makeRegisterExpression(amdgpu_gfx940::v20, output_vec_len ); + case 277: return makeRegisterExpression(amdgpu_gfx940::v21, output_vec_len ); + case 278: return makeRegisterExpression(amdgpu_gfx940::v22, output_vec_len ); + case 279: return makeRegisterExpression(amdgpu_gfx940::v23, output_vec_len ); + case 280: return makeRegisterExpression(amdgpu_gfx940::v24, output_vec_len ); + case 281: return makeRegisterExpression(amdgpu_gfx940::v25, output_vec_len ); + case 282: return makeRegisterExpression(amdgpu_gfx940::v26, output_vec_len ); + case 283: return makeRegisterExpression(amdgpu_gfx940::v27, output_vec_len ); + case 284: return makeRegisterExpression(amdgpu_gfx940::v28, output_vec_len ); + case 285: return makeRegisterExpression(amdgpu_gfx940::v29, output_vec_len ); + case 286: return makeRegisterExpression(amdgpu_gfx940::v30, output_vec_len ); + case 287: return makeRegisterExpression(amdgpu_gfx940::v31, output_vec_len ); + case 288: return makeRegisterExpression(amdgpu_gfx940::v32, output_vec_len ); + case 289: return makeRegisterExpression(amdgpu_gfx940::v33, output_vec_len ); + case 290: return makeRegisterExpression(amdgpu_gfx940::v34, output_vec_len ); + case 291: return makeRegisterExpression(amdgpu_gfx940::v35, output_vec_len ); + case 292: return makeRegisterExpression(amdgpu_gfx940::v36, output_vec_len ); + case 293: return makeRegisterExpression(amdgpu_gfx940::v37, output_vec_len ); + case 294: return makeRegisterExpression(amdgpu_gfx940::v38, output_vec_len ); + case 295: return makeRegisterExpression(amdgpu_gfx940::v39, output_vec_len ); + case 296: return makeRegisterExpression(amdgpu_gfx940::v40, output_vec_len ); + case 297: return makeRegisterExpression(amdgpu_gfx940::v41, output_vec_len ); + case 298: return makeRegisterExpression(amdgpu_gfx940::v42, output_vec_len ); + case 299: return makeRegisterExpression(amdgpu_gfx940::v43, output_vec_len ); + case 300: return makeRegisterExpression(amdgpu_gfx940::v44, output_vec_len ); + case 301: return makeRegisterExpression(amdgpu_gfx940::v45, output_vec_len ); + case 302: return makeRegisterExpression(amdgpu_gfx940::v46, output_vec_len ); + case 303: return makeRegisterExpression(amdgpu_gfx940::v47, output_vec_len ); + case 304: return makeRegisterExpression(amdgpu_gfx940::v48, output_vec_len ); + case 305: return makeRegisterExpression(amdgpu_gfx940::v49, output_vec_len ); + case 306: return makeRegisterExpression(amdgpu_gfx940::v50, output_vec_len ); + case 307: return makeRegisterExpression(amdgpu_gfx940::v51, output_vec_len ); + case 308: return makeRegisterExpression(amdgpu_gfx940::v52, output_vec_len ); + case 309: return makeRegisterExpression(amdgpu_gfx940::v53, output_vec_len ); + case 310: return makeRegisterExpression(amdgpu_gfx940::v54, output_vec_len ); + case 311: return makeRegisterExpression(amdgpu_gfx940::v55, output_vec_len ); + case 312: return makeRegisterExpression(amdgpu_gfx940::v56, output_vec_len ); + case 313: return makeRegisterExpression(amdgpu_gfx940::v57, output_vec_len ); + case 314: return makeRegisterExpression(amdgpu_gfx940::v58, output_vec_len ); + case 315: return makeRegisterExpression(amdgpu_gfx940::v59, output_vec_len ); + case 316: return makeRegisterExpression(amdgpu_gfx940::v60, output_vec_len ); + case 317: return makeRegisterExpression(amdgpu_gfx940::v61, output_vec_len ); + case 318: return makeRegisterExpression(amdgpu_gfx940::v62, output_vec_len ); + case 319: return makeRegisterExpression(amdgpu_gfx940::v63, output_vec_len ); + case 320: return makeRegisterExpression(amdgpu_gfx940::v64, output_vec_len ); + case 321: return makeRegisterExpression(amdgpu_gfx940::v65, output_vec_len ); + case 322: return makeRegisterExpression(amdgpu_gfx940::v66, output_vec_len ); + case 323: return makeRegisterExpression(amdgpu_gfx940::v67, output_vec_len ); + case 324: return makeRegisterExpression(amdgpu_gfx940::v68, output_vec_len ); + case 325: return makeRegisterExpression(amdgpu_gfx940::v69, output_vec_len ); + case 326: return makeRegisterExpression(amdgpu_gfx940::v70, output_vec_len ); + case 327: return makeRegisterExpression(amdgpu_gfx940::v71, output_vec_len ); + case 328: return makeRegisterExpression(amdgpu_gfx940::v72, output_vec_len ); + case 329: return makeRegisterExpression(amdgpu_gfx940::v73, output_vec_len ); + case 330: return makeRegisterExpression(amdgpu_gfx940::v74, output_vec_len ); + case 331: return makeRegisterExpression(amdgpu_gfx940::v75, output_vec_len ); + case 332: return makeRegisterExpression(amdgpu_gfx940::v76, output_vec_len ); + case 333: return makeRegisterExpression(amdgpu_gfx940::v77, output_vec_len ); + case 334: return makeRegisterExpression(amdgpu_gfx940::v78, output_vec_len ); + case 335: return makeRegisterExpression(amdgpu_gfx940::v79, output_vec_len ); + case 336: return makeRegisterExpression(amdgpu_gfx940::v80, output_vec_len ); + case 337: return makeRegisterExpression(amdgpu_gfx940::v81, output_vec_len ); + case 338: return makeRegisterExpression(amdgpu_gfx940::v82, output_vec_len ); + case 339: return makeRegisterExpression(amdgpu_gfx940::v83, output_vec_len ); + case 340: return makeRegisterExpression(amdgpu_gfx940::v84, output_vec_len ); + case 341: return makeRegisterExpression(amdgpu_gfx940::v85, output_vec_len ); + case 342: return makeRegisterExpression(amdgpu_gfx940::v86, output_vec_len ); + case 343: return makeRegisterExpression(amdgpu_gfx940::v87, output_vec_len ); + case 344: return makeRegisterExpression(amdgpu_gfx940::v88, output_vec_len ); + case 345: return makeRegisterExpression(amdgpu_gfx940::v89, output_vec_len ); + case 346: return makeRegisterExpression(amdgpu_gfx940::v90, output_vec_len ); + case 347: return makeRegisterExpression(amdgpu_gfx940::v91, output_vec_len ); + case 348: return makeRegisterExpression(amdgpu_gfx940::v92, output_vec_len ); + case 349: return makeRegisterExpression(amdgpu_gfx940::v93, output_vec_len ); + case 350: return makeRegisterExpression(amdgpu_gfx940::v94, output_vec_len ); + case 351: return makeRegisterExpression(amdgpu_gfx940::v95, output_vec_len ); + case 352: return makeRegisterExpression(amdgpu_gfx940::v96, output_vec_len ); + case 353: return makeRegisterExpression(amdgpu_gfx940::v97, output_vec_len ); + case 354: return makeRegisterExpression(amdgpu_gfx940::v98, output_vec_len ); + case 355: return makeRegisterExpression(amdgpu_gfx940::v99, output_vec_len ); + case 356: return makeRegisterExpression(amdgpu_gfx940::v100, output_vec_len ); + case 357: return makeRegisterExpression(amdgpu_gfx940::v101, output_vec_len ); + case 358: return makeRegisterExpression(amdgpu_gfx940::v102, output_vec_len ); + case 359: return makeRegisterExpression(amdgpu_gfx940::v103, output_vec_len ); + case 360: return makeRegisterExpression(amdgpu_gfx940::v104, output_vec_len ); + case 361: return makeRegisterExpression(amdgpu_gfx940::v105, output_vec_len ); + case 362: return makeRegisterExpression(amdgpu_gfx940::v106, output_vec_len ); + case 363: return makeRegisterExpression(amdgpu_gfx940::v107, output_vec_len ); + case 364: return makeRegisterExpression(amdgpu_gfx940::v108, output_vec_len ); + case 365: return makeRegisterExpression(amdgpu_gfx940::v109, output_vec_len ); + case 366: return makeRegisterExpression(amdgpu_gfx940::v110, output_vec_len ); + case 367: return makeRegisterExpression(amdgpu_gfx940::v111, output_vec_len ); + case 368: return makeRegisterExpression(amdgpu_gfx940::v112, output_vec_len ); + case 369: return makeRegisterExpression(amdgpu_gfx940::v113, output_vec_len ); + case 370: return makeRegisterExpression(amdgpu_gfx940::v114, output_vec_len ); + case 371: return makeRegisterExpression(amdgpu_gfx940::v115, output_vec_len ); + case 372: return makeRegisterExpression(amdgpu_gfx940::v116, output_vec_len ); + case 373: return makeRegisterExpression(amdgpu_gfx940::v117, output_vec_len ); + case 374: return makeRegisterExpression(amdgpu_gfx940::v118, output_vec_len ); + case 375: return makeRegisterExpression(amdgpu_gfx940::v119, output_vec_len ); + case 376: return makeRegisterExpression(amdgpu_gfx940::v120, output_vec_len ); + case 377: return makeRegisterExpression(amdgpu_gfx940::v121, output_vec_len ); + case 378: return makeRegisterExpression(amdgpu_gfx940::v122, output_vec_len ); + case 379: return makeRegisterExpression(amdgpu_gfx940::v123, output_vec_len ); + case 380: return makeRegisterExpression(amdgpu_gfx940::v124, output_vec_len ); + case 381: return makeRegisterExpression(amdgpu_gfx940::v125, output_vec_len ); + case 382: return makeRegisterExpression(amdgpu_gfx940::v126, output_vec_len ); + case 383: return makeRegisterExpression(amdgpu_gfx940::v127, output_vec_len ); + case 384: return makeRegisterExpression(amdgpu_gfx940::v128, output_vec_len ); + case 385: return makeRegisterExpression(amdgpu_gfx940::v129, output_vec_len ); + case 386: return makeRegisterExpression(amdgpu_gfx940::v130, output_vec_len ); + case 387: return makeRegisterExpression(amdgpu_gfx940::v131, output_vec_len ); + case 388: return makeRegisterExpression(amdgpu_gfx940::v132, output_vec_len ); + case 389: return makeRegisterExpression(amdgpu_gfx940::v133, output_vec_len ); + case 390: return makeRegisterExpression(amdgpu_gfx940::v134, output_vec_len ); + case 391: return makeRegisterExpression(amdgpu_gfx940::v135, output_vec_len ); + case 392: return makeRegisterExpression(amdgpu_gfx940::v136, output_vec_len ); + case 393: return makeRegisterExpression(amdgpu_gfx940::v137, output_vec_len ); + case 394: return makeRegisterExpression(amdgpu_gfx940::v138, output_vec_len ); + case 395: return makeRegisterExpression(amdgpu_gfx940::v139, output_vec_len ); + case 396: return makeRegisterExpression(amdgpu_gfx940::v140, output_vec_len ); + case 397: return makeRegisterExpression(amdgpu_gfx940::v141, output_vec_len ); + case 398: return makeRegisterExpression(amdgpu_gfx940::v142, output_vec_len ); + case 399: return makeRegisterExpression(amdgpu_gfx940::v143, output_vec_len ); + case 400: return makeRegisterExpression(amdgpu_gfx940::v144, output_vec_len ); + case 401: return makeRegisterExpression(amdgpu_gfx940::v145, output_vec_len ); + case 402: return makeRegisterExpression(amdgpu_gfx940::v146, output_vec_len ); + case 403: return makeRegisterExpression(amdgpu_gfx940::v147, output_vec_len ); + case 404: return makeRegisterExpression(amdgpu_gfx940::v148, output_vec_len ); + case 405: return makeRegisterExpression(amdgpu_gfx940::v149, output_vec_len ); + case 406: return makeRegisterExpression(amdgpu_gfx940::v150, output_vec_len ); + case 407: return makeRegisterExpression(amdgpu_gfx940::v151, output_vec_len ); + case 408: return makeRegisterExpression(amdgpu_gfx940::v152, output_vec_len ); + case 409: return makeRegisterExpression(amdgpu_gfx940::v153, output_vec_len ); + case 410: return makeRegisterExpression(amdgpu_gfx940::v154, output_vec_len ); + case 411: return makeRegisterExpression(amdgpu_gfx940::v155, output_vec_len ); + case 412: return makeRegisterExpression(amdgpu_gfx940::v156, output_vec_len ); + case 413: return makeRegisterExpression(amdgpu_gfx940::v157, output_vec_len ); + case 414: return makeRegisterExpression(amdgpu_gfx940::v158, output_vec_len ); + case 415: return makeRegisterExpression(amdgpu_gfx940::v159, output_vec_len ); + case 416: return makeRegisterExpression(amdgpu_gfx940::v160, output_vec_len ); + case 417: return makeRegisterExpression(amdgpu_gfx940::v161, output_vec_len ); + case 418: return makeRegisterExpression(amdgpu_gfx940::v162, output_vec_len ); + case 419: return makeRegisterExpression(amdgpu_gfx940::v163, output_vec_len ); + case 420: return makeRegisterExpression(amdgpu_gfx940::v164, output_vec_len ); + case 421: return makeRegisterExpression(amdgpu_gfx940::v165, output_vec_len ); + case 422: return makeRegisterExpression(amdgpu_gfx940::v166, output_vec_len ); + case 423: return makeRegisterExpression(amdgpu_gfx940::v167, output_vec_len ); + case 424: return makeRegisterExpression(amdgpu_gfx940::v168, output_vec_len ); + case 425: return makeRegisterExpression(amdgpu_gfx940::v169, output_vec_len ); + case 426: return makeRegisterExpression(amdgpu_gfx940::v170, output_vec_len ); + case 427: return makeRegisterExpression(amdgpu_gfx940::v171, output_vec_len ); + case 428: return makeRegisterExpression(amdgpu_gfx940::v172, output_vec_len ); + case 429: return makeRegisterExpression(amdgpu_gfx940::v173, output_vec_len ); + case 430: return makeRegisterExpression(amdgpu_gfx940::v174, output_vec_len ); + case 431: return makeRegisterExpression(amdgpu_gfx940::v175, output_vec_len ); + case 432: return makeRegisterExpression(amdgpu_gfx940::v176, output_vec_len ); + case 433: return makeRegisterExpression(amdgpu_gfx940::v177, output_vec_len ); + case 434: return makeRegisterExpression(amdgpu_gfx940::v178, output_vec_len ); + case 435: return makeRegisterExpression(amdgpu_gfx940::v179, output_vec_len ); + case 436: return makeRegisterExpression(amdgpu_gfx940::v180, output_vec_len ); + case 437: return makeRegisterExpression(amdgpu_gfx940::v181, output_vec_len ); + case 438: return makeRegisterExpression(amdgpu_gfx940::v182, output_vec_len ); + case 439: return makeRegisterExpression(amdgpu_gfx940::v183, output_vec_len ); + case 440: return makeRegisterExpression(amdgpu_gfx940::v184, output_vec_len ); + case 441: return makeRegisterExpression(amdgpu_gfx940::v185, output_vec_len ); + case 442: return makeRegisterExpression(amdgpu_gfx940::v186, output_vec_len ); + case 443: return makeRegisterExpression(amdgpu_gfx940::v187, output_vec_len ); + case 444: return makeRegisterExpression(amdgpu_gfx940::v188, output_vec_len ); + case 445: return makeRegisterExpression(amdgpu_gfx940::v189, output_vec_len ); + case 446: return makeRegisterExpression(amdgpu_gfx940::v190, output_vec_len ); + case 447: return makeRegisterExpression(amdgpu_gfx940::v191, output_vec_len ); + case 448: return makeRegisterExpression(amdgpu_gfx940::v192, output_vec_len ); + case 449: return makeRegisterExpression(amdgpu_gfx940::v193, output_vec_len ); + case 450: return makeRegisterExpression(amdgpu_gfx940::v194, output_vec_len ); + case 451: return makeRegisterExpression(amdgpu_gfx940::v195, output_vec_len ); + case 452: return makeRegisterExpression(amdgpu_gfx940::v196, output_vec_len ); + case 453: return makeRegisterExpression(amdgpu_gfx940::v197, output_vec_len ); + case 454: return makeRegisterExpression(amdgpu_gfx940::v198, output_vec_len ); + case 455: return makeRegisterExpression(amdgpu_gfx940::v199, output_vec_len ); + case 456: return makeRegisterExpression(amdgpu_gfx940::v200, output_vec_len ); + case 457: return makeRegisterExpression(amdgpu_gfx940::v201, output_vec_len ); + case 458: return makeRegisterExpression(amdgpu_gfx940::v202, output_vec_len ); + case 459: return makeRegisterExpression(amdgpu_gfx940::v203, output_vec_len ); + case 460: return makeRegisterExpression(amdgpu_gfx940::v204, output_vec_len ); + case 461: return makeRegisterExpression(amdgpu_gfx940::v205, output_vec_len ); + case 462: return makeRegisterExpression(amdgpu_gfx940::v206, output_vec_len ); + case 463: return makeRegisterExpression(amdgpu_gfx940::v207, output_vec_len ); + case 464: return makeRegisterExpression(amdgpu_gfx940::v208, output_vec_len ); + case 465: return makeRegisterExpression(amdgpu_gfx940::v209, output_vec_len ); + case 466: return makeRegisterExpression(amdgpu_gfx940::v210, output_vec_len ); + case 467: return makeRegisterExpression(amdgpu_gfx940::v211, output_vec_len ); + case 468: return makeRegisterExpression(amdgpu_gfx940::v212, output_vec_len ); + case 469: return makeRegisterExpression(amdgpu_gfx940::v213, output_vec_len ); + case 470: return makeRegisterExpression(amdgpu_gfx940::v214, output_vec_len ); + case 471: return makeRegisterExpression(amdgpu_gfx940::v215, output_vec_len ); + case 472: return makeRegisterExpression(amdgpu_gfx940::v216, output_vec_len ); + case 473: return makeRegisterExpression(amdgpu_gfx940::v217, output_vec_len ); + case 474: return makeRegisterExpression(amdgpu_gfx940::v218, output_vec_len ); + case 475: return makeRegisterExpression(amdgpu_gfx940::v219, output_vec_len ); + case 476: return makeRegisterExpression(amdgpu_gfx940::v220, output_vec_len ); + case 477: return makeRegisterExpression(amdgpu_gfx940::v221, output_vec_len ); + case 478: return makeRegisterExpression(amdgpu_gfx940::v222, output_vec_len ); + case 479: return makeRegisterExpression(amdgpu_gfx940::v223, output_vec_len ); + case 480: return makeRegisterExpression(amdgpu_gfx940::v224, output_vec_len ); + case 481: return makeRegisterExpression(amdgpu_gfx940::v225, output_vec_len ); + case 482: return makeRegisterExpression(amdgpu_gfx940::v226, output_vec_len ); + case 483: return makeRegisterExpression(amdgpu_gfx940::v227, output_vec_len ); + case 484: return makeRegisterExpression(amdgpu_gfx940::v228, output_vec_len ); + case 485: return makeRegisterExpression(amdgpu_gfx940::v229, output_vec_len ); + case 486: return makeRegisterExpression(amdgpu_gfx940::v230, output_vec_len ); + case 487: return makeRegisterExpression(amdgpu_gfx940::v231, output_vec_len ); + case 488: return makeRegisterExpression(amdgpu_gfx940::v232, output_vec_len ); + case 489: return makeRegisterExpression(amdgpu_gfx940::v233, output_vec_len ); + case 490: return makeRegisterExpression(amdgpu_gfx940::v234, output_vec_len ); + case 491: return makeRegisterExpression(amdgpu_gfx940::v235, output_vec_len ); + case 492: return makeRegisterExpression(amdgpu_gfx940::v236, output_vec_len ); + case 493: return makeRegisterExpression(amdgpu_gfx940::v237, output_vec_len ); + case 494: return makeRegisterExpression(amdgpu_gfx940::v238, output_vec_len ); + case 495: return makeRegisterExpression(amdgpu_gfx940::v239, output_vec_len ); + case 496: return makeRegisterExpression(amdgpu_gfx940::v240, output_vec_len ); + case 497: return makeRegisterExpression(amdgpu_gfx940::v241, output_vec_len ); + case 498: return makeRegisterExpression(amdgpu_gfx940::v242, output_vec_len ); + case 499: return makeRegisterExpression(amdgpu_gfx940::v243, output_vec_len ); + case 500: return makeRegisterExpression(amdgpu_gfx940::v244, output_vec_len ); + case 501: return makeRegisterExpression(amdgpu_gfx940::v245, output_vec_len ); + case 502: return makeRegisterExpression(amdgpu_gfx940::v246, output_vec_len ); + case 503: return makeRegisterExpression(amdgpu_gfx940::v247, output_vec_len ); + case 504: return makeRegisterExpression(amdgpu_gfx940::v248, output_vec_len ); + case 505: return makeRegisterExpression(amdgpu_gfx940::v249, output_vec_len ); + case 506: return makeRegisterExpression(amdgpu_gfx940::v250, output_vec_len ); + case 507: return makeRegisterExpression(amdgpu_gfx940::v251, output_vec_len ); + case 508: return makeRegisterExpression(amdgpu_gfx940::v252, output_vec_len ); + case 509: return makeRegisterExpression(amdgpu_gfx940::v253, output_vec_len ); + case 510: return makeRegisterExpression(amdgpu_gfx940::v254, output_vec_len ); + case 511: return makeRegisterExpression(amdgpu_gfx940::v255, output_vec_len ); + case 768: return makeRegisterExpression(amdgpu_gfx940::acc0, output_vec_len ); + case 769: return makeRegisterExpression(amdgpu_gfx940::acc1, output_vec_len ); + case 770: return makeRegisterExpression(amdgpu_gfx940::acc2, output_vec_len ); + case 771: return makeRegisterExpression(amdgpu_gfx940::acc3, output_vec_len ); + case 772: return makeRegisterExpression(amdgpu_gfx940::acc4, output_vec_len ); + case 773: return makeRegisterExpression(amdgpu_gfx940::acc5, output_vec_len ); + case 774: return makeRegisterExpression(amdgpu_gfx940::acc6, output_vec_len ); + case 775: return makeRegisterExpression(amdgpu_gfx940::acc7, output_vec_len ); + case 776: return makeRegisterExpression(amdgpu_gfx940::acc8, output_vec_len ); + case 777: return makeRegisterExpression(amdgpu_gfx940::acc9, output_vec_len ); + case 778: return makeRegisterExpression(amdgpu_gfx940::acc10, output_vec_len ); + case 779: return makeRegisterExpression(amdgpu_gfx940::acc11, output_vec_len ); + case 780: return makeRegisterExpression(amdgpu_gfx940::acc12, output_vec_len ); + case 781: return makeRegisterExpression(amdgpu_gfx940::acc13, output_vec_len ); + case 782: return makeRegisterExpression(amdgpu_gfx940::acc14, output_vec_len ); + case 783: return makeRegisterExpression(amdgpu_gfx940::acc15, output_vec_len ); + case 784: return makeRegisterExpression(amdgpu_gfx940::acc16, output_vec_len ); + case 785: return makeRegisterExpression(amdgpu_gfx940::acc17, output_vec_len ); + case 786: return makeRegisterExpression(amdgpu_gfx940::acc18, output_vec_len ); + case 787: return makeRegisterExpression(amdgpu_gfx940::acc19, output_vec_len ); + case 788: return makeRegisterExpression(amdgpu_gfx940::acc20, output_vec_len ); + case 789: return makeRegisterExpression(amdgpu_gfx940::acc21, output_vec_len ); + case 790: return makeRegisterExpression(amdgpu_gfx940::acc22, output_vec_len ); + case 791: return makeRegisterExpression(amdgpu_gfx940::acc23, output_vec_len ); + case 792: return makeRegisterExpression(amdgpu_gfx940::acc24, output_vec_len ); + case 793: return makeRegisterExpression(amdgpu_gfx940::acc25, output_vec_len ); + case 794: return makeRegisterExpression(amdgpu_gfx940::acc26, output_vec_len ); + case 795: return makeRegisterExpression(amdgpu_gfx940::acc27, output_vec_len ); + case 796: return makeRegisterExpression(amdgpu_gfx940::acc28, output_vec_len ); + case 797: return makeRegisterExpression(amdgpu_gfx940::acc29, output_vec_len ); + case 798: return makeRegisterExpression(amdgpu_gfx940::acc30, output_vec_len ); + case 799: return makeRegisterExpression(amdgpu_gfx940::acc31, output_vec_len ); + case 800: return makeRegisterExpression(amdgpu_gfx940::acc32, output_vec_len ); + case 801: return makeRegisterExpression(amdgpu_gfx940::acc33, output_vec_len ); + case 802: return makeRegisterExpression(amdgpu_gfx940::acc34, output_vec_len ); + case 803: return makeRegisterExpression(amdgpu_gfx940::acc35, output_vec_len ); + case 804: return makeRegisterExpression(amdgpu_gfx940::acc36, output_vec_len ); + case 805: return makeRegisterExpression(amdgpu_gfx940::acc37, output_vec_len ); + case 806: return makeRegisterExpression(amdgpu_gfx940::acc38, output_vec_len ); + case 807: return makeRegisterExpression(amdgpu_gfx940::acc39, output_vec_len ); + case 808: return makeRegisterExpression(amdgpu_gfx940::acc40, output_vec_len ); + case 809: return makeRegisterExpression(amdgpu_gfx940::acc41, output_vec_len ); + case 810: return makeRegisterExpression(amdgpu_gfx940::acc42, output_vec_len ); + case 811: return makeRegisterExpression(amdgpu_gfx940::acc43, output_vec_len ); + case 812: return makeRegisterExpression(amdgpu_gfx940::acc44, output_vec_len ); + case 813: return makeRegisterExpression(amdgpu_gfx940::acc45, output_vec_len ); + case 814: return makeRegisterExpression(amdgpu_gfx940::acc46, output_vec_len ); + case 815: return makeRegisterExpression(amdgpu_gfx940::acc47, output_vec_len ); + case 816: return makeRegisterExpression(amdgpu_gfx940::acc48, output_vec_len ); + case 817: return makeRegisterExpression(amdgpu_gfx940::acc49, output_vec_len ); + case 818: return makeRegisterExpression(amdgpu_gfx940::acc50, output_vec_len ); + case 819: return makeRegisterExpression(amdgpu_gfx940::acc51, output_vec_len ); + case 820: return makeRegisterExpression(amdgpu_gfx940::acc52, output_vec_len ); + case 821: return makeRegisterExpression(amdgpu_gfx940::acc53, output_vec_len ); + case 822: return makeRegisterExpression(amdgpu_gfx940::acc54, output_vec_len ); + case 823: return makeRegisterExpression(amdgpu_gfx940::acc55, output_vec_len ); + case 824: return makeRegisterExpression(amdgpu_gfx940::acc56, output_vec_len ); + case 825: return makeRegisterExpression(amdgpu_gfx940::acc57, output_vec_len ); + case 826: return makeRegisterExpression(amdgpu_gfx940::acc58, output_vec_len ); + case 827: return makeRegisterExpression(amdgpu_gfx940::acc59, output_vec_len ); + case 828: return makeRegisterExpression(amdgpu_gfx940::acc60, output_vec_len ); + case 829: return makeRegisterExpression(amdgpu_gfx940::acc61, output_vec_len ); + case 830: return makeRegisterExpression(amdgpu_gfx940::acc62, output_vec_len ); + case 831: return makeRegisterExpression(amdgpu_gfx940::acc63, output_vec_len ); + case 832: return makeRegisterExpression(amdgpu_gfx940::acc64, output_vec_len ); + case 833: return makeRegisterExpression(amdgpu_gfx940::acc65, output_vec_len ); + case 834: return makeRegisterExpression(amdgpu_gfx940::acc66, output_vec_len ); + case 835: return makeRegisterExpression(amdgpu_gfx940::acc67, output_vec_len ); + case 836: return makeRegisterExpression(amdgpu_gfx940::acc68, output_vec_len ); + case 837: return makeRegisterExpression(amdgpu_gfx940::acc69, output_vec_len ); + case 838: return makeRegisterExpression(amdgpu_gfx940::acc70, output_vec_len ); + case 839: return makeRegisterExpression(amdgpu_gfx940::acc71, output_vec_len ); + case 840: return makeRegisterExpression(amdgpu_gfx940::acc72, output_vec_len ); + case 841: return makeRegisterExpression(amdgpu_gfx940::acc73, output_vec_len ); + case 842: return makeRegisterExpression(amdgpu_gfx940::acc74, output_vec_len ); + case 843: return makeRegisterExpression(amdgpu_gfx940::acc75, output_vec_len ); + case 844: return makeRegisterExpression(amdgpu_gfx940::acc76, output_vec_len ); + case 845: return makeRegisterExpression(amdgpu_gfx940::acc77, output_vec_len ); + case 846: return makeRegisterExpression(amdgpu_gfx940::acc78, output_vec_len ); + case 847: return makeRegisterExpression(amdgpu_gfx940::acc79, output_vec_len ); + case 848: return makeRegisterExpression(amdgpu_gfx940::acc80, output_vec_len ); + case 849: return makeRegisterExpression(amdgpu_gfx940::acc81, output_vec_len ); + case 850: return makeRegisterExpression(amdgpu_gfx940::acc82, output_vec_len ); + case 851: return makeRegisterExpression(amdgpu_gfx940::acc83, output_vec_len ); + case 852: return makeRegisterExpression(amdgpu_gfx940::acc84, output_vec_len ); + case 853: return makeRegisterExpression(amdgpu_gfx940::acc85, output_vec_len ); + case 854: return makeRegisterExpression(amdgpu_gfx940::acc86, output_vec_len ); + case 855: return makeRegisterExpression(amdgpu_gfx940::acc87, output_vec_len ); + case 856: return makeRegisterExpression(amdgpu_gfx940::acc88, output_vec_len ); + case 857: return makeRegisterExpression(amdgpu_gfx940::acc89, output_vec_len ); + case 858: return makeRegisterExpression(amdgpu_gfx940::acc90, output_vec_len ); + case 859: return makeRegisterExpression(amdgpu_gfx940::acc91, output_vec_len ); + case 860: return makeRegisterExpression(amdgpu_gfx940::acc92, output_vec_len ); + case 861: return makeRegisterExpression(amdgpu_gfx940::acc93, output_vec_len ); + case 862: return makeRegisterExpression(amdgpu_gfx940::acc94, output_vec_len ); + case 863: return makeRegisterExpression(amdgpu_gfx940::acc95, output_vec_len ); + case 864: return makeRegisterExpression(amdgpu_gfx940::acc96, output_vec_len ); + case 865: return makeRegisterExpression(amdgpu_gfx940::acc97, output_vec_len ); + case 866: return makeRegisterExpression(amdgpu_gfx940::acc98, output_vec_len ); + case 867: return makeRegisterExpression(amdgpu_gfx940::acc99, output_vec_len ); + case 868: return makeRegisterExpression(amdgpu_gfx940::acc100, output_vec_len ); + case 869: return makeRegisterExpression(amdgpu_gfx940::acc101, output_vec_len ); + case 870: return makeRegisterExpression(amdgpu_gfx940::acc102, output_vec_len ); + case 871: return makeRegisterExpression(amdgpu_gfx940::acc103, output_vec_len ); + case 872: return makeRegisterExpression(amdgpu_gfx940::acc104, output_vec_len ); + case 873: return makeRegisterExpression(amdgpu_gfx940::acc105, output_vec_len ); + case 874: return makeRegisterExpression(amdgpu_gfx940::acc106, output_vec_len ); + case 875: return makeRegisterExpression(amdgpu_gfx940::acc107, output_vec_len ); + case 876: return makeRegisterExpression(amdgpu_gfx940::acc108, output_vec_len ); + case 877: return makeRegisterExpression(amdgpu_gfx940::acc109, output_vec_len ); + case 878: return makeRegisterExpression(amdgpu_gfx940::acc110, output_vec_len ); + case 879: return makeRegisterExpression(amdgpu_gfx940::acc111, output_vec_len ); + case 880: return makeRegisterExpression(amdgpu_gfx940::acc112, output_vec_len ); + case 881: return makeRegisterExpression(amdgpu_gfx940::acc113, output_vec_len ); + case 882: return makeRegisterExpression(amdgpu_gfx940::acc114, output_vec_len ); + case 883: return makeRegisterExpression(amdgpu_gfx940::acc115, output_vec_len ); + case 884: return makeRegisterExpression(amdgpu_gfx940::acc116, output_vec_len ); + case 885: return makeRegisterExpression(amdgpu_gfx940::acc117, output_vec_len ); + case 886: return makeRegisterExpression(amdgpu_gfx940::acc118, output_vec_len ); + case 887: return makeRegisterExpression(amdgpu_gfx940::acc119, output_vec_len ); + case 888: return makeRegisterExpression(amdgpu_gfx940::acc120, output_vec_len ); + case 889: return makeRegisterExpression(amdgpu_gfx940::acc121, output_vec_len ); + case 890: return makeRegisterExpression(amdgpu_gfx940::acc122, output_vec_len ); + case 891: return makeRegisterExpression(amdgpu_gfx940::acc123, output_vec_len ); + case 892: return makeRegisterExpression(amdgpu_gfx940::acc124, output_vec_len ); + case 893: return makeRegisterExpression(amdgpu_gfx940::acc125, output_vec_len ); + case 894: return makeRegisterExpression(amdgpu_gfx940::acc126, output_vec_len ); + case 895: return makeRegisterExpression(amdgpu_gfx940::acc127, output_vec_len ); + case 896: return makeRegisterExpression(amdgpu_gfx940::acc128, output_vec_len ); + case 897: return makeRegisterExpression(amdgpu_gfx940::acc129, output_vec_len ); + case 898: return makeRegisterExpression(amdgpu_gfx940::acc130, output_vec_len ); + case 899: return makeRegisterExpression(amdgpu_gfx940::acc131, output_vec_len ); + case 900: return makeRegisterExpression(amdgpu_gfx940::acc132, output_vec_len ); + case 901: return makeRegisterExpression(amdgpu_gfx940::acc133, output_vec_len ); + case 902: return makeRegisterExpression(amdgpu_gfx940::acc134, output_vec_len ); + case 903: return makeRegisterExpression(amdgpu_gfx940::acc135, output_vec_len ); + case 904: return makeRegisterExpression(amdgpu_gfx940::acc136, output_vec_len ); + case 905: return makeRegisterExpression(amdgpu_gfx940::acc137, output_vec_len ); + case 906: return makeRegisterExpression(amdgpu_gfx940::acc138, output_vec_len ); + case 907: return makeRegisterExpression(amdgpu_gfx940::acc139, output_vec_len ); + case 908: return makeRegisterExpression(amdgpu_gfx940::acc140, output_vec_len ); + case 909: return makeRegisterExpression(amdgpu_gfx940::acc141, output_vec_len ); + case 910: return makeRegisterExpression(amdgpu_gfx940::acc142, output_vec_len ); + case 911: return makeRegisterExpression(amdgpu_gfx940::acc143, output_vec_len ); + case 912: return makeRegisterExpression(amdgpu_gfx940::acc144, output_vec_len ); + case 913: return makeRegisterExpression(amdgpu_gfx940::acc145, output_vec_len ); + case 914: return makeRegisterExpression(amdgpu_gfx940::acc146, output_vec_len ); + case 915: return makeRegisterExpression(amdgpu_gfx940::acc147, output_vec_len ); + case 916: return makeRegisterExpression(amdgpu_gfx940::acc148, output_vec_len ); + case 917: return makeRegisterExpression(amdgpu_gfx940::acc149, output_vec_len ); + case 918: return makeRegisterExpression(amdgpu_gfx940::acc150, output_vec_len ); + case 919: return makeRegisterExpression(amdgpu_gfx940::acc151, output_vec_len ); + case 920: return makeRegisterExpression(amdgpu_gfx940::acc152, output_vec_len ); + case 921: return makeRegisterExpression(amdgpu_gfx940::acc153, output_vec_len ); + case 922: return makeRegisterExpression(amdgpu_gfx940::acc154, output_vec_len ); + case 923: return makeRegisterExpression(amdgpu_gfx940::acc155, output_vec_len ); + case 924: return makeRegisterExpression(amdgpu_gfx940::acc156, output_vec_len ); + case 925: return makeRegisterExpression(amdgpu_gfx940::acc157, output_vec_len ); + case 926: return makeRegisterExpression(amdgpu_gfx940::acc158, output_vec_len ); + case 927: return makeRegisterExpression(amdgpu_gfx940::acc159, output_vec_len ); + case 928: return makeRegisterExpression(amdgpu_gfx940::acc160, output_vec_len ); + case 929: return makeRegisterExpression(amdgpu_gfx940::acc161, output_vec_len ); + case 930: return makeRegisterExpression(amdgpu_gfx940::acc162, output_vec_len ); + case 931: return makeRegisterExpression(amdgpu_gfx940::acc163, output_vec_len ); + case 932: return makeRegisterExpression(amdgpu_gfx940::acc164, output_vec_len ); + case 933: return makeRegisterExpression(amdgpu_gfx940::acc165, output_vec_len ); + case 934: return makeRegisterExpression(amdgpu_gfx940::acc166, output_vec_len ); + case 935: return makeRegisterExpression(amdgpu_gfx940::acc167, output_vec_len ); + case 936: return makeRegisterExpression(amdgpu_gfx940::acc168, output_vec_len ); + case 937: return makeRegisterExpression(amdgpu_gfx940::acc169, output_vec_len ); + case 938: return makeRegisterExpression(amdgpu_gfx940::acc170, output_vec_len ); + case 939: return makeRegisterExpression(amdgpu_gfx940::acc171, output_vec_len ); + case 940: return makeRegisterExpression(amdgpu_gfx940::acc172, output_vec_len ); + case 941: return makeRegisterExpression(amdgpu_gfx940::acc173, output_vec_len ); + case 942: return makeRegisterExpression(amdgpu_gfx940::acc174, output_vec_len ); + case 943: return makeRegisterExpression(amdgpu_gfx940::acc175, output_vec_len ); + case 944: return makeRegisterExpression(amdgpu_gfx940::acc176, output_vec_len ); + case 945: return makeRegisterExpression(amdgpu_gfx940::acc177, output_vec_len ); + case 946: return makeRegisterExpression(amdgpu_gfx940::acc178, output_vec_len ); + case 947: return makeRegisterExpression(amdgpu_gfx940::acc179, output_vec_len ); + case 948: return makeRegisterExpression(amdgpu_gfx940::acc180, output_vec_len ); + case 949: return makeRegisterExpression(amdgpu_gfx940::acc181, output_vec_len ); + case 950: return makeRegisterExpression(amdgpu_gfx940::acc182, output_vec_len ); + case 951: return makeRegisterExpression(amdgpu_gfx940::acc183, output_vec_len ); + case 952: return makeRegisterExpression(amdgpu_gfx940::acc184, output_vec_len ); + case 953: return makeRegisterExpression(amdgpu_gfx940::acc185, output_vec_len ); + case 954: return makeRegisterExpression(amdgpu_gfx940::acc186, output_vec_len ); + case 955: return makeRegisterExpression(amdgpu_gfx940::acc187, output_vec_len ); + case 956: return makeRegisterExpression(amdgpu_gfx940::acc188, output_vec_len ); + case 957: return makeRegisterExpression(amdgpu_gfx940::acc189, output_vec_len ); + case 958: return makeRegisterExpression(amdgpu_gfx940::acc190, output_vec_len ); + case 959: return makeRegisterExpression(amdgpu_gfx940::acc191, output_vec_len ); + case 960: return makeRegisterExpression(amdgpu_gfx940::acc192, output_vec_len ); + case 961: return makeRegisterExpression(amdgpu_gfx940::acc193, output_vec_len ); + case 962: return makeRegisterExpression(amdgpu_gfx940::acc194, output_vec_len ); + case 963: return makeRegisterExpression(amdgpu_gfx940::acc195, output_vec_len ); + case 964: return makeRegisterExpression(amdgpu_gfx940::acc196, output_vec_len ); + case 965: return makeRegisterExpression(amdgpu_gfx940::acc197, output_vec_len ); + case 966: return makeRegisterExpression(amdgpu_gfx940::acc198, output_vec_len ); + case 967: return makeRegisterExpression(amdgpu_gfx940::acc199, output_vec_len ); + case 968: return makeRegisterExpression(amdgpu_gfx940::acc200, output_vec_len ); + case 969: return makeRegisterExpression(amdgpu_gfx940::acc201, output_vec_len ); + case 970: return makeRegisterExpression(amdgpu_gfx940::acc202, output_vec_len ); + case 971: return makeRegisterExpression(amdgpu_gfx940::acc203, output_vec_len ); + case 972: return makeRegisterExpression(amdgpu_gfx940::acc204, output_vec_len ); + case 973: return makeRegisterExpression(amdgpu_gfx940::acc205, output_vec_len ); + case 974: return makeRegisterExpression(amdgpu_gfx940::acc206, output_vec_len ); + case 975: return makeRegisterExpression(amdgpu_gfx940::acc207, output_vec_len ); + case 976: return makeRegisterExpression(amdgpu_gfx940::acc208, output_vec_len ); + case 977: return makeRegisterExpression(amdgpu_gfx940::acc209, output_vec_len ); + case 978: return makeRegisterExpression(amdgpu_gfx940::acc210, output_vec_len ); + case 979: return makeRegisterExpression(amdgpu_gfx940::acc211, output_vec_len ); + case 980: return makeRegisterExpression(amdgpu_gfx940::acc212, output_vec_len ); + case 981: return makeRegisterExpression(amdgpu_gfx940::acc213, output_vec_len ); + case 982: return makeRegisterExpression(amdgpu_gfx940::acc214, output_vec_len ); + case 983: return makeRegisterExpression(amdgpu_gfx940::acc215, output_vec_len ); + case 984: return makeRegisterExpression(amdgpu_gfx940::acc216, output_vec_len ); + case 985: return makeRegisterExpression(amdgpu_gfx940::acc217, output_vec_len ); + case 986: return makeRegisterExpression(amdgpu_gfx940::acc218, output_vec_len ); + case 987: return makeRegisterExpression(amdgpu_gfx940::acc219, output_vec_len ); + case 988: return makeRegisterExpression(amdgpu_gfx940::acc220, output_vec_len ); + case 989: return makeRegisterExpression(amdgpu_gfx940::acc221, output_vec_len ); + case 990: return makeRegisterExpression(amdgpu_gfx940::acc222, output_vec_len ); + case 991: return makeRegisterExpression(amdgpu_gfx940::acc223, output_vec_len ); + case 992: return makeRegisterExpression(amdgpu_gfx940::acc224, output_vec_len ); + case 993: return makeRegisterExpression(amdgpu_gfx940::acc225, output_vec_len ); + case 994: return makeRegisterExpression(amdgpu_gfx940::acc226, output_vec_len ); + case 995: return makeRegisterExpression(amdgpu_gfx940::acc227, output_vec_len ); + case 996: return makeRegisterExpression(amdgpu_gfx940::acc228, output_vec_len ); + case 997: return makeRegisterExpression(amdgpu_gfx940::acc229, output_vec_len ); + case 998: return makeRegisterExpression(amdgpu_gfx940::acc230, output_vec_len ); + case 999: return makeRegisterExpression(amdgpu_gfx940::acc231, output_vec_len ); + case 1000: return makeRegisterExpression(amdgpu_gfx940::acc232, output_vec_len ); + case 1001: return makeRegisterExpression(amdgpu_gfx940::acc233, output_vec_len ); + case 1002: return makeRegisterExpression(amdgpu_gfx940::acc234, output_vec_len ); + case 1003: return makeRegisterExpression(amdgpu_gfx940::acc235, output_vec_len ); + case 1004: return makeRegisterExpression(amdgpu_gfx940::acc236, output_vec_len ); + case 1005: return makeRegisterExpression(amdgpu_gfx940::acc237, output_vec_len ); + case 1006: return makeRegisterExpression(amdgpu_gfx940::acc238, output_vec_len ); + case 1007: return makeRegisterExpression(amdgpu_gfx940::acc239, output_vec_len ); + case 1008: return makeRegisterExpression(amdgpu_gfx940::acc240, output_vec_len ); + case 1009: return makeRegisterExpression(amdgpu_gfx940::acc241, output_vec_len ); + case 1010: return makeRegisterExpression(amdgpu_gfx940::acc242, output_vec_len ); + case 1011: return makeRegisterExpression(amdgpu_gfx940::acc243, output_vec_len ); + case 1012: return makeRegisterExpression(amdgpu_gfx940::acc244, output_vec_len ); + case 1013: return makeRegisterExpression(amdgpu_gfx940::acc245, output_vec_len ); + case 1014: return makeRegisterExpression(amdgpu_gfx940::acc246, output_vec_len ); + case 1015: return makeRegisterExpression(amdgpu_gfx940::acc247, output_vec_len ); + case 1016: return makeRegisterExpression(amdgpu_gfx940::acc248, output_vec_len ); + case 1017: return makeRegisterExpression(amdgpu_gfx940::acc249, output_vec_len ); + case 1018: return makeRegisterExpression(amdgpu_gfx940::acc250, output_vec_len ); + case 1019: return makeRegisterExpression(amdgpu_gfx940::acc251, output_vec_len ); + case 1020: return makeRegisterExpression(amdgpu_gfx940::acc252, output_vec_len ); + case 1021: return makeRegisterExpression(amdgpu_gfx940::acc253, output_vec_len ); + case 1022: return makeRegisterExpression(amdgpu_gfx940::acc254, output_vec_len ); + case 1023: return makeRegisterExpression(amdgpu_gfx940::acc255, output_vec_len ); + default: return makeRegisterExpression(amdgpu_gfx940::invalid); + } + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx940::decodeOPR_SRC_VGPR_OR_ACCVGPR_OR_CONST(uint64_t input, uint32_t output_vec_len) + { + switch (input) { + case 256: return makeRegisterExpression(amdgpu_gfx940::v0, output_vec_len ); + case 257: return makeRegisterExpression(amdgpu_gfx940::v1, output_vec_len ); + case 258: return makeRegisterExpression(amdgpu_gfx940::v2, output_vec_len ); + case 259: return makeRegisterExpression(amdgpu_gfx940::v3, output_vec_len ); + case 260: return makeRegisterExpression(amdgpu_gfx940::v4, output_vec_len ); + case 261: return makeRegisterExpression(amdgpu_gfx940::v5, output_vec_len ); + case 262: return makeRegisterExpression(amdgpu_gfx940::v6, output_vec_len ); + case 263: return makeRegisterExpression(amdgpu_gfx940::v7, output_vec_len ); + case 264: return makeRegisterExpression(amdgpu_gfx940::v8, output_vec_len ); + case 265: return makeRegisterExpression(amdgpu_gfx940::v9, output_vec_len ); + case 266: return makeRegisterExpression(amdgpu_gfx940::v10, output_vec_len ); + case 267: return makeRegisterExpression(amdgpu_gfx940::v11, output_vec_len ); + case 268: return makeRegisterExpression(amdgpu_gfx940::v12, output_vec_len ); + case 269: return makeRegisterExpression(amdgpu_gfx940::v13, output_vec_len ); + case 270: return makeRegisterExpression(amdgpu_gfx940::v14, output_vec_len ); + case 271: return makeRegisterExpression(amdgpu_gfx940::v15, output_vec_len ); + case 272: return makeRegisterExpression(amdgpu_gfx940::v16, output_vec_len ); + case 273: return makeRegisterExpression(amdgpu_gfx940::v17, output_vec_len ); + case 274: return makeRegisterExpression(amdgpu_gfx940::v18, output_vec_len ); + case 275: return makeRegisterExpression(amdgpu_gfx940::v19, output_vec_len ); + case 276: return makeRegisterExpression(amdgpu_gfx940::v20, output_vec_len ); + case 277: return makeRegisterExpression(amdgpu_gfx940::v21, output_vec_len ); + case 278: return makeRegisterExpression(amdgpu_gfx940::v22, output_vec_len ); + case 279: return makeRegisterExpression(amdgpu_gfx940::v23, output_vec_len ); + case 280: return makeRegisterExpression(amdgpu_gfx940::v24, output_vec_len ); + case 281: return makeRegisterExpression(amdgpu_gfx940::v25, output_vec_len ); + case 282: return makeRegisterExpression(amdgpu_gfx940::v26, output_vec_len ); + case 283: return makeRegisterExpression(amdgpu_gfx940::v27, output_vec_len ); + case 284: return makeRegisterExpression(amdgpu_gfx940::v28, output_vec_len ); + case 285: return makeRegisterExpression(amdgpu_gfx940::v29, output_vec_len ); + case 286: return makeRegisterExpression(amdgpu_gfx940::v30, output_vec_len ); + case 287: return makeRegisterExpression(amdgpu_gfx940::v31, output_vec_len ); + case 288: return makeRegisterExpression(amdgpu_gfx940::v32, output_vec_len ); + case 289: return makeRegisterExpression(amdgpu_gfx940::v33, output_vec_len ); + case 290: return makeRegisterExpression(amdgpu_gfx940::v34, output_vec_len ); + case 291: return makeRegisterExpression(amdgpu_gfx940::v35, output_vec_len ); + case 292: return makeRegisterExpression(amdgpu_gfx940::v36, output_vec_len ); + case 293: return makeRegisterExpression(amdgpu_gfx940::v37, output_vec_len ); + case 294: return makeRegisterExpression(amdgpu_gfx940::v38, output_vec_len ); + case 295: return makeRegisterExpression(amdgpu_gfx940::v39, output_vec_len ); + case 296: return makeRegisterExpression(amdgpu_gfx940::v40, output_vec_len ); + case 297: return makeRegisterExpression(amdgpu_gfx940::v41, output_vec_len ); + case 298: return makeRegisterExpression(amdgpu_gfx940::v42, output_vec_len ); + case 299: return makeRegisterExpression(amdgpu_gfx940::v43, output_vec_len ); + case 300: return makeRegisterExpression(amdgpu_gfx940::v44, output_vec_len ); + case 301: return makeRegisterExpression(amdgpu_gfx940::v45, output_vec_len ); + case 302: return makeRegisterExpression(amdgpu_gfx940::v46, output_vec_len ); + case 303: return makeRegisterExpression(amdgpu_gfx940::v47, output_vec_len ); + case 304: return makeRegisterExpression(amdgpu_gfx940::v48, output_vec_len ); + case 305: return makeRegisterExpression(amdgpu_gfx940::v49, output_vec_len ); + case 306: return makeRegisterExpression(amdgpu_gfx940::v50, output_vec_len ); + case 307: return makeRegisterExpression(amdgpu_gfx940::v51, output_vec_len ); + case 308: return makeRegisterExpression(amdgpu_gfx940::v52, output_vec_len ); + case 309: return makeRegisterExpression(amdgpu_gfx940::v53, output_vec_len ); + case 310: return makeRegisterExpression(amdgpu_gfx940::v54, output_vec_len ); + case 311: return makeRegisterExpression(amdgpu_gfx940::v55, output_vec_len ); + case 312: return makeRegisterExpression(amdgpu_gfx940::v56, output_vec_len ); + case 313: return makeRegisterExpression(amdgpu_gfx940::v57, output_vec_len ); + case 314: return makeRegisterExpression(amdgpu_gfx940::v58, output_vec_len ); + case 315: return makeRegisterExpression(amdgpu_gfx940::v59, output_vec_len ); + case 316: return makeRegisterExpression(amdgpu_gfx940::v60, output_vec_len ); + case 317: return makeRegisterExpression(amdgpu_gfx940::v61, output_vec_len ); + case 318: return makeRegisterExpression(amdgpu_gfx940::v62, output_vec_len ); + case 319: return makeRegisterExpression(amdgpu_gfx940::v63, output_vec_len ); + case 320: return makeRegisterExpression(amdgpu_gfx940::v64, output_vec_len ); + case 321: return makeRegisterExpression(amdgpu_gfx940::v65, output_vec_len ); + case 322: return makeRegisterExpression(amdgpu_gfx940::v66, output_vec_len ); + case 323: return makeRegisterExpression(amdgpu_gfx940::v67, output_vec_len ); + case 324: return makeRegisterExpression(amdgpu_gfx940::v68, output_vec_len ); + case 325: return makeRegisterExpression(amdgpu_gfx940::v69, output_vec_len ); + case 326: return makeRegisterExpression(amdgpu_gfx940::v70, output_vec_len ); + case 327: return makeRegisterExpression(amdgpu_gfx940::v71, output_vec_len ); + case 328: return makeRegisterExpression(amdgpu_gfx940::v72, output_vec_len ); + case 329: return makeRegisterExpression(amdgpu_gfx940::v73, output_vec_len ); + case 330: return makeRegisterExpression(amdgpu_gfx940::v74, output_vec_len ); + case 331: return makeRegisterExpression(amdgpu_gfx940::v75, output_vec_len ); + case 332: return makeRegisterExpression(amdgpu_gfx940::v76, output_vec_len ); + case 333: return makeRegisterExpression(amdgpu_gfx940::v77, output_vec_len ); + case 334: return makeRegisterExpression(amdgpu_gfx940::v78, output_vec_len ); + case 335: return makeRegisterExpression(amdgpu_gfx940::v79, output_vec_len ); + case 336: return makeRegisterExpression(amdgpu_gfx940::v80, output_vec_len ); + case 337: return makeRegisterExpression(amdgpu_gfx940::v81, output_vec_len ); + case 338: return makeRegisterExpression(amdgpu_gfx940::v82, output_vec_len ); + case 339: return makeRegisterExpression(amdgpu_gfx940::v83, output_vec_len ); + case 340: return makeRegisterExpression(amdgpu_gfx940::v84, output_vec_len ); + case 341: return makeRegisterExpression(amdgpu_gfx940::v85, output_vec_len ); + case 342: return makeRegisterExpression(amdgpu_gfx940::v86, output_vec_len ); + case 343: return makeRegisterExpression(amdgpu_gfx940::v87, output_vec_len ); + case 344: return makeRegisterExpression(amdgpu_gfx940::v88, output_vec_len ); + case 345: return makeRegisterExpression(amdgpu_gfx940::v89, output_vec_len ); + case 346: return makeRegisterExpression(amdgpu_gfx940::v90, output_vec_len ); + case 347: return makeRegisterExpression(amdgpu_gfx940::v91, output_vec_len ); + case 348: return makeRegisterExpression(amdgpu_gfx940::v92, output_vec_len ); + case 349: return makeRegisterExpression(amdgpu_gfx940::v93, output_vec_len ); + case 350: return makeRegisterExpression(amdgpu_gfx940::v94, output_vec_len ); + case 351: return makeRegisterExpression(amdgpu_gfx940::v95, output_vec_len ); + case 352: return makeRegisterExpression(amdgpu_gfx940::v96, output_vec_len ); + case 353: return makeRegisterExpression(amdgpu_gfx940::v97, output_vec_len ); + case 354: return makeRegisterExpression(amdgpu_gfx940::v98, output_vec_len ); + case 355: return makeRegisterExpression(amdgpu_gfx940::v99, output_vec_len ); + case 356: return makeRegisterExpression(amdgpu_gfx940::v100, output_vec_len ); + case 357: return makeRegisterExpression(amdgpu_gfx940::v101, output_vec_len ); + case 358: return makeRegisterExpression(amdgpu_gfx940::v102, output_vec_len ); + case 359: return makeRegisterExpression(amdgpu_gfx940::v103, output_vec_len ); + case 360: return makeRegisterExpression(amdgpu_gfx940::v104, output_vec_len ); + case 361: return makeRegisterExpression(amdgpu_gfx940::v105, output_vec_len ); + case 362: return makeRegisterExpression(amdgpu_gfx940::v106, output_vec_len ); + case 363: return makeRegisterExpression(amdgpu_gfx940::v107, output_vec_len ); + case 364: return makeRegisterExpression(amdgpu_gfx940::v108, output_vec_len ); + case 365: return makeRegisterExpression(amdgpu_gfx940::v109, output_vec_len ); + case 366: return makeRegisterExpression(amdgpu_gfx940::v110, output_vec_len ); + case 367: return makeRegisterExpression(amdgpu_gfx940::v111, output_vec_len ); + case 368: return makeRegisterExpression(amdgpu_gfx940::v112, output_vec_len ); + case 369: return makeRegisterExpression(amdgpu_gfx940::v113, output_vec_len ); + case 370: return makeRegisterExpression(amdgpu_gfx940::v114, output_vec_len ); + case 371: return makeRegisterExpression(amdgpu_gfx940::v115, output_vec_len ); + case 372: return makeRegisterExpression(amdgpu_gfx940::v116, output_vec_len ); + case 373: return makeRegisterExpression(amdgpu_gfx940::v117, output_vec_len ); + case 374: return makeRegisterExpression(amdgpu_gfx940::v118, output_vec_len ); + case 375: return makeRegisterExpression(amdgpu_gfx940::v119, output_vec_len ); + case 376: return makeRegisterExpression(amdgpu_gfx940::v120, output_vec_len ); + case 377: return makeRegisterExpression(amdgpu_gfx940::v121, output_vec_len ); + case 378: return makeRegisterExpression(amdgpu_gfx940::v122, output_vec_len ); + case 379: return makeRegisterExpression(amdgpu_gfx940::v123, output_vec_len ); + case 380: return makeRegisterExpression(amdgpu_gfx940::v124, output_vec_len ); + case 381: return makeRegisterExpression(amdgpu_gfx940::v125, output_vec_len ); + case 382: return makeRegisterExpression(amdgpu_gfx940::v126, output_vec_len ); + case 383: return makeRegisterExpression(amdgpu_gfx940::v127, output_vec_len ); + case 384: return makeRegisterExpression(amdgpu_gfx940::v128, output_vec_len ); + case 385: return makeRegisterExpression(amdgpu_gfx940::v129, output_vec_len ); + case 386: return makeRegisterExpression(amdgpu_gfx940::v130, output_vec_len ); + case 387: return makeRegisterExpression(amdgpu_gfx940::v131, output_vec_len ); + case 388: return makeRegisterExpression(amdgpu_gfx940::v132, output_vec_len ); + case 389: return makeRegisterExpression(amdgpu_gfx940::v133, output_vec_len ); + case 390: return makeRegisterExpression(amdgpu_gfx940::v134, output_vec_len ); + case 391: return makeRegisterExpression(amdgpu_gfx940::v135, output_vec_len ); + case 392: return makeRegisterExpression(amdgpu_gfx940::v136, output_vec_len ); + case 393: return makeRegisterExpression(amdgpu_gfx940::v137, output_vec_len ); + case 394: return makeRegisterExpression(amdgpu_gfx940::v138, output_vec_len ); + case 395: return makeRegisterExpression(amdgpu_gfx940::v139, output_vec_len ); + case 396: return makeRegisterExpression(amdgpu_gfx940::v140, output_vec_len ); + case 397: return makeRegisterExpression(amdgpu_gfx940::v141, output_vec_len ); + case 398: return makeRegisterExpression(amdgpu_gfx940::v142, output_vec_len ); + case 399: return makeRegisterExpression(amdgpu_gfx940::v143, output_vec_len ); + case 400: return makeRegisterExpression(amdgpu_gfx940::v144, output_vec_len ); + case 401: return makeRegisterExpression(amdgpu_gfx940::v145, output_vec_len ); + case 402: return makeRegisterExpression(amdgpu_gfx940::v146, output_vec_len ); + case 403: return makeRegisterExpression(amdgpu_gfx940::v147, output_vec_len ); + case 404: return makeRegisterExpression(amdgpu_gfx940::v148, output_vec_len ); + case 405: return makeRegisterExpression(amdgpu_gfx940::v149, output_vec_len ); + case 406: return makeRegisterExpression(amdgpu_gfx940::v150, output_vec_len ); + case 407: return makeRegisterExpression(amdgpu_gfx940::v151, output_vec_len ); + case 408: return makeRegisterExpression(amdgpu_gfx940::v152, output_vec_len ); + case 409: return makeRegisterExpression(amdgpu_gfx940::v153, output_vec_len ); + case 410: return makeRegisterExpression(amdgpu_gfx940::v154, output_vec_len ); + case 411: return makeRegisterExpression(amdgpu_gfx940::v155, output_vec_len ); + case 412: return makeRegisterExpression(amdgpu_gfx940::v156, output_vec_len ); + case 413: return makeRegisterExpression(amdgpu_gfx940::v157, output_vec_len ); + case 414: return makeRegisterExpression(amdgpu_gfx940::v158, output_vec_len ); + case 415: return makeRegisterExpression(amdgpu_gfx940::v159, output_vec_len ); + case 416: return makeRegisterExpression(amdgpu_gfx940::v160, output_vec_len ); + case 417: return makeRegisterExpression(amdgpu_gfx940::v161, output_vec_len ); + case 418: return makeRegisterExpression(amdgpu_gfx940::v162, output_vec_len ); + case 419: return makeRegisterExpression(amdgpu_gfx940::v163, output_vec_len ); + case 420: return makeRegisterExpression(amdgpu_gfx940::v164, output_vec_len ); + case 421: return makeRegisterExpression(amdgpu_gfx940::v165, output_vec_len ); + case 422: return makeRegisterExpression(amdgpu_gfx940::v166, output_vec_len ); + case 423: return makeRegisterExpression(amdgpu_gfx940::v167, output_vec_len ); + case 424: return makeRegisterExpression(amdgpu_gfx940::v168, output_vec_len ); + case 425: return makeRegisterExpression(amdgpu_gfx940::v169, output_vec_len ); + case 426: return makeRegisterExpression(amdgpu_gfx940::v170, output_vec_len ); + case 427: return makeRegisterExpression(amdgpu_gfx940::v171, output_vec_len ); + case 428: return makeRegisterExpression(amdgpu_gfx940::v172, output_vec_len ); + case 429: return makeRegisterExpression(amdgpu_gfx940::v173, output_vec_len ); + case 430: return makeRegisterExpression(amdgpu_gfx940::v174, output_vec_len ); + case 431: return makeRegisterExpression(amdgpu_gfx940::v175, output_vec_len ); + case 432: return makeRegisterExpression(amdgpu_gfx940::v176, output_vec_len ); + case 433: return makeRegisterExpression(amdgpu_gfx940::v177, output_vec_len ); + case 434: return makeRegisterExpression(amdgpu_gfx940::v178, output_vec_len ); + case 435: return makeRegisterExpression(amdgpu_gfx940::v179, output_vec_len ); + case 436: return makeRegisterExpression(amdgpu_gfx940::v180, output_vec_len ); + case 437: return makeRegisterExpression(amdgpu_gfx940::v181, output_vec_len ); + case 438: return makeRegisterExpression(amdgpu_gfx940::v182, output_vec_len ); + case 439: return makeRegisterExpression(amdgpu_gfx940::v183, output_vec_len ); + case 440: return makeRegisterExpression(amdgpu_gfx940::v184, output_vec_len ); + case 441: return makeRegisterExpression(amdgpu_gfx940::v185, output_vec_len ); + case 442: return makeRegisterExpression(amdgpu_gfx940::v186, output_vec_len ); + case 443: return makeRegisterExpression(amdgpu_gfx940::v187, output_vec_len ); + case 444: return makeRegisterExpression(amdgpu_gfx940::v188, output_vec_len ); + case 445: return makeRegisterExpression(amdgpu_gfx940::v189, output_vec_len ); + case 446: return makeRegisterExpression(amdgpu_gfx940::v190, output_vec_len ); + case 447: return makeRegisterExpression(amdgpu_gfx940::v191, output_vec_len ); + case 448: return makeRegisterExpression(amdgpu_gfx940::v192, output_vec_len ); + case 449: return makeRegisterExpression(amdgpu_gfx940::v193, output_vec_len ); + case 450: return makeRegisterExpression(amdgpu_gfx940::v194, output_vec_len ); + case 451: return makeRegisterExpression(amdgpu_gfx940::v195, output_vec_len ); + case 452: return makeRegisterExpression(amdgpu_gfx940::v196, output_vec_len ); + case 453: return makeRegisterExpression(amdgpu_gfx940::v197, output_vec_len ); + case 454: return makeRegisterExpression(amdgpu_gfx940::v198, output_vec_len ); + case 455: return makeRegisterExpression(amdgpu_gfx940::v199, output_vec_len ); + case 456: return makeRegisterExpression(amdgpu_gfx940::v200, output_vec_len ); + case 457: return makeRegisterExpression(amdgpu_gfx940::v201, output_vec_len ); + case 458: return makeRegisterExpression(amdgpu_gfx940::v202, output_vec_len ); + case 459: return makeRegisterExpression(amdgpu_gfx940::v203, output_vec_len ); + case 460: return makeRegisterExpression(amdgpu_gfx940::v204, output_vec_len ); + case 461: return makeRegisterExpression(amdgpu_gfx940::v205, output_vec_len ); + case 462: return makeRegisterExpression(amdgpu_gfx940::v206, output_vec_len ); + case 463: return makeRegisterExpression(amdgpu_gfx940::v207, output_vec_len ); + case 464: return makeRegisterExpression(amdgpu_gfx940::v208, output_vec_len ); + case 465: return makeRegisterExpression(amdgpu_gfx940::v209, output_vec_len ); + case 466: return makeRegisterExpression(amdgpu_gfx940::v210, output_vec_len ); + case 467: return makeRegisterExpression(amdgpu_gfx940::v211, output_vec_len ); + case 468: return makeRegisterExpression(amdgpu_gfx940::v212, output_vec_len ); + case 469: return makeRegisterExpression(amdgpu_gfx940::v213, output_vec_len ); + case 470: return makeRegisterExpression(amdgpu_gfx940::v214, output_vec_len ); + case 471: return makeRegisterExpression(amdgpu_gfx940::v215, output_vec_len ); + case 472: return makeRegisterExpression(amdgpu_gfx940::v216, output_vec_len ); + case 473: return makeRegisterExpression(amdgpu_gfx940::v217, output_vec_len ); + case 474: return makeRegisterExpression(amdgpu_gfx940::v218, output_vec_len ); + case 475: return makeRegisterExpression(amdgpu_gfx940::v219, output_vec_len ); + case 476: return makeRegisterExpression(amdgpu_gfx940::v220, output_vec_len ); + case 477: return makeRegisterExpression(amdgpu_gfx940::v221, output_vec_len ); + case 478: return makeRegisterExpression(amdgpu_gfx940::v222, output_vec_len ); + case 479: return makeRegisterExpression(amdgpu_gfx940::v223, output_vec_len ); + case 480: return makeRegisterExpression(amdgpu_gfx940::v224, output_vec_len ); + case 481: return makeRegisterExpression(amdgpu_gfx940::v225, output_vec_len ); + case 482: return makeRegisterExpression(amdgpu_gfx940::v226, output_vec_len ); + case 483: return makeRegisterExpression(amdgpu_gfx940::v227, output_vec_len ); + case 484: return makeRegisterExpression(amdgpu_gfx940::v228, output_vec_len ); + case 485: return makeRegisterExpression(amdgpu_gfx940::v229, output_vec_len ); + case 486: return makeRegisterExpression(amdgpu_gfx940::v230, output_vec_len ); + case 487: return makeRegisterExpression(amdgpu_gfx940::v231, output_vec_len ); + case 488: return makeRegisterExpression(amdgpu_gfx940::v232, output_vec_len ); + case 489: return makeRegisterExpression(amdgpu_gfx940::v233, output_vec_len ); + case 490: return makeRegisterExpression(amdgpu_gfx940::v234, output_vec_len ); + case 491: return makeRegisterExpression(amdgpu_gfx940::v235, output_vec_len ); + case 492: return makeRegisterExpression(amdgpu_gfx940::v236, output_vec_len ); + case 493: return makeRegisterExpression(amdgpu_gfx940::v237, output_vec_len ); + case 494: return makeRegisterExpression(amdgpu_gfx940::v238, output_vec_len ); + case 495: return makeRegisterExpression(amdgpu_gfx940::v239, output_vec_len ); + case 496: return makeRegisterExpression(amdgpu_gfx940::v240, output_vec_len ); + case 497: return makeRegisterExpression(amdgpu_gfx940::v241, output_vec_len ); + case 498: return makeRegisterExpression(amdgpu_gfx940::v242, output_vec_len ); + case 499: return makeRegisterExpression(amdgpu_gfx940::v243, output_vec_len ); + case 500: return makeRegisterExpression(amdgpu_gfx940::v244, output_vec_len ); + case 501: return makeRegisterExpression(amdgpu_gfx940::v245, output_vec_len ); + case 502: return makeRegisterExpression(amdgpu_gfx940::v246, output_vec_len ); + case 503: return makeRegisterExpression(amdgpu_gfx940::v247, output_vec_len ); + case 504: return makeRegisterExpression(amdgpu_gfx940::v248, output_vec_len ); + case 505: return makeRegisterExpression(amdgpu_gfx940::v249, output_vec_len ); + case 506: return makeRegisterExpression(amdgpu_gfx940::v250, output_vec_len ); + case 507: return makeRegisterExpression(amdgpu_gfx940::v251, output_vec_len ); + case 508: return makeRegisterExpression(amdgpu_gfx940::v252, output_vec_len ); + case 509: return makeRegisterExpression(amdgpu_gfx940::v253, output_vec_len ); + case 510: return makeRegisterExpression(amdgpu_gfx940::v254, output_vec_len ); + case 511: return makeRegisterExpression(amdgpu_gfx940::v255, output_vec_len ); + case 768: return makeRegisterExpression(amdgpu_gfx940::acc0, output_vec_len ); + case 769: return makeRegisterExpression(amdgpu_gfx940::acc1, output_vec_len ); + case 770: return makeRegisterExpression(amdgpu_gfx940::acc2, output_vec_len ); + case 771: return makeRegisterExpression(amdgpu_gfx940::acc3, output_vec_len ); + case 772: return makeRegisterExpression(amdgpu_gfx940::acc4, output_vec_len ); + case 773: return makeRegisterExpression(amdgpu_gfx940::acc5, output_vec_len ); + case 774: return makeRegisterExpression(amdgpu_gfx940::acc6, output_vec_len ); + case 775: return makeRegisterExpression(amdgpu_gfx940::acc7, output_vec_len ); + case 776: return makeRegisterExpression(amdgpu_gfx940::acc8, output_vec_len ); + case 777: return makeRegisterExpression(amdgpu_gfx940::acc9, output_vec_len ); + case 778: return makeRegisterExpression(amdgpu_gfx940::acc10, output_vec_len ); + case 779: return makeRegisterExpression(amdgpu_gfx940::acc11, output_vec_len ); + case 780: return makeRegisterExpression(amdgpu_gfx940::acc12, output_vec_len ); + case 781: return makeRegisterExpression(amdgpu_gfx940::acc13, output_vec_len ); + case 782: return makeRegisterExpression(amdgpu_gfx940::acc14, output_vec_len ); + case 783: return makeRegisterExpression(amdgpu_gfx940::acc15, output_vec_len ); + case 784: return makeRegisterExpression(amdgpu_gfx940::acc16, output_vec_len ); + case 785: return makeRegisterExpression(amdgpu_gfx940::acc17, output_vec_len ); + case 786: return makeRegisterExpression(amdgpu_gfx940::acc18, output_vec_len ); + case 787: return makeRegisterExpression(amdgpu_gfx940::acc19, output_vec_len ); + case 788: return makeRegisterExpression(amdgpu_gfx940::acc20, output_vec_len ); + case 789: return makeRegisterExpression(amdgpu_gfx940::acc21, output_vec_len ); + case 790: return makeRegisterExpression(amdgpu_gfx940::acc22, output_vec_len ); + case 791: return makeRegisterExpression(amdgpu_gfx940::acc23, output_vec_len ); + case 792: return makeRegisterExpression(amdgpu_gfx940::acc24, output_vec_len ); + case 793: return makeRegisterExpression(amdgpu_gfx940::acc25, output_vec_len ); + case 794: return makeRegisterExpression(amdgpu_gfx940::acc26, output_vec_len ); + case 795: return makeRegisterExpression(amdgpu_gfx940::acc27, output_vec_len ); + case 796: return makeRegisterExpression(amdgpu_gfx940::acc28, output_vec_len ); + case 797: return makeRegisterExpression(amdgpu_gfx940::acc29, output_vec_len ); + case 798: return makeRegisterExpression(amdgpu_gfx940::acc30, output_vec_len ); + case 799: return makeRegisterExpression(amdgpu_gfx940::acc31, output_vec_len ); + case 800: return makeRegisterExpression(amdgpu_gfx940::acc32, output_vec_len ); + case 801: return makeRegisterExpression(amdgpu_gfx940::acc33, output_vec_len ); + case 802: return makeRegisterExpression(amdgpu_gfx940::acc34, output_vec_len ); + case 803: return makeRegisterExpression(amdgpu_gfx940::acc35, output_vec_len ); + case 804: return makeRegisterExpression(amdgpu_gfx940::acc36, output_vec_len ); + case 805: return makeRegisterExpression(amdgpu_gfx940::acc37, output_vec_len ); + case 806: return makeRegisterExpression(amdgpu_gfx940::acc38, output_vec_len ); + case 807: return makeRegisterExpression(amdgpu_gfx940::acc39, output_vec_len ); + case 808: return makeRegisterExpression(amdgpu_gfx940::acc40, output_vec_len ); + case 809: return makeRegisterExpression(amdgpu_gfx940::acc41, output_vec_len ); + case 810: return makeRegisterExpression(amdgpu_gfx940::acc42, output_vec_len ); + case 811: return makeRegisterExpression(amdgpu_gfx940::acc43, output_vec_len ); + case 812: return makeRegisterExpression(amdgpu_gfx940::acc44, output_vec_len ); + case 813: return makeRegisterExpression(amdgpu_gfx940::acc45, output_vec_len ); + case 814: return makeRegisterExpression(amdgpu_gfx940::acc46, output_vec_len ); + case 815: return makeRegisterExpression(amdgpu_gfx940::acc47, output_vec_len ); + case 816: return makeRegisterExpression(amdgpu_gfx940::acc48, output_vec_len ); + case 817: return makeRegisterExpression(amdgpu_gfx940::acc49, output_vec_len ); + case 818: return makeRegisterExpression(amdgpu_gfx940::acc50, output_vec_len ); + case 819: return makeRegisterExpression(amdgpu_gfx940::acc51, output_vec_len ); + case 820: return makeRegisterExpression(amdgpu_gfx940::acc52, output_vec_len ); + case 821: return makeRegisterExpression(amdgpu_gfx940::acc53, output_vec_len ); + case 822: return makeRegisterExpression(amdgpu_gfx940::acc54, output_vec_len ); + case 823: return makeRegisterExpression(amdgpu_gfx940::acc55, output_vec_len ); + case 824: return makeRegisterExpression(amdgpu_gfx940::acc56, output_vec_len ); + case 825: return makeRegisterExpression(amdgpu_gfx940::acc57, output_vec_len ); + case 826: return makeRegisterExpression(amdgpu_gfx940::acc58, output_vec_len ); + case 827: return makeRegisterExpression(amdgpu_gfx940::acc59, output_vec_len ); + case 828: return makeRegisterExpression(amdgpu_gfx940::acc60, output_vec_len ); + case 829: return makeRegisterExpression(amdgpu_gfx940::acc61, output_vec_len ); + case 830: return makeRegisterExpression(amdgpu_gfx940::acc62, output_vec_len ); + case 831: return makeRegisterExpression(amdgpu_gfx940::acc63, output_vec_len ); + case 832: return makeRegisterExpression(amdgpu_gfx940::acc64, output_vec_len ); + case 833: return makeRegisterExpression(amdgpu_gfx940::acc65, output_vec_len ); + case 834: return makeRegisterExpression(amdgpu_gfx940::acc66, output_vec_len ); + case 835: return makeRegisterExpression(amdgpu_gfx940::acc67, output_vec_len ); + case 836: return makeRegisterExpression(amdgpu_gfx940::acc68, output_vec_len ); + case 837: return makeRegisterExpression(amdgpu_gfx940::acc69, output_vec_len ); + case 838: return makeRegisterExpression(amdgpu_gfx940::acc70, output_vec_len ); + case 839: return makeRegisterExpression(amdgpu_gfx940::acc71, output_vec_len ); + case 840: return makeRegisterExpression(amdgpu_gfx940::acc72, output_vec_len ); + case 841: return makeRegisterExpression(amdgpu_gfx940::acc73, output_vec_len ); + case 842: return makeRegisterExpression(amdgpu_gfx940::acc74, output_vec_len ); + case 843: return makeRegisterExpression(amdgpu_gfx940::acc75, output_vec_len ); + case 844: return makeRegisterExpression(amdgpu_gfx940::acc76, output_vec_len ); + case 845: return makeRegisterExpression(amdgpu_gfx940::acc77, output_vec_len ); + case 846: return makeRegisterExpression(amdgpu_gfx940::acc78, output_vec_len ); + case 847: return makeRegisterExpression(amdgpu_gfx940::acc79, output_vec_len ); + case 848: return makeRegisterExpression(amdgpu_gfx940::acc80, output_vec_len ); + case 849: return makeRegisterExpression(amdgpu_gfx940::acc81, output_vec_len ); + case 850: return makeRegisterExpression(amdgpu_gfx940::acc82, output_vec_len ); + case 851: return makeRegisterExpression(amdgpu_gfx940::acc83, output_vec_len ); + case 852: return makeRegisterExpression(amdgpu_gfx940::acc84, output_vec_len ); + case 853: return makeRegisterExpression(amdgpu_gfx940::acc85, output_vec_len ); + case 854: return makeRegisterExpression(amdgpu_gfx940::acc86, output_vec_len ); + case 855: return makeRegisterExpression(amdgpu_gfx940::acc87, output_vec_len ); + case 856: return makeRegisterExpression(amdgpu_gfx940::acc88, output_vec_len ); + case 857: return makeRegisterExpression(amdgpu_gfx940::acc89, output_vec_len ); + case 858: return makeRegisterExpression(amdgpu_gfx940::acc90, output_vec_len ); + case 859: return makeRegisterExpression(amdgpu_gfx940::acc91, output_vec_len ); + case 860: return makeRegisterExpression(amdgpu_gfx940::acc92, output_vec_len ); + case 861: return makeRegisterExpression(amdgpu_gfx940::acc93, output_vec_len ); + case 862: return makeRegisterExpression(amdgpu_gfx940::acc94, output_vec_len ); + case 863: return makeRegisterExpression(amdgpu_gfx940::acc95, output_vec_len ); + case 864: return makeRegisterExpression(amdgpu_gfx940::acc96, output_vec_len ); + case 865: return makeRegisterExpression(amdgpu_gfx940::acc97, output_vec_len ); + case 866: return makeRegisterExpression(amdgpu_gfx940::acc98, output_vec_len ); + case 867: return makeRegisterExpression(amdgpu_gfx940::acc99, output_vec_len ); + case 868: return makeRegisterExpression(amdgpu_gfx940::acc100, output_vec_len ); + case 869: return makeRegisterExpression(amdgpu_gfx940::acc101, output_vec_len ); + case 870: return makeRegisterExpression(amdgpu_gfx940::acc102, output_vec_len ); + case 871: return makeRegisterExpression(amdgpu_gfx940::acc103, output_vec_len ); + case 872: return makeRegisterExpression(amdgpu_gfx940::acc104, output_vec_len ); + case 873: return makeRegisterExpression(amdgpu_gfx940::acc105, output_vec_len ); + case 874: return makeRegisterExpression(amdgpu_gfx940::acc106, output_vec_len ); + case 875: return makeRegisterExpression(amdgpu_gfx940::acc107, output_vec_len ); + case 876: return makeRegisterExpression(amdgpu_gfx940::acc108, output_vec_len ); + case 877: return makeRegisterExpression(amdgpu_gfx940::acc109, output_vec_len ); + case 878: return makeRegisterExpression(amdgpu_gfx940::acc110, output_vec_len ); + case 879: return makeRegisterExpression(amdgpu_gfx940::acc111, output_vec_len ); + case 880: return makeRegisterExpression(amdgpu_gfx940::acc112, output_vec_len ); + case 881: return makeRegisterExpression(amdgpu_gfx940::acc113, output_vec_len ); + case 882: return makeRegisterExpression(amdgpu_gfx940::acc114, output_vec_len ); + case 883: return makeRegisterExpression(amdgpu_gfx940::acc115, output_vec_len ); + case 884: return makeRegisterExpression(amdgpu_gfx940::acc116, output_vec_len ); + case 885: return makeRegisterExpression(amdgpu_gfx940::acc117, output_vec_len ); + case 886: return makeRegisterExpression(amdgpu_gfx940::acc118, output_vec_len ); + case 887: return makeRegisterExpression(amdgpu_gfx940::acc119, output_vec_len ); + case 888: return makeRegisterExpression(amdgpu_gfx940::acc120, output_vec_len ); + case 889: return makeRegisterExpression(amdgpu_gfx940::acc121, output_vec_len ); + case 890: return makeRegisterExpression(amdgpu_gfx940::acc122, output_vec_len ); + case 891: return makeRegisterExpression(amdgpu_gfx940::acc123, output_vec_len ); + case 892: return makeRegisterExpression(amdgpu_gfx940::acc124, output_vec_len ); + case 893: return makeRegisterExpression(amdgpu_gfx940::acc125, output_vec_len ); + case 894: return makeRegisterExpression(amdgpu_gfx940::acc126, output_vec_len ); + case 895: return makeRegisterExpression(amdgpu_gfx940::acc127, output_vec_len ); + case 896: return makeRegisterExpression(amdgpu_gfx940::acc128, output_vec_len ); + case 897: return makeRegisterExpression(amdgpu_gfx940::acc129, output_vec_len ); + case 898: return makeRegisterExpression(amdgpu_gfx940::acc130, output_vec_len ); + case 899: return makeRegisterExpression(amdgpu_gfx940::acc131, output_vec_len ); + case 900: return makeRegisterExpression(amdgpu_gfx940::acc132, output_vec_len ); + case 901: return makeRegisterExpression(amdgpu_gfx940::acc133, output_vec_len ); + case 902: return makeRegisterExpression(amdgpu_gfx940::acc134, output_vec_len ); + case 903: return makeRegisterExpression(amdgpu_gfx940::acc135, output_vec_len ); + case 904: return makeRegisterExpression(amdgpu_gfx940::acc136, output_vec_len ); + case 905: return makeRegisterExpression(amdgpu_gfx940::acc137, output_vec_len ); + case 906: return makeRegisterExpression(amdgpu_gfx940::acc138, output_vec_len ); + case 907: return makeRegisterExpression(amdgpu_gfx940::acc139, output_vec_len ); + case 908: return makeRegisterExpression(amdgpu_gfx940::acc140, output_vec_len ); + case 909: return makeRegisterExpression(amdgpu_gfx940::acc141, output_vec_len ); + case 910: return makeRegisterExpression(amdgpu_gfx940::acc142, output_vec_len ); + case 911: return makeRegisterExpression(amdgpu_gfx940::acc143, output_vec_len ); + case 912: return makeRegisterExpression(amdgpu_gfx940::acc144, output_vec_len ); + case 913: return makeRegisterExpression(amdgpu_gfx940::acc145, output_vec_len ); + case 914: return makeRegisterExpression(amdgpu_gfx940::acc146, output_vec_len ); + case 915: return makeRegisterExpression(amdgpu_gfx940::acc147, output_vec_len ); + case 916: return makeRegisterExpression(amdgpu_gfx940::acc148, output_vec_len ); + case 917: return makeRegisterExpression(amdgpu_gfx940::acc149, output_vec_len ); + case 918: return makeRegisterExpression(amdgpu_gfx940::acc150, output_vec_len ); + case 919: return makeRegisterExpression(amdgpu_gfx940::acc151, output_vec_len ); + case 920: return makeRegisterExpression(amdgpu_gfx940::acc152, output_vec_len ); + case 921: return makeRegisterExpression(amdgpu_gfx940::acc153, output_vec_len ); + case 922: return makeRegisterExpression(amdgpu_gfx940::acc154, output_vec_len ); + case 923: return makeRegisterExpression(amdgpu_gfx940::acc155, output_vec_len ); + case 924: return makeRegisterExpression(amdgpu_gfx940::acc156, output_vec_len ); + case 925: return makeRegisterExpression(amdgpu_gfx940::acc157, output_vec_len ); + case 926: return makeRegisterExpression(amdgpu_gfx940::acc158, output_vec_len ); + case 927: return makeRegisterExpression(amdgpu_gfx940::acc159, output_vec_len ); + case 928: return makeRegisterExpression(amdgpu_gfx940::acc160, output_vec_len ); + case 929: return makeRegisterExpression(amdgpu_gfx940::acc161, output_vec_len ); + case 930: return makeRegisterExpression(amdgpu_gfx940::acc162, output_vec_len ); + case 931: return makeRegisterExpression(amdgpu_gfx940::acc163, output_vec_len ); + case 932: return makeRegisterExpression(amdgpu_gfx940::acc164, output_vec_len ); + case 933: return makeRegisterExpression(amdgpu_gfx940::acc165, output_vec_len ); + case 934: return makeRegisterExpression(amdgpu_gfx940::acc166, output_vec_len ); + case 935: return makeRegisterExpression(amdgpu_gfx940::acc167, output_vec_len ); + case 936: return makeRegisterExpression(amdgpu_gfx940::acc168, output_vec_len ); + case 937: return makeRegisterExpression(amdgpu_gfx940::acc169, output_vec_len ); + case 938: return makeRegisterExpression(amdgpu_gfx940::acc170, output_vec_len ); + case 939: return makeRegisterExpression(amdgpu_gfx940::acc171, output_vec_len ); + case 940: return makeRegisterExpression(amdgpu_gfx940::acc172, output_vec_len ); + case 941: return makeRegisterExpression(amdgpu_gfx940::acc173, output_vec_len ); + case 942: return makeRegisterExpression(amdgpu_gfx940::acc174, output_vec_len ); + case 943: return makeRegisterExpression(amdgpu_gfx940::acc175, output_vec_len ); + case 944: return makeRegisterExpression(amdgpu_gfx940::acc176, output_vec_len ); + case 945: return makeRegisterExpression(amdgpu_gfx940::acc177, output_vec_len ); + case 946: return makeRegisterExpression(amdgpu_gfx940::acc178, output_vec_len ); + case 947: return makeRegisterExpression(amdgpu_gfx940::acc179, output_vec_len ); + case 948: return makeRegisterExpression(amdgpu_gfx940::acc180, output_vec_len ); + case 949: return makeRegisterExpression(amdgpu_gfx940::acc181, output_vec_len ); + case 950: return makeRegisterExpression(amdgpu_gfx940::acc182, output_vec_len ); + case 951: return makeRegisterExpression(amdgpu_gfx940::acc183, output_vec_len ); + case 952: return makeRegisterExpression(amdgpu_gfx940::acc184, output_vec_len ); + case 953: return makeRegisterExpression(amdgpu_gfx940::acc185, output_vec_len ); + case 954: return makeRegisterExpression(amdgpu_gfx940::acc186, output_vec_len ); + case 955: return makeRegisterExpression(amdgpu_gfx940::acc187, output_vec_len ); + case 956: return makeRegisterExpression(amdgpu_gfx940::acc188, output_vec_len ); + case 957: return makeRegisterExpression(amdgpu_gfx940::acc189, output_vec_len ); + case 958: return makeRegisterExpression(amdgpu_gfx940::acc190, output_vec_len ); + case 959: return makeRegisterExpression(amdgpu_gfx940::acc191, output_vec_len ); + case 960: return makeRegisterExpression(amdgpu_gfx940::acc192, output_vec_len ); + case 961: return makeRegisterExpression(amdgpu_gfx940::acc193, output_vec_len ); + case 962: return makeRegisterExpression(amdgpu_gfx940::acc194, output_vec_len ); + case 963: return makeRegisterExpression(amdgpu_gfx940::acc195, output_vec_len ); + case 964: return makeRegisterExpression(amdgpu_gfx940::acc196, output_vec_len ); + case 965: return makeRegisterExpression(amdgpu_gfx940::acc197, output_vec_len ); + case 966: return makeRegisterExpression(amdgpu_gfx940::acc198, output_vec_len ); + case 967: return makeRegisterExpression(amdgpu_gfx940::acc199, output_vec_len ); + case 968: return makeRegisterExpression(amdgpu_gfx940::acc200, output_vec_len ); + case 969: return makeRegisterExpression(amdgpu_gfx940::acc201, output_vec_len ); + case 970: return makeRegisterExpression(amdgpu_gfx940::acc202, output_vec_len ); + case 971: return makeRegisterExpression(amdgpu_gfx940::acc203, output_vec_len ); + case 972: return makeRegisterExpression(amdgpu_gfx940::acc204, output_vec_len ); + case 973: return makeRegisterExpression(amdgpu_gfx940::acc205, output_vec_len ); + case 974: return makeRegisterExpression(amdgpu_gfx940::acc206, output_vec_len ); + case 975: return makeRegisterExpression(amdgpu_gfx940::acc207, output_vec_len ); + case 976: return makeRegisterExpression(amdgpu_gfx940::acc208, output_vec_len ); + case 977: return makeRegisterExpression(amdgpu_gfx940::acc209, output_vec_len ); + case 978: return makeRegisterExpression(amdgpu_gfx940::acc210, output_vec_len ); + case 979: return makeRegisterExpression(amdgpu_gfx940::acc211, output_vec_len ); + case 980: return makeRegisterExpression(amdgpu_gfx940::acc212, output_vec_len ); + case 981: return makeRegisterExpression(amdgpu_gfx940::acc213, output_vec_len ); + case 982: return makeRegisterExpression(amdgpu_gfx940::acc214, output_vec_len ); + case 983: return makeRegisterExpression(amdgpu_gfx940::acc215, output_vec_len ); + case 984: return makeRegisterExpression(amdgpu_gfx940::acc216, output_vec_len ); + case 985: return makeRegisterExpression(amdgpu_gfx940::acc217, output_vec_len ); + case 986: return makeRegisterExpression(amdgpu_gfx940::acc218, output_vec_len ); + case 987: return makeRegisterExpression(amdgpu_gfx940::acc219, output_vec_len ); + case 988: return makeRegisterExpression(amdgpu_gfx940::acc220, output_vec_len ); + case 989: return makeRegisterExpression(amdgpu_gfx940::acc221, output_vec_len ); + case 990: return makeRegisterExpression(amdgpu_gfx940::acc222, output_vec_len ); + case 991: return makeRegisterExpression(amdgpu_gfx940::acc223, output_vec_len ); + case 992: return makeRegisterExpression(amdgpu_gfx940::acc224, output_vec_len ); + case 993: return makeRegisterExpression(amdgpu_gfx940::acc225, output_vec_len ); + case 994: return makeRegisterExpression(amdgpu_gfx940::acc226, output_vec_len ); + case 995: return makeRegisterExpression(amdgpu_gfx940::acc227, output_vec_len ); + case 996: return makeRegisterExpression(amdgpu_gfx940::acc228, output_vec_len ); + case 997: return makeRegisterExpression(amdgpu_gfx940::acc229, output_vec_len ); + case 998: return makeRegisterExpression(amdgpu_gfx940::acc230, output_vec_len ); + case 999: return makeRegisterExpression(amdgpu_gfx940::acc231, output_vec_len ); + case 1000: return makeRegisterExpression(amdgpu_gfx940::acc232, output_vec_len ); + case 1001: return makeRegisterExpression(amdgpu_gfx940::acc233, output_vec_len ); + case 1002: return makeRegisterExpression(amdgpu_gfx940::acc234, output_vec_len ); + case 1003: return makeRegisterExpression(amdgpu_gfx940::acc235, output_vec_len ); + case 1004: return makeRegisterExpression(amdgpu_gfx940::acc236, output_vec_len ); + case 1005: return makeRegisterExpression(amdgpu_gfx940::acc237, output_vec_len ); + case 1006: return makeRegisterExpression(amdgpu_gfx940::acc238, output_vec_len ); + case 1007: return makeRegisterExpression(amdgpu_gfx940::acc239, output_vec_len ); + case 1008: return makeRegisterExpression(amdgpu_gfx940::acc240, output_vec_len ); + case 1009: return makeRegisterExpression(amdgpu_gfx940::acc241, output_vec_len ); + case 1010: return makeRegisterExpression(amdgpu_gfx940::acc242, output_vec_len ); + case 1011: return makeRegisterExpression(amdgpu_gfx940::acc243, output_vec_len ); + case 1012: return makeRegisterExpression(amdgpu_gfx940::acc244, output_vec_len ); + case 1013: return makeRegisterExpression(amdgpu_gfx940::acc245, output_vec_len ); + case 1014: return makeRegisterExpression(amdgpu_gfx940::acc246, output_vec_len ); + case 1015: return makeRegisterExpression(amdgpu_gfx940::acc247, output_vec_len ); + case 1016: return makeRegisterExpression(amdgpu_gfx940::acc248, output_vec_len ); + case 1017: return makeRegisterExpression(amdgpu_gfx940::acc249, output_vec_len ); + case 1018: return makeRegisterExpression(amdgpu_gfx940::acc250, output_vec_len ); + case 1019: return makeRegisterExpression(amdgpu_gfx940::acc251, output_vec_len ); + case 1020: return makeRegisterExpression(amdgpu_gfx940::acc252, output_vec_len ); + case 1021: return makeRegisterExpression(amdgpu_gfx940::acc253, output_vec_len ); + case 1022: return makeRegisterExpression(amdgpu_gfx940::acc254, output_vec_len ); + case 1023: return makeRegisterExpression(amdgpu_gfx940::acc255, output_vec_len ); + case 128: return Immediate::makeImmediate(Result(u32, 0)); + case 129: return Immediate::makeImmediate(Result(u32, 1)); + case 130: return Immediate::makeImmediate(Result(u32, 2)); + case 131: return Immediate::makeImmediate(Result(u32, 3)); + case 132: return Immediate::makeImmediate(Result(u32, 4)); + case 133: return Immediate::makeImmediate(Result(u32, 5)); + case 134: return Immediate::makeImmediate(Result(u32, 6)); + case 135: return Immediate::makeImmediate(Result(u32, 7)); + case 136: return Immediate::makeImmediate(Result(u32, 8)); + case 137: return Immediate::makeImmediate(Result(u32, 9)); + case 138: return Immediate::makeImmediate(Result(u32, 10)); + case 139: return Immediate::makeImmediate(Result(u32, 11)); + case 140: return Immediate::makeImmediate(Result(u32, 12)); + case 141: return Immediate::makeImmediate(Result(u32, 13)); + case 142: return Immediate::makeImmediate(Result(u32, 14)); + case 143: return Immediate::makeImmediate(Result(u32, 15)); + case 144: return Immediate::makeImmediate(Result(u32, 16)); + case 145: return Immediate::makeImmediate(Result(u32, 17)); + case 146: return Immediate::makeImmediate(Result(u32, 18)); + case 147: return Immediate::makeImmediate(Result(u32, 19)); + case 148: return Immediate::makeImmediate(Result(u32, 20)); + case 149: return Immediate::makeImmediate(Result(u32, 21)); + case 150: return Immediate::makeImmediate(Result(u32, 22)); + case 151: return Immediate::makeImmediate(Result(u32, 23)); + case 152: return Immediate::makeImmediate(Result(u32, 24)); + case 153: return Immediate::makeImmediate(Result(u32, 25)); + case 154: return Immediate::makeImmediate(Result(u32, 26)); + case 155: return Immediate::makeImmediate(Result(u32, 27)); + case 156: return Immediate::makeImmediate(Result(u32, 28)); + case 157: return Immediate::makeImmediate(Result(u32, 29)); + case 158: return Immediate::makeImmediate(Result(u32, 30)); + case 159: return Immediate::makeImmediate(Result(u32, 31)); + case 160: return Immediate::makeImmediate(Result(u32, 32)); + case 161: return Immediate::makeImmediate(Result(u32, 33)); + case 162: return Immediate::makeImmediate(Result(u32, 34)); + case 163: return Immediate::makeImmediate(Result(u32, 35)); + case 164: return Immediate::makeImmediate(Result(u32, 36)); + case 165: return Immediate::makeImmediate(Result(u32, 37)); + case 166: return Immediate::makeImmediate(Result(u32, 38)); + case 167: return Immediate::makeImmediate(Result(u32, 39)); + case 168: return Immediate::makeImmediate(Result(u32, 40)); + case 169: return Immediate::makeImmediate(Result(u32, 41)); + case 170: return Immediate::makeImmediate(Result(u32, 42)); + case 171: return Immediate::makeImmediate(Result(u32, 43)); + case 172: return Immediate::makeImmediate(Result(u32, 44)); + case 173: return Immediate::makeImmediate(Result(u32, 45)); + case 174: return Immediate::makeImmediate(Result(u32, 46)); + case 175: return Immediate::makeImmediate(Result(u32, 47)); + case 176: return Immediate::makeImmediate(Result(u32, 48)); + case 177: return Immediate::makeImmediate(Result(u32, 49)); + case 178: return Immediate::makeImmediate(Result(u32, 50)); + case 179: return Immediate::makeImmediate(Result(u32, 51)); + case 180: return Immediate::makeImmediate(Result(u32, 52)); + case 181: return Immediate::makeImmediate(Result(u32, 53)); + case 182: return Immediate::makeImmediate(Result(u32, 54)); + case 183: return Immediate::makeImmediate(Result(u32, 55)); + case 184: return Immediate::makeImmediate(Result(u32, 56)); + case 185: return Immediate::makeImmediate(Result(u32, 57)); + case 186: return Immediate::makeImmediate(Result(u32, 58)); + case 187: return Immediate::makeImmediate(Result(u32, 59)); + case 188: return Immediate::makeImmediate(Result(u32, 60)); + case 189: return Immediate::makeImmediate(Result(u32, 61)); + case 190: return Immediate::makeImmediate(Result(u32, 62)); + case 191: return Immediate::makeImmediate(Result(u32, 63)); + case 192: return Immediate::makeImmediate(Result(u32, 64)); + case 193: return Immediate::makeImmediate(Result(u32, -1)); + case 194: return Immediate::makeImmediate(Result(u32, -2)); + case 195: return Immediate::makeImmediate(Result(u32, -3)); + case 196: return Immediate::makeImmediate(Result(u32, -4)); + case 197: return Immediate::makeImmediate(Result(u32, -5)); + case 198: return Immediate::makeImmediate(Result(u32, -6)); + case 199: return Immediate::makeImmediate(Result(u32, -7)); + case 200: return Immediate::makeImmediate(Result(u32, -8)); + case 201: return Immediate::makeImmediate(Result(u32, -9)); + case 202: return Immediate::makeImmediate(Result(u32, -10)); + case 203: return Immediate::makeImmediate(Result(u32, -11)); + case 204: return Immediate::makeImmediate(Result(u32, -12)); + case 205: return Immediate::makeImmediate(Result(u32, -13)); + case 206: return Immediate::makeImmediate(Result(u32, -14)); + case 207: return Immediate::makeImmediate(Result(u32, -15)); + case 208: return Immediate::makeImmediate(Result(u32, -16)); + case 240: return Immediate::makeImmediate(Result(sp_float, 0.5)); + case 241: return Immediate::makeImmediate(Result(sp_float, -0.5)); + case 242: return Immediate::makeImmediate(Result(sp_float, 1.0)); + case 243: return Immediate::makeImmediate(Result(sp_float, -1.0)); + case 244: return Immediate::makeImmediate(Result(sp_float, 2.0)); + case 245: return Immediate::makeImmediate(Result(sp_float, -2.0)); + case 246: return Immediate::makeImmediate(Result(sp_float, 4.0)); + case 247: return Immediate::makeImmediate(Result(sp_float, -4.0)); + case 248: return Immediate::makeImmediate(Result(sp_float, 0.15915494)); + default: return makeRegisterExpression(amdgpu_gfx940::invalid); + } + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx940::decodeOPR_SREG(uint64_t input, uint32_t output_vec_len) + { + switch (input) { + case 0: return makeRegisterExpression(amdgpu_gfx940::s0, output_vec_len ); + case 1: return makeRegisterExpression(amdgpu_gfx940::s1, output_vec_len ); + case 2: return makeRegisterExpression(amdgpu_gfx940::s2, output_vec_len ); + case 3: return makeRegisterExpression(amdgpu_gfx940::s3, output_vec_len ); + case 4: return makeRegisterExpression(amdgpu_gfx940::s4, output_vec_len ); + case 5: return makeRegisterExpression(amdgpu_gfx940::s5, output_vec_len ); + case 6: return makeRegisterExpression(amdgpu_gfx940::s6, output_vec_len ); + case 7: return makeRegisterExpression(amdgpu_gfx940::s7, output_vec_len ); + case 8: return makeRegisterExpression(amdgpu_gfx940::s8, output_vec_len ); + case 9: return makeRegisterExpression(amdgpu_gfx940::s9, output_vec_len ); + case 10: return makeRegisterExpression(amdgpu_gfx940::s10, output_vec_len ); + case 11: return makeRegisterExpression(amdgpu_gfx940::s11, output_vec_len ); + case 12: return makeRegisterExpression(amdgpu_gfx940::s12, output_vec_len ); + case 13: return makeRegisterExpression(amdgpu_gfx940::s13, output_vec_len ); + case 14: return makeRegisterExpression(amdgpu_gfx940::s14, output_vec_len ); + case 15: return makeRegisterExpression(amdgpu_gfx940::s15, output_vec_len ); + case 16: return makeRegisterExpression(amdgpu_gfx940::s16, output_vec_len ); + case 17: return makeRegisterExpression(amdgpu_gfx940::s17, output_vec_len ); + case 18: return makeRegisterExpression(amdgpu_gfx940::s18, output_vec_len ); + case 19: return makeRegisterExpression(amdgpu_gfx940::s19, output_vec_len ); + case 20: return makeRegisterExpression(amdgpu_gfx940::s20, output_vec_len ); + case 21: return makeRegisterExpression(amdgpu_gfx940::s21, output_vec_len ); + case 22: return makeRegisterExpression(amdgpu_gfx940::s22, output_vec_len ); + case 23: return makeRegisterExpression(amdgpu_gfx940::s23, output_vec_len ); + case 24: return makeRegisterExpression(amdgpu_gfx940::s24, output_vec_len ); + case 25: return makeRegisterExpression(amdgpu_gfx940::s25, output_vec_len ); + case 26: return makeRegisterExpression(amdgpu_gfx940::s26, output_vec_len ); + case 27: return makeRegisterExpression(amdgpu_gfx940::s27, output_vec_len ); + case 28: return makeRegisterExpression(amdgpu_gfx940::s28, output_vec_len ); + case 29: return makeRegisterExpression(amdgpu_gfx940::s29, output_vec_len ); + case 30: return makeRegisterExpression(amdgpu_gfx940::s30, output_vec_len ); + case 31: return makeRegisterExpression(amdgpu_gfx940::s31, output_vec_len ); + case 32: return makeRegisterExpression(amdgpu_gfx940::s32, output_vec_len ); + case 33: return makeRegisterExpression(amdgpu_gfx940::s33, output_vec_len ); + case 34: return makeRegisterExpression(amdgpu_gfx940::s34, output_vec_len ); + case 35: return makeRegisterExpression(amdgpu_gfx940::s35, output_vec_len ); + case 36: return makeRegisterExpression(amdgpu_gfx940::s36, output_vec_len ); + case 37: return makeRegisterExpression(amdgpu_gfx940::s37, output_vec_len ); + case 38: return makeRegisterExpression(amdgpu_gfx940::s38, output_vec_len ); + case 39: return makeRegisterExpression(amdgpu_gfx940::s39, output_vec_len ); + case 40: return makeRegisterExpression(amdgpu_gfx940::s40, output_vec_len ); + case 41: return makeRegisterExpression(amdgpu_gfx940::s41, output_vec_len ); + case 42: return makeRegisterExpression(amdgpu_gfx940::s42, output_vec_len ); + case 43: return makeRegisterExpression(amdgpu_gfx940::s43, output_vec_len ); + case 44: return makeRegisterExpression(amdgpu_gfx940::s44, output_vec_len ); + case 45: return makeRegisterExpression(amdgpu_gfx940::s45, output_vec_len ); + case 46: return makeRegisterExpression(amdgpu_gfx940::s46, output_vec_len ); + case 47: return makeRegisterExpression(amdgpu_gfx940::s47, output_vec_len ); + case 48: return makeRegisterExpression(amdgpu_gfx940::s48, output_vec_len ); + case 49: return makeRegisterExpression(amdgpu_gfx940::s49, output_vec_len ); + case 50: return makeRegisterExpression(amdgpu_gfx940::s50, output_vec_len ); + case 51: return makeRegisterExpression(amdgpu_gfx940::s51, output_vec_len ); + case 52: return makeRegisterExpression(amdgpu_gfx940::s52, output_vec_len ); + case 53: return makeRegisterExpression(amdgpu_gfx940::s53, output_vec_len ); + case 54: return makeRegisterExpression(amdgpu_gfx940::s54, output_vec_len ); + case 55: return makeRegisterExpression(amdgpu_gfx940::s55, output_vec_len ); + case 56: return makeRegisterExpression(amdgpu_gfx940::s56, output_vec_len ); + case 57: return makeRegisterExpression(amdgpu_gfx940::s57, output_vec_len ); + case 58: return makeRegisterExpression(amdgpu_gfx940::s58, output_vec_len ); + case 59: return makeRegisterExpression(amdgpu_gfx940::s59, output_vec_len ); + case 60: return makeRegisterExpression(amdgpu_gfx940::s60, output_vec_len ); + case 61: return makeRegisterExpression(amdgpu_gfx940::s61, output_vec_len ); + case 62: return makeRegisterExpression(amdgpu_gfx940::s62, output_vec_len ); + case 63: return makeRegisterExpression(amdgpu_gfx940::s63, output_vec_len ); + case 64: return makeRegisterExpression(amdgpu_gfx940::s64, output_vec_len ); + case 65: return makeRegisterExpression(amdgpu_gfx940::s65, output_vec_len ); + case 66: return makeRegisterExpression(amdgpu_gfx940::s66, output_vec_len ); + case 67: return makeRegisterExpression(amdgpu_gfx940::s67, output_vec_len ); + case 68: return makeRegisterExpression(amdgpu_gfx940::s68, output_vec_len ); + case 69: return makeRegisterExpression(amdgpu_gfx940::s69, output_vec_len ); + case 70: return makeRegisterExpression(amdgpu_gfx940::s70, output_vec_len ); + case 71: return makeRegisterExpression(amdgpu_gfx940::s71, output_vec_len ); + case 72: return makeRegisterExpression(amdgpu_gfx940::s72, output_vec_len ); + case 73: return makeRegisterExpression(amdgpu_gfx940::s73, output_vec_len ); + case 74: return makeRegisterExpression(amdgpu_gfx940::s74, output_vec_len ); + case 75: return makeRegisterExpression(amdgpu_gfx940::s75, output_vec_len ); + case 76: return makeRegisterExpression(amdgpu_gfx940::s76, output_vec_len ); + case 77: return makeRegisterExpression(amdgpu_gfx940::s77, output_vec_len ); + case 78: return makeRegisterExpression(amdgpu_gfx940::s78, output_vec_len ); + case 79: return makeRegisterExpression(amdgpu_gfx940::s79, output_vec_len ); + case 80: return makeRegisterExpression(amdgpu_gfx940::s80, output_vec_len ); + case 81: return makeRegisterExpression(amdgpu_gfx940::s81, output_vec_len ); + case 82: return makeRegisterExpression(amdgpu_gfx940::s82, output_vec_len ); + case 83: return makeRegisterExpression(amdgpu_gfx940::s83, output_vec_len ); + case 84: return makeRegisterExpression(amdgpu_gfx940::s84, output_vec_len ); + case 85: return makeRegisterExpression(amdgpu_gfx940::s85, output_vec_len ); + case 86: return makeRegisterExpression(amdgpu_gfx940::s86, output_vec_len ); + case 87: return makeRegisterExpression(amdgpu_gfx940::s87, output_vec_len ); + case 88: return makeRegisterExpression(amdgpu_gfx940::s88, output_vec_len ); + case 89: return makeRegisterExpression(amdgpu_gfx940::s89, output_vec_len ); + case 90: return makeRegisterExpression(amdgpu_gfx940::s90, output_vec_len ); + case 91: return makeRegisterExpression(amdgpu_gfx940::s91, output_vec_len ); + case 92: return makeRegisterExpression(amdgpu_gfx940::s92, output_vec_len ); + case 93: return makeRegisterExpression(amdgpu_gfx940::s93, output_vec_len ); + case 94: return makeRegisterExpression(amdgpu_gfx940::s94, output_vec_len ); + case 95: return makeRegisterExpression(amdgpu_gfx940::s95, output_vec_len ); + case 96: return makeRegisterExpression(amdgpu_gfx940::s96, output_vec_len ); + case 97: return makeRegisterExpression(amdgpu_gfx940::s97, output_vec_len ); + case 98: return makeRegisterExpression(amdgpu_gfx940::s98, output_vec_len ); + case 99: return makeRegisterExpression(amdgpu_gfx940::s99, output_vec_len ); + case 100: return makeRegisterExpression(amdgpu_gfx940::s100, output_vec_len ); + case 101: return makeRegisterExpression(amdgpu_gfx940::s101, output_vec_len ); + case 104: return makeRegisterExpression(amdgpu_gfx940::xnack_mask_lo, output_vec_len ); + case 105: return makeRegisterExpression(amdgpu_gfx940::xnack_mask_hi, output_vec_len ); + case 102: return makeRegisterExpression(amdgpu_gfx940::flat_scratch_lo, output_vec_len ); + case 103: return makeRegisterExpression(amdgpu_gfx940::flat_scratch_hi, output_vec_len ); + case 108: return makeRegisterExpression(amdgpu_gfx940::ttmp0, output_vec_len ); + case 109: return makeRegisterExpression(amdgpu_gfx940::ttmp1, output_vec_len ); + case 110: return makeRegisterExpression(amdgpu_gfx940::ttmp2, output_vec_len ); + case 111: return makeRegisterExpression(amdgpu_gfx940::ttmp3, output_vec_len ); + case 112: return makeRegisterExpression(amdgpu_gfx940::ttmp4, output_vec_len ); + case 113: return makeRegisterExpression(amdgpu_gfx940::ttmp5, output_vec_len ); + case 114: return makeRegisterExpression(amdgpu_gfx940::ttmp6, output_vec_len ); + case 115: return makeRegisterExpression(amdgpu_gfx940::ttmp7, output_vec_len ); + case 116: return makeRegisterExpression(amdgpu_gfx940::ttmp8, output_vec_len ); + case 117: return makeRegisterExpression(amdgpu_gfx940::ttmp9, output_vec_len ); + case 118: return makeRegisterExpression(amdgpu_gfx940::ttmp10, output_vec_len ); + case 119: return makeRegisterExpression(amdgpu_gfx940::ttmp11, output_vec_len ); + case 120: return makeRegisterExpression(amdgpu_gfx940::ttmp12, output_vec_len ); + case 121: return makeRegisterExpression(amdgpu_gfx940::ttmp13, output_vec_len ); + case 122: return makeRegisterExpression(amdgpu_gfx940::ttmp14, output_vec_len ); + case 123: return makeRegisterExpression(amdgpu_gfx940::ttmp15, output_vec_len ); + case 106: return makeRegisterExpression(amdgpu_gfx940::vcc_lo, output_vec_len ); + case 107: return makeRegisterExpression(amdgpu_gfx940::vcc_hi, output_vec_len ); + default: return makeRegisterExpression(amdgpu_gfx940::invalid); + } + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx940::decodeOPR_SREG_NOVCC(uint64_t input, uint32_t output_vec_len) + { + switch (input) { + case 0: return makeRegisterExpression(amdgpu_gfx940::s0, output_vec_len ); + case 1: return makeRegisterExpression(amdgpu_gfx940::s1, output_vec_len ); + case 2: return makeRegisterExpression(amdgpu_gfx940::s2, output_vec_len ); + case 3: return makeRegisterExpression(amdgpu_gfx940::s3, output_vec_len ); + case 4: return makeRegisterExpression(amdgpu_gfx940::s4, output_vec_len ); + case 5: return makeRegisterExpression(amdgpu_gfx940::s5, output_vec_len ); + case 6: return makeRegisterExpression(amdgpu_gfx940::s6, output_vec_len ); + case 7: return makeRegisterExpression(amdgpu_gfx940::s7, output_vec_len ); + case 8: return makeRegisterExpression(amdgpu_gfx940::s8, output_vec_len ); + case 9: return makeRegisterExpression(amdgpu_gfx940::s9, output_vec_len ); + case 10: return makeRegisterExpression(amdgpu_gfx940::s10, output_vec_len ); + case 11: return makeRegisterExpression(amdgpu_gfx940::s11, output_vec_len ); + case 12: return makeRegisterExpression(amdgpu_gfx940::s12, output_vec_len ); + case 13: return makeRegisterExpression(amdgpu_gfx940::s13, output_vec_len ); + case 14: return makeRegisterExpression(amdgpu_gfx940::s14, output_vec_len ); + case 15: return makeRegisterExpression(amdgpu_gfx940::s15, output_vec_len ); + case 16: return makeRegisterExpression(amdgpu_gfx940::s16, output_vec_len ); + case 17: return makeRegisterExpression(amdgpu_gfx940::s17, output_vec_len ); + case 18: return makeRegisterExpression(amdgpu_gfx940::s18, output_vec_len ); + case 19: return makeRegisterExpression(amdgpu_gfx940::s19, output_vec_len ); + case 20: return makeRegisterExpression(amdgpu_gfx940::s20, output_vec_len ); + case 21: return makeRegisterExpression(amdgpu_gfx940::s21, output_vec_len ); + case 22: return makeRegisterExpression(amdgpu_gfx940::s22, output_vec_len ); + case 23: return makeRegisterExpression(amdgpu_gfx940::s23, output_vec_len ); + case 24: return makeRegisterExpression(amdgpu_gfx940::s24, output_vec_len ); + case 25: return makeRegisterExpression(amdgpu_gfx940::s25, output_vec_len ); + case 26: return makeRegisterExpression(amdgpu_gfx940::s26, output_vec_len ); + case 27: return makeRegisterExpression(amdgpu_gfx940::s27, output_vec_len ); + case 28: return makeRegisterExpression(amdgpu_gfx940::s28, output_vec_len ); + case 29: return makeRegisterExpression(amdgpu_gfx940::s29, output_vec_len ); + case 30: return makeRegisterExpression(amdgpu_gfx940::s30, output_vec_len ); + case 31: return makeRegisterExpression(amdgpu_gfx940::s31, output_vec_len ); + case 32: return makeRegisterExpression(amdgpu_gfx940::s32, output_vec_len ); + case 33: return makeRegisterExpression(amdgpu_gfx940::s33, output_vec_len ); + case 34: return makeRegisterExpression(amdgpu_gfx940::s34, output_vec_len ); + case 35: return makeRegisterExpression(amdgpu_gfx940::s35, output_vec_len ); + case 36: return makeRegisterExpression(amdgpu_gfx940::s36, output_vec_len ); + case 37: return makeRegisterExpression(amdgpu_gfx940::s37, output_vec_len ); + case 38: return makeRegisterExpression(amdgpu_gfx940::s38, output_vec_len ); + case 39: return makeRegisterExpression(amdgpu_gfx940::s39, output_vec_len ); + case 40: return makeRegisterExpression(amdgpu_gfx940::s40, output_vec_len ); + case 41: return makeRegisterExpression(amdgpu_gfx940::s41, output_vec_len ); + case 42: return makeRegisterExpression(amdgpu_gfx940::s42, output_vec_len ); + case 43: return makeRegisterExpression(amdgpu_gfx940::s43, output_vec_len ); + case 44: return makeRegisterExpression(amdgpu_gfx940::s44, output_vec_len ); + case 45: return makeRegisterExpression(amdgpu_gfx940::s45, output_vec_len ); + case 46: return makeRegisterExpression(amdgpu_gfx940::s46, output_vec_len ); + case 47: return makeRegisterExpression(amdgpu_gfx940::s47, output_vec_len ); + case 48: return makeRegisterExpression(amdgpu_gfx940::s48, output_vec_len ); + case 49: return makeRegisterExpression(amdgpu_gfx940::s49, output_vec_len ); + case 50: return makeRegisterExpression(amdgpu_gfx940::s50, output_vec_len ); + case 51: return makeRegisterExpression(amdgpu_gfx940::s51, output_vec_len ); + case 52: return makeRegisterExpression(amdgpu_gfx940::s52, output_vec_len ); + case 53: return makeRegisterExpression(amdgpu_gfx940::s53, output_vec_len ); + case 54: return makeRegisterExpression(amdgpu_gfx940::s54, output_vec_len ); + case 55: return makeRegisterExpression(amdgpu_gfx940::s55, output_vec_len ); + case 56: return makeRegisterExpression(amdgpu_gfx940::s56, output_vec_len ); + case 57: return makeRegisterExpression(amdgpu_gfx940::s57, output_vec_len ); + case 58: return makeRegisterExpression(amdgpu_gfx940::s58, output_vec_len ); + case 59: return makeRegisterExpression(amdgpu_gfx940::s59, output_vec_len ); + case 60: return makeRegisterExpression(amdgpu_gfx940::s60, output_vec_len ); + case 61: return makeRegisterExpression(amdgpu_gfx940::s61, output_vec_len ); + case 62: return makeRegisterExpression(amdgpu_gfx940::s62, output_vec_len ); + case 63: return makeRegisterExpression(amdgpu_gfx940::s63, output_vec_len ); + case 64: return makeRegisterExpression(amdgpu_gfx940::s64, output_vec_len ); + case 65: return makeRegisterExpression(amdgpu_gfx940::s65, output_vec_len ); + case 66: return makeRegisterExpression(amdgpu_gfx940::s66, output_vec_len ); + case 67: return makeRegisterExpression(amdgpu_gfx940::s67, output_vec_len ); + case 68: return makeRegisterExpression(amdgpu_gfx940::s68, output_vec_len ); + case 69: return makeRegisterExpression(amdgpu_gfx940::s69, output_vec_len ); + case 70: return makeRegisterExpression(amdgpu_gfx940::s70, output_vec_len ); + case 71: return makeRegisterExpression(amdgpu_gfx940::s71, output_vec_len ); + case 72: return makeRegisterExpression(amdgpu_gfx940::s72, output_vec_len ); + case 73: return makeRegisterExpression(amdgpu_gfx940::s73, output_vec_len ); + case 74: return makeRegisterExpression(amdgpu_gfx940::s74, output_vec_len ); + case 75: return makeRegisterExpression(amdgpu_gfx940::s75, output_vec_len ); + case 76: return makeRegisterExpression(amdgpu_gfx940::s76, output_vec_len ); + case 77: return makeRegisterExpression(amdgpu_gfx940::s77, output_vec_len ); + case 78: return makeRegisterExpression(amdgpu_gfx940::s78, output_vec_len ); + case 79: return makeRegisterExpression(amdgpu_gfx940::s79, output_vec_len ); + case 80: return makeRegisterExpression(amdgpu_gfx940::s80, output_vec_len ); + case 81: return makeRegisterExpression(amdgpu_gfx940::s81, output_vec_len ); + case 82: return makeRegisterExpression(amdgpu_gfx940::s82, output_vec_len ); + case 83: return makeRegisterExpression(amdgpu_gfx940::s83, output_vec_len ); + case 84: return makeRegisterExpression(amdgpu_gfx940::s84, output_vec_len ); + case 85: return makeRegisterExpression(amdgpu_gfx940::s85, output_vec_len ); + case 86: return makeRegisterExpression(amdgpu_gfx940::s86, output_vec_len ); + case 87: return makeRegisterExpression(amdgpu_gfx940::s87, output_vec_len ); + case 88: return makeRegisterExpression(amdgpu_gfx940::s88, output_vec_len ); + case 89: return makeRegisterExpression(amdgpu_gfx940::s89, output_vec_len ); + case 90: return makeRegisterExpression(amdgpu_gfx940::s90, output_vec_len ); + case 91: return makeRegisterExpression(amdgpu_gfx940::s91, output_vec_len ); + case 92: return makeRegisterExpression(amdgpu_gfx940::s92, output_vec_len ); + case 93: return makeRegisterExpression(amdgpu_gfx940::s93, output_vec_len ); + case 94: return makeRegisterExpression(amdgpu_gfx940::s94, output_vec_len ); + case 95: return makeRegisterExpression(amdgpu_gfx940::s95, output_vec_len ); + case 96: return makeRegisterExpression(amdgpu_gfx940::s96, output_vec_len ); + case 97: return makeRegisterExpression(amdgpu_gfx940::s97, output_vec_len ); + case 98: return makeRegisterExpression(amdgpu_gfx940::s98, output_vec_len ); + case 99: return makeRegisterExpression(amdgpu_gfx940::s99, output_vec_len ); + case 100: return makeRegisterExpression(amdgpu_gfx940::s100, output_vec_len ); + case 101: return makeRegisterExpression(amdgpu_gfx940::s101, output_vec_len ); + case 104: return makeRegisterExpression(amdgpu_gfx940::xnack_mask_lo, output_vec_len ); + case 105: return makeRegisterExpression(amdgpu_gfx940::xnack_mask_hi, output_vec_len ); + case 102: return makeRegisterExpression(amdgpu_gfx940::flat_scratch_lo, output_vec_len ); + case 103: return makeRegisterExpression(amdgpu_gfx940::flat_scratch_hi, output_vec_len ); + case 108: return makeRegisterExpression(amdgpu_gfx940::ttmp0, output_vec_len ); + case 109: return makeRegisterExpression(amdgpu_gfx940::ttmp1, output_vec_len ); + case 110: return makeRegisterExpression(amdgpu_gfx940::ttmp2, output_vec_len ); + case 111: return makeRegisterExpression(amdgpu_gfx940::ttmp3, output_vec_len ); + case 112: return makeRegisterExpression(amdgpu_gfx940::ttmp4, output_vec_len ); + case 113: return makeRegisterExpression(amdgpu_gfx940::ttmp5, output_vec_len ); + case 114: return makeRegisterExpression(amdgpu_gfx940::ttmp6, output_vec_len ); + case 115: return makeRegisterExpression(amdgpu_gfx940::ttmp7, output_vec_len ); + case 116: return makeRegisterExpression(amdgpu_gfx940::ttmp8, output_vec_len ); + case 117: return makeRegisterExpression(amdgpu_gfx940::ttmp9, output_vec_len ); + case 118: return makeRegisterExpression(amdgpu_gfx940::ttmp10, output_vec_len ); + case 119: return makeRegisterExpression(amdgpu_gfx940::ttmp11, output_vec_len ); + case 120: return makeRegisterExpression(amdgpu_gfx940::ttmp12, output_vec_len ); + case 121: return makeRegisterExpression(amdgpu_gfx940::ttmp13, output_vec_len ); + case 122: return makeRegisterExpression(amdgpu_gfx940::ttmp14, output_vec_len ); + case 123: return makeRegisterExpression(amdgpu_gfx940::ttmp15, output_vec_len ); + default: return makeRegisterExpression(amdgpu_gfx940::invalid); + } + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx940::decodeOPR_SSRC(uint64_t input, uint32_t output_vec_len) + { + switch (input) { + case 0: return makeRegisterExpression(amdgpu_gfx940::s0, output_vec_len ); + case 1: return makeRegisterExpression(amdgpu_gfx940::s1, output_vec_len ); + case 2: return makeRegisterExpression(amdgpu_gfx940::s2, output_vec_len ); + case 3: return makeRegisterExpression(amdgpu_gfx940::s3, output_vec_len ); + case 4: return makeRegisterExpression(amdgpu_gfx940::s4, output_vec_len ); + case 5: return makeRegisterExpression(amdgpu_gfx940::s5, output_vec_len ); + case 6: return makeRegisterExpression(amdgpu_gfx940::s6, output_vec_len ); + case 7: return makeRegisterExpression(amdgpu_gfx940::s7, output_vec_len ); + case 8: return makeRegisterExpression(amdgpu_gfx940::s8, output_vec_len ); + case 9: return makeRegisterExpression(amdgpu_gfx940::s9, output_vec_len ); + case 10: return makeRegisterExpression(amdgpu_gfx940::s10, output_vec_len ); + case 11: return makeRegisterExpression(amdgpu_gfx940::s11, output_vec_len ); + case 12: return makeRegisterExpression(amdgpu_gfx940::s12, output_vec_len ); + case 13: return makeRegisterExpression(amdgpu_gfx940::s13, output_vec_len ); + case 14: return makeRegisterExpression(amdgpu_gfx940::s14, output_vec_len ); + case 15: return makeRegisterExpression(amdgpu_gfx940::s15, output_vec_len ); + case 16: return makeRegisterExpression(amdgpu_gfx940::s16, output_vec_len ); + case 17: return makeRegisterExpression(amdgpu_gfx940::s17, output_vec_len ); + case 18: return makeRegisterExpression(amdgpu_gfx940::s18, output_vec_len ); + case 19: return makeRegisterExpression(amdgpu_gfx940::s19, output_vec_len ); + case 20: return makeRegisterExpression(amdgpu_gfx940::s20, output_vec_len ); + case 21: return makeRegisterExpression(amdgpu_gfx940::s21, output_vec_len ); + case 22: return makeRegisterExpression(amdgpu_gfx940::s22, output_vec_len ); + case 23: return makeRegisterExpression(amdgpu_gfx940::s23, output_vec_len ); + case 24: return makeRegisterExpression(amdgpu_gfx940::s24, output_vec_len ); + case 25: return makeRegisterExpression(amdgpu_gfx940::s25, output_vec_len ); + case 26: return makeRegisterExpression(amdgpu_gfx940::s26, output_vec_len ); + case 27: return makeRegisterExpression(amdgpu_gfx940::s27, output_vec_len ); + case 28: return makeRegisterExpression(amdgpu_gfx940::s28, output_vec_len ); + case 29: return makeRegisterExpression(amdgpu_gfx940::s29, output_vec_len ); + case 30: return makeRegisterExpression(amdgpu_gfx940::s30, output_vec_len ); + case 31: return makeRegisterExpression(amdgpu_gfx940::s31, output_vec_len ); + case 32: return makeRegisterExpression(amdgpu_gfx940::s32, output_vec_len ); + case 33: return makeRegisterExpression(amdgpu_gfx940::s33, output_vec_len ); + case 34: return makeRegisterExpression(amdgpu_gfx940::s34, output_vec_len ); + case 35: return makeRegisterExpression(amdgpu_gfx940::s35, output_vec_len ); + case 36: return makeRegisterExpression(amdgpu_gfx940::s36, output_vec_len ); + case 37: return makeRegisterExpression(amdgpu_gfx940::s37, output_vec_len ); + case 38: return makeRegisterExpression(amdgpu_gfx940::s38, output_vec_len ); + case 39: return makeRegisterExpression(amdgpu_gfx940::s39, output_vec_len ); + case 40: return makeRegisterExpression(amdgpu_gfx940::s40, output_vec_len ); + case 41: return makeRegisterExpression(amdgpu_gfx940::s41, output_vec_len ); + case 42: return makeRegisterExpression(amdgpu_gfx940::s42, output_vec_len ); + case 43: return makeRegisterExpression(amdgpu_gfx940::s43, output_vec_len ); + case 44: return makeRegisterExpression(amdgpu_gfx940::s44, output_vec_len ); + case 45: return makeRegisterExpression(amdgpu_gfx940::s45, output_vec_len ); + case 46: return makeRegisterExpression(amdgpu_gfx940::s46, output_vec_len ); + case 47: return makeRegisterExpression(amdgpu_gfx940::s47, output_vec_len ); + case 48: return makeRegisterExpression(amdgpu_gfx940::s48, output_vec_len ); + case 49: return makeRegisterExpression(amdgpu_gfx940::s49, output_vec_len ); + case 50: return makeRegisterExpression(amdgpu_gfx940::s50, output_vec_len ); + case 51: return makeRegisterExpression(amdgpu_gfx940::s51, output_vec_len ); + case 52: return makeRegisterExpression(amdgpu_gfx940::s52, output_vec_len ); + case 53: return makeRegisterExpression(amdgpu_gfx940::s53, output_vec_len ); + case 54: return makeRegisterExpression(amdgpu_gfx940::s54, output_vec_len ); + case 55: return makeRegisterExpression(amdgpu_gfx940::s55, output_vec_len ); + case 56: return makeRegisterExpression(amdgpu_gfx940::s56, output_vec_len ); + case 57: return makeRegisterExpression(amdgpu_gfx940::s57, output_vec_len ); + case 58: return makeRegisterExpression(amdgpu_gfx940::s58, output_vec_len ); + case 59: return makeRegisterExpression(amdgpu_gfx940::s59, output_vec_len ); + case 60: return makeRegisterExpression(amdgpu_gfx940::s60, output_vec_len ); + case 61: return makeRegisterExpression(amdgpu_gfx940::s61, output_vec_len ); + case 62: return makeRegisterExpression(amdgpu_gfx940::s62, output_vec_len ); + case 63: return makeRegisterExpression(amdgpu_gfx940::s63, output_vec_len ); + case 64: return makeRegisterExpression(amdgpu_gfx940::s64, output_vec_len ); + case 65: return makeRegisterExpression(amdgpu_gfx940::s65, output_vec_len ); + case 66: return makeRegisterExpression(amdgpu_gfx940::s66, output_vec_len ); + case 67: return makeRegisterExpression(amdgpu_gfx940::s67, output_vec_len ); + case 68: return makeRegisterExpression(amdgpu_gfx940::s68, output_vec_len ); + case 69: return makeRegisterExpression(amdgpu_gfx940::s69, output_vec_len ); + case 70: return makeRegisterExpression(amdgpu_gfx940::s70, output_vec_len ); + case 71: return makeRegisterExpression(amdgpu_gfx940::s71, output_vec_len ); + case 72: return makeRegisterExpression(amdgpu_gfx940::s72, output_vec_len ); + case 73: return makeRegisterExpression(amdgpu_gfx940::s73, output_vec_len ); + case 74: return makeRegisterExpression(amdgpu_gfx940::s74, output_vec_len ); + case 75: return makeRegisterExpression(amdgpu_gfx940::s75, output_vec_len ); + case 76: return makeRegisterExpression(amdgpu_gfx940::s76, output_vec_len ); + case 77: return makeRegisterExpression(amdgpu_gfx940::s77, output_vec_len ); + case 78: return makeRegisterExpression(amdgpu_gfx940::s78, output_vec_len ); + case 79: return makeRegisterExpression(amdgpu_gfx940::s79, output_vec_len ); + case 80: return makeRegisterExpression(amdgpu_gfx940::s80, output_vec_len ); + case 81: return makeRegisterExpression(amdgpu_gfx940::s81, output_vec_len ); + case 82: return makeRegisterExpression(amdgpu_gfx940::s82, output_vec_len ); + case 83: return makeRegisterExpression(amdgpu_gfx940::s83, output_vec_len ); + case 84: return makeRegisterExpression(amdgpu_gfx940::s84, output_vec_len ); + case 85: return makeRegisterExpression(amdgpu_gfx940::s85, output_vec_len ); + case 86: return makeRegisterExpression(amdgpu_gfx940::s86, output_vec_len ); + case 87: return makeRegisterExpression(amdgpu_gfx940::s87, output_vec_len ); + case 88: return makeRegisterExpression(amdgpu_gfx940::s88, output_vec_len ); + case 89: return makeRegisterExpression(amdgpu_gfx940::s89, output_vec_len ); + case 90: return makeRegisterExpression(amdgpu_gfx940::s90, output_vec_len ); + case 91: return makeRegisterExpression(amdgpu_gfx940::s91, output_vec_len ); + case 92: return makeRegisterExpression(amdgpu_gfx940::s92, output_vec_len ); + case 93: return makeRegisterExpression(amdgpu_gfx940::s93, output_vec_len ); + case 94: return makeRegisterExpression(amdgpu_gfx940::s94, output_vec_len ); + case 95: return makeRegisterExpression(amdgpu_gfx940::s95, output_vec_len ); + case 96: return makeRegisterExpression(amdgpu_gfx940::s96, output_vec_len ); + case 97: return makeRegisterExpression(amdgpu_gfx940::s97, output_vec_len ); + case 98: return makeRegisterExpression(amdgpu_gfx940::s98, output_vec_len ); + case 99: return makeRegisterExpression(amdgpu_gfx940::s99, output_vec_len ); + case 100: return makeRegisterExpression(amdgpu_gfx940::s100, output_vec_len ); + case 101: return makeRegisterExpression(amdgpu_gfx940::s101, output_vec_len ); + case 104: return makeRegisterExpression(amdgpu_gfx940::xnack_mask_lo, output_vec_len ); + case 105: return makeRegisterExpression(amdgpu_gfx940::xnack_mask_hi, output_vec_len ); + case 102: return makeRegisterExpression(amdgpu_gfx940::flat_scratch_lo, output_vec_len ); + case 103: return makeRegisterExpression(amdgpu_gfx940::flat_scratch_hi, output_vec_len ); + case 108: return makeRegisterExpression(amdgpu_gfx940::ttmp0, output_vec_len ); + case 109: return makeRegisterExpression(amdgpu_gfx940::ttmp1, output_vec_len ); + case 110: return makeRegisterExpression(amdgpu_gfx940::ttmp2, output_vec_len ); + case 111: return makeRegisterExpression(amdgpu_gfx940::ttmp3, output_vec_len ); + case 112: return makeRegisterExpression(amdgpu_gfx940::ttmp4, output_vec_len ); + case 113: return makeRegisterExpression(amdgpu_gfx940::ttmp5, output_vec_len ); + case 114: return makeRegisterExpression(amdgpu_gfx940::ttmp6, output_vec_len ); + case 115: return makeRegisterExpression(amdgpu_gfx940::ttmp7, output_vec_len ); + case 116: return makeRegisterExpression(amdgpu_gfx940::ttmp8, output_vec_len ); + case 117: return makeRegisterExpression(amdgpu_gfx940::ttmp9, output_vec_len ); + case 118: return makeRegisterExpression(amdgpu_gfx940::ttmp10, output_vec_len ); + case 119: return makeRegisterExpression(amdgpu_gfx940::ttmp11, output_vec_len ); + case 120: return makeRegisterExpression(amdgpu_gfx940::ttmp12, output_vec_len ); + case 121: return makeRegisterExpression(amdgpu_gfx940::ttmp13, output_vec_len ); + case 122: return makeRegisterExpression(amdgpu_gfx940::ttmp14, output_vec_len ); + case 123: return makeRegisterExpression(amdgpu_gfx940::ttmp15, output_vec_len ); + case 106: return makeRegisterExpression(amdgpu_gfx940::vcc_lo, output_vec_len ); + case 107: return makeRegisterExpression(amdgpu_gfx940::vcc_hi, output_vec_len ); + case 124: return makeRegisterExpression(amdgpu_gfx940::m0, output_vec_len ); + case 126: return makeRegisterExpression(amdgpu_gfx940::exec_lo, output_vec_len ); + case 127: return makeRegisterExpression(amdgpu_gfx940::exec_hi, output_vec_len ); + case 128: return Immediate::makeImmediate(Result(u32, 0)); + case 129: return Immediate::makeImmediate(Result(u32, 1)); + case 130: return Immediate::makeImmediate(Result(u32, 2)); + case 131: return Immediate::makeImmediate(Result(u32, 3)); + case 132: return Immediate::makeImmediate(Result(u32, 4)); + case 133: return Immediate::makeImmediate(Result(u32, 5)); + case 134: return Immediate::makeImmediate(Result(u32, 6)); + case 135: return Immediate::makeImmediate(Result(u32, 7)); + case 136: return Immediate::makeImmediate(Result(u32, 8)); + case 137: return Immediate::makeImmediate(Result(u32, 9)); + case 138: return Immediate::makeImmediate(Result(u32, 10)); + case 139: return Immediate::makeImmediate(Result(u32, 11)); + case 140: return Immediate::makeImmediate(Result(u32, 12)); + case 141: return Immediate::makeImmediate(Result(u32, 13)); + case 142: return Immediate::makeImmediate(Result(u32, 14)); + case 143: return Immediate::makeImmediate(Result(u32, 15)); + case 144: return Immediate::makeImmediate(Result(u32, 16)); + case 145: return Immediate::makeImmediate(Result(u32, 17)); + case 146: return Immediate::makeImmediate(Result(u32, 18)); + case 147: return Immediate::makeImmediate(Result(u32, 19)); + case 148: return Immediate::makeImmediate(Result(u32, 20)); + case 149: return Immediate::makeImmediate(Result(u32, 21)); + case 150: return Immediate::makeImmediate(Result(u32, 22)); + case 151: return Immediate::makeImmediate(Result(u32, 23)); + case 152: return Immediate::makeImmediate(Result(u32, 24)); + case 153: return Immediate::makeImmediate(Result(u32, 25)); + case 154: return Immediate::makeImmediate(Result(u32, 26)); + case 155: return Immediate::makeImmediate(Result(u32, 27)); + case 156: return Immediate::makeImmediate(Result(u32, 28)); + case 157: return Immediate::makeImmediate(Result(u32, 29)); + case 158: return Immediate::makeImmediate(Result(u32, 30)); + case 159: return Immediate::makeImmediate(Result(u32, 31)); + case 160: return Immediate::makeImmediate(Result(u32, 32)); + case 161: return Immediate::makeImmediate(Result(u32, 33)); + case 162: return Immediate::makeImmediate(Result(u32, 34)); + case 163: return Immediate::makeImmediate(Result(u32, 35)); + case 164: return Immediate::makeImmediate(Result(u32, 36)); + case 165: return Immediate::makeImmediate(Result(u32, 37)); + case 166: return Immediate::makeImmediate(Result(u32, 38)); + case 167: return Immediate::makeImmediate(Result(u32, 39)); + case 168: return Immediate::makeImmediate(Result(u32, 40)); + case 169: return Immediate::makeImmediate(Result(u32, 41)); + case 170: return Immediate::makeImmediate(Result(u32, 42)); + case 171: return Immediate::makeImmediate(Result(u32, 43)); + case 172: return Immediate::makeImmediate(Result(u32, 44)); + case 173: return Immediate::makeImmediate(Result(u32, 45)); + case 174: return Immediate::makeImmediate(Result(u32, 46)); + case 175: return Immediate::makeImmediate(Result(u32, 47)); + case 176: return Immediate::makeImmediate(Result(u32, 48)); + case 177: return Immediate::makeImmediate(Result(u32, 49)); + case 178: return Immediate::makeImmediate(Result(u32, 50)); + case 179: return Immediate::makeImmediate(Result(u32, 51)); + case 180: return Immediate::makeImmediate(Result(u32, 52)); + case 181: return Immediate::makeImmediate(Result(u32, 53)); + case 182: return Immediate::makeImmediate(Result(u32, 54)); + case 183: return Immediate::makeImmediate(Result(u32, 55)); + case 184: return Immediate::makeImmediate(Result(u32, 56)); + case 185: return Immediate::makeImmediate(Result(u32, 57)); + case 186: return Immediate::makeImmediate(Result(u32, 58)); + case 187: return Immediate::makeImmediate(Result(u32, 59)); + case 188: return Immediate::makeImmediate(Result(u32, 60)); + case 189: return Immediate::makeImmediate(Result(u32, 61)); + case 190: return Immediate::makeImmediate(Result(u32, 62)); + case 191: return Immediate::makeImmediate(Result(u32, 63)); + case 192: return Immediate::makeImmediate(Result(u32, 64)); + case 193: return Immediate::makeImmediate(Result(u32, -1)); + case 194: return Immediate::makeImmediate(Result(u32, -2)); + case 195: return Immediate::makeImmediate(Result(u32, -3)); + case 196: return Immediate::makeImmediate(Result(u32, -4)); + case 197: return Immediate::makeImmediate(Result(u32, -5)); + case 198: return Immediate::makeImmediate(Result(u32, -6)); + case 199: return Immediate::makeImmediate(Result(u32, -7)); + case 200: return Immediate::makeImmediate(Result(u32, -8)); + case 201: return Immediate::makeImmediate(Result(u32, -9)); + case 202: return Immediate::makeImmediate(Result(u32, -10)); + case 203: return Immediate::makeImmediate(Result(u32, -11)); + case 204: return Immediate::makeImmediate(Result(u32, -12)); + case 205: return Immediate::makeImmediate(Result(u32, -13)); + case 206: return Immediate::makeImmediate(Result(u32, -14)); + case 207: return Immediate::makeImmediate(Result(u32, -15)); + case 208: return Immediate::makeImmediate(Result(u32, -16)); + case 240: return Immediate::makeImmediate(Result(sp_float, 0.5)); + case 241: return Immediate::makeImmediate(Result(sp_float, -0.5)); + case 242: return Immediate::makeImmediate(Result(sp_float, 1.0)); + case 243: return Immediate::makeImmediate(Result(sp_float, -1.0)); + case 244: return Immediate::makeImmediate(Result(sp_float, 2.0)); + case 245: return Immediate::makeImmediate(Result(sp_float, -2.0)); + case 246: return Immediate::makeImmediate(Result(sp_float, 4.0)); + case 247: return Immediate::makeImmediate(Result(sp_float, -4.0)); + case 248: return Immediate::makeImmediate(Result(sp_float, 0.15915494)); + case 251: return makeRegisterExpression(amdgpu_gfx940::src_vccz, output_vec_len ); + case 252: return makeRegisterExpression(amdgpu_gfx940::src_execz, output_vec_len ); + case 253: return makeRegisterExpression(amdgpu_gfx940::src_scc, output_vec_len ); + case 235: return makeRegisterExpression(amdgpu_gfx940::src_shared_base, output_vec_len ); + case 236: return makeRegisterExpression(amdgpu_gfx940::src_shared_limit, output_vec_len ); + case 237: return makeRegisterExpression(amdgpu_gfx940::src_private_base, output_vec_len ); + case 238: return makeRegisterExpression(amdgpu_gfx940::src_private_limit, output_vec_len ); + case 239: return makeRegisterExpression(amdgpu_gfx940::src_pops_exiting_wave_id, output_vec_len ); + case 255: return Immediate::makeImmediate(Result(u32,decodeOPR_LITERAL())); + case 249 : return decodeOPR_SDWA(); + default: return makeRegisterExpression(amdgpu_gfx940::invalid); + } + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx940::decodeOPR_SSRC_LANESEL(uint64_t input, uint32_t output_vec_len) + { + switch (input) { + case 0: return makeRegisterExpression(amdgpu_gfx940::s0, output_vec_len ); + case 1: return makeRegisterExpression(amdgpu_gfx940::s1, output_vec_len ); + case 2: return makeRegisterExpression(amdgpu_gfx940::s2, output_vec_len ); + case 3: return makeRegisterExpression(amdgpu_gfx940::s3, output_vec_len ); + case 4: return makeRegisterExpression(amdgpu_gfx940::s4, output_vec_len ); + case 5: return makeRegisterExpression(amdgpu_gfx940::s5, output_vec_len ); + case 6: return makeRegisterExpression(amdgpu_gfx940::s6, output_vec_len ); + case 7: return makeRegisterExpression(amdgpu_gfx940::s7, output_vec_len ); + case 8: return makeRegisterExpression(amdgpu_gfx940::s8, output_vec_len ); + case 9: return makeRegisterExpression(amdgpu_gfx940::s9, output_vec_len ); + case 10: return makeRegisterExpression(amdgpu_gfx940::s10, output_vec_len ); + case 11: return makeRegisterExpression(amdgpu_gfx940::s11, output_vec_len ); + case 12: return makeRegisterExpression(amdgpu_gfx940::s12, output_vec_len ); + case 13: return makeRegisterExpression(amdgpu_gfx940::s13, output_vec_len ); + case 14: return makeRegisterExpression(amdgpu_gfx940::s14, output_vec_len ); + case 15: return makeRegisterExpression(amdgpu_gfx940::s15, output_vec_len ); + case 16: return makeRegisterExpression(amdgpu_gfx940::s16, output_vec_len ); + case 17: return makeRegisterExpression(amdgpu_gfx940::s17, output_vec_len ); + case 18: return makeRegisterExpression(amdgpu_gfx940::s18, output_vec_len ); + case 19: return makeRegisterExpression(amdgpu_gfx940::s19, output_vec_len ); + case 20: return makeRegisterExpression(amdgpu_gfx940::s20, output_vec_len ); + case 21: return makeRegisterExpression(amdgpu_gfx940::s21, output_vec_len ); + case 22: return makeRegisterExpression(amdgpu_gfx940::s22, output_vec_len ); + case 23: return makeRegisterExpression(amdgpu_gfx940::s23, output_vec_len ); + case 24: return makeRegisterExpression(amdgpu_gfx940::s24, output_vec_len ); + case 25: return makeRegisterExpression(amdgpu_gfx940::s25, output_vec_len ); + case 26: return makeRegisterExpression(amdgpu_gfx940::s26, output_vec_len ); + case 27: return makeRegisterExpression(amdgpu_gfx940::s27, output_vec_len ); + case 28: return makeRegisterExpression(amdgpu_gfx940::s28, output_vec_len ); + case 29: return makeRegisterExpression(amdgpu_gfx940::s29, output_vec_len ); + case 30: return makeRegisterExpression(amdgpu_gfx940::s30, output_vec_len ); + case 31: return makeRegisterExpression(amdgpu_gfx940::s31, output_vec_len ); + case 32: return makeRegisterExpression(amdgpu_gfx940::s32, output_vec_len ); + case 33: return makeRegisterExpression(amdgpu_gfx940::s33, output_vec_len ); + case 34: return makeRegisterExpression(amdgpu_gfx940::s34, output_vec_len ); + case 35: return makeRegisterExpression(amdgpu_gfx940::s35, output_vec_len ); + case 36: return makeRegisterExpression(amdgpu_gfx940::s36, output_vec_len ); + case 37: return makeRegisterExpression(amdgpu_gfx940::s37, output_vec_len ); + case 38: return makeRegisterExpression(amdgpu_gfx940::s38, output_vec_len ); + case 39: return makeRegisterExpression(amdgpu_gfx940::s39, output_vec_len ); + case 40: return makeRegisterExpression(amdgpu_gfx940::s40, output_vec_len ); + case 41: return makeRegisterExpression(amdgpu_gfx940::s41, output_vec_len ); + case 42: return makeRegisterExpression(amdgpu_gfx940::s42, output_vec_len ); + case 43: return makeRegisterExpression(amdgpu_gfx940::s43, output_vec_len ); + case 44: return makeRegisterExpression(amdgpu_gfx940::s44, output_vec_len ); + case 45: return makeRegisterExpression(amdgpu_gfx940::s45, output_vec_len ); + case 46: return makeRegisterExpression(amdgpu_gfx940::s46, output_vec_len ); + case 47: return makeRegisterExpression(amdgpu_gfx940::s47, output_vec_len ); + case 48: return makeRegisterExpression(amdgpu_gfx940::s48, output_vec_len ); + case 49: return makeRegisterExpression(amdgpu_gfx940::s49, output_vec_len ); + case 50: return makeRegisterExpression(amdgpu_gfx940::s50, output_vec_len ); + case 51: return makeRegisterExpression(amdgpu_gfx940::s51, output_vec_len ); + case 52: return makeRegisterExpression(amdgpu_gfx940::s52, output_vec_len ); + case 53: return makeRegisterExpression(amdgpu_gfx940::s53, output_vec_len ); + case 54: return makeRegisterExpression(amdgpu_gfx940::s54, output_vec_len ); + case 55: return makeRegisterExpression(amdgpu_gfx940::s55, output_vec_len ); + case 56: return makeRegisterExpression(amdgpu_gfx940::s56, output_vec_len ); + case 57: return makeRegisterExpression(amdgpu_gfx940::s57, output_vec_len ); + case 58: return makeRegisterExpression(amdgpu_gfx940::s58, output_vec_len ); + case 59: return makeRegisterExpression(amdgpu_gfx940::s59, output_vec_len ); + case 60: return makeRegisterExpression(amdgpu_gfx940::s60, output_vec_len ); + case 61: return makeRegisterExpression(amdgpu_gfx940::s61, output_vec_len ); + case 62: return makeRegisterExpression(amdgpu_gfx940::s62, output_vec_len ); + case 63: return makeRegisterExpression(amdgpu_gfx940::s63, output_vec_len ); + case 64: return makeRegisterExpression(amdgpu_gfx940::s64, output_vec_len ); + case 65: return makeRegisterExpression(amdgpu_gfx940::s65, output_vec_len ); + case 66: return makeRegisterExpression(amdgpu_gfx940::s66, output_vec_len ); + case 67: return makeRegisterExpression(amdgpu_gfx940::s67, output_vec_len ); + case 68: return makeRegisterExpression(amdgpu_gfx940::s68, output_vec_len ); + case 69: return makeRegisterExpression(amdgpu_gfx940::s69, output_vec_len ); + case 70: return makeRegisterExpression(amdgpu_gfx940::s70, output_vec_len ); + case 71: return makeRegisterExpression(amdgpu_gfx940::s71, output_vec_len ); + case 72: return makeRegisterExpression(amdgpu_gfx940::s72, output_vec_len ); + case 73: return makeRegisterExpression(amdgpu_gfx940::s73, output_vec_len ); + case 74: return makeRegisterExpression(amdgpu_gfx940::s74, output_vec_len ); + case 75: return makeRegisterExpression(amdgpu_gfx940::s75, output_vec_len ); + case 76: return makeRegisterExpression(amdgpu_gfx940::s76, output_vec_len ); + case 77: return makeRegisterExpression(amdgpu_gfx940::s77, output_vec_len ); + case 78: return makeRegisterExpression(amdgpu_gfx940::s78, output_vec_len ); + case 79: return makeRegisterExpression(amdgpu_gfx940::s79, output_vec_len ); + case 80: return makeRegisterExpression(amdgpu_gfx940::s80, output_vec_len ); + case 81: return makeRegisterExpression(amdgpu_gfx940::s81, output_vec_len ); + case 82: return makeRegisterExpression(amdgpu_gfx940::s82, output_vec_len ); + case 83: return makeRegisterExpression(amdgpu_gfx940::s83, output_vec_len ); + case 84: return makeRegisterExpression(amdgpu_gfx940::s84, output_vec_len ); + case 85: return makeRegisterExpression(amdgpu_gfx940::s85, output_vec_len ); + case 86: return makeRegisterExpression(amdgpu_gfx940::s86, output_vec_len ); + case 87: return makeRegisterExpression(amdgpu_gfx940::s87, output_vec_len ); + case 88: return makeRegisterExpression(amdgpu_gfx940::s88, output_vec_len ); + case 89: return makeRegisterExpression(amdgpu_gfx940::s89, output_vec_len ); + case 90: return makeRegisterExpression(amdgpu_gfx940::s90, output_vec_len ); + case 91: return makeRegisterExpression(amdgpu_gfx940::s91, output_vec_len ); + case 92: return makeRegisterExpression(amdgpu_gfx940::s92, output_vec_len ); + case 93: return makeRegisterExpression(amdgpu_gfx940::s93, output_vec_len ); + case 94: return makeRegisterExpression(amdgpu_gfx940::s94, output_vec_len ); + case 95: return makeRegisterExpression(amdgpu_gfx940::s95, output_vec_len ); + case 96: return makeRegisterExpression(amdgpu_gfx940::s96, output_vec_len ); + case 97: return makeRegisterExpression(amdgpu_gfx940::s97, output_vec_len ); + case 98: return makeRegisterExpression(amdgpu_gfx940::s98, output_vec_len ); + case 99: return makeRegisterExpression(amdgpu_gfx940::s99, output_vec_len ); + case 100: return makeRegisterExpression(amdgpu_gfx940::s100, output_vec_len ); + case 101: return makeRegisterExpression(amdgpu_gfx940::s101, output_vec_len ); + case 104: return makeRegisterExpression(amdgpu_gfx940::xnack_mask_lo, output_vec_len ); + case 105: return makeRegisterExpression(amdgpu_gfx940::xnack_mask_hi, output_vec_len ); + case 102: return makeRegisterExpression(amdgpu_gfx940::flat_scratch_lo, output_vec_len ); + case 103: return makeRegisterExpression(amdgpu_gfx940::flat_scratch_hi, output_vec_len ); + case 108: return makeRegisterExpression(amdgpu_gfx940::ttmp0, output_vec_len ); + case 109: return makeRegisterExpression(amdgpu_gfx940::ttmp1, output_vec_len ); + case 110: return makeRegisterExpression(amdgpu_gfx940::ttmp2, output_vec_len ); + case 111: return makeRegisterExpression(amdgpu_gfx940::ttmp3, output_vec_len ); + case 112: return makeRegisterExpression(amdgpu_gfx940::ttmp4, output_vec_len ); + case 113: return makeRegisterExpression(amdgpu_gfx940::ttmp5, output_vec_len ); + case 114: return makeRegisterExpression(amdgpu_gfx940::ttmp6, output_vec_len ); + case 115: return makeRegisterExpression(amdgpu_gfx940::ttmp7, output_vec_len ); + case 116: return makeRegisterExpression(amdgpu_gfx940::ttmp8, output_vec_len ); + case 117: return makeRegisterExpression(amdgpu_gfx940::ttmp9, output_vec_len ); + case 118: return makeRegisterExpression(amdgpu_gfx940::ttmp10, output_vec_len ); + case 119: return makeRegisterExpression(amdgpu_gfx940::ttmp11, output_vec_len ); + case 120: return makeRegisterExpression(amdgpu_gfx940::ttmp12, output_vec_len ); + case 121: return makeRegisterExpression(amdgpu_gfx940::ttmp13, output_vec_len ); + case 122: return makeRegisterExpression(amdgpu_gfx940::ttmp14, output_vec_len ); + case 123: return makeRegisterExpression(amdgpu_gfx940::ttmp15, output_vec_len ); + case 106: return makeRegisterExpression(amdgpu_gfx940::vcc_lo, output_vec_len ); + case 107: return makeRegisterExpression(amdgpu_gfx940::vcc_hi, output_vec_len ); + case 124: return makeRegisterExpression(amdgpu_gfx940::m0, output_vec_len ); + case 128: return Immediate::makeImmediate(Result(u32, 0)); + case 129: return Immediate::makeImmediate(Result(u32, 1)); + case 130: return Immediate::makeImmediate(Result(u32, 2)); + case 131: return Immediate::makeImmediate(Result(u32, 3)); + case 132: return Immediate::makeImmediate(Result(u32, 4)); + case 133: return Immediate::makeImmediate(Result(u32, 5)); + case 134: return Immediate::makeImmediate(Result(u32, 6)); + case 135: return Immediate::makeImmediate(Result(u32, 7)); + case 136: return Immediate::makeImmediate(Result(u32, 8)); + case 137: return Immediate::makeImmediate(Result(u32, 9)); + case 138: return Immediate::makeImmediate(Result(u32, 10)); + case 139: return Immediate::makeImmediate(Result(u32, 11)); + case 140: return Immediate::makeImmediate(Result(u32, 12)); + case 141: return Immediate::makeImmediate(Result(u32, 13)); + case 142: return Immediate::makeImmediate(Result(u32, 14)); + case 143: return Immediate::makeImmediate(Result(u32, 15)); + case 144: return Immediate::makeImmediate(Result(u32, 16)); + case 145: return Immediate::makeImmediate(Result(u32, 17)); + case 146: return Immediate::makeImmediate(Result(u32, 18)); + case 147: return Immediate::makeImmediate(Result(u32, 19)); + case 148: return Immediate::makeImmediate(Result(u32, 20)); + case 149: return Immediate::makeImmediate(Result(u32, 21)); + case 150: return Immediate::makeImmediate(Result(u32, 22)); + case 151: return Immediate::makeImmediate(Result(u32, 23)); + case 152: return Immediate::makeImmediate(Result(u32, 24)); + case 153: return Immediate::makeImmediate(Result(u32, 25)); + case 154: return Immediate::makeImmediate(Result(u32, 26)); + case 155: return Immediate::makeImmediate(Result(u32, 27)); + case 156: return Immediate::makeImmediate(Result(u32, 28)); + case 157: return Immediate::makeImmediate(Result(u32, 29)); + case 158: return Immediate::makeImmediate(Result(u32, 30)); + case 159: return Immediate::makeImmediate(Result(u32, 31)); + case 160: return Immediate::makeImmediate(Result(u32, 32)); + case 161: return Immediate::makeImmediate(Result(u32, 33)); + case 162: return Immediate::makeImmediate(Result(u32, 34)); + case 163: return Immediate::makeImmediate(Result(u32, 35)); + case 164: return Immediate::makeImmediate(Result(u32, 36)); + case 165: return Immediate::makeImmediate(Result(u32, 37)); + case 166: return Immediate::makeImmediate(Result(u32, 38)); + case 167: return Immediate::makeImmediate(Result(u32, 39)); + case 168: return Immediate::makeImmediate(Result(u32, 40)); + case 169: return Immediate::makeImmediate(Result(u32, 41)); + case 170: return Immediate::makeImmediate(Result(u32, 42)); + case 171: return Immediate::makeImmediate(Result(u32, 43)); + case 172: return Immediate::makeImmediate(Result(u32, 44)); + case 173: return Immediate::makeImmediate(Result(u32, 45)); + case 174: return Immediate::makeImmediate(Result(u32, 46)); + case 175: return Immediate::makeImmediate(Result(u32, 47)); + case 176: return Immediate::makeImmediate(Result(u32, 48)); + case 177: return Immediate::makeImmediate(Result(u32, 49)); + case 178: return Immediate::makeImmediate(Result(u32, 50)); + case 179: return Immediate::makeImmediate(Result(u32, 51)); + case 180: return Immediate::makeImmediate(Result(u32, 52)); + case 181: return Immediate::makeImmediate(Result(u32, 53)); + case 182: return Immediate::makeImmediate(Result(u32, 54)); + case 183: return Immediate::makeImmediate(Result(u32, 55)); + case 184: return Immediate::makeImmediate(Result(u32, 56)); + case 185: return Immediate::makeImmediate(Result(u32, 57)); + case 186: return Immediate::makeImmediate(Result(u32, 58)); + case 187: return Immediate::makeImmediate(Result(u32, 59)); + case 188: return Immediate::makeImmediate(Result(u32, 60)); + case 189: return Immediate::makeImmediate(Result(u32, 61)); + case 190: return Immediate::makeImmediate(Result(u32, 62)); + case 191: return Immediate::makeImmediate(Result(u32, 63)); + default: return makeRegisterExpression(amdgpu_gfx940::invalid); + } + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx940::decodeOPR_SSRC_NOLIT(uint64_t input, uint32_t output_vec_len) + { + switch (input) { + case 0: return makeRegisterExpression(amdgpu_gfx940::s0, output_vec_len ); + case 1: return makeRegisterExpression(amdgpu_gfx940::s1, output_vec_len ); + case 2: return makeRegisterExpression(amdgpu_gfx940::s2, output_vec_len ); + case 3: return makeRegisterExpression(amdgpu_gfx940::s3, output_vec_len ); + case 4: return makeRegisterExpression(amdgpu_gfx940::s4, output_vec_len ); + case 5: return makeRegisterExpression(amdgpu_gfx940::s5, output_vec_len ); + case 6: return makeRegisterExpression(amdgpu_gfx940::s6, output_vec_len ); + case 7: return makeRegisterExpression(amdgpu_gfx940::s7, output_vec_len ); + case 8: return makeRegisterExpression(amdgpu_gfx940::s8, output_vec_len ); + case 9: return makeRegisterExpression(amdgpu_gfx940::s9, output_vec_len ); + case 10: return makeRegisterExpression(amdgpu_gfx940::s10, output_vec_len ); + case 11: return makeRegisterExpression(amdgpu_gfx940::s11, output_vec_len ); + case 12: return makeRegisterExpression(amdgpu_gfx940::s12, output_vec_len ); + case 13: return makeRegisterExpression(amdgpu_gfx940::s13, output_vec_len ); + case 14: return makeRegisterExpression(amdgpu_gfx940::s14, output_vec_len ); + case 15: return makeRegisterExpression(amdgpu_gfx940::s15, output_vec_len ); + case 16: return makeRegisterExpression(amdgpu_gfx940::s16, output_vec_len ); + case 17: return makeRegisterExpression(amdgpu_gfx940::s17, output_vec_len ); + case 18: return makeRegisterExpression(amdgpu_gfx940::s18, output_vec_len ); + case 19: return makeRegisterExpression(amdgpu_gfx940::s19, output_vec_len ); + case 20: return makeRegisterExpression(amdgpu_gfx940::s20, output_vec_len ); + case 21: return makeRegisterExpression(amdgpu_gfx940::s21, output_vec_len ); + case 22: return makeRegisterExpression(amdgpu_gfx940::s22, output_vec_len ); + case 23: return makeRegisterExpression(amdgpu_gfx940::s23, output_vec_len ); + case 24: return makeRegisterExpression(amdgpu_gfx940::s24, output_vec_len ); + case 25: return makeRegisterExpression(amdgpu_gfx940::s25, output_vec_len ); + case 26: return makeRegisterExpression(amdgpu_gfx940::s26, output_vec_len ); + case 27: return makeRegisterExpression(amdgpu_gfx940::s27, output_vec_len ); + case 28: return makeRegisterExpression(amdgpu_gfx940::s28, output_vec_len ); + case 29: return makeRegisterExpression(amdgpu_gfx940::s29, output_vec_len ); + case 30: return makeRegisterExpression(amdgpu_gfx940::s30, output_vec_len ); + case 31: return makeRegisterExpression(amdgpu_gfx940::s31, output_vec_len ); + case 32: return makeRegisterExpression(amdgpu_gfx940::s32, output_vec_len ); + case 33: return makeRegisterExpression(amdgpu_gfx940::s33, output_vec_len ); + case 34: return makeRegisterExpression(amdgpu_gfx940::s34, output_vec_len ); + case 35: return makeRegisterExpression(amdgpu_gfx940::s35, output_vec_len ); + case 36: return makeRegisterExpression(amdgpu_gfx940::s36, output_vec_len ); + case 37: return makeRegisterExpression(amdgpu_gfx940::s37, output_vec_len ); + case 38: return makeRegisterExpression(amdgpu_gfx940::s38, output_vec_len ); + case 39: return makeRegisterExpression(amdgpu_gfx940::s39, output_vec_len ); + case 40: return makeRegisterExpression(amdgpu_gfx940::s40, output_vec_len ); + case 41: return makeRegisterExpression(amdgpu_gfx940::s41, output_vec_len ); + case 42: return makeRegisterExpression(amdgpu_gfx940::s42, output_vec_len ); + case 43: return makeRegisterExpression(amdgpu_gfx940::s43, output_vec_len ); + case 44: return makeRegisterExpression(amdgpu_gfx940::s44, output_vec_len ); + case 45: return makeRegisterExpression(amdgpu_gfx940::s45, output_vec_len ); + case 46: return makeRegisterExpression(amdgpu_gfx940::s46, output_vec_len ); + case 47: return makeRegisterExpression(amdgpu_gfx940::s47, output_vec_len ); + case 48: return makeRegisterExpression(amdgpu_gfx940::s48, output_vec_len ); + case 49: return makeRegisterExpression(amdgpu_gfx940::s49, output_vec_len ); + case 50: return makeRegisterExpression(amdgpu_gfx940::s50, output_vec_len ); + case 51: return makeRegisterExpression(amdgpu_gfx940::s51, output_vec_len ); + case 52: return makeRegisterExpression(amdgpu_gfx940::s52, output_vec_len ); + case 53: return makeRegisterExpression(amdgpu_gfx940::s53, output_vec_len ); + case 54: return makeRegisterExpression(amdgpu_gfx940::s54, output_vec_len ); + case 55: return makeRegisterExpression(amdgpu_gfx940::s55, output_vec_len ); + case 56: return makeRegisterExpression(amdgpu_gfx940::s56, output_vec_len ); + case 57: return makeRegisterExpression(amdgpu_gfx940::s57, output_vec_len ); + case 58: return makeRegisterExpression(amdgpu_gfx940::s58, output_vec_len ); + case 59: return makeRegisterExpression(amdgpu_gfx940::s59, output_vec_len ); + case 60: return makeRegisterExpression(amdgpu_gfx940::s60, output_vec_len ); + case 61: return makeRegisterExpression(amdgpu_gfx940::s61, output_vec_len ); + case 62: return makeRegisterExpression(amdgpu_gfx940::s62, output_vec_len ); + case 63: return makeRegisterExpression(amdgpu_gfx940::s63, output_vec_len ); + case 64: return makeRegisterExpression(amdgpu_gfx940::s64, output_vec_len ); + case 65: return makeRegisterExpression(amdgpu_gfx940::s65, output_vec_len ); + case 66: return makeRegisterExpression(amdgpu_gfx940::s66, output_vec_len ); + case 67: return makeRegisterExpression(amdgpu_gfx940::s67, output_vec_len ); + case 68: return makeRegisterExpression(amdgpu_gfx940::s68, output_vec_len ); + case 69: return makeRegisterExpression(amdgpu_gfx940::s69, output_vec_len ); + case 70: return makeRegisterExpression(amdgpu_gfx940::s70, output_vec_len ); + case 71: return makeRegisterExpression(amdgpu_gfx940::s71, output_vec_len ); + case 72: return makeRegisterExpression(amdgpu_gfx940::s72, output_vec_len ); + case 73: return makeRegisterExpression(amdgpu_gfx940::s73, output_vec_len ); + case 74: return makeRegisterExpression(amdgpu_gfx940::s74, output_vec_len ); + case 75: return makeRegisterExpression(amdgpu_gfx940::s75, output_vec_len ); + case 76: return makeRegisterExpression(amdgpu_gfx940::s76, output_vec_len ); + case 77: return makeRegisterExpression(amdgpu_gfx940::s77, output_vec_len ); + case 78: return makeRegisterExpression(amdgpu_gfx940::s78, output_vec_len ); + case 79: return makeRegisterExpression(amdgpu_gfx940::s79, output_vec_len ); + case 80: return makeRegisterExpression(amdgpu_gfx940::s80, output_vec_len ); + case 81: return makeRegisterExpression(amdgpu_gfx940::s81, output_vec_len ); + case 82: return makeRegisterExpression(amdgpu_gfx940::s82, output_vec_len ); + case 83: return makeRegisterExpression(amdgpu_gfx940::s83, output_vec_len ); + case 84: return makeRegisterExpression(amdgpu_gfx940::s84, output_vec_len ); + case 85: return makeRegisterExpression(amdgpu_gfx940::s85, output_vec_len ); + case 86: return makeRegisterExpression(amdgpu_gfx940::s86, output_vec_len ); + case 87: return makeRegisterExpression(amdgpu_gfx940::s87, output_vec_len ); + case 88: return makeRegisterExpression(amdgpu_gfx940::s88, output_vec_len ); + case 89: return makeRegisterExpression(amdgpu_gfx940::s89, output_vec_len ); + case 90: return makeRegisterExpression(amdgpu_gfx940::s90, output_vec_len ); + case 91: return makeRegisterExpression(amdgpu_gfx940::s91, output_vec_len ); + case 92: return makeRegisterExpression(amdgpu_gfx940::s92, output_vec_len ); + case 93: return makeRegisterExpression(amdgpu_gfx940::s93, output_vec_len ); + case 94: return makeRegisterExpression(amdgpu_gfx940::s94, output_vec_len ); + case 95: return makeRegisterExpression(amdgpu_gfx940::s95, output_vec_len ); + case 96: return makeRegisterExpression(amdgpu_gfx940::s96, output_vec_len ); + case 97: return makeRegisterExpression(amdgpu_gfx940::s97, output_vec_len ); + case 98: return makeRegisterExpression(amdgpu_gfx940::s98, output_vec_len ); + case 99: return makeRegisterExpression(amdgpu_gfx940::s99, output_vec_len ); + case 100: return makeRegisterExpression(amdgpu_gfx940::s100, output_vec_len ); + case 101: return makeRegisterExpression(amdgpu_gfx940::s101, output_vec_len ); + case 104: return makeRegisterExpression(amdgpu_gfx940::xnack_mask_lo, output_vec_len ); + case 105: return makeRegisterExpression(amdgpu_gfx940::xnack_mask_hi, output_vec_len ); + case 102: return makeRegisterExpression(amdgpu_gfx940::flat_scratch_lo, output_vec_len ); + case 103: return makeRegisterExpression(amdgpu_gfx940::flat_scratch_hi, output_vec_len ); + case 108: return makeRegisterExpression(amdgpu_gfx940::ttmp0, output_vec_len ); + case 109: return makeRegisterExpression(amdgpu_gfx940::ttmp1, output_vec_len ); + case 110: return makeRegisterExpression(amdgpu_gfx940::ttmp2, output_vec_len ); + case 111: return makeRegisterExpression(amdgpu_gfx940::ttmp3, output_vec_len ); + case 112: return makeRegisterExpression(amdgpu_gfx940::ttmp4, output_vec_len ); + case 113: return makeRegisterExpression(amdgpu_gfx940::ttmp5, output_vec_len ); + case 114: return makeRegisterExpression(amdgpu_gfx940::ttmp6, output_vec_len ); + case 115: return makeRegisterExpression(amdgpu_gfx940::ttmp7, output_vec_len ); + case 116: return makeRegisterExpression(amdgpu_gfx940::ttmp8, output_vec_len ); + case 117: return makeRegisterExpression(amdgpu_gfx940::ttmp9, output_vec_len ); + case 118: return makeRegisterExpression(amdgpu_gfx940::ttmp10, output_vec_len ); + case 119: return makeRegisterExpression(amdgpu_gfx940::ttmp11, output_vec_len ); + case 120: return makeRegisterExpression(amdgpu_gfx940::ttmp12, output_vec_len ); + case 121: return makeRegisterExpression(amdgpu_gfx940::ttmp13, output_vec_len ); + case 122: return makeRegisterExpression(amdgpu_gfx940::ttmp14, output_vec_len ); + case 123: return makeRegisterExpression(amdgpu_gfx940::ttmp15, output_vec_len ); + case 106: return makeRegisterExpression(amdgpu_gfx940::vcc_lo, output_vec_len ); + case 107: return makeRegisterExpression(amdgpu_gfx940::vcc_hi, output_vec_len ); + case 124: return makeRegisterExpression(amdgpu_gfx940::m0, output_vec_len ); + case 126: return makeRegisterExpression(amdgpu_gfx940::exec_lo, output_vec_len ); + case 127: return makeRegisterExpression(amdgpu_gfx940::exec_hi, output_vec_len ); + case 128: return Immediate::makeImmediate(Result(u32, 0)); + case 129: return Immediate::makeImmediate(Result(u32, 1)); + case 130: return Immediate::makeImmediate(Result(u32, 2)); + case 131: return Immediate::makeImmediate(Result(u32, 3)); + case 132: return Immediate::makeImmediate(Result(u32, 4)); + case 133: return Immediate::makeImmediate(Result(u32, 5)); + case 134: return Immediate::makeImmediate(Result(u32, 6)); + case 135: return Immediate::makeImmediate(Result(u32, 7)); + case 136: return Immediate::makeImmediate(Result(u32, 8)); + case 137: return Immediate::makeImmediate(Result(u32, 9)); + case 138: return Immediate::makeImmediate(Result(u32, 10)); + case 139: return Immediate::makeImmediate(Result(u32, 11)); + case 140: return Immediate::makeImmediate(Result(u32, 12)); + case 141: return Immediate::makeImmediate(Result(u32, 13)); + case 142: return Immediate::makeImmediate(Result(u32, 14)); + case 143: return Immediate::makeImmediate(Result(u32, 15)); + case 144: return Immediate::makeImmediate(Result(u32, 16)); + case 145: return Immediate::makeImmediate(Result(u32, 17)); + case 146: return Immediate::makeImmediate(Result(u32, 18)); + case 147: return Immediate::makeImmediate(Result(u32, 19)); + case 148: return Immediate::makeImmediate(Result(u32, 20)); + case 149: return Immediate::makeImmediate(Result(u32, 21)); + case 150: return Immediate::makeImmediate(Result(u32, 22)); + case 151: return Immediate::makeImmediate(Result(u32, 23)); + case 152: return Immediate::makeImmediate(Result(u32, 24)); + case 153: return Immediate::makeImmediate(Result(u32, 25)); + case 154: return Immediate::makeImmediate(Result(u32, 26)); + case 155: return Immediate::makeImmediate(Result(u32, 27)); + case 156: return Immediate::makeImmediate(Result(u32, 28)); + case 157: return Immediate::makeImmediate(Result(u32, 29)); + case 158: return Immediate::makeImmediate(Result(u32, 30)); + case 159: return Immediate::makeImmediate(Result(u32, 31)); + case 160: return Immediate::makeImmediate(Result(u32, 32)); + case 161: return Immediate::makeImmediate(Result(u32, 33)); + case 162: return Immediate::makeImmediate(Result(u32, 34)); + case 163: return Immediate::makeImmediate(Result(u32, 35)); + case 164: return Immediate::makeImmediate(Result(u32, 36)); + case 165: return Immediate::makeImmediate(Result(u32, 37)); + case 166: return Immediate::makeImmediate(Result(u32, 38)); + case 167: return Immediate::makeImmediate(Result(u32, 39)); + case 168: return Immediate::makeImmediate(Result(u32, 40)); + case 169: return Immediate::makeImmediate(Result(u32, 41)); + case 170: return Immediate::makeImmediate(Result(u32, 42)); + case 171: return Immediate::makeImmediate(Result(u32, 43)); + case 172: return Immediate::makeImmediate(Result(u32, 44)); + case 173: return Immediate::makeImmediate(Result(u32, 45)); + case 174: return Immediate::makeImmediate(Result(u32, 46)); + case 175: return Immediate::makeImmediate(Result(u32, 47)); + case 176: return Immediate::makeImmediate(Result(u32, 48)); + case 177: return Immediate::makeImmediate(Result(u32, 49)); + case 178: return Immediate::makeImmediate(Result(u32, 50)); + case 179: return Immediate::makeImmediate(Result(u32, 51)); + case 180: return Immediate::makeImmediate(Result(u32, 52)); + case 181: return Immediate::makeImmediate(Result(u32, 53)); + case 182: return Immediate::makeImmediate(Result(u32, 54)); + case 183: return Immediate::makeImmediate(Result(u32, 55)); + case 184: return Immediate::makeImmediate(Result(u32, 56)); + case 185: return Immediate::makeImmediate(Result(u32, 57)); + case 186: return Immediate::makeImmediate(Result(u32, 58)); + case 187: return Immediate::makeImmediate(Result(u32, 59)); + case 188: return Immediate::makeImmediate(Result(u32, 60)); + case 189: return Immediate::makeImmediate(Result(u32, 61)); + case 190: return Immediate::makeImmediate(Result(u32, 62)); + case 191: return Immediate::makeImmediate(Result(u32, 63)); + case 192: return Immediate::makeImmediate(Result(u32, 64)); + case 193: return Immediate::makeImmediate(Result(u32, -1)); + case 194: return Immediate::makeImmediate(Result(u32, -2)); + case 195: return Immediate::makeImmediate(Result(u32, -3)); + case 196: return Immediate::makeImmediate(Result(u32, -4)); + case 197: return Immediate::makeImmediate(Result(u32, -5)); + case 198: return Immediate::makeImmediate(Result(u32, -6)); + case 199: return Immediate::makeImmediate(Result(u32, -7)); + case 200: return Immediate::makeImmediate(Result(u32, -8)); + case 201: return Immediate::makeImmediate(Result(u32, -9)); + case 202: return Immediate::makeImmediate(Result(u32, -10)); + case 203: return Immediate::makeImmediate(Result(u32, -11)); + case 204: return Immediate::makeImmediate(Result(u32, -12)); + case 205: return Immediate::makeImmediate(Result(u32, -13)); + case 206: return Immediate::makeImmediate(Result(u32, -14)); + case 207: return Immediate::makeImmediate(Result(u32, -15)); + case 208: return Immediate::makeImmediate(Result(u32, -16)); + case 240: return Immediate::makeImmediate(Result(sp_float, 0.5)); + case 241: return Immediate::makeImmediate(Result(sp_float, -0.5)); + case 242: return Immediate::makeImmediate(Result(sp_float, 1.0)); + case 243: return Immediate::makeImmediate(Result(sp_float, -1.0)); + case 244: return Immediate::makeImmediate(Result(sp_float, 2.0)); + case 245: return Immediate::makeImmediate(Result(sp_float, -2.0)); + case 246: return Immediate::makeImmediate(Result(sp_float, 4.0)); + case 247: return Immediate::makeImmediate(Result(sp_float, -4.0)); + case 248: return Immediate::makeImmediate(Result(sp_float, 0.15915494)); + case 251: return makeRegisterExpression(amdgpu_gfx940::src_vccz, output_vec_len ); + case 252: return makeRegisterExpression(amdgpu_gfx940::src_execz, output_vec_len ); + case 253: return makeRegisterExpression(amdgpu_gfx940::src_scc, output_vec_len ); + case 235: return makeRegisterExpression(amdgpu_gfx940::src_shared_base, output_vec_len ); + case 236: return makeRegisterExpression(amdgpu_gfx940::src_shared_limit, output_vec_len ); + case 237: return makeRegisterExpression(amdgpu_gfx940::src_private_base, output_vec_len ); + case 238: return makeRegisterExpression(amdgpu_gfx940::src_private_limit, output_vec_len ); + case 239: return makeRegisterExpression(amdgpu_gfx940::src_pops_exiting_wave_id, output_vec_len ); + default: return makeRegisterExpression(amdgpu_gfx940::invalid); + } + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx940::decodeOPR_SSRC_SPECIAL_SCC(uint64_t input, uint32_t output_vec_len) + { + switch (input) { + case 253: return makeRegisterExpression(amdgpu_gfx940::src_scc, output_vec_len ); + default: return makeRegisterExpression(amdgpu_gfx940::invalid); + } + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx940::decodeOPR_VCC(uint64_t input, uint32_t ) + { + switch (input) { + case 0: return makeRegisterExpression(amdgpu_gfx940::vcc); + default: return makeRegisterExpression(amdgpu_gfx940::invalid); + } + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx940::decodeOPR_VGPR(uint64_t input, uint32_t output_vec_len) + { + switch (input) { + case 0: return makeRegisterExpression(amdgpu_gfx940::v0, output_vec_len ); + case 1: return makeRegisterExpression(amdgpu_gfx940::v1, output_vec_len ); + case 2: return makeRegisterExpression(amdgpu_gfx940::v2, output_vec_len ); + case 3: return makeRegisterExpression(amdgpu_gfx940::v3, output_vec_len ); + case 4: return makeRegisterExpression(amdgpu_gfx940::v4, output_vec_len ); + case 5: return makeRegisterExpression(amdgpu_gfx940::v5, output_vec_len ); + case 6: return makeRegisterExpression(amdgpu_gfx940::v6, output_vec_len ); + case 7: return makeRegisterExpression(amdgpu_gfx940::v7, output_vec_len ); + case 8: return makeRegisterExpression(amdgpu_gfx940::v8, output_vec_len ); + case 9: return makeRegisterExpression(amdgpu_gfx940::v9, output_vec_len ); + case 10: return makeRegisterExpression(amdgpu_gfx940::v10, output_vec_len ); + case 11: return makeRegisterExpression(amdgpu_gfx940::v11, output_vec_len ); + case 12: return makeRegisterExpression(amdgpu_gfx940::v12, output_vec_len ); + case 13: return makeRegisterExpression(amdgpu_gfx940::v13, output_vec_len ); + case 14: return makeRegisterExpression(amdgpu_gfx940::v14, output_vec_len ); + case 15: return makeRegisterExpression(amdgpu_gfx940::v15, output_vec_len ); + case 16: return makeRegisterExpression(amdgpu_gfx940::v16, output_vec_len ); + case 17: return makeRegisterExpression(amdgpu_gfx940::v17, output_vec_len ); + case 18: return makeRegisterExpression(amdgpu_gfx940::v18, output_vec_len ); + case 19: return makeRegisterExpression(amdgpu_gfx940::v19, output_vec_len ); + case 20: return makeRegisterExpression(amdgpu_gfx940::v20, output_vec_len ); + case 21: return makeRegisterExpression(amdgpu_gfx940::v21, output_vec_len ); + case 22: return makeRegisterExpression(amdgpu_gfx940::v22, output_vec_len ); + case 23: return makeRegisterExpression(amdgpu_gfx940::v23, output_vec_len ); + case 24: return makeRegisterExpression(amdgpu_gfx940::v24, output_vec_len ); + case 25: return makeRegisterExpression(amdgpu_gfx940::v25, output_vec_len ); + case 26: return makeRegisterExpression(amdgpu_gfx940::v26, output_vec_len ); + case 27: return makeRegisterExpression(amdgpu_gfx940::v27, output_vec_len ); + case 28: return makeRegisterExpression(amdgpu_gfx940::v28, output_vec_len ); + case 29: return makeRegisterExpression(amdgpu_gfx940::v29, output_vec_len ); + case 30: return makeRegisterExpression(amdgpu_gfx940::v30, output_vec_len ); + case 31: return makeRegisterExpression(amdgpu_gfx940::v31, output_vec_len ); + case 32: return makeRegisterExpression(amdgpu_gfx940::v32, output_vec_len ); + case 33: return makeRegisterExpression(amdgpu_gfx940::v33, output_vec_len ); + case 34: return makeRegisterExpression(amdgpu_gfx940::v34, output_vec_len ); + case 35: return makeRegisterExpression(amdgpu_gfx940::v35, output_vec_len ); + case 36: return makeRegisterExpression(amdgpu_gfx940::v36, output_vec_len ); + case 37: return makeRegisterExpression(amdgpu_gfx940::v37, output_vec_len ); + case 38: return makeRegisterExpression(amdgpu_gfx940::v38, output_vec_len ); + case 39: return makeRegisterExpression(amdgpu_gfx940::v39, output_vec_len ); + case 40: return makeRegisterExpression(amdgpu_gfx940::v40, output_vec_len ); + case 41: return makeRegisterExpression(amdgpu_gfx940::v41, output_vec_len ); + case 42: return makeRegisterExpression(amdgpu_gfx940::v42, output_vec_len ); + case 43: return makeRegisterExpression(amdgpu_gfx940::v43, output_vec_len ); + case 44: return makeRegisterExpression(amdgpu_gfx940::v44, output_vec_len ); + case 45: return makeRegisterExpression(amdgpu_gfx940::v45, output_vec_len ); + case 46: return makeRegisterExpression(amdgpu_gfx940::v46, output_vec_len ); + case 47: return makeRegisterExpression(amdgpu_gfx940::v47, output_vec_len ); + case 48: return makeRegisterExpression(amdgpu_gfx940::v48, output_vec_len ); + case 49: return makeRegisterExpression(amdgpu_gfx940::v49, output_vec_len ); + case 50: return makeRegisterExpression(amdgpu_gfx940::v50, output_vec_len ); + case 51: return makeRegisterExpression(amdgpu_gfx940::v51, output_vec_len ); + case 52: return makeRegisterExpression(amdgpu_gfx940::v52, output_vec_len ); + case 53: return makeRegisterExpression(amdgpu_gfx940::v53, output_vec_len ); + case 54: return makeRegisterExpression(amdgpu_gfx940::v54, output_vec_len ); + case 55: return makeRegisterExpression(amdgpu_gfx940::v55, output_vec_len ); + case 56: return makeRegisterExpression(amdgpu_gfx940::v56, output_vec_len ); + case 57: return makeRegisterExpression(amdgpu_gfx940::v57, output_vec_len ); + case 58: return makeRegisterExpression(amdgpu_gfx940::v58, output_vec_len ); + case 59: return makeRegisterExpression(amdgpu_gfx940::v59, output_vec_len ); + case 60: return makeRegisterExpression(amdgpu_gfx940::v60, output_vec_len ); + case 61: return makeRegisterExpression(amdgpu_gfx940::v61, output_vec_len ); + case 62: return makeRegisterExpression(amdgpu_gfx940::v62, output_vec_len ); + case 63: return makeRegisterExpression(amdgpu_gfx940::v63, output_vec_len ); + case 64: return makeRegisterExpression(amdgpu_gfx940::v64, output_vec_len ); + case 65: return makeRegisterExpression(amdgpu_gfx940::v65, output_vec_len ); + case 66: return makeRegisterExpression(amdgpu_gfx940::v66, output_vec_len ); + case 67: return makeRegisterExpression(amdgpu_gfx940::v67, output_vec_len ); + case 68: return makeRegisterExpression(amdgpu_gfx940::v68, output_vec_len ); + case 69: return makeRegisterExpression(amdgpu_gfx940::v69, output_vec_len ); + case 70: return makeRegisterExpression(amdgpu_gfx940::v70, output_vec_len ); + case 71: return makeRegisterExpression(amdgpu_gfx940::v71, output_vec_len ); + case 72: return makeRegisterExpression(amdgpu_gfx940::v72, output_vec_len ); + case 73: return makeRegisterExpression(amdgpu_gfx940::v73, output_vec_len ); + case 74: return makeRegisterExpression(amdgpu_gfx940::v74, output_vec_len ); + case 75: return makeRegisterExpression(amdgpu_gfx940::v75, output_vec_len ); + case 76: return makeRegisterExpression(amdgpu_gfx940::v76, output_vec_len ); + case 77: return makeRegisterExpression(amdgpu_gfx940::v77, output_vec_len ); + case 78: return makeRegisterExpression(amdgpu_gfx940::v78, output_vec_len ); + case 79: return makeRegisterExpression(amdgpu_gfx940::v79, output_vec_len ); + case 80: return makeRegisterExpression(amdgpu_gfx940::v80, output_vec_len ); + case 81: return makeRegisterExpression(amdgpu_gfx940::v81, output_vec_len ); + case 82: return makeRegisterExpression(amdgpu_gfx940::v82, output_vec_len ); + case 83: return makeRegisterExpression(amdgpu_gfx940::v83, output_vec_len ); + case 84: return makeRegisterExpression(amdgpu_gfx940::v84, output_vec_len ); + case 85: return makeRegisterExpression(amdgpu_gfx940::v85, output_vec_len ); + case 86: return makeRegisterExpression(amdgpu_gfx940::v86, output_vec_len ); + case 87: return makeRegisterExpression(amdgpu_gfx940::v87, output_vec_len ); + case 88: return makeRegisterExpression(amdgpu_gfx940::v88, output_vec_len ); + case 89: return makeRegisterExpression(amdgpu_gfx940::v89, output_vec_len ); + case 90: return makeRegisterExpression(amdgpu_gfx940::v90, output_vec_len ); + case 91: return makeRegisterExpression(amdgpu_gfx940::v91, output_vec_len ); + case 92: return makeRegisterExpression(amdgpu_gfx940::v92, output_vec_len ); + case 93: return makeRegisterExpression(amdgpu_gfx940::v93, output_vec_len ); + case 94: return makeRegisterExpression(amdgpu_gfx940::v94, output_vec_len ); + case 95: return makeRegisterExpression(amdgpu_gfx940::v95, output_vec_len ); + case 96: return makeRegisterExpression(amdgpu_gfx940::v96, output_vec_len ); + case 97: return makeRegisterExpression(amdgpu_gfx940::v97, output_vec_len ); + case 98: return makeRegisterExpression(amdgpu_gfx940::v98, output_vec_len ); + case 99: return makeRegisterExpression(amdgpu_gfx940::v99, output_vec_len ); + case 100: return makeRegisterExpression(amdgpu_gfx940::v100, output_vec_len ); + case 101: return makeRegisterExpression(amdgpu_gfx940::v101, output_vec_len ); + case 102: return makeRegisterExpression(amdgpu_gfx940::v102, output_vec_len ); + case 103: return makeRegisterExpression(amdgpu_gfx940::v103, output_vec_len ); + case 104: return makeRegisterExpression(amdgpu_gfx940::v104, output_vec_len ); + case 105: return makeRegisterExpression(amdgpu_gfx940::v105, output_vec_len ); + case 106: return makeRegisterExpression(amdgpu_gfx940::v106, output_vec_len ); + case 107: return makeRegisterExpression(amdgpu_gfx940::v107, output_vec_len ); + case 108: return makeRegisterExpression(amdgpu_gfx940::v108, output_vec_len ); + case 109: return makeRegisterExpression(amdgpu_gfx940::v109, output_vec_len ); + case 110: return makeRegisterExpression(amdgpu_gfx940::v110, output_vec_len ); + case 111: return makeRegisterExpression(amdgpu_gfx940::v111, output_vec_len ); + case 112: return makeRegisterExpression(amdgpu_gfx940::v112, output_vec_len ); + case 113: return makeRegisterExpression(amdgpu_gfx940::v113, output_vec_len ); + case 114: return makeRegisterExpression(amdgpu_gfx940::v114, output_vec_len ); + case 115: return makeRegisterExpression(amdgpu_gfx940::v115, output_vec_len ); + case 116: return makeRegisterExpression(amdgpu_gfx940::v116, output_vec_len ); + case 117: return makeRegisterExpression(amdgpu_gfx940::v117, output_vec_len ); + case 118: return makeRegisterExpression(amdgpu_gfx940::v118, output_vec_len ); + case 119: return makeRegisterExpression(amdgpu_gfx940::v119, output_vec_len ); + case 120: return makeRegisterExpression(amdgpu_gfx940::v120, output_vec_len ); + case 121: return makeRegisterExpression(amdgpu_gfx940::v121, output_vec_len ); + case 122: return makeRegisterExpression(amdgpu_gfx940::v122, output_vec_len ); + case 123: return makeRegisterExpression(amdgpu_gfx940::v123, output_vec_len ); + case 124: return makeRegisterExpression(amdgpu_gfx940::v124, output_vec_len ); + case 125: return makeRegisterExpression(amdgpu_gfx940::v125, output_vec_len ); + case 126: return makeRegisterExpression(amdgpu_gfx940::v126, output_vec_len ); + case 127: return makeRegisterExpression(amdgpu_gfx940::v127, output_vec_len ); + case 128: return makeRegisterExpression(amdgpu_gfx940::v128, output_vec_len ); + case 129: return makeRegisterExpression(amdgpu_gfx940::v129, output_vec_len ); + case 130: return makeRegisterExpression(amdgpu_gfx940::v130, output_vec_len ); + case 131: return makeRegisterExpression(amdgpu_gfx940::v131, output_vec_len ); + case 132: return makeRegisterExpression(amdgpu_gfx940::v132, output_vec_len ); + case 133: return makeRegisterExpression(amdgpu_gfx940::v133, output_vec_len ); + case 134: return makeRegisterExpression(amdgpu_gfx940::v134, output_vec_len ); + case 135: return makeRegisterExpression(amdgpu_gfx940::v135, output_vec_len ); + case 136: return makeRegisterExpression(amdgpu_gfx940::v136, output_vec_len ); + case 137: return makeRegisterExpression(amdgpu_gfx940::v137, output_vec_len ); + case 138: return makeRegisterExpression(amdgpu_gfx940::v138, output_vec_len ); + case 139: return makeRegisterExpression(amdgpu_gfx940::v139, output_vec_len ); + case 140: return makeRegisterExpression(amdgpu_gfx940::v140, output_vec_len ); + case 141: return makeRegisterExpression(amdgpu_gfx940::v141, output_vec_len ); + case 142: return makeRegisterExpression(amdgpu_gfx940::v142, output_vec_len ); + case 143: return makeRegisterExpression(amdgpu_gfx940::v143, output_vec_len ); + case 144: return makeRegisterExpression(amdgpu_gfx940::v144, output_vec_len ); + case 145: return makeRegisterExpression(amdgpu_gfx940::v145, output_vec_len ); + case 146: return makeRegisterExpression(amdgpu_gfx940::v146, output_vec_len ); + case 147: return makeRegisterExpression(amdgpu_gfx940::v147, output_vec_len ); + case 148: return makeRegisterExpression(amdgpu_gfx940::v148, output_vec_len ); + case 149: return makeRegisterExpression(amdgpu_gfx940::v149, output_vec_len ); + case 150: return makeRegisterExpression(amdgpu_gfx940::v150, output_vec_len ); + case 151: return makeRegisterExpression(amdgpu_gfx940::v151, output_vec_len ); + case 152: return makeRegisterExpression(amdgpu_gfx940::v152, output_vec_len ); + case 153: return makeRegisterExpression(amdgpu_gfx940::v153, output_vec_len ); + case 154: return makeRegisterExpression(amdgpu_gfx940::v154, output_vec_len ); + case 155: return makeRegisterExpression(amdgpu_gfx940::v155, output_vec_len ); + case 156: return makeRegisterExpression(amdgpu_gfx940::v156, output_vec_len ); + case 157: return makeRegisterExpression(amdgpu_gfx940::v157, output_vec_len ); + case 158: return makeRegisterExpression(amdgpu_gfx940::v158, output_vec_len ); + case 159: return makeRegisterExpression(amdgpu_gfx940::v159, output_vec_len ); + case 160: return makeRegisterExpression(amdgpu_gfx940::v160, output_vec_len ); + case 161: return makeRegisterExpression(amdgpu_gfx940::v161, output_vec_len ); + case 162: return makeRegisterExpression(amdgpu_gfx940::v162, output_vec_len ); + case 163: return makeRegisterExpression(amdgpu_gfx940::v163, output_vec_len ); + case 164: return makeRegisterExpression(amdgpu_gfx940::v164, output_vec_len ); + case 165: return makeRegisterExpression(amdgpu_gfx940::v165, output_vec_len ); + case 166: return makeRegisterExpression(amdgpu_gfx940::v166, output_vec_len ); + case 167: return makeRegisterExpression(amdgpu_gfx940::v167, output_vec_len ); + case 168: return makeRegisterExpression(amdgpu_gfx940::v168, output_vec_len ); + case 169: return makeRegisterExpression(amdgpu_gfx940::v169, output_vec_len ); + case 170: return makeRegisterExpression(amdgpu_gfx940::v170, output_vec_len ); + case 171: return makeRegisterExpression(amdgpu_gfx940::v171, output_vec_len ); + case 172: return makeRegisterExpression(amdgpu_gfx940::v172, output_vec_len ); + case 173: return makeRegisterExpression(amdgpu_gfx940::v173, output_vec_len ); + case 174: return makeRegisterExpression(amdgpu_gfx940::v174, output_vec_len ); + case 175: return makeRegisterExpression(amdgpu_gfx940::v175, output_vec_len ); + case 176: return makeRegisterExpression(amdgpu_gfx940::v176, output_vec_len ); + case 177: return makeRegisterExpression(amdgpu_gfx940::v177, output_vec_len ); + case 178: return makeRegisterExpression(amdgpu_gfx940::v178, output_vec_len ); + case 179: return makeRegisterExpression(amdgpu_gfx940::v179, output_vec_len ); + case 180: return makeRegisterExpression(amdgpu_gfx940::v180, output_vec_len ); + case 181: return makeRegisterExpression(amdgpu_gfx940::v181, output_vec_len ); + case 182: return makeRegisterExpression(amdgpu_gfx940::v182, output_vec_len ); + case 183: return makeRegisterExpression(amdgpu_gfx940::v183, output_vec_len ); + case 184: return makeRegisterExpression(amdgpu_gfx940::v184, output_vec_len ); + case 185: return makeRegisterExpression(amdgpu_gfx940::v185, output_vec_len ); + case 186: return makeRegisterExpression(amdgpu_gfx940::v186, output_vec_len ); + case 187: return makeRegisterExpression(amdgpu_gfx940::v187, output_vec_len ); + case 188: return makeRegisterExpression(amdgpu_gfx940::v188, output_vec_len ); + case 189: return makeRegisterExpression(amdgpu_gfx940::v189, output_vec_len ); + case 190: return makeRegisterExpression(amdgpu_gfx940::v190, output_vec_len ); + case 191: return makeRegisterExpression(amdgpu_gfx940::v191, output_vec_len ); + case 192: return makeRegisterExpression(amdgpu_gfx940::v192, output_vec_len ); + case 193: return makeRegisterExpression(amdgpu_gfx940::v193, output_vec_len ); + case 194: return makeRegisterExpression(amdgpu_gfx940::v194, output_vec_len ); + case 195: return makeRegisterExpression(amdgpu_gfx940::v195, output_vec_len ); + case 196: return makeRegisterExpression(amdgpu_gfx940::v196, output_vec_len ); + case 197: return makeRegisterExpression(amdgpu_gfx940::v197, output_vec_len ); + case 198: return makeRegisterExpression(amdgpu_gfx940::v198, output_vec_len ); + case 199: return makeRegisterExpression(amdgpu_gfx940::v199, output_vec_len ); + case 200: return makeRegisterExpression(amdgpu_gfx940::v200, output_vec_len ); + case 201: return makeRegisterExpression(amdgpu_gfx940::v201, output_vec_len ); + case 202: return makeRegisterExpression(amdgpu_gfx940::v202, output_vec_len ); + case 203: return makeRegisterExpression(amdgpu_gfx940::v203, output_vec_len ); + case 204: return makeRegisterExpression(amdgpu_gfx940::v204, output_vec_len ); + case 205: return makeRegisterExpression(amdgpu_gfx940::v205, output_vec_len ); + case 206: return makeRegisterExpression(amdgpu_gfx940::v206, output_vec_len ); + case 207: return makeRegisterExpression(amdgpu_gfx940::v207, output_vec_len ); + case 208: return makeRegisterExpression(amdgpu_gfx940::v208, output_vec_len ); + case 209: return makeRegisterExpression(amdgpu_gfx940::v209, output_vec_len ); + case 210: return makeRegisterExpression(amdgpu_gfx940::v210, output_vec_len ); + case 211: return makeRegisterExpression(amdgpu_gfx940::v211, output_vec_len ); + case 212: return makeRegisterExpression(amdgpu_gfx940::v212, output_vec_len ); + case 213: return makeRegisterExpression(amdgpu_gfx940::v213, output_vec_len ); + case 214: return makeRegisterExpression(amdgpu_gfx940::v214, output_vec_len ); + case 215: return makeRegisterExpression(amdgpu_gfx940::v215, output_vec_len ); + case 216: return makeRegisterExpression(amdgpu_gfx940::v216, output_vec_len ); + case 217: return makeRegisterExpression(amdgpu_gfx940::v217, output_vec_len ); + case 218: return makeRegisterExpression(amdgpu_gfx940::v218, output_vec_len ); + case 219: return makeRegisterExpression(amdgpu_gfx940::v219, output_vec_len ); + case 220: return makeRegisterExpression(amdgpu_gfx940::v220, output_vec_len ); + case 221: return makeRegisterExpression(amdgpu_gfx940::v221, output_vec_len ); + case 222: return makeRegisterExpression(amdgpu_gfx940::v222, output_vec_len ); + case 223: return makeRegisterExpression(amdgpu_gfx940::v223, output_vec_len ); + case 224: return makeRegisterExpression(amdgpu_gfx940::v224, output_vec_len ); + case 225: return makeRegisterExpression(amdgpu_gfx940::v225, output_vec_len ); + case 226: return makeRegisterExpression(amdgpu_gfx940::v226, output_vec_len ); + case 227: return makeRegisterExpression(amdgpu_gfx940::v227, output_vec_len ); + case 228: return makeRegisterExpression(amdgpu_gfx940::v228, output_vec_len ); + case 229: return makeRegisterExpression(amdgpu_gfx940::v229, output_vec_len ); + case 230: return makeRegisterExpression(amdgpu_gfx940::v230, output_vec_len ); + case 231: return makeRegisterExpression(amdgpu_gfx940::v231, output_vec_len ); + case 232: return makeRegisterExpression(amdgpu_gfx940::v232, output_vec_len ); + case 233: return makeRegisterExpression(amdgpu_gfx940::v233, output_vec_len ); + case 234: return makeRegisterExpression(amdgpu_gfx940::v234, output_vec_len ); + case 235: return makeRegisterExpression(amdgpu_gfx940::v235, output_vec_len ); + case 236: return makeRegisterExpression(amdgpu_gfx940::v236, output_vec_len ); + case 237: return makeRegisterExpression(amdgpu_gfx940::v237, output_vec_len ); + case 238: return makeRegisterExpression(amdgpu_gfx940::v238, output_vec_len ); + case 239: return makeRegisterExpression(amdgpu_gfx940::v239, output_vec_len ); + case 240: return makeRegisterExpression(amdgpu_gfx940::v240, output_vec_len ); + case 241: return makeRegisterExpression(amdgpu_gfx940::v241, output_vec_len ); + case 242: return makeRegisterExpression(amdgpu_gfx940::v242, output_vec_len ); + case 243: return makeRegisterExpression(amdgpu_gfx940::v243, output_vec_len ); + case 244: return makeRegisterExpression(amdgpu_gfx940::v244, output_vec_len ); + case 245: return makeRegisterExpression(amdgpu_gfx940::v245, output_vec_len ); + case 246: return makeRegisterExpression(amdgpu_gfx940::v246, output_vec_len ); + case 247: return makeRegisterExpression(amdgpu_gfx940::v247, output_vec_len ); + case 248: return makeRegisterExpression(amdgpu_gfx940::v248, output_vec_len ); + case 249: return makeRegisterExpression(amdgpu_gfx940::v249, output_vec_len ); + case 250: return makeRegisterExpression(amdgpu_gfx940::v250, output_vec_len ); + case 251: return makeRegisterExpression(amdgpu_gfx940::v251, output_vec_len ); + case 252: return makeRegisterExpression(amdgpu_gfx940::v252, output_vec_len ); + case 253: return makeRegisterExpression(amdgpu_gfx940::v253, output_vec_len ); + case 254: return makeRegisterExpression(amdgpu_gfx940::v254, output_vec_len ); + case 255: return makeRegisterExpression(amdgpu_gfx940::v255, output_vec_len ); + default: return makeRegisterExpression(amdgpu_gfx940::invalid); + } + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx940::decodeOPR_VGPR_OR_ACCVGPR(uint64_t input, uint32_t output_vec_len) + { + switch (input) { + case 0: return makeRegisterExpression(amdgpu_gfx940::v0, output_vec_len ); + case 1: return makeRegisterExpression(amdgpu_gfx940::v1, output_vec_len ); + case 2: return makeRegisterExpression(amdgpu_gfx940::v2, output_vec_len ); + case 3: return makeRegisterExpression(amdgpu_gfx940::v3, output_vec_len ); + case 4: return makeRegisterExpression(amdgpu_gfx940::v4, output_vec_len ); + case 5: return makeRegisterExpression(amdgpu_gfx940::v5, output_vec_len ); + case 6: return makeRegisterExpression(amdgpu_gfx940::v6, output_vec_len ); + case 7: return makeRegisterExpression(amdgpu_gfx940::v7, output_vec_len ); + case 8: return makeRegisterExpression(amdgpu_gfx940::v8, output_vec_len ); + case 9: return makeRegisterExpression(amdgpu_gfx940::v9, output_vec_len ); + case 10: return makeRegisterExpression(amdgpu_gfx940::v10, output_vec_len ); + case 11: return makeRegisterExpression(amdgpu_gfx940::v11, output_vec_len ); + case 12: return makeRegisterExpression(amdgpu_gfx940::v12, output_vec_len ); + case 13: return makeRegisterExpression(amdgpu_gfx940::v13, output_vec_len ); + case 14: return makeRegisterExpression(amdgpu_gfx940::v14, output_vec_len ); + case 15: return makeRegisterExpression(amdgpu_gfx940::v15, output_vec_len ); + case 16: return makeRegisterExpression(amdgpu_gfx940::v16, output_vec_len ); + case 17: return makeRegisterExpression(amdgpu_gfx940::v17, output_vec_len ); + case 18: return makeRegisterExpression(amdgpu_gfx940::v18, output_vec_len ); + case 19: return makeRegisterExpression(amdgpu_gfx940::v19, output_vec_len ); + case 20: return makeRegisterExpression(amdgpu_gfx940::v20, output_vec_len ); + case 21: return makeRegisterExpression(amdgpu_gfx940::v21, output_vec_len ); + case 22: return makeRegisterExpression(amdgpu_gfx940::v22, output_vec_len ); + case 23: return makeRegisterExpression(amdgpu_gfx940::v23, output_vec_len ); + case 24: return makeRegisterExpression(amdgpu_gfx940::v24, output_vec_len ); + case 25: return makeRegisterExpression(amdgpu_gfx940::v25, output_vec_len ); + case 26: return makeRegisterExpression(amdgpu_gfx940::v26, output_vec_len ); + case 27: return makeRegisterExpression(amdgpu_gfx940::v27, output_vec_len ); + case 28: return makeRegisterExpression(amdgpu_gfx940::v28, output_vec_len ); + case 29: return makeRegisterExpression(amdgpu_gfx940::v29, output_vec_len ); + case 30: return makeRegisterExpression(amdgpu_gfx940::v30, output_vec_len ); + case 31: return makeRegisterExpression(amdgpu_gfx940::v31, output_vec_len ); + case 32: return makeRegisterExpression(amdgpu_gfx940::v32, output_vec_len ); + case 33: return makeRegisterExpression(amdgpu_gfx940::v33, output_vec_len ); + case 34: return makeRegisterExpression(amdgpu_gfx940::v34, output_vec_len ); + case 35: return makeRegisterExpression(amdgpu_gfx940::v35, output_vec_len ); + case 36: return makeRegisterExpression(amdgpu_gfx940::v36, output_vec_len ); + case 37: return makeRegisterExpression(amdgpu_gfx940::v37, output_vec_len ); + case 38: return makeRegisterExpression(amdgpu_gfx940::v38, output_vec_len ); + case 39: return makeRegisterExpression(amdgpu_gfx940::v39, output_vec_len ); + case 40: return makeRegisterExpression(amdgpu_gfx940::v40, output_vec_len ); + case 41: return makeRegisterExpression(amdgpu_gfx940::v41, output_vec_len ); + case 42: return makeRegisterExpression(amdgpu_gfx940::v42, output_vec_len ); + case 43: return makeRegisterExpression(amdgpu_gfx940::v43, output_vec_len ); + case 44: return makeRegisterExpression(amdgpu_gfx940::v44, output_vec_len ); + case 45: return makeRegisterExpression(amdgpu_gfx940::v45, output_vec_len ); + case 46: return makeRegisterExpression(amdgpu_gfx940::v46, output_vec_len ); + case 47: return makeRegisterExpression(amdgpu_gfx940::v47, output_vec_len ); + case 48: return makeRegisterExpression(amdgpu_gfx940::v48, output_vec_len ); + case 49: return makeRegisterExpression(amdgpu_gfx940::v49, output_vec_len ); + case 50: return makeRegisterExpression(amdgpu_gfx940::v50, output_vec_len ); + case 51: return makeRegisterExpression(amdgpu_gfx940::v51, output_vec_len ); + case 52: return makeRegisterExpression(amdgpu_gfx940::v52, output_vec_len ); + case 53: return makeRegisterExpression(amdgpu_gfx940::v53, output_vec_len ); + case 54: return makeRegisterExpression(amdgpu_gfx940::v54, output_vec_len ); + case 55: return makeRegisterExpression(amdgpu_gfx940::v55, output_vec_len ); + case 56: return makeRegisterExpression(amdgpu_gfx940::v56, output_vec_len ); + case 57: return makeRegisterExpression(amdgpu_gfx940::v57, output_vec_len ); + case 58: return makeRegisterExpression(amdgpu_gfx940::v58, output_vec_len ); + case 59: return makeRegisterExpression(amdgpu_gfx940::v59, output_vec_len ); + case 60: return makeRegisterExpression(amdgpu_gfx940::v60, output_vec_len ); + case 61: return makeRegisterExpression(amdgpu_gfx940::v61, output_vec_len ); + case 62: return makeRegisterExpression(amdgpu_gfx940::v62, output_vec_len ); + case 63: return makeRegisterExpression(amdgpu_gfx940::v63, output_vec_len ); + case 64: return makeRegisterExpression(amdgpu_gfx940::v64, output_vec_len ); + case 65: return makeRegisterExpression(amdgpu_gfx940::v65, output_vec_len ); + case 66: return makeRegisterExpression(amdgpu_gfx940::v66, output_vec_len ); + case 67: return makeRegisterExpression(amdgpu_gfx940::v67, output_vec_len ); + case 68: return makeRegisterExpression(amdgpu_gfx940::v68, output_vec_len ); + case 69: return makeRegisterExpression(amdgpu_gfx940::v69, output_vec_len ); + case 70: return makeRegisterExpression(amdgpu_gfx940::v70, output_vec_len ); + case 71: return makeRegisterExpression(amdgpu_gfx940::v71, output_vec_len ); + case 72: return makeRegisterExpression(amdgpu_gfx940::v72, output_vec_len ); + case 73: return makeRegisterExpression(amdgpu_gfx940::v73, output_vec_len ); + case 74: return makeRegisterExpression(amdgpu_gfx940::v74, output_vec_len ); + case 75: return makeRegisterExpression(amdgpu_gfx940::v75, output_vec_len ); + case 76: return makeRegisterExpression(amdgpu_gfx940::v76, output_vec_len ); + case 77: return makeRegisterExpression(amdgpu_gfx940::v77, output_vec_len ); + case 78: return makeRegisterExpression(amdgpu_gfx940::v78, output_vec_len ); + case 79: return makeRegisterExpression(amdgpu_gfx940::v79, output_vec_len ); + case 80: return makeRegisterExpression(amdgpu_gfx940::v80, output_vec_len ); + case 81: return makeRegisterExpression(amdgpu_gfx940::v81, output_vec_len ); + case 82: return makeRegisterExpression(amdgpu_gfx940::v82, output_vec_len ); + case 83: return makeRegisterExpression(amdgpu_gfx940::v83, output_vec_len ); + case 84: return makeRegisterExpression(amdgpu_gfx940::v84, output_vec_len ); + case 85: return makeRegisterExpression(amdgpu_gfx940::v85, output_vec_len ); + case 86: return makeRegisterExpression(amdgpu_gfx940::v86, output_vec_len ); + case 87: return makeRegisterExpression(amdgpu_gfx940::v87, output_vec_len ); + case 88: return makeRegisterExpression(amdgpu_gfx940::v88, output_vec_len ); + case 89: return makeRegisterExpression(amdgpu_gfx940::v89, output_vec_len ); + case 90: return makeRegisterExpression(amdgpu_gfx940::v90, output_vec_len ); + case 91: return makeRegisterExpression(amdgpu_gfx940::v91, output_vec_len ); + case 92: return makeRegisterExpression(amdgpu_gfx940::v92, output_vec_len ); + case 93: return makeRegisterExpression(amdgpu_gfx940::v93, output_vec_len ); + case 94: return makeRegisterExpression(amdgpu_gfx940::v94, output_vec_len ); + case 95: return makeRegisterExpression(amdgpu_gfx940::v95, output_vec_len ); + case 96: return makeRegisterExpression(amdgpu_gfx940::v96, output_vec_len ); + case 97: return makeRegisterExpression(amdgpu_gfx940::v97, output_vec_len ); + case 98: return makeRegisterExpression(amdgpu_gfx940::v98, output_vec_len ); + case 99: return makeRegisterExpression(amdgpu_gfx940::v99, output_vec_len ); + case 100: return makeRegisterExpression(amdgpu_gfx940::v100, output_vec_len ); + case 101: return makeRegisterExpression(amdgpu_gfx940::v101, output_vec_len ); + case 102: return makeRegisterExpression(amdgpu_gfx940::v102, output_vec_len ); + case 103: return makeRegisterExpression(amdgpu_gfx940::v103, output_vec_len ); + case 104: return makeRegisterExpression(amdgpu_gfx940::v104, output_vec_len ); + case 105: return makeRegisterExpression(amdgpu_gfx940::v105, output_vec_len ); + case 106: return makeRegisterExpression(amdgpu_gfx940::v106, output_vec_len ); + case 107: return makeRegisterExpression(amdgpu_gfx940::v107, output_vec_len ); + case 108: return makeRegisterExpression(amdgpu_gfx940::v108, output_vec_len ); + case 109: return makeRegisterExpression(amdgpu_gfx940::v109, output_vec_len ); + case 110: return makeRegisterExpression(amdgpu_gfx940::v110, output_vec_len ); + case 111: return makeRegisterExpression(amdgpu_gfx940::v111, output_vec_len ); + case 112: return makeRegisterExpression(amdgpu_gfx940::v112, output_vec_len ); + case 113: return makeRegisterExpression(amdgpu_gfx940::v113, output_vec_len ); + case 114: return makeRegisterExpression(amdgpu_gfx940::v114, output_vec_len ); + case 115: return makeRegisterExpression(amdgpu_gfx940::v115, output_vec_len ); + case 116: return makeRegisterExpression(amdgpu_gfx940::v116, output_vec_len ); + case 117: return makeRegisterExpression(amdgpu_gfx940::v117, output_vec_len ); + case 118: return makeRegisterExpression(amdgpu_gfx940::v118, output_vec_len ); + case 119: return makeRegisterExpression(amdgpu_gfx940::v119, output_vec_len ); + case 120: return makeRegisterExpression(amdgpu_gfx940::v120, output_vec_len ); + case 121: return makeRegisterExpression(amdgpu_gfx940::v121, output_vec_len ); + case 122: return makeRegisterExpression(amdgpu_gfx940::v122, output_vec_len ); + case 123: return makeRegisterExpression(amdgpu_gfx940::v123, output_vec_len ); + case 124: return makeRegisterExpression(amdgpu_gfx940::v124, output_vec_len ); + case 125: return makeRegisterExpression(amdgpu_gfx940::v125, output_vec_len ); + case 126: return makeRegisterExpression(amdgpu_gfx940::v126, output_vec_len ); + case 127: return makeRegisterExpression(amdgpu_gfx940::v127, output_vec_len ); + case 128: return makeRegisterExpression(amdgpu_gfx940::v128, output_vec_len ); + case 129: return makeRegisterExpression(amdgpu_gfx940::v129, output_vec_len ); + case 130: return makeRegisterExpression(amdgpu_gfx940::v130, output_vec_len ); + case 131: return makeRegisterExpression(amdgpu_gfx940::v131, output_vec_len ); + case 132: return makeRegisterExpression(amdgpu_gfx940::v132, output_vec_len ); + case 133: return makeRegisterExpression(amdgpu_gfx940::v133, output_vec_len ); + case 134: return makeRegisterExpression(amdgpu_gfx940::v134, output_vec_len ); + case 135: return makeRegisterExpression(amdgpu_gfx940::v135, output_vec_len ); + case 136: return makeRegisterExpression(amdgpu_gfx940::v136, output_vec_len ); + case 137: return makeRegisterExpression(amdgpu_gfx940::v137, output_vec_len ); + case 138: return makeRegisterExpression(amdgpu_gfx940::v138, output_vec_len ); + case 139: return makeRegisterExpression(amdgpu_gfx940::v139, output_vec_len ); + case 140: return makeRegisterExpression(amdgpu_gfx940::v140, output_vec_len ); + case 141: return makeRegisterExpression(amdgpu_gfx940::v141, output_vec_len ); + case 142: return makeRegisterExpression(amdgpu_gfx940::v142, output_vec_len ); + case 143: return makeRegisterExpression(amdgpu_gfx940::v143, output_vec_len ); + case 144: return makeRegisterExpression(amdgpu_gfx940::v144, output_vec_len ); + case 145: return makeRegisterExpression(amdgpu_gfx940::v145, output_vec_len ); + case 146: return makeRegisterExpression(amdgpu_gfx940::v146, output_vec_len ); + case 147: return makeRegisterExpression(amdgpu_gfx940::v147, output_vec_len ); + case 148: return makeRegisterExpression(amdgpu_gfx940::v148, output_vec_len ); + case 149: return makeRegisterExpression(amdgpu_gfx940::v149, output_vec_len ); + case 150: return makeRegisterExpression(amdgpu_gfx940::v150, output_vec_len ); + case 151: return makeRegisterExpression(amdgpu_gfx940::v151, output_vec_len ); + case 152: return makeRegisterExpression(amdgpu_gfx940::v152, output_vec_len ); + case 153: return makeRegisterExpression(amdgpu_gfx940::v153, output_vec_len ); + case 154: return makeRegisterExpression(amdgpu_gfx940::v154, output_vec_len ); + case 155: return makeRegisterExpression(amdgpu_gfx940::v155, output_vec_len ); + case 156: return makeRegisterExpression(amdgpu_gfx940::v156, output_vec_len ); + case 157: return makeRegisterExpression(amdgpu_gfx940::v157, output_vec_len ); + case 158: return makeRegisterExpression(amdgpu_gfx940::v158, output_vec_len ); + case 159: return makeRegisterExpression(amdgpu_gfx940::v159, output_vec_len ); + case 160: return makeRegisterExpression(amdgpu_gfx940::v160, output_vec_len ); + case 161: return makeRegisterExpression(amdgpu_gfx940::v161, output_vec_len ); + case 162: return makeRegisterExpression(amdgpu_gfx940::v162, output_vec_len ); + case 163: return makeRegisterExpression(amdgpu_gfx940::v163, output_vec_len ); + case 164: return makeRegisterExpression(amdgpu_gfx940::v164, output_vec_len ); + case 165: return makeRegisterExpression(amdgpu_gfx940::v165, output_vec_len ); + case 166: return makeRegisterExpression(amdgpu_gfx940::v166, output_vec_len ); + case 167: return makeRegisterExpression(amdgpu_gfx940::v167, output_vec_len ); + case 168: return makeRegisterExpression(amdgpu_gfx940::v168, output_vec_len ); + case 169: return makeRegisterExpression(amdgpu_gfx940::v169, output_vec_len ); + case 170: return makeRegisterExpression(amdgpu_gfx940::v170, output_vec_len ); + case 171: return makeRegisterExpression(amdgpu_gfx940::v171, output_vec_len ); + case 172: return makeRegisterExpression(amdgpu_gfx940::v172, output_vec_len ); + case 173: return makeRegisterExpression(amdgpu_gfx940::v173, output_vec_len ); + case 174: return makeRegisterExpression(amdgpu_gfx940::v174, output_vec_len ); + case 175: return makeRegisterExpression(amdgpu_gfx940::v175, output_vec_len ); + case 176: return makeRegisterExpression(amdgpu_gfx940::v176, output_vec_len ); + case 177: return makeRegisterExpression(amdgpu_gfx940::v177, output_vec_len ); + case 178: return makeRegisterExpression(amdgpu_gfx940::v178, output_vec_len ); + case 179: return makeRegisterExpression(amdgpu_gfx940::v179, output_vec_len ); + case 180: return makeRegisterExpression(amdgpu_gfx940::v180, output_vec_len ); + case 181: return makeRegisterExpression(amdgpu_gfx940::v181, output_vec_len ); + case 182: return makeRegisterExpression(amdgpu_gfx940::v182, output_vec_len ); + case 183: return makeRegisterExpression(amdgpu_gfx940::v183, output_vec_len ); + case 184: return makeRegisterExpression(amdgpu_gfx940::v184, output_vec_len ); + case 185: return makeRegisterExpression(amdgpu_gfx940::v185, output_vec_len ); + case 186: return makeRegisterExpression(amdgpu_gfx940::v186, output_vec_len ); + case 187: return makeRegisterExpression(amdgpu_gfx940::v187, output_vec_len ); + case 188: return makeRegisterExpression(amdgpu_gfx940::v188, output_vec_len ); + case 189: return makeRegisterExpression(amdgpu_gfx940::v189, output_vec_len ); + case 190: return makeRegisterExpression(amdgpu_gfx940::v190, output_vec_len ); + case 191: return makeRegisterExpression(amdgpu_gfx940::v191, output_vec_len ); + case 192: return makeRegisterExpression(amdgpu_gfx940::v192, output_vec_len ); + case 193: return makeRegisterExpression(amdgpu_gfx940::v193, output_vec_len ); + case 194: return makeRegisterExpression(amdgpu_gfx940::v194, output_vec_len ); + case 195: return makeRegisterExpression(amdgpu_gfx940::v195, output_vec_len ); + case 196: return makeRegisterExpression(amdgpu_gfx940::v196, output_vec_len ); + case 197: return makeRegisterExpression(amdgpu_gfx940::v197, output_vec_len ); + case 198: return makeRegisterExpression(amdgpu_gfx940::v198, output_vec_len ); + case 199: return makeRegisterExpression(amdgpu_gfx940::v199, output_vec_len ); + case 200: return makeRegisterExpression(amdgpu_gfx940::v200, output_vec_len ); + case 201: return makeRegisterExpression(amdgpu_gfx940::v201, output_vec_len ); + case 202: return makeRegisterExpression(amdgpu_gfx940::v202, output_vec_len ); + case 203: return makeRegisterExpression(amdgpu_gfx940::v203, output_vec_len ); + case 204: return makeRegisterExpression(amdgpu_gfx940::v204, output_vec_len ); + case 205: return makeRegisterExpression(amdgpu_gfx940::v205, output_vec_len ); + case 206: return makeRegisterExpression(amdgpu_gfx940::v206, output_vec_len ); + case 207: return makeRegisterExpression(amdgpu_gfx940::v207, output_vec_len ); + case 208: return makeRegisterExpression(amdgpu_gfx940::v208, output_vec_len ); + case 209: return makeRegisterExpression(amdgpu_gfx940::v209, output_vec_len ); + case 210: return makeRegisterExpression(amdgpu_gfx940::v210, output_vec_len ); + case 211: return makeRegisterExpression(amdgpu_gfx940::v211, output_vec_len ); + case 212: return makeRegisterExpression(amdgpu_gfx940::v212, output_vec_len ); + case 213: return makeRegisterExpression(amdgpu_gfx940::v213, output_vec_len ); + case 214: return makeRegisterExpression(amdgpu_gfx940::v214, output_vec_len ); + case 215: return makeRegisterExpression(amdgpu_gfx940::v215, output_vec_len ); + case 216: return makeRegisterExpression(amdgpu_gfx940::v216, output_vec_len ); + case 217: return makeRegisterExpression(amdgpu_gfx940::v217, output_vec_len ); + case 218: return makeRegisterExpression(amdgpu_gfx940::v218, output_vec_len ); + case 219: return makeRegisterExpression(amdgpu_gfx940::v219, output_vec_len ); + case 220: return makeRegisterExpression(amdgpu_gfx940::v220, output_vec_len ); + case 221: return makeRegisterExpression(amdgpu_gfx940::v221, output_vec_len ); + case 222: return makeRegisterExpression(amdgpu_gfx940::v222, output_vec_len ); + case 223: return makeRegisterExpression(amdgpu_gfx940::v223, output_vec_len ); + case 224: return makeRegisterExpression(amdgpu_gfx940::v224, output_vec_len ); + case 225: return makeRegisterExpression(amdgpu_gfx940::v225, output_vec_len ); + case 226: return makeRegisterExpression(amdgpu_gfx940::v226, output_vec_len ); + case 227: return makeRegisterExpression(amdgpu_gfx940::v227, output_vec_len ); + case 228: return makeRegisterExpression(amdgpu_gfx940::v228, output_vec_len ); + case 229: return makeRegisterExpression(amdgpu_gfx940::v229, output_vec_len ); + case 230: return makeRegisterExpression(amdgpu_gfx940::v230, output_vec_len ); + case 231: return makeRegisterExpression(amdgpu_gfx940::v231, output_vec_len ); + case 232: return makeRegisterExpression(amdgpu_gfx940::v232, output_vec_len ); + case 233: return makeRegisterExpression(amdgpu_gfx940::v233, output_vec_len ); + case 234: return makeRegisterExpression(amdgpu_gfx940::v234, output_vec_len ); + case 235: return makeRegisterExpression(amdgpu_gfx940::v235, output_vec_len ); + case 236: return makeRegisterExpression(amdgpu_gfx940::v236, output_vec_len ); + case 237: return makeRegisterExpression(amdgpu_gfx940::v237, output_vec_len ); + case 238: return makeRegisterExpression(amdgpu_gfx940::v238, output_vec_len ); + case 239: return makeRegisterExpression(amdgpu_gfx940::v239, output_vec_len ); + case 240: return makeRegisterExpression(amdgpu_gfx940::v240, output_vec_len ); + case 241: return makeRegisterExpression(amdgpu_gfx940::v241, output_vec_len ); + case 242: return makeRegisterExpression(amdgpu_gfx940::v242, output_vec_len ); + case 243: return makeRegisterExpression(amdgpu_gfx940::v243, output_vec_len ); + case 244: return makeRegisterExpression(amdgpu_gfx940::v244, output_vec_len ); + case 245: return makeRegisterExpression(amdgpu_gfx940::v245, output_vec_len ); + case 246: return makeRegisterExpression(amdgpu_gfx940::v246, output_vec_len ); + case 247: return makeRegisterExpression(amdgpu_gfx940::v247, output_vec_len ); + case 248: return makeRegisterExpression(amdgpu_gfx940::v248, output_vec_len ); + case 249: return makeRegisterExpression(amdgpu_gfx940::v249, output_vec_len ); + case 250: return makeRegisterExpression(amdgpu_gfx940::v250, output_vec_len ); + case 251: return makeRegisterExpression(amdgpu_gfx940::v251, output_vec_len ); + case 252: return makeRegisterExpression(amdgpu_gfx940::v252, output_vec_len ); + case 253: return makeRegisterExpression(amdgpu_gfx940::v253, output_vec_len ); + case 254: return makeRegisterExpression(amdgpu_gfx940::v254, output_vec_len ); + case 255: return makeRegisterExpression(amdgpu_gfx940::v255, output_vec_len ); + case 512: return makeRegisterExpression(amdgpu_gfx940::acc0, output_vec_len ); + case 513: return makeRegisterExpression(amdgpu_gfx940::acc1, output_vec_len ); + case 514: return makeRegisterExpression(amdgpu_gfx940::acc2, output_vec_len ); + case 515: return makeRegisterExpression(amdgpu_gfx940::acc3, output_vec_len ); + case 516: return makeRegisterExpression(amdgpu_gfx940::acc4, output_vec_len ); + case 517: return makeRegisterExpression(amdgpu_gfx940::acc5, output_vec_len ); + case 518: return makeRegisterExpression(amdgpu_gfx940::acc6, output_vec_len ); + case 519: return makeRegisterExpression(amdgpu_gfx940::acc7, output_vec_len ); + case 520: return makeRegisterExpression(amdgpu_gfx940::acc8, output_vec_len ); + case 521: return makeRegisterExpression(amdgpu_gfx940::acc9, output_vec_len ); + case 522: return makeRegisterExpression(amdgpu_gfx940::acc10, output_vec_len ); + case 523: return makeRegisterExpression(amdgpu_gfx940::acc11, output_vec_len ); + case 524: return makeRegisterExpression(amdgpu_gfx940::acc12, output_vec_len ); + case 525: return makeRegisterExpression(amdgpu_gfx940::acc13, output_vec_len ); + case 526: return makeRegisterExpression(amdgpu_gfx940::acc14, output_vec_len ); + case 527: return makeRegisterExpression(amdgpu_gfx940::acc15, output_vec_len ); + case 528: return makeRegisterExpression(amdgpu_gfx940::acc16, output_vec_len ); + case 529: return makeRegisterExpression(amdgpu_gfx940::acc17, output_vec_len ); + case 530: return makeRegisterExpression(amdgpu_gfx940::acc18, output_vec_len ); + case 531: return makeRegisterExpression(amdgpu_gfx940::acc19, output_vec_len ); + case 532: return makeRegisterExpression(amdgpu_gfx940::acc20, output_vec_len ); + case 533: return makeRegisterExpression(amdgpu_gfx940::acc21, output_vec_len ); + case 534: return makeRegisterExpression(amdgpu_gfx940::acc22, output_vec_len ); + case 535: return makeRegisterExpression(amdgpu_gfx940::acc23, output_vec_len ); + case 536: return makeRegisterExpression(amdgpu_gfx940::acc24, output_vec_len ); + case 537: return makeRegisterExpression(amdgpu_gfx940::acc25, output_vec_len ); + case 538: return makeRegisterExpression(amdgpu_gfx940::acc26, output_vec_len ); + case 539: return makeRegisterExpression(amdgpu_gfx940::acc27, output_vec_len ); + case 540: return makeRegisterExpression(amdgpu_gfx940::acc28, output_vec_len ); + case 541: return makeRegisterExpression(amdgpu_gfx940::acc29, output_vec_len ); + case 542: return makeRegisterExpression(amdgpu_gfx940::acc30, output_vec_len ); + case 543: return makeRegisterExpression(amdgpu_gfx940::acc31, output_vec_len ); + case 544: return makeRegisterExpression(amdgpu_gfx940::acc32, output_vec_len ); + case 545: return makeRegisterExpression(amdgpu_gfx940::acc33, output_vec_len ); + case 546: return makeRegisterExpression(amdgpu_gfx940::acc34, output_vec_len ); + case 547: return makeRegisterExpression(amdgpu_gfx940::acc35, output_vec_len ); + case 548: return makeRegisterExpression(amdgpu_gfx940::acc36, output_vec_len ); + case 549: return makeRegisterExpression(amdgpu_gfx940::acc37, output_vec_len ); + case 550: return makeRegisterExpression(amdgpu_gfx940::acc38, output_vec_len ); + case 551: return makeRegisterExpression(amdgpu_gfx940::acc39, output_vec_len ); + case 552: return makeRegisterExpression(amdgpu_gfx940::acc40, output_vec_len ); + case 553: return makeRegisterExpression(amdgpu_gfx940::acc41, output_vec_len ); + case 554: return makeRegisterExpression(amdgpu_gfx940::acc42, output_vec_len ); + case 555: return makeRegisterExpression(amdgpu_gfx940::acc43, output_vec_len ); + case 556: return makeRegisterExpression(amdgpu_gfx940::acc44, output_vec_len ); + case 557: return makeRegisterExpression(amdgpu_gfx940::acc45, output_vec_len ); + case 558: return makeRegisterExpression(amdgpu_gfx940::acc46, output_vec_len ); + case 559: return makeRegisterExpression(amdgpu_gfx940::acc47, output_vec_len ); + case 560: return makeRegisterExpression(amdgpu_gfx940::acc48, output_vec_len ); + case 561: return makeRegisterExpression(amdgpu_gfx940::acc49, output_vec_len ); + case 562: return makeRegisterExpression(amdgpu_gfx940::acc50, output_vec_len ); + case 563: return makeRegisterExpression(amdgpu_gfx940::acc51, output_vec_len ); + case 564: return makeRegisterExpression(amdgpu_gfx940::acc52, output_vec_len ); + case 565: return makeRegisterExpression(amdgpu_gfx940::acc53, output_vec_len ); + case 566: return makeRegisterExpression(amdgpu_gfx940::acc54, output_vec_len ); + case 567: return makeRegisterExpression(amdgpu_gfx940::acc55, output_vec_len ); + case 568: return makeRegisterExpression(amdgpu_gfx940::acc56, output_vec_len ); + case 569: return makeRegisterExpression(amdgpu_gfx940::acc57, output_vec_len ); + case 570: return makeRegisterExpression(amdgpu_gfx940::acc58, output_vec_len ); + case 571: return makeRegisterExpression(amdgpu_gfx940::acc59, output_vec_len ); + case 572: return makeRegisterExpression(amdgpu_gfx940::acc60, output_vec_len ); + case 573: return makeRegisterExpression(amdgpu_gfx940::acc61, output_vec_len ); + case 574: return makeRegisterExpression(amdgpu_gfx940::acc62, output_vec_len ); + case 575: return makeRegisterExpression(amdgpu_gfx940::acc63, output_vec_len ); + case 576: return makeRegisterExpression(amdgpu_gfx940::acc64, output_vec_len ); + case 577: return makeRegisterExpression(amdgpu_gfx940::acc65, output_vec_len ); + case 578: return makeRegisterExpression(amdgpu_gfx940::acc66, output_vec_len ); + case 579: return makeRegisterExpression(amdgpu_gfx940::acc67, output_vec_len ); + case 580: return makeRegisterExpression(amdgpu_gfx940::acc68, output_vec_len ); + case 581: return makeRegisterExpression(amdgpu_gfx940::acc69, output_vec_len ); + case 582: return makeRegisterExpression(amdgpu_gfx940::acc70, output_vec_len ); + case 583: return makeRegisterExpression(amdgpu_gfx940::acc71, output_vec_len ); + case 584: return makeRegisterExpression(amdgpu_gfx940::acc72, output_vec_len ); + case 585: return makeRegisterExpression(amdgpu_gfx940::acc73, output_vec_len ); + case 586: return makeRegisterExpression(amdgpu_gfx940::acc74, output_vec_len ); + case 587: return makeRegisterExpression(amdgpu_gfx940::acc75, output_vec_len ); + case 588: return makeRegisterExpression(amdgpu_gfx940::acc76, output_vec_len ); + case 589: return makeRegisterExpression(amdgpu_gfx940::acc77, output_vec_len ); + case 590: return makeRegisterExpression(amdgpu_gfx940::acc78, output_vec_len ); + case 591: return makeRegisterExpression(amdgpu_gfx940::acc79, output_vec_len ); + case 592: return makeRegisterExpression(amdgpu_gfx940::acc80, output_vec_len ); + case 593: return makeRegisterExpression(amdgpu_gfx940::acc81, output_vec_len ); + case 594: return makeRegisterExpression(amdgpu_gfx940::acc82, output_vec_len ); + case 595: return makeRegisterExpression(amdgpu_gfx940::acc83, output_vec_len ); + case 596: return makeRegisterExpression(amdgpu_gfx940::acc84, output_vec_len ); + case 597: return makeRegisterExpression(amdgpu_gfx940::acc85, output_vec_len ); + case 598: return makeRegisterExpression(amdgpu_gfx940::acc86, output_vec_len ); + case 599: return makeRegisterExpression(amdgpu_gfx940::acc87, output_vec_len ); + case 600: return makeRegisterExpression(amdgpu_gfx940::acc88, output_vec_len ); + case 601: return makeRegisterExpression(amdgpu_gfx940::acc89, output_vec_len ); + case 602: return makeRegisterExpression(amdgpu_gfx940::acc90, output_vec_len ); + case 603: return makeRegisterExpression(amdgpu_gfx940::acc91, output_vec_len ); + case 604: return makeRegisterExpression(amdgpu_gfx940::acc92, output_vec_len ); + case 605: return makeRegisterExpression(amdgpu_gfx940::acc93, output_vec_len ); + case 606: return makeRegisterExpression(amdgpu_gfx940::acc94, output_vec_len ); + case 607: return makeRegisterExpression(amdgpu_gfx940::acc95, output_vec_len ); + case 608: return makeRegisterExpression(amdgpu_gfx940::acc96, output_vec_len ); + case 609: return makeRegisterExpression(amdgpu_gfx940::acc97, output_vec_len ); + case 610: return makeRegisterExpression(amdgpu_gfx940::acc98, output_vec_len ); + case 611: return makeRegisterExpression(amdgpu_gfx940::acc99, output_vec_len ); + case 612: return makeRegisterExpression(amdgpu_gfx940::acc100, output_vec_len ); + case 613: return makeRegisterExpression(amdgpu_gfx940::acc101, output_vec_len ); + case 614: return makeRegisterExpression(amdgpu_gfx940::acc102, output_vec_len ); + case 615: return makeRegisterExpression(amdgpu_gfx940::acc103, output_vec_len ); + case 616: return makeRegisterExpression(amdgpu_gfx940::acc104, output_vec_len ); + case 617: return makeRegisterExpression(amdgpu_gfx940::acc105, output_vec_len ); + case 618: return makeRegisterExpression(amdgpu_gfx940::acc106, output_vec_len ); + case 619: return makeRegisterExpression(amdgpu_gfx940::acc107, output_vec_len ); + case 620: return makeRegisterExpression(amdgpu_gfx940::acc108, output_vec_len ); + case 621: return makeRegisterExpression(amdgpu_gfx940::acc109, output_vec_len ); + case 622: return makeRegisterExpression(amdgpu_gfx940::acc110, output_vec_len ); + case 623: return makeRegisterExpression(amdgpu_gfx940::acc111, output_vec_len ); + case 624: return makeRegisterExpression(amdgpu_gfx940::acc112, output_vec_len ); + case 625: return makeRegisterExpression(amdgpu_gfx940::acc113, output_vec_len ); + case 626: return makeRegisterExpression(amdgpu_gfx940::acc114, output_vec_len ); + case 627: return makeRegisterExpression(amdgpu_gfx940::acc115, output_vec_len ); + case 628: return makeRegisterExpression(amdgpu_gfx940::acc116, output_vec_len ); + case 629: return makeRegisterExpression(amdgpu_gfx940::acc117, output_vec_len ); + case 630: return makeRegisterExpression(amdgpu_gfx940::acc118, output_vec_len ); + case 631: return makeRegisterExpression(amdgpu_gfx940::acc119, output_vec_len ); + case 632: return makeRegisterExpression(amdgpu_gfx940::acc120, output_vec_len ); + case 633: return makeRegisterExpression(amdgpu_gfx940::acc121, output_vec_len ); + case 634: return makeRegisterExpression(amdgpu_gfx940::acc122, output_vec_len ); + case 635: return makeRegisterExpression(amdgpu_gfx940::acc123, output_vec_len ); + case 636: return makeRegisterExpression(amdgpu_gfx940::acc124, output_vec_len ); + case 637: return makeRegisterExpression(amdgpu_gfx940::acc125, output_vec_len ); + case 638: return makeRegisterExpression(amdgpu_gfx940::acc126, output_vec_len ); + case 639: return makeRegisterExpression(amdgpu_gfx940::acc127, output_vec_len ); + case 640: return makeRegisterExpression(amdgpu_gfx940::acc128, output_vec_len ); + case 641: return makeRegisterExpression(amdgpu_gfx940::acc129, output_vec_len ); + case 642: return makeRegisterExpression(amdgpu_gfx940::acc130, output_vec_len ); + case 643: return makeRegisterExpression(amdgpu_gfx940::acc131, output_vec_len ); + case 644: return makeRegisterExpression(amdgpu_gfx940::acc132, output_vec_len ); + case 645: return makeRegisterExpression(amdgpu_gfx940::acc133, output_vec_len ); + case 646: return makeRegisterExpression(amdgpu_gfx940::acc134, output_vec_len ); + case 647: return makeRegisterExpression(amdgpu_gfx940::acc135, output_vec_len ); + case 648: return makeRegisterExpression(amdgpu_gfx940::acc136, output_vec_len ); + case 649: return makeRegisterExpression(amdgpu_gfx940::acc137, output_vec_len ); + case 650: return makeRegisterExpression(amdgpu_gfx940::acc138, output_vec_len ); + case 651: return makeRegisterExpression(amdgpu_gfx940::acc139, output_vec_len ); + case 652: return makeRegisterExpression(amdgpu_gfx940::acc140, output_vec_len ); + case 653: return makeRegisterExpression(amdgpu_gfx940::acc141, output_vec_len ); + case 654: return makeRegisterExpression(amdgpu_gfx940::acc142, output_vec_len ); + case 655: return makeRegisterExpression(amdgpu_gfx940::acc143, output_vec_len ); + case 656: return makeRegisterExpression(amdgpu_gfx940::acc144, output_vec_len ); + case 657: return makeRegisterExpression(amdgpu_gfx940::acc145, output_vec_len ); + case 658: return makeRegisterExpression(amdgpu_gfx940::acc146, output_vec_len ); + case 659: return makeRegisterExpression(amdgpu_gfx940::acc147, output_vec_len ); + case 660: return makeRegisterExpression(amdgpu_gfx940::acc148, output_vec_len ); + case 661: return makeRegisterExpression(amdgpu_gfx940::acc149, output_vec_len ); + case 662: return makeRegisterExpression(amdgpu_gfx940::acc150, output_vec_len ); + case 663: return makeRegisterExpression(amdgpu_gfx940::acc151, output_vec_len ); + case 664: return makeRegisterExpression(amdgpu_gfx940::acc152, output_vec_len ); + case 665: return makeRegisterExpression(amdgpu_gfx940::acc153, output_vec_len ); + case 666: return makeRegisterExpression(amdgpu_gfx940::acc154, output_vec_len ); + case 667: return makeRegisterExpression(amdgpu_gfx940::acc155, output_vec_len ); + case 668: return makeRegisterExpression(amdgpu_gfx940::acc156, output_vec_len ); + case 669: return makeRegisterExpression(amdgpu_gfx940::acc157, output_vec_len ); + case 670: return makeRegisterExpression(amdgpu_gfx940::acc158, output_vec_len ); + case 671: return makeRegisterExpression(amdgpu_gfx940::acc159, output_vec_len ); + case 672: return makeRegisterExpression(amdgpu_gfx940::acc160, output_vec_len ); + case 673: return makeRegisterExpression(amdgpu_gfx940::acc161, output_vec_len ); + case 674: return makeRegisterExpression(amdgpu_gfx940::acc162, output_vec_len ); + case 675: return makeRegisterExpression(amdgpu_gfx940::acc163, output_vec_len ); + case 676: return makeRegisterExpression(amdgpu_gfx940::acc164, output_vec_len ); + case 677: return makeRegisterExpression(amdgpu_gfx940::acc165, output_vec_len ); + case 678: return makeRegisterExpression(amdgpu_gfx940::acc166, output_vec_len ); + case 679: return makeRegisterExpression(amdgpu_gfx940::acc167, output_vec_len ); + case 680: return makeRegisterExpression(amdgpu_gfx940::acc168, output_vec_len ); + case 681: return makeRegisterExpression(amdgpu_gfx940::acc169, output_vec_len ); + case 682: return makeRegisterExpression(amdgpu_gfx940::acc170, output_vec_len ); + case 683: return makeRegisterExpression(amdgpu_gfx940::acc171, output_vec_len ); + case 684: return makeRegisterExpression(amdgpu_gfx940::acc172, output_vec_len ); + case 685: return makeRegisterExpression(amdgpu_gfx940::acc173, output_vec_len ); + case 686: return makeRegisterExpression(amdgpu_gfx940::acc174, output_vec_len ); + case 687: return makeRegisterExpression(amdgpu_gfx940::acc175, output_vec_len ); + case 688: return makeRegisterExpression(amdgpu_gfx940::acc176, output_vec_len ); + case 689: return makeRegisterExpression(amdgpu_gfx940::acc177, output_vec_len ); + case 690: return makeRegisterExpression(amdgpu_gfx940::acc178, output_vec_len ); + case 691: return makeRegisterExpression(amdgpu_gfx940::acc179, output_vec_len ); + case 692: return makeRegisterExpression(amdgpu_gfx940::acc180, output_vec_len ); + case 693: return makeRegisterExpression(amdgpu_gfx940::acc181, output_vec_len ); + case 694: return makeRegisterExpression(amdgpu_gfx940::acc182, output_vec_len ); + case 695: return makeRegisterExpression(amdgpu_gfx940::acc183, output_vec_len ); + case 696: return makeRegisterExpression(amdgpu_gfx940::acc184, output_vec_len ); + case 697: return makeRegisterExpression(amdgpu_gfx940::acc185, output_vec_len ); + case 698: return makeRegisterExpression(amdgpu_gfx940::acc186, output_vec_len ); + case 699: return makeRegisterExpression(amdgpu_gfx940::acc187, output_vec_len ); + case 700: return makeRegisterExpression(amdgpu_gfx940::acc188, output_vec_len ); + case 701: return makeRegisterExpression(amdgpu_gfx940::acc189, output_vec_len ); + case 702: return makeRegisterExpression(amdgpu_gfx940::acc190, output_vec_len ); + case 703: return makeRegisterExpression(amdgpu_gfx940::acc191, output_vec_len ); + case 704: return makeRegisterExpression(amdgpu_gfx940::acc192, output_vec_len ); + case 705: return makeRegisterExpression(amdgpu_gfx940::acc193, output_vec_len ); + case 706: return makeRegisterExpression(amdgpu_gfx940::acc194, output_vec_len ); + case 707: return makeRegisterExpression(amdgpu_gfx940::acc195, output_vec_len ); + case 708: return makeRegisterExpression(amdgpu_gfx940::acc196, output_vec_len ); + case 709: return makeRegisterExpression(amdgpu_gfx940::acc197, output_vec_len ); + case 710: return makeRegisterExpression(amdgpu_gfx940::acc198, output_vec_len ); + case 711: return makeRegisterExpression(amdgpu_gfx940::acc199, output_vec_len ); + case 712: return makeRegisterExpression(amdgpu_gfx940::acc200, output_vec_len ); + case 713: return makeRegisterExpression(amdgpu_gfx940::acc201, output_vec_len ); + case 714: return makeRegisterExpression(amdgpu_gfx940::acc202, output_vec_len ); + case 715: return makeRegisterExpression(amdgpu_gfx940::acc203, output_vec_len ); + case 716: return makeRegisterExpression(amdgpu_gfx940::acc204, output_vec_len ); + case 717: return makeRegisterExpression(amdgpu_gfx940::acc205, output_vec_len ); + case 718: return makeRegisterExpression(amdgpu_gfx940::acc206, output_vec_len ); + case 719: return makeRegisterExpression(amdgpu_gfx940::acc207, output_vec_len ); + case 720: return makeRegisterExpression(amdgpu_gfx940::acc208, output_vec_len ); + case 721: return makeRegisterExpression(amdgpu_gfx940::acc209, output_vec_len ); + case 722: return makeRegisterExpression(amdgpu_gfx940::acc210, output_vec_len ); + case 723: return makeRegisterExpression(amdgpu_gfx940::acc211, output_vec_len ); + case 724: return makeRegisterExpression(amdgpu_gfx940::acc212, output_vec_len ); + case 725: return makeRegisterExpression(amdgpu_gfx940::acc213, output_vec_len ); + case 726: return makeRegisterExpression(amdgpu_gfx940::acc214, output_vec_len ); + case 727: return makeRegisterExpression(amdgpu_gfx940::acc215, output_vec_len ); + case 728: return makeRegisterExpression(amdgpu_gfx940::acc216, output_vec_len ); + case 729: return makeRegisterExpression(amdgpu_gfx940::acc217, output_vec_len ); + case 730: return makeRegisterExpression(amdgpu_gfx940::acc218, output_vec_len ); + case 731: return makeRegisterExpression(amdgpu_gfx940::acc219, output_vec_len ); + case 732: return makeRegisterExpression(amdgpu_gfx940::acc220, output_vec_len ); + case 733: return makeRegisterExpression(amdgpu_gfx940::acc221, output_vec_len ); + case 734: return makeRegisterExpression(amdgpu_gfx940::acc222, output_vec_len ); + case 735: return makeRegisterExpression(amdgpu_gfx940::acc223, output_vec_len ); + case 736: return makeRegisterExpression(amdgpu_gfx940::acc224, output_vec_len ); + case 737: return makeRegisterExpression(amdgpu_gfx940::acc225, output_vec_len ); + case 738: return makeRegisterExpression(amdgpu_gfx940::acc226, output_vec_len ); + case 739: return makeRegisterExpression(amdgpu_gfx940::acc227, output_vec_len ); + case 740: return makeRegisterExpression(amdgpu_gfx940::acc228, output_vec_len ); + case 741: return makeRegisterExpression(amdgpu_gfx940::acc229, output_vec_len ); + case 742: return makeRegisterExpression(amdgpu_gfx940::acc230, output_vec_len ); + case 743: return makeRegisterExpression(amdgpu_gfx940::acc231, output_vec_len ); + case 744: return makeRegisterExpression(amdgpu_gfx940::acc232, output_vec_len ); + case 745: return makeRegisterExpression(amdgpu_gfx940::acc233, output_vec_len ); + case 746: return makeRegisterExpression(amdgpu_gfx940::acc234, output_vec_len ); + case 747: return makeRegisterExpression(amdgpu_gfx940::acc235, output_vec_len ); + case 748: return makeRegisterExpression(amdgpu_gfx940::acc236, output_vec_len ); + case 749: return makeRegisterExpression(amdgpu_gfx940::acc237, output_vec_len ); + case 750: return makeRegisterExpression(amdgpu_gfx940::acc238, output_vec_len ); + case 751: return makeRegisterExpression(amdgpu_gfx940::acc239, output_vec_len ); + case 752: return makeRegisterExpression(amdgpu_gfx940::acc240, output_vec_len ); + case 753: return makeRegisterExpression(amdgpu_gfx940::acc241, output_vec_len ); + case 754: return makeRegisterExpression(amdgpu_gfx940::acc242, output_vec_len ); + case 755: return makeRegisterExpression(amdgpu_gfx940::acc243, output_vec_len ); + case 756: return makeRegisterExpression(amdgpu_gfx940::acc244, output_vec_len ); + case 757: return makeRegisterExpression(amdgpu_gfx940::acc245, output_vec_len ); + case 758: return makeRegisterExpression(amdgpu_gfx940::acc246, output_vec_len ); + case 759: return makeRegisterExpression(amdgpu_gfx940::acc247, output_vec_len ); + case 760: return makeRegisterExpression(amdgpu_gfx940::acc248, output_vec_len ); + case 761: return makeRegisterExpression(amdgpu_gfx940::acc249, output_vec_len ); + case 762: return makeRegisterExpression(amdgpu_gfx940::acc250, output_vec_len ); + case 763: return makeRegisterExpression(amdgpu_gfx940::acc251, output_vec_len ); + case 764: return makeRegisterExpression(amdgpu_gfx940::acc252, output_vec_len ); + case 765: return makeRegisterExpression(amdgpu_gfx940::acc253, output_vec_len ); + case 766: return makeRegisterExpression(amdgpu_gfx940::acc254, output_vec_len ); + case 767: return makeRegisterExpression(amdgpu_gfx940::acc255, output_vec_len ); + default: return makeRegisterExpression(amdgpu_gfx940::invalid); + } + } + + Expression::Ptr InstructionDecoder_amdgpu_gfx940::decodeOPR_VGPR_OR_LDS(uint64_t input, uint32_t output_vec_len) + { + switch (input) { + case 256: return makeRegisterExpression(amdgpu_gfx940::v0, output_vec_len ); + case 257: return makeRegisterExpression(amdgpu_gfx940::v1, output_vec_len ); + case 258: return makeRegisterExpression(amdgpu_gfx940::v2, output_vec_len ); + case 259: return makeRegisterExpression(amdgpu_gfx940::v3, output_vec_len ); + case 260: return makeRegisterExpression(amdgpu_gfx940::v4, output_vec_len ); + case 261: return makeRegisterExpression(amdgpu_gfx940::v5, output_vec_len ); + case 262: return makeRegisterExpression(amdgpu_gfx940::v6, output_vec_len ); + case 263: return makeRegisterExpression(amdgpu_gfx940::v7, output_vec_len ); + case 264: return makeRegisterExpression(amdgpu_gfx940::v8, output_vec_len ); + case 265: return makeRegisterExpression(amdgpu_gfx940::v9, output_vec_len ); + case 266: return makeRegisterExpression(amdgpu_gfx940::v10, output_vec_len ); + case 267: return makeRegisterExpression(amdgpu_gfx940::v11, output_vec_len ); + case 268: return makeRegisterExpression(amdgpu_gfx940::v12, output_vec_len ); + case 269: return makeRegisterExpression(amdgpu_gfx940::v13, output_vec_len ); + case 270: return makeRegisterExpression(amdgpu_gfx940::v14, output_vec_len ); + case 271: return makeRegisterExpression(amdgpu_gfx940::v15, output_vec_len ); + case 272: return makeRegisterExpression(amdgpu_gfx940::v16, output_vec_len ); + case 273: return makeRegisterExpression(amdgpu_gfx940::v17, output_vec_len ); + case 274: return makeRegisterExpression(amdgpu_gfx940::v18, output_vec_len ); + case 275: return makeRegisterExpression(amdgpu_gfx940::v19, output_vec_len ); + case 276: return makeRegisterExpression(amdgpu_gfx940::v20, output_vec_len ); + case 277: return makeRegisterExpression(amdgpu_gfx940::v21, output_vec_len ); + case 278: return makeRegisterExpression(amdgpu_gfx940::v22, output_vec_len ); + case 279: return makeRegisterExpression(amdgpu_gfx940::v23, output_vec_len ); + case 280: return makeRegisterExpression(amdgpu_gfx940::v24, output_vec_len ); + case 281: return makeRegisterExpression(amdgpu_gfx940::v25, output_vec_len ); + case 282: return makeRegisterExpression(amdgpu_gfx940::v26, output_vec_len ); + case 283: return makeRegisterExpression(amdgpu_gfx940::v27, output_vec_len ); + case 284: return makeRegisterExpression(amdgpu_gfx940::v28, output_vec_len ); + case 285: return makeRegisterExpression(amdgpu_gfx940::v29, output_vec_len ); + case 286: return makeRegisterExpression(amdgpu_gfx940::v30, output_vec_len ); + case 287: return makeRegisterExpression(amdgpu_gfx940::v31, output_vec_len ); + case 288: return makeRegisterExpression(amdgpu_gfx940::v32, output_vec_len ); + case 289: return makeRegisterExpression(amdgpu_gfx940::v33, output_vec_len ); + case 290: return makeRegisterExpression(amdgpu_gfx940::v34, output_vec_len ); + case 291: return makeRegisterExpression(amdgpu_gfx940::v35, output_vec_len ); + case 292: return makeRegisterExpression(amdgpu_gfx940::v36, output_vec_len ); + case 293: return makeRegisterExpression(amdgpu_gfx940::v37, output_vec_len ); + case 294: return makeRegisterExpression(amdgpu_gfx940::v38, output_vec_len ); + case 295: return makeRegisterExpression(amdgpu_gfx940::v39, output_vec_len ); + case 296: return makeRegisterExpression(amdgpu_gfx940::v40, output_vec_len ); + case 297: return makeRegisterExpression(amdgpu_gfx940::v41, output_vec_len ); + case 298: return makeRegisterExpression(amdgpu_gfx940::v42, output_vec_len ); + case 299: return makeRegisterExpression(amdgpu_gfx940::v43, output_vec_len ); + case 300: return makeRegisterExpression(amdgpu_gfx940::v44, output_vec_len ); + case 301: return makeRegisterExpression(amdgpu_gfx940::v45, output_vec_len ); + case 302: return makeRegisterExpression(amdgpu_gfx940::v46, output_vec_len ); + case 303: return makeRegisterExpression(amdgpu_gfx940::v47, output_vec_len ); + case 304: return makeRegisterExpression(amdgpu_gfx940::v48, output_vec_len ); + case 305: return makeRegisterExpression(amdgpu_gfx940::v49, output_vec_len ); + case 306: return makeRegisterExpression(amdgpu_gfx940::v50, output_vec_len ); + case 307: return makeRegisterExpression(amdgpu_gfx940::v51, output_vec_len ); + case 308: return makeRegisterExpression(amdgpu_gfx940::v52, output_vec_len ); + case 309: return makeRegisterExpression(amdgpu_gfx940::v53, output_vec_len ); + case 310: return makeRegisterExpression(amdgpu_gfx940::v54, output_vec_len ); + case 311: return makeRegisterExpression(amdgpu_gfx940::v55, output_vec_len ); + case 312: return makeRegisterExpression(amdgpu_gfx940::v56, output_vec_len ); + case 313: return makeRegisterExpression(amdgpu_gfx940::v57, output_vec_len ); + case 314: return makeRegisterExpression(amdgpu_gfx940::v58, output_vec_len ); + case 315: return makeRegisterExpression(amdgpu_gfx940::v59, output_vec_len ); + case 316: return makeRegisterExpression(amdgpu_gfx940::v60, output_vec_len ); + case 317: return makeRegisterExpression(amdgpu_gfx940::v61, output_vec_len ); + case 318: return makeRegisterExpression(amdgpu_gfx940::v62, output_vec_len ); + case 319: return makeRegisterExpression(amdgpu_gfx940::v63, output_vec_len ); + case 320: return makeRegisterExpression(amdgpu_gfx940::v64, output_vec_len ); + case 321: return makeRegisterExpression(amdgpu_gfx940::v65, output_vec_len ); + case 322: return makeRegisterExpression(amdgpu_gfx940::v66, output_vec_len ); + case 323: return makeRegisterExpression(amdgpu_gfx940::v67, output_vec_len ); + case 324: return makeRegisterExpression(amdgpu_gfx940::v68, output_vec_len ); + case 325: return makeRegisterExpression(amdgpu_gfx940::v69, output_vec_len ); + case 326: return makeRegisterExpression(amdgpu_gfx940::v70, output_vec_len ); + case 327: return makeRegisterExpression(amdgpu_gfx940::v71, output_vec_len ); + case 328: return makeRegisterExpression(amdgpu_gfx940::v72, output_vec_len ); + case 329: return makeRegisterExpression(amdgpu_gfx940::v73, output_vec_len ); + case 330: return makeRegisterExpression(amdgpu_gfx940::v74, output_vec_len ); + case 331: return makeRegisterExpression(amdgpu_gfx940::v75, output_vec_len ); + case 332: return makeRegisterExpression(amdgpu_gfx940::v76, output_vec_len ); + case 333: return makeRegisterExpression(amdgpu_gfx940::v77, output_vec_len ); + case 334: return makeRegisterExpression(amdgpu_gfx940::v78, output_vec_len ); + case 335: return makeRegisterExpression(amdgpu_gfx940::v79, output_vec_len ); + case 336: return makeRegisterExpression(amdgpu_gfx940::v80, output_vec_len ); + case 337: return makeRegisterExpression(amdgpu_gfx940::v81, output_vec_len ); + case 338: return makeRegisterExpression(amdgpu_gfx940::v82, output_vec_len ); + case 339: return makeRegisterExpression(amdgpu_gfx940::v83, output_vec_len ); + case 340: return makeRegisterExpression(amdgpu_gfx940::v84, output_vec_len ); + case 341: return makeRegisterExpression(amdgpu_gfx940::v85, output_vec_len ); + case 342: return makeRegisterExpression(amdgpu_gfx940::v86, output_vec_len ); + case 343: return makeRegisterExpression(amdgpu_gfx940::v87, output_vec_len ); + case 344: return makeRegisterExpression(amdgpu_gfx940::v88, output_vec_len ); + case 345: return makeRegisterExpression(amdgpu_gfx940::v89, output_vec_len ); + case 346: return makeRegisterExpression(amdgpu_gfx940::v90, output_vec_len ); + case 347: return makeRegisterExpression(amdgpu_gfx940::v91, output_vec_len ); + case 348: return makeRegisterExpression(amdgpu_gfx940::v92, output_vec_len ); + case 349: return makeRegisterExpression(amdgpu_gfx940::v93, output_vec_len ); + case 350: return makeRegisterExpression(amdgpu_gfx940::v94, output_vec_len ); + case 351: return makeRegisterExpression(amdgpu_gfx940::v95, output_vec_len ); + case 352: return makeRegisterExpression(amdgpu_gfx940::v96, output_vec_len ); + case 353: return makeRegisterExpression(amdgpu_gfx940::v97, output_vec_len ); + case 354: return makeRegisterExpression(amdgpu_gfx940::v98, output_vec_len ); + case 355: return makeRegisterExpression(amdgpu_gfx940::v99, output_vec_len ); + case 356: return makeRegisterExpression(amdgpu_gfx940::v100, output_vec_len ); + case 357: return makeRegisterExpression(amdgpu_gfx940::v101, output_vec_len ); + case 358: return makeRegisterExpression(amdgpu_gfx940::v102, output_vec_len ); + case 359: return makeRegisterExpression(amdgpu_gfx940::v103, output_vec_len ); + case 360: return makeRegisterExpression(amdgpu_gfx940::v104, output_vec_len ); + case 361: return makeRegisterExpression(amdgpu_gfx940::v105, output_vec_len ); + case 362: return makeRegisterExpression(amdgpu_gfx940::v106, output_vec_len ); + case 363: return makeRegisterExpression(amdgpu_gfx940::v107, output_vec_len ); + case 364: return makeRegisterExpression(amdgpu_gfx940::v108, output_vec_len ); + case 365: return makeRegisterExpression(amdgpu_gfx940::v109, output_vec_len ); + case 366: return makeRegisterExpression(amdgpu_gfx940::v110, output_vec_len ); + case 367: return makeRegisterExpression(amdgpu_gfx940::v111, output_vec_len ); + case 368: return makeRegisterExpression(amdgpu_gfx940::v112, output_vec_len ); + case 369: return makeRegisterExpression(amdgpu_gfx940::v113, output_vec_len ); + case 370: return makeRegisterExpression(amdgpu_gfx940::v114, output_vec_len ); + case 371: return makeRegisterExpression(amdgpu_gfx940::v115, output_vec_len ); + case 372: return makeRegisterExpression(amdgpu_gfx940::v116, output_vec_len ); + case 373: return makeRegisterExpression(amdgpu_gfx940::v117, output_vec_len ); + case 374: return makeRegisterExpression(amdgpu_gfx940::v118, output_vec_len ); + case 375: return makeRegisterExpression(amdgpu_gfx940::v119, output_vec_len ); + case 376: return makeRegisterExpression(amdgpu_gfx940::v120, output_vec_len ); + case 377: return makeRegisterExpression(amdgpu_gfx940::v121, output_vec_len ); + case 378: return makeRegisterExpression(amdgpu_gfx940::v122, output_vec_len ); + case 379: return makeRegisterExpression(amdgpu_gfx940::v123, output_vec_len ); + case 380: return makeRegisterExpression(amdgpu_gfx940::v124, output_vec_len ); + case 381: return makeRegisterExpression(amdgpu_gfx940::v125, output_vec_len ); + case 382: return makeRegisterExpression(amdgpu_gfx940::v126, output_vec_len ); + case 383: return makeRegisterExpression(amdgpu_gfx940::v127, output_vec_len ); + case 384: return makeRegisterExpression(amdgpu_gfx940::v128, output_vec_len ); + case 385: return makeRegisterExpression(amdgpu_gfx940::v129, output_vec_len ); + case 386: return makeRegisterExpression(amdgpu_gfx940::v130, output_vec_len ); + case 387: return makeRegisterExpression(amdgpu_gfx940::v131, output_vec_len ); + case 388: return makeRegisterExpression(amdgpu_gfx940::v132, output_vec_len ); + case 389: return makeRegisterExpression(amdgpu_gfx940::v133, output_vec_len ); + case 390: return makeRegisterExpression(amdgpu_gfx940::v134, output_vec_len ); + case 391: return makeRegisterExpression(amdgpu_gfx940::v135, output_vec_len ); + case 392: return makeRegisterExpression(amdgpu_gfx940::v136, output_vec_len ); + case 393: return makeRegisterExpression(amdgpu_gfx940::v137, output_vec_len ); + case 394: return makeRegisterExpression(amdgpu_gfx940::v138, output_vec_len ); + case 395: return makeRegisterExpression(amdgpu_gfx940::v139, output_vec_len ); + case 396: return makeRegisterExpression(amdgpu_gfx940::v140, output_vec_len ); + case 397: return makeRegisterExpression(amdgpu_gfx940::v141, output_vec_len ); + case 398: return makeRegisterExpression(amdgpu_gfx940::v142, output_vec_len ); + case 399: return makeRegisterExpression(amdgpu_gfx940::v143, output_vec_len ); + case 400: return makeRegisterExpression(amdgpu_gfx940::v144, output_vec_len ); + case 401: return makeRegisterExpression(amdgpu_gfx940::v145, output_vec_len ); + case 402: return makeRegisterExpression(amdgpu_gfx940::v146, output_vec_len ); + case 403: return makeRegisterExpression(amdgpu_gfx940::v147, output_vec_len ); + case 404: return makeRegisterExpression(amdgpu_gfx940::v148, output_vec_len ); + case 405: return makeRegisterExpression(amdgpu_gfx940::v149, output_vec_len ); + case 406: return makeRegisterExpression(amdgpu_gfx940::v150, output_vec_len ); + case 407: return makeRegisterExpression(amdgpu_gfx940::v151, output_vec_len ); + case 408: return makeRegisterExpression(amdgpu_gfx940::v152, output_vec_len ); + case 409: return makeRegisterExpression(amdgpu_gfx940::v153, output_vec_len ); + case 410: return makeRegisterExpression(amdgpu_gfx940::v154, output_vec_len ); + case 411: return makeRegisterExpression(amdgpu_gfx940::v155, output_vec_len ); + case 412: return makeRegisterExpression(amdgpu_gfx940::v156, output_vec_len ); + case 413: return makeRegisterExpression(amdgpu_gfx940::v157, output_vec_len ); + case 414: return makeRegisterExpression(amdgpu_gfx940::v158, output_vec_len ); + case 415: return makeRegisterExpression(amdgpu_gfx940::v159, output_vec_len ); + case 416: return makeRegisterExpression(amdgpu_gfx940::v160, output_vec_len ); + case 417: return makeRegisterExpression(amdgpu_gfx940::v161, output_vec_len ); + case 418: return makeRegisterExpression(amdgpu_gfx940::v162, output_vec_len ); + case 419: return makeRegisterExpression(amdgpu_gfx940::v163, output_vec_len ); + case 420: return makeRegisterExpression(amdgpu_gfx940::v164, output_vec_len ); + case 421: return makeRegisterExpression(amdgpu_gfx940::v165, output_vec_len ); + case 422: return makeRegisterExpression(amdgpu_gfx940::v166, output_vec_len ); + case 423: return makeRegisterExpression(amdgpu_gfx940::v167, output_vec_len ); + case 424: return makeRegisterExpression(amdgpu_gfx940::v168, output_vec_len ); + case 425: return makeRegisterExpression(amdgpu_gfx940::v169, output_vec_len ); + case 426: return makeRegisterExpression(amdgpu_gfx940::v170, output_vec_len ); + case 427: return makeRegisterExpression(amdgpu_gfx940::v171, output_vec_len ); + case 428: return makeRegisterExpression(amdgpu_gfx940::v172, output_vec_len ); + case 429: return makeRegisterExpression(amdgpu_gfx940::v173, output_vec_len ); + case 430: return makeRegisterExpression(amdgpu_gfx940::v174, output_vec_len ); + case 431: return makeRegisterExpression(amdgpu_gfx940::v175, output_vec_len ); + case 432: return makeRegisterExpression(amdgpu_gfx940::v176, output_vec_len ); + case 433: return makeRegisterExpression(amdgpu_gfx940::v177, output_vec_len ); + case 434: return makeRegisterExpression(amdgpu_gfx940::v178, output_vec_len ); + case 435: return makeRegisterExpression(amdgpu_gfx940::v179, output_vec_len ); + case 436: return makeRegisterExpression(amdgpu_gfx940::v180, output_vec_len ); + case 437: return makeRegisterExpression(amdgpu_gfx940::v181, output_vec_len ); + case 438: return makeRegisterExpression(amdgpu_gfx940::v182, output_vec_len ); + case 439: return makeRegisterExpression(amdgpu_gfx940::v183, output_vec_len ); + case 440: return makeRegisterExpression(amdgpu_gfx940::v184, output_vec_len ); + case 441: return makeRegisterExpression(amdgpu_gfx940::v185, output_vec_len ); + case 442: return makeRegisterExpression(amdgpu_gfx940::v186, output_vec_len ); + case 443: return makeRegisterExpression(amdgpu_gfx940::v187, output_vec_len ); + case 444: return makeRegisterExpression(amdgpu_gfx940::v188, output_vec_len ); + case 445: return makeRegisterExpression(amdgpu_gfx940::v189, output_vec_len ); + case 446: return makeRegisterExpression(amdgpu_gfx940::v190, output_vec_len ); + case 447: return makeRegisterExpression(amdgpu_gfx940::v191, output_vec_len ); + case 448: return makeRegisterExpression(amdgpu_gfx940::v192, output_vec_len ); + case 449: return makeRegisterExpression(amdgpu_gfx940::v193, output_vec_len ); + case 450: return makeRegisterExpression(amdgpu_gfx940::v194, output_vec_len ); + case 451: return makeRegisterExpression(amdgpu_gfx940::v195, output_vec_len ); + case 452: return makeRegisterExpression(amdgpu_gfx940::v196, output_vec_len ); + case 453: return makeRegisterExpression(amdgpu_gfx940::v197, output_vec_len ); + case 454: return makeRegisterExpression(amdgpu_gfx940::v198, output_vec_len ); + case 455: return makeRegisterExpression(amdgpu_gfx940::v199, output_vec_len ); + case 456: return makeRegisterExpression(amdgpu_gfx940::v200, output_vec_len ); + case 457: return makeRegisterExpression(amdgpu_gfx940::v201, output_vec_len ); + case 458: return makeRegisterExpression(amdgpu_gfx940::v202, output_vec_len ); + case 459: return makeRegisterExpression(amdgpu_gfx940::v203, output_vec_len ); + case 460: return makeRegisterExpression(amdgpu_gfx940::v204, output_vec_len ); + case 461: return makeRegisterExpression(amdgpu_gfx940::v205, output_vec_len ); + case 462: return makeRegisterExpression(amdgpu_gfx940::v206, output_vec_len ); + case 463: return makeRegisterExpression(amdgpu_gfx940::v207, output_vec_len ); + case 464: return makeRegisterExpression(amdgpu_gfx940::v208, output_vec_len ); + case 465: return makeRegisterExpression(amdgpu_gfx940::v209, output_vec_len ); + case 466: return makeRegisterExpression(amdgpu_gfx940::v210, output_vec_len ); + case 467: return makeRegisterExpression(amdgpu_gfx940::v211, output_vec_len ); + case 468: return makeRegisterExpression(amdgpu_gfx940::v212, output_vec_len ); + case 469: return makeRegisterExpression(amdgpu_gfx940::v213, output_vec_len ); + case 470: return makeRegisterExpression(amdgpu_gfx940::v214, output_vec_len ); + case 471: return makeRegisterExpression(amdgpu_gfx940::v215, output_vec_len ); + case 472: return makeRegisterExpression(amdgpu_gfx940::v216, output_vec_len ); + case 473: return makeRegisterExpression(amdgpu_gfx940::v217, output_vec_len ); + case 474: return makeRegisterExpression(amdgpu_gfx940::v218, output_vec_len ); + case 475: return makeRegisterExpression(amdgpu_gfx940::v219, output_vec_len ); + case 476: return makeRegisterExpression(amdgpu_gfx940::v220, output_vec_len ); + case 477: return makeRegisterExpression(amdgpu_gfx940::v221, output_vec_len ); + case 478: return makeRegisterExpression(amdgpu_gfx940::v222, output_vec_len ); + case 479: return makeRegisterExpression(amdgpu_gfx940::v223, output_vec_len ); + case 480: return makeRegisterExpression(amdgpu_gfx940::v224, output_vec_len ); + case 481: return makeRegisterExpression(amdgpu_gfx940::v225, output_vec_len ); + case 482: return makeRegisterExpression(amdgpu_gfx940::v226, output_vec_len ); + case 483: return makeRegisterExpression(amdgpu_gfx940::v227, output_vec_len ); + case 484: return makeRegisterExpression(amdgpu_gfx940::v228, output_vec_len ); + case 485: return makeRegisterExpression(amdgpu_gfx940::v229, output_vec_len ); + case 486: return makeRegisterExpression(amdgpu_gfx940::v230, output_vec_len ); + case 487: return makeRegisterExpression(amdgpu_gfx940::v231, output_vec_len ); + case 488: return makeRegisterExpression(amdgpu_gfx940::v232, output_vec_len ); + case 489: return makeRegisterExpression(amdgpu_gfx940::v233, output_vec_len ); + case 490: return makeRegisterExpression(amdgpu_gfx940::v234, output_vec_len ); + case 491: return makeRegisterExpression(amdgpu_gfx940::v235, output_vec_len ); + case 492: return makeRegisterExpression(amdgpu_gfx940::v236, output_vec_len ); + case 493: return makeRegisterExpression(amdgpu_gfx940::v237, output_vec_len ); + case 494: return makeRegisterExpression(amdgpu_gfx940::v238, output_vec_len ); + case 495: return makeRegisterExpression(amdgpu_gfx940::v239, output_vec_len ); + case 496: return makeRegisterExpression(amdgpu_gfx940::v240, output_vec_len ); + case 497: return makeRegisterExpression(amdgpu_gfx940::v241, output_vec_len ); + case 498: return makeRegisterExpression(amdgpu_gfx940::v242, output_vec_len ); + case 499: return makeRegisterExpression(amdgpu_gfx940::v243, output_vec_len ); + case 500: return makeRegisterExpression(amdgpu_gfx940::v244, output_vec_len ); + case 501: return makeRegisterExpression(amdgpu_gfx940::v245, output_vec_len ); + case 502: return makeRegisterExpression(amdgpu_gfx940::v246, output_vec_len ); + case 503: return makeRegisterExpression(amdgpu_gfx940::v247, output_vec_len ); + case 504: return makeRegisterExpression(amdgpu_gfx940::v248, output_vec_len ); + case 505: return makeRegisterExpression(amdgpu_gfx940::v249, output_vec_len ); + case 506: return makeRegisterExpression(amdgpu_gfx940::v250, output_vec_len ); + case 507: return makeRegisterExpression(amdgpu_gfx940::v251, output_vec_len ); + case 508: return makeRegisterExpression(amdgpu_gfx940::v252, output_vec_len ); + case 509: return makeRegisterExpression(amdgpu_gfx940::v253, output_vec_len ); + case 510: return makeRegisterExpression(amdgpu_gfx940::v254, output_vec_len ); + case 511: return makeRegisterExpression(amdgpu_gfx940::v255, output_vec_len ); + default: return makeRegisterExpression(amdgpu_gfx940::invalid); + } + } + +} +} diff --git a/instructionAPI/src/AMDGPU/gfx940/finalizeOperands.C b/instructionAPI/src/AMDGPU/gfx940/finalizeOperands.C new file mode 100644 index 0000000000..d71604df72 --- /dev/null +++ b/instructionAPI/src/AMDGPU/gfx940/finalizeOperands.C @@ -0,0 +1,2267 @@ +#include "registers/AMDGPU/amdgpu_gfx940_regs.h" +#include "InstructionDecoder-amdgpu-gfx940.h" + +namespace Dyninst { +namespace InstructionAPI { + void InstructionDecoder_amdgpu_gfx940::finalizeENC_DSOperands() + { + layout_ENC_DS & layout = insn_layout.ENC_DS; + switch (layout.OP) { + case 0: case 1: case 2: case 3: case 4: // DS_ADD_U32,DS_SUB_U32,DS_RSUB_U32,DS_INC_U32,DS_DEC_U32, + case 5: case 6: case 7: case 8: case 9: // DS_MIN_I32,DS_MAX_I32,DS_MIN_U32,DS_MAX_U32,DS_AND_B32, + case 10: case 11: case 13: case 18: case 19: // DS_OR_B32,DS_XOR_B32,DS_WRITE_B32,DS_MIN_F32,DS_MAX_F32, + case 21: case 30: case 31: case 84: // DS_ADD_F32,DS_WRITE_B8,DS_WRITE_B16,DS_WRITE_B8_D16_HI, + case 85: // DS_WRITE_B16_D16_HI, + appendOPR_VGPR(layout.ADDR,true,false); + appendOPR_VGPR_OR_ACCVGPR(layout.DATA0,true,false); + appendOPR_DSMEM(0,true,false,1,true); + if (layout.OFFSET0 || layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,(layout.OFFSET1 << 8) + layout.OFFSET0)),true,false,false); + } + break; + case 12: case 16: case 17: // DS_MSKOR_B32,DS_CMPST_B32,DS_CMPST_F32, + appendOPR_VGPR(layout.ADDR,true,false); + appendOPR_VGPR_OR_ACCVGPR(layout.DATA0,true,false); + appendOPR_VGPR_OR_ACCVGPR(layout.DATA1,true,false); + appendOPR_DSMEM(0,true,false,1,true); + if (layout.OFFSET0 || layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,(layout.OFFSET1 << 8) + layout.OFFSET0)),true,false,false); + } + break; + case 14: case 15: // DS_WRITE2_B32,DS_WRITE2ST64_B32, + appendOPR_VGPR(layout.ADDR,true,false); + appendOPR_VGPR_OR_ACCVGPR(layout.DATA0,true,false); + appendOPR_VGPR_OR_ACCVGPR(layout.DATA1,true,false); + appendOPR_DSMEM(0,true,false,1,true); + if (layout.OFFSET0) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset0"),Result(u8,layout.OFFSET0)),true,false,false); + } + if (layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset1"),Result(u8,layout.OFFSET1)),true,false,false); + } + break; + case 20: // DS_NOP, + if (layout.OFFSET0 || layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,(layout.OFFSET1 << 8) + layout.OFFSET0)),true,false,false); + } + break; + case 23: case 24: // DS_PK_ADD_F16,DS_PK_ADD_BF16, + appendOPR_VGPR(layout.ADDR,true,false); + appendOPR_VGPR_OR_ACCVGPR(layout.DATA0,true,false); + if (layout.OFFSET0 || layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,(layout.OFFSET1 << 8) + layout.OFFSET0)),true,false,false); + } + break; + case 29: // DS_WRITE_ADDTID_B32, + appendOPR_VGPR_OR_ACCVGPR(layout.DATA0,true,false); + appendOPR_DSMEM(0,true,false,1,true); + appendOPR_SDST_M0(124,true,false,1,true); + if (layout.OFFSET0 || layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,(layout.OFFSET1 << 8) + layout.OFFSET0)),true,false,false); + } + break; + case 32: case 33: case 34: case 35: // DS_ADD_RTN_U32,DS_SUB_RTN_U32,DS_RSUB_RTN_U32,DS_INC_RTN_U32, + case 36: case 37: case 38: case 39: // DS_DEC_RTN_U32,DS_MIN_RTN_I32,DS_MAX_RTN_I32,DS_MIN_RTN_U32, + case 40: case 41: case 42: case 43: // DS_MAX_RTN_U32,DS_AND_RTN_B32,DS_OR_RTN_B32,DS_XOR_RTN_B32, + case 45: case 50: case 51: case 53: // DS_WRXCHG_RTN_B32,DS_MIN_RTN_F32,DS_MAX_RTN_F32,DS_ADD_RTN_F32, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true); + appendOPR_VGPR(layout.ADDR,true,false); + appendOPR_VGPR_OR_ACCVGPR(layout.DATA0,true,false); + appendOPR_DSMEM(0,true,false,1,true); + if (layout.OFFSET0 || layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,(layout.OFFSET1 << 8) + layout.OFFSET0)),true,false,false); + } + break; + case 44: case 48: case 49: case 52: // DS_MSKOR_RTN_B32,DS_CMPST_RTN_B32,DS_CMPST_RTN_F32,DS_WRAP_RTN_B32, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true); + appendOPR_VGPR(layout.ADDR,true,false); + appendOPR_VGPR_OR_ACCVGPR(layout.DATA0,true,false); + appendOPR_VGPR_OR_ACCVGPR(layout.DATA1,true,false); + appendOPR_DSMEM(0,true,false,1,true); + if (layout.OFFSET0 || layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,(layout.OFFSET1 << 8) + layout.OFFSET0)),true,false,false); + } + break; + case 46: case 47: // DS_WRXCHG2_RTN_B32,DS_WRXCHG2ST64_RTN_B32, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true,2); + appendOPR_VGPR(layout.ADDR,true,false); + appendOPR_VGPR_OR_ACCVGPR(layout.DATA0,true,false); + appendOPR_VGPR_OR_ACCVGPR(layout.DATA1,true,false); + appendOPR_DSMEM(0,true,false,1,true); + if (layout.OFFSET0 || layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,(layout.OFFSET1 << 8) + layout.OFFSET0)),true,false,false); + } + break; + case 54: case 57: case 58: case 59: case 60: // DS_READ_B32,DS_READ_I8,DS_READ_U8,DS_READ_I16,DS_READ_U16, + case 86: case 87: case 88: case 89: // DS_READ_U8_D16,DS_READ_U8_D16_HI,DS_READ_I8_D16,DS_READ_I8_D16_HI, + case 90: case 91: // DS_READ_U16_D16,DS_READ_U16_D16_HI, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true); + appendOPR_VGPR(layout.ADDR,true,false); + appendOPR_DSMEM(0,true,false,1,true); + if (layout.OFFSET0 || layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,(layout.OFFSET1 << 8) + layout.OFFSET0)),true,false,false); + } + break; + case 55: case 56: // DS_READ2_B32,DS_READ2ST64_B32, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true,2); + appendOPR_VGPR(layout.ADDR,true,false); + appendOPR_DSMEM(0,true,false,1,true); + if (layout.OFFSET0) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset0"),Result(u8,layout.OFFSET0)),true,false,false); + } + if (layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset1"),Result(u8,layout.OFFSET1)),true,false,false); + } + break; + case 61: // DS_SWIZZLE_B32, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true); + appendOPR_VGPR(layout.ADDR,true,false); + if (layout.OFFSET0 || layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,(layout.OFFSET1 << 8) + layout.OFFSET0)),true,false,false); + } + break; + case 62: case 63: case 183: case 184: // DS_PERMUTE_B32,DS_BPERMUTE_B32,DS_PK_ADD_RTN_F16,DS_PK_ADD_RTN_BF16, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true); + appendOPR_VGPR(layout.ADDR,true,false); + appendOPR_VGPR_OR_ACCVGPR(layout.DATA0,true,false); + if (layout.OFFSET0 || layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,(layout.OFFSET1 << 8) + layout.OFFSET0)),true,false,false); + } + break; + case 64: case 65: case 66: case 67: case 68: // DS_ADD_U64,DS_SUB_U64,DS_RSUB_U64,DS_INC_U64,DS_DEC_U64, + case 69: case 70: case 71: case 72: case 73: // DS_MIN_I64,DS_MAX_I64,DS_MIN_U64,DS_MAX_U64,DS_AND_B64, + case 74: case 75: case 77: case 82: case 83: // DS_OR_B64,DS_XOR_B64,DS_WRITE_B64,DS_MIN_F64,DS_MAX_F64, + appendOPR_VGPR(layout.ADDR,true,false); + appendOPR_VGPR_OR_ACCVGPR(layout.DATA0,true,false,2); + appendOPR_DSMEM(0,true,false,1,true); + if (layout.OFFSET0 || layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,(layout.OFFSET1 << 8) + layout.OFFSET0)),true,false,false); + } + break; + case 76: case 80: case 81: // DS_MSKOR_B64,DS_CMPST_B64,DS_CMPST_F64, + appendOPR_VGPR(layout.ADDR,true,false); + appendOPR_VGPR_OR_ACCVGPR(layout.DATA0,true,false,2); + appendOPR_VGPR_OR_ACCVGPR(layout.DATA1,true,false,2); + appendOPR_DSMEM(0,true,false,1,true); + if (layout.OFFSET0 || layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,(layout.OFFSET1 << 8) + layout.OFFSET0)),true,false,false); + } + break; + case 78: case 79: // DS_WRITE2_B64,DS_WRITE2ST64_B64, + appendOPR_VGPR(layout.ADDR,true,false); + appendOPR_VGPR_OR_ACCVGPR(layout.DATA0,true,false,2); + appendOPR_VGPR_OR_ACCVGPR(layout.DATA1,true,false,2); + appendOPR_DSMEM(0,true,false,1,true); + if (layout.OFFSET0) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset0"),Result(u8,layout.OFFSET0)),true,false,false); + } + if (layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset1"),Result(u8,layout.OFFSET1)),true,false,false); + } + break; + case 92: // DS_ADD_F64, + appendOPR_VGPR(layout.ADDR,true,false); + appendOPR_VGPR_OR_ACCVGPR(layout.DATA0,true,false,2); + if (layout.OFFSET0 || layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,(layout.OFFSET1 << 8) + layout.OFFSET0)),true,false,false); + } + break; + case 96: case 97: case 98: case 99: // DS_ADD_RTN_U64,DS_SUB_RTN_U64,DS_RSUB_RTN_U64,DS_INC_RTN_U64, + case 100: case 101: case 102: case 103: // DS_DEC_RTN_U64,DS_MIN_RTN_I64,DS_MAX_RTN_I64,DS_MIN_RTN_U64, + case 104: case 105: case 106: case 107: // DS_MAX_RTN_U64,DS_AND_RTN_B64,DS_OR_RTN_B64,DS_XOR_RTN_B64, + case 109: case 114: case 115: case 126: // DS_WRXCHG_RTN_B64,DS_MIN_RTN_F64,DS_MAX_RTN_F64,DS_CONDXCHG32_RTN_B64, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true,2); + appendOPR_VGPR(layout.ADDR,true,false); + appendOPR_VGPR_OR_ACCVGPR(layout.DATA0,true,false,2); + appendOPR_DSMEM(0,true,false,1,true); + if (layout.OFFSET0 || layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,(layout.OFFSET1 << 8) + layout.OFFSET0)),true,false,false); + } + break; + case 108: case 112: case 113: // DS_MSKOR_RTN_B64,DS_CMPST_RTN_B64,DS_CMPST_RTN_F64, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true,2); + appendOPR_VGPR(layout.ADDR,true,false); + appendOPR_VGPR_OR_ACCVGPR(layout.DATA0,true,false,2); + appendOPR_VGPR_OR_ACCVGPR(layout.DATA1,true,false,2); + appendOPR_DSMEM(0,true,false,1,true); + if (layout.OFFSET0 || layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,(layout.OFFSET1 << 8) + layout.OFFSET0)),true,false,false); + } + break; + case 110: case 111: // DS_WRXCHG2_RTN_B64,DS_WRXCHG2ST64_RTN_B64, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true,4); + appendOPR_VGPR(layout.ADDR,true,false); + appendOPR_VGPR_OR_ACCVGPR(layout.DATA0,true,false,2); + appendOPR_VGPR_OR_ACCVGPR(layout.DATA1,true,false,2); + appendOPR_DSMEM(0,true,false,1,true); + if (layout.OFFSET0 || layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,(layout.OFFSET1 << 8) + layout.OFFSET0)),true,false,false); + } + break; + case 118: // DS_READ_B64, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true,2); + appendOPR_VGPR(layout.ADDR,true,false); + appendOPR_DSMEM(0,true,false,1,true); + if (layout.OFFSET0 || layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,(layout.OFFSET1 << 8) + layout.OFFSET0)),true,false,false); + } + break; + case 119: case 120: // DS_READ2_B64,DS_READ2ST64_B64, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true,4); + appendOPR_VGPR(layout.ADDR,true,false); + appendOPR_DSMEM(0,true,false,1,true); + if (layout.OFFSET0) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset0"),Result(u8,layout.OFFSET0)),true,false,false); + } + if (layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset1"),Result(u8,layout.OFFSET1)),true,false,false); + } + break; + case 124: // DS_ADD_RTN_F64, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true,2); + appendOPR_VGPR(layout.ADDR,true,false); + appendOPR_VGPR_OR_ACCVGPR(layout.DATA0,true,false,2); + if (layout.OFFSET0 || layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,(layout.OFFSET1 << 8) + layout.OFFSET0)),true,false,false); + } + break; + case 152: case 154: case 156: // DS_GWS_SEMA_RELEASE_ALL,DS_GWS_SEMA_V,DS_GWS_SEMA_P, + appendOPR_SDST_M0(124,true,false,1,true); + if (layout.OFFSET0 || layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,(layout.OFFSET1 << 8) + layout.OFFSET0)),true,false,false); + } + break; + case 153: case 155: case 157: // DS_GWS_INIT,DS_GWS_SEMA_BR,DS_GWS_BARRIER, + appendOPR_VGPR_OR_ACCVGPR(layout.DATA0,true,false); + appendOPR_SDST_M0(124,true,false,1,true); + if (layout.OFFSET0 || layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,(layout.OFFSET1 << 8) + layout.OFFSET0)),true,false,false); + } + break; + case 182: case 189: case 190: // DS_READ_ADDTID_B32,DS_CONSUME,DS_APPEND, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true); + appendOPR_DSMEM(0,true,false,1,true); + appendOPR_SDST_M0(124,true,false,1,true); + if (layout.OFFSET0 || layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,(layout.OFFSET1 << 8) + layout.OFFSET0)),true,false,false); + } + break; + case 222: // DS_WRITE_B96, + appendOPR_VGPR(layout.ADDR,true,false); + appendOPR_VGPR_OR_ACCVGPR(layout.DATA0,true,false,3); + appendOPR_DSMEM(0,true,false,1,true); + if (layout.OFFSET0 || layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,(layout.OFFSET1 << 8) + layout.OFFSET0)),true,false,false); + } + break; + case 223: // DS_WRITE_B128, + appendOPR_VGPR(layout.ADDR,true,false); + appendOPR_VGPR_OR_ACCVGPR(layout.DATA0,true,false,4); + appendOPR_DSMEM(0,true,false,1,true); + if (layout.OFFSET0 || layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,(layout.OFFSET1 << 8) + layout.OFFSET0)),true,false,false); + } + break; + case 254: // DS_READ_B96, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true,3); + appendOPR_VGPR(layout.ADDR,true,false); + appendOPR_DSMEM(0,true,false,1,true); + if (layout.OFFSET0 || layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,(layout.OFFSET1 << 8) + layout.OFFSET0)),true,false,false); + } + break; + case 255: // DS_READ_B128, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true,4); + appendOPR_VGPR(layout.ADDR,true,false); + appendOPR_DSMEM(0,true,false,1,true); + if (layout.OFFSET0 || layout.OFFSET1) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,(layout.OFFSET1 << 8) + layout.OFFSET0)),true,false,false); + } + break; + } + } + + void InstructionDecoder_amdgpu_gfx940::finalizeENC_FLATOperands() + { + layout_ENC_FLAT & layout = insn_layout.ENC_FLAT; + switch (layout.OP) { + case 16: case 17: case 18: case 19: // FLAT_LOAD_UBYTE,FLAT_LOAD_SBYTE,FLAT_LOAD_USHORT,FLAT_LOAD_SSHORT, + case 20: case 32: case 33: // FLAT_LOAD_DWORD,FLAT_LOAD_UBYTE_D16,FLAT_LOAD_UBYTE_D16_HI, + case 34: case 35: case 36: // FLAT_LOAD_SBYTE_D16,FLAT_LOAD_SBYTE_D16_HI,FLAT_LOAD_SHORT_D16, + case 37: // FLAT_LOAD_SHORT_D16_HI, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true); + appendOPR_VGPR(layout.ADDR,true,false,2); + appendOPR_FLAT_SCRATCH(0,true,false,1,true); + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::lgkmcnt,0,16),true,true,true); + break; + case 21: // FLAT_LOAD_DWORDX2, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true,2); + appendOPR_VGPR(layout.ADDR,true,false,2); + appendOPR_FLAT_SCRATCH(0,true,false,1,true); + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::lgkmcnt,0,16),true,true,true); + break; + case 22: // FLAT_LOAD_DWORDX3, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true,3); + appendOPR_VGPR(layout.ADDR,true,false,2); + appendOPR_FLAT_SCRATCH(0,true,false,1,true); + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::lgkmcnt,0,16),true,true,true); + break; + case 23: // FLAT_LOAD_DWORDX4, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true,4); + appendOPR_VGPR(layout.ADDR,true,false,2); + appendOPR_FLAT_SCRATCH(0,true,false,1,true); + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::lgkmcnt,0,16),true,true,true); + break; + case 24: case 25: case 26: // FLAT_STORE_BYTE,FLAT_STORE_BYTE_D16_HI,FLAT_STORE_SHORT, + case 27: case 28: // FLAT_STORE_SHORT_D16_HI,FLAT_STORE_DWORD, + appendOPR_VGPR(layout.ADDR,true,false,2); + appendOPR_VGPR_OR_ACCVGPR(layout.DATA,true,false); + appendOPR_FLAT_SCRATCH(0,true,false,1,true); + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::lgkmcnt,0,16),true,true,true); + break; + case 29: // FLAT_STORE_DWORDX2, + appendOPR_VGPR(layout.ADDR,true,false,2); + appendOPR_VGPR_OR_ACCVGPR(layout.DATA,true,false,2); + appendOPR_FLAT_SCRATCH(0,true,false,1,true); + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::lgkmcnt,0,16),true,true,true); + break; + case 30: // FLAT_STORE_DWORDX3, + appendOPR_VGPR(layout.ADDR,true,false,2); + appendOPR_VGPR_OR_ACCVGPR(layout.DATA,true,false,3); + appendOPR_FLAT_SCRATCH(0,true,false,1,true); + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::lgkmcnt,0,16),true,true,true); + break; + case 31: // FLAT_STORE_DWORDX4, + appendOPR_VGPR(layout.ADDR,true,false,2); + appendOPR_VGPR_OR_ACCVGPR(layout.DATA,true,false,4); + appendOPR_FLAT_SCRATCH(0,true,false,1,true); + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::lgkmcnt,0,16),true,true,true); + break; + case 64: case 66: case 67: case 68: // FLAT_ATOMIC_SWAP,FLAT_ATOMIC_ADD,FLAT_ATOMIC_SUB,FLAT_ATOMIC_SMIN, + case 69: case 70: case 71: case 72: // FLAT_ATOMIC_UMIN,FLAT_ATOMIC_SMAX,FLAT_ATOMIC_UMAX,FLAT_ATOMIC_AND, + case 73: case 74: case 75: case 76: // FLAT_ATOMIC_OR,FLAT_ATOMIC_XOR,FLAT_ATOMIC_INC,FLAT_ATOMIC_DEC, + case 77: case 78: case 82: // FLAT_ATOMIC_ADD_F32,FLAT_ATOMIC_PK_ADD_F16,FLAT_ATOMIC_PK_ADD_BF16, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true); + appendOPR_VGPR(layout.ADDR,true,false,2); + appendOPR_VGPR_OR_ACCVGPR(layout.DATA,true,false); + appendOPR_FLAT_SCRATCH(0,true,false,1,true); + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::lgkmcnt,0,16),true,true,true); + break; + case 65: // FLAT_ATOMIC_CMPSWAP, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true); + appendOPR_VGPR(layout.ADDR,true,false,2); + appendOPR_VGPR_OR_ACCVGPR(layout.DATA,true,false,2); + appendOPR_FLAT_SCRATCH(0,true,false,1,true); + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::lgkmcnt,0,16),true,true,true); + break; + case 79: case 80: case 81: // FLAT_ATOMIC_ADD_F64,FLAT_ATOMIC_MIN_F64,FLAT_ATOMIC_MAX_F64, + case 96: case 98: case 99: // FLAT_ATOMIC_SWAP_X2,FLAT_ATOMIC_ADD_X2,FLAT_ATOMIC_SUB_X2, + case 100: case 101: case 102: // FLAT_ATOMIC_SMIN_X2,FLAT_ATOMIC_UMIN_X2,FLAT_ATOMIC_SMAX_X2, + case 103: case 104: case 105: // FLAT_ATOMIC_UMAX_X2,FLAT_ATOMIC_AND_X2,FLAT_ATOMIC_OR_X2, + case 106: case 107: case 108: // FLAT_ATOMIC_XOR_X2,FLAT_ATOMIC_INC_X2,FLAT_ATOMIC_DEC_X2, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true,2); + appendOPR_VGPR(layout.ADDR,true,false,2); + appendOPR_VGPR_OR_ACCVGPR(layout.DATA,true,false,2); + appendOPR_FLAT_SCRATCH(0,true,false,1,true); + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::lgkmcnt,0,16),true,true,true); + break; + case 97: // FLAT_ATOMIC_CMPSWAP_X2, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true,2); + appendOPR_VGPR(layout.ADDR,true,false,2); + appendOPR_VGPR_OR_ACCVGPR(layout.DATA,true,false,4); + appendOPR_FLAT_SCRATCH(0,true,false,1,true); + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::lgkmcnt,0,16),true,true,true); + break; + } + } + + void InstructionDecoder_amdgpu_gfx940::finalizeENC_FLAT_GLBLOperands() + { + layout_ENC_FLAT_GLBL & layout = insn_layout.ENC_FLAT_GLBL; + switch (layout.OP) { + case 16: case 17: case 18: case 19: // GLOBAL_LOAD_UBYTE,GLOBAL_LOAD_SBYTE,GLOBAL_LOAD_USHORT,GLOBAL_LOAD_SSHORT, + case 20: case 32: case 33: // GLOBAL_LOAD_DWORD,GLOBAL_LOAD_UBYTE_D16,GLOBAL_LOAD_UBYTE_D16_HI, + case 34: case 35: case 36: // GLOBAL_LOAD_SBYTE_D16,GLOBAL_LOAD_SBYTE_D16_HI,GLOBAL_LOAD_SHORT_D16, + case 37: case 38: case 39: // GLOBAL_LOAD_SHORT_D16_HI,GLOBAL_LOAD_LDS_UBYTE,GLOBAL_LOAD_LDS_SBYTE, + case 40: case 41: case 42: // GLOBAL_LOAD_LDS_USHORT,GLOBAL_LOAD_LDS_SSHORT,GLOBAL_LOAD_LDS_DWORD, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true); + if (layout.SADDR == 0x7f) { + appendOPR_VGPR(layout.ADDR,true,false,2); + } else { + appendOPR_VGPR(layout.ADDR,true,false); + } + if (layout.SADDR != 0x7f) { + appendOPR_SREG(layout.SADDR,true,false,2); + } + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::lgkmcnt,0,16),true,true,true); + break; + case 21: // GLOBAL_LOAD_DWORDX2, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true,2); + if (layout.SADDR == 0x7f) { + appendOPR_VGPR(layout.ADDR,true,false,2); + } else { + appendOPR_VGPR(layout.ADDR,true,false); + } + if (layout.SADDR != 0x7f) { + appendOPR_SREG(layout.SADDR,true,false,2); + } + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::lgkmcnt,0,16),true,true,true); + break; + case 22: // GLOBAL_LOAD_DWORDX3, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true,3); + if (layout.SADDR == 0x7f) { + appendOPR_VGPR(layout.ADDR,true,false,2); + } else { + appendOPR_VGPR(layout.ADDR,true,false); + } + if (layout.SADDR != 0x7f) { + appendOPR_SREG(layout.SADDR,true,false,2); + } + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::lgkmcnt,0,16),true,true,true); + break; + case 23: // GLOBAL_LOAD_DWORDX4, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true,4); + if (layout.SADDR == 0x7f) { + appendOPR_VGPR(layout.ADDR,true,false,2); + } else { + appendOPR_VGPR(layout.ADDR,true,false); + } + if (layout.SADDR != 0x7f) { + appendOPR_SREG(layout.SADDR,true,false,2); + } + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::lgkmcnt,0,16),true,true,true); + break; + case 24: case 25: case 26: // GLOBAL_STORE_BYTE,GLOBAL_STORE_BYTE_D16_HI,GLOBAL_STORE_SHORT, + case 27: case 28: // GLOBAL_STORE_SHORT_D16_HI,GLOBAL_STORE_DWORD, + if (layout.SADDR == 0x7f) { + appendOPR_VGPR(layout.ADDR,true,false,2); + } else { + appendOPR_VGPR(layout.ADDR,true,false); + } + appendOPR_VGPR_OR_ACCVGPR(layout.DATA,true,false); + if (layout.SADDR != 0x7f) { + appendOPR_SREG(layout.SADDR,true,false,2); + } + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::lgkmcnt,0,16),true,true,true); + break; + case 29: // GLOBAL_STORE_DWORDX2, + if (layout.SADDR == 0x7f) { + appendOPR_VGPR(layout.ADDR,true,false,2); + } else { + appendOPR_VGPR(layout.ADDR,true,false); + } + appendOPR_VGPR_OR_ACCVGPR(layout.DATA,true,false,2); + if (layout.SADDR != 0x7f) { + appendOPR_SREG(layout.SADDR,true,false,2); + } + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::lgkmcnt,0,16),true,true,true); + break; + case 30: // GLOBAL_STORE_DWORDX3, + if (layout.SADDR == 0x7f) { + appendOPR_VGPR(layout.ADDR,true,false,2); + } else { + appendOPR_VGPR(layout.ADDR,true,false); + } + appendOPR_VGPR_OR_ACCVGPR(layout.DATA,true,false,3); + if (layout.SADDR != 0x7f) { + appendOPR_SREG(layout.SADDR,true,false,2); + } + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::lgkmcnt,0,16),true,true,true); + break; + case 31: // GLOBAL_STORE_DWORDX4, + if (layout.SADDR == 0x7f) { + appendOPR_VGPR(layout.ADDR,true,false,2); + } else { + appendOPR_VGPR(layout.ADDR,true,false); + } + appendOPR_VGPR_OR_ACCVGPR(layout.DATA,true,false,4); + if (layout.SADDR != 0x7f) { + appendOPR_SREG(layout.SADDR,true,false,2); + } + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::lgkmcnt,0,16),true,true,true); + break; + case 64: case 66: case 67: case 68: // GLOBAL_ATOMIC_SWAP,GLOBAL_ATOMIC_ADD,GLOBAL_ATOMIC_SUB,GLOBAL_ATOMIC_SMIN, + case 69: case 70: case 71: case 72: // GLOBAL_ATOMIC_UMIN,GLOBAL_ATOMIC_SMAX,GLOBAL_ATOMIC_UMAX,GLOBAL_ATOMIC_AND, + case 73: case 74: case 75: case 76: // GLOBAL_ATOMIC_OR,GLOBAL_ATOMIC_XOR,GLOBAL_ATOMIC_INC,GLOBAL_ATOMIC_DEC, + case 77: case 78: case 82: // GLOBAL_ATOMIC_ADD_F32,GLOBAL_ATOMIC_PK_ADD_F16,GLOBAL_ATOMIC_PK_ADD_BF16, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true); + if (layout.SADDR == 0x7f) { + appendOPR_VGPR(layout.ADDR,true,false,2); + } else { + appendOPR_VGPR(layout.ADDR,true,false); + } + appendOPR_VGPR_OR_ACCVGPR(layout.DATA,true,false); + if (layout.SADDR != 0x7f) { + appendOPR_SREG(layout.SADDR,true,false,2); + } + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::lgkmcnt,0,16),true,true,true); + break; + case 65: // GLOBAL_ATOMIC_CMPSWAP, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true); + if (layout.SADDR == 0x7f) { + appendOPR_VGPR(layout.ADDR,true,false,2); + } else { + appendOPR_VGPR(layout.ADDR,true,false); + } + appendOPR_VGPR_OR_ACCVGPR(layout.DATA,true,false,2); + if (layout.SADDR != 0x7f) { + appendOPR_SREG(layout.SADDR,true,false,2); + } + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::lgkmcnt,0,16),true,true,true); + break; + case 79: case 80: case 81: // GLOBAL_ATOMIC_ADD_F64,GLOBAL_ATOMIC_MIN_F64,GLOBAL_ATOMIC_MAX_F64, + case 96: case 98: case 99: // GLOBAL_ATOMIC_SWAP_X2,GLOBAL_ATOMIC_ADD_X2,GLOBAL_ATOMIC_SUB_X2, + case 100: case 101: case 102: // GLOBAL_ATOMIC_SMIN_X2,GLOBAL_ATOMIC_UMIN_X2,GLOBAL_ATOMIC_SMAX_X2, + case 103: case 104: case 105: // GLOBAL_ATOMIC_UMAX_X2,GLOBAL_ATOMIC_AND_X2,GLOBAL_ATOMIC_OR_X2, + case 106: case 107: case 108: // GLOBAL_ATOMIC_XOR_X2,GLOBAL_ATOMIC_INC_X2,GLOBAL_ATOMIC_DEC_X2, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true,2); + if (layout.SADDR == 0x7f) { + appendOPR_VGPR(layout.ADDR,true,false,2); + } else { + appendOPR_VGPR(layout.ADDR,true,false); + } + appendOPR_VGPR_OR_ACCVGPR(layout.DATA,true,false,2); + if (layout.SADDR != 0x7f) { + appendOPR_SREG(layout.SADDR,true,false,2); + } + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::lgkmcnt,0,16),true,true,true); + break; + case 97: // GLOBAL_ATOMIC_CMPSWAP_X2, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true,2); + if (layout.SADDR == 0x7f) { + appendOPR_VGPR(layout.ADDR,true,false,2); + } else { + appendOPR_VGPR(layout.ADDR,true,false); + } + appendOPR_VGPR_OR_ACCVGPR(layout.DATA,true,false,4); + if (layout.SADDR != 0x7f) { + appendOPR_SREG(layout.SADDR,true,false,2); + } + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::lgkmcnt,0,16),true,true,true); + break; + } + } + + void InstructionDecoder_amdgpu_gfx940::finalizeENC_FLAT_SCRATCHOperands() + { + layout_ENC_FLAT_SCRATCH & layout = insn_layout.ENC_FLAT_SCRATCH; + switch (layout.OP) { + case 16: case 17: case 18: case 19: // SCRATCH_LOAD_UBYTE,SCRATCH_LOAD_SBYTE,SCRATCH_LOAD_USHORT,SCRATCH_LOAD_SSHORT, + case 20: case 32: case 33: // SCRATCH_LOAD_DWORD,SCRATCH_LOAD_UBYTE_D16,SCRATCH_LOAD_UBYTE_D16_HI, + case 34: case 35: case 36: // SCRATCH_LOAD_SBYTE_D16,SCRATCH_LOAD_SBYTE_D16_HI,SCRATCH_LOAD_SHORT_D16, + case 37: case 38: case 39: // SCRATCH_LOAD_SHORT_D16_HI,SCRATCH_LOAD_LDS_UBYTE,SCRATCH_LOAD_LDS_SBYTE, + case 40: case 41: case 42: // SCRATCH_LOAD_LDS_USHORT,SCRATCH_LOAD_LDS_SSHORT,SCRATCH_LOAD_LDS_DWORD, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true); + if (layout.SADDR == 0x7f) { + appendOPR_VGPR(layout.ADDR,true,false,2); + } else { + appendOPR_VGPR(layout.ADDR,true,false); + } + if (layout.SADDR != 0x7f) { + appendOPR_SREG(layout.SADDR,true,false,2); + } + appendOPR_FLAT_SCRATCH(0,true,false,1,true); + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::lgkmcnt,0,16),true,true,true); + break; + case 21: // SCRATCH_LOAD_DWORDX2, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true,2); + if (layout.SADDR == 0x7f) { + appendOPR_VGPR(layout.ADDR,true,false,2); + } else { + appendOPR_VGPR(layout.ADDR,true,false); + } + if (layout.SADDR != 0x7f) { + appendOPR_SREG(layout.SADDR,true,false,2); + } + appendOPR_FLAT_SCRATCH(0,true,false,1,true); + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::lgkmcnt,0,16),true,true,true); + break; + case 22: // SCRATCH_LOAD_DWORDX3, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true,3); + if (layout.SADDR == 0x7f) { + appendOPR_VGPR(layout.ADDR,true,false,2); + } else { + appendOPR_VGPR(layout.ADDR,true,false); + } + if (layout.SADDR != 0x7f) { + appendOPR_SREG(layout.SADDR,true,false,2); + } + appendOPR_FLAT_SCRATCH(0,true,false,1,true); + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::lgkmcnt,0,16),true,true,true); + break; + case 23: // SCRATCH_LOAD_DWORDX4, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true,4); + if (layout.SADDR == 0x7f) { + appendOPR_VGPR(layout.ADDR,true,false,2); + } else { + appendOPR_VGPR(layout.ADDR,true,false); + } + if (layout.SADDR != 0x7f) { + appendOPR_SREG(layout.SADDR,true,false,2); + } + appendOPR_FLAT_SCRATCH(0,true,false,1,true); + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::lgkmcnt,0,16),true,true,true); + break; + case 24: case 25: case 26: // SCRATCH_STORE_BYTE,SCRATCH_STORE_BYTE_D16_HI,SCRATCH_STORE_SHORT, + case 27: case 28: // SCRATCH_STORE_SHORT_D16_HI,SCRATCH_STORE_DWORD, + if (layout.SADDR == 0x7f) { + appendOPR_VGPR(layout.ADDR,true,false,2); + } else { + appendOPR_VGPR(layout.ADDR,true,false); + } + appendOPR_VGPR_OR_ACCVGPR(layout.DATA,true,false); + if (layout.SADDR != 0x7f) { + appendOPR_SREG(layout.SADDR,true,false,2); + } + appendOPR_FLAT_SCRATCH(0,true,false,1,true); + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::lgkmcnt,0,16),true,true,true); + break; + case 29: // SCRATCH_STORE_DWORDX2, + if (layout.SADDR == 0x7f) { + appendOPR_VGPR(layout.ADDR,true,false,2); + } else { + appendOPR_VGPR(layout.ADDR,true,false); + } + appendOPR_VGPR_OR_ACCVGPR(layout.DATA,true,false,2); + if (layout.SADDR != 0x7f) { + appendOPR_SREG(layout.SADDR,true,false,2); + } + appendOPR_FLAT_SCRATCH(0,true,false,1,true); + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::lgkmcnt,0,16),true,true,true); + break; + case 30: // SCRATCH_STORE_DWORDX3, + if (layout.SADDR == 0x7f) { + appendOPR_VGPR(layout.ADDR,true,false,2); + } else { + appendOPR_VGPR(layout.ADDR,true,false); + } + appendOPR_VGPR_OR_ACCVGPR(layout.DATA,true,false,3); + if (layout.SADDR != 0x7f) { + appendOPR_SREG(layout.SADDR,true,false,2); + } + appendOPR_FLAT_SCRATCH(0,true,false,1,true); + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::lgkmcnt,0,16),true,true,true); + break; + case 31: // SCRATCH_STORE_DWORDX4, + if (layout.SADDR == 0x7f) { + appendOPR_VGPR(layout.ADDR,true,false,2); + } else { + appendOPR_VGPR(layout.ADDR,true,false); + } + appendOPR_VGPR_OR_ACCVGPR(layout.DATA,true,false,4); + if (layout.SADDR != 0x7f) { + appendOPR_SREG(layout.SADDR,true,false,2); + } + appendOPR_FLAT_SCRATCH(0,true,false,1,true); + appendOPR_SDST_M0(124,true,false,1,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::vmcnt,0,36),true,true,true); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::lgkmcnt,0,16),true,true,true); + break; + } + } + + void InstructionDecoder_amdgpu_gfx940::finalizeENC_MTBUFOperands() + { + layout_ENC_MTBUF & layout = insn_layout.ENC_MTBUF; + switch (layout.OP) { + case 0: case 8: case 9: // TBUFFER_LOAD_FORMAT_X,TBUFFER_LOAD_FORMAT_D16_X,TBUFFER_LOAD_FORMAT_D16_XY, + appendOPR_VGPR_OR_ACCVGPR(layout.VDATA,false,true); + appendOPR_VGPR(layout.VADDR,true,false,2); + appendOPR_SREG(layout.SRSRC,true,false,4); + appendOPR_SSRC_NOLIT(layout.SOFFSET,true,false); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::vmcnt,0,36),true,true,true); + break; + case 1: case 10: case 11: // TBUFFER_LOAD_FORMAT_XY,TBUFFER_LOAD_FORMAT_D16_XYZ,TBUFFER_LOAD_FORMAT_D16_XYZW, + appendOPR_VGPR_OR_ACCVGPR(layout.VDATA,false,true,2); + appendOPR_VGPR(layout.VADDR,true,false,2); + appendOPR_SREG(layout.SRSRC,true,false,4); + appendOPR_SSRC_NOLIT(layout.SOFFSET,true,false); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::vmcnt,0,36),true,true,true); + break; + case 2: // TBUFFER_LOAD_FORMAT_XYZ, + appendOPR_VGPR_OR_ACCVGPR(layout.VDATA,false,true,3); + appendOPR_VGPR(layout.VADDR,true,false,2); + appendOPR_SREG(layout.SRSRC,true,false,4); + appendOPR_SSRC_NOLIT(layout.SOFFSET,true,false); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::vmcnt,0,36),true,true,true); + break; + case 3: // TBUFFER_LOAD_FORMAT_XYZW, + appendOPR_VGPR_OR_ACCVGPR(layout.VDATA,false,true,4); + appendOPR_VGPR(layout.VADDR,true,false,2); + appendOPR_SREG(layout.SRSRC,true,false,4); + appendOPR_SSRC_NOLIT(layout.SOFFSET,true,false); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::vmcnt,0,36),true,true,true); + break; + case 4: case 12: case 13: // TBUFFER_STORE_FORMAT_X,TBUFFER_STORE_FORMAT_D16_X,TBUFFER_STORE_FORMAT_D16_XY, + appendOPR_VGPR_OR_ACCVGPR(layout.VDATA,true,false); + appendOPR_VGPR(layout.VADDR,true,false,2); + appendOPR_SREG(layout.SRSRC,true,false,4); + appendOPR_SSRC_NOLIT(layout.SOFFSET,true,false); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::vmcnt,0,36),true,true,true); + break; + case 5: case 14: case 15: // TBUFFER_STORE_FORMAT_XY,TBUFFER_STORE_FORMAT_D16_XYZ,TBUFFER_STORE_FORMAT_D16_XYZW, + appendOPR_VGPR_OR_ACCVGPR(layout.VDATA,true,false,2); + appendOPR_VGPR(layout.VADDR,true,false,2); + appendOPR_SREG(layout.SRSRC,true,false,4); + appendOPR_SSRC_NOLIT(layout.SOFFSET,true,false); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::vmcnt,0,36),true,true,true); + break; + case 6: // TBUFFER_STORE_FORMAT_XYZ, + appendOPR_VGPR_OR_ACCVGPR(layout.VDATA,true,false,3); + appendOPR_VGPR(layout.VADDR,true,false,2); + appendOPR_SREG(layout.SRSRC,true,false,4); + appendOPR_SSRC_NOLIT(layout.SOFFSET,true,false); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::vmcnt,0,36),true,true,true); + break; + case 7: // TBUFFER_STORE_FORMAT_XYZW, + appendOPR_VGPR_OR_ACCVGPR(layout.VDATA,true,false,4); + appendOPR_VGPR(layout.VADDR,true,false,2); + appendOPR_SREG(layout.SRSRC,true,false,4); + appendOPR_SSRC_NOLIT(layout.SOFFSET,true,false); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::vmcnt,0,36),true,true,true); + break; + } + } + + void InstructionDecoder_amdgpu_gfx940::finalizeENC_MUBUFOperands() + { + layout_ENC_MUBUF & layout = insn_layout.ENC_MUBUF; + switch (layout.OP) { + case 0: case 8: case 9: // BUFFER_LOAD_FORMAT_X,BUFFER_LOAD_FORMAT_D16_X,BUFFER_LOAD_FORMAT_D16_XY, + case 16: case 17: case 18: case 19: // BUFFER_LOAD_UBYTE,BUFFER_LOAD_SBYTE,BUFFER_LOAD_USHORT,BUFFER_LOAD_SSHORT, + case 20: case 32: case 33: // BUFFER_LOAD_DWORD,BUFFER_LOAD_UBYTE_D16,BUFFER_LOAD_UBYTE_D16_HI, + case 34: case 35: case 36: // BUFFER_LOAD_SBYTE_D16,BUFFER_LOAD_SBYTE_D16_HI,BUFFER_LOAD_SHORT_D16, + case 37: case 38: // BUFFER_LOAD_SHORT_D16_HI,BUFFER_LOAD_FORMAT_D16_HI_X, + appendOPR_VGPR_OR_ACCVGPR(layout.VDATA,false,true); + if (layout.IDXEN || layout.OFFEN) { + appendOPR_VGPR(layout.VADDR,true,false); + } else if (layout.OFFSET) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::off,1),false,false,false); + } + if (layout.IDXEN && layout.OFFEN) { + appendOPR_VGPR(layout.VADDR+1,true,false); + } + appendOPR_SREG(layout.SRSRC,true,false,4); + appendOPR_SSRC_NOLIT(layout.SOFFSET,true,false); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::vmcnt,0,36),true,true,true); + if (layout.IDXEN) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::idxen,1),false,false,false); + } + if (layout.OFFEN) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::offen,1),false,false,false); + } + if (layout.OFFSET) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,layout.OFFSET)),true,false,false); + } + break; + case 1: case 10: case 11: // BUFFER_LOAD_FORMAT_XY,BUFFER_LOAD_FORMAT_D16_XYZ,BUFFER_LOAD_FORMAT_D16_XYZW, + case 21: // BUFFER_LOAD_DWORDX2, + appendOPR_VGPR_OR_ACCVGPR(layout.VDATA,false,true,2); + if (layout.IDXEN || layout.OFFEN) { + appendOPR_VGPR(layout.VADDR,true,false); + } else if (layout.OFFSET) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::off,1),false,false,false); + } + if (layout.IDXEN && layout.OFFEN) { + appendOPR_VGPR(layout.VADDR+1,true,false); + } + appendOPR_SREG(layout.SRSRC,true,false,4); + appendOPR_SSRC_NOLIT(layout.SOFFSET,true,false); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::vmcnt,0,36),true,true,true); + if (layout.IDXEN) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::idxen,1),false,false,false); + } + if (layout.OFFEN) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::offen,1),false,false,false); + } + if (layout.OFFSET) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,layout.OFFSET)),true,false,false); + } + break; + case 2: case 22: // BUFFER_LOAD_FORMAT_XYZ,BUFFER_LOAD_DWORDX3, + appendOPR_VGPR_OR_ACCVGPR(layout.VDATA,false,true,3); + if (layout.IDXEN || layout.OFFEN) { + appendOPR_VGPR(layout.VADDR,true,false); + } else if (layout.OFFSET) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::off,1),false,false,false); + } + if (layout.IDXEN && layout.OFFEN) { + appendOPR_VGPR(layout.VADDR+1,true,false); + } + appendOPR_SREG(layout.SRSRC,true,false,4); + appendOPR_SSRC_NOLIT(layout.SOFFSET,true,false); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::vmcnt,0,36),true,true,true); + if (layout.IDXEN) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::idxen,1),false,false,false); + } + if (layout.OFFEN) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::offen,1),false,false,false); + } + if (layout.OFFSET) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,layout.OFFSET)),true,false,false); + } + break; + case 3: case 23: // BUFFER_LOAD_FORMAT_XYZW,BUFFER_LOAD_DWORDX4, + appendOPR_VGPR_OR_ACCVGPR(layout.VDATA,false,true,4); + if (layout.IDXEN || layout.OFFEN) { + appendOPR_VGPR(layout.VADDR,true,false); + } else if (layout.OFFSET) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::off,1),false,false,false); + } + if (layout.IDXEN && layout.OFFEN) { + appendOPR_VGPR(layout.VADDR+1,true,false); + } + appendOPR_SREG(layout.SRSRC,true,false,4); + appendOPR_SSRC_NOLIT(layout.SOFFSET,true,false); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::vmcnt,0,36),true,true,true); + if (layout.IDXEN) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::idxen,1),false,false,false); + } + if (layout.OFFEN) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::offen,1),false,false,false); + } + if (layout.OFFSET) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,layout.OFFSET)),true,false,false); + } + break; + case 4: case 12: case 13: // BUFFER_STORE_FORMAT_X,BUFFER_STORE_FORMAT_D16_X,BUFFER_STORE_FORMAT_D16_XY, + case 24: case 25: case 26: // BUFFER_STORE_BYTE,BUFFER_STORE_BYTE_D16_HI,BUFFER_STORE_SHORT, + case 27: case 28: case 39: // BUFFER_STORE_SHORT_D16_HI,BUFFER_STORE_DWORD,BUFFER_STORE_FORMAT_D16_HI_X, + appendOPR_VGPR_OR_ACCVGPR(layout.VDATA,true,false); + if (layout.IDXEN || layout.OFFEN) { + appendOPR_VGPR(layout.VADDR,true,false); + } else if (layout.OFFSET) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::off,1),false,false,false); + } + if (layout.IDXEN && layout.OFFEN) { + appendOPR_VGPR(layout.VADDR+1,true,false); + } + appendOPR_SREG(layout.SRSRC,true,false,4); + appendOPR_SSRC_NOLIT(layout.SOFFSET,true,false); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::vmcnt,0,36),true,true,true); + if (layout.IDXEN) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::idxen,1),false,false,false); + } + if (layout.OFFEN) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::offen,1),false,false,false); + } + if (layout.OFFSET) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,layout.OFFSET)),true,false,false); + } + break; + case 5: case 14: case 15: // BUFFER_STORE_FORMAT_XY,BUFFER_STORE_FORMAT_D16_XYZ,BUFFER_STORE_FORMAT_D16_XYZW, + case 29: // BUFFER_STORE_DWORDX2, + appendOPR_VGPR_OR_ACCVGPR(layout.VDATA,true,false,2); + if (layout.IDXEN || layout.OFFEN) { + appendOPR_VGPR(layout.VADDR,true,false); + } else if (layout.OFFSET) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::off,1),false,false,false); + } + if (layout.IDXEN && layout.OFFEN) { + appendOPR_VGPR(layout.VADDR+1,true,false); + } + appendOPR_SREG(layout.SRSRC,true,false,4); + appendOPR_SSRC_NOLIT(layout.SOFFSET,true,false); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::vmcnt,0,36),true,true,true); + if (layout.IDXEN) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::idxen,1),false,false,false); + } + if (layout.OFFEN) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::offen,1),false,false,false); + } + if (layout.OFFSET) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,layout.OFFSET)),true,false,false); + } + break; + case 6: case 30: // BUFFER_STORE_FORMAT_XYZ,BUFFER_STORE_DWORDX3, + appendOPR_VGPR_OR_ACCVGPR(layout.VDATA,true,false,3); + if (layout.IDXEN || layout.OFFEN) { + appendOPR_VGPR(layout.VADDR,true,false); + } else if (layout.OFFSET) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::off,1),false,false,false); + } + if (layout.IDXEN && layout.OFFEN) { + appendOPR_VGPR(layout.VADDR+1,true,false); + } + appendOPR_SREG(layout.SRSRC,true,false,4); + appendOPR_SSRC_NOLIT(layout.SOFFSET,true,false); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::vmcnt,0,36),true,true,true); + if (layout.IDXEN) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::idxen,1),false,false,false); + } + if (layout.OFFEN) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::offen,1),false,false,false); + } + if (layout.OFFSET) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,layout.OFFSET)),true,false,false); + } + break; + case 7: case 31: // BUFFER_STORE_FORMAT_XYZW,BUFFER_STORE_DWORDX4, + appendOPR_VGPR_OR_ACCVGPR(layout.VDATA,true,false,4); + if (layout.IDXEN || layout.OFFEN) { + appendOPR_VGPR(layout.VADDR,true,false); + } else if (layout.OFFSET) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::off,1),false,false,false); + } + if (layout.IDXEN && layout.OFFEN) { + appendOPR_VGPR(layout.VADDR+1,true,false); + } + appendOPR_SREG(layout.SRSRC,true,false,4); + appendOPR_SSRC_NOLIT(layout.SOFFSET,true,false); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::vmcnt,0,36),true,true,true); + if (layout.IDXEN) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::idxen,1),false,false,false); + } + if (layout.OFFEN) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::offen,1),false,false,false); + } + if (layout.OFFSET) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,layout.OFFSET)),true,false,false); + } + break; + case 40: case 41: // BUFFER_WBL2,BUFFER_INV, + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::vmcnt,0,36),true,true,true); + if (layout.IDXEN) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::idxen,1),false,false,false); + } + if (layout.OFFEN) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::offen,1),false,false,false); + } + if (layout.OFFSET) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,layout.OFFSET)),true,false,false); + } + break; + case 64: case 66: case 67: case 68: // BUFFER_ATOMIC_SWAP,BUFFER_ATOMIC_ADD,BUFFER_ATOMIC_SUB,BUFFER_ATOMIC_SMIN, + case 69: case 70: case 71: case 72: // BUFFER_ATOMIC_UMIN,BUFFER_ATOMIC_SMAX,BUFFER_ATOMIC_UMAX,BUFFER_ATOMIC_AND, + case 73: case 74: case 75: case 76: // BUFFER_ATOMIC_OR,BUFFER_ATOMIC_XOR,BUFFER_ATOMIC_INC,BUFFER_ATOMIC_DEC, + case 77: case 78: // BUFFER_ATOMIC_ADD_F32,BUFFER_ATOMIC_PK_ADD_F16, + appendOPR_VGPR_OR_ACCVGPR(layout.VDATA,true,true); + if (layout.IDXEN || layout.OFFEN) { + appendOPR_VGPR(layout.VADDR,true,false); + } else if (layout.OFFSET) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::off,1),false,false,false); + } + if (layout.IDXEN && layout.OFFEN) { + appendOPR_VGPR(layout.VADDR+1,true,false); + } + appendOPR_SREG(layout.SRSRC,true,false,4); + appendOPR_SSRC_NOLIT(layout.SOFFSET,true,false); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::vmcnt,0,36),true,true,true); + if (layout.IDXEN) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::idxen,1),false,false,false); + } + if (layout.OFFEN) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::offen,1),false,false,false); + } + if (layout.OFFSET) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,layout.OFFSET)),true,false,false); + } + break; + case 65: case 79: case 80: // BUFFER_ATOMIC_CMPSWAP,BUFFER_ATOMIC_ADD_F64,BUFFER_ATOMIC_MIN_F64, + case 81: case 96: case 98: // BUFFER_ATOMIC_MAX_F64,BUFFER_ATOMIC_SWAP_X2,BUFFER_ATOMIC_ADD_X2, + case 99: case 100: case 101: // BUFFER_ATOMIC_SUB_X2,BUFFER_ATOMIC_SMIN_X2,BUFFER_ATOMIC_UMIN_X2, + case 102: case 103: case 104: // BUFFER_ATOMIC_SMAX_X2,BUFFER_ATOMIC_UMAX_X2,BUFFER_ATOMIC_AND_X2, + case 105: case 106: case 107: // BUFFER_ATOMIC_OR_X2,BUFFER_ATOMIC_XOR_X2,BUFFER_ATOMIC_INC_X2, + case 108: // BUFFER_ATOMIC_DEC_X2, + appendOPR_VGPR_OR_ACCVGPR(layout.VDATA,true,true,2); + if (layout.IDXEN || layout.OFFEN) { + appendOPR_VGPR(layout.VADDR,true,false); + } else if (layout.OFFSET) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::off,1),false,false,false); + } + if (layout.IDXEN && layout.OFFEN) { + appendOPR_VGPR(layout.VADDR+1,true,false); + } + appendOPR_SREG(layout.SRSRC,true,false,4); + appendOPR_SSRC_NOLIT(layout.SOFFSET,true,false); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::vmcnt,0,36),true,true,true); + if (layout.IDXEN) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::idxen,1),false,false,false); + } + if (layout.OFFEN) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::offen,1),false,false,false); + } + if (layout.OFFSET) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,layout.OFFSET)),true,false,false); + } + break; + case 97: // BUFFER_ATOMIC_CMPSWAP_X2, + appendOPR_VGPR_OR_ACCVGPR(layout.VDATA,true,true,4); + if (layout.IDXEN || layout.OFFEN) { + appendOPR_VGPR(layout.VADDR,true,false); + } else if (layout.OFFSET) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::off,1),false,false,false); + } + if (layout.IDXEN && layout.OFFEN) { + appendOPR_VGPR(layout.VADDR+1,true,false); + } + appendOPR_SREG(layout.SRSRC,true,false,4); + appendOPR_SSRC_NOLIT(layout.SOFFSET,true,false); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::vmcnt,0,36),true,true,true); + if (layout.IDXEN) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::idxen,1),false,false,false); + } + if (layout.OFFEN) { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::offen,1),false,false,false); + } + if (layout.OFFSET) { + insn_in_progress->appendOperand(NamedImmediate::makeNamedImmediate(std::string("offset"),Result(u16,layout.OFFSET)),true,false,false); + } + break; + } + } + + void InstructionDecoder_amdgpu_gfx940::finalizeENC_SMEMOperands() + { + layout_ENC_SMEM & layout = insn_layout.ENC_SMEM; + switch (layout.OP) { + case 0: case 5: // S_LOAD_DWORD,S_SCRATCH_LOAD_DWORD, + appendOPR_SREG(layout.SDATA,false,true); + appendOPR_SREG(layout.SBASE,true,false,2); + processOPR_SMEM_OFFSET(layout); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::lgkmcnt,0,16),true,true,true); + break; + case 1: case 6: // S_LOAD_DWORDX2,S_SCRATCH_LOAD_DWORDX2, + appendOPR_SREG(layout.SDATA,false,true,2); + appendOPR_SREG(layout.SBASE,true,false,2); + processOPR_SMEM_OFFSET(layout); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::lgkmcnt,0,16),true,true,true); + break; + case 2: case 7: // S_LOAD_DWORDX4,S_SCRATCH_LOAD_DWORDX4, + appendOPR_SREG(layout.SDATA,false,true,4); + appendOPR_SREG(layout.SBASE,true,false,2); + processOPR_SMEM_OFFSET(layout); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::lgkmcnt,0,16),true,true,true); + break; + case 3: // S_LOAD_DWORDX8, + appendOPR_SREG(layout.SDATA,false,true,8); + appendOPR_SREG(layout.SBASE,true,false,2); + processOPR_SMEM_OFFSET(layout); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::lgkmcnt,0,16),true,true,true); + break; + case 4: // S_LOAD_DWORDX16, + appendOPR_SREG(layout.SDATA,false,true,16); + appendOPR_SREG(layout.SBASE,true,false,2); + processOPR_SMEM_OFFSET(layout); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::lgkmcnt,0,16),true,true,true); + break; + case 8: // S_BUFFER_LOAD_DWORD, + appendOPR_SREG(layout.SDATA,false,true); + appendOPR_SREG(layout.SBASE,true,false,4); + processOPR_SMEM_OFFSET(layout); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::lgkmcnt,0,16),true,true,true); + break; + case 9: // S_BUFFER_LOAD_DWORDX2, + appendOPR_SREG(layout.SDATA,false,true,2); + appendOPR_SREG(layout.SBASE,true,false,4); + processOPR_SMEM_OFFSET(layout); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::lgkmcnt,0,16),true,true,true); + break; + case 10: // S_BUFFER_LOAD_DWORDX4, + appendOPR_SREG(layout.SDATA,false,true,4); + appendOPR_SREG(layout.SBASE,true,false,4); + processOPR_SMEM_OFFSET(layout); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::lgkmcnt,0,16),true,true,true); + break; + case 11: // S_BUFFER_LOAD_DWORDX8, + appendOPR_SREG(layout.SDATA,false,true,8); + appendOPR_SREG(layout.SBASE,true,false,4); + processOPR_SMEM_OFFSET(layout); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::lgkmcnt,0,16),true,true,true); + break; + case 12: // S_BUFFER_LOAD_DWORDX16, + appendOPR_SREG(layout.SDATA,false,true,16); + appendOPR_SREG(layout.SBASE,true,false,4); + processOPR_SMEM_OFFSET(layout); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::lgkmcnt,0,16),true,true,true); + break; + case 16: case 21: // S_STORE_DWORD,S_SCRATCH_STORE_DWORD, + appendOPR_SREG(layout.SDATA,true,false); + appendOPR_SREG(layout.SBASE,true,false,2); + processOPR_SMEM_OFFSET(layout); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::lgkmcnt,0,16),true,true,true); + break; + case 17: case 22: // S_STORE_DWORDX2,S_SCRATCH_STORE_DWORDX2, + appendOPR_SREG(layout.SDATA,true,false,2); + appendOPR_SREG(layout.SBASE,true,false,2); + processOPR_SMEM_OFFSET(layout); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::lgkmcnt,0,16),true,true,true); + break; + case 18: case 23: // S_STORE_DWORDX4,S_SCRATCH_STORE_DWORDX4, + appendOPR_SREG(layout.SDATA,true,false,4); + appendOPR_SREG(layout.SBASE,true,false,2); + processOPR_SMEM_OFFSET(layout); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::lgkmcnt,0,16),true,true,true); + break; + case 24: // S_BUFFER_STORE_DWORD, + appendOPR_SREG(layout.SDATA,true,false); + appendOPR_SREG(layout.SBASE,true,false,4); + processOPR_SMEM_OFFSET(layout); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::lgkmcnt,0,16),true,true,true); + break; + case 25: // S_BUFFER_STORE_DWORDX2, + appendOPR_SREG(layout.SDATA,true,false,2); + appendOPR_SREG(layout.SBASE,true,false,4); + processOPR_SMEM_OFFSET(layout); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::lgkmcnt,0,16),true,true,true); + break; + case 26: // S_BUFFER_STORE_DWORDX4, + appendOPR_SREG(layout.SDATA,true,false,4); + appendOPR_SREG(layout.SBASE,true,false,4); + processOPR_SMEM_OFFSET(layout); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::lgkmcnt,0,16),true,true,true); + break; + case 32: case 33: case 34: case 35: // S_DCACHE_INV,S_DCACHE_WB,S_DCACHE_INV_VOL,S_DCACHE_WB_VOL, + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::lgkmcnt,0,16),true,true,true); + break; + case 36: case 37: // S_MEMTIME,S_MEMREALTIME, + appendOPR_SREG(layout.SDATA,false,true,2); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::lgkmcnt,0,16),true,true,true); + break; + case 38: // S_ATC_PROBE, + appendOPR_SIMM8(layout.SDATA,true,false); + appendOPR_SREG(layout.SBASE,true,false,2); + processOPR_SMEM_OFFSET(layout); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::lgkmcnt,0,16),true,true,true); + break; + case 39: // S_ATC_PROBE_BUFFER, + appendOPR_SIMM8(layout.SDATA,true,false); + appendOPR_SREG(layout.SBASE,true,false,4); + processOPR_SMEM_OFFSET(layout); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::lgkmcnt,0,16),true,true,true); + break; + case 40: case 41: // S_DCACHE_DISCARD,S_DCACHE_DISCARD_X2, + appendOPR_SREG(layout.SBASE,true,false,2); + processOPR_SMEM_OFFSET(layout); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::lgkmcnt,0,16),true,true,true); + break; + case 64: case 66: case 67: // S_BUFFER_ATOMIC_SWAP,S_BUFFER_ATOMIC_ADD,S_BUFFER_ATOMIC_SUB, + case 68: case 69: case 70: // S_BUFFER_ATOMIC_SMIN,S_BUFFER_ATOMIC_UMIN,S_BUFFER_ATOMIC_SMAX, + case 71: case 72: case 73: // S_BUFFER_ATOMIC_UMAX,S_BUFFER_ATOMIC_AND,S_BUFFER_ATOMIC_OR, + case 74: case 75: case 76: // S_BUFFER_ATOMIC_XOR,S_BUFFER_ATOMIC_INC,S_BUFFER_ATOMIC_DEC, + appendOPR_SREG(layout.SDATA,true,true); + appendOPR_SREG(layout.SBASE,true,false,4); + processOPR_SMEM_OFFSET(layout); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::lgkmcnt,0,16),true,true,true); + break; + case 65: case 96: case 98: // S_BUFFER_ATOMIC_CMPSWAP,S_BUFFER_ATOMIC_SWAP_X2,S_BUFFER_ATOMIC_ADD_X2, + case 99: case 100: case 101: // S_BUFFER_ATOMIC_SUB_X2,S_BUFFER_ATOMIC_SMIN_X2,S_BUFFER_ATOMIC_UMIN_X2, + case 102: case 103: case 104: // S_BUFFER_ATOMIC_SMAX_X2,S_BUFFER_ATOMIC_UMAX_X2,S_BUFFER_ATOMIC_AND_X2, + case 105: case 106: case 107: // S_BUFFER_ATOMIC_OR_X2,S_BUFFER_ATOMIC_XOR_X2,S_BUFFER_ATOMIC_INC_X2, + case 108: // S_BUFFER_ATOMIC_DEC_X2, + appendOPR_SREG(layout.SDATA,true,true,2); + appendOPR_SREG(layout.SBASE,true,false,4); + processOPR_SMEM_OFFSET(layout); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::lgkmcnt,0,16),true,true,true); + break; + case 97: // S_BUFFER_ATOMIC_CMPSWAP_X2, + appendOPR_SREG(layout.SDATA,true,true,4); + appendOPR_SREG(layout.SBASE,true,false,4); + processOPR_SMEM_OFFSET(layout); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::lgkmcnt,0,16),true,true,true); + break; + case 128: case 130: case 131: case 132: // S_ATOMIC_SWAP,S_ATOMIC_ADD,S_ATOMIC_SUB,S_ATOMIC_SMIN, + case 133: case 134: case 135: case 136: // S_ATOMIC_UMIN,S_ATOMIC_SMAX,S_ATOMIC_UMAX,S_ATOMIC_AND, + case 137: case 138: case 139: case 140: // S_ATOMIC_OR,S_ATOMIC_XOR,S_ATOMIC_INC,S_ATOMIC_DEC, + appendOPR_SREG(layout.SDATA,true,true); + appendOPR_SREG(layout.SBASE,true,false,2); + processOPR_SMEM_OFFSET(layout); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::lgkmcnt,0,16),true,true,true); + break; + case 129: case 160: case 162: case 163: // S_ATOMIC_CMPSWAP,S_ATOMIC_SWAP_X2,S_ATOMIC_ADD_X2,S_ATOMIC_SUB_X2, + case 164: case 165: case 166: case 167: // S_ATOMIC_SMIN_X2,S_ATOMIC_UMIN_X2,S_ATOMIC_SMAX_X2,S_ATOMIC_UMAX_X2, + case 168: case 169: case 170: case 171: // S_ATOMIC_AND_X2,S_ATOMIC_OR_X2,S_ATOMIC_XOR_X2,S_ATOMIC_INC_X2, + case 172: // S_ATOMIC_DEC_X2, + appendOPR_SREG(layout.SDATA,true,true,2); + appendOPR_SREG(layout.SBASE,true,false,2); + processOPR_SMEM_OFFSET(layout); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::lgkmcnt,0,16),true,true,true); + break; + case 161: // S_ATOMIC_CMPSWAP_X2, + appendOPR_SREG(layout.SDATA,true,true,4); + appendOPR_SREG(layout.SBASE,true,false,2); + processOPR_SMEM_OFFSET(layout); + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::lgkmcnt,0,16),true,true,true); + break; + } + } + + void InstructionDecoder_amdgpu_gfx940::finalizeENC_SOP1Operands() + { + layout_ENC_SOP1 & layout = insn_layout.ENC_SOP1; + switch (layout.OP) { + case 0: case 8: case 14: case 16: case 18: // S_MOV_B32,S_BREV_B32,S_FF0_I32_B32,S_FF1_I32_B32,S_FLBIT_I32_B32, + case 20: case 22: case 23: // S_FLBIT_I32,S_SEXT_I32_I8,S_SEXT_I32_I16, + appendOPR_SDST(layout.SDST,false,true); + appendOPR_SSRC(layout.SSRC0,true,false); + break; + case 1: case 9: // S_MOV_B64,S_BREV_B64, + appendOPR_SDST(layout.SDST,false,true,2); + appendOPR_SSRC(layout.SSRC0,true,false,2); + break; + case 2: // S_CMOV_B32, + appendOPR_SDST(layout.SDST,true,true); + appendOPR_SSRC(layout.SSRC0,true,false); + appendOPR_SSRC_SPECIAL_SCC(253,true,false,1,true); + break; + case 3: // S_CMOV_B64, + appendOPR_SDST(layout.SDST,true,true,2); + appendOPR_SSRC(layout.SSRC0,true,false,2); + appendOPR_SSRC_SPECIAL_SCC(253,true,false,1,true); + break; + case 4: case 6: case 10: case 12: case 40: // S_NOT_B32,S_WQM_B32,S_BCNT0_I32_B32,S_BCNT1_I32_B32,S_QUADMASK_B32, + case 48: // S_ABS_I32, + appendOPR_SDST(layout.SDST,false,true); + appendOPR_SSRC(layout.SSRC0,true,false); + appendOPR_SSRC_SPECIAL_SCC(253,false,true,1,true); + break; + case 5: case 7: case 41: // S_NOT_B64,S_WQM_B64,S_QUADMASK_B64, + appendOPR_SDST(layout.SDST,false,true,2); + appendOPR_SSRC(layout.SSRC0,true,false,2); + appendOPR_SSRC_SPECIAL_SCC(253,false,true,1,true); + break; + case 11: case 13: // S_BCNT0_I32_B64,S_BCNT1_I32_B64, + appendOPR_SDST(layout.SDST,false,true); + appendOPR_SSRC(layout.SSRC0,true,false,2); + appendOPR_SSRC_SPECIAL_SCC(253,false,true,1,true); + break; + case 15: case 17: case 19: case 21: // S_FF0_I32_B64,S_FF1_I32_B64,S_FLBIT_I32_B64,S_FLBIT_I32_I64, + appendOPR_SDST(layout.SDST,false,true); + appendOPR_SSRC(layout.SSRC0,true,false,2); + break; + case 24: case 26: // S_BITSET0_B32,S_BITSET1_B32, + appendOPR_SDST(layout.SDST,true,true); + appendOPR_SSRC(layout.SSRC0,true,false); + break; + case 25: case 27: // S_BITSET0_B64,S_BITSET1_B64, + appendOPR_SDST(layout.SDST,true,true,2); + appendOPR_SSRC(layout.SSRC0,true,false); + break; + case 28: // S_GETPC_B64, + appendOPR_SDST(layout.SDST,false,true,2); + appendOPR_PC(0,true,false,1,true); + break; + case 29: // S_SETPC_B64, + setBranch(); + setModifyPC(); + appendOPR_SREG(layout.SSRC0,true,false,2); + appendOPR_PC(0,false,true,1,true); + break; + case 30: // S_SWAPPC_B64, + setBranch(); + setModifyPC(); + appendOPR_SDST(layout.SDST,false,true,2); + appendOPR_SREG(layout.SSRC0,true,false,2); + appendOPR_PC(0,false,true,1,true); + appendOPR_PC(0,true,false,1,true); + break; + case 31: // S_RFE_B64, + appendOPR_SREG(layout.SSRC0,true,false,2); + appendOPR_PC(0,false,true,1,true); + break; + case 32: case 33: case 34: case 35: // S_AND_SAVEEXEC_B64,S_OR_SAVEEXEC_B64,S_XOR_SAVEEXEC_B64,S_ANDN2_SAVEEXEC_B64, + case 36: case 37: case 38: // S_ORN2_SAVEEXEC_B64,S_NAND_SAVEEXEC_B64,S_NOR_SAVEEXEC_B64, + case 39: case 51: case 52: // S_XNOR_SAVEEXEC_B64,S_ANDN1_SAVEEXEC_B64,S_ORN1_SAVEEXEC_B64, + case 53: case 54: // S_ANDN1_WREXEC_B64,S_ANDN2_WREXEC_B64, + appendOPR_SREG(layout.SDST,false,true,2); + appendOPR_SSRC(layout.SSRC0,true,false,2); + appendOPR_SDST_EXEC(126,false,true,1,true); + appendOPR_SSRC_SPECIAL_SCC(253,false,true,1,true); + appendOPR_SDST_EXEC(126,true,false,1,true); + break; + case 42: // S_MOVRELS_B32, + appendOPR_SDST(layout.SDST,false,true); + appendOPR_SREG(layout.SSRC0,true,false); + appendOPR_SDST_M0(124,true,false,1,true); + break; + case 43: // S_MOVRELS_B64, + appendOPR_SDST(layout.SDST,false,true,2); + appendOPR_SREG(layout.SSRC0,true,false,2); + appendOPR_SDST_M0(124,true,false,1,true); + break; + case 44: // S_MOVRELD_B32, + appendOPR_SREG(layout.SDST,false,true); + appendOPR_SSRC(layout.SSRC0,true,false); + appendOPR_SDST_M0(124,true,false,1,true); + break; + case 45: // S_MOVRELD_B64, + appendOPR_SREG(layout.SDST,false,true,2); + appendOPR_SSRC(layout.SSRC0,true,false,2); + appendOPR_SDST_M0(124,true,false,1,true); + break; + case 46: // S_CBRANCH_JOIN, + appendOPR_SREG(layout.SSRC0,true,false); + appendOPR_SDST_EXEC(126,false,true,1,true); + appendOPR_PC(0,false,true,1,true); + break; + case 50: // S_SET_GPR_IDX_IDX, + appendOPR_SSRC(layout.SSRC0,true,false); + appendOPR_SDST_M0(124,false,true,1,true); + appendOPR_SDST_M0(124,true,false,1,true); + break; + case 55: // S_BITREPLICATE_B64_B32, + appendOPR_SDST(layout.SDST,false,true,2); + appendOPR_SSRC(layout.SSRC0,true,false); + break; + } + } + + void InstructionDecoder_amdgpu_gfx940::finalizeENC_SOP2Operands() + { + layout_ENC_SOP2 & layout = insn_layout.ENC_SOP2; + switch (layout.OP) { + case 0: case 1: case 2: case 3: case 6: case 7: // S_ADD_U32,S_SUB_U32,S_ADD_I32,S_SUB_I32,S_MIN_I32,S_MIN_U32, + case 8: case 9: case 12: case 14: case 16: // S_MAX_I32,S_MAX_U32,S_AND_B32,S_OR_B32,S_XOR_B32, + case 18: case 20: case 22: case 24: case 26: // S_ANDN2_B32,S_ORN2_B32,S_NAND_B32,S_NOR_B32,S_XNOR_B32, + case 28: case 30: case 32: case 37: case 38: // S_LSHL_B32,S_LSHR_B32,S_ASHR_I32,S_BFE_U32,S_BFE_I32, + case 42: case 46: case 47: case 48: // S_ABSDIFF_I32,S_LSHL1_ADD_U32,S_LSHL2_ADD_U32,S_LSHL3_ADD_U32, + case 49: // S_LSHL4_ADD_U32, + appendOPR_SDST(layout.SDST,false,true); + appendOPR_SSRC(layout.SSRC0,true,false); + appendOPR_SSRC(layout.SSRC1,true,false); + appendOPR_SSRC_SPECIAL_SCC(253,false,true,1,true); + break; + case 4: case 5: // S_ADDC_U32,S_SUBB_U32, + appendOPR_SDST(layout.SDST,false,true); + appendOPR_SSRC(layout.SSRC0,true,false); + appendOPR_SSRC(layout.SSRC1,true,false); + appendOPR_SSRC_SPECIAL_SCC(253,false,true,1,true); + appendOPR_SSRC_SPECIAL_SCC(253,true,false,1,true); + break; + case 10: // S_CSELECT_B32, + appendOPR_SDST(layout.SDST,false,true); + appendOPR_SSRC(layout.SSRC0,true,false); + appendOPR_SSRC(layout.SSRC1,true,false); + appendOPR_SSRC_SPECIAL_SCC(253,true,false,1,true); + break; + case 11: // S_CSELECT_B64, + appendOPR_SDST(layout.SDST,false,true,2); + appendOPR_SSRC(layout.SSRC0,true,false,2); + appendOPR_SSRC(layout.SSRC1,true,false,2); + appendOPR_SSRC_SPECIAL_SCC(253,true,false,1,true); + break; + case 13: case 15: case 17: case 19: case 21: // S_AND_B64,S_OR_B64,S_XOR_B64,S_ANDN2_B64,S_ORN2_B64, + case 23: case 25: case 27: // S_NAND_B64,S_NOR_B64,S_XNOR_B64, + appendOPR_SDST(layout.SDST,false,true,2); + appendOPR_SSRC(layout.SSRC0,true,false,2); + appendOPR_SSRC(layout.SSRC1,true,false,2); + appendOPR_SSRC_SPECIAL_SCC(253,false,true,1,true); + break; + case 29: case 31: case 33: case 39: case 40: // S_LSHL_B64,S_LSHR_B64,S_ASHR_I64,S_BFE_U64,S_BFE_I64, + appendOPR_SDST(layout.SDST,false,true,2); + appendOPR_SSRC(layout.SSRC0,true,false,2); + appendOPR_SSRC(layout.SSRC1,true,false); + appendOPR_SSRC_SPECIAL_SCC(253,false,true,1,true); + break; + case 34: case 36: case 44: case 45: case 50: // S_BFM_B32,S_MUL_I32,S_MUL_HI_U32,S_MUL_HI_I32,S_PACK_LL_B32_B16, + case 51: case 52: // S_PACK_LH_B32_B16,S_PACK_HH_B32_B16, + appendOPR_SDST(layout.SDST,false,true); + appendOPR_SSRC(layout.SSRC0,true,false); + appendOPR_SSRC(layout.SSRC1,true,false); + break; + case 35: // S_BFM_B64, + appendOPR_SDST(layout.SDST,false,true,2); + appendOPR_SSRC(layout.SSRC0,true,false); + appendOPR_SSRC(layout.SSRC1,true,false); + break; + case 41: // S_CBRANCH_G_FORK, + appendOPR_SSRC_NOLIT(layout.SSRC0,true,false,2); + appendOPR_SSRC_NOLIT(layout.SSRC1,true,false,2); + appendOPR_PC(0,false,true,1,true); + break; + case 43: // S_RFE_RESTORE_B64, + appendOPR_SSRC(layout.SSRC0,true,false,2); + appendOPR_SSRC(layout.SSRC1,true,false); + appendOPR_PC(0,false,true,1,true); + break; + } + } + + void InstructionDecoder_amdgpu_gfx940::finalizeENC_SOPCOperands() + { + layout_ENC_SOPC & layout = insn_layout.ENC_SOPC; + switch (layout.OP) { + case 0: case 1: case 2: case 3: case 4: // S_CMP_EQ_I32,S_CMP_LG_I32,S_CMP_GT_I32,S_CMP_GE_I32,S_CMP_LT_I32, + case 5: case 6: case 7: case 8: case 9: // S_CMP_LE_I32,S_CMP_EQ_U32,S_CMP_LG_U32,S_CMP_GT_U32,S_CMP_GE_U32, + case 10: case 11: case 12: case 13: // S_CMP_LT_U32,S_CMP_LE_U32,S_BITCMP0_B32,S_BITCMP1_B32, + appendOPR_SSRC(layout.SSRC0,true,false); + appendOPR_SSRC(layout.SSRC1,true,false); + appendOPR_SSRC_SPECIAL_SCC(253,false,true,1,true); + break; + case 14: case 15: // S_BITCMP0_B64,S_BITCMP1_B64, + appendOPR_SSRC(layout.SSRC0,true,false,2); + appendOPR_SSRC(layout.SSRC1,true,false); + appendOPR_SSRC_SPECIAL_SCC(253,false,true,1,true); + break; + case 16: // S_SETVSKIP, + appendOPR_SSRC(layout.SSRC0,true,false); + appendOPR_SSRC(layout.SSRC1,true,false); + break; + case 17: // S_SET_GPR_IDX_ON, + appendOPR_SSRC(layout.SSRC0,true,false); + appendOPR_SIMM4(layout.SSRC1,true,false); + appendOPR_SDST_M0(124,false,true,1,true); + appendOPR_SDST_M0(124,true,false,1,true); + break; + case 18: case 19: // S_CMP_EQ_U64,S_CMP_LG_U64, + appendOPR_SSRC(layout.SSRC0,true,false,2); + appendOPR_SSRC(layout.SSRC1,true,false,2); + appendOPR_SSRC_SPECIAL_SCC(253,false,true,1,true); + break; + } + } + + void InstructionDecoder_amdgpu_gfx940::finalizeENC_SOPKOperands() + { + layout_ENC_SOPK & layout = insn_layout.ENC_SOPK; + switch (layout.OP) { + case 0: case 17: // S_MOVK_I32,S_GETREG_B32, + appendOPR_SDST(layout.SDST,false,true); + appendOPR_SIMM16(layout.SIMM16,true,false); + break; + case 1: // S_CMOVK_I32, + appendOPR_SDST(layout.SDST,true,true); + appendOPR_SIMM16(layout.SIMM16,true,false); + appendOPR_SSRC_SPECIAL_SCC(253,true,false,1,true); + break; + case 2: case 3: case 4: case 5: case 6: // S_CMPK_EQ_I32,S_CMPK_LG_I32,S_CMPK_GT_I32,S_CMPK_GE_I32,S_CMPK_LT_I32, + case 7: case 8: case 9: case 10: case 11: // S_CMPK_LE_I32,S_CMPK_EQ_U32,S_CMPK_LG_U32,S_CMPK_GT_U32,S_CMPK_GE_U32, + case 12: case 13: // S_CMPK_LT_U32,S_CMPK_LE_U32, + appendOPR_SDST(layout.SDST,true,false); + appendOPR_SIMM16(layout.SIMM16,true,false); + appendOPR_SSRC_SPECIAL_SCC(253,false,true,1,true); + break; + case 14: // S_ADDK_I32, + appendOPR_SDST(layout.SDST,true,true); + appendOPR_SIMM16(layout.SIMM16,true,false); + appendOPR_SSRC_SPECIAL_SCC(253,false,true,1,true); + break; + case 15: // S_MULK_I32, + appendOPR_SDST(layout.SDST,true,true); + appendOPR_SIMM16(layout.SIMM16,true,false); + break; + case 16: // S_CBRANCH_I_FORK, + appendOPR_SDST(layout.SDST,true,false,2); + insn_in_progress->appendOperand(decodeOPR_LABEL(layout.SIMM16),true,false); + break; + case 18: // S_SETREG_B32, + appendOPR_SIMM16(layout.SIMM16,false,true); + appendOPR_SDST(layout.SDST,true,false); + break; + case 21: // S_CALL_B64, + appendOPR_SDST(layout.SDST,false,true,2); + insn_in_progress->appendOperand(decodeOPR_LABEL(layout.SIMM16),true,false); + appendOPR_PC(0,false,true,1,true); + appendOPR_PC(0,true,false,1,true); + break; + } + } + + void InstructionDecoder_amdgpu_gfx940::finalizeENC_SOPPOperands() + { + layout_ENC_SOPP & layout = insn_layout.ENC_SOPP; + switch (layout.OP) { + case 0: case 11: case 13: case 14: case 15: case 18: // S_NOP,S_SETKILL,S_SETHALT,S_SLEEP,S_SETPRIO,S_TRAP, + case 20: case 21: case 31: // S_INCPERFLEVEL,S_DECPERFLEVEL,S_SET_VALU_COEXEC_MODE, + appendOPR_SIMM16(layout.SIMM16,true,false); + break; + case 1: case 3: case 10: case 19: case 27: // S_ENDPGM,S_WAKEUP,S_BARRIER,S_ICACHE_INV,S_ENDPGM_SAVED, + case 28: case 30: // S_SET_GPR_IDX_OFF,S_ENDPGM_ORDERED_PS_DONE, + break; + case 2: // S_BRANCH, + setBranch(); + makeBranchTarget(isCall,isConditional,layout.SIMM16); + break; + case 4: case 5: // S_CBRANCH_SCC0,S_CBRANCH_SCC1, + setBranch(); + setConditionalBranch(); + makeBranchTarget(isCall,isConditional,layout.SIMM16); + appendOPR_SSRC_SPECIAL_SCC(253,true,false,1,true); + break; + case 6: case 7: // S_CBRANCH_VCCZ,S_CBRANCH_VCCNZ, + setBranch(); + setConditionalBranch(); + makeBranchTarget(isCall,isConditional,layout.SIMM16); + appendOPR_VCC(0,true,false,1,true); + break; + case 8: case 9: // S_CBRANCH_EXECZ,S_CBRANCH_EXECNZ, + setBranch(); + setConditionalBranch(); + makeBranchTarget(isCall,isConditional,layout.SIMM16); + appendOPR_SDST_EXEC(126,true,false,1,true); + break; + case 12: // S_WAITCNT, + { + uint32_t vmcnt = ((0x3& (layout.SIMM16 >>14))<<4) | (layout.SIMM16 & 0xf); + uint32_t expcnt = ((layout.SIMM16>>4) & 0x7); + uint32_t lgkmcnt = ((layout.SIMM16>>8) & 0xf); + if (vmcnt != 0x3f) + { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::vmcnt,0,32),false,true); + insn_in_progress->appendOperand(Immediate::makeImmediate(Result(u32,vmcnt)),false,false); + } + if (expcnt != 0x7) + { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::expcnt,0,32),false,true); + insn_in_progress->appendOperand(Immediate::makeImmediate(Result(u32,expcnt)),false,false); + } + if (lgkmcnt != 0xf) + { + insn_in_progress->appendOperand(makeRegisterExpression(amdgpu_gfx940::lgkmcnt,0,32),false,true); + insn_in_progress->appendOperand(Immediate::makeImmediate(Result(u32,lgkmcnt)),false,false); + } + } + break; + case 16: case 17: // S_SENDMSG,S_SENDMSGHALT, + appendOPR_SIMM16(layout.SIMM16,true,false); + appendOPR_SDST_M0(124,true,false,1,true); + break; + case 22: // S_TTRACEDATA, + appendOPR_SDST_M0(124,true,false,1,true); + break; + case 23: case 24: case 25: // S_CBRANCH_CDBGSYS,S_CBRANCH_CDBGUSER,S_CBRANCH_CDBGSYS_OR_USER, + case 26: // S_CBRANCH_CDBGSYS_AND_USER, + insn_in_progress->appendOperand(decodeOPR_LABEL(layout.SIMM16),true,false); + break; + case 29: // S_SET_GPR_IDX_MODE, + appendOPR_SIMM16(layout.SIMM16,true,false); + appendOPR_SDST_M0(124,false,true,1,true); + appendOPR_SDST_M0(124,true,false,1,true); + break; + } + } + + void InstructionDecoder_amdgpu_gfx940::finalizeENC_VOP1Operands() + { + layout_ENC_VOP1 & layout = insn_layout.ENC_VOP1; + switch (layout.OP) { + case 0: case 53: // V_NOP,V_CLREXCP, + break; + case 1: case 5: case 6: case 7: case 8: // V_MOV_B32,V_CVT_F32_I32,V_CVT_F32_U32,V_CVT_U32_F32,V_CVT_I32_F32, + case 10: case 11: case 12: case 13: // V_CVT_F16_F32,V_CVT_F32_F16,V_CVT_RPI_I32_F32,V_CVT_FLR_I32_F32, + case 14: case 17: case 18: case 19: // V_CVT_OFF_F32_I4,V_CVT_F32_UBYTE0,V_CVT_F32_UBYTE1,V_CVT_F32_UBYTE2, + case 20: case 27: case 28: case 29: case 30: // V_CVT_F32_UBYTE3,V_FRACT_F32,V_TRUNC_F32,V_CEIL_F32,V_RNDNE_F32, + case 31: case 32: case 33: case 34: case 35: // V_FLOOR_F32,V_EXP_F32,V_LOG_F32,V_RCP_F32,V_RCP_IFLAG_F32, + case 36: case 39: case 41: case 42: case 43: // V_RSQ_F32,V_SQRT_F32,V_SIN_F32,V_COS_F32,V_NOT_B32, + case 44: case 45: case 46: case 47: case 51: // V_BFREV_B32,V_FFBH_U32,V_FFBL_B32,V_FFBH_I32,V_FREXP_EXP_I32_F32, + case 52: case 55: case 57: case 58: // V_FREXP_MANT_F32,V_SCREEN_PARTITION_4SE_B32,V_CVT_F16_U16,V_CVT_F16_I16, + case 59: case 60: case 61: case 62: case 63: // V_CVT_U16_F16,V_CVT_I16_F16,V_RCP_F16,V_SQRT_F16,V_RSQ_F16, + case 64: case 65: case 66: case 67: // V_LOG_F16,V_EXP_F16,V_FREXP_MANT_F16,V_FREXP_EXP_I16_F16, + case 68: case 69: case 70: case 71: case 72: // V_FLOOR_F16,V_CEIL_F16,V_TRUNC_F16,V_RNDNE_F16,V_FRACT_F16, + case 73: case 74: case 75: case 76: // V_SIN_F16,V_COS_F16,V_EXP_LEGACY_F32,V_LOG_LEGACY_F32, + case 77: case 78: case 79: case 84: // V_CVT_NORM_I16_F16,V_CVT_NORM_U16_F16,V_SAT_PK_U8_I16,V_CVT_F32_FP8, + case 85: // V_CVT_F32_BF8, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_SRC(layout.SRC0,true,false); + break; + case 2: // V_READFIRSTLANE_B32, + appendOPR_SREG_NOVCC(layout.VDST,false,true); + appendOPR_VGPR_OR_LDS(layout.SRC0,true,false); + break; + case 3: case 15: case 21: case 48: // V_CVT_I32_F64,V_CVT_F32_F64,V_CVT_U32_F64,V_FREXP_EXP_I32_F64, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_SRC(layout.SRC0,true,false,2); + break; + case 4: case 16: case 22: case 86: // V_CVT_F64_I32,V_CVT_F64_F32,V_CVT_F64_U32,V_CVT_PK_F32_FP8, + case 87: // V_CVT_PK_F32_BF8, + appendOPR_VGPR(layout.VDST,false,true,2); + appendOPR_SRC(layout.SRC0,true,false); + break; + case 23: case 24: case 25: case 26: case 37: // V_TRUNC_F64,V_CEIL_F64,V_RNDNE_F64,V_FLOOR_F64,V_RCP_F64, + case 38: case 40: case 49: case 50: case 56: // V_RSQ_F64,V_SQRT_F64,V_FREXP_MANT_F64,V_FRACT_F64,V_MOV_B64, + appendOPR_VGPR(layout.VDST,false,true,2); + appendOPR_SRC(layout.SRC0,true,false,2); + break; + case 81: // V_SWAP_B32, + appendOPR_VGPR(layout.VDST,true,true); + appendOPR_SRC_VGPR(layout.SRC0,true,true); + break; + case 82: // V_ACCVGPR_MOV_B32, + appendOPR_ACCVGPR(layout.VDST,false,true); + appendOPR_SRC_ACCVGPR(layout.SRC0,true,false); + break; + } + } + + void InstructionDecoder_amdgpu_gfx940::finalizeENC_VOP3Operands() + { + layout_ENC_VOP3 & layout = insn_layout.ENC_VOP3; + switch (layout.OP) { + case 320: case 373: // V_NOP,V_CLREXCP, + break; + case 321: case 325: case 326: case 327: // V_MOV_B32,V_CVT_F32_I32,V_CVT_F32_U32,V_CVT_U32_F32, + case 328: case 330: case 331: case 332: // V_CVT_I32_F32,V_CVT_F16_F32,V_CVT_F32_F16,V_CVT_RPI_I32_F32, + case 333: case 334: case 337: case 338: // V_CVT_FLR_I32_F32,V_CVT_OFF_F32_I4,V_CVT_F32_UBYTE0,V_CVT_F32_UBYTE1, + case 339: case 340: case 347: case 348: // V_CVT_F32_UBYTE2,V_CVT_F32_UBYTE3,V_FRACT_F32,V_TRUNC_F32, + case 349: case 350: case 351: case 352: case 353: // V_CEIL_F32,V_RNDNE_F32,V_FLOOR_F32,V_EXP_F32,V_LOG_F32, + case 354: case 355: case 356: case 359: case 361: // V_RCP_F32,V_RCP_IFLAG_F32,V_RSQ_F32,V_SQRT_F32,V_SIN_F32, + case 362: case 363: case 364: case 365: case 366: // V_COS_F32,V_NOT_B32,V_BFREV_B32,V_FFBH_U32,V_FFBL_B32, + case 367: case 371: case 372: // V_FFBH_I32,V_FREXP_EXP_I32_F32,V_FREXP_MANT_F32, + case 375: case 377: case 378: case 379: // V_SCREEN_PARTITION_4SE_B32,V_CVT_F16_U16,V_CVT_F16_I16,V_CVT_U16_F16, + case 380: case 381: case 382: case 383: case 384: // V_CVT_I16_F16,V_RCP_F16,V_SQRT_F16,V_RSQ_F16,V_LOG_F16, + case 385: case 386: case 387: case 388: // V_EXP_F16,V_FREXP_MANT_F16,V_FREXP_EXP_I16_F16,V_FLOOR_F16, + case 389: case 390: case 391: case 392: case 393: // V_CEIL_F16,V_TRUNC_F16,V_RNDNE_F16,V_FRACT_F16,V_SIN_F16, + case 394: case 395: case 396: case 397: // V_COS_F16,V_EXP_LEGACY_F32,V_LOG_LEGACY_F32,V_CVT_NORM_I16_F16, + case 398: case 399: case 404: case 405: // V_CVT_NORM_U16_F16,V_SAT_PK_U8_I16,V_CVT_F32_FP8,V_CVT_F32_BF8, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_SRC_NOLIT(layout.SRC0,true,false); + break; + case 322: // V_READFIRSTLANE_B32, + appendOPR_SREG_NOVCC(layout.VDST,false,true); + appendOPR_VGPR_OR_LDS(layout.SRC0,true,false); + break; + case 323: case 335: case 341: case 368: // V_CVT_I32_F64,V_CVT_F32_F64,V_CVT_U32_F64,V_FREXP_EXP_I32_F64, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_SRC_NOLIT(layout.SRC0,true,false,2); + break; + case 324: case 336: case 342: case 406: // V_CVT_F64_I32,V_CVT_F64_F32,V_CVT_F64_U32,V_CVT_PK_F32_FP8, + case 407: // V_CVT_PK_F32_BF8, + appendOPR_VGPR(layout.VDST,false,true,2); + appendOPR_SRC_NOLIT(layout.SRC0,true,false); + break; + case 343: case 344: case 345: case 346: case 357: // V_TRUNC_F64,V_CEIL_F64,V_RNDNE_F64,V_FLOOR_F64,V_RCP_F64, + case 358: case 360: case 369: case 370: case 376: // V_RSQ_F64,V_SQRT_F64,V_FREXP_MANT_F64,V_FRACT_F64,V_MOV_B64, + appendOPR_VGPR(layout.VDST,false,true,2); + appendOPR_SRC_NOLIT(layout.SRC0,true,false,2); + break; + case 401: // V_SWAP_B32, + appendOPR_VGPR(layout.VDST,true,true); + appendOPR_SRC_VGPR(layout.SRC0,true,true); + break; + case 402: // V_ACCVGPR_MOV_B32, + appendOPR_ACCVGPR(layout.VDST,false,true); + appendOPR_SRC_ACCVGPR(layout.SRC0,true,false); + break; + case 256: // V_CNDMASK_B32, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_SRC_NOLIT(layout.SRC0,true,false); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false); + appendOPR_SREG(layout.SRC2,true,false,2); + break; + case 257: case 258: case 259: case 261: case 262: // V_ADD_F32,V_SUB_F32,V_SUBREV_F32,V_MUL_F32,V_MUL_I32_I24, + case 263: case 264: case 265: case 266: // V_MUL_HI_I32_I24,V_MUL_U32_U24,V_MUL_HI_U32_U24,V_MIN_F32, + case 267: case 268: case 269: case 270: case 271: // V_MAX_F32,V_MIN_I32,V_MAX_I32,V_MIN_U32,V_MAX_U32, + case 275: case 276: case 277: case 287: case 288: // V_AND_B32,V_OR_B32,V_XOR_B32,V_ADD_F16,V_SUB_F16, + case 290: case 294: case 295: case 297: case 301: // V_MUL_F16,V_ADD_U16,V_SUB_U16,V_MUL_LO_U16,V_MAX_F16, + case 302: case 303: case 304: case 305: case 306: // V_MIN_F16,V_MAX_U16,V_MAX_I16,V_MIN_U16,V_MIN_I16, + case 307: case 308: case 309: case 317: case 645: // V_LDEXP_F16,V_ADD_U32,V_SUB_U32,V_XNOR_B32,V_MUL_LO_U32, + case 646: case 647: case 648: case 651: // V_MUL_HI_U32,V_MUL_HI_I32,V_LDEXP_F32,V_BCNT_U32_B32, + case 652: case 653: case 659: case 660: // V_MBCNT_LO_U32_B32,V_MBCNT_HI_U32_B32,V_BFM_B32,V_CVT_PKNORM_I16_F32, + case 661: case 662: case 663: // V_CVT_PKNORM_U16_F32,V_CVT_PKRTZ_F16_F32,V_CVT_PK_U16_U32, + case 664: case 665: case 666: case 668: // V_CVT_PK_I16_I32,V_CVT_PKNORM_I16_F16,V_CVT_PKNORM_U16_F16,V_ADD_I32, + case 669: case 670: case 671: case 672: case 673: // V_SUB_I32,V_ADD_I16,V_SUB_I16,V_PACK_B32_F16,V_MUL_LEGACY_F32, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_SRC_NOLIT(layout.SRC0,true,false); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false); + break; + case 260: // V_FMAC_F64, + appendOPR_VGPR(layout.VDST,true,true,2); + appendOPR_SRC_NOLIT(layout.SRC0,true,false,2); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false,2); + break; + case 272: case 273: case 274: case 289: // V_LSHRREV_B32,V_ASHRREV_I32,V_LSHLREV_B32,V_SUBREV_F16, + case 296: case 298: case 299: case 300: // V_SUBREV_U16,V_LSHLREV_B16,V_LSHRREV_B16,V_ASHRREV_I16, + case 310: // V_SUBREV_U32, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_SRC_SIMPLE(layout.SRC0,true,false); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false); + break; + case 291: case 311: case 312: case 313: // V_MAC_F16,V_DOT2C_F32_F16,V_DOT2C_I32_I16,V_DOT4C_I32_I8, + case 314: case 315: case 316: case 496: // V_DOT8C_I32_I4,V_FMAC_F32,V_PK_FMAC_F16,V_CVT_PKACCUM_U8_F32, + case 674: case 675: case 676: case 677: // V_CVT_PK_FP8_F32,V_CVT_PK_BF8_F32,V_CVT_SR_FP8_F32,V_CVT_SR_BF8_F32, + appendOPR_VGPR(layout.VDST,true,true); + appendOPR_SRC_NOLIT(layout.SRC0,true,false); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false); + break; + case 450: case 451: case 452: case 453: // V_MAD_I32_I24,V_MAD_U32_U24,V_CUBEID_F32,V_CUBESC_F32, + case 454: case 455: case 456: case 457: case 458: // V_CUBETC_F32,V_CUBEMA_F32,V_BFE_U32,V_BFE_I32,V_BFI_B32, + case 459: case 461: case 462: case 463: case 464: // V_FMA_F32,V_LERP_U8,V_ALIGNBIT_B32,V_ALIGNBYTE_B32,V_MIN3_F32, + case 465: case 466: case 467: case 468: case 469: // V_MIN3_I32,V_MIN3_U32,V_MAX3_F32,V_MAX3_I32,V_MAX3_U32, + case 470: case 471: case 472: case 473: case 474: // V_MED3_F32,V_MED3_I32,V_MED3_U32,V_SAD_U8,V_SAD_HI_U8, + case 475: case 476: case 477: case 478: case 484: // V_SAD_U16,V_SAD_U32,V_CVT_PK_U8_F32,V_DIV_FIXUP_F32,V_MSAD_U8, + case 490: case 491: case 492: case 493: // V_MAD_LEGACY_F16,V_MAD_LEGACY_U16,V_MAD_LEGACY_I16,V_PERM_B32, + case 494: case 495: case 497: case 498: // V_FMA_LEGACY_F16,V_DIV_FIXUP_LEGACY_F16,V_MAD_U32_U16,V_MAD_I32_I16, + case 499: case 500: case 501: case 502: case 503: // V_XAD_U32,V_MIN3_F16,V_MIN3_I16,V_MIN3_U16,V_MAX3_F16, + case 504: case 505: case 506: case 507: case 508: // V_MAX3_I16,V_MAX3_U16,V_MED3_F16,V_MED3_I16,V_MED3_U16, + case 509: case 510: case 511: case 512: // V_LSHL_ADD_U32,V_ADD_LSHL_U32,V_ADD3_U32,V_LSHL_OR_B32, + case 513: case 514: case 515: case 516: case 517: // V_AND_OR_B32,V_OR3_B32,V_MAD_F16,V_MAD_U16,V_MAD_I16, + case 518: case 519: // V_FMA_F16,V_DIV_FIXUP_F16, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_SRC_NOLIT(layout.SRC0,true,false); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false); + appendOPR_SRC_SIMPLE(layout.SRC2,true,false); + break; + case 460: case 479: // V_FMA_F64,V_DIV_FIXUP_F64, + appendOPR_VGPR(layout.VDST,false,true,2); + appendOPR_SRC_NOLIT(layout.SRC0,true,false,2); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false,2); + appendOPR_SRC_SIMPLE(layout.SRC2,true,false,2); + break; + case 482: // V_DIV_FMAS_F32, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_SRC_NOLIT(layout.SRC0,true,false); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false); + appendOPR_SRC_SIMPLE(layout.SRC2,true,false); + appendOPR_VCC(0,true,false,1,true); + break; + case 483: // V_DIV_FMAS_F64, + appendOPR_VGPR(layout.VDST,false,true,2); + appendOPR_SRC_NOLIT(layout.SRC0,true,false,2); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false,2); + appendOPR_SRC_SIMPLE(layout.SRC2,true,false,2); + appendOPR_VCC(0,true,false,1,true); + break; + case 485: case 486: case 520: // V_QSAD_PK_U16_U8,V_MQSAD_PK_U16_U8,V_LSHL_ADD_U64, + appendOPR_VGPR(layout.VDST,false,true,2); + appendOPR_SRC_NOLIT(layout.SRC0,true,false,2); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false); + appendOPR_SRC_SIMPLE(layout.SRC2,true,false,2); + break; + case 487: // V_MQSAD_U32_U8, + appendOPR_VGPR(layout.VDST,false,true,4); + appendOPR_SRC_NOLIT(layout.SRC0,true,false,2); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false); + appendOPR_SRC_VGPR(layout.SRC2,true,false,4); + break; + case 640: case 641: case 642: case 643: // V_ADD_F64,V_MUL_F64,V_MIN_F64,V_MAX_F64, + appendOPR_VGPR(layout.VDST,false,true,2); + appendOPR_SRC_NOLIT(layout.SRC0,true,false,2); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false,2); + break; + case 644: case 658: // V_LDEXP_F64,V_TRIG_PREOP_F64, + appendOPR_VGPR(layout.VDST,false,true,2); + appendOPR_SRC_NOLIT(layout.SRC0,true,false,2); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false); + break; + case 649: // V_READLANE_B32, + appendOPR_SREG_NOVCC(layout.VDST,false,true); + appendOPR_VGPR_OR_LDS(layout.SRC0,true,false); + appendOPR_SSRC_LANESEL(layout.SRC1,true,false); + break; + case 650: // V_WRITELANE_B32, + appendOPR_VGPR(layout.VDST,true,true); + appendOPR_SSRC_NOLIT(layout.SRC0,true,false); + appendOPR_SSRC_LANESEL(layout.SRC1,true,false); + break; + case 655: case 656: case 657: // V_LSHLREV_B64,V_LSHRREV_B64,V_ASHRREV_I64, + appendOPR_VGPR(layout.VDST,false,true,2); + appendOPR_SRC_SIMPLE(layout.SRC0,true,false); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false,2); + break; + case 16: case 20: case 32: case 33: // V_CMP_CLASS_F32,V_CMP_CLASS_F16,V_CMP_F_F16,V_CMP_LT_F16, + case 34: case 35: case 36: case 37: case 38: // V_CMP_EQ_F16,V_CMP_LE_F16,V_CMP_GT_F16,V_CMP_LG_F16,V_CMP_GE_F16, + case 39: case 40: case 41: case 42: case 43: // V_CMP_O_F16,V_CMP_U_F16,V_CMP_NGE_F16,V_CMP_NLG_F16,V_CMP_NGT_F16, + case 44: case 45: case 46: case 47: case 64: // V_CMP_NLE_F16,V_CMP_NEQ_F16,V_CMP_NLT_F16,V_CMP_TRU_F16,V_CMP_F_F32, + case 65: case 66: case 67: case 68: case 69: // V_CMP_LT_F32,V_CMP_EQ_F32,V_CMP_LE_F32,V_CMP_GT_F32,V_CMP_LG_F32, + case 70: case 71: case 72: case 73: case 74: // V_CMP_GE_F32,V_CMP_O_F32,V_CMP_U_F32,V_CMP_NGE_F32,V_CMP_NLG_F32, + case 75: case 76: case 77: case 78: // V_CMP_NGT_F32,V_CMP_NLE_F32,V_CMP_NEQ_F32,V_CMP_NLT_F32, + case 79: case 160: case 161: case 162: // V_CMP_TRU_F32,V_CMP_F_I16,V_CMP_LT_I16,V_CMP_EQ_I16, + case 163: case 164: case 165: case 166: // V_CMP_LE_I16,V_CMP_GT_I16,V_CMP_NE_I16,V_CMP_GE_I16, + case 167: case 168: case 169: case 170: case 171: // V_CMP_T_I16,V_CMP_F_U16,V_CMP_LT_U16,V_CMP_EQ_U16,V_CMP_LE_U16, + case 172: case 173: case 174: case 175: case 192: // V_CMP_GT_U16,V_CMP_NE_U16,V_CMP_GE_U16,V_CMP_T_U16,V_CMP_F_I32, + case 193: case 194: case 195: case 196: // V_CMP_LT_I32,V_CMP_EQ_I32,V_CMP_LE_I32,V_CMP_GT_I32, + case 197: case 198: case 199: case 200: case 201: // V_CMP_NE_I32,V_CMP_GE_I32,V_CMP_T_I32,V_CMP_F_U32,V_CMP_LT_U32, + case 202: case 203: case 204: case 205: // V_CMP_EQ_U32,V_CMP_LE_U32,V_CMP_GT_U32,V_CMP_NE_U32, + case 206: case 207: // V_CMP_GE_U32,V_CMP_T_U32, + appendOPR_SREG(layout.VDST,false,true,2); + appendOPR_SRC_NOLIT(layout.SRC0,true,false); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false); + break; + case 17: case 21: case 48: case 49: // V_CMPX_CLASS_F32,V_CMPX_CLASS_F16,V_CMPX_F_F16,V_CMPX_LT_F16, + case 50: case 51: case 52: case 53: // V_CMPX_EQ_F16,V_CMPX_LE_F16,V_CMPX_GT_F16,V_CMPX_LG_F16, + case 54: case 55: case 56: case 57: // V_CMPX_GE_F16,V_CMPX_O_F16,V_CMPX_U_F16,V_CMPX_NGE_F16, + case 58: case 59: case 60: case 61: // V_CMPX_NLG_F16,V_CMPX_NGT_F16,V_CMPX_NLE_F16,V_CMPX_NEQ_F16, + case 62: case 63: case 80: case 81: // V_CMPX_NLT_F16,V_CMPX_TRU_F16,V_CMPX_F_F32,V_CMPX_LT_F32, + case 82: case 83: case 84: case 85: // V_CMPX_EQ_F32,V_CMPX_LE_F32,V_CMPX_GT_F32,V_CMPX_LG_F32, + case 86: case 87: case 88: case 89: // V_CMPX_GE_F32,V_CMPX_O_F32,V_CMPX_U_F32,V_CMPX_NGE_F32, + case 90: case 91: case 92: case 93: // V_CMPX_NLG_F32,V_CMPX_NGT_F32,V_CMPX_NLE_F32,V_CMPX_NEQ_F32, + case 94: case 95: case 176: case 177: // V_CMPX_NLT_F32,V_CMPX_TRU_F32,V_CMPX_F_I16,V_CMPX_LT_I16, + case 178: case 179: case 180: case 181: // V_CMPX_EQ_I16,V_CMPX_LE_I16,V_CMPX_GT_I16,V_CMPX_NE_I16, + case 182: case 183: case 184: case 185: // V_CMPX_GE_I16,V_CMPX_T_I16,V_CMPX_F_U16,V_CMPX_LT_U16, + case 186: case 187: case 188: case 189: // V_CMPX_EQ_U16,V_CMPX_LE_U16,V_CMPX_GT_U16,V_CMPX_NE_U16, + case 190: case 191: case 208: case 209: // V_CMPX_GE_U16,V_CMPX_T_U16,V_CMPX_F_I32,V_CMPX_LT_I32, + case 210: case 211: case 212: case 213: // V_CMPX_EQ_I32,V_CMPX_LE_I32,V_CMPX_GT_I32,V_CMPX_NE_I32, + case 214: case 215: case 216: case 217: // V_CMPX_GE_I32,V_CMPX_T_I32,V_CMPX_F_U32,V_CMPX_LT_U32, + case 218: case 219: case 220: case 221: // V_CMPX_EQ_U32,V_CMPX_LE_U32,V_CMPX_GT_U32,V_CMPX_NE_U32, + case 222: case 223: // V_CMPX_GE_U32,V_CMPX_T_U32, + appendOPR_SDST(layout.VDST,false,true,2); + appendOPR_SRC_NOLIT(layout.SRC0,true,false); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false); + appendOPR_SDST_EXEC(126,false,true,1,true); + break; + case 18: // V_CMP_CLASS_F64, + appendOPR_SREG(layout.VDST,false,true,2); + appendOPR_SRC_NOLIT(layout.SRC0,true,false,2); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false); + break; + case 19: // V_CMPX_CLASS_F64, + appendOPR_SDST(layout.VDST,false,true,2); + appendOPR_SRC_NOLIT(layout.SRC0,true,false,2); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false); + appendOPR_SDST_EXEC(126,false,true,1,true); + break; + case 96: case 97: case 98: case 99: case 100: // V_CMP_F_F64,V_CMP_LT_F64,V_CMP_EQ_F64,V_CMP_LE_F64,V_CMP_GT_F64, + case 101: case 102: case 103: case 104: // V_CMP_LG_F64,V_CMP_GE_F64,V_CMP_O_F64,V_CMP_U_F64, + case 105: case 106: case 107: case 108: // V_CMP_NGE_F64,V_CMP_NLG_F64,V_CMP_NGT_F64,V_CMP_NLE_F64, + case 109: case 110: case 111: case 224: // V_CMP_NEQ_F64,V_CMP_NLT_F64,V_CMP_TRU_F64,V_CMP_F_I64, + case 225: case 226: case 227: case 228: // V_CMP_LT_I64,V_CMP_EQ_I64,V_CMP_LE_I64,V_CMP_GT_I64, + case 229: case 230: case 231: case 232: case 233: // V_CMP_NE_I64,V_CMP_GE_I64,V_CMP_T_I64,V_CMP_F_U64,V_CMP_LT_U64, + case 234: case 235: case 236: case 237: // V_CMP_EQ_U64,V_CMP_LE_U64,V_CMP_GT_U64,V_CMP_NE_U64, + case 238: case 239: // V_CMP_GE_U64,V_CMP_T_U64, + appendOPR_SREG(layout.VDST,false,true,2); + appendOPR_SRC_NOLIT(layout.SRC0,true,false,2); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false,2); + break; + case 112: case 113: case 114: case 115: // V_CMPX_F_F64,V_CMPX_LT_F64,V_CMPX_EQ_F64,V_CMPX_LE_F64, + case 116: case 117: case 118: case 119: // V_CMPX_GT_F64,V_CMPX_LG_F64,V_CMPX_GE_F64,V_CMPX_O_F64, + case 120: case 121: case 122: case 123: // V_CMPX_U_F64,V_CMPX_NGE_F64,V_CMPX_NLG_F64,V_CMPX_NGT_F64, + case 124: case 125: case 126: case 127: // V_CMPX_NLE_F64,V_CMPX_NEQ_F64,V_CMPX_NLT_F64,V_CMPX_TRU_F64, + case 240: case 241: case 242: case 243: // V_CMPX_F_I64,V_CMPX_LT_I64,V_CMPX_EQ_I64,V_CMPX_LE_I64, + case 244: case 245: case 246: case 247: // V_CMPX_GT_I64,V_CMPX_NE_I64,V_CMPX_GE_I64,V_CMPX_T_I64, + case 248: case 249: case 250: case 251: // V_CMPX_F_U64,V_CMPX_LT_U64,V_CMPX_EQ_U64,V_CMPX_LE_U64, + case 252: case 253: case 254: case 255: // V_CMPX_GT_U64,V_CMPX_NE_U64,V_CMPX_GE_U64,V_CMPX_T_U64, + appendOPR_SDST(layout.VDST,false,true,2); + appendOPR_SRC_NOLIT(layout.SRC0,true,false,2); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false,2); + appendOPR_SDST_EXEC(126,false,true,1,true); + break; + } + } + + void InstructionDecoder_amdgpu_gfx940::finalizeENC_VOP2Operands() + { + layout_ENC_VOP2 & layout = insn_layout.ENC_VOP2; + switch (layout.OP) { + case 0: // V_CNDMASK_B32, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_SRC(layout.SRC0,true,false); + appendOPR_VGPR(layout.VSRC1,true,false); + appendOPR_VCC(0,true,false,2); + break; + case 1: case 2: case 3: case 5: case 6: // V_ADD_F32,V_SUB_F32,V_SUBREV_F32,V_MUL_F32,V_MUL_I32_I24, + case 7: case 8: case 9: case 10: case 11: // V_MUL_HI_I32_I24,V_MUL_U32_U24,V_MUL_HI_U32_U24,V_MIN_F32,V_MAX_F32, + case 12: case 13: case 14: case 15: case 19: // V_MIN_I32,V_MAX_I32,V_MIN_U32,V_MAX_U32,V_AND_B32, + case 20: case 21: case 31: case 32: case 34: // V_OR_B32,V_XOR_B32,V_ADD_F16,V_SUB_F16,V_MUL_F16, + case 38: case 39: case 41: case 45: case 46: // V_ADD_U16,V_SUB_U16,V_MUL_LO_U16,V_MAX_F16,V_MIN_F16, + case 47: case 48: case 49: case 50: case 51: // V_MAX_U16,V_MAX_I16,V_MIN_U16,V_MIN_I16,V_LDEXP_F16, + case 52: case 53: case 61: // V_ADD_U32,V_SUB_U32,V_XNOR_B32, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_SRC(layout.SRC0,true,false); + appendOPR_VGPR(layout.VSRC1,true,false); + break; + case 4: // V_FMAC_F64, + appendOPR_VGPR(layout.VDST,true,true,2); + appendOPR_SRC(layout.SRC0,true,false,2); + appendOPR_VGPR(layout.VSRC1,true,false,2); + break; + case 16: case 17: case 18: case 33: case 40: // V_LSHRREV_B32,V_ASHRREV_I32,V_LSHLREV_B32,V_SUBREV_F16,V_SUBREV_U16, + case 42: case 43: case 44: case 54: // V_LSHLREV_B16,V_LSHRREV_B16,V_ASHRREV_I16,V_SUBREV_U32, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_SRC_NOLDS(layout.SRC0,true,false); + appendOPR_VGPR(layout.VSRC1,true,false); + break; + case 25: case 26: // V_ADD_CO_U32,V_SUB_CO_U32, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_VCC(0,false,true,2); + appendOPR_SRC(layout.SRC0,true,false); + appendOPR_VGPR(layout.VSRC1,true,false); + break; + case 27: // V_SUBREV_CO_U32, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_VCC(0,false,true,2); + appendOPR_SRC_NOLDS(layout.SRC0,true,false); + appendOPR_VGPR(layout.VSRC1,true,false); + break; + case 28: case 29: // V_ADDC_CO_U32,V_SUBB_CO_U32, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_VCC(0,false,true,2); + appendOPR_SRC(layout.SRC0,true,false); + appendOPR_VGPR(layout.VSRC1,true,false); + appendOPR_VCC(0,true,false,2); + break; + case 30: // V_SUBBREV_CO_U32, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_VCC(0,false,true,2); + appendOPR_SRC_NOLDS(layout.SRC0,true,false); + appendOPR_VGPR(layout.VSRC1,true,false); + appendOPR_VCC(0,true,false,2); + break; + case 35: case 55: case 56: case 57: // V_MAC_F16,V_DOT2C_F32_F16,V_DOT2C_I32_I16,V_DOT4C_I32_I8, + case 58: case 59: case 60: // V_DOT8C_I32_I4,V_FMAC_F32,V_PK_FMAC_F16, + appendOPR_VGPR(layout.VDST,true,true); + appendOPR_SRC(layout.SRC0,true,false); + appendOPR_VGPR(layout.VSRC1,true,false); + break; + } + } + + void InstructionDecoder_amdgpu_gfx940::finalizeENC_VOP2_LITERALOperands() + { + layout_ENC_VOP2_LITERAL & layout = insn_layout.ENC_VOP2_LITERAL; + switch (layout.OP) { + case 23: case 36: // V_FMAMK_F32,V_MADMK_F16, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_SRC(layout.SRC0,true,false); + appendOPR_SIMM32(layout.SIMM32,true,false); + appendOPR_VGPR(layout.VSRC1,true,false); + break; + case 24: case 37: // V_FMAAK_F32,V_MADAK_F16, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_SRC(layout.SRC0,true,false); + appendOPR_VGPR(layout.VSRC1,true,false); + appendOPR_SIMM32(layout.SIMM32,true,false); + break; + } + } + + void InstructionDecoder_amdgpu_gfx940::finalizeENC_VOP3BOperands() + { + layout_ENC_VOP3B & layout = insn_layout.ENC_VOP3B; + switch (layout.OP) { + case 281: case 282: // V_ADD_CO_U32,V_SUB_CO_U32, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_SREG(layout.SDST,false,true,2); + appendOPR_SRC_NOLIT(layout.SRC0,true,false); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false); + break; + case 283: // V_SUBREV_CO_U32, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_SREG(layout.SDST,false,true,2); + appendOPR_SRC_SIMPLE(layout.SRC0,true,false); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false); + break; + case 284: case 285: // V_ADDC_CO_U32,V_SUBB_CO_U32, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_SREG(layout.SDST,false,true,2); + appendOPR_SRC_NOLIT(layout.SRC0,true,false); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false); + appendOPR_SREG(layout.SRC2,true,false,2); + break; + case 286: // V_SUBBREV_CO_U32, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_SREG(layout.SDST,false,true,2); + appendOPR_SRC_SIMPLE(layout.SRC0,true,false); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false); + appendOPR_SREG(layout.SRC2,true,false,2); + break; + case 480: // V_DIV_SCALE_F32, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_VCC(layout.SDST,false,true,2); + appendOPR_SRC_NOLIT(layout.SRC0,true,false); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false); + appendOPR_SRC_SIMPLE(layout.SRC2,true,false); + break; + case 481: // V_DIV_SCALE_F64, + appendOPR_VGPR(layout.VDST,false,true,2); + appendOPR_VCC(layout.SDST,false,true,2); + appendOPR_SRC_NOLIT(layout.SRC0,true,false,2); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false,2); + appendOPR_SRC_SIMPLE(layout.SRC2,true,false,2); + break; + case 488: case 489: // V_MAD_U64_U32,V_MAD_I64_I32, + appendOPR_VGPR(layout.VDST,false,true,2); + appendOPR_SREG(layout.SDST,false,true,2); + appendOPR_SRC_NOLIT(layout.SRC0,true,false); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false); + appendOPR_SRC_SIMPLE(layout.SRC2,true,false,2); + break; + } + } + + void InstructionDecoder_amdgpu_gfx940::finalizeENC_VOP3POperands() + { + layout_ENC_VOP3P & layout = insn_layout.ENC_VOP3P; + switch (layout.OP) { + case 0: case 9: case 14: case 32: case 33: // V_PK_MAD_I16,V_PK_MAD_U16,V_PK_FMA_F16,V_MAD_MIX_F32,V_MAD_MIXLO_F16, + case 34: case 35: case 38: case 39: // V_MAD_MIXHI_F16,V_DOT2_F32_F16,V_DOT2_I32_I16,V_DOT2_U32_U16, + case 40: case 41: case 42: case 43: // V_DOT4_I32_I8,V_DOT4_U32_U8,V_DOT8_I32_I4,V_DOT8_U32_U4, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_SRC_NOLIT(layout.SRC0,true,false); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false); + appendOPR_SRC_SIMPLE(layout.SRC2,true,false); + break; + case 1: case 2: case 3: case 7: case 8: // V_PK_MUL_LO_U16,V_PK_ADD_I16,V_PK_SUB_I16,V_PK_MAX_I16,V_PK_MIN_I16, + case 10: case 11: case 12: case 13: case 15: // V_PK_ADD_U16,V_PK_SUB_U16,V_PK_MAX_U16,V_PK_MIN_U16,V_PK_ADD_F16, + case 16: case 17: case 18: // V_PK_MUL_F16,V_PK_MIN_F16,V_PK_MAX_F16, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_SRC_NOLIT(layout.SRC0,true,false); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false); + break; + case 4: case 5: case 6: // V_PK_LSHLREV_B16,V_PK_LSHRREV_B16,V_PK_ASHRREV_I16, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_SRC_SIMPLE(layout.SRC0,true,false); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false); + break; + case 48: // V_PK_FMA_F32, + appendOPR_VGPR(layout.VDST,false,true,2); + appendOPR_SRC_NOLIT(layout.SRC0,true,false,2); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false,2); + appendOPR_SRC_SIMPLE(layout.SRC2,true,false,2); + break; + case 49: case 50: case 51: // V_PK_MUL_F32,V_PK_ADD_F32,V_PK_MOV_B32, + appendOPR_VGPR(layout.VDST,false,true,2); + appendOPR_SRC_NOLIT(layout.SRC0,true,false,2); + appendOPR_SRC_SIMPLE(layout.SRC1,true,false,2); + break; + case 88: // V_ACCVGPR_READ, + appendOPR_VGPR(layout.VDST,false,true); + appendOPR_SRC_ACCVGPR(layout.SRC0,true,false); + break; + case 89: // V_ACCVGPR_WRITE, + appendOPR_ACCVGPR(layout.VDST,false,true); + appendOPR_SRC_NOLIT(layout.SRC0,true,false); + break; + } + } + + void InstructionDecoder_amdgpu_gfx940::finalizeENC_VOP3P_MFMAOperands() + { + layout_ENC_VOP3P_MFMA & layout = insn_layout.ENC_VOP3P_MFMA; + switch (layout.OP) { + case 62: case 74: case 77: // V_MFMA_F32_16X16X8_XF32,V_MFMA_F32_4X4X4_16B_F16,V_MFMA_F32_16X16X16_F16, + case 87: case 95: case 97: // V_MFMA_I32_16X16X32_I8,V_MFMA_F32_4X4X4_16B_BF16,V_MFMA_F32_16X16X16_BF16, + case 112: case 113: case 114: // V_MFMA_F32_16X16X32_BF8_BF8,V_MFMA_F32_16X16X32_BF8_FP8,V_MFMA_F32_16X16X32_FP8_BF8, + case 115: // V_MFMA_F32_16X16X32_FP8_FP8, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true,4); + appendOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,true,false,2); + appendOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,true,false,2); + appendOPR_SRC_VGPR_OR_ACCVGPR_OR_CONST(layout.SRC2,true,false,4); + break; + case 63: case 73: case 76: // V_MFMA_F32_32X32X4_XF32,V_MFMA_F32_16X16X4_4B_F16,V_MFMA_F32_32X32X8_F16, + case 86: case 94: case 96: // V_MFMA_I32_32X32X16_I8,V_MFMA_F32_16X16X4_4B_BF16,V_MFMA_F32_32X32X8_BF16, + case 116: case 117: case 118: // V_MFMA_F32_32X32X16_BF8_BF8,V_MFMA_F32_32X32X16_BF8_FP8,V_MFMA_F32_32X32X16_FP8_BF8, + case 119: // V_MFMA_F32_32X32X16_FP8_FP8, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true,16); + appendOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,true,false,2); + appendOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,true,false,2); + appendOPR_SRC_VGPR_OR_ACCVGPR_OR_CONST(layout.SRC2,true,false,16); + break; + case 64: case 80: // V_MFMA_F32_32X32X1_2B_F32,V_MFMA_I32_32X32X4_2B_I8, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true,32); + appendOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,true,false); + appendOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,true,false); + appendOPR_SRC_VGPR_OR_ACCVGPR_OR_CONST(layout.SRC2,true,false,32); + break; + case 65: case 68: case 81: // V_MFMA_F32_16X16X1_4B_F32,V_MFMA_F32_32X32X2_F32,V_MFMA_I32_16X16X4_4B_I8, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true,16); + appendOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,true,false); + appendOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,true,false); + appendOPR_SRC_VGPR_OR_ACCVGPR_OR_CONST(layout.SRC2,true,false,16); + break; + case 66: case 69: case 82: // V_MFMA_F32_4X4X1_16B_F32,V_MFMA_F32_16X16X4_F32,V_MFMA_I32_4X4X4_16B_I8, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true,4); + appendOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,true,false); + appendOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,true,false); + appendOPR_SRC_VGPR_OR_ACCVGPR_OR_CONST(layout.SRC2,true,false,4); + break; + case 72: case 93: // V_MFMA_F32_32X32X4_2B_F16,V_MFMA_F32_32X32X4_2B_BF16, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true,32); + appendOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,true,false,2); + appendOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,true,false,2); + appendOPR_SRC_VGPR_OR_ACCVGPR_OR_CONST(layout.SRC2,true,false,32); + break; + case 98: case 106: case 120: // V_SMFMAC_F32_16X16X32_F16,V_SMFMAC_I32_16X16X64_I8,V_SMFMAC_F32_16X16X64_BF8_BF8, + case 121: case 122: // V_SMFMAC_F32_16X16X64_BF8_FP8,V_SMFMAC_F32_16X16X64_FP8_BF8, + case 123: // V_SMFMAC_F32_16X16X64_FP8_FP8, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,true,true,4); + appendOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,true,false,2); + appendOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,true,false,4); + appendOPR_SRC_VGPR(layout.SRC2,true,false); + break; + case 100: case 102: // V_SMFMAC_F32_32X32X16_F16,V_SMFMAC_F32_16X16X32_BF16, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,true,true,16); + appendOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,true,false,2); + appendOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,true,false,2); + appendOPR_SRC_VGPR(layout.SRC2,true,false,16); + break; + case 104: // V_SMFMAC_F32_32X32X16_BF16, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,true,true,32); + appendOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,true,false); + appendOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,true,false); + appendOPR_SRC_VGPR(layout.SRC2,true,false,32); + break; + case 108: // V_SMFMAC_I32_32X32X32_I8, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,true,true,16); + appendOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,true,false); + appendOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,true,false); + appendOPR_SRC_VGPR(layout.SRC2,true,false,16); + break; + case 110: // V_MFMA_F64_16X16X4_F64, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true,8); + appendOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,true,false,2); + appendOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,true,false,2); + appendOPR_SRC_VGPR_OR_ACCVGPR_OR_CONST(layout.SRC2,true,false,8); + break; + case 111: // V_MFMA_F64_4X4X4_4B_F64, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,false,true,2); + appendOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,true,false,2); + appendOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,true,false,2); + appendOPR_SRC_VGPR_OR_ACCVGPR_OR_CONST(layout.SRC2,true,false,2); + break; + case 124: case 125: // V_SMFMAC_F32_32X32X32_BF8_BF8,V_SMFMAC_F32_32X32X32_BF8_FP8, + case 126: case 127: // V_SMFMAC_F32_32X32X32_FP8_BF8,V_SMFMAC_F32_32X32X32_FP8_FP8, + appendOPR_VGPR_OR_ACCVGPR(layout.VDST,true,true,16); + appendOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC0,true,false,2); + appendOPR_SRC_VGPR_OR_ACCVGPR(layout.SRC1,true,false,4); + appendOPR_SRC_VGPR(layout.SRC2,true,false); + break; + } + } + + void InstructionDecoder_amdgpu_gfx940::finalizeENC_VOPCOperands() + { + layout_ENC_VOPC & layout = insn_layout.ENC_VOPC; + switch (layout.OP) { + case 16: case 20: case 32: case 33: // V_CMP_CLASS_F32,V_CMP_CLASS_F16,V_CMP_F_F16,V_CMP_LT_F16, + case 34: case 35: case 36: case 37: case 38: // V_CMP_EQ_F16,V_CMP_LE_F16,V_CMP_GT_F16,V_CMP_LG_F16,V_CMP_GE_F16, + case 39: case 40: case 41: case 42: case 43: // V_CMP_O_F16,V_CMP_U_F16,V_CMP_NGE_F16,V_CMP_NLG_F16,V_CMP_NGT_F16, + case 44: case 45: case 46: case 47: case 64: // V_CMP_NLE_F16,V_CMP_NEQ_F16,V_CMP_NLT_F16,V_CMP_TRU_F16,V_CMP_F_F32, + case 65: case 66: case 67: case 68: case 69: // V_CMP_LT_F32,V_CMP_EQ_F32,V_CMP_LE_F32,V_CMP_GT_F32,V_CMP_LG_F32, + case 70: case 71: case 72: case 73: case 74: // V_CMP_GE_F32,V_CMP_O_F32,V_CMP_U_F32,V_CMP_NGE_F32,V_CMP_NLG_F32, + case 75: case 76: case 77: case 78: // V_CMP_NGT_F32,V_CMP_NLE_F32,V_CMP_NEQ_F32,V_CMP_NLT_F32, + case 79: case 160: case 161: case 162: // V_CMP_TRU_F32,V_CMP_F_I16,V_CMP_LT_I16,V_CMP_EQ_I16, + case 163: case 164: case 165: case 166: // V_CMP_LE_I16,V_CMP_GT_I16,V_CMP_NE_I16,V_CMP_GE_I16, + case 167: case 168: case 169: case 170: case 171: // V_CMP_T_I16,V_CMP_F_U16,V_CMP_LT_U16,V_CMP_EQ_U16,V_CMP_LE_U16, + case 172: case 173: case 174: case 175: case 192: // V_CMP_GT_U16,V_CMP_NE_U16,V_CMP_GE_U16,V_CMP_T_U16,V_CMP_F_I32, + case 193: case 194: case 195: case 196: // V_CMP_LT_I32,V_CMP_EQ_I32,V_CMP_LE_I32,V_CMP_GT_I32, + case 197: case 198: case 199: case 200: case 201: // V_CMP_NE_I32,V_CMP_GE_I32,V_CMP_T_I32,V_CMP_F_U32,V_CMP_LT_U32, + case 202: case 203: case 204: case 205: // V_CMP_EQ_U32,V_CMP_LE_U32,V_CMP_GT_U32,V_CMP_NE_U32, + case 206: case 207: // V_CMP_GE_U32,V_CMP_T_U32, + appendOPR_VCC(0,false,true,2); + appendOPR_SRC(layout.SRC0,true,false); + appendOPR_VGPR(layout.VSRC1,true,false); + break; + case 17: case 21: case 48: case 49: // V_CMPX_CLASS_F32,V_CMPX_CLASS_F16,V_CMPX_F_F16,V_CMPX_LT_F16, + case 50: case 51: case 52: case 53: // V_CMPX_EQ_F16,V_CMPX_LE_F16,V_CMPX_GT_F16,V_CMPX_LG_F16, + case 54: case 55: case 56: case 57: // V_CMPX_GE_F16,V_CMPX_O_F16,V_CMPX_U_F16,V_CMPX_NGE_F16, + case 58: case 59: case 60: case 61: // V_CMPX_NLG_F16,V_CMPX_NGT_F16,V_CMPX_NLE_F16,V_CMPX_NEQ_F16, + case 62: case 63: case 80: case 81: // V_CMPX_NLT_F16,V_CMPX_TRU_F16,V_CMPX_F_F32,V_CMPX_LT_F32, + case 82: case 83: case 84: case 85: // V_CMPX_EQ_F32,V_CMPX_LE_F32,V_CMPX_GT_F32,V_CMPX_LG_F32, + case 86: case 87: case 88: case 89: // V_CMPX_GE_F32,V_CMPX_O_F32,V_CMPX_U_F32,V_CMPX_NGE_F32, + case 90: case 91: case 92: case 93: // V_CMPX_NLG_F32,V_CMPX_NGT_F32,V_CMPX_NLE_F32,V_CMPX_NEQ_F32, + case 94: case 95: case 176: case 177: // V_CMPX_NLT_F32,V_CMPX_TRU_F32,V_CMPX_F_I16,V_CMPX_LT_I16, + case 178: case 179: case 180: case 181: // V_CMPX_EQ_I16,V_CMPX_LE_I16,V_CMPX_GT_I16,V_CMPX_NE_I16, + case 182: case 183: case 184: case 185: // V_CMPX_GE_I16,V_CMPX_T_I16,V_CMPX_F_U16,V_CMPX_LT_U16, + case 186: case 187: case 188: case 189: // V_CMPX_EQ_U16,V_CMPX_LE_U16,V_CMPX_GT_U16,V_CMPX_NE_U16, + case 190: case 191: case 208: case 209: // V_CMPX_GE_U16,V_CMPX_T_U16,V_CMPX_F_I32,V_CMPX_LT_I32, + case 210: case 211: case 212: case 213: // V_CMPX_EQ_I32,V_CMPX_LE_I32,V_CMPX_GT_I32,V_CMPX_NE_I32, + case 214: case 215: case 216: case 217: // V_CMPX_GE_I32,V_CMPX_T_I32,V_CMPX_F_U32,V_CMPX_LT_U32, + case 218: case 219: case 220: case 221: // V_CMPX_EQ_U32,V_CMPX_LE_U32,V_CMPX_GT_U32,V_CMPX_NE_U32, + case 222: case 223: // V_CMPX_GE_U32,V_CMPX_T_U32, + appendOPR_VCC(0,false,true,2); + appendOPR_SRC(layout.SRC0,true,false); + appendOPR_VGPR(layout.VSRC1,true,false); + appendOPR_SDST_EXEC(126,false,true,1,true); + break; + case 18: // V_CMP_CLASS_F64, + appendOPR_VCC(0,false,true,2); + appendOPR_SRC(layout.SRC0,true,false,2); + appendOPR_VGPR(layout.VSRC1,true,false); + break; + case 19: // V_CMPX_CLASS_F64, + appendOPR_VCC(0,false,true,2); + appendOPR_SRC(layout.SRC0,true,false,2); + appendOPR_VGPR(layout.VSRC1,true,false); + appendOPR_SDST_EXEC(126,false,true,1,true); + break; + case 96: case 97: case 98: case 99: case 100: // V_CMP_F_F64,V_CMP_LT_F64,V_CMP_EQ_F64,V_CMP_LE_F64,V_CMP_GT_F64, + case 101: case 102: case 103: case 104: // V_CMP_LG_F64,V_CMP_GE_F64,V_CMP_O_F64,V_CMP_U_F64, + case 105: case 106: case 107: case 108: // V_CMP_NGE_F64,V_CMP_NLG_F64,V_CMP_NGT_F64,V_CMP_NLE_F64, + case 109: case 110: case 111: case 224: // V_CMP_NEQ_F64,V_CMP_NLT_F64,V_CMP_TRU_F64,V_CMP_F_I64, + case 225: case 226: case 227: case 228: // V_CMP_LT_I64,V_CMP_EQ_I64,V_CMP_LE_I64,V_CMP_GT_I64, + case 229: case 230: case 231: case 232: case 233: // V_CMP_NE_I64,V_CMP_GE_I64,V_CMP_T_I64,V_CMP_F_U64,V_CMP_LT_U64, + case 234: case 235: case 236: case 237: // V_CMP_EQ_U64,V_CMP_LE_U64,V_CMP_GT_U64,V_CMP_NE_U64, + case 238: case 239: // V_CMP_GE_U64,V_CMP_T_U64, + appendOPR_VCC(0,false,true,2); + appendOPR_SRC(layout.SRC0,true,false,2); + appendOPR_VGPR(layout.VSRC1,true,false,2); + break; + case 112: case 113: case 114: case 115: // V_CMPX_F_F64,V_CMPX_LT_F64,V_CMPX_EQ_F64,V_CMPX_LE_F64, + case 116: case 117: case 118: case 119: // V_CMPX_GT_F64,V_CMPX_LG_F64,V_CMPX_GE_F64,V_CMPX_O_F64, + case 120: case 121: case 122: case 123: // V_CMPX_U_F64,V_CMPX_NGE_F64,V_CMPX_NLG_F64,V_CMPX_NGT_F64, + case 124: case 125: case 126: case 127: // V_CMPX_NLE_F64,V_CMPX_NEQ_F64,V_CMPX_NLT_F64,V_CMPX_TRU_F64, + case 240: case 241: case 242: case 243: // V_CMPX_F_I64,V_CMPX_LT_I64,V_CMPX_EQ_I64,V_CMPX_LE_I64, + case 244: case 245: case 246: case 247: // V_CMPX_GT_I64,V_CMPX_NE_I64,V_CMPX_GE_I64,V_CMPX_T_I64, + case 248: case 249: case 250: case 251: // V_CMPX_F_U64,V_CMPX_LT_U64,V_CMPX_EQ_U64,V_CMPX_LE_U64, + case 252: case 253: case 254: case 255: // V_CMPX_GT_U64,V_CMPX_NE_U64,V_CMPX_GE_U64,V_CMPX_T_U64, + appendOPR_VCC(0,false,true,2); + appendOPR_SRC(layout.SRC0,true,false,2); + appendOPR_VGPR(layout.VSRC1,true,false,2); + appendOPR_SDST_EXEC(126,false,true,1,true); + break; + } + } + +void InstructionDecoder_amdgpu_gfx940::finalizeENC_VINTRPOperands() { +} + +void InstructionDecoder_amdgpu_gfx940::finalizeENC_MIMGOperands() { +} + +void InstructionDecoder_amdgpu_gfx940::finalizeSOPK_INST_LITERAL_Operands() { +} + +} +} diff --git a/instructionAPI/src/ArchSpecificFormatters.C b/instructionAPI/src/ArchSpecificFormatters.C index 5f1fe1ec81..a953502232 100644 --- a/instructionAPI/src/ArchSpecificFormatters.C +++ b/instructionAPI/src/ArchSpecificFormatters.C @@ -4,24 +4,51 @@ #include "ArchSpecificFormatters.h" #include +#include #include #include #include #include #include +#include +#include +#include "../../common/h/compiler_diagnostics.h" +#include "Architecture.h" +#include "registers/AMDGPU/amdgpu_gfx908_regs.h" +#include "registers/AMDGPU/amdgpu_gfx90a_regs.h" +#include "registers/AMDGPU/amdgpu_gfx940_regs.h" + using namespace Dyninst::InstructionAPI; ///////// Base Formatter -std::string ArchSpecificFormatter::formatBinaryFunc(std::string left, std::string func, std::string right) { +std::string ArchSpecificFormatter::getInstructionString(const std::vector &operands) const +{ + // non-x86_64 operand formatter: join non-empty operands strings with ", " + std::string result; + for(const auto &op : operands) { + if(!op.empty()) { + if(!result.empty()) result += ", "; + result += op; + } + } + return result; +} + +std::string ArchSpecificFormatter::formatBinaryFunc(const std::string &left, const std::string &func, const std::string &right) const { // if(isAdd()) // { return left + " " + func + " " + right; // } else retVal << "NOT VALID FOR AT&T"; } +bool ArchSpecificFormatter::operandPrintOrderReversed() const +{ + return false; +} + /////////////////////////// ///////// Formatter for PowerPC @@ -29,14 +56,14 @@ std::string ArchSpecificFormatter::formatBinaryFunc(std::string left, std::strin PPCFormatter::PPCFormatter() { } -std::string PPCFormatter::formatImmediate(std::string evalString) { +std::string PPCFormatter::formatImmediate(const std::string &evalString) const { size_t endPos; long long long_val = stoll(evalString, &endPos, 16); signed short val = static_cast(long_val); return std::to_string(val); } -std::string PPCFormatter::formatRegister(std::string regName) { +std::string PPCFormatter::formatRegister(const std::string ®Name) const { if (regName == "ppc64::pc" || regName == "ppc64::ctr" || regName == "ppc64::lr" || @@ -54,7 +81,7 @@ std::string PPCFormatter::formatRegister(std::string regName) { return ret; } -std::string PPCFormatter::formatDeref(std::string addrString) { +std::string PPCFormatter::formatDeref(const std::string &addrString) const { size_t commaPos = addrString.find(","); if (commaPos == std::string::npos || commaPos > addrString.length() - 2) { return "(" + addrString + ")"; @@ -64,22 +91,7 @@ std::string PPCFormatter::formatDeref(std::string addrString) { return offset + "(" + base + ")"; } -std::string PPCFormatter::getInstructionString(std::vector operands) { - std::string out; - - for(std::vector::iterator itr = operands.begin(); itr != operands.end(); itr++) { - if (*itr != "") { - out += *itr; - if(itr != operands.end() - 1) { - out += ", "; - } - } - } - - return out; -} - -std::string PPCFormatter::formatBinaryFunc(std::string left, std::string func, std::string right) { +std::string PPCFormatter::formatBinaryFunc(const std::string &left, const std::string &func, const std::string &right) const { if (left == "") { return right; } @@ -95,11 +107,11 @@ ArmFormatter::ArmFormatter() { binaryFuncModifier["<<"] = "lsl"; } -std::string ArmFormatter::formatImmediate(std::string evalString) { +std::string ArmFormatter::formatImmediate(const std::string &evalString) const { return "0x" + evalString; } -std::string ArmFormatter::formatRegister(std::string regName) { +std::string ArmFormatter::formatRegister(const std::string ®Name) const { std::string::size_type substr = regName.rfind(':'); std::string ret = regName; @@ -111,7 +123,7 @@ std::string ArmFormatter::formatRegister(std::string regName) { return ret; } -std::string ArmFormatter::formatDeref(std::string addrString) { +std::string ArmFormatter::formatDeref(const std::string &addrString) const { std::string out; size_t pluspos = addrString.find("+"); @@ -128,21 +140,9 @@ std::string ArmFormatter::formatDeref(std::string addrString) { return out; } -std::string ArmFormatter::getInstructionString(std::vector operands) { - std::string out; - - for(std::vector::iterator itr = operands.begin(); itr != operands.end(); itr++) { - out += *itr; - if(itr != operands.end() - 1) - out += ", "; - } - - return out; -} - -std::string ArmFormatter::formatBinaryFunc(std::string left, std::string func, std::string right) { +std::string ArmFormatter::formatBinaryFunc(const std::string &left, const std::string &func, const std::string &right) const { if(binaryFuncModifier.count(func) > 0) - return left + ", " + binaryFuncModifier[func] + " " + right; + return left + ", " + binaryFuncModifier.at(func) + " " + right; /*else if(left == "PC") return right;*/ else @@ -155,17 +155,17 @@ AmdgpuFormatter::AmdgpuFormatter() { binaryFuncModifier["<<"] = "lsl"; } -std::string AmdgpuFormatter::formatImmediate(std::string evalString) { +std::string AmdgpuFormatter::formatImmediate(const std::string &evalString) const { return "0x" + evalString; } -std::string AmdgpuFormatter::formatRegister(std::string regName) { +std::string AmdgpuFormatter::formatRegister(const std::string ®Name) const { std::string ret = regName; for(auto &c : ret ) c = ::toupper(c); return ret; } -std::string AmdgpuFormatter::formatDeref(std::string addrString) { +std::string AmdgpuFormatter::formatDeref(const std::string &addrString) const { std::string out; size_t pluspos = addrString.find("+"); @@ -182,27 +182,99 @@ std::string AmdgpuFormatter::formatDeref(std::string addrString) { return out; } -std::string AmdgpuFormatter::getInstructionString(std::vector operands) { - std::string out; - - for(std::vector::iterator itr = operands.begin(); itr != operands.end(); itr++) { - out += *itr; - if(itr != operands.end() - 1) - out += ", "; - } - - return out; -} - -std::string AmdgpuFormatter::formatBinaryFunc(std::string left, std::string func, std::string right) { +std::string AmdgpuFormatter::formatBinaryFunc(const std::string &left, const std::string &func, const std::string &right) const { if(binaryFuncModifier.count(func) > 0) - return "("+left + ", " + binaryFuncModifier[func] + " " + right+")"; + return "("+left + ", " + binaryFuncModifier.at(func) + " " + right+")"; /*else if(left == "PC") return right;*/ else return "("+left + " " + func + " " + right+")"; } +std::string AmdgpuFormatter::formatRegister(MachRegister m_Reg, uint32_t m_num_elements, unsigned m_Low , unsigned m_High) { + std::string name = m_Reg.name(); + std::string::size_type substr = name.rfind("::"); + if(substr != std::string::npos){ + name = name.substr(substr+2,name.length()); + } + if( m_num_elements ==0 ){ + return ""; + }else if ( m_num_elements > 1){ + uint32_t id = m_Reg & 0xff ; + uint32_t regClass = m_Reg.regClass(); + + uint32_t size = m_num_elements; + + DYNINST_DIAGNOSTIC_BEGIN_SUPPRESS_LOGICAL_OP + + if(regClass == amdgpu_gfx908::SGPR || regClass == amdgpu_gfx90a::SGPR || + regClass == amdgpu_gfx940::SGPR){ + return "S["+std::to_string(id) + ":" + std::to_string(id+size-1)+"]"; + } + + if(regClass == amdgpu_gfx908::VGPR || regClass == amdgpu_gfx90a::VGPR || + regClass == amdgpu_gfx940::VGPR){ + return "V["+std::to_string(id) + ":" + std::to_string(id+size-1)+"]"; + } + + if(regClass == amdgpu_gfx908::ACC_VGPR || regClass == amdgpu_gfx90a::ACC_VGPR || + regClass == amdgpu_gfx940::ACC_VGPR){ + return "ACC["+std::to_string(id) + ":" + std::to_string(id+size-1)+"]"; + } + + DYNINST_DIAGNOSTIC_END_SUPPRESS_LOGICAL_OP + + if(m_Reg == amdgpu_gfx908::vcc_lo || m_Reg == amdgpu_gfx90a::vcc_lo || + m_Reg == amdgpu_gfx940::vcc_lo) + return "VCC"; + if(m_Reg == amdgpu_gfx908::exec_lo || m_Reg == amdgpu_gfx90a::exec_lo || + m_Reg == amdgpu_gfx940::exec_lo) + return "EXEC"; + + + }else if ( m_High -m_Low > 32 && m_Reg.size()*8 != m_High - m_Low){ + + // Size of base register * 8 != m_High - mLow ( in bits) when we it is a register vector + uint32_t id = m_Reg & 0xff ; + uint32_t regClass = m_Reg.regClass(); + uint32_t size = (m_High - m_Low ) / 32; + + // Suppress warning (for compilers where it is a false positive) + // The values of the two *::SGPR constants are identical, as + // are the two *::VGPR constants + DYNINST_DIAGNOSTIC_BEGIN_SUPPRESS_LOGICAL_OP + + if(regClass == amdgpu_gfx908::SGPR || regClass == amdgpu_gfx90a::SGPR || + regClass == amdgpu_gfx940::SGPR){ + return "S["+std::to_string(id) + ":" + std::to_string(id+size-1)+"]"; + } + + if(regClass == amdgpu_gfx908::VGPR || regClass == amdgpu_gfx90a::VGPR || + regClass == amdgpu_gfx940::VGPR){ + return "V["+std::to_string(id) + ":" + std::to_string(id+size-1)+"]"; + } + + if(regClass == amdgpu_gfx908::ACC_VGPR || regClass == amdgpu_gfx90a::ACC_VGPR || + regClass == amdgpu_gfx940::ACC_VGPR){ + return "ACC["+std::to_string(id) + ":" + std::to_string(id+size-1)+"]"; + } + + DYNINST_DIAGNOSTIC_END_SUPPRESS_LOGICAL_OP + + if(m_Reg == amdgpu_gfx908::vcc_lo || m_Reg == amdgpu_gfx90a::vcc_lo || + m_Reg == amdgpu_gfx940::vcc_lo) + return "VCC"; + + if(m_Reg == amdgpu_gfx908::exec_lo || m_Reg == amdgpu_gfx90a::exec_lo || + m_Reg == amdgpu_gfx940::exec_lo) + return "EXEC"; + + name += "["+std::to_string(m_Low)+":"+std::to_string(m_High)+"]"; + } + + return name; +} + /////////////////////////// x86 Formatter functions @@ -211,38 +283,30 @@ x86Formatter::x86Formatter() } -std::string x86Formatter::formatImmediate(std::string evalString) +std::string x86Formatter::formatImmediate(const std::string &evalString) const { return "$0x" + evalString; } -std::string x86Formatter::formatRegister(std::string regName) +std::string x86Formatter::formatRegister(const std::string ®Name) const { - for(char &c : regName) c = std::tolower(c); - - char* orig = strdup(regName.c_str()); + std::string outReg{'%'}; - /* Get rid of the Arch*:: prefix */ - int ccount = 0; - char* pointer = orig; - while(ccount < 2) - { - if(!*pointer) break; - - if(*pointer == ':') - ccount++; - pointer++; + auto regNameOffset = regName.find("::"); + if (regNameOffset == std::string::npos) { + regNameOffset = 0; // no "::", copy whole string + } else { + regNameOffset += 2; // skip "::" } + auto sBegin = regName.cbegin() + regNameOffset; + auto sEnd = regName.cend(); + auto outRegInserter = std::back_inserter(outReg); + std::transform(sBegin, sEnd, outRegInserter, [](unsigned char c){ return std::tolower(c);}); - /* convert to a standard string */ - regName = pointer; - free(orig); - std::string ss = "%" + regName; - regName = ss; - return ss; + return outReg; } -std::string x86Formatter::formatDeref(std::string addrString) +std::string x86Formatter::formatDeref(const std::string &addrString) const { // fprintf(stderr, "Must format dereference: %s\n", addrString.c_str()); @@ -252,58 +316,24 @@ std::string x86Formatter::formatDeref(std::string addrString) else return addrString; } -std::string x86Formatter::getInstructionString(std::vector operands) +std::string x86Formatter::getInstructionString(const std::vector &operands) const { - // fprintf(stderr, "Operands: "); - // for(auto iter = operands.begin(); iter != operands.end(); iter++) - // { - // if(iter == operands.begin()) - // fprintf(stderr, "%s", (*iter).c_str()); - // else fprintf(stderr, ", %s", (*iter).c_str()); - // } - - /* We have to reorder the operands here */ - std::string source_ops = ""; - std::string dest_op = ""; - std::string kmask_op = ""; - - /** - * We have to convert the Intel syntax operand ordering to AT&T because - * our tables are in Intel ordering - */ - for(auto itr = operands.begin(); itr != operands.end(); itr++) - { - std::string op = *itr; - - /* If we still have a leading ##, it's an indirect call or SIB expression */ - if(!op.compare(0, 2, "##")) - { - op = "0x0(" + op.substr(2) + ")"; - } - - if(itr == operands.begin()) - { - dest_op = op; - } else if(!op.compare(0, 2, "%k")) - { - kmask_op = "{" + op + "}"; - } else if(!source_ops.compare("")) - { - source_ops = op; - } else { - source_ops += "," + op; - } + std::string s; + bool oneOperandAdded{false}; + + // append the operands in reverse order to convert from Intel to AT&T syntax order + for (auto i = operands.crbegin(); i != operands.crend(); ++i) { + if (oneOperandAdded) { + s += ','; + } + s += *i; + oneOperandAdded = true; } - /* Put the instruction together */ - std::string ret = source_ops; - if (ret.compare("")) ret += ","; - ret += dest_op; - ret += kmask_op; - return ret; + return s; } -std::string x86Formatter::formatBinaryFunc(std::string left, std::string func, std::string right) +std::string x86Formatter::formatBinaryFunc(const std::string &left, const std::string &func, const std::string &right) const { // fprintf(stderr, "left: %s func: %s right: %s\n", left.c_str(), func.c_str(), right.c_str()); @@ -377,28 +407,35 @@ std::string x86Formatter::formatBinaryFunc(std::string left, std::string func, s return retval; } +bool x86Formatter::operandPrintOrderReversed() const +{ + return true; +} + /////////////////////////// ArchSpecificFormatter& ArchSpecificFormatter::getFormatter(Architecture a) { - static dyn_tls std::map > theFormatters; + static dyn_tls std::map > theFormatters; auto found = theFormatters.find(a); if(found != theFormatters.end()) return *found->second; switch(a) { - case Arch_amdgpu_vega: - theFormatters[a] = boost::shared_ptr(new AmdgpuFormatter()); + case Arch_amdgpu_gfx908: + case Arch_amdgpu_gfx90a: + case Arch_amdgpu_gfx940: + theFormatters[a] = dyncompat::shared_ptr(new AmdgpuFormatter()); break; case Arch_aarch32: case Arch_aarch64: - theFormatters[a] = boost::shared_ptr(new ArmFormatter()); + theFormatters[a] = dyncompat::shared_ptr(new ArmFormatter()); break; case Arch_ppc32: case Arch_ppc64: - theFormatters[a] = boost::shared_ptr(new PPCFormatter()); + theFormatters[a] = dyncompat::shared_ptr(new PPCFormatter()); break; case Arch_x86: case Arch_x86_64: default: - theFormatters[a] = boost::shared_ptr(new x86Formatter()); + theFormatters[a] = dyncompat::shared_ptr(new x86Formatter()); break; } return *theFormatters[a]; diff --git a/instructionAPI/src/BinaryFunction.C b/instructionAPI/src/BinaryFunction.C index 098da7ff96..75c2448067 100644 --- a/instructionAPI/src/BinaryFunction.C +++ b/instructionAPI/src/BinaryFunction.C @@ -367,8 +367,8 @@ namespace Dyninst const Result& BinaryFunction::eval() const { - Expression::Ptr arg1 = boost::dynamic_pointer_cast(m_arg1); - Expression::Ptr arg2 = boost::dynamic_pointer_cast(m_arg2); + Expression::Ptr arg1 = dyncompat::dynamic_pointer_cast(m_arg1); + Expression::Ptr arg2 = dyncompat::dynamic_pointer_cast(m_arg2); if(arg1 && arg2) { diff --git a/instructionAPI/src/Immediate.C b/instructionAPI/src/Immediate.C index d185e7920e..d46926f17c 100644 --- a/instructionAPI/src/Immediate.C +++ b/instructionAPI/src/Immediate.C @@ -28,6 +28,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include #include #include @@ -36,7 +37,7 @@ #include "../../common/src/singleton_object_pool.h" #include "Visitor.h" #include "ArchSpecificFormatters.h" -#include +#include namespace Dyninst { namespace InstructionAPI { @@ -85,8 +86,23 @@ namespace Dyninst { v->visit(this); } + NamedImmediate::NamedImmediate(std::string name, const Result &val) : Immediate(val) , name_(name){ + } + + Immediate::Ptr NamedImmediate::makeNamedImmediate(std::string name, const Result &val) { + Immediate::Ptr ret = make_shared(singleton_object_pool::construct(name,val)); + return ret; + } + + std::string NamedImmediate::format(Architecture, formatStyle f) const { + return format(f); + } + + std::string NamedImmediate::format(formatStyle f) const { + return name_+std::string(":0x")+Immediate::format(f); + } ArmConditionImmediate::ArmConditionImmediate(const Result &val) : Immediate(val) { - m_condLookupMap = boost::assign::map_list_of(0, "eq")(1, "ne")(2, "cs")(3, "cc")(4, "mi")(5, "pl")(6, "vs")(7, "vc") + m_condLookupMap = dyncompat::assign::map_list_of(0, "eq")(1, "ne")(2, "cs")(3, "cc")(4, "mi")(5, "pl")(6, "vs")(7, "vc") (8, "hi")(9, "ls")(10, "ge")(11, "lt")(12, "gt")(13, "le")(14, "al")(15, "nv").convert_to_container >(); } @@ -108,7 +124,7 @@ namespace Dyninst { } ArmPrfmTypeImmediate::ArmPrfmTypeImmediate(const Result &val) : Immediate(val) { - m_prfmTypeLookupMap = boost::assign::map_list_of(0, "PLDL1KEEP")(1, "PLDL1STRM")(2, "PLDL2KEEP")(3, "PLDL2STRM")(4, "PLDL3KEEP")(5, "PLDL3STRM")(8, "PLIL1KEEP")(9, "PLIL1STRM")(10, "PLIL2KEEP")(11, "PLIL2STRM")(12, "PLIL3KEEP")(13, "PLIL3STRM")(16, "PSTL1KEEP")(17, "PSTL1STRM")(18, "PSTL2KEEP")(19, "PSTL2STRM")(20, "PSTL3KEEP")(21, "PSTL3STRM").convert_to_container >(); + m_prfmTypeLookupMap = dyncompat::assign::map_list_of(0, "PLDL1KEEP")(1, "PLDL1STRM")(2, "PLDL2KEEP")(3, "PLDL2STRM")(4, "PLDL3KEEP")(5, "PLDL3STRM")(8, "PLIL1KEEP")(9, "PLIL1STRM")(10, "PLIL2KEEP")(11, "PLIL2STRM")(12, "PLIL3KEEP")(13, "PLIL3STRM")(16, "PSTL1KEEP")(17, "PSTL1STRM")(18, "PSTL2KEEP")(19, "PSTL2STRM")(20, "PSTL3KEEP")(21, "PSTL3STRM").convert_to_container >(); } Immediate::Ptr ArmPrfmTypeImmediate::makeArmPrfmTypeImmediate(const Result &val) { diff --git a/instructionAPI/src/Instruction.C b/instructionAPI/src/Instruction.C index 1063d77fc9..67525e3825 100644 --- a/instructionAPI/src/Instruction.C +++ b/instructionAPI/src/Instruction.C @@ -29,8 +29,6 @@ */ #define INSIDE_INSTRUCTION_API -// Needs to be the first include. -#include "common/src/Types.h" #include #include @@ -41,12 +39,12 @@ #include "Operation_impl.h" #include "InstructionDecoder.h" #include "Dereference.h" -#include #include #include #include #include #include +#include #include "common/src/arch-x86.h" #include "dyninstversion.h" @@ -57,622 +55,606 @@ using namespace NS_x86; #include "../../common/src/singleton_object_pool.h" #include "ArchSpecificFormatters.h" +#define DECODE_OPERANDS() \ + do { \ + if (arch_decoded_from != Arch_cuda && arch_decoded_from != Arch_amdgpu_gfx908 && arch_decoded_from != Arch_amdgpu_gfx90a && arch_decoded_from != Arch_amdgpu_gfx940 && m_Operands.empty()) { \ + decodeOperands(); \ + }\ + }while(0) + namespace Dyninst { - namespace InstructionAPI - { - - static const int IAPI_major_version = DYNINST_MAJOR_VERSION; - static const int IAPI_minor_version = DYNINST_MINOR_VERSION; - static const int IAPI_maintenance_version = DYNINST_PATCH_VERSION; - - void Instruction::version(int& major, int& minor, int& maintenance) - { - major = IAPI_major_version; - minor = IAPI_minor_version; - maintenance = IAPI_maintenance_version; - } - - int Instruction::numInsnsAllocated = 0; - INSTRUCTION_EXPORT Instruction::Instruction(Operation what, - size_t size, const unsigned char* raw, - Dyninst::Architecture arch) - : m_InsnOp(what), m_Valid(true), arch_decoded_from(arch), - formatter(ArchSpecificFormatter::getFormatter(arch)) + namespace InstructionAPI { - copyRaw(size, raw); -#if defined(DEBUG_INSN_ALLOCATIONS) - numInsnsAllocated++; - if((numInsnsAllocated % 1000) == 0) + static const int IAPI_major_version = DYNINST_MAJOR_VERSION; + static const int IAPI_minor_version = DYNINST_MINOR_VERSION; + static const int IAPI_maintenance_version = DYNINST_PATCH_VERSION; + + void Instruction::version(int& major, int& minor, int& maintenance) { - fprintf(stderr, "Instruction CTOR, %d insns allocated\n", numInsnsAllocated); + major = IAPI_major_version; + minor = IAPI_minor_version; + maintenance = IAPI_maintenance_version; } -#endif - } - void Instruction::copyRaw(size_t size, const unsigned char* raw) - { - - if(raw) - { - m_size = size; - m_RawInsn.small_insn = 0; - if(size <= sizeof(m_RawInsn.small_insn)) - { - memcpy(&m_RawInsn.small_insn, raw, size); - } - else - { - m_RawInsn.large_insn = new unsigned char[size]; - memcpy(m_RawInsn.large_insn, raw, size); - } - } - else - { - m_size = 0; - m_RawInsn.small_insn = 0; - } - } + int Instruction::numInsnsAllocated = 0; + INSTRUCTION_EXPORT Instruction::Instruction(Operation what, + size_t size, const unsigned char* raw, + Dyninst::Architecture arch) + : m_InsnOp(what), m_Valid(what.getID() != e_No_Entry), arch_decoded_from(arch), + formatter(&ArchSpecificFormatter::getFormatter(arch)) + { + copyRaw(size, raw); - void Instruction::decodeOperands() const - { - //m_Operands.reserve(5); - InstructionDecoder dec(ptr(), size(), arch_decoded_from); - dec.doDelayedDecode(this); - } - - INSTRUCTION_EXPORT Instruction::Instruction() : - m_Valid(false), m_size(0), arch_decoded_from(Arch_none), formatter(ArchSpecificFormatter::getFormatter(Arch_x86_64)) - { #if defined(DEBUG_INSN_ALLOCATIONS) - numInsnsAllocated++; - if((numInsnsAllocated % 1000) == 0) + numInsnsAllocated++; + if((numInsnsAllocated % 1000) == 0) + { + fprintf(stderr, "Instruction CTOR, %d insns allocated\n", numInsnsAllocated); + } +#endif + } + + void Instruction::copyRaw(size_t size, const unsigned char* raw) + { + + if(raw) + { + m_size = size; + m_RawInsn.small_insn = 0; + if(size <= sizeof(m_RawInsn.small_insn)) + { + memcpy(&m_RawInsn.small_insn, raw, size); + } + else + { + m_RawInsn.large_insn = new unsigned char[size]; + memcpy(m_RawInsn.large_insn, raw, size); + } + } + else + { + m_size = 0; + m_RawInsn.small_insn = 0; + } + } + + void Instruction::decodeOperands() const { - fprintf(stderr, "Instruction CTOR, %d insns allocated\n", numInsnsAllocated); + if (!m_Valid) return; + //m_Operands.reserve(5); + InstructionDecoder dec(ptr(), size(), arch_decoded_from); + dec.doDelayedDecode(this); } + + INSTRUCTION_EXPORT Instruction::Instruction() : + m_Valid(false), m_size(0), arch_decoded_from(Arch_none), formatter(nullptr) + { +#if defined(DEBUG_INSN_ALLOCATIONS) + numInsnsAllocated++; + if((numInsnsAllocated % 1000) == 0) + { + fprintf(stderr, "Instruction CTOR, %d insns allocated\n", numInsnsAllocated); + } #endif - } - - INSTRUCTION_EXPORT Instruction::~Instruction() - { + } + + INSTRUCTION_EXPORT Instruction::~Instruction() + { - if(m_size > sizeof(m_RawInsn.small_insn)) - { - delete[] m_RawInsn.large_insn; - } + if(m_size > sizeof(m_RawInsn.small_insn)) + { + delete[] m_RawInsn.large_insn; + } #if defined(DEBUG_INSN_ALLOCATIONS) - numInsnsAllocated--; - if((numInsnsAllocated % 1000) == 0) - { - fprintf(stderr, "Instruction DTOR, %d insns allocated\n", numInsnsAllocated); - } + numInsnsAllocated--; + if((numInsnsAllocated % 1000) == 0) + { + fprintf(stderr, "Instruction DTOR, %d insns allocated\n", numInsnsAllocated); + } #endif - } + } - INSTRUCTION_EXPORT Instruction::Instruction(const Instruction& o) : - m_Operands(o.m_Operands), - m_InsnOp(o.m_InsnOp), - m_Valid(o.m_Valid), - arch_decoded_from(o.arch_decoded_from), - formatter(o.formatter) + INSTRUCTION_EXPORT Instruction::Instruction(const Instruction& o) : + m_Operands(o.m_Operands), + m_InsnOp(o.m_InsnOp), + m_Valid(o.m_Valid), + arch_decoded_from(o.arch_decoded_from), + formatter(o.formatter) - { - m_size = o.m_size; - if(o.m_size > sizeof(m_RawInsn.small_insn)) - { - m_RawInsn.large_insn = new unsigned char[o.m_size]; - memcpy(m_RawInsn.large_insn, o.m_RawInsn.large_insn, m_size); - } - else - { - m_RawInsn.small_insn = o.m_RawInsn.small_insn; - } - - m_Successors = o.m_Successors; + { + m_size = o.m_size; + if(o.m_size > sizeof(m_RawInsn.small_insn)) + { + m_RawInsn.large_insn = new unsigned char[o.m_size]; + memcpy(m_RawInsn.large_insn, o.m_RawInsn.large_insn, m_size); + } + else + { + m_RawInsn.small_insn = o.m_RawInsn.small_insn; + } + + m_Successors = o.m_Successors; #if defined(DEBUG_INSN_ALLOCATIONS) - numInsnsAllocated++; - if((numInsnsAllocated % 1000) == 0) - { - fprintf(stderr, "Instruction COPY CTOR, %d insns allocated\n", numInsnsAllocated); - } + numInsnsAllocated++; + if((numInsnsAllocated % 1000) == 0) + { + fprintf(stderr, "Instruction COPY CTOR, %d insns allocated\n", numInsnsAllocated); + } #endif - } + } - INSTRUCTION_EXPORT const Instruction& Instruction::operator=(const Instruction& rhs) - { - m_Operands = rhs.m_Operands; - //m_Operands.reserve(rhs.m_Operands.size()); - //std::copy(rhs.m_Operands.begin(), rhs.m_Operands.end(), std::back_inserter(m_Operands)); - if(m_size > sizeof(m_RawInsn.small_insn)) - { - delete[] m_RawInsn.large_insn; - } - - m_size = rhs.m_size; - if(rhs.m_size > sizeof(m_RawInsn.small_insn)) - { - m_RawInsn.large_insn = new unsigned char[rhs.m_size]; - memcpy(m_RawInsn.large_insn, rhs.m_RawInsn.large_insn, m_size); - } - else - { - m_RawInsn.small_insn = rhs.m_RawInsn.small_insn; - } - - - m_InsnOp = rhs.m_InsnOp; - m_Valid = rhs.m_Valid; - formatter = rhs.formatter; - arch_decoded_from = rhs.arch_decoded_from; - m_Successors = rhs.m_Successors; - return *this; - } - - INSTRUCTION_EXPORT bool Instruction::isValid() const - { - return m_Valid; - } - - INSTRUCTION_EXPORT Operation& Instruction::getOperation() - { - return m_InsnOp; - } - INSTRUCTION_EXPORT const Operation& Instruction::getOperation() const - { - return m_InsnOp; - } + INSTRUCTION_EXPORT const Instruction& Instruction::operator=(const Instruction& rhs) + { + m_Operands = rhs.m_Operands; + //m_Operands.reserve(rhs.m_Operands.size()); + //std::copy(rhs.m_Operands.begin(), rhs.m_Operands.end(), std::back_inserter(m_Operands)); + if(m_size > sizeof(m_RawInsn.small_insn)) + { + delete[] m_RawInsn.large_insn; + } + + m_size = rhs.m_size; + if(rhs.m_size > sizeof(m_RawInsn.small_insn)) + { + m_RawInsn.large_insn = new unsigned char[rhs.m_size]; + memcpy(m_RawInsn.large_insn, rhs.m_RawInsn.large_insn, m_size); + } + else + { + m_RawInsn.small_insn = rhs.m_RawInsn.small_insn; + } + + + m_InsnOp = rhs.m_InsnOp; + m_Valid = rhs.m_Valid; + formatter = rhs.formatter; + arch_decoded_from = rhs.arch_decoded_from; + m_Successors = rhs.m_Successors; + return *this; + } + + INSTRUCTION_EXPORT bool Instruction::isValid() const + { + return m_Valid; + } - INSTRUCTION_EXPORT void Instruction::getOperands(std::vector& operands) const - { - if (arch_decoded_from != Arch_cuda && m_Operands.empty()) { - decodeOperands(); - } - - std::copy(m_Operands.begin(), m_Operands.end(), std::back_inserter(operands)); - } - - INSTRUCTION_EXPORT Operand Instruction::getOperand(int index) const - { - if (arch_decoded_from != Arch_cuda && m_Operands.empty()) { - decodeOperands(); - } + INSTRUCTION_EXPORT Operation& Instruction::getOperation() + { + return m_InsnOp; + } + INSTRUCTION_EXPORT const Operation& Instruction::getOperation() const + { + return m_InsnOp; + } - if(index < 0 || index >= (int)(m_Operands.size())) + INSTRUCTION_EXPORT void Instruction::getOperands(std::vector& operands) const { - // Out of range = empty operand - return Operand(Expression::Ptr(), false, false); + + DECODE_OPERANDS(); + std::copy(m_Operands.begin(), m_Operands.end(), std::back_inserter(operands)); } - std::list::const_iterator found = m_Operands.begin(); - std::advance(found, index); - return *found; - } - - INSTRUCTION_EXPORT const void* Instruction::ptr() const - { - if(m_size > sizeof(m_RawInsn.small_insn)) - { - return m_RawInsn.large_insn; - } - else - { - return reinterpret_cast(&m_RawInsn.small_insn); - } - } - INSTRUCTION_EXPORT unsigned char Instruction::rawByte(unsigned int index) const - { - if(index >= m_size) return 0; - if(m_size > sizeof(m_RawInsn.small_insn)) - { - return m_RawInsn.large_insn[index]; - } - else - { - return reinterpret_cast(&m_RawInsn.small_insn)[index]; - } - } - - INSTRUCTION_EXPORT size_t Instruction::size() const - { - return m_size; - - } - - INSTRUCTION_EXPORT void Instruction::getReadSet(std::set& regsRead) const - { - if (arch_decoded_from != Arch_cuda && m_Operands.empty()) { - decodeOperands(); - } - - for(std::list::const_iterator curOperand = m_Operands.begin(); - curOperand != m_Operands.end(); - ++curOperand) - { - curOperand->getReadSet(regsRead); - } - std::copy(m_InsnOp.implicitReads().begin(), m_InsnOp.implicitReads().end(), - std::inserter(regsRead, regsRead.begin())); - - } - - INSTRUCTION_EXPORT void Instruction::getWriteSet(std::set& regsWritten) const - { - if (arch_decoded_from != Arch_cuda && m_Operands.empty()) { - decodeOperands(); - } - - for(std::list::const_iterator curOperand = m_Operands.begin(); - curOperand != m_Operands.end(); - ++curOperand) - { - curOperand->getWriteSet(regsWritten); - } - std::copy(m_InsnOp.implicitWrites().begin(), m_InsnOp.implicitWrites().end(), - std::inserter(regsWritten, regsWritten.begin())); - - } - - INSTRUCTION_EXPORT bool Instruction::isRead(Expression::Ptr candidate) const - { - if (arch_decoded_from != Arch_cuda && m_Operands.empty()) { - decodeOperands(); - } - - for(std::list::const_iterator curOperand = m_Operands.begin(); - curOperand != m_Operands.end(); - ++curOperand) - { - if(curOperand->isRead(candidate)) - { - return true; - } - } - return m_InsnOp.isRead(candidate); - } - INSTRUCTION_EXPORT bool Instruction::isWritten(Expression::Ptr candidate) const - { - if (arch_decoded_from != Arch_cuda && m_Operands.empty()) { - decodeOperands(); - } - - for(std::list::const_iterator curOperand = m_Operands.begin(); - curOperand != m_Operands.end(); - ++curOperand) - { - if(curOperand->isWritten(candidate)) - { - return true; - } - } - return m_InsnOp.isWritten(candidate); - } - - INSTRUCTION_EXPORT bool Instruction::readsMemory() const - { - if (arch_decoded_from != Arch_cuda && m_Operands.empty()) { - decodeOperands(); - } - - if(getCategory() == c_PrefetchInsn) - { - return false; - } - for(std::list::const_iterator curOperand = m_Operands.begin(); - curOperand != m_Operands.end(); - ++curOperand) - { - if(curOperand->readsMemory()) - { - return true; - } - } - return !m_InsnOp.getImplicitMemReads().empty(); - } - - INSTRUCTION_EXPORT bool Instruction::writesMemory() const - { - if (arch_decoded_from != Arch_cuda && m_Operands.empty()) { - decodeOperands(); - } - - for(std::list::const_iterator curOperand = m_Operands.begin(); - curOperand != m_Operands.end(); - ++curOperand) - { - if(curOperand->writesMemory()) - { - return true; - } - } - return !m_InsnOp.getImplicitMemWrites().empty(); - } - - INSTRUCTION_EXPORT void Instruction::getMemoryReadOperands(std::set& memAccessors) const - { - if (arch_decoded_from != Arch_cuda && m_Operands.empty()) { - decodeOperands(); - } - - for(std::list::const_iterator curOperand = m_Operands.begin(); - curOperand != m_Operands.end(); - ++curOperand) - { - curOperand->addEffectiveReadAddresses(memAccessors); - } - std::copy(m_InsnOp.getImplicitMemReads().begin(), m_InsnOp.getImplicitMemReads().end(), std::inserter(memAccessors, -memAccessors.begin())); - } - - INSTRUCTION_EXPORT void Instruction::getMemoryWriteOperands(std::set& memAccessors) const - { - if (arch_decoded_from != Arch_cuda && m_Operands.empty()) { - decodeOperands(); - } - - for(std::list::const_iterator curOperand = m_Operands.begin(); - curOperand != m_Operands.end(); - ++curOperand) - { - curOperand->addEffectiveWriteAddresses(memAccessors); - } - std::copy(m_InsnOp.getImplicitMemWrites().begin(), m_InsnOp.getImplicitMemWrites().end(), std::inserter(memAccessors, -memAccessors.begin())); - } + INSTRUCTION_EXPORT std::vector Instruction::getDisplayOrderedOperands() const + { + DECODE_OPERANDS(); - INSTRUCTION_EXPORT Operand Instruction::getPredicateOperand() const - { - if (arch_decoded_from != Arch_cuda && m_Operands.empty()) { - decodeOperands(); - } + std::vector operands; + auto operandsInserter{std::back_inserter(operands)}; + auto isNotImplicitPred = [](const Operand & x){return !x.isImplicit();}; + + if (formatter->operandPrintOrderReversed()) { + copy_if(m_Operands.crbegin(), m_Operands.crend(), operandsInserter, isNotImplicitPred); + } else { + copy_if(m_Operands.cbegin(), m_Operands.cend(), operandsInserter, isNotImplicitPred); + } - for(auto const &op : m_Operands) { - if (op.isTruePredicate() || op.isFalsePredicate()) { - return op; + return operands; } - } - return Operand(Expression::Ptr(), false, false); - } - INSTRUCTION_EXPORT bool Instruction::hasPredicateOperand() const - { - if (arch_decoded_from != Arch_cuda && m_Operands.empty()) { - decodeOperands(); - } + INSTRUCTION_EXPORT Operand Instruction::getOperand(int index) const + { + DECODE_OPERANDS(); + if(index < 0 || index >= (int)(m_Operands.size())) + { + // Out of range = empty operand + return Operand(Expression::Ptr(), false, false); + } + std::list::const_iterator found = m_Operands.begin(); + std::advance(found, index); + return *found; + } - for(auto const &op : m_Operands) { - if (op.isTruePredicate() || op.isFalsePredicate()) { - return true; + INSTRUCTION_EXPORT const void* Instruction::ptr() const + { + if(m_size > sizeof(m_RawInsn.small_insn)) + { + return m_RawInsn.large_insn; + } + else + { + return reinterpret_cast(&m_RawInsn.small_insn); + } + } + INSTRUCTION_EXPORT unsigned char Instruction::rawByte(unsigned int index) const + { + if(index >= m_size) return 0; + if(m_size > sizeof(m_RawInsn.small_insn)) + { + return m_RawInsn.large_insn[index]; + } + else + { + return reinterpret_cast(&m_RawInsn.small_insn)[index]; + } } - } - return false; - } + INSTRUCTION_EXPORT size_t Instruction::size() const + { + return m_size; - INSTRUCTION_EXPORT Expression::Ptr Instruction::getControlFlowTarget() const - { - // We assume control flow transfer instructions have the PC as - // an implicit write, and that we have decoded the control flow - // target's full location as the first and only operand. - // If this is not the case, we'll squawk for the time being... - if(getCategory() == c_NoCategory || - getCategory() == c_CompareInsn || - getCategory() == c_PrefetchInsn) + } + + INSTRUCTION_EXPORT void Instruction::getReadSet(std::set& regsRead) const { - return Expression::Ptr(); + DECODE_OPERANDS(); + for(std::list::const_iterator curOperand = m_Operands.begin(); + curOperand != m_Operands.end(); + ++curOperand) + { + curOperand->getReadSet(regsRead); + } + std::copy(m_InsnOp.implicitReads().begin(), m_InsnOp.implicitReads().end(), + std::inserter(regsRead, regsRead.begin())); + } - if(getCategory() == c_ReturnInsn) + + INSTRUCTION_EXPORT void Instruction::getWriteSet(std::set& regsWritten) const + { + DECODE_OPERANDS(); + for(std::list::const_iterator curOperand = m_Operands.begin(); + curOperand != m_Operands.end(); + ++curOperand) + { + curOperand->getWriteSet(regsWritten); + } + std::copy(m_InsnOp.implicitWrites().begin(), m_InsnOp.implicitWrites().end(), + std::inserter(regsWritten, regsWritten.begin())); + + } + + INSTRUCTION_EXPORT bool Instruction::isRead(Expression::Ptr candidate) const { - return makeReturnExpression(); + DECODE_OPERANDS(); + for(std::list::const_iterator curOperand = m_Operands.begin(); + curOperand != m_Operands.end(); + ++curOperand) + { + // Check if the candidate is read as an explicit operand + if(curOperand->isRead(candidate)) + { + return true; + } + } + // Check if the candidate is read as an implicit operand + return m_InsnOp.isRead(candidate); } - if (arch_decoded_from != Arch_cuda && m_Operands.empty()) { - decodeOperands(); + + INSTRUCTION_EXPORT bool Instruction::isWritten(Expression::Ptr candidate) const + { + DECODE_OPERANDS(); + + for(std::list::const_iterator curOperand = m_Operands.begin(); + curOperand != m_Operands.end(); + ++curOperand) + { + if(curOperand->isWritten(candidate)) + { + return true; + } + } + return m_InsnOp.isWritten(candidate); } - if(m_Successors.empty()) + INSTRUCTION_EXPORT bool Instruction::readsMemory() const { - return Expression::Ptr(); + DECODE_OPERANDS(); + if(getCategory() == c_PrefetchInsn) + { + return false; + } + for(std::list::const_iterator curOperand = m_Operands.begin(); + curOperand != m_Operands.end(); + ++curOperand) + { + if(curOperand->readsMemory()) + { + return true; + } + } + return !m_InsnOp.getImplicitMemReads().empty(); } - return m_Successors.front().target; - } - INSTRUCTION_EXPORT ArchSpecificFormatter& Instruction::getFormatter() const { - return formatter; - } + INSTRUCTION_EXPORT bool Instruction::writesMemory() const + { + DECODE_OPERANDS(); + for(std::list::const_iterator curOperand = m_Operands.begin(); + curOperand != m_Operands.end(); + ++curOperand) + { + if(curOperand->writesMemory()) + { + return true; + } + } + return !m_InsnOp.getImplicitMemWrites().empty(); + } - INSTRUCTION_EXPORT std::string Instruction::format(Address addr) const - { - if (arch_decoded_from != Arch_cuda && m_Operands.empty()) { - decodeOperands(); + INSTRUCTION_EXPORT void Instruction::getMemoryReadOperands(std::set& memAccessors) const + { + DECODE_OPERANDS(); + for(std::list::const_iterator curOperand = m_Operands.begin(); + curOperand != m_Operands.end(); + ++curOperand) + { + curOperand->addEffectiveReadAddresses(memAccessors); + } + std::copy(m_InsnOp.getImplicitMemReads().begin(), m_InsnOp.getImplicitMemReads().end(), std::inserter(memAccessors, + memAccessors.begin())); } - //remove this once ArchSpecificFormatter is extended for all architectures + INSTRUCTION_EXPORT void Instruction::getMemoryWriteOperands(std::set& memAccessors) const + { + DECODE_OPERANDS(); + for(std::list::const_iterator curOperand = m_Operands.begin(); + curOperand != m_Operands.end(); + ++curOperand) + { + curOperand->addEffectiveWriteAddresses(memAccessors); + } + std::copy(m_InsnOp.getImplicitMemWrites().begin(), m_InsnOp.getImplicitMemWrites().end(), std::inserter(memAccessors, + memAccessors.begin())); + } - std::string opstr = m_InsnOp.format(); - opstr += " "; - std::list::const_iterator currOperand; - std::vector formattedOperands; - int op = 0; - for(currOperand = m_Operands.begin(); - currOperand != m_Operands.end(); - op++, ++currOperand) + INSTRUCTION_EXPORT Operand Instruction::getPredicateOperand() const { - /* If this operand is implicit, don't put it in the list of operands. */ - if(currOperand->isImplicit()) - continue; + DECODE_OPERANDS(); + for(auto const &op : m_Operands) { + if (op.isTruePredicate() || op.isFalsePredicate()) { + return op; + } + } + + return Operand(Expression::Ptr(), false, false); + } + INSTRUCTION_EXPORT bool Instruction::hasPredicateOperand() const + { + DECODE_OPERANDS(); + for(auto const &op : m_Operands) { + if (op.isTruePredicate() || op.isFalsePredicate()) { + return true; + } + } + + return false; + } + + INSTRUCTION_EXPORT Expression::Ptr Instruction::getControlFlowTarget() const + { + // We assume control flow transfer instructions have the PC as + // an implicit write, and that we have decoded the control flow + // target's full location as the first and only operand. + // If this is not the case, we'll squawk for the time being... + if(getCategory() == c_NoCategory || + getCategory() == c_CompareInsn || + getCategory() == c_PrefetchInsn) + { + return Expression::Ptr(); + } + if(getCategory() == c_ReturnInsn) + { + return makeReturnExpression(); + } + DECODE_OPERANDS(); + if(m_Successors.empty()) + { + return Expression::Ptr(); + } + return m_Successors.front().target; + } - formattedOperands.push_back(currOperand->format(getArch(), addr)); + INSTRUCTION_EXPORT ArchSpecificFormatter& Instruction::getFormatter() const { + return *formatter; } + INSTRUCTION_EXPORT std::string Instruction::format(Address addr) const + { + // if Arch_none, this is an error and the formatter is nullptr, + // so return an error string (could also abort or except) + if (arch_decoded_from == Arch_none) { + return "ERROR_NO_ARCH_SET_FOR_INSTRUCTION"; + } + + DECODE_OPERANDS(); + //remove this once ArchSpecificFormatter is extended for all architectures + + std::string opstr = m_InsnOp.format(); + opstr += " "; + std::list::const_iterator currOperand; + std::vector formattedOperands; + for(currOperand = m_Operands.begin(); + currOperand != m_Operands.end(); + ++currOperand) + { + /* If this operand is implicit, don't put it in the list of operands. */ + if(currOperand->isImplicit()) + continue; + + formattedOperands.push_back(currOperand->format(getArch(), addr)); + } + #if defined(DEBUG_READ_WRITE) - std::set tmp; - getReadSet(tmp); - cout << "Read set:" << endl; - for(std::set::iterator i = tmp.begin(); - i != tmp.end(); - ++i) - { - cout << (*i)->format() << " "; - } - cout << endl; - tmp.clear(); - getWriteSet(tmp); - cout << "Write set:" << endl; - for(std::set::iterator i = tmp.begin(); - i != tmp.end(); - ++i) - { - cout << (*i)->format() << " "; - } - cout << endl; - std::set mem; - getMemoryReadOperands(mem); - cout << "Read mem:" << endl; - for(std::set::iterator i = mem.begin(); - i != mem.end(); - ++i) - { - cout << (*i)->format() << " "; - } - cout << endl; - mem.clear(); - getMemoryWriteOperands(mem); - cout << "Write mem:" << endl; - for(std::set::iterator i = mem.begin(); - i != mem.end(); - ++i) - { - cout << (*i)->format() << " "; - } - cout << endl; + std::set tmp; + getReadSet(tmp); + cout << "Read set:" << endl; + for(std::set::iterator i = tmp.begin(); + i != tmp.end(); + ++i) + { + cout << (*i)->format() << " "; + } + cout << endl; + tmp.clear(); + getWriteSet(tmp); + cout << "Write set:" << endl; + for(std::set::iterator i = tmp.begin(); + i != tmp.end(); + ++i) + { + cout << (*i)->format() << " "; + } + cout << endl; + std::set mem; + getMemoryReadOperands(mem); + cout << "Read mem:" << endl; + for(std::set::iterator i = mem.begin(); + i != mem.end(); + ++i) + { + cout << (*i)->format() << " "; + } + cout << endl; + mem.clear(); + getMemoryWriteOperands(mem); + cout << "Write mem:" << endl; + for(std::set::iterator i = mem.begin(); + i != mem.end(); + ++i) + { + cout << (*i)->format() << " "; + } + cout << endl; #endif // defined(DEBUG_READ_WRITE) - return opstr + formatter.getInstructionString(formattedOperands); - } + return opstr + formatter->getInstructionString(formattedOperands); + } - INSTRUCTION_EXPORT bool Instruction::allowsFallThrough() const - { - switch(m_InsnOp.getID()) - { - case e_ret_far: - case e_ret_near: - case e_iret: - case e_jmp: - case e_hlt: - case e_sysret: - case e_sysexit: - case e_call: - case e_syscall: - case amdgpu_op_s_swappc_b64: - return false; - case e_jnb: - case e_jb: - case e_jb_jnaej_j: - case e_jbe: - case e_jcxz_jec: - case e_jl: - case e_jle: - case e_jnb_jae_j: - case e_jnbe: - case e_jnl: - case e_jnle: - case e_jno: - case e_jnp: - case e_jns: - case e_jnz: - case e_jo: - case e_jp: - case e_js: - case e_jz: - return true; - default: - { - if (arch_decoded_from != Arch_cuda && m_Operands.empty()) { - decodeOperands(); - } - for(cftConstIter targ = m_Successors.begin(); - targ != m_Successors.end(); - ++targ) - { - if(targ->isFallthrough) return true; - } - return m_Successors.empty(); - } - } - // can't happen but make the compiler happy - return false; - } - INSTRUCTION_EXPORT bool Instruction::isLegalInsn() const - { - return (m_InsnOp.getID() != e_No_Entry); - } + INSTRUCTION_EXPORT bool Instruction::allowsFallThrough() const + { + switch(m_InsnOp.getID()) + { + case e_ret_far: + case e_ret_near: + case e_iret: + case e_jmp: + case e_hlt: + case e_sysret: + case e_sysexit: + case e_call: + case e_syscall: + case amdgpu_gfx908_op_S_SETPC_B64: + case amdgpu_gfx908_op_S_SWAPPC_B64: + case amdgpu_gfx90a_op_S_SETPC_B64: + case amdgpu_gfx90a_op_S_SWAPPC_B64: + case amdgpu_gfx940_op_S_SETPC_B64: + case amdgpu_gfx940_op_S_SWAPPC_B64: + return false; + case e_jae: + case e_jb: + case e_jb_jnaej_j: + case e_jbe: + case e_jcxz_jec: + case e_jl: + case e_jle: + case e_jnb_jae_j: + case e_ja: + case e_jge: + case e_jg: + case e_jno: + case e_jnp: + case e_jns: + case e_jne: + case e_jo: + case e_jp: + case e_js: + case e_je: + return true; + default: + { + DECODE_OPERANDS(); + for(cftConstIter targ = m_Successors.begin(); + targ != m_Successors.end(); + ++targ) + { + if(targ->isFallthrough) return true; + } + return m_Successors.empty(); + } + } + // can't happen but make the compiler happy + return false; + } + INSTRUCTION_EXPORT bool Instruction::isLegalInsn() const + { + return (m_InsnOp.getID() != e_No_Entry); + } - INSTRUCTION_EXPORT Architecture Instruction::getArch() const { - return arch_decoded_from; - } + INSTRUCTION_EXPORT Architecture Instruction::getArch() const { + return arch_decoded_from; + } - Expression::Ptr Instruction::makeReturnExpression() const - { - Expression::Ptr stackPtr = Expression::Ptr(new RegisterAST(MachRegister::getStackPointer(arch_decoded_from), - 0, MachRegister::getStackPointer(arch_decoded_from).size())); - Expression::Ptr retLoc = Expression::Ptr(new Dereference(stackPtr, u32)); - return retLoc; - } - INSTRUCTION_EXPORT InsnCategory Instruction::getCategory() const - { - if(m_InsnOp.isVectorInsn) return c_VectorInsn; - InsnCategory c = entryToCategory(m_InsnOp.getID()); - if(c == c_BranchInsn && (arch_decoded_from == Arch_ppc32 || arch_decoded_from == Arch_ppc64)) - { - if (arch_decoded_from != Arch_cuda && m_Operands.empty()) { - decodeOperands(); - } - for(cftConstIter cft = cft_begin(); - cft != cft_end(); - ++cft) - { - if(cft->isCall) - { - return c_CallInsn; - } - } - if(m_InsnOp.getID() == power_op_bclr) - { - return c_ReturnInsn; - } - } - return c; - } - void Instruction::addSuccessor(Expression::Ptr e, - bool isCall, - bool isIndirect, - bool isConditional, - bool isFallthrough) const - { - CFT c(e, isCall, isIndirect, isConditional, isFallthrough); - m_Successors.push_back(c); - if (!isFallthrough) appendOperand(e, true, false); - } - void Instruction::appendOperand(Expression::Ptr e, bool isRead, bool isWritten) const - { - m_Operands.push_back(Operand(e, isRead, isWritten)); - } + Expression::Ptr Instruction::makeReturnExpression() const + { + Expression::Ptr stackPtr = Expression::Ptr(new RegisterAST(MachRegister::getStackPointer(arch_decoded_from), + 0, MachRegister::getStackPointer(arch_decoded_from).size())); + Expression::Ptr retLoc = Expression::Ptr(new Dereference(stackPtr, u32)); + return retLoc; + } + INSTRUCTION_EXPORT InsnCategory Instruction::getCategory() const + { + if(m_InsnOp.isVectorInsn) return c_VectorInsn; + InsnCategory c = entryToCategory(m_InsnOp.getID()); + if(c == c_BranchInsn && (arch_decoded_from == Arch_ppc32 || arch_decoded_from == Arch_ppc64)) + { + DECODE_OPERANDS(); + for(cftConstIter cft = cft_begin(); + cft != cft_end(); + ++cft) + { + if(cft->isCall) + { + return c_CallInsn; + } + } + if(m_InsnOp.getID() == power_op_bclr) + { + return c_ReturnInsn; + } + } + return c; + } + void Instruction::addSuccessor(Expression::Ptr e, + bool isCall, + bool isIndirect, + bool isConditional, + bool isFallthrough, + bool isImplicit) const + { + CFT c(e, isCall, isIndirect, isConditional, isFallthrough); + m_Successors.push_back(c); + if (!isFallthrough) appendOperand(e, true, false, isImplicit); + } - void Instruction::appendOperand(Expression::Ptr e, - bool isRead, bool isWritten, bool isImplicit) const - { - m_Operands.push_back(Operand(e, isRead, isWritten, isImplicit)); - } - - void Instruction::appendOperand(Expression::Ptr e, - bool isRead, bool isWritten, bool isImplicit, bool trueP, bool falseP) const - { - m_Operands.push_back(Operand(e, isRead, isWritten, isImplicit, trueP, falseP)); - } + void Instruction::appendOperand(Expression::Ptr e, + bool isRead, bool isWritten, bool isImplicit, bool trueP, bool falseP) const + { + m_Operands.push_back(Operand(e, isRead, isWritten, isImplicit, trueP, falseP)); + } - } + } } diff --git a/instructionAPI/src/InstructionCategories.C b/instructionAPI/src/InstructionCategories.C index d0de937d91..1d4e5f27a3 100644 --- a/instructionAPI/src/InstructionCategories.C +++ b/instructionAPI/src/InstructionCategories.C @@ -43,7 +43,9 @@ namespace Dyninst case e_ret_far: case aarch64_op_ret: return c_ReturnInsn; - case amdgpu_op_s_endpgm: // special treatment for endpgm + case amdgpu_gfx908_op_S_ENDPGM: // special treatment for endpgm + case amdgpu_gfx90a_op_S_ENDPGM: // special treatment for endpgm + case amdgpu_gfx940_op_S_ENDPGM: // special treatment for endpgm return c_GPUKernelExitInsn; case e_call: case aarch64_op_bl: @@ -56,23 +58,22 @@ namespace Dyninst case e_jcxz_jec: case e_jl: case e_jle: - case e_jmpe: - case e_jnb: + case e_jae: case e_jnb_jae_j: - case e_jnbe: - case e_jnl: - case e_jnle: + case e_ja: + case e_jge: + case e_jg: case e_jno: case e_jnp: case e_jns: - case e_jnz: + case e_jne: case e_jo: case e_jp: case e_js: - case e_jz: + case e_je: case e_loop: case e_loope: - case e_loopn: + case e_loopne: case aarch64_op_b_uncond: case aarch64_op_b_cond: case aarch64_op_tbz: @@ -89,18 +90,18 @@ namespace Dyninst case e_cmpsd: case e_cmpss: case e_cmpsw: - case e_cmpxch: - case e_cmpxch8b: + case e_cmpxchg: + case e_cmpxchg8b: case power_op_cmp: case power_op_cmpi: case power_op_cmpl: case power_op_cmpli: return c_CompareInsn; case e_prefetch: - case e_prefetchNTA: - case e_prefetchT0: - case e_prefetchT1: - case e_prefetchT2: + case e_prefetchnta: + case e_prefetcht0: + case e_prefetcht1: + case e_prefetcht2: case e_prefetch_w: case e_prefetchw: return c_PrefetchInsn; @@ -112,6 +113,7 @@ namespace Dyninst case e_sysenter: return c_SysEnterInsn; case e_syscall: + case e_int: return c_SyscallInsn; default: return c_NoCategory; diff --git a/instructionAPI/src/InstructionDecoder-aarch64.C b/instructionAPI/src/InstructionDecoder-aarch64.C index 502738e94d..d42bfeefee 100644 --- a/instructionAPI/src/InstructionDecoder-aarch64.C +++ b/instructionAPI/src/InstructionDecoder-aarch64.C @@ -29,6 +29,8 @@ */ #include "InstructionDecoder-aarch64.h" +#include +#include "registers/aarch64_regs.h" namespace Dyninst { namespace InstructionAPI { @@ -303,12 +305,12 @@ namespace Dyninst { void InstructionDecoder_aarch64::processOptionFieldLSRegOffsetInsn() { if (optionField == 0x3) //option = LSL { - int sizeVal = field<30, 31>(insn), extend; + int sizeVal = field<30, 31>(insn); if (field<23, 23>(insn) == 1) sizeVal = 4; - extend = sField * sizeVal; + unsigned extend = sField * sizeVal; int extendSize = 31; while (extendSize >= 0 && ((extend << (31 - extendSize)) & 0x80000000) == 0) extendSize--; @@ -2870,7 +2872,7 @@ Expression::Ptr InstructionDecoder_aarch64::makeMemRefExPair2(){ uint64_t imm = 0; for (int imm_index = 0; imm_index < 8; imm_index++) - imm |= (simdAlphabetImm & (1 << imm_index)) ? (0xFF << (imm_index * 8)) : 0; + imm |= (simdAlphabetImm & (1 << imm_index)) ? (0xFFULL << (imm_index * 8)) : 0; insn_in_progress->appendOperand(Immediate::makeImmediate(Result(u64, imm)), true, false); } @@ -2960,7 +2962,7 @@ Expression::Ptr InstructionDecoder_aarch64::makeMemRefExPair2(){ skipRm = true; for (std::size_t i = 0; i < insn_table_entry.operandCnt; i++) { - std::mem_fun(insn_table_entry.operands[i])(this); + std::mem_fn(insn_table_entry.operands[i])(this); } if (insn_table_index == 0) diff --git a/instructionAPI/src/InstructionDecoder-aarch64.h b/instructionAPI/src/InstructionDecoder-aarch64.h index 7994d0b1cc..ab58125ba2 100644 --- a/instructionAPI/src/InstructionDecoder-aarch64.h +++ b/instructionAPI/src/InstructionDecoder-aarch64.h @@ -28,10 +28,13 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include +#include +#include #include "InstructionDecoderImpl.h" #include #include "Immediate.h" -#include "dyn_regs.h" +#include "registers/MachRegister.h" namespace Dyninst { namespace InstructionAPI { @@ -151,24 +154,24 @@ namespace Dyninst { private: virtual Result_Type makeSizeType(unsigned int opType); - bool isPstateRead, isPstateWritten; - bool isFPInsn, isSIMDInsn; - bool skipRn, skipRm; - bool is64Bit; - bool isValid; + bool isPstateRead{}, isPstateWritten{}; + bool isFPInsn{}, isSIMDInsn{}; + bool skipRn{}, skipRm{}; + bool is64Bit{}; + bool isValid{}; void mainDecode(); int findInsnTableIndex(unsigned int); /*members for handling operand re-ordering, will be removed later once a generic operand ordering method is incorporated*/ - int oprRotateAmt; - bool hasb5; + int oprRotateAmt{}; + bool hasb5{}; void reorderOperands(); - unsigned int insn; - boost::shared_ptr insn_in_progress; + unsigned int insn{}; + dyncompat::shared_ptr insn_in_progress; template int field(unsigned int raw) { @@ -219,42 +222,42 @@ namespace Dyninst { return -1; } - int op1Field, op2Field, crmField; + int op1Field{}, op2Field{}, crmField{}; void processSystemInsn(); - bool hasHw; - int hwField; + bool hasHw{}; + int hwField{}; void processHwFieldInsn(int, int); - bool hasShift; - int shiftField; + bool hasShift{}; + int shiftField{}; void processShiftFieldShiftedInsn(int, int); void processShiftFieldImmInsn(int, int); - bool hasOption; - int optionField; + bool hasOption{}; + int optionField{}; void processOptionFieldLSRegOffsetInsn(); - bool hasN; - int immr, immrLen; - int sField, nField, nLen; + bool hasN{}; + int immr, immrLen{}; + int sField{}, nField{}, nLen{}; - int immlo, immloLen; + int immlo{}, immloLen{}; void makeBranchTarget(bool, bool, int, int); Expression::Ptr makeFallThroughExpr(); - int _szField, size; - int _typeField; - int cmode; - int op; - int simdAlphabetImm; + int _szField{}, size{}; + int _typeField{}; + int cmode{}; + int op{}; + int simdAlphabetImm{}; void processAlphabetImm(); @@ -502,9 +505,9 @@ namespace Dyninst { void setFlags(); - unsigned int _Q; - unsigned int _L; - unsigned int _R; + unsigned int _Q{}; + unsigned int _L{}; + unsigned int _R{}; void getSIMD_MULT_RptSelem(unsigned int &rpt, unsigned int &selem); diff --git a/instructionAPI/src/InstructionDecoder-amdgpu-vega.C b/instructionAPI/src/InstructionDecoder-amdgpu-vega.C deleted file mode 100644 index 79ec72be3d..0000000000 --- a/instructionAPI/src/InstructionDecoder-amdgpu-vega.C +++ /dev/null @@ -1,755 +0,0 @@ -/* - * See the dyninst/COPYRIGHT file for copyright information. - * - * We provide the Paradyn Tools (below described as "Paradyn") - * on an AS IS basis, and do not warrant its validity or performance. - * We reserve the right to update, modify, or discontinue this - * software at any time. We shall have no obligation to supply such - * updates or modifications or any other form of support to you. - * - * By your use of Paradyn, you understand and agree that we (or any - * other person or entity with proprietary rights in Paradyn) are - * under no obligation to provide either maintenance services, - * update services, notices of latent defects, or correction of - * defects for Paradyn. - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include "Ternary.h" -#include "InstructionDecoder-amdgpu-vega.h" - -namespace Dyninst { - namespace InstructionAPI { - typedef void (InstructionDecoder_amdgpu_vega::*operandFactory)(); - - typedef amdgpu_insn_entry amdgpu_insn_table[]; - typedef amdgpu_mask_entry amdgpu_decoder_table[]; - - const std::array InstructionDecoder_amdgpu_vega::condNames = { { - "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", "hi", "ls", "ge", - "lt", "gt", "le", "al", "nv", - } }; - - const char* InstructionDecoder_amdgpu_vega::bitfieldInsnAliasMap(entryID e) { - switch(e) { - default: assert(!"no alias for entryID"); - }; - } - const char* InstructionDecoder_amdgpu_vega::condInsnAliasMap(entryID e) { - switch(e) { - default: assert(!"no alias for entryID"); - }; - } - -#include "amdgpu_insn_entry.h" - struct amdgpu_mask_entry { - unsigned int mask; - std::size_t branchCnt; - const std::pair* nodeBranches; - int insnTableIndex; - - static const amdgpu_decoder_table main_decoder_table; - static const std::pair branchTable[]; - }; - -#include "amdgpu_opcode_tables.C" - - InstructionDecoder_amdgpu_vega::InstructionDecoder_amdgpu_vega(Architecture a) - : InstructionDecoderImpl(a), - insn_size(0), immLen(0) , num_elements(1) , isSMEM(false), isLoad(false), isStore(false),isBuffer(false), - isScratch(false) , isBranch(false), isConditional(false) ,isCall(false), isModifyPC(false) - { - } - - InstructionDecoder_amdgpu_vega::~InstructionDecoder_amdgpu_vega() { - } - - - using namespace std; - void InstructionDecoder_amdgpu_vega::NOTHING() { - } - - Result_Type InstructionDecoder_amdgpu_vega::makeSizeType(unsigned int) { - assert(0); //not implemented - return u32; - } - - // **************** - // decoding opcodes - // **************** - - MachRegister InstructionDecoder_amdgpu_vega::makeAmdgpuRegID(MachRegister base, unsigned int encoding , unsigned int len) { - MachRegister realBase = base; - if (base == amdgpu_vega::sgpr0){ - switch(len){ - case 2: - realBase = amdgpu_vega::sgpr_vec2_0; - break; - case 4: - realBase = amdgpu_vega::sgpr_vec4_0; - break; - case 8: - realBase = amdgpu_vega::sgpr_vec8_0; - break; - case 16: - realBase = amdgpu_vega::sgpr_vec16_0; - break; - } - }else if (base == amdgpu_vega::vgpr0){ - switch(len){ - case 2: - realBase = amdgpu_vega::vgpr_vec2_0; - break; - case 4: - realBase = amdgpu_vega::vgpr_vec4_0; - break; - case 8: - realBase = amdgpu_vega::vgpr_vec8_0; - break; - case 16: - realBase = amdgpu_vega::vgpr_vec16_0; - break; - } - - } - return MachRegister(realBase.val() + encoding); - - } - - Expression::Ptr InstructionDecoder_amdgpu_vega::makePCExpr() { - MachRegister baseReg = amdgpu_vega::pc; - - return makeRegisterExpression(baseReg); - } - - void InstructionDecoder_amdgpu_vega::makeBranchTarget(bool branchIsCall, bool bIsConditional, int immVal, - int immLen_ = 16) { - Expression::Ptr lhs = makeAddExpression(makePCExpr(),Immediate::makeImmediate(Result(s48,4)),s48); - int64_t offset = sign_extend64(immLen_, immVal * 4); - - Expression::Ptr rhs = Immediate::makeImmediate(Result(s64, offset)); - - insn_in_progress->addSuccessor(makeAddExpression(lhs, rhs, s64), branchIsCall, false, bIsConditional, - false); - if (bIsConditional || branchIsCall) { - insn_in_progress->addSuccessor(makeFallThroughExpr(), false, false, false, true); - } - - } - - Expression::Ptr InstructionDecoder_amdgpu_vega::makeFallThroughExpr() { - // TODO: while s_call_B64 is always 4 bytes, it is not clear whether all instructions that has a fall through branch are 4 bytes long - return makeAddExpression(makePCExpr(), Immediate::makeImmediate(Result(u64, unsign_extend64(3, 4))), u64); - } - - - bool InstructionDecoder_amdgpu_vega::decodeOperands(const Instruction *) { - assert(0 && "decodeOperands deprecated for amdgpu"); - return true; - } - - Expression::Ptr InstructionDecoder_amdgpu_vega::decodeSGPRorM0(unsigned int offset){ - if( offset <= 104) - return makeRegisterExpression(makeAmdgpuRegID(amdgpu_vega::sgpr0,offset)); - if (offset == 124) - return makeRegisterExpression(amdgpu_vega::m0); - cerr << " unknown offset in sgpr or m0 " << offset << endl; - assert(0 && "shouldn't reach here"); - } - - - void InstructionDecoder_amdgpu_vega::finalizeFLATOperands(){ - layout_flat & layout = insn_layout.flat; - - Expression::Ptr addr_ast = - makeTernaryExpression( - makeRegisterExpression(amdgpu_vega::address_mode_32), // TODO: type needs to be fixed - makeRegisterExpression(makeAmdgpuRegID(amdgpu_vega::vgpr0,layout.addr)), - makeRegisterExpression(makeAmdgpuRegID(amdgpu_vega::vgpr0,layout.addr,2)), - u64 - ); - switch(layout.seg){ - case 1: - insn_in_progress->getOperation().mnemonic += "_scratch"; - break; - case 2: - insn_in_progress->getOperation().mnemonic += "_global"; - break; - default: - break; - } - - insn_in_progress->appendOperand(addr_ast,false,true); - - } - void InstructionDecoder_amdgpu_vega::finalizeMUBUFOperands(){ - layout_mubuf & layout = insn_layout.mubuf; - MachRegister vsharp = makeAmdgpuRegID(amdgpu_vega::sgpr0,layout.srsrc<<2,4); - Expression::Ptr const_base_ast = makeRegisterExpression(vsharp,0,47); - Expression::Ptr const_stride_ast = makeRegisterExpression(vsharp,48,65); - Expression::Ptr num_records = makeRegisterExpression(vsharp,66,97); - Expression::Ptr add_tid_enable = makeRegisterExpression(vsharp,98,98); - Expression::Ptr swizzle_enable = makeRegisterExpression(vsharp,99,99); - Expression::Ptr element_size = makeRegisterExpression(vsharp,100,101); - Expression::Ptr index_stride = makeRegisterExpression(vsharp,102,103); - - Expression::Ptr offset_expr = Immediate::makeImmediate(Result(u32,0)) ; - Expression::Ptr index_expr = Immediate::makeImmediate(Result(u32,0)) ; - - if(layout.idxen){ - if(layout.offen){ - index_expr = makeRegisterExpression(makeAmdgpuRegID(amdgpu_vega::vgpr0,layout.vaddr)); - offset_expr = makeRegisterExpression(makeAmdgpuRegID(amdgpu_vega::vgpr0,layout.vaddr+1)); - }else{ - index_expr = makeRegisterExpression(makeAmdgpuRegID(amdgpu_vega::vgpr0,layout.vaddr)); - } - - }else{ - if(layout.offen){ - offset_expr = makeRegisterExpression(makeAmdgpuRegID(amdgpu_vega::vgpr0,layout.vaddr)); - }else{ - // do nothing - } - } - - - Expression::Ptr index_ast = - makeAddExpression( - index_expr - , - makeTernaryExpression( - add_tid_enable, - makeRegisterExpression(amdgpu_vega::tid), - Immediate::makeImmediate(Result(u32,0)), - u32 - ), - u32 - ); - - Expression::Ptr offset_ast = - makeAddExpression( - offset_expr, - Immediate::makeImmediate(Result(u32,layout.offset)), - u32 - ); - - Expression::Ptr buffer_offset = makeAddExpression( - offset_ast, - makeMultiplyExpression( - const_stride_ast, - index_ast, - u64 - ), - u64 - ); - - Expression::Ptr sgpr_offset_ast = decodeSSRC(layout.soffset); - Expression::Ptr addr_ast = makeAddExpression( - makeAddExpression( - const_base_ast, - sgpr_offset_ast, - u64), - buffer_offset, - u64 - ); - - Expression::Ptr vdata_ast = makeRegisterExpression( - makeAmdgpuRegID(amdgpu_vega::vgpr0,layout.vdata, - num_elements// TODO: This depends on number of elements, which is available from opcode - )); - - insn_in_progress->appendOperand(addr_ast,true,true); - insn_in_progress->appendOperand(vdata_ast,true,true); - - if(layout.lds){ - Expression::Ptr lds_offset_ast = makeRegisterExpression(amdgpu_vega::m0,0,15); - Expression::Ptr mem_offset_ast = makeRegisterExpression( - makeAmdgpuRegID(amdgpu_vega::sgpr0,layout.soffset)); - Expression::Ptr inst_offset_ast = Immediate::makeImmediate(Result(u32,layout.offset)); - Expression::Ptr lds_addr_ast = - makeAddExpression( - makeAddExpression( - makeAddExpression( - makeRegisterExpression(amdgpu_vega::lds_base), - lds_offset_ast, - u32 - ), - inst_offset_ast, - u32 - ), - makeMultiplyExpression( - makeRegisterExpression(amdgpu_vega::tid), - Immediate::makeImmediate(Result(u16,4)), - u32 - ), - u32 - ); - insn_in_progress->getOperation().mnemonic+="_lds"; - insn_in_progress->appendOperand(lds_addr_ast,false,true); - - } - } - - - void InstructionDecoder_amdgpu_vega::finalizeMTBUFOperands(){ - layout_mtbuf & layout = insn_layout.mtbuf; - MachRegister vsharp = makeAmdgpuRegID(amdgpu_vega::sgpr0,layout.srsrc<<2,4); - Expression::Ptr const_base_ast = makeRegisterExpression(vsharp,0,47); - Expression::Ptr const_stride_ast = makeRegisterExpression(vsharp,48,65); - Expression::Ptr num_records = makeRegisterExpression(vsharp,66,97); - Expression::Ptr add_tid_enable = makeRegisterExpression(vsharp,98,98); - Expression::Ptr swizzle_enable = makeRegisterExpression(vsharp,99,99); - Expression::Ptr element_size = makeRegisterExpression(vsharp,100,101); - Expression::Ptr index_stride = makeRegisterExpression(vsharp,102,103); - - Expression::Ptr offset_expr = Immediate::makeImmediate(Result(u32,0)) ; - Expression::Ptr index_expr = Immediate::makeImmediate(Result(u32,0)) ; - - if(layout.idxen){ - if(layout.offen){ - index_expr = makeRegisterExpression(makeAmdgpuRegID(amdgpu_vega::vgpr0,layout.vaddr)); - offset_expr = makeRegisterExpression(makeAmdgpuRegID(amdgpu_vega::vgpr0,layout.vaddr+1)); - }else{ - index_expr = makeRegisterExpression(makeAmdgpuRegID(amdgpu_vega::vgpr0,layout.vaddr)); - } - - }else{ - if(layout.offen){ - offset_expr = makeRegisterExpression(makeAmdgpuRegID(amdgpu_vega::vgpr0,layout.vaddr)); - }else{ - // do nothing - } - } - - - Expression::Ptr index_ast = - makeAddExpression( - index_expr - , - makeTernaryExpression( - add_tid_enable, - makeRegisterExpression(amdgpu_vega::tid), - Immediate::makeImmediate(Result(u32,0)), - u32 - ), - u32 - ); - - Expression::Ptr offset_ast = - makeAddExpression( - offset_expr, - Immediate::makeImmediate(Result(u32,layout.offset)), - u32 - ); - - Expression::Ptr buffer_offset = makeAddExpression( - offset_ast, - makeMultiplyExpression( - const_stride_ast, - index_ast, - u64 - ), - u64 - ); - - Expression::Ptr sgpr_offset_ast = decodeSGPRorM0(layout.soffset); - Expression::Ptr addr_ast = makeAddExpression( - makeAddExpression( - const_base_ast, - sgpr_offset_ast, - u64), - buffer_offset, - u64 - ); - - Expression::Ptr vdata_ast = makeRegisterExpression( - makeAmdgpuRegID(amdgpu_vega::vgpr0,layout.vdata, - num_elements// TODO: This depends on number of elements, which is available from opcode - )); - - insn_in_progress->appendOperand(addr_ast,true,true); - insn_in_progress->appendOperand(vdata_ast,true,true); - - - } - void InstructionDecoder_amdgpu_vega::finalizeVOP1Operands(){ - - layout_vop1 & layout = insn_layout.vop1; - //cout << " finalizing vop1 operands , vdst = " << std::dec << layout.vdst << " src0 = " << layout.src0 <appendOperand(decodeVDST(layout.vdst),false,true); - insn_in_progress->appendOperand(decodeSSRC(layout.src0),true,false); - - } - - - void InstructionDecoder_amdgpu_vega::finalizeSOP1Operands(){ - - layout_sop1 & layout = insn_layout.sop1; - - if(isBranch){ - if(isModifyPC){ - Expression::Ptr new_pc_ast; - new_pc_ast = makeRegisterExpression( - makeAmdgpuRegID(amdgpu_vega::sgpr0,layout.ssrc0,2) - ); - - // TODO : addSuccessors commented out to avoid jump table analysis aborts - if(insn_in_progress->getOperation().operationID == amdgpu_op_s_setpc_b64){ - - //RegisterAST::Ptr tmpqq = boost::dynamic_pointer_cast(new_pc_ast); - //std::cout << "setting pc to offset " << std::hex <getID()<< std::endl; - // non fall through branches are added as Successor - //insn_in_progress->appendOperand(new_pc_ast,true,false); - insn_in_progress->addSuccessor(new_pc_ast, false, false, false, false); - }else if(insn_in_progress->getOperation().operationID == amdgpu_op_s_swappc_b64){ - Expression::Ptr store_pc_ast; - store_pc_ast = makeRegisterExpression( - makeAmdgpuRegID(amdgpu_vega::sgpr0,layout.sdst,2) - ); - - - // for swap pc we assume it is a call, so we add the fall through expr - // iscall , is indirect, isconditional , isfall through - insn_in_progress->addSuccessor(new_pc_ast, false, true, false, false); - insn_in_progress->addSuccessor(makeFallThroughExpr(), false, false, false, true); - insn_in_progress->appendOperand(store_pc_ast,false,true); - } - } - }else{ - if(insn_in_progress->getOperation().operationID == amdgpu_op_s_getpc_b64){ - - Expression::Ptr dst_sgpr_pair_ast; - dst_sgpr_pair_ast = makeRegisterExpression( - makeAmdgpuRegID(amdgpu_vega::sgpr0,layout.sdst,2) - ); - insn_in_progress->appendOperand(dst_sgpr_pair_ast,false,true); - }else{ - insn_in_progress->appendOperand(decodeSSRC(layout.sdst),false,true); - insn_in_progress->appendOperand(decodeSSRC(layout.ssrc0),true,false); - } - } - - } - - void InstructionDecoder_amdgpu_vega::finalizeSOPPOperands(){ - - layout_sopp & layout = insn_layout.sopp; - - if(isBranch){ - if(!isModifyPC){ - //cout << "calling make branch target "<< endl; - makeBranchTarget(isCall,isConditional,layout.simm16); - } - - } - - } - - void InstructionDecoder_amdgpu_vega::finalizeSOPKOperands(){ - - layout_sopp & layout = insn_layout.sopp; - - if(isBranch){ - if(!isModifyPC){ - //cout << "calling make branch target "<< endl; - - makeBranchTarget(isCall,isConditional,layout.simm16); - } - - } - - } - - - - - void InstructionDecoder_amdgpu_vega::finalizeSOP2Operands(){ - - layout_sop2 & layout = insn_layout.sop2; - auto opID = insn_in_progress->getOperation().operationID ; - - switch(opID){ - case amdgpu_op_s_add_u32: - case amdgpu_op_s_addc_u32: - /*Expression::Ptr src0_expr = decodeSSRC(layout.ssrc0); - Expression::Ptr src1_expr = decodeSSRC(layout.ssrc1); - Expression::Ptr dst_expr = decodeSSRC(layout.sdst); - - Expression::Ptr sum_expr = makeAddExpression(src0_expr,src1_expr,u32); - - break;*/ - default: - insn_in_progress->appendOperand(decodeSSRC(layout.sdst),false,true); - insn_in_progress->appendOperand(decodeSSRC(layout.ssrc1),true,false); - insn_in_progress->appendOperand(decodeSSRC(layout.ssrc0),true,false); - break; - } - - } - void InstructionDecoder_amdgpu_vega::finalizeSMEMOperands(){ - layout_smem & layout = insn_layout.smem; - - if(IS_LD_ST()){ - Expression::Ptr offset_expr ; - Expression::Ptr inst_offset_expr ; - if(layout.imm==0){ - unsigned int indexing_offset = layout.soe ? layout.soffset : layout.offset; - offset_expr = decodeSGPRorM0(indexing_offset); - inst_offset_expr = Immediate::makeImmediate(Result(u64,0)); - }else{ - inst_offset_expr = Immediate::makeImmediate(Result(u32,layout.offset)); - offset_expr = layout.soe ? - decodeSGPRorM0(layout.soffset) : Immediate::makeImmediate(Result(u64,0)); - } - // cout << "layout.sbase = " << std::hex << layout.sbase << endl; - //MachRegister mr = makeAmdgpuRegID(amdgpu_vega::sgpr0,4,2); - // cout << " shouldn't it be " << amdgpu_vega::sgpr_vec2_0 << " " << mr << endl; - Expression::Ptr sbase_expr = makeRegisterExpression(makeAmdgpuRegID(amdgpu_vega::sgpr0,layout.sbase << 1,2)); - if(isScratch) - offset_expr = makeMultiplyExpression(offset_expr, - Immediate::makeImmediate(Result(u64,64)),u64); - - Expression::Ptr remain_expr = makeAddExpression(inst_offset_expr,offset_expr,u64); - Expression::Ptr addr_expr = makeDereferenceExpression(makeAddExpression(sbase_expr,remain_expr,u64),u64); - - - - Expression::Ptr sdata_expr = makeRegisterExpression(makeAmdgpuRegID(amdgpu_vega::sgpr0,layout.sdata,num_elements)); - - - insn_in_progress->appendOperand(sdata_expr,true,false); - - insn_in_progress->appendOperand(addr_expr,false,true); - - } - - } - - void InstructionDecoder_amdgpu_vega::finalizeSOPCOperands() { - } - void InstructionDecoder_amdgpu_vega::finalizeVOPCOperands() { - } - void InstructionDecoder_amdgpu_vega::finalizeVOP2Operands() { - } - void InstructionDecoder_amdgpu_vega::finalizeVINTRPOperands() { - } - void InstructionDecoder_amdgpu_vega::finalizeDSOperands() { - } - void InstructionDecoder_amdgpu_vega::finalizeVOP3ABOperands() { - } - void InstructionDecoder_amdgpu_vega::finalizeVOP3POperands() { - } - - bool InstructionDecoder_amdgpu_vega::decodeOperands(const amdgpu_insn_entry & insn_entry) { - if(insn_entry.operandCnt!=0){ - for (std::size_t i =0 ; i < insn_entry.operandCnt; i++){ - std::mem_fun(insn_entry.operands[i])(this); - } - } - return true; - } - - - inline unsigned int get32bit(InstructionDecoder::buffer &b,unsigned int offset ){ - assert(offset %4 ==0 ); - return b.start[offset+3] << 24 | b.start[offset + 2] << 16 | b.start[offset +1 ] << 8 | b.start [offset]; - } - - void InstructionDecoder_amdgpu_vega::insnSize(unsigned int insn_size_) { - this->insn_size = insn_size_; - } - - - Expression::Ptr InstructionDecoder_amdgpu_vega::decodeVDST(unsigned int index){ - index += 255; - return decodeSSRC(index); - } - - - Expression::Ptr InstructionDecoder_amdgpu_vega::decodeVSRC(unsigned int index){ - if (index > 255) - index = 0; - MachRegister mr = makeAmdgpuRegID(amdgpu_vega::vgpr0,index & 0xff); - return makeRegisterExpression(mr); - } - - Expression::Ptr InstructionDecoder_amdgpu_vega::decodeSSRC(unsigned int index){ - if (index < 102){ - MachRegister mr = makeAmdgpuRegID(amdgpu_vega::sgpr0,index); - return makeRegisterExpression(mr); - }else if(index ==102){ - return makeRegisterExpression(amdgpu_vega::flat_scratch_lo); - }else if(index ==103){ - return makeRegisterExpression(amdgpu_vega::flat_scratch_hi); - }else if(index ==104){ - return makeRegisterExpression(amdgpu_vega::xnack_mask_lo); - }else if(index ==105){ - return makeRegisterExpression(amdgpu_vega::xnack_mask_hi); - }else if ( 106 == index ){ - return makeRegisterExpression(amdgpu_vega::vcc_lo); - }else if ( 107 == index ){ - return makeRegisterExpression(amdgpu_vega::vcc_hi); - }else if (107 < index && index < 124){ - MachRegister mr = makeAmdgpuRegID(amdgpu_vega::ttmp0,index-108); - return makeRegisterExpression(mr); - }else if (124 == index ){ - return makeRegisterExpression(amdgpu_vega::m0); - }else if ( 126 == index ){ - return makeRegisterExpression(amdgpu_vega::exec_lo); - }else if ( 127 == index ){ - return makeRegisterExpression(amdgpu_vega::exec_hi); - }else if( 128 <= index && index <= 192){ - return Immediate::makeImmediate(Result(u32, unsign_extend32(32,index - 128 ))); - }else if( 193 <= index && index <= 208 ){ - return Immediate::makeImmediate(Result(s32, sign_extend32(32,-(index - 192) ))); - }else if( 209 <= index && index <= 234){ - assert ( 0 && "reserved index " ) ; - }else if( 235 == index){ - return makeRegisterExpression(amdgpu_vega::shared_base); - }else if( 236 == index){ - return makeRegisterExpression(amdgpu_vega::shared_limit); - }else if( 237 == index){ - return makeRegisterExpression(amdgpu_vega::private_base); - }else if( 238 == index){ - return makeRegisterExpression(amdgpu_vega::private_limit); - }else if( 239 == index){ - return makeRegisterExpression(amdgpu_vega::pops_exiting_wave_id); - }else if (240 == index){ - return Immediate::makeImmediate(Result(sp_float, 0.5) ); - }else if (241 == index){ - return Immediate::makeImmediate(Result(sp_float, -0.5) ); - }else if (242 == index){ - return Immediate::makeImmediate(Result(sp_float, 1.0) ); - }else if (243 == index){ - return Immediate::makeImmediate(Result(sp_float, -1.0) ); - }else if (244 == index){ - return Immediate::makeImmediate(Result(sp_float, 2.0) ); - }else if (245 == index){ - return Immediate::makeImmediate(Result(sp_float, -2.0) ); - }else if (246 == index){ - return Immediate::makeImmediate(Result(sp_float, 4.0) ); - }else if (247 == index){ - return Immediate::makeImmediate(Result(sp_float, -4.0) ); - }else if (248 == index){ - /* - * TODO: 1/(2PI) = 0.15915494 - * The exact value used is - * half: - * 0x3118 - * single: - * 0x3e22f983 - * double: - * 0x3fc45f306dc9c882 - */ - return Immediate::makeImmediate(Result(dp_float, (1.0 / (3.1415926535*2)) ) ); - }else if (249 == index || 250 == index){ - assert ( 0 && "reserved index " ) ; - }else if ( 251 == index ){ - return makeRegisterExpression(amdgpu_vega::vccz); - }else if ( 252 == index ){ - return makeRegisterExpression(amdgpu_vega::execz); - }else if ( 253 == index ){ - return makeRegisterExpression(amdgpu_vega::scc); - }else if ( 254 == index ){ - assert ( 0 && "reserved index " ) ; - } - else if(index == 0xff){ - //std::cerr << "\nusing imm " << imm << std::endl; - return Immediate::makeImmediate(Result(u32, unsign_extend32(32,immLiteral ))); - }else if( 256 <= index && index <= 511){ - MachRegister mr = makeAmdgpuRegID(amdgpu_vega::vgpr0,index >>8); - return makeRegisterExpression(mr); - } - - cerr << "WARNING UNKNOWN REGISTER : " << std::dec << index << " " <<(108 <= index && index <= 123 )< b.end) - return; - insn = get32bit(b,0); - if(b.start + 4 <= b.end) - insn_long = get32bit(b,4); - insn_high = insn_long; - insn_long = (insn_long << 32) | insn; - - } - void InstructionDecoder_amdgpu_vega::decodeOpcode(InstructionDecoder::buffer &b) { - setupInsnWord(b); - mainDecodeOpcode(b); - b.start += insn_in_progress->size(); - } - - void InstructionDecoder_amdgpu_vega::debug_instr(){ - cout << "\ndecoded instruction " << insn_in_progress->getOperation().mnemonic - << " length = " << insn_in_progress->size()<< endl; - - } - - - Instruction InstructionDecoder_amdgpu_vega::decode(InstructionDecoder::buffer &b) { - setupInsnWord(b); - mainDecodeOpcode(b); - if(entryToCategory(insn_in_progress->getOperation().getID())==c_BranchInsn){ - std::mem_fun(decode_lookup_table[instr_family])(this); - } - //debug_instr(); - cout.clear(); - b.start += insn_in_progress->size(); - return *insn_in_progress; - } - - void InstructionDecoder_amdgpu_vega::doDelayedDecode(const Instruction *insn_to_complete) { - InstructionDecoder::buffer b(insn_to_complete->ptr(), insn_to_complete->size()); - setupInsnWord(b); - mainDecode(b); - //debug_instr(); - cout.clear(); - Instruction* iptr = const_cast(insn_to_complete); - *iptr = *(insn_in_progress.get()); - b.start += insn_in_progress->size(); - } - } -} - - - diff --git a/instructionAPI/src/InstructionDecoder-amdgpu-vega.h b/instructionAPI/src/InstructionDecoder-amdgpu-vega.h deleted file mode 100644 index ce89b4701a..0000000000 --- a/instructionAPI/src/InstructionDecoder-amdgpu-vega.h +++ /dev/null @@ -1,341 +0,0 @@ -/* - * See the dyninst/COPYRIGHT file for copyright information. - * - * We provide the Paradyn Tools (below described as "Paradyn") - * on an AS IS basis, and do not warrant its validity or performance. - * We reserve the right to update, modify, or discontinue this - * software at any time. We shall have no obligation to supply such - * updates or modifications or any other form of support to you. - * - * By your use of Paradyn, you understand and agree that we (or any - * other person or entity with proprietary rights in Paradyn) are - * under no obligation to provide either maintenance services, - * update services, notices of latent defects, or correction of - * defects for Paradyn. - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include "InstructionDecoderImpl.h" -#include -#include "Immediate.h" -#include "dyn_regs.h" - -namespace Dyninst { - namespace InstructionAPI { - -#if defined(__GNUC__) -#define insn_printf(format, ...) \ - do{ \ - printf("[%s:%u]insn_debug " format, FILE__, __LINE__, ## __VA_ARGS__); \ - }while(0) -#endif - - struct amdgpu_insn_entry; - struct amdgpu_mask_entry; - - class InstructionDecoder_amdgpu_vega : public InstructionDecoderImpl { - friend struct amdgpu_insn_entry; - friend struct amdgpu_mask_entry; - enum DecodeFamily {sopp}; - - public: - InstructionDecoder_amdgpu_vega(Architecture a); - - virtual ~InstructionDecoder_amdgpu_vega(); - - virtual void decodeOpcode(InstructionDecoder::buffer &b); - - // decode one instruction starting from b.start - // will advance b.start whenver a instruction is successfully decoded - virtual Instruction decode(InstructionDecoder::buffer &b); - - virtual void setMode(bool) { } - - virtual bool decodeOperands(const Instruction *insn_to_complete); - - bool decodeOperands(const amdgpu_insn_entry & insn_entry); - - virtual void doDelayedDecode(const Instruction *insn_to_complete); - - static const std::array condNames; - static MachRegister sysRegMap(unsigned int); - static const char* bitfieldInsnAliasMap(entryID); - static const char* condInsnAliasMap(entryID); - - - - private: - virtual Result_Type makeSizeType(unsigned int opType); - - bool is64Bit; - - unsigned int insn_size; // size of the instruction that we are currently working on - unsigned int insn; // the first 32 bit - unsigned int insn_high; // the second 32 bit - unsigned long long int insn_long; // the combined 64 bit: insn_high << 32 | insn - - // the main process of decoding an instruciton, won't advance buffer - void mainDecode(InstructionDecoder::buffer &b); - - void mainDecodeOpcode(InstructionDecoder::buffer &b); - - - void setupInsnWord(InstructionDecoder::buffer &b); - // pointer to the instruction that we are currently working on - boost::shared_ptr insn_in_progress; - - template - int field(unsigned int raw) { -#if defined DEBUG_FIELD - std::cerr << start << "-" << end << ":" << std::dec << (raw >> (start) & - (0xFFFFFFFF >> (31 - (end - start)))) << " "; -#endif - return (raw >> (start) & (0xFFFFFFFF >> (31 - (end - start)))); - } - - template - int longfield(unsigned long long int raw) { -#if defined DEBUG_FIELD - std::cerr << start << "-" << end << ":" << std::dec << (raw >> (start) & - (0xFFFFFFFFFFFFFFFF >> (63 - (end - start)))) << " "; -#endif - return ( (raw >> (start)) & (0xFFFFFFFFFFFFFFFF >> (63 - (end - start)))); - } - - template - int rev_field(unsigned int raw) { -#if defined DEBUG_FIELD - std::cerr << start << "-" << end << ":" << std::dec << (raw >> (start) & - (0xFFFFFFFF >> (31 - (end - start)))) << " "; -#endif - unsigned int le = (raw >> (start) & (0xFFFFFFFF >> (31 - (end - start)))); - - std::cerr << "operating on le " << std::hex << le << std::endl; - unsigned int be = __builtin_bswap32(le); - - std::cerr << "operating on be " << std::hex << be << std::endl; - return be >> (31 - (end-start)); - } - - - int32_t sign_extend32(int size_, int in) { - int32_t val = 0 | in; - - return (val << (32 - size_)) >> (32 - size_); - } - - int64_t sign_extend64(int size_, int in) { - int64_t val = 0 | in; - - return (val << (64 - size_)) >> (64 - size_); - } - - uint32_t unsign_extend32(int size_, int in) { - uint32_t mask = ~0; - - return (mask >> (32 - size_)) & in; - } - - uint64_t unsign_extend64(int size_, int in) { - uint64_t mask = ~0; - - return (mask >> (64 - size_)) & in; - } - - int highest_set_bit(int32_t val) { - for (int bit_index = 31; bit_index >= 0; bit_index--) - if (((static_cast(val) >> bit_index) & 0x1) == 0x1) - return bit_index + 1; - - return -1; - } - - int lowest_set_bit(int32_t val) { - for (int bit_index = 0; bit_index <= 31; bit_index++) - if (((static_cast(val) >> bit_index) & 0x1) == 0x1) - return bit_index + 1; - - return -1; - } - - - bool hasHw; - int hwField; - - void processHwFieldInsn(int, int); - - bool hasShift; - int shiftField; - - void makeBranchTarget(bool, bool, int, int); - - Expression::Ptr makeFallThroughExpr(); - - int _szField, size; - int _typeField; - int cmode; - int op; - int simdAlphabetImm; - - void processAlphabetImm(); - - void NOTHING(); - bool fix_bitfieldinsn_alias(int, int); - void fix_condinsn_alias_and_cond(int &); - void modify_mnemonic_simd_upperhalf_insns(); - - MachRegister makeAmdgpuRegID(MachRegister, unsigned int, unsigned int len = 1); - - MachRegister getLoadStoreSimdRegister(int encoding); - - Expression::Ptr makePCExpr(); - - - template - Expression::Ptr makeLogicalImm(int immr, int imms, int immsLen, Result_Type rT); - - - //for load store - void insnSize(unsigned int insn_size ); - - Expression::Ptr decodeSSRC(unsigned int index); - Expression::Ptr decodeVSRC(unsigned int index); - Expression::Ptr decodeVDST(unsigned int index); - - Expression::Ptr decodeSGPRorM0(unsigned int offset); - - - void finalizeFLATOperands(); - void finalizeSMEMOperands(); - - void finalizeSOPKOperands(); - void finalizeSOPPOperands(); - void finalizeSOP2Operands(); - void finalizeSOP1Operands(); - void finalizeSOPCOperands(); - - void finalizeVOP1Operands(); - void finalizeVOP2Operands(); - void finalizeVOPCOperands(); - void finalizeVINTRPOperands(); - void finalizeDSOperands(); - void finalizeMTBUFOperands(); - void finalizeMUBUFOperands(); - void finalizeVOP3ABOperands(); - void finalizeVOP3POperands(); - - bool useImm; - unsigned int immLen; - unsigned int immLiteral; - bool setSCC; - -#define IS_LD_ST() (isLoad || isStore ) - - unsigned int num_elements ; // the number of elements that will be load or store by each instruction - bool isSMEM; // this is set when using smem instruction - bool isLoad; // this is set when a smem instruction is load, will set number of elements that are loaded at the same time - bool isStore; // similar to isLoad, but for store instructions - bool isBuffer; // - bool isScratch; - - bool isBranch; // this is set for all branch instructions, - bool isConditional; // this is set for all conditional branch instruction, will set branchCond - bool isCall; // this is a call function - - - - // this is set for instructions that directly modify pc - // namely s_setpc and s_swappc - bool isModifyPC; - - // reset the decoder internal state for decoding the next instruction - void reset(); - - Expression::Ptr branchCond; - Expression::Ptr branchTarget; - - void setBranch(){ - isBranch = true; - } - - void setConditionalBranch(){ - isConditional = true; - // TODO : set conditional branch - } - void setModifyPC(){ - isModifyPC = true; - } - - void setCall(){ - isCall = true; - } - - inline unsigned int get32bit(InstructionDecoder::buffer &b,unsigned int offset ){ - assert(offset %4 ==0 ); - return b.start[offset+3] << 24 | b.start[offset + 2] << 16 | b.start[offset +1 ] << 8 | b.start [offset]; - } - - template - void setUseImm(InstructionDecoder::buffer & b, unsigned int offset){ - if ( longfield(insn_long) == candidate ){ - useImm = true; - immLen = 4; - immLiteral = get32bit(b,offset); - } - - } - - void setSMEM() {isSMEM = true;} - - - - template - void setLoad(){isLoad = true; this->num_elements = num_elements; } - - template - void setStore() {isStore = true;this->num_elements = num_elements;} - - void setScratch() {isScratch = true;} - - void setBuffer() {isBuffer = true;} - - typedef struct buffer_resource_desc{ - unsigned long long base_address; - unsigned stride; - unsigned cache_swizzle; - unsigned swizzle_enable; - unsigned num_records; - unsigned dst_sel_x; - unsigned dst_sel_y; - unsigned dst_sel_z; - unsigned dst_sel_w; - unsigned num_format; - unsigned data_format; - unsigned user_vm_enable; - unsigned user_vm_mode; - unsigned index_stride; - unsigned add_tid_enable; - unsigned non_volatile; - unsigned type; - }buffer_resource_desc; - - void debug_instr(); - -#include "amdgpu_decoder_impl_vega.h" - }; - } -} - diff --git a/instructionAPI/src/InstructionDecoder-power.C b/instructionAPI/src/InstructionDecoder-power.C index ffd38bcf3e..b2a674fb71 100644 --- a/instructionAPI/src/InstructionDecoder-power.C +++ b/instructionAPI/src/InstructionDecoder-power.C @@ -29,9 +29,14 @@ */ #include "InstructionDecoder-power.h" -#include +#include +#include #include "../../common/src/singleton_object_pool.h" #include +#include "unaligned_memory_access.h" +#include "registers/ppc32_regs.h" +#include "registers/ppc64_regs.h" + namespace Dyninst { namespace InstructionAPI @@ -262,7 +267,7 @@ namespace Dyninst isRAWritten = false; isFPInsn = false; bcIsConditional = false; - insn = *((const uint32_t*)b.start); + insn = Dyninst::read_memory_as(b.start); #if defined(DEBUG_RAW_INSN) cout.width(0); cout << "0x"; @@ -297,7 +302,7 @@ namespace Dyninst const power_entry* current = &power_entry::main_opcode_table[field<0,5>(insn)]; while(current->next_table) { - current = &(std::mem_fun(current->next_table)(this)); + current = &(std::mem_fn(current->next_table)(this)); } if (findRAAndRS(current)) { isRAWritten = true; @@ -314,7 +319,7 @@ namespace Dyninst curFn != current->operands.end(); ++curFn) { - std::mem_fun(*curFn)(this); + std::mem_fn(*curFn)(this); } if(current->op == power_op_bclr) { @@ -887,7 +892,7 @@ namespace Dyninst void InstructionDecoder_power::doDelayedDecode(const Instruction* insn_to_complete) { - insn_in_progress = boost::shared_ptr(new Instruction(*insn_to_complete)); + insn_in_progress = dyncompat::shared_ptr(new Instruction(*insn_to_complete)); decodeOperands(insn_in_progress.get()); Instruction* iptr = const_cast(insn_to_complete); *iptr = *(insn_in_progress.get()); @@ -909,7 +914,7 @@ namespace Dyninst #define fn(x) (&InstructionDecoder_power::x) -using namespace boost::assign; +using namespace dyncompat::assign; #include "power_opcode_tables.C" @@ -1429,7 +1434,7 @@ using namespace boost::assign; const power_entry* current = &power_entry::main_opcode_table[field<0,5>(insn)]; while(current->next_table) { - current = &(std::mem_fun(current->next_table)(this)); + current = &(std::mem_fn(current->next_table)(this)); } insn_in_progress = makeInstruction(current->op, current->mnemonic, 4, reinterpret_cast(&insn)); if(current->op == power_op_b || diff --git a/instructionAPI/src/InstructionDecoder-power.h b/instructionAPI/src/InstructionDecoder-power.h index e3906ab704..151c860dd9 100644 --- a/instructionAPI/src/InstructionDecoder-power.h +++ b/instructionAPI/src/InstructionDecoder-power.h @@ -31,8 +31,10 @@ #include "InstructionDecoderImpl.h" #include +#include +#include #include "Immediate.h" -#include "dyn_regs.h" +#include "registers/ppc32_regs.h" //#define DEBUG_FIELD namespace Dyninst { @@ -321,7 +323,7 @@ namespace Dyninst { Expression::Ptr makeFallThroughExpr(); unsigned int insn; - boost::shared_ptr insn_in_progress; + dyncompat::shared_ptr insn_in_progress; bool isRAWritten; bool invertBranchCondition; bool isFPInsn; diff --git a/instructionAPI/src/InstructionDecoder-x86.C b/instructionAPI/src/InstructionDecoder-x86.C index af06c3b408..adb7b33f82 100644 --- a/instructionAPI/src/InstructionDecoder-x86.C +++ b/instructionAPI/src/InstructionDecoder-x86.C @@ -30,7 +30,6 @@ #define INSIDE_INSTRUCTION_API -#include "common/src/Types.h" #include "InstructionDecoder-x86.h" #include "Expression.h" #include "common/src/arch-x86.h" @@ -39,6 +38,10 @@ #include "Immediate.h" #include "BinaryFunction.h" #include "common/src/singleton_object_pool.h" +#include "unaligned_memory_access.h" +#include "registers/x86_regs.h" +#include "registers/x86_64_regs.h" +#include "registers/abstract_regs.h" // #define VEX_DEBUG @@ -140,7 +143,7 @@ namespace Dyninst sizePrefixPresent(false), addrSizePrefixPresent(false) { - if(a == Arch_x86_64) setMode(true); + if(a == Arch_x86_64) InstructionDecoder_x86::setMode(true); } INSTRUCTION_EXPORT InstructionDecoder_x86::~InstructionDecoder_x86() @@ -300,20 +303,20 @@ namespace Dyninst return Immediate::makeImmediate(Result(isSigned ? s8 : u8 ,*(const byte_t*)(immStart))); break; case op_d: - return Immediate::makeImmediate(Result(isSigned ? s32 : u32,*(const dword_t*)(immStart))); + return Immediate::makeImmediate(Result(isSigned ? s32 : u32,Dyninst::read_memory_as(immStart))); case op_w: - return Immediate::makeImmediate(Result(isSigned ? s16 : u16,*(const word_t*)(immStart))); + return Immediate::makeImmediate(Result(isSigned ? s16 : u16,Dyninst::read_memory_as(immStart))); break; case op_q: - return Immediate::makeImmediate(Result(isSigned ? s64 : u64,*(const int64_t*)(immStart))); + return Immediate::makeImmediate(Result(isSigned ? s64 : u64,Dyninst::read_memory_as(immStart))); break; case op_v: if (locs->rex_w || isDefault64Insn()) { - return Immediate::makeImmediate(Result(isSigned ? s64 : u64,*(const int64_t*)(immStart))); + return Immediate::makeImmediate(Result(isSigned ? s64 : u64,Dyninst::read_memory_as(immStart))); } //if(!sizePrefixPresent) //{ - return Immediate::makeImmediate(Result(isSigned ? s32 : u32,*(const dword_t*)(immStart))); + return Immediate::makeImmediate(Result(isSigned ? s32 : u32,Dyninst::read_memory_as(immStart))); //} //else //{ @@ -325,7 +328,7 @@ namespace Dyninst // 16 bit mode, no prefix or 32 bit mode, prefix => 16 bit //if(!addrSizePrefixPresent) //{ - return Immediate::makeImmediate(Result(isSigned ? s32 : u32,*(const dword_t*)(immStart))); + return Immediate::makeImmediate(Result(isSigned ? s32 : u32,Dyninst::read_memory_as(immStart))); //} //else //{ @@ -337,11 +340,11 @@ namespace Dyninst // 16 bit mode, no prefix or 32 bit mode, prefix => 32 bit if(!sizePrefixPresent) { - return Immediate::makeImmediate(Result(isSigned ? s48 : u48,*(const int64_t*)(immStart))); + return Immediate::makeImmediate(Result(isSigned ? s48 : u48,Dyninst::read_memory_as(immStart))); } else { - return Immediate::makeImmediate(Result(isSigned ? s32 : u32,*(const dword_t*)(immStart))); + return Immediate::makeImmediate(Result(isSigned ? s32 : u32,Dyninst::read_memory_as(immStart))); } break; @@ -374,19 +377,19 @@ namespace Dyninst switch(locs->modrm_mod) { case 1: - return make_shared(singleton_object_pool::construct(Result(s8, (*(const byte_t*)(b.start + - disp_pos))))); + return make_shared(singleton_object_pool::construct(Result(s8, Dyninst::read_memory_as(b.start + + disp_pos)))); break; case 2: if(0 && sizePrefixPresent) { - return make_shared(singleton_object_pool::construct(Result(s16, *((const word_t*)(b.start + - disp_pos))))); + return make_shared(singleton_object_pool::construct(Result(s16, Dyninst::read_memory_as(b.start + + disp_pos)))); } else { - return make_shared(singleton_object_pool::construct(Result(s32, *((const dword_t*)(b.start + - disp_pos))))); + return make_shared(singleton_object_pool::construct(Result(s32, Dyninst::read_memory_as(b.start + + disp_pos)))); } break; case 0: @@ -396,14 +399,14 @@ namespace Dyninst if(locs->modrm_rm == 6) { return make_shared(singleton_object_pool::construct(Result(s16, - *((const dword_t*)(b.start + disp_pos))))); + Dyninst::read_memory_as(b.start + disp_pos)))); } // TODO FIXME; this was decoding wrong, but I'm not sure // why... else if (locs->modrm_rm == 5) { assert(b.start + disp_pos + 4 <= b.end); return make_shared(singleton_object_pool::construct(Result(s32, - *((const dword_t*)(b.start + disp_pos))))); + Dyninst::read_memory_as(b.start + disp_pos)))); } else { assert(b.start + disp_pos + 1 <= b.end); return make_shared(singleton_object_pool::construct(Result(s8, 0))); @@ -417,7 +420,7 @@ namespace Dyninst { if (b.start + disp_pos + 4 <= b.end) return make_shared(singleton_object_pool::construct(Result(s32, - *((const dword_t*)(b.start + disp_pos))))); + Dyninst::read_memory_as(b.start + disp_pos)))); else return make_shared(singleton_object_pool::construct(Result())); } @@ -1618,7 +1621,7 @@ namespace Dyninst { Expression::Ptr edx(makeRegisterExpression(m_Arch == Arch_x86 ? x86::edx : x86_64::edx)); Expression::Ptr eax(makeRegisterExpression(m_Arch == Arch_x86 ? x86::eax : x86_64::eax)); - Expression::Ptr highAddr = makeMultiplyExpression(edx, Immediate::makeImmediate(Result(u64, 2^32)), u64); + Expression::Ptr highAddr = makeMultiplyExpression(edx, Immediate::makeImmediate(Result(u64, 1LL << 32)), u64); Expression::Ptr addr = makeAddExpression(highAddr, eax, u64); Expression::Ptr op = makeDereferenceExpression(addr, u64); insn_to_complete->appendOperand(op, isRead, isWritten, isImplicit); @@ -1627,7 +1630,7 @@ namespace Dyninst Expression::Ptr ecx(makeRegisterExpression(m_Arch == Arch_x86 ? x86::ecx : x86_64::ecx)); Expression::Ptr ebx(makeRegisterExpression(m_Arch == Arch_x86 ? x86::ebx : x86_64::ebx)); Expression::Ptr highAddr = makeMultiplyExpression(ecx, - Immediate::makeImmediate(Result(u64, 2^32)), u64); + Immediate::makeImmediate(Result(u64, 1LL << 32)), u64); Expression::Ptr addr = makeAddExpression(highAddr, ebx, u64); Expression::Ptr op = makeDereferenceExpression(addr, u64); insn_to_complete->appendOperand(op, isRead, isWritten, isImplicit); @@ -1758,13 +1761,20 @@ namespace Dyninst assert(locs->sib_position == -1); decodedInstruction = new (decodedInstruction) ia32_instruction(NULL, NULL, locs); ia32_decode(IA32_DECODE_PREFIXES, b.start, *decodedInstruction, is64BitMode); + + static ia32_entry invalid = { e_No_Entry, 0, 0, false, { {0,0}, {0,0}, {0,0} }, 0, 0, 0 }; + if(decodedInstruction->getLegacyType() == ILLEGAL) { + m_Operation = Operation(&invalid, nullptr, nullptr, m_Arch); + return; + } + sizePrefixPresent = (decodedInstruction->getPrefix()->getOperSzPrefix() == 0x66); if (decodedInstruction->getPrefix()->rexW()) { // as per 2.2.1.2 - rex.w overrides 66h sizePrefixPresent = false; } addrSizePrefixPresent = (decodedInstruction->getPrefix()->getAddrSzPrefix() == 0x67); - static ia32_entry invalid = { e_No_Entry, 0, 0, false, { {0,0}, {0,0}, {0,0} }, 0, 0, 0 }; + if(decodedInstruction->getEntry()) { // check prefix validity // lock prefix only allowed on certain insns. @@ -1779,8 +1789,8 @@ namespace Dyninst case e_btc: case e_btr: case e_bts: - case e_cmpxch: - case e_cmpxch8b: + case e_cmpxchg: + case e_cmpxchg8b: case e_dec: case e_inc: case e_neg: @@ -1797,7 +1807,17 @@ namespace Dyninst decodedInstruction->getPrefix(), locs, m_Arch); return; } - } + } else if (decodedInstruction->getPrefix()->getPrefix(0) == PREFIX_REP && + *(b.start+1) == (unsigned char)(0x0F) && *(b.start+2) == (unsigned char)(0x1E)) { + // handling ENDBR family + if (*(b.start+3) == (unsigned char)(0xFB)) { + m_Operation = Operation(e_endbr32, entryNames_IAPI[e_endbr32], m_Arch); + return; + } else if (*(b.start+3) == (unsigned char)(0xFA)) { + m_Operation = Operation(e_endbr64, entryNames_IAPI[e_endbr64], m_Arch); + return; + } + } m_Operation = Operation(decodedInstruction->getEntry(), decodedInstruction->getPrefix(), locs, m_Arch); @@ -1816,6 +1836,10 @@ namespace Dyninst void InstructionDecoder_x86::decodeOpcode(InstructionDecoder::buffer& b) { doIA32Decode(b); + + // Do not move through the buffer if a bad instruction was encountered + if(m_Operation.getID() == e_No_Entry) return; + b.start += decodedInstruction->getSize(); } @@ -1833,8 +1857,13 @@ namespace Dyninst decodedInstruction->getEntry()->getID() == e_ret_far) { Expression::Ptr ret_addr = makeDereferenceExpression(makeRegisterExpression(is64BitMode ? x86_64::rsp : x86::esp), is64BitMode ? u64 : u32); - insn_to_complete->addSuccessor(ret_addr, false, true, false, false); - } + insn_to_complete->addSuccessor(ret_addr, false, true, false, false, true); + } + if (insn_to_complete->getOperation().getID() == e_endbr32 || + insn_to_complete->getOperation().getID() == e_endbr64) { + insn_to_complete->m_Operands.clear(); + return true; + } for(int i = 0; i < 3; i++) { diff --git a/instructionAPI/src/InstructionDecoder.C b/instructionAPI/src/InstructionDecoder.C index 78fa3fad4f..78f9180700 100644 --- a/instructionAPI/src/InstructionDecoder.C +++ b/instructionAPI/src/InstructionDecoder.C @@ -31,6 +31,14 @@ #include "InstructionDecoder.h" #include "InstructionDecoderImpl.h" #include "Instruction.h" +#include +#include + +namespace { + namespace ia = Dyninst::InstructionAPI; + using ui = ia::InstructionDecoder::unknown_instruction; + ui::callback_t callback{}; +} using namespace std; namespace Dyninst @@ -53,13 +61,27 @@ namespace Dyninst INSTRUCTION_EXPORT Instruction InstructionDecoder::decode() { if(m_buf.start >= m_buf.end) return Instruction(); - return m_Impl->decode(m_buf); + Instruction const& ins = m_Impl->decode(m_buf); + + if(!ins.isLegalInsn() && ::callback) { + auto const buf_len = static_cast(m_buf.end - m_buf.start); + auto const size = (maxInstructionLength < buf_len) ? maxInstructionLength : buf_len; + + // Don't let the user modify the real byte stream + std::array buf{}; + std::copy_n(m_buf.start, size, buf.data()); + buffer user_buf{buf.data(), buf.data()+size}; + + auto user_ins = ::callback(user_buf); + m_buf.start += user_ins.size(); + return user_ins; + } + return ins; } INSTRUCTION_EXPORT Instruction InstructionDecoder::decode(const unsigned char* b) { buffer tmp(b, b+maxInstructionLength); - return m_Impl->decode(tmp); } INSTRUCTION_EXPORT void InstructionDecoder::doDelayedDecode(const Instruction* i) @@ -67,7 +89,14 @@ namespace Dyninst m_Impl->doDelayedDecode(i); } - + using cbt = InstructionDecoder::unknown_instruction::callback_t; + void InstructionDecoder::unknown_instruction::register_callback(cbt cb) { + ::callback = cb; + } + cbt InstructionDecoder::unknown_instruction::unregister_callback() { + auto c = ::callback; + ::callback = nullptr; + return c; + } } } - diff --git a/instructionAPI/src/InstructionDecoderImpl.C b/instructionAPI/src/InstructionDecoderImpl.C index 1784a2f446..6462df6d07 100644 --- a/instructionAPI/src/InstructionDecoderImpl.C +++ b/instructionAPI/src/InstructionDecoderImpl.C @@ -33,7 +33,9 @@ #include "InstructionDecoder-x86.h" #include "InstructionDecoder-power.h" #include "InstructionDecoder-aarch64.h" -#include "InstructionDecoder-amdgpu-vega.h" +#include "AMDGPU/gfx908/InstructionDecoder-amdgpu-gfx908.h" +#include "AMDGPU/gfx90a/InstructionDecoder-amdgpu-gfx90a.h" +#include "AMDGPU/gfx940/InstructionDecoder-amdgpu-gfx940.h" #include "BinaryFunction.h" #include "Dereference.h" @@ -44,7 +46,7 @@ namespace Dyninst { namespace InstructionAPI { - boost::shared_ptr InstructionDecoderImpl::makeInstruction(entryID opcode, const char* mnem, + dyncompat::shared_ptr InstructionDecoderImpl::makeInstruction(entryID opcode, const char* mnem, unsigned int decodedSize, const unsigned char* raw) { Operation tmp(opcode, mnem, m_Arch); @@ -75,8 +77,12 @@ namespace Dyninst case Arch_aarch32: case Arch_aarch64: return Ptr(new InstructionDecoder_aarch64(a)); - case Arch_amdgpu_vega: - return Ptr(new InstructionDecoder_amdgpu_vega(a)); + case Arch_amdgpu_gfx908: + return Ptr(new InstructionDecoder_amdgpu_gfx908(a)); + case Arch_amdgpu_gfx90a: + return Ptr(new InstructionDecoder_amdgpu_gfx90a(a)); + case Arch_amdgpu_gfx940: + return Ptr(new InstructionDecoder_amdgpu_gfx940(a)); default: assert(0); return Ptr(); @@ -129,13 +135,13 @@ namespace Dyninst { return make_shared(singleton_object_pool::construct(addrToDereference, resultType)); } - Expression::Ptr InstructionDecoderImpl::makeRegisterExpression(MachRegister registerID) + Expression::Ptr InstructionDecoderImpl::makeRegisterExpression(MachRegister registerID, uint32_t num_elements ) { int newID = registerID.val(); int minusArch = newID & ~(registerID.getArchitecture()); int convertedID = minusArch | m_Arch; MachRegister converted(convertedID); - return make_shared(singleton_object_pool::construct(converted, 0, registerID.size() * 8)); + return make_shared(singleton_object_pool::construct(converted, 0, registerID.size() * 8,num_elements)); } @@ -165,7 +171,6 @@ namespace Dyninst MachRegister converted(convertedID); return make_shared(singleton_object_pool::construct(converted, 0, registerID.size() * 8)); } - } } diff --git a/instructionAPI/src/InstructionDecoderImpl.h b/instructionAPI/src/InstructionDecoderImpl.h index b59257c586..bf0b168b24 100644 --- a/instructionAPI/src/InstructionDecoderImpl.h +++ b/instructionAPI/src/InstructionDecoderImpl.h @@ -31,8 +31,9 @@ #if !defined(INSTRUCTION_DECODER_IMPL_H) #define INSTRUCTION_DECODER_IMPL_H +#include #include "Expression.h" -#include "dyn_regs.h" +#include "Architecture.h" #include "Operation_impl.h" #include "entryIDs.h" #include "Instruction.h" @@ -45,7 +46,7 @@ namespace InstructionAPI class InstructionDecoderImpl { public: - typedef boost::shared_ptr Ptr; + typedef dyncompat::shared_ptr Ptr; InstructionDecoderImpl(Architecture a) : m_Arch(a) {} virtual ~InstructionDecoderImpl() {} @@ -67,7 +68,10 @@ class InstructionDecoderImpl virtual Expression::Ptr makeRightLogicalShiftExpression(Expression::Ptr lhs, Expression::Ptr rhs, Result_Type resultType); virtual Expression::Ptr makeRightRotateExpression(Expression::Ptr lhs, Expression::Ptr rhs, Result_Type resultType); virtual Expression::Ptr makeDereferenceExpression(Expression::Ptr addrToDereference, Result_Type resultType); - virtual Expression::Ptr makeRegisterExpression(MachRegister reg); + + + + virtual Expression::Ptr makeRegisterExpression(MachRegister reg, uint32_t num_elements = 1); // added version to support loading partial values out of register virtual Expression::Ptr makeRegisterExpression(MachRegister reg, unsigned int start , unsigned int end); virtual Expression::Ptr makeMaskRegisterExpression(MachRegister reg); @@ -76,7 +80,7 @@ class InstructionDecoderImpl // added to support ternary value virtual Expression::Ptr makeTernaryExpression(Expression::Ptr cond, Expression::Ptr first, Expression::Ptr second, Result_Type resultType); //Instruction* makeInstruction(entryID opcode, const char* mnem, unsigned int decodedSize,const unsigned char* raw); - boost::shared_ptr makeInstruction(entryID opcode, const char* mnem, unsigned int decodedSize, + dyncompat::shared_ptr makeInstruction(entryID opcode, const char* mnem, unsigned int decodedSize, const unsigned char* raw); protected: diff --git a/instructionAPI/src/InstructionTest.C b/instructionAPI/src/InstructionTest.C index 4a269cd4b5..6548a241e7 100644 --- a/instructionAPI/src/InstructionTest.C +++ b/instructionAPI/src/InstructionTest.C @@ -30,12 +30,12 @@ #include "../h/InstructionDecoder.h" #include -#include +#include #include "../h/Register.h" using namespace Dyninst::InstructionAPI; using namespace std; -using namespace boost::assign; +using namespace dyncompat::assign; template< typename strT > strT& operator<<(strT& s, std::set regs) @@ -74,7 +74,7 @@ public: return testAssertEqual(expectedRead, actualRead) && testAssertEqual(expectedWritten, actualWritten); } template< typename T1, typename T2> - bool testAssertEqual(boost::shared_ptr lhs, boost::shared_ptr rhs) + bool testAssertEqual(dyncompat::shared_ptr lhs, dyncompat::shared_ptr rhs) { numTests++; if(*lhs == *rhs) diff --git a/instructionAPI/src/Operand.C b/instructionAPI/src/Operand.C index 3bd216ed5d..63fda095eb 100644 --- a/instructionAPI/src/Operand.C +++ b/instructionAPI/src/Operand.C @@ -41,109 +41,115 @@ using namespace std; namespace Dyninst { - namespace InstructionAPI - { - INSTRUCTION_EXPORT void Operand::getReadSet(std::set& regsRead) const + namespace InstructionAPI { - std::set useSet; - op_value->getUses(useSet); - std::set::const_iterator curUse; - for(curUse = useSet.begin(); curUse != useSet.end(); ++curUse) - { - RegisterAST::Ptr tmp = boost::dynamic_pointer_cast(*curUse); - if(tmp) - { - if(m_isRead || !(*tmp == *op_value)) - regsRead.insert(tmp); - } - } - } - INSTRUCTION_EXPORT void Operand::getWriteSet(std::set& regsWritten) const - { - RegisterAST::Ptr op_as_reg = boost::dynamic_pointer_cast(op_value); - if(m_isWritten && op_as_reg) - { - regsWritten.insert(op_as_reg); - } - } + INSTRUCTION_EXPORT void Operand::getReadSet(std::set& regsRead) const + { + std::set useSet; + // This thing returns something only for RegisterAST Expression + op_value->getUses(useSet); + std::set::const_iterator curUse; + for(curUse = useSet.begin(); curUse != useSet.end(); ++curUse) + { + RegisterAST::Ptr tmp = dyncompat::dynamic_pointer_cast(*curUse); + if(tmp) + { + if(m_isRead || !(*tmp == *op_value)) + regsRead.insert(tmp); + } + } + } + INSTRUCTION_EXPORT void Operand::getWriteSet(std::set& regsWritten) const + { + RegisterAST::Ptr op_as_reg = dyncompat::dynamic_pointer_cast(op_value); + if(m_isWritten && op_as_reg) + { + regsWritten.insert(op_as_reg); + } + } - INSTRUCTION_EXPORT RegisterAST::Ptr Operand::getPredicate() const - { - RegisterAST::Ptr op_as_reg = boost::dynamic_pointer_cast(op_value); - if (m_isTruePredicate || m_isFalsePredicate) { - return op_as_reg; - } - return nullptr; - } + INSTRUCTION_EXPORT RegisterAST::Ptr Operand::getPredicate() const + { + RegisterAST::Ptr op_as_reg = dyncompat::dynamic_pointer_cast(op_value); + if (m_isTruePredicate || m_isFalsePredicate) { + return op_as_reg; + } + return nullptr; + } - INSTRUCTION_EXPORT bool Operand::isRead(Expression::Ptr candidate) const - { - // The whole expression of a read, any subexpression of a write - return op_value->isUsed(candidate) && (m_isRead || !(*candidate == *op_value)); - } - INSTRUCTION_EXPORT bool Operand::isWritten(Expression::Ptr candidate) const - { - // Whole expression of a write - return m_isWritten && (*op_value == *candidate); - } - INSTRUCTION_EXPORT bool Operand::readsMemory() const - { - return (boost::dynamic_pointer_cast(op_value) && m_isRead); - } - INSTRUCTION_EXPORT bool Operand::writesMemory() const - { - return (boost::dynamic_pointer_cast(op_value) && m_isWritten); - } - INSTRUCTION_EXPORT void Operand::addEffectiveReadAddresses(std::set& memAccessors) const - { - if(m_isRead && boost::dynamic_pointer_cast(op_value)) - { - std::vector tmp; - op_value->getChildren(tmp); - for(std::vector::const_iterator curKid = tmp.begin(); - curKid != tmp.end(); - ++curKid) - { - memAccessors.insert(*curKid); - } - } - } - INSTRUCTION_EXPORT void Operand::addEffectiveWriteAddresses(std::set& memAccessors) const - { - if(m_isWritten && boost::dynamic_pointer_cast(op_value)) - { - std::vector tmp; - op_value->getChildren(tmp); - for(std::vector::const_iterator curKid = tmp.begin(); - curKid != tmp.end(); - ++curKid) - { - memAccessors.insert(*curKid); - } - } - } + INSTRUCTION_EXPORT bool Operand::isRead(Expression::Ptr candidate) const + { + // The whole expression of a read, any subexpression of a write + return op_value->isUsed(candidate) && (m_isRead || !(*candidate == *op_value)); + } + INSTRUCTION_EXPORT bool Operand::isWritten(Expression::Ptr candidate) const + { + // Whole expression of a write + return m_isWritten && (*op_value == *candidate); + } + INSTRUCTION_EXPORT bool Operand::readsMemory() const + { + return (dyncompat::dynamic_pointer_cast(op_value) && m_isRead); + } + INSTRUCTION_EXPORT bool Operand::writesMemory() const + { + return (dyncompat::dynamic_pointer_cast(op_value) && m_isWritten); + } + INSTRUCTION_EXPORT void Operand::addEffectiveReadAddresses(std::set& memAccessors) const + { + if(m_isRead && dyncompat::dynamic_pointer_cast(op_value)) + { + std::vector tmp; + op_value->getChildren(tmp); + for(std::vector::const_iterator curKid = tmp.begin(); + curKid != tmp.end(); + ++curKid) + { + memAccessors.insert(*curKid); + } + } + } + INSTRUCTION_EXPORT void Operand::addEffectiveWriteAddresses(std::set& memAccessors) const + { + if(m_isWritten && dyncompat::dynamic_pointer_cast(op_value)) + { + std::vector tmp; + op_value->getChildren(tmp); + for(std::vector::const_iterator curKid = tmp.begin(); + curKid != tmp.end(); + ++curKid) + { + memAccessors.insert(*curKid); + } + } + } - INSTRUCTION_EXPORT std::string Operand::format(Architecture arch, Address addr) const - { - if(!op_value) return "ERROR: format() called on empty operand!"; - if (addr) { - Expression::Ptr thePC = Expression::Ptr(new RegisterAST(MachRegister::getPC(arch))); - op_value->bind(thePC.get(), Result(u32, addr)); - Result res = op_value->eval(); - if (res.defined) { - char hex[20]; - snprintf(hex, 20, "%lux", res.convert()); - return string(hex); - } - } - return op_value->format(arch); - } + INSTRUCTION_EXPORT std::string Operand::format(Architecture arch, Address addr) const + { + if(!op_value) return "ERROR: format() called on empty operand!"; + if (addr) { + Expression::Ptr thePC = Expression::Ptr(new RegisterAST(MachRegister::getPC(arch))); + op_value->bind(thePC.get(), Result(u32, addr)); + Result res = op_value->eval(); + if (res.defined) { + char hex[20]; + snprintf(hex, 20, "0x%lx", res.convert()); + return string(hex); + } + } + auto s = op_value->format(arch); + if (!s.compare(0, 2, "##")) { + s.replace(0, 2, "0x0("); // fix-up ##X to indirection syntax 0x0(X) + s += ')'; + } + return s; + } - INSTRUCTION_EXPORT Expression::Ptr Operand::getValue() const - { - return op_value; + INSTRUCTION_EXPORT Expression::Ptr Operand::getValue() const + { + return op_value; + } } - } } diff --git a/instructionAPI/src/Operation.C b/instructionAPI/src/Operation.C index 084312d878..a7939219f6 100644 --- a/instructionAPI/src/Operation.C +++ b/instructionAPI/src/Operation.C @@ -30,18 +30,19 @@ #define INSIDE_INSTRUCTION_API +#include #include "common/src/vgannotations.h" -#include "common/src/Types.h" #include "Operation_impl.h" #include "common/src/arch-x86.h" #include "entryIDs.h" -#include "common/src/Singleton.h" #include "Register.h" #include #include #include "concurrent.h" #include "common/src/singleton_object_pool.h" +#include "registers/x86_regs.h" +#include "registers/x86_64_regs.h" using namespace NS_x86; #include "BinaryFunction.h" @@ -49,503 +50,502 @@ using namespace NS_x86; namespace Dyninst { - namespace InstructionAPI - { - RegisterAST::Ptr makeRegFromID(MachRegister regID, unsigned int low, unsigned int high) + namespace InstructionAPI { - return make_shared(singleton_object_pool::construct(regID, low, high)); - } - RegisterAST::Ptr makeRegFromID(MachRegister regID) - { - return make_shared(singleton_object_pool::construct(regID, 0, regID.size() * 8)); - } + RegisterAST::Ptr makeRegFromID(MachRegister regID, unsigned int low, unsigned int high) + { + return make_shared(singleton_object_pool::construct(regID, low, high)); + } + RegisterAST::Ptr makeRegFromID(MachRegister regID) + { + return make_shared(singleton_object_pool::construct(regID, 0, regID.size() * 8)); + } - Operation_impl::Operation_impl(entryID id, std::string m, Architecture arch) - : operationID(id), archDecodedFrom(arch), prefixID(prefix_none) - { - switch(archDecodedFrom) + Operation::Operation(entryID id, std::string m, Architecture arch) + : operationID(id), archDecodedFrom(arch), prefixID(prefix_none) { - case Arch_x86: - case Arch_ppc32: - addrWidth = u32; - break; - default: - addrWidth = u64; - break; + switch(archDecodedFrom) + { + case Arch_x86: + case Arch_ppc32: + addrWidth = u32; + break; + default: + addrWidth = u64; + break; + } + segPrefix = 0; + isVectorInsn = false; + mnemonic = m; } - segPrefix = 0; - isVectorInsn = false; - mnemonic = m; - } - static bool getVectorizationInfo(ia32_entry* e) - { - for(int i = 0; i < 3; i++) + static bool getVectorizationInfo(ia32_entry* e) { - switch(e->operands[i].admet) + for(int i = 0; i < 3; i++) { - case am_V: - case am_W: - case am_P: - case am_Q: - case am_HK: - case am_H: - case am_X: - case am_XH: - case am_XU: - case am_XV: - case am_XW: - case am_Y: - case am_YH: - case am_YU: - case am_YV: - case am_YW: - case am_VK: - case am_WK: + switch(e->operands[i].admet) + { + case am_V: + case am_W: + case am_P: + case am_Q: + case am_HK: + case am_H: + case am_X: + case am_XH: + case am_XU: + case am_XV: + case am_XW: + case am_Y: + case am_YH: + case am_YU: + case am_YV: + case am_YW: + case am_VK: + case am_WK: - return true; + return true; + default: + break; + } + } + return false; + } + + Operation::Operation(ia32_entry* e, ia32_prefixes* p, ia32_locations* l, Architecture arch) : + archDecodedFrom(arch), prefixID(prefix_none) + { + segPrefix = 0; + isVectorInsn = getVectorizationInfo(e); + operationID = e->getID(l); + // Defaults for no size prefix + switch(archDecodedFrom) + { + case Arch_x86: + case Arch_ppc32: + addrWidth = u32; + break; default: + addrWidth = u64; break; } + if(p && p->getCount()) + { + if (p->getPrefix(0) == PREFIX_REP) prefixID = prefix_rep; + if (p->getPrefix(0) == PREFIX_REPNZ) prefixID = prefix_repnz; + segPrefix = p->getPrefix(1); + if(p->getAddrSzPrefix()) + { + addrWidth = u16; + } + } } - return false; - } - - Operation_impl::Operation_impl(ia32_entry* e, ia32_prefixes* p, ia32_locations* l, Architecture arch) : - archDecodedFrom(arch), prefixID(prefix_none) - { - segPrefix = 0; - isVectorInsn = getVectorizationInfo(e); - operationID = e->getID(l); - // Defaults for no size prefix - switch(archDecodedFrom) - { - case Arch_x86: - case Arch_ppc32: - addrWidth = u32; - break; - default: - addrWidth = u64; - break; - } - if(p && p->getCount()) - { - if (p->getPrefix(0) == PREFIX_REP) prefixID = prefix_rep; - if (p->getPrefix(0) == PREFIX_REPNZ) prefixID = prefix_repnz; - segPrefix = p->getPrefix(1); - if(p->getAddrSzPrefix()) + + Operation::Operation(const Operation& o) { - addrWidth = u16; + operationID = o.operationID; + archDecodedFrom = o.archDecodedFrom; + prefixID = o.prefixID; + addrWidth = o.addrWidth; + segPrefix = o.segPrefix; + isVectorInsn = o.isVectorInsn; + mnemonic = o.mnemonic; + } + const Operation& Operation::operator=(const Operation& o) + { + operationID = o.operationID; + archDecodedFrom = o.archDecodedFrom; + prefixID = o.prefixID; + addrWidth = o.addrWidth; + segPrefix = o.segPrefix; + isVectorInsn = o.isVectorInsn; + mnemonic = o.mnemonic; + return *this; + } + Operation::Operation() + { + operationID = e_No_Entry; + archDecodedFrom = Arch_none; + prefixID = prefix_none; + addrWidth = u64; + segPrefix = 0; + isVectorInsn = false; } - } - } - - Operation_impl::Operation_impl(const Operation_impl& o) - { - operationID = o.operationID; - archDecodedFrom = o.archDecodedFrom; - prefixID = o.prefixID; - addrWidth = o.addrWidth; - segPrefix = o.segPrefix; - isVectorInsn = o.isVectorInsn; - mnemonic = o.mnemonic; - } - const Operation_impl& Operation_impl::operator=(const Operation_impl& o) - { - operationID = o.operationID; - archDecodedFrom = o.archDecodedFrom; - prefixID = o.prefixID; - addrWidth = o.addrWidth; - segPrefix = o.segPrefix; - isVectorInsn = o.isVectorInsn; - mnemonic = o.mnemonic; - return *this; - } - Operation_impl::Operation_impl() - { - operationID = e_No_Entry; - archDecodedFrom = Arch_none; - prefixID = prefix_none; - addrWidth = u64; - segPrefix = 0; - isVectorInsn = false; - } - - const Operation_impl::registerSet& Operation_impl::implicitReads() - { - SetUpNonOperandData(); - - return otherRead; - } - const Operation_impl::registerSet& Operation_impl::implicitWrites() - { - SetUpNonOperandData(); - return otherWritten; - } - bool Operation_impl::isRead(Expression::Ptr candidate) - { - - SetUpNonOperandData(); - - for(registerSet::const_iterator r = otherRead.begin(); - r != otherRead.end(); - ++r) - { - if(*candidate == *(*r)) - { - return true; - } - } - for(VCSet::const_iterator e = otherEffAddrsRead.begin(); - e != otherEffAddrsRead.end(); - ++e) - { - if(*candidate == *(*e)) - { - return true; - } - } - return false; - } - const Operation_impl::VCSet& Operation_impl::getImplicitMemReads() - { - SetUpNonOperandData(); - return otherEffAddrsRead; - } - const Operation_impl::VCSet& Operation_impl::getImplicitMemWrites() - { - SetUpNonOperandData(); - return otherEffAddrsWritten; - } + const Operation::registerSet& Operation::implicitReads() + { + SetUpNonOperandData(); - bool Operation_impl::isWritten(Expression::Ptr candidate) - { - - SetUpNonOperandData(); - - for(registerSet::const_iterator r = otherWritten.begin(); - r != otherWritten.end(); - ++r) - { - if(*candidate == *(*r)) - { - return true; - } - } - for(VCSet::const_iterator e = otherEffAddrsWritten.begin(); - e != otherEffAddrsWritten.end(); - ++e) - { - if(*candidate == *(*e)) - { - return true; - } - } - return false; - } - - std::string Operation_impl::format() const - { - if(mnemonic != "") + return otherRead; + } + const Operation::registerSet& Operation::implicitWrites() { - return mnemonic; + SetUpNonOperandData(); + + return otherWritten; } - dyn_hash_map::const_iterator foundPrefix = prefixEntryNames_IAPI.find(prefixID); - dyn_hash_map::const_iterator found = entryNames_IAPI.find(operationID); - std::string result; - if(foundPrefix != prefixEntryNames_IAPI.end()) - { - result += (foundPrefix->second + " "); - } - if(found != entryNames_IAPI.end()) - { - result += found->second; - } - else - { - result += "[INVALID]"; - } - return result; - } + bool Operation::isRead(Expression::Ptr candidate) + { - entryID Operation_impl::getID() const - { - return operationID; - } + SetUpNonOperandData(); - prefixEntryID Operation_impl::getPrefixID() const - { - return prefixID; - } + for(registerSet::const_iterator r = otherRead.begin(); + r != otherRead.end(); + ++r) + { + if(*candidate == *(*r)) + { + return true; + } + } + for(VCSet::const_iterator e = otherEffAddrsRead.begin(); + e != otherEffAddrsRead.end(); + ++e) + { + if(*candidate == *(*e)) + { + return true; + } + } + return false; + } + const Operation::VCSet& Operation::getImplicitMemReads() + { + SetUpNonOperandData(); + return otherEffAddrsRead; + } + const Operation::VCSet& Operation::getImplicitMemWrites() + { + SetUpNonOperandData(); + return otherEffAddrsWritten; + } - struct OperationMaps - { - typedef dyn_c_hash_map reg_info_t; - typedef dyn_c_hash_map mem_info_t; - public: - OperationMaps(Architecture arch) - { - thePC.insert(RegisterAST::Ptr(new RegisterAST(MachRegister::getPC(arch)))); - pcAndSP.insert(RegisterAST::Ptr(new RegisterAST(MachRegister::getPC(arch)))); - pcAndSP.insert(RegisterAST::Ptr(new RegisterAST(MachRegister::getStackPointer(arch)))); - stackPointer.insert(RegisterAST::Ptr(new RegisterAST(MachRegister::getStackPointer(arch)))); - stackPointerAsExpr.insert(RegisterAST::Ptr(new RegisterAST(MachRegister::getStackPointer(arch)))); - framePointer.insert(RegisterAST::Ptr(new RegisterAST(MachRegister::getFramePointer(arch)))); - spAndBP.insert(RegisterAST::Ptr(new RegisterAST(MachRegister::getStackPointer(arch)))); - spAndBP.insert(RegisterAST::Ptr(new RegisterAST(MachRegister::getFramePointer(arch)))); - si.insert(RegisterAST::Ptr(new RegisterAST(arch == Arch_x86_64 ? x86_64::rsi : x86::esi))); - di.insert(RegisterAST::Ptr(new RegisterAST(arch == Arch_x86_64 ? x86_64::rdi : x86::edi))); - si_and_di.insert(RegisterAST::Ptr(new RegisterAST(arch == Arch_x86_64 ? x86_64::rsi : x86::esi))); - si_and_di.insert(RegisterAST::Ptr(new RegisterAST(arch == Arch_x86_64 ? x86_64::rdi : x86::edi))); - - nonOperandRegisterReads.insert(make_pair(e_call, pcAndSP)); - nonOperandRegisterReads.insert(make_pair(e_ret_near, stackPointer)); - nonOperandRegisterReads.insert(make_pair(e_ret_far, stackPointer)); - nonOperandRegisterReads.insert(make_pair(e_leave, framePointer)); - nonOperandRegisterReads.insert(make_pair(e_enter, spAndBP)); - - nonOperandRegisterWrites.insert(make_pair(e_call, pcAndSP)); - nonOperandRegisterWrites.insert(make_pair(e_ret_near, pcAndSP)); - nonOperandRegisterWrites.insert(make_pair(e_ret_far, pcAndSP)); - nonOperandRegisterWrites.insert(make_pair(e_leave, spAndBP)); - nonOperandRegisterWrites.insert(make_pair(e_enter, spAndBP)); - - nonOperandRegisterWrites.insert(make_pair(e_loop, thePC)); - nonOperandRegisterWrites.insert(make_pair(e_loope, thePC)); - nonOperandRegisterWrites.insert(make_pair(e_loopn, thePC)); - - nonOperandRegisterWrites.insert(make_pair(e_jb, thePC)); - nonOperandRegisterWrites.insert(make_pair(e_jb_jnaej_j, thePC)); - nonOperandRegisterWrites.insert(make_pair(e_jbe, thePC)); - nonOperandRegisterWrites.insert(make_pair(e_jcxz_jec, thePC)); - nonOperandRegisterWrites.insert(make_pair(e_jl, thePC)); - nonOperandRegisterWrites.insert(make_pair(e_jle, thePC)); - nonOperandRegisterWrites.insert(make_pair(e_jmp, thePC)); - nonOperandRegisterWrites.insert(make_pair(e_jnb, thePC)); - nonOperandRegisterWrites.insert(make_pair(e_jnb_jae_j, thePC)); - nonOperandRegisterWrites.insert(make_pair(e_jnbe, thePC)); - nonOperandRegisterWrites.insert(make_pair(e_jnl, thePC)); - nonOperandRegisterWrites.insert(make_pair(e_jnle, thePC)); - nonOperandRegisterWrites.insert(make_pair(e_jno, thePC)); - nonOperandRegisterWrites.insert(make_pair(e_jnp, thePC)); - nonOperandRegisterWrites.insert(make_pair(e_jns, thePC)); - nonOperandRegisterWrites.insert(make_pair(e_jnz, thePC)); - nonOperandRegisterWrites.insert(make_pair(e_jo, thePC)); - nonOperandRegisterWrites.insert(make_pair(e_jp, thePC)); - nonOperandRegisterWrites.insert(make_pair(e_js, thePC)); - nonOperandRegisterWrites.insert(make_pair(e_jz, thePC)); - - nonOperandMemoryReads.insert(make_pair(e_pop, stackPointerAsExpr)); - nonOperandMemoryReads.insert(make_pair(e_popa, stackPointerAsExpr)); - nonOperandMemoryReads.insert(make_pair(e_popad, stackPointerAsExpr)); - nonOperandMemoryWrites.insert(make_pair(e_push, stackPointerAsExpr)); - nonOperandMemoryWrites.insert(make_pair(e_pusha, stackPointerAsExpr)); - nonOperandMemoryWrites.insert(make_pair(e_pushad, stackPointerAsExpr)); - nonOperandMemoryWrites.insert(make_pair(e_call, stackPointerAsExpr)); - nonOperandMemoryReads.insert(make_pair(e_ret_near, stackPointerAsExpr)); - nonOperandMemoryReads.insert(make_pair(e_ret_far, stackPointerAsExpr)); - nonOperandMemoryReads.insert(make_pair(e_leave, stackPointerAsExpr)); - - nonOperandRegisterWrites.insert(make_pair(e_cmpsb, si_and_di)); - nonOperandRegisterWrites.insert(make_pair(e_cmpsd, si_and_di)); - nonOperandRegisterWrites.insert(make_pair(e_cmpsw, si_and_di)); - nonOperandRegisterWrites.insert(make_pair(e_movsb, si_and_di)); - nonOperandRegisterWrites.insert(make_pair(e_movsd, si_and_di)); - nonOperandRegisterWrites.insert(make_pair(e_movsw, si_and_di)); - nonOperandRegisterWrites.insert(make_pair(e_insb, di)); - nonOperandRegisterWrites.insert(make_pair(e_insd, di)); - nonOperandRegisterWrites.insert(make_pair(e_insw, di)); - nonOperandRegisterWrites.insert(make_pair(e_stosb, di)); - nonOperandRegisterWrites.insert(make_pair(e_stosd, di)); - nonOperandRegisterWrites.insert(make_pair(e_stosw, di)); - nonOperandRegisterWrites.insert(make_pair(e_scasb, di)); - nonOperandRegisterWrites.insert(make_pair(e_scasd, di)); - nonOperandRegisterWrites.insert(make_pair(e_scasw, di)); - nonOperandRegisterWrites.insert(make_pair(e_lodsb, di)); - nonOperandRegisterWrites.insert(make_pair(e_lodsd, di)); - nonOperandRegisterWrites.insert(make_pair(e_lodsw, di)); - nonOperandRegisterWrites.insert(make_pair(e_outsb, di)); - nonOperandRegisterWrites.insert(make_pair(e_outsd, di)); - nonOperandRegisterWrites.insert(make_pair(e_outsw, di)); - - - } - Operation_impl::registerSet thePC; - Operation_impl::registerSet pcAndSP; - Operation_impl::registerSet stackPointer; - Operation_impl::VCSet stackPointerAsExpr; - Operation_impl::registerSet framePointer; - Operation_impl::registerSet spAndBP; - Operation_impl::registerSet si; - Operation_impl::registerSet di; - Operation_impl::registerSet si_and_di; - - reg_info_t nonOperandRegisterReads; - reg_info_t nonOperandRegisterWrites; - - mem_info_t nonOperandMemoryReads; - mem_info_t nonOperandMemoryWrites; - }; - OperationMaps op_data_32(Arch_x86); - OperationMaps op_data_64(Arch_x86_64); - const OperationMaps& op_data(Architecture arch) - { - switch(arch) + bool Operation::isWritten(Expression::Ptr candidate) { - case Arch_x86: - return op_data_32; - case Arch_x86_64: - return op_data_64; - default: - return op_data_32; + + SetUpNonOperandData(); + + for(registerSet::const_iterator r = otherWritten.begin(); + r != otherWritten.end(); + ++r) + { + if(*candidate == *(*r)) + { + return true; + } + } + for(VCSet::const_iterator e = otherEffAddrsWritten.begin(); + e != otherEffAddrsWritten.end(); + ++e) + { + if(*candidate == *(*e)) + { + return true; + } + } + return false; } - } - void Operation_impl::SetUpNonOperandData() - { - if (archDecodedFrom != Arch_x86 && archDecodedFrom != Arch_x86_64) return; - std::call_once(data_initialized, [&]() { - if (prefixID == prefix_rep || prefixID == prefix_repnz) { - otherRead.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::df : x86_64::df)); - otherRead.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::ecx : x86_64::rcx)); - otherWritten.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::ecx : x86_64::rcx)); - if(prefixID == prefix_repnz) + + std::string Operation::format() const + { + if(mnemonic != "") + { + return mnemonic; + } + dyn_hash_map::const_iterator foundPrefix = prefixEntryNames_IAPI.find(prefixID); + dyn_hash_map::const_iterator found = entryNames_IAPI.find(operationID); + std::string result; + if(foundPrefix != prefixEntryNames_IAPI.end()) + { + result += (foundPrefix->second + " "); + } + if(found != entryNames_IAPI.end()) + { + result += found->second; + } + else { - otherRead.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::zf : x86_64::zf)); + result += "[INVALID]"; } + return result; } - switch(segPrefix) + + entryID Operation::getID() const { - case PREFIX_SEGCS: - otherRead.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::cs : x86_64::cs)); - break; - case PREFIX_SEGDS: - otherRead.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::ds : x86_64::ds)); - break; - case PREFIX_SEGES: - otherRead.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::es : x86_64::es)); - break; - case PREFIX_SEGFS: - otherRead.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::fs : x86_64::fs)); - break; - case PREFIX_SEGGS: - otherRead.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::gs : x86_64::gs)); - break; - case PREFIX_SEGSS: - otherRead.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::ss : x86_64::ss)); - break; + return operationID; } - OperationMaps::reg_info_t::const_accessor a, b; - if (op_data(archDecodedFrom).nonOperandRegisterReads.find(a, operationID)) { - otherRead.insert(a->second.begin(), a->second.end()); - } - if (op_data(archDecodedFrom).nonOperandRegisterWrites.find(b, operationID)) { - otherWritten.insert(b->second.begin(), b->second.end()); - } - OperationMaps::mem_info_t::const_accessor c, d; - if (op_data(archDecodedFrom).nonOperandMemoryReads.find(c, operationID)) { - otherEffAddrsRead.insert(c->second.begin(), c->second.end()); + prefixEntryID Operation::getPrefixID() const + { + return prefixID; + } + + struct OperationMaps + { + typedef dyn_c_hash_map reg_info_t; + typedef dyn_c_hash_map mem_info_t; + public: + OperationMaps(Architecture arch) + { + thePC.insert(RegisterAST::Ptr(new RegisterAST(MachRegister::getPC(arch)))); + pcAndSP.insert(RegisterAST::Ptr(new RegisterAST(MachRegister::getPC(arch)))); + pcAndSP.insert(RegisterAST::Ptr(new RegisterAST(MachRegister::getStackPointer(arch)))); + stackPointer.insert(RegisterAST::Ptr(new RegisterAST(MachRegister::getStackPointer(arch)))); + stackPointerAsExpr.insert(RegisterAST::Ptr(new RegisterAST(MachRegister::getStackPointer(arch)))); + framePointer.insert(RegisterAST::Ptr(new RegisterAST(MachRegister::getFramePointer(arch)))); + spAndBP.insert(RegisterAST::Ptr(new RegisterAST(MachRegister::getStackPointer(arch)))); + spAndBP.insert(RegisterAST::Ptr(new RegisterAST(MachRegister::getFramePointer(arch)))); + si.insert(RegisterAST::Ptr(new RegisterAST(arch == Arch_x86_64 ? x86_64::rsi : x86::esi))); + di.insert(RegisterAST::Ptr(new RegisterAST(arch == Arch_x86_64 ? x86_64::rdi : x86::edi))); + si_and_di.insert(RegisterAST::Ptr(new RegisterAST(arch == Arch_x86_64 ? x86_64::rsi : x86::esi))); + si_and_di.insert(RegisterAST::Ptr(new RegisterAST(arch == Arch_x86_64 ? x86_64::rdi : x86::edi))); + + nonOperandRegisterReads.insert(make_pair(e_call, pcAndSP)); + nonOperandRegisterReads.insert(make_pair(e_ret_near, stackPointer)); + nonOperandRegisterReads.insert(make_pair(e_ret_far, stackPointer)); + nonOperandRegisterReads.insert(make_pair(e_leave, framePointer)); + nonOperandRegisterReads.insert(make_pair(e_enter, spAndBP)); + + nonOperandRegisterWrites.insert(make_pair(e_call, pcAndSP)); + nonOperandRegisterWrites.insert(make_pair(e_ret_near, pcAndSP)); + nonOperandRegisterWrites.insert(make_pair(e_ret_far, pcAndSP)); + nonOperandRegisterWrites.insert(make_pair(e_leave, spAndBP)); + nonOperandRegisterWrites.insert(make_pair(e_enter, spAndBP)); + + nonOperandRegisterWrites.insert(make_pair(e_loop, thePC)); + nonOperandRegisterWrites.insert(make_pair(e_loope, thePC)); + nonOperandRegisterWrites.insert(make_pair(e_loopne, thePC)); + + nonOperandRegisterWrites.insert(make_pair(e_jb, thePC)); + nonOperandRegisterWrites.insert(make_pair(e_jb_jnaej_j, thePC)); + nonOperandRegisterWrites.insert(make_pair(e_jbe, thePC)); + nonOperandRegisterWrites.insert(make_pair(e_jcxz_jec, thePC)); + nonOperandRegisterWrites.insert(make_pair(e_jl, thePC)); + nonOperandRegisterWrites.insert(make_pair(e_jle, thePC)); + nonOperandRegisterWrites.insert(make_pair(e_jmp, thePC)); + nonOperandRegisterWrites.insert(make_pair(e_jae, thePC)); + nonOperandRegisterWrites.insert(make_pair(e_jnb_jae_j, thePC)); + nonOperandRegisterWrites.insert(make_pair(e_ja, thePC)); + nonOperandRegisterWrites.insert(make_pair(e_jge, thePC)); + nonOperandRegisterWrites.insert(make_pair(e_jg, thePC)); + nonOperandRegisterWrites.insert(make_pair(e_jno, thePC)); + nonOperandRegisterWrites.insert(make_pair(e_jnp, thePC)); + nonOperandRegisterWrites.insert(make_pair(e_jns, thePC)); + nonOperandRegisterWrites.insert(make_pair(e_jne, thePC)); + nonOperandRegisterWrites.insert(make_pair(e_jo, thePC)); + nonOperandRegisterWrites.insert(make_pair(e_jp, thePC)); + nonOperandRegisterWrites.insert(make_pair(e_js, thePC)); + nonOperandRegisterWrites.insert(make_pair(e_je, thePC)); + + nonOperandMemoryReads.insert(make_pair(e_pop, stackPointerAsExpr)); + nonOperandMemoryReads.insert(make_pair(e_popal, stackPointerAsExpr)); + nonOperandMemoryReads.insert(make_pair(e_popaw, stackPointerAsExpr)); + nonOperandMemoryWrites.insert(make_pair(e_push, stackPointerAsExpr)); + nonOperandMemoryWrites.insert(make_pair(e_pushal, stackPointerAsExpr)); + nonOperandMemoryWrites.insert(make_pair(e_call, stackPointerAsExpr)); + nonOperandMemoryReads.insert(make_pair(e_ret_near, stackPointerAsExpr)); + nonOperandMemoryReads.insert(make_pair(e_ret_far, stackPointerAsExpr)); + nonOperandMemoryReads.insert(make_pair(e_leave, stackPointerAsExpr)); + + nonOperandRegisterWrites.insert(make_pair(e_cmpsb, si_and_di)); + nonOperandRegisterWrites.insert(make_pair(e_cmpsd, si_and_di)); + nonOperandRegisterWrites.insert(make_pair(e_cmpsw, si_and_di)); + nonOperandRegisterWrites.insert(make_pair(e_movsb, si_and_di)); + nonOperandRegisterWrites.insert(make_pair(e_movsd, si_and_di)); + nonOperandRegisterWrites.insert(make_pair(e_movsw, si_and_di)); + nonOperandRegisterWrites.insert(make_pair(e_insb, di)); + nonOperandRegisterWrites.insert(make_pair(e_insd, di)); + nonOperandRegisterWrites.insert(make_pair(e_insw, di)); + nonOperandRegisterWrites.insert(make_pair(e_stosb, di)); + nonOperandRegisterWrites.insert(make_pair(e_stosd, di)); + nonOperandRegisterWrites.insert(make_pair(e_stosw, di)); + nonOperandRegisterWrites.insert(make_pair(e_scasb, di)); + nonOperandRegisterWrites.insert(make_pair(e_scasd, di)); + nonOperandRegisterWrites.insert(make_pair(e_scasw, di)); + nonOperandRegisterWrites.insert(make_pair(e_lodsb, di)); + nonOperandRegisterWrites.insert(make_pair(e_lodsd, di)); + nonOperandRegisterWrites.insert(make_pair(e_lodsw, di)); + nonOperandRegisterWrites.insert(make_pair(e_outsb, di)); + nonOperandRegisterWrites.insert(make_pair(e_outsd, di)); + nonOperandRegisterWrites.insert(make_pair(e_outsw, di)); + + } - if (operationID == e_push) { - BinaryFunction::funcT::Ptr adder(new BinaryFunction::addResult()); - // special case for push: we write at the new value of the SP. - Result dummy(addrWidth, 0); - Expression::Ptr push_addr(new BinaryFunction( - *(op_data(archDecodedFrom).stackPointerAsExpr.begin()), - Immediate::makeImmediate(Result(s8, -(dummy.size()))), - addrWidth, - adder)); - - otherEffAddrsWritten.insert(push_addr); - - } else { - if (op_data(archDecodedFrom).nonOperandMemoryWrites.find(d, operationID)) { - otherEffAddrsWritten.insert(d->second.begin(), d->second.end()); - } + Operation::registerSet thePC; + Operation::registerSet pcAndSP; + Operation::registerSet stackPointer; + Operation::VCSet stackPointerAsExpr; + Operation::registerSet framePointer; + Operation::registerSet spAndBP; + Operation::registerSet si; + Operation::registerSet di; + Operation::registerSet si_and_di; + + reg_info_t nonOperandRegisterReads; + reg_info_t nonOperandRegisterWrites; + + mem_info_t nonOperandMemoryReads; + mem_info_t nonOperandMemoryWrites; + }; + OperationMaps op_data_32(Arch_x86); + OperationMaps op_data_64(Arch_x86_64); + const OperationMaps& op_data(Architecture arch) + { + switch(arch) + { + case Arch_x86: + return op_data_32; + case Arch_x86_64: + return op_data_64; + default: + return op_data_32; } + } + void Operation::SetUpNonOperandData() + { + if (archDecodedFrom != Arch_x86 && archDecodedFrom != Arch_x86_64) return; + std::call_once(data_initialized, [&]() { + if (prefixID == prefix_rep || prefixID == prefix_repnz) { + otherRead.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::df : x86_64::df)); + otherRead.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::ecx : x86_64::rcx)); + otherWritten.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::ecx : x86_64::rcx)); + if(prefixID == prefix_repnz) + { + otherRead.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::zf : x86_64::zf)); + } + } + switch(segPrefix) + { + case PREFIX_SEGCS: + otherRead.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::cs : x86_64::cs)); + break; + case PREFIX_SEGDS: + otherRead.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::ds : x86_64::ds)); + break; + case PREFIX_SEGES: + otherRead.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::es : x86_64::es)); + break; + case PREFIX_SEGFS: + otherRead.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::fs : x86_64::fs)); + break; + case PREFIX_SEGGS: + otherRead.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::gs : x86_64::gs)); + break; + case PREFIX_SEGSS: + otherRead.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::ss : x86_64::ss)); + break; + } - dyn_hash_map::const_iterator found = ia32_instruction::getFlagTable().find(operationID); - if (found != ia32_instruction::getFlagTable().end()) { - for (unsigned i = 0; i < found->second.readFlags.size(); i++) { - switch (found->second.readFlags[i]) { - case x86::icf: - otherRead.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::cf : x86_64::cf)); - break; - case x86::ipf: - otherRead.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::pf : x86_64::pf)); - break; - case x86::iaf: - otherRead.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::af : x86_64::af)); - break; - case x86::izf: - otherRead.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::zf : x86_64::zf)); - break; - case x86::isf: - otherRead.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::sf : x86_64::sf)); - break; - case x86::itf: - otherRead.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::tf : x86_64::tf)); - break; - case x86::idf: - otherRead.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::df : x86_64::df)); - break; - case x86::iof: - otherRead.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::of : x86_64::of)); - break; - case x86::int_: - otherRead.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::nt_ : x86_64::nt_)); - break; - case x86::iif_: - otherRead.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::if_ : x86_64::if_)); - break; - default: - assert(0); + OperationMaps::reg_info_t::const_accessor a, b; + if (op_data(archDecodedFrom).nonOperandRegisterReads.find(a, operationID)) { + otherRead.insert(a->second.begin(), a->second.end()); } - } + if (op_data(archDecodedFrom).nonOperandRegisterWrites.find(b, operationID)) { + otherWritten.insert(b->second.begin(), b->second.end()); + } + OperationMaps::mem_info_t::const_accessor c, d; + if (op_data(archDecodedFrom).nonOperandMemoryReads.find(c, operationID)) { + otherEffAddrsRead.insert(c->second.begin(), c->second.end()); + } + if (operationID == e_push) { + BinaryFunction::funcT::Ptr adder(new BinaryFunction::addResult()); + // special case for push: we write at the new value of the SP. + Result dummy(addrWidth, 0); + Expression::Ptr push_addr(new BinaryFunction( + *(op_data(archDecodedFrom).stackPointerAsExpr.begin()), + Immediate::makeImmediate(Result(s8, -(dummy.size()))), + addrWidth, + adder)); + + otherEffAddrsWritten.insert(push_addr); - for (unsigned j = 0; j < found->second.writtenFlags.size(); j++) { - switch (found->second.writtenFlags[j]) { - case x86::icf: - otherWritten.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::cf : x86_64::cf)); - break; - case x86::ipf: - otherWritten.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::pf : x86_64::pf)); - break; - case x86::iaf: - otherWritten.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::af : x86_64::af)); - break; - case x86::izf: - otherWritten.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::zf : x86_64::zf)); - break; - case x86::isf: - otherWritten.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::sf : x86_64::sf)); - break; - case x86::itf: - otherWritten.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::tf : x86_64::tf)); - break; - case x86::idf: - otherWritten.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::df : x86_64::df)); - break; - case x86::iof: - otherWritten.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::of : x86_64::of)); - break; - case x86::int_: - otherWritten.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::nt_ : x86_64::nt_)); - break; - case x86::iif_: - otherWritten.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::if_ : x86_64::if_)); - break; - default: - fprintf(stderr, "ERROR: unhandled entry %s\n", - found->second.writtenFlags[j].name().c_str()); - assert(0); + } else { + if (op_data(archDecodedFrom).nonOperandMemoryWrites.find(d, operationID)) { + otherEffAddrsWritten.insert(d->second.begin(), d->second.end()); + } } - } - } - }); - return; + + dyn_hash_map::const_iterator found = ia32_instruction::getFlagTable().find(operationID); + if (found != ia32_instruction::getFlagTable().end()) { + for (unsigned i = 0; i < found->second.readFlags.size(); i++) { + switch (found->second.readFlags[i]) { + case x86::icf: + otherRead.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::cf : x86_64::cf)); + break; + case x86::ipf: + otherRead.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::pf : x86_64::pf)); + break; + case x86::iaf: + otherRead.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::af : x86_64::af)); + break; + case x86::izf: + otherRead.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::zf : x86_64::zf)); + break; + case x86::isf: + otherRead.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::sf : x86_64::sf)); + break; + case x86::itf: + otherRead.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::tf : x86_64::tf)); + break; + case x86::idf: + otherRead.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::df : x86_64::df)); + break; + case x86::iof: + otherRead.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::of : x86_64::of)); + break; + case x86::int_: + otherRead.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::nt_ : x86_64::nt_)); + break; + case x86::iif_: + otherRead.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::if_ : x86_64::if_)); + break; + default: + assert(0); + } + } + + for (unsigned j = 0; j < found->second.writtenFlags.size(); j++) { + switch (found->second.writtenFlags[j]) { + case x86::icf: + otherWritten.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::cf : x86_64::cf)); + break; + case x86::ipf: + otherWritten.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::pf : x86_64::pf)); + break; + case x86::iaf: + otherWritten.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::af : x86_64::af)); + break; + case x86::izf: + otherWritten.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::zf : x86_64::zf)); + break; + case x86::isf: + otherWritten.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::sf : x86_64::sf)); + break; + case x86::itf: + otherWritten.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::tf : x86_64::tf)); + break; + case x86::idf: + otherWritten.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::df : x86_64::df)); + break; + case x86::iof: + otherWritten.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::of : x86_64::of)); + break; + case x86::int_: + otherWritten.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::nt_ : x86_64::nt_)); + break; + case x86::iif_: + otherWritten.insert(makeRegFromID((archDecodedFrom == Arch_x86) ? x86::if_ : x86_64::if_)); + break; + default: + fprintf(stderr, "ERROR: unhandled entry %s\n", + found->second.writtenFlags[j].name().c_str()); + assert(0); + } + } + } + }); + return; + } } - } } diff --git a/instructionAPI/src/Register.C b/instructionAPI/src/Register.C index 306328ae93..a476489bb3 100644 --- a/instructionAPI/src/Register.C +++ b/instructionAPI/src/Register.C @@ -29,15 +29,17 @@ */ #include "Register.h" -#include "../../common/src/Singleton.h" #include #include #include #include "Visitor.h" #include "../../common/src/singleton_object_pool.h" #include "InstructionDecoder-power.h" -#include "dyn_regs.h" +#include "registers/MachRegister.h" +#include "Architecture.h" #include "ArchSpecificFormatters.h" +#include "../../common/h/compiler_diagnostics.h" +#include "registers/x86_regs.h" using namespace std; @@ -48,19 +50,19 @@ namespace Dyninst { namespace InstructionAPI { - RegisterAST::RegisterAST(MachRegister r, unsigned int lowbit, unsigned int highbit) : - Expression(r), m_Reg(r), m_Low(lowbit), m_High(highbit) + RegisterAST::RegisterAST(MachRegister r, unsigned int lowbit, unsigned int highbit ,uint32_t num_elements) : + Expression(r), m_Reg(r), m_Low(lowbit), m_High(highbit) , m_num_elements(num_elements) { } - RegisterAST::RegisterAST(MachRegister r) : - Expression(r), m_Reg(r), m_Low(0) + RegisterAST::RegisterAST(MachRegister r, uint32_t num_elements) : + Expression(r), m_Reg(r), m_Low(0), m_num_elements(num_elements) { m_High = r.size() * 8; } - RegisterAST::RegisterAST(MachRegister r, unsigned int lowbit, unsigned int highbit, Result_Type regType): - Expression(regType), m_Reg(r), m_Low(lowbit), m_High(highbit) + RegisterAST::RegisterAST(MachRegister r, unsigned int lowbit, unsigned int highbit, Result_Type regType, uint32_t num_elements): + Expression(regType), m_Reg(r), m_Low(lowbit), m_High(highbit), m_num_elements(num_elements) { } @@ -89,10 +91,10 @@ namespace Dyninst return m_Reg; } - std::string RegisterAST::format(Architecture arch, formatStyle f) const + std::string RegisterAST::format(Architecture arch, formatStyle) const { - if(arch == Arch_amdgpu_vega){ - return RegisterAST::format(f); + if(arch == Arch_amdgpu_gfx908 || arch == Arch_amdgpu_gfx90a || arch == Arch_amdgpu_gfx940){ + return AmdgpuFormatter::formatRegister(m_Reg,m_num_elements,m_Low,m_High); } return ArchSpecificFormatter::getFormatter(arch).formatRegister(m_Reg.name()); } @@ -100,15 +102,11 @@ namespace Dyninst std::string RegisterAST::format(formatStyle) const { std::string name = m_Reg.name(); - std::string::size_type substr = name.rfind(':'); + std::string::size_type substr = name.rfind("::"); if(substr != std::string::npos) { - name = name.substr(substr + 1, name.length()); + name = name.substr(substr + 2, name.length()); } - if ( m_Reg.size()*8 != m_High - m_Low){ - name += "["+to_string(m_Low)+":"+to_string(m_High)+"]"; - } - /* we have moved to AT&T syntax (lowercase registers) */ for(char &c : name) c = std::toupper(c); @@ -162,7 +160,7 @@ namespace Dyninst return false; } RegisterAST::Ptr RegisterAST::promote(const InstructionAST::Ptr regPtr) { - const RegisterAST::Ptr r = boost::dynamic_pointer_cast(regPtr); + const RegisterAST::Ptr r = dyncompat::dynamic_pointer_cast(regPtr); return RegisterAST::promote(r.get()); } MachRegister RegisterAST::getPromotedReg() const diff --git a/instructionAPI/src/Ternary.C b/instructionAPI/src/Ternary.C index 8c96b679bd..0996cb7cde 100644 --- a/instructionAPI/src/Ternary.C +++ b/instructionAPI/src/Ternary.C @@ -29,14 +29,12 @@ */ #include "Ternary.h" -#include "../../common/src/Singleton.h" #include #include #include #include "Visitor.h" #include "../../common/src/singleton_object_pool.h" #include "InstructionDecoder-power.h" -#include "dyn_regs.h" #include "ArchSpecificFormatters.h" using namespace std; diff --git a/instructionAPI/src/amdgpu_branchinsn_table.h b/instructionAPI/src/amdgpu_branchinsn_table.h index b6b9bcfd7a..2332acc93c 100644 --- a/instructionAPI/src/amdgpu_branchinsn_table.h +++ b/instructionAPI/src/amdgpu_branchinsn_table.h @@ -1,16 +1,48 @@ - case amdgpu_op_s_branch: - case amdgpu_op_s_cbranch_scc0: - case amdgpu_op_s_cbranch_scc1: - case amdgpu_op_s_cbranch_vccz: - case amdgpu_op_s_cbranch_vccnz: - case amdgpu_op_s_cbranch_execz: - case amdgpu_op_s_cbranch_execnz: - case amdgpu_op_s_cbranch_cdbgsys: - case amdgpu_op_s_cbranch_cdbguser: - case amdgpu_op_s_cbranch_cdbgsys_and_user: - case amdgpu_op_s_setpc_b64: - case amdgpu_op_s_swappc_b64: - case amdgpu_op_s_rfe_b64: - case amdgpu_op_s_cbranch_g_fork: - case amdgpu_op_s_cbranch_i_fork: - case amdgpu_op_s_call_b64: +case amdgpu_gfx908_op_S_BRANCH: +case amdgpu_gfx908_op_S_CBRANCH_SCC0: +case amdgpu_gfx908_op_S_CBRANCH_SCC1: +case amdgpu_gfx908_op_S_CBRANCH_VCCZ: +case amdgpu_gfx908_op_S_CBRANCH_VCCNZ: +case amdgpu_gfx908_op_S_CBRANCH_EXECZ: +case amdgpu_gfx908_op_S_CBRANCH_EXECNZ: +case amdgpu_gfx908_op_S_CBRANCH_CDBGSYS: +case amdgpu_gfx908_op_S_CBRANCH_CDBGUSER: +case amdgpu_gfx908_op_S_CBRANCH_CDBGSYS_AND_USER: +case amdgpu_gfx908_op_S_SETPC_B64: +case amdgpu_gfx908_op_S_SWAPPC_B64: +case amdgpu_gfx908_op_S_RFE_B64: +case amdgpu_gfx908_op_S_CBRANCH_G_FORK: +case amdgpu_gfx908_op_S_CBRANCH_I_FORK: +case amdgpu_gfx908_op_S_CALL_B64: +case amdgpu_gfx90a_op_S_BRANCH: +case amdgpu_gfx90a_op_S_CBRANCH_SCC0: +case amdgpu_gfx90a_op_S_CBRANCH_SCC1: +case amdgpu_gfx90a_op_S_CBRANCH_VCCZ: +case amdgpu_gfx90a_op_S_CBRANCH_VCCNZ: +case amdgpu_gfx90a_op_S_CBRANCH_EXECZ: +case amdgpu_gfx90a_op_S_CBRANCH_EXECNZ: +case amdgpu_gfx90a_op_S_CBRANCH_CDBGSYS: +case amdgpu_gfx90a_op_S_CBRANCH_CDBGUSER: +case amdgpu_gfx90a_op_S_CBRANCH_CDBGSYS_AND_USER: +case amdgpu_gfx90a_op_S_SETPC_B64: +case amdgpu_gfx90a_op_S_SWAPPC_B64: +case amdgpu_gfx90a_op_S_RFE_B64: +case amdgpu_gfx90a_op_S_CBRANCH_G_FORK: +case amdgpu_gfx90a_op_S_CBRANCH_I_FORK: +case amdgpu_gfx90a_op_S_CALL_B64: +case amdgpu_gfx940_op_S_BRANCH: +case amdgpu_gfx940_op_S_CBRANCH_SCC0: +case amdgpu_gfx940_op_S_CBRANCH_SCC1: +case amdgpu_gfx940_op_S_CBRANCH_VCCZ: +case amdgpu_gfx940_op_S_CBRANCH_VCCNZ: +case amdgpu_gfx940_op_S_CBRANCH_EXECZ: +case amdgpu_gfx940_op_S_CBRANCH_EXECNZ: +case amdgpu_gfx940_op_S_CBRANCH_CDBGSYS: +case amdgpu_gfx940_op_S_CBRANCH_CDBGUSER: +case amdgpu_gfx940_op_S_CBRANCH_CDBGSYS_AND_USER: +case amdgpu_gfx940_op_S_SETPC_B64: +case amdgpu_gfx940_op_S_SWAPPC_B64: +case amdgpu_gfx940_op_S_RFE_B64: +case amdgpu_gfx940_op_S_CBRANCH_G_FORK: +case amdgpu_gfx940_op_S_CBRANCH_I_FORK: +case amdgpu_gfx940_op_S_CALL_B64: diff --git a/instructionAPI/src/amdgpu_decoder_impl_vega.C b/instructionAPI/src/amdgpu_decoder_impl_vega.C deleted file mode 100644 index 6d376c115c..0000000000 --- a/instructionAPI/src/amdgpu_decoder_impl_vega.C +++ /dev/null @@ -1,484 +0,0 @@ -void InstructionDecoder_amdgpu_vega::decodeSOP2(){ - unsigned insn_size_ = 4; - layout_sop2 & layout = insn_layout.sop2; - layout.ssrc0 = longfield<0,7>(insn_long); - layout.ssrc1 = longfield<8,15>(insn_long); - layout.sdst = longfield<16,22>(insn_long); - layout.op = longfield<23,29>(insn_long); - const amdgpu_insn_entry &insn_entry = amdgpu_insn_entry::sop2_insn_table[layout.op]; - decodeOperands(insn_entry); - this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); - finalizeSOP2Operands(); -} -void InstructionDecoder_amdgpu_vega::decodeSOP1(){ - unsigned insn_size_ = 4; - layout_sop1 & layout = insn_layout.sop1; - layout.ssrc0 = longfield<0,7>(insn_long); - layout.op = longfield<8,15>(insn_long); - layout.sdst = longfield<16,22>(insn_long); - const amdgpu_insn_entry &insn_entry = amdgpu_insn_entry::sop1_insn_table[layout.op]; - decodeOperands(insn_entry); - this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); - finalizeSOP1Operands(); -} -void InstructionDecoder_amdgpu_vega::decodeSOPK(){ - unsigned insn_size_ = 4; - layout_sopk & layout = insn_layout.sopk; - layout.simm16 = longfield<0,15>(insn_long); - layout.sdst = longfield<16,22>(insn_long); - layout.op = longfield<23,27>(insn_long); - const amdgpu_insn_entry &insn_entry = amdgpu_insn_entry::sopk_insn_table[layout.op]; - decodeOperands(insn_entry); - this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); - finalizeSOPKOperands(); -} -void InstructionDecoder_amdgpu_vega::decodeSOPC(){ - unsigned insn_size_ = 4; - layout_sopc & layout = insn_layout.sopc; - layout.ssrc0 = longfield<0,7>(insn_long); - layout.ssrc1 = longfield<8,15>(insn_long); - layout.op = longfield<16,22>(insn_long); - const amdgpu_insn_entry &insn_entry = amdgpu_insn_entry::sopc_insn_table[layout.op]; - decodeOperands(insn_entry); - this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); - finalizeSOPCOperands(); -} -void InstructionDecoder_amdgpu_vega::decodeSOPP(){ - unsigned insn_size_ = 4; - layout_sopp & layout = insn_layout.sopp; - layout.simm16 = longfield<0,15>(insn_long); - layout.op = longfield<16,22>(insn_long); - const amdgpu_insn_entry &insn_entry = amdgpu_insn_entry::sopp_insn_table[layout.op]; - decodeOperands(insn_entry); - this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); - finalizeSOPPOperands(); -} -void InstructionDecoder_amdgpu_vega::decodeSMEM(){ - unsigned insn_size_ = 8; - layout_smem & layout = insn_layout.smem; - layout.sbase = longfield<0,5>(insn_long); - layout.sdata = longfield<6,12>(insn_long); - layout.soe = longfield<14,14>(insn_long); - layout.nv = longfield<15,15>(insn_long); - layout.glc = longfield<16,16>(insn_long); - layout.imm = longfield<17,17>(insn_long); - layout.op = longfield<18,25>(insn_long); - layout.offset = longfield<32,52>(insn_long); - layout.soffset = longfield<57,63>(insn_long); - const amdgpu_insn_entry &insn_entry = amdgpu_insn_entry::smem_insn_table[layout.op]; - decodeOperands(insn_entry); - this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); - finalizeSMEMOperands(); -} -void InstructionDecoder_amdgpu_vega::decodeVOP2(){ - unsigned insn_size_ = 4; - layout_vop2 & layout = insn_layout.vop2; - layout.src0 = longfield<0,8>(insn_long); - layout.vsrc1 = longfield<9,16>(insn_long); - layout.vdst = longfield<17,24>(insn_long); - layout.op = longfield<25,30>(insn_long); - if (layout.src0 == 249){ - vop_literal_layout_sdwa &vop_literal = layout.literal.sdwa; - vop_literal.src0 = longfield<32,39>(insn_long); - vop_literal.dst_sel = longfield<40,42>(insn_long); - vop_literal.dst_u = longfield<43,44>(insn_long); - vop_literal.clmp = longfield<45,45>(insn_long); - vop_literal.omod = longfield<46,47>(insn_long); - vop_literal.src0_sel = longfield<48,50>(insn_long); - vop_literal.src0_next = longfield<51,51>(insn_long); - vop_literal.src0_neg = longfield<52,52>(insn_long); - vop_literal.src0_abs = longfield<53,53>(insn_long); - vop_literal.s0 = longfield<55,55>(insn_long); - vop_literal.src1_sel = longfield<56,58>(insn_long); - vop_literal.src_sext = longfield<59,59>(insn_long); - vop_literal.src1_neg = longfield<60,60>(insn_long); - vop_literal.s1 = longfield<63,63>(insn_long); - } - if (layout.src0 == 250){ - vop_literal_layout_dpp &vop_literal = layout.literal.dpp; - vop_literal.src0 = longfield<32,39>(insn_long); - vop_literal.dpp_ctrl = longfield<40,48>(insn_long); - vop_literal.bc = longfield<51,51>(insn_long); - vop_literal.src0_neg = longfield<52,52>(insn_long); - vop_literal.src0_abs = longfield<53,53>(insn_long); - vop_literal.src1_neg = longfield<54,54>(insn_long); - vop_literal.src1_abs = longfield<55,55>(insn_long); - vop_literal.bank_mask = longfield<56,59>(insn_long); - vop_literal.row_mask = longfield<60,63>(insn_long); - } - const amdgpu_insn_entry &insn_entry = amdgpu_insn_entry::vop2_insn_table[layout.op]; - decodeOperands(insn_entry); - this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); - finalizeVOP2Operands(); -} -void InstructionDecoder_amdgpu_vega::decodeVOP1(){ - unsigned insn_size_ = 4; - layout_vop1 & layout = insn_layout.vop1; - layout.src0 = longfield<0,8>(insn_long); - layout.op = longfield<9,16>(insn_long); - layout.vdst = longfield<17,24>(insn_long); - if (layout.src0 == 249){ - vop_literal_layout_sdwa &vop_literal = layout.literal.sdwa; - vop_literal.src0 = longfield<32,39>(insn_long); - vop_literal.dst_sel = longfield<40,42>(insn_long); - vop_literal.dst_u = longfield<43,44>(insn_long); - vop_literal.clmp = longfield<45,45>(insn_long); - vop_literal.omod = longfield<46,47>(insn_long); - vop_literal.src0_sel = longfield<48,50>(insn_long); - vop_literal.src0_next = longfield<51,51>(insn_long); - vop_literal.src0_neg = longfield<52,52>(insn_long); - vop_literal.src0_abs = longfield<53,53>(insn_long); - vop_literal.s0 = longfield<55,55>(insn_long); - vop_literal.src1_sel = longfield<56,58>(insn_long); - vop_literal.src_sext = longfield<59,59>(insn_long); - vop_literal.src1_neg = longfield<60,60>(insn_long); - vop_literal.s1 = longfield<63,63>(insn_long); - } - if (layout.src0 == 250){ - vop_literal_layout_dpp &vop_literal = layout.literal.dpp; - vop_literal.src0 = longfield<32,39>(insn_long); - vop_literal.dpp_ctrl = longfield<40,48>(insn_long); - vop_literal.bc = longfield<51,51>(insn_long); - vop_literal.src0_neg = longfield<52,52>(insn_long); - vop_literal.src0_abs = longfield<53,53>(insn_long); - vop_literal.src1_neg = longfield<54,54>(insn_long); - vop_literal.src1_abs = longfield<55,55>(insn_long); - vop_literal.bank_mask = longfield<56,59>(insn_long); - vop_literal.row_mask = longfield<60,63>(insn_long); - } - const amdgpu_insn_entry &insn_entry = amdgpu_insn_entry::vop1_insn_table[layout.op]; - decodeOperands(insn_entry); - this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); - finalizeVOP1Operands(); -} -void InstructionDecoder_amdgpu_vega::decodeVOPC(){ - unsigned insn_size_ = 4; - layout_vopc & layout = insn_layout.vopc; - layout.src0 = longfield<0,8>(insn_long); - layout.vsrc1 = longfield<9,16>(insn_long); - layout.op = longfield<17,24>(insn_long); - if (layout.src0 == 249){ - vop_literal_layout_sdwab &vop_literal = layout.literal.sdwab; - vop_literal.src0 = longfield<32,39>(insn_long); - vop_literal.sdst = longfield<40,46>(insn_long); - vop_literal.sd = longfield<47,47>(insn_long); - vop_literal.src0_sel = longfield<48,50>(insn_long); - vop_literal.src0_next = longfield<51,51>(insn_long); - vop_literal.src0_neg = longfield<52,52>(insn_long); - vop_literal.src0_abs = longfield<53,53>(insn_long); - vop_literal.s0 = longfield<55,55>(insn_long); - vop_literal.src1_sel = longfield<56,58>(insn_long); - vop_literal.src_sext = longfield<59,59>(insn_long); - vop_literal.src1_neg = longfield<60,60>(insn_long); - vop_literal.s1 = longfield<63,63>(insn_long); - } - if (layout.src0 == 250){ - vop_literal_layout_dpp &vop_literal = layout.literal.dpp; - vop_literal.src0 = longfield<32,39>(insn_long); - vop_literal.dpp_ctrl = longfield<40,48>(insn_long); - vop_literal.bc = longfield<51,51>(insn_long); - vop_literal.src0_neg = longfield<52,52>(insn_long); - vop_literal.src0_abs = longfield<53,53>(insn_long); - vop_literal.src1_neg = longfield<54,54>(insn_long); - vop_literal.src1_abs = longfield<55,55>(insn_long); - vop_literal.bank_mask = longfield<56,59>(insn_long); - vop_literal.row_mask = longfield<60,63>(insn_long); - } - const amdgpu_insn_entry &insn_entry = amdgpu_insn_entry::vopc_insn_table[layout.op]; - decodeOperands(insn_entry); - this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); - finalizeVOPCOperands(); -} -void InstructionDecoder_amdgpu_vega::decodeVINTRP(){ - unsigned insn_size_ = 4; - layout_vintrp & layout = insn_layout.vintrp; - layout.vsrc = longfield<0,7>(insn_long); - layout.attr_chan = longfield<8,9>(insn_long); - layout.attr = longfield<10,15>(insn_long); - layout.op = longfield<16,17>(insn_long); - layout.vdst = longfield<18,25>(insn_long); - const amdgpu_insn_entry &insn_entry = amdgpu_insn_entry::vintrp_insn_table[layout.op]; - decodeOperands(insn_entry); - this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); - finalizeVINTRPOperands(); -} -void InstructionDecoder_amdgpu_vega::decodeDS(){ - unsigned insn_size_ = 8; - layout_ds & layout = insn_layout.ds; - layout.offset0 = longfield<0,7>(insn_long); - layout.offset1 = longfield<8,15>(insn_long); - layout.gds = longfield<16,16>(insn_long); - layout.op = longfield<17,24>(insn_long); - layout.addr = longfield<32,39>(insn_long); - layout.data0 = longfield<40,47>(insn_long); - layout.data1 = longfield<48,55>(insn_long); - layout.vdst = longfield<56,63>(insn_long); - const amdgpu_insn_entry &insn_entry = amdgpu_insn_entry::ds_insn_table[layout.op]; - decodeOperands(insn_entry); - this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); - finalizeDSOperands(); -} -void InstructionDecoder_amdgpu_vega::decodeMTBUF(){ - unsigned insn_size_ = 8; - layout_mtbuf & layout = insn_layout.mtbuf; - layout.offset = longfield<0,11>(insn_long); - layout.offen = longfield<12,12>(insn_long); - layout.idxen = longfield<13,13>(insn_long); - layout.glc = longfield<14,14>(insn_long); - layout.op = longfield<15,18>(insn_long); - layout.dfmt = longfield<19,22>(insn_long); - layout.nfmt = longfield<23,25>(insn_long); - layout.vaddr = longfield<32,39>(insn_long); - layout.vdata = longfield<40,47>(insn_long); - layout.srsrc = longfield<48,52>(insn_long); - layout.slc = longfield<54,54>(insn_long); - layout.tfe = longfield<55,55>(insn_long); - layout.soffset = longfield<56,63>(insn_long); - const amdgpu_insn_entry &insn_entry = amdgpu_insn_entry::mtbuf_insn_table[layout.op]; - decodeOperands(insn_entry); - this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); - finalizeMTBUFOperands(); -} -void InstructionDecoder_amdgpu_vega::decodeMUBUF(){ - unsigned insn_size_ = 8; - layout_mubuf & layout = insn_layout.mubuf; - layout.offset = longfield<0,11>(insn_long); - layout.offen = longfield<12,12>(insn_long); - layout.idxen = longfield<13,13>(insn_long); - layout.glc = longfield<14,14>(insn_long); - layout.lds = longfield<16,16>(insn_long); - layout.slc = longfield<17,17>(insn_long); - layout.op = longfield<18,24>(insn_long); - layout.vaddr = longfield<32,39>(insn_long); - layout.vdata = longfield<40,47>(insn_long); - layout.srsrc = longfield<48,52>(insn_long); - layout.tfe = longfield<55,55>(insn_long); - layout.soffset = longfield<56,63>(insn_long); - const amdgpu_insn_entry &insn_entry = amdgpu_insn_entry::mubuf_insn_table[layout.op]; - decodeOperands(insn_entry); - this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); - finalizeMUBUFOperands(); -} -void InstructionDecoder_amdgpu_vega::decodeVOP3AB(){ - unsigned insn_size_ = 8; - layout_vop3ab & layout = insn_layout.vop3ab; - layout.op = longfield<16,25>(insn_long); - const amdgpu_insn_entry &insn_entry = amdgpu_insn_entry::vop3ab_insn_table[layout.op]; - decodeOperands(insn_entry); - this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); - finalizeVOP3ABOperands(); -} -void InstructionDecoder_amdgpu_vega::decodeVOP3P(){ - unsigned insn_size_ = 8; - layout_vop3p & layout = insn_layout.vop3p; - layout.vdst = longfield<0,7>(insn_long); - layout.neg_hi = longfield<8,10>(insn_long); - layout.opsel = longfield<11,13>(insn_long); - layout.opsel_hi2 = longfield<14,14>(insn_long); - layout.clmp = longfield<15,15>(insn_long); - layout.op = longfield<16,22>(insn_long); - layout.src0 = longfield<32,40>(insn_long); - layout.src1 = longfield<41,49>(insn_long); - layout.src2 = longfield<50,58>(insn_long); - layout.opsel_hi = longfield<59,60>(insn_long); - layout.neg = longfield<61,63>(insn_long); - const amdgpu_insn_entry &insn_entry = amdgpu_insn_entry::vop3p_insn_table[layout.op]; - decodeOperands(insn_entry); - this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); - finalizeVOP3POperands(); -} -void InstructionDecoder_amdgpu_vega::decodeFLAT(){ - unsigned insn_size_ = 8; - layout_flat & layout = insn_layout.flat; - layout.offset = longfield<0,12>(insn_long); - layout.lds = longfield<13,13>(insn_long); - layout.seg = longfield<14,15>(insn_long); - layout.glc = longfield<16,16>(insn_long); - layout.slc = longfield<17,17>(insn_long); - layout.op = longfield<18,24>(insn_long); - layout.addr = longfield<32,39>(insn_long); - layout.data = longfield<40,47>(insn_long); - layout.saddr = longfield<48,54>(insn_long); - layout.nv = longfield<55,55>(insn_long); - layout.vdst = longfield<56,63>(insn_long); - const amdgpu_insn_entry &insn_entry = amdgpu_insn_entry::flat_insn_table[layout.op]; - decodeOperands(insn_entry); - this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); - finalizeFLATOperands(); -} -void InstructionDecoder_amdgpu_vega::mainDecode(InstructionDecoder::buffer &b){ - if(IS_SOP2(insn_long)){ - setUseImm<0,7,255>(b,4); - setUseImm<8,15,255>(b,4); - decodeSOP2(); - } - else if(IS_SOP1(insn_long)){ - setUseImm<0,7,255>(b,4); - decodeSOP1(); - } - else if(IS_SOPK(insn_long)){ - decodeSOPK(); - } - else if(IS_SOPC(insn_long)){ - decodeSOPC(); - } - else if(IS_SOPP(insn_long)){ - decodeSOPP(); - } - else if(IS_SMEM(insn_long)){ - decodeSMEM(); - } - else if(IS_VOP2(insn_long)){ - setUseImm<0,8,249>(b,4); - setUseImm<0,8,250>(b,4); - setUseImm<0,8,255>(b,4); - decodeVOP2(); - } - else if(IS_VOP1(insn_long)){ - setUseImm<0,8,249>(b,4); - setUseImm<0,8,250>(b,4); - setUseImm<0,8,255>(b,4); - decodeVOP1(); - } - else if(IS_VOPC(insn_long)){ - setUseImm<0,8,255>(b,4); - decodeVOPC(); - } - else if(IS_VINTRP(insn_long)){ - decodeVINTRP(); - } - else if(IS_DS(insn_long)){ - decodeDS(); - } - else if(IS_MTBUF(insn_long)){ - decodeMTBUF(); - } - else if(IS_MUBUF(insn_long)){ - decodeMUBUF(); - } - else if(IS_VOP3AB(insn_long)){ - decodeVOP3AB(); - } - else if(IS_VOP3P(insn_long)){ - decodeVOP3P(); - } - else if(IS_FLAT(insn_long)){ - decodeFLAT(); - } - else{ - assert(0); - } - -} -void InstructionDecoder_amdgpu_vega::mainDecodeOpcode(InstructionDecoder::buffer &b){ - if(IS_SOP2(insn_long)){ - unsigned insn_size_ = 4; - const amdgpu_insn_entry &insn_entry = amdgpu_insn_entry::sop2_insn_table[longfield<23,29>(insn_long)]; - setUseImm<0,7,255>(b,4); - setUseImm<8,15,255>(b,4); - this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); - instr_family = SOP2; - } - else if(IS_SOP1(insn_long)){ - unsigned insn_size_ = 4; - const amdgpu_insn_entry &insn_entry = amdgpu_insn_entry::sop1_insn_table[longfield<8,15>(insn_long)]; - setUseImm<0,7,255>(b,4); - this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); - instr_family = SOP1; - } - else if(IS_SOPK(insn_long)){ - unsigned insn_size_ = 4; - const amdgpu_insn_entry &insn_entry = amdgpu_insn_entry::sopk_insn_table[longfield<23,27>(insn_long)]; - this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); - instr_family = SOPK; - } - else if(IS_SOPC(insn_long)){ - unsigned insn_size_ = 4; - const amdgpu_insn_entry &insn_entry = amdgpu_insn_entry::sopc_insn_table[longfield<16,22>(insn_long)]; - this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); - instr_family = SOPC; - } - else if(IS_SOPP(insn_long)){ - unsigned insn_size_ = 4; - const amdgpu_insn_entry &insn_entry = amdgpu_insn_entry::sopp_insn_table[longfield<16,22>(insn_long)]; - this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); - instr_family = SOPP; - } - else if(IS_SMEM(insn_long)){ - unsigned insn_size_ = 8; - const amdgpu_insn_entry &insn_entry = amdgpu_insn_entry::smem_insn_table[longfield<18,25>(insn_long)]; - this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); - instr_family = SMEM; - } - else if(IS_VOP2(insn_long)){ - unsigned insn_size_ = 4; - const amdgpu_insn_entry &insn_entry = amdgpu_insn_entry::vop2_insn_table[longfield<25,30>(insn_long)]; - setUseImm<0,8,249>(b,4); - setUseImm<0,8,250>(b,4); - setUseImm<0,8,255>(b,4); - this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); - instr_family = VOP2; - } - else if(IS_VOP1(insn_long)){ - unsigned insn_size_ = 4; - const amdgpu_insn_entry &insn_entry = amdgpu_insn_entry::vop1_insn_table[longfield<9,16>(insn_long)]; - setUseImm<0,8,249>(b,4); - setUseImm<0,8,250>(b,4); - setUseImm<0,8,255>(b,4); - this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); - instr_family = VOP1; - } - else if(IS_VOPC(insn_long)){ - unsigned insn_size_ = 4; - const amdgpu_insn_entry &insn_entry = amdgpu_insn_entry::vopc_insn_table[longfield<17,24>(insn_long)]; - setUseImm<0,8,255>(b,4); - this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); - instr_family = VOPC; - } - else if(IS_VINTRP(insn_long)){ - unsigned insn_size_ = 4; - const amdgpu_insn_entry &insn_entry = amdgpu_insn_entry::vintrp_insn_table[longfield<16,17>(insn_long)]; - this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); - instr_family = VINTRP; - } - else if(IS_DS(insn_long)){ - unsigned insn_size_ = 8; - const amdgpu_insn_entry &insn_entry = amdgpu_insn_entry::ds_insn_table[longfield<17,24>(insn_long)]; - this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); - instr_family = DS; - } - else if(IS_MTBUF(insn_long)){ - unsigned insn_size_ = 8; - const amdgpu_insn_entry &insn_entry = amdgpu_insn_entry::mtbuf_insn_table[longfield<15,18>(insn_long)]; - this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); - instr_family = MTBUF; - } - else if(IS_MUBUF(insn_long)){ - unsigned insn_size_ = 8; - const amdgpu_insn_entry &insn_entry = amdgpu_insn_entry::mubuf_insn_table[longfield<18,24>(insn_long)]; - this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); - instr_family = MUBUF; - } - else if(IS_VOP3AB(insn_long)){ - unsigned insn_size_ = 8; - const amdgpu_insn_entry &insn_entry = amdgpu_insn_entry::vop3ab_insn_table[longfield<16,25>(insn_long)]; - this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); - instr_family = VOP3AB; - } - else if(IS_VOP3P(insn_long)){ - unsigned insn_size_ = 8; - const amdgpu_insn_entry &insn_entry = amdgpu_insn_entry::vop3p_insn_table[longfield<11,13>(insn_long)]; - this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); - instr_family = VOP3P; - } - else if(IS_FLAT(insn_long)){ - unsigned insn_size_ = 8; - const amdgpu_insn_entry &insn_entry = amdgpu_insn_entry::flat_insn_table[longfield<18,24>(insn_long)]; - this->insn_in_progress = makeInstruction(insn_entry.op,insn_entry.mnemonic,insn_size_+immLen,reinterpret_cast(&insn)); - instr_family = FLAT; - } - else{ - assert(0); - } - -} diff --git a/instructionAPI/src/amdgpu_decoder_impl_vega.h b/instructionAPI/src/amdgpu_decoder_impl_vega.h deleted file mode 100644 index 14e3c0a13f..0000000000 --- a/instructionAPI/src/amdgpu_decoder_impl_vega.h +++ /dev/null @@ -1,264 +0,0 @@ -enum InstructionFamily{ - SOP2 = 0, - SOP1 = 1, - SOPK = 2, - SOPC = 3, - SOPP = 4, - SMEM = 5, - VOP2 = 6, - VOP1 = 7, - VOPC = 8, - VINTRP = 9, - DS = 10, - MTBUF = 11, - MUBUF = 12, - VOP3AB = 13, - VOP3P = 14, - FLAT = 15 -}; -typedef void (InstructionDecoder_amdgpu_vega::*func_ptr)(void); -func_ptr decode_lookup_table [16] = { - (&InstructionDecoder_amdgpu_vega::decodeSOP2), - (&InstructionDecoder_amdgpu_vega::decodeSOP1), - (&InstructionDecoder_amdgpu_vega::decodeSOPK), - (&InstructionDecoder_amdgpu_vega::decodeSOPC), - (&InstructionDecoder_amdgpu_vega::decodeSOPP), - (&InstructionDecoder_amdgpu_vega::decodeSMEM), - (&InstructionDecoder_amdgpu_vega::decodeVOP2), - (&InstructionDecoder_amdgpu_vega::decodeVOP1), - (&InstructionDecoder_amdgpu_vega::decodeVOPC), - (&InstructionDecoder_amdgpu_vega::decodeVINTRP), - (&InstructionDecoder_amdgpu_vega::decodeDS), - (&InstructionDecoder_amdgpu_vega::decodeMTBUF), - (&InstructionDecoder_amdgpu_vega::decodeMUBUF), - (&InstructionDecoder_amdgpu_vega::decodeVOP3AB), - (&InstructionDecoder_amdgpu_vega::decodeVOP3P), - (&InstructionDecoder_amdgpu_vega::decodeFLAT) -}; -InstructionFamily instr_family; -typedef struct vop_literal_layout_sdwa{ - unsigned int src0 : 8; - unsigned int dst_sel : 3; - unsigned int dst_u : 2; - unsigned int clmp : 1; - unsigned int omod : 2; - unsigned int src0_sel : 3; - unsigned int src0_next : 1; - unsigned int src0_neg : 1; - unsigned int src0_abs : 1; - unsigned int s0 : 1; - unsigned int src1_sel : 3; - unsigned int src_sext : 1; - unsigned int src1_neg : 1; - unsigned int s1 : 1; -}vop_literal_layout_sdwa; -typedef struct vop_literal_layout_sdwab{ - unsigned int src0 : 8; - unsigned int sdst : 7; - unsigned int sd : 1; - unsigned int src0_sel : 3; - unsigned int src0_next : 1; - unsigned int src0_neg : 1; - unsigned int src0_abs : 1; - unsigned int s0 : 1; - unsigned int src1_sel : 3; - unsigned int src_sext : 1; - unsigned int src1_neg : 1; - unsigned int s1 : 1; -}vop_literal_layout_sdwab; -typedef struct vop_literal_layout_dpp{ - unsigned int src0 : 8; - unsigned int dpp_ctrl : 9; - unsigned int bc : 1; - unsigned int src0_neg : 1; - unsigned int src0_abs : 1; - unsigned int src1_neg : 1; - unsigned int src1_abs : 1; - unsigned int bank_mask : 4; - unsigned int row_mask : 4; -}vop_literal_layout_dpp; -typedef union vop_literal_layout { - vop_literal_layout_sdwa sdwa; - vop_literal_layout_sdwab sdwab; - vop_literal_layout_dpp dpp; -} vop_literal_layout; -#define IS_SOP2(I) ((longfield<30,31>(I) == 0x2)&&(longfield<28,29>(I) != 0x3)&&(longfield<23,29>(I) != 0x3d)&&(longfield<23,29>(I) != 0x3e)&&(longfield<23,29>(I) != 0x3f)) -#define IS_SOP1(I) ((longfield<23,31>(I) == 0x17d)) -#define IS_SOPK(I) ((longfield<30,31>(I) == 0x2)&&(longfield<28,31>(I) == 0xb)&&(longfield<23,27>(I) != 0x1d)&&(longfield<23,27>(I) != 0x1e)&&(longfield<23,27>(I) != 0x1f)) -#define IS_SOPC(I) ((longfield<23,31>(I) == 0x17e)) -#define IS_SOPP(I) ((longfield<23,31>(I) == 0x17f)) -#define IS_SMEM(I) ((longfield<26,31>(I) == 0x30)) -#define IS_VOP2(I) ((longfield<31,31>(I) == 0x0)&&(longfield<25,30>(I) != 0x3e)&&(longfield<25,30>(I) != 0x3f)) -#define IS_VOP1(I) ((longfield<25,31>(I) == 0x3f)) -#define IS_VOPC(I) ((longfield<25,31>(I) == 0x3e)) -#define IS_VINTRP(I) ((longfield<26,31>(I) == 0x35)) -#define IS_DS(I) ((longfield<26,31>(I) == 0x36)) -#define IS_MTBUF(I) ((longfield<26,31>(I) == 0x3a)) -#define IS_MUBUF(I) ((longfield<26,31>(I) == 0x38)) -#define IS_VOP3AB(I) ((longfield<26,31>(I) == 0x34)&&(longfield<23,25>(I) != 0x7)) -#define IS_VOP3P(I) ((longfield<23,31>(I) == 0x1a7)) -#define IS_FLAT(I) ((longfield<26,31>(I) == 0x37)) -typedef struct layout_sop2{ - unsigned int op : 7; - unsigned int sdst : 7; - unsigned int ssrc1 : 8; - unsigned int ssrc0 : 8; -}layout_sop2; -typedef struct layout_sop1{ - unsigned int sdst : 7; - unsigned int op : 8; - unsigned int ssrc0 : 8; -}layout_sop1; -typedef struct layout_sopk{ - unsigned int op : 5; - unsigned int sdst : 7; - int simm16 : 16; -}layout_sopk; -typedef struct layout_sopc{ - unsigned int ssrc0 : 8; - unsigned int ssrc1 : 8; - unsigned int op : 7; -}layout_sopc; -typedef struct layout_sopp{ - int simm16 : 16; - unsigned int op : 7; -}layout_sopp; -typedef struct layout_smem{ - unsigned int soffset : 7; - unsigned int offset : 21; - unsigned int op : 8; - unsigned int imm : 1; - unsigned int glc : 1; - unsigned int nv : 1; - unsigned int soe : 1; - unsigned int sdata : 7; - unsigned int sbase : 6; -}layout_smem; -typedef struct layout_vop2{ - unsigned int op : 6; - unsigned int vdst : 8; - unsigned int vsrc1 : 8; - unsigned int src0 : 9; - vop_literal_layout literal; -}layout_vop2; -typedef struct layout_vop1{ - unsigned int src0 : 9; - unsigned int op : 8; - unsigned int vdst : 8; - vop_literal_layout literal; -}layout_vop1; -typedef struct layout_vopc{ - unsigned int src0 : 9; - unsigned int vsrc1 : 8; - unsigned int op : 8; - vop_literal_layout literal; -}layout_vopc; -typedef struct layout_vintrp{ - unsigned int vsrc : 8; - unsigned int attr_chan : 2; - unsigned int attr : 6; - unsigned int op : 2; - unsigned int vdst : 8; -}layout_vintrp; -typedef struct layout_ds{ - unsigned int offset0 : 8; - unsigned int offset1 : 8; - unsigned int gds : 1; - unsigned int op : 8; - unsigned int addr : 8; - unsigned int data0 : 8; - unsigned int data1 : 8; - unsigned int vdst : 8; -}layout_ds; -typedef struct layout_mtbuf{ - unsigned int offset : 12; - unsigned int offen : 1; - unsigned int idxen : 1; - unsigned int glc : 1; - unsigned int op : 4; - unsigned int dfmt : 4; - unsigned int nfmt : 3; - unsigned int vaddr : 8; - unsigned int vdata : 8; - unsigned int srsrc : 5; - unsigned int slc : 1; - unsigned int tfe : 1; - unsigned int soffset : 8; -}layout_mtbuf; -typedef struct layout_mubuf{ - unsigned int offset : 12; - unsigned int offen : 1; - unsigned int idxen : 1; - unsigned int glc : 1; - unsigned int lds : 1; - unsigned int slc : 1; - unsigned int op : 7; - unsigned int vaddr : 8; - unsigned int vdata : 8; - unsigned int srsrc : 5; - unsigned int tfe : 1; - unsigned int soffset : 8; -}layout_mubuf; -typedef struct layout_vop3ab{ - unsigned int op : 10; -}layout_vop3ab; -typedef struct layout_vop3p{ - unsigned int vdst : 8; - unsigned int neg_hi : 3; - unsigned int opsel : 3; - unsigned int opsel_hi2 : 1; - unsigned int clmp : 1; - unsigned int op : 7; - unsigned int src0 : 9; - unsigned int src1 : 9; - unsigned int src2 : 9; - unsigned int opsel_hi : 2; - unsigned int neg : 3; -}layout_vop3p; -typedef struct layout_flat{ - unsigned int offset : 13; - unsigned int lds : 1; - unsigned int seg : 2; - unsigned int glc : 1; - unsigned int slc : 1; - unsigned int op : 7; - unsigned int addr : 8; - unsigned int data : 8; - unsigned int saddr : 7; - unsigned int nv : 1; - unsigned int vdst : 8; -}layout_flat; -union insn_layouts{ - layout_sop2 sop2; - layout_sop1 sop1; - layout_sopk sopk; - layout_sopc sopc; - layout_sopp sopp; - layout_smem smem; - layout_vop2 vop2; - layout_vop1 vop1; - layout_vopc vopc; - layout_vintrp vintrp; - layout_ds ds; - layout_mtbuf mtbuf; - layout_mubuf mubuf; - layout_vop3ab vop3ab; - layout_vop3p vop3p; - layout_flat flat; -}insn_layout; -void decodeSOP2(); -void decodeSOP1(); -void decodeSOPK(); -void decodeSOPC(); -void decodeSOPP(); -void decodeSMEM(); -void decodeVOP2(); -void decodeVOP1(); -void decodeVOPC(); -void decodeVINTRP(); -void decodeDS(); -void decodeMTBUF(); -void decodeMUBUF(); -void decodeVOP3AB(); -void decodeVOP3P(); -void decodeFLAT(); diff --git a/instructionAPI/src/amdgpu_insn_entry.h b/instructionAPI/src/amdgpu_insn_entry.h deleted file mode 100644 index 2f13df5b88..0000000000 --- a/instructionAPI/src/amdgpu_insn_entry.h +++ /dev/null @@ -1,24 +0,0 @@ -struct amdgpu_insn_entry { - entryID op; - const char *mnemonic; - std::size_t operandCnt; - const operandFactory *operands; - static const amdgpu_insn_table main_insn_table; - static const operandFactory operandTable[]; - static const amdgpu_insn_table sop2_insn_table; - static const amdgpu_insn_table sop1_insn_table; - static const amdgpu_insn_table sopk_insn_table; - static const amdgpu_insn_table sopc_insn_table; - static const amdgpu_insn_table sopp_insn_table; - static const amdgpu_insn_table smem_insn_table; - static const amdgpu_insn_table vop2_insn_table; - static const amdgpu_insn_table vop1_insn_table; - static const amdgpu_insn_table vopc_insn_table; - static const amdgpu_insn_table vintrp_insn_table; - static const amdgpu_insn_table ds_insn_table; - static const amdgpu_insn_table mtbuf_insn_table; - static const amdgpu_insn_table mubuf_insn_table; - static const amdgpu_insn_table vop3ab_insn_table; - static const amdgpu_insn_table vop3p_insn_table; - static const amdgpu_insn_table flat_insn_table; -}; diff --git a/instructionAPI/src/amdgpu_opcode_tables.C b/instructionAPI/src/amdgpu_opcode_tables.C deleted file mode 100644 index ae76753077..0000000000 --- a/instructionAPI/src/amdgpu_opcode_tables.C +++ /dev/null @@ -1,2056 +0,0 @@ -#define fn(...) (&InstructionDecoder_amdgpu_vega::__VA_ARGS__) -const operandFactory amdgpu_insn_entry::operandTable[] = { - fn(NOTHING), - fn(setSMEM),fn(setLoad<1>),//s_load_dword - fn(setSMEM),fn(setLoad<2>),//s_load_dwordx2 - fn(setSMEM),fn(setLoad<4>),//s_load_dwordx4 - fn(setSMEM),fn(setLoad<8>),//s_load_dwordx8 - fn(setSMEM),fn(setLoad<16>),//s_load_dwordx16 - fn(setSMEM),fn(setLoad<1>),//s_buffer_load_dword - fn(setSMEM),fn(setLoad<2>),//s_buffer_load_dwordx2 - fn(setSMEM),fn(setLoad<4>),//s_buffer_load_dwordx4 - fn(setSMEM),fn(setLoad<8>),//s_buffer_load_dwordx8 - fn(setSMEM),fn(setLoad<16>),//s_buffer_load_dwordx16 - fn(setSMEM),fn(setLoad<1>),//buffer_load_format_x - fn(setSMEM),fn(setLoad<2>),//buffer_load_format_xy - fn(setSMEM),fn(setLoad<3>),//buffer_load_format_xyz - fn(setSMEM),fn(setLoad<4>),//buffer_load_format_xyzw - fn(setSMEM),fn(setStore<1>),//buffer_store_format_x - fn(setSMEM),fn(setStore<2>),//buffer_store_format_xy - fn(setSMEM),fn(setStore<3>),//buffer_store_format_xyz - fn(setSMEM),fn(setStore<4>),//buffer_store_format_xyzw - fn(setSMEM),fn(setLoad<1>),//tbuffer_load_format_x - fn(setSMEM),fn(setLoad<2>),//tbuffer_load_format_xy - fn(setSMEM),fn(setLoad<3>),//tbuffer_load_format_xyz - fn(setSMEM),fn(setLoad<4>),//tbuffer_load_format_xyzw - fn(setSMEM),fn(setStore<1>),//tbuffer_store_format_x - fn(setSMEM),fn(setStore<2>),//tbuffer_store_format_xy - fn(setSMEM),fn(setStore<3>),//tbuffer_store_format_xyz - fn(setSMEM),fn(setStore<4>),//tbuffer_store_format_xyzw - fn(setBranch),//s_branch - fn(setBranch),fn(setConditionalBranch),//s_cbranch_scc0 - fn(setBranch),fn(setConditionalBranch),//s_cbranch_scc1 - fn(setBranch),fn(setConditionalBranch),//s_cbranch_vccz - fn(setBranch),fn(setConditionalBranch),//s_cbranch_vccnz - fn(setBranch),fn(setConditionalBranch),//s_cbranch_execz - fn(setBranch),fn(setConditionalBranch),//s_cbranch_execnz - fn(setBranch),fn(setConditionalBranch),//s_cbranch_cdbgsys - fn(setBranch),fn(setConditionalBranch),//s_cbranch_cdbguser - fn(setBranch),fn(setConditionalBranch),//s_cbranch_cdbgsys_and_user - fn(setBranch),fn(setCall),//s_call_b64 - fn(setBranch),fn(setModifyPC),//s_setpc_b64 - fn(setBranch),fn(setModifyPC),//s_swappc_b64 -}; -const amdgpu_insn_table amdgpu_insn_entry::sop2_insn_table = { - {amdgpu_op_s_add_u32,"s_add_u32",0,&operandTable[0]} ,//0 - {amdgpu_op_s_sub_u32,"s_sub_u32",0,&operandTable[0]} ,//1 - {amdgpu_op_s_add_i32,"s_add_i32",0,&operandTable[0]} ,//2 - {amdgpu_op_s_sub_i32,"s_sub_i32",0,&operandTable[0]} ,//3 - {amdgpu_op_s_addc_u32,"s_addc_u32",0,&operandTable[0]} ,//4 - {amdgpu_op_s_subb_u32,"s_subb_u32",0,&operandTable[0]} ,//5 - {amdgpu_op_s_min_i32,"s_min_i32",0,&operandTable[0]} ,//6 - {amdgpu_op_s_min_u32,"s_min_u32",0,&operandTable[0]} ,//7 - {amdgpu_op_s_max_i32,"s_max_i32",0,&operandTable[0]} ,//8 - {amdgpu_op_s_max_u32,"s_max_u32",0,&operandTable[0]} ,//9 - {amdgpu_op_s_cslect_b32,"s_cslect_b32",0,&operandTable[0]} ,//10 - {amdgpu_op_s_cslect_b64,"s_cslect_b64",0,&operandTable[0]} ,//11 - {amdgpu_op_s_and_b32,"s_and_b32",0,&operandTable[0]} ,//12 - {amdgpu_op_s_and_b64,"s_and_b64",0,&operandTable[0]} ,//13 - {amdgpu_op_s_or_b32,"s_or_b32",0,&operandTable[0]} ,//14 - {amdgpu_op_s_or_b64,"s_or_b64",0,&operandTable[0]} ,//15 - {amdgpu_op_s_xor_b32,"s_xor_b32",0,&operandTable[0]} ,//16 - {amdgpu_op_s_xor_b64,"s_xor_b64",0,&operandTable[0]} ,//17 - {amdgpu_op_s_andn2_b32,"s_andn2_b32",0,&operandTable[0]} ,//18 - {amdgpu_op_s_andn2_b64,"s_andn2_b64",0,&operandTable[0]} ,//19 - {amdgpu_op_s_orn2_b32,"s_orn2_b32",0,&operandTable[0]} ,//20 - {amdgpu_op_s_orn2_b64,"s_orn2_b64",0,&operandTable[0]} ,//21 - {amdgpu_op_s_nand_b32,"s_nand_b32",0,&operandTable[0]} ,//22 - {amdgpu_op_s_nand_b64,"s_nand_b64",0,&operandTable[0]} ,//23 - {amdgpu_op_s_nor_b32,"s_nor_b32",0,&operandTable[0]} ,//24 - {amdgpu_op_s_nor_b64,"s_nor_b64",0,&operandTable[0]} ,//25 - {amdgpu_op_s_xnor_b32,"s_xnor_b32",0,&operandTable[0]} ,//26 - {amdgpu_op_s_xnor_b64,"s_xnor_b64",0,&operandTable[0]} ,//27 - {amdgpu_op_s_lshl_b32,"s_lshl_b32",0,&operandTable[0]} ,//28 - {amdgpu_op_s_lshl_b64,"s_lshl_b64",0,&operandTable[0]} ,//29 - {amdgpu_op_s_lshr_b32,"s_lshr_b32",0,&operandTable[0]} ,//30 - {amdgpu_op_s_lshr_b64,"s_lshr_b64",0,&operandTable[0]} ,//31 - {amdgpu_op_s_ashr_i32,"s_ashr_i32",0,&operandTable[0]} ,//32 - {amdgpu_op_s_ashr_i64,"s_ashr_i64",0,&operandTable[0]} ,//33 - {amdgpu_op_s_bfm_b32,"s_bfm_b32",0,&operandTable[0]} ,//34 - {amdgpu_op_s_bfm_b64,"s_bfm_b64",0,&operandTable[0]} ,//35 - {amdgpu_op_s_mul_i32,"s_mul_i32",0,&operandTable[0]} ,//36 - {amdgpu_op_s_bfe_u32,"s_bfe_u32",0,&operandTable[0]} ,//37 - {amdgpu_op_s_bfe_i32,"s_bfe_i32",0,&operandTable[0]} ,//38 - {amdgpu_op_s_bfe_u64,"s_bfe_u64",0,&operandTable[0]} ,//39 - {amdgpu_op_s_bfe_i64,"s_bfe_i64",0,&operandTable[0]} ,//40 - {amdgpu_op_s_cbranch_g_fork,"s_cbranch_g_fork",0,&operandTable[0]} ,//41 - {amdgpu_op_s_absdiff_i32,"s_absdiff_i32",0,&operandTable[0]} ,//42 - {amdgpu_op_s_rfe_restore_b64,"s_rfe_restore_b64",0,&operandTable[0]} ,//43 - {amdgpu_op_s_mul_hi_u32,"s_mul_hi_u32",0,&operandTable[0]} ,//44 - {amdgpu_op_s_mul_hi_i32,"s_mul_hi_i32",0,&operandTable[0]} ,//45 - {amdgpu_op_s_lshl1_add_u32,"s_lshl1_add_u32",0,&operandTable[0]} ,//46 - {amdgpu_op_s_lshsl2_add_u32,"s_lshsl2_add_u32",0,&operandTable[0]} ,//47 - {amdgpu_op_s_lshl3_add_u32,"s_lshl3_add_u32",0,&operandTable[0]} ,//48 - {amdgpu_op_s_lshl4_add_u32,"s_lshl4_add_u32",0,&operandTable[0]} ,//49 - {amdgpu_op_s_pack_ll_b32_b16,"s_pack_ll_b32_b16",0,&operandTable[0]} ,//50 - {amdgpu_op_s_pack_lh_b32_b16,"s_pack_lh_b32_b16",0,&operandTable[0]} ,//51 - {amdgpu_op_s_pack_hh_b32_B16,"s_pack_hh_b32_B16",0,&operandTable[0]} ,//52 -}; // end s_pack_hh_b32_B16_insn_table - -const amdgpu_insn_table amdgpu_insn_entry::sop1_insn_table = { - {amdgpu_op_s_mov_b32,"s_mov_b32",0,&operandTable[0]} ,//0 - {amdgpu_op_s_mov_b64,"s_mov_b64",0,&operandTable[0]} ,//1 - {amdgpu_op_s_cmov_b32,"s_cmov_b32",0,&operandTable[0]} ,//2 - {amdgpu_op_s_cmov_b64,"s_cmov_b64",0,&operandTable[0]} ,//3 - {amdgpu_op_s_not_b32,"s_not_b32",0,&operandTable[0]} ,//4 - {amdgpu_op_s_not_b64,"s_not_b64",0,&operandTable[0]} ,//5 - {amdgpu_op_s_wqm_b32,"s_wqm_b32",0,&operandTable[0]} ,//6 - {amdgpu_op_s_wqm_b64,"s_wqm_b64",0,&operandTable[0]} ,//7 - {amdgpu_op_s_brev_b32,"s_brev_b32",0,&operandTable[0]} ,//8 - {amdgpu_op_s_brev_b64,"s_brev_b64",0,&operandTable[0]} ,//9 - {amdgpu_op_s_bcnt0_i32_b32,"s_bcnt0_i32_b32",0,&operandTable[0]} ,//10 - {amdgpu_op_s_bcnt0_i32_b64,"s_bcnt0_i32_b64",0,&operandTable[0]} ,//11 - {amdgpu_op_s_bcnt1_i32_b32,"s_bcnt1_i32_b32",0,&operandTable[0]} ,//12 - {amdgpu_op_s_bcnt1_i32_b64,"s_bcnt1_i32_b64",0,&operandTable[0]} ,//13 - {amdgpu_op_s_ff0_i32_b32,"s_ff0_i32_b32",0,&operandTable[0]} ,//14 - {amdgpu_op_s_ff0_i32_b64,"s_ff0_i32_b64",0,&operandTable[0]} ,//15 - {amdgpu_op_s_ff1_i32_b32,"s_ff1_i32_b32",0,&operandTable[0]} ,//16 - {amdgpu_op_s_ff1_i32_b64,"s_ff1_i32_b64",0,&operandTable[0]} ,//17 - {amdgpu_op_s_flbit_i32_b32,"s_flbit_i32_b32",0,&operandTable[0]} ,//18 - {amdgpu_op_s_flbit_i32_b64,"s_flbit_i32_b64",0,&operandTable[0]} ,//19 - {amdgpu_op_s_fltbit_i32,"s_fltbit_i32",0,&operandTable[0]} ,//20 - {amdgpu_op_s_fltbit_i32_i64,"s_fltbit_i32_i64",0,&operandTable[0]} ,//21 - {amdgpu_op_s_sext_i32_i8,"s_sext_i32_i8",0,&operandTable[0]} ,//22 - {amdgpu_op_s_sext_i32_i16,"s_sext_i32_i16",0,&operandTable[0]} ,//23 - {amdgpu_op_s_bitset0_b32,"s_bitset0_b32",0,&operandTable[0]} ,//24 - {amdgpu_op_s_bitset0_b64,"s_bitset0_b64",0,&operandTable[0]} ,//25 - {amdgpu_op_s_bitset1_b32,"s_bitset1_b32",0,&operandTable[0]} ,//26 - {amdgpu_op_s_bitset1_b64,"s_bitset1_b64",0,&operandTable[0]} ,//27 - {amdgpu_op_s_getpc_b64,"s_getpc_b64",0,&operandTable[0]} ,//28 - {amdgpu_op_s_setpc_b64,"s_setpc_b64",2,&operandTable[74]} ,//29 - {amdgpu_op_s_swappc_b64,"s_swappc_b64",2,&operandTable[76]} ,//30 - {amdgpu_op_s_rfe_b64,"s_rfe_b64",0,&operandTable[0]} ,//31 - {amdgpu_op_s_and_saveexec_b64,"s_and_saveexec_b64",0,&operandTable[0]} ,//32 - {amdgpu_op_s_or_savexec_b64,"s_or_savexec_b64",0,&operandTable[0]} ,//33 - {amdgpu_op_s_xor_savexec_b64,"s_xor_savexec_b64",0,&operandTable[0]} ,//34 - {amdgpu_op_s_andn2_savexec_b64,"s_andn2_savexec_b64",0,&operandTable[0]} ,//35 - {amdgpu_op_s_orn2_savexec_b64,"s_orn2_savexec_b64",0,&operandTable[0]} ,//36 - {amdgpu_op_s_nand_savexec_b64,"s_nand_savexec_b64",0,&operandTable[0]} ,//37 - {amdgpu_op_s_nor_savexec_b64,"s_nor_savexec_b64",0,&operandTable[0]} ,//38 - {amdgpu_op_s_xnor_savexec_b64,"s_xnor_savexec_b64",0,&operandTable[0]} ,//39 - {amdgpu_op_s_quadmask_b32,"s_quadmask_b32",0,&operandTable[0]} ,//40 - {amdgpu_op_s_quadmask_b64,"s_quadmask_b64",0,&operandTable[0]} ,//41 - {amdgpu_op_s_movrels_b32,"s_movrels_b32",0,&operandTable[0]} ,//42 - {amdgpu_op_s_movrels_b64,"s_movrels_b64",0,&operandTable[0]} ,//43 - {amdgpu_op_s_movreld_b32,"s_movreld_b32",0,&operandTable[0]} ,//44 - {amdgpu_op_s_movreld_b64,"s_movreld_b64",0,&operandTable[0]} ,//45 - {amdgpu_op_s_cbranch_join,"s_cbranch_join",0,&operandTable[0]} ,//46 - {amdgpu_op_s_invalid_1,"s_invalid_1",0,&operandTable[0]} ,//47 - {amdgpu_op_s_abs_i32,"s_abs_i32",0,&operandTable[0]} ,//48 - {amdgpu_op_s_invalid_2,"s_invalid_2",0,&operandTable[0]} ,//49 - {amdgpu_op_s_set_gpr_idx_idx,"s_set_gpr_idx_idx",0,&operandTable[0]} ,//50 - {amdgpu_op_s_andn1_saveexec_b64,"s_andn1_saveexec_b64",0,&operandTable[0]} ,//51 - {amdgpu_op_s_orn1_saveexec_b64,"s_orn1_saveexec_b64",0,&operandTable[0]} ,//52 - {amdgpu_op_s_andn1_wrexec_b64,"s_andn1_wrexec_b64",0,&operandTable[0]} ,//53 - {amdgpu_op_s_andn2_wrexec_b64,"s_andn2_wrexec_b64",0,&operandTable[0]} ,//54 - {amdgpu_op_s_bitreplicate_b64_b32,"s_bitreplicate_b64_b32",0,&operandTable[0]} ,//55 -}; // end s_bitreplicate_b64_b32_insn_table - -const amdgpu_insn_table amdgpu_insn_entry::sopk_insn_table = { - {amdgpu_op_s_movk_i32,"s_movk_i32",0,&operandTable[0]} ,//0 - {amdgpu_op_s_cmovk_i32,"s_cmovk_i32",0,&operandTable[0]} ,//1 - {amdgpu_op_s_cmpk_eq_i32,"s_cmpk_eq_i32",0,&operandTable[0]} ,//2 - {amdgpu_op_s_cmpk_lg_i32,"s_cmpk_lg_i32",0,&operandTable[0]} ,//3 - {amdgpu_op_s_cmpk_gt_i32,"s_cmpk_gt_i32",0,&operandTable[0]} ,//4 - {amdgpu_op_s_cmpk_ge_i32,"s_cmpk_ge_i32",0,&operandTable[0]} ,//5 - {amdgpu_op_s_cmpk_lt_i32,"s_cmpk_lt_i32",0,&operandTable[0]} ,//6 - {amdgpu_op_s_cmpk_le_i32,"s_cmpk_le_i32",0,&operandTable[0]} ,//7 - {amdgpu_op_s_cmpk_eq_u32,"s_cmpk_eq_u32",0,&operandTable[0]} ,//8 - {amdgpu_op_s_cmpk_lg_u32,"s_cmpk_lg_u32",0,&operandTable[0]} ,//9 - {amdgpu_op_s_cmpk_gt_u32,"s_cmpk_gt_u32",0,&operandTable[0]} ,//10 - {amdgpu_op_s_cmpk_ge_u32,"s_cmpk_ge_u32",0,&operandTable[0]} ,//11 - {amdgpu_op_s_cmpk_lt_u32,"s_cmpk_lt_u32",0,&operandTable[0]} ,//12 - {amdgpu_op_s_cmpk_le_u32,"s_cmpk_le_u32",0,&operandTable[0]} ,//13 - {amdgpu_op_s_addk_i32,"s_addk_i32",0,&operandTable[0]} ,//14 - {amdgpu_op_s_mulk_i32,"s_mulk_i32",0,&operandTable[0]} ,//15 - {amdgpu_op_s_cbranch_i_fork,"s_cbranch_i_fork",0,&operandTable[0]} ,//16 - {amdgpu_op_s_getreg_b32,"s_getreg_b32",0,&operandTable[0]} ,//17 - {amdgpu_op_s_setreg_b32,"s_setreg_b32",0,&operandTable[0]} ,//18 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//19 - {amdgpu_op_s_setreg_imm32_b32,"s_setreg_imm32_b32",0,&operandTable[0]} ,//20 - {amdgpu_op_s_call_b64,"s_call_b64",2,&operandTable[72]} ,//21 -}; // end s_call_b64_insn_table - -const amdgpu_insn_table amdgpu_insn_entry::sopc_insn_table = { - {amdgpu_op_s_cmp_ge_eq_i32,"s_cmp_ge_eq_i32",0,&operandTable[0]} ,//0 - {amdgpu_op_s_cmp_ge_eq_u32,"s_cmp_ge_eq_u32",0,&operandTable[0]} ,//1 - {amdgpu_op_s_cmp_lg_i32,"s_cmp_lg_i32",0,&operandTable[0]} ,//2 - {amdgpu_op_s_cmp_lg_u32,"s_cmp_lg_u32",0,&operandTable[0]} ,//3 - {amdgpu_op_s_cmp_gt_i32,"s_cmp_gt_i32",0,&operandTable[0]} ,//4 - {amdgpu_op_s_cmp_gt_u32,"s_cmp_gt_u32",0,&operandTable[0]} ,//5 - {amdgpu_op_s_cmp_ge_i32,"s_cmp_ge_i32",0,&operandTable[0]} ,//6 - {amdgpu_op_s_cmp_ge_u32,"s_cmp_ge_u32",0,&operandTable[0]} ,//7 - {amdgpu_op_s_cmp_lt_i32,"s_cmp_lt_i32",0,&operandTable[0]} ,//8 - {amdgpu_op_s_cmp_lt_u32,"s_cmp_lt_u32",0,&operandTable[0]} ,//9 - {amdgpu_op_s_cmp_le_i32,"s_cmp_le_i32",0,&operandTable[0]} ,//10 - {amdgpu_op_s_cmp_le_u32,"s_cmp_le_u32",0,&operandTable[0]} ,//11 - {amdgpu_op_s_bitcmp0_b32,"s_bitcmp0_b32",0,&operandTable[0]} ,//12 - {amdgpu_op_s_bitcmp1_b32,"s_bitcmp1_b32",0,&operandTable[0]} ,//13 - {amdgpu_op_s_bitcmp0_b64,"s_bitcmp0_b64",0,&operandTable[0]} ,//14 - {amdgpu_op_s_bitcmp1_b64,"s_bitcmp1_b64",0,&operandTable[0]} ,//15 - {amdgpu_op_s_setvkip,"s_setvkip",0,&operandTable[0]} ,//16 - {amdgpu_op_s_set_gpr_idx_on,"s_set_gpr_idx_on",0,&operandTable[0]} ,//17 - {amdgpu_op_s_cmp_eq_u64,"s_cmp_eq_u64",0,&operandTable[0]} ,//18 - {amdgpu_op_s_cmp_lg_u64,"s_cmp_lg_u64",0,&operandTable[0]} ,//19 -}; // end s_cmp_lg_u64_insn_table - -const amdgpu_insn_table amdgpu_insn_entry::sopp_insn_table = { - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//0 - {amdgpu_op_s_endpgm,"s_endpgm",0,&operandTable[0]} ,//1 - {amdgpu_op_s_branch,"s_branch",1,&operandTable[53]} ,//2 - {amdgpu_op_s_wakeup,"s_wakeup",0,&operandTable[0]} ,//3 - {amdgpu_op_s_cbranch_scc0,"s_cbranch_scc0",2,&operandTable[54]} ,//4 - {amdgpu_op_s_cbranch_scc1,"s_cbranch_scc1",2,&operandTable[56]} ,//5 - {amdgpu_op_s_cbranch_vccz,"s_cbranch_vccz",2,&operandTable[58]} ,//6 - {amdgpu_op_s_cbranch_vccnz,"s_cbranch_vccnz",2,&operandTable[60]} ,//7 - {amdgpu_op_s_cbranch_execz,"s_cbranch_execz",2,&operandTable[62]} ,//8 - {amdgpu_op_s_cbranch_execnz,"s_cbranch_execnz",2,&operandTable[64]} ,//9 - {amdgpu_op_s_barrier,"s_barrier",0,&operandTable[0]} ,//10 - {amdgpu_op_s_setkill,"s_setkill",0,&operandTable[0]} ,//11 - {amdgpu_op_s_waitcnt,"s_waitcnt",0,&operandTable[0]} ,//12 - {amdgpu_op_s_sethalt,"s_sethalt",0,&operandTable[0]} ,//13 - {amdgpu_op_s_sleep,"s_sleep",0,&operandTable[0]} ,//14 - {amdgpu_op_s_setprio,"s_setprio",0,&operandTable[0]} ,//15 - {amdgpu_op_s_sendmsg,"s_sendmsg",0,&operandTable[0]} ,//16 - {amdgpu_op_s_sendmsghalt,"s_sendmsghalt",0,&operandTable[0]} ,//17 - {amdgpu_op_s_trap,"s_trap",0,&operandTable[0]} ,//18 - {amdgpu_op_s_icache_inv,"s_icache_inv",0,&operandTable[0]} ,//19 - {amdgpu_op_s_incperflevel,"s_incperflevel",0,&operandTable[0]} ,//20 - {amdgpu_op_s_decperflevel,"s_decperflevel",0,&operandTable[0]} ,//21 - {amdgpu_op_s_ttracedata,"s_ttracedata",0,&operandTable[0]} ,//22 - {amdgpu_op_s_cbranch_cdbgsys,"s_cbranch_cdbgsys",2,&operandTable[66]} ,//23 - {amdgpu_op_s_cbranch_cdbguser,"s_cbranch_cdbguser",2,&operandTable[68]} ,//24 - {amdgpu_op_s_cbranch_cdbgsys_or_user,"s_cbranch_cdbgsys_or_user",0,&operandTable[0]} ,//25 - {amdgpu_op_s_cbranch_cdbgsys_and_user,"s_cbranch_cdbgsys_and_user",2,&operandTable[70]} ,//26 - {amdgpu_op_s_endpgm_saved,"s_endpgm_saved",0,&operandTable[0]} ,//27 - {amdgpu_op_s_set_gpr_idx_off,"s_set_gpr_idx_off",0,&operandTable[0]} ,//28 - {amdgpu_op_s_set_gpr_idx_mode,"s_set_gpr_idx_mode",0,&operandTable[0]} ,//29 - {amdgpu_op_s_endpgm_ordered_ps_done,"s_endpgm_ordered_ps_done",0,&operandTable[0]} ,//30 -}; // end s_endpgm_ordered_ps_done_insn_table - -const amdgpu_insn_table amdgpu_insn_entry::smem_insn_table = { - {amdgpu_op_s_load_dword,"s_load_dword",2,&operandTable[1]} ,//0 - {amdgpu_op_s_load_dwordx2,"s_load_dwordx2",2,&operandTable[3]} ,//1 - {amdgpu_op_s_load_dwordx4,"s_load_dwordx4",2,&operandTable[5]} ,//2 - {amdgpu_op_s_load_dwordx8,"s_load_dwordx8",2,&operandTable[7]} ,//3 - {amdgpu_op_s_load_dwordx16,"s_load_dwordx16",2,&operandTable[9]} ,//4 - {amdgpu_op_s_scratch_load_dword,"s_scratch_load_dword",0,&operandTable[0]} ,//5 - {amdgpu_op_s_scratch_load_dwordx2,"s_scratch_load_dwordx2",0,&operandTable[0]} ,//6 - {amdgpu_op_s_scratch_load_dwordx4,"s_scratch_load_dwordx4",0,&operandTable[0]} ,//7 - {amdgpu_op_s_buffer_load_dword,"s_buffer_load_dword",2,&operandTable[11]} ,//8 - {amdgpu_op_s_buffer_load_dwordx2,"s_buffer_load_dwordx2",2,&operandTable[13]} ,//9 - {amdgpu_op_s_buffer_load_dwordx4,"s_buffer_load_dwordx4",2,&operandTable[15]} ,//10 - {amdgpu_op_s_buffer_load_dwordx8,"s_buffer_load_dwordx8",2,&operandTable[17]} ,//11 - {amdgpu_op_s_buffer_load_dwordx16,"s_buffer_load_dwordx16",2,&operandTable[19]} ,//12 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//13 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//14 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//15 - {amdgpu_op_s_store_dword,"s_store_dword",0,&operandTable[0]} ,//16 - {amdgpu_op_s_store_dwordx2,"s_store_dwordx2",0,&operandTable[0]} ,//17 - {amdgpu_op_s_store_dwordx4,"s_store_dwordx4",0,&operandTable[0]} ,//18 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//19 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//20 - {amdgpu_op_s_scratch_store_dword,"s_scratch_store_dword",0,&operandTable[0]} ,//21 - {amdgpu_op_s_scratch_store_dwordx2,"s_scratch_store_dwordx2",0,&operandTable[0]} ,//22 - {amdgpu_op_s_scratch_store_dwordx4,"s_scratch_store_dwordx4",0,&operandTable[0]} ,//23 - {amdgpu_op_s_buffer_store_dword,"s_buffer_store_dword",0,&operandTable[0]} ,//24 - {amdgpu_op_s_buffer_store_dwordx2,"s_buffer_store_dwordx2",0,&operandTable[0]} ,//25 - {amdgpu_op_s_buffer_store_dwordx4,"s_buffer_store_dwordx4",0,&operandTable[0]} ,//26 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//27 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//28 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//29 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//30 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//31 - {amdgpu_op_s_dcache_inv,"s_dcache_inv",0,&operandTable[0]} ,//32 - {amdgpu_op_s_dcache_wb,"s_dcache_wb",0,&operandTable[0]} ,//33 - {amdgpu_op_s_dcache_inv_vol,"s_dcache_inv_vol",0,&operandTable[0]} ,//34 - {amdgpu_op_s_dcache_wb_vol,"s_dcache_wb_vol",0,&operandTable[0]} ,//35 - {amdgpu_op_s_dcache_memtime,"s_dcache_memtime",0,&operandTable[0]} ,//36 - {amdgpu_op_s_dcache_memrealtime,"s_dcache_memrealtime",0,&operandTable[0]} ,//37 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//38 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//39 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//40 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//41 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//42 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//43 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//44 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//45 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//46 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//47 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//48 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//49 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//50 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//51 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//52 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//53 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//54 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//55 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//56 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//57 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//58 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//59 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//60 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//61 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//62 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//63 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//64 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//65 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//66 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//67 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//68 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//69 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//70 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//71 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//72 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//73 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//74 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//75 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//76 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//77 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//78 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//79 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//80 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//81 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//82 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//83 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//84 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//85 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//86 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//87 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//88 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//89 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//90 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//91 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//92 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//93 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//94 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//95 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//96 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//97 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//98 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//99 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//100 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//101 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//102 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//103 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//104 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//105 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//106 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//107 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//108 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//109 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//110 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//111 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//112 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//113 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//114 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//115 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//116 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//117 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//118 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//119 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//120 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//121 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//122 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//123 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//124 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//125 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//126 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//127 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//128 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//129 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//130 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//131 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//132 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//133 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//134 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//135 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//136 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//137 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//138 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//139 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//140 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//141 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//142 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//143 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//144 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//145 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//146 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//147 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//148 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//149 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//150 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//151 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//152 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//153 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//154 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//155 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//156 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//157 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//158 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//159 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//160 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//161 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//162 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//163 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//164 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//165 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//166 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//167 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//168 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//169 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//170 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//171 - {amdgpu_op_s_atomic_dec_x2,"s_atomic_dec_x2",0,&operandTable[0]} ,//172 -}; // end s_atomic_dec_x2_insn_table - -const amdgpu_insn_table amdgpu_insn_entry::vop2_insn_table = { - {amdgpu_op_v_cndmask_b32,"v_cndmask_b32",0,&operandTable[0]} ,//0 - {amdgpu_op_v_add_f32,"v_add_f32",0,&operandTable[0]} ,//1 - {amdgpu_op_v_sub_f32,"v_sub_f32",0,&operandTable[0]} ,//2 - {amdgpu_op_v_subrev_f32,"v_subrev_f32",0,&operandTable[0]} ,//3 - {amdgpu_op_v_mul_legacy_f32,"v_mul_legacy_f32",0,&operandTable[0]} ,//4 - {amdgpu_op_v_mul_f32,"v_mul_f32",0,&operandTable[0]} ,//5 - {amdgpu_op_v_mul_i32_i24,"v_mul_i32_i24",0,&operandTable[0]} ,//6 - {amdgpu_op_v_mul_hi_i32_i24,"v_mul_hi_i32_i24",0,&operandTable[0]} ,//7 - {amdgpu_op_v_mul_u32_u24,"v_mul_u32_u24",0,&operandTable[0]} ,//8 - {amdgpu_op_v_mul_hi_u32_u24,"v_mul_hi_u32_u24",0,&operandTable[0]} ,//9 - {amdgpu_op_v_min_f32,"v_min_f32",0,&operandTable[0]} ,//10 - {amdgpu_op_v_max_f32,"v_max_f32",0,&operandTable[0]} ,//11 - {amdgpu_op_v_min_i32,"v_min_i32",0,&operandTable[0]} ,//12 - {amdgpu_op_v_max_i32,"v_max_i32",0,&operandTable[0]} ,//13 - {amdgpu_op_v_min_u32,"v_min_u32",0,&operandTable[0]} ,//14 - {amdgpu_op_v_max_u32,"v_max_u32",0,&operandTable[0]} ,//15 - {amdgpu_op_v_lshrrev_b32,"v_lshrrev_b32",0,&operandTable[0]} ,//16 - {amdgpu_op_v_ashrrev_i32,"v_ashrrev_i32",0,&operandTable[0]} ,//17 - {amdgpu_op_v_lshlrev_b32,"v_lshlrev_b32",0,&operandTable[0]} ,//18 - {amdgpu_op_v_add_b32,"v_add_b32",0,&operandTable[0]} ,//19 - {amdgpu_op_v_or_b32,"v_or_b32",0,&operandTable[0]} ,//20 - {amdgpu_op_v_xor_b32,"v_xor_b32",0,&operandTable[0]} ,//21 - {amdgpu_op_v_mac_b32,"v_mac_b32",0,&operandTable[0]} ,//22 - {amdgpu_op_v_madmk_f32,"v_madmk_f32",0,&operandTable[0]} ,//23 - {amdgpu_op_v_madak_f32,"v_madak_f32",0,&operandTable[0]} ,//24 - {amdgpu_op_v_add_co_u32,"v_add_co_u32",0,&operandTable[0]} ,//25 - {amdgpu_op_v_sub_co_u32,"v_sub_co_u32",0,&operandTable[0]} ,//26 - {amdgpu_op_v_subrev_co_u32,"v_subrev_co_u32",0,&operandTable[0]} ,//27 - {amdgpu_op_v_addc_co_u32,"v_addc_co_u32",0,&operandTable[0]} ,//28 - {amdgpu_op_v_subb_co_u32,"v_subb_co_u32",0,&operandTable[0]} ,//29 - {amdgpu_op_v_subbrev_co_u32,"v_subbrev_co_u32",0,&operandTable[0]} ,//30 - {amdgpu_op_v_add_f16,"v_add_f16",0,&operandTable[0]} ,//31 - {amdgpu_op_v_sub_f16,"v_sub_f16",0,&operandTable[0]} ,//32 - {amdgpu_op_v_subrev_f16,"v_subrev_f16",0,&operandTable[0]} ,//33 - {amdgpu_op_v_mul_f16,"v_mul_f16",0,&operandTable[0]} ,//34 - {amdgpu_op_v_mac_f16,"v_mac_f16",0,&operandTable[0]} ,//35 - {amdgpu_op_v_madmk_f16,"v_madmk_f16",0,&operandTable[0]} ,//36 - {amdgpu_op_v_madak_f16,"v_madak_f16",0,&operandTable[0]} ,//37 - {amdgpu_op_v_add_u16,"v_add_u16",0,&operandTable[0]} ,//38 - {amdgpu_op_v_sub_u16,"v_sub_u16",0,&operandTable[0]} ,//39 - {amdgpu_op_v_subrev_u16,"v_subrev_u16",0,&operandTable[0]} ,//40 - {amdgpu_op_v_mul_lo_u16,"v_mul_lo_u16",0,&operandTable[0]} ,//41 - {amdgpu_op_v_lshlrev_b16,"v_lshlrev_b16",0,&operandTable[0]} ,//42 - {amdgpu_op_v_lshrrev_b16,"v_lshrrev_b16",0,&operandTable[0]} ,//43 - {amdgpu_op_v_ashrrev_i16,"v_ashrrev_i16",0,&operandTable[0]} ,//44 - {amdgpu_op_v_max_f16,"v_max_f16",0,&operandTable[0]} ,//45 - {amdgpu_op_v_min_f16,"v_min_f16",0,&operandTable[0]} ,//46 - {amdgpu_op_v_max_u16,"v_max_u16",0,&operandTable[0]} ,//47 - {amdgpu_op_v_max_i16,"v_max_i16",0,&operandTable[0]} ,//48 - {amdgpu_op_v_min_u16,"v_min_u16",0,&operandTable[0]} ,//49 - {amdgpu_op_v_min_i16,"v_min_i16",0,&operandTable[0]} ,//50 - {amdgpu_op_v_ldexp_f16,"v_ldexp_f16",0,&operandTable[0]} ,//51 - {amdgpu_op_v_add_u32,"v_add_u32",0,&operandTable[0]} ,//52 - {amdgpu_op_v_sub_u32,"v_sub_u32",0,&operandTable[0]} ,//53 - {amdgpu_op_v_subrev_u32,"v_subrev_u32",0,&operandTable[0]} ,//54 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//55 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//56 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//57 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//58 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//59 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//60 - {amdgpu_op_v_xno2_b32,"v_xno2_b32",0,&operandTable[0]} ,//61 -}; // end v_xno2_b32_insn_table - -const amdgpu_insn_table amdgpu_insn_entry::vop1_insn_table = { - {amdgpu_op_v_nop,"v_nop",0,&operandTable[0]} ,//0 - {amdgpu_op_v_mov_b32,"v_mov_b32",0,&operandTable[0]} ,//1 - {amdgpu_op_v_readfirstlane_b32,"v_readfirstlane_b32",0,&operandTable[0]} ,//2 - {amdgpu_op_v_cvt_i32_f64,"v_cvt_i32_f64",0,&operandTable[0]} ,//3 - {amdgpu_op_v_cvt_f64_i32,"v_cvt_f64_i32",0,&operandTable[0]} ,//4 - {amdgpu_op_v_cvt_f32_i32,"v_cvt_f32_i32",0,&operandTable[0]} ,//5 - {amdgpu_op_v_cvt_f32_u32,"v_cvt_f32_u32",0,&operandTable[0]} ,//6 - {amdgpu_op_v_cvt_u32_f32,"v_cvt_u32_f32",0,&operandTable[0]} ,//7 - {amdgpu_op_v_cvt_i32_f32,"v_cvt_i32_f32",0,&operandTable[0]} ,//8 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//9 - {amdgpu_op_v_cvt_f16_f32,"v_cvt_f16_f32",0,&operandTable[0]} ,//10 - {amdgpu_op_v_cvt_f32_f16,"v_cvt_f32_f16",0,&operandTable[0]} ,//11 - {amdgpu_op_v_cvt_rpi_i32_f32,"v_cvt_rpi_i32_f32",0,&operandTable[0]} ,//12 - {amdgpu_op_v_cvt_flr_i32_f32,"v_cvt_flr_i32_f32",0,&operandTable[0]} ,//13 - {amdgpu_op_v_cvt_off_f32_i4,"v_cvt_off_f32_i4",0,&operandTable[0]} ,//14 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//15 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//16 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//17 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//18 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//19 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//20 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//21 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//22 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//23 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//24 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//25 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//26 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//27 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//28 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//29 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//30 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//31 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//32 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//33 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//34 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//35 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//36 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//37 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//38 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//39 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//40 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//41 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//42 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//43 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//44 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//45 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//46 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//47 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//48 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//49 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//50 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//51 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//52 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//53 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//54 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//55 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//56 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//57 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//58 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//59 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//60 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//61 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//62 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//63 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//64 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//65 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//66 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//67 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//68 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//69 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//70 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//71 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//72 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//73 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//74 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//75 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//76 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//77 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//78 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//79 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//80 - {amdgpu_op_v_swap_b32,"v_swap_b32",0,&operandTable[0]} ,//81 -}; // end v_swap_b32_insn_table - -const amdgpu_insn_table amdgpu_insn_entry::vopc_insn_table = { - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//0 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//1 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//2 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//3 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//4 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//5 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//6 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//7 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//8 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//9 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//10 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//11 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//12 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//13 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//14 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//15 - {amdgpu_op_v_cmp_class_f32,"v_cmp_class_f32",0,&operandTable[0]} ,//16 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//17 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//18 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//19 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//20 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//21 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//22 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//23 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//24 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//25 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//26 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//27 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//28 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//29 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//30 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//31 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//32 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//33 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//34 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//35 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//36 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//37 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//38 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//39 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//40 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//41 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//42 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//43 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//44 - {amdgpu_op_v_cmp_neq_f16,"v_cmp_neq_f16",0,&operandTable[0]} ,//45 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//46 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//47 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//48 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//49 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//50 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//51 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//52 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//53 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//54 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//55 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//56 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//57 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//58 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//59 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//60 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//61 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//62 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//63 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//64 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//65 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//66 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//67 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//68 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//69 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//70 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//71 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//72 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//73 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//74 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//75 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//76 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//77 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//78 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//79 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//80 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//81 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//82 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//83 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//84 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//85 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//86 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//87 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//88 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//89 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//90 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//91 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//92 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//93 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//94 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//95 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//96 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//97 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//98 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//99 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//100 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//101 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//102 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//103 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//104 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//105 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//106 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//107 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//108 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//109 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//110 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//111 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//112 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//113 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//114 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//115 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//116 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//117 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//118 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//119 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//120 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//121 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//122 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//123 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//124 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//125 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//126 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//127 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//128 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//129 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//130 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//131 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//132 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//133 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//134 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//135 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//136 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//137 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//138 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//139 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//140 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//141 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//142 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//143 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//144 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//145 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//146 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//147 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//148 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//149 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//150 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//151 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//152 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//153 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//154 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//155 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//156 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//157 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//158 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//159 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//160 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//161 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//162 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//163 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//164 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//165 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//166 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//167 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//168 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//169 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//170 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//171 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//172 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//173 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//174 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//175 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//176 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//177 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//178 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//179 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//180 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//181 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//182 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//183 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//184 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//185 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//186 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//187 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//188 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//189 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//190 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//191 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//192 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//193 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//194 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//195 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//196 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//197 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//198 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//199 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//200 - {amdgpu_op_v_cmp_lt_u32,"v_cmp_lt_u32",0,&operandTable[0]} ,//201 - {amdgpu_op_v_cmp_eq_u32,"v_cmp_eq_u32",0,&operandTable[0]} ,//202 - {amdgpu_op_v_cmp_le_u32,"v_cmp_le_u32",0,&operandTable[0]} ,//203 - {amdgpu_op_v_cmp_gt_u32,"v_cmp_gt_u32",0,&operandTable[0]} ,//204 - {amdgpu_op_v_cmp_ne_u32,"v_cmp_ne_u32",0,&operandTable[0]} ,//205 - {amdgpu_op_v_cmp_ge_u32,"v_cmp_ge_u32",0,&operandTable[0]} ,//206 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//207 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//208 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//209 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//210 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//211 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//212 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//213 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//214 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//215 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//216 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//217 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//218 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//219 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//220 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//221 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//222 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//223 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//224 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//225 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//226 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//227 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//228 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//229 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//230 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//231 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//232 - {amdgpu_op_v_cmp_lt_u64,"v_cmp_lt_u64",0,&operandTable[0]} ,//233 - {amdgpu_op_v_cmp_eq_u64,"v_cmp_eq_u64",0,&operandTable[0]} ,//234 - {amdgpu_op_v_cmp_le_u64,"v_cmp_le_u64",0,&operandTable[0]} ,//235 - {amdgpu_op_v_cmp_gt_u64,"v_cmp_gt_u64",0,&operandTable[0]} ,//236 - {amdgpu_op_v_cmp_ne_u64,"v_cmp_ne_u64",0,&operandTable[0]} ,//237 - {amdgpu_op_v_cmp_ge_u64,"v_cmp_ge_u64",0,&operandTable[0]} ,//238 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//239 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//240 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//241 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//242 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//243 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//244 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//245 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//246 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//247 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//248 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//249 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//250 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//251 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//252 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//253 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//254 - {amdgpu_op_v_cmpx_t_u64,"v_cmpx_t_u64",0,&operandTable[0]} ,//255 -}; // end v_cmpx_t_u64_insn_table - -const amdgpu_insn_table amdgpu_insn_entry::vintrp_insn_table = { - {amdgpu_op_v_interp_p1_f32,"v_interp_p1_f32",0,&operandTable[0]} ,//0 - {amdgpu_op_v_interp_p2_f32,"v_interp_p2_f32",0,&operandTable[0]} ,//1 - {amdgpu_op_v_interp_mov_f32,"v_interp_mov_f32",0,&operandTable[0]} ,//2 -}; // end v_interp_mov_f32_insn_table - -const amdgpu_insn_table amdgpu_insn_entry::ds_insn_table = { - {amdgpu_op_ds_add_u32,"ds_add_u32",0,&operandTable[0]} ,//0 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//1 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//2 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//3 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//4 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//5 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//6 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//7 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//8 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//9 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//10 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//11 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//12 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//13 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//14 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//15 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//16 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//17 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//18 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//19 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//20 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//21 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//22 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//23 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//24 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//25 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//26 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//27 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//28 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//29 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//30 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//31 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//32 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//33 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//34 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//35 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//36 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//37 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//38 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//39 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//40 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//41 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//42 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//43 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//44 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//45 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//46 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//47 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//48 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//49 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//50 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//51 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//52 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//53 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//54 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//55 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//56 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//57 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//58 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//59 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//60 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//61 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//62 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//63 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//64 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//65 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//66 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//67 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//68 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//69 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//70 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//71 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//72 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//73 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//74 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//75 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//76 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//77 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//78 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//79 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//80 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//81 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//82 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//83 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//84 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//85 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//86 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//87 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//88 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//89 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//90 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//91 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//92 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//93 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//94 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//95 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//96 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//97 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//98 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//99 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//100 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//101 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//102 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//103 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//104 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//105 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//106 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//107 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//108 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//109 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//110 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//111 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//112 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//113 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//114 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//115 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//116 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//117 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//118 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//119 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//120 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//121 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//122 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//123 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//124 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//125 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//126 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//127 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//128 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//129 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//130 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//131 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//132 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//133 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//134 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//135 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//136 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//137 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//138 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//139 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//140 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//141 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//142 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//143 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//144 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//145 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//146 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//147 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//148 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//149 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//150 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//151 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//152 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//153 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//154 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//155 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//156 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//157 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//158 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//159 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//160 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//161 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//162 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//163 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//164 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//165 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//166 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//167 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//168 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//169 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//170 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//171 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//172 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//173 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//174 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//175 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//176 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//177 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//178 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//179 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//180 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//181 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//182 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//183 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//184 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//185 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//186 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//187 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//188 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//189 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//190 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//191 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//192 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//193 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//194 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//195 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//196 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//197 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//198 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//199 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//200 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//201 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//202 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//203 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//204 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//205 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//206 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//207 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//208 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//209 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//210 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//211 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//212 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//213 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//214 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//215 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//216 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//217 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//218 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//219 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//220 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//221 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//222 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//223 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//224 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//225 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//226 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//227 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//228 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//229 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//230 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//231 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//232 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//233 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//234 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//235 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//236 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//237 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//238 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//239 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//240 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//241 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//242 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//243 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//244 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//245 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//246 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//247 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//248 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//249 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//250 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//251 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//252 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//253 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//254 - {amdgpu_op_ds_read_b128,"ds_read_b128",0,&operandTable[0]} ,//255 -}; // end ds_read_b128_insn_table - -const amdgpu_insn_table amdgpu_insn_entry::mtbuf_insn_table = { - {amdgpu_op_tbuffer_load_format_x,"tbuffer_load_format_x",2,&operandTable[37]} ,//0 - {amdgpu_op_tbuffer_load_format_xy,"tbuffer_load_format_xy",2,&operandTable[39]} ,//1 - {amdgpu_op_tbuffer_load_format_xyz,"tbuffer_load_format_xyz",2,&operandTable[41]} ,//2 - {amdgpu_op_tbuffer_load_format_xyzw,"tbuffer_load_format_xyzw",2,&operandTable[43]} ,//3 - {amdgpu_op_tbuffer_store_format_x,"tbuffer_store_format_x",2,&operandTable[45]} ,//4 - {amdgpu_op_tbuffer_store_format_xy,"tbuffer_store_format_xy",2,&operandTable[47]} ,//5 - {amdgpu_op_tbuffer_store_format_xyz,"tbuffer_store_format_xyz",2,&operandTable[49]} ,//6 - {amdgpu_op_tbuffer_store_format_xyzw,"tbuffer_store_format_xyzw",2,&operandTable[51]} ,//7 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//8 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//9 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//10 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//11 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//12 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//13 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//14 - {amdgpu_op_tbuffer_store_format_d16_xyzw,"tbuffer_store_format_d16_xyzw",0,&operandTable[0]} ,//15 -}; // end tbuffer_store_format_d16_xyzw_insn_table - -const amdgpu_insn_table amdgpu_insn_entry::mubuf_insn_table = { - {amdgpu_op_buffer_load_format_x,"buffer_load_format_x",2,&operandTable[21]} ,//0 - {amdgpu_op_buffer_load_format_xy,"buffer_load_format_xy",2,&operandTable[23]} ,//1 - {amdgpu_op_buffer_load_format_xyz,"buffer_load_format_xyz",2,&operandTable[25]} ,//2 - {amdgpu_op_buffer_load_format_xyzw,"buffer_load_format_xyzw",2,&operandTable[27]} ,//3 - {amdgpu_op_buffer_store_format_x,"buffer_store_format_x",2,&operandTable[29]} ,//4 - {amdgpu_op_buffer_store_format_xy,"buffer_store_format_xy",2,&operandTable[31]} ,//5 - {amdgpu_op_buffer_store_format_xyz,"buffer_store_format_xyz",2,&operandTable[33]} ,//6 - {amdgpu_op_buffer_store_format_xyzw,"buffer_store_format_xyzw",2,&operandTable[35]} ,//7 - {amdgpu_op_buffer_load_dwordx4,"buffer_load_dwordx4",0,&operandTable[0]} ,//8 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//9 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//10 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//11 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//12 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//13 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//14 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//15 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//16 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//17 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//18 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//19 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//20 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//21 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//22 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//23 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//24 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//25 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//26 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//27 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//28 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//29 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//30 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//31 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//32 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//33 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//34 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//35 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//36 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//37 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//38 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//39 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//40 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//41 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//42 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//43 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//44 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//45 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//46 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//47 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//48 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//49 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//50 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//51 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//52 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//53 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//54 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//55 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//56 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//57 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//58 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//59 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//60 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//61 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//62 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//63 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//64 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//65 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//66 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//67 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//68 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//69 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//70 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//71 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//72 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//73 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//74 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//75 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//76 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//77 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//78 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//79 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//80 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//81 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//82 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//83 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//84 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//85 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//86 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//87 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//88 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//89 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//90 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//91 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//92 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//93 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//94 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//95 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//96 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//97 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//98 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//99 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//100 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//101 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//102 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//103 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//104 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//105 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//106 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//107 - {amdgpu_op_buffer_atomic_dec_x2,"buffer_atomic_dec_x2",0,&operandTable[0]} ,//108 -}; // end buffer_atomic_dec_x2_insn_table - -const amdgpu_insn_table amdgpu_insn_entry::vop3ab_insn_table = { - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//0 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//1 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//2 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//3 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//4 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//5 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//6 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//7 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//8 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//9 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//10 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//11 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//12 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//13 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//14 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//15 - {amdgpu_op_v_cmp_class_f32_e64,"v_cmp_class_f32_e64",0,&operandTable[0]} ,//16 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//17 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//18 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//19 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//20 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//21 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//22 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//23 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//24 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//25 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//26 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//27 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//28 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//29 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//30 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//31 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//32 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//33 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//34 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//35 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//36 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//37 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//38 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//39 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//40 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//41 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//42 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//43 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//44 - {amdgpu_op_v_cmp_neq_f16_e64,"v_cmp_neq_f16_e64",0,&operandTable[0]} ,//45 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//46 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//47 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//48 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//49 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//50 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//51 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//52 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//53 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//54 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//55 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//56 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//57 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//58 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//59 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//60 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//61 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//62 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//63 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//64 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//65 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//66 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//67 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//68 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//69 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//70 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//71 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//72 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//73 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//74 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//75 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//76 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//77 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//78 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//79 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//80 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//81 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//82 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//83 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//84 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//85 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//86 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//87 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//88 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//89 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//90 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//91 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//92 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//93 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//94 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//95 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//96 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//97 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//98 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//99 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//100 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//101 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//102 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//103 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//104 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//105 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//106 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//107 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//108 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//109 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//110 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//111 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//112 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//113 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//114 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//115 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//116 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//117 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//118 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//119 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//120 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//121 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//122 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//123 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//124 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//125 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//126 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//127 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//128 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//129 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//130 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//131 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//132 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//133 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//134 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//135 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//136 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//137 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//138 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//139 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//140 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//141 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//142 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//143 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//144 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//145 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//146 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//147 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//148 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//149 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//150 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//151 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//152 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//153 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//154 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//155 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//156 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//157 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//158 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//159 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//160 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//161 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//162 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//163 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//164 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//165 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//166 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//167 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//168 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//169 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//170 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//171 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//172 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//173 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//174 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//175 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//176 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//177 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//178 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//179 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//180 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//181 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//182 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//183 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//184 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//185 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//186 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//187 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//188 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//189 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//190 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//191 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//192 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//193 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//194 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//195 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//196 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//197 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//198 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//199 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//200 - {amdgpu_op_v_cmp_lt_u32_e64,"v_cmp_lt_u32_e64",0,&operandTable[0]} ,//201 - {amdgpu_op_v_cmp_eq_u32_e64,"v_cmp_eq_u32_e64",0,&operandTable[0]} ,//202 - {amdgpu_op_v_cmp_le_u32_e64,"v_cmp_le_u32_e64",0,&operandTable[0]} ,//203 - {amdgpu_op_v_cmp_gt_u32_e64,"v_cmp_gt_u32_e64",0,&operandTable[0]} ,//204 - {amdgpu_op_v_cmp_ne_u32_e64,"v_cmp_ne_u32_e64",0,&operandTable[0]} ,//205 - {amdgpu_op_v_cmp_ge_u32_e64,"v_cmp_ge_u32_e64",0,&operandTable[0]} ,//206 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//207 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//208 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//209 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//210 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//211 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//212 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//213 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//214 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//215 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//216 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//217 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//218 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//219 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//220 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//221 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//222 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//223 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//224 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//225 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//226 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//227 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//228 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//229 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//230 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//231 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//232 - {amdgpu_op_v_cmp_lt_u64_e64,"v_cmp_lt_u64_e64",0,&operandTable[0]} ,//233 - {amdgpu_op_v_cmp_eq_u64_e64,"v_cmp_eq_u64_e64",0,&operandTable[0]} ,//234 - {amdgpu_op_v_cmp_le_u64_e64,"v_cmp_le_u64_e64",0,&operandTable[0]} ,//235 - {amdgpu_op_v_cmp_gt_u64_e64,"v_cmp_gt_u64_e64",0,&operandTable[0]} ,//236 - {amdgpu_op_v_cmp_ne_u64_e64,"v_cmp_ne_u64_e64",0,&operandTable[0]} ,//237 - {amdgpu_op_v_cmp_ge_u64_e64,"v_cmp_ge_u64_e64",0,&operandTable[0]} ,//238 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//239 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//240 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//241 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//242 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//243 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//244 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//245 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//246 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//247 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//248 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//249 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//250 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//251 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//252 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//253 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//254 - {amdgpu_op_v_cmpx_t_u64_e64,"v_cmpx_t_u64_e64",0,&operandTable[0]} ,//255 - {amdgpu_op_v_cndmask_b32_e64,"v_cndmask_b32_e64",0,&operandTable[0]} ,//256 - {amdgpu_op_v_add_f32_e64,"v_add_f32_e64",0,&operandTable[0]} ,//257 - {amdgpu_op_v_sub_f32_e64,"v_sub_f32_e64",0,&operandTable[0]} ,//258 - {amdgpu_op_v_subrev_f32_e64,"v_subrev_f32_e64",0,&operandTable[0]} ,//259 - {amdgpu_op_v_mul_legacy_f32_e64,"v_mul_legacy_f32_e64",0,&operandTable[0]} ,//260 - {amdgpu_op_v_mul_f32_e64,"v_mul_f32_e64",0,&operandTable[0]} ,//261 - {amdgpu_op_v_mul_i32_i24_e64,"v_mul_i32_i24_e64",0,&operandTable[0]} ,//262 - {amdgpu_op_v_mul_hi_i32_i24_e64,"v_mul_hi_i32_i24_e64",0,&operandTable[0]} ,//263 - {amdgpu_op_v_mul_u32_u24_e64,"v_mul_u32_u24_e64",0,&operandTable[0]} ,//264 - {amdgpu_op_v_mul_hi_u32_u24_e64,"v_mul_hi_u32_u24_e64",0,&operandTable[0]} ,//265 - {amdgpu_op_v_min_f32_e64,"v_min_f32_e64",0,&operandTable[0]} ,//266 - {amdgpu_op_v_max_f32_e64,"v_max_f32_e64",0,&operandTable[0]} ,//267 - {amdgpu_op_v_min_i32_e64,"v_min_i32_e64",0,&operandTable[0]} ,//268 - {amdgpu_op_v_max_i32_e64,"v_max_i32_e64",0,&operandTable[0]} ,//269 - {amdgpu_op_v_min_u32_e64,"v_min_u32_e64",0,&operandTable[0]} ,//270 - {amdgpu_op_v_max_u32_e64,"v_max_u32_e64",0,&operandTable[0]} ,//271 - {amdgpu_op_v_lshrrev_b32_e64,"v_lshrrev_b32_e64",0,&operandTable[0]} ,//272 - {amdgpu_op_v_ashrrev_i32_e64,"v_ashrrev_i32_e64",0,&operandTable[0]} ,//273 - {amdgpu_op_v_lshlrev_b32_e64,"v_lshlrev_b32_e64",0,&operandTable[0]} ,//274 - {amdgpu_op_v_add_b32_e64,"v_add_b32_e64",0,&operandTable[0]} ,//275 - {amdgpu_op_v_or_b32_e64,"v_or_b32_e64",0,&operandTable[0]} ,//276 - {amdgpu_op_v_xor_b32_e64,"v_xor_b32_e64",0,&operandTable[0]} ,//277 - {amdgpu_op_v_mac_b32_e64,"v_mac_b32_e64",0,&operandTable[0]} ,//278 - {amdgpu_op_v_madmk_f32_e64,"v_madmk_f32_e64",0,&operandTable[0]} ,//279 - {amdgpu_op_v_madak_f32_e64,"v_madak_f32_e64",0,&operandTable[0]} ,//280 - {amdgpu_op_v_add_co_u32_e64,"v_add_co_u32_e64",0,&operandTable[0]} ,//281 - {amdgpu_op_v_sub_co_u32_e64,"v_sub_co_u32_e64",0,&operandTable[0]} ,//282 - {amdgpu_op_v_subrev_co_u32_e64,"v_subrev_co_u32_e64",0,&operandTable[0]} ,//283 - {amdgpu_op_v_addc_co_u32_e64,"v_addc_co_u32_e64",0,&operandTable[0]} ,//284 - {amdgpu_op_v_subb_co_u32_e64,"v_subb_co_u32_e64",0,&operandTable[0]} ,//285 - {amdgpu_op_v_subbrev_co_u32_e64,"v_subbrev_co_u32_e64",0,&operandTable[0]} ,//286 - {amdgpu_op_v_add_f16_e64,"v_add_f16_e64",0,&operandTable[0]} ,//287 - {amdgpu_op_v_sub_f16_e64,"v_sub_f16_e64",0,&operandTable[0]} ,//288 - {amdgpu_op_v_subrev_f16_e64,"v_subrev_f16_e64",0,&operandTable[0]} ,//289 - {amdgpu_op_v_mul_f16_e64,"v_mul_f16_e64",0,&operandTable[0]} ,//290 - {amdgpu_op_v_mac_f16_e64,"v_mac_f16_e64",0,&operandTable[0]} ,//291 - {amdgpu_op_v_madmk_f16_e64,"v_madmk_f16_e64",0,&operandTable[0]} ,//292 - {amdgpu_op_v_madak_f16_e64,"v_madak_f16_e64",0,&operandTable[0]} ,//293 - {amdgpu_op_v_add_u16_e64,"v_add_u16_e64",0,&operandTable[0]} ,//294 - {amdgpu_op_v_sub_u16_e64,"v_sub_u16_e64",0,&operandTable[0]} ,//295 - {amdgpu_op_v_subrev_u16_e64,"v_subrev_u16_e64",0,&operandTable[0]} ,//296 - {amdgpu_op_v_mul_lo_u16_e64,"v_mul_lo_u16_e64",0,&operandTable[0]} ,//297 - {amdgpu_op_v_lshlrev_b16_e64,"v_lshlrev_b16_e64",0,&operandTable[0]} ,//298 - {amdgpu_op_v_lshrrev_b16_e64,"v_lshrrev_b16_e64",0,&operandTable[0]} ,//299 - {amdgpu_op_v_ashrrev_i16_e64,"v_ashrrev_i16_e64",0,&operandTable[0]} ,//300 - {amdgpu_op_v_max_f16_e64,"v_max_f16_e64",0,&operandTable[0]} ,//301 - {amdgpu_op_v_min_f16_e64,"v_min_f16_e64",0,&operandTable[0]} ,//302 - {amdgpu_op_v_max_u16_e64,"v_max_u16_e64",0,&operandTable[0]} ,//303 - {amdgpu_op_v_max_i16_e64,"v_max_i16_e64",0,&operandTable[0]} ,//304 - {amdgpu_op_v_min_u16_e64,"v_min_u16_e64",0,&operandTable[0]} ,//305 - {amdgpu_op_v_min_i16_e64,"v_min_i16_e64",0,&operandTable[0]} ,//306 - {amdgpu_op_v_ldexp_f16_e64,"v_ldexp_f16_e64",0,&operandTable[0]} ,//307 - {amdgpu_op_v_add_u32_e64,"v_add_u32_e64",0,&operandTable[0]} ,//308 - {amdgpu_op_v_sub_u32_e64,"v_sub_u32_e64",0,&operandTable[0]} ,//309 - {amdgpu_op_v_subrev_u32_e64,"v_subrev_u32_e64",0,&operandTable[0]} ,//310 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//311 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//312 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//313 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//314 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//315 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//316 - {amdgpu_op_v_xno2_b32_e64,"v_xno2_b32_e64",0,&operandTable[0]} ,//317 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//318 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//319 - {amdgpu_op_v_nop_e64,"v_nop_e64",0,&operandTable[0]} ,//320 - {amdgpu_op_v_mov_b32_e64,"v_mov_b32_e64",0,&operandTable[0]} ,//321 - {amdgpu_op_v_readfirstlane_b32_e64,"v_readfirstlane_b32_e64",0,&operandTable[0]} ,//322 - {amdgpu_op_v_cvt_i32_f64_e64,"v_cvt_i32_f64_e64",0,&operandTable[0]} ,//323 - {amdgpu_op_v_cvt_f64_i32_e64,"v_cvt_f64_i32_e64",0,&operandTable[0]} ,//324 - {amdgpu_op_v_cvt_f32_i32_e64,"v_cvt_f32_i32_e64",0,&operandTable[0]} ,//325 - {amdgpu_op_v_cvt_f32_u32_e64,"v_cvt_f32_u32_e64",0,&operandTable[0]} ,//326 - {amdgpu_op_v_cvt_u32_f32_e64,"v_cvt_u32_f32_e64",0,&operandTable[0]} ,//327 - {amdgpu_op_v_cvt_i32_f32_e64,"v_cvt_i32_f32_e64",0,&operandTable[0]} ,//328 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//329 - {amdgpu_op_v_cvt_f16_f32_e64,"v_cvt_f16_f32_e64",0,&operandTable[0]} ,//330 - {amdgpu_op_v_cvt_f32_f16_e64,"v_cvt_f32_f16_e64",0,&operandTable[0]} ,//331 - {amdgpu_op_v_cvt_rpi_i32_f32_e64,"v_cvt_rpi_i32_f32_e64",0,&operandTable[0]} ,//332 - {amdgpu_op_v_cvt_flr_i32_f32_e64,"v_cvt_flr_i32_f32_e64",0,&operandTable[0]} ,//333 - {amdgpu_op_v_cvt_off_f32_i4_e64,"v_cvt_off_f32_i4_e64",0,&operandTable[0]} ,//334 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//335 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//336 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//337 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//338 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//339 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//340 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//341 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//342 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//343 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//344 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//345 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//346 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//347 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//348 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//349 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//350 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//351 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//352 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//353 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//354 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//355 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//356 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//357 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//358 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//359 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//360 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//361 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//362 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//363 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//364 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//365 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//366 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//367 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//368 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//369 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//370 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//371 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//372 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//373 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//374 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//375 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//376 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//377 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//378 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//379 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//380 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//381 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//382 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//383 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//384 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//385 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//386 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//387 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//388 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//389 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//390 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//391 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//392 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//393 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//394 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//395 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//396 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//397 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//398 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//399 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//400 - {amdgpu_op_v_swap_b32_e64,"v_swap_b32_e64",0,&operandTable[0]} ,//401 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//402 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//403 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//404 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//405 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//406 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//407 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//408 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//409 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//410 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//411 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//412 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//413 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//414 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//415 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//416 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//417 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//418 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//419 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//420 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//421 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//422 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//423 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//424 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//425 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//426 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//427 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//428 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//429 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//430 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//431 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//432 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//433 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//434 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//435 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//436 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//437 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//438 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//439 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//440 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//441 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//442 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//443 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//444 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//445 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//446 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//447 - {amdgpu_op_v_mad_legacy_f32,"v_mad_legacy_f32",0,&operandTable[0]} ,//448 - {amdgpu_op_v_mad_f32,"v_mad_f32",0,&operandTable[0]} ,//449 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//450 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//451 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//452 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//453 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//454 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//455 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//456 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//457 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//458 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//459 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//460 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//461 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//462 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//463 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//464 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//465 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//466 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//467 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//468 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//469 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//470 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//471 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//472 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//473 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//474 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//475 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//476 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//477 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//478 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//479 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//480 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//481 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//482 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//483 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//484 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//485 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//486 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//487 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//488 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//489 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//490 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//491 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//492 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//493 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//494 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//495 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//496 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//497 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//498 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//499 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//500 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//501 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//502 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//503 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//504 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//505 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//506 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//507 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//508 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//509 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//510 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//511 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//512 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//513 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//514 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//515 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//516 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//517 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//518 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//519 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//520 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//521 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//522 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//523 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//524 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//525 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//526 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//527 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//528 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//529 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//530 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//531 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//532 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//533 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//534 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//535 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//536 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//537 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//538 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//539 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//540 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//541 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//542 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//543 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//544 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//545 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//546 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//547 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//548 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//549 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//550 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//551 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//552 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//553 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//554 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//555 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//556 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//557 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//558 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//559 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//560 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//561 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//562 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//563 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//564 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//565 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//566 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//567 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//568 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//569 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//570 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//571 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//572 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//573 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//574 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//575 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//576 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//577 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//578 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//579 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//580 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//581 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//582 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//583 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//584 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//585 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//586 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//587 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//588 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//589 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//590 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//591 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//592 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//593 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//594 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//595 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//596 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//597 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//598 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//599 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//600 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//601 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//602 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//603 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//604 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//605 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//606 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//607 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//608 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//609 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//610 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//611 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//612 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//613 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//614 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//615 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//616 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//617 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//618 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//619 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//620 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//621 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//622 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//623 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//624 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//625 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//626 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//627 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//628 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//629 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//630 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//631 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//632 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//633 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//634 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//635 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//636 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//637 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//638 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//639 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//640 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//641 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//642 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//643 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//644 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//645 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//646 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//647 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//648 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//649 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//650 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//651 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//652 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//653 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//654 - {amdgpu_op_v_lshlrev_b64,"v_lshlrev_b64",0,&operandTable[0]} ,//655 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//656 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//657 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//658 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//659 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//660 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//661 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//662 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//663 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//664 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//665 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//666 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//667 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//668 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//669 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//670 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//671 - {amdgpu_op_v_pack_b32_f16,"v_pack_b32_f16",0,&operandTable[0]} ,//672 -}; // end v_pack_b32_f16_insn_table - -const amdgpu_insn_table amdgpu_insn_entry::vop3p_insn_table = { - {amdgpu_op_v_pk_mad_i16,"v_pk_mad_i16",0,&operandTable[0]} ,//0 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//1 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//2 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//3 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//4 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//5 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//6 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//7 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//8 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//9 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//10 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//11 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//12 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//13 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//14 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//15 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//16 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//17 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//18 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//19 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//20 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//21 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//22 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//23 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//24 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//25 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//26 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//27 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//28 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//29 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//30 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//31 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//32 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//33 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//34 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//35 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//36 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//37 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//38 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//39 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//40 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//41 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//42 - {amdgpu_op_v_dot8_u32_u4,"v_dot8_u32_u4",0,&operandTable[0]} ,//43 -}; // end v_dot8_u32_u4_insn_table - -const amdgpu_insn_table amdgpu_insn_entry::flat_insn_table = { - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//0 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//1 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//2 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//3 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//4 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//5 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//6 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//7 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//8 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//9 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//10 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//11 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//12 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//13 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//14 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//15 - {amdgpu_op_load_ubyte,"load_ubyte",0,&operandTable[0]} ,//16 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//17 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//18 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//19 - {amdgpu_op_load_dword,"load_dword",0,&operandTable[0]} ,//20 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//21 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//22 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//23 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//24 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//25 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//26 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//27 - {amdgpu_op_store_dword,"store_dword",0,&operandTable[0]} ,//28 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//29 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//30 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//31 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//32 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//33 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//34 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//35 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//36 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//37 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//38 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//39 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//40 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//41 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//42 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//43 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//44 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//45 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//46 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//47 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//48 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//49 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//50 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//51 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//52 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//53 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//54 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//55 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//56 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//57 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//58 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//59 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//60 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//61 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//62 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//63 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//64 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//65 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//66 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//67 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//68 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//69 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//70 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//71 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//72 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//73 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//74 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//75 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//76 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//77 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//78 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//79 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//80 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//81 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//82 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//83 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//84 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//85 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//86 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//87 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//88 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//89 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//90 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//91 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//92 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//93 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//94 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//95 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//96 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//97 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//98 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//99 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//100 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//101 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//102 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//103 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//104 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//105 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//106 - {amdgpu_op_s_nop,"s_nop",0,&operandTable[0]} ,//107 - {amdgpu_op_atomic_dec_x2,"atomic_dec_x2",0,&operandTable[0]} ,//108 -}; // end atomic_dec_x2_insn_table - diff --git a/instructionAPI/src/debug.C b/instructionAPI/src/debug.C new file mode 100644 index 0000000000..d7b1ca9842 --- /dev/null +++ b/instructionAPI/src/debug.C @@ -0,0 +1,36 @@ +#include "debug.h" +#include +#include +#include +#include + +namespace { + bool debug_decode = false; + std::once_flag init_flag{}; + + void init() { + std::call_once(init_flag, + []() noexcept { + if(getenv("INSTRUCTIONAPI_DEBUG_DECODE")) { + debug_decode = true; + } + } + ); + } +} + +namespace Dyninst { namespace InstructionAPI { + + void decode_printf(const char *format, ...) { + if (NULL == format) return; + + init(); + if (!debug_decode) return; + + va_list va; + va_start(va, format); + vfprintf(stderr, format, va); + va_end(va); + } + +}} diff --git a/common/src/machineType.h b/instructionAPI/src/debug.h similarity index 84% rename from common/src/machineType.h rename to instructionAPI/src/debug.h index 631528d2b1..a6b11c9de1 100644 --- a/common/src/machineType.h +++ b/instructionAPI/src/debug.h @@ -1,39 +1,42 @@ /* * See the dyninst/COPYRIGHT file for copyright information. - * + * * We provide the Paradyn Tools (below described as "Paradyn") * on an AS IS basis, and do not warrant its validity or performance. * We reserve the right to update, modify, or discontinue this * software at any time. We shall have no obligation to supply such * updates or modifications or any other form of support to you. - * + * * By your use of Paradyn, you understand and agree that we (or any * other person or entity with proprietary rights in Paradyn) are * under no obligation to provide either maintenance services, * update services, notices of latent defects, or correction of * defects for Paradyn. - * + * * This library is free software; you can redistribute it and/or * modify it under the terms of the GNU Lesser General Public * License as published by the Free Software Foundation; either * version 2.1 of the License, or (at your option) any later version. - * + * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU * Lesser General Public License for more details. - * + * * You should have received a copy of the GNU Lesser General Public * License along with this library; if not, write to the Free Software * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef MACHINE_TYPE_ENUM -#define MACHINE_TYPE_ENUM +#ifndef DYNINST_INSTRUCTIONAPI_DEBUG_H +#define DYNINST_INSTRUCTIONAPI_DEBUG_H -// $Id: machineType.h,v +#include "compiler_annotations.h" -#define metCM5 1 -#define metUNIX 2 +namespace Dyninst { namespace InstructionAPI { + + void decode_printf(const char *format, ...) DYNINST_PRINTF_ANNOTATION(1, 2); + +}} #endif diff --git a/patchAPI/test/findPoint/mutatee/main.c b/instructionAPI/src/interrupts.C similarity index 56% rename from patchAPI/test/findPoint/mutatee/main.c rename to instructionAPI/src/interrupts.C index 80f36bc975..8c95226cd2 100644 --- a/patchAPI/test/findPoint/mutatee/main.c +++ b/instructionAPI/src/interrupts.C @@ -1,46 +1,83 @@ /* * See the dyninst/COPYRIGHT file for copyright information. - * + * * We provide the Paradyn Tools (below described as "Paradyn") * on an AS IS basis, and do not warrant its validity or performance. * We reserve the right to update, modify, or discontinue this * software at any time. We shall have no obligation to supply such * updates or modifications or any other form of support to you. - * + * * By your use of Paradyn, you understand and agree that we (or any * other person or entity with proprietary rights in Paradyn) are * under no obligation to provide either maintenance services, * update services, notices of latent defects, or correction of * defects for Paradyn. - * + * * This library is free software; you can redistribute it and/or * modify it under the terms of the GNU Lesser General Public * License as published by the Free Software Foundation; either * version 2.1 of the License, or (at your option) any later version. - * + * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU * Lesser General Public License for more details. - * + * * You should have received a copy of the GNU Lesser General Public * License along with this library; if not, write to the Free Software * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ -#include -#include -void foo1() { - printf("i'm foo1\n"); +#include "debug.h" +#include "interrupts.h" + +namespace di = Dyninst::InstructionAPI; + +namespace x86 { + bool isSoftwareInterrupt(di::Instruction const& ins) { + auto id = ins.getOperation().getID(); + switch(id) { + case e_int: + case e_int1: + case e_into: + case e_int3: + return true; + default: + return false; + } + } } -void foo2() { - printf("i'm foo2\n"); + +namespace ppc { + bool isSoftwareInterrupt(di::Instruction const&) { + return false; + } +} + +namespace aarch64 { + bool isSoftwareInterrupt(di::Instruction const&) { + return false; + } } -int main(int argc, const char *argv[]) -{ - if (argc > 2) return 0; - foo1(); - foo2(); - return 0; +bool di::isSoftwareInterrupt(Instruction const& ins) { + switch(ins.getArch()) { + case Arch_x86: + case Arch_x86_64: + return ::x86::isSoftwareInterrupt(ins); + case Arch_ppc32: + case Arch_ppc64: + return ::ppc::isSoftwareInterrupt(ins); + case Arch_aarch64: + return ::aarch64::isSoftwareInterrupt(ins); + case Arch_none: + case Arch_aarch32: + case Arch_cuda: + case Arch_amdgpu_gfx908: + case Arch_amdgpu_gfx90a: + case Arch_amdgpu_gfx940: + case Arch_intelGen9: + return false; + } + return false; } diff --git a/instructionAPI/src/syscalls.C b/instructionAPI/src/syscalls.C new file mode 100644 index 0000000000..8d2f6e4641 --- /dev/null +++ b/instructionAPI/src/syscalls.C @@ -0,0 +1,202 @@ +/* + * See the dyninst/COPYRIGHT file for copyright information. + * + * We provide the Paradyn Tools (below described as "Paradyn") + * on an AS IS basis, and do not warrant its validity or performance. + * We reserve the right to update, modify, or discontinue this + * software at any time. We shall have no obligation to supply such + * updates or modifications or any other form of support to you. + * + * By your use of Paradyn, you understand and agree that we (or any + * other person or entity with proprietary rights in Paradyn) are + * under no obligation to provide either maintenance services, + * update services, notices of latent defects, or correction of + * defects for Paradyn. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "BinaryFunction.h" +#include "Dereference.h" +#include "Immediate.h" +#include "Register.h" +#include "Result.h" +#include "Visitor.h" +#include "debug.h" +#include "registers/x86_regs.h" +#include "syscalls.h" + +namespace di = Dyninst::InstructionAPI; + +namespace x86 { + + /* Thread Control Block syscall visitor + * + * Used to detect 'call gs:[0x10]' syscalls in 32-bit code. + */ + struct tcb_syscall_visitor : di::Visitor { + di::Result value; + int num_imm{0}; + bool valid{true}; + bool found_deref{false}; + + void visit(di::BinaryFunction*) override { valid = false; } + + void visit(di::Immediate* imm) override { + num_imm++; + value = imm->eval(); + } + + void visit(di::RegisterAST*) override { valid = false; } + + void visit(di::Dereference*) override { found_deref = true; } + }; + + namespace { + di::RegisterAST::Ptr gs(new di::RegisterAST(Dyninst::x86::gs)); + } + + /* Check for system call idioms + * + * Idioms checked: + * + * syscall + * int (e.g., 'int 0x80') + * call DWORD PTR gs:[0x10] + * + * Calls to Linux vdso functions (e.g., __vdso_clock_gettime) + * are not considered system calls because they use the standard + * call mechanism to explicitly bypass the kernel. + * + * 'sysenter' is checked by IA_IAPI::isSysEnter(). + */ + bool isSystemCall(di::Instruction const& ins) { + auto const id = ins.getOperation().getID(); + + /* + * 'syscall' is only available in 64-bit mode, but is the most likely + * instruction to be encountered for system calls so check it first. + */ + if(id == e_syscall) { + return true; + } + + /* Software interrupts + * + * All interrupts that specify a vector go directly through the kernel, + * so they are system calls. + * + * Interrupts for traps/breakpoints (notable int3, int1, and into) don't + * directly go through the kernel, so aren't considered system calls. + */ + if(id == e_int) { + return true; + } + + /* !! Everything below here is for 32-bit code only !! + * + * Although technically possible, these idioms are very unlikely to + * be encountered in 64-bit mode. Because they use generic instructions + * like 'call', we don't want to introduce the overhead of checking them + * unless it's truly necessary. + */ + if(ins.getArch() != Dyninst::Arch_x86) { + return false; + } + + /* Check 'call gs:[0x10]' + * + * In some old 32-bit libc's, it was cheaper for the loader to put the + * value of the kernel's system call entry point (AT_SYSINFO) into a fixed + * location. One particular place was at 'gs:0x10' (in the Thread Control Block). + * That value was likely taken from https://articles.manugarg.com/systemcallinlinux2_6.html. + * In this case, 'call gs:[0x10]' is really a system call. + * + * Dyninst doesn't correctly represent segment registers in AST, so the instruction + * it produces is 'call [0x10]'. This isn't something a compiler would generate, + * so we'll consider it as our special case here. + */ + if(id == e_call) { + std::vector operands; + ins.getOperands(operands); + + if(operands.size() != 1) { + di::decode_printf("[%s:%d] Incorrect number of arguments to 'call'. Found %lu, expected 1\n", + __FILE__, __LINE__, operands.size()); + return false; + } + + auto in = ins; // 'isRead' isn't const + if(!in.getOperation().isRead(gs)) { + return false; + } + + tcb_syscall_visitor v; + operands[0].getValue()->apply(&v); + + // The addressing mode should have a single dereference and one immediate value + if(!v.valid || !v.found_deref || v.num_imm != 1) { + return false; + } + + // That value should be 0x10. + auto result = v.value; + if(result.defined && result.convert() == 0x10) { + return true; + } + } + + return false; + } +} + +namespace ppc { + bool isSystemCall(di::Instruction const& ins) { + auto const id = ins.getOperation().getID(); + + // There is also a vectorized form (scv), but Dyninst can't decode it. + return id == power_op_sc; + } +} + +namespace aarch64 { + bool isSystemCall(di::Instruction const& ins) { + auto const id = ins.getOperation().getID(); + + return id == aarch64_op_svc; + } +} + +bool di::isSystemCall(Instruction const& ins) { + switch(ins.getArch()) { + case Arch_x86: + case Arch_x86_64: + return ::x86::isSystemCall(ins); + case Arch_ppc32: + case Arch_ppc64: + return ::ppc::isSystemCall(ins); + case Arch_aarch64: + return ::aarch64::isSystemCall(ins); + case Arch_none: + case Arch_aarch32: + case Arch_cuda: + case Arch_amdgpu_gfx908: + case Arch_amdgpu_gfx90a: + case Arch_amdgpu_gfx940: + case Arch_intelGen9: + return false; + } + return false; +} diff --git a/instructionAPI/src/test/test_aarch64_decoder.C b/instructionAPI/src/test/test_aarch64_decoder.C index d6fdde073d..70f1496d00 100644 --- a/instructionAPI/src/test/test_aarch64_decoder.C +++ b/instructionAPI/src/test/test_aarch64_decoder.C @@ -1,9 +1,9 @@ #include #include #include -#include +#include #include -using namespace boost::assign; +using namespace dyncompat::assign; #include "test_aarch64_decoder_table.h" using namespace std; diff --git a/instructionAPI/src/test/test_aarch64_decoder_table.h b/instructionAPI/src/test/test_aarch64_decoder_table.h index 3b9583afbc..072c4ab5f3 100644 --- a/instructionAPI/src/test/test_aarch64_decoder_table.h +++ b/instructionAPI/src/test/test_aarch64_decoder_table.h @@ -1,3 +1,6 @@ +#include +#include + struct aarch64_mask_entry; struct aarch64_insn_entry; diff --git a/parseAPI/CMakeLists.txt b/parseAPI/CMakeLists.txt index 41245da9af..c74b3123b0 100644 --- a/parseAPI/CMakeLists.txt +++ b/parseAPI/CMakeLists.txt @@ -1,140 +1,137 @@ -# CMake configuration for parseAPI directory - -include_directories ( - ${PROJECT_SOURCE_DIR}/parseAPI/src - ) - -set (SRC_LIST - src/ParserDetails.C - src/Parser.C - src/CFGFactory.C - src/Function.C - src/Block.C - src/CodeObject.C - src/debug_parse.C - src/CodeSource.C - src/ParseData.C - src/InstructionAdapter.C - src/Parser-speculative.C - src/ParseCallback.C - src/IA_IAPI.C - src/IA_x86.C - src/IA_power.C - src/IA_aarch64.C +include_guard(GLOBAL) + +include(DyninstLibrary) + +set(SRC_LIST + src/ParserDetails.C + src/Parser.C + src/CFGFactory.C + src/Function.C + src/Block.C + src/CodeObject.C + src/debug_parse.C + src/CodeSource.C + src/ParseData.C + src/InstructionAdapter.C + src/Parser-speculative.C + src/ParseCallback.C + src/IA_IAPI.C + src/IA_x86.C + src/IA_power.C + src/IA_aarch64.C src/IA_amdgpu.C - src/CFGModifier.C - src/StackTamperVisitor.C - src/JumpTableFormatPred.C - src/JumpTableIndexPred.C - src/IndirectAnalyzer.C - src/IndirectASTVisitor.C - src/SymbolicExpression.C - src/BoundFactCalculator.C - src/BoundFactData.C - src/ThunkData.C - ../dataflowAPI/src/ABI.C - src/dominator.C - src/LoopAnalyzer.C - src/Loop.C - src/LoopTreeNode.C - src/IdiomModelDesc.C - src/ProbabilisticParser.C - ) + src/CFGModifier.C + src/StackTamperVisitor.C + src/JumpTableFormatPred.C + src/JumpTableIndexPred.C + src/IndirectAnalyzer.C + src/IndirectASTVisitor.C + src/SymbolicExpression.C + src/BoundFactCalculator.C + src/BoundFactData.C + src/ThunkData.C + src/dominator.C + src/LoopAnalyzer.C + src/Loop.C + src/LoopTreeNode.C + src/IdiomModelDesc.C + src/ProbabilisticParser.C) + +set(DATAFLOW_SRC + ${PROJECT_SOURCE_DIR}/dataflowAPI/src/ABI.C + ${PROJECT_SOURCE_DIR}/dataflowAPI/src/Absloc.C + ${PROJECT_SOURCE_DIR}/dataflowAPI/src/AbslocInterface.C + ${PROJECT_SOURCE_DIR}/dataflowAPI/src/convertOpcodes.C + ${PROJECT_SOURCE_DIR}/dataflowAPI/src/debug_dataflow.C + ${PROJECT_SOURCE_DIR}/dataflowAPI/src/ExpressionConversionVisitor.C + ${PROJECT_SOURCE_DIR}/dataflowAPI/src/InstructionCache.C + ${PROJECT_SOURCE_DIR}/dataflowAPI/src/liveness.C + ${PROJECT_SOURCE_DIR}/dataflowAPI/src/RegisterMap.C + ${PROJECT_SOURCE_DIR}/dataflowAPI/src/RoseImpl.C + ${PROJECT_SOURCE_DIR}/dataflowAPI/src/RoseInsnFactory.C + ${PROJECT_SOURCE_DIR}/dataflowAPI/src/slicing.C + ${PROJECT_SOURCE_DIR}/dataflowAPI/src/stackanalysis.C + ${PROJECT_SOURCE_DIR}/dataflowAPI/src/SymbolicExpansion.C + ${PROJECT_SOURCE_DIR}/dataflowAPI/src/SymEval.C + ${PROJECT_SOURCE_DIR}/dataflowAPI/src/SymEvalPolicy.C + ${PROJECT_SOURCE_DIR}/dataflowAPI/src/Visitors.C) set(ROSE_SRC - ../dataflowAPI/src/ABI.C - ../dataflowAPI/src/Absloc.C - ../dataflowAPI/src/AbslocInterface.C - ../dataflowAPI/src/convertOpcodes.C - ../dataflowAPI/src/debug_dataflow.C - ../dataflowAPI/src/ExpressionConversionVisitor.C - ../dataflowAPI/src/InstructionCache.C - ../dataflowAPI/src/liveness.C - ../dataflowAPI/src/RegisterMap.C - ../dataflowAPI/src/RoseImpl.C - ../dataflowAPI/src/RoseInsnFactory.C - ../dataflowAPI/src/slicing.C - ../dataflowAPI/src/stackanalysis.C - ../dataflowAPI/src/SymbolicExpansion.C - ../dataflowAPI/src/SymEval.C - ../dataflowAPI/src/SymEvalPolicy.C - ../dataflowAPI/src/templates.C - ../dataflowAPI/src/Visitors.C - ../dataflowAPI/rose/ExtentMap.C - ../dataflowAPI/rose/rangemap.C - ../dataflowAPI/rose/util/Assert.C - ../dataflowAPI/rose/util/Message.C - ../dataflowAPI/rose/util/Sawyer.C - ../dataflowAPI/rose/util/Synchronization.C - ../dataflowAPI/rose/util/rose_getline.C - ../dataflowAPI/rose/util/SmallObject.C - ../dataflowAPI/rose/util/Stopwatch.C - ../dataflowAPI/rose/util/StringUtility.C - ../dataflowAPI/rose/util/Attribute.C - ../dataflowAPI/rose/util/Combinatorics.C - ../dataflowAPI/rose/util/LinearCongruentialGenerator.C - ../dataflowAPI/rose/semantics/BaseSemantics2.C - ../dataflowAPI/rose/semantics/DispatcherARM64.C - ../dataflowAPI/rose/semantics/DispatcherAmdgpuVega.C - ../dataflowAPI/rose/semantics/DispatcherPowerpc.C - ../dataflowAPI/rose/semantics/RegisterParts.C - ../dataflowAPI/rose/semantics/Registers.C - ../dataflowAPI/rose/semantics/BinarySymbolicExpr.C - ../dataflowAPI/rose/semantics/RegisterStateGeneric.C - ../dataflowAPI/rose/semantics/SymEvalSemantics.C -) + ${PROJECT_SOURCE_DIR}/dataflowAPI/rose/ExtentMap.C + ${PROJECT_SOURCE_DIR}/dataflowAPI/rose/rangemap.C + ${PROJECT_SOURCE_DIR}/dataflowAPI/rose/util/Assert.C + ${PROJECT_SOURCE_DIR}/dataflowAPI/rose/util/Message.C + ${PROJECT_SOURCE_DIR}/dataflowAPI/rose/util/Sawyer.C + ${PROJECT_SOURCE_DIR}/dataflowAPI/rose/util/Synchronization.C + ${PROJECT_SOURCE_DIR}/dataflowAPI/rose/util/rose_getline.C + ${PROJECT_SOURCE_DIR}/dataflowAPI/rose/util/SmallObject.C + ${PROJECT_SOURCE_DIR}/dataflowAPI/rose/util/Stopwatch.C + ${PROJECT_SOURCE_DIR}/dataflowAPI/rose/util/StringUtility.C + ${PROJECT_SOURCE_DIR}/dataflowAPI/rose/util/Attribute.C + ${PROJECT_SOURCE_DIR}/dataflowAPI/rose/util/Combinatorics.C + ${PROJECT_SOURCE_DIR}/dataflowAPI/rose/util/LinearCongruentialGenerator.C + ${PROJECT_SOURCE_DIR}/dataflowAPI/rose/semantics/BaseSemantics2.C + ${PROJECT_SOURCE_DIR}/dataflowAPI/rose/semantics/DispatcherARM64.C + ${PROJECT_SOURCE_DIR}/dataflowAPI/rose/semantics/DispatcherAMDGPU.C + ${PROJECT_SOURCE_DIR}/dataflowAPI/rose/semantics/DispatcherPowerpc.C + ${PROJECT_SOURCE_DIR}/dataflowAPI/rose/semantics/RegisterParts.C + ${PROJECT_SOURCE_DIR}/dataflowAPI/rose/semantics/Registers.C + ${PROJECT_SOURCE_DIR}/dataflowAPI/rose/semantics/BinarySymbolicExpr.C + ${PROJECT_SOURCE_DIR}/dataflowAPI/rose/semantics/RegisterStateGeneric.C + ${PROJECT_SOURCE_DIR}/dataflowAPI/rose/semantics/SymEvalSemantics.C) # FIXME: Rose needs a bunch of warning cleanup -SET_SOURCE_FILES_PROPERTIES(${ROSE_SRC} PROPERTIES LANGUAGE CXX COMPILE_FLAGS -w) -set (SRC_LIST ${SRC_LIST} - ${ROSE_SRC} -) +set_source_files_properties(${ROSE_SRC} PROPERTIES LANGUAGE CXX COMPILE_FLAGS -w) +set(SRC_LIST ${SRC_LIST} ${DATAFLOW_SRC} ${ROSE_SRC}) -if (LIGHTWEIGHT_SYMTAB) -set (SRC_LIST ${SRC_LIST} - src/SymLiteCodeSource.C -) +if(LIGHTWEIGHT_SYMTAB) + list(APPEND SRC_LIST src/SymLiteCodeSource.C) else() -set (SRC_LIST ${SRC_LIST} - src/SymtabCodeSource.C -) + list(APPEND SRC_LIST src/SymtabCodeSource.C) endif() -if (ENABLE_PARSE_API_GRAPHS) -set (SRC_LIST ${SRC_LIST} - src/GraphAdapter.C - ) +file(GLOB parseapi_headers "h/*.h") +file(GLOB dataflowapi_headers "${PROJECT_SOURCE_DIR}/dataflowAPI/h/*.h") + +if(ENABLE_PARSE_API_GRAPHS) + list(APPEND SRC_LIST src/GraphAdapter.C) endif() +# cmake-format: off +dyninst_library( + parseAPI + PRIVATE_HEADER_FILES ${parseapi_headers} ${dataflowapi_headers} + SOURCE_FILES ${SRC_LIST} ${ROSE_SRC} + DEFINES PARSER_LIB DATAFLOW_LIB + DYNINST_DEPS common instructionAPI ${SYMREADER} + PUBLIC_DEPS + PRIVATE_DEPS OpenMP::OpenMP_CXX +) +# cmake-format: on -ADD_DEFINITIONS(-DPARSER_LIB) -ADD_DEFINITIONS(-DDATAFLOW_LIB) -if(WIN32) -ADD_DEFINITIONS(-DROSE_UTIL_EXPORTS) -ADD_DEFINITIONS(-DNOMINMAX) -endif() -dyninst_library(parseAPI common instructionAPI ${SYMREADER}) +foreach(t ${parseAPI_TARGETS}) + # There is both a common/h/util.h and a parseAPI/h/util.h, so put + # the common/h include path first + target_include_directories(${t} BEFORE + PRIVATE "$") -target_link_private_libraries(parseAPI ${Boost_LIBRARIES} ${TBB_LIBRARIES} tbbmalloc) + target_include_directories( + ${t} PUBLIC "$") -if (WIN32) -target_link_private_libraries(parseAPI shlwapi) -endif() -message(STATUS "Architecture is: ${CMAKE_LIBRARY_ARCHITECTURE}") -FILE (GLOB headers "h/*.h") -FILE (GLOB dataflowheaders "../dataflowAPI/h/*.h") -set_target_properties (parseAPI PROPERTIES PUBLIC_HEADER "${headers};${dataflowheaders}") + set_property(TARGET ${t} PROPERTY PUBLIC_HEADER ${parseapi_headers} + ${dataflowapi_headers}) -if (USE_OpenMP) -set_target_properties (parseAPI PROPERTIES COMPILE_FLAGS ${OpenMP_CXX_FLAGS} LINK_FLAGS ${OpenMP_CXX_FLAGS}) -endif() + if(DYNINST_OS_Windows) + target_compile_definitions(${t} PRIVATE "ROSE_UTIL_EXPORTS" "NOMINMAX") + target_link_libraries(parseAPI PRIVATE shlwapi) + endif() -if(${ENABLE_STATIC_LIBS}) - set_target_properties (parseAPI_static PROPERTIES PUBLIC_HEADER "${headers};${dataflowheaders}") -endif() + install(TARGETS ${t} PUBLIC_HEADER DESTINATION ${DYNINST_INSTALL_INCLUDEDIR}) + + # When using symlite, we still need the symtabAPI headers + if(LIGHTWEIGHT_SYMTAB) + target_include_directories( + ${t} PUBLIC "$") + endif() -install (TARGETS parseAPI - RUNTIME DESTINATION ${INSTALL_LIB_DIR} - LIBRARY DESTINATION ${INSTALL_LIB_DIR} - ARCHIVE DESTINATION ${INSTALL_LIB_DIR} - PUBLIC_HEADER DESTINATION ${INSTALL_INCLUDE_DIR}) +endforeach() diff --git a/parseAPI/doc/API/CodeObject.tex b/parseAPI/doc/API/CodeObject.tex index 52325cfa54..bf885c88c8 100644 --- a/parseAPI/doc/API/CodeObject.tex +++ b/parseAPI/doc/API/CodeObject.tex @@ -92,6 +92,15 @@ \subsection{Class CodeObject} \end{apient} \apidesc{Speculatively parse the indicated region of the binary using the specified technique to find likely function entry points, enabled on the x86 and x86-64 platforms.} +\fbox{\begin{minipage}[t]{1\columnwidth}% +\begin{center}{\textbf{A note on using the lookup functions}}\end{center} +When parsing binary objects such as .o files and static libraries which may have multiple +\texttt{CodeRegion} objects that overlap in the address space, the \texttt{CodeRegion} argument +\textit{must} be passed. For executable binaries and shared libraries that are fully linked, there +is no ambiguity, and {\scshape null} can be passed. The only exception is \texttt{findFuncsByBlock} +which always requires a valid \texttt{CodeRegion}.% +\end{minipage}} + \begin{apient} Function * findFuncByEntry(CodeRegion * cr, Address entry) diff --git a/parseAPI/doc/API/Function.tex b/parseAPI/doc/API/Function.tex index ae438dc66a..8ac41174b9 100644 --- a/parseAPI/doc/API/Function.tex +++ b/parseAPI/doc/API/Function.tex @@ -106,7 +106,7 @@ \subsection{Class Function} \begin{apient} Block* getImmediateDominator(Block *A); \end{apient} -\apidesc{Return the immediate dominator of block \code{A}，\code{NULL} if the block \code{A} does not have an immediate dominator.} +\apidesc{Return the immediate dominator of block \code{A}, \code{NULL} if the block \code{A} does not have an immediate dominator.} \begin{apient} void getImmediateDominates(Block *A, set &imm); @@ -127,7 +127,7 @@ \subsection{Class Function} \begin{apient} Block* getImmediatePostDominator(Block *A); \end{apient} -\apidesc{Return the immediate post-dominator of block \code{A}，\code{NULL} if the block \code{A} does not have an immediate post-dominator.} +\apidesc{Return the immediate post-dominator of block \code{A}, \code{NULL} if the block \code{A} does not have an immediate post-dominator.} \begin{apient} void getImmediatePostDominates(Block *A, set &imm); diff --git a/parseAPI/doc/code_sample.cc b/parseAPI/doc/code_sample.cc index 60b8dcf46f..3b4c2b9fd2 100644 --- a/parseAPI/doc/code_sample.cc +++ b/parseAPI/doc/code_sample.cc @@ -66,7 +66,7 @@ int main(int argc, char **argv){ fbl--; Block *b = *fbl; Address lastAddr = b->last(); - //if current function has zero instructions, don’t output it + //if current function has zero instructions, don't output it if(crtAddr == lastAddr) continue; cout << "\n\n\"" << f->name() << "\" :"; diff --git a/parseAPI/doc/example.cc b/parseAPI/doc/example.cc index eb5051f9d4..aae2b870ff 100644 --- a/parseAPI/doc/example.cc +++ b/parseAPI/doc/example.cc @@ -4,6 +4,7 @@ // Improvements by E. Robbins (er209 at kent dot ac dot uk) // +#include #include #include #include diff --git a/parseAPI/doc/parseAPI.pdf b/parseAPI/doc/parseAPI.pdf index a388bdaa19..c1643e4add 100644 Binary files a/parseAPI/doc/parseAPI.pdf and b/parseAPI/doc/parseAPI.pdf differ diff --git a/parseAPI/h/CFG.h b/parseAPI/h/CFG.h index f2ea37463c..3ccdcba5a2 100644 --- a/parseAPI/h/CFG.h +++ b/parseAPI/h/CFG.h @@ -30,14 +30,18 @@ #ifndef _PARSER_CFG_H_ #define _PARSER_CFG_H_ +#include +#include +#include +#include #include #include #include #include #include -#include -#include -#include +#include +#include +#include #include "dyntypes.h" #include "IBSTree.h" @@ -45,18 +49,19 @@ #include "ParseContainers.h" #include "Annotatable.h" #include "DynAST.h" +#include "CodeSource.h" #include -#include -#include -#include +#include +#include +#include #include namespace Dyninst { namespace InstructionAPI { class Instruction; - typedef boost::shared_ptr InstructionPtr; + typedef dyncompat::shared_ptr InstructionPtr; } namespace ParseAPI { @@ -89,7 +94,7 @@ class PARSER_EXPORT Edge { friend class CFGModifier; friend class Block; protected: - boost::atomic _source; + dyncompat::atomic _source; Block * _target; ParseData* index; Offset _target_off; @@ -97,14 +102,6 @@ class PARSER_EXPORT Edge { private: -#if defined(_MSC_VER) - typedef unsigned __int16 uint16_t; - typedef unsigned __int8 uint8_t; -#else - typedef unsigned short uint16_t; - typedef unsigned char uint8_t; -#endif - struct EdgeType { EdgeType(EdgeTypeEnum t, bool s) : _type_enum(t), _sink(s), _interproc(false) @@ -162,6 +159,8 @@ class PARSER_EXPORT EdgePredicate { public: virtual bool pred_impl(Edge *) const; + EdgePredicate() = default; + EdgePredicate(const EdgePredicate&) = default; virtual ~EdgePredicate() = default; bool operator()(Edge* e) const { @@ -234,7 +233,7 @@ class CodeRegion; class PARSER_EXPORT Block : public Dyninst::SimpleInterval, - public boost::lockable_adapter { + public dyncompat::lockable_adapter { friend class CFGModifier; friend class Parser; public: @@ -254,7 +253,6 @@ class PARSER_EXPORT Block : Address end, Address last, Function* f = NULL); virtual ~Block(); - boost::recursive_mutex& lockable() { return boost::lockable_adapter::lockable(); } inline Address start() const { return _start; } inline Address end() const { return _end; } @@ -271,15 +269,11 @@ class PARSER_EXPORT Block : /* Edge access */ const edgelist & sources() const { return _srclist; } const edgelist & targets() const { return _trglist; } - void copy_sources(edgelist & src) { - boost::lock_guard g(*this); - src = _srclist; - } - void copy_targets(edgelist & trg) { - boost::lock_guard g(*this); - trg = _trglist; - } + void copy_sources(edgelist & src) const; + void copy_targets(edgelist & trg) const; + bool hasCallSource() const; + Edge* getOnlyIncomingEdge() const; bool consistent(Address addr, Address & prev_insn); int containingFuncs() const; @@ -339,7 +333,7 @@ class PARSER_EXPORT Block : edgelist _srclist; edgelist _trglist; - boost::atomic _func_cnt; + dyncompat::atomic _func_cnt; bool _parsed; Function * _createdByFunc; @@ -382,7 +376,7 @@ class FuncExtent; class Loop; class LoopTreeNode; -class PARSER_EXPORT Function : public AnnotatableSparse, public boost::lockable_adapter { +class PARSER_EXPORT Function : public AnnotatableSparse, public dyncompat::lockable_adapter { friend class CFGModifier; friend class LoopAnalyzer; protected: @@ -393,7 +387,7 @@ class PARSER_EXPORT Function : public AnnotatableSparse, public boost::lockable_ bool _cache_valid; FuncSource _src; - boost::atomic _rs; + dyncompat::atomic _rs; std::string _name; Block * _entry; @@ -429,17 +423,17 @@ class PARSER_EXPORT Function : public AnnotatableSparse, public boost::lockable_ typedef select2nd selector; - typedef boost::transform_iterator bmap_iterator; - typedef boost::transform_iterator bmap_const_iterator; - typedef boost::iterator_range blocklist; - typedef boost::iterator_range const_blocklist; + typedef dyncompat::transform_iterator bmap_iterator; + typedef dyncompat::transform_iterator bmap_const_iterator; + typedef dyncompat::iterator_range blocklist; + typedef dyncompat::iterator_range const_blocklist; typedef std::set edgelist; Function(Address addr, std::string name, CodeObject * obj, CodeRegion * region, InstructionSource * isource); virtual ~Function(); - boost::recursive_mutex& lockable() { return boost::lockable_adapter::lockable(); } + dyncompat::recursive_mutex& lockable() { return dyncompat::lockable_adapter::lockable(); } virtual const std::string & name() const; void rename(std::string n) { _name = n; } @@ -461,7 +455,7 @@ class PARSER_EXPORT Function : public AnnotatableSparse, public boost::lockable_ const_blocklist blocks() const; size_t num_blocks() { - boost::lock_guard g(*this); + dyncompat::lock_guard g(*this); if(!_cache_valid) finalize(); return _bmap.size(); } @@ -515,14 +509,71 @@ class PARSER_EXPORT Function : public AnnotatableSparse, public boost::lockable_ struct less { + /** + * If there are more than one guest binary file loaded, multiple + * functions may have the same entry point address in different + * code regions. And regions themselves may use the same + * address ranges. + * + * We order functions by their regions first, by their address second. + * + * We order regions by their start first, by their end second, + * by the numeric value of their pointers third. We consider NULL + * to be less than any non-NULL region. + * + * The algorithm below is the same as ordering with per-component + * comparison vectors + * + * ( Region::low(), Region::high(), Region::ptr, Function::addr(), Function::ptr ) + * + * where low() and high() for NULL region are considered to be -INF. + * + * For typical shared libraries and executables this should order + * functions by their address. For static libraries it should group + * functions by their object files and order object files by their + * size. + */ bool operator()(const Function * f1, const Function * f2) const { - if (f1->region() < f2->region()) return true; - else if (f1->region() == f2->region() && - f1->addr() < f2->addr()) { - return true; + CodeRegion *f1_region = f1->region(); + CodeRegion *f2_region = f2->region(); + + /** + * Same region or both regions are NULL => order by addr() + * For this case we need regions to be the same object, + * not just have the same parameters, thus pointer comparison. + */ + if (f1_region == f2_region) { + if (f1->addr() < f2->addr()) return true; + if (f1->addr() > f2->addr()) return false; + if (f1 == f2) return false; /* Compare to self */ + /* Same region, same address, different functions. + Realistically we should never get here, but just in case... */ + return uintptr_t(f1) < uintptr_t(f2); } - return false; + + /* Only one region can be NULL by this point */ + if (!f1_region) return true; + if (!f2_region) return false; + + if (f1_region->low() < f2_region->low()) return true; + if (f1_region->low() > f2_region->low()) return false; + + /** + * Two functions from different binaries with relocatable code + * (.o, DSO, PIE, etc.) can possibly have the same low(), + * high(), and addr(). + * + * Still, try ordering by high() first. + */ + if (f1_region->high() < f2_region->high()) return true; + if (f1_region->high() > f2_region->high()) return false; + + /** + * Corner case: different regions with the same address and the same size, + * probably from different files. Order by numeric value of their pointers. + */ + return uintptr_t(f1_region) < uintptr_t(f2_region); } }; diff --git a/parseAPI/h/CFGFactory.h b/parseAPI/h/CFGFactory.h index 49e6567421..1d3bdcc13b 100644 --- a/parseAPI/h/CFGFactory.h +++ b/parseAPI/h/CFGFactory.h @@ -30,6 +30,8 @@ #ifndef _CFG_FACTORY_H_ #define _CFG_FACTORY_H_ +#include + #include "dyntypes.h" #include "LockFreeQueue.h" diff --git a/parseAPI/h/CFGModifier.h b/parseAPI/h/CFGModifier.h index 803acae159..c425bb1c51 100644 --- a/parseAPI/h/CFGModifier.h +++ b/parseAPI/h/CFGModifier.h @@ -31,6 +31,7 @@ #ifndef _CFG_MODIFIER_H_ #define _CFG_MODIFIER_H_ +#include #include "dyntypes.h" // A collection of methods for user-triggered modification of a ParseAPI CFG. diff --git a/parseAPI/h/CodeObject.h b/parseAPI/h/CodeObject.h index ef972b3109..ab03f76740 100644 --- a/parseAPI/h/CodeObject.h +++ b/parseAPI/h/CodeObject.h @@ -31,6 +31,9 @@ #ifndef CODE_OBJECT_H #define CODE_OBJECT_H +#include +#include +#include #include #include "Symtab.h" diff --git a/parseAPI/h/CodeSource.h b/parseAPI/h/CodeSource.h index 1bd4034303..752794a7c0 100644 --- a/parseAPI/h/CodeSource.h +++ b/parseAPI/h/CodeSource.h @@ -30,6 +30,7 @@ #ifndef _CODE_SOURCE_H_ #define _CODE_SOURCE_H_ +#include #include #include #include @@ -41,8 +42,8 @@ #include "InstructionSource.h" -#include -#include +#include +#include #include "concurrent.h" class StatContainer; @@ -257,7 +258,7 @@ class PARSER_EXPORT SymtabCodeRegion : public CodeRegion { SymtabAPI::Region * symRegion() const { return _region; } }; -class PARSER_EXPORT SymtabCodeSource : public CodeSource, public boost::lockable_adapter { +class PARSER_EXPORT SymtabCodeSource : public CodeSource, public dyncompat::lockable_adapter { private: SymtabAPI::Symtab * _symtab; bool owns_symtab; @@ -286,7 +287,7 @@ class PARSER_EXPORT SymtabCodeSource : public CodeSource, public boost::lockable hint_filt *, bool allLoadedRegions=false); SymtabCodeSource(SymtabAPI::Symtab *); - SymtabCodeSource(char *); + SymtabCodeSource(const char *); ~SymtabCodeSource(); diff --git a/common/h/Display b/parseAPI/h/GraphAdapter.h similarity index 100% rename from common/h/Display rename to parseAPI/h/GraphAdapter.h diff --git a/parseAPI/h/InstructionAdapter.h b/parseAPI/h/InstructionAdapter.h index dfd0ae789c..28a0ec4985 100644 --- a/parseAPI/h/InstructionAdapter.h +++ b/parseAPI/h/InstructionAdapter.h @@ -31,6 +31,12 @@ #if !defined(INSTRUCTION_ADAPTER_H) #define INSTRUCTION_ADAPTER_H +#include +#include +#include +#include +#include + #include "dyntypes.h" #include "CodeObject.h" diff --git a/parseAPI/h/InstructionSource.h b/parseAPI/h/InstructionSource.h index 3fd8443a3d..b1d88c0022 100644 --- a/parseAPI/h/InstructionSource.h +++ b/parseAPI/h/InstructionSource.h @@ -33,7 +33,7 @@ #ifndef INSTRUCTION_SOURCE_H #define INSTRUCTION_SOURCE_H -#include "dyn_regs.h" +#include "Architecture.h" #include "dyntypes.h" namespace Dyninst { diff --git a/parseAPI/h/Location.h b/parseAPI/h/Location.h index 8c857e4894..81b8ea2ce4 100644 --- a/parseAPI/h/Location.h +++ b/parseAPI/h/Location.h @@ -39,6 +39,9 @@ #include "Instruction.h" #include +#include +#include +#include namespace Dyninst{ namespace ParseAPI{ @@ -157,10 +160,10 @@ Location(Edge *e) : func(NULL), block(NULL), offset(0), edge(e), untrusted(false for (Function::blocklist::iterator blockIter = blk.begin(); blockIter != blk.end(); ++blockIter){ Intraproc epred; const Block::edgelist& target_edges = (*blockIter) -> targets(); - if(std::find(boost::make_filter_iterator(epred, target_edges.begin(), target_edges.end()), - boost::make_filter_iterator(epred, target_edges.end(), target_edges.end()), + if(std::find(dyncompat::make_filter_iterator(epred, target_edges.begin(), target_edges.end()), + dyncompat::make_filter_iterator(epred, target_edges.end(), target_edges.end()), edge) - != boost::make_filter_iterator(epred, target_edges.end(), target_edges.end())) + != dyncompat::make_filter_iterator(epred, target_edges.end(), target_edges.end())) { return true; } diff --git a/parseAPI/h/LockFreeQueue.h b/parseAPI/h/LockFreeQueue.h index c566577533..e76d4ebb9f 100644 --- a/parseAPI/h/LockFreeQueue.h +++ b/parseAPI/h/LockFreeQueue.h @@ -30,8 +30,10 @@ #ifndef _LOCK_FREE_QUEUE_H_ #define _LOCK_FREE_QUEUE_H_ +#include +#include #include -#include +#include #define DEBUG_LOCKFREEQUEUE 0 @@ -85,7 +87,7 @@ class LockFreeQueueItem { return (item_type * const) ~0; } - boost::atomic _next; + dyncompat::atomic _next; T _value; LFQ_DEBUG(item_type *validate;) }; @@ -215,7 +217,7 @@ class LockFreeQueue { } private: - boost::atomic head; + dyncompat::atomic head; }; #endif diff --git a/parseAPI/h/ParseCallback.h b/parseAPI/h/ParseCallback.h index fd31d6eeda..7cd6c06617 100644 --- a/parseAPI/h/ParseCallback.h +++ b/parseAPI/h/ParseCallback.h @@ -38,6 +38,10 @@ during parsing. **/ +#include +#include +#include +#include #include "InstructionAdapter.h" #include "dyntypes.h" diff --git a/parseAPI/h/ParseContainers.h b/parseAPI/h/ParseContainers.h index cb035fec8f..db8980ee9b 100644 --- a/parseAPI/h/ParseContainers.h +++ b/parseAPI/h/ParseContainers.h @@ -30,9 +30,9 @@ #ifndef _ITERATORS_H_ #define _ITERATORS_H_ -#include -#include -#include +#include +#include +#include /* * An iterator and a predicate interface, and a * ContainerWrapper that can provide a forward @@ -93,8 +93,8 @@ template < public: - typedef boost::filter_iterator::type::iterator> iterator; - typedef boost::filter_iterator::type::const_iterator> const_iterator; + typedef dyncompat::filter_iterator::type::iterator> iterator; + typedef dyncompat::filter_iterator::type::const_iterator> const_iterator; PARSER_EXPORT ContainerWrapper(C & cont) : _m_container(cont) { } @@ -102,47 +102,47 @@ template < iterator begin() { - return boost::make_filter_iterator(_m_container.begin(), _m_container.end()); + return dyncompat::make_filter_iterator(_m_container.begin(), _m_container.end()); } template - boost::filter_iterator::type::iterator> + dyncompat::filter_iterator::type::iterator> begin(P * p) { - return boost::make_filter_iterator(*p, _m_container.begin(), _m_container.end()); + return dyncompat::make_filter_iterator(*p, _m_container.begin(), _m_container.end()); } iterator end() { - return boost::make_filter_iterator(_m_container.end(), _m_container.end()); + return dyncompat::make_filter_iterator(_m_container.end(), _m_container.end()); } template - boost::filter_iterator::type::iterator> + dyncompat::filter_iterator::type::iterator> end(P * p) { - return boost::make_filter_iterator<>(*p, _m_container.end(), _m_container.end()); + return dyncompat::make_filter_iterator<>(*p, _m_container.end(), _m_container.end()); } const_iterator begin() const { - return boost::make_filter_iterator(_m_container.begin(), _m_container.end()); + return dyncompat::make_filter_iterator(_m_container.begin(), _m_container.end()); } template - boost::filter_iterator::type::const_iterator> + dyncompat::filter_iterator::type::const_iterator> begin(P * p) const { - return boost::make_filter_iterator(*p, _m_container.begin(), _m_container.end()); + return dyncompat::make_filter_iterator(*p, _m_container.begin(), _m_container.end()); } const_iterator end() const { - return boost::make_filter_iterator(_m_container.end(), _m_container.end()); + return dyncompat::make_filter_iterator(_m_container.end(), _m_container.end()); } template - boost::filter_iterator::type::const_iterator> + dyncompat::filter_iterator::type::const_iterator> end(P * p) const { - return boost::make_filter_iterator(*p, _m_container.end(), _m_container.end()); + return dyncompat::make_filter_iterator(*p, _m_container.end(), _m_container.end()); } size_t size() const; diff --git a/parseAPI/h/SymLiteCodeSource.h b/parseAPI/h/SymLiteCodeSource.h index edcc5dd148..cd2b7668a4 100644 --- a/parseAPI/h/SymLiteCodeSource.h +++ b/parseAPI/h/SymLiteCodeSource.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 1996-2021 Barton P. Miller + * See the dyninst/COPYRIGHT file for copyright information. * * We provide the Paradyn Parallel Performance Tools (below * described as "Paradyn") on an AS IS basis, and do not warrant its @@ -58,23 +58,24 @@ class SymReaderCodeRegion : public CodeRegion { PARSER_EXPORT SymReaderCodeRegion(SymReader *, SymSegment *); PARSER_EXPORT ~SymReaderCodeRegion(); - PARSER_EXPORT void names(Address, std::vector &); - PARSER_EXPORT bool findCatchBlock(Address addr, Address & catchStart); + PARSER_EXPORT void names(Address, std::vector &) override; + PARSER_EXPORT bool findCatchBlock(Address addr, Address & catchStart) override; /** InstructionSource implementation **/ - PARSER_EXPORT bool isValidAddress(const Address) const; - PARSER_EXPORT void* getPtrToInstruction(const Address) const; - PARSER_EXPORT void* getPtrToData(const Address) const; - PARSER_EXPORT unsigned int getAddressWidth() const; - PARSER_EXPORT bool isCode(const Address) const; - PARSER_EXPORT bool isData(const Address) const; - PARSER_EXPORT Address offset() const; - PARSER_EXPORT Address length() const; - PARSER_EXPORT Architecture getArch() const; + PARSER_EXPORT bool isValidAddress(const Address) const override; + PARSER_EXPORT void* getPtrToInstruction(const Address) const override; + PARSER_EXPORT void* getPtrToData(const Address) const override; + PARSER_EXPORT unsigned int getAddressWidth() const override; + PARSER_EXPORT bool isCode(const Address) const override; + PARSER_EXPORT bool isData(const Address) const override; + PARSER_EXPORT bool isReadOnly(const Address) const override; + PARSER_EXPORT Address offset() const override; + PARSER_EXPORT Address length() const override; + PARSER_EXPORT Architecture getArch() const override; /** interval **/ - PARSER_EXPORT Address low() const { return offset(); } - PARSER_EXPORT Address high() const { return offset() + length(); } + PARSER_EXPORT Address low() const override { return offset(); } + PARSER_EXPORT Address high() const override { return offset() + length(); } PARSER_EXPORT SymSegment * symRegion() const { return _region; } }; @@ -109,6 +110,7 @@ class SymReaderCodeSource : public CodeSource { PARSER_EXPORT unsigned int getAddressWidth() const; PARSER_EXPORT bool isCode(const Address) const; PARSER_EXPORT bool isData(const Address) const; + PARSER_EXPORT bool isReadOnly(const Address) const; PARSER_EXPORT Address offset() const; PARSER_EXPORT Address length() const; PARSER_EXPORT Architecture getArch() const; diff --git a/parseAPI/src/Block.C b/parseAPI/src/Block.C index 2e819dcbb9..06e0c837ba 100644 --- a/parseAPI/src/Block.C +++ b/parseAPI/src/Block.C @@ -53,7 +53,8 @@ Block::Block(CodeObject * o, CodeRegion *r, Address start, Function *f) : _parsed(false), _createdByFunc(f) { - if (_obj && _obj->cs()) { + assert(_obj); + if (_obj->cs()) { _obj->cs()->incrementCounter(PARSE_BLOCK_COUNT); _obj->cs()->addCounter(PARSE_BLOCK_SIZE, size()); } @@ -76,15 +77,16 @@ Block::Block( _parsed(false), _createdByFunc(f) { + assert(_obj); } Block::~Block() { // nothing special - if (_obj && _obj->cs()) { + if (_obj->cs()) { _obj->cs()->decrementCounter(PARSE_BLOCK_COUNT); - _obj->cs()->addCounter(PARSE_BLOCK_SIZE, -1*size()); + _obj->cs()->addCounter(PARSE_BLOCK_SIZE, -static_cast(size())); } } @@ -93,7 +95,7 @@ Block::consistent(Address addr, Address & prev_insn) { if (addr >= end() || addr < start()) return false; InstructionSource * isrc; - if(_obj && !_obj->cs()->regionsOverlap()) + if(!_obj->cs()->regionsOverlap()) isrc = _obj->cs(); else isrc = region(); @@ -118,7 +120,6 @@ Block::consistent(Address addr, Address & prev_insn) void Block::getFuncs(vector & funcs) { - if(!_obj) return; // universal sink set stab; _obj->findFuncsByBlock(region(),this,stab); set::iterator sit = stab.begin(); @@ -172,13 +173,13 @@ SingleContextOrInterproc::pred_impl(Edge * e) const } int Block::containingFuncs() const { - if(_obj) _obj->finalize(); + _obj->finalize(); return _func_cnt; } void Block::removeFunc(Function *) { - if ((0 == _func_cnt) && _obj) { + if (0 == _func_cnt) { _obj->finalize(); } assert(0 != _func_cnt); @@ -187,7 +188,6 @@ void Block::removeFunc(Function *) void Block::updateEnd(Address addr) { - if(!_obj) return; _obj->cs()->addCounter(PARSE_BLOCK_SIZE, -1*size()); _end = addr; high_ = addr; @@ -285,8 +285,8 @@ Block::getInsn(Offset a) const { bool Block::operator==(const Block &rhs) const { - boost::lock_guard g1(*this); - boost::lock_guard g2(rhs); + dyncompat::lock_guard g1(*this); + dyncompat::lock_guard g2(rhs); // All sinks are equal if(_start == std::numeric_limits
::max()) { return rhs._start == _start; @@ -308,13 +308,13 @@ bool Block::operator!=(const Block &rhs) const { void Block::addSource(Edge * e) { - boost::lock_guard g(*this); + dyncompat::lock_guard g(*this); _srclist.insert(e); } void Block::addTarget(Edge * e) { - boost::lock_guard g(*this); + dyncompat::lock_guard g(*this); if(e->type() == FALLTHROUGH || e->type() == COND_NOT_TAKEN) { @@ -327,19 +327,19 @@ void Block::addTarget(Edge * e) void Block::removeTarget(Edge * e) { if (e == NULL) return; - boost::lock_guard g(*this); + dyncompat::lock_guard g(*this); _trglist.erase(e); } void Block::removeSource(Edge * e) { if (e == NULL) return; - boost::lock_guard g(*this); + dyncompat::lock_guard g(*this); _srclist.erase(e); } void Block::moveTargetEdges(Block* B) { if (this == B) return; - boost::lock_guard g(*this); + dyncompat::lock_guard g(*this); Block* A = this; /* We move outgoing edges from this block to block B, which is * necessary when spliting blocks. @@ -356,3 +356,26 @@ void Block::moveTargetEdges(Block* B) { } trgs.clear(); } + +void Block::copy_sources(edgelist & src) const { + dyncompat::lock_guard g(lockable()); + src = _srclist; +} + +void Block::copy_targets(edgelist & trg) const { + dyncompat::lock_guard g(lockable()); + trg = _trglist; +} + +bool Block::hasCallSource() const { + dyncompat::lock_guard g(lockable()); + for (auto e: _srclist) + if (e->type() == CALL) + return true; + return false; +} + +Edge* Block::getOnlyIncomingEdge() const { + dyncompat::lock_guard g(lockable()); + return _srclist.size() == 1 ? *_srclist.begin() : nullptr; +} diff --git a/parseAPI/src/BoundFactCalculator.C b/parseAPI/src/BoundFactCalculator.C index 312976ee01..bdb3cd1840 100644 --- a/parseAPI/src/BoundFactCalculator.C +++ b/parseAPI/src/BoundFactCalculator.C @@ -1,12 +1,13 @@ +#include #include "dyntypes.h" #include "CodeObject.h" #include "CodeSource.h" - #include "BoundFactCalculator.h" #include "IndirectASTVisitor.h" #include "debug_parse.h" #include "Instruction.h" #include "JumpTableIndexPred.h" +#include "registers/x86_64_regs.h" using namespace Dyninst::InstructionAPI; void BoundFactsCalculator::NaturalDFS(Node::Ptr cur) { @@ -96,7 +97,7 @@ void BoundFactsCalculator::DetermineAnalysisOrder() { if (curNodes.size() == 1) { // If the SCC has only one node, // we connect the virtual entry to this single node - SliceNode::Ptr node = boost::static_pointer_cast(*(curNodes.begin())); + SliceNode::Ptr node = dyncompat::static_pointer_cast(*(curNodes.begin())); slice->insertPair(virtualEntry, node, TypedSliceEdge::create(virtualEntry, node, FALLTHROUGH)); } else { // If there are more than one node in this SCC, @@ -108,7 +109,7 @@ void BoundFactsCalculator::DetermineAnalysisOrder() { set visit; map >targetMap; for (auto nit = curNodes.begin(); nit != curNodes.end(); ++nit) { - SliceNode::Ptr node = boost::static_pointer_cast(*nit); + SliceNode::Ptr node = dyncompat::static_pointer_cast(*nit); ParseAPI::Block * b = node->block(); Address addr = node->addr(); if (targetMap.find(b) == targetMap.end()) { @@ -196,7 +197,7 @@ bool BoundFactsCalculator::CalculateBoundedFacts() { workingList.pop(); inQueue.erase(curNode); - SliceNode::Ptr node = boost::static_pointer_cast(curNode); + SliceNode::Ptr node = dyncompat::static_pointer_cast(curNode); ++inQueueLimit[curNode]; if (inQueueLimit[curNode] > IN_QUEUE_LIMIT) continue; @@ -259,12 +260,12 @@ bool BoundFactsCalculator::CalculateBoundedFacts() { static bool IsConditionalJump(Instruction insn) { entryID id = insn.getOperation().getID(); - if (id == e_jz || id == e_jnz || - id == e_jb || id == e_jnb || - id == e_jbe || id == e_jnbe || + if (id == e_je || id == e_jne || + id == e_jb || id == e_jae || + id == e_jbe || id == e_ja || id == e_jb_jnaej_j || id == e_jnb_jae_j || id == e_jle || id == e_jl || - id == e_jnl || id == e_jnle) return true; + id == e_jge || id == e_jg) return true; if (id == aarch64_op_b_cond) return true; if (id == power_op_bc || id == power_op_bcctr || id == power_op_bclr) return true; return false; @@ -272,7 +273,7 @@ static bool IsConditionalJump(Instruction insn) { BoundFact* BoundFactsCalculator::Meet(Node::Ptr curNode) { - SliceNode::Ptr node = boost::static_pointer_cast(curNode); + SliceNode::Ptr node = dyncompat::static_pointer_cast(curNode); EdgeIterator gbegin, gend; curNode->ins(gbegin, gend); @@ -280,8 +281,8 @@ BoundFact* BoundFactsCalculator::Meet(Node::Ptr curNode) { bool first = true; for (; gbegin != gend; ++gbegin) { - TypedSliceEdge::Ptr edge = boost::static_pointer_cast(*gbegin); - SliceNode::Ptr srcNode = boost::static_pointer_cast(edge->source()); + TypedSliceEdge::Ptr edge = dyncompat::static_pointer_cast(*gbegin); + SliceNode::Ptr srcNode = dyncompat::static_pointer_cast(edge->source()); BoundFact *prevFact = GetBoundFactOut(srcNode); bool newCopy = false; if (prevFact == NULL) { @@ -341,7 +342,7 @@ BoundFact* BoundFactsCalculator::Meet(Node::Ptr curNode) { } void BoundFactsCalculator::CalcTransferFunction(Node::Ptr curNode, BoundFact *newFact){ - SliceNode::Ptr node = boost::static_pointer_cast(curNode); + SliceNode::Ptr node = dyncompat::static_pointer_cast(curNode); if (!node->assign()) return; if (node->assign() && node->assign()->out().absloc().type() == Absloc::Register && @@ -438,7 +439,7 @@ void BoundFactsCalculator::CalcTransferFunction(Node::Ptr curNode, BoundFact *ne if (id == e_push) { if (calculation->getID() == AST::V_ConstantAST) { - ConstantAST::Ptr c = boost::static_pointer_cast(calculation); + ConstantAST::Ptr c = dyncompat::static_pointer_cast(calculation); newFact->PushAConst(c->val().val); parsing_printf("\t\t\tCalculating transfer function: Output facts\n"); newFact->Print(); @@ -455,7 +456,7 @@ void BoundFactsCalculator::CalcTransferFunction(Node::Ptr curNode, BoundFact *ne } // Assume all SETxx entry ids are contiguous - if (id >= e_setb && id <= e_setz) { + if (id >= e_setb && id <= e_sete) { newFact->GenFact(outAST, new StridedInterval(1,0,1), false); parsing_printf("\t\t\tCalculating transfer function: Output facts\n"); newFact->Print(); diff --git a/parseAPI/src/BoundFactCalculator.h b/parseAPI/src/BoundFactCalculator.h index 4b53caeb7a..b3b53e6347 100644 --- a/parseAPI/src/BoundFactCalculator.h +++ b/parseAPI/src/BoundFactCalculator.h @@ -7,6 +7,7 @@ #include "SymbolicExpression.h" #include "slicing.h" +#include #include #include diff --git a/parseAPI/src/BoundFactData.C b/parseAPI/src/BoundFactData.C index 3723c8bbfa..f8428064e4 100644 --- a/parseAPI/src/BoundFactData.C +++ b/parseAPI/src/BoundFactData.C @@ -1,3 +1,4 @@ +#include #include "dyntypes.h" #include "BoundFactData.h" #include "debug_parse.h" @@ -506,8 +507,8 @@ void BoundFact::KillFact(const AST::Ptr ast, bool isConditionalJump) { for (auto rit = relation.begin(); rit != relation.end();) { // If the one of them is changed, // we no longer know their relationship - if (*((*rit)->left) == *ast || *((*rit)->right) == *ast) { - if (*rit != NULL) delete *rit; + if (*((*rit)->left) == *ast || *((*rit)->right) == *ast) { + delete *rit; rit = relation.erase(rit); } else ++rit; } @@ -582,7 +583,7 @@ bool BoundFact::ConditionalJumpBound(Instruction insn, EdgeTypeEnum type) { if (type == COND_TAKEN) { switch (id) { // unsigned - case e_jnbe: { + case e_ja: { if (pred.e1->getID() == AST::V_ConstantAST) { if (pred.e2->getID() == AST::V_ConstantAST) { // If both elements are constant, @@ -590,29 +591,29 @@ bool BoundFact::ConditionalJumpBound(Instruction insn, EdgeTypeEnum type) { // It is possible to happen, but should be unlikely parsing_printf("WARNING: both predicate elements are constants!\n"); } else { - ConstantAST::Ptr constAST = boost::static_pointer_cast(pred.e1); + ConstantAST::Ptr constAST = dyncompat::static_pointer_cast(pred.e1); IntersectInterval(pred.e1, StridedInterval(1, 0, constAST->val().val - 1)); } } else if (pred.e2->getID() == AST::V_ConstantAST) { - ConstantAST::Ptr constAST = boost::static_pointer_cast(pred.e2); + ConstantAST::Ptr constAST = dyncompat::static_pointer_cast(pred.e2); IntersectInterval(pred.e1, StridedInterval(1, constAST->val().val + 1, StridedInterval::maxValue)); } else { InsertRelation(pred.e1, pred.e2,UnsignedLargerThan); } break; } - case e_jnb: + case e_jae: case e_jnb_jae_j: { if (pred.e1->getID() == AST::V_ConstantAST) { if (pred.e2->getID() == AST::V_ConstantAST) { parsing_printf("WARNING: both predicate elements are constants!\n"); } else { - ConstantAST::Ptr constAST = boost::static_pointer_cast(pred.e1); + ConstantAST::Ptr constAST = dyncompat::static_pointer_cast(pred.e1); parsing_printf("XXX\n"); IntersectInterval(pred.e2, StridedInterval(1, 0, constAST->val().val)); } } else if (pred.e2->getID() == AST::V_ConstantAST) { - ConstantAST::Ptr constAST = boost::static_pointer_cast(pred.e2); + ConstantAST::Ptr constAST = dyncompat::static_pointer_cast(pred.e2); parsing_printf("YYY\n"); IntersectInterval(pred.e1, StridedInterval(1, constAST->val().val, StridedInterval::maxValue)); } else { @@ -626,11 +627,11 @@ bool BoundFact::ConditionalJumpBound(Instruction insn, EdgeTypeEnum type) { if (pred.e2->getID() == AST::V_ConstantAST) { parsing_printf("WARNING: both predicate elements are constants!\n"); } else { - ConstantAST::Ptr constAST = boost::static_pointer_cast(pred.e1); + ConstantAST::Ptr constAST = dyncompat::static_pointer_cast(pred.e1); IntersectInterval(pred.e2, StridedInterval(1, constAST->val().val + 1, StridedInterval::maxValue)); } } else if (pred.e2->getID() == AST::V_ConstantAST) { - ConstantAST::Ptr constAST = boost::static_pointer_cast(pred.e2); + ConstantAST::Ptr constAST = dyncompat::static_pointer_cast(pred.e2); // Assuming a-loc pred.e1 is always used as // unsigned value before it gets rewritten. IntersectInterval(pred.e1, StridedInterval(1, 0 , constAST->val().val - 1)); @@ -646,11 +647,11 @@ bool BoundFact::ConditionalJumpBound(Instruction insn, EdgeTypeEnum type) { if (pred.e2->getID() == AST::V_ConstantAST) { parsing_printf("WARNING: both predicate elements are constants!\n"); } else { - ConstantAST::Ptr constAST = boost::static_pointer_cast(pred.e1); + ConstantAST::Ptr constAST = dyncompat::static_pointer_cast(pred.e1); IntersectInterval(pred.e2, StridedInterval(1, constAST->val().val, StridedInterval::maxValue)); } } else if (pred.e2->getID() == AST::V_ConstantAST) { - ConstantAST::Ptr constAST = boost::static_pointer_cast(pred.e2); + ConstantAST::Ptr constAST = dyncompat::static_pointer_cast(pred.e2); // Assuming a-loc pred.e1 is always used as // unsigned value before it gets rewritten. IntersectInterval(pred.e1,StridedInterval(1, 0 , constAST->val().val)); @@ -659,7 +660,7 @@ bool BoundFact::ConditionalJumpBound(Instruction insn, EdgeTypeEnum type) { } break; } - case e_jz: { + case e_je: { if (pred.e1->getID() == AST::V_ConstantAST) { if (pred.e2->getID() == AST::V_ConstantAST) { parsing_printf("WARNING: both predicate elements are constants!\n"); @@ -678,16 +679,16 @@ bool BoundFact::ConditionalJumpBound(Instruction insn, EdgeTypeEnum type) { } break; } - case e_jnz: { + case e_jne: { if (pred.e1->getID() == AST::V_ConstantAST) { if (pred.e2->getID() == AST::V_ConstantAST) { parsing_printf("WARNING: both predicate elements are constants!\n"); } else { - ConstantAST::Ptr constAST = boost::static_pointer_cast(pred.e1); + ConstantAST::Ptr constAST = dyncompat::static_pointer_cast(pred.e1); DeleteElementFromInterval(pred.e2, constAST->val().val); } } else if (pred.e2->getID() == AST::V_ConstantAST) { - ConstantAST::Ptr constAST = boost::static_pointer_cast(pred.e2); + ConstantAST::Ptr constAST = dyncompat::static_pointer_cast(pred.e2); DeleteElementFromInterval(pred.e1, constAST->val().val); } else { InsertRelation(pred.e1, pred.e2, NotEqual); @@ -696,32 +697,32 @@ bool BoundFact::ConditionalJumpBound(Instruction insn, EdgeTypeEnum type) { } // signed - case e_jnle: { + case e_jg: { if (pred.e1->getID() == AST::V_ConstantAST) { if (pred.e2->getID() == AST::V_ConstantAST) { parsing_printf("WARNING: both predicate elements are constants!\n"); } else { - ConstantAST::Ptr constAST = boost::static_pointer_cast(pred.e1); + ConstantAST::Ptr constAST = dyncompat::static_pointer_cast(pred.e1); IntersectInterval(pred.e2, StridedInterval(1, 0 , constAST->val().val - 1)); } } else if (pred.e2->getID() == AST::V_ConstantAST) { - ConstantAST::Ptr constAST = boost::static_pointer_cast(pred.e2); + ConstantAST::Ptr constAST = dyncompat::static_pointer_cast(pred.e2); IntersectInterval(pred.e1, StridedInterval(1, constAST->val().val + 1, StridedInterval::maxValue)); } else { InsertRelation(pred.e1, pred.e2, SignedLargerThan); } break; } - case e_jnl: { + case e_jge: { if (pred.e1->getID() == AST::V_ConstantAST) { if (pred.e2->getID() == AST::V_ConstantAST) { parsing_printf("WARNING: both predicate elements are constants!\n"); } else { - ConstantAST::Ptr constAST = boost::static_pointer_cast(pred.e1); + ConstantAST::Ptr constAST = dyncompat::static_pointer_cast(pred.e1); IntersectInterval(pred.e2, StridedInterval(1, 0, constAST->val().val)); } } else if (pred.e2->getID() == AST::V_ConstantAST) { - ConstantAST::Ptr constAST = boost::static_pointer_cast(pred.e2); + ConstantAST::Ptr constAST = dyncompat::static_pointer_cast(pred.e2); IntersectInterval(pred.e1, StridedInterval(1, constAST->val().val, StridedInterval::maxValue)); } else { InsertRelation(pred.e1, pred.e2,SignedLargerThanOrEqual); @@ -733,11 +734,11 @@ bool BoundFact::ConditionalJumpBound(Instruction insn, EdgeTypeEnum type) { if (pred.e2->getID() == AST::V_ConstantAST) { parsing_printf("WARNING: both predicate elements are constants!\n"); } else { - ConstantAST::Ptr constAST = boost::static_pointer_cast(pred.e1); + ConstantAST::Ptr constAST = dyncompat::static_pointer_cast(pred.e1); IntersectInterval(pred.e2, StridedInterval(1, constAST->val().val + 1, StridedInterval::maxValue)); } } else if (pred.e2->getID() == AST::V_ConstantAST) { - ConstantAST::Ptr constAST = boost::static_pointer_cast(pred.e2); + ConstantAST::Ptr constAST = dyncompat::static_pointer_cast(pred.e2); IntersectInterval(pred.e1, StridedInterval(1, 0 , constAST->val().val - 1)); } else { InsertRelation(pred.e1, pred.e2,SignedLessThan); @@ -750,11 +751,11 @@ bool BoundFact::ConditionalJumpBound(Instruction insn, EdgeTypeEnum type) { if (pred.e2->getID() == AST::V_ConstantAST) { parsing_printf("WARNING: both predicate elements are constants!\n"); } else { - ConstantAST::Ptr constAST = boost::static_pointer_cast(pred.e1); + ConstantAST::Ptr constAST = dyncompat::static_pointer_cast(pred.e1); IntersectInterval(pred.e2, StridedInterval(1, constAST->val().val, StridedInterval::maxValue)); } } else if (pred.e2->getID() == AST::V_ConstantAST) { - ConstantAST::Ptr constAST = boost::static_pointer_cast(pred.e2); + ConstantAST::Ptr constAST = dyncompat::static_pointer_cast(pred.e2); IntersectInterval(pred.e1, StridedInterval(1, 0 , constAST->val().val)); } else { InsertRelation(pred.e1, pred.e2,SignedLessThanOrEqual); @@ -780,11 +781,11 @@ bool BoundFact::ConditionalJumpBound(Instruction insn, EdgeTypeEnum type) { // It is possible to happen, but should be unlikely parsing_printf("WARNING: both predicate elements are constants!\n"); } else { - ConstantAST::Ptr constAST = boost::static_pointer_cast(pred.e1); + ConstantAST::Ptr constAST = dyncompat::static_pointer_cast(pred.e1); IntersectInterval(pred.e2, StridedInterval(1, 0, constAST->val().val - 1)); } } else if (pred.e2->getID() == AST::V_ConstantAST) { - ConstantAST::Ptr constAST = boost::static_pointer_cast(pred.e2); + ConstantAST::Ptr constAST = dyncompat::static_pointer_cast(pred.e2); IntersectInterval(pred.e1, StridedInterval(1, constAST->val().val + 1, StridedInterval::maxValue)); } else { InsertRelation(pred.e1, pred.e2,UnsignedLargerThan); @@ -797,29 +798,29 @@ bool BoundFact::ConditionalJumpBound(Instruction insn, EdgeTypeEnum type) { if (pred.e2->getID() == AST::V_ConstantAST) { parsing_printf("WARNING: both predicate elements are constants!\n"); } else { - ConstantAST::Ptr constAST = boost::static_pointer_cast(pred.e1); + ConstantAST::Ptr constAST = dyncompat::static_pointer_cast(pred.e1); IntersectInterval(pred.e2,StridedInterval(1, 0, constAST->val().val)); } } else if (pred.e2->getID() == AST::V_ConstantAST) { - ConstantAST::Ptr constAST = boost::static_pointer_cast(pred.e2); + ConstantAST::Ptr constAST = dyncompat::static_pointer_cast(pred.e2); IntersectInterval(pred.e1, StridedInterval(1, constAST->val().val, StridedInterval::maxValue)); } else { InsertRelation(pred.e1, pred.e2 ,UnsignedLargerThanOrEqual); } break; } - case e_jnb: + case e_jae: case e_jnb_jae_j: { if (pred.e1->getID() == AST::V_ConstantAST) { if (pred.e2->getID() == AST::V_ConstantAST) { parsing_printf("WARNING: both predicate elements are constants!\n"); } else { - ConstantAST::Ptr constAST = boost::static_pointer_cast(pred.e1); + ConstantAST::Ptr constAST = dyncompat::static_pointer_cast(pred.e1); parsing_printf("!!!\n"); IntersectInterval(pred.e2, StridedInterval(1, constAST->val().val + 1, StridedInterval::maxValue)); } } else if (pred.e2->getID() == AST::V_ConstantAST) { - ConstantAST::Ptr constAST = boost::static_pointer_cast(pred.e2); + ConstantAST::Ptr constAST = dyncompat::static_pointer_cast(pred.e2); // Assuming a-loc pred.e1 is always used as // unsigned value before it gets rewritten. parsing_printf("@@@\n"); @@ -831,16 +832,16 @@ bool BoundFact::ConditionalJumpBound(Instruction insn, EdgeTypeEnum type) { } case aarch64_op_b_cond: case power_op_bc: - case e_jnbe: { + case e_ja: { if (pred.e1->getID() == AST::V_ConstantAST) { if (pred.e2->getID() == AST::V_ConstantAST) { parsing_printf("WARNING: both predicate elements are constants!\n"); } else { - ConstantAST::Ptr constAST = boost::static_pointer_cast(pred.e1); + ConstantAST::Ptr constAST = dyncompat::static_pointer_cast(pred.e1); IntersectInterval(pred.e2, StridedInterval(1, constAST->val().val, StridedInterval::maxValue)); } } else if (pred.e2->getID() == AST::V_ConstantAST) { - ConstantAST::Ptr constAST = boost::static_pointer_cast(pred.e2); + ConstantAST::Ptr constAST = dyncompat::static_pointer_cast(pred.e2); // Assuming a-loc pred.e1 is always used as // unsigned value before it gets rewritten. IntersectInterval(pred.e1, StridedInterval(1, 0 , constAST->val().val)); @@ -849,7 +850,7 @@ bool BoundFact::ConditionalJumpBound(Instruction insn, EdgeTypeEnum type) { } break; } - case e_jnz: { + case e_jne: { if (pred.e1->getID() == AST::V_ConstantAST) { if (pred.e2->getID() == AST::V_ConstantAST) { parsing_printf("WARNING: both predicate elements are constants!\n"); @@ -858,7 +859,7 @@ bool BoundFact::ConditionalJumpBound(Instruction insn, EdgeTypeEnum type) { //IntersectInterval(pred.e2, StridedInterval(1, constAST->val().val, constAST->val().val)); } } else if (pred.e2->getID() == AST::V_ConstantAST) { - ConstantAST::Ptr constAST = boost::static_pointer_cast(pred.e2); + ConstantAST::Ptr constAST = dyncompat::static_pointer_cast(pred.e2); // the predicate sometimes is between the low 8 bits of a register // and a constant. If I simply extends the predicate to the whole // 64 bits of a register. I may get wrong constant value. @@ -870,16 +871,16 @@ bool BoundFact::ConditionalJumpBound(Instruction insn, EdgeTypeEnum type) { } break; } - case e_jz: { + case e_je: { if (pred.e1->getID() == AST::V_ConstantAST) { if (pred.e2->getID() == AST::V_ConstantAST) { parsing_printf("WARNING: both predicate elements are constants!\n"); } else { - ConstantAST::Ptr constAST = boost::static_pointer_cast(pred.e1); + ConstantAST::Ptr constAST = dyncompat::static_pointer_cast(pred.e1); DeleteElementFromInterval(pred.e2, constAST->val().val); } } else if (pred.e2->getID() == AST::V_ConstantAST) { - ConstantAST::Ptr constAST = boost::static_pointer_cast(pred.e2); + ConstantAST::Ptr constAST = dyncompat::static_pointer_cast(pred.e2); DeleteElementFromInterval(pred.e1, constAST->val().val); } else { InsertRelation(pred.e1, pred.e2,NotEqual); @@ -893,11 +894,11 @@ bool BoundFact::ConditionalJumpBound(Instruction insn, EdgeTypeEnum type) { if (pred.e2->getID() == AST::V_ConstantAST) { parsing_printf("WARNING: both predicate elements are constants!\n"); } else { - ConstantAST::Ptr constAST = boost::static_pointer_cast(pred.e1); + ConstantAST::Ptr constAST = dyncompat::static_pointer_cast(pred.e1); IntersectInterval(pred.e2, StridedInterval(1, 0, constAST->val().val - 1)); } } else if (pred.e2->getID() == AST::V_ConstantAST) { - ConstantAST::Ptr constAST = boost::static_pointer_cast(pred.e2); + ConstantAST::Ptr constAST = dyncompat::static_pointer_cast(pred.e2); IntersectInterval(pred.e1, StridedInterval(1, constAST->val().val + 1, StridedInterval::maxValue)); } else { InsertRelation(pred.e1, pred.e2, SignedLargerThan); @@ -909,27 +910,27 @@ bool BoundFact::ConditionalJumpBound(Instruction insn, EdgeTypeEnum type) { if (pred.e2->getID() == AST::V_ConstantAST) { parsing_printf("WARNING: both predicate elements are constants!\n"); } else { - ConstantAST::Ptr constAST = boost::static_pointer_cast(pred.e1); + ConstantAST::Ptr constAST = dyncompat::static_pointer_cast(pred.e1); IntersectInterval(pred.e2, StridedInterval(1, 0, constAST->val().val)); } } else if (pred.e2->getID() == AST::V_ConstantAST) { - ConstantAST::Ptr constAST = boost::static_pointer_cast(pred.e2); + ConstantAST::Ptr constAST = dyncompat::static_pointer_cast(pred.e2); IntersectInterval(pred.e1, StridedInterval(1, constAST->val().val, StridedInterval::maxValue)); } else { InsertRelation(pred.e1, pred.e2, SignedLargerThanOrEqual); } break; } - case e_jnl: { + case e_jge: { if (pred.e1->getID() == AST::V_ConstantAST) { if (pred.e2->getID() == AST::V_ConstantAST) { parsing_printf("WARNING: both predicate elements are constants!\n"); } else { - ConstantAST::Ptr constAST = boost::static_pointer_cast(pred.e1); + ConstantAST::Ptr constAST = dyncompat::static_pointer_cast(pred.e1); IntersectInterval(pred.e2, StridedInterval(1, constAST->val().val + 1, StridedInterval::maxValue)); } } else if (pred.e2->getID() == AST::V_ConstantAST) { - ConstantAST::Ptr constAST = boost::static_pointer_cast(pred.e2); + ConstantAST::Ptr constAST = dyncompat::static_pointer_cast(pred.e2); IntersectInterval(pred.e1, StridedInterval(1, 0 , constAST->val().val - 1)); } else { InsertRelation(pred.e1, pred.e2,SignedLessThan); @@ -937,16 +938,16 @@ bool BoundFact::ConditionalJumpBound(Instruction insn, EdgeTypeEnum type) { break; } - case e_jnle: { + case e_jg: { if (pred.e1->getID() == AST::V_ConstantAST) { if (pred.e2->getID() == AST::V_ConstantAST) { parsing_printf("WARNING: both predicate elements are constants!\n"); } else { -// ConstantAST::Ptr constAST = boost::static_pointer_cast(pred.e1); +// ConstantAST::Ptr constAST = dyncompat::static_pointer_cast(pred.e1); // IntersectInterval(pred.e2, StridedInterval(1, constAST->val().val, StridedInterval::maxValue)); } } else if (pred.e2->getID() == AST::V_ConstantAST) { - ConstantAST::Ptr constAST = boost::static_pointer_cast(pred.e2); + ConstantAST::Ptr constAST = dyncompat::static_pointer_cast(pred.e2); IntersectInterval(pred.e1, StridedInterval(1, 0 , constAST->val().val)); } else { InsertRelation(pred.e1, pred.e2,SignedLessThanOrEqual); @@ -968,13 +969,13 @@ bool BoundFact::ConditionalJumpBound(Instruction insn, EdgeTypeEnum type) { if (pred.e2->getID() == AST::V_ConstantAST) { StridedInterval *val = GetBound(pred.e1); if (val != NULL) { - ConstantAST::Ptr constAST = boost::static_pointer_cast(pred.e2); + ConstantAST::Ptr constAST = dyncompat::static_pointer_cast(pred.e2); val->Sub(StridedInterval(constAST->val().val)); } } else if (pred.e1->getID() == AST::V_ConstantAST) { StridedInterval *val = GetBound(pred.e2); if (val != NULL) { - ConstantAST::Ptr constAST = boost::static_pointer_cast(pred.e1); + ConstantAST::Ptr constAST = dyncompat::static_pointer_cast(pred.e1); val->Sub(StridedInterval(constAST->val().val)); } @@ -1005,10 +1006,10 @@ void BoundFact::SetPredicate(Assignment::Ptr assign,std::pair ex switch (id) { case e_test: { if (simplifiedAST->getID() == AST::V_RoseAST) { - RoseAST::Ptr rootRoseAST = boost::static_pointer_cast(simplifiedAST); + RoseAST::Ptr rootRoseAST = dyncompat::static_pointer_cast(simplifiedAST); if (rootRoseAST->val().op == ROSEOperation::equalToZeroOp && rootRoseAST->child(0)->getID() == AST::V_RoseAST) { - RoseAST::Ptr childAST = boost::static_pointer_cast(rootRoseAST->child(0)); + RoseAST::Ptr childAST = dyncompat::static_pointer_cast(rootRoseAST->child(0)); if (childAST->val().op == ROSEOperation::andOp) { if (*childAST->child(0) == *childAST->child(1)) { pred.e1 = childAST->child(0); @@ -1027,16 +1028,16 @@ void BoundFact::SetPredicate(Assignment::Ptr assign,std::pair ex } case e_and: { if (simplifiedAST->getID() == AST::V_RoseAST) { - RoseAST::Ptr rootRoseAST = boost::static_pointer_cast(simplifiedAST); + RoseAST::Ptr rootRoseAST = dyncompat::static_pointer_cast(simplifiedAST); if (rootRoseAST->val().op == ROSEOperation::equalToZeroOp && rootRoseAST->child(0)->getID() == AST::V_RoseAST) { - RoseAST::Ptr childAST = boost::static_pointer_cast(rootRoseAST->child(0)); + RoseAST::Ptr childAST = dyncompat::static_pointer_cast(rootRoseAST->child(0)); if (childAST->val().op == ROSEOperation::andOp) { // The effect of the and instruction can be // evaluated now. And the predicate is actually // simply comparing value to 0 if (childAST->child(1)->getID() == AST::V_ConstantAST) { - ConstantAST::Ptr constAST = boost::static_pointer_cast(childAST->child(1)); + ConstantAST::Ptr constAST = dyncompat::static_pointer_cast(childAST->child(1)); StridedInterval si(1,0,constAST->val().val); IntersectInterval(childAST->child(0), si); pred.e1 = childAST->child(0); @@ -1044,7 +1045,7 @@ void BoundFact::SetPredicate(Assignment::Ptr assign,std::pair ex pred.id = id; break; } else if (childAST->child(0)->getID() == AST::V_ConstantAST){ - ConstantAST::Ptr constAST = boost::static_pointer_cast(childAST->child(0)); + ConstantAST::Ptr constAST = dyncompat::static_pointer_cast(childAST->child(0)); StridedInterval si(1,0,constAST->val().val); IntersectInterval(childAST->child(1), si); pred.e1 = ConstantAST::create(Constant(0)); @@ -1177,10 +1178,10 @@ void BoundFact::AdjustPredicate(AST::Ptr out, AST::Ptr in) { if (*out == *pred.e1 && pred.e2->getID() == AST::V_ConstantAST) { parsing_printf("\t\t\t Adjust predicate\n"); if (in->getID() == AST::V_RoseAST) { - RoseAST::Ptr root = boost::static_pointer_cast(in); + RoseAST::Ptr root = dyncompat::static_pointer_cast(in); if (root->val().op == ROSEOperation::addOp && *pred.e1 == *(root->child(0)) && in->child(1)->getID() == AST::V_ConstantAST) { - ConstantAST::Ptr v1 = boost::static_pointer_cast(pred.e2); - ConstantAST::Ptr v2 = boost::static_pointer_cast(in->child(1)); + ConstantAST::Ptr v1 = dyncompat::static_pointer_cast(pred.e2); + ConstantAST::Ptr v2 = dyncompat::static_pointer_cast(in->child(1)); uint64_t newV = v1->val().val + v2->val().val; if (v1->val().size != 64) newV = newV & ((1ULL << v1->val().size) - 1); @@ -1191,10 +1192,10 @@ void BoundFact::AdjustPredicate(AST::Ptr out, AST::Ptr in) { } else if (*out == *pred.e2 && pred.e1->getID() == AST::V_ConstantAST) { parsing_printf("\t\t\t Adjust predicate\n"); if (in->getID() == AST::V_RoseAST) { - RoseAST::Ptr root = boost::static_pointer_cast(in); + RoseAST::Ptr root = dyncompat::static_pointer_cast(in); if (root->val().op == ROSEOperation::addOp && *pred.e2 == *(root->child(0)) && in->child(1)->getID() == AST::V_ConstantAST) { - ConstantAST::Ptr v1 = boost::static_pointer_cast(pred.e1); - ConstantAST::Ptr v2 = boost::static_pointer_cast(in->child(1)); + ConstantAST::Ptr v1 = dyncompat::static_pointer_cast(pred.e1); + ConstantAST::Ptr v2 = dyncompat::static_pointer_cast(in->child(1)); uint64_t newV = v1->val().val + v2->val().val; if (v1->val().size != 64) newV = newV & ((1ULL << v1->val().size) - 1); @@ -1254,20 +1255,20 @@ StridedInterval * BoundFact::ApplyRelations(AST::Ptr outAST) { } parsing_printf("\t\tApply relations to %s\n", cal->format().c_str()); if (cal->getID() != AST::V_RoseAST) return NULL; - RoseAST::Ptr root = boost::static_pointer_cast(cal); + RoseAST::Ptr root = dyncompat::static_pointer_cast(cal); if (root->val().op != ROSEOperation::addOp) return NULL; if (root->child(0)->getID() != AST::V_RoseAST || root->child(1)->getID() != AST::V_RoseAST) return NULL; - RoseAST::Ptr leftChild = boost::static_pointer_cast(root->child(0)); - RoseAST::Ptr rightChild = boost::static_pointer_cast(root->child(1)); + RoseAST::Ptr leftChild = dyncompat::static_pointer_cast(root->child(0)); + RoseAST::Ptr rightChild = dyncompat::static_pointer_cast(root->child(1)); if (leftChild->val().op != ROSEOperation::addOp || rightChild->val().op != ROSEOperation::addOp) return NULL; AST::Ptr leftOp = leftChild->child(0); if (leftChild->child(1)->getID() != AST::V_ConstantAST) return NULL; - ConstantAST::Ptr baseAST = boost::static_pointer_cast(leftChild->child(1)); + ConstantAST::Ptr baseAST = dyncompat::static_pointer_cast(leftChild->child(1)); int64_t baseValue = baseAST->val().val; if (rightChild->child(0)->getID() != AST::V_RoseAST || rightChild->child(1)->getID() != AST::V_ConstantAST) return NULL; - RoseAST::Ptr invertAST = boost::static_pointer_cast(rightChild->child(0)); + RoseAST::Ptr invertAST = dyncompat::static_pointer_cast(rightChild->child(0)); if (invertAST->val().op != ROSEOperation::invertOp) return NULL; - ConstantAST::Ptr subAST = boost::static_pointer_cast(rightChild->child(1)); + ConstantAST::Ptr subAST = dyncompat::static_pointer_cast(rightChild->child(1)); if (subAST->val().val != 1) return NULL; AST::Ptr rightOp = invertAST->child(0); bool matched = false; @@ -1293,28 +1294,28 @@ StridedInterval * BoundFact::ApplyRelations2(AST::Ptr outAST) { } parsing_printf("\t\tApply relations2 to %s\n", cal->format().c_str()); if (cal->getID() != AST::V_RoseAST) return NULL; - RoseAST::Ptr root = boost::static_pointer_cast(cal); + RoseAST::Ptr root = dyncompat::static_pointer_cast(cal); if (root->val().op != ROSEOperation::addOp) return NULL; if (root->child(0)->getID() != AST::V_VariableAST || root->child(1)->getID() != AST::V_RoseAST) return NULL; - VariableAST::Ptr leftChild = boost::static_pointer_cast(root->child(0)); - RoseAST::Ptr rightChild = boost::static_pointer_cast(root->child(1)); + VariableAST::Ptr leftChild = dyncompat::static_pointer_cast(root->child(0)); + RoseAST::Ptr rightChild = dyncompat::static_pointer_cast(root->child(1)); if (rightChild->val().op != ROSEOperation::addOp) return NULL; if (rightChild->child(0)->getID() != AST::V_RoseAST || rightChild->child(1)->getID() != AST::V_ConstantAST) return NULL; - RoseAST::Ptr invertAST = boost::static_pointer_cast(rightChild->child(0)); + RoseAST::Ptr invertAST = dyncompat::static_pointer_cast(rightChild->child(0)); if (invertAST->val().op != ROSEOperation::invertOp) return NULL; - ConstantAST::Ptr subAST = boost::static_pointer_cast(rightChild->child(1)); + ConstantAST::Ptr subAST = dyncompat::static_pointer_cast(rightChild->child(1)); if (subAST->val().val != 1) return NULL; if (invertAST->child(0)->getID() != AST::V_RoseAST) return NULL; - RoseAST::Ptr shlAST = boost::static_pointer_cast(invertAST->child(0)); + RoseAST::Ptr shlAST = dyncompat::static_pointer_cast(invertAST->child(0)); if (shlAST->val().op != ROSEOperation::shiftLOp) return NULL; - ConstantAST::Ptr shlBit = boost::static_pointer_cast(shlAST->child(1)); + ConstantAST::Ptr shlBit = dyncompat::static_pointer_cast(shlAST->child(1)); if (shlAST->child(0)->getID() != AST::V_RoseAST) return NULL; - RoseAST::Ptr shrAST = boost::static_pointer_cast(shlAST->child(0)); + RoseAST::Ptr shrAST = dyncompat::static_pointer_cast(shlAST->child(0)); if (shrAST->val().op != ROSEOperation::shiftROp) return NULL; - ConstantAST::Ptr shrBit = boost::static_pointer_cast(shrAST->child(1)); + ConstantAST::Ptr shrBit = dyncompat::static_pointer_cast(shrAST->child(1)); if (shrBit->val().val != shlBit->val().val) return NULL; if (shrAST->child(0)->getID() != AST::V_VariableAST) return NULL; - VariableAST::Ptr leftChild2 = boost::static_pointer_cast(shrAST->child(0)); + VariableAST::Ptr leftChild2 = dyncompat::static_pointer_cast(shrAST->child(0)); if (leftChild->val().reg != leftChild2->val().reg) return NULL; return new StridedInterval(StridedInterval(1,0,(1 << shlBit->val().val)-1)); } diff --git a/parseAPI/src/BoundFactData.h b/parseAPI/src/BoundFactData.h index 5eed634ebc..5e0b392b13 100644 --- a/parseAPI/src/BoundFactData.h +++ b/parseAPI/src/BoundFactData.h @@ -10,6 +10,10 @@ #include "entryIDs.h" #include +#include +#include +#include +#include using namespace std; using namespace Dyninst; using namespace Dyninst::ParseAPI; @@ -157,7 +161,7 @@ struct BoundFact { } pred; struct StackTop { - int64_t value; + int64_t value{}; bool valid; StackTop(): valid(false) {} diff --git a/parseAPI/src/CFGFactory.C b/parseAPI/src/CFGFactory.C index e734071072..31c6405ddd 100644 --- a/parseAPI/src/CFGFactory.C +++ b/parseAPI/src/CFGFactory.C @@ -169,7 +169,7 @@ CFGFactory::mkedge(Block * src, Block * trg, EdgeTypeEnum type) { } void CFGFactory::destroy_func(Function *f) { - free_func(f); + CFGFactory::free_func(f); } void @@ -179,7 +179,7 @@ CFGFactory::free_func(Function *f) { void CFGFactory::destroy_block(Block *b) { - free_block(b); + CFGFactory::free_block(b); } void @@ -202,7 +202,7 @@ std::string to_str(EdgeState e) void CFGFactory::destroy_edge(Edge *e, Dyninst::ParseAPI::EdgeState reason) { if(reason == destroyed_all) { - free_edge(e); + CFGFactory::free_edge(e); } } diff --git a/parseAPI/src/CFGModifier.C b/parseAPI/src/CFGModifier.C index a005d12875..df7408c5a0 100644 --- a/parseAPI/src/CFGModifier.C +++ b/parseAPI/src/CFGModifier.C @@ -28,6 +28,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include "ParseData.h" #include "CFGModifier.h" @@ -67,7 +68,7 @@ bool CFGModifier::redirect(Edge *edge, Block *target) { // if the source block has a sink edge of the same type, remove this edge bool hasSink = false; if (linkToSink) { - boost::lock_guard g(*edge->src()); + dyncompat::lock_guard g(*edge->src()); const Block::edgelist & trgs = edge->src()->targets(); for (Block::edgelist::const_iterator titer = trgs.begin(); titer != trgs.end(); titer++) { if ((*titer)->sinkEdge() && (*titer)->type() == edge->type()) { diff --git a/parseAPI/src/CodeObject.C b/parseAPI/src/CodeObject.C index 5bd7ac5c65..6bbee37c51 100644 --- a/parseAPI/src/CodeObject.C +++ b/parseAPI/src/CodeObject.C @@ -258,7 +258,7 @@ CodeObject::parseNewEdges( vector & worklist ) // don't add edges that already exist // (this could happen because of shared code) bool edgeExists = false; - boost::lock_guard g(*worklist[idx].source); + dyncompat::lock_guard g(*worklist[idx].source); const Block::edgelist & existingTs = worklist[idx].source->targets(); for (Block::edgelist::const_iterator tit = existingTs.begin(); tit != existingTs.end(); @@ -281,7 +281,7 @@ CodeObject::parseNewEdges( vector & worklist ) fit != funcs.end(); fit++) { - boost::lock_guard blockGuard(*worklist[idx].source); + dyncompat::lock_guard blockGuard(*worklist[idx].source); const Block::edgelist & tedges = worklist[idx].source->targets(); for(Block::edgelist::const_iterator eit = tedges.begin(); eit != tedges.end(); diff --git a/parseAPI/src/CodeSource.C b/parseAPI/src/CodeSource.C index 8a519f48fa..d8c1f4f8ac 100644 --- a/parseAPI/src/CodeSource.C +++ b/parseAPI/src/CodeSource.C @@ -1,5 +1,5 @@ /* - * Copyright (c) 1996-2021 Barton P. Miller + * See the dyninst/COPYRIGHT file for copyright information. * * We provide the Paradyn Parallel Performance Tools (below * described as "Paradyn") on an AS IS basis, and do not warrant its @@ -28,10 +28,11 @@ * License along with this library; if not, write to the Free Software * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include #include #include -#include +#include #include "dyntypes.h" @@ -87,7 +88,7 @@ CodeSource::findRegions(Address addr, set & ret) const dyn_hash_map CodeSource::non_returning_funcs = - boost::assign::map_list_of + dyncompat::assign::map_list_of // libc-2.31.so from glibc 2.31 ("_Exit", true) ("__GI___assert_fail", true) @@ -226,13 +227,13 @@ CodeSource::non_returning_funcs = dyn_hash_map CodeSource::non_returning_syscalls_x86 = - boost::assign::map_list_of + dyncompat::assign::map_list_of (1 /*exit*/,true) (119 /*sigreturn*/, true); dyn_hash_map CodeSource::non_returning_syscalls_x86_64 = - boost::assign::map_list_of + dyncompat::assign::map_list_of (60 /*exit*/,true) (15 /*sigreturn*/, true); diff --git a/parseAPI/src/Function.C b/parseAPI/src/Function.C index af8e04bd02..ceba93f7df 100644 --- a/parseAPI/src/Function.C +++ b/parseAPI/src/Function.C @@ -48,7 +48,7 @@ #include "StackTamperVisitor.h" #include "common/src/dthread.h" -#include +#include using namespace std; @@ -138,7 +138,7 @@ Function::~Function() Function::blocklist Function::blocks() { - boost::lock_guard g(*this); + dyncompat::lock_guard g(*this); if(!_cache_valid) finalize(); return blocklist(blocks_begin(), blocks_end()); @@ -149,7 +149,7 @@ Function::blocks() Function::const_blocklist Function::blocks() const { - boost::lock_guard g(*this); + dyncompat::lock_guard g(*this); assert(_cache_valid); return const_blocklist(blocks_begin(), blocks_end()); @@ -158,7 +158,7 @@ Function::blocks() const const Function::edgelist & Function::callEdges() { - boost::lock_guard g(*this); + dyncompat::lock_guard g(*this); if(!_cache_valid) finalize(); return _call_edge_list; @@ -166,7 +166,7 @@ Function::callEdges() { Function::const_blocklist Function::returnBlocks() { - boost::lock_guard g(*this); + dyncompat::lock_guard g(*this); if (!_cache_valid) finalize(); return const_blocklist(ret_begin(), ret_end()); @@ -174,7 +174,7 @@ Function::returnBlocks() { Function::const_blocklist Function::exitBlocks() { - boost::lock_guard g(*this); + dyncompat::lock_guard g(*this); if (!_cache_valid) finalize(); return const_blocklist(exit_begin(), exit_end()); @@ -184,7 +184,7 @@ Function::exitBlocks() { Function::const_blocklist Function::exitBlocks() const { - boost::lock_guard g(*this); + dyncompat::lock_guard g(*this); assert(_cache_valid); return const_blocklist(exit_begin(), exit_end()); @@ -193,7 +193,7 @@ Function::exitBlocks() const { vector const& Function::extents() { - boost::lock_guard g(*this); + dyncompat::lock_guard g(*this); if(!_cache_valid) finalize(); return _extents; @@ -202,7 +202,7 @@ Function::extents() void Function::finalize() { - boost::lock_guard g(*this); + dyncompat::lock_guard g(*this); bool done; do { _extents.clear(); @@ -226,7 +226,7 @@ Function::finalize() Function::blocklist Function::blocks_int() { - boost::lock_guard g(*this); + dyncompat::lock_guard g(*this); if(_cache_valid || !_entry) return blocklist(blocks_begin(), blocks_end()); @@ -259,7 +259,7 @@ Function::blocks_int() bool exit_func = false; bool found_call = false; bool found_call_ft = false; - boost::lock_guard blockGuard(*cur); + dyncompat::lock_guard blockGuard(*cur); Block::edgelist targets; cur->copy_targets(targets); @@ -404,12 +404,12 @@ Function::blocks_int() void Function::delayed_link_return(CodeObject * o, Block * retblk) { - boost::lock_guard g(*this); + dyncompat::lock_guard g(*this); bool link_entry = false; Block::edgelist::const_iterator eit; dyn_hash_map linked; { - boost::lock_guard blockGuard(*retblk); + dyncompat::lock_guard blockGuard(*retblk); eit = retblk->targets().begin(); for( ; eit != retblk->targets().end(); ++eit) { Edge * e = *eit; @@ -418,7 +418,7 @@ Function::delayed_link_return(CodeObject * o, Block * retblk) } - boost::lock_guard g2(*_entry); + dyncompat::lock_guard g2(*_entry); eit = _entry->sources().begin(); for( ; eit != _entry->sources().end(); ++eit) { Edge * e = *eit; @@ -451,7 +451,7 @@ Function::delayed_link_return(CodeObject * o, Block * retblk) void Function::add_block(Block *b) { - boost::lock_guard g(*this); + dyncompat::lock_guard g(*this); b->_func_cnt.fetch_add(1); // block counts references _bmap[b->start()] = b; } @@ -465,7 +465,7 @@ Function::name() const bool Function::contains(Block *b) { - boost::lock_guard g(*this); + dyncompat::lock_guard g(*this); if (b == NULL) return false; if(!_cache_valid) finalize(); @@ -476,7 +476,7 @@ Function::contains(Block *b) bool Function::contains(Block *b) const { -// boost::lock_guard g(*this); +// dyncompat::lock_guard g(*this); if (b == NULL) return false; return HASHDEF(_bmap,b->start()); } @@ -484,7 +484,7 @@ Function::contains(Block *b) const void Function::setEntryBlock(Block *new_entry) { - boost::lock_guard g(*this); + dyncompat::lock_guard g(*this); obj()->parser->move_func(this, new_entry->start(), new_entry->region()); _region = new_entry->region(); _start = new_entry->start(); @@ -493,7 +493,7 @@ void Function::setEntryBlock(Block *new_entry) void Function::set_retstatus(FuncReturnStatus rs) { - boost::lock_guard g(*this); + dyncompat::lock_guard g(*this); // If this function is a known non-returning function, // we should ignore this result. // A exmaple is .Unwind_Resume, which is non-returning. @@ -536,7 +536,7 @@ void Function::set_retstatus(FuncReturnStatus rs) void Function::removeBlock(Block* dead) { - boost::lock_guard g(*this); + dyncompat::lock_guard g(*this); _cache_valid = false; // specify replacement entry prior to deleting entry block, unless // deleting all blocks @@ -548,7 +548,7 @@ Function::removeBlock(Block* dead) } // remove dead block from _retBL and _call_edge_list - boost::lock_guard g2(*dead); + dyncompat::lock_guard g2(*dead); const Block::edgelist & outs = dead->targets(); for (Block::edgelist::const_iterator oit = outs.begin(); outs.end() != oit; @@ -587,7 +587,7 @@ class ST_Predicates : public Slicer::Predicates {}; StackTamper Function::tampersStack(bool recalculate) { - boost::lock_guard g(*this); + dyncompat::lock_guard g(*this); using namespace SymbolicEvaluation; using namespace InstructionAPI; @@ -664,7 +664,7 @@ Function::tampersStack(bool recalculate) retnAddr, FILE__,__LINE__); continue; } - StackTamperVisitor vis(Absloc(-1 * isrc()->getAddressWidth(), 0, this)); + StackTamperVisitor vis(Absloc(-static_cast(isrc()->getAddressWidth()), 0, this)); Address curTamperAddr=0; StackTamper curtamper = vis.tampersStack(sliceAtRet, curTamperAddr); mal_printf("StackTamperVisitor for func at 0x%lx block[%lx %lx) w/ " @@ -711,7 +711,7 @@ void Function::destroy(Function *f) { } LoopTreeNode* Function::getLoopTree() const{ - boost::lock_guard g(*this); + dyncompat::lock_guard g(*this); if (_loop_root == NULL) { LoopAnalyzer la(this); la.createLoopHierarchy(); @@ -725,7 +725,7 @@ LoopTreeNode* Function::getLoopTree() const{ void Function::getLoopsByNestingLevel(vector& lbb, bool outerMostOnly) const { - boost::lock_guard g(*this); + dyncompat::lock_guard g(*this); if (_loop_analyzed == false) { LoopAnalyzer la(this); la.analyzeLoops(); @@ -748,7 +748,7 @@ void Function::getLoopsByNestingLevel(vector& lbb, bool Function::getLoops(vector& lbb) const { - boost::lock_guard g(*this); + dyncompat::lock_guard g(*this); getLoopsByNestingLevel(lbb, false); return true; } @@ -757,14 +757,14 @@ Function::getLoops(vector& lbb) const bool Function::getOuterLoops(vector& lbb) const { - boost::lock_guard g(*this); + dyncompat::lock_guard g(*this); getLoopsByNestingLevel(lbb, true); return true; } Loop *Function::findLoop(const char *name) const { - boost::lock_guard g(*this); + dyncompat::lock_guard g(*this); return getLoopTree()->findLoop(name); } @@ -778,7 +778,7 @@ Loop *Function::findLoop(const char *name) const //be called to process dominator related fields and methods. void Function::fillDominatorInfo() const { - boost::lock_guard g(*this); + dyncompat::lock_guard g(*this); if (!isDominatorInfoReady) { dominatorCFG domcfg(this); domcfg.calcDominators(); @@ -788,7 +788,7 @@ void Function::fillDominatorInfo() const void Function::fillPostDominatorInfo() const { - boost::lock_guard g(*this); + dyncompat::lock_guard g(*this); if (!isPostDominatorInfoReady) { dominatorCFG domcfg(this); domcfg.calcPostDominators(); @@ -797,7 +797,7 @@ void Function::fillPostDominatorInfo() const } bool Function::dominates(Block* A, Block *B) const { - boost::lock_guard g(*this); + dyncompat::lock_guard g(*this); if (A == NULL || B == NULL) return false; if (A == B) return true; @@ -811,20 +811,20 @@ bool Function::dominates(Block* A, Block *B) const { } Block* Function::getImmediateDominator(Block *A) const { - boost::lock_guard g(*this); + dyncompat::lock_guard g(*this); fillDominatorInfo(); return immediateDominator[A]; } void Function::getImmediateDominates(Block *A, set &imd) const { - boost::lock_guard g(*this); + dyncompat::lock_guard g(*this); fillDominatorInfo(); if (immediateDominates[A] != NULL) imd.insert(immediateDominates[A]->begin(), immediateDominates[A]->end()); } void Function::getAllDominates(Block *A, set &d) const { - boost::lock_guard g(*this); + dyncompat::lock_guard g(*this); fillDominatorInfo(); d.insert(A); if (immediateDominates[A] == NULL) return; @@ -834,7 +834,7 @@ void Function::getAllDominates(Block *A, set &d) const { } bool Function::postDominates(Block* A, Block *B) const { - boost::lock_guard g(*this); + dyncompat::lock_guard g(*this); if (A == NULL || B == NULL) return false; if (A == B) return true; @@ -848,20 +848,20 @@ bool Function::postDominates(Block* A, Block *B) const { } Block* Function::getImmediatePostDominator(Block *A) const { - boost::lock_guard g(*this); + dyncompat::lock_guard g(*this); fillPostDominatorInfo(); return immediatePostDominator[A]; } void Function::getImmediatePostDominates(Block *A, set &imd) const { - boost::lock_guard g(*this); + dyncompat::lock_guard g(*this); fillPostDominatorInfo(); if (immediatePostDominates[A] != NULL) imd.insert(immediatePostDominates[A]->begin(), immediatePostDominates[A]->end()); } void Function::getAllPostDominates(Block *A, set &d) const { - boost::lock_guard g(*this); + dyncompat::lock_guard g(*this); fillPostDominatorInfo(); d.insert(A); if (immediatePostDominates[A] == NULL) return; diff --git a/parseAPI/src/GraphAdapter.C b/parseAPI/src/GraphAdapter.C index 68d7acb230..e69de29bb2 100644 --- a/parseAPI/src/GraphAdapter.C +++ b/parseAPI/src/GraphAdapter.C @@ -1,162 +0,0 @@ -#include "../h/GraphAdapter.h" -#include -#include -#include -#include - -#if BOOST_VERSION > 104000 -#include -#else -#include -#endif - -#include - -#include - -using namespace Dyninst; -using namespace ParseAPI; -using namespace boost; -using namespace std; - -typedef graph_traits::vertex_descriptor Vertex; - -namespace boost -{ - template<> - struct property_map - { - typedef boost::associative_property_map< std::map::vertex_descriptor, int> > type; - typedef type const_type; - - }; -} - - -namespace Dyninst -{ - namespace ParseAPI - { - - - - - template - typename property_map::const_type get(PROPERTY, const Function& f) - { - typedef typename property_map::const_type prop_map; - typedef typename property_traits::value_type value_type; - typedef typename property_traits::key_type key_type; - static std::map m; - - typename property_map::const_type r(m); - return r; - } - - } -} - -bool contains(Block* b, Address a) -{ - return b && (b->start() <= a) && (a < b->end()); -} - - -std::string block_info(Block* b) -{ - std::stringstream s; - if(b) - { - s << "[" << b->start() << ", " << b->end() << ")"; - } - else - { - s << "(NULL)"; - } - return s.str(); -} - -template -OS& operator<<(OS& os, Block* b) -{ - os << block_info(b); - return os; -} - -struct print_vertex : public base_visitor -{ - typedef on_discover_vertex event_filter; - template - void operator()(Vertex v, Graph& g) - { - cout << v << endl; - } -}; - -template -std::string block_and_index(Block* b, IndexMap indexMap) -{ - std::stringstream s; - s << "Block " << get(indexMap, b) << ": " << block_info(b); - return s.str(); -} - -bool dominates(Function& f, Block* a, Block* b) -{ - graph_traits::vertex_iterator firstBlock, curBlock, lastBlock; - - - // Concept checks for testing - BOOST_CONCEPT_ASSERT((GraphConcept)); - BOOST_CONCEPT_ASSERT((IncidenceGraphConcept)); - BOOST_CONCEPT_ASSERT((VertexListGraphConcept)); - BOOST_CONCEPT_ASSERT((BidirectionalGraphConcept)); - BOOST_CONCEPT_ASSERT((MultiPassInputIteratorConcept::vertex_iterator>)); - - tie(firstBlock, lastBlock) = vertices(f); - vector domTreePredVector = vector(num_vertices(f), graph_traits::null_vertex()); - typedef property_map::type IndexMap; - typedef iterator_property_map::iterator, IndexMap> PredMap; - const IndexMap indexMap(get(vertex_index, f)); - graph_traits::vertex_iterator ui, ue; - int index = 0; - for(tie(ui, ue) = vertices(f); ui != ue; ++ui, ++index) - { - put(indexMap, *ui, index); - } - - - PredMap results(make_iterator_property_map(domTreePredVector.begin(), indexMap)); - - - lengauer_tarjan_dominator_tree(f, f.entry(), results); - - // now walk through the tree and find whether a dominates b - Vertex cur_idom = b; - do - { - Vertex next_idom = get(results, cur_idom); - cur_idom = next_idom; - } while(cur_idom != a && cur_idom != graph_traits::null_vertex()); - return cur_idom == a; -} - -bool dominates(Function& f, Address a, Address b) -{ - Function::blocklist::const_iterator found_a, found_b; - found_a = std::find_if(f.blocks().begin(), - f.blocks().end(), - boost::bind(contains, boost::placeholders::_1, a)); - found_b = std::find_if(f.blocks().begin(), - f.blocks().end(), - boost::bind(contains, boost::placeholders::_1, b)); - // If either address is not in f, - // then no dominator relationship - if(found_a == f.blocks().end()) return false; - if(found_b == f.blocks().end()) return false; - // If same block, go by address - if(found_a == found_b) return a < b; - // Check the blocks - return dominates(f, *found_a, *found_b); - -} diff --git a/parseAPI/src/IA_IAPI.C b/parseAPI/src/IA_IAPI.C index 5ffc9a6ed6..cab2bc40e3 100644 --- a/parseAPI/src/IA_IAPI.C +++ b/parseAPI/src/IA_IAPI.C @@ -28,24 +28,26 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include "common/src/vgannotations.h" #include "dyntypes.h" -#include "dyn_regs.h" +#include "registers/x86_regs.h" #include "IA_IAPI.h" #include "util.h" -#include "Register.h" #include "Dereference.h" #include "Immediate.h" #include "BinaryFunction.h" #include "debug_parse.h" #include "IndirectAnalyzer.h" #include "util.h" -#include "common/src/Types.h" #include "dyntypes.h" +#include "instructionAPI/h/syscalls.h" +#include "instructionAPI/h/interrupts.h" #include #include +#include "Register.h" #include "IA_x86.h" #include "IA_power.h" #include "IA_aarch64.h" @@ -120,9 +122,12 @@ IA_IAPI* IA_IAPI::makePlatformIA_IAPI(Architecture arch, return new IA_power(dec_, where_, o, r, isrc, curBlk_); case Arch_aarch64: return new IA_aarch64(dec_, where_, o, r, isrc, curBlk_); - case Arch_amdgpu_vega: + case Arch_amdgpu_gfx908: + case Arch_amdgpu_gfx90a: + case Arch_amdgpu_gfx940: return new IA_amdgpu(dec_, where_, o, r, isrc, curBlk_); + default: assert(!"unimplemented architecture"); } @@ -136,21 +141,25 @@ void IA_IAPI::initASTs() std::call_once(IA_IAPI::ptrInit, [&]{ if(framePtr.empty()) { - framePtr[Arch_x86] = RegisterAST::Ptr(new RegisterAST(MachRegister::getFramePointer(Arch_x86))); - framePtr[Arch_x86_64] = RegisterAST::Ptr(new RegisterAST(MachRegister::getFramePointer(Arch_x86_64))); - framePtr[Arch_ppc32] = RegisterAST::Ptr(new RegisterAST(MachRegister::getFramePointer(Arch_ppc32))); - framePtr[Arch_ppc64] = RegisterAST::Ptr(new RegisterAST(MachRegister::getFramePointer(Arch_ppc64))); - framePtr[Arch_aarch64] = RegisterAST::Ptr(new RegisterAST(MachRegister::getFramePointer(Arch_aarch64))); - framePtr[Arch_amdgpu_vega] = RegisterAST::Ptr(new RegisterAST(MachRegister::getFramePointer(Arch_amdgpu_vega))); + framePtr[Arch_x86] = RegisterAST::Ptr(new RegisterAST(MachRegister::getFramePointer(Arch_x86))); + framePtr[Arch_x86_64] = RegisterAST::Ptr(new RegisterAST(MachRegister::getFramePointer(Arch_x86_64))); + framePtr[Arch_ppc32] = RegisterAST::Ptr(new RegisterAST(MachRegister::getFramePointer(Arch_ppc32))); + framePtr[Arch_ppc64] = RegisterAST::Ptr(new RegisterAST(MachRegister::getFramePointer(Arch_ppc64))); + framePtr[Arch_aarch64] = RegisterAST::Ptr(new RegisterAST(MachRegister::getFramePointer(Arch_aarch64))); + framePtr[Arch_amdgpu_gfx908] = RegisterAST::Ptr(new RegisterAST(MachRegister::getFramePointer(Arch_amdgpu_gfx908))); + framePtr[Arch_amdgpu_gfx90a] = RegisterAST::Ptr(new RegisterAST(MachRegister::getFramePointer(Arch_amdgpu_gfx90a))); + framePtr[Arch_amdgpu_gfx940] = RegisterAST::Ptr(new RegisterAST(MachRegister::getFramePointer(Arch_amdgpu_gfx940))); } if(stackPtr.empty()) { - stackPtr[Arch_x86] = RegisterAST::Ptr(new RegisterAST(MachRegister::getStackPointer(Arch_x86))); - stackPtr[Arch_x86_64] = RegisterAST::Ptr(new RegisterAST(MachRegister::getStackPointer(Arch_x86_64))); - stackPtr[Arch_ppc32] = RegisterAST::Ptr(new RegisterAST(MachRegister::getStackPointer(Arch_ppc32))); - stackPtr[Arch_ppc64] = RegisterAST::Ptr(new RegisterAST(MachRegister::getStackPointer(Arch_ppc64))); - stackPtr[Arch_aarch64] = RegisterAST::Ptr(new RegisterAST(MachRegister::getStackPointer(Arch_aarch64))); - stackPtr[Arch_amdgpu_vega] = RegisterAST::Ptr(new RegisterAST(MachRegister::getStackPointer(Arch_amdgpu_vega))); + stackPtr[Arch_x86] = RegisterAST::Ptr(new RegisterAST(MachRegister::getStackPointer(Arch_x86))); + stackPtr[Arch_x86_64] = RegisterAST::Ptr(new RegisterAST(MachRegister::getStackPointer(Arch_x86_64))); + stackPtr[Arch_ppc32] = RegisterAST::Ptr(new RegisterAST(MachRegister::getStackPointer(Arch_ppc32))); + stackPtr[Arch_ppc64] = RegisterAST::Ptr(new RegisterAST(MachRegister::getStackPointer(Arch_ppc64))); + stackPtr[Arch_aarch64] = RegisterAST::Ptr(new RegisterAST(MachRegister::getStackPointer(Arch_aarch64))); + stackPtr[Arch_amdgpu_gfx908] = RegisterAST::Ptr(new RegisterAST(MachRegister::getStackPointer(Arch_amdgpu_gfx908))); + stackPtr[Arch_amdgpu_gfx90a] = RegisterAST::Ptr(new RegisterAST(MachRegister::getStackPointer(Arch_amdgpu_gfx90a))); + stackPtr[Arch_amdgpu_gfx940] = RegisterAST::Ptr(new RegisterAST(MachRegister::getStackPointer(Arch_amdgpu_gfx940))); } if(thePC.empty()) { @@ -159,7 +168,9 @@ void IA_IAPI::initASTs() thePC[Arch_ppc32] = RegisterAST::Ptr(new RegisterAST(MachRegister::getPC(Arch_ppc32))); thePC[Arch_ppc64] = RegisterAST::Ptr(new RegisterAST(MachRegister::getPC(Arch_ppc64))); thePC[Arch_aarch64] = RegisterAST::Ptr(new RegisterAST(MachRegister::getPC(Arch_aarch64))); - thePC[Arch_amdgpu_vega] = RegisterAST::Ptr(new RegisterAST(MachRegister::getPC(Arch_amdgpu_vega))); + thePC[Arch_amdgpu_gfx908] = RegisterAST::Ptr(new RegisterAST(MachRegister::getPC(Arch_amdgpu_gfx908))); + thePC[Arch_amdgpu_gfx90a] = RegisterAST::Ptr(new RegisterAST(MachRegister::getPC(Arch_amdgpu_gfx90a))); + thePC[Arch_amdgpu_gfx940] = RegisterAST::Ptr(new RegisterAST(MachRegister::getPC(Arch_amdgpu_gfx940))); } ANNOTATE_HAPPENS_BEFORE(&IA_IAPI::ptrInit); }); @@ -182,7 +193,7 @@ IA_IAPI::IA_IAPI(InstructionDecoder dec_, hascftstatus.first = false; tailCalls.clear(); - //boost::tuples::tie(curInsnIter, boost::tuples::ignore) = allInsns.insert(std::make_pair(current, dec.decode())); + //dyncompat::tuples::tie(curInsnIter, dyncompat::tuples::ignore) = allInsns.insert(std::make_pair(current, dec.decode())); curInsnIter = allInsns.insert( allInsns.end(), @@ -283,8 +294,6 @@ bool IA_IAPI::retreat() size_t IA_IAPI::getSize() const { - if (!curInsn().isValid()) return 0; - if (curInsn().getOperation().getID() == e_No_Entry) return 0; return curInsn().size(); } @@ -456,7 +465,7 @@ bool IA_IAPI::isDynamicCall() const { Address addr; bool success; - boost::tie(success, addr) = getCFT(); + std::tie(success, addr) = getCFT(); if (!success) { parsing_printf("... Call 0x%lx is indirect\n", current); return true; @@ -471,7 +480,7 @@ bool IA_IAPI::isAbsoluteCall() const if(ci.getCategory() == c_CallInsn) { Expression::Ptr cft = ci.getControlFlowTarget(); - if(cft && boost::dynamic_pointer_cast(cft)) + if(cft && dyncompat::dynamic_pointer_cast(cft)) { return true; } @@ -494,29 +503,7 @@ bool IA_IAPI::isCall() const bool IA_IAPI::isInterruptOrSyscall() const { - return (isInterrupt() && isSyscall()); -} - -bool IA_IAPI::isSyscall() const -{ - static RegisterAST::Ptr gs(new RegisterAST(x86::gs)); - - Instruction ci = curInsn(); - - return (((ci.getOperation().getID() == e_call) && - (ci.getOperation().isRead(gs)) && - (ci.getOperand(0).format(ci.getArch()) == "16")) || - (ci.getOperation().getID() == e_syscall) || - (ci.getOperation().getID() == e_int) || - (ci.getOperation().getID() == power_op_sc)); -} - - -bool IA_IAPI::isInterrupt() const -{ - Instruction ci = curInsn(); - return ((ci.getOperation().getID() == e_int) || - (ci.getOperation().getID() == e_int3)); + return (Dyninst::InstructionAPI::isSoftwareInterrupt(curInsn()) || Dyninst::InstructionAPI::isSystemCall(curInsn())); } bool IA_IAPI::isSysEnter() const @@ -531,7 +518,7 @@ bool IA_IAPI::isIndirectJump() const { if(ci.allowsFallThrough()) return false; bool valid; Address target; - boost::tie(valid, target) = getCFT(); + std::tie(valid, target) = getCFT(); if (valid) return false; parsing_printf("... indirect jump at 0x%lx, delay parsing it\n", current); return true; @@ -585,7 +572,7 @@ void IA_IAPI::getNewEdges(std::vector >& outEd { bool success; Address target; - boost::tie(success, target) = getCFT(); + std::tie(success, target) = getCFT(); bool callEdge = true; bool ftEdge = true; if( success && !isDynamicCall() ) @@ -649,7 +636,7 @@ void IA_IAPI::getNewEdges(std::vector >& outEd bool valid; Address target; - boost::tie(valid, target) = getCFT(); + std::tie(valid, target) = getCFT(); // Direct jump if (valid) { @@ -753,7 +740,7 @@ void IA_IAPI::getNewEdges(std::vector >& outEd { parseSysEnter(outEdges); return; - } else if (DEBUGGABLE() && isSyscall()) { + } else if (DEBUGGABLE() && Dyninst::InstructionAPI::isSystemCall(curInsn())) { parseSyscall(outEdges); return; } @@ -772,7 +759,7 @@ bool IA_IAPI::isIPRelativeBranch() const bool valid; Address target; - boost::tie(valid, target) = getCFT(); + std::tie(valid, target) = getCFT(); if(ci.getCategory() == c_BranchInsn && !valid) { @@ -814,7 +801,7 @@ bool IA_IAPI::isRealCall() const // Obviated by simulateJump bool success; Address addr; - boost::tie(success, addr) = getCFT(); + std::tie(success, addr) = getCFT(); if (success && (addr == getNextAddr())) { parsing_printf("... getting PC\n"); @@ -892,7 +879,7 @@ bool IA_IAPI::isRelocatable(InstrumentableLevel lvl) const if(!isDynamicCall()) { bool valid; Address addr; - boost::tie(valid, addr) = getCFT(); + std::tie(valid, addr) = getCFT(); assert(valid); if(!_isrc->isValidAddress(addr)) { diff --git a/parseAPI/src/IA_IAPI.h b/parseAPI/src/IA_IAPI.h index 3fa0f15843..4a717199ee 100644 --- a/parseAPI/src/IA_IAPI.h +++ b/parseAPI/src/IA_IAPI.h @@ -31,8 +31,14 @@ #if !defined(IA_IAPI_H) #define IA_IAPI_H -#include -#include +#include +#include +#include +#include +#include +#include +#include +#include #include "InstructionAdapter.h" #include "InstructionDecoder.h" @@ -110,8 +116,6 @@ class IA_IAPI : public InstructionAdapter { virtual bool isConditional() const; virtual bool isBranch() const; virtual bool isInterruptOrSyscall() const; - virtual bool isSyscall() const; - virtual bool isInterrupt() const; virtual bool isCall() const; virtual bool isReturnAddrSave(Address &ret_addr) const = 0; virtual bool isNopJump() const = 0; diff --git a/parseAPI/src/IA_aarch64.C b/parseAPI/src/IA_aarch64.C index 988525ea8c..92031ca1a8 100644 --- a/parseAPI/src/IA_aarch64.C +++ b/parseAPI/src/IA_aarch64.C @@ -29,13 +29,9 @@ */ #include "IA_aarch64.h" -#include "Register.h" -#include "Dereference.h" -#include "Immediate.h" -#include "BinaryFunction.h" - +#include "instructionAPI/h/syscalls.h" #include "common/src/arch.h" - +#include "registers/aarch64_regs.h" #include "parseAPI/src/debug_parse.h" #include @@ -44,6 +40,7 @@ #include #include #include +#include "Register.h" using namespace Dyninst; using namespace InstructionAPI; @@ -136,7 +133,7 @@ bool IA_aarch64::isTailCall(const Function* context, EdgeTypeEnum type, unsigned } bool valid; Address addr; - boost::tie(valid, addr) = getCFT(); + std::tie(valid, addr) = getCFT(); Function *callee = _obj->findFuncByEntry(_cr, addr); Block *target = _obj->findBlockByEntry(_cr, addr); diff --git a/parseAPI/src/IA_aarch64.h b/parseAPI/src/IA_aarch64.h index 0201a469d7..16980e4f0a 100644 --- a/parseAPI/src/IA_aarch64.h +++ b/parseAPI/src/IA_aarch64.h @@ -29,6 +29,7 @@ */ #if !defined(IA_AARCH64__H) #define IA_AARCH64__H +#include #include "common/h/DynAST.h" #include "dataflowAPI/h/Absloc.h" #include "dataflowAPI/h/SymEval.h" diff --git a/parseAPI/src/IA_amdgpu.C b/parseAPI/src/IA_amdgpu.C index c3305017cc..9a7e5ccb30 100644 --- a/parseAPI/src/IA_amdgpu.C +++ b/parseAPI/src/IA_amdgpu.C @@ -29,7 +29,6 @@ */ #include "IA_amdgpu.h" -#include "Register.h" #include "Dereference.h" #include "Immediate.h" #include "BinaryFunction.h" @@ -44,6 +43,7 @@ #include #include #include +#include "Register.h" using namespace Dyninst; using namespace InstructionAPI; @@ -73,7 +73,9 @@ bool IA_amdgpu::isFrameSetupInsn(Instruction ) const bool IA_amdgpu::isNop() const { Instruction ci = curInsn(); - if(ci.getOperation().getID() == amdgpu_op_s_nop) + auto id = ci.getOperation().getID(); + if(id == amdgpu_gfx908_op_S_NOP || + id == amdgpu_gfx90a_op_S_NOP || id == amdgpu_gfx940_op_S_NOP) return true; return false; } diff --git a/parseAPI/src/IA_amdgpu.h b/parseAPI/src/IA_amdgpu.h index 0fb3d75e07..4a340472ca 100644 --- a/parseAPI/src/IA_amdgpu.h +++ b/parseAPI/src/IA_amdgpu.h @@ -29,6 +29,7 @@ */ #if !defined(IA_AMDGPU__H) #define IA_AMDGPU__H +#include #include "common/h/DynAST.h" #include "dataflowAPI/h/Absloc.h" #include "dataflowAPI/h/SymEval.h" diff --git a/parseAPI/src/IA_power.C b/parseAPI/src/IA_power.C index 83a7415746..e3d1985305 100644 --- a/parseAPI/src/IA_power.C +++ b/parseAPI/src/IA_power.C @@ -31,13 +31,11 @@ #include "IA_power.h" -#include "Register.h" -#include "Dereference.h" -#include "Immediate.h" -#include "BinaryFunction.h" +#include "instructionAPI/h/syscalls.h" #include "common/src/arch.h" - +#include "registers/ppc32_regs.h" +#include "registers/ppc64_regs.h" #include "parseAPI/src/debug_parse.h" #include @@ -46,6 +44,7 @@ #include #include #include +#include "Register.h" using namespace Dyninst; using namespace InstructionAPI; @@ -122,7 +121,7 @@ bool IA_power::isTailCall(const Function* context, EdgeTypeEnum type, unsigned i } bool valid; Address addr; - boost::tie(valid, addr) = getCFT(); + std::tie(valid, addr) = getCFT(); Function* callee = _obj->findFuncByEntry(_cr, addr); Block* target = _obj->findBlockByEntry(_cr, addr); @@ -437,395 +436,12 @@ bool IA_power::isIATcall(std::string &) const return false; } -const unsigned int B_UNCOND = 0x48000000; -const unsigned int ADDIS_R12_R12 = 0x3d8c0000; -const unsigned int ADDIS_R12_R2 = 0x3d820000; -const unsigned int ADDIS_R2_R2 = 0x3c420000; -const unsigned int ADDI_R12_R12 = 0x398c0000; -const unsigned int ADDI_R2_R2 = 0x38420000; -const unsigned int STD_R2_40R1 = 0xf8410028; -const unsigned int LD_R2_40R1 = 0xe8410028; -const unsigned int LD_R2_0R2 = 0xe8420000; -const unsigned int LD_R2_0R12 = 0xe84c0000; -const unsigned int LD_R11_0R12 = 0xe96c0000; -const unsigned int LD_R11_0R2 = 0xe9620000; -const unsigned int MTCTR_R11 = 0x7d6903a6; -const unsigned int BCTR = 0x4e800420; - -typedef enum { - STUB_UNKNOWN, - STUB_LONG_BRANCH, - STUB_TOC_BRANCH, - STUB_PLT_CALL -} linker_stub_t; - -linker_stub_t checkLinkerStub(void *insn_buf, Offset &off) -{ -#if defined(ppc64_linux) - /* - * Linker stubs seen from GNU's binutils. - * (see the following functions in binutils' bfd/elf64-ppc.c: - * ppc_build_one_stub() - * build_plt_stub() - * build_tls_get_addr_stub() - * - * We could be clever and create some sort of state machine that will - * determine the correct signature by only reading each instruction - * once. However, I assume this will also make the code harder to - * maintain, and so I've gone the dumb route. We can re-code this - * section if it's determined to be a performance bottleneck. - * - * Add stub signatures as we see more. - */ - - // ---------------------------------------------- - // ppc_stub_plt_call: - // - - // binutils >= 2.18 PLT stub signatures look like this: - // if (PPC_HA (off) != 0) - // ADDIS_R12_R2 | PPC_HA (off) - // STD_R2_40R1 - // LD_R11_0R12 | PPC_LO (off) - // ADDI_R12_R12 | PPC_LO (off) if (PPC_HA (off + 16) != PPC_HA (off)) - // MTCTR_R11 - // LD_R2_0R12 | PPC_LO (off + 8) - // LD_R11_0R12 | PPC_LO (off + 16) - // BCTR - // else - // STD_R2_40R1 - // LD_R11_0R2 | PPC_LO (off) - // ADDI_R2_R2 | PPC_LO (off) - // MTCTR_R11 - // LD_R11_0R2 | PPC_LO (off + 16) - // LD_R2_0R2 | PPC_LO (off + 8) - // BCTR - // endif - // - // This results in three possible stubs: - - instruction *insn = static_cast(insn_buf); - if ( (insn[0].asInt() & 0xffff0000) == ADDIS_R12_R2 - && insn[1].asInt() == STD_R2_40R1 - && (insn[2].asInt() & 0xffff0000) == LD_R11_0R12 - && (insn[2].asInt() & 0xffff0000) == ADDI_R12_R12 - && insn[4].asInt() == MTCTR_R11 - && (insn[3].asInt() & 0xffff0000) == LD_R2_0R12 - && (insn[5].asInt() & 0xffff0000) == LD_R11_0R12 - && insn[6].asInt() == BCTR) - { - off = (DFORM_SI(insn[0]) << 16) + DFORM_SI(insn[2]); - return STUB_PLT_CALL; - } - - if ( (insn[0].asInt() & 0xffff0000) == ADDIS_R12_R2 - && insn[1].asInt() == STD_R2_40R1 - && (insn[2].asInt() & 0xffff0000) == LD_R11_0R12 - && insn[4].asInt() == MTCTR_R11 - && (insn[3].asInt() & 0xffff0000) == LD_R2_0R12 - && (insn[5].asInt() & 0xffff0000) == LD_R11_0R12 - && insn[6].asInt() == BCTR) - { - off = (DFORM_SI(insn[0]) << 16) + DFORM_SI(insn[2]); - return STUB_PLT_CALL; - } - - if ( insn[1].asInt() == STD_R2_40R1 - && (insn[2].asInt() & 0xffff0000) == LD_R11_0R2 - && (insn[2].asInt() & 0xffff0000) == ADDI_R2_R2 - && insn[4].asInt() == MTCTR_R11 - && (insn[3].asInt() & 0xffff0000) == LD_R11_0R12 - && (insn[5].asInt() & 0xffff0000) == LD_R2_0R12 - && insn[6].asInt() == BCTR) - { - off = DFORM_SI(insn[1]); - return STUB_PLT_CALL; - } - - // binutils from 1.15 -> 2.18 PLT stub signatures look like this: - // ADDIS_R12_R2 | PPC_HA (off) - // STD_R2_40R1 - // LD_R11_0R12 | PPC_LO (off) - // ADDIS_R12_R12 | 1 if (PPC_HA (off + 8) != PPC_HA (off)) - // LD_R2_0R12 | PPC_LO (off) - // ADDIS_R12_R12 | 1 if (PPC_HA (off + 16) != PPC_HA (off)) - // MTCTR_R11 - // LD_R11_0R12 | PPC_LO (off) - // BCTR - // - // This results in three possible stubs: - - if ( (insn[0].asInt() & 0xffff0000) == ADDIS_R12_R2 - && insn[1].asInt() == STD_R2_40R1 - && (insn[2].asInt() & 0xffff0000) == LD_R11_0R12 - && (insn[3].asInt() & 0xffff0000) == LD_R2_0R12 - && insn[4].asInt() == MTCTR_R11 - && (insn[5].asInt() & 0xffff0000) == LD_R11_0R12 - && insn[6].asInt() == BCTR) - { - off = (DFORM_SI(insn[0]) << 16) + DFORM_SI(insn[2]); - return STUB_PLT_CALL; - } - - if ( (insn[0].asInt() & 0xffff0000) == ADDIS_R12_R2 - && insn[1].asInt() == STD_R2_40R1 - && (insn[2].asInt() & 0xffff0000) == LD_R11_0R12 - && (insn[3].asInt() & 0xffff0000) == LD_R2_0R12 - && insn[4].asInt() == (ADDIS_R12_R12 | 1) - && insn[5].asInt() == MTCTR_R11 - && (insn[6].asInt() & 0xffff0000) == LD_R11_0R12 - && insn[7].asInt() == BCTR) - { - off = (DFORM_SI(insn[0]) << 16) + DFORM_SI(insn[2]); - return STUB_PLT_CALL; - } - - if ( (insn[0].asInt() & 0xffff0000) == ADDIS_R12_R2 - && insn[1].asInt() == STD_R2_40R1 - && (insn[2].asInt() & 0xffff0000) == LD_R11_0R12 - && insn[3].asInt() == (ADDIS_R12_R12 | 1) - && (insn[4].asInt() & 0xffff0000) == LD_R2_0R12 - && insn[5].asInt() == (ADDIS_R12_R12 | 1) - && insn[6].asInt() == MTCTR_R11 - && (insn[7].asInt() & 0xffff0000) == LD_R11_0R12 - && insn[8].asInt() == BCTR) - { - off = (DFORM_SI(insn[0]) << 16) + DFORM_SI(insn[2]); - return STUB_PLT_CALL; - } - - // binutils < 1.15 PLT stub signatures look like this: - // LD_R2_40R1 if (glink) - // ADDIS_R12_R2 | PPC_HA (off) - // STD_R2_40R1 if (!glink) - // LD_R11_0R12 | PPC_LO (off) - // ADDIS_R12_R12 | 1 if (PPC_HA (off + 8) != PPC_HA (off)) - // LD_R2_0R12 | PPC_LO (off) - // ADDIS_R12_R12 | 1 if (PPC_HA (off + 16) != PPC_HA (off)) - // MTCTR_R11 - // LD_R11_0R12 | PPC_LO (off) - // BCTR - // - // The non-glink case is identical to the cases above, so we need only - // handle the three glink cases: - - /* Ugg. The toc register is pulled off the stack for these cases. - This is most likely the toc for the callee, but we don't know - who the callee is yet. - */ - - if ( insn[0].asInt() == LD_R2_40R1 - && (insn[1].asInt() & 0xffff0000) == ADDIS_R12_R2 - && (insn[2].asInt() & 0xffff0000) == LD_R11_0R12 - && (insn[3].asInt() & 0xffff0000) == LD_R2_0R12 - && insn[4].asInt() == MTCTR_R11 - && (insn[5].asInt() & 0xffff0000) == LD_R11_0R12 - && insn[6].asInt() == BCTR) - { - fprintf(stderr, "WARNING: Pre-binutils 1.15 linker detected. PLT call stubs may not be handled properly.\n"); - return STUB_UNKNOWN; - //off = (DFORM_SI(insn[0]) << 16) + DFORM_SI(insn[2]); - //return STUB_PLT_CALL; - } - - if ( insn[0].asInt() == LD_R2_40R1 - && (insn[1].asInt() & 0xffff0000) == ADDIS_R12_R2 - && (insn[2].asInt() & 0xffff0000) == LD_R11_0R12 - && (insn[3].asInt() & 0xffff0000) == LD_R2_0R12 - && insn[4].asInt() == (ADDIS_R12_R12 | 1) - && insn[5].asInt() == MTCTR_R11 - && (insn[6].asInt() & 0xffff0000) == LD_R11_0R12 - && insn[7].asInt() == BCTR) - { - fprintf(stderr, "WARNING: Pre-binutils 1.15 linker detected. PLT call stubs may not be handled properly.\n"); - return STUB_UNKNOWN; - //off = (DFORM_SI(insn[0]) << 16) + DFORM_SI(insn[2]); - //return STUB_PLT_CALL; - } - - if ( insn[0].asInt() == LD_R2_40R1 - && (insn[1].asInt() & 0xffff0000) == ADDIS_R12_R2 - && (insn[2].asInt() & 0xffff0000) == LD_R11_0R12 - && insn[3].asInt() == (ADDIS_R12_R12 | 1) - && (insn[4].asInt() & 0xffff0000) == LD_R2_0R12 - && insn[5].asInt() == (ADDIS_R12_R12 | 1) - && insn[6].asInt() == MTCTR_R11 - && (insn[7].asInt() & 0xffff0000) == LD_R11_0R12 - && insn[8].asInt() == BCTR) - { - fprintf(stderr, "WARNING: Pre-binutils 1.15 linker detected. PLT call stubs may not be handled properly.\n"); - return STUB_UNKNOWN; - //off = (DFORM_SI(insn[0]) << 16) + DFORM_SI(insn[2]); - //return STUB_PLT_CALL; - } - - // ---------------------------------------------- - // ppc_stub_long_branch: - // ppc_stub_long_branch_r2off: - if ( (insn[0].asInt() & 0xfc000000) == B_UNCOND) - { - off = IFORM_LI(insn[0]) << 2; - return STUB_LONG_BRANCH; - } - - if ( insn[0].asInt() == STD_R2_40R1 - && (insn[1].asInt() & 0xffff0000) == ADDIS_R2_R2 - && (insn[2].asInt() & 0xffff0000) == ADDI_R2_R2 - && (insn[3].asInt() & 0xfc000003) == B_UNCOND) - { - off = (3 * 4) + (IFORM_LI(insn[3]) << 2); - return STUB_LONG_BRANCH; - } - - if ( insn[0].asInt() == STD_R2_40R1 - && (insn[1].asInt() & 0xffff0000) == ADDI_R2_R2 - && (insn[2].asInt() & 0xfc000003) == B_UNCOND) - { - off = (2 * 4) + (IFORM_LI(insn[2]) << 2); - return STUB_LONG_BRANCH; - } - - // ---------------------------------------------- - // ppc_stub_plt_branch: - // - if ( (insn[0].asInt() & 0xffff0000) == ADDIS_R12_R2 - && (insn[1].asInt() & 0xffff0000) == LD_R11_0R12 - && insn[2].asInt() == MTCTR_R11 - && insn[3].asInt() == BCTR) - { - off = (DFORM_SI(insn[0]) << 16) + DFORM_SI(insn[1]); - return STUB_TOC_BRANCH; - } - - if ( (insn[0].asInt() & 0xffff0000) == LD_R11_0R2 - && insn[1].asInt() == MTCTR_R11 - && insn[2].asInt() == BCTR) - { - off = DFORM_SI(insn[0]); - return STUB_TOC_BRANCH; - } - - // ---------------------------------------------- - // ppc_stub_plt_branch_r2off: - // - - // With offset > 16 bits && r2offset > 16 bits - if ( insn[0].asInt() == STD_R2_40R1 - && (insn[1].asInt() & 0xffff0000) == ADDIS_R12_R2 - && (insn[2].asInt() & 0xffff0000) == LD_R11_0R12 - && (insn[3].asInt() & 0xffff0000) == ADDIS_R2_R2 - && (insn[4].asInt() & 0xffff0000) == ADDI_R2_R2 - && insn[5].asInt() == MTCTR_R11 - && insn[6].asInt() == BCTR) - { - off = (DFORM_SI(insn[1]) << 16) + DFORM_SI(insn[2]); - return STUB_TOC_BRANCH; - } - - // With offset > 16 bits && r2offset <= 16 bits - if ( insn[0].asInt() == STD_R2_40R1 - && (insn[1].asInt() & 0xffff0000) == ADDIS_R12_R2 - && (insn[2].asInt() & 0xffff0000) == LD_R11_0R12 - && (insn[3].asInt() & 0xffff0000) == ADDI_R2_R2 - && insn[4].asInt() == MTCTR_R11 - && insn[5].asInt() == BCTR) - { - off = (DFORM_SI(insn[1]) << 16) + DFORM_SI(insn[2]); - return STUB_TOC_BRANCH; - } - - // With offset <= 16 bits && r2offset > 16 bits - if ( insn[0].asInt() == STD_R2_40R1 - && (insn[1].asInt() & 0xffff0000) == LD_R11_0R2 - && (insn[2].asInt() & 0xffff0000) == ADDIS_R2_R2 - && (insn[3].asInt() & 0xffff0000) == ADDI_R2_R2 - && insn[4].asInt() == MTCTR_R11 - && insn[5].asInt() == BCTR) - { - off = DFORM_SI(insn[1]); - return STUB_TOC_BRANCH; - } - - // With offset <= 16 bits && r2offset <= 16 bits - if ( insn[0].asInt() == STD_R2_40R1 - && (insn[1].asInt() & 0xffff0000) == LD_R11_0R2 - && (insn[2].asInt() & 0xffff0000) == ADDI_R2_R2 - && insn[3].asInt() == MTCTR_R11 - && insn[4].asInt() == BCTR) - { - off = DFORM_SI(insn[1]); - return STUB_TOC_BRANCH; - } -#else - (void)insn_buf; -#endif - - off = 0; - return STUB_UNKNOWN; -} - bool IA_power::isLinkerStub() const { // Disabling this code because it ends with an // incorrect CFG. return false; - - if (validLinkerStubState) - return cachedLinkerStubState; - - if (!validCFT) - return false; - - if (!isCall()) { - cachedLinkerStubState = false; - validLinkerStubState = true; - return cachedLinkerStubState; - } - - if (!cachedCFT.first) return false; - - void *insn_buf = _isrc->getPtrToInstruction(cachedCFT.second); - if (!insn_buf) - return false; - - Offset off; - linker_stub_t stub_type = checkLinkerStub(insn_buf, off); - - switch (stub_type) { - case STUB_UNKNOWN: - // It's not a linker stub (that we know of). Allow processing to - // continue unmodified, probably leading to the eventual creation - // of a targXXXXX function. - break; - - case STUB_LONG_BRANCH: - cachedCFT.second += off; - break; - - case STUB_TOC_BRANCH: - cachedCFT.second += off; - assert(0 && "STUB_TOC_BRANCH not implemented yet."); - - // Although tempting, we cannot just read the word directly from the - // mutatee, and find the symbol that matches. There may be no - // child process to read from. - // - // In theory, we can use the relocations to determine the final - // address/symbol. But, I can't get binutils to actually generate - // this kind of stub. Let's deal with this once we find a binary - // that uses it. - break; - - case STUB_PLT_CALL: - cachedCFT.second = _obj->cs()->getTOC(current) + off; - break; - } - - cachedLinkerStubState = (stub_type != STUB_UNKNOWN); - validLinkerStubState = true; - - return cachedLinkerStubState; } AST::Ptr PPC_BLR_Visitor::visit(AST *a) { @@ -909,5 +525,3 @@ bool IA_power::isNopJump() const { return false; } - - diff --git a/parseAPI/src/IA_power.h b/parseAPI/src/IA_power.h index 21e92c6aff..0b9982c1e1 100644 --- a/parseAPI/src/IA_power.h +++ b/parseAPI/src/IA_power.h @@ -29,6 +29,7 @@ */ #if !defined(IA_POWER__H) #define IA_POWER__H +#include #include "common/h/DynAST.h" #include "dataflowAPI/h/Absloc.h" #include "dataflowAPI/h/SymEval.h" diff --git a/parseAPI/src/IA_x86.C b/parseAPI/src/IA_x86.C index 132a8499d8..f4c9546087 100644 --- a/parseAPI/src/IA_x86.C +++ b/parseAPI/src/IA_x86.C @@ -29,8 +29,8 @@ */ +#include #include "IA_x86.h" -#include "Register.h" #include "Dereference.h" #include "Immediate.h" #include "BinaryFunction.h" @@ -42,7 +42,13 @@ //#include "StackTamperVisitor.h" #include "instructionAPI/h/Visitor.h" +#include "instructionAPI/h/syscalls.h" + #include +#include "Register.h" + +#include +#include using namespace Dyninst; using namespace InstructionAPI; @@ -91,75 +97,120 @@ bool IA_x86::isFrameSetupInsn(Instruction i) const return false; } -class nopVisitor : public InstructionAPI::Visitor -{ - public: - nopVisitor() : foundReg(false), foundImm(false), foundBin(false), isNop(true) {} - virtual ~nopVisitor() {} - bool foundReg; - bool foundImm; - bool foundBin; - bool isNop; +/* + * Simplify an effective address calulation for 'lea' instruction + * + * A common idiom for a multi-byte nop is to perform an effective address + * calculation that results in storing the value of a register into itself. + * + * Examples: + * + * lea rax, [rax] + * lea rax, [rax*1 + 0] + * + * This visitor uses a stack and an RPN-style calculation to simplify instances + * of multiplicitive (1) and additive (0) identities. If a binary expression + * with an identity operand is encountered the result is the other value of the + * expression. All other expressions result in the original expression. The + * final result simplifies to either a register expression or some other + * expression. + * + * After applying the visitor to both operands, A NOP is then determined by + * testing if each visitor's result is a register and are identical. + * + * There are special cases that are handled implicitly. + * + * 1) The pseudoregister `riz` in `lea rsi, [rsi+riz*1+0x0]` is an assembly + * construct to indicate a SIB, is not present in the expression not considered + * to be read. This reduces the expression to `rsi+0x0`. + * + * 2) If the source and destination registers are different sizes, then the + * instruction is not considered a nop. For example, `lea eax, [rax]`. + * + */ +class leaSimplifyVisitor : public InstructionAPI::Visitor +{ + using ExprNodeValues = dyncompat::variant2::variant; + using ExprStack = std::stack; + ExprStack exprStack; - virtual void visit(BinaryFunction*) - { - if (foundBin) isNop = false; - if (!foundImm) isNop = false; - if (!foundReg) isNop = false; - foundBin = true; + public: + void visit(BinaryFunction *bf) override { + auto op1 = exprStack.top(); + exprStack.pop(); + auto op2 = exprStack.top(); + exprStack.pop(); + + auto value = dyncompat::variant2::get_if(&op1); + if (!value) { + std::swap(op1, op2); // op1 not an immediate, commute and try again + value = dyncompat::variant2::get_if(&op1); + } + if (value && ((*value == 0 && bf->isAdd()) || (*value == 1 && bf->isMultiply()))) { + exprStack.push(op2); // additive or multiplicative identity, simplify to op2 + } else { + exprStack.push(bf); // no simplification, use BinaryFunction expression + } } - virtual void visit(Immediate *imm) - { - if (imm != 0) isNop = false; - foundImm = true; + void visit(Immediate *imm) override { + auto const value = imm->eval().convert(); + exprStack.push(value); } - virtual void visit(RegisterAST *) - { - foundReg = true; + void visit(RegisterAST *reg) override { + exprStack.push(reg); } - virtual void visit(Dereference *) - { - isNop = false; + void visit(Dereference *deref) override { + parsing_printf("%s[%d]: malformed lea instruction, dereference expression encountered\n", + FILE__, __LINE__); + exprStack.pop(); // pop the Dereference's child expression + exprStack.push(deref); // replace with the Dereference exprression + } + + // return simplified result RegisterAST* or nullptr if not a registerAST* + const RegisterAST *getRegister() const { + auto value = dyncompat::variant2::get_if(&exprStack.top()); + return value ? *value : nullptr; + } + void reset() { // reset the visitor for reuse + exprStack = {}; // clear the stack } }; -bool isNopInsn(Instruction insn) -{ - // TODO: add LEA no-ops - if(insn.getOperation().getID() == e_nop) - return true; - if(insn.getOperation().getID() == e_lea) - { - std::set memReadAddr; - insn.getMemoryReadOperands(memReadAddr); - std::set writtenRegs; - insn.getWriteSet(writtenRegs); - if(memReadAddr.size() == 1 && writtenRegs.size() == 1) - { - if(**(memReadAddr.begin()) == **(writtenRegs.begin())) - { - return true; - } +bool isNopInsn(Instruction insn) { + if (insn.getOperation().getID() == e_nop) { + return true; + } else if (insn.getOperation().getID() == e_lea) { + std::vector operands; + insn.getOperands(operands); + + if (operands.size() != 2) { + parsing_printf("%s[%d]: malformed lea instruction number of operands (%lu) not 2", + FILE__, __LINE__, operands.size()); + return false; } - // Check for zero displacement - nopVisitor visitor; - // We need to get the src operand - insn.getOperand(1).getValue()->apply(&visitor); - if (visitor.isNop) return true; + leaSimplifyVisitor op1Visitor, op2Visitor; + operands[0].getValue()->apply(&op1Visitor); + operands[1].getValue()->apply(&op2Visitor); + + auto op1Reg = op1Visitor.getRegister(); + auto op2Reg = op2Visitor.getRegister(); + + // both operands simplify to registers and they are the same + return op1Reg && op2Reg && *op1Reg == *op2Reg; } + return false; } + bool IA_x86::isNop() const { Instruction ci = curInsn(); - return isNopInsn(ci); - } /* @@ -197,7 +248,7 @@ namespace { bool IA_x86::isThunk() const { // Before we go a-wandering, check the target bool valid; Address addr; - boost::tie(valid, addr) = getCFT(); + std::tie(valid, addr) = getCFT(); if (!valid || !_isrc->isValidAddress(addr)) { parsing_printf("... Call to 0x%lx is invalid (outside code or data)\n", @@ -259,7 +310,7 @@ bool IA_x86::isTailCall(const Function *context, EdgeTypeEnum type, unsigned int } bool valid; Address addr; - boost::tie(valid, addr) = getCFT(); + std::tie(valid, addr) = getCFT(); Function* callee = _obj->findFuncByEntry(_cr, addr); Block* target = _obj->findBlockByEntry(_cr, addr); @@ -359,7 +410,7 @@ bool IA_x86::isTailCall(const Function *context, EdgeTypeEnum type, unsigned int if(prevInsn.isWritten(stackPtr[_isrc->getArch()])) { bool call_fallthrough = false; - boost::lock_guard g(*_curBlk); + dyncompat::lock_guard g(*_curBlk); if (_curBlk->start() == prevIter->first) { for (auto eit = _curBlk->sources().begin(); eit != _curBlk->sources().end(); ++eit) { @@ -477,7 +528,7 @@ bool IA_x86::isFakeCall() const // get func entry bool tampers = false; bool valid; Address entry; - boost::tie(valid, entry) = getCFT(); + std::tie(valid, entry) = getCFT(); if (!valid) return false; @@ -507,7 +558,7 @@ bool IA_x86::isFakeCall() const while (insn.getCategory() == c_CallInsn || insn.getCategory() == c_BranchInsn) { - boost::tie(valid, entry) = ah->getCFT(); + std::tie(valid, entry) = ah->getCFT(); if ( !valid || ! _cr->contains(entry) || ! _isrc->isCode(entry) ) { mal_printf("WARNING: found call to function at %lx that " "leaves to %lx, out of the code region %s[%d]\n", @@ -557,12 +608,11 @@ bool IA_x86::isFakeCall() const stackDelta += sign * size; break; } - case e_pusha: - case e_pushad: + case e_pushal: sign = -1; //FALLTHROUGH - case e_popa: - case e_popad: + case e_popal: + case e_popaw: if (1 == sign) { mal_printf("popad ins'n at %lx in func at %lx changes sp " "by %d. %s[%d]\n", ah->getAddr(), @@ -571,7 +621,6 @@ bool IA_x86::isFakeCall() const stackDelta += sign * 8 * addrWidth; break; case e_pushf: - case e_pushfd: sign = -1; //FALLTHROUGH case e_popf: @@ -762,7 +811,7 @@ bool IA_x86::isNopJump() const return false; } bool valid; Address addr; - boost::tie(valid, addr) = getCFT(); + std::tie(valid, addr) = getCFT(); if(valid && current+1 == addr) { return true; } diff --git a/parseAPI/src/IA_x86.h b/parseAPI/src/IA_x86.h index 220a512e76..945132c23a 100644 --- a/parseAPI/src/IA_x86.h +++ b/parseAPI/src/IA_x86.h @@ -29,6 +29,7 @@ */ #if !defined(IA_X86__H) #define IA_X86__H +#include #include "common/h/DynAST.h" #include "dataflowAPI/h/Absloc.h" #include "dataflowAPI/h/SymEval.h" diff --git a/parseAPI/src/IdiomModelDesc.C b/parseAPI/src/IdiomModelDesc.C index 409f48c816..09a5554507 100644 --- a/parseAPI/src/IdiomModelDesc.C +++ b/parseAPI/src/IdiomModelDesc.C @@ -4,7 +4,8 @@ #include "ProbabilisticParser.h" #include "util.h" -#include "dyn_regs.h" +#include "registers/x86_regs.h" +#include "registers/x86_64_regs.h" #include #include @@ -73,7 +74,7 @@ IdiomModel::IdiomModel(string model_spec) { i7.w = 7.568732; i7.prefix = false; i7.terms.push_back(IdiomTerm(e_cmp, MEMARG, IMMARG)); - i7.terms.push_back(IdiomTerm(e_jz, x86::eip, NOARG)); + i7.terms.push_back(IdiomTerm(e_je, x86::eip, NOARG)); i7.terms.push_back(IdiomTerm(e_sub, x86::esp, IMMARG)); normal.addIdiom(i7); @@ -233,7 +234,7 @@ IdiomModel::IdiomModel(string model_spec) { i30.prefix = false; i30.terms.push_back(WILDCARD_TERM); i30.terms.push_back(WILDCARD_TERM); - i30.terms.push_back(IdiomTerm(e_jnbe, x86::eip, NOARG)); + i30.terms.push_back(IdiomTerm(e_ja, x86::eip, NOARG)); normal.addIdiom(i30); Idiom i31; @@ -254,7 +255,7 @@ IdiomModel::IdiomModel(string model_spec) { i33.w = 1.549826; i33.prefix = false; i33.terms.push_back(WILDCARD_TERM); - i33.terms.push_back(IdiomTerm(e_jz, x86::eip, NOARG)); + i33.terms.push_back(IdiomTerm(e_je, x86::eip, NOARG)); normal.addIdiom(i33); Idiom i34; @@ -287,7 +288,7 @@ IdiomModel::IdiomModel(string model_spec) { i37.prefix = true; i37.terms.push_back(IdiomTerm(e_jmp, x86::eip, NOARG)); i37.terms.push_back(WILDCARD_TERM); - i37.terms.push_back(IdiomTerm(e_jnz, x86::eip, NOARG)); + i37.terms.push_back(IdiomTerm(e_jne, x86::eip, NOARG)); reverse(i37.terms.begin(), i37.terms.end()); prefix.addIdiom(i37); @@ -763,7 +764,7 @@ IdiomModel::IdiomModel(string model_spec) { Idiom i55; i55.w = -8.526088; i55.prefix = true; - i55.terms.push_back(IdiomTerm(e_jz, x86::eip, NOARG)); + i55.terms.push_back(IdiomTerm(e_je, x86::eip, NOARG)); reverse(i55.terms.begin(), i55.terms.end()); prefix.addIdiom(i55); @@ -855,7 +856,7 @@ IdiomModel::IdiomModel(string model_spec) { i10.w = 11.854041; i10.prefix = false; i10.terms.push_back(IdiomTerm(e_cmp, MEMARG, IMMARG)); - i10.terms.push_back(IdiomTerm(e_jnz, x86_64::rip, NOARG)); + i10.terms.push_back(IdiomTerm(e_jne, x86_64::rip, NOARG)); i10.terms.push_back(IdiomTerm(e_push, x86_64::rbp, x86_64::rsp)); normal.addIdiom(i10); @@ -1068,7 +1069,7 @@ IdiomModel::IdiomModel(string model_spec) { Idiom i36; i36.w = 8.383780; i36.prefix = true; - i36.terms.push_back(IdiomTerm(e_jz, x86_64::rip, NOARG)); + i36.terms.push_back(IdiomTerm(e_je, x86_64::rip, NOARG)); i36.terms.push_back(IdiomTerm(e_call, x86_64::rip, NOARG)); i36.terms.push_back(IdiomTerm(e_nop, NOARG, NOARG)); reverse(i36.terms.begin(), i36.terms.end()); @@ -1176,7 +1177,7 @@ IdiomModel::IdiomModel(string model_spec) { Idiom i49; i49.w = -6.592325; i49.prefix = true; - i49.terms.push_back(IdiomTerm(e_jz, x86_64::rip, NOARG)); + i49.terms.push_back(IdiomTerm(e_je, x86_64::rip, NOARG)); reverse(i49.terms.begin(), i49.terms.end()); prefix.addIdiom(i49); @@ -1192,7 +1193,7 @@ IdiomModel::IdiomModel(string model_spec) { Idiom i51; i51.w = -11.891171; i51.prefix = true; - i51.terms.push_back(IdiomTerm(e_jnz, x86_64::rip, NOARG)); + i51.terms.push_back(IdiomTerm(e_jne, x86_64::rip, NOARG)); reverse(i51.terms.begin(), i51.terms.end()); prefix.addIdiom(i51); diff --git a/parseAPI/src/IndirectASTVisitor.C b/parseAPI/src/IndirectASTVisitor.C index e9df43401b..531b847135 100644 --- a/parseAPI/src/IndirectASTVisitor.C +++ b/parseAPI/src/IndirectASTVisitor.C @@ -184,7 +184,7 @@ AST::Ptr ComparisonVisitor::visit(DataflowAPI::RoseAST *ast) { bool minuendIsZero = true; AST::Ptr child = ast->child(0); if (child->getID() == AST::V_RoseAST) { - RoseAST::Ptr childRose = boost::static_pointer_cast(child); + RoseAST::Ptr childRose = dyncompat::static_pointer_cast(child); if (childRose->val().op == ROSEOperation::addOp) { minuendIsZero = false; subtrahend = childRose->child(0); @@ -192,7 +192,7 @@ AST::Ptr ComparisonVisitor::visit(DataflowAPI::RoseAST *ast) { // If the minuend is a constant, then // the minuend is currently in its two-complement form if (minuend->getID() == AST::V_ConstantAST) { - ConstantAST::Ptr constAST = boost::static_pointer_cast(minuend); + ConstantAST::Ptr constAST = dyncompat::static_pointer_cast(minuend); uint64_t val = constAST->val().val; int size = constAST->val().size; if (size < 64) @@ -203,10 +203,10 @@ AST::Ptr ComparisonVisitor::visit(DataflowAPI::RoseAST *ast) { parsing_printf("WARNING: constant bit size %d exceeds 64!\n", size); minuend = ConstantAST::create(Constant(val, size)); } else if (minuend->getID() == AST::V_RoseAST) { - RoseAST::Ptr sub = boost::static_pointer_cast(minuend); + RoseAST::Ptr sub = dyncompat::static_pointer_cast(minuend); minuend = AST::Ptr(); if (sub->val().op == ROSEOperation::addOp && sub->child(0)->getID() == AST::V_RoseAST) { - sub = boost::static_pointer_cast(sub->child(0)); + sub = dyncompat::static_pointer_cast(sub->child(0)); if (sub->val().op == ROSEOperation::invertOp) { // Otherwise, the minuend ast is in the form of add(invert(minuend), 1) // Need to extract the real minuend @@ -258,11 +258,11 @@ AST::Ptr JumpTableFormatVisitor::visit(DataflowAPI::RoseAST *ast) { firstAdd = false; Address tableBase = 0; if (ast->child(0)->getID() == AST::V_ConstantAST && PotentialIndexing(ast->child(1))) { - ConstantAST::Ptr constAST = boost::static_pointer_cast(ast->child(0)); + ConstantAST::Ptr constAST = dyncompat::static_pointer_cast(ast->child(0)); tableBase = (Address)constAST->val().val; } if (ast->child(1)->getID() == AST::V_ConstantAST && PotentialIndexing(ast->child(0))) { - ConstantAST::Ptr constAST = boost::static_pointer_cast(ast->child(1)); + ConstantAST::Ptr constAST = dyncompat::static_pointer_cast(ast->child(1)); tableBase = (Address)constAST->val().val; } if (tableBase) { @@ -294,25 +294,25 @@ AST::Ptr JumpTableFormatVisitor::visit(DataflowAPI::RoseAST *ast) { ast->val().op == ROSEOperation::shiftLOp || ast->val().op == ROSEOperation::rotateLOp) && memoryReadLayer > 0) { if (ast->child(0)->getID() == AST::V_ConstantAST && ast->child(1)->getID() == AST::V_VariableAST) { - ConstantAST::Ptr constAst = boost::static_pointer_cast(ast->child(0)); + ConstantAST::Ptr constAst = dyncompat::static_pointer_cast(ast->child(0)); if (!((ast->val().op == ROSEOperation::uMultOp || ast->val().op == ROSEOperation::sMultOp) && !findTableBase && constAst->val().val == 1)) { findIndex = true; numOfVar++; - VariableAST::Ptr varAst = boost::static_pointer_cast(ast->child(1)); + VariableAST::Ptr varAst = dyncompat::static_pointer_cast(ast->child(1)); index = varAst->val().reg; return AST::Ptr(); } } if (ast->child(1)->getID() == AST::V_ConstantAST && ast->child(0)->getID() == AST::V_VariableAST) { - ConstantAST::Ptr constAst = boost::static_pointer_cast(ast->child(1)); + ConstantAST::Ptr constAst = dyncompat::static_pointer_cast(ast->child(1)); if (!((ast->val().op == ROSEOperation::uMultOp || ast->val().op == ROSEOperation::sMultOp) && !findTableBase && constAst->val().val == 1)) { findIndex = true; numOfVar++; - VariableAST::Ptr varAst = boost::static_pointer_cast(ast->child(0)); + VariableAST::Ptr varAst = dyncompat::static_pointer_cast(ast->child(0)); index = varAst->val().reg; return AST::Ptr(); } @@ -335,7 +335,7 @@ AST::Ptr JumpTableFormatVisitor::visit(DataflowAPI::VariableAST *) { bool JumpTableFormatVisitor::PotentialIndexing(AST::Ptr ast) { if (ast->getID() == AST::V_VariableAST) return true; if (ast->getID() == AST::V_RoseAST) { - RoseAST::Ptr r = boost::static_pointer_cast(ast); + RoseAST::Ptr r = dyncompat::static_pointer_cast(ast); if (r->val().op == ROSEOperation::uMultOp || r->val().op == ROSEOperation::sMultOp || r->val().op == ROSEOperation::shiftLOp || @@ -348,8 +348,8 @@ bool JumpTableFormatVisitor::PotentialIndexing(AST::Ptr ast) { if (r->val().op == ROSEOperation::addOp) { // The index can be subtracted if (r->child(0)->getID() == AST::V_RoseAST && r->child(1)->getID() == AST::V_ConstantAST) { - RoseAST::Ptr lc = boost::static_pointer_cast(r->child(0)); - ConstantAST::Ptr rc = boost::static_pointer_cast(r->child(1)); + RoseAST::Ptr lc = dyncompat::static_pointer_cast(r->child(0)); + ConstantAST::Ptr rc = dyncompat::static_pointer_cast(r->child(1)); if (lc->val().op == ROSEOperation::invertOp && rc->val().val == 1) { return PotentialIndexing(lc->child(0)); } diff --git a/parseAPI/src/IndirectASTVisitor.h b/parseAPI/src/IndirectASTVisitor.h index 36d83daa25..9ef17960d2 100644 --- a/parseAPI/src/IndirectASTVisitor.h +++ b/parseAPI/src/IndirectASTVisitor.h @@ -1,6 +1,7 @@ #ifndef INDIRECT_AST_VISITOR_H #define INDIRECT_AST_VISITOR_H +#include #include #include "DynAST.h" diff --git a/parseAPI/src/IndirectAnalyzer.C b/parseAPI/src/IndirectAnalyzer.C index 413132b530..5c8960c4f1 100644 --- a/parseAPI/src/IndirectAnalyzer.C +++ b/parseAPI/src/IndirectAnalyzer.C @@ -1,5 +1,8 @@ +#include #include "dyntypes.h" #include "IndirectAnalyzer.h" + +#include "Register.h" #include "BoundFactCalculator.h" #include "JumpTableFormatPred.h" #include "JumpTableIndexPred.h" @@ -13,20 +16,20 @@ #include "Instruction.h" #include "InstructionDecoder.h" -#include "Register.h" #include "SymEval.h" + using namespace Dyninst::ParseAPI; using namespace Dyninst::InstructionAPI; static bool IsIndexing(AST::Ptr node, AbsRegion &index) { - RoseAST::Ptr n = boost::static_pointer_cast(node); + RoseAST::Ptr n = dyncompat::static_pointer_cast(node); if (n->val().op != ROSEOperation::sMultOp && n->val().op != ROSEOperation::uMultOp && n->val().op != ROSEOperation::shiftLOp && n->val().op != ROSEOperation::rotateLOp) return false; if (n->child(0)->getID() != AST::V_VariableAST) return false; if (n->child(1)->getID() != AST::V_ConstantAST) return false; - VariableAST::Ptr var = boost::static_pointer_cast(n->child(0)); + VariableAST::Ptr var = dyncompat::static_pointer_cast(n->child(0)); index = var->val().reg; return true; } @@ -35,18 +38,18 @@ static bool IsVariableArgumentFormat(AST::Ptr t, AbsRegion &index) { if (t->getID() != AST::V_RoseAST) { return false; } - RoseAST::Ptr rt = boost::static_pointer_cast(t); + RoseAST::Ptr rt = dyncompat::static_pointer_cast(t); if (rt->val().op != ROSEOperation::addOp) { return false; } if (rt->child(0)->getID() != AST::V_ConstantAST || rt->child(1)->getID() != AST::V_RoseAST) { return false; } - RoseAST::Ptr c1 = boost::static_pointer_cast(rt->child(1)); + RoseAST::Ptr c1 = dyncompat::static_pointer_cast(rt->child(1)); if (c1->val().op == ROSEOperation::addOp) { if (c1->child(0)->getID() == AST::V_RoseAST && c1->child(1)->getID() == AST::V_ConstantAST) { - RoseAST::Ptr lc = boost::static_pointer_cast(c1->child(0)); - ConstantAST::Ptr rc = boost::static_pointer_cast(c1->child(1)); + RoseAST::Ptr lc = dyncompat::static_pointer_cast(c1->child(0)); + ConstantAST::Ptr rc = dyncompat::static_pointer_cast(c1->child(1)); if (lc->val().op == ROSEOperation::invertOp && rc->val().val == 1) { return IsIndexing(lc->child(0), index); } @@ -65,7 +68,7 @@ bool IndirectControlFlowAnalyzer::NewJumpTableAnalysis(std::vectorlast(), func->name().c_str()); parsing_printf("Looking for thunk\n"); - boost::make_lock_guard(*func); + dyncompat::make_lock_guard(*func); // Find all blocks that reach the block containing the indirect jump // This is a prerequisit for finding thunks GetAllReachableBlock(); @@ -94,7 +97,11 @@ bool IndirectControlFlowAnalyzer::NewJumpTableAnalysis(std::vectorgetArch() == Arch_amdgpu_vega && insn.getOperation().getID() == amdgpu_op_s_swappc_b64 ) { + if ((se.cs->getArch() == Arch_amdgpu_gfx908 && insn.getOperation().getID() == amdgpu_gfx908_op_S_SETPC_B64) || + (se.cs->getArch() == Arch_amdgpu_gfx908 && insn.getOperation().getID() == amdgpu_gfx908_op_S_SWAPPC_B64) || + (se.cs->getArch() == Arch_amdgpu_gfx90a && insn.getOperation().getID() == amdgpu_gfx90a_op_S_SETPC_B64 ) || + (se.cs->getArch() == Arch_amdgpu_gfx940 && insn.getOperation().getID() == amdgpu_gfx940_op_S_SWAPPC_B64 )){ + Result_t symRet; SymEval::expand(slice,symRet); @@ -114,7 +121,7 @@ bool IndirectControlFlowAnalyzer::NewJumpTableAnalysis(std::vectorgetID() == AST::V_ConstantAST) { ConstantAST::Ptr constAST = - boost::static_pointer_cast(new_ast); + dyncompat::static_pointer_cast(new_ast); uint64_t val = constAST->val().val; //std::cerr << " resolved, value = " << std::hex < g(*cur); + dyncompat::lock_guard g(*cur); for (auto eit = cur->sources().begin(); eit != cur->sources().end(); ++eit) if ((*eit)->intraproc()) { if ((*eit)->src() == NULL) { @@ -243,7 +250,7 @@ static Address ThunkAdjustment(Address afterThunk, MachRegister reg, ParseAPI::B if (nextInsn.getOperation().getID() != e_add) return 0; vector operands; nextInsn.getOperands(operands); - RegisterAST::Ptr regAST = boost::dynamic_pointer_cast(operands[0].getValue()); + RegisterAST::Ptr regAST = dyncompat::dynamic_pointer_cast(operands[0].getValue()); // The first operand should be a register if (regAST == 0) return 0; if (regAST->getID() != reg) return 0; @@ -270,26 +277,31 @@ void IndirectControlFlowAnalyzer::FindAllThunks() { InsnAdapter::IA_IAPI* insnBlock = InsnAdapter::IA_IAPI::makePlatformIA_IAPI(b->obj()->cs()->getArch(), dec, b->start(), b->obj() , b->region(), b->obj()->cs(), b); Address cur = b->start(); while (cur < b->end()) { - if (insnBlock->getInstruction().getCategory() == c_CallInsn && insnBlock->isThunk()) { - bool valid; - Address addr; - boost::tie(valid, addr) = insnBlock->getCFT(); - const unsigned char *target = (const unsigned char *) b->region()->getPtrToInstruction(addr); - InstructionDecoder targetChecker(target, InstructionDecoder::maxInstructionLength, b->obj()->cs()->getArch()); - Instruction thunkFirst = targetChecker.decode(); - set thunkTargetRegs; - thunkFirst.getWriteSet(thunkTargetRegs); - - for (auto curReg = thunkTargetRegs.begin(); curReg != thunkTargetRegs.end(); ++curReg) { - ThunkInfo t; - t.reg = (*curReg)->getID(); - t.value = insnBlock->getAddr() + insnBlock->getInstruction().size(); - t.value += ThunkAdjustment(t.value, t.reg, b); - t.block = b; - thunks.insert(make_pair(insnBlock->getAddr(), t)); - parsing_printf("\tfind thunk at %lx, storing value %lx to %s\n", insnBlock->getAddr(), t.value , t.reg.name().c_str()); - } - } + if (insnBlock->getInstruction().getCategory() == c_CallInsn && insnBlock->isThunk()) { + bool valid; + Address addr; + std::tie(valid, addr) = insnBlock->getCFT(); + const unsigned char *target = (const unsigned char *) b->region()->getPtrToInstruction(addr); + // CFT may be located in another Region. In such case target will be 0, and we should find proper Region + // TODO search for the correct Region instead of just ignoring the instruction + if ( target ) + { + InstructionDecoder targetChecker(target, InstructionDecoder::maxInstructionLength, b->obj()->cs()->getArch()); + Instruction thunkFirst = targetChecker.decode(); + set thunkTargetRegs; + thunkFirst.getWriteSet(thunkTargetRegs); + + for (auto curReg = thunkTargetRegs.begin(); curReg != thunkTargetRegs.end(); ++curReg) { + ThunkInfo t; + t.reg = (*curReg)->getID(); + t.value = insnBlock->getAddr() + insnBlock->getInstruction().size(); + t.value += ThunkAdjustment(t.value, t.reg, b); + t.block = b; + thunks.insert(make_pair(insnBlock->getAddr(), t)); + parsing_printf("\tfind thunk at %lx, storing value %lx to %s\n", insnBlock->getAddr(), t.value , t.reg.name().c_str()); + } + } + } cur += insnBlock->getInstruction().size(); if (cur < b->end()) insnBlock->advance(); } diff --git a/parseAPI/src/IndirectAnalyzer.h b/parseAPI/src/IndirectAnalyzer.h index 2da3abd8f3..4019380e85 100644 --- a/parseAPI/src/IndirectAnalyzer.h +++ b/parseAPI/src/IndirectAnalyzer.h @@ -1,6 +1,10 @@ #ifndef INDIRECT_ANALYZER_H #define INDIRECT_ANALYZER_H +#include +#include +#include +#include #include "ThunkData.h" #include "BoundFactData.h" #include "CFG.h" diff --git a/parseAPI/src/InstructionAdapter.C b/parseAPI/src/InstructionAdapter.C index aec1434dc0..2a9e1350cf 100644 --- a/parseAPI/src/InstructionAdapter.C +++ b/parseAPI/src/InstructionAdapter.C @@ -28,13 +28,12 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "common/src/Types.h" //#include "arch.h" #include "InstructionAdapter.h" #include "debug_parse.h" #include "parseAPI/h/CodeObject.h" -#include "boost/tuple/tuple.hpp" +#include "dyncompat/tuple/tuple.hpp" using namespace std; using namespace Dyninst; @@ -110,7 +109,7 @@ FuncReturnStatus InstructionAdapter::getReturnStatus(Function * context , // Branch that's not resolvable by binding IP, // therefore indirect... bool valid; Address addr; - boost::tie(valid, addr) = getCFT(); + std::tie(valid, addr) = getCFT(); if(isBranch() && !valid) { if(num_insns == 2) @@ -156,7 +155,7 @@ bool InstructionAdapter::hasUnresolvedControlFlow(Function* context, unsigned in InstrumentableLevel InstructionAdapter::getInstLevel(Function * context, unsigned int num_insns) const { bool valid; Address target; - boost::tie(valid, target) = getCFT(); + std::tie(valid, target) = getCFT(); if(isBranch() && !valid) { if(num_insns == 2) diff --git a/parseAPI/src/JumpTableFormatPred.C b/parseAPI/src/JumpTableFormatPred.C index 22bf114c89..23f13b9825 100644 --- a/parseAPI/src/JumpTableFormatPred.C +++ b/parseAPI/src/JumpTableFormatPred.C @@ -1,3 +1,4 @@ +#include #include "JumpTableFormatPred.h" #include "SymbolicExpression.h" #include "IndirectASTVisitor.h" @@ -5,6 +6,9 @@ #include "CodeObject.h" #include "CodeSource.h" #include "debug_parse.h" +#include "registers/ppc32_regs.h" +#include "registers/ppc64_regs.h" + using namespace Dyninst; using namespace Dyninst::DataflowAPI; using namespace Dyninst::ParseAPI; @@ -154,14 +158,14 @@ bool JumpTableFormatPred::modifyCurrentFrame(Slicer::SliceFrame &frame, Graph::P std::unordered_map exprs; std::unordered_map inDegree; for (; nbegin != nend; ++nbegin) { - SliceNode::Ptr n = boost::static_pointer_cast(*nbegin); + SliceNode::Ptr n = dyncompat::static_pointer_cast(*nbegin); working_list.push(n); inQueue.insert(n->assign()); } g->allNodes(nbegin, nend); for (; nbegin != nend; ++nbegin) { - SliceNode::Ptr n = boost::static_pointer_cast(*nbegin); + SliceNode::Ptr n = dyncompat::static_pointer_cast(*nbegin); inDegree[n->assign()] = CountInDegree(n); } AST::Ptr jumpTarget; @@ -218,7 +222,7 @@ bool JumpTableFormatPred::modifyCurrentFrame(Slicer::SliceFrame &frame, Graph::P } parsing_printf("JumpTableFormatPred: analyze %s at %lx\n", n->assign()->format().c_str(), n->assign()->addr()); for (; nbegin != nend; ++nbegin) { - SliceNode::Ptr p = boost::static_pointer_cast(*nbegin); + SliceNode::Ptr p = dyncompat::static_pointer_cast(*nbegin); if (exprs.find(p->assign()) == exprs.end()) { parsing_printf("\tWARNING: For %s, its predecessor %s does not have an expression\n", n->assign()->format().c_str(), p->assign()->format().c_str()); @@ -261,7 +265,7 @@ bool JumpTableFormatPred::modifyCurrentFrame(Slicer::SliceFrame &frame, Graph::P if (*lhs == *exp) { match++; if (rhs->getID() == AST::V_ConstantAST) { - ConstantAST::Ptr c = boost::static_pointer_cast(rhs); + ConstantAST::Ptr c = dyncompat::static_pointer_cast(rhs); constAddr.insert(c->val().val); } else { nonConstant++; @@ -294,7 +298,7 @@ bool JumpTableFormatPred::modifyCurrentFrame(Slicer::SliceFrame &frame, Graph::P // Enumerate every successor and add them to the working list n->outs(nbegin, nend); for (; nbegin != nend; ++nbegin) { - SliceNode::Ptr p = boost::static_pointer_cast(*nbegin); + SliceNode::Ptr p = dyncompat::static_pointer_cast(*nbegin); inDegree[p->assign()] --; if (inDegree[p->assign()] == 0 && inQueue.find(p->assign()) == inQueue.end()) { inQueue.insert(p->assign()); @@ -356,7 +360,7 @@ bool JumpTableFormatPred::findRead(Graph::Ptr g, SliceNode::Ptr &readNode) { NodeIterator gbegin, gend; g->allNodes(gbegin, gend); for (; gbegin != gend; ++gbegin) { - SliceNode::Ptr n = boost::static_pointer_cast(*gbegin); + SliceNode::Ptr n = dyncompat::static_pointer_cast(*gbegin); if (n->assign() == memLoc) { continue; } @@ -481,7 +485,7 @@ bool JumpTableFormatPred::adjustSliceFrame(Slicer::SliceFrame &frame, SliceNode: n->outs(nbegin, nend); parsing_printf("\tadd %s to active map\n", src.format().c_str()); for (; nbegin != nend; ++nbegin) { - SliceNode::Ptr next = boost::static_pointer_cast(*nbegin); + SliceNode::Ptr next = dyncompat::static_pointer_cast(*nbegin); frame.active[src].push_back(Slicer::Element(next->block(), next->func(), src, next->assign())); if (n->assign()->out() != src) { aliases[next->assign()] = make_pair(VariableAST::create(Variable(n->assign()->out())), VariableAST::create(Variable(src))); diff --git a/parseAPI/src/JumpTableFormatPred.h b/parseAPI/src/JumpTableFormatPred.h index bce40e1fb7..10666d7cd7 100644 --- a/parseAPI/src/JumpTableFormatPred.h +++ b/parseAPI/src/JumpTableFormatPred.h @@ -1,6 +1,8 @@ #ifndef JUMP_TABLE_FORMAT_PRED_H #define JUMP_TABLE_FORMAT_PRED_H +#include +#include #include "CFG.h" #include "slicing.h" #include "Edge.h" diff --git a/parseAPI/src/JumpTableIndexPred.C b/parseAPI/src/JumpTableIndexPred.C index 8be886ee07..e16e6e8a42 100644 --- a/parseAPI/src/JumpTableIndexPred.C +++ b/parseAPI/src/JumpTableIndexPred.C @@ -1,3 +1,4 @@ +#include #include "dyntypes.h" #include "Node.h" #include "Graph.h" @@ -149,7 +150,7 @@ GraphPtr JumpTableIndexPred::BuildAnalysisGraph(set &visitedEdg // Start from each node to do DFS and build edges newG->allNodes(gbegin, gend); for (; gbegin != gend; ++gbegin) { - SliceNode::Ptr node = boost::static_pointer_cast(*gbegin); + SliceNode::Ptr node = dyncompat::static_pointer_cast(*gbegin); BuildEdges(node, targetMap, newG, visitedEdges); } parsing_printf("\t\t calculate edges in the new graph\n"); @@ -159,7 +160,7 @@ GraphPtr JumpTableIndexPred::BuildAnalysisGraph(set &visitedEdg newG->addNode(virtualExit); newG->allNodes(gbegin, gend); for (; gbegin != gend; ++gbegin) { - SliceNode::Ptr cur = boost::static_pointer_cast(*gbegin); + SliceNode::Ptr cur = dyncompat::static_pointer_cast(*gbegin); if (!cur->hasOutEdges() && cur != virtualExit) { newG->insertPair(cur, virtualExit, TypedSliceEdge::create(cur, virtualExit, FALLTHROUGH)); } @@ -218,7 +219,7 @@ bool JumpTableIndexPred::addNodeCallback(AssignmentPtr ap, set // that in the future we can match a // corresponding write to identify aliasing if (ap->insn().readsMemory() && expandRet.first->getID() == AST::V_RoseAST) { - RoseAST::Ptr roseAST = boost::static_pointer_cast(expandRet.first); + RoseAST::Ptr roseAST = dyncompat::static_pointer_cast(expandRet.first); if (roseAST->val().op == ROSEOperation::derefOp) { readAST.push_back(expandRet.first); } @@ -256,9 +257,9 @@ bool JumpTableIndexPred::IsIndexBounded(GraphPtr slice, parsing_printf("WARNING: Do not find exit node for analyzing indirect jump at %lx ....\n", block->last()); return false; } - SliceNode::Ptr virtualExit = boost::static_pointer_cast(*exitBegin); + SliceNode::Ptr virtualExit = dyncompat::static_pointer_cast(*exitBegin); virtualExit->ins(srcBegin, srcEnd); - SliceNode::Ptr jumpNode = boost::static_pointer_cast(*srcBegin); + SliceNode::Ptr jumpNode = dyncompat::static_pointer_cast(*srcBegin); BoundFact *bf = bfc.GetBoundFactOut(virtualExit); VariableAST::Ptr i = VariableAST::create(Variable(index)); diff --git a/parseAPI/src/JumpTableIndexPred.h b/parseAPI/src/JumpTableIndexPred.h index f933eb5aac..8919cb35c0 100644 --- a/parseAPI/src/JumpTableIndexPred.h +++ b/parseAPI/src/JumpTableIndexPred.h @@ -1,6 +1,8 @@ #ifndef JUMP_TABLE_INDEX_PRED_H #define JUMP_TABLE_INDEX_PRED_H +#include +#include #include "CFG.h" #include "slicing.h" #include "Edge.h" @@ -55,7 +57,7 @@ class TypedSliceEdge: public Dyninst::Edge { ParseAPI::EdgeTypeEnum t) : Dyninst::Edge(source, target), type_(t) {} public: - typedef boost::shared_ptr Ptr; + typedef dyncompat::shared_ptr Ptr; static TypedSliceEdge::Ptr create(SliceNode::Ptr source, SliceNode::Ptr target, ParseAPI::EdgeTypeEnum t) { diff --git a/parseAPI/src/Loop.C b/parseAPI/src/Loop.C index bef4023e4a..ec7f0d5944 100644 --- a/parseAPI/src/Loop.C +++ b/parseAPI/src/Loop.C @@ -32,7 +32,6 @@ #include #include #include -#include "common/src/std_namesp.h" #include #include #include "CFG.h" diff --git a/parseAPI/src/LoopAnalyzer.C b/parseAPI/src/LoopAnalyzer.C index f3b748857c..3d5fddf136 100644 --- a/parseAPI/src/LoopAnalyzer.C +++ b/parseAPI/src/LoopAnalyzer.C @@ -28,6 +28,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include #include #include diff --git a/parseAPI/src/LoopAnalyzer.h b/parseAPI/src/LoopAnalyzer.h index 34fa1a7d95..dab7574991 100644 --- a/parseAPI/src/LoopAnalyzer.h +++ b/parseAPI/src/LoopAnalyzer.h @@ -33,6 +33,7 @@ #include #include +#include #include "Annotatable.h" #include "CFG.h" diff --git a/parseAPI/src/ParseCallback.C b/parseAPI/src/ParseCallback.C index 830b3814fa..8603218931 100644 --- a/parseAPI/src/ParseCallback.C +++ b/parseAPI/src/ParseCallback.C @@ -186,7 +186,7 @@ void ParseCallbackManager::overlapping_blocks(Block *a, Block *b) { } void ParseCallbackManager::newfunction_retstatus(Function *f) { - boost::lock_guard g(*f); + dyncompat::lock_guard g(*f); for (iterator iter = begin(); iter != end(); ++iter) (*iter)->newfunction_retstatus(f); } diff --git a/parseAPI/src/ParseData.C b/parseAPI/src/ParseData.C index 3144431b21..8bcfbacd89 100644 --- a/parseAPI/src/ParseData.C +++ b/parseAPI/src/ParseData.C @@ -27,6 +27,7 @@ * License along with this library; if not, write to the Free Software * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include "ParseData.h" #include "Parser.h" #include "CodeObject.h" diff --git a/parseAPI/src/ParseData.h b/parseAPI/src/ParseData.h index 7d84ff7533..b31ab1c688 100644 --- a/parseAPI/src/ParseData.h +++ b/parseAPI/src/ParseData.h @@ -34,6 +34,8 @@ #include #include +#include +#include #include #include "dyntypes.h" @@ -44,10 +46,10 @@ #include "ParserDetails.h" #include "debug_parse.h" -#include -#include -#include -#include +#include +#include +#include +#include #include "concurrent.h" @@ -61,7 +63,7 @@ class ParseData; /** Describes a saved frame during recursive parsing **/ // Parsing data for a function. -class ParseFrame : public boost::lockable_adapter { +class ParseFrame : public dyncompat::lockable_adapter { public: enum Status { UNPARSED, @@ -100,12 +102,12 @@ class ParseFrame : public boost::lockable_adapter { ParseWorkBundle *b, Function* shared_func); void pushWork(ParseWorkElem * elem) { - boost::lock_guard g(*this); + dyncompat::lock_guard g(*this); parsing_printf("\t pushing work element for block %p, edge %p, target %p\n", (void*)elem->cur(), (void*)elem->edge(), (void*)elem->target()); worklist.push(elem); } ParseWorkElem * popWork() { - boost::lock_guard g(*this); + dyncompat::lock_guard g(*this); ParseWorkElem * ret = NULL; if(!worklist.empty()) { ret = worklist.top(); @@ -115,7 +117,7 @@ class ParseFrame : public boost::lockable_adapter { } void pushDelayedWork(ParseWorkElem * elem, Function * ct) { - boost::lock_guard g(*this); + dyncompat::lock_guard g(*this); delayedWork.insert(make_pair(elem, ct)); } @@ -162,7 +164,7 @@ class ParseFrame : public boost::lockable_adapter { void set_status(Status); void set_internal_status(Status s) { _status.store(s); } private: - boost::atomic _status; + dyncompat::atomic _status; ParseData * _pd; }; diff --git a/parseAPI/src/Parser.C b/parseAPI/src/Parser.C index 37276bd47b..4a83b8dfb4 100644 --- a/parseAPI/src/Parser.C +++ b/parseAPI/src/Parser.C @@ -49,11 +49,11 @@ #include "util.h" #include "debug_parse.h" #include "IndirectAnalyzer.h" - -#include +#include "registers/ppc32_regs.h" +#include "registers/abstract_regs.h" +#include #include - -#include "tbb/concurrent_vector.h" +#include "instructionAPI/h/syscalls.h" using namespace std; using namespace Dyninst; @@ -349,7 +349,7 @@ Parser::parse_edges( vector< ParseWorkElem * > & work_elems ) if (elem->order() == ParseWorkElem::call_fallthrough) { ParseAPI::Edge *callEdge = NULL; - boost::lock_guard g(*src); + dyncompat::lock_guard g(*src); Block::edgelist trgs = src->targets(); for (Block::edgelist::iterator eit = trgs.begin(); eit != trgs.end(); @@ -447,9 +447,9 @@ Parser::ProcessOneFrame(ParseFrame* pf, bool recursive) { LockFreeQueueItem *frame_list = 0; assert(pf->func); { - boost::lock_guard g(*pf); + dyncompat::lock_guard g(*pf); #ifdef ADD_PARSE_FRAME_TIMERS - boost::timer::cpu_timer t; + std::chrono::steady_clock t; t.start(); #endif parse_frame(*pf,recursive); @@ -578,7 +578,7 @@ LockFreeQueueItem *Parser::postProcessFrame(ParseFrame *pf, bool r continue; } a->second.insert(pf); - delayed_frames_changed.exchange(true, boost::memory_order_relaxed); + delayed_frames_changed.exchange(true, std::memory_order_relaxed); } } } else { @@ -804,7 +804,7 @@ void Parser::cleanup_frames() { bool Parser::finalize(Function *f) { - boost::lock_guard g(*f); + dyncompat::lock_guard g(*f); if(f->_cache_valid) { return true; } @@ -852,14 +852,7 @@ Parser::finalize(Function *f) Block* trg_block = e->trg(); - bool trg_has_call_edge = false; - Block::edgelist sources; - trg_block->copy_sources(sources); - for (auto e2: sources) - if (e2->type() == CALL) { - trg_has_call_edge = true; - break; - } + bool trg_has_call_edge = trg_block->hasCallSource(); // Rule 1: // If an edge is currently not a tail call, but the edge target has a CALL incoming edge, @@ -884,7 +877,7 @@ Parser::finalize(Function *f) // the edge is a tail call. // For example, if a jump from .text to .plt (different sections), then // no matter what, this edge is a tail call. - if (trg_func->region() != b->region()) continue; + if (trg_func && trg_func->region() != b->region()) continue; // Rule 2: // Find a tail call targeting a block within the same function. @@ -900,13 +893,7 @@ Parser::finalize(Function *f) // Rule 3: // If an edge is currently a tail call, but the edge target has only the current edge as incoming edges, // we treat this as not tail call. - bool only_incoming = true; - for (auto e2: sources) - if (e2 != e) { - only_incoming = false; - break; - } - if (only_incoming) { + if (trg_block->getOnlyIncomingEdge() == e) { e->_type._interproc = false; parsing_printf("from %lx to %lx, marked as not tail call (single entry), re-finalize\n", b->last(), e->trg()->start()); return false; @@ -933,9 +920,11 @@ Parser::finalize(Function *f) b->copy_targets(targets); for (auto e : targets) { if (!e->interproc() && (e->type() == INDIRECT || e->type() == DIRECT)) { + if (b->last() != e->trg()->start()) { // if not an instruction that branches to itself e->_type._interproc = true; parsing_printf("from %lx to %lx, marked as tail call (jump at entry), re-finalize\n", b->last(), e->trg()->start()); return false; + } } } } @@ -995,7 +984,7 @@ Parser::finalize(Function *f) eit != edges.end(); eit++) { - boost::lock_guard blockGuard(*(*eit)->src()); + dyncompat::lock_guard blockGuard(*(*eit)->src()); if (2 > (*eit)->src()->targets().size()) { Block *ft = _parse_data->findBlock((*eit)->src()->region(), (*eit)->src()->end()); @@ -1023,6 +1012,21 @@ Parser::finalize() finalize_funcs(discover_funcs); clean_bogus_funcs(discover_funcs); + // We need to redo finalization one more time to get correct + // function boundaries. This is intended to handle tail call + // correction. Suppose function A contains function B, and + // function B tail calls C. + // Further, we assume that parseAPI fails to identify the tail call + // in B. Then during finalizaiton, we can correct the tail call + // either when we finalize A or B, but not both. Therefore, + // after finalization, either A or B would have incorrect function + // boundary. Therefore, we recompute function boundary. + // In addition, there is no need for a loop to redo finalization + // as there would be no more tail call correction. + // We only need to get correct function boundaries. + finalize_funcs(hint_funcs); + finalize_funcs(discover_funcs); + for (auto it = hint_funcs.begin(); it != hint_funcs.end(); ++it) if (deleted_func.find(*it) == deleted_func.end()) { sorted_funcs.insert(*it); @@ -1489,13 +1493,13 @@ Parser::parse_frame_one_iteration(ParseFrame &frame, bool recursive) { // check for system call FT ParseAPI::Edge* edge = work->edge(); Block::Insns blockInsns; - // boost::lock_guard src_guard(*edge->src()); + // dyncompat::lock_guard src_guard(*edge->src()); edge->src()->getInsns(blockInsns); auto prev = blockInsns.rbegin(); InstructionAPI::Instruction prevInsn = prev->second; bool is_nonret = false; - if (prevInsn.getOperation().getID() == e_syscall) { + if (Dyninst::InstructionAPI::isSystemCall(prevInsn)) { Address src = edge->src()->lastInsnAddr(); @@ -1765,6 +1769,13 @@ Parser::parse_frame_one_iteration(ParseFrame &frame, bool recursive) { // this is special treatment for non-returning instruction // examples are amdgpu_op_s_endpgm and amddgpu_op_s_endpgm_saved //cout << "calling endblock for non-returning instruction " << std::hex <getAddr() << endl; + // + + + parsing_printf("[%s:%d] gpu exit insn 0x%lx: %s \n", + FILE__,__LINE__,curAddr, ah->getInstruction().format().c_str() ); + + end_block(cur,ahPtr); break; } @@ -1847,27 +1858,6 @@ Parser::parse_frame_one_iteration(ParseFrame &frame, bool recursive) { if (!set_edge_parsing_status(frame,cur->last(), cur)) break; link_addr(ahPtr->getAddr(), _sink, DIRECT, true, func); break; - } else if ( ah->isInterruptOrSyscall() ) { - // 5. Raising instructions - end_block(cur,ahPtr); - if (!set_edge_parsing_status(frame,cur->last(), cur)) break; - ParseAPI::Edge* newedge = link_tempsink(cur, FALLTHROUGH); - parsing_printf("[%s:%d] pushing %lx onto worklist\n", - FILE__,__LINE__,curAddr); - frame.pushWork( - frame.mkWork( - NULL, - newedge, - ahPtr->getAddr(), - ahPtr->getNextAddr(), - true, - false) - ); - if (unlikely(func->obj()->defensiveMode())) { - fprintf(stderr,"parsed bluepill insn sysenter or syscall " - "in defensive mode at %lx\n",curAddr); - } - break; } else if (unlikely(func->obj()->defensiveMode())) { if (!_pcb.hasWeirdInsns(func) && ah->isGarbageInsn()) { // add instrumentation at this addr so we can @@ -1995,7 +1985,7 @@ Parser::block_at(ParseFrame &frame, #ifdef ENABLE_RACE_DETECTION // this lock causes deadlock when running in parallel, but it is // useful for suppressing unimportant races on the iterator - boost::lock_guard g(*owner); + dyncompat::lock_guard g(*owner); #endif // An already existing block auto iter = frame.leadersToBlock.find(addr); @@ -2420,7 +2410,7 @@ void Parser::resumeFrames(Function * func, LockFreeQueue & work) } // remove func from delayedFrames map delayed_frames.erase(a); - delayed_frames_changed.exchange(true, boost::memory_order_relaxed); + delayed_frames_changed.exchange(true, std::memory_order_relaxed); } } diff --git a/parseAPI/src/Parser.h b/parseAPI/src/Parser.h index 751c65c37b..d6b7ee7d1e 100644 --- a/parseAPI/src/Parser.h +++ b/parseAPI/src/Parser.h @@ -50,8 +50,8 @@ #include "ParseCallback.h" #include "common/src/dthread.h" -#include -#include +#include +#include #include using namespace std; @@ -86,7 +86,7 @@ namespace Dyninst { // All allocated frames LockFreeQueue frames; - boost::atomic delayed_frames_changed; + dyncompat::atomic delayed_frames_changed; dyn_c_hash_map > delayed_frames; // differentiate those provided via hints and @@ -101,7 +101,7 @@ namespace Dyninst { dyn_hash_map plt_entries; // a sink block for unbound edges - boost::atomic _sink; + dyncompat::atomic _sink; #ifdef ADD_PARSE_FRAME_TIMERS dyn_c_hash_map time_histogram; #endif @@ -273,7 +273,7 @@ namespace Dyninst { Mutex parse_mutex; - struct NewFrames : public std::set, public boost::lockable_adapter {}; + struct NewFrames : public std::set, public dyncompat::lockable_adapter {}; LockFreeQueueItem *ProcessOneFrame(ParseFrame *pf, bool recursive); diff --git a/parseAPI/src/ParserDetails.C b/parseAPI/src/ParserDetails.C index 7a0aefbda7..7a96b2cdb5 100644 --- a/parseAPI/src/ParserDetails.C +++ b/parseAPI/src/ParserDetails.C @@ -27,6 +27,7 @@ * License along with this library; if not, write to the Free Software * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include "ParseData.h" #include "CodeObject.h" @@ -330,7 +331,7 @@ void Parser::ProcessUnresBranchEdge( bool valid; Address addr; - boost::tie(valid, addr) = ah->getCFT(); + std::tie(valid, addr) = ah->getCFT(); if (!valid) { det.data.unres.dynamic = true; det.data.unres.absolute_address = true; diff --git a/parseAPI/src/ParserDetails.h b/parseAPI/src/ParserDetails.h index 50ba0a7f4a..c560374a5e 100644 --- a/parseAPI/src/ParserDetails.h +++ b/parseAPI/src/ParserDetails.h @@ -30,6 +30,7 @@ #ifndef _PARSER_DETAILS_H_ #define _PARSER_DETAILS_H_ +#include #include "IA_IAPI.h" namespace Dyninst { @@ -273,19 +274,19 @@ class ParseWorkElem }; private: - ParseWorkBundle * _bundle; - Edge * _edge; - Address _src; - Address _targ; - bool _can_resolve; - bool _tailcall; - parse_work_order _order; - bool _call_processed; + ParseWorkBundle * _bundle{}; + Edge * _edge{}; + Address _src{}; + Address _targ{}; + bool _can_resolve{}; + bool _tailcall{}; + parse_work_order _order{}; + bool _call_processed{}; // Data for continuing parsing jump tables - Block* _cur; - InsnAdapter::IA_IAPI* _ah; - Function * _shared_func; + Block* _cur{}; + InsnAdapter::IA_IAPI* _ah{}; + Function * _shared_func{}; }; // ParseWorkElem container diff --git a/parseAPI/src/ProbabilisticParser.C b/parseAPI/src/ProbabilisticParser.C index 0c2c0bbc93..22eb2cc434 100644 --- a/parseAPI/src/ProbabilisticParser.C +++ b/parseAPI/src/ProbabilisticParser.C @@ -39,7 +39,7 @@ #include #include "entryIDs.h" -#include "dyn_regs.h" +#include "registers/x86_64_regs.h" #include "InstructionDecoder.h" #include "Instruction.h" diff --git a/parseAPI/src/ProbabilisticParser.h b/parseAPI/src/ProbabilisticParser.h index 6f01d6358e..37db29f3d2 100644 --- a/parseAPI/src/ProbabilisticParser.h +++ b/parseAPI/src/ProbabilisticParser.h @@ -39,6 +39,8 @@ #include "Parser.h" +#include +#include #include #include #include @@ -49,7 +51,6 @@ #include "common/h/dyntypes.h" #include "CodeSource.h" #include "entryIDs.h" -#include "RegisterIDs.h" #include "CFG.h" #include "Instruction.h" @@ -86,7 +87,7 @@ namespace hd { #define ARG2_MASK (((uint64_t)(1< terms; - double w; - bool prefix; + double w{}; + bool prefix{}; Idiom() {} Idiom(std::string f, double weight, bool pre); bool operator < (const Idiom& i) const; @@ -114,9 +115,9 @@ class IdiomPrefixTree { typedef std::vector > ChildrenType; typedef dyn_hash_map ChildrenByEntryID; private: - ChildrenByEntryID childrenClusters; - double w; - bool feature; + ChildrenByEntryID childrenClusters{}; + double w{}; + bool feature{}; void addIdiom(int cur, const Idiom& idiom); @@ -133,11 +134,11 @@ class IdiomPrefixTree { }; class IdiomModel { - IdiomPrefixTree normal; - IdiomPrefixTree prefix; + IdiomPrefixTree normal{}; + IdiomPrefixTree prefix{}; - double bias; - double prob_threshold; + double bias{}; + double prob_threshold{}; IdiomModel() {} public: diff --git a/parseAPI/src/StackTamperVisitor.h b/parseAPI/src/StackTamperVisitor.h index b30c374161..4bcb563175 100644 --- a/parseAPI/src/StackTamperVisitor.h +++ b/parseAPI/src/StackTamperVisitor.h @@ -35,7 +35,7 @@ #include #include -#include "dataflowAPI/h/Absloc.h" // MemEmulator analysis +#include "dataflowAPI/h/Absloc.h" #include "dataflowAPI/h/AbslocInterface.h" // And more of the same #include "dataflowAPI/h/SymEval.h" // Variable class #include "common/h/DynAST.h" diff --git a/parseAPI/src/SymLiteCodeSource.C b/parseAPI/src/SymLiteCodeSource.C index 9bb02a62de..67a864003c 100644 --- a/parseAPI/src/SymLiteCodeSource.C +++ b/parseAPI/src/SymLiteCodeSource.C @@ -1,5 +1,5 @@ /* - * Copyright (c) 1996-2021 Barton P. Miller + * See the dyninst/COPYRIGHT file for copyright information. * * We provide the Paradyn Parallel Performance Tools (below * described as "Paradyn") on an AS IS basis, and do not warrant its @@ -28,10 +28,11 @@ * License along with this library; if not, write to the Free Software * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include #include -#include +#include #include "common/src/stats.h" #include "dyntypes.h" @@ -148,7 +149,7 @@ bool SymReaderCodeRegion::isCode(const Address addr) const { if(!contains(addr)) return false; - return true; + return _region->perms & PF_X; /* // XXX this is the predicate from SymReader::isCode(a) + @@ -163,7 +164,7 @@ bool SymReaderCodeRegion::isData(const Address addr) const { if(!contains(addr)) return false; - return true; + return !(_region->perms & PF_X); /* @@ -174,6 +175,16 @@ SymReaderCodeRegion::isData(const Address addr) const */ } +bool +SymReaderCodeRegion::isReadOnly(const Address addr) const +{ + if (!contains(addr)) { + return false; + } + + return !(_region->perms & PF_W); +} + Address SymReaderCodeRegion::offset() const { @@ -400,7 +411,7 @@ inline void SymReaderCodeSource::overlapping_warn(const char * file, unsigned line) const { if(regionsOverlap()) { - fprintf(stderr,"Invocation of routine at %s:%d is ambiguous for " + fprintf(stderr,"Invocation of routine at %s:%u is ambiguous for " "binaries with overlapping code regions\n", file,line); } @@ -484,6 +495,18 @@ SymReaderCodeSource::isData(const Address addr) const return false; } +bool +SymReaderCodeSource::isReadOnly(const Address addr) const +{ + overlapping_warn(FILE__,__LINE__); + + CodeRegion * cr = lookup_region(addr); + if(cr) + return cr->isReadOnly(addr); + else + return false; +} + Address SymReaderCodeSource::offset() const { diff --git a/parseAPI/src/SymbolicExpression.C b/parseAPI/src/SymbolicExpression.C index e44a0582de..fcfd55faa5 100644 --- a/parseAPI/src/SymbolicExpression.C +++ b/parseAPI/src/SymbolicExpression.C @@ -1,3 +1,4 @@ +#include #include "SymbolicExpression.h" #include "SymEval.h" #include "Absloc.h" @@ -50,15 +51,15 @@ bool SymbolicExpression::ReadMemory(Address addr, uint64_t &v, int ) { }*/ AST::Ptr SymbolicExpression::SimplifyRoot(AST::Ptr ast, Address addr, bool keepMultiOne) { if (ast->getID() == AST::V_RoseAST) { - RoseAST::Ptr roseAST = boost::static_pointer_cast(ast); + RoseAST::Ptr roseAST = dyncompat::static_pointer_cast(ast); switch (roseAST->val().op) { case ROSEOperation::invertOp: if (roseAST->child(0)->getID() == AST::V_RoseAST) { - RoseAST::Ptr child = boost::static_pointer_cast(roseAST->child(0)); + RoseAST::Ptr child = dyncompat::static_pointer_cast(roseAST->child(0)); if (child->val().op == ROSEOperation::invertOp) return child->child(0); } else if (roseAST->child(0)->getID() == AST::V_ConstantAST) { - ConstantAST::Ptr child = boost::static_pointer_cast(roseAST->child(0)); + ConstantAST::Ptr child = dyncompat::static_pointer_cast(roseAST->child(0)); size_t size = child->val().size; uint64_t val = child->val().val; if (size < 64) { @@ -74,22 +75,30 @@ AST::Ptr SymbolicExpression::SimplifyRoot(AST::Ptr ast, Address addr, bool keepM } case ROSEOperation::extractOp: { if (roseAST->child(0)->getID() == AST::V_ConstantAST) { - size_t size = roseAST->val().size; - ConstantAST::Ptr child0 = boost::static_pointer_cast(roseAST->child(0)); - uint64_t val = child0->val().val; - // clip value according to size, but do not clip size 0 values - // and size 64 values - uint64_t clipped_value = (size ==0 ||size ==64 ) ? - val : val & ((1ULL << size) -1); - - return ConstantAST::create(Constant(clipped_value, size)); + assert(roseAST->child(1)->getID() == AST::V_ConstantAST); + assert(roseAST->child(2)->getID() == AST::V_ConstantAST); + + + ConstantAST::Ptr from = ConstantAST::convert(roseAST->child(1)); + ConstantAST::Ptr to = ConstantAST::convert(roseAST->child(2)); + ConstantAST::Ptr val = dyncompat::static_pointer_cast(roseAST->child(0)); + + auto lowBitPos{from->val().val}; + auto highBitPos{to->val().val}; + uint64_t newValue{val->val().val}; + if(highBitPos < 64) + newValue &= ((1ULL << highBitPos) - 1); // zero highBitPos and higher + newValue >>= lowBitPos; // shift to bit 0, eliminating unwanted low bits + + return ConstantAST::create(Constant(newValue, highBitPos - lowBitPos)); } + return roseAST->child(0); } case ROSEOperation::signExtendOp: { if (roseAST->child(0)->getID() == AST::V_ConstantAST && roseAST->child(1)->getID() == AST::V_ConstantAST) { - ConstantAST::Ptr child0 = boost::static_pointer_cast(roseAST->child(0)); - ConstantAST::Ptr child1 = boost::static_pointer_cast(roseAST->child(1)); + ConstantAST::Ptr child0 = dyncompat::static_pointer_cast(roseAST->child(0)); + ConstantAST::Ptr child1 = dyncompat::static_pointer_cast(roseAST->child(1)); uint64_t val = child0->val().val; if (val & (1 << (child0->val().size - 1))) { switch (child0->val().size) { @@ -110,20 +119,20 @@ AST::Ptr SymbolicExpression::SimplifyRoot(AST::Ptr ast, Address addr, bool keepM } case ROSEOperation::concatOp: { if (roseAST->child(0)->getID() == AST::V_ConstantAST && roseAST->child(1)->getID() == AST::V_ConstantAST) { - ConstantAST::Ptr child0 = boost::static_pointer_cast(roseAST->child(0)); - ConstantAST::Ptr child1 = boost::static_pointer_cast(roseAST->child(1)); + ConstantAST::Ptr child0 = dyncompat::static_pointer_cast(roseAST->child(0)); + ConstantAST::Ptr child1 = dyncompat::static_pointer_cast(roseAST->child(1)); uint64_t val = (child1->val().val << child0->val().size) + child0->val().val; size_t size = child1->val().size + child0->val().size; return ConstantAST::create(Constant(val,size)); } if (roseAST->child(1)->getID() == AST::V_ConstantAST) { - ConstantAST::Ptr child1 = boost::static_pointer_cast(roseAST->child(1)); + ConstantAST::Ptr child1 = dyncompat::static_pointer_cast(roseAST->child(1)); if (child1->val().val == 0) { return roseAST->child(0); } } if (roseAST->child(1)->getID() == AST::V_RoseAST) { - RoseAST::Ptr child1 = boost::static_pointer_cast(roseAST->child(1)); + RoseAST::Ptr child1 = dyncompat::static_pointer_cast(roseAST->child(1)); if (child1->val().op == ROSEOperation::ifOp) break; } return roseAST->child(0); @@ -132,8 +141,8 @@ AST::Ptr SymbolicExpression::SimplifyRoot(AST::Ptr ast, Address addr, bool keepM // We simplify the addition as much as we can // Case 1: two constants if (roseAST->child(0)->getID() == AST::V_ConstantAST && roseAST->child(1)->getID() == AST::V_ConstantAST) { - ConstantAST::Ptr child0 = boost::static_pointer_cast(roseAST->child(0)); - ConstantAST::Ptr child1 = boost::static_pointer_cast(roseAST->child(1)); + ConstantAST::Ptr child0 = dyncompat::static_pointer_cast(roseAST->child(0)); + ConstantAST::Ptr child1 = dyncompat::static_pointer_cast(roseAST->child(1)); uint64_t val = child0->val().val + child1->val().val; size_t size; if (child0->val().size > child1->val().size) @@ -144,22 +153,22 @@ AST::Ptr SymbolicExpression::SimplifyRoot(AST::Ptr ast, Address addr, bool keepM } // Case 2: anything adding zero stays the same if (roseAST->child(0)->getID() == AST::V_ConstantAST) { - ConstantAST::Ptr child = boost::static_pointer_cast(roseAST->child(0)); + ConstantAST::Ptr child = dyncompat::static_pointer_cast(roseAST->child(0)); if (child->val().val == 0) return roseAST->child(1); } if (roseAST->child(1)->getID() == AST::V_ConstantAST) { - ConstantAST::Ptr child = boost::static_pointer_cast(roseAST->child(1)); + ConstantAST::Ptr child = dyncompat::static_pointer_cast(roseAST->child(1)); if (child->val().val == 0) return roseAST->child(0); } // Case 3: if v + v * c = v * (c+1), where v is a variable and c is a constant if (roseAST->child(0)->getID() == AST::V_VariableAST && roseAST->child(1)->getID() == AST::V_RoseAST) { - RoseAST::Ptr rOp = boost::static_pointer_cast(roseAST->child(1)); + RoseAST::Ptr rOp = dyncompat::static_pointer_cast(roseAST->child(1)); if (rOp->val().op == ROSEOperation::uMultOp || rOp->val().op == ROSEOperation::sMultOp) { if (rOp->child(0)->getID() == AST::V_VariableAST && rOp->child(1)->getID() == AST::V_ConstantAST) { - VariableAST::Ptr varAST1 = boost::static_pointer_cast(roseAST->child(0)); - VariableAST::Ptr varAST2 = boost::static_pointer_cast(rOp->child(0)); + VariableAST::Ptr varAST1 = dyncompat::static_pointer_cast(roseAST->child(0)); + VariableAST::Ptr varAST2 = dyncompat::static_pointer_cast(rOp->child(0)); if (varAST1->val().reg == varAST2->val().reg) { - ConstantAST::Ptr oldC = boost::static_pointer_cast(rOp->child(1)); + ConstantAST::Ptr oldC = dyncompat::static_pointer_cast(rOp->child(1)); ConstantAST::Ptr newC = ConstantAST::create(Constant(oldC->val().val + 1, oldC->val().size)); RoseAST::Ptr newRoot = RoseAST::create(ROSEOperation(rOp->val()), varAST1, newC); return newRoot; @@ -171,31 +180,31 @@ AST::Ptr SymbolicExpression::SimplifyRoot(AST::Ptr ast, Address addr, bool keepM case ROSEOperation::sMultOp: case ROSEOperation::uMultOp: if (roseAST->child(0)->getID() == AST::V_ConstantAST && roseAST->child(1)->getID() == AST::V_ConstantAST) { - ConstantAST::Ptr child0 = boost::static_pointer_cast(roseAST->child(0)); - ConstantAST::Ptr child1 = boost::static_pointer_cast(roseAST->child(1)); + ConstantAST::Ptr child0 = dyncompat::static_pointer_cast(roseAST->child(0)); + ConstantAST::Ptr child1 = dyncompat::static_pointer_cast(roseAST->child(1)); return ConstantAST::create(Constant(child0->val().val * child1->val().val, 64)); } if (roseAST->child(0)->getID() == AST::V_ConstantAST) { - ConstantAST::Ptr child0 = boost::static_pointer_cast(roseAST->child(0)); + ConstantAST::Ptr child0 = dyncompat::static_pointer_cast(roseAST->child(0)); if (child0->val().val == 1 && !keepMultiOne) return roseAST->child(1); } if (roseAST->child(1)->getID() == AST::V_ConstantAST) { - ConstantAST::Ptr child1 = boost::static_pointer_cast(roseAST->child(1)); + ConstantAST::Ptr child1 = dyncompat::static_pointer_cast(roseAST->child(1)); if (child1->val().val == 1 && !keepMultiOne) return roseAST->child(0); } break; case ROSEOperation::xorOp: if (roseAST->child(0)->getID() == AST::V_VariableAST && roseAST->child(1)->getID() == AST::V_VariableAST) { - VariableAST::Ptr child0 = boost::static_pointer_cast(roseAST->child(0)); - VariableAST::Ptr child1 = boost::static_pointer_cast(roseAST->child(1)); + VariableAST::Ptr child0 = dyncompat::static_pointer_cast(roseAST->child(0)); + VariableAST::Ptr child1 = dyncompat::static_pointer_cast(roseAST->child(1)); if (child0->val() == child1->val()) { return ConstantAST::create(Constant(0 , 32)); } } else if (roseAST->child(0)->getID() == AST::V_ConstantAST && roseAST->child(1)->getID() == AST::V_ConstantAST) { - ConstantAST::Ptr child0 = boost::static_pointer_cast(roseAST->child(0)); - ConstantAST::Ptr child1 = boost::static_pointer_cast(roseAST->child(1)); + ConstantAST::Ptr child0 = dyncompat::static_pointer_cast(roseAST->child(0)); + ConstantAST::Ptr child1 = dyncompat::static_pointer_cast(roseAST->child(1)); return ConstantAST::create(Constant(child0->val().val ^ child1->val().val, 64)); } @@ -206,7 +215,7 @@ AST::Ptr SymbolicExpression::SimplifyRoot(AST::Ptr ast, Address addr, bool keepM // However, dereference longer than 8-bit should be regarded the same. if (roseAST->child(0)->getID() == AST::V_ConstantAST) { uint64_t val = 0; - ConstantAST::Ptr c = boost::static_pointer_cast(roseAST->child(0)); + ConstantAST::Ptr c = dyncompat::static_pointer_cast(roseAST->child(0)); Address a = c->val().val; if (ReadMemory(a, val, roseAST->val().size / 8)) { return ConstantAST::create(Constant(val, 64)); @@ -220,33 +229,39 @@ AST::Ptr SymbolicExpression::SimplifyRoot(AST::Ptr ast, Address addr, bool keepM case ROSEOperation::shiftLOp: case ROSEOperation::rotateLOp: if (roseAST->child(0)->getID() == AST::V_ConstantAST && roseAST->child(1)->getID() == AST::V_ConstantAST) { - ConstantAST::Ptr child0 = boost::static_pointer_cast(roseAST->child(0)); - ConstantAST::Ptr child1 = boost::static_pointer_cast(roseAST->child(1)); + ConstantAST::Ptr child0 = dyncompat::static_pointer_cast(roseAST->child(0)); + ConstantAST::Ptr child1 = dyncompat::static_pointer_cast(roseAST->child(1)); return ConstantAST::create(Constant(child0->val().val << child1->val().val, 64)); } if (roseAST->child(1)->getID() == AST::V_ConstantAST) { parsing_printf("keep multi one %d\n", keepMultiOne); - ConstantAST::Ptr child1 = boost::static_pointer_cast(roseAST->child(1)); + ConstantAST::Ptr child1 = dyncompat::static_pointer_cast(roseAST->child(1)); if (child1->val().val == 0 && !keepMultiOne) return roseAST->child(0); } break; case ROSEOperation::andOp: if (roseAST->child(0)->getID() == AST::V_ConstantAST && roseAST->child(1)->getID() == AST::V_ConstantAST) { - ConstantAST::Ptr child0 = boost::static_pointer_cast(roseAST->child(0)); - ConstantAST::Ptr child1 = boost::static_pointer_cast(roseAST->child(1)); - return ConstantAST::create(Constant(child0->val().val & child1->val().val, 64)); + ConstantAST::Ptr child0 = dyncompat::static_pointer_cast(roseAST->child(0)); + ConstantAST::Ptr child1 = dyncompat::static_pointer_cast(roseAST->child(1)); + auto size0{child0->val().size}; + auto size1{child1->val().size}; + uint64_t newSize{std::max(size0,size1)}; + return ConstantAST::create(Constant(child0->val().val & child1->val().val, newSize)); } break; case ROSEOperation::orOp: if (roseAST->child(0)->getID() == AST::V_ConstantAST && roseAST->child(1)->getID() == AST::V_ConstantAST) { - ConstantAST::Ptr child0 = boost::static_pointer_cast(roseAST->child(0)); - ConstantAST::Ptr child1 = boost::static_pointer_cast(roseAST->child(1)); - return ConstantAST::create(Constant(child0->val().val | child1->val().val, 64)); + ConstantAST::Ptr child0 = dyncompat::static_pointer_cast(roseAST->child(0)); + ConstantAST::Ptr child1 = dyncompat::static_pointer_cast(roseAST->child(1)); + auto size0{child0->val().size}; + auto size1{child1->val().size}; + uint64_t newSize{std::max(size0,size1)}; + return ConstantAST::create(Constant(child0->val().val | child1->val().val, newSize)); } break; case ROSEOperation::ifOp: if (roseAST->child(0)->getID() == AST::V_ConstantAST) { - ConstantAST::Ptr c = boost::static_pointer_cast(roseAST->child(0)); + ConstantAST::Ptr c = dyncompat::static_pointer_cast(roseAST->child(0)); if (c->val().val != 0) { return roseAST->child(1); } else { @@ -257,13 +272,13 @@ AST::Ptr SymbolicExpression::SimplifyRoot(AST::Ptr ast, Address addr, bool keepM break; case ROSEOperation::shiftROp: if (roseAST->child(0)->getID() == AST::V_ConstantAST && roseAST->child(1)->getID() == AST::V_ConstantAST) { - ConstantAST::Ptr child0 = boost::static_pointer_cast(roseAST->child(0)); - ConstantAST::Ptr child1 = boost::static_pointer_cast(roseAST->child(1)); + ConstantAST::Ptr child0 = dyncompat::static_pointer_cast(roseAST->child(0)); + ConstantAST::Ptr child1 = dyncompat::static_pointer_cast(roseAST->child(1)); return ConstantAST::create(Constant(child0->val().val >> child1->val().val, 64)); } if (roseAST->child(1)->getID() == AST::V_ConstantAST) { parsing_printf("keep multi one %d\n", keepMultiOne); - ConstantAST::Ptr child1 = boost::static_pointer_cast(roseAST->child(1)); + ConstantAST::Ptr child1 = dyncompat::static_pointer_cast(roseAST->child(1)); if (child1->val().val == 0 && !keepMultiOne) return roseAST->child(0); } break; @@ -271,17 +286,17 @@ AST::Ptr SymbolicExpression::SimplifyRoot(AST::Ptr ast, Address addr, bool keepM case ROSEOperation::equalToZeroOp: if (roseAST->child(0)->getID() == AST::V_ConstantAST) { - ConstantAST::Ptr child0 = boost::static_pointer_cast(roseAST->child(0)); + ConstantAST::Ptr child0 = dyncompat::static_pointer_cast(roseAST->child(0)); if(child0->val().val == 0) - return ConstantAST::create(Constant(1, 64)); + return ConstantAST::create(Constant(1, 1)); else - return ConstantAST::create(Constant(0, 64)); + return ConstantAST::create(Constant(0, 1)); } break; case ROSEOperation::negateOp: if (roseAST->child(0)->getID() == AST::V_ConstantAST) { - ConstantAST::Ptr child0 = boost::static_pointer_cast(roseAST->child(0)); + ConstantAST::Ptr child0 = dyncompat::static_pointer_cast(roseAST->child(0)); return ConstantAST::create(Constant(~child0->val().val, 64)); } @@ -293,7 +308,7 @@ AST::Ptr SymbolicExpression::SimplifyRoot(AST::Ptr ast, Address addr, bool keepM } } else if (ast->getID() == AST::V_VariableAST) { - VariableAST::Ptr varAST = boost::static_pointer_cast(ast); + VariableAST::Ptr varAST = dyncompat::static_pointer_cast(ast); if (varAST->val().reg.absloc().isPC()) { MachRegister pc = varAST->val().reg.absloc().reg(); return ConstantAST::create(Constant(addr, getArchAddressWidth(pc.getArchitecture()) * 8)); @@ -305,7 +320,7 @@ AST::Ptr SymbolicExpression::SimplifyRoot(AST::Ptr ast, Address addr, bool keepM // compare two ast. return VariableAST::create(Variable(varAST->val().reg)); } else if (ast->getID() == AST::V_ConstantAST) { - ConstantAST::Ptr constAST = boost::static_pointer_cast(ast); + ConstantAST::Ptr constAST = dyncompat::static_pointer_cast(ast); size_t size = constAST->val().size; uint64_t val = constAST->val().val; @@ -341,7 +356,7 @@ bool SymbolicExpression::ContainAnAST(AST::Ptr root, AST::Ptr check) { AST::Ptr SymbolicExpression::DeepCopyAnAST(AST::Ptr ast) { if (ast->getID() == AST::V_RoseAST) { - RoseAST::Ptr roseAST = boost::static_pointer_cast(ast); + RoseAST::Ptr roseAST = dyncompat::static_pointer_cast(ast); AST::Children kids; unsigned totalChildren = ast->numChildren(); for (unsigned i = 0 ; i < totalChildren; ++i) { @@ -349,13 +364,13 @@ AST::Ptr SymbolicExpression::DeepCopyAnAST(AST::Ptr ast) { } return RoseAST::create(ROSEOperation(roseAST->val()), kids); } else if (ast->getID() == AST::V_VariableAST) { - VariableAST::Ptr varAST = boost::static_pointer_cast(ast); + VariableAST::Ptr varAST = dyncompat::static_pointer_cast(ast); return VariableAST::create(Variable(varAST->val())); } else if (ast->getID() == AST::V_ConstantAST) { - ConstantAST::Ptr constAST = boost::static_pointer_cast(ast); + ConstantAST::Ptr constAST = dyncompat::static_pointer_cast(ast); return ConstantAST::create(Constant(constAST->val())); } else if (ast->getID() == AST::V_BottomAST) { - BottomAST::Ptr bottomAST = boost::static_pointer_cast(ast); + BottomAST::Ptr bottomAST = dyncompat::static_pointer_cast(ast); return BottomAST::create(bottomAST->val()); } fprintf(stderr, "ast type %d, %s\n", ast->getID(), ast->format().c_str()); @@ -412,7 +427,7 @@ AST::Ptr SymbolicExpression::SubstituteAnAST(AST::Ptr ast, const mapgetID() == AST::V_VariableAST) { // If this variable is not in the aliasMap yet, // this variable is from the input. - VariableAST::Ptr varAST = boost::static_pointer_cast(ast); + VariableAST::Ptr varAST = dyncompat::static_pointer_cast(ast); return VariableAST::create(Variable(varAST->val().reg, 1)); } return ast; @@ -422,10 +437,11 @@ Address SymbolicExpression::PCValue(Address cur, size_t insnSize, Architecture a switch (a) { case Arch_x86: case Arch_x86_64: - case Arch_amdgpu_vega: + case Arch_amdgpu_gfx908: + case Arch_amdgpu_gfx90a: + case Arch_amdgpu_gfx940: return cur + insnSize; case Arch_aarch64: - case Arch_amdgpu_rdna: case Arch_ppc32: case Arch_ppc64: return cur; diff --git a/parseAPI/src/SymbolicExpression.h b/parseAPI/src/SymbolicExpression.h index fd10859cc7..13b12a828e 100644 --- a/parseAPI/src/SymbolicExpression.h +++ b/parseAPI/src/SymbolicExpression.h @@ -4,6 +4,9 @@ #include "DynAST.h" #include "Absloc.h" #include "CodeSource.h" +#include +#include +#include #include using Dyninst::AST; using namespace Dyninst; diff --git a/parseAPI/src/SymtabCodeSource.C b/parseAPI/src/SymtabCodeSource.C index 6d098cfdbe..42028bd5fc 100644 --- a/parseAPI/src/SymtabCodeSource.C +++ b/parseAPI/src/SymtabCodeSource.C @@ -27,10 +27,12 @@ * License along with this library; if not, write to the Free Software * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include #include +#include -#include +#include #include "common/src/stats.h" #include "dyntypes.h" @@ -42,6 +44,7 @@ #include "CodeSource.h" #include "debug_parse.h" #include "util.h" +#include "unaligned_memory_access.h" #include "InstructionDecoder.h" #include "Instruction.h" @@ -259,7 +262,7 @@ SymtabCodeSource::SymtabCodeSource(SymtabAPI::Symtab * st) : init(NULL,false); } -SymtabCodeSource::SymtabCodeSource(char * file) : +SymtabCodeSource::SymtabCodeSource(const char * file) : _symtab(NULL), owns_symtab(true), stats_parse(new ::StatContainer()), @@ -482,6 +485,9 @@ SymtabCodeSource::init_hints(RegionMap &rmap, hint_filt * filt) parsing_printf("[%s:%d] processing %lu symtab hints\n",FILE__,__LINE__, fsyms.size()); + atomic_bool foundEntrySymbol{}; + Address entryOffset = _symtab->getEntryOffset(); + #pragma omp parallel for schedule(auto) for (unsigned int i = 0; i < fsyms.size(); i++) { SymtabAPI::Function *f = fsyms[i]; @@ -542,6 +548,10 @@ SymtabCodeSource::init_hints(RegionMap &rmap, hint_filt * filt) sr->getMemOffset(), sr->getMemOffset()+sr->getDiskSize()); } else { + if (entryOffset == offset) { + foundEntrySymbol = true; + } + _hints.push_back(Hint(f->getOffset(), f->getSymbolSize(), cr, fname_s)); parsing_printf("\t<%lx,%s,[%lx,%lx)>\n", f->getOffset(), @@ -550,6 +560,40 @@ SymtabCodeSource::init_hints(RegionMap &rmap, hint_filt * filt) cr->offset()+cr->length()); } } + + if (!foundEntrySymbol && _symtab->isExecutable()) { + // add entry point as this object is an executable + // and no symbol referenced the entry point + parsing_printf("Adding exectable entry point at %lx\n", entryOffset); + SymtabAPI::Region *sr = _symtab->findEnclosingRegion(entryOffset); + if (sr) { + CodeRegion *cr = NULL; + { + RegionMap::const_accessor a; + bool found = rmap.find(a, sr); + if (found) { + cr = a->second; + } + } + + if (cr) { + const char startFuncName[] = "_start"; + // use 0 for function length as length is unknown and value unused + _hints.push_back(Hint(entryOffset, 0, cr, startFuncName)); + parsing_printf("\t<%lx,%s,[%lx,%lx)>\n", + entryOffset, + startFuncName, + cr->offset(), + cr->offset() + cr->length()); + } else { + parsing_printf("[%s:%d] unrecognized Region %lx entry point function %lx\n", + FILE__, __LINE__, sr->getMemOffset(), entryOffset); + } + } else { + parsing_printf("[%s:%d] Symtab Region for entry point function %lx not found\n", + FILE__, __LINE__, entryOffset); + } + } } void @@ -592,7 +636,7 @@ SymtabCodeSource::init_linkage() // Scan each PLT stub for (size_t off = 0; off < plt_sec->getMemSize(); off += plt_entry_size) { - int disp = *((const int*)(buffer + off + pc_rela_disp)); + auto disp = Dyninst::read_memory_as(buffer + off + pc_rela_disp); Address rel_addr = plt_sec->getMemOffset() + off + pc_rela_disp + 4 /* four byte pc-relative displacment */ + disp; if (rel_addr_to_name.find(rel_addr) != rel_addr_to_name.end()) { Address tar = plt_sec->getMemOffset() + off; diff --git a/parseAPI/src/ThunkData.C b/parseAPI/src/ThunkData.C index 798dda3650..39add70494 100644 --- a/parseAPI/src/ThunkData.C +++ b/parseAPI/src/ThunkData.C @@ -1,3 +1,4 @@ +#include #include "dyntypes.h" #include "ThunkData.h" #include "IndirectASTVisitor.h" diff --git a/parseAPI/src/ThunkData.h b/parseAPI/src/ThunkData.h index 7b81b8b84c..c9b5f9fcce 100644 --- a/parseAPI/src/ThunkData.h +++ b/parseAPI/src/ThunkData.h @@ -4,6 +4,7 @@ #include "CFG.h" //#include "Instruction.h" #include "DynAST.h" +#include "registers/MachRegister.h" using namespace std; using namespace Dyninst; diff --git a/parseAPI/src/debug_parse.C b/parseAPI/src/debug_parse.C index 498dc5f5e5..3b2b72a0d4 100644 --- a/parseAPI/src/debug_parse.C +++ b/parseAPI/src/debug_parse.C @@ -30,9 +30,14 @@ #include #include #include +#include #include "debug_parse.h" +#ifdef _OPENMP +#include +#endif + using namespace Dyninst::ParseAPI; int Dyninst::ParseAPI::dyn_debug_parsing = 0; @@ -40,17 +45,6 @@ int Dyninst::ParseAPI::dyn_debug_malware = 0; int Dyninst::ParseAPI::dyn_debug_indirect_collect = 0; int Dyninst::ParseAPI::dyn_debug_initialized = 0; -#if defined(_MSC_VER) -#pragma warning(push) -#pragma warning(disable:4996) -#endif - -#if defined(_OPENMP) -#include -#endif - -dyn_tls FILE* log_file = NULL; - int Dyninst::ParseAPI::parsing_printf_int(const char *format, ...) { if(!dyn_debug_initialized) { @@ -63,23 +57,29 @@ int Dyninst::ParseAPI::parsing_printf_int(const char *format, ...) if(!dyn_debug_parsing) return 0; if(NULL == format) return -1; - if (log_file == NULL) { - char filename[128]; -#if defined(_OPENMP) - snprintf(filename, 128, "%s-%d.txt", getenv("DYNINST_DEBUG_PARSING"), omp_get_thread_num()); -#else - snprintf(filename, 128, "%s-%d.txt", getenv("DYNINST_DEBUG_PARSING"), 0); -#endif - log_file = fopen(filename, "w"); - } + auto const id = []() -> int { +#ifdef _OPENMP + return omp_get_thread_num(); +#endif + return 0; + }(); va_list va; va_start(va,format); - int ret = vfprintf(log_file, format, va); - fflush(log_file); - va_end(va); + auto ret = 0; + + #pragma omp critical + { + ret = fprintf(stderr, "[thread %d] ", id); + if(ret >= 0) { + ret = vfprintf(stderr, format, va); + } + fflush(stderr); + } + + va_end(va); return ret; } @@ -139,7 +139,3 @@ const std::string PARSE_TAILCALL_FAIL("isTailcallFail"); const std::string PARSE_TOTAL_TIME("parseTotalTime"); const std::string PARSE_JUMPTABLE_TIME("parseJumpTableTime"); - -#if defined(_MSC_VER) -#pragma warning(pop) -#endif diff --git a/parseAPI/src/debug_parse.h b/parseAPI/src/debug_parse.h index 0719e59d3c..7b5bd18a33 100644 --- a/parseAPI/src/debug_parse.h +++ b/parseAPI/src/debug_parse.h @@ -30,9 +30,10 @@ #ifndef _PARSEAPI_DEBUG_ #define _PARSEAPI_DEBUG_ +#include #include #include -#include +#include #include "compiler_annotations.h" namespace Dyninst { diff --git a/parseAPI/src/dominator.C b/parseAPI/src/dominator.C index f0df7651ed..5077ee9cb8 100644 --- a/parseAPI/src/dominator.C +++ b/parseAPI/src/dominator.C @@ -28,6 +28,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include "CFG.h" #include #include diff --git a/parseThat/.gitignore b/parseThat/.gitignore index 171119f8ae..d67fb0ff91 100644 --- a/parseThat/.gitignore +++ b/parseThat/.gitignore @@ -3,7 +3,6 @@ i386-unknown-freebsd7.2/ i386-unknown-linux2.4/ i386-unknown-vxworks6.x/ ppc32_bgp/ -ppc32_linux/ ppc32-unknown-vxworks6.x/ ppc64_linux/ x86_64-unknown-linux2.4/ diff --git a/parseThat/CMakeLists.txt b/parseThat/CMakeLists.txt index 96121b3b9b..ffe4b7aea2 100644 --- a/parseThat/CMakeLists.txt +++ b/parseThat/CMakeLists.txt @@ -1,9 +1,32 @@ -add_executable(parseThat src/parseThat.C src/config.C src/ipc.C src/record.C src/strlist.C src/reglist.C src/log.C src/utils.C src/sha1.C src/dyninstCore.C src/dyninstCompat.v5.C) -add_definitions(-DHAVE_BPATCH_PROCESS_H) +include_guard(GLOBAL) -if (USE_OpenMP) -set_target_properties (parseThat PROPERTIES COMPILE_FLAGS ${OpenMP_CXX_FLAGS} LINK_FLAGS ${OpenMP_CXX_FLAGS}) +# parseThat requires dyninstAPI which doesn't work with symlite +if(LIGHTWEIGHT_SYMTAB) + message(STATUS "LIGHTWEIGHT_SYMTAB enabled; parseThat not built.") + return() endif() -target_link_private_libraries(parseThat dyninstAPI patchAPI parseAPI instructionAPI stackwalk symtabAPI common pcontrol dynDwarf dynElf ${Boost_LIBRARIES} ${ElfUtils_LIBRARIES}) +add_executable( + parseThat + src/parseThat.C + src/config.C + src/ipc.C + src/record.C + src/strlist.C + src/reglist.C + src/log.C + src/utils.C + src/sha1.C + src/dyninstCore.C + src/dyninstCompat.v5.C) + +target_compile_definitions(parseThat PRIVATE HAVE_BPATCH_PROCESS_H) + +target_link_libraries(parseThat PRIVATE dyninstAPI) + +# There is both a common/h/util.h and a dyninstAPI/src/util.h, so put +# the common/h include path first +target_include_directories(parseThat BEFORE + PRIVATE "$") + install(TARGETS parseThat RUNTIME DESTINATION bin) diff --git a/parseThat/src/parseThat.C b/parseThat/src/parseThat.C index 8a2c900281..c76c4bb0ec 100644 --- a/parseThat/src/parseThat.C +++ b/parseThat/src/parseThat.C @@ -31,7 +31,6 @@ #include #include #include -//#include #include #include #include diff --git a/parseThat/src/sha1.C b/parseThat/src/sha1.C index 98ee0e70dc..64350070ce 100644 --- a/parseThat/src/sha1.C +++ b/parseThat/src/sha1.C @@ -102,23 +102,10 @@ A million repetitions of "a" #include "sha1.h" #include #include +#include "unaligned_memory_access.h" -#if defined(HAVE_INTTYPES_H) -#include - -#else -#if defined(HAVE_STDINT_H) #include -#else -typedef long long int int64_t; -typedef unsigned long long int uint64_t; -typedef int int32_t; -typedef unsigned int uint32_t; - -#endif -#endif - /* #include */ /* prototype for exit() - JHB */ /* Using return() instead of exit() - SWR */ @@ -178,11 +165,11 @@ typedef union { } CHAR64LONG16; CHAR64LONG16* block; #ifdef SHA1HANDSOFF -static unsigned char workspace[64]; +alignas(alignof(CHAR64LONG16)) static unsigned char workspace[64]; block = (CHAR64LONG16*)workspace; memcpy(block, buffer, 64); #else - block = (CHAR64LONG16*)buffer; + block = Dyninst::alignas_cast(buffer); #endif /* Copy context->state[] to working vars */ a = state[0]; diff --git a/patchAPI/CMakeLists.txt b/patchAPI/CMakeLists.txt index 237e870f06..9584bb55c4 100644 --- a/patchAPI/CMakeLists.txt +++ b/patchAPI/CMakeLists.txt @@ -1,31 +1,49 @@ -# CMake configuration for patchAPI directory +include_guard(GLOBAL) -include_directories ( - ${PROJECT_SOURCE_DIR}/patchAPI/src - ) +include(DyninstLibrary) -set (SRC_LIST - src/AddrSpace.C - src/Instrumenter.C - src/PatchObject.C - src/PatchBlock.C - src/PatchEdge.C - src/PatchFunction.C - src/PatchMgr.C - src/Point.C - src/CFGMaker.C - src/PointMaker.C - src/Command.C - src/PatchCallback.C - src/ParseCallback.C - src/PatchModifier.C - src/PatchLoop.C - src/PatchLoopTreeNode.C - ) +set(_public_headers + h/AddrSpace.h + h/CFGMaker.h + h/Command.h + h/Instrumenter.h + h/PatchCallback.h + h/PatchCFG.h + h/PatchCommon.h + h/PatchMgr.h + h/PatchModifier.h + h/PatchObject.h + h/Point.h + h/Snippet.h) -SET_SOURCE_FILES_PROPERTIES(${SRC_LIST} PROPERTIES LANGUAGE CXX) +set(_private_headers src/ParseCallback.h) -ADD_DEFINITIONS(-DPATCHAPI_LIB) +set(_sources + src/AddrSpace.C + src/CFGMaker.C + src/Command.C + src/Instrumenter.C + src/ParseCallback.C + src/PatchBlock.C + src/PatchCallback.C + src/PatchEdge.C + src/PatchFunction.C + src/PatchLoop.C + src/PatchLoopTreeNode.C + src/PatchMgr.C + src/PatchModifier.C + src/PatchObject.C + src/Point.C + src/PointMaker.C) -dyninst_library(patchAPI common instructionAPI parseAPI) -target_link_private_libraries(patchAPI ${Boost_LIBRARIES}) +# cmake-format: off +dyninst_library( + patchAPI + PUBLIC_HEADER_FILES ${_public_headers} + PRIVATE_HEADER_FILES ${_private_headers} + SOURCE_FILES ${_sources} + DEFINES PATCHAPI_LIB + DYNINST_DEPS common instructionAPI parseAPI + PRIVATE_DEPS +) +# cmake-format: on diff --git a/patchAPI/doc/patchAPI.pdf b/patchAPI/doc/patchAPI.pdf index 8afa89f973..ba23d669bd 100644 Binary files a/patchAPI/doc/patchAPI.pdf and b/patchAPI/doc/patchAPI.pdf differ diff --git a/patchAPI/doc/section/4_api_public.tex b/patchAPI/doc/section/4_api_public.tex index 5f70c2ecd1..6c2b5c9ab1 100644 --- a/patchAPI/doc/section/4_api_public.tex +++ b/patchAPI/doc/section/4_api_public.tex @@ -295,7 +295,7 @@ \subsubsection{PatchFunction} \begin{apient} PatchBlock* getImmediateDominator(PatchBlock *A); \end{apient} -\apidesc{Return the immediate dominator of block \code{A}，\code{NULL} if the block \code{A} does not have an immediate dominator.} +\apidesc{Return the immediate dominator of block \code{A}, \code{NULL} if the block \code{A} does not have an immediate dominator.} \begin{apient} void getImmediateDominates(PatchBlock *A, set &imm); @@ -316,7 +316,7 @@ \subsubsection{PatchFunction} \begin{apient} PatchBlock* getImmediatePostDominator(PatchBlock *A); \end{apient} -\apidesc{Return the immediate post-dominator of block \code{A}，\code{NULL} if the block \code{A} does not have an immediate post-dominator.} +\apidesc{Return the immediate post-dominator of block \code{A}, \code{NULL} if the block \code{A} does not have an immediate post-dominator.} \begin{apient} void getImmediatePostDominates(PatchBlock *A, set &imm); diff --git a/patchAPI/example/README.md b/patchAPI/example/README.md deleted file mode 100644 index b545f58e9a..0000000000 --- a/patchAPI/example/README.md +++ /dev/null @@ -1,22 +0,0 @@ -To build you need to set the three environment variables `DYNINST`, `BOOST`, and -`TBB` to the install directories of these three dependencies. - - -For example, if you `spack` installed `dyninst` you could do: - - -``` -export DYNINST=`spack location --install-dir dyninst` -export BOOST=`spack location --install-dir boost` -export TBB=`spack location --install-dir tbb` -``` - -Then to build and test: - -``` -make test -``` - -To run the rewritten mutatee program you will also need to set the -`DYNINSTAPI_RT_LIB` environment variable to -`${DYNINST}/lib/libdyninstAPI_RT.so.1` diff --git a/patchAPI/example/main.cpp b/patchAPI/example/main.cpp deleted file mode 100644 index fbdc9e6337..0000000000 --- a/patchAPI/example/main.cpp +++ /dev/null @@ -1,125 +0,0 @@ -// DynInst -#include "BPatch.h" -#include "BPatch_binaryEdit.h" -#include "BPatch_image.h" -#include "BPatch_function.h" -#include "BPatch_object.h" -#include "BPatch_point.h" -#include "BPatch_Vector.h" - -#include -#include -#include -#include -#include -#include - -// patchAPI -#include "PatchMgr.h" - -using namespace std; -using namespace Dyninst; -using namespace PatchAPI; - - -// a simple example, just insert a bunch of no ops -class NoopSnippet : public Snippet { - -public: - bool generate(Point *pt, Buffer &buffer){ - uint8_t byte = 0x90; - cout << "inserting a no op @" << pt << endl; - for(int i = 0; i < 10; i++){ - buffer.push_back(byte); - } - return true; - } - -}; - - - -int main(int argc, const char *argv[]) { - - if(argc != 3){ - cerr << "Usage:\n\t" << argv[0] << " " << endl; - return 1; - } - - const char* input_binary = argv[1]; - const char* output_binary = argv[2]; - - BPatch bpatch; - - BPatch_binaryEdit* app = bpatch.openBinary(input_binary, false); - - if(app == NULL){ - return 0; - } - - cout << "app OK" << endl; - - BPatch_image* image = app->getImage(); - - if(image == NULL){ - return 0; - } - - cout << "image OK" << endl; - - PatchMgrPtr patchMgr = PatchAPI::convert(image); - - vector objects; - - image->getObjects(objects); - - int ocount = objects.size(); - - cout << "objects: " << ocount << endl; - - if(ocount <= 0){ - return 0; - } - - BPatch_object* batchObj = objects[0]; - - // Not mentioned in A.2 of https://dyninst.org/sites/default/files/manuals/dyninst/patchAPI.pdf - // But found in the header file: "BPatch_object.h" - PatchObject* binobj = PatchAPI::convert(batchObj); - - Patcher patcher(patchMgr); - - NoopSnippet::Ptr snippet = NoopSnippet::create(new NoopSnippet); - - vector functions; - - binobj->funcs(back_inserter(functions)); - - - for(vector::iterator funIter = functions.begin(); funIter != functions.end(); funIter++){ - PatchFunction *fun = *funIter; - - vector f_entryPoints; - patchMgr->findPoints(PatchAPI::Scope(fun), PatchAPI::Point::FuncEntry, back_inserter(f_entryPoints)); - - - cout << fun->name() << " has:\n\t" << f_entryPoints.size() << " entry points" << endl; - - for(vector::iterator pointIter = f_entryPoints.begin(); pointIter!= f_entryPoints.end(); pointIter++){ - Point* point = *pointIter; - cerr << "Patching @ " << point << endl; - patcher.add(PushBackCommand::create(point, snippet)); - } - - } - - patcher.commit(); - - cout << "Commited" << endl; - - app->writeFile(output_binary); - - cout << "Written" << endl; - - -} diff --git a/patchAPI/example/mutatee/main.c b/patchAPI/example/mutatee/main.c deleted file mode 100644 index 642cee691c..0000000000 --- a/patchAPI/example/mutatee/main.c +++ /dev/null @@ -1,34 +0,0 @@ - -#include -#include - - -static int status = -1; - -void foo0(void){ - status = 0; -} - -void foo1(void) { - status = 1; -} - -void foo2(void) { - status = 2; -} - -void message(const char* msg){ - printf("%s\n", msg); -} - -int main(int argc, const char *argv[]) -{ - if (argc > 2){ - foo0(); - } else { - foo1(); - foo2(); - } - message("Done\n"); - return 0; -} diff --git a/patchAPI/h/AddrSpace.h b/patchAPI/h/AddrSpace.h index fd099d6dd0..562905c347 100644 --- a/patchAPI/h/AddrSpace.h +++ b/patchAPI/h/AddrSpace.h @@ -33,7 +33,11 @@ #ifndef PATCHAPI_H_ADDRSPACE_H_ #define PATCHAPI_H_ADDRSPACE_H_ +#include +#include +#include #include "PatchCommon.h" +#include "dyntypes.h" namespace Dyninst { namespace PatchAPI { @@ -50,17 +54,17 @@ class PATCHAPI_EXPORT AddrSpace { virtual ~AddrSpace(); // Write data in mutatee's address space - virtual bool write(PatchObject* /*obj*/, Address /*to*/, - Address /*from*/, size_t /*size*/); + virtual bool write(PatchObject* /*obj*/, Dyninst::Address /*to*/, + Dyninst::Address /*from*/, size_t /*size*/); // Memory allocation / reallocation / deallocation in mutatee's addressSpace - virtual Address malloc(PatchObject* /*obj*/, size_t /*size*/, - Address /*near*/); + virtual Dyninst::Address malloc(PatchObject* /*obj*/, size_t /*size*/, + Dyninst::Address /*near*/); - virtual bool realloc(PatchObject* /*obj*/, Address /*orig*/, + virtual bool realloc(PatchObject* /*obj*/, Dyninst::Address /*orig*/, size_t /*size*/); - virtual bool free(PatchObject* /*obj*/, Address /*orig*/); + virtual bool free(PatchObject* /*obj*/, Dyninst::Address /*orig*/); // Load a binary oject into the address space virtual bool loadObject(PatchObject* obj); @@ -79,7 +83,7 @@ class PATCHAPI_EXPORT AddrSpace { protected: ObjMap obj_map_; - PatchObject* first_object_; + PatchObject* first_object_{}; PatchMgrPtr mgr_; bool init(PatchObject*); diff --git a/patchAPI/h/Command.h b/patchAPI/h/Command.h index 1453f772f1..49fb6384f1 100644 --- a/patchAPI/h/Command.h +++ b/patchAPI/h/Command.h @@ -32,6 +32,7 @@ #ifndef PATCHAPI_COMMAND_H_ #define PATCHAPI_COMMAND_H_ +#include #include "PatchCommon.h" namespace Dyninst { @@ -81,9 +82,9 @@ class PATCHAPI_EXPORT BatchCommand : public Command { class PATCHAPI_EXPORT Patcher : public BatchCommand { public: - using Ptr = boost::shared_ptr; + using Ptr = dyncompat::shared_ptr; static Ptr create(Dyninst::PatchAPI::PatchMgrPtr mgr) { - return boost::make_shared(mgr); + return dyncompat::make_shared(mgr); } Patcher(Dyninst::PatchAPI::PatchMgrPtr mgr) : mgr_(mgr) {} virtual ~Patcher() {} diff --git a/patchAPI/h/Instrumenter.h b/patchAPI/h/Instrumenter.h index 5995224cd2..ec9511cb20 100644 --- a/patchAPI/h/Instrumenter.h +++ b/patchAPI/h/Instrumenter.h @@ -32,6 +32,7 @@ #ifndef PATCHAPI_H_INSTRUMENTOR_H_ #define PATCHAPI_H_INSTRUMENTOR_H_ +#include #include "PatchCommon.h" #include "Point.h" #include "AddrSpace.h" diff --git a/patchAPI/h/PatchCFG.h b/patchAPI/h/PatchCFG.h index 3df181a432..dd06d91105 100644 --- a/patchAPI/h/PatchCFG.h +++ b/patchAPI/h/PatchCFG.h @@ -32,6 +32,11 @@ #ifndef _PATCHAPI_DYNINST_CFG_H_ #define _PATCHAPI_DYNINST_CFG_H_ +#include +#include +#include +#include +#include #include "CFG.h" #include "PatchCommon.h" #include "PatchObject.h" diff --git a/patchAPI/h/PatchCallback.h b/patchAPI/h/PatchCallback.h index 757a2790b0..5f1dce877a 100644 --- a/patchAPI/h/PatchCallback.h +++ b/patchAPI/h/PatchCallback.h @@ -36,6 +36,7 @@ #if !defined(_PATCH_CALLBACK_H_) #define _PATCH_CALLBACK_H_ +#include #include #include "util.h" diff --git a/patchAPI/h/PatchCommon.h b/patchAPI/h/PatchCommon.h index 4addd25b98..fab985aa87 100644 --- a/patchAPI/h/PatchCommon.h +++ b/patchAPI/h/PatchCommon.h @@ -31,6 +31,10 @@ #define PATCHAPI_H_COMMON_H_ // C++ +#include +#include +#include +#include #include #include #include @@ -58,13 +62,13 @@ typedef std::set PointSet; typedef PointSet::iterator PointIter; class Instance; -typedef boost::shared_ptr InstancePtr; +typedef dyncompat::shared_ptr InstancePtr; typedef std::set InstanceSet; typedef std::list InstanceList; class Instrumenter; class PatchMgr; -typedef boost::shared_ptr PatchMgrPtr; +typedef dyncompat::shared_ptr PatchMgrPtr; class PatchFunction; class PatchBlock; @@ -78,7 +82,7 @@ class BatchCommand; class Patcher; class Snippet; -typedef boost::shared_ptr SnippetPtr; +typedef dyncompat::shared_ptr SnippetPtr; typedef std::map FuncModMap; typedef std::map > FuncWrapMap; diff --git a/patchAPI/h/PatchMgr.h b/patchAPI/h/PatchMgr.h index 2ecd99d5a1..345487ba6d 100644 --- a/patchAPI/h/PatchMgr.h +++ b/patchAPI/h/PatchMgr.h @@ -34,6 +34,8 @@ +#include +#include #include "PatchCommon.h" #include "Point.h" #include "Instrumenter.h" @@ -62,7 +64,7 @@ Scope(PatchFunction *f) : obj(NULL), func(f), block(NULL), wholeProgram(false) { }; -class PATCHAPI_EXPORT PatchMgr : public boost::enable_shared_from_this { +class PATCHAPI_EXPORT PatchMgr : public dyncompat::enable_shared_from_this { friend class Point; friend class PatchObject; // for splitting blocks as that is _not_ public. typedef std::pair BlockInstance; @@ -78,7 +80,7 @@ class PATCHAPI_EXPORT PatchMgr : public boost::enable_shared_from_this typedef std::vector EnumeratedTypes; public: - typedef boost::shared_ptr Ptr; + typedef dyncompat::shared_ptr Ptr; typedef std::pair Candidate; typedef std::vector Candidates; diff --git a/patchAPI/h/PatchModifier.h b/patchAPI/h/PatchModifier.h index 696b622eb5..6a9bcd0ebc 100644 --- a/patchAPI/h/PatchModifier.h +++ b/patchAPI/h/PatchModifier.h @@ -31,6 +31,8 @@ #ifndef _PATCH_MODIFIER_H_ #define _PATCH_MODIFIER_H_ +#include +#include #include "dyntypes.h" // A collection of methods for user-triggered modification of a PatchAPI CFG, @@ -54,7 +56,7 @@ class PATCHAPI_EXPORT InsertedCode { public: InsertedCode() : entry_(NULL) {} - typedef boost::shared_ptr Ptr; + typedef dyncompat::shared_ptr Ptr; PatchBlock *entry() { return entry_; } const std::vector &exits() { return exits_;} const std::set &blocks() { return blocks_; } diff --git a/patchAPI/h/PatchObject.h b/patchAPI/h/PatchObject.h index a8a1eadb29..c9d37be567 100644 --- a/patchAPI/h/PatchObject.h +++ b/patchAPI/h/PatchObject.h @@ -32,6 +32,9 @@ #ifndef PATCHAPI_H_DYNINST_OBJECT_H_ #define PATCHAPI_H_DYNINST_OBJECT_H_ +#include +#include +#include #include "PatchCommon.h" #include "CFGMaker.h" diff --git a/patchAPI/h/Point.h b/patchAPI/h/Point.h index 4b9249eab1..9972f31d21 100644 --- a/patchAPI/h/Point.h +++ b/patchAPI/h/Point.h @@ -32,9 +32,13 @@ #ifndef PATCHAPI_H_POINT_H_ #define PATCHAPI_H_POINT_H_ +#include +#include +#include #include "PatchCommon.h" #include "Snippet.h" #include "util.h" +#include "dyntypes.h" namespace Dyninst { namespace PatchAPI { @@ -60,9 +64,9 @@ ExitSite_t(PatchFunction *f, PatchBlock *b) : func(f), block(b) {} struct InsnLoc_t { PatchBlock *block; - Address addr; + Dyninst::Address addr; InstructionAPI::Instruction insn; -InsnLoc_t(PatchBlock *b, Address a, InstructionAPI::Instruction i) : +InsnLoc_t(PatchBlock *b, Dyninst::Address a, InstructionAPI::Instruction i) : block(b), addr(a), insn(i) {} }; @@ -82,16 +86,16 @@ struct Location { static Location Instruction(InsnLoc_t l) { return Location(NULL, l.block, l.addr, l.insn, NULL, true, Instruction_); } - static Location Instruction(PatchBlock *b, Address a) { + static Location Instruction(PatchBlock *b, Dyninst::Address a) { return Location(NULL, b, a, InstructionAPI::Instruction(), NULL, false, Instruction_); } static Location InstructionInstance(PatchFunction *f, InsnLoc_t l, bool trusted = false) { return Location(f, l.block, l.addr, l.insn, NULL, trusted, InstructionInstance_); } - static Location InstructionInstance(PatchFunction *f, PatchBlock *b, Address a) { + static Location InstructionInstance(PatchFunction *f, PatchBlock *b, Dyninst::Address a) { return Location(f, b, a, InstructionAPI::Instruction(), NULL, false, InstructionInstance_); } - static Location InstructionInstance(PatchFunction *f, PatchBlock *b, Address a, + static Location InstructionInstance(PatchFunction *f, PatchBlock *b, Dyninst::Address a, InstructionAPI::Instruction i, bool trusted = false) { return Location(f, b, a, i, NULL, trusted, InstructionInstance_); } @@ -138,20 +142,20 @@ struct Location { PatchFunction *func; PatchBlock *block; - Address addr; + Dyninst::Address addr; InstructionAPI::Instruction insn; PatchEdge *edge; bool trusted; type_t type; private: -Location(PatchFunction *f, PatchBlock *b, Address a, InstructionAPI::Instruction i, PatchEdge *e, bool u, type_t t) : +Location(PatchFunction *f, PatchBlock *b, Dyninst::Address a, InstructionAPI::Instruction i, PatchEdge *e, bool u, type_t t) : func(f), block(b), addr(a), insn(i), edge(e), trusted(u), type(t) {} }; // Used in PointType definition -#define type_val(seq) (0x00000001 << seq) +#define type_val(seq) (0x00000001u << seq) /* A location on the CFG that acts as a container of inserted instances. Points @@ -195,7 +199,7 @@ class PATCHAPI_EXPORT Point { }; template - static Point* create(Address addr, + static Point* create(Dyninst::Address addr, Point::Type type, PatchMgrPtr mgr, Scope* scope) { @@ -207,7 +211,7 @@ class PATCHAPI_EXPORT Point { // Block instrumentation /w/ optional function context Point(Point::Type t, PatchMgrPtr mgr, PatchBlock *, PatchFunction * = NULL); // Insn instrumentation /w/ optional function context - Point(Point::Type t, PatchMgrPtr mgr, PatchBlock *, Address, InstructionAPI::Instruction, PatchFunction * = NULL); + Point(Point::Type t, PatchMgrPtr mgr, PatchBlock *, Dyninst::Address, InstructionAPI::Instruction, PatchFunction * = NULL); // Function entry or during Point(Point::Type t, PatchMgrPtr mgr, PatchFunction *); // Function call or exit site @@ -230,7 +234,7 @@ class PATCHAPI_EXPORT Point { // Getters size_t size(); - Address addr() const { return addr_; } + Dyninst::Address addr() const { return addr_; } Type type() const {return type_;} bool empty() const { return instanceList_.empty();} @@ -264,12 +268,12 @@ class PATCHAPI_EXPORT Point { InstanceList instanceList_; - Address addr_; - Type type_; + Dyninst::Address addr_{}; + Type type_{}; PatchMgrPtr mgr_; - PatchBlock* the_block_; - PatchEdge* the_edge_; - PatchFunction* the_func_; + PatchBlock* the_block_{}; + PatchEdge* the_edge_{}; + PatchFunction* the_func_{}; InstructionAPI::Instruction insn_; }; @@ -319,9 +323,9 @@ enum SnippetState { /* A representation of a particular snippet inserted at a particular point */ -class PATCHAPI_EXPORT Instance : public boost::enable_shared_from_this { +class PATCHAPI_EXPORT Instance : public dyncompat::enable_shared_from_this { public: - typedef boost::shared_ptr Ptr; + typedef dyncompat::shared_ptr Ptr; Instance(Point* point, SnippetPtr snippet) : point_(point), snippet_(snippet), state_(PENDING), type_(SYSTEM), guarded_(true) { } @@ -369,7 +373,7 @@ class PATCHAPI_EXPORT PointMaker { virtual Point *mkFuncPoint(Point::Type t, PatchMgrPtr m, PatchFunction *); virtual Point *mkFuncSitePoint(Point::Type t, PatchMgrPtr m, PatchFunction *, PatchBlock *); virtual Point *mkBlockPoint(Point::Type t, PatchMgrPtr m, PatchBlock *, PatchFunction *context); - virtual Point *mkInsnPoint(Point::Type t, PatchMgrPtr m, PatchBlock *, Address, InstructionAPI::Instruction, + virtual Point *mkInsnPoint(Point::Type t, PatchMgrPtr m, PatchBlock *, Dyninst::Address, InstructionAPI::Instruction, PatchFunction *context); virtual Point *mkEdgePoint(Point::Type t, PatchMgrPtr m, PatchEdge *, PatchFunction *context); @@ -378,34 +382,48 @@ class PATCHAPI_EXPORT PointMaker { }; // Collection classes -typedef std::map InsnPoints; +typedef std::map InsnPoints; struct BlockPoints { - Point *entry; - Point *during; - Point *exit; + Point *entry{}; + Point *during{}; + Point *exit{}; InsnPoints preInsn; InsnPoints postInsn; -BlockPoints() : entry(NULL), during(NULL), exit(NULL) {} + BlockPoints() = default; + BlockPoints(const BlockPoints&) = delete; + BlockPoints(BlockPoints&& other) + { + *this = other; + other.entry = nullptr; + other.during = nullptr; + other.exit = nullptr; + } bool consistency(const PatchBlock *block, const PatchFunction *func) const; ~BlockPoints(); + private: + // used by move constructor to default copy members + BlockPoints& operator=(const BlockPoints&) = default; }; struct EdgePoints { - Point *during; -EdgePoints() : during(NULL) {} + Point *during{}; + EdgePoints() = default; + EdgePoints(EdgePoints&& other) { during = other.during; other.during = nullptr; } ~EdgePoints() { if (during) delete during; } bool consistency(const PatchEdge *edge, const PatchFunction *func) const; + EdgePoints(const EdgePoints&) = delete; }; struct FuncPoints { - Point *entry; - Point *during; + Point *entry{}; + Point *during{}; std::map exits; std::map preCalls; std::map postCalls; -FuncPoints() : entry(NULL), during(NULL) {} + FuncPoints() = default; + FuncPoints(const FuncPoints&) = delete; ~FuncPoints(); bool consistency(const PatchFunction *func) const; }; diff --git a/patchAPI/h/Snippet.h b/patchAPI/h/Snippet.h index 8df1893202..fdcd7ba5aa 100644 --- a/patchAPI/h/Snippet.h +++ b/patchAPI/h/Snippet.h @@ -51,7 +51,7 @@ namespace PatchAPI { */ class PATCHAPI_EXPORT Snippet { public: - typedef boost::shared_ptr Ptr; + typedef dyncompat::shared_ptr Ptr; Snippet() {} virtual ~Snippet() {} static Snippet::Ptr create(Snippet *a) { return Ptr(a); } diff --git a/patchAPI/src/AddrSpace.C b/patchAPI/src/AddrSpace.C index 05d327b6d4..7ce23e908f 100644 --- a/patchAPI/src/AddrSpace.C +++ b/patchAPI/src/AddrSpace.C @@ -29,7 +29,7 @@ */ /* Public Interface */ -#include "common/src/Types.h" +#include #include "AddrSpace.h" #include "PatchObject.h" #include "PatchMgr.h" @@ -73,25 +73,25 @@ AddrSpace::~AddrSpace() { } bool -AddrSpace::write(PatchObject* /*obj*/, Address /*to*/, - Address /*from*/, size_t /*size*/) { +AddrSpace::write(PatchObject* /*obj*/, Dyninst::Address /*to*/, + Dyninst::Address /*from*/, size_t /*size*/) { return false; } -Address +Dyninst::Address AddrSpace::malloc(PatchObject* /*obj*/, size_t /*size*/, - Address /*near*/) { + Dyninst::Address /*near*/) { return false; } bool -AddrSpace::realloc(PatchObject* /*obj*/, Address /*orig*/, +AddrSpace::realloc(PatchObject* /*obj*/, Dyninst::Address /*orig*/, size_t /*size*/) { return false; } bool -AddrSpace::free(PatchObject* /*obj*/, Address /*orig*/) { +AddrSpace::free(PatchObject* /*obj*/, Dyninst::Address /*orig*/) { return false; } diff --git a/patchAPI/src/Instrumenter.C b/patchAPI/src/Instrumenter.C index 65823aefd4..59dbe94bd0 100644 --- a/patchAPI/src/Instrumenter.C +++ b/patchAPI/src/Instrumenter.C @@ -29,6 +29,7 @@ */ /* Plugin */ +#include #include "Instrumenter.h" #include "PatchCFG.h" diff --git a/patchAPI/src/PatchBlock.C b/patchAPI/src/PatchBlock.C index be5bf1147a..df4ff54ceb 100644 --- a/patchAPI/src/PatchBlock.C +++ b/patchAPI/src/PatchBlock.C @@ -29,6 +29,7 @@ */ /* Public Interface */ +#include #include "PatchCommon.h" #include "PatchCFG.h" #include "AddrSpace.h" @@ -36,7 +37,7 @@ #include "PatchMgr.h" #include "PatchCallback.h" #include "Point.h" -#include +#include using namespace std; using namespace Dyninst; @@ -256,7 +257,7 @@ PatchBlock::containsDynamicCall() { rit != regs.end(); rit++) { if (RegisterAST::makePC(obj()->co()->cs()->getArch()).getID() != - boost::dynamic_pointer_cast(*rit)->getID()) + dyncompat::dynamic_pointer_cast(*rit)->getID()) { return true; } diff --git a/patchAPI/src/PatchFunction.C b/patchAPI/src/PatchFunction.C index fb45e6beea..a2bc2ae0fc 100644 --- a/patchAPI/src/PatchFunction.C +++ b/patchAPI/src/PatchFunction.C @@ -29,6 +29,7 @@ */ /* Public Interface */ +#include #include "PatchCFG.h" #include "PatchMgr.h" #include "PatchCallback.h" @@ -189,7 +190,7 @@ Point *PatchFunction::findPoint(Location loc, Point::Type type, bool create) { if (iter == blockPoints_.end()) { if (!create) return NULL; BlockPoints bp; - iter = blockPoints_.insert(blockPoints_.begin(), std::make_pair(loc.block, bp)); + iter = blockPoints_.insert(blockPoints_.begin(), std::make_pair(loc.block, std::move(bp))); } switch (type) { case Point::BlockEntry: @@ -248,7 +249,7 @@ Point *PatchFunction::findPoint(Location loc, Point::Type type, bool create) { if (iter == edgePoints_.end()) { if (!create) return NULL; EdgePoints ep; - iter = edgePoints_.insert(edgePoints_.begin(), std::make_pair(loc.edge, ep)); + iter = edgePoints_.insert(edgePoints_.begin(), std::make_pair(loc.edge, std::move(ep))); } if (!iter->second.during && create) { iter->second.during = maker->createPoint(loc, type); diff --git a/patchAPI/src/PatchLoop.C b/patchAPI/src/PatchLoop.C index a231004412..52126457c6 100644 --- a/patchAPI/src/PatchLoop.C +++ b/patchAPI/src/PatchLoop.C @@ -32,7 +32,6 @@ #include #include #include -#include "common/src/std_namesp.h" #include #include #include "CFG.h" diff --git a/patchAPI/src/PatchMgr.C b/patchAPI/src/PatchMgr.C index 66201346e0..faa380956f 100644 --- a/patchAPI/src/PatchMgr.C +++ b/patchAPI/src/PatchMgr.C @@ -29,6 +29,7 @@ */ /* Public Interface */ +#include #include "PatchMgr.h" #include "PatchObject.h" #include "PatchCFG.h" diff --git a/patchAPI/src/PatchModifier.C b/patchAPI/src/PatchModifier.C index 360a48c16b..6e042521ce 100644 --- a/patchAPI/src/PatchModifier.C +++ b/patchAPI/src/PatchModifier.C @@ -28,6 +28,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include "PatchModifier.h" #include "PatchCFG.h" #include "PatchMgr.h" diff --git a/patchAPI/src/PatchObject.C b/patchAPI/src/PatchObject.C index c8230a3bba..1faffa68e9 100644 --- a/patchAPI/src/PatchObject.C +++ b/patchAPI/src/PatchObject.C @@ -29,6 +29,7 @@ */ /* Plugin */ +#include #include "PatchObject.h" #include "PatchCFG.h" #include "AddrSpace.h" diff --git a/patchAPI/src/Point.C b/patchAPI/src/Point.C index 009cae098b..11c54b011e 100644 --- a/patchAPI/src/Point.C +++ b/patchAPI/src/Point.C @@ -29,6 +29,7 @@ */ /* Public Interface */ +#include #include "Point.h" #include "PatchMgr.h" #include "PatchObject.h" @@ -113,7 +114,7 @@ PatchObject *Point::obj() const { } /* for single instruction */ -Point::Point(Point::Type type, PatchMgrPtr mgr, PatchBlock *b, Address a, InstructionAPI::Instruction i, PatchFunction *f) +Point::Point(Point::Type type, PatchMgrPtr mgr, PatchBlock *b, Dyninst::Address a, InstructionAPI::Instruction i, PatchFunction *f) :addr_(a), type_(type), mgr_(mgr), the_block_(b), the_edge_(NULL), the_func_(f), insn_(i) { initCodeStructure(); diff --git a/patchAPI/src/PointMaker.C b/patchAPI/src/PointMaker.C index df32abc478..ad6ef081b7 100644 --- a/patchAPI/src/PointMaker.C +++ b/patchAPI/src/PointMaker.C @@ -27,7 +27,6 @@ * License along with this library; if not, write to the Free Software * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "common/src/Types.h" #include "Point.h" #include "PatchMgr.h" #include "PatchObject.h" diff --git a/patchAPI/test/findPoint/Makefile b/patchAPI/test/findPoint/Makefile deleted file mode 100644 index f758780811..0000000000 --- a/patchAPI/test/findPoint/Makefile +++ /dev/null @@ -1,26 +0,0 @@ -DYNINST_ROOT = /afs/cs.wisc.edu/p/paradyn/development/wenbin/dyninst -INC_DIR = -I$(DYNINST_ROOT)/include -I$(DYNINST_ROOT)/dyninst/patchAPI/h -I$(DYNINST_ROOT)/dyninst -I$(DYNINST_ROOT)/dyninst/dyninstAPI/src -I$(DYNINST_ROOT)/dyninst/patchAPI/src -I$(DYNINST_ROOT)/dyninst/patchAPI/src/dyninst -I$(DYNINST_ROOT)/dyninst/dyninstAPI/src/Relocation - -LIB_DIR = -L$(DYNINST_ROOT)/$(PLATFORM)/lib -LIB = -ldyninstAPI -lsymtabAPI -linstructionAPI -lcommon -lpcontrol -lparseAPI -lpatchAPI -CC = g++ -cc = gcc -CXXFLAG = -Wall -g -Dos_linux -Darch_x86_64 -Darch_64bit -Dx86_64_unknown_linux2_4 -Dcap_ptrace -Dcap_stripped_binaries -Dcap_async_events -Dcap_threads -Dcap_dynamic_heap -Dcap_relocation -Dcap_dwarf -Dcap_32_64 -Dcap_liveness -Dcap_fixpoint_gen -Dcap_noaddr_gen -Dcap_mutatee_traps -Dcap_binary_rewriter -Dcap_registers -Dcap_instruction_api -Dcap_instruction_replacement -Dcap_tramp_liveness -Dbug_syscall_changepc_rewind -D__STDC_LIMIT_MACROS -D__STDC_CONSTANT_MACROS -CFLAG = -Wall -fPIC - -PLATFORM = x86_64-unknown-linux2.4 - -#VPATH += $(DYNINST_ROOT)/dyninst/patchAPI/h -VPATH += $(DYNINST_ROOT)/dyninst/common/h -VPATH += $(DYNINST_ROOT)/dyninst/common -VPATH += $(DYNINST_ROOT)/dyninst/ - -CA_DEP = main.C - -all: test.exe - -test.exe: main.C $(DYNINST_ROOT)/$(PLATFORM)/lib/libdyninstAPI.so - $(CC) -o $@ $(LIB_DIR) $(INC_DIR) $(CXXFLAG) $< $(LIB) - -clean: - rm -f test.exe diff --git a/patchAPI/test/findPoint/main.C b/patchAPI/test/findPoint/main.C deleted file mode 100644 index 65a55dcd74..0000000000 --- a/patchAPI/test/findPoint/main.C +++ /dev/null @@ -1,126 +0,0 @@ -/* - * See the dyninst/COPYRIGHT file for copyright information. - * - * We provide the Paradyn Tools (below described as "Paradyn") - * on an AS IS basis, and do not warrant its validity or performance. - * We reserve the right to update, modify, or discontinue this - * software at any time. We shall have no obligation to supply such - * updates or modifications or any other form of support to you. - * - * By your use of Paradyn, you understand and agree that we (or any - * other person or entity with proprietary rights in Paradyn) are - * under no obligation to provide either maintenance services, - * update services, notices of latent defects, or correction of - * defects for Paradyn. - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - */ -#include "SnippetRep.h" -#include "PatchMgr.h" -#include "Point.h" -#include "PatchCFG.h" - -#include "DynObject.h" -#include "DynAddrSpace.h" - -#include "BPatch.h" -#include "BPatch_binaryEdit.h" -#include "BPatch_image.h" -#include "BPatch_function.h" -#include "BPatch_Vector.h" -#include "addressSpace.h" -#include "mapped_object.h" - -//parse API -#include -#include - -#include -#include -#include -#include -#include - -using namespace Dyninst::PatchAPI; -using namespace Dyninst::ParseAPI; - -int main(int argc, const char *argv[]) { - - // Use BPatch_* classes to initialize - BPatch bpatch; - BPatch_binaryEdit* app = bpatch.openBinary("mutatee/c"); - BPatch_image* image = app->getImage(); - - - BPatch_Vector found_funcs; - app->loadLibrary("mutatee/liblib.so"); - - found_funcs.clear(); - image->findFunction("foo3", found_funcs); - Function* foo3_func = found_funcs[0]->getParseAPIFunc(); - - // Here we go, create PatchAPI objects! - vector addrSpaces; - app->getAS(addrSpaces); - - mapped_object* obj = addrSpaces[0]->getAOut(); - DynAddrSpacePtr as = DynAddrSpace::create(obj); - PatchMgrPtr mgr = PatchMgr::create(as); - - mapped_object* lib_obj = addrSpaces[1]->getAOut(); - as->loadLibrary(lib_obj); - - // Find Points - PatchFunction* foo3 = lib_obj->getFunc(foo3_func); - const vector& blks = foo3->getCallBlocks(); - for (int i = 0; i < blks.size(); i++) { - vector func_points; - mgr->findPoints(blks[i], Point::PreInsn|Point::PostInsn, inserter(func_points, func_points.begin())); - cerr << std::hex << blks[i]->start() << "--" << func_points.size() << " points found\n"; - } - /* - vector pts; - mgr->findPoints(foo3, Point::FuncExit, inserter(pts, pts.begin())); - cerr << pts.size() << " exit points found\n"; - const vector& blks2 = foo3->getExitBlocks(); - cerr << blks2.size() << " exit blocks\n"; - - // Insert snippets - BPatch_variableExpr *intCounter = app->malloc(*image->findType("int")); - BPatch_arithExpr addOne(BPatch_assign, *intCounter, - BPatch_arithExpr(BPatch_plus, *intCounter, BPatch_constExpr(1))); - BPatch_arithExpr addTwo(BPatch_assign, *intCounter, - BPatch_arithExpr(BPatch_plus, *intCounter, BPatch_constExpr(2))); - BPatch_arithExpr addThree(BPatch_assign, *intCounter, - BPatch_arithExpr(BPatch_plus, *intCounter, BPatch_constExpr(3))); - BPatch_arithExpr addFour(BPatch_assign, *intCounter, - BPatch_arithExpr(BPatch_plus, *intCounter, BPatch_constExpr(4))); - - SnippetRep one(addOne.ast_wrapper); - SnippetRep two(addTwo.ast_wrapper); - SnippetRep three(addThree.ast_wrapper); - SnippetRep four(addFour.ast_wrapper); - SnippetPtr snippet = Snippet::create(&one); - SnippetPtr snippet1 = Snippet::create(&two); - SnippetPtr snippet2 = Snippet::create(&three); - SnippetPtr snippet3 = Snippet::create(&four); - - vector errorInstances; - - mgr->batchStart(); - func_points[0]->push_back(snippet); - mgr->batchFinish(errorInstances); - */ -} diff --git a/patchAPI/test/findPoint/mutatee/Makefile b/patchAPI/test/findPoint/mutatee/Makefile deleted file mode 100644 index 59d467fbd8..0000000000 --- a/patchAPI/test/findPoint/mutatee/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -all: c liblib.so - -c: main.c - gcc -o c main.c - objdump -S c > bin - -liblib.so: lib.c - gcc -o liblib.so lib.c -shared -fPIC - -clean: - rm -rf c bin *.so diff --git a/patchAPI/test/findPoint/mutatee/lib.c b/patchAPI/test/findPoint/mutatee/lib.c deleted file mode 100644 index f9e2cb29f8..0000000000 --- a/patchAPI/test/findPoint/mutatee/lib.c +++ /dev/null @@ -1,38 +0,0 @@ -/* - * See the dyninst/COPYRIGHT file for copyright information. - * - * We provide the Paradyn Tools (below described as "Paradyn") - * on an AS IS basis, and do not warrant its validity or performance. - * We reserve the right to update, modify, or discontinue this - * software at any time. We shall have no obligation to supply such - * updates or modifications or any other form of support to you. - * - * By your use of Paradyn, you understand and agree that we (or any - * other person or entity with proprietary rights in Paradyn) are - * under no obligation to provide either maintenance services, - * update services, notices of latent defects, or correction of - * defects for Paradyn. - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - */ -#include -#include - -void foo3() { - printf("i'm foo3\n"); - if (rand() < 100) return; - else return; - return; -} diff --git a/patchAPI/test/findPoint/run.sh b/patchAPI/test/findPoint/run.sh deleted file mode 100644 index fea3bb8eb2..0000000000 --- a/patchAPI/test/findPoint/run.sh +++ /dev/null @@ -1,2 +0,0 @@ -rm log -./test.exe > log diff --git a/proccontrol/CMakeLists.txt b/proccontrol/CMakeLists.txt index 327e1938c2..9d6af6f2c6 100644 --- a/proccontrol/CMakeLists.txt +++ b/proccontrol/CMakeLists.txt @@ -1,95 +1,127 @@ -# CMake configuration for proccontrol directory +include_guard(GLOBAL) -include_directories ( - src - h - ) +include(DyninstLibrary) -set (SRC_LIST - src/event.C - src/generator.C - src/handler.C - src/mailbox.C - src/process.C - src/pcerrors.C - src/procpool.C - src/irpc.C - src/response.C - src/resp.C - src/memcache.C - src/procset.C - src/processplat.C - src/loadLibrary/injector.C - src/loadLibrary/codegen.C - src/loadLibrary/codegen-x86.C - src/loadLibrary/codegen-ppc.C - src/loadLibrary/codegen-aarch64.C - src/x86_process.C - src/ppc_process.C - src/arm_process.C - src/pcmachsyscall.C - ) -if(UNIX) -set (SRC_LIST ${SRC_LIST} - src/sysv.C - src/int_thread_db.C - src/mmapalloc.C -) -elseif(WIN32) -set (SRC_LIST ${SRC_LIST} - src/GeneratorWindows.C - src/DecoderWindows.C - src/windows_handler.C - src/windows_process.C - src/windows_thread.C - src/loadLibrary/codegen-win.C - ../common/src/dthread-win.C - ../common/src/dthread.C -) -endif() - -if (PLATFORM MATCHES freebsd) -set (SRC_LIST ${SRC_LIST} - src/freebsd.C - src/unix.C - src/notify_pipe.C - ../common/src/dthread-unix.C - ../common/src/dthread.C - src/loadLibrary/codegen-freebsd.C - ) -elseif (PLATFORM MATCHES linux) -set (SRC_LIST ${SRC_LIST} - src/linux.C - src/unix.C - src/notify_pipe.C - ../common/src/dthread-unix.C - ../common/src/dthread.C - src/loadLibrary/codegen-linux.C - ) -elseif (PLATFORM MATCHES cnl) -set (SRC_LIST ${SRC_LIST} - src/linux.C - src/unix.C - src/notify_pipe.C - ../common/src/dthread-unix.C - ../common/src/dthread.C - src/loadLibrary/codegen-stub.C - ) -endif() +set(_public_headers + h/Decoder.h + h/Event.h + h/EventType.h + h/Handler.h + h/Mailbox.h + h/PCErrors.h + h/PCProcess.h + h/PlatFeatures.h + h/ProcessSet.h) -SET_SOURCE_FILES_PROPERTIES(${SRC_LIST} PROPERTIES LANGUAGE CXX) +set(_private_headers + src/arm_process.h + src/DecoderWindows.h + src/freebsd.h + src/GeneratorWindows.h + src/int_event.h + src/int_handler.h + src/int_process.h + src/int_thread_db.h + src/irpc.h + src/linux.h + src/loadLibrary/codegen.h + src/loadLibrary/injector.h + src/memcache.h + src/mmapalloc.h + src/notify_pipe.h + src/ppc_process.h + src/processplat.h + src/procpool.h + src/proc_service_wrapper.h + src/resp.h + src/response.h + src/snippets.h + src/sysv.h + src/unix.h + src/windows_handler.h + src/windows_process.h + src/windows_thread.h + src/x86_process.h) -ADD_DEFINITIONS(-DPROCCONTROL_EXPORTS) +set(_sources + src/event.C + src/generator.C + src/handler.C + src/mailbox.C + src/process.C + src/pcerrors.C + src/procpool.C + src/irpc.C + src/response.C + src/resp.C + src/memcache.C + src/procset.C + src/processplat.C + src/loadLibrary/injector.C + src/loadLibrary/codegen.C + src/loadLibrary/codegen-x86.C + src/loadLibrary/codegen-ppc.C + src/loadLibrary/codegen-aarch64.C + src/x86_process.C + src/ppc_process.C + src/arm_process.C + src/pcmachsyscall.C) -set (DEPS common ${SYMREADER}) +if(DYNINST_OS_UNIX) + list(APPEND _sources src/sysv.C src/int_thread_db.C src/mmapalloc.C) +elseif(DYNINST_OS_Windows) + list( + APPEND + _sources + src/GeneratorWindows.C + src/DecoderWindows.C + src/windows_handler.C + src/windows_process.C + src/windows_thread.C + src/loadLibrary/codegen-win.C + ../common/src/dthread-win.C + ../common/src/dthread.C) +endif() -dyninst_library(pcontrol ${DEPS}) +if(DYNINST_OS_FreeBSD) + list( + APPEND + _sources + src/freebsd.C + src/unix.C + src/notify_pipe.C + ../common/src/dthread-unix.C + ../common/src/dthread.C + src/loadLibrary/codegen-freebsd.C) +elseif(DYNINST_OS_Linux) + list( + APPEND + _sources + src/linux.C + src/unix.C + src/notify_pipe.C + ../common/src/dthread-unix.C + ../common/src/dthread.C + src/loadLibrary/codegen-linux.C) +endif() -target_link_private_libraries(pcontrol ${CMAKE_DL_LIBS}) -target_link_private_libraries(pcontrol ${Boost_LIBRARIES}) +# cmake-format: off +dyninst_library( + pcontrol + PUBLIC_HEADER_FILES ${_public_headers} + PRIVATE_HEADER_FILES ${_private_headers} + SOURCE_FILES ${_sources} + DEFINES PROCCONTROL_EXPORTS + DYNINST_DEPS common ${SYMREADER} + PUBLIC_DEPS + PRIVATE_DEPS ${CMAKE_DL_LIBS} Dyninst::Thread_DB Threads::Threads +) +# cmake-format: on -if (UNIX) -# Boost auto-links on Windows; don't double-link -target_link_private_libraries(pcontrol pthread) +# When using symlite, we still need the symtabAPI headers +if(LIGHTWEIGHT_SYMTAB) + foreach(t ${pcontrol_TARGETS}) + target_include_directories( + ${t} PUBLIC "$") + endforeach() endif() - diff --git a/proccontrol/doc/proccontrol.docx b/proccontrol/doc/proccontrol.docx index 7e9eafb010..5a2d7a4396 100644 Binary files a/proccontrol/doc/proccontrol.docx and b/proccontrol/doc/proccontrol.docx differ diff --git a/proccontrol/doc/proccontrol.pdf b/proccontrol/doc/proccontrol.pdf index ab2c419eee..288d2ca99a 100644 Binary files a/proccontrol/doc/proccontrol.pdf and b/proccontrol/doc/proccontrol.pdf differ diff --git a/proccontrol/dumplibpthread.asm b/proccontrol/dumplibpthread.asm deleted file mode 100644 index a249f0cd39..0000000000 --- a/proccontrol/dumplibpthread.asm +++ /dev/null @@ -1,14605 +0,0 @@ - -/usr/lib64/libpthread-2.20.so: file format elf64-littleaarch64 - - -Disassembly of section .init: - -0000000000004f28 <_init>: - 4f28: a9bf7bfd stp x29, x30, [sp,#-16]! - 4f2c: 910003fd mov x29, sp - 4f30: 940001f8 bl 5710 <__pthread_initialize_minimal> - 4f34: a8c17bfd ldp x29, x30, [sp],#16 - 4f38: d65f03c0 ret - -Disassembly of section .plt: - -0000000000004f40 : - 4f40: a9bf7bf0 stp x16, x30, [sp,#-16]! - 4f44: f0000150 adrp x16, 2f000 <__FRAME_END__+0x18e30> - 4f48: f947fe11 ldr x17, [x16,#4088] - 4f4c: 913fe210 add x16, x16, #0xff8 - 4f50: d61f0220 br x17 - 4f54: d503201f nop - 4f58: d503201f nop - 4f5c: d503201f nop - -0000000000004f60 : - 4f60: 90000170 adrp x16, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 4f64: f9400211 ldr x17, [x16] - 4f68: 91000210 add x16, x16, #0x0 - 4f6c: d61f0220 br x17 - -0000000000004f70 <_exit@plt>: - 4f70: 90000170 adrp x16, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 4f74: f9400611 ldr x17, [x16,#8] - 4f78: 91002210 add x16, x16, #0x8 - 4f7c: d61f0220 br x17 - -0000000000004f80 : - 4f80: 90000170 adrp x16, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 4f84: f9400a11 ldr x17, [x16,#16] - 4f88: 91004210 add x16, x16, #0x10 - 4f8c: d61f0220 br x17 - -0000000000004f90 : - 4f90: 90000170 adrp x16, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 4f94: f9400e11 ldr x17, [x16,#24] - 4f98: 91006210 add x16, x16, #0x18 - 4f9c: d61f0220 br x17 - -0000000000004fa0 <_setjmp@plt>: - 4fa0: 90000170 adrp x16, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 4fa4: f9401211 ldr x17, [x16,#32] - 4fa8: 91008210 add x16, x16, #0x20 - 4fac: d61f0220 br x17 - -0000000000004fb0 <__getrlimit@plt>: - 4fb0: 90000170 adrp x16, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 4fb4: f9401611 ldr x17, [x16,#40] - 4fb8: 9100a210 add x16, x16, #0x28 - 4fbc: d61f0220 br x17 - -0000000000004fc0 <__gettimeofday@plt>: - 4fc0: 90000170 adrp x16, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 4fc4: f9401a11 ldr x17, [x16,#48] - 4fc8: 9100c210 add x16, x16, #0x30 - 4fcc: d61f0220 br x17 - -0000000000004fd0 : - 4fd0: 90000170 adrp x16, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 4fd4: f9401e11 ldr x17, [x16,#56] - 4fd8: 9100e210 add x16, x16, #0x38 - 4fdc: d61f0220 br x17 - -0000000000004fe0 <__libc_dlclose@plt>: - 4fe0: 90000170 adrp x16, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 4fe4: f9402211 ldr x17, [x16,#64] - 4fe8: 91010210 add x16, x16, #0x40 - 4fec: d61f0220 br x17 - -0000000000004ff0 <__libc_fatal@plt>: - 4ff0: 90000170 adrp x16, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 4ff4: f9402611 ldr x17, [x16,#72] - 4ff8: 91012210 add x16, x16, #0x48 - 4ffc: d61f0220 br x17 - -0000000000005000 <__getpagesize@plt>: - 5000: f0000150 adrp x16, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 5004: f9402a11 ldr x17, [x16,#80] - 5008: 91014210 add x16, x16, #0x50 - 500c: d61f0220 br x17 - -0000000000005010 <__cxa_finalize@plt>: - 5010: f0000150 adrp x16, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 5014: f9402e11 ldr x17, [x16,#88] - 5018: 91016210 add x16, x16, #0x58 - 501c: d61f0220 br x17 - -0000000000005020 : - 5020: f0000150 adrp x16, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 5024: f9403211 ldr x17, [x16,#96] - 5028: 91018210 add x16, x16, #0x60 - 502c: d61f0220 br x17 - -0000000000005030 : - 5030: f0000150 adrp x16, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 5034: f9403611 ldr x17, [x16,#104] - 5038: 9101a210 add x16, x16, #0x68 - 503c: d61f0220 br x17 - -0000000000005040 : - 5040: f0000150 adrp x16, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 5044: f9403a11 ldr x17, [x16,#112] - 5048: 9101c210 add x16, x16, #0x70 - 504c: d61f0220 br x17 - -0000000000005050 : - 5050: f0000150 adrp x16, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 5054: f9403e11 ldr x17, [x16,#120] - 5058: 9101e210 add x16, x16, #0x78 - 505c: d61f0220 br x17 - -0000000000005060 <__libc_system@plt>: - 5060: f0000150 adrp x16, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 5064: f9404211 ldr x17, [x16,#128] - 5068: 91020210 add x16, x16, #0x80 - 506c: d61f0220 br x17 - -0000000000005070 : - 5070: f0000150 adrp x16, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 5074: f9404611 ldr x17, [x16,#136] - 5078: 91022210 add x16, x16, #0x88 - 507c: d61f0220 br x17 - -0000000000005080 : - 5080: f0000150 adrp x16, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 5084: f9404a11 ldr x17, [x16,#144] - 5088: 91024210 add x16, x16, #0x90 - 508c: d61f0220 br x17 - -0000000000005090 : - 5090: f0000150 adrp x16, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 5094: f9404e11 ldr x17, [x16,#152] - 5098: 91026210 add x16, x16, #0x98 - 509c: d61f0220 br x17 - -00000000000050a0 <__libc_fork@plt>: - 50a0: f0000150 adrp x16, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 50a4: f9405211 ldr x17, [x16,#160] - 50a8: 91028210 add x16, x16, #0xa0 - 50ac: d61f0220 br x17 - -00000000000050b0 <__endmntent@plt>: - 50b0: f0000150 adrp x16, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 50b4: f9405611 ldr x17, [x16,#168] - 50b8: 9102a210 add x16, x16, #0xa8 - 50bc: d61f0220 br x17 - -00000000000050c0 : - 50c0: f0000150 adrp x16, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 50c4: f9405a11 ldr x17, [x16,#176] - 50c8: 9102c210 add x16, x16, #0xb0 - 50cc: d61f0220 br x17 - -00000000000050d0 : - 50d0: f0000150 adrp x16, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 50d4: f9405e11 ldr x17, [x16,#184] - 50d8: 9102e210 add x16, x16, #0xb8 - 50dc: d61f0220 br x17 - -00000000000050e0 <_dl_deallocate_tls@plt>: - 50e0: f0000150 adrp x16, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 50e4: f9406211 ldr x17, [x16,#192] - 50e8: 91030210 add x16, x16, #0xc0 - 50ec: d61f0220 br x17 - -00000000000050f0 : - 50f0: f0000150 adrp x16, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 50f4: f9406611 ldr x17, [x16,#200] - 50f8: 91032210 add x16, x16, #0xc8 - 50fc: d61f0220 br x17 - -0000000000005100 <__call_tls_dtors@plt>: - 5100: f0000150 adrp x16, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 5104: f9406a11 ldr x17, [x16,#208] - 5108: 91034210 add x16, x16, #0xd0 - 510c: d61f0220 br x17 - -0000000000005110 : - 5110: f0000150 adrp x16, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 5114: f9406e11 ldr x17, [x16,#216] - 5118: 91036210 add x16, x16, #0xd8 - 511c: d61f0220 br x17 - -0000000000005120 <__libc_thread_freeres@plt>: - 5120: f0000150 adrp x16, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 5124: f9407211 ldr x17, [x16,#224] - 5128: 91038210 add x16, x16, #0xe0 - 512c: d61f0220 br x17 - -0000000000005130 <__sched_getparam@plt>: - 5130: f0000150 adrp x16, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 5134: f9407611 ldr x17, [x16,#232] - 5138: 9103a210 add x16, x16, #0xe8 - 513c: d61f0220 br x17 - -0000000000005140 : - 5140: f0000150 adrp x16, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 5144: f9407a11 ldr x17, [x16,#240] - 5148: 9103c210 add x16, x16, #0xf0 - 514c: d61f0220 br x17 - -0000000000005150 <__statfs@plt>: - 5150: f0000150 adrp x16, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 5154: f9407e11 ldr x17, [x16,#248] - 5158: 9103e210 add x16, x16, #0xf8 - 515c: d61f0220 br x17 - -0000000000005160 : - 5160: f0000150 adrp x16, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 5164: f9408211 ldr x17, [x16,#256] - 5168: 91040210 add x16, x16, #0x100 - 516c: d61f0220 br x17 - -0000000000005170 : - 5170: f0000150 adrp x16, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 5174: f9408611 ldr x17, [x16,#264] - 5178: 91042210 add x16, x16, #0x108 - 517c: d61f0220 br x17 - -0000000000005180 <__sched_get_priority_min@plt>: - 5180: f0000150 adrp x16, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 5184: f9408a11 ldr x17, [x16,#272] - 5188: 91044210 add x16, x16, #0x110 - 518c: d61f0220 br x17 - -0000000000005190 <__libc_current_sigrtmax_private@plt>: - 5190: f0000150 adrp x16, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 5194: f9408e11 ldr x17, [x16,#280] - 5198: 91046210 add x16, x16, #0x118 - 519c: d61f0220 br x17 - -00000000000051a0 : - 51a0: f0000150 adrp x16, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 51a4: f9409211 ldr x17, [x16,#288] - 51a8: 91048210 add x16, x16, #0x120 - 51ac: d61f0220 br x17 - -00000000000051b0 <__libc_dlopen_mode@plt>: - 51b0: f0000150 adrp x16, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 51b4: f9409611 ldr x17, [x16,#296] - 51b8: 9104a210 add x16, x16, #0x128 - 51bc: d61f0220 br x17 - -00000000000051c0 : - 51c0: f0000150 adrp x16, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 51c4: f9409a11 ldr x17, [x16,#304] - 51c8: 9104c210 add x16, x16, #0x130 - 51cc: d61f0220 br x17 - -00000000000051d0 : - 51d0: f0000150 adrp x16, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 51d4: f9409e11 ldr x17, [x16,#312] - 51d8: 9104e210 add x16, x16, #0x138 - 51dc: d61f0220 br x17 - -00000000000051e0 <_dl_make_stack_executable@plt>: - 51e0: f0000150 adrp x16, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 51e4: f940a211 ldr x17, [x16,#320] - 51e8: 91050210 add x16, x16, #0x140 - 51ec: d61f0220 br x17 - -00000000000051f0 : - 51f0: f0000150 adrp x16, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 51f4: f940a611 ldr x17, [x16,#328] - 51f8: 91052210 add x16, x16, #0x148 - 51fc: d61f0220 br x17 - -0000000000005200 <__libc_pthread_init@plt>: - 5200: f0000150 adrp x16, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 5204: f940aa11 ldr x17, [x16,#336] - 5208: 91054210 add x16, x16, #0x150 - 520c: d61f0220 br x17 - -0000000000005210 <__ctype_init@plt>: - 5210: f0000150 adrp x16, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 5214: f940ae11 ldr x17, [x16,#344] - 5218: 91056210 add x16, x16, #0x158 - 521c: d61f0220 br x17 - -0000000000005220 : - 5220: f0000150 adrp x16, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 5224: f940b211 ldr x17, [x16,#352] - 5228: 91058210 add x16, x16, #0x160 - 522c: d61f0220 br x17 - -0000000000005230 : - 5230: f0000150 adrp x16, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 5234: f940b611 ldr x17, [x16,#360] - 5238: 9105a210 add x16, x16, #0x168 - 523c: d61f0220 br x17 - -0000000000005240 <__setmntent@plt>: - 5240: f0000150 adrp x16, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 5244: f940ba11 ldr x17, [x16,#368] - 5248: 9105c210 add x16, x16, #0x170 - 524c: d61f0220 br x17 - -0000000000005250 <__getmntent_r@plt>: - 5250: f0000150 adrp x16, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 5254: f940be11 ldr x17, [x16,#376] - 5258: 9105e210 add x16, x16, #0x178 - 525c: d61f0220 br x17 - -0000000000005260 : - 5260: f0000150 adrp x16, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 5264: f940c211 ldr x17, [x16,#384] - 5268: 91060210 add x16, x16, #0x180 - 526c: d61f0220 br x17 - -0000000000005270 <__fxstat64@plt>: - 5270: f0000150 adrp x16, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 5274: f940c611 ldr x17, [x16,#392] - 5278: 91062210 add x16, x16, #0x188 - 527c: d61f0220 br x17 - -0000000000005280 <__libc_dlsym@plt>: - 5280: f0000150 adrp x16, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 5284: f940ca11 ldr x17, [x16,#400] - 5288: 91064210 add x16, x16, #0x190 - 528c: d61f0220 br x17 - -0000000000005290 <__sched_setscheduler@plt>: - 5290: f0000150 adrp x16, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 5294: f940ce11 ldr x17, [x16,#408] - 5298: 91066210 add x16, x16, #0x198 - 529c: d61f0220 br x17 - -00000000000052a0 <__libc_current_sigrtmin_private@plt>: - 52a0: f0000150 adrp x16, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 52a4: f940d211 ldr x17, [x16,#416] - 52a8: 91068210 add x16, x16, #0x1a0 - 52ac: d61f0220 br x17 - -00000000000052b0 : - 52b0: f0000150 adrp x16, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 52b4: f940d611 ldr x17, [x16,#424] - 52b8: 9106a210 add x16, x16, #0x1a8 - 52bc: d61f0220 br x17 - -00000000000052c0 : - 52c0: f0000150 adrp x16, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 52c4: f940da11 ldr x17, [x16,#432] - 52c8: 9106c210 add x16, x16, #0x1b0 - 52cc: d61f0220 br x17 - -00000000000052d0 <__madvise@plt>: - 52d0: f0000150 adrp x16, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 52d4: f940de11 ldr x17, [x16,#440] - 52d8: 9106e210 add x16, x16, #0x1b8 - 52dc: d61f0220 br x17 - -00000000000052e0 <__libc_dl_error_tsd@plt>: - 52e0: f0000150 adrp x16, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 52e4: f940e211 ldr x17, [x16,#448] - 52e8: 91070210 add x16, x16, #0x1c0 - 52ec: d61f0220 br x17 - -00000000000052f0 <__mktemp@plt>: - 52f0: f0000150 adrp x16, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 52f4: f940e611 ldr x17, [x16,#456] - 52f8: 91072210 add x16, x16, #0x1c8 - 52fc: d61f0220 br x17 - -0000000000005300 <__clone@plt>: - 5300: f0000150 adrp x16, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 5304: f940ea11 ldr x17, [x16,#464] - 5308: 91074210 add x16, x16, #0x1d0 - 530c: d61f0220 br x17 - -0000000000005310 <_dl_allocate_tls@plt>: - 5310: f0000150 adrp x16, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 5314: f940ee11 ldr x17, [x16,#472] - 5318: 91076210 add x16, x16, #0x1d8 - 531c: d61f0220 br x17 - -0000000000005320 : - 5320: f0000150 adrp x16, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 5324: f940f211 ldr x17, [x16,#480] - 5328: 91078210 add x16, x16, #0x1e0 - 532c: d61f0220 br x17 - -0000000000005330 <__sched_getscheduler@plt>: - 5330: f0000150 adrp x16, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 5334: f940f611 ldr x17, [x16,#488] - 5338: 9107a210 add x16, x16, #0x1e8 - 533c: d61f0220 br x17 - -0000000000005340 <_dl_get_tls_static_info@plt>: - 5340: f0000150 adrp x16, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 5344: f940fa11 ldr x17, [x16,#496] - 5348: 9107c210 add x16, x16, #0x1f0 - 534c: d61f0220 br x17 - -0000000000005350 <__sched_get_priority_max@plt>: - 5350: f0000150 adrp x16, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 5354: f940fe11 ldr x17, [x16,#504] - 5358: 9107e210 add x16, x16, #0x1f8 - 535c: d61f0220 br x17 - -0000000000005360 <__libc_alloca_cutoff@plt>: - 5360: f0000150 adrp x16, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 5364: f9410211 ldr x17, [x16,#512] - 5368: 91080210 add x16, x16, #0x200 - 536c: d61f0220 br x17 - -0000000000005370 <_dl_allocate_tls_init@plt>: - 5370: f0000150 adrp x16, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 5374: f9410611 ldr x17, [x16,#520] - 5378: 91082210 add x16, x16, #0x208 - 537c: d61f0220 br x17 - -0000000000005380 : - 5380: f0000150 adrp x16, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 5384: f9410a11 ldr x17, [x16,#528] - 5388: 91084210 add x16, x16, #0x210 - 538c: d61f0220 br x17 - -0000000000005390 <__libc_allocate_rtsig_private@plt>: - 5390: f0000150 adrp x16, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 5394: f9410e11 ldr x17, [x16,#536] - 5398: 91086210 add x16, x16, #0x218 - 539c: d61f0220 br x17 - -00000000000053a0 <__libc_longjmp@plt>: - 53a0: f0000150 adrp x16, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 53a4: f9411211 ldr x17, [x16,#544] - 53a8: 91088210 add x16, x16, #0x220 - 53ac: d61f0220 br x17 - -00000000000053b0 : - 53b0: f0000150 adrp x16, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 53b4: f9411611 ldr x17, [x16,#552] - 53b8: 9108a210 add x16, x16, #0x228 - 53bc: d61f0220 br x17 - -00000000000053c0 <__getdelim@plt>: - 53c0: f0000150 adrp x16, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 53c4: f9411a11 ldr x17, [x16,#560] - 53c8: 9108c210 add x16, x16, #0x230 - 53cc: d61f0220 br x17 - -00000000000053d0 : - 53d0: f0000150 adrp x16, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 53d4: f9411e11 ldr x17, [x16,#568] - 53d8: 9108e210 add x16, x16, #0x238 - 53dc: d61f0220 br x17 - -00000000000053e0 : - 53e0: a9bf0fe2 stp x2, x3, [sp,#-16]! - 53e4: d0000142 adrp x2, 2f000 <__FRAME_END__+0x18e30> - 53e8: d0000143 adrp x3, 2f000 <__FRAME_END__+0x18e30> - 53ec: f947f042 ldr x2, [x2,#4064] - 53f0: 913fa063 add x3, x3, #0xfe8 - 53f4: d61f0040 br x2 - 53f8: d503201f nop - 53fc: d503201f nop - -Disassembly of section .text: - -0000000000005400 : - 5400: f0000141 adrp x1, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 5404: f0000140 adrp x0, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 5408: 910a0021 add x1, x1, #0x280 - 540c: 910a0000 add x0, x0, #0x280 - 5410: 91001c21 add x1, x1, #0x7 - 5414: a9bf7bfd stp x29, x30, [sp,#-16]! - 5418: cb000021 sub x1, x1, x0 - 541c: f100383f cmp x1, #0xe - 5420: 910003fd mov x29, sp - 5424: 540000a9 b.ls 5438 - 5428: d0000141 adrp x1, 2f000 <__FRAME_END__+0x18e30> - 542c: f947c021 ldr x1, [x1,#3968] - 5430: b4000041 cbz x1, 5438 - 5434: d63f0020 blr x1 - 5438: a8c17bfd ldp x29, x30, [sp],#16 - 543c: d65f03c0 ret - -0000000000005440 : - 5440: f0000140 adrp x0, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 5444: f0000141 adrp x1, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 5448: 910a0000 add x0, x0, #0x280 - 544c: 910a0021 add x1, x1, #0x280 - 5450: cb000021 sub x1, x1, x0 - 5454: 9343fc22 asr x2, x1, #3 - 5458: a9bf7bfd stp x29, x30, [sp,#-16]! - 545c: 8b42fc42 add x2, x2, x2, lsr #63 - 5460: 9341fc41 asr x1, x2, #1 - 5464: 910003fd mov x29, sp - 5468: b40000a1 cbz x1, 547c - 546c: d0000142 adrp x2, 2f000 <__FRAME_END__+0x18e30> - 5470: f947e842 ldr x2, [x2,#4048] - 5474: b4000042 cbz x2, 547c - 5478: d63f0040 blr x2 - 547c: a8c17bfd ldp x29, x30, [sp],#16 - 5480: d65f03c0 ret - -0000000000005484 <__do_global_dtors_aux>: - 5484: a9be7bfd stp x29, x30, [sp,#-32]! - 5488: 910003fd mov x29, sp - 548c: f9000bf3 str x19, [sp,#16] - 5490: f0000153 adrp x19, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 5494: 394a0260 ldrb w0, [x19,#640] - 5498: 35000140 cbnz w0, 54c0 <__do_global_dtors_aux+0x3c> - 549c: d0000140 adrp x0, 2f000 <__FRAME_END__+0x18e30> - 54a0: f947c800 ldr x0, [x0,#3984] - 54a4: b4000080 cbz x0, 54b4 <__do_global_dtors_aux+0x30> - 54a8: d0000140 adrp x0, 2f000 <__FRAME_END__+0x18e30> - 54ac: 912e0000 add x0, x0, #0xb80 - 54b0: 97fffed8 bl 5010 <__cxa_finalize@plt> - 54b4: 97ffffd3 bl 5400 - 54b8: 52800020 mov w0, #0x1 // #1 - 54bc: 390a0260 strb w0, [x19,#640] - 54c0: f9400bf3 ldr x19, [sp,#16] - 54c4: a8c27bfd ldp x29, x30, [sp],#32 - 54c8: d65f03c0 ret - -00000000000054cc : - 54cc: a9bf7bfd stp x29, x30, [sp,#-16]! - 54d0: d0000140 adrp x0, 2f000 <__FRAME_END__+0x18e30> - 54d4: 910003fd mov x29, sp - 54d8: 912de000 add x0, x0, #0xb78 - 54dc: f9400001 ldr x1, [x0] - 54e0: b5000061 cbnz x1, 54ec - 54e4: a8c17bfd ldp x29, x30, [sp],#16 - 54e8: 17ffffd6 b 5440 - 54ec: d0000141 adrp x1, 2f000 <__FRAME_END__+0x18e30> - 54f0: f947e421 ldr x1, [x1,#4040] - 54f4: b4ffff81 cbz x1, 54e4 - 54f8: d63f0020 blr x1 - 54fc: 17fffffa b 54e4 - -0000000000005500 <__nptl_set_robust>: - 5500: 91038000 add x0, x0, #0xe0 - 5504: d2800301 mov x1, #0x18 // #24 - 5508: d2800c68 mov x8, #0x63 // #99 - 550c: d4000001 svc #0x0 - 5510: d65f03c0 ret - -0000000000005514 : - 5514: d53bd043 mrs x3, tpidr_el0 - 5518: 7100801f cmp w0, #0x20 - 551c: a9be7bfd stp x29, x30, [sp,#-32]! - 5520: d11bc062 sub x2, x3, #0x6f0 - 5524: 910003fd mov x29, sp - 5528: b940d440 ldr w0, [x2,#212] - 552c: 54000060 b.eq 5538 - 5530: a8c27bfd ldp x29, x30, [sp],#32 - 5534: d65f03c0 ret - 5538: 93407c00 sxtw x0, w0 - 553c: b9401024 ldr w4, [x1,#16] - 5540: ca80fc05 eor x5, x0, x0, asr #63 - 5544: cb80fca0 sub x0, x5, x0, asr #63 - 5548: 6b00009f cmp w4, w0 - 554c: 54ffff21 b.ne 5530 - 5550: b9400820 ldr w0, [x1,#8] - 5554: 3100181f cmn w0, #0x6 - 5558: 54fffec1 b.ne 5530 - 555c: b9410840 ldr w0, [x2,#264] - 5560: 321e0404 orr w4, w0, #0xc - 5564: 6b04001f cmp w0, w4 - 5568: 54fffe40 b.eq 5530 - 556c: 3727fe20 tbnz w0, #4, 5530 - 5570: 910083a6 add x6, x29, #0x20 - 5574: 91042045 add x5, x2, #0x108 - 5578: 2a0003e1 mov w1, w0 - 557c: b81fccc0 str w0, [x6,#-4]! - 5580: 885ffca7 ldaxr w7, [x5] - 5584: 6b0100ff cmp w7, w1 - 5588: 54000061 b.ne 5594 - 558c: 88087ca4 stxr w8, w4, [x5] - 5590: 35ffff88 cbnz w8, 5580 - 5594: 54000040 b.eq 559c - 5598: b9001fa7 str w7, [x29,#28] - 559c: b9401fa1 ldr w1, [x29,#28] - 55a0: 6b01001f cmp w0, w1 - 55a4: 54000060 b.eq 55b0 - 55a8: 2a0103e0 mov w0, w1 - 55ac: 17ffffed b 5560 - 55b0: 92800001 mov x1, #0xffffffffffffffff // #-1 - 55b4: f9021441 str x1, [x2,#1064] - 55b8: 360ffbc0 tbz w0, #1, 5530 - 55bc: d117a063 sub x3, x3, #0x5e8 - 55c0: b9400060 ldr w0, [x3] - 55c4: b9001fa0 str w0, [x29,#28] - 55c8: 321c0004 orr w4, w0, #0x10 - 55cc: 885ffca1 ldaxr w1, [x5] - 55d0: 6b00003f cmp w1, w0 - 55d4: 54000061 b.ne 55e0 - 55d8: 88077ca4 stxr w7, w4, [x5] - 55dc: 35ffff87 cbnz w7, 55cc - 55e0: 54000060 b.eq 55ec - 55e4: b90000c1 str w1, [x6] - 55e8: 17fffff6 b 55c0 - 55ec: f9408040 ldr x0, [x2,#256] - 55f0: 940027c5 bl f504 <__pthread_unwind> - -00000000000055f4 : - 55f4: a9bd7bfd stp x29, x30, [sp,#-48]! - 55f8: 7100841f cmp w0, #0x21 - 55fc: 910003fd mov x29, sp - 5600: a90153f3 stp x19, x20, [sp,#16] - 5604: d53bd053 mrs x19, tpidr_el0 - 5608: d11bc273 sub x19, x19, #0x6f0 - 560c: b940d660 ldr w0, [x19,#212] - 5610: 54000080 b.eq 5620 - 5614: a94153f3 ldp x19, x20, [sp,#16] - 5618: a8c37bfd ldp x29, x30, [sp],#48 - 561c: d65f03c0 ret - 5620: 93407c00 sxtw x0, w0 - 5624: b9401022 ldr w2, [x1,#16] - 5628: ca80fc03 eor x3, x0, x0, asr #63 - 562c: cb80fc60 sub x0, x3, x0, asr #63 - 5630: 6b00005f cmp w2, w0 - 5634: 54ffff01 b.ne 5614 - 5638: b9400820 ldr w0, [x1,#8] - 563c: 3100181f cmn w0, #0x6 - 5640: 54fffea1 b.ne 5614 - 5644: f0000174 adrp x20, 34000 <__GI___pthread_keys+0x3d78> - 5648: f9418a83 ldr x3, [x20,#784] - 564c: f9400460 ldr x0, [x3,#8] - 5650: f9400861 ldr x1, [x3,#16] - 5654: f9400c62 ldr x2, [x3,#24] - 5658: b9800068 ldrsw x8, [x3] - 565c: d4000001 svc #0x0 - 5660: aa0003e1 mov x1, x0 - 5664: f9418a80 ldr x0, [x20,#784] - 5668: 3140043f cmn w1, #0x1, lsl #12 - 566c: 5a8197e1 csneg w1, wzr, w1, ls - 5670: 9400037a bl 6458 <__nptl_setxid_error> - 5674: 91042261 add x1, x19, #0x108 - 5678: 9100b3a5 add x5, x29, #0x2c - 567c: b9410a60 ldr w0, [x19,#264] - 5680: b9002fa0 str w0, [x29,#44] - 5684: 12197803 and w3, w0, #0xffffffbf - 5688: 2a0003e2 mov w2, w0 - 568c: 885ffc24 ldaxr w4, [x1] - 5690: 6b02009f cmp w4, w2 - 5694: 54000061 b.ne 56a0 - 5698: 88067c23 stxr w6, w3, [x1] - 569c: 35ffff86 cbnz w6, 568c - 56a0: 54000040 b.eq 56a8 - 56a4: b90000a4 str w4, [x5] - 56a8: b9402fa2 ldr w2, [x29,#44] - 56ac: 6b02001f cmp w0, w2 - 56b0: 54fffe61 b.ne 567c - 56b4: 52800021 mov w1, #0x1 // #1 - 56b8: 91107260 add x0, x19, #0x41c - 56bc: b9041e61 str w1, [x19,#1052] - 56c0: d2800022 mov x2, #0x1 // #1 - 56c4: d2801021 mov x1, #0x81 // #129 - 56c8: d2800003 mov x3, #0x0 // #0 - 56cc: d2800c48 mov x8, #0x62 // #98 - 56d0: d4000001 svc #0x0 - 56d4: f9418a80 ldr x0, [x20,#784] - 56d8: 91008000 add x0, x0, #0x20 - 56dc: 885ffc04 ldaxr w4, [x0] - 56e0: 51000485 sub w5, w4, #0x1 - 56e4: 88067c05 stxr w6, w5, [x0] - 56e8: 35ffffa6 cbnz w6, 56dc - 56ec: b9002fa4 str w4, [x29,#44] - 56f0: b9402fa0 ldr w0, [x29,#44] - 56f4: 7100041f cmp w0, #0x1 - 56f8: 54fff8e1 b.ne 5614 - 56fc: f0000160 adrp x0, 34000 <__GI___pthread_keys+0x3d78> - 5700: f9418800 ldr x0, [x0,#784] - 5704: 91008000 add x0, x0, #0x20 - 5708: d4000001 svc #0x0 - 570c: 17ffffc2 b 5614 - -0000000000005710 <__pthread_initialize_minimal>: - 5710: a9b17bfd stp x29, x30, [sp,#-240]! - 5714: d53bd044 mrs x4, tpidr_el0 - 5718: d2800c08 mov x8, #0x60 // #96 - 571c: 910003fd mov x29, sp - 5720: d11bc083 sub x3, x4, #0x6f0 - 5724: 91034060 add x0, x3, #0xd0 - 5728: a90153f3 stp x19, x20, [sp,#16] - 572c: f90013f5 str x21, [sp,#32] - 5730: d4000001 svc #0x0 - 5734: 91038062 add x2, x3, #0xe0 - 5738: 91044061 add x1, x3, #0x110 - 573c: b900d060 str w0, [x3,#208] - 5740: d2800c68 mov x8, #0x63 // #99 - 5744: b900d460 str w0, [x3,#212] - 5748: 52800020 mov w0, #0x1 // #1 - 574c: f9018861 str x1, [x3,#784] - 5750: d2800301 mov x1, #0x18 // #24 - 5754: 39104860 strb w0, [x3,#1042] - 5758: aa0203e0 mov x0, x2 - 575c: f9006c62 str x2, [x3,#216] - 5760: f9007062 str x2, [x3,#224] - 5764: 928003e2 mov x2, #0xffffffffffffffe0 // #-32 - 5768: f9007462 str x2, [x3,#232] - 576c: d4000001 svc #0x0 - 5770: d0000147 adrp x7, 2f000 <__FRAME_END__+0x18e30> - 5774: f0000166 adrp x6, 34000 <__GI___pthread_keys+0x3d78> - 5778: 910aa0c5 add x5, x6, #0x2a8 - 577c: d118c084 sub x4, x4, #0x630 - 5780: 910183b3 add x19, x29, #0x60 - 5784: 91030068 add x8, x3, #0xc0 - 5788: f947e0e7 ldr x7, [x7,#4032] - 578c: 910163b5 add x21, x29, #0x58 - 5790: 52800094 mov w20, #0x4 // #4 - 5794: aa1503e1 mov x1, x21 - 5798: d2800002 mov x2, #0x0 // #0 - 579c: 52800400 mov w0, #0x20 // #32 - 57a0: f94000e7 ldr x7, [x7] - 57a4: f9024c67 str x7, [x3,#1176] - 57a8: f90154c5 str x5, [x6,#680] - 57ac: f90004a5 str x5, [x5,#8] - 57b0: f9000085 str x5, [x4] - 57b4: f9000485 str x5, [x4,#8] - 57b8: f94154c4 ldr x4, [x6,#680] - 57bc: f9000488 str x8, [x4,#8] - 57c0: f0000144 adrp x4, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 57c4: d5033bbf dmb ish - 57c8: f90154c8 str x8, [x6,#680] - 57cc: 394a0484 ldrb w4, [x4,#641] - 57d0: a9017e7f stp xzr, xzr, [x19,#16] - 57d4: a9027e7f stp xzr, xzr, [x19,#32] - 57d8: b900e3b4 str w20, [x29,#224] - 57dc: 72a20014 movk w20, #0x1000, lsl #16 - 57e0: 39104464 strb w4, [x3,#1041] - 57e4: 90000003 adrp x3, 5000 <__getpagesize@plt> - 57e8: 91145063 add x3, x3, #0x514 - 57ec: f9002fa3 str x3, [x29,#88] - 57f0: a9007e7f stp xzr, xzr, [x19] - 57f4: a9037e7f stp xzr, xzr, [x19,#48] - 57f8: a9047e7f stp xzr, xzr, [x19,#64] - 57fc: a9057e7f stp xzr, xzr, [x19,#80] - 5800: a9067e7f stp xzr, xzr, [x19,#96] - 5804: a9077e7f stp xzr, xzr, [x19,#112] - 5808: 94002eb1 bl 112cc <__libc_sigaction> - 580c: b900e3b4 str w20, [x29,#224] - 5810: 90000003 adrp x3, 5000 <__getpagesize@plt> - 5814: aa1503e1 mov x1, x21 - 5818: 9117d063 add x3, x3, #0x5f4 - 581c: d2800002 mov x2, #0x0 // #0 - 5820: 52800420 mov w0, #0x21 // #33 - 5824: f9002fa3 str x3, [x29,#88] - 5828: 94002ea9 bl 112cc <__libc_sigaction> - 582c: f94033a3 ldr x3, [x29,#96] - 5830: d2800020 mov x0, #0x1 // #1 - 5834: aa1303e1 mov x1, x19 - 5838: d2800002 mov x2, #0x0 // #0 - 583c: b2610464 orr x4, x3, #0x180000000 - 5840: d28010e8 mov x8, #0x87 // #135 - 5844: d2800103 mov x3, #0x8 // #8 - 5848: f90033a4 str x4, [x29,#96] - 584c: d4000001 svc #0x0 - 5850: f0000173 adrp x19, 34000 <__GI___pthread_keys+0x3d78> - 5854: 910103a1 add x1, x29, #0x40 - 5858: 910c8260 add x0, x19, #0x320 - 585c: 97fffeb9 bl 5340 <_dl_get_tls_static_info@plt> - 5860: f94023a4 ldr x4, [x29,#64] - 5864: f1003c9f cmp x4, #0xf - 5868: 54000e68 b.hi 5a34 <__pthread_initialize_minimal+0x324> - 586c: f0000160 adrp x0, 34000 <__GI___pthread_keys+0x3d78> - 5870: d2800202 mov x2, #0x10 // #16 - 5874: d28001e1 mov x1, #0xf // #15 - 5878: f90023a2 str x2, [x29,#64] - 587c: aa0203e4 mov x4, x2 - 5880: f9018c01 str x1, [x0,#792] - 5884: f9419262 ldr x2, [x19,#800] - 5888: 52800060 mov w0, #0x3 // #3 - 588c: 910123a1 add x1, x29, #0x48 - 5890: d1000443 sub x3, x2, #0x1 - 5894: 8b040063 add x3, x3, x4 - 5898: 9ac40863 udiv x3, x3, x4 - 589c: 9b047c62 mul x2, x3, x4 - 58a0: f9019262 str x2, [x19,#800] - 58a4: 97fffdc3 bl 4fb0 <__getrlimit@plt> - 58a8: 34000b60 cbz w0, 5a14 <__pthread_initialize_minimal+0x304> - 58ac: d2a00403 mov x3, #0x200000 // #2097152 - 58b0: d0000141 adrp x1, 2f000 <__FRAME_END__+0x18e30> - 58b4: f9419262 ldr x2, [x19,#800] - 58b8: f0000173 adrp x19, 34000 <__GI___pthread_keys+0x3d78> - 58bc: b9003fbf str wzr, [x29,#60] - 58c0: 910a2260 add x0, x19, #0x288 - 58c4: f947d421 ldr x1, [x1,#4008] - 58c8: f9400c34 ldr x20, [x1,#24] - 58cc: 8b020282 add x2, x20, x2 - 58d0: d1000684 sub x4, x20, #0x1 - 58d4: 91200041 add x1, x2, #0x800 - 58d8: cb1403e2 neg x2, x20 - 58dc: eb03003f cmp x1, x3 - 58e0: 9a832021 csel x1, x1, x3, cs - 58e4: 8b040021 add x1, x1, x4 - 58e8: 8a020021 and x1, x1, x2 - 58ec: f90027a1 str x1, [x29,#72] - 58f0: 52800021 mov w1, #0x1 // #1 - 58f4: 885ffc02 ldaxr w2, [x0] - 58f8: 6b1f005f cmp w2, wzr - 58fc: 54000061 b.ne 5908 <__pthread_initialize_minimal+0x1f8> - 5900: 88037c01 stxr w3, w1, [x0] - 5904: 35ffff83 cbnz w3, 58f4 <__pthread_initialize_minimal+0x1e4> - 5908: 54000801 b.ne 5a08 <__pthread_initialize_minimal+0x2f8> - 590c: f0000161 adrp x1, 34000 <__GI___pthread_keys+0x3d78> - 5910: f94027a2 ldr x2, [x29,#72] - 5914: 910cc021 add x1, x1, #0x330 - 5918: 910a2260 add x0, x19, #0x288 - 591c: f9001022 str x2, [x1,#32] - 5920: 52800002 mov w2, #0x0 // #0 - 5924: f9000834 str x20, [x1,#16] - 5928: 885f7c01 ldxr w1, [x0] - 592c: 8803fc02 stlxr w3, w2, [x0] - 5930: 35ffffc3 cbnz w3, 5928 <__pthread_initialize_minimal+0x218> - 5934: 7100043f cmp w1, #0x1 - 5938: 5400086c b.gt 5a44 <__pthread_initialize_minimal+0x334> - 593c: d0000154 adrp x20, 2f000 <__FRAME_END__+0x18e30> - 5940: 97fffe68 bl 52e0 <__libc_dl_error_tsd@plt> - 5944: aa0003f3 mov x19, x0 - 5948: f947ee95 ldr x21, [x20,#4056] - 594c: f9450ea0 ldr x0, [x21,#2584] - 5950: d63f0000 blr x0 - 5954: f9400000 ldr x0, [x0] - 5958: f9000260 str x0, [x19] - 595c: d0000140 adrp x0, 2f000 <__FRAME_END__+0x18e30> - 5960: b9498eb3 ldr w19, [x21,#2444] - 5964: f947dc00 ldr x0, [x0,#4024] - 5968: f9050ea0 str x0, [x21,#2584] - 596c: 90000020 adrp x0, 9000 <__pthread_mutex_lock_full+0x1a0> - 5970: 910f6000 add x0, x0, #0x3d8 - 5974: f907c6a0 str x0, [x21,#3976] - 5978: b0000020 adrp x0, a000 - 597c: b9098ebf str wzr, [x21,#2444] - 5980: 91296000 add x0, x0, #0xa58 - 5984: f907caa0 str x0, [x21,#3984] - 5988: 340000d3 cbz w19, 59a0 <__pthread_initialize_minimal+0x290> - 598c: f947ee80 ldr x0, [x20,#4056] - 5990: 91262000 add x0, x0, #0x988 - 5994: 94000e91 bl 93d8 <__pthread_mutex_lock> - 5998: 71000673 subs w19, w19, #0x1 - 599c: 54ffff81 b.ne 598c <__pthread_initialize_minimal+0x27c> - 59a0: f947ee94 ldr x20, [x20,#4056] - 59a4: b0000003 adrp x3, 6000 - 59a8: 91014063 add x3, x3, #0x50 - 59ac: f0000160 adrp x0, 34000 <__GI___pthread_keys+0x3d78> - 59b0: b0000001 adrp x1, 6000 - 59b4: d0000142 adrp x2, 2f000 <__FRAME_END__+0x18e30> - 59b8: f907ce83 str x3, [x20,#3992] - 59bc: b0000003 adrp x3, 6000 - 59c0: 91224063 add x3, x3, #0x890 - 59c4: f907f683 str x3, [x20,#4072] - 59c8: b0000003 adrp x3, 6000 - 59cc: 9106e021 add x1, x1, #0x1b8 - 59d0: 91285063 add x3, x3, #0xa14 - 59d4: 912e2042 add x2, x2, #0xb88 - 59d8: 910e2000 add x0, x0, #0x388 - 59dc: f907fa83 str x3, [x20,#4080] - 59e0: 97fffe08 bl 5200 <__libc_pthread_init@plt> - 59e4: f94013f5 ldr x21, [sp,#32] - 59e8: f0000161 adrp x1, 34000 <__GI___pthread_keys+0x3d78> - 59ec: a94153f3 ldp x19, x20, [sp,#16] - 59f0: a8cf7bfd ldp x29, x30, [sp],#240 - 59f4: f901b820 str x0, [x1,#880] - 59f8: f0000160 adrp x0, 34000 <__GI___pthread_keys+0x3d78> - 59fc: 52800021 mov w1, #0x1 // #1 - 5a00: b9032c01 str w1, [x0,#812] - 5a04: d65f03c0 ret - 5a08: b9003fa2 str w2, [x29,#60] - 5a0c: 94002757 bl f768 <__lll_lock_wait_private> - 5a10: 17ffffbf b 590c <__pthread_initialize_minimal+0x1fc> - 5a14: f94027a3 ldr x3, [x29,#72] - 5a18: b100047f cmn x3, #0x1 - 5a1c: 54fff480 b.eq 58ac <__pthread_initialize_minimal+0x19c> - 5a20: b24043e0 mov x0, #0x1ffff // #131071 - 5a24: eb00007f cmp x3, x0 - 5a28: d2a00040 mov x0, #0x20000 // #131072 - 5a2c: 9a808063 csel x3, x3, x0, hi - 5a30: 17ffffa0 b 58b0 <__pthread_initialize_minimal+0x1a0> - 5a34: f0000161 adrp x1, 34000 <__GI___pthread_keys+0x3d78> - 5a38: d1000480 sub x0, x4, #0x1 - 5a3c: f9018c20 str x0, [x1,#792] - 5a40: 17ffff91 b 5884 <__pthread_initialize_minimal+0x174> - 5a44: d2801021 mov x1, #0x81 // #129 - 5a48: d2800022 mov x2, #0x1 // #1 - 5a4c: d2800003 mov x3, #0x0 // #0 - 5a50: d2800c48 mov x8, #0x62 // #98 - 5a54: d4000001 svc #0x0 - 5a58: 17ffffb9 b 593c <__pthread_initialize_minimal+0x22c> - -0000000000005a5c <__pthread_get_minstack>: - 5a5c: d0000142 adrp x2, 2f000 <__FRAME_END__+0x18e30> - 5a60: f9400803 ldr x3, [x0,#16] - 5a64: f0000160 adrp x0, 34000 <__GI___pthread_keys+0x3d78> - 5a68: f947d442 ldr x2, [x2,#4008] - 5a6c: f9419001 ldr x1, [x0,#800] - 5a70: f9400c40 ldr x0, [x2,#24] - 5a74: 8b010000 add x0, x0, x1 - 5a78: 91408000 add x0, x0, #0x20, lsl #12 - 5a7c: 8b030000 add x0, x0, x3 - 5a80: d65f03c0 ret - -0000000000005a84 <__GI___nptl_create_event>: - 5a84: d65f03c0 ret - -0000000000005a88 <__GI___nptl_death_event>: - 5a88: d65f03c0 ret - -0000000000005a8c <__nptl_main>: - 5a8c: a9bf7bfd stp x29, x30, [sp,#-16]! - 5a90: b0000061 adrp x1, 12000 <__pthread_current_priority+0xa8> - 5a94: d2800020 mov x0, #0x1 // #1 - 5a98: 910003fd mov x29, sp - 5a9c: 9121c021 add x1, x1, #0x870 - 5aa0: d28023a2 mov x2, #0x11d // #285 - 5aa4: d2800808 mov x8, #0x40 // #64 - 5aa8: d4000001 svc #0x0 - 5aac: 52800000 mov w0, #0x0 // #0 - 5ab0: 97fffd30 bl 4f70 <_exit@plt> - -0000000000005ab4 : - 5ab4: aa0003e4 mov x4, x0 - 5ab8: b9441c00 ldr w0, [x0,#1052] - 5abc: d10043ff sub sp, sp, #0x10 - 5ac0: 3100041f cmn w0, #0x1 - 5ac4: 54000420 b.eq 5b48 - 5ac8: b9410881 ldr w1, [x4,#264] - 5acc: 91042082 add x2, x4, #0x108 - 5ad0: b9041c9f str wzr, [x4,#1052] - 5ad4: 321a0023 orr w3, w1, #0x40 - 5ad8: 2a0103e0 mov w0, w1 - 5adc: 37200201 tbnz w1, #4, 5b1c - 5ae0: b9000fe1 str w1, [sp,#12] - 5ae4: 885ffc41 ldaxr w1, [x2] - 5ae8: 6b00003f cmp w1, w0 - 5aec: 54000061 b.ne 5af8 - 5af0: 88057c43 stxr w5, w3, [x2] - 5af4: 35ffff85 cbnz w5, 5ae4 - 5af8: 54000061 b.ne 5b04 - 5afc: 910043ff add sp, sp, #0x10 - 5b00: d65f03c0 ret - 5b04: b9000fe1 str w1, [sp,#12] - 5b08: 91042082 add x2, x4, #0x108 - 5b0c: b9410881 ldr w1, [x4,#264] - 5b10: 321a0023 orr w3, w1, #0x40 - 5b14: 2a0103e0 mov w0, w1 - 5b18: 3627fe41 tbz w1, #4, 5ae0 - 5b1c: 3737ff01 tbnz w1, #6, 5afc - 5b20: 52800021 mov w1, #0x1 // #1 - 5b24: 91107080 add x0, x4, #0x41c - 5b28: b9041c81 str w1, [x4,#1052] - 5b2c: d2800022 mov x2, #0x1 // #1 - 5b30: d2801021 mov x1, #0x81 // #129 - 5b34: d2800003 mov x3, #0x0 // #0 - 5b38: d2800c48 mov x8, #0x62 // #98 - 5b3c: d4000001 svc #0x0 - 5b40: 910043ff add sp, sp, #0x10 - 5b44: d65f03c0 ret - 5b48: b9000fe0 str w0, [sp,#12] - 5b4c: 91107085 add x5, x4, #0x41c - 5b50: 12800020 mov w0, #0xfffffffe // #-2 - 5b54: 12800002 mov w2, #0xffffffff // #-1 - 5b58: 885ffca1 ldaxr w1, [x5] - 5b5c: 6b02003f cmp w1, w2 - 5b60: 54000061 b.ne 5b6c - 5b64: 88037ca0 stxr w3, w0, [x5] - 5b68: 35ffff83 cbnz w3, 5b58 - 5b6c: 54000161 b.ne 5b98 - 5b70: aa0503e0 mov x0, x5 - 5b74: d2801001 mov x1, #0x80 // #128 - 5b78: 92800022 mov x2, #0xfffffffffffffffe // #-2 - 5b7c: d2800003 mov x3, #0x0 // #0 - 5b80: d2800c48 mov x8, #0x62 // #98 - 5b84: d4000001 svc #0x0 - 5b88: b9441c80 ldr w0, [x4,#1052] - 5b8c: 3100081f cmn w0, #0x2 - 5b90: 54ffff00 b.eq 5b70 - 5b94: 17ffffcd b 5ac8 - 5b98: b9000fe1 str w1, [sp,#12] - 5b9c: 17ffffcb b 5ac8 - -0000000000005ba0 <__free_stacks>: - 5ba0: a9bc7bfd stp x29, x30, [sp,#-64]! - 5ba4: 910003fd mov x29, sp - 5ba8: a9025bf5 stp x21, x22, [sp,#32] - 5bac: f0000155 adrp x21, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 5bb0: 910962b5 add x21, x21, #0x258 - 5bb4: a90363f7 stp x23, x24, [sp,#48] - 5bb8: a90153f3 stp x19, x20, [sp,#16] - 5bbc: f94006a2 ldr x2, [x21,#8] - 5bc0: aa0003f8 mov x24, x0 - 5bc4: f0000177 adrp x23, 34000 <__GI___pthread_keys+0x3d78> - 5bc8: eb15005f cmp x2, x21 - 5bcc: f9400453 ldr x19, [x2,#8] - 5bd0: 540000e1 b.ne 5bec <__free_stacks+0x4c> - 5bd4: 14000022 b 5c5c <__free_stacks+0xbc> - 5bd8: eb15027f cmp x19, x21 - 5bdc: f9400661 ldr x1, [x19,#8] - 5be0: aa1303e2 mov x2, x19 - 5be4: 540003c0 b.eq 5c5c <__free_stacks+0xbc> - 5be8: aa0103f3 mov x19, x1 - 5bec: d1030054 sub x20, x2, #0xc0 - 5bf0: b940d281 ldr w1, [x20,#208] - 5bf4: 6b1f003f cmp w1, wzr - 5bf8: 54ffff0c b.gt 5bd8 <__free_stacks+0x38> - 5bfc: f9014ae2 str x2, [x23,#656] - 5c00: 9118c040 add x0, x2, #0x630 - 5c04: 910a42f6 add x22, x23, #0x290 - 5c08: 52800001 mov w1, #0x0 // #0 - 5c0c: d5033bbf dmb ish - 5c10: f9400043 ldr x3, [x2] - 5c14: f9400444 ldr x4, [x2,#8] - 5c18: f9000464 str x4, [x3,#8] - 5c1c: f9400442 ldr x2, [x2,#8] - 5c20: f9000043 str x3, [x2] - 5c24: d5033bbf dmb ish - 5c28: f94006c2 ldr x2, [x22,#8] - 5c2c: f9424e83 ldr x3, [x20,#1176] - 5c30: f9014aff str xzr, [x23,#656] - 5c34: cb030042 sub x2, x2, x3 - 5c38: f90006c2 str x2, [x22,#8] - 5c3c: 97fffd29 bl 50e0 <_dl_deallocate_tls@plt> - 5c40: f9424a80 ldr x0, [x20,#1168] - 5c44: f9424e81 ldr x1, [x20,#1176] - 5c48: 97fffd9a bl 52b0 - 5c4c: 35000120 cbnz w0, 5c70 <__free_stacks+0xd0> - 5c50: f94006c1 ldr x1, [x22,#8] - 5c54: eb18003f cmp x1, x24 - 5c58: 54fffc08 b.hi 5bd8 <__free_stacks+0x38> - 5c5c: a94153f3 ldp x19, x20, [sp,#16] - 5c60: a9425bf5 ldp x21, x22, [sp,#32] - 5c64: a94363f7 ldp x23, x24, [sp,#48] - 5c68: a8c47bfd ldp x29, x30, [sp],#64 - 5c6c: d65f03c0 ret - 5c70: 97fffd40 bl 5170 - -0000000000005c74 <__deallocate_stack>: - 5c74: a9bb7bfd stp x29, x30, [sp,#-80]! - 5c78: 910003fd mov x29, sp - 5c7c: a90153f3 stp x19, x20, [sp,#16] - 5c80: f0000173 adrp x19, 34000 <__GI___pthread_keys+0x3d78> - 5c84: aa0003f4 mov x20, x0 - 5c88: 910a4261 add x1, x19, #0x290 - 5c8c: b9004fbf str wzr, [x29,#76] - 5c90: 91004020 add x0, x1, #0x10 - 5c94: 52800021 mov w1, #0x1 // #1 - 5c98: a9025bf5 stp x21, x22, [sp,#32] - 5c9c: a90363f7 stp x23, x24, [sp,#48] - 5ca0: 885ffc02 ldaxr w2, [x0] - 5ca4: 6b1f005f cmp w2, wzr - 5ca8: 54000061 b.ne 5cb4 <__deallocate_stack+0x40> - 5cac: 88037c01 stxr w3, w1, [x0] - 5cb0: 35ffff83 cbnz w3, 5ca0 <__deallocate_stack+0x2c> - 5cb4: 54000601 b.ne 5d74 <__deallocate_stack+0x100> - 5cb8: 91030280 add x0, x20, #0xc0 - 5cbc: f9014a60 str x0, [x19,#656] - 5cc0: f0000163 adrp x3, 34000 <__GI___pthread_keys+0x3d78> - 5cc4: 910a4262 add x2, x19, #0x290 - 5cc8: d5033bbf dmb ish - 5ccc: f9406281 ldr x1, [x20,#192] - 5cd0: f9406684 ldr x4, [x20,#200] - 5cd4: f9000424 str x4, [x1,#8] - 5cd8: f9406684 ldr x4, [x20,#200] - 5cdc: f9000081 str x1, [x4] - 5ce0: d5033bbf dmb ish - 5ce4: 39504a81 ldrb w1, [x20,#1042] - 5ce8: f9014a7f str xzr, [x19,#656] - 5cec: 350004a1 cbnz w1, 5d80 <__deallocate_stack+0x10c> - 5cf0: f0000141 adrp x1, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 5cf4: b2400004 orr x4, x0, #0x1 - 5cf8: f9014864 str x4, [x3,#656] - 5cfc: 91096036 add x22, x1, #0x258 - 5d00: d2a05005 mov x5, #0x2800000 // #41943040 - 5d04: d5033bbf dmb ish - 5d08: f9412c24 ldr x4, [x1,#600] - 5d0c: f9006284 str x4, [x20,#192] - 5d10: f9006696 str x22, [x20,#200] - 5d14: f9000480 str x0, [x4,#8] - 5d18: d5033bbf dmb ish - 5d1c: f9012c20 str x0, [x1,#600] - 5d20: d5033bbf dmb ish - 5d24: f9400441 ldr x1, [x2,#8] - 5d28: f9424e80 ldr x0, [x20,#1176] - 5d2c: f901487f str xzr, [x3,#656] - 5d30: 8b000020 add x0, x1, x0 - 5d34: f9000440 str x0, [x2,#8] - 5d38: eb05001f cmp x0, x5 - 5d3c: 540003e8 b.hi 5db8 <__deallocate_stack+0x144> - 5d40: 910a4260 add x0, x19, #0x290 - 5d44: 52800002 mov w2, #0x0 // #0 - 5d48: 91004000 add x0, x0, #0x10 - 5d4c: 885f7c01 ldxr w1, [x0] - 5d50: 8803fc02 stlxr w3, w2, [x0] - 5d54: 35ffffc3 cbnz w3, 5d4c <__deallocate_stack+0xd8> - 5d58: 7100043f cmp w1, #0x1 - 5d5c: 540001ac b.gt 5d90 <__deallocate_stack+0x11c> - 5d60: a94153f3 ldp x19, x20, [sp,#16] - 5d64: a9425bf5 ldp x21, x22, [sp,#32] - 5d68: a94363f7 ldp x23, x24, [sp,#48] - 5d6c: a8c57bfd ldp x29, x30, [sp],#80 - 5d70: d65f03c0 ret - 5d74: b9004fa2 str w2, [x29,#76] - 5d78: 9400267c bl f768 <__lll_lock_wait_private> - 5d7c: 17ffffcf b 5cb8 <__deallocate_stack+0x44> - 5d80: 911bc280 add x0, x20, #0x6f0 - 5d84: 52800001 mov w1, #0x0 // #0 - 5d88: 97fffcd6 bl 50e0 <_dl_deallocate_tls@plt> - 5d8c: 17ffffed b 5d40 <__deallocate_stack+0xcc> - 5d90: d2801021 mov x1, #0x81 // #129 - 5d94: d2800022 mov x2, #0x1 // #1 - 5d98: d2800003 mov x3, #0x0 // #0 - 5d9c: d2800c48 mov x8, #0x62 // #98 - 5da0: d4000001 svc #0x0 - 5da4: a94153f3 ldp x19, x20, [sp,#16] - 5da8: a9425bf5 ldp x21, x22, [sp,#32] - 5dac: a94363f7 ldp x23, x24, [sp,#48] - 5db0: a8c57bfd ldp x29, x30, [sp],#80 - 5db4: d65f03c0 ret - 5db8: f94006c2 ldr x2, [x22,#8] - 5dbc: eb16005f cmp x2, x22 - 5dc0: f9400454 ldr x20, [x2,#8] - 5dc4: 54fffbe0 b.eq 5d40 <__deallocate_stack+0xcc> - 5dc8: aa0503f7 mov x23, x5 - 5dcc: 14000006 b 5de4 <__deallocate_stack+0x170> - 5dd0: eb16029f cmp x20, x22 - 5dd4: f9400680 ldr x0, [x20,#8] - 5dd8: aa1403e2 mov x2, x20 - 5ddc: 54fffb20 b.eq 5d40 <__deallocate_stack+0xcc> - 5de0: aa0003f4 mov x20, x0 - 5de4: d1030055 sub x21, x2, #0xc0 - 5de8: b940d2a0 ldr w0, [x21,#208] - 5dec: 6b1f001f cmp w0, wzr - 5df0: 54ffff0c b.gt 5dd0 <__deallocate_stack+0x15c> - 5df4: f9014a62 str x2, [x19,#656] - 5df8: 9118c040 add x0, x2, #0x630 - 5dfc: 910a4278 add x24, x19, #0x290 - 5e00: 52800001 mov w1, #0x0 // #0 - 5e04: d5033bbf dmb ish - 5e08: f9400043 ldr x3, [x2] - 5e0c: f9400444 ldr x4, [x2,#8] - 5e10: f9000464 str x4, [x3,#8] - 5e14: f9400442 ldr x2, [x2,#8] - 5e18: f9000043 str x3, [x2] - 5e1c: d5033bbf dmb ish - 5e20: f9400702 ldr x2, [x24,#8] - 5e24: f9424ea3 ldr x3, [x21,#1176] - 5e28: f9014a7f str xzr, [x19,#656] - 5e2c: cb030042 sub x2, x2, x3 - 5e30: f9000702 str x2, [x24,#8] - 5e34: 97fffcab bl 50e0 <_dl_deallocate_tls@plt> - 5e38: f9424aa0 ldr x0, [x21,#1168] - 5e3c: f9424ea1 ldr x1, [x21,#1176] - 5e40: 97fffd1c bl 52b0 - 5e44: 350000a0 cbnz w0, 5e58 <__deallocate_stack+0x1e4> - 5e48: f9400700 ldr x0, [x24,#8] - 5e4c: eb17001f cmp x0, x23 - 5e50: 54fffc08 b.hi 5dd0 <__deallocate_stack+0x15c> - 5e54: 17ffffbb b 5d40 <__deallocate_stack+0xcc> - 5e58: 97fffcc6 bl 5170 - -0000000000005e5c : - 5e5c: a9bb7bfd stp x29, x30, [sp,#-80]! - 5e60: 911bc005 add x5, x0, #0x6f0 - 5e64: 910003fd mov x29, sp - 5e68: a90153f3 stp x19, x20, [sp,#16] - 5e6c: f90013f6 str x22, [sp,#32] - 5e70: f0000154 adrp x20, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 5e74: aa0003f3 mov x19, x0 - 5e78: aa0103f6 mov x22, x1 - 5e7c: 91094280 add x0, x20, #0x250 - 5e80: aa0203e1 mov x1, x2 - 5e84: 35000303 cbnz w3, 5ee4 - 5e88: 885ffc02 ldaxr w2, [x0] - 5e8c: 11000442 add w2, w2, #0x1 - 5e90: 88037c02 stxr w3, w2, [x0] - 5e94: 35ffffa3 cbnz w3, 5e88 - 5e98: 91034264 add x4, x19, #0xd0 - 5e9c: 5281e002 mov w2, #0xf00 // #3840 - 5ea0: b0000000 adrp x0, 6000 - 5ea4: 72a007a2 movk w2, #0x3d, lsl #16 - 5ea8: 913a3000 add x0, x0, #0xe8c - 5eac: aa1303e3 mov x3, x19 - 5eb0: aa0403e6 mov x6, x4 - 5eb4: 97fffd13 bl 5300 <__clone@plt> - 5eb8: 3100041f cmn w0, #0x1 - 5ebc: 540008c0 b.eq 5fd4 - 5ec0: d53bd041 mrs x1, tpidr_el0 - 5ec4: 52800022 mov w2, #0x1 // #1 - 5ec8: d11bc021 sub x1, x1, #0x6f0 - 5ecc: 52800000 mov w0, #0x0 // #0 - 5ed0: b9000022 str w2, [x1] - 5ed4: a94153f3 ldp x19, x20, [sp,#16] - 5ed8: f94013f6 ldr x22, [sp,#32] - 5edc: a8c57bfd ldp x29, x30, [sp],#80 - 5ee0: d65f03c0 ret - 5ee4: b9004fbf str wzr, [x29,#76] - 5ee8: 91106260 add x0, x19, #0x418 - 5eec: 52800023 mov w3, #0x1 // #1 - 5ef0: 885ffc02 ldaxr w2, [x0] - 5ef4: 6b1f005f cmp w2, wzr - 5ef8: 54000061 b.ne 5f04 - 5efc: 88047c03 stxr w4, w3, [x0] - 5f00: 35ffff84 cbnz w4, 5ef0 - 5f04: 540005a1 b.ne 5fb8 - 5f08: f0000154 adrp x20, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 5f0c: 91094280 add x0, x20, #0x250 - 5f10: 885ffc02 ldaxr w2, [x0] - 5f14: 11000442 add w2, w2, #0x1 - 5f18: 88037c02 stxr w3, w2, [x0] - 5f1c: 35ffffa3 cbnz w3, 5f10 - 5f20: 91034264 add x4, x19, #0xd0 - 5f24: 5281e002 mov w2, #0xf00 // #3840 - 5f28: b0000000 adrp x0, 6000 - 5f2c: 72a007a2 movk w2, #0x3d, lsl #16 - 5f30: 913a3000 add x0, x0, #0xe8c - 5f34: aa1303e3 mov x3, x19 - 5f38: aa0403e6 mov x6, x4 - 5f3c: 97fffcf1 bl 5300 <__clone@plt> - 5f40: 3100041f cmn w0, #0x1 - 5f44: 54000480 b.eq 5fd4 - 5f48: f94016c2 ldr x2, [x22,#40] - 5f4c: b40000e2 cbz x2, 5f68 - 5f50: b980d260 ldrsw x0, [x19,#208] - 5f54: d2800f48 mov x8, #0x7a // #122 - 5f58: f9401ac1 ldr x1, [x22,#48] - 5f5c: d4000001 svc #0x0 - 5f60: 3140041f cmn w0, #0x1, lsl #12 - 5f64: 54000148 b.hi 5f8c - 5f68: b9400ac0 ldr w0, [x22,#8] - 5f6c: 360ffaa0 tbz w0, #1, 5ec0 - 5f70: b980d260 ldrsw x0, [x19,#208] - 5f74: 9110c262 add x2, x19, #0x430 - 5f78: b9843661 ldrsw x1, [x19,#1076] - 5f7c: d2800ee8 mov x8, #0x77 // #119 - 5f80: d4000001 svc #0x0 - 5f84: 3140041f cmn w0, #0x1, lsl #12 - 5f88: 54fff9c9 b.ls 5ec0 - 5f8c: 2a0003e3 mov w3, w0 - 5f90: d53bd040 mrs x0, tpidr_el0 - 5f94: d11bc000 sub x0, x0, #0x6f0 - 5f98: b980d261 ldrsw x1, [x19,#208] - 5f9c: d2800402 mov x2, #0x20 // #32 - 5fa0: d2801068 mov x8, #0x83 // #131 - 5fa4: b980d400 ldrsw x0, [x0,#212] - 5fa8: d4000001 svc #0x0 - 5fac: 3140047f cmn w3, #0x1, lsl #12 - 5fb0: 5a8397e0 csneg w0, wzr, w3, ls - 5fb4: 17ffffc8 b 5ed4 - 5fb8: f9001ba1 str x1, [x29,#48] - 5fbc: f9001fa5 str x5, [x29,#56] - 5fc0: b9004fa2 str w2, [x29,#76] - 5fc4: 940025e9 bl f768 <__lll_lock_wait_private> - 5fc8: f9401fa5 ldr x5, [x29,#56] - 5fcc: f9401ba1 ldr x1, [x29,#48] - 5fd0: 17ffffce b 5f08 - 5fd4: 91094294 add x20, x20, #0x250 - 5fd8: 885ffe80 ldaxr w0, [x20] - 5fdc: 51000400 sub w0, w0, #0x1 - 5fe0: 88017e80 stxr w1, w0, [x20] - 5fe4: 35ffffa1 cbnz w1, 5fd8 - 5fe8: 91107260 add x0, x19, #0x41c - 5fec: 52800002 mov w2, #0x0 // #0 - 5ff0: 885ffc01 ldaxr w1, [x0] - 5ff4: 88037c02 stxr w3, w2, [x0] - 5ff8: 35ffffc3 cbnz w3, 5ff0 - 5ffc: 3100083f cmn w1, #0x2 - 6000: 540001c0 b.eq 6038 - 6004: aa1303e0 mov x0, x19 - 6008: 97ffff1b bl 5c74 <__deallocate_stack> - 600c: f94013f6 ldr x22, [sp,#32] - 6010: b0000141 adrp x1, 2f000 <__FRAME_END__+0x18e30> - 6014: f947c421 ldr x1, [x1,#3976] - 6018: d53bd040 mrs x0, tpidr_el0 - 601c: a94153f3 ldp x19, x20, [sp,#16] - 6020: a8c57bfd ldp x29, x30, [sp],#80 - 6024: b8616800 ldr w0, [x0,x1] - 6028: 52800161 mov w1, #0xb // #11 - 602c: 7100301f cmp w0, #0xc - 6030: 1a811000 csel w0, w0, w1, ne - 6034: d65f03c0 ret - 6038: d2801021 mov x1, #0x81 // #129 - 603c: d2800022 mov x2, #0x1 // #1 - 6040: d2800003 mov x3, #0x0 // #0 - 6044: d2800c48 mov x8, #0x62 // #98 - 6048: d4000001 svc #0x0 - 604c: 17ffffee b 6004 - -0000000000006050 <__make_stacks_executable>: - 6050: a9bb7bfd stp x29, x30, [sp,#-80]! - 6054: 910003fd mov x29, sp - 6058: a9025bf5 stp x21, x22, [sp,#32] - 605c: a90153f3 stp x19, x20, [sp,#16] - 6060: a90363f7 stp x23, x24, [sp,#48] - 6064: 97fffc5f bl 51e0 <_dl_make_stack_executable@plt> - 6068: 2a0003f6 mov w22, w0 - 606c: 340000e0 cbz w0, 6088 <__make_stacks_executable+0x38> - 6070: 2a1603e0 mov w0, w22 - 6074: a94153f3 ldp x19, x20, [sp,#16] - 6078: a9425bf5 ldp x21, x22, [sp,#32] - 607c: a94363f7 ldp x23, x24, [sp,#48] - 6080: a8c57bfd ldp x29, x30, [sp],#80 - 6084: d65f03c0 ret - 6088: d0000177 adrp x23, 34000 <__GI___pthread_keys+0x3d78> - 608c: b9004fa0 str w0, [x29,#76] - 6090: 910a42e0 add x0, x23, #0x290 - 6094: 52800021 mov w1, #0x1 // #1 - 6098: 91004000 add x0, x0, #0x10 - 609c: 885ffc02 ldaxr w2, [x0] - 60a0: 6b1f005f cmp w2, wzr - 60a4: 54000061 b.ne 60b0 <__make_stacks_executable+0x60> - 60a8: 88037c01 stxr w3, w1, [x0] - 60ac: 35ffff83 cbnz w3, 609c <__make_stacks_executable+0x4c> - 60b0: 540004e1 b.ne 614c <__make_stacks_executable+0xfc> - 60b4: d0000158 adrp x24, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 60b8: 91096314 add x20, x24, #0x258 - 60bc: f8410e93 ldr x19, [x20,#16]! - 60c0: eb14027f cmp x19, x20 - 60c4: 540004a0 b.eq 6158 <__make_stacks_executable+0x108> - 60c8: b0000155 adrp x21, 2f000 <__FRAME_END__+0x18e30> - 60cc: f947c6b5 ldr x21, [x21,#3976] - 60d0: d53bd040 mrs x0, tpidr_el0 - 60d4: 8b150015 add x21, x0, x21 - 60d8: 14000004 b 60e8 <__make_stacks_executable+0x98> - 60dc: f9400273 ldr x19, [x19] - 60e0: eb14027f cmp x19, x20 - 60e4: 540003a0 b.eq 6158 <__make_stacks_executable+0x108> - 60e8: f941f261 ldr x1, [x19,#992] - 60ec: 528000e2 mov w2, #0x7 // #7 - 60f0: f941ea60 ldr x0, [x19,#976] - 60f4: f941ee63 ldr x3, [x19,#984] - 60f8: 8b010000 add x0, x0, x1 - 60fc: cb010061 sub x1, x3, x1 - 6100: 97fffcac bl 53b0 - 6104: 34fffec0 cbz w0, 60dc <__make_stacks_executable+0x8c> - 6108: b94002a1 ldr w1, [x21] - 610c: 34fffe81 cbz w1, 60dc <__make_stacks_executable+0x8c> - 6110: 2a0103f6 mov w22, w1 - 6114: 910a42e0 add x0, x23, #0x290 - 6118: 52800002 mov w2, #0x0 // #0 - 611c: 91004000 add x0, x0, #0x10 - 6120: 885f7c01 ldxr w1, [x0] - 6124: 8803fc02 stlxr w3, w2, [x0] - 6128: 35ffffc3 cbnz w3, 6120 <__make_stacks_executable+0xd0> - 612c: 7100043f cmp w1, #0x1 - 6130: 54fffa0d b.le 6070 <__make_stacks_executable+0x20> - 6134: d2801021 mov x1, #0x81 // #129 - 6138: d2800022 mov x2, #0x1 // #1 - 613c: d2800003 mov x3, #0x0 // #0 - 6140: d2800c48 mov x8, #0x62 // #98 - 6144: d4000001 svc #0x0 - 6148: 17ffffca b 6070 <__make_stacks_executable+0x20> - 614c: b9004fa2 str w2, [x29,#76] - 6150: 94002586 bl f768 <__lll_lock_wait_private> - 6154: 17ffffd8 b 60b4 <__make_stacks_executable+0x64> - 6158: f9412f13 ldr x19, [x24,#600] - 615c: 91096314 add x20, x24, #0x258 - 6160: eb14027f cmp x19, x20 - 6164: 54fffd80 b.eq 6114 <__make_stacks_executable+0xc4> - 6168: b0000155 adrp x21, 2f000 <__FRAME_END__+0x18e30> - 616c: f947c6b5 ldr x21, [x21,#3976] - 6170: d53bd040 mrs x0, tpidr_el0 - 6174: 8b150015 add x21, x0, x21 - 6178: 14000004 b 6188 <__make_stacks_executable+0x138> - 617c: f9400273 ldr x19, [x19] - 6180: eb14027f cmp x19, x20 - 6184: 54fffc80 b.eq 6114 <__make_stacks_executable+0xc4> - 6188: f941f261 ldr x1, [x19,#992] - 618c: 528000e2 mov w2, #0x7 // #7 - 6190: f941ea60 ldr x0, [x19,#976] - 6194: f941ee63 ldr x3, [x19,#984] - 6198: 8b010000 add x0, x0, x1 - 619c: cb010061 sub x1, x3, x1 - 61a0: 97fffc84 bl 53b0 - 61a4: 34fffec0 cbz w0, 617c <__make_stacks_executable+0x12c> - 61a8: b94002a0 ldr w0, [x21] - 61ac: 34fffe80 cbz w0, 617c <__make_stacks_executable+0x12c> - 61b0: 2a0003f6 mov w22, w0 - 61b4: 17ffffd8 b 6114 <__make_stacks_executable+0xc4> - -00000000000061b8 <__reclaim_stacks>: - 61b8: a9b97bfd stp x29, x30, [sp,#-112]! - 61bc: d53bd040 mrs x0, tpidr_el0 - 61c0: 910003fd mov x29, sp - 61c4: a9046bf9 stp x25, x26, [sp,#64] - 61c8: d0000179 adrp x25, 34000 <__GI___pthread_keys+0x3d78> - 61cc: a90363f7 stp x23, x24, [sp,#48] - 61d0: fd0033e8 str d8, [sp,#96] - 61d4: d11bc018 sub x24, x0, #0x6f0 - 61d8: 9e670008 fmov d8, x0 - 61dc: f9414b20 ldr x0, [x25,#656] - 61e0: a90153f3 stp x19, x20, [sp,#16] - 61e4: a9025bf5 stp x21, x22, [sp,#32] - 61e8: a90573fb stp x27, x28, [sp,#80] - 61ec: b5000e20 cbnz x0, 63b0 <__reclaim_stacks+0x1f8> - 61f0: d000015a adrp x26, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 61f4: 91096340 add x0, x26, #0x258 - 61f8: f9400817 ldr x23, [x0,#16] - 61fc: 91096340 add x0, x26, #0x258 - 6200: 9100401c add x28, x0, #0x10 - 6204: eb1c02ff cmp x23, x28 - 6208: 54001120 b.eq 642c <__reclaim_stacks+0x274> - 620c: 52800036 mov w22, #0x1 // #1 - 6210: aa0003fb mov x27, x0 - 6214: 14000004 b 6224 <__reclaim_stacks+0x6c> - 6218: f94002f7 ldr x23, [x23] - 621c: eb1c02ff cmp x23, x28 - 6220: 54000440 b.eq 62a8 <__reclaim_stacks+0xf0> - 6224: d10302f4 sub x20, x23, #0xc0 - 6228: eb14031f cmp x24, x20 - 622c: 54ffff60 b.eq 6218 <__reclaim_stacks+0x60> - 6230: 910a4321 add x1, x25, #0x290 - 6234: f9424e80 ldr x0, [x20,#1176] - 6238: b940d703 ldr w3, [x24,#212] - 623c: 39504282 ldrb w2, [x20,#1040] - 6240: f9400424 ldr x4, [x1,#8] - 6244: b900d29f str wzr, [x20,#208] - 6248: 8b000080 add x0, x4, x0 - 624c: b900d683 str w3, [x20,#212] - 6250: f9000420 str x0, [x1,#8] - 6254: 34fffe22 cbz w2, 6218 <__reclaim_stacks+0x60> - 6258: 910142e0 add x0, x23, #0x50 - 625c: 52800001 mov w1, #0x0 // #0 - 6260: d2804002 mov x2, #0x200 // #512 - 6264: 910962f3 add x19, x23, #0x258 - 6268: 910d42f5 add x21, x23, #0x350 - 626c: 97fffb89 bl 5090 - 6270: 3910429f strb wzr, [x20,#1040] - 6274: f9400263 ldr x3, [x19] - 6278: 52800001 mov w1, #0x0 // #0 - 627c: d2804002 mov x2, #0x200 // #512 - 6280: 91002273 add x19, x19, #0x8 - 6284: aa0303e0 mov x0, x3 - 6288: b4000063 cbz x3, 6294 <__reclaim_stacks+0xdc> - 628c: 97fffb81 bl 5090 - 6290: 39104296 strb w22, [x20,#1040] - 6294: eb15027f cmp x19, x21 - 6298: 54fffee1 b.ne 6274 <__reclaim_stacks+0xbc> - 629c: f94002f7 ldr x23, [x23] - 62a0: eb1c02ff cmp x23, x28 - 62a4: 54fffc01 b.ne 6224 <__reclaim_stacks+0x6c> - 62a8: f9400363 ldr x3, [x27] - 62ac: f9400b77 ldr x23, [x27,#16] - 62b0: eb1b007f cmp x3, x27 - 62b4: 54000100 b.eq 62d4 <__reclaim_stacks+0x11c> - 62b8: aa0303e0 mov x0, x3 - 62bc: 91096342 add x2, x26, #0x258 - 62c0: b940d701 ldr w1, [x24,#212] - 62c4: b9001401 str w1, [x0,#20] - 62c8: f9400000 ldr x0, [x0] - 62cc: eb02001f cmp x0, x2 - 62d0: 54ffff81 b.ne 62c0 <__reclaim_stacks+0x108> - 62d4: 91096340 add x0, x26, #0x258 - 62d8: 91004001 add x1, x0, #0x10 - 62dc: eb0102ff cmp x23, x1 - 62e0: 54000100 b.eq 6300 <__reclaim_stacks+0x148> - 62e4: f90006e0 str x0, [x23,#8] - 62e8: f9400c01 ldr x1, [x0,#24] - 62ec: f9000023 str x3, [x1] - 62f0: f9412f42 ldr x2, [x26,#600] - 62f4: f9400800 ldr x0, [x0,#16] - 62f8: f9012f40 str x0, [x26,#600] - 62fc: f9000441 str x1, [x2,#8] - 6300: 9e660100 fmov x0, d8 - 6304: 91030302 add x2, x24, #0xc0 - 6308: f9014b22 str x2, [x25,#656] - 630c: 910a4323 add x3, x25, #0x290 - 6310: 9109635a add x26, x26, #0x258 - 6314: 91006061 add x1, x3, #0x18 - 6318: d5033bbf dmb ish - 631c: d118c01b sub x27, x0, #0x630 - 6320: 91004340 add x0, x26, #0x10 - 6324: f9400364 ldr x4, [x27] - 6328: f9400765 ldr x5, [x27,#8] - 632c: f9000485 str x5, [x4,#8] - 6330: f9400765 ldr x5, [x27,#8] - 6334: f90000a4 str x4, [x5] - 6338: d5033bbf dmb ish - 633c: 39504b04 ldrb w4, [x24,#1042] - 6340: f9014b3f str xzr, [x25,#656] - 6344: f9000f40 str x0, [x26,#24] - 6348: f9000b40 str x0, [x26,#16] - 634c: f9000421 str x1, [x1,#8] - 6350: f9000c61 str x1, [x3,#24] - 6354: 350005e4 cbnz w4, 6410 <__reclaim_stacks+0x258> - 6358: f9000360 str x0, [x27] - 635c: f9000760 str x0, [x27,#8] - 6360: f9400b40 ldr x0, [x26,#16] - 6364: f9000402 str x2, [x0,#8] - 6368: d5033bbf dmb ish - 636c: f9000b42 str x2, [x26,#16] - 6370: 910a4320 add x0, x25, #0x290 - 6374: d0000141 adrp x1, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 6378: f9014b3f str xzr, [x25,#656] - 637c: 52800022 mov w2, #0x1 // #1 - 6380: a94153f3 ldp x19, x20, [sp,#16] - 6384: b900101f str wzr, [x0,#16] - 6388: d0000160 adrp x0, 34000 <__GI___pthread_keys+0x3d78> - 638c: a9425bf5 ldp x21, x22, [sp,#32] - 6390: a94363f7 ldp x23, x24, [sp,#48] - 6394: a9446bf9 ldp x25, x26, [sp,#64] - 6398: a94573fb ldp x27, x28, [sp,#80] - 639c: fd4033e8 ldr d8, [sp,#96] - 63a0: b9025022 str w2, [x1,#592] - 63a4: b902881f str wzr, [x0,#648] - 63a8: a8c77bfd ldp x29, x30, [sp],#112 - 63ac: d65f03c0 ret - 63b0: 927ff801 and x1, x0, #0xfffffffffffffffe - 63b4: 360001c0 tbz w0, #0, 63ec <__reclaim_stacks+0x234> - 63b8: d000015a adrp x26, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 63bc: 91096342 add x2, x26, #0x258 - 63c0: aa0203e0 mov x0, x2 - 63c4: f8410c17 ldr x23, [x0,#16]! - 63c8: f94006e3 ldr x3, [x23,#8] - 63cc: eb00007f cmp x3, x0 - 63d0: 54000360 b.eq 643c <__reclaim_stacks+0x284> - 63d4: f9000037 str x23, [x1] - 63d8: 91096342 add x2, x26, #0x258 - 63dc: f9000420 str x0, [x1,#8] - 63e0: f9000001 str x1, [x0] - 63e4: f9400857 ldr x23, [x2,#16] - 63e8: 17ffff85 b 61fc <__reclaim_stacks+0x44> - 63ec: f9400020 ldr x0, [x1] - 63f0: d000015a adrp x26, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 63f4: f9400423 ldr x3, [x1,#8] - 63f8: 91096342 add x2, x26, #0x258 - 63fc: f9000403 str x3, [x0,#8] - 6400: f9400421 ldr x1, [x1,#8] - 6404: f9000020 str x0, [x1] - 6408: f9400857 ldr x23, [x2,#16] - 640c: 17ffff7c b 61fc <__reclaim_stacks+0x44> - 6410: f9000361 str x1, [x27] - 6414: f9000761 str x1, [x27,#8] - 6418: f9400c60 ldr x0, [x3,#24] - 641c: f9000402 str x2, [x0,#8] - 6420: d5033bbf dmb ish - 6424: f9000c62 str x2, [x3,#24] - 6428: 17ffffd2 b 6370 <__reclaim_stacks+0x1b8> - 642c: f9412f43 ldr x3, [x26,#600] - 6430: eb00007f cmp x3, x0 - 6434: 54fff421 b.ne 62b8 <__reclaim_stacks+0x100> - 6438: 17ffffb2 b 6300 <__reclaim_stacks+0x148> - 643c: f9412f40 ldr x0, [x26,#600] - 6440: f9400403 ldr x3, [x0,#8] - 6444: eb02007f cmp x3, x2 - 6448: 54ffeda0 b.eq 61fc <__reclaim_stacks+0x44> - 644c: aa0003f7 mov x23, x0 - 6450: aa0203e0 mov x0, x2 - 6454: 17ffffe0 b 63d4 <__reclaim_stacks+0x21c> - -0000000000006458 <__nptl_setxid_error>: - 6458: a9be7bfd stp x29, x30, [sp,#-32]! - 645c: 910003fd mov x29, sp - 6460: b9402402 ldr w2, [x0,#36] - 6464: 6b01005f cmp w2, w1 - 6468: 54000180 b.eq 6498 <__nptl_setxid_error+0x40> - 646c: 3100045f cmn w2, #0x1 - 6470: 540001c1 b.ne 64a8 <__nptl_setxid_error+0x50> - 6474: b9001fa2 str w2, [x29,#28] - 6478: 91009002 add x2, x0, #0x24 - 647c: b9401fa3 ldr w3, [x29,#28] - 6480: 885ffc44 ldaxr w4, [x2] - 6484: 6b03009f cmp w4, w3 - 6488: 54000061 b.ne 6494 <__nptl_setxid_error+0x3c> - 648c: 88057c41 stxr w5, w1, [x2] - 6490: 35ffff85 cbnz w5, 6480 <__nptl_setxid_error+0x28> - 6494: 54000061 b.ne 64a0 <__nptl_setxid_error+0x48> - 6498: a8c27bfd ldp x29, x30, [sp],#32 - 649c: d65f03c0 ret - 64a0: b9001fa4 str w4, [x29,#28] - 64a4: 17ffffef b 6460 <__nptl_setxid_error+0x8> - 64a8: 97fffb32 bl 5170 - -00000000000064ac <__nptl_setxid>: - 64ac: a9ba7bfd stp x29, x30, [sp,#-96]! - 64b0: 910003fd mov x29, sp - 64b4: a9025bf5 stp x21, x22, [sp,#32] - 64b8: d0000175 adrp x21, 34000 <__GI___pthread_keys+0x3d78> - 64bc: f90023f9 str x25, [sp,#64] - 64c0: 910a42a1 add x1, x21, #0x290 - 64c4: b9005fbf str wzr, [x29,#92] - 64c8: a90153f3 stp x19, x20, [sp,#16] - 64cc: a90363f7 stp x23, x24, [sp,#48] - 64d0: aa0003f4 mov x20, x0 - 64d4: 91004020 add x0, x1, #0x10 - 64d8: 52800021 mov w1, #0x1 // #1 - 64dc: 885ffc02 ldaxr w2, [x0] - 64e0: 6b1f005f cmp w2, wzr - 64e4: 54000061 b.ne 64f0 <__nptl_setxid+0x44> - 64e8: 88037c01 stxr w3, w1, [x0] - 64ec: 35ffff83 cbnz w3, 64dc <__nptl_setxid+0x30> - 64f0: 54000060 b.eq 64fc <__nptl_setxid+0x50> - 64f4: b9005fa2 str w2, [x29,#92] - 64f8: 9400249c bl f768 <__lll_lock_wait_private> - 64fc: d0000157 adrp x23, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 6500: 12800000 mov w0, #0xffffffff // #-1 - 6504: 910962f9 add x25, x23, #0x258 - 6508: b900229f str wzr, [x20,#32] - 650c: b9002680 str w0, [x20,#36] - 6510: d0000160 adrp x0, 34000 <__GI___pthread_keys+0x3d78> - 6514: d53bd056 mrs x22, tpidr_el0 - 6518: f8410f38 ldr x24, [x25,#16]! - 651c: d11bc2d3 sub x19, x22, #0x6f0 - 6520: f9018814 str x20, [x0,#784] - 6524: eb19031f cmp x24, x25 - 6528: 54000100 b.eq 6548 <__nptl_setxid+0x9c> - 652c: d1030300 sub x0, x24, #0xc0 - 6530: eb13001f cmp x0, x19 - 6534: 54000040 b.eq 653c <__nptl_setxid+0x90> - 6538: 97fffd5f bl 5ab4 - 653c: f9400318 ldr x24, [x24] - 6540: eb19031f cmp x24, x25 - 6544: 54ffff41 b.ne 652c <__nptl_setxid+0x80> - 6548: 910a42a0 add x0, x21, #0x290 - 654c: 91006019 add x25, x0, #0x18 - 6550: f9400c18 ldr x24, [x0,#24] - 6554: eb19031f cmp x24, x25 - 6558: 54000100 b.eq 6578 <__nptl_setxid+0xcc> - 655c: d1030300 sub x0, x24, #0xc0 - 6560: eb13001f cmp x0, x19 - 6564: 54000040 b.eq 656c <__nptl_setxid+0xc0> - 6568: 97fffd53 bl 5ab4 - 656c: f9400318 ldr x24, [x24] - 6570: eb19031f cmp x24, x25 - 6574: 54ffff41 b.ne 655c <__nptl_setxid+0xb0> - 6578: 910962e9 add x9, x23, #0x258 - 657c: 910a42a6 add x6, x21, #0x290 - 6580: 91004127 add x7, x9, #0x10 - 6584: 910060c6 add x6, x6, #0x18 - 6588: f9400923 ldr x3, [x9,#16] - 658c: 52800004 mov w4, #0x0 // #0 - 6590: eb07007f cmp x3, x7 - 6594: 54000240 b.eq 65dc <__nptl_setxid+0x130> - 6598: d1030061 sub x1, x3, #0xc0 - 659c: eb01027f cmp x19, x1 - 65a0: 54000180 b.eq 65d0 <__nptl_setxid+0x124> - 65a4: b9410820 ldr w0, [x1,#264] - 65a8: 36300100 tbz w0, #6, 65c8 <__nptl_setxid+0x11c> - 65ac: b980d660 ldrsw x0, [x19,#212] - 65b0: d2800422 mov x2, #0x21 // #33 - 65b4: b980d021 ldrsw x1, [x1,#208] - 65b8: d2801068 mov x8, #0x83 // #131 - 65bc: d4000001 svc #0x0 - 65c0: 3140041f cmn w0, #0x1, lsl #12 - 65c4: 540010e9 b.ls 67e0 <__nptl_setxid+0x334> - 65c8: 52800000 mov w0, #0x0 // #0 - 65cc: 0b000084 add w4, w4, w0 - 65d0: f9400063 ldr x3, [x3] - 65d4: eb07007f cmp x3, x7 - 65d8: 54fffe01 b.ne 6598 <__nptl_setxid+0xec> - 65dc: f94000c3 ldr x3, [x6] - 65e0: eb06007f cmp x3, x6 - 65e4: 54000240 b.eq 662c <__nptl_setxid+0x180> - 65e8: d1030061 sub x1, x3, #0xc0 - 65ec: eb01027f cmp x19, x1 - 65f0: 54000180 b.eq 6620 <__nptl_setxid+0x174> - 65f4: b9410820 ldr w0, [x1,#264] - 65f8: 36300100 tbz w0, #6, 6618 <__nptl_setxid+0x16c> - 65fc: b980d660 ldrsw x0, [x19,#212] - 6600: d2800422 mov x2, #0x21 // #33 - 6604: b980d021 ldrsw x1, [x1,#208] - 6608: d2801068 mov x8, #0x83 // #131 - 660c: d4000001 svc #0x0 - 6610: 3140041f cmn w0, #0x1, lsl #12 - 6614: 54000f89 b.ls 6804 <__nptl_setxid+0x358> - 6618: 52800000 mov w0, #0x0 // #0 - 661c: 0b000084 add w4, w4, w0 - 6620: f9400063 ldr x3, [x3] - 6624: eb06007f cmp x3, x6 - 6628: 54fffe01 b.ne 65e8 <__nptl_setxid+0x13c> - 662c: aa1403e5 mov x5, x20 - 6630: b8420ca2 ldr w2, [x5,#32]! - 6634: 34000122 cbz w2, 6658 <__nptl_setxid+0x1ac> - 6638: aa0503e0 mov x0, x5 - 663c: d2801001 mov x1, #0x80 // #128 - 6640: 93407c42 sxtw x2, w2 - 6644: d2800003 mov x3, #0x0 // #0 - 6648: d2800c48 mov x8, #0x62 // #98 - 664c: d4000001 svc #0x0 - 6650: b9402282 ldr w2, [x20,#32] - 6654: 35ffff22 cbnz w2, 6638 <__nptl_setxid+0x18c> - 6658: 35fff984 cbnz w4, 6588 <__nptl_setxid+0xdc> - 665c: 910962f7 add x23, x23, #0x258 - 6660: 52800026 mov w6, #0x1 // #1 - 6664: f8410ee4 ldr x4, [x23,#16]! - 6668: eb17009f cmp x4, x23 - 666c: 54000320 b.eq 66d0 <__nptl_setxid+0x224> - 6670: d1030085 sub x5, x4, #0xc0 - 6674: eb05027f cmp x19, x5 - 6678: 54000260 b.eq 66c4 <__nptl_setxid+0x218> - 667c: b94108a1 ldr w1, [x5,#264] - 6680: 36300221 tbz w1, #6, 66c4 <__nptl_setxid+0x218> - 6684: b9005fa1 str w1, [x29,#92] - 6688: 12197823 and w3, w1, #0xffffffbf - 668c: 91012082 add x2, x4, #0x48 - 6690: 885ffc40 ldaxr w0, [x2] - 6694: 6b01001f cmp w0, w1 - 6698: 54000061 b.ne 66a4 <__nptl_setxid+0x1f8> - 669c: 88077c43 stxr w7, w3, [x2] - 66a0: 35ffff87 cbnz w7, 6690 <__nptl_setxid+0x1e4> - 66a4: 54000c21 b.ne 6828 <__nptl_setxid+0x37c> - 66a8: b9041ca6 str w6, [x5,#1052] - 66ac: 910d7080 add x0, x4, #0x35c - 66b0: d2801021 mov x1, #0x81 // #129 - 66b4: d2800022 mov x2, #0x1 // #1 - 66b8: d2800003 mov x3, #0x0 // #0 - 66bc: d2800c48 mov x8, #0x62 // #98 - 66c0: d4000001 svc #0x0 - 66c4: f9400084 ldr x4, [x4] - 66c8: eb17009f cmp x4, x23 - 66cc: 54fffd21 b.ne 6670 <__nptl_setxid+0x1c4> - 66d0: 910a42a0 add x0, x21, #0x290 - 66d4: 52800027 mov w7, #0x1 // #1 - 66d8: 91006006 add x6, x0, #0x18 - 66dc: f9400c04 ldr x4, [x0,#24] - 66e0: eb06009f cmp x4, x6 - 66e4: 54000320 b.eq 6748 <__nptl_setxid+0x29c> - 66e8: d1030085 sub x5, x4, #0xc0 - 66ec: eb05027f cmp x19, x5 - 66f0: 54000260 b.eq 673c <__nptl_setxid+0x290> - 66f4: b94108a1 ldr w1, [x5,#264] - 66f8: 36300221 tbz w1, #6, 673c <__nptl_setxid+0x290> - 66fc: b9005fa1 str w1, [x29,#92] - 6700: 12197823 and w3, w1, #0xffffffbf - 6704: 91012082 add x2, x4, #0x48 - 6708: 885ffc40 ldaxr w0, [x2] - 670c: 6b01001f cmp w0, w1 - 6710: 54000061 b.ne 671c <__nptl_setxid+0x270> - 6714: 88087c43 stxr w8, w3, [x2] - 6718: 35ffff88 cbnz w8, 6708 <__nptl_setxid+0x25c> - 671c: 540008a1 b.ne 6830 <__nptl_setxid+0x384> - 6720: b9041ca7 str w7, [x5,#1052] - 6724: 910d7080 add x0, x4, #0x35c - 6728: d2801021 mov x1, #0x81 // #129 - 672c: d2800022 mov x2, #0x1 // #1 - 6730: d2800003 mov x3, #0x0 // #0 - 6734: d2800c48 mov x8, #0x62 // #98 - 6738: d4000001 svc #0x0 - 673c: f9400084 ldr x4, [x4] - 6740: eb06009f cmp x4, x6 - 6744: 54fffd21 b.ne 66e8 <__nptl_setxid+0x23c> - 6748: f9400680 ldr x0, [x20,#8] - 674c: f9400a81 ldr x1, [x20,#16] - 6750: f9400e82 ldr x2, [x20,#24] - 6754: b9800288 ldrsw x8, [x20] - 6758: d4000001 svc #0x0 - 675c: 3140041f cmn w0, #0x1, lsl #12 - 6760: 2a0003e5 mov w5, w0 - 6764: 540006e8 b.hi 6840 <__nptl_setxid+0x394> - 6768: 52800002 mov w2, #0x0 // #0 - 676c: b9402681 ldr w1, [x20,#36] - 6770: 6b01005f cmp w2, w1 - 6774: 54000180 b.eq 67a4 <__nptl_setxid+0x2f8> - 6778: 3100043f cmn w1, #0x1 - 677c: 54000881 b.ne 688c <__nptl_setxid+0x3e0> - 6780: b9005fa1 str w1, [x29,#92] - 6784: 91009281 add x1, x20, #0x24 - 6788: b9405fa3 ldr w3, [x29,#92] - 678c: 885ffc24 ldaxr w4, [x1] - 6790: 6b03009f cmp w4, w3 - 6794: 54000061 b.ne 67a0 <__nptl_setxid+0x2f4> - 6798: 88007c22 stxr w0, w2, [x1] - 679c: 35ffff80 cbnz w0, 678c <__nptl_setxid+0x2e0> - 67a0: 540004c1 b.ne 6838 <__nptl_setxid+0x38c> - 67a4: 910a42b5 add x21, x21, #0x290 - 67a8: 52800001 mov w1, #0x0 // #0 - 67ac: 910042b5 add x21, x21, #0x10 - 67b0: 885f7ea0 ldxr w0, [x21] - 67b4: 8802fea1 stlxr w2, w1, [x21] - 67b8: 35ffffc2 cbnz w2, 67b0 <__nptl_setxid+0x304> - 67bc: 7100041f cmp w0, #0x1 - 67c0: 540004cc b.gt 6858 <__nptl_setxid+0x3ac> - 67c4: 2a0503e0 mov w0, w5 - 67c8: f94023f9 ldr x25, [sp,#64] - 67cc: a94153f3 ldp x19, x20, [sp,#16] - 67d0: a9425bf5 ldp x21, x22, [sp,#32] - 67d4: a94363f7 ldp x23, x24, [sp,#48] - 67d8: a8c67bfd ldp x29, x30, [sp],#96 - 67dc: d65f03c0 ret - 67e0: 91008280 add x0, x20, #0x20 - 67e4: 885ffc01 ldaxr w1, [x0] - 67e8: 11000422 add w2, w1, #0x1 - 67ec: 88057c02 stxr w5, w2, [x0] - 67f0: 35ffffa5 cbnz w5, 67e4 <__nptl_setxid+0x338> - 67f4: b90057a1 str w1, [x29,#84] - 67f8: 52800020 mov w0, #0x1 // #1 - 67fc: b94057a1 ldr w1, [x29,#84] - 6800: 17ffff73 b 65cc <__nptl_setxid+0x120> - 6804: 91008280 add x0, x20, #0x20 - 6808: 885ffc01 ldaxr w1, [x0] - 680c: 11000422 add w2, w1, #0x1 - 6810: 88057c02 stxr w5, w2, [x0] - 6814: 35ffffa5 cbnz w5, 6808 <__nptl_setxid+0x35c> - 6818: b9005ba1 str w1, [x29,#88] - 681c: 52800020 mov w0, #0x1 // #1 - 6820: b9405ba1 ldr w1, [x29,#88] - 6824: 17ffff7e b 661c <__nptl_setxid+0x170> - 6828: b9005fa0 str w0, [x29,#92] - 682c: 17ffff94 b 667c <__nptl_setxid+0x1d0> - 6830: b9005fa0 str w0, [x29,#92] - 6834: 17ffffb0 b 66f4 <__nptl_setxid+0x248> - 6838: b9005fa4 str w4, [x29,#92] - 683c: 17ffffcc b 676c <__nptl_setxid+0x2c0> - 6840: 4b0003e2 neg w2, w0 - 6844: b0000140 adrp x0, 2f000 <__FRAME_END__+0x18e30> - 6848: f947c400 ldr x0, [x0,#3976] - 684c: 12800005 mov w5, #0xffffffff // #-1 - 6850: b8206ac2 str w2, [x22,x0] - 6854: 17ffffc6 b 676c <__nptl_setxid+0x2c0> - 6858: aa1503e0 mov x0, x21 - 685c: d2801021 mov x1, #0x81 // #129 - 6860: d2800022 mov x2, #0x1 // #1 - 6864: d2800003 mov x3, #0x0 // #0 - 6868: d2800c48 mov x8, #0x62 // #98 - 686c: d4000001 svc #0x0 - 6870: 2a0503e0 mov w0, w5 - 6874: f94023f9 ldr x25, [sp,#64] - 6878: a94153f3 ldp x19, x20, [sp,#16] - 687c: a9425bf5 ldp x21, x22, [sp,#32] - 6880: a94363f7 ldp x23, x24, [sp,#48] - 6884: a8c67bfd ldp x29, x30, [sp],#96 - 6888: d65f03c0 ret - 688c: 97fffa39 bl 5170 - -0000000000006890 <__pthread_init_static_tls>: - 6890: a9bb7bfd stp x29, x30, [sp,#-80]! - 6894: 910003fd mov x29, sp - 6898: a9025bf5 stp x21, x22, [sp,#32] - 689c: d0000175 adrp x21, 34000 <__GI___pthread_keys+0x3d78> - 68a0: f9001bf7 str x23, [sp,#48] - 68a4: 910a42a1 add x1, x21, #0x290 - 68a8: b9004fbf str wzr, [x29,#76] - 68ac: a90153f3 stp x19, x20, [sp,#16] - 68b0: aa0003f3 mov x19, x0 - 68b4: 91004020 add x0, x1, #0x10 - 68b8: 52800021 mov w1, #0x1 // #1 - 68bc: 885ffc02 ldaxr w2, [x0] - 68c0: 6b1f005f cmp w2, wzr - 68c4: 54000061 b.ne 68d0 <__pthread_init_static_tls+0x40> - 68c8: 88037c01 stxr w3, w1, [x0] - 68cc: 35ffff83 cbnz w3, 68bc <__pthread_init_static_tls+0x2c> - 68d0: 54000881 b.ne 69e0 <__pthread_init_static_tls+0x150> - 68d4: d0000156 adrp x22, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 68d8: 52800037 mov w23, #0x1 // #1 - 68dc: 910962d6 add x22, x22, #0x258 - 68e0: f8410ed4 ldr x20, [x22,#16]! - 68e4: eb16029f cmp x20, x22 - 68e8: 540002c0 b.eq 6940 <__pthread_init_static_tls+0xb0> - 68ec: f9422262 ldr x2, [x19,#1088] - 68f0: f9431a83 ldr x3, [x20,#1584] - 68f4: f9421e61 ldr x1, [x19,#1080] - 68f8: d37cec42 lsl x2, x2, #4 - 68fc: 8b020064 add x4, x3, x2 - 6900: 9118c021 add x1, x1, #0x630 - 6904: 8b010281 add x1, x20, x1 - 6908: f8226861 str x1, [x3,x2] - 690c: 39002097 strb w23, [x4,#8] - 6910: aa0103e0 mov x0, x1 - 6914: f9420e62 ldr x2, [x19,#1048] - 6918: f9420a61 ldr x1, [x19,#1040] - 691c: 97fffa51 bl 5260 - 6920: f9421263 ldr x3, [x19,#1056] - 6924: 52800001 mov w1, #0x0 // #0 - 6928: f9420e62 ldr x2, [x19,#1048] - 692c: cb020062 sub x2, x3, x2 - 6930: 97fff9d8 bl 5090 - 6934: f9400294 ldr x20, [x20] - 6938: eb16029f cmp x20, x22 - 693c: 54fffd81 b.ne 68ec <__pthread_init_static_tls+0x5c> - 6940: 910a42a0 add x0, x21, #0x290 - 6944: 52800037 mov w23, #0x1 // #1 - 6948: 91006016 add x22, x0, #0x18 - 694c: f9400c14 ldr x20, [x0,#24] - 6950: eb16029f cmp x20, x22 - 6954: 540002c0 b.eq 69ac <__pthread_init_static_tls+0x11c> - 6958: f9422262 ldr x2, [x19,#1088] - 695c: f9431a83 ldr x3, [x20,#1584] - 6960: f9421e61 ldr x1, [x19,#1080] - 6964: d37cec42 lsl x2, x2, #4 - 6968: 8b020064 add x4, x3, x2 - 696c: 9118c021 add x1, x1, #0x630 - 6970: 8b010281 add x1, x20, x1 - 6974: f8226861 str x1, [x3,x2] - 6978: 39002097 strb w23, [x4,#8] - 697c: aa0103e0 mov x0, x1 - 6980: f9420e62 ldr x2, [x19,#1048] - 6984: f9420a61 ldr x1, [x19,#1040] - 6988: 97fffa36 bl 5260 - 698c: f9421263 ldr x3, [x19,#1056] - 6990: 52800001 mov w1, #0x0 // #0 - 6994: f9420e62 ldr x2, [x19,#1048] - 6998: cb020062 sub x2, x3, x2 - 699c: 97fff9bd bl 5090 - 69a0: f9400294 ldr x20, [x20] - 69a4: eb16029f cmp x20, x22 - 69a8: 54fffd81 b.ne 6958 <__pthread_init_static_tls+0xc8> - 69ac: 910a42a0 add x0, x21, #0x290 - 69b0: 52800002 mov w2, #0x0 // #0 - 69b4: 91004000 add x0, x0, #0x10 - 69b8: 885f7c01 ldxr w1, [x0] - 69bc: 8803fc02 stlxr w3, w2, [x0] - 69c0: 35ffffc3 cbnz w3, 69b8 <__pthread_init_static_tls+0x128> - 69c4: 7100043f cmp w1, #0x1 - 69c8: 5400012c b.gt 69ec <__pthread_init_static_tls+0x15c> - 69cc: a94153f3 ldp x19, x20, [sp,#16] - 69d0: a9425bf5 ldp x21, x22, [sp,#32] - 69d4: f9401bf7 ldr x23, [sp,#48] - 69d8: a8c57bfd ldp x29, x30, [sp],#80 - 69dc: d65f03c0 ret - 69e0: b9004fa2 str w2, [x29,#76] - 69e4: 94002361 bl f768 <__lll_lock_wait_private> - 69e8: 17ffffbb b 68d4 <__pthread_init_static_tls+0x44> - 69ec: d2801021 mov x1, #0x81 // #129 - 69f0: d2800022 mov x2, #0x1 // #1 - 69f4: d2800003 mov x3, #0x0 // #0 - 69f8: d2800c48 mov x8, #0x62 // #98 - 69fc: d4000001 svc #0x0 - 6a00: a94153f3 ldp x19, x20, [sp,#16] - 6a04: a9425bf5 ldp x21, x22, [sp,#32] - 6a08: f9401bf7 ldr x23, [sp,#48] - 6a0c: a8c57bfd ldp x29, x30, [sp],#80 - 6a10: d65f03c0 ret - -0000000000006a14 <__wait_lookup_done>: - 6a14: a9bd7bfd stp x29, x30, [sp,#-48]! - 6a18: 52800021 mov w1, #0x1 // #1 - 6a1c: 910003fd mov x29, sp - 6a20: f9000bf3 str x19, [sp,#16] - 6a24: d0000173 adrp x19, 34000 <__GI___pthread_keys+0x3d78> - 6a28: 910a4260 add x0, x19, #0x290 - 6a2c: b9002fbf str wzr, [x29,#44] - 6a30: 91004000 add x0, x0, #0x10 - 6a34: 885ffc02 ldaxr w2, [x0] - 6a38: 6b1f005f cmp w2, wzr - 6a3c: 54000061 b.ne 6a48 <__wait_lookup_done+0x34> - 6a40: 88037c01 stxr w3, w1, [x0] - 6a44: 35ffff83 cbnz w3, 6a34 <__wait_lookup_done+0x20> - 6a48: 540004c1 b.ne 6ae0 <__wait_lookup_done+0xcc> - 6a4c: d0000147 adrp x7, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 6a50: d53bd046 mrs x6, tpidr_el0 - 6a54: 910960e7 add x7, x7, #0x258 - 6a58: d11bc0c6 sub x6, x6, #0x6f0 - 6a5c: 52800029 mov w9, #0x1 // #1 - 6a60: 5280004a mov w10, #0x2 // #2 - 6a64: f8410ce4 ldr x4, [x7,#16]! - 6a68: eb07009f cmp x4, x7 - 6a6c: 540000a1 b.ne 6a80 <__wait_lookup_done+0x6c> - 6a70: 14000023 b 6afc <__wait_lookup_done+0xe8> - 6a74: f9400084 ldr x4, [x4] - 6a78: eb07009f cmp x4, x7 - 6a7c: 54000400 b.eq 6afc <__wait_lookup_done+0xe8> - 6a80: d1030081 sub x1, x4, #0xc0 - 6a84: eb0100df cmp x6, x1 - 6a88: 54ffff60 b.eq 6a74 <__wait_lookup_done+0x60> - 6a8c: b8544082 ldr w2, [x4,#-188] - 6a90: 34ffff22 cbz w2, 6a74 <__wait_lookup_done+0x60> - 6a94: b9002fa9 str w9, [x29,#44] - 6a98: 91001025 add x5, x1, #0x4 - 6a9c: 2a0903e0 mov w0, w9 - 6aa0: 885ffca1 ldaxr w1, [x5] - 6aa4: 6b00003f cmp w1, w0 - 6aa8: 54000061 b.ne 6ab4 <__wait_lookup_done+0xa0> - 6aac: 88027caa stxr w2, w10, [x5] - 6ab0: 35ffff82 cbnz w2, 6aa0 <__wait_lookup_done+0x8c> - 6ab4: 540001c1 b.ne 6aec <__wait_lookup_done+0xd8> - 6ab8: aa0503e0 mov x0, x5 - 6abc: d2801001 mov x1, #0x80 // #128 - 6ac0: d2800042 mov x2, #0x2 // #2 - 6ac4: d2800003 mov x3, #0x0 // #0 - 6ac8: d2800c48 mov x8, #0x62 // #98 - 6acc: d4000001 svc #0x0 - 6ad0: b8544080 ldr w0, [x4,#-188] - 6ad4: 7100081f cmp w0, #0x2 - 6ad8: 54ffff00 b.eq 6ab8 <__wait_lookup_done+0xa4> - 6adc: 17ffffe6 b 6a74 <__wait_lookup_done+0x60> - 6ae0: b9002fa2 str w2, [x29,#44] - 6ae4: 94002321 bl f768 <__lll_lock_wait_private> - 6ae8: 17ffffd9 b 6a4c <__wait_lookup_done+0x38> - 6aec: b9002fa1 str w1, [x29,#44] - 6af0: f9400084 ldr x4, [x4] - 6af4: eb07009f cmp x4, x7 - 6af8: 54fffc41 b.ne 6a80 <__wait_lookup_done+0x6c> - 6afc: 910a4260 add x0, x19, #0x290 - 6b00: 52800029 mov w9, #0x1 // #1 - 6b04: 91006007 add x7, x0, #0x18 - 6b08: 5280004a mov w10, #0x2 // #2 - 6b0c: f9400c04 ldr x4, [x0,#24] - 6b10: eb07009f cmp x4, x7 - 6b14: 540000a1 b.ne 6b28 <__wait_lookup_done+0x114> - 6b18: 14000020 b 6b98 <__wait_lookup_done+0x184> - 6b1c: f9400084 ldr x4, [x4] - 6b20: eb07009f cmp x4, x7 - 6b24: 540003a0 b.eq 6b98 <__wait_lookup_done+0x184> - 6b28: d1030081 sub x1, x4, #0xc0 - 6b2c: eb0100df cmp x6, x1 - 6b30: 54ffff60 b.eq 6b1c <__wait_lookup_done+0x108> - 6b34: b8544082 ldr w2, [x4,#-188] - 6b38: 34ffff22 cbz w2, 6b1c <__wait_lookup_done+0x108> - 6b3c: b9002fa9 str w9, [x29,#44] - 6b40: 91001025 add x5, x1, #0x4 - 6b44: 2a0903e0 mov w0, w9 - 6b48: 885ffca1 ldaxr w1, [x5] - 6b4c: 6b00003f cmp w1, w0 - 6b50: 54000061 b.ne 6b5c <__wait_lookup_done+0x148> - 6b54: 88027caa stxr w2, w10, [x5] - 6b58: 35ffff82 cbnz w2, 6b48 <__wait_lookup_done+0x134> - 6b5c: 54000161 b.ne 6b88 <__wait_lookup_done+0x174> - 6b60: aa0503e0 mov x0, x5 - 6b64: d2801001 mov x1, #0x80 // #128 - 6b68: d2800042 mov x2, #0x2 // #2 - 6b6c: d2800003 mov x3, #0x0 // #0 - 6b70: d2800c48 mov x8, #0x62 // #98 - 6b74: d4000001 svc #0x0 - 6b78: b8544080 ldr w0, [x4,#-188] - 6b7c: 7100081f cmp w0, #0x2 - 6b80: 54ffff00 b.eq 6b60 <__wait_lookup_done+0x14c> - 6b84: 17ffffe6 b 6b1c <__wait_lookup_done+0x108> - 6b88: b9002fa1 str w1, [x29,#44] - 6b8c: f9400084 ldr x4, [x4] - 6b90: eb07009f cmp x4, x7 - 6b94: 54fffca1 b.ne 6b28 <__wait_lookup_done+0x114> - 6b98: 910a4260 add x0, x19, #0x290 - 6b9c: 52800002 mov w2, #0x0 // #0 - 6ba0: 91004000 add x0, x0, #0x10 - 6ba4: 885f7c01 ldxr w1, [x0] - 6ba8: 8803fc02 stlxr w3, w2, [x0] - 6bac: 35ffffc3 cbnz w3, 6ba4 <__wait_lookup_done+0x190> - 6bb0: 7100043f cmp w1, #0x1 - 6bb4: 5400008c b.gt 6bc4 <__wait_lookup_done+0x1b0> - 6bb8: f9400bf3 ldr x19, [sp,#16] - 6bbc: a8c37bfd ldp x29, x30, [sp],#48 - 6bc0: d65f03c0 ret - 6bc4: d2801021 mov x1, #0x81 // #129 - 6bc8: d2800022 mov x2, #0x1 // #1 - 6bcc: d2800003 mov x3, #0x0 // #0 - 6bd0: d2800c48 mov x8, #0x62 // #98 - 6bd4: d4000001 svc #0x0 - 6bd8: f9400bf3 ldr x19, [sp,#16] - 6bdc: a8c37bfd ldp x29, x30, [sp],#48 - 6be0: d65f03c0 ret - -0000000000006be4 <__find_in_stack_list>: - 6be4: a9bd7bfd stp x29, x30, [sp,#-48]! - 6be8: 910003fd mov x29, sp - 6bec: a90153f3 stp x19, x20, [sp,#16] - 6bf0: d0000174 adrp x20, 34000 <__GI___pthread_keys+0x3d78> - 6bf4: aa0003f3 mov x19, x0 - 6bf8: 910a4281 add x1, x20, #0x290 - 6bfc: b9002fbf str wzr, [x29,#44] - 6c00: 91004020 add x0, x1, #0x10 - 6c04: 52800021 mov w1, #0x1 // #1 - 6c08: 885ffc02 ldaxr w2, [x0] - 6c0c: 6b1f005f cmp w2, wzr - 6c10: 54000061 b.ne 6c1c <__find_in_stack_list+0x38> - 6c14: 88037c01 stxr w3, w1, [x0] - 6c18: 35ffff83 cbnz w3, 6c08 <__find_in_stack_list+0x24> - 6c1c: 54000421 b.ne 6ca0 <__find_in_stack_list+0xbc> - 6c20: d0000143 adrp x3, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 6c24: 91096063 add x3, x3, #0x258 - 6c28: f8410c61 ldr x1, [x3,#16]! - 6c2c: eb03003f cmp x1, x3 - 6c30: 54000160 b.eq 6c5c <__find_in_stack_list+0x78> - 6c34: d1030020 sub x0, x1, #0xc0 - 6c38: eb00027f cmp x19, x0 - 6c3c: 54000081 b.ne 6c4c <__find_in_stack_list+0x68> - 6c40: 1400001b b 6cac <__find_in_stack_list+0xc8> - 6c44: eb02027f cmp x19, x2 - 6c48: 54000320 b.eq 6cac <__find_in_stack_list+0xc8> - 6c4c: f9400021 ldr x1, [x1] - 6c50: eb03003f cmp x1, x3 - 6c54: d1030022 sub x2, x1, #0xc0 - 6c58: 54ffff61 b.ne 6c44 <__find_in_stack_list+0x60> - 6c5c: 910a4280 add x0, x20, #0x290 - 6c60: 91006002 add x2, x0, #0x18 - 6c64: f9400c00 ldr x0, [x0,#24] - 6c68: eb02001f cmp x0, x2 - 6c6c: 54000160 b.eq 6c98 <__find_in_stack_list+0xb4> - 6c70: d1030001 sub x1, x0, #0xc0 - 6c74: eb01027f cmp x19, x1 - 6c78: 54000081 b.ne 6c88 <__find_in_stack_list+0xa4> - 6c7c: 1400000d b 6cb0 <__find_in_stack_list+0xcc> - 6c80: eb01027f cmp x19, x1 - 6c84: 54000160 b.eq 6cb0 <__find_in_stack_list+0xcc> - 6c88: f9400000 ldr x0, [x0] - 6c8c: eb02001f cmp x0, x2 - 6c90: d1030001 sub x1, x0, #0xc0 - 6c94: 54ffff61 b.ne 6c80 <__find_in_stack_list+0x9c> - 6c98: d2800013 mov x19, #0x0 // #0 - 6c9c: 14000005 b 6cb0 <__find_in_stack_list+0xcc> - 6ca0: b9002fa2 str w2, [x29,#44] - 6ca4: 940022b1 bl f768 <__lll_lock_wait_private> - 6ca8: 17ffffde b 6c20 <__find_in_stack_list+0x3c> - 6cac: b4fffd93 cbz x19, 6c5c <__find_in_stack_list+0x78> - 6cb0: 910a4280 add x0, x20, #0x290 - 6cb4: 52800002 mov w2, #0x0 // #0 - 6cb8: 91004000 add x0, x0, #0x10 - 6cbc: 885f7c01 ldxr w1, [x0] - 6cc0: 8803fc02 stlxr w3, w2, [x0] - 6cc4: 35ffffc3 cbnz w3, 6cbc <__find_in_stack_list+0xd8> - 6cc8: 7100043f cmp w1, #0x1 - 6ccc: 540000ac b.gt 6ce0 <__find_in_stack_list+0xfc> - 6cd0: aa1303e0 mov x0, x19 - 6cd4: a94153f3 ldp x19, x20, [sp,#16] - 6cd8: a8c37bfd ldp x29, x30, [sp],#48 - 6cdc: d65f03c0 ret - 6ce0: d2801021 mov x1, #0x81 // #129 - 6ce4: d2800022 mov x2, #0x1 // #1 - 6ce8: d2800003 mov x3, #0x0 // #0 - 6cec: d2800c48 mov x8, #0x62 // #98 - 6cf0: d4000001 svc #0x0 - 6cf4: aa1303e0 mov x0, x19 - 6cf8: a94153f3 ldp x19, x20, [sp,#16] - 6cfc: a8c37bfd ldp x29, x30, [sp],#48 - 6d00: d65f03c0 ret - -0000000000006d04 <__nptl_deallocate_tsd>: - 6d04: a9ba7bfd stp x29, x30, [sp,#-96]! - 6d08: 910003fd mov x29, sp - 6d0c: a90363f7 stp x23, x24, [sp,#48] - 6d10: d53bd058 mrs x24, tpidr_el0 - 6d14: a9046bf9 stp x25, x26, [sp,#64] - 6d18: d11bc319 sub x25, x24, #0x6f0 - 6d1c: a90153f3 stp x19, x20, [sp,#16] - 6d20: a9025bf5 stp x21, x22, [sp,#32] - 6d24: 39504320 ldrb w0, [x25,#1040] - 6d28: a90573fb stp x27, x28, [sp,#80] - 6d2c: 340006e0 cbz w0, 6e08 <__nptl_deallocate_tsd+0x104> - 6d30: d280009a mov x26, #0x4 // #4 - 6d34: d10f831c sub x28, x24, #0x3e0 - 6d38: d000015b adrp x27, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 6d3c: 3910433f strb wzr, [x25,#1040] - 6d40: aa1c03f7 mov x23, x28 - 6d44: 91124375 add x21, x27, #0x490 - 6d48: d2800416 mov x22, #0x20 // #32 - 6d4c: f94002f3 ldr x19, [x23] - 6d50: b40002d3 cbz x19, 6da8 <__nptl_deallocate_tsd+0xa4> - 6d54: 91002273 add x19, x19, #0x8 - 6d58: d10802b4 sub x20, x21, #0x200 - 6d5c: 14000005 b 6d70 <__nptl_deallocate_tsd+0x6c> - 6d60: 91004294 add x20, x20, #0x10 - 6d64: 91004273 add x19, x19, #0x10 - 6d68: eb15029f cmp x20, x21 - 6d6c: 540001e0 b.eq 6da8 <__nptl_deallocate_tsd+0xa4> - 6d70: f9400260 ldr x0, [x19] - 6d74: b4ffff60 cbz x0, 6d60 <__nptl_deallocate_tsd+0x5c> - 6d78: f85f8282 ldr x2, [x20,#-8] - 6d7c: f85f8263 ldr x3, [x19,#-8] - 6d80: f900027f str xzr, [x19] - 6d84: eb02007f cmp x3, x2 - 6d88: 54fffec1 b.ne 6d60 <__nptl_deallocate_tsd+0x5c> - 6d8c: f9400282 ldr x2, [x20] - 6d90: b4fffe82 cbz x2, 6d60 <__nptl_deallocate_tsd+0x5c> - 6d94: d63f0040 blr x2 - 6d98: 91004294 add x20, x20, #0x10 - 6d9c: eb15029f cmp x20, x21 - 6da0: 91004273 add x19, x19, #0x10 - 6da4: 54fffe61 b.ne 6d70 <__nptl_deallocate_tsd+0x6c> - 6da8: 910082d6 add x22, x22, #0x20 - 6dac: 910022f7 add x23, x23, #0x8 - 6db0: f11082df cmp x22, #0x420 - 6db4: 910802b5 add x21, x21, #0x200 - 6db8: 54fffca1 b.ne 6d4c <__nptl_deallocate_tsd+0x48> - 6dbc: 39504320 ldrb w0, [x25,#1040] - 6dc0: 340000e0 cbz w0, 6ddc <__nptl_deallocate_tsd+0xd8> - 6dc4: f100075a subs x26, x26, #0x1 - 6dc8: 54fffba1 b.ne 6d3c <__nptl_deallocate_tsd+0x38> - 6dcc: 91044320 add x0, x25, #0x110 - 6dd0: 2a1a03e1 mov w1, w26 - 6dd4: d2804002 mov x2, #0x200 // #512 - 6dd8: 97fff8ae bl 5090 - 6ddc: d10f6313 sub x19, x24, #0x3d8 - 6de0: d10b8314 sub x20, x24, #0x2e0 - 6de4: f9400261 ldr x1, [x19] - 6de8: aa0103e0 mov x0, x1 - 6dec: b4000061 cbz x1, 6df8 <__nptl_deallocate_tsd+0xf4> - 6df0: 97fff90c bl 5220 - 6df4: f900027f str xzr, [x19] - 6df8: 91002273 add x19, x19, #0x8 - 6dfc: eb14027f cmp x19, x20 - 6e00: 54ffff21 b.ne 6de4 <__nptl_deallocate_tsd+0xe0> - 6e04: 3910433f strb wzr, [x25,#1040] - 6e08: a94153f3 ldp x19, x20, [sp,#16] - 6e0c: a9425bf5 ldp x21, x22, [sp,#32] - 6e10: a94363f7 ldp x23, x24, [sp,#48] - 6e14: a9446bf9 ldp x25, x26, [sp,#64] - 6e18: a94573fb ldp x27, x28, [sp,#80] - 6e1c: a8c67bfd ldp x29, x30, [sp],#96 - 6e20: d65f03c0 ret - -0000000000006e24 <__free_tcb>: - 6e24: a9bd7bfd stp x29, x30, [sp,#-48]! - 6e28: 91042002 add x2, x0, #0x108 - 6e2c: 910003fd mov x29, sp - 6e30: f9000bf3 str x19, [sp,#16] - 6e34: b9410801 ldr w1, [x0,#264] - 6e38: b9002fa1 str w1, [x29,#44] - 6e3c: 321b0024 orr w4, w1, #0x20 - 6e40: 2a0103e3 mov w3, w1 - 6e44: 885ffc45 ldaxr w5, [x2] - 6e48: 6b0300bf cmp w5, w3 - 6e4c: 54000061 b.ne 6e58 <__free_tcb+0x34> - 6e50: 88067c44 stxr w6, w4, [x2] - 6e54: 35ffff86 cbnz w6, 6e44 <__free_tcb+0x20> - 6e58: 54fffee1 b.ne 6e34 <__free_tcb+0x10> - 6e5c: 372800c1 tbnz w1, #5, 6e74 <__free_tcb+0x50> - 6e60: aa0003f3 mov x19, x0 - 6e64: f9425800 ldr x0, [x0,#1200] - 6e68: b50000c0 cbnz x0, 6e80 <__free_tcb+0x5c> - 6e6c: aa1303e0 mov x0, x19 - 6e70: 97fffb81 bl 5c74 <__deallocate_stack> - 6e74: f9400bf3 ldr x19, [sp,#16] - 6e78: a8c37bfd ldp x29, x30, [sp],#48 - 6e7c: d65f03c0 ret - 6e80: f9025a7f str xzr, [x19,#1200] - 6e84: 97fff8e7 bl 5220 - 6e88: 17fffff9 b 6e6c <__free_tcb+0x48> - -0000000000006e8c : - 6e8c: a9ae7bfd stp x29, x30, [sp,#-288]! - 6e90: 9112e002 add x2, x0, #0x4b8 - 6e94: b0000141 adrp x1, 2f000 <__FRAME_END__+0x18e30> - 6e98: f947cc21 ldr x1, [x1,#3992] - 6e9c: 910003fd mov x29, sp - 6ea0: a90153f3 stp x19, x20, [sp,#16] - 6ea4: aa0003f3 mov x19, x0 - 6ea8: f90013f5 str x21, [sp,#32] - 6eac: f9001fa0 str x0, [x29,#56] - 6eb0: d53bd040 mrs x0, tpidr_el0 - 6eb4: f8216802 str x2, [x0,x1] - 6eb8: 97fff8d6 bl 5210 <__ctype_init@plt> - 6ebc: 91107260 add x0, x19, #0x41c - 6ec0: 52800002 mov w2, #0x0 // #0 - 6ec4: 885ffc01 ldaxr w1, [x0] - 6ec8: 88037c02 stxr w3, w2, [x0] - 6ecc: 35ffffc3 cbnz w3, 6ec4 - 6ed0: 3100083f cmn w1, #0x2 - 6ed4: 54000e00 b.eq 7094 - 6ed8: f9401fa2 ldr x2, [x29,#56] - 6edc: d2800301 mov x1, #0x18 // #24 - 6ee0: d2800c68 mov x8, #0x63 // #99 - 6ee4: 91038040 add x0, x2, #0xe0 - 6ee8: d4000001 svc #0x0 - 6eec: b9441440 ldr w0, [x2,#1044] - 6ef0: 37100880 tbnz w0, #2, 7000 - 6ef4: 910123a0 add x0, x29, #0x48 - 6ef8: f90083bf str xzr, [x29,#256] - 6efc: f90087bf str xzr, [x29,#264] - 6f00: 97fff828 bl 4fa0 <_setjmp@plt> - 6f04: 2a0003f3 mov w19, w0 - 6f08: 35000160 cbnz w0, 6f34 - 6f0c: f9401fa2 ldr x2, [x29,#56] - 6f10: 910123a1 add x1, x29, #0x48 - 6f14: 39504c40 ldrb w0, [x2,#1043] - 6f18: f9008041 str x1, [x2,#256] - 6f1c: 350008e0 cbnz w0, 7038 - 6f20: f9401fb3 ldr x19, [x29,#56] - 6f24: f9421e61 ldr x1, [x19,#1080] - 6f28: f9422260 ldr x0, [x19,#1088] - 6f2c: d63f0020 blr x1 - 6f30: f9021660 str x0, [x19,#1064] - 6f34: 97fff873 bl 5100 <__call_tls_dtors@plt> - 6f38: 97ffff73 bl 6d04 <__nptl_deallocate_tsd> - 6f3c: 97fff879 bl 5120 <__libc_thread_freeres@plt> - 6f40: d0000140 adrp x0, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 6f44: 91094000 add x0, x0, #0x250 - 6f48: 885ffc01 ldaxr w1, [x0] - 6f4c: 51000422 sub w2, w1, #0x1 - 6f50: 88037c02 stxr w3, w2, [x0] - 6f54: 35ffffa3 cbnz w3, 6f48 - 6f58: 7100043f cmp w1, #0x1 - 6f5c: 54000ae0 b.eq 70b8 - 6f60: f9401fa0 ldr x0, [x29,#56] - 6f64: 39504400 ldrb w0, [x0,#1041] - 6f68: 35000c00 cbnz w0, 70e8 - 6f6c: f9401fa0 ldr x0, [x29,#56] - 6f70: 91042001 add x1, x0, #0x108 - 6f74: f9401fa0 ldr x0, [x29,#56] - 6f78: b9410800 ldr w0, [x0,#264] - 6f7c: b90043a0 str w0, [x29,#64] - 6f80: 321c0003 orr w3, w0, #0x10 - 6f84: 885ffc22 ldaxr w2, [x1] - 6f88: 6b00005f cmp w2, w0 - 6f8c: 54000061 b.ne 6f98 - 6f90: 88047c23 stxr w4, w3, [x1] - 6f94: 35ffff84 cbnz w4, 6f84 - 6f98: 1a9f17e0 cset w0, eq - 6f9c: 35000040 cbnz w0, 6fa4 - 6fa0: b90043a2 str w2, [x29,#64] - 6fa4: 34fffe80 cbz w0, 6f74 - 6fa8: 97fff816 bl 5000 <__getpagesize@plt> - 6fac: f9401fa1 ldr x1, [x29,#56] - 6fb0: f9424822 ldr x2, [x1,#1168] - 6fb4: 51000401 sub w1, w0, #0x1 - 6fb8: cb0203a0 sub x0, x29, x2 - 6fbc: 93407c21 sxtw x1, w1 - 6fc0: 8a210001 bic x1, x0, x1 - 6fc4: f140803f cmp x1, #0x20, lsl #12 - 6fc8: 54000f88 b.hi 71b8 - 6fcc: f9401fa1 ldr x1, [x29,#56] - 6fd0: f9421020 ldr x0, [x1,#1056] - 6fd4: eb00003f cmp x1, x0 - 6fd8: 54000ea0 b.eq 71ac - 6fdc: f9401fa0 ldr x0, [x29,#56] - 6fe0: b9410800 ldr w0, [x0,#264] - 6fe4: 373009a0 tbnz w0, #6, 7118 - 6fe8: d2800002 mov x2, #0x0 // #0 - 6fec: d2800ba1 mov x1, #0x5d // #93 - 6ff0: aa0203e0 mov x0, x2 - 6ff4: aa0103e8 mov x8, x1 - 6ff8: d4000001 svc #0x0 - 6ffc: 17fffffd b 6ff0 - 7000: 910123b3 add x19, x29, #0x48 - 7004: 52800001 mov w1, #0x0 // #0 - 7008: aa1303e0 mov x0, x19 - 700c: d2801002 mov x2, #0x80 // #128 - 7010: 97fff820 bl 5090 - 7014: d2b00001 mov x1, #0x80000000 // #2147483648 - 7018: d2800020 mov x0, #0x1 // #1 - 701c: f90027a1 str x1, [x29,#72] - 7020: d2800002 mov x2, #0x0 // #0 - 7024: aa1303e1 mov x1, x19 - 7028: d2800103 mov x3, #0x8 // #8 - 702c: d28010e8 mov x8, #0x87 // #135 - 7030: d4000001 svc #0x0 - 7034: 17ffffb0 b 6ef4 - 7038: 94002178 bl f618 <__pthread_enable_asynccancel> - 703c: 2a0003f5 mov w21, w0 - 7040: f9401fa0 ldr x0, [x29,#56] - 7044: 52800021 mov w1, #0x1 // #1 - 7048: b90043b3 str w19, [x29,#64] - 704c: 91106014 add x20, x0, #0x418 - 7050: 885ffe80 ldaxr w0, [x20] - 7054: 6b13001f cmp w0, w19 - 7058: 54000061 b.ne 7064 - 705c: 88027e81 stxr w2, w1, [x20] - 7060: 35ffff82 cbnz w2, 7050 - 7064: 1a9f17e1 cset w1, eq - 7068: 34000221 cbz w1, 70ac - 706c: 340002a1 cbz w1, 70c0 - 7070: 52800001 mov w1, #0x0 // #0 - 7074: 885f7e80 ldxr w0, [x20] - 7078: 8802fe81 stlxr w2, w1, [x20] - 707c: 35ffffc2 cbnz w2, 7074 - 7080: 7100041f cmp w0, #0x1 - 7084: 5400024c b.gt 70cc - 7088: 2a1503e0 mov w0, w21 - 708c: 94002193 bl f6d8 <__pthread_disable_asynccancel> - 7090: 17ffffa4 b 6f20 - 7094: d2801021 mov x1, #0x81 // #129 - 7098: d2800022 mov x2, #0x1 // #1 - 709c: d2800003 mov x3, #0x0 // #0 - 70a0: d2800c48 mov x8, #0x62 // #98 - 70a4: d4000001 svc #0x0 - 70a8: 17ffff8c b 6ed8 - 70ac: b90043a0 str w0, [x29,#64] - 70b0: 35fffe01 cbnz w1, 7070 - 70b4: 14000003 b 70c0 - 70b8: 52800000 mov w0, #0x0 // #0 - 70bc: 97fff7b5 bl 4f90 - 70c0: aa1403e0 mov x0, x20 - 70c4: 940021a9 bl f768 <__lll_lock_wait_private> - 70c8: 17ffffea b 7070 - 70cc: aa1403e0 mov x0, x20 - 70d0: d2801021 mov x1, #0x81 // #129 - 70d4: d2800022 mov x2, #0x1 // #1 - 70d8: d2800003 mov x3, #0x0 // #0 - 70dc: d2800c48 mov x8, #0x62 // #98 - 70e0: d4000001 svc #0x0 - 70e4: 17ffffe9 b 7088 - 70e8: b0000163 adrp x3, 34000 <__GI___pthread_keys+0x3d78> - 70ec: f9401fa0 ldr x0, [x29,#56] - 70f0: 910a4063 add x3, x3, #0x290 - 70f4: b9444801 ldr w1, [x0,#1096] - 70f8: b9402860 ldr w0, [x3,#40] - 70fc: 2a000020 orr w0, w1, w0 - 7100: 3647f360 tbz w0, #8, 6f6c - 7104: f9401fa0 ldr x0, [x29,#56] - 7108: f9423000 ldr x0, [x0,#1120] - 710c: b4000280 cbz x0, 715c - 7110: 97fffa5e bl 5a88 <__GI___nptl_death_event> - 7114: 17ffff96 b 6f6c - 7118: f9401fa0 ldr x0, [x29,#56] - 711c: d2801006 mov x6, #0x80 // #128 - 7120: d2800004 mov x4, #0x0 // #0 - 7124: d2800c45 mov x5, #0x62 // #98 - 7128: 91107007 add x7, x0, #0x41c - 712c: aa0703e0 mov x0, x7 - 7130: aa0603e1 mov x1, x6 - 7134: aa0403e2 mov x2, x4 - 7138: aa0403e3 mov x3, x4 - 713c: aa0503e8 mov x8, x5 - 7140: d4000001 svc #0x0 - 7144: f9401fa0 ldr x0, [x29,#56] - 7148: b9410800 ldr w0, [x0,#264] - 714c: 3737ff00 tbnz w0, #6, 712c - 7150: f9401fa0 ldr x0, [x29,#56] - 7154: b9041c04 str w4, [x0,#1052] - 7158: 17ffffa4 b 6fe8 - 715c: f9401fa4 ldr x4, [x29,#56] - 7160: aa0403e0 mov x0, x4 - 7164: f9022c04 str x4, [x0,#1112] - 7168: 52800120 mov w0, #0x9 // #9 - 716c: b9045080 str w0, [x4,#1104] - 7170: aa0303e1 mov x1, x3 - 7174: f9401fa2 ldr x2, [x29,#56] - 7178: f8430c20 ldr x0, [x1,#48]! - 717c: f9023040 str x0, [x2,#1120] - 7180: f90023a0 str x0, [x29,#64] - 7184: c85ffc22 ldaxr x2, [x1] - 7188: eb00005f cmp x2, x0 - 718c: 54000061 b.ne 7198 - 7190: c8057c24 stxr w5, x4, [x1] - 7194: 35ffff85 cbnz w5, 7184 - 7198: 1a9f17e0 cset w0, eq - 719c: 35000040 cbnz w0, 71a4 - 71a0: f90023a2 str x2, [x29,#64] - 71a4: 34fffe60 cbz w0, 7170 - 71a8: 17ffffda b 7110 - 71ac: f9401fa0 ldr x0, [x29,#56] - 71b0: 97ffff1d bl 6e24 <__free_tcb> - 71b4: 17ffff8d b 6fe8 - 71b8: aa0203e0 mov x0, x2 - 71bc: d1408021 sub x1, x1, #0x20, lsl #12 - 71c0: 52800082 mov w2, #0x4 // #4 - 71c4: 97fff843 bl 52d0 <__madvise@plt> - 71c8: 17ffff81 b 6fcc - -00000000000071cc : - 71cc: a9b17bfd stp x29, x30, [sp,#-240]! - 71d0: 910003fd mov x29, sp - 71d4: 6d0627e8 stp d8, d9, [sp,#96] - 71d8: a90363f7 stp x23, x24, [sp,#48] - 71dc: 6d072fea stp d10, d11, [sp,#112] - 71e0: a90573fb stp x27, x28, [sp,#80] - 71e4: 6d0837ec stp d12, d13, [sp,#128] - 71e8: a90153f3 stp x19, x20, [sp,#16] - 71ec: a9025bf5 stp x21, x22, [sp,#32] - 71f0: a9046bf9 stp x25, x26, [sp,#64] - 71f4: aa0103f8 mov x24, x1 - 71f8: aa0203fb mov x27, x2 - 71fc: 9e67000b fmov d11, x0 - 7200: 9e67006c fmov d12, x3 - 7204: 1e2703e8 fmov s8, wzr - 7208: b40038a1 cbz x1, 791c - 720c: 97fff77d bl 5000 <__getpagesize@plt> - 7210: f9401314 ldr x20, [x24,#32] - 7214: 51000400 sub w0, w0, #0x1 - 7218: 93407c13 sxtw x19, w0 - 721c: b4001d14 cbz x20, 75bc - 7220: b9400b00 ldr w0, [x24,#8] - 7224: 37185020 tbnz w0, #3, 7c28 - 7228: 9000014a adrp x10, 2f000 <__FRAME_END__+0x18e30> - 722c: b000016b adrp x11, 34000 <__GI___pthread_keys+0x3d78> - 7230: b000016c adrp x12, 34000 <__GI___pthread_keys+0x3d78> - 7234: f9400b19 ldr x25, [x24,#16] - 7238: aa3303e0 mvn x0, x19 - 723c: 52800095 mov w21, #0x4 // #4 - 7240: f947ed41 ldr x1, [x10,#4056] - 7244: 8b190279 add x25, x19, x25 - 7248: f9419162 ldr x2, [x11,#800] - 724c: 8a190019 and x25, x0, x25 - 7250: f9418d89 ldr x9, [x12,#792] - 7254: 528000fa mov w26, #0x7 // #7 - 7258: b94fa021 ldr w1, [x1,#4000] - 725c: 91200042 add x2, x2, #0x800 - 7260: 8b130053 add x19, x2, x19 - 7264: 8a29029c bic x28, x20, x9 - 7268: 72000021 ands w1, w1, #0x1 - 726c: 8b190273 add x19, x19, x25 - 7270: 8a000273 and x19, x19, x0 - 7274: 1a9f12b5 csel w21, w21, wzr, ne - 7278: 52800060 mov w0, #0x3 // #3 - 727c: 6b1f003f cmp w1, wzr - 7280: 1a801340 csel w0, w26, w0, ne - 7284: eb13039f cmp x28, x19 - 7288: 1e27000d fmov s13, w0 - 728c: 54001d03 b.cc 762c - 7290: b0000174 adrp x20, 34000 <__GI___pthread_keys+0x3d78> - 7294: b900b3bf str wzr, [x29,#176] - 7298: 910a4280 add x0, x20, #0x290 - 729c: 52800021 mov w1, #0x1 // #1 - 72a0: 91004000 add x0, x0, #0x10 - 72a4: 885ffc02 ldaxr w2, [x0] - 72a8: 6b1f005f cmp w2, wzr - 72ac: 54000061 b.ne 72b8 - 72b0: 88037c01 stxr w3, w1, [x0] - 72b4: 35ffff83 cbnz w3, 72a4 - 72b8: 54001581 b.ne 7568 - 72bc: b0000156 adrp x22, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 72c0: 910962c7 add x7, x22, #0x258 - 72c4: f9412ec4 ldr x4, [x22,#600] - 72c8: eb07009f cmp x4, x7 - 72cc: 54002460 b.eq 7758 - 72d0: d2800013 mov x19, #0x0 // #0 - 72d4: 14000004 b 72e4 - 72d8: f9400084 ldr x4, [x4] - 72dc: eb07009f cmp x4, x7 - 72e0: 54000200 b.eq 7320 - 72e4: d1030085 sub x5, x4, #0xc0 - 72e8: b940d0a6 ldr w6, [x5,#208] - 72ec: 6b1f00df cmp w6, wzr - 72f0: 54ffff4c b.gt 72d8 - 72f4: f9424ca0 ldr x0, [x5,#1176] - 72f8: eb00039f cmp x28, x0 - 72fc: 54fffee8 b.hi 72d8 - 7300: 54004240 b.eq 7b48 - 7304: b4001993 cbz x19, 7634 - 7308: f9424e61 ldr x1, [x19,#1176] - 730c: f9400084 ldr x4, [x4] - 7310: eb01001f cmp x0, x1 - 7314: 9a852273 csel x19, x19, x5, cs - 7318: eb07009f cmp x4, x7 - 731c: 54fffe41 b.ne 72e4 - 7320: b40021d3 cbz x19, 7758 - 7324: f9424e60 ldr x0, [x19,#1176] - 7328: eb1c081f cmp x0, x28, lsl #2 - 732c: 54002168 b.hi 7758 - 7330: 9103027a add x26, x19, #0xc0 - 7334: 12800000 mov w0, #0xffffffff // #-1 - 7338: f9014a9a str x26, [x20,#656] - 733c: 910962d6 add x22, x22, #0x258 - 7340: b9041e60 str w0, [x19,#1052] - 7344: aa1603e2 mov x2, x22 - 7348: b2400344 orr x4, x26, #0x1 - 734c: 910a4281 add x1, x20, #0x290 - 7350: d5033bbf dmb ish - 7354: f9406263 ldr x3, [x19,#192] - 7358: f9406665 ldr x5, [x19,#200] - 735c: 91004020 add x0, x1, #0x10 - 7360: f9000465 str x5, [x3,#8] - 7364: f9406665 ldr x5, [x19,#200] - 7368: f90000a3 str x3, [x5] - 736c: d5033bbf dmb ish - 7370: f9014a84 str x4, [x20,#656] - 7374: d5033bbf dmb ish - 7378: f8410c43 ldr x3, [x2,#16]! - 737c: f9006263 str x3, [x19,#192] - 7380: f9006662 str x2, [x19,#200] - 7384: f900047a str x26, [x3,#8] - 7388: d5033bbf dmb ish - 738c: f9000ada str x26, [x22,#16] - 7390: d5033bbf dmb ish - 7394: f9400422 ldr x2, [x1,#8] - 7398: f9424e63 ldr x3, [x19,#1176] - 739c: f9014a9f str xzr, [x20,#656] - 73a0: cb030042 sub x2, x2, x3 - 73a4: f9000422 str x2, [x1,#8] - 73a8: 52800002 mov w2, #0x0 // #0 - 73ac: 885f7c01 ldxr w1, [x0] - 73b0: 8803fc02 stlxr w3, w2, [x0] - 73b4: 35ffffc3 cbnz w3, 73ac - 73b8: 7100043f cmp w1, #0x1 - 73bc: 540043ac b.gt 7c30 - 73c0: f9437a77 ldr x23, [x19,#1776] - 73c4: d2800016 mov x22, #0x0 // #0 - 73c8: f9424e60 ldr x0, [x19,#1176] - 73cc: b9010a7f str wzr, [x19,#264] - 73d0: 910042f5 add x21, x23, #0x10 - 73d4: f9007e76 str x22, [x19,#248] - 73d8: f9023276 str x22, [x19,#1120] - 73dc: 9e670009 fmov d9, x0 - 73e0: f9424a60 ldr x0, [x19,#1168] - 73e4: f85f02e5 ldr x5, [x23,#-16] - 73e8: eb0502df cmp x22, x5 - 73ec: 9e67000a fmov d10, x0 - 73f0: 54000182 b.cs 7420 - 73f4: 394022a4 ldrb w4, [x21,#8] - 73f8: 910006d6 add x22, x22, #0x1 - 73fc: 350000c4 cbnz w4, 7414 - 7400: f94002a0 ldr x0, [x21] - 7404: b100041f cmn x0, #0x1 - 7408: 54000060 b.eq 7414 - 740c: 97fff785 bl 5220 - 7410: f85f02e5 ldr x5, [x23,#-16] - 7414: eb0502df cmp x22, x5 - 7418: 910042b5 add x21, x21, #0x10 - 741c: 54fffec3 b.cc 73f4 - 7420: 910004a2 add x2, x5, #0x1 - 7424: aa1703e0 mov x0, x23 - 7428: d53bd043 mrs x3, tpidr_el0 - 742c: 52800001 mov w1, #0x0 // #0 - 7430: d37cec42 lsl x2, x2, #4 - 7434: 911bc275 add x21, x19, #0x6f0 - 7438: aa0303f7 mov x23, x3 - 743c: aa1503f6 mov x22, x21 - 7440: 97fff714 bl 5090 - 7444: aa1503e0 mov x0, x21 - 7448: 97fff7ca bl 5370 <_dl_allocate_tls_init@plt> - 744c: f9425261 ldr x1, [x19,#1184] - 7450: eb01033f cmp x25, x1 - 7454: 540037e8 b.hi 7b50 - 7458: 9e660120 fmov x0, d9 - 745c: cb190021 sub x1, x1, x25 - 7460: cb1c0009 sub x9, x0, x28 - 7464: eb09003f cmp x1, x9 - 7468: 54003d28 b.hi 7c0c - 746c: f9025679 str x25, [x19,#1192] - 7470: d11bc2f5 sub x21, x23, #0x6f0 - 7474: b9400b03 ldr w3, [x24,#8] - 7478: 911122a4 add x4, x21, #0x448 - 747c: b9410ea1 ldr w1, [x21,#268] - 7480: 91038262 add x2, x19, #0xe0 - 7484: 12000065 and w5, w3, #0x1 - 7488: 12197460 and w0, w3, #0xffffff9f - 748c: 6b1f00bf cmp w5, wzr - 7490: 121b0421 and w1, w1, #0x60 - 7494: 91112265 add x5, x19, #0x448 - 7498: 2a000021 orr w1, w1, w0 - 749c: 928003e0 mov x0, #0xffffffffffffffe0 // #-32 - 74a0: b94436a6 ldr w6, [x21,#1076] - 74a4: a9402488 ldp x8, x9, [x4] - 74a8: f9006e62 str x2, [x19,#216] - 74ac: f9007262 str x2, [x19,#224] - 74b0: d11bc262 sub x2, x19, #0x6f0 - 74b4: f9007660 str x0, [x19,#232] - 74b8: 9a9f1260 csel x0, x19, xzr, ne - 74bc: b9041a7f str wzr, [x19,#1048] - 74c0: f9021260 str x0, [x19,#1056] - 74c4: f9007a7f str xzr, [x19,#240] - 74c8: f9021e7b str x27, [x19,#1080] - 74cc: fd02226c str d12, [x19,#1088] - 74d0: b9010e61 str w1, [x19,#268] - 74d4: a90024a8 stp x8, x9, [x5] - 74d8: f9422ea0 ldr x0, [x21,#1112] - 74dc: f9022e60 str x0, [x19,#1112] - 74e0: b94432a0 ldr w0, [x21,#1072] - 74e4: b9043260 str w0, [x19,#1072] - 74e8: b9043666 str w6, [x19,#1076] - 74ec: 37082923 tbnz w3, #1, 7a10 - 74f0: 9e660161 fmov x1, d11 - 74f4: 395046a0 ldrb w0, [x21,#1041] - 74f8: f9000033 str x19, [x1] - 74fc: 35002e20 cbnz w0, 7ac0 - 7500: f9401703 ldr x3, [x24,#40] - 7504: b4002703 cbz x3, 79e4 - 7508: b9410aa0 ldr w0, [x21,#264] - 750c: 52800021 mov w1, #0x1 // #1 - 7510: b9041660 str w0, [x19,#1044] - 7514: 52800023 mov w3, #0x1 // #1 - 7518: 39104e61 strb w1, [x19,#1043] - 751c: aa1303e0 mov x0, x19 - 7520: aa1803e1 mov x1, x24 - 7524: 97fffa4e bl 5e5c - 7528: 2a0003f5 mov w21, w0 - 752c: 34000300 cbz w0, 758c - 7530: 1e260100 fmov w0, s8 - 7534: 350003e0 cbnz w0, 75b0 - 7538: 910003bf mov sp, x29 - 753c: 2a1503e0 mov w0, w21 - 7540: 6d4627e8 ldp d8, d9, [sp,#96] - 7544: a94153f3 ldp x19, x20, [sp,#16] - 7548: 6d472fea ldp d10, d11, [sp,#112] - 754c: a9425bf5 ldp x21, x22, [sp,#32] - 7550: 6d4837ec ldp d12, d13, [sp,#128] - 7554: a94363f7 ldp x23, x24, [sp,#48] - 7558: a9446bf9 ldp x25, x26, [sp,#64] - 755c: a94573fb ldp x27, x28, [sp,#80] - 7560: a8cf7bfd ldp x29, x30, [sp],#240 - 7564: d65f03c0 ret - 7568: f9004fac str x12, [x29,#152] - 756c: f90053aa str x10, [x29,#160] - 7570: f90057ab str x11, [x29,#168] - 7574: b900b3a2 str w2, [x29,#176] - 7578: 9400207c bl f768 <__lll_lock_wait_private> - 757c: f9404fac ldr x12, [x29,#152] - 7580: f94053aa ldr x10, [x29,#160] - 7584: f94057ab ldr x11, [x29,#168] - 7588: 17ffff4d b 72bc - 758c: 91106260 add x0, x19, #0x418 - 7590: 885f7c01 ldxr w1, [x0] - 7594: 8802fc15 stlxr w2, w21, [x0] - 7598: 35ffffc2 cbnz w2, 7590 - 759c: 7100043f cmp w1, #0x1 - 75a0: 5400386c b.gt 7cac - 75a4: 1e260100 fmov w0, s8 - 75a8: 52800015 mov w21, #0x0 // #0 - 75ac: 34fffc60 cbz w0, 7538 - 75b0: f94073a0 ldr x0, [x29,#224] - 75b4: 97fff71b bl 5220 - 75b8: 17ffffe0 b 7538 - 75bc: b900b3b4 str w20, [x29,#176] - 75c0: b0000174 adrp x20, 34000 <__GI___pthread_keys+0x3d78> - 75c4: 910a2280 add x0, x20, #0x288 - 75c8: 52800022 mov w2, #0x1 // #1 - 75cc: 885ffc01 ldaxr w1, [x0] - 75d0: 6b1f003f cmp w1, wzr - 75d4: 54000061 b.ne 75e0 - 75d8: 88037c02 stxr w3, w2, [x0] - 75dc: 35ffff83 cbnz w3, 75cc - 75e0: 540002e1 b.ne 763c - 75e4: b0000161 adrp x1, 34000 <__GI___pthread_keys+0x3d78> - 75e8: 910a2280 add x0, x20, #0x288 - 75ec: 52800002 mov w2, #0x0 // #0 - 75f0: f941a834 ldr x20, [x1,#848] - 75f4: 885f7c01 ldxr w1, [x0] - 75f8: 8803fc02 stlxr w3, w2, [x0] - 75fc: 35ffffc3 cbnz w3, 75f4 - 7600: 7100043f cmp w1, #0x1 - 7604: 5400348c b.gt 7c94 - 7608: b9400b00 ldr w0, [x24,#8] - 760c: 361fe0e0 tbz w0, #3, 7228 - 7610: f9401300 ldr x0, [x24,#32] - 7614: b40001a0 cbz x0, 7648 - 7618: b0000161 adrp x1, 34000 <__GI___pthread_keys+0x3d78> - 761c: f9419033 ldr x19, [x1,#800] - 7620: 91200261 add x1, x19, #0x800 - 7624: eb00003f cmp x1, x0 - 7628: 54000149 b.ls 7650 - 762c: 528002d5 mov w21, #0x16 // #22 - 7630: 17ffffc0 b 7530 - 7634: aa0503f3 mov x19, x5 - 7638: 17ffff28 b 72d8 - 763c: b900b3a1 str w1, [x29,#176] - 7640: 9400204a bl f768 <__lll_lock_wait_private> - 7644: 17ffffe8 b 75e4 - 7648: b0000160 adrp x0, 34000 <__GI___pthread_keys+0x3d78> - 764c: f9419013 ldr x19, [x0,#800] - 7650: f9400f00 ldr x0, [x24,#24] - 7654: 52800001 mov w1, #0x0 // #0 - 7658: d280de02 mov x2, #0x6f0 // #1776 - 765c: 52800036 mov w22, #0x1 // #1 - 7660: cb130013 sub x19, x0, x19 - 7664: b0000160 adrp x0, 34000 <__GI___pthread_keys+0x3d78> - 7668: d53bd059 mrs x25, tpidr_el0 - 766c: d11bc335 sub x21, x25, #0x6f0 - 7670: f9418c00 ldr x0, [x0,#792] - 7674: 8a200273 bic x19, x19, x0 - 7678: d11bc273 sub x19, x19, #0x6f0 - 767c: aa1303e0 mov x0, x19 - 7680: 97fff684 bl 5090 - 7684: 91044261 add x1, x19, #0x110 - 7688: f9400f00 ldr x0, [x24,#24] - 768c: f9018a61 str x1, [x19,#784] - 7690: b0000161 adrp x1, 34000 <__GI___pthread_keys+0x3d78> - 7694: b9000276 str w22, [x19] - 7698: cb140000 sub x0, x0, x20 - 769c: f9024e74 str x20, [x19,#1176] - 76a0: 52800022 mov w2, #0x1 // #1 - 76a4: f941b821 ldr x1, [x1,#880] - 76a8: f9024a60 str x0, [x19,#1168] - 76ac: 911bc260 add x0, x19, #0x6f0 - 76b0: 39104a62 strb w2, [x19,#1042] - 76b4: b9000036 str w22, [x1] - 76b8: b0000161 adrp x1, 34000 <__GI___pthread_keys+0x3d78> - 76bc: b9032836 str w22, [x1,#808] - 76c0: b940d6a1 ldr w1, [x21,#212] - 76c4: b900d661 str w1, [x19,#212] - 76c8: 12800001 mov w1, #0xffffffff // #-1 - 76cc: b9041e61 str w1, [x19,#1052] - 76d0: 97fff710 bl 5310 <_dl_allocate_tls@plt> - 76d4: b4002d80 cbz x0, 7c84 - 76d8: b0000174 adrp x20, 34000 <__GI___pthread_keys+0x3d78> - 76dc: b900b3bf str wzr, [x29,#176] - 76e0: 910a4280 add x0, x20, #0x290 - 76e4: 91004000 add x0, x0, #0x10 - 76e8: 885ffc01 ldaxr w1, [x0] - 76ec: 6b1f003f cmp w1, wzr - 76f0: 54000061 b.ne 76fc - 76f4: 88027c16 stxr w2, w22, [x0] - 76f8: 35ffff82 cbnz w2, 76e8 - 76fc: 54002b81 b.ne 7c6c - 7700: 910a4281 add x1, x20, #0x290 - 7704: 91030262 add x2, x19, #0xc0 - 7708: 91006020 add x0, x1, #0x18 - 770c: f9006660 str x0, [x19,#200] - 7710: 91004020 add x0, x1, #0x10 - 7714: f9400c23 ldr x3, [x1,#24] - 7718: f9006263 str x3, [x19,#192] - 771c: f9000462 str x2, [x3,#8] - 7720: d5033bbf dmb ish - 7724: f9000c22 str x2, [x1,#24] - 7728: 52800002 mov w2, #0x0 // #0 - 772c: 885f7c01 ldxr w1, [x0] - 7730: 8803fc02 stlxr w3, w2, [x0] - 7734: 35ffffc3 cbnz w3, 772c - 7738: 7100043f cmp w1, #0x1 - 773c: 54ffe9cd b.le 7474 - 7740: d2801021 mov x1, #0x81 // #129 - 7744: d2800022 mov x2, #0x1 // #1 - 7748: d2800003 mov x3, #0x0 // #0 - 774c: d2800c48 mov x8, #0x62 // #98 - 7750: d4000001 svc #0x0 - 7754: 17ffff48 b 7474 - 7758: 910a4280 add x0, x20, #0x290 - 775c: 52800002 mov w2, #0x0 // #0 - 7760: 91004000 add x0, x0, #0x10 - 7764: 885f7c01 ldxr w1, [x0] - 7768: 8803fc02 stlxr w3, w2, [x0] - 776c: 35ffffc3 cbnz w3, 7764 - 7770: 7100043f cmp w1, #0x1 - 7774: 54002aec b.gt 7cd0 - 7778: 1e2601a2 fmov w2, s13 - 777c: d2800000 mov x0, #0x0 // #0 - 7780: 52800443 mov w3, #0x22 // #34 - 7784: aa1c03e1 mov x1, x28 - 7788: 72a00043 movk w3, #0x2, lsl #16 - 778c: 12800004 mov w4, #0xffffffff // #-1 - 7790: aa0003e5 mov x5, x0 - 7794: f9004fac str x12, [x29,#152] - 7798: f90053aa str x10, [x29,#160] - 779c: f90057ab str x11, [x29,#168] - 77a0: 97fff68c bl 51d0 - 77a4: b100041f cmn x0, #0x1 - 77a8: f94057ab ldr x11, [x29,#168] - 77ac: 9e67000a fmov d10, x0 - 77b0: f94053aa ldr x10, [x29,#160] - 77b4: f9404fac ldr x12, [x29,#152] - 77b8: 54002fe0 b.eq 7db4 - 77bc: 9e660143 fmov x3, d10 - 77c0: f9419160 ldr x0, [x11,#800] - 77c4: f9418d84 ldr x4, [x12,#792] - 77c8: 5280003a mov w26, #0x1 // #1 - 77cc: cb000380 sub x0, x28, x0 - 77d0: d53bd041 mrs x1, tpidr_el0 - 77d4: d11bc022 sub x2, x1, #0x6f0 - 77d8: f90053aa str x10, [x29,#160] - 77dc: 8b000060 add x0, x3, x0 - 77e0: b0000163 adrp x3, 34000 <__GI___pthread_keys+0x3d78> - 77e4: 8a240004 bic x4, x0, x4 - 77e8: aa0103f7 mov x23, x1 - 77ec: d11bc093 sub x19, x4, #0x6f0 - 77f0: aa0403e0 mov x0, x4 - 77f4: 91044265 add x5, x19, #0x110 - 77f8: f90057a4 str x4, [x29,#168] - 77fc: b900027a str w26, [x19] - 7800: fd024a6a str d10, [x19,#1168] - 7804: f941b863 ldr x3, [x3,#880] - 7808: f9024e7c str x28, [x19,#1176] - 780c: f9018a65 str x5, [x19,#784] - 7810: b900007a str w26, [x3] - 7814: 12800003 mov w3, #0xffffffff // #-1 - 7818: b9041e63 str w3, [x19,#1052] - 781c: b940d442 ldr w2, [x2,#212] - 7820: b900d662 str w2, [x19,#212] - 7824: b0000162 adrp x2, 34000 <__GI___pthread_keys+0x3d78> - 7828: b903285a str w26, [x2,#808] - 782c: 97fff6b9 bl 5310 <_dl_allocate_tls@plt> - 7830: f94057a4 ldr x4, [x29,#168] - 7834: f94053aa ldr x10, [x29,#160] - 7838: b4002b00 cbz x0, 7d98 - 783c: 910a4280 add x0, x20, #0x290 - 7840: b900b3bf str wzr, [x29,#176] - 7844: 91004000 add x0, x0, #0x10 - 7848: 885ffc02 ldaxr w2, [x0] - 784c: 6b1f005f cmp w2, wzr - 7850: 54000061 b.ne 785c - 7854: 88017c1a stxr w1, w26, [x0] - 7858: 35ffff81 cbnz w1, 7848 - 785c: 54001fa1 b.ne 7c50 - 7860: 910962d6 add x22, x22, #0x258 - 7864: 9103027a add x26, x19, #0xc0 - 7868: aa1603e1 mov x1, x22 - 786c: b2400340 orr x0, x26, #0x1 - 7870: f9014a80 str x0, [x20,#656] - 7874: 910a4280 add x0, x20, #0x290 - 7878: 91004000 add x0, x0, #0x10 - 787c: d5033bbf dmb ish - 7880: f8410c22 ldr x2, [x1,#16]! - 7884: f9006262 str x2, [x19,#192] - 7888: f9006661 str x1, [x19,#200] - 788c: f900045a str x26, [x2,#8] - 7890: 52800002 mov w2, #0x0 // #0 - 7894: d5033bbf dmb ish - 7898: f9000ada str x26, [x22,#16] - 789c: d5033bbf dmb ish - 78a0: f9014a9f str xzr, [x20,#656] - 78a4: 885f7c01 ldxr w1, [x0] - 78a8: 8803fc02 stlxr w3, w2, [x0] - 78ac: 35ffffc3 cbnz w3, 78a4 - 78b0: 7100043f cmp w1, #0x1 - 78b4: 540025ac b.gt 7d68 - 78b8: f947ed4a ldr x10, [x10,#4056] - 78bc: aa0403f6 mov x22, x4 - 78c0: 9e670389 fmov d9, x28 - 78c4: b94fa140 ldr w0, [x10,#4000] - 78c8: 3607dc20 tbz w0, #0, 744c - 78cc: 35ffdc15 cbnz w21, 744c - 78d0: f9425261 ldr x1, [x19,#1184] - 78d4: 528000e2 mov w2, #0x7 // #7 - 78d8: f9424a60 ldr x0, [x19,#1168] - 78dc: f9424e63 ldr x3, [x19,#1176] - 78e0: 8b010000 add x0, x0, x1 - 78e4: cb010061 sub x1, x3, x1 - 78e8: 97fff6b2 bl 53b0 - 78ec: 340022e0 cbz w0, 7d48 - 78f0: 90000140 adrp x0, 2f000 <__FRAME_END__+0x18e30> - 78f4: f947c400 ldr x0, [x0,#3976] - 78f8: b8606af5 ldr w21, [x23,x0] - 78fc: 34ffda95 cbz w21, 744c - 7900: 9e660140 fmov x0, d10 - 7904: aa1c03e1 mov x1, x28 - 7908: 97fff66a bl 52b0 - 790c: 710032bf cmp w21, #0xc - 7910: 52800160 mov w0, #0xb // #11 - 7914: 1a8012b5 csel w21, w21, w0, ne - 7918: 17ffff06 b 7530 - 791c: b0000174 adrp x20, 34000 <__GI___pthread_keys+0x3d78> - 7920: b900bba1 str w1, [x29,#184] - 7924: 910a2280 add x0, x20, #0x288 - 7928: 52800022 mov w2, #0x1 // #1 - 792c: 885ffc01 ldaxr w1, [x0] - 7930: 6b1f003f cmp w1, wzr - 7934: 54000061 b.ne 7940 - 7938: 88037c02 stxr w3, w2, [x0] - 793c: 35ffff83 cbnz w3, 792c - 7940: 54000060 b.eq 794c - 7944: b900bba1 str w1, [x29,#184] - 7948: 94001f88 bl f768 <__lll_lock_wait_private> - 794c: b0000160 adrp x0, 34000 <__GI___pthread_keys+0x3d78> - 7950: 9102e3b8 add x24, x29, #0xb8 - 7954: 910cc000 add x0, x0, #0x330 - 7958: a9401404 ldp x4, x5, [x0] - 795c: a9410c02 ldp x2, x3, [x0,#16] - 7960: f9401813 ldr x19, [x0,#48] - 7964: a9420400 ldp x0, x1, [x0,#32] - 7968: f90077b3 str x19, [x29,#232] - 796c: a9001704 stp x4, x5, [x24] - 7970: a9010f02 stp x2, x3, [x24,#16] - 7974: a9020700 stp x0, x1, [x24,#32] - 7978: b4001693 cbz x19, 7c48 - 797c: f140227f cmp x19, #0x8, lsl #12 - 7980: 54001b48 b.hi 7ce8 - 7984: 91007a60 add x0, x19, #0x1e - 7988: 910003e1 mov x1, sp - 798c: 927cec00 and x0, x0, #0xfffffffffffffff0 - 7990: 1e2703e8 fmov s8, wzr - 7994: cb20603f sub sp, x1, x0 - 7998: 910003e3 mov x3, sp - 799c: f94073a1 ldr x1, [x29,#224] - 79a0: aa0303e0 mov x0, x3 - 79a4: aa1303e2 mov x2, x19 - 79a8: 97fff56e bl 4f60 - 79ac: f90073a0 str x0, [x29,#224] - 79b0: 910a2280 add x0, x20, #0x288 - 79b4: 52800002 mov w2, #0x0 // #0 - 79b8: 885f7c01 ldxr w1, [x0] - 79bc: 8803fc02 stlxr w3, w2, [x0] - 79c0: 35ffffc3 cbnz w3, 79b8 - 79c4: 7100043f cmp w1, #0x1 - 79c8: 54ffc22d b.le 720c - 79cc: d2801021 mov x1, #0x81 // #129 - 79d0: d2800022 mov x2, #0x1 // #1 - 79d4: d2800003 mov x3, #0x0 // #0 - 79d8: d2800c48 mov x8, #0x62 // #98 - 79dc: d4000001 svc #0x0 - 79e0: 17fffe0b b 720c - 79e4: b9400b00 ldr w0, [x24,#8] - 79e8: 121f0001 and w1, w0, #0x2 - 79ec: 370fd8e0 tbnz w0, #1, 7508 - 79f0: b9410aa4 ldr w4, [x21,#264] - 79f4: aa1303e0 mov x0, x19 - 79f8: 39104e61 strb w1, [x19,#1043] - 79fc: aa1803e1 mov x1, x24 - 7a00: b9041664 str w4, [x19,#1044] - 7a04: 97fff916 bl 5e5c - 7a08: 2a0003f5 mov w21, w0 - 7a0c: 17fffec9 b 7530 - 7a10: 721b047f tst w3, #0x60 - 7a14: 54ffd6e0 b.eq 74f0 - 7a18: 37301303 tbnz w3, #6, 7c78 - 7a1c: 37300121 tbnz w1, #6, 7a40 - 7a20: d2800000 mov x0, #0x0 // #0 - 7a24: d2800f08 mov x8, #0x78 // #120 - 7a28: d4000001 svc #0x0 - 7a2c: b9410e61 ldr w1, [x19,#268] - 7a30: b9400b03 ldr w3, [x24,#8] - 7a34: 321a0021 orr w1, w1, #0x40 - 7a38: b9043660 str w0, [x19,#1076] - 7a3c: b9010e61 str w1, [x19,#268] - 7a40: 37281423 tbnz w3, #5, 7cc4 - 7a44: 37280101 tbnz w1, #5, 7a64 - 7a48: d2800000 mov x0, #0x0 // #0 - 7a4c: 9110c261 add x1, x19, #0x430 - 7a50: d2800f28 mov x8, #0x79 // #121 - 7a54: d4000001 svc #0x0 - 7a58: b9410e60 ldr w0, [x19,#268] - 7a5c: 321b0000 orr w0, w0, #0x20 - 7a60: b9010e60 str w0, [x19,#268] - 7a64: b9800700 ldrsw x0, [x24,#4] - 7a68: d2800fc8 mov x8, #0x7e // #126 - 7a6c: d4000001 svc #0x0 - 7a70: d2800fa8 mov x8, #0x7d // #125 - 7a74: aa0003e3 mov x3, x0 - 7a78: b9800700 ldrsw x0, [x24,#4] - 7a7c: d4000001 svc #0x0 - 7a80: b9443261 ldr w1, [x19,#1072] - 7a84: 6b03003f cmp w1, w3 - 7a88: 5400006b b.lt 7a94 - 7a8c: 6b00003f cmp w1, w0 - 7a90: 54ffd30d b.le 74f0 - 7a94: 91107260 add x0, x19, #0x41c - 7a98: 52800002 mov w2, #0x0 // #0 - 7a9c: 885ffc01 ldaxr w1, [x0] - 7aa0: 88037c02 stxr w3, w2, [x0] - 7aa4: 35ffffc3 cbnz w3, 7a9c - 7aa8: 3100083f cmn w1, #0x2 - 7aac: 54001520 b.eq 7d50 - 7ab0: aa1303e0 mov x0, x19 - 7ab4: 528002d5 mov w21, #0x16 // #22 - 7ab8: 97fff86f bl 5c74 <__deallocate_stack> - 7abc: 17fffe9d b 7530 - 7ac0: 910a4294 add x20, x20, #0x290 - 7ac4: b9444a61 ldr w1, [x19,#1096] - 7ac8: b9402a80 ldr w0, [x20,#40] - 7acc: 2a000020 orr w0, w1, w0 - 7ad0: 363fd180 tbz w0, #7, 7500 - 7ad4: 52800021 mov w1, #0x1 // #1 - 7ad8: aa1303e0 mov x0, x19 - 7adc: 39104e61 strb w1, [x19,#1043] - 7ae0: 52800023 mov w3, #0x1 // #1 - 7ae4: aa1803e1 mov x1, x24 - 7ae8: 97fff8dd bl 5e5c - 7aec: 2a0003f5 mov w21, w0 - 7af0: 35ffd200 cbnz w0, 7530 - 7af4: 52800100 mov w0, #0x8 // #8 - 7af8: f9022e73 str x19, [x19,#1112] - 7afc: b9045260 str w0, [x19,#1104] - 7b00: aa1403e3 mov x3, x20 - 7b04: aa0303e2 mov x2, x3 - 7b08: f8430c41 ldr x1, [x2,#48]! - 7b0c: f9023261 str x1, [x19,#1120] - 7b10: f9005ba1 str x1, [x29,#176] - 7b14: c85ffc44 ldaxr x4, [x2] - 7b18: eb01009f cmp x4, x1 - 7b1c: 54000061 b.ne 7b28 - 7b20: c8007c53 stxr w0, x19, [x2] - 7b24: 35ffff80 cbnz w0, 7b14 - 7b28: 54fffee1 b.ne 7b04 - 7b2c: 97fff7d6 bl 5a84 <__GI___nptl_create_event> - 7b30: 91106260 add x0, x19, #0x418 - 7b34: 52800002 mov w2, #0x0 // #0 - 7b38: 885f7c01 ldxr w1, [x0] - 7b3c: 8803fc02 stlxr w3, w2, [x0] - 7b40: 34ffd2e3 cbz w3, 759c - 7b44: 17fffffd b 7b38 - 7b48: aa0503f3 mov x19, x5 - 7b4c: 17fffdf5 b 7320 - 7b50: 9e660140 fmov x0, d10 - 7b54: aa1903e1 mov x1, x25 - 7b58: 52800002 mov w2, #0x0 // #0 - 7b5c: 97fff615 bl 53b0 - 7b60: 34000600 cbz w0, 7c20 - 7b64: 910a4280 add x0, x20, #0x290 - 7b68: b900b3bf str wzr, [x29,#176] - 7b6c: 91004000 add x0, x0, #0x10 - 7b70: 52800022 mov w2, #0x1 // #1 - 7b74: 885ffc01 ldaxr w1, [x0] - 7b78: 6b1f003f cmp w1, wzr - 7b7c: 54000061 b.ne 7b88 - 7b80: 88037c02 stxr w3, w2, [x0] - 7b84: 35ffff83 cbnz w3, 7b74 - 7b88: 54000060 b.eq 7b94 - 7b8c: b900b3a1 str w1, [x29,#176] - 7b90: 94001ef6 bl f768 <__lll_lock_wait_private> - 7b94: f9014a9a str x26, [x20,#656] - 7b98: 910a4280 add x0, x20, #0x290 - 7b9c: 91004000 add x0, x0, #0x10 - 7ba0: d5033bbf dmb ish - 7ba4: f9406261 ldr x1, [x19,#192] - 7ba8: f9406662 ldr x2, [x19,#200] - 7bac: f9000422 str x2, [x1,#8] - 7bb0: f9406662 ldr x2, [x19,#200] - 7bb4: f9000041 str x1, [x2] - 7bb8: 52800002 mov w2, #0x0 // #0 - 7bbc: d5033bbf dmb ish - 7bc0: f9014a9f str xzr, [x20,#656] - 7bc4: 885f7c01 ldxr w1, [x0] - 7bc8: 8803fc02 stlxr w3, w2, [x0] - 7bcc: 35ffffc3 cbnz w3, 7bc4 - 7bd0: 7100043f cmp w1, #0x1 - 7bd4: 54000d6c b.gt 7d80 - 7bd8: aa1603e0 mov x0, x22 - 7bdc: 52800001 mov w1, #0x0 // #0 - 7be0: 97fff540 bl 50e0 <_dl_deallocate_tls@plt> - 7be4: 9e660140 fmov x0, d10 - 7be8: 9e660121 fmov x1, d9 - 7bec: 97fff5b1 bl 52b0 - 7bf0: 90000140 adrp x0, 2f000 <__FRAME_END__+0x18e30> - 7bf4: f947c400 ldr x0, [x0,#3976] - 7bf8: b8606af5 ldr w21, [x23,x0] - 7bfc: 35ffe895 cbnz w21, 790c - 7c00: d2800000 mov x0, #0x0 // #0 - 7c04: f9021c1b str x27, [x0,#1080] - 7c08: d4207d00 brk #0x3e8 - 7c0c: 9e660140 fmov x0, d10 - 7c10: 1e2601a2 fmov w2, s13 - 7c14: 8b190000 add x0, x0, x25 - 7c18: 97fff5e6 bl 53b0 - 7c1c: 35fffa40 cbnz w0, 7b64 - 7c20: f9025279 str x25, [x19,#1184] - 7c24: 17fffe12 b 746c - 7c28: aa1403e0 mov x0, x20 - 7c2c: 17fffe7b b 7618 - 7c30: d2801021 mov x1, #0x81 // #129 - 7c34: d2800022 mov x2, #0x1 // #1 - 7c38: d2800003 mov x3, #0x0 // #0 - 7c3c: d2800c48 mov x8, #0x62 // #98 - 7c40: d4000001 svc #0x0 - 7c44: 17fffddf b 73c0 - 7c48: 1e270268 fmov s8, w19 - 7c4c: 17ffff59 b 79b0 - 7c50: f90053aa str x10, [x29,#160] - 7c54: f90057a4 str x4, [x29,#168] - 7c58: b900b3a2 str w2, [x29,#176] - 7c5c: 94001ec3 bl f768 <__lll_lock_wait_private> - 7c60: f94053aa ldr x10, [x29,#160] - 7c64: f94057a4 ldr x4, [x29,#168] - 7c68: 17fffefe b 7860 - 7c6c: b900b3a1 str w1, [x29,#176] - 7c70: 94001ebe bl f768 <__lll_lock_wait_private> - 7c74: 17fffea3 b 7700 - 7c78: b9400700 ldr w0, [x24,#4] - 7c7c: b9043660 str w0, [x19,#1076] - 7c80: 17ffff70 b 7a40 - 7c84: 90000140 adrp x0, 2f000 <__FRAME_END__+0x18e30> - 7c88: f947c400 ldr x0, [x0,#3976] - 7c8c: b8606b35 ldr w21, [x25,x0] - 7c90: 17ffffdb b 7bfc - 7c94: d2801021 mov x1, #0x81 // #129 - 7c98: d2800022 mov x2, #0x1 // #1 - 7c9c: d2800003 mov x3, #0x0 // #0 - 7ca0: d2800c48 mov x8, #0x62 // #98 - 7ca4: d4000001 svc #0x0 - 7ca8: 17fffe58 b 7608 - 7cac: d2801021 mov x1, #0x81 // #129 - 7cb0: d2800022 mov x2, #0x1 // #1 - 7cb4: d2800003 mov x3, #0x0 // #0 - 7cb8: d2800c48 mov x8, #0x62 // #98 - 7cbc: d4000001 svc #0x0 - 7cc0: 17fffe1c b 7530 - 7cc4: b9400300 ldr w0, [x24] - 7cc8: b9043260 str w0, [x19,#1072] - 7ccc: 17ffff66 b 7a64 - 7cd0: d2801021 mov x1, #0x81 // #129 - 7cd4: d2800022 mov x2, #0x1 // #1 - 7cd8: d2800003 mov x3, #0x0 // #0 - 7cdc: d2800c48 mov x8, #0x62 // #98 - 7ce0: d4000001 svc #0x0 - 7ce4: 17fffea5 b 7778 - 7ce8: aa1303e0 mov x0, x19 - 7cec: 97fff59d bl 5360 <__libc_alloca_cutoff@plt> - 7cf0: 2a0003f5 mov w21, w0 - 7cf4: 35ffe480 cbnz w0, 7984 - 7cf8: aa1303e0 mov x0, x19 - 7cfc: 97fff4e1 bl 5080 - 7d00: aa0003e3 mov x3, x0 - 7d04: b4000080 cbz x0, 7d14 - 7d08: 52800020 mov w0, #0x1 // #1 - 7d0c: 1e270008 fmov s8, w0 - 7d10: 17ffff23 b 799c - 7d14: 910a2294 add x20, x20, #0x288 - 7d18: 885f7e80 ldxr w0, [x20] - 7d1c: 8801fe95 stlxr w1, w21, [x20] - 7d20: 35ffffc1 cbnz w1, 7d18 - 7d24: 7100041f cmp w0, #0x1 - 7d28: 52800195 mov w21, #0xc // #12 - 7d2c: 54ffc06d b.le 7538 - 7d30: aa1403e0 mov x0, x20 - 7d34: d2801021 mov x1, #0x81 // #129 - 7d38: d2800022 mov x2, #0x1 // #1 - 7d3c: d2800c48 mov x8, #0x62 // #98 - 7d40: d4000001 svc #0x0 - 7d44: 17fffdfd b 7538 - 7d48: 9e670389 fmov d9, x28 - 7d4c: 17fffdc0 b 744c - 7d50: d2801021 mov x1, #0x81 // #129 - 7d54: d2800022 mov x2, #0x1 // #1 - 7d58: d2800003 mov x3, #0x0 // #0 - 7d5c: d2800c48 mov x8, #0x62 // #98 - 7d60: d4000001 svc #0x0 - 7d64: 17ffff53 b 7ab0 - 7d68: d2801021 mov x1, #0x81 // #129 - 7d6c: d2800022 mov x2, #0x1 // #1 - 7d70: d2800003 mov x3, #0x0 // #0 - 7d74: d2800c48 mov x8, #0x62 // #98 - 7d78: d4000001 svc #0x0 - 7d7c: 17fffecf b 78b8 - 7d80: d2801021 mov x1, #0x81 // #129 - 7d84: d2800022 mov x2, #0x1 // #1 - 7d88: d2800003 mov x3, #0x0 // #0 - 7d8c: d2800c48 mov x8, #0x62 // #98 - 7d90: d4000001 svc #0x0 - 7d94: 17ffff91 b 7bd8 - 7d98: 9e660140 fmov x0, d10 - 7d9c: aa1c03e1 mov x1, x28 - 7da0: 97fff544 bl 52b0 - 7da4: 90000140 adrp x0, 2f000 <__FRAME_END__+0x18e30> - 7da8: f947c400 ldr x0, [x0,#3976] - 7dac: b8606af5 ldr w21, [x23,x0] - 7db0: 17ffff93 b 7bfc - 7db4: d53bd040 mrs x0, tpidr_el0 - 7db8: 90000141 adrp x1, 2f000 <__FRAME_END__+0x18e30> - 7dbc: f947c421 ldr x1, [x1,#3976] - 7dc0: b8616815 ldr w21, [x0,x1] - 7dc4: 17ffff8e b 7bfc - -0000000000007dc8 : - 7dc8: d53bd041 mrs x1, tpidr_el0 - 7dcc: a9be7bfd stp x29, x30, [sp,#-32]! - 7dd0: d11bc022 sub x2, x1, #0x6f0 - 7dd4: d117a021 sub x1, x1, #0x5e8 - 7dd8: 910003fd mov x29, sp - 7ddc: 910073a6 add x6, x29, #0x1c - 7de0: 91042043 add x3, x2, #0x108 - 7de4: f9021440 str x0, [x2,#1064] - 7de8: b9400020 ldr w0, [x1] - 7dec: b9001fa0 str w0, [x29,#28] - 7df0: 321c0004 orr w4, w0, #0x10 - 7df4: 885ffc65 ldaxr w5, [x3] - 7df8: 6b0000bf cmp w5, w0 - 7dfc: 54000061 b.ne 7e08 - 7e00: 88077c64 stxr w7, w4, [x3] - 7e04: 35ffff87 cbnz w7, 7df4 - 7e08: 54000060 b.eq 7e14 - 7e0c: b90000c5 str w5, [x6] - 7e10: 17fffff6 b 7de8 - 7e14: f9408040 ldr x0, [x2,#256] - 7e18: 94001dbb bl f504 <__pthread_unwind> - -0000000000007e1c : - 7e1c: a9be7bfd stp x29, x30, [sp,#-32]! - 7e20: aa0003e1 mov x1, x0 - 7e24: 910003fd mov x29, sp - 7e28: b940d002 ldr w2, [x0,#208] - 7e2c: 37f802c2 tbnz w2, #31, 7e84 - 7e30: f9000fbf str xzr, [x29,#24] - 7e34: 91108002 add x2, x0, #0x420 - 7e38: c85ffc43 ldaxr x3, [x2] - 7e3c: eb1f007f cmp x3, xzr - 7e40: 54000061 b.ne 7e4c - 7e44: c8047c41 stxr w4, x1, [x2] - 7e48: 35ffff84 cbnz w4, 7e38 - 7e4c: 540000e1 b.ne 7e68 - 7e50: b9410822 ldr w2, [x1,#264] - 7e54: 121c0041 and w1, w2, #0x10 - 7e58: 36200102 tbz w2, #4, 7e78 - 7e5c: 97fffbf2 bl 6e24 <__free_tcb> - 7e60: 52800001 mov w1, #0x0 // #0 - 7e64: 14000005 b 7e78 - 7e68: f9421020 ldr x0, [x1,#1056] - 7e6c: eb01001f cmp x0, x1 - 7e70: 528002c1 mov w1, #0x16 // #22 - 7e74: 1a8113e1 csel w1, wzr, w1, ne - 7e78: 2a0103e0 mov w0, w1 - 7e7c: a8c27bfd ldp x29, x30, [sp],#32 - 7e80: d65f03c0 ret - 7e84: 52800061 mov w1, #0x3 // #3 - 7e88: 2a0103e0 mov w0, w1 - 7e8c: a8c27bfd ldp x29, x30, [sp],#32 - 7e90: d65f03c0 ret - -0000000000007e94 : - 7e94: d10043ff sub sp, sp, #0x10 - 7e98: d53bd041 mrs x1, tpidr_el0 - 7e9c: d11bc021 sub x1, x1, #0x6f0 - 7ea0: d2800002 mov x2, #0x0 // #0 - 7ea4: f90007e1 str x1, [sp,#8] - 7ea8: c85ffc03 ldaxr x3, [x0] - 7eac: eb01007f cmp x3, x1 - 7eb0: 54000061 b.ne 7ebc - 7eb4: c8047c02 stxr w4, x2, [x0] - 7eb8: 35ffff84 cbnz w4, 7ea8 - 7ebc: 910043ff add sp, sp, #0x10 - 7ec0: d65f03c0 ret - -0000000000007ec4 : - 7ec4: a9b97bfd stp x29, x30, [sp,#-112]! - 7ec8: 910003fd mov x29, sp - 7ecc: a90153f3 stp x19, x20, [sp,#16] - 7ed0: aa0003f3 mov x19, x0 - 7ed4: b940d000 ldr w0, [x0,#208] - 7ed8: a9025bf5 stp x21, x22, [sp,#32] - 7edc: a90363f7 stp x23, x24, [sp,#48] - 7ee0: 37f80a20 tbnz w0, #31, 8024 - 7ee4: f9421262 ldr x2, [x19,#1056] - 7ee8: 528002c0 mov w0, #0x16 // #22 - 7eec: eb13005f cmp x2, x19 - 7ef0: 54000420 b.eq 7f74 - 7ef4: aa0103f7 mov x23, x1 - 7ef8: 91108276 add x22, x19, #0x420 - 7efc: 910143b8 add x24, x29, #0x50 - 7f00: 90000001 adrp x1, 7000 - 7f04: aa1803e0 mov x0, x24 - 7f08: 913a5021 add x1, x1, #0xe94 - 7f0c: aa1603e2 mov x2, x22 - 7f10: d53bd055 mrs x21, tpidr_el0 - 7f14: d11bc2b5 sub x21, x21, #0x6f0 - 7f18: 94001cba bl f200 <_pthread_cleanup_push> - 7f1c: 94001dbf bl f618 <__pthread_enable_asynccancel> - 7f20: 2a0003e5 mov w5, w0 - 7f24: eb15027f cmp x19, x21 - 7f28: 54000700 b.eq 8008 - 7f2c: f94212a0 ldr x0, [x21,#1056] - 7f30: eb13001f cmp x0, x19 - 7f34: 54000640 b.eq 7ffc - 7f38: f90027bf str xzr, [x29,#72] - 7f3c: c85ffec0 ldaxr x0, [x22] - 7f40: eb1f001f cmp x0, xzr - 7f44: 54000061 b.ne 7f50 - 7f48: c8017ed5 stxr w1, x21, [x22] - 7f4c: 35ffff81 cbnz w1, 7f3c - 7f50: 540001c0 b.eq 7f88 - 7f54: f90027a0 str x0, [x29,#72] - 7f58: 528002d4 mov w20, #0x16 // #22 - 7f5c: 2a0503e0 mov w0, w5 - 7f60: 94001dde bl f6d8 <__pthread_disable_asynccancel> - 7f64: aa1803e0 mov x0, x24 - 7f68: 52800001 mov w1, #0x0 // #0 - 7f6c: 94001cad bl f220 <_pthread_cleanup_pop> - 7f70: 2a1403e0 mov w0, w20 - 7f74: a94153f3 ldp x19, x20, [sp,#16] - 7f78: a9425bf5 ldp x21, x22, [sp,#32] - 7f7c: a94363f7 ldp x23, x24, [sp,#48] - 7f80: a8c77bfd ldp x29, x30, [sp],#112 - 7f84: d65f03c0 ret - 7f88: b940d262 ldr w2, [x19,#208] - 7f8c: 34000142 cbz w2, 7fb4 - 7f90: 91034264 add x4, x19, #0xd0 - 7f94: d2800001 mov x1, #0x0 // #0 - 7f98: aa0403e0 mov x0, x4 - 7f9c: 93407c42 sxtw x2, w2 - 7fa0: aa0103e3 mov x3, x1 - 7fa4: d2800c48 mov x8, #0x62 // #98 - 7fa8: d4000001 svc #0x0 - 7fac: b940d262 ldr w2, [x19,#208] - 7fb0: 35ffff22 cbnz w2, 7f94 - 7fb4: 2a0503e0 mov w0, w5 - 7fb8: 94001dc8 bl f6d8 <__pthread_disable_asynccancel> - 7fbc: aa1803e0 mov x0, x24 - 7fc0: 52800001 mov w1, #0x0 // #0 - 7fc4: 94001c97 bl f220 <_pthread_cleanup_pop> - 7fc8: 12800000 mov w0, #0xffffffff // #-1 - 7fcc: b900d260 str w0, [x19,#208] - 7fd0: b4000077 cbz x23, 7fdc - 7fd4: f9421660 ldr x0, [x19,#1064] - 7fd8: f90002e0 str x0, [x23] - 7fdc: aa1303e0 mov x0, x19 - 7fe0: 97fffb91 bl 6e24 <__free_tcb> - 7fe4: 52800000 mov w0, #0x0 // #0 - 7fe8: a94153f3 ldp x19, x20, [sp,#16] - 7fec: a9425bf5 ldp x21, x22, [sp,#32] - 7ff0: a94363f7 ldp x23, x24, [sp,#48] - 7ff4: a8c77bfd ldp x29, x30, [sp],#112 - 7ff8: d65f03c0 ret - 7ffc: b9410a60 ldr w0, [x19,#264] - 8000: 721e0c1f tst w0, #0x3c - 8004: 54fff9a1 b.ne 7f38 - 8008: b9410aa1 ldr w1, [x21,#264] - 800c: 128008c0 mov w0, #0xffffffb9 // #-71 - 8010: 52800474 mov w20, #0x23 // #35 - 8014: 0a000020 and w0, w1, w0 - 8018: 7100201f cmp w0, #0x8 - 801c: 54fffa01 b.ne 7f5c - 8020: 17ffffc6 b 7f38 - 8024: 52800060 mov w0, #0x3 // #3 - 8028: a94153f3 ldp x19, x20, [sp,#16] - 802c: a9425bf5 ldp x21, x22, [sp,#32] - 8030: a94363f7 ldp x23, x24, [sp,#48] - 8034: a8c77bfd ldp x29, x30, [sp],#112 - 8038: d65f03c0 ret - -000000000000803c : - 803c: a9bd7bfd stp x29, x30, [sp,#-48]! - 8040: 910003fd mov x29, sp - 8044: f9421002 ldr x2, [x0,#1056] - 8048: f9000bf3 str x19, [sp,#16] - 804c: eb00005f cmp x2, x0 - 8050: 54000380 b.eq 80c0 - 8054: d53bd042 mrs x2, tpidr_el0 - 8058: d11bc042 sub x2, x2, #0x6f0 - 805c: eb02001f cmp x0, x2 - 8060: 54000160 b.eq 808c - 8064: f9421043 ldr x3, [x2,#1056] - 8068: eb00007f cmp x3, x0 - 806c: 54000100 b.eq 808c - 8070: b940d013 ldr w19, [x0,#208] - 8074: 34000173 cbz w19, 80a0 - 8078: 52800213 mov w19, #0x10 // #16 - 807c: 2a1303e0 mov w0, w19 - 8080: f9400bf3 ldr x19, [sp,#16] - 8084: a8c37bfd ldp x29, x30, [sp],#48 - 8088: d65f03c0 ret - 808c: 52800473 mov w19, #0x23 // #35 - 8090: 2a1303e0 mov w0, w19 - 8094: f9400bf3 ldr x19, [sp,#16] - 8098: a8c37bfd ldp x29, x30, [sp],#48 - 809c: d65f03c0 ret - 80a0: f90017bf str xzr, [x29,#40] - 80a4: 91108003 add x3, x0, #0x420 - 80a8: c85ffc64 ldaxr x4, [x3] - 80ac: eb1f009f cmp x4, xzr - 80b0: 54000061 b.ne 80bc - 80b4: c8057c62 stxr w5, x2, [x3] - 80b8: 35ffff85 cbnz w5, 80a8 - 80bc: 540000c0 b.eq 80d4 - 80c0: 528002d3 mov w19, #0x16 // #22 - 80c4: 2a1303e0 mov w0, w19 - 80c8: f9400bf3 ldr x19, [sp,#16] - 80cc: a8c37bfd ldp x29, x30, [sp],#48 - 80d0: d65f03c0 ret - 80d4: b4000061 cbz x1, 80e0 - 80d8: f9421402 ldr x2, [x0,#1064] - 80dc: f9000022 str x2, [x1] - 80e0: 97fffb51 bl 6e24 <__free_tcb> - 80e4: 17ffffe6 b 807c - -00000000000080e8 : - 80e8: f900001f str xzr, [x0] - 80ec: d65f03c0 ret - -00000000000080f0 : - 80f0: a9b97bfd stp x29, x30, [sp,#-112]! - 80f4: 910003fd mov x29, sp - 80f8: b940d003 ldr w3, [x0,#208] - 80fc: a90153f3 stp x19, x20, [sp,#16] - 8100: a9025bf5 stp x21, x22, [sp,#32] - 8104: f9001bf7 str x23, [sp,#48] - 8108: 37f80a43 tbnz w3, #31, 8250 - 810c: f9421003 ldr x3, [x0,#1056] - 8110: eb00007f cmp x3, x0 - 8114: 54000220 b.eq 8158 - 8118: d53bd043 mrs x3, tpidr_el0 - 811c: d11bc063 sub x3, x3, #0x6f0 - 8120: eb03001f cmp x0, x3 - 8124: 54000640 b.eq 81ec - 8128: f9421065 ldr x5, [x3,#1056] - 812c: 52800464 mov w4, #0x23 // #35 - 8130: eb0000bf cmp x5, x0 - 8134: 54000140 b.eq 815c - 8138: f9002bbf str xzr, [x29,#80] - 813c: 91108004 add x4, x0, #0x420 - 8140: c85ffc85 ldaxr x5, [x4] - 8144: eb1f00bf cmp x5, xzr - 8148: 54000061 b.ne 8154 - 814c: c8067c83 stxr w6, x3, [x4] - 8150: 35ffff86 cbnz w6, 8140 - 8154: 54000100 b.eq 8174 - 8158: 528002c4 mov w4, #0x16 // #22 - 815c: 2a0403e0 mov w0, w4 - 8160: f9401bf7 ldr x23, [sp,#48] - 8164: a94153f3 ldp x19, x20, [sp,#16] - 8168: a9425bf5 ldp x21, x22, [sp,#32] - 816c: a8c77bfd ldp x29, x30, [sp],#112 - 8170: d65f03c0 ret - 8174: aa0103f5 mov x21, x1 - 8178: 910143b6 add x22, x29, #0x50 - 817c: 90000001 adrp x1, 8000 - 8180: aa0003f3 mov x19, x0 - 8184: 9103a021 add x1, x1, #0xe8 - 8188: aa1603e0 mov x0, x22 - 818c: aa0203f4 mov x20, x2 - 8190: aa0403e2 mov x2, x4 - 8194: 94001c1b bl f200 <_pthread_cleanup_push> - 8198: 94001d20 bl f618 <__pthread_enable_asynccancel> - 819c: 2a0003f7 mov w23, w0 - 81a0: b940d261 ldr w1, [x19,#208] - 81a4: 35000321 cbnz w1, 8208 - 81a8: f90027a1 str x1, [x29,#72] - 81ac: 94001d4b bl f6d8 <__pthread_disable_asynccancel> - 81b0: f94027a1 ldr x1, [x29,#72] - 81b4: aa1603e0 mov x0, x22 - 81b8: 94001c1a bl f220 <_pthread_cleanup_pop> - 81bc: b4000075 cbz x21, 81c8 - 81c0: f9421660 ldr x0, [x19,#1064] - 81c4: f90002a0 str x0, [x21] - 81c8: aa1303e0 mov x0, x19 - 81cc: 97fffb16 bl 6e24 <__free_tcb> - 81d0: f9401bf7 ldr x23, [sp,#48] - 81d4: 52800004 mov w4, #0x0 // #0 - 81d8: 2a0403e0 mov w0, w4 - 81dc: a94153f3 ldp x19, x20, [sp,#16] - 81e0: a9425bf5 ldp x21, x22, [sp,#32] - 81e4: a8c77bfd ldp x29, x30, [sp],#112 - 81e8: d65f03c0 ret - 81ec: 52800464 mov w4, #0x23 // #35 - 81f0: f9401bf7 ldr x23, [sp,#48] - 81f4: 2a0403e0 mov w0, w4 - 81f8: a94153f3 ldp x19, x20, [sp,#16] - 81fc: a9425bf5 ldp x21, x22, [sp,#32] - 8200: a8c77bfd ldp x29, x30, [sp],#112 - 8204: d65f03c0 ret - 8208: aa1403e1 mov x1, x20 - 820c: 91034260 add x0, x19, #0xd0 - 8210: 94001dcf bl f94c <__lll_timedwait_tid> - 8214: 2a0003f4 mov w20, w0 - 8218: 2a1703e0 mov w0, w23 - 821c: 94001d2f bl f6d8 <__pthread_disable_asynccancel> - 8220: aa1603e0 mov x0, x22 - 8224: 52800001 mov w1, #0x0 // #0 - 8228: 94001bfe bl f220 <_pthread_cleanup_pop> - 822c: 34fffc94 cbz w20, 81bc - 8230: f902127f str xzr, [x19,#1056] - 8234: 2a1403e4 mov w4, w20 - 8238: 2a0403e0 mov w0, w4 - 823c: f9401bf7 ldr x23, [sp,#48] - 8240: a94153f3 ldp x19, x20, [sp,#16] - 8244: a9425bf5 ldp x21, x22, [sp,#32] - 8248: a8c77bfd ldp x29, x30, [sp],#112 - 824c: d65f03c0 ret - 8250: 52800064 mov w4, #0x3 // #3 - 8254: f9401bf7 ldr x23, [sp,#48] - 8258: 2a0403e0 mov w0, w4 - 825c: a94153f3 ldp x19, x20, [sp,#16] - 8260: a9425bf5 ldp x21, x22, [sp,#32] - 8264: a8c77bfd ldp x29, x30, [sp],#112 - 8268: d65f03c0 ret - -000000000000826c : - 826c: d53bd040 mrs x0, tpidr_el0 - 8270: d11bc000 sub x0, x0, #0x6f0 - 8274: d65f03c0 ret - -0000000000008278 : - 8278: eb01001f cmp x0, x1 - 827c: 1a9f17e0 cset w0, eq - 8280: d65f03c0 ret - -0000000000008284 : - 8284: 17fff3db b 51f0 - -0000000000008288 : - 8288: 90000160 adrp x0, 34000 <__GI___pthread_keys+0x3d78> - 828c: b9437800 ldr w0, [x0,#888] - 8290: d65f03c0 ret - -0000000000008294 : - 8294: 2a0003e1 mov w1, w0 - 8298: 528002c0 mov w0, #0x16 // #22 - 829c: 37f80081 tbnz w1, #31, 82ac - 82a0: 90000162 adrp x2, 34000 <__GI___pthread_keys+0x3d78> - 82a4: 52800000 mov w0, #0x0 // #0 - 82a8: b9037841 str w1, [x2,#888] - 82ac: d65f03c0 ret - -00000000000082b0 : - 82b0: a9bc7bfd stp x29, x30, [sp,#-64]! - 82b4: 910003fd mov x29, sp - 82b8: b940d003 ldr w3, [x0,#208] - 82bc: a90153f3 stp x19, x20, [sp,#16] - 82c0: a9025bf5 stp x21, x22, [sp,#32] - 82c4: 6b1f007f cmp w3, wzr - 82c8: 5400074d b.le 83b0 - 82cc: aa0003f3 mov x19, x0 - 82d0: 91106014 add x20, x0, #0x418 - 82d4: aa0203f6 mov x22, x2 - 82d8: aa0103f5 mov x21, x1 - 82dc: b9003fbf str wzr, [x29,#60] - 82e0: 52800020 mov w0, #0x1 // #1 - 82e4: 885ffe81 ldaxr w1, [x20] - 82e8: 6b1f003f cmp w1, wzr - 82ec: 54000061 b.ne 82f8 - 82f0: 88027e80 stxr w2, w0, [x20] - 82f4: 35ffff82 cbnz w2, 82e4 - 82f8: 54000281 b.ne 8348 - 82fc: b9410e60 ldr w0, [x19,#268] - 8300: 362802e0 tbz w0, #5, 835c - 8304: 363003c0 tbz w0, #6, 837c - 8308: b9443660 ldr w0, [x19,#1076] - 830c: 52800004 mov w4, #0x0 // #0 - 8310: b90002a0 str w0, [x21] - 8314: b9443260 ldr w0, [x19,#1072] - 8318: b90002c0 str w0, [x22] - 831c: 52800001 mov w1, #0x0 // #0 - 8320: 885f7e80 ldxr w0, [x20] - 8324: 8802fe81 stlxr w2, w1, [x20] - 8328: 35ffffc2 cbnz w2, 8320 - 832c: 7100041f cmp w0, #0x1 - 8330: 540004cc b.gt 83c8 - 8334: 2a0403e0 mov w0, w4 - 8338: a94153f3 ldp x19, x20, [sp,#16] - 833c: a9425bf5 ldp x21, x22, [sp,#32] - 8340: a8c47bfd ldp x29, x30, [sp],#64 - 8344: d65f03c0 ret - 8348: aa1403e0 mov x0, x20 - 834c: b9003fa1 str w1, [x29,#60] - 8350: 94001d06 bl f768 <__lll_lock_wait_private> - 8354: b9410e60 ldr w0, [x19,#268] - 8358: 372ffd60 tbnz w0, #5, 8304 - 835c: b940d260 ldr w0, [x19,#208] - 8360: 9110c261 add x1, x19, #0x430 - 8364: 97fff373 bl 5130 <__sched_getparam@plt> - 8368: 340001c0 cbz w0, 83a0 - 836c: b9410e60 ldr w0, [x19,#268] - 8370: 363003a0 tbz w0, #6, 83e4 - 8374: 52800024 mov w4, #0x1 // #1 - 8378: 17ffffe9 b 831c - 837c: b940d260 ldr w0, [x19,#208] - 8380: 97fff3ec bl 5330 <__sched_getscheduler@plt> - 8384: 3100041f cmn w0, #0x1 - 8388: b9043660 str w0, [x19,#1076] - 838c: 54ffff40 b.eq 8374 - 8390: b9410e60 ldr w0, [x19,#268] - 8394: 321a0000 orr w0, w0, #0x40 - 8398: b9010e60 str w0, [x19,#268] - 839c: 17ffffdb b 8308 - 83a0: b9410e60 ldr w0, [x19,#268] - 83a4: 321b0000 orr w0, w0, #0x20 - 83a8: b9010e60 str w0, [x19,#268] - 83ac: 17ffffd6 b 8304 - 83b0: 52800064 mov w4, #0x3 // #3 - 83b4: 2a0403e0 mov w0, w4 - 83b8: a94153f3 ldp x19, x20, [sp,#16] - 83bc: a9425bf5 ldp x21, x22, [sp,#32] - 83c0: a8c47bfd ldp x29, x30, [sp],#64 - 83c4: d65f03c0 ret - 83c8: aa1403e0 mov x0, x20 - 83cc: d2801021 mov x1, #0x81 // #129 - 83d0: d2800022 mov x2, #0x1 // #1 - 83d4: d2800003 mov x3, #0x0 // #0 - 83d8: d2800c48 mov x8, #0x62 // #98 - 83dc: d4000001 svc #0x0 - 83e0: 17ffffd5 b 8334 - 83e4: b940d260 ldr w0, [x19,#208] - 83e8: 97fff3d2 bl 5330 <__sched_getscheduler@plt> - 83ec: 3100041f cmn w0, #0x1 - 83f0: b9043660 str w0, [x19,#1076] - 83f4: 54fffc00 b.eq 8374 - 83f8: b9410e60 ldr w0, [x19,#268] - 83fc: 52800024 mov w4, #0x1 // #1 - 8400: 321a0000 orr w0, w0, #0x40 - 8404: b9010e60 str w0, [x19,#268] - 8408: 17ffffc5 b 831c - -000000000000840c : - 840c: a9bc7bfd stp x29, x30, [sp,#-64]! - 8410: 910003fd mov x29, sp - 8414: b940d003 ldr w3, [x0,#208] - 8418: a90153f3 stp x19, x20, [sp,#16] - 841c: a9025bf5 stp x21, x22, [sp,#32] - 8420: 6b1f007f cmp w3, wzr - 8424: 5400056d b.le 84d0 - 8428: aa0003f3 mov x19, x0 - 842c: 91106014 add x20, x0, #0x418 - 8430: aa0203f5 mov x21, x2 - 8434: 2a0103f6 mov w22, w1 - 8438: b9003bbf str wzr, [x29,#56] - 843c: 52800020 mov w0, #0x1 // #1 - 8440: 885ffe81 ldaxr w1, [x20] - 8444: 6b1f003f cmp w1, wzr - 8448: 54000061 b.ne 8454 - 844c: 88027e80 stxr w2, w0, [x20] - 8450: 35ffff82 cbnz w2, 8440 - 8454: 54000361 b.ne 84c0 - 8458: f9425a60 ldr x0, [x19,#1200] - 845c: aa1503e2 mov x2, x21 - 8460: b5000440 cbnz x0, 84e8 - 8464: b940d260 ldr w0, [x19,#208] - 8468: 2a1603e1 mov w1, w22 - 846c: 97fff389 bl 5290 <__sched_setscheduler@plt> - 8470: 3100041f cmn w0, #0x1 - 8474: 54000480 b.eq 8504 - 8478: b9043676 str w22, [x19,#1076] - 847c: 52800004 mov w4, #0x0 // #0 - 8480: b9410e60 ldr w0, [x19,#268] - 8484: b94002a1 ldr w1, [x21] - 8488: 321b0400 orr w0, w0, #0x60 - 848c: b9043261 str w1, [x19,#1072] - 8490: b9010e60 str w0, [x19,#268] - 8494: 52800001 mov w1, #0x0 // #0 - 8498: 885f7e80 ldxr w0, [x20] - 849c: 8802fe81 stlxr w2, w1, [x20] - 84a0: 35ffffc2 cbnz w2, 8498 - 84a4: 7100041f cmp w0, #0x1 - 84a8: 5400038c b.gt 8518 - 84ac: 2a0403e0 mov w0, w4 - 84b0: a94153f3 ldp x19, x20, [sp,#16] - 84b4: a9425bf5 ldp x21, x22, [sp,#32] - 84b8: a8c47bfd ldp x29, x30, [sp],#64 - 84bc: d65f03c0 ret - 84c0: aa1403e0 mov x0, x20 - 84c4: b9003ba1 str w1, [x29,#56] - 84c8: 94001ca8 bl f768 <__lll_lock_wait_private> - 84cc: 17ffffe3 b 8458 - 84d0: 52800064 mov w4, #0x3 // #3 - 84d4: 2a0403e0 mov w0, w4 - 84d8: a94153f3 ldp x19, x20, [sp,#16] - 84dc: a9425bf5 ldp x21, x22, [sp,#32] - 84e0: a8c47bfd ldp x29, x30, [sp],#64 - 84e4: d65f03c0 ret - 84e8: b9400000 ldr w0, [x0] - 84ec: b94002a1 ldr w1, [x21] - 84f0: 6b01001f cmp w0, w1 - 84f4: 54fffb8d b.le 8464 - 84f8: 910103a2 add x2, x29, #0x40 - 84fc: b81f8c40 str w0, [x2,#-8]! - 8500: 17ffffd9 b 8464 - 8504: d53bd040 mrs x0, tpidr_el0 - 8508: f0000121 adrp x1, 2f000 <__FRAME_END__+0x18e30> - 850c: f947c421 ldr x1, [x1,#3976] - 8510: b8616804 ldr w4, [x0,x1] - 8514: 17ffffe0 b 8494 - 8518: aa1403e0 mov x0, x20 - 851c: d2801021 mov x1, #0x81 // #129 - 8520: d2800022 mov x2, #0x1 // #1 - 8524: d2800003 mov x3, #0x0 // #0 - 8528: d2800c48 mov x8, #0x62 // #98 - 852c: d4000001 svc #0x0 - 8530: 17ffffdf b 84ac - -0000000000008534 : - 8534: a9bc7bfd stp x29, x30, [sp,#-64]! - 8538: 910003fd mov x29, sp - 853c: b940d002 ldr w2, [x0,#208] - 8540: a90153f3 stp x19, x20, [sp,#16] - 8544: f90013f5 str x21, [sp,#32] - 8548: 6b1f005f cmp w2, wzr - 854c: 5400052d b.le 85f0 - 8550: aa0003f3 mov x19, x0 - 8554: 91106015 add x21, x0, #0x418 - 8558: 2a0103f4 mov w20, w1 - 855c: b9003ba1 str w1, [x29,#56] - 8560: b9003fbf str wzr, [x29,#60] - 8564: 52800020 mov w0, #0x1 // #1 - 8568: 885ffea1 ldaxr w1, [x21] - 856c: 6b1f003f cmp w1, wzr - 8570: 54000061 b.ne 857c - 8574: 88027ea0 stxr w2, w0, [x21] - 8578: 35ffff82 cbnz w2, 8568 - 857c: 54000321 b.ne 85e0 - 8580: f9425a60 ldr x0, [x19,#1200] - 8584: b5000420 cbnz x0, 8608 - 8588: b940d260 ldr w0, [x19,#208] - 858c: 9100e3a1 add x1, x29, #0x38 - 8590: 97fff304 bl 51a0 - 8594: 3100041f cmn w0, #0x1 - 8598: 54000420 b.eq 861c - 859c: b9410e60 ldr w0, [x19,#268] - 85a0: 52800004 mov w4, #0x0 // #0 - 85a4: b9003bb4 str w20, [x29,#56] - 85a8: 321b0000 orr w0, w0, #0x20 - 85ac: b9043274 str w20, [x19,#1072] - 85b0: b9010e60 str w0, [x19,#268] - 85b4: 52800001 mov w1, #0x0 // #0 - 85b8: 885f7ea0 ldxr w0, [x21] - 85bc: 8802fea1 stlxr w2, w1, [x21] - 85c0: 35ffffc2 cbnz w2, 85b8 - 85c4: 7100041f cmp w0, #0x1 - 85c8: 5400034c b.gt 8630 - 85cc: 2a0403e0 mov w0, w4 - 85d0: f94013f5 ldr x21, [sp,#32] - 85d4: a94153f3 ldp x19, x20, [sp,#16] - 85d8: a8c47bfd ldp x29, x30, [sp],#64 - 85dc: d65f03c0 ret - 85e0: aa1503e0 mov x0, x21 - 85e4: b9003fa1 str w1, [x29,#60] - 85e8: 94001c60 bl f768 <__lll_lock_wait_private> - 85ec: 17ffffe5 b 8580 - 85f0: 52800064 mov w4, #0x3 // #3 - 85f4: f94013f5 ldr x21, [sp,#32] - 85f8: 2a0403e0 mov w0, w4 - 85fc: a94153f3 ldp x19, x20, [sp,#16] - 8600: a8c47bfd ldp x29, x30, [sp],#64 - 8604: d65f03c0 ret - 8608: b9400000 ldr w0, [x0] - 860c: 6b00029f cmp w20, w0 - 8610: 54fffbca b.ge 8588 - 8614: b9003ba0 str w0, [x29,#56] - 8618: 17ffffdc b 8588 - 861c: d53bd040 mrs x0, tpidr_el0 - 8620: f0000121 adrp x1, 2f000 <__FRAME_END__+0x18e30> - 8624: f947c421 ldr x1, [x1,#3976] - 8628: b8616804 ldr w4, [x0,x1] - 862c: 17ffffe2 b 85b4 - 8630: aa1503e0 mov x0, x21 - 8634: d2801021 mov x1, #0x81 // #129 - 8638: d2800022 mov x2, #0x1 // #1 - 863c: d2800003 mov x3, #0x0 // #0 - 8640: d2800c48 mov x8, #0x62 // #98 - 8644: d4000001 svc #0x0 - 8648: 17ffffe1 b 85cc - -000000000000864c : - 864c: a9be7bfd stp x29, x30, [sp,#-32]! - 8650: 910003fd mov x29, sp - 8654: f9000bf3 str x19, [sp,#16] - 8658: aa0003f3 mov x19, x0 - 865c: a9007c1f stp xzr, xzr, [x0] - 8660: a9017c1f stp xzr, xzr, [x0,#16] - 8664: a9027c1f stp xzr, xzr, [x0,#32] - 8668: a9037c1f stp xzr, xzr, [x0,#48] - 866c: 97fff265 bl 5000 <__getpagesize@plt> - 8670: 93407c01 sxtw x1, w0 - 8674: f9000a61 str x1, [x19,#16] - 8678: 52800000 mov w0, #0x0 // #0 - 867c: f9400bf3 ldr x19, [sp,#16] - 8680: a8c27bfd ldp x29, x30, [sp],#32 - 8684: d65f03c0 ret - -0000000000008688 : - 8688: a9bf7bfd stp x29, x30, [sp,#-16]! - 868c: 910003fd mov x29, sp - 8690: f9401400 ldr x0, [x0,#40] - 8694: 97fff2e3 bl 5220 - 8698: 52800000 mov w0, #0x0 // #0 - 869c: a8c17bfd ldp x29, x30, [sp],#16 - 86a0: d65f03c0 ret - -00000000000086a4 : - 86a4: b9400802 ldr w2, [x0,#8] - 86a8: 52800000 mov w0, #0x0 // #0 - 86ac: 12000042 and w2, w2, #0x1 - 86b0: b9000022 str w2, [x1] - 86b4: d65f03c0 ret - -00000000000086b8 : - 86b8: 7100043f cmp w1, #0x1 - 86bc: 540000e0 b.eq 86d8 - 86c0: 35000181 cbnz w1, 86f0 - 86c4: b9400802 ldr w2, [x0,#8] - 86c8: 121f7842 and w2, w2, #0xfffffffe - 86cc: b9000802 str w2, [x0,#8] - 86d0: 2a0103e0 mov w0, w1 - 86d4: d65f03c0 ret - 86d8: b9400802 ldr w2, [x0,#8] - 86dc: 52800001 mov w1, #0x0 // #0 - 86e0: 32000042 orr w2, w2, #0x1 - 86e4: b9000802 str w2, [x0,#8] - 86e8: 2a0103e0 mov w0, w1 - 86ec: d65f03c0 ret - 86f0: 528002c1 mov w1, #0x16 // #22 - 86f4: 17fffff7 b 86d0 - -00000000000086f8 : - 86f8: f9400802 ldr x2, [x0,#16] - 86fc: 52800000 mov w0, #0x0 // #0 - 8700: f9000022 str x2, [x1] - 8704: d65f03c0 ret - -0000000000008708 : - 8708: f9000801 str x1, [x0,#16] - 870c: 52800000 mov w0, #0x0 // #0 - 8710: d65f03c0 ret - -0000000000008714 : - 8714: b9400002 ldr w2, [x0] - 8718: 52800000 mov w0, #0x0 // #0 - 871c: b9000022 str w2, [x1] - 8720: d65f03c0 ret - -0000000000008724 : - 8724: a9bc7bfd stp x29, x30, [sp,#-64]! - 8728: 910003fd mov x29, sp - 872c: a90153f3 stp x19, x20, [sp,#16] - 8730: b9400413 ldr w19, [x0,#4] - 8734: a9025bf5 stp x21, x22, [sp,#32] - 8738: aa0003f5 mov x21, x0 - 873c: 2a1303e0 mov w0, w19 - 8740: b9400036 ldr w22, [x1] - 8744: f9001fa1 str x1, [x29,#56] - 8748: 97fff28e bl 5180 <__sched_get_priority_min@plt> - 874c: 2a0003f4 mov w20, w0 - 8750: 2a1303e0 mov w0, w19 - 8754: 97fff2ff bl 5350 <__sched_get_priority_max@plt> - 8758: 37f80074 tbnz w20, #31, 8764 - 875c: f9401fa1 ldr x1, [x29,#56] - 8760: 36f800c0 tbz w0, #31, 8778 - 8764: 528002c0 mov w0, #0x16 // #22 - 8768: a94153f3 ldp x19, x20, [sp,#16] - 876c: a9425bf5 ldp x21, x22, [sp,#32] - 8770: a8c47bfd ldp x29, x30, [sp],#64 - 8774: d65f03c0 ret - 8778: 6b1402df cmp w22, w20 - 877c: 54ffff4b b.lt 8764 - 8780: 6b0002df cmp w22, w0 - 8784: 54ffff0c b.gt 8764 - 8788: b9400aa2 ldr w2, [x21,#8] - 878c: 52800000 mov w0, #0x0 // #0 - 8790: b9400021 ldr w1, [x1] - 8794: b90002a1 str w1, [x21] - 8798: 321b0042 orr w2, w2, #0x20 - 879c: b9000aa2 str w2, [x21,#8] - 87a0: a94153f3 ldp x19, x20, [sp,#16] - 87a4: a9425bf5 ldp x21, x22, [sp,#32] - 87a8: a8c47bfd ldp x29, x30, [sp],#64 - 87ac: d65f03c0 ret - -00000000000087b0 : - 87b0: b9400402 ldr w2, [x0,#4] - 87b4: 52800000 mov w0, #0x0 // #0 - 87b8: b9000022 str w2, [x1] - 87bc: d65f03c0 ret - -00000000000087c0 : - 87c0: 7100083f cmp w1, #0x2 - 87c4: 528002c2 mov w2, #0x16 // #22 - 87c8: 540000c8 b.hi 87e0 - 87cc: b9400803 ldr w3, [x0,#8] - 87d0: 52800002 mov w2, #0x0 // #0 - 87d4: b9000401 str w1, [x0,#4] - 87d8: 321a0063 orr w3, w3, #0x40 - 87dc: b9000803 str w3, [x0,#8] - 87e0: 2a0203e0 mov w0, w2 - 87e4: d65f03c0 ret - -00000000000087e8 : - 87e8: b9400802 ldr w2, [x0,#8] - 87ec: 52800000 mov w0, #0x0 // #0 - 87f0: d3410442 ubfx x2, x2, #1, #1 - 87f4: b9000022 str w2, [x1] - 87f8: d65f03c0 ret - -00000000000087fc : - 87fc: 7100043f cmp w1, #0x1 - 8800: aa0003e2 mov x2, x0 - 8804: 528002c0 mov w0, #0x16 // #22 - 8808: 54000049 b.ls 8810 - 880c: d65f03c0 ret - 8810: 350000c1 cbnz w1, 8828 - 8814: b9400843 ldr w3, [x2,#8] - 8818: 2a0103e0 mov w0, w1 - 881c: 121e7863 and w3, w3, #0xfffffffd - 8820: b9000843 str w3, [x2,#8] - 8824: d65f03c0 ret - 8828: b9400841 ldr w1, [x2,#8] - 882c: 52800000 mov w0, #0x0 // #0 - 8830: 321f0021 orr w1, w1, #0x2 - 8834: b9000841 str w1, [x2,#8] - 8838: d65f03c0 ret - -000000000000883c : - 883c: b9400802 ldr w2, [x0,#8] - 8840: 52800000 mov w0, #0x0 // #0 - 8844: d3420842 ubfx x2, x2, #2, #1 - 8848: b9000022 str w2, [x1] - 884c: d65f03c0 ret - -0000000000008850 : - 8850: 340000e1 cbz w1, 886c - 8854: 7100043f cmp w1, #0x1 - 8858: 52800be0 mov w0, #0x5f // #95 - 885c: 528002c1 mov w1, #0x16 // #22 - 8860: 1a810001 csel w1, w0, w1, eq - 8864: 2a0103e0 mov w0, w1 - 8868: d65f03c0 ret - 886c: b9400802 ldr w2, [x0,#8] - 8870: 121d7842 and w2, w2, #0xfffffffb - 8874: b9000802 str w2, [x0,#8] - 8878: 2a0103e0 mov w0, w1 - 887c: d65f03c0 ret - -0000000000008880 : - 8880: f9400c02 ldr x2, [x0,#24] - 8884: 52800000 mov w0, #0x0 // #0 - 8888: f9000022 str x2, [x1] - 888c: d65f03c0 ret - -0000000000008890 : - 8890: aa0003e2 mov x2, x0 - 8894: 52800000 mov w0, #0x0 // #0 - 8898: b9400843 ldr w3, [x2,#8] - 889c: f9000c41 str x1, [x2,#24] - 88a0: 321d0063 orr w3, w3, #0x8 - 88a4: b9000843 str w3, [x2,#8] - 88a8: d65f03c0 ret - -00000000000088ac : - 88ac: a9bd7bfd stp x29, x30, [sp,#-48]! - 88b0: 910003fd mov x29, sp - 88b4: f9401004 ldr x4, [x0,#32] - 88b8: a90153f3 stp x19, x20, [sp,#16] - 88bc: aa0103f4 mov x20, x1 - 88c0: b40000c4 cbz x4, 88d8 - 88c4: f9000284 str x4, [x20] - 88c8: 52800000 mov w0, #0x0 // #0 - 88cc: a94153f3 ldp x19, x20, [sp,#16] - 88d0: a8c37bfd ldp x29, x30, [sp],#48 - 88d4: d65f03c0 ret - 88d8: 90000173 adrp x19, 34000 <__GI___pthread_keys+0x3d78> - 88dc: b9002fa4 str w4, [x29,#44] - 88e0: 910a2260 add x0, x19, #0x288 - 88e4: 52800021 mov w1, #0x1 // #1 - 88e8: 885ffc02 ldaxr w2, [x0] - 88ec: 6b1f005f cmp w2, wzr - 88f0: 54000061 b.ne 88fc - 88f4: 88037c01 stxr w3, w1, [x0] - 88f8: 35ffff83 cbnz w3, 88e8 - 88fc: 54000201 b.ne 893c - 8900: 90000161 adrp x1, 34000 <__GI___pthread_keys+0x3d78> - 8904: 910a2260 add x0, x19, #0x288 - 8908: 52800002 mov w2, #0x0 // #0 - 890c: f941a824 ldr x4, [x1,#848] - 8910: 885f7c01 ldxr w1, [x0] - 8914: 8803fc02 stlxr w3, w2, [x0] - 8918: 35ffffc3 cbnz w3, 8910 - 891c: 7100043f cmp w1, #0x1 - 8920: 54fffd2d b.le 88c4 - 8924: d2801021 mov x1, #0x81 // #129 - 8928: d2800022 mov x2, #0x1 // #1 - 892c: d2800003 mov x3, #0x0 // #0 - 8930: d2800c48 mov x8, #0x62 // #98 - 8934: d4000001 svc #0x0 - 8938: 17ffffe3 b 88c4 - 893c: b9002fa2 str w2, [x29,#44] - 8940: 94001b8a bl f768 <__lll_lock_wait_private> - 8944: 17ffffef b 8900 - -0000000000008948 : - 8948: b24043e2 mov x2, #0x1ffff // #131071 - 894c: eb02003f cmp x1, x2 - 8950: 54000068 b.hi 895c - 8954: 528002c0 mov w0, #0x16 // #22 - 8958: d65f03c0 ret - 895c: f9001001 str x1, [x0,#32] - 8960: 52800000 mov w0, #0x0 // #0 - 8964: d65f03c0 ret - -0000000000008968 : - 8968: aa0003e3 mov x3, x0 - 896c: 52800000 mov w0, #0x0 // #0 - 8970: f9401064 ldr x4, [x3,#32] - 8974: f9400c63 ldr x3, [x3,#24] - 8978: cb040063 sub x3, x3, x4 - 897c: f9000023 str x3, [x1] - 8980: f9000044 str x4, [x2] - 8984: d65f03c0 ret - -0000000000008988 : - 8988: b24043e3 mov x3, #0x1ffff // #131071 - 898c: eb03005f cmp x2, x3 - 8990: 54000088 b.hi 89a0 - 8994: 528002c2 mov w2, #0x16 // #22 - 8998: 2a0203e0 mov w0, w2 - 899c: d65f03c0 ret - 89a0: b9400803 ldr w3, [x0,#8] - 89a4: 8b020021 add x1, x1, x2 - 89a8: f9001002 str x2, [x0,#32] - 89ac: 52800002 mov w2, #0x0 // #0 - 89b0: 321d0063 orr w3, w3, #0x8 - 89b4: f9000c01 str x1, [x0,#24] - 89b8: b9000803 str w3, [x0,#8] - 89bc: 2a0203e0 mov w0, w2 - 89c0: d65f03c0 ret - -00000000000089c4 : - 89c4: a9b57bfd stp x29, x30, [sp,#-176]! - 89c8: 910003fd mov x29, sp - 89cc: 6d0627e8 stp d8, d9, [sp,#96] - 89d0: a9025bf5 stp x21, x22, [sp,#32] - 89d4: a90363f7 stp x23, x24, [sp,#48] - 89d8: a9046bf9 stp x25, x26, [sp,#64] - 89dc: aa0003f5 mov x21, x0 - 89e0: 91106019 add x25, x0, #0x418 - 89e4: a90153f3 stp x19, x20, [sp,#16] - 89e8: a90573fb stp x27, x28, [sp,#80] - 89ec: b900a3bf str wzr, [x29,#160] - 89f0: aa0103f7 mov x23, x1 - 89f4: 52800020 mov w0, #0x1 // #1 - 89f8: fd003bea str d10, [sp,#112] - 89fc: 885fff21 ldaxr w1, [x25] - 8a00: 6b1f003f cmp w1, wzr - 8a04: 54000061 b.ne 8a10 - 8a08: 88027f20 stxr w2, w0, [x25] - 8a0c: 35ffff82 cbnz w2, 89fc - 8a10: 54000741 b.ne 8af8 - 8a14: b94432a0 ldr w0, [x21,#1072] - 8a18: b90002e0 str w0, [x23] - 8a1c: f94212a2 ldr x2, [x21,#1056] - 8a20: b94436a1 ldr w1, [x21,#1076] - 8a24: b9410ea0 ldr w0, [x21,#268] - 8a28: eb15005f cmp x2, x21 - 8a2c: b90006e1 str w1, [x23,#4] - 8a30: b9000ae0 str w0, [x23,#8] - 8a34: 54000740 b.eq 8b1c - 8a38: f94256a1 ldr x1, [x21,#1192] - 8a3c: f9424ab3 ldr x19, [x21,#1168] - 8a40: f9000ae1 str x1, [x23,#16] - 8a44: b4000793 cbz x19, 8b34 - 8a48: f9424ea1 ldr x1, [x21,#1176] - 8a4c: 321d0000 orr w0, w0, #0x8 - 8a50: f90012e1 str x1, [x23,#32] - 8a54: b9000ae0 str w0, [x23,#8] - 8a58: 8b010261 add x1, x19, x1 - 8a5c: f9000ee1 str x1, [x23,#24] - 8a60: d2800016 mov x22, #0x0 // #0 - 8a64: d2800213 mov x19, #0x10 // #16 - 8a68: b2404ff8 mov x24, #0xfffff // #1048575 - 8a6c: 14000007 b 8a88 - 8a70: 9400227e bl 11468 - 8a74: 7100581f cmp w0, #0x16 - 8a78: aa1403f6 mov x22, x20 - 8a7c: 54000461 b.ne 8b08 - 8a80: eb18027f cmp x19, x24 - 8a84: 54000428 b.hi 8b08 - 8a88: d37ffa73 lsl x19, x19, #1 - 8a8c: aa1603e0 mov x0, x22 - 8a90: aa1303e1 mov x1, x19 - 8a94: 97fff19f bl 5110 - 8a98: aa0003f4 mov x20, x0 - 8a9c: aa1303e1 mov x1, x19 - 8aa0: aa1503e0 mov x0, x21 - 8aa4: aa1403e2 mov x2, x20 - 8aa8: b5fffe54 cbnz x20, 8a70 - 8aac: aa1603e0 mov x0, x22 - 8ab0: 52800196 mov w22, #0xc // #12 - 8ab4: 97fff1db bl 5220 - 8ab8: 52800001 mov w1, #0x0 // #0 - 8abc: 885f7f20 ldxr w0, [x25] - 8ac0: 8802ff21 stlxr w2, w1, [x25] - 8ac4: 35ffffc2 cbnz w2, 8abc - 8ac8: 7100041f cmp w0, #0x1 - 8acc: 5400096c b.gt 8bf8 - 8ad0: 2a1603e0 mov w0, w22 - 8ad4: 6d4627e8 ldp d8, d9, [sp,#96] - 8ad8: a94153f3 ldp x19, x20, [sp,#16] - 8adc: a9425bf5 ldp x21, x22, [sp,#32] - 8ae0: a94363f7 ldp x23, x24, [sp,#48] - 8ae4: a9446bf9 ldp x25, x26, [sp,#64] - 8ae8: a94573fb ldp x27, x28, [sp,#80] - 8aec: fd403bea ldr d10, [sp,#112] - 8af0: a8cb7bfd ldp x29, x30, [sp],#176 - 8af4: d65f03c0 ret - 8af8: aa1903e0 mov x0, x25 - 8afc: b900a3a1 str w1, [x29,#160] - 8b00: 94001b1a bl f768 <__lll_lock_wait_private> - 8b04: 17ffffc4 b 8a14 - 8b08: 2a0003f6 mov w22, w0 - 8b0c: 35000f40 cbnz w0, 8cf4 - 8b10: f90016f4 str x20, [x23,#40] - 8b14: f9001af3 str x19, [x23,#48] - 8b18: 17ffffe8 b 8ab8 - 8b1c: f94256a1 ldr x1, [x21,#1192] - 8b20: 32000000 orr w0, w0, #0x1 - 8b24: f9424ab3 ldr x19, [x21,#1168] - 8b28: b9000ae0 str w0, [x23,#8] - 8b2c: f9000ae1 str x1, [x23,#16] - 8b30: b5fff8d3 cbnz x19, 8a48 - 8b34: d0000040 adrp x0, 12000 <__pthread_current_priority+0xa8> - 8b38: d0000041 adrp x1, 12000 <__pthread_current_priority+0xa8> - 8b3c: 912e6000 add x0, x0, #0xb98 - 8b40: 912ea021 add x1, x1, #0xba8 - 8b44: 97fff14b bl 5070 - 8b48: aa0003f4 mov x20, x0 - 8b4c: b4000a20 cbz x0, 8c90 - 8b50: 52800060 mov w0, #0x3 // #3 - 8b54: 910283a1 add x1, x29, #0xa0 - 8b58: 97fff1da bl 52c0 - 8b5c: 35000740 cbnz w0, 8c44 - 8b60: f0000120 adrp x0, 2f000 <__FRAME_END__+0x18e30> - 8b64: b9400284 ldr w4, [x20] - 8b68: 9e670268 fmov d8, x19 - 8b6c: d0000058 adrp x24, 12000 <__pthread_current_priority+0xa8> - 8b70: 32110084 orr w4, w4, #0x8000 - 8b74: 910203bb add x27, x29, #0x80 - 8b78: f947e001 ldr x1, [x0,#4032] - 8b7c: f0000120 adrp x0, 2f000 <__FRAME_END__+0x18e30> - 8b80: 910223ba add x26, x29, #0x88 - 8b84: 912ec318 add x24, x24, #0xbb0 - 8b88: 910243b6 add x22, x29, #0x90 - 8b8c: 910263bc add x28, x29, #0x98 - 8b90: f947d400 ldr x0, [x0,#4008] - 8b94: f9400021 ldr x1, [x1] - 8b98: b9000284 str w4, [x20] - 8b9c: f9400c00 ldr x0, [x0,#24] - 8ba0: 9e67002a fmov d10, x1 - 8ba4: f90043b3 str x19, [x29,#128] - 8ba8: f90047b3 str x19, [x29,#136] - 8bac: 9e670009 fmov d9, x0 - 8bb0: aa1a03e1 mov x1, x26 - 8bb4: aa1403e3 mov x3, x20 - 8bb8: aa1b03e0 mov x0, x27 - 8bbc: 52800142 mov w2, #0xa // #10 - 8bc0: 121c0093 and w19, w4, #0x10 - 8bc4: 372005e4 tbnz w4, #4, 8c80 - 8bc8: 97fff1fe bl 53c0 <__getdelim@plt> - 8bcc: eb1f001f cmp x0, xzr - 8bd0: aa1803e1 mov x1, x24 - 8bd4: aa1603e2 mov x2, x22 - 8bd8: aa1c03e3 mov x3, x28 - 8bdc: 5400052d b.le 8c80 - 8be0: f94043a0 ldr x0, [x29,#128] - 8be4: 97fff13b bl 50d0 - 8be8: 7100081f cmp w0, #0x2 - 8bec: 54000140 b.eq 8c14 - 8bf0: b9400284 ldr w4, [x20] - 8bf4: 17ffffef b 8bb0 - 8bf8: aa1903e0 mov x0, x25 - 8bfc: d2801021 mov x1, #0x81 // #129 - 8c00: d2800022 mov x2, #0x1 // #1 - 8c04: d2800003 mov x3, #0x0 // #0 - 8c08: d2800c48 mov x8, #0x62 // #98 - 8c0c: d4000001 svc #0x0 - 8c10: 17ffffb0 b 8ad0 - 8c14: f0000120 adrp x0, 2f000 <__FRAME_END__+0x18e30> - 8c18: f9404ba1 ldr x1, [x29,#144] - 8c1c: f947e000 ldr x0, [x0,#4032] - 8c20: f9400000 ldr x0, [x0] - 8c24: eb01001f cmp x0, x1 - 8c28: 54000243 b.cc 8c70 - 8c2c: f9404fa1 ldr x1, [x29,#152] - 8c30: eb01001f cmp x0, x1 - 8c34: 54000383 b.cc 8ca4 - 8c38: 9e670028 fmov d8, x1 - 8c3c: b9400284 ldr w4, [x20] - 8c40: 17ffffdc b 8bb0 - 8c44: d53bd040 mrs x0, tpidr_el0 - 8c48: f0000121 adrp x1, 2f000 <__FRAME_END__+0x18e30> - 8c4c: f947c421 ldr x1, [x1,#3976] - 8c50: b8616816 ldr w22, [x0,x1] - 8c54: aa1403e0 mov x0, x20 - 8c58: 97fff0fe bl 5050 - 8c5c: b9400ae0 ldr w0, [x23,#8] - 8c60: 321d0000 orr w0, w0, #0x8 - 8c64: b9000ae0 str w0, [x23,#8] - 8c68: 35fff296 cbnz w22, 8ab8 - 8c6c: 17ffff7d b 8a60 - 8c70: f9404fa0 ldr x0, [x29,#152] - 8c74: b9400284 ldr w4, [x20] - 8c78: 9e670008 fmov d8, x0 - 8c7c: 17ffffcd b 8bb0 - 8c80: 52800056 mov w22, #0x2 // #2 - 8c84: f94043a0 ldr x0, [x29,#128] - 8c88: 97fff166 bl 5220 - 8c8c: 17fffff2 b 8c54 - 8c90: d53bd040 mrs x0, tpidr_el0 - 8c94: f0000121 adrp x1, 2f000 <__FRAME_END__+0x18e30> - 8c98: f947c421 ldr x1, [x1,#3976] - 8c9c: b8616816 ldr w22, [x0,x1] - 8ca0: 17ffffef b 8c5c - 8ca4: 9e660123 fmov x3, d9 - 8ca8: 9e660140 fmov x0, d10 - 8cac: 9e660104 fmov x4, d8 - 8cb0: cb0303e2 neg x2, x3 - 8cb4: 8a020000 and x0, x0, x2 - 8cb8: 8b030000 add x0, x0, x3 - 8cbc: f94053a3 ldr x3, [x29,#160] - 8cc0: f9000ee0 str x0, [x23,#24] - 8cc4: 8b030003 add x3, x0, x3 - 8cc8: cb040000 sub x0, x0, x4 - 8ccc: cb010061 sub x1, x3, x1 - 8cd0: 8a020021 and x1, x1, x2 - 8cd4: eb00003f cmp x1, x0 - 8cd8: 54000088 b.hi 8ce8 - 8cdc: f90012e1 str x1, [x23,#32] - 8ce0: 2a1303f6 mov w22, w19 - 8ce4: 17ffffe8 b 8c84 - 8ce8: f90012e0 str x0, [x23,#32] - 8cec: 2a1303f6 mov w22, w19 - 8cf0: 17ffffe5 b 8c84 - 8cf4: aa1403e0 mov x0, x20 - 8cf8: 97fff14a bl 5220 - 8cfc: 71009adf cmp w22, #0x26 - 8d00: 54ffedc1 b.ne 8ab8 - 8d04: f90016ff str xzr, [x23,#40] - 8d08: 52800016 mov w22, #0x0 // #0 - 8d0c: f9001aff str xzr, [x23,#48] - 8d10: 17ffff6a b 8ab8 - -0000000000008d14 <__pthread_mutex_init>: - 8d14: a9bd7bfd stp x29, x30, [sp,#-48]! - 8d18: 910003fd mov x29, sp - 8d1c: a90153f3 stp x19, x20, [sp,#16] - 8d20: aa0003f3 mov x19, x0 - 8d24: b4000761 cbz x1, 8e10 <__pthread_mutex_init+0xfc> - 8d28: b9400022 ldr w2, [x1] - 8d2c: 72040440 ands w0, w2, #0x30000000 - 8d30: 54000120 b.eq 8d54 <__pthread_mutex_init+0x40> - 8d34: 52a20003 mov w3, #0x10000000 // #268435456 - 8d38: 6b03001f cmp w0, w3 - 8d3c: 540000c0 b.eq 8d54 <__pthread_mutex_init+0x40> - 8d40: 52800be0 mov w0, #0x5f // #95 - 8d44: 36f00082 tbz w2, #30, 8d54 <__pthread_mutex_init+0x40> - 8d48: a94153f3 ldp x19, x20, [sp,#16] - 8d4c: a8c37bfd ldp x29, x30, [sp],#48 - 8d50: d65f03c0 ret - 8d54: a9017e7f stp xzr, xzr, [x19,#16] - 8d58: a9007e7f stp xzr, xzr, [x19] - 8d5c: a9027e7f stp xzr, xzr, [x19,#32] - 8d60: 5281ffe0 mov w0, #0xfff // #4095 - 8d64: b9400022 ldr w2, [x1] - 8d68: 72a1e000 movk w0, #0xf00, lsl #16 - 8d6c: 0a000040 and w0, w2, w0 - 8d70: b9001260 str w0, [x19,#16] - 8d74: b9400022 ldr w2, [x1] - 8d78: 36f00082 tbz w2, #30, 8d88 <__pthread_mutex_init+0x74> - 8d7c: 321c0000 orr w0, w0, #0x10 - 8d80: b9001260 str w0, [x19,#16] - 8d84: b9400022 ldr w2, [x1] - 8d88: 12040443 and w3, w2, #0x30000000 - 8d8c: 52a20004 mov w4, #0x10000000 // #268435456 - 8d90: 6b04007f cmp w3, w4 - 8d94: 54000360 b.eq 8e00 <__pthread_mutex_init+0xec> - 8d98: 52a40004 mov w4, #0x20000000 // #536870912 - 8d9c: 6b04007f cmp w3, w4 - 8da0: 540001e1 b.ne 8ddc <__pthread_mutex_init+0xc8> - 8da4: 321a0000 orr w0, w0, #0x40 - 8da8: b9001260 str w0, [x19,#16] - 8dac: b9400020 ldr w0, [x1] - 8db0: d34c5c00 ubfx x0, x0, #12, #12 - 8db4: 350000e0 cbnz w0, 8dd0 <__pthread_mutex_init+0xbc> - 8db8: 90000154 adrp x20, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 8dbc: b9427e80 ldr w0, [x20,#636] - 8dc0: 3100041f cmn w0, #0x1 - 8dc4: 540002c0 b.eq 8e1c <__pthread_mutex_init+0x108> - 8dc8: 6b1f001f cmp w0, wzr - 8dcc: 1a9fa000 csel w0, w0, wzr, ge - 8dd0: 530d3000 lsl w0, w0, #19 - 8dd4: b9000260 str w0, [x19] - 8dd8: b9400022 ldr w2, [x1] - 8ddc: 7202045f tst w2, #0xc0000000 - 8de0: 52800000 mov w0, #0x0 // #0 - 8de4: 54fffb20 b.eq 8d48 <__pthread_mutex_init+0x34> - 8de8: b9401261 ldr w1, [x19,#16] - 8dec: 32190021 orr w1, w1, #0x80 - 8df0: b9001261 str w1, [x19,#16] - 8df4: a94153f3 ldp x19, x20, [sp,#16] - 8df8: a8c37bfd ldp x29, x30, [sp],#48 - 8dfc: d65f03c0 ret - 8e00: 321b0000 orr w0, w0, #0x20 - 8e04: b9001260 str w0, [x19,#16] - 8e08: b9400022 ldr w2, [x1] - 8e0c: 17fffff4 b 8ddc <__pthread_mutex_init+0xc8> - 8e10: d0000041 adrp x1, 12000 <__pthread_current_priority+0xa8> - 8e14: 912ee021 add x1, x1, #0xbb8 - 8e18: 17ffffc4 b 8d28 <__pthread_mutex_init+0x14> - 8e1c: f90017a1 str x1, [x29,#40] - 8e20: 9400237f bl 11c1c <__init_sched_fifo_prio> - 8e24: b9427e80 ldr w0, [x20,#636] - 8e28: f94017a1 ldr x1, [x29,#40] - 8e2c: 17ffffe7 b 8dc8 <__pthread_mutex_init+0xb4> - -0000000000008e30 <__pthread_mutex_destroy>: - 8e30: b9401001 ldr w1, [x0,#16] - 8e34: 372000c1 tbnz w1, #4, 8e4c <__pthread_mutex_destroy+0x1c> - 8e38: b9400c02 ldr w2, [x0,#12] - 8e3c: 52800201 mov w1, #0x10 // #16 - 8e40: 34000062 cbz w2, 8e4c <__pthread_mutex_destroy+0x1c> - 8e44: 2a0103e0 mov w0, w1 - 8e48: d65f03c0 ret - 8e4c: 52800001 mov w1, #0x0 // #0 - 8e50: 12800002 mov w2, #0xffffffff // #-1 - 8e54: b9001002 str w2, [x0,#16] - 8e58: 2a0103e0 mov w0, w1 - 8e5c: d65f03c0 ret - -0000000000008e60 <__pthread_mutex_lock_full>: - 8e60: a9bb7bfd stp x29, x30, [sp,#-80]! - 8e64: 910003fd mov x29, sp - 8e68: a9025bf5 stp x21, x22, [sp,#32] - 8e6c: a90153f3 stp x19, x20, [sp,#16] - 8e70: a90363f7 stp x23, x24, [sp,#48] - 8e74: d53bd056 mrs x22, tpidr_el0 - 8e78: b9401001 ldr w1, [x0,#16] - 8e7c: d11bc2d6 sub x22, x22, #0x6f0 - 8e80: 12001822 and w2, w1, #0x7f - 8e84: 51004042 sub w2, w2, #0x10 - 8e88: b940d2d5 ldr w21, [x22,#208] - 8e8c: 7100cc5f cmp w2, #0x33 - 8e90: 54000109 b.ls 8eb0 <__pthread_mutex_lock_full+0x50> - 8e94: 528002d4 mov w20, #0x16 // #22 - 8e98: 2a1403e0 mov w0, w20 - 8e9c: a94153f3 ldp x19, x20, [sp,#16] - 8ea0: a9425bf5 ldp x21, x22, [sp,#32] - 8ea4: a94363f7 ldp x23, x24, [sp,#48] - 8ea8: a8c57bfd ldp x29, x30, [sp],#80 - 8eac: d65f03c0 ret - 8eb0: aa0003f3 mov x19, x0 - 8eb4: d0000040 adrp x0, 12000 <__pthread_current_priority+0xa8> - 8eb8: 912f0000 add x0, x0, #0xbc0 - 8ebc: 78625800 ldrh w0, [x0,w2,uxtw #1] - 8ec0: 10000062 adr x2, 8ecc <__pthread_mutex_lock_full+0x6c> - 8ec4: 8b20a840 add x0, x2, w0, sxth #2 - 8ec8: d61f0000 br x0 - 8ecc: b9400a60 ldr w0, [x19,#8] - 8ed0: b9400263 ldr w3, [x19] - 8ed4: 6b15001f cmp w0, w21 - 8ed8: 54001da0 b.eq 928c <__pthread_mutex_lock_full+0x42c> - 8edc: 12800016 mov w22, #0xffffffff // #-1 - 8ee0: 53137c74 lsr w20, w3, #19 - 8ee4: 9400241d bl 11f58 <__pthread_current_priority> - 8ee8: 6b00029f cmp w20, w0 - 8eec: 5400204b b.lt 92f4 <__pthread_mutex_lock_full+0x494> - 8ef0: 2a1603e0 mov w0, w22 - 8ef4: 2a1403e1 mov w1, w20 - 8ef8: 94002358 bl 11c58 <__pthread_tpp_change_priority> - 8efc: 35001f80 cbnz w0, 92ec <__pthread_mutex_lock_full+0x48c> - 8f00: 910143a5 add x5, x29, #0x50 - 8f04: 530d3284 lsl w4, w20, #19 - 8f08: 32000089 orr w9, w4, #0x1 - 8f0c: 2a0403e0 mov w0, w4 - 8f10: b81fcca4 str w4, [x5,#-4]! - 8f14: 885ffe61 ldaxr w1, [x19] - 8f18: 6b00003f cmp w1, w0 - 8f1c: 54000061 b.ne 8f28 <__pthread_mutex_lock_full+0xc8> - 8f20: 88027e69 stxr w2, w9, [x19] - 8f24: 35ffff82 cbnz w2, 8f14 <__pthread_mutex_lock_full+0xb4> - 8f28: 54000040 b.eq 8f30 <__pthread_mutex_lock_full+0xd0> - 8f2c: b9004fa1 str w1, [x29,#76] - 8f30: b9404fa0 ldr w0, [x29,#76] - 8f34: 6b00009f cmp w4, w0 - 8f38: 540004c0 b.eq 8fd0 <__pthread_mutex_lock_full+0x170> - 8f3c: 321f0087 orr w7, w4, #0x2 - 8f40: 93407cea sxtw x10, w7 - 8f44: b9004fa9 str w9, [x29,#76] - 8f48: b94000a0 ldr w0, [x5] - 8f4c: 885ffe63 ldaxr w3, [x19] - 8f50: 6b00007f cmp w3, w0 - 8f54: 54000061 b.ne 8f60 <__pthread_mutex_lock_full+0x100> - 8f58: 88017e67 stxr w1, w7, [x19] - 8f5c: 35ffff81 cbnz w1, 8f4c <__pthread_mutex_lock_full+0xec> - 8f60: 54000040 b.eq 8f68 <__pthread_mutex_lock_full+0x108> - 8f64: b90000a3 str w3, [x5] - 8f68: b9404fa3 ldr w3, [x29,#76] - 8f6c: 120d3060 and w0, w3, #0xfff80000 - 8f70: 6b04001f cmp w0, w4 - 8f74: 54001581 b.ne 9224 <__pthread_mutex_lock_full+0x3c4> - 8f78: 6b03009f cmp w4, w3 - 8f7c: 54000120 b.eq 8fa0 <__pthread_mutex_lock_full+0x140> - 8f80: b9401266 ldr w6, [x19,#16] - 8f84: aa1303e0 mov x0, x19 - 8f88: aa0a03e2 mov x2, x10 - 8f8c: d2800003 mov x3, #0x0 // #0 - 8f90: 2a2603e1 mvn w1, w6 - 8f94: d2800c48 mov x8, #0x62 // #98 - 8f98: 92790021 and x1, x1, #0x80 - 8f9c: d4000001 svc #0x0 - 8fa0: b9004fa4 str w4, [x29,#76] - 8fa4: b94000a0 ldr w0, [x5] - 8fa8: 885ffe63 ldaxr w3, [x19] - 8fac: 6b00007f cmp w3, w0 - 8fb0: 54000061 b.ne 8fbc <__pthread_mutex_lock_full+0x15c> - 8fb4: 88017e67 stxr w1, w7, [x19] - 8fb8: 35ffff81 cbnz w1, 8fa8 <__pthread_mutex_lock_full+0x148> - 8fbc: 54000040 b.eq 8fc4 <__pthread_mutex_lock_full+0x164> - 8fc0: b90000a3 str w3, [x5] - 8fc4: b9404fa0 ldr w0, [x29,#76] - 8fc8: 6b00009f cmp w4, w0 - 8fcc: 54fffbc1 b.ne 8f44 <__pthread_mutex_lock_full+0xe4> - 8fd0: 52800020 mov w0, #0x1 // #1 - 8fd4: b9000660 str w0, [x19,#4] - 8fd8: b9400e60 ldr w0, [x19,#12] - 8fdc: 52800014 mov w20, #0x0 // #0 - 8fe0: b9000a75 str w21, [x19,#8] - 8fe4: 11000400 add w0, w0, #0x1 - 8fe8: b9000e60 str w0, [x19,#12] - 8fec: 2a1403e0 mov w0, w20 - 8ff0: a94153f3 ldp x19, x20, [sp,#16] - 8ff4: a9425bf5 ldp x21, x22, [sp,#32] - 8ff8: a94363f7 ldp x23, x24, [sp,#48] - 8ffc: a8c57bfd ldp x29, x30, [sp],#80 - 9000: d65f03c0 ret - 9004: 121c0024 and w4, w1, #0x10 - 9008: 36200081 tbz w1, #4, 9018 <__pthread_mutex_lock_full+0x1b8> - 900c: 91008260 add x0, x19, #0x20 - 9010: b2400000 orr x0, x0, #0x1 - 9014: f9007ac0 str x0, [x22,#240] - 9018: b9400260 ldr w0, [x19] - 901c: 12007400 and w0, w0, #0x3fffffff - 9020: 6b0002bf cmp w21, w0 - 9024: 540014a0 b.eq 92b8 <__pthread_mutex_lock_full+0x458> - 9028: b9004fbf str wzr, [x29,#76] - 902c: 885ffe60 ldaxr w0, [x19] - 9030: 6b1f001f cmp w0, wzr - 9034: 54000061 b.ne 9040 <__pthread_mutex_lock_full+0x1e0> - 9038: 88017e75 stxr w1, w21, [x19] - 903c: 35ffff81 cbnz w1, 902c <__pthread_mutex_lock_full+0x1cc> - 9040: 540011e1 b.ne 927c <__pthread_mutex_lock_full+0x41c> - 9044: b9404fa0 ldr w0, [x29,#76] - 9048: 34000a40 cbz w0, 9190 <__pthread_mutex_lock_full+0x330> - 904c: d28000c1 mov x1, #0x6 // #6 - 9050: 350000c4 cbnz w4, 9068 <__pthread_mutex_lock_full+0x208> - 9054: b9401261 ldr w1, [x19,#16] - 9058: 528010c0 mov w0, #0x86 // #134 - 905c: 12190021 and w1, w1, #0x80 - 9060: 4a000021 eor w1, w1, w0 - 9064: 93407c21 sxtw x1, w1 - 9068: aa1303e0 mov x0, x19 - 906c: d2800022 mov x2, #0x1 // #1 - 9070: d2800003 mov x3, #0x0 // #0 - 9074: d2800c48 mov x8, #0x62 // #98 - 9078: d4000001 svc #0x0 - 907c: 3140041f cmn w0, #0x1, lsl #12 - 9080: 54000089 b.ls 9090 <__pthread_mutex_lock_full+0x230> - 9084: 121a7800 and w0, w0, #0xffffffdf - 9088: 31008c1f cmn w0, #0x23 - 908c: 54000f20 b.eq 9270 <__pthread_mutex_lock_full+0x410> - 9090: b9400260 ldr w0, [x19] - 9094: 36f007e0 tbz w0, #30, 9190 <__pthread_mutex_lock_full+0x330> - 9098: 910133a5 add x5, x29, #0x4c - 909c: b9004fa0 str w0, [x29,#76] - 90a0: 12017800 and w0, w0, #0xbfffffff - 90a4: b94000a2 ldr w2, [x5] - 90a8: 885ffe61 ldaxr w1, [x19] - 90ac: 6b02003f cmp w1, w2 - 90b0: 54000061 b.ne 90bc <__pthread_mutex_lock_full+0x25c> - 90b4: 88037e60 stxr w3, w0, [x19] - 90b8: 35ffff83 cbnz w3, 90a8 <__pthread_mutex_lock_full+0x248> - 90bc: 540012a0 b.eq 9310 <__pthread_mutex_lock_full+0x4b0> - 90c0: b90000a1 str w1, [x5] - 90c4: b9400260 ldr w0, [x19] - 90c8: 17fffff5 b 909c <__pthread_mutex_lock_full+0x23c> - 90cc: 91008277 add x23, x19, #0x20 - 90d0: f9007ad7 str x23, [x22,#240] - 90d4: 321f77f8 mov w24, #0x7ffffffe // #2147483646 - 90d8: b9400260 ldr w0, [x19] - 90dc: 12020014 and w20, w0, #0x40000000 - 90e0: 35000a74 cbnz w20, 922c <__pthread_mutex_lock_full+0x3cc> - 90e4: 12007400 and w0, w0, #0x3fffffff - 90e8: 6b0002bf cmp w21, w0 - 90ec: 54000380 b.eq 915c <__pthread_mutex_lock_full+0x2fc> - 90f0: b9004fbf str wzr, [x29,#76] - 90f4: 885ffe62 ldaxr w2, [x19] - 90f8: 6b1f005f cmp w2, wzr - 90fc: 54000061 b.ne 9108 <__pthread_mutex_lock_full+0x2a8> - 9100: 88007e75 stxr w0, w21, [x19] - 9104: 35ffff80 cbnz w0, 90f4 <__pthread_mutex_lock_full+0x294> - 9108: 54000680 b.eq 91d8 <__pthread_mutex_lock_full+0x378> - 910c: 52801001 mov w1, #0x80 // #128 - 9110: aa1303e0 mov x0, x19 - 9114: b9004fa2 str w2, [x29,#76] - 9118: 94001a4e bl fa50 <__lll_robust_lock_wait> - 911c: b9400a61 ldr w1, [x19,#8] - 9120: 6b18003f cmp w1, w24 - 9124: 54000620 b.eq 91e8 <__pthread_mutex_lock_full+0x388> - 9128: 12020014 and w20, w0, #0x40000000 - 912c: 37f7fda0 tbnz w0, #30, 90e0 <__pthread_mutex_lock_full+0x280> - 9130: aa1603e0 mov x0, x22 - 9134: 52800021 mov w1, #0x1 // #1 - 9138: b9000661 str w1, [x19,#4] - 913c: f84e0c01 ldr x1, [x0,#224]! - 9140: 927ff822 and x2, x1, #0xfffffffffffffffe - 9144: f81f8057 str x23, [x2,#-8] - 9148: f9001261 str x1, [x19,#32] - 914c: f9000e60 str x0, [x19,#24] - 9150: f90072d7 str x23, [x22,#224] - 9154: f9007adf str xzr, [x22,#240] - 9158: 17ffffa0 b 8fd8 <__pthread_mutex_lock_full+0x178> - 915c: b9401260 ldr w0, [x19,#16] - 9160: 12001800 and w0, w0, #0x7f - 9164: 7100481f cmp w0, #0x12 - 9168: 54001320 b.eq 93cc <__pthread_mutex_lock_full+0x56c> - 916c: 7100441f cmp w0, #0x11 - 9170: 54fffc01 b.ne 90f0 <__pthread_mutex_lock_full+0x290> - 9174: f9007adf str xzr, [x22,#240] - 9178: b9400660 ldr w0, [x19,#4] - 917c: 3100041f cmn w0, #0x1 - 9180: 54000980 b.eq 92b0 <__pthread_mutex_lock_full+0x450> - 9184: 11000400 add w0, w0, #0x1 - 9188: b9000660 str w0, [x19,#4] - 918c: 17ffff98 b 8fec <__pthread_mutex_lock_full+0x18c> - 9190: 34fff204 cbz w4, 8fd0 <__pthread_mutex_lock_full+0x170> - 9194: b9400a61 ldr w1, [x19,#8] - 9198: 321f77e0 mov w0, #0x7ffffffe // #2147483646 - 919c: 6b00003f cmp w1, w0 - 91a0: 54001020 b.eq 93a4 <__pthread_mutex_lock_full+0x544> - 91a4: aa1603e0 mov x0, x22 - 91a8: 52800021 mov w1, #0x1 // #1 - 91ac: b9000661 str w1, [x19,#4] - 91b0: 91008262 add x2, x19, #0x20 - 91b4: b2400043 orr x3, x2, #0x1 - 91b8: f84e0c01 ldr x1, [x0,#224]! - 91bc: 927ff824 and x4, x1, #0xfffffffffffffffe - 91c0: f81f8082 str x2, [x4,#-8] - 91c4: f9001261 str x1, [x19,#32] - 91c8: f9000e60 str x0, [x19,#24] - 91cc: f90072c3 str x3, [x22,#224] - 91d0: f9007adf str xzr, [x22,#240] - 91d4: 17ffff81 b 8fd8 <__pthread_mutex_lock_full+0x178> - 91d8: b9400a61 ldr w1, [x19,#8] - 91dc: 321f77e0 mov w0, #0x7ffffffe // #2147483646 - 91e0: 6b00003f cmp w1, w0 - 91e4: 54fffa61 b.ne 9130 <__pthread_mutex_lock_full+0x2d0> - 91e8: b900067f str wzr, [x19,#4] - 91ec: 52800001 mov w1, #0x0 // #0 - 91f0: 885f7e60 ldxr w0, [x19] - 91f4: 8802fe61 stlxr w2, w1, [x19] - 91f8: 35ffffc2 cbnz w2, 91f0 <__pthread_mutex_lock_full+0x390> - 91fc: 7100041f cmp w0, #0x1 - 9200: 54000c4c b.gt 9388 <__pthread_mutex_lock_full+0x528> - 9204: f9007adf str xzr, [x22,#240] - 9208: 52801074 mov w20, #0x83 // #131 - 920c: 2a1403e0 mov w0, w20 - 9210: a94153f3 ldp x19, x20, [sp,#16] - 9214: a9425bf5 ldp x21, x22, [sp,#32] - 9218: a94363f7 ldp x23, x24, [sp,#48] - 921c: a8c57bfd ldp x29, x30, [sp],#80 - 9220: d65f03c0 ret - 9224: 2a1403f6 mov w22, w20 - 9228: 17ffff2e b 8ee0 <__pthread_mutex_lock_full+0x80> - 922c: 12010001 and w1, w0, #0x80000000 - 9230: b9004fa0 str w0, [x29,#76] - 9234: 2a150021 orr w1, w1, w21 - 9238: 2a0003e2 mov w2, w0 - 923c: 885ffe63 ldaxr w3, [x19] - 9240: 6b02007f cmp w3, w2 - 9244: 54000061 b.ne 9250 <__pthread_mutex_lock_full+0x3f0> - 9248: 88047e61 stxr w4, w1, [x19] - 924c: 35ffff84 cbnz w4, 923c <__pthread_mutex_lock_full+0x3dc> - 9250: 54000040 b.eq 9258 <__pthread_mutex_lock_full+0x3f8> - 9254: b9004fa3 str w3, [x29,#76] - 9258: b9404fa1 ldr w1, [x29,#76] - 925c: 6b01001f cmp w0, w1 - 9260: 54000780 b.eq 9350 <__pthread_mutex_lock_full+0x4f0> - 9264: 2a0103e0 mov w0, w1 - 9268: 12020034 and w20, w1, #0x40000000 - 926c: 17ffff9d b 90e0 <__pthread_mutex_lock_full+0x280> - 9270: 94001dfa bl 10a58 <__pause_nocancel> - 9274: 94001df9 bl 10a58 <__pause_nocancel> - 9278: 17fffffe b 9270 <__pthread_mutex_lock_full+0x410> - 927c: b9004fa0 str w0, [x29,#76] - 9280: b9404fa0 ldr w0, [x29,#76] - 9284: 34fff860 cbz w0, 9190 <__pthread_mutex_lock_full+0x330> - 9288: 17ffff71 b 904c <__pthread_mutex_lock_full+0x1ec> - 928c: 12000421 and w1, w1, #0x3 - 9290: 52800474 mov w20, #0x23 // #35 - 9294: 7100083f cmp w1, #0x2 - 9298: 54ffeaa0 b.eq 8fec <__pthread_mutex_lock_full+0x18c> - 929c: 7100043f cmp w1, #0x1 - 92a0: 54ffe1e1 b.ne 8edc <__pthread_mutex_lock_full+0x7c> - 92a4: b9400660 ldr w0, [x19,#4] - 92a8: 3100041f cmn w0, #0x1 - 92ac: 54000181 b.ne 92dc <__pthread_mutex_lock_full+0x47c> - 92b0: 52800174 mov w20, #0xb // #11 - 92b4: 17ffff4e b 8fec <__pthread_mutex_lock_full+0x18c> - 92b8: 12000421 and w1, w1, #0x3 - 92bc: 7100083f cmp w1, #0x2 - 92c0: 54000860 b.eq 93cc <__pthread_mutex_lock_full+0x56c> - 92c4: 7100043f cmp w1, #0x1 - 92c8: 54ffeb01 b.ne 9028 <__pthread_mutex_lock_full+0x1c8> - 92cc: f9007adf str xzr, [x22,#240] - 92d0: b9400660 ldr w0, [x19,#4] - 92d4: 3100041f cmn w0, #0x1 - 92d8: 54fffec0 b.eq 92b0 <__pthread_mutex_lock_full+0x450> - 92dc: 11000400 add w0, w0, #0x1 - 92e0: 52800014 mov w20, #0x0 // #0 - 92e4: b9000660 str w0, [x19,#4] - 92e8: 17ffff41 b 8fec <__pthread_mutex_lock_full+0x18c> - 92ec: 2a0003f4 mov w20, w0 - 92f0: 17ffff3f b 8fec <__pthread_mutex_lock_full+0x18c> - 92f4: 310006df cmn w22, #0x1 - 92f8: 528002d4 mov w20, #0x16 // #22 - 92fc: 54ffe780 b.eq 8fec <__pthread_mutex_lock_full+0x18c> - 9300: 2a1603e0 mov w0, w22 - 9304: 12800001 mov w1, #0xffffffff // #-1 - 9308: 94002254 bl 11c58 <__pthread_tpp_change_priority> - 930c: 17ffff38 b 8fec <__pthread_mutex_lock_full+0x18c> - 9310: aa1603e0 mov x0, x22 - 9314: 52800021 mov w1, #0x1 // #1 - 9318: b9000661 str w1, [x19,#4] - 931c: 12b00001 mov w1, #0x7fffffff // #2147483647 - 9320: b9000a61 str w1, [x19,#8] - 9324: 91008262 add x2, x19, #0x20 - 9328: b2400043 orr x3, x2, #0x1 - 932c: 52801054 mov w20, #0x82 // #130 - 9330: f84e0c01 ldr x1, [x0,#224]! - 9334: 927ff824 and x4, x1, #0xfffffffffffffffe - 9338: f81f8082 str x2, [x4,#-8] - 933c: f9001261 str x1, [x19,#32] - 9340: f9000e60 str x0, [x19,#24] - 9344: f90072c3 str x3, [x22,#224] - 9348: f9007adf str xzr, [x22,#240] - 934c: 17ffff28 b 8fec <__pthread_mutex_lock_full+0x18c> - 9350: aa1603e0 mov x0, x22 - 9354: 52800021 mov w1, #0x1 // #1 - 9358: b9000661 str w1, [x19,#4] - 935c: 12b00001 mov w1, #0x7fffffff // #2147483647 - 9360: b9000a61 str w1, [x19,#8] - 9364: 52801054 mov w20, #0x82 // #130 - 9368: f84e0c01 ldr x1, [x0,#224]! - 936c: 927ff822 and x2, x1, #0xfffffffffffffffe - 9370: f81f8057 str x23, [x2,#-8] - 9374: f9001261 str x1, [x19,#32] - 9378: f9000e60 str x0, [x19,#24] - 937c: f90072d7 str x23, [x22,#224] - 9380: f9007adf str xzr, [x22,#240] - 9384: 17ffff1a b 8fec <__pthread_mutex_lock_full+0x18c> - 9388: d2800021 mov x1, #0x1 // #1 - 938c: aa1303e0 mov x0, x19 - 9390: aa0103e2 mov x2, x1 - 9394: d2800003 mov x3, #0x0 // #0 - 9398: d2800c48 mov x8, #0x62 // #98 - 939c: d4000001 svc #0x0 - 93a0: 17ffff99 b 9204 <__pthread_mutex_lock_full+0x3a4> - 93a4: d2800002 mov x2, #0x0 // #0 - 93a8: b900067f str wzr, [x19,#4] - 93ac: aa1303e0 mov x0, x19 - 93b0: d28000e1 mov x1, #0x7 // #7 - 93b4: aa0203e3 mov x3, x2 - 93b8: d2800c48 mov x8, #0x62 // #98 - 93bc: d4000001 svc #0x0 - 93c0: 52801074 mov w20, #0x83 // #131 - 93c4: f9007ac2 str x2, [x22,#240] - 93c8: 17ffff09 b 8fec <__pthread_mutex_lock_full+0x18c> - 93cc: f9007adf str xzr, [x22,#240] - 93d0: 52800474 mov w20, #0x23 // #35 - 93d4: 17ffff06 b 8fec <__pthread_mutex_lock_full+0x18c> - -00000000000093d8 <__pthread_mutex_lock>: - 93d8: a9bc7bfd stp x29, x30, [sp,#-64]! - 93dc: 52802fe1 mov w1, #0x17f // #383 - 93e0: 910003fd mov x29, sp - 93e4: a90153f3 stp x19, x20, [sp,#16] - 93e8: f90013f5 str x21, [sp,#32] - 93ec: aa0003f3 mov x19, x0 - 93f0: b9401002 ldr w2, [x0,#16] - 93f4: 721e1043 ands w3, w2, #0x7c - 93f8: 0a010041 and w1, w2, w1 - 93fc: 540003c1 b.ne 9474 <__pthread_mutex_lock+0x9c> - 9400: 35000441 cbnz w1, 9488 <__pthread_mutex_lock+0xb0> - 9404: b9003fa1 str w1, [x29,#60] - 9408: 52800020 mov w0, #0x1 // #1 - 940c: 885ffe63 ldaxr w3, [x19] - 9410: 6b1f007f cmp w3, wzr - 9414: 54000061 b.ne 9420 <__pthread_mutex_lock+0x48> - 9418: 88017e60 stxr w1, w0, [x19] - 941c: 35ffff81 cbnz w1, 940c <__pthread_mutex_lock+0x34> - 9420: 54000120 b.eq 9444 <__pthread_mutex_lock+0x6c> - 9424: b9401261 ldr w1, [x19,#16] - 9428: d53bd042 mrs x2, tpidr_el0 - 942c: b9003fa3 str w3, [x29,#60] - 9430: 12190021 and w1, w1, #0x80 - 9434: aa1303e0 mov x0, x19 - 9438: d11bc054 sub x20, x2, #0x6f0 - 943c: 940018e2 bl f7c4 <__lll_lock_wait> - 9440: 14000003 b 944c <__pthread_mutex_lock+0x74> - 9444: d53bd042 mrs x2, tpidr_el0 - 9448: d11bc054 sub x20, x2, #0x6f0 - 944c: b9400e61 ldr w1, [x19,#12] - 9450: 52800000 mov w0, #0x0 // #0 - 9454: b940d282 ldr w2, [x20,#208] - 9458: 11000421 add w1, w1, #0x1 - 945c: b9000a62 str w2, [x19,#8] - 9460: b9000e61 str w1, [x19,#12] - 9464: a94153f3 ldp x19, x20, [sp,#16] - 9468: f94013f5 ldr x21, [sp,#32] - 946c: a8c47bfd ldp x29, x30, [sp],#64 - 9470: d65f03c0 ret - 9474: 97fffe7b bl 8e60 <__pthread_mutex_lock_full> - 9478: f94013f5 ldr x21, [sp,#32] - 947c: a94153f3 ldp x19, x20, [sp,#16] - 9480: a8c47bfd ldp x29, x30, [sp],#64 - 9484: d65f03c0 ret - 9488: 12001841 and w1, w2, #0x7f - 948c: 7100043f cmp w1, #0x1 - 9490: 54000381 b.ne 9500 <__pthread_mutex_lock+0x128> - 9494: d53bd042 mrs x2, tpidr_el0 - 9498: b9400804 ldr w4, [x0,#8] - 949c: d11bc054 sub x20, x2, #0x6f0 - 94a0: b940d282 ldr w2, [x20,#208] - 94a4: 6b02009f cmp w4, w2 - 94a8: 540001e0 b.eq 94e4 <__pthread_mutex_lock+0x10c> - 94ac: b9003fa3 str w3, [x29,#60] - 94b0: 885ffe62 ldaxr w2, [x19] - 94b4: 6b1f005f cmp w2, wzr - 94b8: 54000061 b.ne 94c4 <__pthread_mutex_lock+0xec> - 94bc: 88037e61 stxr w3, w1, [x19] - 94c0: 35ffff83 cbnz w3, 94b0 <__pthread_mutex_lock+0xd8> - 94c4: 540000a0 b.eq 94d8 <__pthread_mutex_lock+0x100> - 94c8: b9401261 ldr w1, [x19,#16] - 94cc: b9003fa2 str w2, [x29,#60] - 94d0: 12190021 and w1, w1, #0x80 - 94d4: 940018bc bl f7c4 <__lll_lock_wait> - 94d8: 52800020 mov w0, #0x1 // #1 - 94dc: b9000660 str w0, [x19,#4] - 94e0: 17ffffdb b 944c <__pthread_mutex_lock+0x74> - 94e4: b9400400 ldr w0, [x0,#4] - 94e8: 3100041f cmn w0, #0x1 - 94ec: 540002e0 b.eq 9548 <__pthread_mutex_lock+0x170> - 94f0: 11000401 add w1, w0, #0x1 - 94f4: 2a0303e0 mov w0, w3 - 94f8: b9000661 str w1, [x19,#4] - 94fc: 17ffffda b 9464 <__pthread_mutex_lock+0x8c> - 9500: 71000c3f cmp w1, #0x3 - 9504: 54000881 b.ne 9614 <__pthread_mutex_lock+0x23c> - 9508: f0000140 adrp x0, 34000 <__GI___pthread_keys+0x3d78> - 950c: b9432c00 ldr w0, [x0,#812] - 9510: 35000200 cbnz w0, 9550 <__pthread_mutex_lock+0x178> - 9514: d53bd042 mrs x2, tpidr_el0 - 9518: b9003fbf str wzr, [x29,#60] - 951c: 52800020 mov w0, #0x1 // #1 - 9520: 885ffe63 ldaxr w3, [x19] - 9524: 6b1f007f cmp w3, wzr - 9528: 54000061 b.ne 9534 <__pthread_mutex_lock+0x15c> - 952c: 88017e60 stxr w1, w0, [x19] - 9530: 35ffff81 cbnz w1, 9520 <__pthread_mutex_lock+0x148> - 9534: 54fff8a0 b.eq 9448 <__pthread_mutex_lock+0x70> - 9538: b9401261 ldr w1, [x19,#16] - 953c: b9003fa3 str w3, [x29,#60] - 9540: 12190021 and w1, w1, #0x80 - 9544: 17ffffbc b 9434 <__pthread_mutex_lock+0x5c> - 9548: 52800160 mov w0, #0xb // #11 - 954c: 17ffffc6 b 9464 <__pthread_mutex_lock+0x8c> - 9550: b9003fa3 str w3, [x29,#60] - 9554: 52800022 mov w2, #0x1 // #1 - 9558: 885ffe60 ldaxr w0, [x19] - 955c: 6b1f001f cmp w0, wzr - 9560: 54000061 b.ne 956c <__pthread_mutex_lock+0x194> - 9564: 88017e62 stxr w1, w2, [x19] - 9568: 35ffff81 cbnz w1, 9558 <__pthread_mutex_lock+0x180> - 956c: 1a9f17f5 cset w21, eq - 9570: 35fff6b5 cbnz w21, 9444 <__pthread_mutex_lock+0x6c> - 9574: b9401661 ldr w1, [x19,#20] - 9578: 52800c80 mov w0, #0x64 // #100 - 957c: 11001421 add w1, w1, #0x5 - 9580: 531f7821 lsl w1, w1, #1 - 9584: 7101903f cmp w1, #0x64 - 9588: 1a80d021 csel w1, w1, w0, le - 958c: 110006b5 add w21, w21, #0x1 - 9590: b9003fbf str wzr, [x29,#60] - 9594: 510006a0 sub w0, w21, #0x1 - 9598: 6b01001f cmp w0, w1 - 959c: 5400022a b.ge 95e0 <__pthread_mutex_lock+0x208> - 95a0: 885ffe60 ldaxr w0, [x19] - 95a4: 6b1f001f cmp w0, wzr - 95a8: 54000061 b.ne 95b4 <__pthread_mutex_lock+0x1dc> - 95ac: 88037e62 stxr w3, w2, [x19] - 95b0: 35ffff83 cbnz w3, 95a0 <__pthread_mutex_lock+0x1c8> - 95b4: 54fffec1 b.ne 958c <__pthread_mutex_lock+0x1b4> - 95b8: b9401661 ldr w1, [x19,#20] - 95bc: d53bd042 mrs x2, tpidr_el0 - 95c0: d11bc054 sub x20, x2, #0x6f0 - 95c4: 4b0102b5 sub w21, w21, w1 - 95c8: 11001ea0 add w0, w21, #0x7 - 95cc: 6b1f02bf cmp w21, wzr - 95d0: 1a95b015 csel w21, w0, w21, lt - 95d4: 0b950c35 add w21, w1, w21, asr #3 - 95d8: b9001675 str w21, [x19,#20] - 95dc: 17ffff9c b 944c <__pthread_mutex_lock+0x74> - 95e0: 52800020 mov w0, #0x1 // #1 - 95e4: 885ffe62 ldaxr w2, [x19] - 95e8: 6b1f005f cmp w2, wzr - 95ec: 54000061 b.ne 95f8 <__pthread_mutex_lock+0x220> - 95f0: 88017e60 stxr w1, w0, [x19] - 95f4: 35ffff81 cbnz w1, 95e4 <__pthread_mutex_lock+0x20c> - 95f8: 54fffe00 b.eq 95b8 <__pthread_mutex_lock+0x1e0> - 95fc: b9401261 ldr w1, [x19,#16] - 9600: aa1303e0 mov x0, x19 - 9604: b9003fa2 str w2, [x29,#60] - 9608: 12190021 and w1, w1, #0x80 - 960c: 9400186e bl f7c4 <__lll_lock_wait> - 9610: 17ffffea b 95b8 <__pthread_mutex_lock+0x1e0> - 9614: d53bd042 mrs x2, tpidr_el0 - 9618: b9400800 ldr w0, [x0,#8] - 961c: d11bc041 sub x1, x2, #0x6f0 - 9620: b940d021 ldr w1, [x1,#208] - 9624: 6b00003f cmp w1, w0 - 9628: 54fff781 b.ne 9518 <__pthread_mutex_lock+0x140> - 962c: 52800460 mov w0, #0x23 // #35 - 9630: 17ffff8d b 9464 <__pthread_mutex_lock+0x8c> - -0000000000009634 <__pthread_mutex_trylock>: - 9634: a9bb7bfd stp x29, x30, [sp,#-80]! - 9638: aa0003e4 mov x4, x0 - 963c: d53bd045 mrs x5, tpidr_el0 - 9640: 910003fd mov x29, sp - 9644: f9001bf7 str x23, [sp,#48] - 9648: d11bc0a5 sub x5, x5, #0x6f0 - 964c: a90153f3 stp x19, x20, [sp,#16] - 9650: a9025bf5 stp x21, x22, [sp,#32] - 9654: b940d0b7 ldr w23, [x5,#208] - 9658: b9401002 ldr w2, [x0,#16] - 965c: 52802fe0 mov w0, #0x17f // #383 - 9660: 0a000040 and w0, w2, w0 - 9664: 71008c1f cmp w0, #0x23 - 9668: 54000328 b.hi 96cc <__pthread_mutex_trylock+0x98> - 966c: 7100801f cmp w0, #0x20 - 9670: 54000542 b.cs 9718 <__pthread_mutex_trylock+0xe4> - 9674: 71000c1f cmp w0, #0x3 - 9678: 54001008 b.hi 9878 <__pthread_mutex_trylock+0x244> - 967c: 7100081f cmp w0, #0x2 - 9680: 54000962 b.cs 97ac <__pthread_mutex_trylock+0x178> - 9684: 34000940 cbz w0, 97ac <__pthread_mutex_trylock+0x178> - 9688: 7100041f cmp w0, #0x1 - 968c: 54000821 b.ne 9790 <__pthread_mutex_trylock+0x15c> - 9690: b9400880 ldr w0, [x4,#8] - 9694: 6b17001f cmp w0, w23 - 9698: 540019e1 b.ne 99d4 <__pthread_mutex_trylock+0x3a0> - 969c: b9400480 ldr w0, [x4,#4] - 96a0: 3100041f cmn w0, #0x1 - 96a4: 540021c0 b.eq 9adc <__pthread_mutex_trylock+0x4a8> - 96a8: 11000400 add w0, w0, #0x1 - 96ac: 52800013 mov w19, #0x0 // #0 - 96b0: b9000480 str w0, [x4,#4] - 96b4: 2a1303e0 mov w0, w19 - 96b8: f9401bf7 ldr x23, [sp,#48] - 96bc: a94153f3 ldp x19, x20, [sp,#16] - 96c0: a9425bf5 ldp x21, x22, [sp,#32] - 96c4: a8c57bfd ldp x29, x30, [sp],#80 - 96c8: d65f03c0 ret - 96cc: 71010c1f cmp w0, #0x43 - 96d0: 540001a9 b.ls 9704 <__pthread_mutex_trylock+0xd0> - 96d4: 7104001f cmp w0, #0x100 - 96d8: 54000581 b.ne 9788 <__pthread_mutex_trylock+0x154> - 96dc: b9004fbf str wzr, [x29,#76] - 96e0: 52800020 mov w0, #0x1 // #1 - 96e4: 885ffc81 ldaxr w1, [x4] - 96e8: 6b1f003f cmp w1, wzr - 96ec: 54000061 b.ne 96f8 <__pthread_mutex_trylock+0xc4> - 96f0: 88027c80 stxr w2, w0, [x4] - 96f4: 35ffff82 cbnz w2, 96e4 <__pthread_mutex_trylock+0xb0> - 96f8: 540003a1 b.ne 976c <__pthread_mutex_trylock+0x138> - 96fc: 52800013 mov w19, #0x0 // #0 - 9700: 17ffffed b 96b4 <__pthread_mutex_trylock+0x80> - 9704: 7101001f cmp w0, #0x40 - 9708: 540006e2 b.cs 97e4 <__pthread_mutex_trylock+0x1b0> - 970c: 5100c000 sub w0, w0, #0x30 - 9710: 71000c1f cmp w0, #0x3 - 9714: 540003e8 b.hi 9790 <__pthread_mutex_trylock+0x15c> - 9718: 121c0046 and w6, w2, #0x10 - 971c: 36200082 tbz w2, #4, 972c <__pthread_mutex_trylock+0xf8> - 9720: 91008080 add x0, x4, #0x20 - 9724: b2400000 orr x0, x0, #0x1 - 9728: f90078a0 str x0, [x5,#240] - 972c: b9400080 ldr w0, [x4] - 9730: 12007400 and w0, w0, #0x3fffffff - 9734: 6b0002ff cmp w23, w0 - 9738: 54001c00 b.eq 9ab8 <__pthread_mutex_trylock+0x484> - 973c: b9004fbf str wzr, [x29,#76] - 9740: 885ffc80 ldaxr w0, [x4] - 9744: 6b1f001f cmp w0, wzr - 9748: 54000061 b.ne 9754 <__pthread_mutex_trylock+0x120> - 974c: 88017c97 stxr w1, w23, [x4] - 9750: 35ffff81 cbnz w1, 9740 <__pthread_mutex_trylock+0x10c> - 9754: 54000040 b.eq 975c <__pthread_mutex_trylock+0x128> - 9758: b9004fa0 str w0, [x29,#76] - 975c: b9404fa0 ldr w0, [x29,#76] - 9760: 34001580 cbz w0, 9a10 <__pthread_mutex_trylock+0x3dc> - 9764: 37f01840 tbnz w0, #30, 9a6c <__pthread_mutex_trylock+0x438> - 9768: f90078bf str xzr, [x5,#240] - 976c: 52800213 mov w19, #0x10 // #16 - 9770: f9401bf7 ldr x23, [sp,#48] - 9774: 2a1303e0 mov w0, w19 - 9778: a94153f3 ldp x19, x20, [sp,#16] - 977c: a9425bf5 ldp x21, x22, [sp,#32] - 9780: a8c57bfd ldp x29, x30, [sp],#80 - 9784: d65f03c0 ret - 9788: 7104041f cmp w0, #0x101 - 978c: 54fff820 b.eq 9690 <__pthread_mutex_trylock+0x5c> - 9790: 528002d3 mov w19, #0x16 // #22 - 9794: f9401bf7 ldr x23, [sp,#48] - 9798: 2a1303e0 mov w0, w19 - 979c: a94153f3 ldp x19, x20, [sp,#16] - 97a0: a9425bf5 ldp x21, x22, [sp,#32] - 97a4: a8c57bfd ldp x29, x30, [sp],#80 - 97a8: d65f03c0 ret - 97ac: b9004fbf str wzr, [x29,#76] - 97b0: 52800020 mov w0, #0x1 // #1 - 97b4: 885ffc81 ldaxr w1, [x4] - 97b8: 6b1f003f cmp w1, wzr - 97bc: 54000061 b.ne 97c8 <__pthread_mutex_trylock+0x194> - 97c0: 88027c80 stxr w2, w0, [x4] - 97c4: 35ffff82 cbnz w2, 97b4 <__pthread_mutex_trylock+0x180> - 97c8: 54fffd21 b.ne 976c <__pthread_mutex_trylock+0x138> - 97cc: b9400c80 ldr w0, [x4,#12] - 97d0: 52800013 mov w19, #0x0 // #0 - 97d4: b9000897 str w23, [x4,#8] - 97d8: 11000400 add w0, w0, #0x1 - 97dc: b9000c80 str w0, [x4,#12] - 97e0: 17ffffb5 b 96b4 <__pthread_mutex_trylock+0x80> - 97e4: b9400880 ldr w0, [x4,#8] - 97e8: b9400081 ldr w1, [x4] - 97ec: 6b17001f cmp w0, w23 - 97f0: 540017a0 b.eq 9ae4 <__pthread_mutex_trylock+0x4b0> - 97f4: aa0403f5 mov x21, x4 - 97f8: 12800016 mov w22, #0xffffffff // #-1 - 97fc: 53137c34 lsr w20, w1, #19 - 9800: 940021d6 bl 11f58 <__pthread_current_priority> - 9804: 6b00029f cmp w20, w0 - 9808: 2a1403e1 mov w1, w20 - 980c: 2a1603e0 mov w0, w22 - 9810: 5400178b b.lt 9b00 <__pthread_mutex_trylock+0x4cc> - 9814: 94002111 bl 11c58 <__pthread_tpp_change_priority> - 9818: 530d3282 lsl w2, w20, #19 - 981c: 350017e0 cbnz w0, 9b18 <__pthread_mutex_trylock+0x4e4> - 9820: b9004fa2 str w2, [x29,#76] - 9824: 32000040 orr w0, w2, #0x1 - 9828: 2a0203e1 mov w1, w2 - 982c: 885ffea3 ldaxr w3, [x21] - 9830: 6b01007f cmp w3, w1 - 9834: 54000061 b.ne 9840 <__pthread_mutex_trylock+0x20c> - 9838: 88047ea0 stxr w4, w0, [x21] - 983c: 35ffff84 cbnz w4, 982c <__pthread_mutex_trylock+0x1f8> - 9840: 54000040 b.eq 9848 <__pthread_mutex_trylock+0x214> - 9844: b9004fa3 str w3, [x29,#76] - 9848: b9404fa1 ldr w1, [x29,#76] - 984c: 2a1403f6 mov w22, w20 - 9850: 6b01005f cmp w2, w1 - 9854: 120d3020 and w0, w1, #0xfff80000 - 9858: 54001640 b.eq 9b20 <__pthread_mutex_trylock+0x4ec> - 985c: 6b02001f cmp w0, w2 - 9860: 54fffce1 b.ne 97fc <__pthread_mutex_trylock+0x1c8> - 9864: 2a1403e0 mov w0, w20 - 9868: 12800001 mov w1, #0xffffffff // #-1 - 986c: 52800213 mov w19, #0x10 // #16 - 9870: 940020fa bl 11c58 <__pthread_tpp_change_priority> - 9874: 17ffff90 b 96b4 <__pthread_mutex_trylock+0x80> - 9878: 51004000 sub w0, w0, #0x10 - 987c: 71000c1f cmp w0, #0x3 - 9880: 54fff888 b.hi 9790 <__pthread_mutex_trylock+0x15c> - 9884: 91008087 add x7, x4, #0x20 - 9888: f90078a7 str x7, [x5,#240] - 988c: 321f77e3 mov w3, #0x7ffffffe // #2147483646 - 9890: b9400081 ldr w1, [x4] - 9894: 12020033 and w19, w1, #0x40000000 - 9898: 350007d3 cbnz w19, 9990 <__pthread_mutex_trylock+0x35c> - 989c: 12007421 and w1, w1, #0x3fffffff - 98a0: 6b0102ff cmp w23, w1 - 98a4: 54000360 b.eq 9910 <__pthread_mutex_trylock+0x2dc> - 98a8: b9004fbf str wzr, [x29,#76] - 98ac: 885ffc80 ldaxr w0, [x4] - 98b0: 6b1f001f cmp w0, wzr - 98b4: 54000061 b.ne 98c0 <__pthread_mutex_trylock+0x28c> - 98b8: 88017c97 stxr w1, w23, [x4] - 98bc: 35ffff81 cbnz w1, 98ac <__pthread_mutex_trylock+0x278> - 98c0: 54000040 b.eq 98c8 <__pthread_mutex_trylock+0x294> - 98c4: b9004fa0 str w0, [x29,#76] - 98c8: b9404fa1 ldr w1, [x29,#76] - 98cc: 340003c1 cbz w1, 9944 <__pthread_mutex_trylock+0x310> - 98d0: 12020033 and w19, w1, #0x40000000 - 98d4: 36f7f4a1 tbz w1, #30, 9768 <__pthread_mutex_trylock+0x134> - 98d8: b9400880 ldr w0, [x4,#8] - 98dc: 6b03001f cmp w0, w3 - 98e0: 54fffdc1 b.ne 9898 <__pthread_mutex_trylock+0x264> - 98e4: b900049f str wzr, [x4,#4] - 98e8: 6b0102ff cmp w23, w1 - 98ec: 540012a0 b.eq 9b40 <__pthread_mutex_trylock+0x50c> - 98f0: f90078bf str xzr, [x5,#240] - 98f4: 52801073 mov w19, #0x83 // #131 - 98f8: 2a1303e0 mov w0, w19 - 98fc: f9401bf7 ldr x23, [sp,#48] - 9900: a94153f3 ldp x19, x20, [sp,#16] - 9904: a9425bf5 ldp x21, x22, [sp,#32] - 9908: a8c57bfd ldp x29, x30, [sp],#80 - 990c: d65f03c0 ret - 9910: b9401080 ldr w0, [x4,#16] - 9914: 12001800 and w0, w0, #0x7f - 9918: 7100481f cmp w0, #0x12 - 991c: 54001480 b.eq 9bac <__pthread_mutex_trylock+0x578> - 9920: 7100441f cmp w0, #0x11 - 9924: 54fffc21 b.ne 98a8 <__pthread_mutex_trylock+0x274> - 9928: f90078bf str xzr, [x5,#240] - 992c: b9400480 ldr w0, [x4,#4] - 9930: 3100041f cmn w0, #0x1 - 9934: 54000d40 b.eq 9adc <__pthread_mutex_trylock+0x4a8> - 9938: 11000400 add w0, w0, #0x1 - 993c: b9000480 str w0, [x4,#4] - 9940: 17ffff5d b 96b4 <__pthread_mutex_trylock+0x80> - 9944: b9400882 ldr w2, [x4,#8] - 9948: 321f77e0 mov w0, #0x7ffffffe // #2147483646 - 994c: 6b00005f cmp w2, w0 - 9950: 54fffca0 b.eq 98e4 <__pthread_mutex_trylock+0x2b0> - 9954: aa0503e0 mov x0, x5 - 9958: f84e0c01 ldr x1, [x0,#224]! - 995c: 927ff822 and x2, x1, #0xfffffffffffffffe - 9960: f81f8047 str x7, [x2,#-8] - 9964: f9001081 str x1, [x4,#32] - 9968: 52800021 mov w1, #0x1 // #1 - 996c: f9000c80 str x0, [x4,#24] - 9970: f90070a7 str x7, [x5,#224] - 9974: f90078bf str xzr, [x5,#240] - 9978: b9000897 str w23, [x4,#8] - 997c: b9400c80 ldr w0, [x4,#12] - 9980: b9000481 str w1, [x4,#4] - 9984: 0b010000 add w0, w0, w1 - 9988: b9000c80 str w0, [x4,#12] - 998c: 17ffff4a b 96b4 <__pthread_mutex_trylock+0x80> - 9990: 12010020 and w0, w1, #0x80000000 - 9994: b9004fa1 str w1, [x29,#76] - 9998: 2a170000 orr w0, w0, w23 - 999c: 2a0103e2 mov w2, w1 - 99a0: 885ffc86 ldaxr w6, [x4] - 99a4: 6b0200df cmp w6, w2 - 99a8: 54000061 b.ne 99b4 <__pthread_mutex_trylock+0x380> - 99ac: 88087c80 stxr w8, w0, [x4] - 99b0: 35ffff88 cbnz w8, 99a0 <__pthread_mutex_trylock+0x36c> - 99b4: 54000040 b.eq 99bc <__pthread_mutex_trylock+0x388> - 99b8: b9004fa6 str w6, [x29,#76] - 99bc: b9404fa0 ldr w0, [x29,#76] - 99c0: 6b00003f cmp w1, w0 - 99c4: 54000d80 b.eq 9b74 <__pthread_mutex_trylock+0x540> - 99c8: 2a0003e1 mov w1, w0 - 99cc: 12020013 and w19, w0, #0x40000000 - 99d0: 17ffffb2 b 9898 <__pthread_mutex_trylock+0x264> - 99d4: b9004fbf str wzr, [x29,#76] - 99d8: 52800020 mov w0, #0x1 // #1 - 99dc: 885ffc81 ldaxr w1, [x4] - 99e0: 6b1f003f cmp w1, wzr - 99e4: 54000061 b.ne 99f0 <__pthread_mutex_trylock+0x3bc> - 99e8: 88027c80 stxr w2, w0, [x4] - 99ec: 35ffff82 cbnz w2, 99dc <__pthread_mutex_trylock+0x3a8> - 99f0: 54ffebe1 b.ne 976c <__pthread_mutex_trylock+0x138> - 99f4: b9400c81 ldr w1, [x4,#12] - 99f8: 52800013 mov w19, #0x0 // #0 - 99fc: b9000897 str w23, [x4,#8] - 9a00: 11000421 add w1, w1, #0x1 - 9a04: b9000480 str w0, [x4,#4] - 9a08: b9000c81 str w1, [x4,#12] - 9a0c: 17ffff2a b 96b4 <__pthread_mutex_trylock+0x80> - 9a10: 340001e6 cbz w6, 9a4c <__pthread_mutex_trylock+0x418> - 9a14: b9400881 ldr w1, [x4,#8] - 9a18: 321f77e0 mov w0, #0x7ffffffe // #2147483646 - 9a1c: 6b00003f cmp w1, w0 - 9a20: 54001020 b.eq 9c24 <__pthread_mutex_trylock+0x5f0> - 9a24: aa0503e0 mov x0, x5 - 9a28: 91008082 add x2, x4, #0x20 - 9a2c: b2400043 orr x3, x2, #0x1 - 9a30: f84e0c01 ldr x1, [x0,#224]! - 9a34: 927ff826 and x6, x1, #0xfffffffffffffffe - 9a38: f81f80c2 str x2, [x6,#-8] - 9a3c: f9001081 str x1, [x4,#32] - 9a40: f9000c80 str x0, [x4,#24] - 9a44: f90070a3 str x3, [x5,#224] - 9a48: f90078bf str xzr, [x5,#240] - 9a4c: b9400c80 ldr w0, [x4,#12] - 9a50: 52800021 mov w1, #0x1 // #1 - 9a54: b9000897 str w23, [x4,#8] - 9a58: 52800013 mov w19, #0x0 // #0 - 9a5c: 11000400 add w0, w0, #0x1 - 9a60: b9000481 str w1, [x4,#4] - 9a64: b9000c80 str w0, [x4,#12] - 9a68: 17ffff13 b 96b4 <__pthread_mutex_trylock+0x80> - 9a6c: d2800101 mov x1, #0x8 // #8 - 9a70: 350000c6 cbnz w6, 9a88 <__pthread_mutex_trylock+0x454> - 9a74: b9401081 ldr w1, [x4,#16] - 9a78: 52801100 mov w0, #0x88 // #136 - 9a7c: 12190021 and w1, w1, #0x80 - 9a80: 4a000021 eor w1, w1, w0 - 9a84: 93407c21 sxtw x1, w1 - 9a88: d2800002 mov x2, #0x0 // #0 - 9a8c: aa0403e0 mov x0, x4 - 9a90: aa0203e3 mov x3, x2 - 9a94: d2800c48 mov x8, #0x62 // #98 - 9a98: d4000001 svc #0x0 - 9a9c: 31002c1f cmn w0, #0xb - 9aa0: 540008c1 b.ne 9bb8 <__pthread_mutex_trylock+0x584> - 9aa4: 3140041f cmn w0, #0x1, lsl #12 - 9aa8: 54000889 b.ls 9bb8 <__pthread_mutex_trylock+0x584> - 9aac: f90078a2 str x2, [x5,#240] - 9ab0: 52800213 mov w19, #0x10 // #16 - 9ab4: 17ffff00 b 96b4 <__pthread_mutex_trylock+0x80> - 9ab8: 12000442 and w2, w2, #0x3 - 9abc: 7100085f cmp w2, #0x2 - 9ac0: 54000760 b.eq 9bac <__pthread_mutex_trylock+0x578> - 9ac4: 7100045f cmp w2, #0x1 - 9ac8: 54ffe3a1 b.ne 973c <__pthread_mutex_trylock+0x108> - 9acc: f90078bf str xzr, [x5,#240] - 9ad0: b9400480 ldr w0, [x4,#4] - 9ad4: 3100041f cmn w0, #0x1 - 9ad8: 54ffde81 b.ne 96a8 <__pthread_mutex_trylock+0x74> - 9adc: 52800173 mov w19, #0xb // #11 - 9ae0: 17fffef5 b 96b4 <__pthread_mutex_trylock+0x80> - 9ae4: 12000442 and w2, w2, #0x3 - 9ae8: 52800473 mov w19, #0x23 // #35 - 9aec: 7100085f cmp w2, #0x2 - 9af0: 54ffde20 b.eq 96b4 <__pthread_mutex_trylock+0x80> - 9af4: 7100045f cmp w2, #0x1 - 9af8: 54ffe7e1 b.ne 97f4 <__pthread_mutex_trylock+0x1c0> - 9afc: 17fffee8 b 969c <__pthread_mutex_trylock+0x68> - 9b00: 310006df cmn w22, #0x1 - 9b04: 528002d3 mov w19, #0x16 // #22 - 9b08: 54ffdd60 b.eq 96b4 <__pthread_mutex_trylock+0x80> - 9b0c: 12800001 mov w1, #0xffffffff // #-1 - 9b10: 94002052 bl 11c58 <__pthread_tpp_change_priority> - 9b14: 17fffee8 b 96b4 <__pthread_mutex_trylock+0x80> - 9b18: 2a0003f3 mov w19, w0 - 9b1c: 17fffee6 b 96b4 <__pthread_mutex_trylock+0x80> - 9b20: b9400ea0 ldr w0, [x21,#12] - 9b24: 52800021 mov w1, #0x1 // #1 - 9b28: b9000ab7 str w23, [x21,#8] - 9b2c: 52800013 mov w19, #0x0 // #0 - 9b30: 11000400 add w0, w0, #0x1 - 9b34: b90006a1 str w1, [x21,#4] - 9b38: b9000ea0 str w0, [x21,#12] - 9b3c: 17fffede b 96b4 <__pthread_mutex_trylock+0x80> - 9b40: 52800001 mov w1, #0x0 // #0 - 9b44: 885f7c80 ldxr w0, [x4] - 9b48: 8802fc81 stlxr w2, w1, [x4] - 9b4c: 35ffffc2 cbnz w2, 9b44 <__pthread_mutex_trylock+0x510> - 9b50: 7100041f cmp w0, #0x1 - 9b54: 54ffeced b.le 98f0 <__pthread_mutex_trylock+0x2bc> - 9b58: d2800021 mov x1, #0x1 // #1 - 9b5c: aa0403e0 mov x0, x4 - 9b60: aa0103e2 mov x2, x1 - 9b64: d2800003 mov x3, #0x0 // #0 - 9b68: d2800c48 mov x8, #0x62 // #98 - 9b6c: d4000001 svc #0x0 - 9b70: 17ffff60 b 98f0 <__pthread_mutex_trylock+0x2bc> - 9b74: aa0503e0 mov x0, x5 - 9b78: 52800021 mov w1, #0x1 // #1 - 9b7c: b9000481 str w1, [x4,#4] - 9b80: 12b00001 mov w1, #0x7fffffff // #2147483647 - 9b84: b9000881 str w1, [x4,#8] - 9b88: 52801053 mov w19, #0x82 // #130 - 9b8c: f84e0c01 ldr x1, [x0,#224]! - 9b90: 927ff822 and x2, x1, #0xfffffffffffffffe - 9b94: f81f8047 str x7, [x2,#-8] - 9b98: f9001081 str x1, [x4,#32] - 9b9c: f9000c80 str x0, [x4,#24] - 9ba0: f90070a7 str x7, [x5,#224] - 9ba4: f90078bf str xzr, [x5,#240] - 9ba8: 17fffec3 b 96b4 <__pthread_mutex_trylock+0x80> - 9bac: f90078bf str xzr, [x5,#240] - 9bb0: 52800473 mov w19, #0x23 // #35 - 9bb4: 17fffec0 b 96b4 <__pthread_mutex_trylock+0x80> - 9bb8: b9400080 ldr w0, [x4] - 9bbc: 36f7f2a0 tbz w0, #30, 9a10 <__pthread_mutex_trylock+0x3dc> - 9bc0: b9004fa0 str w0, [x29,#76] - 9bc4: 12017801 and w1, w0, #0xbfffffff - 9bc8: 885ffc82 ldaxr w2, [x4] - 9bcc: 6b00005f cmp w2, w0 - 9bd0: 54000061 b.ne 9bdc <__pthread_mutex_trylock+0x5a8> - 9bd4: 88037c81 stxr w3, w1, [x4] - 9bd8: 35ffff83 cbnz w3, 9bc8 <__pthread_mutex_trylock+0x594> - 9bdc: 54000060 b.eq 9be8 <__pthread_mutex_trylock+0x5b4> - 9be0: b9400080 ldr w0, [x4] - 9be4: 17fffff7 b 9bc0 <__pthread_mutex_trylock+0x58c> - 9be8: aa0503e0 mov x0, x5 - 9bec: 52800021 mov w1, #0x1 // #1 - 9bf0: b9000481 str w1, [x4,#4] - 9bf4: 12b00001 mov w1, #0x7fffffff // #2147483647 - 9bf8: b9000881 str w1, [x4,#8] - 9bfc: 91008081 add x1, x4, #0x20 - 9c00: 52801053 mov w19, #0x82 // #130 - 9c04: f84e0c02 ldr x2, [x0,#224]! - 9c08: 927ff843 and x3, x2, #0xfffffffffffffffe - 9c0c: f81f8061 str x1, [x3,#-8] - 9c10: f9001082 str x2, [x4,#32] - 9c14: f9000c80 str x0, [x4,#24] - 9c18: f90070a1 str x1, [x5,#224] - 9c1c: f90078bf str xzr, [x5,#240] - 9c20: 17fffea5 b 96b4 <__pthread_mutex_trylock+0x80> - 9c24: d2800002 mov x2, #0x0 // #0 - 9c28: b900049f str wzr, [x4,#4] - 9c2c: aa0403e0 mov x0, x4 - 9c30: d28000e1 mov x1, #0x7 // #7 - 9c34: aa0203e3 mov x3, x2 - 9c38: d2800c48 mov x8, #0x62 // #98 - 9c3c: d4000001 svc #0x0 - 9c40: 52801073 mov w19, #0x83 // #131 - 9c44: f90078a2 str x2, [x5,#240] - 9c48: 17fffe9b b 96b4 <__pthread_mutex_trylock+0x80> - -0000000000009c4c : - 9c4c: a9b77bfd stp x29, x30, [sp,#-144]! - 9c50: 52802fe2 mov w2, #0x17f // #383 - 9c54: 910003fd mov x29, sp - 9c58: a90153f3 stp x19, x20, [sp,#16] - 9c5c: a9025bf5 stp x21, x22, [sp,#32] - 9c60: a90363f7 stp x23, x24, [sp,#48] - 9c64: a9046bf9 stp x25, x26, [sp,#64] - 9c68: a90573fb stp x27, x28, [sp,#80] - 9c6c: fd0033e8 str d8, [sp,#96] - 9c70: d53bd054 mrs x20, tpidr_el0 - 9c74: b9401003 ldr w3, [x0,#16] - 9c78: d11bc294 sub x20, x20, #0x6f0 - 9c7c: aa0003f3 mov x19, x0 - 9c80: aa0103f5 mov x21, x1 - 9c84: 0a020062 and w2, w3, w2 - 9c88: 71008c5f cmp w2, #0x23 - 9c8c: b940d296 ldr w22, [x20,#208] - 9c90: 54000788 b.hi 9d80 - 9c94: 7100805f cmp w2, #0x20 - 9c98: 54000822 b.cs 9d9c - 9c9c: 7100085f cmp w2, #0x2 - 9ca0: 54001560 b.eq 9f4c - 9ca4: 54000f69 b.ls 9e90 - 9ca8: 71000c5f cmp w2, #0x3 - 9cac: 540015a0 b.eq 9f60 - 9cb0: 51004042 sub w2, w2, #0x10 - 9cb4: 71000c5f cmp w2, #0x3 - 9cb8: 54002ce8 b.hi a254 - 9cbc: 91008018 add x24, x0, #0x20 - 9cc0: f9007a98 str x24, [x20,#240] - 9cc4: 321f77f7 mov w23, #0x7ffffffe // #2147483646 - 9cc8: b9400002 ldr w2, [x0] - 9ccc: 12020040 and w0, w2, #0x40000000 - 9cd0: 35000360 cbnz w0, 9d3c - 9cd4: 12007442 and w2, w2, #0x3fffffff - 9cd8: 6b0202df cmp w22, w2 - 9cdc: 54001a60 b.eq a028 - 9ce0: b90083bf str wzr, [x29,#128] - 9ce4: 885ffe63 ldaxr w3, [x19] - 9ce8: 6b1f007f cmp w3, wzr - 9cec: 54000061 b.ne 9cf8 - 9cf0: 88007e76 stxr w0, w22, [x19] - 9cf4: 35ffff80 cbnz w0, 9ce4 - 9cf8: 54001b20 b.eq a05c - 9cfc: 52801002 mov w2, #0x80 // #128 - 9d00: aa1303e0 mov x0, x19 - 9d04: aa1503e1 mov x1, x21 - 9d08: b90083a3 str w3, [x29,#128] - 9d0c: 9400177b bl faf8 <__lll_robust_timedlock_wait> - 9d10: 2a0003e2 mov w2, w0 - 9d14: b9400a60 ldr w0, [x19,#8] - 9d18: 6b17001f cmp w0, w23 - 9d1c: 54002ae0 b.eq a278 - 9d20: 7100585f cmp w2, #0x16 - 9d24: 54003760 b.eq a410 - 9d28: 7101b85f cmp w2, #0x6e - 9d2c: 54003720 b.eq a410 - 9d30: 12020040 and w0, w2, #0x40000000 - 9d34: 36f019e2 tbz w2, #30, a070 - 9d38: 34fffce0 cbz w0, 9cd4 - 9d3c: 12010040 and w0, w2, #0x80000000 - 9d40: b90083a2 str w2, [x29,#128] - 9d44: 2a160000 orr w0, w0, w22 - 9d48: 2a0203e1 mov w1, w2 - 9d4c: 885ffe63 ldaxr w3, [x19] - 9d50: 6b01007f cmp w3, w1 - 9d54: 54000061 b.ne 9d60 - 9d58: 88047e60 stxr w4, w0, [x19] - 9d5c: 35ffff84 cbnz w4, 9d4c - 9d60: 54000040 b.eq 9d68 - 9d64: b90083a3 str w3, [x29,#128] - 9d68: b94083a0 ldr w0, [x29,#128] - 9d6c: 6b00005f cmp w2, w0 - 9d70: 54003880 b.eq a480 - 9d74: 2a0003e2 mov w2, w0 - 9d78: 12020000 and w0, w0, #0x40000000 - 9d7c: 17ffffd5 b 9cd0 - 9d80: 71010c5f cmp w2, #0x43 - 9d84: 54000b28 b.hi 9ee8 - 9d88: 7101005f cmp w2, #0x40 - 9d8c: 54001882 b.cs a09c - 9d90: 5100c042 sub w2, w2, #0x30 - 9d94: 71000c5f cmp w2, #0x3 - 9d98: 540025e8 b.hi a254 - 9d9c: 121c0064 and w4, w3, #0x10 - 9da0: 36200083 tbz w3, #4, 9db0 - 9da4: 91008260 add x0, x19, #0x20 - 9da8: b2400000 orr x0, x0, #0x1 - 9dac: f9007a80 str x0, [x20,#240] - 9db0: b9400260 ldr w0, [x19] - 9db4: 12007400 and w0, w0, #0x3fffffff - 9db8: 6b0002df cmp w22, w0 - 9dbc: 54002d40 b.eq a364 - 9dc0: b90083bf str wzr, [x29,#128] - 9dc4: 885ffe60 ldaxr w0, [x19] - 9dc8: 6b1f001f cmp w0, wzr - 9dcc: 54000061 b.ne 9dd8 - 9dd0: 88017e76 stxr w1, w22, [x19] - 9dd4: 35ffff81 cbnz w1, 9dc4 - 9dd8: 54000040 b.eq 9de0 - 9ddc: b90083a0 str w0, [x29,#128] - 9de0: b94083a0 ldr w0, [x29,#128] - 9de4: 340025e0 cbz w0, a2a0 - 9de8: d28000c1 mov x1, #0x6 // #6 - 9dec: 350000c4 cbnz w4, 9e04 - 9df0: b9401261 ldr w1, [x19,#16] - 9df4: 528010c0 mov w0, #0x86 // #134 - 9df8: 12190021 and w1, w1, #0x80 - 9dfc: 4a000021 eor w1, w1, w0 - 9e00: 93407c21 sxtw x1, w1 - 9e04: aa1303e0 mov x0, x19 - 9e08: d2800022 mov x2, #0x1 // #1 - 9e0c: aa1503e3 mov x3, x21 - 9e10: d2800c48 mov x8, #0x62 // #98 - 9e14: d4000001 svc #0x0 - 9e18: 3140041f cmn w0, #0x1, lsl #12 - 9e1c: aa0003e1 mov x1, x0 - 9e20: 54002849 b.ls a328 - 9e24: 3101b81f cmn w0, #0x6e - 9e28: 52800dc0 mov w0, #0x6e // #110 - 9e2c: 540004e0 b.eq 9ec8 - 9e30: 121a7820 and w0, w1, #0xffffffdf - 9e34: 31008c1f cmn w0, #0x23 - 9e38: 54003401 b.ne a4b8 - 9e3c: d2800000 mov x0, #0x0 // #0 - 9e40: 910203a1 add x1, x29, #0x80 - 9e44: d2800e28 mov x8, #0x71 // #113 - 9e48: d4000001 svc #0x0 - 9e4c: f94002a0 ldr x0, [x21] - 9e50: f94006a1 ldr x1, [x21,#8] - 9e54: f94047a2 ldr x2, [x29,#136] - 9e58: f94043a3 ldr x3, [x29,#128] - 9e5c: eb020021 subs x1, x1, x2 - 9e60: cb030000 sub x0, x0, x3 - 9e64: f9003ba0 str x0, [x29,#112] - 9e68: 540034c4 b.mi a500 - 9e6c: f9003fa1 str x1, [x29,#120] - 9e70: b7f800c0 tbnz x0, #63, 9e88 - 9e74: 9101c3b3 add x19, x29, #0x70 - 9e78: aa1303e0 mov x0, x19 - 9e7c: aa1303e1 mov x1, x19 - 9e80: 940019bc bl 10570 <__nanosleep_nocancel> - 9e84: 35ffffa0 cbnz w0, 9e78 - 9e88: 52800dc0 mov w0, #0x6e // #110 - 9e8c: 1400000f b 9ec8 - 9e90: 35000b42 cbnz w2, 9ff8 - 9e94: b90083bf str wzr, [x29,#128] - 9e98: 52800020 mov w0, #0x1 // #1 - 9e9c: 885ffe63 ldaxr w3, [x19] - 9ea0: 6b1f007f cmp w3, wzr - 9ea4: 54000061 b.ne 9eb0 - 9ea8: 88017e60 stxr w1, w0, [x19] - 9eac: 35ffff81 cbnz w1, 9e9c - 9eb0: 540003a1 b.ne 9f24 - 9eb4: b9400e61 ldr w1, [x19,#12] - 9eb8: 52800000 mov w0, #0x0 // #0 - 9ebc: b9000a76 str w22, [x19,#8] - 9ec0: 11000421 add w1, w1, #0x1 - 9ec4: b9000e61 str w1, [x19,#12] - 9ec8: a94153f3 ldp x19, x20, [sp,#16] - 9ecc: a9425bf5 ldp x21, x22, [sp,#32] - 9ed0: a94363f7 ldp x23, x24, [sp,#48] - 9ed4: a9446bf9 ldp x25, x26, [sp,#64] - 9ed8: a94573fb ldp x27, x28, [sp,#80] - 9edc: fd4033e8 ldr d8, [sp,#96] - 9ee0: a8c97bfd ldp x29, x30, [sp],#144 - 9ee4: d65f03c0 ret - 9ee8: 7104005f cmp w2, #0x100 - 9eec: 54001b01 b.ne a24c - 9ef0: b90083bf str wzr, [x29,#128] - 9ef4: 52800022 mov w2, #0x1 // #1 - 9ef8: 885ffe63 ldaxr w3, [x19] - 9efc: 6b1f007f cmp w3, wzr - 9f00: 54000061 b.ne 9f0c - 9f04: 88047e62 stxr w4, w2, [x19] - 9f08: 35ffff84 cbnz w4, 9ef8 - 9f0c: 540018e0 b.eq a228 - 9f10: b9401262 ldr w2, [x19,#16] - 9f14: b90083a3 str w3, [x29,#128] - 9f18: 12190042 and w2, w2, #0x80 - 9f1c: 94001645 bl f830 <__lll_timedlock_wait> - 9f20: 17ffffea b 9ec8 - 9f24: b9401262 ldr w2, [x19,#16] - 9f28: aa1303e0 mov x0, x19 - 9f2c: aa1503e1 mov x1, x21 - 9f30: b90083a3 str w3, [x29,#128] - 9f34: 12190042 and w2, w2, #0x80 - 9f38: 9400163e bl f830 <__lll_timedlock_wait> - 9f3c: 2a0003e2 mov w2, w0 - 9f40: 2a0203e0 mov w0, w2 - 9f44: 35fffc22 cbnz w2, 9ec8 - 9f48: 17ffffdb b 9eb4 - 9f4c: b9400800 ldr w0, [x0,#8] - 9f50: 6b0002df cmp w22, w0 - 9f54: 54fffa01 b.ne 9e94 - 9f58: 52800460 mov w0, #0x23 // #35 - 9f5c: 17ffffdb b 9ec8 - 9f60: f0000140 adrp x0, 34000 <__GI___pthread_keys+0x3d78> - 9f64: b9432c00 ldr w0, [x0,#812] - 9f68: 34fff960 cbz w0, 9e94 - 9f6c: b90083bf str wzr, [x29,#128] - 9f70: 52800022 mov w2, #0x1 // #1 - 9f74: 885ffe60 ldaxr w0, [x19] - 9f78: 6b1f001f cmp w0, wzr - 9f7c: 54000061 b.ne 9f88 - 9f80: 88017e62 stxr w1, w2, [x19] - 9f84: 35ffff81 cbnz w1, 9f74 - 9f88: 1a9f17f4 cset w20, eq - 9f8c: 35fff954 cbnz w20, 9eb4 - 9f90: b9401661 ldr w1, [x19,#20] - 9f94: 52800c80 mov w0, #0x64 // #100 - 9f98: 11001421 add w1, w1, #0x5 - 9f9c: 531f7821 lsl w1, w1, #1 - 9fa0: 7101903f cmp w1, #0x64 - 9fa4: 1a80d021 csel w1, w1, w0, le - 9fa8: 11000694 add w20, w20, #0x1 - 9fac: b90083bf str wzr, [x29,#128] - 9fb0: 51000680 sub w0, w20, #0x1 - 9fb4: 6b01001f cmp w0, w1 - 9fb8: 5400200a b.ge a3b8 - 9fbc: 885ffe60 ldaxr w0, [x19] - 9fc0: 6b1f001f cmp w0, wzr - 9fc4: 54000061 b.ne 9fd0 - 9fc8: 88037e62 stxr w3, w2, [x19] - 9fcc: 35ffff83 cbnz w3, 9fbc - 9fd0: 54fffec1 b.ne 9fa8 - 9fd4: 52800002 mov w2, #0x0 // #0 - 9fd8: b9401661 ldr w1, [x19,#20] - 9fdc: 4b010294 sub w20, w20, w1 - 9fe0: 11001e80 add w0, w20, #0x7 - 9fe4: 6b1f029f cmp w20, wzr - 9fe8: 1a94b014 csel w20, w0, w20, lt - 9fec: 0b940c34 add w20, w1, w20, asr #3 - 9ff0: b9001674 str w20, [x19,#20] - 9ff4: 17ffffd3 b 9f40 - 9ff8: 7100045f cmp w2, #0x1 - 9ffc: 540012c1 b.ne a254 - a000: b9400a60 ldr w0, [x19,#8] - a004: 6b16001f cmp w0, w22 - a008: 54001701 b.ne a2e8 - a00c: b9400660 ldr w0, [x19,#4] - a010: 3100041f cmn w0, #0x1 - a014: 54001ba0 b.eq a388 - a018: 11000401 add w1, w0, #0x1 - a01c: 52800000 mov w0, #0x0 // #0 - a020: b9000661 str w1, [x19,#4] - a024: 17ffffa9 b 9ec8 - a028: b9401261 ldr w1, [x19,#16] - a02c: 12001821 and w1, w1, #0x7f - a030: 7100483f cmp w1, #0x12 - a034: 54002200 b.eq a474 - a038: 7100443f cmp w1, #0x11 - a03c: 54ffe521 b.ne 9ce0 - a040: f9007a9f str xzr, [x20,#240] - a044: b9400661 ldr w1, [x19,#4] - a048: 3100043f cmn w1, #0x1 - a04c: 540019e0 b.eq a388 - a050: 11000421 add w1, w1, #0x1 - a054: b9000661 str w1, [x19,#4] - a058: 17ffff9c b 9ec8 - a05c: b9400a61 ldr w1, [x19,#8] - a060: 321f77e0 mov w0, #0x7ffffffe // #2147483646 - a064: 6b00003f cmp w1, w0 - a068: 54001080 b.eq a278 - a06c: 52800002 mov w2, #0x0 // #0 - a070: aa1403e0 mov x0, x20 - a074: 52800021 mov w1, #0x1 // #1 - a078: b9000661 str w1, [x19,#4] - a07c: f84e0c01 ldr x1, [x0,#224]! - a080: 927ff823 and x3, x1, #0xfffffffffffffffe - a084: f81f8078 str x24, [x3,#-8] - a088: f9001261 str x1, [x19,#32] - a08c: f9000e60 str x0, [x19,#24] - a090: f9007298 str x24, [x20,#224] - a094: f9007a9f str xzr, [x20,#240] - a098: 17ffffaa b 9f40 - a09c: b9400800 ldr w0, [x0,#8] - a0a0: b9400261 ldr w1, [x19] - a0a4: 6b16001f cmp w0, w22 - a0a8: 54001a60 b.eq a3f4 - a0ac: 12800014 mov w20, #0xffffffff // #-1 - a0b0: 9101c3b8 add x24, x29, #0x70 - a0b4: 53137c20 lsr w0, w1, #19 - a0b8: 2a0003f7 mov w23, w0 - a0bc: 1e270008 fmov s8, w0 - a0c0: 94001fa6 bl 11f58 <__pthread_current_priority> - a0c4: 6b0002ff cmp w23, w0 - a0c8: 54001fcb b.lt a4c0 - a0cc: 2a1403e0 mov w0, w20 - a0d0: 2a1703e1 mov w1, w23 - a0d4: 94001ee1 bl 11c58 <__pthread_tpp_change_priority> - a0d8: 35ffef80 cbnz w0, 9ec8 - a0dc: 910243bc add x28, x29, #0x90 - a0e0: 530d32f4 lsl w20, w23, #19 - a0e4: 32000297 orr w23, w20, #0x1 - a0e8: 2a1403e0 mov w0, w20 - a0ec: b81f0f94 str w20, [x28,#-16]! - a0f0: 885ffe61 ldaxr w1, [x19] - a0f4: 6b00003f cmp w1, w0 - a0f8: 54000061 b.ne a104 - a0fc: 88027e77 stxr w2, w23, [x19] - a100: 35ffff82 cbnz w2, a0f0 - a104: 54000040 b.eq a10c - a108: b90083a1 str w1, [x29,#128] - a10c: b94083a0 ldr w0, [x29,#128] - a110: 6b00029f cmp w20, w0 - a114: 54000780 b.eq a204 - a118: 321f029b orr w27, w20, #0x2 - a11c: 910203ba add x26, x29, #0x80 - a120: 93407f79 sxtw x25, w27 - a124: b90083b7 str w23, [x29,#128] - a128: b9400380 ldr w0, [x28] - a12c: 885ffe61 ldaxr w1, [x19] - a130: 6b00003f cmp w1, w0 - a134: 54000061 b.ne a140 - a138: 88027e7b stxr w2, w27, [x19] - a13c: 35ffff82 cbnz w2, a12c - a140: 54000040 b.eq a148 - a144: b9000381 str w1, [x28] - a148: b94083a1 ldr w1, [x29,#128] - a14c: 120d3020 and w0, w1, #0xfff80000 - a150: 6b00029f cmp w20, w0 - a154: 540011e1 b.ne a390 - a158: 6b01029f cmp w20, w1 - a15c: 540003c0 b.eq a1d4 - a160: f94006a1 ldr x1, [x21,#8] - a164: d2993fe0 mov x0, #0xc9ff // #51711 - a168: f2a77340 movk x0, #0x3b9a, lsl #16 - a16c: eb00003f cmp x1, x0 - a170: 54001148 b.hi a398 - a174: d2800001 mov x1, #0x0 // #0 - a178: aa1803e0 mov x0, x24 - a17c: 97ffeb91 bl 4fc0 <__gettimeofday@plt> - a180: f9403fa7 ldr x7, [x29,#120] - a184: f94002a6 ldr x6, [x21] - a188: f94006a0 ldr x0, [x21,#8] - a18c: cb0714e5 sub x5, x7, x7, lsl #5 - a190: f9403ba1 ldr x1, [x29,#112] - a194: d37ef4a5 lsl x5, x5, #2 - a198: cb0700a4 sub x4, x5, x7 - a19c: cb0100c6 sub x6, x6, x1 - a1a0: f90043a6 str x6, [x29,#128] - a1a4: ab040c04 adds x4, x0, x4, lsl #3 - a1a8: 54000344 b.mi a210 - a1ac: f90047a4 str x4, [x29,#136] - a1b0: b7f81006 tbnz x6, #63, a3b0 - a1b4: b9401261 ldr w1, [x19,#16] - a1b8: aa1303e0 mov x0, x19 - a1bc: aa1903e2 mov x2, x25 - a1c0: aa1a03e3 mov x3, x26 - a1c4: 2a2103e1 mvn w1, w1 - a1c8: d2800c48 mov x8, #0x62 // #98 - a1cc: 92790021 and x1, x1, #0x80 - a1d0: d4000001 svc #0x0 - a1d4: b90083b4 str w20, [x29,#128] - a1d8: b9400380 ldr w0, [x28] - a1dc: 885ffe61 ldaxr w1, [x19] - a1e0: 6b00003f cmp w1, w0 - a1e4: 54000061 b.ne a1f0 - a1e8: 88027e7b stxr w2, w27, [x19] - a1ec: 35ffff82 cbnz w2, a1dc - a1f0: 54000040 b.eq a1f8 - a1f4: b9000381 str w1, [x28] - a1f8: b94083a0 ldr w0, [x29,#128] - a1fc: 6b00029f cmp w20, w0 - a200: 54fff921 b.ne a124 - a204: 52800020 mov w0, #0x1 // #1 - a208: b9000660 str w0, [x19,#4] - a20c: 17ffff2a b 9eb4 - a210: d2994000 mov x0, #0xca00 // #51712 - a214: d10004c6 sub x6, x6, #0x1 - a218: f2a77340 movk x0, #0x3b9a, lsl #16 - a21c: f90043a6 str x6, [x29,#128] - a220: 8b000084 add x4, x4, x0 - a224: 17ffffe2 b a1ac - a228: 52800000 mov w0, #0x0 // #0 - a22c: a94153f3 ldp x19, x20, [sp,#16] - a230: a9425bf5 ldp x21, x22, [sp,#32] - a234: a94363f7 ldp x23, x24, [sp,#48] - a238: a9446bf9 ldp x25, x26, [sp,#64] - a23c: a94573fb ldp x27, x28, [sp,#80] - a240: fd4033e8 ldr d8, [sp,#96] - a244: a8c97bfd ldp x29, x30, [sp],#144 - a248: d65f03c0 ret - a24c: 7104045f cmp w2, #0x101 - a250: 54ffed80 b.eq a000 - a254: 528002c0 mov w0, #0x16 // #22 - a258: a94153f3 ldp x19, x20, [sp,#16] - a25c: a9425bf5 ldp x21, x22, [sp,#32] - a260: a94363f7 ldp x23, x24, [sp,#48] - a264: a9446bf9 ldp x25, x26, [sp,#64] - a268: a94573fb ldp x27, x28, [sp,#80] - a26c: fd4033e8 ldr d8, [sp,#96] - a270: a8c97bfd ldp x29, x30, [sp],#144 - a274: d65f03c0 ret - a278: b900067f str wzr, [x19,#4] - a27c: 52800001 mov w1, #0x0 // #0 - a280: 885f7e60 ldxr w0, [x19] - a284: 8802fe61 stlxr w2, w1, [x19] - a288: 35ffffc2 cbnz w2, a280 - a28c: 7100041f cmp w0, #0x1 - a290: 54000e4c b.gt a458 - a294: f9007a9f str xzr, [x20,#240] - a298: 52801060 mov w0, #0x83 // #131 - a29c: 17ffff0b b 9ec8 - a2a0: 34fffb24 cbz w4, a204 - a2a4: b9400a61 ldr w1, [x19,#8] - a2a8: 321f77e0 mov w0, #0x7ffffffe // #2147483646 - a2ac: 6b00003f cmp w1, w0 - a2b0: 54001140 b.eq a4d8 - a2b4: aa1403e0 mov x0, x20 - a2b8: 52800021 mov w1, #0x1 // #1 - a2bc: b9000661 str w1, [x19,#4] - a2c0: 91008262 add x2, x19, #0x20 - a2c4: b2400043 orr x3, x2, #0x1 - a2c8: f84e0c01 ldr x1, [x0,#224]! - a2cc: 927ff824 and x4, x1, #0xfffffffffffffffe - a2d0: f81f8082 str x2, [x4,#-8] - a2d4: f9001261 str x1, [x19,#32] - a2d8: f9000e60 str x0, [x19,#24] - a2dc: f9007283 str x3, [x20,#224] - a2e0: f9007a9f str xzr, [x20,#240] - a2e4: 17fffef4 b 9eb4 - a2e8: b90083bf str wzr, [x29,#128] - a2ec: 52800020 mov w0, #0x1 // #1 - a2f0: 885ffe63 ldaxr w3, [x19] - a2f4: 6b1f007f cmp w3, wzr - a2f8: 54000061 b.ne a304 - a2fc: 88017e60 stxr w1, w0, [x19] - a300: 35ffff81 cbnz w1, a2f0 - a304: 54fff800 b.eq a204 - a308: b9401262 ldr w2, [x19,#16] - a30c: aa1303e0 mov x0, x19 - a310: aa1503e1 mov x1, x21 - a314: b90083a3 str w3, [x29,#128] - a318: 12190042 and w2, w2, #0x80 - a31c: 94001545 bl f830 <__lll_timedlock_wait> - a320: 35ffdd40 cbnz w0, 9ec8 - a324: 17ffffb8 b a204 - a328: b9400260 ldr w0, [x19] - a32c: 36f7fba0 tbz w0, #30, a2a0 - a330: 910203bc add x28, x29, #0x80 - a334: b90083a0 str w0, [x29,#128] - a338: 12017800 and w0, w0, #0xbfffffff - a33c: b9400381 ldr w1, [x28] - a340: 885ffe62 ldaxr w2, [x19] - a344: 6b01005f cmp w2, w1 - a348: 54000061 b.ne a354 - a34c: 88037e60 stxr w3, w0, [x19] - a350: 35ffff83 cbnz w3, a340 - a354: 54000620 b.eq a418 - a358: b9000382 str w2, [x28] - a35c: b9400260 ldr w0, [x19] - a360: 17fffff5 b a334 - a364: 12000463 and w3, w3, #0x3 - a368: 7100087f cmp w3, #0x2 - a36c: 54000840 b.eq a474 - a370: 7100047f cmp w3, #0x1 - a374: 54ffd261 b.ne 9dc0 - a378: f9007a9f str xzr, [x20,#240] - a37c: b9400660 ldr w0, [x19,#4] - a380: 3100041f cmn w0, #0x1 - a384: 54ffe4a1 b.ne a018 - a388: 52800160 mov w0, #0xb // #11 - a38c: 17fffecf b 9ec8 - a390: 1e260114 fmov w20, s8 - a394: 17ffff48 b a0b4 - a398: 528002d3 mov w19, #0x16 // #22 - a39c: 1e260100 fmov w0, s8 - a3a0: 12800001 mov w1, #0xffffffff // #-1 - a3a4: 94001e2d bl 11c58 <__pthread_tpp_change_priority> - a3a8: 2a1303e0 mov w0, w19 - a3ac: 17fffec7 b 9ec8 - a3b0: 52800dd3 mov w19, #0x6e // #110 - a3b4: 17fffffa b a39c - a3b8: 52800020 mov w0, #0x1 // #1 - a3bc: 885ffe63 ldaxr w3, [x19] - a3c0: 6b1f007f cmp w3, wzr - a3c4: 54000061 b.ne a3d0 - a3c8: 88017e60 stxr w1, w0, [x19] - a3cc: 35ffff81 cbnz w1, a3bc - a3d0: 54ffe020 b.eq 9fd4 - a3d4: b9401262 ldr w2, [x19,#16] - a3d8: aa1303e0 mov x0, x19 - a3dc: aa1503e1 mov x1, x21 - a3e0: b90083a3 str w3, [x29,#128] - a3e4: 12190042 and w2, w2, #0x80 - a3e8: 94001512 bl f830 <__lll_timedlock_wait> - a3ec: 2a0003e2 mov w2, w0 - a3f0: 17fffefa b 9fd8 - a3f4: 12000463 and w3, w3, #0x3 - a3f8: 52800460 mov w0, #0x23 // #35 - a3fc: 7100087f cmp w3, #0x2 - a400: 54ffd640 b.eq 9ec8 - a404: 7100047f cmp w3, #0x1 - a408: 54ffe521 b.ne a0ac - a40c: 17ffff00 b a00c - a410: 2a0203e0 mov w0, w2 - a414: 17fffead b 9ec8 - a418: aa1403e1 mov x1, x20 - a41c: 52800020 mov w0, #0x1 // #1 - a420: b9000660 str w0, [x19,#4] - a424: 12b00000 mov w0, #0x7fffffff // #2147483647 - a428: b9000a60 str w0, [x19,#8] - a42c: 91008263 add x3, x19, #0x20 - a430: b2400064 orr x4, x3, #0x1 - a434: 52801040 mov w0, #0x82 // #130 - a438: f84e0c22 ldr x2, [x1,#224]! - a43c: 927ff845 and x5, x2, #0xfffffffffffffffe - a440: f81f80a3 str x3, [x5,#-8] - a444: f9001262 str x2, [x19,#32] - a448: f9000e61 str x1, [x19,#24] - a44c: f9007284 str x4, [x20,#224] - a450: f9007a9f str xzr, [x20,#240] - a454: 17fffe9d b 9ec8 - a458: d2800021 mov x1, #0x1 // #1 - a45c: aa1303e0 mov x0, x19 - a460: aa0103e2 mov x2, x1 - a464: d2800003 mov x3, #0x0 // #0 - a468: d2800c48 mov x8, #0x62 // #98 - a46c: d4000001 svc #0x0 - a470: 17ffff89 b a294 - a474: f9007a9f str xzr, [x20,#240] - a478: 52800460 mov w0, #0x23 // #35 - a47c: 17fffe93 b 9ec8 - a480: aa1403e1 mov x1, x20 - a484: 52800020 mov w0, #0x1 // #1 - a488: b9000660 str w0, [x19,#4] - a48c: 12b00000 mov w0, #0x7fffffff // #2147483647 - a490: b9000a60 str w0, [x19,#8] - a494: 52801040 mov w0, #0x82 // #130 - a498: f84e0c22 ldr x2, [x1,#224]! - a49c: 927ff843 and x3, x2, #0xfffffffffffffffe - a4a0: f81f8078 str x24, [x3,#-8] - a4a4: f9001262 str x2, [x19,#32] - a4a8: f9000e61 str x1, [x19,#24] - a4ac: f9007298 str x24, [x20,#224] - a4b0: f9007a9f str xzr, [x20,#240] - a4b4: 17fffe85 b 9ec8 - a4b8: 4b0103e0 neg w0, w1 - a4bc: 17fffe83 b 9ec8 - a4c0: 3100069f cmn w20, #0x1 - a4c4: 528002c0 mov w0, #0x16 // #22 - a4c8: 54ffd000 b.eq 9ec8 - a4cc: 1e270288 fmov s8, w20 - a4d0: 2a0003f3 mov w19, w0 - a4d4: 17ffffb2 b a39c - a4d8: d2800002 mov x2, #0x0 // #0 - a4dc: b900067f str wzr, [x19,#4] - a4e0: aa1303e0 mov x0, x19 - a4e4: d28000e1 mov x1, #0x7 // #7 - a4e8: aa0203e3 mov x3, x2 - a4ec: d2800c48 mov x8, #0x62 // #98 - a4f0: d4000001 svc #0x0 - a4f4: 52801060 mov w0, #0x83 // #131 - a4f8: f9007a82 str x2, [x20,#240] - a4fc: 17fffe73 b 9ec8 - a500: d2994002 mov x2, #0xca00 // #51712 - a504: d1000400 sub x0, x0, #0x1 - a508: f2a77342 movk x2, #0x3b9a, lsl #16 - a50c: f9003ba0 str x0, [x29,#112] - a510: 8b020021 add x1, x1, x2 - a514: 17fffe56 b 9e6c - -000000000000a518 <__pthread_mutex_unlock_full>: - a518: a9be7bfd stp x29, x30, [sp,#-32]! - a51c: 910003fd mov x29, sp - a520: b9401005 ldr w5, [x0,#16] - a524: 120018a2 and w2, w5, #0x7f - a528: 51004042 sub w2, w2, #0x10 - a52c: 7100cc5f cmp w2, #0x33 - a530: 540000a9 b.ls a544 <__pthread_mutex_unlock_full+0x2c> - a534: 528002c4 mov w4, #0x16 // #22 - a538: 2a0403e0 mov w0, w4 - a53c: a8c27bfd ldp x29, x30, [sp],#32 - a540: d65f03c0 ret - a544: 90000043 adrp x3, 12000 <__pthread_current_priority+0xa8> - a548: 9130a063 add x3, x3, #0xc28 - a54c: 78625862 ldrh w2, [x3,w2,uxtw #1] - a550: 10000063 adr x3, a55c <__pthread_mutex_unlock_full+0x44> - a554: 8b22a862 add x2, x3, w2, sxth #2 - a558: d61f0040 br x2 - a55c: d53bd045 mrs x5, tpidr_el0 - a560: b9400002 ldr w2, [x0] - a564: d11bc0a5 sub x5, x5, #0x6f0 - a568: 12007444 and w4, w2, #0x3fffffff - a56c: b940d0a3 ldr w3, [x5,#208] - a570: 6b03009f cmp w4, w3 - a574: 54001761 b.ne a860 <__pthread_mutex_unlock_full+0x348> - a578: 34001742 cbz w2, a860 <__pthread_mutex_unlock_full+0x348> - a57c: b9400803 ldr w3, [x0,#8] - a580: 12b00002 mov w2, #0x7fffffff // #2147483647 - a584: 6b02007f cmp w3, w2 - a588: 321f77e2 mov w2, #0x7ffffffe // #2147483646 - a58c: 1a8213e2 csel w2, wzr, w2, ne - a590: 14000095 b a7e4 <__pthread_mutex_unlock_full+0x2cc> - a594: d53bd042 mrs x2, tpidr_el0 - a598: b9400803 ldr w3, [x0,#8] - a59c: d11bc042 sub x2, x2, #0x6f0 - a5a0: 52800024 mov w4, #0x1 // #1 - a5a4: b940d042 ldr w2, [x2,#208] - a5a8: 6b02007f cmp w3, w2 - a5ac: 54fffc61 b.ne a538 <__pthread_mutex_unlock_full+0x20> - a5b0: b9400002 ldr w2, [x0] - a5b4: 12004843 and w3, w2, #0x7ffff - a5b8: 34fffc03 cbz w3, a538 <__pthread_mutex_unlock_full+0x20> - a5bc: b900081f str wzr, [x0,#8] - a5c0: 35000581 cbnz w1, a670 <__pthread_mutex_unlock_full+0x158> - a5c4: 2a0203e1 mov w1, w2 - a5c8: b9001fa1 str w1, [x29,#28] - a5cc: 120d3024 and w4, w1, #0xfff80000 - a5d0: 2a0103e2 mov w2, w1 - a5d4: 885f7c03 ldxr w3, [x0] - a5d8: 6b02007f cmp w3, w2 - a5dc: 54000061 b.ne a5e8 <__pthread_mutex_unlock_full+0xd0> - a5e0: 8805fc04 stlxr w5, w4, [x0] - a5e4: 35ffff85 cbnz w5, a5d4 <__pthread_mutex_unlock_full+0xbc> - a5e8: 540004c1 b.ne a680 <__pthread_mutex_unlock_full+0x168> - a5ec: 12004821 and w1, w1, #0x7ffff - a5f0: 7100043f cmp w1, #0x1 - a5f4: 54000149 b.ls a61c <__pthread_mutex_unlock_full+0x104> - a5f8: b9401001 ldr w1, [x0,#16] - a5fc: d2800022 mov x2, #0x1 // #1 - a600: d2800003 mov x3, #0x0 // #0 - a604: d2800c48 mov x8, #0x62 // #98 - a608: 12190025 and w5, w1, #0x80 - a60c: 52801021 mov w1, #0x81 // #129 - a610: 4a0100a1 eor w1, w5, w1 - a614: 93407c21 sxtw x1, w1 - a618: d4000001 svc #0x0 - a61c: 13137c80 asr w0, w4, #19 - a620: 12800001 mov w1, #0xffffffff // #-1 - a624: 94001d8d bl 11c58 <__pthread_tpp_change_priority> - a628: 2a0003e4 mov w4, w0 - a62c: 2a0403e0 mov w0, w4 - a630: a8c27bfd ldp x29, x30, [sp],#32 - a634: d65f03c0 ret - a638: d53bd042 mrs x2, tpidr_el0 - a63c: b9400803 ldr w3, [x0,#8] - a640: d11bc042 sub x2, x2, #0x6f0 - a644: 52800024 mov w4, #0x1 // #1 - a648: b940d042 ldr w2, [x2,#208] - a64c: 6b02007f cmp w3, w2 - a650: 54fff741 b.ne a538 <__pthread_mutex_unlock_full+0x20> - a654: b9400402 ldr w2, [x0,#4] - a658: 51000442 sub w2, w2, #0x1 - a65c: b9000402 str w2, [x0,#4] - a660: 35000f82 cbnz w2, a850 <__pthread_mutex_unlock_full+0x338> - a664: b900081f str wzr, [x0,#8] - a668: b9400002 ldr w2, [x0] - a66c: 34fffac1 cbz w1, a5c4 <__pthread_mutex_unlock_full+0xac> - a670: b9400c01 ldr w1, [x0,#12] - a674: 51000421 sub w1, w1, #0x1 - a678: b9000c01 str w1, [x0,#12] - a67c: 17ffffd2 b a5c4 <__pthread_mutex_unlock_full+0xac> - a680: b9400001 ldr w1, [x0] - a684: 17ffffd1 b a5c8 <__pthread_mutex_unlock_full+0xb0> - a688: d53bd043 mrs x3, tpidr_el0 - a68c: b9400004 ldr w4, [x0] - a690: d11bc063 sub x3, x3, #0x6f0 - a694: 12007482 and w2, w4, #0x3fffffff - a698: b940d066 ldr w6, [x3,#208] - a69c: 6b06005f cmp w2, w6 - a6a0: b9400802 ldr w2, [x0,#8] - a6a4: 54001060 b.eq a8b0 <__pthread_mutex_unlock_full+0x398> - a6a8: 6b0200df cmp w6, w2 - a6ac: 52800024 mov w4, #0x1 // #1 - a6b0: 54fff441 b.ne a538 <__pthread_mutex_unlock_full+0x20> - a6b4: b9400402 ldr w2, [x0,#4] - a6b8: 51000442 sub w2, w2, #0x1 - a6bc: b9000402 str w2, [x0,#4] - a6c0: 340010a2 cbz w2, a8d4 <__pthread_mutex_unlock_full+0x3bc> - a6c4: 14000063 b a850 <__pthread_mutex_unlock_full+0x338> - a6c8: d53bd043 mrs x3, tpidr_el0 - a6cc: b9400805 ldr w5, [x0,#8] - a6d0: d11bc063 sub x3, x3, #0x6f0 - a6d4: 52800024 mov w4, #0x1 // #1 - a6d8: b940d062 ldr w2, [x3,#208] - a6dc: 6b0200bf cmp w5, w2 - a6e0: 54fff2c1 b.ne a538 <__pthread_mutex_unlock_full+0x20> - a6e4: b9400402 ldr w2, [x0,#4] - a6e8: 51000442 sub w2, w2, #0x1 - a6ec: b9000402 str w2, [x0,#4] - a6f0: 35000b02 cbnz w2, a850 <__pthread_mutex_unlock_full+0x338> - a6f4: b9400004 ldr w4, [x0] - a6f8: b9000802 str w2, [x0,#8] - a6fc: 34000081 cbz w1, a70c <__pthread_mutex_unlock_full+0x1f4> - a700: b9400c01 ldr w1, [x0,#12] - a704: 51000421 sub w1, w1, #0x1 - a708: b9000c01 str w1, [x0,#12] - a70c: 37f80164 tbnz w4, #31, a738 <__pthread_mutex_unlock_full+0x220> - a710: b940d061 ldr w1, [x3,#208] - a714: 52800004 mov w4, #0x0 // #0 - a718: b9001fa1 str w1, [x29,#28] - a71c: 885f7c02 ldxr w2, [x0] - a720: 6b01005f cmp w2, w1 - a724: 54000061 b.ne a730 <__pthread_mutex_unlock_full+0x218> - a728: 8805fc04 stlxr w5, w4, [x0] - a72c: 35ffff85 cbnz w5, a71c <__pthread_mutex_unlock_full+0x204> - a730: 540000e0 b.eq a74c <__pthread_mutex_unlock_full+0x234> - a734: b9001fa2 str w2, [x29,#28] - a738: b9401001 ldr w1, [x0,#16] - a73c: 36200b01 tbz w1, #4, a89c <__pthread_mutex_unlock_full+0x384> - a740: d28000e1 mov x1, #0x7 // #7 - a744: d2800c48 mov x8, #0x62 // #98 - a748: d4000001 svc #0x0 - a74c: f900787f str xzr, [x3,#240] - a750: 52800004 mov w4, #0x0 // #0 - a754: 2a0403e0 mov w0, w4 - a758: a8c27bfd ldp x29, x30, [sp],#32 - a75c: d65f03c0 ret - a760: d53bd043 mrs x3, tpidr_el0 - a764: b9400004 ldr w4, [x0] - a768: d11bc063 sub x3, x3, #0x6f0 - a76c: 12007486 and w6, w4, #0x3fffffff - a770: b940d062 ldr w2, [x3,#208] - a774: 6b0200df cmp w6, w2 - a778: 54000741 b.ne a860 <__pthread_mutex_unlock_full+0x348> - a77c: 6b1f009f cmp w4, wzr - a780: 1a9f17e2 cset w2, eq - a784: 350006e2 cbnz w2, a860 <__pthread_mutex_unlock_full+0x348> - a788: 3627fb85 tbz w5, #4, a6f8 <__pthread_mutex_unlock_full+0x1e0> - a78c: b9400804 ldr w4, [x0,#8] - a790: 12b00002 mov w2, #0x7fffffff // #2147483647 - a794: 6b02009f cmp w4, w2 - a798: 321f77e2 mov w2, #0x7ffffffe // #2147483646 - a79c: 1a8213e2 csel w2, wzr, w2, ne - a7a0: 1400004d b a8d4 <__pthread_mutex_unlock_full+0x3bc> - a7a4: d53bd045 mrs x5, tpidr_el0 - a7a8: b9400002 ldr w2, [x0] - a7ac: d11bc0a5 sub x5, x5, #0x6f0 - a7b0: 12007442 and w2, w2, #0x3fffffff - a7b4: b940d0a3 ldr w3, [x5,#208] - a7b8: 6b03005f cmp w2, w3 - a7bc: b9400802 ldr w2, [x0,#8] - a7c0: 54000580 b.eq a870 <__pthread_mutex_unlock_full+0x358> - a7c4: 6b02007f cmp w3, w2 - a7c8: 52800024 mov w4, #0x1 // #1 - a7cc: 54ffeb61 b.ne a538 <__pthread_mutex_unlock_full+0x20> - a7d0: b9400403 ldr w3, [x0,#4] - a7d4: 52800002 mov w2, #0x0 // #0 - a7d8: 51000463 sub w3, w3, #0x1 - a7dc: b9000403 str w3, [x0,#4] - a7e0: 35000383 cbnz w3, a850 <__pthread_mutex_unlock_full+0x338> - a7e4: 91008003 add x3, x0, #0x20 - a7e8: f90078a3 str x3, [x5,#240] - a7ec: f9401004 ldr x4, [x0,#32] - a7f0: f9400c06 ldr x6, [x0,#24] - a7f4: 927ff883 and x3, x4, #0xfffffffffffffffe - a7f8: f81f8066 str x6, [x3,#-8] - a7fc: f9400c03 ldr x3, [x0,#24] - a800: 927ff863 and x3, x3, #0xfffffffffffffffe - a804: f9000064 str x4, [x3] - a808: f9000c1f str xzr, [x0,#24] - a80c: f900101f str xzr, [x0,#32] - a810: b9000802 str w2, [x0,#8] - a814: 34000081 cbz w1, a824 <__pthread_mutex_unlock_full+0x30c> - a818: b9400c01 ldr w1, [x0,#12] - a81c: 51000421 sub w1, w1, #0x1 - a820: b9000c01 str w1, [x0,#12] - a824: 52800002 mov w2, #0x0 // #0 - a828: 885f7c01 ldxr w1, [x0] - a82c: 8803fc02 stlxr w3, w2, [x0] - a830: 35ffffc3 cbnz w3, a828 <__pthread_mutex_unlock_full+0x310> - a834: 36f800c1 tbz w1, #31, a84c <__pthread_mutex_unlock_full+0x334> - a838: d2800021 mov x1, #0x1 // #1 - a83c: d2800003 mov x3, #0x0 // #0 - a840: aa0103e2 mov x2, x1 - a844: d2800c48 mov x8, #0x62 // #98 - a848: d4000001 svc #0x0 - a84c: f90078bf str xzr, [x5,#240] - a850: 52800004 mov w4, #0x0 // #0 - a854: 2a0403e0 mov w0, w4 - a858: a8c27bfd ldp x29, x30, [sp],#32 - a85c: d65f03c0 ret - a860: 52800024 mov w4, #0x1 // #1 - a864: 2a0403e0 mov w0, w4 - a868: a8c27bfd ldp x29, x30, [sp],#32 - a86c: d65f03c0 ret - a870: 12b00004 mov w4, #0x7fffffff // #2147483647 - a874: 6b04005f cmp w2, w4 - a878: 54fffa61 b.ne a7c4 <__pthread_mutex_unlock_full+0x2ac> - a87c: b9400402 ldr w2, [x0,#4] - a880: 51000442 sub w2, w2, #0x1 - a884: b9000402 str w2, [x0,#4] - a888: 34000422 cbz w2, a90c <__pthread_mutex_unlock_full+0x3f4> - a88c: 52801064 mov w4, #0x83 // #131 - a890: 2a0403e0 mov w0, w4 - a894: a8c27bfd ldp x29, x30, [sp],#32 - a898: d65f03c0 ret - a89c: 12190022 and w2, w1, #0x80 - a8a0: 528010e1 mov w1, #0x87 // #135 - a8a4: 4a010041 eor w1, w2, w1 - a8a8: 93407c21 sxtw x1, w1 - a8ac: 17ffffa6 b a744 <__pthread_mutex_unlock_full+0x22c> - a8b0: 12b00007 mov w7, #0x7fffffff // #2147483647 - a8b4: 6b07005f cmp w2, w7 - a8b8: 54ffef81 b.ne a6a8 <__pthread_mutex_unlock_full+0x190> - a8bc: b9400402 ldr w2, [x0,#4] - a8c0: 51000442 sub w2, w2, #0x1 - a8c4: b9000402 str w2, [x0,#4] - a8c8: 35fffe22 cbnz w2, a88c <__pthread_mutex_unlock_full+0x374> - a8cc: 321f77e2 mov w2, #0x7ffffffe // #2147483646 - a8d0: 3627f145 tbz w5, #4, a6f8 <__pthread_mutex_unlock_full+0x1e0> - a8d4: 91008004 add x4, x0, #0x20 - a8d8: b2400084 orr x4, x4, #0x1 - a8dc: f9007864 str x4, [x3,#240] - a8e0: f9401005 ldr x5, [x0,#32] - a8e4: f9400c06 ldr x6, [x0,#24] - a8e8: 927ff8a4 and x4, x5, #0xfffffffffffffffe - a8ec: f81f8086 str x6, [x4,#-8] - a8f0: f9400c04 ldr x4, [x0,#24] - a8f4: 927ff884 and x4, x4, #0xfffffffffffffffe - a8f8: f9000085 str x5, [x4] - a8fc: f9000c1f str xzr, [x0,#24] - a900: b9400004 ldr w4, [x0] - a904: f900101f str xzr, [x0,#32] - a908: 17ffff7c b a6f8 <__pthread_mutex_unlock_full+0x1e0> - a90c: 321f77e2 mov w2, #0x7ffffffe // #2147483646 - a910: 17ffffb5 b a7e4 <__pthread_mutex_unlock_full+0x2cc> - -000000000000a914 <__pthread_mutex_unlock_usercnt>: - a914: b9401003 ldr w3, [x0,#16] - a918: 52802fe4 mov w4, #0x17f // #383 - a91c: aa0003e2 mov x2, x0 - a920: 2a0103e6 mov w6, w1 - a924: 721e1065 ands w5, w3, #0x7c - a928: 0a040064 and w4, w3, w4 - a92c: 54000201 b.ne a96c <__pthread_mutex_unlock_usercnt+0x58> - a930: 35000204 cbnz w4, a970 <__pthread_mutex_unlock_usercnt+0x5c> - a934: b900085f str wzr, [x2,#8] - a938: 35000126 cbnz w6, a95c <__pthread_mutex_unlock_usercnt+0x48> - a93c: 52800001 mov w1, #0x0 // #0 - a940: 885f7c40 ldxr w0, [x2] - a944: 8803fc41 stlxr w3, w1, [x2] - a948: 35ffffc3 cbnz w3, a940 <__pthread_mutex_unlock_usercnt+0x2c> - a94c: 7100041f cmp w0, #0x1 - a950: 5400032c b.gt a9b4 <__pthread_mutex_unlock_usercnt+0xa0> - a954: 2a0503e0 mov w0, w5 - a958: d65f03c0 ret - a95c: b9400c40 ldr w0, [x2,#12] - a960: 51000400 sub w0, w0, #0x1 - a964: b9000c40 str w0, [x2,#12] - a968: 17fffff5 b a93c <__pthread_mutex_unlock_usercnt+0x28> - a96c: 17fffeeb b a518 <__pthread_mutex_unlock_full> - a970: 7104009f cmp w4, #0x100 - a974: 54000361 b.ne a9e0 <__pthread_mutex_unlock_usercnt+0xcc> - a978: 885f7c41 ldxr w1, [x2] - a97c: 8803fc45 stlxr w3, w5, [x2] - a980: 35ffffc3 cbnz w3, a978 <__pthread_mutex_unlock_usercnt+0x64> - a984: 7100043f cmp w1, #0x1 - a988: 54fffe6d b.le a954 <__pthread_mutex_unlock_usercnt+0x40> - a98c: b9401041 ldr w1, [x2,#16] - a990: d2800003 mov x3, #0x0 // #0 - a994: d2800022 mov x2, #0x1 // #1 - a998: d2800c48 mov x8, #0x62 // #98 - a99c: 12190024 and w4, w1, #0x80 - a9a0: 52801021 mov w1, #0x81 // #129 - a9a4: 4a010081 eor w1, w4, w1 - a9a8: 93407c21 sxtw x1, w1 - a9ac: d4000001 svc #0x0 - a9b0: 17ffffe9 b a954 <__pthread_mutex_unlock_usercnt+0x40> - a9b4: b9401041 ldr w1, [x2,#16] - a9b8: aa0203e0 mov x0, x2 - a9bc: d2800003 mov x3, #0x0 // #0 - a9c0: d2800022 mov x2, #0x1 // #1 - a9c4: 12190024 and w4, w1, #0x80 - a9c8: 52801021 mov w1, #0x81 // #129 - a9cc: 4a010081 eor w1, w4, w1 - a9d0: d2800c48 mov x8, #0x62 // #98 - a9d4: 93407c21 sxtw x1, w1 - a9d8: d4000001 svc #0x0 - a9dc: 17ffffde b a954 <__pthread_mutex_unlock_usercnt+0x40> - a9e0: 12001863 and w3, w3, #0x7f - a9e4: 7100047f cmp w3, #0x1 - a9e8: 540001c1 b.ne aa20 <__pthread_mutex_unlock_usercnt+0x10c> - a9ec: b9400801 ldr w1, [x0,#8] - a9f0: d53bd040 mrs x0, tpidr_el0 - a9f4: d11bc000 sub x0, x0, #0x6f0 - a9f8: b940d000 ldr w0, [x0,#208] - a9fc: 6b00003f cmp w1, w0 - aa00: 54000060 b.eq aa0c <__pthread_mutex_unlock_usercnt+0xf8> - aa04: 2a0303e5 mov w5, w3 - aa08: 17ffffd3 b a954 <__pthread_mutex_unlock_usercnt+0x40> - aa0c: b9400440 ldr w0, [x2,#4] - aa10: 51000400 sub w0, w0, #0x1 - aa14: b9000440 str w0, [x2,#4] - aa18: 34fff8e0 cbz w0, a934 <__pthread_mutex_unlock_usercnt+0x20> - aa1c: 17ffffce b a954 <__pthread_mutex_unlock_usercnt+0x40> - aa20: 71000c7f cmp w3, #0x3 - aa24: 54fff880 b.eq a934 <__pthread_mutex_unlock_usercnt+0x20> - aa28: b9400801 ldr w1, [x0,#8] - aa2c: d53bd040 mrs x0, tpidr_el0 - aa30: d11bc000 sub x0, x0, #0x6f0 - aa34: b940d000 ldr w0, [x0,#208] - aa38: 6b00003f cmp w1, w0 - aa3c: 54000060 b.eq aa48 <__pthread_mutex_unlock_usercnt+0x134> - aa40: 52800025 mov w5, #0x1 // #1 - aa44: 17ffffc4 b a954 <__pthread_mutex_unlock_usercnt+0x40> - aa48: b9400040 ldr w0, [x2] - aa4c: 35fff740 cbnz w0, a934 <__pthread_mutex_unlock_usercnt+0x20> - aa50: 52800025 mov w5, #0x1 // #1 - aa54: 17ffffc0 b a954 <__pthread_mutex_unlock_usercnt+0x40> - -000000000000aa58 <__pthread_mutex_unlock>: - aa58: b9401001 ldr w1, [x0,#16] - aa5c: 52802fe3 mov w3, #0x17f // #383 - aa60: aa0003e2 mov x2, x0 - aa64: 721e1024 ands w4, w1, #0x7c - aa68: 0a030023 and w3, w1, w3 - aa6c: 540001c1 b.ne aaa4 <__pthread_mutex_unlock+0x4c> - aa70: 350001e3 cbnz w3, aaac <__pthread_mutex_unlock+0x54> - aa74: b9400c41 ldr w1, [x2,#12] - aa78: b900085f str wzr, [x2,#8] - aa7c: 51000421 sub w1, w1, #0x1 - aa80: b9000c41 str w1, [x2,#12] - aa84: 52800001 mov w1, #0x0 // #0 - aa88: 885f7c40 ldxr w0, [x2] - aa8c: 8803fc41 stlxr w3, w1, [x2] - aa90: 35ffffc3 cbnz w3, aa88 <__pthread_mutex_unlock+0x30> - aa94: 7100041f cmp w0, #0x1 - aa98: 540002cc b.gt aaf0 <__pthread_mutex_unlock+0x98> - aa9c: 2a0403e0 mov w0, w4 - aaa0: d65f03c0 ret - aaa4: 52800021 mov w1, #0x1 // #1 - aaa8: 17fffe9c b a518 <__pthread_mutex_unlock_full> - aaac: 7104007f cmp w3, #0x100 - aab0: 54000361 b.ne ab1c <__pthread_mutex_unlock+0xc4> - aab4: 885f7c41 ldxr w1, [x2] - aab8: 8803fc44 stlxr w3, w4, [x2] - aabc: 35ffffc3 cbnz w3, aab4 <__pthread_mutex_unlock+0x5c> - aac0: 7100043f cmp w1, #0x1 - aac4: 54fffecd b.le aa9c <__pthread_mutex_unlock+0x44> - aac8: b9401041 ldr w1, [x2,#16] - aacc: d2800003 mov x3, #0x0 // #0 - aad0: d2800022 mov x2, #0x1 // #1 - aad4: d2800c48 mov x8, #0x62 // #98 - aad8: 12190025 and w5, w1, #0x80 - aadc: 52801021 mov w1, #0x81 // #129 - aae0: 4a0100a1 eor w1, w5, w1 - aae4: 93407c21 sxtw x1, w1 - aae8: d4000001 svc #0x0 - aaec: 17ffffec b aa9c <__pthread_mutex_unlock+0x44> - aaf0: b9401041 ldr w1, [x2,#16] - aaf4: aa0203e0 mov x0, x2 - aaf8: d2800003 mov x3, #0x0 // #0 - aafc: d2800022 mov x2, #0x1 // #1 - ab00: 12190025 and w5, w1, #0x80 - ab04: 52801021 mov w1, #0x81 // #129 - ab08: 4a0100a1 eor w1, w5, w1 - ab0c: d2800c48 mov x8, #0x62 // #98 - ab10: 93407c21 sxtw x1, w1 - ab14: d4000001 svc #0x0 - ab18: 17ffffe1 b aa9c <__pthread_mutex_unlock+0x44> - ab1c: 12001821 and w1, w1, #0x7f - ab20: 7100043f cmp w1, #0x1 - ab24: 540001c1 b.ne ab5c <__pthread_mutex_unlock+0x104> - ab28: b9400803 ldr w3, [x0,#8] - ab2c: d53bd040 mrs x0, tpidr_el0 - ab30: d11bc000 sub x0, x0, #0x6f0 - ab34: b940d000 ldr w0, [x0,#208] - ab38: 6b00007f cmp w3, w0 - ab3c: 54000060 b.eq ab48 <__pthread_mutex_unlock+0xf0> - ab40: 2a0103e4 mov w4, w1 - ab44: 17ffffd6 b aa9c <__pthread_mutex_unlock+0x44> - ab48: b9400440 ldr w0, [x2,#4] - ab4c: 51000400 sub w0, w0, #0x1 - ab50: b9000440 str w0, [x2,#4] - ab54: 34fff900 cbz w0, aa74 <__pthread_mutex_unlock+0x1c> - ab58: 17ffffd1 b aa9c <__pthread_mutex_unlock+0x44> - ab5c: 71000c3f cmp w1, #0x3 - ab60: 54fff8a0 b.eq aa74 <__pthread_mutex_unlock+0x1c> - ab64: b9400801 ldr w1, [x0,#8] - ab68: d53bd040 mrs x0, tpidr_el0 - ab6c: d11bc000 sub x0, x0, #0x6f0 - ab70: b940d000 ldr w0, [x0,#208] - ab74: 6b00003f cmp w1, w0 - ab78: 54000060 b.eq ab84 <__pthread_mutex_unlock+0x12c> - ab7c: 52800024 mov w4, #0x1 // #1 - ab80: 17ffffc7 b aa9c <__pthread_mutex_unlock+0x44> - ab84: b9400040 ldr w0, [x2] - ab88: 35fff760 cbnz w0, aa74 <__pthread_mutex_unlock+0x1c> - ab8c: 52800024 mov w4, #0x1 // #1 - ab90: 17ffffc3 b aa9c <__pthread_mutex_unlock+0x44> - -000000000000ab94 <__pthread_mutex_cond_lock_full>: - ab94: a9ba7bfd stp x29, x30, [sp,#-96]! - ab98: 910003fd mov x29, sp - ab9c: a9025bf5 stp x21, x22, [sp,#32] - aba0: a90153f3 stp x19, x20, [sp,#16] - aba4: a90363f7 stp x23, x24, [sp,#48] - aba8: f90023f9 str x25, [sp,#64] - abac: d53bd056 mrs x22, tpidr_el0 - abb0: d11bc2d6 sub x22, x22, #0x6f0 - abb4: b9401001 ldr w1, [x0,#16] - abb8: 12001822 and w2, w1, #0x7f - abbc: b940d2d5 ldr w21, [x22,#208] - abc0: 51004042 sub w2, w2, #0x10 - abc4: 7100cc5f cmp w2, #0x33 - abc8: 54000129 b.ls abec <__pthread_mutex_cond_lock_full+0x58> - abcc: 528002d4 mov w20, #0x16 // #22 - abd0: f94023f9 ldr x25, [sp,#64] - abd4: 2a1403e0 mov w0, w20 - abd8: a94153f3 ldp x19, x20, [sp,#16] - abdc: a9425bf5 ldp x21, x22, [sp,#32] - abe0: a94363f7 ldp x23, x24, [sp,#48] - abe4: a8c67bfd ldp x29, x30, [sp],#96 - abe8: d65f03c0 ret - abec: aa0003f3 mov x19, x0 - abf0: 90000040 adrp x0, 12000 <__pthread_current_priority+0xa8> - abf4: 91324000 add x0, x0, #0xc90 - abf8: 38624800 ldrb w0, [x0,w2,uxtw] - abfc: 10000062 adr x2, ac08 <__pthread_mutex_cond_lock_full+0x74> - ac00: 8b208840 add x0, x2, w0, sxtb #2 - ac04: d61f0000 br x0 - ac08: b9400a60 ldr w0, [x19,#8] - ac0c: b9400263 ldr w3, [x19] - ac10: 6b15001f cmp w0, w21 - ac14: 54001da0 b.eq afc8 <__pthread_mutex_cond_lock_full+0x434> - ac18: 12800016 mov w22, #0xffffffff // #-1 - ac1c: 53137c74 lsr w20, w3, #19 - ac20: 94001cce bl 11f58 <__pthread_current_priority> - ac24: 6b00029f cmp w20, w0 - ac28: 54001eab b.lt affc <__pthread_mutex_cond_lock_full+0x468> - ac2c: 2a1603e0 mov w0, w22 - ac30: 2a1403e1 mov w1, w20 - ac34: 94001c09 bl 11c58 <__pthread_tpp_change_priority> - ac38: 35001de0 cbnz w0, aff4 <__pthread_mutex_cond_lock_full+0x460> - ac3c: 910183a5 add x5, x29, #0x60 - ac40: 530d3284 lsl w4, w20, #19 - ac44: 321f0087 orr w7, w4, #0x2 - ac48: 2a0403e0 mov w0, w4 - ac4c: b81fcca4 str w4, [x5,#-4]! - ac50: 885ffe61 ldaxr w1, [x19] - ac54: 6b00003f cmp w1, w0 - ac58: 54000061 b.ne ac64 <__pthread_mutex_cond_lock_full+0xd0> - ac5c: 88027e67 stxr w2, w7, [x19] - ac60: 35ffff82 cbnz w2, ac50 <__pthread_mutex_cond_lock_full+0xbc> - ac64: 54000040 b.eq ac6c <__pthread_mutex_cond_lock_full+0xd8> - ac68: b9005fa1 str w1, [x29,#92] - ac6c: b9405fa0 ldr w0, [x29,#92] - ac70: 6b00009f cmp w4, w0 - ac74: 540004c0 b.eq ad0c <__pthread_mutex_cond_lock_full+0x178> - ac78: 32000089 orr w9, w4, #0x1 - ac7c: 93407cea sxtw x10, w7 - ac80: b9005fa9 str w9, [x29,#92] - ac84: b94000a0 ldr w0, [x5] - ac88: 885ffe63 ldaxr w3, [x19] - ac8c: 6b00007f cmp w3, w0 - ac90: 54000061 b.ne ac9c <__pthread_mutex_cond_lock_full+0x108> - ac94: 88017e67 stxr w1, w7, [x19] - ac98: 35ffff81 cbnz w1, ac88 <__pthread_mutex_cond_lock_full+0xf4> - ac9c: 54000040 b.eq aca4 <__pthread_mutex_cond_lock_full+0x110> - aca0: b90000a3 str w3, [x5] - aca4: b9405fa3 ldr w3, [x29,#92] - aca8: 120d3060 and w0, w3, #0xfff80000 - acac: 6b04001f cmp w0, w4 - acb0: 54001541 b.ne af58 <__pthread_mutex_cond_lock_full+0x3c4> - acb4: 6b03009f cmp w4, w3 - acb8: 54000120 b.eq acdc <__pthread_mutex_cond_lock_full+0x148> - acbc: b9401266 ldr w6, [x19,#16] - acc0: aa1303e0 mov x0, x19 - acc4: aa0a03e2 mov x2, x10 - acc8: d2800003 mov x3, #0x0 // #0 - accc: 2a2603e1 mvn w1, w6 - acd0: d2800c48 mov x8, #0x62 // #98 - acd4: 92790021 and x1, x1, #0x80 - acd8: d4000001 svc #0x0 - acdc: b9005fa4 str w4, [x29,#92] - ace0: b94000a0 ldr w0, [x5] - ace4: 885ffe63 ldaxr w3, [x19] - ace8: 6b00007f cmp w3, w0 - acec: 54000061 b.ne acf8 <__pthread_mutex_cond_lock_full+0x164> - acf0: 88017e67 stxr w1, w7, [x19] - acf4: 35ffff81 cbnz w1, ace4 <__pthread_mutex_cond_lock_full+0x150> - acf8: 54000040 b.eq ad00 <__pthread_mutex_cond_lock_full+0x16c> - acfc: b90000a3 str w3, [x5] - ad00: b9405fa0 ldr w0, [x29,#92] - ad04: 6b00009f cmp w4, w0 - ad08: 54fffbc1 b.ne ac80 <__pthread_mutex_cond_lock_full+0xec> - ad0c: 52800020 mov w0, #0x1 // #1 - ad10: b9000660 str w0, [x19,#4] - ad14: b9000a75 str w21, [x19,#8] - ad18: 52800014 mov w20, #0x0 // #0 - ad1c: 2a1403e0 mov w0, w20 - ad20: f94023f9 ldr x25, [sp,#64] - ad24: a94153f3 ldp x19, x20, [sp,#16] - ad28: a9425bf5 ldp x21, x22, [sp,#32] - ad2c: a94363f7 ldp x23, x24, [sp,#48] - ad30: a8c67bfd ldp x29, x30, [sp],#96 - ad34: d65f03c0 ret - ad38: 121c0024 and w4, w1, #0x10 - ad3c: 37201301 tbnz w1, #4, af9c <__pthread_mutex_cond_lock_full+0x408> - ad40: b9400260 ldr w0, [x19] - ad44: 12007400 and w0, w0, #0x3fffffff - ad48: 6b0002bf cmp w21, w0 - ad4c: 54001660 b.eq b018 <__pthread_mutex_cond_lock_full+0x484> - ad50: b9005fbf str wzr, [x29,#92] - ad54: 320102a1 orr w1, w21, #0x80000000 - ad58: 885ffe60 ldaxr w0, [x19] - ad5c: 6b1f001f cmp w0, wzr - ad60: 54000061 b.ne ad6c <__pthread_mutex_cond_lock_full+0x1d8> - ad64: 88027e61 stxr w2, w1, [x19] - ad68: 35ffff82 cbnz w2, ad58 <__pthread_mutex_cond_lock_full+0x1c4> - ad6c: 54001261 b.ne afb8 <__pthread_mutex_cond_lock_full+0x424> - ad70: b9405fa0 ldr w0, [x29,#92] - ad74: 34000a60 cbz w0, aec0 <__pthread_mutex_cond_lock_full+0x32c> - ad78: d28000c1 mov x1, #0x6 // #6 - ad7c: 350000c4 cbnz w4, ad94 <__pthread_mutex_cond_lock_full+0x200> - ad80: b9401261 ldr w1, [x19,#16] - ad84: 528010c0 mov w0, #0x86 // #134 - ad88: 12190021 and w1, w1, #0x80 - ad8c: 4a000021 eor w1, w1, w0 - ad90: 93407c21 sxtw x1, w1 - ad94: aa1303e0 mov x0, x19 - ad98: d2800022 mov x2, #0x1 // #1 - ad9c: d2800003 mov x3, #0x0 // #0 - ada0: d2800c48 mov x8, #0x62 // #98 - ada4: d4000001 svc #0x0 - ada8: 3140041f cmn w0, #0x1, lsl #12 - adac: 54000089 b.ls adbc <__pthread_mutex_cond_lock_full+0x228> - adb0: 121a7800 and w0, w0, #0xffffffdf - adb4: 31008c1f cmn w0, #0x23 - adb8: 54000fa0 b.eq afac <__pthread_mutex_cond_lock_full+0x418> - adbc: b9400260 ldr w0, [x19] - adc0: 36f00800 tbz w0, #30, aec0 <__pthread_mutex_cond_lock_full+0x32c> - adc4: 910173a5 add x5, x29, #0x5c - adc8: b9005fa0 str w0, [x29,#92] - adcc: 12017800 and w0, w0, #0xbfffffff - add0: b94000a2 ldr w2, [x5] - add4: 885ffe61 ldaxr w1, [x19] - add8: 6b02003f cmp w1, w2 - addc: 54000061 b.ne ade8 <__pthread_mutex_cond_lock_full+0x254> - ade0: 88037e60 stxr w3, w0, [x19] - ade4: 35ffff83 cbnz w3, add4 <__pthread_mutex_cond_lock_full+0x240> - ade8: 54001320 b.eq b04c <__pthread_mutex_cond_lock_full+0x4b8> - adec: b90000a1 str w1, [x5] - adf0: b9400260 ldr w0, [x19] - adf4: 17fffff5 b adc8 <__pthread_mutex_cond_lock_full+0x234> - adf8: 91008277 add x23, x19, #0x20 - adfc: f9007ad7 str x23, [x22,#240] - ae00: 320102b8 orr w24, w21, #0x80000000 - ae04: 321f77f9 mov w25, #0x7ffffffe // #2147483646 - ae08: b9400260 ldr w0, [x19] - ae0c: 12020014 and w20, w0, #0x40000000 - ae10: 35000a94 cbnz w20, af60 <__pthread_mutex_cond_lock_full+0x3cc> - ae14: 12007400 and w0, w0, #0x3fffffff - ae18: 6b0002bf cmp w21, w0 - ae1c: 54000380 b.eq ae8c <__pthread_mutex_cond_lock_full+0x2f8> - ae20: b9005fbf str wzr, [x29,#92] - ae24: 885ffe62 ldaxr w2, [x19] - ae28: 6b1f005f cmp w2, wzr - ae2c: 54000061 b.ne ae38 <__pthread_mutex_cond_lock_full+0x2a4> - ae30: 88007e78 stxr w0, w24, [x19] - ae34: 35ffff80 cbnz w0, ae24 <__pthread_mutex_cond_lock_full+0x290> - ae38: 54000680 b.eq af08 <__pthread_mutex_cond_lock_full+0x374> - ae3c: 52801001 mov w1, #0x80 // #128 - ae40: aa1303e0 mov x0, x19 - ae44: b9005fa2 str w2, [x29,#92] - ae48: 94001302 bl fa50 <__lll_robust_lock_wait> - ae4c: b9400a61 ldr w1, [x19,#8] - ae50: 6b19003f cmp w1, w25 - ae54: 54000620 b.eq af18 <__pthread_mutex_cond_lock_full+0x384> - ae58: 12020014 and w20, w0, #0x40000000 - ae5c: 37f7fda0 tbnz w0, #30, ae10 <__pthread_mutex_cond_lock_full+0x27c> - ae60: aa1603e0 mov x0, x22 - ae64: 52800021 mov w1, #0x1 // #1 - ae68: b9000661 str w1, [x19,#4] - ae6c: f84e0c01 ldr x1, [x0,#224]! - ae70: 927ff822 and x2, x1, #0xfffffffffffffffe - ae74: f81f8057 str x23, [x2,#-8] - ae78: f9001261 str x1, [x19,#32] - ae7c: f9000e60 str x0, [x19,#24] - ae80: f90072d7 str x23, [x22,#224] - ae84: f9007adf str xzr, [x22,#240] - ae88: 17ffffa3 b ad14 <__pthread_mutex_cond_lock_full+0x180> - ae8c: b9401260 ldr w0, [x19,#16] - ae90: 12001800 and w0, w0, #0x7f - ae94: 7100481f cmp w0, #0x12 - ae98: 54001440 b.eq b120 <__pthread_mutex_cond_lock_full+0x58c> - ae9c: 7100441f cmp w0, #0x11 - aea0: 54fffc01 b.ne ae20 <__pthread_mutex_cond_lock_full+0x28c> - aea4: f9007adf str xzr, [x22,#240] - aea8: b9400660 ldr w0, [x19,#4] - aeac: 3100041f cmn w0, #0x1 - aeb0: 540009e0 b.eq afec <__pthread_mutex_cond_lock_full+0x458> - aeb4: 11000400 add w0, w0, #0x1 - aeb8: b9000660 str w0, [x19,#4] - aebc: 17ffff98 b ad1c <__pthread_mutex_cond_lock_full+0x188> - aec0: 34fff264 cbz w4, ad0c <__pthread_mutex_cond_lock_full+0x178> - aec4: b9400a61 ldr w1, [x19,#8] - aec8: 321f77e0 mov w0, #0x7ffffffe // #2147483646 - aecc: 6b00003f cmp w1, w0 - aed0: 54001140 b.eq b0f8 <__pthread_mutex_cond_lock_full+0x564> - aed4: aa1603e0 mov x0, x22 - aed8: 52800021 mov w1, #0x1 // #1 - aedc: b9000661 str w1, [x19,#4] - aee0: 91008262 add x2, x19, #0x20 - aee4: b2400043 orr x3, x2, #0x1 - aee8: f84e0c01 ldr x1, [x0,#224]! - aeec: 927ff824 and x4, x1, #0xfffffffffffffffe - aef0: f81f8082 str x2, [x4,#-8] - aef4: f9001261 str x1, [x19,#32] - aef8: f9000e60 str x0, [x19,#24] - aefc: f90072c3 str x3, [x22,#224] - af00: f9007adf str xzr, [x22,#240] - af04: 17ffff84 b ad14 <__pthread_mutex_cond_lock_full+0x180> - af08: b9400a61 ldr w1, [x19,#8] - af0c: 321f77e0 mov w0, #0x7ffffffe // #2147483646 - af10: 6b00003f cmp w1, w0 - af14: 54fffa61 b.ne ae60 <__pthread_mutex_cond_lock_full+0x2cc> - af18: b900067f str wzr, [x19,#4] - af1c: 52800001 mov w1, #0x0 // #0 - af20: 885f7e60 ldxr w0, [x19] - af24: 8802fe61 stlxr w2, w1, [x19] - af28: 35ffffc2 cbnz w2, af20 <__pthread_mutex_cond_lock_full+0x38c> - af2c: 7100041f cmp w0, #0x1 - af30: 54000d6c b.gt b0dc <__pthread_mutex_cond_lock_full+0x548> - af34: f9007adf str xzr, [x22,#240] - af38: 52801074 mov w20, #0x83 // #131 - af3c: 2a1403e0 mov w0, w20 - af40: f94023f9 ldr x25, [sp,#64] - af44: a94153f3 ldp x19, x20, [sp,#16] - af48: a9425bf5 ldp x21, x22, [sp,#32] - af4c: a94363f7 ldp x23, x24, [sp,#48] - af50: a8c67bfd ldp x29, x30, [sp],#96 - af54: d65f03c0 ret - af58: 2a1403f6 mov w22, w20 - af5c: 17ffff30 b ac1c <__pthread_mutex_cond_lock_full+0x88> - af60: b9005fa0 str w0, [x29,#92] - af64: 2a0003e1 mov w1, w0 - af68: 885ffe62 ldaxr w2, [x19] - af6c: 6b01005f cmp w2, w1 - af70: 54000061 b.ne af7c <__pthread_mutex_cond_lock_full+0x3e8> - af74: 88037e78 stxr w3, w24, [x19] - af78: 35ffff83 cbnz w3, af68 <__pthread_mutex_cond_lock_full+0x3d4> - af7c: 54000040 b.eq af84 <__pthread_mutex_cond_lock_full+0x3f0> - af80: b9005fa2 str w2, [x29,#92] - af84: b9405fa1 ldr w1, [x29,#92] - af88: 6b01001f cmp w0, w1 - af8c: 54000860 b.eq b098 <__pthread_mutex_cond_lock_full+0x504> - af90: 2a0103e0 mov w0, w1 - af94: 12020034 and w20, w1, #0x40000000 - af98: 17ffff9e b ae10 <__pthread_mutex_cond_lock_full+0x27c> - af9c: 91008260 add x0, x19, #0x20 - afa0: b2400000 orr x0, x0, #0x1 - afa4: f9007ac0 str x0, [x22,#240] - afa8: 17ffff66 b ad40 <__pthread_mutex_cond_lock_full+0x1ac> - afac: 940016ab bl 10a58 <__pause_nocancel> - afb0: 940016aa bl 10a58 <__pause_nocancel> - afb4: 17fffffe b afac <__pthread_mutex_cond_lock_full+0x418> - afb8: b9005fa0 str w0, [x29,#92] - afbc: b9405fa0 ldr w0, [x29,#92] - afc0: 34fff800 cbz w0, aec0 <__pthread_mutex_cond_lock_full+0x32c> - afc4: 17ffff6d b ad78 <__pthread_mutex_cond_lock_full+0x1e4> - afc8: 12000421 and w1, w1, #0x3 - afcc: 52800474 mov w20, #0x23 // #35 - afd0: 7100083f cmp w1, #0x2 - afd4: 54ffea40 b.eq ad1c <__pthread_mutex_cond_lock_full+0x188> - afd8: 7100043f cmp w1, #0x1 - afdc: 54ffe1e1 b.ne ac18 <__pthread_mutex_cond_lock_full+0x84> - afe0: b9400660 ldr w0, [x19,#4] - afe4: 3100041f cmn w0, #0x1 - afe8: 540002a1 b.ne b03c <__pthread_mutex_cond_lock_full+0x4a8> - afec: 52800174 mov w20, #0xb // #11 - aff0: 17ffff4b b ad1c <__pthread_mutex_cond_lock_full+0x188> - aff4: 2a0003f4 mov w20, w0 - aff8: 17ffff49 b ad1c <__pthread_mutex_cond_lock_full+0x188> - affc: 310006df cmn w22, #0x1 - b000: 528002d4 mov w20, #0x16 // #22 - b004: 54ffe8c0 b.eq ad1c <__pthread_mutex_cond_lock_full+0x188> - b008: 2a1603e0 mov w0, w22 - b00c: 12800001 mov w1, #0xffffffff // #-1 - b010: 94001b12 bl 11c58 <__pthread_tpp_change_priority> - b014: 17ffff42 b ad1c <__pthread_mutex_cond_lock_full+0x188> - b018: 12000421 and w1, w1, #0x3 - b01c: 7100083f cmp w1, #0x2 - b020: 54000800 b.eq b120 <__pthread_mutex_cond_lock_full+0x58c> - b024: 7100043f cmp w1, #0x1 - b028: 54ffe941 b.ne ad50 <__pthread_mutex_cond_lock_full+0x1bc> - b02c: f9007adf str xzr, [x22,#240] - b030: b9400660 ldr w0, [x19,#4] - b034: 3100041f cmn w0, #0x1 - b038: 54fffda0 b.eq afec <__pthread_mutex_cond_lock_full+0x458> - b03c: 11000400 add w0, w0, #0x1 - b040: 52800014 mov w20, #0x0 // #0 - b044: b9000660 str w0, [x19,#4] - b048: 17ffff35 b ad1c <__pthread_mutex_cond_lock_full+0x188> - b04c: aa1603e0 mov x0, x22 - b050: 52800021 mov w1, #0x1 // #1 - b054: b9000661 str w1, [x19,#4] - b058: 12b00001 mov w1, #0x7fffffff // #2147483647 - b05c: b9000a61 str w1, [x19,#8] - b060: 91008262 add x2, x19, #0x20 - b064: b2400043 orr x3, x2, #0x1 - b068: 52801054 mov w20, #0x82 // #130 - b06c: f84e0c01 ldr x1, [x0,#224]! - b070: 927ff824 and x4, x1, #0xfffffffffffffffe - b074: f81f8082 str x2, [x4,#-8] - b078: f9000e60 str x0, [x19,#24] - b07c: f9001261 str x1, [x19,#32] - b080: f90072c3 str x3, [x22,#224] - b084: f9007adf str xzr, [x22,#240] - b088: b9400e60 ldr w0, [x19,#12] - b08c: 51000400 sub w0, w0, #0x1 - b090: b9000e60 str w0, [x19,#12] - b094: 17ffff22 b ad1c <__pthread_mutex_cond_lock_full+0x188> - b098: aa1603e0 mov x0, x22 - b09c: 52800021 mov w1, #0x1 // #1 - b0a0: b9000661 str w1, [x19,#4] - b0a4: 12b00001 mov w1, #0x7fffffff // #2147483647 - b0a8: b9000a61 str w1, [x19,#8] - b0ac: 52801054 mov w20, #0x82 // #130 - b0b0: f84e0c01 ldr x1, [x0,#224]! - b0b4: 927ff822 and x2, x1, #0xfffffffffffffffe - b0b8: f81f8057 str x23, [x2,#-8] - b0bc: f9000e60 str x0, [x19,#24] - b0c0: f9001261 str x1, [x19,#32] - b0c4: f90072d7 str x23, [x22,#224] - b0c8: f9007adf str xzr, [x22,#240] - b0cc: b9400e60 ldr w0, [x19,#12] - b0d0: 51000400 sub w0, w0, #0x1 - b0d4: b9000e60 str w0, [x19,#12] - b0d8: 17ffff11 b ad1c <__pthread_mutex_cond_lock_full+0x188> - b0dc: d2800021 mov x1, #0x1 // #1 - b0e0: aa1303e0 mov x0, x19 - b0e4: aa0103e2 mov x2, x1 - b0e8: d2800003 mov x3, #0x0 // #0 - b0ec: d2800c48 mov x8, #0x62 // #98 - b0f0: d4000001 svc #0x0 - b0f4: 17ffff90 b af34 <__pthread_mutex_cond_lock_full+0x3a0> - b0f8: d2800002 mov x2, #0x0 // #0 - b0fc: b900067f str wzr, [x19,#4] - b100: aa1303e0 mov x0, x19 - b104: d28000e1 mov x1, #0x7 // #7 - b108: aa0203e3 mov x3, x2 - b10c: d2800c48 mov x8, #0x62 // #98 - b110: d4000001 svc #0x0 - b114: 52801074 mov w20, #0x83 // #131 - b118: f9007ac2 str x2, [x22,#240] - b11c: 17ffff00 b ad1c <__pthread_mutex_cond_lock_full+0x188> - b120: f9007adf str xzr, [x22,#240] - b124: 52800474 mov w20, #0x23 // #35 - b128: 17fffefd b ad1c <__pthread_mutex_cond_lock_full+0x188> - -000000000000b12c <__pthread_mutex_cond_lock>: - b12c: a9bc7bfd stp x29, x30, [sp,#-64]! - b130: 52802fe2 mov w2, #0x17f // #383 - b134: 910003fd mov x29, sp - b138: a90153f3 stp x19, x20, [sp,#16] - b13c: f90013f5 str x21, [sp,#32] - b140: aa0003f3 mov x19, x0 - b144: b9401001 ldr w1, [x0,#16] - b148: 721e1023 ands w3, w1, #0x7c - b14c: 0a020022 and w2, w1, w2 - b150: 540004e1 b.ne b1ec <__pthread_mutex_cond_lock+0xc0> - b154: 350001e2 cbnz w2, b190 <__pthread_mutex_cond_lock+0x64> - b158: d53bd054 mrs x20, tpidr_el0 - b15c: 52800041 mov w1, #0x2 // #2 - b160: 885ffe60 ldaxr w0, [x19] - b164: 88027e61 stxr w2, w1, [x19] - b168: 35ffffc2 cbnz w2, b160 <__pthread_mutex_cond_lock+0x34> - b16c: 35000340 cbnz w0, b1d4 <__pthread_mutex_cond_lock+0xa8> - b170: d11bc294 sub x20, x20, #0x6f0 - b174: b940d281 ldr w1, [x20,#208] - b178: 52800000 mov w0, #0x0 // #0 - b17c: b9000a61 str w1, [x19,#8] - b180: a94153f3 ldp x19, x20, [sp,#16] - b184: f94013f5 ldr x21, [sp,#32] - b188: a8c47bfd ldp x29, x30, [sp],#64 - b18c: d65f03c0 ret - b190: 12001821 and w1, w1, #0x7f - b194: 7100043f cmp w1, #0x1 - b198: 54000421 b.ne b21c <__pthread_mutex_cond_lock+0xf0> - b19c: d53bd054 mrs x20, tpidr_el0 - b1a0: b9400802 ldr w2, [x0,#8] - b1a4: d11bc294 sub x20, x20, #0x6f0 - b1a8: b940d281 ldr w1, [x20,#208] - b1ac: 6b01005f cmp w2, w1 - b1b0: 54000280 b.eq b200 <__pthread_mutex_cond_lock+0xd4> - b1b4: 52800042 mov w2, #0x2 // #2 - b1b8: 885ffe61 ldaxr w1, [x19] - b1bc: 88037e62 stxr w3, w2, [x19] - b1c0: 35ffffc3 cbnz w3, b1b8 <__pthread_mutex_cond_lock+0x8c> - b1c4: 350004c1 cbnz w1, b25c <__pthread_mutex_cond_lock+0x130> - b1c8: 52800020 mov w0, #0x1 // #1 - b1cc: b9000660 str w0, [x19,#4] - b1d0: 17ffffe9 b b174 <__pthread_mutex_cond_lock+0x48> - b1d4: b9401261 ldr w1, [x19,#16] - b1d8: aa1303e0 mov x0, x19 - b1dc: d11bc294 sub x20, x20, #0x6f0 - b1e0: 12190021 and w1, w1, #0x80 - b1e4: 94001178 bl f7c4 <__lll_lock_wait> - b1e8: 17ffffe3 b b174 <__pthread_mutex_cond_lock+0x48> - b1ec: 97fffe6a bl ab94 <__pthread_mutex_cond_lock_full> - b1f0: f94013f5 ldr x21, [sp,#32] - b1f4: a94153f3 ldp x19, x20, [sp,#16] - b1f8: a8c47bfd ldp x29, x30, [sp],#64 - b1fc: d65f03c0 ret - b200: b9400400 ldr w0, [x0,#4] - b204: 3100041f cmn w0, #0x1 - b208: 54000320 b.eq b26c <__pthread_mutex_cond_lock+0x140> - b20c: 11000401 add w1, w0, #0x1 - b210: 2a0303e0 mov w0, w3 - b214: b9000661 str w1, [x19,#4] - b218: 17ffffda b b180 <__pthread_mutex_cond_lock+0x54> - b21c: 71000c3f cmp w1, #0x3 - b220: 540007a1 b.ne b314 <__pthread_mutex_cond_lock+0x1e8> - b224: b0000140 adrp x0, 34000 <__GI___pthread_keys+0x3d78> - b228: b9432c00 ldr w0, [x0,#812] - b22c: 34fff960 cbz w0, b158 <__pthread_mutex_cond_lock+0x2c> - b230: b9003fa3 str w3, [x29,#60] - b234: 52800042 mov w2, #0x2 // #2 - b238: 885ffe60 ldaxr w0, [x19] - b23c: 6b1f001f cmp w0, wzr - b240: 54000061 b.ne b24c <__pthread_mutex_cond_lock+0x120> - b244: 88017e62 stxr w1, w2, [x19] - b248: 35ffff81 cbnz w1, b238 <__pthread_mutex_cond_lock+0x10c> - b24c: 1a9f17f5 cset w21, eq - b250: 34000135 cbz w21, b274 <__pthread_mutex_cond_lock+0x148> - b254: d53bd054 mrs x20, tpidr_el0 - b258: 17ffffc6 b b170 <__pthread_mutex_cond_lock+0x44> - b25c: b9401261 ldr w1, [x19,#16] - b260: 12190021 and w1, w1, #0x80 - b264: 94001158 bl f7c4 <__lll_lock_wait> - b268: 17ffffd8 b b1c8 <__pthread_mutex_cond_lock+0x9c> - b26c: 52800160 mov w0, #0xb // #11 - b270: 17ffffc4 b b180 <__pthread_mutex_cond_lock+0x54> - b274: b9401661 ldr w1, [x19,#20] - b278: b9003fa0 str w0, [x29,#60] - b27c: 52800c80 mov w0, #0x64 // #100 - b280: 11001421 add w1, w1, #0x5 - b284: 531f7821 lsl w1, w1, #1 - b288: 7101903f cmp w1, #0x64 - b28c: 1a80d021 csel w1, w1, w0, le - b290: 110006b5 add w21, w21, #0x1 - b294: 510006a0 sub w0, w21, #0x1 - b298: 6b01001f cmp w0, w1 - b29c: 5400028a b.ge b2ec <__pthread_mutex_cond_lock+0x1c0> - b2a0: b9003fbf str wzr, [x29,#60] - b2a4: 885ffe60 ldaxr w0, [x19] - b2a8: 6b1f001f cmp w0, wzr - b2ac: 54000061 b.ne b2b8 <__pthread_mutex_cond_lock+0x18c> - b2b0: 88037e62 stxr w3, w2, [x19] - b2b4: 35ffff83 cbnz w3, b2a4 <__pthread_mutex_cond_lock+0x178> - b2b8: 54000161 b.ne b2e4 <__pthread_mutex_cond_lock+0x1b8> - b2bc: b9401661 ldr w1, [x19,#20] - b2c0: d53bd054 mrs x20, tpidr_el0 - b2c4: d11bc294 sub x20, x20, #0x6f0 - b2c8: 4b0102b5 sub w21, w21, w1 - b2cc: 11001ea0 add w0, w21, #0x7 - b2d0: 6b1f02bf cmp w21, wzr - b2d4: 1a95b015 csel w21, w0, w21, lt - b2d8: 0b950c35 add w21, w1, w21, asr #3 - b2dc: b9001675 str w21, [x19,#20] - b2e0: 17ffffa5 b b174 <__pthread_mutex_cond_lock+0x48> - b2e4: b9003fa0 str w0, [x29,#60] - b2e8: 17ffffea b b290 <__pthread_mutex_cond_lock+0x164> - b2ec: 52800041 mov w1, #0x2 // #2 - b2f0: 885ffe60 ldaxr w0, [x19] - b2f4: 88027e61 stxr w2, w1, [x19] - b2f8: 35ffffc2 cbnz w2, b2f0 <__pthread_mutex_cond_lock+0x1c4> - b2fc: 34fffe00 cbz w0, b2bc <__pthread_mutex_cond_lock+0x190> - b300: b9401261 ldr w1, [x19,#16] - b304: aa1303e0 mov x0, x19 - b308: 12190021 and w1, w1, #0x80 - b30c: 9400112e bl f7c4 <__lll_lock_wait> - b310: 17ffffeb b b2bc <__pthread_mutex_cond_lock+0x190> - b314: d53bd054 mrs x20, tpidr_el0 - b318: b9400800 ldr w0, [x0,#8] - b31c: d11bc281 sub x1, x20, #0x6f0 - b320: b940d021 ldr w1, [x1,#208] - b324: 6b00003f cmp w1, w0 - b328: 54fff1a1 b.ne b15c <__pthread_mutex_cond_lock+0x30> - b32c: 52800460 mov w0, #0x23 // #35 - b330: 17ffff94 b b180 <__pthread_mutex_cond_lock+0x54> - -000000000000b334 <__pthread_mutex_cond_lock_adjust>: - b334: d53bd041 mrs x1, tpidr_el0 - b338: b9401002 ldr w2, [x0,#16] - b33c: d11bc021 sub x1, x1, #0x6f0 - b340: 7100845f cmp w2, #0x21 - b344: b940d021 ldr w1, [x1,#208] - b348: b9000801 str w1, [x0,#8] - b34c: 54000040 b.eq b354 <__pthread_mutex_cond_lock_adjust+0x20> - b350: d65f03c0 ret - b354: b9400401 ldr w1, [x0,#4] - b358: 11000421 add w1, w1, #0x1 - b35c: b9000401 str w1, [x0,#4] - b360: d65f03c0 ret - -000000000000b364 <__pthread_mutexattr_init>: - b364: f900001f str xzr, [x0] - b368: 52800000 mov w0, #0x0 // #0 - b36c: d65f03c0 ret - -000000000000b370 <__pthread_mutexattr_destroy>: - b370: 52800000 mov w0, #0x0 // #0 - b374: d65f03c0 ret - -000000000000b378 : - b378: b9400002 ldr w2, [x0] - b37c: 52800000 mov w0, #0x0 // #0 - b380: 531f7c42 lsr w2, w2, #31 - b384: b9000022 str w2, [x1] - b388: d65f03c0 ret - -000000000000b38c : - b38c: 350000c1 cbnz w1, b3a4 - b390: b9400002 ldr w2, [x0] - b394: 12007842 and w2, w2, #0x7fffffff - b398: b9000002 str w2, [x0] - b39c: 2a0103e0 mov w0, w1 - b3a0: d65f03c0 ret - b3a4: 7100043f cmp w1, #0x1 - b3a8: 540000e1 b.ne b3c4 - b3ac: b9400002 ldr w2, [x0] - b3b0: 52800001 mov w1, #0x0 // #0 - b3b4: 32010042 orr w2, w2, #0x80000000 - b3b8: b9000002 str w2, [x0] - b3bc: 2a0103e0 mov w0, w1 - b3c0: d65f03c0 ret - b3c4: 528002c1 mov w1, #0x16 // #22 - b3c8: 17fffff5 b b39c - -000000000000b3cc : - b3cc: b9400003 ldr w3, [x0] - b3d0: 5281ffe2 mov w2, #0xfff // #4095 - b3d4: 72a1e002 movk w2, #0xf00, lsl #16 - b3d8: 52800000 mov w0, #0x0 // #0 - b3dc: 0a020062 and w2, w3, w2 - b3e0: b9000022 str w2, [x1] - b3e4: d65f03c0 ret - -000000000000b3e8 <__pthread_mutexattr_settype>: - b3e8: 71000c3f cmp w1, #0x3 - b3ec: aa0003e3 mov x3, x0 - b3f0: 528002c0 mov w0, #0x16 // #22 - b3f4: 54000049 b.ls b3fc <__pthread_mutexattr_settype+0x14> - b3f8: d65f03c0 ret - b3fc: b9400060 ldr w0, [x3] - b400: 529e0002 mov w2, #0xf000 // #61440 - b404: 6b1f003f cmp w1, wzr - b408: 52804004 mov w4, #0x200 // #512 - b40c: 72be1fe2 movk w2, #0xf0ff, lsl #16 - b410: 1a841021 csel w1, w1, w4, ne - b414: 0a020002 and w2, w0, w2 - b418: 52800000 mov w0, #0x0 // #0 - b41c: 2a020021 orr w1, w1, w2 - b420: b9000061 str w1, [x3] - b424: d65f03c0 ret - -000000000000b428 <__pthread_rwlock_init>: - b428: aa0003e2 mov x2, x0 - b42c: b4000201 cbz x1, b46c <__pthread_rwlock_init+0x44> - b430: a9017c5f stp xzr, xzr, [x2,#16] - b434: f900185f str xzr, [x2,#48] - b438: 52800000 mov w0, #0x0 // #0 - b43c: a9007c5f stp xzr, xzr, [x2] - b440: a9027c5f stp xzr, xzr, [x2,#32] - b444: b9400023 ldr w3, [x1] - b448: 7100087f cmp w3, #0x2 - b44c: 1a9f17e3 cset w3, eq - b450: b9003043 str w3, [x2,#48] - b454: 52801003 mov w3, #0x80 // #128 - b458: b9400421 ldr w1, [x1,#4] - b45c: 6b00003f cmp w1, w0 - b460: 1a830021 csel w1, w1, w3, eq - b464: b9001c41 str w1, [x2,#28] - b468: d65f03c0 ret - b46c: f0000021 adrp x1, 12000 <__pthread_current_priority+0xa8> - b470: 912ee021 add x1, x1, #0xbb8 - b474: 17ffffef b b430 <__pthread_rwlock_init+0x8> - -000000000000b478 <__pthread_rwlock_destroy>: - b478: 52800000 mov w0, #0x0 // #0 - b47c: d65f03c0 ret - -000000000000b480 <__pthread_rwlock_rdlock_slow>: - b480: a9bb7bfd stp x29, x30, [sp,#-80]! - b484: 910003fd mov x29, sp - b488: a90153f3 stp x19, x20, [sp,#16] - b48c: a9025bf5 stp x21, x22, [sp,#32] - b490: f9001bf7 str x23, [sp,#48] - b494: d53bd054 mrs x20, tpidr_el0 - b498: aa0003f3 mov x19, x0 - b49c: d11bc294 sub x20, x20, #0x6f0 - b4a0: b9401801 ldr w1, [x0,#24] - b4a4: 52800016 mov w22, #0x0 // #0 - b4a8: 52801037 mov w23, #0x81 // #129 - b4ac: 52800035 mov w21, #0x1 // #1 - b4b0: b940d280 ldr w0, [x20,#208] - b4b4: 6b01001f cmp w0, w1 - b4b8: 54000700 b.eq b598 <__pthread_rwlock_rdlock_slow+0x118> - b4bc: b9401261 ldr w1, [x19,#16] - b4c0: 11000420 add w0, w1, #0x1 - b4c4: b9001260 str w0, [x19,#16] - b4c8: 340006c0 cbz w0, b5a0 <__pthread_rwlock_rdlock_slow+0x120> - b4cc: b9400a64 ldr w4, [x19,#8] - b4d0: 885f7e60 ldxr w0, [x19] - b4d4: 8801fe76 stlxr w1, w22, [x19] - b4d8: 35ffffc1 cbnz w1, b4d0 <__pthread_rwlock_rdlock_slow+0x50> - b4dc: 7100041f cmp w0, #0x1 - b4e0: 5400066c b.gt b5ac <__pthread_rwlock_rdlock_slow+0x12c> - b4e4: b9401e61 ldr w1, [x19,#28] - b4e8: 93407c82 sxtw x2, w4 - b4ec: 91002260 add x0, x19, #0x8 - b4f0: d2800003 mov x3, #0x0 // #0 - b4f4: 52190021 eor w1, w1, #0x80 - b4f8: d2800c48 mov x8, #0x62 // #98 - b4fc: 93407c21 sxtw x1, w1 - b500: d4000001 svc #0x0 - b504: b9004fa3 str w3, [x29,#76] - b508: 885ffe62 ldaxr w2, [x19] - b50c: 6b1f005f cmp w2, wzr - b510: 54000061 b.ne b51c <__pthread_rwlock_rdlock_slow+0x9c> - b514: 88007e75 stxr w0, w21, [x19] - b518: 35ffff80 cbnz w0, b508 <__pthread_rwlock_rdlock_slow+0x88> - b51c: aa1303e0 mov x0, x19 - b520: 54000080 b.eq b530 <__pthread_rwlock_rdlock_slow+0xb0> - b524: b9401e61 ldr w1, [x19,#28] - b528: b9004fa2 str w2, [x29,#76] - b52c: 940010a6 bl f7c4 <__lll_lock_wait> - b530: b9401260 ldr w0, [x19,#16] - b534: b9401a61 ldr w1, [x19,#24] - b538: 51000400 sub w0, w0, #0x1 - b53c: b9001260 str w0, [x19,#16] - b540: 35fffb81 cbnz w1, b4b0 <__pthread_rwlock_rdlock_slow+0x30> - b544: b9401660 ldr w0, [x19,#20] - b548: 34000060 cbz w0, b554 <__pthread_rwlock_rdlock_slow+0xd4> - b54c: b9403260 ldr w0, [x19,#48] - b550: 35fffb00 cbnz w0, b4b0 <__pthread_rwlock_rdlock_slow+0x30> - b554: b9400661 ldr w1, [x19,#4] - b558: 52800004 mov w4, #0x0 // #0 - b55c: 11000420 add w0, w1, #0x1 - b560: b9000660 str w0, [x19,#4] - b564: 34000540 cbz w0, b60c <__pthread_rwlock_rdlock_slow+0x18c> - b568: 52800001 mov w1, #0x0 // #0 - b56c: 885f7e60 ldxr w0, [x19] - b570: 8802fe61 stlxr w2, w1, [x19] - b574: 35ffffc2 cbnz w2, b56c <__pthread_rwlock_rdlock_slow+0xec> - b578: 7100041f cmp w0, #0x1 - b57c: 540002ac b.gt b5d0 <__pthread_rwlock_rdlock_slow+0x150> - b580: 2a0403e0 mov w0, w4 - b584: f9401bf7 ldr x23, [sp,#48] - b588: a94153f3 ldp x19, x20, [sp,#16] - b58c: a9425bf5 ldp x21, x22, [sp,#32] - b590: a8c57bfd ldp x29, x30, [sp],#80 - b594: d65f03c0 ret - b598: 52800464 mov w4, #0x23 // #35 - b59c: 17fffff3 b b568 <__pthread_rwlock_rdlock_slow+0xe8> - b5a0: b9001261 str w1, [x19,#16] - b5a4: 52800164 mov w4, #0xb // #11 - b5a8: 17fffff0 b b568 <__pthread_rwlock_rdlock_slow+0xe8> - b5ac: b9401e61 ldr w1, [x19,#28] - b5b0: aa1303e0 mov x0, x19 - b5b4: d2800022 mov x2, #0x1 // #1 - b5b8: d2800003 mov x3, #0x0 // #0 - b5bc: 4a170021 eor w1, w1, w23 - b5c0: d2800c48 mov x8, #0x62 // #98 - b5c4: 93407c21 sxtw x1, w1 - b5c8: d4000001 svc #0x0 - b5cc: 17ffffc6 b b4e4 <__pthread_rwlock_rdlock_slow+0x64> - b5d0: b9401e63 ldr w3, [x19,#28] - b5d4: 52801021 mov w1, #0x81 // #129 - b5d8: aa1303e0 mov x0, x19 - b5dc: d2800022 mov x2, #0x1 // #1 - b5e0: 4a010061 eor w1, w3, w1 - b5e4: d2800c48 mov x8, #0x62 // #98 - b5e8: d2800003 mov x3, #0x0 // #0 - b5ec: 93407c21 sxtw x1, w1 - b5f0: d4000001 svc #0x0 - b5f4: 2a0403e0 mov w0, w4 - b5f8: f9401bf7 ldr x23, [sp,#48] - b5fc: a94153f3 ldp x19, x20, [sp,#16] - b600: a9425bf5 ldp x21, x22, [sp,#32] - b604: a8c57bfd ldp x29, x30, [sp],#80 - b608: d65f03c0 ret - b60c: b9000661 str w1, [x19,#4] - b610: 52800164 mov w4, #0xb // #11 - b614: 17ffffd5 b b568 <__pthread_rwlock_rdlock_slow+0xe8> - -000000000000b618 <__pthread_rwlock_rdlock>: - b618: a9bd7bfd stp x29, x30, [sp,#-48]! - b61c: 52800021 mov w1, #0x1 // #1 - b620: 910003fd mov x29, sp - b624: f9000bf3 str x19, [sp,#16] - b628: aa0003f3 mov x19, x0 - b62c: b9002fbf str wzr, [x29,#44] - b630: 885ffe62 ldaxr w2, [x19] - b634: 6b1f005f cmp w2, wzr - b638: 54000061 b.ne b644 <__pthread_rwlock_rdlock+0x2c> - b63c: 88037e61 stxr w3, w1, [x19] - b640: 35ffff83 cbnz w3, b630 <__pthread_rwlock_rdlock+0x18> - b644: 54000281 b.ne b694 <__pthread_rwlock_rdlock+0x7c> - b648: b9401a60 ldr w0, [x19,#24] - b64c: 350002e0 cbnz w0, b6a8 <__pthread_rwlock_rdlock+0x90> - b650: b9401660 ldr w0, [x19,#20] - b654: 35000380 cbnz w0, b6c4 <__pthread_rwlock_rdlock+0xac> - b658: b9400661 ldr w1, [x19,#4] - b65c: 52800004 mov w4, #0x0 // #0 - b660: 11000420 add w0, w1, #0x1 - b664: b9000660 str w0, [x19,#4] - b668: 340003c0 cbz w0, b6e0 <__pthread_rwlock_rdlock+0xc8> - b66c: 52800001 mov w1, #0x0 // #0 - b670: 885f7e60 ldxr w0, [x19] - b674: 8802fe61 stlxr w2, w1, [x19] - b678: 35ffffc2 cbnz w2, b670 <__pthread_rwlock_rdlock+0x58> - b67c: 7100041f cmp w0, #0x1 - b680: 5400036c b.gt b6ec <__pthread_rwlock_rdlock+0xd4> - b684: 2a0403e0 mov w0, w4 - b688: f9400bf3 ldr x19, [sp,#16] - b68c: a8c37bfd ldp x29, x30, [sp],#48 - b690: d65f03c0 ret - b694: b9401e61 ldr w1, [x19,#28] - b698: b9002fa2 str w2, [x29,#44] - b69c: 9400104a bl f7c4 <__lll_lock_wait> - b6a0: b9401a60 ldr w0, [x19,#24] - b6a4: 34fffd60 cbz w0, b650 <__pthread_rwlock_rdlock+0x38> - b6a8: aa1303e0 mov x0, x19 - b6ac: 97ffff75 bl b480 <__pthread_rwlock_rdlock_slow> - b6b0: 2a0003e4 mov w4, w0 - b6b4: 2a0403e0 mov w0, w4 - b6b8: f9400bf3 ldr x19, [sp,#16] - b6bc: a8c37bfd ldp x29, x30, [sp],#48 - b6c0: d65f03c0 ret - b6c4: b9403260 ldr w0, [x19,#48] - b6c8: 35ffff00 cbnz w0, b6a8 <__pthread_rwlock_rdlock+0x90> - b6cc: b9400661 ldr w1, [x19,#4] - b6d0: 52800004 mov w4, #0x0 // #0 - b6d4: 11000420 add w0, w1, #0x1 - b6d8: b9000660 str w0, [x19,#4] - b6dc: 35fffc80 cbnz w0, b66c <__pthread_rwlock_rdlock+0x54> - b6e0: b9000661 str w1, [x19,#4] - b6e4: 52800164 mov w4, #0xb // #11 - b6e8: 17ffffe1 b b66c <__pthread_rwlock_rdlock+0x54> - b6ec: b9401e63 ldr w3, [x19,#28] - b6f0: 52801021 mov w1, #0x81 // #129 - b6f4: aa1303e0 mov x0, x19 - b6f8: d2800022 mov x2, #0x1 // #1 - b6fc: 4a010061 eor w1, w3, w1 - b700: d2800c48 mov x8, #0x62 // #98 - b704: d2800003 mov x3, #0x0 // #0 - b708: 93407c21 sxtw x1, w1 - b70c: d4000001 svc #0x0 - b710: 17ffffdd b b684 <__pthread_rwlock_rdlock+0x6c> - -000000000000b714 : - b714: a9ba7bfd stp x29, x30, [sp,#-96]! - b718: 910003fd mov x29, sp - b71c: a90153f3 stp x19, x20, [sp,#16] - b720: a9025bf5 stp x21, x22, [sp,#32] - b724: aa0103f4 mov x20, x1 - b728: b9005fbf str wzr, [x29,#92] - b72c: a90363f7 stp x23, x24, [sp,#48] - b730: aa0003f3 mov x19, x0 - b734: 52800021 mov w1, #0x1 // #1 - b738: 885ffe62 ldaxr w2, [x19] - b73c: 6b1f005f cmp w2, wzr - b740: 54000061 b.ne b74c - b744: 88037e61 stxr w3, w1, [x19] - b748: 35ffff83 cbnz w3, b738 - b74c: 54000721 b.ne b830 - b750: d53bd055 mrs x21, tpidr_el0 - b754: 52800017 mov w23, #0x0 // #0 - b758: d11bc2b5 sub x21, x21, #0x6f0 - b75c: 52801038 mov w24, #0x81 // #129 - b760: 52803136 mov w22, #0x189 // #393 - b764: b9401a60 ldr w0, [x19,#24] - b768: 350000a0 cbnz w0, b77c - b76c: b9401661 ldr w1, [x19,#20] - b770: 34000f21 cbz w1, b954 - b774: b9403261 ldr w1, [x19,#48] - b778: 34000ee1 cbz w1, b954 - b77c: b940d2a1 ldr w1, [x21,#208] - b780: 6b01001f cmp w0, w1 - b784: 54000b00 b.eq b8e4 - b788: f9400681 ldr x1, [x20,#8] - b78c: d2993fe0 mov x0, #0xc9ff // #51711 - b790: f2a77340 movk x0, #0x3b9a, lsl #16 - b794: eb00003f cmp x1, x0 - b798: 54000aa8 b.hi b8ec - b79c: f9400280 ldr x0, [x20] - b7a0: b7f80760 tbnz x0, #63, b88c - b7a4: b9401261 ldr w1, [x19,#16] - b7a8: 11000420 add w0, w1, #0x1 - b7ac: b9001260 str w0, [x19,#16] - b7b0: 34000e00 cbz w0, b970 - b7b4: b9400a65 ldr w5, [x19,#8] - b7b8: 885f7e60 ldxr w0, [x19] - b7bc: 8801fe77 stlxr w1, w23, [x19] - b7c0: 35ffffc1 cbnz w1, b7b8 - b7c4: 7100041f cmp w0, #0x1 - b7c8: 5400096c b.gt b8f4 - b7cc: b9401e64 ldr w4, [x19,#28] - b7d0: 93407ca2 sxtw x2, w5 - b7d4: 91002260 add x0, x19, #0x8 - b7d8: aa1403e3 mov x3, x20 - b7dc: 4a160081 eor w1, w4, w22 - b7e0: b2407fe5 mov x5, #0xffffffff // #4294967295 - b7e4: d2800004 mov x4, #0x0 // #0 - b7e8: d2800c48 mov x8, #0x62 // #98 - b7ec: 93407c21 sxtw x1, w1 - b7f0: d4000001 svc #0x0 - b7f4: b9005fa4 str w4, [x29,#92] - b7f8: b140041f cmn x0, #0x1, lsl #12 - b7fc: 54000228 b.hi b840 - b800: 2a0403e0 mov w0, w4 - b804: 52800021 mov w1, #0x1 // #1 - b808: 885ffe62 ldaxr w2, [x19] - b80c: 6b00005f cmp w2, w0 - b810: 54000061 b.ne b81c - b814: 88037e61 stxr w3, w1, [x19] - b818: 35ffff83 cbnz w3, b808 - b81c: 54000601 b.ne b8dc - b820: b9401260 ldr w0, [x19,#16] - b824: 51000400 sub w0, w0, #0x1 - b828: b9001260 str w0, [x19,#16] - b82c: 17ffffce b b764 - b830: b9401e61 ldr w1, [x19,#28] - b834: b9005fa2 str w2, [x29,#92] - b838: 94000fe3 bl f7c4 <__lll_lock_wait> - b83c: 17ffffc5 b b750 - b840: 52800021 mov w1, #0x1 // #1 - b844: 885ffe62 ldaxr w2, [x19] - b848: 6b1f005f cmp w2, wzr - b84c: 54000061 b.ne b858 - b850: 88037e61 stxr w3, w1, [x19] - b854: 35ffff83 cbnz w3, b844 - b858: 54000340 b.eq b8c0 - b85c: b9005fa2 str w2, [x29,#92] - b860: aa0003e4 mov x4, x0 - b864: b9401e61 ldr w1, [x19,#28] - b868: aa1303e0 mov x0, x19 - b86c: f90027a4 str x4, [x29,#72] - b870: 94000fd5 bl f7c4 <__lll_lock_wait> - b874: b9401260 ldr w0, [x19,#16] - b878: f94027a4 ldr x4, [x29,#72] - b87c: 51000400 sub w0, w0, #0x1 - b880: b9001260 str w0, [x19,#16] - b884: b101b89f cmn x4, #0x6e - b888: 54fff6e1 b.ne b764 - b88c: 52800dc4 mov w4, #0x6e // #110 - b890: 52800001 mov w1, #0x0 // #0 - b894: 885f7e60 ldxr w0, [x19] - b898: 8802fe61 stlxr w2, w1, [x19] - b89c: 35ffffc2 cbnz w2, b894 - b8a0: 7100041f cmp w0, #0x1 - b8a4: 540003ac b.gt b918 - b8a8: 2a0403e0 mov w0, w4 - b8ac: a94153f3 ldp x19, x20, [sp,#16] - b8b0: a9425bf5 ldp x21, x22, [sp,#32] - b8b4: a94363f7 ldp x23, x24, [sp,#48] - b8b8: a8c67bfd ldp x29, x30, [sp],#96 - b8bc: d65f03c0 ret - b8c0: aa0003e4 mov x4, x0 - b8c4: b9401260 ldr w0, [x19,#16] - b8c8: b101b89f cmn x4, #0x6e - b8cc: 51000400 sub w0, w0, #0x1 - b8d0: b9001260 str w0, [x19,#16] - b8d4: 54fff481 b.ne b764 - b8d8: 17ffffed b b88c - b8dc: b9005fa2 str w2, [x29,#92] - b8e0: 17ffffe1 b b864 - b8e4: 52800464 mov w4, #0x23 // #35 - b8e8: 17ffffea b b890 - b8ec: 528002c4 mov w4, #0x16 // #22 - b8f0: 17ffffe8 b b890 - b8f4: b9401e61 ldr w1, [x19,#28] - b8f8: aa1303e0 mov x0, x19 - b8fc: d2800022 mov x2, #0x1 // #1 - b900: d2800003 mov x3, #0x0 // #0 - b904: 4a180021 eor w1, w1, w24 - b908: d2800c48 mov x8, #0x62 // #98 - b90c: 93407c21 sxtw x1, w1 - b910: d4000001 svc #0x0 - b914: 17ffffae b b7cc - b918: b9401e63 ldr w3, [x19,#28] - b91c: 52801021 mov w1, #0x81 // #129 - b920: aa1303e0 mov x0, x19 - b924: d2800022 mov x2, #0x1 // #1 - b928: 4a010061 eor w1, w3, w1 - b92c: d2800c48 mov x8, #0x62 // #98 - b930: d2800003 mov x3, #0x0 // #0 - b934: 93407c21 sxtw x1, w1 - b938: d4000001 svc #0x0 - b93c: 2a0403e0 mov w0, w4 - b940: a94153f3 ldp x19, x20, [sp,#16] - b944: a9425bf5 ldp x21, x22, [sp,#32] - b948: a94363f7 ldp x23, x24, [sp,#48] - b94c: a8c67bfd ldp x29, x30, [sp],#96 - b950: d65f03c0 ret - b954: b9400660 ldr w0, [x19,#4] - b958: 52800164 mov w4, #0xb // #11 - b95c: 31000400 adds w0, w0, #0x1 - b960: 54fff980 b.eq b890 - b964: b9000660 str w0, [x19,#4] - b968: 52800004 mov w4, #0x0 // #0 - b96c: 17ffffc9 b b890 - b970: b9001261 str w1, [x19,#16] - b974: 52800164 mov w4, #0xb // #11 - b978: 17ffffc6 b b890 - -000000000000b97c <__pthread_rwlock_wrlock_slow>: - b97c: a9bb7bfd stp x29, x30, [sp,#-80]! - b980: 910003fd mov x29, sp - b984: a90153f3 stp x19, x20, [sp,#16] - b988: a9025bf5 stp x21, x22, [sp,#32] - b98c: f9001bf7 str x23, [sp,#48] - b990: d53bd054 mrs x20, tpidr_el0 - b994: aa0003f3 mov x19, x0 - b998: d11bc294 sub x20, x20, #0x6f0 - b99c: b9401801 ldr w1, [x0,#24] - b9a0: 52800016 mov w22, #0x0 // #0 - b9a4: 52801037 mov w23, #0x81 // #129 - b9a8: 52800035 mov w21, #0x1 // #1 - b9ac: b940d280 ldr w0, [x20,#208] - b9b0: 6b01001f cmp w0, w1 - b9b4: 54000680 b.eq ba84 <__pthread_rwlock_wrlock_slow+0x108> - b9b8: b9401661 ldr w1, [x19,#20] - b9bc: 11000420 add w0, w1, #0x1 - b9c0: b9001660 str w0, [x19,#20] - b9c4: 34000760 cbz w0, bab0 <__pthread_rwlock_wrlock_slow+0x134> - b9c8: b9400e64 ldr w4, [x19,#12] - b9cc: 885f7e60 ldxr w0, [x19] - b9d0: 8801fe76 stlxr w1, w22, [x19] - b9d4: 35ffffc1 cbnz w1, b9cc <__pthread_rwlock_wrlock_slow+0x50> - b9d8: 7100041f cmp w0, #0x1 - b9dc: 5400058c b.gt ba8c <__pthread_rwlock_wrlock_slow+0x110> - b9e0: b9401e61 ldr w1, [x19,#28] - b9e4: 93407c82 sxtw x2, w4 - b9e8: 91003260 add x0, x19, #0xc - b9ec: d2800003 mov x3, #0x0 // #0 - b9f0: 52190021 eor w1, w1, #0x80 - b9f4: d2800c48 mov x8, #0x62 // #98 - b9f8: 93407c21 sxtw x1, w1 - b9fc: d4000001 svc #0x0 - ba00: b9004fa3 str w3, [x29,#76] - ba04: 885ffe62 ldaxr w2, [x19] - ba08: 6b1f005f cmp w2, wzr - ba0c: 54000061 b.ne ba18 <__pthread_rwlock_wrlock_slow+0x9c> - ba10: 88007e75 stxr w0, w21, [x19] - ba14: 35ffff80 cbnz w0, ba04 <__pthread_rwlock_wrlock_slow+0x88> - ba18: aa1303e0 mov x0, x19 - ba1c: 54000080 b.eq ba2c <__pthread_rwlock_wrlock_slow+0xb0> - ba20: b9401e61 ldr w1, [x19,#28] - ba24: b9004fa2 str w2, [x29,#76] - ba28: 94000f67 bl f7c4 <__lll_lock_wait> - ba2c: b9401660 ldr w0, [x19,#20] - ba30: b9401a61 ldr w1, [x19,#24] - ba34: 51000400 sub w0, w0, #0x1 - ba38: b9001660 str w0, [x19,#20] - ba3c: 35fffb81 cbnz w1, b9ac <__pthread_rwlock_wrlock_slow+0x30> - ba40: b9400660 ldr w0, [x19,#4] - ba44: 35fffb40 cbnz w0, b9ac <__pthread_rwlock_wrlock_slow+0x30> - ba48: b940d281 ldr w1, [x20,#208] - ba4c: 2a0003e4 mov w4, w0 - ba50: b9001a61 str w1, [x19,#24] - ba54: 52800001 mov w1, #0x0 // #0 - ba58: 885f7e60 ldxr w0, [x19] - ba5c: 8802fe61 stlxr w2, w1, [x19] - ba60: 35ffffc2 cbnz w2, ba58 <__pthread_rwlock_wrlock_slow+0xdc> - ba64: 7100041f cmp w0, #0x1 - ba68: 540002ac b.gt babc <__pthread_rwlock_wrlock_slow+0x140> - ba6c: 2a0403e0 mov w0, w4 - ba70: f9401bf7 ldr x23, [sp,#48] - ba74: a94153f3 ldp x19, x20, [sp,#16] - ba78: a9425bf5 ldp x21, x22, [sp,#32] - ba7c: a8c57bfd ldp x29, x30, [sp],#80 - ba80: d65f03c0 ret - ba84: 52800464 mov w4, #0x23 // #35 - ba88: 17fffff3 b ba54 <__pthread_rwlock_wrlock_slow+0xd8> - ba8c: b9401e61 ldr w1, [x19,#28] - ba90: aa1303e0 mov x0, x19 - ba94: d2800022 mov x2, #0x1 // #1 - ba98: d2800003 mov x3, #0x0 // #0 - ba9c: 4a170021 eor w1, w1, w23 - baa0: d2800c48 mov x8, #0x62 // #98 - baa4: 93407c21 sxtw x1, w1 - baa8: d4000001 svc #0x0 - baac: 17ffffcd b b9e0 <__pthread_rwlock_wrlock_slow+0x64> - bab0: b9001661 str w1, [x19,#20] - bab4: 52800164 mov w4, #0xb // #11 - bab8: 17ffffe7 b ba54 <__pthread_rwlock_wrlock_slow+0xd8> - babc: b9401e63 ldr w3, [x19,#28] - bac0: 52801021 mov w1, #0x81 // #129 - bac4: aa1303e0 mov x0, x19 - bac8: d2800022 mov x2, #0x1 // #1 - bacc: 4a010061 eor w1, w3, w1 - bad0: d2800c48 mov x8, #0x62 // #98 - bad4: d2800003 mov x3, #0x0 // #0 - bad8: 93407c21 sxtw x1, w1 - badc: d4000001 svc #0x0 - bae0: 2a0403e0 mov w0, w4 - bae4: f9401bf7 ldr x23, [sp,#48] - bae8: a94153f3 ldp x19, x20, [sp,#16] - baec: a9425bf5 ldp x21, x22, [sp,#32] - baf0: a8c57bfd ldp x29, x30, [sp],#80 - baf4: d65f03c0 ret - -000000000000baf8 <__pthread_rwlock_wrlock>: - baf8: a9bd7bfd stp x29, x30, [sp,#-48]! - bafc: 52800021 mov w1, #0x1 // #1 - bb00: 910003fd mov x29, sp - bb04: f9000bf3 str x19, [sp,#16] - bb08: aa0003f3 mov x19, x0 - bb0c: b9002fbf str wzr, [x29,#44] - bb10: 885ffe62 ldaxr w2, [x19] - bb14: 6b1f005f cmp w2, wzr - bb18: 54000061 b.ne bb24 <__pthread_rwlock_wrlock+0x2c> - bb1c: 88037e61 stxr w3, w1, [x19] - bb20: 35ffff83 cbnz w3, bb10 <__pthread_rwlock_wrlock+0x18> - bb24: 54000261 b.ne bb70 <__pthread_rwlock_wrlock+0x78> - bb28: b9401a61 ldr w1, [x19,#24] - bb2c: b9400660 ldr w0, [x19,#4] - bb30: 2a000020 orr w0, w1, w0 - bb34: 350002c0 cbnz w0, bb8c <__pthread_rwlock_wrlock+0x94> - bb38: d53bd041 mrs x1, tpidr_el0 - bb3c: d11bc021 sub x1, x1, #0x6f0 - bb40: b940d021 ldr w1, [x1,#208] - bb44: b9001a61 str w1, [x19,#24] - bb48: 885f7e61 ldxr w1, [x19] - bb4c: 8802fe60 stlxr w2, w0, [x19] - bb50: 35ffffc2 cbnz w2, bb48 <__pthread_rwlock_wrlock+0x50> - bb54: 7100043f cmp w1, #0x1 - bb58: 2a0003e4 mov w4, w0 - bb5c: 5400026c b.gt bba8 <__pthread_rwlock_wrlock+0xb0> - bb60: 2a0403e0 mov w0, w4 - bb64: f9400bf3 ldr x19, [sp,#16] - bb68: a8c37bfd ldp x29, x30, [sp],#48 - bb6c: d65f03c0 ret - bb70: b9401e61 ldr w1, [x19,#28] - bb74: b9002fa2 str w2, [x29,#44] - bb78: 94000f13 bl f7c4 <__lll_lock_wait> - bb7c: b9401a61 ldr w1, [x19,#24] - bb80: b9400660 ldr w0, [x19,#4] - bb84: 2a000020 orr w0, w1, w0 - bb88: 34fffd80 cbz w0, bb38 <__pthread_rwlock_wrlock+0x40> - bb8c: aa1303e0 mov x0, x19 - bb90: 97ffff7b bl b97c <__pthread_rwlock_wrlock_slow> - bb94: 2a0003e4 mov w4, w0 - bb98: 2a0403e0 mov w0, w4 - bb9c: f9400bf3 ldr x19, [sp,#16] - bba0: a8c37bfd ldp x29, x30, [sp],#48 - bba4: d65f03c0 ret - bba8: b9401e63 ldr w3, [x19,#28] - bbac: 52801021 mov w1, #0x81 // #129 - bbb0: aa1303e0 mov x0, x19 - bbb4: d2800022 mov x2, #0x1 // #1 - bbb8: 4a010061 eor w1, w3, w1 - bbbc: d2800c48 mov x8, #0x62 // #98 - bbc0: d2800003 mov x3, #0x0 // #0 - bbc4: 93407c21 sxtw x1, w1 - bbc8: d4000001 svc #0x0 - bbcc: 17ffffe5 b bb60 <__pthread_rwlock_wrlock+0x68> - -000000000000bbd0 : - bbd0: a9b97bfd stp x29, x30, [sp,#-112]! - bbd4: 910003fd mov x29, sp - bbd8: a90153f3 stp x19, x20, [sp,#16] - bbdc: a9025bf5 stp x21, x22, [sp,#32] - bbe0: aa0103f4 mov x20, x1 - bbe4: f90023f9 str x25, [sp,#64] - bbe8: a90363f7 stp x23, x24, [sp,#48] - bbec: b9006fbf str wzr, [x29,#108] - bbf0: aa0003f3 mov x19, x0 - bbf4: 52800021 mov w1, #0x1 // #1 - bbf8: 885ffe62 ldaxr w2, [x19] - bbfc: 6b1f005f cmp w2, wzr - bc00: 54000061 b.ne bc0c - bc04: 88037e61 stxr w3, w1, [x19] - bc08: 35ffff83 cbnz w3, bbf8 - bc0c: 540006e1 b.ne bce8 - bc10: d53bd055 mrs x21, tpidr_el0 - bc14: 52800018 mov w24, #0x0 // #0 - bc18: d11bc2b5 sub x21, x21, #0x6f0 - bc1c: 52801039 mov w25, #0x81 // #129 - bc20: 52803137 mov w23, #0x189 // #393 - bc24: 52800036 mov w22, #0x1 // #1 - bc28: b9401a62 ldr w2, [x19,#24] - bc2c: 35000062 cbnz w2, bc38 - bc30: b9400660 ldr w0, [x19,#4] - bc34: 34000f40 cbz w0, be1c - bc38: b940d2a0 ldr w0, [x21,#208] - bc3c: 6b00005f cmp w2, w0 - bc40: 54000ae0 b.eq bd9c - bc44: f9400681 ldr x1, [x20,#8] - bc48: d2993fe0 mov x0, #0xc9ff // #51711 - bc4c: f2a77340 movk x0, #0x3b9a, lsl #16 - bc50: eb00003f cmp x1, x0 - bc54: 54000a88 b.hi bda4 - bc58: f9400280 ldr x0, [x20] - bc5c: b7f80720 tbnz x0, #63, bd40 - bc60: b9401661 ldr w1, [x19,#20] - bc64: 11000420 add w0, w1, #0x1 - bc68: b9001660 str w0, [x19,#20] - bc6c: 34000d20 cbz w0, be10 - bc70: b9400e65 ldr w5, [x19,#12] - bc74: 885f7e60 ldxr w0, [x19] - bc78: 8801fe78 stlxr w1, w24, [x19] - bc7c: 35ffffc1 cbnz w1, bc74 - bc80: 7100041f cmp w0, #0x1 - bc84: 5400094c b.gt bdac - bc88: b9401e64 ldr w4, [x19,#28] - bc8c: 93407ca2 sxtw x2, w5 - bc90: 91003260 add x0, x19, #0xc - bc94: aa1403e3 mov x3, x20 - bc98: 4a170081 eor w1, w4, w23 - bc9c: b2407fe5 mov x5, #0xffffffff // #4294967295 - bca0: d2800004 mov x4, #0x0 // #0 - bca4: d2800c48 mov x8, #0x62 // #98 - bca8: 93407c21 sxtw x1, w1 - bcac: d4000001 svc #0x0 - bcb0: b9006fa4 str w4, [x29,#108] - bcb4: b140041f cmn x0, #0x1, lsl #12 - bcb8: 54000208 b.hi bcf8 - bcbc: 2a0403e0 mov w0, w4 - bcc0: 885ffe61 ldaxr w1, [x19] - bcc4: 6b00003f cmp w1, w0 - bcc8: 54000061 b.ne bcd4 - bccc: 88027e76 stxr w2, w22, [x19] - bcd0: 35ffff82 cbnz w2, bcc0 - bcd4: 54000601 b.ne bd94 - bcd8: b9401660 ldr w0, [x19,#20] - bcdc: 51000400 sub w0, w0, #0x1 - bce0: b9001660 str w0, [x19,#20] - bce4: 17ffffd1 b bc28 - bce8: b9401e61 ldr w1, [x19,#28] - bcec: b9006fa2 str w2, [x29,#108] - bcf0: 94000eb5 bl f7c4 <__lll_lock_wait> - bcf4: 17ffffc7 b bc10 - bcf8: 885ffe61 ldaxr w1, [x19] - bcfc: 6b1f003f cmp w1, wzr - bd00: 54000061 b.ne bd0c - bd04: 88027e76 stxr w2, w22, [x19] - bd08: 35ffff82 cbnz w2, bcf8 - bd0c: 54000360 b.eq bd78 - bd10: b9006fa1 str w1, [x29,#108] - bd14: aa0003e4 mov x4, x0 - bd18: b9401e61 ldr w1, [x19,#28] - bd1c: aa1303e0 mov x0, x19 - bd20: f9002fa4 str x4, [x29,#88] - bd24: 94000ea8 bl f7c4 <__lll_lock_wait> - bd28: b9401660 ldr w0, [x19,#20] - bd2c: f9402fa4 ldr x4, [x29,#88] - bd30: 51000400 sub w0, w0, #0x1 - bd34: b9001660 str w0, [x19,#20] - bd38: b101b89f cmn x4, #0x6e - bd3c: 54fff761 b.ne bc28 - bd40: 52800dc4 mov w4, #0x6e // #110 - bd44: 52800001 mov w1, #0x0 // #0 - bd48: 885f7e60 ldxr w0, [x19] - bd4c: 8802fe61 stlxr w2, w1, [x19] - bd50: 35ffffc2 cbnz w2, bd48 - bd54: 7100041f cmp w0, #0x1 - bd58: 540003cc b.gt bdd0 - bd5c: 2a0403e0 mov w0, w4 - bd60: f94023f9 ldr x25, [sp,#64] - bd64: a94153f3 ldp x19, x20, [sp,#16] - bd68: a9425bf5 ldp x21, x22, [sp,#32] - bd6c: a94363f7 ldp x23, x24, [sp,#48] - bd70: a8c77bfd ldp x29, x30, [sp],#112 - bd74: d65f03c0 ret - bd78: aa0003e4 mov x4, x0 - bd7c: b9401660 ldr w0, [x19,#20] - bd80: b101b89f cmn x4, #0x6e - bd84: 51000400 sub w0, w0, #0x1 - bd88: b9001660 str w0, [x19,#20] - bd8c: 54fff4e1 b.ne bc28 - bd90: 17ffffec b bd40 - bd94: b9006fa1 str w1, [x29,#108] - bd98: 17ffffe0 b bd18 - bd9c: 52800464 mov w4, #0x23 // #35 - bda0: 17ffffe9 b bd44 - bda4: 528002c4 mov w4, #0x16 // #22 - bda8: 17ffffe7 b bd44 - bdac: b9401e61 ldr w1, [x19,#28] - bdb0: aa1303e0 mov x0, x19 - bdb4: d2800022 mov x2, #0x1 // #1 - bdb8: d2800003 mov x3, #0x0 // #0 - bdbc: 4a190021 eor w1, w1, w25 - bdc0: d2800c48 mov x8, #0x62 // #98 - bdc4: 93407c21 sxtw x1, w1 - bdc8: d4000001 svc #0x0 - bdcc: 17ffffaf b bc88 - bdd0: b9401e63 ldr w3, [x19,#28] - bdd4: 52801021 mov w1, #0x81 // #129 - bdd8: aa1303e0 mov x0, x19 - bddc: d2800022 mov x2, #0x1 // #1 - bde0: 4a010061 eor w1, w3, w1 - bde4: d2800c48 mov x8, #0x62 // #98 - bde8: d2800003 mov x3, #0x0 // #0 - bdec: 93407c21 sxtw x1, w1 - bdf0: d4000001 svc #0x0 - bdf4: 2a0403e0 mov w0, w4 - bdf8: f94023f9 ldr x25, [sp,#64] - bdfc: a94153f3 ldp x19, x20, [sp,#16] - be00: a9425bf5 ldp x21, x22, [sp,#32] - be04: a94363f7 ldp x23, x24, [sp,#48] - be08: a8c77bfd ldp x29, x30, [sp],#112 - be0c: d65f03c0 ret - be10: b9001661 str w1, [x19,#20] - be14: 52800164 mov w4, #0xb // #11 - be18: 17ffffcb b bd44 - be1c: b940d2a1 ldr w1, [x21,#208] - be20: 2a0003e4 mov w4, w0 - be24: b9001a61 str w1, [x19,#24] - be28: 17ffffc7 b bd44 - -000000000000be2c <__pthread_rwlock_tryrdlock>: - be2c: a9bd7bfd stp x29, x30, [sp,#-48]! - be30: 52800021 mov w1, #0x1 // #1 - be34: 910003fd mov x29, sp - be38: f9000bf3 str x19, [sp,#16] - be3c: aa0003f3 mov x19, x0 - be40: b9002fbf str wzr, [x29,#44] - be44: 885ffe62 ldaxr w2, [x19] - be48: 6b1f005f cmp w2, wzr - be4c: 54000061 b.ne be58 <__pthread_rwlock_tryrdlock+0x2c> - be50: 88037e61 stxr w3, w1, [x19] - be54: 35ffff83 cbnz w3, be44 <__pthread_rwlock_tryrdlock+0x18> - be58: 540001c1 b.ne be90 <__pthread_rwlock_tryrdlock+0x64> - be5c: b9401a60 ldr w0, [x19,#24] - be60: 52800204 mov w4, #0x10 // #16 - be64: 34000220 cbz w0, bea8 <__pthread_rwlock_tryrdlock+0x7c> - be68: 52800001 mov w1, #0x0 // #0 - be6c: 885f7e60 ldxr w0, [x19] - be70: 8802fe61 stlxr w2, w1, [x19] - be74: 35ffffc2 cbnz w2, be6c <__pthread_rwlock_tryrdlock+0x40> - be78: 7100041f cmp w0, #0x1 - be7c: 5400030c b.gt bedc <__pthread_rwlock_tryrdlock+0xb0> - be80: 2a0403e0 mov w0, w4 - be84: f9400bf3 ldr x19, [sp,#16] - be88: a8c37bfd ldp x29, x30, [sp],#48 - be8c: d65f03c0 ret - be90: b9401e61 ldr w1, [x19,#28] - be94: b9002fa2 str w2, [x29,#44] - be98: 94000e4b bl f7c4 <__lll_lock_wait> - be9c: b9401a60 ldr w0, [x19,#24] - bea0: 52800204 mov w4, #0x10 // #16 - bea4: 35fffe20 cbnz w0, be68 <__pthread_rwlock_tryrdlock+0x3c> - bea8: b9401660 ldr w0, [x19,#20] - beac: 35000120 cbnz w0, bed0 <__pthread_rwlock_tryrdlock+0xa4> - beb0: b9400661 ldr w1, [x19,#4] - beb4: 52800004 mov w4, #0x0 // #0 - beb8: 11000420 add w0, w1, #0x1 - bebc: b9000660 str w0, [x19,#4] - bec0: 35fffd40 cbnz w0, be68 <__pthread_rwlock_tryrdlock+0x3c> - bec4: b9000661 str w1, [x19,#4] - bec8: 52800164 mov w4, #0xb // #11 - becc: 17ffffe7 b be68 <__pthread_rwlock_tryrdlock+0x3c> - bed0: b9403260 ldr w0, [x19,#48] - bed4: 35fffca0 cbnz w0, be68 <__pthread_rwlock_tryrdlock+0x3c> - bed8: 17fffff6 b beb0 <__pthread_rwlock_tryrdlock+0x84> - bedc: b9401e63 ldr w3, [x19,#28] - bee0: 52801021 mov w1, #0x81 // #129 - bee4: aa1303e0 mov x0, x19 - bee8: d2800022 mov x2, #0x1 // #1 - beec: 4a010061 eor w1, w3, w1 - bef0: d2800c48 mov x8, #0x62 // #98 - bef4: d2800003 mov x3, #0x0 // #0 - bef8: 93407c21 sxtw x1, w1 - befc: d4000001 svc #0x0 - bf00: 2a0403e0 mov w0, w4 - bf04: f9400bf3 ldr x19, [sp,#16] - bf08: a8c37bfd ldp x29, x30, [sp],#48 - bf0c: d65f03c0 ret - -000000000000bf10 <__pthread_rwlock_trywrlock>: - bf10: a9bd7bfd stp x29, x30, [sp,#-48]! - bf14: 52800021 mov w1, #0x1 // #1 - bf18: 910003fd mov x29, sp - bf1c: f9000bf3 str x19, [sp,#16] - bf20: aa0003f3 mov x19, x0 - bf24: b9002fbf str wzr, [x29,#44] - bf28: 885ffe62 ldaxr w2, [x19] - bf2c: 6b1f005f cmp w2, wzr - bf30: 54000061 b.ne bf3c <__pthread_rwlock_trywrlock+0x2c> - bf34: 88037e61 stxr w3, w1, [x19] - bf38: 35ffff83 cbnz w3, bf28 <__pthread_rwlock_trywrlock+0x18> - bf3c: 540001c1 b.ne bf74 <__pthread_rwlock_trywrlock+0x64> - bf40: b9401a60 ldr w0, [x19,#24] - bf44: 52800204 mov w4, #0x10 // #16 - bf48: 34000220 cbz w0, bf8c <__pthread_rwlock_trywrlock+0x7c> - bf4c: 52800001 mov w1, #0x0 // #0 - bf50: 885f7e60 ldxr w0, [x19] - bf54: 8802fe61 stlxr w2, w1, [x19] - bf58: 35ffffc2 cbnz w2, bf50 <__pthread_rwlock_trywrlock+0x40> - bf5c: 7100041f cmp w0, #0x1 - bf60: 5400026c b.gt bfac <__pthread_rwlock_trywrlock+0x9c> - bf64: 2a0403e0 mov w0, w4 - bf68: f9400bf3 ldr x19, [sp,#16] - bf6c: a8c37bfd ldp x29, x30, [sp],#48 - bf70: d65f03c0 ret - bf74: b9401e61 ldr w1, [x19,#28] - bf78: b9002fa2 str w2, [x29,#44] - bf7c: 94000e12 bl f7c4 <__lll_lock_wait> - bf80: b9401a60 ldr w0, [x19,#24] - bf84: 52800204 mov w4, #0x10 // #16 - bf88: 35fffe20 cbnz w0, bf4c <__pthread_rwlock_trywrlock+0x3c> - bf8c: b9400660 ldr w0, [x19,#4] - bf90: 35fffde0 cbnz w0, bf4c <__pthread_rwlock_trywrlock+0x3c> - bf94: 2a0003e4 mov w4, w0 - bf98: d53bd040 mrs x0, tpidr_el0 - bf9c: d11bc000 sub x0, x0, #0x6f0 - bfa0: b940d000 ldr w0, [x0,#208] - bfa4: b9001a60 str w0, [x19,#24] - bfa8: 17ffffe9 b bf4c <__pthread_rwlock_trywrlock+0x3c> - bfac: b9401e63 ldr w3, [x19,#28] - bfb0: 52801021 mov w1, #0x81 // #129 - bfb4: aa1303e0 mov x0, x19 - bfb8: d2800022 mov x2, #0x1 // #1 - bfbc: 4a010061 eor w1, w3, w1 - bfc0: d2800c48 mov x8, #0x62 // #98 - bfc4: d2800003 mov x3, #0x0 // #0 - bfc8: 93407c21 sxtw x1, w1 - bfcc: d4000001 svc #0x0 - bfd0: 2a0403e0 mov w0, w4 - bfd4: f9400bf3 ldr x19, [sp,#16] - bfd8: a8c37bfd ldp x29, x30, [sp],#48 - bfdc: d65f03c0 ret - -000000000000bfe0 <__pthread_rwlock_unlock>: - bfe0: a9bd7bfd stp x29, x30, [sp,#-48]! - bfe4: 52800021 mov w1, #0x1 // #1 - bfe8: 910003fd mov x29, sp - bfec: f9000bf3 str x19, [sp,#16] - bff0: aa0003f3 mov x19, x0 - bff4: b9002fbf str wzr, [x29,#44] - bff8: 885ffe62 ldaxr w2, [x19] - bffc: 6b1f005f cmp w2, wzr - c000: 54000061 b.ne c00c <__pthread_rwlock_unlock+0x2c> - c004: 88037e61 stxr w3, w1, [x19] - c008: 35ffff83 cbnz w3, bff8 <__pthread_rwlock_unlock+0x18> - c00c: 54000281 b.ne c05c <__pthread_rwlock_unlock+0x7c> - c010: b9401a60 ldr w0, [x19,#24] - c014: 340002e0 cbz w0, c070 <__pthread_rwlock_unlock+0x90> - c018: b9400660 ldr w0, [x19,#4] - c01c: b9001a7f str wzr, [x19,#24] - c020: 350000a0 cbnz w0, c034 <__pthread_rwlock_unlock+0x54> - c024: b9401661 ldr w1, [x19,#20] - c028: 350002c1 cbnz w1, c080 <__pthread_rwlock_unlock+0xa0> - c02c: b9401261 ldr w1, [x19,#16] - c030: 35000521 cbnz w1, c0d4 <__pthread_rwlock_unlock+0xf4> - c034: 52800001 mov w1, #0x0 // #0 - c038: 885f7e60 ldxr w0, [x19] - c03c: 8802fe61 stlxr w2, w1, [x19] - c040: 35ffffc2 cbnz w2, c038 <__pthread_rwlock_unlock+0x58> - c044: 7100041f cmp w0, #0x1 - c048: 540005ec b.gt c104 <__pthread_rwlock_unlock+0x124> - c04c: 52800000 mov w0, #0x0 // #0 - c050: f9400bf3 ldr x19, [sp,#16] - c054: a8c37bfd ldp x29, x30, [sp],#48 - c058: d65f03c0 ret - c05c: b9401e61 ldr w1, [x19,#28] - c060: b9002fa2 str w2, [x29,#44] - c064: 94000dd8 bl f7c4 <__lll_lock_wait> - c068: b9401a60 ldr w0, [x19,#24] - c06c: 35fffd60 cbnz w0, c018 <__pthread_rwlock_unlock+0x38> - c070: b9400660 ldr w0, [x19,#4] - c074: 51000400 sub w0, w0, #0x1 - c078: b9000660 str w0, [x19,#4] - c07c: 17ffffe9 b c020 <__pthread_rwlock_unlock+0x40> - c080: b9400e61 ldr w1, [x19,#12] - c084: 11000421 add w1, w1, #0x1 - c088: b9000e61 str w1, [x19,#12] - c08c: 885f7e61 ldxr w1, [x19] - c090: 8802fe60 stlxr w2, w0, [x19] - c094: 35ffffc2 cbnz w2, c08c <__pthread_rwlock_unlock+0xac> - c098: 7100043f cmp w1, #0x1 - c09c: 540003ac b.gt c110 <__pthread_rwlock_unlock+0x130> - c0a0: b9401e63 ldr w3, [x19,#28] - c0a4: 91003260 add x0, x19, #0xc - c0a8: d2800022 mov x2, #0x1 // #1 - c0ac: 52801021 mov w1, #0x81 // #129 - c0b0: d2800c48 mov x8, #0x62 // #98 - c0b4: 4a010061 eor w1, w3, w1 - c0b8: d2800003 mov x3, #0x0 // #0 - c0bc: 93407c21 sxtw x1, w1 - c0c0: d4000001 svc #0x0 - c0c4: 52800000 mov w0, #0x0 // #0 - c0c8: f9400bf3 ldr x19, [sp,#16] - c0cc: a8c37bfd ldp x29, x30, [sp],#48 - c0d0: d65f03c0 ret - c0d4: b9400a61 ldr w1, [x19,#8] - c0d8: 11000421 add w1, w1, #0x1 - c0dc: b9000a61 str w1, [x19,#8] - c0e0: 885f7e61 ldxr w1, [x19] - c0e4: 8802fe60 stlxr w2, w0, [x19] - c0e8: 35ffffc2 cbnz w2, c0e0 <__pthread_rwlock_unlock+0x100> - c0ec: 7100043f cmp w1, #0x1 - c0f0: 5400024c b.gt c138 <__pthread_rwlock_unlock+0x158> - c0f4: b9401e63 ldr w3, [x19,#28] - c0f8: 91002260 add x0, x19, #0x8 - c0fc: b2407be2 mov x2, #0x7fffffff // #2147483647 - c100: 17ffffeb b c0ac <__pthread_rwlock_unlock+0xcc> - c104: b9401e63 ldr w3, [x19,#28] - c108: aa1303e0 mov x0, x19 - c10c: 17ffffe7 b c0a8 <__pthread_rwlock_unlock+0xc8> - c110: b9401e63 ldr w3, [x19,#28] - c114: 52801021 mov w1, #0x81 // #129 - c118: aa1303e0 mov x0, x19 - c11c: d2800022 mov x2, #0x1 // #1 - c120: 4a010061 eor w1, w3, w1 - c124: d2800c48 mov x8, #0x62 // #98 - c128: d2800003 mov x3, #0x0 // #0 - c12c: 93407c21 sxtw x1, w1 - c130: d4000001 svc #0x0 - c134: 17ffffdb b c0a0 <__pthread_rwlock_unlock+0xc0> - c138: b9401e63 ldr w3, [x19,#28] - c13c: 52801021 mov w1, #0x81 // #129 - c140: aa1303e0 mov x0, x19 - c144: d2800022 mov x2, #0x1 // #1 - c148: 4a010061 eor w1, w3, w1 - c14c: d2800c48 mov x8, #0x62 // #98 - c150: d2800003 mov x3, #0x0 // #0 - c154: 93407c21 sxtw x1, w1 - c158: d4000001 svc #0x0 - c15c: 17ffffe6 b c0f4 <__pthread_rwlock_unlock+0x114> - -000000000000c160 : - c160: aa0003e1 mov x1, x0 - c164: 52800000 mov w0, #0x0 // #0 - c168: b9000020 str w0, [x1] - c16c: b9000420 str w0, [x1,#4] - c170: d65f03c0 ret - -000000000000c174 : - c174: 52800000 mov w0, #0x0 // #0 - c178: d65f03c0 ret - -000000000000c17c : - c17c: b9400402 ldr w2, [x0,#4] - c180: 52800000 mov w0, #0x0 // #0 - c184: b9000022 str w2, [x1] - c188: d65f03c0 ret - -000000000000c18c : - c18c: 7100043f cmp w1, #0x1 - c190: 54000088 b.hi c1a0 - c194: b9000401 str w1, [x0,#4] - c198: 52800000 mov w0, #0x0 // #0 - c19c: d65f03c0 ret - c1a0: 528002c0 mov w0, #0x16 // #22 - c1a4: d65f03c0 ret - -000000000000c1a8 : - c1a8: b9400002 ldr w2, [x0] - c1ac: 52800000 mov w0, #0x0 // #0 - c1b0: b9000022 str w2, [x1] - c1b4: d65f03c0 ret - -000000000000c1b8 : - c1b8: 7100083f cmp w1, #0x2 - c1bc: 54000088 b.hi c1cc - c1c0: b9000001 str w1, [x0] - c1c4: 52800000 mov w0, #0x0 // #0 - c1c8: d65f03c0 ret - c1cc: 528002c0 mov w0, #0x16 // #22 - c1d0: d65f03c0 ret - -000000000000c1d4 : - c1d4: b900001f str wzr, [x0] - c1d8: b900041f str wzr, [x0,#4] - c1dc: b40001e1 cbz x1, c218 - c1e0: b9400022 ldr w2, [x1] - c1e4: f900041f str xzr, [x0,#8] - c1e8: f900081f str xzr, [x0,#16] - c1ec: d3410442 ubfx x2, x2, #1, #1 - c1f0: f9000c1f str xzr, [x0,#24] - c1f4: b9002802 str w2, [x0,#40] - c1f8: b9400021 ldr w1, [x1] - c1fc: b9002c1f str wzr, [x0,#44] - c200: 12000021 and w1, w1, #0x1 - c204: 6b1f003f cmp w1, wzr - c208: da9f03e2 csetm x2, ne - c20c: f9001002 str x2, [x0,#32] - c210: 52800000 mov w0, #0x0 // #0 - c214: d65f03c0 ret - c218: b9002801 str w1, [x0,#40] - c21c: aa0103e2 mov x2, x1 - c220: f9000401 str x1, [x0,#8] - c224: f9000801 str x1, [x0,#16] - c228: f9000c01 str x1, [x0,#24] - c22c: f9001002 str x2, [x0,#32] - c230: b9002c1f str wzr, [x0,#44] - c234: 52800000 mov w0, #0x0 // #0 - c238: d65f03c0 ret - -000000000000c23c : - c23c: a9ba7bfd stp x29, x30, [sp,#-96]! - c240: 910003fd mov x29, sp - c244: a90153f3 stp x19, x20, [sp,#16] - c248: a9025bf5 stp x21, x22, [sp,#32] - c24c: a90363f7 stp x23, x24, [sp,#48] - c250: a9046bf9 stp x25, x26, [sp,#64] - c254: aa0003f3 mov x19, x0 - c258: b9005fbf str wzr, [x29,#92] - c25c: f9401000 ldr x0, [x0,#32] - c260: b100041f cmn x0, #0x1 - c264: 52800020 mov w0, #0x1 // #1 - c268: 54000d00 b.eq c408 - c26c: 885ffe61 ldaxr w1, [x19] - c270: 6b1f003f cmp w1, wzr - c274: 54000061 b.ne c280 - c278: 88027e60 stxr w2, w0, [x19] - c27c: 35ffff82 cbnz w2, c26c - c280: 1a9f17e0 cset w0, eq - c284: 52800014 mov w20, #0x0 // #0 - c288: 34000700 cbz w0, c368 - c28c: f9400661 ldr x1, [x19,#8] - c290: f9400a60 ldr x0, [x19,#16] - c294: eb00003f cmp x1, x0 - c298: 54000988 b.hi c3c8 - c29c: b9402a64 ldr w4, [x19,#40] - c2a0: 92800000 mov x0, #0xffffffffffffffff // #-1 - c2a4: f9000660 str x0, [x19,#8] - c2a8: 7100049f cmp w4, #0x1 - c2ac: 540006a9 b.ls c380 - c2b0: f9401260 ldr x0, [x19,#32] - c2b4: d1000401 sub x1, x0, #0x1 - c2b8: b1000c3f cmn x1, #0x3 - c2bc: 54000729 b.ls c3a0 - c2c0: 5280103a mov w26, #0x81 // #129 - c2c4: 52190295 eor w21, w20, #0x80 - c2c8: 4a1a029a eor w26, w20, w26 - c2cc: 9100a278 add x24, x19, #0x28 - c2d0: 93407eb5 sxtw x21, w21 - c2d4: 910173b9 add x25, x29, #0x5c - c2d8: 52800017 mov w23, #0x0 // #0 - c2dc: 93407f5a sxtw x26, w26 - c2e0: 52800036 mov w22, #0x1 // #1 - c2e4: 14000015 b c338 - c2e8: 2a0403e2 mov w2, w4 - c2ec: aa1803e0 mov x0, x24 - c2f0: aa1503e1 mov x1, x21 - c2f4: d2800003 mov x3, #0x0 // #0 - c2f8: d2800c48 mov x8, #0x62 // #98 - c2fc: d4000001 svc #0x0 - c300: b9005fa3 str w3, [x29,#92] - c304: 885ffe62 ldaxr w2, [x19] - c308: 6b1f005f cmp w2, wzr - c30c: 54000061 b.ne c318 - c310: 88007e76 stxr w0, w22, [x19] - c314: 35ffff80 cbnz w0, c304 - c318: aa1303e0 mov x0, x19 - c31c: 2a1403e1 mov w1, w20 - c320: 54000060 b.eq c32c - c324: b9000322 str w2, [x25] - c328: 94000d27 bl f7c4 <__lll_lock_wait> - c32c: b9402a64 ldr w4, [x19,#40] - c330: 7100049f cmp w4, #0x1 - c334: 54000269 b.ls c380 - c338: 885f7e62 ldxr w2, [x19] - c33c: 8800fe77 stlxr w0, w23, [x19] - c340: 35ffffc0 cbnz w0, c338 - c344: 7100045f cmp w2, #0x1 - c348: 54fffd0d b.le c2e8 - c34c: aa1303e0 mov x0, x19 - c350: aa1a03e1 mov x1, x26 - c354: d2800022 mov x2, #0x1 // #1 - c358: d2800003 mov x3, #0x0 // #0 - c35c: d2800c48 mov x8, #0x62 // #98 - c360: d4000001 svc #0x0 - c364: 17ffffe1 b c2e8 - c368: b9005fa1 str w1, [x29,#92] - c36c: 2a0003f4 mov w20, w0 - c370: aa1303e0 mov x0, x19 - c374: 2a1403e1 mov w1, w20 - c378: 94000d13 bl f7c4 <__lll_lock_wait> - c37c: 17ffffc4 b c28c - c380: 52800004 mov w4, #0x0 // #0 - c384: 2a0403e0 mov w0, w4 - c388: a94153f3 ldp x19, x20, [sp,#16] - c38c: a9425bf5 ldp x21, x22, [sp,#32] - c390: a94363f7 ldp x23, x24, [sp,#48] - c394: a9446bf9 ldp x25, x26, [sp,#64] - c398: a8c67bfd ldp x29, x30, [sp],#96 - c39c: d65f03c0 ret - c3a0: b9401001 ldr w1, [x0,#16] - c3a4: b2407be2 mov x2, #0x7fffffff // #2147483647 - c3a8: d2800003 mov x3, #0x0 // #0 - c3ac: d2800c48 mov x8, #0x62 // #98 - c3b0: 12190025 and w5, w1, #0x80 - c3b4: 52801021 mov w1, #0x81 // #129 - c3b8: 4a0100a1 eor w1, w5, w1 - c3bc: 93407c21 sxtw x1, w1 - c3c0: d4000001 svc #0x0 - c3c4: 17ffffbf b c2c0 - c3c8: 52800001 mov w1, #0x0 // #0 - c3cc: 885f7e60 ldxr w0, [x19] - c3d0: 8802fe61 stlxr w2, w1, [x19] - c3d4: 35ffffc2 cbnz w2, c3cc - c3d8: 7100041f cmp w0, #0x1 - c3dc: 52800204 mov w4, #0x10 // #16 - c3e0: 54fffd2d b.le c384 - c3e4: 52801021 mov w1, #0x81 // #129 - c3e8: aa1303e0 mov x0, x19 - c3ec: 4a010281 eor w1, w20, w1 - c3f0: d2800022 mov x2, #0x1 // #1 - c3f4: d2800003 mov x3, #0x0 // #0 - c3f8: d2800c48 mov x8, #0x62 // #98 - c3fc: 93407c21 sxtw x1, w1 - c400: d4000001 svc #0x0 - c404: 17ffffe0 b c384 - c408: 885ffe61 ldaxr w1, [x19] - c40c: 6b1f003f cmp w1, wzr - c410: 54000061 b.ne c41c - c414: 88027e60 stxr w2, w0, [x19] - c418: 35ffff82 cbnz w2, c408 - c41c: 54000080 b.eq c42c - c420: b9005fa1 str w1, [x29,#92] - c424: 52801014 mov w20, #0x80 // #128 - c428: 17ffffd2 b c370 - c42c: 52801014 mov w20, #0x80 // #128 - c430: 17ffff97 b c28c - -000000000000c434 <__condvar_cleanup>: - c434: a9bd7bfd stp x29, x30, [sp,#-48]! - c438: 910003fd mov x29, sp - c43c: a90153f3 stp x19, x20, [sp,#16] - c440: aa0003f3 mov x19, x0 - c444: f9400400 ldr x0, [x0,#8] - c448: b9002fbf str wzr, [x29,#44] - c44c: f9401001 ldr x1, [x0,#32] - c450: b100043f cmn x1, #0x1 - c454: 52800021 mov w1, #0x1 // #1 - c458: 54000c40 b.eq c5e0 <__condvar_cleanup+0x1ac> - c45c: 885ffc03 ldaxr w3, [x0] - c460: 6b1f007f cmp w3, wzr - c464: 54000061 b.ne c470 <__condvar_cleanup+0x3c> - c468: 88027c01 stxr w2, w1, [x0] - c46c: 35ffff82 cbnz w2, c45c <__condvar_cleanup+0x28> - c470: 1a9f17e2 cset w2, eq - c474: d2801034 mov x20, #0x81 // #129 - c478: 340004c2 cbz w2, c510 <__condvar_cleanup+0xdc> - c47c: f9400660 ldr x0, [x19,#8] - c480: b9401a62 ldr w2, [x19,#24] - c484: b9402c01 ldr w1, [x0,#44] - c488: 6b01005f cmp w2, w1 - c48c: 540008a0 b.eq c5a0 <__condvar_cleanup+0x16c> - c490: b9402802 ldr w2, [x0,#40] - c494: 51000842 sub w2, w2, #0x2 - c498: b9002802 str w2, [x0,#40] - c49c: f9400660 ldr x0, [x19,#8] - c4a0: f9400401 ldr x1, [x0,#8] - c4a4: b100043f cmn x1, #0x1 - c4a8: 540004e0 b.eq c544 <__condvar_cleanup+0x110> - c4ac: 52800002 mov w2, #0x0 // #0 - c4b0: 885f7c01 ldxr w1, [x0] - c4b4: 8803fc02 stlxr w3, w2, [x0] - c4b8: 35ffffc3 cbnz w3, c4b0 <__condvar_cleanup+0x7c> - c4bc: 7100043f cmp w1, #0x1 - c4c0: 5400060c b.gt c580 <__condvar_cleanup+0x14c> - c4c4: f9400660 ldr x0, [x19,#8] - c4c8: aa1403e1 mov x1, x20 - c4cc: b2407be2 mov x2, #0x7fffffff // #2147483647 - c4d0: d2800003 mov x3, #0x0 // #0 - c4d4: 91001000 add x0, x0, #0x4 - c4d8: d2800c48 mov x8, #0x62 // #98 - c4dc: d4000001 svc #0x0 - c4e0: f9400a60 ldr x0, [x19,#16] - c4e4: d1000401 sub x1, x0, #0x1 - c4e8: b1000c3f cmn x1, #0x3 - c4ec: 540000a8 b.hi c500 <__condvar_cleanup+0xcc> - c4f0: b9401001 ldr w1, [x0,#16] - c4f4: 121c0421 and w1, w1, #0x30 - c4f8: 7100803f cmp w1, #0x20 - c4fc: 54000120 b.eq c520 <__condvar_cleanup+0xec> - c500: 97fffb0b bl b12c <__pthread_mutex_cond_lock> - c504: a94153f3 ldp x19, x20, [sp,#16] - c508: a8c37bfd ldp x29, x30, [sp],#48 - c50c: d65f03c0 ret - c510: 2a0203e1 mov w1, w2 - c514: b9002fa3 str w3, [x29,#44] - c518: 94000cab bl f7c4 <__lll_lock_wait> - c51c: 17ffffd8 b c47c <__condvar_cleanup+0x48> - c520: d53bd042 mrs x2, tpidr_el0 - c524: b9400001 ldr w1, [x0] - c528: d11bc042 sub x2, x2, #0x6f0 - c52c: 12007421 and w1, w1, #0x3fffffff - c530: b940d042 ldr w2, [x2,#208] - c534: 6b02003f cmp w1, w2 - c538: 54fffe41 b.ne c500 <__condvar_cleanup+0xcc> - c53c: 97fffb7e bl b334 <__pthread_mutex_cond_lock_adjust> - c540: 17fffff1 b c504 <__condvar_cleanup+0xd0> - c544: b9402801 ldr w1, [x0,#40] - c548: 7100043f cmp w1, #0x1 - c54c: 54fffb08 b.hi c4ac <__condvar_cleanup+0x78> - c550: 9100a000 add x0, x0, #0x28 - c554: aa1403e1 mov x1, x20 - c558: d2800022 mov x2, #0x1 // #1 - c55c: d2800003 mov x3, #0x0 // #0 - c560: d2800c48 mov x8, #0x62 // #98 - c564: d4000001 svc #0x0 - c568: f9400660 ldr x0, [x19,#8] - c56c: 885f7c01 ldxr w1, [x0] - c570: 8804fc03 stlxr w4, w3, [x0] - c574: 35ffffc4 cbnz w4, c56c <__condvar_cleanup+0x138> - c578: 7100043f cmp w1, #0x1 - c57c: 54fffb2d b.le c4e0 <__condvar_cleanup+0xac> - c580: 2a0203e4 mov w4, w2 - c584: aa1403e1 mov x1, x20 - c588: d2800022 mov x2, #0x1 // #1 - c58c: d2800003 mov x3, #0x0 // #0 - c590: d2800c48 mov x8, #0x62 // #98 - c594: d4000001 svc #0x0 - c598: 35fffa44 cbnz w4, c4e0 <__condvar_cleanup+0xac> - c59c: 17ffffca b c4c4 <__condvar_cleanup+0x90> - c5a0: f9400801 ldr x1, [x0,#16] - c5a4: f9400402 ldr x2, [x0,#8] - c5a8: eb02003f cmp x1, x2 - c5ac: 54000102 b.cs c5cc <__condvar_cleanup+0x198> - c5b0: 91000421 add x1, x1, #0x1 - c5b4: f9000801 str x1, [x0,#16] - c5b8: f9400661 ldr x1, [x19,#8] - c5bc: b9400420 ldr w0, [x1,#4] - c5c0: 11000400 add w0, w0, #0x1 - c5c4: b9000420 str w0, [x1,#4] - c5c8: f9400660 ldr x0, [x19,#8] - c5cc: f9400c01 ldr x1, [x0,#24] - c5d0: 91000421 add x1, x1, #0x1 - c5d4: f9000c01 str x1, [x0,#24] - c5d8: f9400660 ldr x0, [x19,#8] - c5dc: 17ffffad b c490 <__condvar_cleanup+0x5c> - c5e0: 885ffc02 ldaxr w2, [x0] - c5e4: 6b1f005f cmp w2, wzr - c5e8: 54000061 b.ne c5f4 <__condvar_cleanup+0x1c0> - c5ec: 88037c01 stxr w3, w1, [x0] - c5f0: 35ffff83 cbnz w3, c5e0 <__condvar_cleanup+0x1ac> - c5f4: 540000c0 b.eq c60c <__condvar_cleanup+0x1d8> - c5f8: 52801001 mov w1, #0x80 // #128 - c5fc: b9002fa2 str w2, [x29,#44] - c600: d2800034 mov x20, #0x1 // #1 - c604: 94000c70 bl f7c4 <__lll_lock_wait> - c608: 17ffff9d b c47c <__condvar_cleanup+0x48> - c60c: d2800034 mov x20, #0x1 // #1 - c610: 17ffff9b b c47c <__condvar_cleanup+0x48> - -000000000000c614 : - c614: a9b47bfd stp x29, x30, [sp,#-192]! - c618: 910003fd mov x29, sp - c61c: 6d0627e8 stp d8, d9, [sp,#96] - c620: a90153f3 stp x19, x20, [sp,#16] - c624: a90363f7 stp x23, x24, [sp,#48] - c628: a9025bf5 stp x21, x22, [sp,#32] - c62c: a9046bf9 stp x25, x26, [sp,#64] - c630: a90573fb stp x27, x28, [sp,#80] - c634: aa0003f3 mov x19, x0 - c638: b900a3bf str wzr, [x29,#160] - c63c: f9401000 ldr x0, [x0,#32] - c640: aa0103f7 mov x23, x1 - c644: b100041f cmn x0, #0x1 - c648: 52800020 mov w0, #0x1 // #1 - c64c: 54001520 b.eq c8f0 - c650: 885ffe61 ldaxr w1, [x19] - c654: 6b1f003f cmp w1, wzr - c658: 54000061 b.ne c664 - c65c: 88027e60 stxr w2, w0, [x19] - c660: 35ffff82 cbnz w2, c650 - c664: 1a9f17e0 cset w0, eq - c668: 52800018 mov w24, #0x0 // #0 - c66c: 34000f00 cbz w0, c84c - c670: aa1703e0 mov x0, x23 - c674: 52800001 mov w1, #0x0 // #0 - c678: 97fff8a7 bl a914 <__pthread_mutex_unlock_usercnt> - c67c: 35001560 cbnz w0, c928 - c680: f9400662 ldr x2, [x19,#8] - c684: b9400661 ldr w1, [x19,#4] - c688: b9402a60 ldr w0, [x19,#40] - c68c: 91000442 add x2, x2, #0x1 - c690: f9401263 ldr x3, [x19,#32] - c694: 11000421 add w1, w1, #0x1 - c698: 11000800 add w0, w0, #0x2 - c69c: f9000662 str x2, [x19,#8] - c6a0: b9000661 str w1, [x19,#4] - c6a4: b100047f cmn x3, #0x1 - c6a8: b9002a60 str w0, [x19,#40] - c6ac: 54000040 b.eq c6b4 - c6b0: f9001277 str x23, [x19,#32] - c6b4: 910203a0 add x0, x29, #0x80 - c6b8: 910283b4 add x20, x29, #0xa0 - c6bc: 90000001 adrp x1, c000 <__pthread_rwlock_unlock+0x20> - c6c0: aa1403e2 mov x2, x20 - c6c4: 9e670009 fmov d9, x0 - c6c8: 9110d021 add x1, x1, #0x434 - c6cc: f90057b3 str x19, [x29,#168] - c6d0: 5280117c mov w28, #0x8b // #139 - c6d4: f9005bb7 str x23, [x29,#176] - c6d8: 4a1c031c eor w28, w24, w28 - c6dc: d10006f9 sub x25, x23, #0x1 - c6e0: 52800015 mov w21, #0x0 // #0 - c6e4: 94000ac7 bl f200 <_pthread_cleanup_push> - c6e8: f9400a7a ldr x26, [x19,#16] - c6ec: 52801020 mov w0, #0x81 // #129 - c6f0: b9402e61 ldr w1, [x19,#44] - c6f4: 4a000300 eor w0, w24, w0 - c6f8: 9101f3bb add x27, x29, #0x7c - c6fc: b900bba1 str w1, [x29,#184] - c700: 93407f9c sxtw x28, w28 - c704: 93407c00 sxtw x0, w0 - c708: 9e670008 fmov d8, x0 - c70c: b9400676 ldr w22, [x19,#4] - c710: 52800001 mov w1, #0x0 // #0 - c714: 885f7e60 ldxr w0, [x19] - c718: 8802fe61 stlxr w2, w1, [x19] - c71c: 35ffffc2 cbnz w2, c714 - c720: 7100041f cmp w0, #0x1 - c724: 54000c0c b.gt c8a4 - c728: 94000bbc bl f618 <__pthread_enable_asynccancel> - c72c: b9000280 str w0, [x20] - c730: 350009b5 cbnz w21, c864 - c734: b1000f3f cmn x25, #0x3 - c738: 540000a8 b.hi c74c - c73c: b94012e0 ldr w0, [x23,#16] - c740: 121c0400 and w0, w0, #0x30 - c744: 7100801f cmp w0, #0x20 - c748: 540009a0 b.eq c87c - c74c: 52190305 eor w5, w24, #0x80 - c750: 91001260 add x0, x19, #0x4 - c754: 2a1603e2 mov w2, w22 - c758: d2800003 mov x3, #0x0 // #0 - c75c: 93407ca1 sxtw x1, w5 - c760: d2800c48 mov x8, #0x62 // #98 - c764: d4000001 svc #0x0 - c768: 2a0303f5 mov w21, w3 - c76c: b9400280 ldr w0, [x20] - c770: 94000bda bl f6d8 <__pthread_disable_asynccancel> - c774: b9007fbf str wzr, [x29,#124] - c778: 52800022 mov w2, #0x1 // #1 - c77c: 885ffe63 ldaxr w3, [x19] - c780: 6b1f007f cmp w3, wzr - c784: 54000061 b.ne c790 - c788: 88007e62 stxr w0, w2, [x19] - c78c: 35ffff80 cbnz w0, c77c - c790: 540000a0 b.eq c7a4 - c794: aa1303e0 mov x0, x19 - c798: 2a1803e1 mov w1, w24 - c79c: b9000363 str w3, [x27] - c7a0: 94000c09 bl f7c4 <__lll_lock_wait> - c7a4: b9401a83 ldr w3, [x20,#24] - c7a8: b9402e62 ldr w2, [x19,#44] - c7ac: 6b02007f cmp w3, w2 - c7b0: 54000121 b.ne c7d4 - c7b4: f9400a62 ldr x2, [x19,#16] - c7b8: eb1a005f cmp x2, x26 - c7bc: 54fffa80 b.eq c70c - c7c0: f9400e60 ldr x0, [x19,#24] - c7c4: eb02001f cmp x0, x2 - c7c8: 54fffa20 b.eq c70c - c7cc: 91000400 add x0, x0, #0x1 - c7d0: f9000e60 str x0, [x19,#24] - c7d4: b9402a60 ldr w0, [x19,#40] - c7d8: 51000800 sub w0, w0, #0x2 - c7dc: b9002a60 str w0, [x19,#40] - c7e0: 7100041f cmp w0, #0x1 - c7e4: 54000088 b.hi c7f4 - c7e8: f9400660 ldr x0, [x19,#8] - c7ec: b100041f cmn x0, #0x1 - c7f0: 540006e0 b.eq c8cc - c7f4: 52800001 mov w1, #0x0 // #0 - c7f8: 885f7e60 ldxr w0, [x19] - c7fc: 8802fe61 stlxr w2, w1, [x19] - c800: 35ffffc2 cbnz w2, c7f8 - c804: 7100041f cmp w0, #0x1 - c808: 54000b0c b.gt c968 - c80c: 9e660120 fmov x0, d9 - c810: 52800001 mov w1, #0x0 // #0 - c814: 94000a83 bl f220 <_pthread_cleanup_pop> - c818: aa1703e0 mov x0, x23 - c81c: 35000535 cbnz w21, c8c0 - c820: 97fffa43 bl b12c <__pthread_mutex_cond_lock> - c824: 2a0003e4 mov w4, w0 - c828: 2a0403e0 mov w0, w4 - c82c: 6d4627e8 ldp d8, d9, [sp,#96] - c830: a94153f3 ldp x19, x20, [sp,#16] - c834: a9425bf5 ldp x21, x22, [sp,#32] - c838: a94363f7 ldp x23, x24, [sp,#48] - c83c: a9446bf9 ldp x25, x26, [sp,#64] - c840: a94573fb ldp x27, x28, [sp,#80] - c844: a8cc7bfd ldp x29, x30, [sp],#192 - c848: d65f03c0 ret - c84c: b900a3a1 str w1, [x29,#160] - c850: 2a0003f8 mov w24, w0 - c854: aa1303e0 mov x0, x19 - c858: 2a1803e1 mov w1, w24 - c85c: 94000bda bl f7c4 <__lll_lock_wait> - c860: 17ffff84 b c670 - c864: aa1703e0 mov x0, x23 - c868: 97fffab3 bl b334 <__pthread_mutex_cond_lock_adjust> - c86c: aa1703e0 mov x0, x23 - c870: 52800001 mov w1, #0x0 // #0 - c874: 97fff828 bl a914 <__pthread_mutex_unlock_usercnt> - c878: 17ffffaf b c734 - c87c: 91001260 add x0, x19, #0x4 - c880: aa1c03e1 mov x1, x28 - c884: 2a1603e2 mov w2, w22 - c888: d2800003 mov x3, #0x0 // #0 - c88c: aa1703e4 mov x4, x23 - c890: d2800c48 mov x8, #0x62 // #98 - c894: d4000001 svc #0x0 - c898: b140041f cmn x0, #0x1, lsl #12 - c89c: 1a9f87f5 cset w21, ls - c8a0: 17ffffb3 b c76c - c8a4: aa1303e0 mov x0, x19 - c8a8: d2800022 mov x2, #0x1 // #1 - c8ac: 9e660101 fmov x1, d8 - c8b0: d2800003 mov x3, #0x0 // #0 - c8b4: d2800c48 mov x8, #0x62 // #98 - c8b8: d4000001 svc #0x0 - c8bc: 17ffff9b b c728 - c8c0: 97fffa9d bl b334 <__pthread_mutex_cond_lock_adjust> - c8c4: 52800004 mov w4, #0x0 // #0 - c8c8: 17ffffd8 b c828 - c8cc: 52801021 mov w1, #0x81 // #129 - c8d0: 9100a260 add x0, x19, #0x28 - c8d4: 4a010301 eor w1, w24, w1 - c8d8: d2800022 mov x2, #0x1 // #1 - c8dc: d2800003 mov x3, #0x0 // #0 - c8e0: d2800c48 mov x8, #0x62 // #98 - c8e4: 93407c21 sxtw x1, w1 - c8e8: d4000001 svc #0x0 - c8ec: 17ffffc2 b c7f4 - c8f0: 885ffe61 ldaxr w1, [x19] - c8f4: 6b1f003f cmp w1, wzr - c8f8: 54000061 b.ne c904 - c8fc: 88027e60 stxr w2, w0, [x19] - c900: 35ffff82 cbnz w2, c8f0 - c904: 54000080 b.eq c914 - c908: b900a3a1 str w1, [x29,#160] - c90c: 52801018 mov w24, #0x80 // #128 - c910: 17ffffd1 b c854 - c914: aa1703e0 mov x0, x23 - c918: 52800001 mov w1, #0x0 // #0 - c91c: 52801018 mov w24, #0x80 // #128 - c920: 97fff7fd bl a914 <__pthread_mutex_unlock_usercnt> - c924: 34ffeae0 cbz w0, c680 - c928: 52800002 mov w2, #0x0 // #0 - c92c: 885f7e61 ldxr w1, [x19] - c930: 8803fe62 stlxr w3, w2, [x19] - c934: 35ffffc3 cbnz w3, c92c - c938: 7100043f cmp w1, #0x1 - c93c: 2a0003e4 mov w4, w0 - c940: 54fff74d b.le c828 - c944: 52801021 mov w1, #0x81 // #129 - c948: aa1303e0 mov x0, x19 - c94c: 4a010301 eor w1, w24, w1 - c950: d2800022 mov x2, #0x1 // #1 - c954: d2800003 mov x3, #0x0 // #0 - c958: d2800c48 mov x8, #0x62 // #98 - c95c: 93407c21 sxtw x1, w1 - c960: d4000001 svc #0x0 - c964: 17ffffb1 b c828 - c968: 52801021 mov w1, #0x81 // #129 - c96c: aa1303e0 mov x0, x19 - c970: 4a010301 eor w1, w24, w1 - c974: d2800022 mov x2, #0x1 // #1 - c978: d2800003 mov x3, #0x0 // #0 - c97c: d2800c48 mov x8, #0x62 // #98 - c980: 93407c21 sxtw x1, w1 - c984: d4000001 svc #0x0 - c988: 17ffffa1 b c80c - -000000000000c98c : - c98c: a9b37bfd stp x29, x30, [sp,#-208]! - c990: d2993fe3 mov x3, #0xc9ff // #51711 - c994: 528002c4 mov w4, #0x16 // #22 - c998: 910003fd mov x29, sp - c99c: 6d0627e8 stp d8, d9, [sp,#96] - c9a0: f9400445 ldr x5, [x2,#8] - c9a4: f2a77343 movk x3, #0x3b9a, lsl #16 - c9a8: a90153f3 stp x19, x20, [sp,#16] - c9ac: a9025bf5 stp x21, x22, [sp,#32] - c9b0: a90363f7 stp x23, x24, [sp,#48] - c9b4: a9046bf9 stp x25, x26, [sp,#64] - c9b8: a90573fb stp x27, x28, [sp,#80] - c9bc: eb0300bf cmp x5, x3 - c9c0: fd003bea str d10, [sp,#112] - c9c4: 54000169 b.ls c9f0 - c9c8: 2a0403e0 mov w0, w4 - c9cc: 6d4627e8 ldp d8, d9, [sp,#96] - c9d0: a94153f3 ldp x19, x20, [sp,#16] - c9d4: a9425bf5 ldp x21, x22, [sp,#32] - c9d8: a94363f7 ldp x23, x24, [sp,#48] - c9dc: a9446bf9 ldp x25, x26, [sp,#64] - c9e0: a94573fb ldp x27, x28, [sp,#80] - c9e4: fd403bea ldr d10, [sp,#112] - c9e8: a8cd7bfd ldp x29, x30, [sp],#208 - c9ec: d65f03c0 ret - c9f0: aa0003f3 mov x19, x0 - c9f4: f9401000 ldr x0, [x0,#32] - c9f8: b900b3bf str wzr, [x29,#176] - c9fc: aa0103f5 mov x21, x1 - ca00: b100041f cmn x0, #0x1 - ca04: aa0203f6 mov x22, x2 - ca08: 52800020 mov w0, #0x1 // #1 - ca0c: 540019a0 b.eq cd40 - ca10: 885ffe61 ldaxr w1, [x19] - ca14: 6b1f003f cmp w1, wzr - ca18: 54000061 b.ne ca24 - ca1c: 88027e60 stxr w2, w0, [x19] - ca20: 35ffff82 cbnz w2, ca10 - ca24: 1a9f17e0 cset w0, eq - ca28: 52800017 mov w23, #0x0 // #0 - ca2c: 34001360 cbz w0, cc98 - ca30: aa1503e0 mov x0, x21 - ca34: 52800001 mov w1, #0x0 // #0 - ca38: 97fff7b7 bl a914 <__pthread_mutex_unlock_usercnt> - ca3c: 35001500 cbnz w0, ccdc - ca40: f9400663 ldr x3, [x19,#8] - ca44: b9400662 ldr w2, [x19,#4] - ca48: b9402a61 ldr w1, [x19,#40] - ca4c: 91000463 add x3, x3, #0x1 - ca50: 11000442 add w2, w2, #0x1 - ca54: f9000663 str x3, [x19,#8] - ca58: b9000662 str w2, [x19,#4] - ca5c: 11000821 add w1, w1, #0x2 - ca60: b9002a61 str w1, [x19,#40] - ca64: f94002c4 ldr x4, [x22] - ca68: b7f81a44 tbnz x4, #63, cdb0 - ca6c: f9401260 ldr x0, [x19,#32] - ca70: b100041f cmn x0, #0x1 - ca74: 54000040 b.eq ca7c - ca78: f9001275 str x21, [x19,#32] - ca7c: 910243a0 add x0, x29, #0x90 - ca80: 9102c3b4 add x20, x29, #0xb0 - ca84: 90000001 adrp x1, c000 <__pthread_rwlock_unlock+0x20> - ca88: aa1403e2 mov x2, x20 - ca8c: 9e670009 fmov d9, x0 - ca90: 9110d021 add x1, x1, #0x434 - ca94: f9005fb3 str x19, [x29,#184] - ca98: 5280001b mov w27, #0x0 // #0 - ca9c: f90063b5 str x21, [x29,#192] - caa0: d10006b9 sub x25, x21, #0x1 - caa4: 2a1b03f8 mov w24, w27 - caa8: 940009d6 bl f200 <_pthread_cleanup_push> - caac: f9400a7a ldr x26, [x19,#16] - cab0: 52801020 mov w0, #0x81 // #129 - cab4: b9402e61 ldr w1, [x19,#44] - cab8: 4a0002e0 eor w0, w23, w0 - cabc: b900cba1 str w1, [x29,#200] - cac0: 910233a1 add x1, x29, #0x8c - cac4: 93407c00 sxtw x0, w0 - cac8: 9e670028 fmov d8, x1 - cacc: 9e67000a fmov d10, x0 - cad0: b940067c ldr w28, [x19,#4] - cad4: 885f7e60 ldxr w0, [x19] - cad8: 8801fe78 stlxr w1, w24, [x19] - cadc: 35ffffc1 cbnz w1, cad4 - cae0: 7100041f cmp w0, #0x1 - cae4: 54000e6c b.gt ccb0 - cae8: 94000acc bl f618 <__pthread_enable_asynccancel> - caec: b9000280 str w0, [x20] - caf0: 35000a5b cbnz w27, cc38 - caf4: b1000f3f cmn x25, #0x3 - caf8: 540000a8 b.hi cb0c - cafc: b94012a0 ldr w0, [x21,#16] - cb00: 121c0400 and w0, w0, #0x30 - cb04: 7100801f cmp w0, #0x20 - cb08: 54000a40 b.eq cc50 - cb0c: b9402a65 ldr w5, [x19,#40] - cb10: 52801121 mov w1, #0x89 // #137 - cb14: 52803126 mov w6, #0x189 // #393 - cb18: 91001260 add x0, x19, #0x4 - cb1c: 120000a5 and w5, w5, #0x1 - cb20: 2a1c03e2 mov w2, w28 - cb24: 6b1f00bf cmp w5, wzr - cb28: aa1603e3 mov x3, x22 - cb2c: 1a861026 csel w6, w1, w6, ne - cb30: d2800004 mov x4, #0x0 // #0 - cb34: b2407fe5 mov x5, #0xffffffff // #4294967295 - cb38: d2800c48 mov x8, #0x62 // #98 - cb3c: 4a1700c1 eor w1, w6, w23 - cb40: d4000001 svc #0x0 - cb44: b13ffc1f cmn x0, #0xfff - cb48: 2a0403fb mov w27, w4 - cb4c: 1a9f201c csel w28, w0, wzr, cs - cb50: b9400280 ldr w0, [x20] - cb54: 94000ae1 bl f6d8 <__pthread_disable_asynccancel> - cb58: b9008fbf str wzr, [x29,#140] - cb5c: 52800020 mov w0, #0x1 // #1 - cb60: 885ffe62 ldaxr w2, [x19] - cb64: 6b1f005f cmp w2, wzr - cb68: 54000061 b.ne cb74 - cb6c: 88017e60 stxr w1, w0, [x19] - cb70: 35ffff81 cbnz w1, cb60 - cb74: 540000c0 b.eq cb8c - cb78: 9e660103 fmov x3, d8 - cb7c: aa1303e0 mov x0, x19 - cb80: 2a1703e1 mov w1, w23 - cb84: b9000062 str w2, [x3] - cb88: 94000b0f bl f7c4 <__lll_lock_wait> - cb8c: b9401a81 ldr w1, [x20,#24] - cb90: b9402e60 ldr w0, [x19,#44] - cb94: 6b00003f cmp w1, w0 - cb98: 54000ea1 b.ne cd6c - cb9c: f9400a65 ldr x5, [x19,#16] - cba0: eb1a00bf cmp x5, x26 - cba4: 54000080 b.eq cbb4 - cba8: f9400e60 ldr x0, [x19,#24] - cbac: eb05001f cmp x0, x5 - cbb0: 54000e61 b.ne cd7c - cbb4: 3101bb9f cmn w28, #0x6e - cbb8: 54fff8c1 b.ne cad0 - cbbc: b9400662 ldr w2, [x19,#4] - cbc0: b9402a61 ldr w1, [x19,#40] - cbc4: f9400663 ldr x3, [x19,#8] - cbc8: f9400e60 ldr x0, [x19,#24] - cbcc: 910004a5 add x5, x5, #0x1 - cbd0: 11000442 add w2, w2, #0x1 - cbd4: f9000a65 str x5, [x19,#16] - cbd8: b9000662 str w2, [x19,#4] - cbdc: 52800dd4 mov w20, #0x6e // #110 - cbe0: 91000400 add x0, x0, #0x1 - cbe4: f9000e60 str x0, [x19,#24] - cbe8: 51000821 sub w1, w1, #0x2 - cbec: b9002a61 str w1, [x19,#40] - cbf0: 7100043f cmp w1, #0x1 - cbf4: 54000068 b.hi cc00 - cbf8: b100047f cmn x3, #0x1 - cbfc: 54000900 b.eq cd1c - cc00: 52800001 mov w1, #0x0 // #0 - cc04: 885f7e60 ldxr w0, [x19] - cc08: 8802fe61 stlxr w2, w1, [x19] - cc0c: 35ffffc2 cbnz w2, cc04 - cc10: 7100041f cmp w0, #0x1 - cc14: 54000bcc b.gt cd8c - cc18: 9e660120 fmov x0, d9 - cc1c: 52800001 mov w1, #0x0 // #0 - cc20: 94000980 bl f220 <_pthread_cleanup_pop> - cc24: aa1503e0 mov x0, x21 - cc28: 3400053b cbz w27, cccc - cc2c: 97fff9c2 bl b334 <__pthread_mutex_cond_lock_adjust> - cc30: 2a1403e4 mov w4, w20 - cc34: 17ffff65 b c9c8 - cc38: aa1503e0 mov x0, x21 - cc3c: 97fff9be bl b334 <__pthread_mutex_cond_lock_adjust> - cc40: aa1503e0 mov x0, x21 - cc44: 52800001 mov w1, #0x0 // #0 - cc48: 97fff733 bl a914 <__pthread_mutex_unlock_usercnt> - cc4c: 17ffffaa b caf4 - cc50: b9402a61 ldr w1, [x19,#40] - cc54: 52803164 mov w4, #0x18b // #395 - cc58: 91001260 add x0, x19, #0x4 - cc5c: 2a1c03e2 mov w2, w28 - cc60: 12000021 and w1, w1, #0x1 - cc64: aa1603e3 mov x3, x22 - cc68: 6b1f003f cmp w1, wzr - cc6c: 52801161 mov w1, #0x8b // #139 - cc70: 1a841021 csel w1, w1, w4, ne - cc74: d2800c48 mov x8, #0x62 // #98 - cc78: aa1503e4 mov x4, x21 - cc7c: 4a170021 eor w1, w1, w23 - cc80: d4000001 svc #0x0 - cc84: b13ffc1f cmn x0, #0xfff - cc88: 1a9f201c csel w28, w0, wzr, cs - cc8c: b13ffc1f cmn x0, #0xfff - cc90: 1a9f27fb cset w27, cc - cc94: 17ffffaf b cb50 - cc98: b900b3a1 str w1, [x29,#176] - cc9c: 2a0003f7 mov w23, w0 - cca0: aa1303e0 mov x0, x19 - cca4: 2a1703e1 mov w1, w23 - cca8: 94000ac7 bl f7c4 <__lll_lock_wait> - ccac: 17ffff61 b ca30 - ccb0: aa1303e0 mov x0, x19 - ccb4: d2800022 mov x2, #0x1 // #1 - ccb8: 9e660141 fmov x1, d10 - ccbc: d2800003 mov x3, #0x0 // #0 - ccc0: d2800c48 mov x8, #0x62 // #98 - ccc4: d4000001 svc #0x0 - ccc8: 17ffff88 b cae8 - cccc: 97fff918 bl b12c <__pthread_mutex_cond_lock> - ccd0: 6b1f001f cmp w0, wzr - ccd4: 1a941004 csel w4, w0, w20, ne - ccd8: 17ffff3c b c9c8 - ccdc: 52800002 mov w2, #0x0 // #0 - cce0: 885f7e61 ldxr w1, [x19] - cce4: 8803fe62 stlxr w3, w2, [x19] - cce8: 35ffffc3 cbnz w3, cce0 - ccec: 7100043f cmp w1, #0x1 - ccf0: 2a0003e4 mov w4, w0 - ccf4: 54ffe6ad b.le c9c8 - ccf8: 52801021 mov w1, #0x81 // #129 - ccfc: aa1303e0 mov x0, x19 - cd00: 4a0102e1 eor w1, w23, w1 - cd04: d2800022 mov x2, #0x1 // #1 - cd08: d2800003 mov x3, #0x0 // #0 - cd0c: d2800c48 mov x8, #0x62 // #98 - cd10: 93407c21 sxtw x1, w1 - cd14: d4000001 svc #0x0 - cd18: 17ffff2c b c9c8 - cd1c: 52801021 mov w1, #0x81 // #129 - cd20: 9100a260 add x0, x19, #0x28 - cd24: 4a0102e1 eor w1, w23, w1 - cd28: d2800022 mov x2, #0x1 // #1 - cd2c: d2800003 mov x3, #0x0 // #0 - cd30: d2800c48 mov x8, #0x62 // #98 - cd34: 93407c21 sxtw x1, w1 - cd38: d4000001 svc #0x0 - cd3c: 17ffffb1 b cc00 - cd40: 885ffe61 ldaxr w1, [x19] - cd44: 6b1f003f cmp w1, wzr - cd48: 54000061 b.ne cd54 - cd4c: 88027e60 stxr w2, w0, [x19] - cd50: 35ffff82 cbnz w2, cd40 - cd54: 54000080 b.eq cd64 - cd58: b900b3a1 str w1, [x29,#176] - cd5c: 52801017 mov w23, #0x80 // #128 - cd60: 17ffffd0 b cca0 - cd64: 52801017 mov w23, #0x80 // #128 - cd68: 17ffff32 b ca30 - cd6c: b9402a61 ldr w1, [x19,#40] - cd70: 52800014 mov w20, #0x0 // #0 - cd74: f9400663 ldr x3, [x19,#8] - cd78: 17ffff9c b cbe8 - cd7c: b9402a61 ldr w1, [x19,#40] - cd80: 52800014 mov w20, #0x0 // #0 - cd84: f9400663 ldr x3, [x19,#8] - cd88: 17ffff96 b cbe0 - cd8c: 52801021 mov w1, #0x81 // #129 - cd90: aa1303e0 mov x0, x19 - cd94: 4a0102e1 eor w1, w23, w1 - cd98: d2800022 mov x2, #0x1 // #1 - cd9c: d2800003 mov x3, #0x0 // #0 - cda0: d2800c48 mov x8, #0x62 // #98 - cda4: 93407c21 sxtw x1, w1 - cda8: d4000001 svc #0x0 - cdac: 17ffff9b b cc18 - cdb0: 2a0003fb mov w27, w0 - cdb4: 910243a0 add x0, x29, #0x90 - cdb8: f9400a65 ldr x5, [x19,#16] - cdbc: 9e670009 fmov d9, x0 - cdc0: 17ffff82 b cbc8 - -000000000000cdc4 : - cdc4: a9bd7bfd stp x29, x30, [sp,#-48]! - cdc8: 910003fd mov x29, sp - cdcc: a90153f3 stp x19, x20, [sp,#16] - cdd0: aa0003f3 mov x19, x0 - cdd4: f9401000 ldr x0, [x0,#32] - cdd8: b9002fbf str wzr, [x29,#44] - cddc: b100041f cmn x0, #0x1 - cde0: 52800020 mov w0, #0x1 // #1 - cde4: 54000ba0 b.eq cf58 - cde8: 885ffe61 ldaxr w1, [x19] - cdec: 6b1f003f cmp w1, wzr - cdf0: 54000061 b.ne cdfc - cdf4: 88027e60 stxr w2, w0, [x19] - cdf8: 35ffff82 cbnz w2, cde8 - cdfc: 1a9f17e0 cset w0, eq - ce00: 52800014 mov w20, #0x0 // #0 - ce04: 34000400 cbz w0, ce84 - ce08: f9400a60 ldr x0, [x19,#16] - ce0c: f9400661 ldr x1, [x19,#8] - ce10: eb00003f cmp x1, x0 - ce14: 54000849 b.ls cf1c - ce18: f9401264 ldr x4, [x19,#32] - ce1c: 91000400 add x0, x0, #0x1 - ce20: b9400665 ldr w5, [x19,#4] - ce24: d1000481 sub x1, x4, #0x1 - ce28: f9000a60 str x0, [x19,#16] - ce2c: 110004a5 add w5, w5, #0x1 - ce30: b1000c3f cmn x1, #0x3 - ce34: b9000665 str w5, [x19,#4] - ce38: 54000329 b.ls ce9c - ce3c: 528010a1 mov w1, #0x85 // #133 - ce40: d2800022 mov x2, #0x1 // #1 - ce44: 4a010281 eor w1, w20, w1 - ce48: 91001266 add x6, x19, #0x4 - ce4c: aa0203e5 mov x5, x2 - ce50: aa0603e0 mov x0, x6 - ce54: 93407c21 sxtw x1, w1 - ce58: aa0203e3 mov x3, x2 - ce5c: aa1303e4 mov x4, x19 - ce60: f2a08005 movk x5, #0x400, lsl #16 - ce64: d2800c48 mov x8, #0x62 // #98 - ce68: d4000001 svc #0x0 - ce6c: b140041f cmn x0, #0x1, lsl #12 - ce70: 540004a8 b.hi cf04 - ce74: 52800000 mov w0, #0x0 // #0 - ce78: a94153f3 ldp x19, x20, [sp,#16] - ce7c: a8c37bfd ldp x29, x30, [sp],#48 - ce80: d65f03c0 ret - ce84: b9002fa1 str w1, [x29,#44] - ce88: 2a0003f4 mov w20, w0 - ce8c: aa1303e0 mov x0, x19 - ce90: 2a1403e1 mov w1, w20 - ce94: 94000a4c bl f7c4 <__lll_lock_wait> - ce98: 17ffffdc b ce08 - ce9c: b9401080 ldr w0, [x4,#16] - cea0: 121c0400 and w0, w0, #0x30 - cea4: 7100801f cmp w0, #0x20 - cea8: 54fffca1 b.ne ce3c - ceac: 52801181 mov w1, #0x8c // #140 - ceb0: 91001260 add x0, x19, #0x4 - ceb4: 4a010281 eor w1, w20, w1 - ceb8: d2800022 mov x2, #0x1 // #1 - cebc: d2800003 mov x3, #0x0 // #0 - cec0: d2800c48 mov x8, #0x62 // #98 - cec4: 93407c21 sxtw x1, w1 - cec8: d4000001 svc #0x0 - cecc: b140041f cmn x0, #0x1, lsl #12 - ced0: 2a0303e1 mov w1, w3 - ced4: 54fffb48 b.hi ce3c - ced8: 885f7e60 ldxr w0, [x19] - cedc: 8804fe61 stlxr w4, w1, [x19] - cee0: 35ffffc4 cbnz w4, ced8 - cee4: 7100041f cmp w0, #0x1 - cee8: 54fffc6d b.le ce74 - ceec: 52801021 mov w1, #0x81 // #129 - cef0: aa1303e0 mov x0, x19 - cef4: 4a010281 eor w1, w20, w1 - cef8: 93407c21 sxtw x1, w1 - cefc: d4000001 svc #0x0 - cf00: 17ffffdd b ce74 - cf04: 52801021 mov w1, #0x81 // #129 - cf08: aa0603e0 mov x0, x6 - cf0c: 4a010281 eor w1, w20, w1 - cf10: d2800003 mov x3, #0x0 // #0 - cf14: 93407c21 sxtw x1, w1 - cf18: d4000001 svc #0x0 - cf1c: 52800001 mov w1, #0x0 // #0 - cf20: 885f7e60 ldxr w0, [x19] - cf24: 8802fe61 stlxr w2, w1, [x19] - cf28: 35ffffc2 cbnz w2, cf20 - cf2c: 7100041f cmp w0, #0x1 - cf30: 54fffa2d b.le ce74 - cf34: 52801021 mov w1, #0x81 // #129 - cf38: aa1303e0 mov x0, x19 - cf3c: 4a010281 eor w1, w20, w1 - cf40: d2800022 mov x2, #0x1 // #1 - cf44: d2800003 mov x3, #0x0 // #0 - cf48: d2800c48 mov x8, #0x62 // #98 - cf4c: 93407c21 sxtw x1, w1 - cf50: d4000001 svc #0x0 - cf54: 17ffffc8 b ce74 - cf58: 885ffe61 ldaxr w1, [x19] - cf5c: 6b1f003f cmp w1, wzr - cf60: 54000061 b.ne cf6c - cf64: 88027e60 stxr w2, w0, [x19] - cf68: 35ffff82 cbnz w2, cf58 - cf6c: 54000080 b.eq cf7c - cf70: b9002fa1 str w1, [x29,#44] - cf74: 52801014 mov w20, #0x80 // #128 - cf78: 17ffffc5 b ce8c - cf7c: 52801014 mov w20, #0x80 // #128 - cf80: 17ffffa2 b ce08 - -000000000000cf84 : - cf84: a9bd7bfd stp x29, x30, [sp,#-48]! - cf88: 910003fd mov x29, sp - cf8c: a90153f3 stp x19, x20, [sp,#16] - cf90: aa0003f3 mov x19, x0 - cf94: f9401000 ldr x0, [x0,#32] - cf98: b9002fbf str wzr, [x29,#44] - cf9c: b100041f cmn x0, #0x1 - cfa0: 52800020 mov w0, #0x1 // #1 - cfa4: 540009a0 b.eq d0d8 - cfa8: 885ffe61 ldaxr w1, [x19] - cfac: 6b1f003f cmp w1, wzr - cfb0: 54000061 b.ne cfbc - cfb4: 88027e60 stxr w2, w0, [x19] - cfb8: 35ffff82 cbnz w2, cfa8 - cfbc: 1a9f17e0 cset w0, eq - cfc0: 52800014 mov w20, #0x0 // #0 - cfc4: 340005e0 cbz w0, d080 - cfc8: f9400660 ldr x0, [x19,#8] - cfcc: f9400a61 ldr x1, [x19,#16] - cfd0: eb01001f cmp x0, x1 - cfd4: 54000629 b.ls d098 - cfd8: b9402e61 ldr w1, [x19,#44] - cfdc: 531f7805 lsl w5, w0, #1 - cfe0: f9000a60 str x0, [x19,#16] - cfe4: 11000421 add w1, w1, #0x1 - cfe8: f9000e60 str x0, [x19,#24] - cfec: b9002e61 str w1, [x19,#44] - cff0: 52800001 mov w1, #0x0 // #0 - cff4: b9000665 str w5, [x19,#4] - cff8: 885f7e60 ldxr w0, [x19] - cffc: 8802fe61 stlxr w2, w1, [x19] - d000: 35ffffc2 cbnz w2, cff8 - d004: 7100041f cmp w0, #0x1 - d008: 540007ec b.gt d104 - d00c: f9401264 ldr x4, [x19,#32] - d010: b100049f cmn x4, #0x1 - d014: 540001e0 b.eq d050 - d018: b9401080 ldr w0, [x4,#16] - d01c: 373801a0 tbnz w0, #7, d050 - d020: d1000481 sub x1, x4, #0x1 - d024: b1000c3f cmn x1, #0x3 - d028: 540004c9 b.ls d0c0 - d02c: 91001260 add x0, x19, #0x4 - d030: d2801081 mov x1, #0x84 // #132 - d034: d2800022 mov x2, #0x1 // #1 - d038: b2407be3 mov x3, #0x7fffffff // #2147483647 - d03c: 93407ca5 sxtw x5, w5 - d040: d2800c48 mov x8, #0x62 // #98 - d044: d4000001 svc #0x0 - d048: b140041f cmn x0, #0x1, lsl #12 - d04c: 54000329 b.ls d0b0 - d050: 52801021 mov w1, #0x81 // #129 - d054: 91001260 add x0, x19, #0x4 - d058: 4a010281 eor w1, w20, w1 - d05c: b2407be2 mov x2, #0x7fffffff // #2147483647 - d060: d2800003 mov x3, #0x0 // #0 - d064: d2800c48 mov x8, #0x62 // #98 - d068: 93407c21 sxtw x1, w1 - d06c: d4000001 svc #0x0 - d070: 52800000 mov w0, #0x0 // #0 - d074: a94153f3 ldp x19, x20, [sp,#16] - d078: a8c37bfd ldp x29, x30, [sp],#48 - d07c: d65f03c0 ret - d080: b9002fa1 str w1, [x29,#44] - d084: 2a0003f4 mov w20, w0 - d088: aa1303e0 mov x0, x19 - d08c: 2a1403e1 mov w1, w20 - d090: 940009cd bl f7c4 <__lll_lock_wait> - d094: 17ffffcd b cfc8 - d098: 52800001 mov w1, #0x0 // #0 - d09c: 885f7e60 ldxr w0, [x19] - d0a0: 8802fe61 stlxr w2, w1, [x19] - d0a4: 35ffffc2 cbnz w2, d09c - d0a8: 7100041f cmp w0, #0x1 - d0ac: 540003ec b.gt d128 - d0b0: 52800000 mov w0, #0x0 // #0 - d0b4: a94153f3 ldp x19, x20, [sp,#16] - d0b8: a8c37bfd ldp x29, x30, [sp],#48 - d0bc: d65f03c0 ret - d0c0: 121c0400 and w0, w0, #0x30 - d0c4: 7100801f cmp w0, #0x20 - d0c8: 54fffb21 b.ne d02c - d0cc: 91001260 add x0, x19, #0x4 - d0d0: d2801181 mov x1, #0x8c // #140 - d0d4: 17ffffd8 b d034 - d0d8: 885ffe61 ldaxr w1, [x19] - d0dc: 6b1f003f cmp w1, wzr - d0e0: 54000061 b.ne d0ec - d0e4: 88027e60 stxr w2, w0, [x19] - d0e8: 35ffff82 cbnz w2, d0d8 - d0ec: 54000080 b.eq d0fc - d0f0: b9002fa1 str w1, [x29,#44] - d0f4: 52801014 mov w20, #0x80 // #128 - d0f8: 17ffffe4 b d088 - d0fc: 52801014 mov w20, #0x80 // #128 - d100: 17ffffb2 b cfc8 - d104: 52801021 mov w1, #0x81 // #129 - d108: aa1303e0 mov x0, x19 - d10c: 4a010281 eor w1, w20, w1 - d110: d2800022 mov x2, #0x1 // #1 - d114: d2800003 mov x3, #0x0 // #0 - d118: d2800c48 mov x8, #0x62 // #98 - d11c: 93407c21 sxtw x1, w1 - d120: d4000001 svc #0x0 - d124: 17ffffba b d00c - d128: 52801021 mov w1, #0x81 // #129 - d12c: aa1303e0 mov x0, x19 - d130: 4a010281 eor w1, w20, w1 - d134: d2800022 mov x2, #0x1 // #1 - d138: d2800003 mov x3, #0x0 // #0 - d13c: d2800c48 mov x8, #0x62 // #98 - d140: 93407c21 sxtw x1, w1 - d144: d4000001 svc #0x0 - d148: 17ffffda b d0b0 - -000000000000d14c : - d14c: f900001f str xzr, [x0] - d150: 52800000 mov w0, #0x0 // #0 - d154: d65f03c0 ret - -000000000000d158 : - d158: 52800000 mov w0, #0x0 // #0 - d15c: d65f03c0 ret - -000000000000d160 : - d160: b9400002 ldr w2, [x0] - d164: 52800000 mov w0, #0x0 // #0 - d168: 12000042 and w2, w2, #0x1 - d16c: b9000022 str w2, [x1] - d170: d65f03c0 ret - -000000000000d174 : - d174: 7100043f cmp w1, #0x1 - d178: 54000108 b.hi d198 - d17c: b9400002 ldr w2, [x0] - d180: 52800003 mov w3, #0x0 // #0 - d184: 121f7842 and w2, w2, #0xfffffffe - d188: 2a020021 orr w1, w1, w2 - d18c: b9000001 str w1, [x0] - d190: 2a0303e0 mov w0, w3 - d194: d65f03c0 ret - d198: 528002c3 mov w3, #0x16 // #22 - d19c: 2a0303e0 mov w0, w3 - d1a0: d65f03c0 ret - -000000000000d1a4 : - d1a4: b9400002 ldr w2, [x0] - d1a8: 52800000 mov w0, #0x0 // #0 - d1ac: d3410442 ubfx x2, x2, #1, #1 - d1b0: b9000022 str w2, [x1] - d1b4: d65f03c0 ret - -000000000000d1b8 : - d1b8: 7100043f cmp w1, #0x1 - d1bc: aa0003e2 mov x2, x0 - d1c0: 528002c0 mov w0, #0x16 // #22 - d1c4: 54000049 b.ls d1cc - d1c8: d65f03c0 ret - d1cc: b9400043 ldr w3, [x2] - d1d0: 52800000 mov w0, #0x0 // #0 - d1d4: 121e7863 and w3, w3, #0xfffffffd - d1d8: 2a010461 orr w1, w3, w1, lsl #1 - d1dc: b9000041 str w1, [x2] - d1e0: d65f03c0 ret - -000000000000d1e4 : - d1e4: aa0003e1 mov x1, x0 - d1e8: 52800000 mov w0, #0x0 // #0 - d1ec: b9000020 str w0, [x1] - d1f0: d65f03c0 ret - -000000000000d1f4 : - d1f4: 52800000 mov w0, #0x0 // #0 - d1f8: d65f03c0 ret - -000000000000d1fc : - d1fc: d10043ff sub sp, sp, #0x10 - d200: 52800024 mov w4, #0x1 // #1 - d204: 885ffc01 ldaxr w1, [x0] - d208: 88027c04 stxr w2, w4, [x0] - d20c: 35ffffc2 cbnz w2, d204 - d210: b90007e1 str w1, [sp,#4] - d214: b94007e1 ldr w1, [sp,#4] - d218: 340002e1 cbz w1, d274 - d21c: 910033e3 add x3, sp, #0xc - d220: b9400001 ldr w1, [x0] - d224: 340000e1 cbz w1, d240 - d228: 52807d01 mov w1, #0x3e8 // #1000 - d22c: 14000002 b d234 - d230: 34000081 cbz w1, d240 - d234: b9400002 ldr w2, [x0] - d238: 51000421 sub w1, w1, #0x1 - d23c: 35ffffa2 cbnz w2, d230 - d240: b9000fff str wzr, [sp,#12] - d244: b9400061 ldr w1, [x3] - d248: 885ffc02 ldaxr w2, [x0] - d24c: 6b01005f cmp w2, w1 - d250: 54000061 b.ne d25c - d254: 88057c04 stxr w5, w4, [x0] - d258: 35ffff85 cbnz w5, d248 - d25c: 54000040 b.eq d264 - d260: b9000062 str w2, [x3] - d264: b9400fe1 ldr w1, [sp,#12] - d268: b9000be1 str w1, [sp,#8] - d26c: b9400be1 ldr w1, [sp,#8] - d270: 35fffd81 cbnz w1, d220 - d274: 52800000 mov w0, #0x0 // #0 - d278: 910043ff add sp, sp, #0x10 - d27c: d65f03c0 ret - -000000000000d280 : - d280: d10043ff sub sp, sp, #0x10 - d284: 52800022 mov w2, #0x1 // #1 - d288: 885ffc01 ldaxr w1, [x0] - d28c: 88037c02 stxr w3, w2, [x0] - d290: 35ffffc3 cbnz w3, d288 - d294: b9000fe1 str w1, [sp,#12] - d298: b9400fe0 ldr w0, [sp,#12] - d29c: 910043ff add sp, sp, #0x10 - d2a0: 6b1f001f cmp w0, wzr - d2a4: 52800200 mov w0, #0x10 // #16 - d2a8: 1a9f1000 csel w0, w0, wzr, ne - d2ac: d65f03c0 ret - -000000000000d2b0 : - d2b0: aa0003e1 mov x1, x0 - d2b4: d5033bbf dmb ish - d2b8: 52800000 mov w0, #0x0 // #0 - d2bc: b9000020 str w0, [x1] - d2c0: d65f03c0 ret - -000000000000d2c4 : - d2c4: 340002c2 cbz w2, d31c - d2c8: b40002e1 cbz x1, d324 - d2cc: b9400021 ldr w1, [x1] - d2d0: 34000161 cbz w1, d2fc - d2d4: 7100043f cmp w1, #0x1 - d2d8: 54000221 b.ne d31c - d2dc: 52800003 mov w3, #0x0 // #0 - d2e0: b900041f str wzr, [x0,#4] - d2e4: b9000802 str w2, [x0,#8] - d2e8: b9000c02 str w2, [x0,#12] - d2ec: b9000003 str w3, [x0] - d2f0: b9001003 str w3, [x0,#16] - d2f4: 52800000 mov w0, #0x0 // #0 - d2f8: d65f03c0 ret - d2fc: b9000401 str w1, [x0,#4] - d300: 52801003 mov w3, #0x80 // #128 - d304: b9000802 str w2, [x0,#8] - d308: b9000c02 str w2, [x0,#12] - d30c: b9000001 str w1, [x0] - d310: b9001003 str w3, [x0,#16] - d314: 52800000 mov w0, #0x0 // #0 - d318: d65f03c0 ret - d31c: 528002c0 mov w0, #0x16 // #22 - d320: d65f03c0 ret - d324: b0000021 adrp x1, 12000 <__pthread_current_priority+0xa8> - d328: 912ee021 add x1, x1, #0xbb8 - d32c: 17ffffe8 b d2cc - -000000000000d330 : - d330: a9bd7bfd stp x29, x30, [sp,#-48]! - d334: 910003fd mov x29, sp - d338: a90153f3 stp x19, x20, [sp,#16] - d33c: aa0003f3 mov x19, x0 - d340: 91001014 add x20, x0, #0x4 - d344: b9002fbf str wzr, [x29,#44] - d348: 52800020 mov w0, #0x1 // #1 - d34c: 885ffe82 ldaxr w2, [x20] - d350: 6b1f005f cmp w2, wzr - d354: 54000061 b.ne d360 - d358: 88017e80 stxr w1, w0, [x20] - d35c: 35ffff81 cbnz w1, d34c - d360: 54000141 b.ne d388 - d364: b9400a61 ldr w1, [x19,#8] - d368: 52800004 mov w4, #0x0 // #0 - d36c: b9400e60 ldr w0, [x19,#12] - d370: 6b00003f cmp w1, w0 - d374: 540001e1 b.ne d3b0 - d378: 2a0403e0 mov w0, w4 - d37c: a94153f3 ldp x19, x20, [sp,#16] - d380: a8c37bfd ldp x29, x30, [sp],#48 - d384: d65f03c0 ret - d388: b9401261 ldr w1, [x19,#16] - d38c: aa1403e0 mov x0, x20 - d390: b9002fa2 str w2, [x29,#44] - d394: 52190021 eor w1, w1, #0x80 - d398: 9400090b bl f7c4 <__lll_lock_wait> - d39c: b9400a61 ldr w1, [x19,#8] - d3a0: 52800004 mov w4, #0x0 // #0 - d3a4: b9400e60 ldr w0, [x19,#12] - d3a8: 6b00003f cmp w1, w0 - d3ac: 54fffe60 b.eq d378 - d3b0: 885f7e80 ldxr w0, [x20] - d3b4: 8801fe84 stlxr w1, w4, [x20] - d3b8: 35ffffc1 cbnz w1, d3b0 - d3bc: 7100041f cmp w0, #0x1 - d3c0: 52800204 mov w4, #0x10 // #16 - d3c4: 54fffdad b.le d378 - d3c8: b9401261 ldr w1, [x19,#16] - d3cc: aa1403e0 mov x0, x20 - d3d0: d2800022 mov x2, #0x1 // #1 - d3d4: d2800003 mov x3, #0x0 // #0 - d3d8: 52000021 eor w1, w1, #0x1 - d3dc: d2800c48 mov x8, #0x62 // #98 - d3e0: 93407c21 sxtw x1, w1 - d3e4: d4000001 svc #0x0 - d3e8: 17ffffe4 b d378 - -000000000000d3ec : - d3ec: a9bd7bfd stp x29, x30, [sp,#-48]! - d3f0: 910003fd mov x29, sp - d3f4: a90153f3 stp x19, x20, [sp,#16] - d3f8: aa0003f3 mov x19, x0 - d3fc: 91001014 add x20, x0, #0x4 - d400: b9002fbf str wzr, [x29,#44] - d404: 52800020 mov w0, #0x1 // #1 - d408: 885ffe82 ldaxr w2, [x20] - d40c: 6b1f005f cmp w2, wzr - d410: 54000061 b.ne d41c - d414: 88017e80 stxr w1, w0, [x20] - d418: 35ffff81 cbnz w1, d408 - d41c: 54000481 b.ne d4ac - d420: b9400a60 ldr w0, [x19,#8] - d424: 51000400 sub w0, w0, #0x1 - d428: b9000a60 str w0, [x19,#8] - d42c: 340007c0 cbz w0, d524 - d430: b9400264 ldr w4, [x19] - d434: 52800001 mov w1, #0x0 // #0 - d438: 885f7e80 ldxr w0, [x20] - d43c: 8802fe81 stlxr w2, w1, [x20] - d440: 35ffffc2 cbnz w2, d438 - d444: 7100041f cmp w0, #0x1 - d448: 540003ec b.gt d4c4 - d44c: 2a0403e5 mov w5, w4 - d450: aa1303e0 mov x0, x19 - d454: b9801261 ldrsw x1, [x19,#16] - d458: aa0503e2 mov x2, x5 - d45c: d2800003 mov x3, #0x0 // #0 - d460: d2800c48 mov x8, #0x62 // #98 - d464: d4000001 svc #0x0 - d468: b9400261 ldr w1, [x19] - d46c: 6b04003f cmp w1, w4 - d470: 54ffff00 b.eq d450 - d474: 2a0303e4 mov w4, w3 - d478: b9400e60 ldr w0, [x19,#12] - d47c: 91002262 add x2, x19, #0x8 - d480: 885ffc41 ldaxr w1, [x2] - d484: 11000423 add w3, w1, #0x1 - d488: 88057c43 stxr w5, w3, [x2] - d48c: 35ffffa5 cbnz w5, d480 - d490: 11000421 add w1, w1, #0x1 - d494: 6b00003f cmp w1, w0 - d498: 54000280 b.eq d4e8 - d49c: 2a0403e0 mov w0, w4 - d4a0: a94153f3 ldp x19, x20, [sp,#16] - d4a4: a8c37bfd ldp x29, x30, [sp],#48 - d4a8: d65f03c0 ret - d4ac: b9401261 ldr w1, [x19,#16] - d4b0: aa1403e0 mov x0, x20 - d4b4: b9002fa2 str w2, [x29,#44] - d4b8: 52190021 eor w1, w1, #0x80 - d4bc: 940008c2 bl f7c4 <__lll_lock_wait> - d4c0: 17ffffd8 b d420 - d4c4: b9401261 ldr w1, [x19,#16] - d4c8: aa1403e0 mov x0, x20 - d4cc: d2800022 mov x2, #0x1 // #1 - d4d0: d2800003 mov x3, #0x0 // #0 - d4d4: 52000021 eor w1, w1, #0x1 - d4d8: d2800c48 mov x8, #0x62 // #98 - d4dc: 93407c21 sxtw x1, w1 - d4e0: d4000001 svc #0x0 - d4e4: 17ffffda b d44c - d4e8: 52800001 mov w1, #0x0 // #0 - d4ec: 885f7e80 ldxr w0, [x20] - d4f0: 8802fe81 stlxr w2, w1, [x20] - d4f4: 35ffffc2 cbnz w2, d4ec - d4f8: 7100041f cmp w0, #0x1 - d4fc: 54fffd0d b.le d49c - d500: b9401261 ldr w1, [x19,#16] - d504: aa1403e0 mov x0, x20 - d508: d2800022 mov x2, #0x1 // #1 - d50c: d2800003 mov x3, #0x0 // #0 - d510: 52000021 eor w1, w1, #0x1 - d514: d2800c48 mov x8, #0x62 // #98 - d518: 93407c21 sxtw x1, w1 - d51c: d4000001 svc #0x0 - d520: 17ffffdf b d49c - d524: b9401261 ldr w1, [x19,#16] - d528: aa1303e0 mov x0, x19 - d52c: b9400264 ldr w4, [x19] - d530: b2407be2 mov x2, #0x7fffffff // #2147483647 - d534: 52000021 eor w1, w1, #0x1 - d538: d2800003 mov x3, #0x0 // #0 - d53c: 11000484 add w4, w4, #0x1 - d540: d2800c48 mov x8, #0x62 // #98 - d544: b9000264 str w4, [x19] - d548: 93407c21 sxtw x1, w1 - d54c: d4000001 svc #0x0 - d550: 12800004 mov w4, #0xffffffff // #-1 - d554: 17ffffc9 b d478 - -000000000000d558 : - d558: b900001f str wzr, [x0] - d55c: 52800000 mov w0, #0x0 // #0 - d560: d65f03c0 ret - -000000000000d564 : - d564: 52800000 mov w0, #0x0 // #0 - d568: d65f03c0 ret - -000000000000d56c : - d56c: b9400002 ldr w2, [x0] - d570: 52800000 mov w0, #0x0 // #0 - d574: b9000022 str w2, [x1] - d578: d65f03c0 ret - -000000000000d57c : - d57c: 7100043f cmp w1, #0x1 - d580: 54000088 b.hi d590 - d584: b9000001 str w1, [x0] - d588: 52800000 mov w0, #0x0 // #0 - d58c: d65f03c0 ret - d590: 528002c0 mov w0, #0x16 // #22 - d594: d65f03c0 ret - -000000000000d598 <__pthread_key_create>: - d598: f0000108 adrp x8, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - d59c: d10043ff sub sp, sp, #0x10 - d5a0: 910a2103 add x3, x8, #0x288 - d5a4: d2800004 mov x4, #0x0 // #0 - d5a8: 14000005 b d5bc <__pthread_key_create+0x24> - d5ac: 91000484 add x4, x4, #0x1 - d5b0: 91004063 add x3, x3, #0x10 - d5b4: f110009f cmp x4, #0x400 - d5b8: 54000280 b.eq d608 <__pthread_key_create+0x70> - d5bc: f9400062 ldr x2, [x3] - d5c0: 91000845 add x5, x2, #0x2 - d5c4: 92400046 and x6, x2, #0x1 - d5c8: eb05005f cmp x2, x5 - d5cc: 3707ff02 tbnz w2, #0, d5ac <__pthread_key_create+0x14> - d5d0: 54fffee2 b.cs d5ac <__pthread_key_create+0x14> - d5d4: f90007e2 str x2, [sp,#8] - d5d8: 91000445 add x5, x2, #0x1 - d5dc: c85ffc67 ldaxr x7, [x3] - d5e0: eb0200ff cmp x7, x2 - d5e4: 54000061 b.ne d5f0 <__pthread_key_create+0x58> - d5e8: c8097c65 stxr w9, x5, [x3] - d5ec: 35ffff89 cbnz w9, d5dc <__pthread_key_create+0x44> - d5f0: 54fffde1 b.ne d5ac <__pthread_key_create+0x14> - d5f4: 910a2108 add x8, x8, #0x288 - d5f8: 8b041108 add x8, x8, x4, lsl #4 - d5fc: f9000501 str x1, [x8,#8] - d600: b9000004 str w4, [x0] - d604: 14000002 b d60c <__pthread_key_create+0x74> - d608: 52800166 mov w6, #0xb // #11 - d60c: 2a0603e0 mov w0, w6 - d610: 910043ff add sp, sp, #0x10 - d614: d65f03c0 ret - -000000000000d618 : - d618: 710ffc1f cmp w0, #0x3ff - d61c: d10043ff sub sp, sp, #0x10 - d620: 54000208 b.hi d660 - d624: f0000101 adrp x1, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - d628: d37c7c00 ubfiz x0, x0, #4, #32 - d62c: 910a2021 add x1, x1, #0x288 - d630: 8b000022 add x2, x1, x0 - d634: f8606820 ldr x0, [x1,x0] - d638: 36000140 tbz w0, #0, d660 - d63c: 92407c01 and x1, x0, #0xffffffff - d640: 11000400 add w0, w0, #0x1 - d644: f90007e1 str x1, [sp,#8] - d648: c85ffc43 ldaxr x3, [x2] - d64c: eb01007f cmp x3, x1 - d650: 54000061 b.ne d65c - d654: c8047c40 stxr w4, x0, [x2] - d658: 35ffff84 cbnz w4, d648 - d65c: 54000080 b.eq d66c - d660: 528002c0 mov w0, #0x16 // #22 - d664: 910043ff add sp, sp, #0x10 - d668: d65f03c0 ret - d66c: 52800000 mov w0, #0x0 // #0 - d670: 17fffffd b d664 - -000000000000d674 <__pthread_getspecific>: - d674: 71007c1f cmp w0, #0x1f - d678: 540002a8 b.hi d6cc <__pthread_getspecific+0x58> - d67c: 2a0003e1 mov w1, w0 - d680: d53bd042 mrs x2, tpidr_el0 - d684: 8b011041 add x1, x2, x1, lsl #4 - d688: d1178021 sub x1, x1, #0x5e0 - d68c: f9400423 ldr x3, [x1,#8] - d690: b40001a3 cbz x3, d6c4 <__pthread_getspecific+0x50> - d694: d37c7c02 ubfiz x2, x0, #4, #32 - d698: aa0303e0 mov x0, x3 - d69c: f0000103 adrp x3, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - d6a0: f9400024 ldr x4, [x1] - d6a4: 910a2063 add x3, x3, #0x288 - d6a8: f8626862 ldr x2, [x3,x2] - d6ac: eb02009f cmp x4, x2 - d6b0: 54000041 b.ne d6b8 <__pthread_getspecific+0x44> - d6b4: d65f03c0 ret - d6b8: f900043f str xzr, [x1,#8] - d6bc: d2800000 mov x0, #0x0 // #0 - d6c0: d65f03c0 ret - d6c4: aa0303e0 mov x0, x3 - d6c8: d65f03c0 ret - d6cc: 710ffc1f cmp w0, #0x3ff - d6d0: 54000168 b.hi d6fc <__pthread_getspecific+0x88> - d6d4: d3457c01 ubfx x1, x0, #5, #27 - d6d8: d53bd043 mrs x3, tpidr_el0 - d6dc: d11bc063 sub x3, x3, #0x6f0 - d6e0: 91018821 add x1, x1, #0x62 - d6e4: 12001002 and w2, w0, #0x1f - d6e8: f8617861 ldr x1, [x3,x1,lsl #3] - d6ec: b40000c1 cbz x1, d704 <__pthread_getspecific+0x90> - d6f0: d37c1042 ubfiz x2, x2, #4, #5 - d6f4: 8b020021 add x1, x1, x2 - d6f8: 17ffffe5 b d68c <__pthread_getspecific+0x18> - d6fc: d2800000 mov x0, #0x0 // #0 - d700: d65f03c0 ret - d704: aa0103e0 mov x0, x1 - d708: d65f03c0 ret - -000000000000d70c <__pthread_setspecific>: - d70c: a9bc7bfd stp x29, x30, [sp,#-64]! - d710: 71007c1f cmp w0, #0x1f - d714: 910003fd mov x29, sp - d718: a90153f3 stp x19, x20, [sp,#16] - d71c: a9025bf5 stp x21, x22, [sp,#32] - d720: f9001bf7 str x23, [sp,#48] - d724: aa0103f6 mov x22, x1 - d728: d53bd054 mrs x20, tpidr_el0 - d72c: 540003c8 b.hi d7a4 <__pthread_setspecific+0x98> - d730: 2a0003e2 mov w2, w0 - d734: f0000103 adrp x3, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - d738: d37cec40 lsl x0, x2, #4 - d73c: 910a2063 add x3, x3, #0x288 - d740: 528002c4 mov w4, #0x16 // #22 - d744: f8606863 ldr x3, [x3,x0] - d748: 2a0303f5 mov w21, w3 - d74c: 370000e3 tbnz w3, #0, d768 <__pthread_setspecific+0x5c> - d750: 2a0403e0 mov w0, w4 - d754: f9401bf7 ldr x23, [sp,#48] - d758: a94153f3 ldp x19, x20, [sp,#16] - d75c: a9425bf5 ldp x21, x22, [sp,#32] - d760: a8c47bfd ldp x29, x30, [sp],#64 - d764: d65f03c0 ret - d768: 91004440 add x0, x2, #0x11 - d76c: d11bc294 sub x20, x20, #0x6f0 - d770: 8b001280 add x0, x20, x0, lsl #4 - d774: b4000061 cbz x1, d780 <__pthread_setspecific+0x74> - d778: 52800021 mov w1, #0x1 // #1 - d77c: 39104281 strb w1, [x20,#1040] - d780: f9000416 str x22, [x0,#8] - d784: f9000015 str x21, [x0] - d788: 52800004 mov w4, #0x0 // #0 - d78c: f9401bf7 ldr x23, [sp,#48] - d790: 2a0403e0 mov w0, w4 - d794: a94153f3 ldp x19, x20, [sp,#16] - d798: a9425bf5 ldp x21, x22, [sp,#32] - d79c: a8c47bfd ldp x29, x30, [sp],#64 - d7a0: d65f03c0 ret - d7a4: 710ffc1f cmp w0, #0x3ff - d7a8: 528002c4 mov w4, #0x16 // #22 - d7ac: 54fffd28 b.hi d750 <__pthread_setspecific+0x44> - d7b0: f0000102 adrp x2, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - d7b4: d37c7c01 ubfiz x1, x0, #4, #32 - d7b8: 910a2042 add x2, x2, #0x288 - d7bc: f8616841 ldr x1, [x2,x1] - d7c0: 2a0103f5 mov w21, w1 - d7c4: 3607fc61 tbz w1, #0, d750 <__pthread_setspecific+0x44> - d7c8: d3457c17 ubfx x23, x0, #5, #27 - d7cc: 12001013 and w19, w0, #0x1f - d7d0: 8b170e97 add x23, x20, x23, lsl #3 - d7d4: d10f82f7 sub x23, x23, #0x3e0 - d7d8: f94002e0 ldr x0, [x23] - d7dc: b40000a0 cbz x0, d7f0 <__pthread_setspecific+0xe4> - d7e0: d37c1273 ubfiz x19, x19, #4, #5 - d7e4: d11bc294 sub x20, x20, #0x6f0 - d7e8: 8b130000 add x0, x0, x19 - d7ec: 17ffffe3 b d778 <__pthread_setspecific+0x6c> - d7f0: b4fffcd6 cbz x22, d788 <__pthread_setspecific+0x7c> - d7f4: d2800400 mov x0, #0x20 // #32 - d7f8: d2800201 mov x1, #0x10 // #16 - d7fc: 97ffde3d bl 50f0 - d800: b4000060 cbz x0, d80c <__pthread_setspecific+0x100> - d804: f90002e0 str x0, [x23] - d808: 17fffff6 b d7e0 <__pthread_setspecific+0xd4> - d80c: 52800184 mov w4, #0xc // #12 - d810: 17ffffd0 b d750 <__pthread_setspecific+0x44> - -000000000000d814 : - d814: a9b67bfd stp x29, x30, [sp,#-160]! - d818: aa0103e3 mov x3, x1 - d81c: 910003fd mov x29, sp - d820: a90153f3 stp x19, x20, [sp,#16] - d824: 2a0003f4 mov w20, w0 - d828: aa0203f3 mov x19, x2 - d82c: b4000081 cbz x1, d83c - d830: f9400020 ldr x0, [x1] - d834: f261041f tst x0, #0x180000000 - d838: 54000181 b.ne d868 - d83c: aa0303e1 mov x1, x3 - d840: 93407e80 sxtw x0, w20 - d844: aa1303e2 mov x2, x19 - d848: d2800103 mov x3, #0x8 // #8 - d84c: d28010e8 mov x8, #0x87 // #135 - d850: d4000001 svc #0x0 - d854: 3140041f cmn w0, #0x1, lsl #12 - d858: 5a8097e0 csneg w0, wzr, w0, ls - d85c: a94153f3 ldp x19, x20, [sp,#16] - d860: a8ca7bfd ldp x29, x30, [sp],#160 - d864: d65f03c0 ret - d868: 910083a3 add x3, x29, #0x20 - d86c: d2801002 mov x2, #0x80 // #128 - d870: aa0303e0 mov x0, x3 - d874: 97ffddbb bl 4f60 - d878: aa0003e1 mov x1, x0 - d87c: f94013a0 ldr x0, [x29,#32] - d880: 925ff400 and x0, x0, #0xfffffffe7fffffff - d884: f90013a0 str x0, [x29,#32] - d888: 17ffffee b d840 - -000000000000d88c : - d88c: b940d003 ldr w3, [x0,#208] - d890: 93407c22 sxtw x2, w1 - d894: 2a0303e1 mov w1, w3 - d898: 6b1f003f cmp w1, wzr - d89c: 540001cd b.le d8d4 - d8a0: 51008044 sub w4, w2, #0x20 - d8a4: 528002c0 mov w0, #0x16 // #22 - d8a8: 7100049f cmp w4, #0x1 - d8ac: 54000129 b.ls d8d0 - d8b0: d53bd040 mrs x0, tpidr_el0 - d8b4: 93407c21 sxtw x1, w1 - d8b8: d11bc000 sub x0, x0, #0x6f0 - d8bc: d2801068 mov x8, #0x83 // #131 - d8c0: b980d400 ldrsw x0, [x0,#212] - d8c4: d4000001 svc #0x0 - d8c8: 3140041f cmn w0, #0x1, lsl #12 - d8cc: 5a8097e0 csneg w0, wzr, w0, ls - d8d0: d65f03c0 ret - d8d4: 52800060 mov w0, #0x3 // #3 - d8d8: d65f03c0 ret - -000000000000d8dc : - d8dc: a9b57bfd stp x29, x30, [sp,#-176]! - d8e0: 910003fd mov x29, sp - d8e4: a90153f3 stp x19, x20, [sp,#16] - d8e8: a9025bf5 stp x21, x22, [sp,#32] - d8ec: b940d013 ldr w19, [x0,#208] - d8f0: 6b1f027f cmp w19, wzr - d8f4: 540004ad b.le d988 - d8f8: 51008023 sub w3, w1, #0x20 - d8fc: 528002c0 mov w0, #0x16 // #22 - d900: 7100047f cmp w3, #0x1 - d904: 540003a9 b.ls d978 - d908: d53bd056 mrs x22, tpidr_el0 - d90c: 2a0103f4 mov w20, w1 - d910: d11bc2d6 sub x22, x22, #0x6f0 - d914: aa0203f5 mov x21, x2 - d918: a9037fbf stp xzr, xzr, [x29,#48] - d91c: b90033a1 str w1, [x29,#48] - d920: 12800001 mov w1, #0xffffffff // #-1 - d924: b940d6c0 ldr w0, [x22,#212] - d928: a9047fbf stp xzr, xzr, [x29,#64] - d92c: b9003ba1 str w1, [x29,#56] - d930: a9057fbf stp xzr, xzr, [x29,#80] - d934: a9067fbf stp xzr, xzr, [x29,#96] - d938: a9077fbf stp xzr, xzr, [x29,#112] - d93c: a9087fbf stp xzr, xzr, [x29,#128] - d940: a9097fbf stp xzr, xzr, [x29,#144] - d944: a90a7fbf stp xzr, xzr, [x29,#160] - d948: b90043a0 str w0, [x29,#64] - d94c: 97ffddb9 bl 5030 - d950: 93407e61 sxtw x1, w19 - d954: b90047a0 str w0, [x29,#68] - d958: f90027b5 str x21, [x29,#72] - d95c: 93407e82 sxtw x2, w20 - d960: b980d6c0 ldrsw x0, [x22,#212] - d964: 9100c3a3 add x3, x29, #0x30 - d968: d2801e08 mov x8, #0xf0 // #240 - d96c: d4000001 svc #0x0 - d970: 3140041f cmn w0, #0x1, lsl #12 - d974: 5a8097e0 csneg w0, wzr, w0, ls - d978: a94153f3 ldp x19, x20, [sp,#16] - d97c: a9425bf5 ldp x21, x22, [sp,#32] - d980: a8cb7bfd ldp x29, x30, [sp],#176 - d984: d65f03c0 ret - d988: 52800060 mov w0, #0x3 // #3 - d98c: a94153f3 ldp x19, x20, [sp,#16] - d990: a9425bf5 ldp x21, x22, [sp,#32] - d994: a8cb7bfd ldp x29, x30, [sp],#176 - d998: d65f03c0 ret - -000000000000d99c : - d99c: a9bd7bfd stp x29, x30, [sp,#-48]! - d9a0: 910003fd mov x29, sp - d9a4: b940d001 ldr w1, [x0,#208] - d9a8: f9000bf3 str x19, [sp,#16] - d9ac: 6b1f003f cmp w1, wzr - d9b0: 5400078d b.le daa0 - d9b4: aa0003f3 mov x19, x0 - d9b8: 94000fb5 bl 1188c - d9bc: d53bd047 mrs x7, tpidr_el0 - d9c0: f0000126 adrp x6, 34000 <__GI___pthread_keys+0x3d78> - d9c4: 12800885 mov w5, #0xffffffbb // #-69 - d9c8: d11bc0e7 sub x7, x7, #0x6f0 - d9cc: 52800023 mov w3, #0x1 // #1 - d9d0: f0000128 adrp x8, 34000 <__GI___pthread_keys+0x3d78> - d9d4: 910ca0c6 add x6, x6, #0x328 - d9d8: b9410a61 ldr w1, [x19,#264] - d9dc: 91042260 add x0, x19, #0x108 - d9e0: 321e0422 orr w2, w1, #0xc - d9e4: 6b02003f cmp w1, w2 - d9e8: 0a050044 and w4, w2, w5 - d9ec: 540001e0 b.eq da28 - d9f0: 7100289f cmp w4, #0xa - d9f4: 54000260 b.eq da40 - d9f8: b90000e3 str w3, [x7] - d9fc: f941b904 ldr x4, [x8,#880] - da00: b9000083 str w3, [x4] - da04: b9002fa1 str w1, [x29,#44] - da08: b90000c3 str w3, [x6] - da0c: b9402fa1 ldr w1, [x29,#44] - da10: 885ffc04 ldaxr w4, [x0] - da14: 6b01009f cmp w4, w1 - da18: 54000061 b.ne da24 - da1c: 88097c02 stxr w9, w2, [x0] - da20: 35ffff89 cbnz w9, da10 - da24: 540000a1 b.ne da38 - da28: 52800000 mov w0, #0x0 // #0 - da2c: f9400bf3 ldr x19, [sp,#16] - da30: a8c37bfd ldp x29, x30, [sp],#48 - da34: d65f03c0 ret - da38: b9002fa4 str w4, [x29,#44] - da3c: 17ffffe7 b d9d8 - da40: b9002ba1 str w1, [x29,#40] - da44: 91042260 add x0, x19, #0x108 - da48: 321e0021 orr w1, w1, #0x4 - da4c: b9402ba2 ldr w2, [x29,#40] - da50: 885ffc04 ldaxr w4, [x0] - da54: 6b02009f cmp w4, w2 - da58: 54000061 b.ne da64 - da5c: 88097c01 stxr w9, w1, [x0] - da60: 35ffff89 cbnz w9, da50 - da64: 540001a1 b.ne da98 - da68: d53bd040 mrs x0, tpidr_el0 - da6c: b940d261 ldr w1, [x19,#208] - da70: d11bc000 sub x0, x0, #0x6f0 - da74: d2800402 mov x2, #0x20 // #32 - da78: d2801068 mov x8, #0x83 // #131 - da7c: 93407c21 sxtw x1, w1 - da80: b980d400 ldrsw x0, [x0,#212] - da84: d4000001 svc #0x0 - da88: 3140041f cmn w0, #0x1, lsl #12 - da8c: 54fffce9 b.ls da28 - da90: 4b0003e0 neg w0, w0 - da94: 17ffffe6 b da2c - da98: b9002ba4 str w4, [x29,#40] - da9c: 17ffffcf b d9d8 - daa0: 52800060 mov w0, #0x3 // #3 - daa4: f9400bf3 ldr x19, [sp,#16] - daa8: a8c37bfd ldp x29, x30, [sp],#48 - daac: d65f03c0 ret - -000000000000dab0 : - dab0: d53bd042 mrs x2, tpidr_el0 - dab4: 128008c0 mov w0, #0xffffffb9 // #-71 - dab8: d11bc041 sub x1, x2, #0x6f0 - dabc: a9be7bfd stp x29, x30, [sp,#-32]! - dac0: 910003fd mov x29, sp - dac4: b9410823 ldr w3, [x1,#264] - dac8: 0a000060 and w0, w3, w0 - dacc: 7100201f cmp w0, #0x8 - dad0: 54000060 b.eq dadc - dad4: a8c27bfd ldp x29, x30, [sp],#32 - dad8: d65f03c0 ret - dadc: 92800000 mov x0, #0xffffffffffffffff // #-1 - dae0: 91042023 add x3, x1, #0x108 - dae4: f9021420 str x0, [x1,#1064] - dae8: d117a042 sub x2, x2, #0x5e8 - daec: 910073a4 add x4, x29, #0x1c - daf0: b9400040 ldr w0, [x2] - daf4: b9001fa0 str w0, [x29,#28] - daf8: 321c0006 orr w6, w0, #0x10 - dafc: 885ffc65 ldaxr w5, [x3] - db00: 6b0000bf cmp w5, w0 - db04: 54000061 b.ne db10 - db08: 88077c66 stxr w7, w6, [x3] - db0c: 35ffff87 cbnz w7, dafc - db10: 54000060 b.eq db1c - db14: b9000085 str w5, [x4] - db18: 17fffff6 b daf0 - db1c: f9408020 ldr x0, [x1,#256] - db20: 94000679 bl f504 <__pthread_unwind> - -000000000000db24 : - db24: a9be7bfd stp x29, x30, [sp,#-32]! - db28: 7100041f cmp w0, #0x1 - db2c: 528002c0 mov w0, #0x16 // #22 - db30: 910003fd mov x29, sp - db34: 54000069 b.ls db40 - db38: a8c27bfd ldp x29, x30, [sp],#32 - db3c: d65f03c0 ret - db40: d53bd045 mrs x5, tpidr_el0 - db44: d11bc0a4 sub x4, x5, #0x6f0 - db48: b9410880 ldr w0, [x4,#264] - db4c: 540007e0 b.eq dc48 - db50: b40004a1 cbz x1, dbe4 - db54: 121f7802 and w2, w0, #0xfffffffe - db58: 12000003 and w3, w0, #0x1 - db5c: 6b00005f cmp w2, w0 - db60: b9000023 str w3, [x1] - db64: 54000260 b.eq dbb0 - db68: b9001ba0 str w0, [x29,#24] - db6c: 91042083 add x3, x4, #0x108 - db70: b9401ba6 ldr w6, [x29,#24] - db74: 885ffc67 ldaxr w7, [x3] - db78: 6b0600ff cmp w7, w6 - db7c: 54000061 b.ne db88 - db80: 88087c62 stxr w8, w2, [x3] - db84: 35ffff88 cbnz w8, db74 - db88: 540001a1 b.ne dbbc - db8c: b9401ba6 ldr w6, [x29,#24] - db90: b90017a6 str w6, [x29,#20] - db94: b94017a6 ldr w6, [x29,#20] - db98: 6b06001f cmp w0, w6 - db9c: 54000ac1 b.ne dcf4 - dba0: 12800880 mov w0, #0xffffffbb // #-69 - dba4: 0a000042 and w2, w2, w0 - dba8: 7100285f cmp w2, #0xa - dbac: 54000340 b.eq dc14 - dbb0: 52800000 mov w0, #0x0 // #0 - dbb4: a8c27bfd ldp x29, x30, [sp],#32 - dbb8: d65f03c0 ret - dbbc: b9001ba7 str w7, [x29,#24] - dbc0: 17fffff3 b db8c - dbc4: 54000040 b.eq dbcc - dbc8: b9001ba6 str w6, [x29,#24] - dbcc: b9401ba1 ldr w1, [x29,#24] - dbd0: b90017a1 str w1, [x29,#20] - dbd4: b94017a1 ldr w1, [x29,#20] - dbd8: 6b01001f cmp w0, w1 - dbdc: 54fffe20 b.eq dba0 - dbe0: 2a0103e0 mov w0, w1 - dbe4: 121f7802 and w2, w0, #0xfffffffe - dbe8: 6b02001f cmp w0, w2 - dbec: 54fffe20 b.eq dbb0 - dbf0: b9001ba0 str w0, [x29,#24] - dbf4: 91042083 add x3, x4, #0x108 - dbf8: b9401ba1 ldr w1, [x29,#24] - dbfc: 885ffc66 ldaxr w6, [x3] - dc00: 6b0100df cmp w6, w1 - dc04: 54fffe01 b.ne dbc4 - dc08: 88077c62 stxr w7, w2, [x3] - dc0c: 34fffdc7 cbz w7, dbc4 - dc10: 17fffffb b dbfc - dc14: d117a0a5 sub x5, x5, #0x5e8 - dc18: 910073a1 add x1, x29, #0x1c - dc1c: b94000a0 ldr w0, [x5] - dc20: b9001fa0 str w0, [x29,#28] - dc24: 321c0006 orr w6, w0, #0x10 - dc28: 885ffc62 ldaxr w2, [x3] - dc2c: 6b00005f cmp w2, w0 - dc30: 54000061 b.ne dc3c - dc34: 88077c66 stxr w7, w6, [x3] - dc38: 35ffff87 cbnz w7, dc28 - dc3c: 54000600 b.eq dcfc - dc40: b9000022 str w2, [x1] - dc44: 17fffff6 b dc1c - dc48: b40003e1 cbz x1, dcc4 - dc4c: 32000002 orr w2, w0, #0x1 - dc50: 12000003 and w3, w0, #0x1 - dc54: 6b02001f cmp w0, w2 - dc58: b9000023 str w3, [x1] - dc5c: 54fffaa0 b.eq dbb0 - dc60: b9001ba0 str w0, [x29,#24] - dc64: 91042083 add x3, x4, #0x108 - dc68: b9401ba6 ldr w6, [x29,#24] - dc6c: 885ffc67 ldaxr w7, [x3] - dc70: 6b0600ff cmp w7, w6 - dc74: 54000061 b.ne dc80 - dc78: 88087c62 stxr w8, w2, [x3] - dc7c: 35ffff88 cbnz w8, dc6c - dc80: 54000040 b.eq dc88 - dc84: b9001ba7 str w7, [x29,#24] - dc88: b9401ba6 ldr w6, [x29,#24] - dc8c: b90017a6 str w6, [x29,#20] - dc90: b94017a6 ldr w6, [x29,#20] - dc94: 6b06001f cmp w0, w6 - dc98: 54fff840 b.eq dba0 - dc9c: 2a0603e0 mov w0, w6 - dca0: 17ffffeb b dc4c - dca4: 54000040 b.eq dcac - dca8: b9001ba6 str w6, [x29,#24] - dcac: b9401ba1 ldr w1, [x29,#24] - dcb0: b90017a1 str w1, [x29,#20] - dcb4: b94017a1 ldr w1, [x29,#20] - dcb8: 6b01001f cmp w0, w1 - dcbc: 54fff720 b.eq dba0 - dcc0: 2a0103e0 mov w0, w1 - dcc4: 32000002 orr w2, w0, #0x1 - dcc8: 6b02001f cmp w0, w2 - dccc: 54fff720 b.eq dbb0 - dcd0: b9001ba0 str w0, [x29,#24] - dcd4: 91042083 add x3, x4, #0x108 - dcd8: b9401ba1 ldr w1, [x29,#24] - dcdc: 885ffc66 ldaxr w6, [x3] - dce0: 6b0100df cmp w6, w1 - dce4: 54fffe01 b.ne dca4 - dce8: 88077c62 stxr w7, w2, [x3] - dcec: 34fffdc7 cbz w7, dca4 - dcf0: 17fffffb b dcdc - dcf4: 2a0603e0 mov w0, w6 - dcf8: 17ffff97 b db54 - dcfc: f9408080 ldr x0, [x4,#256] - dd00: 94000601 bl f504 <__pthread_unwind> - -000000000000dd04 : - dd04: a9be7bfd stp x29, x30, [sp,#-32]! - dd08: 7100041f cmp w0, #0x1 - dd0c: 528002c0 mov w0, #0x16 // #22 - dd10: 910003fd mov x29, sp - dd14: 54000069 b.ls dd20 - dd18: a8c27bfd ldp x29, x30, [sp],#32 - dd1c: d65f03c0 ret - dd20: d53bd045 mrs x5, tpidr_el0 - dd24: d11bc0a4 sub x4, x5, #0x6f0 - dd28: b9410880 ldr w0, [x4,#264] - dd2c: 54000820 b.eq de30 - dd30: b40004a1 cbz x1, ddc4 - dd34: 121e7802 and w2, w0, #0xfffffffd - dd38: d3410403 ubfx x3, x0, #1, #1 - dd3c: 6b00005f cmp w2, w0 - dd40: b9000023 str w3, [x1] - dd44: 54000260 b.eq dd90 - dd48: b9001ba0 str w0, [x29,#24] - dd4c: 91042083 add x3, x4, #0x108 - dd50: b9401ba6 ldr w6, [x29,#24] - dd54: 885ffc67 ldaxr w7, [x3] - dd58: 6b0600ff cmp w7, w6 - dd5c: 54000061 b.ne dd68 - dd60: 88087c62 stxr w8, w2, [x3] - dd64: 35ffff88 cbnz w8, dd54 - dd68: 540001a1 b.ne dd9c - dd6c: b9401ba6 ldr w6, [x29,#24] - dd70: b90017a6 str w6, [x29,#20] - dd74: b94017a6 ldr w6, [x29,#20] - dd78: 6b06001f cmp w0, w6 - dd7c: 54000b01 b.ne dedc - dd80: 12800880 mov w0, #0xffffffbb // #-69 - dd84: 0a000042 and w2, w2, w0 - dd88: 7100285f cmp w2, #0xa - dd8c: 54000340 b.eq ddf4 - dd90: 52800000 mov w0, #0x0 // #0 - dd94: a8c27bfd ldp x29, x30, [sp],#32 - dd98: d65f03c0 ret - dd9c: b9001ba7 str w7, [x29,#24] - dda0: 17fffff3 b dd6c - dda4: 54000040 b.eq ddac - dda8: b9001ba6 str w6, [x29,#24] - ddac: b9401ba1 ldr w1, [x29,#24] - ddb0: b90017a1 str w1, [x29,#20] - ddb4: b94017a1 ldr w1, [x29,#20] - ddb8: 6b01001f cmp w0, w1 - ddbc: 54fffe20 b.eq dd80 - ddc0: 2a0103e0 mov w0, w1 - ddc4: 121e7802 and w2, w0, #0xfffffffd - ddc8: 6b02001f cmp w0, w2 - ddcc: 54fffe20 b.eq dd90 - ddd0: b9001ba0 str w0, [x29,#24] - ddd4: 91042083 add x3, x4, #0x108 - ddd8: b9401ba1 ldr w1, [x29,#24] - dddc: 885ffc66 ldaxr w6, [x3] - dde0: 6b0100df cmp w6, w1 - dde4: 54fffe01 b.ne dda4 - dde8: 88077c62 stxr w7, w2, [x3] - ddec: 34fffdc7 cbz w7, dda4 - ddf0: 17fffffb b dddc - ddf4: 92800000 mov x0, #0xffffffffffffffff // #-1 - ddf8: d117a0a5 sub x5, x5, #0x5e8 - ddfc: f9021480 str x0, [x4,#1064] - de00: 910073a1 add x1, x29, #0x1c - de04: b94000a0 ldr w0, [x5] - de08: b9001fa0 str w0, [x29,#28] - de0c: 321c0006 orr w6, w0, #0x10 - de10: 885ffc62 ldaxr w2, [x3] - de14: 6b00005f cmp w2, w0 - de18: 54000061 b.ne de24 - de1c: 88077c66 stxr w7, w6, [x3] - de20: 35ffff87 cbnz w7, de10 - de24: 54000600 b.eq dee4 - de28: b9000022 str w2, [x1] - de2c: 17fffff6 b de04 - de30: b40003e1 cbz x1, deac - de34: 321f0002 orr w2, w0, #0x2 - de38: d3410403 ubfx x3, x0, #1, #1 - de3c: 6b02001f cmp w0, w2 - de40: b9000023 str w3, [x1] - de44: 54fffa60 b.eq dd90 - de48: b9001ba0 str w0, [x29,#24] - de4c: 91042083 add x3, x4, #0x108 - de50: b9401ba6 ldr w6, [x29,#24] - de54: 885ffc67 ldaxr w7, [x3] - de58: 6b0600ff cmp w7, w6 - de5c: 54000061 b.ne de68 - de60: 88087c62 stxr w8, w2, [x3] - de64: 35ffff88 cbnz w8, de54 - de68: 54000040 b.eq de70 - de6c: b9001ba7 str w7, [x29,#24] - de70: b9401ba6 ldr w6, [x29,#24] - de74: b90017a6 str w6, [x29,#20] - de78: b94017a6 ldr w6, [x29,#20] - de7c: 6b06001f cmp w0, w6 - de80: 54fff800 b.eq dd80 - de84: 2a0603e0 mov w0, w6 - de88: 17ffffeb b de34 - de8c: 54000040 b.eq de94 - de90: b9001ba6 str w6, [x29,#24] - de94: b9401ba1 ldr w1, [x29,#24] - de98: b90017a1 str w1, [x29,#20] - de9c: b94017a1 ldr w1, [x29,#20] - dea0: 6b01001f cmp w0, w1 - dea4: 54fff6e0 b.eq dd80 - dea8: 2a0103e0 mov w0, w1 - deac: 321f0002 orr w2, w0, #0x2 - deb0: 6b02001f cmp w0, w2 - deb4: 54fff6e0 b.eq dd90 - deb8: b9001ba0 str w0, [x29,#24] - debc: 91042083 add x3, x4, #0x108 - dec0: b9401ba1 ldr w1, [x29,#24] - dec4: 885ffc66 ldaxr w6, [x3] - dec8: 6b0100df cmp w6, w1 - decc: 54fffe01 b.ne de8c - ded0: 88077c62 stxr w7, w2, [x3] - ded4: 34fffdc7 cbz w7, de8c - ded8: 17fffffb b dec4 - dedc: 2a0603e0 mov w0, w6 - dee0: 17ffff95 b dd34 - dee4: f9408080 ldr x0, [x4,#256] - dee8: 94000587 bl f504 <__pthread_unwind> - -000000000000deec : - deec: b900001f str wzr, [x0] - def0: d2801021 mov x1, #0x81 // #129 - def4: b2407be2 mov x2, #0x7fffffff // #2147483647 - def8: d2800003 mov x3, #0x0 // #0 - defc: d2800c48 mov x8, #0x62 // #98 - df00: d4000001 svc #0x0 - df04: d65f03c0 ret - -000000000000df08 <__pthread_once>: - df08: a9bb7bfd stp x29, x30, [sp,#-80]! - df0c: aa0003e4 mov x4, x0 - df10: aa0103e5 mov x5, x1 - df14: 910003fd mov x29, sp - df18: a90153f3 stp x19, x20, [sp,#16] - df1c: f90013f5 str x21, [sp,#32] - df20: f0000126 adrp x6, 34000 <__GI___pthread_keys+0x3d78> - df24: b9400083 ldr w3, [x4] - df28: d5033bbf dmb ish - df2c: 360800c3 tbz w3, #1, df44 <__pthread_once+0x3c> - df30: 52800000 mov w0, #0x0 // #0 - df34: f94013f5 ldr x21, [sp,#32] - df38: a94153f3 ldp x19, x20, [sp,#16] - df3c: a8c57bfd ldp x29, x30, [sp],#80 - df40: d65f03c0 ret - df44: 910143b5 add x21, x29, #0x50 - df48: f941c4c2 ldr x2, [x6,#904] - df4c: 2a0303e0 mov w0, w3 - df50: 32000042 orr w2, w2, #0x1 - df54: b81e0ea3 str w3, [x21,#-32]! - df58: 885ffc81 ldaxr w1, [x4] - df5c: 6b00003f cmp w1, w0 - df60: 54000061 b.ne df6c <__pthread_once+0x64> - df64: 88077c82 stxr w7, w2, [x4] - df68: 35ffff87 cbnz w7, df58 <__pthread_once+0x50> - df6c: 54000040 b.eq df74 <__pthread_once+0x6c> - df70: b90033a1 str w1, [x29,#48] - df74: b94033a0 ldr w0, [x29,#48] - df78: 6b00007f cmp w3, w0 - df7c: 54000401 b.ne dffc <__pthread_once+0xf4> - df80: 36000063 tbz w3, #0, df8c <__pthread_once+0x84> - df84: 6b03005f cmp w2, w3 - df88: 540002c0 b.eq dfe0 <__pthread_once+0xd8> - df8c: 90000001 adrp x1, d000 - df90: aa0403e2 mov x2, x4 - df94: aa0503f4 mov x20, x5 - df98: aa1503e0 mov x0, x21 - df9c: 913bb021 add x1, x1, #0xeec - dfa0: aa0403f3 mov x19, x4 - dfa4: 94000497 bl f200 <_pthread_cleanup_push> - dfa8: d63f0280 blr x20 - dfac: aa1503e0 mov x0, x21 - dfb0: 52800001 mov w1, #0x0 // #0 - dfb4: 9400049b bl f220 <_pthread_cleanup_pop> - dfb8: d5033bbf dmb ish - dfbc: 52800041 mov w1, #0x2 // #2 - dfc0: aa1303e0 mov x0, x19 - dfc4: b9000261 str w1, [x19] - dfc8: b2407be2 mov x2, #0x7fffffff // #2147483647 - dfcc: d2801021 mov x1, #0x81 // #129 - dfd0: d2800003 mov x3, #0x0 // #0 - dfd4: d2800c48 mov x8, #0x62 // #98 - dfd8: d4000001 svc #0x0 - dfdc: 17ffffd5 b df30 <__pthread_once+0x28> - dfe0: aa0403e0 mov x0, x4 - dfe4: d2801001 mov x1, #0x80 // #128 - dfe8: 93407c42 sxtw x2, w2 - dfec: d2800003 mov x3, #0x0 // #0 - dff0: d2800c48 mov x8, #0x62 // #98 - dff4: d4000001 svc #0x0 - dff8: 17ffffcb b df24 <__pthread_once+0x1c> - dffc: 2a0003e3 mov w3, w0 - e000: 17ffffcb b df2c <__pthread_once+0x24> - -000000000000e004 : - e004: b940d000 ldr w0, [x0,#208] - e008: 6b1f001f cmp w0, wzr - e00c: 540000ed b.le e028 - e010: 2a2003e2 mvn w2, w0 - e014: 52800000 mov w0, #0x0 // #0 - e018: 531d7042 lsl w2, w2, #3 - e01c: 321f0442 orr w2, w2, #0x6 - e020: b9000022 str w2, [x1] - e024: d65f03c0 ret - e028: 52800060 mov w0, #0x3 // #3 - e02c: d65f03c0 ret - -000000000000e030 : - e030: 37f80142 tbnz w2, #31, e058 - e034: 6b1f003f cmp w1, wzr - e038: 52801001 mov w1, #0x80 // #128 - e03c: 1a8113e1 csel w1, wzr, w1, ne - e040: b9000401 str w1, [x0,#4] - e044: 52800001 mov w1, #0x0 // #0 - e048: b9000002 str w2, [x0] - e04c: f900041f str xzr, [x0,#8] - e050: 2a0103e0 mov w0, w1 - e054: d65f03c0 ret - e058: d53bd040 mrs x0, tpidr_el0 - e05c: b0000102 adrp x2, 2f000 <__FRAME_END__+0x18e30> - e060: f947c442 ldr x2, [x2,#3976] - e064: 12800001 mov w1, #0xffffffff // #-1 - e068: 528002c3 mov w3, #0x16 // #22 - e06c: b8226803 str w3, [x0,x2] - e070: 2a0103e0 mov w0, w1 - e074: d65f03c0 ret - -000000000000e078 : - e078: 52800000 mov w0, #0x0 // #0 - e07c: d65f03c0 ret - -000000000000e080 <__where_is_shmfs>: - e080: d10a83ff sub sp, sp, #0x2a0 - e084: 90000020 adrp x0, 12000 <__pthread_current_priority+0xa8> - e088: 91348000 add x0, x0, #0xd20 - e08c: a9bb7bfd stp x29, x30, [sp,#-80]! - e090: 910003fd mov x29, sp - e094: a9025bf5 stp x21, x22, [sp,#32] - e098: 9101e3b5 add x21, x29, #0x78 - e09c: f90023f9 str x25, [sp,#64] - e0a0: aa1503e1 mov x1, x21 - e0a4: a90153f3 stp x19, x20, [sp,#16] - e0a8: a90363f7 stp x23, x24, [sp,#48] - e0ac: 97ffdc29 bl 5150 <__statfs@plt> - e0b0: 35000140 cbnz w0, e0d8 <__where_is_shmfs+0x58> - e0b4: f94002a1 ldr x1, [x21] - e0b8: d28b1ec0 mov x0, #0x58f6 // #22774 - e0bc: f2b0b080 movk x0, #0x8584, lsl #16 - e0c0: eb00003f cmp x1, x0 - e0c4: 54000b80 b.eq e234 <__where_is_shmfs+0x1b4> - e0c8: d2833280 mov x0, #0x1994 // #6548 - e0cc: f2a02040 movk x0, #0x102, lsl #16 - e0d0: eb00003f cmp x1, x0 - e0d4: 54000b00 b.eq e234 <__where_is_shmfs+0x1b4> - e0d8: 90000033 adrp x19, 12000 <__pthread_current_priority+0xa8> - e0dc: 90000020 adrp x0, 12000 <__pthread_current_priority+0xa8> - e0e0: 91336273 add x19, x19, #0xcd8 - e0e4: 91332000 add x0, x0, #0xcc8 - e0e8: aa1303e1 mov x1, x19 - e0ec: 97ffdc55 bl 5240 <__setmntent@plt> - e0f0: aa0003f6 mov x22, x0 - e0f4: b4000c00 cbz x0, e274 <__where_is_shmfs+0x1f4> - e0f8: 90000037 adrp x23, 12000 <__pthread_current_priority+0xa8> - e0fc: 910143b9 add x25, x29, #0x50 - e100: 9103c3b8 add x24, x29, #0xf0 - e104: 9133c2f7 add x23, x23, #0xcf0 - e108: aa1903e1 mov x1, x25 - e10c: aa1803e2 mov x2, x24 - e110: 52804003 mov w3, #0x200 // #512 - e114: aa1603e0 mov x0, x22 - e118: 97ffdc4e bl 5250 <__getmntent_r@plt> - e11c: aa0003f3 mov x19, x0 - e120: aa1703e1 mov x1, x23 - e124: b4000760 cbz x0, e210 <__where_is_shmfs+0x190> - e128: f9400a74 ldr x20, [x19,#16] - e12c: aa1403e0 mov x0, x20 - e130: 97ffdc24 bl 51c0 - e134: 34000180 cbz w0, e164 <__where_is_shmfs+0xe4> - e138: 39400283 ldrb w3, [x20] - e13c: 7101cc7f cmp w3, #0x73 - e140: 54fffe41 b.ne e108 <__where_is_shmfs+0x88> - e144: 39400680 ldrb w0, [x20,#1] - e148: 7101a01f cmp w0, #0x68 - e14c: 54fffde1 b.ne e108 <__where_is_shmfs+0x88> - e150: 39400a80 ldrb w0, [x20,#2] - e154: 7101b41f cmp w0, #0x6d - e158: 54fffd81 b.ne e108 <__where_is_shmfs+0x88> - e15c: 39400e80 ldrb w0, [x20,#3] - e160: 35fffd40 cbnz w0, e108 <__where_is_shmfs+0x88> - e164: f9400660 ldr x0, [x19,#8] - e168: aa1503e1 mov x1, x21 - e16c: 97ffdbf9 bl 5150 <__statfs@plt> - e170: d28b1ec3 mov x3, #0x58f6 // #22774 - e174: f2b0b083 movk x3, #0x8584, lsl #16 - e178: 35fffc80 cbnz w0, e108 <__where_is_shmfs+0x88> - e17c: f94002a1 ldr x1, [x21] - e180: d2833280 mov x0, #0x1994 // #6548 - e184: f2a02040 movk x0, #0x102, lsl #16 - e188: eb03003f cmp x1, x3 - e18c: 54000060 b.eq e198 <__where_is_shmfs+0x118> - e190: eb00003f cmp x1, x0 - e194: 54fffba1 b.ne e108 <__where_is_shmfs+0x88> - e198: f9400674 ldr x20, [x19,#8] - e19c: aa1403e0 mov x0, x20 - e1a0: 97ffdb78 bl 4f80 - e1a4: aa0003f3 mov x19, x0 - e1a8: b4fffb00 cbz x0, e108 <__where_is_shmfs+0x88> - e1ac: d0000135 adrp x21, 34000 <__GI___pthread_keys+0x3d78> - e1b0: 91001800 add x0, x0, #0x6 - e1b4: 97ffdbb3 bl 5080 - e1b8: aa0003f7 mov x23, x0 - e1bc: f901caa0 str x0, [x21,#912] - e1c0: b4000280 cbz x0, e210 <__where_is_shmfs+0x190> - e1c4: aa1403e1 mov x1, x20 - e1c8: aa1303e2 mov x2, x19 - e1cc: 97ffdc25 bl 5260 - e1d0: 385ff001 ldrb w1, [x0,#-1] - e1d4: 7100bc3f cmp w1, #0x2f - e1d8: 540004a0 b.eq e26c <__where_is_shmfs+0x1ec> - e1dc: 528005e1 mov w1, #0x2f // #47 - e1e0: 91000403 add x3, x0, #0x1 - e1e4: 39000001 strb w1, [x0] - e1e8: 90000022 adrp x2, 12000 <__pthread_current_priority+0xa8> - e1ec: aa0303e1 mov x1, x3 - e1f0: 9133e042 add x2, x2, #0xcf8 - e1f4: 910e42b5 add x21, x21, #0x390 - e1f8: b9400040 ldr w0, [x2] - e1fc: b9000060 str w0, [x3] - e200: 39401040 ldrb w0, [x2,#4] - e204: 38004c20 strb w0, [x1,#4]! - e208: cb170021 sub x1, x1, x23 - e20c: f90006a1 str x1, [x21,#8] - e210: aa1603e0 mov x0, x22 - e214: 97ffdba7 bl 50b0 <__endmntent@plt> - e218: a94153f3 ldp x19, x20, [sp,#16] - e21c: a9425bf5 ldp x21, x22, [sp,#32] - e220: a94363f7 ldp x23, x24, [sp,#48] - e224: f94023f9 ldr x25, [sp,#64] - e228: a8c57bfd ldp x29, x30, [sp],#80 - e22c: 910a83ff add sp, sp, #0x2a0 - e230: d65f03c0 ret - e234: d0000121 adrp x1, 34000 <__GI___pthread_keys+0x3d78> - e238: 90000020 adrp x0, 12000 <__pthread_current_priority+0xa8> - e23c: 910e4022 add x2, x1, #0x390 - e240: 91344000 add x0, x0, #0xd10 - e244: a94153f3 ldp x19, x20, [sp,#16] - e248: f901c820 str x0, [x1,#912] - e24c: d28001a0 mov x0, #0xd // #13 - e250: f9000440 str x0, [x2,#8] - e254: a9425bf5 ldp x21, x22, [sp,#32] - e258: a94363f7 ldp x23, x24, [sp,#48] - e25c: f94023f9 ldr x25, [sp,#64] - e260: a8c57bfd ldp x29, x30, [sp],#80 - e264: 910a83ff add sp, sp, #0x2a0 - e268: d65f03c0 ret - e26c: aa0003e3 mov x3, x0 - e270: 17ffffde b e1e8 <__where_is_shmfs+0x168> - e274: 90000020 adrp x0, 12000 <__pthread_current_priority+0xa8> - e278: aa1303e1 mov x1, x19 - e27c: 91338000 add x0, x0, #0xce0 - e280: 97ffdbf0 bl 5240 <__setmntent@plt> - e284: aa0003f6 mov x22, x0 - e288: b5fff380 cbnz x0, e0f8 <__where_is_shmfs+0x78> - e28c: 17ffffe3 b e218 <__where_is_shmfs+0x198> - -000000000000e290 : - e290: a9b17bfd stp x29, x30, [sp,#-240]! - e294: 910003fd mov x29, sp - e298: a90363f7 stp x23, x24, [sp,#48] - e29c: 9101c3b7 add x23, x29, #0x70 - e2a0: 2a0203f8 mov w24, w2 - e2a4: a9025bf5 stp x21, x22, [sp,#32] - e2a8: a9046bf9 stp x25, x26, [sp,#64] - e2ac: a90153f3 stp x19, x20, [sp,#16] - e2b0: a90573fb stp x27, x28, [sp,#80] - e2b4: aa0003f9 mov x25, x0 - e2b8: aa0103f6 mov x22, x1 - e2bc: 52800000 mov w0, #0x0 // #0 - e2c0: 2a0203e1 mov w1, w2 - e2c4: aa1703e2 mov x2, x23 - e2c8: aa0303f5 mov x21, x3 - e2cc: 97ffdbe9 bl 5270 <__fxstat64@plt> - e2d0: 35000860 cbnz w0, e3dc - e2d4: d0000133 adrp x19, 34000 <__GI___pthread_keys+0x3d78> - e2d8: b9006fa0 str w0, [x29,#108] - e2dc: 910b3263 add x3, x19, #0x2cc - e2e0: 52800020 mov w0, #0x1 // #1 - e2e4: 885ffc61 ldaxr w1, [x3] - e2e8: 6b1f003f cmp w1, wzr - e2ec: 54000061 b.ne e2f8 - e2f0: 88027c60 stxr w2, w0, [x3] - e2f4: 35ffff82 cbnz w2, e2e4 - e2f8: 540006a1 b.ne e3cc - e2fc: 9100fac5 add x5, x22, #0x3e - e300: 910003e0 mov x0, sp - e304: 927ceca5 and x5, x5, #0xfffffffffffffff0 - e308: aa1903e1 mov x1, x25 - e30c: cb25601f sub sp, x0, x5 - e310: aa1603e2 mov x2, x22 - e314: 910083e0 add x0, sp, #0x20 - e318: d000013b adrp x27, 34000 <__GI___pthread_keys+0x3d78> - e31c: 9000001a adrp x26, e000 <__pthread_once+0xf8> - e320: 910082dc add x28, x22, #0x20 - e324: 97ffdb0f bl 4f60 - e328: f9403ba3 ldr x3, [x29,#112] - e32c: 910003e0 mov x0, sp - e330: f90003e3 str x3, [sp] - e334: 910e8361 add x1, x27, #0x3a0 - e338: f9403fa3 ldr x3, [x29,#120] - e33c: 91139342 add x2, x26, #0x4e4 - e340: f90007e3 str x3, [sp,#8] - e344: 97ffdb3f bl 5040 - e348: b4000680 cbz x0, e418 - e34c: f9400000 ldr x0, [x0] - e350: d10006a1 sub x1, x21, #0x1 - e354: b1000c3f cmn x1, #0x3 - e358: 1a9f87e4 cset w4, ls - e35c: f9400c05 ldr x5, [x0,#24] - e360: b9401002 ldr w2, [x0,#16] - e364: eb0502bf cmp x21, x5 - e368: 1a9f07e1 cset w1, ne - e36c: 11000442 add w2, w2, #0x1 - e370: 0a010084 and w4, w4, w1 - e374: b9001002 str w2, [x0,#16] - e378: 910b3261 add x1, x19, #0x2cc - e37c: 52800002 mov w2, #0x0 // #0 - e380: 885f7c20 ldxr w0, [x1] - e384: 8803fc22 stlxr w3, w2, [x1] - e388: 35ffffc3 cbnz w3, e380 - e38c: 7100041f cmp w0, #0x1 - e390: 5400036c b.gt e3fc - e394: 340000a4 cbz w4, e3a8 - e398: aa1503e0 mov x0, x21 - e39c: d2800401 mov x1, #0x20 // #32 - e3a0: d2801ae8 mov x8, #0xd7 // #215 - e3a4: d4000001 svc #0x0 - e3a8: 910003bf mov sp, x29 - e3ac: aa0503e0 mov x0, x5 - e3b0: a94153f3 ldp x19, x20, [sp,#16] - e3b4: a9425bf5 ldp x21, x22, [sp,#32] - e3b8: a94363f7 ldp x23, x24, [sp,#48] - e3bc: a9446bf9 ldp x25, x26, [sp,#64] - e3c0: a94573fb ldp x27, x28, [sp,#80] - e3c4: a8cf7bfd ldp x29, x30, [sp],#240 - e3c8: d65f03c0 ret - e3cc: aa0303e0 mov x0, x3 - e3d0: b9006fa1 str w1, [x29,#108] - e3d4: 940004e5 bl f768 <__lll_lock_wait_private> - e3d8: 17ffffc9 b e2fc - e3dc: d10006a0 sub x0, x21, #0x1 - e3e0: d2800005 mov x5, #0x0 // #0 - e3e4: b1000c1f cmn x0, #0x3 - e3e8: 1a9f87e4 cset w4, ls - e3ec: eb0502bf cmp x21, x5 - e3f0: 1a9f07e1 cset w1, ne - e3f4: 0a010084 and w4, w4, w1 - e3f8: 17ffffe7 b e394 - e3fc: aa0103e0 mov x0, x1 - e400: d2800022 mov x2, #0x1 // #1 - e404: d2801021 mov x1, #0x81 // #129 - e408: d2800003 mov x3, #0x0 // #0 - e40c: d2800c48 mov x8, #0x62 // #98 - e410: d4000001 svc #0x0 - e414: 17ffffe0 b e394 - e418: aa1c03e0 mov x0, x28 - e41c: 97ffdb19 bl 5080 - e420: aa0003f4 mov x20, x0 - e424: b40002a0 cbz x0, e478 - e428: b40004d5 cbz x21, e4c0 - e42c: 3dc002e0 ldr q0, [x23] - e430: 52800023 mov w3, #0x1 // #1 - e434: 91008280 add x0, x20, #0x20 - e438: aa1903e1 mov x1, x25 - e43c: aa1603e2 mov x2, x22 - e440: f9000e95 str x21, [x20,#24] - e444: b9001283 str w3, [x20,#16] - e448: 3d800280 str q0, [x20] - e44c: 97ffdac5 bl 4f60 - e450: b10006bf cmn x21, #0x1 - e454: 54000220 b.eq e498 - e458: aa1403e0 mov x0, x20 - e45c: 910e8361 add x1, x27, #0x3a0 - e460: 91139342 add x2, x26, #0x4e4 - e464: 97ffdb17 bl 50c0 - e468: b4000180 cbz x0, e498 - e46c: aa1503e5 mov x5, x21 - e470: 52800004 mov w4, #0x0 // #0 - e474: 17ffffc1 b e378 - e478: d10006a0 sub x0, x21, #0x1 - e47c: aa1403e5 mov x5, x20 - e480: b1000c1f cmn x0, #0x3 - e484: 1a9f87e4 cset w4, ls - e488: eb1f02bf cmp x21, xzr - e48c: 1a9f07e1 cset w1, ne - e490: 0a010084 and w4, w4, w1 - e494: 17ffffb9 b e378 - e498: aa1403e0 mov x0, x20 - e49c: 97ffdb61 bl 5220 - e4a0: d10006a0 sub x0, x21, #0x1 - e4a4: d2800005 mov x5, #0x0 // #0 - e4a8: b1000c1f cmn x0, #0x3 - e4ac: 1a9f87e4 cset w4, ls - e4b0: eb0502bf cmp x21, x5 - e4b4: 1a9f07e1 cset w1, ne - e4b8: 0a010084 and w4, w4, w1 - e4bc: 17ffffaf b e378 - e4c0: aa1503e0 mov x0, x21 - e4c4: aa1503e5 mov x5, x21 - e4c8: d2800401 mov x1, #0x20 // #32 - e4cc: 52800062 mov w2, #0x3 // #3 - e4d0: 52800023 mov w3, #0x1 // #1 - e4d4: 2a1803e4 mov w4, w24 - e4d8: 97ffdb3e bl 51d0 - e4dc: aa0003f5 mov x21, x0 - e4e0: 17ffffd3 b e42c - -000000000000e4e4 <__sem_search>: - e4e4: f9400403 ldr x3, [x0,#8] - e4e8: f9400422 ldr x2, [x1,#8] - e4ec: eb02007f cmp x3, x2 - e4f0: 54000080 b.eq e500 <__sem_search+0x1c> - e4f4: 12800000 mov w0, #0xffffffff // #-1 - e4f8: 1a9f3400 csinc w0, w0, wzr, cc - e4fc: d65f03c0 ret - e500: f9400003 ldr x3, [x0] - e504: f9400022 ldr x2, [x1] - e508: eb02007f cmp x3, x2 - e50c: 54ffff41 b.ne e4f4 <__sem_search+0x10> - e510: 91008000 add x0, x0, #0x20 - e514: 91008021 add x1, x1, #0x20 - e518: 17ffdb2a b 51c0 - -000000000000e51c : - e51c: a9a87bfd stp x29, x30, [sp,#-384]! - e520: 910003fd mov x29, sp - e524: 6d0627e8 stp d8, d9, [sp,#96] - e528: a90153f3 stp x19, x20, [sp,#16] - e52c: a9046bf9 stp x25, x26, [sp,#64] - e530: a9025bf5 stp x21, x22, [sp,#32] - e534: a90363f7 stp x23, x24, [sp,#48] - e538: a90573fb stp x27, x28, [sp,#80] - e53c: fd003bea str d10, [sp,#112] - e540: aa0003f3 mov x19, x0 - e544: b90083a1 str w1, [x29,#128] - e548: d0000120 adrp x0, 34000 <__GI___pthread_keys+0x3d78> - e54c: f900aba2 str x2, [x29,#336] - e550: 910403a2 add x2, x29, #0x100 - e554: f900afa3 str x3, [x29,#344] - e558: d000013a adrp x26, 34000 <__GI___pthread_keys+0x3d78> - e55c: f900b3a4 str x4, [x29,#352] - e560: 910b3000 add x0, x0, #0x2cc - e564: f900b7a5 str x5, [x29,#360] - e568: 90000001 adrp x1, e000 <__pthread_once+0xf8> - e56c: f900bba6 str x6, [x29,#368] - e570: 91001000 add x0, x0, #0x4 - e574: f900bfa7 str x7, [x29,#376] - e578: 91020021 add x1, x1, #0x80 - e57c: 3d8037a0 str q0, [x29,#208] - e580: 3d803ba1 str q1, [x29,#224] - e584: 3d803fa2 str q2, [x29,#240] - e588: 3d800043 str q3, [x2] - e58c: 910443a2 add x2, x29, #0x110 - e590: 3d800044 str q4, [x2] - e594: 910483a2 add x2, x29, #0x120 - e598: 3d800045 str q5, [x2] - e59c: 9104c3a2 add x2, x29, #0x130 - e5a0: 3d800046 str q6, [x2] - e5a4: 910503a2 add x2, x29, #0x140 - e5a8: 3d800047 str q7, [x2] - e5ac: 97fffe57 bl df08 <__pthread_once> - e5b0: f941cb54 ldr x20, [x26,#912] - e5b4: b4001934 cbz x20, e8d8 - e5b8: 39400262 ldrb w2, [x19] - e5bc: 7100bc5f cmp w2, #0x2f - e5c0: 54000081 b.ne e5d0 - e5c4: 38401e62 ldrb w2, [x19,#1]! - e5c8: 7100bc5f cmp w2, #0x2f - e5cc: 54ffffc0 b.eq e5c4 - e5d0: 34000f62 cbz w2, e7bc - e5d4: aa1303e0 mov x0, x19 - e5d8: 97ffda6a bl 4f80 - e5dc: 91000400 add x0, x0, #0x1 - e5e0: 910e4342 add x2, x26, #0x390 - e5e4: aa1403e1 mov x1, x20 - e5e8: 9e67000a fmov d10, x0 - e5ec: f9400442 ldr x2, [x2,#8] - e5f0: 8b020003 add x3, x0, x2 - e5f4: 910003e0 mov x0, sp - e5f8: 91007863 add x3, x3, #0x1e - e5fc: 927cec63 and x3, x3, #0xfffffffffffffff0 - e600: cb23601f sub sp, x0, x3 - e604: 910003e0 mov x0, sp - e608: 9e670009 fmov d9, x0 - e60c: 97ffdb15 bl 5260 - e610: 9e660142 fmov x2, d10 - e614: aa1303e1 mov x1, x19 - e618: 97ffda52 bl 4f60 - e61c: b94083a0 ldr w0, [x29,#128] - e620: 121a0400 and w0, w0, #0xc0 - e624: 7103001f cmp w0, #0xc0 - e628: 54000540 b.eq e6d0 - e62c: b94083a0 ldr w0, [x29,#128] - e630: 12900861 mov w1, #0xffff7fbc // #-32836 - e634: 52900042 mov w2, #0x8002 // #32770 - e638: 0a010001 and w1, w0, w1 - e63c: 9e660120 fmov x0, d9 - e640: 2a020021 orr w1, w1, w2 - e644: 940007e7 bl 105e0 <__open> - e648: 3100041f cmn w0, #0x1 - e64c: 2a0003f5 mov w21, w0 - e650: 540002e0 b.eq e6ac - e654: 9e660141 fmov x1, d10 - e658: aa1303e0 mov x0, x19 - e65c: 2a1503e2 mov w2, w21 - e660: d2800003 mov x3, #0x0 // #0 - e664: 97ffff0b bl e290 - e668: aa0003f4 mov x20, x0 - e66c: b100069f cmn x20, #0x1 - e670: 93407ea0 sxtw x0, w21 - e674: 9a9f1294 csel x20, x20, xzr, ne - e678: d2800728 mov x8, #0x39 // #57 - e67c: d4000001 svc #0x0 - e680: aa1403e0 mov x0, x20 - e684: 910003bf mov sp, x29 - e688: 6d4627e8 ldp d8, d9, [sp,#96] - e68c: fd403bea ldr d10, [sp,#112] - e690: a94153f3 ldp x19, x20, [sp,#16] - e694: a9425bf5 ldp x21, x22, [sp,#32] - e698: a94363f7 ldp x23, x24, [sp,#48] - e69c: a9446bf9 ldp x25, x26, [sp,#64] - e6a0: a94573fb ldp x27, x28, [sp,#80] - e6a4: a8d87bfd ldp x29, x30, [sp],#384 - e6a8: d65f03c0 ret - e6ac: f94043a1 ldr x1, [x29,#128] - e6b0: d2800000 mov x0, #0x0 // #0 - e6b4: 3637fe81 tbz w1, #6, e684 - e6b8: d53bd041 mrs x1, tpidr_el0 - e6bc: b0000102 adrp x2, 2f000 <__FRAME_END__+0x18e30> - e6c0: f947c442 ldr x2, [x2,#3976] - e6c4: b8626821 ldr w1, [x1,x2] - e6c8: 7100083f cmp w1, #0x2 - e6cc: 54fffdc1 b.ne e684 - e6d0: 910603a0 add x0, x29, #0x180 - e6d4: f9004ba0 str x0, [x29,#144] - e6d8: f9004fa0 str x0, [x29,#152] - e6dc: 910543a0 add x0, x29, #0x150 - e6e0: b9415ba2 ldr w2, [x29,#344] - e6e4: f90053a0 str x0, [x29,#160] - e6e8: 12800fe0 mov w0, #0xffffff80 // #-128 - e6ec: b900afa0 str w0, [x29,#172] - e6f0: 128004e0 mov w0, #0xffffffd8 // #-40 - e6f4: b900aba0 str w0, [x29,#168] - e6f8: b94153bc ldr w28, [x29,#336] - e6fc: 37f80e02 tbnz w2, #31, e8bc - e700: 910e4340 add x0, x26, #0x390 - e704: b900b3a2 str w2, [x29,#176] - e708: 910003e3 mov x3, sp - e70c: f941cb41 ldr x1, [x26,#912] - e710: b900b7bf str wzr, [x29,#180] - e714: 52800655 mov w21, #0x32 // #50 - e718: f9400402 ldr x2, [x0,#8] - e71c: f9005fbf str xzr, [x29,#184] - e720: 91009440 add x0, x2, #0x25 - e724: b0000119 adrp x25, 2f000 <__FRAME_END__+0x18e30> - e728: f947c739 ldr x25, [x25,#3976] - e72c: 927cec00 and x0, x0, #0xfffffffffffffff0 - e730: cb20607f sub sp, x3, x0 - e734: 910003e0 mov x0, sp - e738: 910003f7 mov x23, sp - e73c: a90c7fbf stp xzr, xzr, [x29,#192] - e740: 97ffdac8 bl 5260 - e744: aa0003f4 mov x20, x0 - e748: 90000020 adrp x0, 12000 <__pthread_current_priority+0xa8> - e74c: d53bd041 mrs x1, tpidr_el0 - e750: 91340000 add x0, x0, #0xd00 - e754: 8b190039 add x25, x1, x25 - e758: b9400001 ldr w1, [x0] - e75c: 7940081b ldrh w27, [x0,#4] - e760: 39401818 ldrb w24, [x0,#6] - e764: 1e270028 fmov s8, w1 - e768: 1400000b b e794 - e76c: aa1703e0 mov x0, x23 - e770: 9400079c bl 105e0 <__open> - e774: 3100041f cmn w0, #0x1 - e778: 2a0003f6 mov w22, w0 - e77c: 540002e1 b.ne e7d8 - e780: b9400323 ldr w3, [x25] - e784: 7100447f cmp w3, #0x11 - e788: 54000161 b.ne e7b4 - e78c: 710006b5 subs w21, w21, #0x1 - e790: 54000860 b.eq e89c - e794: bd000288 str s8, [x20] - e798: aa1703e0 mov x0, x23 - e79c: 79000a9b strh w27, [x20,#4] - e7a0: 39001a98 strb w24, [x20,#6] - e7a4: 97ffdad3 bl 52f0 <__mktemp@plt> - e7a8: 52801841 mov w1, #0xc2 // #194 - e7ac: 2a1c03e2 mov w2, w28 - e7b0: b5fffde0 cbnz x0, e76c - e7b4: d2800000 mov x0, #0x0 // #0 - e7b8: 17ffffb3 b e684 - e7bc: d53bd041 mrs x1, tpidr_el0 - e7c0: b0000102 adrp x2, 2f000 <__FRAME_END__+0x18e30> - e7c4: f947c442 ldr x2, [x2,#3976] - e7c8: 528002c3 mov w3, #0x16 // #22 - e7cc: d2800000 mov x0, #0x0 // #0 - e7d0: b8226823 str w3, [x1,x2] - e7d4: 17ffffac b e684 - e7d8: b0000114 adrp x20, 2f000 <__FRAME_END__+0x18e30> - e7dc: f947c694 ldr x20, [x20,#3976] - e7e0: 2a0003f5 mov w21, w0 - e7e4: d53bd040 mrs x0, tpidr_el0 - e7e8: 9102c3bc add x28, x29, #0xb0 - e7ec: 8b140014 add x20, x0, x20 - e7f0: 14000004 b e800 - e7f4: b9400280 ldr w0, [x20] - e7f8: 7100101f cmp w0, #0x4 - e7fc: 54000581 b.ne e8ac - e800: 2a1603e0 mov w0, w22 - e804: aa1c03e1 mov x1, x28 - e808: d2800402 mov x2, #0x20 // #32 - e80c: 94000505 bl fc20 <__write> - e810: b100041f cmn x0, #0x1 - e814: aa0003f9 mov x25, x0 - e818: 54fffee0 b.eq e7f4 - e81c: f100801f cmp x0, #0x20 - e820: 54000461 b.ne e8ac - e824: d2800000 mov x0, #0x0 // #0 - e828: aa1903e1 mov x1, x25 - e82c: 52800062 mov w2, #0x3 // #3 - e830: 52800023 mov w3, #0x1 // #1 - e834: 2a1603e4 mov w4, w22 - e838: aa0003e5 mov x5, x0 - e83c: 97ffda65 bl 51d0 - e840: b100041f cmn x0, #0x1 - e844: aa0003f4 mov x20, x0 - e848: 54000340 b.eq e8b0 - e84c: 9e660121 fmov x1, d9 - e850: aa1703e0 mov x0, x23 - e854: 97ffdab3 bl 5320 - e858: 340004e0 cbz w0, e8f4 - e85c: aa1403e0 mov x0, x20 - e860: aa1903e1 mov x1, x25 - e864: 97ffda93 bl 52b0 - e868: f94043a0 ldr x0, [x29,#128] - e86c: 37380200 tbnz w0, #7, e8ac - e870: d53bd040 mrs x0, tpidr_el0 - e874: b0000101 adrp x1, 2f000 <__FRAME_END__+0x18e30> - e878: f947c421 ldr x1, [x1,#3976] - e87c: b8616800 ldr w0, [x0,x1] - e880: 7100441f cmp w0, #0x11 - e884: 54000141 b.ne e8ac - e888: aa1703e0 mov x0, x23 - e88c: 97ffdad1 bl 53d0 - e890: 2a1603e0 mov w0, w22 - e894: 9400051b bl fd00 <__close> - e898: 17ffff65 b e62c - e89c: 52800160 mov w0, #0xb // #11 - e8a0: b9000320 str w0, [x25] - e8a4: d2800000 mov x0, #0x0 // #0 - e8a8: 17ffff77 b e684 - e8ac: d2800014 mov x20, #0x0 // #0 - e8b0: aa1703e0 mov x0, x23 - e8b4: 97ffdac7 bl 53d0 - e8b8: 17ffff6d b e66c - e8bc: d53bd040 mrs x0, tpidr_el0 - e8c0: b0000101 adrp x1, 2f000 <__FRAME_END__+0x18e30> - e8c4: f947c421 ldr x1, [x1,#3976] - e8c8: 528002c2 mov w2, #0x16 // #22 - e8cc: b8216802 str w2, [x0,x1] - e8d0: d2800000 mov x0, #0x0 // #0 - e8d4: 17ffff6c b e684 - e8d8: d53bd041 mrs x1, tpidr_el0 - e8dc: b0000102 adrp x2, 2f000 <__FRAME_END__+0x18e30> - e8e0: f947c442 ldr x2, [x2,#3976] - e8e4: 528004c3 mov w3, #0x26 // #38 - e8e8: aa1403e0 mov x0, x20 - e8ec: b8226823 str w3, [x1,x2] - e8f0: 17ffff65 b e684 - e8f4: 9e660141 fmov x1, d10 - e8f8: aa1403e3 mov x3, x20 - e8fc: aa1303e0 mov x0, x19 - e900: 2a1603e2 mov w2, w22 - e904: 97fffe63 bl e290 - e908: aa0003f4 mov x20, x0 - e90c: 17ffffe9 b e8b0 - -000000000000e910 : - e910: d0000121 adrp x1, 34000 <__GI___pthread_keys+0x3d78> - e914: f9400000 ldr x0, [x0] - e918: 910b6023 add x3, x1, #0x2d8 - e91c: f9400c02 ldr x2, [x0,#24] - e920: f9416c21 ldr x1, [x1,#728] - e924: eb01005f cmp x2, x1 - e928: 54000040 b.eq e930 - e92c: d65f03c0 ret - e930: f9000460 str x0, [x3,#8] - e934: d65f03c0 ret - -000000000000e938 : - e938: a9bc7bfd stp x29, x30, [sp,#-64]! - e93c: 910003fd mov x29, sp - e940: a90153f3 stp x19, x20, [sp,#16] - e944: d0000133 adrp x19, 34000 <__GI___pthread_keys+0x3d78> - e948: a9025bf5 stp x21, x22, [sp,#32] - e94c: b9003fbf str wzr, [x29,#60] - e950: aa0003f5 mov x21, x0 - e954: 910b3261 add x1, x19, #0x2cc - e958: 52800020 mov w0, #0x1 // #1 - e95c: 885ffc22 ldaxr w2, [x1] - e960: 6b1f005f cmp w2, wzr - e964: 54000061 b.ne e970 - e968: 88037c20 stxr w3, w0, [x1] - e96c: 35ffff83 cbnz w3, e95c - e970: 540003c1 b.ne e9e8 - e974: d0000123 adrp x3, 34000 <__GI___pthread_keys+0x3d78> - e978: d0000122 adrp x2, 34000 <__GI___pthread_keys+0x3d78> - e97c: 910b6054 add x20, x2, #0x2d8 - e980: 90000001 adrp x1, e000 <__pthread_once+0xf8> - e984: 91244021 add x1, x1, #0x910 - e988: 910e8076 add x22, x3, #0x3a0 - e98c: f941d060 ldr x0, [x3,#928] - e990: f900069f str xzr, [x20,#8] - e994: f9016c55 str x21, [x2,#728] - e998: 97ffd98e bl 4fd0 - e99c: f9400680 ldr x0, [x20,#8] - e9a0: b40005a0 cbz x0, ea54 - e9a4: b9401002 ldr w2, [x0,#16] - e9a8: 52800015 mov w21, #0x0 // #0 - e9ac: 51000442 sub w2, w2, #0x1 - e9b0: b9001002 str w2, [x0,#16] - e9b4: 34000222 cbz w2, e9f8 - e9b8: 910b3261 add x1, x19, #0x2cc - e9bc: 52800002 mov w2, #0x0 // #0 - e9c0: 885f7c20 ldxr w0, [x1] - e9c4: 8803fc22 stlxr w3, w2, [x1] - e9c8: 35ffffc3 cbnz w3, e9c0 - e9cc: 7100041f cmp w0, #0x1 - e9d0: 540002cc b.gt ea28 - e9d4: 2a1503e0 mov w0, w21 - e9d8: a94153f3 ldp x19, x20, [sp,#16] - e9dc: a9425bf5 ldp x21, x22, [sp,#32] - e9e0: a8c47bfd ldp x29, x30, [sp],#64 - e9e4: d65f03c0 ret - e9e8: aa0103e0 mov x0, x1 - e9ec: b9003fa2 str w2, [x29,#60] - e9f0: 9400035e bl f768 <__lll_lock_wait_private> - e9f4: 17ffffe0 b e974 - e9f8: 90000002 adrp x2, e000 <__pthread_once+0xf8> - e9fc: aa1603e1 mov x1, x22 - ea00: 91139042 add x2, x2, #0x4e4 - ea04: 97ffd9d7 bl 5160 - ea08: f9400680 ldr x0, [x20,#8] - ea0c: d2800401 mov x1, #0x20 // #32 - ea10: f9400c00 ldr x0, [x0,#24] - ea14: 97ffda27 bl 52b0 - ea18: 2a0003f5 mov w21, w0 - ea1c: f9400680 ldr x0, [x20,#8] - ea20: 97ffda00 bl 5220 - ea24: 17ffffe5 b e9b8 - ea28: aa0103e0 mov x0, x1 - ea2c: d2800022 mov x2, #0x1 // #1 - ea30: d2801021 mov x1, #0x81 // #129 - ea34: d2800003 mov x3, #0x0 // #0 - ea38: d2800c48 mov x8, #0x62 // #98 - ea3c: d4000001 svc #0x0 - ea40: 2a1503e0 mov w0, w21 - ea44: a94153f3 ldp x19, x20, [sp,#16] - ea48: a9425bf5 ldp x21, x22, [sp,#32] - ea4c: a8c47bfd ldp x29, x30, [sp],#64 - ea50: d65f03c0 ret - ea54: d53bd040 mrs x0, tpidr_el0 - ea58: b0000101 adrp x1, 2f000 <__FRAME_END__+0x18e30> - ea5c: f947c421 ldr x1, [x1,#3976] - ea60: 528002c2 mov w2, #0x16 // #22 - ea64: 12800015 mov w21, #0xffffffff // #-1 - ea68: b8216802 str w2, [x0,x1] - ea6c: 17ffffd3 b e9b8 - -000000000000ea70 : - ea70: a9bc7bfd stp x29, x30, [sp,#-64]! - ea74: 90000001 adrp x1, e000 <__pthread_once+0xf8> - ea78: 910003fd mov x29, sp - ea7c: a90153f3 stp x19, x20, [sp,#16] - ea80: aa0003f3 mov x19, x0 - ea84: d0000120 adrp x0, 34000 <__GI___pthread_keys+0x3d78> - ea88: 91020021 add x1, x1, #0x80 - ea8c: f90013f5 str x21, [sp,#32] - ea90: d0000134 adrp x20, 34000 <__GI___pthread_keys+0x3d78> - ea94: 910b4000 add x0, x0, #0x2d0 - ea98: 97fffd1c bl df08 <__pthread_once> - ea9c: f941ca81 ldr x1, [x20,#912] - eaa0: b4000621 cbz x1, eb64 - eaa4: 39400260 ldrb w0, [x19] - eaa8: 7100bc1f cmp w0, #0x2f - eaac: 54000081 b.ne eabc - eab0: 38401e60 ldrb w0, [x19,#1]! - eab4: 7100bc1f cmp w0, #0x2f - eab8: 54ffffc0 b.eq eab0 - eabc: 34000460 cbz w0, eb48 - eac0: aa1303e0 mov x0, x19 - eac4: 910e4294 add x20, x20, #0x390 - eac8: f9001fa1 str x1, [x29,#56] - eacc: 97ffd92d bl 4f80 - ead0: aa0003f5 mov x21, x0 - ead4: f9400682 ldr x2, [x20,#8] - ead8: f9401fa1 ldr x1, [x29,#56] - eadc: 8b000043 add x3, x2, x0 - eae0: 910003e0 mov x0, sp - eae4: 91007c63 add x3, x3, #0x1f - eae8: 927cec63 and x3, x3, #0xfffffffffffffff0 - eaec: cb23601f sub sp, x0, x3 - eaf0: 910003e0 mov x0, sp - eaf4: 97ffd9db bl 5260 - eaf8: aa1303e1 mov x1, x19 - eafc: 910006a2 add x2, x21, #0x1 - eb00: 97ffd918 bl 4f60 - eb04: 910003e0 mov x0, sp - eb08: 97ffda32 bl 53d0 - eb0c: 37f800c0 tbnz w0, #31, eb24 - eb10: 910003bf mov sp, x29 - eb14: a94153f3 ldp x19, x20, [sp,#16] - eb18: f94013f5 ldr x21, [sp,#32] - eb1c: a8c47bfd ldp x29, x30, [sp],#64 - eb20: d65f03c0 ret - eb24: d53bd042 mrs x2, tpidr_el0 - eb28: b0000101 adrp x1, 2f000 <__FRAME_END__+0x18e30> - eb2c: f947c421 ldr x1, [x1,#3976] - eb30: b8616843 ldr w3, [x2,x1] - eb34: 7100047f cmp w3, #0x1 - eb38: 54fffec1 b.ne eb10 - eb3c: 528001a3 mov w3, #0xd // #13 - eb40: b8216843 str w3, [x2,x1] - eb44: 17fffff3 b eb10 - eb48: d53bd041 mrs x1, tpidr_el0 - eb4c: b0000102 adrp x2, 2f000 <__FRAME_END__+0x18e30> - eb50: f947c442 ldr x2, [x2,#3976] - eb54: 52800043 mov w3, #0x2 // #2 - eb58: 12800000 mov w0, #0xffffffff // #-1 - eb5c: b8226823 str w3, [x1,x2] - eb60: 17ffffec b eb10 - eb64: d53bd041 mrs x1, tpidr_el0 - eb68: b0000102 adrp x2, 2f000 <__FRAME_END__+0x18e30> - eb6c: f947c442 ldr x2, [x2,#3976] - eb70: 528004c3 mov w3, #0x26 // #38 - eb74: 12800000 mov w0, #0xffffffff // #-1 - eb78: b8226823 str w3, [x1,x2] - eb7c: 17ffffe5 b eb10 - -000000000000eb80 : - eb80: b9400002 ldr w2, [x0] - eb84: 52800000 mov w0, #0x0 // #0 - eb88: b9000022 str w2, [x1] - eb8c: d65f03c0 ret - -000000000000eb90 <__sem_wait_cleanup>: - eb90: 91002000 add x0, x0, #0x8 - eb94: c85ffc01 ldaxr x1, [x0] - eb98: d1000421 sub x1, x1, #0x1 - eb9c: c8027c01 stxr w2, x1, [x0] - eba0: 35ffffa2 cbnz w2, eb94 <__sem_wait_cleanup+0x4> - eba4: d65f03c0 ret - -000000000000eba8 : - eba8: a9be7bfd stp x29, x30, [sp,#-32]! - ebac: 910003fd mov x29, sp - ebb0: f9000bf3 str x19, [sp,#16] - ebb4: aa0003f3 mov x19, x0 - ebb8: 94000298 bl f618 <__pthread_enable_asynccancel> - ebbc: 2a0003e4 mov w4, w0 - ebc0: d2800002 mov x2, #0x0 // #0 - ebc4: aa1303e0 mov x0, x19 - ebc8: b9800661 ldrsw x1, [x19,#4] - ebcc: aa0203e3 mov x3, x2 - ebd0: d2800c48 mov x8, #0x62 // #98 - ebd4: d4000001 svc #0x0 - ebd8: aa0003e1 mov x1, x0 - ebdc: 2a0403e0 mov w0, w4 - ebe0: b13ffc3f cmn x1, #0xfff - ebe4: 1a813053 csel w19, w2, w1, cc - ebe8: 940002bc bl f6d8 <__pthread_disable_asynccancel> - ebec: 2a1303e0 mov w0, w19 - ebf0: f9400bf3 ldr x19, [sp,#16] - ebf4: a8c27bfd ldp x29, x30, [sp],#32 - ebf8: d65f03c0 ret - -000000000000ebfc : - ebfc: a9ba7bfd stp x29, x30, [sp,#-96]! - ec00: 910003fd mov x29, sp - ec04: b9400001 ldr w1, [x0] - ec08: a90153f3 stp x19, x20, [sp,#16] - ec0c: f90013f5 str x21, [sp,#32] - ec10: 910103b4 add x20, x29, #0x40 - ec14: 51000423 sub w3, w1, #0x1 - ec18: 2a0103e2 mov w2, w1 - ec1c: 34000241 cbz w1, ec64 - ec20: b90043a1 str w1, [x29,#64] - ec24: 885ffc01 ldaxr w1, [x0] - ec28: 6b02003f cmp w1, w2 - ec2c: 54000061 b.ne ec38 - ec30: 88047c03 stxr w4, w3, [x0] - ec34: 35ffff84 cbnz w4, ec24 - ec38: 540000c1 b.ne ec50 - ec3c: 52800000 mov w0, #0x0 // #0 - ec40: f94013f5 ldr x21, [sp,#32] - ec44: a94153f3 ldp x19, x20, [sp,#16] - ec48: a8c67bfd ldp x29, x30, [sp],#96 - ec4c: d65f03c0 ret - ec50: b9000281 str w1, [x20] - ec54: b9400001 ldr w1, [x0] - ec58: 51000423 sub w3, w1, #0x1 - ec5c: 2a0103e2 mov w2, w1 - ec60: 35fffe01 cbnz w1, ec20 - ec64: aa0003f3 mov x19, x0 - ec68: 91002015 add x21, x0, #0x8 - ec6c: c85ffea0 ldaxr x0, [x21] - ec70: 91000400 add x0, x0, #0x1 - ec74: c8017ea0 stxr w1, x0, [x21] - ec78: 35ffffa1 cbnz w1, ec6c - ec7c: 90000001 adrp x1, e000 <__pthread_once+0xf8> - ec80: aa1403e0 mov x0, x20 - ec84: 912e4021 add x1, x1, #0xb90 - ec88: aa1303e2 mov x2, x19 - ec8c: 9400015d bl f200 <_pthread_cleanup_push> - ec90: aa1303e0 mov x0, x19 - ec94: 97ffffc5 bl eba8 - ec98: 31002c1f cmn w0, #0xb - ec9c: 54000040 b.eq eca4 - eca0: 35000360 cbnz w0, ed0c - eca4: b9400261 ldr w1, [x19] - eca8: 51000423 sub w3, w1, #0x1 - ecac: 2a0103e2 mov w2, w1 - ecb0: 34ffff01 cbz w1, ec90 - ecb4: b9003fa1 str w1, [x29,#60] - ecb8: 885ffe61 ldaxr w1, [x19] - ecbc: 6b02003f cmp w1, w2 - ecc0: 54000061 b.ne eccc - ecc4: 88007e63 stxr w0, w3, [x19] - ecc8: 35ffff80 cbnz w0, ecb8 - eccc: 54000060 b.eq ecd8 - ecd0: b9003fa1 str w1, [x29,#60] - ecd4: 17fffff4 b eca4 - ecd8: 52800013 mov w19, #0x0 // #0 - ecdc: aa1403e0 mov x0, x20 - ece0: 52800001 mov w1, #0x0 // #0 - ece4: 9400014f bl f220 <_pthread_cleanup_pop> - ece8: c85ffea0 ldaxr x0, [x21] - ecec: d1000400 sub x0, x0, #0x1 - ecf0: c8017ea0 stxr w1, x0, [x21] - ecf4: 35ffffa1 cbnz w1, ece8 - ecf8: 2a1303e0 mov w0, w19 - ecfc: f94013f5 ldr x21, [sp,#32] - ed00: a94153f3 ldp x19, x20, [sp,#16] - ed04: a8c67bfd ldp x29, x30, [sp],#96 - ed08: d65f03c0 ret - ed0c: 4b0003e1 neg w1, w0 - ed10: b0000102 adrp x2, 2f000 <__FRAME_END__+0x18e30> - ed14: f947c442 ldr x2, [x2,#3976] - ed18: d53bd040 mrs x0, tpidr_el0 - ed1c: 12800013 mov w19, #0xffffffff // #-1 - ed20: b8226801 str w1, [x0,x2] - ed24: 17ffffee b ecdc - -000000000000ed28 : - ed28: b9400001 ldr w1, [x0] - ed2c: d10043ff sub sp, sp, #0x10 - ed30: 6b1f003f cmp w1, wzr - ed34: 540001ed b.le ed70 - ed38: b9000fe1 str w1, [sp,#12] - ed3c: 51000422 sub w2, w1, #0x1 - ed40: 885ffc03 ldaxr w3, [x0] - ed44: 6b01007f cmp w3, w1 - ed48: 54000061 b.ne ed54 - ed4c: 88047c02 stxr w4, w2, [x0] - ed50: 35ffff84 cbnz w4, ed40 - ed54: 54000081 b.ne ed64 - ed58: 52800000 mov w0, #0x0 // #0 - ed5c: 910043ff add sp, sp, #0x10 - ed60: d65f03c0 ret - ed64: b9400001 ldr w1, [x0] - ed68: 6b1f003f cmp w1, wzr - ed6c: 54fffe6c b.gt ed38 - ed70: d53bd041 mrs x1, tpidr_el0 - ed74: b0000102 adrp x2, 2f000 <__FRAME_END__+0x18e30> - ed78: f947c442 ldr x2, [x2,#3976] - ed7c: 12800000 mov w0, #0xffffffff // #-1 - ed80: 52800163 mov w3, #0xb // #11 - ed84: 910043ff add sp, sp, #0x10 - ed88: b8226823 str w3, [x1,x2] - ed8c: d65f03c0 ret - -000000000000ed90 : - ed90: a9bd7bfd stp x29, x30, [sp,#-48]! - ed94: 910003fd mov x29, sp - ed98: f9000bf3 str x19, [sp,#16] - ed9c: aa0003f3 mov x19, x0 - eda0: f90017a1 str x1, [x29,#40] - eda4: 9400021d bl f618 <__pthread_enable_asynccancel> - eda8: b9800661 ldrsw x1, [x19,#4] - edac: 2a0003e4 mov w4, w0 - edb0: d2800002 mov x2, #0x0 // #0 - edb4: aa1303e0 mov x0, x19 - edb8: f94017a3 ldr x3, [x29,#40] - edbc: d2800c48 mov x8, #0x62 // #98 - edc0: d4000001 svc #0x0 - edc4: aa0003e1 mov x1, x0 - edc8: 2a0403e0 mov w0, w4 - edcc: b13ffc3f cmn x1, #0xfff - edd0: 1a813053 csel w19, w2, w1, cc - edd4: 94000241 bl f6d8 <__pthread_disable_asynccancel> - edd8: 2a1303e0 mov w0, w19 - eddc: f9400bf3 ldr x19, [sp,#16] - ede0: a8c37bfd ldp x29, x30, [sp],#48 - ede4: d65f03c0 ret - -000000000000ede8 : - ede8: a9b67bfd stp x29, x30, [sp,#-160]! - edec: 910003fd mov x29, sp - edf0: b9400002 ldr w2, [x0] - edf4: a90153f3 stp x19, x20, [sp,#16] - edf8: a9025bf5 stp x21, x22, [sp,#32] - edfc: a90363f7 stp x23, x24, [sp,#48] - ee00: f90023f9 str x25, [sp,#64] - ee04: 51000444 sub w4, w2, #0x1 - ee08: 2a0203e3 mov w3, w2 - ee0c: 34000282 cbz w2, ee5c - ee10: b90083a2 str w2, [x29,#128] - ee14: 885ffc02 ldaxr w2, [x0] - ee18: 6b03005f cmp w2, w3 - ee1c: 54000061 b.ne ee28 - ee20: 88057c04 stxr w5, w4, [x0] - ee24: 35ffff85 cbnz w5, ee14 - ee28: 54000101 b.ne ee48 - ee2c: 52800000 mov w0, #0x0 // #0 - ee30: a94153f3 ldp x19, x20, [sp,#16] - ee34: a9425bf5 ldp x21, x22, [sp,#32] - ee38: a94363f7 ldp x23, x24, [sp,#48] - ee3c: f94023f9 ldr x25, [sp,#64] - ee40: a8ca7bfd ldp x29, x30, [sp],#160 - ee44: d65f03c0 ret - ee48: b90083a2 str w2, [x29,#128] - ee4c: b9400002 ldr w2, [x0] - ee50: 51000444 sub w4, w2, #0x1 - ee54: 2a0203e3 mov w3, w2 - ee58: 35fffdc2 cbnz w2, ee10 - ee5c: f9400423 ldr x3, [x1,#8] - ee60: d2993fe2 mov x2, #0xc9ff // #51711 - ee64: f2a77342 movk x2, #0x3b9a, lsl #16 - ee68: eb02007f cmp x3, x2 - ee6c: 54000aa8 b.hi efc0 - ee70: aa0103f4 mov x20, x1 - ee74: aa0003f3 mov x19, x0 - ee78: 91002017 add x23, x0, #0x8 - ee7c: c85ffee0 ldaxr x0, [x23] - ee80: 91000400 add x0, x0, #0x1 - ee84: c8017ee0 stxr w1, x0, [x23] - ee88: 35ffffa1 cbnz w1, ee7c - ee8c: 910203b8 add x24, x29, #0x80 - ee90: 90000001 adrp x1, e000 <__pthread_once+0xf8> - ee94: aa1803e0 mov x0, x24 - ee98: 912e4021 add x1, x1, #0xb90 - ee9c: aa1303e2 mov x2, x19 - eea0: 910183b6 add x22, x29, #0x60 - eea4: 12807cf5 mov w21, #0xfffffc18 // #-1000 - eea8: 9101c3b9 add x25, x29, #0x70 - eeac: 940000d5 bl f200 <_pthread_cleanup_push> - eeb0: aa1603e0 mov x0, x22 - eeb4: d2800001 mov x1, #0x0 // #0 - eeb8: 97ffd842 bl 4fc0 <__gettimeofday@plt> - eebc: f9400682 ldr x2, [x20,#8] - eec0: f94037a3 ldr x3, [x29,#104] - eec4: f9400284 ldr x4, [x20] - eec8: 1b030aa3 madd w3, w21, w3, w2 - eecc: f94033a2 ldr x2, [x29,#96] - eed0: 4b020084 sub w4, w4, w2 - eed4: 37f80323 tbnz w3, #31, ef38 - eed8: 37f803a4 tbnz w4, #31, ef4c - eedc: 93407c84 sxtw x4, w4 - eee0: 93407c63 sxtw x3, w3 - eee4: aa1303e0 mov x0, x19 - eee8: aa1903e1 mov x1, x25 - eeec: f9003ba4 str x4, [x29,#112] - eef0: f9003fa3 str x3, [x29,#120] - eef4: 97ffffa7 bl ed90 - eef8: 31002c1f cmn w0, #0xb - eefc: 54000040 b.eq ef04 - ef00: 35000520 cbnz w0, efa4 - ef04: b9400263 ldr w3, [x19] - ef08: 51000460 sub w0, w3, #0x1 - ef0c: 2a0303e2 mov w2, w3 - ef10: 34fffd03 cbz w3, eeb0 - ef14: b9005fa3 str w3, [x29,#92] - ef18: 885ffe61 ldaxr w1, [x19] - ef1c: 6b02003f cmp w1, w2 - ef20: 54000061 b.ne ef2c - ef24: 88037e60 stxr w3, w0, [x19] - ef28: 35ffff83 cbnz w3, ef18 - ef2c: 540001e0 b.eq ef68 - ef30: b9005fa1 str w1, [x29,#92] - ef34: 17fffff4 b ef04 - ef38: 52994000 mov w0, #0xca00 // #51712 - ef3c: 51000484 sub w4, w4, #0x1 - ef40: 72a77340 movk w0, #0x3b9a, lsl #16 - ef44: 0b000063 add w3, w3, w0 - ef48: 36fffca4 tbz w4, #31, eedc - ef4c: d53bd040 mrs x0, tpidr_el0 - ef50: b0000101 adrp x1, 2f000 <__FRAME_END__+0x18e30> - ef54: f947c421 ldr x1, [x1,#3976] - ef58: 52800dc2 mov w2, #0x6e // #110 - ef5c: 12800013 mov w19, #0xffffffff // #-1 - ef60: b8216802 str w2, [x0,x1] - ef64: 14000002 b ef6c - ef68: 52800013 mov w19, #0x0 // #0 - ef6c: aa1803e0 mov x0, x24 - ef70: 52800001 mov w1, #0x0 // #0 - ef74: 940000ab bl f220 <_pthread_cleanup_pop> - ef78: c85ffee0 ldaxr x0, [x23] - ef7c: d1000400 sub x0, x0, #0x1 - ef80: c8017ee0 stxr w1, x0, [x23] - ef84: 35ffffa1 cbnz w1, ef78 - ef88: 2a1303e0 mov w0, w19 - ef8c: f94023f9 ldr x25, [sp,#64] - ef90: a94153f3 ldp x19, x20, [sp,#16] - ef94: a9425bf5 ldp x21, x22, [sp,#32] - ef98: a94363f7 ldp x23, x24, [sp,#48] - ef9c: a8ca7bfd ldp x29, x30, [sp],#160 - efa0: d65f03c0 ret - efa4: 4b0003e1 neg w1, w0 - efa8: b0000102 adrp x2, 2f000 <__FRAME_END__+0x18e30> - efac: f947c442 ldr x2, [x2,#3976] - efb0: d53bd040 mrs x0, tpidr_el0 - efb4: 12800013 mov w19, #0xffffffff // #-1 - efb8: b8226801 str w1, [x0,x2] - efbc: 17ffffec b ef6c - efc0: d53bd041 mrs x1, tpidr_el0 - efc4: b0000102 adrp x2, 2f000 <__FRAME_END__+0x18e30> - efc8: f947c442 ldr x2, [x2,#3976] - efcc: 528002c3 mov w3, #0x16 // #22 - efd0: 12800000 mov w0, #0xffffffff // #-1 - efd4: b8226823 str w3, [x1,x2] - efd8: 17ffff96 b ee30 - -000000000000efdc : - efdc: d10043ff sub sp, sp, #0x10 - efe0: 12b00004 mov w4, #0x7fffffff // #2147483647 - efe4: b9400001 ldr w1, [x0] - efe8: 6b04003f cmp w1, w4 - efec: 11000423 add w3, w1, #0x1 - eff0: 2a0103e2 mov w2, w1 - eff4: 540002c0 b.eq f04c - eff8: b9000fe1 str w1, [sp,#12] - effc: 885f7c01 ldxr w1, [x0] - f000: 6b02003f cmp w1, w2 - f004: 54000061 b.ne f010 - f008: 8805fc03 stlxr w5, w3, [x0] - f00c: 35ffff85 cbnz w5, effc - f010: 54fffea1 b.ne efe4 - f014: d5033bbf dmb ish - f018: f9400401 ldr x1, [x0,#8] - f01c: b4000141 cbz x1, f044 - f020: b9400401 ldr w1, [x0,#4] - f024: d2800022 mov x2, #0x1 // #1 - f028: d2800003 mov x3, #0x0 // #0 - f02c: d2800c48 mov x8, #0x62 // #98 - f030: 52000021 eor w1, w1, #0x1 - f034: 93407c21 sxtw x1, w1 - f038: d4000001 svc #0x0 - f03c: b140041f cmn x0, #0x1, lsl #12 - f040: 54000168 b.hi f06c - f044: 52800000 mov w0, #0x0 // #0 - f048: 14000007 b f064 - f04c: d53bd041 mrs x1, tpidr_el0 - f050: 90000102 adrp x2, 2f000 <__FRAME_END__+0x18e30> - f054: f947c442 ldr x2, [x2,#3976] - f058: 52800963 mov w3, #0x4b // #75 - f05c: 12800000 mov w0, #0xffffffff // #-1 - f060: b8226823 str w3, [x1,x2] - f064: 910043ff add sp, sp, #0x10 - f068: d65f03c0 ret - f06c: d53bd042 mrs x2, tpidr_el0 - f070: 90000103 adrp x3, 2f000 <__FRAME_END__+0x18e30> - f074: f947c463 ldr x3, [x3,#3976] - f078: 4b0003e1 neg w1, w0 - f07c: 12800000 mov w0, #0xffffffff // #-1 - f080: b8236841 str w1, [x2,x3] - f084: 17fffff8 b f064 - -000000000000f088 <__pthread_register_cancel>: - f088: d53bd041 mrs x1, tpidr_el0 - f08c: d11bc021 sub x1, x1, #0x6f0 - f090: f9408022 ldr x2, [x1,#256] - f094: f9005c02 str x2, [x0,#184] - f098: f9407c22 ldr x2, [x1,#248] - f09c: f9006002 str x2, [x0,#192] - f0a0: f9008020 str x0, [x1,#256] - f0a4: d65f03c0 ret - -000000000000f0a8 <__pthread_unregister_cancel>: - f0a8: f9405c01 ldr x1, [x0,#184] - f0ac: d53bd040 mrs x0, tpidr_el0 - f0b0: d11bc000 sub x0, x0, #0x6f0 - f0b4: f9008001 str x1, [x0,#256] - f0b8: d65f03c0 ret - -000000000000f0bc <__pthread_register_cancel_defer>: - f0bc: d53bd041 mrs x1, tpidr_el0 - f0c0: d10043ff sub sp, sp, #0x10 - f0c4: d11bc021 sub x1, x1, #0x6f0 - f0c8: f9408022 ldr x2, [x1,#256] - f0cc: f9005c02 str x2, [x0,#184] - f0d0: f9407c22 ldr x2, [x1,#248] - f0d4: f9006002 str x2, [x0,#192] - f0d8: b9410822 ldr w2, [x1,#264] - f0dc: 370800c2 tbnz w2, #1, f0f4 <__pthread_register_cancel_defer+0x38> - f0e0: d3410442 ubfx x2, x2, #1, #1 - f0e4: b900c802 str w2, [x0,#200] - f0e8: f9008020 str x0, [x1,#256] - f0ec: 910043ff add sp, sp, #0x10 - f0f0: d65f03c0 ret - f0f4: 91042023 add x3, x1, #0x108 - f0f8: 2a0203e4 mov w4, w2 - f0fc: 910033e7 add x7, sp, #0xc - f100: b9000fe2 str w2, [sp,#12] - f104: 121e7845 and w5, w2, #0xfffffffd - f108: 885ffc66 ldaxr w6, [x3] - f10c: 6b0200df cmp w6, w2 - f110: 54000061 b.ne f11c <__pthread_register_cancel_defer+0x60> - f114: 88087c65 stxr w8, w5, [x3] - f118: 35ffff88 cbnz w8, f108 <__pthread_register_cancel_defer+0x4c> - f11c: 54000040 b.eq f124 <__pthread_register_cancel_defer+0x68> - f120: b90000e6 str w6, [x7] - f124: b9400fe2 ldr w2, [sp,#12] - f128: 6b02009f cmp w4, w2 - f12c: 54fffda0 b.eq f0e0 <__pthread_register_cancel_defer+0x24> - f130: 2a0203e4 mov w4, w2 - f134: 17fffff3 b f100 <__pthread_register_cancel_defer+0x44> - -000000000000f138 <__pthread_unregister_cancel_restore>: - f138: d53bd042 mrs x2, tpidr_el0 - f13c: a9be7bfd stp x29, x30, [sp,#-32]! - f140: d11bc041 sub x1, x2, #0x6f0 - f144: 910003fd mov x29, sp - f148: f9405c03 ldr x3, [x0,#184] - f14c: f9008023 str x3, [x1,#256] - f150: b940c800 ldr w0, [x0,#200] - f154: 340002e0 cbz w0, f1b0 <__pthread_unregister_cancel_restore+0x78> - f158: b9410820 ldr w0, [x1,#264] - f15c: 370802a0 tbnz w0, #1, f1b0 <__pthread_unregister_cancel_restore+0x78> - f160: 91042024 add x4, x1, #0x108 - f164: 910073a7 add x7, x29, #0x1c - f168: b9001fa0 str w0, [x29,#28] - f16c: 321f0003 orr w3, w0, #0x2 - f170: 2a0003e5 mov w5, w0 - f174: 885ffc86 ldaxr w6, [x4] - f178: 6b0500df cmp w6, w5 - f17c: 54000061 b.ne f188 <__pthread_unregister_cancel_restore+0x50> - f180: 88087c83 stxr w8, w3, [x4] - f184: 35ffff88 cbnz w8, f174 <__pthread_unregister_cancel_restore+0x3c> - f188: 54000040 b.eq f190 <__pthread_unregister_cancel_restore+0x58> - f18c: b90000e6 str w6, [x7] - f190: b9401fa3 ldr w3, [x29,#28] - f194: 6b03001f cmp w0, w3 - f198: 540002c1 b.ne f1f0 <__pthread_unregister_cancel_restore+0xb8> - f19c: b9410823 ldr w3, [x1,#264] - f1a0: 128008c0 mov w0, #0xffffffb9 // #-71 - f1a4: 0a000060 and w0, w3, w0 - f1a8: 7100201f cmp w0, #0x8 - f1ac: 54000060 b.eq f1b8 <__pthread_unregister_cancel_restore+0x80> - f1b0: a8c27bfd ldp x29, x30, [sp],#32 - f1b4: d65f03c0 ret - f1b8: 92800000 mov x0, #0xffffffffffffffff // #-1 - f1bc: d117a042 sub x2, x2, #0x5e8 - f1c0: f9021420 str x0, [x1,#1064] - f1c4: b9400040 ldr w0, [x2] - f1c8: b9001fa0 str w0, [x29,#28] - f1cc: 321c0005 orr w5, w0, #0x10 - f1d0: 885ffc83 ldaxr w3, [x4] - f1d4: 6b00007f cmp w3, w0 - f1d8: 54000061 b.ne f1e4 <__pthread_unregister_cancel_restore+0xac> - f1dc: 88067c85 stxr w6, w5, [x4] - f1e0: 35ffff86 cbnz w6, f1d0 <__pthread_unregister_cancel_restore+0x98> - f1e4: 540000a0 b.eq f1f8 <__pthread_unregister_cancel_restore+0xc0> - f1e8: b90000e3 str w3, [x7] - f1ec: 17fffff6 b f1c4 <__pthread_unregister_cancel_restore+0x8c> - f1f0: 2a0303e0 mov w0, w3 - f1f4: 17ffffdd b f168 <__pthread_unregister_cancel_restore+0x30> - f1f8: f9408020 ldr x0, [x1,#256] - f1fc: 940000c2 bl f504 <__pthread_unwind> - -000000000000f200 <_pthread_cleanup_push>: - f200: d53bd043 mrs x3, tpidr_el0 - f204: f9000001 str x1, [x0] - f208: d11bc063 sub x3, x3, #0x6f0 - f20c: f9407c61 ldr x1, [x3,#248] - f210: f9000c01 str x1, [x0,#24] - f214: f9000402 str x2, [x0,#8] - f218: f9007c60 str x0, [x3,#248] - f21c: d65f03c0 ret - -000000000000f220 <_pthread_cleanup_pop>: - f220: d53bd042 mrs x2, tpidr_el0 - f224: a9bf7bfd stp x29, x30, [sp,#-16]! - f228: d11bc042 sub x2, x2, #0x6f0 - f22c: 910003fd mov x29, sp - f230: f9400c03 ldr x3, [x0,#24] - f234: f9007c43 str x3, [x2,#248] - f238: 34000081 cbz w1, f248 <_pthread_cleanup_pop+0x28> - f23c: f9400001 ldr x1, [x0] - f240: f9400400 ldr x0, [x0,#8] - f244: d63f0020 blr x1 - f248: a8c17bfd ldp x29, x30, [sp],#16 - f24c: d65f03c0 ret - -000000000000f250 <_pthread_cleanup_push_defer>: - f250: d53bd043 mrs x3, tpidr_el0 - f254: f9000001 str x1, [x0] - f258: d11bc063 sub x3, x3, #0x6f0 - f25c: d10043ff sub sp, sp, #0x10 - f260: f9407c64 ldr x4, [x3,#248] - f264: b9410861 ldr w1, [x3,#264] - f268: f9000402 str x2, [x0,#8] - f26c: f9000c04 str x4, [x0,#24] - f270: 370800c1 tbnz w1, #1, f288 <_pthread_cleanup_push_defer+0x38> - f274: d3410421 ubfx x1, x1, #1, #1 - f278: b9001001 str w1, [x0,#16] - f27c: f9007c60 str x0, [x3,#248] - f280: 910043ff add sp, sp, #0x10 - f284: d65f03c0 ret - f288: 91042062 add x2, x3, #0x108 - f28c: 2a0103e4 mov w4, w1 - f290: 910033e7 add x7, sp, #0xc - f294: b9000fe1 str w1, [sp,#12] - f298: 121e7825 and w5, w1, #0xfffffffd - f29c: 885ffc46 ldaxr w6, [x2] - f2a0: 6b0100df cmp w6, w1 - f2a4: 54000061 b.ne f2b0 <_pthread_cleanup_push_defer+0x60> - f2a8: 88087c45 stxr w8, w5, [x2] - f2ac: 35ffff88 cbnz w8, f29c <_pthread_cleanup_push_defer+0x4c> - f2b0: 54000040 b.eq f2b8 <_pthread_cleanup_push_defer+0x68> - f2b4: b90000e6 str w6, [x7] - f2b8: b9400fe1 ldr w1, [sp,#12] - f2bc: 6b01009f cmp w4, w1 - f2c0: 54fffda0 b.eq f274 <_pthread_cleanup_push_defer+0x24> - f2c4: 2a0103e4 mov w4, w1 - f2c8: 17fffff3 b f294 <_pthread_cleanup_push_defer+0x44> - -000000000000f2cc <_pthread_cleanup_pop_restore>: - f2cc: d53bd043 mrs x3, tpidr_el0 - f2d0: a9be7bfd stp x29, x30, [sp,#-32]! - f2d4: d11bc062 sub x2, x3, #0x6f0 - f2d8: 910003fd mov x29, sp - f2dc: f9400c05 ldr x5, [x0,#24] - f2e0: b9401004 ldr w4, [x0,#16] - f2e4: f9007c45 str x5, [x2,#248] - f2e8: 350000e4 cbnz w4, f304 <_pthread_cleanup_pop_restore+0x38> - f2ec: 34000081 cbz w1, f2fc <_pthread_cleanup_pop_restore+0x30> - f2f0: f9400001 ldr x1, [x0] - f2f4: f9400400 ldr x0, [x0,#8] - f2f8: d63f0020 blr x1 - f2fc: a8c27bfd ldp x29, x30, [sp],#32 - f300: d65f03c0 ret - f304: b9410844 ldr w4, [x2,#264] - f308: 370fff24 tbnz w4, #1, f2ec <_pthread_cleanup_pop_restore+0x20> - f30c: 91042046 add x6, x2, #0x108 - f310: 910073a9 add x9, x29, #0x1c - f314: b9001fa4 str w4, [x29,#28] - f318: 321f0085 orr w5, w4, #0x2 - f31c: 2a0403e7 mov w7, w4 - f320: 885ffcc8 ldaxr w8, [x6] - f324: 6b07011f cmp w8, w7 - f328: 54000061 b.ne f334 <_pthread_cleanup_pop_restore+0x68> - f32c: 880a7cc5 stxr w10, w5, [x6] - f330: 35ffff8a cbnz w10, f320 <_pthread_cleanup_pop_restore+0x54> - f334: 540002e1 b.ne f390 <_pthread_cleanup_pop_restore+0xc4> - f338: b9401fa5 ldr w5, [x29,#28] - f33c: 6b05009f cmp w4, w5 - f340: 540002c1 b.ne f398 <_pthread_cleanup_pop_restore+0xcc> - f344: b9410845 ldr w5, [x2,#264] - f348: 128008c4 mov w4, #0xffffffb9 // #-71 - f34c: 0a0400a4 and w4, w5, w4 - f350: 7100209f cmp w4, #0x8 - f354: 54fffcc1 b.ne f2ec <_pthread_cleanup_pop_restore+0x20> - f358: 92800000 mov x0, #0xffffffffffffffff // #-1 - f35c: d117a063 sub x3, x3, #0x5e8 - f360: f9021440 str x0, [x2,#1064] - f364: b9400060 ldr w0, [x3] - f368: b9001fa0 str w0, [x29,#28] - f36c: 321c0004 orr w4, w0, #0x10 - f370: 885ffcc1 ldaxr w1, [x6] - f374: 6b00003f cmp w1, w0 - f378: 54000061 b.ne f384 <_pthread_cleanup_pop_restore+0xb8> - f37c: 88057cc4 stxr w5, w4, [x6] - f380: 35ffff85 cbnz w5, f370 <_pthread_cleanup_pop_restore+0xa4> - f384: 540000e0 b.eq f3a0 <_pthread_cleanup_pop_restore+0xd4> - f388: b9000121 str w1, [x9] - f38c: 17fffff6 b f364 <_pthread_cleanup_pop_restore+0x98> - f390: b9000128 str w8, [x9] - f394: 17ffffe9 b f338 <_pthread_cleanup_pop_restore+0x6c> - f398: 2a0503e4 mov w4, w5 - f39c: 17ffffde b f314 <_pthread_cleanup_pop_restore+0x48> - f3a0: f9408040 ldr x0, [x2,#256] - f3a4: 94000058 bl f504 <__pthread_unwind> - -000000000000f3a8 : - f3a8: a9bf7bfd stp x29, x30, [sp,#-16]! - f3ac: f0000001 adrp x1, 12000 <__pthread_current_priority+0xa8> - f3b0: d2800040 mov x0, #0x2 // #2 - f3b4: 910003fd mov x29, sp - f3b8: 9134c021 add x1, x1, #0xd30 - f3bc: d28003c2 mov x2, #0x1e // #30 - f3c0: d2800808 mov x8, #0x40 // #64 - f3c4: d4000001 svc #0x0 - f3c8: 97ffd76a bl 5170 - -000000000000f3cc : - f3cc: a9ba7bfd stp x29, x30, [sp,#-96]! - f3d0: 910003fd mov x29, sp - f3d4: a90153f3 stp x19, x20, [sp,#16] - f3d8: d53bd054 mrs x20, tpidr_el0 - f3dc: f90023f9 str x25, [sp,#64] - f3e0: d11bc294 sub x20, x20, #0x6f0 - f3e4: a9025bf5 stp x21, x22, [sp,#32] - f3e8: a90363f7 stp x23, x24, [sp,#48] - f3ec: f9424a95 ldr x21, [x20,#1168] - f3f0: aa0503f7 mov x23, x5 - f3f4: f9424e82 ldr x2, [x20,#1176] - f3f8: f9407e93 ldr x19, [x20,#248] - f3fc: 8b0202b5 add x21, x21, x2 - f400: 362000a1 tbz w1, #4, f414 - f404: b5000333 cbnz x19, f468 - f408: aa1703e0 mov x0, x23 - f40c: 52800021 mov w1, #0x1 // #1 - f410: 97ffd7e4 bl 53a0 <__libc_longjmp@plt> - f414: aa0403e0 mov x0, x4 - f418: f9002fa4 str x4, [x29,#88] - f41c: 940009a2 bl 11aa4 <_Unwind_GetCFA> - f420: cb150000 sub x0, x0, x21 - f424: 90000102 adrp x2, 2f000 <__FRAME_END__+0x18e30> - f428: f94036e3 ldr x3, [x23,#104] - f42c: f9402fa4 ldr x4, [x29,#88] - f430: f947d042 ldr x2, [x2,#4000] - f434: f9400041 ldr x1, [x2] - f438: ca010061 eor x1, x3, x1 - f43c: cb150021 sub x1, x1, x21 - f440: eb01001f cmp x0, x1 - f444: 54fffe02 b.cs f404 - f448: b5000313 cbnz x19, f4a8 - f44c: 52800000 mov w0, #0x0 // #0 - f450: f94023f9 ldr x25, [sp,#64] - f454: a94153f3 ldp x19, x20, [sp,#16] - f458: a9425bf5 ldp x21, x22, [sp,#32] - f45c: a94363f7 ldp x23, x24, [sp,#48] - f460: a8c67bfd ldp x29, x30, [sp],#96 - f464: d65f03c0 ret - f468: aa0403e0 mov x0, x4 - f46c: f94062f5 ldr x21, [x23,#192] - f470: 9400098d bl 11aa4 <_Unwind_GetCFA> - f474: eb15027f cmp x19, x21 - f478: 54fffc80 b.eq f408 - f47c: f9400261 ldr x1, [x19] - f480: f9400660 ldr x0, [x19,#8] - f484: f9400e76 ldr x22, [x19,#24] - f488: d63f0020 blr x1 - f48c: aa1603f3 mov x19, x22 - f490: eb1502df cmp x22, x21 - f494: 54ffff41 b.ne f47c - f498: 52800020 mov w0, #0x1 // #1 - f49c: f9007e96 str x22, [x20,#248] - f4a0: 34fffd60 cbz w0, f44c - f4a4: 17ffffd9 b f408 - f4a8: aa0403e0 mov x0, x4 - f4ac: f94062f8 ldr x24, [x23,#192] - f4b0: 9400097d bl 11aa4 <_Unwind_GetCFA> - f4b4: eb18027f cmp x19, x24 - f4b8: 54fffca0 b.eq f44c - f4bc: cb150019 sub x25, x0, x21 - f4c0: cb150260 sub x0, x19, x21 - f4c4: eb00033f cmp x25, x0 - f4c8: 54fffc23 b.cc f44c - f4cc: f9400261 ldr x1, [x19] - f4d0: f9400660 ldr x0, [x19,#8] - f4d4: f9400e76 ldr x22, [x19,#24] - f4d8: d63f0020 blr x1 - f4dc: eb16031f cmp x24, x22 - f4e0: 540000e0 b.eq f4fc - f4e4: cb1502c1 sub x1, x22, x21 - f4e8: aa1603f3 mov x19, x22 - f4ec: eb19003f cmp x1, x25 - f4f0: 54fffee9 b.ls f4cc - f4f4: f9007e96 str x22, [x20,#248] - f4f8: 17ffffd5 b f44c - f4fc: 52800000 mov w0, #0x0 // #0 - f500: 17ffffe7 b f49c - -000000000000f504 <__pthread_unwind>: - f504: d53bd043 mrs x3, tpidr_el0 - f508: 90000001 adrp x1, f000 - f50c: a9bf7bfd stp x29, x30, [sp,#-16]! - f510: d11bc063 sub x3, x3, #0x6f0 - f514: 90000004 adrp x4, f000 - f518: 910003fd mov x29, sp - f51c: aa0003e2 mov x2, x0 - f520: 910ea084 add x4, x4, #0x3a8 - f524: 910f3021 add x1, x1, #0x3cc - f528: f902387f str xzr, [x3,#1136] - f52c: 9111c060 add x0, x3, #0x470 - f530: f9023c64 str x4, [x3,#1144] - f534: 94000943 bl 11a40 <_Unwind_ForcedUnwind> - f538: 97ffd70e bl 5170 - -000000000000f53c <__pthread_unwind_next>: - f53c: a9bf7bfd stp x29, x30, [sp,#-16]! - f540: 910003fd mov x29, sp - f544: f9405c00 ldr x0, [x0,#184] - f548: 97ffffef bl f504 <__pthread_unwind> - -000000000000f54c : - f54c: a9bf7bfd stp x29, x30, [sp,#-16]! - f550: 910003fd mov x29, sp - f554: 97ffd793 bl 53a0 <__libc_longjmp@plt> - -000000000000f558 <__GI___pthread_cleanup_upto>: - f558: a9bc7bfd stp x29, x30, [sp,#-64]! - f55c: 910003fd mov x29, sp - f560: a90363f7 stp x23, x24, [sp,#48] - f564: d53bd058 mrs x24, tpidr_el0 - f568: d11bc318 sub x24, x24, #0x6f0 - f56c: a90153f3 stp x19, x20, [sp,#16] - f570: a9025bf5 stp x21, x22, [sp,#32] - f574: f9424b14 ldr x20, [x24,#1168] - f578: f9424f02 ldr x2, [x24,#1176] - f57c: f9407f13 ldr x19, [x24,#248] - f580: 8b020294 add x20, x20, x2 - f584: cb140037 sub x23, x1, x20 - f588: b40003b3 cbz x19, f5fc <__GI___pthread_cleanup_upto+0xa4> - f58c: 90000116 adrp x22, 2f000 <__FRAME_END__+0x18e30> - f590: f9403403 ldr x3, [x0,#104] - f594: cb140262 sub x2, x19, x20 - f598: f947d2c1 ldr x1, [x22,#4000] - f59c: f9400021 ldr x1, [x1] - f5a0: ca010061 eor x1, x3, x1 - f5a4: cb140021 sub x1, x1, x20 - f5a8: eb01005f cmp x2, x1 - f5ac: 540002a2 b.cs f600 <__GI___pthread_cleanup_upto+0xa8> - f5b0: eb0202ff cmp x23, x2 - f5b4: aa0003f5 mov x21, x0 - f5b8: 54000163 b.cc f5e4 <__GI___pthread_cleanup_upto+0x8c> - f5bc: 14000010 b f5fc <__GI___pthread_cleanup_upto+0xa4> - f5c0: f947d2c2 ldr x2, [x22,#4000] - f5c4: f94036a4 ldr x4, [x21,#104] - f5c8: f9400042 ldr x2, [x2] - f5cc: ca020082 eor x2, x4, x2 - f5d0: cb140042 sub x2, x2, x20 - f5d4: eb02007f cmp x3, x2 - f5d8: 54000142 b.cs f600 <__GI___pthread_cleanup_upto+0xa8> - f5dc: eb0302ff cmp x23, x3 - f5e0: 540000e2 b.cs f5fc <__GI___pthread_cleanup_upto+0xa4> - f5e4: f9400262 ldr x2, [x19] - f5e8: f9400660 ldr x0, [x19,#8] - f5ec: d63f0040 blr x2 - f5f0: f9400e73 ldr x19, [x19,#24] - f5f4: cb140263 sub x3, x19, x20 - f5f8: b5fffe53 cbnz x19, f5c0 <__GI___pthread_cleanup_upto+0x68> - f5fc: d2800013 mov x19, #0x0 // #0 - f600: f9007f13 str x19, [x24,#248] - f604: a9425bf5 ldp x21, x22, [sp,#32] - f608: a94153f3 ldp x19, x20, [sp,#16] - f60c: a94363f7 ldp x23, x24, [sp,#48] - f610: a8c47bfd ldp x29, x30, [sp],#64 - f614: d65f03c0 ret - -000000000000f618 <__pthread_enable_asynccancel>: - f618: d53bd046 mrs x6, tpidr_el0 - f61c: d11bc0c5 sub x5, x6, #0x6f0 - f620: a9be7bfd stp x29, x30, [sp,#-32]! - f624: 910003fd mov x29, sp - f628: b94108a1 ldr w1, [x5,#264] - f62c: 321f0022 orr w2, w1, #0x2 - f630: 6b01005f cmp w2, w1 - f634: 540002e0 b.eq f690 <__pthread_enable_asynccancel+0x78> - f638: 910083a4 add x4, x29, #0x20 - f63c: 910420a3 add x3, x5, #0x108 - f640: 2a0103e0 mov w0, w1 - f644: b81fcc81 str w1, [x4,#-4]! - f648: 885ffc67 ldaxr w7, [x3] - f64c: 6b0000ff cmp w7, w0 - f650: 54000061 b.ne f65c <__pthread_enable_asynccancel+0x44> - f654: 88087c62 stxr w8, w2, [x3] - f658: 35ffff88 cbnz w8, f648 <__pthread_enable_asynccancel+0x30> - f65c: 54000040 b.eq f664 <__pthread_enable_asynccancel+0x4c> - f660: b9001fa7 str w7, [x29,#28] - f664: b9401fa0 ldr w0, [x29,#28] - f668: 6b00003f cmp w1, w0 - f66c: 540000e1 b.ne f688 <__pthread_enable_asynccancel+0x70> - f670: 12800881 mov w1, #0xffffffbb // #-69 - f674: 0a010042 and w2, w2, w1 - f678: 7100285f cmp w2, #0xa - f67c: 540000e0 b.eq f698 <__pthread_enable_asynccancel+0x80> - f680: a8c27bfd ldp x29, x30, [sp],#32 - f684: d65f03c0 ret - f688: 2a0003e1 mov w1, w0 - f68c: 17ffffe8 b f62c <__pthread_enable_asynccancel+0x14> - f690: 2a0103e0 mov w0, w1 - f694: 17fffffb b f680 <__pthread_enable_asynccancel+0x68> - f698: 92800000 mov x0, #0xffffffffffffffff // #-1 - f69c: d117a0c6 sub x6, x6, #0x5e8 - f6a0: f90214a0 str x0, [x5,#1064] - f6a4: b94000c0 ldr w0, [x6] - f6a8: b9001fa0 str w0, [x29,#28] - f6ac: 321c0002 orr w2, w0, #0x10 - f6b0: 885ffc61 ldaxr w1, [x3] - f6b4: 6b00003f cmp w1, w0 - f6b8: 54000061 b.ne f6c4 <__pthread_enable_asynccancel+0xac> - f6bc: 88077c62 stxr w7, w2, [x3] - f6c0: 35ffff87 cbnz w7, f6b0 <__pthread_enable_asynccancel+0x98> - f6c4: 54000060 b.eq f6d0 <__pthread_enable_asynccancel+0xb8> - f6c8: b9000081 str w1, [x4] - f6cc: 17fffff6 b f6a4 <__pthread_enable_asynccancel+0x8c> - f6d0: f94080a0 ldr x0, [x5,#256] - f6d4: 97ffff8c bl f504 <__pthread_unwind> - -000000000000f6d8 <__pthread_disable_asynccancel>: - f6d8: d10043ff sub sp, sp, #0x10 - f6dc: 370802a0 tbnz w0, #1, f730 <__pthread_disable_asynccancel+0x58> - f6e0: d53bd044 mrs x4, tpidr_el0 - f6e4: 910033e6 add x6, sp, #0xc - f6e8: d11bc084 sub x4, x4, #0x6f0 - f6ec: 91042085 add x5, x4, #0x108 - f6f0: b9410881 ldr w1, [x4,#264] - f6f4: b9000fe1 str w1, [sp,#12] - f6f8: 121e7822 and w2, w1, #0xfffffffd - f6fc: 2a0103e0 mov w0, w1 - f700: 885ffca3 ldaxr w3, [x5] - f704: 6b00007f cmp w3, w0 - f708: 54000061 b.ne f714 <__pthread_disable_asynccancel+0x3c> - f70c: 88077ca2 stxr w7, w2, [x5] - f710: 35ffff87 cbnz w7, f700 <__pthread_disable_asynccancel+0x28> - f714: 54000121 b.ne f738 <__pthread_disable_asynccancel+0x60> - f718: b9400fe0 ldr w0, [sp,#12] - f71c: 6b00003f cmp w1, w0 - f720: 54000201 b.ne f760 <__pthread_disable_asynccancel+0x88> - f724: 121e0440 and w0, w2, #0xc - f728: 7100101f cmp w0, #0x4 - f72c: 540000a0 b.eq f740 <__pthread_disable_asynccancel+0x68> - f730: 910043ff add sp, sp, #0x10 - f734: d65f03c0 ret - f738: b90000c3 str w3, [x6] - f73c: 17fffff7 b f718 <__pthread_disable_asynccancel+0x40> - f740: aa0503e0 mov x0, x5 - f744: d2801001 mov x1, #0x80 // #128 - f748: 93407c42 sxtw x2, w2 - f74c: d2800003 mov x3, #0x0 // #0 - f750: d2800c48 mov x8, #0x62 // #98 - f754: d4000001 svc #0x0 - f758: b9410882 ldr w2, [x4,#264] - f75c: 17fffff2 b f724 <__pthread_disable_asynccancel+0x4c> - f760: 2a0003e1 mov w1, w0 - f764: 17ffffe4 b f6f4 <__pthread_disable_asynccancel+0x1c> - -000000000000f768 <__lll_lock_wait_private>: - f768: b9400001 ldr w1, [x0] - f76c: aa0003e4 mov x4, x0 - f770: 7100083f cmp w1, #0x2 - f774: 540001c0 b.eq f7ac <__lll_lock_wait_private+0x44> - f778: 52800045 mov w5, #0x2 // #2 - f77c: 14000007 b f798 <__lll_lock_wait_private+0x30> - f780: aa0403e0 mov x0, x4 - f784: d2801001 mov x1, #0x80 // #128 - f788: d2800042 mov x2, #0x2 // #2 - f78c: d2800003 mov x3, #0x0 // #0 - f790: d2800c48 mov x8, #0x62 // #98 - f794: d4000001 svc #0x0 - f798: 885ffc80 ldaxr w0, [x4] - f79c: 88017c85 stxr w1, w5, [x4] - f7a0: 35ffffc1 cbnz w1, f798 <__lll_lock_wait_private+0x30> - f7a4: 35fffee0 cbnz w0, f780 <__lll_lock_wait_private+0x18> - f7a8: d65f03c0 ret - f7ac: d2801001 mov x1, #0x80 // #128 - f7b0: d2800042 mov x2, #0x2 // #2 - f7b4: d2800003 mov x3, #0x0 // #0 - f7b8: d2800c48 mov x8, #0x62 // #98 - f7bc: d4000001 svc #0x0 - f7c0: 17ffffee b f778 <__lll_lock_wait_private+0x10> - -000000000000f7c4 <__lll_lock_wait>: - f7c4: 2a0103e5 mov w5, w1 - f7c8: b9400001 ldr w1, [x0] - f7cc: aa0003e4 mov x4, x0 - f7d0: 7100083f cmp w1, #0x2 - f7d4: 54000200 b.eq f814 <__lll_lock_wait+0x50> - f7d8: 521900a5 eor w5, w5, #0x80 - f7dc: 52800046 mov w6, #0x2 // #2 - f7e0: 93407ca5 sxtw x5, w5 - f7e4: 14000007 b f800 <__lll_lock_wait+0x3c> - f7e8: aa0403e0 mov x0, x4 - f7ec: aa0503e1 mov x1, x5 - f7f0: d2800042 mov x2, #0x2 // #2 - f7f4: d2800003 mov x3, #0x0 // #0 - f7f8: d2800c48 mov x8, #0x62 // #98 - f7fc: d4000001 svc #0x0 - f800: 885ffc80 ldaxr w0, [x4] - f804: 88017c86 stxr w1, w6, [x4] - f808: 35ffffc1 cbnz w1, f800 <__lll_lock_wait+0x3c> - f80c: 35fffee0 cbnz w0, f7e8 <__lll_lock_wait+0x24> - f810: d65f03c0 ret - f814: 521900a1 eor w1, w5, #0x80 - f818: d2800042 mov x2, #0x2 // #2 - f81c: d2800003 mov x3, #0x0 // #0 - f820: d2800c48 mov x8, #0x62 // #98 - f824: 93407c21 sxtw x1, w1 - f828: d4000001 svc #0x0 - f82c: 17ffffeb b f7d8 <__lll_lock_wait+0x14> - -000000000000f830 <__lll_timedlock_wait>: - f830: a9ba7bfd stp x29, x30, [sp,#-96]! - f834: d2993fe3 mov x3, #0xc9ff // #51711 - f838: 910003fd mov x29, sp - f83c: f9400424 ldr x4, [x1,#8] - f840: f2a77343 movk x3, #0x3b9a, lsl #16 - f844: a90153f3 stp x19, x20, [sp,#16] - f848: a9025bf5 stp x21, x22, [sp,#32] - f84c: a90363f7 stp x23, x24, [sp,#48] - f850: eb03009f cmp x4, x3 - f854: aa0003f3 mov x19, x0 - f858: 528002c0 mov w0, #0x16 // #22 - f85c: 540000c9 b.ls f874 <__lll_timedlock_wait+0x44> - f860: a94153f3 ldp x19, x20, [sp,#16] - f864: a9425bf5 ldp x21, x22, [sp,#32] - f868: a94363f7 ldp x23, x24, [sp,#48] - f86c: a8c67bfd ldp x29, x30, [sp],#96 - f870: d65f03c0 ret - f874: 52190055 eor w21, w2, #0x80 - f878: aa0103f4 mov x20, x1 - f87c: 52800057 mov w23, #0x2 // #2 - f880: 910103b6 add x22, x29, #0x40 - f884: 910143b8 add x24, x29, #0x50 - f888: 93407eb5 sxtw x21, w21 - f88c: 14000009 b f8b0 <__lll_timedlock_wait+0x80> - f890: f9002fa2 str x2, [x29,#88] - f894: aa1303e0 mov x0, x19 - f898: aa1503e1 mov x1, x21 - f89c: b7f80405 tbnz x5, #63, f91c <__lll_timedlock_wait+0xec> - f8a0: d2800042 mov x2, #0x2 // #2 - f8a4: aa1803e3 mov x3, x24 - f8a8: d2800c48 mov x8, #0x62 // #98 - f8ac: d4000001 svc #0x0 - f8b0: 885ffe62 ldaxr w2, [x19] - f8b4: 88007e77 stxr w0, w23, [x19] - f8b8: 35ffffc0 cbnz w0, f8b0 <__lll_timedlock_wait+0x80> - f8bc: aa1603e0 mov x0, x22 - f8c0: d2800001 mov x1, #0x0 // #0 - f8c4: 34000382 cbz w2, f934 <__lll_timedlock_wait+0x104> - f8c8: 97ffd5be bl 4fc0 <__gettimeofday@plt> - f8cc: f94027a6 ldr x6, [x29,#72] - f8d0: f94023a2 ldr x2, [x29,#64] - f8d4: f9400285 ldr x5, [x20] - f8d8: cb0614c4 sub x4, x6, x6, lsl #5 - f8dc: f9400687 ldr x7, [x20,#8] - f8e0: d37ef484 lsl x4, x4, #2 - f8e4: cb0200a5 sub x5, x5, x2 - f8e8: cb060082 sub x2, x4, x6 - f8ec: f9002ba5 str x5, [x29,#80] - f8f0: ab020ce2 adds x2, x7, x2, lsl #3 - f8f4: 54fffce5 b.pl f890 <__lll_timedlock_wait+0x60> - f8f8: d2994001 mov x1, #0xca00 // #51712 - f8fc: d10004a5 sub x5, x5, #0x1 - f900: f2a77341 movk x1, #0x3b9a, lsl #16 - f904: f9002ba5 str x5, [x29,#80] - f908: 8b010042 add x2, x2, x1 - f90c: f9002fa2 str x2, [x29,#88] - f910: aa1303e0 mov x0, x19 - f914: aa1503e1 mov x1, x21 - f918: b6fffc45 tbz x5, #63, f8a0 <__lll_timedlock_wait+0x70> - f91c: 52800dc0 mov w0, #0x6e // #110 - f920: a94153f3 ldp x19, x20, [sp,#16] - f924: a9425bf5 ldp x21, x22, [sp,#32] - f928: a94363f7 ldp x23, x24, [sp,#48] - f92c: a8c67bfd ldp x29, x30, [sp],#96 - f930: d65f03c0 ret - f934: 2a0203e0 mov w0, w2 - f938: a94153f3 ldp x19, x20, [sp,#16] - f93c: a9425bf5 ldp x21, x22, [sp,#32] - f940: a94363f7 ldp x23, x24, [sp,#48] - f944: a8c67bfd ldp x29, x30, [sp],#96 - f948: d65f03c0 ret - -000000000000f94c <__lll_timedwait_tid>: - f94c: a9ba7bfd stp x29, x30, [sp,#-96]! - f950: d2993fe2 mov x2, #0xc9ff // #51711 - f954: 910003fd mov x29, sp - f958: f9400423 ldr x3, [x1,#8] - f95c: f2a77342 movk x2, #0x3b9a, lsl #16 - f960: a9025bf5 stp x21, x22, [sp,#32] - f964: a90153f3 stp x19, x20, [sp,#16] - f968: f9001bf7 str x23, [sp,#48] - f96c: eb02007f cmp x3, x2 - f970: aa0003f5 mov x21, x0 - f974: 528002c0 mov w0, #0x16 // #22 - f978: 540000c9 b.ls f990 <__lll_timedwait_tid+0x44> - f97c: a94153f3 ldp x19, x20, [sp,#16] - f980: a9425bf5 ldp x21, x22, [sp,#32] - f984: f9401bf7 ldr x23, [sp,#48] - f988: a8c67bfd ldp x29, x30, [sp],#96 - f98c: d65f03c0 ret - f990: b94002b3 ldr w19, [x21] - f994: aa0103f4 mov x20, x1 - f998: 910103b7 add x23, x29, #0x40 - f99c: 910143b6 add x22, x29, #0x50 - f9a0: 35000093 cbnz w19, f9b0 <__lll_timedwait_tid+0x64> - f9a4: 14000029 b fa48 <__lll_timedwait_tid+0xfc> - f9a8: b94002b3 ldr w19, [x21] - f9ac: 340004f3 cbz w19, fa48 <__lll_timedwait_tid+0xfc> - f9b0: d2800001 mov x1, #0x0 // #0 - f9b4: aa1703e0 mov x0, x23 - f9b8: 97ffd582 bl 4fc0 <__gettimeofday@plt> - f9bc: f94027a7 ldr x7, [x29,#72] - f9c0: f9400286 ldr x6, [x20] - f9c4: f9400682 ldr x2, [x20,#8] - f9c8: cb0714e5 sub x5, x7, x7, lsl #5 - f9cc: f94023a1 ldr x1, [x29,#64] - f9d0: d37ef4a5 lsl x5, x5, #2 - f9d4: cb0700a4 sub x4, x5, x7 - f9d8: cb0100c6 sub x6, x6, x1 - f9dc: f9002ba6 str x6, [x29,#80] - f9e0: ab040c44 adds x4, x2, x4, lsl #3 - f9e4: 54000264 b.mi fa30 <__lll_timedwait_tid+0xe4> - f9e8: f9002fa4 str x4, [x29,#88] - f9ec: aa1503e0 mov x0, x21 - f9f0: d2800001 mov x1, #0x0 // #0 - f9f4: 93407e62 sxtw x2, w19 - f9f8: aa1603e3 mov x3, x22 - f9fc: d2800c48 mov x8, #0x62 // #98 - fa00: b7f800c6 tbnz x6, #63, fa18 <__lll_timedwait_tid+0xcc> - fa04: d4000001 svc #0x0 - fa08: b140041f cmn x0, #0x1, lsl #12 - fa0c: 54fffce9 b.ls f9a8 <__lll_timedwait_tid+0x5c> - fa10: b101b81f cmn x0, #0x6e - fa14: 54fffca1 b.ne f9a8 <__lll_timedwait_tid+0x5c> - fa18: 52800dc0 mov w0, #0x6e // #110 - fa1c: f9401bf7 ldr x23, [sp,#48] - fa20: a94153f3 ldp x19, x20, [sp,#16] - fa24: a9425bf5 ldp x21, x22, [sp,#32] - fa28: a8c67bfd ldp x29, x30, [sp],#96 - fa2c: d65f03c0 ret - fa30: d2994001 mov x1, #0xca00 // #51712 - fa34: d10004c6 sub x6, x6, #0x1 - fa38: f2a77341 movk x1, #0x3b9a, lsl #16 - fa3c: f9002ba6 str x6, [x29,#80] - fa40: 8b010084 add x4, x4, x1 - fa44: 17ffffe9 b f9e8 <__lll_timedwait_tid+0x9c> - fa48: 52800000 mov w0, #0x0 // #0 - fa4c: 17ffffcc b f97c <__lll_timedwait_tid+0x30> - -000000000000fa50 <__lll_robust_lock_wait>: - fa50: d53bd042 mrs x2, tpidr_el0 - fa54: aa0003e4 mov x4, x0 - fa58: d11bc042 sub x2, x2, #0x6f0 - fa5c: b9400000 ldr w0, [x0] - fa60: d10043ff sub sp, sp, #0x10 - fa64: 2a0103e6 mov w6, w1 - fa68: b940d047 ldr w7, [x2,#208] - fa6c: 34000260 cbz w0, fab8 <__lll_robust_lock_wait+0x68> - fa70: 37f00380 tbnz w0, #30, fae0 <__lll_robust_lock_wait+0x90> - fa74: 32010002 orr w2, w0, #0x80000000 - fa78: 6b02001f cmp w0, w2 - fa7c: 54000100 b.eq fa9c <__lll_robust_lock_wait+0x4c> - fa80: b9000fe0 str w0, [sp,#12] - fa84: 885ffc81 ldaxr w1, [x4] - fa88: 6b00003f cmp w1, w0 - fa8c: 54000061 b.ne fa98 <__lll_robust_lock_wait+0x48> - fa90: 88037c82 stxr w3, w2, [x4] - fa94: 35ffff83 cbnz w3, fa84 <__lll_robust_lock_wait+0x34> - fa98: 54000101 b.ne fab8 <__lll_robust_lock_wait+0x68> - fa9c: 521900c5 eor w5, w6, #0x80 - faa0: aa0403e0 mov x0, x4 - faa4: 93407c42 sxtw x2, w2 - faa8: d2800003 mov x3, #0x0 // #0 - faac: 93407ca1 sxtw x1, w5 - fab0: d2800c48 mov x8, #0x62 // #98 - fab4: d4000001 svc #0x0 - fab8: b9000fff str wzr, [sp,#12] - fabc: 320100e0 orr w0, w7, #0x80000000 - fac0: 885ffc81 ldaxr w1, [x4] - fac4: 6b1f003f cmp w1, wzr - fac8: 54000061 b.ne fad4 <__lll_robust_lock_wait+0x84> - facc: 88027c80 stxr w2, w0, [x4] - fad0: 35ffff82 cbnz w2, fac0 <__lll_robust_lock_wait+0x70> - fad4: 540000a1 b.ne fae8 <__lll_robust_lock_wait+0x98> - fad8: b9400fe0 ldr w0, [sp,#12] - fadc: 35fffca0 cbnz w0, fa70 <__lll_robust_lock_wait+0x20> - fae0: 910043ff add sp, sp, #0x10 - fae4: d65f03c0 ret - fae8: b9000fe1 str w1, [sp,#12] - faec: b9400fe0 ldr w0, [sp,#12] - faf0: 35fffc00 cbnz w0, fa70 <__lll_robust_lock_wait+0x20> - faf4: 17fffffb b fae0 <__lll_robust_lock_wait+0x90> - -000000000000faf8 <__lll_robust_timedlock_wait>: - faf8: aa0103e6 mov x6, x1 - fafc: d2993fe5 mov x5, #0xc9ff // #51711 - fb00: f9400421 ldr x1, [x1,#8] - fb04: f2a77345 movk x5, #0x3b9a, lsl #16 - fb08: aa0003e7 mov x7, x0 - fb0c: d10043ff sub sp, sp, #0x10 - fb10: eb05003f cmp x1, x5 - fb14: 2a0203e9 mov w9, w2 - fb18: 528002c0 mov w0, #0x16 // #22 - fb1c: 54000069 b.ls fb28 <__lll_robust_timedlock_wait+0x30> - fb20: 910043ff add sp, sp, #0x10 - fb24: d65f03c0 ret - fb28: d53bd040 mrs x0, tpidr_el0 - fb2c: b94000e4 ldr w4, [x7] - fb30: d11bc000 sub x0, x0, #0x6f0 - fb34: b940d00a ldr w10, [x0,#208] - fb38: 340001c4 cbz w4, fb70 <__lll_robust_timedlock_wait+0x78> - fb3c: f94000c0 ldr x0, [x6] - fb40: b7f804a0 tbnz x0, #63, fbd4 <__lll_robust_timedlock_wait+0xdc> - fb44: 37f002a4 tbnz w4, #30, fb98 <__lll_robust_timedlock_wait+0xa0> - fb48: 32010082 orr w2, w4, #0x80000000 - fb4c: 6b02009f cmp w4, w2 - fb50: 54000280 b.eq fba0 <__lll_robust_timedlock_wait+0xa8> - fb54: b9000fe4 str w4, [sp,#12] - fb58: 885ffce0 ldaxr w0, [x7] - fb5c: 6b04001f cmp w0, w4 - fb60: 54000061 b.ne fb6c <__lll_robust_timedlock_wait+0x74> - fb64: 88017ce2 stxr w1, w2, [x7] - fb68: 35ffff81 cbnz w1, fb58 <__lll_robust_timedlock_wait+0x60> - fb6c: 540001a0 b.eq fba0 <__lll_robust_timedlock_wait+0xa8> - fb70: b9000fff str wzr, [sp,#12] - fb74: 32010140 orr w0, w10, #0x80000000 - fb78: 885ffce1 ldaxr w1, [x7] - fb7c: 6b1f003f cmp w1, wzr - fb80: 54000061 b.ne fb8c <__lll_robust_timedlock_wait+0x94> - fb84: 88027ce0 stxr w2, w0, [x7] - fb88: 35ffff82 cbnz w2, fb78 <__lll_robust_timedlock_wait+0x80> - fb8c: 54000201 b.ne fbcc <__lll_robust_timedlock_wait+0xd4> - fb90: b9400fe4 ldr w4, [sp,#12] - fb94: 35fffd84 cbnz w4, fb44 <__lll_robust_timedlock_wait+0x4c> - fb98: 2a0403e0 mov w0, w4 - fb9c: 17ffffe1 b fb20 <__lll_robust_timedlock_wait+0x28> - fba0: 52803121 mov w1, #0x189 // #393 - fba4: aa0703e0 mov x0, x7 - fba8: 4a010121 eor w1, w9, w1 - fbac: 93407c42 sxtw x2, w2 - fbb0: aa0603e3 mov x3, x6 - fbb4: d2800004 mov x4, #0x0 // #0 - fbb8: 93407c21 sxtw x1, w1 - fbbc: b2407fe5 mov x5, #0xffffffff // #4294967295 - fbc0: d2800c48 mov x8, #0x62 // #98 - fbc4: d4000001 svc #0x0 - fbc8: 17ffffea b fb70 <__lll_robust_timedlock_wait+0x78> - fbcc: b9000fe1 str w1, [sp,#12] - fbd0: 17fffff0 b fb90 <__lll_robust_timedlock_wait+0x98> - fbd4: 52800dc0 mov w0, #0x6e // #110 - fbd8: 17ffffd2 b fb20 <__lll_robust_timedlock_wait+0x28> - -000000000000fbdc <__fork>: - fbdc: 17ffd531 b 50a0 <__libc_fork@plt> - -000000000000fbe0 : - fbe0: 90000100 adrp x0, 2f000 <__FRAME_END__+0x18e30> - fbe4: f947d800 ldr x0, [x0,#4016] - fbe8: d65f03c0 ret - fbec: 00000000 .inst 0x00000000 ; undefined - -000000000000fbf0 <__write_nocancel>: - fbf0: d2800808 mov x8, #0x40 // #64 - fbf4: d4000001 svc #0x0 - fbf8: b13ffc1f cmn x0, #0xfff - fbfc: 54000042 b.cs fc04 <__write_nocancel+0x14> - fc00: d65f03c0 ret - fc04: 90000101 adrp x1, 2f000 <__FRAME_END__+0x18e30> - fc08: 4b0003e2 neg w2, w0 - fc0c: f947c421 ldr x1, [x1,#3976] - fc10: d53bd043 mrs x3, tpidr_el0 - fc14: 92800000 mov x0, #0xffffffffffffffff // #-1 - fc18: b8236822 str w2, [x1,x3] - fc1c: d65f03c0 ret - -000000000000fc20 <__write>: - fc20: b0000130 adrp x16, 34000 <__GI___pthread_keys+0x3d78> - fc24: b9432a10 ldr w16, [x16,#808] - fc28: 34fffe50 cbz w16, fbf0 <__write_nocancel> - fc2c: a9bc03fe stp x30, x0, [sp,#-64]! - fc30: a9010be1 stp x1, x2, [sp,#16] - fc34: 97fffe79 bl f618 <__pthread_enable_asynccancel> - fc38: aa0003f0 mov x16, x0 - fc3c: f94007e0 ldr x0, [sp,#8] - fc40: a9410be1 ldp x1, x2, [sp,#16] - fc44: d2800808 mov x8, #0x40 // #64 - fc48: d4000001 svc #0x0 - fc4c: f90007e0 str x0, [sp,#8] - fc50: aa1003e0 mov x0, x16 - fc54: 97fffea1 bl f6d8 <__pthread_disable_asynccancel> - fc58: a8c403fe ldp x30, x0, [sp],#64 - fc5c: 17ffffe7 b fbf8 <__write_nocancel+0x8> - -000000000000fc60 <__read_nocancel>: - fc60: d28007e8 mov x8, #0x3f // #63 - fc64: d4000001 svc #0x0 - fc68: b13ffc1f cmn x0, #0xfff - fc6c: 54000042 b.cs fc74 <__read_nocancel+0x14> - fc70: d65f03c0 ret - fc74: 90000101 adrp x1, 2f000 <__FRAME_END__+0x18e30> - fc78: 4b0003e2 neg w2, w0 - fc7c: f947c421 ldr x1, [x1,#3976] - fc80: d53bd043 mrs x3, tpidr_el0 - fc84: 92800000 mov x0, #0xffffffffffffffff // #-1 - fc88: b8236822 str w2, [x1,x3] - fc8c: d65f03c0 ret - -000000000000fc90 <__read>: - fc90: b0000130 adrp x16, 34000 <__GI___pthread_keys+0x3d78> - fc94: b9432a10 ldr w16, [x16,#808] - fc98: 34fffe50 cbz w16, fc60 <__read_nocancel> - fc9c: a9bc03fe stp x30, x0, [sp,#-64]! - fca0: a9010be1 stp x1, x2, [sp,#16] - fca4: 97fffe5d bl f618 <__pthread_enable_asynccancel> - fca8: aa0003f0 mov x16, x0 - fcac: f94007e0 ldr x0, [sp,#8] - fcb0: a9410be1 ldp x1, x2, [sp,#16] - fcb4: d28007e8 mov x8, #0x3f // #63 - fcb8: d4000001 svc #0x0 - fcbc: f90007e0 str x0, [sp,#8] - fcc0: aa1003e0 mov x0, x16 - fcc4: 97fffe85 bl f6d8 <__pthread_disable_asynccancel> - fcc8: a8c403fe ldp x30, x0, [sp],#64 - fccc: 17ffffe7 b fc68 <__read_nocancel+0x8> - -000000000000fcd0 <__close_nocancel>: - fcd0: d2800728 mov x8, #0x39 // #57 - fcd4: d4000001 svc #0x0 - fcd8: b13ffc1f cmn x0, #0xfff - fcdc: 54000042 b.cs fce4 <__close_nocancel+0x14> - fce0: d65f03c0 ret - fce4: 90000101 adrp x1, 2f000 <__FRAME_END__+0x18e30> - fce8: 4b0003e2 neg w2, w0 - fcec: f947c421 ldr x1, [x1,#3976] - fcf0: d53bd043 mrs x3, tpidr_el0 - fcf4: 92800000 mov x0, #0xffffffffffffffff // #-1 - fcf8: b8236822 str w2, [x1,x3] - fcfc: d65f03c0 ret - -000000000000fd00 <__close>: - fd00: b0000130 adrp x16, 34000 <__GI___pthread_keys+0x3d78> - fd04: b9432a10 ldr w16, [x16,#808] - fd08: 34fffe50 cbz w16, fcd0 <__close_nocancel> - fd0c: a9bc03fe stp x30, x0, [sp,#-64]! - fd10: 97fffe42 bl f618 <__pthread_enable_asynccancel> - fd14: aa0003f0 mov x16, x0 - fd18: f94007e0 ldr x0, [sp,#8] - fd1c: d2800728 mov x8, #0x39 // #57 - fd20: d4000001 svc #0x0 - fd24: f90007e0 str x0, [sp,#8] - fd28: aa1003e0 mov x0, x16 - fd2c: 97fffe6b bl f6d8 <__pthread_disable_asynccancel> - fd30: a8c403fe ldp x30, x0, [sp],#64 - fd34: 17ffffe9 b fcd8 <__close_nocancel+0x8> - fd38: d503201f nop - fd3c: d503201f nop - -000000000000fd40 <__fcntl_nocancel>: - fd40: d10383ff sub sp, sp, #0xe0 - fd44: 7100243f cmp w1, #0x9 - fd48: 93407c00 sxtw x0, w0 - fd4c: 3d800fe0 str q0, [sp,#48] - fd50: f9005fe3 str x3, [sp,#184] - fd54: 910383e3 add x3, sp, #0xe0 - fd58: f9000be3 str x3, [sp,#16] - fd5c: f9000fe3 str x3, [sp,#24] - fd60: 9102c3e3 add x3, sp, #0xb0 - fd64: f90013e3 str x3, [sp,#32] - fd68: 128005e3 mov w3, #0xffffffd0 // #-48 - fd6c: f9005be2 str x2, [sp,#176] - fd70: b9002be3 str w3, [sp,#40] - fd74: 12800fe3 mov w3, #0xffffff80 // #-128 - fd78: f90063e4 str x4, [sp,#192] - fd7c: f90067e5 str x5, [sp,#200] - fd80: f9006be6 str x6, [sp,#208] - fd84: f9006fe7 str x7, [sp,#216] - fd88: b9002fe3 str w3, [sp,#44] - fd8c: 3d8013e1 str q1, [sp,#64] - fd90: 3d8017e2 str q2, [sp,#80] - fd94: 3d801be3 str q3, [sp,#96] - fd98: 3d801fe4 str q4, [sp,#112] - fd9c: 3d8023e5 str q5, [sp,#128] - fda0: 3d8027e6 str q6, [sp,#144] - fda4: 3d802be7 str q7, [sp,#160] - fda8: 54000100 b.eq fdc8 <__fcntl_nocancel+0x88> - fdac: 93407c21 sxtw x1, w1 - fdb0: d2800328 mov x8, #0x19 // #25 - fdb4: d4000001 svc #0x0 - fdb8: b140041f cmn x0, #0x1, lsl #12 - fdbc: 540001e8 b.hi fdf8 <__fcntl_nocancel+0xb8> - fdc0: 910383ff add sp, sp, #0xe0 - fdc4: d65f03c0 ret - fdc8: d2800201 mov x1, #0x10 // #16 - fdcc: 910023e2 add x2, sp, #0x8 - fdd0: d2800328 mov x8, #0x19 // #25 - fdd4: d4000001 svc #0x0 - fdd8: 3140041f cmn w0, #0x1, lsl #12 - fddc: 540001c8 b.hi fe14 <__fcntl_nocancel+0xd4> - fde0: b9400be0 ldr w0, [sp,#8] - fde4: 7100081f cmp w0, #0x2 - fde8: b9400fe0 ldr w0, [sp,#12] - fdec: 54fffea1 b.ne fdc0 <__fcntl_nocancel+0x80> - fdf0: 4b0003e0 neg w0, w0 - fdf4: 17fffff3 b fdc0 <__fcntl_nocancel+0x80> - fdf8: d53bd041 mrs x1, tpidr_el0 - fdfc: 90000102 adrp x2, 2f000 <__FRAME_END__+0x18e30> - fe00: f947c442 ldr x2, [x2,#3976] - fe04: 4b0003e3 neg w3, w0 - fe08: 12800000 mov w0, #0xffffffff // #-1 - fe0c: b8226823 str w3, [x1,x2] - fe10: 17ffffec b fdc0 <__fcntl_nocancel+0x80> - fe14: d53bd042 mrs x2, tpidr_el0 - fe18: 90000103 adrp x3, 2f000 <__FRAME_END__+0x18e30> - fe1c: f947c463 ldr x3, [x3,#3976] - fe20: 4b0003e1 neg w1, w0 - fe24: 12800000 mov w0, #0xffffffff // #-1 - fe28: b8236841 str w1, [x2,x3] - fe2c: 17ffffe5 b fdc0 <__fcntl_nocancel+0x80> - -000000000000fe30 <__fcntl>: - fe30: a9af7bfd stp x29, x30, [sp,#-272]! - fe34: 71001c3f cmp w1, #0x7 - fe38: 910003fd mov x29, sp - fe3c: f9000bf3 str x19, [sp,#16] - fe40: 3d801ba0 str q0, [x29,#96] - fe44: f90077a3 str x3, [x29,#232] - fe48: 910443a3 add x3, x29, #0x110 - fe4c: f90023a3 str x3, [x29,#64] - fe50: f90027a3 str x3, [x29,#72] - fe54: 910383a3 add x3, x29, #0xe0 - fe58: f9002ba3 str x3, [x29,#80] - fe5c: 128005e3 mov w3, #0xffffffd0 // #-48 - fe60: f90073a2 str x2, [x29,#224] - fe64: b9005ba3 str w3, [x29,#88] - fe68: 12800fe3 mov w3, #0xffffff80 // #-128 - fe6c: f9007ba4 str x4, [x29,#240] - fe70: f9007fa5 str x5, [x29,#248] - fe74: f90083a6 str x6, [x29,#256] - fe78: f90087a7 str x7, [x29,#264] - fe7c: b9005fa3 str w3, [x29,#92] - fe80: 3d801fa1 str q1, [x29,#112] - fe84: 3d8023a2 str q2, [x29,#128] - fe88: 3d8027a3 str q3, [x29,#144] - fe8c: 3d802ba4 str q4, [x29,#160] - fe90: 3d802fa5 str q5, [x29,#176] - fe94: 3d8033a6 str q6, [x29,#192] - fe98: 3d8037a7 str q7, [x29,#208] - fe9c: 54000081 b.ne feac <__fcntl+0x7c> - fea0: b0000123 adrp x3, 34000 <__GI___pthread_keys+0x3d78> - fea4: b9432863 ldr w3, [x3,#808] - fea8: 350004c3 cbnz w3, ff40 <__fcntl+0x110> - feac: 7100243f cmp w1, #0x9 - feb0: 93407c00 sxtw x0, w0 - feb4: 54000160 b.eq fee0 <__fcntl+0xb0> - feb8: 93407c21 sxtw x1, w1 - febc: d2800328 mov x8, #0x19 // #25 - fec0: d4000001 svc #0x0 - fec4: b140041f cmn x0, #0x1, lsl #12 - fec8: 540002e8 b.hi ff24 <__fcntl+0xf4> - fecc: 2a0003f3 mov w19, w0 - fed0: 2a1303e0 mov w0, w19 - fed4: f9400bf3 ldr x19, [sp,#16] - fed8: a8d17bfd ldp x29, x30, [sp],#272 - fedc: d65f03c0 ret - fee0: d2800201 mov x1, #0x10 // #16 - fee4: 9100e3a2 add x2, x29, #0x38 - fee8: d2800328 mov x8, #0x19 // #25 - feec: d4000001 svc #0x0 - fef0: 3140041f cmn w0, #0x1, lsl #12 - fef4: 54000188 b.hi ff24 <__fcntl+0xf4> - fef8: b9403ba0 ldr w0, [x29,#56] - fefc: 7100081f cmp w0, #0x2 - ff00: 540000c0 b.eq ff18 <__fcntl+0xe8> - ff04: b9403fb3 ldr w19, [x29,#60] - ff08: 2a1303e0 mov w0, w19 - ff0c: f9400bf3 ldr x19, [sp,#16] - ff10: a8d17bfd ldp x29, x30, [sp],#272 - ff14: d65f03c0 ret - ff18: b9403fa0 ldr w0, [x29,#60] - ff1c: 4b0003f3 neg w19, w0 - ff20: 17ffffec b fed0 <__fcntl+0xa0> - ff24: d53bd041 mrs x1, tpidr_el0 - ff28: 90000102 adrp x2, 2f000 <__FRAME_END__+0x18e30> - ff2c: f947c442 ldr x2, [x2,#3976] - ff30: 4b0003e0 neg w0, w0 - ff34: 12800013 mov w19, #0xffffffff // #-1 - ff38: b8226820 str w0, [x1,x2] - ff3c: 17ffffe5 b fed0 <__fcntl+0xa0> - ff40: 2a0003f3 mov w19, w0 - ff44: f90017a2 str x2, [x29,#40] - ff48: 97fffdb4 bl f618 <__pthread_enable_asynccancel> - ff4c: 2a0003e3 mov w3, w0 - ff50: d28000e1 mov x1, #0x7 // #7 - ff54: 93407e60 sxtw x0, w19 - ff58: f94017a2 ldr x2, [x29,#40] - ff5c: d2800328 mov x8, #0x19 // #25 - ff60: d4000001 svc #0x0 - ff64: b140041f cmn x0, #0x1, lsl #12 - ff68: 540000a8 b.hi ff7c <__fcntl+0x14c> - ff6c: 2a0003f3 mov w19, w0 - ff70: 2a0303e0 mov w0, w3 - ff74: 97fffdd9 bl f6d8 <__pthread_disable_asynccancel> - ff78: 17ffffd6 b fed0 <__fcntl+0xa0> - ff7c: d53bd041 mrs x1, tpidr_el0 - ff80: 90000102 adrp x2, 2f000 <__FRAME_END__+0x18e30> - ff84: f947c442 ldr x2, [x2,#3976] - ff88: 4b0003e0 neg w0, w0 - ff8c: 12800013 mov w19, #0xffffffff // #-1 - ff90: b8226820 str w0, [x1,x2] - ff94: 17fffff7 b ff70 <__fcntl+0x140> - ... - -000000000000ffa0 <__accept_nocancel>: - ffa0: d2801948 mov x8, #0xca // #202 - ffa4: d4000001 svc #0x0 - ffa8: b13ffc1f cmn x0, #0xfff - ffac: 54000042 b.cs ffb4 <__accept_nocancel+0x14> - ffb0: d65f03c0 ret - ffb4: 90000101 adrp x1, 2f000 <__FRAME_END__+0x18e30> - ffb8: 4b0003e2 neg w2, w0 - ffbc: f947c421 ldr x1, [x1,#3976] - ffc0: d53bd043 mrs x3, tpidr_el0 - ffc4: 92800000 mov x0, #0xffffffffffffffff // #-1 - ffc8: b8236822 str w2, [x1,x3] - ffcc: d65f03c0 ret - -000000000000ffd0 : - ffd0: b0000130 adrp x16, 34000 <__GI___pthread_keys+0x3d78> - ffd4: b9432a10 ldr w16, [x16,#808] - ffd8: 34fffe50 cbz w16, ffa0 <__accept_nocancel> - ffdc: a9bc03fe stp x30, x0, [sp,#-64]! - ffe0: a9010be1 stp x1, x2, [sp,#16] - ffe4: 97fffd8d bl f618 <__pthread_enable_asynccancel> - ffe8: aa0003f0 mov x16, x0 - ffec: f94007e0 ldr x0, [sp,#8] - fff0: a9410be1 ldp x1, x2, [sp,#16] - fff4: d2801948 mov x8, #0xca // #202 - fff8: d4000001 svc #0x0 - fffc: f90007e0 str x0, [sp,#8] - 10000: aa1003e0 mov x0, x16 - 10004: 97fffdb5 bl f6d8 <__pthread_disable_asynccancel> - 10008: a8c403fe ldp x30, x0, [sp],#64 - 1000c: 17ffffe7 b ffa8 <__accept_nocancel+0x8> - -0000000000010010 <__connect_nocancel>: - 10010: d2801968 mov x8, #0xcb // #203 - 10014: d4000001 svc #0x0 - 10018: b13ffc1f cmn x0, #0xfff - 1001c: 54000042 b.cs 10024 <__connect_nocancel+0x14> - 10020: d65f03c0 ret - 10024: f00000e1 adrp x1, 2f000 <__FRAME_END__+0x18e30> - 10028: 4b0003e2 neg w2, w0 - 1002c: f947c421 ldr x1, [x1,#3976] - 10030: d53bd043 mrs x3, tpidr_el0 - 10034: 92800000 mov x0, #0xffffffffffffffff // #-1 - 10038: b8236822 str w2, [x1,x3] - 1003c: d65f03c0 ret - -0000000000010040 <__connect>: - 10040: 90000130 adrp x16, 34000 <__GI___pthread_keys+0x3d78> - 10044: b9432a10 ldr w16, [x16,#808] - 10048: 34fffe50 cbz w16, 10010 <__connect_nocancel> - 1004c: a9bc03fe stp x30, x0, [sp,#-64]! - 10050: a9010be1 stp x1, x2, [sp,#16] - 10054: 97fffd71 bl f618 <__pthread_enable_asynccancel> - 10058: aa0003f0 mov x16, x0 - 1005c: f94007e0 ldr x0, [sp,#8] - 10060: a9410be1 ldp x1, x2, [sp,#16] - 10064: d2801968 mov x8, #0xcb // #203 - 10068: d4000001 svc #0x0 - 1006c: f90007e0 str x0, [sp,#8] - 10070: aa1003e0 mov x0, x16 - 10074: 97fffd99 bl f6d8 <__pthread_disable_asynccancel> - 10078: a8c403fe ldp x30, x0, [sp],#64 - 1007c: 17ffffe7 b 10018 <__connect_nocancel+0x8> - -0000000000010080 : - 10080: 90000124 adrp x4, 34000 <__GI___pthread_keys+0x3d78> - 10084: a9bd7bfd stp x29, x30, [sp,#-48]! - 10088: 910003fd mov x29, sp - 1008c: b9432884 ldr w4, [x4,#808] - 10090: a90153f3 stp x19, x20, [sp,#16] - 10094: 350001c4 cbnz w4, 100cc - 10098: d2800004 mov x4, #0x0 // #0 - 1009c: 93407c00 sxtw x0, w0 - 100a0: 93407c63 sxtw x3, w3 - 100a4: aa0403e5 mov x5, x4 - 100a8: d28019e8 mov x8, #0xcf // #207 - 100ac: d4000001 svc #0x0 - 100b0: b140041f cmn x0, #0x1, lsl #12 - 100b4: 540003a8 b.hi 10128 - 100b8: aa0003f3 mov x19, x0 - 100bc: aa1303e0 mov x0, x19 - 100c0: a94153f3 ldp x19, x20, [sp,#16] - 100c4: a8c37bfd ldp x29, x30, [sp],#48 - 100c8: d65f03c0 ret - 100cc: 2a0303f3 mov w19, w3 - 100d0: f90013a2 str x2, [x29,#32] - 100d4: f90017a1 str x1, [x29,#40] - 100d8: 2a0003f4 mov w20, w0 - 100dc: 97fffd4f bl f618 <__pthread_enable_asynccancel> - 100e0: 2a0003e6 mov w6, w0 - 100e4: d2800004 mov x4, #0x0 // #0 - 100e8: 93407e80 sxtw x0, w20 - 100ec: f94017a1 ldr x1, [x29,#40] - 100f0: 93407e63 sxtw x3, w19 - 100f4: f94013a2 ldr x2, [x29,#32] - 100f8: aa0403e5 mov x5, x4 - 100fc: d28019e8 mov x8, #0xcf // #207 - 10100: d4000001 svc #0x0 - 10104: b140041f cmn x0, #0x1, lsl #12 - 10108: 540001e8 b.hi 10144 - 1010c: aa0003f3 mov x19, x0 - 10110: 2a0603e0 mov w0, w6 - 10114: 97fffd71 bl f6d8 <__pthread_disable_asynccancel> - 10118: aa1303e0 mov x0, x19 - 1011c: a94153f3 ldp x19, x20, [sp,#16] - 10120: a8c37bfd ldp x29, x30, [sp],#48 - 10124: d65f03c0 ret - 10128: d53bd041 mrs x1, tpidr_el0 - 1012c: f00000e2 adrp x2, 2f000 <__FRAME_END__+0x18e30> - 10130: f947c442 ldr x2, [x2,#3976] - 10134: 4b0003e0 neg w0, w0 - 10138: 92800013 mov x19, #0xffffffffffffffff // #-1 - 1013c: b8226820 str w0, [x1,x2] - 10140: 17ffffdf b 100bc - 10144: d53bd041 mrs x1, tpidr_el0 - 10148: f00000e2 adrp x2, 2f000 <__FRAME_END__+0x18e30> - 1014c: f947c442 ldr x2, [x2,#3976] - 10150: 4b0003e0 neg w0, w0 - 10154: 92800013 mov x19, #0xffffffffffffffff // #-1 - 10158: b8226820 str w0, [x1,x2] - 1015c: 17ffffed b 10110 - -0000000000010160 <__recvfrom_nocancel>: - 10160: d28019e8 mov x8, #0xcf // #207 - 10164: d4000001 svc #0x0 - 10168: b13ffc1f cmn x0, #0xfff - 1016c: 54000042 b.cs 10174 <__recvfrom_nocancel+0x14> - 10170: d65f03c0 ret - 10174: f00000e1 adrp x1, 2f000 <__FRAME_END__+0x18e30> - 10178: 4b0003e2 neg w2, w0 - 1017c: f947c421 ldr x1, [x1,#3976] - 10180: d53bd043 mrs x3, tpidr_el0 - 10184: 92800000 mov x0, #0xffffffffffffffff // #-1 - 10188: b8236822 str w2, [x1,x3] - 1018c: d65f03c0 ret - -0000000000010190 : - 10190: 90000130 adrp x16, 34000 <__GI___pthread_keys+0x3d78> - 10194: b9432a10 ldr w16, [x16,#808] - 10198: 34fffe50 cbz w16, 10160 <__recvfrom_nocancel> - 1019c: a9bc03fe stp x30, x0, [sp,#-64]! - 101a0: a9010be1 stp x1, x2, [sp,#16] - 101a4: a90213e3 stp x3, x4, [sp,#32] - 101a8: f9001be5 str x5, [sp,#48] - 101ac: 97fffd1b bl f618 <__pthread_enable_asynccancel> - 101b0: aa0003f0 mov x16, x0 - 101b4: a94087e0 ldp x0, x1, [sp,#8] - 101b8: a9418fe2 ldp x2, x3, [sp,#24] - 101bc: a94297e4 ldp x4, x5, [sp,#40] - 101c0: d28019e8 mov x8, #0xcf // #207 - 101c4: d4000001 svc #0x0 - 101c8: f90007e0 str x0, [sp,#8] - 101cc: aa1003e0 mov x0, x16 - 101d0: 97fffd42 bl f6d8 <__pthread_disable_asynccancel> - 101d4: a8c403fe ldp x30, x0, [sp],#64 - 101d8: 17ffffe4 b 10168 <__recvfrom_nocancel+0x8> - 101dc: d503201f nop - -00000000000101e0 <__recvmsg_nocancel>: - 101e0: d2801a88 mov x8, #0xd4 // #212 - 101e4: d4000001 svc #0x0 - 101e8: b13ffc1f cmn x0, #0xfff - 101ec: 54000042 b.cs 101f4 <__recvmsg_nocancel+0x14> - 101f0: d65f03c0 ret - 101f4: f00000e1 adrp x1, 2f000 <__FRAME_END__+0x18e30> - 101f8: 4b0003e2 neg w2, w0 - 101fc: f947c421 ldr x1, [x1,#3976] - 10200: d53bd043 mrs x3, tpidr_el0 - 10204: 92800000 mov x0, #0xffffffffffffffff // #-1 - 10208: b8236822 str w2, [x1,x3] - 1020c: d65f03c0 ret - -0000000000010210 : - 10210: 90000130 adrp x16, 34000 <__GI___pthread_keys+0x3d78> - 10214: b9432a10 ldr w16, [x16,#808] - 10218: 34fffe50 cbz w16, 101e0 <__recvmsg_nocancel> - 1021c: a9bc03fe stp x30, x0, [sp,#-64]! - 10220: a9010be1 stp x1, x2, [sp,#16] - 10224: 97fffcfd bl f618 <__pthread_enable_asynccancel> - 10228: aa0003f0 mov x16, x0 - 1022c: f94007e0 ldr x0, [sp,#8] - 10230: a9410be1 ldp x1, x2, [sp,#16] - 10234: d2801a88 mov x8, #0xd4 // #212 - 10238: d4000001 svc #0x0 - 1023c: f90007e0 str x0, [sp,#8] - 10240: aa1003e0 mov x0, x16 - 10244: 97fffd25 bl f6d8 <__pthread_disable_asynccancel> - 10248: a8c403fe ldp x30, x0, [sp],#64 - 1024c: 17ffffe7 b 101e8 <__recvmsg_nocancel+0x8> - -0000000000010250 <__send>: - 10250: 90000124 adrp x4, 34000 <__GI___pthread_keys+0x3d78> - 10254: a9bd7bfd stp x29, x30, [sp,#-48]! - 10258: 910003fd mov x29, sp - 1025c: b9432884 ldr w4, [x4,#808] - 10260: a90153f3 stp x19, x20, [sp,#16] - 10264: 350001c4 cbnz w4, 1029c <__send+0x4c> - 10268: d2800004 mov x4, #0x0 // #0 - 1026c: 93407c00 sxtw x0, w0 - 10270: 93407c63 sxtw x3, w3 - 10274: aa0403e5 mov x5, x4 - 10278: d28019c8 mov x8, #0xce // #206 - 1027c: d4000001 svc #0x0 - 10280: b140041f cmn x0, #0x1, lsl #12 - 10284: 540003a8 b.hi 102f8 <__send+0xa8> - 10288: aa0003f3 mov x19, x0 - 1028c: aa1303e0 mov x0, x19 - 10290: a94153f3 ldp x19, x20, [sp,#16] - 10294: a8c37bfd ldp x29, x30, [sp],#48 - 10298: d65f03c0 ret - 1029c: 2a0303f3 mov w19, w3 - 102a0: f90013a2 str x2, [x29,#32] - 102a4: f90017a1 str x1, [x29,#40] - 102a8: 2a0003f4 mov w20, w0 - 102ac: 97fffcdb bl f618 <__pthread_enable_asynccancel> - 102b0: 2a0003e6 mov w6, w0 - 102b4: d2800004 mov x4, #0x0 // #0 - 102b8: 93407e80 sxtw x0, w20 - 102bc: f94017a1 ldr x1, [x29,#40] - 102c0: 93407e63 sxtw x3, w19 - 102c4: f94013a2 ldr x2, [x29,#32] - 102c8: aa0403e5 mov x5, x4 - 102cc: d28019c8 mov x8, #0xce // #206 - 102d0: d4000001 svc #0x0 - 102d4: b140041f cmn x0, #0x1, lsl #12 - 102d8: 540001e8 b.hi 10314 <__send+0xc4> - 102dc: aa0003f3 mov x19, x0 - 102e0: 2a0603e0 mov w0, w6 - 102e4: 97fffcfd bl f6d8 <__pthread_disable_asynccancel> - 102e8: aa1303e0 mov x0, x19 - 102ec: a94153f3 ldp x19, x20, [sp,#16] - 102f0: a8c37bfd ldp x29, x30, [sp],#48 - 102f4: d65f03c0 ret - 102f8: d53bd041 mrs x1, tpidr_el0 - 102fc: f00000e2 adrp x2, 2f000 <__FRAME_END__+0x18e30> - 10300: f947c442 ldr x2, [x2,#3976] - 10304: 4b0003e0 neg w0, w0 - 10308: 92800013 mov x19, #0xffffffffffffffff // #-1 - 1030c: b8226820 str w0, [x1,x2] - 10310: 17ffffdf b 1028c <__send+0x3c> - 10314: d53bd041 mrs x1, tpidr_el0 - 10318: f00000e2 adrp x2, 2f000 <__FRAME_END__+0x18e30> - 1031c: f947c442 ldr x2, [x2,#3976] - 10320: 4b0003e0 neg w0, w0 - 10324: 92800013 mov x19, #0xffffffffffffffff // #-1 - 10328: b8226820 str w0, [x1,x2] - 1032c: 17ffffed b 102e0 <__send+0x90> - -0000000000010330 <__sendmsg_nocancel>: - 10330: d2801a68 mov x8, #0xd3 // #211 - 10334: d4000001 svc #0x0 - 10338: b13ffc1f cmn x0, #0xfff - 1033c: 54000042 b.cs 10344 <__sendmsg_nocancel+0x14> - 10340: d65f03c0 ret - 10344: f00000e1 adrp x1, 2f000 <__FRAME_END__+0x18e30> - 10348: 4b0003e2 neg w2, w0 - 1034c: f947c421 ldr x1, [x1,#3976] - 10350: d53bd043 mrs x3, tpidr_el0 - 10354: 92800000 mov x0, #0xffffffffffffffff // #-1 - 10358: b8236822 str w2, [x1,x3] - 1035c: d65f03c0 ret - -0000000000010360 : - 10360: 90000130 adrp x16, 34000 <__GI___pthread_keys+0x3d78> - 10364: b9432a10 ldr w16, [x16,#808] - 10368: 34fffe50 cbz w16, 10330 <__sendmsg_nocancel> - 1036c: a9bc03fe stp x30, x0, [sp,#-64]! - 10370: a9010be1 stp x1, x2, [sp,#16] - 10374: 97fffca9 bl f618 <__pthread_enable_asynccancel> - 10378: aa0003f0 mov x16, x0 - 1037c: f94007e0 ldr x0, [sp,#8] - 10380: a9410be1 ldp x1, x2, [sp,#16] - 10384: d2801a68 mov x8, #0xd3 // #211 - 10388: d4000001 svc #0x0 - 1038c: f90007e0 str x0, [sp,#8] - 10390: aa1003e0 mov x0, x16 - 10394: 97fffcd1 bl f6d8 <__pthread_disable_asynccancel> - 10398: a8c403fe ldp x30, x0, [sp],#64 - 1039c: 17ffffe7 b 10338 <__sendmsg_nocancel+0x8> - -00000000000103a0 <__sendto_nocancel>: - 103a0: d28019c8 mov x8, #0xce // #206 - 103a4: d4000001 svc #0x0 - 103a8: b13ffc1f cmn x0, #0xfff - 103ac: 54000042 b.cs 103b4 <__sendto_nocancel+0x14> - 103b0: d65f03c0 ret - 103b4: f00000e1 adrp x1, 2f000 <__FRAME_END__+0x18e30> - 103b8: 4b0003e2 neg w2, w0 - 103bc: f947c421 ldr x1, [x1,#3976] - 103c0: d53bd043 mrs x3, tpidr_el0 - 103c4: 92800000 mov x0, #0xffffffffffffffff // #-1 - 103c8: b8236822 str w2, [x1,x3] - 103cc: d65f03c0 ret - -00000000000103d0 : - 103d0: 90000130 adrp x16, 34000 <__GI___pthread_keys+0x3d78> - 103d4: b9432a10 ldr w16, [x16,#808] - 103d8: 34fffe50 cbz w16, 103a0 <__sendto_nocancel> - 103dc: a9bc03fe stp x30, x0, [sp,#-64]! - 103e0: a9010be1 stp x1, x2, [sp,#16] - 103e4: a90213e3 stp x3, x4, [sp,#32] - 103e8: f9001be5 str x5, [sp,#48] - 103ec: 97fffc8b bl f618 <__pthread_enable_asynccancel> - 103f0: aa0003f0 mov x16, x0 - 103f4: a94087e0 ldp x0, x1, [sp,#8] - 103f8: a9418fe2 ldp x2, x3, [sp,#24] - 103fc: a94297e4 ldp x4, x5, [sp,#40] - 10400: d28019c8 mov x8, #0xce // #206 - 10404: d4000001 svc #0x0 - 10408: f90007e0 str x0, [sp,#8] - 1040c: aa1003e0 mov x0, x16 - 10410: 97fffcb2 bl f6d8 <__pthread_disable_asynccancel> - 10414: a8c403fe ldp x30, x0, [sp],#64 - 10418: 17ffffe4 b 103a8 <__sendto_nocancel+0x8> - 1041c: d503201f nop - -0000000000010420 <__fsync_nocancel>: - 10420: d2800a48 mov x8, #0x52 // #82 - 10424: d4000001 svc #0x0 - 10428: b13ffc1f cmn x0, #0xfff - 1042c: 54000042 b.cs 10434 <__fsync_nocancel+0x14> - 10430: d65f03c0 ret - 10434: f00000e1 adrp x1, 2f000 <__FRAME_END__+0x18e30> - 10438: 4b0003e2 neg w2, w0 - 1043c: f947c421 ldr x1, [x1,#3976] - 10440: d53bd043 mrs x3, tpidr_el0 - 10444: 92800000 mov x0, #0xffffffffffffffff // #-1 - 10448: b8236822 str w2, [x1,x3] - 1044c: d65f03c0 ret - -0000000000010450 : - 10450: 90000130 adrp x16, 34000 <__GI___pthread_keys+0x3d78> - 10454: b9432a10 ldr w16, [x16,#808] - 10458: 34fffe50 cbz w16, 10420 <__fsync_nocancel> - 1045c: a9bc03fe stp x30, x0, [sp,#-64]! - 10460: 97fffc6e bl f618 <__pthread_enable_asynccancel> - 10464: aa0003f0 mov x16, x0 - 10468: f94007e0 ldr x0, [sp,#8] - 1046c: d2800a48 mov x8, #0x52 // #82 - 10470: d4000001 svc #0x0 - 10474: f90007e0 str x0, [sp,#8] - 10478: aa1003e0 mov x0, x16 - 1047c: 97fffc97 bl f6d8 <__pthread_disable_asynccancel> - 10480: a8c403fe ldp x30, x0, [sp],#64 - 10484: 17ffffe9 b 10428 <__fsync_nocancel+0x8> - 10488: d503201f nop - 1048c: d503201f nop - -0000000000010490 <__lseek_nocancel>: - 10490: d28007c8 mov x8, #0x3e // #62 - 10494: d4000001 svc #0x0 - 10498: b13ffc1f cmn x0, #0xfff - 1049c: 54000042 b.cs 104a4 <__lseek_nocancel+0x14> - 104a0: d65f03c0 ret - 104a4: f00000e1 adrp x1, 2f000 <__FRAME_END__+0x18e30> - 104a8: 4b0003e2 neg w2, w0 - 104ac: f947c421 ldr x1, [x1,#3976] - 104b0: d53bd043 mrs x3, tpidr_el0 - 104b4: 92800000 mov x0, #0xffffffffffffffff // #-1 - 104b8: b8236822 str w2, [x1,x3] - 104bc: d65f03c0 ret - -00000000000104c0 <__lseek>: - 104c0: 90000130 adrp x16, 34000 <__GI___pthread_keys+0x3d78> - 104c4: b9432a10 ldr w16, [x16,#808] - 104c8: 34fffe50 cbz w16, 10490 <__lseek_nocancel> - 104cc: a9bc03fe stp x30, x0, [sp,#-64]! - 104d0: a9010be1 stp x1, x2, [sp,#16] - 104d4: 97fffc51 bl f618 <__pthread_enable_asynccancel> - 104d8: aa0003f0 mov x16, x0 - 104dc: f94007e0 ldr x0, [sp,#8] - 104e0: a9410be1 ldp x1, x2, [sp,#16] - 104e4: d28007c8 mov x8, #0x3e // #62 - 104e8: d4000001 svc #0x0 - 104ec: f90007e0 str x0, [sp,#8] - 104f0: aa1003e0 mov x0, x16 - 104f4: 97fffc79 bl f6d8 <__pthread_disable_asynccancel> - 104f8: a8c403fe ldp x30, x0, [sp],#64 - 104fc: 17ffffe7 b 10498 <__lseek_nocancel+0x8> - -0000000000010500 <__msync_nocancel>: - 10500: d2801c68 mov x8, #0xe3 // #227 - 10504: d4000001 svc #0x0 - 10508: b13ffc1f cmn x0, #0xfff - 1050c: 54000042 b.cs 10514 <__msync_nocancel+0x14> - 10510: d65f03c0 ret - 10514: f00000e1 adrp x1, 2f000 <__FRAME_END__+0x18e30> - 10518: 4b0003e2 neg w2, w0 - 1051c: f947c421 ldr x1, [x1,#3976] - 10520: d53bd043 mrs x3, tpidr_el0 - 10524: 92800000 mov x0, #0xffffffffffffffff // #-1 - 10528: b8236822 str w2, [x1,x3] - 1052c: d65f03c0 ret - -0000000000010530 : - 10530: 90000130 adrp x16, 34000 <__GI___pthread_keys+0x3d78> - 10534: b9432a10 ldr w16, [x16,#808] - 10538: 34fffe50 cbz w16, 10500 <__msync_nocancel> - 1053c: a9bc03fe stp x30, x0, [sp,#-64]! - 10540: a9010be1 stp x1, x2, [sp,#16] - 10544: 97fffc35 bl f618 <__pthread_enable_asynccancel> - 10548: aa0003f0 mov x16, x0 - 1054c: f94007e0 ldr x0, [sp,#8] - 10550: a9410be1 ldp x1, x2, [sp,#16] - 10554: d2801c68 mov x8, #0xe3 // #227 - 10558: d4000001 svc #0x0 - 1055c: f90007e0 str x0, [sp,#8] - 10560: aa1003e0 mov x0, x16 - 10564: 97fffc5d bl f6d8 <__pthread_disable_asynccancel> - 10568: a8c403fe ldp x30, x0, [sp],#64 - 1056c: 17ffffe7 b 10508 <__msync_nocancel+0x8> - -0000000000010570 <__nanosleep_nocancel>: - 10570: d2800ca8 mov x8, #0x65 // #101 - 10574: d4000001 svc #0x0 - 10578: b13ffc1f cmn x0, #0xfff - 1057c: 54000042 b.cs 10584 <__nanosleep_nocancel+0x14> - 10580: d65f03c0 ret - 10584: f00000e1 adrp x1, 2f000 <__FRAME_END__+0x18e30> - 10588: 4b0003e2 neg w2, w0 - 1058c: f947c421 ldr x1, [x1,#3976] - 10590: d53bd043 mrs x3, tpidr_el0 - 10594: 92800000 mov x0, #0xffffffffffffffff // #-1 - 10598: b8236822 str w2, [x1,x3] - 1059c: d65f03c0 ret - -00000000000105a0 <__nanosleep>: - 105a0: 90000130 adrp x16, 34000 <__GI___pthread_keys+0x3d78> - 105a4: b9432a10 ldr w16, [x16,#808] - 105a8: 34fffe50 cbz w16, 10570 <__nanosleep_nocancel> - 105ac: a9bc03fe stp x30, x0, [sp,#-64]! - 105b0: f9000be1 str x1, [sp,#16] - 105b4: 97fffc19 bl f618 <__pthread_enable_asynccancel> - 105b8: aa0003f0 mov x16, x0 - 105bc: a94087e0 ldp x0, x1, [sp,#8] - 105c0: d2800ca8 mov x8, #0x65 // #101 - 105c4: d4000001 svc #0x0 - 105c8: f90007e0 str x0, [sp,#8] - 105cc: aa1003e0 mov x0, x16 - 105d0: 97fffc42 bl f6d8 <__pthread_disable_asynccancel> - 105d4: a8c403fe ldp x30, x0, [sp],#64 - 105d8: 17ffffe8 b 10578 <__nanosleep_nocancel+0x8> - 105dc: d503201f nop - -00000000000105e0 <__open>: - 105e0: a9b07bfd stp x29, x30, [sp,#-256]! - 105e4: 910003fd mov x29, sp - 105e8: f9000bf3 str x19, [sp,#16] - 105ec: 2a0103f3 mov w19, w1 - 105f0: 3d8017a0 str q0, [x29,#80] - 105f4: aa0003e1 mov x1, x0 - 105f8: f9006fa3 str x3, [x29,#216] - 105fc: d2800003 mov x3, #0x0 // #0 - 10600: f9006ba2 str x2, [x29,#208] - 10604: f90073a4 str x4, [x29,#224] - 10608: f90077a5 str x5, [x29,#232] - 1060c: f9007ba6 str x6, [x29,#240] - 10610: f9007fa7 str x7, [x29,#248] - 10614: 3d801ba1 str q1, [x29,#96] - 10618: 3d801fa2 str q2, [x29,#112] - 1061c: 3d8023a3 str q3, [x29,#128] - 10620: 3d8027a4 str q4, [x29,#144] - 10624: 3d802ba5 str q5, [x29,#160] - 10628: 3d802fa6 str q6, [x29,#176] - 1062c: 3d8033a7 str q7, [x29,#192] - 10630: 373001f3 tbnz w19, #6, 1066c <__open+0x8c> - 10634: 90000120 adrp x0, 34000 <__GI___pthread_keys+0x3d78> - 10638: b9432800 ldr w0, [x0,#808] - 1063c: 35000320 cbnz w0, 106a0 <__open+0xc0> - 10640: 92800c60 mov x0, #0xffffffffffffff9c // #-100 - 10644: 93407e62 sxtw x2, w19 - 10648: d2800708 mov x8, #0x38 // #56 - 1064c: d4000001 svc #0x0 - 10650: b140041f cmn x0, #0x1, lsl #12 - 10654: 540004c8 b.hi 106ec <__open+0x10c> - 10658: 2a0003f3 mov w19, w0 - 1065c: 2a1303e0 mov w0, w19 - 10660: f9400bf3 ldr x19, [sp,#16] - 10664: a8d07bfd ldp x29, x30, [sp],#256 - 10668: d65f03c0 ret - 1066c: 910343a0 add x0, x29, #0xd0 - 10670: f90023a0 str x0, [x29,#64] - 10674: 128005e0 mov w0, #0xffffffd0 // #-48 - 10678: b9004ba0 str w0, [x29,#72] - 1067c: 12800fe0 mov w0, #0xffffff80 // #-128 - 10680: b9004fa0 str w0, [x29,#76] - 10684: 90000120 adrp x0, 34000 <__GI___pthread_keys+0x3d78> - 10688: 910403a2 add x2, x29, #0x100 - 1068c: f9001ba2 str x2, [x29,#48] - 10690: f9001fa2 str x2, [x29,#56] - 10694: b9432800 ldr w0, [x0,#808] - 10698: b980d3a3 ldrsw x3, [x29,#208] - 1069c: 34fffd20 cbz w0, 10640 <__open+0x60> - 106a0: f90013a1 str x1, [x29,#32] - 106a4: f90017a3 str x3, [x29,#40] - 106a8: 97fffbdc bl f618 <__pthread_enable_asynccancel> - 106ac: f94013a1 ldr x1, [x29,#32] - 106b0: 2a0003e4 mov w4, w0 - 106b4: 93407e62 sxtw x2, w19 - 106b8: 92800c60 mov x0, #0xffffffffffffff9c // #-100 - 106bc: f94017a3 ldr x3, [x29,#40] - 106c0: d2800708 mov x8, #0x38 // #56 - 106c4: d4000001 svc #0x0 - 106c8: b140041f cmn x0, #0x1, lsl #12 - 106cc: 540001e8 b.hi 10708 <__open+0x128> - 106d0: 2a0003f3 mov w19, w0 - 106d4: 2a0403e0 mov w0, w4 - 106d8: 97fffc00 bl f6d8 <__pthread_disable_asynccancel> - 106dc: 2a1303e0 mov w0, w19 - 106e0: f9400bf3 ldr x19, [sp,#16] - 106e4: a8d07bfd ldp x29, x30, [sp],#256 - 106e8: d65f03c0 ret - 106ec: d53bd041 mrs x1, tpidr_el0 - 106f0: f00000e2 adrp x2, 2f000 <__FRAME_END__+0x18e30> - 106f4: f947c442 ldr x2, [x2,#3976] - 106f8: 4b0003e0 neg w0, w0 - 106fc: 12800013 mov w19, #0xffffffff // #-1 - 10700: b8226820 str w0, [x1,x2] - 10704: 17ffffd6 b 1065c <__open+0x7c> - 10708: d53bd041 mrs x1, tpidr_el0 - 1070c: f00000e2 adrp x2, 2f000 <__FRAME_END__+0x18e30> - 10710: f947c442 ldr x2, [x2,#3976] - 10714: 4b0003e0 neg w0, w0 - 10718: 12800013 mov w19, #0xffffffff // #-1 - 1071c: b8226820 str w0, [x1,x2] - 10720: 17ffffed b 106d4 <__open+0xf4> - -0000000000010724 <__open_nocancel>: - 10724: d10343ff sub sp, sp, #0xd0 - 10728: 3d800be0 str q0, [sp,#32] - 1072c: f90053e2 str x2, [sp,#160] - 10730: 93407c22 sxtw x2, w1 - 10734: f90057e3 str x3, [sp,#168] - 10738: aa0003e1 mov x1, x0 - 1073c: f9005be4 str x4, [sp,#176] - 10740: d2800003 mov x3, #0x0 // #0 - 10744: f9005fe5 str x5, [sp,#184] - 10748: f90063e6 str x6, [sp,#192] - 1074c: f90067e7 str x7, [sp,#200] - 10750: 3d800fe1 str q1, [sp,#48] - 10754: 3d8013e2 str q2, [sp,#64] - 10758: 3d8017e3 str q3, [sp,#80] - 1075c: 3d801be4 str q4, [sp,#96] - 10760: 3d801fe5 str q5, [sp,#112] - 10764: 3d8023e6 str q6, [sp,#128] - 10768: 3d8027e7 str q7, [sp,#144] - 1076c: 37300102 tbnz w2, #6, 1078c <__open_nocancel+0x68> - 10770: 92800c60 mov x0, #0xffffffffffffff9c // #-100 - 10774: d2800708 mov x8, #0x38 // #56 - 10778: d4000001 svc #0x0 - 1077c: b140041f cmn x0, #0x1, lsl #12 - 10780: 54000248 b.hi 107c8 <__open_nocancel+0xa4> - 10784: 910343ff add sp, sp, #0xd0 - 10788: d65f03c0 ret - 1078c: 910283e0 add x0, sp, #0xa0 - 10790: f9000be0 str x0, [sp,#16] - 10794: 128005e0 mov w0, #0xffffffd0 // #-48 - 10798: b9001be0 str w0, [sp,#24] - 1079c: 12800fe0 mov w0, #0xffffff80 // #-128 - 107a0: 910343e4 add x4, sp, #0xd0 - 107a4: b9001fe0 str w0, [sp,#28] - 107a8: d2800708 mov x8, #0x38 // #56 - 107ac: b980a3e3 ldrsw x3, [sp,#160] - 107b0: 92800c60 mov x0, #0xffffffffffffff9c // #-100 - 107b4: f90003e4 str x4, [sp] - 107b8: f90007e4 str x4, [sp,#8] - 107bc: d4000001 svc #0x0 - 107c0: b140041f cmn x0, #0x1, lsl #12 - 107c4: 54fffe09 b.ls 10784 <__open_nocancel+0x60> - 107c8: d53bd041 mrs x1, tpidr_el0 - 107cc: f00000e2 adrp x2, 2f000 <__FRAME_END__+0x18e30> - 107d0: f947c442 ldr x2, [x2,#3976] - 107d4: 4b0003e3 neg w3, w0 - 107d8: 910343ff add sp, sp, #0xd0 - 107dc: 12800000 mov w0, #0xffffffff // #-1 - 107e0: b8226823 str w3, [x1,x2] - 107e4: d65f03c0 ret - -00000000000107e8 <__open64>: - 107e8: a9b07bfd stp x29, x30, [sp,#-256]! - 107ec: 910003fd mov x29, sp - 107f0: f9000bf3 str x19, [sp,#16] - 107f4: 2a0103f3 mov w19, w1 - 107f8: 3d8017a0 str q0, [x29,#80] - 107fc: aa0003e1 mov x1, x0 - 10800: f9006fa3 str x3, [x29,#216] - 10804: d2800003 mov x3, #0x0 // #0 - 10808: f9006ba2 str x2, [x29,#208] - 1080c: f90073a4 str x4, [x29,#224] - 10810: f90077a5 str x5, [x29,#232] - 10814: f9007ba6 str x6, [x29,#240] - 10818: f9007fa7 str x7, [x29,#248] - 1081c: 3d801ba1 str q1, [x29,#96] - 10820: 3d801fa2 str q2, [x29,#112] - 10824: 3d8023a3 str q3, [x29,#128] - 10828: 3d8027a4 str q4, [x29,#144] - 1082c: 3d802ba5 str q5, [x29,#160] - 10830: 3d802fa6 str q6, [x29,#176] - 10834: 3d8033a7 str q7, [x29,#192] - 10838: 373001f3 tbnz w19, #6, 10874 <__open64+0x8c> - 1083c: 90000120 adrp x0, 34000 <__GI___pthread_keys+0x3d78> - 10840: b9432800 ldr w0, [x0,#808] - 10844: 35000320 cbnz w0, 108a8 <__open64+0xc0> - 10848: 92800c60 mov x0, #0xffffffffffffff9c // #-100 - 1084c: 93407e62 sxtw x2, w19 - 10850: d2800708 mov x8, #0x38 // #56 - 10854: d4000001 svc #0x0 - 10858: b140041f cmn x0, #0x1, lsl #12 - 1085c: 540004c8 b.hi 108f4 <__open64+0x10c> - 10860: 2a0003f3 mov w19, w0 - 10864: 2a1303e0 mov w0, w19 - 10868: f9400bf3 ldr x19, [sp,#16] - 1086c: a8d07bfd ldp x29, x30, [sp],#256 - 10870: d65f03c0 ret - 10874: 910343a0 add x0, x29, #0xd0 - 10878: f90023a0 str x0, [x29,#64] - 1087c: 128005e0 mov w0, #0xffffffd0 // #-48 - 10880: b9004ba0 str w0, [x29,#72] - 10884: 12800fe0 mov w0, #0xffffff80 // #-128 - 10888: b9004fa0 str w0, [x29,#76] - 1088c: 90000120 adrp x0, 34000 <__GI___pthread_keys+0x3d78> - 10890: 910403a2 add x2, x29, #0x100 - 10894: f9001ba2 str x2, [x29,#48] - 10898: f9001fa2 str x2, [x29,#56] - 1089c: b9432800 ldr w0, [x0,#808] - 108a0: b980d3a3 ldrsw x3, [x29,#208] - 108a4: 34fffd20 cbz w0, 10848 <__open64+0x60> - 108a8: f90013a1 str x1, [x29,#32] - 108ac: f90017a3 str x3, [x29,#40] - 108b0: 97fffb5a bl f618 <__pthread_enable_asynccancel> - 108b4: f94013a1 ldr x1, [x29,#32] - 108b8: 2a0003e4 mov w4, w0 - 108bc: 93407e62 sxtw x2, w19 - 108c0: 92800c60 mov x0, #0xffffffffffffff9c // #-100 - 108c4: f94017a3 ldr x3, [x29,#40] - 108c8: d2800708 mov x8, #0x38 // #56 - 108cc: d4000001 svc #0x0 - 108d0: b140041f cmn x0, #0x1, lsl #12 - 108d4: 540001e8 b.hi 10910 <__open64+0x128> - 108d8: 2a0003f3 mov w19, w0 - 108dc: 2a0403e0 mov w0, w4 - 108e0: 97fffb7e bl f6d8 <__pthread_disable_asynccancel> - 108e4: 2a1303e0 mov w0, w19 - 108e8: f9400bf3 ldr x19, [sp,#16] - 108ec: a8d07bfd ldp x29, x30, [sp],#256 - 108f0: d65f03c0 ret - 108f4: d53bd041 mrs x1, tpidr_el0 - 108f8: f00000e2 adrp x2, 2f000 <__FRAME_END__+0x18e30> - 108fc: f947c442 ldr x2, [x2,#3976] - 10900: 4b0003e0 neg w0, w0 - 10904: 12800013 mov w19, #0xffffffff // #-1 - 10908: b8226820 str w0, [x1,x2] - 1090c: 17ffffd6 b 10864 <__open64+0x7c> - 10910: d53bd041 mrs x1, tpidr_el0 - 10914: f00000e2 adrp x2, 2f000 <__FRAME_END__+0x18e30> - 10918: f947c442 ldr x2, [x2,#3976] - 1091c: 4b0003e0 neg w0, w0 - 10920: 12800013 mov w19, #0xffffffff // #-1 - 10924: b8226820 str w0, [x1,x2] - 10928: 17ffffed b 108dc <__open64+0xf4> - -000000000001092c : - 1092c: 90000120 adrp x0, 34000 <__GI___pthread_keys+0x3d78> - 10930: a9b67bfd stp x29, x30, [sp,#-160]! - 10934: 910003fd mov x29, sp - 10938: b9432800 ldr w0, [x0,#808] - 1093c: f9000bf3 str x19, [sp,#16] - 10940: 350003c0 cbnz w0, 109b8 - 10944: 910083a4 add x4, x29, #0x20 - 10948: d2800000 mov x0, #0x0 // #0 - 1094c: aa0003e1 mov x1, x0 - 10950: aa0403e2 mov x2, x4 - 10954: d2800103 mov x3, #0x8 // #8 - 10958: d28010e8 mov x8, #0x87 // #135 - 1095c: d4000001 svc #0x0 - 10960: b140041f cmn x0, #0x1, lsl #12 - 10964: 540001c8 b.hi 1099c - 10968: 2a0003e1 mov w1, w0 - 1096c: 35000100 cbnz w0, 1098c - 10970: aa0403e0 mov x0, x4 - 10974: aa0303e1 mov x1, x3 - 10978: d28010a8 mov x8, #0x85 // #133 - 1097c: d4000001 svc #0x0 - 10980: b140041f cmn x0, #0x1, lsl #12 - 10984: 540000c8 b.hi 1099c - 10988: 2a0003e1 mov w1, w0 - 1098c: 2a0103e0 mov w0, w1 - 10990: f9400bf3 ldr x19, [sp,#16] - 10994: a8ca7bfd ldp x29, x30, [sp],#160 - 10998: d65f03c0 ret - 1099c: d53bd042 mrs x2, tpidr_el0 - 109a0: f00000e3 adrp x3, 2f000 <__FRAME_END__+0x18e30> - 109a4: f947c463 ldr x3, [x3,#3976] - 109a8: 4b0003e0 neg w0, w0 - 109ac: 12800001 mov w1, #0xffffffff // #-1 - 109b0: b8236840 str w0, [x2,x3] - 109b4: 17fffff6 b 1098c - 109b8: 97fffb18 bl f618 <__pthread_enable_asynccancel> - 109bc: 2a0003e5 mov w5, w0 - 109c0: 910083a4 add x4, x29, #0x20 - 109c4: d2800000 mov x0, #0x0 // #0 - 109c8: aa0003e1 mov x1, x0 - 109cc: aa0403e2 mov x2, x4 - 109d0: d2800103 mov x3, #0x8 // #8 - 109d4: d28010e8 mov x8, #0x87 // #135 - 109d8: d4000001 svc #0x0 - 109dc: b140041f cmn x0, #0x1, lsl #12 - 109e0: 54000208 b.hi 10a20 - 109e4: 2a0003f3 mov w19, w0 - 109e8: 35000100 cbnz w0, 10a08 - 109ec: aa0403e0 mov x0, x4 - 109f0: aa0303e1 mov x1, x3 - 109f4: d28010a8 mov x8, #0x85 // #133 - 109f8: d4000001 svc #0x0 - 109fc: b140041f cmn x0, #0x1, lsl #12 - 10a00: 540001e8 b.hi 10a3c - 10a04: 2a0003f3 mov w19, w0 - 10a08: 2a0503e0 mov w0, w5 - 10a0c: 97fffb33 bl f6d8 <__pthread_disable_asynccancel> - 10a10: 2a1303e0 mov w0, w19 - 10a14: f9400bf3 ldr x19, [sp,#16] - 10a18: a8ca7bfd ldp x29, x30, [sp],#160 - 10a1c: d65f03c0 ret - 10a20: 4b0003e1 neg w1, w0 - 10a24: f00000e2 adrp x2, 2f000 <__FRAME_END__+0x18e30> - 10a28: f947c442 ldr x2, [x2,#3976] - 10a2c: d53bd040 mrs x0, tpidr_el0 - 10a30: 12800013 mov w19, #0xffffffff // #-1 - 10a34: b8226801 str w1, [x0,x2] - 10a38: 17fffff4 b 10a08 - 10a3c: d53bd041 mrs x1, tpidr_el0 - 10a40: f00000e2 adrp x2, 2f000 <__FRAME_END__+0x18e30> - 10a44: f947c442 ldr x2, [x2,#3976] - 10a48: 4b0003e0 neg w0, w0 - 10a4c: 12800013 mov w19, #0xffffffff // #-1 - 10a50: b8226820 str w0, [x1,x2] - 10a54: 17ffffed b 10a08 - -0000000000010a58 <__pause_nocancel>: - 10a58: d10203ff sub sp, sp, #0x80 - 10a5c: d2800000 mov x0, #0x0 // #0 - 10a60: aa0003e1 mov x1, x0 - 10a64: 910003e2 mov x2, sp - 10a68: d2800103 mov x3, #0x8 // #8 - 10a6c: d28010e8 mov x8, #0x87 // #135 - 10a70: d4000001 svc #0x0 - 10a74: b140041f cmn x0, #0x1, lsl #12 - 10a78: 540001a8 b.hi 10aac <__pause_nocancel+0x54> - 10a7c: 2a0003e1 mov w1, w0 - 10a80: 35000100 cbnz w0, 10aa0 <__pause_nocancel+0x48> - 10a84: 910003e0 mov x0, sp - 10a88: aa0303e1 mov x1, x3 - 10a8c: d28010a8 mov x8, #0x85 // #133 - 10a90: d4000001 svc #0x0 - 10a94: b140041f cmn x0, #0x1, lsl #12 - 10a98: 540000a8 b.hi 10aac <__pause_nocancel+0x54> - 10a9c: 2a0003e1 mov w1, w0 - 10aa0: 2a0103e0 mov w0, w1 - 10aa4: 910203ff add sp, sp, #0x80 - 10aa8: d65f03c0 ret - 10aac: d53bd042 mrs x2, tpidr_el0 - 10ab0: f00000e3 adrp x3, 2f000 <__FRAME_END__+0x18e30> - 10ab4: f947c463 ldr x3, [x3,#3976] - 10ab8: 4b0003e0 neg w0, w0 - 10abc: 12800001 mov w1, #0xffffffff // #-1 - 10ac0: 910203ff add sp, sp, #0x80 - 10ac4: b8236840 str w0, [x2,x3] - 10ac8: 2a0103e0 mov w0, w1 - 10acc: d65f03c0 ret - -0000000000010ad0 <__pread_nocancel>: - 10ad0: d2800868 mov x8, #0x43 // #67 - 10ad4: d4000001 svc #0x0 - 10ad8: b13ffc1f cmn x0, #0xfff - 10adc: 54000042 b.cs 10ae4 <__pread_nocancel+0x14> - 10ae0: d65f03c0 ret - 10ae4: f00000e1 adrp x1, 2f000 <__FRAME_END__+0x18e30> - 10ae8: 4b0003e2 neg w2, w0 - 10aec: f947c421 ldr x1, [x1,#3976] - 10af0: d53bd043 mrs x3, tpidr_el0 - 10af4: 92800000 mov x0, #0xffffffffffffffff // #-1 - 10af8: b8236822 str w2, [x1,x3] - 10afc: d65f03c0 ret - -0000000000010b00 <__pread64>: - 10b00: 90000130 adrp x16, 34000 <__GI___pthread_keys+0x3d78> - 10b04: b9432a10 ldr w16, [x16,#808] - 10b08: 34fffe50 cbz w16, 10ad0 <__pread_nocancel> - 10b0c: a9bc03fe stp x30, x0, [sp,#-64]! - 10b10: a9010be1 stp x1, x2, [sp,#16] - 10b14: f90013e3 str x3, [sp,#32] - 10b18: 97fffac0 bl f618 <__pthread_enable_asynccancel> - 10b1c: aa0003f0 mov x16, x0 - 10b20: a94087e0 ldp x0, x1, [sp,#8] - 10b24: a9418fe2 ldp x2, x3, [sp,#24] - 10b28: d2800868 mov x8, #0x43 // #67 - 10b2c: d4000001 svc #0x0 - 10b30: f90007e0 str x0, [sp,#8] - 10b34: aa1003e0 mov x0, x16 - 10b38: 97fffae8 bl f6d8 <__pthread_disable_asynccancel> - 10b3c: a8c403fe ldp x30, x0, [sp],#64 - 10b40: 17ffffe6 b 10ad8 <__pread_nocancel+0x8> - 10b44: d503201f nop - 10b48: d503201f nop - 10b4c: d503201f nop - -0000000000010b50 <__pwrite_nocancel>: - 10b50: d2800888 mov x8, #0x44 // #68 - 10b54: d4000001 svc #0x0 - 10b58: b13ffc1f cmn x0, #0xfff - 10b5c: 54000042 b.cs 10b64 <__pwrite_nocancel+0x14> - 10b60: d65f03c0 ret - 10b64: f00000e1 adrp x1, 2f000 <__FRAME_END__+0x18e30> - 10b68: 4b0003e2 neg w2, w0 - 10b6c: f947c421 ldr x1, [x1,#3976] - 10b70: d53bd043 mrs x3, tpidr_el0 - 10b74: 92800000 mov x0, #0xffffffffffffffff // #-1 - 10b78: b8236822 str w2, [x1,x3] - 10b7c: d65f03c0 ret - -0000000000010b80 <__pwrite64>: - 10b80: 90000130 adrp x16, 34000 <__GI___pthread_keys+0x3d78> - 10b84: b9432a10 ldr w16, [x16,#808] - 10b88: 34fffe50 cbz w16, 10b50 <__pwrite_nocancel> - 10b8c: a9bc03fe stp x30, x0, [sp,#-64]! - 10b90: a9010be1 stp x1, x2, [sp,#16] - 10b94: f90013e3 str x3, [sp,#32] - 10b98: 97fffaa0 bl f618 <__pthread_enable_asynccancel> - 10b9c: aa0003f0 mov x16, x0 - 10ba0: a94087e0 ldp x0, x1, [sp,#8] - 10ba4: a9418fe2 ldp x2, x3, [sp,#24] - 10ba8: d2800888 mov x8, #0x44 // #68 - 10bac: d4000001 svc #0x0 - 10bb0: f90007e0 str x0, [sp,#8] - 10bb4: aa1003e0 mov x0, x16 - 10bb8: 97fffac8 bl f6d8 <__pthread_disable_asynccancel> - 10bbc: a8c403fe ldp x30, x0, [sp],#64 - 10bc0: 17ffffe6 b 10b58 <__pwrite_nocancel+0x8> - 10bc4: d503201f nop - 10bc8: d503201f nop - 10bcc: d503201f nop - -0000000000010bd0 : - 10bd0: 90000121 adrp x1, 34000 <__GI___pthread_keys+0x3d78> - 10bd4: a9be7bfd stp x29, x30, [sp,#-32]! - 10bd8: 910003fd mov x29, sp - 10bdc: b9432821 ldr w1, [x1,#808] - 10be0: f9000bf3 str x19, [sp,#16] - 10be4: 350001a1 cbnz w1, 10c18 - 10be8: 93407c00 sxtw x0, w0 - 10bec: d28a8121 mov x1, #0x5409 // #21513 - 10bf0: d2800022 mov x2, #0x1 // #1 - 10bf4: d28003a8 mov x8, #0x1d // #29 - 10bf8: d4000001 svc #0x0 - 10bfc: b140041f cmn x0, #0x1, lsl #12 - 10c00: 540002e8 b.hi 10c5c - 10c04: 2a0003f3 mov w19, w0 - 10c08: 2a1303e0 mov w0, w19 - 10c0c: f9400bf3 ldr x19, [sp,#16] - 10c10: a8c27bfd ldp x29, x30, [sp],#32 - 10c14: d65f03c0 ret - 10c18: 2a0003f3 mov w19, w0 - 10c1c: 97fffa7f bl f618 <__pthread_enable_asynccancel> - 10c20: d28a8121 mov x1, #0x5409 // #21513 - 10c24: 2a0003e3 mov w3, w0 - 10c28: d2800022 mov x2, #0x1 // #1 - 10c2c: 93407e60 sxtw x0, w19 - 10c30: d28003a8 mov x8, #0x1d // #29 - 10c34: d4000001 svc #0x0 - 10c38: b140041f cmn x0, #0x1, lsl #12 - 10c3c: 540001e8 b.hi 10c78 - 10c40: 2a0003f3 mov w19, w0 - 10c44: 2a0303e0 mov w0, w3 - 10c48: 97fffaa4 bl f6d8 <__pthread_disable_asynccancel> - 10c4c: 2a1303e0 mov w0, w19 - 10c50: f9400bf3 ldr x19, [sp,#16] - 10c54: a8c27bfd ldp x29, x30, [sp],#32 - 10c58: d65f03c0 ret - 10c5c: d53bd041 mrs x1, tpidr_el0 - 10c60: f00000e2 adrp x2, 2f000 <__FRAME_END__+0x18e30> - 10c64: f947c442 ldr x2, [x2,#3976] - 10c68: 4b0003e0 neg w0, w0 - 10c6c: 12800013 mov w19, #0xffffffff // #-1 - 10c70: b8226820 str w0, [x1,x2] - 10c74: 17ffffe5 b 10c08 - 10c78: d53bd041 mrs x1, tpidr_el0 - 10c7c: f00000e2 adrp x2, 2f000 <__FRAME_END__+0x18e30> - 10c80: f947c442 ldr x2, [x2,#3976] - 10c84: 4b0003e0 neg w0, w0 - 10c88: 12800013 mov w19, #0xffffffff // #-1 - 10c8c: b8226820 str w0, [x1,x2] - 10c90: 17ffffed b 10c44 - -0000000000010c94 <__wait>: - 10c94: aa0003e1 mov x1, x0 - 10c98: 90000120 adrp x0, 34000 <__GI___pthread_keys+0x3d78> - 10c9c: a9bd7bfd stp x29, x30, [sp,#-48]! - 10ca0: 910003fd mov x29, sp - 10ca4: b9432800 ldr w0, [x0,#808] - 10ca8: f9000bf3 str x19, [sp,#16] - 10cac: 350001a0 cbnz w0, 10ce0 <__wait+0x4c> - 10cb0: d2800002 mov x2, #0x0 // #0 - 10cb4: 92800000 mov x0, #0xffffffffffffffff // #-1 - 10cb8: aa0203e3 mov x3, x2 - 10cbc: d2802088 mov x8, #0x104 // #260 - 10cc0: d4000001 svc #0x0 - 10cc4: b140041f cmn x0, #0x1, lsl #12 - 10cc8: 54000308 b.hi 10d28 <__wait+0x94> - 10ccc: 2a0003f3 mov w19, w0 - 10cd0: 2a1303e0 mov w0, w19 - 10cd4: f9400bf3 ldr x19, [sp,#16] - 10cd8: a8c37bfd ldp x29, x30, [sp],#48 - 10cdc: d65f03c0 ret - 10ce0: f90017a1 str x1, [x29,#40] - 10ce4: 97fffa4d bl f618 <__pthread_enable_asynccancel> - 10ce8: d2800002 mov x2, #0x0 // #0 - 10cec: 2a0003e4 mov w4, w0 - 10cf0: f94017a1 ldr x1, [x29,#40] - 10cf4: 92800000 mov x0, #0xffffffffffffffff // #-1 - 10cf8: aa0203e3 mov x3, x2 - 10cfc: d2802088 mov x8, #0x104 // #260 - 10d00: d4000001 svc #0x0 - 10d04: b140041f cmn x0, #0x1, lsl #12 - 10d08: 540001e8 b.hi 10d44 <__wait+0xb0> - 10d0c: 2a0003f3 mov w19, w0 - 10d10: 2a0403e0 mov w0, w4 - 10d14: 97fffa71 bl f6d8 <__pthread_disable_asynccancel> - 10d18: 2a1303e0 mov w0, w19 - 10d1c: f9400bf3 ldr x19, [sp,#16] - 10d20: a8c37bfd ldp x29, x30, [sp],#48 - 10d24: d65f03c0 ret - 10d28: d53bd041 mrs x1, tpidr_el0 - 10d2c: f00000e2 adrp x2, 2f000 <__FRAME_END__+0x18e30> - 10d30: f947c442 ldr x2, [x2,#3976] - 10d34: 4b0003e0 neg w0, w0 - 10d38: 12800013 mov w19, #0xffffffff // #-1 - 10d3c: b8226820 str w0, [x1,x2] - 10d40: 17ffffe4 b 10cd0 <__wait+0x3c> - 10d44: d53bd041 mrs x1, tpidr_el0 - 10d48: f00000e2 adrp x2, 2f000 <__FRAME_END__+0x18e30> - 10d4c: f947c442 ldr x2, [x2,#3976] - 10d50: 4b0003e0 neg w0, w0 - 10d54: 12800013 mov w19, #0xffffffff // #-1 - 10d58: b8226820 str w0, [x1,x2] - 10d5c: 17ffffed b 10d10 <__wait+0x7c> - -0000000000010d60 : - 10d60: 90000123 adrp x3, 34000 <__GI___pthread_keys+0x3d78> - 10d64: a9bd7bfd stp x29, x30, [sp,#-48]! - 10d68: 910003fd mov x29, sp - 10d6c: b9432863 ldr w3, [x3,#808] - 10d70: a90153f3 stp x19, x20, [sp,#16] - 10d74: 350001a3 cbnz w3, 10da8 - 10d78: 93407c00 sxtw x0, w0 - 10d7c: 93407c42 sxtw x2, w2 - 10d80: d2800003 mov x3, #0x0 // #0 - 10d84: d2802088 mov x8, #0x104 // #260 - 10d88: d4000001 svc #0x0 - 10d8c: b140041f cmn x0, #0x1, lsl #12 - 10d90: 54000348 b.hi 10df8 - 10d94: 2a0003f3 mov w19, w0 - 10d98: 2a1303e0 mov w0, w19 - 10d9c: a94153f3 ldp x19, x20, [sp,#16] - 10da0: a8c37bfd ldp x29, x30, [sp],#48 - 10da4: d65f03c0 ret - 10da8: 2a0203f3 mov w19, w2 - 10dac: 2a0003f4 mov w20, w0 - 10db0: f90017a1 str x1, [x29,#40] - 10db4: 97fffa19 bl f618 <__pthread_enable_asynccancel> - 10db8: f94017a1 ldr x1, [x29,#40] - 10dbc: 2a0003e4 mov w4, w0 - 10dc0: 93407e62 sxtw x2, w19 - 10dc4: 93407e80 sxtw x0, w20 - 10dc8: d2800003 mov x3, #0x0 // #0 - 10dcc: d2802088 mov x8, #0x104 // #260 - 10dd0: d4000001 svc #0x0 - 10dd4: b140041f cmn x0, #0x1, lsl #12 - 10dd8: 540001e8 b.hi 10e14 - 10ddc: 2a0003f3 mov w19, w0 - 10de0: 2a0403e0 mov w0, w4 - 10de4: 97fffa3d bl f6d8 <__pthread_disable_asynccancel> - 10de8: 2a1303e0 mov w0, w19 - 10dec: a94153f3 ldp x19, x20, [sp,#16] - 10df0: a8c37bfd ldp x29, x30, [sp],#48 - 10df4: d65f03c0 ret - 10df8: d53bd041 mrs x1, tpidr_el0 - 10dfc: f00000e2 adrp x2, 2f000 <__FRAME_END__+0x18e30> - 10e00: f947c442 ldr x2, [x2,#3976] - 10e04: 4b0003e0 neg w0, w0 - 10e08: 12800013 mov w19, #0xffffffff // #-1 - 10e0c: b8226820 str w0, [x1,x2] - 10e10: 17ffffe2 b 10d98 - 10e14: d53bd041 mrs x1, tpidr_el0 - 10e18: f00000e2 adrp x2, 2f000 <__FRAME_END__+0x18e30> - 10e1c: f947c442 ldr x2, [x2,#3976] - 10e20: 4b0003e0 neg w0, w0 - 10e24: 12800013 mov w19, #0xffffffff // #-1 - 10e28: b8226820 str w0, [x1,x2] - 10e2c: 17ffffed b 10de0 - -0000000000010e30 <__msgrcv_nocancel>: - 10e30: d2801788 mov x8, #0xbc // #188 - 10e34: d4000001 svc #0x0 - 10e38: b13ffc1f cmn x0, #0xfff - 10e3c: 54000042 b.cs 10e44 <__msgrcv_nocancel+0x14> - 10e40: d65f03c0 ret - 10e44: f00000e1 adrp x1, 2f000 <__FRAME_END__+0x18e30> - 10e48: 4b0003e2 neg w2, w0 - 10e4c: f947c421 ldr x1, [x1,#3976] - 10e50: d53bd043 mrs x3, tpidr_el0 - 10e54: 92800000 mov x0, #0xffffffffffffffff // #-1 - 10e58: b8236822 str w2, [x1,x3] - 10e5c: d65f03c0 ret - -0000000000010e60 <__msgrcv>: - 10e60: 90000130 adrp x16, 34000 <__GI___pthread_keys+0x3d78> - 10e64: b9432a10 ldr w16, [x16,#808] - 10e68: 34fffe50 cbz w16, 10e30 <__msgrcv_nocancel> - 10e6c: a9bc03fe stp x30, x0, [sp,#-64]! - 10e70: a9010be1 stp x1, x2, [sp,#16] - 10e74: a90213e3 stp x3, x4, [sp,#32] - 10e78: 97fff9e8 bl f618 <__pthread_enable_asynccancel> - 10e7c: aa0003f0 mov x16, x0 - 10e80: f94007e0 ldr x0, [sp,#8] - 10e84: a9410be1 ldp x1, x2, [sp,#16] - 10e88: a94213e3 ldp x3, x4, [sp,#32] - 10e8c: d2801788 mov x8, #0xbc // #188 - 10e90: d4000001 svc #0x0 - 10e94: f90007e0 str x0, [sp,#8] - 10e98: aa1003e0 mov x0, x16 - 10e9c: 97fffa0f bl f6d8 <__pthread_disable_asynccancel> - 10ea0: a8c403fe ldp x30, x0, [sp],#64 - 10ea4: 17ffffe5 b 10e38 <__msgrcv_nocancel+0x8> - 10ea8: d503201f nop - 10eac: d503201f nop - -0000000000010eb0 <__msgsnd_nocancel>: - 10eb0: d28017a8 mov x8, #0xbd // #189 - 10eb4: d4000001 svc #0x0 - 10eb8: b13ffc1f cmn x0, #0xfff - 10ebc: 54000042 b.cs 10ec4 <__msgsnd_nocancel+0x14> - 10ec0: d65f03c0 ret - 10ec4: f00000e1 adrp x1, 2f000 <__FRAME_END__+0x18e30> - 10ec8: 4b0003e2 neg w2, w0 - 10ecc: f947c421 ldr x1, [x1,#3976] - 10ed0: d53bd043 mrs x3, tpidr_el0 - 10ed4: 92800000 mov x0, #0xffffffffffffffff // #-1 - 10ed8: b8236822 str w2, [x1,x3] - 10edc: d65f03c0 ret - -0000000000010ee0 <__msgsnd>: - 10ee0: 90000130 adrp x16, 34000 <__GI___pthread_keys+0x3d78> - 10ee4: b9432a10 ldr w16, [x16,#808] - 10ee8: 34fffe50 cbz w16, 10eb0 <__msgsnd_nocancel> - 10eec: a9bc03fe stp x30, x0, [sp,#-64]! - 10ef0: a9010be1 stp x1, x2, [sp,#16] - 10ef4: f90013e3 str x3, [sp,#32] - 10ef8: 97fff9c8 bl f618 <__pthread_enable_asynccancel> - 10efc: aa0003f0 mov x16, x0 - 10f00: a94087e0 ldp x0, x1, [sp,#8] - 10f04: a9418fe2 ldp x2, x3, [sp,#24] - 10f08: d28017a8 mov x8, #0xbd // #189 - 10f0c: d4000001 svc #0x0 - 10f10: f90007e0 str x0, [sp,#8] - 10f14: aa1003e0 mov x0, x16 - 10f18: 97fff9f0 bl f6d8 <__pthread_disable_asynccancel> - 10f1c: a8c403fe ldp x30, x0, [sp],#64 - 10f20: 17ffffe6 b 10eb8 <__msgsnd_nocancel+0x8> - 10f24: d503201f nop - 10f28: d503201f nop - 10f2c: d503201f nop - -0000000000010f30 : - 10f30: 90000122 adrp x2, 34000 <__GI___pthread_keys+0x3d78> - 10f34: aa0103e5 mov x5, x1 - 10f38: a9b67bfd stp x29, x30, [sp,#-160]! - 10f3c: 910003fd mov x29, sp - 10f40: b9432842 ldr w2, [x2,#808] - 10f44: a90153f3 stp x19, x20, [sp,#16] - 10f48: 350003e2 cbnz w2, 10fc4 - 10f4c: b4000080 cbz x0, 10f5c - 10f50: f9400002 ldr x2, [x0] - 10f54: f261045f tst x2, #0x180000000 - 10f58: 540002e1 b.ne 10fb4 - 10f5c: aa0003e4 mov x4, x0 - 10f60: 14000003 b 10f6c - 10f64: 3140041f cmn w0, #0x1, lsl #12 - 10f68: 54000169 b.ls 10f94 - 10f6c: d2800001 mov x1, #0x0 // #0 - 10f70: aa0403e0 mov x0, x4 - 10f74: aa0103e2 mov x2, x1 - 10f78: d2800103 mov x3, #0x8 // #8 - 10f7c: d2801128 mov x8, #0x89 // #137 - 10f80: d4000001 svc #0x0 - 10f84: 3100101f cmn w0, #0x4 - 10f88: 2a0003e2 mov w2, w0 - 10f8c: 2a0003e3 mov w3, w0 - 10f90: 54fffea0 b.eq 10f64 - 10f94: 3140047f cmn w3, #0x1, lsl #12 - 10f98: 4b0203e0 neg w0, w2 - 10f9c: 54000068 b.hi 10fa8 - 10fa0: b90000a2 str w2, [x5] - 10fa4: 52800000 mov w0, #0x0 // #0 - 10fa8: a94153f3 ldp x19, x20, [sp,#16] - 10fac: a8ca7bfd ldp x29, x30, [sp],#160 - 10fb0: d65f03c0 ret - 10fb4: 925ff442 and x2, x2, #0xfffffffe7fffffff - 10fb8: 910083a4 add x4, x29, #0x20 - 10fbc: f90013a2 str x2, [x29,#32] - 10fc0: 17ffffeb b 10f6c - 10fc4: aa0003f3 mov x19, x0 - 10fc8: aa0103f4 mov x20, x1 - 10fcc: 97fff993 bl f618 <__pthread_enable_asynccancel> - 10fd0: 2a0003e5 mov w5, w0 - 10fd4: b4000093 cbz x19, 10fe4 - 10fd8: f9400260 ldr x0, [x19] - 10fdc: f261041f tst x0, #0x180000000 - 10fe0: 54000341 b.ne 11048 - 10fe4: aa1303e4 mov x4, x19 - 10fe8: 14000003 b 10ff4 - 10fec: 3140041f cmn w0, #0x1, lsl #12 - 10ff0: 54000169 b.ls 1101c - 10ff4: d2800001 mov x1, #0x0 // #0 - 10ff8: aa0403e0 mov x0, x4 - 10ffc: aa0103e2 mov x2, x1 - 11000: d2800103 mov x3, #0x8 // #8 - 11004: d2801128 mov x8, #0x89 // #137 - 11008: d4000001 svc #0x0 - 1100c: 3100101f cmn w0, #0x4 - 11010: 2a0003e1 mov w1, w0 - 11014: 2a0003e2 mov w2, w0 - 11018: 54fffea0 b.eq 10fec - 1101c: 3140045f cmn w2, #0x1, lsl #12 - 11020: 4b0103f3 neg w19, w1 - 11024: 54000068 b.hi 11030 - 11028: b9000281 str w1, [x20] - 1102c: 52800013 mov w19, #0x0 // #0 - 11030: 2a0503e0 mov w0, w5 - 11034: 97fff9a9 bl f6d8 <__pthread_disable_asynccancel> - 11038: 2a1303e0 mov w0, w19 - 1103c: a94153f3 ldp x19, x20, [sp,#16] - 11040: a8ca7bfd ldp x29, x30, [sp],#160 - 11044: d65f03c0 ret - 11048: 925ff400 and x0, x0, #0xfffffffe7fffffff - 1104c: 910083a4 add x4, x29, #0x20 - 11050: f90013a0 str x0, [x29,#32] - 11054: 17ffffe8 b 10ff4 - -0000000000011058 <__libc_sigsuspend>: - 11058: f0000101 adrp x1, 34000 <__GI___pthread_keys+0x3d78> - 1105c: a9be7bfd stp x29, x30, [sp,#-32]! - 11060: 910003fd mov x29, sp - 11064: b9432821 ldr w1, [x1,#808] - 11068: f9000bf3 str x19, [sp,#16] - 1106c: 35000161 cbnz w1, 11098 <__libc_sigsuspend+0x40> - 11070: d2800101 mov x1, #0x8 // #8 - 11074: d28010a8 mov x8, #0x85 // #133 - 11078: d4000001 svc #0x0 - 1107c: b140041f cmn x0, #0x1, lsl #12 - 11080: 540002c8 b.hi 110d8 <__libc_sigsuspend+0x80> - 11084: 2a0003f3 mov w19, w0 - 11088: 2a1303e0 mov w0, w19 - 1108c: f9400bf3 ldr x19, [sp,#16] - 11090: a8c27bfd ldp x29, x30, [sp],#32 - 11094: d65f03c0 ret - 11098: aa0003f3 mov x19, x0 - 1109c: 97fff95f bl f618 <__pthread_enable_asynccancel> - 110a0: d2800101 mov x1, #0x8 // #8 - 110a4: 2a0003e2 mov w2, w0 - 110a8: d28010a8 mov x8, #0x85 // #133 - 110ac: aa1303e0 mov x0, x19 - 110b0: d4000001 svc #0x0 - 110b4: b140041f cmn x0, #0x1, lsl #12 - 110b8: 540001e8 b.hi 110f4 <__libc_sigsuspend+0x9c> - 110bc: 2a0003f3 mov w19, w0 - 110c0: 2a0203e0 mov w0, w2 - 110c4: 97fff985 bl f6d8 <__pthread_disable_asynccancel> - 110c8: 2a1303e0 mov w0, w19 - 110cc: f9400bf3 ldr x19, [sp,#16] - 110d0: a8c27bfd ldp x29, x30, [sp],#32 - 110d4: d65f03c0 ret - 110d8: d53bd041 mrs x1, tpidr_el0 - 110dc: d00000e2 adrp x2, 2f000 <__FRAME_END__+0x18e30> - 110e0: f947c442 ldr x2, [x2,#3976] - 110e4: 4b0003e0 neg w0, w0 - 110e8: 12800013 mov w19, #0xffffffff // #-1 - 110ec: b8226820 str w0, [x1,x2] - 110f0: 17ffffe6 b 11088 <__libc_sigsuspend+0x30> - 110f4: d53bd041 mrs x1, tpidr_el0 - 110f8: d00000e3 adrp x3, 2f000 <__FRAME_END__+0x18e30> - 110fc: f947c463 ldr x3, [x3,#3976] - 11100: 4b0003e0 neg w0, w0 - 11104: 12800013 mov w19, #0xffffffff // #-1 - 11108: b8236820 str w0, [x1,x3] - 1110c: 17ffffed b 110c0 <__libc_sigsuspend+0x68> - -0000000000011110 <__sigsuspend_nocancel>: - 11110: d2800101 mov x1, #0x8 // #8 - 11114: d28010a8 mov x8, #0x85 // #133 - 11118: d4000001 svc #0x0 - 1111c: b140041f cmn x0, #0x1, lsl #12 - 11120: 54000048 b.hi 11128 <__sigsuspend_nocancel+0x18> - 11124: d65f03c0 ret - 11128: d53bd041 mrs x1, tpidr_el0 - 1112c: d00000e2 adrp x2, 2f000 <__FRAME_END__+0x18e30> - 11130: f947c442 ldr x2, [x2,#3976] - 11134: 4b0003e3 neg w3, w0 - 11138: 12800000 mov w0, #0xffffffff // #-1 - 1113c: b8226823 str w3, [x1,x2] - 11140: d65f03c0 ret - -0000000000011144 : - 11144: d53bd043 mrs x3, tpidr_el0 - 11148: 93407c02 sxtw x2, w0 - 1114c: d11bc061 sub x1, x3, #0x6f0 - 11150: d2801068 mov x8, #0x83 // #131 - 11154: b980d420 ldrsw x0, [x1,#212] - 11158: b980d021 ldrsw x1, [x1,#208] - 1115c: ca80fc04 eor x4, x0, x0, asr #63 - 11160: cb80fc80 sub x0, x4, x0, asr #63 - 11164: 93407c00 sxtw x0, w0 - 11168: d4000001 svc #0x0 - 1116c: b140041f cmn x0, #0x1, lsl #12 - 11170: 54000048 b.hi 11178 - 11174: d65f03c0 ret - 11178: d00000e1 adrp x1, 2f000 <__FRAME_END__+0x18e30> - 1117c: f947c421 ldr x1, [x1,#3976] - 11180: 4b0003e2 neg w2, w0 - 11184: 12800000 mov w0, #0xffffffff // #-1 - 11188: b8216862 str w2, [x3,x1] - 1118c: d65f03c0 ret - -0000000000011190 : - 11190: 17ffcfb4 b 5060 <__libc_system@plt> - -0000000000011194 <_IO_flockfile>: - 11194: a9bd7bfd stp x29, x30, [sp,#-48]! - 11198: 910003fd mov x29, sp - 1119c: f9404401 ldr x1, [x0,#136] - 111a0: a90153f3 stp x19, x20, [sp,#16] - 111a4: d53bd054 mrs x20, tpidr_el0 - 111a8: f9400422 ldr x2, [x1,#8] - 111ac: d11bc294 sub x20, x20, #0x6f0 - 111b0: eb14005f cmp x2, x20 - 111b4: 540001a0 b.eq 111e8 <_IO_flockfile+0x54> - 111b8: aa0003f3 mov x19, x0 - 111bc: b9002fbf str wzr, [x29,#44] - 111c0: 52800020 mov w0, #0x1 // #1 - 111c4: 885ffc22 ldaxr w2, [x1] - 111c8: 6b1f005f cmp w2, wzr - 111cc: 54000061 b.ne 111d8 <_IO_flockfile+0x44> - 111d0: 88037c20 stxr w3, w0, [x1] - 111d4: 35ffff83 cbnz w3, 111c4 <_IO_flockfile+0x30> - 111d8: 54000141 b.ne 11200 <_IO_flockfile+0x6c> - 111dc: f9404660 ldr x0, [x19,#136] - 111e0: aa0003e1 mov x1, x0 - 111e4: f9000414 str x20, [x0,#8] - 111e8: b9400420 ldr w0, [x1,#4] - 111ec: a94153f3 ldp x19, x20, [sp,#16] - 111f0: 11000400 add w0, w0, #0x1 - 111f4: b9000420 str w0, [x1,#4] - 111f8: a8c37bfd ldp x29, x30, [sp],#48 - 111fc: d65f03c0 ret - 11200: aa0103e0 mov x0, x1 - 11204: b9002fa2 str w2, [x29,#44] - 11208: 97fff958 bl f768 <__lll_lock_wait_private> - 1120c: 17fffff4 b 111dc <_IO_flockfile+0x48> - -0000000000011210 <_IO_ftrylockfile>: - 11210: f9404402 ldr x2, [x0,#136] - 11214: d53bd041 mrs x1, tpidr_el0 - 11218: d11bc021 sub x1, x1, #0x6f0 - 1121c: d10043ff sub sp, sp, #0x10 - 11220: f9400443 ldr x3, [x2,#8] - 11224: eb01007f cmp x3, x1 - 11228: 54000180 b.eq 11258 <_IO_ftrylockfile+0x48> - 1122c: b9000fff str wzr, [sp,#12] - 11230: 52800023 mov w3, #0x1 // #1 - 11234: 885ffc44 ldaxr w4, [x2] - 11238: 6b1f009f cmp w4, wzr - 1123c: 54000061 b.ne 11248 <_IO_ftrylockfile+0x38> - 11240: 88057c43 stxr w5, w3, [x2] - 11244: 35ffff85 cbnz w5, 11234 <_IO_ftrylockfile+0x24> - 11248: 54000140 b.eq 11270 <_IO_ftrylockfile+0x60> - 1124c: 52800200 mov w0, #0x10 // #16 - 11250: 910043ff add sp, sp, #0x10 - 11254: d65f03c0 ret - 11258: b9400441 ldr w1, [x2,#4] - 1125c: 52800000 mov w0, #0x0 // #0 - 11260: 910043ff add sp, sp, #0x10 - 11264: 11000421 add w1, w1, #0x1 - 11268: b9000441 str w1, [x2,#4] - 1126c: d65f03c0 ret - 11270: f9404402 ldr x2, [x0,#136] - 11274: 52800000 mov w0, #0x0 // #0 - 11278: f9000441 str x1, [x2,#8] - 1127c: b9000443 str w3, [x2,#4] - 11280: 17fffff4 b 11250 <_IO_ftrylockfile+0x40> - -0000000000011284 <_IO_funlockfile>: - 11284: f9404400 ldr x0, [x0,#136] - 11288: b9400401 ldr w1, [x0,#4] - 1128c: 51000421 sub w1, w1, #0x1 - 11290: b9000401 str w1, [x0,#4] - 11294: 34000041 cbz w1, 1129c <_IO_funlockfile+0x18> - 11298: d65f03c0 ret - 1129c: f900041f str xzr, [x0,#8] - 112a0: 885f7c02 ldxr w2, [x0] - 112a4: 8803fc01 stlxr w3, w1, [x0] - 112a8: 35ffffc3 cbnz w3, 112a0 <_IO_funlockfile+0x1c> - 112ac: 7100045f cmp w2, #0x1 - 112b0: 54ffff4d b.le 11298 <_IO_funlockfile+0x14> - 112b4: d2801021 mov x1, #0x81 // #129 - 112b8: d2800022 mov x2, #0x1 // #1 - 112bc: d2800003 mov x3, #0x0 // #0 - 112c0: d2800c48 mov x8, #0x62 // #98 - 112c4: d4000001 svc #0x0 - 112c8: d65f03c0 ret - -00000000000112cc <__libc_sigaction>: - 112cc: a9aa7bfd stp x29, x30, [sp,#-352]! - 112d0: 910003fd mov x29, sp - 112d4: a9025bf5 stp x21, x22, [sp,#32] - 112d8: a90153f3 stp x19, x20, [sp,#16] - 112dc: 2a0003f6 mov w22, w0 - 112e0: aa0103f4 mov x20, x1 - 112e4: aa0203f5 mov x21, x2 - 112e8: b4000581 cbz x1, 11398 <__libc_sigaction+0xcc> - 112ec: 9100c3b3 add x19, x29, #0x30 - 112f0: f8408420 ldr x0, [x1],#8 - 112f4: aa1303e3 mov x3, x19 - 112f8: d2801002 mov x2, #0x80 // #128 - 112fc: f8018460 str x0, [x3],#24 - 11300: aa0303e0 mov x0, x3 - 11304: 97ffcf17 bl 4f60 - 11308: b9408a81 ldr w1, [x20,#136] - 1130c: 93407c20 sxtw x0, w1 - 11310: f9000660 str x0, [x19,#8] - 11314: 37d003c1 tbnz w1, #26, 1138c <__libc_sigaction+0xc0> - 11318: aa1503e2 mov x2, x21 - 1131c: b4000055 cbz x21, 11324 <__libc_sigaction+0x58> - 11320: 910323a2 add x2, x29, #0xc8 - 11324: aa1303e1 mov x1, x19 - 11328: 93407ec0 sxtw x0, w22 - 1132c: d2800103 mov x3, #0x8 // #8 - 11330: d28010c8 mov x8, #0x86 // #134 - 11334: d4000001 svc #0x0 - 11338: b140041f cmn x0, #0x1, lsl #12 - 1133c: 540003e8 b.hi 113b8 <__libc_sigaction+0xec> - 11340: 2a0003f3 mov w19, w0 - 11344: 37f801a0 tbnz w0, #31, 11378 <__libc_sigaction+0xac> - 11348: 37f80180 tbnz w0, #31, 11378 <__libc_sigaction+0xac> - 1134c: b4000175 cbz x21, 11378 <__libc_sigaction+0xac> - 11350: aa1503e0 mov x0, x21 - 11354: f94067a3 ldr x3, [x29,#200] - 11358: 910383a1 add x1, x29, #0xe0 - 1135c: d2801002 mov x2, #0x80 // #128 - 11360: f8008403 str x3, [x0],#8 - 11364: 97ffceff bl 4f60 - 11368: f9406ba0 ldr x0, [x29,#208] - 1136c: b9008aa0 str w0, [x21,#136] - 11370: f9406fa0 ldr x0, [x29,#216] - 11374: f9004aa0 str x0, [x21,#144] - 11378: 2a1303e0 mov w0, w19 - 1137c: a94153f3 ldp x19, x20, [sp,#16] - 11380: a9425bf5 ldp x21, x22, [sp,#32] - 11384: a8d67bfd ldp x29, x30, [sp],#352 - 11388: d65f03c0 ret - 1138c: f9404a80 ldr x0, [x20,#144] - 11390: f9000a60 str x0, [x19,#16] - 11394: 17ffffe1 b 11318 <__libc_sigaction+0x4c> - 11398: b4000262 cbz x2, 113e4 <__libc_sigaction+0x118> - 1139c: 910323a2 add x2, x29, #0xc8 - 113a0: 93407ec0 sxtw x0, w22 - 113a4: d2800103 mov x3, #0x8 // #8 - 113a8: d28010c8 mov x8, #0x86 // #134 - 113ac: d4000001 svc #0x0 - 113b0: b140041f cmn x0, #0x1, lsl #12 - 113b4: 54fffc69 b.ls 11340 <__libc_sigaction+0x74> - 113b8: 4b0003e1 neg w1, w0 - 113bc: d00000e2 adrp x2, 2f000 <__FRAME_END__+0x18e30> - 113c0: f947c442 ldr x2, [x2,#3976] - 113c4: d53bd040 mrs x0, tpidr_el0 - 113c8: 12800013 mov w19, #0xffffffff // #-1 - 113cc: a9425bf5 ldp x21, x22, [sp,#32] - 113d0: b8226801 str w1, [x0,x2] - 113d4: 2a1303e0 mov w0, w19 - 113d8: a94153f3 ldp x19, x20, [sp,#16] - 113dc: a8d67bfd ldp x29, x30, [sp],#352 - 113e0: d65f03c0 ret - 113e4: aa1503e2 mov x2, x21 - 113e8: aa1503e1 mov x1, x21 - 113ec: 17ffffcf b 11328 <__libc_sigaction+0x5c> - -00000000000113f0 <__sigaction>: - 113f0: 51008003 sub w3, w0, #0x20 - 113f4: 7100047f cmp w3, #0x1 - 113f8: 54000049 b.ls 11400 <__sigaction+0x10> - 113fc: 17ffffb4 b 112cc <__libc_sigaction> - 11400: d53bd040 mrs x0, tpidr_el0 - 11404: d00000e1 adrp x1, 2f000 <__FRAME_END__+0x18e30> - 11408: f947c421 ldr x1, [x1,#3976] - 1140c: 528002c2 mov w2, #0x16 // #22 - 11410: b8216802 str w2, [x0,x1] - 11414: 12800000 mov w0, #0xffffffff // #-1 - 11418: d65f03c0 ret - -000000000001141c <__h_errno_location>: - 1141c: a9bf7bfd stp x29, x30, [sp,#-16]! - 11420: f00000e0 adrp x0, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 11424: f9412001 ldr x1, [x0,#576] - 11428: 91090000 add x0, x0, #0x240 - 1142c: d63f0020 blr x1 - 11430: 910003fd mov x29, sp - 11434: d53bd041 mrs x1, tpidr_el0 - 11438: 8b000020 add x0, x1, x0 - 1143c: a8c17bfd ldp x29, x30, [sp],#16 - 11440: d65f03c0 ret - -0000000000011444 <__res_state>: - 11444: d00000e1 adrp x1, 2f000 <__FRAME_END__+0x18e30> - 11448: f947cc21 ldr x1, [x1,#3992] - 1144c: d53bd040 mrs x0, tpidr_el0 - 11450: f8616800 ldr x0, [x0,x1] - 11454: d65f03c0 ret - -0000000000011458 <__libc_current_sigrtmin>: - 11458: 17ffcf92 b 52a0 <__libc_current_sigrtmin_private@plt> - -000000000001145c <__libc_current_sigrtmax>: - 1145c: 17ffcf4d b 5190 <__libc_current_sigrtmax_private@plt> - -0000000000011460 <__libc_allocate_rtsig>: - 11460: 17ffcfcc b 5390 <__libc_allocate_rtsig_private@plt> - -0000000000011464 : - 11464: d65f03c0 ret - -0000000000011468 : - 11468: a9bf7bfd stp x29, x30, [sp,#-16]! - 1146c: aa0103e4 mov x4, x1 - 11470: b2407be1 mov x1, #0x7fffffff // #2147483647 - 11474: eb01009f cmp x4, x1 - 11478: 910003fd mov x29, sp - 1147c: aa0203e5 mov x5, x2 - 11480: 9a819081 csel x1, x4, x1, ls - 11484: b980d000 ldrsw x0, [x0,#208] - 11488: d2800f68 mov x8, #0x7b // #123 - 1148c: d4000001 svc #0x0 - 11490: 3140041f cmn w0, #0x1, lsl #12 - 11494: 54000089 b.ls 114a4 - 11498: 4b0003e0 neg w0, w0 - 1149c: a8c17bfd ldp x29, x30, [sp],#16 - 114a0: d65f03c0 ret - 114a4: 93407c02 sxtw x2, w0 - 114a8: 52800001 mov w1, #0x0 // #0 - 114ac: 8b0200a0 add x0, x5, x2 - 114b0: cb020082 sub x2, x4, x2 - 114b4: 97ffcef7 bl 5090 - 114b8: 52800000 mov w0, #0x0 // #0 - 114bc: a8c17bfd ldp x29, x30, [sp],#16 - 114c0: d65f03c0 ret - -00000000000114c4 <__determine_cpumask_size>: - 114c4: a9bf7bfd stp x29, x30, [sp,#-16]! - 114c8: 93407c06 sxtw x6, w0 - 114cc: d2801004 mov x4, #0x80 // #128 - 114d0: 910003fd mov x29, sp - 114d4: d10243ff sub sp, sp, #0x90 - 114d8: 910003e5 mov x5, sp - 114dc: 1400000b b 11508 <__determine_cpumask_size+0x44> - 114e0: 927cec63 and x3, x3, #0xfffffffffffffff0 - 114e4: 340002a1 cbz w1, 11538 <__determine_cpumask_size+0x74> - 114e8: 91004061 add x1, x3, #0x10 - 114ec: 910003e0 mov x0, sp - 114f0: cb21601f sub sp, x0, x1 - 114f4: 8b040064 add x4, x3, x4 - 114f8: 8b2363e2 add x2, sp, x3 - 114fc: eb0200bf cmp x5, x2 - 11500: 910003e5 mov x5, sp - 11504: 9a830084 csel x4, x4, x3, eq - 11508: aa0603e0 mov x0, x6 - 1150c: aa0403e1 mov x1, x4 - 11510: aa0503e2 mov x2, x5 - 11514: d2800f68 mov x8, #0x7b // #123 - 11518: d4000001 svc #0x0 - 1151c: 3140041f cmn w0, #0x1, lsl #12 - 11520: d37ff883 lsl x3, x4, #1 - 11524: 1a9f97e1 cset w1, hi - 11528: 3100581f cmn w0, #0x16 - 1152c: 93407c02 sxtw x2, w0 - 11530: 91003c63 add x3, x3, #0xf - 11534: 54fffd60 b.eq 114e0 <__determine_cpumask_size+0x1c> - 11538: 34000102 cbz w2, 11558 <__determine_cpumask_size+0x94> - 1153c: 350000e1 cbnz w1, 11558 <__determine_cpumask_size+0x94> - 11540: 2a0103e0 mov w0, w1 - 11544: f0000101 adrp x1, 34000 <__GI___pthread_keys+0x3d78> - 11548: 910003bf mov sp, x29 - 1154c: f901d422 str x2, [x1,#936] - 11550: a8c17bfd ldp x29, x30, [sp],#16 - 11554: d65f03c0 ret - 11558: 910003bf mov sp, x29 - 1155c: 4b0203e0 neg w0, w2 - 11560: a8c17bfd ldp x29, x30, [sp],#16 - 11564: d65f03c0 ret - -0000000000011568 : - 11568: a9bd7bfd stp x29, x30, [sp,#-48]! - 1156c: 910003fd mov x29, sp - 11570: a90153f3 stp x19, x20, [sp,#16] - 11574: f0000113 adrp x19, 34000 <__GI___pthread_keys+0x3d78> - 11578: aa0003f4 mov x20, x0 - 1157c: f941d663 ldr x3, [x19,#936] - 11580: b40002a3 cbz x3, 115d4 - 11584: eb01007f cmp x3, x1 - 11588: 540000a3 b.cc 1159c - 1158c: 1400000a b 115b4 - 11590: 91000463 add x3, x3, #0x1 - 11594: eb03003f cmp x1, x3 - 11598: 540000e9 b.ls 115b4 - 1159c: 38636844 ldrb w4, [x2,x3] - 115a0: 34ffff84 cbz w4, 11590 - 115a4: 528002c0 mov w0, #0x16 // #22 - 115a8: a94153f3 ldp x19, x20, [sp,#16] - 115ac: a8c37bfd ldp x29, x30, [sp],#48 - 115b0: d65f03c0 ret - 115b4: b980d280 ldrsw x0, [x20,#208] - 115b8: d2800f48 mov x8, #0x7a // #122 - 115bc: d4000001 svc #0x0 - 115c0: 3140041f cmn w0, #0x1, lsl #12 - 115c4: 5a8097e0 csneg w0, wzr, w0, ls - 115c8: a94153f3 ldp x19, x20, [sp,#16] - 115cc: a8c37bfd ldp x29, x30, [sp],#48 - 115d0: d65f03c0 ret - 115d4: b940d000 ldr w0, [x0,#208] - 115d8: f90013a2 str x2, [x29,#32] - 115dc: f90017a1 str x1, [x29,#40] - 115e0: 97ffffb9 bl 114c4 <__determine_cpumask_size> - 115e4: 35fffe20 cbnz w0, 115a8 - 115e8: f941d663 ldr x3, [x19,#936] - 115ec: f94013a2 ldr x2, [x29,#32] - 115f0: f94017a1 ldr x1, [x29,#40] - 115f4: 17ffffe4 b 11584 - -00000000000115f8 : - 115f8: a9bd7bfd stp x29, x30, [sp,#-48]! - 115fc: 910003fd mov x29, sp - 11600: f9401405 ldr x5, [x0,#40] - 11604: a90153f3 stp x19, x20, [sp,#16] - 11608: f90013f5 str x21, [sp,#32] - 1160c: aa0103f4 mov x20, x1 - 11610: aa0003f5 mov x21, x0 - 11614: b4000525 cbz x5, 116b8 - 11618: f9401806 ldr x6, [x0,#48] - 1161c: eb06003f cmp x1, x6 - 11620: 54000142 b.cs 11648 - 11624: 386168a1 ldrb w1, [x5,x1] - 11628: 350002c1 cbnz w1, 11680 - 1162c: aa1403e3 mov x3, x20 - 11630: 14000003 b 1163c - 11634: 386368a4 ldrb w4, [x5,x3] - 11638: 35000244 cbnz w4, 11680 - 1163c: 91000463 add x3, x3, #0x1 - 11640: eb06007f cmp x3, x6 - 11644: 54ffff83 b.cc 11634 - 11648: eb06029f cmp x20, x6 - 1164c: aa0203e0 mov x0, x2 - 11650: aa0503e1 mov x1, x5 - 11654: 9a869282 csel x2, x20, x6, ls - 11658: 52800013 mov w19, #0x0 // #0 - 1165c: 97ffcf01 bl 5260 - 11660: f9401aa2 ldr x2, [x21,#48] - 11664: eb02029f cmp x20, x2 - 11668: 54000188 b.hi 11698 - 1166c: 2a1303e0 mov w0, w19 - 11670: f94013f5 ldr x21, [sp,#32] - 11674: a94153f3 ldp x19, x20, [sp,#16] - 11678: a8c37bfd ldp x29, x30, [sp],#48 - 1167c: d65f03c0 ret - 11680: 528002d3 mov w19, #0x16 // #22 - 11684: f94013f5 ldr x21, [sp,#32] - 11688: 2a1303e0 mov w0, w19 - 1168c: a94153f3 ldp x19, x20, [sp,#16] - 11690: a8c37bfd ldp x29, x30, [sp],#48 - 11694: d65f03c0 ret - 11698: 2a1303e1 mov w1, w19 - 1169c: cb020282 sub x2, x20, x2 - 116a0: 97ffce7c bl 5090 - 116a4: f94013f5 ldr x21, [sp,#32] - 116a8: 2a1303e0 mov w0, w19 - 116ac: a94153f3 ldp x19, x20, [sp,#16] - 116b0: a8c37bfd ldp x29, x30, [sp],#48 - 116b4: d65f03c0 ret - 116b8: aa0203e0 mov x0, x2 - 116bc: 12800001 mov w1, #0xffffffff // #-1 - 116c0: aa1403e2 mov x2, x20 - 116c4: 2a0503f3 mov w19, w5 - 116c8: 97ffce72 bl 5090 - 116cc: 17ffffe8 b 1166c - -00000000000116d0 : - 116d0: a9bc7bfd stp x29, x30, [sp,#-64]! - 116d4: 910003fd mov x29, sp - 116d8: a90153f3 stp x19, x20, [sp,#16] - 116dc: f90013f5 str x21, [sp,#32] - 116e0: aa0003f4 mov x20, x0 - 116e4: aa0103f3 mov x19, x1 - 116e8: b40004c2 cbz x2, 11780 - 116ec: b40004a1 cbz x1, 11780 - 116f0: f0000115 adrp x21, 34000 <__GI___pthread_keys+0x3d78> - 116f4: f941d6a3 ldr x3, [x21,#936] - 116f8: b4000563 cbz x3, 117a4 - 116fc: eb03027f cmp x19, x3 - 11700: 540001a9 b.ls 11734 - 11704: 38636840 ldrb w0, [x2,x3] - 11708: 34000100 cbz w0, 11728 - 1170c: 528002c0 mov w0, #0x16 // #22 - 11710: a94153f3 ldp x19, x20, [sp,#16] - 11714: f94013f5 ldr x21, [sp,#32] - 11718: a8c47bfd ldp x29, x30, [sp],#64 - 1171c: d65f03c0 ret - 11720: 38636844 ldrb w4, [x2,x3] - 11724: 35ffff44 cbnz w4, 1170c - 11728: 91000463 add x3, x3, #0x1 - 1172c: eb03027f cmp x19, x3 - 11730: 54ffff88 b.hi 11720 - 11734: f9401a80 ldr x0, [x20,#48] - 11738: eb13001f cmp x0, x19 - 1173c: 54000460 b.eq 117c8 - 11740: f9401680 ldr x0, [x20,#40] - 11744: aa1303e1 mov x1, x19 - 11748: f9001fa2 str x2, [x29,#56] - 1174c: 97ffce71 bl 5110 - 11750: b4000400 cbz x0, 117d0 - 11754: f9401fa2 ldr x2, [x29,#56] - 11758: f9001680 str x0, [x20,#40] - 1175c: f9001a93 str x19, [x20,#48] - 11760: aa0203e1 mov x1, x2 - 11764: aa1303e2 mov x2, x19 - 11768: 97ffcdfe bl 4f60 - 1176c: f94013f5 ldr x21, [sp,#32] - 11770: 52800000 mov w0, #0x0 // #0 - 11774: a94153f3 ldp x19, x20, [sp,#16] - 11778: a8c47bfd ldp x29, x30, [sp],#64 - 1177c: d65f03c0 ret - 11780: f9401680 ldr x0, [x20,#40] - 11784: 97ffcea7 bl 5220 - 11788: f900169f str xzr, [x20,#40] - 1178c: f9001a9f str xzr, [x20,#48] - 11790: 52800000 mov w0, #0x0 // #0 - 11794: a94153f3 ldp x19, x20, [sp,#16] - 11798: f94013f5 ldr x21, [sp,#32] - 1179c: a8c47bfd ldp x29, x30, [sp],#64 - 117a0: d65f03c0 ret - 117a4: d53bd040 mrs x0, tpidr_el0 - 117a8: f9001fa2 str x2, [x29,#56] - 117ac: d11bc000 sub x0, x0, #0x6f0 - 117b0: b940d000 ldr w0, [x0,#208] - 117b4: 97ffff44 bl 114c4 <__determine_cpumask_size> - 117b8: 35fffac0 cbnz w0, 11710 - 117bc: f941d6a3 ldr x3, [x21,#936] - 117c0: f9401fa2 ldr x2, [x29,#56] - 117c4: 17ffffce b 116fc - 117c8: f9401680 ldr x0, [x20,#40] - 117cc: 17ffffe5 b 11760 - 117d0: 52800180 mov w0, #0xc // #12 - 117d4: 17ffffcf b 11710 - -00000000000117d8 : - 117d8: b9400002 ldr w2, [x0] - 117dc: 52800000 mov w0, #0x0 // #0 - 117e0: d35e7842 ubfx x2, x2, #30, #1 - 117e4: b9000022 str w2, [x1] - 117e8: d65f03c0 ret - -00000000000117ec : - 117ec: 350000c1 cbnz w1, 11804 - 117f0: b9400002 ldr w2, [x0] - 117f4: 12017842 and w2, w2, #0xbfffffff - 117f8: b9000002 str w2, [x0] - 117fc: 2a0103e0 mov w0, w1 - 11800: d65f03c0 ret - 11804: 7100043f cmp w1, #0x1 - 11808: 540000e1 b.ne 11824 - 1180c: b9400002 ldr w2, [x0] - 11810: 52800001 mov w1, #0x0 // #0 - 11814: 32020042 orr w2, w2, #0x40000000 - 11818: b9000002 str w2, [x0] - 1181c: 2a0103e0 mov w0, w1 - 11820: d65f03c0 ret - 11824: 528002c1 mov w1, #0x16 // #22 - 11828: 17fffff5 b 117fc - -000000000001182c : - 1182c: b9401002 ldr w2, [x0,#16] - 11830: 528002c1 mov w1, #0x16 // #22 - 11834: 37200062 tbnz w2, #4, 11840 - 11838: 2a0103e0 mov w0, w1 - 1183c: d65f03c0 ret - 11840: b9400803 ldr w3, [x0,#8] - 11844: 12b00002 mov w2, #0x7fffffff // #2147483647 - 11848: 6b02007f cmp w3, w2 - 1184c: 54ffff61 b.ne 11838 - 11850: d53bd042 mrs x2, tpidr_el0 - 11854: 52800001 mov w1, #0x0 // #0 - 11858: d11bc042 sub x2, x2, #0x6f0 - 1185c: b940d042 ldr w2, [x2,#208] - 11860: b9000802 str w2, [x0,#8] - 11864: 17fffff5 b 11838 - -0000000000011868 <__pthread_cleanup_routine>: - 11868: a9bf7bfd stp x29, x30, [sp,#-16]! - 1186c: 910003fd mov x29, sp - 11870: b9401001 ldr w1, [x0,#16] - 11874: 34000081 cbz w1, 11884 <__pthread_cleanup_routine+0x1c> - 11878: f9400001 ldr x1, [x0] - 1187c: f9400400 ldr x0, [x0,#8] - 11880: d63f0020 blr x1 - 11884: a8c17bfd ldp x29, x30, [sp],#16 - 11888: d65f03c0 ret - -000000000001188c : - 1188c: a9bc7bfd stp x29, x30, [sp,#-64]! - 11890: 910003fd mov x29, sp - 11894: a90153f3 stp x19, x20, [sp,#16] - 11898: f0000113 adrp x19, 34000 <__GI___pthread_keys+0x3d78> - 1189c: a9025bf5 stp x21, x22, [sp,#32] - 118a0: a90363f7 stp x23, x24, [sp,#48] - 118a4: f9417660 ldr x0, [x19,#744] - 118a8: 910ba274 add x20, x19, #0x2e8 - 118ac: b40000c0 cbz x0, 118c4 - 118b0: a94153f3 ldp x19, x20, [sp,#16] - 118b4: a9425bf5 ldp x21, x22, [sp,#32] - 118b8: a94363f7 ldp x23, x24, [sp,#48] - 118bc: a8c47bfd ldp x29, x30, [sp],#64 - 118c0: d65f03c0 ret - 118c4: b0000000 adrp x0, 12000 <__pthread_current_priority+0xa8> - 118c8: 320107e1 mov w1, #0x80000001 // #-2147483647 - 118cc: 91354000 add x0, x0, #0xd50 - 118d0: 97ffce38 bl 51b0 <__libc_dlopen_mode@plt> - 118d4: aa0003f5 mov x21, x0 - 118d8: b40004a0 cbz x0, 1196c - 118dc: b0000001 adrp x1, 12000 <__pthread_current_priority+0xa8> - 118e0: 91368021 add x1, x1, #0xda0 - 118e4: 97ffce67 bl 5280 <__libc_dlsym@plt> - 118e8: aa0003f6 mov x22, x0 - 118ec: b4000400 cbz x0, 1196c - 118f0: b0000001 adrp x1, 12000 <__pthread_current_priority+0xa8> - 118f4: aa1503e0 mov x0, x21 - 118f8: 9136c021 add x1, x1, #0xdb0 - 118fc: 97ffce61 bl 5280 <__libc_dlsym@plt> - 11900: aa0003f8 mov x24, x0 - 11904: b4000340 cbz x0, 1196c - 11908: b0000001 adrp x1, 12000 <__pthread_current_priority+0xa8> - 1190c: aa1503e0 mov x0, x21 - 11910: 91372021 add x1, x1, #0xdc8 - 11914: 97ffce5b bl 5280 <__libc_dlsym@plt> - 11918: aa0003f7 mov x23, x0 - 1191c: b4000280 cbz x0, 1196c - 11920: b0000001 adrp x1, 12000 <__pthread_current_priority+0xa8> - 11924: aa1503e0 mov x0, x21 - 11928: 91378021 add x1, x1, #0xde0 - 1192c: 97ffce55 bl 5280 <__libc_dlsym@plt> - 11930: b40001e0 cbz x0, 1196c - 11934: d00000e2 adrp x2, 2f000 <__FRAME_END__+0x18e30> - 11938: f947d042 ldr x2, [x2,#4000] - 1193c: f9400041 ldr x1, [x2] - 11940: ca0102d6 eor x22, x22, x1 - 11944: ca010318 eor x24, x24, x1 - 11948: ca0102f7 eor x23, x23, x1 - 1194c: f9000696 str x22, [x20,#8] - 11950: f9000a98 str x24, [x20,#16] - 11954: ca010001 eor x1, x0, x1 - 11958: f9000e97 str x23, [x20,#24] - 1195c: f9001281 str x1, [x20,#32] - 11960: d5033bbf dmb ish - 11964: f9017675 str x21, [x19,#744] - 11968: 17ffffd2 b 118b0 - 1196c: b0000000 adrp x0, 12000 <__pthread_current_priority+0xa8> - 11970: 91358000 add x0, x0, #0xd60 - 11974: 97ffcd9f bl 4ff0 <__libc_fatal@plt> - -0000000000011978 <_Unwind_Resume>: - 11978: a9bd7bfd stp x29, x30, [sp,#-48]! - 1197c: 910003fd mov x29, sp - 11980: f9000bf3 str x19, [sp,#16] - 11984: f0000113 adrp x19, 34000 <__GI___pthread_keys+0x3d78> - 11988: f9417661 ldr x1, [x19,#744] - 1198c: b4000181 cbz x1, 119bc <_Unwind_Resume+0x44> - 11990: d5033bbf dmb ish - 11994: d00000e2 adrp x2, 2f000 <__FRAME_END__+0x18e30> - 11998: 910ba273 add x19, x19, #0x2e8 - 1199c: f947d042 ldr x2, [x2,#4000] - 119a0: f9400663 ldr x3, [x19,#8] - 119a4: f9400041 ldr x1, [x2] - 119a8: ca010061 eor x1, x3, x1 - 119ac: d63f0020 blr x1 - 119b0: f9400bf3 ldr x19, [sp,#16] - 119b4: a8c37bfd ldp x29, x30, [sp],#48 - 119b8: d65f03c0 ret - 119bc: f90017a0 str x0, [x29,#40] - 119c0: 97ffffb3 bl 1188c - 119c4: f94017a0 ldr x0, [x29,#40] - 119c8: 17fffff3 b 11994 <_Unwind_Resume+0x1c> - -00000000000119cc <__gcc_personality_v0>: - 119cc: a9bb7bfd stp x29, x30, [sp,#-80]! - 119d0: 910003fd mov x29, sp - 119d4: f9000bf3 str x19, [sp,#16] - 119d8: f0000113 adrp x19, 34000 <__GI___pthread_keys+0x3d78> - 119dc: f9417665 ldr x5, [x19,#744] - 119e0: b4000185 cbz x5, 11a10 <__gcc_personality_v0+0x44> - 119e4: d5033bbf dmb ish - 119e8: d00000e6 adrp x6, 2f000 <__FRAME_END__+0x18e30> - 119ec: 910ba273 add x19, x19, #0x2e8 - 119f0: f947d0c6 ldr x6, [x6,#4000] - 119f4: f9400a67 ldr x7, [x19,#16] - 119f8: f94000c5 ldr x5, [x6] - 119fc: ca0500e5 eor x5, x7, x5 - 11a00: d63f00a0 blr x5 - 11a04: f9400bf3 ldr x19, [sp,#16] - 11a08: a8c57bfd ldp x29, x30, [sp],#80 - 11a0c: d65f03c0 ret - 11a10: f90017a4 str x4, [x29,#40] - 11a14: f9001ba3 str x3, [x29,#48] - 11a18: f9001fa2 str x2, [x29,#56] - 11a1c: f90023a1 str x1, [x29,#64] - 11a20: f90027a0 str x0, [x29,#72] - 11a24: 97ffff9a bl 1188c - 11a28: f94027a0 ldr x0, [x29,#72] - 11a2c: f94023a1 ldr x1, [x29,#64] - 11a30: f9401fa2 ldr x2, [x29,#56] - 11a34: f9401ba3 ldr x3, [x29,#48] - 11a38: f94017a4 ldr x4, [x29,#40] - 11a3c: 17ffffeb b 119e8 <__gcc_personality_v0+0x1c> - -0000000000011a40 <_Unwind_ForcedUnwind>: - 11a40: a9bc7bfd stp x29, x30, [sp,#-64]! - 11a44: 910003fd mov x29, sp - 11a48: f9000bf3 str x19, [sp,#16] - 11a4c: f0000113 adrp x19, 34000 <__GI___pthread_keys+0x3d78> - 11a50: f9417663 ldr x3, [x19,#744] - 11a54: b4000183 cbz x3, 11a84 <_Unwind_ForcedUnwind+0x44> - 11a58: d5033bbf dmb ish - 11a5c: d00000e4 adrp x4, 2f000 <__FRAME_END__+0x18e30> - 11a60: 910ba273 add x19, x19, #0x2e8 - 11a64: f947d084 ldr x4, [x4,#4000] - 11a68: f9400e65 ldr x5, [x19,#24] - 11a6c: f9400083 ldr x3, [x4] - 11a70: ca0300a3 eor x3, x5, x3 - 11a74: d63f0060 blr x3 - 11a78: f9400bf3 ldr x19, [sp,#16] - 11a7c: a8c47bfd ldp x29, x30, [sp],#64 - 11a80: d65f03c0 ret - 11a84: f90017a2 str x2, [x29,#40] - 11a88: f9001ba1 str x1, [x29,#48] - 11a8c: f9001fa0 str x0, [x29,#56] - 11a90: 97ffff7f bl 1188c - 11a94: f9401fa0 ldr x0, [x29,#56] - 11a98: f9401ba1 ldr x1, [x29,#48] - 11a9c: f94017a2 ldr x2, [x29,#40] - 11aa0: 17ffffef b 11a5c <_Unwind_ForcedUnwind+0x1c> - -0000000000011aa4 <_Unwind_GetCFA>: - 11aa4: a9bd7bfd stp x29, x30, [sp,#-48]! - 11aa8: 910003fd mov x29, sp - 11aac: f9000bf3 str x19, [sp,#16] - 11ab0: f0000113 adrp x19, 34000 <__GI___pthread_keys+0x3d78> - 11ab4: f9417661 ldr x1, [x19,#744] - 11ab8: b4000181 cbz x1, 11ae8 <_Unwind_GetCFA+0x44> - 11abc: d5033bbf dmb ish - 11ac0: d00000e2 adrp x2, 2f000 <__FRAME_END__+0x18e30> - 11ac4: 910ba273 add x19, x19, #0x2e8 - 11ac8: f947d042 ldr x2, [x2,#4000] - 11acc: f9401263 ldr x3, [x19,#32] - 11ad0: f9400041 ldr x1, [x2] - 11ad4: ca010061 eor x1, x3, x1 - 11ad8: d63f0020 blr x1 - 11adc: f9400bf3 ldr x19, [sp,#16] - 11ae0: a8c37bfd ldp x29, x30, [sp],#48 - 11ae4: d65f03c0 ret - 11ae8: f90017a0 str x0, [x29,#40] - 11aec: 97ffff68 bl 1188c - 11af0: f94017a0 ldr x0, [x29,#40] - 11af4: 17fffff3 b 11ac0 <_Unwind_GetCFA+0x1c> - -0000000000011af8 : - 11af8: b9400002 ldr w2, [x0] - 11afc: 52800000 mov w0, #0x0 // #0 - 11b00: d35c7442 ubfx x2, x2, #28, #2 - 11b04: b9000022 str w2, [x1] - 11b08: d65f03c0 ret - -0000000000011b0c : - 11b0c: 7100083f cmp w1, #0x2 - 11b10: 54000108 b.hi 11b30 - 11b14: b9400002 ldr w2, [x0] - 11b18: 52800003 mov w3, #0x0 // #0 - 11b1c: 12027442 and w2, w2, #0xcfffffff - 11b20: 2a017041 orr w1, w2, w1, lsl #28 - 11b24: b9000001 str w1, [x0] - 11b28: 2a0303e0 mov w0, w3 - 11b2c: d65f03c0 ret - 11b30: 528002c3 mov w3, #0x16 // #22 - 11b34: 2a0303e0 mov w0, w3 - 11b38: d65f03c0 ret - -0000000000011b3c : - 11b3c: a9bd7bfd stp x29, x30, [sp,#-48]! - 11b40: 910003fd mov x29, sp - 11b44: b9400000 ldr w0, [x0] - 11b48: f9000bf3 str x19, [sp,#16] - 11b4c: d34c5c00 ubfx x0, x0, #12, #12 - 11b50: 350000e0 cbnz w0, 11b6c - 11b54: f00000f3 adrp x19, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 11b58: b9427e60 ldr w0, [x19,#636] - 11b5c: 3100041f cmn w0, #0x1 - 11b60: 54000100 b.eq 11b80 - 11b64: 6b1f001f cmp w0, wzr - 11b68: 1a9fa000 csel w0, w0, wzr, ge - 11b6c: b9000020 str w0, [x1] - 11b70: 52800000 mov w0, #0x0 // #0 - 11b74: f9400bf3 ldr x19, [sp,#16] - 11b78: a8c37bfd ldp x29, x30, [sp],#48 - 11b7c: d65f03c0 ret - 11b80: f90017a1 str x1, [x29,#40] - 11b84: 94000026 bl 11c1c <__init_sched_fifo_prio> - 11b88: b9427e60 ldr w0, [x19,#636] - 11b8c: f94017a1 ldr x1, [x29,#40] - 11b90: 17fffff5 b 11b64 - -0000000000011b94 : - 11b94: a9bd7bfd stp x29, x30, [sp,#-48]! - 11b98: 910003fd mov x29, sp - 11b9c: a90153f3 stp x19, x20, [sp,#16] - 11ba0: f00000f4 adrp x20, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 11ba4: aa0003f3 mov x19, x0 - 11ba8: b9427e82 ldr w2, [x20,#636] - 11bac: 3100045f cmn w2, #0x1 - 11bb0: 540002c0 b.eq 11c08 - 11bb4: 6b02003f cmp w1, w2 - 11bb8: 5400020b b.lt 11bf8 - 11bbc: f00000e0 adrp x0, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 11bc0: b9427800 ldr w0, [x0,#632] - 11bc4: 6b00003f cmp w1, w0 - 11bc8: 5400018c b.gt 11bf8 - 11bcc: 12002c20 and w0, w1, #0xfff - 11bd0: 6b00003f cmp w1, w0 - 11bd4: 54000121 b.ne 11bf8 - 11bd8: b9400262 ldr w2, [x19] - 11bdc: 52800000 mov w0, #0x0 // #0 - 11be0: 12084c42 and w2, w2, #0xff000fff - 11be4: 2a013041 orr w1, w2, w1, lsl #12 - 11be8: b9000261 str w1, [x19] - 11bec: a94153f3 ldp x19, x20, [sp,#16] - 11bf0: a8c37bfd ldp x29, x30, [sp],#48 - 11bf4: d65f03c0 ret - 11bf8: 528002c0 mov w0, #0x16 // #22 - 11bfc: a94153f3 ldp x19, x20, [sp,#16] - 11c00: a8c37bfd ldp x29, x30, [sp],#48 - 11c04: d65f03c0 ret - 11c08: f90017a1 str x1, [x29,#40] - 11c0c: 94000004 bl 11c1c <__init_sched_fifo_prio> - 11c10: b9427e82 ldr w2, [x20,#636] - 11c14: f94017a1 ldr x1, [x29,#40] - 11c18: 17ffffe7 b 11bb4 - -0000000000011c1c <__init_sched_fifo_prio>: - 11c1c: a9be7bfd stp x29, x30, [sp,#-32]! - 11c20: 52800020 mov w0, #0x1 // #1 - 11c24: 910003fd mov x29, sp - 11c28: f9000bf3 str x19, [sp,#16] - 11c2c: 97ffcd45 bl 5140 - 11c30: f00000e1 adrp x1, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 11c34: 9109e033 add x19, x1, #0x278 - 11c38: b9027820 str w0, [x1,#632] - 11c3c: 52800020 mov w0, #0x1 // #1 - 11c40: d5033bbf dmb ish - 11c44: 97ffcd7b bl 5230 - 11c48: b9000660 str w0, [x19,#4] - 11c4c: f9400bf3 ldr x19, [sp,#16] - 11c50: a8c27bfd ldp x29, x30, [sp],#32 - 11c54: d65f03c0 ret - -0000000000011c58 <__pthread_tpp_change_priority>: - 11c58: a9ba7bfd stp x29, x30, [sp,#-96]! - 11c5c: 910003fd mov x29, sp - 11c60: a90363f7 stp x23, x24, [sp,#48] - 11c64: d53bd058 mrs x24, tpidr_el0 - 11c68: f90023f9 str x25, [sp,#64] - 11c6c: a9025bf5 stp x21, x22, [sp,#32] - 11c70: d11bc315 sub x21, x24, #0x6f0 - 11c74: 2a0003f6 mov w22, w0 - 11c78: a90153f3 stp x19, x20, [sp,#16] - 11c7c: 2a0103f3 mov w19, w1 - 11c80: f9425ab4 ldr x20, [x21,#1200] - 11c84: b4000df4 cbz x20, 11e40 <__pthread_tpp_change_priority+0x1e8> - 11c88: b9400297 ldr w23, [x20] - 11c8c: 3100067f cmn w19, #0x1 - 11c90: 54000640 b.eq 11d58 <__pthread_tpp_change_priority+0x100> - 11c94: f00000e0 adrp x0, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 11c98: 52800164 mov w4, #0xb // #11 - 11c9c: b9427c01 ldr w1, [x0,#636] - 11ca0: 4b010260 sub w0, w19, w1 - 11ca4: 8b20ca80 add x0, x20, w0, sxtw #2 - 11ca8: b9400402 ldr w2, [x0,#4] - 11cac: 3100045f cmn w2, #0x1 - 11cb0: 54000460 b.eq 11d3c <__pthread_tpp_change_priority+0xe4> - 11cb4: 11000442 add w2, w2, #0x1 - 11cb8: 6b17027f cmp w19, w23 - 11cbc: b9000402 str w2, [x0,#4] - 11cc0: 540004cd b.le 11d58 <__pthread_tpp_change_priority+0x100> - 11cc4: 310006df cmn w22, #0x1 - 11cc8: 54000680 b.eq 11d98 <__pthread_tpp_change_priority+0x140> - 11ccc: 4b0102c2 sub w2, w22, w1 - 11cd0: 8b22ca82 add x2, x20, w2, sxtw #2 - 11cd4: b9400440 ldr w0, [x2,#4] - 11cd8: 51000400 sub w0, w0, #0x1 - 11cdc: b9000440 str w0, [x2,#4] - 11ce0: 350005c0 cbnz w0, 11d98 <__pthread_tpp_change_priority+0x140> - 11ce4: 6b1702df cmp w22, w23 - 11ce8: 54000581 b.ne 11d98 <__pthread_tpp_change_priority+0x140> - 11cec: 6b1302df cmp w22, w19 - 11cf0: 5400054d b.le 11d98 <__pthread_tpp_change_priority+0x140> - 11cf4: 510006d3 sub w19, w22, #0x1 - 11cf8: 6b01027f cmp w19, w1 - 11cfc: 540001ab b.lt 11d30 <__pthread_tpp_change_priority+0xd8> - 11d00: 4b010260 sub w0, w19, w1 - 11d04: 8b20ca80 add x0, x20, w0, sxtw #2 - 11d08: b9400400 ldr w0, [x0,#4] - 11d0c: 34000080 cbz w0, 11d1c <__pthread_tpp_change_priority+0xc4> - 11d10: 14000008 b 11d30 <__pthread_tpp_change_priority+0xd8> - 11d14: b9400400 ldr w0, [x0,#4] - 11d18: 350000c0 cbnz w0, 11d30 <__pthread_tpp_change_priority+0xd8> - 11d1c: 51000673 sub w19, w19, #0x1 - 11d20: 6b01027f cmp w19, w1 - 11d24: 4b010260 sub w0, w19, w1 - 11d28: 8b20ca80 add x0, x20, w0, sxtw #2 - 11d2c: 54ffff4a b.ge 11d14 <__pthread_tpp_change_priority+0xbc> - 11d30: 6b17027f cmp w19, w23 - 11d34: 54000321 b.ne 11d98 <__pthread_tpp_change_priority+0x140> - 11d38: 52800004 mov w4, #0x0 // #0 - 11d3c: 2a0403e0 mov w0, w4 - 11d40: f94023f9 ldr x25, [sp,#64] - 11d44: a94153f3 ldp x19, x20, [sp,#16] - 11d48: a9425bf5 ldp x21, x22, [sp,#32] - 11d4c: a94363f7 ldp x23, x24, [sp,#48] - 11d50: a8c67bfd ldp x29, x30, [sp],#96 - 11d54: d65f03c0 ret - 11d58: 310006df cmn w22, #0x1 - 11d5c: 54fffee0 b.eq 11d38 <__pthread_tpp_change_priority+0xe0> - 11d60: f00000e0 adrp x0, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 11d64: b9427c01 ldr w1, [x0,#636] - 11d68: 4b0102c2 sub w2, w22, w1 - 11d6c: 8b22ca82 add x2, x20, w2, sxtw #2 - 11d70: b9400440 ldr w0, [x2,#4] - 11d74: 51000400 sub w0, w0, #0x1 - 11d78: b9000440 str w0, [x2,#4] - 11d7c: 35fffde0 cbnz w0, 11d38 <__pthread_tpp_change_priority+0xe0> - 11d80: 6b1702df cmp w22, w23 - 11d84: 54fffda1 b.ne 11d38 <__pthread_tpp_change_priority+0xe0> - 11d88: 6b1302df cmp w22, w19 - 11d8c: 54fffb4c b.gt 11cf4 <__pthread_tpp_change_priority+0x9c> - 11d90: 52800004 mov w4, #0x0 // #0 - 11d94: 17ffffea b 11d3c <__pthread_tpp_change_priority+0xe4> - 11d98: b9005bbf str wzr, [x29,#88] - 11d9c: 911062b6 add x22, x21, #0x418 - 11da0: 52800020 mov w0, #0x1 // #1 - 11da4: 885ffec1 ldaxr w1, [x22] - 11da8: 6b1f003f cmp w1, wzr - 11dac: 54000061 b.ne 11db8 <__pthread_tpp_change_priority+0x160> - 11db0: 88027ec0 stxr w2, w0, [x22] - 11db4: 35ffff82 cbnz w2, 11da4 <__pthread_tpp_change_priority+0x14c> - 11db8: 54000080 b.eq 11dc8 <__pthread_tpp_change_priority+0x170> - 11dbc: aa1603e0 mov x0, x22 - 11dc0: b9005ba1 str w1, [x29,#88] - 11dc4: 97fff669 bl f768 <__lll_lock_wait_private> - 11dc8: b9410ea0 ldr w0, [x21,#268] - 11dcc: b9000293 str w19, [x20] - 11dd0: 362805c0 tbz w0, #5, 11e88 <__pthread_tpp_change_priority+0x230> - 11dd4: 121a0004 and w4, w0, #0x40 - 11dd8: 363007a0 tbz w0, #6, 11ecc <__pthread_tpp_change_priority+0x274> - 11ddc: b94432a0 ldr w0, [x21,#1072] - 11de0: b9005ba0 str w0, [x29,#88] - 11de4: 6b00027f cmp w19, w0 - 11de8: 540006cd b.le 11ec0 <__pthread_tpp_change_priority+0x268> - 11dec: b9005bb3 str w19, [x29,#88] - 11df0: b940d2a0 ldr w0, [x21,#208] - 11df4: 910163a2 add x2, x29, #0x58 - 11df8: b94436a1 ldr w1, [x21,#1076] - 11dfc: 97ffcd25 bl 5290 <__sched_setscheduler@plt> - 11e00: 37f80840 tbnz w0, #31, 11f08 <__pthread_tpp_change_priority+0x2b0> - 11e04: 52800014 mov w20, #0x0 // #0 - 11e08: 52800001 mov w1, #0x0 // #0 - 11e0c: 885f7ec0 ldxr w0, [x22] - 11e10: 8802fec1 stlxr w2, w1, [x22] - 11e14: 35ffffc2 cbnz w2, 11e0c <__pthread_tpp_change_priority+0x1b4> - 11e18: 7100041f cmp w0, #0x1 - 11e1c: 2a1403e4 mov w4, w20 - 11e20: 54fff8ed b.le 11d3c <__pthread_tpp_change_priority+0xe4> - 11e24: aa1603e0 mov x0, x22 - 11e28: d2801021 mov x1, #0x81 // #129 - 11e2c: d2800022 mov x2, #0x1 // #1 - 11e30: d2800003 mov x3, #0x0 // #0 - 11e34: d2800c48 mov x8, #0x62 // #98 - 11e38: d4000001 svc #0x0 - 11e3c: 17ffffc0 b 11d3c <__pthread_tpp_change_priority+0xe4> - 11e40: f00000f4 adrp x20, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 11e44: 9109e299 add x25, x20, #0x278 - 11e48: b9400737 ldr w23, [x25,#4] - 11e4c: 310006ff cmn w23, #0x1 - 11e50: 54000720 b.eq 11f34 <__pthread_tpp_change_priority+0x2dc> - 11e54: b9427a82 ldr w2, [x20,#632] - 11e58: d2800021 mov x1, #0x1 // #1 - 11e5c: d2800080 mov x0, #0x4 // #4 - 11e60: 4b170042 sub w2, w2, w23 - 11e64: 11000442 add w2, w2, #0x1 - 11e68: 8b22c800 add x0, x0, w2, sxtw #2 - 11e6c: 97ffcca1 bl 50f0 - 11e70: aa0003f4 mov x20, x0 - 11e74: b4000520 cbz x0, 11f18 <__pthread_tpp_change_priority+0x2c0> - 11e78: 510006f7 sub w23, w23, #0x1 - 11e7c: f9025aa0 str x0, [x21,#1200] - 11e80: b9000017 str w23, [x0] - 11e84: 17ffff82 b 11c8c <__pthread_tpp_change_priority+0x34> - 11e88: b940d2a0 ldr w0, [x21,#208] - 11e8c: 9110c2a1 add x1, x21, #0x430 - 11e90: 97ffcca8 bl 5130 <__sched_getparam@plt> - 11e94: 34000320 cbz w0, 11ef8 <__pthread_tpp_change_priority+0x2a0> - 11e98: d00000e1 adrp x1, 2f000 <__FRAME_END__+0x18e30> - 11e9c: f947c421 ldr x1, [x1,#3976] - 11ea0: b9410ea0 ldr w0, [x21,#268] - 11ea4: b8616b14 ldr w20, [x24,x1] - 11ea8: 36300140 tbz w0, #6, 11ed0 <__pthread_tpp_change_priority+0x278> - 11eac: 35fffaf4 cbnz w20, 11e08 <__pthread_tpp_change_priority+0x1b0> - 11eb0: b94432a0 ldr w0, [x21,#1072] - 11eb4: b9005ba0 str w0, [x29,#88] - 11eb8: 6b00027f cmp w19, w0 - 11ebc: 54fff98c b.gt 11dec <__pthread_tpp_change_priority+0x194> - 11ec0: 6b17001f cmp w0, w23 - 11ec4: 54fff96b b.lt 11df0 <__pthread_tpp_change_priority+0x198> - 11ec8: 17ffffcf b 11e04 <__pthread_tpp_change_priority+0x1ac> - 11ecc: 2a0403f4 mov w20, w4 - 11ed0: b940d2a0 ldr w0, [x21,#208] - 11ed4: 97ffcd17 bl 5330 <__sched_getscheduler@plt> - 11ed8: 3100041f cmn w0, #0x1 - 11edc: b90436a0 str w0, [x21,#1076] - 11ee0: 54000200 b.eq 11f20 <__pthread_tpp_change_priority+0x2c8> - 11ee4: b9410ea0 ldr w0, [x21,#268] - 11ee8: 321a0000 orr w0, w0, #0x40 - 11eec: b9010ea0 str w0, [x21,#268] - 11ef0: 35fff8d4 cbnz w20, 11e08 <__pthread_tpp_change_priority+0x1b0> - 11ef4: 17ffffef b 11eb0 <__pthread_tpp_change_priority+0x258> - 11ef8: b9410ea0 ldr w0, [x21,#268] - 11efc: 321b0000 orr w0, w0, #0x20 - 11f00: b9010ea0 str w0, [x21,#268] - 11f04: 17ffffb4 b 11dd4 <__pthread_tpp_change_priority+0x17c> - 11f08: d00000e0 adrp x0, 2f000 <__FRAME_END__+0x18e30> - 11f0c: f947c400 ldr x0, [x0,#3976] - 11f10: b8606b14 ldr w20, [x24,x0] - 11f14: 17ffffbd b 11e08 <__pthread_tpp_change_priority+0x1b0> - 11f18: 52800184 mov w4, #0xc // #12 - 11f1c: 17ffff88 b 11d3c <__pthread_tpp_change_priority+0xe4> - 11f20: d00000e0 adrp x0, 2f000 <__FRAME_END__+0x18e30> - 11f24: f947c400 ldr x0, [x0,#3976] - 11f28: b8606b14 ldr w20, [x24,x0] - 11f2c: 35fff6f4 cbnz w20, 11e08 <__pthread_tpp_change_priority+0x1b0> - 11f30: 17ffffe0 b 11eb0 <__pthread_tpp_change_priority+0x258> - 11f34: 52800020 mov w0, #0x1 // #1 - 11f38: 97ffcc82 bl 5140 - 11f3c: b9027a80 str w0, [x20,#632] - 11f40: 52800020 mov w0, #0x1 // #1 - 11f44: d5033bbf dmb ish - 11f48: 97ffccba bl 5230 - 11f4c: 2a0003f7 mov w23, w0 - 11f50: b9000720 str w0, [x25,#4] - 11f54: 17ffffc0 b 11e54 <__pthread_tpp_change_priority+0x1fc> - -0000000000011f58 <__pthread_current_priority>: - 11f58: a9bd7bfd stp x29, x30, [sp,#-48]! - 11f5c: 910003fd mov x29, sp - 11f60: a90153f3 stp x19, x20, [sp,#16] - 11f64: d53bd053 mrs x19, tpidr_el0 - 11f68: d11bc273 sub x19, x19, #0x6f0 - 11f6c: b9410e60 ldr w0, [x19,#268] - 11f70: 121b0400 and w0, w0, #0x60 - 11f74: 7101801f cmp w0, #0x60 - 11f78: 540003c0 b.eq 11ff0 <__pthread_current_priority+0x98> - 11f7c: b9002fbf str wzr, [x29,#44] - 11f80: 91106274 add x20, x19, #0x418 - 11f84: 52800020 mov w0, #0x1 // #1 - 11f88: 885ffe81 ldaxr w1, [x20] - 11f8c: 6b1f003f cmp w1, wzr - 11f90: 54000061 b.ne 11f9c <__pthread_current_priority+0x44> - 11f94: 88027e80 stxr w2, w0, [x20] - 11f98: 35ffff82 cbnz w2, 11f88 <__pthread_current_priority+0x30> - 11f9c: 540001e1 b.ne 11fd8 <__pthread_current_priority+0x80> - 11fa0: b9410e60 ldr w0, [x19,#268] - 11fa4: 36280300 tbz w0, #5, 12004 <__pthread_current_priority+0xac> - 11fa8: 363003e0 tbz w0, #6, 12024 <__pthread_current_priority+0xcc> - 11fac: b9443264 ldr w4, [x19,#1072] - 11fb0: 52800001 mov w1, #0x0 // #0 - 11fb4: 885f7e80 ldxr w0, [x20] - 11fb8: 8802fe81 stlxr w2, w1, [x20] - 11fbc: 35ffffc2 cbnz w2, 11fb4 <__pthread_current_priority+0x5c> - 11fc0: 7100041f cmp w0, #0x1 - 11fc4: 5400060c b.gt 12084 <__pthread_current_priority+0x12c> - 11fc8: 2a0403e0 mov w0, w4 - 11fcc: a94153f3 ldp x19, x20, [sp,#16] - 11fd0: a8c37bfd ldp x29, x30, [sp],#48 - 11fd4: d65f03c0 ret - 11fd8: aa1403e0 mov x0, x20 - 11fdc: b9002fa1 str w1, [x29,#44] - 11fe0: 97fff5e2 bl f768 <__lll_lock_wait_private> - 11fe4: b9410e60 ldr w0, [x19,#268] - 11fe8: 372ffe00 tbnz w0, #5, 11fa8 <__pthread_current_priority+0x50> - 11fec: 14000006 b 12004 <__pthread_current_priority+0xac> - 11ff0: b9443264 ldr w4, [x19,#1072] - 11ff4: a94153f3 ldp x19, x20, [sp,#16] - 11ff8: 2a0403e0 mov w0, w4 - 11ffc: a8c37bfd ldp x29, x30, [sp],#48 - 12000: d65f03c0 ret - 12004: b940d260 ldr w0, [x19,#208] - 12008: 9110c261 add x1, x19, #0x430 - 1200c: 97ffcc49 bl 5130 <__sched_getparam@plt> - 12010: 350001e0 cbnz w0, 1204c <__pthread_current_priority+0xf4> - 12014: b9410e60 ldr w0, [x19,#268] - 12018: 321b0000 orr w0, w0, #0x20 - 1201c: b9010e60 str w0, [x19,#268] - 12020: 3737fc60 tbnz w0, #6, 11fac <__pthread_current_priority+0x54> - 12024: b940d260 ldr w0, [x19,#208] - 12028: 97ffccc2 bl 5330 <__sched_getscheduler@plt> - 1202c: 3100041f cmn w0, #0x1 - 12030: b9043660 str w0, [x19,#1076] - 12034: 54000100 b.eq 12054 <__pthread_current_priority+0xfc> - 12038: b9410e60 ldr w0, [x19,#268] - 1203c: b9443264 ldr w4, [x19,#1072] - 12040: 321a0000 orr w0, w0, #0x40 - 12044: b9010e60 str w0, [x19,#268] - 12048: 17ffffda b 11fb0 <__pthread_current_priority+0x58> - 1204c: b9410e60 ldr w0, [x19,#268] - 12050: 36300060 tbz w0, #6, 1205c <__pthread_current_priority+0x104> - 12054: 12800004 mov w4, #0xffffffff // #-1 - 12058: 17ffffd6 b 11fb0 <__pthread_current_priority+0x58> - 1205c: b940d260 ldr w0, [x19,#208] - 12060: 97ffccb4 bl 5330 <__sched_getscheduler@plt> - 12064: 3100041f cmn w0, #0x1 - 12068: b9043660 str w0, [x19,#1076] - 1206c: 54ffff40 b.eq 12054 <__pthread_current_priority+0xfc> - 12070: b9410e60 ldr w0, [x19,#268] - 12074: 12800004 mov w4, #0xffffffff // #-1 - 12078: 321a0000 orr w0, w0, #0x40 - 1207c: b9010e60 str w0, [x19,#268] - 12080: 17ffffcc b 11fb0 <__pthread_current_priority+0x58> - 12084: aa1403e0 mov x0, x20 - 12088: d2801021 mov x1, #0x81 // #129 - 1208c: d2800022 mov x2, #0x1 // #1 - 12090: d2800003 mov x3, #0x0 // #0 - 12094: d2800c48 mov x8, #0x62 // #98 - 12098: d4000001 svc #0x0 - 1209c: 17ffffcb b 11fc8 <__pthread_current_priority+0x70> - -00000000000120a0 : - 120a0: b9401002 ldr w2, [x0,#16] - 120a4: 363000c2 tbz w2, #6, 120bc - 120a8: b9400002 ldr w2, [x0] - 120ac: 52800000 mov w0, #0x0 // #0 - 120b0: 53137c42 lsr w2, w2, #19 - 120b4: b9000022 str w2, [x1] - 120b8: d65f03c0 ret - 120bc: 528002c0 mov w0, #0x16 // #22 - 120c0: d65f03c0 ret - -00000000000120c4 : - 120c4: a9bc7bfd stp x29, x30, [sp,#-64]! - 120c8: 910003fd mov x29, sp - 120cc: a90153f3 stp x19, x20, [sp,#16] - 120d0: a9025bf5 stp x21, x22, [sp,#32] - 120d4: aa0003f3 mov x19, x0 - 120d8: 2a0103f4 mov w20, w1 - 120dc: b9401000 ldr w0, [x0,#16] - 120e0: aa0203f5 mov x21, x2 - 120e4: 373000c0 tbnz w0, #6, 120fc - 120e8: 528002c0 mov w0, #0x16 // #22 - 120ec: a94153f3 ldp x19, x20, [sp,#16] - 120f0: a9425bf5 ldp x21, x22, [sp,#32] - 120f4: a8c47bfd ldp x29, x30, [sp],#64 - 120f8: d65f03c0 ret - 120fc: d00000f6 adrp x22, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 12100: b9427ec0 ldr w0, [x22,#636] - 12104: 3100041f cmn w0, #0x1 - 12108: 54000dc0 b.eq 122c0 - 1210c: 6b00029f cmp w20, w0 - 12110: 54fffecb b.lt 120e8 - 12114: d00000e0 adrp x0, 30000 <_GLOBAL_OFFSET_TABLE_+0x88> - 12118: b9427800 ldr w0, [x0,#632] - 1211c: 6b00029f cmp w20, w0 - 12120: 54fffe4c b.gt 120e8 - 12124: 12002e80 and w0, w20, #0xfff - 12128: 6b00029f cmp w20, w0 - 1212c: 54fffde1 b.ne 120e8 - 12130: d53bd040 mrs x0, tpidr_el0 - 12134: b9400a61 ldr w1, [x19,#8] - 12138: d11bc000 sub x0, x0, #0x6f0 - 1213c: b9401262 ldr w2, [x19,#16] - 12140: b940d000 ldr w0, [x0,#208] - 12144: 6b00003f cmp w1, w0 - 12148: 54000960 b.eq 12274 - 1214c: b9400264 ldr w4, [x19] - 12150: 120d3084 and w4, w4, #0xfff80000 - 12154: b9003fa4 str w4, [x29,#60] - 12158: 32000086 orr w6, w4, #0x1 - 1215c: 885ffe60 ldaxr w0, [x19] - 12160: 6b04001f cmp w0, w4 - 12164: 54000061 b.ne 12170 - 12168: 88017e66 stxr w1, w6, [x19] - 1216c: 35ffff81 cbnz w1, 1215c - 12170: 54000040 b.eq 12178 - 12174: b9003fa0 str w0, [x29,#60] - 12178: b9403fa0 ldr w0, [x29,#60] - 1217c: 6b00009f cmp w4, w0 - 12180: 540009c0 b.eq 122b8 - 12184: 321f0087 orr w7, w4, #0x2 - 12188: 9100f3aa add x10, x29, #0x3c - 1218c: 93407ce9 sxtw x9, w7 - 12190: b9003fa6 str w6, [x29,#60] - 12194: 2a0603e0 mov w0, w6 - 12198: 885ffe61 ldaxr w1, [x19] - 1219c: 6b00003f cmp w1, w0 - 121a0: 54000061 b.ne 121ac - 121a4: 88027e67 stxr w2, w7, [x19] - 121a8: 35ffff82 cbnz w2, 12198 - 121ac: 54000040 b.eq 121b4 - 121b0: b9000141 str w1, [x10] - 121b4: b9403fa5 ldr w5, [x29,#60] - 121b8: aa1303e0 mov x0, x19 - 121bc: aa0903e2 mov x2, x9 - 121c0: d2800003 mov x3, #0x0 // #0 - 121c4: 120d30a1 and w1, w5, #0xfff80000 - 121c8: d2800c48 mov x8, #0x62 // #98 - 121cc: 6b04003f cmp w1, w4 - 121d0: 54000261 b.ne 1221c - 121d4: 6b05009f cmp w4, w5 - 121d8: 540000a0 b.eq 121ec - 121dc: b9401261 ldr w1, [x19,#16] - 121e0: 2a2103e1 mvn w1, w1 - 121e4: 92790021 and x1, x1, #0x80 - 121e8: d4000001 svc #0x0 - 121ec: b9003fa4 str w4, [x29,#60] - 121f0: 2a0403e0 mov w0, w4 - 121f4: 885ffe61 ldaxr w1, [x19] - 121f8: 6b00003f cmp w1, w0 - 121fc: 54000061 b.ne 12208 - 12200: 88027e67 stxr w2, w7, [x19] - 12204: 35ffff82 cbnz w2, 121f4 - 12208: 54000040 b.eq 12210 - 1220c: b9000141 str w1, [x10] - 12210: b9403fa0 ldr w0, [x29,#60] - 12214: 6b00009f cmp w4, w0 - 12218: 54fffbc1 b.ne 12190 - 1221c: 53137ca5 lsr w5, w5, #19 - 12220: b4000075 cbz x21, 1222c - 12224: b90002a5 str w5, [x21] - 12228: 52800015 mov w21, #0x0 // #0 - 1222c: 2a144eb4 orr w20, w21, w20, lsl #19 - 12230: b9000274 str w20, [x19] - 12234: aa1303e0 mov x0, x19 - 12238: b2407be2 mov x2, #0x7fffffff // #2147483647 - 1223c: d5033bbf dmb ish - 12240: b9401261 ldr w1, [x19,#16] - 12244: d2800003 mov x3, #0x0 // #0 - 12248: d2800c48 mov x8, #0x62 // #98 - 1224c: 12190024 and w4, w1, #0x80 - 12250: 52801021 mov w1, #0x81 // #129 - 12254: 4a010081 eor w1, w4, w1 - 12258: 93407c21 sxtw x1, w1 - 1225c: d4000001 svc #0x0 - 12260: 2a0303e0 mov w0, w3 - 12264: a94153f3 ldp x19, x20, [sp,#16] - 12268: a9425bf5 ldp x21, x22, [sp,#32] - 1226c: a8c47bfd ldp x29, x30, [sp],#64 - 12270: d65f03c0 ret - 12274: 12001842 and w2, w2, #0x7f - 12278: 52800460 mov w0, #0x23 // #35 - 1227c: 7101085f cmp w2, #0x42 - 12280: 54fff360 b.eq 120ec - 12284: 7101045f cmp w2, #0x41 - 12288: 54fff621 b.ne 1214c - 1228c: b9400276 ldr w22, [x19] - 12290: 2a1403e1 mov w1, w20 - 12294: 53137ed6 lsr w22, w22, #19 - 12298: 2a1603e0 mov w0, w22 - 1229c: 97fffe6f bl 11c58 <__pthread_tpp_change_priority> - 122a0: 35fff260 cbnz w0, 120ec - 122a4: b4000055 cbz x21, 122ac - 122a8: b90002b6 str w22, [x21] - 122ac: b9400275 ldr w21, [x19] - 122b0: 12004ab5 and w21, w21, #0x7ffff - 122b4: 17ffffde b 1222c - 122b8: 2a0403e5 mov w5, w4 - 122bc: 17ffffd8 b 1221c - 122c0: 97fffe57 bl 11c1c <__init_sched_fifo_prio> - 122c4: b9427ec0 ldr w0, [x22,#636] - 122c8: 17ffff91 b 1210c - -00000000000122cc : - 122cc: a9ba7bfd stp x29, x30, [sp,#-96]! - 122d0: 910003fd mov x29, sp - 122d4: a9025bf5 stp x21, x22, [sp,#32] - 122d8: aa0003f5 mov x21, x0 - 122dc: aa0103e0 mov x0, x1 - 122e0: a90153f3 stp x19, x20, [sp,#16] - 122e4: f9001bf7 str x23, [sp,#48] - 122e8: aa0103f4 mov x20, x1 - 122ec: 97ffcb25 bl 4f80 - 122f0: f1003c1f cmp x0, #0xf - 122f4: aa0003f3 mov x19, x0 - 122f8: 52800440 mov w0, #0x22 // #34 - 122fc: 540000c9 b.ls 12314 - 12300: a94153f3 ldp x19, x20, [sp,#16] - 12304: a9425bf5 ldp x21, x22, [sp,#32] - 12308: f9401bf7 ldr x23, [sp,#48] - 1230c: a8c67bfd ldp x29, x30, [sp],#96 - 12310: d65f03c0 ret - 12314: d53bd056 mrs x22, tpidr_el0 - 12318: d11bc2c0 sub x0, x22, #0x6f0 - 1231c: eb0002bf cmp x21, x0 - 12320: 540004e0 b.eq 123bc - 12324: b940d2a2 ldr w2, [x21,#208] - 12328: 90000001 adrp x1, 12000 <__pthread_current_priority+0xa8> - 1232c: 910103a0 add x0, x29, #0x40 - 12330: 9137c021 add x1, x1, #0xdf0 - 12334: aa0003f5 mov x21, x0 - 12338: 97ffcb3a bl 5020 - 1233c: aa1503e0 mov x0, x21 - 12340: 52800041 mov w1, #0x2 // #2 - 12344: 97fff8f8 bl 10724 <__open_nocancel> - 12348: 3100041f cmn w0, #0x1 - 1234c: 2a0003f5 mov w21, w0 - 12350: 540003e0 b.eq 123cc - 12354: b00000f7 adrp x23, 2f000 <__FRAME_END__+0x18e30> - 12358: f947c6f7 ldr x23, [x23,#3976] - 1235c: 14000004 b 1236c - 12360: b8776ac3 ldr w3, [x22,x23] - 12364: 7100107f cmp w3, #0x4 - 12368: 54000181 b.ne 12398 - 1236c: 2a1503e0 mov w0, w21 - 12370: aa1403e1 mov x1, x20 - 12374: aa1303e2 mov x2, x19 - 12378: 97fff61e bl fbf0 <__write_nocancel> - 1237c: 93407c00 sxtw x0, w0 - 12380: b100041f cmn x0, #0x1 - 12384: 54fffee0 b.eq 12360 - 12388: b7f802a0 tbnz x0, #63, 123dc - 1238c: eb13001f cmp x0, x19 - 12390: 528000a3 mov w3, #0x5 // #5 - 12394: 1a8303e3 csel w3, wzr, w3, eq - 12398: 93407ea0 sxtw x0, w21 - 1239c: d2800728 mov x8, #0x39 // #57 - 123a0: d4000001 svc #0x0 - 123a4: 2a0303e0 mov w0, w3 - 123a8: f9401bf7 ldr x23, [sp,#48] - 123ac: a94153f3 ldp x19, x20, [sp,#16] - 123b0: a9425bf5 ldp x21, x22, [sp,#32] - 123b4: a8c67bfd ldp x29, x30, [sp],#96 - 123b8: d65f03c0 ret - 123bc: 528001e0 mov w0, #0xf // #15 - 123c0: aa1403e1 mov x1, x20 - 123c4: 97ffcbef bl 5380 - 123c8: 34fff9c0 cbz w0, 12300 - 123cc: b00000e0 adrp x0, 2f000 <__FRAME_END__+0x18e30> - 123d0: f947c400 ldr x0, [x0,#3976] - 123d4: b8606ac0 ldr w0, [x22,x0] - 123d8: 17ffffca b 12300 - 123dc: b00000e0 adrp x0, 2f000 <__FRAME_END__+0x18e30> - 123e0: f947c400 ldr x0, [x0,#3976] - 123e4: b8606ac3 ldr w3, [x22,x0] - 123e8: 17ffffec b 12398 - -00000000000123ec : - 123ec: a9ba7bfd stp x29, x30, [sp,#-96]! - 123f0: f1003c5f cmp x2, #0xf - 123f4: aa0003e3 mov x3, x0 - 123f8: 910003fd mov x29, sp - 123fc: a90153f3 stp x19, x20, [sp,#16] - 12400: a9025bf5 stp x21, x22, [sp,#32] - 12404: f9001bf7 str x23, [sp,#48] - 12408: aa0103f4 mov x20, x1 - 1240c: 52800440 mov w0, #0x22 // #34 - 12410: 540000c8 b.hi 12428 - 12414: a94153f3 ldp x19, x20, [sp,#16] - 12418: a9425bf5 ldp x21, x22, [sp,#32] - 1241c: f9401bf7 ldr x23, [sp,#48] - 12420: a8c67bfd ldp x29, x30, [sp],#96 - 12424: d65f03c0 ret - 12428: d53bd056 mrs x22, tpidr_el0 - 1242c: aa0203f3 mov x19, x2 - 12430: d11bc2c0 sub x0, x22, #0x6f0 - 12434: eb00007f cmp x3, x0 - 12438: 54000580 b.eq 124e8 - 1243c: 910103b5 add x21, x29, #0x40 - 12440: b940d062 ldr w2, [x3,#208] - 12444: 90000001 adrp x1, 12000 <__pthread_current_priority+0xa8> - 12448: aa1503e0 mov x0, x21 - 1244c: 9137c021 add x1, x1, #0xdf0 - 12450: 97ffcaf4 bl 5020 - 12454: aa1503e0 mov x0, x21 - 12458: 52800001 mov w1, #0x0 // #0 - 1245c: 97fff8b2 bl 10724 <__open_nocancel> - 12460: 3100041f cmn w0, #0x1 - 12464: 2a0003f5 mov w21, w0 - 12468: 54000460 b.eq 124f4 - 1246c: b00000f7 adrp x23, 2f000 <__FRAME_END__+0x18e30> - 12470: f947c6f7 ldr x23, [x23,#3976] - 12474: 14000004 b 12484 - 12478: b8776ac3 ldr w3, [x22,x23] - 1247c: 7100107f cmp w3, #0x4 - 12480: 54000221 b.ne 124c4 - 12484: 2a1503e0 mov w0, w21 - 12488: aa1403e1 mov x1, x20 - 1248c: aa1303e2 mov x2, x19 - 12490: 97fff5f4 bl fc60 <__read_nocancel> - 12494: 93407c03 sxtw x3, w0 - 12498: b100047f cmn x3, #0x1 - 1249c: 54fffee0 b.eq 12478 - 124a0: b7f803c3 tbnz x3, #63, 12518 - 124a4: d1000460 sub x0, x3, #0x1 - 124a8: 38606a81 ldrb w1, [x20,x0] - 124ac: 7100283f cmp w1, #0xa - 124b0: 540002a0 b.eq 12504 - 124b4: eb03027f cmp x19, x3 - 124b8: 540002c0 b.eq 12510 - 124bc: 38236a9f strb wzr, [x20,x3] - 124c0: 52800003 mov w3, #0x0 // #0 - 124c4: 93407ea0 sxtw x0, w21 - 124c8: d2800728 mov x8, #0x39 // #57 - 124cc: d4000001 svc #0x0 - 124d0: 2a0303e0 mov w0, w3 - 124d4: f9401bf7 ldr x23, [sp,#48] - 124d8: a94153f3 ldp x19, x20, [sp,#16] - 124dc: a9425bf5 ldp x21, x22, [sp,#32] - 124e0: a8c67bfd ldp x29, x30, [sp],#96 - 124e4: d65f03c0 ret - 124e8: 52800200 mov w0, #0x10 // #16 - 124ec: 97ffcba5 bl 5380 - 124f0: 34fff920 cbz w0, 12414 - 124f4: b00000e0 adrp x0, 2f000 <__FRAME_END__+0x18e30> - 124f8: f947c400 ldr x0, [x0,#3976] - 124fc: b8606ac0 ldr w0, [x22,x0] - 12500: 17ffffc5 b 12414 - 12504: 38206a9f strb wzr, [x20,x0] - 12508: 52800003 mov w3, #0x0 // #0 - 1250c: 17ffffee b 124c4 - 12510: 52800443 mov w3, #0x22 // #34 - 12514: 17ffffec b 124c4 - 12518: b00000e0 adrp x0, 2f000 <__FRAME_END__+0x18e30> - 1251c: f947c400 ldr x0, [x0,#3976] - 12520: b8606ac3 ldr w3, [x22,x0] - 12524: 17ffffe8 b 124c4 - -0000000000012528 : - 12528: a9b87bfd stp x29, x30, [sp,#-128]! - 1252c: 910003fd mov x29, sp - 12530: a90153f3 stp x19, x20, [sp,#16] - 12534: b9400413 ldr w19, [x0,#4] - 12538: a9025bf5 stp x21, x22, [sp,#32] - 1253c: a90363f7 stp x23, x24, [sp,#48] - 12540: a9046bf9 stp x25, x26, [sp,#64] - 12544: a90573fb stp x27, x28, [sp,#80] - 12548: 71000a7f cmp w19, #0x2 - 1254c: fd0033e8 str d8, [sp,#96] - 12550: 54000188 b.hi 12580 - 12554: b9400015 ldr w21, [x0] - 12558: aa0003f4 mov x20, x0 - 1255c: 6b1f02bf cmp w21, wzr - 12560: 540002cd b.le 125b8 - 12564: 2a1303e0 mov w0, w19 - 12568: 97ffcb06 bl 5180 <__sched_get_priority_min@plt> - 1256c: 2a0003f6 mov w22, w0 - 12570: 2a1303e0 mov w0, w19 - 12574: 97ffcb77 bl 5350 <__sched_get_priority_max@plt> - 12578: 37f80056 tbnz w22, #31, 12580 - 1257c: 36f80160 tbz w0, #31, 125a8 - 12580: 528002c4 mov w4, #0x16 // #22 - 12584: 2a0403e0 mov w0, w4 - 12588: a94153f3 ldp x19, x20, [sp,#16] - 1258c: a9425bf5 ldp x21, x22, [sp,#32] - 12590: a94363f7 ldp x23, x24, [sp,#48] - 12594: a9446bf9 ldp x25, x26, [sp,#64] - 12598: a94573fb ldp x27, x28, [sp,#80] - 1259c: fd4033e8 ldr d8, [sp,#96] - 125a0: a8c87bfd ldp x29, x30, [sp],#128 - 125a4: d65f03c0 ret - 125a8: 6b1602bf cmp w21, w22 - 125ac: 54fffeab b.lt 12580 - 125b0: 6b0002bf cmp w21, w0 - 125b4: 54fffe6c b.gt 12580 - 125b8: d0000116 adrp x22, 34000 <__GI___pthread_keys+0x3d78> - 125bc: f9401695 ldr x21, [x20,#40] - 125c0: f9401a93 ldr x19, [x20,#48] - 125c4: f941d6c1 ldr x1, [x22,#936] - 125c8: b40009c1 cbz x1, 12700 - 125cc: eb01027f cmp x19, x1 - 125d0: 54000129 b.ls 125f4 - 125d4: 38616aa0 ldrb w0, [x21,x1] - 125d8: 34000080 cbz w0, 125e8 - 125dc: 17ffffe9 b 12580 - 125e0: 38616aa2 ldrb w2, [x21,x1] - 125e4: 35fffce2 cbnz w2, 12580 - 125e8: 91000421 add x1, x1, #0x1 - 125ec: eb01027f cmp x19, x1 - 125f0: 54ffff88 b.hi 125e0 - 125f4: f9401295 ldr x21, [x20,#32] - 125f8: b27f3fe0 mov x0, #0x1fffe // #131070 - 125fc: d10006a1 sub x1, x21, #0x1 - 12600: eb00003f cmp x1, x0 - 12604: 54fffbe9 b.ls 12580 - 12608: b9400a93 ldr w19, [x20,#8] - 1260c: 121d0260 and w0, w19, #0x8 - 12610: 371ffb93 tbnz w19, #3, 12580 - 12614: b9007fa0 str w0, [x29,#124] - 12618: d0000116 adrp x22, 34000 <__GI___pthread_keys+0x3d78> - 1261c: b9400280 ldr w0, [x20] - 12620: 52800021 mov w1, #0x1 // #1 - 12624: b940069c ldr w28, [x20,#4] - 12628: f9400a9b ldr x27, [x20,#16] - 1262c: f9400e9a ldr x26, [x20,#24] - 12630: f9401699 ldr x25, [x20,#40] - 12634: f9401a97 ldr x23, [x20,#48] - 12638: 1e270008 fmov s8, w0 - 1263c: 910a22c0 add x0, x22, #0x288 - 12640: 885ffc02 ldaxr w2, [x0] - 12644: 6b1f005f cmp w2, wzr - 12648: 54000061 b.ne 12654 - 1264c: 88037c01 stxr w3, w1, [x0] - 12650: 35ffff83 cbnz w3, 12640 - 12654: 54000060 b.eq 12660 - 12658: b9007fa2 str w2, [x29,#124] - 1265c: 97fff443 bl f768 <__lll_lock_wait_private> - 12660: d0000118 adrp x24, 34000 <__GI___pthread_keys+0x3d78> - 12664: 910cc300 add x0, x24, #0x330 - 12668: b40005d7 cbz x23, 12720 - 1266c: f9401801 ldr x1, [x0,#48] - 12670: eb17003f cmp x1, x23 - 12674: 540005c0 b.eq 1272c - 12678: f9401400 ldr x0, [x0,#40] - 1267c: aa1703e1 mov x1, x23 - 12680: 97ffcaa4 bl 5110 - 12684: aa0003f9 mov x25, x0 - 12688: b40005e0 cbz x0, 12744 - 1268c: f9401681 ldr x1, [x20,#40] - 12690: aa1703e2 mov x2, x23 - 12694: 97ffca33 bl 4f60 - 12698: b5000075 cbnz x21, 126a4 - 1269c: 910cc300 add x0, x24, #0x330 - 126a0: f9401015 ldr x21, [x0,#32] - 126a4: 910cc303 add x3, x24, #0x330 - 126a8: bd033308 str s8, [x24,#816] - 126ac: 52800004 mov w4, #0x0 // #0 - 126b0: b900047c str w28, [x3,#4] - 126b4: b9000873 str w19, [x3,#8] - 126b8: f900087b str x27, [x3,#16] - 126bc: f9000c7a str x26, [x3,#24] - 126c0: f9001075 str x21, [x3,#32] - 126c4: f9001479 str x25, [x3,#40] - 126c8: f9001877 str x23, [x3,#48] - 126cc: 910a22c0 add x0, x22, #0x288 - 126d0: 52800002 mov w2, #0x0 // #0 - 126d4: 885f7c01 ldxr w1, [x0] - 126d8: 8803fc02 stlxr w3, w2, [x0] - 126dc: 35ffffc3 cbnz w3, 126d4 - 126e0: 7100043f cmp w1, #0x1 - 126e4: 54fff50d b.le 12584 - 126e8: d2801021 mov x1, #0x81 // #129 - 126ec: d2800022 mov x2, #0x1 // #1 - 126f0: d2800003 mov x3, #0x0 // #0 - 126f4: d2800c48 mov x8, #0x62 // #98 - 126f8: d4000001 svc #0x0 - 126fc: 17ffffa2 b 12584 - 12700: d53bd040 mrs x0, tpidr_el0 - 12704: d11bc000 sub x0, x0, #0x6f0 - 12708: b940d000 ldr w0, [x0,#208] - 1270c: 97fffb6e bl 114c4 <__determine_cpumask_size> - 12710: 2a0003e4 mov w4, w0 - 12714: 35fff380 cbnz w0, 12584 - 12718: f941d6c1 ldr x1, [x22,#936] - 1271c: 17ffffac b 125cc - 12720: f9401400 ldr x0, [x0,#40] - 12724: 97ffcabf bl 5220 - 12728: 17ffffdc b 12698 - 1272c: f9401419 ldr x25, [x0,#40] - 12730: aa1703e2 mov x2, x23 - 12734: f9401681 ldr x1, [x20,#40] - 12738: aa1903e0 mov x0, x25 - 1273c: 97ffca09 bl 4f60 - 12740: 17ffffd6 b 12698 - 12744: 52800184 mov w4, #0xc // #12 - 12748: 17ffffe1 b 126cc - -000000000001274c : - 1274c: a9bd7bfd stp x29, x30, [sp,#-48]! - 12750: 52800021 mov w1, #0x1 // #1 - 12754: 910003fd mov x29, sp - 12758: a90153f3 stp x19, x20, [sp,#16] - 1275c: d0000113 adrp x19, 34000 <__GI___pthread_keys+0x3d78> - 12760: aa0003f4 mov x20, x0 - 12764: b9002fbf str wzr, [x29,#44] - 12768: 910a2260 add x0, x19, #0x288 - 1276c: 885ffc02 ldaxr w2, [x0] - 12770: 6b1f005f cmp w2, wzr - 12774: 54000061 b.ne 12780 - 12778: 88037c01 stxr w3, w1, [x0] - 1277c: 35ffff83 cbnz w3, 1276c - 12780: 540002c1 b.ne 127d8 - 12784: d0000101 adrp x1, 34000 <__GI___pthread_keys+0x3d78> - 12788: 910a2262 add x2, x19, #0x288 - 1278c: 910cc021 add x1, x1, #0x330 - 12790: a9401424 ldp x4, x5, [x1] - 12794: a9001684 stp x4, x5, [x20] - 12798: a9411424 ldp x4, x5, [x1,#16] - 1279c: a9011684 stp x4, x5, [x20,#16] - 127a0: a9421424 ldp x4, x5, [x1,#32] - 127a4: a9021684 stp x4, x5, [x20,#32] - 127a8: f9401820 ldr x0, [x1,#48] - 127ac: 52800001 mov w1, #0x0 // #0 - 127b0: f9001a80 str x0, [x20,#48] - 127b4: 885f7c40 ldxr w0, [x2] - 127b8: 8803fc41 stlxr w3, w1, [x2] - 127bc: 35ffffc3 cbnz w3, 127b4 - 127c0: 7100041f cmp w0, #0x1 - 127c4: 5400010c b.gt 127e4 - 127c8: 52800000 mov w0, #0x0 // #0 - 127cc: a94153f3 ldp x19, x20, [sp,#16] - 127d0: a8c37bfd ldp x29, x30, [sp],#48 - 127d4: d65f03c0 ret - 127d8: b9002fa2 str w2, [x29,#44] - 127dc: 97fff3e3 bl f768 <__lll_lock_wait_private> - 127e0: 17ffffe9 b 12784 - 127e4: aa0203e0 mov x0, x2 - 127e8: d2801021 mov x1, #0x81 // #129 - 127ec: d2800022 mov x2, #0x1 // #1 - 127f0: d2800003 mov x3, #0x0 // #0 - 127f4: d2800c48 mov x8, #0x62 // #98 - 127f8: d4000001 svc #0x0 - 127fc: 52800000 mov w0, #0x0 // #0 - 12800: a94153f3 ldp x19, x20, [sp,#16] - 12804: a8c37bfd ldp x29, x30, [sp],#48 - 12808: d65f03c0 ret - -000000000001280c <__errno_location>: - 1280c: b00000e1 adrp x1, 2f000 <__FRAME_END__+0x18e30> - 12810: f947c421 ldr x1, [x1,#3976] - 12814: d53bd040 mrs x0, tpidr_el0 - 12818: 8b010000 add x0, x0, x1 - 1281c: d65f03c0 ret - -Disassembly of section __libc_freeres_fn: - -0000000000012820 : - 12820: a9bf7bfd stp x29, x30, [sp,#-16]! - 12824: 910003fd mov x29, sp - 12828: 94000004 bl 12838 <__unwind_freeres> - 1282c: a8c17bfd ldp x29, x30, [sp],#16 - 12830: d2800000 mov x0, #0x0 // #0 - 12834: 17ffccdb b 5ba0 <__free_stacks> - -0000000000012838 <__unwind_freeres>: - 12838: d0000101 adrp x1, 34000 <__GI___pthread_keys+0x3d78> - 1283c: f9417420 ldr x0, [x1,#744] - 12840: b4000060 cbz x0, 1284c <__unwind_freeres+0x14> - 12844: f901743f str xzr, [x1,#744] - 12848: 17ffc9e6 b 4fe0 <__libc_dlclose@plt> - 1284c: d65f03c0 ret - -Disassembly of section .fini: - -0000000000012850 <_fini>: - 12850: a9bf7bfd stp x29, x30, [sp,#-16]! - 12854: 910003fd mov x29, sp - 12858: a8c17bfd ldp x29, x30, [sp],#16 - 1285c: d65f03c0 ret diff --git a/proccontrol/h/Event.h b/proccontrol/h/Event.h index 478732abbf..affdcac3d2 100644 --- a/proccontrol/h/Event.h +++ b/proccontrol/h/Event.h @@ -32,6 +32,8 @@ #include #include +#include +#include #include "dyntypes.h" #include "MachSyscall.h" #include "EventType.h" @@ -97,17 +99,17 @@ class EventSyscall; class EventPreSyscall; class EventPostSyscall; -class PC_EXPORT Event : public boost::enable_shared_from_this +class PC_EXPORT Event : public dyncompat::enable_shared_from_this { - friend void boost::checked_delete(Event *) CHECKED_DELETE_NOEXCEPT; - friend void boost::checked_delete(const Event *) CHECKED_DELETE_NOEXCEPT; + friend void dyncompat::checked_delete(Event *) noexcept; + friend void dyncompat::checked_delete(const Event *) noexcept; friend class ::HandlerPool; friend class ::int_process; friend class ::HandleCallbacks; public: - typedef boost::shared_ptr ptr; - typedef boost::shared_ptr const_ptr; - typedef boost::weak_ptr weak_ptr; + typedef dyncompat::shared_ptr ptr; + typedef dyncompat::shared_ptr const_ptr; + typedef dyncompat::weak_ptr weak_ptr; Event(EventType etype_, Thread::ptr thread_ = Thread::ptr()); virtual ~Event(); @@ -140,128 +142,128 @@ class PC_EXPORT Event : public boost::enable_shared_from_this Event::weak_ptr subservientTo() const; void addSubservientEvent(Event::ptr ev); - boost::shared_ptr getEventTerminate(); - boost::shared_ptr getEventTerminate() const; + dyncompat::shared_ptr getEventTerminate(); + dyncompat::shared_ptr getEventTerminate() const; - boost::shared_ptr getEventExit(); - boost::shared_ptr getEventExit() const; + dyncompat::shared_ptr getEventExit(); + dyncompat::shared_ptr getEventExit() const; - boost::shared_ptr getEventCrash(); - boost::shared_ptr getEventCrash() const; + dyncompat::shared_ptr getEventCrash(); + dyncompat::shared_ptr getEventCrash() const; - boost::shared_ptr getEventForceTerminate(); - boost::shared_ptr getEventForceTerminate() const; + dyncompat::shared_ptr getEventForceTerminate(); + dyncompat::shared_ptr getEventForceTerminate() const; - boost::shared_ptr getEventExec(); - boost::shared_ptr getEventExec() const; + dyncompat::shared_ptr getEventExec(); + dyncompat::shared_ptr getEventExec() const; - boost::shared_ptr getEventStop(); - boost::shared_ptr getEventStop() const; + dyncompat::shared_ptr getEventStop(); + dyncompat::shared_ptr getEventStop() const; - boost::shared_ptr getEventBreakpoint(); - boost::shared_ptr getEventBreakpoint() const; + dyncompat::shared_ptr getEventBreakpoint(); + dyncompat::shared_ptr getEventBreakpoint() const; - boost::shared_ptr getEventNewThread(); - boost::shared_ptr getEventNewThread() const; + dyncompat::shared_ptr getEventNewThread(); + dyncompat::shared_ptr getEventNewThread() const; - boost::shared_ptr getEventNewUserThread(); - boost::shared_ptr getEventNewUserThread() const; + dyncompat::shared_ptr getEventNewUserThread(); + dyncompat::shared_ptr getEventNewUserThread() const; - boost::shared_ptr getEventNewLWP(); - boost::shared_ptr getEventNewLWP() const; + dyncompat::shared_ptr getEventNewLWP(); + dyncompat::shared_ptr getEventNewLWP() const; - boost::shared_ptr getEventThreadDestroy(); - boost::shared_ptr getEventThreadDestroy() const; + dyncompat::shared_ptr getEventThreadDestroy(); + dyncompat::shared_ptr getEventThreadDestroy() const; - boost::shared_ptr getEventUserThreadDestroy(); - boost::shared_ptr getEventUserThreadDestroy() const; + dyncompat::shared_ptr getEventUserThreadDestroy(); + dyncompat::shared_ptr getEventUserThreadDestroy() const; - boost::shared_ptr getEventLWPDestroy(); - boost::shared_ptr getEventLWPDestroy() const; + dyncompat::shared_ptr getEventLWPDestroy(); + dyncompat::shared_ptr getEventLWPDestroy() const; - boost::shared_ptr getEventFork(); - boost::shared_ptr getEventFork() const; + dyncompat::shared_ptr getEventFork(); + dyncompat::shared_ptr getEventFork() const; - boost::shared_ptr getEventSignal(); - boost::shared_ptr getEventSignal() const; + dyncompat::shared_ptr getEventSignal(); + dyncompat::shared_ptr getEventSignal() const; - boost::shared_ptr getEventBootstrap(); - boost::shared_ptr getEventBootstrap() const; + dyncompat::shared_ptr getEventBootstrap(); + dyncompat::shared_ptr getEventBootstrap() const; - boost::shared_ptr getEventPreBootstrap(); - boost::shared_ptr getEventPreBootstrap() const; + dyncompat::shared_ptr getEventPreBootstrap(); + dyncompat::shared_ptr getEventPreBootstrap() const; - boost::shared_ptr getEventRPC(); - boost::shared_ptr getEventRPC() const; + dyncompat::shared_ptr getEventRPC(); + dyncompat::shared_ptr getEventRPC() const; - boost::shared_ptr getEventRPCLaunch(); - boost::shared_ptr getEventRPCLaunch() const; + dyncompat::shared_ptr getEventRPCLaunch(); + dyncompat::shared_ptr getEventRPCLaunch() const; - boost::shared_ptr getEventSingleStep(); - boost::shared_ptr getEventSingleStep() const; + dyncompat::shared_ptr getEventSingleStep(); + dyncompat::shared_ptr getEventSingleStep() const; - boost::shared_ptr getEventBreakpointClear(); - boost::shared_ptr getEventBreakpointClear() const; + dyncompat::shared_ptr getEventBreakpointClear(); + dyncompat::shared_ptr getEventBreakpointClear() const; - boost::shared_ptr getEventBreakpointRestore(); - boost::shared_ptr getEventBreakpointRestore() const; + dyncompat::shared_ptr getEventBreakpointRestore(); + dyncompat::shared_ptr getEventBreakpointRestore() const; - boost::shared_ptr getEventLibrary(); - boost::shared_ptr getEventLibrary() const; + dyncompat::shared_ptr getEventLibrary(); + dyncompat::shared_ptr getEventLibrary() const; - boost::shared_ptr getEventAsync(); - boost::shared_ptr getEventAsync() const; + dyncompat::shared_ptr getEventAsync(); + dyncompat::shared_ptr getEventAsync() const; - boost::shared_ptr getEventChangePCStop(); - boost::shared_ptr getEventChangePCStop() const; + dyncompat::shared_ptr getEventChangePCStop(); + dyncompat::shared_ptr getEventChangePCStop() const; - boost::shared_ptr getEventDetach(); - boost::shared_ptr getEventDetach() const; + dyncompat::shared_ptr getEventDetach(); + dyncompat::shared_ptr getEventDetach() const; - boost::shared_ptr getEventIntBootstrap(); - boost::shared_ptr getEventIntBootstrap() const; + dyncompat::shared_ptr getEventIntBootstrap(); + dyncompat::shared_ptr getEventIntBootstrap() const; - boost::shared_ptr getEventNop(); - boost::shared_ptr getEventNop() const; + dyncompat::shared_ptr getEventNop(); + dyncompat::shared_ptr getEventNop() const; - boost::shared_ptr getEventThreadDB(); - boost::shared_ptr getEventThreadDB() const; + dyncompat::shared_ptr getEventThreadDB(); + dyncompat::shared_ptr getEventThreadDB() const; - boost::shared_ptr getEventWinStopThreadDestroy(); - boost::shared_ptr getEventWinStopThreadDestroy() const; + dyncompat::shared_ptr getEventWinStopThreadDestroy(); + dyncompat::shared_ptr getEventWinStopThreadDestroy() const; - boost::shared_ptr getEventControlAuthority(); - boost::shared_ptr getEventControlAuthority() const; + dyncompat::shared_ptr getEventControlAuthority(); + dyncompat::shared_ptr getEventControlAuthority() const; - boost::shared_ptr getEventAsyncIO(); - boost::shared_ptr getEventAsyncIO() const; + dyncompat::shared_ptr getEventAsyncIO(); + dyncompat::shared_ptr getEventAsyncIO() const; - boost::shared_ptr getEventAsyncRead(); - boost::shared_ptr getEventAsyncRead() const; + dyncompat::shared_ptr getEventAsyncRead(); + dyncompat::shared_ptr getEventAsyncRead() const; - boost::shared_ptr getEventAsyncWrite(); - boost::shared_ptr getEventAsyncWrite() const; + dyncompat::shared_ptr getEventAsyncWrite(); + dyncompat::shared_ptr getEventAsyncWrite() const; - boost::shared_ptr getEventAsyncReadAllRegs(); - boost::shared_ptr getEventAsyncReadAllRegs() const; + dyncompat::shared_ptr getEventAsyncReadAllRegs(); + dyncompat::shared_ptr getEventAsyncReadAllRegs() const; - boost::shared_ptr getEventAsyncSetAllRegs(); - boost::shared_ptr getEventAsyncSetAllRegs() const; + dyncompat::shared_ptr getEventAsyncSetAllRegs(); + dyncompat::shared_ptr getEventAsyncSetAllRegs() const; - boost::shared_ptr getEventAsyncFileRead(); - boost::shared_ptr getEventAsyncFileRead() const; + dyncompat::shared_ptr getEventAsyncFileRead(); + dyncompat::shared_ptr getEventAsyncFileRead() const; - boost::shared_ptr getEventPostponedSyscall(); - boost::shared_ptr getEventPostponedSyscall() const; + dyncompat::shared_ptr getEventPostponedSyscall(); + dyncompat::shared_ptr getEventPostponedSyscall() const; - boost::shared_ptr getEventSyscall(); - boost::shared_ptr getEventSyscall() const; + dyncompat::shared_ptr getEventSyscall(); + dyncompat::shared_ptr getEventSyscall() const; - boost::shared_ptr getEventPreSyscall(); - boost::shared_ptr getEventPreSyscall() const; + dyncompat::shared_ptr getEventPreSyscall(); + dyncompat::shared_ptr getEventPreSyscall() const; - boost::shared_ptr getEventPostSyscall(); - boost::shared_ptr getEventPostSyscall() const; + dyncompat::shared_ptr getEventPostSyscall(); + dyncompat::shared_ptr getEventPostSyscall() const; //Not meant for public consumption @@ -307,24 +309,24 @@ OS& operator<<(OS& str, Event& e) class PC_EXPORT EventTerminate : public Event { - friend void boost::checked_delete(EventTerminate *) CHECKED_DELETE_NOEXCEPT; - friend void boost::checked_delete(const EventTerminate *) CHECKED_DELETE_NOEXCEPT; + friend void dyncompat::checked_delete(EventTerminate *) noexcept; + friend void dyncompat::checked_delete(const EventTerminate *) noexcept; public: - typedef boost::shared_ptr ptr; - typedef boost::shared_ptr const_ptr; + typedef dyncompat::shared_ptr ptr; + typedef dyncompat::shared_ptr const_ptr; EventTerminate(EventType type_); virtual ~EventTerminate(); }; class PC_EXPORT EventExit : public EventTerminate { - friend void boost::checked_delete(EventExit *) CHECKED_DELETE_NOEXCEPT; - friend void boost::checked_delete(const EventExit *) CHECKED_DELETE_NOEXCEPT; + friend void dyncompat::checked_delete(EventExit *) noexcept; + friend void dyncompat::checked_delete(const EventExit *) noexcept; private: int exitcode; public: - typedef boost::shared_ptr ptr; - typedef boost::shared_ptr const_ptr; + typedef dyncompat::shared_ptr ptr; + typedef dyncompat::shared_ptr const_ptr; int getExitCode() const; EventExit(EventType::Time eventtime, int exitcode_); virtual ~EventExit(); @@ -332,13 +334,13 @@ class PC_EXPORT EventExit : public EventTerminate class PC_EXPORT EventCrash : public EventTerminate { - friend void boost::checked_delete(EventCrash *) CHECKED_DELETE_NOEXCEPT; - friend void boost::checked_delete(const EventCrash *) CHECKED_DELETE_NOEXCEPT; + friend void dyncompat::checked_delete(EventCrash *) noexcept; + friend void dyncompat::checked_delete(const EventCrash *) noexcept; private: int termsig; public: - typedef boost::shared_ptr ptr; - typedef boost::shared_ptr const_ptr; + typedef dyncompat::shared_ptr ptr; + typedef dyncompat::shared_ptr const_ptr; int getTermSignal() const; EventCrash(int termsig); virtual ~EventCrash(); @@ -346,13 +348,13 @@ class PC_EXPORT EventCrash : public EventTerminate class PC_EXPORT EventForceTerminate : public EventTerminate { - friend void boost::checked_delete(EventForceTerminate *) CHECKED_DELETE_NOEXCEPT; - friend void boost::checked_delete(const EventForceTerminate *) CHECKED_DELETE_NOEXCEPT; + friend void dyncompat::checked_delete(EventForceTerminate *) noexcept; + friend void dyncompat::checked_delete(const EventForceTerminate *) noexcept; private: int termsig; public: - typedef boost::shared_ptr ptr; - typedef boost::shared_ptr const_ptr; + typedef dyncompat::shared_ptr ptr; + typedef dyncompat::shared_ptr const_ptr; int getTermSignal() const; EventForceTerminate(int termsig); virtual ~EventForceTerminate(); @@ -360,13 +362,13 @@ class PC_EXPORT EventForceTerminate : public EventTerminate class PC_EXPORT EventExec : public Event { - friend void boost::checked_delete(EventExec *) CHECKED_DELETE_NOEXCEPT; - friend void boost::checked_delete(const EventExec *) CHECKED_DELETE_NOEXCEPT; + friend void dyncompat::checked_delete(EventExec *) noexcept; + friend void dyncompat::checked_delete(const EventExec *) noexcept; private: std::string execpath; public: - typedef boost::shared_ptr ptr; - typedef boost::shared_ptr const_ptr; + typedef dyncompat::shared_ptr ptr; + typedef dyncompat::shared_ptr const_ptr; EventExec(EventType::Time etime_, std::string path = std::string("")); virtual ~EventExec(); @@ -376,22 +378,22 @@ class PC_EXPORT EventExec : public Event class PC_EXPORT EventStop : public Event { - friend void boost::checked_delete(EventStop *) CHECKED_DELETE_NOEXCEPT; - friend void boost::checked_delete(const EventStop *) CHECKED_DELETE_NOEXCEPT; + friend void dyncompat::checked_delete(EventStop *) noexcept; + friend void dyncompat::checked_delete(const EventStop *) noexcept; public: - typedef boost::shared_ptr ptr; - typedef boost::shared_ptr const_ptr; + typedef dyncompat::shared_ptr ptr; + typedef dyncompat::shared_ptr const_ptr; EventStop(); virtual ~EventStop(); }; class PC_EXPORT EventNewThread : public Event { - friend void boost::checked_delete(EventNewThread *) CHECKED_DELETE_NOEXCEPT; - friend void boost::checked_delete(const EventNewThread *) CHECKED_DELETE_NOEXCEPT; + friend void dyncompat::checked_delete(EventNewThread *) noexcept; + friend void dyncompat::checked_delete(const EventNewThread *) noexcept; public: - typedef boost::shared_ptr ptr; - typedef boost::shared_ptr const_ptr; + typedef dyncompat::shared_ptr ptr; + typedef dyncompat::shared_ptr const_ptr; EventNewThread(EventType et); virtual ~EventNewThread(); @@ -402,13 +404,13 @@ class PC_EXPORT EventNewThread : public Event class int_eventNewUserThread; class PC_EXPORT EventNewUserThread : public EventNewThread { - friend void boost::checked_delete(EventNewUserThread *) CHECKED_DELETE_NOEXCEPT; - friend void boost::checked_delete(const EventNewUserThread *) CHECKED_DELETE_NOEXCEPT; + friend void dyncompat::checked_delete(EventNewUserThread *) noexcept; + friend void dyncompat::checked_delete(const EventNewUserThread *) noexcept; private: int_eventNewUserThread *iev; public: - typedef boost::shared_ptr ptr; - typedef boost::shared_ptr const_ptr; + typedef dyncompat::shared_ptr ptr; + typedef dyncompat::shared_ptr const_ptr; EventNewUserThread(); virtual ~EventNewUserThread(); @@ -421,15 +423,15 @@ class PC_EXPORT EventNewUserThread : public EventNewThread class int_eventNewLWP; class PC_EXPORT EventNewLWP : public EventNewThread { - friend void boost::checked_delete(EventNewLWP *) CHECKED_DELETE_NOEXCEPT; - friend void boost::checked_delete(const EventNewLWP *) CHECKED_DELETE_NOEXCEPT; + friend void dyncompat::checked_delete(EventNewLWP *) noexcept; + friend void dyncompat::checked_delete(const EventNewLWP *) noexcept; private: int_eventNewLWP *iev; Dyninst::LWP lwp; public: int_eventNewLWP *getInternalEvent(); - typedef boost::shared_ptr ptr; - typedef boost::shared_ptr const_ptr; + typedef dyncompat::shared_ptr ptr; + typedef dyncompat::shared_ptr const_ptr; EventNewLWP(Dyninst::LWP lwp_, int status = 0); virtual ~EventNewLWP(); @@ -439,46 +441,46 @@ class PC_EXPORT EventNewLWP : public EventNewThread class PC_EXPORT EventThreadDestroy : public Event { - friend void boost::checked_delete(EventThreadDestroy *) CHECKED_DELETE_NOEXCEPT; - friend void boost::checked_delete(const EventThreadDestroy *) CHECKED_DELETE_NOEXCEPT; + friend void dyncompat::checked_delete(EventThreadDestroy *) noexcept; + friend void dyncompat::checked_delete(const EventThreadDestroy *) noexcept; public: - typedef boost::shared_ptr ptr; - typedef boost::shared_ptr const_ptr; + typedef dyncompat::shared_ptr ptr; + typedef dyncompat::shared_ptr const_ptr; EventThreadDestroy(EventType et); virtual ~EventThreadDestroy() = 0; }; class PC_EXPORT EventUserThreadDestroy : public EventThreadDestroy { - friend void boost::checked_delete(EventUserThreadDestroy *) CHECKED_DELETE_NOEXCEPT; - friend void boost::checked_delete(const EventUserThreadDestroy *) CHECKED_DELETE_NOEXCEPT; + friend void dyncompat::checked_delete(EventUserThreadDestroy *) noexcept; + friend void dyncompat::checked_delete(const EventUserThreadDestroy *) noexcept; public: - typedef boost::shared_ptr ptr; - typedef boost::shared_ptr const_ptr; + typedef dyncompat::shared_ptr ptr; + typedef dyncompat::shared_ptr const_ptr; EventUserThreadDestroy(EventType::Time time_); virtual ~EventUserThreadDestroy(); }; class PC_EXPORT EventLWPDestroy : public EventThreadDestroy { - friend void boost::checked_delete(EventLWPDestroy *) CHECKED_DELETE_NOEXCEPT; - friend void boost::checked_delete(const EventLWPDestroy *) CHECKED_DELETE_NOEXCEPT; + friend void dyncompat::checked_delete(EventLWPDestroy *) noexcept; + friend void dyncompat::checked_delete(const EventLWPDestroy *) noexcept; public: - typedef boost::shared_ptr ptr; - typedef boost::shared_ptr const_ptr; + typedef dyncompat::shared_ptr ptr; + typedef dyncompat::shared_ptr const_ptr; EventLWPDestroy(EventType::Time time_); virtual ~EventLWPDestroy(); }; class PC_EXPORT EventFork : public Event { - friend void boost::checked_delete(EventFork *) CHECKED_DELETE_NOEXCEPT; - friend void boost::checked_delete(const EventFork *) CHECKED_DELETE_NOEXCEPT; + friend void dyncompat::checked_delete(EventFork *) noexcept; + friend void dyncompat::checked_delete(const EventFork *) noexcept; private: Dyninst::PID pid; public: - typedef boost::shared_ptr ptr; - typedef boost::shared_ptr const_ptr; + typedef dyncompat::shared_ptr ptr; + typedef dyncompat::shared_ptr const_ptr; EventFork(EventType::Time time_, Dyninst::PID pid_); virtual ~EventFork(); Dyninst::PID getPID() const; @@ -491,8 +493,8 @@ class PC_EXPORT EventSignal : public Event // causes of signal. unknown refers to all non-access violations. // this is needed for defensve mode. enum Cause { Unknown, ReadViolation, WriteViolation, ExecuteViolation }; - friend void boost::checked_delete(EventSignal *) CHECKED_DELETE_NOEXCEPT; - friend void boost::checked_delete(const EventSignal *) CHECKED_DELETE_NOEXCEPT; + friend void dyncompat::checked_delete(EventSignal *) noexcept; + friend void dyncompat::checked_delete(const EventSignal *) noexcept; private: int sig; // address that caused the signal (if any), the cause, and @@ -501,8 +503,8 @@ class PC_EXPORT EventSignal : public Event Cause cause; bool first; public: - typedef boost::shared_ptr ptr; - typedef boost::shared_ptr const_ptr; + typedef dyncompat::shared_ptr ptr; + typedef dyncompat::shared_ptr const_ptr; EventSignal(int sig); EventSignal(int s, Address a, Cause c, bool f) : Event(EventType(EventType::None, EventType::Signal)), sig(s), addr(a), cause(c), first(f) { } @@ -520,22 +522,22 @@ class PC_EXPORT EventSignal : public Event class PC_EXPORT EventBootstrap : public Event { - friend void boost::checked_delete(EventBootstrap *) CHECKED_DELETE_NOEXCEPT; - friend void boost::checked_delete(const EventBootstrap *) CHECKED_DELETE_NOEXCEPT; + friend void dyncompat::checked_delete(EventBootstrap *) noexcept; + friend void dyncompat::checked_delete(const EventBootstrap *) noexcept; public: - typedef boost::shared_ptr ptr; - typedef boost::shared_ptr const_ptr; + typedef dyncompat::shared_ptr ptr; + typedef dyncompat::shared_ptr const_ptr; EventBootstrap(); virtual ~EventBootstrap(); }; class PC_EXPORT EventPreBootstrap : public Event { - friend void boost::checked_delete(EventPreBootstrap *) CHECKED_DELETE_NOEXCEPT; - friend void boost::checked_delete(const EventPreBootstrap *) CHECKED_DELETE_NOEXCEPT; + friend void dyncompat::checked_delete(EventPreBootstrap *) noexcept; + friend void dyncompat::checked_delete(const EventPreBootstrap *) noexcept; public: - typedef boost::shared_ptr ptr; - typedef boost::shared_ptr const_ptr; + typedef dyncompat::shared_ptr ptr; + typedef dyncompat::shared_ptr const_ptr; EventPreBootstrap(); virtual ~EventPreBootstrap(); }; @@ -544,16 +546,16 @@ class PC_EXPORT EventPreBootstrap : public Event class int_eventRPC; class PC_EXPORT EventRPC : public Event { - friend void boost::checked_delete(EventRPC *) CHECKED_DELETE_NOEXCEPT; - friend void boost::checked_delete(const EventRPC *) CHECKED_DELETE_NOEXCEPT; + friend void dyncompat::checked_delete(EventRPC *) noexcept; + friend void dyncompat::checked_delete(const EventRPC *) noexcept; private: int_eventRPC *int_rpc; rpc_wrapper *wrapper; public: virtual bool suppressCB() const; rpc_wrapper *getllRPC(); - typedef boost::shared_ptr ptr; - typedef boost::shared_ptr const_ptr; + typedef dyncompat::shared_ptr ptr; + typedef dyncompat::shared_ptr const_ptr; EventRPC(rpc_wrapper *wrapper_); virtual ~EventRPC(); @@ -563,11 +565,11 @@ class PC_EXPORT EventRPC : public Event class PC_EXPORT EventRPCLaunch : public Event { - friend void boost::checked_delete(EventRPCLaunch *) CHECKED_DELETE_NOEXCEPT; - friend void boost::checked_delete(const EventRPCLaunch *) CHECKED_DELETE_NOEXCEPT; + friend void dyncompat::checked_delete(EventRPCLaunch *) noexcept; + friend void dyncompat::checked_delete(const EventRPCLaunch *) noexcept; public: - typedef boost::shared_ptr ptr; - typedef boost::shared_ptr const_ptr; + typedef dyncompat::shared_ptr ptr; + typedef dyncompat::shared_ptr const_ptr; virtual bool procStopper() const; EventRPCLaunch(); virtual ~EventRPCLaunch(); @@ -575,25 +577,25 @@ class PC_EXPORT EventRPCLaunch : public Event class PC_EXPORT EventSingleStep : public Event { - friend void boost::checked_delete(EventSingleStep *) CHECKED_DELETE_NOEXCEPT; - friend void boost::checked_delete(const EventSingleStep *) CHECKED_DELETE_NOEXCEPT; + friend void dyncompat::checked_delete(EventSingleStep *) noexcept; + friend void dyncompat::checked_delete(const EventSingleStep *) noexcept; public: - typedef boost::shared_ptr ptr; - typedef boost::shared_ptr const_ptr; + typedef dyncompat::shared_ptr ptr; + typedef dyncompat::shared_ptr const_ptr; EventSingleStep(); virtual ~EventSingleStep(); }; class PC_EXPORT EventSyscall : public Event { - friend void boost::checked_delete(EventSyscall *) CHECKED_DELETE_NOEXCEPT; - friend void boost::checked_delete(const EventSyscall *) CHECKED_DELETE_NOEXCEPT; + friend void dyncompat::checked_delete(EventSyscall *) noexcept; + friend void dyncompat::checked_delete(const EventSyscall *) noexcept; friend MachSyscall makeFromEvent(const EventSyscall *); public: - typedef boost::shared_ptr ptr; - typedef boost::shared_ptr const_ptr; + typedef dyncompat::shared_ptr ptr; + typedef dyncompat::shared_ptr const_ptr; EventSyscall(EventType type_); virtual ~EventSyscall(); @@ -606,28 +608,28 @@ class PC_EXPORT EventSyscall : public Event class PC_EXPORT EventPreSyscall : public EventSyscall { - friend void boost::checked_delete(EventPreSyscall *) CHECKED_DELETE_NOEXCEPT; - friend void boost::checked_delete(const EventPreSyscall *) CHECKED_DELETE_NOEXCEPT; + friend void dyncompat::checked_delete(EventPreSyscall *) noexcept; + friend void dyncompat::checked_delete(const EventPreSyscall *) noexcept; friend MachSyscall makeFromEvent(const EventPreSyscall *); public: - typedef boost::shared_ptr ptr; - typedef boost::shared_ptr const_ptr; + typedef dyncompat::shared_ptr ptr; + typedef dyncompat::shared_ptr const_ptr; EventPreSyscall(); virtual ~EventPreSyscall(); }; class PC_EXPORT EventPostSyscall : public EventSyscall { - friend void boost::checked_delete(EventPostSyscall *) CHECKED_DELETE_NOEXCEPT; - friend void boost::checked_delete(const EventPostSyscall *) CHECKED_DELETE_NOEXCEPT; + friend void dyncompat::checked_delete(EventPostSyscall *) noexcept; + friend void dyncompat::checked_delete(const EventPostSyscall *) noexcept; friend MachSyscall makeFromEvent(const EventPostSyscall *); public: - typedef boost::shared_ptr ptr; - typedef boost::shared_ptr const_ptr; + typedef dyncompat::shared_ptr ptr; + typedef dyncompat::shared_ptr const_ptr; EventPostSyscall(); virtual ~EventPostSyscall(); @@ -637,13 +639,13 @@ class PC_EXPORT EventPostSyscall : public EventSyscall class int_eventBreakpoint; class PC_EXPORT EventBreakpoint : public Event { - friend void boost::checked_delete(EventBreakpoint *) CHECKED_DELETE_NOEXCEPT; - friend void boost::checked_delete(const EventBreakpoint *) CHECKED_DELETE_NOEXCEPT; + friend void dyncompat::checked_delete(EventBreakpoint *) noexcept; + friend void dyncompat::checked_delete(const EventBreakpoint *) noexcept; private: int_eventBreakpoint *int_bp; public: - typedef boost::shared_ptr ptr; - typedef boost::shared_ptr const_ptr; + typedef dyncompat::shared_ptr ptr; + typedef dyncompat::shared_ptr const_ptr; int_eventBreakpoint *getInternal() const; EventBreakpoint(int_eventBreakpoint *ibp); @@ -660,13 +662,13 @@ class PC_EXPORT EventBreakpoint : public Event class int_eventBreakpointClear; class PC_EXPORT EventBreakpointClear : public Event { - friend void boost::checked_delete(EventBreakpointClear *) CHECKED_DELETE_NOEXCEPT; - friend void boost::checked_delete(const EventBreakpointClear *) CHECKED_DELETE_NOEXCEPT; + friend void dyncompat::checked_delete(EventBreakpointClear *) noexcept; + friend void dyncompat::checked_delete(const EventBreakpointClear *) noexcept; private: int_eventBreakpointClear *int_bpc; public: - typedef boost::shared_ptr ptr; - typedef boost::shared_ptr const_ptr; + typedef dyncompat::shared_ptr ptr; + typedef dyncompat::shared_ptr const_ptr; EventBreakpointClear(); virtual ~EventBreakpointClear(); @@ -677,13 +679,13 @@ class PC_EXPORT EventBreakpointClear : public Event class int_eventBreakpointRestore; class EventBreakpointRestore : public Event { - friend void boost::checked_delete(EventBreakpointRestore *) CHECKED_DELETE_NOEXCEPT; - friend void boost::checked_delete(const EventBreakpointRestore *) CHECKED_DELETE_NOEXCEPT; + friend void dyncompat::checked_delete(EventBreakpointRestore *) noexcept; + friend void dyncompat::checked_delete(const EventBreakpointRestore *) noexcept; private: int_eventBreakpointRestore *int_bpr; public: - typedef boost::shared_ptr ptr; - typedef boost::shared_ptr const_ptr; + typedef dyncompat::shared_ptr ptr; + typedef dyncompat::shared_ptr const_ptr; EventBreakpointRestore(int_eventBreakpointRestore *iebpr); virtual ~EventBreakpointRestore(); @@ -693,14 +695,14 @@ class EventBreakpointRestore : public Event class PC_EXPORT EventLibrary : public Event { - friend void boost::checked_delete(EventLibrary *) CHECKED_DELETE_NOEXCEPT; - friend void boost::checked_delete(const EventLibrary *) CHECKED_DELETE_NOEXCEPT; + friend void dyncompat::checked_delete(EventLibrary *) noexcept; + friend void dyncompat::checked_delete(const EventLibrary *) noexcept; private: std::set added_libs; std::set rmd_libs; public: - typedef boost::shared_ptr ptr; - typedef boost::shared_ptr const_ptr; + typedef dyncompat::shared_ptr ptr; + typedef dyncompat::shared_ptr const_ptr; EventLibrary(); EventLibrary(const std::set &added_libs_, const std::set &rmd_libs_); @@ -715,14 +717,14 @@ class PC_EXPORT EventLibrary : public Event class int_eventAsync; class PC_EXPORT EventAsync : public Event { - friend void boost::checked_delete(EventAsync *) CHECKED_DELETE_NOEXCEPT; - friend void boost::checked_delete(const EventAsync *) CHECKED_DELETE_NOEXCEPT; + friend void dyncompat::checked_delete(EventAsync *) noexcept; + friend void dyncompat::checked_delete(const EventAsync *) noexcept; private: int_eventAsync *internal; public: - typedef boost::shared_ptr ptr; - typedef boost::shared_ptr const_ptr; + typedef dyncompat::shared_ptr ptr; + typedef dyncompat::shared_ptr const_ptr; EventAsync(int_eventAsync *ievent); virtual ~EventAsync(); @@ -731,11 +733,11 @@ class PC_EXPORT EventAsync : public Event class PC_EXPORT EventChangePCStop : public Event { - friend void boost::checked_delete(EventChangePCStop *) CHECKED_DELETE_NOEXCEPT; - friend void boost::checked_delete(const EventChangePCStop *) CHECKED_DELETE_NOEXCEPT; + friend void dyncompat::checked_delete(EventChangePCStop *) noexcept; + friend void dyncompat::checked_delete(const EventChangePCStop *) noexcept; public: - typedef boost::shared_ptr ptr; - typedef boost::shared_ptr const_ptr; + typedef dyncompat::shared_ptr ptr; + typedef dyncompat::shared_ptr const_ptr; EventChangePCStop(); virtual ~EventChangePCStop(); }; @@ -743,12 +745,12 @@ class PC_EXPORT EventChangePCStop : public Event class int_eventDetach; class PC_EXPORT EventDetach : public Event { - friend void boost::checked_delete(EventDetach *) CHECKED_DELETE_NOEXCEPT; - friend void boost::checked_delete(const EventDetach *) CHECKED_DELETE_NOEXCEPT; + friend void dyncompat::checked_delete(EventDetach *) noexcept; + friend void dyncompat::checked_delete(const EventDetach *) noexcept; int_eventDetach *int_detach; public: - typedef boost::shared_ptr ptr; - typedef boost::shared_ptr const_ptr; + typedef dyncompat::shared_ptr ptr; + typedef dyncompat::shared_ptr const_ptr; EventDetach(); virtual ~EventDetach(); @@ -758,13 +760,13 @@ class PC_EXPORT EventDetach : public Event class PC_EXPORT EventIntBootstrap : public Event { - friend void boost::checked_delete(EventIntBootstrap *) CHECKED_DELETE_NOEXCEPT; - friend void boost::checked_delete(const EventIntBootstrap *) CHECKED_DELETE_NOEXCEPT; + friend void dyncompat::checked_delete(EventIntBootstrap *) noexcept; + friend void dyncompat::checked_delete(const EventIntBootstrap *) noexcept; void *data; public: - typedef boost::shared_ptr ptr; - typedef boost::shared_ptr const_ptr; + typedef dyncompat::shared_ptr ptr; + typedef dyncompat::shared_ptr const_ptr; EventIntBootstrap(void *d = NULL); virtual ~EventIntBootstrap(); @@ -774,11 +776,11 @@ class PC_EXPORT EventIntBootstrap : public Event class PC_EXPORT EventNop : public Event { - friend void boost::checked_delete(EventNop *) CHECKED_DELETE_NOEXCEPT; - friend void boost::checked_delete(const EventNop *) CHECKED_DELETE_NOEXCEPT; + friend void dyncompat::checked_delete(EventNop *) noexcept; + friend void dyncompat::checked_delete(const EventNop *) noexcept; public: - typedef boost::shared_ptr ptr; - typedef boost::shared_ptr const_ptr; + typedef dyncompat::shared_ptr ptr; + typedef dyncompat::shared_ptr const_ptr; EventNop(); virtual ~EventNop(); }; @@ -786,12 +788,12 @@ class PC_EXPORT EventNop : public Event class int_eventThreadDB; class PC_EXPORT EventThreadDB : public Event { - friend void boost::checked_delete(EventThreadDB *) CHECKED_DELETE_NOEXCEPT; - friend void boost::checked_delete(const EventThreadDB *) CHECKED_DELETE_NOEXCEPT; + friend void dyncompat::checked_delete(EventThreadDB *) noexcept; + friend void dyncompat::checked_delete(const EventThreadDB *) noexcept; int_eventThreadDB *int_etdb; public: - typedef boost::shared_ptr ptr; - typedef boost::shared_ptr const_ptr; + typedef dyncompat::shared_ptr ptr; + typedef dyncompat::shared_ptr const_ptr; int_eventThreadDB *getInternal() const; EventThreadDB(); @@ -802,11 +804,11 @@ class PC_EXPORT EventThreadDB : public Event class PC_EXPORT EventWinStopThreadDestroy : public EventThreadDestroy { - friend void boost::checked_delete(EventWinStopThreadDestroy *) CHECKED_DELETE_NOEXCEPT; - friend void boost::checked_delete(const EventWinStopThreadDestroy *) CHECKED_DELETE_NOEXCEPT; + friend void dyncompat::checked_delete(EventWinStopThreadDestroy *) noexcept; + friend void dyncompat::checked_delete(const EventWinStopThreadDestroy *) noexcept; public: - typedef boost::shared_ptr ptr; - typedef boost::shared_ptr const_ptr; + typedef dyncompat::shared_ptr ptr; + typedef dyncompat::shared_ptr const_ptr; EventWinStopThreadDestroy(EventType::Time time_); virtual ~EventWinStopThreadDestroy(); }; @@ -814,12 +816,12 @@ class PC_EXPORT EventWinStopThreadDestroy : public EventThreadDestroy class int_eventControlAuthority; class PC_EXPORT EventControlAuthority : public Event { - friend void boost::checked_delete(EventControlAuthority *) CHECKED_DELETE_NOEXCEPT; - friend void boost::checked_delete(const EventControlAuthority *) CHECKED_DELETE_NOEXCEPT; + friend void dyncompat::checked_delete(EventControlAuthority *) noexcept; + friend void dyncompat::checked_delete(const EventControlAuthority *) noexcept; int_eventControlAuthority *iev; public: - typedef boost::shared_ptr ptr; - typedef boost::shared_ptr const_ptr; + typedef dyncompat::shared_ptr ptr; + typedef dyncompat::shared_ptr const_ptr; int_eventControlAuthority *getInternalEvent() const; EventControlAuthority(EventType::Time t, int_eventControlAuthority *iev_); @@ -841,13 +843,13 @@ class PC_EXPORT EventControlAuthority : public Event class int_eventAsyncIO; class PC_EXPORT EventAsyncIO : public Event { - friend void boost::checked_delete(EventAsyncIO *) CHECKED_DELETE_NOEXCEPT; - friend void boost::checked_delete(const EventAsyncIO *) CHECKED_DELETE_NOEXCEPT; + friend void dyncompat::checked_delete(EventAsyncIO *) noexcept; + friend void dyncompat::checked_delete(const EventAsyncIO *) noexcept; protected: int_eventAsyncIO *iev; public: - typedef boost::shared_ptr ptr; - typedef boost::shared_ptr const_ptr; + typedef dyncompat::shared_ptr ptr; + typedef dyncompat::shared_ptr const_ptr; int_eventAsyncIO *getInternalEvent() const; EventAsyncIO(EventType et, int_eventAsyncIO *iev_); @@ -858,11 +860,11 @@ class PC_EXPORT EventAsyncIO : public Event { }; class PC_EXPORT EventAsyncRead : public EventAsyncIO { - friend void boost::checked_delete(EventAsyncRead *) CHECKED_DELETE_NOEXCEPT; - friend void boost::checked_delete(const EventAsyncRead *) CHECKED_DELETE_NOEXCEPT; + friend void dyncompat::checked_delete(EventAsyncRead *) noexcept; + friend void dyncompat::checked_delete(const EventAsyncRead *) noexcept; public: - typedef boost::shared_ptr ptr; - typedef boost::shared_ptr const_ptr; + typedef dyncompat::shared_ptr ptr; + typedef dyncompat::shared_ptr const_ptr; EventAsyncRead(int_eventAsyncIO *iev_); ~EventAsyncRead(); @@ -873,11 +875,11 @@ class PC_EXPORT EventAsyncRead : public EventAsyncIO { }; class PC_EXPORT EventAsyncWrite : public EventAsyncIO { - friend void boost::checked_delete(EventAsyncWrite *) CHECKED_DELETE_NOEXCEPT; - friend void boost::checked_delete(const EventAsyncWrite *) CHECKED_DELETE_NOEXCEPT; + friend void dyncompat::checked_delete(EventAsyncWrite *) noexcept; + friend void dyncompat::checked_delete(const EventAsyncWrite *) noexcept; public: - typedef boost::shared_ptr ptr; - typedef boost::shared_ptr const_ptr; + typedef dyncompat::shared_ptr ptr; + typedef dyncompat::shared_ptr const_ptr; EventAsyncWrite(int_eventAsyncIO *iev_); ~EventAsyncWrite(); @@ -887,11 +889,11 @@ class PC_EXPORT EventAsyncWrite : public EventAsyncIO { }; class PC_EXPORT EventAsyncReadAllRegs : public EventAsyncIO { - friend void boost::checked_delete(EventAsyncReadAllRegs *) CHECKED_DELETE_NOEXCEPT; - friend void boost::checked_delete(const EventAsyncReadAllRegs *) CHECKED_DELETE_NOEXCEPT; + friend void dyncompat::checked_delete(EventAsyncReadAllRegs *) noexcept; + friend void dyncompat::checked_delete(const EventAsyncReadAllRegs *) noexcept; public: - typedef boost::shared_ptr ptr; - typedef boost::shared_ptr const_ptr; + typedef dyncompat::shared_ptr ptr; + typedef dyncompat::shared_ptr const_ptr; EventAsyncReadAllRegs(int_eventAsyncIO *iev_); ~EventAsyncReadAllRegs(); @@ -900,11 +902,11 @@ class PC_EXPORT EventAsyncReadAllRegs : public EventAsyncIO { }; class PC_EXPORT EventAsyncSetAllRegs : public EventAsyncIO { - friend void boost::checked_delete(EventAsyncSetAllRegs *) CHECKED_DELETE_NOEXCEPT; - friend void boost::checked_delete(const EventAsyncSetAllRegs *) CHECKED_DELETE_NOEXCEPT; + friend void dyncompat::checked_delete(EventAsyncSetAllRegs *) noexcept; + friend void dyncompat::checked_delete(const EventAsyncSetAllRegs *) noexcept; public: - typedef boost::shared_ptr ptr; - typedef boost::shared_ptr const_ptr; + typedef dyncompat::shared_ptr ptr; + typedef dyncompat::shared_ptr const_ptr; EventAsyncSetAllRegs(int_eventAsyncIO *iev_); ~EventAsyncSetAllRegs(); @@ -912,12 +914,12 @@ class PC_EXPORT EventAsyncSetAllRegs : public EventAsyncIO { class int_eventAsyncFileRead; class PC_EXPORT EventAsyncFileRead : public Event { - friend void boost::checked_delete(EventAsyncFileRead *) CHECKED_DELETE_NOEXCEPT; - friend void boost::checked_delete(const EventAsyncFileRead *) CHECKED_DELETE_NOEXCEPT; + friend void dyncompat::checked_delete(EventAsyncFileRead *) noexcept; + friend void dyncompat::checked_delete(const EventAsyncFileRead *) noexcept; int_eventAsyncFileRead *iev; public: - typedef boost::shared_ptr ptr; - typedef boost::shared_ptr const_ptr; + typedef dyncompat::shared_ptr ptr; + typedef dyncompat::shared_ptr const_ptr; int_eventAsyncFileRead *getInternal(); EventAsyncFileRead(int_eventAsyncFileRead *iev_); @@ -936,11 +938,11 @@ class PC_EXPORT EventAsyncFileRead : public Event { class EventPostponedSyscall : public Event { - friend void boost::checked_delete(EventPostponedSyscall *) CHECKED_DELETE_NOEXCEPT; - friend void boost::checked_delete(const EventPostponedSyscall *) CHECKED_DELETE_NOEXCEPT; + friend void dyncompat::checked_delete(EventPostponedSyscall *) noexcept; + friend void dyncompat::checked_delete(const EventPostponedSyscall *) noexcept; public: - typedef boost::shared_ptr ptr; - typedef boost::shared_ptr const_ptr; + typedef dyncompat::shared_ptr ptr; + typedef dyncompat::shared_ptr const_ptr; EventPostponedSyscall(); virtual ~EventPostponedSyscall(); diff --git a/proccontrol/h/EventType.h b/proccontrol/h/EventType.h index 2d89350332..f56a79147d 100644 --- a/proccontrol/h/EventType.h +++ b/proccontrol/h/EventType.h @@ -30,6 +30,7 @@ #if !defined(EVENTTYPE_H_) #define EVENTTYPE_H_ +#include #include "util.h" namespace Dyninst { diff --git a/proccontrol/h/Generator.h b/proccontrol/h/Generator.h index 16f2b3801b..ab154809b2 100644 --- a/proccontrol/h/Generator.h +++ b/proccontrol/h/Generator.h @@ -40,6 +40,7 @@ #include #include #include +#include struct GeneratorMTInternals; class int_process; diff --git a/proccontrol/h/Handler.h b/proccontrol/h/Handler.h index 374edb9a92..92c9136023 100644 --- a/proccontrol/h/Handler.h +++ b/proccontrol/h/Handler.h @@ -33,6 +33,7 @@ #include "Event.h" #include "util.h" +#include #include #include diff --git a/proccontrol/h/PCProcess.h b/proccontrol/h/PCProcess.h index 3fe43e2e88..cd40225134 100644 --- a/proccontrol/h/PCProcess.h +++ b/proccontrol/h/PCProcess.h @@ -36,23 +36,21 @@ #include #include #include +#include +#include #include "dyntypes.h" -#include "dyn_regs.h" +#include "Architecture.h" +#include "registers/MachRegister.h" #include "EventType.h" #include "util.h" #include "PCErrors.h" -#include "boost/checked_delete.hpp" -#include "boost/shared_ptr.hpp" -#include "boost/weak_ptr.hpp" -#include "boost/enable_shared_from_this.hpp" -#include "boost/version.hpp" +#include "dyncompat/checked_delete.hpp" +#include "dyncompat/shared_ptr.hpp" +#include "dyncompat/weak_ptr.hpp" +#include "dyncompat/enable_shared_from_this.hpp" +#include "dyncompat/version.hpp" -#if BOOST_VERSION >= 107000 -#define CHECKED_DELETE_NOEXCEPT BOOST_NOEXCEPT -#else -#define CHECKED_DELETE_NOEXCEPT -#endif @@ -74,7 +72,7 @@ class MTLock; #define PC_VERSION_8_1_0 #define PC_VERSION_8_2_0 -#define pc_const_cast boost::const_pointer_cast +#define pc_const_cast dyncompat::const_pointer_cast namespace Dyninst { @@ -110,8 +108,8 @@ class ExecFileInfo; class PC_EXPORT Breakpoint { friend class ::int_breakpoint; - friend void boost::checked_delete(Breakpoint *) CHECKED_DELETE_NOEXCEPT; - friend void boost::checked_delete(const Breakpoint *) CHECKED_DELETE_NOEXCEPT; + friend void dyncompat::checked_delete(Breakpoint *) noexcept; + friend void dyncompat::checked_delete(const Breakpoint *) noexcept; private: int_breakpoint *llbreakpoint_; Breakpoint(); @@ -122,14 +120,15 @@ class PC_EXPORT Breakpoint static const int BP_R = 4; int_breakpoint *llbp() const; - typedef boost::shared_ptr ptr; - typedef boost::shared_ptr const_ptr; - typedef boost::weak_ptr weak_ptr; + typedef dyncompat::shared_ptr ptr; + typedef dyncompat::shared_ptr const_ptr; + typedef dyncompat::weak_ptr weak_ptr; static Breakpoint::ptr newBreakpoint(); static Breakpoint::ptr newTransferBreakpoint(Dyninst::Address to); static Breakpoint::ptr newTransferOffsetBreakpoint(signed long shift); static Breakpoint::ptr newHardwareBreakpoint(unsigned int mode, unsigned int size); + static Breakpoint::ptr newSynchronousBreakpoint(); void *getData() const; void setData(void *p) const; @@ -139,20 +138,22 @@ class PC_EXPORT Breakpoint void setSuppressCallbacks(bool); bool suppressCallbacks() const; + + bool isSynchronous() const; }; class PC_EXPORT Library { friend class ::int_library; - friend void boost::checked_delete(Library *) CHECKED_DELETE_NOEXCEPT; - friend void boost::checked_delete(const Library *) CHECKED_DELETE_NOEXCEPT; + friend void dyncompat::checked_delete(Library *) noexcept; + friend void dyncompat::checked_delete(const Library *) noexcept; private: int_library *lib; Library(); ~Library(); public: - typedef boost::shared_ptr ptr; - typedef boost::shared_ptr const_ptr; + typedef dyncompat::shared_ptr ptr; + typedef dyncompat::shared_ptr const_ptr; std::string getName() const; std::string getAbsoluteName() const; @@ -201,8 +202,8 @@ class PC_EXPORT LibraryPool public: const_iterator(); Library::const_ptr operator*() const; - bool operator==(const const_iterator &i); - bool operator!=(const const_iterator &i); + bool operator==(const const_iterator &i) const; + bool operator!=(const const_iterator &i) const; LibraryPool::const_iterator operator++(); LibraryPool::const_iterator operator++(int); @@ -234,8 +235,8 @@ class PC_EXPORT LibraryPool class PC_EXPORT IRPC { friend class ::int_iRPC; - friend void boost::checked_delete(IRPC *) CHECKED_DELETE_NOEXCEPT; - friend void boost::checked_delete(const IRPC *) CHECKED_DELETE_NOEXCEPT; + friend void dyncompat::checked_delete(IRPC *) noexcept; + friend void dyncompat::checked_delete(const IRPC *) noexcept; private: rpc_wrapper *wrapper; IRPC(rpc_wrapper *wrapper_); @@ -249,9 +250,9 @@ class PC_EXPORT IRPC // Callback = 4, Done = 5 } State; - typedef boost::shared_ptr ptr; - typedef boost::shared_ptr const_ptr; - typedef boost::weak_ptr weak_ptr; + typedef dyncompat::shared_ptr ptr; + typedef dyncompat::shared_ptr const_ptr; + typedef dyncompat::weak_ptr weak_ptr; static IRPC::ptr createIRPC(void *binary_blob, unsigned size, bool non_blocking = false); @@ -281,7 +282,7 @@ class PC_EXPORT IRPC bool continueStoppedIRPC(); }; -class PC_EXPORT Process : public boost::enable_shared_from_this +class PC_EXPORT Process : public dyncompat::enable_shared_from_this { private: friend class ::int_process; @@ -292,13 +293,13 @@ class PC_EXPORT Process : public boost::enable_shared_from_this Process(); ~Process(); - friend void boost::checked_delete(Process *) CHECKED_DELETE_NOEXCEPT; - friend void boost::checked_delete(const Process *) CHECKED_DELETE_NOEXCEPT; + friend void dyncompat::checked_delete(Process *) noexcept; + friend void dyncompat::checked_delete(const Process *) noexcept; public: - typedef boost::shared_ptr ptr; - typedef boost::shared_ptr const_ptr; - typedef boost::weak_ptr weak_ptr; - typedef boost::weak_ptr const_weak_ptr; + typedef dyncompat::shared_ptr ptr; + typedef dyncompat::shared_ptr const_ptr; + typedef dyncompat::weak_ptr weak_ptr; + typedef dyncompat::weak_ptr const_weak_ptr; static void version(int& major, int& minor, int& maintenance); @@ -350,7 +351,7 @@ class PC_EXPORT Process : public boost::enable_shared_from_this //cb_func_t really takes an 'Event::const_ptr' as parameter, but this declaration // defines the shared_ptr declaration due to Event::const_ptr not being defined yet. - typedef cb_ret_t(*cb_func_t)(boost::shared_ptr); + typedef cb_ret_t(*cb_func_t)(dyncompat::shared_ptr); static bool handleEvents(bool block); static bool registerEventCallback(EventType evt, cb_func_t cbfunc); @@ -557,7 +558,7 @@ class PC_EXPORT Process : public boost::enable_shared_from_this ExecFileInfo* getExecutableInfo() const; }; -class PC_EXPORT Thread : public boost::enable_shared_from_this +class PC_EXPORT Thread : public dyncompat::enable_shared_from_this { protected: friend class ::int_thread; @@ -566,14 +567,14 @@ class PC_EXPORT Thread : public boost::enable_shared_from_this Thread(); ~Thread(); - friend void boost::checked_delete(Thread *) CHECKED_DELETE_NOEXCEPT; - friend void boost::checked_delete(const Thread *) CHECKED_DELETE_NOEXCEPT; + friend void dyncompat::checked_delete(Thread *) noexcept; + friend void dyncompat::checked_delete(const Thread *) noexcept; public: - typedef boost::shared_ptr ptr; - typedef boost::shared_ptr const_ptr; - typedef boost::weak_ptr weak_ptr; - typedef boost::weak_ptr const_weak_ptr; + typedef dyncompat::shared_ptr ptr; + typedef dyncompat::shared_ptr const_ptr; + typedef dyncompat::weak_ptr weak_ptr; + typedef dyncompat::weak_ptr const_weak_ptr; int_thread *llthrd() const; void setLastError(err_t ec, const char *es) const; @@ -666,8 +667,8 @@ class PC_EXPORT ThreadPool public: iterator(); Thread::ptr operator*() const; - bool operator==(const iterator &i); - bool operator!=(const iterator &i); + bool operator==(const iterator &i) const; + bool operator!=(const iterator &i) const; ThreadPool::iterator operator++(); ThreadPool::iterator operator++(int); }; @@ -686,8 +687,8 @@ class PC_EXPORT ThreadPool public: const_iterator(); Thread::const_ptr operator*() const; - bool operator==(const const_iterator &i); - bool operator!=(const const_iterator &i); + bool operator==(const const_iterator &i) const; + bool operator!=(const const_iterator &i) const; ThreadPool::const_iterator operator++(); ThreadPool::const_iterator operator++(int); @@ -728,8 +729,8 @@ class PC_EXPORT RegisterPool public: iterator(); std::pair operator*(); - bool operator==(const iterator &i); - bool operator!=(const iterator &i); + bool operator==(const iterator &i) const; + bool operator!=(const iterator &i) const; RegisterPool::iterator operator++(); RegisterPool::iterator operator++(int); }; @@ -746,8 +747,8 @@ class PC_EXPORT RegisterPool public: const_iterator(); std::pair operator*() const; - bool operator==(const const_iterator &i); - bool operator!=(const const_iterator &i); + bool operator==(const const_iterator &i) const; + bool operator!=(const const_iterator &i) const; RegisterPool::const_iterator operator++(); RegisterPool::const_iterator operator++(int); }; diff --git a/proccontrol/h/PlatFeatures.h b/proccontrol/h/PlatFeatures.h index 208fe2158e..56feb155e0 100644 --- a/proccontrol/h/PlatFeatures.h +++ b/proccontrol/h/PlatFeatures.h @@ -34,6 +34,8 @@ #include #include #include +#include +#include #if !defined(PLATFEATURES_H_) #define PLATFEATURES_H_ @@ -349,7 +351,7 @@ extern "C" struct stat64_ret_t { }; typedef stat64_ret_t *stat64_ptr; -typedef boost::shared_ptr int_fileInfo_ptr; +typedef dyncompat::shared_ptr int_fileInfo_ptr; class RemoteIO; class RemoteIOSet; diff --git a/proccontrol/h/ProcessSet.h b/proccontrol/h/ProcessSet.h index 31c078c4f5..db7200f1a6 100644 --- a/proccontrol/h/ProcessSet.h +++ b/proccontrol/h/ProcessSet.h @@ -33,6 +33,10 @@ #include #include +#include +#include +#include +#include #include "dyntypes.h" #include "PCProcess.h" @@ -57,10 +61,10 @@ class MemoryUsageSet; class PSetFeatures; class TSetFeatures; -typedef boost::shared_ptr ProcessSet_ptr; -typedef boost::shared_ptr ThreadSet_ptr; -typedef boost::shared_ptr ProcessSet_const_ptr; -typedef boost::shared_ptr ThreadSet_const_ptr; +typedef dyncompat::shared_ptr ProcessSet_ptr; +typedef dyncompat::shared_ptr ThreadSet_ptr; +typedef dyncompat::shared_ptr ProcessSet_const_ptr; +typedef dyncompat::shared_ptr ThreadSet_const_ptr; /** * AddressSet represents a set of Process/Address pairs. It is used to @@ -80,15 +84,15 @@ class PC_EXPORT AddressSet { private: int_addressSet *iaddrs; - friend void boost::checked_delete(AddressSet *) CHECKED_DELETE_NOEXCEPT; + friend void dyncompat::checked_delete(AddressSet *) noexcept; friend class ProcessSet; AddressSet(); ~AddressSet(); public: int_addressSet *get_iaddrs() { return iaddrs; } - typedef boost::shared_ptr ptr; - typedef boost::shared_ptr const_ptr; + typedef dyncompat::shared_ptr ptr; + typedef dyncompat::shared_ptr const_ptr; /** * Create new Address sets @@ -160,7 +164,7 @@ class PC_EXPORT AddressSet * perform collective operations on the entire set, which may be more effecient * than the equivalent sequential operations. **/ -class PC_EXPORT ProcessSet : public boost::enable_shared_from_this +class PC_EXPORT ProcessSet : public dyncompat::enable_shared_from_this { friend class ThreadSet; private: @@ -170,13 +174,13 @@ class PC_EXPORT ProcessSet : public boost::enable_shared_from_this ProcessSet(); ~ProcessSet(); - friend void boost::checked_delete(ProcessSet *) CHECKED_DELETE_NOEXCEPT; + friend void dyncompat::checked_delete(ProcessSet *) noexcept; public: int_processSet *getIntProcessSet(); //Not for public use - typedef boost::shared_ptr ptr; - typedef boost::shared_ptr const_ptr; - typedef boost::weak_ptr weak_ptr; - typedef boost::weak_ptr const_weak_ptr; + typedef dyncompat::shared_ptr ptr; + typedef dyncompat::shared_ptr const_ptr; + typedef dyncompat::weak_ptr weak_ptr; + typedef dyncompat::weak_ptr const_weak_ptr; /** * Create new ProcessSets from existing Process objects @@ -250,6 +254,7 @@ class PC_EXPORT ProcessSet : public boost::enable_shared_from_this public: const_iterator(); ~const_iterator(); + const_iterator(const const_iterator&) = default; Process::ptr operator*() const; bool operator==(const const_iterator &i) const; bool operator!=(const const_iterator &i) const; @@ -407,19 +412,19 @@ class PC_EXPORT ProcessSet : public boost::enable_shared_from_this **/ ProcessSet::const_ptr getAllProcs(); -class PC_EXPORT ThreadSet : public boost::enable_shared_from_this { +class PC_EXPORT ThreadSet : public dyncompat::enable_shared_from_this { private: int_threadSet *ithrset; TSetFeatures *features; ThreadSet(); ~ThreadSet(); - friend void boost::checked_delete(ThreadSet *) CHECKED_DELETE_NOEXCEPT; + friend void dyncompat::checked_delete(ThreadSet *) noexcept; public: - typedef boost::shared_ptr ptr; - typedef boost::shared_ptr const_ptr; - typedef boost::weak_ptr weak_ptr; - typedef boost::weak_ptr const_weak_ptr; + typedef dyncompat::shared_ptr ptr; + typedef dyncompat::shared_ptr const_ptr; + typedef dyncompat::weak_ptr weak_ptr; + typedef dyncompat::weak_ptr const_weak_ptr; int_threadSet *getIntThreadSet() const; @@ -449,8 +454,8 @@ class PC_EXPORT ThreadSet : public boost::enable_shared_from_this { iterator(int_threadSet::iterator i); public: Thread::ptr operator*(); - bool operator==(const iterator &i); - bool operator!=(const iterator &i); + bool operator==(const iterator &i) const; + bool operator!=(const iterator &i) const; ThreadSet::iterator operator++(); ThreadSet::iterator operator++(int); }; @@ -463,9 +468,10 @@ class PC_EXPORT ThreadSet : public boost::enable_shared_from_this { public: const_iterator(); ~const_iterator(); + const_iterator(const const_iterator&) = default; Thread::ptr operator*(); - bool operator==(const const_iterator &i); - bool operator!=(const const_iterator &i); + bool operator==(const const_iterator &i) const; + bool operator!=(const const_iterator &i) const; ThreadSet::const_iterator operator++(); ThreadSet::const_iterator operator++(int); }; diff --git a/proccontrol/src/DecoderWindows.C b/proccontrol/src/DecoderWindows.C index afa8e99ede..5ad98cb7ee 100644 --- a/proccontrol/src/DecoderWindows.C +++ b/proccontrol/src/DecoderWindows.C @@ -64,16 +64,16 @@ Dyninst::Address DecoderWindows::adjustTrapAddr(Dyninst::Address addr, Dyninst:: void DecoderWindows::dumpSurroundingMemory( unsigned problemArea, int_process* proc ) { - fprintf(stderr, "segfault in mutatee at %p\n", problemArea); + fprintf(stderr, "segfault in mutatee at %ux\n", problemArea); for(unsigned i = problemArea-16; i < problemArea+16; i++) { unsigned char tmp = 0; if(proc->plat_readMem(NULL, &tmp, i, 1)) { - fprintf(stderr, "%p: %x\n", i, tmp); + fprintf(stderr, "%ux: %x\n", i, tmp); } else { - fprintf(stderr, "failed to read from %p\n", i); + fprintf(stderr, "failed to read from %ux\n", i); } } } diff --git a/proccontrol/src/DecoderWindows.h b/proccontrol/src/DecoderWindows.h index ed9a9e2f1f..a9a33c3f0d 100644 --- a/proccontrol/src/DecoderWindows.h +++ b/proccontrol/src/DecoderWindows.h @@ -30,6 +30,8 @@ #if !defined(DECODER_WINDOWS_H) #define DECODER_WINDOWS_H +#include +#include #include "Decoder.h" #include "Event.h" #include "int_process.h" diff --git a/proccontrol/src/Display b/proccontrol/src/Display deleted file mode 100644 index e69de29bb2..0000000000 diff --git a/proccontrol/src/FileType b/proccontrol/src/FileType deleted file mode 100644 index e69de29bb2..0000000000 diff --git a/proccontrol/src/GeneratorWindows.C b/proccontrol/src/GeneratorWindows.C index 8f5c4e71da..57cd0202ba 100644 --- a/proccontrol/src/GeneratorWindows.C +++ b/proccontrol/src/GeneratorWindows.C @@ -28,6 +28,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include "Generator.h" #include "GeneratorWindows.h" #include "DecoderWindows.h" diff --git a/proccontrol/src/GeneratorWindows.h b/proccontrol/src/GeneratorWindows.h index 031069a57c..256c57dfaa 100644 --- a/proccontrol/src/GeneratorWindows.h +++ b/proccontrol/src/GeneratorWindows.h @@ -35,6 +35,7 @@ #include "int_process.h" #include #include +#include #include @@ -65,7 +66,7 @@ class GeneratorWindows : public GeneratorMT }; struct processData { - typedef boost::shared_ptr ptr; + typedef dyncompat::shared_ptr ptr; bool unhandled_exception; int_process* proc; state_t state; diff --git a/proccontrol/src/Initial b/proccontrol/src/Initial deleted file mode 100644 index e69de29bb2..0000000000 diff --git a/proccontrol/src/Others b/proccontrol/src/Others deleted file mode 100644 index e69de29bb2..0000000000 diff --git a/proccontrol/src/arm_process.C b/proccontrol/src/arm_process.C index d4cf870320..75cc4f97f9 100644 --- a/proccontrol/src/arm_process.C +++ b/proccontrol/src/arm_process.C @@ -28,6 +28,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include #include #include "proccontrol/src/arm_process.h" diff --git a/proccontrol/src/arm_process.h b/proccontrol/src/arm_process.h index d2f5a8333e..648932f691 100644 --- a/proccontrol/src/arm_process.h +++ b/proccontrol/src/arm_process.h @@ -31,6 +31,8 @@ #if !defined(arm_process_h_) #define arm_process_h_ +#include +#include #include #include #include "int_process.h" diff --git a/proccontrol/src/event.C b/proccontrol/src/event.C index 20e8303d3a..6c35e8d5f2 100644 --- a/proccontrol/src/event.C +++ b/proccontrol/src/event.C @@ -535,6 +535,17 @@ Dyninst::LWP EventNewLWP::getLWP() const Thread::const_ptr EventNewLWP::getNewThread() const { int_thread *thr = getProcess()->llproc()->threadPool()->findThreadByLWP(lwp); + +#if defined(os_linux) || defined(os_freebsd) + if (!thr) { + int pid = getProcess()->llproc()->getPid(); + if (lwp != pid) { + pthrd_printf("Non-main thread %d/%d not found\n", pid, lwp); + return Thread::const_ptr(); + } + } +#endif + assert(thr); return thr->thread(); } @@ -1365,41 +1376,41 @@ bool int_eventAsyncFileRead::isComplete() #define DEFN_EVENT_CAST(NAME, TYPE) \ NAME::ptr Event::get ## NAME() { \ if (etype.code() != EventType::TYPE) return NAME::ptr(); \ - return boost::static_pointer_cast(shared_from_this()); \ + return dyncompat::static_pointer_cast(shared_from_this()); \ } \ NAME::const_ptr Event::get ## NAME() const { \ if (etype.code() != EventType::TYPE) return NAME::const_ptr(); \ - return boost::static_pointer_cast(shared_from_this()); \ + return dyncompat::static_pointer_cast(shared_from_this()); \ } #define DEFN_EVENT_CAST2(NAME, TYPE, TYPE2) \ NAME::ptr Event::get ## NAME() { \ if (etype.code() != EventType::TYPE && etype.code() != EventType::TYPE2) return NAME::ptr(); \ - return boost::static_pointer_cast(shared_from_this()); \ + return dyncompat::static_pointer_cast(shared_from_this()); \ } \ NAME::const_ptr Event::get ## NAME() const { \ if (etype.code() != EventType::TYPE && etype.code() != EventType::TYPE2) return NAME::const_ptr(); \ - return boost::static_pointer_cast(shared_from_this()); \ + return dyncompat::static_pointer_cast(shared_from_this()); \ } #define DEFN_EVENT_CAST3(NAME, TYPE, TYPE2, TYPE3) \ NAME::ptr Event::get ## NAME() { \ if (etype.code() != EventType::TYPE && etype.code() != EventType::TYPE2 && etype.code() != EventType::TYPE3) return NAME::ptr(); \ - return boost::static_pointer_cast(shared_from_this()); \ + return dyncompat::static_pointer_cast(shared_from_this()); \ } \ NAME::const_ptr Event::get ## NAME() const { \ if (etype.code() != EventType::TYPE && etype.code() != EventType::TYPE2 && etype.code() != EventType::TYPE3) return NAME::const_ptr(); \ - return boost::static_pointer_cast(shared_from_this()); \ + return dyncompat::static_pointer_cast(shared_from_this()); \ } #define DEFN_EVENT_CAST4(NAME, TYPE, TYPE2, TYPE3, TYPE4) \ NAME::ptr Event::get ## NAME() { \ if (etype.code() != EventType::TYPE && etype.code() != EventType::TYPE2 && etype.code() != EventType::TYPE3 && etype.code() != EventType::TYPE4) return NAME::ptr(); \ - return boost::static_pointer_cast(shared_from_this()); \ + return dyncompat::static_pointer_cast(shared_from_this()); \ } \ NAME::const_ptr Event::get ## NAME() const { \ if (etype.code() != EventType::TYPE && etype.code() != EventType::TYPE2 && etype.code() != EventType::TYPE3 && etype.code() != EventType::TYPE4) return NAME::const_ptr(); \ - return boost::static_pointer_cast(shared_from_this()); \ + return dyncompat::static_pointer_cast(shared_from_this()); \ } diff --git a/proccontrol/src/freebsd.C b/proccontrol/src/freebsd.C index 74eed0f281..bf9d001273 100644 --- a/proccontrol/src/freebsd.C +++ b/proccontrol/src/freebsd.C @@ -28,7 +28,8 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "common/h/dyn_regs.h" +#include +#include "Architecture.h" #include "common/h/dyntypes.h" #include "PCErrors.h" #include "Generator.h" @@ -792,7 +793,7 @@ freebsd_process::freebsd_process(Dyninst::PID pid_, int_process *p) : freebsd_process::~freebsd_process() { - int eventQueue = getEventQueue(); + int eventQueue = freebsd_process::getEventQueue(); if( -1 != eventQueue ) { // Remove the event for this process struct kevent event; diff --git a/proccontrol/src/freebsd.h b/proccontrol/src/freebsd.h index 26ef642c6c..b4d44e7ac0 100644 --- a/proccontrol/src/freebsd.h +++ b/proccontrol/src/freebsd.h @@ -30,6 +30,11 @@ #if !defined(FREEBSD_H_) #define FREEBSD_H_ +#include +#include +#include +#include +#include #include "Generator.h" #include "Event.h" #include "Decoder.h" diff --git a/proccontrol/src/generator.C b/proccontrol/src/generator.C index a2067e221c..56309c89e7 100644 --- a/proccontrol/src/generator.C +++ b/proccontrol/src/generator.C @@ -27,6 +27,7 @@ * License along with this library; if not, write to the Free Software * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include "Generator.h" #include "Event.h" #include "Mailbox.h" diff --git a/proccontrol/src/handler.C b/proccontrol/src/handler.C index 9f7d667057..280efc31b9 100644 --- a/proccontrol/src/handler.C +++ b/proccontrol/src/handler.C @@ -27,6 +27,7 @@ * License along with this library; if not, write to the Free Software * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include "Handler.h" #include "PCErrors.h" #include "PCProcess.h" @@ -39,7 +40,7 @@ #include "response.h" #include "int_event.h" #include "processplat.h" -#include "common/h/dyn_regs.h" +#include "registers/MachRegister.h" #if defined(os_windows) #include "windows_process.h" @@ -53,10 +54,6 @@ using namespace std; #include #include -#ifdef _MSC_VER -#pragma warning(disable:4477) -#endif - Handler::Handler(std::string name_) : name(name_) { @@ -1455,7 +1452,22 @@ Handler::handler_ret_t HandleBreakpoint::handleEvent(Event::ptr ev) if (!int_ebp->cb_bps.empty() && !ebp->suppressCB()) { pthrd_printf("BP handler is setting user state to reflect breakpoint\n"); - switch (ebp->getSyncType()) { + + const Event::SyncType effective_sync_type = [&ebp, &hl_bps]() { + /** + * A synchronous breakpoint requires all threads in the process to be + * stopped before it is "executed". + **/ + for(auto &&bp : hl_bps) { + if(bp->isSynchronous()) { + pthrd_printf("Found synchronous breakpoint, upgrading to sync_process\n"); + return Event::sync_process; + } + } + return ebp->getSyncType(); + }(); + + switch (effective_sync_type) { case Event::sync_process: { int_threadPool *pool = proc->threadPool(); for (int_threadPool::iterator i = pool->begin(); i != pool->end(); i++) diff --git a/proccontrol/src/int_event.h b/proccontrol/src/int_event.h index 9bd2f547db..0864578496 100644 --- a/proccontrol/src/int_event.h +++ b/proccontrol/src/int_event.h @@ -35,6 +35,9 @@ #endif #include "response.h" #include "resp.h" +#include +#include +#include #include namespace Dyninst { diff --git a/proccontrol/src/int_handler.h b/proccontrol/src/int_handler.h index 85eb1aec75..ec9207f846 100644 --- a/proccontrol/src/int_handler.h +++ b/proccontrol/src/int_handler.h @@ -30,6 +30,7 @@ #include "Handler.h" #include "PCProcess.h" +#include #include #include diff --git a/proccontrol/src/int_process.h b/proccontrol/src/int_process.h index 0e7e52bf55..0e27db7f2d 100644 --- a/proccontrol/src/int_process.h +++ b/proccontrol/src/int_process.h @@ -39,10 +39,13 @@ #include "response.h" #include "memcache.h" -#include "common/h/dyn_regs.h" +#include "registers/MachRegister.h" +#include "Architecture.h" #include "common/h/SymReader.h" #include "common/src/dthread.h" +#include +#include #include #include #include @@ -70,7 +73,7 @@ typedef std::multimap i typedef std::set int_processSet; typedef std::set int_threadSet; -typedef boost::shared_ptr int_iRPC_ptr; +typedef dyncompat::shared_ptr int_iRPC_ptr; typedef std::map > dynreg_to_user_t; typedef std::list rpc_list_t; @@ -1301,6 +1304,10 @@ class int_breakpoint bool procstopper; bool suppress_callbacks; bool offset_transfer; + + // all threads in process need to be synchronized at this breakpoint + bool is_proc_synchronous{false}; + std::set thread_specific; public: int_breakpoint(Breakpoint::ptr up); @@ -1327,6 +1334,9 @@ class int_breakpoint void setSuppressCallbacks(bool); bool suppressCallbacks(void) const; + + void makeSynchronous() { is_proc_synchronous = true; } + bool isSynchronous() const { return is_proc_synchronous; } bool isHW() const; unsigned getHWSize() const; diff --git a/proccontrol/src/int_thread_db.C b/proccontrol/src/int_thread_db.C index 63018b3cf1..d84ee1a507 100644 --- a/proccontrol/src/int_thread_db.C +++ b/proccontrol/src/int_thread_db.C @@ -28,7 +28,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "common/src/Types.h" +#include #include "int_thread_db.h" @@ -46,7 +46,7 @@ #include "int_event.h" #include "Mailbox.h" -#include "boost/filesystem.hpp" +#include using namespace std; @@ -949,7 +949,7 @@ td_thragent_t *thread_db_process::getThreadDBAgent() { static string stripLibraryName(const char *libname) { - boost::filesystem::path p(libname); + std::filesystem::path p(libname); return p.filename().string(); } diff --git a/proccontrol/src/int_thread_db.h b/proccontrol/src/int_thread_db.h index 42f59ddbf0..ab1221f43c 100644 --- a/proccontrol/src/int_thread_db.h +++ b/proccontrol/src/int_thread_db.h @@ -56,6 +56,8 @@ extern "C" { #include "proc_service_wrapper.h" } +#include +#include #include #include #include diff --git a/proccontrol/src/irpc.C b/proccontrol/src/irpc.C index 8be07974a2..f07c8906a1 100644 --- a/proccontrol/src/irpc.C +++ b/proccontrol/src/irpc.C @@ -48,10 +48,6 @@ #include #include -#ifdef _MSC_VER -#pragma warning(disable:4477) -#endif - using namespace std; unsigned long int_iRPC::next_id; @@ -146,6 +142,7 @@ void int_iRPC::setBinarySize(unsigned long s) void int_iRPC::copyBinaryBlob(void *b, unsigned long s) { + if(binary_blob && freeBinaryBlob) free(binary_blob); binary_blob = malloc(s); assert(binary_blob); binary_size = s; diff --git a/proccontrol/src/irpc.h b/proccontrol/src/irpc.h index a52ee0f4aa..e68444fb34 100644 --- a/proccontrol/src/irpc.h +++ b/proccontrol/src/irpc.h @@ -31,6 +31,7 @@ #if !defined(IRPC_H_) #define IRPC_H_ +#include #include #include #include @@ -58,9 +59,9 @@ class IRPC; class iRPCAllocation { - friend void boost::checked_delete(iRPCAllocation *) CHECKED_DELETE_NOEXCEPT; + friend void dyncompat::checked_delete(iRPCAllocation *) noexcept; public: - typedef boost::shared_ptr ptr; + typedef dyncompat::shared_ptr ptr; iRPCAllocation() : addr(0), size(0), @@ -87,17 +88,17 @@ class iRPCAllocation int ref_count; //These are NULL if the user handed us memory to run the iRPC in. - boost::weak_ptr creation_irpc; - boost::weak_ptr deletion_irpc; + dyncompat::weak_ptr creation_irpc; + dyncompat::weak_ptr deletion_irpc; }; -class int_iRPC : public boost::enable_shared_from_this +class int_iRPC : public dyncompat::enable_shared_from_this { - friend void boost::checked_delete(int_iRPC *) CHECKED_DELETE_NOEXCEPT; + friend void dyncompat::checked_delete(int_iRPC *) noexcept; friend class iRPCMgr; friend class Dyninst::ProcControlAPI::IRPC; public: - typedef boost::shared_ptr ptr; + typedef dyncompat::shared_ptr ptr; typedef enum { diff --git a/proccontrol/src/linux.C b/proccontrol/src/linux.C index ac4d169cc4..c21649aa39 100644 --- a/proccontrol/src/linux.C +++ b/proccontrol/src/linux.C @@ -28,6 +28,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include #include #include @@ -42,9 +43,13 @@ #include #include -#include "common/h/dyn_regs.h" +#include "registers/x86_regs.h" +#include "registers/x86_64_regs.h" +#include "registers/ppc32_regs.h" +#include "registers/ppc64_regs.h" +#include "registers/aarch64_regs.h" #include "common/h/dyntypes.h" - +#include "common/src/vm_maps.h" #include "compiler_annotations.h" #include "common/src/pathName.h" @@ -68,15 +73,19 @@ #include "common/src/linuxKludges.h" #include "common/src/parseauxv.h" -#include "boost/shared_ptr.hpp" +#include "dyncompat/shared_ptr.hpp" + +#include "unaligned_memory_access.h" //needed by GETREGSET/SETREGSET #if defined(arch_aarch64) #include #include #include +#if !defined(WITH_SYMLITE) #include #endif +#endif // Before glibc-2.7, sys/ptrace.h lacked PTRACE_O_* and PTRACE_EVENT_*, so we // need them from linux/ptrace.h. (Conditionally, as later glibc conflicts.) @@ -1106,7 +1115,7 @@ bool linux_process::plat_attachWillTriggerStop() { // Retrieve the state of the process and its controlling tty snprintf(procName, 64, "/proc/%d/stat", pid); - boost::shared_ptr sfile(fopen(procName, "r"), fclose); + dyncompat::shared_ptr sfile(fopen(procName, "r"), fclose); if (!sfile) { perr_printf("Failed to determine whether attach would trigger stop -- assuming it will\n"); return true; @@ -1136,7 +1145,7 @@ bool linux_process::plat_execed() char proc_exec_name[128]; snprintf(proc_exec_name, 128, "/proc/%d/exe", getPid()); - executable = std::move(resolve_file_path(proc_exec_name)); + executable = resolve_file_path(proc_exec_name); return true; } @@ -1887,7 +1896,7 @@ bool linux_process::readStatM(unsigned long &stk, unsigned long &heap, unsigned path[63] = '\0'; unsigned long size, resident, shared, text, lib, data, dt; - boost::shared_ptr f(fopen(path, "r"), fclose); + dyncompat::shared_ptr f(fopen(path, "r"), fclose); if (!f) { perr_printf("Could not open %s: %s\n", path, strerror(errno)); setLastError(err_internal, "Could not access /proc"); @@ -2361,11 +2370,11 @@ bool linux_thread::plat_getAllRegisters(int_registerPool ®pool) } if (Dyninst::getArchAddressWidth(curplat) == 4) { uint32_t val = (uint32_t) result; - *((uint32_t *) (user_area + i->second.first)) = val; + write_memory_as(user_area + i->second.first, val); } else if (Dyninst::getArchAddressWidth(curplat) == 8) { uint64_t val = (uint64_t) result; - *((uint64_t *) (user_area + i->second.first)) = val; + write_memory_as(user_area + i->second.first, val); } else { assert(0); @@ -2393,14 +2402,14 @@ bool linux_thread::plat_getAllRegisters(int_registerPool ®pool) if (size == 4) { if( sizeof(void *) == 8 ) { // Avoid endian issues - uint64_t tmpVal = *((uint64_t *) (user_area+offset)); + auto tmpVal = Dyninst::read_memory_as(user_area+offset); val = (uint32_t) tmpVal; }else{ - val = *((uint32_t *) (user_area+offset)); + val = Dyninst::read_memory_as(user_area+offset); } } else if (size == 8) { - val = *((uint64_t *) (user_area+offset)); + val = Dyninst::read_memory_as(user_area+offset); } else { assert(0); @@ -2677,13 +2686,13 @@ bool linux_thread::plat_convertToSystemRegs(const int_registerPool ®pool, uns if (size == 4) { if( sizeof(void *) == 8 ) { - *((uint64_t *) (user_area+offset)) = (uint64_t) val; + write_memory_as(user_area+offset, uint64_t{val}); } else { - *((uint32_t *) (user_area+offset)) = (uint32_t) val; + write_memory_as(user_area+offset, static_cast(val)); } } else if (size == 8) { - *((uint64_t *) (user_area+offset)) = (uint64_t) val; + write_memory_as(user_area+offset, uint64_t{val}); } else { assert(0); diff --git a/proccontrol/src/linux.h b/proccontrol/src/linux.h index 261087a736..80af3197c1 100644 --- a/proccontrol/src/linux.h +++ b/proccontrol/src/linux.h @@ -49,6 +49,10 @@ #include "processplat.h" #include "common/src/dthread.h" +#include +#include +#include +#include #include #include diff --git a/proccontrol/src/loadLibrary/codegen-aarch64.C b/proccontrol/src/loadLibrary/codegen-aarch64.C index 3c1e2732af..7fc4c53dab 100644 --- a/proccontrol/src/loadLibrary/codegen-aarch64.C +++ b/proccontrol/src/loadLibrary/codegen-aarch64.C @@ -8,6 +8,8 @@ #include "common/src/arch-aarch64.h" +#include "unaligned_memory_access.h" + using namespace Dyninst; using namespace NS_aarch64; using namespace ProcControlAPI; @@ -73,8 +75,8 @@ bool Codegen::generateCallAARCH64(Address addr, const std::vector
&args for(unsigned int i = 0; i <= 12; i+=4){ BYTE_ASSGN(_buf, i, (uint16_t)(val>>(i*4)) ) SWAP4BYTE(_buf, i) - retAddr = copyInt( *(unsigned int*)(_buf+i) + regIndex); - pthrd_printf("0x%8lx: 0x%8x\n", retAddr, *(unsigned int*)(_buf+i) + regIndex); + retAddr = copyInt( Dyninst::read_memory_as(_buf+i) + regIndex); + pthrd_printf("0x%8lx: 0x%8x\n", retAddr, Dyninst::read_memory_as(_buf+i) + regIndex); } regIndex ++; } @@ -84,8 +86,8 @@ bool Codegen::generateCallAARCH64(Address addr, const std::vector
&args for(unsigned int i = 0; i <= 12; i+=4){ BYTE_ASSGN(_buf, i, (uint16_t)(addr>>(i*4)) ) SWAP4BYTE(_buf, i) - retAddr = copyInt( *(unsigned int*)(_buf+i) + X8); //x8 = 8 - pthrd_printf("0x%8lx: 0x%8x\n", retAddr, *(unsigned int*)(_buf+i) + X8); + retAddr = copyInt( Dyninst::read_memory_as(_buf+i) + X8); //x8 = 8 + pthrd_printf("0x%8lx: 0x%8x\n", retAddr, Dyninst::read_memory_as(_buf+i) + X8); } //blr x8 diff --git a/proccontrol/src/loadLibrary/codegen-linux.C b/proccontrol/src/loadLibrary/codegen-linux.C index c2017a36e2..83b965481f 100644 --- a/proccontrol/src/loadLibrary/codegen-linux.C +++ b/proccontrol/src/loadLibrary/codegen-linux.C @@ -6,6 +6,7 @@ #include #include "PCProcess.h" #include +#include using namespace Dyninst; using namespace std; diff --git a/proccontrol/src/loadLibrary/codegen.C b/proccontrol/src/loadLibrary/codegen.C index 1244b74484..852e5db0e8 100644 --- a/proccontrol/src/loadLibrary/codegen.C +++ b/proccontrol/src/loadLibrary/codegen.C @@ -1,6 +1,7 @@ // Platform-independent code generation methods; mainly function // lookup +#include #include "loadLibrary/codegen.h" #include #include "int_process.h" diff --git a/proccontrol/src/loadLibrary/codegen.h b/proccontrol/src/loadLibrary/codegen.h index b30c7676fa..aa96467539 100644 --- a/proccontrol/src/loadLibrary/codegen.h +++ b/proccontrol/src/loadLibrary/codegen.h @@ -6,6 +6,9 @@ #if !defined(_INJECTOR_CODEGEN_H_) #define _INJECTOR_CODEGEN_H_ +#include +#include +#include #include "PCProcess.h" #include "Buffer.h" diff --git a/proccontrol/src/loadLibrary/injector.h b/proccontrol/src/loadLibrary/injector.h index 96d9b10529..40f74e68e6 100644 --- a/proccontrol/src/loadLibrary/injector.h +++ b/proccontrol/src/loadLibrary/injector.h @@ -3,6 +3,7 @@ #if !defined(_INJECTOR_H_) #define _INJECTOR_H_ +#include #include "PCProcess.h" namespace Dyninst { diff --git a/proccontrol/src/memcache.C b/proccontrol/src/memcache.C index d13016086f..ca0616112a 100644 --- a/proccontrol/src/memcache.C +++ b/proccontrol/src/memcache.C @@ -28,6 +28,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include "memcache.h" #include "int_process.h" #include @@ -301,9 +302,7 @@ async_ret_t memCache::doOperation(memEntry *me, int_thread *op_thread) return aret_error; } - memEntry *me_copy = new memEntry(me, me->buffer); - - mem_cache.push_back(me_copy); + mem_cache.push_back(new memEntry(me, me->buffer)); last_operation = mem_cache.end(); last_operation--; diff --git a/proccontrol/src/memcache.h b/proccontrol/src/memcache.h index 8ea60df4f8..74af12c748 100644 --- a/proccontrol/src/memcache.h +++ b/proccontrol/src/memcache.h @@ -33,6 +33,7 @@ #include "common/h/dyntypes.h" #include "response.h" +#include #include #include diff --git a/proccontrol/src/mmapalloc.C b/proccontrol/src/mmapalloc.C index d69b0767ab..4cc53d5b8e 100644 --- a/proccontrol/src/mmapalloc.C +++ b/proccontrol/src/mmapalloc.C @@ -28,10 +28,15 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "common/src/Types.h" #include "mmapalloc.h" #include #include +#include "unaligned_memory_access.h" +#include "registers/ppc32_regs.h" +#include "registers/ppc64_regs.h" +#include "registers/x86_regs.h" +#include "registers/x86_64_regs.h" +#include "registers/aarch64_regs.h" static const unsigned int linux_x86_64_mmap_flags_position = 26; static const unsigned int linux_x86_64_mmap_size_position = 43; @@ -489,14 +494,17 @@ bool mmap_alloc_process::plat_createAllocationSnippet(Dyninst::Address addr, boo memcpy(buffer, buf_tmp, buffer_size); //Assuming endianess of debugger and debugee match. - *((unsigned int *) (((char *) buffer)+size_pos)) = size; - *((unsigned int *) (((char *) buffer)+flags_pos)) = flags; - if (addr_size == 8) - *((unsigned long *) (((char *) buffer)+addr_pos)) = addr; - else if (addr_size == 4) - *((unsigned *) (((char *) buffer)+addr_pos)) = (unsigned) addr; - else + assert(size <= std::numeric_limits::max() && "size more than 32 bits"); + write_memory_as(static_cast(buffer)+size_pos, static_cast(size)); + write_memory_as(static_cast(buffer)+flags_pos, static_cast(flags)); + if (addr_size == 8) { + write_memory_as(static_cast(buffer)+addr_pos, uint64_t{addr}); + } else if (addr_size == 4) { + assert(addr <= std::numeric_limits::max() && "addr more than 32 bits"); + write_memory_as(static_cast(buffer)+addr_pos, static_cast(addr)); + } else { assert(0); + } } else if (getTargetArch() == Arch_ppc32) { unsigned int flags_hi_position; @@ -528,12 +536,12 @@ bool mmap_alloc_process::plat_createAllocationSnippet(Dyninst::Address addr, boo memcpy(buffer, buf_tmp, buffer_size); // Assuming endianess of debugger and debuggee match - *((uint16_t *) (((char *) buffer)+size_hi_position)) = (uint16_t)(size >> 16); - *((uint16_t *) (((char *) buffer)+size_lo_position)) = (uint16_t)size; - *((uint16_t *) (((char *) buffer)+flags_hi_position)) = (uint16_t)(flags >> 16); - *((uint16_t *) (((char *) buffer)+flags_lo_position)) = (uint16_t)flags; - *((uint16_t *) (((char *) buffer)+addr_hi_position)) = (uint16_t)(addr >> 16); - *((uint16_t *) (((char *) buffer)+addr_lo_position)) = (uint16_t)addr; + write_memory_as(static_cast(buffer)+size_hi_position, static_cast(size >> 16)); + write_memory_as(static_cast(buffer)+size_lo_position, static_cast(size)); + write_memory_as(static_cast(buffer)+flags_hi_position, static_cast(flags >> 16)); + write_memory_as(static_cast(buffer)+flags_lo_position, static_cast(flags)); + write_memory_as(static_cast(buffer)+addr_hi_position, static_cast(addr >> 16)); + write_memory_as(static_cast(buffer)+addr_lo_position, static_cast(addr)); } else if (getTargetArch() == Arch_ppc64) { unsigned int flags_highest_position; @@ -578,18 +586,18 @@ bool mmap_alloc_process::plat_createAllocationSnippet(Dyninst::Address addr, boo uint32_t *pwords = (uint32_t *)buffer; // MJMTODO - Assumes endianess of debugger and debuggee match - pwords[size_highest_position] |= (uint32_t)(((uint64_t)size >> 48) & 0x0000ffff); - pwords[size_higher_position] |= (uint32_t)(((uint64_t)size >> 32) & 0x0000ffff); - pwords[size_hi_position] |= (uint32_t)(((uint64_t)size >> 16) & 0x0000ffff); - pwords[size_lo_position] |= (uint32_t)((uint64_t)size & 0x0000ffff); - pwords[flags_highest_position] |= (uint32_t)(((uint64_t)flags >> 48) & 0x0000ffff); - pwords[flags_higher_position] |= (uint32_t)(((uint64_t)flags >> 32) & 0x0000ffff); - pwords[flags_hi_position] |= (uint32_t)(((uint64_t)flags >> 16) & 0x0000ffff); - pwords[flags_lo_position] |= (uint32_t)((uint64_t)flags & 0x0000ffff); - pwords[addr_highest_position] |= (uint32_t)(((uint64_t)addr >> 48) & 0x0000ffff); - pwords[addr_higher_position] |= (uint32_t)(((uint64_t)addr >> 32) & 0x0000ffff); - pwords[addr_hi_position] |= (uint32_t)(((uint64_t)addr >> 16) & 0x0000ffff); - pwords[addr_lo_position] |= (uint32_t)((uint64_t)addr & 0x0000ffff); + pwords[size_highest_position] |= static_cast((uint64_t{size} >> 48) & 0x0000ffff); + pwords[size_higher_position] |= static_cast((uint64_t{size} >> 32) & 0x0000ffff); + pwords[size_hi_position] |= static_cast((uint64_t{size} >> 16) & 0x0000ffff); + pwords[size_lo_position] |= static_cast(uint64_t{size} & 0x0000ffff); + pwords[flags_highest_position] |= static_cast((static_cast(flags) >> 48) & 0x0000ffff); + pwords[flags_higher_position] |= static_cast((static_cast(flags) >> 32) & 0x0000ffff); + pwords[flags_hi_position] |= static_cast((static_cast(flags) >> 16) & 0x0000ffff); + pwords[flags_lo_position] |= static_cast(static_cast(flags) & 0x0000ffff); + pwords[addr_highest_position] |= static_cast((uint64_t{addr} >> 48) & 0x0000ffff); + pwords[addr_higher_position] |= static_cast((uint64_t{addr} >> 32) & 0x0000ffff); + pwords[addr_hi_position] |= static_cast((uint64_t{addr} >> 16) & 0x0000ffff); + pwords[addr_lo_position] |= static_cast(uint64_t{addr} & 0x0000ffff); } else if( getTargetArch() == Arch_aarch64 ){ const void *buf_tmp; unsigned int addr_pos, size_pos, flags_pos; @@ -613,34 +621,34 @@ bool mmap_alloc_process::plat_createAllocationSnippet(Dyninst::Address addr, boo // To avoid the matter of endianness, I decided to operate on byte. pthrd_printf("ARM-info: create alloc snippet...\n"); #define BYTE_ASSGN(POS, VAL) \ - (*(((char *) buffer) + POS + 1)) |= ((VAL>>11)&0x1f);\ - (*(((char *) buffer) + POS + 2)) |= ((VAL>> 3)&0xff);\ - (*(((char *) buffer) + POS + 3)) |= ((VAL<< 5)&0xf0); + (*(static_cast(buffer) + POS + 1)) |= ((VAL>>11)&0x1f);\ + (*(static_cast(buffer) + POS + 2)) |= ((VAL>> 3)&0xff);\ + (*(static_cast(buffer) + POS + 3)) |= ((VAL<< 5)&0xf0); - BYTE_ASSGN(addr_pos, (uint16_t)(addr) ) - BYTE_ASSGN(addr_pos+4, (uint16_t)(addr>>16) ) - BYTE_ASSGN(addr_pos+8, (uint16_t)(addr>>32) ) - BYTE_ASSGN(addr_pos+12, (uint16_t)(addr>>48) ) + BYTE_ASSGN(addr_pos, static_cast(addr) ) + BYTE_ASSGN(addr_pos+4, static_cast(addr>>16) ) + BYTE_ASSGN(addr_pos+8, static_cast(addr>>32) ) + BYTE_ASSGN(addr_pos+12, static_cast(addr>>48) ) - BYTE_ASSGN(size_pos, (uint16_t)(size) ) - BYTE_ASSGN(size_pos+4, (uint16_t)(size>>16) ) - BYTE_ASSGN(size_pos+8, (uint16_t)(size>>32) ) - BYTE_ASSGN(size_pos+12, (uint16_t)(size>>48) ) + BYTE_ASSGN(size_pos, static_cast(size) ) + BYTE_ASSGN(size_pos+4, static_cast(size>>16) ) + BYTE_ASSGN(size_pos+8, static_cast(size>>32) ) + BYTE_ASSGN(size_pos+12, static_cast(size>>48) ) - BYTE_ASSGN(flags_pos, (uint16_t)(flags) ) - BYTE_ASSGN(flags_pos+4, (uint16_t)(flags>>16) ) - //BYTE_ASSGN(flags_pos+8, (uint16_t)(flags>>32) ) - //BYTE_ASSGN(flags_pos+12, (uint16_t)(flags>>48) ) + BYTE_ASSGN(flags_pos, static_cast(flags) ) + BYTE_ASSGN(flags_pos+4, static_cast(flags>>16) ) + //BYTE_ASSGN(flags_pos+8, static_cast(flags>>32) ) + //BYTE_ASSGN(flags_pos+12, static_cast(flags>>48) ) //according to experiments, aarch64 is little-endian //the byte order with a word should be re-arranged #define SWAP4BYTE(POS) \ - ((char *)buffer)[POS+3]^= ((char*)buffer)[POS]; \ - ((char *)buffer)[POS] ^= ((char*)buffer)[POS+3]; \ - ((char *)buffer)[POS+3]^= ((char*)buffer)[POS]; \ - ((char *)buffer)[POS+2]^= ((char*)buffer)[POS+1]; \ - ((char *)buffer)[POS+1]^= ((char*)buffer)[POS+2]; \ - ((char *)buffer)[POS+2]^= ((char*)buffer)[POS+1]; + static_cast(buffer)[POS+3]^= static_cast(buffer)[POS]; \ + static_cast(buffer)[POS] ^= static_cast(buffer)[POS+3]; \ + static_cast(buffer)[POS+3]^= static_cast(buffer)[POS]; \ + static_cast(buffer)[POS+2]^= static_cast(buffer)[POS+1]; \ + static_cast(buffer)[POS+1]^= static_cast(buffer)[POS+2]; \ + static_cast(buffer)[POS+2]^= static_cast(buffer)[POS+1]; for(unsigned int i=0; i < buffer_size ; i+=4){ SWAP4BYTE(i) @@ -654,7 +662,7 @@ bool mmap_alloc_process::plat_createAllocationSnippet(Dyninst::Address addr, boo pthrd_printf("flags 0x%x:\n", (unsigned int)flags); for(unsigned int i = 0; i< buffer_size ; i+=4){ - pthrd_printf("0x%8x\n", *((unsigned int *)(((char *)buffer)+i)) ); + pthrd_printf("0x%8x\n", Dyninst::read_memory_as(static_cast(buffer)+i)) ; } #endif @@ -721,13 +729,16 @@ bool mmap_alloc_process::plat_createDeallocationSnippet(Dyninst::Address addr, memcpy(buffer, buf_tmp, buffer_size); //Assuming endianess of debugger and debugee match. - *((unsigned int *) (((char *) buffer)+size_pos)) = size; - if (addr_size == 8) - *((unsigned long *) (((char *) buffer)+addr_pos)) = addr; - else if (addr_size == 4) - *((unsigned *) (((char *) buffer)+addr_pos)) = (unsigned) addr; - else + assert(size <= std::numeric_limits::max() && "size more than 32 bits"); + write_memory_as(static_cast(buffer)+size_pos, static_cast(size)); + if (addr_size == 8) { + write_memory_as(static_cast(buffer)+addr_pos, uint64_t{addr}); + } else if (addr_size == 4) { + assert(addr <= std::numeric_limits::max() && "addr more than 32 bits"); + write_memory_as(static_cast(buffer)+addr_pos, static_cast(addr)); + } else { assert(0); + } } else if (getTargetArch() == Arch_ppc32) { unsigned int size_hi_position; @@ -754,10 +765,10 @@ bool mmap_alloc_process::plat_createDeallocationSnippet(Dyninst::Address addr, memcpy(buffer, buf_tmp, buffer_size); // Assuming endianess of debugger and debuggee match - *((uint16_t *) (((char *) buffer)+size_hi_position)) = (uint16_t)(size >> 16); - *((uint16_t *) (((char *) buffer)+size_lo_position)) = (uint16_t)size; - *((uint16_t *) (((char *) buffer)+addr_hi_position)) = (uint16_t)(addr >> 16); - *((uint16_t *) (((char *) buffer)+addr_lo_position)) = (uint16_t)addr; + write_memory_as(static_cast(buffer)+size_hi_position, static_cast(size >> 16)); + write_memory_as(static_cast(buffer)+size_lo_position, static_cast(size)); + write_memory_as(static_cast(buffer)+addr_hi_position, static_cast(addr >> 16)); + write_memory_as(static_cast(buffer)+addr_lo_position, static_cast(addr)); } else if( getTargetArch() == Arch_ppc64 ) { unsigned int size_highest_position; @@ -791,17 +802,17 @@ bool mmap_alloc_process::plat_createDeallocationSnippet(Dyninst::Address addr, buffer = malloc(buffer_size); memcpy(buffer, buf_tmp, buffer_size); - uint32_t *pwords = (uint32_t *)buffer; + uint32_t *pwords = static_cast(buffer); // MJMTODO - Assumes endianess of debugger and debuggee match - pwords[size_highest_position] |= (uint32_t)(((uint64_t)size >> 48) & 0x0000ffff); - pwords[size_higher_position] |= (uint32_t)(((uint64_t)size >> 32) & 0x0000ffff); - pwords[size_hi_position] |= (uint32_t)(((uint64_t)size >> 16) & 0x0000ffff); - pwords[size_lo_position] |= (uint32_t)((uint64_t)size & 0x0000ffff); - pwords[addr_highest_position] |= (uint32_t)(((uint64_t)addr >> 48) & 0x0000ffff); - pwords[addr_higher_position] |= (uint32_t)(((uint64_t)addr >> 32) & 0x0000ffff); - pwords[addr_hi_position] |= (uint32_t)(((uint64_t)addr >> 16) & 0x0000ffff); - pwords[addr_lo_position] |= (uint32_t)((uint64_t)addr & 0x0000ffff); + pwords[size_highest_position] |= static_cast((uint64_t{size} >> 48) & 0x0000ffff); + pwords[size_higher_position] |= static_cast((uint64_t{size} >> 32) & 0x0000ffff); + pwords[size_hi_position] |= static_cast((uint64_t{size} >> 16) & 0x0000ffff); + pwords[size_lo_position] |= static_cast(uint64_t{size} & 0x0000ffff); + pwords[addr_highest_position] |= static_cast((uint64_t{addr} >> 48) & 0x0000ffff); + pwords[addr_higher_position] |= static_cast((uint64_t{addr} >> 32) & 0x0000ffff); + pwords[addr_hi_position] |= static_cast((uint64_t{addr} >> 16) & 0x0000ffff); + pwords[addr_lo_position] |= static_cast(uint64_t{addr} & 0x0000ffff); } else if( getTargetArch() == Arch_aarch64 ) { const void *buf_tmp = NULL; @@ -827,15 +838,15 @@ bool mmap_alloc_process::plat_createDeallocationSnippet(Dyninst::Address addr, pthrd_printf("ARM-info: create de-alloc snippet...\n"); - BYTE_ASSGN(addr_pos, (uint16_t)(addr) ) - BYTE_ASSGN(addr_pos+4, (uint16_t)(addr>>16) ) - BYTE_ASSGN(addr_pos+8, (uint16_t)(addr>>32) ) - BYTE_ASSGN(addr_pos+12, (uint16_t)(addr>>48) ) + BYTE_ASSGN(addr_pos, static_cast(addr) ) + BYTE_ASSGN(addr_pos+4, static_cast(addr>>16) ) + BYTE_ASSGN(addr_pos+8, static_cast(addr>>32) ) + BYTE_ASSGN(addr_pos+12, static_cast(addr>>48) ) - BYTE_ASSGN(size_pos, (uint16_t)(size) ) - BYTE_ASSGN(size_pos+4, (uint16_t)(size>>16) ) - BYTE_ASSGN(size_pos+8, (uint16_t)(size>>32) ) - BYTE_ASSGN(size_pos+12, (uint16_t)(size>>48) ) + BYTE_ASSGN(size_pos, static_cast(size) ) + BYTE_ASSGN(size_pos+4, static_cast(size>>16) ) + BYTE_ASSGN(size_pos+8, static_cast(size>>32) ) + BYTE_ASSGN(size_pos+12, static_cast(size>>48) ) //swap 4bytes for(unsigned int i=0; i +#include +#include #include "int_process.h" /** diff --git a/proccontrol/src/ppc_process.C b/proccontrol/src/ppc_process.C index eed181180e..aa4600565a 100644 --- a/proccontrol/src/ppc_process.C +++ b/proccontrol/src/ppc_process.C @@ -28,10 +28,12 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include "ppc_process.h" #include "common/src/arch-power.h" #include #include +#include "unaligned_memory_access.h" using namespace NS_power; using namespace std; @@ -58,9 +60,8 @@ unsigned ppc_process::plat_breakpointSize() void ppc_process::plat_breakpointBytes(unsigned char *buffer) { - uint32_t *p = (uint32_t*)buffer; - - *p = 0x7d821008; // MJMTODO = Assumes host and target architecture match (and algnment) + write_memory_as(buffer, uint32_t{0x7d821008}); + // MJMTODO = Assumes host and target architecture match (and algnment) } bool ppc_process::plat_breakpointAdvancesPC() const diff --git a/proccontrol/src/ppc_process.h b/proccontrol/src/ppc_process.h index 8cb74f85f2..7e6136f054 100644 --- a/proccontrol/src/ppc_process.h +++ b/proccontrol/src/ppc_process.h @@ -31,6 +31,9 @@ #if !defined(ppc_process_h_) #define ppc_process_h_ +#include +#include +#include #include #include "int_process.h" diff --git a/proccontrol/src/proc_service_wrapper.h b/proccontrol/src/proc_service_wrapper.h index cb2ab646a4..1d70f2a88e 100644 --- a/proccontrol/src/proc_service_wrapper.h +++ b/proccontrol/src/proc_service_wrapper.h @@ -42,6 +42,7 @@ /* The definitions in this file must correspond to those in the debugger. */ +#include #include /* Functions in this interface return one of these status codes. */ diff --git a/proccontrol/src/process.C b/proccontrol/src/process.C index 4d50a2559b..96caf60f41 100644 --- a/proccontrol/src/process.C +++ b/proccontrol/src/process.C @@ -27,6 +27,7 @@ * License along with this library; if not, write to the Free Software * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include "dyninstversion.h" #include "int_process.h" #include "irpc.h" @@ -59,10 +60,6 @@ #include #include -#if defined(os_windows) -#pragma warning(disable:4355 4477) -#endif - using namespace Dyninst; using namespace ProcControlAPI; using namespace std; @@ -1937,8 +1934,10 @@ int int_process::getAddressWidth() case Arch_cuda: case Arch_intelGen9: return 8; - case Arch_amdgpu_vega: // according to the vega architecture, there are 32/64 address mode - case Arch_amdgpu_rdna: + case Arch_amdgpu_gfx908: + case Arch_amdgpu_gfx90a: + case Arch_amdgpu_gfx940: + return 8; case Arch_none: assert(0); } @@ -2300,11 +2299,11 @@ void int_process::updateSyncState(Event::ptr ev, bool gen) } case Event::sync_thread: { int_thread *thrd = ev->getThread()->llthrd(); - int_thread::StateTracker &st = gen ? thrd->getGeneratorState() : thrd->getHandlerState(); if (!thrd) { pthrd_printf("No thread for sync thread event, assuming thread exited\n"); return; } + int_thread::StateTracker &st = gen ? thrd->getGeneratorState() : thrd->getHandlerState(); int_thread::State old_state = st.getState(); if (old_state == int_thread::exited) { //Silly, linux. Giving us events on processes that have exited. @@ -4375,26 +4374,26 @@ bool int_thread::StateTracker::isDesynced() const { bool int_thread::StateTracker::setState(State to) { std::string s = int_thread::stateIDToName(id); - Dyninst::LWP lwp = up_thr->getLWP(); + Dyninst::LWP thisLwp = up_thr->getLWP(); Dyninst::PID pid = up_thr->llproc()->getPid(); if (state == to) { - pthrd_printf("Leaving %s state for %d/%d in state %s\n", s.c_str(), pid, lwp, stateStr(to)); + pthrd_printf("Leaving %s state for %d/%d in state %s\n", s.c_str(), pid, thisLwp, stateStr(to)); return true; } if (state == errorstate) { perr_printf("Attempted %s state reversion for %d/%d from errorstate to %s\n", - s.c_str(), pid, lwp, stateStr(to)); + s.c_str(), pid, thisLwp, stateStr(to)); return false; } if (state == exited && to != errorstate) { perr_printf("Attempted %s state reversion for %d/%d from exited to %s\n", - s.c_str(), pid, lwp, stateStr(to)); + s.c_str(), pid, thisLwp, stateStr(to)); return false; } if (to == neonatal && state != none) { perr_printf("Attempted %s state reversion for %d/%d from %s to neonatal\n", - s.c_str(), pid, lwp, stateStr(state)); + s.c_str(), pid, thisLwp, stateStr(state)); return false; } @@ -4442,7 +4441,7 @@ bool int_thread::StateTracker::setState(State to) up_thr->neonatalThreadCount().inc(); } } - pthrd_printf("Changing %s state for %d/%d from %s to %s\n", s.c_str(), pid, lwp, + pthrd_printf("Changing %s state for %d/%d from %s to %s\n", s.c_str(), pid, thisLwp, stateStr(state), stateStr(to)); state = to; @@ -5787,12 +5786,12 @@ RegisterPool::iterator RegisterPool::find(MachRegister r) return RegisterPool::iterator(llregpool->regs.find(r)); } -bool RegisterPool::iterator::operator==(const iterator &iter) +bool RegisterPool::iterator::operator==(const iterator &iter) const { return i == iter.i; } -bool RegisterPool::iterator::operator!=(const iterator &iter) +bool RegisterPool::iterator::operator!=(const iterator &iter) const { return i != iter.i; } @@ -5812,12 +5811,12 @@ RegisterPool::const_iterator RegisterPool::find(MachRegister r) const return RegisterPool::const_iterator(llregpool->regs.find(r)); } -bool RegisterPool::const_iterator::operator==(const const_iterator &iter) +bool RegisterPool::const_iterator::operator==(const const_iterator &iter) const { return i == iter.i; } -bool RegisterPool::const_iterator::operator!=(const const_iterator &iter) +bool RegisterPool::const_iterator::operator!=(const const_iterator &iter) const { return i != iter.i; } @@ -6047,13 +6046,13 @@ Library::const_ptr LibraryPool::getExecutable() const } LibraryPool::iterator LibraryPool::find(Library::ptr lib) { - LibraryPool::iterator i; + LibraryPool::iterator i{}; i.int_iter = proc->memory()->libs.find(lib->debug()); return i; } LibraryPool::const_iterator LibraryPool::find(Library::ptr lib) const { - LibraryPool::const_iterator i; + LibraryPool::const_iterator i{}; i.int_iter = proc->memory()->libs.find(lib->debug()); return i; } @@ -6082,14 +6081,14 @@ LibraryPool::iterator LibraryPool::iterator::operator++(int) // postfix LibraryPool::iterator LibraryPool::begin() { - LibraryPool::iterator i; + LibraryPool::iterator i{}; i.int_iter = proc->memory()->libs.begin(); return i; } LibraryPool::iterator LibraryPool::end() { - LibraryPool::iterator i; + LibraryPool::iterator i{}; i.int_iter = proc->memory()->libs.end(); return i; } @@ -6106,14 +6105,14 @@ bool LibraryPool::iterator::operator!=(const LibraryPool::iterator &i) const LibraryPool::const_iterator LibraryPool::begin() const { - LibraryPool::const_iterator i; + LibraryPool::const_iterator i{}; i.int_iter = proc->memory()->libs.begin(); return i; } LibraryPool::const_iterator LibraryPool::end() const { - LibraryPool::const_iterator i; + LibraryPool::const_iterator i{}; i.int_iter = proc->memory()->libs.end(); return i; } @@ -6127,12 +6126,12 @@ Library::const_ptr LibraryPool::const_iterator::operator*() const return (*int_iter)->up_lib; } -bool LibraryPool::const_iterator::operator==(const LibraryPool::const_iterator &i) +bool LibraryPool::const_iterator::operator==(const LibraryPool::const_iterator &i) const { return int_iter == i.int_iter; } -bool LibraryPool::const_iterator::operator!=(const LibraryPool::const_iterator &i) +bool LibraryPool::const_iterator::operator!=(const LibraryPool::const_iterator &i) const { return int_iter != i.int_iter; } @@ -7960,12 +7959,12 @@ ThreadPool::iterator::iterator() curh = Thread::ptr(); } -bool ThreadPool::iterator::operator==(const iterator &i) +bool ThreadPool::iterator::operator==(const iterator &i) const { return (i.curh == curh); } -bool ThreadPool::iterator::operator!=(const iterator &i) +bool ThreadPool::iterator::operator!=(const iterator &i) const { return (i.curh != curh); } @@ -8028,7 +8027,7 @@ ThreadPool::iterator ThreadPool::iterator::operator++(int) // postfix ThreadPool::iterator ThreadPool::begin() { MTLock lock_this_func; - ThreadPool::iterator i; + ThreadPool::iterator i{}; i.curp = threadpool; i.curi = 0; @@ -8043,7 +8042,7 @@ ThreadPool::iterator ThreadPool::begin() ThreadPool::iterator ThreadPool::end() { MTLock lock_this_func; - ThreadPool::iterator i; + ThreadPool::iterator i{}; i.curp = threadpool; i.curi = iterator::end_val; i.curh = Thread::ptr(); @@ -8053,7 +8052,7 @@ ThreadPool::iterator ThreadPool::end() ThreadPool::iterator ThreadPool::find(Dyninst::LWP lwp) { MTLock lock_this_func; - ThreadPool::iterator i; + ThreadPool::iterator i{}; int_thread *thread = threadpool->findThreadByLWP(lwp); if( !thread ) return end(); @@ -8071,12 +8070,12 @@ ThreadPool::const_iterator::const_iterator() curh = Thread::ptr(); } -bool ThreadPool::const_iterator::operator==(const const_iterator &i) +bool ThreadPool::const_iterator::operator==(const const_iterator &i) const { return (i.curh == curh); } -bool ThreadPool::const_iterator::operator!=(const const_iterator &i) +bool ThreadPool::const_iterator::operator!=(const const_iterator &i) const { return (i.curh != curh); } @@ -8139,7 +8138,7 @@ ThreadPool::const_iterator ThreadPool::const_iterator::operator++(int) // postfi ThreadPool::const_iterator ThreadPool::begin() const { MTLock lock_this_func; - ThreadPool::const_iterator i; + ThreadPool::const_iterator i{}; i.curp = threadpool; i.curi = 0; @@ -8160,7 +8159,7 @@ ThreadPool::const_iterator ThreadPool::begin() const ThreadPool::const_iterator ThreadPool::end() const { MTLock lock_this_func; - ThreadPool::const_iterator i; + ThreadPool::const_iterator i{}; i.curp = threadpool; i.curi = const_iterator::end_val; i.curh = Thread::ptr(); @@ -8170,7 +8169,7 @@ ThreadPool::const_iterator ThreadPool::end() const ThreadPool::const_iterator ThreadPool::find(Dyninst::LWP lwp) const { MTLock lock_this_func; - ThreadPool::const_iterator i; + ThreadPool::const_iterator i{}; int_thread *thread = threadpool->findThreadByLWP(lwp); if( !thread ) return end(); @@ -8271,6 +8270,13 @@ Breakpoint::ptr Breakpoint::newHardwareBreakpoint(unsigned int mode, return newbp; } +Breakpoint::ptr Breakpoint::newSynchronousBreakpoint() { + Breakpoint::ptr newbp = Breakpoint::ptr(new Breakpoint()); + newbp->llbreakpoint_ = new int_breakpoint(newbp); + newbp->llbreakpoint_->makeSynchronous(); + return newbp; +} + void *Breakpoint::getData() const { return llbreakpoint_->getData(); } @@ -8298,6 +8304,10 @@ bool Breakpoint::suppressCallbacks() const return llbreakpoint_->suppressCallbacks(); } +bool Breakpoint::isSynchronous() const { + return llbreakpoint_->isSynchronous(); +} + // Note: These locks are intentionally indirect and leaked! // This is because we can't guarantee destructor order between compilation // units, and a static array of locks here in process.C may be destroyed before diff --git a/proccontrol/src/processplat.C b/proccontrol/src/processplat.C index fd411ce9da..a8f7895038 100644 --- a/proccontrol/src/processplat.C +++ b/proccontrol/src/processplat.C @@ -35,10 +35,6 @@ #include "processplat.h" #include "int_event.h" -#ifdef _MSC_VER -#pragma warning(disable:4477) -#endif - using namespace Dyninst; using namespace ProcControlAPI; using namespace std; diff --git a/proccontrol/src/processplat.h b/proccontrol/src/processplat.h index a4958a3c0f..93f7605015 100644 --- a/proccontrol/src/processplat.h +++ b/proccontrol/src/processplat.h @@ -31,6 +31,12 @@ #if !defined(PROCESSPLAT_H_) #define PROCESSPLAT_H_ +#include +#include +#include +#include +#include +#include #include "int_process.h" #include "resp.h" diff --git a/proccontrol/src/procpool.C b/proccontrol/src/procpool.C index 920d27ae6a..31dbf3b4e7 100644 --- a/proccontrol/src/procpool.C +++ b/proccontrol/src/procpool.C @@ -27,6 +27,7 @@ * License along with this library; if not, write to the Free Software * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include "procpool.h" #include "int_process.h" #include "PCErrors.h" diff --git a/proccontrol/src/procset.C b/proccontrol/src/procset.C index b4b1b353d2..c3ae68c6be 100644 --- a/proccontrol/src/procset.C +++ b/proccontrol/src/procset.C @@ -40,21 +40,13 @@ #include "response.h" #include "processplat.h" #include "int_event.h" -#include "common/src/Types.h" #include #include #include -#if defined(os_windows) -#include "external/stdint-win.h" -#include "external/inttypes-win.h" -#endif -#include +#include #include -#ifdef _MSC_VER -#pragma warning(disable:4477) -#endif using namespace Dyninst; using namespace ProcControlAPI; @@ -517,6 +509,7 @@ static int_addressSet::iterator get_end(AddressSet::ptr as) { static void thread_err_check(int_thread *ithr, err_t *thread_error) { if (!ithr) { *thread_error = err_exited; + return; } if (ithr->getUserState().getState() == int_thread::running) { *thread_error = err_notrunning; @@ -1793,7 +1786,7 @@ struct bufferCompare { buffer = b; size = s; use_checksum = uc; - boost::crc_32_type crcComputer; + dyncompat::crc_32_type crcComputer; crcComputer.process_bytes(b, s); checksum = crcComputer.checksum(); } @@ -3049,12 +3042,12 @@ Thread::ptr ThreadSet::iterator::operator*() return *int_iter; } -bool ThreadSet::iterator::operator==(const iterator &i) +bool ThreadSet::iterator::operator==(const iterator &i) const { return int_iter == i.int_iter; } -bool ThreadSet::iterator::operator!=(const iterator &i) +bool ThreadSet::iterator::operator!=(const iterator &i) const { return int_iter != i.int_iter; } @@ -3087,12 +3080,12 @@ Thread::ptr ThreadSet::const_iterator::operator*() return *int_iter; } -bool ThreadSet::const_iterator::operator==(const const_iterator &i) +bool ThreadSet::const_iterator::operator==(const const_iterator &i) const { return int_iter == i.int_iter; } -bool ThreadSet::const_iterator::operator!=(const const_iterator &i) +bool ThreadSet::const_iterator::operator!=(const const_iterator &i) const { return int_iter != i.int_iter; } @@ -3350,8 +3343,7 @@ bool ThreadTrackingSet::refreshThreads() const for (int_processSet::iterator i = iter.begin(procset); i != iter.end(); i = iter.inc()) { int_threadTracking *proc = (*i)->llproc()->getThreadTracking(); if (!proc) { - perr_printf("Thread tracking not supported on process %d\n", proc->getPid()); - proc->setLastError(err_unsupported, "No thread tracking on this platform\n"); + perr_printf("Thread tracking not supported on process\n"); had_error = true; continue; } @@ -3409,8 +3401,7 @@ bool LWPTrackingSet::refreshLWPs() const for (int_processSet::iterator i = iter.begin(procset); i != iter.end(); i = iter.inc()) { int_LWPTracking *proc = (*i)->llproc()->getLWPTracking(); if (!proc) { - perr_printf("LWP tracking not supported on process %d\n", proc->getPid()); - proc->setLastError(err_unsupported, "No LWP tracking on this platform\n"); + perr_printf("LWP tracking not supported on process\n"); had_error = true; continue; } @@ -3486,8 +3477,7 @@ bool FollowForkSet::setFollowFork(FollowFork::follow_t f) const for (int_processSet::iterator i = iter.begin(procset); i != iter.end(); i = iter.inc()) { int_followFork *proc = (*i)->llproc()->getFollowFork(); if (!proc) { - perr_printf("Follow Fork not supported on process %d\n", proc->getPid()); - proc->setLastError(err_unsupported, "No follow fork control on this platform\n"); + perr_printf("Follow Fork not supported on process\n"); had_error = true; continue; } @@ -3615,8 +3605,7 @@ bool RemoteIOSet::getFileNames(FileSet *fset) for (int_processSet::iterator i = iter.begin(procset); i != iter.end(); i = iter.inc()) { int_remoteIO *proc = (*i)->llproc()->getRemoteIO(); if (!proc) { - perr_printf("getFileNames attempted on non RemoteIO process %d\n", proc->getPid()); - proc->setLastError(err_unsupported, "getFileNames not supported on this platform"); + perr_printf("getFileNames attempted on non RemoteIO process\n"); had_error = true; continue; } @@ -3670,8 +3659,7 @@ bool RemoteIOSet::getFileStatData(FileSet *fset) fflush(stderr); int_remoteIO *proc = i->first->llproc()->getRemoteIO(); if (!proc) { - perr_printf("getFileStatData attempted on non RemoteIO process %d\n", proc->getPid()); - proc->setLastError(err_unsupported, "getFileStatData not supported on this platform"); + perr_printf("getFileStatData attempted on non RemoteIO process\n"); had_error = true; continue; } @@ -3717,8 +3705,7 @@ bool RemoteIOSet::readFileContents(const FileSet *fset) for (FileSet::const_iterator i = fset->begin(); i != fset->end(); i++) { int_remoteIO *proc = i->first->llproc()->getRemoteIO(); if (!proc) { - perr_printf("getFileStatData attempted on non RemoteIO process %d\n", proc->getPid()); - proc->setLastError(err_unsupported, "getFileStatData not supported on this platform"); + perr_printf("getFileStatData attempted on non RemoteIO\n"); had_error = true; continue; } @@ -3789,8 +3776,7 @@ bool MemoryUsageSet::usedX(std::map &used, Me for (int_processSet::iterator i = iter.begin(procset); i != iter.end(); i = iter.inc()) { int_memUsage *proc = (*i)->llproc()->getMemUsage(); if (!proc) { - perr_printf("GetMemUsage not supported on process %d\n", proc->getPid()); - proc->setLastError(err_unsupported, "No getMemUsage on this platform\n"); + perr_printf("GetMemUsage not supported\n"); had_error = true; continue; } diff --git a/proccontrol/src/resp.C b/proccontrol/src/resp.C index c0e9e28e87..26a3647976 100644 --- a/proccontrol/src/resp.C +++ b/proccontrol/src/resp.C @@ -28,6 +28,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include #include "response.h" #include "resp.h" diff --git a/proccontrol/src/resp.h b/proccontrol/src/resp.h index ff17f15558..7638d1f1a7 100644 --- a/proccontrol/src/resp.h +++ b/proccontrol/src/resp.h @@ -35,6 +35,7 @@ #include "int_process.h" #include #include +#include /** * The Resp class is a second implementation of the response diff --git a/proccontrol/src/response.C b/proccontrol/src/response.C index b95446c30f..2ac37e977e 100644 --- a/proccontrol/src/response.C +++ b/proccontrol/src/response.C @@ -28,6 +28,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include "Event.h" #include "response.h" @@ -240,42 +241,42 @@ void response::setProcess(int_process *p) result_response::ptr response::getResultResponse() { return resp_type == rt_result ? - boost::static_pointer_cast(shared_from_this()) : + dyncompat::static_pointer_cast(shared_from_this()) : result_response::ptr(); } mem_response::ptr response::getMemResponse() { return resp_type == rt_mem ? - boost::static_pointer_cast(shared_from_this()) : + dyncompat::static_pointer_cast(shared_from_this()) : mem_response::ptr(); } reg_response::ptr response::getRegResponse() { return resp_type == rt_reg ? - boost::static_pointer_cast(shared_from_this()) : + dyncompat::static_pointer_cast(shared_from_this()) : reg_response::ptr(); } allreg_response::ptr response::getAllRegResponse() { return resp_type == rt_allreg ? - boost::static_pointer_cast(shared_from_this()) : + dyncompat::static_pointer_cast(shared_from_this()) : allreg_response::ptr(); } stack_response::ptr response::getStackResponse() { return resp_type == rt_stack ? - boost::static_pointer_cast(shared_from_this()) : + dyncompat::static_pointer_cast(shared_from_this()) : stack_response::ptr(); } data_response::ptr response::getDataResponse() { return resp_type == rt_data ? - boost::static_pointer_cast(shared_from_this()) : + dyncompat::static_pointer_cast(shared_from_this()) : data_response::ptr(); } diff --git a/proccontrol/src/response.h b/proccontrol/src/response.h index 18443aa827..4d0aa140b0 100644 --- a/proccontrol/src/response.h +++ b/proccontrol/src/response.h @@ -33,6 +33,7 @@ #include "Event.h" #include "common/src/dthread.h" +#include #include #include @@ -47,9 +48,9 @@ class stack_response; class data_response; class HandlerPool; -class response : public boost::enable_shared_from_this { - friend void boost::checked_delete(response *) CHECKED_DELETE_NOEXCEPT; - friend void boost::checked_delete(const response *) CHECKED_DELETE_NOEXCEPT; +class response : public dyncompat::enable_shared_from_this { + friend void dyncompat::checked_delete(response *) noexcept; + friend void dyncompat::checked_delete(const response *) noexcept; friend class responses_pending; friend unsigned newResponseID(); friend unsigned newResponseID(unsigned); @@ -92,19 +93,19 @@ class response : public boost::enable_shared_from_this { int multi_resp_recvd; public: - typedef boost::shared_ptr ptr; - typedef boost::shared_ptr const_ptr; + typedef dyncompat::shared_ptr ptr; + typedef dyncompat::shared_ptr const_ptr; virtual ~response(); unsigned int getID() const; - boost::shared_ptr getResultResponse(); - boost::shared_ptr getMemResponse(); - boost::shared_ptr getRegResponse(); - boost::shared_ptr getAllRegResponse(); - boost::shared_ptr getStackResponse(); - boost::shared_ptr getDataResponse(); + dyncompat::shared_ptr getResultResponse(); + dyncompat::shared_ptr getMemResponse(); + dyncompat::shared_ptr getRegResponse(); + dyncompat::shared_ptr getAllRegResponse(); + dyncompat::shared_ptr getStackResponse(); + dyncompat::shared_ptr getDataResponse(); bool isReady() const; bool testReady() const; @@ -162,15 +163,15 @@ class result_response : public response { friend class linux_process; friend class linux_thread; - friend void boost::checked_delete(result_response *) CHECKED_DELETE_NOEXCEPT; - friend void boost::checked_delete(const result_response *) CHECKED_DELETE_NOEXCEPT; + friend void dyncompat::checked_delete(result_response *) noexcept; + friend void dyncompat::checked_delete(const result_response *) noexcept; private: bool b; result_response(); public: - typedef boost::shared_ptr ptr; - typedef boost::shared_ptr const_ptr; + typedef dyncompat::shared_ptr ptr; + typedef dyncompat::shared_ptr const_ptr; static result_response::ptr createResultResponse(); @@ -185,8 +186,8 @@ class result_response : public response class reg_response : public response { friend class linux_thread; - friend void boost::checked_delete(reg_response *) CHECKED_DELETE_NOEXCEPT; - friend void boost::checked_delete(const reg_response *) CHECKED_DELETE_NOEXCEPT; + friend void dyncompat::checked_delete(reg_response *) noexcept; + friend void dyncompat::checked_delete(const reg_response *) noexcept; private: Dyninst::MachRegisterVal val; reg_response(); @@ -195,8 +196,8 @@ class reg_response : public response int_thread *thr; public: - typedef boost::shared_ptr ptr; - typedef boost::shared_ptr const_ptr; + typedef dyncompat::shared_ptr ptr; + typedef dyncompat::shared_ptr const_ptr; static reg_response::ptr createRegResponse(); @@ -210,8 +211,8 @@ class reg_response : public response class allreg_response : public response { - friend void boost::checked_delete(allreg_response *) CHECKED_DELETE_NOEXCEPT; - friend void boost::checked_delete(const allreg_response *) CHECKED_DELETE_NOEXCEPT; + friend void dyncompat::checked_delete(allreg_response *) noexcept; + friend void dyncompat::checked_delete(const allreg_response *) noexcept; private: int_registerPool *regpool; int_thread *thr; @@ -220,8 +221,8 @@ class allreg_response : public response allreg_response(); public: - typedef boost::shared_ptr ptr; - typedef boost::shared_ptr const_ptr; + typedef dyncompat::shared_ptr ptr; + typedef dyncompat::shared_ptr const_ptr; static allreg_response::ptr createAllRegResponse(int_registerPool *regpool); static allreg_response::ptr createAllRegResponse(); @@ -242,8 +243,8 @@ class allreg_response : public response class mem_response : public response { - friend void boost::checked_delete(mem_response *) CHECKED_DELETE_NOEXCEPT; - friend void boost::checked_delete(const mem_response *) CHECKED_DELETE_NOEXCEPT; + friend void dyncompat::checked_delete(mem_response *) noexcept; + friend void dyncompat::checked_delete(const mem_response *) noexcept; private: char *buffer; unsigned size; @@ -253,8 +254,8 @@ class mem_response : public response mem_response(char *targ, unsigned targ_size); public: - typedef boost::shared_ptr ptr; - typedef boost::shared_ptr const_ptr; + typedef dyncompat::shared_ptr ptr; + typedef dyncompat::shared_ptr const_ptr; static mem_response::ptr createMemResponse(); static mem_response::ptr createMemResponse(char *targ, unsigned targ_size); @@ -275,16 +276,16 @@ class mem_response : public response class stack_response : public response { - friend void boost::checked_delete(stack_response *) CHECKED_DELETE_NOEXCEPT; - friend void boost::checked_delete(const stack_response *) CHECKED_DELETE_NOEXCEPT; + friend void dyncompat::checked_delete(stack_response *) noexcept; + friend void dyncompat::checked_delete(const stack_response *) noexcept; private: void *data; int_thread *thr; stack_response(int_thread *t); public: - typedef boost::shared_ptr ptr; - typedef boost::shared_ptr const_ptr; + typedef dyncompat::shared_ptr ptr; + typedef dyncompat::shared_ptr const_ptr; static stack_response::ptr createStackResponse(int_thread *t); @@ -297,14 +298,14 @@ class stack_response : public response class data_response : public response { - friend void boost::checked_delete(data_response *) CHECKED_DELETE_NOEXCEPT; - friend void boost::checked_delete(const data_response *) CHECKED_DELETE_NOEXCEPT; + friend void dyncompat::checked_delete(data_response *) noexcept; + friend void dyncompat::checked_delete(const data_response *) noexcept; private: void *data; data_response(); public: - typedef boost::shared_ptr ptr; - typedef boost::shared_ptr const_ptr; + typedef dyncompat::shared_ptr ptr; + typedef dyncompat::shared_ptr const_ptr; static data_response::ptr createDataResponse(); diff --git a/proccontrol/src/sysv.C b/proccontrol/src/sysv.C index 314774e868..53d94b247d 100644 --- a/proccontrol/src/sysv.C +++ b/proccontrol/src/sysv.C @@ -30,7 +30,6 @@ #include "common/h/SymReader.h" #include "common/h/dyntypes.h" -#include "common/src/Types.h" #if defined(os_linux) #include "common/src/linuxKludges.h" #elif defined(os_freebsd) diff --git a/proccontrol/src/sysv.h b/proccontrol/src/sysv.h index b5ef13c1b9..b66277903b 100644 --- a/proccontrol/src/sysv.h +++ b/proccontrol/src/sysv.h @@ -31,6 +31,10 @@ #if !defined(SYSV_H_) #define SYSV_H_ +#include +#include +#include +#include #include "common/h/ProcReader.h" #include "int_process.h" #include "processplat.h" diff --git a/proccontrol/src/unix.C b/proccontrol/src/unix.C index 907d7aafde..26b0f1c057 100644 --- a/proccontrol/src/unix.C +++ b/proccontrol/src/unix.C @@ -40,7 +40,7 @@ #include #include -#include "common/src/Types.h" +#include "common/src/vm_maps.h" #if defined(os_linux) #include "common/src/linuxKludges.h" #elif defined(os_freebsd) diff --git a/proccontrol/src/unix.h b/proccontrol/src/unix.h index 3fffed72b7..f9cda69855 100644 --- a/proccontrol/src/unix.h +++ b/proccontrol/src/unix.h @@ -31,6 +31,10 @@ #if !defined(UNIX_H_) #define UNIX_H_ +#include +#include +#include +#include #include "int_process.h" /** diff --git a/proccontrol/src/windows_handler.C b/proccontrol/src/windows_handler.C index cc35169bef..5df6b546e7 100644 --- a/proccontrol/src/windows_handler.C +++ b/proccontrol/src/windows_handler.C @@ -33,7 +33,6 @@ #include -#include "common/h/dyn_regs.h" #include "common/h/dyntypes.h" #include "symtabAPI/h/Symtab.h" #include "common/src/pathName.h" @@ -140,7 +139,7 @@ Handler::handler_ret_t WindowsHandleNewThr::handleEvent(Event::ptr ev) ProcPool()->condvar()->unlock(); assert(thr); - WinEventNewThread::ptr we = boost::dynamic_pointer_cast(ev); + WinEventNewThread::ptr we = dyncompat::dynamic_pointer_cast(ev); if(we) { pthrd_printf("WinHandleCreateThread handling thread creation for thread %d, handle %x\n", @@ -339,7 +338,7 @@ Handler::handler_ret_t WindowsHandleSetThreadInfo::handleEvent( Event::ptr ev ) { windows_thread *thr = static_cast(ev->getThread()->llthrd()); - WinEventThreadInfo::ptr we = boost::dynamic_pointer_cast(ev); + WinEventThreadInfo::ptr we = dyncompat::dynamic_pointer_cast(ev); if(we) { ProcPool()->rmThread(thr); diff --git a/proccontrol/src/windows_handler.h b/proccontrol/src/windows_handler.h index 149a88367a..e07fb07363 100644 --- a/proccontrol/src/windows_handler.h +++ b/proccontrol/src/windows_handler.h @@ -64,11 +64,11 @@ class ArchEventWindows : public ArchEvent class PC_EXPORT WinEventNewThread : public EventNewLWP { - friend void boost::checked_delete(WinEventNewThread *) CHECKED_DELETE_NOEXCEPT; - friend void boost::checked_delete(const WinEventNewThread *) CHECKED_DELETE_NOEXCEPT; + friend void dyncompat::checked_delete(WinEventNewThread *) noexcept; + friend void dyncompat::checked_delete(const WinEventNewThread *) noexcept; public: - typedef boost::shared_ptr ptr; - typedef boost::shared_ptr const_ptr; + typedef dyncompat::shared_ptr ptr; + typedef dyncompat::shared_ptr const_ptr; WinEventNewThread(Dyninst::LWP l, HANDLE ht, LPTHREAD_START_ROUTINE ts, LPVOID base) : EventNewLWP(l, (int) int_thread::as_created_attached), hthread(ht), thread_start(ts), tls_base(base) @@ -86,11 +86,11 @@ class PC_EXPORT WinEventNewThread : public EventNewLWP class PC_EXPORT WinEventThreadInfo : public Event { - friend void boost::checked_delete(WinEventThreadInfo *) CHECKED_DELETE_NOEXCEPT; - friend void boost::checked_delete(const WinEventThreadInfo *) CHECKED_DELETE_NOEXCEPT; + friend void dyncompat::checked_delete(WinEventThreadInfo *) noexcept; + friend void dyncompat::checked_delete(const WinEventThreadInfo *) noexcept; public: - typedef boost::shared_ptr ptr; - typedef boost::shared_ptr const_ptr; + typedef dyncompat::shared_ptr ptr; + typedef dyncompat::shared_ptr const_ptr; WinEventThreadInfo(Dyninst::LWP l, HANDLE ht, LPTHREAD_START_ROUTINE ts, LPVOID base) : Event(EventType(EventType::None, EventType::ThreadInfo)), hthread(ht), thread_start(ts), tls_base(base), lwp(l) diff --git a/proccontrol/src/windows_process.C b/proccontrol/src/windows_process.C index 02bfef9a86..29cdd392f7 100644 --- a/proccontrol/src/windows_process.C +++ b/proccontrol/src/windows_process.C @@ -27,6 +27,7 @@ * License along with this library; if not, write to the Free Software * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include "windows_process.h" #include "int_process.h" #include "GeneratorWindows.h" @@ -400,7 +401,7 @@ bool windows_process::plat_readMem(int_thread *thr, void *local, if(!::ReadProcessMemory(hproc, (unsigned char*)remote, (unsigned char*)local, size, NULL)) { errcode = ::GetLastError(); - pthrd_printf("ReadProcessMemory() failed to get %d bytes from 0x%x, error %d\n", + pthrd_printf("ReadProcessMemory() failed to get %zu bytes from 0x%lx, error %d\n", size, remote, errcode); return false; } @@ -544,7 +545,7 @@ Dyninst::Address windows_process::plat_mallocExecMemory(Dyninst::Address min, un { Dyninst::Address alloc_result = (Dyninst::Address)::VirtualAllocEx(hproc, (LPVOID)min, size, MEM_COMMIT, PAGE_EXECUTE_READWRITE); if(alloc_result == 0) { - pthrd_printf("mallocExecMemory failed to VirtualAllocEx %d bytes, error code %d\n", size, ::GetLastError()); + pthrd_printf("mallocExecMemory failed to VirtualAllocEx %u bytes, error code %d\n", size, ::GetLastError()); } return alloc_result; } @@ -597,8 +598,8 @@ Dyninst::Address windows_process::direct_infMalloc(unsigned long size, bool use_ Dyninst::Address result = (Dyninst::Address)(::VirtualAllocEx(hproc, (LPVOID)addr, size, MEM_RESERVE | MEM_COMMIT, PAGE_EXECUTE_READWRITE)); if(result == 0) { - pthrd_printf("infMalloc failed to VirtualAllocEx %d bytes, error code %d\n", size, ::GetLastError()); - fprintf(stderr, "infMalloc failed to VirtualAllocEx %d bytes, error code %d\n", size, ::GetLastError()); + pthrd_printf("infMalloc failed to VirtualAllocEx %u bytes, error code %d\n", size, ::GetLastError()); + fprintf(stderr, "infMalloc failed to VirtualAllocEx %u bytes, error code %d\n", size, ::GetLastError()); MEMORY_BASIC_INFORMATION info; memset(&info, 0, sizeof(MEMORY_BASIC_INFORMATION)); VirtualQueryEx(hproc, (LPCVOID) (Address) addr, @@ -745,7 +746,7 @@ void windows_process::findSystemLibs() { } int_thread *windows_process::RPCThread() { - pthrd_printf("Query for RPC thread: ret 0x%lx\n", + pthrd_printf("Query for RPC thread: ret %p\n", dummyRPCThread_); return dummyRPCThread_; } @@ -754,7 +755,7 @@ int_thread *windows_process::createRPCThread(int_thread* best_candidate) { if(best_candidate) return best_candidate; if (!dummyRPCThread_) { dummyRPCThread_ = static_cast(int_thread::createRPCThread(this)); - pthrd_printf("Creating RPC thread: 0x%lx\n", dummyRPCThread_); + pthrd_printf("Creating RPC thread: %p\n", dummyRPCThread_); } else { pthrd_printf("Create RPC thread returning previous copy\n"); @@ -769,7 +770,7 @@ void windows_process::instantiateRPCThread() { if (!dummyRPCThread_->isRPCpreCreate()) return; - pthrd_printf("Promoting dummy RPC thread 0x%lx to a real thread\n", dummyRPCThread_); + pthrd_printf("Promoting dummy RPC thread %p to a real thread\n", dummyRPCThread_); // We want to: // 1) Take the dummy thread diff --git a/proccontrol/src/windows_process.h b/proccontrol/src/windows_process.h index 6a46144415..faa4777896 100644 --- a/proccontrol/src/windows_process.h +++ b/proccontrol/src/windows_process.h @@ -31,12 +31,17 @@ #if !defined(WINDOWS_PROCESS_H) #define WINDOWS_PROCESS_H +#include +#include +#include +#include +#include +#include #include "x86_process.h" #include "common/src/IntervalTree.h" class windows_thread; -#pragma warning (disable: 4250) class windows_process : virtual public x86_process, virtual public hybrid_lwp_control_process { public: diff --git a/proccontrol/src/windows_thread.h b/proccontrol/src/windows_thread.h index 42d903bc51..21238dbe95 100644 --- a/proccontrol/src/windows_thread.h +++ b/proccontrol/src/windows_thread.h @@ -30,6 +30,8 @@ #if !defined(WINDOWS_THREAD_H) #define WINDOWS_THREAD_H +#include +#include #include "int_process.h" #if !defined(TF_BIT) diff --git a/proccontrol/src/x86_process.C b/proccontrol/src/x86_process.C index bcf4a73e3e..fc47a62966 100644 --- a/proccontrol/src/x86_process.C +++ b/proccontrol/src/x86_process.C @@ -31,10 +31,8 @@ #include "x86_process.h" #include "int_event.h" #include "Event.h" - -#ifdef _MSC_VER -#pragma warning(disable:4477) -#endif +#include "registers/x86_regs.h" +#include "registers/x86_64_regs.h" x86_process::x86_process(Dyninst::PID p, std::string e, std::vector a, std::vector envp, std::map f) : int_process(p, e, a, envp, f) @@ -234,7 +232,7 @@ bool x86_thread::addHWBreakpoint(hw_breakpoint *bp, //Set bits 18-19, 22-23, 26-27, or 30-31 to size offset = cur*4+18; - new_dr7 &= ~((unsigned long) (3 << offset)); + new_dr7 &= ~((unsigned long) (3U << offset)); new_dr7 |= size_code << offset; //Set bit 8 to on (exact match required) diff --git a/proccontrol/src/x86_process.h b/proccontrol/src/x86_process.h index f69d814a3a..cdb61ed987 100644 --- a/proccontrol/src/x86_process.h +++ b/proccontrol/src/x86_process.h @@ -32,8 +32,13 @@ #if !defined(x86_process_h_) #define x86_process_h_ +#include +#include +#include +#include +#include #include "int_process.h" -#include "common/h/dyn_regs.h" +#include "registers/MachRegister.h" class x86_process : virtual public int_process { diff --git a/scripts/dynsysname b/scripts/dynsysname deleted file mode 100755 index dc6692a81a..0000000000 --- a/scripts/dynsysname +++ /dev/null @@ -1,75 +0,0 @@ -#!/bin/bash - -P=$1 - -# i386/Linux, x86-64/Linux, ppc/Linux, ppc64/Linux -if [ ${P/linux/} != ${P} ]; then -if [ ${P/i686/} != ${P} ]; then -PLATFORM=i386-unknown-linux2.4 -fi -if [ ${P/i586/} != ${P} ]; then -PLATFORM=i386-unknown-linux2.4 -fi -if [ ${P/i486/} != ${P} ]; then -PLATFORM=i386-unknown-linux2.4 -fi -if [ ${P/i386/} != ${P} ]; then -PLATFORM=i386-unknown-linux2.4 -fi -if [ ${P/x86_64/} != ${P} ]; then -PLATFORM=x86_64-unknown-linux2.4 -fi -if [ ${P/ppc64/} != ${P} ]; then -PLATFORM=ppc64_linux -fi -if [ ${P/powerpc64/} != ${P} ]; then -PLATFORM=ppc64_linux -fi -if [ ${P/powerpc-/} != ${P} ]; then -PLATFORM=ppc32_linux -fi -if [ ${P/ppc-/} != ${P} ]; then -PLATFORM=ppc32_linux -fi -if [ ${P/aarch64-/} != ${P} ]; then -PLATFORM=aarch64-unknown-linux -fi -# Freebsd -elif [ ${P/freebsd/} != ${P} ]; then -if [ ${P/i686/} != ${P} ]; then -PLATFORM=i386-unknown-freebsd7.2 -fi -if [ ${P/i586/} != ${P} ]; then -PLATFORM=i386-unknown-freebsd7.2 -fi -if [ ${P/i486/} != ${P} ]; then -PLATFORM=i386-unknown-freebsd7.2 -fi -if [ ${P/i386/} != ${P} ]; then -PLATFORM=i386-unknown-freebsd7.2 -fi -if [ ${P/x86_64/} != ${P} ]; then -PLATFORM=amd64-unknown-freebsd7.2 -fi - - -# VxWorks -elif [ ${P/vxworks/} != ${P} ]; then -if [ ${P/i686/} != ${P} ]; then -PLATFORM=i386-unknown-vxworks6.x -fi -if [ ${P/i586/} != ${P} ]; then -PLATFORM=i386-unknown-vxworks6.x -fi -if [ ${P/i486/} != ${P} ]; then -PLATFORM=i386-unknown-vxworks6.x -fi -if [ ${P/i386/} != ${P} ]; then -PLATFORM=i386-unknown-vxworks6.x -fi -if [ ${P/powerpc-/} != ${P} ]; then -PLATFORM=ppc32-unknown-vxworks6.x -fi -fi - -echo $PLATFORM diff --git a/scripts/sysname b/scripts/sysname deleted file mode 100755 index 16f5404834..0000000000 --- a/scripts/sysname +++ /dev/null @@ -1,586 +0,0 @@ -#!/bin/bash -# $Id: sysname,v 1.6 2005/08/09 16:13:16 gquinn Exp $ -# Attempt to guess a canonical system name. -# Copyright (C) 1992, 1993, 1994, 1995 Free Software Foundation, Inc. -# -# This file is free software; you can redistribute it and/or modify it -# under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, but -# WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -# General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. -# -# As a special exception to the GNU General Public License, if you -# distribute this file as part of a program that contains a -# configuration script generated by Autoconf, you may include it under -# the same distribution terms that you use for the rest of that program. - -# Written by Per Bothner . -# The master version of this file is at the FSF in /home/gd/gnu/lib. -# -# This script attempts to guess a canonical system name similar to -# config.sub. If it succeeds, it prints the system name on stdout, and -# exits with 0. Otherwise, it exits with 1. -# -# The plan is that this can be called by configure scripts if you -# don't specify an explicit system type (host/target name). -# -# Only a few systems have been added to this list; please add others -# (but try to keep the structure clean). -# - -# This is needed to find uname on a Pyramid OSx when run in the BSD universe. -# (ghazi@noc.rutgers.edu 8/24/94.) -if (test -f /.attbin/uname) >/dev/null 2>&1 ; then - PATH=$PATH:/.attbin ; export PATH -fi - -UNAME_MACHINE=`(uname -m) 2>/dev/null` || UNAME_MACHINE=unknown -UNAME_RELEASE=`(uname -r) 2>/dev/null` || UNAME_RELEASE=unknown -UNAME_SYSTEM=`(uname -s) 2>/dev/null` || UNAME_SYSTEM=unknown -UNAME_VERSION=`(uname -v) 2>/dev/null` || UNAME_VERSION=unknown - -trap 'rm -f dummy.c dummy.o dummy; exit 1' 1 2 15 - -# Note: order is significant - the case branches are not exclusive. - -case "${UNAME_MACHINE}:${UNAME_SYSTEM}:${UNAME_RELEASE}:${UNAME_VERSION}" in - alpha:OSF1:V*:*) - # After 1.2, OSF1 uses "V1.3" for uname -r. - echo alpha-dec-osf`echo ${UNAME_RELEASE} | sed -e 's/^V//'` - exit 0 ;; - alpha:OSF1:*:*) - # 1.2 uses "1.2" for uname -r. - echo alpha-dec-osf${UNAME_RELEASE} - exit 0 ;; - 21064:Windows_NT:50:3) - echo alpha-dec-winnt3.5 - exit 0 ;; - amiga:NetBSD:*:*) - echo m68k-cbm-netbsd${UNAME_RELEASE} - exit 0 ;; - arm:RISC*:1.[012]*:*|arm:riscix:1.[012]*:*) - echo arm-acorn-riscix${UNAME_RELEASE} - exit 0;; - Pyramid*:OSx*:*:*) - if test "`(/bin/universe) 2>/dev/null`" = att ; then - echo pyramid-pyramid-sysv3 - else - echo pyramid-pyramid-bsd - fi - exit 0 ;; - sun4*:SunOS:5.*:*) - echo sparc-sun-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'` - exit 0 ;; - i86pc:SunOS:5.*:*) - echo i386-unknown-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'` - exit 0 ;; - sun4*:SunOS:6*:*) - # According to config.sub, this is the proper way to canonicalize - # SunOS6. Hard to guess exactly what SunOS6 will be like, but - # it's likely to be more like Solaris than SunOS4. - echo sparc-sun-solaris3`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'` - exit 0 ;; - sun4*:SunOS:*:*) - case "`/usr/bin/arch -k`" in - Series*|S4*) - UNAME_RELEASE=`uname -v` - ;; - esac - # Japanese Language versions have a version number like `4.1.3-JL'. - echo sparc-sun-sunos`echo ${UNAME_RELEASE}|sed -e 's/-/_/'` - exit 0 ;; - sun3*:SunOS:*:*) - echo m68k-sun-sunos${UNAME_RELEASE} - exit 0 ;; - atari*:NetBSD:*:*) - echo m68k-atari-netbsd${UNAME_RELEASE} - exit 0 ;; - sun3*:NetBSD:*:*) - echo m68k-sun-netbsd${UNAME_RELEASE} - exit 0 ;; - mac68k:NetBSD:*:*) - echo m68k-apple-netbsd${UNAME_RELEASE} - exit 0 ;; - RISC*:ULTRIX:*:*) - echo mips-dec-ultrix${UNAME_RELEASE} - exit 0 ;; - VAX*:ULTRIX*:*:*) - echo vax-dec-ultrix${UNAME_RELEASE} - exit 0 ;; - mips:*:4*:UMIPS) - echo mips-mips-riscos4sysv - exit 0 ;; - mips:*:5*:RISCos) - echo mips-mips-riscos${UNAME_RELEASE} - exit 0 ;; - m88k:CX/UX:7*:*) - echo m88k-harris-cxux7 - exit 0 ;; - m88k:*:4*:R4*) - echo m88k-motorola-sysv4 - exit 0 ;; - m88k:*:3*:R3*) - echo m88k-motorola-sysv3 - exit 0 ;; - AViiON:dgux:*:*) - if [ ${TARGET_BINARY_INTERFACE}x = m88kdguxelfx \ - -o ${TARGET_BINARY_INTERFACE}x = x ] ; then - echo m88k-dg-dgux${UNAME_RELEASE} - else - echo m88k-dg-dguxbcs${UNAME_RELEASE} - fi - exit 0 ;; - M88*:DolphinOS:*:*) # DolphinOS (SVR3) - echo m88k-dolphin-sysv3 - exit 0 ;; - M88*:*:R3*:*) - # Delta 88k system running SVR3 - echo m88k-motorola-sysv3 - exit 0 ;; - XD88*:*:*:*) # Tektronix XD88 system running UTekV (SVR3) - echo m88k-tektronix-sysv3 - exit 0 ;; - Tek43[0-9][0-9]:UTek:*:*) # Tektronix 4300 system running UTek (BSD) - echo m68k-tektronix-bsd - exit 0 ;; - *:IRIX*:*:*) - echo mips-sgi-irix`echo ${UNAME_RELEASE}|sed -e 's/-/_/g'` - exit 0 ;; - ????????:AIX?:[12].1:2) # AIX 2.2.1 or AIX 2.1.1 is RT/PC AIX. - echo romp-ibm-aix # uname -m gives an 8 hex-code CPU id - exit 0 ;; # Note that: echo "'`uname -s`'" gives 'AIX ' - i[34]86:AIX:*:*) - echo i386-ibm-aix - exit 0 ;; - *:AIX:2:3) - if grep bos325 /usr/include/stdio.h >/dev/null 2>&1; then - sed 's/^ //' << EOF >dummy.c - #include - - main() - { - if (!__power_pc()) - exit(1); - puts("powerpc-ibm-aix3.2.5"); - exit(0); - } -EOF - ${CC-cc} dummy.c -o dummy && ./dummy && rm dummy.c dummy && exit 0 - rm -f dummy.c dummy - echo rs6000-ibm-aix3.2.5 - elif grep bos324 /usr/include/stdio.h >/dev/null 2>&1; then - echo rs6000-ibm-aix3.2.4 - else - echo rs6000-ibm-aix3.2 - fi - exit 0 ;; - *:AIX:*:4) - if /usr/sbin/lsattr -EHl proc0 | grep POWER >/dev/null 2>&1; then - IBM_ARCH=rs6000 - else - IBM_ARCH=powerpc - fi - if [ -x /usr/bin/oslevel ] ; then - IBM_REV=`/usr/bin/oslevel` - else - IBM_REV=4.${UNAME_RELEASE} - fi - echo ${IBM_ARCH}-ibm-aix${IBM_REV} - exit 0 ;; - *:AIX:*:5) - if /usr/sbin/lsattr -EHl proc0 | grep POWER >/dev/null 2>&1; then - IBM_ARCH=rs6000 - else - IBM_ARCH=powerpc - fi - if [ -x /usr/bin/oslevel ] ; then - IBM_REV=`/usr/bin/oslevel` - else - IBM_REV=5.${UNAME_RELEASE} - fi - echo ${IBM_ARCH}-ibm-aix${IBM_REV} - exit 0 ;; - *:AIX:*:*) - echo rs6000-ibm-aix - exit 0 ;; - ibmrt:4.4BSD:*|romp-ibm:BSD:*) - echo romp-ibm-bsd4.4 - exit 0 ;; - ibmrt:*BSD:*|romp-ibm:BSD:*) # covers RT/PC NetBSD and - echo romp-ibm-bsd${UNAME_RELEASE} # 4.3 with uname added to - exit 0 ;; # report: romp-ibm BSD 4.3 - *:BOSX:*:*) - echo rs6000-bull-bosx - exit 0 ;; - DPX/2?00:B.O.S.:*:*) - echo m68k-bull-sysv3 - exit 0 ;; - 9000/[34]??:4.3bsd:1.*:*) - echo m68k-hp-bsd - exit 0 ;; - hp300:4.4BSD:*:* | 9000/[34]??:4.3bsd:2.*:*) - echo m68k-hp-bsd4.4 - exit 0 ;; - 9000/[3478]??:HP-UX:*:*) - case "${UNAME_MACHINE}" in - 9000/31? ) HP_ARCH=m68000 ;; - 9000/[34]?? ) HP_ARCH=m68k ;; - 9000/7?? | 9000/8?[79] ) HP_ARCH=hppa1.1 ;; - 9000/8?? ) HP_ARCH=hppa1.0 ;; - esac - HPUX_REV=`echo ${UNAME_RELEASE}|sed -e 's/[^.]*.[0B]*//'` - echo ${HP_ARCH}-hp-hpux${HPUX_REV} - exit 0 ;; - 3050*:HI-UX:*:*) - sed 's/^ //' << EOF >dummy.c - #include - int - main () - { - long cpu = sysconf (_SC_CPU_VERSION); - /* The order matters, because CPU_IS_HP_MC68K erroneously returns - true for CPU_PA_RISC1_0. CPU_IS_PA_RISC returns correct - results, however. */ - if (CPU_IS_PA_RISC (cpu)) - { - switch (cpu) - { - case CPU_PA_RISC1_0: puts ("hppa1.0-hitachi-hiuxwe2"); break; - case CPU_PA_RISC1_1: puts ("hppa1.1-hitachi-hiuxwe2"); break; - case CPU_PA_RISC2_0: puts ("hppa2.0-hitachi-hiuxwe2"); break; - default: puts ("hppa-hitachi-hiuxwe2"); break; - } - } - else if (CPU_IS_HP_MC68K (cpu)) - puts ("m68k-hitachi-hiuxwe2"); - else puts ("unknown-hitachi-hiuxwe2"); - exit (0); - } -EOF - ${CC-cc} dummy.c -o dummy && ./dummy && rm dummy.c dummy && exit 0 - rm -f dummy.c dummy - echo unknown-hitachi-hiuxwe2 - exit 0 ;; - 9000/7??:4.3bsd:*:* | 9000/8?[79]:4.3bsd:*:* ) - echo hppa1.1-hp-bsd - exit 0 ;; - 9000/8??:4.3bsd:*:*) - echo hppa1.0-hp-bsd - exit 0 ;; - hp7??:OSF1:*:* | hp8?[79]:OSF1:*:* ) - echo hppa1.1-hp-osf - exit 0 ;; - hp8??:OSF1:*:*) - echo hppa1.0-hp-osf - exit 0 ;; - parisc*:Lites*:*:*) - echo hppa1.1-hp-lites - exit 0 ;; - C1*:ConvexOS:*:* | convex:ConvexOS:C1*:*) - echo c1-convex-bsd - exit 0 ;; - C2*:ConvexOS:*:* | convex:ConvexOS:C2*:*) - if getsysinfo -f scalar_acc - then echo c32-convex-bsd - else echo c2-convex-bsd - fi - exit 0 ;; - C34*:ConvexOS:*:* | convex:ConvexOS:C34*:*) - echo c34-convex-bsd - exit 0 ;; - C38*:ConvexOS:*:* | convex:ConvexOS:C38*:*) - echo c38-convex-bsd - exit 0 ;; - C4*:ConvexOS:*:* | convex:ConvexOS:C4*:*) - echo c4-convex-bsd - exit 0 ;; - CRAY*X-MP:*:*:*) - echo xmp-cray-unicos - exit 0 ;; - CRAY*Y-MP:*:*:*) - echo ymp-cray-unicos${UNAME_RELEASE} - exit 0 ;; - CRAY*C90:*:*:*) - echo c90-cray-unicos${UNAME_RELEASE} - exit 0 ;; - CRAY-2:*:*:*) - echo cray2-cray-unicos - exit 0 ;; - hp3[0-9][05]:NetBSD:*:*) - echo m68k-hp-netbsd${UNAME_RELEASE} - exit 0 ;; - i[34]86:BSD/386:*:* | *:BSD/OS:*:*) - echo ${UNAME_MACHINE}-unknown-bsdi${UNAME_RELEASE} - exit 0 ;; - i[3456]86:CYGWIN_NT*:*:*) - echo i386-unknown-nt4.0 - exit 0 ;; - *:FreeBSD:*:*) - echo ${UNAME_MACHINE}-unknown-freebsd`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` - exit 0 ;; - *:NetBSD:*:*) - echo ${UNAME_MACHINE}-unknown-netbsd`echo ${UNAME_RELEASE}|sed -e 's/[-_].*/\./'` - exit 0 ;; - *:GNU:*:*) - echo `echo ${UNAME_MACHINE}|sed -e 's,/.*$,,'`-unknown-gnu`echo ${UNAME_RELEASE}|sed -e 's,/.*$,,'` - exit 0 ;; - *:Linux:*:*) - # The BFD linker knows what the default object file format is, so - # first see if it will tell us. - ld_help_string=`ld --help 2>&1` - if echo $ld_help_string | grep >/dev/null 2>&1 "supported emulations: elf_i[345]86"; then - echo "${UNAME_MACHINE}-unknown-linux" ; exit 0 - elif echo $ld_help_string | grep >/dev/null 2>&1 "supported emulations: i[345]86linux"; then - echo "${UNAME_MACHINE}-unknown-linuxaout" ; exit 0 - elif echo $ld_help_string | grep >/dev/null 2>&1 "supported emulations: i[345]86coff"; then - echo "${UNAME_MACHINE}-unknown-linuxcoff" ; exit 0 - elif echo $ld_help_string | grep >/dev/null 2>&1 "supported emulations: elf64_ia64"; then - echo "${UNAME_MACHINE}-unknown-linux" ; exit 0 - elif echo $ld_help_string | grep >/dev/null 2>&1 "supported emulations: elf_x86_64"; then - echo "${UNAME_MACHINE}-unknown-linux" ; exit 0 - elif test "${UNAME_MACHINE}" = "alpha" ; then - echo alpha-unknown-linux ; exit 0 - else - # Either a pre-BFD a.out linker (linuxoldld) or one that does not give us - # useful --help. Gcc wants to distinguish between linuxoldld and linuxaout. - test ! -d /usr/lib/ldscripts/. \ - && echo "${UNAME_MACHINE}-unknown-linuxoldld" && exit 0 - # Determine whether the default compiler is a.out or elf - cat >dummy.c </dev/null && ./dummy "${UNAME_MACHINE}" && rm dummy.c dummy && exit 0 - rm -f dummy.c dummy - fi ;; -# ptx 4.0 does uname -s correctly, with DYNIX/ptx in there. earlier versions -# are messed up and put the nodename in both sysname and nodename. - i[34]86:DYNIX/ptx:4*:*) - echo i386-sequent-sysv4 - exit 0 ;; - i[34]86:*:4.*:* | i[34]86:SYSTEM_V:4.*:*) - if grep Novell /usr/include/link.h >/dev/null 2>/dev/null; then - echo ${UNAME_MACHINE}-univel-sysv${UNAME_RELEASE} - else - echo ${UNAME_MACHINE}-unknown-sysv${UNAME_RELEASE} - fi - exit 0 ;; - i[34]86:*:3.2:*) - if test -f /usr/options/cb.name; then - UNAME_REL=`sed -n 's/.*Version //p' /dev/null >/dev/null ; then - UNAME_REL=`(/bin/uname -X|egrep Release|sed -e 's/.*= //')` - (/bin/uname -X|egrep i80486 >/dev/null) && UNAME_MACHINE=i486 - echo ${UNAME_MACHINE}-unknown-sco$UNAME_REL - else - echo ${UNAME_MACHINE}-unknown-sysv32 - fi - exit 0 ;; - Intel:Mach:3*:*) - echo i386-unknown-mach3 - exit 0 ;; - paragon:*:*:*) - echo i860-intel-osf1 - exit 0 ;; - i860:*:4.*:*) # i860-SVR4 - if grep Stardent /usr/include/sys/uadmin.h >/dev/null 2>&1 ; then - echo i860-stardent-sysv${UNAME_RELEASE} # Stardent Vistra i860-SVR4 - else # Add other i860-SVR4 vendors below as they are discovered. - echo i860-unknown-sysv${UNAME_RELEASE} # Unknown i860-SVR4 - fi - exit 0 ;; - mini*:CTIX:SYS*5:*) - # "miniframe" - echo m68010-convergent-sysv - exit 0 ;; - M680[234]0:*:R3V[567]*:*) - test -r /sysV68 && echo 'm68k-motorola-sysv' && exit 0 ;; - 3[34]??:*:4.0:3.0 | 3[34]??,*:*:4.0:3.0) - uname -p 2>/dev/null | grep 86 >/dev/null \ - && echo i486-ncr-sysv4.3 && exit 0 ;; - 3[34]??:*:4.0:* | 3[34]??,*:*:4.0:*) - uname -p 2>/dev/null | grep 86 >/dev/null \ - && echo i486-ncr-sysv4 && exit 0 ;; - m680[234]0:LynxOS:2.[23]*:*) - echo m68k-lynx-lynxos${UNAME_RELEASE} - exit 0 ;; - mc68030:UNIX_System_V:4.*:*) - echo m68k-atari-sysv4 - exit 0 ;; - i[34]86:LynxOS:2.[23]*:*) - echo i386-lynx-lynxos${UNAME_RELEASE} - exit 0 ;; - TSUNAMI:LynxOS:2.[23]*:*) - echo sparc-lynx-lynxos${UNAME_RELEASE} - exit 0 ;; - rs6000:LynxOS:2.[23]*:*) - echo rs6000-lynx-lynxos${UNAME_RELEASE} - exit 0 ;; - RM*:SINIX-*:*:*) - echo mips-sni-sysv4 - exit 0 ;; - *:SINIX-*:*:*) - if uname -p 2>/dev/null >/dev/null ; then - UNAME_MACHINE=`(uname -p) 2>/dev/null` - echo ${UNAME_MACHINE}-sni-sysv4 - else - echo ns32k-sni-sysv - fi - exit 0 ;; -esac - -#echo '(No uname command or uname output not recognized.)' 1>&2 -#echo "${UNAME_MACHINE}:${UNAME_SYSTEM}:${UNAME_RELEASE}:${UNAME_VERSION}" 1>&2 - -cat >dummy.c < -# include -#endif -main () -{ -#if defined (sony) -#if defined (MIPSEB) - /* BFD wants "bsd" instead of "newsos". Perhaps BFD should be changed, - I don't know.... */ - printf ("mips-sony-bsd\n"); exit (0); -#else -#include - printf ("m68k-sony-newsos%s\n", -#ifdef NEWSOS4 - "4" -#else - "" -#endif - ); exit (0); -#endif -#endif - -#if defined (__arm) && defined (__acorn) && defined (__unix) - printf ("arm-acorn-riscix"); exit (0); -#endif - -#if defined (hp300) && !defined (hpux) - printf ("m68k-hp-bsd\n"); exit (0); -#endif - -#if defined (NeXT) -#if !defined (__ARCHITECTURE__) -#define __ARCHITECTURE__ "m68k" -#endif - int version; - version=`(hostinfo | sed -n 's/.*NeXT Mach \([0-9]*\).*/\1/p') 2>/dev/null`; - printf ("%s-next-nextstep%s\n", __ARCHITECTURE__, version==2 ? "2" : "3"); - exit (0); -#endif - -#if defined (MULTIMAX) || defined (n16) -#if defined (UMAXV) - printf ("ns32k-encore-sysv\n"); exit (0); -#else -#if defined (CMU) - printf ("ns32k-encore-mach\n"); exit (0); -#else - printf ("ns32k-encore-bsd\n"); exit (0); -#endif -#endif -#endif - -#if defined (__386BSD__) - printf ("i386-unknown-bsd\n"); exit (0); -#endif - -#if defined (sequent) -#if defined (i386) - printf ("i386-sequent-dynix\n"); exit (0); -#endif -#if defined (ns32000) - printf ("ns32k-sequent-dynix\n"); exit (0); -#endif -#endif - -#if defined (_SEQUENT_) - struct utsname un; - - uname(&un); - - if (strncmp(un.version, "V2", 2) == 0) { - printf ("i386-sequent-ptx2\n"); exit (0); - } - if (strncmp(un.version, "V1", 2) == 0) { /* XXX is V1 correct? */ - printf ("i386-sequent-ptx1\n"); exit (0); - } - printf ("i386-sequent-ptx\n"); exit (0); - -#endif - -#if defined (vax) -#if !defined (ultrix) - printf ("vax-dec-bsd\n"); exit (0); -#else - printf ("vax-dec-ultrix\n"); exit (0); -#endif -#endif - -#if defined (alliant) && defined (i860) - printf ("i860-alliant-bsd\n"); exit (0); -#endif - - exit (1); -} -EOF - -${CC-cc} dummy.c -o dummy 2>/dev/null && ./dummy && rm dummy.c dummy && exit 0 -rm -f dummy.c dummy - -# Apollos put the system type in the environment. - -test -d /usr/apollo && { echo ${ISP}-apollo-${SYSTYPE}; exit 0; } - -# Convex versions that predate uname can use getsysinfo(1) - -if [ -x /usr/convex/getsysinfo ] -then - case `getsysinfo -f cpu_type` in - c1*) - echo c1-convex-bsd - exit 0 ;; - c2*) - if getsysinfo -f scalar_acc - then echo c32-convex-bsd - else echo c2-convex-bsd - fi - exit 0 ;; - c34*) - echo c34-convex-bsd - exit 0 ;; - c38*) - echo c38-convex-bsd - exit 0 ;; - c4*) - echo c4-convex-bsd - exit 0 ;; - esac -fi - -#echo '(Unable to guess system type)' 1>&2 - -exit 1 diff --git a/stackwalk/CMakeLists.txt b/stackwalk/CMakeLists.txt index 106717e693..f9fa6223d9 100644 --- a/stackwalk/CMakeLists.txt +++ b/stackwalk/CMakeLists.txt @@ -1,103 +1,96 @@ -# CMake configuration for proccontrol directory +include_guard(GLOBAL) -include_directories ( - ${PROJECT_SOURCE_DIR}/proccontrol/h - ${PROJECT_SOURCE_DIR}/elf/h - ${PROJECT_SOURCE_DIR}/dwarf/h - src - h - ) +include(DyninstLibrary) -set (SRC_LIST - src/frame.C - src/framestepper.C - src/swk_errors.C - src/symlookup.C - src/walker.C - src/procstate.C - src/steppergroup.C - src/libstate.C - src/sw_pcontrol.C -) +set(_public_headers + h/basetypes.h + h/frame.h + h/framestepper.h + h/local_var.h + h/procstate.h + h/steppergroup.h + h/swk_errors.h + h/symlookup.h + h/walker.h) -if (PLATFORM MATCHES freebsd) -set (SRC_LIST ${SRC_LIST} - src/freebsd-swk.C - src/x86-swk.C - src/symtab-swk.C - src/dbginfo-stepper.C - src/x86-wanderer.C - src/linuxbsd-swk.C - src/linuxbsd-x86-swk.C - src/freebsd-x86-swk.C -) -elseif (PLATFORM MATCHES linux OR PLATFORM MATCHES freebsd) - set (SRC_LIST ${SRC_LIST} - src/symtab-swk.C - src/linuxbsd-swk.C - src/linux-swk.C - ) - if (PLATFORM MATCHES ppc) - set (SRC_LIST ${SRC_LIST} - src/linux-ppc-swk.C - src/ppc-swk.C - ) +set(_private_headers + src/addrRange.h + src/aarch64-swk.h + src/analysis_stepper.h + src/dbgstepper-impl.h + src/framestepper_pimple.h + src/freebsd-swk.h + src/get_trap_instruction.h + src/libstate.h + src/linuxbsd-swk.h + src/linux-swk.h + src/sw.h + src/symtab-swk.h + src/x86-swk.h) - elseif (PLATFORM MATCHES aarch64) - set (SRC_LIST ${SRC_LIST} - src/linux-aarch64-swk.C - src/aarch64-swk.C - src/dbginfo-stepper.C - ) +set(_sources + src/frame.C + src/framestepper.C + src/swk_errors.C + src/symlookup.C + src/walker.C + src/procstate.C + src/steppergroup.C + src/libstate.C + src/sw_pcontrol.C + src/symtab-swk.C) - elseif (PLATFORM MATCHES i386 OR PLATFORM MATCHES x86_64) - set (SRC_LIST ${SRC_LIST} - src/dbginfo-stepper.C - src/linux-x86-swk.C - src/x86-wanderer.C - src/linuxbsd-x86-swk.C - src/x86-swk.C - ) - endif() -endif() -if (PLATFORM MATCHES nt OR PLATFORM MATCHES windows) - set (SRC_LIST ${SRC_LIST} - src/x86-wanderer.C - src/x86-swk.C - src/win-x86-swk.C - src/symtab-swk.C - ) +if(DYNINST_ARCH_i386 OR DYNINST_ARCH_x86_64) + list(APPEND _sources src/x86-swk.C src/x86-wanderer.C) endif() -if (SW_ANALYSIS_STEPPER) - set (SRC_LIST ${SRC_LIST} - src/analysis_stepper.C - src/callchecker-IAPI.C - ) -else () - set (SRC_LIST ${SRC_LIST} - src/callchecker.C - ) +if(DYNINST_OS_FreeBSD) + list(APPEND _sources src/freebsd-swk.C) +elseif(DYNINST_OS_Windows) + list(APPEND _sources src/win-x86-swk.C) endif() -SET_SOURCE_FILES_PROPERTIES(${SRC_LIST} PROPERTIES LANGUAGE CXX) - -ADD_DEFINITIONS(-DSTACKWALKER_EXPORTS) - -set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} ${FORCE_FRAME_POINTER}") -set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} ${FORCE_FRAME_POINTER}") - -set(DEPS common instructionAPI pcontrol) -if (UNIX) -set (DEPS ${DEPS} dynDwarf dynElf) +if(DYNINST_OS_UNIX) + list(APPEND _sources src/linuxbsd-swk.C src/linux-swk.C) + if(DYNINST_ARCH_ppc64le) + list(APPEND _sources src/linux-ppc-swk.C src/ppc-swk.C) + elseif(DYNINST_ARCH_aarch64) + list(APPEND _sources src/linux-aarch64-swk.C src/aarch64-swk.C src/dbginfo-stepper.C) + elseif(DYNINST_ARCH_i386 OR DYNINST_ARCH_x86_64) + list(APPEND _sources src/linux-x86-swk.C src/linuxbsd-x86-swk.C src/dbginfo-stepper.C) + if(DYNINST_OS_FreeBSD) + list(APPEND _sources src/freebsd-x86-swk.C) + endif() + endif() endif() -set (DEPS ${DEPS} ${SYMREADER}) - -if (SW_ANALYSIS_STEPPER) -set (DEPS ${DEPS} parseAPI) -endif() +# cmake-format: off +dyninst_library( + stackwalk + PUBLIC_HEADER_FILES ${_public_headers} + PRIVATE_HEADER_FILES ${_private_headers} + SOURCE_FILES ${_sources} + DEFINES STACKWALKER_EXPORTS + DYNINST_DEPS common dynDwarf dynElf instructionAPI pcontrol ${SYMREADER} + PUBLIC_DEPS + PRIVATE_DEPS Dyninst::ElfUtils +) +# cmake-format: on +foreach(t ${stackwalk_TARGETS}) + # Force frame pointers in stackwalker, no matter the optimization level + # See commit 2608333f7 + target_compile_options(${t} PRIVATE ${DYNINST_FORCE_FRAME_POINTER}) -dyninst_library(stackwalk ${DEPS}) -target_link_private_libraries(stackwalk ${Boost_LIBRARIES}) + if(SW_ANALYSIS_STEPPER) + target_compile_definitions(${t} PRIVATE USE_PARSE_API) + if(${t} MATCHES "static") + target_link_libraries(${t} PUBLIC parseAPI_static) + else() + target_link_libraries(${t} PUBLIC parseAPI) + endif() + target_sources(${t} PRIVATE src/analysis_stepper.C src/callchecker-IAPI.C) + else() + target_sources(${t} PRIVATE src/callchecker.C) + endif() +endforeach() diff --git a/stackwalk/doc/stackwalk.pdf b/stackwalk/doc/stackwalk.pdf index 6f1b2d3a58..9647dd09ff 100644 Binary files a/stackwalk/doc/stackwalk.pdf and b/stackwalk/doc/stackwalk.pdf differ diff --git a/stackwalk/h/basetypes.h b/stackwalk/h/basetypes.h index f5c2c924b6..cbc95b94d0 100644 --- a/stackwalk/h/basetypes.h +++ b/stackwalk/h/basetypes.h @@ -32,8 +32,9 @@ #define BASETYPES_H_ #include "dyntypes.h" -#include "dyn_regs.h" +#include "registers/MachRegister.h" #include "SymReader.h" +#include #include #include diff --git a/stackwalk/h/frame.h b/stackwalk/h/frame.h index 16f8e1b4a6..8f93105989 100644 --- a/stackwalk/h/frame.h +++ b/stackwalk/h/frame.h @@ -35,6 +35,7 @@ #include "Annotatable.h" #include #include +#include class StackCallback; diff --git a/stackwalk/h/framestepper.h b/stackwalk/h/framestepper.h index e9202d7466..40b338b751 100644 --- a/stackwalk/h/framestepper.h +++ b/stackwalk/h/framestepper.h @@ -33,6 +33,7 @@ #include "basetypes.h" #include "procstate.h" +#include #include namespace Dyninst { diff --git a/stackwalk/h/local_var.h b/stackwalk/h/local_var.h new file mode 100644 index 0000000000..098c03e402 --- /dev/null +++ b/stackwalk/h/local_var.h @@ -0,0 +1,292 @@ +/* + * See the dyninst/COPYRIGHT file for copyright information. + * + * We provide the Paradyn Tools (below described as "Paradyn") + * on an AS IS basis, and do not warrant its validity or performance. + * We reserve the right to update, modify, or discontinue this + * software at any time. We shall have no obligation to supply such + * updates or modifications or any other form of support to you. + * + * By your use of Paradyn, you understand and agree that we (or any + * other person or entity with proprietary rights in Paradyn) are + * under no obligation to provide either maintenance services, + * update services, notices of latent defects, or correction of + * defects for Paradyn. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ +#if !defined (local_var_h_) +#define local_var_h_ + +#include +#include +#include "Symbol.h" +#include "Symtab.h" +#include "Type.h" +#include "Function.h" +#include "Architecture.h" +#include "registers/MachRegister.h" +#include "registers/abstract_regs.h" +#include "frame.h" +#include "procstate.h" +#include "walker.h" + +#include +#include + +using namespace Dyninst; +using namespace SymtabAPI; +using namespace Stackwalker; + +static Symtab *getSymtabForName(std::string name) +{ + static std::map symtabs; + std::map::iterator i; + + i = symtabs.find(name); + if (i != symtabs.end()) { + return i->second; + } + + Symtab *obj = NULL; + Symtab::openFile(obj, name); + symtabs[name] = obj; + return obj; +} + +class LVReader : public MemRegReader +{ + private: + ProcessState *proc; + int current_depth; + std::vector *swalk; + Dyninst::THR_ID thrd; + + bool isFrameRegister(MachRegister reg) + { + return reg.isFramePointer(); + } + + bool isStackRegister(MachRegister reg) + { + return reg.isStackPointer(); + } + public: + + LVReader(ProcessState *p, int f, std::vector *s, Dyninst::THR_ID t) : + proc(p), + current_depth(f), + swalk(s), + thrd(t) + { + } + + virtual bool ReadMem(Address addr, void *buffer, unsigned size) + { + return proc->readMem(buffer, addr, size); + } + + + virtual bool GetReg(MachRegister reg, MachRegisterVal &val) + { + Frame &f = (*swalk)[current_depth]; + if (isFrameRegister(reg)) { + val = static_cast(f.getFP()); + return true; + } + if (isStackRegister(reg)) { + val = static_cast(f.getSP()); + return true; + } + if (reg.isPC() || reg == Dyninst::ReturnAddr) { + val = static_cast(f.getRA()); + return true; + } + + if (!current_depth) { + return proc->getRegValue(reg, thrd, val); + } + + current_depth--; + Frame &g = (*swalk)[current_depth]; + Offset offset; + void *symtab_v; + std::string lib; + g.getLibOffset(lib, offset, symtab_v); + Symtab *symtab = getSymtabForName(lib); + if (!symtab) + return false; + + bool result = symtab->getRegValueAtFrame(offset, reg, val, this); + current_depth++; + return result; + } + + virtual bool start() { + return true; + } + virtual bool done() { + return true; + } + virtual ~LVReader() {} +}; + +/** + * Given a StackwalkerAPI frame, return the SymtabAPI function + * that created the frame. + **/ +static Dyninst::SymtabAPI::Function *getFunctionForFrame(Frame f) +{ + Offset offset; + void *symtab_v; + std::string lib_name; + bool result = f.getLibOffset(lib_name, offset, symtab_v); + if (!result) + return NULL; + Symtab *symtab = NULL; + if (symtab_v) { + symtab = (Symtab *) symtab_v; + } + else { + symtab = getSymtabForName(lib_name); + } + Function *func; + result = symtab->getContainingFunction(offset, func); + if (!result) + return NULL; + return func; +} + +/** + * Given a frame in a stackwalk, and a local variable, get the value + * of that local variable in the frame. + * + * 'localVar' is the variable that we're getting the value of. + * 'swalk' is a stackwalk from StackwalkerAPI + * 'frame' is an index into swalk and notes the frame that we'll be reading + * the variable from. localVar should be part of the frame defined by + * swalk[frame] + * 'out_buffer' is a buffer where we will write the value of the local variable. + * out_buffer_size should be the size of out_buffer, used to prevent buffer overflows + * + * getLocalVariableValue will return one of the following on success or error + **/ +static int glvv_Success = 0; +static int glvv_EParam = -1; +static int glvv_EOutOfScope = -2; +static int glvv_EBufferSize = -3; +static int glvv_EUnknown = -4; + +static int getLocalVariableValue(localVar *var, + std::vector &swalk, unsigned frame, + void *out_buffer, unsigned out_buffer_size) +{ + bool result; + + if (!var || frame < 0 || frame >= swalk.size() || !out_buffer) { + return glvv_EParam; + } + + /** + * Find the SymtabAPI object for this frame + * Find the offset for this frame's RA() + **/ + std::string lib_name; + Offset offset; + void *symtab_v; + swalk[frame].getLibOffset(lib_name, offset, symtab_v); + THR_ID thrd = swalk[frame].getThread(); + ProcessState *proc = swalk[frame].getWalker()->getProcessState(); + + /** + * Find the variable location that is valid at this point. + **/ + bool deref; + std::vector &locs = var->getLocationLists(); + std::vector::iterator i; + for (i = locs.begin(); i != locs.end(); i++) { + if (i->lowPC <= offset && offset < i->hiPC) { + break; + } + } + if (i == locs.end()) { + return glvv_EOutOfScope; + } + VariableLocation &loc = *i; + + /** + * Interpret the variable location + **/ + Address var_addr = 0; + deref = (loc.refClass == storageRef); + switch (loc.stClass) { + case storageAddr: + var_addr = loc.frameOffset; + break; + case storageReg: + case storageRegOffset: { + MachRegisterVal reg_value; + MachRegister reg = loc.mr_reg; + if (loc.stClass == storageRegOffset && reg == -1) { + reg = MachRegister::getFramePointer(proc->getAddressWidth() == 4 ? Arch_x86 : Arch_x86_64); + } + + LVReader r(proc, frame, &swalk, thrd); + result = r.GetReg(reg, reg_value); + + if (loc.stClass == storageReg) { + var_addr = reg_value; + } + else { + deref = true; + var_addr = reg_value + loc.frameOffset; + } + break; + } + } + + /** + * Get the size of the variable + **/ + unsigned size = out_buffer_size; + Type *var_type = var->getType(); + if (var_type) { + size = var_type->getSize(); + } + if (size > out_buffer_size) { + return glvv_EBufferSize; + } + + /** + * Read the resulting value + **/ + if (deref) { + result = proc->readMem(out_buffer, var_addr, size); + if (!result) { + return glvv_EUnknown; + } + return glvv_Success; + } + + if (size > sizeof(var_addr)) { + //Value stored in register, but larger than a register? + return glvv_EBufferSize; + } + memcpy(out_buffer, &var_addr, size); + + return glvv_Success; +} + +#endif diff --git a/stackwalk/h/procstate.h b/stackwalk/h/procstate.h index 6ecd16c4d8..03aaaf1f29 100644 --- a/stackwalk/h/procstate.h +++ b/stackwalk/h/procstate.h @@ -35,7 +35,8 @@ #define PROCSTATE_H_ #include "basetypes.h" -#include "dyn_regs.h" +#include "registers/MachRegister.h" +#include "Architecture.h" #include "PCProcess.h" @@ -43,6 +44,9 @@ #include #include #include +#include +#include +#include namespace Dyninst { namespace Stackwalker { @@ -86,7 +90,6 @@ class SW_EXPORT ProcessState { //Return the size of an address in process in bytes virtual unsigned getAddressWidth() = 0; - //Get Architecture, see dyn_regs.h virtual Dyninst::Architecture getArchitecture() = 0; virtual ~ProcessState(); diff --git a/stackwalk/h/walker.h b/stackwalk/h/walker.h index b33664c346..c504ef6d8e 100644 --- a/stackwalk/h/walker.h +++ b/stackwalk/h/walker.h @@ -34,6 +34,7 @@ #include "basetypes.h" #include "PCProcess.h" #include +#include #include #include #include diff --git a/stackwalk/src/aarch64-swk.C b/stackwalk/src/aarch64-swk.C index 71c0bdf7fa..4c667f7a0d 100644 --- a/stackwalk/src/aarch64-swk.C +++ b/stackwalk/src/aarch64-swk.C @@ -28,13 +28,15 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include "stackwalk/h/swk_errors.h" #include "stackwalk/h/procstate.h" #include "stackwalk/h/framestepper.h" #include "stackwalk/h/basetypes.h" #include "stackwalk/h/frame.h" #include "stackwalk/h/walker.h" - +#include "registers/abstract_regs.h" +#include "registers/aarch64_regs.h" #include "stackwalk/src/sw.h" #include "get_trap_instruction.h" diff --git a/stackwalk/src/aarch64-swk.h b/stackwalk/src/aarch64-swk.h index b13413fee4..457955e938 100644 --- a/stackwalk/src/aarch64-swk.h +++ b/stackwalk/src/aarch64-swk.h @@ -1,6 +1,7 @@ #ifndef aarch64_swk_h_ #define aarch64_swk_h_ +#include #include "stackwalk/h/steppergroup.h" #include "stackwalk/h/framestepper.h" diff --git a/common/src/addrRange.h b/stackwalk/src/addrRange.h similarity index 96% rename from common/src/addrRange.h rename to stackwalk/src/addrRange.h index cb137830ac..aca2570b12 100644 --- a/common/src/addrRange.h +++ b/stackwalk/src/addrRange.h @@ -37,9 +37,8 @@ #include #include +#include #include -#include "common/src/Types.h" -#include "common/src/std_namesp.h" /** template class for addrRangeTree. The implementation is based on red black * tree implementation for efficiency concerns and for getting sorted @@ -54,7 +53,7 @@ typedef enum { TREE_RED, TREE_BLACK } color_t; class addrRange { public: - virtual Address get_address() const = 0; + virtual Dyninst::Address get_address() const = 0; virtual unsigned long get_size() const = 0; virtual std::string get_name() const { return std::string("UNNAMED"); @@ -71,7 +70,7 @@ class addrRangeTree { /** tree implementation structure. Used to implement the RB tree */ typedef struct entry { - Address key; + Dyninst::Address key; T *value; color_t color; /* color of the node */ struct entry* left; /* left child */ @@ -98,7 +97,7 @@ class addrRangeTree { * @param d data element * @param e nill entry */ - entry(Address key_, T *value_, entry* e) + entry(Dyninst::Address key_, T *value_, entry* e) : key(key_), value(value_), color(TREE_RED), left(e), right(e), parent(NULL) { @@ -241,7 +240,7 @@ class addrRangeTree { // insertion to a binary search tree. It returns the new element pointer // that is inserted. If element is already there it returns NULL - entry* treeInsert(Address key, T *value) + entry* treeInsert(Dyninst::Address key, T *value) { entry* y = NULL; entry* x = setData; @@ -292,7 +291,7 @@ class addrRangeTree { // method that returns the entry pointer for the element that is searched //for. If the entry is not found then it retuns NULL - entry* find_internal(Address element) const + entry* find_internal(Dyninst::Address element) const { entry* x = setData; while(x != nil){ @@ -355,7 +354,7 @@ class addrRangeTree { } // Similar to precessor, but returns an entry - bool precessor_internal(Address key, entry * &value) const + bool precessor_internal(Dyninst::Address key, entry * &value) const { entry *x = setData; entry *last = nil; @@ -389,7 +388,7 @@ class addrRangeTree { // Similar to successor, but returns an entry - bool successor_internal(Address key, entry * &value) const + bool successor_internal(Dyninst::Address key, entry * &value) const { entry *x = setData; entry *last = nil; @@ -504,7 +503,7 @@ class addrRangeTree { /** removes the element in the tree * @param 1 element that will be removed */ - void remove(Address key) + void remove(Dyninst::Address key) { entry* z = find_internal(key); if(!z) @@ -536,7 +535,7 @@ class addrRangeTree { /** returns true if the argument is member of the addrRangeTree * @param e the element that will be searched for */ - virtual bool find(Address key, T *& value) const + virtual bool find(Dyninst::Address key, T *& value) const { value = NULL; if (!precessor(key, value)) @@ -559,7 +558,7 @@ class addrRangeTree { /** Fills in the vector with all address ranges that overlap * with the address range defined by (start, end] */ - virtual bool find(Address start, Address end, + virtual bool find(Dyninst::Address start, Dyninst::Address end, std::vector &ranges) const { entry *cur = nil; @@ -585,7 +584,7 @@ class addrRangeTree { /** Returns the largest value less than or equal to the * key given */ - virtual bool precessor(Address key, T *& value) const + virtual bool precessor(Dyninst::Address key, T *& value) const { entry *val; bool result = precessor_internal(key, val); @@ -599,7 +598,7 @@ class addrRangeTree { /** Returns the smallest value greater than or equal to the * key given */ - virtual bool successor(Address key, T *& value) const + virtual bool successor(Dyninst::Address key, T *& value) const { entry *val; bool result = successor_internal(key, val); diff --git a/stackwalk/src/analysis_stepper.C b/stackwalk/src/analysis_stepper.C index e300fe2f7c..d859421b64 100644 --- a/stackwalk/src/analysis_stepper.C +++ b/stackwalk/src/analysis_stepper.C @@ -28,6 +28,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include "stackwalk/src/analysis_stepper.h" #include "dataflowAPI/h/stackanalysis.h" #include "stackwalk/h/swk_errors.h" @@ -45,7 +46,7 @@ #elif defined(WITH_SYMTAB_API) #include "symtabAPI/h/Symtab.h" #include "symtabAPI/h/SymtabReader.h" -using namespace SymtabAPI; +using namespace Dyninst::SymtabAPI; #else #error "No defined symbol reader" #endif diff --git a/stackwalk/src/analysis_stepper.h b/stackwalk/src/analysis_stepper.h index eb75e7f4ad..ff5b671bb0 100644 --- a/stackwalk/src/analysis_stepper.h +++ b/stackwalk/src/analysis_stepper.h @@ -37,6 +37,10 @@ #include "SymReader.h" #include +#include +#include +#include +#include namespace Dyninst { namespace ParseAPI { diff --git a/stackwalk/src/callchecker-IAPI.C b/stackwalk/src/callchecker-IAPI.C index 46701d88ae..be6b55a2a0 100644 --- a/stackwalk/src/callchecker-IAPI.C +++ b/stackwalk/src/callchecker-IAPI.C @@ -32,6 +32,7 @@ #include "stackwalk/src/sw.h" #include "instructionAPI/h/InstructionDecoder.h" +#include "unaligned_memory_access.h" using namespace Dyninst; using namespace Stackwalker; @@ -78,7 +79,7 @@ bool CallChecker::isPrevInstrACall(Address addr, Address &target) // is it (a) aligned and (b) a call? if ( (aligned == size) && (prevInsn.getOperation().getID() == e_call) ) { - int disp = *((int*)(bufferPtr+(size-prevInsn.size() + 2))); + int disp = Dyninst::read_memory_as(bufferPtr+(size-prevInsn.size() + 2)); target = addr + disp; sw_printf("[%s:%d] - Found call encoded by %d to %lx (addr = %lx, disp = %x)\n", FILE__, __LINE__, diff --git a/stackwalk/src/callchecker.C b/stackwalk/src/callchecker.C index 48cd52d006..ac4b36523e 100644 --- a/stackwalk/src/callchecker.C +++ b/stackwalk/src/callchecker.C @@ -44,12 +44,12 @@ bool CallChecker::isPrevInstrACall(Address addr, Address & target) bool result; unsigned char buffer[max_call_length]; - sw_printf("[%s:%u] - isPrevInstrACall on %lx\n", FILE__, __LINE__, addr); + sw_printf("[%s:%d] - isPrevInstrACall on %lx\n", FILE__, __LINE__, addr); Address start = addr - max_call_length; result = proc->readMem(buffer, start, max_call_length); if (!result) { - sw_printf("[%s:%u] - Address 0x%lx is not a call--unreadable\n", + sw_printf("[%s:%d] - Address 0x%lx is not a call--unreadable\n", FILE__, __LINE__, addr); return false; } @@ -57,7 +57,7 @@ bool CallChecker::isPrevInstrACall(Address addr, Address & target) if (buffer[max_call_length - 5] == 0xe8) { int32_t disp = *((int32_t *) (buffer+1)); target = addr + disp; - sw_printf("[%s:%u] - Found call encoded by %x to %lx (addr = %lx, disp = %lx)\n", + sw_printf("[%s:%d] - Found call encoded by %x to %lx (addr = %lx, disp = %dx)\n", FILE__, __LINE__, (int) buffer[0], target, addr, disp); return true; @@ -102,7 +102,7 @@ bool CallChecker::isPrevInstrACall(Address addr, Address & target) if (i + size == max_call_length) { - sw_printf("[%s:%u] - Found call of size %d encoded by: ", + sw_printf("[%s:%d] - Found call of size %u encoded by: ", FILE__, __LINE__, size); for (unsigned j=i; j #include "stackwalk/h/framestepper.h" #include "stackwalk/h/frame.h" #include "stackwalk/h/procstate.h" @@ -39,9 +40,16 @@ #include "stackwalk/src/libstate.h" #include "common/h/dyntypes.h" #include "common/h/VariableLocation.h" -#include "common/src/Types.h" #include "dwarfFrameParser.h" #include "dwarfHandle.h" +#include "Architecture.h" +#include "registers/abstract_regs.h" +#include "registers/x86_regs.h" +#include "registers/x86_64_regs.h" + +#ifdef arch_aarch64 +# include "registers/aarch64_regs.h" +#endif #if defined(WITH_SYMTAB_API) #include "symtabAPI/h/Symtab.h" @@ -680,3 +688,4 @@ bool DebugStepperImpl::lookupInCache(const Frame &cur, Frame &caller) { #endif //end if defined aarch64 + diff --git a/stackwalk/src/dbgstepper-impl.h b/stackwalk/src/dbgstepper-impl.h index 8e3e03a554..a80dd9e378 100644 --- a/stackwalk/src/dbgstepper-impl.h +++ b/stackwalk/src/dbgstepper-impl.h @@ -38,7 +38,7 @@ namespace Dyninst { namespace DwarfDyninst { class DwarfFrameParser; -typedef boost::shared_ptr DwarfFrameParserPtr; +typedef dyncompat::shared_ptr DwarfFrameParserPtr; } namespace Stackwalker { diff --git a/stackwalk/src/framestepper.C b/stackwalk/src/framestepper.C index e6384749e8..7895f2fa13 100644 --- a/stackwalk/src/framestepper.C +++ b/stackwalk/src/framestepper.C @@ -28,6 +28,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include "stackwalk/h/framestepper.h" #include "stackwalk/h/walker.h" #include "stackwalk/h/procstate.h" @@ -378,8 +379,8 @@ gcframe_ret_t DyninstInstFrameStepperImpl::getCallerFrame(const Frame &in, Frame return gcf_not_me; } - sw_printf("[%s:%d] - %lx reading from memory at location %lx with framePtr %lx\n", - FILE__, __LINE__, ret, framePtr + addr_width, framePtr); + sw_printf("[%s:%d] - reading from memory at location %lx with framePtr %lx\n", + FILE__, __LINE__, framePtr + addr_width, framePtr); // Read the location in the stack where the Special Value should be. // This value was inserted into the stack at inst frame creation. diff --git a/stackwalk/src/freebsd-swk.h b/stackwalk/src/freebsd-swk.h index f1a02ede11..b3fcda1978 100644 --- a/stackwalk/src/freebsd-swk.h +++ b/stackwalk/src/freebsd-swk.h @@ -31,7 +31,6 @@ #ifndef FREEBSD_SWK_H #define FREEBSD_SWK_H -#include "common/src/Types.h" #include "common/src/freebsdKludges.h" #define START_THREAD_FUNC_NAME "thread_start" diff --git a/stackwalk/src/freebsd-x86-swk.C b/stackwalk/src/freebsd-x86-swk.C index 036acae036..c9450a88cf 100644 --- a/stackwalk/src/freebsd-x86-swk.C +++ b/stackwalk/src/freebsd-x86-swk.C @@ -40,8 +40,6 @@ #include "stackwalk/src/dbgstepper-impl.h" #include "stackwalk/src/x86-swk.h" -#include "common/src/Types.h" - #include #include #include diff --git a/stackwalk/src/libstate.h b/stackwalk/src/libstate.h index 349b8b345a..58067a4990 100644 --- a/stackwalk/src/libstate.h +++ b/stackwalk/src/libstate.h @@ -35,6 +35,10 @@ #include "common/h/SymReader.h" #include "stackwalk/h/procstate.h" #include "common/src/addrtranslate.h" +#include +#include +#include +#include #include namespace Dyninst { diff --git a/stackwalk/src/linux-aarch64-swk.C b/stackwalk/src/linux-aarch64-swk.C index e5111e99bc..31a18acc30 100644 --- a/stackwalk/src/linux-aarch64-swk.C +++ b/stackwalk/src/linux-aarch64-swk.C @@ -37,8 +37,8 @@ #include "stackwalk/src/linuxbsd-swk.h" #include "stackwalk/src/dbgstepper-impl.h" - -#include "common/h/dyn_regs.h" +#include "registers/aarch64_regs.h" +#include "registers/MachRegister.h" #include "frame.h" #include diff --git a/stackwalk/src/linux-ppc-swk.C b/stackwalk/src/linux-ppc-swk.C index 78113cf5f8..147912b3a3 100644 --- a/stackwalk/src/linux-ppc-swk.C +++ b/stackwalk/src/linux-ppc-swk.C @@ -34,7 +34,6 @@ #include "stackwalk/h/procstate.h" #include "stackwalk/h/framestepper.h" #include "stackwalk/src/linuxbsd-swk.h" -#include "common/h/dyn_regs.h" #include #include #include diff --git a/stackwalk/src/linux-swk.C b/stackwalk/src/linux-swk.C index cf21add5d6..b62673c048 100644 --- a/stackwalk/src/linux-swk.C +++ b/stackwalk/src/linux-swk.C @@ -28,6 +28,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include "stackwalk/h/swk_errors.h" #include "stackwalk/h/symlookup.h" #include "stackwalk/h/walker.h" @@ -58,7 +59,6 @@ #include #include "common/src/parseauxv.h" -#include "common/h/dyn_regs.h" #include "symtabAPI/h/SymtabReader.h" diff --git a/stackwalk/src/linux-swk.h b/stackwalk/src/linux-swk.h index ba988857be..bb363b117a 100644 --- a/stackwalk/src/linux-swk.h +++ b/stackwalk/src/linux-swk.h @@ -31,10 +31,10 @@ #ifndef LINUX_SWK_H #define LINUX_SWK_H +#include #include "common/h/dyntypes.h" #include "common/h/SymReader.h" -#include "common/src/Types.h" #include "common/src/linuxKludges.h" #define START_THREAD_FUNC_NAME "start_thread" diff --git a/stackwalk/src/linux-x86-swk.C b/stackwalk/src/linux-x86-swk.C index e9b65eccc0..f6a7210ba7 100644 --- a/stackwalk/src/linux-x86-swk.C +++ b/stackwalk/src/linux-x86-swk.C @@ -40,8 +40,6 @@ #include "stackwalk/src/dbgstepper-impl.h" #include "stackwalk/src/x86-swk.h" -#include "common/src/Types.h" - #include #include #include diff --git a/stackwalk/src/linuxbsd-swk.C b/stackwalk/src/linuxbsd-swk.C index ce10f9881a..7afbb72424 100644 --- a/stackwalk/src/linuxbsd-swk.C +++ b/stackwalk/src/linuxbsd-swk.C @@ -34,7 +34,7 @@ #include "stackwalk/h/steppergroup.h" #include "stackwalk/h/procstate.h" #include "stackwalk/h/frame.h" - +#include "common/src/vm_maps.h" #include "stackwalk/src/sw.h" #include "stackwalk/src/symtab-swk.h" #include "stackwalk/src/libstate.h" diff --git a/stackwalk/src/linuxbsd-swk.h b/stackwalk/src/linuxbsd-swk.h index 63fa9e995f..0b8061c625 100644 --- a/stackwalk/src/linuxbsd-swk.h +++ b/stackwalk/src/linuxbsd-swk.h @@ -34,8 +34,6 @@ #include "common/h/dyntypes.h" #include "common/h/SymReader.h" -#include "common/src/Types.h" - #include "stackwalk/h/framestepper.h" #define MAX_TRAP_LEN 8 diff --git a/stackwalk/src/linuxbsd-x86-swk.C b/stackwalk/src/linuxbsd-x86-swk.C index 21c39aa2f7..563973830d 100644 --- a/stackwalk/src/linuxbsd-x86-swk.C +++ b/stackwalk/src/linuxbsd-x86-swk.C @@ -40,7 +40,8 @@ #include "stackwalk/src/dbgstepper-impl.h" #include "stackwalk/src/x86-swk.h" -#include "common/src/Types.h" +#include "registers/x86_regs.h" +#include "registers/x86_64_regs.h" #include #include diff --git a/stackwalk/src/ppc-swk.C b/stackwalk/src/ppc-swk.C index 9761a9f645..a92022bf9e 100644 --- a/stackwalk/src/ppc-swk.C +++ b/stackwalk/src/ppc-swk.C @@ -34,7 +34,9 @@ #include "stackwalk/h/basetypes.h" #include "stackwalk/h/frame.h" #include "stackwalk/h/walker.h" - +#include "registers/abstract_regs.h" +#include "registers/ppc64_regs.h" +#include "registers/ppc32_regs.h" #include "stackwalk/src/sw.h" #include "get_trap_instruction.h" diff --git a/stackwalk/src/procstate.C b/stackwalk/src/procstate.C index abb9f185ca..38576d35e2 100644 --- a/stackwalk/src/procstate.C +++ b/stackwalk/src/procstate.C @@ -28,6 +28,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include "stackwalk/h/swk_errors.h" #include "stackwalk/h/procstate.h" #include "stackwalk/src/libstate.h" diff --git a/stackwalk/src/steppergroup.C b/stackwalk/src/steppergroup.C index b5b507443a..9476ca862d 100644 --- a/stackwalk/src/steppergroup.C +++ b/stackwalk/src/steppergroup.C @@ -28,6 +28,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include "stackwalk/h/steppergroup.h" #include "stackwalk/h/framestepper.h" #include "stackwalk/h/swk_errors.h" diff --git a/stackwalk/src/sw.h b/stackwalk/src/sw.h index 62498f9bbd..7cfe523b71 100644 --- a/stackwalk/src/sw.h +++ b/stackwalk/src/sw.h @@ -32,7 +32,10 @@ #define SW_INTERNAL_H_ #include -#include "common/src/addrRange.h" +#include +#include +#include +#include "addrRange.h" #include "stackwalk/h/framestepper.h" #include "stackwalk/h/procstate.h" #include "stackwalk/h/walker.h" diff --git a/stackwalk/src/sw_pcontrol.C b/stackwalk/src/sw_pcontrol.C index 790bf0d00b..e70173e77f 100644 --- a/stackwalk/src/sw_pcontrol.C +++ b/stackwalk/src/sw_pcontrol.C @@ -28,6 +28,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include "stackwalk/h/procstate.h" #include "stackwalk/h/swk_errors.h" #include "stackwalk/h/walker.h" @@ -38,7 +39,7 @@ #include "PlatFeatures.h" #include "PCErrors.h" -#include "common/h/dyn_regs.h" +#include "registers/abstract_regs.h" #include "common/h/SymReader.h" #include "stackwalk/src/libstate.h" diff --git a/stackwalk/src/walker.C b/stackwalk/src/walker.C index d5aa78e4a6..327de04a08 100644 --- a/stackwalk/src/walker.C +++ b/stackwalk/src/walker.C @@ -28,6 +28,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include "stackwalk/h/walker.h" #include "stackwalk/h/frame.h" #include "stackwalk/h/swk_errors.h" @@ -38,6 +39,7 @@ #include "stackwalk/src/sw.h" #include "stackwalk/src/libstate.h" #include +#include "registers/abstract_regs.h" using namespace Dyninst; using namespace Dyninst::Stackwalker; diff --git a/stackwalk/src/x86-swk.C b/stackwalk/src/x86-swk.C index c5ec3a2456..1e28d40398 100644 --- a/stackwalk/src/x86-swk.C +++ b/stackwalk/src/x86-swk.C @@ -28,6 +28,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include "stackwalk/h/basetypes.h" #include "stackwalk/h/swk_errors.h" #include "stackwalk/h/procstate.h" @@ -42,7 +43,9 @@ #include "stackwalk/src/libstate.h" #include "common/src/lru_cache.h" - +#include "registers/x86_regs.h" +#include "registers/x86_64_regs.h" +#include "registers/abstract_regs.h" #include "common/h/SymReader.h" using namespace Dyninst; diff --git a/stackwalk/src/x86-swk.h b/stackwalk/src/x86-swk.h index a2f3681feb..19023e7ccc 100644 --- a/stackwalk/src/x86-swk.h +++ b/stackwalk/src/x86-swk.h @@ -31,6 +31,7 @@ #ifndef x86_swk_h_ #define x86_swk_h_ +#include #include "stackwalk/h/steppergroup.h" #include "stackwalk/h/framestepper.h" #include "common/h/dyntypes.h" diff --git a/stackwalk/src/x86-wanderer.C b/stackwalk/src/x86-wanderer.C index c69f2adaa7..41c120c7f5 100644 --- a/stackwalk/src/x86-wanderer.C +++ b/stackwalk/src/x86-wanderer.C @@ -38,12 +38,12 @@ #include "stackwalk/src/libstate.h" #include "stackwalk/src/sw.h" -#include "common/src/Types.h" - #include "compiler_annotations.h" #include "common/h/SymReader.h" +#include "unaligned_memory_access.h" + using namespace Dyninst; using namespace Stackwalker; @@ -249,11 +249,11 @@ WandererHelper::pc_state WandererHelper::isPCInFunc(Address func_entry, Address result = proc->readMem(buffer, func_entry, MAX_PLT32_IDIOM_SIZE); if (buffer[0] == 0xff && buffer[1] == 0xa3) { //Indirect jump off of ebx - got_offset = *((int32_t*) (buffer+2)); + got_offset = Dyninst::read_memory_as(buffer+2); } else if (buffer[0] == 0xff && buffer[1] == 0x25) { //Indirect jump through absolute - got_abs = *((uint32_t*) (buffer+2)); + got_abs = Dyninst::read_memory_as(buffer+2); } else { sw_printf("[%s:%d] - Unrecognized PLT idiom at %lx: ", @@ -271,7 +271,7 @@ WandererHelper::pc_state WandererHelper::isPCInFunc(Address func_entry, Address result = proc->readMem(buffer, func_entry, MAX_PLT64_IDIOM_SIZE); if (buffer[0] == 0xff && buffer[1] == 0x25) { //PC Relative jump indirect - got_abs = *((int32_t *) (buffer+2)) + func_entry + 6; + got_abs = Dyninst::read_memory_as(buffer+2) + func_entry + 6; } else { sw_printf("[%s:%d] - Unrecognized PLT idiom at %lx: ", diff --git a/symlite/CMakeLists.txt b/symlite/CMakeLists.txt index 343ae92f86..ad05391f4a 100644 --- a/symlite/CMakeLists.txt +++ b/symlite/CMakeLists.txt @@ -1,31 +1,28 @@ -# CMake configuration for symlite directory +include_guard(GLOBAL) -if (NOT UNIX) +if(NOT LIGHTWEIGHT_SYMTAB) return() endif() -include_directories ( - src - ${PROJECT_SOURCE_DIR}/elf/h - ) +include(DyninstLibrary) -set (SRC_LIST - src/SymLite-elf.C - ) -add_definitions(-DSYMLITE_LIB) +if(NOT DYNINST_OS_UNIX) + if(NOT TARGET symLite) + add_library(symLite INTERFACE) + endif() + return() +endif() -#add_library (symLite ${SRC_LIST}) -#add_library (symLite_static STATIC ${SRC_LIST}) -#FILE (GLOB headers "h/*.h") -#set_target_properties (symLite symLite_static PROPERTIES PUBLIC_HEADER "${headers}") +set(_public_headers h/SymLite-elf.h) -#target_link_private_libraries (symLite common) -#target_link_private_libraries (symLite dynElf) +set(_sources src/SymLite-elf.C) -#INSTALL (TARGETS symLite symLite_static -# EXPORT DyninstTargets -# RUNTIME DESTINATION ${INSTALL_LIB_DIR} -# LIBRARY DESTINATION ${INSTALL_LIB_DIR} -# ARCHIVE DESTINATION ${INSTALL_LIB_DIR} -# PUBLIC_HEADER DESTINATION ${INSTALL_INCLUDE_DIR}) -dyninst_library(symLite common dynElf) +# cmake-format: off +dyninst_library( + symLite + PUBLIC_HEADER_FILES ${_public_headers} + SOURCE_FILES ${_sources} + DEFINES SYMLITE_LIB + DYNINST_DEPS common dynElf +) +# cmake-format: on diff --git a/symlite/h/SymLite-elf.h b/symlite/h/SymLite-elf.h index 104bbc61fe..ff82e14da7 100644 --- a/symlite/h/SymLite-elf.h +++ b/symlite/h/SymLite-elf.h @@ -28,10 +28,10 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "common/h/SymReader.h" +#include "SymReader.h" #include "Elf_X.h" -#include "common/src/headers.h" +#include #include namespace Dyninst { diff --git a/symlite/src/SymLite-elf.C b/symlite/src/SymLite-elf.C index 887c5f80a0..ef117e88a5 100644 --- a/symlite/src/SymLite-elf.C +++ b/symlite/src/SymLite-elf.C @@ -28,7 +28,10 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include "SymLite-elf.h" +#include "common/src/headers.h" +#include "unaligned_memory_access.h" #include #include #include @@ -400,7 +403,7 @@ unsigned long SymElf::getSymOffset(const Elf_X_Sym &symbol, unsigned idx) unsigned long sym_offset = symbol.st_value(idx); while (sym_offset >= odp_addr && sym_offset < odp_addr + odp_size) - sym_offset = *((const unsigned long *) (odp_data + sym_offset - odp_addr)); + sym_offset = Dyninst::read_memory_as(odp_data + sym_offset - odp_addr); return sym_offset; } @@ -418,7 +421,7 @@ unsigned long SymElf::getSymTOC(const Elf_X_Sym &symbol, unsigned idx) if (sym_offset < odp_addr || (sym_offset >= odp_addr + odp_size)) return 0; - unsigned long toc = *((const unsigned long *) (odp_data + (sym_offset - odp_addr + sizeof(long)))); + auto toc = Dyninst::read_memory_as(odp_data + (sym_offset - odp_addr + sizeof(long))); return toc; } diff --git a/symtabAPI/CMakeLists.txt b/symtabAPI/CMakeLists.txt index 1f1f2027f7..14a7ecc52a 100644 --- a/symtabAPI/CMakeLists.txt +++ b/symtabAPI/CMakeLists.txt @@ -1,120 +1,107 @@ -# CMake configuration for symtabAPI directory - -include_directories ( - src - h - ${PROJECT_SOURCE_DIR}/dwarf/h - ${PROJECT_SOURCE_DIR}/elf/h - ) - -if(NOT WIN32) - include_directories(${PROJECT_SOURCE_DIR}/common/src) -endif() - - - -set (SRC_LIST - src/Object.C - src/Aggregate.C - src/Function.C - src/Variable.C - src/Symbol.C - src/LineInformation.C - src/Symtab.C - src/Symtab-edit.C - src/Symtab-lookup.C - src/Module.C - src/Region.C - src/Collections.C - src/Type.C - src/AddrLookup.C - src/annotations.C - src/debug.C - src/SymtabReader.C - ) - -if (PLATFORM MATCHES freebsd OR - PLATFORM MATCHES linux OR - PLATFORM MATCHES cnl) - -set (SRC_LIST ${SRC_LIST} - src/Object-elf.C - src/Archive.C - src/Archive-elf.C +include_guard(GLOBAL) + +include(DyninstLibrary) + +set(_public_headers + h/AddrLookup.h + h/Aggregate.h + h/Archive.h + h/Collections.h + h/ExceptionBlock.h + h/Function.h + h/LineInformation.h + h/Module.h + h/RangeLookup.h + h/Region.h + h/relocationEntry.h + h/Statement.h + h/StringTable.h + h/Symbol.h + h/Symtab.h + h/SymtabReader.h + h/symutil.h + h/Type.h + h/Variable.h) + +set(_private_headers + src/annotations.h + src/debug.h + src/dwarfWalker.h + src/emitElf.h + src/emitElfStatic.h + src/emitWin.h + src/LinkMap.h + src/Object-elf.h + src/Object.h + src/Object-nt.h + src/Type-mem.h + src/indexed_symbols.hpp + src/symtab_impl.hpp + src/indexed_modules.h) + +set(_sources + src/AddrLookup.C + src/Aggregate.C + src/annotations.C + src/Collections.C + src/debug.C + src/ExceptionBlock.C + src/Function.C + src/LineInformation.C + src/Module.C + src/Object.C + src/Region.C + src/relocationEntry.C + src/Statement.C + src/Symbol.C + src/Symtab-edit.C + src/Symtab-lookup.C + src/Symtab.C + src/SymtabReader.C + src/Type.C + src/Variable.C) + +if(DYNINST_OS_UNIX) + list( + APPEND + _sources + src/Object-elf.C + src/Archive.C + src/Archive-elf.C src/parseDwarf.C - src/parseStab.C - src/LinkMap.C - src/emitElf.C + src/LinkMap.C + src/emitElf.C src/emitElfStatic.C - src/dwarfWalker.C -) - -if (PLATFORM MATCHES x86_64 OR PLATFORM MATCHES amd64) -set (SRC_LIST ${SRC_LIST} - src/emitElfStatic-x86.C - src/relocationEntry-elf-x86.C - ) -elseif (PLATFORM MATCHES i386) -set (SRC_LIST ${SRC_LIST} - src/emitElfStatic-x86.C - src/relocationEntry-elf-x86.C - ) -elseif (PLATFORM MATCHES ppc32) -set (SRC_LIST ${SRC_LIST} - src/emitElfStatic-ppc32.C - src/relocationEntry-elf-ppc32.C - ) -elseif (PLATFORM MATCHES ppc64) -set (SRC_LIST ${SRC_LIST} - src/emitElfStatic-ppc64.C - src/relocationEntry-elf-ppc64.C - ) -elseif (PLATFORM MATCHES aarch64) -set (SRC_LIST ${SRC_LIST} - src/emitElfStatic-aarch64.C - src/relocationEntry-elf-aarch64.C - ) -else (TRUE) -set (SRC_LIST ${SRC_LIST} - src/emitElfStatic-stub.C - src/relocationEntry-stub.C - ) -endif() + src/dwarfWalker.C) + + if(DYNINST_ARCH_x86_64 OR DYNINST_ARCH_i386) + list(APPEND _sources src/emitElfStatic-x86.C src/relocationEntry-elf-x86.C) + elseif(DYNINST_ARCH_ppc64le) + list(APPEND _sources src/emitElfStatic-ppc64.C src/relocationEntry-elf-ppc64.C) + elseif(DYNINST_ARCH_aarch64) + list(APPEND _sources src/emitElfStatic-aarch64.C src/relocationEntry-elf-aarch64.C) + else() + list(APPEND _sources src/emitElfStatic-stub.C src/relocationEntry-stub.C) + endif() +elseif(DYNINST_OS_Windows) + list(APPEND _sources src/Object-nt.C src/emitWin.C src/relocationEntry-stub.C) endif() - -if (PLATFORM MATCHES nt) -set (SRC_LIST ${SRC_LIST} - src/Object-nt.C - src/emitWin.C - src/relocationEntry-stub.C +# cmake-format: off +dyninst_library( + symtabAPI + PUBLIC_HEADER_FILES ${_public_headers} + PRIVATE_HEADER_FILES ${_private_headers} + SOURCE_FILES ${_sources} + DEFINES SYMTAB_LIB + DYNINST_DEPS common dynElf dynDwarf + PRIVATE_DEPS OpenMP::OpenMP_CXX + PUBLIC_DEPS Dyninst::ElfUtils ) -endif() - -SET_SOURCE_FILES_PROPERTIES(${SRC_LIST} PROPERTIES LANGUAGE CXX) - -ADD_DEFINITIONS(-DSYMTAB_LIB) - -set (DEPS common) - -if(UNIX) - list (APPEND DEPS - dynElf - dynDwarf - ${ElfUtils_LIBRARIES} - ) -else() - list (APPEND DEPS dbghelp) -endif() - -dyninst_library(symtabAPI ${DEPS}) - -if(TARGET ElfUtils) - add_dependencies(symtabAPI ElfUtils) -endif() - -target_link_private_libraries(symtabAPI ${Boost_LIBRARIES}) +# cmake-format: on -if(USE_OpenMP) - set_target_properties(symtabAPI PROPERTIES COMPILE_FLAGS ${OpenMP_CXX_FLAGS} LINK_FLAGS ${OpenMP_CXX_FLAGS}) +if(DYNINST_OS_Windows) + foreach(t ${symtabAPI_TARGETS}) + target_link_libraries(${t} PRIVATE dbghelp) + endforeach() endif() diff --git a/symtabAPI/doc/1-Intro.tex b/symtabAPI/doc/1-Intro.tex index c3078cc9ef..39fc2a6e2a 100644 --- a/symtabAPI/doc/1-Intro.tex +++ b/symtabAPI/doc/1-Intro.tex @@ -5,7 +5,7 @@ \section{Introduction} object file headers and debug information. SymtabAPI currently supports the ELF (IA-32, AMD-64, ARMv8-64, and POWER) and PE (Windows) object file formats. In addition, it also supports the DWARF -and stabs debugging formats. +debugging format. The main goal of this API is to provide an abstract view of binaries and libraries across multiple platforms. An abstract interface provides two diff --git a/symtabAPI/doc/3-Examples.tex b/symtabAPI/doc/3-Examples.tex index 32292b48f3..35a281742f 100644 --- a/symtabAPI/doc/3-Examples.tex +++ b/symtabAPI/doc/3-Examples.tex @@ -56,17 +56,14 @@ \section{Simple Examples} using namespace Dyninst; using namespace SymtabAPI; -//Module for the symbol -Module *mod; - // obj represents a handle to a parsed object file. -// Lookup module handle for "DEFAULT_MODULE" -obj->findModuleByName(mod, "DEFAULT_MODULE"); +for(auto *m : obj->findModulesByName("/path/to/foo.c")) { -// Create a new function symbol -Variable *newVar = mod->createVariable("newIntVar", // Name of new variable + // Create a new function symbol + Variable *newVar = m->createVariable("newIntVar", // Name of new variable 0x12345, // Offset from data section sizeof(int)); // Size of symbol +} \end{lstlisting} SymtabAPI gives the ability to query type information present in the object file. Also, new user defined types can be added to SymtabAPI. The following example shows both how to query type information after an object file is successfully parsed and also add a new structure type. diff --git a/symtabAPI/doc/4-Definitions.tex b/symtabAPI/doc/4-Definitions.tex index 85600d40fe..d638d9a199 100644 --- a/symtabAPI/doc/4-Definitions.tex +++ b/symtabAPI/doc/4-Definitions.tex @@ -20,18 +20,18 @@ \subsection{Definitions} \item[Mangled Name] A mangled name for a symbol provides a way of encoding additional information about a function, structure, class or another data type in a symbol name. It is a technique used to produce unique names for programming entities in many modern programming languages. For example, the method \emph{foo} of class C with signature \emph{int C::foo(int, int)} has a mangled name \emph{\_ZN1C3fooEii} when compiled with gcc. -Mangled names may include a sequence of clone suffixes (begins with `.' that indicate a compiler synthesized function), and this may be followed by a version suffix (begins with `@') or stabs type information (begins with `:'). +Mangled names may include a sequence of clone suffixes (begins with `.' that indicate a compiler synthesized function), and this may be followed by a version suffix (begins with `@'). \item[Pretty Name] A pretty name for a symbol is the demangled user-level symbolic name without type information for the function parameters and return types. For non-mangled names, the pretty name is the symbol name. Any function clone suffixes of the symbol are appended to the result of the demangler. For example, a symbol with a mangled name \emph{\_ZN1C3fooEii} for the method \emph{int C::foo(int, int)} has a pretty name \emph{C::foo}. -Version and stabs suffixes are removed from the mangled name before conversion to the pretty name. +Version suffixes are removed from the mangled name before conversion to the pretty name. The pretty name can be obtained by running the command line tool \code{c++filt} as \code{c++filt -i -p \emph{name}}, or using the libiberty library function \code{cplus\_demangle} with options of \code{DMGL\_AUTO | DMGL\_ANSI}. \item[Typed Name] A typed name for a symbol is the demangled user-level symbolic name including type information for the function parameters. Typically, but not always, function return type information is not included. Any function clone information is also included. For non-mangled names, the typed name is the symbol name. For example, a symbol with a mangled name \emph{\_ZN1C3fooEii} for the method \emph{int C::foo(int, int)} has a typed name \emph{C::foo(int, int)}. -Version and stabs suffixes are removed from the mangled name before conversion to the typed name. +Version suffixes are removed from the mangled name before conversion to the typed name. The typed name can be obtained by running the command line tool \code{c++filt} as \code{c++filt -i \emph{name}}, or using the libiberty library function \code{cplus\_demangle} with options of \code{DMGL\_AUTO | DMGL\_ANSI | DMGL\_PARAMS}. \item[Symbol Linkage] The symbol linkage for a symbol gives information on the visibility (binding) of this symbol, whether it is visible only in the object file where it is defined (local), if it is visible to all the object files that are being linked (global), or if its a weak alias to a global symbol. \item[Symbol Type] Symbol type for a symbol represents the category of symbols to which it belongs. It can be a function symbol or a variable symbol or a module symbol. diff --git a/symtabAPI/doc/API/LineInfo/Iterating.tex b/symtabAPI/doc/API/LineInfo/Iterating.tex index 17164b4f6e..93810dcee0 100644 --- a/symtabAPI/doc/API/LineInfo/Iterating.tex +++ b/symtabAPI/doc/API/LineInfo/Iterating.tex @@ -11,19 +11,20 @@ \subsection{Iterating over Line Information}\label{subsec:LineNoIterating} Module *mod; //Find the module \lq foo\rq within the object. -obj->findModuleByName(mod, "foo"); +for(auto *m : findModulesByName("foo")) { -// Get the Line Information for module foo. -LineInformation *info = mod->getLineInformation(); - -//Iterate over the line information -LineInformation::const_iterator iter; -for( iter = info->begin(); iter != info->end(); iter++) -{ -// First component represents the address range for the line -const std::pair addrRange = iter->first; - -//Second component gives information about the line itself. -LineNoTuple lt = iter->second; + // Get the Line Information for module foo. + LineInformation *info = m->getLineInformation(); + + //Iterate over the line information + LineInformation::const_iterator iter; + for( iter = info->begin(); iter != info->end(); iter++) + { + // First component represents the address range for the line + const std::pair addrRange = iter->first; + + //Second component gives information about the line itself. + LineNoTuple lt = iter->second; + } } \end{lstlisting} diff --git a/symtabAPI/doc/API/LineInfo/LineInformation.tex b/symtabAPI/doc/API/LineInfo/LineInformation.tex index 13154ebc1a..4ad42f3291 100644 --- a/symtabAPI/doc/API/LineInfo/LineInformation.tex +++ b/symtabAPI/doc/API/LineInfo/LineInformation.tex @@ -24,7 +24,7 @@ \subsection{Class LineInformation}\label{LineInformation} } \begin{apient} -bool addLine(const char * lineSource, +bool addLine(const std::string & lineSource, unsigned int lineNo, unsigned int lineOffset, Offset lowInclusiveAddr, diff --git a/symtabAPI/doc/API/Symtab/Function.tex b/symtabAPI/doc/API/Symtab/Function.tex index b739fdacfa..3afd1eb8d5 100644 --- a/symtabAPI/doc/API/Symtab/Function.tex +++ b/symtabAPI/doc/API/Symtab/Function.tex @@ -108,12 +108,3 @@ \subsection{Class Function}\label{Function} This method returns a list of local variables within a function that have name \code{name}. \code{vars} contains the list of variables found. Returns \code{true} on success and \code{false} on failure. } - - - -\begin{apient} -bool setReturnType(Type *type) -\end{apient} -\apidesc{ -Sets the return type of a function to \code{type}. -} diff --git a/symtabAPI/doc/API/Symtab/FunctionBase.tex b/symtabAPI/doc/API/Symtab/FunctionBase.tex index b2e21136c3..e451b2df55 100644 --- a/symtabAPI/doc/API/Symtab/FunctionBase.tex +++ b/symtabAPI/doc/API/Symtab/FunctionBase.tex @@ -95,15 +95,6 @@ \subsection{Class FunctionBase}\label{FunctionBase} Returns \code{true} on success and \code{false} on failure. } - - -\begin{apient} -bool setReturnType(Type *type) -\end{apient} -\apidesc{ -Sets the return type of a function to \code{type}. -} - \begin{apient} FunctionBase* getInlinedParent() \end{apient} diff --git a/symtabAPI/doc/API/Symtab/Module.tex b/symtabAPI/doc/API/Symtab/Module.tex index 30424305ca..f367cf2fc8 100644 --- a/symtabAPI/doc/API/Symtab/Module.tex +++ b/symtabAPI/doc/API/Symtab/Module.tex @@ -28,23 +28,12 @@ \subsection{Class Module}\label{Module} language & supportedLanguages & The source language used by the Module. \\ addr & Offset & Offset of the start of the module, as reported by the symbol table, assuming contiguous modules. \\ exec & Symtab * & Symtab object that contains the module. \\ -hasLineInformation & bool & True if the module has line information. \\ \bottomrule \end{tabular} \subsubsection{Function, Variable, Symbol lookup} -\begin{apient} -bool findFunctionByEntryOffset(Function *&ret, - const Offset offset) -\end{apient} -\apidesc{ -This method returns the \code{Function} object that begins at \code{offset}. Returns \code{true} on -success and \code{false} if there is no matching function. The error value is set to -\code{No\_Such\_Function}. -} - \begin{apient} typedef enum { mangledName, @@ -54,25 +43,11 @@ \subsubsection{Function, Variable, Symbol lookup} } NameType; \end{apient} -\begin{apient} -bool findFunctionsByName(vector &ret, - const string name, - Symtab::NameType nameType = anyName, - bool isRegex = false, - bool checkCase = true) -\end{apient} -\apidesc{ -This method finds and returns a vector of \code{Functions} whose names match the given pattern. The \code{nameType} parameter determines which names are searched: mangled, pretty, typed, or any. If the \code{isRegex} flag is set a regular expression match is performed with the symbol names. \code{checkCase} is applicable only if \code{isRegex} has been set. This indicates if the case be considered while performing regular expression matching. \code{ret} contains the list of matching \code{Function}s, if any. -Returns \code{true} if it finds functions that match the given name, otherwise returns -\code{false}. The error value is set to \code{No\_Such\_Function}. -} - \begin{apient} bool getAllFunctions(vector &ret) \end{apient} \apidesc{ -This method returns all functions in the object file. Returns \code{true} on success -and \code{false} if there are no modules. The error value is set to \code{No\_Such\_Function}. +Returns all functions located within the PC address ranges covered by this module. } \begin{apient} @@ -99,14 +74,6 @@ \subsubsection{Function, Variable, Symbol lookup} \code{false}. The error value is set to \code{No\_Such\_Variable}. } -\begin{apient} -bool getAllVariables(vector &ret) -\end{apient} -\apidesc{ -This method returns all variables in the object file. Returns \code{true} on success -and \code{false} if there are no modules. The error value is set to \code{No\_Such\_Variable}. -} - \begin{apient} bool getAllSymbols(vector &ret) \end{apient} diff --git a/symtabAPI/doc/API/Symtab/Region.tex b/symtabAPI/doc/API/Symtab/Region.tex index 912006a139..899e180754 100644 --- a/symtabAPI/doc/API/Symtab/Region.tex +++ b/symtabAPI/doc/API/Symtab/Region.tex @@ -31,6 +31,7 @@ \subsection{Class Region} RT\_SYMVERNEEDED & Versioning information for symbols \\ RT\_REL & Relocation section \\ RT\_RELA & Relocation section \\ +RT\_RELR & Relative relocation section \\ RT\_PLTREL & Relocation section for PLT (inter-library references) entries \\ RT\_PLTRELA & Relocation section for PLT (inter-library references) entries \\ RT\_DYNAMIC & Decription of library dependencies \\ diff --git a/symtabAPI/doc/API/Symtab/Symtab.tex b/symtabAPI/doc/API/Symtab/Symtab.tex index c7c3cedeea..c4bf5f1d3e 100644 --- a/symtabAPI/doc/API/Symtab/Symtab.tex +++ b/symtabAPI/doc/API/Symtab/Symtab.tex @@ -148,26 +148,33 @@ \subsubsection{File opening/parsing} \subsubsection{Module lookup} \begin{apient} -Module *getDefaultModule() +Module *getDefaultModule() const \end{apient} \apidesc{ Returns the default module, a collection of all functions, variables, and symbols that do not have an explicit module specified. } \begin{apient} -bool findModuleByName(Module *&ret, - const string name) +std::vector findModulesByName(std::string const& name) const \end{apient} \apidesc{ -This method searches for a module with name \code{name}. If the module exists returns \code{true} with \code{ret} set to the module handle; otherwise returns \code{false} with \code{ret} set to \code{NULL}. +Retrieve all modules with name \code{name}. } \begin{apient} -bool findModuleByOffset(Module *&ret, - Offset offset) +Module* findModuleByOffset(Offset offset) const \end{apient} \apidesc{ -This method searches for a module that starts at offset \code{offset}. If the module exists returns \code{true} with \code{ret} set to the module handle; otherwise returns \code{false} with \code{ret} set to \code{NULL}. +Returns the module starting at \code{offset}; \code{nullptr}, if not found. +} + +\begin{apient} +Module* getContainingModule(Offset offset) const +\end{apient} +\apidesc{ +Returns the module with PC ranges that contain \code{offset}; \code{nullptr}, if not found. +The default module will be returned if and only if it is the only module present. By contrast, +\code{findModuleByOffset}, finds a module \it{starting} at \code{offset}. } \begin{apient} @@ -554,29 +561,6 @@ \subsubsection{Line number information} Return \code{true} if at least one tuple corresponding to the offset was found and returns \code{false} if none found. } -\begin{apient} -bool addLine(string lineSource, - unsigned int lineNo, - unsigned int lineOffset, - Offset lowInclusiveAddr, - Offset highExclusiveAddr) -\end{apient} -\apidesc{ -This method adds a new line to the line map. \code{lineSource} represents the source file name. \code{lineNo} represents the line number. -Returns \code{true} on success and \code{false} on error. -} - -\begin{apient} -bool addAddressRange(Offset lowInclusiveAddr, - Offset highExclusiveAddr, - string lineSource, - unsigned int lineNo, - unsigned int lineOffset = 0); -\end{apient} -\apidesc{ -This method adds an address range \code{[lowInclusiveAddr, highExclusiveAddr)} for the line with line number \code{lineNo} in source file \code{lineSource} at offset \code{lineOffset}. -Returns \code{true} on success and \code{false} on error.} - \subsubsection{Type information} \begin{apient} diff --git a/symtabAPI/doc/API/Types/Type.tex b/symtabAPI/doc/API/Types/Type.tex index f9e3d272e3..dd9a28060b 100644 --- a/symtabAPI/doc/API/Types/Type.tex +++ b/symtabAPI/doc/API/Types/Type.tex @@ -165,7 +165,7 @@ \subsection{Class typeEnum} Symtab *obj) \end{apient} \apidesc{ -These factory methods create a new enumerated type. There are two variations to this function. \code{consts} supplies the names and Id’s of the constants of the enum. The first variant is used when user-defined identifiers are required; the second variant is used when system-defined identifiers will be used. +These factory methods create a new enumerated type. There are two variations to this function. \code{consts} supplies the names and Id's of the constants of the enum. The first variant is used when user-defined identifiers are required; the second variant is used when system-defined identifiers will be used. The newly created type is added to the \code{Symtab} object \code{obj}. If \code{obj} is \code{NULL} the type is not added to any object file, but it will be available for further queries. } diff --git a/symtabAPI/doc/symtabAPI.pdf b/symtabAPI/doc/symtabAPI.pdf index c92826d7bf..662b96ae16 100644 Binary files a/symtabAPI/doc/symtabAPI.pdf and b/symtabAPI/doc/symtabAPI.pdf differ diff --git a/symtabAPI/h/AddrLookup.h b/symtabAPI/h/AddrLookup.h index 917c358c82..9209febb1a 100644 --- a/symtabAPI/h/AddrLookup.h +++ b/symtabAPI/h/AddrLookup.h @@ -32,6 +32,8 @@ #define __AddrLookup_H__ #include "Annotatable.h" +#include +#include #include namespace Dyninst { diff --git a/symtabAPI/h/Aggregate.h b/symtabAPI/h/Aggregate.h index bcc9302528..da078ae4f5 100644 --- a/symtabAPI/h/Aggregate.h +++ b/symtabAPI/h/Aggregate.h @@ -39,11 +39,12 @@ #if !defined(_Aggregate_h_) #define _Aggregate_h_ +#include +#include #include #include "Annotatable.h" -#include +#include #include -#include "concurrent.h" namespace Dyninst{ namespace SymtabAPI{ @@ -86,7 +87,7 @@ class SYMTAB_EXPORT Aggregate //std::vector getAllMangledNames(); //std::vector getAllPrettyNames(); //std::vector getAllTypedNames(); - typedef boost::transform_iterator, std::vector::const_iterator> name_iter; + using name_iter = dyncompat::transform_iterator::const_iterator>; name_iter mangled_names_begin() const; name_iter mangled_names_end() const; name_iter pretty_names_begin() const; @@ -115,7 +116,6 @@ class SYMTAB_EXPORT Aggregate // Offset comes from a symbol // Module we keep here so we can have the correct "primary" - // (AKA 'not DEFAULT_MODULE') module Module *module_; mutable dyn_mutex lock_; diff --git a/symtabAPI/h/Archive.h b/symtabAPI/h/Archive.h index 2e33790c4a..e2ebfa572e 100644 --- a/symtabAPI/h/Archive.h +++ b/symtabAPI/h/Archive.h @@ -30,6 +30,11 @@ #ifndef __ARCHIVE_H__ #define __ARCHIVE_H__ + +#include +#include +#include +#include class MappedFile; diff --git a/symtabAPI/h/Collections.h b/symtabAPI/h/Collections.h index 55257a6854..0c1920de68 100644 --- a/symtabAPI/h/Collections.h +++ b/symtabAPI/h/Collections.h @@ -31,11 +31,15 @@ #ifndef _Collections_h_ #define _Collections_h_ +#include +#include +#include +#include #include "concurrent.h" #include "Type.h" #include "Variable.h" -#include -#include +#include +#include namespace Dyninst { @@ -82,9 +86,9 @@ class SYMTAB_EXPORT typeCollection friend class Type; friend class DwarfWalker; - dyn_c_hash_map> typesByName; - dyn_c_hash_map> globalVarsByName; - dyn_c_hash_map> typesByID; + dyn_c_hash_map> typesByName; + dyn_c_hash_map> globalVarsByName; + dyn_c_hash_map> typesByID; // DWARF: @@ -100,8 +104,8 @@ class SYMTAB_EXPORT typeCollection typeCollection(); ~typeCollection(); public: - static void addDeferredLookup(int, dataClass, boost::shared_ptr *); - static boost::mutex create_lock; + static void addDeferredLookup(int, dataClass, dyncompat::shared_ptr *); + static dyncompat::mutex create_lock; static typeCollection *getModTypeCollection(Module *mod); @@ -109,21 +113,21 @@ class SYMTAB_EXPORT typeCollection bool dwarfParsed() { return dwarfParsed_; } void setDwarfParsed() { dwarfParsed_ = true; } - boost::shared_ptr findType(std::string name, Type::do_share_t); + dyncompat::shared_ptr findType(std::string name, Type::do_share_t); Type* findType(std::string n) { return findType(n, Type::share).get(); } - boost::shared_ptr findType(const int ID, Type::do_share_t); + dyncompat::shared_ptr findType(const int ID, Type::do_share_t); Type* findType(const int i) { return findType(i, Type::share).get(); } - boost::shared_ptr findTypeLocal(std::string name, Type::do_share_t); + dyncompat::shared_ptr findTypeLocal(std::string name, Type::do_share_t); Type* findTypeLocal(std::string n) { return findTypeLocal(n, Type::share).get(); } - boost::shared_ptr findTypeLocal(const int ID, Type::do_share_t); + dyncompat::shared_ptr findTypeLocal(const int ID, Type::do_share_t); Type* findTypeLocal(const int i) { return findTypeLocal(i, Type::share).get(); } - void addType(boost::shared_ptr type); + void addType(dyncompat::shared_ptr type); void addType(Type* t) { addType(t->reshare()); } - void addType(boost::shared_ptr type, dyn_mutex::unique_lock&); + void addType(dyncompat::shared_ptr type, dyn_mutex::unique_lock&); void addType(Type* t, dyn_mutex::unique_lock& g) { addType(t->reshare(), g); } - void addGlobalVariable(boost::shared_ptr type); + void addGlobalVariable(dyncompat::shared_ptr type); void addGlobalVariable(Type* t) { addGlobalVariable(t->reshare()); } @@ -131,33 +135,33 @@ class SYMTAB_EXPORT typeCollection /* Some debug formats allow forward references. Rather than fill in forward in a second pass, generate placeholder types, and fill them in as we go. Because we require - One True Pointer for each type (in parseStab.C), when + One True Pointer for each type, when updating a type, return that One True Pointer. */ - boost::shared_ptr findOrCreateType( const int ID, Type::do_share_t ); + dyncompat::shared_ptr findOrCreateType( const int ID, Type::do_share_t ); Type* findOrCreateType(const int i) { return findOrCreateType(i, Type::share).get(); } template - typename boost::enable_if< - boost::integral_constant::value)>, - boost::shared_ptr>::type addOrUpdateType(boost::shared_ptr type); + typename std::enable_if< + !std::is_same::value, + dyncompat::shared_ptr>::type addOrUpdateType(dyncompat::shared_ptr type); template T* addOrUpdateType(T* t) { - return &dynamic_cast(*addOrUpdateType(boost::dynamic_pointer_cast(t->reshare()))); + return &dynamic_cast(*addOrUpdateType(dyncompat::dynamic_pointer_cast(t->reshare()))); } - boost::shared_ptr findVariableType(std::string &name, Type::do_share_t); + dyncompat::shared_ptr findVariableType(std::string &name, Type::do_share_t); Type* findVariableType(std::string& n) { return findVariableType(n, Type::share).get(); } - void getAllTypes(std::vector>&); + void getAllTypes(std::vector>&); std::vector* getAllTypes() { - std::vector> v; + std::vector> v; getAllTypes(v); auto r = new std::vector(v.size()); for(std::size_t i = 0; i < v.size(); i++) (*r)[i] = v[i].get(); return r; } - void getAllGlobalVariables(std::vector>>&); + void getAllGlobalVariables(std::vector>>&); std::vector>* getAllGlobalVariables() { - std::vector>> v; + std::vector>> v; getAllGlobalVariables(v); auto r = new std::vector>(v.size()); for(std::size_t i = 0; i < v.size(); i++) @@ -179,22 +183,22 @@ class SYMTAB_EXPORT typeCollection class SYMTAB_EXPORT builtInTypeCollection { - dyn_c_hash_map> builtInTypesByID; - dyn_c_hash_map> builtInTypesByName; + dyn_c_hash_map> builtInTypesByID; + dyn_c_hash_map> builtInTypesByName; public: builtInTypeCollection(); ~builtInTypeCollection(); - boost::shared_ptr findBuiltInType(std::string &name, Type::do_share_t); + dyncompat::shared_ptr findBuiltInType(std::string &name, Type::do_share_t); Type* findBuiltInType(std::string& n) { return findBuiltInType(n, Type::share).get(); } - boost::shared_ptr findBuiltInType(const int ID, Type::do_share_t); + dyncompat::shared_ptr findBuiltInType(const int ID, Type::do_share_t); Type* findBuiltInType(const int i) { return findBuiltInType(i, Type::share).get(); } - void addBuiltInType(boost::shared_ptr); + void addBuiltInType(dyncompat::shared_ptr); void addBuiltInType(Type* t) { addBuiltInType(t->reshare()); } - void getAllBuiltInTypes(std::vector>&); + void getAllBuiltInTypes(std::vector>&); std::vector* getAllBuiltInTypes() { - std::vector> v; + std::vector> v; getAllBuiltInTypes(v); auto r = new std::vector(v.size()); for(std::size_t i = 0; i < v.size(); i++) (*r)[i] = v[i].get(); diff --git a/symtabAPI/h/ExceptionBlock.h b/symtabAPI/h/ExceptionBlock.h new file mode 100644 index 0000000000..21f9b4966f --- /dev/null +++ b/symtabAPI/h/ExceptionBlock.h @@ -0,0 +1,111 @@ +/* + * See the dyninst/COPYRIGHT file for copyright information. + * + * We provide the Paradyn Tools (below described as "Paradyn") + * on an AS IS basis, and do not warrant its validity or performance. + * We reserve the right to update, modify, or discontinue this + * software at any time. We shall have no obligation to supply such + * updates or modifications or any other form of support to you. + * + * By your use of Paradyn, you understand and agree that we (or any + * other person or entity with proprietary rights in Paradyn) are + * under no obligation to provide either maintenance services, + * update services, notices of latent defects, or correction of + * defects for Paradyn. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __EXCEPTIONBLOCK_H__ +#define __EXCEPTIONBLOCK_H__ + +#include + +#include "util.h" +#include "dyntypes.h" +#include "Annotatable.h" + + +namespace Dyninst { + +namespace SymtabAPI { + + +/** + * Used to represent something like a C++ try/catch block. + * Currently only used on Linux + **/ + +class SYMTAB_EXPORT ExceptionBlock : public AnnotatableSparse { + // Accessors provide consistent access to the *original* offsets. + // We allow this to be updated (e.g. to account for relocated code + public: + ExceptionBlock(Offset tStart, unsigned tSize, Offset cStart); + ExceptionBlock(Offset cStart); + SYMTAB_EXPORT ExceptionBlock(const ExceptionBlock &eb) = default; + SYMTAB_EXPORT ~ExceptionBlock() = default; + SYMTAB_EXPORT ExceptionBlock() = default; + SYMTAB_EXPORT ExceptionBlock& operator=(const ExceptionBlock &eb) = default; + + bool hasTry() const; + Offset tryStart() const; + Offset tryEnd() const; + Offset trySize() const; + Offset catchStart() const; + bool contains(Offset a) const; + void setTryStart(Offset ts) + { + tryStart_ptr = ts; + } + void setTryEnd(Offset te) + { + tryEnd_ptr = te; + } + + void setCatchStart(Offset cs) + { + catchStart_ptr = cs; + } + + void setFdeStart(Offset fs) + { + fdeStart_ptr = fs; + } + + void setFdeEnd(Offset fe) + { + fdeEnd_ptr = fe; + } + + + friend SYMTAB_EXPORT std::ostream &operator<<(std::ostream &os, const ExceptionBlock &q); + private: + Offset tryStart_{}; + unsigned trySize_{}; + Offset catchStart_{}; + bool hasTry_{}; + Offset tryStart_ptr{}; + Offset tryEnd_ptr{}; + Offset catchStart_ptr{}; + Offset fdeStart_ptr{}; + Offset fdeEnd_ptr{}; +}; + +SYMTAB_EXPORT std::ostream &operator<<(std::ostream &os, const ExceptionBlock &q); + +}//namespace SymtabAPI + +}//namespace Dyninst +#endif diff --git a/symtabAPI/h/Function.h b/symtabAPI/h/Function.h index 231db3ea23..9c6479d733 100644 --- a/symtabAPI/h/Function.h +++ b/symtabAPI/h/Function.h @@ -36,11 +36,15 @@ #if !defined(_Function_h_) #define _Function_h_ +#include +#include +#include +#include +#include #include "Annotatable.h" #include "Aggregate.h" #include "Variable.h" -#include "IBSTree.h" -#include "concurrent.h" +#include "VariableLocation.h" SYMTAB_EXPORT std::ostream &operator<<(std::ostream &os, const Dyninst::SymtabAPI::Function &); @@ -71,10 +75,8 @@ class SYMTAB_EXPORT FuncRange { typedef Dyninst::Offset type; }; -typedef IBSTree FuncRangeLookup; typedef std::vector FuncRangeCollection; typedef std::vector InlineCollection; -typedef std::vector FuncRangeCollection; class SYMTAB_EXPORT FunctionBase { @@ -83,8 +85,7 @@ class SYMTAB_EXPORT FunctionBase friend class DwarfWalker; public: /***** Return Type Information *****/ - dyn_mutex ret_lock; - boost::shared_ptr getReturnType(Type::do_share_t) const; + dyncompat::shared_ptr getReturnType(Type::do_share_t) const; Type* getReturnType() const { return getReturnType(Type::share).get(); } @@ -119,30 +120,27 @@ class SYMTAB_EXPORT FunctionBase /* internal helper functions */ bool addLocalVar(localVar *); bool addParam(localVar *); - bool setReturnType(boost::shared_ptr); - bool setReturnType(Type* t) { return setReturnType(t->reshare()); } + bool setReturnType(dyncompat::shared_ptr); virtual Offset getOffset() const = 0; virtual unsigned getSize() const = 0; virtual Module* getModule() const = 0; + virtual ~FunctionBase(); + protected: - FunctionBase(Symbol *); - FunctionBase(Module *); FunctionBase(); - virtual ~FunctionBase(); localVarCollection *locals; localVarCollection *params; mutable unsigned functionSize_; - boost::shared_ptr retType_; + dyncompat::shared_ptr retType_; dyn_mutex inlines_lock; InlineCollection inlines; FunctionBase *inline_parent; - dyn_mutex ranges_lock; FuncRangeCollection ranges; std::vector frameBase_; dyn_mutex frameBaseLock_; @@ -152,21 +150,22 @@ class SYMTAB_EXPORT FunctionBase std::vector &ret); }; +/* + * `Function` can be derived from (e.g., ParseAPI::PLTFunction), but does not create an + * interface separate from FunctionBase. + */ class SYMTAB_EXPORT Function : public FunctionBase, public Aggregate { - friend class Symtab; friend std::ostream &::operator<<(std::ostream &os, const Dyninst::SymtabAPI::Function &); - protected: - Function(Symbol *sym); - public: Function(); + Function(Symbol *sym); virtual ~Function(); /* Symbol management */ - bool removeSymbol(Symbol *sym); + bool removeSymbol(Symbol *sym) override; /***** IA64-Specific Frame Pointer Information *****/ bool setFramePtrRegnum(int regnum); @@ -176,35 +175,36 @@ class SYMTAB_EXPORT FunctionBase Offset getPtrOffset() const; Offset getTOCOffset() const; - virtual unsigned getSymbolSize() const; - virtual unsigned getSize() const; - virtual std::string getName() const; - virtual Offset getOffset() const { return Aggregate::getOffset(); } - virtual bool addMangledName(std::string name, bool isPrimary, bool isDebug=false) + unsigned getSymbolSize() const; + unsigned getSize() const override; + std::string getName() const override; + Offset getOffset() const override { return Aggregate::getOffset(); } + bool addMangledName(std::string name, bool isPrimary, bool isDebug=false) override {return Aggregate::addMangledName(name, isPrimary, isDebug);} - virtual bool addPrettyName(std::string name, bool isPrimary, bool isDebug=false) + bool addPrettyName(std::string name, bool isPrimary, bool isDebug=false) override {return Aggregate::addPrettyName(name, isPrimary, isDebug);} - virtual Module * getModule() const; + Module * getModule() const override; }; class SYMTAB_EXPORT InlinedFunction : public FunctionBase { friend class Symtab; friend class DwarfWalker; - protected: - InlinedFunction(FunctionBase *parent); - ~InlinedFunction(); - virtual Module* getModule() const { return module_; } + friend class Object; public: + InlinedFunction(FunctionBase *parent); + virtual ~InlinedFunction(); + + Module* getModule() const override { return module_; } typedef std::vector::const_iterator name_iter; std::pair getCallsite(); - virtual bool removeSymbol(Symbol *sym); - virtual bool addMangledName(std::string name, bool isPrimary, bool isDebug=false); - virtual bool addPrettyName(std::string name, bool isPrimary, bool isDebug=false); - virtual std::string getName() const; - virtual Offset getOffset() const; - virtual unsigned getSize() const; + bool removeSymbol(Symbol *sym); + bool addMangledName(std::string name, bool isPrimary, bool isDebug=false) override; + bool addPrettyName(std::string name, bool isPrimary, bool isDebug=false) override; + std::string getName() const override; + Offset getOffset() const override; + unsigned getSize() const override; void setFile(std::string filename); private: size_t callsite_file_number; diff --git a/symtabAPI/h/LineInformation.h b/symtabAPI/h/LineInformation.h index 5bbfcb7804..9e4ad9faf0 100644 --- a/symtabAPI/h/LineInformation.h +++ b/symtabAPI/h/LineInformation.h @@ -31,29 +31,50 @@ #if ! defined( LINE_INFORMATION_H ) #define LINE_INFORMATION_H +#include +#include +#include +#include +#include #include "symutil.h" -#include "RangeLookup.h" #include "Annotatable.h" -#include "Module.h" +#include "RangeLookup.h" +#include "Statement.h" #define NEW_GETSOURCELINES_INTERFACE namespace Dyninst{ namespace SymtabAPI{ -class SYMTAB_EXPORT LineInformation : - private RangeLookupTypes< Statement >::type -{ +class SYMTAB_EXPORT LineInformation final { +public: + typedef Statement::Ptr Statement_t; + +private: + struct StatementAddrLess { + bool operator()(Statement::Ptr lhs, Statement::Ptr rhs) const; + }; + + struct LineInfoKey { + unsigned int file_index{}; + unsigned int line{}; + }; + + struct LineInfoKeyLess { + bool operator()(const LineInfoKey &lhs, const LineInfoKey &rhs) const; + }; + + using addr_index_t = std::set; + using line_index_t = std::multimap; + using upper_bound_index_t = std::multimap; + public: - typedef RangeLookupTypes< Statement> traits; - typedef RangeLookupTypes< Statement >::type impl_t; - typedef impl_t::index::type::const_iterator const_iterator; - typedef impl_t::index::type::const_iterator const_line_info_iterator; - typedef traits::value_type Statement_t; + typedef addr_index_t::const_iterator const_iterator; + typedef line_index_t::const_iterator const_line_info_iterator; + LineInformation(); - /* You MAY freely deallocate the lineSource strings you pass in. */ - bool addLine( std::string lineSource, + bool addLine( const std::string &lineSource, unsigned int lineNo, unsigned int lineOffset, Offset lowInclusiveAddr, @@ -72,16 +93,15 @@ class SYMTAB_EXPORT LineInformation : unsigned int lineNo, unsigned int lineOffset = 0 ); - /* You MUST NOT deallocate the strings returned. */ bool getSourceLines(Offset addressInRange, std::vector &lines); bool getSourceLines(Offset addressInRange, std::vector &lines); bool getAddressRanges( const char * lineSource, unsigned int LineNo, std::vector< AddressRange > & ranges ); const_line_info_iterator begin_by_source() const; const_line_info_iterator end_by_source() const; - std::pair range(std::string file, + std::pair range(std::string const& file, const unsigned int lineNo) const; - std::pair equal_range(std::string file) const; + std::pair equal_range(std::string const& file) const; const_iterator begin() const; const_iterator end() const; const_iterator find(Offset addressInRange) const; @@ -91,21 +111,29 @@ class SYMTAB_EXPORT LineInformation : void dump(); - virtual ~LineInformation(); + ~LineInformation() = default; StringTablePtr strings_; - protected: -public: + StringTablePtr getStrings() ; void setStrings(StringTablePtr strings_); -protected: - mutable int wasted_compares; - mutable int num_queries; -}; +private: + std::pair insert(Statement::Ptr statement); + + template + void insert(Iterator first, Iterator last) { + for (; first != last; ++first) { + insert(*first); + } + } + static LineInfoKey make_key(unsigned int file_index, unsigned int line_no); - /* end class LineInformation */ + addr_index_t by_addr_; + line_index_t by_line_; + upper_bound_index_t by_end_; +}; }//namespace SymtabAPI }//namespace Dyninst diff --git a/symtabAPI/h/Module.h b/symtabAPI/h/Module.h index 23ce8a4f0e..dd8bafd691 100644 --- a/symtabAPI/h/Module.h +++ b/symtabAPI/h/Module.h @@ -1,28 +1,28 @@ /* * See the dyninst/COPYRIGHT file for copyright information. - * + * * We provide the Paradyn Tools (below described as "Paradyn") * on an AS IS basis, and do not warrant its validity or performance. * We reserve the right to update, modify, or discontinue this * software at any time. We shall have no obligation to supply such * updates or modifications or any other form of support to you. - * + * * By your use of Paradyn, you understand and agree that we (or any * other person or entity with proprietary rights in Paradyn) are * under no obligation to provide either maintenance services, * update services, notices of latent defects, or correction of * defects for Paradyn. - * + * * This library is free software; you can redistribute it and/or * modify it under the terms of the GNU Lesser General Public * License as published by the Free Software Foundation; either * version 2.1 of the License, or (at your option) any later version. - * + * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU * Lesser General Public License for more details. - * + * * You should have received a copy of the GNU Lesser General Public * License along with this library; if not, write to the Free Software * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA @@ -31,288 +31,174 @@ #ifndef __MODULE__H__ #define __MODULE__H__ -#include "symutil.h" -#include "Symbol.h" - #include "Annotatable.h" -#include "IBSTree.h" -#include "IBSTree-fast.h" -#if defined(cap_dwarf) -#include "elfutils/libdw.h" -#endif -#include #include "RangeLookup.h" +#include "Statement.h" +#include "Symbol.h" -#include "StringTable.h" - -namespace Dyninst{ - namespace SymtabAPI{ - - class typeCollection; - class LineInformation; - class localVar; - class Symtab; - - - class SYMTAB_EXPORT Statement : public AddressRange - { - friend class Module; - friend class LineInformation; - Statement(int file_index, unsigned int line, unsigned int col = 0, - Offset start_addr = (Offset) -1L, Offset end_addr = (Offset) -1L) : - AddressRange(start_addr, end_addr), - file_index_(file_index), - line_(line), - column_(col) - { - } - - unsigned int file_index_; // Maybe this should be module? - unsigned int line_; - unsigned int column_; - StringTablePtr strings_; - public: - StringTablePtr getStrings_() const; - - void setStrings_(StringTablePtr strings_); - - public: - - Statement() : AddressRange(0,0), file_index_(0), line_(0), column_(0) {} - struct StatementLess { - bool operator () ( const Statement &lhs, const Statement &rhs ) const; - }; - - typedef StatementLess LineNoTupleLess; - bool operator==(const Statement &cmp) const; - bool operator==(Offset addr) const { - return AddressRange::contains(addr); - } - bool operator<(Offset addr) const { - return startAddr() <= addr; - } - bool operator>(Offset addr) const { - return !((*this) < addr || (*this == addr)); - } - ~Statement() {} - - Offset startAddr() const { return first;} - Offset endAddr() const {return second;} - const std::string& getFile() const; - unsigned int getFileIndex() const { return file_index_; } - unsigned int getLine()const {return line_;} - unsigned int getColumn() const { return column_; } - struct addr_range {}; - struct line_info {}; - struct upper_bound {}; - - typedef Statement* Ptr; - typedef const Statement* ConstPtr; - - }; - template - OS& operator<<(OS& os, const Statement& s) - { - os << ": [" << std::hex << s.startAddr() << ", " << s.endAddr() << std::dec << ") @ " << s.getFile() - << " (" << s.getFileIndex() << "): " << s.getLine(); - return os; - } - template - OS& operator<<(OS& os, Statement* s) - { - os << ": [" << std::hex << s->startAddr() << ", " << s->endAddr() << std::dec << ") @ " << s->getFile() - << " (" << s->getFileIndex() << "): " << s->getLine(); - return os; - } - - - typedef Statement LineNoTuple; -#define MODULE_ANNOTATABLE_CLASS AnnotatableSparse - - class SYMTAB_EXPORT Module : public LookupInterface - { - friend class Symtab; - - public: -#if defined(cap_dwarf) - typedef Dwarf_Die DebugInfoT; -#else - typedef void* DebugInfoT; -#endif +#include +#include +#include +#include +#include + +namespace Dyninst { namespace SymtabAPI { + + class typeCollection; + class LineInformation; + class localVar; + class Symtab; + + typedef Dyninst::SimpleInterval ModRange; + + class SYMTAB_EXPORT Module : public LookupInterface { + friend class Symtab; + + public: + Module(); + Module(supportedLanguages lang, Offset adr, std::string fullNm, Symtab *img); + Module(const Module &mod); + bool operator==(Module &mod); + + const std::string &fileName() const; + const std::string &fullName() const; - Module(); - Module(supportedLanguages lang, Offset adr, std::string fullNm, - Symtab *img); - Module(const Module &mod); - bool operator==(Module &mod); - - const std::string &fileName() const; - const std::string &fullName() const; - bool setName(std::string newName); - - supportedLanguages language() const; - void setLanguage(supportedLanguages lang); - - Offset addr() const; - Symtab *exec() const; - - bool isShared() const; - ~Module(); - - std::string getCompDir(); - std::string getCompDir(Module::DebugInfoT&); // For internal use - - // Symbol output methods - virtual bool findSymbol(std::vector &ret, - const std::string& name, - Symbol::SymbolType sType = Symbol::ST_UNKNOWN, - NameType nameType = anyName, - bool isRegex = false, - bool checkCase = false, - bool includeUndefined = false); - virtual bool getAllSymbolsByType(std::vector &ret, - Symbol::SymbolType sType); - virtual bool getAllSymbols(std::vector &ret); - - - // Function based methods - bool getAllFunctions(std::vector&ret); - bool findFunctionByEntryOffset(Function *&ret, const Offset offset); - bool findFunctionsByName(std::vector &ret, const std::string& name, - NameType nameType = anyName, - bool isRegex = false, - bool checkCase = true); - - // Variable based methods - bool findVariablesByOffset(std::vector &ret, const Offset offset); - bool findVariablesByName(std::vector &ret, const std::string& name, - NameType nameType = anyName, - bool isRegex = false, - bool checkCase = true); - - // Type output methods - virtual bool findType(boost::shared_ptr& type, std::string name); - bool findType(Type*& t, std::string n) { - boost::shared_ptr tp; - auto r = findType(tp, n); - t = tp.get(); - return r; - } - virtual bool findVariableType(boost::shared_ptr& type, std::string name); - bool findVariableType(Type*& t, std::string n) { - boost::shared_ptr tp; - auto r = findVariableType(tp, n); - t = tp.get(); - return r; - } - - void getAllTypes(std::vector>&); - std::vector* getAllTypes() { - std::vector> v; - getAllTypes(v); - auto r = new std::vector(v.size()); - for(std::size_t i = 0; i < v.size(); i++) (*r)[i] = v[i].get(); - return r; - } - void getAllGlobalVars(std::vector>>&); - std::vector>* getAllGlobalVars() { - std::vector>> v; - getAllGlobalVars(v); - auto r = new std::vector>(v.size()); - for(std::size_t i = 0; i < v.size(); i++) - (*r)[i] = {v[i].first, v[i].second.get()}; - return r; - } - - typeCollection *getModuleTypes(); - - /***** Local Variable Information *****/ - bool findLocalVariable(std::vector&vars, std::string name); - - /***** Line Number Information *****/ - bool getAddressRanges(std::vector&ranges, - std::string lineSource, unsigned int LineNo); - bool getSourceLines(std::vector &lines, - Offset addressInRange); - bool getSourceLines(std::vector &lines, - Offset addressInRange); - bool getStatements(std::vector &statements); - LineInformation *getLineInformation(); - LineInformation* parseLineInformation(); - - bool setDefaultNamespacePrefix(std::string str); - - - // Super secret private methods that aren't really private - typeCollection *getModuleTypesPrivate(); - void setModuleTypes(typeCollection* tc) - { - typeInfo_ = tc; - } - - bool setLineInfo(Dyninst::SymtabAPI::LineInformation *lineInfo); - void addRange(Dyninst::Address low, Dyninst::Address high); - bool hasRanges() const { return !ranges.empty() || ranges_finalized; } - void addDebugInfo(Module::DebugInfoT info); - - void finalizeRanges(); - - private: - bool objectLevelLineInfo; - Dyninst::SymtabAPI::LineInformation* lineInfo_; - typeCollection* typeInfo_; - dyn_c_queue info_; - - - std::string fileName_; // short file - std::string fullName_; // full path to file - std::string compDir_; - supportedLanguages language_; - Offset addr_; // starting address of module - Symtab *exec_; - std::set ranges; - - StringTablePtr strings_; - public: - StringTablePtr & getStrings() ; - - private: - bool ranges_finalized; - - void finalizeOneRange(Address ext_s, Address ext_e) const; - }; - template - OS& operator<<(OS& os, const Module& m) - { - os << m.fileName() << ": " << m.addr(); - return os; - } - template - OS& operator<<(OS& os, Module* m) - { - os << m->fileName() << ": " << m->addr(); - return os; - } - - typedef Dyninst::SimpleInterval ModRange; - - inline bool operator==(Offset off, const ModRange& r) { - return (r.low() <= off) && (off < r.high()); - } - inline bool operator==(const ModRange& r, Offset off) { - return off == r; - } - template - OS& operator<<(OS& os, const ModRange& m) - { - os << m.id() << ": [" << m.low() << ", " << m.high() << ")"; - return os; - } - - - }//namespace SymtabAPI - -}//namespace Dyninst + supportedLanguages language() const; + void setLanguage(supportedLanguages lang); + Offset addr() const; + Symtab *exec() const; + + bool isShared() const; + ~Module(); + + // Symbol output methods + virtual bool findSymbol(std::vector &ret, const std::string &name, + Symbol::SymbolType sType = Symbol::ST_UNKNOWN, + NameType nameType = anyName, bool isRegex = false, + bool checkCase = false, bool includeUndefined = false); + virtual bool getAllSymbolsByType(std::vector &ret, Symbol::SymbolType sType); + virtual bool getAllSymbols(std::vector &ret); + + // Function based methods + std::vector getAllFunctions() const; + + // Variable based methods + bool findVariablesByOffset(std::vector &ret, const Offset offset); + bool findVariablesByName(std::vector &ret, const std::string &name, + NameType nameType = anyName, bool isRegex = false, + bool checkCase = true); + + // Type output methods + virtual bool findType(dyncompat::shared_ptr &type, std::string name); + + bool findType(Type *&t, std::string n) { + dyncompat::shared_ptr tp; + auto r = findType(tp, n); + t = tp.get(); + return r; + } + + virtual bool findVariableType(dyncompat::shared_ptr &type, std::string name); + + bool findVariableType(Type *&t, std::string n) { + dyncompat::shared_ptr tp; + auto r = findVariableType(tp, n); + t = tp.get(); + return r; + } + + void getAllTypes(std::vector> &); + + std::vector *getAllTypes() { + std::vector> v; + getAllTypes(v); + auto r = new std::vector(v.size()); + for (std::size_t i = 0; i < v.size(); i++) + (*r)[i] = v[i].get(); + return r; + } + + void getAllGlobalVars(std::vector>> &); + + std::vector> *getAllGlobalVars() { + std::vector>> v; + getAllGlobalVars(v); + auto r = new std::vector>(v.size()); + for (std::size_t i = 0; i < v.size(); i++) + (*r)[i] = {v[i].first, v[i].second.get()}; + return r; + } + + typeCollection *getModuleTypes(); + + /***** Local Variable Information *****/ + bool findLocalVariable(std::vector &vars, std::string name); + + /***** Line Number Information *****/ + bool getAddressRanges(std::vector &ranges, std::string lineSource, + unsigned int LineNo); + bool getSourceLines(std::vector &lines, Offset addressInRange); + bool getSourceLines(std::vector &lines, Offset addressInRange); + bool getStatements(std::vector &statements); + LineInformation *getLineInformation(); + LineInformation *parseLineInformation(); + + bool setDefaultNamespacePrefix(std::string str); + + // Super secret private methods that aren't really private + typeCollection *getModuleTypesPrivate(); + + void setModuleTypes(typeCollection *tc) { typeInfo_ = tc; } + + bool setLineInfo(Dyninst::SymtabAPI::LineInformation *lineInfo); + void addRange(Dyninst::Address low, Dyninst::Address high); + + bool hasRanges() const { return !ranges.empty(); } + + StringTablePtr &getStrings(); + + private: + bool objectLevelLineInfo; + Dyninst::SymtabAPI::LineInformation *lineInfo_; + typeCollection *typeInfo_; + + std::string fileName_; // full path to file + std::string compDir_; + supportedLanguages language_; + Offset addr_; // starting address of module + Symtab *exec_; + std::set ranges; + std::vector finalizeRanges(); + + StringTablePtr strings_; + }; + + template OS &operator<<(OS &os, const Module &m) { + os << m.fileName() << ": " << m.addr(); + return os; + } + + template OS &operator<<(OS &os, Module *m) { + if (m) { + os << m->fileName() << ": " << m->addr(); + } else { + os << "null"; + } + return os; + } + + inline bool operator==(Offset off, const ModRange &r) { + return (r.low() <= off) && (off < r.high()); + } + + inline bool operator==(const ModRange &r, Offset off) { return off == r; } + + template OS &operator<<(OS &os, const ModRange &m) { + os << m.id() << ": [" << m.low() << ", " << m.high() << ")"; + return os; + } + +}} #endif diff --git a/symtabAPI/h/RangeLookup.h b/symtabAPI/h/RangeLookup.h index bf54f0d2a8..436614a4cf 100644 --- a/symtabAPI/h/RangeLookup.h +++ b/symtabAPI/h/RangeLookup.h @@ -31,20 +31,15 @@ #if ! defined( RANGE_LOOKUP_H ) #define RANGE_LOOKUP_H +#include +#include #include #include #include #include #include "dyntypes.h" #include "util.h" -#include -#include -#include -#include -#include -#include -#include - +#include "IBSTree.h" namespace Dyninst { namespace SymtabAPI { @@ -66,7 +61,7 @@ namespace Dyninst { first = start; second = end; } - AddressRange(const AddressRange& other) : std::pair(other) + AddressRange(const AddressRange& other) noexcept : std::pair(other) { } AddressRange& operator=(const AddressRange& other) @@ -95,40 +90,6 @@ namespace Dyninst { os << std::hex << "[" << ar.first << ", " << ar.second << ")"; return os; } - template - struct RangeLookupTypes - { - typedef typename boost::multi_index::composite_key, - boost::multi_index::const_mem_fun > - addr_range_key; - typedef typename boost::multi_index::composite_key, - boost::multi_index::const_mem_fun > - upper_bound_key; - typedef typename boost::multi_index::composite_key, - boost::multi_index::const_mem_fun > - line_info_key; - typedef typename boost::multi_index_container - < - typename Value::Ptr, - boost::multi_index::indexed_by< - boost::multi_index::ordered_non_unique< boost::multi_index::tag, addr_range_key>, - boost::multi_index::ordered_non_unique< boost::multi_index::tag, upper_bound_key>, - boost::multi_index::ordered_non_unique< boost::multi_index::tag, line_info_key > - > - > type; - typedef typename boost::multi_index::index::type addr_range_index; - typedef typename boost::multi_index::index::type upper_bound_index; - typedef typename boost::multi_index::index::type line_info_index; - typedef typename type::value_type value_type; - - - }; - - } } #endif - diff --git a/symtabAPI/h/Region.h b/symtabAPI/h/Region.h index 303243ecdf..ad5b91cee6 100644 --- a/symtabAPI/h/Region.h +++ b/symtabAPI/h/Region.h @@ -30,6 +30,9 @@ #ifndef __REGION__H__ #define __REGION__H__ +#include +#include +#include #include "symutil.h" #include "Annotatable.h" @@ -72,6 +75,7 @@ class SYMTAB_EXPORT Region : public AnnotatableSparse { RT_SYMVERNEEDED, RT_REL, RT_RELA, + RT_RELR, RT_PLTREL, RT_PLTRELA, RT_DYNAMIC, diff --git a/symtabAPI/h/Statement.h b/symtabAPI/h/Statement.h new file mode 100644 index 0000000000..d0fceb7569 --- /dev/null +++ b/symtabAPI/h/Statement.h @@ -0,0 +1,118 @@ +/* + * See the dyninst/COPYRIGHT file for copyright information. + * + * We provide the Paradyn Tools (below described as "Paradyn") + * on an AS IS basis, and do not warrant its validity or performance. + * We reserve the right to update, modify, or discontinue this + * software at any time. We shall have no obligation to supply such + * updates or modifications or any other form of support to you. + * + * By your use of Paradyn, you understand and agree that we (or any + * other person or entity with proprietary rights in Paradyn) are + * under no obligation to provide either maintenance services, + * update services, notices of latent defects, or correction of + * defects for Paradyn. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __STATEMENT__H__ +#define __STATEMENT__H__ + +#include "Annotatable.h" +#include "RangeLookup.h" +#include "StringTable.h" +#include "util.h" + +namespace Dyninst { namespace SymtabAPI { + + class LineInformation; + + class SYMTAB_EXPORT Statement : public AddressRange { + friend class Module; + friend class LineInformation; + + Statement(int file_index, unsigned int line, unsigned int col = 0, + Offset start_addr = (Offset)-1L, Offset end_addr = (Offset)-1L) + : AddressRange(start_addr, end_addr), file_index_(file_index), line_(line), column_(col) {} + + unsigned int file_index_{}; // Maybe this should be module? + unsigned int line_{}; + unsigned int column_{}; + StringTablePtr strings_{}; + + public: + StringTablePtr getStrings_() const; + + void setStrings_(StringTablePtr strings_); + + Statement() : AddressRange(0, 0) {} + + Statement(const Statement &) = default; + + ~Statement() = default; + + struct StatementLess { + bool operator()(const Statement &lhs, const Statement &rhs) const; + }; + + typedef StatementLess LineNoTupleLess; + bool operator==(const Statement &cmp) const; + + bool operator==(Offset addr) const { return AddressRange::contains(addr); } + + bool operator<(Offset addr) const { return startAddr() <= addr; } + + bool operator>(Offset addr) const { return !((*this) < addr || (*this == addr)); } + + Offset startAddr() const { return first; } + + Offset endAddr() const { return second; } + + const std::string &getFile() const; + + unsigned int getFileIndex() const { return file_index_; } + + unsigned int getLine() const { return line_; } + + unsigned int getColumn() const { return column_; } + + struct addr_range {}; + + struct line_info {}; + + struct upper_bound {}; + + typedef Statement *Ptr; + typedef const Statement *ConstPtr; + }; + + typedef Statement LineNoTuple; + + template OS &operator<<(OS &os, const Statement &s) { + os << ": [" << std::hex << s.startAddr() << ", " << s.endAddr() << std::dec << ") @ " + << s.getFile() << " (" << s.getFileIndex() << "): " << s.getLine(); + return os; + } + + template OS &operator<<(OS &os, Statement *s) { + os << ": [" << std::hex << s->startAddr() << ", " << s->endAddr() << std::dec + << ") @ " << s->getFile() << " (" << s->getFileIndex() << "): " << s->getLine(); + return os; + } + +}} + +#endif diff --git a/symtabAPI/h/StringTable.h b/symtabAPI/h/StringTable.h index 25ee32628f..31d54cff10 100644 --- a/symtabAPI/h/StringTable.h +++ b/symtabAPI/h/StringTable.h @@ -5,14 +5,15 @@ #ifndef DYNINST_STRINGTABLE_H #define DYNINST_STRINGTABLE_H +#include +#include +#include +#include +#include +#include +#include #include "concurrent.h" -#include -#include -#include -#include -#include -#include -#include +#include namespace Dyninst { namespace SymtabAPI { @@ -22,39 +23,73 @@ namespace Dyninst { struct StringTableEntry { std::string str; std::string filename; - StringTableEntry(std::string s, std::string f) : str(s), filename(f){} + StringTableEntry(std::string s, std::string f) + : str(std::move(s)), + filename(f.empty() ? std::filesystem::path(str).filename().string() : std::move(f)) {} bool operator==(std::string s) const { return s == str || s == str.substr(str.rfind("/")+1); } }; - namespace bmi = boost::multi_index; - typedef boost::multi_index_container - < - StringTableEntry, - bmi::indexed_by - < - bmi::random_access<>, - bmi::ordered_non_unique - < - bmi::member - >, - bmi::ordered_non_unique - < - bmi::member - > - > - > - StringTableBase; - - struct StringTable : public StringTableBase { - StringTable() : StringTableBase() {} - ~StringTable() {} + struct StringTable { + using container_type = std::vector; + using value_type = container_type::value_type; + using iterator = container_type::iterator; + using const_iterator = container_type::const_iterator; + dyn_mutex lock; + + size_t size() const { return entries_.size(); } + bool empty() const { return entries_.empty(); } + + value_type &operator[](size_t idx) { return entries_[idx]; } + const value_type &operator[](size_t idx) const { return entries_[idx]; } + + iterator begin() { return entries_.begin(); } + iterator end() { return entries_.end(); } + const_iterator begin() const { return entries_.begin(); } + const_iterator end() const { return entries_.end(); } + + template + void emplace_back(S1 &&str, S2 &&filename) { + entries_.emplace_back(std::forward(str), std::forward(filename)); + } + + size_t ensure(std::string str, std::string filename = "") { + if (auto idx = find(str)) { + return *idx; + } + entries_.emplace_back(std::move(str), std::move(filename)); + return entries_.size() - 1; + } + + bool contains(const std::string &str) const { return static_cast(find(str)); } + + std::vector find_by_filename(const std::string &filename) const { + std::vector matches; + for (size_t i = 0; i < entries_.size(); ++i) { + if (entries_[i].filename == filename) { + matches.push_back(i); + } + } + return matches; + } + + std::optional find(const std::string &str) const { + for (size_t i = 0; i < entries_.size(); ++i) { + if (entries_[i].str == str) { + return i; + } + } + return std::nullopt; + } + + private: + container_type entries_; }; - typedef boost::shared_ptr StringTablePtr; + typedef dyncompat::shared_ptr StringTablePtr; inline std::ostream& operator<<(std::ostream& s, StringTableEntry e) { @@ -78,4 +113,3 @@ namespace Dyninst { #endif //DYNINST_STRINGTABLE_H - diff --git a/symtabAPI/h/Symbol.h b/symtabAPI/h/Symbol.h index f9318e8b4a..1a0c322759 100644 --- a/symtabAPI/h/Symbol.h +++ b/symtabAPI/h/Symbol.h @@ -43,7 +43,10 @@ #include "symutil.h" #include "Annotatable.h" -#include +#include +#include +#include +#include #ifndef CASE_RETURN_STR #define CASE_RETURN_STR(x) case x: return #x @@ -77,9 +80,6 @@ class SYMTAB_EXPORT Symbol : public AnnotatableSparse friend class Aggregate; friend class relocationEntry; - friend std::string parseStabString(Module *, int linenum, char *, int, - typeCommon *); - public: struct Ptr { @@ -295,16 +295,16 @@ class SYMTAB_EXPORT LookupInterface bool isRegex = false, bool checkCase = false, bool includeUndefined = false) = 0; - virtual bool findType(boost::shared_ptr& type, std::string name) = 0; + virtual bool findType(dyncompat::shared_ptr& type, std::string name) = 0; bool findType(Type*& t, std::string n) { - boost::shared_ptr tp; + dyncompat::shared_ptr tp; auto r = findType(tp, n); t = tp.get(); return r; } - virtual bool findVariableType(boost::shared_ptr& type, std::string name)= 0; + virtual bool findVariableType(dyncompat::shared_ptr& type, std::string name)= 0; bool findVariableType(Type*& t, std::string n) { - boost::shared_ptr tp; + dyncompat::shared_ptr tp; auto r = findVariableType(tp, n); t = tp.get(); return r; diff --git a/symtabAPI/h/Symtab.h b/symtabAPI/h/Symtab.h index 8a7730ef06..8b4ea3aa14 100644 --- a/symtabAPI/h/Symtab.h +++ b/symtabAPI/h/Symtab.h @@ -31,39 +31,28 @@ #ifndef __SYMTAB_H__ #define __SYMTAB_H__ +#include +#include +#include +#include +#include +#include #include +#include #include "Symbol.h" #include "Module.h" #include "Region.h" - +#include "Function.h" #include "Annotatable.h" #include "ProcReader.h" -#include "IBSTree.h" #include "Type.h" - +#include "compiler_annotations.h" +#include "relocationEntry.h" +#include "ExceptionBlock.h" #include "dyninstversion.h" -#include "concurrent.h" - -#include "boost/shared_ptr.hpp" -#include "boost/multi_index_container.hpp" -#include -#include -#include -#include -#include -#include -using boost::multi_index_container; -using boost::multi_index::indexed_by; -using boost::multi_index::ordered_unique; -using boost::multi_index::ordered_non_unique; -using boost::multi_index::hashed_non_unique; - -using boost::multi_index::identity; -using boost::multi_index::tag; -using boost::multi_index::const_mem_fun; -using boost::multi_index::member; +#include "dyncompat/shared_ptr.hpp" class MappedFile; @@ -80,16 +69,11 @@ namespace SymtabAPI { class Archive; class builtInTypeCollection; -class ExceptionBlock; class Object; class localVar; -class relocationEntry; class Type; -class FunctionBase; -class FuncRange; +struct symtab_impl; -typedef IBSTree< ModRange > ModRangeLookup; -typedef IBSTree FuncRangeLookup; typedef Dyninst::ProcessReader MemRegReader; class SYMTAB_EXPORT Symtab : public LookupInterface, @@ -105,6 +89,10 @@ class SYMTAB_EXPORT Symtab : public LookupInterface, friend class emitWin; friend class Aggregate; friend class relocationEntry; + friend class Object; + + // Hide implementation details that are complex or add large dependencies + const std::unique_ptr impl; public: @@ -112,14 +100,19 @@ class SYMTAB_EXPORT Symtab : public LookupInterface, /***** Public Member Functions *****/ public: static void version(int& major, int& minor, int& maintenance); - Symtab(MappedFile *); Symtab(); - Symtab(const Symtab& obj); Symtab(unsigned char *mem_image, size_t image_size, const std::string &name, bool defensive_binary, bool &err); + ~Symtab(); + + Symtab(Symtab const&) = delete; + Symtab& operator=(Symtab const&) = delete; + Symtab(Symtab&&) = delete; + Symtab& operator=(Symtab&&) = delete; + typedef enum { NotDefensive, Defensive} def_t; @@ -131,9 +124,6 @@ class SYMTAB_EXPORT Symtab : public LookupInterface, static Symtab *findOpenSymtab(std::string filename); static bool closeSymtab(Symtab *); - bool exportXML(std::string filename); - bool exportBin(std::string filename); - static Symtab *importBin(std::string filename); bool getRegValueAtFrame(Address pc, Dyninst::MachRegister reg, Dyninst::MachRegisterVal ®_result, @@ -193,10 +183,11 @@ class SYMTAB_EXPORT Symtab : public LookupInterface, // Module bool getAllModules(std::vector&ret); - bool findModuleByOffset(std::set& ret, Offset off); - bool findModuleByOffset(Module *& ret, Offset off); - bool findModuleByName(Module *&ret, const std::string name); - Module *getDefaultModule(); + DYNINST_DEPRECATED("Use findModulesByOffset(Offset)") bool findModuleByOffset(Module *& ret, Offset off); + Module* findModuleByOffset(Offset offset) const; + std::vector findModulesByName(std::string const& name) const; + Module *getDefaultModule() const; + Module* getContainingModule(Offset offset) const; // Region @@ -218,6 +209,7 @@ class SYMTAB_EXPORT Symtab : public LookupInterface, // Relocation entries bool getFuncBindingTable(std::vector &fbt) const; + bool findPltEntryByTarget(Address target_address, relocationEntry &result) const; bool updateFuncBindingTable(Offset stub_addr, Offset plt_addr); /************************************** @@ -253,28 +245,22 @@ class SYMTAB_EXPORT Symtab : public LookupInterface, Offset addressInRange); bool getSourceLines(std::vector &lines, Offset addressInRange); - bool addLine(std::string lineSource, unsigned int lineNo, - unsigned int lineOffset, Offset lowInclAddr, - Offset highExclAddr); - bool addAddressRange(Offset lowInclAddr, Offset highExclAddr, std::string lineSource, - unsigned int lineNo, unsigned int lineOffset = 0); void setTruncateLinePaths(bool value); bool getTruncateLinePaths(); - void forceFullLineInfoParse(); /***** Type Information *****/ - virtual bool findType(boost::shared_ptr& type, std::string name); + virtual bool findType(dyncompat::shared_ptr& type, std::string name); bool findType(Type*& t, std::string n) { - boost::shared_ptr tp; + dyncompat::shared_ptr tp; auto r = findType(tp, n); t = tp.get(); return r; } - virtual boost::shared_ptr findType(unsigned type_id, Type::do_share_t); + virtual dyncompat::shared_ptr findType(unsigned type_id, Type::do_share_t); Type* findType(unsigned i) { return findType(i, Type::share).get(); } - virtual bool findVariableType(boost::shared_ptr& type, std::string name); + virtual bool findVariableType(dyncompat::shared_ptr& type, std::string name); bool findVariableType(Type*& t, std::string n) { - boost::shared_ptr tp; + dyncompat::shared_ptr tp; auto r = findVariableType(tp, n); t = tp.get(); return r; @@ -282,20 +268,20 @@ class SYMTAB_EXPORT Symtab : public LookupInterface, bool addType(Type *typ); - static boost::shared_ptr& builtInTypes(); - static boost::shared_ptr& stdTypes(); + static dyncompat::shared_ptr& builtInTypes(); + static dyncompat::shared_ptr& stdTypes(); - static void getAllstdTypes(std::vector>&); + static void getAllstdTypes(std::vector>&); static std::vector* getAllstdTypes() { - std::vector> v; + std::vector> v; getAllstdTypes(v); auto r = new std::vector(v.size()); for(std::size_t i = 0; i < v.size(); i++) (*r)[i] = v[i].get(); return r; } - static void getAllbuiltInTypes(std::vector>&); + static void getAllbuiltInTypes(std::vector>&); static std::vector* getAllbuiltInTypes() { - std::vector> v; + std::vector> v; getAllbuiltInTypes(v); auto r = new std::vector(v.size()); for(std::size_t i = 0; i < v.size(); i++) (*r)[i] = v[i].get(); @@ -335,7 +321,6 @@ class SYMTAB_EXPORT Symtab : public LookupInterface, Offset newDataOffset, Offset newDataLength); bool fixup_RegionAddr(const char* name, Offset memOffset, long memSize); - bool fixup_SymbolAddr(const char* name, Offset newOffset); bool updateRegion(const char* name, void *buffer, unsigned size); bool updateCode(void *buffer, unsigned size); bool updateData(void *buffer, unsigned size); @@ -401,13 +386,9 @@ class SYMTAB_EXPORT Symtab : public LookupInterface, static void setSymtabError(SymtabError new_err); static std::string printError(SymtabError serr); - ~Symtab(); - bool delSymbol(Symbol *sym) { return deleteSymbol(sym); } bool deleteSymbol(Symbol *sym); - Symbol *getSymbolByIndex(unsigned); - /***** Private Member Functions *****/ private: @@ -429,7 +410,6 @@ class SYMTAB_EXPORT Symtab : public LookupInterface, bool addSymbolToIndices(Symbol *&sym, bool undefined); bool addSymbolToAggregates(const Symbol *sym); bool doNotAggregate(const Symbol *sym); - bool updateIndices(Symbol *sym, std::string newName, NameType nameType); void setModuleLanguages(dyn_hash_map *mod_langs); @@ -437,7 +417,6 @@ class SYMTAB_EXPORT Symtab : public LookupInterface, // Change the type of a symbol after the fact bool changeType(Symbol *sym, Symbol::SymbolType oldType); - bool changeSymbolOffset(Symbol *sym, Offset newOffset); bool deleteSymbolFromIndices(Symbol *sym); bool changeAggregateOffset(Aggregate *agg, Offset oldOffset, Offset newOffset); @@ -450,8 +429,8 @@ class SYMTAB_EXPORT Symtab : public LookupInterface, bool canBeShared(); - Module *getOrCreateModule(const std::string &modName, - const Offset modAddr); + DYNINST_DEPRECATED("Use getContainingModule") + Module *getOrCreateModule(const std::string &modName, const Offset modAddr); bool parseFunctionRanges(); //Only valid on ELF formats @@ -462,8 +441,7 @@ class SYMTAB_EXPORT Symtab : public LookupInterface, private: void createDefaultModule(); - - Module *newModule(const std::string &name, const Offset addr, supportedLanguages lang); + void addModule(Module *m); //bool buildFunctionLists(std::vector &raw_funcs); //void enterFunctionInTables(Symbol *func, bool wasSymtab); @@ -471,8 +449,6 @@ class SYMTAB_EXPORT Symtab : public LookupInterface, bool addSymtabVariables(); - void checkPPC64DescriptorSymbols(Object *linkedFile); - void parseLineInformation(); @@ -486,303 +462,103 @@ class SYMTAB_EXPORT Symtab : public LookupInterface, /***** Private Data Members *****/ private: - static boost::shared_ptr setupStdTypes(); - static boost::shared_ptr setupBuiltinTypes(); - dyn_rwlock symbols_rwlock; - // boost::mutex symbols_mutex; - - std::string member_name_; - Offset member_offset_; - Archive * parentArchive_; - MappedFile *mf; - MappedFile *mfForDebugInfo; - - Offset preferedBase_; - Offset imageOffset_; - unsigned imageLen_; - Offset dataOffset_; - unsigned dataLen_; - - bool is_a_out; - Offset main_call_addr_; // address of call to main() - - unsigned address_width_; - char *code_ptr_; - char *data_ptr_; - std::string interpreter_name_; - Offset entry_address_; - Offset base_address_; - Offset load_address_; - ObjectType object_type_; - bool is_eel_; - std::vector segments_; + static dyncompat::shared_ptr setupStdTypes(); + static dyncompat::shared_ptr setupBuiltinTypes(); + dyn_rwlock symbols_rwlock{}; + // dyncompat::mutex symbols_mutex; + + std::string member_name_{}; + Offset member_offset_{}; + Archive * parentArchive_{}; + MappedFile *mf{}; + + Offset preferedBase_{}; + Offset imageOffset_{}; + unsigned imageLen_{}; + Offset dataOffset_{}; + unsigned dataLen_{}; + + bool is_a_out{false}; + Offset main_call_addr_{}; // address of call to main() + + unsigned address_width_{sizeof(int)}; + std::string interpreter_name_{}; + Offset entry_address_{}; + Offset base_address_{}; + Offset load_address_{}; + ObjectType object_type_{obj_Unknown}; + bool is_eel_{false}; + std::vector segments_{}; + // make sure is_a_out is set before calling symbolsToFunctions // A std::vector of all Symtabs. Used to avoid duplicating // a Symtab that already exists. static std::vector allSymtabs; - std::string defaultNamespacePrefix; + std::string defaultNamespacePrefix{}; //sections - unsigned no_of_sections; - std::vector regions_; - std::vector codeRegions_; - std::vector dataRegions_; - dyn_hash_map regionsByEntryAddr; + unsigned no_of_sections{}; + std::vector regions_{}; + std::vector codeRegions_{}; + std::vector dataRegions_{}; + dyn_hash_map regionsByEntryAddr{}; //Point where new loadable sections will be inserted - unsigned newSectionInsertPoint; + unsigned newSectionInsertPoint{}; //symbols - unsigned no_of_symbols; - - struct indexed_symbols { - typedef dyn_c_hash_map master_t; - typedef std::vector symvec_t; - typedef dyn_c_hash_map by_offset_t; - typedef dyn_c_hash_map by_name_t; - - master_t master; - by_offset_t by_offset; - by_name_t by_mangled; - by_name_t by_pretty; - by_name_t by_typed; - - // Only inserts if not present. Returns whether it inserted. - bool insert(Symbol* s); - - // Clears the table. Do not use in parallel. - void clear(); - - // Erases symbols from the table. Do not use in parallel. - void erase(Symbol* s); - - // Iterator for the symbols. Do not use in parallel. - class iterator : public std::iterator { - master_t::iterator m; - public: - iterator(master_t::iterator i) : m(i) {} - bool operator==(const iterator& x) { return m == x.m; } - bool operator!=(const iterator& x) { return !operator==(x); } - Symbol* const& operator*() const { return m->first; } - Symbol* const* operator->() const { return &operator*(); } - iterator& operator++() { ++m; return *this; } - iterator operator++(int) { - iterator old(m); - operator++(); - return old; - } - }; - - iterator begin() { return iterator(master.begin()); } - iterator end() { return iterator(master.end()); } - }; - - indexed_symbols everyDefinedSymbol; - indexed_symbols undefDynSyms; + unsigned no_of_symbols{}; // We also need per-Aggregate indices - bool sorted_everyFunction; - std::vector everyFunction; - // Since Functions are unique by address we require this structure to - // efficiently track them. - dyn_c_hash_map funcsByOffset; + bool sorted_everyFunction{false}; + std::vector everyFunction{}; // Similar for Variables - std::vector everyVariable; - using VarsByOffsetMap = dyn_c_hash_map >; - VarsByOffsetMap varsByOffset; + std::vector everyVariable{}; - dyn_mutex im_lock; - boost::multi_index_container, - boost::multi_index::ordered_unique >, - boost::multi_index::ordered_non_unique< - boost::multi_index::const_mem_fun >, - boost::multi_index::ordered_non_unique< - boost::multi_index::const_mem_fun > - > - > - indexed_modules; + std::vector relocation_table_{}; + std::vector excpBlocks{}; - - std::vector relocation_table_; - std::vector excpBlocks; - - std::vector deps_; + std::vector deps_{}; // This set is used during static linking to satisfy dependencies - std::vector linkingResources_; + std::vector linkingResources_{}; // This set represents Symtabs referenced by a new external Symbol bool getExplicitSymtabRefs(std::set &refs); - std::set explicitSymtabRefs_; - - //type info valid flag - bool isTypeInfoValid_; - - int nlines_; - unsigned long fdptr_; - char *lines_; - char *stabstr_; - int nstabs_; - void *stabs_; - char *stringpool_; + std::set explicitSymtabRefs_{}; //Relocation sections - bool hasRel_; - bool hasRela_; - bool hasReldyn_; - bool hasReladyn_; - bool hasRelplt_; - bool hasRelaplt_; - - bool isStaticBinary_; - bool isDefensiveBinary_; + bool hasRel_{false}; + bool hasRela_{false}; + bool hasReldyn_{false}; + bool hasReladyn_{false}; + bool hasRelplt_{false}; + bool hasRelaplt_{false}; - FuncRangeLookup *func_lookup; - ModRangeLookup *mod_lookup_; + bool isStaticBinary_{false}; + bool isDefensiveBinary_{false}; //Don't use obj_private, use getObject() instead. public: Object *getObject(); const Object *getObject() const; - ModRangeLookup* mod_lookup(); void dumpModRanges(); void dumpFuncRanges(); private: - Object *obj_private; + Object *obj_private{}; // dynamic library name substitutions - std::map dynLibSubs; + std::map dynLibSubs{}; public: - static boost::shared_ptr& type_Error(); - static boost::shared_ptr& type_Untyped(); + static dyncompat::shared_ptr& type_Error(); + static dyncompat::shared_ptr& type_Untyped(); private: - unsigned _ref_cnt; -}; - -/** - * Used to represent something like a C++ try/catch block. - * Currently only used on Linux - **/ -SYMTAB_EXPORT std::ostream &operator<<(std::ostream &os, const ExceptionBlock &q); - -class SYMTAB_EXPORT ExceptionBlock : public AnnotatableSparse { - // Accessors provide consistent access to the *original* offsets. - // We allow this to be updated (e.g. to account for relocated code - public: - ExceptionBlock(Offset tStart, unsigned tSize, Offset cStart); - ExceptionBlock(Offset cStart); - SYMTAB_EXPORT ExceptionBlock(const ExceptionBlock &eb) = default; - SYMTAB_EXPORT ~ExceptionBlock() = default; - SYMTAB_EXPORT ExceptionBlock() = default; - - bool hasTry() const; - Offset tryStart() const; - Offset tryEnd() const; - Offset trySize() const; - Offset catchStart() const; - bool contains(Offset a) const; - void setTryStart(Offset ts) - { - tryStart_ptr = ts; - } - void setTryEnd(Offset te) - { - tryEnd_ptr = te; - } - - void setCatchStart(Offset cs) - { - catchStart_ptr = cs; - } - - void setFdeStart(Offset fs) - { - fdeStart_ptr = fs; - } - - void setFdeEnd(Offset fe) - { - fdeEnd_ptr = fe; - } - - - friend SYMTAB_EXPORT std::ostream &operator<<(std::ostream &os, const ExceptionBlock &q); - private: - Offset tryStart_; - unsigned trySize_; - Offset catchStart_; - bool hasTry_; - Offset tryStart_ptr; - Offset tryEnd_ptr; - Offset catchStart_ptr; - Offset fdeStart_ptr; - Offset fdeEnd_ptr; -}; - -// relocation information for calls to functions not in this image -SYMTAB_EXPORT std::ostream &operator<<(std::ostream &os, const relocationEntry &q); - -class SYMTAB_EXPORT relocationEntry : public AnnotatableSparse { - public: - - relocationEntry(); - relocationEntry(Offset ta, Offset ra, Offset add, - std::string n, Symbol *dynref = NULL, unsigned long relType = 0); - relocationEntry(Offset ta, Offset ra, std::string n, - Symbol *dynref = NULL, unsigned long relType = 0); - relocationEntry(Offset ra, std::string n, Symbol *dynref = NULL, - unsigned long relType = 0, Region::RegionType rtype = Region::RT_REL); - relocationEntry(Offset ta, Offset ra, Offset add, - std::string n, Symbol *dynref = NULL, unsigned long relType = 0, - Region::RegionType rtype = Region::RT_REL); - - Offset target_addr() const; - Offset rel_addr() const; - Offset addend() const; - Region::RegionType regionType() const; - const std::string &name() const; - Symbol *getDynSym() const; - bool addDynSym(Symbol *dynref); - unsigned long getRelType() const; - - void setTargetAddr(const Offset); - void setRelAddr(const Offset); - void setAddend(const Offset); - void setRegionType(const Region::RegionType); - void setName(const std::string &newName); - void setRelType(unsigned long relType) { relType_ = relType; } - - // dump output. Currently setup as a debugging aid, not really - // for object persistance.... - //std::ostream & operator<<(std::ostream &s) const; - friend SYMTAB_EXPORT std::ostream & operator<<(std::ostream &os, const relocationEntry &q); - - enum {pltrel = 1, dynrel = 2}; - bool operator==(const relocationEntry &) const; - - enum category { relative, jump_slot, absolute }; - - // Architecture-specific functions - static unsigned long getGlobalRelType(unsigned addressWidth, Symbol *sym = NULL); - static const char *relType2Str(unsigned long r, unsigned addressWidth = sizeof(Address)); - category getCategory( unsigned addressWidth ); - - private: - Offset target_addr_; // target address of call instruction - Offset rel_addr_; // address of corresponding relocation entry - Offset addend_; // addend (from RELA entries) - Region::RegionType rtype_; // RT_REL vs. RT_RELA - std::string name_; - Symbol *dynref_; - unsigned long relType_; - Offset rel_struct_addr_; + unsigned _ref_cnt{1}; }; }//namespace SymtabAPI diff --git a/symtabAPI/h/SymtabReader.h b/symtabAPI/h/SymtabReader.h index 7674cc417e..f392c5458d 100644 --- a/symtabAPI/h/SymtabReader.h +++ b/symtabAPI/h/SymtabReader.h @@ -34,6 +34,7 @@ #include "SymReader.h" #include #include +#include //Some components (StackwalkerAPI, ProcControlAPI) use a SymReader (defined in dyn_util/h) // to read symbols rather than a straight dependency on SymtabAPI. A component can // either define its own SymReader (as ProcControlAPI does) or it can use SymtabAPI as diff --git a/symtabAPI/h/Type.h b/symtabAPI/h/Type.h index b827802e66..10d986dd8f 100644 --- a/symtabAPI/h/Type.h +++ b/symtabAPI/h/Type.h @@ -31,13 +31,17 @@ #ifndef __Type_h__ #define __Type_h__ +#include +#include +#include +#include #include "Annotatable.h" #include "symutil.h" #include "concurrent.h" -#include +#include #include -#include +#include namespace Dyninst{ namespace SymtabAPI{ @@ -111,11 +115,9 @@ SYMTAB_EXPORT const char *visibility2Str(visibility_t v); class SYMTAB_EXPORT Type : public TYPE_ANNOTATABLE_CLASS { friend class typeCollection; - friend std::string parseStabString(Module *, int linenum, char *, int, - typeCommon*); static Type* upgradePlaceholder(Type *placeholder, Type *new_type); - boost::weak_ptr self_; // For carrying the reference count across + dyncompat::weak_ptr self_; // For carrying the reference count across // the older pointer-based API. public: @@ -123,18 +125,18 @@ class SYMTAB_EXPORT Type : public TYPE_ANNOTATABLE_CLASS enum do_share_t { share }; template - static boost::shared_ptr make_shared(Args&&... args) { - auto sp = boost::make_shared(std::forward(args)...); + static dyncompat::shared_ptr make_shared(Args&&... args) { + auto sp = dyncompat::make_shared(std::forward(args)...); sp->reshare(sp); return sp; } - boost::shared_ptr reshare() { - boost::shared_ptr r = self_.lock(); - if(!r) self_ = (r = boost::shared_ptr(this)); + dyncompat::shared_ptr reshare() { + dyncompat::shared_ptr r = self_.lock(); + if(!r) self_ = (r = dyncompat::shared_ptr(this)); return r; } - void reshare(boost::shared_ptr const & sp) { + void reshare(dyncompat::shared_ptr const & sp) { assert(!self_.lock()); self_ = sp; } @@ -166,7 +168,7 @@ class SYMTAB_EXPORT Type : public TYPE_ANNOTATABLE_CLASS public: virtual bool operator==(const Type &) const; - bool isCompatible(boost::shared_ptr x) { return isCompatible(x.get()); } + bool isCompatible(dyncompat::shared_ptr x) { return isCompatible(x.get()); } virtual bool isCompatible(Type *oType); virtual void fixupUnknowns(Module *); @@ -182,7 +184,7 @@ class SYMTAB_EXPORT Type : public TYPE_ANNOTATABLE_CLASS Type* ptr; public: unique_ptr_Type(Type* p) : ptr(p) {} - operator boost::shared_ptr() { + operator dyncompat::shared_ptr() { return ptr->reshare(); } operator Type*() { return ptr; } @@ -251,7 +253,7 @@ class SYMTAB_EXPORT Field : public FIELD_ANNOTATABLE_CLASS friend class CBlock; std::string fieldName_; - boost::shared_ptr type_; + dyncompat::shared_ptr type_; visibility_t vis_; int offset_; @@ -261,7 +263,7 @@ class SYMTAB_EXPORT Field : public FIELD_ANNOTATABLE_CLASS public: Field(); - Field(std::string name, boost::shared_ptr typ, int offsetVal = -1, + Field(std::string name, dyncompat::shared_ptr typ, int offsetVal = -1, visibility_t vis = visUnknown); Field(std::string n, Type* t, int ov = -1, visibility_t v = visUnknown) : Field(n, t ? t->reshare() : nullptr, ov, v) {} @@ -271,7 +273,7 @@ class SYMTAB_EXPORT Field : public FIELD_ANNOTATABLE_CLASS virtual ~Field(); std::string &getName(); - boost::shared_ptr getType(Type::do_share_t); + dyncompat::shared_ptr getType(Type::do_share_t); Type* getType() { return getType(Type::share).get(); } visibility_t getVisibility(); unsigned int getSize(); @@ -303,7 +305,8 @@ class SYMTAB_EXPORT rangedInterface { class SYMTAB_EXPORT derivedInterface{ public: virtual ~derivedInterface() = default; - virtual boost::shared_ptr getConstituentType(Type::do_share_t) const = 0; + derivedInterface& operator=(const derivedInterface&) = default; + virtual dyncompat::shared_ptr getConstituentType(Type::do_share_t) const = 0; Type* getConstituentType() const { return getConstituentType(Type::share).get(); } }; @@ -323,6 +326,7 @@ class SYMTAB_EXPORT fieldListType : public Type, public fieldListInterface ~fieldListType(); fieldListType& operator=(const fieldListType&) = default; bool operator==(const Type &) const; + bool operator==(const fieldListType &otype) const { return *this == static_cast(otype); } dyn_c_vector *getComponents() const; dyn_c_vector *getFields() const; @@ -330,11 +334,11 @@ class SYMTAB_EXPORT fieldListType : public Type, public fieldListInterface virtual void postFieldInsert(int nsize) = 0; /* Add field for C++ struct or union */ - void addField(std::string fieldname, boost::shared_ptr type, int offsetVal = -1, visibility_t vis = visUnknown); + void addField(std::string fieldname, dyncompat::shared_ptr type, int offsetVal = -1, visibility_t vis = visUnknown); void addField(std::string n, Type* t, int ov = -1, visibility_t v = visUnknown) { addField(n, t->reshare(), ov, v); } - void addField(unsigned num, std::string fieldname, boost::shared_ptr type, int offsetVal = -1, visibility_t vis = visUnknown); + void addField(unsigned num, std::string fieldname, dyncompat::shared_ptr type, int offsetVal = -1, visibility_t vis = visUnknown); void addField(unsigned n, std::string f, Type* t, int o = -1, visibility_t v = visUnknown) { addField(n, f, t->reshare(), o, v); } @@ -358,6 +362,7 @@ class SYMTAB_EXPORT rangedType : public Type, public rangedInterface { public: rangedType(); bool operator==(const Type &) const; + bool operator==(const rangedType &otype) const { return *this == static_cast(otype); } unsigned long getLow() const { return low_; } unsigned long getHigh() const { return hi_; } }; @@ -366,14 +371,15 @@ bool Type::isRangedType() { return dynamic_cast(this) != NULL; } class SYMTAB_EXPORT derivedType : public Type, public derivedInterface { protected: - boost::shared_ptr baseType_; + dyncompat::shared_ptr baseType_; protected: derivedType(std::string &name, typeId_t id, int size, dataClass typeDes); derivedType(std::string &name, int size, dataClass typeDes); public: derivedType(); bool operator==(const Type &) const; - boost::shared_ptr getConstituentType(Type::do_share_t) const; + bool operator==(const derivedType &otype) const { return *this == static_cast(otype); } + dyncompat::shared_ptr getConstituentType(Type::do_share_t) const; Type* getConstituentType() const { return getConstituentType(Type::share).get(); } }; derivedType& Type::asDerivedType() { return dynamic_cast(*this); } @@ -381,21 +387,23 @@ bool Type::isDerivedType() { return dynamic_cast(this) != NULL; } // Derived classes from Type -class SYMTAB_EXPORT typeEnum : public Type { +class SYMTAB_EXPORT typeEnum : public derivedType { private: dyn_c_vector > consts; + bool is_scoped_{false}; // C++11 scoped enum (i.e., 'enum class')? public: - typeEnum(); - typeEnum(typeId_t ID, std::string name = ""); - typeEnum(std::string name); - static typeEnum *create(std::string &name, dyn_c_vector *>&elements, - Symtab *obj = NULL); - static typeEnum *create(std::string &name, dyn_c_vector &constNames, Symtab *obj); + struct scoped_t final {}; + typeEnum() = default; + typeEnum(dyncompat::shared_ptr underlying_type, std::string name); + typeEnum(dyncompat::shared_ptr underlying_type, std::string name, typeId_t ID); + typeEnum(dyncompat::shared_ptr underlying_type, std::string name, typeId_t ID, scoped_t) : + typeEnum(underlying_type, std::move(name), ID) { is_scoped_=true; } + bool addConstant(const std::string &fieldname,int value); dyn_c_vector > &getConstants(); - bool setName(const char *name); - bool isCompatible(boost::shared_ptr x) { return isCompatible(x.get()); } + bool isCompatible(dyncompat::shared_ptr x) { return isCompatible(x.get()); } bool isCompatible(Type *otype); + bool is_scoped() const noexcept { return is_scoped_; } }; typeEnum& Type::asEnumType() { return dynamic_cast(*this); } bool Type::isEnumType() { return dynamic_cast(this) != NULL; } @@ -404,33 +412,33 @@ class SYMTAB_EXPORT typeFunction : public Type { protected: void fixupUnknowns(Module *); private: - boost::shared_ptr retType_; /* Return type of the function */ - dyn_c_vector> params_; + dyncompat::shared_ptr retType_; /* Return type of the function */ + dyn_c_vector> params_; public: typeFunction(); - typeFunction(typeId_t ID, boost::shared_ptr retType, std::string name = ""); + typeFunction(typeId_t ID, dyncompat::shared_ptr retType, std::string name = ""); typeFunction(typeId_t i, Type* r, std::string n = "") : typeFunction(i, r->reshare(), n) {} - typeFunction(boost::shared_ptr retType, std::string name = ""); + typeFunction(dyncompat::shared_ptr retType, std::string name = ""); typeFunction(Type* retType, std::string name = "") : typeFunction(retType->reshare(), name) {} - static typeFunction *create(std::string &name, boost::shared_ptr retType, - dyn_c_vector> ¶mTypes, Symtab *obj = NULL); + static typeFunction *create(std::string &name, dyncompat::shared_ptr retType, + dyn_c_vector> ¶mTypes, Symtab *obj = NULL); static typeFunction *create(std::string &n, Type* rt, dyn_c_vector &p, Symtab* o = NULL) { - dyn_c_vector> pp; + dyn_c_vector> pp; auto r = create(n, rt->reshare(), pp, o); for(auto it = pp.begin(); it != pp.end(); ++it) p.push_back(it->get()); return r; } - bool addParam(boost::shared_ptr type); + bool addParam(dyncompat::shared_ptr type); bool addParam(Type* t) { return addParam(t->reshare()); } - boost::shared_ptr getReturnType(Type::do_share_t) const; + dyncompat::shared_ptr getReturnType(Type::do_share_t) const; Type* getReturnType() const { return getReturnType(Type::share).get(); } - bool setRetType(boost::shared_ptr rtype); + bool setRetType(dyncompat::shared_ptr rtype); bool setRetType(Type* t) { return setRetType(t->reshare()); } - dyn_c_vector> &getParams(); - bool isCompatible(boost::shared_ptr x) { return isCompatible(x.get()); } + dyn_c_vector> &getParams(); + bool isCompatible(dyncompat::shared_ptr x) { return isCompatible(x.get()); } bool isCompatible(Type *otype); }; typeFunction& Type::asFunctionType() { return dynamic_cast(*this); } @@ -476,12 +484,18 @@ class SYMTAB_EXPORT typeScalar : public Type { } typeScalar(unsigned int size, std::string name = "", bool isSigned = false) - : typeScalar(this->getUniqueTypeId(), size, name, isSigned) {} + : typeScalar() + { + ID_ = this->getUniqueTypeId(); + size_ = size; + name_ = name; + props.is_signed = isSigned; + } static typeScalar *create(std::string &name, int size, Symtab *obj = NULL); bool isSigned() const { return props.is_signed; } properties_t const& properties() const { return props; } - bool isCompatible(boost::shared_ptr x) {return isCompatible(x.get());} + bool isCompatible(dyncompat::shared_ptr x) {return isCompatible(x.get());} bool isCompatible(Type *otype); }; @@ -532,13 +546,13 @@ class SYMTAB_EXPORT typeStruct : public fieldListType { typeStruct(); typeStruct(typeId_t ID, std::string name = ""); typeStruct(std::string name); - static typeStruct *create(std::string &name, dyn_c_vector< std::pair > *> &flds, + static typeStruct *create(std::string &name, dyn_c_vector< std::pair > *> &flds, Symtab *obj = NULL); static typeStruct *create(std::string &n, dyn_c_vector*> &f, Symtab *o = NULL) { - dyn_c_vector>*> fp(f.size()); + dyn_c_vector>*> fp(f.size()); for(auto it = f.begin(); it != f.end(); ++it) - fp[it - f.begin()] = new std::pair>( + fp[it - f.begin()] = new std::pair>( (*it)->first, (*it)->second->reshare()); auto r = create(n, fp, o); for(auto it = fp.begin(); it != fp.end(); ++it) delete *it; @@ -547,7 +561,7 @@ class SYMTAB_EXPORT typeStruct : public fieldListType { static typeStruct *create(std::string &name, dyn_c_vector &fields, Symtab *obj = NULL); - bool isCompatible(boost::shared_ptr x) { return isCompatible(x.get()); } + bool isCompatible(dyncompat::shared_ptr x) { return isCompatible(x.get()); } bool isCompatible(Type *otype); }; bool Type::isStructType() { return dynamic_cast(this) != NULL; } @@ -562,13 +576,13 @@ class SYMTAB_EXPORT typeUnion : public fieldListType { typeUnion(); typeUnion(typeId_t ID, std::string name = ""); typeUnion(std::string name); - static typeUnion *create(std::string &name, dyn_c_vector> *> &fieldNames, + static typeUnion *create(std::string &name, dyn_c_vector> *> &fieldNames, Symtab *obj = NULL); static typeUnion *create(std::string &n, dyn_c_vector*> &f, Symtab *o = NULL) { - dyn_c_vector>*> fp(f.size()); + dyn_c_vector>*> fp(f.size()); for(auto it = f.begin(); it != f.end(); ++it) - fp[it - f.begin()] = new std::pair>( + fp[it - f.begin()] = new std::pair>( (*it)->first, (*it)->second->reshare()); auto r = create(n, fp, o); for(auto it = fp.begin(); it != fp.end(); ++it) delete *it; @@ -576,7 +590,7 @@ class SYMTAB_EXPORT typeUnion : public fieldListType { } static typeUnion *create(std::string &name, dyn_c_vector &fields, Symtab *obj = NULL); - bool isCompatible(boost::shared_ptr x) { return isCompatible(x.get()); } + bool isCompatible(dyncompat::shared_ptr x) { return isCompatible(x.get()); } bool isCompatible(Type *otype); }; @@ -585,25 +599,25 @@ class SYMTAB_EXPORT typePointer : public derivedType { void fixupUnknowns(Module *); public: typePointer(); - typePointer(typeId_t ID, boost::shared_ptr ptr, std::string name = ""); + typePointer(typeId_t ID, dyncompat::shared_ptr ptr, std::string name = ""); typePointer(typeId_t i, Type* p, std::string n = "") : typePointer(i, p->reshare(), n) {} - typePointer(boost::shared_ptr ptr, std::string name = ""); + typePointer(dyncompat::shared_ptr ptr, std::string name = ""); typePointer(Type* p, std::string n = "") : typePointer(p->reshare(), n) {} - static typePointer *create(std::string &name, boost::shared_ptr ptr, Symtab *obj = NULL); + static typePointer *create(std::string &name, dyncompat::shared_ptr ptr, Symtab *obj = NULL); static typePointer *create(std::string &n, Type* p, Symtab *o = NULL) { return create(n, p->reshare(), o); } - static typePointer *create(std::string &name, boost::shared_ptr ptr, int size, + static typePointer *create(std::string &name, dyncompat::shared_ptr ptr, int size, Symtab *obj = NULL); static typePointer *create(std::string &n, Type* p, int s, Symtab *o = NULL) { return create(n, p->reshare(), s, o); } - bool isCompatible(boost::shared_ptr x) { return isCompatible(x.get()); } + bool isCompatible(dyncompat::shared_ptr x) { return isCompatible(x.get()); } bool isCompatible(Type *otype); - bool setPtr(boost::shared_ptr ptr); + bool setPtr(dyncompat::shared_ptr ptr); bool setPtr(Type* ptr) { return setPtr(ptr->reshare()); } }; @@ -617,40 +631,48 @@ class SYMTAB_EXPORT typeTypedef: public derivedType { public: typeTypedef(); - typeTypedef(typeId_t ID, boost::shared_ptr base, std::string name, unsigned int sizeHint = 0); + typeTypedef(typeId_t ID, dyncompat::shared_ptr base, std::string name, unsigned int sizeHint = 0); typeTypedef(typeId_t i, Type* b, std::string n, unsigned int s = 0) : typeTypedef(i, b->reshare(), n, s) {} - typeTypedef(boost::shared_ptr base, std::string name, unsigned int sizeHint = 0); + typeTypedef(dyncompat::shared_ptr base, std::string name, unsigned int sizeHint = 0); typeTypedef(Type* b, std::string n, unsigned int s = 0) : typeTypedef(b->reshare(), n, s) {} - static typeTypedef *create(std::string &name, boost::shared_ptr ptr, Symtab *obj = NULL); + static typeTypedef *create(std::string &name, dyncompat::shared_ptr ptr, Symtab *obj = NULL); static typeTypedef *create(std::string &n, Type* p, Symtab *o = NULL) { return create(n, p->reshare(), o); } - bool isCompatible(boost::shared_ptr x) { return isCompatible(x.get()); } + bool isCompatible(dyncompat::shared_ptr x) { return isCompatible(x.get()); } bool isCompatible(Type *otype); bool operator==(const Type &otype) const; + bool operator==(const typeTypedef &otype) const { return *this == static_cast(otype); } }; class SYMTAB_EXPORT typeRef : public derivedType { + private: + bool is_rvalue_{false}; protected: void fixupUnknowns(Module *); public: + struct rvalue_t final{}; typeRef(); - typeRef(typeId_t ID, boost::shared_ptr refType, std::string name); + typeRef(typeId_t ID, dyncompat::shared_ptr refType, std::string name); + typeRef(typeId_t ID, dyncompat::shared_ptr refType, std::string name, rvalue_t) : + typeRef(ID, refType, name) { is_rvalue_ = true; } typeRef(typeId_t i, Type* r, std::string n) : typeRef(i, r->reshare(), n) {} - typeRef(boost::shared_ptr refType, std::string name); + typeRef(dyncompat::shared_ptr refType, std::string name); typeRef(Type* r, std::string n) : typeRef(r->reshare(), n) {} - static typeRef *create(std::string &name, boost::shared_ptr ptr, Symtab * obj = NULL); + static typeRef *create(std::string &name, dyncompat::shared_ptr ptr, Symtab * obj = NULL); static typeRef *create(std::string &n, Type* p, Symtab * o = NULL) { return create(n, p->reshare(), o); } - bool isCompatible(boost::shared_ptr x) { return isCompatible(x.get()); } + bool isCompatible(dyncompat::shared_ptr x) { return isCompatible(x.get()); } bool isCompatible(Type *otype); bool operator==(const Type &otype) const; + bool operator==(const typeRef &otype) const { return *this == static_cast(otype); } + bool is_rvalue() const noexcept { return is_rvalue_; } }; class SYMTAB_EXPORT typeSubrange : public rangedType { @@ -661,34 +683,35 @@ class SYMTAB_EXPORT typeSubrange : public rangedType { typeSubrange(typeId_t ID, int size, long low, long hi, std::string name); typeSubrange( int size, long low, long hi, std::string name); static typeSubrange *create(std::string &name, int size, long low, long hi, Symtab *obj = NULL); - bool isCompatible(boost::shared_ptr x) { return isCompatible(x.get()); } + bool isCompatible(dyncompat::shared_ptr x) { return isCompatible(x.get()); } bool isCompatible(Type *otype); }; class SYMTAB_EXPORT typeArray : public rangedType { private: - boost::shared_ptr arrayElem; + dyncompat::shared_ptr arrayElem; unsigned int sizeHint_; protected: void updateSize(); void merge(Type *other); public: typeArray(); - typeArray(typeId_t ID, boost::shared_ptr base, long low, long hi, std::string name, unsigned int sizeHint = 0); + typeArray(typeId_t ID, dyncompat::shared_ptr base, long low, long hi, std::string name, unsigned int sizeHint = 0); typeArray(typeId_t i, Type* b, long l, long h, std::string n, unsigned int s = 0) : typeArray(i, b->reshare(), l, h, n, s) {} - typeArray(boost::shared_ptr base, long low, long hi, std::string name, unsigned int sizeHint = 0); + typeArray(dyncompat::shared_ptr base, long low, long hi, std::string name, unsigned int sizeHint = 0); typeArray(Type* b, long l, long h, std::string n, unsigned int s = 0) : typeArray(b->reshare(), l, h, n, s) {} - static typeArray *create(std::string &name, boost::shared_ptr typ, long low, long hi, Symtab *obj = NULL); + static typeArray *create(std::string &name, dyncompat::shared_ptr typ, long low, long hi, Symtab *obj = NULL); static typeArray *create(std::string &n, Type* t, long l, long h, Symtab *o = NULL) { return create(n, t->reshare(), l, h, o); } - boost::shared_ptr getBaseType(Type::do_share_t) const; + dyncompat::shared_ptr getBaseType(Type::do_share_t) const; Type* getBaseType() const { return getBaseType(Type::share).get(); } - bool isCompatible(boost::shared_ptr x) { return isCompatible(x.get()); } + bool isCompatible(dyncompat::shared_ptr x) { return isCompatible(x.get()); } bool isCompatible(Type *otype); bool operator==(const Type &otype) const; + bool operator==(const typeArray &otype) const { return *this == static_cast(otype); } void fixupUnknowns(Module *); }; typeArray& Type::asArrayType() { return dynamic_cast(*this); } diff --git a/symtabAPI/h/Variable.h b/symtabAPI/h/Variable.h index ef312ab1da..99d219f539 100644 --- a/symtabAPI/h/Variable.h +++ b/symtabAPI/h/Variable.h @@ -31,11 +31,14 @@ #if !defined(_Variable_h_) #define _Variable_h_ +#include +#include +#include #include "Annotatable.h" #include "Symtab.h" #include "Aggregate.h" -#include "dyn_regs.h" #include "VariableLocation.h" +#include "Type.h" namespace Dyninst { namespace SymtabAPI { @@ -59,9 +62,9 @@ class SYMTAB_EXPORT Variable : public Aggregate, public AnnotatableSparse { /* Symbol management */ bool removeSymbol(Symbol *sym); - void setType(boost::shared_ptr type); + void setType(dyncompat::shared_ptr type); void setType(Type* t) { setType(t->reshare()); } - boost::shared_ptr getType(Type::do_share_t); + dyncompat::shared_ptr getType(Type::do_share_t); Type* getType() { return getType(Type::share).get(); } bool operator==(const Variable &v); @@ -72,7 +75,7 @@ class SYMTAB_EXPORT Variable : public Aggregate, public AnnotatableSparse { private: - boost::shared_ptr type_; + dyncompat::shared_ptr type_; void print(std::ostream &) const; }; @@ -83,7 +86,7 @@ class SYMTAB_EXPORT localVar : public AnnotatableSparse friend class localVarCollection; std::string name_; - boost::shared_ptr type_; + dyncompat::shared_ptr type_; std::string fileName_; int lineNum_; FunctionBase *func_; @@ -102,7 +105,7 @@ class SYMTAB_EXPORT localVar : public AnnotatableSparse localVar() : type_(NULL), lineNum_(-1), func_(NULL), locsExpanded_(false) {} // Internal use only - localVar(std::string name, boost::shared_ptr typ, std::string fileName, + localVar(std::string name, dyncompat::shared_ptr typ, std::string fileName, int lineNum, FunctionBase *f, std::vector *locs = NULL); localVar(std::string n, Type* t, std::string fn, int l, FunctionBase *f, @@ -118,9 +121,9 @@ class SYMTAB_EXPORT localVar : public AnnotatableSparse public: // end of functions for internal use only std::string &getName(); - boost::shared_ptr getType(Type::do_share_t); + dyncompat::shared_ptr getType(Type::do_share_t); Type* getType() { return getType(Type::share).get(); } - bool setType(boost::shared_ptr newType); + bool setType(dyncompat::shared_ptr newType); bool setType(Type* t) { return setType(t->reshare()); } int getLineNum(); std::string &getFileName(); diff --git a/symtabAPI/h/relocationEntry.h b/symtabAPI/h/relocationEntry.h new file mode 100644 index 0000000000..796783fce4 --- /dev/null +++ b/symtabAPI/h/relocationEntry.h @@ -0,0 +1,114 @@ +/* + * See the dyninst/COPYRIGHT file for copyright information. + * + * We provide the Paradyn Tools (below described as "Paradyn") + * on an AS IS basis, and do not warrant its validity or performance. + * We reserve the right to update, modify, or discontinue this + * software at any time. We shall have no obligation to supply such + * updates or modifications or any other form of support to you. + * + * By your use of Paradyn, you understand and agree that we (or any + * other person or entity with proprietary rights in Paradyn) are + * under no obligation to provide either maintenance services, + * update services, notices of latent defects, or correction of + * defects for Paradyn. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __RELOCATIONENTRY_H__ +#define __RELOCATIONENTRY_H__ + +#include +#include + +#include "util.h" +#include "dyntypes.h" +#include "Annotatable.h" +#include "Region.h" + + +namespace Dyninst { + + struct SymSegment; + +namespace SymtabAPI { + +class Symbol; + +class SYMTAB_EXPORT relocationEntry : public AnnotatableSparse { + public: + + relocationEntry(); + relocationEntry(Offset ta, Offset ra, Offset add, + std::string n, Symbol *dynref = NULL, unsigned long relType = 0); + relocationEntry(Offset ta, Offset ra, std::string n, + Symbol *dynref = NULL, unsigned long relType = 0); + relocationEntry(Offset ra, std::string n, Symbol *dynref = NULL, + unsigned long relType = 0, Region::RegionType rtype = Region::RT_REL); + relocationEntry(Offset ta, Offset ra, Offset add, + std::string n, Symbol *dynref = NULL, unsigned long relType = 0, + Region::RegionType rtype = Region::RT_REL); + + Offset target_addr() const; + Offset rel_addr() const; + Offset addend() const; + Region::RegionType regionType() const; + const std::string &name() const; + Symbol *getDynSym() const; + bool addDynSym(Symbol *dynref); + unsigned long getRelType() const; + + void setTargetAddr(const Offset); + void setRelAddr(const Offset); + void setAddend(const Offset); + void setRegionType(const Region::RegionType); + void setName(const std::string &newName); + void setRelType(unsigned long relType) { relType_ = relType; } + + // dump output. Currently setup as a debugging aid, not really + // for object persistance.... + //std::ostream & operator<<(std::ostream &s) const; + friend SYMTAB_EXPORT std::ostream & operator<<(std::ostream &os, const relocationEntry &q); + + enum {pltrel = 1, dynrel = 2}; + bool operator==(const relocationEntry &) const; + + enum category { relative, jump_slot, absolute }; + + // Architecture-specific functions + static unsigned long getGlobalRelType(unsigned addressWidth, Symbol *sym = NULL); + static const char *relType2Str(unsigned long r, unsigned addressWidth = sizeof(Address)); + category getCategory( unsigned addressWidth ); + + private: + Offset target_addr_; // target address of call instruction + Offset rel_addr_; // address of corresponding relocation entry + Offset addend_; // addend (from RELA entries) + Region::RegionType rtype_; // RT_REL vs. RT_RELA + std::string name_; + Symbol *dynref_; + unsigned long relType_; + Offset rel_struct_addr_; +}; + + +// relocation information for calls to functions not in this image +SYMTAB_EXPORT std::ostream &operator<<(std::ostream &os, const relocationEntry &q); + +}//namespace SymtabAPI + +}//namespace Dyninst +#endif diff --git a/symtabAPI/h/symutil.h b/symtabAPI/h/symutil.h index 6ecd8f013d..0f0b1b9bf8 100644 --- a/symtabAPI/h/symutil.h +++ b/symtabAPI/h/symutil.h @@ -61,7 +61,6 @@ typedef enum { lang_CPlusPlus, lang_GnuCPlusPlus, lang_Fortran, - lang_Fortran_with_pretty_debug, lang_CMFortran } supportedLanguages; diff --git a/symtabAPI/src/Aggregate.C b/symtabAPI/src/Aggregate.C index 2fc69358df..c0dbdb5da4 100644 --- a/symtabAPI/src/Aggregate.C +++ b/symtabAPI/src/Aggregate.C @@ -27,6 +27,7 @@ * License along with this library; if not, write to the Free Software * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include "dyntypes.h" #include "Annotatable.h" @@ -92,7 +93,7 @@ unsigned Aggregate::getSize() const Region * Aggregate::getRegion() const { - boost::unique_lock l(lock_); + dyncompat::unique_lock l(lock_); if (!firstSymbol) { create_printf("%s[%d]: ERROR: Aggregate w/out symbols\n", FILE__, __LINE__); @@ -103,16 +104,12 @@ Region * Aggregate::getRegion() const bool Aggregate::addSymbol(Symbol *sym) { - // We keep a "primary" module, which is defined as "anything not DEFAULT_MODULE". + // We keep a "primary" module. if (module_ == NULL) { module_ = sym->getModule(); } - else if (module_->fileName() == "DEFAULT_MODULE") { - module_ = sym->getModule(); - } - // else keep current module. - boost::unique_lock l(lock_); + dyncompat::unique_lock l(lock_); // No need to re-add symbols. for (unsigned i = 0; i < symbols_.size(); ++i) @@ -157,7 +154,7 @@ Symbol * Aggregate::getFirstSymbol() const bool Aggregate::addMangledNameInternal(std::string name, bool /*isPrimary*/, bool /*demangle*/) { // Check to see if we're duplicating - boost::unique_lock l(lock_); + dyncompat::unique_lock l(lock_); for (auto i = mangled_names_begin(); i != mangled_names_end(); ++i) @@ -176,7 +173,7 @@ SYMTAB_EXPORT bool Aggregate::addMangledName(string name, bool isPrimary, bool i Symbol *staticSym = NULL; Symbol *dynamicSym = NULL; { - boost::unique_lock l(lock_); + dyncompat::unique_lock l(lock_); for (unsigned i = 0; i < symbols_.size(); ++i) { if (symbols_[i]->isInDynSymtab()) { dynamicSym = symbols_[i]; @@ -211,7 +208,7 @@ SYMTAB_EXPORT bool Aggregate::addPrettyName(string name, bool isPrimary, bool is { // Check to see if we're duplicating { - boost::unique_lock l(lock_); + dyncompat::unique_lock l(lock_); for (auto i = pretty_names_begin(); i != pretty_names_end(); i++) { @@ -226,7 +223,7 @@ SYMTAB_EXPORT bool Aggregate::addTypedName(string name, bool isPrimary, bool isD { // Check to see if we're duplicating { - boost::unique_lock l(lock_); + dyncompat::unique_lock l(lock_); for (auto i = typed_names_begin(); i != typed_names_end(); i++) { @@ -260,7 +257,7 @@ bool Aggregate::changeSymbolOffset(Symbol *sym) } void Aggregate::print(std::ostream &os) const { - std::string modname = module_ ? module_->fullName() : std::string("no_mod"); + std::string modname = module_ ? module_->fileName() : std::string("no_mod"); os << "Aggregate{" << " Module=" << modname << " MangledNames=["; @@ -283,7 +280,7 @@ bool Aggregate::operator==(const Aggregate &a) if (symbols_.size() != a.symbols_.size()) return false; if (module_ && !a.module_) return false; if (!module_ && a.module_) return false; - if (module_ && (module_->fullName() != a.module_->fullName())) return false; + if (module_ && (module_->fileName() != a.module_->fileName())) return false; for (unsigned int i = 0; i < symbols_.size(); ++i) { @@ -307,26 +304,26 @@ bool Aggregate::operator==(const Aggregate &a) Aggregate::name_iter Aggregate::mangled_names_begin() const { - return boost::make_transform_iterator(symbols_.begin(), std::mem_fun(&Symbol::getMangledName)); + return dyncompat::make_transform_iterator(symbols_.cbegin(), std::mem_fn(&Symbol::getMangledName)); } Aggregate::name_iter Aggregate::mangled_names_end() const { - return boost::make_transform_iterator(symbols_.end(), std::mem_fun(&Symbol::getMangledName)); + return dyncompat::make_transform_iterator(symbols_.cend(), std::mem_fn(&Symbol::getMangledName)); } Aggregate::name_iter Aggregate::pretty_names_begin() const { - return boost::make_transform_iterator(symbols_.begin(), std::mem_fun(&Symbol::getPrettyName)); + return dyncompat::make_transform_iterator(symbols_.cbegin(), std::mem_fn(&Symbol::getPrettyName)); } Aggregate::name_iter Aggregate::pretty_names_end() const { - return boost::make_transform_iterator(symbols_.end(), std::mem_fun(&Symbol::getPrettyName)); + return dyncompat::make_transform_iterator(symbols_.cend(), std::mem_fn(&Symbol::getPrettyName)); } Aggregate::name_iter Aggregate::typed_names_begin() const { - return boost::make_transform_iterator(symbols_.begin(), std::mem_fun(&Symbol::getTypedName)); + return dyncompat::make_transform_iterator(symbols_.cbegin(), std::mem_fn(&Symbol::getTypedName)); } Aggregate::name_iter Aggregate::typed_names_end() const { - return boost::make_transform_iterator(symbols_.end(), std::mem_fun(&Symbol::getTypedName)); + return dyncompat::make_transform_iterator(symbols_.cend(), std::mem_fn(&Symbol::getTypedName)); } diff --git a/symtabAPI/src/Archive.C b/symtabAPI/src/Archive.C index f0ac69c3ce..7d7bf967c5 100644 --- a/symtabAPI/src/Archive.C +++ b/symtabAPI/src/Archive.C @@ -28,6 +28,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include "symtabAPI/h/Symtab.h" #include "symtabAPI/h/Archive.h" #include "symtabAPI/src/Object.h" @@ -95,7 +96,7 @@ bool Archive::openArchive(Archive * &img, std::string filename) for (ar_it = allArchives.begin(); ar_it != allArchives.end(); ++ar_it) { assert( *ar_it != NULL ); - if( (*ar_it)->mf->pathname() == filename ) { + if( (*ar_it)->mf->filename() == filename ) { img = *ar_it; return true; } diff --git a/symtabAPI/src/Collections.C b/symtabAPI/src/Collections.C index 601bf95772..77e8385781 100644 --- a/symtabAPI/src/Collections.C +++ b/symtabAPI/src/Collections.C @@ -28,6 +28,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include #include @@ -113,29 +114,29 @@ const dyn_c_vector &localVarCollection::getAllVars() const // Could be somewhere else... for DWARF-work. dyn_c_hash_map typeCollection::fileToTypesMap; -dyn_hash_map*> > *> *deferred_lookups_p = NULL; +dyn_hash_map*> > *> *deferred_lookups_p = NULL; -void typeCollection::addDeferredLookup(int tid, dataClass tdc, boost::shared_ptr*th) +void typeCollection::addDeferredLookup(int tid, dataClass tdc, dyncompat::shared_ptr*th) { if (!deferred_lookups_p) - deferred_lookups_p = new dyn_hash_map*> > *>(); + deferred_lookups_p = new dyn_hash_map*> > *>(); auto& deferred_lookups = *deferred_lookups_p; auto iter = deferred_lookups.find(tid); if (iter == deferred_lookups.end()) - deferred_lookups[tid] = new std::vector *> >(); + deferred_lookups[tid] = new std::vector *> >(); deferred_lookups[tid]->push_back(std::make_pair(tdc, th)); } bool typeCollection::doDeferredLookups(typeCollection *primary_tc) { if (!deferred_lookups_p) return true; // nothing to do - dyn_hash_map*> > *> &deferred_lookups = *deferred_lookups_p; + dyn_hash_map*> > *> &deferred_lookups = *deferred_lookups_p; bool err = false; - dyn_hash_map*> > *>::iterator iter; + dyn_hash_map*> > *>::iterator iter; for (iter = deferred_lookups.begin(); iter != deferred_lookups.end(); iter++) { - std::vector*> > *to_assign = iter->second; + std::vector*> > *to_assign = iter->second; if (!to_assign->size()) { continue; @@ -144,9 +145,9 @@ bool typeCollection::doDeferredLookups(typeCollection *primary_tc) for (unsigned int i = 0; i < to_assign->size(); ++i) { dataClass ldc = (*to_assign)[i].first; - boost::shared_ptr*th = (*to_assign)[i].second; + dyncompat::shared_ptr*th = (*to_assign)[i].second; - boost::shared_ptr t = primary_tc->findType(iter->first, Type::share); + dyncompat::shared_ptr t = primary_tc->findType(iter->first, Type::share); if (t && (t->getDataClass() != ldc)) t = NULL; if (!t) @@ -167,17 +168,15 @@ bool typeCollection::doDeferredLookups(typeCollection *primary_tc) } if (!t) { - int nfound = 0; dyn_c_hash_map::iterator tciter; for (tciter = fileToTypesMap.begin(); tciter != fileToTypesMap.end(); tciter++) { if (tciter->second == primary_tc) continue; - boost::shared_ptr localt = tciter->second->findType(iter->first, Type::share); + dyncompat::shared_ptr localt = tciter->second->findType(iter->first, Type::share); if (localt) { if (localt->getDataClass() != ldc) continue; - nfound++; t = localt; } //if (t) break; @@ -253,41 +252,41 @@ typeCollection::~typeCollection() {} * name The name of the type to look up. * id The unique type ID of the type tp look up. */ -boost::shared_ptr typeCollection::findType(std::string name, Type::do_share_t) +dyncompat::shared_ptr typeCollection::findType(std::string name, Type::do_share_t) { - dyn_c_hash_map>::const_accessor a; + dyn_c_hash_map>::const_accessor a; if (typesByName.find(a, name)) return a->second; else if (Symtab::builtInTypes()) return Symtab::builtInTypes()->findBuiltInType(name, Type::share); else - return boost::shared_ptr(); + return dyncompat::shared_ptr(); } -boost::shared_ptr typeCollection::findTypeLocal(std::string name, Type::do_share_t) +dyncompat::shared_ptr typeCollection::findTypeLocal(std::string name, Type::do_share_t) { - dyn_c_hash_map>::const_accessor a; + dyn_c_hash_map>::const_accessor a; if (typesByName.find(a, name)) return a->second; else - return boost::shared_ptr(); + return dyncompat::shared_ptr(); } -boost::shared_ptr typeCollection::findTypeLocal(const int ID, Type::do_share_t) +dyncompat::shared_ptr typeCollection::findTypeLocal(const int ID, Type::do_share_t) { - dyn_c_hash_map>::const_accessor a; + dyn_c_hash_map>::const_accessor a; if (typesByID.find(a, ID)) return a->second; else - return boost::shared_ptr(); + return dyncompat::shared_ptr(); } -boost::shared_ptr typeCollection::findOrCreateType( const int ID, Type::do_share_t) +dyncompat::shared_ptr typeCollection::findOrCreateType( const int ID, Type::do_share_t) { - dyn_c_hash_map>::const_accessor ca; + dyn_c_hash_map>::const_accessor ca; if (typesByID.find(ca, ID)) { return ca->second; @@ -295,7 +294,7 @@ boost::shared_ptr typeCollection::findOrCreateType( const int ID, Type::do if ( Symtab::builtInTypes() ) { - boost::shared_ptr returnType = Symtab::builtInTypes()->findBuiltInType(ID, Type::share); + dyncompat::shared_ptr returnType = Symtab::builtInTypes()->findBuiltInType(ID, Type::share); if (returnType) return returnType; @@ -303,8 +302,8 @@ boost::shared_ptr typeCollection::findOrCreateType( const int ID, Type::do // If someone else added a placeholder in the meanwhile, return that. // Note: name == "", so typesByName doesn't need updated. - dyn_c_hash_map>::accessor a; - if (!typesByID.insert(a, {ID, boost::shared_ptr()})) + dyn_c_hash_map>::accessor a; + if (!typesByID.insert(a, {ID, dyncompat::shared_ptr()})) { return a->second; } @@ -316,14 +315,14 @@ boost::shared_ptr typeCollection::findOrCreateType( const int ID, Type::do return a->second; } /* end findOrCreateType() */ -boost::shared_ptr typeCollection::findType(const int ID, Type::do_share_t) +dyncompat::shared_ptr typeCollection::findType(const int ID, Type::do_share_t) { - dyn_c_hash_map>::const_accessor a; + dyn_c_hash_map>::const_accessor a; if (typesByID.find(a, ID)) return a->second; else { - boost::shared_ptr ret = NULL; + dyncompat::shared_ptr ret = NULL; if (Symtab::builtInTypes()) ret = Symtab::builtInTypes()->findBuiltInType(ID, Type::share); @@ -341,13 +340,13 @@ boost::shared_ptr typeCollection::findType(const int ID, Type::do_share_t) * * name The name of the type to look up. */ -boost::shared_ptr typeCollection::findVariableType(std::string &name, Type::do_share_t) +dyncompat::shared_ptr typeCollection::findVariableType(std::string &name, Type::do_share_t) { - dyn_c_hash_map>::const_accessor a; + dyn_c_hash_map>::const_accessor a; if (globalVarsByName.find(a, name)) return a->second; else - return boost::shared_ptr(); + return dyncompat::shared_ptr(); } /* @@ -358,9 +357,9 @@ boost::shared_ptr typeCollection::findVariableType(std::string &name, Type * when it is no longer needed. For one thing, this means that a type * allocated on the stack should *NEVER* be put into a typeCollection. */ -void typeCollection::addType(boost::shared_ptr type) +void typeCollection::addType(dyncompat::shared_ptr type) { - dyn_c_hash_map>::accessor a; + dyn_c_hash_map>::accessor a; if(!typesByID.insert({type->getID(), type})) return; // Type is already present if(type->getName() != "") { //Type could have no name. @@ -368,7 +367,7 @@ void typeCollection::addType(boost::shared_ptr type) } } -void typeCollection::addGlobalVariable(boost::shared_ptr type) +void typeCollection::addGlobalVariable(dyncompat::shared_ptr type) { globalVarsByName.insert({type->getName(), type}); } @@ -382,7 +381,7 @@ void typeCollection::clearNumberedTypes() * localVarCollection::getAllVars() * this function returns all the local variables in the collection. */ -void typeCollection::getAllTypes(std::vector>& vec) { +void typeCollection::getAllTypes(std::vector>& vec) { for (auto it = typesByName.begin(); it != typesByName.end(); it ++) { @@ -390,7 +389,7 @@ void typeCollection::getAllTypes(std::vector>& vec) { } } -void typeCollection::getAllGlobalVariables(vector>>& vec) { +void typeCollection::getAllGlobalVariables(vector>>& vec) { for(auto it = globalVarsByName.begin(); it != globalVarsByName.end(); it++) { vec.push_back(make_pair(it->first, it->second)); @@ -433,25 +432,25 @@ builtInTypeCollection::~builtInTypeCollection() * name The name of the type to look up. * id The unique type ID of the type tp look up. */ -boost::shared_ptr builtInTypeCollection::findBuiltInType(std::string &name, Type::do_share_t) +dyncompat::shared_ptr builtInTypeCollection::findBuiltInType(std::string &name, Type::do_share_t) { - dyn_c_hash_map>::const_accessor a; + dyn_c_hash_map>::const_accessor a; if (builtInTypesByName.find(a, name)) return a->second; else - return boost::shared_ptr(); + return dyncompat::shared_ptr(); } -boost::shared_ptr builtInTypeCollection::findBuiltInType(const int ID, Type::do_share_t) +dyncompat::shared_ptr builtInTypeCollection::findBuiltInType(const int ID, Type::do_share_t) { - dyn_c_hash_map>::const_accessor a; + dyn_c_hash_map>::const_accessor a; if (builtInTypesByID.find(a, ID)) return a->second; else - return boost::shared_ptr(); + return dyncompat::shared_ptr(); } -void builtInTypeCollection::addBuiltInType(boost::shared_ptr type) +void builtInTypeCollection::addBuiltInType(dyncompat::shared_ptr type) { if(type->getName() != "") { //Type could have no name. { @@ -465,7 +464,7 @@ void builtInTypeCollection::addBuiltInType(boost::shared_ptr type) } } -void builtInTypeCollection::getAllBuiltInTypes(std::vector>& vec) { +void builtInTypeCollection::getAllBuiltInTypes(std::vector>& vec) { for (auto it = builtInTypesByID.begin(); it != builtInTypesByID.end(); it ++) { diff --git a/common/src/stringDecl.h b/symtabAPI/src/ExceptionBlock.C similarity index 58% rename from common/src/stringDecl.h rename to symtabAPI/src/ExceptionBlock.C index 670c1d1946..7653119f79 100644 --- a/common/src/stringDecl.h +++ b/symtabAPI/src/ExceptionBlock.C @@ -1,66 +1,78 @@ /* * See the dyninst/COPYRIGHT file for copyright information. - * + * * We provide the Paradyn Tools (below described as "Paradyn") * on an AS IS basis, and do not warrant its validity or performance. * We reserve the right to update, modify, or discontinue this * software at any time. We shall have no obligation to supply such * updates or modifications or any other form of support to you. - * + * * By your use of Paradyn, you understand and agree that we (or any * other person or entity with proprietary rights in Paradyn) are * under no obligation to provide either maintenance services, * update services, notices of latent defects, or correction of * defects for Paradyn. - * * This library is free software; you can redistribute it and/or * modify it under the terms of the GNU Lesser General Public * License as published by the Free Software Foundation; either * version 2.1 of the License, or (at your option) any later version. - * + * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU * Lesser General Public License for more details. - * + * * You should have received a copy of the GNU Lesser General Public * License along with this library; if not, write to the Free Software * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include "ExceptionBlock.h" -#ifndef _STRING_DECL_H -#define _STRING_DECL_H -/* - * $Log: stringDecl.h,v $ - * Revision 1.6 2007/05/30 19:20:07 legendre - * Update copyright notice to LGPL - * - * Revision 1.5 2005/12/19 19:41:40 pack - * MRNet replaces xdr for frontend to daemon communication. New igen - - - - * MRNet changes - * - * Revision 1.1.1.1 2004/11/05 22:17:36 darnold - * start - * - * Revision 1.1.1.1 2004/10/18 20:35:55 darnold - * Manual Branch for MRNet Integration based on Release_4.1 - * - * Revision 1.4 2004/03/23 01:11:53 eli - * Updated copyright string - * - * Revision 1.3 1996/08/16 21:30:46 tamches - * updated copyright for release 1.1 - * - * Revision 1.2 1994/09/02 19:42:46 markc - * Added missing semicolon to end of typedef - * - * Revision 1.1 1994/09/02 10:43:50 markc - * Moved typedef for stringHandle outside of stringPool.h - * - */ +namespace Dyninst { +namespace SymtabAPI { + + +SYMTAB_EXPORT ExceptionBlock::ExceptionBlock(Offset tStart, + unsigned tSize, + Offset cStart) +: tryStart_(tStart), trySize_(tSize), catchStart_(cStart), hasTry_(true), + tryStart_ptr(0), tryEnd_ptr(0), catchStart_ptr(0), fdeStart_ptr(0), fdeEnd_ptr(0) +{ +} + + SYMTAB_EXPORT ExceptionBlock::ExceptionBlock(Offset cStart) +: tryStart_(0), trySize_(0), catchStart_(cStart), hasTry_(false), + tryStart_ptr(0), tryEnd_ptr(0), catchStart_ptr(0), fdeStart_ptr(0), fdeEnd_ptr(0) +{ +} + +SYMTAB_EXPORT bool ExceptionBlock::hasTry() const +{ + return hasTry_; +} + +SYMTAB_EXPORT Offset ExceptionBlock::tryStart() const +{ + return tryStart_; +} + +SYMTAB_EXPORT Offset ExceptionBlock::tryEnd() const +{ + return tryStart_ + trySize_; +} + +SYMTAB_EXPORT Offset ExceptionBlock::trySize() const +{ + return trySize_; +} + +SYMTAB_EXPORT bool ExceptionBlock::contains(Offset a) const +{ + return (a >= tryStart_ && a < tryStart_ + trySize_); +} -typedef void *stringHandle; -#endif /* _STRING_DECL_H */ +} +} diff --git a/symtabAPI/src/Function.C b/symtabAPI/src/Function.C index bff659bde9..4070d0d9da 100644 --- a/symtabAPI/src/Function.C +++ b/symtabAPI/src/Function.C @@ -37,6 +37,7 @@ #include "Function.h" #include "VariableLocation.h" #include "Object.h" +#include "registers/abstract_regs.h" #if !defined(os_windows) #include "dwarfFrameParser.h" @@ -62,13 +63,13 @@ FunctionBase::FunctionBase() : { } -boost::shared_ptr FunctionBase::getReturnType(Type::do_share_t) const +dyncompat::shared_ptr FunctionBase::getReturnType(Type::do_share_t) const { getModule()->exec()->parseTypesNow(); return retType_; } -bool FunctionBase::setReturnType(boost::shared_ptr newType) +bool FunctionBase::setReturnType(dyncompat::shared_ptr newType) { retType_ = newType; return true; @@ -391,7 +392,7 @@ std::ostream &operator<<(std::ostream &os, const Dyninst::VariableLocation &l) std::ostream &operator<<(std::ostream &os, const Dyninst::SymtabAPI::Function &f) { - boost::shared_ptr retType = (const_cast(f)).getReturnType(Type::share); + dyncompat::shared_ptr retType = (const_cast(f)).getReturnType(Type::share); std::string tname(retType ? retType->getName() : "no_type"); const Aggregate *ag = dynamic_cast(&f); @@ -444,7 +445,7 @@ InlinedFunction::InlinedFunction(FunctionBase *parent) : { inline_parent = parent; offset_ = parent->getOffset(); - boost::unique_lock l(parent->inlines_lock); + dyncompat::unique_lock l(parent->inlines_lock); parent->inlines.push_back(this); } @@ -486,12 +487,8 @@ unsigned InlinedFunction::getSize() const void InlinedFunction::setFile(string filename) { StringTablePtr strs = module_->getStrings(); - boost::unique_lock l(strs->lock); - // This looks gross, but here's what it does: - // Get index 1 (unique by name). Insert the filename on that index (which defaults to push_back if empty). - // Returns an ; get the iterator (we don't care if it's new). Project to random access (index 0). - // Difference from begin == array index in string table. - callsite_file_number = strs->project<0>(strs->get<1>().insert(StringTableEntry(filename,"")).first) - strs->begin(); + dyncompat::unique_lock l(strs->lock); + callsite_file_number = strs->ensure(std::move(filename)); } Module* Function::getModule() const { diff --git a/symtabAPI/src/LineInformation.C b/symtabAPI/src/LineInformation.C index 56c3ad6169..b65b4c2e55 100644 --- a/symtabAPI/src/LineInformation.C +++ b/symtabAPI/src/LineInformation.C @@ -28,16 +28,16 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include +#include #include #include -#include -#include "boost/functional/hash.hpp" #include "common/src/headers.h" #include "Module.h" -#include #include +#include using namespace Dyninst; using namespace Dyninst::SymtabAPI; @@ -46,9 +46,40 @@ using std::vector; #include "LineInformation.h" #include -LineInformation::LineInformation() :strings_(new StringTable), wasted_compares(0), num_queries(0) +LineInformation::LineInformation() :strings_(new StringTable) { -} /* end LineInformation constructor */ +} + +bool LineInformation::StatementAddrLess::operator()(Statement::Ptr lhs, Statement::Ptr rhs) const +{ + if (lhs->startAddr() != rhs->startAddr()) return lhs->startAddr() < rhs->startAddr(); + if (lhs->endAddr() != rhs->endAddr()) return lhs->endAddr() < rhs->endAddr(); + if (lhs->getFileIndex() != rhs->getFileIndex()) return lhs->getFileIndex() < rhs->getFileIndex(); + if (lhs->getLine() != rhs->getLine()) return lhs->getLine() < rhs->getLine(); + if (lhs->getColumn() != rhs->getColumn()) return lhs->getColumn() < rhs->getColumn(); + return false; +} + +bool LineInformation::LineInfoKeyLess::operator()(const LineInfoKey &lhs, const LineInfoKey &rhs) const +{ + if (lhs.file_index != rhs.file_index) return lhs.file_index < rhs.file_index; + return lhs.line < rhs.line; +} + +LineInformation::LineInfoKey LineInformation::make_key(unsigned int file_index, unsigned int line_no) +{ + return LineInfoKey{file_index, line_no}; +} + +std::pair LineInformation::insert(Statement::Ptr statement) +{ + auto inserted = by_addr_.insert(statement); + if (inserted.second) { + by_line_.emplace(make_key(statement->getFileIndex(), statement->getLine()), statement); + by_end_.emplace(statement->endAddr(), statement); + } + return inserted; +} bool LineInformation::addLine( unsigned int lineSource, unsigned int lineNo, @@ -56,30 +87,42 @@ bool LineInformation::addLine( unsigned int lineSource, Offset lowInclusiveAddr, Offset highExclusiveAddr ) { + if (lowInclusiveAddr == highExclusiveAddr) { + // if the range is [low, low), adjust it to be [low, low + 1) + // as the DWARF spec says the address is include along with any + // subsequent address up to but not including the next records address + ++highExclusiveAddr; + } Statement* the_stmt = new Statement(lineSource, lineNo, lineOffset, lowInclusiveAddr, highExclusiveAddr); Statement::Ptr insert_me(the_stmt); insert_me->setStrings_(strings_); - return insert( insert_me).second; - -} /* end setLineToAddressRangeMapping() */ -bool LineInformation::addLine( std::string lineSource, + bool result; +#pragma omp critical (addLine) +{ + result = insert( insert_me).second; +} + return result; +} +bool LineInformation::addLine( const std::string &lineSource, unsigned int lineNo, unsigned int lineOffset, Offset lowInclusiveAddr, Offset highExclusiveAddr ) { - auto i = strings_->get<1>().insert(StringTableEntry(lineSource,"")).first; - - return addLine(i->str, lineNo, lineOffset, lowInclusiveAddr, highExclusiveAddr); + auto i = strings_->ensure(lineSource); + return addLine(static_cast(i), lineNo, lineOffset, lowInclusiveAddr, highExclusiveAddr); } void LineInformation::addLineInfo(LineInformation *lineInfo) { if(!lineInfo) return; +#pragma omp critical (addLine) +{ insert(lineInfo->begin(), lineInfo->end()); } +} bool LineInformation::addAddressRange( Offset lowInclusiveAddr, Offset highExclusiveAddr, @@ -88,7 +131,7 @@ bool LineInformation::addAddressRange( Offset lowInclusiveAddr, unsigned int lineOffset ) { return addLine( lineSource, lineNo, lineOffset, lowInclusiveAddr, highExclusiveAddr ); -} /* end setAddressRangeToLineMapping() */ +} std::string print(const Dyninst::SymtabAPI::Statement& stmt) @@ -103,18 +146,13 @@ std::string print(const Dyninst::SymtabAPI::Statement& stmt) bool LineInformation::getSourceLines(Offset addressInRange, vector &lines) { - const_iterator start_addr_valid = project(get().lower_bound(addressInRange )); - const_iterator end_addr_valid = impl_t::upper_bound(addressInRange ); - while(start_addr_valid != end_addr_valid && start_addr_valid != end()) - { - if(*(*start_addr_valid) == addressInRange) - { - lines.push_back(*start_addr_valid); + for (auto iter = by_end_.upper_bound(addressInRange); iter != by_end_.end(); ++iter) { + if (*(iter->second) == addressInRange) { + lines.push_back(iter->second); } - ++start_addr_valid; } return true; -} /* end getLinesFromAddress() */ +} bool LineInformation::getSourceLines( Offset addressInRange, vector &lines) @@ -126,7 +164,7 @@ bool LineInformation::getSourceLines( Offset addressInRange, lines.push_back(**i); } return true; -} /* end getLinesFromAddress() */ +} @@ -138,87 +176,74 @@ bool LineInformation::getAddressRanges( const char * lineSource, i != found_statements.second; ++i) { - ranges.push_back(AddressRange(**i)); + ranges.push_back(AddressRange(*(i->second))); } return found_statements.first != found_statements.second; -} /* end getAddressRangesFromLine() */ +} LineInformation::const_iterator LineInformation::begin() const { - return impl_t::begin(); -} /* end begin() */ + return by_addr_.begin(); +} LineInformation::const_iterator LineInformation::end() const { - return impl_t::end(); -} /* end end() */ + return by_addr_.end(); +} LineInformation::const_iterator LineInformation::find(Offset addressInRange) const { - const_iterator start_addr_valid = project(get().lower_bound(addressInRange )); - if(start_addr_valid == end()) return end(); - const_iterator end_addr_valid = impl_t::upper_bound(addressInRange + 1); - while(start_addr_valid != end_addr_valid && start_addr_valid != end()) - { - if(*(*start_addr_valid) == addressInRange) - { - return start_addr_valid; + for (auto iter = by_addr_.begin(); iter != by_addr_.end(); ++iter) { + if (**iter == addressInRange) { + return iter; } - ++start_addr_valid; } return end(); -} /* end find() */ - - - -unsigned LineInformation::getSize() const -{ - return impl_t::size(); } -LineInformation::~LineInformation() +unsigned LineInformation::getSize() const { - impl_t::clear_(); + return by_addr_.size(); } LineInformation::const_line_info_iterator LineInformation::begin_by_source() const { - const traits::line_info_index& i = impl_t::get(); - return i.begin(); + return by_line_.begin(); } LineInformation::const_line_info_iterator LineInformation::end_by_source() const { - const traits::line_info_index& i = impl_t::get(); - return i.end(); + return by_line_.end(); } std::pair -LineInformation::range(std::string file, const unsigned int lineNo) const +LineInformation::range(std::string const& file, const unsigned int lineNo) const { - using namespace boost::filesystem; - auto found_range = strings_->get<2>().equal_range(path(file).filename().string()); + namespace fs = std::filesystem; + auto found_range = strings_->find_by_filename(fs::path(file).filename().string()); std::pair bounds; - for(auto found = found_range.first; ((found != found_range.second) && (found != strings_->get<2>().end())); ++found) + for(auto found : found_range) { - unsigned i = strings_->project<0>(found) - strings_->begin(); - auto idx = boost::make_tuple(i, lineNo); - bounds = get().equal_range(idx); + bounds = by_line_.equal_range(make_key(static_cast(found), lineNo)); if(bounds.first != bounds.second) { return bounds; } } - bounds = make_pair(get().end(), get().end()); + bounds = std::make_pair(by_line_.end(), by_line_.end()); return bounds; } std::pair -LineInformation::equal_range(std::string file) const { - auto found = strings_->get<1>().find(file); - unsigned i = strings_->project<0>(found) - strings_->begin(); - return get().equal_range(i); +LineInformation::equal_range(std::string const& file) const { + auto found = strings_->find(file); + if (!found) { + return std::make_pair(by_line_.end(), by_line_.end()); + } + return std::make_pair(by_line_.lower_bound(make_key(static_cast(*found), 0)), + by_line_.upper_bound(make_key(static_cast(*found), + std::numeric_limits::max()))); } StringTablePtr LineInformation::getStrings() { @@ -258,6 +283,3 @@ void LineInformation::dump() std::endl; } } - -/* end LineInformation destructor */ - diff --git a/symtabAPI/src/LinkMap.C b/symtabAPI/src/LinkMap.C index df23ce7f44..9579987664 100644 --- a/symtabAPI/src/LinkMap.C +++ b/symtabAPI/src/LinkMap.C @@ -28,6 +28,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include "LinkMap.h" #include diff --git a/symtabAPI/src/LinkMap.h b/symtabAPI/src/LinkMap.h index f039fcb9a3..fdfb65a415 100644 --- a/symtabAPI/src/LinkMap.h +++ b/symtabAPI/src/LinkMap.h @@ -36,6 +36,8 @@ #include "Symbol.h" #include "Function.h" +#include +#include #include #include #include diff --git a/symtabAPI/src/Module.C b/symtabAPI/src/Module.C index c969e57c78..b62a027d5c 100644 --- a/symtabAPI/src/Module.C +++ b/symtabAPI/src/Module.C @@ -45,69 +45,22 @@ #include "common/src/pathName.h" #include "Object.h" -#include +#include +#include #if defined(cap_dwarf) #include "dwarfWalker.h" #include "dwarf.h" #endif +#include + using namespace Dyninst; using namespace Dyninst::SymtabAPI; using namespace std; static SymtabError serr; -StringTablePtr Statement::getStrings_() const { - return strings_; -} - -void Statement::setStrings_(StringTablePtr strings) { - Statement::strings_ = strings; -} -const std::string& Statement::getFile() const { - if(strings_) { - if(file_index_ < strings_->size()) { - // can't be ->[] on shared pointer to multi_index container or compiler gets confused - return (*strings_)[file_index_].str; - - } - - } - // This string will be pointed to, so it has to persist. - static std::string emptyStr; - return emptyStr; -} - -string Module::getCompDir(Module::DebugInfoT& cu) -{ - if(!compDir_.empty()) return compDir_; - -#if defined(cap_dwarf) - if(!dwarf_hasattr(&cu, DW_AT_comp_dir)) - { - return ""; - } - - Dwarf_Attribute attr; - auto comp_dir = dwarf_formstring( dwarf_attr(&cu, DW_AT_comp_dir, &attr) ); - compDir_ = std::string( comp_dir ? comp_dir : "" ); - return compDir_; - -#else - // TODO Implement this for non-dwarf format - return compDir_; -#endif -} - -string Module::getCompDir() -{ - if(!compDir_.empty()) return compDir_; - - return ""; -} - - bool Module::findSymbol(std::vector &found, const std::string& name, Symbol::SymbolType sType, @@ -159,7 +112,7 @@ const std::string &Module::fileName() const const std::string &Module::fullName() const { - return fullName_; + return fileName(); } Symtab *Module::exec() const @@ -218,33 +171,21 @@ bool Module::getSourceLines(std::vector &lines, Offset addressInRan } LineInformation *Module::parseLineInformation() { - bool popped = false; - Module::DebugInfoT cu; - if (exec()->getArchitecture() != Arch_cuda && - (exec()->getObject()->hasDebugInfo() || (popped = info_.try_pop(cu)) )) { - // Allocate if none - if (!lineInfo_) { - lineInfo_ = new LineInformation; - // share our string table - lineInfo_->setStrings(strings_); - } - - // Parse any CUs that have been added to our list - if(popped || info_.try_pop(cu)) { - Module::DebugInfoT cu2 = cu; - do { - exec()->getObject()->parseLineInfoForCU(cu2, lineInfo_); - } while(info_.try_pop(cu2)); + if(lineInfo_) return lineInfo_; - // Make sure to call getCompDir so its stored and ready. - getCompDir(cu); - } + const bool is_cuda = exec()->getArchitecture() == Arch_cuda; + const bool debug_info = exec()->getObject()->hasDebugInfo(); - // Work queue has now been emptied. - } else if (!lineInfo_) { - objectLevelLineInfo = true; - lineInfo_ = exec()->getObject()->parseLineInfoForObject(strings_); + if (!debug_info || is_cuda) { + objectLevelLineInfo = true; + lineInfo_ = exec()->getObject()->parseLineInfoForObject(strings_); + return lineInfo_; } + + lineInfo_ = new LineInformation; + lineInfo_->setStrings(strings_); + + exec()->getObject()->parseLineInfoForCU(addr(), lineInfo_); return lineInfo_; } @@ -259,13 +200,13 @@ bool Module::getStatements(std::vector &statements return (statements.size() > initial_size); } -void Module::getAllTypes(vector>& v) +void Module::getAllTypes(vector>& v) { exec_->parseTypesNow(); if(typeInfo_) typeInfo_->getAllTypes(v); } -void Module::getAllGlobalVars(vector>>& v) +void Module::getAllGlobalVars(vector>>& v) { exec_->parseTypesNow(); if(typeInfo_) typeInfo_->getAllGlobalVariables(v); @@ -282,7 +223,7 @@ typeCollection *Module::getModuleTypesPrivate() return typeInfo_; } -bool Module::findType(boost::shared_ptr &type, std::string name) +bool Module::findType(dyncompat::shared_ptr &type, std::string name) { typeCollection *tc = getModuleTypes(); if (!tc) return false; @@ -295,7 +236,7 @@ bool Module::findType(boost::shared_ptr &type, std::string name) return true; } -bool Module::findVariableType(boost::shared_ptr &type, std::string name) +bool Module::findVariableType(dyncompat::shared_ptr &type, std::string name) { typeCollection *tc = getModuleTypes(); if (!tc) return false; @@ -349,29 +290,23 @@ Module::Module(supportedLanguages lang, Offset adr, objectLevelLineInfo(false), lineInfo_(NULL), typeInfo_(NULL), - fullName_(fullNm), + fileName_(fullNm), compDir_(""), language_(lang), addr_(adr), exec_(img), - strings_(new StringTable), - ranges_finalized(false) -{ - fileName_ = extract_pathname_tail(fullNm); -} + strings_(new StringTable) +{} Module::Module() : objectLevelLineInfo(false), lineInfo_(NULL), typeInfo_(NULL), fileName_(""), - fullName_(""), - compDir_(""), language_(lang_Unknown), addr_(0), exec_(NULL), - strings_(new StringTable), - ranges_finalized(false) + strings_(new StringTable) { } @@ -380,15 +315,11 @@ Module::Module(const Module &mod) : objectLevelLineInfo(mod.objectLevelLineInfo), lineInfo_(mod.lineInfo_), typeInfo_(mod.typeInfo_), - info_(mod.info_), fileName_(mod.fileName_), - fullName_(mod.fullName_), - compDir_(mod.compDir_), language_(mod.language_), addr_(mod.addr_), exec_(mod.exec_), - strings_(mod.strings_), - ranges_finalized(mod.ranges_finalized) + strings_(mod.strings_) { } @@ -429,9 +360,16 @@ bool Module::getAllSymbolsByType(std::vector &found, Symbol::SymbolTyp return false; } -bool Module::getAllFunctions(std::vector &ret) +std::vector Module::getAllFunctions() const { - return exec()->getAllFunctions(ret); + auto const& all_funcs = exec()->getAllFunctionsRef(); + std::vector funcs; + std::copy_if(all_funcs.begin(), all_funcs.end(), std::back_inserter(funcs), + [this] (Function *f) { + return f->getModule() == this; + } + ); + return funcs; } bool Module::operator==(Module &mod) @@ -447,19 +385,11 @@ bool Module::operator==(Module &mod) return ( (language_==mod.language_) && (addr_==mod.addr_) - && (fullName_==mod.fullName_) && (fileName_==mod.fileName_) && (lineInfo_ == mod.lineInfo_) ); } -bool Module::setName(std::string newName) -{ - fullName_ = newName; - fileName_ = extract_pathname_tail(fullName_); - return true; -} - void Module::setLanguage(supportedLanguages lang) { language_ = lang; @@ -535,38 +465,30 @@ void Module::addRange(Dyninst::Address low, Dyninst::Address high) // exec_->mod_lookup()->insert(new ModRange(low, high, this)); } -void Module::finalizeRanges() +std::vector Module::finalizeRanges() { if(ranges.empty()) { - return; + return {}; } + + std::vector mod_ranges; + mod_ranges.reserve(ranges.size()); + auto bit = ranges.begin(); Address ext_s = bit->first; Address ext_e = ext_s; for( ; bit != ranges.end(); ++bit) { if(bit->first > ext_e) { - finalizeOneRange(ext_s, ext_e); + mod_ranges.push_back(new ModRange(ext_s, ext_e, this)); ext_s = bit->first; } ext_e = bit->second; } - finalizeOneRange(ext_s, ext_e); - ranges_finalized = true; + mod_ranges.push_back(new ModRange(ext_s, ext_e, this)); ranges.clear(); -} - -void Module::finalizeOneRange(Address ext_s, Address ext_e) const { - ModRange* r = new ModRange(ext_s, ext_e, const_cast(this)); - ModRangeLookup* lookup = exec_->mod_lookup(); -// cout << "Inserting range " << std::hex << (*r) << std::dec << endl; - lookup->insert(r); -} - -void Module::addDebugInfo(Module::DebugInfoT info) { -// cout << "Adding CU DIE to " << fileName() << endl; - info_.push(info); + return mod_ranges; } StringTablePtr & Module::getStrings() { diff --git a/symtabAPI/src/Object-elf.C b/symtabAPI/src/Object-elf.C index 822eb588d1..13e0763f5f 100644 --- a/symtabAPI/src/Object-elf.C +++ b/symtabAPI/src/Object-elf.C @@ -33,7 +33,10 @@ * Object-elf.C: Object class for ELF file format ************************************************************************/ +#include #include "common/src/vgannotations.h" +#include "unaligned_memory_access.h" +#include #include "Type.h" #include "Variable.h" @@ -47,6 +50,8 @@ #include "dwarfWalker.h" +#include "Object-elf.h" + using namespace Dyninst; using namespace Dyninst::SymtabAPI; using namespace Dyninst::DwarfDyninst; @@ -59,6 +64,7 @@ using namespace std; #if defined(cap_dwarf) #include "dwarf.h" +#include #endif @@ -71,29 +77,21 @@ using namespace std; #include -#include -#include -#include +#include +#include +#include #include "SymReader.h" #include -using namespace boost::assign; +using namespace dyncompat::assign; // add some space to avoid looking for functions in data regions #define EXTRA_SPACE 8 bool Object::truncateLineFilenames = false; -string symt_current_func_name; -string symt_current_mangled_func_name; -Symbol *symt_current_func = NULL; - std::vector opdsymbols_; -extern void print_symbols(std::vector &allsymbols); - -extern void print_symbol_map(dyn_hash_map > *symbols); - void (*dwarf_err_func)(const char *); // error callback for dwarf errors static bool pdelf_check_ehdr(Elf_X &elf) { @@ -109,6 +107,26 @@ static bool pdelf_check_ehdr(Elf_X &elf) { ); } +template +static void decodeRelrEntries(const RelrT *entries, size_t count, + std::vector &relocs) { + Offset next = 0; + for (size_t i = 0; i < count; ++i) { + RelrT entry = entries[i]; + if ((entry & 1) == 0) { + relocs.push_back(static_cast(entry)); + next = static_cast(entry + sizeof(RelrT)); + } else { + entry >>= 1; + for (size_t bit = 0; entry != 0; ++bit, entry >>= 1) { + if (entry & 1) + relocs.push_back(next + bit * sizeof(RelrT)); + } + next += (sizeof(RelrT) * 8 - 1) * sizeof(RelrT); + } + } +} + const char *pdelf_get_shnames(Elf_X *elf) { const char *result = NULL; size_t shstrndx = elf->e_shstrndx(); @@ -128,7 +146,7 @@ const char *pdelf_get_shnames(Elf_X *elf) { // // Compare function for use with the Vector sort method. // -struct SectionHeaderSortFunction : public binary_function { +struct SectionHeaderSortFunction { bool operator()(Elf_X_Shdr *hdr1, Elf_X_Shdr *hdr2) { return (hdr1->sh_addr() < hdr2->sh_addr()); } @@ -226,6 +244,20 @@ Region::perm_t getRegionPerms(unsigned long flags) { return Region::RP_R; } +// Older elf.h headers may not define RELR section/dynamic tag constants +#if !defined(SHT_RELR) +#define SHT_RELR 19 +#endif +#if !defined(DT_RELRSZ) +#define DT_RELRSZ 35 +#endif +#if !defined(DT_RELR) +#define DT_RELR 36 +#endif +#if !defined(DT_RELRENT) +#define DT_RELRENT 37 +#endif + Region::RegionType getRegionType(unsigned long type, unsigned long flags, const char *reg_name) { switch (type) { case SHT_DYNSYM: @@ -238,6 +270,8 @@ Region::RegionType getRegionType(unsigned long type, unsigned long flags, const return Region::RT_REL; case SHT_RELA: return Region::RT_RELA; + case SHT_RELR: + return Region::RT_RELR; case SHT_NOBITS: //Darn it, Linux/PPC has the PLT as a NOBITS. Can't just default // call this bss @@ -279,6 +313,7 @@ static Region::RegionType getRelTypeByElfMachine(Elf_X *localHdr) { case EM_X86_64: case EM_IA_64: case EM_AARCH64: + case EM_AMDGPU: ret = Region::RT_RELA; break; default: @@ -297,10 +332,6 @@ const char *BSS_NAME = ".bss"; const char *SYMTAB_NAME = ".symtab"; const char *STRTAB_NAME = ".strtab"; const char *SYMTAB_SHNDX_NAME = ".symtab_shndx"; -const char *STAB_NAME = ".stab"; -const char *STABSTR_NAME = ".stabstr"; -const char *STAB_INDX_NAME = ".stab.index"; -const char *STABSTR_INDX_NAME = ".stab.indexstr"; const char *COMMENT_NAME = ".comment"; const char *OPD_NAME = ".opd"; // PPC64 Official Procedure Descriptors // sections from dynamic executables and shared objects @@ -336,8 +367,6 @@ set debugInfoSections = list_of(string(SYMTAB_NAME)) bool Object::loaded_elf(Offset &txtaddr, Offset &dataddr, Elf_X_Shdr *&bssscnp, Elf_X_Shdr *&symscnp, Elf_X_Shdr *&strscnp, - Elf_X_Shdr *&stabscnp, Elf_X_Shdr *&stabstrscnp, - Elf_X_Shdr *&stabs_indxcnp, Elf_X_Shdr *&stabstrs_indxcnp, Elf_X_Shdr *&rel_plt_scnp, Elf_X_Shdr *&plt_scnp, Elf_X_Shdr *&got_scnp, Elf_X_Shdr *&dynsym_scnp, Elf_X_Shdr *&dynstr_scnp, Elf_X_Shdr *&dynamic_scnp, @@ -393,24 +422,16 @@ bool Object::loaded_elf(Offset &txtaddr, Offset &dataddr, plt_size_ = 0; symtab_addr_ = 0; strtab_addr_ = 0; -#if defined (ppc32_linux) - plt_entry_size_ = 8; - rel_plt_entry_size_ = 8; -#else plt_entry_size_ = 0; rel_plt_entry_size_ = 0; -#endif rel_plt_addr_ = 0; rel_plt_size_ = 0; rel_addr_ = 0; rel_size_ = 0; rel_entry_size_ = 0; - stab_off_ = 0; - stab_size_ = 0; - stabstr_off_ = 0; - stab_indx_off_ = 0; - stab_indx_size_ = 0; - stabstr_indx_off_ = 0; + relr_addr_ = 0; + relr_size_ = 0; + relr_entry_size_ = 0; dwarvenDebugInfo = false; txtaddr = 0; @@ -490,6 +511,10 @@ bool Object::loaded_elf(Offset &txtaddr, Offset &dataddr, hasReladyn_ = true; secAddrTagMapping[dynsecData.d_ptr(j)] = dynsecData.d_tag(j); break; + case DT_RELR: + hasRelrdyn_ = true; + secAddrTagMapping[dynsecData.d_ptr(j)] = dynsecData.d_tag(j); + break; case DT_JMPREL: secAddrTagMapping[dynsecData.d_ptr(j)] = dynsecData.d_tag(j); break; @@ -517,6 +542,9 @@ bool Object::loaded_elf(Offset &txtaddr, Offset &dataddr, case DT_RELASZ: secTagSizeMapping[DT_RELA] = dynsecData.d_val(j); break; + case DT_RELRSZ: + secTagSizeMapping[DT_RELR] = dynsecData.d_val(j); + break; case DT_PLTRELSZ: secTagSizeMapping[DT_JMPREL] = dynsecData.d_val(j); break; @@ -545,6 +573,7 @@ bool Object::loaded_elf(Offset &txtaddr, Offset &dataddr, // Only sections with these tags are moved in the new rewritten binary case DT_REL: case DT_RELA: + case DT_RELR: case DT_JMPREL: case DT_SYMTAB: case DT_STRTAB: @@ -750,22 +779,7 @@ bool Object::loaded_elf(Offset &txtaddr, Offset &dataddr, strscnp = scnp; strtab_addr_ = scn.sh_addr(); } - } else if (strcmp(name, STAB_INDX_NAME) == 0) { - stabs_indxcnp = scnp; - stab_indx_off_ = scn.sh_offset(); - stab_indx_size_ = scn.sh_size(); - } else if (strcmp(name, STABSTR_INDX_NAME) == 0) { - stabstrs_indxcnp = scnp; - stabstr_indx_off_ = scn.sh_offset(); - } else if (strcmp(name, STAB_NAME) == 0) { - stabscnp = scnp; - stab_off_ = scn.sh_offset(); - stab_size_ = scn.sh_size(); - } else if (strcmp(name, STABSTR_NAME) == 0) { - stabstrscnp = scnp; - stabstr_off_ = scn.sh_offset(); - } - else if ((secAddrTagMapping.find(scn.sh_addr()) != secAddrTagMapping.end()) && + } else if ((secAddrTagMapping.find(scn.sh_addr()) != secAddrTagMapping.end()) && secAddrTagMapping[scn.sh_addr()] == DT_JMPREL) { rel_plt_scnp = scnp; rel_plt_addr_ = scn.sh_addr(); @@ -946,6 +960,7 @@ void Object::parseDynamic(Elf_X_Shdr *&dyn_scnp, Elf_X_Shdr *&dynsym_scnp, Elf_X_Data data = dyn_scnp->get_data(); Elf_X_Dyn dyns = data.get_dyn(); int rel_scnp_index = -1; + int relr_scnp_index = -1; for (unsigned i = 0; i < dyns.count(); ++i) { switch (dyns.d_tag(i)) { @@ -955,6 +970,10 @@ void Object::parseDynamic(Elf_X_Shdr *&dyn_scnp, Elf_X_Shdr *&dynsym_scnp, rel_addr_ = (Offset) dyns.d_ptr(i); rel_scnp_index = getRegionHdrIndexByAddr(dyns.d_ptr(i)); break; + case DT_RELR: + relr_addr_ = (Offset) dyns.d_ptr(i); + relr_scnp_index = getRegionHdrIndexByAddr(dyns.d_ptr(i)); + break; case DT_JMPREL: rel_plt_addr_ = (Offset) dyns.d_ptr(i); break; @@ -971,6 +990,12 @@ void Object::parseDynamic(Elf_X_Shdr *&dyn_scnp, Elf_X_Shdr *&dynsym_scnp, /* Maybe */ //rel_plt_entry_size_ = dyns.d_val(i); break; + case DT_RELRSZ: + relr_size_ = dyns.d_val(i); + break; + case DT_RELRENT: + relr_entry_size_ = dyns.d_val(i); + break; case DT_INIT: init_addr_ = dyns.d_val(i); break; @@ -983,8 +1008,52 @@ void Object::parseDynamic(Elf_X_Shdr *&dyn_scnp, Elf_X_Shdr *&dynsym_scnp, } if (rel_scnp_index != -1) get_relocationDyn_entries(rel_scnp_index, dynsym_scnp, dynstr_scnp); + if (relr_scnp_index != -1) + get_relocationRelr_entries(relr_scnp_index); } +/* parse relative relocations for the section represented by DT_RELR in + * the dynamic section. This section is encoded as RELR entries, which + * decode to relocation addresses + */ +bool Object::get_relocationRelr_entries(unsigned relr_scnp_index) { + Elf_X_Shdr *relr_scnp = getRegionHdrByIndex(relr_scnp_index); + if (!relr_scnp) return false; + + Elf_X_Data relrdata = relr_scnp->get_data(); + if (!relrdata.isValid()) return false; + + unsigned char *ident = elfHdr ? elfHdr->e_ident() : NULL; + if (!ident) return false; + + size_t entry_size = 0; + if (ident[EI_CLASS] == ELFCLASS32) + entry_size = sizeof(uint32_t); + else if (ident[EI_CLASS] == ELFCLASS64) + entry_size = sizeof(uint64_t); + else + return false; + + // DT_RELRENT must match the Elf{32,64}_Relr entry size, and DT_RELRSZ + // must describe the byte size of the encoded RELR table + if (relr_entry_size_ != entry_size) return false; + if (relr_size_ != relrdata.d_size()) return false; + if (relr_size_ % entry_size != 0) return false; + + size_t entry_count = relr_size_ / entry_size; + if (entry_size == sizeof(uint32_t)) { + decodeRelrEntries(reinterpret_cast(relrdata.d_buf()), + entry_count, + relr_relocation_table_); + } else { + decodeRelrEntries(reinterpret_cast(relrdata.d_buf()), + entry_count, + relr_relocation_table_); + } + + return true; + } + /* parse relocations for the sections represented by DT_REL/DT_RELA in * the dynamic section. This section is the one we would want to emit */ @@ -1125,7 +1194,7 @@ bool Object::get_relocation_entries(Elf_X_Shdr *&rel_plt_scnp, if (got != NULL) { unsigned char *data = (unsigned char *) got->getPtrToRawData(); - glink_addr = *(unsigned int *) + glink_addr = Dyninst::read_memory_as (data + (g_o_t - got->getMemOffset() + 4)); break; } @@ -1136,7 +1205,7 @@ bool Object::get_relocation_entries(Elf_X_Shdr *&rel_plt_scnp, // Otherwise, first entry in .plt section holds the glink address if (glink_addr == 0) { unsigned char *data = (unsigned char *) plt->getPtrToRawData(); - glink_addr = *(unsigned int *) (data); + glink_addr = Dyninst::read_memory_as(data); } // Search for region that contains glink address @@ -1163,7 +1232,7 @@ bool Object::get_relocation_entries(Elf_X_Shdr *&rel_plt_scnp, const unsigned int BCTR = 0x4e800420; unsigned char *sec_data = (unsigned char *) glink->getPtrToRawData(); - unsigned int *insn = (unsigned int *) + auto insn = alignas_cast (sec_data + (stub_addr - glink->getMemOffset())); // Keep moving pointer back if more -fPIC stubs are found. @@ -1483,10 +1552,6 @@ void Object::load_object(bool alloc_syms) { Elf_X_Shdr *bssscnp = 0; Elf_X_Shdr *symscnp = 0; Elf_X_Shdr *strscnp = 0; - Elf_X_Shdr *stabscnp = 0; - Elf_X_Shdr *stabstrscnp = 0; - Elf_X_Shdr *stabs_indxcnp = 0; - Elf_X_Shdr *stabstrs_indxcnp = 0; Offset txtaddr = 0; Offset dataddr = 0; Elf_X_Shdr *rel_plt_scnp = 0; @@ -1513,7 +1578,6 @@ void Object::load_object(bool alloc_syms) { // EEL, added one more parameter if (!loaded_elf(txtaddr, dataddr, bssscnp, symscnp, strscnp, - stabscnp, stabstrscnp, stabs_indxcnp, stabstrs_indxcnp, rel_plt_scnp, plt_scnp, got_scnp, dynsym_scnp, dynstr_scnp, dynamic_scnp, eh_frame_scnp, gcc_except, interp_scnp, opd_scnp, symtab_shndx_scnp, true)) { @@ -1525,12 +1589,6 @@ void Object::load_object(bool alloc_syms) { // find code and data segments.... find_code_and_data(*elfHdr, txtaddr, dataddr); - if (elfHdr->e_type() != ET_REL) { - if (!code_ptr_ || !code_len_) { - //bpfatal( "no text segment\n"); - goto cleanup; - } - } get_valid_memory_areas(*elfHdr); #if (defined(os_linux) || defined(os_freebsd)) @@ -1547,8 +1605,7 @@ void Object::load_object(bool alloc_syms) { interpreter_name_ = (char *) interp_scnp->get_data().d_buf(); } - // global symbols are put in global_symbols. Later we read the - // stab section to find the module to where they belong. + // global symbols are put in global_symbols. // Experiment : lets try to be a bit more intelligent about // how we initially size the global_symbols table. // dictionary_lite takes an initial # of bins (2nd param), @@ -1562,32 +1619,24 @@ void Object::load_object(bool alloc_syms) { #endif if (alloc_syms) { // find symbol and string data - string module = "DEFAULT_MODULE"; - string name = "DEFAULT_NAME"; Elf_X_Data symdata, strdata; if (symscnp && strscnp) { symdata = symscnp->get_data(); strdata = strscnp->get_data(); - parse_symbols(symdata, strdata, bssscnp, symscnp, symtab_shndx_scnp, false, module); + parse_symbols(symdata, strdata, bssscnp, symscnp, symtab_shndx_scnp, false); } no_of_symbols_ = nsymbols(); // try to resolve the module names of global symbols - // Sun compiler stab.index section - fix_global_symbol_modules_static_stab(stabs_indxcnp, stabstrs_indxcnp); - - // STABS format (.stab section) - fix_global_symbol_modules_static_stab(stabscnp, stabstrscnp); - // DWARF format (.debug_info section) fix_global_symbol_modules_static_dwarf(); if (dynamic_addr_ && dynsym_scnp && dynstr_scnp) { symdata = dynsym_scnp->get_data(); strdata = dynstr_scnp->get_data(); - parse_dynamicSymbols(dynamic_scnp, symdata, strdata, false, module); + parse_dynamicSymbols(dynamic_scnp, symdata, strdata, false); } @@ -1871,7 +1920,7 @@ bool Object::parse_symbols(Elf_X_Data &symdata, Elf_X_Data &strdata, Elf_X_Shdr *bssscnp, Elf_X_Shdr *symscnp, Elf_X_Shdr *symtab_shndx_scnp, - bool /*shared*/, string smodule) { + bool /*shared*/) { #if defined(TIMED_PARSE) struct timeval starttime; gettimeofday(&starttime, NULL); @@ -1884,7 +1933,6 @@ bool Object::parse_symbols(Elf_X_Data &symdata, Elf_X_Data &strdata, Elf_X_Sym syms = symdata.get_sym(); const char *strs = strdata.get_string(); if (syms.isValid()) { - std::vector mods(syms.count()); std::vector newsyms(syms.count()); { #pragma omp for schedule(dynamic) @@ -1922,7 +1970,6 @@ bool Object::parse_symbols(Elf_X_Data &symdata, Elf_X_Data &strdata, soffset = soffset_dbg; if (soffset_dbg) { bool result; - #pragma omp critical result = convertDebugOffset(soffset_dbg, soffset); if (!result) { //Symbol does not match any section, can't convert @@ -1968,9 +2015,6 @@ bool Object::parse_symbols(Elf_X_Data &symdata, Elf_X_Data &strdata, soffset = sec->getDiskOffset(); } - if (stype == Symbol::ST_MODULE) { - mods[i] = sname; - } Symbol *newsym = new Symbol(sname, stype, slinkage, @@ -2004,16 +2048,7 @@ bool Object::parse_symbols(Elf_X_Data &symdata, Elf_X_Data &strdata, if(!symsByOffset_.insert(a2, {newsym->getOffset(), {newsym}})) a2->second.push_back(newsym); } - } // Implicit barrier keeps Master from changing things too early - #pragma omp master - for(unsigned i = 0; i < syms.count(); i++) { - if(mods[i].empty()) mods[i] = smodule; - else smodule = mods[i]; } - #pragma omp barrier // Ensure no threads start running til ready - #pragma omp for nowait // nowait to save a barrier - for(unsigned i = 0; i < syms.count(); i++) - symsToModules_.insert({newsyms[i], mods[i]}); } } // syms.isValid() #if defined(TIMED_PARSE) @@ -2035,8 +2070,7 @@ bool Object::parse_symbols(Elf_X_Data &symdata, Elf_X_Data &strdata, void Object::parse_dynamicSymbols(Elf_X_Shdr *& dyn_scnp, Elf_X_Data &symdata, Elf_X_Data &strdata, - bool /*shared*/, - std::string smodule) { + bool /*shared*/) { #if defined(TIMED_PARSE) struct timeval starttime; gettimeofday(&starttime, NULL); @@ -2140,10 +2174,6 @@ dyn_scnp, Elf_X_Data &symdata, int ind = int(i); int strindex = syms.st_name(i); - if (stype == Symbol::ST_MODULE) { - smodule = sname; - } - Symbol *newsym = new Symbol(sname, stype, slinkage, @@ -2197,7 +2227,6 @@ dyn_scnp, Elf_X_Data &symdata, if(!symsByOffset_.insert(a2, {newsym->getOffset(), {newsym}})) a2->second.push_back(newsym); } - symsToModules_.insert({newsym, smodule}); } } @@ -2212,30 +2241,6 @@ dyn_scnp, Elf_X_Data &symdata, #endif } -#if defined(cap_dwarf) - -string Object::find_symbol(string name) { - string name2; - - // pass #1: unmodified - name2 = name; - if (symbols_.contains(name2)) return name2; - - // pass #2: leading underscore (C) - name2 = "_" + name; - if (symbols_.contains(name2)) return name2; - - // pass #3: trailing underscore (Fortran) - name2 = name + "_"; - if (symbols_.contains(name2)) - return name2; - - return ""; -} - -#endif - - /******************************************************** * * For object files only.... @@ -2248,63 +2253,6 @@ string Object::find_symbol(string name) { #if defined(cap_dwarf) -void pd_dwarf_handler() { - const char *dwarf_msg = dwarf_errmsg(0); - - if (dwarf_msg == NULL) - return; - - string str = string("DWARF Error: ") + dwarf_msg; - dwarf_err_func(str.c_str()); - - //bperr( "DWARF error: %s\n", dwarf_msg); -} - -Dwarf_Sword declFileNo = 0; -char **declFileNoToName = NULL; - -bool Object::dwarf_parse_aranges(Dwarf *dbg, std::set &/*dies_seen*/) { - Dwarf_Aranges *ranges; - size_t num_ranges; - int status = dwarf_getaranges(dbg, &ranges, &num_ranges); - if (status != 0) return false; - dwarf_printf("dwarf_parse_aranges: Processing %zu DWARF ranges\n", num_ranges); - for (size_t i = 0; i < num_ranges; i++) { - Dwarf_Arange *range = dwarf_onearange(ranges, i); - if (!range) continue; - - Dwarf_Addr start; - Dwarf_Word len; - Dwarf_Off some_offset; - status = dwarf_getarangeinfo(range, &start, &len, &some_offset); - assert(status == 0); - if (len == 0) continue; - - Dwarf_Die cu_die, *cu_die_off_p; - cu_die_off_p = dwarf_addrdie(dbg, start, &cu_die); - assert(cu_die_off_p != NULL); - auto off_die = dwarf_dieoffset(&cu_die); - //if (dies_seen.find(off_die) != dies_seen.end()) continue; - - std::string modname; - if (!DwarfWalker::findDieName(cu_die, modname)) { - modname = associated_symtab->file(); // default module - } - - Offset actual_start, actual_end; - convertDebugOffset(start, actual_start); - convertDebugOffset(start + len, actual_end); - Module *m = associated_symtab->getOrCreateModule(modname, actual_start); - m->addRange(actual_start, actual_end); - m->addDebugInfo(cu_die); - cerr << "File in module " << modname << ", DIE CU " << hex << off_die << dec << endl; - DwarfWalker::buildSrcFiles(dbg, cu_die, m->getStrings()); - //dies_seen.insert(off_die); - } - dwarf_printf("end of dwarf_parse_aranges\n"); - return true; -} - bool Object::fix_global_symbol_modules_static_dwarf() { /* Initialize libdwarf. */ Dwarf **dbg_ptr = dwarf->type_dbg(); @@ -2312,10 +2260,6 @@ bool Object::fix_global_symbol_modules_static_dwarf() { dwarf_printf("At fix_global_symbol_modules_static_dwarf\n"); Dwarf *dbg = *dbg_ptr; - std::set dies_seen; - /*if (!dwarf_parse_aranges(dbg, dies_seen)) { - return false; - }*/ std::vector dies; size_t cu_header_size; @@ -2328,8 +2272,10 @@ bool Object::fix_global_symbol_modules_static_dwarf() { Dwarf_Die cu_die, *cu_die_p; cu_die_p = dwarf_offdie(dbg, cu_die_off, &cu_die); - Dwarf_Half moduleTag = dwarf_tag(&cu_die); - if (moduleTag != DW_TAG_compile_unit) { + // As of DWARF 5, only full and partial CUs contain debug info for symbols + bool const is_partialcu = DwarfDyninst::is_partial_unit(cu_die); + bool const is_fullcu = DwarfDyninst::is_full_unit(cu_die); + if (!(is_partialcu || is_fullcu)) { continue; } @@ -2344,36 +2290,24 @@ bool Object::fix_global_symbol_modules_static_dwarf() { for (size_t i = 0; i < dies.size(); i++) { Dwarf_Die cu_die = dies[i]; - std::string modname; - if (!DwarfWalker::findDieName(cu_die, modname)) { - modname = associated_symtab->file(); // default module - } - if(modname=="") - { - auto off_die = dwarf_dieoffset(&cu_die); - std::stringstream suffix; - suffix << std::hex << off_die; - modname = "" + suffix.str(); - } + std::string modname = DwarfDyninst::cu_name(cu_die); - //cerr << "Processing CU DIE for " << modname << " offset: " << next_cu_off << endl; - Address tempModLow; - Address modLow = 0; - if (DwarfWalker::findConstant(DW_AT_low_pc, tempModLow, &cu_die, dbg)) { - #pragma omp critical - convertDebugOffset(tempModLow, modLow); + auto const loc = dwarf_dieoffset(&cu_die); + + dwarf_printf("Locating ranges for module '%s' at offset 0x%zx\n", modname.c_str(), loc); + std::vector mod_ranges = DwarfWalker::getDieRanges(cu_die); + auto *m = associated_symtab->findModuleByOffset(loc); + if(!m) { + m = new SymtabAPI::Module(lang_Unknown, loc, modname, associated_symtab); } - std::vector mod_ranges = DwarfWalker::getDieRanges(dbg, cu_die, modLow); - Module *m; - #pragma omp critical - m = associated_symtab->getOrCreateModule(modname, modLow); + dwarf_printf("Adding %zu ranges to '%s'\n", mod_ranges.size(), m->fileName().c_str()); for (auto r = mod_ranges.begin(); r != mod_ranges.end(); ++r) { m->addRange(r->first, r->second); } if (!m->hasRanges()) { -// cout << "No ranges for module " << modname << ", need to extract from statements\n"; + dwarf_printf("No ranges found. Checking source lines\n"); Dwarf_Lines *lines; size_t num_lines; if (dwarf_getsrclines(&cu_die, &lines, &num_lines) == 0) @@ -2399,18 +2333,16 @@ bool Object::fix_global_symbol_modules_static_dwarf() { } } -// cout << "Adding range [" << hex << low << ", " << high << ") to " << dec << -// m->fileName() << " based on statements" << endl; m->addRange(low, high); } } } } - #pragma omp critical - m->addDebugInfo(cu_die); - //cerr << "Files in module " << modname << endl; DwarfWalker::buildSrcFiles(dbg, cu_die, m->getStrings()); // dies_seen.insert(cu_die_off); + + // 'addModule' finalizes the Module's ranges, so do not add until after they are computed + associated_symtab->addModule(m); } return true; @@ -2424,224 +2356,6 @@ bool Object::fix_global_symbol_modules_static_dwarf() #endif // cap_dwarf -/******************************************************** - * - * For object files only.... - * read the .stab section to find the module of global symbols - * - ********************************************************/ - -bool Object::fix_global_symbol_modules_static_stab(Elf_X_Shdr *stabscnp, Elf_X_Shdr *stabstrscnp) { - // Read the stab section to find the module of global symbols. - // The symbols appear in the stab section by module. A module begins - // with a symbol of type N_UNDF and ends with a symbol of type N_ENDM. - // All the symbols in between those two symbols belong to the module. - - if (!stabscnp || !stabstrscnp) return false; - - Elf_X_Data stabdata = stabscnp->get_data(); - Elf_X_Data stabstrdata = stabstrscnp->get_data(); - stab_entry *stabptr = NULL; - - if (!stabdata.isValid() || !stabstrdata.isValid()) return false; - - switch (addressWidth_nbytes) { - case 4: - stabptr = new stab_entry_32(stabdata.d_buf(), - stabstrdata.get_string(), - stabscnp->sh_size() / sizeof(stab32)); - break; - - case 8: - stabptr = new stab_entry_64(stabdata.d_buf(), - stabstrdata.get_string(), - stabscnp->sh_size() / sizeof(stab64)); - break; - }; - - const char *next_stabstr = stabptr->getStringBase(); - string module = "DEFAULT_MODULE"; - - // the stabstr contains one string table for each module. - // stabstr_offset gives the offset from the begining of stabstr of the - // string table for the current module. - - bool is_fortran = false; // is the current module fortran code? - - for (unsigned i = 0; i < stabptr->count(); i++) { - switch (stabptr->type(i)) { - case N_UNDF: /* start of object file */ - stabptr->setStringBase(next_stabstr); - next_stabstr = stabptr->getStringBase() + stabptr->val(i); - break; - - case N_ENDM: /* end of object file */ - is_fortran = false; - module = "DEFAULT_MODULE"; - break; - - case N_SO: /* compilation source or file name */ - if ((stabptr->desc(i) == N_SO_FORTRAN) || (stabptr->desc(i) == N_SO_F90)) - is_fortran = true; - - module = string(stabptr->name(i)); - break; - - case N_ENTRY: /* fortran alternate subroutine entry point */ - case N_GSYM: /* global symbol */ - // the name string of a function or object appears in the stab - // string table as : - // where is a one char code. - // we must extract the name and descriptor from the string - { - const char *p = stabptr->name(i); - // bperr("got %d type, str = %s\n", stabptr->type(i), p); - // if (stabptr->type(i) == N_FUN && strlen(p) == 0) { - - if (strlen(p) == 0) { - // GNU CC 2.8 and higher associate a null-named function - // entry with the end of a function. Just skip it. - break; - } - - const char *q = strchr(p, ':'); - unsigned len; - - if (q) { - len = q - p; - } else { - len = strlen(p); - } - - if (len == 0) { - // symbol name is empty.Skip it.- 02/12/07 -Giri - break; - } - - char *sname = new char[len + 1]; - strncpy(sname, p, len); - sname[len] = 0; - - string SymName = string(sname); - - // q points to the ':' in the name string, so - // q[1] is the symbol descriptor. We must check the symbol descriptor - // here to skip things we are not interested in, such as prototypes. - - bool res = symbols_.contains(SymName); - - if (!res && is_fortran) { - // Fortran symbols usually appear with an '_' appended in .symtab, - // but not on .stab - SymName += "_"; - res = symbols_.contains(SymName); - } - - if (res && (q == 0 || q[1] != SD_PROTOTYPE)) { - unsigned int count = 0; - dyn_c_hash_map>::const_accessor ca; - if (!symbols_.find(ca, SymName)) { - assert(!"symbols_.find(ca, SymName)"); - } - const std::vector &syms = ca->second; - - /* If there's only one, apply regardless. */ - if (syms.size() == 1) { - // TODO: set module - // symbols_[SymName][0]->setModuleName(module); - } else { - for (unsigned int j = 0; j < syms.size(); j++) { - if (syms[j]->getLinkage() == Symbol::SL_GLOBAL) { - // TODO: set module - // symbols_[SymName][j]->setModuleName(module); - count++; - } - } - } - } - break; - } - case N_FUN: - /* function */ - { - const char *p = stabptr->name(i); - - if (strlen(p) == 0) { - // Rumours are that GNU CC 2.8 and higher associate a - // null-named function entry with the end of a - // function. Just skip it. - break; - } - - const char *q = strchr(p, ':'); - - if (q == 0) { - // bperr( "Unrecognized stab format: %s\n", p); - // Happens with the Solaris native compiler (.xstabs entries?) - break; - } - - if (q[1] == SD_PROTOTYPE) { - // We see a prototype, skip it - break; - } - - unsigned long entryAddr = stabptr->val(i); - - if (entryAddr == 0) { - // The function stab doesn't contain a function address - // (happens with the Solaris native compiler). We have to - // look up the symbol by its name. That's unfortunate, since - // names may not be unique and we may end up assigning a wrong - // module name to the symbol. - unsigned len = q - p; - if (len == 0) { - // symbol name is empty.Skip it.- 02/12/07 -Giri - break; - } - - char *sname = new char[len + 1]; - strncpy(sname, p, len); - sname[len] = 0; - string nameFromStab = string(sname); - delete[] sname; - - dyn_c_hash_map>::const_accessor ca; - if (!symbols_.find(ca, nameFromStab)) { - assert(!"symbols_.find(ca, nameFromStab)"); - } - for (unsigned j = 0; j < ca->second.size(); j++) { - symsToModules_.insert({ca->second[j], module}); - } - } else { - if (!symsByOffset_.contains(entryAddr)) { - //bperr( "fix_global_symbol_modules_static_stab " - // "can't find address 0x%lx of STABS entry %s\n", entryAddr, p); - break; - } - dyn_c_hash_map>::const_accessor ca; - if (!symsByOffset_.find(ca, entryAddr)) { - assert(!"symsByOffset_.find(ca, entryAddr)"); - } - for (unsigned j = 0; j < ca->second.size(); j++) { - symsToModules_.insert({ca->second[j], module}); - } - } - break; - } - - default: - /* ignore other entries */ - break; - } - } - - delete stabptr; - - return true; -} - - // find_code_and_data(): populates the following members: // code_ptr_, code_off_, code_len_ // data_ptr_, data_off_, data_len_ @@ -2672,9 +2386,9 @@ void Object::find_code_and_data(Elf_X &elf, // txtaddr=0, so in this case we set these values by // identifying the segment that contains the entryAddress if (((phdr.p_vaddr() <= txtaddr) && - (phdr.p_vaddr() + phdr.p_filesz() >= txtaddr)) || + (phdr.p_vaddr() + phdr.p_filesz() > txtaddr)) || (!txtaddr && ((phdr.p_vaddr() <= entryAddress_) && - (phdr.p_vaddr() + phdr.p_filesz() >= entryAddress_)))) { + (phdr.p_vaddr() + phdr.p_filesz() > entryAddress_)))) { if (code_ptr_ == 0 && code_off_ == 0 && code_len_ == 0) { code_ptr_ = (char *) (void *) &file_ptr[phdr.p_offset()]; @@ -2683,7 +2397,7 @@ void Object::find_code_and_data(Elf_X &elf, } } else if (((phdr.p_vaddr() <= dataddr) && - (phdr.p_vaddr() + phdr.p_filesz() >= dataddr)) || + (phdr.p_vaddr() + phdr.p_filesz() > dataddr)) || (!dataddr && (phdr.p_type() == PT_LOAD))) { if (data_ptr_ == 0 && data_off_ == 0 && data_len_ == 0) { data_ptr_ = (char *) (void *) &file_ptr[phdr.p_offset()]; @@ -2695,48 +2409,13 @@ void Object::find_code_and_data(Elf_X &elf, //if (addressWidth_nbytes == 8) bperr( ">>> 64-bit find_code_and_data() successful\n"); } -const char *Object::elf_vaddr_to_ptr(Offset vaddr) const { - const char *ret = NULL; - unsigned code_size_ = code_len_; - unsigned data_size_ = data_len_; - - if (vaddr >= code_off_ && vaddr < code_off_ + code_size_) { - ret = ((char *) code_ptr_) + (vaddr - code_off_); - } else if (vaddr >= data_off_ && vaddr < data_off_ + data_size_) { - ret = ((char *) data_ptr_) + (vaddr - data_off_); - } - - return ret; -} - -stab_entry *Object::get_stab_info() const { - char *file_ptr = (char *) mf->base_addr(); - - // check that file has .stab info - if (stab_off_ && stab_size_ && stabstr_off_) { - switch (addressWidth_nbytes) { - case 4: // 32-bit object - return new stab_entry_32(file_ptr + stab_off_, - file_ptr + stabstr_off_, - stab_size_ / sizeof(stab32)); - break; - case 8: // 64-bit object - return new stab_entry_64(file_ptr + stab_off_, - file_ptr + stabstr_off_, - stab_size_ / sizeof(stab64)); - break; - }; - } - - return new stab_entry_64(); -} - Object::Object(MappedFile *mf_, bool, void (*err_func)(const char *), bool alloc_syms, Symtab *st) : AObject(mf_, err_func, st), elfHdr(NULL), hasReldyn_(false), hasReladyn_(false), + hasRelrdyn_(false), hasRelplt_(false), hasRelaplt_(false), relType_(Region::RT_REL), @@ -2751,9 +2430,8 @@ Object::Object(MappedFile *mf_, bool, void (*err_func)(const char *), plt_addr_(0), plt_size_(0), plt_entry_size_(0), rel_plt_addr_(0), rel_plt_size_(0), rel_plt_entry_size_(0), rel_addr_(0), rel_size_(0), rel_entry_size_(0), + relr_addr_(0), relr_size_(0), relr_entry_size_(0), opd_addr_(0), opd_size_(0), - stab_off_(0), stab_size_(0), stabstr_off_(0), - stab_indx_off_(0), stab_indx_size_(0), stabstr_indx_off_(0), dwarvenDebugInfo(false), loadAddress_(0), entryAddress_(0), interpreter_name_(NULL), @@ -2769,7 +2447,8 @@ Object::Object(MappedFile *mf_, bool, void (*err_func)(const char *), EEL(false), did_open(false), obj_type_(obj_Unknown), DbgSectionMapSorted(false), - soname_(NULL) + soname_(NULL), + containingFunc(nullptr) { li_for_object = NULL; @@ -2779,9 +2458,9 @@ Object::Object(MappedFile *mf_, bool, void (*err_func)(const char *), #endif if (mf->base_addr() == NULL) { - elfHdr = Elf_X::newElf_X(mf->getFD(), ELF_C_READ, NULL, mf_->pathname()); + elfHdr = Elf_X::newElf_X(mf->getFD(), ELF_C_READ, NULL, mf_->filename()); } else { - elfHdr = Elf_X::newElf_X((char *) mf->base_addr(), mf->size(), mf_->pathname()); + elfHdr = Elf_X::newElf_X((char *) mf->base_addr(), mf->size(), mf_->filename()); } // ELF header: sanity check @@ -2796,10 +2475,9 @@ Object::Object(MappedFile *mf_, bool, void (*err_func)(const char *), return; } - dwarf = DwarfHandle::createDwarfHandle(mf_->pathname(), elfHdr); + dwarf = DwarfHandle::createDwarfHandle(mf_->filename(), elfHdr); if (elfHdr->e_type() == ET_DYN) { -// load_shared_object(alloc_syms); load_object(alloc_syms); } else if (elfHdr->e_type() == ET_REL || elfHdr->e_type() == ET_EXEC) { load_object(alloc_syms); @@ -2814,9 +2492,6 @@ Object::Object(MappedFile *mf_, bool, void (*err_func)(const char *), // executables are treated as shared libraries. is_aout_ = isOnlyExecutable(); -#ifdef BINEDIT_DEBUG - print_symbol_map(&symbols_); -#endif #if defined(TIMED_PARSE) struct timeval endtime; gettimeofday(&endtime, NULL); @@ -2891,9 +2566,9 @@ const ostream &Object::dump_state_info(ostream &s) s << " rel_plt_entry_size_ = " << rel_plt_entry_size_ << endl; s << " rel_size_ = " << rel_size_ << endl; s << " rel_entry_size_ = " << rel_entry_size_ << endl; - s << " stab_off_ = " << stab_off_ << endl; - s << " stab_size_ = " << stab_size_ << endl; - s << " stabstr_off_ = " << stabstr_off_ << endl; + s << " relr_addr_ = " << relr_addr_ << endl; + s << " relr_size_ = " << relr_size_ << endl; + s << " relr_entry_size_ = " << relr_entry_size_ << endl; s << " dwarvenDebugInfo = " << dwarvenDebugInfo << endl; // and dump the relocation table.... @@ -3065,10 +2740,10 @@ static int read_val_of_type(int type, unsigned long *value, const unsigned char switch (type & 0x0f) { case DW_EH_PE_absptr: if (mi.word_size == 4) { - *value = (unsigned long) endian_32bit(*((const uint32_t *) addr), mi.big_input); + *value = (unsigned long) endian_32bit(Dyninst::read_memory_as(addr), mi.big_input); size = 4; } else if (mi.word_size == 8) { - *value = (unsigned long) endian_64bit(*((const uint64_t *) addr), mi.big_input); + *value = (unsigned long) endian_64bit(Dyninst::read_memory_as(addr), mi.big_input); size = 8; } break; @@ -3079,27 +2754,27 @@ static int read_val_of_type(int type, unsigned long *value, const unsigned char *value = read_sleb128(addr, &size); break; case DW_EH_PE_udata2: - *value = endian_16bit(*((const uint16_t *) addr), mi.big_input); + *value = endian_16bit(Dyninst::read_memory_as(addr), mi.big_input); size = 2; break; case DW_EH_PE_sdata2: - *value = endian_16bit(*((const uint16_t *) addr), mi.big_input); + *value = endian_16bit(Dyninst::read_memory_as(addr), mi.big_input); size = 2; break; case DW_EH_PE_udata4: - *value = endian_32bit(*((const uint32_t *) addr), mi.big_input); + *value = endian_32bit(Dyninst::read_memory_as(addr), mi.big_input); size = 4; break; case DW_EH_PE_sdata4: - *value = endian_32bit(*((const uint32_t *) addr), mi.big_input); + *value = endian_32bit(Dyninst::read_memory_as(addr), mi.big_input); size = 4; break; case DW_EH_PE_udata8: - *value = endian_64bit(*((const uint64_t *) addr), mi.big_input); + *value = endian_64bit(Dyninst::read_memory_as(addr), mi.big_input); size = 8; break; case DW_EH_PE_sdata8: - *value = endian_64bit(*((const uint64_t *) addr), mi.big_input); + *value = endian_64bit(Dyninst::read_memory_as(addr), mi.big_input); size = 8; break; default: @@ -3284,7 +2959,7 @@ int read_except_table_gcc3( // Calculate size in bytes of PC Begin const unsigned char* pc_begin_start = fde_bytes + 4 /* CIE Pointer size is 4 bytes */ + - (*(uint32_t*)fde_bytes == 0xffffffff ? LONG_FDE_HLEN : SHORT_FDE_HLEN); + (Dyninst::read_memory_as(fde_bytes) == 0xffffffff ? LONG_FDE_HLEN : SHORT_FDE_HLEN); unsigned long pc_begin_val; mi.pc = fde_addr + (unsigned long) (pc_begin_start - fde_bytes); int pc_begin_size = read_val_of_type(range_encoding, &pc_begin_val, pc_begin_start, mi); @@ -3311,7 +2986,7 @@ int read_except_table_gcc3( // Get the augmentation data for the FDE cur_augdata = fde_bytes + 4 /* CIE Pointer size is 4 bytes */ + - (*(uint32_t*)fde_bytes == 0xffffffff ? LONG_FDE_HLEN : SHORT_FDE_HLEN) + + (Dyninst::read_memory_as(fde_bytes) == 0xffffffff ? LONG_FDE_HLEN : SHORT_FDE_HLEN) + pc_begin_size + pc_range_size + aug_length_size; for (j=0; j { +struct exception_compare { bool operator()(const ExceptionBlock &e1, const ExceptionBlock &e2) const { if (e1.tryStart() < e2.tryStart()) return true; @@ -3484,169 +3159,14 @@ ObjectType Object::objType() const { return obj_type_; } +void Object::addModule(SymtabAPI::Module* m) { + associated_symtab->addModule(m); +} + void Object::getModuleLanguageInfo(dyn_hash_map *mod_langs) { string working_module; - const char *ptr; - // check .stabs section to get language info for modules: - // int stab_nsyms; - // char *stabstr_nextoffset; - // const char *stabstrs = 0; - string mod_string; - // This ugly flag is set when certain (sun) fortran compilers are detected. - // If it is set at any point during the following iteration, this routine - // ends with "backtrack mode" and reiterates through all chosen languages, changing - // lang_Fortran to lang_Fortran_with_pretty_debug. - // - // This may be ugly, but it is set up this way since the information that is used - // to determine whether this flag is set comes from the N_OPT field, which - // seems to come only once per image. The kludge is that we assume that all - // fortran sources in the module have this property (they probably do, but - // could conceivably be mixed (???)). - int fortran_kludge_flag = 0; - - // "state variables" we use to accumulate potentially useful information - // A final module<->language decision is not made until we have arrived at the - // next module entry, at which point we use any and all info we have to - // make the most sensible guess - supportedLanguages working_lang = lang_Unknown; - char *working_options = NULL; - const char *working_name = NULL; - - stab_entry *stabptr = NULL; - const char *next_stabstr = NULL; -#if defined(TIMED_PARSE) - struct timeval starttime; - gettimeofday(&starttime, NULL); -#endif - - //Using the Object to get the pointers to the .stab and .stabstr - // XXX - Elf32 specific needs to be in seperate file -- jkh 3/18/99 - stabptr = get_stab_info(); - next_stabstr = stabptr->getStringBase(); - - for (unsigned int i = 0; i < stabptr->count(); i++) { - if (stabptr->type(i) == N_UNDF) {/* start of object file */ - /* value contains offset of the next string table for next module */ - // assert(stabptr->nameIdx(i) == 1); - stabptr->setStringBase(next_stabstr); - next_stabstr = stabptr->getStringBase() + stabptr->val(i); - } else if (stabptr->type(i) == N_OPT) { - // We can use the compiler option string (in a pinch) to guess at the source file language - // There is possibly more useful information encoded somewhere around here, but I lack - // an immediate reference.... - if (working_name) - working_options = const_cast(stabptr->name(i)); - } else if ((stabptr->type(i) == N_SO) || (stabptr->type(i) == N_ENDM)) { /* compilation source or file name */ - // We have arrived at the next source file, finish up with the last one and reset state - // before starting next - - - // XXXXXXXXXXX This block is mirrored near the end of routine, if you edit it, - // XXXXXXXXXXX change it there too. - if (working_name) { - working_lang = pickLanguage(working_module, working_options, working_lang); - if (working_lang == lang_Fortran_with_pretty_debug) - fortran_kludge_flag = 1; - (*mod_langs)[working_module] = working_lang; - - } - // XXXXXXXXXXX - - // reset "state" here - working_lang = lang_Unknown; - working_options = NULL; - - // Now: out with the old, in with the new - - if (stabptr->type(i) == N_ENDM) { - // special case: - // which is most likely both broken (and ignorable ???) - working_name = "DEFAULT_MODULE"; - } else { - working_name = stabptr->name(i); - ptr = strrchr(working_name, '/'); - if (ptr) { - ptr++; - working_name = ptr; - } - } - working_module = string(working_name); - - if ((mod_langs->find(working_module) != mod_langs->end()) && (*mod_langs)[working_module] != lang_Unknown) { - // we already have a module with this name in the map. If it has been given - // a language assignment (not lang_Unknown), we can just skip ahead - working_name = NULL; - working_options = NULL; - continue; - } else { - //cerr << __FILE__ << __LINE__ << ": Module: " <desc(i) << endl; - switch (stabptr->desc(i)) { - case N_SO_FORTRAN: - working_lang = lang_Fortran; - break; - case N_SO_F90: - working_lang = lang_Fortran; // not sure if this should be different from N_SO_FORTRAN - break; - case N_SO_AS: - working_lang = lang_Assembly; - break; - case N_SO_ANSI_C: - case N_SO_C: - working_lang = lang_C; - break; - case N_SO_CC: - working_lang = lang_CPlusPlus; - break; - default: - // currently uncovered options are lang_CMFortran, and lang_GnuCPlusPlus - // do we need to make this kind of distinction here? - working_lang = lang_Unknown; - break; - } - - } - } // end N_SO section - } // for loop - - // Need to make sure we finish up with the module we were last collecting information - // about - - // XXXXXXXXXXX see note above (find the X's) - if (working_name) { - working_lang = pickLanguage(working_module, working_options, working_lang); - if (working_lang == lang_Fortran_with_pretty_debug) - fortran_kludge_flag = 1; - (*mod_langs)[working_module] = working_lang; - } - // XXXXXXXXXXX - - if (fortran_kludge_flag) { - // XXX This code does not appear to be used anymore?? - // go through map and change all lang_Fortran to lang_Fortran_with_pretty_symtab - dyn_hash_map::iterator iter = (*mod_langs).begin(); - string aname; - supportedLanguages alang; - for (; iter != (*mod_langs).end(); iter++) { - aname = iter->first; - alang = iter->second; - if (lang_Fortran == alang) { - (*mod_langs)[aname] = lang_Fortran_with_pretty_debug; - } - } - } -#if defined(TIMED_PARSE) - struct timeval endtime; - gettimeofday(&endtime, NULL); - unsigned long lstarttime = starttime.tv_sec * 1000 * 1000 + starttime.tv_usec; - unsigned long lendtime = endtime.tv_sec * 1000 * 1000 + endtime.tv_usec; - unsigned long difftime = lendtime - lstarttime; - double dursecs = difftime/(1000 ); - cout << __FILE__ << ":" << __LINE__ <<": getModuleLanguageInfo took "<type_dbg(); @@ -3668,31 +3188,12 @@ void Object::getModuleLanguageInfo(dyn_hash_map *mod cu_die_p = dwarf_offdie(dbg, cu_die_off, &moduleDIE); if (cu_die_p == NULL) break; - Dwarf_Half moduleTag = dwarf_tag(&moduleDIE); - if (moduleTag != DW_TAG_compile_unit) { + if (!DwarfDyninst::is_full_unit(moduleDIE)) { continue; } /* Extract the name of this module. */ - auto moduleName = dwarf_diename(&moduleDIE); - if (!moduleName) { - break; - } - ptr = strrchr(moduleName, '/'); - if (ptr) - ptr++; - else - ptr = moduleName; - - working_module = string(ptr); - - if(working_module=="") - { - auto off_die = dwarf_dieoffset(&moduleDIE); - std::stringstream suffix; - suffix << std::hex << off_die; - working_module = "" + suffix.str(); - } + auto moduleName = DwarfDyninst::die_name(moduleDIE); auto attr_p = dwarf_attr(&moduleDIE, DW_AT_language, &languageAttribute); if (attr_p == NULL) { @@ -3709,24 +3210,21 @@ void Object::getModuleLanguageInfo(dyn_hash_map *mod case DW_LANG_C: case DW_LANG_C89: case DW_LANG_C99: -#ifdef DW_LANG_C11 case DW_LANG_C11: -#endif - (*mod_langs)[working_module] = lang_C; + (*mod_langs)[moduleName] = lang_C; break; case DW_LANG_C_plus_plus: -#ifdef DW_LANG_C_plus_plus_03 case DW_LANG_C_plus_plus_03: -#endif -#ifdef DW_LANG_C_plus_plus_11 case DW_LANG_C_plus_plus_11: -#endif - (*mod_langs)[working_module] = lang_CPlusPlus; + case DW_LANG_C_plus_plus_14: + (*mod_langs)[moduleName] = lang_CPlusPlus; break; case DW_LANG_Fortran77: case DW_LANG_Fortran90: case DW_LANG_Fortran95: - (*mod_langs)[working_module] = lang_Fortran; + case DW_LANG_Fortran03: + case DW_LANG_Fortran08: + (*mod_langs)[moduleName] = lang_Fortran; break; default: /* We know what the language is but don't care. */ @@ -3744,7 +3242,7 @@ bool AObject::getSegments(vector &segs) const { (regions_[i]->getRegionName() == ".fini") || (regions_[i]->getRegionName() == ".rodata") || (regions_[i]->getRegionName() == ".plt") || (regions_[i]->getRegionName() == ".data")) { - Segment seg; + Segment seg{}; seg.data = regions_[i]->getPtrToRawData(); seg.loadaddr = regions_[i]->getDiskOffset(); seg.size = regions_[i]->getDiskSize(); @@ -3758,12 +3256,6 @@ bool AObject::getSegments(vector &segs) const { bool Object::emitDriver(string fName, std::set &allSymbols, unsigned) { -#ifdef BINEDIT_DEBUG - printf("emitting...\n"); - //print_symbol_map(&symbols_); - print_symbols(allSymbols); - printf("%d total symbol(s)\n", allSymbols.size()); -#endif if (elfHdr->e_ident()[EI_CLASS] == ELFCLASS32) { Dyninst::SymtabAPI::emitElf *em = new Dyninst::SymtabAPI::emitElf(elfHdr, isStripped, this, err_func_, @@ -3792,234 +3284,14 @@ const char *Object::interpreter_name() const { return interpreter_name_; } -/* Parse everything in the file on disk, and cache that we've done so, - because our modules may not bear any relation to the name source files. */ -void Object::parseStabFileLineInfo() { - static dyn_hash_map haveParsedFileMap; - - /* We haven't parsed this file already, so iterate over its stab entries. */ - - stab_entry *stabEntry = get_stab_info(); - if (stabEntry == NULL) return; - const char *nextStabString = stabEntry->getStringBase(); - - const char *currentSourceFile = NULL; - const char *moduleName = NULL; - Function *currentFunction = NULL; - Offset currentAddress = 0; - unsigned currentLineBase = 0; - unsigned functionLineToPossiblyAdd = 0; - - //Offset baseAddress = getBaseAddress(); - LineInformation *li_for_module = NULL; - - for (unsigned int i = 0; i < stabEntry->count(); i++) { - switch (stabEntry->type(i)) { - case N_UNDF: /* start of an object file */ - { - stabEntry->setStringBase(nextStabString); - nextStabString = stabEntry->getStringBase() + stabEntry->val(i); - - currentSourceFile = NULL; - } - break; - - case N_SO: /* compilation source or file name */ - { - const char *sourceFile = stabEntry->name(i); - currentSourceFile = strrchr(sourceFile, '/'); - - if (currentSourceFile == NULL) { - currentSourceFile = sourceFile; - } else { - ++currentSourceFile; - } - Module *mod; - - moduleName = currentSourceFile; - if (!associated_symtab->findModuleByName(mod, moduleName)) { - mod = associated_symtab->getDefaultModule(); - } - li_for_module = mod->getLineInformation(); - if (!li_for_module) { - li_for_module = new LineInformation; - mod->setLineInfo(li_for_module); - } - - } - break; - - case N_SOL: /* file name (possibly an include file) */ - { - const char *sourceFile = stabEntry->name(i); - currentSourceFile = strrchr(sourceFile, '/'); - if (currentSourceFile == NULL) { - currentSourceFile = sourceFile; - } else { - ++currentSourceFile; - } - - } - break; - - case N_FUN: /* a function */ - { - if (*stabEntry->name(i) == 0) { - currentFunction = NULL; - currentLineBase = 0; - break; - } /* end if the N_FUN is an end-of-function-marker. */ - - std::vector funcs; - char stringbuf[2048]; - const char *stabstr = stabEntry->name(i); - unsigned iter = 0; - - while (iter < 2048) { - char c = stabstr[iter]; - - if ((c == ':') || (c == '\0')) { - //stabstrs use ':' as delimiter - stringbuf[iter] = '\0'; - break; - } - - stringbuf[iter] = c; - - iter++; - } - - if (iter >= 2047) { - create_printf("%s[%d]: something went horribly awry\n", FILE__, __LINE__); - continue; - } else { - switch (stabstr[iter + 1]) { - case 'F': - case 'f': - // A "good" function - break; - case 'P': - case 'p': - // A prototype function? need to discard - continue; - break; - default: - continue; - break; - }; - } - - if (!associated_symtab->findFunctionsByName(funcs, std::string(stringbuf)) - || !funcs.size()) { - continue; - } - - currentFunction = funcs[0]; - currentLineBase = stabEntry->desc(i); - functionLineToPossiblyAdd = currentLineBase; - - if (!currentFunction) continue; - currentAddress = currentFunction->getOffset(); - - } - break; - - case N_SLINE: { - unsigned current_col = 0; - - if (!currentLineBase) { - continue; - } - - unsigned newLineSpec = stabEntry->desc(i); - - // Addresses specified in SLINEs are relative to the beginning of the fn - Offset newLineAddress = stabEntry->val(i) + currentFunction->getOffset(); - - if (newLineAddress <= currentAddress) { - continue; - } - - // If we just got our first N_SLINE after a function definition - // its possible that the line number specified in the function - // definition was less than the line number that we are currently on - // If so, add an additional line number entry that encompasses - // the line number of the original function definition in addition - // to this SLINE ( use the same address range) - - if (functionLineToPossiblyAdd) { - if (functionLineToPossiblyAdd < newLineSpec) { - if (li_for_module) - li_for_module->addLine(currentSourceFile, - functionLineToPossiblyAdd, - current_col, currentAddress, - newLineAddress); - } - - functionLineToPossiblyAdd = 0; - } - - if (li_for_module) - li_for_module->addLine(currentSourceFile, newLineSpec, - current_col, currentAddress, - newLineAddress); - - currentAddress = newLineAddress; - currentLineBase = newLineSpec + 1; - - } - break; - - } /* end switch on the ith stab entry's type */ - - } /* end iteration over stab entries. */ - - // haveParsedFileMap[ key ] = true; -} /* end parseStabFileLineInfo() */ - -class open_statement { - public: - open_statement() { reset(); } - Dwarf_Addr noAddress() { return (Dwarf_Addr) ~0; } - bool uninitialized() { - return start_addr == noAddress(); - } - void reset() { - string_table_index = -1; - start_addr = noAddress(); - end_addr = noAddress(); - line_number = 0; - column_number = 0; - } - bool sameFileLineColumn(const open_statement &rhs) { - return ((string_table_index == rhs.string_table_index) && - (line_number == rhs.line_number) && - (column_number == rhs.column_number)); - } - void operator=(const open_statement &rhs) { - string_table_index = rhs.string_table_index; - start_addr = rhs.start_addr; - end_addr = rhs.end_addr; - line_number = rhs.line_number; - column_number = rhs.column_number; - } - friend std::ostream& operator<<(std::ostream& os, const open_statement& st) - { - os << hex << st.start_addr << " " << st.end_addr << " line:" - << dec << st.line_number << " file:" << st.string_table_index << " col:" << st.column_number << std::endl; - return os; - } - public: - Dwarf_Word string_table_index; - Dwarf_Addr start_addr; - Dwarf_Addr end_addr; - int line_number; - int column_number; -}; - - -void Object::parseLineInfoForCU(Dwarf_Die cuDIE, LineInformation* li_for_module) +void Object::parseLineInfoForCU(Offset offset_, LineInformation* li_for_module) { + Dwarf_Die cuDIE{}; + if(!DwarfDyninst::find_cu(*dwarf->type_dbg(), offset_, &cuDIE)) { + lineinfo_printf("No CU found at offset 0x%zx: %s\n", offset_, dwarf_errmsg(dwarf_errno())); + return; + } + /* Acquire this CU's source lines. */ Dwarf_Lines *lineBuffer; Dwarf_Attribute attr2; @@ -4034,7 +3306,7 @@ void Object::parseLineInfoForCU(Dwarf_Die cuDIE, LineInformation* li_for_module) } StringTablePtr strings(li_for_module->getStrings()); - boost::unique_lock l(strings->lock); + dyncompat::unique_lock l(strings->lock); Dwarf_Files *files; size_t offset = strings->size(); size_t filecount; @@ -4064,12 +3336,8 @@ void Object::parseLineInfoForCU(Dwarf_Die cuDIE, LineInformation* li_for_module) return s_name; }; - // dwarf_line_srcfileno == 0 means unknown; 1...n means files[0...n-1] - // so we ensure that we're adding a block of unknown, 1...n to the string table - // and that offset + dwarf_line_srcfileno points to the correct string - using namespace boost::filesystem; - strings->emplace_back("",""); - for(size_t i = 1; i < filecount; i++) + using namespace std::filesystem; + for(size_t i = 0; i < filecount; i++) { auto filename = dwarf_filesrc(files, i, nullptr, nullptr); if(!filename) continue; @@ -4197,14 +3465,138 @@ void Object::parseLineInfoForCU(Dwarf_Die cuDIE, LineInformation* li_for_module) } -LineInformation* Object::parseLineInfoForObject(StringTablePtr strings_) +void +dumpLineWithInlineContext +( + open_statement &saved_statement, + vector &inline_context +) +{ + saved_statement.dump(cout, true); + if (inline_context.size()) { + for (unsigned int i = inline_context.size(); i > 0; i--) { + inline_context[i -1].dump(cout, false); + } + } +} + + +void +Object::recordLine +( + Region *debug_str, + open_statement &saved_statement, + vector &inline_context +) { + lineinfo_printf("Object::recordLine for [%lx, %lx)\n", saved_statement.start_addr, saved_statement.end_addr); + // record line map entry + li_for_object->addLine((unsigned int)(saved_statement.string_table_index), + (unsigned int)(saved_statement.line_number), + (unsigned int)(saved_statement.column_number), + saved_statement.start_addr, saved_statement.end_addr); + // record inline context, if any + if (debug_str != nullptr && inline_context.size()) { + + // We only do a lookup when the current function does not contain the current range + if (containingFunc == nullptr || + containingFunc->getOffset() >= saved_statement.start_addr || + containingFunc->getOffset() + containingFunc->getSize() < saved_statement.start_addr) { + if (containingFunc != nullptr) { + associated_symtab->addFunctionRange(containingFunc, 0); + } + + associated_symtab->getContainingFunction(saved_statement.start_addr, containingFunc); + if (containingFunc == nullptr) { + lineinfo_printf("Cannot find function contains range [%lx, %lx)\n", saved_statement.start_addr, saved_statement.end_addr); + return; + } + } + + FunctionBase* cur = static_cast(containingFunc); + StringTablePtr strings(li_for_object->getStrings()); + + // Record all inline call sites + for (unsigned int i = 0; i < inline_context.size() - 1; ++i) { + cur = recordAnInlinedFunction( + inline_context[i], + inline_context[i + 1], + strings, + cur, + saved_statement.start_addr, + saved_statement.end_addr); + } + recordAnInlinedFunction( + *(inline_context.rbegin()), + saved_statement, + strings, + cur, + saved_statement.start_addr, + saved_statement.end_addr); + } + + if (common_debug_lineinfo) { + dumpLineWithInlineContext(saved_statement, inline_context); + } +} + +InlinedFunction* Object::recordAnInlinedFunction( + open_statement& caller, + open_statement& callee, + StringTablePtr strings, + FunctionBase *parent, + Dwarf_Addr start, + Dwarf_Addr end +) { + InlinedFunction *ifunc = new InlinedFunction(parent); + + // Use the filename and line number from the caller + const string& src_file = (*strings)[caller.string_table_index].str; + ifunc->callsite_file_number = strings->ensure(src_file); + ifunc->callsite_line = caller.line_number; + + // Use the function name from the callee + if (callee.funcname != nullptr) { + ifunc->addMangledName(callee.funcname, true, true); + } + ifunc->ranges.emplace_back(FuncRange(start, end - start, ifunc)); + return ifunc; +} + + +void +Object::lookupInlinedContext +( + vector &inline_context, + open_statement &saved_statement +) +{ + // If we encounter an unseen inline context, + // the current inlining call path is stored with the inline context id. + // Otherwise, we replace current context with the stored one + void* c = (void*)saved_statement.context; + if (c != nullptr) { + if (contextMap.find(c) == contextMap.end()) { + contextMap[c] = inline_context; + } else { + inline_context = contextMap[c]; + } + } +} + + +LineInformation* Object::parseLineInfoForObject(StringTablePtr strings) +{ + Region *debug_str = nullptr; + std::string debug_str_secname = ".debug_str"; + associated_symtab->findRegion(debug_str, debug_str_secname); + if (li_for_object) { // The line information for this object has been parsed. return li_for_object; } - li_for_object = new LineInformation(); - li_for_object->setStrings(strings_); + li_for_object = new LineInformation(); + li_for_object->setStrings(strings); /* Initialize libdwarf. */ Dwarf **dbg_ptr = dwarf->type_dbg(); if (!dbg_ptr) return li_for_object; @@ -4221,20 +3613,21 @@ LineInformation* Object::parseLineInfoForObject(StringTablePtr strings_) int status; - while ((status = dwarf_next_lines(dbg, off = next_off, &next_off, &cu, - &files, &fileCount, &lineBuffer, &lineCount)) == 0) - { + while (1) { - StringTablePtr strings(li_for_object->getStrings()); - boost::unique_lock l(strings->lock); +#pragma omp critical (next_lines) +{ + status = dwarf_next_lines(dbg, off = next_off, &next_off, &cu, + &files, &fileCount, &lineBuffer, &lineCount); +} + if (status != 0) break; + + + dyncompat::unique_lock l(strings->lock); size_t offset = strings->size(); - // dwarf_line_srcfileno == 0 means unknown; 1...n means files[0...n-1] - // so we ensure that we're adding a block of unknown, 1...n to the string table - // and that offset + dwarf_line_srcfileno points to the correct string - using namespace boost::filesystem; - strings->emplace_back("",""); - for(size_t i = 1; i < fileCount; i++) + using namespace std::filesystem; + for(size_t i = 0; i < fileCount; i++) { auto filename = dwarf_filesrc(files, i, nullptr, nullptr); if(!filename) continue; @@ -4259,12 +3652,19 @@ LineInformation* Object::parseLineInfoForObject(StringTablePtr strings_) Offset baseAddr = getBaseAddress(); - /* Iterate over this CU's source lines. */ - open_statement current_line; + /* Iterate over this object's source lines. */ + open_statement saved_statement; open_statement current_statement; + + vector inline_context; + // The line map may contain un-relocated entries, + // which often corresponds to dead code. + // If we find line map entries with zero address, + // we ignore them until the end of sequence + bool isZeroAddress = false; for(size_t i = 0; i < lineCount; i++ ) { - auto line = dwarf_onesrcline(lineBuffer, i); + auto line = dwarf_onesrcline(lineBuffer, i); /* Acquire the line number, address, source, and end of sequence flag. */ status = dwarf_lineno(line, ¤t_statement.line_number); @@ -4282,6 +3682,10 @@ LineInformation* Object::parseLineInfoForObject(StringTablePtr strings_) cout << "dwarf_lineaddr failed" << endl; continue; } + if (current_statement.start_addr == 0) { + isZeroAddress = true; + containingFunc = nullptr; + } current_statement.start_addr += baseAddr; @@ -4291,7 +3695,7 @@ LineInformation* Object::parseLineInfoForObject(StringTablePtr strings_) if (result) current_statement.start_addr = new_lineAddr; } - + //status = dwarf_line_srcfileno(line, ¤t_statement.string_table_index); const char * file_name = dwarf_linesrc(line, NULL, NULL); if ( !file_name ) { @@ -4304,9 +3708,9 @@ LineInformation* Object::parseLineInfoForObject(StringTablePtr strings_) int index = -1; for(size_t idx = offset; idx < strings->size(); ++idx) { - if((*strings)[idx].str==file_name_str) - { - index = idx; + if((*strings)[idx].str==file_name_str) + { + index = idx; break; } } @@ -4331,23 +3735,60 @@ LineInformation* Object::parseLineInfoForObject(StringTablePtr strings_) cout << "dwarf_linebeginstatement failed" << endl; continue; } - if (current_line.uninitialized()) { - current_line = current_statement; - } else { - current_line.end_addr = current_statement.start_addr; - if (!current_line.sameFileLineColumn(current_statement) || - isEndOfSequence) { - li_for_object->addLine((unsigned int)(current_line.string_table_index), - (unsigned int)(current_line.line_number), - (unsigned int)(current_line.column_number), - current_line.start_addr, current_line.end_addr); - current_line = current_statement; - } - } - if (isEndOfSequence) { - current_line.reset(); - } - } + + // Only attempt to parse inlining context and inline function name + // when there is a .debug_str section. + if (debug_str != nullptr) { + current_statement.context = dwarf_linecontext(lineBuffer, line); + current_statement.funcname = dwarf_linefunctionname(dbg, line); + } + + if (!isZeroAddress && saved_statement.uninitialized()) { + saved_statement = current_statement; + } else if (!isZeroAddress) { + bool pushed = false; + saved_statement.end_addr = current_statement.start_addr; + if (saved_statement.context || current_statement.context) { + // if saved_statement.context is non-zero, we need to remove any previously + // recorded inlined context that matches saved_statement.context or is + // nexted inside the matching context + lookupInlinedContext(inline_context, saved_statement); + + // record saved_statement and its inlining context if any addresses fall + // between saved_statement and current_statement. + if (current_statement.start_addr != saved_statement.start_addr) + recordLine (debug_str, saved_statement, inline_context); + + // record saved_statement as inlined context for current_statement` + inline_context.push_back(saved_statement); + pushed = true; + } + if ((!saved_statement.sameFileLineColumn(current_statement) || isEndOfSequence)) { + + if (!pushed) { + // we didn't add saved_statement to the inlined context of current_statement, + // so a line map entry for saved_statement needs to be recorded + recordLine (debug_str, saved_statement, inline_context); + } + + if (current_statement.context == 0) { + // a line map statement with context 0 clears all inlined context. + // remove all inlined context entries in the vector. + inline_context.resize(0); + } + + saved_statement = current_statement; + } + } + if (isEndOfSequence) { + isZeroAddress = false; + saved_statement.reset(); + contextMap.clear(); + if (containingFunc != nullptr) { + associated_symtab->addFunctionRange(containingFunc, 0); + } + } + } } return li_for_object; } @@ -4357,21 +3798,16 @@ void Object::parseLineInfoForAddr(Offset addr_to_find) { Dwarf **dbg_ptr = dwarf->line_dbg(); if (!dbg_ptr) return; - std::set mod_for_offset; - associated_symtab->findModuleByOffset(mod_for_offset, addr_to_find); - for (auto mod = mod_for_offset.begin(); - mod != mod_for_offset.end(); - ++mod) { - (*mod)->parseLineInformation(); - } + auto *m = associated_symtab->getContainingModule(addr_to_find); + if(m) m->parseLineInformation(); // no mod for offset means no line info for sure if we've parsed all ranges... } bool Object::hasDebugInfo() { - Region *ignore; + Region *unused; std::string debug_info = ".debug_info"; - bool hasDebugInfo = associated_symtab->findRegion(ignore, debug_info); + bool hasDebugInfo = associated_symtab->findRegion(unused, debug_info); return hasDebugInfo; } @@ -4391,7 +3827,6 @@ void Object::parseDwarfFileLineInfo() void Object::parseFileLineInfo() { if (parsedAllLineInfo) return; - parseStabFileLineInfo(); parseDwarfFileLineInfo(); parsedAllLineInfo = true; @@ -4403,7 +3838,6 @@ void Object::parseTypeInfo() { gettimeofday(&starttime, NULL); #endif - parseStabTypes(); Dwarf **typeInfo = dwarf->type_dbg(); if (!typeInfo) return; DwarfWalker walker(associated_symtab, *typeInfo); @@ -4420,318 +3854,6 @@ void Object::parseTypeInfo() { #endif } -void Object::parseStabTypes() { - types_printf("Entry to parseStabTypes for %s\n", associated_symtab->name().c_str()); - stab_entry *stabptr = NULL; - const char *next_stabstr = NULL; - - unsigned i; - char *modName = NULL; - string temp; - char *ptr = NULL, *ptr2 = NULL, *ptr3 = NULL; - bool parseActive = false; - - std::string *currentFunctionName = NULL; - Symbol *commonBlockVar = NULL; - string *commonBlockName = NULL; - boost::shared_ptr commonBlock = NULL; - - Module *mod; - typeCollection *tc = NULL; - -#if defined(TIMED_PARSE) - struct timeval starttime; - gettimeofday(&starttime, NULL); - unsigned int pss_count = 0; - double pss_dur = 0; - unsigned int src_count = 0; - double src_dur = 0; - unsigned int fun_count = 0; - double fun_dur = 0; - struct timeval t1, t2; -#endif - - - stabptr = get_stab_info(); - if (!stabptr) { - types_printf("\tWarning: no stab ptr, returning immediately\n"); - return; - } - - //Using the Object to get the pointers to the .stab and .stabstr - // XXX - Elf32 specific needs to be in seperate file -- jkh 3/18/99 - next_stabstr = stabptr->getStringBase(); - types_printf("\t Parsing %lu stab entries\n", stabptr->count()); - for (i = 0; i < stabptr->count(); i++) { - switch (stabptr->type(i)) { - case N_UNDF: /* start of object file */ - /* value contains offset of the next string table for next module */ - // assert(stabptr->nameIdx(i) == 1); - stabptr->setStringBase(next_stabstr); - next_stabstr = stabptr->getStringBase() + stabptr->val(i); - - //N_UNDF is the start of object file. It is time to - //clean source file name at this moment. - /* - if(currentSourceFile){ - delete currentSourceFile; - currentSourceFile = NULL; - delete absoluteDirectory; - absoluteDirectory = NULL; - delete currentFunctionName; - currentFunctionName = NULL; - currentFileInfo = NULL; - currentFuncInfo = NULL; - } - */ - break; - - case N_ENDM: /* end of object file */ - break; - - case N_SO: /* compilation source or file name */ - /* bperr("Resetting CURRENT FUNCTION NAME FOR NEXT OBJECT FILE\n");*/ -#ifdef TIMED_PARSE - src_count++; - gettimeofday(&t1, NULL); -#endif - symt_current_func_name = ""; // reset for next object file - symt_current_mangled_func_name = ""; // reset for next object file - symt_current_func = NULL; - - modName = const_cast(stabptr->name(i)); - // cerr << "checkpoint B" << endl; - ptr = strrchr(modName, '/'); - // cerr << "checkpoint C" << endl; - if (ptr) { - ptr++; - modName = ptr; - } - if (associated_symtab->findModuleByName(mod, modName)) { - tc = typeCollection::getModTypeCollection(mod); - parseActive = true; - if (!mod) { - create_printf("%s[%d]: FIXME\n", FILE__, __LINE__); - } else if (!tc) { - create_printf("%s[%d]: FIXME\n", FILE__, __LINE__); - } else - tc->clearNumberedTypes(); - } else { - //parseActive = false; - mod = associated_symtab->getDefaultModule(); - tc = typeCollection::getModTypeCollection(mod); - types_printf("\t Warning: failed to find module name matching %s, using %s\n", modName, - mod->fileName().c_str()); - } - -#ifdef TIMED_PARSE - gettimeofday(&t2, NULL); - src_dur += (t2.tv_sec - t1.tv_sec)*1000.0 + (t2.tv_usec - t1.tv_usec)/1000.0; - //src_dur += (t2.tv_sec/1000 + t2.tv_usec*1000) - (t1.tv_sec/1000 + t1.tv_usec*1000) ; -#endif - break; - case N_SLINE: - break; - default: - break; - } - if (parseActive || !is_aout()) { - std::vector bpfv; - switch (stabptr->type(i)) { - case N_FUN: -#ifdef TIMED_PARSE - fun_count++; - gettimeofday(&t1, NULL); -#endif - //all we have to do with function stabs at this point is to assure that we have - //properly set the var currentFunctionName for the later case of (parseActive) - symt_current_func = NULL; - int currentEntry = i; - int funlen = strlen(stabptr->name(currentEntry)); - ptr = new char[funlen + 1]; - strcpy(ptr, stabptr->name(currentEntry)); - while (strlen(ptr) != 0 && ptr[strlen(ptr) - 1] == '\\') { - ptr[strlen(ptr) - 1] = '\0'; - currentEntry++; - strcat(ptr, stabptr->name(currentEntry)); - } - char *colonPtr = NULL; - if (currentFunctionName) delete currentFunctionName; - if (!ptr || !(colonPtr = strchr(ptr, ':'))) - currentFunctionName = NULL; - else { - char *tmp = new char[colonPtr - ptr + 1]; - strncpy(tmp, ptr, colonPtr - ptr); - tmp[colonPtr - ptr] = '\0'; - currentFunctionName = new string(tmp); - // Shouldn't this be a function name lookup? - std::vector syms; - if (!associated_symtab->findSymbol(syms, - *currentFunctionName, - Symbol::ST_FUNCTION, - mangledName)) { - if (!associated_symtab->findSymbol(syms, - "_" + *currentFunctionName, - Symbol::ST_FUNCTION, - mangledName)) { - string fortranName = *currentFunctionName + string("_"); - if (associated_symtab->findSymbol(syms, - fortranName, - Symbol::ST_FUNCTION, - mangledName)) { - delete currentFunctionName; - currentFunctionName = new string(fortranName); - } - } - } - syms.clear(); - delete[] tmp; - } - delete[] ptr; -#ifdef TIMED_PARSE - gettimeofday(&t2, NULL); - fun_dur += (t2.tv_sec - t1.tv_sec)*1000.0 + (t2.tv_usec - t1.tv_usec)/1000.0; - //fun_dur += (t2.tv_sec/1000 + t2.tv_usec*1000) - (t1.tv_sec/1000 + t1.tv_usec*1000); -#endif - break; - } - if (!parseActive) continue; - switch (stabptr->type(i)) { - case N_BCOMM: { - // begin Fortran named common block - string tmp = string(stabptr->name(i)); - commonBlockName = &tmp; - // find the variable for the common block - - //TODO? change this. findLocalVar will cause an infinite loop - std::vector vars; - if (!associated_symtab->findSymbol(vars, - *commonBlockName, - Symbol::ST_OBJECT, - mangledName)) { - if (!associated_symtab->findSymbol(vars, - *commonBlockName, - Symbol::ST_OBJECT, - mangledName, - true)) - commonBlockVar = NULL; - else - commonBlockVar = vars[0]; - } else - commonBlockVar = vars[0]; - if (!commonBlockVar) { - // //bperr("unable to find variable %s\n", commonBlockName); - } else { - commonBlock = tc->findVariableType(*commonBlockName, Type::share); - if (!commonBlock->isCommonType()) { - // its still the null type, create a new one for it - commonBlock = Type::make_shared(*commonBlockName); - tc->addGlobalVariable(commonBlock); - } - // reset field list - commonBlock->asCommonType().beginCommonBlock(); - } - break; - } - case N_ECOMM: { - //copy this set of fields - if (!currentFunctionName) break; - if (!associated_symtab->findSymbol(bpfv, - *currentFunctionName, - Symbol::ST_FUNCTION, - mangledName)) { - if (!associated_symtab->findSymbol(bpfv, - *currentFunctionName, - Symbol::ST_FUNCTION, - mangledName, - true)) { - // //bperr("unable to locate current function %s\n", currentFunctionName->c_str()); - } else { - Symbol *func = bpfv[0]; - commonBlock->asCommonType().endCommonBlock(func, (void *) commonBlockVar->getOffset()); - } - } else { - if (bpfv.size() > 1) { - // warn if we find more than one function with this name - // //bperr("%s[%d]: WARNING: found %d funcs matching name %s, using the first\n", - // __FILE__, __LINE__, bpfv.size(), currentFunctionName->c_str()); - } - Symbol *func = bpfv[0]; - commonBlock->asCommonType().endCommonBlock(func, (void *) commonBlockVar->getOffset()); - } - //TODO?? size for local variables?? - // // update size if needed - // if (commonBlockVar) - // commonBlockVar->setSize(commonBlock->getSize()); - commonBlockVar = NULL; - commonBlock.reset(); - break; - } - // case C_BINCL: -- what is the elf version of this jkh 8/21/01 - // case C_EINCL: -- what is the elf version of this jkh 8/21/01 - case 32: // Global symbols -- N_GYSM - case 38: // Global Static -- N_STSYM - case N_FUN: - case 128: // typedefs and variables -- N_LSYM - case 160: // parameter variable -- N_PSYM - case 0xc6: // position-independant local typedefs -- N_ISYM - case 0xc8: // position-independant external typedefs -- N_ESYM -#ifdef TIMED_PARSE - pss_count++; - gettimeofday(&t1, NULL); -#endif - if (stabptr->type(i) == N_FUN) symt_current_func = NULL; - ptr = const_cast(stabptr->name(i)); - while (ptr[strlen(ptr) - 1] == '\\') { - //ptr[strlen(ptr)-1] = '\0'; - ptr2 = const_cast(stabptr->name(i + 1)); - ptr3 = (char *) malloc(strlen(ptr) + strlen(ptr2) + 1); - strcpy(ptr3, ptr); - ptr3[strlen(ptr) - 1] = '\0'; - strcat(ptr3, ptr2); - ptr = ptr3; - i++; - // XXX - memory leak on multiple cont. lines - } - // bperr("stab #%d = %s\n", i, ptr); - // may be nothing to parse - XXX jdd 5/13/99 - - temp = parseStabString(mod, stabptr->desc(i), (char *) ptr, stabptr->val(i), &commonBlock->asCommonType()); - if (temp.length()) { - //Error parsing the stabstr, return should be \0 - // //bperr( "Stab string parsing ERROR!! More to parse: %s\n", - // temp.c_str()); - // //bperr( " symbol: %s\n", ptr); - } -#ifdef TIMED_PARSE - gettimeofday(&t2, NULL); - pss_dur += (t2.tv_sec - t1.tv_sec)*1000.0 + (t2.tv_usec - t1.tv_usec)/1000.0; - // pss_dur += (t2.tv_sec/1000 + t2.tv_usec*1000) - (t1.tv_sec/1000 + t1.tv_usec*1000); -#endif - break; - default: - break; - } - } - } -#if defined(TIMED_PARSE) - struct timeval endtime; - gettimeofday(&endtime, NULL); - unsigned long lstarttime = starttime.tv_sec * 1000 * 1000 + starttime.tv_usec; - unsigned long lendtime = endtime.tv_sec * 1000 * 1000 + endtime.tv_usec; - unsigned long difftime = lendtime - lstarttime; - double dursecs = difftime/(1000 ); - cout << __FILE__ << ":" << __LINE__ <<": parseTypes("<< mod->fileName() - <<") took "< &segs) { } } -std::string Object::getFileName() const { - if (soname_) { - return soname_; - } - - return mf->filename(); -} - - // Object::isLoadable // True if this object is a loadable executable or library. This function // should produce the same result as the is_loadable() function in elfutils' diff --git a/symtabAPI/src/Object-elf.h b/symtabAPI/src/Object-elf.h index 456eb744a7..b17ab88962 100644 --- a/symtabAPI/src/Object-elf.h +++ b/symtabAPI/src/Object-elf.h @@ -43,12 +43,17 @@ #include "dwarfHandle.h" #endif +#include +#include +#include +#include +#include +#include #include #include "headers.h" -#include "Types.h" #include "MappedFile.h" #include "IntervalTree.h" - +#include "Module.h" #include #include #include @@ -68,198 +73,80 @@ namespace Dyninst{ namespace DwarfDyninst { class DwarfFrameParser; - typedef boost::shared_ptr DwarfFrameParserPtr; + typedef dyncompat::shared_ptr DwarfFrameParserPtr; } namespace SymtabAPI{ -/* - * The standard symbol table in an elf file is the .symtab section. This section does - * not have information to find the module to which a global symbol belongs, so we must - * also read the .stab section to get this info. - */ - -// Declarations for the .stab section. -// These are not declared in any system header files, so we must provide our own -// declarations. The declarations below were taken from: -// SPARCWorks 3.0.x Debugger Interface, July 1994 -// -struct stab32 { - unsigned int name; // stabstr table index for this symbol - unsigned char type; // type of this symbol - unsigned char other; - unsigned short desc; - unsigned int val; // value of this symbol -- usually zero. The real value must - // be obtained from the symtab section -}; -struct stab64 { - // XXX ELF stabs are currently not implementing actual 64-bit support - // on AMD-64, for which this separation was introduced. Until we - // start seeing stab records with fields of the appropriate length, - // we should assume the smaller records. - //unsigned long name; // stabstr table index for this symbol - unsigned int name; // stabstr table index for this symbol - unsigned char type; // type of this symbol - unsigned char other; - unsigned short desc; - //unsigned long val; - unsigned int val; // value of this symbol -- usually zero. The real value must - // be obtained from the symtab section -}; - -// -// Extended to a class for 32/64-bit stab entries at runtime. - Ray -// -class stab_entry { - public: - stab_entry(void *_stabptr = 0, const char *_stabstr = 0, long _nsyms = 0) - : stabptr(_stabptr), stabstr(_stabstr), nsyms(_nsyms) { } - virtual ~stab_entry() {} - - virtual const char *name(int i) = 0; - virtual unsigned long nameIdx(int i) = 0; - virtual unsigned char type(int i) = 0; - virtual unsigned char other(int i) = 0; - virtual unsigned short desc(int i) = 0; - virtual unsigned long val(int i) = 0; - - unsigned long count() { return nsyms; } - void setStringBase(const char *ptr) { stabstr = const_cast(ptr); } - const char *getStringBase() { return stabstr; } - - protected: - void *stabptr; - const char *stabstr; - long nsyms; -}; - -class stab_entry_32 : public stab_entry { - public: - stab_entry_32(void *_stabptr = 0, const char *_stabstr = 0, long _nsyms = 0) - : stab_entry(_stabptr, _stabstr, _nsyms) { } - virtual ~stab_entry_32() {} - - const char *name(int i = 0) { - if (!stabptr) { - return "bad_name"; - } - return stabstr + ((stab32 *)stabptr)[i].name; - } - unsigned long nameIdx(int i = 0) { - if (!stabptr) { - return 0L; - } - return ((stab32 *)stabptr)[i].name; - } - unsigned char type(int i = 0) { - if (!stabptr) { - return 0; - } - return ((stab32 *)stabptr)[i].type; - } - unsigned char other(int i = 0) { - if (!stabptr) { - return 0; - } - return ((stab32 *)stabptr)[i].other; - } - unsigned short desc(int i = 0) { - if (!stabptr) { - return 0; - } - return ((stab32 *)stabptr)[i].desc; - } - unsigned long val(int i = 0) { - if (!stabptr) { - return 0L; - } - return ((stab32 *)stabptr)[i].val; - } -}; - -class stab_entry_64 : public stab_entry { - public: - stab_entry_64(void *_stabptr = 0, const char *_stabstr = 0, long _nsyms = 0) - : stab_entry(_stabptr, _stabstr, _nsyms) { } - virtual ~stab_entry_64() {} - - const char *name(int i = 0) { - if (!stabptr) { - return "bad_name"; - } - return stabstr + ((stab64 *)stabptr)[i].name; - } - unsigned long nameIdx(int i = 0) { - if (!stabptr) { - return 0L; - } - return ((stab64 *)stabptr)[i].name; - } - unsigned char type(int i = 0) { - if (!stabptr) { - return 0; - } - return ((stab64 *)stabptr)[i].type; - } - unsigned char other(int i = 0) { - if (!stabptr) { - return 0; - } - return ((stab64 *)stabptr)[i].other; - } - unsigned short desc(int i = 0) { - if (!stabptr) { - return 0; - } - return ((stab64 *)stabptr)[i].desc; - } - unsigned long val(int i = 0) { - if (!stabptr) { - return 0L; - } - return ((stab64 *)stabptr)[i].val; - } -}; - -// Types -#define N_UNDF 0x00 /* start of object file */ -#define N_GSYM 0x20 /* global symbol */ -#define N_FUN 0x24 /* function or procedure */ -#define N_STSYM 0x26 /* initialized static symbol */ -#define N_LCSYM 0x28 /* unitialized static symbol */ -#define N_ROSYM 0x2c /* read-only static symbol */ -#define N_OPT 0x3c /* compiler options */ -#define N_ENDM 0x62 /* end module */ -#define N_SO 0x64 /* source directory and file */ -#define N_ENTRY 0xa4 /* fortran alternate subroutine entry point */ -#define N_BCOMM 0xe2 /* start fortran named common block */ -#define N_ECOMM 0xe4 /* start fortran named common block */ - -// Language code -- the desc field in a N_SO entry is a language code -#define N_SO_AS 1 /* assembler source */ -#define N_SO_C 2 /* K & R C source */ -#define N_SO_ANSI_C 3 /* ANSI C source */ -#define N_SO_CC 4 /* C++ source */ -#define N_SO_FORTRAN 5 /* fortran source */ -#define N_SO_PASCAL 6 /* Pascal source */ -#define N_SO_F90 7 /* Fortran90 source */ - -//line information data -#define N_SLINE 0x44 /* line number in text segment */ -#define N_SOL 0x84 /* name of the include file*/ - -// Symbol descriptors -// The format of a name is ": -// The following are the descriptors of interest -#define SD_GLOBAL_FUN 'F' /* global function or procedure */ -#define SD_PROTOTYPE 'P' /* function prototypes */ -#define SD_GLOBAL_VAR 'G' /* global variable */ - -// end of stab declarations class pdElfShdr; class Symtab; class Region; class Object; +class InlinedFunction; + +class open_statement { + public: + open_statement() { reset(); } + open_statement(const open_statement&) = default; + Dwarf_Addr noAddress() { return (Dwarf_Addr) ~0; } + bool uninitialized() { + return start_addr == noAddress(); + } + void reset() { + string_table_index = -1; + start_addr = noAddress(); + end_addr = noAddress(); + line_number = 0; + column_number = 0; + context = nullptr; + funcname = nullptr; + } + bool sameFileLineColumn(const open_statement &rhs) { + return ((string_table_index == rhs.string_table_index) && + (line_number == rhs.line_number) && + (column_number == rhs.column_number)); + } + void operator=(const open_statement &rhs) { + string_table_index = rhs.string_table_index; + start_addr = rhs.start_addr; + end_addr = rhs.end_addr; + line_number = rhs.line_number; + column_number = rhs.column_number; + context = rhs.context; + funcname = rhs.funcname; + } + friend std::ostream& operator<<(std::ostream& os, const open_statement& st) + { + st.dump(os, true); + return os; + } + + void dump(std::ostream& os, bool addrRange) const { + // to facilitate comparison with nvdisasm output, where each function starts at 0, + // set o to an offset that makes a function of interest report addresses that + // match its unrelocated offsets reported by nvdisasm + unsigned int o = 0; + if (addrRange) os << "[" << std::hex << start_addr - o << ", " << end_addr - o << "]"; + else os << " inlined at"; + os << " file:" << string_table_index; + os << " line:" << std::dec << line_number; + os << " col:" << column_number; + if (context != nullptr) { + os << " context " << context; + os << " function name " << funcname; + } + os << std::endl; + } + public: + Dwarf_Word string_table_index; + Dwarf_Addr start_addr; + Dwarf_Addr end_addr; + int line_number; + int column_number; + Dwarf_Line* context; + const char* funcname; +}; + class Object : public AObject { @@ -275,24 +162,20 @@ class Object : public AObject virtual ~Object(); bool emitDriver(std::string fName, std::set &allSymbols, unsigned flag); - - const char *elf_vaddr_to_ptr(Offset vaddr) const; - bool hasStabInfo() const { return ! ( !stab_off_ || !stab_size_ || !stabstr_off_ ); } + bool hasDwarfInfo() const { return dwarvenDebugInfo; } - stab_entry * get_stab_info() const; - std::string getFileName() const; void getModuleLanguageInfo(dyn_hash_map *mod_langs); void parseFileLineInfo(); - void parseTypeInfo(); + void addModule(SymtabAPI::Module* m) override; - bool needs_function_binding() const { return (plt_addr_ > 0); } - bool get_func_binding_table(std::vector &fbt) const; - bool get_func_binding_table_ptr(const std::vector *&fbt) const; + bool needs_function_binding() const override { return (plt_addr_ > 0); } + bool get_func_binding_table(std::vector &fbt) const override; + bool get_func_binding_table_ptr(const std::vector *&fbt) const override; void getDependencies(std::vector &deps); std::vector &libsRMd(); - bool addRelocationEntry(relocationEntry &re); + bool addRelocationEntry(relocationEntry &re) override; //getLoadAddress may return 0 on shared objects Offset getLoadAddress() const { return loadAddress_; } @@ -306,7 +189,7 @@ class Object : public AObject bool removePrereqLibrary(std::string libname); void insertDynamicEntry(long name, long value); - virtual char *mem_image() const + virtual char *mem_image() const override { assert(mf); return (char *)mf->base_addr(); @@ -349,9 +232,9 @@ class Object : public AObject return false; } - Dyninst::Architecture getArch() const; - bool isBigEndianDataEncoding() const; - bool getABIVersion(int &major, int &minor) const; + Dyninst::Architecture getArch() const override; + bool isBigEndianDataEncoding() const override; + bool getABIVersion(int &major, int &minor) const override; bool is_offset_in_plt(Offset offset) const; Elf_X_Shdr *getRegionHdrByAddr(Offset addr); int getRegionHdrIndexByAddr(Offset addr); @@ -361,20 +244,22 @@ class Object : public AObject bool getRegValueAtFrame(Address pc, Dyninst::MachRegister reg, Dyninst::MachRegisterVal ®_result, - MemRegReader *reader); - bool hasFrameDebugInfo(); + MemRegReader *reader) override; + bool hasFrameDebugInfo() override; bool convertDebugOffset(Offset off, Offset &new_off); std::vector< std::vector > getMoveSecAddrRange() const {return moveSecAddrRange;} dyn_hash_map getTagRegionMapping() const { return secTagRegionMapping;} + bool get_relocationRelr_entries(unsigned relr_scnp_index); bool hasReldyn() const {return hasReldyn_;} bool hasReladyn() const {return hasReladyn_;} + bool hasRelrdyn() const {return hasRelrdyn_;} bool hasRelplt() const {return hasRelplt_;} bool hasRelaplt() const {return hasRelaplt_;} bool hasNoteSection() const {return hasNoteSection_;} - Region::RegionType getRelType() const { return relType_; } + Region::RegionType getRelType() const override { return relType_; } Offset getTextAddr() const {return text_addr_;} Offset getSymtabAddr() const {return symtab_addr_;} @@ -387,6 +272,9 @@ class Object : public AObject Offset getRelPLTSize() const { return rel_plt_size_; } Offset getRelDynAddr() const { return rel_addr_; } Offset getRelDynSize() const { return rel_size_; } + Offset getRelrDynAddr() const { return relr_addr_; } + Offset getRelrDynSize() const { return relr_size_; } + Offset getRelrDynEntrySize() const { return relr_entry_size_; } const char* getSoname() const { return soname_; } bool hasPieFlag() const { return hasPieFlag_; } bool hasProgramLoad() const { return hasProgramLoad_; } @@ -405,22 +293,26 @@ class Object : public AObject std::vector &getPLTRelocs() { return fbt_; } std::vector &getDynRelocs() { return relocation_table_; } + std::vector &getRelrDynRelocs() { return relr_relocation_table_; } + + const dyn_hash_map> &getVersionMapping() const { return versionMapping; } + const dyn_hash_map &getVersionFileNameMapping() const { return versionFileNameMapping; } Offset getInitAddr() const {return init_addr_; } Offset getFiniAddr() const { return fini_addr_; } - virtual void setTruncateLinePaths(bool value); - virtual bool getTruncateLinePaths(); + virtual void setTruncateLinePaths(bool value) override; + virtual bool getTruncateLinePaths() override; Elf_X * getElfHandle() { return elfHdr; } unsigned gotSize() const { return got_size_; } Offset gotAddr() const { return got_addr_; } - SYMTAB_EXPORT virtual void getSegmentsSymReader(std::vector &segs); + SYMTAB_EXPORT virtual void getSegmentsSymReader(std::vector &segs) override; private: - std::vector > > freeList; + std::vector > > freeList; static void log_elferror (void (*)(const char *), const char *); Elf_X *elfHdr; @@ -432,9 +324,11 @@ class Object : public AObject bool hasReldyn_; bool hasReladyn_; + bool hasRelrdyn_; bool hasRelplt_; bool hasRelaplt_; Region::RegionType relType_; + std::vector relr_relocation_table_; bool hasNoteSection_; @@ -464,17 +358,12 @@ class Object : public AObject Offset rel_addr_; unsigned rel_size_; // DT_REL/DT_RELA in dynamic section unsigned rel_entry_size_; // DT_REL/DT_RELA in dynamic section + Offset relr_addr_; + unsigned relr_size_; // DT_RELR in dynamic section + unsigned relr_entry_size_; // DT_RELR in dynamic section Offset opd_addr_; unsigned opd_size_; - Offset stab_off_; // .stab section - unsigned stab_size_; // .stab section - Offset stabstr_off_; // .stabstr section - - Offset stab_indx_off_; // .stab.index section - unsigned stab_indx_size_; // .stab.index section - Offset stabstr_indx_off_; // .stabstr.index section - bool dwarvenDebugInfo; // is DWARF debug info present? Offset loadAddress_; // The object may specify a load address // Set to 0 if it may load anywhere @@ -524,8 +413,6 @@ class Object : public AObject bool loaded_elf( Offset &, Offset &, Elf_X_Shdr* &, Elf_X_Shdr* &, Elf_X_Shdr* &, - Elf_X_Shdr* &, Elf_X_Shdr* &, - Elf_X_Shdr* &, Elf_X_Shdr* &, Elf_X_Shdr*& rel_plt_scnp, Elf_X_Shdr*& plt_scnp, Elf_X_Shdr*& got_scnp, Elf_X_Shdr*& dynsym_scnp, Elf_X_Shdr*& dynstr_scnp, Elf_X_Shdr*& dynamic_scnp, Elf_X_Shdr*& eh_frame, @@ -536,7 +423,6 @@ class Object : public AObject Symbol *handle_opd_symbol(Region *opd, Symbol *sym); void handle_opd_relocations(); void parse_opd(Elf_X_Shdr *); - void parseStabFileLineInfo(); public: void parseDwarfFileLineInfo(); void parseLineInfoForAddr(Offset addr_to_find); @@ -544,17 +430,29 @@ class Object : public AObject bool hasDebugInfo(); private: - void parseLineInfoForCU(Module::DebugInfoT cuDIE, LineInformation* li); + void parseLineInfoForCU(Offset offset, LineInformation* li) override; + void recordLine( + Region *debug_str, + open_statement &saved_statement, + std::vector &inline_context + ); + InlinedFunction* recordAnInlinedFunction( + open_statement&, + open_statement&, + StringTablePtr, + FunctionBase*, + Dwarf_Addr, + Dwarf_Addr + ); + + void lookupInlinedContext( std::vector &, open_statement &); LineInformation* li_for_object; LineInformation* parseLineInfoForObject(StringTablePtr strings); - bool dwarf_parse_aranges(::Dwarf *dbg, std::set& dies_seen); void parseDwarfTypes(Symtab *obj); - void parseStabTypes(); void load_object(bool); - void load_shared_object(bool); // initialize relocation_table_ from .rel[a].plt section entries bool get_relocation_entries(Elf_X_Shdr *&rel_plt_scnp, @@ -577,17 +475,14 @@ class Object : public AObject Elf_X_Shdr* bssscnp, Elf_X_Shdr* symscnp, Elf_X_Shdr* symtab_shndx_scnp, - bool shared_library, - std::string module); + bool shared_library); void parse_dynamicSymbols( Elf_X_Shdr *& dyn_scnp, Elf_X_Data &symdata, - Elf_X_Data &strdata, bool shared_library, - std::string module); + Elf_X_Data &strdata, bool shared_library); void find_code_and_data(Elf_X &elf, Offset txtaddr, Offset dataddr); - bool fix_global_symbol_modules_static_stab(Elf_X_Shdr *stabscnp, - Elf_X_Shdr *stabstrscnp); + bool fix_global_symbol_modules_static_dwarf(); void get_valid_memory_areas(Elf_X &elf); @@ -597,10 +492,6 @@ class Object : public AObject std::vector &catch_addrs); // Line info: CUs to skip std::set modules_parsed_for_line_info; -#if defined(cap_dwarf) - std::string find_symbol(std::string name); - -#endif public: struct DbgAddrConversion_t { @@ -620,6 +511,8 @@ class Object : public AObject std::vector > new_dynamic_entries; private: const char* soname_; + Function* containingFunc; + std::unordered_map > contextMap; }; diff --git a/symtabAPI/src/Object-nt.C b/symtabAPI/src/Object-nt.C index 80318d7a8d..ecfb2cf7ed 100644 --- a/symtabAPI/src/Object-nt.C +++ b/symtabAPI/src/Object-nt.C @@ -28,6 +28,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include #include #include @@ -81,7 +82,7 @@ static void printSysError(unsigned errNo) { fprintf(stderr, "Couldn't print error message\n"); printSysError(GetLastError()); } - fprintf(stderr, "*** System error [%d]: %s\n", errNo, buf); + fprintf(stderr, "*** System error [%u]: %s\n", errNo, buf); fflush(stderr); } @@ -157,19 +158,17 @@ Object::Module::FindFile( std::string name ) void Object::File::DefineSymbols( dyn_hash_map >& allSyms, - map &symsToMods, const std::string& modName ) const { for( std::vector::const_iterator iter = syms.begin(); iter != syms.end(); iter++ ) { const Object::intSymbol* curSym = * iter; assert( curSym != NULL ); - curSym->DefineSymbol( allSyms, symsToMods, modName ); + curSym->DefineSymbol( allSyms, modName ); } } void Object::intSymbol::DefineSymbol(dyn_hash_map >&allSyms, - map &symsToMods, const std::string& modName ) const { Symbol *sym = new Symbol(GetName(), @@ -181,13 +180,11 @@ Object::intSymbol::DefineSymbol(dyn_hash_map > GetRegion(), GetSize()); allSyms[GetName()].push_back(sym); - symsToMods[sym] = modName; } void Object::Module::DefineSymbols( const Object* obj, - dyn_hash_map > & syms, - map &symsToMods ) const + dyn_hash_map > & syms) const { // define Paradyn/dyninst modules and symbols if( !isDll ) @@ -211,9 +208,8 @@ Object::Module::DefineSymbols( const Object* obj, // TODO also pass size // add symbols for each of the file's symbols syms[curFile->GetName()].push_back(sym); - symsToMods[sym] = curFile->GetName(); - curFile->DefineSymbols( syms, symsToMods, curFile->GetName() ); + curFile->DefineSymbols( syms, curFile->GetName() ); } } else @@ -241,7 +237,7 @@ Object::Module::DefineSymbols( const Object* obj, const File* curFile = *iter; assert( curFile != NULL ); // add symbols for each of the file's symbols - curFile->DefineSymbols( syms, symsToMods, name ); + curFile->DefineSymbols( syms, name ); } } } @@ -585,7 +581,7 @@ void Object::ParseSymbolInfo( bool alloc_syms ) assert( curModule != NULL ); curModule->BuildSymbolMap( this ); if (alloc_syms) - curModule->DefineSymbols( this, symbols_, symsToModules_ ); + curModule->DefineSymbols( this, symbols_); no_of_symbols_ = symbols_.size(); //fprintf(stderr, "%s[%d]: removed call to parseFileLineInfo here\n", FILE__, __LINE__); @@ -631,10 +627,13 @@ void Object::AddTLSFunctions() // calculate the address of the TLS callback array and make sure it's valid secn = findEnclosingRegion(tlsDir->AddressOfCallBacks - imgBase); + if (!secn) { + return; + } Offset cbOffSec = tlsDir->AddressOfCallBacks - secn->getMemOffset() - imgBase; - if (!secn || cbOffSec > secn->getDiskSize()) { + if (cbOffSec > secn->getDiskSize()) { return; } Offset cbOffDisk = cbOffSec + secn->getDiskOffset(); @@ -652,7 +651,7 @@ void Object::AddTLSFunctions() Offset baseAddr = 0; Object::File *pFile = curModule->GetDefaultFile(); char funcName [128]; - snprintf(funcName, 128, "tls_cb_%d", tidx); + snprintf(funcName, 128, "tls_cb_%u", tidx); pFile->AddSymbol( new Object::intSymbol ( funcName, funcOff, @@ -830,7 +829,6 @@ void Object::FindInterestingSections(bool alloc_syms, bool defensive) funcAddr); sym->setDynamic(true); // it's exported, equivalent to ELF dynamic syms symbols_[name].push_back(sym); - symsToModules_[sym] = curModule->GetName(); } } } @@ -1184,9 +1182,9 @@ void Object::parseFileLineInfo() } typedef struct localsStruct { - Function *func; - Offset base; - HANDLE p; + Function *func{}; + Offset base{}; + HANDLE p{}; map foundSyms; localsStruct() : foundSyms() {} } localsStruct; @@ -1305,7 +1303,7 @@ BOOL CALLBACK enumLocalSymbols(PSYMBOL_INFO pSymInfo, unsigned long symSize, } else { - fprintf(stderr, "[%s:%u] - Local variable of unknown type. %s in %s\n", + fprintf(stderr, "[%s:%d] - Local variable of unknown type. %s in %s\n", __FILE__, __LINE__, pSymInfo->Name, func->pretty_names_begin()->c_str()); paramType = "unknown"; } @@ -1533,7 +1531,7 @@ static Type *getPointerType(HANDLE p, Offset base, int typeIndex, Module *mod) { result = SymGetTypeInfo(p, base, typeIndex, TI_GET_TYPEID, &baseTypeIndex); if (!result) { - fprintf(stderr, "[%s:%u] - TI_GET_TYPEID failed\n", __FILE__, __LINE__); + fprintf(stderr, "[%s:%d] - TI_GET_TYPEID failed\n", __FILE__, __LINE__); return NULL; } @@ -1547,7 +1545,7 @@ static Type *getPointerType(HANDLE p, Offset base, int typeIndex, Module *mod) { baseType = getType(p, base, baseTypeIndex, mod); if (!baseType) { - fprintf(stderr, "[%s:%u] - getType failed\n", __FILE__, __LINE__); + fprintf(stderr, "[%s:%d] - getType failed\n", __FILE__, __LINE__); return NULL; } @@ -1566,7 +1564,7 @@ static Type *getArrayType(HANDLE p, Offset base, int typeIndex, Module *mod) { //Get the index type (usually an int of some kind). Currently not used. result = SymGetTypeInfo(p, base, typeIndex, TI_GET_ARRAYINDEXTYPEID, &index); if (!result) { - fprintf(stderr, "[%s:%u] - TI_GET_ARRAYINDEXTYPEID failed\n", + fprintf(stderr, "[%s:%d] - TI_GET_ARRAYINDEXTYPEID failed\n", __FILE__, __LINE__); return NULL; } @@ -1575,7 +1573,7 @@ static Type *getArrayType(HANDLE p, Offset base, int typeIndex, Module *mod) { //Get the base type (the type of the elements in the array) result = SymGetTypeInfo(p, base, typeIndex, TI_GET_TYPEID, &baseIndex); if (!result) { - fprintf(stderr, "[%s:%u] - TI_GET_TYPEID failed\n", __FILE__, __LINE__); + fprintf(stderr, "[%s:%d] - TI_GET_TYPEID failed\n", __FILE__, __LINE__); return NULL; } baseType = getType(p, base, baseIndex, mod); @@ -1608,7 +1606,7 @@ static Type *getTypedefType(HANDLE p, Offset base, int typeIndex, Module *mod) { result = SymGetTypeInfo(p, base, typeIndex, TI_GET_TYPEID, &baseTypeIndex); if (!result) { - fprintf(stderr, "[%s:%u] - TI_GET_TYPEID failed\n", __FILE__, __LINE__); + fprintf(stderr, "[%s:%d] - TI_GET_TYPEID failed\n", __FILE__, __LINE__); return NULL; } baseType = getType(p, base, baseTypeIndex, mod); @@ -1762,7 +1760,7 @@ static Type *getFunctionType(HANDLE p, Offset base, int typeIndex, Module *mod) result = SymGetTypeInfo(p, base, typeIndex, TI_GET_TYPEID, &retTypeIndex); if (!result) { - fprintf(stderr, "[%s:%u] - Couldn't TI_GET_TYPEID\n", __FILE__, __LINE__); + fprintf(stderr, "[%s:%d] - Couldn't TI_GET_TYPEID\n", __FILE__, __LINE__); return NULL; } diff --git a/symtabAPI/src/Object-nt.h b/symtabAPI/src/Object-nt.h index 7283d97d25..4c2958bd4e 100644 --- a/symtabAPI/src/Object-nt.h +++ b/symtabAPI/src/Object-nt.h @@ -44,7 +44,9 @@ * header files. ************************************************************************/ -#include "common/src/Types.h" +#include +#include +#include #include #include #include diff --git a/symtabAPI/src/Object.C b/symtabAPI/src/Object.C index f32f428f14..0ba9d5347c 100644 --- a/symtabAPI/src/Object.C +++ b/symtabAPI/src/Object.C @@ -30,6 +30,7 @@ // $Id: Object.C,v 1.31 2008/11/03 15:19:25 jaw Exp $ +#include #include "symutil.h" #include "Annotatable.h" @@ -52,98 +53,6 @@ using namespace std; using namespace Dyninst; using namespace Dyninst::SymtabAPI; - -//#ifdef BINEDIT_DEBUG -bool ____sym_hdr_printed = false; -void print_symbols( std::vector< Symbol *>& allsymbols ) { - FILE* fd = stdout; - Symbol *sym; - std::string modname; - if (!____sym_hdr_printed) { - fprintf(fd, "%-20s %-15s %-10s %5s SEC TYP LN VIS INFO\n", - "SYMBOL", "MODULE", "ADDR", "SIZE"); - ____sym_hdr_printed = true; - } - for (unsigned i=0; igetModule() ? sym->getModule()->fileName() : ""); - //if (sym->getName() == "__gmon_start__") { - //if (modname == "libspecial.so" || modname == "libprofile.so") { - //if (sym->getLinkage() == Symbol::SL_WEAK) { - //if (sym->isInDynSymtab()) { - if (1) { - fprintf(fd, "%-20s %-15s 0x%08x %5u %3u", - sym->getMangledName().substr(0,20).c_str(), - //modname.size() > 15 ? modname.substr(modname.size()-15,15).c_str() : modname.c_str(), - "", - (unsigned)sym->getOffset(), - (unsigned)sym->getSize(), - sym->getRegion() ? sym->getRegion()->getRegionNumber() : 0 - ); - switch (sym->getType()) { - case Symbol::ST_FUNCTION: fprintf(fd, " FUN"); break; - case Symbol::ST_TLS: fprintf(fd, " TLS"); break; - case Symbol::ST_OBJECT: fprintf(fd, " OBJ"); break; - case Symbol::ST_MODULE: fprintf(fd, " MOD"); break; - case Symbol::ST_SECTION: fprintf(fd, " SEC"); break; - case Symbol::ST_DELETED: fprintf(fd, " DEL"); break; - case Symbol::ST_NOTYPE: fprintf(fd, " - "); break; - default: - case Symbol::ST_UNKNOWN: fprintf(fd, " ???"); break; - } - switch (sym->getLinkage()) { - case Symbol::SL_UNKNOWN: fprintf(fd, " ??"); break; - case Symbol::SL_GLOBAL: fprintf(fd, " GL"); break; - case Symbol::SL_LOCAL: fprintf(fd, " LO"); break; - case Symbol::SL_WEAK: fprintf(fd, " WK"); break; - case Symbol::SL_UNIQUE: fprintf(fd, " UQ"); break; - } - switch (sym->getVisibility()) { - case Symbol::SV_UNKNOWN: fprintf(fd, " ???"); break; - case Symbol::SV_DEFAULT: fprintf(fd, " - "); break; - case Symbol::SV_INTERNAL: fprintf(fd, " INT"); break; - case Symbol::SV_HIDDEN: fprintf(fd, " HID"); break; - case Symbol::SV_PROTECTED: fprintf(fd, " PRO"); break; - } - fprintf(fd, " "); - if (sym->isInSymtab()) - fprintf(fd, " STA"); - if (sym->isInDynSymtab()) - fprintf(fd, " DYN"); - if (sym->isAbsolute()) - fprintf(fd, " ABS"); - if (sym->isDebug()) - fprintf(fd, " DBG"); - std::string fileName; - std::vector *vers; - if (sym->getVersionFileName(fileName)) - fprintf(fd, " [%s]", fileName.c_str()); - if (sym->getVersions(vers)) { - fprintf(fd, " {"); - for (unsigned j=0; j < vers->size(); j++) { - if (j > 0) - fprintf(fd, ", "); - fprintf(fd, "%s", (*vers)[j].c_str()); - } - fprintf(fd, "}"); - } - fprintf(fd,"\n"); - } - } -} -void print_symbol_map( dyn_hash_map< std::string, std::vector< Symbol *> > *symbols) { - dyn_hash_map< std::string, std::vector< Symbol *> >::iterator siter = symbols->begin(); - int total_syms = 0; - while (siter != symbols->end()) { - print_symbols(siter->second); - total_syms += siter->second.size(); - siter++; - } - printf("%d total symbol(s)\n", total_syms); -} -//#endif - - const char *Dyninst::SymtabAPI::supportedLanguages2Str(supportedLanguages s) { switch(s) { @@ -153,7 +62,6 @@ const char *Dyninst::SymtabAPI::supportedLanguages2Str(supportedLanguages s) CASE_RETURN_STR(lang_CPlusPlus); CASE_RETURN_STR(lang_GnuCPlusPlus); CASE_RETURN_STR(lang_Fortran); - CASE_RETURN_STR(lang_Fortran_with_pretty_debug); CASE_RETURN_STR(lang_CMFortran); }; return "bad_language"; @@ -394,75 +302,6 @@ SYMTAB_EXPORT AObject::AObject(MappedFile *mf_, void (*err_func)(const char *), { } -// a helper routine that selects a language based on information from the symtab -supportedLanguages AObject::pickLanguage(string &working_module, char *working_options, - supportedLanguages working_lang) -{ - supportedLanguages lang = lang_Unknown; - static int sticky_fortran_modifier_flag = 0; - // (2) -- check suffixes -- try to keep most common suffixes near the top of the checklist - string::size_type len = working_module.length(); - if((len>2) && (working_module.substr(len-2,2) == string(".c"))) lang = lang_C; - else if ((len>2) && (working_module.substr(len-2,2) == string(".C"))) lang = lang_CPlusPlus; - else if ((len>4) && (working_module.substr(len-4,4) == string(".cpp"))) lang = lang_CPlusPlus; - else if ((len>2) && (working_module.substr(len-2,2) == string(".F"))) lang = lang_Fortran; - else if ((len>2) && (working_module.substr(len-2,2) == string(".f"))) lang = lang_Fortran; - else if ((len>3) && (working_module.substr(len-3,3) == string(".cc"))) lang = lang_C; - else if ((len>2) && (working_module.substr(len-2,2) == string(".a"))) lang = lang_Assembly; // is this right? - else if ((len>2) && (working_module.substr(len-2,2) == string(".S"))) lang = lang_Assembly; - else if ((len>2) && (working_module.substr(len-2,2) == string(".s"))) lang = lang_Assembly; - else - { - //(3) -- try to use options string -- if we have 'em - if (working_options) - { - // NOTE: a binary is labeled "gcc2_compiled" even if compiled w/g77 -- thus this is - // quite inaccurate to make such assumptions - if (strstr(working_options, "gcc")) - lang = lang_C; - else if (strstr(working_options, "g++")) - lang = lang_CPlusPlus; - } - } - // This next section tries to determine the version of the debug info generator for a - // Sun fortran compiler. Some leave the underscores on names in the debug info, and some - // have the "pretty" names, we need to detect this in order to properly read the debug. - if (working_lang == lang_Fortran) - { - if (sticky_fortran_modifier_flag) - { - //cerr << FILE__ << __LINE__ << ": UPDATE: lang_Fortran->lang_Fortran_with_pretty_debug." << endl; - working_lang = lang_Fortran_with_pretty_debug; - } - else if (working_options) - { - char *dbg_gen = NULL; - //cerr << FILE__ << __LINE__ << ": OPT: " << working_options << endl; - if (NULL != (dbg_gen = strstr(working_options, "DBG_GEN="))) - { - //cerr << __FILE__ << __LINE__ << ": OPT: " << dbg_gen << endl; - // Sun fortran compiler (probably), need to examine version - char *dbg_gen_ver_maj = dbg_gen + strlen("DBG_GEN="); - //cerr << __FILE__ << __LINE__ << ": OPT: " << dbg_gen_ver_maj << endl; - char *next_dot = strchr(dbg_gen_ver_maj, '.'); - if (NULL != next_dot) - { - *next_dot = '\0'; //terminate major version number string - int ver_maj = atoi(dbg_gen_ver_maj); - //cerr <<"Major Debug Ver. "<lang_Fortran_with_pretty_debug. " << "Major Debug Ver. "<second)[ currentPositionInVector ]); } -const std::string AObject::findModuleForSym(Symbol *sym) { - dyn_c_hash_map::const_accessor ca; - if (!symsToModules_.find(ca, sym)) { - assert(!"symsToModules_.find(ca, sym)"); - } - return ca->second; -} - -void AObject::clearSymsToMods() { - symsToModules_.clear(); -} - bool AObject::hasError() const { return has_error; @@ -546,18 +373,3 @@ bool AObject::getTruncateLinePaths() { return false; } - -void AObject::setModuleForOffset(Offset sym_off, std::string module) { - dyn_c_hash_map>::const_accessor found_syms; - if(!symsByOffset_.find(found_syms, sym_off)) return; - - for(auto s = found_syms->second.begin(); - s != found_syms->second.end(); - ++s) - { - if (!symsToModules_.insert({*s, module})) { - assert(!"symsToModules_.insert({*s, module})"); - } - } -} - diff --git a/symtabAPI/src/Object.h b/symtabAPI/src/Object.h index 1c14da69ba..be67a3e053 100644 --- a/symtabAPI/src/Object.h +++ b/symtabAPI/src/Object.h @@ -42,11 +42,14 @@ ************************************************************************/ // trace data streams +#include +#include #include #include #include "Symbol.h" #include "Symtab.h" +#include "Module.h" #include "LineInformation.h" #include "common/src/headers.h" #include "common/src/MappedFile.h" @@ -98,9 +101,6 @@ class AObject { SYMTAB_EXPORT bool getAllExceptions(std::vector&excpBlocks) const; SYMTAB_EXPORT std::vector getAllRegions() const; - SYMTAB_EXPORT supportedLanguages pickLanguage(std::string &working_module, char *working_options, - supportedLanguages working_lang); - SYMTAB_EXPORT Offset loader_off() const; SYMTAB_EXPORT unsigned loader_len() const; SYMTAB_EXPORT int getAddressWidth() const; @@ -129,9 +129,6 @@ class AObject { Dyninst::SymtabAPI::MemRegReader * /*reader*/) {return false;} SYMTAB_EXPORT virtual Dyninst::Architecture getArch() const { return Arch_none; } - SYMTAB_EXPORT const std::string findModuleForSym(Symbol *sym); - SYMTAB_EXPORT void setModuleForOffset(Offset sym_off, std::string module); - SYMTAB_EXPORT void clearSymsToMods(); SYMTAB_EXPORT bool hasError() const; SYMTAB_EXPORT virtual bool isBigEndianDataEncoding() const { return false; } SYMTAB_EXPORT virtual bool getABIVersion(int & /*major*/, int & /*minor*/) const { return false; } @@ -144,12 +141,13 @@ class AObject { // Only implemented for ELF right now SYMTAB_EXPORT virtual void getSegmentsSymReader(std::vector &) {} SYMTAB_EXPORT virtual void rebase(Offset) {} + virtual void addModule(SymtabAPI::Module *) {} protected: SYMTAB_EXPORT virtual ~AObject(); // explicitly protected SYMTAB_EXPORT AObject(MappedFile *, void (*err_func)(const char *), Symtab*); friend class Module; - virtual void parseLineInfoForCU(Module::DebugInfoT , LineInformation* ) { } + virtual void parseLineInfoForCU(Offset , LineInformation* ) { } MappedFile *mf; @@ -159,7 +157,6 @@ friend class Module; // is reclaimed from this structure dyn_c_hash_map< std::string, std::vector< Symbol *> > symbols_; dyn_hash_map< std::string, std::vector< Symbol *> > symbols_tmp_; - dyn_c_hash_map< Symbol *, std::string > symsToModules_; dyn_c_hash_map > symsByOffset_; std::vector > modules_; diff --git a/symtabAPI/src/Region.C b/symtabAPI/src/Region.C index e3284f3ddc..db5a5a67c5 100644 --- a/symtabAPI/src/Region.C +++ b/symtabAPI/src/Region.C @@ -175,6 +175,7 @@ const char *Region::regionType2Str(RegionType rt) CASE_RETURN_STR(RT_SYMVERNEEDED); CASE_RETURN_STR(RT_REL); CASE_RETURN_STR(RT_RELA); + CASE_RETURN_STR(RT_RELR); CASE_RETURN_STR(RT_PLTREL); CASE_RETURN_STR(RT_PLTRELA); CASE_RETURN_STR(RT_DYNAMIC); diff --git a/symtabAPI/src/Statement.C b/symtabAPI/src/Statement.C new file mode 100644 index 0000000000..b061a51926 --- /dev/null +++ b/symtabAPI/src/Statement.C @@ -0,0 +1,51 @@ +/* + * See the dyninst/COPYRIGHT file for copyright information. + * + * We provide the Paradyn Tools (below described as "Paradyn") + * on an AS IS basis, and do not warrant its validity or performance. + * We reserve the right to update, modify, or discontinue this + * software at any time. We shall have no obligation to supply such + * updates or modifications or any other form of support to you. + * + * By your use of Paradyn, you understand and agree that we (or any + * other person or entity with proprietary rights in Paradyn) are + * under no obligation to provide either maintenance services, + * update services, notices of latent defects, or correction of + * defects for Paradyn. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "Statement.h" + +namespace Dyninst { namespace SymtabAPI { + + StringTablePtr Statement::getStrings_() const { return strings_; } + + void Statement::setStrings_(StringTablePtr strings) { Statement::strings_ = strings; } + + const std::string &Statement::getFile() const { + if (strings_) { + if (file_index_ < strings_->size()) { + // can't be ->[] on shared pointer to multi_index container or compiler gets confused + return (*strings_)[file_index_].str; + } + } + // This string will be pointed to, so it has to persist. + static std::string emptyStr; + return emptyStr; + } + +}} diff --git a/symtabAPI/src/Symbol.C b/symtabAPI/src/Symbol.C index b13bf6484e..e08f1e3a24 100644 --- a/symtabAPI/src/Symbol.C +++ b/symtabAPI/src/Symbol.C @@ -273,10 +273,7 @@ std::ostream& Dyninst::SymtabAPI::operator<< (ostream &os, const Symbol &s) << " }"; } - Offset tryStart_; - unsigned trySize_; - Offset catchStart_; - bool hasTry_; + ostream & Dyninst::SymtabAPI::operator<< (ostream &s, const ExceptionBlock &eb) { @@ -309,7 +306,7 @@ bool Symbol::operator==(const Symbol& s) const if (module_ && !s.module_) return false; if (module_) { - if (module_->fullName() != s.module_->fullName()) + if (module_->fileName() != s.module_->fileName()) return false; } @@ -413,3 +410,59 @@ Symbol* Symbol::getReferringSymbol() const return referring_; } +const char *Symbol::symbolType2Str(SymbolType t) +{ + switch (t) + { + CASE_RETURN_STR(ST_UNKNOWN); + CASE_RETURN_STR(ST_FUNCTION); + CASE_RETURN_STR(ST_OBJECT); + CASE_RETURN_STR(ST_MODULE); + CASE_RETURN_STR(ST_SECTION); + CASE_RETURN_STR(ST_TLS); + CASE_RETURN_STR(ST_DELETED); + CASE_RETURN_STR(ST_NOTYPE); + CASE_RETURN_STR(ST_INDIRECT); + }; + + return "invalid symbol type"; +} + +const char *Symbol::symbolLinkage2Str(SymbolLinkage t) +{ + switch (t) + { + CASE_RETURN_STR(SL_UNKNOWN); + CASE_RETURN_STR(SL_GLOBAL); + CASE_RETURN_STR(SL_LOCAL); + CASE_RETURN_STR(SL_WEAK); + CASE_RETURN_STR(SL_UNIQUE); + }; + + return "invalid symbol linkage"; +} + +const char *Symbol::symbolTag2Str(SymbolTag t) +{ + switch (t) + { + CASE_RETURN_STR(TAG_UNKNOWN); + CASE_RETURN_STR(TAG_USER); + CASE_RETURN_STR(TAG_LIBRARY); + CASE_RETURN_STR(TAG_INTERNAL); + }; + + return "invalid symbol tag"; +} + +const char *Symbol::symbolVisibility2Str(SymbolVisibility t) +{ + switch(t) { + CASE_RETURN_STR(SV_UNKNOWN); + CASE_RETURN_STR(SV_DEFAULT); + CASE_RETURN_STR(SV_INTERNAL); + CASE_RETURN_STR(SV_HIDDEN); + CASE_RETURN_STR(SV_PROTECTED); + } + return "invalid symbol visibility"; +} diff --git a/symtabAPI/src/Symtab-edit.C b/symtabAPI/src/Symtab-edit.C index 32c56db40d..7f6894974d 100644 --- a/symtabAPI/src/Symtab-edit.C +++ b/symtabAPI/src/Symtab-edit.C @@ -43,10 +43,10 @@ #include "Collections.h" #include "Function.h" #include "Variable.h" - +#include "symtab_impl.hpp" #include "symtabAPI/src/Object.h" -#include "boost/tuple/tuple.hpp" +#include "dyncompat/tuple/tuple.hpp" using namespace Dyninst; using namespace Dyninst::SymtabAPI; @@ -109,7 +109,7 @@ bool Symtab::deleteFunction(Function *func) { } } */ - funcsByOffset.erase(func->getOffset()); + impl->funcsByOffset.erase(func->getOffset()); // Now handle the Aggregate stuff return deleteAggregate(func); @@ -121,13 +121,13 @@ bool Symtab::deleteVariable(Variable *var) { // remove variable from varsByOffset { - VarsByOffsetMap::accessor a; - bool found = !varsByOffset.find(a, var->getOffset()); + decltype(impl->varsByOffset)::accessor a; + bool found = !impl->varsByOffset.find(a, var->getOffset()); if (found) { - VarsByOffsetMap::mapped_type &vars = a->second; + decltype(impl->varsByOffset)::mapped_type &vars = a->second; vars.erase(std::remove(vars.begin(), vars.end(), var), vars.end()); if (vars.empty()) { - varsByOffset.erase(a); + impl->varsByOffset.erase(a); } } } @@ -148,14 +148,14 @@ bool Symtab::deleteAggregate(Aggregate *agg) { } bool Symtab::deleteSymbolFromIndices(Symbol *sym) { - everyDefinedSymbol.erase(sym); - undefDynSyms.erase(sym); + impl->everyDefinedSymbol.erase(sym); + impl->undefDynSyms.erase(sym); return true; } bool Symtab::deleteSymbol(Symbol *sym) { - boost::unique_lock l(symbols_rwlock); + dyncompat::unique_lock l(symbols_rwlock); if (sym->aggregate_) { sym->aggregate_->removeSymbol(sym); } @@ -163,60 +163,30 @@ bool Symtab::deleteSymbol(Symbol *sym) return result; } -bool Symtab::changeSymbolOffset(Symbol *sym, Offset newOffset) { - // If we aren't part of an aggregate, change the symbol offset - // and update symsByOffset. - // If we are part of an aggregate and the only symbol element, - // do that and update funcsByOffset or varsByOffset. - // If we are and not the only symbol, do 1), remove from - // the aggregate, and make a new aggregate. - { - indexed_symbols::master_t::accessor a; - if (!everyDefinedSymbol.master.find(a, sym)) { - assert(!"everyDefinedSymbol.master.find(a, sym)"); - } - - indexed_symbols::by_offset_t::accessor oa; - if (!everyDefinedSymbol.by_offset.find(oa, sym->offset_)) { - assert(!"everyDefinedSymbol.by_offset.find(oa, sym->offset_)"); - } - auto &syms = oa->second; - syms.erase(std::remove(syms.begin(), syms.end(), sym), syms.end()); - everyDefinedSymbol.by_offset.insert(oa, newOffset); - oa->second.push_back(sym); - - a->second = newOffset; - sym->offset_ = newOffset; - } - - if (sym->aggregate_ == NULL) return true; - else return sym->aggregate_->changeSymbolOffset(sym); -} - bool Symtab::changeAggregateOffset(Aggregate *agg, Offset oldOffset, Offset newOffset) { Function *func = dynamic_cast(agg); Variable *var = dynamic_cast(agg); if (func) { - funcsByOffset.erase(oldOffset); - if (!funcsByOffset.insert({newOffset, func})) { + impl->funcsByOffset.erase(oldOffset); + if (!impl->funcsByOffset.insert({newOffset, func})) { // Already someone there... odd, so don't do anything. } } if (var) { - VarsByOffsetMap::accessor a; - bool found = !varsByOffset.find(a, oldOffset); - VarsByOffsetMap::mapped_type &vars = a->second; + decltype(impl->varsByOffset)::accessor a; + bool found = !impl->varsByOffset.find(a, oldOffset); + decltype(impl->varsByOffset)::mapped_type &vars = a->second; if (found) { vars.erase(std::remove(vars.begin(), vars.end(), var), vars.end()); if (vars.empty()) { - varsByOffset.erase(a); + impl->varsByOffset.erase(a); } } else { assert(0); } - found = !varsByOffset.insert(a, newOffset); + found = !impl->varsByOffset.insert(a, newOffset); if (found) { found = false; for (auto v: vars) { @@ -244,15 +214,15 @@ bool Symtab::addSymbol(Symbol *newSym, Symbol *referringSymbol) newSym->setReferringSymbol(referringSymbol); string filename = referringSymbol->getModule()->exec()->name(); - vector *vers, *newSymVers = new vector; + vector *vers{}; newSym->setVersionFileName(filename); std::string rstr; newSym->getVersionFileName(rstr); if (referringSymbol->getVersions(vers) && vers != NULL && vers->size() > 0) { - newSymVers->push_back((*vers)[0]); - newSym->setVersions(*newSymVers); + auto newSymVers = std::vector{(*vers)[0]}; + newSym->setVersions(newSymVers); } }else{ newSym->setReferringSymbol(referringSymbol); @@ -307,8 +277,6 @@ Function *Symtab::createFunction(std::string name, mod = getDefaultModule(); } - // Check to see if we contain this module... - if(indexed_modules.get<1>().find(mod) == indexed_modules.get<1>().end()) return NULL; // // bool found = false; // for (unsigned i = 0; i < indexed_modules.size(); i++) { @@ -355,8 +323,7 @@ Variable *Symtab::createVariable(std::string name, if (mod == NULL) { mod = getDefaultModule(); } - // Check to see if we contain this module... - if(indexed_modules.get<1>().find(mod) == indexed_modules.get<1>().end()) return NULL; + // // bool found = false; // for (unsigned i = 0; i < indexed_modules.size(); i++) { diff --git a/symtabAPI/src/Symtab-lookup.C b/symtabAPI/src/Symtab-lookup.C index 0f5d88c3db..5954312581 100644 --- a/symtabAPI/src/Symtab-lookup.C +++ b/symtabAPI/src/Symtab-lookup.C @@ -49,11 +49,11 @@ #include "Function.h" #include "Variable.h" #include "annotations.h" - +#include "symtab_impl.hpp" #include "symtabAPI/src/Object.h" -#include -#include +#include +#include using namespace Dyninst; using namespace Dyninst::SymtabAPI; @@ -66,8 +66,8 @@ bool pattern_match( const char *p, const char *s, bool checkCase ); std::vector Symtab::findSymbolByOffset(Offset o) { - indexed_symbols::by_offset_t::const_accessor oa; - if(everyDefinedSymbol.by_offset.find(oa, o)) + decltype(impl->everyDefinedSymbol)::by_offset_t::const_accessor oa; + if(impl->everyDefinedSymbol.by_offset.find(oa, o)) return oa->second; return std::vector(); } @@ -84,37 +84,37 @@ bool Symtab::findSymbol(std::vector &ret, const std::string& name, // Easy case if (nameType & mangledName) { { - indexed_symbols::by_name_t::const_accessor ma; - if(everyDefinedSymbol.by_mangled.find(ma, name)) + decltype(impl->everyDefinedSymbol)::by_name_t::const_accessor ma; + if(impl->everyDefinedSymbol.by_mangled.find(ma, name)) candidates.insert(candidates.end(), ma->second.begin(), ma->second.end()); } if(includeUndefined) { - indexed_symbols::by_name_t::const_accessor ma; - if(undefDynSyms.by_mangled.find(ma, name)) + decltype(impl->undefDynSyms)::by_name_t::const_accessor ma; + if(impl->undefDynSyms.by_mangled.find(ma, name)) candidates.insert(candidates.end(), ma->second.begin(), ma->second.end()); } } if (nameType & prettyName) { { - indexed_symbols::by_name_t::const_accessor pa; - if(everyDefinedSymbol.by_pretty.find(pa, name)) + decltype(impl->everyDefinedSymbol)::by_name_t::const_accessor pa; + if(impl->everyDefinedSymbol.by_pretty.find(pa, name)) candidates.insert(candidates.end(), pa->second.begin(), pa->second.end()); } if(includeUndefined) { - indexed_symbols::by_name_t::const_accessor pa; - if(undefDynSyms.by_pretty.find(pa, name)) + decltype(impl->undefDynSyms)::by_name_t::const_accessor pa; + if(impl->undefDynSyms.by_pretty.find(pa, name)) candidates.insert(candidates.end(), pa->second.begin(), pa->second.end()); } } if (nameType & typedName) { { - indexed_symbols::by_name_t::const_accessor ta; - if(everyDefinedSymbol.by_typed.find(ta, name)) + decltype(impl->everyDefinedSymbol)::by_name_t::const_accessor ta; + if(impl->everyDefinedSymbol.by_typed.find(ta, name)) candidates.insert(candidates.end(), ta->second.begin(), ta->second.end()); } if(includeUndefined) { - indexed_symbols::by_name_t::const_accessor ta; - if(undefDynSyms.by_typed.find(ta, name)) + decltype(impl->undefDynSyms)::by_name_t::const_accessor ta; + if(impl->undefDynSyms.by_typed.find(ta, name)) candidates.insert(candidates.end(), ta->second.begin(), ta->second.end()); } } @@ -126,7 +126,7 @@ bool Symtab::findSymbol(std::vector &ret, const std::string& name, cerr << "Warning: regex search of undefined symbols is not supported" << endl; } - for (auto i = everyDefinedSymbol.begin(); i != everyDefinedSymbol.end(); i++) { + for (auto i = impl->everyDefinedSymbol.begin(); i != impl->everyDefinedSymbol.end(); i++) { if (nameType & mangledName) { if (regexEquiv(name, (*i)->getMangledName(), checkCase)) candidates.push_back(*i); @@ -169,8 +169,8 @@ bool Symtab::findSymbol(std::vector &ret, const std::string& name, bool Symtab::getAllSymbols(std::vector &ret) { - std::copy(everyDefinedSymbol.begin(), everyDefinedSymbol.end(), back_inserter(ret)); - std::copy(undefDynSyms.begin(), undefDynSyms.end(), back_inserter(ret)); + std::copy(impl->everyDefinedSymbol.begin(), impl->everyDefinedSymbol.end(), back_inserter(ret)); + std::copy(impl->undefDynSyms.begin(), impl->undefDynSyms.end(), back_inserter(ret)); if(ret.size() > 0) { return true; @@ -188,14 +188,14 @@ bool Symtab::getAllSymbolsByType(std::vector &ret, Symbol::SymbolType unsigned old_size = ret.size(); // Filter by the given type - for (auto i = everyDefinedSymbol.begin(); i != everyDefinedSymbol.end(); i++) { + for (auto i = impl->everyDefinedSymbol.begin(); i != impl->everyDefinedSymbol.end(); i++) { if ((*i)->getType() == sType) { ret.push_back(*i); } } - for (auto j = undefDynSyms.begin(); j != undefDynSyms.end(); j++) { + for (auto j = impl->undefDynSyms.begin(); j != impl->undefDynSyms.end(); j++) { if ((*j)->getType() == sType) { ret.push_back(*j); @@ -216,7 +216,7 @@ bool Symtab::getAllDefinedSymbols(std::vector &ret) { ret.clear(); - std::copy(everyDefinedSymbol.begin(), everyDefinedSymbol.end(), back_inserter(ret)); + std::copy(impl->everyDefinedSymbol.begin(), impl->everyDefinedSymbol.end(), back_inserter(ret)); if(ret.size() > 0) return true; @@ -227,7 +227,7 @@ bool Symtab::getAllDefinedSymbols(std::vector &ret) bool Symtab::getAllUndefinedSymbols(std::vector &ret){ unsigned size = ret.size(); - ret.insert(ret.end(), undefDynSyms.begin(), undefDynSyms.end()); + ret.insert(ret.end(), impl->undefDynSyms.begin(), impl->undefDynSyms.end()); if(ret.size()>size) return true; @@ -245,7 +245,7 @@ bool Symtab::findFuncByEntryOffset(Function *&ret, const Offset entry) */ { dyn_c_hash_map::const_accessor ca; - if (funcsByOffset.find(ca, entry)) { + if (impl->funcsByOffset.find(ca, entry)) { ret = ca->second; return true; } @@ -303,8 +303,8 @@ bool Symtab::findVariablesByOffset(std::vector &ret, const Offset of * relocatable files -- this discrepancy applies here as well. */ { - VarsByOffsetMap::const_accessor ca; - if (varsByOffset.find(ca, offset)) { + decltype(impl->varsByOffset)::const_accessor ca; + if (impl->varsByOffset.find(ca, offset)) { ret = ca->second; return true; } @@ -349,67 +349,28 @@ bool Symtab::getAllVariables(std::vector &ret) bool Symtab::getAllModules(std::vector &ret) { - dyn_mutex::unique_lock l(im_lock); - if (indexed_modules.size() >0 ) - { - std::copy(indexed_modules.begin(), indexed_modules.end(), std::back_inserter(ret)); - return true; - } - - return false; + auto const size = ret.size(); + std::copy(impl->modules.begin(), impl->modules.end(), std::back_inserter(ret)); + return ret.size() != size; } bool Symtab::findModuleByOffset(Module *&ret, Offset off) { - dyn_mutex::unique_lock l(im_lock); - std::set mods; - mod_lookup()->find(off, mods); - if(!mods.empty()) - { - ret = (*mods.begin())->id(); - } - return !mods.empty(); + ret = findModuleByOffset(off); + return ret != nullptr; } -bool Symtab::findModuleByOffset(std::set&ret, Offset off) -{ - dyn_mutex::unique_lock l(im_lock); - std::set mods; - ret.clear(); - mod_lookup()->find(off, mods); - for(auto i = mods.begin(); - i != mods.end(); - ++i) - { - ret.insert((*i)->id()); - } - return !ret.empty(); +Module* Symtab::findModuleByOffset(Offset offset) const { + return impl->modules.find(offset); } -bool Symtab::findModuleByName(Module *&ret, const std::string name) -{ - dyn_mutex::unique_lock l(im_lock); - auto loc = indexed_modules.get<3>().find(name); - - if (loc != indexed_modules.get<3>().end()) - { - ret = *(loc); - return true; - } - - std::string tmp = extract_pathname_tail(name); - - auto loc2 = indexed_modules.get<2>().find(tmp); - - if (loc2 != indexed_modules.get<2>().end()) - { - ret = *loc2; - return true; - } +std::vector Symtab::findModulesByName(std::string const& name) const { + return impl->modules.find(name); +} - ret = NULL; - return false; +Module* Symtab::getContainingModule(Offset offset) const { + return impl->getContainingModule(offset); } bool Symtab::getAllRegions(std::vector&ret) @@ -722,14 +683,14 @@ bool Symtab::addFunctionRange(FunctionBase *func, Dyninst::Offset next_start) for (FuncRangeCollection::iterator i = ranges.begin(); i != ranges.end(); i++) { FuncRange &range = *i; if (range.low() == sym_low && range.high() == sym_high) - found_sym_range = true; - func_lookup->insert(&range); + found_sym_range = true; + impl->func_lookup.insert(&range); } //Add symbol range to func_lookup, if present and not already added if (!found_sym_range && sym_low && sym_high) { - FuncRange *frange = new FuncRange(sym_low, sym_high - sym_low, func); - func_lookup->insert(frange); + FuncRange *frange = new FuncRange(sym_low, sym_high - sym_low, func); + impl->func_lookup.insert(frange); } //Recursively add inlined functions @@ -743,8 +704,6 @@ bool Symtab::addFunctionRange(FunctionBase *func, Dyninst::Offset next_start) bool Symtab::parseFunctionRanges() { parseTypesNow(); - assert(!func_lookup); - func_lookup = new FuncRangeLookup(); if (everyFunction.size() && !sorted_everyFunction) { @@ -781,12 +740,9 @@ bool Symtab::getContainingFunction(Offset offset, Function* &func) if (!isCode(offset)) { return false; } - if (everyFunction.size() && !sorted_everyFunction) - { - std::sort(everyFunction.begin(), everyFunction.end(), - SymbolCompareByAddr()); - sorted_everyFunction = true; - } + + // Lazily parse the function ranges, but ensure we only do it once. + std::call_once(impl->funcRangesAreParsed, [this](){ this->parseFunctionRanges(); }); unsigned low = 0; unsigned high = everyFunction.size(); @@ -825,13 +781,12 @@ bool Symtab::getContainingFunction(Offset offset, Function* &func) } bool Symtab::getContainingInlinedFunction(Offset offset, FunctionBase* &func) -{ - if (!func_lookup) - parseFunctionRanges(); - assert(func_lookup); +{ + // Lazily parse the function ranges, but ensure we only do it once. + std::call_once(impl->funcRangesAreParsed, [this](){ this->parseFunctionRanges(); }); set ranges; - int num_found = func_lookup->find(offset, ranges); + int num_found = impl->func_lookup.find(offset, ranges); if (num_found == 0) { func = NULL; return false; @@ -851,7 +806,7 @@ bool Symtab::getContainingInlinedFunction(Offset offset, FunctionBase* &func) // Therefore, here we heuristicaly prefer the deeper call chain // to reflect inlining information. int maxDepth = 0; - for (auto range : ranges) { + for (auto range : ranges) { FunctionBase *cur_func = range->container; int depth = 0; while (cur_func) { @@ -862,14 +817,12 @@ bool Symtab::getContainingInlinedFunction(Offset offset, FunctionBase* &func) maxDepth = depth; func = range->container; } - } + } return true; } -Module *Symtab::getDefaultModule() { - dyn_mutex::unique_lock l(im_lock); - if(indexed_modules.empty()) createDefaultModule(); - return indexed_modules[0]; +Module *Symtab::getDefaultModule() const { + return impl->default_module; } unsigned Function::getSymbolSize() const { diff --git a/symtabAPI/src/Symtab.C b/symtabAPI/src/Symtab.C index a0a90a558d..9116eddcea 100644 --- a/symtabAPI/src/Symtab.C +++ b/symtabAPI/src/Symtab.C @@ -46,12 +46,13 @@ #include "Collections.h" #include "Function.h" #include "Variable.h" - +#include "pathName.h" #include "annotations.h" #include "debug.h" #include "symtabAPI/src/Object.h" +#include "symtab_impl.hpp" #if !defined(os_windows) @@ -69,7 +70,7 @@ using namespace Dyninst; using namespace Dyninst::SymtabAPI; using namespace std; -static std::string errMsg; +static thread_local std::string errMsg; static const int Symtab_major_version = DYNINST_MAJOR_VERSION; static const int Symtab_minor_version = DYNINST_MINOR_VERSION; @@ -141,41 +142,40 @@ std::string Symtab::printError(SymtabError e) } } -static LazySingleton> ls_type_Error; -boost::shared_ptr& Symtab::type_Error() +static LazySingleton> ls_type_Error; +dyncompat::shared_ptr& Symtab::type_Error() { return ls_type_Error.get([](){ return Type::make_shared(std::string("> ls_type_Untyped; -boost::shared_ptr& Symtab::type_Untyped() +static LazySingleton> ls_type_Untyped; +dyncompat::shared_ptr& Symtab::type_Untyped() { return ls_type_Untyped.get([](){ return Type::make_shared(std::string(""), 0, dataUnknownType); }); } -static LazySingleton> ls_builtInTypes; -boost::shared_ptr& Symtab::builtInTypes() +static LazySingleton> ls_builtInTypes; +dyncompat::shared_ptr& Symtab::builtInTypes() { return ls_builtInTypes.get(setupBuiltinTypes); } -static LazySingleton> ls_stdTypes; -boost::shared_ptr& Symtab::stdTypes() +static LazySingleton> ls_stdTypes; +dyncompat::shared_ptr& Symtab::stdTypes() { return ls_stdTypes.get(setupStdTypes); } -boost::shared_ptr Symtab::setupBuiltinTypes() +dyncompat::shared_ptr Symtab::setupBuiltinTypes() { - boost::shared_ptr builtInTypes = - boost::shared_ptr(new builtInTypeCollection); + dyncompat::shared_ptr builtInTypes = + dyncompat::shared_ptr(new builtInTypeCollection); // NOTE: integral type mean twos-complement // -1 int, 32 bit signed integral type - // in stab document, size specified in bits, system size is in bytes builtInTypes->addBuiltInType(Type::make_shared(-1, 4, "int", true)); // -2 char, 8 bit type holding a character. GDB treats as signed builtInTypes->addBuiltInType(Type::make_shared(-2, 1, "char", true)); @@ -267,10 +267,10 @@ boost::shared_ptr Symtab::setupBuiltinTypes() } -boost::shared_ptr Symtab::setupStdTypes() +dyncompat::shared_ptr Symtab::setupStdTypes() { - boost::shared_ptr stdTypes = - boost::shared_ptr(new typeCollection); + dyncompat::shared_ptr stdTypes = + dyncompat::shared_ptr(new typeCollection); stdTypes->addType(Type::make_shared(-1, sizeof(int), "int")); auto charType = Type::make_shared(-2, sizeof(char), "char"); @@ -304,70 +304,12 @@ SYMTAB_EXPORT bool Symtab::isBigEndianDataEncoding() const return obj_private->isBigEndianDataEncoding(); } -SYMTAB_EXPORT Symtab::Symtab(MappedFile *mf_) : - AnnotatableSparse(), - member_offset_(0), - parentArchive_(NULL), - mf(mf_), mfForDebugInfo(NULL), - imageOffset_(0), imageLen_(0), - dataOffset_(0), dataLen_(0), - is_a_out(false), - main_call_addr_(0), - address_width_(sizeof(int)), - code_ptr_(NULL), data_ptr_(NULL), - entry_address_(0), base_address_(0), load_address_(0), - object_type_(obj_Unknown), is_eel_(false), - no_of_sections(0), - newSectionInsertPoint(0), - no_of_symbols(0), - sorted_everyFunction(false), - isTypeInfoValid_(false), - nlines_(0), fdptr_(0), lines_(NULL), - stabstr_(NULL), nstabs_(0), stabs_(NULL), - stringpool_(NULL), - hasRel_(false), hasRela_(false), hasReldyn_(false), - hasReladyn_(false), hasRelplt_(false), hasRelaplt_(false), - isStaticBinary_(false), isDefensiveBinary_(false), - func_lookup(NULL), - mod_lookup_(NULL), - obj_private(NULL), - _ref_cnt(1) -{ - init_debug_symtabAPI(); -} - SYMTAB_EXPORT Symtab::Symtab() : LookupInterface(), AnnotatableSparse(), - member_offset_(0), - parentArchive_(NULL), - mf(NULL), mfForDebugInfo(NULL), - imageOffset_(0), imageLen_(0), - dataOffset_(0), dataLen_(0), - is_a_out(false), - main_call_addr_(0), - address_width_(sizeof(int)), - code_ptr_(NULL), data_ptr_(NULL), - entry_address_(0), base_address_(0), load_address_(0), - object_type_(obj_Unknown), is_eel_(false), - no_of_sections(0), - newSectionInsertPoint(0), - no_of_symbols(0), - sorted_everyFunction(false), - isTypeInfoValid_(false), - nlines_(0), fdptr_(0), lines_(NULL), - stabstr_(NULL), nstabs_(0), stabs_(NULL), - stringpool_(NULL), - hasRel_(false), hasRela_(false), hasReldyn_(false), - hasReladyn_(false), hasRelplt_(false), hasRelaplt_(false), - isStaticBinary_(false), isDefensiveBinary_(false), - func_lookup(NULL), - mod_lookup_(NULL), - obj_private(NULL), - _ref_cnt(1) + impl{std::unique_ptr(new symtab_impl{})} { init_debug_symtabAPI(); - create_printf("%s[%d]: Created symtab via default constructor\n", FILE__, __LINE__); } SYMTAB_EXPORT bool Symtab::isExec() const @@ -433,17 +375,6 @@ SYMTAB_EXPORT void Symtab::fixup_code_and_data(Offset newImageOffset, // Should we update the underlying Object? } -/* -SYMTAB_EXPORT char* Symtab::image_ptr () const -{ - return code_ptr_; -} - -SYMTAB_EXPORT char* Symtab::data_ptr () const -{ - return data_ptr_; -} -*/ SYMTAB_EXPORT const char* Symtab::getInterpreterName() const { if (interpreter_name_.length()) @@ -486,78 +417,6 @@ SYMTAB_EXPORT string Symtab::getDefaultNamespacePrefix() const return defaultNamespacePrefix; } -// Operations on the indexed_symbols compound table. -bool Symtab::indexed_symbols::insert(Symbol* s) { - Offset o = s->getOffset(); - master_t::accessor a; - if(master.insert(a, std::make_pair(s, o))) { - { - by_offset_t::accessor oa; - by_offset.insert(oa, o); - oa->second.push_back(s); - } - { - by_name_t::accessor ma; - by_mangled.insert(ma, s->getMangledName()); - ma->second.push_back(s); - } - { - by_name_t::accessor pa; - by_pretty.insert(pa, s->getPrettyName()); - pa->second.push_back(s); - } - { - by_name_t::accessor ta; - by_typed.insert(ta, s->getTypedName()); - ta->second.push_back(s); - } - - return true; - } - return false; -} - -void Symtab::indexed_symbols::clear() { - master.clear(); - by_offset.clear(); - by_mangled.clear(); - by_pretty.clear(); - by_typed.clear(); -} - -void Symtab::indexed_symbols::erase(Symbol* s) { - if(master.erase(s)) { - { - by_offset_t::accessor oa; - if (!by_offset.find(oa, s->getOffset())) { - assert(!"by_offset.find(oa, s->getOffset())"); - } - std::remove(oa->second.begin(), oa->second.end(), s); - } - { - by_name_t::accessor ma; - if (!by_mangled.find(ma, s->getMangledName())) { - assert(!"by_mangled.find(ma, s->getMangledName())"); - } - std::remove(ma->second.begin(), ma->second.end(), s); - } - { - by_name_t::accessor pa; - if (!by_pretty.find(pa, s->getPrettyName())) { - assert(!"by_pretty.find(pa, s->getPrettyName())"); - } - std::remove(pa->second.begin(), pa->second.end(), s); - } - { - by_name_t::accessor ta; - if (!by_typed.find(ta, s->getTypedName())) { - assert(!"by_typed.find(ta, s->getTypedName())"); - } - std::remove(ta->second.begin(), ta->second.end(), s); - } - } -} - /* * extractSymbolsFromFile @@ -592,7 +451,7 @@ bool Symtab::extractSymbolsFromFile(Object *linkedFile, std::vector &r // relocation entries have references to these undefined dynamic symbols. // We also have undefined symbols for the static binary case. if (sym->getRegion() == NULL && !sym->isAbsolute() && !sym->isCommonStorage()) { - undefDynSyms.insert(sym); + impl->undefDynSyms.insert(sym); continue; } @@ -634,9 +493,9 @@ bool Symtab::fixSymModules(std::vector &raw_syms) if (!obj) { return false; } - for (auto i = indexed_modules.begin(); i != indexed_modules.end(); ++i) - { - (*i)->finalizeRanges(); + + if(!impl->default_module) { + createDefaultModule(); } // const std::vector > &mods = obj->modules_; @@ -676,7 +535,7 @@ bool Symtab::createIndices(std::vector &raw_syms, bool undefined) { bool Symtab::createAggregates() { - std::vector syms(everyDefinedSymbol.begin(), everyDefinedSymbol.end()); + std::vector syms(impl->everyDefinedSymbol.begin(), impl->everyDefinedSymbol.end()); #pragma omp parallel for for(size_t i = 0; i < syms.size(); ++i) @@ -690,8 +549,7 @@ bool Symtab::createAggregates() bool Symtab::fixSymModule(Symbol *&sym) { - Module* mod = NULL; - findModuleByOffset(mod, sym->getOffset()); + Module* mod = getContainingModule(sym->getOffset()); if(!mod) mod = getDefaultModule(); sym->setModule(mod); return true; @@ -702,11 +560,11 @@ bool Symtab::addSymbolToIndices(Symbol *&sym, bool undefined) { assert(sym); if (!undefined) { - everyDefinedSymbol.insert(sym); + impl->everyDefinedSymbol.insert(sym); } else { // multi-index container should handle duplication - undefDynSyms.insert(sym); + impl->undefDynSyms.insert(sym); } return true; @@ -724,21 +582,29 @@ bool Symtab::addSymbolToAggregates(const Symbol *sym_tmp) // If no function exists, create and add. // Combine this information // Add this symbol's names to the function. - // Keep module information + // Keep module information + + auto add_func = [this](Function *f) { + dyncompat::unique_lock l(symbols_rwlock); + everyFunction.push_back(f); + sorted_everyFunction = false; + }; Function *func = NULL; bool found = false; { dyn_c_hash_map::accessor a; - found = !funcsByOffset.insert(a, sym->getOffset()); - if(found) func = a->second; - else { - // Create a new function - // Also, update the symbol to point to this function. - func = new Function(sym); + found = !impl->funcsByOffset.insert(a, sym->getOffset()); + if(found){ + func = a->second; + } else { + // Create a new function + // Also, update the symbol to point to this function. + func = new Function(sym); a->second = func; + } } - } // Release the lock on the offset/function pair + if(found) { /* XXX * For relocatable files, the offset of a symbol is relative to the @@ -751,16 +617,16 @@ bool Symtab::addSymbolToAggregates(const Symbol *sym_tmp) if( func->getRegion() != sym->getRegion() ) { func = new Function(sym); - boost::unique_lock l(symbols_rwlock); - everyFunction.push_back(func); - sorted_everyFunction = false; + add_func(func); + } else { + // The function has an additional name + // e.g., two symbols aliasing the same code location + func->addSymbol(sym); } - func->addSymbol(sym); } else { - boost::unique_lock l(symbols_rwlock); - everyFunction.push_back(func); - sorted_everyFunction = false; + add_func(func); } + sym->setFunction(func); break; @@ -771,9 +637,9 @@ bool Symtab::addSymbolToAggregates(const Symbol *sym_tmp) Variable *var = NULL; bool found = false; { - VarsByOffsetMap::accessor a; - found = !varsByOffset.insert(a, sym->getOffset()); - VarsByOffsetMap::mapped_type &vars = a->second; + decltype(impl->varsByOffset)::accessor a; + found = !impl->varsByOffset.insert(a, sym->getOffset()); + decltype(impl->varsByOffset)::mapped_type &vars = a->second; if (found) { found = false; for (auto v: vars) { @@ -805,13 +671,13 @@ bool Symtab::addSymbolToAggregates(const Symbol *sym_tmp) NULL == sym->getRegion() ) ) { var = new Variable(sym); - boost::unique_lock l(symbols_rwlock); + dyncompat::unique_lock l(symbols_rwlock); everyVariable.push_back(var); }else{ var->addSymbol(sym); } } else { - boost::unique_lock l(symbols_rwlock); + dyncompat::unique_lock l(symbols_rwlock); everyVariable.push_back(var); } sym->setVariable(var); @@ -861,70 +727,6 @@ bool Symtab::doNotAggregate(const Symbol* sym) { return false; } -/* Add the new name to the appropriate symbol index */ - -bool Symtab::updateIndices(Symbol * /*sym*/, std::string /*newName*/, NameType /*nameType*/) { - -#if 0 - if (nameType & mangledName) { - // Add this symbol under the given name (as mangled) - symsByMangledName[newName].push_back(sym); - } - if (nameType & prettyName) { - // Add this symbol under the given name (as pretty) - symsByPrettyName[newName].push_back(sym); - } - if (nameType & typedName) { - // Add this symbol under the given name (as typed) - symsByTypedName[newName].push_back(sym); - } -#endif - return true; -} - -#if 0 -/* checkPPC64DescriptorSymbols() is no longer needed. 3-word descriptor - * symbols are properly taken care of during symbol parsing. See - * parse_symbols() in Object-elf.C for details. - */ - -#if defined(ppc64_linux) -/* Special case for ppc64 ELF binaries. Sometimes a function has a 3-byte descriptor symbol - * along with it in the symbol table and "." preceding its original pretty name for the correct - * function symbol. This checks to see if we have a corresponding 3-byte descriptor symbol existing - * and if it does we remove the preceding "." from the name of the symbol - */ - -void Symtab::checkPPC64DescriptorSymbols(Object *linkedFile) -{ - // find the real functions -- those with the correct type in the symbol table - for(SymbolIter symIter(*linkedFile); symIter;symIter++) - { - Symbol *lookUp = symIter.currval(); - const char *np = lookUp->getMangledName().c_str(); - if(!np) - continue; - - if(np[0] == '.' && (lookUp->getType() == Symbol::ST_FUNCTION)) - { - std::vectorsyms; - std::string newName = np+1; - if(linkedFile->get_symbols(newName, syms) && (syms[0]->getSize() == 24 || syms[0]->getSize() == 0)) - { - //Remove the "." from the name - lookUp->mangledNames[0] = newName; - - //Change the type of the descriptor symbol - syms[0]->type_ = Symbol::ST_NOTYPE; - } - } - } - -} - -#endif -#endif - // setModuleLanguages is only called after modules have been defined. // it attempts to set each module's language, information which is needed // before names can be demangled. @@ -932,13 +734,11 @@ void Symtab::setModuleLanguages(dyn_hash_map *m { if (!mod_langs->size()) return; // cannot do anything here - // this case will arise on non-stabs platforms until language parsing can be introduced at this level - Module *currmod = NULL; + // this case will arise until language parsing can be introduced at this level //int dump = 0; - for (auto i = indexed_modules.begin(); i != indexed_modules.end(); ++i) + for (auto *currmod : impl->modules) { - currmod = (*i); supportedLanguages currLang; if (currmod->isShared()) { continue; // need to find some way to get shared object languages? @@ -973,129 +773,42 @@ void Symtab::setModuleLanguages(dyn_hash_map *m } void Symtab::createDefaultModule() { - assert(indexed_modules.empty()); Module *mod = new Module(lang_Unknown, imageOffset_, - name(), + file(), this); mod->addRange(imageOffset_, imageLen_ + imageOffset_); - indexed_modules.push_back(mod); - mod->finalizeRanges(); + impl->default_module = mod; + addModule(mod); } - +void Symtab::addModule(Module *mod) { + impl->modules.insert(mod); + for(auto *m : mod->finalizeRanges()) { + impl->mod_lookup_.insert(m); + } +} Module *Symtab::getOrCreateModule(const std::string &modName, const Offset modAddr) { - if(indexed_modules.empty()) { - createDefaultModule(); - } - std::string nameToUse; - if (modName.length() > 0) - nameToUse = modName; - else - nameToUse = "DEFAULT_MODULE"; + Module *fm = getContainingModule(modAddr); - Module *fm = NULL; - if (findModuleByName(fm, nameToUse)) - { - if(modAddr && (modAddr < fm->addr())) - { - fm->addr_ = modAddr; - } - return fm; - } + if (fm) return fm; - const char *str = nameToUse.c_str(); - int len = nameToUse.length(); - assert(len>0); + create_printf("%s[%d]: Module '%s' at location 0x'%zx' not found. Creating new module.\n", + FILE__, __LINE__, modName.c_str(), modAddr); - // TODO ignore directory definitions for now - if (str[len-1] == '/') - return NULL; + Module *mod = new Module(lang_Unknown, modAddr, modName, this); + addModule(mod); - return (newModule(nameToUse, modAddr, lang_Unknown)); + return mod; } - -Module *Symtab::newModule(const std::string &name, const Offset addr, supportedLanguages lang) -{ - Module *ret = NULL; - // modules can be defined several times in C++ due to templates and - // in-line member functions. - if (findModuleByName(ret, name)) - { - return(ret); - } - - //parsing_printf("=== image, creating new pdmodule %s, addr 0x%x\n", - // name.c_str(), addr); - - std::string fileNm, fullNm; - fullNm = name; - fileNm = extract_pathname_tail(name); - - create_printf("%s[%d]: In %p: Creating new module '%s'/'%s'\n", FILE__, __LINE__, (void*)this, fileNm.c_str(), fullNm.c_str()); - - ret = new Module(lang, addr, fullNm, this); - assert(ret); - - /* - * FIXME - * - * There are cases where the fileName can be the same, but the full name is - * different and the modules are actually different. This is an inherent - * problem with how modules are processed. - */ - if (indexed_modules.get<2>().end() != indexed_modules.get<2>().find(ret->fileName())) - { - create_printf("%s[%d]: WARN: LEAK? already have module with name %s\n", - FILE__, __LINE__, ret->fileName().c_str()); - } - - if (indexed_modules.get<3>().end() != indexed_modules.get<3>().find(ret->fullName())) - { - create_printf("%s[%d]: WARN: LEAK? already have module with name %s\n", - FILE__, __LINE__, ret->fullName().c_str()); - } - - indexed_modules.push_back(ret); - - return (ret); -} +Symtab::Symtab(std::string filename, bool defensive_bin, bool &err) : Symtab() +{ + isDefensiveBinary_ = defensive_bin; -Symtab::Symtab(std::string filename, bool defensive_bin, bool &err) : - LookupInterface(), - AnnotatableSparse(), - member_offset_(0), - parentArchive_(NULL), - mf(NULL), mfForDebugInfo(NULL), - imageOffset_(0), imageLen_(0), - dataOffset_(0), dataLen_(0), - is_a_out(false), - main_call_addr_(0), - address_width_(sizeof(int)), - code_ptr_(NULL), data_ptr_(NULL), - entry_address_(0), base_address_(0), load_address_(0), - object_type_(obj_Unknown), is_eel_(false), - no_of_sections(0), - newSectionInsertPoint(0), - no_of_symbols(0), - sorted_everyFunction(false), - isTypeInfoValid_(false), - nlines_(0), fdptr_(0), lines_(NULL), - stabstr_(NULL), nstabs_(0), stabs_(NULL), - stringpool_(NULL), - hasRel_(false), hasRela_(false), hasReldyn_(false), - hasReladyn_(false), hasRelplt_(false), hasRelaplt_(false), - isStaticBinary_(false), isDefensiveBinary_(defensive_bin), - func_lookup(NULL), - mod_lookup_(NULL), - obj_private(NULL), - _ref_cnt(1) -{ - init_debug_symtabAPI(); // Initialize error parameter err = false; @@ -1138,37 +851,9 @@ Symtab::Symtab(std::string filename, bool defensive_bin, bool &err) : } Symtab::Symtab(unsigned char *mem_image, size_t image_size, - const std::string &name, bool defensive_bin, bool &err) : - LookupInterface(), - AnnotatableSparse(), - member_offset_(0), - parentArchive_(NULL), - mf(NULL), mfForDebugInfo(NULL), - imageOffset_(0), imageLen_(0), - dataOffset_(0), dataLen_(0), - is_a_out(false), - main_call_addr_(0), - address_width_(sizeof(int)), - code_ptr_(NULL), data_ptr_(NULL), - entry_address_(0), base_address_(0), load_address_(0), - object_type_(obj_Unknown), is_eel_(false), - no_of_sections(0), - newSectionInsertPoint(0), - no_of_symbols(0), - sorted_everyFunction(false), - isTypeInfoValid_(false), - nlines_(0), fdptr_(0), lines_(NULL), - stabstr_(NULL), nstabs_(0), stabs_(NULL), - stringpool_(NULL), - hasRel_(false), hasRela_(false), hasReldyn_(false), - hasReladyn_(false), hasRelplt_(false), hasRelaplt_(false), - isStaticBinary_(false), - isDefensiveBinary_(defensive_bin), - func_lookup(NULL), - mod_lookup_(NULL), - obj_private(NULL), - _ref_cnt(1) + const std::string &name, bool defensive_bin, bool &err) : Symtab() { + isDefensiveBinary_ = defensive_bin; // Initialize error parameter err = false; @@ -1211,9 +896,6 @@ bool sort_reg_by_addr(const Region* a, const Region* b) return a->getMemOffset() < b->getMemOffset(); } -extern void print_symbols( std::vector< Symbol *>& allsymbols ); -extern void print_symbol_map( dyn_hash_map< std::string, std::vector< Symbol *> > *symbols); - static bool ExceptionBlockCmp(ExceptionBlock *a, ExceptionBlock *b) { return a->catchStart() < b->catchStart(); } @@ -1331,8 +1013,6 @@ bool Symtab::extractInfo(Object *linkedFile) /* insert error check here. check if parsed */ address_width_ = linkedFile->getAddressWidth(); is_a_out = linkedFile->is_aout(); - code_ptr_ = linkedFile->code_ptr(); - data_ptr_ = linkedFile->data_ptr(); if (linkedFile->interpreter_name()) interpreter_name_ = std::string(linkedFile->interpreter_name()); @@ -1350,11 +1030,6 @@ bool Symtab::extractInfo(Object *linkedFile) // a vector to hold all created symbols until they are properly classified std::vector raw_syms; -#ifdef BINEDIT_DEBUG - printf("== from linkedFile...\n"); - print_symbol_map(linkedFile->getAllSymbols()); -#endif - if (!extractSymbolsFromFile(linkedFile, raw_syms)) { setSymtabError(Syms_To_Functions); @@ -1366,12 +1041,6 @@ bool Symtab::extractInfo(Object *linkedFile) setSymtabError(Syms_To_Functions); return false; } - Object *obj = getObject(); - if (!obj) - { - return false; - } - obj->clearSymsToMods(); // wait until all modules are defined before applying languages to // them we want to do it this way so that module information comes @@ -1420,73 +1089,6 @@ bool Symtab::extractInfo(Object *linkedFile) return true; } -Symtab::Symtab(const Symtab& obj) : - LookupInterface(), - AnnotatableSparse(), - member_name_(obj.member_name_), - member_offset_(obj.member_offset_), - parentArchive_(NULL), - mf(NULL), mfForDebugInfo(NULL), - imageOffset_(obj.imageOffset_), imageLen_(obj.imageLen_), - dataOffset_(obj.dataOffset_), dataLen_(obj.dataLen_), - is_a_out(obj.is_a_out), - main_call_addr_(obj.main_call_addr_), - address_width_(sizeof(int)), - code_ptr_(NULL), data_ptr_(NULL), - entry_address_(0), base_address_(0), load_address_(0), - object_type_(obj_Unknown), is_eel_(false), - defaultNamespacePrefix(obj.defaultNamespacePrefix), - no_of_sections(0), - newSectionInsertPoint(0), - no_of_symbols(obj.no_of_symbols), - sorted_everyFunction(false), - isTypeInfoValid_(obj.isTypeInfoValid_), - nlines_(0), fdptr_(0), lines_(NULL), - stabstr_(NULL), nstabs_(0), stabs_(NULL), - stringpool_(NULL), - hasRel_(false), hasRela_(false), hasReldyn_(false), - hasReladyn_(false), hasRelplt_(false), hasRelaplt_(false), - isStaticBinary_(false), isDefensiveBinary_(obj.isDefensiveBinary_), - func_lookup(NULL), - mod_lookup_(NULL), - obj_private(NULL), - _ref_cnt(1) -{ - create_printf("%s[%d]: Creating symtab 0x%p from symtab 0x%p\n", FILE__, __LINE__, (const void*)this, (const void*)&obj); - - unsigned i; - - for (i=0;isetSymtab(this); - } - - for (i=0;igetMemOffset()] = regions_[i]; - - // TODO FIXME: copying symbols/Functions/Variables - // (and perhaps anything else initialized zero above) - - - for (i=0;i &fbt return true; } +SYMTAB_EXPORT bool Symtab::findPltEntryByTarget(const Address target_address, relocationEntry &result) const +{ + /** + * Object files and static binaries will not have a function binding table + * because the function binding table holds relocations used by the dynamic + * linker + */ + if(relocation_table_.empty() && !isStaticBinary() && + getObjectType() != obj_RelocatableFile) + { + fprintf(stderr, "%s[%d]: WARN: zero func bindings\n", FILE__, __LINE__); + } + + auto it = std::find_if(relocation_table_.cbegin(), relocation_table_.cend(), + [=](const relocationEntry& entry) { + return entry.target_addr() == target_address; + }); + if(it == relocation_table_.cend()) + return false; + + result = *it; + return true; +} + SYMTAB_EXPORT bool Symtab::updateFuncBindingTable(Offset stub_addr, Offset plt_addr) { int stub_idx = -1, plt_idx = -1; @@ -1638,8 +1264,8 @@ Symtab::~Symtab() } // Symbols are copied from linkedFile, and NOT deleted - everyDefinedSymbol.clear(); - undefDynSyms.clear(); + impl->everyDefinedSymbol.clear(); + impl->undefDynSyms.clear(); for (unsigned i = 0; i < everyFunction.size(); i++) @@ -1648,7 +1274,7 @@ Symtab::~Symtab() } everyFunction.clear(); - funcsByOffset.clear(); + impl->funcsByOffset.clear(); for (unsigned i = 0; i < everyVariable.size(); i++) { @@ -1656,13 +1282,12 @@ Symtab::~Symtab() } everyVariable.clear(); - varsByOffset.clear(); + impl->varsByOffset.clear(); - for (auto i = indexed_modules.begin(); i != indexed_modules.end(); ++i) + for (auto *m : impl->modules) { - delete (*i); + delete m; } - indexed_modules.clear(); for (unsigned i=0;i &ranges, parseLineInformation(); /* Iteratate over the modules, looking for ranges in each. */ - for (auto i = indexed_modules.begin(); i != indexed_modules.end(); ++i) + for (auto *m : impl->modules) { - StringTablePtr s = (*i)->getStrings(); - boost::unique_lock l(s->lock); + StringTablePtr s = m->getStrings(); + dyncompat::unique_lock l(s->lock); // Only check modules that have this filename present - if(s->get<1>().find(lineSource) == s->get<1>().end()) { + if(!s->contains(lineSource)) { continue; } - LineInformation *lineInformation = (*i)->parseLineInformation(); + LineInformation *lineInformation = m->parseLineInformation(); if (lineInformation) { lineInformation->getAddressRanges( lineSource.c_str(), lineNo, ranges ); } @@ -1967,14 +1574,11 @@ SYMTAB_EXPORT bool Symtab::getAddressRanges(std::vector &ranges, SYMTAB_EXPORT bool Symtab::getSourceLines(std::vector &lines, Offset addressInRange) { unsigned int originalSize = lines.size(); - std::set mods_for_offset; - findModuleByOffset(mods_for_offset, addressInRange); - for(auto i = mods_for_offset.begin(); - i != mods_for_offset.end(); - ++i) - { - (*i)->getSourceLines(lines, addressInRange); - } + Module* m = getContainingModule(addressInRange); + + if(!m) return false; + + m->getSourceLines(lines, addressInRange); if ( lines.size() != originalSize ) return true; @@ -1995,55 +1599,6 @@ SYMTAB_EXPORT bool Symtab::getSourceLines(std::vector &lines, Offse return true; } -SYMTAB_EXPORT bool Symtab::addLine(std::string lineSource, unsigned int lineNo, - unsigned int lineOffset, Offset lowInclAddr, - Offset highExclAddr) -{ - Module *mod; - - if (!findModuleByName(mod, lineSource)) - { - std::string fileNm = extract_pathname_tail(lineSource); - - if (!findModuleByName(mod, fileNm)) - { - if (!findModuleByName(mod, mf->pathname())) - return false; - } - } - - LineInformation *lineInfo = mod->getLineInformation(); - - if (!lineInfo) - return false; - - return (lineInfo->addLine(lineSource.c_str(), lineNo, lineOffset, - lowInclAddr, highExclAddr)); -} - -SYMTAB_EXPORT bool Symtab::addAddressRange( Offset lowInclusiveAddr, Offset highExclusiveAddr, - std::string lineSource, unsigned int lineNo, - unsigned int lineOffset) -{ - Module *mod; - - if (!findModuleByName(mod, lineSource)) - { - std::string fileNm = extract_pathname_tail(lineSource); - - if (!findModuleByName(mod, fileNm)) - return false; - } - - LineInformation *lineInfo = mod->getLineInformation(); - - if (!lineInfo) - return false; - - return (lineInfo->addAddressRange(lowInclusiveAddr, highExclusiveAddr, - lineSource.c_str(), lineNo, lineOffset)); -} - void Symtab::setTruncateLinePaths(bool value) { getObject()->setTruncateLinePaths(value); @@ -2063,10 +1618,12 @@ void Symtab::parseTypes() } linkedFile->parseTypeInfo(); - for (auto i = indexed_modules.begin(); i != indexed_modules.end(); ++i) + for (auto *m : impl->modules) { - (*i)->setModuleTypes(typeCollection::getModTypeCollection((*i))); - (*i)->finalizeRanges(); + m->setModuleTypes(typeCollection::getModTypeCollection(m)); + for(auto *mr : m->finalizeRanges()) { + impl->mod_lookup_.insert(mr); + } } // optionally we might want to clear the static data struct in typeCollection @@ -2086,26 +1643,26 @@ bool Symtab::addType(Type *type) return true; } -SYMTAB_EXPORT void Symtab::getAllstdTypes(vector>& v) +SYMTAB_EXPORT void Symtab::getAllstdTypes(vector>& v) { return stdTypes()->getAllTypes(v); } -SYMTAB_EXPORT void Symtab::getAllbuiltInTypes(vector>& v) +SYMTAB_EXPORT void Symtab::getAllbuiltInTypes(vector>& v) { return builtInTypes()->getAllBuiltInTypes(v); } -SYMTAB_EXPORT bool Symtab::findType(boost::shared_ptr &type, std::string name) +SYMTAB_EXPORT bool Symtab::findType(dyncompat::shared_ptr &type, std::string name) { parseTypesNow(); - if (indexed_modules.empty()) + if (impl->modules.empty()) return false; - for (auto i = indexed_modules.begin(); i != indexed_modules.end(); ++i) + for (auto *m : impl->modules) { - typeCollection *tc = (*i)->getModuleTypes(); + typeCollection *tc = m->getModuleTypes(); if (!tc) continue; type = tc->findType(name, Type::share); if (type) return true; @@ -2117,19 +1674,19 @@ SYMTAB_EXPORT bool Symtab::findType(boost::shared_ptr &type, std::string n return true; } -SYMTAB_EXPORT boost::shared_ptr Symtab::findType(unsigned type_id, Type::do_share_t) +SYMTAB_EXPORT dyncompat::shared_ptr Symtab::findType(unsigned type_id, Type::do_share_t) { - boost::shared_ptr t; + dyncompat::shared_ptr t; parseTypesNow(); - if (indexed_modules.empty()) + if (impl->modules.empty()) { return NULL; } - for (auto i = indexed_modules.begin(); i != indexed_modules.end(); ++i) + for (auto *m : impl->modules) { - typeCollection *tc = (*i)->getModuleTypes(); + typeCollection *tc = m->getModuleTypes(); if (!tc) continue; t = tc->findType(type_id, Type::share); if (t) break; @@ -2155,13 +1712,13 @@ SYMTAB_EXPORT boost::shared_ptr Symtab::findType(unsigned type_id, Type::d return t; } -SYMTAB_EXPORT bool Symtab::findVariableType(boost::shared_ptr& type, std::string name) +SYMTAB_EXPORT bool Symtab::findVariableType(dyncompat::shared_ptr& type, std::string name) { parseTypesNow(); type = NULL; - for (auto i = indexed_modules.begin(); i != indexed_modules.end(); ++i) + for (auto *m : impl->modules) { - typeCollection *tc = (*i)->getModuleTypes(); + typeCollection *tc = m->getModuleTypes(); if (!tc) continue; type = tc->findVariableType(name, Type::share); if (type) break; @@ -2234,11 +1791,11 @@ SYMTAB_EXPORT bool Symtab::emitSymbols(Object *linkedFile,std::string filename, { // Start with all the defined symbols std::set allSyms; - allSyms.insert(everyDefinedSymbol.begin(), everyDefinedSymbol.end()); + allSyms.insert(impl->everyDefinedSymbol.begin(), impl->everyDefinedSymbol.end()); // Add the undefined dynamic symbols - allSyms.insert(undefDynSyms.begin(), undefDynSyms.end()); + allSyms.insert(impl->undefDynSyms.begin(), impl->undefDynSyms.end()); // Write the new file return linkedFile->emitDriver(filename, allSyms, flag); @@ -2262,18 +1819,6 @@ SYMTAB_EXPORT void Symtab::addDynLibSubstitution(std::string oldName, std::strin SYMTAB_EXPORT std::string Symtab::getDynLibSubstitution(std::string name) { -#ifdef BINEDIT_DEBUG - map::iterator iter = dynLibSubs.begin(); - - printf ("substitutions for %s:\n", mf->filename().c_str()); - - while (iter != dynLibSubs.end()) - { - printf(" \"%s\" => \"%s\"\n", iter->first.c_str(), iter->second.c_str()); - iter++; - } -#endif - map::iterator loc = dynLibSubs.find(name); if (loc == dynLibSubs.end()) @@ -2353,47 +1898,6 @@ SYMTAB_EXPORT bool Symtab::fixup_RegionAddr(const char* name, Offset memOffset, return true; } -SYMTAB_EXPORT bool Symtab::fixup_SymbolAddr(const char* name, Offset newOffset) -{ - Symbol* sym; - { - // Find the symbol. - indexed_symbols::by_name_t::const_accessor ma; - if(!everyDefinedSymbol.by_mangled.find(ma, name)) return false; - if(ma->second.size() > 1) - create_printf("*** Found %zu symbols with name %s. Expecting 1.\n", - ma->second.size(), name); - sym = ma->second[0]; - - // Update symbol. - indexed_symbols::master_t::accessor a; - if (!everyDefinedSymbol.master.find(a, sym)) { - assert(!"everyDefinedSymbol.master.find(a, sym)"); - } - Offset old = a->second; - - sym->setOffset(newOffset); - a->second = newOffset; - - // Update the by_offset table - indexed_symbols::by_offset_t::accessor oa; - if (!everyDefinedSymbol.by_offset.find(oa, old)) { - assert(!"everyDefinedSymbol.by_offset.find(oa, old)"); - } - std::remove(oa->second.begin(), oa->second.end(), sym); - - everyDefinedSymbol.by_offset.insert(oa, newOffset); - oa->second.push_back(sym); - } - - // Update aggregates. - if (!doNotAggregate(sym)) { - addSymbolToAggregates(sym); - } - - return true; -} - SYMTAB_EXPORT bool Symtab::updateRegion(const char* name, void *buffer, unsigned size) { Region *sec; @@ -2515,12 +2019,12 @@ SYMTAB_EXPORT char *Symtab::mem_image() const SYMTAB_EXPORT std::string Symtab::file() const { assert(mf); - return mf->pathname(); + return mf->filename(); } SYMTAB_EXPORT std::string Symtab::name() const { - return mf->filename(); + return extract_pathname_tail(mf->filename()); } SYMTAB_EXPORT std::string Symtab::memberName() const @@ -2547,279 +2051,6 @@ SYMTAB_EXPORT LookupInterface::~LookupInterface() { } - -SYMTAB_EXPORT ExceptionBlock::ExceptionBlock(Offset tStart, - unsigned tSize, - Offset cStart) -: tryStart_(tStart), trySize_(tSize), catchStart_(cStart), hasTry_(true), - tryStart_ptr(0), tryEnd_ptr(0), catchStart_ptr(0), fdeStart_ptr(0), fdeEnd_ptr(0) -{ -} - - SYMTAB_EXPORT ExceptionBlock::ExceptionBlock(Offset cStart) -: tryStart_(0), trySize_(0), catchStart_(cStart), hasTry_(false), - tryStart_ptr(0), tryEnd_ptr(0), catchStart_ptr(0), fdeStart_ptr(0), fdeEnd_ptr(0) -{ -} - -SYMTAB_EXPORT bool ExceptionBlock::hasTry() const -{ - return hasTry_; -} - -SYMTAB_EXPORT Offset ExceptionBlock::tryStart() const -{ - return tryStart_; -} - -SYMTAB_EXPORT Offset ExceptionBlock::tryEnd() const -{ - return tryStart_ + trySize_; -} - -SYMTAB_EXPORT Offset ExceptionBlock::trySize() const -{ - return trySize_; -} - -SYMTAB_EXPORT bool ExceptionBlock::contains(Offset a) const -{ - return (a >= tryStart_ && a < tryStart_ + trySize_); -} - -SYMTAB_EXPORT relocationEntry::relocationEntry() : - target_addr_(0), - rel_addr_(0), - addend_(0), - rtype_(Region::RT_REL), - name_(""), - dynref_(NULL), - relType_(0), - rel_struct_addr_(0) -{ -} - -SYMTAB_EXPORT relocationEntry::relocationEntry(Offset ta, Offset ra, std::string n, - Symbol *dynref, unsigned long relType) : - target_addr_(ta), - rel_addr_(ra), - addend_(0), - rtype_(Region::RT_REL), - name_(n), - dynref_(dynref), - relType_(relType), - rel_struct_addr_(0) -{ -} - -SYMTAB_EXPORT relocationEntry::relocationEntry(Offset ta, Offset ra, Offset add, - std::string n, Symbol *dynref, unsigned long relType) : - target_addr_(ta), - rel_addr_(ra), - addend_(add), - rtype_(Region::RT_REL), - name_(n), - dynref_(dynref), - relType_(relType), - rel_struct_addr_(0) -{ -} - -SYMTAB_EXPORT relocationEntry::relocationEntry(Offset ra, std::string n, - Symbol *dynref, unsigned long relType, Region::RegionType rtype) : - target_addr_(0), - rel_addr_(ra), - addend_(0), - rtype_(rtype), - name_(n), - dynref_(dynref), - relType_(relType), - rel_struct_addr_(0) -{ -} - -SYMTAB_EXPORT relocationEntry::relocationEntry(Offset ta, Offset ra, Offset add, - std::string n, Symbol *dynref, unsigned long relType, - Region::RegionType rtype) : - target_addr_(ta), - rel_addr_(ra), - addend_(add), - rtype_(rtype), - name_(n), - dynref_(dynref), - relType_(relType), - rel_struct_addr_(0) -{ -} - -SYMTAB_EXPORT Offset relocationEntry::target_addr() const -{ - return target_addr_; -} - -SYMTAB_EXPORT void relocationEntry::setTargetAddr(const Offset off) -{ - target_addr_ = off; -} - -SYMTAB_EXPORT Offset relocationEntry::rel_addr() const -{ - return rel_addr_; -} - -SYMTAB_EXPORT void relocationEntry::setRelAddr(const Offset value) -{ - rel_addr_ = value; -} - -SYMTAB_EXPORT const string &relocationEntry::name() const -{ - return name_; -} - -SYMTAB_EXPORT Symbol *relocationEntry::getDynSym() const -{ - return dynref_; -} - -SYMTAB_EXPORT bool relocationEntry::addDynSym(Symbol *dynref) -{ - dynref_ = dynref; - return true; -} - -SYMTAB_EXPORT Region::RegionType relocationEntry::regionType() const -{ - return rtype_; -} - -SYMTAB_EXPORT unsigned long relocationEntry::getRelType() const -{ - return relType_; -} - -SYMTAB_EXPORT Offset relocationEntry::addend() const -{ - return addend_; -} - -SYMTAB_EXPORT void relocationEntry::setAddend(const Offset value) -{ - addend_ = value; -} - -SYMTAB_EXPORT void relocationEntry::setRegionType(const Region::RegionType value) -{ - rtype_ = value; -} - -SYMTAB_EXPORT void relocationEntry::setName(const std::string &newName) { - name_ = newName; -} - -bool relocationEntry::operator==(const relocationEntry &r) const -{ - if (target_addr_ != r.target_addr_) return false; - if (rel_addr_ != r.rel_addr_) return false; - if (addend_ != r.addend_) return false; - if (rtype_ != r.rtype_) return false; - if (name_ != r.name_) return false; - if (relType_ != r.relType_) return false; - if (dynref_ && !r.dynref_) return false; - if (!dynref_ && r.dynref_) return false; - if (dynref_) - { - if (dynref_->getMangledName() != r.dynref_->getMangledName()) return false; - if (dynref_->getOffset() != r.dynref_->getOffset()) return false; - } - - return true; -} - -ostream & Dyninst::SymtabAPI::operator<< (ostream &os, const relocationEntry &r) -{ - if( r.getDynSym() != NULL ) { - os << "Name: " << setw(20) << ( "'" + r.getDynSym()->getMangledName() + "'" ); - }else{ - os << "Name: " << setw(20) << r.name(); - } - os << " Offset: " << std::hex << std::setfill('0') << setw(8) << r.rel_addr() - << std::dec << std::setfill(' ') - << " Offset: " << std::hex << std::setfill('0') << setw(8) << r.target_addr() - << std::dec << std::setfill(' ') - << " Addend: " << r.addend() - << " Region: " << Region::regionType2Str(r.regionType()) - << " Type: " << setw(15) << relocationEntry::relType2Str(r.getRelType()) - << "(" << r.getRelType() << ")"; - if( r.getDynSym() != NULL ) { - os << " Symbol Offset: " << std::hex << std::setfill('0') << setw(8) << r.getDynSym()->getOffset(); - os << std::dec << std::setfill(' '); - if( r.getDynSym()->isCommonStorage() ) { - os << " COM"; - }else if( r.getDynSym()->getRegion() == NULL ) { - os << " UND"; - } - } - return os; -} - -const char *Symbol::symbolType2Str(SymbolType t) -{ - switch (t) - { - CASE_RETURN_STR(ST_UNKNOWN); - CASE_RETURN_STR(ST_FUNCTION); - CASE_RETURN_STR(ST_OBJECT); - CASE_RETURN_STR(ST_MODULE); - CASE_RETURN_STR(ST_SECTION); - CASE_RETURN_STR(ST_TLS); - CASE_RETURN_STR(ST_DELETED); - CASE_RETURN_STR(ST_NOTYPE); - CASE_RETURN_STR(ST_INDIRECT); - }; - - return "invalid symbol type"; -} - -const char *Symbol::symbolLinkage2Str(SymbolLinkage t) -{ - switch (t) - { - CASE_RETURN_STR(SL_UNKNOWN); - CASE_RETURN_STR(SL_GLOBAL); - CASE_RETURN_STR(SL_LOCAL); - CASE_RETURN_STR(SL_WEAK); - CASE_RETURN_STR(SL_UNIQUE); - }; - - return "invalid symbol linkage"; -} - -const char *Symbol::symbolTag2Str(SymbolTag t) -{ - switch (t) - { - CASE_RETURN_STR(TAG_UNKNOWN); - CASE_RETURN_STR(TAG_USER); - CASE_RETURN_STR(TAG_LIBRARY); - CASE_RETURN_STR(TAG_INTERNAL); - }; - - return "invalid symbol tag"; -} - -const char *Symbol::symbolVisibility2Str(SymbolVisibility t) -{ - switch(t) { - CASE_RETURN_STR(SV_UNKNOWN); - CASE_RETURN_STR(SV_DEFAULT); - CASE_RETURN_STR(SV_INTERNAL); - CASE_RETURN_STR(SV_HIDDEN); - CASE_RETURN_STR(SV_PROTECTED); - } - return "invalid symbol visibility"; -} - bool Symtab::hasStackwalkDebugInfo() { @@ -2856,11 +2087,7 @@ const Object *Symtab::getObject() const void Symtab::parseTypesNow() { - if (isTypeInfoValid_) - return; - isTypeInfoValid_ = true; - - parseTypes(); + std::call_once(this->impl->types_parsed, [this](){ this->parseTypes(); }); } SYMTAB_EXPORT Offset Symtab::getElfDynamicOffset() @@ -3072,21 +2299,10 @@ void Symtab::rebase(Offset loadOff) load_address_ = loadOff; } -ModRangeLookup *Symtab::mod_lookup() { - if(!mod_lookup_) mod_lookup_ = new ModRangeLookup; - return mod_lookup_; - -} - - void Symtab::dumpModRanges() { - if (mod_lookup_) { - mod_lookup_->PrintPreorder(); - } + impl->mod_lookup_.PrintPreorder(); } void Symtab::dumpFuncRanges() { - if (func_lookup) { - func_lookup->PrintPreorder(); - } + impl->func_lookup.PrintPreorder(); } diff --git a/symtabAPI/src/SymtabReader.C b/symtabAPI/src/SymtabReader.C index 2e22c60b8b..cfc87e22a7 100644 --- a/symtabAPI/src/SymtabReader.C +++ b/symtabAPI/src/SymtabReader.C @@ -28,6 +28,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include "symtabAPI/h/SymtabReader.h" #include "symtabAPI/h/Symtab.h" #include "symtabAPI/h/Symbol.h" diff --git a/symtabAPI/src/Type-mem.h b/symtabAPI/src/Type-mem.h index 356664982c..2f534a7d6e 100644 --- a/symtabAPI/src/Type-mem.h +++ b/symtabAPI/src/Type-mem.h @@ -32,7 +32,10 @@ #define TYPE_MEM_H_ #include "symtabAPI/h/Type.h" -#include "boost/static_assert.hpp" +#include "dyncompat/static_assert.hpp" +#include +#include +#include #include using namespace Dyninst; @@ -41,31 +44,27 @@ using namespace SymtabAPI; template T *upgradePlaceholder(Type *placeholder, T *new_type) { - assert(sizeof(T) <= Type::max_size); - - void* mem = realloc((void *) placeholder, sizeof(T)); - assert(mem == (void *) placeholder); - memset(mem, 0, sizeof(T)); - - T *ret = new(mem) T(); - assert(mem == (void *) ret); - *ret = *new_type; - return ret; + assert(sizeof(T) <= Type::max_size); + memset(static_cast(placeholder), 0, Type::max_size); + T* ret = new(placeholder) T{}; + assert(static_cast(placeholder) == static_cast(ret)); + *ret = *new_type; + return ret; } template -typename boost::enable_if< - boost::integral_constant::value)>, -boost::shared_ptr>::type typeCollection::addOrUpdateType(boost::shared_ptr type) +typename std::enable_if< + !std::is_same::value, +dyncompat::shared_ptr>::type typeCollection::addOrUpdateType(dyncompat::shared_ptr type) { //Instanciating this function for 'Type' would be a mistake, which //the following assert tries to guard against. If you trigger this, //then a caller to this function is likely using 'Type'. Change //this to a more specific call, e.g. typeFunction instead of Type // NOTE: Disabled, we use SFINAE instead to handle this. - // BOOST_STATIC_ASSERT(sizeof(T) != sizeof(Type)); + // DYN_STATIC_ASSERT(sizeof(T) != sizeof(Type)); - dyn_c_hash_map>::accessor a; + dyn_c_hash_map>::accessor a; if (typesByID.insert(a, {type->getID(), type})) { if ( type->getName() != "" ) @@ -96,7 +95,7 @@ boost::shared_ptr>::type typeCollection::addOrUpdateType(boost::shared_ptr /* The type may have gained a name. */ if ( a->second->getName() != "") { - dyn_c_hash_map>::accessor o; + dyn_c_hash_map>::accessor o; if (typesByName.find(o, a->second->getName())) { if (a->second != o->second) diff --git a/symtabAPI/src/Type.C b/symtabAPI/src/Type.C index 2bd1336fb0..d1a34d2752 100644 --- a/symtabAPI/src/Type.C +++ b/symtabAPI/src/Type.C @@ -28,6 +28,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include "common/src/vgannotations.h" #include @@ -45,7 +46,7 @@ #include #include "concurrent.h" -#include +#include using namespace Dyninst; using namespace Dyninst::SymtabAPI; @@ -58,7 +59,7 @@ static int findIntrensicType(std::string &name); // This is the ID that is decremented for each type a user defines. It is // Global so that every type that the user defines has a unique ID. -static boost::atomic user_type_id(-10000); +static dyncompat::atomic user_type_id(-10000); static typeId_t getUniqueTypeId() { @@ -296,42 +297,12 @@ bool Type::isCompatible(Type * /*oType*/) /* * ENUM */ -typeEnum::typeEnum(int ID, std::string name) - : Type(name, ID, dataEnum) -{ - size_ = sizeof(int); -} - -typeEnum::typeEnum(std::string name) - : Type(name, ::getUniqueTypeId(), dataEnum) -{ - size_ = sizeof(int); -} - -typeEnum *typeEnum::create(std::string &name, dyn_c_vector< std::pair *> &constants, Symtab *obj) -{ - typeEnum *typ = new typeEnum(name); - for(unsigned i=0; iaddConstant(constants[i]->first, constants[i]->second); - - if(obj) - obj->addType(typ); - //obj->addType(typ); TODO: declare a static container if obj is NULL and add to it. - //Symtab::noObjTypes->push_back(typ); ?? - return typ; +typeEnum::typeEnum(dyncompat::shared_ptr underlying_type, std::string name, typeId_t ID) : + derivedType(name, ID, underlying_type->getSize(), dataEnum) { + baseType_ = underlying_type; } - -typeEnum *typeEnum::create(std::string &name, dyn_c_vector &constNames, Symtab *obj) -{ - typeEnum *typ = new typeEnum(name); - for(unsigned i=0; iaddConstant(constNames[i], i); - if(obj) - obj->addType(typ); - //obj->addType(typ); TODO: declare a static container if obj is NULL and add to it. - //Symtab::noObjTypes->push_back(typ); ?? - return typ; -} +typeEnum::typeEnum(dyncompat::shared_ptr underlying_type, std::string name) : + typeEnum(underlying_type, std::move(name), ::getUniqueTypeId()) {} dyn_c_vector > &typeEnum::getConstants() { @@ -389,21 +360,21 @@ bool typeEnum::isCompatible(Type *otype) * POINTER */ -typePointer::typePointer(int ID, boost::shared_ptr ptr, std::string name) +typePointer::typePointer(int ID, dyncompat::shared_ptr ptr, std::string name) : derivedType(name, ID, 0, dataPointer) { size_ = sizeof(void *); if (ptr) setPtr(ptr); } -typePointer::typePointer(boost::shared_ptr ptr, std::string name) +typePointer::typePointer(dyncompat::shared_ptr ptr, std::string name) : derivedType(name, getUniqueTypeId(), 0, dataPointer) { size_ = sizeof(void *); if (ptr) setPtr(ptr); } -typePointer *typePointer::create(std::string &name, boost::shared_ptr ptr, Symtab *obj) +typePointer *typePointer::create(std::string &name, dyncompat::shared_ptr ptr, Symtab *obj) { if(!ptr) return NULL; @@ -417,7 +388,7 @@ typePointer *typePointer::create(std::string &name, boost::shared_ptr ptr, return typ; } -typePointer *typePointer::create(std::string &name, boost::shared_ptr ptr, int size, Symtab *obj) +typePointer *typePointer::create(std::string &name, dyncompat::shared_ptr ptr, int size, Symtab *obj) { if(!ptr) return NULL; @@ -432,7 +403,7 @@ typePointer *typePointer::create(std::string &name, boost::shared_ptr ptr, return typ; } -bool typePointer::setPtr(boost::shared_ptr ptr) { +bool typePointer::setPtr(dyncompat::shared_ptr ptr) { assert(ptr); baseType_ = ptr; @@ -473,21 +444,21 @@ void typePointer::fixupUnknowns(Module *module) * FUNCTION */ -typeFunction::typeFunction(typeId_t ID, boost::shared_ptr retType, std::string name) : +typeFunction::typeFunction(typeId_t ID, dyncompat::shared_ptr retType, std::string name) : Type(name, ID, dataFunction), retType_(retType) { size_ = sizeof(void *); } -typeFunction::typeFunction(boost::shared_ptr retType, std::string name) : +typeFunction::typeFunction(dyncompat::shared_ptr retType, std::string name) : Type(name, ::getUniqueTypeId(), dataFunction), retType_(retType) { size_ = sizeof(void *); } -typeFunction *typeFunction::create(std::string &name, boost::shared_ptr retType, dyn_c_vector> ¶mTypes, Symtab *obj) +typeFunction *typeFunction::create(std::string &name, dyncompat::shared_ptr retType, dyn_c_vector> ¶mTypes, Symtab *obj) { typeFunction *type = new typeFunction(retType, name); for(unsigned i=0;i re return type; } -boost::shared_ptr typeFunction::getReturnType(Type::do_share_t) const{ +dyncompat::shared_ptr typeFunction::getReturnType(Type::do_share_t) const{ return retType_; } -bool typeFunction::setRetType(boost::shared_ptr rtype) { +bool typeFunction::setRetType(dyncompat::shared_ptr rtype) { retType_ = rtype; return true; } -bool typeFunction::addParam(boost::shared_ptr paramType){ +bool typeFunction::addParam(dyncompat::shared_ptr paramType){ params_.push_back(paramType); return true; } -dyn_c_vector> &typeFunction::getParams(){ +dyn_c_vector> &typeFunction::getParams(){ return params_; } @@ -531,8 +502,8 @@ bool typeFunction::isCompatible(Type *otype) { if (retType_ != oFunctiontype->retType_) return false; - dyn_c_vector>& fields1 = this->getParams(); - dyn_c_vector>& fields2 = oFunctiontype->getParams(); + dyn_c_vector>& fields1 = this->getParams(); + dyn_c_vector>& fields2 = oFunctiontype->getParams(); if (fields1.size() != fields2.size()) { //reportError(BPatchWarning, 112, @@ -615,7 +586,7 @@ bool typeSubrange::isCompatible(Type *otype) { */ typeArray::typeArray(typeId_t ID, - boost::shared_ptr base, + dyncompat::shared_ptr base, long low, long hi, std::string name, @@ -627,7 +598,7 @@ typeArray::typeArray(typeId_t ID, //if (!base) arrayElem = Symtab::type_Error; } -typeArray::typeArray(boost::shared_ptr base, +typeArray::typeArray(dyncompat::shared_ptr base, long low, long hi, std::string name, @@ -639,7 +610,7 @@ typeArray::typeArray(boost::shared_ptr base, assert(base); } -typeArray *typeArray::create(std::string &name, boost::shared_ptr type, long low, long hi, Symtab *obj) +typeArray *typeArray::create(std::string &name, dyncompat::shared_ptr type, long low, long hi, Symtab *obj) { typeArray *typ = new typeArray(type, low, hi, name); @@ -684,7 +655,7 @@ void typeArray::merge(Type *other) arrayElem = otherarray->arrayElem; } -boost::shared_ptr typeArray::getBaseType(Type::do_share_t) const +dyncompat::shared_ptr typeArray::getBaseType(Type::do_share_t) const { return arrayElem; } @@ -782,7 +753,7 @@ typeStruct::typeStruct(std::string name) : { } -typeStruct *typeStruct::create(std::string &name, dyn_c_vector< std::pair> *> &flds, +typeStruct *typeStruct::create(std::string &name, dyn_c_vector< std::pair> *> &flds, Symtab *obj) { int offset = 0; @@ -918,7 +889,7 @@ typeUnion::typeUnion(std::string name) : { } -typeUnion *typeUnion::create(std::string &name, dyn_c_vector< std::pair> *> &flds, +typeUnion *typeUnion::create(std::string &name, dyn_c_vector< std::pair> *> &flds, Symtab *obj) { typeUnion *typ = new typeUnion(name); @@ -1173,7 +1144,7 @@ dyn_c_vector *typeCommon::getCblocks() const * TYPEDEF */ -typeTypedef::typeTypedef(typeId_t ID, boost::shared_ptr base, std::string name, unsigned int sizeHint) : +typeTypedef::typeTypedef(typeId_t ID, dyncompat::shared_ptr base, std::string name, unsigned int sizeHint) : derivedType(name, ID, 0, dataTypedef) { baseType_ = base; @@ -1186,7 +1157,7 @@ typeTypedef::typeTypedef(typeId_t ID, boost::shared_ptr base, std::string sizeHint_ = sizeHint / 8; } -typeTypedef::typeTypedef(boost::shared_ptr base, std::string name, unsigned int sizeHint) : +typeTypedef::typeTypedef(dyncompat::shared_ptr base, std::string name, unsigned int sizeHint) : derivedType(name, getUniqueTypeId(), 0, dataTypedef) { assert(base != NULL); @@ -1194,7 +1165,7 @@ typeTypedef::typeTypedef(boost::shared_ptr base, std::string name, unsigne sizeHint_ = sizeHint / 8; } -typeTypedef *typeTypedef::create(std::string &name, boost::shared_ptr baseType, Symtab *obj) +typeTypedef *typeTypedef::create(std::string &name, dyncompat::shared_ptr baseType, Symtab *obj) { if(!baseType) return NULL; @@ -1255,19 +1226,19 @@ void typeTypedef::fixupUnknowns(Module *module) * REFERENCE */ -typeRef::typeRef(int ID, boost::shared_ptr refType, std::string name) : +typeRef::typeRef(int ID, dyncompat::shared_ptr refType, std::string name) : derivedType(name, ID, 0, dataReference) { baseType_ = refType; } -typeRef::typeRef(boost::shared_ptr refType, std::string name) : +typeRef::typeRef(dyncompat::shared_ptr refType, std::string name) : derivedType(name, getUniqueTypeId(), 0, dataReference) { baseType_ = refType; } -typeRef *typeRef::create(std::string &name, boost::shared_ptr ref, Symtab *obj) +typeRef *typeRef::create(std::string &name, dyncompat::shared_ptr ref, Symtab *obj) { typeRef *typ = new typeRef(ref, name); @@ -1411,7 +1382,7 @@ void fieldListType::fixupComponents() * type object. * STRUCTS OR UNIONS */ -void fieldListType::addField(std::string fieldname, boost::shared_ptr type, int offsetVal, visibility_t vis) +void fieldListType::addField(std::string fieldname, dyncompat::shared_ptr type, int offsetVal, visibility_t vis) { Field * newField; newField = new Field(fieldname, type, offsetVal, vis); @@ -1433,7 +1404,7 @@ void fieldListType::addField(Field *fld) postFieldInsert(newField->getSize()); } -void fieldListType::addField(unsigned num, std::string fieldname, boost::shared_ptr type, int offsetVal, visibility_t vis) +void fieldListType::addField(unsigned num, std::string fieldname, dyncompat::shared_ptr type, int offsetVal, visibility_t vis) { Field * newField; newField = new Field(fieldname, type, offsetVal, vis); @@ -1495,7 +1466,7 @@ derivedType::derivedType(std::string &name, int size, dataClass typeDes) size_ = size; } -boost::shared_ptr derivedType::getConstituentType(Type::do_share_t) const +dyncompat::shared_ptr derivedType::getConstituentType(Type::do_share_t) const { return baseType_; } @@ -1600,7 +1571,7 @@ Field::Field() : * an enumerated type. * type = offset = size = 0; */ -Field::Field(std::string name, boost::shared_ptr typ, int offsetVal, visibility_t vis) : +Field::Field(std::string name, dyncompat::shared_ptr typ, int offsetVal, visibility_t vis) : FIELD_ANNOTATABLE_CLASS(), fieldName_(name), type_(typ), @@ -1613,7 +1584,7 @@ std::string &Field::getName() return fieldName_; } -boost::shared_ptr Field::getType(Type::do_share_t) +dyncompat::shared_ptr Field::getType(Type::do_share_t) { return type_; } @@ -1695,7 +1666,6 @@ Type::Type() : ID_(0), name_(std::string("unnamedType")), size_(0), fieldListType::fieldListType() : derivedFieldList(NULL) {} rangedType::rangedType() : low_(0), hi_(0) {} derivedType::derivedType() : baseType_(NULL) {} -typeEnum::typeEnum() {} typeFunction::typeFunction() : retType_(NULL) {} typeCommon::typeCommon() {} typeStruct::typeStruct() {} diff --git a/symtabAPI/src/Variable.C b/symtabAPI/src/Variable.C index 5ec2b35877..0adc8dbb58 100644 --- a/symtabAPI/src/Variable.C +++ b/symtabAPI/src/Variable.C @@ -30,6 +30,7 @@ // $Id: Object.C,v 1.31 2008/11/03 15:19:25 jaw Exp $ +#include #include "Annotatable.h" #include "Symtab.h" @@ -40,7 +41,7 @@ #include "Aggregate.h" #include "Function.h" #include - +#include "registers/abstract_regs.h" #include "symtabAPI/src/Object.h" #include @@ -61,19 +62,19 @@ Variable::Variable() : type_(NULL) { } -void Variable::setType(boost::shared_ptr type) +void Variable::setType(dyncompat::shared_ptr type) { type_ = type; } -boost::shared_ptr Variable::getType(Type::do_share_t) +dyncompat::shared_ptr Variable::getType(Type::do_share_t) { module_->exec()->parseTypesNow(); return type_; } void Variable::print(std::ostream &os) const { - boost::shared_ptr var_t = const_cast(this)->getType(Type::share); + dyncompat::shared_ptr var_t = const_cast(this)->getType(Type::share); std::string tname(var_t ? var_t->getName() : "no_type"); os << "Variable{" @@ -107,7 +108,7 @@ bool Variable::removeSymbol(Symbol *sym) return true; } -localVar::localVar(std::string name, boost::shared_ptr typ, std::string fileName, +localVar::localVar(std::string name, dyncompat::shared_ptr typ, std::string fileName, int lineNum, FunctionBase *f, std::vector *locs) : name_(name), type_(typ), @@ -260,12 +261,12 @@ std::string &localVar::getName() return name_; } -boost::shared_ptr localVar::getType(Type::do_share_t) +dyncompat::shared_ptr localVar::getType(Type::do_share_t) { return type_; } -bool localVar::setType(boost::shared_ptr newType) +bool localVar::setType(dyncompat::shared_ptr newType) { type_ = newType; return true; diff --git a/symtabAPI/src/debug.C b/symtabAPI/src/debug.C index 98e9a0bff9..376b9b5f4d 100644 --- a/symtabAPI/src/debug.C +++ b/symtabAPI/src/debug.C @@ -42,11 +42,6 @@ int sym_debug_types = 0; int sym_debug_translate = 0; int sym_debug_rewrite = 0; -#if defined(_MSC_VER) -#pragma warning(push) -#pragma warning(disable:4996) -#endif - bool init_debug_symtabAPI() { static bool initialized = false; if (initialized) return true; @@ -154,8 +149,3 @@ int rewrite_printf(const char *format, ...) return ret; } - - -#if defined(_MSC_VER) -#pragma warning(pop) -#endif diff --git a/symtabAPI/src/dwarfWalker.C b/symtabAPI/src/dwarfWalker.C index b948e54d1c..d7c26e4dde 100644 --- a/symtabAPI/src/dwarfWalker.C +++ b/symtabAPI/src/dwarfWalker.C @@ -28,7 +28,9 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include "common/src/vgannotations.h" +#include "compiler_diagnostics.h" #include "dwarfWalker.h" #include "headers.h" #include "Module.h" @@ -43,50 +45,53 @@ #include "pathName.h" #include "debug_common.h" #include "Type-mem.h" -#include "elfutils/libdw.h" #include +#include +#include +#include +#include using namespace Dyninst; using namespace SymtabAPI; using namespace DwarfDyninst; using namespace std; -#define DWARF_FAIL_RET_VAL(x, v) { \ +#define DWARF_FAIL_RET_VAL(x, v) do { \ int dwarf_fail_ret_val_status = (x); \ if (dwarf_fail_ret_val_status != 0) { \ types_printf("[%s:%d]: libdwarf returned %d, ret false\n", \ FILE__, __LINE__, dwarf_fail_ret_val_status); \ return (v); \ } \ - } + } while (0) #define DWARF_FAIL_RET(x) DWARF_FAIL_RET_VAL(x, false) -#define DWARF_ERROR_RET_VAL(x, v) { \ +#define DWARF_ERROR_RET_VAL(x, v) do { \ int dwarf_error_ret_val_status = (x); \ if (dwarf_error_ret_val_status == 1 /*DW_DLV_ERROR*/) { \ types_printf("[%s:%d]: parsing failure, ret false\n", \ FILE__, __LINE__); \ return (v); \ } \ - } + } while (0) #define DWARF_ERROR_RET(x) DWARF_ERROR_RET_VAL(x, false) -#define DWARF_CHECK_RET_VAL(x, v) { \ +#define DWARF_CHECK_RET_VAL(x, v) do { \ if (x) { \ types_printf("[%s:%d]: parsing failure, ret false\n", \ FILE__, __LINE__); \ return (v); \ } \ - } + } while (0) #define DWARF_CHECK_RET(x) DWARF_CHECK_RET_VAL(x, false) -DwarfWalker::DwarfWalker(Symtab *symtab, ::Dwarf * dbg) : +DwarfWalker::DwarfWalker(Symtab *symtab, ::Dwarf *dbg, std::shared_ptr pf) : DwarfParseActions(symtab, dbg), + parsedFuncs(pf), is_mangled_name_(false), modLow(0), modHigh(0), cu_header_length(0), - version(0), abbrev_offset(0), addr_size(0), offset_size(0), @@ -96,6 +101,9 @@ DwarfWalker::DwarfWalker(Symtab *symtab, ::Dwarf * dbg) : next_cu_header(0), compile_offset(0) { + if (!parsedFuncs) { + parsedFuncs = std::make_shared(); + } } DwarfWalker::~DwarfWalker() { @@ -142,10 +150,6 @@ bool DwarfWalker::parse() { { if(!dwarf_offdie_types(dbg(), cu_off + cu_header_length, ¤t_cu_die)) continue; - /*Dwarf_Half moduleTag = dwarf_tag(¤t_cu_die); - if (moduleTag == DW_TAG_partial_unit) { - continue; - }*/ module_dies.push_back(current_cu_die); compile_offset = next_cu_header; } @@ -160,10 +164,6 @@ bool DwarfWalker::parse() { { if(!dwarf_offdie(dbg(), cu_off + cu_header_length, ¤t_cu_die)) continue; - /*Dwarf_Half moduleTag = dwarf_tag(¤t_cu_die); - if (moduleTag == DW_TAG_partial_unit) { - continue; - }*/ module_dies.push_back(current_cu_die); compile_offset = next_cu_header; } @@ -180,7 +180,7 @@ bool DwarfWalker::parse() { } else { #pragma omp parallel { - DwarfWalker w(symtab(), dbg()); + DwarfWalker w(symtab(), dbg(), parsedFuncs); #pragma omp for reduction(leftmost:fixUnknownMod) \ schedule(dynamic) nowait for (unsigned int i = 0; i < module_dies.size(); i++) { @@ -203,7 +203,7 @@ bool DwarfWalker::parse() { for (;typeIter!=moduleTypes->typesByID.end();typeIter++) { typeIter->second->fixupUnknowns(fixUnknownMod); - } /* end iteration over types. */ + } /* Fix the types of variables. */ std::string variableName; @@ -214,56 +214,34 @@ bool DwarfWalker::parse() { moduleTypes->findType( variableIter->second->getID(), Type::share ) != NULL ) { variableIter->second = moduleTypes->findType(variableIter->second->getID(), Type::share); - } /* end if data class is unknown but the type exists. */ - } /* end iteration over variables. */ + } + } moduleTypes->setDwarfParsed(); return true; } bool DwarfWalker::parseModule(Dwarf_Die moduleDIE, Module *&fixUnknownMod) { - /* Make sure we've got the right one. */ - Dwarf_Half moduleTag; - moduleTag = dwarf_tag(&moduleDIE); - - if (moduleTag != DW_TAG_compile_unit - && moduleTag != DW_TAG_partial_unit - && moduleTag != DW_TAG_type_unit) + // Make sure `moduleDIE` is actually a compilation unit + if (!DwarfDyninst::is_parseable_unit(moduleDIE)) { + dwarf_printf("(0x%lx) Attempting to parse unit that isn't parseable.\n", id()); return false; - - /* Extract the name of this module. */ - std::string moduleName; - if (!findDieName(moduleDIE, moduleName)) return false; - - // DIEs without name or named will be associated to - // the default module (whose name is ELF filename) - setModuleFromName(moduleName); - dwarf_printf("Mapped to Symtab module 0x%p %s\n", (void*)mod(), mod()->fileName().c_str()); - - if (moduleName.empty() && moduleTag == DW_TAG_type_unit) { - uint64_t sig8 = * reinterpret_cast(&signature); - char buf[20]; - snprintf(buf, sizeof(buf), "{%016llx}", (unsigned long long)sig8); - moduleName = buf; } - if (moduleName.empty()) { - moduleName = "{ANONYMOUS}"; - } + std::string moduleName = DwarfDyninst::die_name(moduleDIE); - if(moduleName=="") - { - auto off_die = dwarf_dieoffset(&moduleDIE); - std::stringstream suffix; - suffix << std::hex << off_die; - moduleName = "" + suffix.str(); + auto moduleTag = dwarf_tag(&moduleDIE); + if (moduleName.empty() && moduleTag == DW_TAG_type_unit) { + uint64_t sig8 = * reinterpret_cast(&signature); + char buf[20]; + snprintf(buf, sizeof(buf), "{%016llx}", (unsigned long long)sig8); + moduleName = buf; } dwarf_printf("Next DWARF module: %s with DIE %p and tag %d\n", moduleName.c_str(), (void*)moduleDIE.addr, moduleTag); /* Set the language, if any. */ Dwarf_Attribute languageAttribute; - //DWARF_ERROR_RET(dwarf_attr( moduleDIE, DW_AT_language, & languageAttribute, NULL )); dwarf_attr(&moduleDIE, DW_AT_language, &languageAttribute); // Set low and high ranges; this can fail, so don't check return addr. @@ -282,6 +260,16 @@ bool DwarfWalker::parseModule(Dwarf_Die moduleDIE, Module *&fixUnknownMod) { if (findConstant(DW_AT_high_pc, tempModHigh, &e, dbg())) { modHigh = convertDebugOffset(tempModHigh); } + + // Find the Symtab Module corresponding to this CU + mod() = [this]() { + SymtabAPI::Module* m = symtab()->findModuleByOffset(offset()); + if(m) return m; + return symtab()->getDefaultModule(); + }(); + + dwarf_printf("Mapped to Symtab module %p from '%s' at offset %zx\n", (void*)mod(), mod()->fileName().c_str(), offset()); + if(!fixUnknownMod){ fixUnknownMod = mod(); } @@ -292,50 +280,26 @@ bool DwarfWalker::parseModule(Dwarf_Die moduleDIE, Module *&fixUnknownMod) { return true; } - -void DwarfParseActions::setModuleFromName(std::string moduleName) -{ - if (!symtab()->findModuleByName(mod(), moduleName)) - { - moduleName = symtab()->file(); - if (!symtab()->findModuleByName(mod(), moduleName)) { - mod() = (symtab()->getDefaultModule()); - } - } -} - bool DwarfWalker::buildSrcFiles(::Dwarf * /*dbg*/, Dwarf_Die entry, StringTablePtr srcFiles) { size_t cnt = 0; Dwarf_Files * df; int ret = dwarf_getsrcfiles(&entry, &df, &cnt); if(ret==-1) return true; - boost::unique_lock l(srcFiles->lock); + dyncompat::unique_lock l(srcFiles->lock); if(!srcFiles->empty()) { return true; } // already parsed, the module had better be right. - srcFiles->emplace_back("Unknown file",""); - // get comp_dir in case need to make absolute paths - Dwarf_Attribute attr; - const char * comp_dir = dwarf_formstring( dwarf_attr(&entry, DW_AT_comp_dir, &attr) ); - std::string comp_dir_str( comp_dir ? comp_dir : "" ); + // The CU name is always an absolute path + auto comp_dir = Dyninst::DwarfDyninst::cu_dirname(entry); // store all file sources found by libdw - for (unsigned i = 1; i < cnt; ++i) { + for (unsigned i = 0; i < cnt; ++i) { auto filename = dwarf_filesrc(df, i, NULL, NULL); if(!filename) continue; - - // change to absolute if it's relative - std::string s_name(filename); - if(filename[0]!='/') - { - s_name = comp_dir_str + "/" + s_name; - } - - srcFiles->emplace_back(s_name,""); + srcFiles->emplace_back(DwarfDyninst::detail::absolute_path(filename, comp_dir),""); } - //cerr << "pointer: " << srcFiles.get() << endl << *(srcFiles.get()) << endl; return true; } @@ -364,7 +328,7 @@ bool DwarfWalker::parse_int(Dwarf_Die e, bool parseSib, bool dissociate_context) id(), stack_size(), curFunc()?curFunc()->getName().c_str():"(N/A)", (void*)curEnclosure().get(), (dbg()!=desc)?"sup":"not sup", - mod()->fullName().c_str(), (unsigned int)dwarf_tag(&e)); + mod()->fileName().c_str(), (unsigned int)dwarf_tag(&e)); bool ret = false; switch(dwarf_tag(&e)) { @@ -378,6 +342,12 @@ bool DwarfWalker::parse_int(Dwarf_Die e, bool parseSib, bool dissociate_context) case DW_TAG_lexical_block: ret = parseLexicalBlock(); break; + case DW_TAG_try_block: + ret = parseTryBlock(); + break; + case DW_TAG_catch_block: + ret = parseCatchBlock(); + break; case DW_TAG_common_block: ret = parseCommonBlock(); break; @@ -430,6 +400,7 @@ bool DwarfWalker::parse_int(Dwarf_Die e, bool parseSib, bool dissociate_context) case DW_TAG_ptr_to_member_type: case DW_TAG_pointer_type: case DW_TAG_reference_type: + case DW_TAG_rvalue_reference_type: ret = parseTypeReferences(); break; case DW_TAG_compile_unit: @@ -477,7 +448,6 @@ bool DwarfWalker::parse_int(Dwarf_Die e, bool parseSib, bool dissociate_context) if (ret && parseChild() ) { // Parse children Dwarf_Die childDwarf; - //Dwarf_Die e = entry(); int status = dwarf_child(&e, &childDwarf); if(status == -1) return false; @@ -520,21 +490,18 @@ bool DwarfWalker::parseCallsite() if (!has_line) return true; - std::string inline_file; - bool result = findString(DW_AT_call_file, inline_file); - if (!result) + using opt_string = dyncompat::optional; + opt_string inline_file = find_call_file(); + if (!inline_file) return false; Dyninst::Offset inline_line; - result = findConstant(DW_AT_call_line, inline_line, &e, dbg()); + bool result = findConstant(DW_AT_call_line, inline_line, &e, dbg()); if (!result) return false; InlinedFunction *ifunc = static_cast(curFunc()); - // cout << "Found inline call site in func (0x" << hex << id() << ") " - // << curFunc()->getName() << " at " << curFunc()->getOffset() << dec - // << ", file " << inline_file << ": " << inline_line << endl; - ifunc->setFile(inline_file); + ifunc->setFile(inline_file.get()); ifunc->callsite_line = inline_line; return true; } @@ -611,23 +578,44 @@ void DwarfParseActions::addPrettyFuncName(std::string name) curFunc()->addPrettyName(name, true, true); } + +// helper class to set and restore currentSubprogramFunction +namespace { +class SetAndRestoreFunction +{ + public: + SetAndRestoreFunction(FunctionBase* &v, FunctionBase* newFunc) : var(v) + { + savedFunc = var; + var = newFunc; + } + ~SetAndRestoreFunction() + { + var = savedFunc; + } + private: + FunctionBase* &var; + FunctionBase* savedFunc; +}; +} + + bool DwarfWalker::parseSubprogram(DwarfWalker::inline_t func_type) { bool name_result; dwarf_printf("(0x%lx) parseSubprogram entry\n", id()); - parseRangeTypes(dbg(), entry()); + parseRangeTypes(entry()); setFunctionFromRange(func_type); // Name first FunctionBase *func = curFunc(); name_result = findFuncName(); -// if(func) cout << hex << "Begin parseSubprogram for (" << id() << ") " << func->getName() << " at " << func->getOffset() << dec << endl; if (curEnclosure() && !func) { // This is a member function; create the type entry // Since curFunc is false, we're not going back to reparse this // entry with a function object. - boost::shared_ptr ftype = NULL; - getReturnType(false, ftype); + dyncompat::shared_ptr ftype = NULL; + getReturnType(ftype); addFuncToContainer(ftype); dwarf_printf("(0x%lx) parseSubprogram not parsing member function's children\n", id()); @@ -646,15 +634,29 @@ bool DwarfWalker::parseSubprogram(DwarfWalker::inline_t func_type) { return true; } - if (parsedFuncs.find(func) != parsedFuncs.end()) { - dwarf_printf("(0x%lx) parseSubprogram not parsing children b/c curFunc() not in parsedFuncs\n", id()); - if(name_result) { - dwarf_printf("\tname is %s\n", curName().c_str()); - } - setParseChild(false); - return true; + // this function's accessor lock to check if parsed and/or parse it + ParsedFuncs::accessor funcParsed; + + // recursive if parsing a specification or abstract origin, + // accessor is already locked + bool isRecursiveSubprogramParse = (func == currentSubprogramFunction); + + if (!isRecursiveSubprogramParse) { + // check if function is parsed, hold mutex until scope is left + parsedFuncs->insert(funcParsed, func); + if (funcParsed->second) { + dwarf_printf("(0x%lx) parseSubprogram not parsing children b/c curFunc() marked parsed in parsedFuncs\n", id()); + if(name_result) { + dwarf_printf("\tname is %s\n", curName().c_str()); + } + setParseChild(false); + return true; + } } + // set the current function being parsed and restore old value on return + SetAndRestoreFunction setAndRestore(currentSubprogramFunction, func); + if (name_result && !curName().empty()) { dwarf_printf("(0x%lx) Identified function name as %s\n", id(), curName().c_str()); if (isMangledName()) { @@ -662,7 +664,6 @@ bool DwarfWalker::parseSubprogram(DwarfWalker::inline_t func_type) { } // Only keep pretty names around for inlines, which probably don't have mangled names else { -// printf("(0x%lx) Adding %s as pretty name to inline at 0x%lx\n", id(), curName().c_str(), func->getOffset()); dwarf_printf("(0x%lx) Adding as pretty name to inline\n", id()); func->addPrettyName(curName(), true); } @@ -670,7 +671,6 @@ bool DwarfWalker::parseSubprogram(DwarfWalker::inline_t func_type) { //Collect callsite information for inlined functions. if (func_type == InlinedFunc) { -// cout << "Parsing callsite for (0x" << hex << id() << ") " << curName() << " at " << func->getOffset() << dec << endl; parseCallsite(); } @@ -712,7 +712,11 @@ bool DwarfWalker::parseSubprogram(DwarfWalker::inline_t func_type) { return false; } - parsedFuncs.insert(func); + if (!isRecursiveSubprogramParse) { + // the function is now parsed + funcParsed->second = true; + } + if (func_type == InlinedFunc) { dwarf_printf("End parseSubprogram for inlined func at 0x%p\n", (void*)func->getOffset()); } @@ -721,12 +725,9 @@ bool DwarfWalker::parseSubprogram(DwarfWalker::inline_t func_type) { } void DwarfWalker::setRanges(FunctionBase *func) { - dyn_mutex::unique_lock l(func->ranges_lock); if(func->ranges.empty()) { Address last_low = 0, last_high = 0; -// func->ranges.reserve(rangesSize()); for (auto i = ranges_begin(); i != ranges_end(); i++) { -// cerr << "Adding " << rangesSize() << " ranges\n"; Address low = i->first; Address high = i->second; if (last_low == low && last_high == high) @@ -739,50 +740,11 @@ void DwarfWalker::setRanges(FunctionBase *func) { } } -pair DwarfWalker::parseHighPCLowPC(Dwarf * /*dbg*/, Dwarf_Die entry) -{ - Dwarf_Addr low, high; - int low_result = dwarf_lowpc(&entry, &low); - int high_result = dwarf_highpc(&entry, &high); - bool ok = (low_result == 0) && - (high_result == 0) && - (low != 0) && - (high != 0); - - return make_pair(AddressRange(low, high), ok); -// Dwarf_Attribute hasLow; -// -// Dwarf_Attribute hasHigh; -// std::pair result = make_pair(AddressRange(0,0), false); -// if(dwarf_attr(&entry, DW_AT_low_pc, &hasLow) == NULL) return result; -// if(dwarf_attr(&entry, DW_AT_high_pc, &hasHigh) == NULL) return result; -// -// Address low, high; -// if (!findConstant(DW_AT_low_pc, low, entry, dbg)) return result; -// if (!findConstant(DW_AT_high_pc, high, entry, dbg)) return result; -// Dwarf_Half form = dwarf_whatform(&hasHigh); -// if(form==0) return result; -// -// if(form != DW_FORM_addr) -// { -// high += low; -// } -// // Don't add 0,0; it's not a real range but a sign something went wrong. -// if(low || high) -// { -// dwarf_printf("Lexical block from 0x%lx to 0x%lx\n", low, high); -// result = make_pair(AddressRange(low, high), true); -// } -// return result; -} - -bool DwarfWalker::parseRangeTypes(Dwarf * dbg, Dwarf_Die die) { +bool DwarfWalker::parseRangeTypes(Dwarf_Die die) { dwarf_printf("(0x%lx) Parsing ranges\n", id()); clearRanges(); - std::vector newRanges = getDieRanges(dbg, die, modLow); -// cerr << "parseRangeTypes generating new ranges, size is " << newRanges.size() -// << ", DIE offset is " << die.addr << endl; + std::vector newRanges = getDieRanges(die); for(auto r = newRanges.begin(); r != newRanges.end(); ++r) @@ -792,7 +754,7 @@ bool DwarfWalker::parseRangeTypes(Dwarf * dbg, Dwarf_Die die) { return !newRanges.empty(); } -vector DwarfWalker::getDieRanges(Dwarf * /*dbg*/, Dwarf_Die die, Offset /*range_base*/) +vector DwarfWalker::getDieRanges(Dwarf_Die die) { std::vector newRanges; @@ -805,7 +767,6 @@ vector DwarfWalker::getDieRanges(Dwarf * /*dbg*/, Dwarf_Die die, O if(offset < 0) return std::vector(); if(offset == 0) break; dwarf_printf("Lexical block from 0x%lx to 0x%lx\n", start, end); -// printf("Lexical block from 0x%lx to 0x%lx, offset is %p, %d entries\n", start, end, offset, newRanges.size()); newRanges.push_back(AddressRange(start, end)); } return newRanges; @@ -813,14 +774,23 @@ vector DwarfWalker::getDieRanges(Dwarf * /*dbg*/, Dwarf_Die die, O bool DwarfWalker::parseLexicalBlock() { dwarf_printf("(0x%lx) Parsing lexical block\n", id()); - return parseRangeTypes(dbg(), entry()); + return parseRangeTypes(entry()); +} + +bool DwarfWalker::parseTryBlock() { + dwarf_printf("(0x%lx) Parsing try block ranges\n", id()); + return parseRangeTypes(entry()); +} + +bool DwarfWalker::parseCatchBlock() { + dwarf_printf("(0x%lx) Parsing catch block ranges\n", id()); + return parseRangeTypes(entry()); } bool DwarfWalker::parseCommonBlock() { dwarf_printf("(0x%lx) Parsing common block\n", id()); - std::string commonBlockName; - if (!findDieName(entry(), commonBlockName)) return false; + std::string commonBlockName = die_name(); Symbol* commonBlockVar = findSymbolForCommonBlock(commonBlockName); if(!commonBlockVar) { @@ -836,7 +806,7 @@ Symbol *DwarfWalker::findSymbolForCommonBlock(const string &commonBlockName) { return findSymbolByName(commonBlockName, Symbol::ST_OBJECT); } -boost::shared_ptr DwarfWalker::getCommonBlockType(string &commonBlockName) { +dyncompat::shared_ptr DwarfWalker::getCommonBlockType(string &commonBlockName) { auto commonBlockType = tc()->findVariableType(commonBlockName, Type::share); if(!commonBlockType || !commonBlockType->isCommonType()) { commonBlockType = Type::make_shared( type_id(), commonBlockName ); @@ -867,7 +837,7 @@ bool DwarfWalker::parseVariable() { Variables may have two entries, the second, with a _specification, being the only one with the location. */ - boost::shared_ptr type; + dyncompat::shared_ptr type; if (!findType(type, false)) return false; if(!type) @@ -878,9 +848,7 @@ bool DwarfWalker::parseVariable() { if (!handleSpecification(hasSpecification)) return false; - if (!findName(curName())) - return false; - + curName() = die_name(); removeFortranUnderscore(curName()); /* We'll start with the location, since that's most likely to @@ -892,8 +860,6 @@ bool DwarfWalker::parseVariable() { if (locs.empty()) return true; for (unsigned i=0; i &locs, boost::shared_ptr type) { +bool DwarfWalker::addStaticClassVariable(const vector &locs, dyncompat::shared_ptr type) { if( locs[0].stClass != storageRegOffset ) { dwarf_printf("(0x%lx) Adding variable to an enclosure\n", id()); @@ -949,7 +915,7 @@ bool DwarfWalker::addStaticClassVariable(const vector &locs, b return false; } -void DwarfWalker::createGlobalVariable(const vector &locs, boost::shared_ptr type) { +void DwarfWalker::createGlobalVariable(const vector &locs, dyncompat::shared_ptr type) { /* The typeOffset forms a module-unique type identifier, so the Type look-ups by it rather than name. */ dwarf_printf("(0x%lx) Adding global variable\n", id()); @@ -967,7 +933,7 @@ void DwarfWalker::createGlobalVariable(const vector &locs, boo tc()->addGlobalVariable(type); } -void DwarfWalker::createLocalVariable(const vector &locs, boost::shared_ptr type, +void DwarfWalker::createLocalVariable(const vector &locs, dyncompat::shared_ptr type, Dwarf_Word variableLineNo, const string &fileName) { localVar * newVariable = new localVar(curName(), @@ -1033,14 +999,14 @@ bool DwarfWalker::parseFormalParam() { } /* Acquire the parameter's type. */ - boost::shared_ptr paramType; + dyncompat::shared_ptr paramType; if (!findType(paramType, false)) { dwarf_printf("(0x%lx) param type not acquired\n", id()); return false; } - if (!findName(curName())) return false; + curName() = die_name(); /* We can't do anything with anonymous parameters. */ if (!nameDefined()) { dwarf_printf("(0x%lx) No name associated with formal, returning\n", id()); @@ -1057,7 +1023,7 @@ bool DwarfWalker::parseFormalParam() { } void DwarfWalker::createParameter(const vector &locs, - boost::shared_ptr paramType, Dwarf_Word lineNo, const string &fileName) + dyncompat::shared_ptr paramType, Dwarf_Word lineNo, const string &fileName) { localVar * newParameter = new localVar(curName(), paramType, @@ -1067,8 +1033,6 @@ void DwarfWalker::createParameter(const vector &locs, id(), curName().c_str(), (void*)paramType.get(), paramType->getName().c_str(), - // ((curFunc() && !curFunc()->getAllMangledNames().empty()) ? - //curFunc()->getAllMangledNames()[0].c_str() : ""), (void*)curFunc()); for (unsigned int i = 0; i < locs.size(); ++i) @@ -1085,7 +1049,7 @@ bool DwarfWalker::parseBaseType() { if(!tc()) return false; dwarf_printf("(0x%lx) parseBaseType entry\n", id()); - if (!findName(curName())) return false; + curName() = die_name(); if (!nameDefined()) { dwarf_printf("(0x%lx) No name for type, returning early\n", id()); return true; @@ -1166,10 +1130,10 @@ bool DwarfWalker::parseBaseType() { bool DwarfWalker::parseTypedef() { dwarf_printf("(0x%lx) parseTypedef entry\n", id()); - boost::shared_ptr referencedType; + dyncompat::shared_ptr referencedType; if (!findType(referencedType, true)) return false; - if (!findName(curName())) return false; + curName() = die_name(); if (!nameDefined()) { if (!fixName(curName(), referencedType)) return false; } @@ -1177,94 +1141,149 @@ bool DwarfWalker::parseTypedef() { auto typeDef = tc()->addOrUpdateType( Type::make_shared( type_id(), referencedType, curName()) ); dwarf_printf("(0x%lx) Created type %p / %s for type_id %d, offset 0x%lx, size %u, in TC %p, mod:%s\n", id(), (void*)typeDef.get(), typeDef->getName().c_str(), type_id(), - offset(), typeDef->getSize(), (void*)tc(), mod()->fullName().c_str()); + offset(), typeDef->getSize(), (void*)tc(), mod()->fileName().c_str()); return true; } bool DwarfWalker::parseArray() { - dwarf_printf("(0x%lx) Parsing array\n", id()); - /* Two words about pgf90 arrays. - - Primus: the PGI extensions to DWARF are documented in - '/p/paradyn/doc/External/manuals/pgf90-dwarf-arrays.txt'. + dwarf_printf("(0x%lx) Parsing array\n", id()); - Secundus: we ignore DW_AT_PGI_lbase, DW_AT_PGI_loffset, and DW_AT_PGI_lstride, - even though libdwarf recognizes them, because our type modelling doesn't allow - us to make use of this information. Similarly, in virtually every place where - the Portland Group extends DWARF to allow _form_block attributes encoding location - lists, we ignore them. We should, however, recognize these cases and ignore them - gracefully, that is, without an error. :) - */ + dyncompat::shared_ptr elementType; + if (!findType(elementType, false)) + return false; + if (!elementType) + return false; - boost::shared_ptr elementType = NULL; - if (!findType(elementType, false)) return false; - if (!elementType) return false; + curName() = die_name(); - if (!findName(curName())) return false; + Dwarf_Die e = entry(); - // curName may get overridden by the subrange parsing code. - // TODO: make this part of the context stack. - //std::string nameToUse = curName(); + // The dimensions of an array are stored as subranges in the child DIE + Dwarf_Die child; + int result = dwarf_child(&e, &child); + if (result < 0) { + dwarf_printf("(0x%lx) Error calling dwarf_child\n", id()); + return false; + } + if (result == 1) { + dwarf_printf("(0x%lx) dwarf_child found no subranges for array\n", id()); + return false; + } - /* Find the range(s) of the elements. */ - Dwarf_Die firstRange; - Dwarf_Die e = entry(); - int result = dwarf_child(&e, &firstRange); - if(result != 0) { - dwarf_printf("(0x%lx) parseArray return false as dwarf_child returns 0\n", id()); - return false; + // Find the subranges + // A multidimensional array will have a subrange for each dimension + std::stack> subranges; + do { + auto subrange = parseSubrange(&child); + if (!subrange) { + return false; } -// push(); + // Register the subrange with the type collection + tc()->addOrUpdateType(subrange); - boost::shared_ptr baseType = parseMultiDimensionalArray(&firstRange, - elementType); + subranges.push(std::move(subrange)); + } while (dwarf_siblingof(&child, &child) == 0); -// pop(); + // This should never happen, but it's good to be paranoid + if (subranges.size() == 0) { + dwarf_printf("(0x%lx) No subranges found for array\n", id()); + return false; + } - if (!baseType) { - dwarf_printf("(0x%lx) parseArray returns false as baseArrayType is NULL\n", id()); - return false; - } - auto& baseArrayType = baseType->asArrayType(); - - /* The baseArrayType is an anonymous type with its own typeID. Extract - the information and add an array type for this DIE. */ - std::string baseTypeName = baseArrayType.getBaseType(Type::share)->getName(); - dwarf_printf("(0x%lx) Creating array with base type %s, low bound %lu, high bound %lu, named %s\n", - id(), baseTypeName.c_str(), - baseArrayType.getLow(), - baseArrayType.getHigh(), - curName().c_str()); - tc()->addOrUpdateType( Type::make_shared( type_id(), - baseArrayType.getBaseType(Type::share), - baseArrayType.getLow(), - baseArrayType.getHigh(), - baseTypeName+"[]")); - - /* Don't parse the children again. */ - setParseChild(false); + std::string name{"__array" + std::to_string(offset())}; + + auto convert = [this, &name](dyncompat::shared_ptr t, + dyncompat::shared_ptr base_t) { + auto arr_t = + Type::make_shared(base_t, t->getLow(), t->getHigh(), name); + auto type = tc()->addOrUpdateType(arr_t); + dwarf_printf("(0x%lx) Creating array dimension. ID: %d, %s[%lu:%lu]\n", + id(), type->getID(), name.c_str(), t->getLow(), t->getHigh()); + return type; + }; + + auto make_base_t = [this, &name](dyncompat::shared_ptr t, + dyncompat::shared_ptr base) { + auto arr_t = + Type::make_shared(type_id(), base, t->getLow(), + t->getHigh(), name + "[]"); + auto type = tc()->addOrUpdateType(arr_t); + dwarf_printf("(0x%lx) Creating array. ID: %d, %s[%lu:%lu]\n", + id(), type->getID(), arr_t->getName().c_str(), t->getLow(), t->getHigh()); + return type; + }; + + // Convert the subranges to a Type sequence + dyncompat::shared_ptr base_t; + if(subranges.size() == 1) { + auto cur_subrange = subranges.top(); + subranges.pop(); + base_t = make_base_t(cur_subrange, elementType); + } else { + // The last subrange (i.e., the highest dimension) gets the element type as + // its base type + auto cur_subrange = subranges.top(); + subranges.pop(); + auto base = convert(cur_subrange, elementType); + + // The rest get the subsequent dimension's type as their base types + while (subranges.size() > 1) { + cur_subrange = subranges.top(); + subranges.pop(); + base = convert(cur_subrange, base); + } - return true; + // The first subrange acts as the entry point for the array's type, so it + // needs an explicit `type_id` and different name. + cur_subrange = subranges.top(); + subranges.pop(); + base_t = make_base_t(cur_subrange, base); + } + + /* Don't parse the children again. */ + setParseChild(false); + + return true; } bool DwarfWalker::parseSubrange() { - dwarf_printf("(0x%lx) parseSubrange entry\n", id()); + Dwarf_Die e = entry(); + auto subrange = parseSubrange(&e); - std::string loBound; - std::string hiBound; - parseSubrangeAUX(entry(), loBound, hiBound); + dyncompat::shared_ptr rangeType = tc()->addOrUpdateType(subrange); + dwarf_printf("(0x%lx) Created subrange type: ID 0x%d, pointer %p (tc %p)\n", id(), + rangeType->getID(), (void *)rangeType.get(), (void *)tc()); - return true; + return true; } bool DwarfWalker::parseEnum() { if(!tc()) return false; dwarf_printf("(0x%lx) parseEnum entry\n", id()); - if (!findName(curName())) return false; - //setEnum(tc()->addOrUpdateType( Type::make_shared( type_id(), "enum " + curName()))); - setEnum(tc()->addOrUpdateType( Type::make_shared( type_id(), curName()))); + + dyncompat::shared_ptr underlying_type{}; + if (!findType(underlying_type, false)) { + dwarf_printf("(0x%lx) type not found\n", id()); + return false; + } + + curName() = die_name(); + + // Handle C++ scoped enums (i.e., 'enum class') + auto type = [this, &underlying_type]() { + Dwarf_Attribute valueAttr{}; + Dwarf_Die e = entry(); + if(dwarf_attr(&e, DW_AT_enum_class, & valueAttr)) { + return Type::make_shared(underlying_type, curName(), type_id(), typeEnum::scoped_t{}); + } + return Type::make_shared(underlying_type, curName(), type_id()); + }(); + + setEnum(tc()->addOrUpdateType(type)); + + dwarf_printf("(0x%lx) end parseEnum\n", id()); return true; } @@ -1272,7 +1291,7 @@ bool DwarfWalker::parseInheritance() { dwarf_printf("(0x%lx) parseInheritance entry\n", id()); /* Acquire the super class's type. */ - boost::shared_ptr superClass = NULL; + dyncompat::shared_ptr superClass = NULL; if (!findType(superClass, false)) return false; if (!superClass) return false; @@ -1301,7 +1320,7 @@ bool DwarfWalker::parseStructUnionClass() { return false; } - if (!findName(curName())) return false; + curName() = die_name(); dwarf_printf("(0x%lx) Struct/Union/Class name from dwarf: %s\n", id(), curName().c_str()); if (!nameDefined()) { @@ -1332,7 +1351,7 @@ bool DwarfWalker::parseStructUnionClass() { unsigned size=0; findSize(size); - boost::shared_ptr containingType; + dyncompat::shared_ptr containingType; switch ( tag() ) { case DW_TAG_structure_type: case DW_TAG_class_type: @@ -1342,7 +1361,7 @@ bool DwarfWalker::parseStructUnionClass() { containingType = tc()->addOrUpdateType(ts); dwarf_printf("(0x%lx) Created type %p / %s for type_id %d, offset 0x%lx, size %u, in TC %p, mod:%s\n", id(), (void*)containingType.get(), containingType->getName().c_str(), type_id(), - offset(), containingType->getSize(), (void*)tc(), mod()->fullName().c_str()); + offset(), containingType->getSize(), (void*)tc(), mod()->fileName().c_str()); break; } case DW_TAG_union_type: @@ -1352,7 +1371,7 @@ bool DwarfWalker::parseStructUnionClass() { containingType = tc()->addOrUpdateType(tu); dwarf_printf("(0x%lx) Created type %p / %s for type_id %d, offset 0x%lx, size %u, in TC %p, mod:%s\n", id(), (void*)containingType.get(), containingType->getName().c_str(), type_id(), - offset(), containingType->getSize(), (void*)tc(), mod()->fullName().c_str()); + offset(), containingType->getSize(), (void*)tc(), mod()->fileName().c_str()); break; } default: @@ -1372,14 +1391,14 @@ bool DwarfWalker::parseStructUnionClass() { bool DwarfWalker::parseEnumEntry() { dwarf_printf("(0x%lx) parseEnumEntry entry\n", id()); - std::string name; - if (!findName(name)) return false; + std::string name = die_name(); + + auto value = findConstValue(); + if(!value) { return false; } - long value = 0; - bool valid; - if (!findValue(value, valid)) return false; + curEnum()->asEnumType().addConstant(name, *value); - curEnum()->asEnumType().addConstant(name, value); + dwarf_printf("(0x%lx) end parseEnumEntry\n", id()); return true; } @@ -1387,16 +1406,13 @@ bool DwarfWalker::parseMember() { dwarf_printf("(0x%lx) parseMember entry\n", id()); if (!curEnclosure()) return false; - boost::shared_ptr memberType = NULL; + dyncompat::shared_ptr memberType = NULL; if (!findType(memberType, false)) return false; if (!memberType) return false; - if (!findName(curName())) return false; + curName() = die_name(); - long value; - bool hasValue; - if (!findValue(value, hasValue)) return false; - if (hasValue) { + if (findConstValue()) { if(!nameDefined()) return false; dwarf_printf("(0x%lx) member is a named constant, forwarding to parseConstant\n", id()); return parseConstant(); @@ -1444,10 +1460,10 @@ bool DwarfWalker::parseMember() { bool DwarfWalker::parseConstPackedVolatile() { dwarf_printf("(0x%lx) parseConstPackedVolatile entry\n", id()); - boost::shared_ptr type = NULL; + dyncompat::shared_ptr type = NULL; if (!findType(type, true)) return false; - if (!findName(curName())) return false; + curName() = die_name(); if (!nameDefined()) { dwarf_printf("(0x%lx) parseConstPackedVolatile fixName\n", id()); if (!fixName(curName(), type)) return false; @@ -1460,21 +1476,17 @@ bool DwarfWalker::parseConstPackedVolatile() { bool DwarfWalker::parseTypeReferences() { dwarf_printf("(0x%lx) parseTypeReferences entry\n", id()); - boost::shared_ptr typePointedTo = NULL; + dyncompat::shared_ptr typePointedTo = NULL; if (!findType(typePointedTo, true)) { dwarf_printf("(0x%lx) type not found\n", id()); return false; } - if (!findName(curName())) - { - dwarf_printf("(0x%lx) name not found\n", id()); - return false; - } + curName() = die_name(); Dwarf_Die e = entry(); - boost::shared_ptr indirectType; + dyncompat::shared_ptr indirectType; switch ( tag() ) { case DW_TAG_subroutine_type: indirectType = tc()->addOrUpdateType(Type::make_shared( @@ -1486,15 +1498,28 @@ bool DwarfWalker::parseTypeReferences() { type_id(), typePointedTo, curName())); dwarf_printf("(0x%lx) Created type %p / %s for type_id %d, offset 0x%lx, size %u, in TC %p, mod:%s\n", id(), (void*)indirectType.get(), indirectType->getName().c_str(), type_id(), - offset(), indirectType->getSize(), (void*)tc(), mod()->fullName().c_str()); + offset(), indirectType->getSize(), (void*)tc(), mod()->fileName().c_str()); break; case DW_TAG_reference_type: + if(!nameDefined()){ + curName() = "&"; + } indirectType = tc()->addOrUpdateType(Type::make_shared( type_id(), typePointedTo, curName())); dwarf_printf("(0x%lx) Created type %p / %s for type_id %d, offset 0x%lx, size %u, in TC %p\n", id(), (void*)indirectType.get(), indirectType->getName().c_str(), type_id(), offset(), indirectType->getSize(), (void*)tc()); break; + case DW_TAG_rvalue_reference_type: + if(!nameDefined()) { + curName() = "&&"; + } + indirectType = tc()->addOrUpdateType(Type::make_shared( + type_id(), typePointedTo, curName(), typeRef::rvalue_t{})); + dwarf_printf("(0x%lx) Created type %p / %s for type_id %d, offset 0x%lx, size %u, in TC %p\n", id(), + (void*)indirectType.get(), indirectType->getName().c_str(), type_id(), + offset(), indirectType->getSize(), (void*)tc()); + break; default: dwarf_printf("(0x%lx) Warning: nothing done for tag 0x%x, dwarf_tag(): 0x%x\n", id(), tag(), (unsigned int)dwarf_tag(&e)); @@ -1514,7 +1539,6 @@ bool DwarfWalker::hasDeclaration(bool &isDecl) { bool DwarfWalker::findTag() { Dwarf_Die e = entry(); Dwarf_Half dieTag = dwarf_tag(&e); - //DWARF_FAIL_RET(dieTag); setTag(dieTag); return true; } @@ -1576,48 +1600,67 @@ bool DwarfWalker::handleSpecification(bool &hasSpec) { return true; } -bool DwarfWalker::findDieName(Dwarf_Die die, std::string &name) -{ - auto cname = dwarf_diename(&die); - if (cname == 0) { - name = std::string(); - return true; - } - - name = cname; - return true; -} - -bool DwarfWalker::findName(std::string &name) { - if (!findDieName(specEntry(), name)) return false; +std::string DwarfWalker::die_name() { + auto name = DwarfDyninst::die_name(specEntry()); dwarf_printf("(0x%lx) Found name %s.\n", id(), name.c_str()); - return true; + return name; } bool DwarfWalker::findFuncName() { - dwarf_printf("(0x%lx) Checking for linkage name\n", id()); - /* Prefer linkage names. */ + dwarf_printf("(0x%lx) Checking for function name\n", id()); - Dwarf_Attribute linkageNameAttr; Dwarf_Die e = entry(); - auto status = dwarf_attr_integrate(&e, DW_AT_MIPS_linkage_name, &linkageNameAttr); - - if (status == 0) - status = dwarf_attr_integrate(&e, DW_AT_linkage_name, &linkageNameAttr); - if ( status != 0 ) { // previously ==1 - const char *dwarfName = dwarf_formstring(&linkageNameAttr); - //DWARF_FAIL_RET(dwarfName); - if(dwarfName==NULL) return false; - curName() = dwarfName; - setMangledName(true); - dwarf_printf("(0x%lx) Found DW_AT_linkage_name of %s, using\n", id(), curName().c_str()); - return true; + + // Does this function have a linkage name? + { + Dwarf_Attribute linkageNameAttr{}; + Dwarf_Attribute *attr = dwarf_attr_integrate(&e, DW_AT_linkage_name, &linkageNameAttr); + if (attr) { + char const* dwarfName = dwarf_formstring(attr); + if(!dwarfName) { + dwarf_printf("(0x%lx) Found 'DW_AT_linkage_name', but formstring is empty\n", id()); + return false; + } + curName() = dwarfName; + setMangledName(true); + dwarf_printf("(0x%lx) Found DW_AT_linkage_name of %s\n", id(), curName().c_str()); + return true; + } } - dwarf_printf("(0x%lx) DW_AT_linkage_name name not found\n", id()); + // Is this an inlined function? + { + if(dwarf_hasattr(&e, DW_AT_inline)) { + // Find the 'DW_AT_name' for this DIE. Do not traverse this as an abstract + // instance root (if it is one)- i.e., don't use dwarf_attr_integrate here. + Dwarf_Attribute nameAttr{}; + Dwarf_Attribute *res = dwarf_attr(&e, DW_AT_name, &nameAttr); + if(!res) { + dwarf_printf("(0x%lx) Found an inlined subroutine, but has no 'DW_AT_name'\n", id()); + return false; + } + char const* dwarfName = dwarf_formstring(&nameAttr); + if(!dwarfName) { + dwarf_printf("(0x%lx) Found an inlined subroutine, but formstring is empty\n", id()); + return false; + } + curName() = dwarfName; + + // Section 2.15 of the DWARF5 spec suggests that DW_AT_name should be the name as it + // appears in the source- not mangled. + setMangledName(false); + + dwarf_printf("(0x%lx) Found inline DW_AT_name '%s'\n", id(), curName().c_str()); + return true; + } + } + + // Assume the name is the unmangled name associated with the current DIE, if any + curName() = die_name(); setMangledName(false); - return findDieName(entry(), curName()); + dwarf_printf("(0x%lx) No explicit function name found; using most-recently found name '%s'\n", id(), curName().c_str()); + return true; } std::vector& DwarfParseActions::getFramePtrRefForInit() @@ -1630,7 +1673,7 @@ std::vector& DwarfParseActions::getFramePtrRefForInit() bool DwarfWalker::getFrameBase() { dwarf_printf("(0x%lx) Checking for frame pointer information\n", id()); - boost::unique_lock l(curFunc()->getFramePtrLock()); + dyncompat::unique_lock l(curFunc()->getFramePtrLock()); std::vector &funlocs = getFramePtrRefForInit(); if (!funlocs.empty()) { DWARF_CHECK_RET(false); @@ -1643,24 +1686,15 @@ bool DwarfWalker::getFrameBase() { return true || !funlocs.empty(); // johnmc added true } -bool DwarfWalker::getReturnType(bool hasSpecification, boost::shared_ptr&returnType) { +bool DwarfWalker::getReturnType(dyncompat::shared_ptr&returnType) { dwarf_printf("(0x%lx) In getReturnType().\n", id()); Dwarf_Attribute typeAttribute; Dwarf_Attribute* status = 0; bool is_info = true; - Dwarf_Die e = specEntry(); - if (hasSpecification) { - //is_info = dwarf_get_die_infotypes_flag(specEntry()); - is_info = !dwarf_hasattr_integrate(&e, DW_TAG_type_unit); - status = dwarf_attr( &e, DW_AT_type, &typeAttribute); - } - if (!hasSpecification || (status == 0)) { - //is_info = dwarf_get_die_infotypes_flag(entry()); - e = entry(); - is_info = !dwarf_hasattr_integrate(&e, DW_TAG_type_unit); - status = dwarf_attr(&e, DW_AT_type, &typeAttribute); - } + Dwarf_Die e = entry(); + is_info = !dwarf_hasattr_integrate(&e, DW_TAG_type_unit); + status = dwarf_attr(&e, DW_AT_type, &typeAttribute); if ( status == 0) { dwarf_printf("(0x%lx) Return type is void\n", id()); @@ -1676,7 +1710,7 @@ bool DwarfWalker::getReturnType(bool hasSpecification, boost::shared_ptr&r // I'm not sure how the provided fieldListType is different from curEnclosure(), // but that's the way the code was structured and it was working. -bool DwarfWalker::addFuncToContainer(boost::shared_ptr returnType) { +bool DwarfWalker::addFuncToContainer(dyncompat::shared_ptr returnType) { /* Using the mangled name allows us to distinguish between overridden functions, but confuses the tests. Since Type uses vectors to hold field names, however, duplicate -- demangled names -- are OK. */ @@ -1701,21 +1735,14 @@ bool DwarfWalker::isStaticStructMember(std::vector &locs, bool // if parsing a struct-member which is not a regular member (i.e. not with an offset) if (curEnclosure()->getDataClass() == dataStructure && locs.size() == 0) { - long value; - bool hasValue; - if (!findValue(value, hasValue)) return false; - - // and, if it is not a constant, then it must be a static field member - if (!hasValue) { - isStatic = true; - return true; - } + // and it is not a constant, then it must be a static field member + isStatic = !findConstValue(); } return true; } -bool DwarfWalker::findType(boost::shared_ptr&type, bool defaultToVoid) { +bool DwarfWalker::findType(dyncompat::shared_ptr&type, bool defaultToVoid) { if(!tc()) return false; // Do *not* return true unless type is actually usable. @@ -1757,7 +1784,6 @@ bool DwarfWalker::findDieOffset(Dwarf_Attribute attr, Dwarf_Off &offset) { auto ret_p = dwarf_formref_die(&attr, &die); if(!ret_p) return false; offset = dwarf_dieoffset(&die); - //if(form==DW_FORM_GNU_ref_alt) is_sup = true; return true; } /* Then there's DW_FORM_sec_offset which refer other sections, or @@ -1771,7 +1797,7 @@ bool DwarfWalker::findDieOffset(Dwarf_Attribute attr, Dwarf_Off &offset) { } bool DwarfWalker::findAnyType(Dwarf_Attribute typeAttribute, - bool is_info, boost::shared_ptr&type) + bool is_info, dyncompat::shared_ptr&type) { /* If this is a ref_sig8, look for the type elsewhere. */ Dwarf_Half form = dwarf_whatform(&typeAttribute); @@ -1818,7 +1844,7 @@ bool DwarfWalker::findAnyType(Dwarf_Attribute typeAttribute, } dwarf_printf("(0x%lx) type pointer %p / name:%s, type_id %d, tc():%p, mod: %s, specificType:%s\n", - id(), (void*)type.get(), type->getName().c_str(), type_id, (void*)tc(), mod()->fullName().c_str(), type->specificType().c_str()); + id(), (void*)type.get(), type->getName().c_str(), type_id, (void*)tc(), mod()->fileName().c_str(), type->specificType().c_str()); return true; } @@ -1833,7 +1859,7 @@ bool DwarfWalker::getLineInformation(Dwarf_Word &variableLineNo, if (status != 0) { StringTablePtr files = srcFiles(); - boost::unique_lock l(files->lock); + dyncompat::unique_lock l(files->lock); Dwarf_Word fileNameDeclVal; DWARF_FAIL_RET(dwarf_formudata(&fileDeclAttribute, &fileNameDeclVal)); if (fileNameDeclVal >= files->size() || fileNameDeclVal <= 0) { @@ -1841,7 +1867,7 @@ bool DwarfWalker::getLineInformation(Dwarf_Word &variableLineNo, fileNameDeclVal, files->size()); return false; } - fileName = ((files->get<0>())[fileNameDeclVal]).str; + fileName = (*files)[fileNameDeclVal].str; } else { return true; @@ -1907,7 +1933,7 @@ bool DwarfWalker::decodeLocationList(Dwarf_Half attr, offset = dwarf_getlocations(&locationAttribute, offset, &basep, &start, &end, &exprs, &exprlen); if(offset==-1){ - cerr << "err message: " << dwarf_errmsg(dwarf_errno()) << endl; + dwarf_printf("err message: %s\n", dwarf_errmsg(dwarf_errno())); return false; } if(offset==0) break; @@ -1949,65 +1975,20 @@ bool DwarfWalker::checkForConstantOrExpr(Dwarf_Half /*attr*/, return true; } -bool DwarfWalker::findString(Dwarf_Half attr, - string &str) -{ - Dwarf_Half form; - Dwarf_Attribute strattr; - +dyncompat::optional DwarfWalker::find_call_file() { Dwarf_Die e = entry(); - if (attr == DW_AT_call_file || attr == DW_AT_decl_file) { - unsigned long line_index; - bool result = findConstant(attr, line_index, &e, dbg()); - if (!result) - return false; - StringTablePtr strs = mod()->getStrings(); - boost::unique_lock l(strs->lock); - if (line_index >= strs->size()) { - dwarf_printf("Dwarf error reading line index %lu from srcFiles(%p) of size %lu\n", - line_index, (void*)strs.get(), strs->size()); - return false; - } - // cout << "findString found " << (*srcFiles())[line_index].str << " at srcFiles[" << line_index << "] for " << mod()->fileName() << endl; - str = (*srcFiles())[line_index].str; - return true; - } - auto ret_p = dwarf_attr(&e, attr, &strattr); - if(!ret_p) return false; - form = dwarf_whatform(&strattr); - if (form != 0) { - return false; - } - - bool result; - switch (form) { - case DW_FORM_string: - { - const char *s = dwarf_formstring(&strattr); - if(!s) return false; - // cout << "findString found " << s << " in DW_FORM_string" << endl; - str = s; - result = true; - break; - } - case DW_FORM_block: - case DW_FORM_block1: - case DW_FORM_block2: - case DW_FORM_block4: - { - Dwarf_Block *block = NULL; - DWARF_FAIL_RET(dwarf_formblock(&strattr, block)); - str = (char *) block->data; - // cout << "findString found " << str << " in DW_FORM_block" << endl; - result = !str.empty(); - break; - } - default: - dwarf_printf("(0x%lx) Warning: string form not used 0x%x\n", id(), (int) form); - result = false; - break; + unsigned long line_index; + bool result = findConstant(DW_AT_call_file, line_index, &e, dbg()); + if (!result) + return {}; + StringTablePtr strs = mod()->getStrings(); + dyncompat::unique_lock l(strs->lock); + if (line_index >= strs->size()) { + dwarf_printf("Dwarf error reading line index %lu from srcFiles(%p) of size %lu\n", + line_index, (void*)strs.get(), strs->size()); + return {}; } - return result; + return (*srcFiles())[line_index].str; } bool DwarfWalker::findConstant(Dwarf_Half attr, Address &value, Dwarf_Die *entry, Dwarf * /*dbg*/) { @@ -2132,31 +2113,35 @@ bool DwarfWalker::findVisibility(visibility_t &visibility) { case DW_ACCESS_protected: visibility = visProtected; break; case DW_ACCESS_private: visibility = visPrivate; break; default: - //bperr ( "Uknown visibility, ignoring.\n" ); break; - } /* end visibility switch */ + } return true; } -bool DwarfWalker::findValue(long &value, bool &valid) { - Dwarf_Attribute valueAttr; +dyncompat::optional DwarfWalker::findConstValue() { + dwarf_printf("(0x%lx) findConstValue entry\n", id()); + + Dwarf_Attribute valueAttr{}; Dwarf_Die e = entry(); - auto status = dwarf_attr(&e, DW_AT_const_value, & valueAttr); - if (status == 0) { - valid = false; - return true; + // This also applies to constexpr objects (i.e., DW_AT_const_expr) + if(!dwarf_attr(&e, DW_AT_const_value, & valueAttr)) { + dwarf_printf("No const value found\n"); + return {}; } Dwarf_Sword enumValue; + if(dwarf_formsdata(&valueAttr, &enumValue) != 0) { + dwarf_printf("ERROR: dwarf_formsdata error for entry %p\n", static_cast(&e)); + return {}; + } - DWARF_FAIL_RET(dwarf_formsdata(&valueAttr, &enumValue)); + dwarf_printf("Found value '%ld'\n", static_cast(enumValue)); - value = enumValue; - valid = true; + dwarf_printf("(0x%lx) end findConstValue\n", id()); - return true; + return enumValue; } bool DwarfWalker::fixBitFields(std::vector &locs, @@ -2187,11 +2172,11 @@ bool DwarfWalker::fixBitFields(std::vector &locs, if (locs.size()) locs[0].frameOffset *= 8; size *= 8; - } /* end if not a bit field member. */ + } return true; } -bool DwarfWalker::fixName(std::string &name, boost::shared_ptr type) { +bool DwarfWalker::fixName(std::string &name, dyncompat::shared_ptr type) { switch(tag()){ case DW_TAG_const_type: name = std::string("const ") + type->getName(); @@ -2214,240 +2199,89 @@ void DwarfWalker::removeFortranUnderscore(std::string &name) { supportedLanguages lang = mod()->language(); if ((lang != lang_Fortran) && - (lang != lang_CMFortran) && - (lang != lang_Fortran_with_pretty_debug)) return; + (lang != lang_CMFortran)) return; if (name[name.length()-1] == '_') { name = name.substr(0, name.length()-1); } } -bool DwarfWalker::parseSubrangeAUX(Dwarf_Die entry, - std::string &loBound, - std::string &hiBound) { - dwarf_printf("(0x%lx) Parsing subrange /w/ auxiliary function\n", id()); - loBound = "{unknown or default}"; - hiBound = "{unknown or default}"; - - /* Set the default lower bound, if we know it. */ - switch ( mod()->language() ) { - case lang_Fortran: - case lang_Fortran_with_pretty_debug: - case lang_CMFortran: - loBound = "1"; - break; - case lang_C: - case lang_CPlusPlus: - loBound = "0"; - break; - default: - break; - } /* end default lower bound switch */ - - /* Look for the lower bound. */ - Dwarf_Attribute lowerBoundAttribute; - //bool is_info = dwarf_get_die_infotypes_flag(entry); - bool is_info = !dwarf_hasattr_integrate(&entry, DW_TAG_type_unit); - auto status = dwarf_attr( &entry, DW_AT_lower_bound, & lowerBoundAttribute); - - if ( status != 0 ) { - if (!decipherBound(lowerBoundAttribute, is_info, loBound )) return false; - } /* end if we found a lower bound. */ - - /* Look for the upper bound. */ - Dwarf_Attribute upperBoundAttribute; - status = dwarf_attr( &entry, DW_AT_upper_bound, & upperBoundAttribute); - - if ( status == 0 ) { - status = dwarf_attr( &entry, DW_AT_count, & upperBoundAttribute); - } - - if ( status != 0 ) { - if (!decipherBound(upperBoundAttribute, is_info, hiBound )) return false; - } /* end if we found an upper bound or count. */ - - /* Construct the range type. */ - if (!findName(curName())) { - dwarf_printf("cannot find subrange name %s\n", curName().c_str()); - return false; - } - if (!nameDefined()) { - curName() = "{anonymousRange}"; - } +dyncompat::shared_ptr DwarfWalker::parseSubrange(Dwarf_Die *entry) { + const auto subrange_id = dwarf_dieoffset(entry) - this->compile_offset; + dwarf_printf("(0x%lx) parseSubrange entry for <0x%lx>\n", id(), subrange_id); - Dwarf_Off subrangeOffset = dwarf_dieoffset(&entry); - //DWARF_ERROR_RET(subrangeOffset); - typeId_t type_id = get_type_id(subrangeOffset, is_info, false); + dyncompat::optional upper_bound, lower_bound; - errno = 0; - unsigned long low_conv = strtoul(loBound.c_str(), NULL, 10); - if (errno) { - low_conv = LONG_MIN; + /* An array can have DW_TAG_subrange_type or DW_TAG_enumeration_type + children instead that give the size of each dimension. */ + switch (dwarf_tag(entry)) { + case DW_TAG_subrange_type: { + namespace dw = Dyninst::DwarfDyninst; + auto bounds = dwarf_subrange_bounds(entry); + if (!bounds.lower || !bounds.upper) { + dwarf_printf("parseSubrange failed, error finding range bounds\n"); + return nullptr; } - errno = 0; - unsigned long hi_conv = strtoul(hiBound.c_str(), NULL, 10); - if (errno) { - hi_conv = LONG_MAX; + if (!bounds.lower.value) { + // dwarf_subrange_bounds will try dwarf_default_lower_bound for the + // current DIE. If we got here, that didn't work, so try using the one + // Dyninst parsed. + switch (mod()->language()) { + case lang_Fortran: + case lang_CMFortran: + bounds.lower.value = 1; + break; + default: + // Assume all non-Fortran languages use 0 + bounds.lower.value = 0; + break; + } } - dwarf_printf("(0x%lx) Adding subrange type: id %d, low %lu, high %lu, named %s\n", - id(), type_id, - low_conv, hi_conv, curName().c_str()); - boost::shared_ptr rangeType = tc()->addOrUpdateType( - Type::make_shared( type_id, 0, low_conv, hi_conv, curName())); - dwarf_printf("(0x%lx) Subrange has pointer %p (tc %p)\n", id(), (void*)rangeType.get(), (void*)tc()); - return true; -} - -boost::shared_ptr DwarfWalker::parseMultiDimensionalArray(Dwarf_Die *range, - boost::shared_ptr elementType) -{ - char buf[32]; - /* Get the (negative) typeID for this range/subarray. */ - //Dwarf_Off dieOffset = dwarf_dieoffset(&range); - - /* Determine the range. */ - std::string loBound; - std::string hiBound; - if (!parseSubrangeAUX(*range, loBound, hiBound)) { - dwarf_printf("parseMultiDimensionalArray failed, cannot find array range\n"); - return NULL; + upper_bound = bounds.upper.value; + lower_bound = bounds.lower.value; + } break; + case DW_TAG_enumeration_type: { + // If there is an enum value, then it represents the total number of + // elements in the array. We take the bounds to be [0, upper-1) + auto upper = dwarf_subrange_length_from_enum(entry); + if (!upper) { + dwarf_printf("parseSubrange failed, error finding length from enum\n"); + return nullptr; } - - - - /* Does the recursion continue? */ - Dwarf_Die nextSibling; - int status = dwarf_siblingof(range, &nextSibling); - DWARF_CHECK_RET_VAL(status == -1, NULL); - - snprintf(buf, 31, "__array%d", (int) offset()); - - if ( status == 1 ) { - /* Terminate the recursion by building an array type out of the elemental type. - Use the negative dieOffset to avoid conflicts with the range type created - by parseSubRangeDIE(). */ - // N.B. I'm going to ignore the type id, and just create an anonymous type here - std::string aName = buf; - auto innermostType = tc()->addOrUpdateType( - Type::make_shared( elementType, - atoi(loBound.c_str()), - atoi(hiBound.c_str()), - aName )); - /* dwarf_printf("\t(0x%lx)parseMultiDimentionalArray status 1, typ %p, innermosttype %p, lower bound %d, upper bound %d\n", id(), typ, innermostType, innermostType->asArrayType().getLow(), innermostType->asArrayType().getHigh()); */ - return innermostType; - } /* end base-case of recursion. */ - - /* If it does, build this array type out of the array type returned from the next recusion. */ - boost::shared_ptr innerType = parseMultiDimensionalArray( &nextSibling, elementType); - if(!innerType) { - dwarf_printf("\tparseMultiDimensionalArray return Null because innerType == NULL\n"); - return NULL; + if (upper) { + upper.value.get() -= 1; } - // same here - type id ignored jmo - std::string aName = buf; - auto outerType = tc()->addOrUpdateType( - Type::make_shared( innerType, - atoi(loBound.c_str()), atoi(hiBound.c_str()), aName)); - dwarf_printf("\t(0x%lx)parseMultiDimentionalArray status 0, lower bound %lu, upper bound %lu\n",id(), outerType->asArrayType().getLow(), outerType->asArrayType().getHigh()); - return outerType; -} /* end parseMultiDimensionalArray() */ - -bool DwarfWalker::decipherBound(Dwarf_Attribute boundAttribute, bool /*is_info*/, - std::string &boundString ) -{ - Dwarf_Half boundForm = dwarf_whatform(&boundAttribute); - if(!boundForm) return false; - - switch( boundForm ) { - case DW_FORM_data1: - case DW_FORM_data2: - case DW_FORM_data4: - case DW_FORM_data8: - case DW_FORM_udata: - { - dwarf_printf("(0x%lx) Decoding form %d with formudata\n", - id(), boundForm); - - Dwarf_Word constantBound; - DWARF_FAIL_RET(dwarf_formudata( &boundAttribute, & constantBound)); - char bString[40]; - sprintf(bString, "%llu", (unsigned long long)constantBound); - boundString = bString; - return true; - } break; - - case DW_FORM_sdata: - { - dwarf_printf("(0x%lx) Decoding form %d with formsdata\n", - id(), boundForm); - - Dwarf_Sword constantBound; - DWARF_FAIL_RET(dwarf_formsdata( &boundAttribute, & constantBound)); - char bString[40]; - sprintf(bString, "%lld", (long long)constantBound); - boundString = bString; - return true; - } break; - - case DW_FORM_ref_addr: - case DW_FORM_ref1: - case DW_FORM_ref2: - case DW_FORM_ref4: - case DW_FORM_ref8: - case DW_FORM_ref_udata: - { - /* Acquire the referenced DIE. */ - //Dwarf_Off boundOffset; - Dwarf_Die boundEntry; - auto ret_p = dwarf_formref_die(&boundAttribute, &boundEntry); - if(!ret_p) return false; - - /* Does it have a name? */ - if (findDieName(boundEntry, boundString) - && !boundString.empty()) - return true; - - /* Does it describe a nameless constant? */ - Dwarf_Attribute constBoundAttribute; - auto status = dwarf_attr(&boundEntry, DW_AT_const_value, &constBoundAttribute); + lower_bound = 0; + upper_bound = upper.value; + } + } - if ( status != 0 ) { - Dwarf_Word constBoundValue; - DWARF_FAIL_RET(dwarf_formudata( &constBoundAttribute, & constBoundValue)); + // Don't set the name until we're guaranteed a subrange was found + curName() = die_name(); + if (!nameDefined()) { + curName() = "{anonymousRange}"; + } - char bString[40]; - sprintf(bString, "%lu", (unsigned long)constBoundValue); - boundString = bString; + Dwarf_Off subrangeOffset = dwarf_dieoffset(entry); + bool is_info = !dwarf_hasattr_integrate(entry, DW_TAG_type_unit); + typeId_t type_id = get_type_id(subrangeOffset, is_info, false); - return true; - } + // `typeSubrange` expects numeric values for the bounds + DYNINST_DIAGNOSTIC_BEGIN_SUPPRESS_MAYBE_UNINITIALIZED + auto range = Type::make_shared( + type_id, 0, lower_bound.value_or(LONG_MIN), + upper_bound.value_or(LONG_MAX), curName()); + DYNINST_DIAGNOSTIC_END_SUPPRESS_MAYBE_UNINITIALIZED - return false; - } break; - case DW_FORM_block: - case DW_FORM_block1: - { - /* PGI extends DWARF to allow some bounds to be location lists. Since we can't - do anything sane with them, ignore them. */ - // Dwarf_Op* * locationList; - // Dwarf_Sword listLength; - // status = dwarf_loclist( boundAttribute, & locationList, & listLength, NULL ); - boundString = "{PGI extension}"; - return false; - } break; + dwarf_printf( + "(0x%lx) Parsed subrange: id %d, low %lu, high %lu, named %s\n", + id(), type_id, range->getLow(), range->getHigh(), curName().c_str()); - default: - //bperr ( "Invalid bound form 0x%x\n", boundForm ); - boundString = "{invalid bound form}"; - return false; - break; - } /* end boundForm switch */ - return true; + return range; } - bool DwarfWalker::decodeExpression(Dwarf_Attribute &locationAttribute, std::vector &locs) { @@ -2467,10 +2301,8 @@ bool DwarfWalker::decodeExpression(Dwarf_Attribute &locationAttribute, ld.dwarfOp = exprs; ld.opLen = exprlen; locDescs.push_back(ld); - //if(start==0 && end==-1) break; }while(offset > 0); - //assert(locDescs.size()!=1); bool ret = decodeLocationListForStaticOffsetOrAddress(locDescs, 1, locs); return ret; } @@ -2573,9 +2405,10 @@ bool DwarfWalker::decodeLocationListForStaticOffsetOrAddress( } } else { - dwarf_printf("(0x%lx) Using lexical range, shifted by module low\n", id()); - loc.lowPC = location->ld_lopc + base; - loc.hiPC = location->ld_hipc + base; + dwarf_printf("(0x%lx) Using lexical range\n", id()); + + loc.lowPC = location->ld_lopc; + loc.hiPC = location->ld_hipc; dwarf_printf("(0x%lx) valid over range 0x%lx to 0x%lx\n", id(), loc.lowPC, loc.hiPC); @@ -2585,19 +2418,9 @@ bool DwarfWalker::decodeLocationListForStaticOffsetOrAddress( /* decode successful */ return !locs.empty(); -} /* end decodeLocationListForStaticOffsetOrAddress() */ +} -void DwarfWalker::deallocateLocationList( Dwarf_Op ** /*locationList*/, - Dwarf_Sword listLength ) -{ - for( int i = 0; i < listLength; i++ ) { - //dwarf_dealloc( dbg(), locationList[i]->ld_s, DW_DLA_LOC_BLOCK ); - //dwarf_dealloc( dbg(), locationList[i], DW_DLA_LOCDESC ); - } - //dwarf_dealloc( dbg(), locationList, DW_DLA_LIST ); -} /* end deallocateLocationList() */ - void DwarfWalker::setEntry(Dwarf_Die entry) { DwarfParseActions::setEntry(entry); DwarfParseActions::setSpecEntry(entry); @@ -2644,7 +2467,7 @@ void DwarfParseActions::clearFunc() { unsigned int DwarfWalker::getNextTypeId(){ - static boost::atomic next_type_id(1); + static dyncompat::atomic next_type_id(1); unsigned int val = next_type_id.fetch_add(1); return val; } @@ -2664,7 +2487,7 @@ typeId_t DwarfWalker::get_type_id(Dwarf_Off offset, bool is_info, bool is_sup) type_map::accessor a; type_key tk{offset, is_sup, mod()}; type_ids.insert(a, make_pair(tk, val)); - dwarf_printf("(0x%lx) type_id %u, key created {0x%lx,%s,mod: %s}\n", id(),val,offset,is_sup?"sup":"not sup", mod()->fullName().c_str()); + dwarf_printf("(0x%lx) type_id %u, key created {0x%lx,%s,mod: %s}\n", id(),val,offset,is_sup?"sup":"not sup", mod()->fileName().c_str()); } return val; @@ -2696,8 +2519,7 @@ void DwarfWalker::findAllSig8Types() if(!dwarf_offdie_types(dbg(), cu_off + cu_header_length, ¤t_cu_die)) continue; - Dwarf_Half moduleTag = dwarf_tag(¤t_cu_die); - if (moduleTag == DW_TAG_partial_unit) { + if (DwarfDyninst::is_partial_unit(current_cu_die)) { continue; } parseModuleSig8(false); @@ -2712,8 +2534,7 @@ void DwarfWalker::findAllSig8Types() { if(!dwarf_offdie(dbg(), cu_off + cu_header_length, ¤t_cu_die)) continue; - Dwarf_Half moduleTag = dwarf_tag(¤t_cu_die); - if (moduleTag == DW_TAG_partial_unit) { + if (DwarfDyninst::is_partial_unit(current_cu_die)) { continue; } parseModuleSig8(true); @@ -2723,24 +2544,10 @@ void DwarfWalker::findAllSig8Types() bool DwarfWalker::parseModuleSig8(bool is_info) { - /* Obtain the type DIE. */ - Dwarf_Die typeDIE = current_cu_die; - - /* Make sure we've got the right one. */ - Dwarf_Half typeTag = dwarf_tag(&typeDIE); - //DWARF_FAIL_RET(typeTag); - - if (typeTag != DW_TAG_type_unit) + if (!DwarfDyninst::is_type_unit(current_cu_die)) return false; - /* typeoffset is relative to the type unit; we want the global offset. */ - //FIXME - //Dwarf_Off cu_off, cu_length; - //DWARF_FAIL_RET(dwarf_die_CU_offset_range(typeDIE, &cu_off, &cu_length, NULL )); - //cerr << "a) " << dwarf_dieoffset(&typeDIE) << endl; - //cerr << "b) " << dwarf_cuoffset(&typeDIE) << endl; - uint64_t sig8 = * reinterpret_cast(&signature); - typeId_t type_id = get_type_id(/*cu_off +*/ typeoffset, is_info, false); + typeId_t type_id = get_type_id(typeoffset, is_info, false); { dyn_c_hash_map::accessor a; @@ -2750,7 +2557,7 @@ bool DwarfWalker::parseModuleSig8(bool is_info) return true; } -bool DwarfWalker::findSig8Type(Dwarf_Sig8 * s, boost::shared_ptr&returnType) +bool DwarfWalker::findSig8Type(Dwarf_Sig8 * s, dyncompat::shared_ptr&returnType) { uint64_t sig8 = * reinterpret_cast(s); typeId_t type_id = 0; @@ -2781,12 +2588,9 @@ Offset DwarfParseActions::convertDebugOffset(Offset from) { void DwarfWalker::setFuncReturnType() { dwarf_printf("(0x%lx) In setFuncReturnType().\n", id()); - boost::shared_ptr returnType; - boost::unique_lock l(curFunc()->ret_lock); - if (!curFunc()->getReturnType(Type::share)) { - getReturnType(false, returnType); + dyncompat::shared_ptr returnType; + getReturnType(returnType); if (returnType) curFunc()->setReturnType(returnType); - } } diff --git a/symtabAPI/src/dwarfWalker.h b/symtabAPI/src/dwarfWalker.h index 5dd6663c67..e3d3dd4ca6 100644 --- a/symtabAPI/src/dwarfWalker.h +++ b/symtabAPI/src/dwarfWalker.h @@ -8,6 +8,9 @@ #include "elf.h" #include "libelf.h" #include "elfutils/libdw.h" +#include +#include +#include #include #include #include @@ -16,39 +19,37 @@ #include "VariableLocation.h" #include "Type.h" #include "Object.h" -#include -#include +#include +#include +#include #include //Concurrent Hash Map #include "concurrent.h" -#include namespace Dyninst { -namespace SymtabAPI { - typedef struct { - Dwarf_Off off; - bool file; - Module * m; - } type_key; -} -} - -namespace tbb { - using namespace Dyninst::SymtabAPI; - template<> - struct tbb_hash_compare { - static size_t hash(const type_key& k) { - size_t seed = 0; - boost::hash_combine(seed, k.off); - boost::hash_combine(seed, k.file); - boost::hash_combine(seed, static_cast(k.m)); - return seed; - } - static bool equal(const type_key& k1, const type_key& k2) { - return (k1.off==k2.off && k1.file==k2.file && k1.m==k2.m); - } - }; + namespace SymtabAPI { + typedef struct { + Dwarf_Off off; + bool file; + Module * m; + } type_key; + inline bool operator==(type_key const& k1, type_key const& k2) { + return k1.off==k2.off && k1.file==k2.file && k1.m==k2.m; + } + } + namespace concurrent { + template<> + struct hasher { + size_t operator()(const SymtabAPI::type_key& k) const { + size_t seed = 0; + dyncompat::hash_combine(seed, k.off); + dyncompat::hash_combine(seed, k.file); + dyncompat::hash_combine(seed, static_cast(k.m)); + return seed; + } + }; + } } namespace Dyninst { @@ -94,40 +95,21 @@ class DwarfParseActions { } virtual ~DwarfParseActions() = default; typedef std::vector > range_set_t; - typedef boost::shared_ptr > > range_set_ptr; + typedef dyncompat::shared_ptr > > range_set_ptr; private: struct Context { - FunctionBase *func; - boost::shared_ptr commonBlock; - boost::shared_ptr enumType; - boost::shared_ptr enclosure; - bool parseSibling; - bool parseChild; - Dwarf_Die offset; - Dwarf_Die specEntry; - Dwarf_Die abstractEntry; - unsigned int tag; - Address base; - range_set_ptr ranges; - Context() : - func(NULL), commonBlock(NULL), - enumType(NULL), enclosure(NULL), - parseSibling(true), parseChild(true), - tag(0), base(0) { - } - Context(const Context& o) noexcept : - func(o.func), - commonBlock(o.commonBlock), - enumType(o.enumType), - enclosure(o.enclosure), - parseSibling(o.parseSibling), - parseChild(o.parseChild), - offset(o.offset), - specEntry(o.specEntry), - abstractEntry(o.specEntry), - tag(o.tag), - base(o.base) - {} + FunctionBase *func{}; + dyncompat::shared_ptr commonBlock{}; + dyncompat::shared_ptr enumType{}; + dyncompat::shared_ptr enclosure{}; + bool parseSibling{true}; + bool parseChild{true}; + Dwarf_Die offset{}; + Dwarf_Die specEntry{}; + Dwarf_Die abstractEntry{}; + unsigned int tag{}; + Address base{}; + range_set_ptr ranges{}; }; std::stack c; @@ -140,9 +122,9 @@ class DwarfParseActions { virtual std::vector& getFramePtrRefForInit(); virtual void addMangledFuncName(std::string); virtual void addPrettyFuncName(std::string); - boost::shared_ptr curCommon() { return c.top().commonBlock; } - boost::shared_ptr curEnum() { return c.top().enumType; } - boost::shared_ptr curEnclosure() { return c.top().enclosure; } + dyncompat::shared_ptr curCommon() { return c.top().commonBlock; } + dyncompat::shared_ptr curEnum() { return c.top().enumType; } + dyncompat::shared_ptr curEnclosure() { return c.top().enclosure; } bool parseSibling() { return c.top().parseSibling; } bool parseChild() { return c.top().parseChild; } Dwarf_Die entry() { @@ -160,9 +142,9 @@ class DwarfParseActions { range_set_ptr ranges() { return c.top().ranges; } void setFunc(FunctionBase *f); - void setCommon(boost::shared_ptr tc) { c.top().commonBlock = tc; } - void setEnum(boost::shared_ptr e) { c.top().enumType = e; } - void setEnclosure(boost::shared_ptr f) { c.top().enclosure = f; } + void setCommon(dyncompat::shared_ptr tc) { c.top().commonBlock = tc; } + void setEnum(dyncompat::shared_ptr e) { c.top().enumType = e; } + void setEnclosure(dyncompat::shared_ptr f) { c.top().enclosure = f; } void setParseSibling(bool p) { c.top().parseSibling = p; } void setParseChild(bool p) { c.top().parseChild = p; } virtual void setEntry(Dwarf_Die e) { c.top().offset = e; } @@ -188,7 +170,6 @@ class DwarfParseActions { { return symtab()->file(); } - virtual void setModuleFromName(std::string moduleName); virtual Dyninst::Architecture getArchitecture() const { return symtab()->getArchitecture(); @@ -213,6 +194,10 @@ class DwarfParseActions { Symtab *symtab_; virtual Object * obj() const ; + // Function object of current subprogram being parsed; used to detect + // parseSubprogram recursion + FunctionBase *currentSubprogramFunction = nullptr; + }; // class DwarfParseActions struct ContextGuard { @@ -232,7 +217,9 @@ class DwarfWalker : public DwarfParseActions { } Error; - DwarfWalker(Symtab *symtab, Dwarf* dbg); + using ParsedFuncs = Dyninst::dyn_c_hash_map; + + DwarfWalker(Symtab *symtab, Dwarf* dbg, std::shared_ptr pf = nullptr); DwarfWalker(const DwarfWalker& o) : DwarfParseActions(o), @@ -242,7 +229,6 @@ class DwarfWalker : public DwarfParseActions { is_mangled_name_(o.is_mangled_name_), modLow(o.modLow), modHigh(o.modHigh), cu_header_length(o.cu_header_length), - version(o.version), abbrev_offset(o.abbrev_offset), addr_size(o.addr_size), offset_size(o.offset_size), @@ -253,7 +239,12 @@ class DwarfWalker : public DwarfParseActions { compile_offset(o.compile_offset), info_type_ids_(o.info_type_ids_), types_type_ids_(o.types_type_ids_), - sig8_type_ids_(o.sig8_type_ids_) {} + sig8_type_ids_(o.sig8_type_ids_) + { + if (!parsedFuncs) { + parsedFuncs = std::make_shared(); + } + } virtual ~DwarfWalker(); @@ -278,7 +269,9 @@ class DwarfWalker : public DwarfParseActions { bool parseSubprogram(inline_t func_type); bool parseLexicalBlock(); - bool parseRangeTypes(Dwarf* dbg, Dwarf_Die die); + bool parseTryBlock(); + bool parseCatchBlock(); + bool parseRangeTypes(Dwarf_Die die); bool parseCommonBlock(); bool parseConstant(); virtual bool parseVariable(); @@ -294,8 +287,6 @@ class DwarfWalker : public DwarfParseActions { bool parseMember(); bool parseConstPackedVolatile(); bool parseTypeReferences(); - static std::pair parseHighPCLowPC(Dwarf* dbg, Dwarf_Die entry); - // These vary as we parse the tree @@ -333,30 +324,26 @@ class DwarfWalker : public DwarfParseActions { bool setFunctionFromRange(inline_t func_type); virtual void setEntry(Dwarf_Die e); bool getFrameBase(); - bool getReturnType(bool hasSpecification, boost::shared_ptr&returnType); - bool addFuncToContainer(boost::shared_ptr returnType); + bool getReturnType(dyncompat::shared_ptr&returnType); + bool addFuncToContainer(dyncompat::shared_ptr returnType); bool isStaticStructMember(std::vector &locs, bool &isStatic); - virtual bool findType(boost::shared_ptr&, bool defaultToVoid); + virtual bool findType(dyncompat::shared_ptr&, bool defaultToVoid); bool findAnyType(Dwarf_Attribute typeAttribute, - bool is_info, boost::shared_ptr&type); + bool is_info, dyncompat::shared_ptr&type); bool findDieOffset(Dwarf_Attribute attr, Dwarf_Off &offset); bool getLineInformation(Dwarf_Word &variableLineNo, bool &hasLineNumber, std::string &filename); -public: - static bool findDieName(Dwarf_Die die, std::string &); private: - bool findName(std::string &); + std::string die_name(); void removeFortranUnderscore(std::string &); bool findSize(unsigned &size); bool findVisibility(visibility_t &visibility); - bool findValue(long &value, bool &valid); - bool fixName(std::string &name, boost::shared_ptr type); + dyncompat::optional findConstValue(); + bool fixName(std::string &name, dyncompat::shared_ptr type); bool fixBitFields(std::vector &locs, long &size); - bool parseSubrangeAUX(Dwarf_Die entry, - std::string &lobound, - std::string &hibound); + dyncompat::shared_ptr parseSubrange(Dwarf_Die *entry); bool decodeLocationList(Dwarf_Half attr, Address *initialVal, std::vector &locs); @@ -365,21 +352,19 @@ class DwarfWalker : public DwarfParseActions { bool &constant, bool &expr, Dwarf_Half &form); - bool findString(Dwarf_Half attr, std::string &str); + dyncompat::optional find_call_file(); public: static bool findConstant(Dwarf_Half attr, Address &value, Dwarf_Die *entry, Dwarf *dbg); static bool findConstantWithForm(Dwarf_Attribute &attr, Dwarf_Half form, Address &value); - static std::vector getDieRanges(Dwarf* dbg, Dwarf_Die die, Offset base); + static std::vector getDieRanges(Dwarf_Die die); private: bool decodeConstantLocation(Dwarf_Attribute &attr, Dwarf_Half form, std::vector &locs); bool constructConstantVariableLocation(Address value, std::vector &locs); - boost::shared_ptr parseMultiDimensionalArray(Dwarf_Die *firstRange, - boost::shared_ptr elementType); - bool decipherBound(Dwarf_Attribute boundAttribute, bool is_info, - std::string &name); + dyncompat::shared_ptr parseMultiDimensionalArray(Dwarf_Die *firstRange, + dyncompat::shared_ptr elementType); bool decodeExpression(Dwarf_Attribute &attr, std::vector &locs); @@ -395,12 +380,10 @@ class DwarfWalker : public DwarfParseActions { Dwarf_Sword listLength, std::vector& locs, Address * initialStackValue = NULL); - void deallocateLocationList(Dwarf_Op **locationList, - Dwarf_Sword listLength); - // Header-only functions get multiple parsed. - std::set parsedFuncs; + // Map of Function* to bool (indicates function parsed) + std::shared_ptr parsedFuncs; private: std::string name_; bool is_mangled_name_; @@ -409,7 +392,6 @@ class DwarfWalker : public DwarfParseActions { Address modLow; Address modHigh; size_t cu_header_length; - Dwarf_Half version; Dwarf_Word abbrev_offset; uint8_t /*Dwarf_Half*/ addr_size; uint8_t /*Dwarf_Half*/ offset_size; @@ -443,12 +425,12 @@ class DwarfWalker : public DwarfParseActions { bool parseModuleSig8(bool is_info); void findAllSig8Types(); - bool findSig8Type(Dwarf_Sig8 * signature, boost::shared_ptr&type); + bool findSig8Type(Dwarf_Sig8 * signature, dyncompat::shared_ptr&type); unsigned int getNextTypeId(); protected: virtual void setFuncReturnType(); - virtual void createLocalVariable(const std::vector &locs, boost::shared_ptr type, + virtual void createLocalVariable(const std::vector &locs, dyncompat::shared_ptr type, Dwarf_Word variableLineNo, const std::string &fileName); @@ -457,15 +439,15 @@ class DwarfWalker : public DwarfParseActions { virtual void setFuncFromLowest(Address lowest); virtual void createParameter(const std::vector &locs, - boost::shared_ptr paramType, Dwarf_Word lineNo, const std::string &fileName); + dyncompat::shared_ptr paramType, Dwarf_Word lineNo, const std::string &fileName); virtual void setRanges(FunctionBase *func); - virtual void createGlobalVariable(const std::vector &locs, boost::shared_ptr type); + virtual void createGlobalVariable(const std::vector &locs, dyncompat::shared_ptr type); - virtual bool addStaticClassVariable(const std::vector &locs, boost::shared_ptr type); + virtual bool addStaticClassVariable(const std::vector &locs, dyncompat::shared_ptr type); - virtual boost::shared_ptr getCommonBlockType(std::string &commonBlockName); + virtual dyncompat::shared_ptr getCommonBlockType(std::string &commonBlockName); virtual Symbol *findSymbolForCommonBlock(const std::string &commonBlockName); diff --git a/symtabAPI/src/emitElf.C b/symtabAPI/src/emitElf.C index 139504181d..c2f0e945de 100644 --- a/symtabAPI/src/emitElf.C +++ b/symtabAPI/src/emitElf.C @@ -35,6 +35,7 @@ #include "emitElfStatic.h" #include "common/src/pathName.h" #include "dyninstAPI_RT/h/dyninstAPI_RT.h" +#include "unaligned_memory_access.h" #if defined(os_freebsd) @@ -342,7 +343,7 @@ bool emitElf::createElfSymbol(Symbol *symbol, unsigned strIndex, vecto else { if (vers) { // There should only be one version string by this time - //If the verison name already exists then add the same version number to the version symbol table + //If the version name already exists then add the same version number to the version symbol table //Else give a new number and add it to the mapping. if (versionNames.find((*vers)[0]) == versionNames.end()) { mpos += sprintf(mpos, " new version name: %s\n", (*vers)[0].c_str()); @@ -372,9 +373,6 @@ bool emitElf::createElfSymbol(Symbol *symbol, unsigned strIndex, vecto } } } -#ifdef BINEDIT_DEBUG - printf("%s", msg); -#endif } return true; @@ -580,6 +578,27 @@ bool emitElf::driver(std::string fName) { newshdr->sh_entsize = 0x0; } + if (library_adjust > 0 && newdata->d_buf && newdata->d_size) { + std::vector &relr_relocs = object->getRelrDynRelocs(); + for (unsigned ri = 0; ri < relr_relocs.size(); ++ri) { + Offset relr_addr = relr_relocs[ri]; + if (relr_addr < shdr->sh_addr || + relr_addr + sizeof(Elf_Relr) > shdr->sh_addr + shdr->sh_size) + continue; + + Offset relr_off = relr_addr - shdr->sh_addr; + if (relr_off + sizeof(Elf_Relr) > newdata->d_size) + continue; + + char *loc = static_cast(newdata->d_buf) + relr_off; + Elf_Relr val = 0; + memcpy(&val, loc, sizeof(val)); + if (!val) continue; + val += library_adjust; + memcpy(loc, &val, sizeof(val)); + } + } + if (BSSExpandFlag) { // Add the expanded SHT_NOBITS section size if the section comes after those sections if (scncount > NOBITSstartPoint) @@ -682,7 +701,17 @@ bool emitElf::driver(std::string fName) { (strcmp(name, ".init_array") == 0 || strcmp(name, ".fini_array") == 0 || strcmp(name, "__libc_subfreeres") == 0 || strcmp(name, "__libc_atexit") == 0 || strcmp(name, "__libc_thread_subfreeres") == 0 || strcmp(name, "__libc_IO_vtables") == 0)) { + std::vector &relr_relocs = object->getRelrDynRelocs(); for(std::size_t off = 0; off < newdata->d_size; off += sizeof(void*)) { + Offset addr = shdr->sh_addr + off; + bool is_relr_location = false; + for (unsigned ri = 0; ri < relr_relocs.size(); ++ri) { + if (relr_relocs[ri] == addr) { + is_relr_location = true; + break; + } + } + if (is_relr_location) continue; char *loc = static_cast(newdata->d_buf) + off; size_t val{}; // The calls to memcpy are required to not break the aliasing rules. @@ -694,7 +723,7 @@ bool emitElf::driver(std::string fName) { } // Change offsets of sections based on the newly added sections if (movePHdrsFirst) { - /* This special case is specific to FreeBSD but there is no hurt in + /* This special case is specific to FreeBSD but there is no harm in * handling it on other platforms. * * This is necessary because the INTERP header must be located within in @@ -1105,7 +1134,7 @@ void emitElf::fixPhdrs(unsigned &extraAlignSize) { return; //We made a new section to contain the program headers--keeps - // libelf from overwriting the program headers data when outputing + // libelf from overwriting the program headers data when outputting // sections. Fill in the new section's data with what we just wrote. Elf_Data *data = elf_newdata(phdrs_scn); size_t total_size = (size_t) newEhdr->e_phnum * (size_t) newEhdr->e_phentsize; @@ -1130,12 +1159,25 @@ void emitElf::fixPhdrs(unsigned &extraAlignSize) { #if !defined(DT_TLSDESC_GOT) #define DT_TLSDESC_GOT 0x6ffffef7 #endif +// Older elf.h headers may not define RELR dynamic tag constants +#if !defined(DT_RELRSZ) +#define DT_RELRSZ 35 +#endif +#if !defined(DT_RELR) +#define DT_RELR 36 +#endif +#if !defined(DT_RELRENT) +#define DT_RELRENT 37 +#endif +#if !defined(SHT_RELR) +#define SHT_RELR 19 +#endif //This method updates the .dynamic section to reflect the changes to the relocation section template void emitElf::updateDynamic(unsigned tag, Elf_Addr val) { if (isStaticBinary) return; - // This is for REL/RELA if it doesnt already exist in the original binary; + // This is for REL/RELA if it doesn't already exist in the original binary; if(dynamicSecData.find(tag) != dynamicSecData.end()) dynamicSecData[tag][0]->d_tag = tag; else return; @@ -1143,10 +1185,12 @@ void emitElf::updateDynamic(unsigned tag, Elf_Addr val) { case DT_STRSZ: case DT_RELSZ: case DT_RELASZ: + case DT_RELRSZ: case DT_PLTRELSZ: case DT_RELACOUNT: case DT_RELENT: case DT_RELAENT: + case DT_RELRENT: dynamicSecData[tag][0]->d_un.d_val = val; break; case DT_HASH: @@ -1155,6 +1199,7 @@ void emitElf::updateDynamic(unsigned tag, Elf_Addr val) { case DT_STRTAB: case DT_REL: case DT_RELA: + case DT_RELR: case DT_VERSYM: case DT_JMPREL: dynamicSecData[tag][0]->d_un.d_ptr = val; @@ -1277,7 +1322,7 @@ bool emitElf::createLoadableSections(Elf_Shdr *&shdr, unsigned &extraA } else if (!firstNewLoadSec || !newSecs[i]->getDiskOffset()) { newshdr->sh_offset = shdr->sh_offset + shdr->sh_size; } else { - // The offset can be computed by determing the difference from + // The offset can be computed by determining the difference from // the first new loadable section newshdr->sh_offset = firstNewLoadSec->sh_offset + library_adjust + (newSecs[i]->getDiskOffset() - firstNewLoadSec->sh_addr); @@ -1334,6 +1379,20 @@ bool emitElf::createLoadableSections(Elf_Shdr *&shdr, unsigned &extraA else if (newSecs[i]->getRegionType() == Region::RT_PLTRELA) updateDynamic(DT_JMPREL, newshdr->sh_addr); } + else if (newSecs[i]->getRegionType() == Region::RT_RELR) + { + newshdr->sh_type = SHT_RELR; + newshdr->sh_flags = SHF_ALLOC; + newshdr->sh_entsize = sizeof(Elf_Relr); + // SHT_RELR entries are Elf32_Word for ELFCLASS32 and Elf64_Xword + // for ELFCLASS64 + newdata->d_type = + (sizeof(Elf_Relr) == sizeof(Elf32_Word)) ? ELF_T_WORD : ELF_T_XWORD; + newdata->d_align = sizeof(Elf_Relr); + updateDynamic(DT_RELR, newshdr->sh_addr); + updateDynamic(DT_RELRSZ, newSecs[i]->getDiskSize()); + updateDynamic(DT_RELRENT, sizeof(Elf_Relr)); + } else if (newSecs[i]->getRegionType() == Region::RT_STRTAB) //String table Section { newshdr->sh_type = SHT_STRTAB; @@ -1632,7 +1691,7 @@ bool emitElf::createNonLoadableSections(Elf_Shdr *&shdr) { /* Regenerates the .symtab, .strtab sections from the symbols * Add new .dynsym, .dynstr sections for the newly added dynamic symbols - * Method - For every symbol call createElfSymbol to get a Elf_Sym corresposnding + * Method - For every symbol call createElfSymbol to get a Elf_Sym corresponding * to a Symbol object. Accumulate all and their names to form the sections * and add them to the list of new sections */ @@ -1718,7 +1777,7 @@ bool emitElf::createSymbolTables(set &allSymbols) { + errMsg; Symtab::setSymtabError(Emit_Error); symtab_log_perror(linkStaticError.c_str()); - fprintf(stderr, "##### %s\n", linkStaticError.c_str()); + fprintf(stderr, "##### %s\n", linkStaticError.c_str()); return false; } @@ -1755,7 +1814,7 @@ bool emitElf::createSymbolTables(set &allSymbols) { } } - // sort allSymbols in a way that every symmbol with index -1 are in order of offset + // sort allSymbols in a way that every symbol with index -1 are in order of offset std::sort(allDynSymbols.begin(), allDynSymbols.end(), sortByOffsetNewIndices()); int max_index = -1; @@ -1981,6 +2040,7 @@ bool emitElf::createSymbolTables(set &allSymbols) { createRelocationSections(object_->getDynRelocs(), true, dynSymNameMapping); createRelocationSections(object_->getPLTRelocs(), false, dynSymNameMapping); } + createRelrRelocationSection(object_->getRelrDynRelocs()); //add .dynamic section if (dynsecSize) @@ -1990,6 +2050,32 @@ bool emitElf::createSymbolTables(set &allSymbols) { if (!obj->getAllNewRegions(newSecs)) log_elferror(err_func_, "No new sections to add"); + unsigned int prev_size = 0; + unsigned long sec_addr = 0; + for (unsigned long nsi = 0; nsi < newSecs.size(); nsi++) { + // Update the _DYNAMIC symbol; described in the elf standard as: + // The program header table will have an element of type PT_DYNAMIC. + // This "segment" contains the .dynamic section. A special symbol, + // _DYNAMIC, labels the section + if (newSecs[nsi]->getDiskOffset()) + sec_addr = newSecs[nsi]->getDiskOffset() + library_adjust; + else + sec_addr += prev_size; + prev_size = newSecs[nsi]->getDiskSize(); + if (".dynamic" == newSecs[nsi]->getRegionName()) { + // Found the .dynamic section + for (unsigned long symi = 0; symi < symbolStrs.size(); symi++) + if ("_DYNAMIC" == symbolStrs[symi]) { + // Found the _DYNAMIC symbol + rewrite_printf("update _DYNAMIC symbol from %#lx to %#lx\n", + (unsigned long) syms[symi].st_value, (unsigned long) sec_addr); + syms[symi].st_value = sec_addr; + break; + } + break; + } + } + return true; } @@ -2170,6 +2256,26 @@ void emitElf::createRelocationSections(std::vector &r updateDynamic(dsize_type, dynamic_reloc_size); } +template +void emitElf::createRelrRelocationSection(std::vector &relr_table) { + if (relr_table.empty()) return; + + Elf_Relr *relrs = (Elf_Relr *) malloc(sizeof(Elf_Relr) * relr_table.size()); + for (unsigned i = 0; i < relr_table.size(); ++i) { + relrs[i] = static_cast(relr_table[i] + library_adjust); + } + + dyn_hash_map secTagRegionMapping = object->getTagRegionMapping(); + string name; + if (secTagRegionMapping.find(DT_RELR) != secTagRegionMapping.end()) + name = secTagRegionMapping[DT_RELR]->getRegionName(); + else + name = ".relr.dyn"; + + obj->addRegion(0, relrs, relr_table.size() * sizeof(Elf_Relr), name, + Region::RT_RELR, true); +} + template void emitElf::createSymbolVersions(Elf_Half *&symVers, char *&verneedSecData, unsigned &verneedSecSize, char *&verdefSecData, @@ -2189,6 +2295,29 @@ void emitElf::createSymbolVersions(Elf_Half *&symVers, char *&verneedS for (unsigned i = 0; i < versionSymTable.size(); i++) symVers[i] = versionSymTable[i]; + // Preserve original .gnu.version_r entries that were not recreated through + // symbol version references, unless their provider library was removed + const auto &originalVersionMapping = object->getVersionMapping(); + const auto &originalVersionFileNameMapping = object->getVersionFileNameMapping(); + const auto &removedLibraries = object->libsRMd(); + for (const auto &versionEntry : originalVersionMapping) { + auto fileEntry = originalVersionFileNameMapping.find(versionEntry.first); + if (fileEntry == originalVersionFileNameMapping.end()) continue; + if (find(removedLibraries.begin(), removedLibraries.end(), fileEntry->second) != + removedLibraries.end()) continue; + + auto &versionEntries = verneedEntries[fileEntry->second]; + for (const auto &versionName : versionEntry.second) { + if (versionEntries.find(versionName) != versionEntries.end()) continue; + if (versionNames.find(versionName) == versionNames.end()) { + versionNames[versionName] = dynSymbolNamesLength; + dynStrs.push_back(versionName); + dynSymbolNamesLength += versionName.size() + 1; + } + versionEntries[versionName] = curVersionNum++; + } + } + //reconstruct .gnu.version_r section verneedSecSize = 0; map >::iterator it = verneedEntries.begin(); @@ -2287,7 +2416,7 @@ void emitElf::createHashSection(Elf_Word *&hashsecData, unsigned &hash Elf_Scn *scn = NULL; Elf_Shdr *shdr = NULL; - for (unsigned scncount = 0; (scn = elf_nextscn(oldElf, scn)); scncount++) { + while ((scn = elf_nextscn(oldElf, scn))) { shdr = ElfTypes::elf_getshdr(scn); if (obj->getObject()->getElfHashAddr() != 0 && obj->getObject()->getElfHashAddr() == shdr->sh_addr) { @@ -2372,9 +2501,9 @@ void emitElf::createDynamicSection(void *dynData_, unsigned size, Elf_ dynamicSecData[DT_NEEDED].push_back(dynsecData + curpos); curpos++; } - for (unsigned i = 0; i < new_dynamic_entries.size(); i++) { - long name = new_dynamic_entries[i].first; - long value = new_dynamic_entries[i].second; + for (auto const& entry: new_dynamic_entries){ + long name = entry.first; + long value = entry.second; dynsecData[curpos].d_tag = name; long adjust = 0; switch(name) @@ -2401,8 +2530,8 @@ void emitElf::createDynamicSection(void *dynData_, unsigned size, Elf_ if (obj->findRegion(dyninstReg, ".dyninstInst") && library_adjust) { // The trap mapping header's in-memory offset is specified by the dynamic entry // We now need to get raw section data, and the raw sectiond data offset of the header - struct trap_mapping_header* header = (struct trap_mapping_header *) ((char*)dyninstReg->getPtrToRawData() + value - dyninstReg->getMemOffset()); - for (i = 0; i < header->num_entries; i++) { + auto header = alignas_cast(((char*)dyninstReg->getPtrToRawData() + value - dyninstReg->getMemOffset())); + for (unsigned i = 0; i < header->num_entries; i++) { header->traps[i].source = (void*) ((char*)header->traps[i].source + library_adjust); header->traps[i].target = (void*) ((char*)header->traps[i].target + library_adjust); } diff --git a/symtabAPI/src/emitElf.h b/symtabAPI/src/emitElf.h index 50ccf0945d..9744c17166 100644 --- a/symtabAPI/src/emitElf.h +++ b/symtabAPI/src/emitElf.h @@ -36,6 +36,11 @@ #include "Elf_X.h" #include +#include +#include +#include +#include +#include #include #include #include @@ -49,7 +54,7 @@ extern const char *STRTAB_NAME; extern const char *SYMTAB_NAME; extern const char *INTERP_NAME; -extern const char *pdelf_get_shnames(Elf_X *elf); +extern const char *pdelf_get_shnames(Dyninst::Elf_X *elf); #define PT_PAX_FLAGS (PT_LOOS + 0x5041580) /* PaX flags */ @@ -87,6 +92,7 @@ namespace Dyninst { typedef Elf32_Section Elf_Section; typedef Elf32_Rel Elf_Rel; typedef Elf32_Rela Elf_Rela; + typedef Elf32_Word Elf_Relr; typedef Elf32_Verneed Elf_Verneed; typedef Elf32_Vernaux Elf_Vernaux; typedef Elf32_Verdef Elf_Verdef; @@ -118,6 +124,7 @@ namespace Dyninst { typedef Elf64_Section Elf_Section; typedef Elf64_Rel Elf_Rel; typedef Elf64_Rela Elf_Rela; + typedef Elf64_Xword Elf_Relr; typedef Elf64_Verneed Elf_Verneed; typedef Elf64_Vernaux Elf_Vernaux; typedef Elf64_Verdef Elf_Verdef; @@ -152,6 +159,7 @@ namespace Dyninst { typedef typename ElfTypes::Elf_Section Elf_Section; typedef typename ElfTypes::Elf_Rel Elf_Rel; typedef typename ElfTypes::Elf_Rela Elf_Rela; + typedef typename ElfTypes::Elf_Relr Elf_Relr; typedef typename ElfTypes::Elf_Verneed Elf_Verneed; typedef typename ElfTypes::Elf_Vernaux Elf_Vernaux; typedef typename ElfTypes::Elf_Verdef Elf_Verdef; @@ -205,7 +213,7 @@ namespace Dyninst { std::map > verdauxEntries; std::map versionNames; std::vector versionSymTable; - int curVersionNum, verneednum, verdefnum, dynsym_info; + int curVersionNum, verneednum, verdefnum, dynsym_info{}; // Needed when adding a new segment Elf_Off newSegmentStart; @@ -257,6 +265,8 @@ namespace Dyninst { void createRelocationSections(std::vector &relocation_table, bool isDynRelocs, std::unordered_map &dynSymNameMapping); + + void createRelrRelocationSection(std::vector &relr_table); void updateSymbols(Elf_Data* symtabData,Elf_Data* strData, unsigned long loadSecsSize); diff --git a/symtabAPI/src/emitElfStatic-ppc32.C b/symtabAPI/src/emitElfStatic-ppc32.C deleted file mode 100644 index e10508b0be..0000000000 --- a/symtabAPI/src/emitElfStatic-ppc32.C +++ /dev/null @@ -1,744 +0,0 @@ -/* - * See the dyninst/COPYRIGHT file for copyright information. - * - * We provide the Paradyn Tools (below described as "Paradyn") - * on an AS IS basis, and do not warrant its validity or performance. - * We reserve the right to update, modify, or discontinue this - * software at any time. We shall have no obligation to supply such - * updates or modifications or any other form of support to you. - * - * By your use of Paradyn, you understand and agree that we (or any - * other person or entity with proprietary rights in Paradyn) are - * under no obligation to provide either maintenance services, - * update services, notices of latent defects, or correction of - * defects for Paradyn. - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* - * holds architecture specific functions for x86 and x86_64 architecture needed for the - * static executable rewriter - */ - -#include -#include -#include -#include -#include -#include -#include - -#include "emitElfStatic.h" -#include "Symtab.h" -#include "Symbol.h" -#include "Archive.h" -#include "Object.h" -#include "Region.h" -#include "debug.h" - -using namespace Dyninst; -using namespace Dyninst::SymtabAPI; - -static const unsigned PPC32_WIDTH = 4; -static const unsigned PPC64_WIDTH = 8; - -static const Elf64_Word X86_HEADER = 0xffffffff; -static const Elf64_Word X86_TRAILER = 0x00000000; -static const Elf64_Xword X86_64_HEADER = 0xffffffffffffffffULL; -static const Elf64_Xword X86_64_TRAILER = 0x0000000000000000ULL; - -unsigned int setBits(unsigned int target, unsigned int pos, unsigned int len, unsigned int value) { - rewrite_printf("setBits target 0x%lx value 0x%lx pos %d len %d \n", target, value, pos, len); - unsigned int mask; - mask = ~(~0 << len); - value = value & mask; - - mask = ~(mask << pos); - value = value << pos; - - target = target & mask; - target = target | value; - rewrite_printf( "setBits target 0x%lx value 0x%lx pos %d len %d \n", target, value, pos, len); - return target; -} - -#if defined(os_freebsd) -#define R_X86_64_JUMP_SLOT R_X86_64_JMP_SLOT -#endif - -// Used in an assert so needs to be a macro -#define UNKNOWN_ADDRESS_WIDTH_ASSERT "An unknown address width was encountered, can't continue" - -/* NOTE: - * As most of these functions are defined per architecture, the description of - * each of these functions is in the emitElfStatic header. Comments describing - * the function interface are explicitly left out. - */ - -/** - * - * Given a relocation, determines if the relocation corresponds to a .ctors or .dtors - * table that requires special consideration. Modifies the passed symbol offset to - * point to the right table, if applicable. - * - * rel The relocation entry to examine - * globalOffset The offset of the linked code (used for symbol offset calculation) - * lmap Holds information about .ctors/.dtors tables - * errMsg Set on error - * symbolOffset Modified by this routine to contain the offset of the table - * - * Returns true, if there are no errors including the case where the relocation - * entry doesn't reference the .ctors/.dtors tables. - */ - -static bool computeCtorDtorAddress(relocationEntry &rel, Offset globalOffset, - LinkMap &lmap, string &errMsg, Offset &symbolOffset) -{ - if( rel.name() == SYMTAB_CTOR_LIST_REL ) { - // This needs to be: (the location of the .ctors table) - if( lmap.newCtorRegions.size() > 0 ) { - symbolOffset = lmap.ctorRegionOffset + globalOffset; - }else if( lmap.originalCtorRegion != NULL ) { - symbolOffset = lmap.originalCtorRegion->getMemOffset(); - }else{ - errMsg = "Failed to locate original .ctors Region -- cannot apply relocation"; - rewrite_printf("Failed to locate original .ctors Region -- cannot apply relocation\n"); - return false; - } - }else if( rel.name() == SYMTAB_DTOR_LIST_REL ) { - // This needs to be: (the location of the .dtors table) - if( lmap.newDtorRegions.size() > 0 ) { - symbolOffset = lmap.dtorRegionOffset + globalOffset; - }else if( lmap.originalDtorRegion != NULL ) { - symbolOffset = lmap.originalDtorRegion->getMemOffset(); - }else{ - errMsg = "Failed to locate original .dtors Region -- cannot apply relocation"; - rewrite_printf("Failed to locate original .dtors Region -- cannot apply relocation\n"); - return false; - } - } - - return true; -} - - -bool emitElfStatic::archSpecificRelocation(Symtab *, Symtab *, char *targetData, relocationEntry &rel, - Offset dest, Offset relOffset, Offset globalOffset, LinkMap &lmap, - string &errMsg) -{ - rewrite_printf(" archSpecificRelocation %s \n", rel.name().c_str()); - if( PPC32_WIDTH == addressWidth_ ) { - int relocation_length = sizeof(Elf32_Word)*8; // in bits - int relocation_pos = 0; // in bits - int branch_pred = -1; - /* - * Referring to the SYSV 386 supplement: - * - * All relocations on x86 are one word32 == Elf32_Word - * - * S = symbolOffset - * A = addend - * P = relOffset - */ - - Offset symbolOffset = rel.getDynSym()->getOffset(); - - Elf32_Word addend; - if( rel.regionType() == Region::RT_REL ) { - memcpy(&addend, &targetData[dest], sizeof(Elf32_Word)); - }else if( rel.regionType() == Region::RT_RELA ) { - addend = rel.addend(); - } - - if(!computeCtorDtorAddress(rel, globalOffset, lmap, errMsg, symbolOffset)) { - return false; - } - - rewrite_printf("relocation for '%s': TYPE = %s(%lu) S = %lx A = %lx P = %lx\n", - rel.name().c_str(), - relocationEntry::relType2Str(rel.getRelType(), addressWidth_), - rel.getRelType(), symbolOffset, addend, relOffset); - - Offset relocation = 0; - map::iterator result; - stringstream tmp; - - switch(rel.getRelType()) { - -/* PowerPC relocations defined by the ABIs */ -case R_PPC_NONE:/* 0 */ - break; -case R_PPC_ADDR32:/* 1 32bit absolute address */ - relocation = symbolOffset + addend; - break; -case R_PPC_ADDR24:/* 2 26bit address, 2 bits ignored. */ - relocation_length = 26; - relocation_pos = 2; - relocation = (symbolOffset + addend) >> 2; - break; -case R_PPC_ADDR16:/* 3 16bit absolute address */ - relocation_length = 16; - relocation_pos = 16; - relocation = symbolOffset + addend; - break; -case R_PPC_ADDR16_LO:/* 4 lower 16bit of absolute address */ - relocation_length = 16; - relocation_pos = 0; - relocation = symbolOffset + addend; - relocation = (relocation & 0xffff); - break; -case R_PPC_ADDR16_HI:/* 5 high 16bit of absolute address */ - relocation_length = 16; - relocation_pos = 0; - relocation = symbolOffset + addend; - relocation = ((relocation >> 16) & 0xffff); - break; -case R_PPC_ADDR16_HA:/* 6 adjusted high 16bit */ - relocation_length = 16; - relocation_pos = 0; - relocation = symbolOffset + addend; - relocation = (((relocation >> 16) + ((relocation & 0x8000)? 1:0)) & 0xffff); - break; -case R_PPC_ADDR14:/* 7 16bit address, 2 bits ignored */ - relocation_length = 14; - relocation_pos = 16; - relocation = (symbolOffset + addend) >> 2; - break; -case R_PPC_ADDR14_BRTAKEN:/* 8 */ - relocation_length = 14; - relocation_pos = 16; - relocation = (symbolOffset + addend) >> 2; - // bit 10 is set - branch_pred = 1; - break; -case R_PPC_ADDR14_BRNTAKEN:/* 9 */ - relocation_length = 14; - relocation_pos = 16; - relocation = (symbolOffset + addend) >> 2; - // bit 10 is set - branch_pred = 0; - break; -case R_PPC_REL24:/* 10 PC relative 26 bit */ - relocation_length = 24; - relocation_pos = 2; - relocation = (symbolOffset + addend - relOffset) >> 2; - break; -case R_PPC_REL14:/* 11 PC relative 16 bit */ - relocation_length = 14; - relocation_pos = 16; - relocation = (symbolOffset + addend - relOffset) >> 2; - break; -case R_PPC_REL14_BRTAKEN:/* 12*/ - relocation_length = 14; - relocation_pos = 16; - relocation = (symbolOffset + addend - relOffset) >> 2; - branch_pred = 1; - break; -case R_PPC_REL14_BRNTAKEN:/* 13*/ - relocation_length = 14; - relocation_pos = 16; - relocation = (symbolOffset + addend - relOffset) >> 2; - branch_pred = 0; - break; -case R_PPC_GOT16:/* 14*/ - result = lmap.gotSymbols.find(rel.getDynSym()); - if( result == lmap.gotSymbols.end() ) { - errMsg = "Expected GOT symbol does not exist in GOT symbol mapping"; - return false; - } - relocation = result->second; - relocation = (relocation) >> 16; - relocation_length = 16; - relocation_pos = 16; - break; -case R_PPC_GOT16_LO:/* 15*/ - result = lmap.gotSymbols.find(rel.getDynSym()); - if( result == lmap.gotSymbols.end() ) { - errMsg = "Expected GOT symbol does not exist in GOT symbol mapping"; - return false; - } - relocation = result->second; - relocation = (relocation & 0xffff); - relocation_length = 16; - relocation_pos = 0; - break; -case R_PPC_GOT16_HI:/* 16*/ - result = lmap.gotSymbols.find(rel.getDynSym()); - if( result == lmap.gotSymbols.end() ) { - errMsg = "Expected GOT symbol does not exist in GOT symbol mapping"; - return false; - } - relocation = result->second; - relocation = ((relocation >> 16) & 0xffff); - relocation_length = 16; - relocation_pos = 0; - break; -case R_PPC_GOT16_HA:/* 17*/ - result = lmap.gotSymbols.find(rel.getDynSym()); - if( result == lmap.gotSymbols.end() ) { - errMsg = "Expected GOT symbol does not exist in GOT symbol mapping"; - return false; - } - relocation = result->second; - relocation = (((relocation >> 16) + ((relocation & 0x8000)? 1:0)) & 0xffff); - relocation_length = 16; - relocation_pos = 0; - break; -case R_PPC_PLTREL24:/* 18*/ - relocation_length = 24; - relocation_pos = 2; - relocation = (symbolOffset + addend - relOffset) >> 2; - break; -case R_PPC_COPY:/* 19*/ - break; -case R_PPC_GLOB_DAT:/* 20*/ - relocation = symbolOffset + addend; - break; -case R_PPC_JMP_SLOT:/* 21*/ - break; -case R_PPC_RELATIVE:/* 22*/ - tmp << "ERROR: encountered relocation type(" << rel.getRelType() << - ") that is meant for use during dynamic linking"; - errMsg = tmp.str(); - return false; -case R_PPC_LOCAL24PC:/* 23*/ - relocation_length = 24; - relocation_pos = 2; - relocation = (symbolOffset + addend - relOffset) >> 2; - break; -case R_PPC_UADDR32:/* 24*/ - relocation = symbolOffset + addend ; - break; -case R_PPC_UADDR16:/* 25*/ - relocation_length = 16; - relocation_pos = 16; - relocation = symbolOffset + addend; - break; -case R_PPC_REL32:/* 26*/ - relocation = symbolOffset + addend - relOffset; - break; -case R_PPC_PLT32:/* 27*/ - relocation = symbolOffset + addend; - break; -case R_PPC_PLTREL32:/* 28*/ - relocation = symbolOffset + addend - relOffset; - break; -case R_PPC_PLT16_LO:/* 29*/ - relocation = symbolOffset + addend; - relocation = (relocation & 0xffff); - break; -case R_PPC_PLT16_HI:/* 30*/ - relocation = symbolOffset + addend; - relocation = ((relocation >> 16) & 0xffff); - break; -case R_PPC_PLT16_HA:/* 31*/ - relocation = symbolOffset + addend; - relocation = (((relocation >> 16) + ((relocation & 0x8000)? 1:0)) & 0xffff); - break; -case R_PPC_SDAREL16:/* 32*/ -case R_PPC_SECTOFF:/* 33*/ -case R_PPC_SECTOFF_LO:/* 34*/ -case R_PPC_SECTOFF_HI:/* 35*/ -case R_PPC_SECTOFF_HA:/* 36*/ - tmp << "Relocation type " << rel.getRelType() - << " currently unimplemented"; - errMsg = tmp.str(); - rewrite_printf(" Relocation type %s currently unimplemented \n", relocationEntry::relType2Str(rel.getRelType(), addressWidth_)); - return false; - -/* PowerPC relocations defined for the TLS access ABI. */ -case R_PPC_TLS:/* 67 none (sym+add)@tls */ -case R_PPC_DTPMOD32:/* 68 word32 (sym+add)@dtpmod */ -case R_PPC_TPREL16:/* 69 half16* (sym+add)@tprel */ -case R_PPC_TPREL16_LO:/* 70 half16 (sym+add)@tprel@l */ -case R_PPC_TPREL16_HI:/* 71 half16 (sym+add)@tprel@h */ -case R_PPC_TPREL16_HA:/* 72 half16 (sym+add)@tprel@ha */ -case R_PPC_TPREL32:/* 73 word32 (sym+add)@tprel */ -case R_PPC_DTPREL16:/* 74 half16* (sym+add)@dtprel */ -case R_PPC_DTPREL16_LO:/* 75 half16 (sym+add)@dtprel@l */ -case R_PPC_DTPREL16_HI:/* 76 half16 (sym+add)@dtprel@h */ -case R_PPC_DTPREL16_HA:/* 77 half16 (sym+add)@dtprel@ha */ -case R_PPC_DTPREL32:/* 78 word32 (sym+add)@dtprel */ -case R_PPC_GOT_TLSGD16:/* 79 half16* (sym+add)@got@tlsgd */ -case R_PPC_GOT_TLSGD16_LO:/* 80 half16 (sym+add)@got@tlsgd@l */ -case R_PPC_GOT_TLSGD16_HI:/* 81 half16 (sym+add)@got@tlsgd@h */ -case R_PPC_GOT_TLSGD16_HA:/* 82 half16 (sym+add)@got@tlsgd@ha */ -case R_PPC_GOT_TLSLD16:/* 83 half16* (sym+add)@got@tlsld */ -case R_PPC_GOT_TLSLD16_LO:/* 84 half16 (sym+add)@got@tlsld@l */ -case R_PPC_GOT_TLSLD16_HI:/* 85 half16 (sym+add)@got@tlsld@h */ -case R_PPC_GOT_TLSLD16_HA:/* 86 half16 (sym+add)@got@tlsld@ha */ -case R_PPC_GOT_TPREL16:/* 87 half16* (sym+add)@got@tprel */ -case R_PPC_GOT_TPREL16_LO:/* 88 half16 (sym+add)@got@tprel@l */ -case R_PPC_GOT_TPREL16_HI:/* 89 half16 (sym+add)@got@tprel@h */ -case R_PPC_GOT_TPREL16_HA:/* 90 half16 (sym+add)@got@tprel@ha */ -case R_PPC_GOT_DTPREL16:/* 91 half16* (sym+add)@got@dtprel */ -case R_PPC_GOT_DTPREL16_LO:/* 92 half16* (sym+add)@got@dtprel@l */ -case R_PPC_GOT_DTPREL16_HI:/* 93 half16* (sym+add)@got@dtprel@h */ -case R_PPC_GOT_DTPREL16_HA:/* 94 half16* (sym+add)@got@dtprel@ha */ - relocation_length = 16; - relocation_pos = 16; - relocation = symbolOffset + addend; - rewrite_printf(" Relocation type %s currently unimplemented \n", relocationEntry::relType2Str(rel.getRelType(), addressWidth_)); - break; - -/* GNU relocs used in PIC code sequences. */ -/* NOTE: The following relocations are not defined in some elf.h - Hence, using numbers instead of name */ -case 249: /*R_PPC_REL16: 249 word32 (sym-.) */ - relocation_length = 16; - relocation_pos = 16; - relocation = symbolOffset + addend - relOffset ; - break; -case 250: /*R_PPC_REL16_LO: 250 half16 (sym-.)@l */ - relocation_length = 16; - relocation_pos = 16; - relocation = symbolOffset + addend - relOffset ; - relocation = (relocation & 0xffff); - break; -case 251: /*R_PPC_REL16_HI: 251 half16 (sym-.)@h */ - relocation_length = 16; - relocation_pos = 16; - relocation = symbolOffset + addend - relOffset ; - relocation = ((relocation >> 16) & 0xffff); - break; -case 252: /*R_PPC_REL16_HA: 252 half16 (sym-.)@ha */ - relocation_length = 16; - relocation_pos = 16; - relocation = symbolOffset + addend - relOffset ; - relocation = (((relocation >> 16) + ((relocation & 0x8000)? 1:0)) & 0xffff); - break; -/* This is a phony reloc to handle any old fashioned TOC16 references - that may still be in object files. */ -case 255: /*R_PPC_TOC16: 255*/ - break; - -default: - tmp << "Relocation type " << rel.getRelType() - << " currently unimplemented"; - rewrite_printf(" Relocation type %s currently unimplemented \n", relocationEntry::relType2Str(rel.getRelType(), addressWidth_)); - errMsg = tmp.str(); - return false; - } - - rewrite_printf(" relocation = 0x%lx @ 0x%lx target data 0x%lx %lx %lx %lx \n", relocation, relOffset, targetData[dest], targetData[dest+1], targetData[dest+2], targetData[dest+3]); - if (rel.getRelType() == R_PPC_REL24) { - unsigned int *td = (unsigned int *) targetData; - unsigned int target; - target = td[dest/4]; - target = setBits(target, relocation_pos, relocation_length, relocation); - memcpy(&targetData[dest], &target, sizeof(Elf32_Word)); - } else { - unsigned int *td = (unsigned int *) targetData; - unsigned int target; - target = td[dest/4]; - target = setBits(target, relocation_pos, relocation_length, relocation); - memcpy(&td[dest/4], &target, sizeof(Elf32_Word)); -// memcpy(&targetData[dest], r+2, relocation_size); - rewrite_printf(" relocation = 0x%lx @ 0x%lx target data 0x%lx %lx %lx %lx \n", relocation, relOffset, targetData[dest], targetData[dest+1], targetData[dest+2], targetData[dest+3]); - } - if (branch_pred >= 0) { - unsigned int *td = (unsigned int *) targetData; - unsigned int target; - target = td[dest/4]; - target = setBits(target, 10, 1, branch_pred); - memcpy(&td[dest/4], &target, sizeof(Elf32_Word)); - } - - } else{ - assert(!UNKNOWN_ADDRESS_WIDTH_ASSERT); - } - return true; -} - -bool emitElfStatic::checkSpecialCaseSymbols(Symtab *, Symbol *) { - return true; -} - -/* The TLS implementation on ppc is Variant 1 */ - -Offset emitElfStatic::layoutTLSImage(Offset globalOffset, Region *dataTLS, Region *bssTLS, LinkMap &lmap) { - return tlsLayoutVariant1(globalOffset, dataTLS, bssTLS, lmap); -} - -Offset emitElfStatic::adjustTLSOffset(Offset curOffset, Offset tlsSize) { - return curOffset; -} - -char emitElfStatic::getPaddingValue(Region::RegionType rtype) { - // TODO: if this matters, we can noop-pad by returning an unsigned - // instead of a char... - return 0x0; -} - -void emitElfStatic::cleanupTLSRegionOffsets(map ®ionAllocs, - Region *dataTLS, Region *bssTLS) -{ - tlsCleanupVariant2(regionAllocs, dataTLS, bssTLS); -} - -static const string CTOR_NAME(".ctors"); -static const string DTOR_NAME(".dtors"); -Offset emitElfStatic::layoutNewCtorRegion(LinkMap &lmap) { - /* - * .ctors sections are processed in reverse order on Linux x86. New .ctors - * sections need to be placed before the original .ctors section - */ - - Offset retOffset = lmap.ctorRegionOffset; - retOffset += addressWidth_; - - pair::iterator, bool> result; - - for(auto reg_it = lmap.newCtorRegions.begin(); reg_it != lmap.newCtorRegions.end(); ++reg_it) { - result = lmap.regionAllocs.insert(make_pair(*reg_it, make_pair(0, retOffset))); - - // If the map already contains this Region, this is a logic error - if( !result.second ) { - return ~0UL; - } - - retOffset += (*reg_it)->getDiskSize(); - } - - if( lmap.originalCtorRegion != NULL ) { - // Account for original .ctors section (minus the header and trailer) - retOffset += lmap.originalCtorRegion->getDiskSize() - addressWidth_ - addressWidth_; - } - retOffset += addressWidth_; - - return retOffset; - - return 0; -} - -bool emitElfStatic::createNewCtorRegion(LinkMap &lmap) { - char *targetData = lmap.allocatedData; - - if( PPC32_WIDTH != addressWidth_ && PPC64_WIDTH != addressWidth_ ) { - assert(!UNKNOWN_ADDRESS_WIDTH_ASSERT); - } - - unsigned trailerSize, headerSize; - - /* Give the new Region a header and trailer */ - Offset headerOffset = lmap.ctorRegionOffset; - Offset trailerOffset; - if( PPC32_WIDTH == addressWidth_ ) { - memcpy(&targetData[headerOffset], &X86_HEADER, sizeof(X86_HEADER)); - trailerOffset = lmap.ctorRegionOffset + lmap.ctorSize - sizeof(X86_TRAILER); - memcpy(&targetData[trailerOffset], &X86_TRAILER, sizeof(X86_TRAILER)); - headerSize = sizeof(X86_HEADER); - trailerSize = sizeof(X86_TRAILER); - }else{ - memcpy(&targetData[headerOffset], &X86_64_HEADER, sizeof(X86_64_HEADER)); - trailerOffset = lmap.ctorRegionOffset + lmap.ctorSize - sizeof(X86_64_TRAILER); - memcpy(&targetData[trailerOffset], &X86_64_TRAILER, sizeof(X86_64_TRAILER)); - headerSize = sizeof(X86_64_HEADER); - trailerSize = sizeof(X86_64_TRAILER); - } - - if( lmap.originalCtorRegion != NULL ) { - /* Determine where the original .ctors section should be placed */ - Offset originalOffset = lmap.ctorRegionOffset + lmap.ctorSize - - trailerSize - (lmap.originalCtorRegion->getDiskSize() - headerSize - trailerSize); - - /* Copy the original .ctors section w/o the header and trailer */ - char *rawRegionData = reinterpret_cast(lmap.originalCtorRegion->getPtrToRawData()); - memcpy(&targetData[originalOffset], &rawRegionData[headerSize], - lmap.originalCtorRegion->getDiskSize() - headerSize - trailerSize); - } - - return true; -} - - -Offset emitElfStatic::layoutNewDtorRegion(LinkMap &lmap) { - /* - * .dtors sections are processed in forward order on Linux x86. So new - * .dtors sections need to be placed after the original .dtors section - */ - - Offset retOffset = lmap.dtorRegionOffset; - retOffset += addressWidth_; - - pair::iterator, bool> result; - if( lmap.originalDtorRegion != NULL ) { - // Account for the original .dtors section (minus the header and trailer) - retOffset += lmap.originalDtorRegion->getDiskSize() - addressWidth_ - addressWidth_; - } - - for(auto reg_it = lmap.newDtorRegions.begin(); reg_it != lmap.newDtorRegions.end(); ++reg_it) { - result = lmap.regionAllocs.insert(make_pair(*reg_it, make_pair(0, retOffset))); - - // If the map already contains this Region, this is a logic error - if( !result.second ) { - return ~0UL; - } - - retOffset += (*reg_it)->getDiskSize(); - } - - retOffset += addressWidth_; - return retOffset; - - return 0; -} - -bool emitElfStatic::createNewDtorRegion(LinkMap &lmap) { - char *targetData = lmap.allocatedData; - - if( PPC32_WIDTH != addressWidth_ && PPC64_WIDTH != addressWidth_ ) { - assert(!UNKNOWN_ADDRESS_WIDTH_ASSERT); - } - - unsigned headerSize, trailerSize; - - /* Give the new Region a header and trailer */ - Offset headerOffset = lmap.dtorRegionOffset; - Offset trailerOffset; - if( PPC32_WIDTH == addressWidth_ ) { - memcpy(&targetData[headerOffset], &X86_HEADER, sizeof(X86_HEADER)); - trailerOffset = lmap.dtorRegionOffset + lmap.dtorSize - sizeof(X86_TRAILER); - memcpy(&targetData[trailerOffset], &X86_TRAILER, sizeof(X86_TRAILER)); - headerSize = sizeof(X86_HEADER); - trailerSize = sizeof(X86_TRAILER); - }else{ - memcpy(&targetData[headerOffset], &X86_64_HEADER, sizeof(X86_64_HEADER)); - trailerOffset = lmap.dtorRegionOffset + lmap.dtorSize - sizeof(X86_64_TRAILER); - memcpy(&targetData[trailerOffset], &X86_64_TRAILER, sizeof(X86_64_TRAILER)); - headerSize = sizeof(X86_64_HEADER); - trailerSize = sizeof(X86_64_TRAILER); - } - - if( lmap.originalDtorRegion != NULL ) { - /* Determine where the original .dtors section should be placed */ - Offset originalOffset = lmap.dtorRegionOffset + headerSize; - - /* Copy the original .dtors section w/o header and trailer */ - char *rawRegionData = reinterpret_cast(lmap.originalDtorRegion->getPtrToRawData()); - memcpy(&targetData[originalOffset], &rawRegionData[headerSize], - lmap.originalDtorRegion->getDiskSize() - headerSize - trailerSize); - } - - return true; - -} - -bool emitElfStatic::isConstructorRegion(Region *reg) { - return ( CTOR_NAME.compare(reg->getRegionName()) == 0 ); - -} - -bool emitElfStatic::isDestructorRegion(Region *reg) { - return ( DTOR_NAME.compare(reg->getRegionName()) == 0 ); -} - -bool emitElfStatic::isGOTRegion(Region *) { - return false; -} - -bool emitElfStatic::isGOTRelocation(unsigned long relType) { - if( PPC32_WIDTH == addressWidth_ ) { - switch(relType) { - case R_PPC_GOT16: - case R_PPC_GOT16_LO: - case R_PPC_GOT16_HI: - case R_PPC_GOT16_HA: - case R_PPC_GOT_TPREL16: - case R_PPC_TLS: - return true; - break; - default: - return false; - break; - } - } else{ - assert(!UNKNOWN_ADDRESS_WIDTH_ASSERT); - } - - return false; -} - -Offset emitElfStatic::getGOTSize(Symtab *, LinkMap &, Offset &) { - return 0; -} - -Offset emitElfStatic::getGOTAlign(LinkMap &) { - return 0; -} - -void emitElfStatic::buildGOT(Symtab *, LinkMap &) { -} - -void emitElfStatic::getExcludedSymbolNames(set &) { -} - -Offset emitElfStatic::allocStubRegions(LinkMap &lmap, Offset) { - // Size 0 - return lmap.stubRegionOffset; -} - -bool emitElfStatic::updateTOC(Symtab *, LinkMap &, Offset) { - return true; -} - - -bool emitElfUtils::updateRelocation(Symtab *obj, relocationEntry &rel, int library_adjust) { - // Currently, only verified on x86 and x86_64 -- this may work on other architectures - Region *targetRegion = obj->findEnclosingRegion(rel.rel_addr()); - if( NULL == targetRegion ) { - rewrite_printf("Failed to find enclosing Region for relocation"); - return false; - } - - unsigned addressWidth = obj->getAddressWidth(); - if( addressWidth == 8 ) { - switch(rel.getRelType()) { - case R_PPC64_IRELATIVE: - case R_PPC64_RELATIVE: - rel.setAddend(rel.addend() + library_adjust); - break; -/* case R_PPC64_JMP_SLOT: - * For PowerPC ABI V2, .plt is a nobit section. - * We do not need to adjust the relocation entry. - */ - default: - //fprintf(stderr, "Unimplemented relType for architecture: %d\n", rel.getRelType()); - //assert(0); - break; - } - } - - // XXX The GOT also holds a pointer to the DYNAMIC segment -- this is currently not - // updated. However, this appears to be unneeded for regular shared libraries. - - // From the SYS V ABI x86 supplement - // "The table's entry zero is reserved to hold the address of the dynamic structure, - // referenced with the symbol _DYNAMIC. This allows a program, such as the - // dynamic linker, to find its own dynamic structure without having yet processed - // its relocation entries. This is especially important for the dynamic linker, because - // it must initialize itself without relying on other programs to relocate its memory - // image." - - // In order to implement this, would have determine the final address of a new .dynamic - // section before outputting the patched GOT data -- this will require some refactoring. - - //rewrite_printf("WARNING: updateRelocation is not implemented on this architecture\n"); - //(void) obj; (void) rel; (void) library_adjust; //silence warnings - - return true; -} - diff --git a/symtabAPI/src/emitElfStatic-ppc64.C b/symtabAPI/src/emitElfStatic-ppc64.C index 500997f7ca..36a9836de5 100644 --- a/symtabAPI/src/emitElfStatic-ppc64.C +++ b/symtabAPI/src/emitElfStatic-ppc64.C @@ -33,6 +33,7 @@ * static executable rewriter */ +#include #include #include #include diff --git a/symtabAPI/src/emitElfStatic-x86.C b/symtabAPI/src/emitElfStatic-x86.C index 2c86510bff..fb95391152 100644 --- a/symtabAPI/src/emitElfStatic-x86.C +++ b/symtabAPI/src/emitElfStatic-x86.C @@ -33,6 +33,7 @@ * static executable rewriter */ +#include #include #include #include diff --git a/symtabAPI/src/emitElfStatic.C b/symtabAPI/src/emitElfStatic.C index c7f125783a..2aea6e0afb 100644 --- a/symtabAPI/src/emitElfStatic.C +++ b/symtabAPI/src/emitElfStatic.C @@ -49,6 +49,7 @@ #include "emitElfStatic.h" #include "debug.h" #include "Object-elf.h" +#include "unaligned_memory_access.h" #if defined(os_freebsd) #define R_X86_64_JUMP_SLOT R_X86_64_JMP_SLOT @@ -1777,14 +1778,14 @@ bool emitElfStatic::buildRela(Symtab *target, Offset globalOffset, unsigned copied = 0; char *data = lmap.allocatedData; - Elf64_Rela *relas = (Elf64_Rela *) &(data[lmap.relRegionOffset]); + auto relas = alignas_cast(&(data[lmap.relRegionOffset])); Region *rela = NULL; target->findRegion(rela, ".rela.plt"); if (rela) { memcpy(relas, rela->getPtrToRawData(), rela->getDiskSize()); copied += rela->getDiskSize(); - relas = (Elf64_Rela *) &(data[lmap.relRegionOffset + rela->getDiskSize()]); + relas = alignas_cast(&(data[lmap.relRegionOffset + rela->getDiskSize()])); } unsigned index = 0; @@ -1803,14 +1804,14 @@ bool emitElfStatic::buildRela(Symtab *target, Offset globalOffset, unsigned copied = 0; char *data = lmap.allocatedData; - Elf32_Rel *rels = (Elf32_Rel *) &(data[lmap.relRegionOffset]); + auto *rels = alignas_cast(&(data[lmap.relRegionOffset])); Region *rel = NULL; target->findRegion(rel, ".rel.plt"); if (rel) { memcpy(rels, rel->getPtrToRawData(), rel->getDiskSize()); copied += rel->getDiskSize(); - rels = (Elf32_Rel *) &(data[lmap.relRegionOffset + rel->getDiskSize()]); + rels = alignas_cast(&(data[lmap.relRegionOffset + rel->getDiskSize()])); } unsigned index = 0; @@ -1825,7 +1826,7 @@ bool emitElfStatic::buildRela(Symtab *target, Offset globalOffset, // and set it to iter->first->getOffset(), AKA the symbol address // We should be writing into .dyninstRELAgot; just have to figure out how. - long *got = (long *) &(data[rels[index].r_offset - globalOffset]); + auto *got = alignas_cast(&(data[rels[index].r_offset - globalOffset])); *got = iter->first->getOffset(); copied += sizeof(Elf32_Rel); diff --git a/symtabAPI/src/emitElfStatic.h b/symtabAPI/src/emitElfStatic.h index 708abf76b5..05b0195c6b 100644 --- a/symtabAPI/src/emitElfStatic.h +++ b/symtabAPI/src/emitElfStatic.h @@ -38,13 +38,15 @@ #include "LinkMap.h" #include "Object.h" +#include +#include #include #include #include #include using namespace std; -#include "boost/tuple/tuple.hpp" +#include "dyncompat/tuple/tuple.hpp" namespace Dyninst{ namespace SymtabAPI{ @@ -396,11 +398,11 @@ class emitElfStatic { bool isStripped_; bool hasRewrittenTLS_; - typedef boost::tuple TOCstub; + typedef dyncompat::tuple TOCstub; std::map stubMap; - Offset getStubOffset(TOCstub &t) { return boost::get<0>(t); } - Offset getNewTOC(TOCstub &t) { return boost::get<1>(t); } - Offset getOldTOC(TOCstub &t) { return boost::get<2>(t); } + Offset getStubOffset(TOCstub &t) { return dyncompat::get<0>(t); } + Offset getNewTOC(TOCstub &t) { return dyncompat::get<1>(t); } + Offset getOldTOC(TOCstub &t) { return dyncompat::get<2>(t); } }; diff --git a/symtabAPI/src/emitWin.h b/symtabAPI/src/emitWin.h index f6da4b9c6f..cfb2f78901 100644 --- a/symtabAPI/src/emitWin.h +++ b/symtabAPI/src/emitWin.h @@ -53,7 +53,7 @@ class emitWin{ const static unsigned int SizeOfSecHeader = 40; //size of section header entry is 40 bytes PCHAR base_addr; //the base address of the mapped image file Offset bit_addr; //the offset of bound import table - unsigned int bit_size; //the size of bound import table + unsigned int bit_size{}; //the size of bound import table Object* obj_nt; Offset PEAlign(Offset dwAddr,Offset dwAlign); unsigned int NumOfTotalAllowedSec(); @@ -62,7 +62,7 @@ class emitWin{ PIMAGE_SECTION_HEADER CreateSecHeader(unsigned int size,PIMAGE_SECTION_HEADER preSecHdr); bool AlignSection(PIMAGE_SECTION_HEADER p); bool writeImpTable(Symtab*); - bool isMoveAhead;//variable indicating whether or not we need to move things ahead to Dos Stub Area + bool isMoveAhead{false};//variable indicating whether or not we need to move things ahead to Dos Stub Area void (*err_func_)(const char*); void log_winerror(void (*err_func)(const char *), const char* msg); diff --git a/symtabAPI/src/indexed_modules.h b/symtabAPI/src/indexed_modules.h new file mode 100644 index 0000000000..d960e0553d --- /dev/null +++ b/symtabAPI/src/indexed_modules.h @@ -0,0 +1,94 @@ +/* + * See the dyninst/COPYRIGHT file for copyright information. + * + * We provide the Paradyn Tools (below described as "Paradyn") + * on an AS IS basis, and do not warrant its validity or performance. + * We reserve the right to update, modify, or discontinue this + * software at any time. We shall have no obligation to supply such + * updates or modifications or any other form of support to you. + * + * By your use of Paradyn, you understand and agree that we (or any + * other person or entity with proprietary rights in Paradyn) are + * under no obligation to provide either maintenance services, + * update services, notices of latent defects, or correction of + * defects for Paradyn. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SYMTAB_INDEXED_MODULES +#define SYMTAB_INDEXED_MODULES + +#include "Module.h" + +#include +#include + +namespace Dyninst { namespace SymtabAPI { + + namespace detail { + // A Module is uniquely identified by its name and offset + struct hash { + size_t operator()(Module *m) const { + size_t seed{0UL}; + dyncompat::hash_combine(seed, m->fileName()); + dyncompat::hash_combine(seed, m->addr()); + return seed; + } + }; + + struct equal { + bool operator()(Module *m1, Module *m2) const { + return m1->fileName() == m2->fileName() && m1->addr() == m2->addr(); + } + }; + } + + class indexed_modules { + tbb::concurrent_unordered_set index; + + public: + void insert(Module *m) { index.insert(m); } + + bool contains(Module *m) const { return index.count(m) != 0UL; } + + std::vector find(std::string const& name) const { + std::vector mods; + std::copy_if(index.begin(), index.end(), std::back_inserter(mods), + [&name](Module *m) { return m->fileName() == name; }); + return mods; + } + + Module *find(Dyninst::Offset offset) const { + for (auto *m : index) { + if (m->addr() == offset) + return m; + } + return nullptr; + } + + bool empty() const { return index.empty(); } + + decltype(index)::iterator begin() { return index.begin(); } + + decltype(index)::iterator end() { return index.end(); } + + decltype(index)::const_iterator cbegin() const { return index.cbegin(); } + + decltype(index)::const_iterator cend() const { return index.cend(); } + }; +}} + +#endif diff --git a/symtabAPI/src/indexed_symbols.hpp b/symtabAPI/src/indexed_symbols.hpp new file mode 100644 index 0000000000..80b0c85540 --- /dev/null +++ b/symtabAPI/src/indexed_symbols.hpp @@ -0,0 +1,131 @@ +#ifndef INDEXED_SYMBOLS_HPP +#define INDEXED_SYMBOLS_HPP + +#include "Symbol.h" +#include "concurrent.h" +#include +#include +#include +#include "dyntypes.h" + +namespace st = Dyninst::SymtabAPI; + +struct indexed_symbols { + typedef Dyninst::dyn_c_hash_map master_t; + typedef std::vector symvec_t; + typedef Dyninst::dyn_c_hash_map by_offset_t; + typedef Dyninst::dyn_c_hash_map by_name_t; + + master_t master; + by_offset_t by_offset; + by_name_t by_mangled; + by_name_t by_pretty; + by_name_t by_typed; + + // Only inserts if not present. Returns whether it inserted. + // Operations on the indexed_symbols compound table. + bool insert(st::Symbol *s) { + Dyninst::Offset o = s->getOffset(); + master_t::accessor a; + if (master.insert(a, std::make_pair(s, o))) { + { + by_offset_t::accessor oa; + by_offset.insert(oa, o); + oa->second.push_back(s); + } + { + by_name_t::accessor ma; + by_mangled.insert(ma, s->getMangledName()); + ma->second.push_back(s); + } + { + by_name_t::accessor pa; + by_pretty.insert(pa, s->getPrettyName()); + pa->second.push_back(s); + } + { + by_name_t::accessor ta; + by_typed.insert(ta, s->getTypedName()); + ta->second.push_back(s); + } + + return true; + } + return false; + } + + // Clears the table. Do not use in parallel. + void clear() { + master.clear(); + by_offset.clear(); + by_mangled.clear(); + by_pretty.clear(); + by_typed.clear(); + } + + // Erases Symbols from the table. Do not use in parallel. + void erase(st::Symbol *s) { + if (master.erase(s)) { + { + by_offset_t::accessor oa; + if (!by_offset.find(oa, s->getOffset())) { + assert(!"by_offset.find(oa, s->getOffset())"); + } + std::remove(oa->second.begin(), oa->second.end(), s); + } + { + by_name_t::accessor ma; + if (!by_mangled.find(ma, s->getMangledName())) { + assert(!"by_mangled.find(ma, s->getMangledName())"); + } + std::remove(ma->second.begin(), ma->second.end(), s); + } + { + by_name_t::accessor pa; + if (!by_pretty.find(pa, s->getPrettyName())) { + assert(!"by_pretty.find(pa, s->getPrettyName())"); + } + std::remove(pa->second.begin(), pa->second.end(), s); + } + { + by_name_t::accessor ta; + if (!by_typed.find(ta, s->getTypedName())) { + assert(!"by_typed.find(ta, s->getTypedName())"); + } + std::remove(ta->second.begin(), ta->second.end(), s); + } + } + } + + // Iterator for the symbols. Do not use in parallel. + class iterator { + master_t::iterator m; + + public: + using iterator_category = std::forward_iterator_tag; + using value_type = st::Symbol *; + using difference_type = std::ptrdiff_t; + using pointer = value_type *; + using reference = value_type &; + + iterator(master_t::iterator i) : m(i) {} + bool operator==(const iterator &x) const { return m == x.m; } + bool operator!=(const iterator &x) const { return !operator==(x); } + st::Symbol *const &operator*() const { return m->first; } + st::Symbol *const *operator->() const { return &operator*(); } + iterator &operator++() { + ++m; + return *this; + } + iterator operator++(int) { + iterator old(m); + operator++(); + return old; + } + }; + + iterator begin() { return iterator(master.begin()); } + iterator end() { return iterator(master.end()); } +}; + +#endif diff --git a/symtabAPI/src/parseDwarf.C b/symtabAPI/src/parseDwarf.C index ec5d553fbe..260f56abc3 100644 --- a/symtabAPI/src/parseDwarf.C +++ b/symtabAPI/src/parseDwarf.C @@ -89,8 +89,6 @@ std::string convertCharToString(char *ptr) return str; } -/* extern void pd_dwarf_handler( Dwarf_Error, Dwarf_Ptr ); */ - void Object::parseDwarfTypes( Symtab *) { assert(0); diff --git a/symtabAPI/src/parseStab.C b/symtabAPI/src/parseStab.C deleted file mode 100644 index 4cfffd2d4a..0000000000 --- a/symtabAPI/src/parseStab.C +++ /dev/null @@ -1,2423 +0,0 @@ -/* - * See the dyninst/COPYRIGHT file for copyright information. - * - * We provide the Paradyn Tools (below described as "Paradyn") - * on an AS IS basis, and do not warrant its validity or performance. - * We reserve the right to update, modify, or discontinue this - * software at any time. We shall have no obligation to supply such - * updates or modifications or any other form of support to you. - * - * By your use of Paradyn, you understand and agree that we (or any - * other person or entity with proprietary rights in Paradyn) are - * under no obligation to provide either maintenance services, - * update services, notices of latent defects, or correction of - * defects for Paradyn. - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include -#include - -#include "symutil.h" -#include "Symtab.h" // For looking up compiler type -#include "Symbol.h" -#include "Function.h" -#include "Variable.h" -#include "Module.h" -#include "Collections.h" -#include "annotations.h" -#include "common/src/headers.h" -#include "compiler_annotations.h" -#include "Type-mem.h" - -#include "debug.h" - -using namespace Dyninst; -using namespace Dyninst::SymtabAPI; - -/* -#include "BPatch.h" -#include "debug.h" -*/ - -extern std::string symt_current_func_name; -extern std::string symt_current_mangled_func_name; -extern Function *symt_current_func; -namespace Dyninst{ -namespace SymtabAPI{ - std::string parseStabString(Module *mod, int linenum, char *stabstr, - int framePtr, typeCommon *commonBlock = NULL); -} -} - -// Forward references for parsing routines -static int parseSymDesc(char *stabstr, int &cnt); -static boost::shared_ptr parseConstantUse(Module *, char *stabstr, int &cnt); -static char *parseTypeDef(Module *, char *stabstr, - const char *name, int ID, unsigned int sizeHint = 0); -static int parseTypeUse(Module*, char *&stabstr, int &cnt, - const char *name); -static inline bool isSymId(char ch); -static std::string getIdentifier(char *stabstr, int &cnt, bool stopOnSpace=false); - -static std::string currentRawSymbolName; - -std::string convertCharToString(const char *ptr){ - if(ptr) - return ptr; - else - return ""; -} - -// -// Start of code to parse Stab information. -// The structure of this code is a recursive decent parser that parses -// information in stab records and builds up the corresponding BPatch_types. -// -// Each non-terminal in the grammer has a function of the form parse. -// -// The grammar for a non-terminal appears in the comments just before -// the non-terminal parsing function -// - -void vectorNameMatchKLUDGE(char *demangled_sym, std::vector &bpfv, std::vector &matches) -{ - // iterate through all matches and demangle names with extra parameters, compare - for (unsigned int i = 0; i < bpfv.size(); ++i) { - std::string l_mangled; - std::vector syms; - bpfv[i]->getSymbols(syms); - if (syms.size()) { - l_mangled = syms[0]->getMangledName(); - - std::string l_demangled_raw = P_cplus_demangle(l_mangled); - - if (l_demangled_raw == demangled_sym) { - matches.push_back(i); - } - } - } /* end iteration over function vector */ -} - -Function *mangledNameMatchKLUDGE(const char *pretty, const char *mangled, - Module *mod) -{ - - std::vector bpfv; - if (!mod->exec()->findFunctionsByName(bpfv, pretty)) { - //cerr << __FILE__ << __LINE__ << ": KLUDGE Cannot find " << pretty << endl; - return NULL; // no pretty name hits, expecting multiple - } - - //cerr << __FILE__ << __LINE__ << ": mangledNameMatchKLUDGE: language = " - //<< mod->getLanguageStr() << endl; - - if (lang_Fortran_with_pretty_debug == mod->language()) { - // debug function symbols are presented in "demangled" style. - if (bpfv.size() == 1) - return bpfv[0]; - else { - cerr << __FILE__ << __LINE__ << ": FIXME!" << endl; - return NULL; - } - } - - // demangle name with extra parameters - std::string demangled = P_cplus_demangle( mangled, true ); - char *demangled_sym = strdup(demangled.c_str()); - - std::vector matches; - - vectorNameMatchKLUDGE(demangled_sym, bpfv, matches); - - Function *ret = NULL; - - if (matches.size() == 1) {ret = bpfv[matches[0]]; goto clean_up;} - if (matches.size() > 1) goto clean_up; - - // check in the uninstrumentable pile - bpfv.clear(); - matches.clear(); - - vectorNameMatchKLUDGE(demangled_sym, bpfv, matches); - if (matches.size() == 1) {ret = bpfv[matches[0]]; goto clean_up;} - if (matches.size() > 1) goto clean_up; - - clean_up: - free( demangled_sym ); - return ret; -} - -// This function takes the stab stabstring and parses it to create a new -// type or variable object. This function only defines the type/variable -// name and ID. -// -// = : | -// :c | -// :f | -// :f,, | -// :F | -// :G | -// :r | -// :S | -// :[pPr] | -// ::T | -// :t | -// :T | -// :v | -// :V | -// :Y[Tc|Ts] -// -// = | ; -// - -std::string Dyninst::SymtabAPI::parseStabString(Module *mod, int linenum, char *stabstr, - int framePtr, typeCommon *commonBlock) -{ - typeCollection *tc = typeCollection::getModTypeCollection(mod); - int cnt; - int ID = 0; - int symdescID = 0; - int funcReturnID = 0; - Function *fp = NULL; - boost::shared_ptr ptrType; - boost::shared_ptr newType = NULL; // For new types to add to the collection - localVar *locVar = NULL; - cnt= 0; - - types_printf("parseStabString, mod %p/%s, linenum %d, stabstr %s\n", - (void*)mod, - (mod != NULL) ? mod->fileName().c_str() : "NULL", - linenum, - stabstr); - - std::string fName = mod->fileName(); - - /* get type or variable name */ - std::string mangledname = getIdentifier( stabstr, cnt ); - - currentRawSymbolName = mangledname; - std::string name = P_cplus_demangle( mangledname ); - - if ( !name.empty() && stabstr[cnt] != ':' ) - { - types_printf("\t returning name %s\n", name.c_str()); - return name; - } - - if (stabstr[cnt] == ':') - { - // skip to type part - cnt++; - } - - if (isSymId(stabstr[cnt])) - { - /* instance of a predefined type */ - - ID = parseSymDesc(stabstr, cnt); - - if (stabstr[cnt] == '=') - { - /* More Stuff to parse, call parseTypeDef */ - - stabstr = parseTypeDef(mod, (&stabstr[cnt+1]), name.c_str(), ID); - cnt = 0; - ptrType = tc->findOrCreateType(ID, Type::share); - if (!symt_current_func) - { - // XXX-may want to use N_LBRAC and N_RBRAC to set function scope - // -- jdd 5/13/99 - // Still need to add to local variable list if in a function - - std::string modName = mod->fileName(); - //bperr("%s[%d] Can't find function %s in module %s\n", __FILE__, __LINE__, - // symt_current_mangled_func_name.c_str(), modName); - //bperr("Unable to add %s to local variable list in %s\n", - // name.c_str(), symt_current_func_name.c_str()); - } - else - { - locVar = new localVar(name, ptrType, fName, linenum, symt_current_func); - VariableLocation loc; - loc.stClass = storageRegOffset; - loc.refClass = storageNoRef; - loc.frameOffset = framePtr; - locVar->addLocation(loc); - if (!ptrType) { - //bperr("adding local var with missing type %s, type = %d\n", - // name, ID); - } - - symt_current_func->addLocalVar(locVar); - } - } - else if (symt_current_func) - { - // Try to find the BPatch_Function - ptrType = tc->findOrCreateType( ID, Type::share); - - locVar = new localVar(name, ptrType, fName, linenum, symt_current_func); - VariableLocation loc; - loc.stClass = storageRegOffset; - loc.refClass = storageNoRef; - loc.frameOffset = framePtr; - locVar->addLocation(loc); - - if (!ptrType) - { - ////bperr("adding local var with missing type %s, type = %d\n", - // name, ID); - } - - symt_current_func->addLocalVar(locVar); - } - } - else if (stabstr[cnt]) - { - std::vector bpfv; - - switch (stabstr[cnt]) { - case 'f': /*Local Function*/ - { - std::string scopeName; - std::string lfuncName; - cnt++; - - symt_current_func_name = name; - symt_current_mangled_func_name = mangledname; - - funcReturnID = parseTypeUse(mod, stabstr, cnt, name.c_str()); - - if (stabstr[cnt]==',') - { - cnt++; /*skip the comma*/ - - /* Local Function Name */ - lfuncName = getIdentifier(stabstr, cnt); - - assert(stabstr[cnt] == ','); - cnt++; /*skip the comma*/ - - /* Scope Name of Local Function */ - scopeName = getIdentifier(stabstr, cnt); - - if (stabstr[cnt]) - { - //bperr("Extra: %s\n", &stabstr[cnt]); - } - } - - if (!scopeName.length()) - { - // Not an embeded function - - ptrType = tc->findOrCreateType(funcReturnID, Type::share); - /* - The shared_ptr type_Untyped is static, so this - otherwise unsafe operation is safe. - */ - if ( !ptrType) ptrType = Symtab::type_Untyped(); - - if (!(mod->exec()->findFunctionsByName(bpfv, name))) - { - //showInfoCallback(string("missing local function ") + - // name + "\n"); - // It's very possible that we might not find a function - // that's a weak reference, and defined in multiple places - // as we only store an object from the last definition - // - // 12/08 - not sure this is necessary anymore - // due to the Function abstraction - fp = NULL; - } - else - { - if (bpfv.size() > 1) - { - // warn if we find more than one function with current_func_name - char msg[1024]; - sprintf(msg, "%s[%d]: found %d functions with name %s, using the first", - __FILE__, __LINE__, (int)bpfv.size(), name.c_str()); - // BPatch::bpatch->reportError(BPatchWarning, 0, msg); - - } - else if (!bpfv.size()) - { - //bperr("%s[%d]: SERIOUS: found 0 functions with name %s", - // __FILE__, __LINE__, name.c_str()); - break; - } - - fp = bpfv[0]; - // set return type. - fp->setReturnType(ptrType); - } - } - else - { - //bperr("%s is an embedded function in %s\n",name.c_str(), scopeName.c_str()); - } - - symt_current_func = fp; - // skip to end - SunPro Compilers output extra info here - jkh 6/9/3 - cnt = strlen(stabstr); - - break; - } - - case 'F':/* Global Function */ - { - cnt++; /*skipping 'F' */ - - funcReturnID = parseTypeUse(mod, stabstr, cnt, name.c_str()); - - symt_current_func_name = name; - symt_current_mangled_func_name = mangledname; - - // - // For SunPro compilers there may be a parameter list after - // the return - // - - while (stabstr[cnt] == ';') - { - cnt++; // skip ';' - (void) parseTypeUse(mod, stabstr, cnt, ""); - } - - // skip to end - SunPro Compilers output extra info here - jkh 6/9/3 - cnt = strlen(stabstr); - - ptrType = tc->findOrCreateType(funcReturnID, Type::share); - if (!ptrType) ptrType = Symtab::type_Untyped(); - - std::vectorfpv; - if (!mod->exec()->findFunctionsByName(fpv, symt_current_mangled_func_name)) - //if (!mod->findSymbol(fpv, symt_current_mangled_func_name, Symbol::ST_FUNCTION, true)) - { - std::string modName = mod->fileName(); - - if (NULL == (fp = mangledNameMatchKLUDGE(symt_current_func_name.c_str(), - symt_current_mangled_func_name.c_str(), mod))) - { - //bpwarn("%s L%d - Cannot find global function with mangled name '%s' or pretty name '%s' with return type '%s' in module '%s', possibly extern\n", - // __FILE__, __LINE__, - // symt_current_mangled_func_name.c_str(), current_func_name.c_str(), - // ((ptrType->getMangledName() == NULL) ? "" : ptrType->getMangledName()), - // modName); - //char prefix[5]; - //strncpy(prefix, current_mangled_func_name, 4); - //prefix[4] = '\0'; - // mod->dumpMangled(prefix); - break; - } - } - fp = fpv[0]; - - fp->setReturnType(ptrType); - symt_current_func = fp; - fpv.clear(); - } - break; - - case 'U':/* Class Declaration - for Sun Compilers - jkh 6/6/03 */ - case 'E':/* Extern'd Global ??? - undocumented type for Sun Compilers - jkh 6/6/03 */ - case 'G':/* Global Varaible */ - cnt++; /* skip the 'G' */ - - { - /* Get variable type number */ - symdescID = parseTypeUse(mod, stabstr, cnt, name.c_str()); - boost::shared_ptr BPtype; - - BPtype = tc->findOrCreateType(symdescID, Type::share); - if (BPtype) - { - Module *toUse = mod; - std::vector ret; - bool result = mod->findVariablesByName(ret, name); - if (!result) { - // Might be in a different module... - if (mod->exec()->getDefaultModule()->findVariablesByName(ret, name)) - toUse = mod->exec()->getDefaultModule(); - } - for (unsigned i=0; isetType(BPtype); - } - - typeCollection *tc_to_use = typeCollection::getModTypeCollection(toUse); - tc_to_use->addGlobalVariable(BPtype); - } - // else // what should be done in the else case??? - // the break was (probably wrongly?) part of the else - break; - } - - case 'P': // function parameter passed in a register (GNU/Solaris) - case 'R': // function parameter passed in a register - case 'v': // Fortran Local Variable - case 'X': // Fortran function return Variable (e.g. function name) - case 'p': - { - // Function Parameter - cnt++; /* skip the 'p' */ - - /* Get variable type number */ - symdescID = parseTypeUse(mod, stabstr, cnt, name.c_str()); - - if (stabstr[cnt] == ';') - { - // parameter type information, not used for now - cnt = strlen(stabstr); - } - // else if (stabstr[cnt]) - // { - //bperr( "\tMore to parse func param %s\n", &stabstr[cnt]); - //bperr( "\tFull String: %s\n", stabstr); - //} - - ptrType = tc->findOrCreateType(symdescID, Type::share); - if (!ptrType) ptrType = Symtab::type_Untyped(); - - localVar *param; - - param = new localVar(name, ptrType, fName, linenum, symt_current_func); - VariableLocation loc; - loc.stClass = storageRegOffset; - loc.refClass = storageNoRef; - loc.frameOffset = framePtr; - param->addLocation(loc); - - if (symt_current_func) - { - symt_current_func->addParam(param); - } - - break; - } - - case 'c': /* constant */ - { - cnt++; /*move past the 'c' */ - if (symt_current_mangled_func_name.length()) - { - std::vectorfpv; - if (mod->exec()->findFunctionsByName(fpv, symt_current_mangled_func_name)) - { - // found function, add parameter - fp = fpv[0]; - symt_current_func = fp; - } - fpv.clear(); - } - - ptrType = parseConstantUse(mod, stabstr, cnt); - - if (!ptrType) ptrType = Symtab::type_Untyped(); - - localVar *var; - var = new localVar(name, ptrType, fName, linenum, symt_current_func); - VariableLocation loc; - loc.stClass = storageRegOffset; - loc.refClass = storageNoRef; - loc.frameOffset = 0; - var->addLocation(loc); - if (symt_current_func) { - symt_current_func->addParam(var); - } - } - break; - - case 'r':/* Register Variable */ - cnt++; /*move past the 'r'*/ - /* get type reference */ - - symdescID = parseSymDesc(stabstr, cnt); - break; - - case 'S':/* Global Static Variable */ - { - cnt++; /*move past the 'S'*/ - - /* get type reference */ - symdescID = parseTypeUse(mod, stabstr, cnt, name.c_str()); - - // lookup symbol and set type - boost::shared_ptr BPtype; - - std::string nameTrailer; - if (name.find(".") < name.length()) - { - std::string defaultNameSpace; - defaultNameSpace = name.substr(0,name.find(".")); - nameTrailer = name.substr(name.find(".")+1,name.length()-name.find(".")-1); - mod->setDefaultNamespacePrefix(defaultNameSpace); - } - else - { - nameTrailer = name; - } - - BPtype = tc->findOrCreateType(symdescID, Type::share); - - if (BPtype) - { - Symtab *img = mod->exec(); - std::vectorsyms; - if (img->findSymbol(syms, - nameTrailer, - Symbol::ST_OBJECT, - mangledName) || - img->findSymbol(syms, - nameTrailer, - Symbol::ST_OBJECT, - mangledName, - true)) - { - - tc->addGlobalVariable(BPtype); - } - } - - //else - //{ - //bperr("ERROR: unable to find type #%d for variable %s\n", - // symdescID, nameTrailer.c_str()); - //} - - break; - } - - case 't': // Type Name - cnt++; /*move past the 't'*/ - - /* get type reference */ - symdescID = parseSymDesc(stabstr, cnt); - - //Create Type. - if (stabstr[cnt] == '=') - { - /* More Stuff to parse, call parseTypeDef */ - //char *oldstabstr = stabstr; - stabstr = parseTypeDef(mod, (&stabstr[cnt+1]), name.c_str(), symdescID); - cnt = 0; - } - else - { - //Create Type defined as a pre-exisitng type. - - ptrType = tc->findOrCreateType(symdescID, Type::share); - if (!ptrType) - { - ptrType = Symtab::type_Untyped(); - } - - // We assume that IDs are unique per type. Instead of reusing the - // underlying base ID, use a SymtabAPI-generated ID. - - auto t = Type::make_shared(ptrType, name); - - if (t) - { - tc->addOrUpdateType(t); - } - } - break; - - case ':': // :T... - skip ":" and parse 'T' - if ((stabstr[cnt+1] == 't') || (stabstr[cnt+1] == 'T')) - { - // parse as a normal typedef - parseStabString(mod, linenum, &stabstr[cnt+1], framePtr); - } - - // else - //{ - //bperr("Unknown type seen %s\n", stabstr); - //} - - break; - - case 'T':/* Aggregate type tag -struct, union, enum */ - cnt++; /*move past the 'T'*/ - - if (stabstr[cnt] == 't') - { - //C++ struct tag "T" and type def "t" - ////bperr("SKipping C++ Identifier t of Tt\n"); - cnt++; //skip it - } - - /* get type reference */ - symdescID = parseSymDesc(stabstr, cnt); - - //Create Type. - if (stabstr[cnt] == '=') - { - /* More Stuff to parse, call parseTypeDef */ - stabstr = parseTypeDef(mod,(&stabstr[cnt+1]),name.c_str(),symdescID); - cnt = 0; - - //if (stabstr[0]) - //{ - //bperr( "\tMore to parse aggregate type %s\n", (&stabstr[cnt])); - //bperr("\tFull String: %s\n", stabstr); - //} - - } - else - { - //Create Type defined as a pre-exisitng type. - - newType = Type::createPlaceholder(symdescID, name); - (void)newType; // unused... - } - - break; - - case 'V':/* Local Static Variable (common block vars too) */ - cnt++; /*move past the 'V'*/ - - // //bperr("parsing 'v' type of %s\n", stabstr); - /* Get variable type number */ - { - symdescID = parseTypeUse(mod, stabstr, cnt, name.c_str()); - - // lookup symbol and set type - auto BPtype = tc->findOrCreateType(symdescID, Type::share); - - if (!BPtype) - { - //bperr("ERROR: unable to find type #%d for variable %s\n", - // symdescID, name.c_str()); - break; - } - - if (commonBlock) - { - /* This variable is in a common block */ - /* add it only if not already there, common block - are re-defined for each subroutine but subroutines - define only the member they care about - */ - - bool found = false; - auto fields = commonBlock->getFields(); - if (fields) - { - for (unsigned int i=0; i < fields->size(); i++) - { - if (name == (*fields)[i]->getName()) - { - found = true; - break; - } - - int start1, start2, end1, end2; - start1 = (*fields)[i]->getOffset(); - end1 = start1 + (*fields)[i]->getSize(); - start2 = framePtr; - end2 = framePtr + BPtype->getSize(); - if ( ((start2 >= start1) && (start2 < end1)) - || ((start1 >= start2) && (start1 < end2)) ) - { - /* common block aliasing detected */ - //bpwarn("WARN: EQUIVALENCE used in %s: %s and %s\n", - // current_func_name.c_str(), name.c_str(), (*fields)[i]->getName()); - - found = true; - break; - } - } - } - - if (!found) - { - commonBlock->addField(name, BPtype, framePtr); - } - } - else - { - // put it into the local variable scope - if (symt_current_func) - { - locVar = new localVar(name, BPtype, fName, linenum, symt_current_func); - VariableLocation loc; - loc.stClass = storageAddr; - loc.refClass = storageNoRef; - loc.frameOffset = framePtr; - locVar->addLocation(loc); - - symt_current_func->addLocalVar(locVar); - } - - //else - //{ - //bperr("Unable to add %s to local variable list in %s\n", - // name.c_str(),current_func_name.c_str()); - //} - } - break; - } - case 'l': - // These are string literals, of the form - // name:l(type);value - // where type must be predefined, and value of of type type. - // It should be safe to ignore these. - - cnt = strlen(stabstr); - break; - - case 'Y': // C++ specific stuff - cnt++; // Skip past the 'Y' - if (stabstr[cnt] == 'I') - { - /* Template instantiation */ - cnt++; // skip past the I; - if (stabstr[cnt] == 'f') /* Template function */ - { - while (stabstr[cnt] != '@') cnt++; - cnt++; // Skip past '@' - cnt++; // Skip past ';' - cnt++; // Skip past ';' - while (stabstr[cnt] != ':') cnt++; - // Create fake stab string that cuts out template garbage - char *dupstring = strdup(stabstr); - strcpy(dupstring, mangledname.c_str()); - strcat(dupstring, stabstr+cnt); - parseStabString(mod, linenum, dupstring, framePtr, commonBlock); - free(dupstring); - } - } - cnt = strlen(stabstr); - break; - - default: - //bperr( "Unknown symbol descriptor: %c\n", stabstr[cnt]); - //bperr( " : %s\n", stabstr); - break; - } - } - - return(&stabstr[cnt]); -} /* end of parseStabString */ - - -// -// Is the current character a valid prefix for a symDesc non-terminal? -// -inline bool isSymId(char ch) -{ - return ((ch == '(') || isdigit(ch) || (ch == '-')); -} - -// -// parse a Symbol Descriptor ID -// symDesc = | (,) -// -int parseSymDesc(char *stabstr, int &cnt) -{ - int id; - int lid; - int hid; - int sign = 1; - bool newForm = false; - - hid = 0; //file-number - // parse both an int and (int,int) format (file-number, type ID) - if (stabstr[cnt] == '(') { - cnt++; - while (isdigit(stabstr[cnt])) { - hid = hid * 10 + stabstr[cnt] - '0'; - cnt++; - } - - // skip "," - if (stabstr[cnt] == ',') cnt++; - newForm = true; - } - - if (stabstr[cnt] == '-') { - sign = -1; - cnt++; - } - - lid = 0; //type ID - while (isdigit(stabstr[cnt])) { - lid = lid * 10 + stabstr[cnt] - '0'; - cnt++; - } - if( hid != 0 ) - assert(lid < 65536); - - // skip closing ')' - if (newForm) cnt++; - - id = hid * 65536 + lid; - id = id * sign; - - return id; -} - -// -// parse an identifier up to a ":" or "," or ";" -// -std::string getIdentifier( char *stabstr, int &cnt, bool stopOnSpace ) { - int i = 0; - int brCnt = 0; - bool idChar = true; - - while( idChar ) { - switch( stabstr[ cnt + i ] ) { - case '<': - case '(': - brCnt++; - i++; - break; - - case '>': - case ')': - brCnt--; - i++; - break; - - case ' ': - if ( !stopOnSpace ) { - i++; - break; - } // else fall through - case '\0': - case ':': - case ',': - case ';': - /* Handle case of '::' */ - if ( stabstr[ cnt + i ] == ':' && stabstr[ cnt + i + 1 ] == ':' && - (stabstr[ cnt + i + 2 ] == '_' || isalpha(stabstr[ cnt + i + 2 ])) ) { - i+=3; - break; - } - /* If we're inside a bracket and we haven't reached - the end of the string, continue. */ - if( brCnt != 0 && stabstr[ cnt + i ] != '\0' ) { - i++; - } -// else if( brCnt ) { -// //bperr( "Failed to find identifier in stabstring '%s;\n", stabstr ); -// idChar = false; -// } - else { - idChar = false; - } - break; - - default: - i++; - break; - } /* end switch */ - } /* end while */ - - char * identifier = (char *)malloc( i + 1 ); - assert( identifier ); - - strncpy( identifier, & stabstr[cnt], i ); - identifier[i] = '\0'; - cnt += i; - - std::string pd_identifier = identifier; - free(identifier); - return pd_identifier; - } /* end getIdentifier() */ - -// -// getFieldName -// -// A simplified version of getIdentifier, it only cares about finding a ':' -// - -char * getFieldName( char *stabstr, int &cnt) { - int i = 0; - bool idChar = true; - - while ( idChar ) { - switch( stabstr[ cnt + i ] ) { - case ':': - idChar = false; - break; - default: - i++; - } - } - - char * identifier = (char *) malloc(i + 1); - assert(identifier); - - strncpy(identifier, &stabstr[cnt], i); - identifier[i] = '\0'; - cnt += i; - - return identifier; -} - -// -// Parse a use of a type. -// -// = | = -// -static int parseTypeUse(Module *mod,char *&stabstr, int &cnt, - const char *name) -{ - int ret = parseSymDesc(stabstr, cnt); - - if (stabstr[cnt] == '=') { - /* More Stuff to parse, call parseTypeDef */ - stabstr = parseTypeDef(mod, (&stabstr[cnt+1]), name, ret); - cnt = 0; - } - return ret; -} - -// -// parseCrossRef - internal struct/union pointer -// -// = [s|u|e] -// -static char *parseCrossRef(typeCollection *moduleTypes,const char * /*name*/, - int ID, char *stabstr, int &cnt) -{ - std::string temp; - boost::shared_ptr newType; - char xreftype; - cnt++; /* skip 'x'*/ - - if ((stabstr[cnt] == 's') || // struct - (stabstr[cnt] == 'u') || // union - (stabstr[cnt] == 'e')) { // enum - xreftype = stabstr[cnt++]; - - temp = getIdentifier(stabstr, cnt); - cnt++; /*skip ':' */ - - // Find type that this one points to. - boost::shared_ptr ptrType = moduleTypes->findType(temp.c_str(), Type::share); - if (!ptrType) { - // This type name hasn't been seen before. Create the - // skeleton for it, and we'll update it later when we actually see - // it - if (xreftype == 'e') { - newType = moduleTypes->addOrUpdateType(Type::make_shared(ID, temp)); - } else if (xreftype == 'u') { - newType = moduleTypes->addOrUpdateType(Type::make_shared(ID, temp)); - } else { - newType = moduleTypes->addOrUpdateType(Type::make_shared(ID, temp)); - } - assert(newType); - } - } else { - /* don't know what it is?? */ - - temp = getIdentifier(stabstr, cnt); - cnt++; /*skip ':' */ - } - - return( &(stabstr[cnt])); -} - -// -// parse the definition of an array. -// arrayDef = ar;;; | -// ar;;; | -// A -// -static boost::shared_ptr parseArrayDef(Module *mod, const char *name, - int ID, char *&stabstr, int &cnt, unsigned int sizeHint) -{ - typeCollection *tc = typeCollection::getModTypeCollection(mod); - char *symdesc; - int symdescID; - int elementType; - boost::shared_ptr newType; - boost::shared_ptr ptrType; - int lowbound, hibound; - - // format is ar;;; - - assert(stabstr[cnt] == 'a' || stabstr[cnt] == 'A'); - - if (stabstr[cnt ++] == 'A') { - // Open array - lowbound = 1; - hibound = 0; - elementType = parseSymDesc(stabstr, cnt); - ptrType = tc->findOrCreateType(elementType, Type::share); - } else { - // Regular (maybe) array - - if (stabstr[cnt] != 'r') { - //bperr("unknown array definition seen %s\n", &stabstr[cnt]); - return(NULL); - } - - /* array with range */ - symdesc = &(stabstr[cnt]); - - cnt++; /* skip 'r' */ - - symdescID = parseTypeUse(mod, stabstr, cnt, name); - - cnt++; /* skip semicolon */ - lowbound = parseSymDesc(stabstr, cnt); - - cnt++; /* skip semicolon */ - if (stabstr[cnt] == 'J') { - /* Fortran unbounded array */ - hibound = 0; - cnt++; - } else if (stabstr[cnt] == 'T') { - /* Fortran runtime bound array - Txx is the form (xx=digits)*/ - hibound = 0; - cnt++; - while (isdigit(stabstr[cnt])) cnt++; - } else { - hibound = parseSymDesc(stabstr, cnt); - } - - cnt++; /* skip semicolon */ - elementType = parseSymDesc(stabstr, cnt); - - if (stabstr[cnt] == 'a') - { - /* multi dimensional array - Fortran style */ - /* it has no valid id, so we give it a known duplicate */ - ptrType = parseArrayDef(mod, name, 0, stabstr, cnt, sizeHint); - } - else - { - if (stabstr[cnt] == '=') - { - /* multi dimensional array */ - char *temp; - temp = parseTypeDef(mod, &(stabstr[cnt+1]), NULL, elementType); - /* parseTypeDef uses old style of returning updated stabstr, - but parseArrayDef function needs to return an updated cnt. - This simple hack updates cnt based on how far parseTypDef - advances it. jkh 12/4/00 */ - cnt = temp-stabstr; - if (stabstr[cnt] == ':') { - //C++ stuff - ////bperr("Skipping C++ rest of array def: %s\n",name ); - while (stabstr[cnt] != ';') cnt++; - } - } - ptrType = tc->findOrCreateType(elementType, Type::share); - } - } - - // //bperr("Symbol Desriptor: %s Descriptor ID: %d Type: %d, Low Bound: %d, Hi Bound: %d,\n", symdesc, symdescID, elementType, lowbound, hibound); - (void)symdesc; (void)symdescID; // otherwise unused symbols from above - - - if (ptrType) { - // Create new type - field in a struct or union - std::string tName = convertCharToString(name); - - auto newAType = Type::make_shared(ID, ptrType, lowbound, hibound, tName, sizeHint); - // Add to Collection - newType = tc->addOrUpdateType(newAType); - - return newAType; - } - - // //bperr( "parsed array def to %d, remaining %s\n", cnt, &stabstr[cnt]); - return newType; -} - -int guessSize(const char *low, const char *hi) -{ - long long l, h; - - if (low[0] == '0') - sscanf(low, "%llo", (unsigned long long *)&l); - else - sscanf(low, "%lld", &l); - if (hi[0] == '0') - sscanf(hi, "%llo", (unsigned long long *)&h); - else - sscanf(hi, "%lld", &h); - - /* - if (( low[0]=='-' && l < -2147483648LL ) - || ( l > || ( h > 2147483647LL)) - return 8; - else if (( l < -32768 ) || ( h > 32767 )) - return 4; - else if (( l < -128 ) || ( h > 127 )) - return 2; - else - return 1; - */ - if (l < 0) { // Must be signed - if (l < -2147483648LL || h > 0x7fffffffLL) - return 8; - else if (l < 0xffff8000 || h > 0x7fff) - return 4; - else if (l < 0xffffff80 || h > 0x7f) - return 2; - else - return 1; - } else { - if (h > 0xffffffffLL) - return 8; - else if (h > 0xffff) - return 4; - else if (h > 0xff) - return 2; - else - return 1; - } -} - -#if defined(i386_unknown_linux2_0) \ - || defined(x86_64_unknown_linux2_4) /* Blind duplication - Ray */ -// -// parse range type of the form: -// -// = r;;; -// -static char *parseRangeType(Module *mod, const char *name, int ID, - char *stabstr, unsigned int sizeHint = 0) -{ - int cnt, i, symdescID; - //int sign = 1; - boost::shared_ptr baseType; - - cnt = i = 0; - - assert(stabstr[0] == 'r'); - cnt++; - - // range index type - not used - symdescID = parseSymDesc(stabstr, cnt); - - typeCollection *tc = typeCollection::getModTypeCollection(mod); - if (!mod || !tc) - { - return NULL; - } - else - { - baseType = tc->findType(symdescID, Type::share); - } - - // //bperr("\tSymbol Descriptor: %c and Value: %d\n",tmpchar, symdescID); - - cnt++; /* Discarding the ';' */ - i=0; - if (stabstr[cnt] == '-' ) { - i++; - } - - /* Getting type range or size */ - - while (isdigit(stabstr[cnt+i])) i++; - - char *low = (char *)malloc(sizeof(char)*(i+1)); - if(!strncpy(low, &(stabstr[cnt]), i)) - /* Error copying size/range*/ - exit(1); - low[i] = '\0'; - - cnt = cnt + i + 1; /* Discard other Semicolon */ - i = 0; - if((stabstr[cnt]) == '-') { - i++; /* discard '-' for (long) unsigned int */ - } - //Find high bound - while (isdigit(stabstr[cnt+i])) i++; - char *hi = (char *)malloc(sizeof(char)*(i+1)); - if(!strncpy(hi, &(stabstr[cnt]), i)) - /* Error copying upper range */ - exit(1); - hi[i] = '\0'; - - int j = atol(hi); - - if (j == 0) { - //Size - int size = atol(low); - - //Add to Collection - tc->addOrUpdateType(Type::make_shared(ID, size, name)); - } - else { - //Range - //Create new type - boost::shared_ptr newType; - std::string tName = convertCharToString(name); - - errno = 0; - long low_conv = strtol(low, NULL, 10); - if (errno) - { - low_conv = LONG_MIN; - } - - errno = 0; - long hi_conv = strtol(hi, NULL, 10); - if (errno) - { - hi_conv = LONG_MAX; - } - - if (baseType == NULL) - newType = Type::make_shared(ID, sizeHint ? sizeHint / 8 : guessSize(low,hi), - low_conv, hi_conv, tName); - else - newType = Type::make_shared(ID, sizeHint ? sizeHint / 8 : baseType->getSize(), - low_conv, hi_conv, tName); - //Add to Collection - tc->addOrUpdateType(newType); - } - free(low); - free(hi); - hi=low=NULL; - - cnt = cnt + i; - if( stabstr[cnt] == ';') - cnt++; - - return(&(stabstr[cnt])); -} - -#else -// -// parse range type of the form: -// -// = r;;; -// -static char *parseRangeType(Module *mod, const char *name, int ID, - char *stabstr, unsigned int sizeHint = 0) -{ - int cnt, i, symdescID; - boost::shared_ptr baseType; - - cnt = i = 0; - - assert(stabstr[0] == 'r'); - cnt++; - - // range index type - symdescID = parseSymDesc(stabstr, cnt); - - typeCollection *tc = typeCollection::getModTypeCollection(mod); - baseType = tc->findType(symdescID, Type::share); - - // //bperr("\tSymbol Descriptor: %c and Value: %d\n",tmpchar, symdescID); - - cnt++; /* Discarding the ';' */ - i=0; - if (stabstr[cnt] == '-' ) { - i++; - } - - /* Getting type range or size */ - while (isdigit(stabstr[cnt+i])) i++; - - char *temp = (char *)malloc(sizeof(char)*(i+1)); - if(!strncpy(temp, &(stabstr[cnt]), i)) - /* Error copying size/range*/ - exit(1); - temp[i] = '\0'; - int j = atol(temp); - - char *low = temp; - cnt = cnt + i + 1; /* Discard other Semicolon */ - i = 0; - if((stabstr[cnt]) == '-') { - i++; /* discard '-' for (long) unsigned int */ - } - - while(isdigit(stabstr[cnt+i])) - i++; - - char *hi = (char *)malloc(sizeof(char)*(i+1)); - if(!strncpy(hi, &(stabstr[cnt]), i)) - /* Error copying upper range */ - exit(1); - hi[i] = '\0'; - - std::string tname = convertCharToString(name); - if ( j <= 0 ) - { - /* range */ - boost::shared_ptr newType; - - // //bperr("\tLower limit: %s and Upper limit: %s\n", low, hi); - //Create new type - errno = 0; - long low_conv = strtol(low, NULL, 10); - if (errno) - { - low_conv = LONG_MIN; - } - - if (low_conv < LONG_MIN) - { - low_conv = LONG_MIN; - } - - errno = 0; - long hi_conv = strtol(hi, NULL, 10); - if (errno) - { - hi_conv = LONG_MAX; - } - - if (hi_conv > LONG_MAX) - { - hi_conv = LONG_MAX; - } - - if (baseType == NULL) - { - newType = Type::make_shared(ID, sizeHint ? sizeHint / 8 : guessSize(low,hi), - low_conv, hi_conv, tname); - } - else - { - newType = Type::make_shared(ID, sizeHint ? sizeHint / 8 : baseType->getSize(), - low_conv, hi_conv, tname); - } - tc->addOrUpdateType(newType); - } - else if( j > 0) - { - j = atol(hi); - if (j == 0) - { - /*size */ - int size = (int)j; - - // //bperr("\tSize of Type : %d bytes\n",size); - //Create new type - - //Add to Collection - tc->addOrUpdateType(Type::make_shared(ID, size, convertCharToString(name))); - } - else - { - /* range */ - boost::shared_ptr newType; - // //bperr("Type RANGE: ERROR!!\n"); - errno = 0; - long low_conv = strtol(low, NULL, 10); - if (errno) - { - low_conv = LONG_MIN; - } - - errno = 0; - long hi_conv = strtol(hi, NULL, 10); - if (errno) - { - hi_conv = LONG_MAX; - } - - if (baseType == NULL) - newType = Type::make_shared(ID, sizeHint ? sizeHint / 8 : sizeof(long), - low_conv, hi_conv, tname); - else - newType = Type::make_shared(ID, sizeHint ? sizeHint / 8 : baseType->getSize(), - low_conv, hi_conv, tname); - tc->addOrUpdateType(newType); - } - } - free(low); - free(hi); - - cnt = cnt + i; - if( stabstr[cnt] == ';') - cnt++; - - return(&(stabstr[cnt])); -} - -#endif - -// -// = @s; -// = @s;(,) -// = @s;r(,);;; -// - -// -// This may in fact be much simpler than first anticipated -// dbx only -// understands @s (size) and @P (packed) types. We only -// parse the size attribute, and should be able to get away -// with simply passing the remainder to the rest of our parser -// -static char *parseAttrType(Module *mod, const char *name, - int ID, char *stabstr, int &cnt) -{ - assert(stabstr[cnt] == '@'); - cnt++; // skip the @ - - if (stabstr[cnt] == 's') { - cnt++; - - int size = parseSymDesc(stabstr, cnt); - cnt++; // skip ';' - - char *newstr = parseTypeDef(mod, stabstr+cnt, name, ID, size); - if (newstr[0] == ';') - return newstr+1; - else - return newstr; - } else { - ////bperr(" Unable to parse Type Attribute: %s ID %d : %s\n", - // name,ID, &(stabstr[cnt])); - while (stabstr[cnt] != ';') cnt++; - cnt++; - return parseTypeDef(mod, stabstr+cnt, name, ID); - } -} -/* -static void parseAttrType(Module *mod, const char *name, - int ID, char *stabstr, int &cnt) -{ - bool includesRange = false; - char *low = NULL, *high = NULL; - - // format @s(size in bits); negative type number; - dataClass typdescr = dataTypeAttrib; - - assert(stabstr[cnt] == '@'); - cnt++; // skip the @ - - if (stabstr[cnt] == 's') { - cnt++; - - int size = parseSymDesc(stabstr, cnt); - cnt++; // skip ';' - - if (stabstr[cnt] == 'r') { - // include range at end - cnt++; - includesRange = true; - } - - int type = parseSymDesc(stabstr, cnt); - // skip ';' end of stab record ??? (at least for bool) - cnt++; - - if (includesRange) { - int len; - - // Parse out low range string. - len = 0; - if (stabstr[cnt] == '-' ) cnt++, len++; - while (isdigit(stabstr[cnt])) cnt++, len++; - cnt++; // skip ';' - - // Store the low range string. - low = (char *)malloc(sizeof(char) * (len + 1)); - assert(low); - strncpy(low, &stabstr[cnt - (len + 1)], len); - low[len] = '\0'; - - // Parse out high range string. - len = 0; - if (stabstr[cnt] == '-' ) cnt++, len++; - while (isdigit(stabstr[cnt])) cnt++, len++; - cnt++; // skip ';' - - // Store the high range string. - high = (char *)malloc(sizeof(char) * (len + 1)); - assert(high); - strncpy(high, &stabstr[cnt - (len + 1)], len); - high[len] = '\0'; - } - - // Create a new B_type that points to a builtInTypes - Type *ptrType =BPatch::bpatch->builtInTypes->findBuiltInType(type); - - if (!ptrType) ptrType = BPatch::bpatch->type_Untyped; - - Type *newType = new Type(name, ID, typdescr, size/8, ptrType); - if(!newType) { - //bperr(" Can't Allocate new type "); - exit(-1); - } - - if (includesRange) { - newType->setLow(low); - newType->setHigh(high); - free(low); - free(high); - } - - // Add type to collection - newType2 = tc->addOrUpdateType(newType); - - if (stabstr[cnt]) { - //bperr("More Type Attribute to Parse: %s ID %d : %s\n", name, - ID, &(stabstr[cnt])); - //bperr("got type = %d\n", type); - //bperr("full string = %s\n", stabstr); - } - } else { - ////bperr(" Unable to parse Type Attribute: %s ID %d : %s\n", - // name,ID, &(stabstr[cnt])); - } -} -*/ -// -// = & -// -static char *parseRefType(Module *mod, const char *name, - int ID, char *stabstr, int &cnt) -{ - /* reference to another type */ - assert(stabstr[cnt] == '&'); - cnt++; - - int refID = parseTypeUse(mod, stabstr, cnt, name); - - // Create a new B_type that points to a structure - typeCollection *tc = typeCollection::getModTypeCollection(mod); - auto ptrType = tc->findOrCreateType(refID, Type::share); - if (!ptrType) ptrType = Symtab::type_Untyped(); - std::string tName = convertCharToString(name); - - // Add to typeCollection - tc->addOrUpdateType(Type::make_shared(ID, ptrType, tName)); - - return(&(stabstr[cnt])); -} - -// -// Given a base class and a new type, add all visible fields to the new class -// -void addBaseClassToClass(Module *mod, int baseID, - boost::shared_ptr newType, int /*offset*/) -{ - - typeCollection *tc = typeCollection::getModTypeCollection(mod); - - //Find base class - auto baseCl = tc->findType(baseID, Type::share); - if( ! baseCl ) { - std::string modName = mod->fileName(); - //bpwarn( "can't find base class id %d in module %s\n", baseID, modName); - baseCl = tc->addOrUpdateType(Type::make_shared(baseID)); - } - std::string fName = "{superclass}"; - newType->asFieldListType().addField( fName, baseCl, -1, visUnknown ); - - //Get field descriptions of the base type - /* - const std::vector *baseClFields = baseCl->getComponents(); - for (unsigned int fieldNum=0; fieldNum < baseClFields->size(); fieldNum++) { - Field *field = (*baseClFields)[fieldNum]; - - if (field->getVisibility() == visPrivate) - continue; //Can not add this member - - newType->addField(field->getName(), field->getTypeDesc(), field->getType(), field->getOffset()+offset, field->getVisibility()); - } - */ -} - -// -// parse a list of fields. -// Format is [A|B|C-M|N|O][c][G]:;offset;size; -// -static char *parseFieldList(Module *mod, boost::shared_ptr newType, - char *stabstr, bool sunCPlusPlus) -{ - int cnt = 0; - int size = 0; - char *compname; - int comptype= 0; - int beg_offset=0; - visibility_t _vis = visUnknown; - dataClass typedescr; - bool hasVirtuals = false; - typeCollection *tc = typeCollection::getModTypeCollection(mod); - assert(tc); - - if (stabstr[cnt] == '!') - { - //Inheritance definition, Add base class field list to the current one - //according to visibility rules. - - cnt++; //Skip '!' - - //Get # of base classes - int baseClNum = atoi(getIdentifier(stabstr, cnt).c_str()); - cnt++; //Skip ',' - - boost::shared_ptr newStructType; - if(newType->isStructType()) newStructType = newType; - //Skip information for each base class - for (int i=0; icG - if (sunCPlusPlus) cnt += 3; - - if ((stabstr[cnt] == 'u') && (stabstr[cnt+1] == ':') && (!isdigit(stabstr[cnt+2]))) - { - cnt += 2; - } - - compname = getFieldName(stabstr, cnt); - - /* - if (strlen(compname) == 0) { - //Something wrong! Most probably unhandled C++ type - //Skip the rest of the structure - while(stabstr[cnt]) cnt++; - return(&stabstr[cnt]); - } - */ - cnt++; // Skip ":" - - if ((stabstr[cnt]) == ':') - { - //Method definition - typedescr = dataFunction; - cnt++; - } - - if ((stabstr[cnt]) == '/') - { // visibility C++ - cnt++; /* get '/' */ - switch (stabstr[cnt]) { - case '0': - _vis = visPrivate; - break; - case '1': - _vis = visProtected; - break; - case '2': - _vis = visPublic; - break; - default: - _vis = visUnknown; - } - cnt++; // get visibility value - } - - // should be a typeDescriptor - comptype = parseTypeUse(mod, stabstr, cnt, ""); - - if (stabstr[cnt] == ':') - { - while (stabstr[cnt] == ':') - { - cnt++; //Discard ':' - beg_offset = 0; - size = 0; - std::string varName = getIdentifier(stabstr, cnt); - - if (typedescr == dataFunction) - { - // Additional qualifiers for methods - cnt++; //Skip ';' - cnt++; //Skip visibility - cnt++; //Skip method modifier - if (stabstr[cnt] == '*') - { - //Virtual fcn definition - hasVirtuals = true; - cnt++; //Skip '*' - while(stabstr[cnt] != ';') cnt++; //Skip vtable index - cnt++; //Skip ';' - if (stabstr[cnt] != ';') - { - parseTypeUse(mod, stabstr, cnt, ""); //Skip type number to the base class - } - cnt++; //Skip ';' - if (isSymId(stabstr[cnt])) - { - parseTypeUse(mod, stabstr, cnt, ""); - } - } else if ( (stabstr[cnt] == '.') - || (stabstr[cnt] == '?') ) - { - cnt++; //Skip '.' or '?' - if (isSymId(stabstr[cnt])) - { - parseTypeUse(mod, stabstr, cnt, ""); - } - } - } - - if (stabstr[cnt] == ';') - cnt++; //Skip ';' - } - } - else if (stabstr[cnt] == ',') - { - cnt++; // skip ',' - beg_offset = parseSymDesc(stabstr, cnt); - - if (stabstr[cnt] == ',') - { - cnt++; // skip ',' - size = parseSymDesc(stabstr, cnt); - } - else - size = 0; - } - - if (stabstr[cnt] == ';') // jaw 03/15/02-- major kludge here for DPCL compat - cnt++; // needs further examination - - // //bperr("\tType: %d, Starting Offset: %d (bits), Size: %d (bits)\n", comptype, beg_offset, size); - (void)size; // otherwise unused symbol - // Add struct field to type - - auto fieldType = tc->findOrCreateType( comptype, Type::share ); - if (!fieldType) - { - //C++ compilers may add extra fields whose types might not available. - //Assign void type to these kind of fields. --Mehmet - fieldType = tc->findType("void", Type::share); - } - std::string fName = convertCharToString(compname); - if (_vis == visUnknown) - { - newType->asFieldListType().addField(fName, fieldType, beg_offset); - } - else - { - // //bperr( "Adding field '%s' to type '%s' @ 0x%x\n", compname, newType->getName(), newType ); - newType->asFieldListType().addField(fName, fieldType, beg_offset, _vis); - ////bperr("Adding Component with VISIBILITY STRUCT\n"); - } - free(compname); - } - - if (hasVirtuals && - stabstr[cnt] == ';' && - stabstr[cnt+1] == '~' && - stabstr[cnt+2] == '%') - { - cnt+=3; - while (stabstr[cnt] != ';') cnt++; - } - - // should end with a ';' - if (stabstr[cnt] == ';') - { - return &stabstr[cnt+1]; - } - else if (stabstr[cnt] == '\0') - { - return &stabstr[cnt]; - } - else - { - //bperr("invalid stab record: %s\n", &stabstr[cnt]); - abort(); - return NULL; // should not get here - } -} - - -// -// Y;;;;; -// ;;;; -// ;;; -// -static char *parseCPlusPlusInfo(Module *mod, - char *stabstr, const char *mangledName, int ID) -{ - typeCollection *tc = typeCollection::getModTypeCollection(mod); - int cnt; - char *name; - int structsize; - bool sunStyle = true; - bool nestedType = false; - dataClass typdescr; - - assert(stabstr[0] == 'Y'); - cnt = 1; - - if (isdigit(stabstr[cnt])) { - structsize = parseSymDesc(stabstr, cnt); - sunStyle = false; - } - - switch(stabstr[cnt]) { - case 'C': - case 'c': - typdescr = dataTypeClass; - break; - - case 'S': - nestedType = true; - DYNINST_FALLTHROUGH; - case 's': - typdescr = dataStructure; - break; - - case 'U': - nestedType = true; - DYNINST_FALLTHROUGH; - case 'u': - typdescr = dataUnion; - break; - - case 'n': // namespace - ignored - cnt = strlen(stabstr); - return(&(stabstr[cnt])); - break; - - default: - //bperr( "ERROR: Unrecognized C++ str = %s\n", stabstr); - cnt = strlen(stabstr); - return(&(stabstr[cnt])); - break; - } (void)nestedType; // unused - - cnt++; // skip to size - if (isdigit(stabstr[cnt])) { - structsize = parseSymDesc(stabstr, cnt); - } - (void)structsize; // unused - - if (stabstr[cnt] == 'V') cnt++; - if (stabstr[cnt] == '(') cnt++; - - if (sunStyle && (stabstr[cnt] != ';')) { - int len; - char *n; - - // Class or Type Name - n = &stabstr[cnt]; - while (stabstr[cnt] != ';') cnt++; - len = &stabstr[cnt] - n; - name = (char *) calloc(len + 1, sizeof(char)); - strncpy(name, n, len); - } else { - name = const_cast< char * >( mangledName ); - } - - std::string tName = convertCharToString(name); - boost::shared_ptr newType; - //Create new type - switch (typdescr) { - case dataTypeClass: - case dataStructure: - newType = tc->addOrUpdateType(Type::make_shared(ID, tName)); - break; - case dataUnion: - newType = tc->addOrUpdateType(Type::make_shared(ID, tName)); - break; - default: - assert(0); - } - //add to type collection - - if (sunStyle) { - cnt++; - // base class(es) - while (stabstr[cnt] != ';') { - // skip visibility flag - cnt++; - - int offset = parseSymDesc(stabstr, cnt); - - // Find base class type identifier - int baseID = parseSymDesc(stabstr, cnt); - addBaseClassToClass(mod, baseID, newType, offset); - } - - cnt++; // skip ; - } - - // parse dataMembers - stabstr = parseFieldList(mod, newType, &stabstr[cnt], sunStyle); - cnt = 0; - - if (stabstr[0]) { - // parse member functions - cnt++; - while (stabstr[cnt] && (stabstr[cnt] != ';')) { - std::string pd_funcName = getIdentifier(stabstr, cnt, true); - const char *funcName = pd_funcName.c_str(); - - funcName++; // skip ppp-code - - if (*funcName == '-') funcName++; // it's a pure vitual - - while (isdigit(*funcName)) funcName++; // skip virtual function index - funcName++; - - char *className = strdup(currentRawSymbolName.c_str()); - className[3] = 'c'; - className[strlen(className)-1] = '\0'; // remove tailing "_" - std::string methodName = std::string(className) + std::string(funcName) + std::string("_"); - - std::string fName = P_cplus_demangle( methodName ); - if( name != NULL ) { - funcName = strrchr( name, ':' ); - if( funcName ) { funcName++; } - else { funcName = name; } - } - - // should include position for virtual methods - auto fieldType = tc->findType("void", Type::share); - - newType->asFieldListType().addField( fName, Type::make_shared( ID, fieldType, fName)); - - free(name); - free(className); - if (stabstr[cnt] == ' ') cnt++; - } - } - - cnt = strlen(stabstr); - return(&(stabstr[cnt])); -} - -// -// This function takes a and parses it -// -// = | -// | -// * | Pointer to a type -// | -// f | function type -// R, | Real type -// b[u|s][c|];; | Builtin -// | -// e | -// | -// | -// k | SunPro constant -// B | SunPro volatile -// M;| Fortran CHARACTER array -// s | Structure is size -// u | Union is size -// V -// -// = : | :, -// -// It adds the typeDef to the type definition with the name name, and id ID. -// -static char *parseTypeDef(Module *mod, char *stabstr, - const char *name, int ID, unsigned int sizeHint) -{ - typeCollection *tc = typeCollection::getModTypeCollection(mod); - boost::shared_ptr newType; - boost::shared_ptr newFieldType; - boost::shared_ptr ptrType; - - std::string compsymdesc; - - dataClass typdescr; - int ptrID=0; - - int value; - int cnt,i,j,k; - int structsize; - int type; - cnt = i = j = k = 0; - - assert (stabstr[0] != '='); - - // //bperr( "parsing %s\n", stabstr); - if (isSymId(stabstr[0])) - { - typdescr = dataScalar; - type = parseSymDesc(stabstr, cnt); - - if (ID == type) - { - // Type:tFOO = FOO - // as far as I can tell, this only happens when defining an empty - // type (i.e. void) - - std::string tName = convertCharToString(name); - newType = tc->addOrUpdateType(Type::make_shared(ID, 0, tName)); - } - else if (stabstr[cnt] == '=') - { - // XXX - in the new type t(0,1)=(0,2)=s... is possible - // skip the second id for now -- jkh 3/21/99 - stabstr = parseTypeDef(mod, &(stabstr[cnt+i+1]), name, type); - cnt = 0; - boost::shared_ptr oldType; - - oldType = tc->findOrCreateType(type, Type::share); - if (!oldType) oldType = Symtab::type_Untyped(); - std::string tName = convertCharToString(name); - tc->addOrUpdateType(Type::make_shared(ID, oldType, tName, sizeHint)); - - } - else - { - boost::shared_ptr oldType; - std::string tName = convertCharToString(name); - oldType = tc->findOrCreateType(type, Type::share); - newType = tc->addOrUpdateType(Type::make_shared(ID, oldType, tName, sizeHint)); - } - } else { - switch (stabstr[0]) { - case 'x': //cross reference - { - parseCrossRef(tc, name, ID, stabstr, cnt); - break; - } - case '*': - { - /* pointer to another type */ - cnt++; - ptrID = parseTypeUse(mod, stabstr, cnt, NULL); - - // Create a new B_type that points to a structure - ptrType = tc->findOrCreateType(ptrID, Type::share); - if (!ptrType) ptrType = Symtab::type_Untyped(); - - // Add to typeCollection - newType = tc->addOrUpdateType(Type::make_shared(ID, ptrType)); - return(&(stabstr[cnt])); - break; - } - case 'a': - case 'A': - { - (void) parseArrayDef(mod, name, ID, stabstr, cnt, sizeHint); - return (&stabstr[cnt]); - break; - } - case 'g': - { - /* function with return type and prototype */ - - // g[]*# - typdescr = dataFunction; - - cnt++; /* skip the g */ - type = parseTypeUse(mod, stabstr, cnt, name); - ptrType = tc->findOrCreateType(type, Type::share); - - { - std::string tName = convertCharToString(name); - auto newFunction = tc->addOrUpdateType(Type::make_shared(ID, ptrType, tName)); - if (!newFunction) { - //bpfatal(" Can't Allocate new type "); - types_printf("%s[%d]: parseTypeDef: unable to allocate newType\n", FILE__, __LINE__); - //exit(-1); - } - - while ((stabstr[cnt] != '#') && (stabstr[cnt])) { - int paramType; - paramType = parseTypeUse(mod, stabstr, cnt, name); - newType = tc->findOrCreateType(paramType, Type::share); - newFunction->asFunctionType().addParam(newType); - //newFunction2->addField(buffer, newType->getDataClass(), newType, curOffset, newType->getSize()); - } - } - - // skip # - if (stabstr[cnt] == '#') cnt++; - break; - } - case 'f': - { - /* function type */ - typdescr = dataFunction; - - cnt++; /* skip the f */ - type = parseTypeUse(mod, stabstr, cnt, name); - ptrType = tc->findOrCreateType(type, Type::share); - - - std::string tName = convertCharToString(name); - newType = tc->addOrUpdateType(Type::make_shared(ID, ptrType, tName)); - - // skip to end - SunPro Compilers output extra info here - jkh 6/9/3 - // cnt = strlen(stabstr); - break; - } - - case 'M': - { - /* CHARACTER ??? */ - cnt++; // skip 'M' - - int baseType = parseSymDesc(stabstr, cnt); - if (baseType != -2 || (stabstr[cnt] != ';')) { - //bperr("unexpected non character array %s\n", stabstr); - } else { - cnt++; // skip ';' - int size; - if (stabstr[cnt] == 'T') { - /* Fortran stack-based array bounds */ - size = 0; - cnt++; // skip 'T' - (void) parseSymDesc(stabstr, cnt); - } else if (stabstr[cnt] == 'J') { - /* Unbounded range */ - size = 0; - cnt++; // skip 'J'; - (void) parseSymDesc(stabstr, cnt); - } else - size = parseSymDesc(stabstr, cnt); - - ptrType = tc->findOrCreateType(baseType, Type::share); - std::string tName = convertCharToString(name); - - newType = tc->addOrUpdateType(Type::make_shared(ID, ptrType, 1, size, tName)); - } - break; - - } - case 'R': - { - // Define a floating point type - R fp-type; bytes; - cnt++; - (void) parseSymDesc(stabstr, cnt); - cnt ++; - - int bytes = parseSymDesc(stabstr, cnt); - - newType = tc->addOrUpdateType(Type::make_shared(ID, bytes, name)); - - if (stabstr[cnt] == ';') cnt++; // skip the final ';' - - // gcc 3.0 adds an extra field that is always 0 (no indication in the code why) - if (stabstr[cnt] == '0') cnt += 2; // skip the final '0;' - - break; - } - - case 'b': - { - // builtin type b - signed char-flag width; offset; nbits - int limit = strlen(&stabstr[cnt]); - - // skip to width - while (!isdigit(stabstr[cnt+i]) && (i < limit)) i++; - if (i >= limit) return(&(stabstr[cnt])); - - cnt += i; - int size = parseSymDesc(stabstr,cnt); - cnt -= i; - i++; // skip the ';' - - // skip to bits - while (stabstr[cnt+i] != ';' && (i < limit)) i++; - if (i >= limit) return(&(stabstr[cnt])); - i++; - - cnt += i; - parseSymDesc(stabstr, cnt); - - if (stabstr[cnt]) cnt++; // skip the final ';' - - //Add to Collection - newType = tc->addOrUpdateType(Type::make_shared(ID, size, name)); - - return &stabstr[cnt]; - break; - } - case 'r': // range type - { - return parseRangeType(mod, name, ID, stabstr, sizeHint); - break; - } - case 'e': // Enumerated type - { - cnt++; /* skip the 'e' */ - - // Create new Enum type - std::string tName = convertCharToString(name); - // Add type to collection - auto newEnumType = tc->addOrUpdateType(Type::make_shared(ID, tName)); - - while (stabstr[cnt]) { - /* Get enum component value */ - compsymdesc = getIdentifier(stabstr, cnt); - cnt++; /* skip colon */ - value = parseSymDesc(stabstr, cnt); - - // add enum field to type - newEnumType->asEnumType().addConstant(compsymdesc, value); - - cnt++; /* skip trailing comma */ - if ((stabstr[cnt]) == ';') cnt++; /* End of enum stab record */ - } - break; - } - case '@': // type attribute, defines size and type (negative num) - { - return parseAttrType(mod, name, ID, stabstr, cnt); - break; - } - case '&': //XXX- Need to complete, may be more to parse jdd 4/22/99 - { - return parseRefType(mod, name, ID, stabstr, cnt); - break; - } - case 'k': // Sun constant type s - parse as - { - return parseTypeDef(mod, &stabstr[cnt+1], name, ID); - break; - } - case 'V': // volatile ? type V - parse as - case 'B': // Sun volatile type B - parse as - return parseTypeDef(mod, &stabstr[cnt+1], name, ID); - break; - - case 's': // struct - case 'u': // union - case 'T': // Fortran TYPE - { - /* Type descriptor */ - if (stabstr[cnt] == 's' || stabstr[cnt] == 'T') { - typdescr = dataStructure; - } else { - typdescr = dataUnion; - } - - cnt++; // skip to size - structsize = parseSymDesc(stabstr, cnt); - (void)structsize; // unused - - std::string tName = convertCharToString(name); - //Create new type - if (typdescr == dataStructure) { - newFieldType = tc->addOrUpdateType(Type::make_shared(ID, tName)); - } - else { - newFieldType = tc->addOrUpdateType(Type::make_shared(ID, tName)); - } - //add to type collection - - //TODO What if two different files have the same structure?? - char *ret = parseFieldList(mod, newFieldType, &stabstr[cnt], false); - return ret; - - break; - } - case 'Y': - { - // C++ specific stabs (Sun compiler) - return parseCPlusPlusInfo(mod, stabstr, name, ID); - break; - } - case 'Z': // What is this ??? - jkh 10/14/99 (xlc compiler uses it) - { - return (&stabstr[1]); - break; - } - case '#': - { - //Class method definition - cnt++; //Skip '#' - if (stabstr[cnt] == '#') { - //Get return type - cnt++; //Skip '#' - parseTypeUse(mod, stabstr, cnt, name); - } - else { - while(1) { - //Skip class type, return typ and arg types - parseTypeUse(mod, stabstr, cnt, name); - if (stabstr[cnt] == ',') - cnt++; - else if (stabstr[cnt] == ';') - break; - } - } - - cnt++; //Skip ';' - return(&(stabstr[cnt])); - break; - } - default: - //bperr( "ERROR: Unrecognized str = %s\n", &stabstr[cnt]); - // return NULL; - // Null probably isn't the right choice here. - cnt = strlen(stabstr); - break; - } - } - - return(&(stabstr[cnt])); -} /* end of parseTypeDef*/ - -// -// parseConstantUse - parse a constant (used by Fortran PARAMETERS) -// -// = =i | -// =r -// -// -static boost::shared_ptr parseConstantUse(Module *mod, char *stabstr, int &cnt) -{ - typeCollection *tc = typeCollection::getModTypeCollection(mod); - // skip = - cnt++; - - boost::shared_ptr ret; - - if (stabstr[cnt] == 'i') { - ret = tc->findType("integer*4", Type::share); - } else if (stabstr[cnt] == 'r') { - ret = tc->findType("double", Type::share); - } else if (stabstr[cnt] == 's') { - ret = tc->findType("char *", Type::share); - } else { - //bperr("unknown constant type %s\n", &stabstr[cnt]); - ret = NULL; - } - - cnt = strlen(stabstr); - - return ret; -} - diff --git a/symtabAPI/src/relocationEntry-elf-ppc32.C b/symtabAPI/src/relocationEntry-elf-ppc32.C deleted file mode 100644 index 7cee2b36c4..0000000000 --- a/symtabAPI/src/relocationEntry-elf-ppc32.C +++ /dev/null @@ -1,143 +0,0 @@ -/* - * See the dyninst/COPYRIGHT file for copyright information. - * - * We provide the Paradyn Tools (below described as "Paradyn") - * on an AS IS basis, and do not warrant its validity or performance. - * We reserve the right to update, modify, or discontinue this - * software at any time. We shall have no obligation to supply such - * updates or modifications or any other form of support to you. - * - * By your use of Paradyn, you understand and agree that we (or any - * other person or entity with proprietary rights in Paradyn) are - * under no obligation to provide either maintenance services, - * update services, notices of latent defects, or correction of - * defects for Paradyn. - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* Functions of the relocationEntry class specific to PPC ELF */ -#include "Symtab.h" -#include "annotations.h" -#include - -const char* relocationEntry::relType2Str(unsigned long r, unsigned /*addressWidth*/) { - switch(r) { - CASE_RETURN_STR(R_PPC_NONE); - CASE_RETURN_STR(R_PPC_ADDR32); - CASE_RETURN_STR(R_PPC_ADDR24); - CASE_RETURN_STR(R_PPC_ADDR16); - CASE_RETURN_STR(R_PPC_ADDR16_LO); - CASE_RETURN_STR(R_PPC_ADDR16_HI); - CASE_RETURN_STR(R_PPC_ADDR16_HA); - CASE_RETURN_STR(R_PPC_ADDR14); - CASE_RETURN_STR(R_PPC_ADDR14_BRTAKEN); - CASE_RETURN_STR(R_PPC_ADDR14_BRNTAKEN); - CASE_RETURN_STR(R_PPC_REL24); - CASE_RETURN_STR(R_PPC_REL14); - CASE_RETURN_STR(R_PPC_REL14_BRTAKEN); - CASE_RETURN_STR(R_PPC_REL14_BRNTAKEN); - CASE_RETURN_STR(R_PPC_GOT16); - CASE_RETURN_STR(R_PPC_GOT16_LO); - CASE_RETURN_STR(R_PPC_GOT16_HI); - CASE_RETURN_STR(R_PPC_GOT16_HA); - CASE_RETURN_STR(R_PPC_PLTREL24); - CASE_RETURN_STR(R_PPC_COPY); - CASE_RETURN_STR(R_PPC_GLOB_DAT); - CASE_RETURN_STR(R_PPC_JMP_SLOT); - CASE_RETURN_STR(R_PPC_RELATIVE); - CASE_RETURN_STR(R_PPC_LOCAL24PC); - CASE_RETURN_STR(R_PPC_UADDR32); - CASE_RETURN_STR(R_PPC_UADDR16); - CASE_RETURN_STR(R_PPC_REL32); - CASE_RETURN_STR(R_PPC_PLT32); - CASE_RETURN_STR(R_PPC_PLTREL32); - CASE_RETURN_STR(R_PPC_PLT16_LO); - CASE_RETURN_STR(R_PPC_PLT16_HI); - CASE_RETURN_STR(R_PPC_PLT16_HA); - CASE_RETURN_STR(R_PPC_SDAREL16); - CASE_RETURN_STR(R_PPC_SECTOFF); - CASE_RETURN_STR(R_PPC_SECTOFF_LO); - CASE_RETURN_STR(R_PPC_SECTOFF_HI); - CASE_RETURN_STR(R_PPC_SECTOFF_HA); - CASE_RETURN_STR(R_PPC_TLS); - CASE_RETURN_STR(R_PPC_DTPMOD32); - CASE_RETURN_STR(R_PPC_TPREL16); - CASE_RETURN_STR(R_PPC_TPREL16_LO); - CASE_RETURN_STR(R_PPC_TPREL16_HI); - CASE_RETURN_STR(R_PPC_TPREL16_HA); - CASE_RETURN_STR(R_PPC_TPREL32); - CASE_RETURN_STR(R_PPC_DTPREL16); - CASE_RETURN_STR(R_PPC_DTPREL16_LO); - CASE_RETURN_STR(R_PPC_DTPREL16_HI); - CASE_RETURN_STR(R_PPC_DTPREL16_HA); - CASE_RETURN_STR(R_PPC_DTPREL32); - CASE_RETURN_STR(R_PPC_GOT_TLSGD16); - CASE_RETURN_STR(R_PPC_GOT_TLSGD16_LO); - CASE_RETURN_STR(R_PPC_GOT_TLSGD16_HI); - CASE_RETURN_STR(R_PPC_GOT_TLSGD16_HA); - CASE_RETURN_STR(R_PPC_GOT_TLSLD16); - CASE_RETURN_STR(R_PPC_GOT_TLSLD16_LO); - CASE_RETURN_STR(R_PPC_GOT_TLSLD16_HI); - CASE_RETURN_STR(R_PPC_GOT_TLSLD16_HA); - CASE_RETURN_STR(R_PPC_GOT_TPREL16); - CASE_RETURN_STR(R_PPC_GOT_TPREL16_LO); - CASE_RETURN_STR(R_PPC_GOT_TPREL16_HI); - CASE_RETURN_STR(R_PPC_GOT_TPREL16_HA); - CASE_RETURN_STR(R_PPC_GOT_DTPREL16); - CASE_RETURN_STR(R_PPC_GOT_DTPREL16_LO); - CASE_RETURN_STR(R_PPC_GOT_DTPREL16_HI); - CASE_RETURN_STR(R_PPC_GOT_DTPREL16_HA); -#if defined(R_PPC_NUM) - CASE_RETURN_STR(R_PPC_NUM); -#endif - CASE_RETURN_STR(R_PPC_EMB_NADDR32); - CASE_RETURN_STR(R_PPC_EMB_NADDR16); - CASE_RETURN_STR(R_PPC_EMB_NADDR16_LO); - CASE_RETURN_STR(R_PPC_EMB_NADDR16_HI); - CASE_RETURN_STR(R_PPC_EMB_NADDR16_HA); - CASE_RETURN_STR(R_PPC_EMB_SDAI16); - CASE_RETURN_STR(R_PPC_EMB_SDA2I16); - CASE_RETURN_STR(R_PPC_EMB_SDA2REL); - CASE_RETURN_STR(R_PPC_EMB_SDA21); - CASE_RETURN_STR(R_PPC_EMB_MRKREF); - CASE_RETURN_STR(R_PPC_EMB_RELSEC16); - CASE_RETURN_STR(R_PPC_EMB_RELST_LO); - CASE_RETURN_STR(R_PPC_EMB_RELST_HI); - CASE_RETURN_STR(R_PPC_EMB_RELST_HA); - CASE_RETURN_STR(R_PPC_EMB_BIT_FLD); - CASE_RETURN_STR(R_PPC_EMB_RELSDA); - CASE_RETURN_STR(R_PPC_DIAB_SDA21_LO); - CASE_RETURN_STR(R_PPC_DIAB_SDA21_HI); - CASE_RETURN_STR(R_PPC_DIAB_SDA21_HA); - CASE_RETURN_STR(R_PPC_DIAB_RELSDA_LO); - CASE_RETURN_STR(R_PPC_DIAB_RELSDA_HI); - CASE_RETURN_STR(R_PPC_DIAB_RELSDA_HA); -#ifdef R_PPC_REL16 - // Older versions of elf.h may not have these defined. - CASE_RETURN_STR(R_PPC_REL16); - CASE_RETURN_STR(R_PPC_REL16_LO); - CASE_RETURN_STR(R_PPC_REL16_HI); - CASE_RETURN_STR(R_PPC_REL16_HA); -#endif - CASE_RETURN_STR(R_PPC_TOC16); - default: - return "?"; - } -} - -SYMTAB_EXPORT unsigned long relocationEntry::getGlobalRelType(unsigned /*addressWidth*/, Symbol *) { - return R_PPC_GLOB_DAT; -} diff --git a/symtabAPI/src/relocationEntry.C b/symtabAPI/src/relocationEntry.C new file mode 100644 index 0000000000..aa574e46ae --- /dev/null +++ b/symtabAPI/src/relocationEntry.C @@ -0,0 +1,221 @@ +/* + * See the dyninst/COPYRIGHT file for copyright information. + * + * We provide the Paradyn Tools (below described as "Paradyn") + * on an AS IS basis, and do not warrant its validity or performance. + * We reserve the right to update, modify, or discontinue this + * software at any time. We shall have no obligation to supply such + * updates or modifications or any other form of support to you. + * + * By your use of Paradyn, you understand and agree that we (or any + * other person or entity with proprietary rights in Paradyn) are + * under no obligation to provide either maintenance services, + * update services, notices of latent defects, or correction of + * defects for Paradyn. + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include + +#include "relocationEntry.h" +#include "Symbol.h" + + +namespace Dyninst { +namespace SymtabAPI { + + +SYMTAB_EXPORT relocationEntry::relocationEntry() : + target_addr_(0), + rel_addr_(0), + addend_(0), + rtype_(Region::RT_REL), + name_(""), + dynref_(NULL), + relType_(0), + rel_struct_addr_(0) +{ +} + +SYMTAB_EXPORT relocationEntry::relocationEntry(Offset ta, Offset ra, std::string n, + Symbol *dynref, unsigned long relType) : + target_addr_(ta), + rel_addr_(ra), + addend_(0), + rtype_(Region::RT_REL), + name_(n), + dynref_(dynref), + relType_(relType), + rel_struct_addr_(0) +{ +} + +SYMTAB_EXPORT relocationEntry::relocationEntry(Offset ta, Offset ra, Offset add, + std::string n, Symbol *dynref, unsigned long relType) : + target_addr_(ta), + rel_addr_(ra), + addend_(add), + rtype_(Region::RT_REL), + name_(n), + dynref_(dynref), + relType_(relType), + rel_struct_addr_(0) +{ +} + +SYMTAB_EXPORT relocationEntry::relocationEntry(Offset ra, std::string n, + Symbol *dynref, unsigned long relType, Region::RegionType rtype) : + target_addr_(0), + rel_addr_(ra), + addend_(0), + rtype_(rtype), + name_(n), + dynref_(dynref), + relType_(relType), + rel_struct_addr_(0) +{ +} + +SYMTAB_EXPORT relocationEntry::relocationEntry(Offset ta, Offset ra, Offset add, + std::string n, Symbol *dynref, unsigned long relType, + Region::RegionType rtype) : + target_addr_(ta), + rel_addr_(ra), + addend_(add), + rtype_(rtype), + name_(n), + dynref_(dynref), + relType_(relType), + rel_struct_addr_(0) +{ +} + +SYMTAB_EXPORT Offset relocationEntry::target_addr() const +{ + return target_addr_; +} + +SYMTAB_EXPORT void relocationEntry::setTargetAddr(const Offset off) +{ + target_addr_ = off; +} + +SYMTAB_EXPORT Offset relocationEntry::rel_addr() const +{ + return rel_addr_; +} + +SYMTAB_EXPORT void relocationEntry::setRelAddr(const Offset value) +{ + rel_addr_ = value; +} + +SYMTAB_EXPORT const std::string &relocationEntry::name() const +{ + return name_; +} + +SYMTAB_EXPORT Symbol *relocationEntry::getDynSym() const +{ + return dynref_; +} + +SYMTAB_EXPORT bool relocationEntry::addDynSym(Symbol *dynref) +{ + dynref_ = dynref; + return true; +} + +SYMTAB_EXPORT Region::RegionType relocationEntry::regionType() const +{ + return rtype_; +} + +SYMTAB_EXPORT unsigned long relocationEntry::getRelType() const +{ + return relType_; +} + +SYMTAB_EXPORT Offset relocationEntry::addend() const +{ + return addend_; +} + +SYMTAB_EXPORT void relocationEntry::setAddend(const Offset value) +{ + addend_ = value; +} + +SYMTAB_EXPORT void relocationEntry::setRegionType(const Region::RegionType value) +{ + rtype_ = value; +} + +SYMTAB_EXPORT void relocationEntry::setName(const std::string &newName) { + name_ = newName; +} + +bool relocationEntry::operator==(const relocationEntry &r) const +{ + if (target_addr_ != r.target_addr_) return false; + if (rel_addr_ != r.rel_addr_) return false; + if (addend_ != r.addend_) return false; + if (rtype_ != r.rtype_) return false; + if (name_ != r.name_) return false; + if (relType_ != r.relType_) return false; + if (dynref_ && !r.dynref_) return false; + if (!dynref_ && r.dynref_) return false; + if (dynref_) + { + if (dynref_->getMangledName() != r.dynref_->getMangledName()) return false; + if (dynref_->getOffset() != r.dynref_->getOffset()) return false; + } + + return true; +} + +std::ostream & operator<< (std::ostream &os, const relocationEntry &r) +{ + using namespace std; + + if( r.getDynSym() != NULL ) { + os << "Name: " << setw(20) << ( "'" + r.getDynSym()->getMangledName() + "'" ); + }else{ + os << "Name: " << setw(20) << r.name(); + } + os << " Offset: " << std::hex << std::setfill('0') << setw(8) << r.rel_addr() + << std::dec << std::setfill(' ') + << " Offset: " << std::hex << std::setfill('0') << setw(8) << r.target_addr() + << std::dec << std::setfill(' ') + << " Addend: " << r.addend() + << " Region: " << Region::regionType2Str(r.regionType()) + << " Type: " << setw(15) << relocationEntry::relType2Str(r.getRelType()) + << "(" << r.getRelType() << ")"; + if( r.getDynSym() != NULL ) { + os << " Symbol Offset: " << std::hex << std::setfill('0') << setw(8) << r.getDynSym()->getOffset(); + os << std::dec << std::setfill(' '); + if( r.getDynSym()->isCommonStorage() ) { + os << " COM"; + }else if( r.getDynSym()->getRegion() == NULL ) { + os << " UND"; + } + } + return os; +} + + +} +} diff --git a/symtabAPI/src/symtab_impl.hpp b/symtabAPI/src/symtab_impl.hpp new file mode 100644 index 0000000000..48dc755028 --- /dev/null +++ b/symtabAPI/src/symtab_impl.hpp @@ -0,0 +1,68 @@ +#ifndef SYMTAB_IMPL_HPP +#define SYMTAB_IMPL_HPP + +#include "IBSTree.h" +#include "Module.h" +#include "Variable.h" +#include "concurrent.h" +#include "indexed_symbols.hpp" +#include "indexed_modules.h" + +#include +#include +#include + +namespace Dyninst { namespace SymtabAPI { + + struct symtab_impl final { + indexed_symbols everyDefinedSymbol{}; + indexed_symbols undefDynSyms{}; + + indexed_modules modules{}; + + std::once_flag funcRangesAreParsed{}; + std::once_flag types_parsed{}; + + // Since Functions are unique by address, we require this structure to + // efficiently track them. + dyn_c_hash_map funcsByOffset{}; + + using VarsByOffsetMap = dyn_c_hash_map>; + VarsByOffsetMap varsByOffset{}; + + using ModRangeLookup = IBSTree; + ModRangeLookup mod_lookup_{}; + + using FuncRangeLookup = IBSTree; + FuncRangeLookup func_lookup{}; + + Module* default_module{}; + + Module* getContainingModule(Offset offset) const { + std::set mods; + mod_lookup_.find(offset, mods); + + if(mods.size() == 1) { + auto const& m = *(mods.begin()); + return m->id(); + } + + /* Because the default module covers the entire PC range of the + file, it will always be found so exclude it. + + It is assumed that the PC ranges of modules are disjoint and this + function can only return a single Module. + */ + for(auto *mr : mods) { + if(mr->id() != default_module) { + return mr->id(); + } + } + + return nullptr; + } + }; + +}} + +#endif diff --git a/syscalls/README b/syscalls/README index c4e033b093..39f16970c7 100644 --- a/syscalls/README +++ b/syscalls/README @@ -1,5 +1 @@ -System header files (unistd*.h) should be placed in Platform-specific files. - -NOTE: unistd.h from Linux/ppc contains both 32- and 64-bit syscall numbers. -This file has been copied to the Arch_ppc32 and Arch_ppc64 directories and -manually edited to reflect architecture-specific system call information. +System header files (unistd*.h) should be placed in Platform-specific files. \ No newline at end of file diff --git a/syscalls/generateSyscallInformation.py b/syscalls/generateSyscallInformation.py index 14eabc5dbc..c767a599dd 100755 --- a/syscalls/generateSyscallInformation.py +++ b/syscalls/generateSyscallInformation.py @@ -42,7 +42,7 @@ def generate_SyscallInformation(allSyscallNames, allSyscalls): # Write out "header" information outFile.write("/* This file was autogenerated from syscalls/generateSyscallInformation.py */" + "\n") - outFile.write("#include \"dyn_regs.h\"\n") + outFile.write("#include \"Architecture.h\"\n") outFile.write("#include \"dyn_syscalls.h\"\n") outFile.write("SyscallInformation::SyscallInformation() {\n") diff --git a/syscalls/unistd-by-platform/Linux/Arch_ppc32/unistd.h.20130604 b/syscalls/unistd-by-platform/Linux/Arch_ppc32/unistd.h.20130604 deleted file mode 100644 index a11a6ad5a0..0000000000 --- a/syscalls/unistd-by-platform/Linux/Arch_ppc32/unistd.h.20130604 +++ /dev/null @@ -1,334 +0,0 @@ -#ifndef _ASM_POWERPC_UNISTD_H_ -#define _ASM_POWERPC_UNISTD_H_ - -/* - * This file contains the system call numbers. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ - -#define __NR_restart_syscall 0 -#define __NR_exit 1 -#define __NR_fork 2 -#define __NR_read 3 -#define __NR_write 4 -#define __NR_open 5 -#define __NR_close 6 -#define __NR_waitpid 7 -#define __NR_creat 8 -#define __NR_link 9 -#define __NR_unlink 10 -#define __NR_execve 11 -#define __NR_chdir 12 -#define __NR_time 13 -#define __NR_mknod 14 -#define __NR_chmod 15 -#define __NR_lchown 16 -#define __NR_break 17 -#define __NR_oldstat 18 -#define __NR_lseek 19 -#define __NR_getpid 20 -#define __NR_mount 21 -#define __NR_umount 22 -#define __NR_setuid 23 -#define __NR_getuid 24 -#define __NR_stime 25 -#define __NR_ptrace 26 -#define __NR_alarm 27 -#define __NR_oldfstat 28 -#define __NR_pause 29 -#define __NR_utime 30 -#define __NR_stty 31 -#define __NR_gtty 32 -#define __NR_access 33 -#define __NR_nice 34 -#define __NR_ftime 35 -#define __NR_sync 36 -#define __NR_kill 37 -#define __NR_rename 38 -#define __NR_mkdir 39 -#define __NR_rmdir 40 -#define __NR_dup 41 -#define __NR_pipe 42 -#define __NR_times 43 -#define __NR_prof 44 -#define __NR_brk 45 -#define __NR_setgid 46 -#define __NR_getgid 47 -#define __NR_signal 48 -#define __NR_geteuid 49 -#define __NR_getegid 50 -#define __NR_acct 51 -#define __NR_umount2 52 -#define __NR_lock 53 -#define __NR_ioctl 54 -#define __NR_fcntl 55 -#define __NR_mpx 56 -#define __NR_setpgid 57 -#define __NR_ulimit 58 -#define __NR_oldolduname 59 -#define __NR_umask 60 -#define __NR_chroot 61 -#define __NR_ustat 62 -#define __NR_dup2 63 -#define __NR_getppid 64 -#define __NR_getpgrp 65 -#define __NR_setsid 66 -#define __NR_sigaction 67 -#define __NR_sgetmask 68 -#define __NR_ssetmask 69 -#define __NR_setreuid 70 -#define __NR_setregid 71 -#define __NR_sigsuspend 72 -#define __NR_sigpending 73 -#define __NR_sethostname 74 -#define __NR_setrlimit 75 -#define __NR_getrlimit 76 -#define __NR_getrusage 77 -#define __NR_gettimeofday 78 -#define __NR_settimeofday 79 -#define __NR_getgroups 80 -#define __NR_setgroups 81 -#define __NR_select 82 -#define __NR_symlink 83 -#define __NR_oldlstat 84 -#define __NR_readlink 85 -#define __NR_uselib 86 -#define __NR_swapon 87 -#define __NR_reboot 88 -#define __NR_readdir 89 -#define __NR_mmap 90 -#define __NR_munmap 91 -#define __NR_truncate 92 -#define __NR_ftruncate 93 -#define __NR_fchmod 94 -#define __NR_fchown 95 -#define __NR_getpriority 96 -#define __NR_setpriority 97 -#define __NR_profil 98 -#define __NR_statfs 99 -#define __NR_fstatfs 100 -#define __NR_ioperm 101 -#define __NR_socketcall 102 -#define __NR_syslog 103 -#define __NR_setitimer 104 -#define __NR_getitimer 105 -#define __NR_stat 106 -#define __NR_lstat 107 -#define __NR_fstat 108 -#define __NR_olduname 109 -#define __NR_iopl 110 -#define __NR_vhangup 111 -#define __NR_idle 112 -#define __NR_vm86 113 -#define __NR_wait4 114 -#define __NR_swapoff 115 -#define __NR_sysinfo 116 -#define __NR_ipc 117 -#define __NR_fsync 118 -#define __NR_sigreturn 119 -#define __NR_clone 120 -#define __NR_setdomainname 121 -#define __NR_uname 122 -#define __NR_modify_ldt 123 -#define __NR_adjtimex 124 -#define __NR_mprotect 125 -#define __NR_sigprocmask 126 -#define __NR_create_module 127 -#define __NR_init_module 128 -#define __NR_delete_module 129 -#define __NR_get_kernel_syms 130 -#define __NR_quotactl 131 -#define __NR_getpgid 132 -#define __NR_fchdir 133 -#define __NR_bdflush 134 -#define __NR_sysfs 135 -#define __NR_personality 136 -#define __NR_afs_syscall 137 /* Syscall for Andrew File System */ -#define __NR_setfsuid 138 -#define __NR_setfsgid 139 -#define __NR__llseek 140 -#define __NR_getdents 141 -#define __NR__newselect 142 -#define __NR_flock 143 -#define __NR_msync 144 -#define __NR_readv 145 -#define __NR_writev 146 -#define __NR_getsid 147 -#define __NR_fdatasync 148 -#define __NR__sysctl 149 -#define __NR_mlock 150 -#define __NR_munlock 151 -#define __NR_mlockall 152 -#define __NR_munlockall 153 -#define __NR_sched_setparam 154 -#define __NR_sched_getparam 155 -#define __NR_sched_setscheduler 156 -#define __NR_sched_getscheduler 157 -#define __NR_sched_yield 158 -#define __NR_sched_get_priority_max 159 -#define __NR_sched_get_priority_min 160 -#define __NR_sched_rr_get_interval 161 -#define __NR_nanosleep 162 -#define __NR_mremap 163 -#define __NR_setresuid 164 -#define __NR_getresuid 165 -#define __NR_query_module 166 -#define __NR_poll 167 -#define __NR_nfsservctl 168 -#define __NR_setresgid 169 -#define __NR_getresgid 170 -#define __NR_prctl 171 -#define __NR_rt_sigreturn 172 -#define __NR_rt_sigaction 173 -#define __NR_rt_sigprocmask 174 -#define __NR_rt_sigpending 175 -#define __NR_rt_sigtimedwait 176 -#define __NR_rt_sigqueueinfo 177 -#define __NR_rt_sigsuspend 178 -#define __NR_pread64 179 -#define __NR_pwrite64 180 -#define __NR_chown 181 -#define __NR_getcwd 182 -#define __NR_capget 183 -#define __NR_capset 184 -#define __NR_sigaltstack 185 -#define __NR_sendfile 186 -#define __NR_getpmsg 187 /* some people actually want streams */ -#define __NR_putpmsg 188 /* some people actually want streams */ -#define __NR_vfork 189 -#define __NR_ugetrlimit 190 /* SuS compliant getrlimit */ -#define __NR_readahead 191 -#define __NR_mmap2 192 -#define __NR_truncate64 193 -#define __NR_ftruncate64 194 -#define __NR_stat64 195 -#define __NR_lstat64 196 -#define __NR_fstat64 197 -#define __NR_pciconfig_read 198 -#define __NR_pciconfig_write 199 -#define __NR_pciconfig_iobase 200 -#define __NR_multiplexer 201 -#define __NR_getdents64 202 -#define __NR_pivot_root 203 -#define __NR_fcntl64 204 -#define __NR_madvise 205 -#define __NR_mincore 206 -#define __NR_gettid 207 -#define __NR_tkill 208 -#define __NR_setxattr 209 -#define __NR_lsetxattr 210 -#define __NR_fsetxattr 211 -#define __NR_getxattr 212 -#define __NR_lgetxattr 213 -#define __NR_fgetxattr 214 -#define __NR_listxattr 215 -#define __NR_llistxattr 216 -#define __NR_flistxattr 217 -#define __NR_removexattr 218 -#define __NR_lremovexattr 219 -#define __NR_fremovexattr 220 -#define __NR_futex 221 -#define __NR_sched_setaffinity 222 -#define __NR_sched_getaffinity 223 -/* 224 currently unused */ -#define __NR_tuxcall 225 -#define __NR_sendfile64 226 -#define __NR_io_setup 227 -#define __NR_io_destroy 228 -#define __NR_io_getevents 229 -#define __NR_io_submit 230 -#define __NR_io_cancel 231 -#define __NR_set_tid_address 232 -#define __NR_fadvise64 233 -#define __NR_exit_group 234 -#define __NR_lookup_dcookie 235 -#define __NR_epoll_create 236 -#define __NR_epoll_ctl 237 -#define __NR_epoll_wait 238 -#define __NR_remap_file_pages 239 -#define __NR_timer_create 240 -#define __NR_timer_settime 241 -#define __NR_timer_gettime 242 -#define __NR_timer_getoverrun 243 -#define __NR_timer_delete 244 -#define __NR_clock_settime 245 -#define __NR_clock_gettime 246 -#define __NR_clock_getres 247 -#define __NR_clock_nanosleep 248 -#define __NR_swapcontext 249 -#define __NR_tgkill 250 -#define __NR_utimes 251 -#define __NR_statfs64 252 -#define __NR_fstatfs64 253 -#define __NR_fadvise64_64 254 -#define __NR_rtas 255 -#define __NR_sys_debug_setcontext 256 -/* Number 257 is reserved for vserver */ -#define __NR_migrate_pages 258 -#define __NR_mbind 259 -#define __NR_get_mempolicy 260 -#define __NR_set_mempolicy 261 -#define __NR_mq_open 262 -#define __NR_mq_unlink 263 -#define __NR_mq_timedsend 264 -#define __NR_mq_timedreceive 265 -#define __NR_mq_notify 266 -#define __NR_mq_getsetattr 267 -#define __NR_kexec_load 268 -#define __NR_add_key 269 -#define __NR_request_key 270 -#define __NR_keyctl 271 -#define __NR_waitid 272 -#define __NR_ioprio_set 273 -#define __NR_ioprio_get 274 -#define __NR_inotify_init 275 -#define __NR_inotify_add_watch 276 -#define __NR_inotify_rm_watch 277 -#define __NR_spu_run 278 -#define __NR_spu_create 279 -#define __NR_pselect6 280 -#define __NR_ppoll 281 -#define __NR_unshare 282 -#define __NR_splice 283 -#define __NR_tee 284 -#define __NR_vmsplice 285 -#define __NR_openat 286 -#define __NR_mkdirat 287 -#define __NR_mknodat 288 -#define __NR_fchownat 289 -#define __NR_futimesat 290 -#define __NR_fstatat64 291 -#define __NR_unlinkat 292 -#define __NR_renameat 293 -#define __NR_linkat 294 -#define __NR_symlinkat 295 -#define __NR_readlinkat 296 -#define __NR_fchmodat 297 -#define __NR_faccessat 298 -#define __NR_get_robust_list 299 -#define __NR_set_robust_list 300 -#define __NR_move_pages 301 -#define __NR_getcpu 302 -#define __NR_epoll_pwait 303 -#define __NR_utimensat 304 -#define __NR_signalfd 305 -#define __NR_timerfd_create 306 -#define __NR_eventfd 307 -#define __NR_sync_file_range2 308 -#define __NR_fallocate 309 -#define __NR_subpage_prot 310 -#define __NR_timerfd_settime 311 -#define __NR_timerfd_gettime 312 -#define __NR_signalfd4 313 -#define __NR_eventfd2 314 -#define __NR_epoll_create1 315 -#define __NR_dup3 316 -#define __NR_pipe2 317 -#define __NR_inotify_init1 318 - - -#endif /* _ASM_POWERPC_UNISTD_H_ */