[LVS] Reading invalid SPICE netlist silently fails

[Scafir]

It seem that the LVS schematic function used to parse a spice file does not handle errors properly.

More specificaly, it seems the netlist.read call cannot fail:

klayout/src/lvs/lvs/built-in-macros/_lvs_netter.rb

Line 951 in ec5de0f

netlist.read(netlist_file, reader)

Interestingly enough, exceptions are raised in the read function:

klayout/src/db/db/dbNetlistSpiceReader.cc

Lines 485 to 511 in ec5de0f

	SpiceCircuitDict::read (tl::InputStream &stream)
	{
	try {
	m_stream.set_stream (stream);
	mp_circuit = 0;
	mp_anonymous_top_level_circuit = 0;
	m_called_circuits.clear ();
	m_variables.clear ();
	m_global_net_names.clear ();
	m_global_nets.clear ();
	m_file_id = file_id (stream.absolute_file_path ());
	while (! at_end ()) {
	read_card ();
	}
	} catch (tl::Exception &ex) {
	// Add a location to the exception
	std::string fmt_msg = ex.msg () + tl::sprintf (tl::to_string (tr (" in %s, line %d")), m_stream.source (), m_stream.line_number ());
	throw tl::Exception (fmt_msg);
	}
	}

The problems seems to come from the c++/ruby interface, where exceptions generated in c++ are not caught in ruby. Unfortunately, I do not have the skills to debug this much further.

A simple way to reproduce the error is to load the following SPICE file for an LVS comparison. You will see that only the first resistor is parsed, whereas the second is not present (due to the spice parser throwing on the "&%ç%&*+£à° line

.subckt top A B sub
R1 A B
"&%ç%&*+£à°
R2 A B
.ends

[klayoutmatthias]

Hi @Scafir,

no, errors are reported. The Ruby/C++ interface is not ignoring errors.

The Spice reader is pretty agnostic and silently skips things it does not understand. Spice is not a single format, but a messy universe of dialects. A parser being able to read all (or most) of them cannot implement one detailed syntax consistently.

Also, the Spice interface is intended to read Spice files generated for data exchange, i.e. netlisted or produced by some flow. Hence, it does not care about potential typing mistakes.

Here is a sample that demonstrates that the reader fails in "good, but wrong" Spice files:

test.sch:

.subckt TOP A B SUB
R1 A B 1k
T2 A SUB 2
R3 B SUB 3
.ends

test.rb:

sch = RBA::Netlist::new()
sch.read("test.sch", RBA::NetlistSpiceReader::new)
puts sch.to_s

Run with

klayout -b -r test.rb

and you will get:

ERROR: RuntimeError: Not a known element type: 'T' in /home/matthias/test.sch, line 3 in Netlist::read
  test.rb:3:in `read'
  test.rb:3:in `<main>'

I raged already about the nonsense that is called Spice format (https://peertube6.f-si.org/w/kcRQYj4wwFJFZ2hQNMoKxy). Why on earth are people not able to come up with a consistent and well-defined netlist format, free of punch-card legacy, embedded models or simulator control statements and using modern container formats? I'd be happy to adopt something in that direction.

Matthias

[Scafir]

Hi Matthias,

Many thanks for the great answer. It turns out I was too quick to identify the issue. There is still some a slight issue that could be corrected tough (which is the original reason I started looking into this).

Let's take the following test.sch file:

.subckt top A B sub
R1 A B 2
X1 a b i_do_not_exist
R2 A B 3
.ends

Then the parsed netlist is:

circuit TOP (A=A,B=B,SUB=SUB);
  device RES '1' (A=A,B=B) (R=2,L=0,W=0,A=0,P=0);
  device RES '2' (A=A,B=B) (R=3,L=0,W=0,A=0,P=0);
  subcircuit I_DO_NOT_EXIST '1' ('1'=A,'2'=B);
end;
circuit I_DO_NOT_EXIST ('1'='1','2'='2');
end;

I think that an error should have been generated: there are no i_do_not_exist subckt defined anywhere. The parser just silently assumes that it must be an empty circuit.

You have my sympathy for the jungle that is the SPICE "format". I hope it will be possible to ditch it at some point...