When I was compiling some program with snackhsail.sh (I do not know when it changed to snackhsail, the old snack.sh does not work properly. Is AMD giving up HSAIL?), I notice some instruction is not compatible with HSA tool chains. I got the following error:
> gcn_min_f32 $s5, $s9, $s5;
> ^
input(124,9): Undefined instruction
and
> gcn_divrelaxed_ftz_f32 $s4, $s5, $s4;
> ^
input(353,20): Undefined instruction
How does gcn_min different the min instruction in HSAIL and how does the gcn_divrelaxed different from the div instruction in HSAIL? Should the CLOC compile the HSAIL program or only compiles for AMD GCN devices? How can another vendor use CLOC or even HSAIL if it generates GCN specific instructions?
When I was compiling some program with snackhsail.sh (I do not know when it changed to snackhsail, the old snack.sh does not work properly. Is AMD giving up HSAIL?), I notice some instruction is not compatible with HSA tool chains. I got the following error:
and
How does gcn_min different the min instruction in HSAIL and how does the gcn_divrelaxed different from the div instruction in HSAIL? Should the CLOC compile the HSAIL program or only compiles for AMD GCN devices? How can another vendor use CLOC or even HSAIL if it generates GCN specific instructions?