From 626648a81ca8028b465a767772c83fc365e08194 Mon Sep 17 00:00:00 2001
From: Victor Hayashi <vtakashi@hotmail.com>
Date: Fri, 20 Mar 2026 14:31:56 -0300
Subject: [PATCH] Add icarus verilog and yosys colab examples

---
 .../(ALU) Icarus Verilog and Yosys.ipynb      | 5452 +++++++++++++
 ... and Adder) Icarus Verilog and Yosys.ipynb | 7250 +++++++++++++++++
 2 files changed, 12702 insertions(+)
 create mode 100644 colab-scripts/(ALU) Icarus Verilog and Yosys.ipynb
 create mode 100644 colab-scripts/(Counter and Adder) Icarus Verilog and Yosys.ipynb

diff --git a/colab-scripts/(ALU) Icarus Verilog and Yosys.ipynb b/colab-scripts/(ALU) Icarus Verilog and Yosys.ipynb
new file mode 100644
index 0000000..5a713f4
--- /dev/null
+++ b/colab-scripts/(ALU) Icarus Verilog and Yosys.ipynb	
@@ -0,0 +1,5452 @@
+{
+  "nbformat": 4,
+  "nbformat_minor": 0,
+  "metadata": {
+    "colab": {
+      "provenance": [],
+      "toc_visible": true
+    },
+    "kernelspec": {
+      "name": "python3",
+      "display_name": "Python 3"
+    },
+    "language_info": {
+      "name": "python"
+    }
+  },
+  "cells": [
+    {
+      "cell_type": "markdown",
+      "metadata": {
+        "id": "ngvQPp1y8pgZ"
+      },
+      "source": [
+        "# 🎁 Open EDA Tooling Treats\n",
+        "\n",
+        "```\n",
+        "Copyright 2021 Google LLC.\n",
+        "SPDX-License-Identifier: Apache-2.0\n",
+        "```\n",
+        "\n",
+        "Context: https://twitter.com/proppy/status/1466020384063430657"
+      ]
+    },
+    {
+      "cell_type": "markdown",
+      "source": [
+        "### ALU generated with Gemini 2.5 Flash"
+      ],
+      "metadata": {
+        "id": "Uu-dHmmYxEwC"
+      }
+    },
+    {
+      "cell_type": "markdown",
+      "source": [
+        "**Prompt**: alu in verilog\n",
+        "\n",
+        "**Response**: Here's a basic 4-bit ALU implementation in Verilog, generated by Gemini 2.5 Flash. It includes common operations like addition, subtraction, AND, OR, XOR, and NOT."
+      ],
+      "metadata": {
+        "id": "DLZzcNJaxlaN"
+      }
+    },
+    {
+      "cell_type": "code",
+      "source": [
+        "%%bash\n",
+        "cat <<EOF > alu.v\n",
+        "module alu(\n",
+        "  input [3:0] a,\n",
+        "  input [3:0] b,\n",
+        "  input [2:0] sel, // Operations: 000: add, 001: sub, 010: and, 011: or,\n",
+        "                   //             100: xor, 101: not(a), 110: pass(a)\n",
+        "  output reg [3:0] result,\n",
+        "  output reg zero_flag\n",
+        ");\n",
+        "\n",
+        "  always @(*) begin // Reverted to always @(*) for iverilog compatibility\n",
+        "    case (sel)\n",
+        "      3'b000: result = a + b; // Addition\n",
+        "      3'b001: result = a - b; // Subtraction\n",
+        "      3'b010: result = a & b; // Bitwise AND\n",
+        "      3'b011: result = a | b; // Bitwise OR\n",
+        "      3'b100: result = a ^ b; // Bitwise XOR\n",
+        "      3'b101: result = ~a;    // Bitwise NOT (on a)\n",
+        "      3'b110: result = a;     // Pass through a\n",
+        "      default: result = 4'b0000; // Defined default value\n",
+        "    endcase\n",
+        "\n",
+        "    if (result == 4'b0000) begin\n",
+        "      zero_flag = 1;\n",
+        "    end else begin\n",
+        "      zero_flag = 0;\n",
+        "    end\n",
+        "  end\n",
+        "\n",
+        "endmodule\n",
+        "EOF\n",
+        "\n",
+        "cat alu.v"
+      ],
+      "metadata": {
+        "colab": {
+          "base_uri": "https://localhost:8080/"
+        },
+        "id": "AtdEMnnzxG_y",
+        "outputId": "edd4b160-a40e-4d18-a32c-c3ec06084112"
+      },
+      "execution_count": 22,
+      "outputs": [
+        {
+          "output_type": "stream",
+          "name": "stdout",
+          "text": [
+            "module alu(\n",
+            "  input [3:0] a,\n",
+            "  input [3:0] b,\n",
+            "  input [2:0] sel, // Operations: 000: add, 001: sub, 010: and, 011: or,\n",
+            "                   //             100: xor, 101: not(a), 110: pass(a)\n",
+            "  output reg [3:0] result,\n",
+            "  output reg zero_flag\n",
+            ");\n",
+            "\n",
+            "  always @(*) begin // Reverted to always @(*) for iverilog compatibility\n",
+            "    case (sel)\n",
+            "      3'b000: result = a + b; // Addition\n",
+            "      3'b001: result = a - b; // Subtraction\n",
+            "      3'b010: result = a & b; // Bitwise AND\n",
+            "      3'b011: result = a | b; // Bitwise OR\n",
+            "      3'b100: result = a ^ b; // Bitwise XOR\n",
+            "      3'b101: result = ~a;    // Bitwise NOT (on a)\n",
+            "      3'b110: result = a;     // Pass through a\n",
+            "      default: result = 4'b0000; // Defined default value\n",
+            "    endcase\n",
+            "\n",
+            "    if (result == 4'b0000) begin\n",
+            "      zero_flag = 1;\n",
+            "    end else begin\n",
+            "      zero_flag = 0;\n",
+            "    end\n",
+            "  end\n",
+            "\n",
+            "endmodule\n"
+          ]
+        }
+      ]
+    },
+    {
+      "cell_type": "markdown",
+      "source": [
+        "**Prompt**: testbench for alu\n",
+        "\n",
+        "**Response**: Sure, here's a basic testbench for the alu.v module. It tests different operations like addition, subtraction, AND, OR, XOR, NOT, and pass-through. After running the cell below, I'll guide you on how to simulate it."
+      ],
+      "metadata": {
+        "id": "lYsCH6AN0Vyp"
+      }
+    },
+    {
+      "cell_type": "code",
+      "metadata": {
+        "colab": {
+          "base_uri": "https://localhost:8080/"
+        },
+        "id": "0c55da0b",
+        "outputId": "12ee918c-f049-41d7-c64a-e80278889815"
+      },
+      "source": [
+        "%%bash\n",
+        "cat <<'EOF' > alu_tb.v\n",
+        "module alu_tb;\n",
+        "\n",
+        "  // Inputs\n",
+        "  reg [3:0] a_tb;\n",
+        "  reg [3:0] b_tb;\n",
+        "  reg [2:0] sel_tb;\n",
+        "\n",
+        "  // Outputs\n",
+        "  wire [3:0] result_tb;\n",
+        "  wire zero_flag_tb;\n",
+        "\n",
+        "  // Instantiate the ALU module\n",
+        "  alu uut (\n",
+        "    .a(a_tb),\n",
+        "    .b(b_tb),\n",
+        "    .sel(sel_tb),\n",
+        "    .result(result_tb),\n",
+        "    .zero_flag(zero_flag_tb)\n",
+        "  );\n",
+        "\n",
+        "  initial begin\n",
+        "    // Test cases\n",
+        "    $display(\"Time\\ta\\tb\\tsel\\tresult\\tzero_flag\");\n",
+        "    $monitor(\"%0d\\t%h\\t%h\\t%b\\t%b\\t%b\", $time, a_tb, b_tb, sel_tb, result_tb, zero_flag_tb);\n",
+        "\n",
+        "    // Add VCD dumping commands\n",
+        "    $dumpfile(\"test.vcd\");\n",
+        "    $dumpvars(0, alu_tb); // Dump all signals in the alu_tb module\n",
+        "\n",
+        "    // Add: 2 + 3 = 5\n",
+        "    a_tb = 4'b0010;\n",
+        "    b_tb = 4'b0011;\n",
+        "    sel_tb = 3'b000; // Add\n",
+        "    #10;\n",
+        "\n",
+        "    // Subtract: 5 - 2 = 3\n",
+        "    a_tb = 4'b0101;\n",
+        "    b_tb = 4'b0010;\n",
+        "    sel_tb = 3'b001; // Subtract\n",
+        "    #10;\n",
+        "\n",
+        "    // AND: 3 & 5 = 1 (0011 & 0101 = 0001)\n",
+        "    a_tb = 4'b0011;\n",
+        "    b_tb = 4'b0101;\n",
+        "    sel_tb = 3'b010; // AND\n",
+        "    #10;\n",
+        "\n",
+        "    // OR: 3 | 5 = 7 (0011 | 0101 = 0111)\n",
+        "    a_tb = 4'b0011;\n",
+        "    b_tb = 4'b0101;\n",
+        "    sel_tb = 3'b011; // OR\n",
+        "    #10;\n",
+        "\n",
+        "    // XOR: 3 ^ 5 = 6 (0011 ^ 0101 = 0110)\n",
+        "    a_tb = 4'b0011;\n",
+        "    b_tb = 4'b0101;\n",
+        "    sel_tb = 3'b100; // XOR\n",
+        "    #10;\n",
+        "\n",
+        "    // NOT: ~A = ~0101 = 1010 (A=5)\n",
+        "    a_tb = 4'b0101;\n",
+        "    b_tb = 4'b0000; // B is not used for NOT operation\n",
+        "    sel_tb = 3'b101; // NOT\n",
+        "    #10;\n",
+        "\n",
+        "    // Pass: A = 7\n",
+        "    a_tb = 4'b0111;\n",
+        "    b_tb = 4'b0000; // B is not used for Pass operation\n",
+        "    sel_tb = 3'b110; // Pass\n",
+        "    #10;\n",
+        "\n",
+        "    // Test zero flag: 2 - 2 = 0\n",
+        "    a_tb = 4'b0010;\n",
+        "    b_tb = 4'b0010;\n",
+        "    sel_tb = 3'b001; // Subtract\n",
+        "    #10;\n",
+        "\n",
+        "    $finish;\n",
+        "  end\n",
+        "\n",
+        "endmodule\n",
+        "EOF\n",
+        "\n",
+        "cat alu_tb.v"
+      ],
+      "execution_count": 29,
+      "outputs": [
+        {
+          "output_type": "stream",
+          "name": "stdout",
+          "text": [
+            "module alu_tb;\n",
+            "\n",
+            "  // Inputs\n",
+            "  reg [3:0] a_tb;\n",
+            "  reg [3:0] b_tb;\n",
+            "  reg [2:0] sel_tb;\n",
+            "\n",
+            "  // Outputs\n",
+            "  wire [3:0] result_tb;\n",
+            "  wire zero_flag_tb;\n",
+            "\n",
+            "  // Instantiate the ALU module\n",
+            "  alu uut (\n",
+            "    .a(a_tb),\n",
+            "    .b(b_tb),\n",
+            "    .sel(sel_tb),\n",
+            "    .result(result_tb),\n",
+            "    .zero_flag(zero_flag_tb)\n",
+            "  );\n",
+            "\n",
+            "  initial begin\n",
+            "    // Test cases\n",
+            "    $display(\"Time\\ta\\tb\\tsel\\tresult\\tzero_flag\");\n",
+            "    $monitor(\"%0d\\t%h\\t%h\\t%b\\t%b\\t%b\", $time, a_tb, b_tb, sel_tb, result_tb, zero_flag_tb);\n",
+            "\n",
+            "    // Add VCD dumping commands\n",
+            "    $dumpfile(\"test.vcd\");\n",
+            "    $dumpvars(0, alu_tb); // Dump all signals in the alu_tb module\n",
+            "\n",
+            "    // Add: 2 + 3 = 5\n",
+            "    a_tb = 4'b0010;\n",
+            "    b_tb = 4'b0011;\n",
+            "    sel_tb = 3'b000; // Add\n",
+            "    #10;\n",
+            "\n",
+            "    // Subtract: 5 - 2 = 3\n",
+            "    a_tb = 4'b0101;\n",
+            "    b_tb = 4'b0010;\n",
+            "    sel_tb = 3'b001; // Subtract\n",
+            "    #10;\n",
+            "\n",
+            "    // AND: 3 & 5 = 1 (0011 & 0101 = 0001)\n",
+            "    a_tb = 4'b0011;\n",
+            "    b_tb = 4'b0101;\n",
+            "    sel_tb = 3'b010; // AND\n",
+            "    #10;\n",
+            "\n",
+            "    // OR: 3 | 5 = 7 (0011 | 0101 = 0111)\n",
+            "    a_tb = 4'b0011;\n",
+            "    b_tb = 4'b0101;\n",
+            "    sel_tb = 3'b011; // OR\n",
+            "    #10;\n",
+            "\n",
+            "    // XOR: 3 ^ 5 = 6 (0011 ^ 0101 = 0110)\n",
+            "    a_tb = 4'b0011;\n",
+            "    b_tb = 4'b0101;\n",
+            "    sel_tb = 3'b100; // XOR\n",
+            "    #10;\n",
+            "\n",
+            "    // NOT: ~A = ~0101 = 1010 (A=5)\n",
+            "    a_tb = 4'b0101;\n",
+            "    b_tb = 4'b0000; // B is not used for NOT operation\n",
+            "    sel_tb = 3'b101; // NOT\n",
+            "    #10;\n",
+            "\n",
+            "    // Pass: A = 7\n",
+            "    a_tb = 4'b0111;\n",
+            "    b_tb = 4'b0000; // B is not used for Pass operation\n",
+            "    sel_tb = 3'b110; // Pass\n",
+            "    #10;\n",
+            "\n",
+            "    // Test zero flag: 2 - 2 = 0\n",
+            "    a_tb = 4'b0010;\n",
+            "    b_tb = 4'b0010;\n",
+            "    sel_tb = 3'b001; // Subtract\n",
+            "    #10;\n",
+            "\n",
+            "    $finish;\n",
+            "  end\n",
+            "\n",
+            "endmodule\n"
+          ]
+        }
+      ]
+    },
+    {
+      "cell_type": "markdown",
+      "metadata": {
+        "id": "Miek1LUU9Xgx"
+      },
+      "source": [
+        "## 🍬 Treat #1: EDA Conda Packages & Notebooks\n",
+        "\n",
+        "The [conda-eda](https://github.com/hdl/conda-eda) project maintains a collection of conda packages recipes. Those package can be used to easily bootstrap EDA environments in Jupyter and Colab notebooks.\n",
+        "\n",
+        "This notebook shows how to lint Verilog cells and plot the simulated waveforms for a simple 4-bits counter design."
+      ]
+    },
+    {
+      "cell_type": "markdown",
+      "metadata": {
+        "id": "k9Ldv3KHAhJ8"
+      },
+      "source": [
+        "### Install packages\n",
+        "\n",
+        "Install packages from the `LiteX-Hub` [channel](https://anaconda.org/LiteX-Hub/repo); also install older packages from the `SymbiFlow` channel, to get better compat with colab: see [conda-eda#146](https://github.com/hdl/conda-eda/issues/146)."
+      ]
+    },
+    {
+      "cell_type": "code",
+      "metadata": {
+        "id": "RSskI42P9Sxa",
+        "colab": {
+          "base_uri": "https://localhost:8080/"
+        },
+        "outputId": "4b574234-562a-4833-954f-b01f80cc96ee"
+      },
+      "source": [
+        "!curl -O https://repo.anaconda.com/miniconda/Miniconda3-py37_4.10.3-Linux-x86_64.sh\n",
+        "!bash Miniconda3-py37_4.10.3-Linux-x86_64.sh -b -f -p miniconda-eda/\n",
+        "!miniconda-eda/bin/conda install --yes -c LiteX-Hub iverilog\n",
+        "!miniconda-eda/bin/conda install --yes -c SymbiFlow verible"
+      ],
+      "execution_count": 2,
+      "outputs": [
+        {
+          "output_type": "stream",
+          "name": "stdout",
+          "text": [
+            "  % Total    % Received % Xferd  Average Speed   Time    Time     Time  Current\n",
+            "                                 Dload  Upload   Total   Spent    Left  Speed\n",
+            "100 84.9M  100 84.9M    0     0  99.7M      0 --:--:-- --:--:-- --:--:-- 99.7M\n",
+            "PREFIX=/content/miniconda-eda\n",
+            "Unpacking payload ...\n",
+            "Collecting package metadata (current_repodata.json): - \b\b\\ \b\bdone\n",
+            "Solving environment: / \b\b- \b\b\\ \b\bdone\n",
+            "\n",
+            "## Package Plan ##\n",
+            "\n",
+            "  environment location: /content/miniconda-eda\n",
+            "\n",
+            "  added / updated specs:\n",
+            "    - _libgcc_mutex==0.1=main\n",
+            "    - _openmp_mutex==4.5=1_gnu\n",
+            "    - brotlipy==0.7.0=py37h27cfd23_1003\n",
+            "    - ca-certificates==2021.7.5=h06a4308_1\n",
+            "    - certifi==2021.5.30=py37h06a4308_0\n",
+            "    - cffi==1.14.6=py37h400218f_0\n",
+            "    - chardet==4.0.0=py37h06a4308_1003\n",
+            "    - conda-package-handling==1.7.3=py37h27cfd23_1\n",
+            "    - conda==4.10.3=py37h06a4308_0\n",
+            "    - cryptography==3.4.7=py37hd23ed53_0\n",
+            "    - idna==2.10=pyhd3eb1b0_0\n",
+            "    - ld_impl_linux-64==2.35.1=h7274673_9\n",
+            "    - libffi==3.3=he6710b0_2\n",
+            "    - libgcc-ng==9.3.0=h5101ec6_17\n",
+            "    - libgomp==9.3.0=h5101ec6_17\n",
+            "    - libstdcxx-ng==9.3.0=hd4cf53a_17\n",
+            "    - ncurses==6.2=he6710b0_1\n",
+            "    - openssl==1.1.1k=h27cfd23_0\n",
+            "    - pip==21.1.3=py37h06a4308_0\n",
+            "    - pycosat==0.6.3=py37h27cfd23_0\n",
+            "    - pycparser==2.20=py_2\n",
+            "    - pyopenssl==20.0.1=pyhd3eb1b0_1\n",
+            "    - pysocks==1.7.1=py37_1\n",
+            "    - python==3.7.10=h12debd9_4\n",
+            "    - readline==8.1=h27cfd23_0\n",
+            "    - requests==2.25.1=pyhd3eb1b0_0\n",
+            "    - ruamel_yaml==0.15.100=py37h27cfd23_0\n",
+            "    - setuptools==52.0.0=py37h06a4308_0\n",
+            "    - six==1.16.0=pyhd3eb1b0_0\n",
+            "    - sqlite==3.36.0=hc218d9a_0\n",
+            "    - tk==8.6.10=hbc83047_0\n",
+            "    - tqdm==4.61.2=pyhd3eb1b0_1\n",
+            "    - urllib3==1.26.6=pyhd3eb1b0_1\n",
+            "    - wheel==0.36.2=pyhd3eb1b0_0\n",
+            "    - xz==5.2.5=h7b6447c_0\n",
+            "    - yaml==0.2.5=h7b6447c_0\n",
+            "    - zlib==1.2.11=h7b6447c_3\n",
+            "\n",
+            "\n",
+            "The following NEW packages will be INSTALLED:\n",
+            "\n",
+            "  _libgcc_mutex      pkgs/main/linux-64::_libgcc_mutex-0.1-main\n",
+            "  _openmp_mutex      pkgs/main/linux-64::_openmp_mutex-4.5-1_gnu\n",
+            "  brotlipy           pkgs/main/linux-64::brotlipy-0.7.0-py37h27cfd23_1003\n",
+            "  ca-certificates    pkgs/main/linux-64::ca-certificates-2021.7.5-h06a4308_1\n",
+            "  certifi            pkgs/main/linux-64::certifi-2021.5.30-py37h06a4308_0\n",
+            "  cffi               pkgs/main/linux-64::cffi-1.14.6-py37h400218f_0\n",
+            "  chardet            pkgs/main/linux-64::chardet-4.0.0-py37h06a4308_1003\n",
+            "  conda              pkgs/main/linux-64::conda-4.10.3-py37h06a4308_0\n",
+            "  conda-package-han~ pkgs/main/linux-64::conda-package-handling-1.7.3-py37h27cfd23_1\n",
+            "  cryptography       pkgs/main/linux-64::cryptography-3.4.7-py37hd23ed53_0\n",
+            "  idna               pkgs/main/noarch::idna-2.10-pyhd3eb1b0_0\n",
+            "  ld_impl_linux-64   pkgs/main/linux-64::ld_impl_linux-64-2.35.1-h7274673_9\n",
+            "  libffi             pkgs/main/linux-64::libffi-3.3-he6710b0_2\n",
+            "  libgcc-ng          pkgs/main/linux-64::libgcc-ng-9.3.0-h5101ec6_17\n",
+            "  libgomp            pkgs/main/linux-64::libgomp-9.3.0-h5101ec6_17\n",
+            "  libstdcxx-ng       pkgs/main/linux-64::libstdcxx-ng-9.3.0-hd4cf53a_17\n",
+            "  ncurses            pkgs/main/linux-64::ncurses-6.2-he6710b0_1\n",
+            "  openssl            pkgs/main/linux-64::openssl-1.1.1k-h27cfd23_0\n",
+            "  pip                pkgs/main/linux-64::pip-21.1.3-py37h06a4308_0\n",
+            "  pycosat            pkgs/main/linux-64::pycosat-0.6.3-py37h27cfd23_0\n",
+            "  pycparser          pkgs/main/noarch::pycparser-2.20-py_2\n",
+            "  pyopenssl          pkgs/main/noarch::pyopenssl-20.0.1-pyhd3eb1b0_1\n",
+            "  pysocks            pkgs/main/linux-64::pysocks-1.7.1-py37_1\n",
+            "  python             pkgs/main/linux-64::python-3.7.10-h12debd9_4\n",
+            "  readline           pkgs/main/linux-64::readline-8.1-h27cfd23_0\n",
+            "  requests           pkgs/main/noarch::requests-2.25.1-pyhd3eb1b0_0\n",
+            "  ruamel_yaml        pkgs/main/linux-64::ruamel_yaml-0.15.100-py37h27cfd23_0\n",
+            "  setuptools         pkgs/main/linux-64::setuptools-52.0.0-py37h06a4308_0\n",
+            "  six                pkgs/main/noarch::six-1.16.0-pyhd3eb1b0_0\n",
+            "  sqlite             pkgs/main/linux-64::sqlite-3.36.0-hc218d9a_0\n",
+            "  tk                 pkgs/main/linux-64::tk-8.6.10-hbc83047_0\n",
+            "  tqdm               pkgs/main/noarch::tqdm-4.61.2-pyhd3eb1b0_1\n",
+            "  urllib3            pkgs/main/noarch::urllib3-1.26.6-pyhd3eb1b0_1\n",
+            "  wheel              pkgs/main/noarch::wheel-0.36.2-pyhd3eb1b0_0\n",
+            "  xz                 pkgs/main/linux-64::xz-5.2.5-h7b6447c_0\n",
+            "  yaml               pkgs/main/linux-64::yaml-0.2.5-h7b6447c_0\n",
+            "  zlib               pkgs/main/linux-64::zlib-1.2.11-h7b6447c_3\n",
+            "\n",
+            "\n",
+            "Preparing transaction: / \b\b- \b\b\\ \b\b| \b\bdone\n",
+            "Executing transaction: - \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\bdone\n",
+            "installation finished.\n",
+            "WARNING:\n",
+            "    You currently have a PYTHONPATH environment variable set. This may cause\n",
+            "    unexpected behavior when running the Python interpreter in Miniconda3.\n",
+            "    For best results, please verify that your PYTHONPATH only points to\n",
+            "    directories of packages that are compatible with the Python interpreter\n",
+            "    in Miniconda3: /content/miniconda-eda\n",
+            "Collecting package metadata (current_repodata.json): - \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\bdone\n",
+            "Solving environment: | \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\bdone\n",
+            "\n",
+            "\n",
+            "==> WARNING: A newer version of conda exists. <==\n",
+            "  current version: 4.10.3\n",
+            "  latest version: 26.1.1\n",
+            "\n",
+            "Please update conda by running\n",
+            "\n",
+            "    $ conda update -n base -c defaults conda\n",
+            "\n",
+            "\n",
+            "\n",
+            "## Package Plan ##\n",
+            "\n",
+            "  environment location: /content/miniconda-eda\n",
+            "\n",
+            "  added / updated specs:\n",
+            "    - iverilog\n",
+            "\n",
+            "\n",
+            "The following packages will be downloaded:\n",
+            "\n",
+            "    package                    |            build\n",
+            "    ---------------------------|-----------------\n",
+            "    ca-certificates-2025.12.2  |       h06a4308_0         125 KB\n",
+            "    iverilog-0_8_5850_g540555fc|  20211214_154543         2.4 MB  LiteX-Hub\n",
+            "    openssl-1.1.1w             |       h7f8727e_0         3.7 MB\n",
+            "    ------------------------------------------------------------\n",
+            "                                           Total:         6.3 MB\n",
+            "\n",
+            "The following NEW packages will be INSTALLED:\n",
+            "\n",
+            "  iverilog           LiteX-Hub/linux-64::iverilog-0_8_5850_g540555fc-20211214_154543\n",
+            "\n",
+            "The following packages will be UPDATED:\n",
+            "\n",
+            "  ca-certificates                       2021.7.5-h06a4308_1 --> 2025.12.2-h06a4308_0\n",
+            "  openssl                                 1.1.1k-h27cfd23_0 --> 1.1.1w-h7f8727e_0\n",
+            "\n",
+            "\n",
+            "\n",
+            "Downloading and Extracting Packages\n",
+            "iverilog-0_8_5850_g5 | 2.4 MB    | : 100% 1.0/1 [00:00<00:00,  1.14it/s]\n",
+            "openssl-1.1.1w       | 3.7 MB    | : 100% 1.0/1 [00:00<00:00,  2.19it/s]               \n",
+            "ca-certificates-2025 | 125 KB    | : 100% 1.0/1 [00:00<00:00,  5.50it/s]\n",
+            "Preparing transaction: - \b\bdone\n",
+            "Verifying transaction: | \b\b/ \b\bdone\n",
+            "Executing transaction: \\ \b\bdone\n",
+            "Collecting package metadata (current_repodata.json): - \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\bdone\n",
+            "Solving environment: / \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\bdone\n",
+            "\n",
+            "\n",
+            "==> WARNING: A newer version of conda exists. <==\n",
+            "  current version: 4.10.3\n",
+            "  latest version: 26.1.1\n",
+            "\n",
+            "Please update conda by running\n",
+            "\n",
+            "    $ conda update -n base -c defaults conda\n",
+            "\n",
+            "\n",
+            "\n",
+            "## Package Plan ##\n",
+            "\n",
+            "  environment location: /content/miniconda-eda\n",
+            "\n",
+            "  added / updated specs:\n",
+            "    - verible\n",
+            "\n",
+            "\n",
+            "The following packages will be downloaded:\n",
+            "\n",
+            "    package                    |            build\n",
+            "    ---------------------------|-----------------\n",
+            "    verible-0.0.836_0000_g1b1294c|  20201231_075710         4.2 MB  SymbiFlow\n",
+            "    ------------------------------------------------------------\n",
+            "                                           Total:         4.2 MB\n",
+            "\n",
+            "The following NEW packages will be INSTALLED:\n",
+            "\n",
+            "  verible            SymbiFlow/linux-64::verible-0.0.836_0000_g1b1294c-20201231_075710\n",
+            "\n",
+            "\n",
+            "\n",
+            "Downloading and Extracting Packages\n",
+            "verible-0.0.836_0000 | 4.2 MB    | : 100% 1.0/1 [00:01<00:00,  1.28s/it]\n",
+            "Preparing transaction: \\ \b\bdone\n",
+            "Verifying transaction: / \b\bdone\n",
+            "Executing transaction: \\ \b\bdone\n"
+          ]
+        }
+      ]
+    },
+    {
+      "cell_type": "markdown",
+      "metadata": {
+        "id": "qB751juXAzVO"
+      },
+      "source": [
+        "### Lint and simulate Verilog cells\n",
+        "\n",
+        "Use the `%%bash` magic to lint the content of the cell with [Verible](https://github.com/chipsalliance/verible) and simulate the test bench using [Icarus Verilog](http://iverilog.icarus.com/).\n"
+      ]
+    },
+    {
+      "cell_type": "markdown",
+      "source": [
+        "**Prompt**: *Simulate the `alu_tb.v` file*\n",
+        "\n",
+        "Some iterations for design correction for simulation were required"
+      ],
+      "metadata": {
+        "id": "jI0tdSzFyQ3N"
+      }
+    },
+    {
+      "cell_type": "code",
+      "metadata": {
+        "colab": {
+          "base_uri": "https://localhost:8080/"
+        },
+        "id": "emWMhIw4ef-P",
+        "outputId": "38465449-93a5-496b-83f6-c88a81111c09"
+      },
+      "source": [
+        "%%bash -c 'source miniconda-eda/bin/activate; iverilog -o alu_sim alu.v alu_tb.v -s alu_tb && vvp alu_sim'"
+      ],
+      "execution_count": 30,
+      "outputs": [
+        {
+          "output_type": "stream",
+          "name": "stdout",
+          "text": [
+            "Time\ta\tb\tsel\tresult\tzero_flag\n",
+            "VCD info: dumpfile test.vcd opened for output.\n",
+            "0\t2\t3\t000\t0101\t0\n",
+            "10\t5\t2\t001\t0011\t0\n",
+            "20\t3\t5\t010\t0001\t0\n",
+            "30\t3\t5\t011\t0111\t0\n",
+            "40\t3\t5\t100\t0110\t0\n",
+            "50\t5\t0\t101\t1010\t0\n",
+            "60\t7\t0\t110\t0111\t0\n",
+            "70\t2\t2\t001\t0000\t1\n",
+            "alu_tb.v:78: $finish called at 80 (1s)\n"
+          ]
+        }
+      ]
+    },
+    {
+      "cell_type": "markdown",
+      "metadata": {
+        "id": "9tKYXxifEFT7"
+      },
+      "source": [
+        "### Plot VCD waveforms\n",
+        "\n",
+        "Use [vcdvcd](https://pypi.org/project/vcdvcd/) VCD parser to plot the simulated waveform using regular matplotlib functions."
+      ]
+    },
+    {
+      "cell_type": "code",
+      "metadata": {
+        "id": "rUdsZqjBAF5o",
+        "colab": {
+          "base_uri": "https://localhost:8080/"
+        },
+        "outputId": "43ebb1fe-e2fc-4394-dbd7-0d89347f3a67"
+      },
+      "source": [
+        "!python -m pip install vcdvcd"
+      ],
+      "execution_count": 27,
+      "outputs": [
+        {
+          "output_type": "stream",
+          "name": "stdout",
+          "text": [
+            "Collecting vcdvcd\n",
+            "  Downloading vcdvcd-2.6.0-py3-none-any.whl.metadata (7.9 kB)\n",
+            "Downloading vcdvcd-2.6.0-py3-none-any.whl (12 kB)\n",
+            "Installing collected packages: vcdvcd\n",
+            "Successfully installed vcdvcd-2.6.0\n"
+          ]
+        }
+      ]
+    },
+    {
+      "cell_type": "markdown",
+      "source": [
+        "**Prompt**: Show how to plot VCD waveforms from test.vcd\n",
+        "\n",
+        "**Prompt**: the graphs are too small"
+      ],
+      "metadata": {
+        "id": "IqQGkagn2vjC"
+      }
+    },
+    {
+      "cell_type": "code",
+      "metadata": {
+        "id": "qfD7ywmvhEyU",
+        "colab": {
+          "base_uri": "https://localhost:8080/",
+          "height": 487
+        },
+        "outputId": "0da30259-7737-4c86-cc3e-e6dcce69899e"
+      },
+      "source": [
+        "from vcdvcd import VCDVCD\n",
+        "\n",
+        "vcd = VCDVCD('test.vcd')\n",
+        "import matplotlib.pyplot as plt\n",
+        "\n",
+        "# Updated signals list for alu_tb module\n",
+        "signals = [\n",
+        "    'alu_tb.a_tb[3:0]',\n",
+        "    'alu_tb.b_tb[3:0]',\n",
+        "    'alu_tb.sel_tb[2:0]',\n",
+        "    'alu_tb.result_tb[3:0]',\n",
+        "    'alu_tb.zero_flag_tb'\n",
+        "]\n",
+        "\n",
+        "f, plots = plt.subplots(len(signals), 1, sharex=True, figsize=(15, len(signals)*2)) # Increased figure width and height scaling\n",
+        "for s, ax in zip(signals, plots):\n",
+        "  x, y = zip(*vcd[s].tv)\n",
+        "  # Convert binary strings to integers for plotting\n",
+        "  y_int = []\n",
+        "  for val in y:\n",
+        "      if val == 'x': # Handle undefined values\n",
+        "          y_int.append(None)\n",
+        "      else:\n",
+        "          try:\n",
+        "              y_int.append(int(val, 2))\n",
+        "          except ValueError:\n",
+        "              y_int.append(None)\n",
+        "\n",
+        "  ax.step(x, y_int, label=s, where = 'post')\n",
+        "  ax.set_title(s)\n",
+        "  ax.set_yticks([0, 1]) # Assuming most signals are 1-bit or can be represented this way\n",
+        "  if 'alu_tb.sel_tb' in s or 'alu_tb.a_tb' in s or 'alu_tb.b_tb' in s or 'alu_tb.result_tb' in s:\n",
+        "    # For multi-bit signals, set appropriate y-ticks\n",
+        "    ax.set_yticks(range(0, 16, 1)) # For 4-bit signals, values from 0 to 15\n",
+        "\n",
+        "f.tight_layout()\n",
+        "f.show()"
+      ],
+      "execution_count": 33,
+      "outputs": [
+        {
+          "output_type": "display_data",
+          "data": {
+            "text/plain": [
+              "<Figure size 1500x1000 with 5 Axes>"
+            ],
+            "image/png": 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0bds2Bg4cGF/96ldj1KhREfH3wP1Pf/pT3HPPPfH2229HSUlJHHrooXHXXXfFoEGD0s+64YYbYsuWLXHzzTdHMpmMU045JX74wx+mQ+1MrrvuujjnnHPiu9/9bmzevDkdfO+Mn/3sZ3HBBRfEt771raivr4/p06enxywoKIj58+fHeeedFxdddFF07tw5pk+fHtOmTdupZ5911llxzz33xI9//ONYt25ddO3aNQ477LC4++6747Of/exOPeP888+Pdu3axbXXXhu/+c1voqysLH784x/HN7/5zZ26HwAAIiISqX/+O1EAAIDdZNGiRTFmzJh48MEHY9SoUdGlS5do23b3r/dZv3591NXVxQknnBA1NTXxwgsv7PYaAADYc9kjHQAAyLuJEydGz549Y9myZXkZ//TTT4+ePXvGH/7wh7yMDwDAns2KdAAAWrR33nkn4xuXFhYW2iv7nzQ0NMQ777yTsU+nTp2iU6dOH3us999/P5YuXZo+HzFiRHTu3PljP7e5/vznP6f3lO/UqVMcdthhu70GAAD2XIJ0AABatIEDB8aqVas+8voRRxwRixYt2n0FfQKsXLmyyf7r2zN9+vSYMWPG7ikIAADyrNmbDz7++OPxwx/+MJYuXRpvvfVWzJ07NyZOnJi+fsYZZ8Ttt9/e5J5x48bF/PnzP3axAADQXHfddVds3rz5I6937dp1N1bzydCnT5945JFHMvbZa6+9dlM1AACQf80O0jdu3BgHHXRQnHXWWXHiiSdut8+xxx4bs2fPTp8nk8ldrxAAAD6GUaNG5buET5z27dvH2LFj810GAADsMZodpI8fPz7Gjx+fsU8ymYw+ffrs1PPq6uqirq4ufd7Y2Bj/93//F927d49EItHc8gAAAAAAYIdSqVSsX78+SktLo02bNhn7NjtI3xmLFi2KXr16RdeuXePII4+MK664Irp3777dvlVVVXHZZZflogwAAAAAAMho9erV0a9fv4x9PtabjSYSiW32SL/nnnuiQ4cOMWjQoHjttdfikksuiU6dOsVTTz0VBQUF2zzjn1ek19TURP/+/WP16tVRXFy8q6UBAAAAAMBHqq2tjbKysli3bl2UlJRk7Jv1Femnnnpq+uNPf/rTMXTo0Bg8eHAsWrQojjrqqG36J5PJ7e6hXlxcLEgHAAAAACCndmaL8cwbv2TBXnvtFT169Ijly5fneigAAAAAAMi6nAfpf/vb3+K9996Lvn375nooAAAAAADIumZv7bJhw4Ymq8tXrFgRy5Yti27dukW3bt3isssuiy996UvRp0+feO211+I///M/Y8iQITFu3LisFg4AAAAAALtDs4P02267LaZOnZo+r6ioiIiI8vLyqK6ujj//+c9x++23x7p16yKZTMaGDRvi8ssv3+4+6AAAAAAAsKdr9tYu++yzT1x66aXxq1/9KiIi5s6dG6lUKubMmRNFRUWxYMGCWLt2bdx7770xePDgKC0tjc6dO2e9cAAAAAAA2B2avSJ9/PjxMX78+Ix93njjjbjgggtiwYIFMWHChF0uDgAAAAAA8q3ZQfqONDY2xumnnx4XXXRRHHDAATvsX1dXF3V1denz2trabJcEAAAAAAC7rNlbu+zI1VdfHW3bto0LL7xwp/pXVVVFSUlJ+igrK8t2SQAAAAAAsMuyGqQvXbo0rr/++pgzZ04kEomduqeysjJqamrSx+rVq7NZEgAAAAAAfCxZDdL/53/+J9auXRv9+/ePtm3bRtu2bWPVqlXx7W9/OwYOHLjde5LJZBQXFzc5AAAAAABgT5HVPdJPP/30GDt2bJO2cePGxemnnx5nnnlmNocCAAAAAIDdotlB+oYNG2L58uXp8xUrVsSyZcuiW7du0b9//+jevXuT/u3atYs+ffrEvvvu+/GrBQAAAACA3azZQfqSJUtizJgx6fOKioqIiCgvL485c+ZkrTAAAAAAANgTNHuP9DZt2sQXvvCF6Nu3b0REzJ07N1KpVDpEnzFjRuy3337RsWPH6Nq1awwZMiRGjhyZ1aIBAAAAAGB3aXaQvnHjxjjooIPixhtv3O71ffbZJ2bNmhXPP/98PPHEEzFw4MA45phj4p133vnYxQIAAAAAwO6WSKVSqV2+OZGIuXPnxsSJEz+yT21tbZSUlMTChQvjqKOO2uZ6XV1d1NXVNelfVlYWNTU1UVxcvKulAQAAAADAR9qaXe9MFt3sFenNUV9fH7feemuUlJTEQQcdtN0+VVVVUVJSkj7KyspyWRIAAAAAADRLToL0efPmRadOnaJ9+/bx4x//OB555JHo0aPHdvtWVlZGTU1N+li9enUuSgIAAAAAgF3SNhcPHTNmTCxbtizefffd+OlPfxqnnHJK/PGPf4xevXpt0zeZTEYymcxFGQAAAAAA8LHlZEV6x44dY8iQIXHYYYfFbbfdFm3bto3bbrstF0MBAAAAAEBO5XSP9K0aGxubvKEoAAAAAAB8UjR7a5cNGzbE8uXL0+crVqyIZcuWRbdu3aJ79+5x5ZVXxvHHHx99+/aNd999N2688cZ444034uSTT85q4QAAAAAAsDskUqlUqjk3XH/99TF16tRt2svLy+OGG26IYcOGxYoVK+LDDz+MNm3aRGlpadxyyy3x+c9/fqeeX1tbGyUlJVFTUxPFxcXNKQ0AAAAAAHZKc7LoZm/tss8++8Sll14av/rVryIiYu7cuZFKpWLOnDnR2NgYAwYMiLvuuiteeumlePLJJ6O0tDSmTZu2a68EAAAAAADyrNkr0pvcnEjE3LlzY+LEiR/Z55lnnolDDz00Vq1aFf3799/hM61IBwAAAAAg15qTRTd7j/TmqqmpiUQiEV26dNnu9bq6uiZvRFpbW5vrkgAAAAAAYKc1e2uX5vjggw/iO9/5Tpx22mkfmehXVVVFSUlJ+igrK8tlSQAAAAAA0Cw5C9K3bNkSp5xySqRSqaiurv7IfpWVlVFTU5M+Vq9enauSAAAAAACg2XKytcvWEH3VqlXx3//93xn3l0kmk5FMJnNRBgAAAAAAfGxZD9K3huivvvpqPPbYY9G9e/dsDwEAAAAAALtNs4P0DRs2xPLly9PnK1asiGXLlkW3bt2ib9++cdJJJ8Wzzz4b8+bNi4aGhlizZk1ERHTr1i0KCwuzVzkAAAAAAOwGiVQqlWrODYsWLYoxY8Zs015eXh4zZsyIQYMGbfe+xx57LEaPHr3D59fW1kZJSUnU1NRk3BIGAAAAAAB2VXOy6Ga/2WibNm3iC1/4QvTt2zciIubOnRupVCrmzJkTAwcOjAceeCCOPvro6NatW0REPPfcc5FKpXYqRAcAAAAAgD1Ns4P0jRs3xkEHHRQ33njjR14//PDD4+qrr/7YxQEAAAAAQL41e4/08ePHx/jx4z/y+umnnx4REStXrtyp59XV1UVdXV36vLa2trklAQAAAABAzjR7RXq2VVVVRUlJSfooKyvLd0kAAAAAAJCW9yC9srIyampq0sfq1avzXRIAAAAAAKQ1e2uXbEsmk5FMJvNdBgAAAAAAbFfeV6QDAAAAAMCeTJAOAAAAAAAZNHtrlw0bNsTy5cvT5ytWrIhly5ZFt27don///vF///d/8frrr8ebb74ZEREvv/xyRET06dMn+vTpk6WyAQAAAABg92j2ivTbbrstDjnkkDjkkEMiIqKioiIOOeSQmDZtWkRE/PrXv45DDjkkJkyYEBERp556ahxyyCFx8803Z7FsAAAAAADYPZodpO+zzz5x6aWXxq9+9auIiJg7d26kUqmYM2dORESsXbs2SkpK4sEHH4z//d//jeOPPz4GDRoUF198cVYLBwAAAACA3aHZW7uMHz8+xo8fv91rqVQqZs6cGd/97nfjhBNOiIiIn//859G7d+948MEH49RTT/141QIAAAC7XSqVis1bGvJdBuwWRe0KIpFI5LsMYA/T7CA9kxUrVsSaNWti7Nix6baSkpIYMWJEPPXUU9sN0uvq6qKuri59Xltbm82SAAAAgI8hlUrFSTc/FUtXvZ/vUmC3GD6ga9x37khhOtBEs7d2yWTNmjUREdG7d+8m7b17905f+2dVVVVRUlKSPsrKyrJZEgAAAPAxbN7SIESnVVmy6n1/gQFsI6sr0ndFZWVlVFRUpM9ra2uF6QAAALAHWvLdsdGhsCDfZUBObKpviOFXLMx3GcAeKqtBep8+fSIi4u23346+ffum299+++04+OCDt3tPMpmMZDKZzTIAAACAHOhQWBAdCvO+Jg8Adrusbu0yaNCg6NOnTzz66KPpttra2vjjH/8YI0eOzOZQAAAAAACwWzT7v5E3bNgQy5cvT5+vWLEili1bFt26dYv+/fvH1KlT44orroi99947Bg0aFN/73veitLQ0Jk6cmM26AQAAAABgt2h2kL5kyZIYM2ZM+nzr/ubl5eUxZ86c+M///M/YuHFjnHPOObFu3bo4/PDDY/78+dG+ffvsVQ0AAAAAALtJs4P00aNHRyqV+sjriUQiLrrooqitrY25c+fGk08+GWeccUZcf/318ZnPfOZjFQsAAAAAALtbVvdI3+rss8+ORx55JO644454/vnn45hjjomxY8fGG2+8kYvhAAAAAAAgZ7IepG/evDkeeOCBuOaaa+Jzn/tcDBkyJGbMmBFDhgyJ6urqbA8HAAAAAAA51eytXXbkww8/jIaGhm32RC8qKoonnnhim/51dXVRV1eXPq+trc12SQAAAAAAsMuyviK9c+fOMXLkyPj+978fb775ZjQ0NMSdd94ZTz31VLz11lvb9K+qqoqSkpL0UVZWlu2SAAAAAABgl+Vkj/Q77rgjUqlU/Mu//Eskk8n4yU9+Eqeddlq0abPtcJWVlVFTU5M+Vq9enYuSAAAAAABgl2R9a5eIiMGDB8fixYtj48aNUVtbG3379o0vf/nLsddee23TN5lMRjKZzEUZAAAAAADwseVkRfpWHTt2jL59+8b7778fCxYsiBNOOCGXwwEAAAAAQNblZEX6ggULIpVKxb777hvLly+Piy66KPbbb78488wzczEcAAAAAADkTE5WpNfU1MTkyZNjv/32i6997Wtx+OGHx4IFC6Jdu3a5GA4AAAAAAHIm60F6Q0NDPP/889HY2Bht2rSJDh06RO/evaO4uDjbQwEAAAAAQM5lfWuXq6++Oqqrq+P222+PAw44IJYsWRJnnnlmlJSUxIUXXpjt4QAAAAAAIKeyHqT/4Q9/iBNOOCEmTJgQEREDBw6MX/ziF/GnP/1pu/3r6uqirq4ufV5bW5vtkgAAAAAAYJdlfWuXf/u3f4tHH300XnnllYiI+N///d944oknYvz48dvtX1VVFSUlJemjrKws2yUBAAAAAMAuy/qK9Isvvjhqa2tjv/32i4KCgmhoaIgrr7wyJk2atN3+lZWVUVFRkT6vra0VpgMAAAAAsMfIepD+y1/+Mu666664++6744ADDohly5bF1KlTo7S0NMrLy7fpn0wmI5lMZrsMAAAAAADIiqwH6RdddFFcfPHFceqpp0ZExKc//elYtWpVVFVVbTdIBwAAAACAPVnW90jftGlTtGnT9LEFBQXR2NiY7aEAAAAAACDnsr4i/bjjjosrr7wy+vfvHwcccEA899xzcd1118VZZ52V7aEAAAAAACDnsh6k//d//3e88cYb8YUvfKFJe01NTbaHAgAAAACAnMt6kL506dJoaGhIn7/wwgtx9NFHp/dMBwAAAACAT5KsB+k9e/Zscn7VVVfF4MGD44gjjsj2UAAA7IFSqVRs3tKw447QAhS1K4hEIpHvMgDIsk31fpah5fNzTPNkPUj/R/X19XHnnXdGRUXFR35R6urqoq6uLn1eW1uby5IAAMihVCoVJ938VCxd9X6+S4HdYviArnHfuSP9EgrQwgy/YmG+S4Cc83NM87TJ5cMffPDBWLduXZxxxhkf2aeqqipKSkrSR1lZWS5LAgAghzZvaRCi06osWfW+v8AAaCGK2hXE8AFd810G7DZ+jmmenK5Iv+2222L8+PFRWlr6kX0qKyujoqIifV5bWytMBwBoAZZ8d2x0KCzIdxmQE5vqG6xWBGhhEolE3HfuSMEiLZ6fY3ZNzoL0VatWxcKFC+NXv/pVxn7JZDKSyWSuygAAIE86FBZEh8KcrtsAAMiqRCLh5xdgu3K2tcvs2bOjV69eMWHChFwNAQAAAAAAOZeTIL2xsTFmz54d5eXl0bat/8UDAAAAAOCTKydB+sKFC+P111+Ps846KxePBwAAAACA3SYnQfoBBxwQkyZNipEjR0ZRUVF8+tOfjiVLluRiKAAAAAAAyKms77vy/vvvx6hRo2LMmDHx8MMPR8+ePePVV1+Nrl27ZnsoAACAvNtU35DvEiCnzHEAyEGQfvXVV0dZWVnMnj073TZo0KCP7F9XVxd1dXXp89ra2myXBAAAkDPDr1iY7xIAAMixrG/t8pvf/CaGDx8eJ598cvTq1SsOOeSQ+OlPf/qR/auqqqKkpCR9lJWVZbskAACArCpqVxDDB/irW1qX4QO6RlG7gnyXAQB5kfUV6X/961+juro6Kioq4pJLLolnnnkmLrzwwigsLIzy8vJt+ldWVkZFRUX6vLa2VpgOAADs0RKJRNx37sjYvMWWF7QeRe0KIpFI5LsMAMiLrAfpjY2NMXz48PjBD34QERGHHHJIvPDCC3HzzTdvN0hPJpORTCazXQYAAEBOJRKJ6FCY9V+pAADYA2V9a5e+ffvG/vvv36TtU5/6VLz++uvZHgoAAAAAAHIu60H6qFGj4uWXX27S9sorr8SAAQOyPRQAAAAAAORc1oP0b33rW/H000/HD37wg1i+fHncfffdceutt8bkyZOzPRQAAAAAAORc1oP0hx56KD788MO49NJLY++9945JkyZF586dY9KkSdkeCgAAAAAAci4n74xzwAEHxMKFC//fIG29AQ8AAAAAAJ9MOUm427ZtG3369MnFo1uFVCoVm7c05LsM2G2K2hVEIpHIdxkAAAAAsF05CdJfffXVKC0tjfbt28fIkSOjqqoq+vfvv92+dXV1UVdXlz6vra3NRUmfKJu3NMT+0xbkuwzYbYYP6Br3nTtSmA4AAADAHinre6SPGDEi5syZE/Pnz4/q6upYsWJFfPazn43169dvt39VVVWUlJSkj7KysmyXBOzhlqx6319hAAAAALDHyvqK9PHjx6c/Hjp0aIwYMSIGDBgQv/zlL+Pf//3ft+lfWVkZFRUV6fPa2tpWH6YXtSuIFy8fl+8yIOc21TfE8CsW7rgjAAAAAORRzt8FtEuXLrHPPvvE8uXLt3s9mUxGMpnMdRmfKIlEIjoUeoNWAAAAAIA9Qda3dvlnGzZsiNdeey369u2b66EAAAAAACDrsh6k/8d//EcsXrw4Vq5cGX/4wx/ii1/8YhQUFMRpp52W7aEAAAAAACDnsr5/yN/+9rc47bTT4r333ouePXvG4YcfHk8//XT07Nkz20MBAAAAAEDOZX1F+j333BNvvvlm1NXVxd/+9rc4+OCDY8iQITF16tRsDwUAAAAAADmX0z3Sn3nmmbjlllti6NChuRwGAAAAAAByJmdB+oYNG2LSpEnx05/+NLp27fqR/erq6qK2trbJAQAAAAAAe4qcBemTJ0+OCRMmxNixYzP2q6qqipKSkvRRVlaWq5IAAAAAAKDZchKk33PPPfHss89GVVXVDvtWVlZGTU1N+li9enUuSgIAAAAAgF3SNtsPXL16dXzzm9+MRx55JNq3b7/D/slkMpLJZLbLAAAAAACArMh6kL506dJYu3Zt/Ou//mu6raGhIR5//PGYNWtW1NXVRUFBQbaHBQAAAACAnMh6kH7UUUfF888/36TtzDPPjP322y++853vCNEBAAAAAPhEyXqQ3rlz5zjwwAObtHXs2DG6d+++TTsAAAAAAOzpsv5mo9XV1TF06NAoLi6O4uLiGDlyZPzf//1ftocBAAAAAIDdIutBer9+/eKqq66KpUuXxpIlS+LII4+Ml156Kb7+9a9neygAAAAAAMi5rG/tctxxxzU5v/LKK6O6ujqefvrpOOCAA7I9HNBCbKpvyHcJsFsUtSuIRCKR7zIAAACAZsh6kP6PGhoa4r777ouNGzfGyJEjt9unrq4u6urq0ue1tbW5LAnYQw2/YmG+S4DdYviArnHfuSOF6QAAAPAJkvWtXSIinn/++ejUqVMkk8k499xzY+7cubH//vtvt29VVVWUlJSkj7KyslyUBOyBitoVxPABXfNdBuxWS1a9H5u3+AsMAAAA+CTJyYr0fffdN5YtWxY1NTVx//33R3l5eSxevHi7YXplZWVUVFSkz2tra4Xp0EokEom479yRQkVahU31Df7yAgAAAD6hchKkFxYWxpAhQyIiYtiwYfHMM8/E9ddfH7fccss2fZPJZCSTyVyUAXwCJBKJ6FCY012mAAAAAOBjycnWLv+ssbGxyT7oAAAAAADwSZH1ZaCVlZUxfvz46N+/f6xfvz7uvvvuWLRoUSxYsCDbQwEAAAAAQM5lPUhfu3ZtfO1rX4u33norSkpKYujQobFgwYI4+uijsz0UAAAAAADkXNa3dhkyZEj07NkzCgsLIyKiU6dO0b9//2wPAwAAAAAAu0XWg/TFixfH5MmT4+mnn45HHnkktmzZEsccc0xs3Lgx20MBAAAAAEDOZX1rl/nz5zc5nzNnTvTq1SuWLl0an/vc57bpX1dX1+SNSGtra7NdEgAAAAAA7LKsr0j/ZzU1NRER0a1bt+1er6qqipKSkvRRVlaW65IAAAAAAGCn5TRIb2xsjKlTp8aoUaPiwAMP3G6fysrKqKmpSR+rV6/OZUkAAAAAANAsWd/a5R9Nnjw5XnjhhXjiiSc+sk8ymYxkMpnLMgAAAAAAYJflLEifMmVKzJs3Lx5//PHo169froYBAAAAAICcynqQnkql4oILLoi5c+fGokWLYtCgQdkeAgAAAAAAdpusB+mTJ0+Ou+++O379619H586dY82aNRERUVJSEkVFRdkeDgAAAAAAcirrbzZaXV0dNTU1MXr06Ojbt2/6uPfee7M9FAAAAAAA5FzWV6T/7ne/iyeffDKGDRsWJ554YsydOzcmTpyY7WEAAAAAAGC3yHqQPn78+Bg/fny2HwsALcam+oZ8lwA5Y34DAAAtUdaD9Oaqq6uLurq69HltbW0eqwGA3Bt+xcJ8lwAAAAA0Q9b3SG+uqqqqKCkpSR9lZWX5LgkAsq6oXUEMH9A132XAbjN8QNcoaleQ7zIAAACyIu8r0isrK6OioiJ9XltbK0wHoMVJJBJx37kjY/MW217QOhS1K4hEIpHvMgAAALIi70F6MpmMZDKZ7zIAIOcSiUR0KMz7P70AAABAM+V9axcAAAAAANiTZX1Z3IYNG2L58uXp8xUrVsSyZcuiW7du0b9//2wPBwAAAAAAOZX1IH3JkiUxZsyY9PnW/c/Ly8tjzpw52R4OAAAAAAByKutbu4wePTpSqVTMmjUrBgwYEMlkMg499NA4//zzsz0UAAAAAADkXE72SL/33nujoqIipk+fHs8++2wcdNBBMW7cuFi7dm0uhgMAAAAAgJzJSZB+3XXXxde//vU488wzY//994+bb745OnToEP/1X/+Vi+EAAAAAACBnsh6k19fXx9KlS2Ps2LH/b5A2bWLs2LHx1FNPbdO/rq4uamtrmxwAAAAAALCnyHqQ/u6770ZDQ0P07t27SXvv3r1jzZo12/SvqqqKkpKS9FFWVpbtkgAAAAAAYJflZGuX5qisrIyampr0sXr16nyXBAAAAADQIhW1K4gXLx8XL14+LoraFeS7nE+Mttl+YI8ePaKgoCDefvvtJu1vv/129OnTZ5v+yWQykslktssAAAAAAOCfJBKJ6FCY9Vi4xcv6Z6ywsDCGDRsWjz76aEycODEiIhobG+PRRx+NKVOm7PD+VCoVEWGvdAAAAAAAcmZrBr01k84kJ//1UFFREeXl5TF8+PA49NBDY+bMmbFx48Y488wzd3jv+vXrIyLslQ4AAAAAQM6tX78+SkpKMvbJSZD+5S9/Od55552YNm1arFmzJg4++OCYP3/+Nm9Auj2lpaWxevXq6Ny5cyQSiVyU94lQW1sbZWVlsXr16iguLs53OZAz5jqtiflOa2Gu01qY67Qm5juthblOa2Gu/10qlYr169dHaWnpDvsmUjuzbp3drra2NkpKSqKmpqZVT2ZaPnOd1sR8p7Uw12ktzHVaE/Od1sJcp7Uw15uvTb4LAAAAAACAPZkgHQAAAAAAMhCk76GSyWRMnz49kslkvkuBnDLXaU3Md1oLc53WwlynNTHfaS3MdVoLc7357JEOAAAAAAAZWJEOAAAAAAAZCNIBAAAAACADQToAAAAAAGQgSAcAAAAAgAwE6QAAAAAAkIEgHQAAAAAAMhCkAwAAAABABoJ0AAAAAADIQJAOAAAAAAAZCNIBAAAAACADQToAAAAAAGQgSAcAAAAAgAwE6QAAAAAAkIEgHQAAAAAAMhCkAwAAAABABoJ0AAAAAADIQJAOAAAAAAAZCNIBAAAAACADQToAAJ9oixYtikQiEYsWLdqt486ZMycSiUQsWbJkt46bT/Pnz4+DDz442rdvH4lEItatWxdnnHFGDBw4MN+lfaQzzjgjOnXqlO8yAAD4hBOkAwBABjfddFPMmTMn32Xk3XvvvRennHJKFBUVxY033hh33HFHdOzYMd9lRUTEpk2bYsaMGbv9P1MAAGg92ua7AAAA2JPddNNN0aNHjzjjjDPyXUpePfPMM7F+/fr4/ve/H2PHjs13OU1s2rQpLrvssoiIGD16dH6LAQCgRbIiHQAAWqCNGzdm9Xlr166NiIguXbpk9bkAAPBJIEgHAGCPtGrVqjj//PNj3333jaKioujevXucfPLJsXLlyh3eO3DgwO2uIB89enSzViwPHDgw/vKXv8TixYsjkUhEIpHY5v5NmzbFN77xjejevXsUFxfH1772tXj//fczPnfrvu7bO/55v/GHH344PvvZz0bHjh2jc+fOMWHChPjLX/7SpM/WfcBfe+21+PznPx+dO3eOSZMmRcTfA/Vvf/vbUVZWFslkMvbdd9/40Y9+FKlUaqc/D6NHj47y8vKIiPjMZz4TiUQi4wr9H/3oR/Fv//Zv0b179ygqKophw4bF/fffv02/zZs3x4UXXhg9evSIzp07x/HHHx9vvPFGJBKJmDFjxk7VtnLlyujZs2dERFx22WXpz+M/3//Xv/41xo0bFx07dozS0tK4/PLLm/U5AACgdbO1CwAAe6Rnnnkm/vCHP8Spp54a/fr1i5UrV0Z1dXWMHj06XnzxxejQoUPOa5g5c2ZccMEF0alTp7j00ksjIqJ3795N+kyZMiW6dOkSM2bMiJdffjmqq6tj1apV6bB8ez71qU/FHXfc0aRt3bp1UVFREb169Uq33XHHHVFeXh7jxo2Lq6++OjZt2hTV1dVx+OGHx3PPPdckdP/www9j3Lhxcfjhh8ePfvSj6NChQ6RSqTj++OPjsccei3//93+Pgw8+OBYsWBAXXXRRvPHGG/HjH/94pz4Pl156aey7775x6623xuWXXx6DBg2KwYMHf2T/66+/Po4//viYNGlS1NfXxz333BMnn3xyzJs3LyZMmJDud8YZZ8Qvf/nLOP300+Owww6LxYsXN7m+M3r27BnV1dVx3nnnxRe/+MU48cQTIyJi6NCh6T4NDQ1x7LHHxmGHHRbXXHNNzJ8/P6ZPnx4ffvhhXH755c0aDwCAVioFAAB7oE2bNm3T9tRTT6UiIvXzn/883fbYY4+lIiL12GOPpdsGDBiQKi8v3+b+I444InXEEUc0q44DDjhgu/fMnj07FRGpYcOGperr69Pt11xzTSoiUr/+9a93eozGxsbUF77whVSnTp1Sf/nLX1KpVCq1fv36VJcuXVJf//rXm/Rds2ZNqqSkpEl7eXl5KiJSF198cZO+Dz74YCoiUldccUWT9pNOOimVSCRSy5cv3+kat77eZ555pkl7eXl5asCAAU3a/vlrV19fnzrwwANTRx55ZLpt6dKlqYhITZ06tUnfM844IxURqenTp+90be+8885H3rP1c3PBBRek2xobG1MTJkxIFRYWpt55552dHgcAgNbL1i4AAOyRioqK0h9v2bIl3nvvvRgyZEh06dIlnn322TxW1tQ555wT7dq1S5+fd9550bZt2/jd736308/4/ve/H/PmzYs5c+bE/vvvHxERjzzySKxbty5OO+20ePfdd9NHQUFBjBgxIh577LFtnnPeeec1Of/d734XBQUFceGFFzZp//a3vx2pVCoefvjh5rzUnfaPX7v3338/ampq4rOf/WyTr9v8+fMjIuL8889vcu8FF1yQk5qmTJmS/jiRSMSUKVOivr4+Fi5cmJPxAABoWWztAgDAHmnz5s1RVVUVs2fPjjfeeKPJftY1NTV5rKypvffeu8l5p06dom/fvju1l3vE3wPlyy67LCorK+NLX/pSuv3VV1+NiIgjjzxyu/cVFxc3OW/btm3069evSduqVauitLQ0Onfu3KT9U5/6VPp6LsybNy+uuOKKWLZsWdTV1aXb/3Grm1WrVkWbNm1i0KBBTe4dMmRI1utp06ZN7LXXXk3a9tlnn4iInf46AQDQugnSAQDYI11wwQUxe/bsmDp1aowcOTJKSkoikUjEqaeeGo2NjRnv/ai9yRsaGqKgoCAX5e6SFStWxKRJk+Loo4+OK664osm1ra/xjjvuiD59+mxzb9u2TX+UTyaT0aZN/v/g9H/+53/i+OOPj8997nNx0003Rd++faNdu3Yxe/bsuPvuu/NdHgAA7BJBOgAAe6T7778/ysvL49prr023ffDBB7Fu3bod3tu1a9ft9lu1atU2K5N35KNC+a1effXVGDNmTPp8w4YN8dZbb8XnP//5jPdt3rw5TjzxxOjSpUv84he/2CYE3/pmnr169YqxY8c2q+atBgwYEAsXLoz169c3WZX+0ksvpa9n2wMPPBDt27ePBQsWRDKZTLfPnj17m9oaGxtjxYoVTVb1L1++vNlj7uhr1NjYGH/961/Tq9AjIl555ZWIiCZv2AoAAB8l/0tWAABgOwoKCpps5xIRccMNN0RDQ8MO7x08eHA8/fTTUV9fn26bN29erF69utl1dOzYMWN4f+utt8aWLVvS59XV1fHhhx/G+PHj021vvfVWvPTSS036nXvuufHKK6/E3Llzo2vXrts8d9y4cVFcXBw/+MEPmty31TvvvLPD2j//+c9HQ0NDzJo1q0n7j3/840gkEk1qzJaCgoJIJBJNvk4rV66MBx98sEm/cePGRUTETTfd1KT9hhtuaPaYHTp0iIjI+HX6x89BKpWKWbNmRbt27eKoo45q9ngAALQ+VqQDALBH+sIXvhB33HFHlJSUxP777x9PPfVULFy4MLp3777De88+++y4//7749hjj41TTjklXnvttbjzzjvTq7ybY9iwYVFdXR1XXHFFDBkyJHr16tVk3/L6+vo46qij4pRTTomXX345brrppjj88MPj+OOPT/eprKyM22+/PVasWBEDBw6Mhx56KH7+85/Hl770pfjzn/8cf/7zn9N9O3XqFBMnTozi4uKorq6O008/Pf71X/81Tj311OjZs2e8/vrr8dBDD8WoUaO2Ccj/2XHHHRdjxoyJSy+9NFauXBkHHXRQ/P73v49f//rXMXXq1F36fOzIhAkT4rrrrotjjz02vvKVr8TatWvjxhtvjCFDhjR5ncOGDYsvfelLMXPmzHjvvffisMMOi8WLF6dXiu9olfk/Kioqiv333z/uvffe2GeffaJbt25x4IEHxoEHHhgREe3bt4/58+dHeXl5jBgxIh5++OF46KGH4pJLLomePXtm9xMAAECLJEgHAGCPdP3110dBQUHcdddd8cEHH8SoUaNi4cKF6ZXMmYwbNy6uvfbauO6662Lq1KkxfPjwmDdvXnz7299udh3Tpk2LVatWxTXXXBPr16+PI444okmQPmvWrLjrrrti2rRpsWXLljjttNPiJz/5ScYgeOtq8gceeCAeeOCBJtcGDBgQEydOjIiIr3zlK1FaWhpXXXVV/PCHP4y6urr4l3/5l/jsZz8bZ5555g5rb9OmTfzmN7+JadOmxb333huzZ8+OgQMHxg9/+MNd+lzsjCOPPDJuu+22uOqqq2Lq1KkxaNCguPrqq2PlypVNgvSIiJ///OfRp0+f+MUvfhFz586NsWPHxr333hv77rtvtG/fvlnj/uxnP4sLLrggvvWtb0V9fX1Mnz49HaQXFBTE/Pnz47zzzouLLrooOnfuHNOnT49p06Zl7XUDANCyJVL//PeyAAAAebJs2bI45JBD4s4774xJkybluxwAAIgIe6QDAAB5snnz5m3aZs6cGW3atInPfe5zeagIAAC2z9YuAAC0Su+8807GNy4tLCyMbt267caK8qOmpma7gfY/6tOnT07Gvuaaa2Lp0qUxZsyYaNu2bTz88MPx8MMPxznnnBNlZWXR0NCwwzdV7dSpU3Tq1Ckn9QEAwFa2dgEAoFUaOHBgrFq16iOvH3HEEbFo0aLdV1CenHHGGXH77bdn7JOrXxkeeeSRuOyyy+LFF1+MDRs2RP/+/eP000+PSy+9NNq2bRsrV66MQYMGZXzG9OnTY8aMGTmpDwAAthKkAwDQKj355JMZV2J37do1hg0bthsryo8XX3wx3nzzzYx9xo4du5uqaeqDDz6IJ554ImOfvfbaK/baa6/dVBEAAK2VIB0AAAAAADLY4/ZIb2xsjDfffDM6d+4ciUQi3+UAAAAAANACpVKpWL9+fZSWlkabNm0y9t3jgvQ333wzysrK8l0GAAAAAACtwOrVq6Nfv34Z++xxQXrnzp0j4u/FFxcX57kaAAAAAABaotra2igrK0tn0pnscUH61u1ciouLBekAAAAAAOTUzmwxnnnjl13w+OOPx3HHHRelpaWRSCTiwQcfzPYQAAAAAACw22Q9SN+4cWMcdNBBceONN2b70QAAAAAAsNtlfWuX8ePHx/jx47P9WAAAAAAAPqZUKhWbtzRERERRu4Kd2taEPWCP9Lq6uqirq0uf19bW5rEaAAAAAICWa/OWhth/2oKIiHjx8nHRoTDvEfEnQta3dmmuqqqqKCkpSR9lZWX5LgkAAAAAANLyHqRXVlZGTU1N+li9enW+SwIAAAAAgLS8r9tPJpORTCbzXQYAAAAAAGxX3lekAwAAAADAnizrK9I3bNgQy5cvT5+vWLEili1bFt26dYv+/ftnezgAAAAAAMiprAfpS5YsiTFjxqTPKyoqIiKivLw85syZk+3hAAAAAAAgp7IepI8ePTpSqVS2HwsAAAAAAHlhj3QAAAAAAMhAkA4AAAAAABkI0gEAAAAAIANBOgAAAAAAZCBIBwAAAACADATpAAAAAACQgSAdAAAAAAAyEKQDAAAAAEAGgnQAAAAAAMhAkA4AAAAAABkI0gEAAAAAIANBOgAAAAAAZCBIBwAAAACADATpAAAAAACQgSAdAAAAAAAyEKQDAAAAAEAGgnQAAAAAAMhAkA4AAAAAABkI0gEAAAAAIANBOgAAAAAAZCBIBwAAAACADATpAAAAAACQgSAdAAAAAAAyEKQDAAAAAEAGgnQAAAAAAMhAkA4AAAAAABkI0gEAAAAAIANBOgAAAAAAZCBIBwAAAACADATpAAAAAACQgSAdAAAAAAAyEKQDAAAAAEAGgnQAAAAAAMhAkA4AAAAAABkI0gEAAAAAIANBOgAAAAAAZCBIBwAAAACADATpAAAAAACQgSAdAAAAAAAyEKQDAAAAAEAGgnQAAAAAAMhAkA4AAAAAABkI0gEAAAAAIANBOgAAAAAAZCBIBwAAAACADATpAAAAAACQgSAdAAAAAAAyEKQDAAAAAEAGgnQAAAAAAMhAkA4AAAAAABkI0gEAAAAAIANBOgAAAAAAZCBIBwAAAACADATpAAAAAACQgSAdAAAAAAAyEKQDAAAAAEAGgnQAAAAAAMhAkA4AAAAAABkI0gEAAAAAIANBOgAAAAAAZCBIBwAAAACADATpAAAAAACQgSAdAAAAAAAyEKQDAAAAAEAGgnQAAAAAAMhAkA4AAAAAABkI0gEAAAAAIANBOgAAAAAAZCBIBwAAAACADATpAAAAAACQgSAdAAAAAAAyEKQDAAAAAEAGgnQAAAAAAMhAkA4AAAAAABkI0gEAAAAAIANBOgAAAAAAZCBIBwAAAACADATpAAAAAACQgSAdAAAAAAAyEKQDAAAAAEAGgnQAAAAAAMhAkA4AAAAAABkI0gEAAAAAIANBOgAAAAAAZCBIBwAAAACADATpAAAAAACQgSAdAAAAAAAyEKQDAAAAAEAGgnQAAAAAAMhAkA4AAAAAABkI0gEAAAAAIANBOgAAAAAAZCBIBwAAAACADATpAAAAAACQgSAdAAAAAAAyEKQDAAAAAEAGgnQAAAAAAMhAkA4AAAAAABkI0gEAAAAAIANBOgAAAAAAZCBIBwAAAACADATpAAAAAACQgSAdAAAAAAAyEKQDAAAAAEAGgnQAAAAAAMhAkA4AAAAAABkI0gEAAAAAIANBOgAAAAAAZCBIBwAAAACADATpAAAAAACQgSAdAAAAAAAyEKQDAAAAAEAGgnQAAAAAAMhAkA4AAAAAABkI0gEAAAAAIANBOgAAAAAAZCBIBwAAAACADATpAAAAAACQgSAdAAAAAAAyEKQDAAAAAEAGgnQAAAAAAMhAkA4AAAAAABkI0gEAAAAAIANBOgAAAAAAZJCzIP3GG2+MgQMHRvv27WPEiBHxpz/9KVdDAQAAAABAzuQkSL/33nujoqIipk+fHs8++2wcdNBBMW7cuFi7dm0uhgMAAAAAgJxpm4uHXnfddfH1r389zjzzzIiIuPnmm+Ohhx6K//qv/4qLL744F0O2KKlUKjZvach3GQAAAABAC7OpXu64K7IepNfX18fSpUujsrIy3damTZsYO3ZsPPXUU9v0r6uri7q6uvR5bW1ttkv6xNm8pSH2n7Yg32UAAAAAABA52Nrl3XffjYaGhujdu3eT9t69e8eaNWu26V9VVRUlJSXpo6ysLNslAQAAAADwD4YP6BpF7QryXcYnRk62dmmOysrKqKioSJ/X1ta2+jC9qF1BvHj5uHyXAQAAAAC0UEXtCiKRSOS7jE+MrAfpPXr0iIKCgnj77bebtL/99tvRp0+fbfonk8lIJpPZLuMTLZFIRIfCvP8fBwAAAAAAkYOtXQoLC2PYsGHx6KOPptsaGxvj0UcfjZEjR2Z7OAAAAAAAyKmcLHuuqKiI8vLyGD58eBx66KExc+bM2LhxY5x55pm5GA4AAAAAAHImJ0H6l7/85XjnnXdi2rRpsWbNmjj44INj/vz527wB6fakUqmI+Pte6QAAAAAAkAtbM+itmXQmidTO9NqN/va3v7X6NxsFAAAAAGD3WL16dfTr1y9jnz0uSG9sbIw333wzOnfu3KrfNba2tjbKyspi9erVUVxcnO9yIGfMdVoT853WwlyntTDXaU3Md1oLc53Wwlz/u1QqFevXr4/S0tJo0ybz24nmZGuXj6NNmzY7TP9bk+Li4lY9mWk9zHVaE/Od1sJcp7Uw12lNzHdaC3Od1sJcjygpKdmpfpljdgAAAAAAaOUE6QAAAAAAkIEgfQ+VTCZj+vTpkUwm810K5JS5TmtivtNamOu0FuY6rYn5TmthrtNamOvNt8e92SgAAAAAAOxJrEgHAAAAAIAMBOkAAAAAAJCBIB0AAAAAADIQpAMAAAAAQAaCdAAAAAAAyECQvoe68cYbY+DAgdG+ffsYMWJE/OlPf8p3SfCxPP7443HcccdFaWlpJBKJePDBB5tcT6VSMW3atOjbt28UFRXF2LFj49VXX81PsfAxVFVVxWc+85no3Llz9OrVKyZOnBgvv/xykz4ffPBBTJ48Obp37x6dOnWKL33pS/H222/nqWLYNdXV1TF06NAoLi6O4uLiGDlyZDz88MPp6+Y5LdVVV10ViUQipk6dmm4z32kpZsyYEYlEosmx3377pa+b67Qkb7zxRnz1q1+N7t27R1FRUXz605+OJUuWpK/7HZWWYuDAgdt8b08kEjF58uSI8L29OQTpe6B77703KioqYvr06fHss8/GQQcdFOPGjYu1a9fmuzTYZRs3boyDDjoobrzxxu1ev+aaa+InP/lJ3HzzzfHHP/4xOnbsGOPGjYsPPvhgN1cKH8/ixYtj8uTJ8fTTT8cjjzwSW7ZsiWOOOSY2btyY7vOtb30rfvvb38Z9990XixcvjjfffDNOPPHEPFYNzdevX7+46qqrYunSpbFkyZI48sgj44QTToi//OUvEWGe0zI988wzccstt8TQoUObtJvvtCQHHHBAvPXWW+njiSeeSF8z12kp3n///Rg1alS0a9cuHn744XjxxRfj2muvja5du6b7+B2VluKZZ55p8n39kUceiYiIk08+OSJ8b2+WFHucQw89NDV58uT0eUNDQ6q0tDRVVVWVx6ogeyIiNXfu3PR5Y2Njqk+fPqkf/vCH6bZ169alkslk6he/+EUeKoTsWbt2bSoiUosXL06lUn+f2+3atUvdd9996T7/3//3/6UiIvXUU0/lq0zIiq5du6Z+9rOfmee0SOvXr0/tvffeqUceeSR1xBFHpL75zW+mUinf12lZpk+fnjrooIO2e81cpyX5zne+kzr88MM/8rrfUWnJvvnNb6YGDx6camxs9L29maxI38PU19fH0qVLY+zYsem2Nm3axNixY+Opp57KY2WQOytWrIg1a9Y0mfclJSUxYsQI855PvJqamoiI6NatW0RELF26NLZs2dJkvu+3337Rv39/851PrIaGhrjnnnti48aNMXLkSPOcFmny5MkxYcKEJvM6wvd1Wp5XX301SktLY6+99opJkybF66+/HhHmOi3Lb37zmxg+fHicfPLJ0atXrzjkkEPipz/9afq631Fpqerr6+POO++Ms846KxKJhO/tzSRI38O8++670dDQEL17927S3rt371izZk2eqoLc2jq3zXtamsbGxpg6dWqMGjUqDjzwwIj4+3wvLCyMLl26NOlrvvNJ9Pzzz0enTp0imUzGueeeG3Pnzo3999/fPKfFueeee+LZZ5+Nqqqqba6Z77QkI0aMiDlz5sT8+fOjuro6VqxYEZ/97Gdj/fr15jotyl//+teorq6OvffeOxYsWBDnnXdeXHjhhXH77bdHhN9RabkefPDBWLduXZxxxhkR4eeY5mqb7wIAoKWaPHlyvPDCC032FoWWZN99941ly5ZFTU1N3H///VFeXh6LFy/Od1mQVatXr45vfvOb8cgjj0T79u3zXQ7k1Pjx49MfDx06NEaMGBEDBgyIX/7yl1FUVJTHyiC7GhsbY/jw4fGDH/wgIiIOOeSQeOGFF+Lmm2+O8vLyPFcHuXPbbbfF+PHjo7S0NN+lfCJZkb6H6dGjRxQUFGzz7rhvv/129OnTJ09VQW5tndvmPS3JlClTYt68efHYY49Fv3790u19+vSJ+vr6WLduXZP+5jufRIWFhTFkyJAYNmxYVFVVxUEHHRTXX3+9eU6LsnTp0li7dm3867/+a7Rt2zbatm0bixcvjp/85CfRtm3b6N27t/lOi9WlS5fYZ599Yvny5b6306L07ds39t9//yZtn/rUp9JbGfkdlZZo1apVsXDhwjj77LPTbb63N48gfQ9TWFgYw4YNi0cffTTd1tjYGI8++miMHDkyj5VB7gwaNCj69OnTZN7X1tbGH//4R/OeT5xUKhVTpkyJuXPnxn//93/HoEGDmlwfNmxYtGvXrsl8f/nll+P111833/nEa2xsjLq6OvOcFuWoo46K559/PpYtW5Y+hg8fHpMmTUp/bL7TUm3YsCFee+216Nu3r+/ttCijRo2Kl19+uUnbK6+8EgMGDIgIv6PSMs2ePTt69eoVEyZMSLf53t48tnbZA1VUVER5eXkMHz48Dj300Jg5c2Zs3LgxzjzzzHyXBrtsw4YNsXz58vT5ihUrYtmyZdGtW7fo379/TJ06Na644orYe++9Y9CgQfG9730vSktLY+LEifkrGnbB5MmT4+67745f//rX0blz5/S+ciUlJVFUVBQlJSXx7//+71FRURHdunWL4uLiuOCCC2LkyJFx2GGH5bl62HmVlZUxfvz46N+/f6xfvz7uvvvuWLRoUSxYsMA8p0Xp3Llz+n0uturYsWN079493W6+01L8x3/8Rxx33HExYMCAePPNN2P69OlRUFAQp512mu/ttCjf+ta34t/+7d/iBz/4QZxyyinxpz/9KW699da49dZbIyIikUj4HZUWpbGxMWbPnh3l5eXRtu3/i4N9b2+mFHukG264IdW/f/9UYWFh6tBDD009/fTT+S4JPpbHHnssFRHbHOXl5alUKpVqbGxMfe9730v17t07lUwmU0cddVTq5Zdfzm/RsAu2N88jIjV79ux0n82bN6fOP//8VNeuXVMdOnRIffGLX0y99dZb+SsadsFZZ52VGjBgQKqwsDDVs2fP1FFHHZX6/e9/n75untOSHXHEEalvfvOb6XPznZbiy1/+cqpv376pwsLC1L/8y7+kvvzlL6eWL1+evm6u05L89re/TR144IGpZDKZ2m+//VK33nprk+t+R6UlWbBgQSoitjuHfW/feYlUKpXKT4QPAAAAAAB7PnukAwAAAABABoJ0AAAAAADIQJAOAAAAAAAZCNIBAAAAACADQToAAAAAAGQgSAcAAAAAgAwE6QAAAAAAkIEgHQAAAAAAMhCkAwAAAABABoJ0AAAAAADIQJAOAAAAAAAZ/P+V+ZRAz7IBIQAAAABJRU5ErkJggg==\n"
+          },
+          "metadata": {}
+        }
+      ]
+    },
+    {
+      "cell_type": "markdown",
+      "metadata": {
+        "id": "98X6edTrm2xZ"
+      },
+      "source": [
+        "## 🍡 Treat #2: Yosys synthesis and circuit drawing\n",
+        "\n",
+        "[Yosys](https://yosyshq.net/yosys/) is a versatile tool to synthesize HDL designs to netlist and map them to the underlying technology target.\n",
+        "\n",
+        "This notebook shows how to synthesize a simple 1-bit adder Verilog design to different levels of technology abstraction (standard logic gates, CMOS, LUTs, discrete ICs) and draw the underlying circuit diagrams."
+      ]
+    },
+    {
+      "cell_type": "markdown",
+      "metadata": {
+        "id": "gnWAUQIppudM"
+      },
+      "source": [
+        "### Install packages\n",
+        "\n",
+        "Install packages from the `LiteX-Hub` and `SymbiFlow` channel."
+      ]
+    },
+    {
+      "cell_type": "code",
+      "metadata": {
+        "id": "rRvhEUG-ppJH",
+        "colab": {
+          "base_uri": "https://localhost:8080/"
+        },
+        "outputId": "a93735f7-5eb4-41d0-e263-f3f8bd0725a8"
+      },
+      "source": [
+        "!curl -O https://repo.anaconda.com/miniconda/Miniconda3-py37_4.10.3-Linux-x86_64.sh\n",
+        "!bash Miniconda3-py37_4.10.3-Linux-x86_64.sh -b -f -p miniconda-synth/\n",
+        "!miniconda-synth/bin/conda install --yes -c LiteX-Hub yosys\n",
+        "!miniconda-synth/bin/conda install --yes -c SymbiFlow verible"
+      ],
+      "execution_count": 34,
+      "outputs": [
+        {
+          "output_type": "stream",
+          "name": "stdout",
+          "text": [
+            "  % Total    % Received % Xferd  Average Speed   Time    Time     Time  Current\n",
+            "                                 Dload  Upload   Total   Spent    Left  Speed\n",
+            "100 84.9M  100 84.9M    0     0  88.3M      0 --:--:-- --:--:-- --:--:-- 88.3M\n",
+            "PREFIX=/content/miniconda-synth\n",
+            "Unpacking payload ...\n",
+            "Collecting package metadata (current_repodata.json): - \b\b\\ \b\bdone\n",
+            "Solving environment: / \b\b- \b\b\\ \b\bdone\n",
+            "\n",
+            "## Package Plan ##\n",
+            "\n",
+            "  environment location: /content/miniconda-synth\n",
+            "\n",
+            "  added / updated specs:\n",
+            "    - _libgcc_mutex==0.1=main\n",
+            "    - _openmp_mutex==4.5=1_gnu\n",
+            "    - brotlipy==0.7.0=py37h27cfd23_1003\n",
+            "    - ca-certificates==2021.7.5=h06a4308_1\n",
+            "    - certifi==2021.5.30=py37h06a4308_0\n",
+            "    - cffi==1.14.6=py37h400218f_0\n",
+            "    - chardet==4.0.0=py37h06a4308_1003\n",
+            "    - conda-package-handling==1.7.3=py37h27cfd23_1\n",
+            "    - conda==4.10.3=py37h06a4308_0\n",
+            "    - cryptography==3.4.7=py37hd23ed53_0\n",
+            "    - idna==2.10=pyhd3eb1b0_0\n",
+            "    - ld_impl_linux-64==2.35.1=h7274673_9\n",
+            "    - libffi==3.3=he6710b0_2\n",
+            "    - libgcc-ng==9.3.0=h5101ec6_17\n",
+            "    - libgomp==9.3.0=h5101ec6_17\n",
+            "    - libstdcxx-ng==9.3.0=hd4cf53a_17\n",
+            "    - ncurses==6.2=he6710b0_1\n",
+            "    - openssl==1.1.1k=h27cfd23_0\n",
+            "    - pip==21.1.3=py37h06a4308_0\n",
+            "    - pycosat==0.6.3=py37h27cfd23_0\n",
+            "    - pycparser==2.20=py_2\n",
+            "    - pyopenssl==20.0.1=pyhd3eb1b0_1\n",
+            "    - pysocks==1.7.1=py37_1\n",
+            "    - python==3.7.10=h12debd9_4\n",
+            "    - readline==8.1=h27cfd23_0\n",
+            "    - requests==2.25.1=pyhd3eb1b0_0\n",
+            "    - ruamel_yaml==0.15.100=py37h27cfd23_0\n",
+            "    - setuptools==52.0.0=py37h06a4308_0\n",
+            "    - six==1.16.0=pyhd3eb1b0_0\n",
+            "    - sqlite==3.36.0=hc218d9a_0\n",
+            "    - tk==8.6.10=hbc83047_0\n",
+            "    - tqdm==4.61.2=pyhd3eb1b0_1\n",
+            "    - urllib3==1.26.6=pyhd3eb1b0_1\n",
+            "    - wheel==0.36.2=pyhd3eb1b0_0\n",
+            "    - xz==5.2.5=h7b6447c_0\n",
+            "    - yaml==0.2.5=h7b6447c_0\n",
+            "    - zlib==1.2.11=h7b6447c_3\n",
+            "\n",
+            "\n",
+            "The following NEW packages will be INSTALLED:\n",
+            "\n",
+            "  _libgcc_mutex      pkgs/main/linux-64::_libgcc_mutex-0.1-main\n",
+            "  _openmp_mutex      pkgs/main/linux-64::_openmp_mutex-4.5-1_gnu\n",
+            "  brotlipy           pkgs/main/linux-64::brotlipy-0.7.0-py37h27cfd23_1003\n",
+            "  ca-certificates    pkgs/main/linux-64::ca-certificates-2021.7.5-h06a4308_1\n",
+            "  certifi            pkgs/main/linux-64::certifi-2021.5.30-py37h06a4308_0\n",
+            "  cffi               pkgs/main/linux-64::cffi-1.14.6-py37h400218f_0\n",
+            "  chardet            pkgs/main/linux-64::chardet-4.0.0-py37h06a4308_1003\n",
+            "  conda              pkgs/main/linux-64::conda-4.10.3-py37h06a4308_0\n",
+            "  conda-package-han~ pkgs/main/linux-64::conda-package-handling-1.7.3-py37h27cfd23_1\n",
+            "  cryptography       pkgs/main/linux-64::cryptography-3.4.7-py37hd23ed53_0\n",
+            "  idna               pkgs/main/noarch::idna-2.10-pyhd3eb1b0_0\n",
+            "  ld_impl_linux-64   pkgs/main/linux-64::ld_impl_linux-64-2.35.1-h7274673_9\n",
+            "  libffi             pkgs/main/linux-64::libffi-3.3-he6710b0_2\n",
+            "  libgcc-ng          pkgs/main/linux-64::libgcc-ng-9.3.0-h5101ec6_17\n",
+            "  libgomp            pkgs/main/linux-64::libgomp-9.3.0-h5101ec6_17\n",
+            "  libstdcxx-ng       pkgs/main/linux-64::libstdcxx-ng-9.3.0-hd4cf53a_17\n",
+            "  ncurses            pkgs/main/linux-64::ncurses-6.2-he6710b0_1\n",
+            "  openssl            pkgs/main/linux-64::openssl-1.1.1k-h27cfd23_0\n",
+            "  pip                pkgs/main/linux-64::pip-21.1.3-py37h06a4308_0\n",
+            "  pycosat            pkgs/main/linux-64::pycosat-0.6.3-py37h27cfd23_0\n",
+            "  pycparser          pkgs/main/noarch::pycparser-2.20-py_2\n",
+            "  pyopenssl          pkgs/main/noarch::pyopenssl-20.0.1-pyhd3eb1b0_1\n",
+            "  pysocks            pkgs/main/linux-64::pysocks-1.7.1-py37_1\n",
+            "  python             pkgs/main/linux-64::python-3.7.10-h12debd9_4\n",
+            "  readline           pkgs/main/linux-64::readline-8.1-h27cfd23_0\n",
+            "  requests           pkgs/main/noarch::requests-2.25.1-pyhd3eb1b0_0\n",
+            "  ruamel_yaml        pkgs/main/linux-64::ruamel_yaml-0.15.100-py37h27cfd23_0\n",
+            "  setuptools         pkgs/main/linux-64::setuptools-52.0.0-py37h06a4308_0\n",
+            "  six                pkgs/main/noarch::six-1.16.0-pyhd3eb1b0_0\n",
+            "  sqlite             pkgs/main/linux-64::sqlite-3.36.0-hc218d9a_0\n",
+            "  tk                 pkgs/main/linux-64::tk-8.6.10-hbc83047_0\n",
+            "  tqdm               pkgs/main/noarch::tqdm-4.61.2-pyhd3eb1b0_1\n",
+            "  urllib3            pkgs/main/noarch::urllib3-1.26.6-pyhd3eb1b0_1\n",
+            "  wheel              pkgs/main/noarch::wheel-0.36.2-pyhd3eb1b0_0\n",
+            "  xz                 pkgs/main/linux-64::xz-5.2.5-h7b6447c_0\n",
+            "  yaml               pkgs/main/linux-64::yaml-0.2.5-h7b6447c_0\n",
+            "  zlib               pkgs/main/linux-64::zlib-1.2.11-h7b6447c_3\n",
+            "\n",
+            "\n",
+            "Preparing transaction: / \b\b- \b\b\\ \b\b| \b\b/ \b\bdone\n",
+            "Executing transaction: \\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\bdone\n",
+            "installation finished.\n",
+            "WARNING:\n",
+            "    You currently have a PYTHONPATH environment variable set. This may cause\n",
+            "    unexpected behavior when running the Python interpreter in Miniconda3.\n",
+            "    For best results, please verify that your PYTHONPATH only points to\n",
+            "    directories of packages that are compatible with the Python interpreter\n",
+            "    in Miniconda3: /content/miniconda-synth\n",
+            "Collecting package metadata (current_repodata.json): - \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\bdone\n",
+            "Solving environment: - \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\bdone\n",
+            "\n",
+            "\n",
+            "==> WARNING: A newer version of conda exists. <==\n",
+            "  current version: 4.10.3\n",
+            "  latest version: 26.1.1\n",
+            "\n",
+            "Please update conda by running\n",
+            "\n",
+            "    $ conda update -n base -c defaults conda\n",
+            "\n",
+            "\n",
+            "\n",
+            "## Package Plan ##\n",
+            "\n",
+            "  environment location: /content/miniconda-synth\n",
+            "\n",
+            "  added / updated specs:\n",
+            "    - yosys\n",
+            "\n",
+            "\n",
+            "The following packages will be downloaded:\n",
+            "\n",
+            "    package                    |            build\n",
+            "    ---------------------------|-----------------\n",
+            "    ca-certificates-2025.12.2  |       h06a4308_0         125 KB\n",
+            "    openssl-1.1.1w             |       h7f8727e_0         3.7 MB\n",
+            "    yosys-0.13_39_g958c3a46a   |20220202_022309_py37        11.0 MB  LiteX-Hub\n",
+            "    ------------------------------------------------------------\n",
+            "                                           Total:        14.8 MB\n",
+            "\n",
+            "The following NEW packages will be INSTALLED:\n",
+            "\n",
+            "  yosys              LiteX-Hub/linux-64::yosys-0.13_39_g958c3a46a-20220202_022309_py37\n",
+            "\n",
+            "The following packages will be UPDATED:\n",
+            "\n",
+            "  ca-certificates                       2021.7.5-h06a4308_1 --> 2025.12.2-h06a4308_0\n",
+            "  openssl                                 1.1.1k-h27cfd23_0 --> 1.1.1w-h7f8727e_0\n",
+            "\n",
+            "\n",
+            "\n",
+            "Downloading and Extracting Packages\n",
+            "ca-certificates-2025 | 125 KB    | : 100% 1.0/1 [00:00<00:00,  3.23it/s]\n",
+            "yosys-0.13_39_g958c3 | 11.0 MB   | : 100% 1.0/1 [00:03<00:00,  3.73s/it]\n",
+            "openssl-1.1.1w       | 3.7 MB    | : 100% 1.0/1 [00:00<00:00,  1.77it/s]               \n",
+            "Preparing transaction: \\ \b\bdone\n",
+            "Verifying transaction: / \b\b- \b\b\\ \b\bdone\n",
+            "Executing transaction: / \b\bdone\n",
+            "Collecting package metadata (current_repodata.json): - \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\bdone\n",
+            "Solving environment: | \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\bdone\n",
+            "\n",
+            "\n",
+            "==> WARNING: A newer version of conda exists. <==\n",
+            "  current version: 4.10.3\n",
+            "  latest version: 26.1.1\n",
+            "\n",
+            "Please update conda by running\n",
+            "\n",
+            "    $ conda update -n base -c defaults conda\n",
+            "\n",
+            "\n",
+            "\n",
+            "## Package Plan ##\n",
+            "\n",
+            "  environment location: /content/miniconda-synth\n",
+            "\n",
+            "  added / updated specs:\n",
+            "    - verible\n",
+            "\n",
+            "\n",
+            "The following packages will be downloaded:\n",
+            "\n",
+            "    package                    |            build\n",
+            "    ---------------------------|-----------------\n",
+            "    verible-0.0.836_0000_g1b1294c|  20201231_075710         4.2 MB  SymbiFlow\n",
+            "    ------------------------------------------------------------\n",
+            "                                           Total:         4.2 MB\n",
+            "\n",
+            "The following NEW packages will be INSTALLED:\n",
+            "\n",
+            "  verible            SymbiFlow/linux-64::verible-0.0.836_0000_g1b1294c-20201231_075710\n",
+            "\n",
+            "\n",
+            "\n",
+            "Downloading and Extracting Packages\n",
+            "verible-0.0.836_0000 | 4.2 MB    | : 100% 1.0/1 [00:01<00:00,  1.32s/it]\n",
+            "Preparing transaction: - \b\bdone\n",
+            "Verifying transaction: | \b\bdone\n",
+            "Executing transaction: - \b\bdone\n"
+          ]
+        }
+      ]
+    },
+    {
+      "cell_type": "markdown",
+      "metadata": {
+        "id": "DvPIEL4LqP_1"
+      },
+      "source": [
+        "### Synth design\n",
+        "\n",
+        "Synthesize design netlist: map to a single `add` cell."
+      ]
+    },
+    {
+      "cell_type": "code",
+      "metadata": {
+        "id": "ItAxi-2Vqky7",
+        "colab": {
+          "base_uri": "https://localhost:8080/"
+        },
+        "outputId": "0906beee-ee91-4370-ed0a-569b9e288b24"
+      },
+      "source": [
+        "%%script miniconda-synth/bin/yosys -Q -T\n",
+        "\n",
+        "read -sv alu.v\n",
+        "hierarchy -top alu\n",
+        "\n",
+        "proc; opt\n",
+        "\n",
+        "opt_clean\n",
+        "show -format dot -prefix synth_design\n",
+        "stat"
+      ],
+      "execution_count": 36,
+      "outputs": [
+        {
+          "output_type": "stream",
+          "name": "stdout",
+          "text": [
+            "\n",
+            "yosys> \n",
+            "yosys> \n",
+            "\n",
+            "1. Executing Verilog-2005 frontend: alu.v\n",
+            "Parsing SystemVerilog input from `alu.v' to AST representation.\n",
+            "Storing AST representation for module `$abstract\\alu'.\n",
+            "Successfully finished Verilog frontend.\n",
+            "\n",
+            "yosys> \n",
+            "2. Executing HIERARCHY pass (managing design hierarchy).\n",
+            "\n",
+            "3. Executing AST frontend in derive mode using pre-parsed AST for module `\\alu'.\n",
+            "Generating RTLIL representation for module `\\alu'.\n",
+            "\n",
+            "3.1. Analyzing design hierarchy..\n",
+            "Top module:  \\alu\n",
+            "\n",
+            "3.2. Analyzing design hierarchy..\n",
+            "Top module:  \\alu\n",
+            "Removing unused module `$abstract\\alu'.\n",
+            "Removed 1 unused modules.\n",
+            "\n",
+            "yosys> \n",
+            "yosys> \n",
+            "4. Executing PROC pass (convert processes to netlists).\n",
+            "\n",
+            "4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).\n",
+            "Cleaned up 0 empty switches.\n",
+            "\n",
+            "4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).\n",
+            "Marked 2 switch rules as full_case in process $proc$alu.v:10$1 in module alu.\n",
+            "Removed a total of 0 dead cases.\n",
+            "\n",
+            "4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).\n",
+            "Removed 0 redundant assignments.\n",
+            "Promoted 2 assignments to connections.\n",
+            "\n",
+            "4.4. Executing PROC_INIT pass (extract init attributes).\n",
+            "\n",
+            "4.5. Executing PROC_ARST pass (detect async resets in processes).\n",
+            "\n",
+            "4.6. Executing PROC_MUX pass (convert decision trees to multiplexers).\n",
+            "Creating decoders for process `\\alu.$proc$alu.v:10$1'.\n",
+            "     1/2: $1\\zero_flag[0:0]\n",
+            "     2/2: $1\\result[3:0]\n",
+            "\n",
+            "4.7. Executing PROC_DLATCH pass (convert process syncs to latches).\n",
+            "No latch inferred for signal `\\alu.\\result' from process `\\alu.$proc$alu.v:10$1'.\n",
+            "No latch inferred for signal `\\alu.\\zero_flag' from process `\\alu.$proc$alu.v:10$1'.\n",
+            "\n",
+            "4.8. Executing PROC_DFF pass (convert process syncs to FFs).\n",
+            "\n",
+            "4.9. Executing PROC_MEMWR pass (convert process memory writes to cells).\n",
+            "\n",
+            "4.10. Executing PROC_CLEAN pass (remove empty switches from decision trees).\n",
+            "Found and cleaned up 2 empty switches in `\\alu.$proc$alu.v:10$1'.\n",
+            "Removing empty process `alu.$proc$alu.v:10$1'.\n",
+            "Cleaned up 2 empty switches.\n",
+            "\n",
+            "4.11. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module alu.\n",
+            "\n",
+            "5. Executing OPT pass (performing simple optimizations).\n",
+            "\n",
+            "5.1. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module alu.\n",
+            "\n",
+            "5.2. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\alu'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n",
+            "Running muxtree optimizer on module \\alu..\n",
+            "  Creating internal representation of mux trees.\n",
+            "  Evaluating internal representation of mux trees.\n",
+            "  Analyzing evaluation results.\n",
+            "Removed 0 multiplexer ports.\n",
+            "\n",
+            "5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n",
+            "  Optimizing cells in module \\alu.\n",
+            "Performed a total of 0 changes.\n",
+            "\n",
+            "5.5. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\alu'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "5.6. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "5.7. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\alu..\n",
+            "Removed 0 unused cells and 7 unused wires.\n",
+            "\n",
+            "5.8. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module alu.\n",
+            "\n",
+            "5.9. Rerunning OPT passes. (Maybe there is more to do..)\n",
+            "\n",
+            "5.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n",
+            "Running muxtree optimizer on module \\alu..\n",
+            "  Creating internal representation of mux trees.\n",
+            "  Evaluating internal representation of mux trees.\n",
+            "  Analyzing evaluation results.\n",
+            "Removed 0 multiplexer ports.\n",
+            "\n",
+            "5.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n",
+            "  Optimizing cells in module \\alu.\n",
+            "Performed a total of 0 changes.\n",
+            "\n",
+            "5.12. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\alu'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "5.13. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "5.14. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\alu..\n",
+            "\n",
+            "5.15. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module alu.\n",
+            "\n",
+            "5.16. Finished OPT passes. (There is nothing left to do.)\n",
+            "\n",
+            "yosys> \n",
+            "yosys> \n",
+            "6. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\alu..\n",
+            "\n",
+            "yosys> \n",
+            "7. Generating Graphviz representation of design.\n",
+            "Writing dot description to `synth_design.dot'.\n",
+            "Dumping module alu to page 1.\n",
+            "\n",
+            "yosys> \n",
+            "8. Printing statistics.\n",
+            "\n",
+            "=== alu ===\n",
+            "\n",
+            "   Number of wires:                 19\n",
+            "   Number of wire bits:             48\n",
+            "   Number of public wires:           5\n",
+            "   Number of public wire bits:      16\n",
+            "   Number of memories:               0\n",
+            "   Number of memory bits:            0\n",
+            "   Number of processes:              0\n",
+            "   Number of cells:                 16\n",
+            "     $add                            1\n",
+            "     $and                            1\n",
+            "     $eq                             6\n",
+            "     $logic_not                      2\n",
+            "     $mux                            1\n",
+            "     $not                            1\n",
+            "     $or                             1\n",
+            "     $pmux                           1\n",
+            "     $sub                            1\n",
+            "     $xor                            1\n",
+            "\n",
+            "\n",
+            "yosys> exit\n"
+          ]
+        }
+      ]
+    },
+    {
+      "cell_type": "code",
+      "metadata": {
+        "colab": {
+          "base_uri": "https://localhost:8080/",
+          "height": 1000
+        },
+        "id": "vHZ3rQJ6tHXM",
+        "outputId": "32a67f90-4ca1-458c-f1e5-06de874b0e04"
+      },
+      "source": [
+        "import graphviz\n",
+        "graphviz.Source.from_file('synth_design.dot')"
+      ],
+      "execution_count": 37,
+      "outputs": [
+        {
+          "output_type": "execute_result",
+          "data": {
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+            "text/plain": [
+              "<graphviz.sources.Source at 0x79c78acce360>"
+            ]
+          },
+          "metadata": {},
+          "execution_count": 37
+        }
+      ]
+    },
+    {
+      "cell_type": "markdown",
+      "metadata": {
+        "id": "k2TGPWtIup5J"
+      },
+      "source": [
+        "### Synth gates\n",
+        "\n",
+        "Synthesize gate netlist: map to built-in `XOR` and `AND` logic gates."
+      ]
+    },
+    {
+      "cell_type": "code",
+      "metadata": {
+        "id": "XJHob_xTup5V",
+        "colab": {
+          "base_uri": "https://localhost:8080/"
+        },
+        "outputId": "1a01aae0-9691-4aab-ef32-dcfafd63c93c"
+      },
+      "source": [
+        "%%script miniconda-synth/bin/yosys -Q -T\n",
+        "\n",
+        "read -sv alu.v\n",
+        "hierarchy -top alu\n",
+        "\n",
+        "proc; opt\n",
+        "techmap; opt\n",
+        "\n",
+        "opt_clean\n",
+        "show -format dot -prefix synth_gate\n",
+        "stat"
+      ],
+      "execution_count": 38,
+      "outputs": [
+        {
+          "output_type": "stream",
+          "name": "stdout",
+          "text": [
+            "\n",
+            "yosys> \n",
+            "yosys> \n",
+            "\n",
+            "1. Executing Verilog-2005 frontend: alu.v\n",
+            "Parsing SystemVerilog input from `alu.v' to AST representation.\n",
+            "Storing AST representation for module `$abstract\\alu'.\n",
+            "Successfully finished Verilog frontend.\n",
+            "\n",
+            "yosys> \n",
+            "2. Executing HIERARCHY pass (managing design hierarchy).\n",
+            "\n",
+            "3. Executing AST frontend in derive mode using pre-parsed AST for module `\\alu'.\n",
+            "Generating RTLIL representation for module `\\alu'.\n",
+            "\n",
+            "3.1. Analyzing design hierarchy..\n",
+            "Top module:  \\alu\n",
+            "\n",
+            "3.2. Analyzing design hierarchy..\n",
+            "Top module:  \\alu\n",
+            "Removing unused module `$abstract\\alu'.\n",
+            "Removed 1 unused modules.\n",
+            "\n",
+            "yosys> \n",
+            "yosys> \n",
+            "4. Executing PROC pass (convert processes to netlists).\n",
+            "\n",
+            "4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).\n",
+            "Cleaned up 0 empty switches.\n",
+            "\n",
+            "4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).\n",
+            "Marked 2 switch rules as full_case in process $proc$alu.v:10$1 in module alu.\n",
+            "Removed a total of 0 dead cases.\n",
+            "\n",
+            "4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).\n",
+            "Removed 0 redundant assignments.\n",
+            "Promoted 2 assignments to connections.\n",
+            "\n",
+            "4.4. Executing PROC_INIT pass (extract init attributes).\n",
+            "\n",
+            "4.5. Executing PROC_ARST pass (detect async resets in processes).\n",
+            "\n",
+            "4.6. Executing PROC_MUX pass (convert decision trees to multiplexers).\n",
+            "Creating decoders for process `\\alu.$proc$alu.v:10$1'.\n",
+            "     1/2: $1\\zero_flag[0:0]\n",
+            "     2/2: $1\\result[3:0]\n",
+            "\n",
+            "4.7. Executing PROC_DLATCH pass (convert process syncs to latches).\n",
+            "No latch inferred for signal `\\alu.\\result' from process `\\alu.$proc$alu.v:10$1'.\n",
+            "No latch inferred for signal `\\alu.\\zero_flag' from process `\\alu.$proc$alu.v:10$1'.\n",
+            "\n",
+            "4.8. Executing PROC_DFF pass (convert process syncs to FFs).\n",
+            "\n",
+            "4.9. Executing PROC_MEMWR pass (convert process memory writes to cells).\n",
+            "\n",
+            "4.10. Executing PROC_CLEAN pass (remove empty switches from decision trees).\n",
+            "Found and cleaned up 2 empty switches in `\\alu.$proc$alu.v:10$1'.\n",
+            "Removing empty process `alu.$proc$alu.v:10$1'.\n",
+            "Cleaned up 2 empty switches.\n",
+            "\n",
+            "4.11. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module alu.\n",
+            "\n",
+            "5. Executing OPT pass (performing simple optimizations).\n",
+            "\n",
+            "5.1. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module alu.\n",
+            "\n",
+            "5.2. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\alu'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n",
+            "Running muxtree optimizer on module \\alu..\n",
+            "  Creating internal representation of mux trees.\n",
+            "  Evaluating internal representation of mux trees.\n",
+            "  Analyzing evaluation results.\n",
+            "Removed 0 multiplexer ports.\n",
+            "\n",
+            "5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n",
+            "  Optimizing cells in module \\alu.\n",
+            "Performed a total of 0 changes.\n",
+            "\n",
+            "5.5. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\alu'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "5.6. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "5.7. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\alu..\n",
+            "Removed 0 unused cells and 7 unused wires.\n",
+            "\n",
+            "5.8. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module alu.\n",
+            "\n",
+            "5.9. Rerunning OPT passes. (Maybe there is more to do..)\n",
+            "\n",
+            "5.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n",
+            "Running muxtree optimizer on module \\alu..\n",
+            "  Creating internal representation of mux trees.\n",
+            "  Evaluating internal representation of mux trees.\n",
+            "  Analyzing evaluation results.\n",
+            "Removed 0 multiplexer ports.\n",
+            "\n",
+            "5.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n",
+            "  Optimizing cells in module \\alu.\n",
+            "Performed a total of 0 changes.\n",
+            "\n",
+            "5.12. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\alu'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "5.13. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "5.14. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\alu..\n",
+            "\n",
+            "5.15. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module alu.\n",
+            "\n",
+            "5.16. Finished OPT passes. (There is nothing left to do.)\n",
+            "\n",
+            "yosys> \n",
+            "6. Executing TECHMAP pass (map to technology primitives).\n",
+            "\n",
+            "6.1. Executing Verilog-2005 frontend: /content/miniconda-synth/bin/../share/yosys/techmap.v\n",
+            "Parsing Verilog input from `/content/miniconda-synth/bin/../share/yosys/techmap.v' to AST representation.\n",
+            "Generating RTLIL representation for module `\\_90_simplemap_bool_ops'.\n",
+            "Generating RTLIL representation for module `\\_90_simplemap_reduce_ops'.\n",
+            "Generating RTLIL representation for module `\\_90_simplemap_logic_ops'.\n",
+            "Generating RTLIL representation for module `\\_90_simplemap_compare_ops'.\n",
+            "Generating RTLIL representation for module `\\_90_simplemap_various'.\n",
+            "Generating RTLIL representation for module `\\_90_simplemap_registers'.\n",
+            "Generating RTLIL representation for module `\\_90_shift_ops_shr_shl_sshl_sshr'.\n",
+            "Generating RTLIL representation for module `\\_90_shift_shiftx'.\n",
+            "Generating RTLIL representation for module `\\_90_fa'.\n",
+            "Generating RTLIL representation for module `\\_90_lcu'.\n",
+            "Generating RTLIL representation for module `\\_90_alu'.\n",
+            "Generating RTLIL representation for module `\\_90_macc'.\n",
+            "Generating RTLIL representation for module `\\_90_alumacc'.\n",
+            "Generating RTLIL representation for module `\\$__div_mod_u'.\n",
+            "Generating RTLIL representation for module `\\$__div_mod_trunc'.\n",
+            "Generating RTLIL representation for module `\\_90_div'.\n",
+            "Generating RTLIL representation for module `\\_90_mod'.\n",
+            "Generating RTLIL representation for module `\\$__div_mod_floor'.\n",
+            "Generating RTLIL representation for module `\\_90_divfloor'.\n",
+            "Generating RTLIL representation for module `\\_90_modfloor'.\n",
+            "Generating RTLIL representation for module `\\_90_pow'.\n",
+            "Generating RTLIL representation for module `\\_90_pmux'.\n",
+            "Generating RTLIL representation for module `\\_90_demux'.\n",
+            "Generating RTLIL representation for module `\\_90_lut'.\n",
+            "Successfully finished Verilog frontend.\n",
+            "\n",
+            "6.2. Continuing TECHMAP pass.\n",
+            "Running \"alumacc\" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=4:B_SIGNED=0:B_WIDTH=4:Y_WIDTH=4:394426c56d1a028ba8fdd5469b163e04011def47.\n",
+            "Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=4:B_SIGNED=0:B_WIDTH=4:Y_WIDTH=4:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=4:B_SIGNED=0:B_WIDTH=4:Y_WIDTH=4:394426c56d1a028ba8fdd5469b163e04011def47.\n",
+            "Running \"alumacc\" on wrapper $extern:wrap:$sub:A_SIGNED=0:A_WIDTH=4:B_SIGNED=0:B_WIDTH=4:Y_WIDTH=4:394426c56d1a028ba8fdd5469b163e04011def47.\n",
+            "Using template $extern:wrap:$sub:A_SIGNED=0:A_WIDTH=4:B_SIGNED=0:B_WIDTH=4:Y_WIDTH=4:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:A_SIGNED=0:A_WIDTH=4:B_SIGNED=0:B_WIDTH=4:Y_WIDTH=4:394426c56d1a028ba8fdd5469b163e04011def47.\n",
+            "Using extmapper simplemap for cells of type $and.\n",
+            "Using extmapper simplemap for cells of type $or.\n",
+            "Using extmapper simplemap for cells of type $xor.\n",
+            "Using extmapper simplemap for cells of type $not.\n",
+            "Using extmapper simplemap for cells of type $logic_not.\n",
+            "Using extmapper simplemap for cells of type $mux.\n",
+            "Using extmapper simplemap for cells of type $eq.\n",
+            "Using template $paramod$33afdd83bf3811dac2de7a968d39eea5718691bc\\_90_pmux for cells of type $pmux.\n",
+            "Using template $paramod$740b056ede97228d3eae64ea2fdc81f0a33e0fe7\\_90_alu for cells of type $alu.\n",
+            "Using extmapper simplemap for cells of type $reduce_or.\n",
+            "Using template $paramod\\_90_lcu\\WIDTH=32'00000000000000000000000000000100 for cells of type $lcu.\n",
+            "Using extmapper simplemap for cells of type $pos.\n",
+            "No more expansions possible.\n",
+            "\n",
+            "7. Executing OPT pass (performing simple optimizations).\n",
+            "\n",
+            "7.1. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module alu.\n",
+            "\n",
+            "7.2. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\alu'.\n",
+            "Removed a total of 22 cells.\n",
+            "\n",
+            "7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n",
+            "Running muxtree optimizer on module \\alu..\n",
+            "  Creating internal representation of mux trees.\n",
+            "  No muxes found in this module.\n",
+            "Removed 0 multiplexer ports.\n",
+            "\n",
+            "7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n",
+            "  Optimizing cells in module \\alu.\n",
+            "Performed a total of 0 changes.\n",
+            "\n",
+            "7.5. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\alu'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "7.6. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "7.7. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\alu..\n",
+            "Removed 11 unused cells and 124 unused wires.\n",
+            "\n",
+            "7.8. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module alu.\n",
+            "\n",
+            "7.9. Rerunning OPT passes. (Maybe there is more to do..)\n",
+            "\n",
+            "7.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n",
+            "Running muxtree optimizer on module \\alu..\n",
+            "  Creating internal representation of mux trees.\n",
+            "  No muxes found in this module.\n",
+            "Removed 0 multiplexer ports.\n",
+            "\n",
+            "7.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n",
+            "  Optimizing cells in module \\alu.\n",
+            "Performed a total of 0 changes.\n",
+            "\n",
+            "7.12. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\alu'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "7.13. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "7.14. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\alu..\n",
+            "\n",
+            "7.15. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module alu.\n",
+            "\n",
+            "7.16. Finished OPT passes. (There is nothing left to do.)\n",
+            "\n",
+            "yosys> \n",
+            "yosys> \n",
+            "8. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\alu..\n",
+            "\n",
+            "yosys> \n",
+            "9. Generating Graphviz representation of design.\n",
+            "Writing dot description to `synth_gate.dot'.\n",
+            "Dumping module alu to page 1.\n",
+            "\n",
+            "yosys> \n",
+            "10. Printing statistics.\n",
+            "\n",
+            "=== alu ===\n",
+            "\n",
+            "   Number of wires:                 45\n",
+            "   Number of wire bits:            150\n",
+            "   Number of public wires:           5\n",
+            "   Number of public wire bits:      16\n",
+            "   Number of memories:               0\n",
+            "   Number of memory bits:            0\n",
+            "   Number of processes:              0\n",
+            "   Number of cells:                130\n",
+            "     $_AND_                         39\n",
+            "     $_MUX_                          4\n",
+            "     $_NOT_                         20\n",
+            "     $_OR_                          53\n",
+            "     $_XOR_                         14\n",
+            "\n",
+            "\n",
+            "yosys> exit\n"
+          ]
+        }
+      ]
+    },
+    {
+      "cell_type": "code",
+      "metadata": {
+        "colab": {
+          "base_uri": "https://localhost:8080/",
+          "height": 1000
+        },
+        "id": "O0OKruObup5W",
+        "outputId": "45229ac7-bf0b-452e-c4b5-a28d77f15d50"
+      },
+      "source": [
+        "import graphviz\n",
+        "graphviz.Source.from_file('synth_gate.dot')"
+      ],
+      "execution_count": 39,
+      "outputs": [
+        {
+          "output_type": "execute_result",
+          "data": {
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+            "text/plain": [
+              "<graphviz.sources.Source at 0x79c788973fe0>"
+            ]
+          },
+          "metadata": {},
+          "execution_count": 39
+        }
+      ]
+    },
+    {
+      "cell_type": "markdown",
+      "metadata": {
+        "id": "JbSxNNLGzIKz"
+      },
+      "source": [
+        "### Synth FPGA\n",
+        "\n",
+        "Synthesize FPGA netlist: map to `IC40` `LUT` gates using a builtin synthesis script."
+      ]
+    },
+    {
+      "cell_type": "code",
+      "metadata": {
+        "id": "WO4xtQYmzIK-",
+        "colab": {
+          "base_uri": "https://localhost:8080/"
+        },
+        "outputId": "77d1c6f4-b5bc-42cd-febd-a1024102013c"
+      },
+      "source": [
+        "%%script miniconda-synth/bin/yosys -Q -T\n",
+        "\n",
+        "read -sv alu.v\n",
+        "hierarchy -top alu\n",
+        "\n",
+        "synth_ice40\n",
+        "\n",
+        "opt_clean\n",
+        "show -format dot -prefix synth_ice40"
+      ],
+      "execution_count": 40,
+      "outputs": [
+        {
+          "output_type": "stream",
+          "name": "stdout",
+          "text": [
+            "\n",
+            "yosys> \n",
+            "yosys> \n",
+            "\n",
+            "1. Executing Verilog-2005 frontend: alu.v\n",
+            "Parsing SystemVerilog input from `alu.v' to AST representation.\n",
+            "Storing AST representation for module `$abstract\\alu'.\n",
+            "Successfully finished Verilog frontend.\n",
+            "\n",
+            "yosys> \n",
+            "2. Executing HIERARCHY pass (managing design hierarchy).\n",
+            "\n",
+            "3. Executing AST frontend in derive mode using pre-parsed AST for module `\\alu'.\n",
+            "Generating RTLIL representation for module `\\alu'.\n",
+            "\n",
+            "3.1. Analyzing design hierarchy..\n",
+            "Top module:  \\alu\n",
+            "\n",
+            "3.2. Analyzing design hierarchy..\n",
+            "Top module:  \\alu\n",
+            "Removing unused module `$abstract\\alu'.\n",
+            "Removed 1 unused modules.\n",
+            "\n",
+            "yosys> \n",
+            "yosys> \n",
+            "4. Executing SYNTH_ICE40 pass.\n",
+            "\n",
+            "4.1. Executing Verilog-2005 frontend: /content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v\n",
+            "Parsing Verilog input from `/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v' to AST representation.\n",
+            "Generating RTLIL representation for module `\\SB_IO'.\n",
+            "Generating RTLIL representation for module `\\SB_GB_IO'.\n",
+            "Generating RTLIL representation for module `\\SB_GB'.\n",
+            "Generating RTLIL representation for module `\\SB_LUT4'.\n",
+            "Generating RTLIL representation for module `\\SB_CARRY'.\n",
+            "Generating RTLIL representation for module `\\SB_DFF'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFE'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFSR'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFR'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFSS'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFS'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFESR'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFER'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFESS'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFES'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFN'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFNE'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFNSR'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFNR'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFNSS'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFNS'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFNESR'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFNER'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFNESS'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFNES'.\n",
+            "Generating RTLIL representation for module `\\SB_RAM40_4K'.\n",
+            "Generating RTLIL representation for module `\\SB_RAM40_4KNR'.\n",
+            "Generating RTLIL representation for module `\\SB_RAM40_4KNW'.\n",
+            "Generating RTLIL representation for module `\\SB_RAM40_4KNRNW'.\n",
+            "Generating RTLIL representation for module `\\ICESTORM_LC'.\n",
+            "Generating RTLIL representation for module `\\SB_PLL40_CORE'.\n",
+            "Generating RTLIL representation for module `\\SB_PLL40_PAD'.\n",
+            "Generating RTLIL representation for module `\\SB_PLL40_2_PAD'.\n",
+            "Generating RTLIL representation for module `\\SB_PLL40_2F_CORE'.\n",
+            "Generating RTLIL representation for module `\\SB_PLL40_2F_PAD'.\n",
+            "Generating RTLIL representation for module `\\SB_WARMBOOT'.\n",
+            "Generating RTLIL representation for module `\\SB_SPRAM256KA'.\n",
+            "Generating RTLIL representation for module `\\SB_HFOSC'.\n",
+            "Generating RTLIL representation for module `\\SB_LFOSC'.\n",
+            "Generating RTLIL representation for module `\\SB_RGBA_DRV'.\n",
+            "Generating RTLIL representation for module `\\SB_LED_DRV_CUR'.\n",
+            "Generating RTLIL representation for module `\\SB_RGB_DRV'.\n",
+            "Generating RTLIL representation for module `\\SB_I2C'.\n",
+            "Generating RTLIL representation for module `\\SB_SPI'.\n",
+            "Generating RTLIL representation for module `\\SB_LEDDA_IP'.\n",
+            "Generating RTLIL representation for module `\\SB_FILTER_50NS'.\n",
+            "Generating RTLIL representation for module `\\SB_IO_I3C'.\n",
+            "Generating RTLIL representation for module `\\SB_IO_OD'.\n",
+            "Generating RTLIL representation for module `\\SB_MAC16'.\n",
+            "Generating RTLIL representation for module `\\ICESTORM_RAM'.\n",
+            "Successfully finished Verilog frontend.\n",
+            "\n",
+            "4.2. Executing HIERARCHY pass (managing design hierarchy).\n",
+            "\n",
+            "4.2.1. Analyzing design hierarchy..\n",
+            "Top module:  \\alu\n",
+            "\n",
+            "4.2.2. Analyzing design hierarchy..\n",
+            "Top module:  \\alu\n",
+            "Removed 0 unused modules.\n",
+            "\n",
+            "4.3. Executing PROC pass (convert processes to netlists).\n",
+            "\n",
+            "4.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).\n",
+            "Cleaned up 0 empty switches.\n",
+            "\n",
+            "4.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:1386$249 in module SB_DFFNES.\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:1328$242 in module SB_DFFNESS.\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:1251$238 in module SB_DFFNER.\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:1193$231 in module SB_DFFNESR.\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:1122$228 in module SB_DFFNS.\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:1072$225 in module SB_DFFNSS.\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:1001$222 in module SB_DFFNR.\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:951$219 in module SB_DFFNSR.\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:789$211 in module SB_DFFES.\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:731$204 in module SB_DFFESS.\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:654$200 in module SB_DFFER.\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:596$193 in module SB_DFFESR.\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:525$190 in module SB_DFFS.\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:475$187 in module SB_DFFSS.\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:404$184 in module SB_DFFR.\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:354$181 in module SB_DFFSR.\n",
+            "Marked 2 switch rules as full_case in process $proc$alu.v:10$1 in module alu.\n",
+            "Removed a total of 0 dead cases.\n",
+            "\n",
+            "4.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).\n",
+            "Removed 8 redundant assignments.\n",
+            "Promoted 24 assignments to connections.\n",
+            "\n",
+            "4.3.4. Executing PROC_INIT pass (extract init attributes).\n",
+            "Found init rule in `\\SB_DFFNES.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$252'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFNESS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$248'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFNER.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$241'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFNESR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$237'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFNS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$230'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFNSS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$227'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFNR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$224'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFNSR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$221'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFNE.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$218'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFN.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$216'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFES.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$214'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFESS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$210'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFER.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$203'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFESR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$199'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$192'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFSS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$189'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$186'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFSR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$183'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFE.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$180'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFF.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$178'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "\n",
+            "4.3.5. Executing PROC_ARST pass (detect async resets in processes).\n",
+            "Found async reset \\S in `\\SB_DFFNES.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:1386$249'.\n",
+            "Found async reset \\R in `\\SB_DFFNER.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:1251$238'.\n",
+            "Found async reset \\S in `\\SB_DFFNS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:1122$228'.\n",
+            "Found async reset \\R in `\\SB_DFFNR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:1001$222'.\n",
+            "Found async reset \\S in `\\SB_DFFES.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:789$211'.\n",
+            "Found async reset \\R in `\\SB_DFFER.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:654$200'.\n",
+            "Found async reset \\S in `\\SB_DFFS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:525$190'.\n",
+            "Found async reset \\R in `\\SB_DFFR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:404$184'.\n",
+            "\n",
+            "4.3.6. Executing PROC_MUX pass (convert decision trees to multiplexers).\n",
+            "Creating decoders for process `\\SB_DFFNES.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$252'.\n",
+            "Creating decoders for process `\\SB_DFFNES.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:1386$249'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFNESS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$248'.\n",
+            "Creating decoders for process `\\SB_DFFNESS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:1328$242'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFNER.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$241'.\n",
+            "Creating decoders for process `\\SB_DFFNER.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:1251$238'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFNESR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$237'.\n",
+            "Creating decoders for process `\\SB_DFFNESR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:1193$231'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFNS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$230'.\n",
+            "Creating decoders for process `\\SB_DFFNS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:1122$228'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFNSS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$227'.\n",
+            "Creating decoders for process `\\SB_DFFNSS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:1072$225'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFNR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$224'.\n",
+            "Creating decoders for process `\\SB_DFFNR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:1001$222'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFNSR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$221'.\n",
+            "Creating decoders for process `\\SB_DFFNSR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:951$219'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFNE.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$218'.\n",
+            "Creating decoders for process `\\SB_DFFNE.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:906$217'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFN.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$216'.\n",
+            "Creating decoders for process `\\SB_DFFN.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:868$215'.\n",
+            "Creating decoders for process `\\SB_DFFES.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$214'.\n",
+            "Creating decoders for process `\\SB_DFFES.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:789$211'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFESS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$210'.\n",
+            "Creating decoders for process `\\SB_DFFESS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:731$204'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFER.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$203'.\n",
+            "Creating decoders for process `\\SB_DFFER.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:654$200'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFESR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$199'.\n",
+            "Creating decoders for process `\\SB_DFFESR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:596$193'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$192'.\n",
+            "Creating decoders for process `\\SB_DFFS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:525$190'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFSS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$189'.\n",
+            "Creating decoders for process `\\SB_DFFSS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:475$187'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$186'.\n",
+            "Creating decoders for process `\\SB_DFFR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:404$184'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFSR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$183'.\n",
+            "Creating decoders for process `\\SB_DFFSR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:354$181'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFE.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$180'.\n",
+            "Creating decoders for process `\\SB_DFFE.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:309$179'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFF.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$178'.\n",
+            "Creating decoders for process `\\SB_DFF.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:271$177'.\n",
+            "Creating decoders for process `\\alu.$proc$alu.v:10$1'.\n",
+            "     1/2: $1\\zero_flag[0:0]\n",
+            "     2/2: $1\\result[3:0]\n",
+            "\n",
+            "4.3.7. Executing PROC_DLATCH pass (convert process syncs to latches).\n",
+            "No latch inferred for signal `\\alu.\\result' from process `\\alu.$proc$alu.v:10$1'.\n",
+            "No latch inferred for signal `\\alu.\\zero_flag' from process `\\alu.$proc$alu.v:10$1'.\n",
+            "\n",
+            "4.3.8. Executing PROC_DFF pass (convert process syncs to FFs).\n",
+            "Creating register for signal `\\SB_DFFNES.\\Q' using process `\\SB_DFFNES.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:1386$249'.\n",
+            "  created $adff cell `$procdff$445' with negative edge clock and positive level reset.\n",
+            "Creating register for signal `\\SB_DFFNESS.\\Q' using process `\\SB_DFFNESS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:1328$242'.\n",
+            "  created $dff cell `$procdff$446' with negative edge clock.\n",
+            "Creating register for signal `\\SB_DFFNER.\\Q' using process `\\SB_DFFNER.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:1251$238'.\n",
+            "  created $adff cell `$procdff$447' with negative edge clock and positive level reset.\n",
+            "Creating register for signal `\\SB_DFFNESR.\\Q' using process `\\SB_DFFNESR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:1193$231'.\n",
+            "  created $dff cell `$procdff$448' with negative edge clock.\n",
+            "Creating register for signal `\\SB_DFFNS.\\Q' using process `\\SB_DFFNS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:1122$228'.\n",
+            "  created $adff cell `$procdff$449' with negative edge clock and positive level reset.\n",
+            "Creating register for signal `\\SB_DFFNSS.\\Q' using process `\\SB_DFFNSS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:1072$225'.\n",
+            "  created $dff cell `$procdff$450' with negative edge clock.\n",
+            "Creating register for signal `\\SB_DFFNR.\\Q' using process `\\SB_DFFNR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:1001$222'.\n",
+            "  created $adff cell `$procdff$451' with negative edge clock and positive level reset.\n",
+            "Creating register for signal `\\SB_DFFNSR.\\Q' using process `\\SB_DFFNSR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:951$219'.\n",
+            "  created $dff cell `$procdff$452' with negative edge clock.\n",
+            "Creating register for signal `\\SB_DFFNE.\\Q' using process `\\SB_DFFNE.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:906$217'.\n",
+            "  created $dff cell `$procdff$453' with negative edge clock.\n",
+            "Creating register for signal `\\SB_DFFN.\\Q' using process `\\SB_DFFN.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:868$215'.\n",
+            "  created $dff cell `$procdff$454' with negative edge clock.\n",
+            "Creating register for signal `\\SB_DFFES.\\Q' using process `\\SB_DFFES.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:789$211'.\n",
+            "  created $adff cell `$procdff$455' with positive edge clock and positive level reset.\n",
+            "Creating register for signal `\\SB_DFFESS.\\Q' using process `\\SB_DFFESS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:731$204'.\n",
+            "  created $dff cell `$procdff$456' with positive edge clock.\n",
+            "Creating register for signal `\\SB_DFFER.\\Q' using process `\\SB_DFFER.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:654$200'.\n",
+            "  created $adff cell `$procdff$457' with positive edge clock and positive level reset.\n",
+            "Creating register for signal `\\SB_DFFESR.\\Q' using process `\\SB_DFFESR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:596$193'.\n",
+            "  created $dff cell `$procdff$458' with positive edge clock.\n",
+            "Creating register for signal `\\SB_DFFS.\\Q' using process `\\SB_DFFS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:525$190'.\n",
+            "  created $adff cell `$procdff$459' with positive edge clock and positive level reset.\n",
+            "Creating register for signal `\\SB_DFFSS.\\Q' using process `\\SB_DFFSS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:475$187'.\n",
+            "  created $dff cell `$procdff$460' with positive edge clock.\n",
+            "Creating register for signal `\\SB_DFFR.\\Q' using process `\\SB_DFFR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:404$184'.\n",
+            "  created $adff cell `$procdff$461' with positive edge clock and positive level reset.\n",
+            "Creating register for signal `\\SB_DFFSR.\\Q' using process `\\SB_DFFSR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:354$181'.\n",
+            "  created $dff cell `$procdff$462' with positive edge clock.\n",
+            "Creating register for signal `\\SB_DFFE.\\Q' using process `\\SB_DFFE.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:309$179'.\n",
+            "  created $dff cell `$procdff$463' with positive edge clock.\n",
+            "Creating register for signal `\\SB_DFF.\\Q' using process `\\SB_DFF.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:271$177'.\n",
+            "  created $dff cell `$procdff$464' with positive edge clock.\n",
+            "\n",
+            "4.3.9. Executing PROC_MEMWR pass (convert process memory writes to cells).\n",
+            "\n",
+            "4.3.10. Executing PROC_CLEAN pass (remove empty switches from decision trees).\n",
+            "Removing empty process `SB_DFFNES.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$252'.\n",
+            "Found and cleaned up 1 empty switch in `\\SB_DFFNES.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:1386$249'.\n",
+            "Removing empty process `SB_DFFNES.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:1386$249'.\n",
+            "Removing empty process `SB_DFFNESS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$248'.\n",
+            "Found and cleaned up 2 empty switches in `\\SB_DFFNESS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:1328$242'.\n",
+            "Removing empty process `SB_DFFNESS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:1328$242'.\n",
+            "Removing empty process `SB_DFFNER.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$241'.\n",
+            "Found and cleaned up 1 empty switch in `\\SB_DFFNER.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:1251$238'.\n",
+            "Removing empty process `SB_DFFNER.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:1251$238'.\n",
+            "Removing empty process `SB_DFFNESR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$237'.\n",
+            "Found and cleaned up 2 empty switches in `\\SB_DFFNESR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:1193$231'.\n",
+            "Removing empty process `SB_DFFNESR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:1193$231'.\n",
+            "Removing empty process `SB_DFFNS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$230'.\n",
+            "Removing empty process `SB_DFFNS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:1122$228'.\n",
+            "Removing empty process `SB_DFFNSS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$227'.\n",
+            "Found and cleaned up 1 empty switch in `\\SB_DFFNSS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:1072$225'.\n",
+            "Removing empty process `SB_DFFNSS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:1072$225'.\n",
+            "Removing empty process `SB_DFFNR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$224'.\n",
+            "Removing empty process `SB_DFFNR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:1001$222'.\n",
+            "Removing empty process `SB_DFFNSR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$221'.\n",
+            "Found and cleaned up 1 empty switch in `\\SB_DFFNSR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:951$219'.\n",
+            "Removing empty process `SB_DFFNSR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:951$219'.\n",
+            "Removing empty process `SB_DFFNE.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$218'.\n",
+            "Found and cleaned up 1 empty switch in `\\SB_DFFNE.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:906$217'.\n",
+            "Removing empty process `SB_DFFNE.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:906$217'.\n",
+            "Removing empty process `SB_DFFN.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$216'.\n",
+            "Removing empty process `SB_DFFN.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:868$215'.\n",
+            "Removing empty process `SB_DFFES.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$214'.\n",
+            "Found and cleaned up 1 empty switch in `\\SB_DFFES.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:789$211'.\n",
+            "Removing empty process `SB_DFFES.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:789$211'.\n",
+            "Removing empty process `SB_DFFESS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$210'.\n",
+            "Found and cleaned up 2 empty switches in `\\SB_DFFESS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:731$204'.\n",
+            "Removing empty process `SB_DFFESS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:731$204'.\n",
+            "Removing empty process `SB_DFFER.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$203'.\n",
+            "Found and cleaned up 1 empty switch in `\\SB_DFFER.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:654$200'.\n",
+            "Removing empty process `SB_DFFER.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:654$200'.\n",
+            "Removing empty process `SB_DFFESR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$199'.\n",
+            "Found and cleaned up 2 empty switches in `\\SB_DFFESR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:596$193'.\n",
+            "Removing empty process `SB_DFFESR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:596$193'.\n",
+            "Removing empty process `SB_DFFS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$192'.\n",
+            "Removing empty process `SB_DFFS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:525$190'.\n",
+            "Removing empty process `SB_DFFSS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$189'.\n",
+            "Found and cleaned up 1 empty switch in `\\SB_DFFSS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:475$187'.\n",
+            "Removing empty process `SB_DFFSS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:475$187'.\n",
+            "Removing empty process `SB_DFFR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$186'.\n",
+            "Removing empty process `SB_DFFR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:404$184'.\n",
+            "Removing empty process `SB_DFFSR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$183'.\n",
+            "Found and cleaned up 1 empty switch in `\\SB_DFFSR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:354$181'.\n",
+            "Removing empty process `SB_DFFSR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:354$181'.\n",
+            "Removing empty process `SB_DFFE.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$180'.\n",
+            "Found and cleaned up 1 empty switch in `\\SB_DFFE.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:309$179'.\n",
+            "Removing empty process `SB_DFFE.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:309$179'.\n",
+            "Removing empty process `SB_DFF.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$178'.\n",
+            "Removing empty process `SB_DFF.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:271$177'.\n",
+            "Found and cleaned up 2 empty switches in `\\alu.$proc$alu.v:10$1'.\n",
+            "Removing empty process `alu.$proc$alu.v:10$1'.\n",
+            "Cleaned up 20 empty switches.\n",
+            "\n",
+            "4.3.11. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module alu.\n",
+            "\n",
+            "4.4. Executing FLATTEN pass (flatten design).\n",
+            "\n",
+            "4.5. Executing TRIBUF pass.\n",
+            "\n",
+            "4.6. Executing DEMINOUT pass (demote inout ports to input or output).\n",
+            "\n",
+            "4.7. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module alu.\n",
+            "\n",
+            "4.8. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\alu..\n",
+            "Removed 0 unused cells and 7 unused wires.\n",
+            "\n",
+            "4.9. Executing CHECK pass (checking for obvious problems).\n",
+            "Checking module alu...\n",
+            "Found and reported 0 problems.\n",
+            "\n",
+            "4.10. Executing OPT pass (performing simple optimizations).\n",
+            "\n",
+            "4.10.1. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module alu.\n",
+            "\n",
+            "4.10.2. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\alu'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "4.10.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n",
+            "Running muxtree optimizer on module \\alu..\n",
+            "  Creating internal representation of mux trees.\n",
+            "  Evaluating internal representation of mux trees.\n",
+            "  Analyzing evaluation results.\n",
+            "Removed 0 multiplexer ports.\n",
+            "\n",
+            "4.10.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n",
+            "  Optimizing cells in module \\alu.\n",
+            "Performed a total of 0 changes.\n",
+            "\n",
+            "4.10.5. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\alu'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "4.10.6. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "4.10.7. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\alu..\n",
+            "\n",
+            "4.10.8. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module alu.\n",
+            "\n",
+            "4.10.9. Finished OPT passes. (There is nothing left to do.)\n",
+            "\n",
+            "4.11. Executing FSM pass (extract and optimize FSM).\n",
+            "\n",
+            "4.11.1. Executing FSM_DETECT pass (finding FSMs in design).\n",
+            "\n",
+            "4.11.2. Executing FSM_EXTRACT pass (extracting FSM from design).\n",
+            "\n",
+            "4.11.3. Executing FSM_OPT pass (simple optimizations of FSMs).\n",
+            "\n",
+            "4.11.4. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\alu..\n",
+            "\n",
+            "4.11.5. Executing FSM_OPT pass (simple optimizations of FSMs).\n",
+            "\n",
+            "4.11.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).\n",
+            "\n",
+            "4.11.7. Executing FSM_INFO pass (dumping all available information on FSM cells).\n",
+            "\n",
+            "4.11.8. Executing FSM_MAP pass (mapping FSMs to basic logic).\n",
+            "\n",
+            "4.12. Executing OPT pass (performing simple optimizations).\n",
+            "\n",
+            "4.12.1. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module alu.\n",
+            "\n",
+            "4.12.2. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\alu'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "4.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n",
+            "Running muxtree optimizer on module \\alu..\n",
+            "  Creating internal representation of mux trees.\n",
+            "  Evaluating internal representation of mux trees.\n",
+            "  Analyzing evaluation results.\n",
+            "Removed 0 multiplexer ports.\n",
+            "\n",
+            "4.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n",
+            "  Optimizing cells in module \\alu.\n",
+            "Performed a total of 0 changes.\n",
+            "\n",
+            "4.12.5. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\alu'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "4.12.6. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "4.12.7. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\alu..\n",
+            "\n",
+            "4.12.8. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module alu.\n",
+            "\n",
+            "4.12.9. Finished OPT passes. (There is nothing left to do.)\n",
+            "\n",
+            "4.13. Executing WREDUCE pass (reducing word size of cells).\n",
+            "Removed top 1 bits (of 3) from port B of cell alu.$procmux$441_CMP0 ($eq).\n",
+            "Removed top 1 bits (of 3) from port B of cell alu.$procmux$442_CMP0 ($eq).\n",
+            "Removed top 2 bits (of 3) from port B of cell alu.$procmux$443_CMP0 ($eq).\n",
+            "\n",
+            "4.14. Executing PEEPOPT pass (run peephole optimizers).\n",
+            "\n",
+            "4.15. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\alu..\n",
+            "\n",
+            "4.16. Executing SHARE pass (SAT-based resource sharing).\n",
+            "\n",
+            "4.17. Executing TECHMAP pass (map to technology primitives).\n",
+            "\n",
+            "4.17.1. Executing Verilog-2005 frontend: /content/miniconda-synth/bin/../share/yosys/cmp2lut.v\n",
+            "Parsing Verilog input from `/content/miniconda-synth/bin/../share/yosys/cmp2lut.v' to AST representation.\n",
+            "Generating RTLIL representation for module `\\_90_lut_cmp_'.\n",
+            "Successfully finished Verilog frontend.\n",
+            "\n",
+            "4.17.2. Continuing TECHMAP pass.\n",
+            "No more expansions possible.\n",
+            "\n",
+            "4.18. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module alu.\n",
+            "\n",
+            "4.19. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\alu..\n",
+            "\n",
+            "4.20. Executing ALUMACC pass (create $alu and $macc cells).\n",
+            "Extracting $alu and $macc cells in module alu:\n",
+            "  creating $macc model for $add$alu.v:12$2 ($add).\n",
+            "  creating $macc model for $sub$alu.v:13$3 ($sub).\n",
+            "  creating $alu model for $macc $sub$alu.v:13$3.\n",
+            "  creating $alu model for $macc $add$alu.v:12$2.\n",
+            "  creating $alu cell for $add$alu.v:12$2: $auto$alumacc.cc:485:replace_alu$466\n",
+            "  creating $alu cell for $sub$alu.v:13$3: $auto$alumacc.cc:485:replace_alu$469\n",
+            "  created 2 $alu and 0 $macc cells.\n",
+            "\n",
+            "4.21. Executing OPT pass (performing simple optimizations).\n",
+            "\n",
+            "4.21.1. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module alu.\n",
+            "\n",
+            "4.21.2. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\alu'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "4.21.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n",
+            "Running muxtree optimizer on module \\alu..\n",
+            "  Creating internal representation of mux trees.\n",
+            "  Evaluating internal representation of mux trees.\n",
+            "  Analyzing evaluation results.\n",
+            "Removed 0 multiplexer ports.\n",
+            "\n",
+            "4.21.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n",
+            "  Optimizing cells in module \\alu.\n",
+            "Performed a total of 0 changes.\n",
+            "\n",
+            "4.21.5. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\alu'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "4.21.6. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "4.21.7. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\alu..\n",
+            "\n",
+            "4.21.8. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module alu.\n",
+            "\n",
+            "4.21.9. Finished OPT passes. (There is nothing left to do.)\n",
+            "\n",
+            "4.22. Executing MEMORY pass.\n",
+            "\n",
+            "4.22.1. Executing OPT_MEM pass (optimize memories).\n",
+            "Performed a total of 0 transformations.\n",
+            "\n",
+            "4.22.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).\n",
+            "Performed a total of 0 transformations.\n",
+            "\n",
+            "4.22.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).\n",
+            "\n",
+            "4.22.4. Executing MEMORY_DFF pass (merging $dff cells to $memrd).\n",
+            "\n",
+            "4.22.5. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\alu..\n",
+            "\n",
+            "4.22.6. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).\n",
+            "\n",
+            "4.22.7. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).\n",
+            "Performed a total of 0 transformations.\n",
+            "\n",
+            "4.22.8. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\alu..\n",
+            "\n",
+            "4.22.9. Executing MEMORY_COLLECT pass (generating $mem cells).\n",
+            "\n",
+            "4.23. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\alu..\n",
+            "\n",
+            "4.24. Executing MEMORY_BRAM pass (mapping $mem cells to block memories).\n",
+            "\n",
+            "4.25. Executing TECHMAP pass (map to technology primitives).\n",
+            "\n",
+            "4.25.1. Executing Verilog-2005 frontend: /content/miniconda-synth/bin/../share/yosys/ice40/brams_map.v\n",
+            "Parsing Verilog input from `/content/miniconda-synth/bin/../share/yosys/ice40/brams_map.v' to AST representation.\n",
+            "Generating RTLIL representation for module `\\$__ICE40_RAM4K'.\n",
+            "Generating RTLIL representation for module `\\$__ICE40_RAM4K_M0'.\n",
+            "Generating RTLIL representation for module `\\$__ICE40_RAM4K_M123'.\n",
+            "Successfully finished Verilog frontend.\n",
+            "\n",
+            "4.25.2. Continuing TECHMAP pass.\n",
+            "No more expansions possible.\n",
+            "\n",
+            "4.26. Executing ICE40_BRAMINIT pass.\n",
+            "\n",
+            "4.27. Executing OPT pass (performing simple optimizations).\n",
+            "\n",
+            "4.27.1. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module alu.\n",
+            "\n",
+            "4.27.2. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\alu'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "4.27.3. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "4.27.4. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\alu..\n",
+            "Removed 0 unused cells and 1 unused wires.\n",
+            "\n",
+            "4.27.5. Finished fast OPT passes.\n",
+            "\n",
+            "4.28. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).\n",
+            "\n",
+            "4.29. Executing OPT pass (performing simple optimizations).\n",
+            "\n",
+            "4.29.1. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module alu.\n",
+            "\n",
+            "4.29.2. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\alu'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "4.29.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n",
+            "Running muxtree optimizer on module \\alu..\n",
+            "  Creating internal representation of mux trees.\n",
+            "  Evaluating internal representation of mux trees.\n",
+            "  Analyzing evaluation results.\n",
+            "Removed 0 multiplexer ports.\n",
+            "\n",
+            "4.29.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n",
+            "  Optimizing cells in module \\alu.\n",
+            "Performed a total of 0 changes.\n",
+            "\n",
+            "4.29.5. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\alu'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "4.29.6. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "4.29.7. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\alu..\n",
+            "\n",
+            "4.29.8. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module alu.\n",
+            "\n",
+            "4.29.9. Finished OPT passes. (There is nothing left to do.)\n",
+            "\n",
+            "4.30. Executing ICE40_WRAPCARRY pass (wrap carries).\n",
+            "\n",
+            "4.31. Executing TECHMAP pass (map to technology primitives).\n",
+            "\n",
+            "4.31.1. Executing Verilog-2005 frontend: /content/miniconda-synth/bin/../share/yosys/techmap.v\n",
+            "Parsing Verilog input from `/content/miniconda-synth/bin/../share/yosys/techmap.v' to AST representation.\n",
+            "Generating RTLIL representation for module `\\_90_simplemap_bool_ops'.\n",
+            "Generating RTLIL representation for module `\\_90_simplemap_reduce_ops'.\n",
+            "Generating RTLIL representation for module `\\_90_simplemap_logic_ops'.\n",
+            "Generating RTLIL representation for module `\\_90_simplemap_compare_ops'.\n",
+            "Generating RTLIL representation for module `\\_90_simplemap_various'.\n",
+            "Generating RTLIL representation for module `\\_90_simplemap_registers'.\n",
+            "Generating RTLIL representation for module `\\_90_shift_ops_shr_shl_sshl_sshr'.\n",
+            "Generating RTLIL representation for module `\\_90_shift_shiftx'.\n",
+            "Generating RTLIL representation for module `\\_90_fa'.\n",
+            "Generating RTLIL representation for module `\\_90_lcu'.\n",
+            "Generating RTLIL representation for module `\\_90_alu'.\n",
+            "Generating RTLIL representation for module `\\_90_macc'.\n",
+            "Generating RTLIL representation for module `\\_90_alumacc'.\n",
+            "Generating RTLIL representation for module `\\$__div_mod_u'.\n",
+            "Generating RTLIL representation for module `\\$__div_mod_trunc'.\n",
+            "Generating RTLIL representation for module `\\_90_div'.\n",
+            "Generating RTLIL representation for module `\\_90_mod'.\n",
+            "Generating RTLIL representation for module `\\$__div_mod_floor'.\n",
+            "Generating RTLIL representation for module `\\_90_divfloor'.\n",
+            "Generating RTLIL representation for module `\\_90_modfloor'.\n",
+            "Generating RTLIL representation for module `\\_90_pow'.\n",
+            "Generating RTLIL representation for module `\\_90_pmux'.\n",
+            "Generating RTLIL representation for module `\\_90_demux'.\n",
+            "Generating RTLIL representation for module `\\_90_lut'.\n",
+            "Successfully finished Verilog frontend.\n",
+            "\n",
+            "4.31.2. Executing Verilog-2005 frontend: /content/miniconda-synth/bin/../share/yosys/ice40/arith_map.v\n",
+            "Parsing Verilog input from `/content/miniconda-synth/bin/../share/yosys/ice40/arith_map.v' to AST representation.\n",
+            "Generating RTLIL representation for module `\\_80_ice40_alu'.\n",
+            "Successfully finished Verilog frontend.\n",
+            "\n",
+            "4.31.3. Continuing TECHMAP pass.\n",
+            "Using template $paramod$740b056ede97228d3eae64ea2fdc81f0a33e0fe7\\_80_ice40_alu for cells of type $alu.\n",
+            "Using extmapper simplemap for cells of type $and.\n",
+            "Using extmapper simplemap for cells of type $or.\n",
+            "Using extmapper simplemap for cells of type $xor.\n",
+            "Using extmapper simplemap for cells of type $not.\n",
+            "Using extmapper simplemap for cells of type $logic_not.\n",
+            "Using extmapper simplemap for cells of type $eq.\n",
+            "Using template $paramod$33afdd83bf3811dac2de7a968d39eea5718691bc\\_90_pmux for cells of type $pmux.\n",
+            "Using extmapper simplemap for cells of type $mux.\n",
+            "Using extmapper simplemap for cells of type $pos.\n",
+            "Using extmapper simplemap for cells of type $reduce_or.\n",
+            "No more expansions possible.\n",
+            "\n",
+            "4.32. Executing OPT pass (performing simple optimizations).\n",
+            "\n",
+            "4.32.1. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module alu.\n",
+            "\n",
+            "4.32.2. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\alu'.\n",
+            "Removed a total of 17 cells.\n",
+            "\n",
+            "4.32.3. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "4.32.4. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\alu..\n",
+            "Removed 4 unused cells and 85 unused wires.\n",
+            "\n",
+            "4.32.5. Finished fast OPT passes.\n",
+            "\n",
+            "4.33. Executing ICE40_OPT pass (performing simple optimizations).\n",
+            "\n",
+            "4.33.1. Running ICE40 specific optimizations.\n",
+            "\n",
+            "4.33.2. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module alu.\n",
+            "\n",
+            "4.33.3. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\alu'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "4.33.4. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "4.33.5. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\alu..\n",
+            "\n",
+            "4.33.6. Finished OPT passes. (There is nothing left to do.)\n",
+            "\n",
+            "4.34. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).\n",
+            "\n",
+            "4.35. Executing TECHMAP pass (map to technology primitives).\n",
+            "\n",
+            "4.35.1. Executing Verilog-2005 frontend: /content/miniconda-synth/bin/../share/yosys/ice40/ff_map.v\n",
+            "Parsing Verilog input from `/content/miniconda-synth/bin/../share/yosys/ice40/ff_map.v' to AST representation.\n",
+            "Generating RTLIL representation for module `\\$_DFF_N_'.\n",
+            "Generating RTLIL representation for module `\\$_DFF_P_'.\n",
+            "Generating RTLIL representation for module `\\$_DFFE_NP_'.\n",
+            "Generating RTLIL representation for module `\\$_DFFE_PP_'.\n",
+            "Generating RTLIL representation for module `\\$_DFF_NP0_'.\n",
+            "Generating RTLIL representation for module `\\$_DFF_NP1_'.\n",
+            "Generating RTLIL representation for module `\\$_DFF_PP0_'.\n",
+            "Generating RTLIL representation for module `\\$_DFF_PP1_'.\n",
+            "Generating RTLIL representation for module `\\$_DFFE_NP0P_'.\n",
+            "Generating RTLIL representation for module `\\$_DFFE_NP1P_'.\n",
+            "Generating RTLIL representation for module `\\$_DFFE_PP0P_'.\n",
+            "Generating RTLIL representation for module `\\$_DFFE_PP1P_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFF_NP0_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFF_NP1_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFF_PP0_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFF_PP1_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFFCE_NP0P_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFFCE_NP1P_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFFCE_PP0P_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFFCE_PP1P_'.\n",
+            "Successfully finished Verilog frontend.\n",
+            "\n",
+            "4.35.2. Continuing TECHMAP pass.\n",
+            "No more expansions possible.\n",
+            "\n",
+            "4.36. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module alu.\n",
+            "\n",
+            "4.37. Executing SIMPLEMAP pass (map simple cells to gate primitives).\n",
+            "\n",
+            "4.38. Executing ICE40_OPT pass (performing simple optimizations).\n",
+            "\n",
+            "4.38.1. Running ICE40 specific optimizations.\n",
+            "\n",
+            "4.38.2. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module alu.\n",
+            "\n",
+            "4.38.3. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\alu'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "4.38.4. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "4.38.5. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\alu..\n",
+            "\n",
+            "4.38.6. Rerunning OPT passes. (Removed registers in this run.)\n",
+            "\n",
+            "4.38.7. Running ICE40 specific optimizations.\n",
+            "\n",
+            "4.38.8. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module alu.\n",
+            "\n",
+            "4.38.9. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\alu'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "4.38.10. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "4.38.11. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\alu..\n",
+            "\n",
+            "4.38.12. Finished OPT passes. (There is nothing left to do.)\n",
+            "\n",
+            "4.39. Executing TECHMAP pass (map to technology primitives).\n",
+            "\n",
+            "4.39.1. Executing Verilog-2005 frontend: /content/miniconda-synth/bin/../share/yosys/ice40/latches_map.v\n",
+            "Parsing Verilog input from `/content/miniconda-synth/bin/../share/yosys/ice40/latches_map.v' to AST representation.\n",
+            "Generating RTLIL representation for module `\\$_DLATCH_N_'.\n",
+            "Generating RTLIL representation for module `\\$_DLATCH_P_'.\n",
+            "Successfully finished Verilog frontend.\n",
+            "\n",
+            "4.39.2. Continuing TECHMAP pass.\n",
+            "No more expansions possible.\n",
+            "\n",
+            "4.40. Executing ABC pass (technology mapping using ABC).\n",
+            "\n",
+            "4.40.1. Extracting gate netlist of module `\\alu' to `<abc-temp-dir>/input.blif'..\n",
+            "Extracted 107 gates and 126 wires to a netlist network with 19 inputs and 9 outputs.\n",
+            "\n",
+            "4.40.1.1. Executing ABC.\n",
+            "Running ABC command: <yosys-exe-dir>/yosys-abc -s -f <abc-temp-dir>/abc.script 2>&1\n",
+            "ABC: ABC command line: \"source <abc-temp-dir>/abc.script\".\n",
+            "ABC: \n",
+            "ABC: + read_blif <abc-temp-dir>/input.blif \n",
+            "ABC: + read_lut <abc-temp-dir>/lutdefs.txt \n",
+            "ABC: + strash \n",
+            "ABC: + ifraig \n",
+            "ABC: + scorr \n",
+            "ABC: Warning: The network is combinational (run \"fraig\" or \"fraig_sweep\").\n",
+            "ABC: + dc2 \n",
+            "ABC: + dretime \n",
+            "ABC: + strash \n",
+            "ABC: + dch -f \n",
+            "ABC: + if \n",
+            "ABC: + mfs2 \n",
+            "ABC: + lutpack -S 1 \n",
+            "ABC: + dress \n",
+            "ABC: Total number of equiv classes                =      29.\n",
+            "ABC: Participating nodes from both networks       =      63.\n",
+            "ABC: Participating nodes from the first network   =      28. (  84.85 % of nodes)\n",
+            "ABC: Participating nodes from the second network  =      35. ( 106.06 % of nodes)\n",
+            "ABC: Node pairs (any polarity)                    =      28. (  84.85 % of names can be moved)\n",
+            "ABC: Node pairs (same polarity)                   =      23. (  69.70 % of names can be moved)\n",
+            "ABC: Total runtime =     0.02 sec\n",
+            "ABC: + write_blif <abc-temp-dir>/output.blif \n",
+            "\n",
+            "4.40.1.2. Re-integrating ABC results.\n",
+            "ABC RESULTS:              $lut cells:       32\n",
+            "ABC RESULTS:        internal signals:       98\n",
+            "ABC RESULTS:           input signals:       19\n",
+            "ABC RESULTS:          output signals:        9\n",
+            "Removing temp directory.\n",
+            "\n",
+            "4.41. Executing ICE40_WRAPCARRY pass (wrap carries).\n",
+            "\n",
+            "4.42. Executing TECHMAP pass (map to technology primitives).\n",
+            "\n",
+            "4.42.1. Executing Verilog-2005 frontend: /content/miniconda-synth/bin/../share/yosys/ice40/ff_map.v\n",
+            "Parsing Verilog input from `/content/miniconda-synth/bin/../share/yosys/ice40/ff_map.v' to AST representation.\n",
+            "Generating RTLIL representation for module `\\$_DFF_N_'.\n",
+            "Generating RTLIL representation for module `\\$_DFF_P_'.\n",
+            "Generating RTLIL representation for module `\\$_DFFE_NP_'.\n",
+            "Generating RTLIL representation for module `\\$_DFFE_PP_'.\n",
+            "Generating RTLIL representation for module `\\$_DFF_NP0_'.\n",
+            "Generating RTLIL representation for module `\\$_DFF_NP1_'.\n",
+            "Generating RTLIL representation for module `\\$_DFF_PP0_'.\n",
+            "Generating RTLIL representation for module `\\$_DFF_PP1_'.\n",
+            "Generating RTLIL representation for module `\\$_DFFE_NP0P_'.\n",
+            "Generating RTLIL representation for module `\\$_DFFE_NP1P_'.\n",
+            "Generating RTLIL representation for module `\\$_DFFE_PP0P_'.\n",
+            "Generating RTLIL representation for module `\\$_DFFE_PP1P_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFF_NP0_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFF_NP1_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFF_PP0_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFF_PP1_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFFCE_NP0P_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFFCE_NP1P_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFFCE_PP0P_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFFCE_PP1P_'.\n",
+            "Successfully finished Verilog frontend.\n",
+            "\n",
+            "4.42.2. Continuing TECHMAP pass.\n",
+            "No more expansions possible.\n",
+            "Removed 2 unused cells and 62 unused wires.\n",
+            "\n",
+            "4.43. Executing OPT_LUT pass (optimize LUTs).\n",
+            "Discovering LUTs.\n",
+            "Number of LUTs:       40\n",
+            "  1-LUT                4\n",
+            "  2-LUT                1\n",
+            "  3-LUT               10\n",
+            "  4-LUT               25\n",
+            "  with \\SB_CARRY    (#0)    6\n",
+            "  with \\SB_CARRY    (#1)    6\n",
+            "\n",
+            "Eliminating LUTs.\n",
+            "Number of LUTs:       40\n",
+            "  1-LUT                4\n",
+            "  2-LUT                1\n",
+            "  3-LUT               10\n",
+            "  4-LUT               25\n",
+            "  with \\SB_CARRY    (#0)    6\n",
+            "  with \\SB_CARRY    (#1)    6\n",
+            "\n",
+            "Combining LUTs.\n",
+            "Number of LUTs:       39\n",
+            "  1-LUT                3\n",
+            "  2-LUT                1\n",
+            "  3-LUT               10\n",
+            "  4-LUT               25\n",
+            "  with \\SB_CARRY    (#0)    6\n",
+            "  with \\SB_CARRY    (#1)    6\n",
+            "\n",
+            "Eliminated 0 LUTs.\n",
+            "Combined 1 LUTs.\n",
+            "\n",
+            "4.44. Executing TECHMAP pass (map to technology primitives).\n",
+            "\n",
+            "4.44.1. Executing Verilog-2005 frontend: /content/miniconda-synth/bin/../share/yosys/ice40/cells_map.v\n",
+            "Parsing Verilog input from `/content/miniconda-synth/bin/../share/yosys/ice40/cells_map.v' to AST representation.\n",
+            "Generating RTLIL representation for module `\\$lut'.\n",
+            "Successfully finished Verilog frontend.\n",
+            "\n",
+            "4.44.2. Continuing TECHMAP pass.\n",
+            "Using template $paramod\\$lut\\WIDTH=32'00000000000000000000000000000001\\LUT=2'01 for cells of type $lut.\n",
+            "Using template $paramod$fd904e9e35cfd343a9df248824bd3f1408724879\\$lut for cells of type $lut.\n",
+            "Using template $paramod$272652f6c6fbe9a75eff76e45cc7e2788835518b\\$lut for cells of type $lut.\n",
+            "Using template $paramod$6e238df02989b317f10820a22773676e71120644\\$lut for cells of type $lut.\n",
+            "Using template $paramod\\$lut\\WIDTH=32'00000000000000000000000000000011\\LUT=8'00010000 for cells of type $lut.\n",
+            "Using template $paramod\\$lut\\WIDTH=32'00000000000000000000000000000011\\LUT=8'01000000 for cells of type $lut.\n",
+            "Using template $paramod$246006d276d15b0766d6d890a33a28800bfa7295\\$lut for cells of type $lut.\n",
+            "Using template $paramod\\$lut\\WIDTH=32'00000000000000000000000000000010\\LUT=4'0100 for cells of type $lut.\n",
+            "Using template $paramod$82b4a585d1edcb5c6e755dc9bd3392228a1c1304\\$lut for cells of type $lut.\n",
+            "Using template $paramod$62982cca7069de3707116b74c6df774a649aefd3\\$lut for cells of type $lut.\n",
+            "Using template $paramod$fe9a0158d0352193457c4f5b6282ac86d35fb3ee\\$lut for cells of type $lut.\n",
+            "Using template $paramod$4282def8dbd6df3d1248ad282c629bee684502c2\\$lut for cells of type $lut.\n",
+            "Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8\\$lut for cells of type $lut.\n",
+            "No more expansions possible.\n",
+            "Removed 0 unused cells and 92 unused wires.\n",
+            "\n",
+            "4.45. Executing AUTONAME pass.\n",
+            "Renamed 253 objects in module alu (10 iterations).\n",
+            "\n",
+            "4.46. Executing HIERARCHY pass (managing design hierarchy).\n",
+            "\n",
+            "4.46.1. Analyzing design hierarchy..\n",
+            "Top module:  \\alu\n",
+            "\n",
+            "4.46.2. Analyzing design hierarchy..\n",
+            "Top module:  \\alu\n",
+            "Removed 0 unused modules.\n",
+            "\n",
+            "4.47. Printing statistics.\n",
+            "\n",
+            "=== alu ===\n",
+            "\n",
+            "   Number of wires:                 19\n",
+            "   Number of wire bits:             72\n",
+            "   Number of public wires:          19\n",
+            "   Number of public wire bits:      72\n",
+            "   Number of memories:               0\n",
+            "   Number of memory bits:            0\n",
+            "   Number of processes:              0\n",
+            "   Number of cells:                 45\n",
+            "     SB_CARRY                        6\n",
+            "     SB_LUT4                        39\n",
+            "\n",
+            "4.48. Executing CHECK pass (checking for obvious problems).\n",
+            "Checking module alu...\n",
+            "Found and reported 0 problems.\n",
+            "\n",
+            "yosys> \n",
+            "yosys> \n",
+            "5. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\alu..\n",
+            "\n",
+            "yosys> \n",
+            "6. Generating Graphviz representation of design.\n",
+            "Writing dot description to `synth_ice40.dot'.\n",
+            "Dumping module alu to page 1.\n",
+            "\n",
+            "yosys> exit\n"
+          ]
+        }
+      ]
+    },
+    {
+      "cell_type": "code",
+      "metadata": {
+        "colab": {
+          "base_uri": "https://localhost:8080/",
+          "height": 1000
+        },
+        "id": "Tp3nbgutzIK_",
+        "outputId": "b6a148be-687f-4ec6-aee2-d8a5791f44f4"
+      },
+      "source": [
+        "import graphviz\n",
+        "graphviz.Source.from_file('synth_ice40.dot')"
+      ],
+      "execution_count": 41,
+      "outputs": [
+        {
+          "output_type": "execute_result",
+          "data": {
+            "image/svg+xml": "<?xml version=\"1.0\" encoding=\"UTF-8\" standalone=\"no\"?>\n<!DOCTYPE svg PUBLIC \"-//W3C//DTD SVG 1.1//EN\"\n \"http://www.w3.org/Graphics/SVG/1.1/DTD/svg11.dtd\">\n<!-- Generated by graphviz version 2.43.0 (0)\n -->\n<!-- Title: alu Pages: 1 -->\n<svg width=\"9405pt\" height=\"4379pt\"\n viewBox=\"0.00 0.00 9405.13 4379.10\" xmlns=\"http://www.w3.org/2000/svg\" xmlns:xlink=\"http://www.w3.org/1999/xlink\">\n<g id=\"graph0\" class=\"graph\" transform=\"scale(1 1) rotate(0) translate(4 4375.1)\">\n<title>alu</title>\n<polygon fill=\"white\" stroke=\"transparent\" points=\"-4,4 -4,-4375.1 9401.13,-4375.1 9401.13,4 -4,4\"/>\n<text text-anchor=\"middle\" x=\"4698.57\" y=\"-7.8\" font-family=\"Times,serif\" font-size=\"14.00\">alu</text>\n<!-- n1 -->\n<g id=\"node1\" class=\"node\">\n<title>n1</title>\n<polygon fill=\"none\" stroke=\"black\" points=\"1388.49,-1738.04 1388.49,-1752.96 1372.67,-1763.5 1350.31,-1763.5 1334.49,-1752.96 1334.49,-1738.04 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+            "text/plain": [
+              "<graphviz.sources.Source at 0x79c7a021fe00>"
+            ]
+          },
+          "metadata": {},
+          "execution_count": 41
+        }
+      ]
+    },
+    {
+      "cell_type": "markdown",
+      "metadata": {
+        "id": "fuTlMelBwLEo"
+      },
+      "source": [
+        "### Synth CMOS\n",
+        "\n",
+        "Synthesize CMOS netlist: map to `NOR` and `NOT` gates using CMOS technology mapping from `yosys examples."
+      ]
+    },
+    {
+      "cell_type": "code",
+      "metadata": {
+        "id": "I34dkQ01xSOj",
+        "colab": {
+          "base_uri": "https://localhost:8080/"
+        },
+        "outputId": "ca5541b8-a4ad-4ba3-e782-dc1d37aee9a2"
+      },
+      "source": [
+        "!curl --silent -L https://github.com/YosysHQ/yosys/archive/refs/tags/yosys-0.11.tar.gz | tar xvzf - yosys-yosys-0.11/examples/cmos --strip-components=2"
+      ],
+      "execution_count": 42,
+      "outputs": [
+        {
+          "output_type": "stream",
+          "name": "stdout",
+          "text": [
+            "yosys-yosys-0.11/examples/cmos/\n",
+            "yosys-yosys-0.11/examples/cmos/.gitignore\n",
+            "yosys-yosys-0.11/examples/cmos/README\n",
+            "yosys-yosys-0.11/examples/cmos/cmos_cells.lib\n",
+            "yosys-yosys-0.11/examples/cmos/cmos_cells.sp\n",
+            "yosys-yosys-0.11/examples/cmos/cmos_cells.v\n",
+            "yosys-yosys-0.11/examples/cmos/cmos_cells_digital.sp\n",
+            "yosys-yosys-0.11/examples/cmos/counter.v\n",
+            "yosys-yosys-0.11/examples/cmos/counter.ys\n",
+            "yosys-yosys-0.11/examples/cmos/counter_digital.ys\n",
+            "yosys-yosys-0.11/examples/cmos/counter_tb.gtkw\n",
+            "yosys-yosys-0.11/examples/cmos/counter_tb.v\n",
+            "yosys-yosys-0.11/examples/cmos/testbench.sh\n",
+            "yosys-yosys-0.11/examples/cmos/testbench.sp\n",
+            "yosys-yosys-0.11/examples/cmos/testbench_digital.sh\n",
+            "yosys-yosys-0.11/examples/cmos/testbench_digital.sp\n"
+          ]
+        }
+      ]
+    },
+    {
+      "cell_type": "code",
+      "metadata": {
+        "id": "m2cny9dXwLE1",
+        "colab": {
+          "base_uri": "https://localhost:8080/"
+        },
+        "outputId": "3f12b273-e3f7-429e-d278-c4e51f8404e6"
+      },
+      "source": [
+        "%%script miniconda-synth/bin/yosys -Q -T\n",
+        "\n",
+        "read -sv alu.v\n",
+        "hierarchy -top alu\n",
+        "\n",
+        "read -sv -lib cmos/cmos_cells.v\n",
+        "synth\n",
+        "dfflibmap -liberty cmos/cmos_cells.lib\n",
+        "abc -liberty cmos/cmos_cells.lib\n",
+        "\n",
+        "opt_clean\n",
+        "show -format dot -prefix synth_cmos\n",
+        "stat -liberty cmos/cmos_cells.lib"
+      ],
+      "execution_count": 43,
+      "outputs": [
+        {
+          "output_type": "stream",
+          "name": "stdout",
+          "text": [
+            "\n",
+            "yosys> \n",
+            "yosys> \n",
+            "\n",
+            "1. Executing Verilog-2005 frontend: alu.v\n",
+            "Parsing SystemVerilog input from `alu.v' to AST representation.\n",
+            "Storing AST representation for module `$abstract\\alu'.\n",
+            "Successfully finished Verilog frontend.\n",
+            "\n",
+            "yosys> \n",
+            "2. Executing HIERARCHY pass (managing design hierarchy).\n",
+            "\n",
+            "3. Executing AST frontend in derive mode using pre-parsed AST for module `\\alu'.\n",
+            "Generating RTLIL representation for module `\\alu'.\n",
+            "\n",
+            "3.1. Analyzing design hierarchy..\n",
+            "Top module:  \\alu\n",
+            "\n",
+            "3.2. Analyzing design hierarchy..\n",
+            "Top module:  \\alu\n",
+            "Removing unused module `$abstract\\alu'.\n",
+            "Removed 1 unused modules.\n",
+            "\n",
+            "yosys> \n",
+            "yosys> \n",
+            "4. Executing Verilog-2005 frontend: cmos/cmos_cells.v\n",
+            "Parsing SystemVerilog input from `cmos/cmos_cells.v' to AST representation.\n",
+            "Storing AST representation for module `$abstract\\BUF'.\n",
+            "Storing AST representation for module `$abstract\\NOT'.\n",
+            "Storing AST representation for module `$abstract\\NAND'.\n",
+            "Storing AST representation for module `$abstract\\NOR'.\n",
+            "Storing AST representation for module `$abstract\\DFF'.\n",
+            "Storing AST representation for module `$abstract\\DFFSR'.\n",
+            "Successfully finished Verilog frontend.\n",
+            "\n",
+            "yosys> \n",
+            "5. Executing SYNTH pass.\n",
+            "\n",
+            "5.1. Executing HIERARCHY pass (managing design hierarchy).\n",
+            "\n",
+            "5.1.1. Analyzing design hierarchy..\n",
+            "Top module:  \\alu\n",
+            "\n",
+            "5.1.2. Analyzing design hierarchy..\n",
+            "Top module:  \\alu\n",
+            "Removing unused module `$abstract\\DFFSR'.\n",
+            "Removing unused module `$abstract\\DFF'.\n",
+            "Removing unused module `$abstract\\NOR'.\n",
+            "Removing unused module `$abstract\\NAND'.\n",
+            "Removing unused module `$abstract\\NOT'.\n",
+            "Removing unused module `$abstract\\BUF'.\n",
+            "Removed 6 unused modules.\n",
+            "\n",
+            "5.2. Executing PROC pass (convert processes to netlists).\n",
+            "\n",
+            "5.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).\n",
+            "Cleaned up 0 empty switches.\n",
+            "\n",
+            "5.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).\n",
+            "Marked 2 switch rules as full_case in process $proc$alu.v:10$1 in module alu.\n",
+            "Removed a total of 0 dead cases.\n",
+            "\n",
+            "5.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).\n",
+            "Removed 0 redundant assignments.\n",
+            "Promoted 2 assignments to connections.\n",
+            "\n",
+            "5.2.4. Executing PROC_INIT pass (extract init attributes).\n",
+            "\n",
+            "5.2.5. Executing PROC_ARST pass (detect async resets in processes).\n",
+            "\n",
+            "5.2.6. Executing PROC_MUX pass (convert decision trees to multiplexers).\n",
+            "Creating decoders for process `\\alu.$proc$alu.v:10$1'.\n",
+            "     1/2: $1\\zero_flag[0:0]\n",
+            "     2/2: $1\\result[3:0]\n",
+            "\n",
+            "5.2.7. Executing PROC_DLATCH pass (convert process syncs to latches).\n",
+            "No latch inferred for signal `\\alu.\\result' from process `\\alu.$proc$alu.v:10$1'.\n",
+            "No latch inferred for signal `\\alu.\\zero_flag' from process `\\alu.$proc$alu.v:10$1'.\n",
+            "\n",
+            "5.2.8. Executing PROC_DFF pass (convert process syncs to FFs).\n",
+            "\n",
+            "5.2.9. Executing PROC_MEMWR pass (convert process memory writes to cells).\n",
+            "\n",
+            "5.2.10. Executing PROC_CLEAN pass (remove empty switches from decision trees).\n",
+            "Found and cleaned up 2 empty switches in `\\alu.$proc$alu.v:10$1'.\n",
+            "Removing empty process `alu.$proc$alu.v:10$1'.\n",
+            "Cleaned up 2 empty switches.\n",
+            "\n",
+            "5.2.11. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module alu.\n",
+            "\n",
+            "5.3. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module alu.\n",
+            "\n",
+            "5.4. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\alu..\n",
+            "Removed 0 unused cells and 7 unused wires.\n",
+            "\n",
+            "5.5. Executing CHECK pass (checking for obvious problems).\n",
+            "Checking module alu...\n",
+            "Found and reported 0 problems.\n",
+            "\n",
+            "5.6. Executing OPT pass (performing simple optimizations).\n",
+            "\n",
+            "5.6.1. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module alu.\n",
+            "\n",
+            "5.6.2. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\alu'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "5.6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n",
+            "Running muxtree optimizer on module \\alu..\n",
+            "  Creating internal representation of mux trees.\n",
+            "  Evaluating internal representation of mux trees.\n",
+            "  Analyzing evaluation results.\n",
+            "Removed 0 multiplexer ports.\n",
+            "\n",
+            "5.6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n",
+            "  Optimizing cells in module \\alu.\n",
+            "Performed a total of 0 changes.\n",
+            "\n",
+            "5.6.5. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\alu'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "5.6.6. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "5.6.7. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\alu..\n",
+            "\n",
+            "5.6.8. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module alu.\n",
+            "\n",
+            "5.6.9. Finished OPT passes. (There is nothing left to do.)\n",
+            "\n",
+            "5.7. Executing FSM pass (extract and optimize FSM).\n",
+            "\n",
+            "5.7.1. Executing FSM_DETECT pass (finding FSMs in design).\n",
+            "\n",
+            "5.7.2. Executing FSM_EXTRACT pass (extracting FSM from design).\n",
+            "\n",
+            "5.7.3. Executing FSM_OPT pass (simple optimizations of FSMs).\n",
+            "\n",
+            "5.7.4. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\alu..\n",
+            "\n",
+            "5.7.5. Executing FSM_OPT pass (simple optimizations of FSMs).\n",
+            "\n",
+            "5.7.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).\n",
+            "\n",
+            "5.7.7. Executing FSM_INFO pass (dumping all available information on FSM cells).\n",
+            "\n",
+            "5.7.8. Executing FSM_MAP pass (mapping FSMs to basic logic).\n",
+            "\n",
+            "5.8. Executing OPT pass (performing simple optimizations).\n",
+            "\n",
+            "5.8.1. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module alu.\n",
+            "\n",
+            "5.8.2. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\alu'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "5.8.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n",
+            "Running muxtree optimizer on module \\alu..\n",
+            "  Creating internal representation of mux trees.\n",
+            "  Evaluating internal representation of mux trees.\n",
+            "  Analyzing evaluation results.\n",
+            "Removed 0 multiplexer ports.\n",
+            "\n",
+            "5.8.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n",
+            "  Optimizing cells in module \\alu.\n",
+            "Performed a total of 0 changes.\n",
+            "\n",
+            "5.8.5. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\alu'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "5.8.6. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "5.8.7. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\alu..\n",
+            "\n",
+            "5.8.8. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module alu.\n",
+            "\n",
+            "5.8.9. Finished OPT passes. (There is nothing left to do.)\n",
+            "\n",
+            "5.9. Executing WREDUCE pass (reducing word size of cells).\n",
+            "Removed top 1 bits (of 3) from port B of cell alu.$procmux$17_CMP0 ($eq).\n",
+            "Removed top 1 bits (of 3) from port B of cell alu.$procmux$18_CMP0 ($eq).\n",
+            "Removed top 2 bits (of 3) from port B of cell alu.$procmux$19_CMP0 ($eq).\n",
+            "\n",
+            "5.10. Executing PEEPOPT pass (run peephole optimizers).\n",
+            "\n",
+            "5.11. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\alu..\n",
+            "\n",
+            "5.12. Executing ALUMACC pass (create $alu and $macc cells).\n",
+            "Extracting $alu and $macc cells in module alu:\n",
+            "  creating $macc model for $add$alu.v:12$2 ($add).\n",
+            "  creating $macc model for $sub$alu.v:13$3 ($sub).\n",
+            "  creating $alu model for $macc $sub$alu.v:13$3.\n",
+            "  creating $alu model for $macc $add$alu.v:12$2.\n",
+            "  creating $alu cell for $add$alu.v:12$2: $auto$alumacc.cc:485:replace_alu$21\n",
+            "  creating $alu cell for $sub$alu.v:13$3: $auto$alumacc.cc:485:replace_alu$24\n",
+            "  created 2 $alu and 0 $macc cells.\n",
+            "\n",
+            "5.13. Executing SHARE pass (SAT-based resource sharing).\n",
+            "\n",
+            "5.14. Executing OPT pass (performing simple optimizations).\n",
+            "\n",
+            "5.14.1. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module alu.\n",
+            "\n",
+            "5.14.2. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\alu'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "5.14.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n",
+            "Running muxtree optimizer on module \\alu..\n",
+            "  Creating internal representation of mux trees.\n",
+            "  Evaluating internal representation of mux trees.\n",
+            "  Analyzing evaluation results.\n",
+            "Removed 0 multiplexer ports.\n",
+            "\n",
+            "5.14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n",
+            "  Optimizing cells in module \\alu.\n",
+            "Performed a total of 0 changes.\n",
+            "\n",
+            "5.14.5. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\alu'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "5.14.6. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "5.14.7. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\alu..\n",
+            "\n",
+            "5.14.8. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module alu.\n",
+            "\n",
+            "5.14.9. Finished OPT passes. (There is nothing left to do.)\n",
+            "\n",
+            "5.15. Executing MEMORY pass.\n",
+            "\n",
+            "5.15.1. Executing OPT_MEM pass (optimize memories).\n",
+            "Performed a total of 0 transformations.\n",
+            "\n",
+            "5.15.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).\n",
+            "Performed a total of 0 transformations.\n",
+            "\n",
+            "5.15.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).\n",
+            "\n",
+            "5.15.4. Executing MEMORY_DFF pass (merging $dff cells to $memrd).\n",
+            "\n",
+            "5.15.5. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\alu..\n",
+            "\n",
+            "5.15.6. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).\n",
+            "\n",
+            "5.15.7. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).\n",
+            "Performed a total of 0 transformations.\n",
+            "\n",
+            "5.15.8. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\alu..\n",
+            "\n",
+            "5.15.9. Executing MEMORY_COLLECT pass (generating $mem cells).\n",
+            "\n",
+            "5.16. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\alu..\n",
+            "\n",
+            "5.17. Executing OPT pass (performing simple optimizations).\n",
+            "\n",
+            "5.17.1. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module alu.\n",
+            "\n",
+            "5.17.2. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\alu'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "5.17.3. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "5.17.4. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\alu..\n",
+            "Removed 0 unused cells and 1 unused wires.\n",
+            "\n",
+            "5.17.5. Finished fast OPT passes.\n",
+            "\n",
+            "5.18. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).\n",
+            "\n",
+            "5.19. Executing OPT pass (performing simple optimizations).\n",
+            "\n",
+            "5.19.1. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module alu.\n",
+            "\n",
+            "5.19.2. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\alu'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "5.19.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n",
+            "Running muxtree optimizer on module \\alu..\n",
+            "  Creating internal representation of mux trees.\n",
+            "  Evaluating internal representation of mux trees.\n",
+            "  Analyzing evaluation results.\n",
+            "Removed 0 multiplexer ports.\n",
+            "\n",
+            "5.19.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n",
+            "  Optimizing cells in module \\alu.\n",
+            "Performed a total of 0 changes.\n",
+            "\n",
+            "5.19.5. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\alu'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "5.19.6. Executing OPT_SHARE pass.\n",
+            "    Found cells that share an operand and can be merged by moving the $pmux $procmux$13 in front of them:\n",
+            "        $auto$alumacc.cc:485:replace_alu$24\n",
+            "        $auto$alumacc.cc:485:replace_alu$21\n",
+            "\n",
+            "5.19.7. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "5.19.8. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\alu..\n",
+            "Removed 0 unused cells and 6 unused wires.\n",
+            "\n",
+            "5.19.9. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module alu.\n",
+            "\n",
+            "5.19.10. Rerunning OPT passes. (Maybe there is more to do..)\n",
+            "\n",
+            "5.19.11. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n",
+            "Running muxtree optimizer on module \\alu..\n",
+            "  Creating internal representation of mux trees.\n",
+            "  Evaluating internal representation of mux trees.\n",
+            "  Analyzing evaluation results.\n",
+            "Removed 0 multiplexer ports.\n",
+            "\n",
+            "5.19.12. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n",
+            "  Optimizing cells in module \\alu.\n",
+            "    New ctrl vector for $pmux cell $procmux$13: { $auto$opt_reduce.cc:134:opt_pmux$35 $procmux$18_CMP $procmux$17_CMP $procmux$16_CMP $procmux$15_CMP $procmux$14_CMP }\n",
+            "  Optimizing cells in module \\alu.\n",
+            "Performed a total of 1 changes.\n",
+            "\n",
+            "5.19.13. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\alu'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "5.19.14. Executing OPT_SHARE pass.\n",
+            "\n",
+            "5.19.15. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "5.19.16. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\alu..\n",
+            "\n",
+            "5.19.17. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module alu.\n",
+            "\n",
+            "5.19.18. Rerunning OPT passes. (Maybe there is more to do..)\n",
+            "\n",
+            "5.19.19. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n",
+            "Running muxtree optimizer on module \\alu..\n",
+            "  Creating internal representation of mux trees.\n",
+            "  Evaluating internal representation of mux trees.\n",
+            "  Analyzing evaluation results.\n",
+            "Removed 0 multiplexer ports.\n",
+            "\n",
+            "5.19.20. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n",
+            "  Optimizing cells in module \\alu.\n",
+            "Performed a total of 0 changes.\n",
+            "\n",
+            "5.19.21. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\alu'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "5.19.22. Executing OPT_SHARE pass.\n",
+            "\n",
+            "5.19.23. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "5.19.24. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\alu..\n",
+            "\n",
+            "5.19.25. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module alu.\n",
+            "\n",
+            "5.19.26. Finished OPT passes. (There is nothing left to do.)\n",
+            "\n",
+            "5.20. Executing TECHMAP pass (map to technology primitives).\n",
+            "\n",
+            "5.20.1. Executing Verilog-2005 frontend: /content/miniconda-synth/bin/../share/yosys/techmap.v\n",
+            "Parsing Verilog input from `/content/miniconda-synth/bin/../share/yosys/techmap.v' to AST representation.\n",
+            "Generating RTLIL representation for module `\\_90_simplemap_bool_ops'.\n",
+            "Generating RTLIL representation for module `\\_90_simplemap_reduce_ops'.\n",
+            "Generating RTLIL representation for module `\\_90_simplemap_logic_ops'.\n",
+            "Generating RTLIL representation for module `\\_90_simplemap_compare_ops'.\n",
+            "Generating RTLIL representation for module `\\_90_simplemap_various'.\n",
+            "Generating RTLIL representation for module `\\_90_simplemap_registers'.\n",
+            "Generating RTLIL representation for module `\\_90_shift_ops_shr_shl_sshl_sshr'.\n",
+            "Generating RTLIL representation for module `\\_90_shift_shiftx'.\n",
+            "Generating RTLIL representation for module `\\_90_fa'.\n",
+            "Generating RTLIL representation for module `\\_90_lcu'.\n",
+            "Generating RTLIL representation for module `\\_90_alu'.\n",
+            "Generating RTLIL representation for module `\\_90_macc'.\n",
+            "Generating RTLIL representation for module `\\_90_alumacc'.\n",
+            "Generating RTLIL representation for module `\\$__div_mod_u'.\n",
+            "Generating RTLIL representation for module `\\$__div_mod_trunc'.\n",
+            "Generating RTLIL representation for module `\\_90_div'.\n",
+            "Generating RTLIL representation for module `\\_90_mod'.\n",
+            "Generating RTLIL representation for module `\\$__div_mod_floor'.\n",
+            "Generating RTLIL representation for module `\\_90_divfloor'.\n",
+            "Generating RTLIL representation for module `\\_90_modfloor'.\n",
+            "Generating RTLIL representation for module `\\_90_pow'.\n",
+            "Generating RTLIL representation for module `\\_90_pmux'.\n",
+            "Generating RTLIL representation for module `\\_90_demux'.\n",
+            "Generating RTLIL representation for module `\\_90_lut'.\n",
+            "Successfully finished Verilog frontend.\n",
+            "\n",
+            "5.20.2. Continuing TECHMAP pass.\n",
+            "Using template $paramod$740b056ede97228d3eae64ea2fdc81f0a33e0fe7\\_90_alu for cells of type $alu.\n",
+            "Using extmapper simplemap for cells of type $reduce_or.\n",
+            "Using extmapper simplemap for cells of type $mux.\n",
+            "Using extmapper simplemap for cells of type $and.\n",
+            "Using extmapper simplemap for cells of type $or.\n",
+            "Using extmapper simplemap for cells of type $xor.\n",
+            "Using extmapper simplemap for cells of type $not.\n",
+            "Using extmapper simplemap for cells of type $logic_not.\n",
+            "Running \"alumacc\" on wrapper $extern:wrap:$neg:A_SIGNED=0:A_WIDTH=4:Y_WIDTH=4:394426c56d1a028ba8fdd5469b163e04011def47.\n",
+            "Using template $extern:wrap:$neg:A_SIGNED=0:A_WIDTH=4:Y_WIDTH=4:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$neg:A_SIGNED=0:A_WIDTH=4:Y_WIDTH=4:394426c56d1a028ba8fdd5469b163e04011def47.\n",
+            "Using extmapper simplemap for cells of type $eq.\n",
+            "Using template $paramod$a13703aa027da371a1931fc542d213d7de559b19\\_90_pmux for cells of type $pmux.\n",
+            "Using template $paramod\\_90_lcu\\WIDTH=32'00000000000000000000000000000100 for cells of type $lcu.\n",
+            "Using extmapper simplemap for cells of type $pos.\n",
+            "Using template $paramod$6b90a16b6f3b57b9c9d958838204f952a01dc262\\_90_alu for cells of type $alu.\n",
+            "No more expansions possible.\n",
+            "\n",
+            "5.21. Executing OPT pass (performing simple optimizations).\n",
+            "\n",
+            "5.21.1. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module alu.\n",
+            "\n",
+            "5.21.2. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\alu'.\n",
+            "Removed a total of 10 cells.\n",
+            "\n",
+            "5.21.3. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "5.21.4. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\alu..\n",
+            "Removed 8 unused cells and 118 unused wires.\n",
+            "\n",
+            "5.21.5. Finished fast OPT passes.\n",
+            "\n",
+            "5.22. Executing ABC pass (technology mapping using ABC).\n",
+            "\n",
+            "5.22.1. Extracting gate netlist of module `\\alu' to `<abc-temp-dir>/input.blif'..\n",
+            "Extracted 126 gates and 138 wires to a netlist network with 11 inputs and 5 outputs.\n",
+            "\n",
+            "5.22.1.1. Executing ABC.\n",
+            "Running ABC command: <yosys-exe-dir>/yosys-abc -s -f <abc-temp-dir>/abc.script 2>&1\n",
+            "ABC: ABC command line: \"source <abc-temp-dir>/abc.script\".\n",
+            "ABC: \n",
+            "ABC: + read_blif <abc-temp-dir>/input.blif \n",
+            "ABC: + read_library <abc-temp-dir>/stdcells.genlib \n",
+            "ABC: Entered genlib library with 13 gates from file \"<abc-temp-dir>/stdcells.genlib\".\n",
+            "ABC: + strash \n",
+            "ABC: + dretime \n",
+            "ABC: + map \n",
+            "ABC: + write_blif <abc-temp-dir>/output.blif \n",
+            "\n",
+            "5.22.1.2. Re-integrating ABC results.\n",
+            "ABC RESULTS:            ANDNOT cells:       41\n",
+            "ABC RESULTS:               MUX cells:        7\n",
+            "ABC RESULTS:              NAND cells:        6\n",
+            "ABC RESULTS:               NOR cells:        7\n",
+            "ABC RESULTS:               NOT cells:        5\n",
+            "ABC RESULTS:                OR cells:       17\n",
+            "ABC RESULTS:             ORNOT cells:        3\n",
+            "ABC RESULTS:              XNOR cells:        5\n",
+            "ABC RESULTS:               XOR cells:        8\n",
+            "ABC RESULTS:        internal signals:      122\n",
+            "ABC RESULTS:           input signals:       11\n",
+            "ABC RESULTS:          output signals:        5\n",
+            "Removing temp directory.\n",
+            "\n",
+            "5.23. Executing OPT pass (performing simple optimizations).\n",
+            "\n",
+            "5.23.1. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module alu.\n",
+            "\n",
+            "5.23.2. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\alu'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "5.23.3. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "5.23.4. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\alu..\n",
+            "Removed 0 unused cells and 60 unused wires.\n",
+            "\n",
+            "5.23.5. Finished fast OPT passes.\n",
+            "\n",
+            "5.24. Executing HIERARCHY pass (managing design hierarchy).\n",
+            "\n",
+            "5.24.1. Analyzing design hierarchy..\n",
+            "Top module:  \\alu\n",
+            "\n",
+            "5.24.2. Analyzing design hierarchy..\n",
+            "Top module:  \\alu\n",
+            "Removed 0 unused modules.\n",
+            "\n",
+            "5.25. Printing statistics.\n",
+            "\n",
+            "=== alu ===\n",
+            "\n",
+            "   Number of wires:                 99\n",
+            "   Number of wire bits:            110\n",
+            "   Number of public wires:           5\n",
+            "   Number of public wire bits:      16\n",
+            "   Number of memories:               0\n",
+            "   Number of memory bits:            0\n",
+            "   Number of processes:              0\n",
+            "   Number of cells:                 99\n",
+            "     $_ANDNOT_                      41\n",
+            "     $_MUX_                          7\n",
+            "     $_NAND_                         6\n",
+            "     $_NOR_                          7\n",
+            "     $_NOT_                          5\n",
+            "     $_ORNOT_                        3\n",
+            "     $_OR_                          17\n",
+            "     $_XNOR_                         5\n",
+            "     $_XOR_                          8\n",
+            "\n",
+            "5.26. Executing CHECK pass (checking for obvious problems).\n",
+            "Checking module alu...\n",
+            "Found and reported 0 problems.\n",
+            "\n",
+            "yosys> \n",
+            "6. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).\n",
+            "  cell DFF (noninv, pins=3, area=18.00) is a direct match for cell type $_DFF_P_.\n",
+            "  cell DFFSR (noninv, pins=5, area=18.00) is a direct match for cell type $_DFFSR_PPP_.\n",
+            "  final dff cell mappings:\n",
+            "    unmapped dff cell: $_DFF_N_\n",
+            "    \\DFF _DFF_P_ (.C( C), .D( D), .Q( Q));\n",
+            "    unmapped dff cell: $_DFF_NN0_\n",
+            "    unmapped dff cell: $_DFF_NN1_\n",
+            "    unmapped dff cell: $_DFF_NP0_\n",
+            "    unmapped dff cell: $_DFF_NP1_\n",
+            "    unmapped dff cell: $_DFF_PN0_\n",
+            "    unmapped dff cell: $_DFF_PN1_\n",
+            "    unmapped dff cell: $_DFF_PP0_\n",
+            "    unmapped dff cell: $_DFF_PP1_\n",
+            "    unmapped dff cell: $_DFFSR_NNN_\n",
+            "    unmapped dff cell: $_DFFSR_NNP_\n",
+            "    unmapped dff cell: $_DFFSR_NPN_\n",
+            "    unmapped dff cell: $_DFFSR_NPP_\n",
+            "    unmapped dff cell: $_DFFSR_PNN_\n",
+            "    unmapped dff cell: $_DFFSR_PNP_\n",
+            "    unmapped dff cell: $_DFFSR_PPN_\n",
+            "    \\DFFSR _DFFSR_PPP_ (.C( C), .D( D), .Q( Q), .R( R), .S( S));\n",
+            "\n",
+            "6.1. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).\n",
+            "Mapping DFF cells in module `\\alu':\n",
+            "\n",
+            "yosys> \n",
+            "7. Executing ABC pass (technology mapping using ABC).\n",
+            "\n",
+            "7.1. Extracting gate netlist of module `\\alu' to `<abc-temp-dir>/input.blif'..\n",
+            "Extracted 99 gates and 110 wires to a netlist network with 11 inputs and 5 outputs.\n",
+            "\n",
+            "7.1.1. Executing ABC.\n",
+            "Running ABC command: <yosys-exe-dir>/yosys-abc -s -f <abc-temp-dir>/abc.script 2>&1\n",
+            "ABC: ABC command line: \"source <abc-temp-dir>/abc.script\".\n",
+            "ABC: \n",
+            "ABC: + read_blif <abc-temp-dir>/input.blif \n",
+            "ABC: + read_lib -w /content/cmos/cmos_cells.lib \n",
+            "ABC: Parsing finished successfully.  Parsing time =     0.00 sec\n",
+            "ABC: Warning: Templates are not defined.\n",
+            "ABC: Libery parser cannot read \"time_unit\".  Assuming   time_unit : \"1ns\".\n",
+            "ABC: Libery parser cannot read \"capacitive_load_unit\". Assuming   capacitive_load_unit(1, pf).\n",
+            "ABC: Scl_LibertyReadGenlib() skipped sequential cell \"DFF\".\n",
+            "ABC: Scl_LibertyReadGenlib() skipped sequential cell \"DFFSR\".\n",
+            "ABC: Library \"demo\" from \"/content/cmos/cmos_cells.lib\" has 4 cells (2 skipped: 2 seq; 0 tri-state; 0 no func; 0 dont_use).  Time =     0.00 sec\n",
+            "ABC: Memory =    0.00 MB. Time =     0.00 sec\n",
+            "ABC: + strash \n",
+            "ABC: + ifraig \n",
+            "ABC: + scorr \n",
+            "ABC: Warning: The network is combinational (run \"fraig\" or \"fraig_sweep\").\n",
+            "ABC: + dc2 \n",
+            "ABC: + dretime \n",
+            "ABC: + strash \n",
+            "ABC: + &get -n \n",
+            "ABC: + &dch -f \n",
+            "ABC: + &nf \n",
+            "ABC: + &put \n",
+            "ABC: + write_blif <abc-temp-dir>/output.blif \n",
+            "\n",
+            "7.1.2. Re-integrating ABC results.\n",
+            "ABC RESULTS:              NAND cells:       63\n",
+            "ABC RESULTS:               NOR cells:       56\n",
+            "ABC RESULTS:               NOT cells:       23\n",
+            "ABC RESULTS:        internal signals:       94\n",
+            "ABC RESULTS:           input signals:       11\n",
+            "ABC RESULTS:          output signals:        5\n",
+            "Removing temp directory.\n",
+            "\n",
+            "yosys> \n",
+            "yosys> \n",
+            "8. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\alu..\n",
+            "Removed 0 unused cells and 110 unused wires.\n",
+            "\n",
+            "yosys> \n",
+            "9. Generating Graphviz representation of design.\n",
+            "Writing dot description to `synth_cmos.dot'.\n",
+            "Dumping module alu to page 1.\n",
+            "\n",
+            "yosys> \n",
+            "10. Printing statistics.\n",
+            "\n",
+            "=== alu ===\n",
+            "\n",
+            "   Number of wires:                142\n",
+            "   Number of wire bits:            153\n",
+            "   Number of public wires:           5\n",
+            "   Number of public wire bits:      16\n",
+            "   Number of memories:               0\n",
+            "   Number of memory bits:            0\n",
+            "   Number of processes:              0\n",
+            "   Number of cells:                142\n",
+            "     NAND                           63\n",
+            "     NOR                            56\n",
+            "     NOT                            23\n",
+            "\n",
+            "   Chip area for module '\\alu': 545.000000\n",
+            "\n",
+            "\n",
+            "yosys> exit\n"
+          ]
+        }
+      ]
+    },
+    {
+      "cell_type": "code",
+      "metadata": {
+        "colab": {
+          "base_uri": "https://localhost:8080/",
+          "height": 1000
+        },
+        "id": "8FhBL03awLE2",
+        "outputId": "761aabe6-fea4-4d7b-e970-494bddeaf87a"
+      },
+      "source": [
+        "import graphviz\n",
+        "graphviz.Source.from_file('synth_cmos.dot')"
+      ],
+      "execution_count": 44,
+      "outputs": [
+        {
+          "output_type": "execute_result",
+          "data": {
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+            "text/plain": [
+              "<graphviz.sources.Source at 0x79c78acf96a0>"
+            ]
+          },
+          "metadata": {},
+          "execution_count": 44
+        }
+      ]
+    },
+    {
+      "cell_type": "markdown",
+      "metadata": {
+        "id": "NIEm0b5h0Bej"
+      },
+      "source": [
+        "### Synth 74xx\n",
+        "\n",
+        "Synthesize 74xx netlist: map to `74AC08` a nd `74AC86` discrete gate ICs using community provided technology mapping."
+      ]
+    },
+    {
+      "cell_type": "code",
+      "metadata": {
+        "id": "ap3OuVzD1omG",
+        "colab": {
+          "base_uri": "https://localhost:8080/"
+        },
+        "outputId": "8eda9272-e8a2-4d0b-96a0-6aa1e0e4ca10"
+      },
+      "source": [
+        "!git clone https://github.com/Ravenslofty/74xx-liberty"
+      ],
+      "execution_count": 45,
+      "outputs": [
+        {
+          "output_type": "stream",
+          "name": "stdout",
+          "text": [
+            "Cloning into '74xx-liberty'...\n",
+            "remote: Enumerating objects: 238, done.\u001b[K\n",
+            "remote: Counting objects: 100% (68/68), done.\u001b[K\n",
+            "remote: Compressing objects: 100% (10/10), done.\u001b[K\n",
+            "remote: Total 238 (delta 59), reused 58 (delta 58), pack-reused 170 (from 1)\u001b[K\n",
+            "Receiving objects: 100% (238/238), 112.96 KiB | 5.94 MiB/s, done.\n",
+            "Resolving deltas: 100% (128/128), done.\n"
+          ]
+        }
+      ]
+    },
+    {
+      "cell_type": "code",
+      "metadata": {
+        "id": "8FDlOsUe0Bet",
+        "colab": {
+          "base_uri": "https://localhost:8080/"
+        },
+        "outputId": "98cdbdcf-8324-497a-a510-d9157cf463f1"
+      },
+      "source": [
+        "%%script miniconda-synth/bin/yosys -Q -T\n",
+        "\n",
+        "read -sv alu.v\n",
+        "hierarchy -top alu\n",
+        "\n",
+        "read -sv -lib 74xx-liberty/74_models.v\n",
+        "synth\n",
+        "abc -liberty 74xx-liberty/74ac.lib\n",
+        "dfflibmap -liberty 74xx-liberty/74ac.lib\n",
+        "\n",
+        "opt_clean\n",
+        "show -format dot -prefix synth_74\n",
+        "stat -liberty 74xx-liberty/74ac.lib"
+      ],
+      "execution_count": 46,
+      "outputs": [
+        {
+          "output_type": "stream",
+          "name": "stdout",
+          "text": [
+            "\n",
+            "yosys> \n",
+            "yosys> \n",
+            "\n",
+            "1. Executing Verilog-2005 frontend: alu.v\n",
+            "Parsing SystemVerilog input from `alu.v' to AST representation.\n",
+            "Storing AST representation for module `$abstract\\alu'.\n",
+            "Successfully finished Verilog frontend.\n",
+            "\n",
+            "yosys> \n",
+            "2. Executing HIERARCHY pass (managing design hierarchy).\n",
+            "\n",
+            "3. Executing AST frontend in derive mode using pre-parsed AST for module `\\alu'.\n",
+            "Generating RTLIL representation for module `\\alu'.\n",
+            "\n",
+            "3.1. Analyzing design hierarchy..\n",
+            "Top module:  \\alu\n",
+            "\n",
+            "3.2. Analyzing design hierarchy..\n",
+            "Top module:  \\alu\n",
+            "Removing unused module `$abstract\\alu'.\n",
+            "Removed 1 unused modules.\n",
+            "\n",
+            "yosys> \n",
+            "yosys> \n",
+            "4. Executing Verilog-2005 frontend: 74xx-liberty/74_models.v\n",
+            "Parsing SystemVerilog input from `74xx-liberty/74_models.v' to AST representation.\n",
+            "Storing AST representation for module `$abstract\\74HC85_1x1CMP4'.\n",
+            "Storing AST representation for module `$abstract\\74AC283_1x1ADD4'.\n",
+            "Storing AST representation for module `$abstract\\74AC377_8x1DFFE'.\n",
+            "Storing AST representation for module `$abstract\\74HC688_1x1EQ8'.\n",
+            "Storing AST representation for module `$abstract\\74AC161_1x1COUNT4'.\n",
+            "Successfully finished Verilog frontend.\n",
+            "\n",
+            "yosys> \n",
+            "5. Executing SYNTH pass.\n",
+            "\n",
+            "5.1. Executing HIERARCHY pass (managing design hierarchy).\n",
+            "\n",
+            "5.1.1. Analyzing design hierarchy..\n",
+            "Top module:  \\alu\n",
+            "\n",
+            "5.1.2. Analyzing design hierarchy..\n",
+            "Top module:  \\alu\n",
+            "Removing unused module `$abstract\\74AC161_1x1COUNT4'.\n",
+            "Removing unused module `$abstract\\74HC688_1x1EQ8'.\n",
+            "Removing unused module `$abstract\\74AC377_8x1DFFE'.\n",
+            "Removing unused module `$abstract\\74AC283_1x1ADD4'.\n",
+            "Removing unused module `$abstract\\74HC85_1x1CMP4'.\n",
+            "Removed 5 unused modules.\n",
+            "\n",
+            "5.2. Executing PROC pass (convert processes to netlists).\n",
+            "\n",
+            "5.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).\n",
+            "Cleaned up 0 empty switches.\n",
+            "\n",
+            "5.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).\n",
+            "Marked 2 switch rules as full_case in process $proc$alu.v:10$1 in module alu.\n",
+            "Removed a total of 0 dead cases.\n",
+            "\n",
+            "5.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).\n",
+            "Removed 0 redundant assignments.\n",
+            "Promoted 2 assignments to connections.\n",
+            "\n",
+            "5.2.4. Executing PROC_INIT pass (extract init attributes).\n",
+            "\n",
+            "5.2.5. Executing PROC_ARST pass (detect async resets in processes).\n",
+            "\n",
+            "5.2.6. Executing PROC_MUX pass (convert decision trees to multiplexers).\n",
+            "Creating decoders for process `\\alu.$proc$alu.v:10$1'.\n",
+            "     1/2: $1\\zero_flag[0:0]\n",
+            "     2/2: $1\\result[3:0]\n",
+            "\n",
+            "5.2.7. Executing PROC_DLATCH pass (convert process syncs to latches).\n",
+            "No latch inferred for signal `\\alu.\\result' from process `\\alu.$proc$alu.v:10$1'.\n",
+            "No latch inferred for signal `\\alu.\\zero_flag' from process `\\alu.$proc$alu.v:10$1'.\n",
+            "\n",
+            "5.2.8. Executing PROC_DFF pass (convert process syncs to FFs).\n",
+            "\n",
+            "5.2.9. Executing PROC_MEMWR pass (convert process memory writes to cells).\n",
+            "\n",
+            "5.2.10. Executing PROC_CLEAN pass (remove empty switches from decision trees).\n",
+            "Found and cleaned up 2 empty switches in `\\alu.$proc$alu.v:10$1'.\n",
+            "Removing empty process `alu.$proc$alu.v:10$1'.\n",
+            "Cleaned up 2 empty switches.\n",
+            "\n",
+            "5.2.11. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module alu.\n",
+            "\n",
+            "5.3. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module alu.\n",
+            "\n",
+            "5.4. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\alu..\n",
+            "Removed 0 unused cells and 7 unused wires.\n",
+            "\n",
+            "5.5. Executing CHECK pass (checking for obvious problems).\n",
+            "Checking module alu...\n",
+            "Found and reported 0 problems.\n",
+            "\n",
+            "5.6. Executing OPT pass (performing simple optimizations).\n",
+            "\n",
+            "5.6.1. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module alu.\n",
+            "\n",
+            "5.6.2. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\alu'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "5.6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n",
+            "Running muxtree optimizer on module \\alu..\n",
+            "  Creating internal representation of mux trees.\n",
+            "  Evaluating internal representation of mux trees.\n",
+            "  Analyzing evaluation results.\n",
+            "Removed 0 multiplexer ports.\n",
+            "\n",
+            "5.6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n",
+            "  Optimizing cells in module \\alu.\n",
+            "Performed a total of 0 changes.\n",
+            "\n",
+            "5.6.5. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\alu'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "5.6.6. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "5.6.7. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\alu..\n",
+            "\n",
+            "5.6.8. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module alu.\n",
+            "\n",
+            "5.6.9. Finished OPT passes. (There is nothing left to do.)\n",
+            "\n",
+            "5.7. Executing FSM pass (extract and optimize FSM).\n",
+            "\n",
+            "5.7.1. Executing FSM_DETECT pass (finding FSMs in design).\n",
+            "\n",
+            "5.7.2. Executing FSM_EXTRACT pass (extracting FSM from design).\n",
+            "\n",
+            "5.7.3. Executing FSM_OPT pass (simple optimizations of FSMs).\n",
+            "\n",
+            "5.7.4. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\alu..\n",
+            "\n",
+            "5.7.5. Executing FSM_OPT pass (simple optimizations of FSMs).\n",
+            "\n",
+            "5.7.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).\n",
+            "\n",
+            "5.7.7. Executing FSM_INFO pass (dumping all available information on FSM cells).\n",
+            "\n",
+            "5.7.8. Executing FSM_MAP pass (mapping FSMs to basic logic).\n",
+            "\n",
+            "5.8. Executing OPT pass (performing simple optimizations).\n",
+            "\n",
+            "5.8.1. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module alu.\n",
+            "\n",
+            "5.8.2. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\alu'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "5.8.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n",
+            "Running muxtree optimizer on module \\alu..\n",
+            "  Creating internal representation of mux trees.\n",
+            "  Evaluating internal representation of mux trees.\n",
+            "  Analyzing evaluation results.\n",
+            "Removed 0 multiplexer ports.\n",
+            "\n",
+            "5.8.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n",
+            "  Optimizing cells in module \\alu.\n",
+            "Performed a total of 0 changes.\n",
+            "\n",
+            "5.8.5. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\alu'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "5.8.6. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "5.8.7. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\alu..\n",
+            "\n",
+            "5.8.8. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module alu.\n",
+            "\n",
+            "5.8.9. Finished OPT passes. (There is nothing left to do.)\n",
+            "\n",
+            "5.9. Executing WREDUCE pass (reducing word size of cells).\n",
+            "Removed top 1 bits (of 3) from port B of cell alu.$procmux$17_CMP0 ($eq).\n",
+            "Removed top 1 bits (of 3) from port B of cell alu.$procmux$18_CMP0 ($eq).\n",
+            "Removed top 2 bits (of 3) from port B of cell alu.$procmux$19_CMP0 ($eq).\n",
+            "\n",
+            "5.10. Executing PEEPOPT pass (run peephole optimizers).\n",
+            "\n",
+            "5.11. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\alu..\n",
+            "\n",
+            "5.12. Executing ALUMACC pass (create $alu and $macc cells).\n",
+            "Extracting $alu and $macc cells in module alu:\n",
+            "  creating $macc model for $add$alu.v:12$2 ($add).\n",
+            "  creating $macc model for $sub$alu.v:13$3 ($sub).\n",
+            "  creating $alu model for $macc $sub$alu.v:13$3.\n",
+            "  creating $alu model for $macc $add$alu.v:12$2.\n",
+            "  creating $alu cell for $add$alu.v:12$2: $auto$alumacc.cc:485:replace_alu$21\n",
+            "  creating $alu cell for $sub$alu.v:13$3: $auto$alumacc.cc:485:replace_alu$24\n",
+            "  created 2 $alu and 0 $macc cells.\n",
+            "\n",
+            "5.13. Executing SHARE pass (SAT-based resource sharing).\n",
+            "\n",
+            "5.14. Executing OPT pass (performing simple optimizations).\n",
+            "\n",
+            "5.14.1. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module alu.\n",
+            "\n",
+            "5.14.2. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\alu'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "5.14.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n",
+            "Running muxtree optimizer on module \\alu..\n",
+            "  Creating internal representation of mux trees.\n",
+            "  Evaluating internal representation of mux trees.\n",
+            "  Analyzing evaluation results.\n",
+            "Removed 0 multiplexer ports.\n",
+            "\n",
+            "5.14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n",
+            "  Optimizing cells in module \\alu.\n",
+            "Performed a total of 0 changes.\n",
+            "\n",
+            "5.14.5. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\alu'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "5.14.6. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "5.14.7. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\alu..\n",
+            "\n",
+            "5.14.8. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module alu.\n",
+            "\n",
+            "5.14.9. Finished OPT passes. (There is nothing left to do.)\n",
+            "\n",
+            "5.15. Executing MEMORY pass.\n",
+            "\n",
+            "5.15.1. Executing OPT_MEM pass (optimize memories).\n",
+            "Performed a total of 0 transformations.\n",
+            "\n",
+            "5.15.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).\n",
+            "Performed a total of 0 transformations.\n",
+            "\n",
+            "5.15.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).\n",
+            "\n",
+            "5.15.4. Executing MEMORY_DFF pass (merging $dff cells to $memrd).\n",
+            "\n",
+            "5.15.5. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\alu..\n",
+            "\n",
+            "5.15.6. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).\n",
+            "\n",
+            "5.15.7. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).\n",
+            "Performed a total of 0 transformations.\n",
+            "\n",
+            "5.15.8. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\alu..\n",
+            "\n",
+            "5.15.9. Executing MEMORY_COLLECT pass (generating $mem cells).\n",
+            "\n",
+            "5.16. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\alu..\n",
+            "\n",
+            "5.17. Executing OPT pass (performing simple optimizations).\n",
+            "\n",
+            "5.17.1. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module alu.\n",
+            "\n",
+            "5.17.2. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\alu'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "5.17.3. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "5.17.4. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\alu..\n",
+            "Removed 0 unused cells and 1 unused wires.\n",
+            "\n",
+            "5.17.5. Finished fast OPT passes.\n",
+            "\n",
+            "5.18. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).\n",
+            "\n",
+            "5.19. Executing OPT pass (performing simple optimizations).\n",
+            "\n",
+            "5.19.1. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module alu.\n",
+            "\n",
+            "5.19.2. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\alu'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "5.19.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n",
+            "Running muxtree optimizer on module \\alu..\n",
+            "  Creating internal representation of mux trees.\n",
+            "  Evaluating internal representation of mux trees.\n",
+            "  Analyzing evaluation results.\n",
+            "Removed 0 multiplexer ports.\n",
+            "\n",
+            "5.19.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n",
+            "  Optimizing cells in module \\alu.\n",
+            "Performed a total of 0 changes.\n",
+            "\n",
+            "5.19.5. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\alu'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "5.19.6. Executing OPT_SHARE pass.\n",
+            "    Found cells that share an operand and can be merged by moving the $pmux $procmux$13 in front of them:\n",
+            "        $auto$alumacc.cc:485:replace_alu$24\n",
+            "        $auto$alumacc.cc:485:replace_alu$21\n",
+            "\n",
+            "5.19.7. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "5.19.8. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\alu..\n",
+            "Removed 0 unused cells and 6 unused wires.\n",
+            "\n",
+            "5.19.9. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module alu.\n",
+            "\n",
+            "5.19.10. Rerunning OPT passes. (Maybe there is more to do..)\n",
+            "\n",
+            "5.19.11. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n",
+            "Running muxtree optimizer on module \\alu..\n",
+            "  Creating internal representation of mux trees.\n",
+            "  Evaluating internal representation of mux trees.\n",
+            "  Analyzing evaluation results.\n",
+            "Removed 0 multiplexer ports.\n",
+            "\n",
+            "5.19.12. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n",
+            "  Optimizing cells in module \\alu.\n",
+            "    New ctrl vector for $pmux cell $procmux$13: { $auto$opt_reduce.cc:134:opt_pmux$35 $procmux$18_CMP $procmux$17_CMP $procmux$16_CMP $procmux$15_CMP $procmux$14_CMP }\n",
+            "  Optimizing cells in module \\alu.\n",
+            "Performed a total of 1 changes.\n",
+            "\n",
+            "5.19.13. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\alu'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "5.19.14. Executing OPT_SHARE pass.\n",
+            "\n",
+            "5.19.15. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "5.19.16. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\alu..\n",
+            "\n",
+            "5.19.17. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module alu.\n",
+            "\n",
+            "5.19.18. Rerunning OPT passes. (Maybe there is more to do..)\n",
+            "\n",
+            "5.19.19. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n",
+            "Running muxtree optimizer on module \\alu..\n",
+            "  Creating internal representation of mux trees.\n",
+            "  Evaluating internal representation of mux trees.\n",
+            "  Analyzing evaluation results.\n",
+            "Removed 0 multiplexer ports.\n",
+            "\n",
+            "5.19.20. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n",
+            "  Optimizing cells in module \\alu.\n",
+            "Performed a total of 0 changes.\n",
+            "\n",
+            "5.19.21. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\alu'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "5.19.22. Executing OPT_SHARE pass.\n",
+            "\n",
+            "5.19.23. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "5.19.24. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\alu..\n",
+            "\n",
+            "5.19.25. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module alu.\n",
+            "\n",
+            "5.19.26. Finished OPT passes. (There is nothing left to do.)\n",
+            "\n",
+            "5.20. Executing TECHMAP pass (map to technology primitives).\n",
+            "\n",
+            "5.20.1. Executing Verilog-2005 frontend: /content/miniconda-synth/bin/../share/yosys/techmap.v\n",
+            "Parsing Verilog input from `/content/miniconda-synth/bin/../share/yosys/techmap.v' to AST representation.\n",
+            "Generating RTLIL representation for module `\\_90_simplemap_bool_ops'.\n",
+            "Generating RTLIL representation for module `\\_90_simplemap_reduce_ops'.\n",
+            "Generating RTLIL representation for module `\\_90_simplemap_logic_ops'.\n",
+            "Generating RTLIL representation for module `\\_90_simplemap_compare_ops'.\n",
+            "Generating RTLIL representation for module `\\_90_simplemap_various'.\n",
+            "Generating RTLIL representation for module `\\_90_simplemap_registers'.\n",
+            "Generating RTLIL representation for module `\\_90_shift_ops_shr_shl_sshl_sshr'.\n",
+            "Generating RTLIL representation for module `\\_90_shift_shiftx'.\n",
+            "Generating RTLIL representation for module `\\_90_fa'.\n",
+            "Generating RTLIL representation for module `\\_90_lcu'.\n",
+            "Generating RTLIL representation for module `\\_90_alu'.\n",
+            "Generating RTLIL representation for module `\\_90_macc'.\n",
+            "Generating RTLIL representation for module `\\_90_alumacc'.\n",
+            "Generating RTLIL representation for module `\\$__div_mod_u'.\n",
+            "Generating RTLIL representation for module `\\$__div_mod_trunc'.\n",
+            "Generating RTLIL representation for module `\\_90_div'.\n",
+            "Generating RTLIL representation for module `\\_90_mod'.\n",
+            "Generating RTLIL representation for module `\\$__div_mod_floor'.\n",
+            "Generating RTLIL representation for module `\\_90_divfloor'.\n",
+            "Generating RTLIL representation for module `\\_90_modfloor'.\n",
+            "Generating RTLIL representation for module `\\_90_pow'.\n",
+            "Generating RTLIL representation for module `\\_90_pmux'.\n",
+            "Generating RTLIL representation for module `\\_90_demux'.\n",
+            "Generating RTLIL representation for module `\\_90_lut'.\n",
+            "Successfully finished Verilog frontend.\n",
+            "\n",
+            "5.20.2. Continuing TECHMAP pass.\n",
+            "Using template $paramod$740b056ede97228d3eae64ea2fdc81f0a33e0fe7\\_90_alu for cells of type $alu.\n",
+            "Using extmapper simplemap for cells of type $reduce_or.\n",
+            "Using extmapper simplemap for cells of type $mux.\n",
+            "Using extmapper simplemap for cells of type $and.\n",
+            "Using extmapper simplemap for cells of type $or.\n",
+            "Using extmapper simplemap for cells of type $xor.\n",
+            "Using extmapper simplemap for cells of type $not.\n",
+            "Using extmapper simplemap for cells of type $logic_not.\n",
+            "Running \"alumacc\" on wrapper $extern:wrap:$neg:A_SIGNED=0:A_WIDTH=4:Y_WIDTH=4:394426c56d1a028ba8fdd5469b163e04011def47.\n",
+            "Using template $extern:wrap:$neg:A_SIGNED=0:A_WIDTH=4:Y_WIDTH=4:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$neg:A_SIGNED=0:A_WIDTH=4:Y_WIDTH=4:394426c56d1a028ba8fdd5469b163e04011def47.\n",
+            "Using extmapper simplemap for cells of type $eq.\n",
+            "Using template $paramod$a13703aa027da371a1931fc542d213d7de559b19\\_90_pmux for cells of type $pmux.\n",
+            "Using template $paramod\\_90_lcu\\WIDTH=32'00000000000000000000000000000100 for cells of type $lcu.\n",
+            "Using extmapper simplemap for cells of type $pos.\n",
+            "Using template $paramod$6b90a16b6f3b57b9c9d958838204f952a01dc262\\_90_alu for cells of type $alu.\n",
+            "No more expansions possible.\n",
+            "\n",
+            "5.21. Executing OPT pass (performing simple optimizations).\n",
+            "\n",
+            "5.21.1. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module alu.\n",
+            "\n",
+            "5.21.2. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\alu'.\n",
+            "Removed a total of 10 cells.\n",
+            "\n",
+            "5.21.3. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "5.21.4. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\alu..\n",
+            "Removed 8 unused cells and 118 unused wires.\n",
+            "\n",
+            "5.21.5. Finished fast OPT passes.\n",
+            "\n",
+            "5.22. Executing ABC pass (technology mapping using ABC).\n",
+            "\n",
+            "5.22.1. Extracting gate netlist of module `\\alu' to `<abc-temp-dir>/input.blif'..\n",
+            "Extracted 126 gates and 138 wires to a netlist network with 11 inputs and 5 outputs.\n",
+            "\n",
+            "5.22.1.1. Executing ABC.\n",
+            "Running ABC command: <yosys-exe-dir>/yosys-abc -s -f <abc-temp-dir>/abc.script 2>&1\n",
+            "ABC: ABC command line: \"source <abc-temp-dir>/abc.script\".\n",
+            "ABC: \n",
+            "ABC: + read_blif <abc-temp-dir>/input.blif \n",
+            "ABC: + read_library <abc-temp-dir>/stdcells.genlib \n",
+            "ABC: Entered genlib library with 13 gates from file \"<abc-temp-dir>/stdcells.genlib\".\n",
+            "ABC: + strash \n",
+            "ABC: + dretime \n",
+            "ABC: + map \n",
+            "ABC: + write_blif <abc-temp-dir>/output.blif \n",
+            "\n",
+            "5.22.1.2. Re-integrating ABC results.\n",
+            "ABC RESULTS:            ANDNOT cells:       41\n",
+            "ABC RESULTS:               MUX cells:        7\n",
+            "ABC RESULTS:              NAND cells:        6\n",
+            "ABC RESULTS:               NOR cells:        7\n",
+            "ABC RESULTS:               NOT cells:        5\n",
+            "ABC RESULTS:                OR cells:       17\n",
+            "ABC RESULTS:             ORNOT cells:        3\n",
+            "ABC RESULTS:              XNOR cells:        5\n",
+            "ABC RESULTS:               XOR cells:        8\n",
+            "ABC RESULTS:        internal signals:      122\n",
+            "ABC RESULTS:           input signals:       11\n",
+            "ABC RESULTS:          output signals:        5\n",
+            "Removing temp directory.\n",
+            "\n",
+            "5.23. Executing OPT pass (performing simple optimizations).\n",
+            "\n",
+            "5.23.1. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module alu.\n",
+            "\n",
+            "5.23.2. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\alu'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "5.23.3. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "5.23.4. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\alu..\n",
+            "Removed 0 unused cells and 60 unused wires.\n",
+            "\n",
+            "5.23.5. Finished fast OPT passes.\n",
+            "\n",
+            "5.24. Executing HIERARCHY pass (managing design hierarchy).\n",
+            "\n",
+            "5.24.1. Analyzing design hierarchy..\n",
+            "Top module:  \\alu\n",
+            "\n",
+            "5.24.2. Analyzing design hierarchy..\n",
+            "Top module:  \\alu\n",
+            "Removed 0 unused modules.\n",
+            "\n",
+            "5.25. Printing statistics.\n",
+            "\n",
+            "=== alu ===\n",
+            "\n",
+            "   Number of wires:                 99\n",
+            "   Number of wire bits:            110\n",
+            "   Number of public wires:           5\n",
+            "   Number of public wire bits:      16\n",
+            "   Number of memories:               0\n",
+            "   Number of memory bits:            0\n",
+            "   Number of processes:              0\n",
+            "   Number of cells:                 99\n",
+            "     $_ANDNOT_                      41\n",
+            "     $_MUX_                          7\n",
+            "     $_NAND_                         6\n",
+            "     $_NOR_                          7\n",
+            "     $_NOT_                          5\n",
+            "     $_ORNOT_                        3\n",
+            "     $_OR_                          17\n",
+            "     $_XNOR_                         5\n",
+            "     $_XOR_                          8\n",
+            "\n",
+            "5.26. Executing CHECK pass (checking for obvious problems).\n",
+            "Checking module alu...\n",
+            "Found and reported 0 problems.\n",
+            "\n",
+            "yosys> \n",
+            "6. Executing ABC pass (technology mapping using ABC).\n",
+            "\n",
+            "6.1. Extracting gate netlist of module `\\alu' to `<abc-temp-dir>/input.blif'..\n",
+            "Extracted 99 gates and 110 wires to a netlist network with 11 inputs and 5 outputs.\n",
+            "\n",
+            "6.1.1. Executing ABC.\n",
+            "Running ABC command: <yosys-exe-dir>/yosys-abc -s -f <abc-temp-dir>/abc.script 2>&1\n",
+            "ABC: ABC command line: \"source <abc-temp-dir>/abc.script\".\n",
+            "ABC: \n",
+            "ABC: + read_blif <abc-temp-dir>/input.blif \n",
+            "ABC: + read_lib -w /content/74xx-liberty/74ac.lib \n",
+            "ABC: Parsing finished successfully.  Parsing time =     0.00 sec\n",
+            "ABC: Warning: Templates are not defined.\n",
+            "ABC: Scl_LibertyReadGenlib() skipped sequential cell \"74AC74_2x1DFFSR\".\n",
+            "ABC: Scl_LibertyReadGenlib() skipped sequential cell \"74AC273_8x1DFFR\".\n",
+            "ABC: Scl_LibertyReadGenlib() skipped sequential cell \"74AC374_8x1DFF\".\n",
+            "ABC: Library \"74series\" from \"/content/74xx-liberty/74ac.lib\" has 13 cells (3 skipped: 3 seq; 0 tri-state; 0 no func; 0 dont_use).  Time =     0.00 sec\n",
+            "ABC: Memory =    0.02 MB. Time =     0.00 sec\n",
+            "ABC: + strash \n",
+            "ABC: + ifraig \n",
+            "ABC: + scorr \n",
+            "ABC: Warning: The network is combinational (run \"fraig\" or \"fraig_sweep\").\n",
+            "ABC: + dc2 \n",
+            "ABC: + dretime \n",
+            "ABC: + strash \n",
+            "ABC: + &get -n \n",
+            "ABC: + &dch -f \n",
+            "ABC: + &nf \n",
+            "ABC: + &put \n",
+            "ABC: + write_blif <abc-temp-dir>/output.blif \n",
+            "\n",
+            "6.1.2. Re-integrating ABC results.\n",
+            "ABC RESULTS:   \\74AC00_4x1NAND2 cells:       11\n",
+            "ABC RESULTS:   \\74AC02_4x1NOR2 cells:       15\n",
+            "ABC RESULTS:    \\74AC04_6x1NOT cells:        5\n",
+            "ABC RESULTS:   \\74AC08_4x1AND2 cells:        8\n",
+            "ABC RESULTS:   \\74AC10_3x1NAND3 cells:        6\n",
+            "ABC RESULTS:   \\74AC20_2x1NAND4 cells:        3\n",
+            "ABC RESULTS:   \\74AC257_4x1MUX2 cells:        3\n",
+            "ABC RESULTS:    \\74AC32_4x1OR2 cells:       15\n",
+            "ABC RESULTS:   \\74AC86_4x1XOR2 cells:       10\n",
+            "ABC RESULTS:        internal signals:       94\n",
+            "ABC RESULTS:           input signals:       11\n",
+            "ABC RESULTS:          output signals:        5\n",
+            "Removing temp directory.\n",
+            "\n",
+            "yosys> \n",
+            "7. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).\n",
+            "  cell 74AC374_8x1DFF (noninv, pins=3, area=2.06) is a direct match for cell type $_DFF_P_.\n",
+            "  cell 74AC273_8x1DFFR (noninv, pins=4, area=2.25) is a direct match for cell type $_DFF_PN0_.\n",
+            "  cell 74AC74_2x1DFFSR (noninv, pins=5, area=5.00) is a direct match for cell type $_DFFSR_PNN_.\n",
+            "  final dff cell mappings:\n",
+            "    unmapped dff cell: $_DFF_N_\n",
+            "    \\74AC374_8x1DFF _DFF_P_ (.CLK( C), .D( D), .Q( Q));\n",
+            "    unmapped dff cell: $_DFF_NN0_\n",
+            "    unmapped dff cell: $_DFF_NN1_\n",
+            "    unmapped dff cell: $_DFF_NP0_\n",
+            "    unmapped dff cell: $_DFF_NP1_\n",
+            "    \\74AC273_8x1DFFR _DFF_PN0_ (.C( R), .CLK( C), .D( D), .Q( Q));\n",
+            "    unmapped dff cell: $_DFF_PN1_\n",
+            "    unmapped dff cell: $_DFF_PP0_\n",
+            "    unmapped dff cell: $_DFF_PP1_\n",
+            "    unmapped dff cell: $_DFFSR_NNN_\n",
+            "    unmapped dff cell: $_DFFSR_NNP_\n",
+            "    unmapped dff cell: $_DFFSR_NPN_\n",
+            "    unmapped dff cell: $_DFFSR_NPP_\n",
+            "    \\74AC74_2x1DFFSR _DFFSR_PNN_ (.C( R), .CLK( C), .D( D), .P( S), .Q( Q));\n",
+            "    unmapped dff cell: $_DFFSR_PNP_\n",
+            "    unmapped dff cell: $_DFFSR_PPN_\n",
+            "    unmapped dff cell: $_DFFSR_PPP_\n",
+            "\n",
+            "7.1. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).\n",
+            "Mapping DFF cells in module `\\alu':\n",
+            "\n",
+            "yosys> \n",
+            "yosys> \n",
+            "8. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\alu..\n",
+            "Removed 0 unused cells and 110 unused wires.\n",
+            "\n",
+            "yosys> \n",
+            "9. Generating Graphviz representation of design.\n",
+            "Writing dot description to `synth_74.dot'.\n",
+            "Dumping module alu to page 1.\n",
+            "\n",
+            "yosys> \n",
+            "10. Printing statistics.\n",
+            "\n",
+            "=== alu ===\n",
+            "\n",
+            "   Number of wires:                 76\n",
+            "   Number of wire bits:             87\n",
+            "   Number of public wires:           5\n",
+            "   Number of public wire bits:      16\n",
+            "   Number of memories:               0\n",
+            "   Number of memory bits:            0\n",
+            "   Number of processes:              0\n",
+            "   Number of cells:                 76\n",
+            "     \\74AC00_4x1NAND2               11\n",
+            "     \\74AC02_4x1NOR2                15\n",
+            "     \\74AC04_6x1NOT                  5\n",
+            "     \\74AC08_4x1AND2                 8\n",
+            "     \\74AC10_3x1NAND3                6\n",
+            "     \\74AC20_2x1NAND4                3\n",
+            "     \\74AC257_4x1MUX2                3\n",
+            "     \\74AC32_4x1OR2                 15\n",
+            "     \\74AC86_4x1XOR2                10\n",
+            "\n",
+            "   Chip area for module '\\alu': 238.000000\n",
+            "\n",
+            "\n",
+            "yosys> exit\n"
+          ]
+        }
+      ]
+    },
+    {
+      "cell_type": "code",
+      "metadata": {
+        "colab": {
+          "base_uri": "https://localhost:8080/",
+          "height": 1000
+        },
+        "id": "JNsm6Rxa0Beu",
+        "outputId": "87816bb3-012c-462a-ee9f-6954940f60b7"
+      },
+      "source": [
+        "import graphviz\n",
+        "graphviz.Source.from_file('synth_74.dot')"
+      ],
+      "execution_count": 47,
+      "outputs": [
+        {
+          "output_type": "execute_result",
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+            "text/plain": [
+              "<graphviz.sources.Source at 0x79c788742090>"
+            ]
+          },
+          "metadata": {},
+          "execution_count": 47
+        }
+      ]
+    },
+    {
+      "cell_type": "markdown",
+      "metadata": {
+        "id": "fa0ed463"
+      },
+      "source": [
+        "## nextpnr and SVG FPGA floormap\n",
+        "I will now proceed with the following steps:\n",
+        "\n",
+        "1. Synthesize the `alu.v` design using Yosys and generate an intermediate JSON file (`alu.json`) for nextpnr.\n",
+        "2. Use `nextpnr-ice40` to perform place and route on the `alu.json` file, targeting the `ICE40UP5K` architecture. This will generate an `.asc` file and an SVG floorplan (`alu_placed.svg`).\n",
+        "3. Display the generated `alu_placed.svg` floorplan using `IPython.display.SVG`.\n",
+        "4. Confirm the successful placement and routing of the ALU and present the generated floorplan.\n",
+        "\n",
+        "Starting with the first step: Synthesizing `alu.v` to `alu.json`.\n",
+        "```python\n",
+        "!miniconda-pnr/bin/yosys -p 'synth_ice40 -top alu -json alu.json' alu.v\n",
+        "```"
+      ]
+    },
+    {
+      "cell_type": "markdown",
+      "metadata": {
+        "id": "0e3f222e"
+      },
+      "source": [
+        "### Synthesize ALU to JSON\n",
+        "\n",
+        "### Subtask:\n",
+        "Synthesize the `alu.v` design using Yosys and generate an intermediate JSON file (`alu.json`) for nextpnr.\n"
+      ]
+    },
+    {
+      "cell_type": "markdown",
+      "metadata": {
+        "id": "6943a7c9"
+      },
+      "source": [
+        "**Reasoning**:\n",
+        "The user wants to synthesize the `alu.v` design using Yosys to generate a JSON file for nextpnr. The provided instruction includes the exact command to achieve this.\n",
+        "\n"
+      ]
+    },
+    {
+      "cell_type": "code",
+      "metadata": {
+        "colab": {
+          "base_uri": "https://localhost:8080/"
+        },
+        "id": "4b97a668",
+        "outputId": "cd140ec2-8103-4a94-e275-a8b0adfef88a"
+      },
+      "source": [
+        "!miniconda-pnr/bin/yosys -p 'synth_ice40 -top alu -json alu.json' alu.v"
+      ],
+      "execution_count": 49,
+      "outputs": [
+        {
+          "output_type": "stream",
+          "name": "stdout",
+          "text": [
+            "\n",
+            " /----------------------------------------------------------------------------\\\n",
+            " |                                                                            |\n",
+            " |  yosys -- Yosys Open SYnthesis Suite                                       |\n",
+            " |                                                                            |\n",
+            " |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |\n",
+            " |                                                                            |\n",
+            " |  Permission to use, copy, modify, and/or distribute this software for any  |\n",
+            " |  purpose with or without fee is hereby granted, provided that the above    |\n",
+            " |  copyright notice and this permission notice appear in all copies.         |\n",
+            " |                                                                            |\n",
+            " |  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |\n",
+            " |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |\n",
+            " |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |\n",
+            " |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |\n",
+            " |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |\n",
+            " |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |\n",
+            " |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |\n",
+            " |                                                                            |\n",
+            " \\----------------------------------------------------------------------------/\n",
+            "\n",
+            " Yosys 0.13+37 (git sha1 958c3a46a, x86_64-conda_cos6-linux-gnu-gcc 1.24.0.133_b0863d8_dirty -fvisibility-inlines-hidden -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -fdebug-prefix-map=/home/runner/work/conda-eda/conda-eda/workdir/conda-env/conda-bld/yosys_1644188991550/work=/usr/local/src/conda/yosys-0.13_39_g958c3a46a -fdebug-prefix-map=/content/miniconda-pnr=/usr/local/src/conda-prefix -fPIC -Os -fno-merge-constants)\n",
+            "\n",
+            "\n",
+            "-- Parsing `alu.v' using frontend ` -vlog2k' --\n",
+            "\n",
+            "1. Executing Verilog-2005 frontend: alu.v\n",
+            "Parsing Verilog input from `alu.v' to AST representation.\n",
+            "Storing AST representation for module `$abstract\\alu'.\n",
+            "Successfully finished Verilog frontend.\n",
+            "\n",
+            "-- Running command `synth_ice40 -top alu -json alu.json' --\n",
+            "\n",
+            "2. Executing SYNTH_ICE40 pass.\n",
+            "\n",
+            "2.1. Executing Verilog-2005 frontend: /content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v\n",
+            "Parsing Verilog input from `/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v' to AST representation.\n",
+            "Generating RTLIL representation for module `\\SB_IO'.\n",
+            "Generating RTLIL representation for module `\\SB_GB_IO'.\n",
+            "Generating RTLIL representation for module `\\SB_GB'.\n",
+            "Generating RTLIL representation for module `\\SB_LUT4'.\n",
+            "Generating RTLIL representation for module `\\SB_CARRY'.\n",
+            "Generating RTLIL representation for module `\\SB_DFF'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFE'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFSR'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFR'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFSS'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFS'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFESR'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFER'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFESS'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFES'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFN'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFNE'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFNSR'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFNR'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFNSS'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFNS'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFNESR'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFNER'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFNESS'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFNES'.\n",
+            "Generating RTLIL representation for module `\\SB_RAM40_4K'.\n",
+            "Generating RTLIL representation for module `\\SB_RAM40_4KNR'.\n",
+            "Generating RTLIL representation for module `\\SB_RAM40_4KNW'.\n",
+            "Generating RTLIL representation for module `\\SB_RAM40_4KNRNW'.\n",
+            "Generating RTLIL representation for module `\\ICESTORM_LC'.\n",
+            "Generating RTLIL representation for module `\\SB_PLL40_CORE'.\n",
+            "Generating RTLIL representation for module `\\SB_PLL40_PAD'.\n",
+            "Generating RTLIL representation for module `\\SB_PLL40_2_PAD'.\n",
+            "Generating RTLIL representation for module `\\SB_PLL40_2F_CORE'.\n",
+            "Generating RTLIL representation for module `\\SB_PLL40_2F_PAD'.\n",
+            "Generating RTLIL representation for module `\\SB_WARMBOOT'.\n",
+            "Generating RTLIL representation for module `\\SB_SPRAM256KA'.\n",
+            "Generating RTLIL representation for module `\\SB_HFOSC'.\n",
+            "Generating RTLIL representation for module `\\SB_LFOSC'.\n",
+            "Generating RTLIL representation for module `\\SB_RGBA_DRV'.\n",
+            "Generating RTLIL representation for module `\\SB_LED_DRV_CUR'.\n",
+            "Generating RTLIL representation for module `\\SB_RGB_DRV'.\n",
+            "Generating RTLIL representation for module `\\SB_I2C'.\n",
+            "Generating RTLIL representation for module `\\SB_SPI'.\n",
+            "Generating RTLIL representation for module `\\SB_LEDDA_IP'.\n",
+            "Generating RTLIL representation for module `\\SB_FILTER_50NS'.\n",
+            "Generating RTLIL representation for module `\\SB_IO_I3C'.\n",
+            "Generating RTLIL representation for module `\\SB_IO_OD'.\n",
+            "Generating RTLIL representation for module `\\SB_MAC16'.\n",
+            "Generating RTLIL representation for module `\\ICESTORM_RAM'.\n",
+            "Successfully finished Verilog frontend.\n",
+            "\n",
+            "2.2. Executing HIERARCHY pass (managing design hierarchy).\n",
+            "\n",
+            "2.3. Executing AST frontend in derive mode using pre-parsed AST for module `\\alu'.\n",
+            "Generating RTLIL representation for module `\\alu'.\n",
+            "\n",
+            "2.3.1. Analyzing design hierarchy..\n",
+            "Top module:  \\alu\n",
+            "\n",
+            "2.3.2. Analyzing design hierarchy..\n",
+            "Top module:  \\alu\n",
+            "Removing unused module `$abstract\\alu'.\n",
+            "Removed 1 unused modules.\n",
+            "\n",
+            "2.4. Executing PROC pass (convert processes to netlists).\n",
+            "\n",
+            "2.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).\n",
+            "Cleaned up 0 empty switches.\n",
+            "\n",
+            "2.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1386$241 in module SB_DFFNES.\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1328$234 in module SB_DFFNESS.\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1251$230 in module SB_DFFNER.\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1193$223 in module SB_DFFNESR.\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1122$220 in module SB_DFFNS.\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1072$217 in module SB_DFFNSS.\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1001$214 in module SB_DFFNR.\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:951$211 in module SB_DFFNSR.\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:789$203 in module SB_DFFES.\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:731$196 in module SB_DFFESS.\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:654$192 in module SB_DFFER.\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:596$185 in module SB_DFFESR.\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:525$182 in module SB_DFFS.\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:475$179 in module SB_DFFSS.\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:404$176 in module SB_DFFR.\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:354$173 in module SB_DFFSR.\n",
+            "Marked 2 switch rules as full_case in process $proc$alu.v:10$381 in module alu.\n",
+            "Removed a total of 0 dead cases.\n",
+            "\n",
+            "2.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).\n",
+            "Removed 8 redundant assignments.\n",
+            "Promoted 24 assignments to connections.\n",
+            "\n",
+            "2.4.4. Executing PROC_INIT pass (extract init attributes).\n",
+            "Found init rule in `\\SB_DFFNES.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$244'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFNESS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$240'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFNER.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$233'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFNESR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$229'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFNS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$222'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFNSS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$219'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFNR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$216'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFNSR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$213'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFNE.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$210'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFN.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$208'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFES.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$206'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFESS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$202'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFER.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$195'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFESR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$191'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$184'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFSS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$181'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$178'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFSR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$175'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFE.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$172'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFF.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$170'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "\n",
+            "2.4.5. Executing PROC_ARST pass (detect async resets in processes).\n",
+            "Found async reset \\S in `\\SB_DFFNES.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1386$241'.\n",
+            "Found async reset \\R in `\\SB_DFFNER.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1251$230'.\n",
+            "Found async reset \\S in `\\SB_DFFNS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1122$220'.\n",
+            "Found async reset \\R in `\\SB_DFFNR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1001$214'.\n",
+            "Found async reset \\S in `\\SB_DFFES.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:789$203'.\n",
+            "Found async reset \\R in `\\SB_DFFER.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:654$192'.\n",
+            "Found async reset \\S in `\\SB_DFFS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:525$182'.\n",
+            "Found async reset \\R in `\\SB_DFFR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:404$176'.\n",
+            "\n",
+            "2.4.6. Executing PROC_MUX pass (convert decision trees to multiplexers).\n",
+            "Creating decoders for process `\\SB_DFFNES.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$244'.\n",
+            "Creating decoders for process `\\SB_DFFNES.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1386$241'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFNESS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$240'.\n",
+            "Creating decoders for process `\\SB_DFFNESS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1328$234'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFNER.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$233'.\n",
+            "Creating decoders for process `\\SB_DFFNER.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1251$230'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFNESR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$229'.\n",
+            "Creating decoders for process `\\SB_DFFNESR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1193$223'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFNS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$222'.\n",
+            "Creating decoders for process `\\SB_DFFNS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1122$220'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFNSS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$219'.\n",
+            "Creating decoders for process `\\SB_DFFNSS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1072$217'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFNR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$216'.\n",
+            "Creating decoders for process `\\SB_DFFNR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1001$214'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFNSR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$213'.\n",
+            "Creating decoders for process `\\SB_DFFNSR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:951$211'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFNE.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$210'.\n",
+            "Creating decoders for process `\\SB_DFFNE.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:906$209'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFN.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$208'.\n",
+            "Creating decoders for process `\\SB_DFFN.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:868$207'.\n",
+            "Creating decoders for process `\\SB_DFFES.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$206'.\n",
+            "Creating decoders for process `\\SB_DFFES.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:789$203'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFESS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$202'.\n",
+            "Creating decoders for process `\\SB_DFFESS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:731$196'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFER.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$195'.\n",
+            "Creating decoders for process `\\SB_DFFER.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:654$192'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFESR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$191'.\n",
+            "Creating decoders for process `\\SB_DFFESR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:596$185'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$184'.\n",
+            "Creating decoders for process `\\SB_DFFS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:525$182'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFSS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$181'.\n",
+            "Creating decoders for process `\\SB_DFFSS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:475$179'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$178'.\n",
+            "Creating decoders for process `\\SB_DFFR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:404$176'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFSR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$175'.\n",
+            "Creating decoders for process `\\SB_DFFSR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:354$173'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFE.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$172'.\n",
+            "Creating decoders for process `\\SB_DFFE.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:309$171'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFF.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$170'.\n",
+            "Creating decoders for process `\\SB_DFF.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:271$169'.\n",
+            "Creating decoders for process `\\alu.$proc$alu.v:10$381'.\n",
+            "     1/2: $1\\zero_flag[0:0]\n",
+            "     2/2: $1\\result[3:0]\n",
+            "\n",
+            "2.4.7. Executing PROC_DLATCH pass (convert process syncs to latches).\n",
+            "No latch inferred for signal `\\alu.\\result' from process `\\alu.$proc$alu.v:10$381'.\n",
+            "No latch inferred for signal `\\alu.\\zero_flag' from process `\\alu.$proc$alu.v:10$381'.\n",
+            "\n",
+            "2.4.8. Executing PROC_DFF pass (convert process syncs to FFs).\n",
+            "Creating register for signal `\\SB_DFFNES.\\Q' using process `\\SB_DFFNES.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1386$241'.\n",
+            "  created $adff cell `$procdff$445' with negative edge clock and positive level reset.\n",
+            "Creating register for signal `\\SB_DFFNESS.\\Q' using process `\\SB_DFFNESS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1328$234'.\n",
+            "  created $dff cell `$procdff$446' with negative edge clock.\n",
+            "Creating register for signal `\\SB_DFFNER.\\Q' using process `\\SB_DFFNER.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1251$230'.\n",
+            "  created $adff cell `$procdff$447' with negative edge clock and positive level reset.\n",
+            "Creating register for signal `\\SB_DFFNESR.\\Q' using process `\\SB_DFFNESR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1193$223'.\n",
+            "  created $dff cell `$procdff$448' with negative edge clock.\n",
+            "Creating register for signal `\\SB_DFFNS.\\Q' using process `\\SB_DFFNS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1122$220'.\n",
+            "  created $adff cell `$procdff$449' with negative edge clock and positive level reset.\n",
+            "Creating register for signal `\\SB_DFFNSS.\\Q' using process `\\SB_DFFNSS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1072$217'.\n",
+            "  created $dff cell `$procdff$450' with negative edge clock.\n",
+            "Creating register for signal `\\SB_DFFNR.\\Q' using process `\\SB_DFFNR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1001$214'.\n",
+            "  created $adff cell `$procdff$451' with negative edge clock and positive level reset.\n",
+            "Creating register for signal `\\SB_DFFNSR.\\Q' using process `\\SB_DFFNSR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:951$211'.\n",
+            "  created $dff cell `$procdff$452' with negative edge clock.\n",
+            "Creating register for signal `\\SB_DFFNE.\\Q' using process `\\SB_DFFNE.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:906$209'.\n",
+            "  created $dff cell `$procdff$453' with negative edge clock.\n",
+            "Creating register for signal `\\SB_DFFN.\\Q' using process `\\SB_DFFN.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:868$207'.\n",
+            "  created $dff cell `$procdff$454' with negative edge clock.\n",
+            "Creating register for signal `\\SB_DFFES.\\Q' using process `\\SB_DFFES.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:789$203'.\n",
+            "  created $adff cell `$procdff$455' with positive edge clock and positive level reset.\n",
+            "Creating register for signal `\\SB_DFFESS.\\Q' using process `\\SB_DFFESS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:731$196'.\n",
+            "  created $dff cell `$procdff$456' with positive edge clock.\n",
+            "Creating register for signal `\\SB_DFFER.\\Q' using process `\\SB_DFFER.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:654$192'.\n",
+            "  created $adff cell `$procdff$457' with positive edge clock and positive level reset.\n",
+            "Creating register for signal `\\SB_DFFESR.\\Q' using process `\\SB_DFFESR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:596$185'.\n",
+            "  created $dff cell `$procdff$458' with positive edge clock.\n",
+            "Creating register for signal `\\SB_DFFS.\\Q' using process `\\SB_DFFS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:525$182'.\n",
+            "  created $adff cell `$procdff$459' with positive edge clock and positive level reset.\n",
+            "Creating register for signal `\\SB_DFFSS.\\Q' using process `\\SB_DFFSS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:475$179'.\n",
+            "  created $dff cell `$procdff$460' with positive edge clock.\n",
+            "Creating register for signal `\\SB_DFFR.\\Q' using process `\\SB_DFFR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:404$176'.\n",
+            "  created $adff cell `$procdff$461' with positive edge clock and positive level reset.\n",
+            "Creating register for signal `\\SB_DFFSR.\\Q' using process `\\SB_DFFSR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:354$173'.\n",
+            "  created $dff cell `$procdff$462' with positive edge clock.\n",
+            "Creating register for signal `\\SB_DFFE.\\Q' using process `\\SB_DFFE.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:309$171'.\n",
+            "  created $dff cell `$procdff$463' with positive edge clock.\n",
+            "Creating register for signal `\\SB_DFF.\\Q' using process `\\SB_DFF.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:271$169'.\n",
+            "  created $dff cell `$procdff$464' with positive edge clock.\n",
+            "\n",
+            "2.4.9. Executing PROC_MEMWR pass (convert process memory writes to cells).\n",
+            "\n",
+            "2.4.10. Executing PROC_CLEAN pass (remove empty switches from decision trees).\n",
+            "Removing empty process `SB_DFFNES.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$244'.\n",
+            "Found and cleaned up 1 empty switch in `\\SB_DFFNES.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1386$241'.\n",
+            "Removing empty process `SB_DFFNES.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1386$241'.\n",
+            "Removing empty process `SB_DFFNESS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$240'.\n",
+            "Found and cleaned up 2 empty switches in `\\SB_DFFNESS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1328$234'.\n",
+            "Removing empty process `SB_DFFNESS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1328$234'.\n",
+            "Removing empty process `SB_DFFNER.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$233'.\n",
+            "Found and cleaned up 1 empty switch in `\\SB_DFFNER.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1251$230'.\n",
+            "Removing empty process `SB_DFFNER.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1251$230'.\n",
+            "Removing empty process `SB_DFFNESR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$229'.\n",
+            "Found and cleaned up 2 empty switches in `\\SB_DFFNESR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1193$223'.\n",
+            "Removing empty process `SB_DFFNESR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1193$223'.\n",
+            "Removing empty process `SB_DFFNS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$222'.\n",
+            "Removing empty process `SB_DFFNS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1122$220'.\n",
+            "Removing empty process `SB_DFFNSS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$219'.\n",
+            "Found and cleaned up 1 empty switch in `\\SB_DFFNSS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1072$217'.\n",
+            "Removing empty process `SB_DFFNSS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1072$217'.\n",
+            "Removing empty process `SB_DFFNR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$216'.\n",
+            "Removing empty process `SB_DFFNR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1001$214'.\n",
+            "Removing empty process `SB_DFFNSR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$213'.\n",
+            "Found and cleaned up 1 empty switch in `\\SB_DFFNSR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:951$211'.\n",
+            "Removing empty process `SB_DFFNSR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:951$211'.\n",
+            "Removing empty process `SB_DFFNE.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$210'.\n",
+            "Found and cleaned up 1 empty switch in `\\SB_DFFNE.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:906$209'.\n",
+            "Removing empty process `SB_DFFNE.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:906$209'.\n",
+            "Removing empty process `SB_DFFN.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$208'.\n",
+            "Removing empty process `SB_DFFN.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:868$207'.\n",
+            "Removing empty process `SB_DFFES.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$206'.\n",
+            "Found and cleaned up 1 empty switch in `\\SB_DFFES.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:789$203'.\n",
+            "Removing empty process `SB_DFFES.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:789$203'.\n",
+            "Removing empty process `SB_DFFESS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$202'.\n",
+            "Found and cleaned up 2 empty switches in `\\SB_DFFESS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:731$196'.\n",
+            "Removing empty process `SB_DFFESS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:731$196'.\n",
+            "Removing empty process `SB_DFFER.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$195'.\n",
+            "Found and cleaned up 1 empty switch in `\\SB_DFFER.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:654$192'.\n",
+            "Removing empty process `SB_DFFER.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:654$192'.\n",
+            "Removing empty process `SB_DFFESR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$191'.\n",
+            "Found and cleaned up 2 empty switches in `\\SB_DFFESR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:596$185'.\n",
+            "Removing empty process `SB_DFFESR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:596$185'.\n",
+            "Removing empty process `SB_DFFS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$184'.\n",
+            "Removing empty process `SB_DFFS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:525$182'.\n",
+            "Removing empty process `SB_DFFSS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$181'.\n",
+            "Found and cleaned up 1 empty switch in `\\SB_DFFSS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:475$179'.\n",
+            "Removing empty process `SB_DFFSS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:475$179'.\n",
+            "Removing empty process `SB_DFFR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$178'.\n",
+            "Removing empty process `SB_DFFR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:404$176'.\n",
+            "Removing empty process `SB_DFFSR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$175'.\n",
+            "Found and cleaned up 1 empty switch in `\\SB_DFFSR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:354$173'.\n",
+            "Removing empty process `SB_DFFSR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:354$173'.\n",
+            "Removing empty process `SB_DFFE.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$172'.\n",
+            "Found and cleaned up 1 empty switch in `\\SB_DFFE.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:309$171'.\n",
+            "Removing empty process `SB_DFFE.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:309$171'.\n",
+            "Removing empty process `SB_DFF.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$170'.\n",
+            "Removing empty process `SB_DFF.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:271$169'.\n",
+            "Found and cleaned up 2 empty switches in `\\alu.$proc$alu.v:10$381'.\n",
+            "Removing empty process `alu.$proc$alu.v:10$381'.\n",
+            "Cleaned up 20 empty switches.\n",
+            "\n",
+            "2.4.11. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module alu.\n",
+            "\n",
+            "2.5. Executing FLATTEN pass (flatten design).\n",
+            "\n",
+            "2.6. Executing TRIBUF pass.\n",
+            "\n",
+            "2.7. Executing DEMINOUT pass (demote inout ports to input or output).\n",
+            "\n",
+            "2.8. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module alu.\n",
+            "\n",
+            "2.9. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\alu..\n",
+            "Removed 0 unused cells and 7 unused wires.\n",
+            "\n",
+            "2.10. Executing CHECK pass (checking for obvious problems).\n",
+            "Checking module alu...\n",
+            "Found and reported 0 problems.\n",
+            "\n",
+            "2.11. Executing OPT pass (performing simple optimizations).\n",
+            "\n",
+            "2.11.1. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module alu.\n",
+            "\n",
+            "2.11.2. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\alu'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "2.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n",
+            "Running muxtree optimizer on module \\alu..\n",
+            "  Creating internal representation of mux trees.\n",
+            "  Evaluating internal representation of mux trees.\n",
+            "  Analyzing evaluation results.\n",
+            "Removed 0 multiplexer ports.\n",
+            "\n",
+            "2.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n",
+            "  Optimizing cells in module \\alu.\n",
+            "Performed a total of 0 changes.\n",
+            "\n",
+            "2.11.5. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\alu'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "2.11.6. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "2.11.7. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\alu..\n",
+            "\n",
+            "2.11.8. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module alu.\n",
+            "\n",
+            "2.11.9. Finished OPT passes. (There is nothing left to do.)\n",
+            "\n",
+            "2.12. Executing FSM pass (extract and optimize FSM).\n",
+            "\n",
+            "2.12.1. Executing FSM_DETECT pass (finding FSMs in design).\n",
+            "\n",
+            "2.12.2. Executing FSM_EXTRACT pass (extracting FSM from design).\n",
+            "\n",
+            "2.12.3. Executing FSM_OPT pass (simple optimizations of FSMs).\n",
+            "\n",
+            "2.12.4. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\alu..\n",
+            "\n",
+            "2.12.5. Executing FSM_OPT pass (simple optimizations of FSMs).\n",
+            "\n",
+            "2.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).\n",
+            "\n",
+            "2.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells).\n",
+            "\n",
+            "2.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic).\n",
+            "\n",
+            "2.13. Executing OPT pass (performing simple optimizations).\n",
+            "\n",
+            "2.13.1. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module alu.\n",
+            "\n",
+            "2.13.2. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\alu'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "2.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n",
+            "Running muxtree optimizer on module \\alu..\n",
+            "  Creating internal representation of mux trees.\n",
+            "  Evaluating internal representation of mux trees.\n",
+            "  Analyzing evaluation results.\n",
+            "Removed 0 multiplexer ports.\n",
+            "\n",
+            "2.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n",
+            "  Optimizing cells in module \\alu.\n",
+            "Performed a total of 0 changes.\n",
+            "\n",
+            "2.13.5. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\alu'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "2.13.6. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "2.13.7. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\alu..\n",
+            "\n",
+            "2.13.8. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module alu.\n",
+            "\n",
+            "2.13.9. Finished OPT passes. (There is nothing left to do.)\n",
+            "\n",
+            "2.14. Executing WREDUCE pass (reducing word size of cells).\n",
+            "Removed top 1 bits (of 3) from port B of cell alu.$procmux$441_CMP0 ($eq).\n",
+            "Removed top 1 bits (of 3) from port B of cell alu.$procmux$442_CMP0 ($eq).\n",
+            "Removed top 2 bits (of 3) from port B of cell alu.$procmux$443_CMP0 ($eq).\n",
+            "\n",
+            "2.15. Executing PEEPOPT pass (run peephole optimizers).\n",
+            "\n",
+            "2.16. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\alu..\n",
+            "\n",
+            "2.17. Executing SHARE pass (SAT-based resource sharing).\n",
+            "\n",
+            "2.18. Executing TECHMAP pass (map to technology primitives).\n",
+            "\n",
+            "2.18.1. Executing Verilog-2005 frontend: /content/miniconda-pnr/bin/../share/yosys/cmp2lut.v\n",
+            "Parsing Verilog input from `/content/miniconda-pnr/bin/../share/yosys/cmp2lut.v' to AST representation.\n",
+            "Generating RTLIL representation for module `\\_90_lut_cmp_'.\n",
+            "Successfully finished Verilog frontend.\n",
+            "\n",
+            "2.18.2. Continuing TECHMAP pass.\n",
+            "No more expansions possible.\n",
+            "\n",
+            "2.19. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module alu.\n",
+            "\n",
+            "2.20. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\alu..\n",
+            "\n",
+            "2.21. Executing ALUMACC pass (create $alu and $macc cells).\n",
+            "Extracting $alu and $macc cells in module alu:\n",
+            "  creating $macc model for $add$alu.v:12$382 ($add).\n",
+            "  creating $macc model for $sub$alu.v:13$383 ($sub).\n",
+            "  creating $alu model for $macc $sub$alu.v:13$383.\n",
+            "  creating $alu model for $macc $add$alu.v:12$382.\n",
+            "  creating $alu cell for $add$alu.v:12$382: $auto$alumacc.cc:485:replace_alu$466\n",
+            "  creating $alu cell for $sub$alu.v:13$383: $auto$alumacc.cc:485:replace_alu$469\n",
+            "  created 2 $alu and 0 $macc cells.\n",
+            "\n",
+            "2.22. Executing OPT pass (performing simple optimizations).\n",
+            "\n",
+            "2.22.1. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module alu.\n",
+            "\n",
+            "2.22.2. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\alu'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "2.22.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n",
+            "Running muxtree optimizer on module \\alu..\n",
+            "  Creating internal representation of mux trees.\n",
+            "  Evaluating internal representation of mux trees.\n",
+            "  Analyzing evaluation results.\n",
+            "Removed 0 multiplexer ports.\n",
+            "\n",
+            "2.22.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n",
+            "  Optimizing cells in module \\alu.\n",
+            "Performed a total of 0 changes.\n",
+            "\n",
+            "2.22.5. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\alu'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "2.22.6. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "2.22.7. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\alu..\n",
+            "\n",
+            "2.22.8. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module alu.\n",
+            "\n",
+            "2.22.9. Finished OPT passes. (There is nothing left to do.)\n",
+            "\n",
+            "2.23. Executing MEMORY pass.\n",
+            "\n",
+            "2.23.1. Executing OPT_MEM pass (optimize memories).\n",
+            "Performed a total of 0 transformations.\n",
+            "\n",
+            "2.23.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).\n",
+            "Performed a total of 0 transformations.\n",
+            "\n",
+            "2.23.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).\n",
+            "\n",
+            "2.23.4. Executing MEMORY_DFF pass (merging $dff cells to $memrd).\n",
+            "\n",
+            "2.23.5. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\alu..\n",
+            "\n",
+            "2.23.6. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).\n",
+            "\n",
+            "2.23.7. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).\n",
+            "Performed a total of 0 transformations.\n",
+            "\n",
+            "2.23.8. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\alu..\n",
+            "\n",
+            "2.23.9. Executing MEMORY_COLLECT pass (generating $mem cells).\n",
+            "\n",
+            "2.24. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\alu..\n",
+            "\n",
+            "2.25. Executing MEMORY_BRAM pass (mapping $mem cells to block memories).\n",
+            "\n",
+            "2.26. Executing TECHMAP pass (map to technology primitives).\n",
+            "\n",
+            "2.26.1. Executing Verilog-2005 frontend: /content/miniconda-pnr/bin/../share/yosys/ice40/brams_map.v\n",
+            "Parsing Verilog input from `/content/miniconda-pnr/bin/../share/yosys/ice40/brams_map.v' to AST representation.\n",
+            "Generating RTLIL representation for module `\\$__ICE40_RAM4K'.\n",
+            "Generating RTLIL representation for module `\\$__ICE40_RAM4K_M0'.\n",
+            "Generating RTLIL representation for module `\\$__ICE40_RAM4K_M123'.\n",
+            "Successfully finished Verilog frontend.\n",
+            "\n",
+            "2.26.2. Continuing TECHMAP pass.\n",
+            "No more expansions possible.\n",
+            "\n",
+            "2.27. Executing ICE40_BRAMINIT pass.\n",
+            "\n",
+            "2.28. Executing OPT pass (performing simple optimizations).\n",
+            "\n",
+            "2.28.1. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module alu.\n",
+            "\n",
+            "2.28.2. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\alu'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "2.28.3. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "2.28.4. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\alu..\n",
+            "Removed 0 unused cells and 1 unused wires.\n",
+            "\n",
+            "2.28.5. Finished fast OPT passes.\n",
+            "\n",
+            "2.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).\n",
+            "\n",
+            "2.30. Executing OPT pass (performing simple optimizations).\n",
+            "\n",
+            "2.30.1. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module alu.\n",
+            "\n",
+            "2.30.2. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\alu'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "2.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n",
+            "Running muxtree optimizer on module \\alu..\n",
+            "  Creating internal representation of mux trees.\n",
+            "  Evaluating internal representation of mux trees.\n",
+            "  Analyzing evaluation results.\n",
+            "Removed 0 multiplexer ports.\n",
+            "\n",
+            "2.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n",
+            "  Optimizing cells in module \\alu.\n",
+            "Performed a total of 0 changes.\n",
+            "\n",
+            "2.30.5. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\alu'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "2.30.6. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "2.30.7. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\alu..\n",
+            "\n",
+            "2.30.8. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module alu.\n",
+            "\n",
+            "2.30.9. Finished OPT passes. (There is nothing left to do.)\n",
+            "\n",
+            "2.31. Executing ICE40_WRAPCARRY pass (wrap carries).\n",
+            "\n",
+            "2.32. Executing TECHMAP pass (map to technology primitives).\n",
+            "\n",
+            "2.32.1. Executing Verilog-2005 frontend: /content/miniconda-pnr/bin/../share/yosys/techmap.v\n",
+            "Parsing Verilog input from `/content/miniconda-pnr/bin/../share/yosys/techmap.v' to AST representation.\n",
+            "Generating RTLIL representation for module `\\_90_simplemap_bool_ops'.\n",
+            "Generating RTLIL representation for module `\\_90_simplemap_reduce_ops'.\n",
+            "Generating RTLIL representation for module `\\_90_simplemap_logic_ops'.\n",
+            "Generating RTLIL representation for module `\\_90_simplemap_compare_ops'.\n",
+            "Generating RTLIL representation for module `\\_90_simplemap_various'.\n",
+            "Generating RTLIL representation for module `\\_90_simplemap_registers'.\n",
+            "Generating RTLIL representation for module `\\_90_shift_ops_shr_shl_sshl_sshr'.\n",
+            "Generating RTLIL representation for module `\\_90_shift_shiftx'.\n",
+            "Generating RTLIL representation for module `\\_90_fa'.\n",
+            "Generating RTLIL representation for module `\\_90_lcu'.\n",
+            "Generating RTLIL representation for module `\\_90_alu'.\n",
+            "Generating RTLIL representation for module `\\_90_macc'.\n",
+            "Generating RTLIL representation for module `\\_90_alumacc'.\n",
+            "Generating RTLIL representation for module `\\$__div_mod_u'.\n",
+            "Generating RTLIL representation for module `\\$__div_mod_trunc'.\n",
+            "Generating RTLIL representation for module `\\_90_div'.\n",
+            "Generating RTLIL representation for module `\\_90_mod'.\n",
+            "Generating RTLIL representation for module `\\$__div_mod_floor'.\n",
+            "Generating RTLIL representation for module `\\_90_divfloor'.\n",
+            "Generating RTLIL representation for module `\\_90_modfloor'.\n",
+            "Generating RTLIL representation for module `\\_90_pow'.\n",
+            "Generating RTLIL representation for module `\\_90_pmux'.\n",
+            "Generating RTLIL representation for module `\\_90_demux'.\n",
+            "Generating RTLIL representation for module `\\_90_lut'.\n",
+            "Successfully finished Verilog frontend.\n",
+            "\n",
+            "2.32.2. Executing Verilog-2005 frontend: /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v\n",
+            "Parsing Verilog input from `/content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v' to AST representation.\n",
+            "Generating RTLIL representation for module `\\_80_ice40_alu'.\n",
+            "Successfully finished Verilog frontend.\n",
+            "\n",
+            "2.32.3. Continuing TECHMAP pass.\n",
+            "Using template $paramod$740b056ede97228d3eae64ea2fdc81f0a33e0fe7\\_80_ice40_alu for cells of type $alu.\n",
+            "Using extmapper simplemap for cells of type $and.\n",
+            "Using extmapper simplemap for cells of type $or.\n",
+            "Using extmapper simplemap for cells of type $xor.\n",
+            "Using extmapper simplemap for cells of type $not.\n",
+            "Using extmapper simplemap for cells of type $logic_not.\n",
+            "Using extmapper simplemap for cells of type $eq.\n",
+            "Using template $paramod$33afdd83bf3811dac2de7a968d39eea5718691bc\\_90_pmux for cells of type $pmux.\n",
+            "Using extmapper simplemap for cells of type $mux.\n",
+            "Using extmapper simplemap for cells of type $pos.\n",
+            "Using extmapper simplemap for cells of type $reduce_or.\n",
+            "No more expansions possible.\n",
+            "\n",
+            "2.33. Executing OPT pass (performing simple optimizations).\n",
+            "\n",
+            "2.33.1. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module alu.\n",
+            "\n",
+            "2.33.2. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\alu'.\n",
+            "Removed a total of 17 cells.\n",
+            "\n",
+            "2.33.3. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "2.33.4. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\alu..\n",
+            "Removed 4 unused cells and 85 unused wires.\n",
+            "\n",
+            "2.33.5. Finished fast OPT passes.\n",
+            "\n",
+            "2.34. Executing ICE40_OPT pass (performing simple optimizations).\n",
+            "\n",
+            "2.34.1. Running ICE40 specific optimizations.\n",
+            "\n",
+            "2.34.2. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module alu.\n",
+            "\n",
+            "2.34.3. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\alu'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "2.34.4. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "2.34.5. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\alu..\n",
+            "\n",
+            "2.34.6. Finished OPT passes. (There is nothing left to do.)\n",
+            "\n",
+            "2.35. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).\n",
+            "\n",
+            "2.36. Executing TECHMAP pass (map to technology primitives).\n",
+            "\n",
+            "2.36.1. Executing Verilog-2005 frontend: /content/miniconda-pnr/bin/../share/yosys/ice40/ff_map.v\n",
+            "Parsing Verilog input from `/content/miniconda-pnr/bin/../share/yosys/ice40/ff_map.v' to AST representation.\n",
+            "Generating RTLIL representation for module `\\$_DFF_N_'.\n",
+            "Generating RTLIL representation for module `\\$_DFF_P_'.\n",
+            "Generating RTLIL representation for module `\\$_DFFE_NP_'.\n",
+            "Generating RTLIL representation for module `\\$_DFFE_PP_'.\n",
+            "Generating RTLIL representation for module `\\$_DFF_NP0_'.\n",
+            "Generating RTLIL representation for module `\\$_DFF_NP1_'.\n",
+            "Generating RTLIL representation for module `\\$_DFF_PP0_'.\n",
+            "Generating RTLIL representation for module `\\$_DFF_PP1_'.\n",
+            "Generating RTLIL representation for module `\\$_DFFE_NP0P_'.\n",
+            "Generating RTLIL representation for module `\\$_DFFE_NP1P_'.\n",
+            "Generating RTLIL representation for module `\\$_DFFE_PP0P_'.\n",
+            "Generating RTLIL representation for module `\\$_DFFE_PP1P_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFF_NP0_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFF_NP1_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFF_PP0_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFF_PP1_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFFCE_NP0P_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFFCE_NP1P_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFFCE_PP0P_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFFCE_PP1P_'.\n",
+            "Successfully finished Verilog frontend.\n",
+            "\n",
+            "2.36.2. Continuing TECHMAP pass.\n",
+            "No more expansions possible.\n",
+            "\n",
+            "2.37. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module alu.\n",
+            "\n",
+            "2.38. Executing SIMPLEMAP pass (map simple cells to gate primitives).\n",
+            "\n",
+            "2.39. Executing ICE40_OPT pass (performing simple optimizations).\n",
+            "\n",
+            "2.39.1. Running ICE40 specific optimizations.\n",
+            "\n",
+            "2.39.2. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module alu.\n",
+            "\n",
+            "2.39.3. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\alu'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "2.39.4. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "2.39.5. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\alu..\n",
+            "\n",
+            "2.39.6. Rerunning OPT passes. (Removed registers in this run.)\n",
+            "\n",
+            "2.39.7. Running ICE40 specific optimizations.\n",
+            "\n",
+            "2.39.8. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module alu.\n",
+            "\n",
+            "2.39.9. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\alu'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "2.39.10. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "2.39.11. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\alu..\n",
+            "\n",
+            "2.39.12. Finished OPT passes. (There is nothing left to do.)\n",
+            "\n",
+            "2.40. Executing TECHMAP pass (map to technology primitives).\n",
+            "\n",
+            "2.40.1. Executing Verilog-2005 frontend: /content/miniconda-pnr/bin/../share/yosys/ice40/latches_map.v\n",
+            "Parsing Verilog input from `/content/miniconda-pnr/bin/../share/yosys/ice40/latches_map.v' to AST representation.\n",
+            "Generating RTLIL representation for module `\\$_DLATCH_N_'.\n",
+            "Generating RTLIL representation for module `\\$_DLATCH_P_'.\n",
+            "Successfully finished Verilog frontend.\n",
+            "\n",
+            "2.40.2. Continuing TECHMAP pass.\n",
+            "No more expansions possible.\n",
+            "\n",
+            "2.41. Executing ABC pass (technology mapping using ABC).\n",
+            "\n",
+            "2.41.1. Extracting gate netlist of module `\\alu' to `<abc-temp-dir>/input.blif'..\n",
+            "Extracted 107 gates and 126 wires to a netlist network with 19 inputs and 9 outputs.\n",
+            "\n",
+            "2.41.1.1. Executing ABC.\n",
+            "Running ABC command: <yosys-exe-dir>/yosys-abc -s -f <abc-temp-dir>/abc.script 2>&1\n",
+            "ABC: ABC command line: \"source <abc-temp-dir>/abc.script\".\n",
+            "ABC: \n",
+            "ABC: + read_blif <abc-temp-dir>/input.blif \n",
+            "ABC: + read_lut <abc-temp-dir>/lutdefs.txt \n",
+            "ABC: + strash \n",
+            "ABC: + ifraig \n",
+            "ABC: + scorr \n",
+            "ABC: Warning: The network is combinational (run \"fraig\" or \"fraig_sweep\").\n",
+            "ABC: + dc2 \n",
+            "ABC: + dretime \n",
+            "ABC: + strash \n",
+            "ABC: + dch -f \n",
+            "ABC: + if \n",
+            "ABC: + mfs2 \n",
+            "ABC: + lutpack -S 1 \n",
+            "ABC: + dress \n",
+            "ABC: Total number of equiv classes                =      29.\n",
+            "ABC: Participating nodes from both networks       =      63.\n",
+            "ABC: Participating nodes from the first network   =      28. (  84.85 % of nodes)\n",
+            "ABC: Participating nodes from the second network  =      35. ( 106.06 % of nodes)\n",
+            "ABC: Node pairs (any polarity)                    =      28. (  84.85 % of names can be moved)\n",
+            "ABC: Node pairs (same polarity)                   =      23. (  69.70 % of names can be moved)\n",
+            "ABC: Total runtime =     0.02 sec\n",
+            "ABC: + write_blif <abc-temp-dir>/output.blif \n",
+            "\n",
+            "2.41.1.2. Re-integrating ABC results.\n",
+            "ABC RESULTS:              $lut cells:       32\n",
+            "ABC RESULTS:        internal signals:       98\n",
+            "ABC RESULTS:           input signals:       19\n",
+            "ABC RESULTS:          output signals:        9\n",
+            "Removing temp directory.\n",
+            "\n",
+            "2.42. Executing ICE40_WRAPCARRY pass (wrap carries).\n",
+            "\n",
+            "2.43. Executing TECHMAP pass (map to technology primitives).\n",
+            "\n",
+            "2.43.1. Executing Verilog-2005 frontend: /content/miniconda-pnr/bin/../share/yosys/ice40/ff_map.v\n",
+            "Parsing Verilog input from `/content/miniconda-pnr/bin/../share/yosys/ice40/ff_map.v' to AST representation.\n",
+            "Generating RTLIL representation for module `\\$_DFF_N_'.\n",
+            "Generating RTLIL representation for module `\\$_DFF_P_'.\n",
+            "Generating RTLIL representation for module `\\$_DFFE_NP_'.\n",
+            "Generating RTLIL representation for module `\\$_DFFE_PP_'.\n",
+            "Generating RTLIL representation for module `\\$_DFF_NP0_'.\n",
+            "Generating RTLIL representation for module `\\$_DFF_NP1_'.\n",
+            "Generating RTLIL representation for module `\\$_DFF_PP0_'.\n",
+            "Generating RTLIL representation for module `\\$_DFF_PP1_'.\n",
+            "Generating RTLIL representation for module `\\$_DFFE_NP0P_'.\n",
+            "Generating RTLIL representation for module `\\$_DFFE_NP1P_'.\n",
+            "Generating RTLIL representation for module `\\$_DFFE_PP0P_'.\n",
+            "Generating RTLIL representation for module `\\$_DFFE_PP1P_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFF_NP0_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFF_NP1_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFF_PP0_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFF_PP1_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFFCE_NP0P_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFFCE_NP1P_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFFCE_PP0P_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFFCE_PP1P_'.\n",
+            "Successfully finished Verilog frontend.\n",
+            "\n",
+            "2.43.2. Continuing TECHMAP pass.\n",
+            "No more expansions possible.\n",
+            "Removed 2 unused cells and 62 unused wires.\n",
+            "\n",
+            "2.44. Executing OPT_LUT pass (optimize LUTs).\n",
+            "Discovering LUTs.\n",
+            "Number of LUTs:       40\n",
+            "  1-LUT                4\n",
+            "  2-LUT                1\n",
+            "  3-LUT               10\n",
+            "  4-LUT               25\n",
+            "  with \\SB_CARRY    (#0)    6\n",
+            "  with \\SB_CARRY    (#1)    6\n",
+            "\n",
+            "Eliminating LUTs.\n",
+            "Number of LUTs:       40\n",
+            "  1-LUT                4\n",
+            "  2-LUT                1\n",
+            "  3-LUT               10\n",
+            "  4-LUT               25\n",
+            "  with \\SB_CARRY    (#0)    6\n",
+            "  with \\SB_CARRY    (#1)    6\n",
+            "\n",
+            "Combining LUTs.\n",
+            "Number of LUTs:       39\n",
+            "  1-LUT                3\n",
+            "  2-LUT                1\n",
+            "  3-LUT               10\n",
+            "  4-LUT               25\n",
+            "  with \\SB_CARRY    (#0)    6\n",
+            "  with \\SB_CARRY    (#1)    6\n",
+            "\n",
+            "Eliminated 0 LUTs.\n",
+            "Combined 1 LUTs.\n",
+            "\n",
+            "2.45. Executing TECHMAP pass (map to technology primitives).\n",
+            "\n",
+            "2.45.1. Executing Verilog-2005 frontend: /content/miniconda-pnr/bin/../share/yosys/ice40/cells_map.v\n",
+            "Parsing Verilog input from `/content/miniconda-pnr/bin/../share/yosys/ice40/cells_map.v' to AST representation.\n",
+            "Generating RTLIL representation for module `\\$lut'.\n",
+            "Successfully finished Verilog frontend.\n",
+            "\n",
+            "2.45.2. Continuing TECHMAP pass.\n",
+            "Using template $paramod\\$lut\\WIDTH=32'00000000000000000000000000000001\\LUT=2'01 for cells of type $lut.\n",
+            "Using template $paramod$fd904e9e35cfd343a9df248824bd3f1408724879\\$lut for cells of type $lut.\n",
+            "Using template $paramod$272652f6c6fbe9a75eff76e45cc7e2788835518b\\$lut for cells of type $lut.\n",
+            "Using template $paramod$6e238df02989b317f10820a22773676e71120644\\$lut for cells of type $lut.\n",
+            "Using template $paramod\\$lut\\WIDTH=32'00000000000000000000000000000011\\LUT=8'00010000 for cells of type $lut.\n",
+            "Using template $paramod\\$lut\\WIDTH=32'00000000000000000000000000000011\\LUT=8'01000000 for cells of type $lut.\n",
+            "Using template $paramod$246006d276d15b0766d6d890a33a28800bfa7295\\$lut for cells of type $lut.\n",
+            "Using template $paramod\\$lut\\WIDTH=32'00000000000000000000000000000010\\LUT=4'0100 for cells of type $lut.\n",
+            "Using template $paramod$82b4a585d1edcb5c6e755dc9bd3392228a1c1304\\$lut for cells of type $lut.\n",
+            "Using template $paramod$62982cca7069de3707116b74c6df774a649aefd3\\$lut for cells of type $lut.\n",
+            "Using template $paramod$fe9a0158d0352193457c4f5b6282ac86d35fb3ee\\$lut for cells of type $lut.\n",
+            "Using template $paramod$4282def8dbd6df3d1248ad282c629bee684502c2\\$lut for cells of type $lut.\n",
+            "Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8\\$lut for cells of type $lut.\n",
+            "No more expansions possible.\n",
+            "Removed 0 unused cells and 92 unused wires.\n",
+            "\n",
+            "2.46. Executing AUTONAME pass.\n",
+            "Renamed 253 objects in module alu (10 iterations).\n",
+            "\n",
+            "2.47. Executing HIERARCHY pass (managing design hierarchy).\n",
+            "\n",
+            "2.47.1. Analyzing design hierarchy..\n",
+            "Top module:  \\alu\n",
+            "\n",
+            "2.47.2. Analyzing design hierarchy..\n",
+            "Top module:  \\alu\n",
+            "Removed 0 unused modules.\n",
+            "\n",
+            "2.48. Printing statistics.\n",
+            "\n",
+            "=== alu ===\n",
+            "\n",
+            "   Number of wires:                 19\n",
+            "   Number of wire bits:             72\n",
+            "   Number of public wires:          19\n",
+            "   Number of public wire bits:      72\n",
+            "   Number of memories:               0\n",
+            "   Number of memory bits:            0\n",
+            "   Number of processes:              0\n",
+            "   Number of cells:                 45\n",
+            "     SB_CARRY                        6\n",
+            "     SB_LUT4                        39\n",
+            "\n",
+            "2.49. Executing CHECK pass (checking for obvious problems).\n",
+            "Checking module alu...\n",
+            "Found and reported 0 problems.\n",
+            "\n",
+            "2.50. Executing JSON backend.\n",
+            "\n",
+            "End of script. Logfile hash: 8ec105c509, CPU: user 0.57s system 0.05s, MEM: 138.03 MB peak\n",
+            "Yosys 0.13+37 (git sha1 958c3a46a, x86_64-conda_cos6-linux-gnu-gcc 1.24.0.133_b0863d8_dirty -fvisibility-inlines-hidden -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -fdebug-prefix-map=/home/runner/work/conda-eda/conda-eda/workdir/conda-env/conda-bld/yosys_1644188991550/work=/usr/local/src/conda/yosys-0.13_39_g958c3a46a -fdebug-prefix-map=/content/miniconda-pnr=/usr/local/src/conda-prefix -fPIC -Os -fno-merge-constants)\n",
+            "Time spent: 43% 12x read_verilog (0 sec), 19% 1x abc (0 sec), ...\n"
+          ]
+        }
+      ]
+    },
+    {
+      "cell_type": "markdown",
+      "metadata": {
+        "id": "d12efb38"
+      },
+      "source": [
+        "**Reasoning**:\n",
+        "The previous step successfully synthesized the `alu.v` design into `alu.json`. Now, the next instruction is to use `nextpnr-ice40` to perform place and route on the generated `alu.json` file, targeting the `ICE40UP5K` architecture, and output an `.asc` file and an SVG floorplan (`alu_placed.svg`).\n",
+        "\n"
+      ]
+    },
+    {
+      "cell_type": "code",
+      "metadata": {
+        "colab": {
+          "base_uri": "https://localhost:8080/"
+        },
+        "id": "d3f2e493",
+        "outputId": "6b8d45a9-7e98-4d84-b33d-8a7a269eb59e"
+      },
+      "source": [
+        "import os\n",
+        "\n",
+        "# Ensure alu.json exists before attempting to run nextpnr\n",
+        "if not os.path.exists('alu.json'):\n",
+        "    print(\"Error: alu.json not found. Please ensure the synthesis step was successful.\")\n",
+        "else:\n",
+        "    !miniconda-pnr/bin/nextpnr-ice40 --up5k --json alu.json --asc alu.asc --placed-svg alu_placed.svg"
+      ],
+      "execution_count": 50,
+      "outputs": [
+        {
+          "output_type": "stream",
+          "name": "stdout",
+          "text": [
+            "Warning: Use of default value for --package is deprecated. Please add '--package sg48' to arguments.\n",
+            "Warning: No PCF file specified; IO pins will be placed automatically\n",
+            "\n",
+            "Info: Packing constants..\n",
+            "Info: Packing IOs..\n",
+            "Info: Packing LUT-FFs..\n",
+            "Info:       39 LCs used as LUT4 only\n",
+            "Info:        0 LCs used as LUT4 and DFF\n",
+            "Info: Packing non-LUT FFs..\n",
+            "Info:        0 LCs used as DFF only\n",
+            "Info: Packing carries..\n",
+            "Info:        0 LCs used as CARRY only\n",
+            "Info: Packing indirect carry+LUT pairs...\n",
+            "Info:        0 LUTs merged into carry LCs\n",
+            "Info: Packing RAMs..\n",
+            "Info: Placing PLLs..\n",
+            "Info: Packing special functions..\n",
+            "Info: Packing PLLs..\n",
+            "Info: Promoting globals..\n",
+            "Info: Constraining chains...\n",
+            "Info:        0 LCs used to legalise carry chains.\n",
+            "Info: Checksum: 0x93cd5f13\n",
+            "\n",
+            "Info: Annotating ports with timing budgets for target frequency 12.00 MHz\n",
+            "Info: Checksum: 0x17ebdc31\n",
+            "\n",
+            "Info: Device utilisation:\n",
+            "Info: \t         ICESTORM_LC:    41/ 5280     0%\n",
+            "Info: \t        ICESTORM_RAM:     0/   30     0%\n",
+            "Info: \t               SB_IO:    16/   96    16%\n",
+            "Info: \t               SB_GB:     0/    8     0%\n",
+            "Info: \t        ICESTORM_PLL:     0/    1     0%\n",
+            "Info: \t         SB_WARMBOOT:     0/    1     0%\n",
+            "Info: \t        ICESTORM_DSP:     0/    8     0%\n",
+            "Info: \t      ICESTORM_HFOSC:     0/    1     0%\n",
+            "Info: \t      ICESTORM_LFOSC:     0/    1     0%\n",
+            "Info: \t              SB_I2C:     0/    2     0%\n",
+            "Info: \t              SB_SPI:     0/    2     0%\n",
+            "Info: \t              IO_I3C:     0/    2     0%\n",
+            "Info: \t         SB_LEDDA_IP:     0/    1     0%\n",
+            "Info: \t         SB_RGBA_DRV:     0/    1     0%\n",
+            "Info: \t      ICESTORM_SPRAM:     0/    4     0%\n",
+            "\n",
+            "Info: Placed 0 cells based on constraints.\n",
+            "Info: Creating initial analytic placement for 34 cells, random placement wirelen = 1162.\n",
+            "Info:     at initial placer iter 0, wirelen = 343\n",
+            "Info:     at initial placer iter 1, wirelen = 341\n",
+            "Info:     at initial placer iter 2, wirelen = 342\n",
+            "Info:     at initial placer iter 3, wirelen = 341\n",
+            "Info: Running main analytical placer.\n",
+            "Info:     at iteration #1, type ICESTORM_LC: wirelen solved = 335, spread = 374, legal = 378; time = 0.00s\n",
+            "Info: HeAP Placer Time: 0.01s\n",
+            "Info:   of which solving equations: 0.01s\n",
+            "Info:   of which spreading cells: 0.00s\n",
+            "Info:   of which strict legalisation: 0.00s\n",
+            "\n",
+            "Info: Running simulated annealing placer for refinement.\n",
+            "Info:   at iteration #1: temp = 0.000000, timing cost = 0, wirelen = 378\n",
+            "Info:   at iteration #5: temp = 0.000000, timing cost = 0, wirelen = 325\n",
+            "Info:   at iteration #9: temp = 0.000000, timing cost = 0, wirelen = 324 \n",
+            "Info: SA placement time 0.01s\n",
+            "Info: No Fmax available; no interior timing paths found in design.\n",
+            "\n",
+            "Info: Max delay <async> -> <async>: 26.11 ns\n",
+            "\n",
+            "Info: Slack histogram:\n",
+            "Info:  legend: * represents 1 endpoint(s)\n",
+            "Info:          + represents [1,1) endpoint(s)\n",
+            "Info: [ 57221,  57639) |* \n",
+            "Info: [ 57639,  58057) |** \n",
+            "Info: [ 58057,  58475) | \n",
+            "Info: [ 58475,  58893) | \n",
+            "Info: [ 58893,  59311) | \n",
+            "Info: [ 59311,  59729) | \n",
+            "Info: [ 59729,  60147) | \n",
+            "Info: [ 60147,  60565) | \n",
+            "Info: [ 60565,  60983) |* \n",
+            "Info: [ 60983,  61401) | \n",
+            "Info: [ 61401,  61819) | \n",
+            "Info: [ 61819,  62237) | \n",
+            "Info: [ 62237,  62655) | \n",
+            "Info: [ 62655,  63073) | \n",
+            "Info: [ 63073,  63491) | \n",
+            "Info: [ 63491,  63909) | \n",
+            "Info: [ 63909,  64327) | \n",
+            "Info: [ 64327,  64745) | \n",
+            "Info: [ 64745,  65163) | \n",
+            "Info: [ 65163,  65581) |* \n",
+            "Info: Checksum: 0x841aa1f3\n",
+            "\n",
+            "Info: Routing..\n",
+            "Info: Setting up routing queue.\n",
+            "Info: Routing 143 arcs.\n",
+            "Info:            |   (re-)routed arcs  |   delta    | remaining|       time spent     |\n",
+            "Info:    IterCnt |  w/ripup   wo/ripup |  w/r  wo/r |      arcs| batch(sec) total(sec)|\n",
+            "Info:        155 |       11        140 |   11   140 |         0|       0.19       0.19|\n",
+            "Info: Routing complete.\n",
+            "Info: Router1 time 0.19s\n",
+            "Info: Checksum: 0x8a9bb067\n",
+            "Info: No Fmax available; no interior timing paths found in design.\n",
+            "\n",
+            "Info: Critical path report for cross-domain path '<async>' -> '<async>':\n",
+            "Info: curr total\n",
+            "Info:  0.0  0.0  Source b[2]$sb_io.D_IN_0\n",
+            "Info:  6.7  6.7    Net b[2]$SB_IO_IN budget 6.561000 ns (12,31) -> (14,1)\n",
+            "Info:                Sink result_SB_LUT4_O_I0_SB_LUT4_O_2_I3_SB_LUT4_O_I3_SB_LUT4_O_3_I2_SB_LUT4_O_LC.I3\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/cells_map.v:6.21-6.22\n",
+            "Info:  0.9  7.6  Source result_SB_LUT4_O_I0_SB_LUT4_O_2_I3_SB_LUT4_O_I3_SB_LUT4_O_3_I2_SB_LUT4_O_LC.O\n",
+            "Info:  1.8  9.3    Net result_SB_LUT4_O_I0_SB_LUT4_O_2_I3_SB_LUT4_O_I3_SB_LUT4_O_3_I2[2] budget 6.561000 ns (14,1) -> (14,1)\n",
+            "Info:                Sink result_SB_LUT4_O_I0_SB_LUT4_O_2_I3_SB_LUT4_O_I3_SB_LUT4_O_1_LC.I2\n",
+            "Info:                Defined in:\n",
+            "Info:                  alu.v:13.24-13.29\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:49.21-49.23\n",
+            "Info:  0.6  9.9  Source result_SB_LUT4_O_I0_SB_LUT4_O_2_I3_SB_LUT4_O_I3_SB_LUT4_O_1_LC.COUT\n",
+            "Info:  0.7 10.6    Net result_SB_LUT4_O_I0_SB_LUT4_O_2_I3_SB_LUT4_O_I3_SB_LUT4_O_I3[3] budget 0.660000 ns (14,1) -> (14,1)\n",
+            "Info:                Sink result_SB_LUT4_O_I0_SB_LUT4_O_2_I3_SB_LUT4_O_I3_SB_LUT4_O_LC.I3\n",
+            "Info:                Defined in:\n",
+            "Info:                  alu.v:13.24-13.29\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.9 11.5  Source result_SB_LUT4_O_I0_SB_LUT4_O_2_I3_SB_LUT4_O_I3_SB_LUT4_O_LC.O\n",
+            "Info:  2.3 13.8    Net result_SB_LUT4_O_I0_SB_LUT4_O_2_I3_SB_LUT4_O_I3[3] budget 13.121000 ns (14,1) -> (16,1)\n",
+            "Info:                Sink result_SB_LUT4_O_I0_SB_LUT4_O_2_I3_SB_LUT4_O_LC.I3\n",
+            "Info:                Defined in:\n",
+            "Info:                  alu.v:13.24-13.29\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:33.26-33.27\n",
+            "Info:  0.9 14.6  Source result_SB_LUT4_O_I0_SB_LUT4_O_2_I3_SB_LUT4_O_LC.O\n",
+            "Info:  1.8 16.4    Net result_SB_LUT4_O_I0_SB_LUT4_O_2_I3[3] budget 13.121000 ns (16,1) -> (16,1)\n",
+            "Info:                Sink result_SB_LUT4_O_I0_SB_LUT4_O_2_LC.I3\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/cells_map.v:6.21-6.22\n",
+            "Info:  0.9 17.3  Source result_SB_LUT4_O_I0_SB_LUT4_O_2_LC.O\n",
+            "Info:  1.8 19.0    Net result_SB_LUT4_O_I0[2] budget 13.121000 ns (16,1) -> (16,2)\n",
+            "Info:                Sink result_SB_LUT4_O_LC.I2\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/cells_map.v:6.21-6.22\n",
+            "Info:  1.2 20.2  Source result_SB_LUT4_O_LC.O\n",
+            "Info:  6.9 27.2    Net result[3]$SB_IO_OUT budget 15.493000 ns (16,2) -> (17,31)\n",
+            "Info:                Sink result[3]$sb_io.D_OUT_0\n",
+            "Info:                Defined in:\n",
+            "Info:                  alu.v:6.20-6.26\n",
+            "Info: 5.3 ns logic, 21.9 ns routing\n",
+            "\n",
+            "Info: Max delay <async> -> <async>: 27.19 ns\n",
+            "\n",
+            "Info: Slack histogram:\n",
+            "Info:  legend: * represents 1 endpoint(s)\n",
+            "Info:          + represents [1,1) endpoint(s)\n",
+            "Info: [ 56144,  56563) |* \n",
+            "Info: [ 56563,  56982) | \n",
+            "Info: [ 56982,  57401) |* \n",
+            "Info: [ 57401,  57820) | \n",
+            "Info: [ 57820,  58239) |* \n",
+            "Info: [ 58239,  58658) | \n",
+            "Info: [ 58658,  59077) | \n",
+            "Info: [ 59077,  59496) | \n",
+            "Info: [ 59496,  59915) |* \n",
+            "Info: [ 59915,  60334) | \n",
+            "Info: [ 60334,  60753) | \n",
+            "Info: [ 60753,  61172) | \n",
+            "Info: [ 61172,  61591) | \n",
+            "Info: [ 61591,  62010) | \n",
+            "Info: [ 62010,  62429) | \n",
+            "Info: [ 62429,  62848) | \n",
+            "Info: [ 62848,  63267) | \n",
+            "Info: [ 63267,  63686) | \n",
+            "Info: [ 63686,  64105) | \n",
+            "Info: [ 64105,  64524) |* \n",
+            "2 warnings, 0 errors\n",
+            "\n",
+            "Info: Program finished normally.\n"
+          ]
+        }
+      ]
+    },
+    {
+      "cell_type": "markdown",
+      "metadata": {
+        "id": "16862d03"
+      },
+      "source": [
+        "**Reasoning**:\n",
+        "The previous step successfully generated the `alu_placed.svg` file. The next instruction is to display this SVG floorplan using `IPython.display.SVG`.\n",
+        "\n"
+      ]
+    },
+    {
+      "cell_type": "code",
+      "metadata": {
+        "colab": {
+          "base_uri": "https://localhost:8080/",
+          "height": 1000
+        },
+        "id": "7e2bd1ea",
+        "outputId": "12836d19-199f-44f3-e059-f79b7aba8b5d"
+      },
+      "source": [
+        "from IPython.display import SVG\n",
+        "SVG(filename='alu_placed.svg')"
+      ],
+      "execution_count": 51,
+      "outputs": [
+        {
+          "output_type": "execute_result",
+          "data": {
+            "text/plain": [
+              "<IPython.core.display.SVG object>"
+            ],
+            "image/svg+xml": "<svg xmlns=\"http://www.w3.org/2000/svg\" viewBox=\"0 0 1349.166504 1643.375000\" width=\"1349.166504\" height=\"1643.375000\">\n<rect x=\"0\" y=\"0\" width=\"100%\" height=\"100%\" stroke=\"#fff\" fill=\"#fff\"/>\n<rect x=\"67.500000\" y=\"2.500000\" width=\"12.500000\" height=\"34.000000\" stroke=\"#808080\" fill=\"none\"/>\n<rect x=\"81.500000\" y=\"2.500000\" width=\"5.000001\" height=\"25.000000\" stroke=\"#808080\" fill=\"none\"/>\n<rect x=\"117.499992\" y=\"2.500000\" width=\"12.500000\" height=\"34.000000\" stroke=\"#808080\" fill=\"none\"/>\n<rect x=\"131.500000\" y=\"2.500000\" width=\"4.999995\" height=\"25.000000\" stroke=\"#808080\" fill=\"none\"/>\n<rect x=\"167.500000\" y=\"2.500000\" width=\"12.500000\" height=\"34.000000\" stroke=\"#808080\" fill=\"none\"/>\n<rect x=\"181.500000\" y=\"2.500000\" width=\"4.999995\" height=\"25.000000\" stroke=\"#808080\" fill=\"none\"/>\n<rect x=\"217.500000\" y=\"2.500000\" width=\"12.500000\" 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+          },
+          "metadata": {},
+          "execution_count": 51
+        }
+      ]
+    },
+    {
+      "cell_type": "markdown",
+      "metadata": {
+        "id": "950c8ad9"
+      },
+      "source": [
+        "### Confirm the successful placement and routing of the ALU and present the generated floorplan.\n",
+        "\n",
+        "### Subtask:\n",
+        "Confirm successful placement and routing and present the generated floorplan.\n"
+      ]
+    },
+    {
+      "cell_type": "markdown",
+      "metadata": {
+        "id": "0a3b15a0"
+      },
+      "source": [
+        "### Confirm the successful placement and routing of the ALU and present the generated floorplan.\n",
+        "\n",
+        "### Subtask:\n",
+        "Confirm successful placement and routing and present the generated floorplan.\n",
+        "\n",
+        "#### Summary of Placement and Routing for ALU\n",
+        "\n",
+        "1.  **Yosys Synthesis (`alu.json`)**: The ALU design was successfully synthesized to an intermediate JSON format by Yosys, ready for place and route.\n",
+        "\n",
+        "2.  **Nextpnr-ice40 Placement and Routing**:\n",
+        "    *   The `nextpnr-ice40` tool successfully performed placement and routing for the `alu.json` design, targeting the `ICE40UP5K` architecture.\n",
+        "    *   **Resource Utilization**: The ALU utilized a small portion of the available resources on the ICE40UP5K FPGA:\n",
+        "        *   ICESTORM_LC (Logic Cells): 41/5280 (0%)\n",
+        "        *   SB_IO (Input/Output Buffers): 16/96 (16%)\n",
+        "    *   **Timing**: The maximum delay reported was 26.11 ns. No critical timing paths were found that would indicate timing violations, suggesting the design meets basic timing requirements.\n",
+        "    *   **Warnings**: A deprecation warning for `--package` was noted, but it did not prevent successful placement and routing.\n",
+        "\n",
+        "3.  **Floorplan Visualization (`alu_placed.svg`)**: The generated `alu_placed.svg` floorplan (displayed above in the previous output) visually confirms the successful placement of the ALU's logic cells and I/O pins on the FPGA fabric, with all necessary connections routed.\n",
+        "\n",
+        "**Conclusion**: The placement and routing process for the ALU design (`alu.v`) was successfully completed, resulting in a low resource utilization and a functional layout as depicted in the floorplan."
+      ]
+    },
+    {
+      "cell_type": "markdown",
+      "metadata": {
+        "id": "f2f2affa"
+      },
+      "source": [
+        "### Confirm the successful placement and routing of the ALU and present the generated floorplan.\n",
+        "\n",
+        "### Subtask:\n",
+        "Confirm successful placement and routing and present the generated floorplan.\n",
+        "\n",
+        "#### Summary of Placement and Routing for ALU\n",
+        "\n",
+        "1.  **Yosys Synthesis (`alu.json`)**: The ALU design was successfully synthesized to an intermediate JSON format by Yosys, ready for place and route.\n",
+        "\n",
+        "2.  **Nextpnr-ice40 Placement and Routing**:\n",
+        "    *   The `nextpnr-ice40` tool successfully performed placement and routing for the `alu.json` design, targeting the `ICE40UP5K` architecture.\n",
+        "    *   **Resource Utilization**: The ALU utilized a small portion of the available resources on the ICE40UP5K FPGA:\n",
+        "        *   ICESTORM_LC (Logic Cells): 41/5280 (0%)\n",
+        "        *   SB_IO (Input/Output Buffers): 16/96 (16%)\n",
+        "    *   **Timing**: The maximum delay reported was 26.11 ns. No critical timing paths were found that would indicate timing violations, suggesting the design meets basic timing requirements.\n",
+        "    *   **Warnings**: A deprecation warning for `--package` was noted, but it did not prevent successful placement and routing.\n",
+        "\n",
+        "3.  **Floorplan Visualization (`alu_placed.svg`)**: The generated `alu_placed.svg` floorplan (displayed above in the previous output) visually confirms the successful placement of the ALU's logic cells and I/O pins on the FPGA fabric, with all necessary connections routed.\n",
+        "\n",
+        "**Conclusion**: The placement and routing process for the ALU design (`alu.v`) was successfully completed, resulting in a low resource utilization and a functional layout as depicted in the floorplan."
+      ]
+    },
+    {
+      "cell_type": "markdown",
+      "metadata": {
+        "id": "ae31dac6"
+      },
+      "source": [
+        "### Final Task\n",
+        "\n",
+        "### Subtask:\n",
+        "Confirm the successful placement and routing of the ALU and present the generated floorplan.\n"
+      ]
+    },
+    {
+      "cell_type": "markdown",
+      "metadata": {
+        "id": "b05e90e7"
+      },
+      "source": [
+        "### Summary:\n",
+        "\n",
+        "### Q&A\n",
+        "The successful placement and routing of the ALU has been confirmed. The `alu.v` design was successfully synthesized into an intermediate JSON format, then placed and routed by `nextpnr-ice40` targeting the `ICE40UP5K` architecture. The generated floorplan (`alu_placed.svg`) visually confirms the successful layout of the design.\n",
+        "\n",
+        "### Data Analysis Key Findings\n",
+        "*   **Synthesis Success**: The `alu.v` design was successfully synthesized by Yosys, generating `alu.json` which contains 45 cells (6 `SB_CARRY` and 39 `SB_LUT4`).\n",
+        "*   **Placement and Routing Completion**: `nextpnr-ice40` successfully completed the placement and routing process for the ALU design on the `ICE40UP5K` architecture.\n",
+        "*   **Low Resource Utilization**: The ALU design utilized a very small portion of the target FPGA's resources: 41 out of 5280 `ICESTORM_LC` (0%) and 16 out of 96 `SB_IO` (16%).\n",
+        "*   **Acceptable Timing**: The reported maximum delay was 26.11 ns, indicating the design meets basic timing requirements with no critical timing path violations reported.\n",
+        "*   **Floorplan Generation**: A visual floorplan (`alu_placed.svg`) was successfully generated, confirming the physical layout of the placed logic cells and routed connections.\n",
+        "\n",
+        "### Insights or Next Steps\n",
+        "*   The current low resource utilization suggests the ALU design is efficient for the `ICE40UP5K` FPGA, leaving ample space for additional logic if the design were to be expanded.\n",
+        "*   For future development or larger designs, consider addressing the noted warnings, such as specifying a package (e.g., `--package sg48`) and providing a PCF file for explicit I/O pin assignments, to ensure more predictable and robust results.\n"
+      ]
+    }
+  ]
+}
\ No newline at end of file
diff --git a/colab-scripts/(Counter and Adder) Icarus Verilog and Yosys.ipynb b/colab-scripts/(Counter and Adder) Icarus Verilog and Yosys.ipynb
new file mode 100644
index 0000000..a3eeee9
--- /dev/null
+++ b/colab-scripts/(Counter and Adder) Icarus Verilog and Yosys.ipynb	
@@ -0,0 +1,7250 @@
+{
+  "nbformat": 4,
+  "nbformat_minor": 0,
+  "metadata": {
+    "colab": {
+      "provenance": [],
+      "toc_visible": true
+    },
+    "kernelspec": {
+      "name": "python3",
+      "display_name": "Python 3"
+    },
+    "language_info": {
+      "name": "python"
+    }
+  },
+  "cells": [
+    {
+      "cell_type": "markdown",
+      "metadata": {
+        "id": "ngvQPp1y8pgZ"
+      },
+      "source": [
+        "# 🎁 Open EDA Tooling Treats\n",
+        "\n",
+        "```\n",
+        "Copyright 2021 Google LLC.\n",
+        "SPDX-License-Identifier: Apache-2.0\n",
+        "```\n",
+        "\n",
+        "Context: https://twitter.com/proppy/status/1466020384063430657"
+      ]
+    },
+    {
+      "cell_type": "markdown",
+      "metadata": {
+        "id": "Miek1LUU9Xgx"
+      },
+      "source": [
+        "## 🍬 Treat #1: EDA Conda Packages & Notebooks\n",
+        "\n",
+        "The [conda-eda](https://github.com/hdl/conda-eda) project maintains a collection of conda packages recipes. Those package can be used to easily bootstrap EDA environments in Jupyter and Colab notebooks.\n",
+        "\n",
+        "This notebook shows how to lint Verilog cells and plot the simulated waveforms for a simple 4-bits counter design."
+      ]
+    },
+    {
+      "cell_type": "markdown",
+      "metadata": {
+        "id": "k9Ldv3KHAhJ8"
+      },
+      "source": [
+        "### Install packages\n",
+        "\n",
+        "Install packages from the `LiteX-Hub` [channel](https://anaconda.org/LiteX-Hub/repo); also install older packages from the `SymbiFlow` channel, to get better compat with colab: see [conda-eda#146](https://github.com/hdl/conda-eda/issues/146)."
+      ]
+    },
+    {
+      "cell_type": "code",
+      "metadata": {
+        "id": "RSskI42P9Sxa",
+        "colab": {
+          "base_uri": "https://localhost:8080/"
+        },
+        "outputId": "c8c5e885-44e6-483a-dcb6-ad52d000cad1"
+      },
+      "source": [
+        "!curl -O https://repo.anaconda.com/miniconda/Miniconda3-py37_4.10.3-Linux-x86_64.sh\n",
+        "!bash Miniconda3-py37_4.10.3-Linux-x86_64.sh -b -f -p miniconda-eda/\n",
+        "!miniconda-eda/bin/conda install --yes -c LiteX-Hub iverilog\n",
+        "!miniconda-eda/bin/conda install --yes -c SymbiFlow verible"
+      ],
+      "execution_count": 1,
+      "outputs": [
+        {
+          "output_type": "stream",
+          "name": "stdout",
+          "text": [
+            "  % Total    % Received % Xferd  Average Speed   Time    Time     Time  Current\n",
+            "                                 Dload  Upload   Total   Spent    Left  Speed\n",
+            "100 84.9M  100 84.9M    0     0   108M      0 --:--:-- --:--:-- --:--:--  108M\n",
+            "PREFIX=/content/miniconda-eda\n",
+            "Unpacking payload ...\n",
+            "Collecting package metadata (current_repodata.json): - \b\b\\ \b\bdone\n",
+            "Solving environment: / \b\b- \b\b\\ \b\bdone\n",
+            "\n",
+            "## Package Plan ##\n",
+            "\n",
+            "  environment location: /content/miniconda-eda\n",
+            "\n",
+            "  added / updated specs:\n",
+            "    - _libgcc_mutex==0.1=main\n",
+            "    - _openmp_mutex==4.5=1_gnu\n",
+            "    - brotlipy==0.7.0=py37h27cfd23_1003\n",
+            "    - ca-certificates==2021.7.5=h06a4308_1\n",
+            "    - certifi==2021.5.30=py37h06a4308_0\n",
+            "    - cffi==1.14.6=py37h400218f_0\n",
+            "    - chardet==4.0.0=py37h06a4308_1003\n",
+            "    - conda-package-handling==1.7.3=py37h27cfd23_1\n",
+            "    - conda==4.10.3=py37h06a4308_0\n",
+            "    - cryptography==3.4.7=py37hd23ed53_0\n",
+            "    - idna==2.10=pyhd3eb1b0_0\n",
+            "    - ld_impl_linux-64==2.35.1=h7274673_9\n",
+            "    - libffi==3.3=he6710b0_2\n",
+            "    - libgcc-ng==9.3.0=h5101ec6_17\n",
+            "    - libgomp==9.3.0=h5101ec6_17\n",
+            "    - libstdcxx-ng==9.3.0=hd4cf53a_17\n",
+            "    - ncurses==6.2=he6710b0_1\n",
+            "    - openssl==1.1.1k=h27cfd23_0\n",
+            "    - pip==21.1.3=py37h06a4308_0\n",
+            "    - pycosat==0.6.3=py37h27cfd23_0\n",
+            "    - pycparser==2.20=py_2\n",
+            "    - pyopenssl==20.0.1=pyhd3eb1b0_1\n",
+            "    - pysocks==1.7.1=py37_1\n",
+            "    - python==3.7.10=h12debd9_4\n",
+            "    - readline==8.1=h27cfd23_0\n",
+            "    - requests==2.25.1=pyhd3eb1b0_0\n",
+            "    - ruamel_yaml==0.15.100=py37h27cfd23_0\n",
+            "    - setuptools==52.0.0=py37h06a4308_0\n",
+            "    - six==1.16.0=pyhd3eb1b0_0\n",
+            "    - sqlite==3.36.0=hc218d9a_0\n",
+            "    - tk==8.6.10=hbc83047_0\n",
+            "    - tqdm==4.61.2=pyhd3eb1b0_1\n",
+            "    - urllib3==1.26.6=pyhd3eb1b0_1\n",
+            "    - wheel==0.36.2=pyhd3eb1b0_0\n",
+            "    - xz==5.2.5=h7b6447c_0\n",
+            "    - yaml==0.2.5=h7b6447c_0\n",
+            "    - zlib==1.2.11=h7b6447c_3\n",
+            "\n",
+            "\n",
+            "The following NEW packages will be INSTALLED:\n",
+            "\n",
+            "  _libgcc_mutex      pkgs/main/linux-64::_libgcc_mutex-0.1-main\n",
+            "  _openmp_mutex      pkgs/main/linux-64::_openmp_mutex-4.5-1_gnu\n",
+            "  brotlipy           pkgs/main/linux-64::brotlipy-0.7.0-py37h27cfd23_1003\n",
+            "  ca-certificates    pkgs/main/linux-64::ca-certificates-2021.7.5-h06a4308_1\n",
+            "  certifi            pkgs/main/linux-64::certifi-2021.5.30-py37h06a4308_0\n",
+            "  cffi               pkgs/main/linux-64::cffi-1.14.6-py37h400218f_0\n",
+            "  chardet            pkgs/main/linux-64::chardet-4.0.0-py37h06a4308_1003\n",
+            "  conda              pkgs/main/linux-64::conda-4.10.3-py37h06a4308_0\n",
+            "  conda-package-han~ pkgs/main/linux-64::conda-package-handling-1.7.3-py37h27cfd23_1\n",
+            "  cryptography       pkgs/main/linux-64::cryptography-3.4.7-py37hd23ed53_0\n",
+            "  idna               pkgs/main/noarch::idna-2.10-pyhd3eb1b0_0\n",
+            "  ld_impl_linux-64   pkgs/main/linux-64::ld_impl_linux-64-2.35.1-h7274673_9\n",
+            "  libffi             pkgs/main/linux-64::libffi-3.3-he6710b0_2\n",
+            "  libgcc-ng          pkgs/main/linux-64::libgcc-ng-9.3.0-h5101ec6_17\n",
+            "  libgomp            pkgs/main/linux-64::libgomp-9.3.0-h5101ec6_17\n",
+            "  libstdcxx-ng       pkgs/main/linux-64::libstdcxx-ng-9.3.0-hd4cf53a_17\n",
+            "  ncurses            pkgs/main/linux-64::ncurses-6.2-he6710b0_1\n",
+            "  openssl            pkgs/main/linux-64::openssl-1.1.1k-h27cfd23_0\n",
+            "  pip                pkgs/main/linux-64::pip-21.1.3-py37h06a4308_0\n",
+            "  pycosat            pkgs/main/linux-64::pycosat-0.6.3-py37h27cfd23_0\n",
+            "  pycparser          pkgs/main/noarch::pycparser-2.20-py_2\n",
+            "  pyopenssl          pkgs/main/noarch::pyopenssl-20.0.1-pyhd3eb1b0_1\n",
+            "  pysocks            pkgs/main/linux-64::pysocks-1.7.1-py37_1\n",
+            "  python             pkgs/main/linux-64::python-3.7.10-h12debd9_4\n",
+            "  readline           pkgs/main/linux-64::readline-8.1-h27cfd23_0\n",
+            "  requests           pkgs/main/noarch::requests-2.25.1-pyhd3eb1b0_0\n",
+            "  ruamel_yaml        pkgs/main/linux-64::ruamel_yaml-0.15.100-py37h27cfd23_0\n",
+            "  setuptools         pkgs/main/linux-64::setuptools-52.0.0-py37h06a4308_0\n",
+            "  six                pkgs/main/noarch::six-1.16.0-pyhd3eb1b0_0\n",
+            "  sqlite             pkgs/main/linux-64::sqlite-3.36.0-hc218d9a_0\n",
+            "  tk                 pkgs/main/linux-64::tk-8.6.10-hbc83047_0\n",
+            "  tqdm               pkgs/main/noarch::tqdm-4.61.2-pyhd3eb1b0_1\n",
+            "  urllib3            pkgs/main/noarch::urllib3-1.26.6-pyhd3eb1b0_1\n",
+            "  wheel              pkgs/main/noarch::wheel-0.36.2-pyhd3eb1b0_0\n",
+            "  xz                 pkgs/main/linux-64::xz-5.2.5-h7b6447c_0\n",
+            "  yaml               pkgs/main/linux-64::yaml-0.2.5-h7b6447c_0\n",
+            "  zlib               pkgs/main/linux-64::zlib-1.2.11-h7b6447c_3\n",
+            "\n",
+            "\n",
+            "Preparing transaction: / \b\b- \b\b\\ \b\b| \b\bdone\n",
+            "Executing transaction: - \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\bdone\n",
+            "installation finished.\n",
+            "WARNING:\n",
+            "    You currently have a PYTHONPATH environment variable set. This may cause\n",
+            "    unexpected behavior when running the Python interpreter in Miniconda3.\n",
+            "    For best results, please verify that your PYTHONPATH only points to\n",
+            "    directories of packages that are compatible with the Python interpreter\n",
+            "    in Miniconda3: /content/miniconda-eda\n",
+            "Collecting package metadata (current_repodata.json): - \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\bdone\n",
+            "Solving environment: / \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\bdone\n",
+            "\n",
+            "\n",
+            "==> WARNING: A newer version of conda exists. <==\n",
+            "  current version: 4.10.3\n",
+            "  latest version: 26.1.1\n",
+            "\n",
+            "Please update conda by running\n",
+            "\n",
+            "    $ conda update -n base -c defaults conda\n",
+            "\n",
+            "\n",
+            "\n",
+            "## Package Plan ##\n",
+            "\n",
+            "  environment location: /content/miniconda-eda\n",
+            "\n",
+            "  added / updated specs:\n",
+            "    - iverilog\n",
+            "\n",
+            "\n",
+            "The following packages will be downloaded:\n",
+            "\n",
+            "    package                    |            build\n",
+            "    ---------------------------|-----------------\n",
+            "    ca-certificates-2025.12.2  |       h06a4308_0         125 KB\n",
+            "    iverilog-0_8_5850_g540555fc|  20211214_154543         2.4 MB  LiteX-Hub\n",
+            "    openssl-1.1.1w             |       h7f8727e_0         3.7 MB\n",
+            "    ------------------------------------------------------------\n",
+            "                                           Total:         6.3 MB\n",
+            "\n",
+            "The following NEW packages will be INSTALLED:\n",
+            "\n",
+            "  iverilog           LiteX-Hub/linux-64::iverilog-0_8_5850_g540555fc-20211214_154543\n",
+            "\n",
+            "The following packages will be UPDATED:\n",
+            "\n",
+            "  ca-certificates                       2021.7.5-h06a4308_1 --> 2025.12.2-h06a4308_0\n",
+            "  openssl                                 1.1.1k-h27cfd23_0 --> 1.1.1w-h7f8727e_0\n",
+            "\n",
+            "\n",
+            "\n",
+            "Downloading and Extracting Packages\n",
+            "openssl-1.1.1w       | 3.7 MB    | : 100% 1.0/1 [00:00<00:00,  2.16it/s]               \n",
+            "iverilog-0_8_5850_g5 | 2.4 MB    | : 100% 1.0/1 [00:01<00:00,  1.08s/it]\n",
+            "ca-certificates-2025 | 125 KB    | : 100% 1.0/1 [00:00<00:00,  4.20it/s]\n",
+            "Preparing transaction: - \b\bdone\n",
+            "Verifying transaction: | \b\b/ \b\bdone\n",
+            "Executing transaction: \\ \b\bdone\n",
+            "Collecting package metadata (current_repodata.json): - \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\bdone\n",
+            "Solving environment: \\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\bdone\n",
+            "\n",
+            "\n",
+            "==> WARNING: A newer version of conda exists. <==\n",
+            "  current version: 4.10.3\n",
+            "  latest version: 26.1.1\n",
+            "\n",
+            "Please update conda by running\n",
+            "\n",
+            "    $ conda update -n base -c defaults conda\n",
+            "\n",
+            "\n",
+            "\n",
+            "## Package Plan ##\n",
+            "\n",
+            "  environment location: /content/miniconda-eda\n",
+            "\n",
+            "  added / updated specs:\n",
+            "    - verible\n",
+            "\n",
+            "\n",
+            "The following packages will be downloaded:\n",
+            "\n",
+            "    package                    |            build\n",
+            "    ---------------------------|-----------------\n",
+            "    verible-0.0.836_0000_g1b1294c|  20201231_075710         4.2 MB  SymbiFlow\n",
+            "    ------------------------------------------------------------\n",
+            "                                           Total:         4.2 MB\n",
+            "\n",
+            "The following NEW packages will be INSTALLED:\n",
+            "\n",
+            "  verible            SymbiFlow/linux-64::verible-0.0.836_0000_g1b1294c-20201231_075710\n",
+            "\n",
+            "\n",
+            "\n",
+            "Downloading and Extracting Packages\n",
+            "verible-0.0.836_0000 | 4.2 MB    | : 100% 1.0/1 [00:01<00:00,  1.77s/it]\n",
+            "Preparing transaction: - \b\bdone\n",
+            "Verifying transaction: | \b\bdone\n",
+            "Executing transaction: - \b\bdone\n"
+          ]
+        }
+      ]
+    },
+    {
+      "cell_type": "markdown",
+      "metadata": {
+        "id": "qB751juXAzVO"
+      },
+      "source": [
+        "### Lint and simulate Verilog cells\n",
+        "\n",
+        "Use the `%%bash` magic to lint the content of the cell with [Verible](https://github.com/chipsalliance/verible) and simulate the test bench using [Icarus Verilog](http://iverilog.icarus.com/).\n"
+      ]
+    },
+    {
+      "cell_type": "code",
+      "metadata": {
+        "colab": {
+          "base_uri": "https://localhost:8080/"
+        },
+        "id": "emWMhIw4ef-P",
+        "outputId": "8febd47d-0afd-4036-e574-750268cb64d5"
+      },
+      "source": [
+        "%%bash -c 'source miniconda-eda/bin/activate; cat > counter.v; verible-verilog-lint counter.v && iverilog counter.v && vvp a.out'\n",
+        "\n",
+        "module counter(input clk, input rst, output reg[3:0] out);\n",
+        "  always @ (posedge clk) begin\n",
+        "    if (rst)\n",
+        "      out <= 0;\n",
+        "    else\n",
+        "      out <= out + 1;\n",
+        "  end\n",
+        "endmodule\n",
+        "\n",
+        "module counter_tb;\n",
+        "  reg clk;\n",
+        "  reg rst;\n",
+        "\n",
+        "  wire [3:0] out;\n",
+        "\n",
+        "  counter c1(.clk(clk), .rst(rst), .out(out));\n",
+        "\n",
+        "  always #1 clk = !clk;\n",
+        "\n",
+        "  initial begin\n",
+        "    $dumpfile(\"test.vcd\");\n",
+        "    $dumpvars(0,counter_tb);\n",
+        "    clk <= 0;\n",
+        "    rst <= 1;\n",
+        "    #1  rst <= 0;\n",
+        "    #11 rst <= 1;\n",
+        "    #1  rst <= 0;\n",
+        "    #51 $finish;\n",
+        "  end\n",
+        "endmodule"
+      ],
+      "execution_count": 2,
+      "outputs": [
+        {
+          "output_type": "stream",
+          "name": "stdout",
+          "text": [
+            "VCD info: dumpfile test.vcd opened for output.\n",
+            "counter.v:29: $finish called at 64 (1s)\n"
+          ]
+        }
+      ]
+    },
+    {
+      "cell_type": "markdown",
+      "metadata": {
+        "id": "9tKYXxifEFT7"
+      },
+      "source": [
+        "### Plot VCD waveforms\n",
+        "\n",
+        "Use [vcdvcd](https://pypi.org/project/vcdvcd/) VCD parser to plot the simulated waveform using regular matplotlib functions."
+      ]
+    },
+    {
+      "cell_type": "code",
+      "metadata": {
+        "id": "rUdsZqjBAF5o",
+        "colab": {
+          "base_uri": "https://localhost:8080/"
+        },
+        "outputId": "162581a5-e463-446a-93d6-85c62306ce24"
+      },
+      "source": [
+        "!python -m pip install vcdvcd"
+      ],
+      "execution_count": 3,
+      "outputs": [
+        {
+          "output_type": "stream",
+          "name": "stdout",
+          "text": [
+            "Collecting vcdvcd\n",
+            "  Downloading vcdvcd-2.6.0-py3-none-any.whl.metadata (7.9 kB)\n",
+            "Downloading vcdvcd-2.6.0-py3-none-any.whl (12 kB)\n",
+            "Installing collected packages: vcdvcd\n",
+            "Successfully installed vcdvcd-2.6.0\n"
+          ]
+        }
+      ]
+    },
+    {
+      "cell_type": "code",
+      "metadata": {
+        "id": "qfD7ywmvhEyU",
+        "colab": {
+          "base_uri": "https://localhost:8080/",
+          "height": 486
+        },
+        "outputId": "158141dc-368e-4255-b0f3-1d8461a01568"
+      },
+      "source": [
+        "from vcdvcd import VCDVCD\n",
+        "\n",
+        "vcd = VCDVCD('test.vcd')\n",
+        "import matplotlib.pyplot as plt\n",
+        "signals = ['counter_tb.clk', 'counter_tb.rst', 'counter_tb.out[3:0]']\n",
+        "f, plots = plt.subplots(len(signals), 1, sharex=True)\n",
+        "for s, plt in zip(signals, plots):\n",
+        "  x, y = zip(*vcd[s].tv)\n",
+        "  y = [int(n, 2) if n != 'x' else None for n in y]\n",
+        "  plt.step(x, y, label=s, where = 'post')\n",
+        "  plt.set_title(s)\n",
+        "f.tight_layout()\n",
+        "f.show()"
+      ],
+      "execution_count": 4,
+      "outputs": [
+        {
+          "output_type": "display_data",
+          "data": {
+            "text/plain": [
+              "<Figure size 640x480 with 3 Axes>"
+            ],
+            "image/png": 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Hjzpf+/bta+4yAQAAWr127izctWtX+fv7q6SkxKW9pKREERERDdpG+/btNXjwYH3zzTe1LmO322W3290pDQAAoM1z64xdQECA4uLilJ2d7WxzOBzKzs5WYmJig7ZRWVmpL774Qj169HCvUgAAANTJrTN2kpSWlqbU1FQNGTJE8fHxeuqpp1RWVqaJEydKkiZMmKCePXsqIyNDkjR37lwNHTpU5557ro4cOaIFCxaosLBQd955p2e/CQAAQBvndrC76aabdPDgQc2aNUvFxcUaNGiQ3n//feeEir1798rP798nAg8fPqxJkyapuLhYYWFhiouL06ZNm9S/f3/PfQsAAAC4H+wkadq0aZo2bVqNn61fv97l/ZNPPqknn3yyMd0AAADADfxWLAAAgEUQ7AAAACyCYAcAAGARBDsAAACLINgBAABYBMEOAADAIgh2AAAAFkGwAwAAsAiCHQAAgEUQ7AAAACyCYAcAAGARBDsAAACLINgBAABYBMEOAADAIgh2AAAAFkGwAwAAsAiCHQAAgEUQ7AAAACyCYAcAAGARBDsAAACLINgBAABYBMEOAADAIgh2AAAAFkGwAwAAsAiCHQAAgEUQ7AAAACyCYAcAAGARBDsAAACLINgBAABYBMEOAADAIgh2AAAAFkGwAwAAsAiCHQAAgEUQ7AAAACyCYAcAAGARBDsAAACLINgBAABYBMEOAADAIhoV7BYtWqSYmBgFBgYqISFBW7ZsqXP51atXq2/fvgoMDNSFF16od999t1HFAgAAoHbt3F1h1apVSktLU2ZmphISEvTUU08pJSVFO3bsUPfu3astv2nTJo0fP14ZGRn6zW9+o7///e8aO3asPvvsM11wwQUe+RKeYIzRyZ8qa/38REXtnzV02aZuwwo1uLO+L9Tgq+PoCzWwL61TA/vSOjWwL71Tgy9xO9g98cQTmjRpkiZOnChJyszM1Nq1a7V06VLNmDGj2vJPP/20Ro0apT/96U+SpIcfflhZWVl69tlnlZmZWWMf5eXlKi8vd74vLS11t0y3nfypUv1nfeCRbQ35yz+8vg1q8I31qcF3arDCd6AGz6xPDb5TgxW+g69x61JsRUWF8vLylJyc/O8N+PkpOTlZOTk5Na6Tk5PjsrwkpaSk1Lq8JGVkZCg0NNT5ioqKcqfMZjUkOkwd2vtXa+/Q3l9DosNaZBtWqKG29X2hhtY0jr5QA/vSOjWwL61TA/uy+WvwVTZjjGnowkVFRerZs6c2bdqkxMREZ/v999+vDRs2aPPmzdXWCQgI0IoVKzR+/Hhn29/+9jfNmTNHJSUlNfZT0xm7qKgoHT16VCEhIQ0t1y31XYqt0qG9v2w2m1e3YYUa6lrfF2poLePoCzWwL61TA/vSOjWwL5u/hp+vX994N1VpaalCQ0MblIPcvhTbEux2u+x2e4v2abPZFBTQtOHwhW1Qg2+sTw2+U4MVvgM1eGZ9avCdGvgOzcetS7Fdu3aVv79/tTNtJSUlioiIqHGdiIgIt5YHAABA47gVNQMCAhQXF6fs7GyNHTtWkuRwOJSdna1p06bVuE5iYqKys7M1ffp0Z1tWVpbLpdz6VF0tbolJFAAAAL6kKv806O4546aVK1cau91uli9fbgoKCszkyZNN586dTXFxsTHGmFtvvdXMmDHDufynn35q2rVrZx5//HHzr3/9y6Snp5v27dubL774osF97tu3z0jixYsXL168ePFqs699+/bVm5ncvjh800036eDBg5o1a5aKi4s1aNAgvf/++woPD5ck7d27V35+/77CO2zYMP3973/XQw89pAcffFDnnXee1qxZ49Yz7CIjI7Vv3z4FBwc3+82JUVFR2rdvX7NN0mgLGEfPYBw9g3H0HMbSMxhHz2hL42iM0bFjxxQZGVnvsm7NirU6d2adoHaMo2cwjp7BOHoOY+kZjKNnMI4147diAQAALIJgBwAAYBEEu5+x2+1KT09v8WfoWQ3j6BmMo2cwjp7DWHoG4+gZjGPNuMcOAADAIjhjBwAAYBEEOwAAAIsg2AEAAFgEwQ4AAMAiCHYAAAAWQbADAACwCIIdAACARRDsAAAALIJgBwAAYBEEOwAAAIsg2AEAAFgEwQ4AAMAiCHYAAAAWQbADAACwCIIdAHjJ8OHDdcEFF3i7DAAWQrADYGlFRUWaPXu28vPz22T/tSkoKNDs2bO1Z88eb5cCwIMIdgAsraioSHPmzPFqsPNm/7UpKCjQnDlzCHaAxRDsAKARysrKvF1CNQ6HQ6dOnfJ2GQC8iGAHwCO+//573XHHHYqMjJTdbldsbKzuvvtuVVRUSJJ27dqlcePGqUuXLgoKCtLQoUO1du1al20sX75cNput2lmk9evXy2azaf369c62qvvTCgoKNGLECAUFBalnz56aP3++y3oXX3yxJGnixImy2Wyy2Wxavny5c5nNmzdr1KhRCg0NVVBQkJKSkvTpp5+69D979mzZbDYVFBTo5ptvVlhYmC699NJ6x6Qh/UtSXl6ehg0bpg4dOig2NlaZmZn1bluSbDabpk2bpldeeUUDBgyQ3W7X+++/L0lauXKl4uLiFBwcrJCQEF144YV6+umnJZ0Z53HjxkmSRowY4azr5+MLoHVq5+0CALR+RUVFio+P15EjRzR58mT17dtX33//vV5//XWdOHFChw8f1rBhw3TixAnde++9Ouuss7RixQr99re/1euvv65rr722Uf0ePnxYo0aN0nXXXacbb7xRr7/+uh544AFdeOGFGj16tPr166e5c+dq1qxZmjx5sn79619LkoYNGyZJ+uijjzR69GjFxcUpPT1dfn5+WrZsmS6//HJ9/PHHio+Pd+lv3LhxOu+88zRv3jwZY+qtr77+q77DVVddpRtvvFHjx4/Xa6+9prvvvlsBAQG6/fbb6+3jo48+0muvvaZp06apa9euiomJUVZWlsaPH6+RI0fqsccekyT961//0qeffqr77rtPl112me69914988wzevDBB9WvXz9nvQBaOQMATTRhwgTj5+dntm7dWu0zh8Nhpk+fbiSZjz/+2Nl+7NgxExsba2JiYkxlZaUxxphly5YZSWb37t0u21i3bp2RZNatW+dsS0pKMpLMiy++6GwrLy83ERER5vrrr3e2bd261Ugyy5Ytq1bXeeedZ1JSUozD4XC2nzhxwsTGxporrrjC2Zaenm4kmfHjx7s1LnX1//PvsHDhQpfvMGjQINO9e3dTUVFR57YlGT8/P/PVV1+5tN93330mJCTEnD59utZ1V69eXW1MAbR+XIoF0CQOh0Nr1qzRmDFjNGTIkGqf22w2vfvuu4qPj3e5fNmpUydNnjxZe/bsUUFBQaP67tSpk2655Rbn+4CAAMXHx2vXrl31rpufn6+dO3fq5ptv1g8//KBDhw7p0KFDKisr08iRI7Vx40Y5HA6XdaZMmdKoOuvSrl073XXXXS7f4a677tKBAweUl5dX7/pJSUnq37+/S1vnzp1VVlamrKwsj9cLwLcR7AA0ycGDB1VaWlrn89gKCwt1/vnnV2uvuvRXWFjYqL579eolm83m0hYWFqbDhw/Xu+7OnTslSampqerWrZvL64UXXlB5ebmOHj3qsk5sbGyj6qxLZGSkOnbs6NLWp08fSWrQjNWaarrnnnvUp08fjR49Wr169dLtt9/uvPcOgLVxjx0An/HLkFalsrKyxnZ/f/8a200D7n+rOhu3YMECDRo0qMZlOnXq5PK+Q4cO9W63pdVUU/fu3ZWfn68PPvhA7733nt577z0tW7ZMEyZM0IoVK7xQJYCWQrAD0CTdunVTSEiIvvzyy1qXiY6O1o4dO6q1b9++3fm5dOZsmyQdOXLEZbnGntGTag+LvXv3liSFhIQoOTm50dtvbP9VioqKVFZW5nLW7uuvv5YkxcTENLrfgIAAjRkzRmPGjJHD4dA999yjxYsX689//rPOPffceusC0DpxKRZAk/j5+Wns2LF6++23lZubW+1zY4yuuuoqbdmyRTk5Oc72srIyLVmyRDExMc57xKrC1saNG53LVVZWasmSJY2uryow/TIsxsXFqXfv3nr88cd1/PjxausdPHiw0X02pP8qp0+f1uLFi53vKyoqtHjxYnXr1k1xcXHO9u3bt2vv3r0N6vOHH35wee/n56eLLrpIklReXt6gugC0TpyxA9Bk8+bN04cffqikpCRNnjxZ/fr10/79+7V69Wp98sknmjFjhl599VWNHj1a9957r7p06aIVK1Zo9+7deuONN+Tnd+bfmAMGDNDQoUM1c+ZM/fjjj+rSpYtWrlyp06dPN7q23r17q3PnzsrMzFRwcLA6duyohIQExcbG6oUXXtDo0aM1YMAATZw4UT179tT333+vdevWKSQkRG+//XaTx6au/qUz99g99thj2rNnj/r06aNVq1YpPz9fS5YsUfv27Z3b6devn5KSkhr0rLk777xTP/74oy6//HL16tVLhYWF+utf/6pBgwY572scNGiQ/P399dhjj+no0aOy2+26/PLL1b179yZ/ZwBe5O1puQCsobCw0EyYMMF069bN2O12c84555ipU6ea8vJyY4wx3377rbnhhhtM586dTWBgoImPjzfvvPNOte18++23Jjk52djtdhMeHm4efPBBk5WVVePjTgYMGFBt/dTUVBMdHe3S9tZbb5n+/fubdu3aVXv0yLZt28x1111nzjrrLGO32010dLS58cYbTXZ2tnOZqsedHDx4sFFjU1v/Vd8hNzfXJCYmmsDAQBMdHW2effbZatuQZJKSkqq1TZ06tdqyr7/+urnyyitN9+7dTUBAgDn77LPNXXfdZfbv3++y3PPPP2/OOecc4+/vz6NPAIuwGdOAu4wBAADg87jHDgAAwCK4xw4AGqGiokI//vhjncuEhob65CNSAFgXwQ4AGmHTpk0aMWJEncssW7ZMt912W8sUBACSuMcOABrh8OHD9f7k14ABA9SjR48WqggACHYAAACW0SouxTocDhUVFSk4OJinpQMAgDbFGKNjx44pMjLS+dzP2rSKYFdUVKSoqChvlwEAAOA1+/btU69evepcxu1gt3HjRi1YsEB5eXnav3+/3nzzTY0dO7bOddavX6+0tDR99dVXioqK0kMPPeTWDcXBwcGSznyhkJAQd0sGAABotUpLSxUVFeXMQ3VxO9iVlZVp4MCBuv3223XdddfVu/zu3bt19dVXa8qUKXrllVeUnZ2tO++8Uz169FBKSkqD+qy6/BoSEkKwAwAAbVJDbkdzO9iNHj1ao0ePbvDymZmZio2N1cKFCyWd+b3DTz75RE8++WSDg11LMMbo5E+V9S7Xob0/9/m1gIbsD/YFAACumv0eu5ycHCUnJ7u0paSkaPr06bWuU15ervLycuf70tLS5irP6eRPleo/64N6lxsSHabVUxIJFM3IGKMbMnOUV3i4zuXYFwAAuGr2nxQrLi5WeHi4S1t4eLhKS0t18uTJGtfJyMhQaGio8+VLEydyCw836MweGu/kT5X1hjqJfQEAwC/55KzYmTNnKi0tzfm+6qbB5tShvb8K5tZ+afhERaWG/OUfzVoDqst9KFlBAf4ubewLAABq1uzBLiIiQiUlJS5tJSUlCgkJqfU3FO12u+x2e3OX5sJmsykowCdzbpsWFODPfgEAoIGa/VJsYmKisrOzXdqysrKUmJjY3F0DAAC0KW4Hu+PHjys/P1/5+fmSzjzOJD8/X3v37pV05jLqhAkTnMtPmTJFu3bt0v3336/t27frb3/7m1577TX94Q9/8Mw3AAAAgKRGBLvc3FwNHjxYgwcPliSlpaVp8ODBmjVrliRp//79zpAnSbGxsVq7dq2ysrI0cOBALVy4UC+88IJPPeoEAADACty+eWn48OEyxtT6+fLly2tcZ9u2be52BQAAADc0+z12AAAAaBkEOwAAAIsg2AEAAFgEwQ4AAMAiCHYAAAAWQbADAACwCIIdAACARRDsAAAALIJgBwAAYBEEOwAAAIsg2AEAAFgEwQ4AAMAiCHYAAAAWQbADAACwCIIdAACARRDsAAAALIJgBwAAYBEEOwAAAIsg2AEAAFgEwQ4AAMAiCHYAAAAWQbADAACwCIIdAACARRDsAAAALIJgBwAAYBEEOwAAAIsg2AEAAFgEwQ4AAMAiCHYAAAAWQbADAACwCIIdAACARRDsAAAALIJgBwAAYBEEOwAAAIsg2AEAAFgEwQ4AAMAiCHYAAAAWQbADAACwiEYFu0WLFikmJkaBgYFKSEjQli1bal12+fLlstlsLq/AwMBGFwwAAICauR3sVq1apbS0NKWnp+uzzz7TwIEDlZKSogMHDtS6TkhIiPbv3+98FRYWNqloAAAAVOd2sHviiSc0adIkTZw4Uf3791dmZqaCgoK0dOnSWtex2WyKiIhwvsLDw+vso7y8XKWlpS4vAAAA1M2tYFdRUaG8vDwlJyf/ewN+fkpOTlZOTk6t6x0/flzR0dGKiorSNddco6+++qrOfjIyMhQaGup8RUVFuVMmAABAm+RWsDt06JAqKyurnXELDw9XcXFxjeucf/75Wrp0qd566y29/PLLcjgcGjZsmL777rta+5k5c6aOHj3qfO3bt8+dMgEAANqkds3dQWJiohITE53vhw0bpn79+mnx4sV6+OGHa1zHbrfLbrc3d2kAAACW4tYZu65du8rf318lJSUu7SUlJYqIiGjQNtq3b6/Bgwfrm2++cadrAAAA1MOtYBcQEKC4uDhlZ2c72xwOh7Kzs13OytWlsrJSX3zxhXr06OFepQAAAKiT25di09LSlJqaqiFDhig+Pl5PPfWUysrKNHHiREnShAkT1LNnT2VkZEiS5s6dq6FDh+rcc8/VkSNHtGDBAhUWFurOO+/07DcBAABo49wOdjfddJMOHjyoWbNmqbi4WIMGDdL777/vnFCxd+9e+fn9+0Tg4cOHNWnSJBUXFyssLExxcXHatGmT+vfv77lvAQAAgMZNnpg2bZqmTZtW42fr1693ef/kk0/qySefbEw3AAAAcAO/FQsAAGARBDsAAACLINgBAABYBMEOAADAIgh2AAAAFkGwAwAAsAiCHQAAgEUQ7AAAACyCYAcAAGARBDsAAACLINgBAABYBMEOAADAIgh2AAAAFkGwAwAAsAiCHQAAgEUQ7AAAACyCYAcAAGARBDsAAACLINgBAABYBMEOAADAIgh2AAAAFkGwAwAAsAiCHQAAgEUQ7AAAACyCYAcAAGARBDsAAACLINgBAABYBMEOAADAIgh2AAAAFkGwAwAAsAiCHQAAgEUQ7AAAACyCYAcAAGARBDsAAACLINgBAABYBMEOAADAIgh2AAAAFtGoYLdo0SLFxMQoMDBQCQkJ2rJlS53Lr169Wn379lVgYKAuvPBCvfvuu40qFgAAALVzO9itWrVKaWlpSk9P12effaaBAwcqJSVFBw4cqHH5TZs2afz48brjjju0bds2jR07VmPHjtWXX37Z5OIBAADwb+3cXeGJJ57QpEmTNHHiRElSZmam1q5dq6VLl2rGjBnVln/66ac1atQo/elPf5IkPfzww8rKytKzzz6rzMzMJpbvHScqKr1dgqUxvgAANI5bwa6iokJ5eXmaOXOms83Pz0/JycnKycmpcZ2cnBylpaW5tKWkpGjNmjW19lNeXq7y8nLn+9LSUnfKbHZD/vIPb5cAAABQjVuXYg8dOqTKykqFh4e7tIeHh6u4uLjGdYqLi91aXpIyMjIUGhrqfEVFRblTZrPo0N5fQ6LDvF1GmzIkOkwd2vt7uwwAAFoNty/FtoSZM2e6nOUrLS31eriz2WxaPSVRJ3/iMmFL6dDeXzabrcb2grkpzv8GAABnuBXsunbtKn9/f5WUlLi0l5SUKCIiosZ1IiIi3Fpekux2u+x2uzultQibzaagAJ/Mwm0K+wEAgJq5dSk2ICBAcXFxys7OdrY5HA5lZ2crMTGxxnUSExNdlpekrKysWpcHAABA47h92iMtLU2pqakaMmSI4uPj9dRTT6msrMw5S3bChAnq2bOnMjIyJEn33XefkpKStHDhQl199dVauXKlcnNztWTJkgb3aYyR5HuTKAAAAJpbVf6pykN1Mo3w17/+1Zx99tkmICDAxMfHm3/+85/Oz5KSkkxqaqrL8q+99prp06ePCQgIMAMGDDBr1651q799+/YZSbx48eLFixcvXm32tW/fvnozk82YhsQ/73I4HCoqKlJwcHCNN9N7StUkjX379ikkJKTZ+rE6xtEzGEfPYBw9h7H0DMbRM9rSOBpjdOzYMUVGRsrPr+676FrFHeh+fn7q1atXi/UXEhJi+T8kLYFx9AzG0TMYR89hLD2DcfSMtjKOoaGhDVquUb8VCwAAAN9DsAMAALAIgt3P2O12paen++Qz9FoTxtEzGEfPYBw9h7H0DMbRMxjHmrWKyRMAAACoH2fsAAAALIJgBwAAYBEEOwAAAIsg2AEAAFgEwQ4AAMAiCHYAAAAWQbADAACwCIIdAACARRDsAAAALIJgBwAAYBEEOwAAAIsg2AEAAFgEwQ4AAMAiCHYAAAAWQbADgHoMHz5cF1xwgbfLaBCbzeZ8Pf74416p4amnnnKp49ChQ16pA2iLCHYAfEJRUZFmz56t/Pz8Ntm/OwoKCjR79mzt2bOnxs+vvfZavfTSS7r66qudbUVFRbrlllt0/vnnKzg4WJ07d1Z8fLxWrFghY0yD+960aZMuvfRSBQUFKSIiQvfee6+OHz/ussyoUaP00ksv6dprr23U9wPQeO28XQAASGeCx5w5cxQTE6NBgwa1uf7dUVBQoDlz5mj48OGKiYmp9vlFF12kW265xaXt0KFD+u6773TDDTfo7LPP1k8//aSsrCzddttt2rFjh+bNm1dvv/n5+Ro5cqT69eunJ554Qt99950ef/xx7dy5U++9955zub59+6pv37765ptv9Oabbzb5+wJoOIIdAEsrKytTx44dvV2G11100UVav369S9u0adM0ZswYPfPMM3r44Yfl7+9f5zYefPBBhYWFaf369QoJCZEkxcTEaNKkSfrwww915ZVXNlf5ABqIS7FAG/P999/rjjvuUGRkpOx2u2JjY3X33XeroqJCkrRr1y6NGzdOXbp0UVBQkIYOHaq1a9e6bGP58uWy2WzVLgWuX79eNpvNJUBU3Z9WUFCgESNGKCgoSD179tT8+fNd1rv44oslSRMnTnTem7V8+XLnMps3b9aoUaMUGhqqoKAgJSUl6dNPP3Xpf/bs2bLZbCooKNDNN9+ssLAwXXrppfWOSUP6l6S8vDwNGzZMHTp0UGxsrDIzM+vdtiSdPn1aDz/8sHr37i273a6YmBg9+OCDKi8vd1nOZrNp9uzZ1daPiYnRbbfdJunM2I8bN06SNGLECGetvwxtDRUTE6MTJ044978knThxQtu3b3e5N660tFRZWVm65ZZbnKFOkiZMmKBOnTrptddea1T/ADyLYAe0IUVFRYqPj9fKlSt100036ZlnntGtt96qDRs26MSJEyopKdGwYcP0wQcf6J577tEjjzyiU6dO6be//W2TLqkdPnxYo0aN0sCBA7Vw4UL17dtXDzzwgPPyXb9+/TR37lxJ0uTJk/XSSy/ppZde0mWXXSZJ+uijj3TZZZeptLRU6enpmjdvno4cOaLLL79cW7ZsqdbfuHHjdOLECc2bN0+TJk2qt776+q/6DldddZXi4uI0f/589erVS3fffbeWLl1a7/bvvPNOzZo1S7/61a/05JNPKikpSRkZGfrd735X/+D9wmWXXaZ7771X0pkzaFW19uvXr0Hrnzx5UocOHdKePXu0YsUKLVu2TImJierQoYNzmS1btqhfv3569tlnnW1ffPGFTp8+rSFDhrhsLyAgQIMGDdK2bdvc/i4AmoEB0GZMmDDB+Pn5ma1bt1b7zOFwmOnTpxtJ5uOPP3a2Hzt2zMTGxpqYmBhTWVlpjDFm2bJlRpLZvXu3yzbWrVtnJJl169Y525KSkowk8+KLLzrbysvLTUREhLn++uudbVu3bjWSzLJly6rVdd5555mUlBTjcDic7SdOnDCxsbHmiiuucLalp6cbSWb8+PFujUtd/f/8OyxcuNDlOwwaNMh0797dVFRU1Lrd/Px8I8nceeedLu3/7//9PyPJfPTRR842SSY9Pb3aNqKjo01qaqrz/erVq6uNc33bqJKRkWEkOV8jR440e/fudVmmaj/+fDtVfW7cuLHaNseNG2ciIiKqtVftj4MHD9ZaDwDP4owd0EY4HA6tWbNGY8aMqXbWRTpzGfDdd99VfHy8y+XLTp06afLkydqzZ48KCgoa1XenTp1cbuYPCAhQfHy8du3aVe+6+fn52rlzp26++Wb98MMPOnTokA4dOqSysjKNHDlSGzdulMPhcFlnypQpjaqzLu3atdNdd93l8h3uuusuHThwQHl5ebWu9+6770qS0tLSXNr/+Mc/SlK1y9zNbfz48crKytLf//533XzzzZLOnMX7ueHDh8sY43JZuGoZu91ebZuBgYHVtgHAO5g8AbQRBw8eVGlpaZ3PYyssLFRCQkK19qrLfIWFhY16nluvXr1ks9lc2sLCwvT555/Xu+7OnTslSampqbUuc/ToUYWFhTnfx8bGul1jfSIjI6tNwujTp48kac+ePRo6dGiN6xUWFsrPz0/nnnuuS3tERIQ6d+6swsJCj9dal+joaEVHR0s6E/ImT56s5ORk7dixw+Vy7C9VffbL+wIl6dSpU3WuC6DlEOwAuO2XIa1KZWVlje21zbY0DXh+WtXZuAULFtT6GJJOnTq5vPfFkFHbmDVEbePqCTfccIOef/55bdy4USkpKbUu16NHD0nS/v37q322f/9+RUZGNluNABqOYAe0Ed26dVNISIi+/PLLWpeJjo7Wjh07qrVv377d+bkk59mxI0eOuCzXlLNPtQWf3r17S5JCQkKUnJzc6O03tv8qRUVF1R6d8vXXX0tSjc+SqxIdHS2Hw6GdO3e6THAoKSnRkSNHnGMqnRnXX45pRUVFtTDVlJD4S1WXUI8ePVrnchdccIHatWun3Nxc3XjjjS715efnu7QB8B7usQPaCD8/P40dO1Zvv/22cnNzq31ujNFVV12lLVu2KCcnx9leVlamJUuWKCYmRv3795f077C1ceNG53KVlZVasmRJo+urCky/DDZxcXHq3bu3Hn/88Wq/cCCducTsCbX1X+X06dNavHix831FRYUWL16sbt26KS4uztm+fft27d271/n+qquuknTmZ7Z+7oknnpAkl1+H6N27t8uYStKSJUuqnbGrr9aa1DZO//Vf/yWbzaZf/epXzraaHncSGhqq5ORkvfzyyzp27Jiz/aWXXtLx48edj2AB4F2csQPakHnz5unDDz9UUlKSJk+erH79+mn//v1avXq1PvnkE82YMUOvvvqqRo8erXvvvVddunTRihUrtHv3br3xxhvy8zvzb8EBAwZo6NChmjlzpn788Ud16dJFK1eu1OnTpxtdW+/evdW5c2dlZmYqODhYHTt2VEJCgmJjY/XCCy9o9OjRGjBggCZOnKiePXvq+++/17p16xQSEqK33367yWNTV//SmXvsHnvsMe3Zs0d9+vTRqlWrlJ+fryVLlqh9+/bO7fTr109JSUnO58oNHDhQqampWrJkiY4cOaKkpCRt2bJFK1as0NixYzVixAjnunfeeaemTJmi66+/XldccYX+93//Vx988IG6du3qUuugQYPk7++vxx57TEePHpXdbtfll1+u7t271/r9HnnkEX366acaNWqUzj77bP3444964403tHXrVv3Hf/yHyz2AW7Zs0YgRI5Senu4ygeKRRx7RsGHDnH9+vvvuOy1cuFBXXnmlRo0a1ZThB+ApXp6VC6CFFRYWmgkTJphu3boZu91uzjnnHDN16lRTXl5ujDHm22+/NTfccIPp3LmzCQwMNPHx8eadd96ptp1vv/3WJCcnG7vdbsLDw82DDz5osrKyanzcyYABA6qtn5qaaqKjo13a3nrrLdO/f3/Trl27ao8e2bZtm7nuuuvMWWedZex2u4mOjjY33nijyc7Odi7T1Mdr1NZ/1XfIzc01iYmJJjAw0ERHR5tnn3222jYkmaSkJJe2n376ycyZM8fExsaa9u3bm6ioKDNz5kxz6tQpl+UqKyvNAw88YLp27WqCgoJMSkqK+eabb6o97sQYY55//nlzzjnnGH9/f5cxVy2PO/nwww/Nb37zGxMZGWnat29vgoODzSWXXGKWLVvm8hgZY2p+3EmVjz/+2AwbNswEBgaabt26malTp5rS0tIax5PHnQAtz2aMG7/+DADwaTabTX/60590//33q2PHjl6ZSHLq1CkdP35c8+fP14IFC3Tw4MFqZx0BNA/usQMAi1mwYIG6deumRYsWeaX/zMxMdevWTQsWLPBK/0Bbxj12ACytoqJCP/74Y53LhIaG+uQjUhojKyvL+d9Vz9lraddff73L8w5DQ0O9UgfQFnEpFoClrV+/3mWCQk2WLVum2267rWUKAoBmRLADYGmHDx+u8ye/pDOzfKsewAsArRnBDgAAwCJaxT12DodDRUVFCg4O9ugT1wEAAHydMUbHjh1TZGSk83mitWkVwa6oqEhRUVHeLgMAAMBr9u3bp169etW5TKsIdsHBwZLOfKGQkBAvVwMAANBySktLFRUV5cxDdWkVwa7q8mtISAjBDgAAtEkNuR2tVQQ7AID1GWN08qfKJm+nQ3t/7sdGm0WwAwB4nTFGN2TmKK/wcJO3NSQ6TKunJBLu0Cbxk2IAAK87+VOlR0KdJOUWHvbImT+gNeKMHQDAp+Q+lKygAH+31ztRUakhf/lHM1QEtB4EOwCATwkK8FdQAH89AY3BpVgAAACL4J9EAACPaMqs1hMV3BMHeALBDgDQZJ6c1Qqg8bgUCwBoMk/Nah0SHaYO7d2fOAHgDM7YAQA8qrGzWiUeLgw0FcEOAOBRzGoFvIdLsQAAABZBsAMAALAIzpUDAJr0qBKJx5UAvoJgBwBtHI8qAayDS7EA0MZ56lElEo8rAbyNM3YAAKemPKpE4nElgLcR7AAATjyqBGjduBQLAABgEfyzDAAsoCmzWpnRClgHwQ4AWjlmtQKowqVYAGjlPDWrlRmtQOvHGTsAsJCmzGplRivQ+hHsAMBCmNUKtG1cigUAALAI/lkHAD6AWa0APIFgBwBexqxWAJ7CpVgA8DJmtQLwFM7YAYAPYVYrgKYg2AGAD2FWK4CmaPKl2I0bN2rMmDGKjIyUzWbTmjVrXD43xmjWrFnq0aOHOnTooOTkZO3cubOp3QIAAOAXmhzsysrKNHDgQC1atKjGz+fPn69nnnlGmZmZ2rx5szp27KiUlBSdOnWqqV0DAADgZ5p8vn/06NEaPXp0jZ8ZY/TUU0/poYce0jXXXCNJevHFFxUeHq41a9bod7/7XVO7BwCva8qjSiQeVwLAc5r1Ro7du3eruLhYycnJzrbQ0FAlJCQoJyen1mBXXl6u8vJy5/vS0tLmLBMAGo1HlQDwJc36uJPi4mJJUnh4uEt7eHi487OaZGRkKDQ01PmKiopqzjIBoNE89agSiceVAGg6n5x6NXPmTKWlpTnfl5aWEu4A+LymPKpE4nElAJquWYNdRESEJKmkpEQ9evRwtpeUlGjQoEG1rme322W325uzNADwOB5VAsDbmvVSbGxsrCIiIpSdne1sKy0t1ebNm5WYmNicXQMAALQ5Tf6n5fHjx/XNN9843+/evVv5+fnq0qWLzj77bE2fPl1/+ctfdN555yk2NlZ//vOfFRkZqbFjxza1awDwiKbMamVGK2BNPz8utKbbJJoc7HJzczVixAjn+6p741JTU7V8+XLdf//9Kisr0+TJk3XkyBFdeumlev/99xUYGNjUrgGgyZjVCqAmJ3+qVP9ZH0iSCuamtJrbLJpc5fDhw2WMqfVzm82muXPnau7cuU3tCgA8zlOzWpnRCsAXtI74CQAtoCmzWlvTpRoA1kWwA4D/w6xWAK1ds86KBQAAQMsh2AEAAFgE1xwAtGpNeVSJxONKAKtqq8cGgh2AVotHlQCoSVs+NnApFkCr5alHlUg8rgSwkrZ8bOCMHQBLaMqjSiQeVwJYVVs7NhDsAFgCjyoBUJO2dmzgUiwAAIBFtJ0IC8AnNWXmWmudtQagfhwbGodgB8Br2vLMNQC149jQeFyKBeA1npq51tpmrQGoG8eGxuOMHQCf0JSZa61t1hqAhuPY4B6CHQCf0NZmrgFoGI4N7uFSLAAAgEUQ7AAAACyCc5sAGq2t/sg2gLpxbPAegh2ARuFxBABqwrHBu7gUC6BR2vKPbAOoHccG7+KMHYAma2s/sg2gYTg2tDyCHYAm43EEAGrCsaHlcSkWAADAIojRaHFNnS1VhVP0TcePbAOoCceG1otghxblydlSQ6LDtHpKIuGukZi5BqAmHBtaNy7FokV5crZUbuFhj5z5a6v4kW0ANeHY0Lpxxg5e09jZUicqKjXkL/9ohoraLn5kG0BNODa0PgQ7eA2zpXwH+wJATTg2tD5cigUAALAIgh0AAIBFcH4VbmMavO9gXwD4paY+UopjQ+tGsINbmAbvO9gXAH6J4wK4FAu3MA3ed7AvAPySJx8pxbGhdeKMHRqNafC+g30B4JeaclyQODa0VgQ7NBrT4H0H+wLAL3FcaJu4FAsAAGARRPk2iJmUvoGZawBqwjEaTUGwa2OYMeUb2A8AasKxAU3Fpdg2hpmUvoGZawBqwjEaTcUZuzaMmZS+gZlrAGrCMRqNQbBrw5gx5RvYDwBqwrEBjcGlWAAAAIsg2AEAAFgE53hbGR6R4Tt4JAGAmnBsgDcR7FoRpsH7DvYFgJpwbIC3cSm2FeERGb6DRxIAqAnHBngbZ+xaKR6R4Tt4JAGAmnBsgDcQ7FoppsH7DvYFgJpwbIA3cCkWAADAIvinRAtjtpRvYHYxgJpwbEBrR7BrQcyW8g3sBwA14dgAK+BSbAtitpRvYHYxgJpwbIAVcMbOS5gt5RuYXQygJhwb0FoR7LyE2VK+gf0AoCYcG9Batdil2EWLFikmJkaBgYFKSEjQli1bWqprAACANqFF/jmyatUqpaWlKTMzUwkJCXrqqaeUkpKiHTt2qHv37i1RQpM1daaUxGyp5tCYMWU/ANbHsQFtVYsEuyeeeEKTJk3SxIkTJUmZmZlau3atli5dqhkzZlRbvry8XOXl5c73paWlLVFmnU7+VKn+sz7wdhn4hSF/+Ye3SwDggzg2oK1q9kuxFRUVysvLU3Jy8r879fNTcnKycnJyalwnIyNDoaGhzldUVFRzl9mimC3VNB3a+2tIdFiTt8N+AKyFYwMg2Ywxpjk7KCoqUs+ePbVp0yYlJiY62++//35t2LBBmzdvrrZOTWfsoqKidPToUYWEhDRnubXyxKXYKsyWajpP7A/2A2A9HBtgRaWlpQoNDW1QDvLJKT92u112u93bZbiw2WzMkPIh7A8ANeHYgLau2S/Fdu3aVf7+/iopKXFpLykpUURERHN3DwAA0GY0+z9rAgICFBcXp+zsbI0dO1aS5HA4lJ2drWnTpjVoG1VXi31hEgUAAEBLqso/Dbl7rkXOV6elpSk1NVVDhgxRfHy8nnrqKZWVlTlnydbn2LFjkmS5SRQAAAANdezYMYWGhta5TIsEu5tuukkHDx7UrFmzVFxcrEGDBun9999XeHh4g9aPjIzUvn37FBwc3Kw3tFZN0ti3b5/XJmlYAePoGYyjZzCOnsNYegbj6BltaRyNMTp27JgiIyPrXbbZZ8W2Ju7MOkHtGEfPYBw9g3H0HMbSMxhHz2Aca9ZiPykGAACA5kWwAwAAsAiC3c/Y7Xalp6f73DP0WhvG0TMYR89gHD2HsfQMxtEzGMeacY8dAACARXDGDgAAwCIIdgAAABZBsAMAALAIgh0AAIBFEOwAAAAsgmD3M4sWLVJMTIwCAwOVkJCgLVu2eLskn7Zx40aNGTNGkZGRstlsWrNmjcvnxhjNmjVLPXr0UIcOHZScnKydO3d6p1gflpGRoYsvvljBwcHq3r27xo4dqx07drgsc+rUKU2dOlVnnXWWOnXqpOuvv14lJSVeqtg3Pffcc7rooosUEhKikJAQJSYm6r333nN+zhg2zqOPPiqbzabp06c72xjL+s2ePVs2m83l1bdvX+fnjGHDff/997rlllt01llnqUOHDrrwwguVm5vr/Jy/a1wR7P7PqlWrlJaWpvT0dH322WcaOHCgUlJSdODAAW+X5rPKyso0cOBALVq0qMbP58+fr2eeeUaZmZnavHmzOnbsqJSUFJ06daqFK/VtGzZs0NSpU/XPf/5TWVlZ+umnn3TllVeqrKzMucwf/vAHvf3221q9erU2bNigoqIiXXfddV6s2vf06tVLjz76qPLy8pSbm6vLL79c11xzjb766itJjGFjbN26VYsXL9ZFF13k0s5YNsyAAQO0f/9+5+uTTz5xfsYYNszhw4d1ySWXqH379nrvvfdUUFCghQsXKiwszLkMf9f8goExxpj4+HgzdepU5/vKykoTGRlpMjIyvFhV6yHJvPnmm873DofDREREmAULFjjbjhw5Yux2u3n11Ve9UGHrceDAASPJbNiwwRhzZtzat29vVq9e7VzmX//6l5FkcnJyvFVmqxAWFmZeeOEFxrARjh07Zs477zyTlZVlkpKSzH333WeM4c9jQ6Wnp5uBAwfW+Blj2HAPPPCAufTSS2v9nL9rquOMnaSKigrl5eUpOTnZ2ebn56fk5GTl5OR4sbLWa/fu3SouLnYZ09DQUCUkJDCm9Th69KgkqUuXLpKkvLw8/fTTTy5j2bdvX5199tmMZS0qKyu1cuVKlZWVKTExkTFshKlTp+rqq692GTOJP4/u2LlzpyIjI3XOOefo97//vfbu3SuJMXTH//zP/2jIkCEaN26cunfvrsGDB+v55593fs7fNdUR7CQdOnRIlZWVCg8Pd2kPDw9XcXGxl6pq3arGjTF1j8Ph0PTp03XJJZfoggsukHRmLAMCAtS5c2eXZRnL6r744gt16tRJdrtdU6ZM0Ztvvqn+/fszhm5auXKlPvvsM2VkZFT7jLFsmISEBC1fvlzvv/++nnvuOe3evVu//vWvdezYMcbQDbt27dJzzz2n8847Tx988IHuvvtu3XvvvVqxYoUk/q6pSTtvFwDg36ZOnaovv/zS5V4cNNz555+v/Px8HT16VK+//rpSU1O1YcMGb5fVquzbt0/33XefsrKyFBgY6O1yWq3Ro0c7//uiiy5SQkKCoqOj9dprr6lDhw5erKx1cTgcGjJkiObNmydJGjx4sL788ktlZmYqNTXVy9X5Js7YSeratav8/f2rzUgqKSlRRESEl6pq3arGjTFtuGnTpumdd97RunXr1KtXL2d7RESEKioqdOTIEZflGcvqAgICdO655youLk4ZGRkaOHCgnn76acbQDXl5eTpw4IB+9atfqV27dmrXrp02bNigZ555Ru3atVN4eDhj2QidO3dWnz599M033/Dn0Q09evRQ//79Xdr69evnvKzN3zXVEex05i+DuLg4ZWdnO9scDoeys7OVmJjoxcpar9jYWEVERLiMaWlpqTZv3syY/oIxRtOmTdObb76pjz76SLGxsS6fx8XFqX379i5juWPHDu3du5exrIfD4VB5eTlj6IaRI0fqiy++UH5+vvM1ZMgQ/f73v3f+N2PpvuPHj+vbb79Vjx49+PPohksuuaTa45++/vprRUdHS+Lvmhp5e/aGr1i5cqWx2+1m+fLlpqCgwEyePNl07tzZFBcXe7s0n3Xs2DGzbds2s23bNiPJPPHEE2bbtm2msLDQGGPMo48+ajp37mzeeust8/nnn5trrrnGxMbGmpMnT3q5ct9y9913m9DQULN+/Xqzf/9+5+vEiRPOZaZMmWLOPvts89FHH5nc3FyTmJhoEhMTvVi175kxY4bZsGGD2b17t/n888/NjBkzjM1mMx9++KExhjFsip/PijWGsWyIP/7xj2b9+vVm9+7d5tNPPzXJycmma9eu5sCBA8YYxrChtmzZYtq1a2ceeeQRs3PnTvPKK6+YoKAg8/LLLzuX4e8aVwS7n/nrX/9qzj77bBMQEGDi4+PNP//5T2+X5NPWrVtnJFV7paamGmPOTEP/85//bMLDw43dbjcjR440O3bs8G7RPqimMZRkli1b5lzm5MmT5p577jFhYWEmKCjIXHvttWb//v3eK9oH3X777SY6OtoEBASYbt26mZEjRzpDnTGMYVP8MtgxlvW76aabTI8ePUxAQIDp2bOnuemmm8w333zj/JwxbLi3337bXHDBBcZut5u+ffuaJUuWuHzO3zWubMYY451zhQAAAPAk7rEDAACwCIIdAACARRDsAAAALIJgBwAAYBEEOwAAAIsg2AEAAFgEwQ4AAMAiCHYAAAAWQbADAACwCIIdAACARRDsAAAALOL/A76nuyJ+nX2jAAAAAElFTkSuQmCC\n"
+          },
+          "metadata": {}
+        }
+      ]
+    },
+    {
+      "cell_type": "markdown",
+      "metadata": {
+        "id": "98X6edTrm2xZ"
+      },
+      "source": [
+        "## 🍡 Treat #2: Yosys synthesis and circuit drawing\n",
+        "\n",
+        "[Yosys](https://yosyshq.net/yosys/) is a versatile tool to synthesize HDL designs to netlist and map them to the underlying technology target.\n",
+        "\n",
+        "This notebook shows how to synthesize a simple 1-bit adder Verilog design to different levels of technology abstraction (standard logic gates, CMOS, LUTs, discrete ICs) and draw the underlying circuit diagrams."
+      ]
+    },
+    {
+      "cell_type": "markdown",
+      "metadata": {
+        "id": "gnWAUQIppudM"
+      },
+      "source": [
+        "### Install packages\n",
+        "\n",
+        "Install packages from the `LiteX-Hub` and `SymbiFlow` channel."
+      ]
+    },
+    {
+      "cell_type": "code",
+      "metadata": {
+        "id": "rRvhEUG-ppJH",
+        "colab": {
+          "base_uri": "https://localhost:8080/"
+        },
+        "outputId": "105d54c5-5d46-4b70-ffdb-c5579c253cb7"
+      },
+      "source": [
+        "!curl -O https://repo.anaconda.com/miniconda/Miniconda3-py37_4.10.3-Linux-x86_64.sh\n",
+        "!bash Miniconda3-py37_4.10.3-Linux-x86_64.sh -b -f -p miniconda-synth/\n",
+        "!miniconda-synth/bin/conda install --yes -c LiteX-Hub yosys\n",
+        "!miniconda-synth/bin/conda install --yes -c SymbiFlow verible"
+      ],
+      "execution_count": 5,
+      "outputs": [
+        {
+          "output_type": "stream",
+          "name": "stdout",
+          "text": [
+            "  % Total    % Received % Xferd  Average Speed   Time    Time     Time  Current\n",
+            "                                 Dload  Upload   Total   Spent    Left  Speed\n",
+            "100 84.9M  100 84.9M    0     0  57.7M      0  0:00:01  0:00:01 --:--:-- 57.7M\n",
+            "PREFIX=/content/miniconda-synth\n",
+            "Unpacking payload ...\n",
+            "Collecting package metadata (current_repodata.json): - \b\b\\ \b\bdone\n",
+            "Solving environment: / \b\b- \b\b\\ \b\bdone\n",
+            "\n",
+            "## Package Plan ##\n",
+            "\n",
+            "  environment location: /content/miniconda-synth\n",
+            "\n",
+            "  added / updated specs:\n",
+            "    - _libgcc_mutex==0.1=main\n",
+            "    - _openmp_mutex==4.5=1_gnu\n",
+            "    - brotlipy==0.7.0=py37h27cfd23_1003\n",
+            "    - ca-certificates==2021.7.5=h06a4308_1\n",
+            "    - certifi==2021.5.30=py37h06a4308_0\n",
+            "    - cffi==1.14.6=py37h400218f_0\n",
+            "    - chardet==4.0.0=py37h06a4308_1003\n",
+            "    - conda-package-handling==1.7.3=py37h27cfd23_1\n",
+            "    - conda==4.10.3=py37h06a4308_0\n",
+            "    - cryptography==3.4.7=py37hd23ed53_0\n",
+            "    - idna==2.10=pyhd3eb1b0_0\n",
+            "    - ld_impl_linux-64==2.35.1=h7274673_9\n",
+            "    - libffi==3.3=he6710b0_2\n",
+            "    - libgcc-ng==9.3.0=h5101ec6_17\n",
+            "    - libgomp==9.3.0=h5101ec6_17\n",
+            "    - libstdcxx-ng==9.3.0=hd4cf53a_17\n",
+            "    - ncurses==6.2=he6710b0_1\n",
+            "    - openssl==1.1.1k=h27cfd23_0\n",
+            "    - pip==21.1.3=py37h06a4308_0\n",
+            "    - pycosat==0.6.3=py37h27cfd23_0\n",
+            "    - pycparser==2.20=py_2\n",
+            "    - pyopenssl==20.0.1=pyhd3eb1b0_1\n",
+            "    - pysocks==1.7.1=py37_1\n",
+            "    - python==3.7.10=h12debd9_4\n",
+            "    - readline==8.1=h27cfd23_0\n",
+            "    - requests==2.25.1=pyhd3eb1b0_0\n",
+            "    - ruamel_yaml==0.15.100=py37h27cfd23_0\n",
+            "    - setuptools==52.0.0=py37h06a4308_0\n",
+            "    - six==1.16.0=pyhd3eb1b0_0\n",
+            "    - sqlite==3.36.0=hc218d9a_0\n",
+            "    - tk==8.6.10=hbc83047_0\n",
+            "    - tqdm==4.61.2=pyhd3eb1b0_1\n",
+            "    - urllib3==1.26.6=pyhd3eb1b0_1\n",
+            "    - wheel==0.36.2=pyhd3eb1b0_0\n",
+            "    - xz==5.2.5=h7b6447c_0\n",
+            "    - yaml==0.2.5=h7b6447c_0\n",
+            "    - zlib==1.2.11=h7b6447c_3\n",
+            "\n",
+            "\n",
+            "The following NEW packages will be INSTALLED:\n",
+            "\n",
+            "  _libgcc_mutex      pkgs/main/linux-64::_libgcc_mutex-0.1-main\n",
+            "  _openmp_mutex      pkgs/main/linux-64::_openmp_mutex-4.5-1_gnu\n",
+            "  brotlipy           pkgs/main/linux-64::brotlipy-0.7.0-py37h27cfd23_1003\n",
+            "  ca-certificates    pkgs/main/linux-64::ca-certificates-2021.7.5-h06a4308_1\n",
+            "  certifi            pkgs/main/linux-64::certifi-2021.5.30-py37h06a4308_0\n",
+            "  cffi               pkgs/main/linux-64::cffi-1.14.6-py37h400218f_0\n",
+            "  chardet            pkgs/main/linux-64::chardet-4.0.0-py37h06a4308_1003\n",
+            "  conda              pkgs/main/linux-64::conda-4.10.3-py37h06a4308_0\n",
+            "  conda-package-han~ pkgs/main/linux-64::conda-package-handling-1.7.3-py37h27cfd23_1\n",
+            "  cryptography       pkgs/main/linux-64::cryptography-3.4.7-py37hd23ed53_0\n",
+            "  idna               pkgs/main/noarch::idna-2.10-pyhd3eb1b0_0\n",
+            "  ld_impl_linux-64   pkgs/main/linux-64::ld_impl_linux-64-2.35.1-h7274673_9\n",
+            "  libffi             pkgs/main/linux-64::libffi-3.3-he6710b0_2\n",
+            "  libgcc-ng          pkgs/main/linux-64::libgcc-ng-9.3.0-h5101ec6_17\n",
+            "  libgomp            pkgs/main/linux-64::libgomp-9.3.0-h5101ec6_17\n",
+            "  libstdcxx-ng       pkgs/main/linux-64::libstdcxx-ng-9.3.0-hd4cf53a_17\n",
+            "  ncurses            pkgs/main/linux-64::ncurses-6.2-he6710b0_1\n",
+            "  openssl            pkgs/main/linux-64::openssl-1.1.1k-h27cfd23_0\n",
+            "  pip                pkgs/main/linux-64::pip-21.1.3-py37h06a4308_0\n",
+            "  pycosat            pkgs/main/linux-64::pycosat-0.6.3-py37h27cfd23_0\n",
+            "  pycparser          pkgs/main/noarch::pycparser-2.20-py_2\n",
+            "  pyopenssl          pkgs/main/noarch::pyopenssl-20.0.1-pyhd3eb1b0_1\n",
+            "  pysocks            pkgs/main/linux-64::pysocks-1.7.1-py37_1\n",
+            "  python             pkgs/main/linux-64::python-3.7.10-h12debd9_4\n",
+            "  readline           pkgs/main/linux-64::readline-8.1-h27cfd23_0\n",
+            "  requests           pkgs/main/noarch::requests-2.25.1-pyhd3eb1b0_0\n",
+            "  ruamel_yaml        pkgs/main/linux-64::ruamel_yaml-0.15.100-py37h27cfd23_0\n",
+            "  setuptools         pkgs/main/linux-64::setuptools-52.0.0-py37h06a4308_0\n",
+            "  six                pkgs/main/noarch::six-1.16.0-pyhd3eb1b0_0\n",
+            "  sqlite             pkgs/main/linux-64::sqlite-3.36.0-hc218d9a_0\n",
+            "  tk                 pkgs/main/linux-64::tk-8.6.10-hbc83047_0\n",
+            "  tqdm               pkgs/main/noarch::tqdm-4.61.2-pyhd3eb1b0_1\n",
+            "  urllib3            pkgs/main/noarch::urllib3-1.26.6-pyhd3eb1b0_1\n",
+            "  wheel              pkgs/main/noarch::wheel-0.36.2-pyhd3eb1b0_0\n",
+            "  xz                 pkgs/main/linux-64::xz-5.2.5-h7b6447c_0\n",
+            "  yaml               pkgs/main/linux-64::yaml-0.2.5-h7b6447c_0\n",
+            "  zlib               pkgs/main/linux-64::zlib-1.2.11-h7b6447c_3\n",
+            "\n",
+            "\n",
+            "Preparing transaction: / \b\b- \b\b\\ \b\b| \b\bdone\n",
+            "Executing transaction: - \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\bdone\n",
+            "installation finished.\n",
+            "WARNING:\n",
+            "    You currently have a PYTHONPATH environment variable set. This may cause\n",
+            "    unexpected behavior when running the Python interpreter in Miniconda3.\n",
+            "    For best results, please verify that your PYTHONPATH only points to\n",
+            "    directories of packages that are compatible with the Python interpreter\n",
+            "    in Miniconda3: /content/miniconda-synth\n",
+            "Collecting package metadata (current_repodata.json): - \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\bdone\n",
+            "Solving environment: / \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\bdone\n",
+            "\n",
+            "\n",
+            "==> WARNING: A newer version of conda exists. <==\n",
+            "  current version: 4.10.3\n",
+            "  latest version: 26.1.1\n",
+            "\n",
+            "Please update conda by running\n",
+            "\n",
+            "    $ conda update -n base -c defaults conda\n",
+            "\n",
+            "\n",
+            "\n",
+            "## Package Plan ##\n",
+            "\n",
+            "  environment location: /content/miniconda-synth\n",
+            "\n",
+            "  added / updated specs:\n",
+            "    - yosys\n",
+            "\n",
+            "\n",
+            "The following packages will be downloaded:\n",
+            "\n",
+            "    package                    |            build\n",
+            "    ---------------------------|-----------------\n",
+            "    ca-certificates-2025.12.2  |       h06a4308_0         125 KB\n",
+            "    openssl-1.1.1w             |       h7f8727e_0         3.7 MB\n",
+            "    yosys-0.13_39_g958c3a46a   |20220202_022309_py37        11.0 MB  LiteX-Hub\n",
+            "    ------------------------------------------------------------\n",
+            "                                           Total:        14.8 MB\n",
+            "\n",
+            "The following NEW packages will be INSTALLED:\n",
+            "\n",
+            "  yosys              LiteX-Hub/linux-64::yosys-0.13_39_g958c3a46a-20220202_022309_py37\n",
+            "\n",
+            "The following packages will be UPDATED:\n",
+            "\n",
+            "  ca-certificates                       2021.7.5-h06a4308_1 --> 2025.12.2-h06a4308_0\n",
+            "  openssl                                 1.1.1k-h27cfd23_0 --> 1.1.1w-h7f8727e_0\n",
+            "\n",
+            "\n",
+            "\n",
+            "Downloading and Extracting Packages\n",
+            "yosys-0.13_39_g958c3 | 11.0 MB   | : 100% 1.0/1 [00:04<00:00,  4.03s/it]\n",
+            "ca-certificates-2025 | 125 KB    | : 100% 1.0/1 [00:00<00:00,  2.16it/s]\n",
+            "openssl-1.1.1w       | 3.7 MB    | : 100% 1.0/1 [00:00<00:00,  2.37it/s]\n",
+            "Preparing transaction: | \b\bdone\n",
+            "Verifying transaction: - \b\b\\ \b\bdone\n",
+            "Executing transaction: / \b\bdone\n",
+            "Collecting package metadata (current_repodata.json): - \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\bdone\n",
+            "Solving environment: - \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\bdone\n",
+            "\n",
+            "\n",
+            "==> WARNING: A newer version of conda exists. <==\n",
+            "  current version: 4.10.3\n",
+            "  latest version: 26.1.1\n",
+            "\n",
+            "Please update conda by running\n",
+            "\n",
+            "    $ conda update -n base -c defaults conda\n",
+            "\n",
+            "\n",
+            "\n",
+            "## Package Plan ##\n",
+            "\n",
+            "  environment location: /content/miniconda-synth\n",
+            "\n",
+            "  added / updated specs:\n",
+            "    - verible\n",
+            "\n",
+            "\n",
+            "The following packages will be downloaded:\n",
+            "\n",
+            "    package                    |            build\n",
+            "    ---------------------------|-----------------\n",
+            "    verible-0.0.836_0000_g1b1294c|  20201231_075710         4.2 MB  SymbiFlow\n",
+            "    ------------------------------------------------------------\n",
+            "                                           Total:         4.2 MB\n",
+            "\n",
+            "The following NEW packages will be INSTALLED:\n",
+            "\n",
+            "  verible            SymbiFlow/linux-64::verible-0.0.836_0000_g1b1294c-20201231_075710\n",
+            "\n",
+            "\n",
+            "\n",
+            "Downloading and Extracting Packages\n",
+            "verible-0.0.836_0000 | 4.2 MB    | : 100% 1.0/1 [00:01<00:00,  1.22s/it]\n",
+            "Preparing transaction: / \b\bdone\n",
+            "Verifying transaction: \\ \b\bdone\n",
+            "Executing transaction: / \b\bdone\n"
+          ]
+        }
+      ]
+    },
+    {
+      "cell_type": "markdown",
+      "metadata": {
+        "id": "qSfpDMU_qqdC"
+      },
+      "source": [
+        "### Lint Verilog\n",
+        "\n",
+        "Use the `%%bash` magic to the `adder` Verilog module with [Verible](https://github.com/chipsalliance/verible)."
+      ]
+    },
+    {
+      "cell_type": "code",
+      "metadata": {
+        "id": "D4IAholPqyy7"
+      },
+      "source": [
+        "%%bash -c 'source miniconda-synth/bin/activate; cat > adder.v; verible-verilog-lint adder.v'\n",
+        "\n",
+        "module adder(\n",
+        "  input wire a,\n",
+        "  input wire b,\n",
+        "  output wire [1:0] out\n",
+        ");\n",
+        "  assign out = a + b;\n",
+        "endmodule"
+      ],
+      "execution_count": 6,
+      "outputs": []
+    },
+    {
+      "cell_type": "markdown",
+      "metadata": {
+        "id": "DvPIEL4LqP_1"
+      },
+      "source": [
+        "### Synth design\n",
+        "\n",
+        "Synthesize design netlist: map to a single `add` cell."
+      ]
+    },
+    {
+      "cell_type": "code",
+      "metadata": {
+        "id": "ItAxi-2Vqky7",
+        "colab": {
+          "base_uri": "https://localhost:8080/"
+        },
+        "outputId": "c1af63e2-aa5f-4385-f3f3-f3bd245e67ca"
+      },
+      "source": [
+        "%%script miniconda-synth/bin/yosys -Q -T\n",
+        "\n",
+        "read -sv adder.v\n",
+        "hierarchy -top adder\n",
+        "\n",
+        "proc; opt\n",
+        "\n",
+        "opt_clean\n",
+        "show -format dot -prefix synth_design\n",
+        "stat"
+      ],
+      "execution_count": 7,
+      "outputs": [
+        {
+          "output_type": "stream",
+          "name": "stdout",
+          "text": [
+            "\n",
+            "yosys> \n",
+            "yosys> \n",
+            "\n",
+            "1. Executing Verilog-2005 frontend: adder.v\n",
+            "Parsing SystemVerilog input from `adder.v' to AST representation.\n",
+            "Storing AST representation for module `$abstract\\adder'.\n",
+            "Successfully finished Verilog frontend.\n",
+            "\n",
+            "yosys> \n",
+            "2. Executing HIERARCHY pass (managing design hierarchy).\n",
+            "\n",
+            "3. Executing AST frontend in derive mode using pre-parsed AST for module `\\adder'.\n",
+            "Generating RTLIL representation for module `\\adder'.\n",
+            "\n",
+            "3.1. Analyzing design hierarchy..\n",
+            "Top module:  \\adder\n",
+            "\n",
+            "3.2. Analyzing design hierarchy..\n",
+            "Top module:  \\adder\n",
+            "Removing unused module `$abstract\\adder'.\n",
+            "Removed 1 unused modules.\n",
+            "\n",
+            "yosys> \n",
+            "yosys> \n",
+            "4. Executing PROC pass (convert processes to netlists).\n",
+            "\n",
+            "4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).\n",
+            "Cleaned up 0 empty switches.\n",
+            "\n",
+            "4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).\n",
+            "Removed a total of 0 dead cases.\n",
+            "\n",
+            "4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).\n",
+            "Removed 0 redundant assignments.\n",
+            "Promoted 0 assignments to connections.\n",
+            "\n",
+            "4.4. Executing PROC_INIT pass (extract init attributes).\n",
+            "\n",
+            "4.5. Executing PROC_ARST pass (detect async resets in processes).\n",
+            "\n",
+            "4.6. Executing PROC_MUX pass (convert decision trees to multiplexers).\n",
+            "\n",
+            "4.7. Executing PROC_DLATCH pass (convert process syncs to latches).\n",
+            "\n",
+            "4.8. Executing PROC_DFF pass (convert process syncs to FFs).\n",
+            "\n",
+            "4.9. Executing PROC_MEMWR pass (convert process memory writes to cells).\n",
+            "\n",
+            "4.10. Executing PROC_CLEAN pass (remove empty switches from decision trees).\n",
+            "Cleaned up 0 empty switches.\n",
+            "\n",
+            "4.11. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module adder.\n",
+            "\n",
+            "5. Executing OPT pass (performing simple optimizations).\n",
+            "\n",
+            "5.1. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module adder.\n",
+            "\n",
+            "5.2. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\adder'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n",
+            "Running muxtree optimizer on module \\adder..\n",
+            "  Creating internal representation of mux trees.\n",
+            "  No muxes found in this module.\n",
+            "Removed 0 multiplexer ports.\n",
+            "\n",
+            "5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n",
+            "  Optimizing cells in module \\adder.\n",
+            "Performed a total of 0 changes.\n",
+            "\n",
+            "5.5. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\adder'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "5.6. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "5.7. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\adder..\n",
+            "Removed 0 unused cells and 1 unused wires.\n",
+            "\n",
+            "5.8. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module adder.\n",
+            "\n",
+            "5.9. Rerunning OPT passes. (Maybe there is more to do..)\n",
+            "\n",
+            "5.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n",
+            "Running muxtree optimizer on module \\adder..\n",
+            "  Creating internal representation of mux trees.\n",
+            "  No muxes found in this module.\n",
+            "Removed 0 multiplexer ports.\n",
+            "\n",
+            "5.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n",
+            "  Optimizing cells in module \\adder.\n",
+            "Performed a total of 0 changes.\n",
+            "\n",
+            "5.12. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\adder'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "5.13. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "5.14. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\adder..\n",
+            "\n",
+            "5.15. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module adder.\n",
+            "\n",
+            "5.16. Finished OPT passes. (There is nothing left to do.)\n",
+            "\n",
+            "yosys> \n",
+            "yosys> \n",
+            "6. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\adder..\n",
+            "\n",
+            "yosys> \n",
+            "7. Generating Graphviz representation of design.\n",
+            "Writing dot description to `synth_design.dot'.\n",
+            "Dumping module adder to page 1.\n",
+            "\n",
+            "yosys> \n",
+            "8. Printing statistics.\n",
+            "\n",
+            "=== adder ===\n",
+            "\n",
+            "   Number of wires:                  3\n",
+            "   Number of wire bits:              4\n",
+            "   Number of public wires:           3\n",
+            "   Number of public wire bits:       4\n",
+            "   Number of memories:               0\n",
+            "   Number of memory bits:            0\n",
+            "   Number of processes:              0\n",
+            "   Number of cells:                  1\n",
+            "     $add                            1\n",
+            "\n",
+            "\n",
+            "yosys> exit\n"
+          ]
+        }
+      ]
+    },
+    {
+      "cell_type": "code",
+      "metadata": {
+        "colab": {
+          "base_uri": "https://localhost:8080/",
+          "height": 182
+        },
+        "id": "vHZ3rQJ6tHXM",
+        "outputId": "8a5b01a8-a954-4bb2-ffaf-313b50c51598"
+      },
+      "source": [
+        "import graphviz\n",
+        "graphviz.Source.from_file('synth_design.dot')"
+      ],
+      "execution_count": 8,
+      "outputs": [
+        {
+          "output_type": "execute_result",
+          "data": {
+            "image/svg+xml": "<?xml version=\"1.0\" encoding=\"UTF-8\" standalone=\"no\"?>\n<!DOCTYPE svg PUBLIC \"-//W3C//DTD SVG 1.1//EN\"\n \"http://www.w3.org/Graphics/SVG/1.1/DTD/svg11.dtd\">\n<!-- Generated by graphviz version 2.43.0 (0)\n -->\n<!-- Title: adder Pages: 1 -->\n<svg width=\"283pt\" height=\"121pt\"\n viewBox=\"0.00 0.00 283.00 121.00\" xmlns=\"http://www.w3.org/2000/svg\" xmlns:xlink=\"http://www.w3.org/1999/xlink\">\n<g id=\"graph0\" class=\"graph\" transform=\"scale(1 1) rotate(0) translate(4 117)\">\n<title>adder</title>\n<polygon fill=\"white\" stroke=\"transparent\" points=\"-4,4 -4,-117 279,-117 279,4 -4,4\"/>\n<text text-anchor=\"middle\" x=\"137.5\" y=\"-7.8\" font-family=\"Times,serif\" font-size=\"14.00\">adder</text>\n<!-- n1 -->\n<g id=\"node1\" class=\"node\">\n<title>n1</title>\n<polygon fill=\"none\" stroke=\"black\" points=\"54,-87.54 54,-102.46 38.18,-113 15.82,-113 0,-102.46 0,-87.54 15.82,-77 38.18,-77 54,-87.54\"/>\n<text text-anchor=\"middle\" x=\"27\" y=\"-91.3\" font-family=\"Times,serif\" font-size=\"14.00\">a</text>\n</g>\n<!-- c7 -->\n<g id=\"node4\" class=\"node\">\n<title>c7</title>\n<polygon fill=\"none\" stroke=\"black\" points=\"90,-45 90,-91 185,-91 185,-45 90,-45\"/>\n<text text-anchor=\"middle\" x=\"103\" y=\"-75.8\" font-family=\"Times,serif\" font-size=\"14.00\">A</text>\n<polyline fill=\"none\" stroke=\"black\" points=\"90,-68 116,-68 \"/>\n<text text-anchor=\"middle\" x=\"103\" y=\"-52.8\" font-family=\"Times,serif\" font-size=\"14.00\">B</text>\n<polyline fill=\"none\" stroke=\"black\" points=\"116,-45 116,-91 \"/>\n<text text-anchor=\"middle\" x=\"137.5\" y=\"-71.8\" font-family=\"Times,serif\" font-size=\"14.00\">$1</text>\n<text text-anchor=\"middle\" x=\"137.5\" y=\"-56.8\" font-family=\"Times,serif\" font-size=\"14.00\">$add</text>\n<polyline fill=\"none\" stroke=\"black\" points=\"159,-45 159,-91 \"/>\n<text text-anchor=\"middle\" x=\"172\" y=\"-64.3\" font-family=\"Times,serif\" font-size=\"14.00\">Y</text>\n</g>\n<!-- n1&#45;&gt;c7 -->\n<g id=\"edge1\" class=\"edge\">\n<title>n1:e&#45;&gt;c7:w</title>\n<path fill=\"none\" stroke=\"black\" d=\"M54,-95C67.27,-95 71.16,-86.21 80.04,-82.09\"/>\n<polygon fill=\"black\" stroke=\"black\" points=\"80.93,-85.47 90,-80 79.49,-78.62 80.93,-85.47\"/>\n</g>\n<!-- n2 -->\n<g id=\"node2\" class=\"node\">\n<title>n2</title>\n<polygon fill=\"none\" stroke=\"black\" points=\"54,-33.54 54,-48.46 38.18,-59 15.82,-59 0,-48.46 0,-33.54 15.82,-23 38.18,-23 54,-33.54\"/>\n<text text-anchor=\"middle\" x=\"27\" y=\"-37.3\" font-family=\"Times,serif\" font-size=\"14.00\">b</text>\n</g>\n<!-- n2&#45;&gt;c7 -->\n<g id=\"edge2\" class=\"edge\">\n<title>n2:e&#45;&gt;c7:w</title>\n<path fill=\"none\" stroke=\"black\" d=\"M54,-41C67.27,-41 71.16,-49.79 80.04,-53.91\"/>\n<polygon fill=\"black\" stroke=\"black\" points=\"79.49,-57.38 90,-56 80.93,-50.53 79.49,-57.38\"/>\n</g>\n<!-- n3 -->\n<g id=\"node3\" class=\"node\">\n<title>n3</title>\n<polygon fill=\"none\" stroke=\"black\" points=\"275,-60.54 275,-75.46 259.18,-86 236.82,-86 221,-75.46 221,-60.54 236.82,-50 259.18,-50 275,-60.54\"/>\n<text text-anchor=\"middle\" x=\"248\" y=\"-64.3\" font-family=\"Times,serif\" font-size=\"14.00\">out</text>\n</g>\n<!-- c7&#45;&gt;n3 -->\n<g id=\"edge3\" class=\"edge\">\n<title>c7:e&#45;&gt;n3:w</title>\n<path fill=\"none\" stroke=\"black\" stroke-width=\"3\" d=\"M185,-68C197,-68 202.25,-68 210.88,-68\"/>\n<polygon fill=\"black\" stroke=\"black\" stroke-width=\"3\" points=\"211,-71.5 221,-68 211,-64.5 211,-71.5\"/>\n</g>\n</g>\n</svg>\n",
+            "text/plain": [
+              "<graphviz.sources.Source at 0x7ee01526ca10>"
+            ]
+          },
+          "metadata": {},
+          "execution_count": 8
+        }
+      ]
+    },
+    {
+      "cell_type": "markdown",
+      "metadata": {
+        "id": "k2TGPWtIup5J"
+      },
+      "source": [
+        "### Synth gates\n",
+        "\n",
+        "Synthesize gate netlist: map to built-in `XOR` and `AND` logic gates."
+      ]
+    },
+    {
+      "cell_type": "code",
+      "metadata": {
+        "id": "XJHob_xTup5V",
+        "colab": {
+          "base_uri": "https://localhost:8080/"
+        },
+        "outputId": "a0c9251a-9b31-48b8-bbc6-59d52a8380a1"
+      },
+      "source": [
+        "%%script miniconda-synth/bin/yosys -Q -T\n",
+        "\n",
+        "read -sv adder.v\n",
+        "hierarchy -top adder\n",
+        "\n",
+        "proc; opt\n",
+        "techmap; opt\n",
+        "\n",
+        "opt_clean\n",
+        "show -format dot -prefix synth_gate\n",
+        "stat"
+      ],
+      "execution_count": 9,
+      "outputs": [
+        {
+          "output_type": "stream",
+          "name": "stdout",
+          "text": [
+            "\n",
+            "yosys> \n",
+            "yosys> \n",
+            "\n",
+            "1. Executing Verilog-2005 frontend: adder.v\n",
+            "Parsing SystemVerilog input from `adder.v' to AST representation.\n",
+            "Storing AST representation for module `$abstract\\adder'.\n",
+            "Successfully finished Verilog frontend.\n",
+            "\n",
+            "yosys> \n",
+            "2. Executing HIERARCHY pass (managing design hierarchy).\n",
+            "\n",
+            "3. Executing AST frontend in derive mode using pre-parsed AST for module `\\adder'.\n",
+            "Generating RTLIL representation for module `\\adder'.\n",
+            "\n",
+            "3.1. Analyzing design hierarchy..\n",
+            "Top module:  \\adder\n",
+            "\n",
+            "3.2. Analyzing design hierarchy..\n",
+            "Top module:  \\adder\n",
+            "Removing unused module `$abstract\\adder'.\n",
+            "Removed 1 unused modules.\n",
+            "\n",
+            "yosys> \n",
+            "yosys> \n",
+            "4. Executing PROC pass (convert processes to netlists).\n",
+            "\n",
+            "4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).\n",
+            "Cleaned up 0 empty switches.\n",
+            "\n",
+            "4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).\n",
+            "Removed a total of 0 dead cases.\n",
+            "\n",
+            "4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).\n",
+            "Removed 0 redundant assignments.\n",
+            "Promoted 0 assignments to connections.\n",
+            "\n",
+            "4.4. Executing PROC_INIT pass (extract init attributes).\n",
+            "\n",
+            "4.5. Executing PROC_ARST pass (detect async resets in processes).\n",
+            "\n",
+            "4.6. Executing PROC_MUX pass (convert decision trees to multiplexers).\n",
+            "\n",
+            "4.7. Executing PROC_DLATCH pass (convert process syncs to latches).\n",
+            "\n",
+            "4.8. Executing PROC_DFF pass (convert process syncs to FFs).\n",
+            "\n",
+            "4.9. Executing PROC_MEMWR pass (convert process memory writes to cells).\n",
+            "\n",
+            "4.10. Executing PROC_CLEAN pass (remove empty switches from decision trees).\n",
+            "Cleaned up 0 empty switches.\n",
+            "\n",
+            "4.11. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module adder.\n",
+            "\n",
+            "5. Executing OPT pass (performing simple optimizations).\n",
+            "\n",
+            "5.1. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module adder.\n",
+            "\n",
+            "5.2. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\adder'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n",
+            "Running muxtree optimizer on module \\adder..\n",
+            "  Creating internal representation of mux trees.\n",
+            "  No muxes found in this module.\n",
+            "Removed 0 multiplexer ports.\n",
+            "\n",
+            "5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n",
+            "  Optimizing cells in module \\adder.\n",
+            "Performed a total of 0 changes.\n",
+            "\n",
+            "5.5. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\adder'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "5.6. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "5.7. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\adder..\n",
+            "Removed 0 unused cells and 1 unused wires.\n",
+            "\n",
+            "5.8. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module adder.\n",
+            "\n",
+            "5.9. Rerunning OPT passes. (Maybe there is more to do..)\n",
+            "\n",
+            "5.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n",
+            "Running muxtree optimizer on module \\adder..\n",
+            "  Creating internal representation of mux trees.\n",
+            "  No muxes found in this module.\n",
+            "Removed 0 multiplexer ports.\n",
+            "\n",
+            "5.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n",
+            "  Optimizing cells in module \\adder.\n",
+            "Performed a total of 0 changes.\n",
+            "\n",
+            "5.12. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\adder'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "5.13. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "5.14. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\adder..\n",
+            "\n",
+            "5.15. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module adder.\n",
+            "\n",
+            "5.16. Finished OPT passes. (There is nothing left to do.)\n",
+            "\n",
+            "yosys> \n",
+            "6. Executing TECHMAP pass (map to technology primitives).\n",
+            "\n",
+            "6.1. Executing Verilog-2005 frontend: /content/miniconda-synth/bin/../share/yosys/techmap.v\n",
+            "Parsing Verilog input from `/content/miniconda-synth/bin/../share/yosys/techmap.v' to AST representation.\n",
+            "Generating RTLIL representation for module `\\_90_simplemap_bool_ops'.\n",
+            "Generating RTLIL representation for module `\\_90_simplemap_reduce_ops'.\n",
+            "Generating RTLIL representation for module `\\_90_simplemap_logic_ops'.\n",
+            "Generating RTLIL representation for module `\\_90_simplemap_compare_ops'.\n",
+            "Generating RTLIL representation for module `\\_90_simplemap_various'.\n",
+            "Generating RTLIL representation for module `\\_90_simplemap_registers'.\n",
+            "Generating RTLIL representation for module `\\_90_shift_ops_shr_shl_sshl_sshr'.\n",
+            "Generating RTLIL representation for module `\\_90_shift_shiftx'.\n",
+            "Generating RTLIL representation for module `\\_90_fa'.\n",
+            "Generating RTLIL representation for module `\\_90_lcu'.\n",
+            "Generating RTLIL representation for module `\\_90_alu'.\n",
+            "Generating RTLIL representation for module `\\_90_macc'.\n",
+            "Generating RTLIL representation for module `\\_90_alumacc'.\n",
+            "Generating RTLIL representation for module `\\$__div_mod_u'.\n",
+            "Generating RTLIL representation for module `\\$__div_mod_trunc'.\n",
+            "Generating RTLIL representation for module `\\_90_div'.\n",
+            "Generating RTLIL representation for module `\\_90_mod'.\n",
+            "Generating RTLIL representation for module `\\$__div_mod_floor'.\n",
+            "Generating RTLIL representation for module `\\_90_divfloor'.\n",
+            "Generating RTLIL representation for module `\\_90_modfloor'.\n",
+            "Generating RTLIL representation for module `\\_90_pow'.\n",
+            "Generating RTLIL representation for module `\\_90_pmux'.\n",
+            "Generating RTLIL representation for module `\\_90_demux'.\n",
+            "Generating RTLIL representation for module `\\_90_lut'.\n",
+            "Successfully finished Verilog frontend.\n",
+            "\n",
+            "6.2. Continuing TECHMAP pass.\n",
+            "Running \"alumacc\" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=1:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=2:394426c56d1a028ba8fdd5469b163e04011def47.\n",
+            "Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=1:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=2:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=1:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=2:394426c56d1a028ba8fdd5469b163e04011def47.\n",
+            "Using template $paramod$1d1e68f77481583066c6d429218f48ea9d5739b3\\_90_alu for cells of type $alu.\n",
+            "Using extmapper simplemap for cells of type $xor.\n",
+            "Using extmapper simplemap for cells of type $and.\n",
+            "Using template $paramod\\_90_lcu\\WIDTH=32'00000000000000000000000000000010 for cells of type $lcu.\n",
+            "Using extmapper simplemap for cells of type $pos.\n",
+            "Using extmapper simplemap for cells of type $mux.\n",
+            "Using extmapper simplemap for cells of type $not.\n",
+            "Using extmapper simplemap for cells of type $or.\n",
+            "No more expansions possible.\n",
+            "\n",
+            "7. Executing OPT pass (performing simple optimizations).\n",
+            "\n",
+            "7.1. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module adder.\n",
+            "\n",
+            "7.2. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\adder'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n",
+            "Running muxtree optimizer on module \\adder..\n",
+            "  Creating internal representation of mux trees.\n",
+            "  No muxes found in this module.\n",
+            "Removed 0 multiplexer ports.\n",
+            "\n",
+            "7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n",
+            "  Optimizing cells in module \\adder.\n",
+            "Performed a total of 0 changes.\n",
+            "\n",
+            "7.5. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\adder'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "7.6. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "7.7. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\adder..\n",
+            "Removed 1 unused cells and 32 unused wires.\n",
+            "\n",
+            "7.8. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module adder.\n",
+            "\n",
+            "7.9. Rerunning OPT passes. (Maybe there is more to do..)\n",
+            "\n",
+            "7.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n",
+            "Running muxtree optimizer on module \\adder..\n",
+            "  Creating internal representation of mux trees.\n",
+            "  No muxes found in this module.\n",
+            "Removed 0 multiplexer ports.\n",
+            "\n",
+            "7.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n",
+            "  Optimizing cells in module \\adder.\n",
+            "Performed a total of 0 changes.\n",
+            "\n",
+            "7.12. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\adder'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "7.13. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "7.14. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\adder..\n",
+            "\n",
+            "7.15. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module adder.\n",
+            "\n",
+            "7.16. Finished OPT passes. (There is nothing left to do.)\n",
+            "\n",
+            "yosys> \n",
+            "yosys> \n",
+            "8. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\adder..\n",
+            "\n",
+            "yosys> \n",
+            "9. Generating Graphviz representation of design.\n",
+            "Writing dot description to `synth_gate.dot'.\n",
+            "Dumping module adder to page 1.\n",
+            "\n",
+            "yosys> \n",
+            "10. Printing statistics.\n",
+            "\n",
+            "=== adder ===\n",
+            "\n",
+            "   Number of wires:                  3\n",
+            "   Number of wire bits:              4\n",
+            "   Number of public wires:           3\n",
+            "   Number of public wire bits:       4\n",
+            "   Number of memories:               0\n",
+            "   Number of memory bits:            0\n",
+            "   Number of processes:              0\n",
+            "   Number of cells:                  2\n",
+            "     $_AND_                          1\n",
+            "     $_XOR_                          1\n",
+            "\n",
+            "\n",
+            "yosys> exit\n"
+          ]
+        }
+      ]
+    },
+    {
+      "cell_type": "code",
+      "metadata": {
+        "colab": {
+          "base_uri": "https://localhost:8080/",
+          "height": 212
+        },
+        "id": "O0OKruObup5W",
+        "outputId": "a4360ece-89f5-4e7a-9d44-552ad7b4439c"
+      },
+      "source": [
+        "import graphviz\n",
+        "graphviz.Source.from_file('synth_gate.dot')"
+      ],
+      "execution_count": 10,
+      "outputs": [
+        {
+          "output_type": "execute_result",
+          "data": {
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+            "text/plain": [
+              "<graphviz.sources.Source at 0x7ee015f09040>"
+            ]
+          },
+          "metadata": {},
+          "execution_count": 10
+        }
+      ]
+    },
+    {
+      "cell_type": "markdown",
+      "metadata": {
+        "id": "JbSxNNLGzIKz"
+      },
+      "source": [
+        "### Synth FPGA\n",
+        "\n",
+        "Synthesize FPGA netlist: map to `IC40` `LUT` gates using a builtin synthesis script."
+      ]
+    },
+    {
+      "cell_type": "code",
+      "metadata": {
+        "id": "WO4xtQYmzIK-",
+        "colab": {
+          "base_uri": "https://localhost:8080/"
+        },
+        "outputId": "99a79d29-758c-4639-a1ee-3318ee596d50"
+      },
+      "source": [
+        "%%script miniconda-synth/bin/yosys -Q -T\n",
+        "\n",
+        "read -sv adder.v\n",
+        "hierarchy -top adder\n",
+        "\n",
+        "synth_ice40\n",
+        "\n",
+        "opt_clean\n",
+        "show -format dot -prefix synth_ice40"
+      ],
+      "execution_count": 11,
+      "outputs": [
+        {
+          "output_type": "stream",
+          "name": "stdout",
+          "text": [
+            "\n",
+            "yosys> \n",
+            "yosys> \n",
+            "\n",
+            "1. Executing Verilog-2005 frontend: adder.v\n",
+            "Parsing SystemVerilog input from `adder.v' to AST representation.\n",
+            "Storing AST representation for module `$abstract\\adder'.\n",
+            "Successfully finished Verilog frontend.\n",
+            "\n",
+            "yosys> \n",
+            "2. Executing HIERARCHY pass (managing design hierarchy).\n",
+            "\n",
+            "3. Executing AST frontend in derive mode using pre-parsed AST for module `\\adder'.\n",
+            "Generating RTLIL representation for module `\\adder'.\n",
+            "\n",
+            "3.1. Analyzing design hierarchy..\n",
+            "Top module:  \\adder\n",
+            "\n",
+            "3.2. Analyzing design hierarchy..\n",
+            "Top module:  \\adder\n",
+            "Removing unused module `$abstract\\adder'.\n",
+            "Removed 1 unused modules.\n",
+            "\n",
+            "yosys> \n",
+            "yosys> \n",
+            "4. Executing SYNTH_ICE40 pass.\n",
+            "\n",
+            "4.1. Executing Verilog-2005 frontend: /content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v\n",
+            "Parsing Verilog input from `/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v' to AST representation.\n",
+            "Generating RTLIL representation for module `\\SB_IO'.\n",
+            "Generating RTLIL representation for module `\\SB_GB_IO'.\n",
+            "Generating RTLIL representation for module `\\SB_GB'.\n",
+            "Generating RTLIL representation for module `\\SB_LUT4'.\n",
+            "Generating RTLIL representation for module `\\SB_CARRY'.\n",
+            "Generating RTLIL representation for module `\\SB_DFF'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFE'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFSR'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFR'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFSS'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFS'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFESR'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFER'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFESS'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFES'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFN'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFNE'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFNSR'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFNR'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFNSS'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFNS'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFNESR'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFNER'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFNESS'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFNES'.\n",
+            "Generating RTLIL representation for module `\\SB_RAM40_4K'.\n",
+            "Generating RTLIL representation for module `\\SB_RAM40_4KNR'.\n",
+            "Generating RTLIL representation for module `\\SB_RAM40_4KNW'.\n",
+            "Generating RTLIL representation for module `\\SB_RAM40_4KNRNW'.\n",
+            "Generating RTLIL representation for module `\\ICESTORM_LC'.\n",
+            "Generating RTLIL representation for module `\\SB_PLL40_CORE'.\n",
+            "Generating RTLIL representation for module `\\SB_PLL40_PAD'.\n",
+            "Generating RTLIL representation for module `\\SB_PLL40_2_PAD'.\n",
+            "Generating RTLIL representation for module `\\SB_PLL40_2F_CORE'.\n",
+            "Generating RTLIL representation for module `\\SB_PLL40_2F_PAD'.\n",
+            "Generating RTLIL representation for module `\\SB_WARMBOOT'.\n",
+            "Generating RTLIL representation for module `\\SB_SPRAM256KA'.\n",
+            "Generating RTLIL representation for module `\\SB_HFOSC'.\n",
+            "Generating RTLIL representation for module `\\SB_LFOSC'.\n",
+            "Generating RTLIL representation for module `\\SB_RGBA_DRV'.\n",
+            "Generating RTLIL representation for module `\\SB_LED_DRV_CUR'.\n",
+            "Generating RTLIL representation for module `\\SB_RGB_DRV'.\n",
+            "Generating RTLIL representation for module `\\SB_I2C'.\n",
+            "Generating RTLIL representation for module `\\SB_SPI'.\n",
+            "Generating RTLIL representation for module `\\SB_LEDDA_IP'.\n",
+            "Generating RTLIL representation for module `\\SB_FILTER_50NS'.\n",
+            "Generating RTLIL representation for module `\\SB_IO_I3C'.\n",
+            "Generating RTLIL representation for module `\\SB_IO_OD'.\n",
+            "Generating RTLIL representation for module `\\SB_MAC16'.\n",
+            "Generating RTLIL representation for module `\\ICESTORM_RAM'.\n",
+            "Successfully finished Verilog frontend.\n",
+            "\n",
+            "4.2. Executing HIERARCHY pass (managing design hierarchy).\n",
+            "\n",
+            "4.2.1. Analyzing design hierarchy..\n",
+            "Top module:  \\adder\n",
+            "\n",
+            "4.2.2. Analyzing design hierarchy..\n",
+            "Top module:  \\adder\n",
+            "Removed 0 unused modules.\n",
+            "\n",
+            "4.3. Executing PROC pass (convert processes to netlists).\n",
+            "\n",
+            "4.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).\n",
+            "Cleaned up 0 empty switches.\n",
+            "\n",
+            "4.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:1386$242 in module SB_DFFNES.\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:1328$235 in module SB_DFFNESS.\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:1251$231 in module SB_DFFNER.\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:1193$224 in module SB_DFFNESR.\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:1122$221 in module SB_DFFNS.\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:1072$218 in module SB_DFFNSS.\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:1001$215 in module SB_DFFNR.\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:951$212 in module SB_DFFNSR.\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:789$204 in module SB_DFFES.\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:731$197 in module SB_DFFESS.\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:654$193 in module SB_DFFER.\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:596$186 in module SB_DFFESR.\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:525$183 in module SB_DFFS.\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:475$180 in module SB_DFFSS.\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:404$177 in module SB_DFFR.\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:354$174 in module SB_DFFSR.\n",
+            "Removed a total of 0 dead cases.\n",
+            "\n",
+            "4.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).\n",
+            "Removed 8 redundant assignments.\n",
+            "Promoted 22 assignments to connections.\n",
+            "\n",
+            "4.3.4. Executing PROC_INIT pass (extract init attributes).\n",
+            "Found init rule in `\\SB_DFFNES.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$245'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFNESS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$241'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFNER.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$234'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFNESR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$230'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFNS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$223'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFNSS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$220'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFNR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$217'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFNSR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$214'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFNE.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$211'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFN.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$209'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFES.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$207'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFESS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$203'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFER.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$196'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFESR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$192'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$185'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFSS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$182'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$179'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFSR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$176'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFE.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$173'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFF.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$171'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "\n",
+            "4.3.5. Executing PROC_ARST pass (detect async resets in processes).\n",
+            "Found async reset \\S in `\\SB_DFFNES.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:1386$242'.\n",
+            "Found async reset \\R in `\\SB_DFFNER.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:1251$231'.\n",
+            "Found async reset \\S in `\\SB_DFFNS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:1122$221'.\n",
+            "Found async reset \\R in `\\SB_DFFNR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:1001$215'.\n",
+            "Found async reset \\S in `\\SB_DFFES.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:789$204'.\n",
+            "Found async reset \\R in `\\SB_DFFER.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:654$193'.\n",
+            "Found async reset \\S in `\\SB_DFFS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:525$183'.\n",
+            "Found async reset \\R in `\\SB_DFFR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:404$177'.\n",
+            "\n",
+            "4.3.6. Executing PROC_MUX pass (convert decision trees to multiplexers).\n",
+            "Creating decoders for process `\\SB_DFFNES.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$245'.\n",
+            "Creating decoders for process `\\SB_DFFNES.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:1386$242'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFNESS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$241'.\n",
+            "Creating decoders for process `\\SB_DFFNESS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:1328$235'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFNER.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$234'.\n",
+            "Creating decoders for process `\\SB_DFFNER.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:1251$231'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFNESR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$230'.\n",
+            "Creating decoders for process `\\SB_DFFNESR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:1193$224'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFNS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$223'.\n",
+            "Creating decoders for process `\\SB_DFFNS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:1122$221'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFNSS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$220'.\n",
+            "Creating decoders for process `\\SB_DFFNSS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:1072$218'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFNR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$217'.\n",
+            "Creating decoders for process `\\SB_DFFNR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:1001$215'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFNSR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$214'.\n",
+            "Creating decoders for process `\\SB_DFFNSR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:951$212'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFNE.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$211'.\n",
+            "Creating decoders for process `\\SB_DFFNE.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:906$210'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFN.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$209'.\n",
+            "Creating decoders for process `\\SB_DFFN.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:868$208'.\n",
+            "Creating decoders for process `\\SB_DFFES.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$207'.\n",
+            "Creating decoders for process `\\SB_DFFES.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:789$204'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFESS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$203'.\n",
+            "Creating decoders for process `\\SB_DFFESS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:731$197'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFER.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$196'.\n",
+            "Creating decoders for process `\\SB_DFFER.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:654$193'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFESR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$192'.\n",
+            "Creating decoders for process `\\SB_DFFESR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:596$186'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$185'.\n",
+            "Creating decoders for process `\\SB_DFFS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:525$183'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFSS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$182'.\n",
+            "Creating decoders for process `\\SB_DFFSS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:475$180'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$179'.\n",
+            "Creating decoders for process `\\SB_DFFR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:404$177'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFSR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$176'.\n",
+            "Creating decoders for process `\\SB_DFFSR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:354$174'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFE.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$173'.\n",
+            "Creating decoders for process `\\SB_DFFE.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:309$172'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFF.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$171'.\n",
+            "Creating decoders for process `\\SB_DFF.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:271$170'.\n",
+            "\n",
+            "4.3.7. Executing PROC_DLATCH pass (convert process syncs to latches).\n",
+            "\n",
+            "4.3.8. Executing PROC_DFF pass (convert process syncs to FFs).\n",
+            "Creating register for signal `\\SB_DFFNES.\\Q' using process `\\SB_DFFNES.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:1386$242'.\n",
+            "  created $adff cell `$procdff$426' with negative edge clock and positive level reset.\n",
+            "Creating register for signal `\\SB_DFFNESS.\\Q' using process `\\SB_DFFNESS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:1328$235'.\n",
+            "  created $dff cell `$procdff$427' with negative edge clock.\n",
+            "Creating register for signal `\\SB_DFFNER.\\Q' using process `\\SB_DFFNER.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:1251$231'.\n",
+            "  created $adff cell `$procdff$428' with negative edge clock and positive level reset.\n",
+            "Creating register for signal `\\SB_DFFNESR.\\Q' using process `\\SB_DFFNESR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:1193$224'.\n",
+            "  created $dff cell `$procdff$429' with negative edge clock.\n",
+            "Creating register for signal `\\SB_DFFNS.\\Q' using process `\\SB_DFFNS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:1122$221'.\n",
+            "  created $adff cell `$procdff$430' with negative edge clock and positive level reset.\n",
+            "Creating register for signal `\\SB_DFFNSS.\\Q' using process `\\SB_DFFNSS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:1072$218'.\n",
+            "  created $dff cell `$procdff$431' with negative edge clock.\n",
+            "Creating register for signal `\\SB_DFFNR.\\Q' using process `\\SB_DFFNR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:1001$215'.\n",
+            "  created $adff cell `$procdff$432' with negative edge clock and positive level reset.\n",
+            "Creating register for signal `\\SB_DFFNSR.\\Q' using process `\\SB_DFFNSR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:951$212'.\n",
+            "  created $dff cell `$procdff$433' with negative edge clock.\n",
+            "Creating register for signal `\\SB_DFFNE.\\Q' using process `\\SB_DFFNE.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:906$210'.\n",
+            "  created $dff cell `$procdff$434' with negative edge clock.\n",
+            "Creating register for signal `\\SB_DFFN.\\Q' using process `\\SB_DFFN.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:868$208'.\n",
+            "  created $dff cell `$procdff$435' with negative edge clock.\n",
+            "Creating register for signal `\\SB_DFFES.\\Q' using process `\\SB_DFFES.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:789$204'.\n",
+            "  created $adff cell `$procdff$436' with positive edge clock and positive level reset.\n",
+            "Creating register for signal `\\SB_DFFESS.\\Q' using process `\\SB_DFFESS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:731$197'.\n",
+            "  created $dff cell `$procdff$437' with positive edge clock.\n",
+            "Creating register for signal `\\SB_DFFER.\\Q' using process `\\SB_DFFER.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:654$193'.\n",
+            "  created $adff cell `$procdff$438' with positive edge clock and positive level reset.\n",
+            "Creating register for signal `\\SB_DFFESR.\\Q' using process `\\SB_DFFESR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:596$186'.\n",
+            "  created $dff cell `$procdff$439' with positive edge clock.\n",
+            "Creating register for signal `\\SB_DFFS.\\Q' using process `\\SB_DFFS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:525$183'.\n",
+            "  created $adff cell `$procdff$440' with positive edge clock and positive level reset.\n",
+            "Creating register for signal `\\SB_DFFSS.\\Q' using process `\\SB_DFFSS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:475$180'.\n",
+            "  created $dff cell `$procdff$441' with positive edge clock.\n",
+            "Creating register for signal `\\SB_DFFR.\\Q' using process `\\SB_DFFR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:404$177'.\n",
+            "  created $adff cell `$procdff$442' with positive edge clock and positive level reset.\n",
+            "Creating register for signal `\\SB_DFFSR.\\Q' using process `\\SB_DFFSR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:354$174'.\n",
+            "  created $dff cell `$procdff$443' with positive edge clock.\n",
+            "Creating register for signal `\\SB_DFFE.\\Q' using process `\\SB_DFFE.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:309$172'.\n",
+            "  created $dff cell `$procdff$444' with positive edge clock.\n",
+            "Creating register for signal `\\SB_DFF.\\Q' using process `\\SB_DFF.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:271$170'.\n",
+            "  created $dff cell `$procdff$445' with positive edge clock.\n",
+            "\n",
+            "4.3.9. Executing PROC_MEMWR pass (convert process memory writes to cells).\n",
+            "\n",
+            "4.3.10. Executing PROC_CLEAN pass (remove empty switches from decision trees).\n",
+            "Removing empty process `SB_DFFNES.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$245'.\n",
+            "Found and cleaned up 1 empty switch in `\\SB_DFFNES.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:1386$242'.\n",
+            "Removing empty process `SB_DFFNES.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:1386$242'.\n",
+            "Removing empty process `SB_DFFNESS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$241'.\n",
+            "Found and cleaned up 2 empty switches in `\\SB_DFFNESS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:1328$235'.\n",
+            "Removing empty process `SB_DFFNESS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:1328$235'.\n",
+            "Removing empty process `SB_DFFNER.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$234'.\n",
+            "Found and cleaned up 1 empty switch in `\\SB_DFFNER.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:1251$231'.\n",
+            "Removing empty process `SB_DFFNER.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:1251$231'.\n",
+            "Removing empty process `SB_DFFNESR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$230'.\n",
+            "Found and cleaned up 2 empty switches in `\\SB_DFFNESR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:1193$224'.\n",
+            "Removing empty process `SB_DFFNESR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:1193$224'.\n",
+            "Removing empty process `SB_DFFNS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$223'.\n",
+            "Removing empty process `SB_DFFNS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:1122$221'.\n",
+            "Removing empty process `SB_DFFNSS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$220'.\n",
+            "Found and cleaned up 1 empty switch in `\\SB_DFFNSS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:1072$218'.\n",
+            "Removing empty process `SB_DFFNSS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:1072$218'.\n",
+            "Removing empty process `SB_DFFNR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$217'.\n",
+            "Removing empty process `SB_DFFNR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:1001$215'.\n",
+            "Removing empty process `SB_DFFNSR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$214'.\n",
+            "Found and cleaned up 1 empty switch in `\\SB_DFFNSR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:951$212'.\n",
+            "Removing empty process `SB_DFFNSR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:951$212'.\n",
+            "Removing empty process `SB_DFFNE.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$211'.\n",
+            "Found and cleaned up 1 empty switch in `\\SB_DFFNE.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:906$210'.\n",
+            "Removing empty process `SB_DFFNE.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:906$210'.\n",
+            "Removing empty process `SB_DFFN.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$209'.\n",
+            "Removing empty process `SB_DFFN.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:868$208'.\n",
+            "Removing empty process `SB_DFFES.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$207'.\n",
+            "Found and cleaned up 1 empty switch in `\\SB_DFFES.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:789$204'.\n",
+            "Removing empty process `SB_DFFES.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:789$204'.\n",
+            "Removing empty process `SB_DFFESS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$203'.\n",
+            "Found and cleaned up 2 empty switches in `\\SB_DFFESS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:731$197'.\n",
+            "Removing empty process `SB_DFFESS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:731$197'.\n",
+            "Removing empty process `SB_DFFER.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$196'.\n",
+            "Found and cleaned up 1 empty switch in `\\SB_DFFER.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:654$193'.\n",
+            "Removing empty process `SB_DFFER.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:654$193'.\n",
+            "Removing empty process `SB_DFFESR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$192'.\n",
+            "Found and cleaned up 2 empty switches in `\\SB_DFFESR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:596$186'.\n",
+            "Removing empty process `SB_DFFESR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:596$186'.\n",
+            "Removing empty process `SB_DFFS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$185'.\n",
+            "Removing empty process `SB_DFFS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:525$183'.\n",
+            "Removing empty process `SB_DFFSS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$182'.\n",
+            "Found and cleaned up 1 empty switch in `\\SB_DFFSS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:475$180'.\n",
+            "Removing empty process `SB_DFFSS.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:475$180'.\n",
+            "Removing empty process `SB_DFFR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$179'.\n",
+            "Removing empty process `SB_DFFR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:404$177'.\n",
+            "Removing empty process `SB_DFFSR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$176'.\n",
+            "Found and cleaned up 1 empty switch in `\\SB_DFFSR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:354$174'.\n",
+            "Removing empty process `SB_DFFSR.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:354$174'.\n",
+            "Removing empty process `SB_DFFE.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$173'.\n",
+            "Found and cleaned up 1 empty switch in `\\SB_DFFE.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:309$172'.\n",
+            "Removing empty process `SB_DFFE.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:309$172'.\n",
+            "Removing empty process `SB_DFF.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:0$171'.\n",
+            "Removing empty process `SB_DFF.$proc$/content/miniconda-synth/bin/../share/yosys/ice40/cells_sim.v:271$170'.\n",
+            "Cleaned up 18 empty switches.\n",
+            "\n",
+            "4.3.11. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module adder.\n",
+            "\n",
+            "4.4. Executing FLATTEN pass (flatten design).\n",
+            "\n",
+            "4.5. Executing TRIBUF pass.\n",
+            "\n",
+            "4.6. Executing DEMINOUT pass (demote inout ports to input or output).\n",
+            "\n",
+            "4.7. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module adder.\n",
+            "\n",
+            "4.8. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\adder..\n",
+            "Removed 0 unused cells and 1 unused wires.\n",
+            "\n",
+            "4.9. Executing CHECK pass (checking for obvious problems).\n",
+            "Checking module adder...\n",
+            "Found and reported 0 problems.\n",
+            "\n",
+            "4.10. Executing OPT pass (performing simple optimizations).\n",
+            "\n",
+            "4.10.1. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module adder.\n",
+            "\n",
+            "4.10.2. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\adder'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "4.10.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n",
+            "Running muxtree optimizer on module \\adder..\n",
+            "  Creating internal representation of mux trees.\n",
+            "  No muxes found in this module.\n",
+            "Removed 0 multiplexer ports.\n",
+            "\n",
+            "4.10.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n",
+            "  Optimizing cells in module \\adder.\n",
+            "Performed a total of 0 changes.\n",
+            "\n",
+            "4.10.5. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\adder'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "4.10.6. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "4.10.7. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\adder..\n",
+            "\n",
+            "4.10.8. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module adder.\n",
+            "\n",
+            "4.10.9. Finished OPT passes. (There is nothing left to do.)\n",
+            "\n",
+            "4.11. Executing FSM pass (extract and optimize FSM).\n",
+            "\n",
+            "4.11.1. Executing FSM_DETECT pass (finding FSMs in design).\n",
+            "\n",
+            "4.11.2. Executing FSM_EXTRACT pass (extracting FSM from design).\n",
+            "\n",
+            "4.11.3. Executing FSM_OPT pass (simple optimizations of FSMs).\n",
+            "\n",
+            "4.11.4. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\adder..\n",
+            "\n",
+            "4.11.5. Executing FSM_OPT pass (simple optimizations of FSMs).\n",
+            "\n",
+            "4.11.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).\n",
+            "\n",
+            "4.11.7. Executing FSM_INFO pass (dumping all available information on FSM cells).\n",
+            "\n",
+            "4.11.8. Executing FSM_MAP pass (mapping FSMs to basic logic).\n",
+            "\n",
+            "4.12. Executing OPT pass (performing simple optimizations).\n",
+            "\n",
+            "4.12.1. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module adder.\n",
+            "\n",
+            "4.12.2. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\adder'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "4.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n",
+            "Running muxtree optimizer on module \\adder..\n",
+            "  Creating internal representation of mux trees.\n",
+            "  No muxes found in this module.\n",
+            "Removed 0 multiplexer ports.\n",
+            "\n",
+            "4.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n",
+            "  Optimizing cells in module \\adder.\n",
+            "Performed a total of 0 changes.\n",
+            "\n",
+            "4.12.5. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\adder'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "4.12.6. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "4.12.7. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\adder..\n",
+            "\n",
+            "4.12.8. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module adder.\n",
+            "\n",
+            "4.12.9. Finished OPT passes. (There is nothing left to do.)\n",
+            "\n",
+            "4.13. Executing WREDUCE pass (reducing word size of cells).\n",
+            "\n",
+            "4.14. Executing PEEPOPT pass (run peephole optimizers).\n",
+            "\n",
+            "4.15. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\adder..\n",
+            "\n",
+            "4.16. Executing SHARE pass (SAT-based resource sharing).\n",
+            "\n",
+            "4.17. Executing TECHMAP pass (map to technology primitives).\n",
+            "\n",
+            "4.17.1. Executing Verilog-2005 frontend: /content/miniconda-synth/bin/../share/yosys/cmp2lut.v\n",
+            "Parsing Verilog input from `/content/miniconda-synth/bin/../share/yosys/cmp2lut.v' to AST representation.\n",
+            "Generating RTLIL representation for module `\\_90_lut_cmp_'.\n",
+            "Successfully finished Verilog frontend.\n",
+            "\n",
+            "4.17.2. Continuing TECHMAP pass.\n",
+            "No more expansions possible.\n",
+            "\n",
+            "4.18. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module adder.\n",
+            "\n",
+            "4.19. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\adder..\n",
+            "\n",
+            "4.20. Executing ALUMACC pass (create $alu and $macc cells).\n",
+            "Extracting $alu and $macc cells in module adder:\n",
+            "  creating $macc model for $add$adder.v:7$1 ($add).\n",
+            "  creating $alu model for $macc $add$adder.v:7$1.\n",
+            "  creating $alu cell for $add$adder.v:7$1: $auto$alumacc.cc:485:replace_alu$447\n",
+            "  created 1 $alu and 0 $macc cells.\n",
+            "\n",
+            "4.21. Executing OPT pass (performing simple optimizations).\n",
+            "\n",
+            "4.21.1. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module adder.\n",
+            "\n",
+            "4.21.2. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\adder'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "4.21.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n",
+            "Running muxtree optimizer on module \\adder..\n",
+            "  Creating internal representation of mux trees.\n",
+            "  No muxes found in this module.\n",
+            "Removed 0 multiplexer ports.\n",
+            "\n",
+            "4.21.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n",
+            "  Optimizing cells in module \\adder.\n",
+            "Performed a total of 0 changes.\n",
+            "\n",
+            "4.21.5. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\adder'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "4.21.6. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "4.21.7. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\adder..\n",
+            "\n",
+            "4.21.8. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module adder.\n",
+            "\n",
+            "4.21.9. Finished OPT passes. (There is nothing left to do.)\n",
+            "\n",
+            "4.22. Executing MEMORY pass.\n",
+            "\n",
+            "4.22.1. Executing OPT_MEM pass (optimize memories).\n",
+            "Performed a total of 0 transformations.\n",
+            "\n",
+            "4.22.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).\n",
+            "Performed a total of 0 transformations.\n",
+            "\n",
+            "4.22.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).\n",
+            "\n",
+            "4.22.4. Executing MEMORY_DFF pass (merging $dff cells to $memrd).\n",
+            "\n",
+            "4.22.5. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\adder..\n",
+            "\n",
+            "4.22.6. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).\n",
+            "\n",
+            "4.22.7. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).\n",
+            "Performed a total of 0 transformations.\n",
+            "\n",
+            "4.22.8. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\adder..\n",
+            "\n",
+            "4.22.9. Executing MEMORY_COLLECT pass (generating $mem cells).\n",
+            "\n",
+            "4.23. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\adder..\n",
+            "\n",
+            "4.24. Executing MEMORY_BRAM pass (mapping $mem cells to block memories).\n",
+            "\n",
+            "4.25. Executing TECHMAP pass (map to technology primitives).\n",
+            "\n",
+            "4.25.1. Executing Verilog-2005 frontend: /content/miniconda-synth/bin/../share/yosys/ice40/brams_map.v\n",
+            "Parsing Verilog input from `/content/miniconda-synth/bin/../share/yosys/ice40/brams_map.v' to AST representation.\n",
+            "Generating RTLIL representation for module `\\$__ICE40_RAM4K'.\n",
+            "Generating RTLIL representation for module `\\$__ICE40_RAM4K_M0'.\n",
+            "Generating RTLIL representation for module `\\$__ICE40_RAM4K_M123'.\n",
+            "Successfully finished Verilog frontend.\n",
+            "\n",
+            "4.25.2. Continuing TECHMAP pass.\n",
+            "No more expansions possible.\n",
+            "\n",
+            "4.26. Executing ICE40_BRAMINIT pass.\n",
+            "\n",
+            "4.27. Executing OPT pass (performing simple optimizations).\n",
+            "\n",
+            "4.27.1. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module adder.\n",
+            "\n",
+            "4.27.2. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\adder'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "4.27.3. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "4.27.4. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\adder..\n",
+            "\n",
+            "4.27.5. Finished fast OPT passes.\n",
+            "\n",
+            "4.28. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).\n",
+            "\n",
+            "4.29. Executing OPT pass (performing simple optimizations).\n",
+            "\n",
+            "4.29.1. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module adder.\n",
+            "\n",
+            "4.29.2. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\adder'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "4.29.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n",
+            "Running muxtree optimizer on module \\adder..\n",
+            "  Creating internal representation of mux trees.\n",
+            "  No muxes found in this module.\n",
+            "Removed 0 multiplexer ports.\n",
+            "\n",
+            "4.29.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n",
+            "  Optimizing cells in module \\adder.\n",
+            "Performed a total of 0 changes.\n",
+            "\n",
+            "4.29.5. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\adder'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "4.29.6. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "4.29.7. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\adder..\n",
+            "\n",
+            "4.29.8. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module adder.\n",
+            "\n",
+            "4.29.9. Finished OPT passes. (There is nothing left to do.)\n",
+            "\n",
+            "4.30. Executing ICE40_WRAPCARRY pass (wrap carries).\n",
+            "\n",
+            "4.31. Executing TECHMAP pass (map to technology primitives).\n",
+            "\n",
+            "4.31.1. Executing Verilog-2005 frontend: /content/miniconda-synth/bin/../share/yosys/techmap.v\n",
+            "Parsing Verilog input from `/content/miniconda-synth/bin/../share/yosys/techmap.v' to AST representation.\n",
+            "Generating RTLIL representation for module `\\_90_simplemap_bool_ops'.\n",
+            "Generating RTLIL representation for module `\\_90_simplemap_reduce_ops'.\n",
+            "Generating RTLIL representation for module `\\_90_simplemap_logic_ops'.\n",
+            "Generating RTLIL representation for module `\\_90_simplemap_compare_ops'.\n",
+            "Generating RTLIL representation for module `\\_90_simplemap_various'.\n",
+            "Generating RTLIL representation for module `\\_90_simplemap_registers'.\n",
+            "Generating RTLIL representation for module `\\_90_shift_ops_shr_shl_sshl_sshr'.\n",
+            "Generating RTLIL representation for module `\\_90_shift_shiftx'.\n",
+            "Generating RTLIL representation for module `\\_90_fa'.\n",
+            "Generating RTLIL representation for module `\\_90_lcu'.\n",
+            "Generating RTLIL representation for module `\\_90_alu'.\n",
+            "Generating RTLIL representation for module `\\_90_macc'.\n",
+            "Generating RTLIL representation for module `\\_90_alumacc'.\n",
+            "Generating RTLIL representation for module `\\$__div_mod_u'.\n",
+            "Generating RTLIL representation for module `\\$__div_mod_trunc'.\n",
+            "Generating RTLIL representation for module `\\_90_div'.\n",
+            "Generating RTLIL representation for module `\\_90_mod'.\n",
+            "Generating RTLIL representation for module `\\$__div_mod_floor'.\n",
+            "Generating RTLIL representation for module `\\_90_divfloor'.\n",
+            "Generating RTLIL representation for module `\\_90_modfloor'.\n",
+            "Generating RTLIL representation for module `\\_90_pow'.\n",
+            "Generating RTLIL representation for module `\\_90_pmux'.\n",
+            "Generating RTLIL representation for module `\\_90_demux'.\n",
+            "Generating RTLIL representation for module `\\_90_lut'.\n",
+            "Successfully finished Verilog frontend.\n",
+            "\n",
+            "4.31.2. Executing Verilog-2005 frontend: /content/miniconda-synth/bin/../share/yosys/ice40/arith_map.v\n",
+            "Parsing Verilog input from `/content/miniconda-synth/bin/../share/yosys/ice40/arith_map.v' to AST representation.\n",
+            "Generating RTLIL representation for module `\\_80_ice40_alu'.\n",
+            "Successfully finished Verilog frontend.\n",
+            "\n",
+            "4.31.3. Continuing TECHMAP pass.\n",
+            "Using template $paramod$1d1e68f77481583066c6d429218f48ea9d5739b3\\_90_alu for cells of type $alu.\n",
+            "Using extmapper simplemap for cells of type $xor.\n",
+            "Using extmapper simplemap for cells of type $and.\n",
+            "Using template $paramod\\_90_lcu\\WIDTH=32'00000000000000000000000000000010 for cells of type $lcu.\n",
+            "Using extmapper simplemap for cells of type $pos.\n",
+            "Using extmapper simplemap for cells of type $mux.\n",
+            "Using extmapper simplemap for cells of type $not.\n",
+            "Using extmapper simplemap for cells of type $or.\n",
+            "No more expansions possible.\n",
+            "\n",
+            "4.32. Executing OPT pass (performing simple optimizations).\n",
+            "\n",
+            "4.32.1. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module adder.\n",
+            "\n",
+            "4.32.2. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\adder'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "4.32.3. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "4.32.4. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\adder..\n",
+            "Removed 1 unused cells and 29 unused wires.\n",
+            "\n",
+            "4.32.5. Finished fast OPT passes.\n",
+            "\n",
+            "4.33. Executing ICE40_OPT pass (performing simple optimizations).\n",
+            "\n",
+            "4.33.1. Running ICE40 specific optimizations.\n",
+            "\n",
+            "4.33.2. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module adder.\n",
+            "\n",
+            "4.33.3. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\adder'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "4.33.4. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "4.33.5. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\adder..\n",
+            "\n",
+            "4.33.6. Finished OPT passes. (There is nothing left to do.)\n",
+            "\n",
+            "4.34. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).\n",
+            "\n",
+            "4.35. Executing TECHMAP pass (map to technology primitives).\n",
+            "\n",
+            "4.35.1. Executing Verilog-2005 frontend: /content/miniconda-synth/bin/../share/yosys/ice40/ff_map.v\n",
+            "Parsing Verilog input from `/content/miniconda-synth/bin/../share/yosys/ice40/ff_map.v' to AST representation.\n",
+            "Generating RTLIL representation for module `\\$_DFF_N_'.\n",
+            "Generating RTLIL representation for module `\\$_DFF_P_'.\n",
+            "Generating RTLIL representation for module `\\$_DFFE_NP_'.\n",
+            "Generating RTLIL representation for module `\\$_DFFE_PP_'.\n",
+            "Generating RTLIL representation for module `\\$_DFF_NP0_'.\n",
+            "Generating RTLIL representation for module `\\$_DFF_NP1_'.\n",
+            "Generating RTLIL representation for module `\\$_DFF_PP0_'.\n",
+            "Generating RTLIL representation for module `\\$_DFF_PP1_'.\n",
+            "Generating RTLIL representation for module `\\$_DFFE_NP0P_'.\n",
+            "Generating RTLIL representation for module `\\$_DFFE_NP1P_'.\n",
+            "Generating RTLIL representation for module `\\$_DFFE_PP0P_'.\n",
+            "Generating RTLIL representation for module `\\$_DFFE_PP1P_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFF_NP0_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFF_NP1_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFF_PP0_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFF_PP1_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFFCE_NP0P_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFFCE_NP1P_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFFCE_PP0P_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFFCE_PP1P_'.\n",
+            "Successfully finished Verilog frontend.\n",
+            "\n",
+            "4.35.2. Continuing TECHMAP pass.\n",
+            "No more expansions possible.\n",
+            "\n",
+            "4.36. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module adder.\n",
+            "\n",
+            "4.37. Executing SIMPLEMAP pass (map simple cells to gate primitives).\n",
+            "\n",
+            "4.38. Executing ICE40_OPT pass (performing simple optimizations).\n",
+            "\n",
+            "4.38.1. Running ICE40 specific optimizations.\n",
+            "\n",
+            "4.38.2. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module adder.\n",
+            "\n",
+            "4.38.3. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\adder'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "4.38.4. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "4.38.5. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\adder..\n",
+            "\n",
+            "4.38.6. Finished OPT passes. (There is nothing left to do.)\n",
+            "\n",
+            "4.39. Executing TECHMAP pass (map to technology primitives).\n",
+            "\n",
+            "4.39.1. Executing Verilog-2005 frontend: /content/miniconda-synth/bin/../share/yosys/ice40/latches_map.v\n",
+            "Parsing Verilog input from `/content/miniconda-synth/bin/../share/yosys/ice40/latches_map.v' to AST representation.\n",
+            "Generating RTLIL representation for module `\\$_DLATCH_N_'.\n",
+            "Generating RTLIL representation for module `\\$_DLATCH_P_'.\n",
+            "Successfully finished Verilog frontend.\n",
+            "\n",
+            "4.39.2. Continuing TECHMAP pass.\n",
+            "No more expansions possible.\n",
+            "\n",
+            "4.40. Executing ABC pass (technology mapping using ABC).\n",
+            "\n",
+            "4.40.1. Extracting gate netlist of module `\\adder' to `<abc-temp-dir>/input.blif'..\n",
+            "Extracted 2 gates and 4 wires to a netlist network with 2 inputs and 2 outputs.\n",
+            "\n",
+            "4.40.1.1. Executing ABC.\n",
+            "Running ABC command: <yosys-exe-dir>/yosys-abc -s -f <abc-temp-dir>/abc.script 2>&1\n",
+            "ABC: ABC command line: \"source <abc-temp-dir>/abc.script\".\n",
+            "ABC: \n",
+            "ABC: + read_blif <abc-temp-dir>/input.blif \n",
+            "ABC: + read_lut <abc-temp-dir>/lutdefs.txt \n",
+            "ABC: + strash \n",
+            "ABC: + ifraig \n",
+            "ABC: + scorr \n",
+            "ABC: Warning: The network is combinational (run \"fraig\" or \"fraig_sweep\").\n",
+            "ABC: + dc2 \n",
+            "ABC: + dretime \n",
+            "ABC: + strash \n",
+            "ABC: + dch -f \n",
+            "ABC: + if \n",
+            "ABC: + mfs2 \n",
+            "ABC: + lutpack -S 1 \n",
+            "ABC: + dress \n",
+            "ABC: Total number of equiv classes                =       3.\n",
+            "ABC: Participating nodes from both networks       =       4.\n",
+            "ABC: Participating nodes from the first network   =       2. (  66.67 % of nodes)\n",
+            "ABC: Participating nodes from the second network  =       2. (  66.67 % of nodes)\n",
+            "ABC: Node pairs (any polarity)                    =       2. (  66.67 % of names can be moved)\n",
+            "ABC: Node pairs (same polarity)                   =       2. (  66.67 % of names can be moved)\n",
+            "ABC: Total runtime =     0.00 sec\n",
+            "ABC: + write_blif <abc-temp-dir>/output.blif \n",
+            "\n",
+            "4.40.1.2. Re-integrating ABC results.\n",
+            "ABC RESULTS:              $lut cells:        2\n",
+            "ABC RESULTS:        internal signals:        0\n",
+            "ABC RESULTS:           input signals:        2\n",
+            "ABC RESULTS:          output signals:        2\n",
+            "Removing temp directory.\n",
+            "\n",
+            "4.41. Executing ICE40_WRAPCARRY pass (wrap carries).\n",
+            "\n",
+            "4.42. Executing TECHMAP pass (map to technology primitives).\n",
+            "\n",
+            "4.42.1. Executing Verilog-2005 frontend: /content/miniconda-synth/bin/../share/yosys/ice40/ff_map.v\n",
+            "Parsing Verilog input from `/content/miniconda-synth/bin/../share/yosys/ice40/ff_map.v' to AST representation.\n",
+            "Generating RTLIL representation for module `\\$_DFF_N_'.\n",
+            "Generating RTLIL representation for module `\\$_DFF_P_'.\n",
+            "Generating RTLIL representation for module `\\$_DFFE_NP_'.\n",
+            "Generating RTLIL representation for module `\\$_DFFE_PP_'.\n",
+            "Generating RTLIL representation for module `\\$_DFF_NP0_'.\n",
+            "Generating RTLIL representation for module `\\$_DFF_NP1_'.\n",
+            "Generating RTLIL representation for module `\\$_DFF_PP0_'.\n",
+            "Generating RTLIL representation for module `\\$_DFF_PP1_'.\n",
+            "Generating RTLIL representation for module `\\$_DFFE_NP0P_'.\n",
+            "Generating RTLIL representation for module `\\$_DFFE_NP1P_'.\n",
+            "Generating RTLIL representation for module `\\$_DFFE_PP0P_'.\n",
+            "Generating RTLIL representation for module `\\$_DFFE_PP1P_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFF_NP0_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFF_NP1_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFF_PP0_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFF_PP1_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFFCE_NP0P_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFFCE_NP1P_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFFCE_PP0P_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFFCE_PP1P_'.\n",
+            "Successfully finished Verilog frontend.\n",
+            "\n",
+            "4.42.2. Continuing TECHMAP pass.\n",
+            "No more expansions possible.\n",
+            "Removed 0 unused cells and 4 unused wires.\n",
+            "\n",
+            "4.43. Executing OPT_LUT pass (optimize LUTs).\n",
+            "Discovering LUTs.\n",
+            "Number of LUTs:        2\n",
+            "  2-LUT                2\n",
+            "  with \\SB_CARRY    (#0)    0\n",
+            "  with \\SB_CARRY    (#1)    0\n",
+            "\n",
+            "Eliminating LUTs.\n",
+            "Number of LUTs:        2\n",
+            "  2-LUT                2\n",
+            "  with \\SB_CARRY    (#0)    0\n",
+            "  with \\SB_CARRY    (#1)    0\n",
+            "\n",
+            "Combining LUTs.\n",
+            "Number of LUTs:        2\n",
+            "  2-LUT                2\n",
+            "  with \\SB_CARRY    (#0)    0\n",
+            "  with \\SB_CARRY    (#1)    0\n",
+            "\n",
+            "Eliminated 0 LUTs.\n",
+            "Combined 0 LUTs.\n",
+            "\n",
+            "4.44. Executing TECHMAP pass (map to technology primitives).\n",
+            "\n",
+            "4.44.1. Executing Verilog-2005 frontend: /content/miniconda-synth/bin/../share/yosys/ice40/cells_map.v\n",
+            "Parsing Verilog input from `/content/miniconda-synth/bin/../share/yosys/ice40/cells_map.v' to AST representation.\n",
+            "Generating RTLIL representation for module `\\$lut'.\n",
+            "Successfully finished Verilog frontend.\n",
+            "\n",
+            "4.44.2. Continuing TECHMAP pass.\n",
+            "Using template $paramod\\$lut\\WIDTH=32'00000000000000000000000000000010\\LUT=4'0110 for cells of type $lut.\n",
+            "Using template $paramod\\$lut\\WIDTH=32'00000000000000000000000000000010\\LUT=4'1000 for cells of type $lut.\n",
+            "No more expansions possible.\n",
+            "Removed 0 unused cells and 4 unused wires.\n",
+            "\n",
+            "4.45. Executing AUTONAME pass.\n",
+            "Renamed 2 objects in module adder (2 iterations).\n",
+            "\n",
+            "4.46. Executing HIERARCHY pass (managing design hierarchy).\n",
+            "\n",
+            "4.46.1. Analyzing design hierarchy..\n",
+            "Top module:  \\adder\n",
+            "\n",
+            "4.46.2. Analyzing design hierarchy..\n",
+            "Top module:  \\adder\n",
+            "Removed 0 unused modules.\n",
+            "\n",
+            "4.47. Printing statistics.\n",
+            "\n",
+            "=== adder ===\n",
+            "\n",
+            "   Number of wires:                  3\n",
+            "   Number of wire bits:              4\n",
+            "   Number of public wires:           3\n",
+            "   Number of public wire bits:       4\n",
+            "   Number of memories:               0\n",
+            "   Number of memory bits:            0\n",
+            "   Number of processes:              0\n",
+            "   Number of cells:                  2\n",
+            "     SB_LUT4                         2\n",
+            "\n",
+            "4.48. Executing CHECK pass (checking for obvious problems).\n",
+            "Checking module adder...\n",
+            "Found and reported 0 problems.\n",
+            "\n",
+            "yosys> \n",
+            "yosys> \n",
+            "5. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\adder..\n",
+            "\n",
+            "yosys> \n",
+            "6. Generating Graphviz representation of design.\n",
+            "Writing dot description to `synth_ice40.dot'.\n",
+            "Dumping module adder to page 1.\n",
+            "\n",
+            "yosys> exit\n"
+          ]
+        }
+      ]
+    },
+    {
+      "cell_type": "code",
+      "metadata": {
+        "colab": {
+          "base_uri": "https://localhost:8080/",
+          "height": 470
+        },
+        "id": "Tp3nbgutzIK_",
+        "outputId": "7062ea23-6f6c-4749-e205-597fe3573b58"
+      },
+      "source": [
+        "import graphviz\n",
+        "graphviz.Source.from_file('synth_ice40.dot')"
+      ],
+      "execution_count": 12,
+      "outputs": [
+        {
+          "output_type": "execute_result",
+          "data": {
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+            "text/plain": [
+              "<graphviz.sources.Source at 0x7ee015ec8e60>"
+            ]
+          },
+          "metadata": {},
+          "execution_count": 12
+        }
+      ]
+    },
+    {
+      "cell_type": "markdown",
+      "metadata": {
+        "id": "fuTlMelBwLEo"
+      },
+      "source": [
+        "### Synth CMOS\n",
+        "\n",
+        "Synthesize CMOS netlist: map to `NOR` and `NOT` gates using CMOS technology mapping from `yosys examples."
+      ]
+    },
+    {
+      "cell_type": "code",
+      "metadata": {
+        "id": "I34dkQ01xSOj",
+        "colab": {
+          "base_uri": "https://localhost:8080/"
+        },
+        "outputId": "7b55d095-c67a-4216-f681-1be9618bf350"
+      },
+      "source": [
+        "!curl --silent -L https://github.com/YosysHQ/yosys/archive/refs/tags/yosys-0.11.tar.gz | tar xvzf - yosys-yosys-0.11/examples/cmos --strip-components=2"
+      ],
+      "execution_count": 13,
+      "outputs": [
+        {
+          "output_type": "stream",
+          "name": "stdout",
+          "text": [
+            "yosys-yosys-0.11/examples/cmos/\n",
+            "yosys-yosys-0.11/examples/cmos/.gitignore\n",
+            "yosys-yosys-0.11/examples/cmos/README\n",
+            "yosys-yosys-0.11/examples/cmos/cmos_cells.lib\n",
+            "yosys-yosys-0.11/examples/cmos/cmos_cells.sp\n",
+            "yosys-yosys-0.11/examples/cmos/cmos_cells.v\n",
+            "yosys-yosys-0.11/examples/cmos/cmos_cells_digital.sp\n",
+            "yosys-yosys-0.11/examples/cmos/counter.v\n",
+            "yosys-yosys-0.11/examples/cmos/counter.ys\n",
+            "yosys-yosys-0.11/examples/cmos/counter_digital.ys\n",
+            "yosys-yosys-0.11/examples/cmos/counter_tb.gtkw\n",
+            "yosys-yosys-0.11/examples/cmos/counter_tb.v\n",
+            "yosys-yosys-0.11/examples/cmos/testbench.sh\n",
+            "yosys-yosys-0.11/examples/cmos/testbench.sp\n",
+            "yosys-yosys-0.11/examples/cmos/testbench_digital.sh\n",
+            "yosys-yosys-0.11/examples/cmos/testbench_digital.sp\n"
+          ]
+        }
+      ]
+    },
+    {
+      "cell_type": "code",
+      "metadata": {
+        "id": "m2cny9dXwLE1",
+        "colab": {
+          "base_uri": "https://localhost:8080/"
+        },
+        "outputId": "7034fdf5-ee69-4952-84e7-83d958802fd0"
+      },
+      "source": [
+        "%%script miniconda-synth/bin/yosys -Q -T\n",
+        "\n",
+        "read -sv adder.v\n",
+        "hierarchy -top adder\n",
+        "\n",
+        "read -sv -lib cmos/cmos_cells.v\n",
+        "synth\n",
+        "dfflibmap -liberty cmos/cmos_cells.lib\n",
+        "abc -liberty cmos/cmos_cells.lib\n",
+        "\n",
+        "opt_clean\n",
+        "show -format dot -prefix synth_cmos\n",
+        "stat -liberty cmos/cmos_cells.lib"
+      ],
+      "execution_count": 14,
+      "outputs": [
+        {
+          "output_type": "stream",
+          "name": "stdout",
+          "text": [
+            "\n",
+            "yosys> \n",
+            "yosys> \n",
+            "\n",
+            "1. Executing Verilog-2005 frontend: adder.v\n",
+            "Parsing SystemVerilog input from `adder.v' to AST representation.\n",
+            "Storing AST representation for module `$abstract\\adder'.\n",
+            "Successfully finished Verilog frontend.\n",
+            "\n",
+            "yosys> \n",
+            "2. Executing HIERARCHY pass (managing design hierarchy).\n",
+            "\n",
+            "3. Executing AST frontend in derive mode using pre-parsed AST for module `\\adder'.\n",
+            "Generating RTLIL representation for module `\\adder'.\n",
+            "\n",
+            "3.1. Analyzing design hierarchy..\n",
+            "Top module:  \\adder\n",
+            "\n",
+            "3.2. Analyzing design hierarchy..\n",
+            "Top module:  \\adder\n",
+            "Removing unused module `$abstract\\adder'.\n",
+            "Removed 1 unused modules.\n",
+            "\n",
+            "yosys> \n",
+            "yosys> \n",
+            "4. Executing Verilog-2005 frontend: cmos/cmos_cells.v\n",
+            "Parsing SystemVerilog input from `cmos/cmos_cells.v' to AST representation.\n",
+            "Storing AST representation for module `$abstract\\BUF'.\n",
+            "Storing AST representation for module `$abstract\\NOT'.\n",
+            "Storing AST representation for module `$abstract\\NAND'.\n",
+            "Storing AST representation for module `$abstract\\NOR'.\n",
+            "Storing AST representation for module `$abstract\\DFF'.\n",
+            "Storing AST representation for module `$abstract\\DFFSR'.\n",
+            "Successfully finished Verilog frontend.\n",
+            "\n",
+            "yosys> \n",
+            "5. Executing SYNTH pass.\n",
+            "\n",
+            "5.1. Executing HIERARCHY pass (managing design hierarchy).\n",
+            "\n",
+            "5.1.1. Analyzing design hierarchy..\n",
+            "Top module:  \\adder\n",
+            "\n",
+            "5.1.2. Analyzing design hierarchy..\n",
+            "Top module:  \\adder\n",
+            "Removing unused module `$abstract\\DFFSR'.\n",
+            "Removing unused module `$abstract\\DFF'.\n",
+            "Removing unused module `$abstract\\NOR'.\n",
+            "Removing unused module `$abstract\\NAND'.\n",
+            "Removing unused module `$abstract\\NOT'.\n",
+            "Removing unused module `$abstract\\BUF'.\n",
+            "Removed 6 unused modules.\n",
+            "\n",
+            "5.2. Executing PROC pass (convert processes to netlists).\n",
+            "\n",
+            "5.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).\n",
+            "Cleaned up 0 empty switches.\n",
+            "\n",
+            "5.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).\n",
+            "Removed a total of 0 dead cases.\n",
+            "\n",
+            "5.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).\n",
+            "Removed 0 redundant assignments.\n",
+            "Promoted 0 assignments to connections.\n",
+            "\n",
+            "5.2.4. Executing PROC_INIT pass (extract init attributes).\n",
+            "\n",
+            "5.2.5. Executing PROC_ARST pass (detect async resets in processes).\n",
+            "\n",
+            "5.2.6. Executing PROC_MUX pass (convert decision trees to multiplexers).\n",
+            "\n",
+            "5.2.7. Executing PROC_DLATCH pass (convert process syncs to latches).\n",
+            "\n",
+            "5.2.8. Executing PROC_DFF pass (convert process syncs to FFs).\n",
+            "\n",
+            "5.2.9. Executing PROC_MEMWR pass (convert process memory writes to cells).\n",
+            "\n",
+            "5.2.10. Executing PROC_CLEAN pass (remove empty switches from decision trees).\n",
+            "Cleaned up 0 empty switches.\n",
+            "\n",
+            "5.2.11. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module adder.\n",
+            "\n",
+            "5.3. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module adder.\n",
+            "\n",
+            "5.4. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\adder..\n",
+            "Removed 0 unused cells and 1 unused wires.\n",
+            "\n",
+            "5.5. Executing CHECK pass (checking for obvious problems).\n",
+            "Checking module adder...\n",
+            "Found and reported 0 problems.\n",
+            "\n",
+            "5.6. Executing OPT pass (performing simple optimizations).\n",
+            "\n",
+            "5.6.1. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module adder.\n",
+            "\n",
+            "5.6.2. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\adder'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "5.6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n",
+            "Running muxtree optimizer on module \\adder..\n",
+            "  Creating internal representation of mux trees.\n",
+            "  No muxes found in this module.\n",
+            "Removed 0 multiplexer ports.\n",
+            "\n",
+            "5.6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n",
+            "  Optimizing cells in module \\adder.\n",
+            "Performed a total of 0 changes.\n",
+            "\n",
+            "5.6.5. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\adder'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "5.6.6. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "5.6.7. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\adder..\n",
+            "\n",
+            "5.6.8. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module adder.\n",
+            "\n",
+            "5.6.9. Finished OPT passes. (There is nothing left to do.)\n",
+            "\n",
+            "5.7. Executing FSM pass (extract and optimize FSM).\n",
+            "\n",
+            "5.7.1. Executing FSM_DETECT pass (finding FSMs in design).\n",
+            "\n",
+            "5.7.2. Executing FSM_EXTRACT pass (extracting FSM from design).\n",
+            "\n",
+            "5.7.3. Executing FSM_OPT pass (simple optimizations of FSMs).\n",
+            "\n",
+            "5.7.4. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\adder..\n",
+            "\n",
+            "5.7.5. Executing FSM_OPT pass (simple optimizations of FSMs).\n",
+            "\n",
+            "5.7.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).\n",
+            "\n",
+            "5.7.7. Executing FSM_INFO pass (dumping all available information on FSM cells).\n",
+            "\n",
+            "5.7.8. Executing FSM_MAP pass (mapping FSMs to basic logic).\n",
+            "\n",
+            "5.8. Executing OPT pass (performing simple optimizations).\n",
+            "\n",
+            "5.8.1. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module adder.\n",
+            "\n",
+            "5.8.2. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\adder'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "5.8.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n",
+            "Running muxtree optimizer on module \\adder..\n",
+            "  Creating internal representation of mux trees.\n",
+            "  No muxes found in this module.\n",
+            "Removed 0 multiplexer ports.\n",
+            "\n",
+            "5.8.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n",
+            "  Optimizing cells in module \\adder.\n",
+            "Performed a total of 0 changes.\n",
+            "\n",
+            "5.8.5. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\adder'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "5.8.6. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "5.8.7. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\adder..\n",
+            "\n",
+            "5.8.8. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module adder.\n",
+            "\n",
+            "5.8.9. Finished OPT passes. (There is nothing left to do.)\n",
+            "\n",
+            "5.9. Executing WREDUCE pass (reducing word size of cells).\n",
+            "\n",
+            "5.10. Executing PEEPOPT pass (run peephole optimizers).\n",
+            "\n",
+            "5.11. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\adder..\n",
+            "\n",
+            "5.12. Executing ALUMACC pass (create $alu and $macc cells).\n",
+            "Extracting $alu and $macc cells in module adder:\n",
+            "  creating $macc model for $add$adder.v:7$1 ($add).\n",
+            "  creating $alu model for $macc $add$adder.v:7$1.\n",
+            "  creating $alu cell for $add$adder.v:7$1: $auto$alumacc.cc:485:replace_alu$2\n",
+            "  created 1 $alu and 0 $macc cells.\n",
+            "\n",
+            "5.13. Executing SHARE pass (SAT-based resource sharing).\n",
+            "\n",
+            "5.14. Executing OPT pass (performing simple optimizations).\n",
+            "\n",
+            "5.14.1. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module adder.\n",
+            "\n",
+            "5.14.2. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\adder'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "5.14.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n",
+            "Running muxtree optimizer on module \\adder..\n",
+            "  Creating internal representation of mux trees.\n",
+            "  No muxes found in this module.\n",
+            "Removed 0 multiplexer ports.\n",
+            "\n",
+            "5.14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n",
+            "  Optimizing cells in module \\adder.\n",
+            "Performed a total of 0 changes.\n",
+            "\n",
+            "5.14.5. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\adder'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "5.14.6. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "5.14.7. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\adder..\n",
+            "\n",
+            "5.14.8. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module adder.\n",
+            "\n",
+            "5.14.9. Finished OPT passes. (There is nothing left to do.)\n",
+            "\n",
+            "5.15. Executing MEMORY pass.\n",
+            "\n",
+            "5.15.1. Executing OPT_MEM pass (optimize memories).\n",
+            "Performed a total of 0 transformations.\n",
+            "\n",
+            "5.15.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).\n",
+            "Performed a total of 0 transformations.\n",
+            "\n",
+            "5.15.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).\n",
+            "\n",
+            "5.15.4. Executing MEMORY_DFF pass (merging $dff cells to $memrd).\n",
+            "\n",
+            "5.15.5. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\adder..\n",
+            "\n",
+            "5.15.6. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).\n",
+            "\n",
+            "5.15.7. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).\n",
+            "Performed a total of 0 transformations.\n",
+            "\n",
+            "5.15.8. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\adder..\n",
+            "\n",
+            "5.15.9. Executing MEMORY_COLLECT pass (generating $mem cells).\n",
+            "\n",
+            "5.16. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\adder..\n",
+            "\n",
+            "5.17. Executing OPT pass (performing simple optimizations).\n",
+            "\n",
+            "5.17.1. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module adder.\n",
+            "\n",
+            "5.17.2. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\adder'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "5.17.3. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "5.17.4. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\adder..\n",
+            "\n",
+            "5.17.5. Finished fast OPT passes.\n",
+            "\n",
+            "5.18. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).\n",
+            "\n",
+            "5.19. Executing OPT pass (performing simple optimizations).\n",
+            "\n",
+            "5.19.1. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module adder.\n",
+            "\n",
+            "5.19.2. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\adder'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "5.19.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n",
+            "Running muxtree optimizer on module \\adder..\n",
+            "  Creating internal representation of mux trees.\n",
+            "  No muxes found in this module.\n",
+            "Removed 0 multiplexer ports.\n",
+            "\n",
+            "5.19.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n",
+            "  Optimizing cells in module \\adder.\n",
+            "Performed a total of 0 changes.\n",
+            "\n",
+            "5.19.5. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\adder'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "5.19.6. Executing OPT_SHARE pass.\n",
+            "\n",
+            "5.19.7. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "5.19.8. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\adder..\n",
+            "\n",
+            "5.19.9. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module adder.\n",
+            "\n",
+            "5.19.10. Finished OPT passes. (There is nothing left to do.)\n",
+            "\n",
+            "5.20. Executing TECHMAP pass (map to technology primitives).\n",
+            "\n",
+            "5.20.1. Executing Verilog-2005 frontend: /content/miniconda-synth/bin/../share/yosys/techmap.v\n",
+            "Parsing Verilog input from `/content/miniconda-synth/bin/../share/yosys/techmap.v' to AST representation.\n",
+            "Generating RTLIL representation for module `\\_90_simplemap_bool_ops'.\n",
+            "Generating RTLIL representation for module `\\_90_simplemap_reduce_ops'.\n",
+            "Generating RTLIL representation for module `\\_90_simplemap_logic_ops'.\n",
+            "Generating RTLIL representation for module `\\_90_simplemap_compare_ops'.\n",
+            "Generating RTLIL representation for module `\\_90_simplemap_various'.\n",
+            "Generating RTLIL representation for module `\\_90_simplemap_registers'.\n",
+            "Generating RTLIL representation for module `\\_90_shift_ops_shr_shl_sshl_sshr'.\n",
+            "Generating RTLIL representation for module `\\_90_shift_shiftx'.\n",
+            "Generating RTLIL representation for module `\\_90_fa'.\n",
+            "Generating RTLIL representation for module `\\_90_lcu'.\n",
+            "Generating RTLIL representation for module `\\_90_alu'.\n",
+            "Generating RTLIL representation for module `\\_90_macc'.\n",
+            "Generating RTLIL representation for module `\\_90_alumacc'.\n",
+            "Generating RTLIL representation for module `\\$__div_mod_u'.\n",
+            "Generating RTLIL representation for module `\\$__div_mod_trunc'.\n",
+            "Generating RTLIL representation for module `\\_90_div'.\n",
+            "Generating RTLIL representation for module `\\_90_mod'.\n",
+            "Generating RTLIL representation for module `\\$__div_mod_floor'.\n",
+            "Generating RTLIL representation for module `\\_90_divfloor'.\n",
+            "Generating RTLIL representation for module `\\_90_modfloor'.\n",
+            "Generating RTLIL representation for module `\\_90_pow'.\n",
+            "Generating RTLIL representation for module `\\_90_pmux'.\n",
+            "Generating RTLIL representation for module `\\_90_demux'.\n",
+            "Generating RTLIL representation for module `\\_90_lut'.\n",
+            "Successfully finished Verilog frontend.\n",
+            "\n",
+            "5.20.2. Continuing TECHMAP pass.\n",
+            "Using template $paramod$1d1e68f77481583066c6d429218f48ea9d5739b3\\_90_alu for cells of type $alu.\n",
+            "Using extmapper simplemap for cells of type $xor.\n",
+            "Using extmapper simplemap for cells of type $and.\n",
+            "Using template $paramod\\_90_lcu\\WIDTH=32'00000000000000000000000000000010 for cells of type $lcu.\n",
+            "Using extmapper simplemap for cells of type $pos.\n",
+            "Using extmapper simplemap for cells of type $mux.\n",
+            "Using extmapper simplemap for cells of type $not.\n",
+            "Using extmapper simplemap for cells of type $or.\n",
+            "No more expansions possible.\n",
+            "\n",
+            "5.21. Executing OPT pass (performing simple optimizations).\n",
+            "\n",
+            "5.21.1. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module adder.\n",
+            "\n",
+            "5.21.2. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\adder'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "5.21.3. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "5.21.4. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\adder..\n",
+            "Removed 1 unused cells and 29 unused wires.\n",
+            "\n",
+            "5.21.5. Finished fast OPT passes.\n",
+            "\n",
+            "5.22. Executing ABC pass (technology mapping using ABC).\n",
+            "\n",
+            "5.22.1. Extracting gate netlist of module `\\adder' to `<abc-temp-dir>/input.blif'..\n",
+            "Extracted 2 gates and 4 wires to a netlist network with 2 inputs and 2 outputs.\n",
+            "\n",
+            "5.22.1.1. Executing ABC.\n",
+            "Running ABC command: <yosys-exe-dir>/yosys-abc -s -f <abc-temp-dir>/abc.script 2>&1\n",
+            "ABC: ABC command line: \"source <abc-temp-dir>/abc.script\".\n",
+            "ABC: \n",
+            "ABC: + read_blif <abc-temp-dir>/input.blif \n",
+            "ABC: + read_library <abc-temp-dir>/stdcells.genlib \n",
+            "ABC: Entered genlib library with 13 gates from file \"<abc-temp-dir>/stdcells.genlib\".\n",
+            "ABC: + strash \n",
+            "ABC: + dretime \n",
+            "ABC: + map \n",
+            "ABC: + write_blif <abc-temp-dir>/output.blif \n",
+            "\n",
+            "5.22.1.2. Re-integrating ABC results.\n",
+            "ABC RESULTS:               AND cells:        1\n",
+            "ABC RESULTS:               XOR cells:        1\n",
+            "ABC RESULTS:        internal signals:        0\n",
+            "ABC RESULTS:           input signals:        2\n",
+            "ABC RESULTS:          output signals:        2\n",
+            "Removing temp directory.\n",
+            "\n",
+            "5.23. Executing OPT pass (performing simple optimizations).\n",
+            "\n",
+            "5.23.1. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module adder.\n",
+            "\n",
+            "5.23.2. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\adder'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "5.23.3. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "5.23.4. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\adder..\n",
+            "Removed 0 unused cells and 4 unused wires.\n",
+            "\n",
+            "5.23.5. Finished fast OPT passes.\n",
+            "\n",
+            "5.24. Executing HIERARCHY pass (managing design hierarchy).\n",
+            "\n",
+            "5.24.1. Analyzing design hierarchy..\n",
+            "Top module:  \\adder\n",
+            "\n",
+            "5.24.2. Analyzing design hierarchy..\n",
+            "Top module:  \\adder\n",
+            "Removed 0 unused modules.\n",
+            "\n",
+            "5.25. Printing statistics.\n",
+            "\n",
+            "=== adder ===\n",
+            "\n",
+            "   Number of wires:                  3\n",
+            "   Number of wire bits:              4\n",
+            "   Number of public wires:           3\n",
+            "   Number of public wire bits:       4\n",
+            "   Number of memories:               0\n",
+            "   Number of memory bits:            0\n",
+            "   Number of processes:              0\n",
+            "   Number of cells:                  2\n",
+            "     $_AND_                          1\n",
+            "     $_XOR_                          1\n",
+            "\n",
+            "5.26. Executing CHECK pass (checking for obvious problems).\n",
+            "Checking module adder...\n",
+            "Found and reported 0 problems.\n",
+            "\n",
+            "yosys> \n",
+            "6. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).\n",
+            "  cell DFF (noninv, pins=3, area=18.00) is a direct match for cell type $_DFF_P_.\n",
+            "  cell DFFSR (noninv, pins=5, area=18.00) is a direct match for cell type $_DFFSR_PPP_.\n",
+            "  final dff cell mappings:\n",
+            "    unmapped dff cell: $_DFF_N_\n",
+            "    \\DFF _DFF_P_ (.C( C), .D( D), .Q( Q));\n",
+            "    unmapped dff cell: $_DFF_NN0_\n",
+            "    unmapped dff cell: $_DFF_NN1_\n",
+            "    unmapped dff cell: $_DFF_NP0_\n",
+            "    unmapped dff cell: $_DFF_NP1_\n",
+            "    unmapped dff cell: $_DFF_PN0_\n",
+            "    unmapped dff cell: $_DFF_PN1_\n",
+            "    unmapped dff cell: $_DFF_PP0_\n",
+            "    unmapped dff cell: $_DFF_PP1_\n",
+            "    unmapped dff cell: $_DFFSR_NNN_\n",
+            "    unmapped dff cell: $_DFFSR_NNP_\n",
+            "    unmapped dff cell: $_DFFSR_NPN_\n",
+            "    unmapped dff cell: $_DFFSR_NPP_\n",
+            "    unmapped dff cell: $_DFFSR_PNN_\n",
+            "    unmapped dff cell: $_DFFSR_PNP_\n",
+            "    unmapped dff cell: $_DFFSR_PPN_\n",
+            "    \\DFFSR _DFFSR_PPP_ (.C( C), .D( D), .Q( Q), .R( R), .S( S));\n",
+            "\n",
+            "6.1. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).\n",
+            "Mapping DFF cells in module `\\adder':\n",
+            "\n",
+            "yosys> \n",
+            "7. Executing ABC pass (technology mapping using ABC).\n",
+            "\n",
+            "7.1. Extracting gate netlist of module `\\adder' to `<abc-temp-dir>/input.blif'..\n",
+            "Extracted 2 gates and 4 wires to a netlist network with 2 inputs and 2 outputs.\n",
+            "\n",
+            "7.1.1. Executing ABC.\n",
+            "Running ABC command: <yosys-exe-dir>/yosys-abc -s -f <abc-temp-dir>/abc.script 2>&1\n",
+            "ABC: ABC command line: \"source <abc-temp-dir>/abc.script\".\n",
+            "ABC: \n",
+            "ABC: + read_blif <abc-temp-dir>/input.blif \n",
+            "ABC: + read_lib -w /content/cmos/cmos_cells.lib \n",
+            "ABC: Parsing finished successfully.  Parsing time =     0.00 sec\n",
+            "ABC: Warning: Templates are not defined.\n",
+            "ABC: Libery parser cannot read \"time_unit\".  Assuming   time_unit : \"1ns\".\n",
+            "ABC: Libery parser cannot read \"capacitive_load_unit\". Assuming   capacitive_load_unit(1, pf).\n",
+            "ABC: Scl_LibertyReadGenlib() skipped sequential cell \"DFF\".\n",
+            "ABC: Scl_LibertyReadGenlib() skipped sequential cell \"DFFSR\".\n",
+            "ABC: Library \"demo\" from \"/content/cmos/cmos_cells.lib\" has 4 cells (2 skipped: 2 seq; 0 tri-state; 0 no func; 0 dont_use).  Time =     0.00 sec\n",
+            "ABC: Memory =    0.00 MB. Time =     0.00 sec\n",
+            "ABC: + strash \n",
+            "ABC: + ifraig \n",
+            "ABC: + scorr \n",
+            "ABC: Warning: The network is combinational (run \"fraig\" or \"fraig_sweep\").\n",
+            "ABC: + dc2 \n",
+            "ABC: + dretime \n",
+            "ABC: + strash \n",
+            "ABC: + &get -n \n",
+            "ABC: + &dch -f \n",
+            "ABC: + &nf \n",
+            "ABC: + &put \n",
+            "ABC: + write_blif <abc-temp-dir>/output.blif \n",
+            "\n",
+            "7.1.2. Re-integrating ABC results.\n",
+            "ABC RESULTS:               NOR cells:        3\n",
+            "ABC RESULTS:               NOT cells:        2\n",
+            "ABC RESULTS:        internal signals:        0\n",
+            "ABC RESULTS:           input signals:        2\n",
+            "ABC RESULTS:          output signals:        2\n",
+            "Removing temp directory.\n",
+            "\n",
+            "yosys> \n",
+            "yosys> \n",
+            "8. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\adder..\n",
+            "Removed 0 unused cells and 4 unused wires.\n",
+            "\n",
+            "yosys> \n",
+            "9. Generating Graphviz representation of design.\n",
+            "Writing dot description to `synth_cmos.dot'.\n",
+            "Dumping module adder to page 1.\n",
+            "\n",
+            "yosys> \n",
+            "10. Printing statistics.\n",
+            "\n",
+            "=== adder ===\n",
+            "\n",
+            "   Number of wires:                  6\n",
+            "   Number of wire bits:              7\n",
+            "   Number of public wires:           3\n",
+            "   Number of public wire bits:       4\n",
+            "   Number of memories:               0\n",
+            "   Number of memory bits:            0\n",
+            "   Number of processes:              0\n",
+            "   Number of cells:                  5\n",
+            "     NOR                             3\n",
+            "     NOT                             2\n",
+            "\n",
+            "   Chip area for module '\\adder': 18.000000\n",
+            "\n",
+            "\n",
+            "yosys> exit\n"
+          ]
+        }
+      ]
+    },
+    {
+      "cell_type": "code",
+      "metadata": {
+        "colab": {
+          "base_uri": "https://localhost:8080/",
+          "height": 621
+        },
+        "id": "8FhBL03awLE2",
+        "outputId": "09cf2138-e365-4a0b-cc32-1b36ed43e5ae"
+      },
+      "source": [
+        "import graphviz\n",
+        "graphviz.Source.from_file('synth_cmos.dot')"
+      ],
+      "execution_count": 15,
+      "outputs": [
+        {
+          "output_type": "execute_result",
+          "data": {
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+            "text/plain": [
+              "<graphviz.sources.Source at 0x7ee0152a7f50>"
+            ]
+          },
+          "metadata": {},
+          "execution_count": 15
+        }
+      ]
+    },
+    {
+      "cell_type": "markdown",
+      "metadata": {
+        "id": "NIEm0b5h0Bej"
+      },
+      "source": [
+        "### Synth 74xx\n",
+        "\n",
+        "Synthesize 74xx netlist: map to `74AC08` a nd `74AC86` discrete gate ICs using community provided technology mapping."
+      ]
+    },
+    {
+      "cell_type": "code",
+      "metadata": {
+        "id": "ap3OuVzD1omG",
+        "colab": {
+          "base_uri": "https://localhost:8080/"
+        },
+        "outputId": "3407c6f2-35e5-42a8-8cc8-1513d2af901e"
+      },
+      "source": [
+        "!git clone https://github.com/Ravenslofty/74xx-liberty"
+      ],
+      "execution_count": 16,
+      "outputs": [
+        {
+          "output_type": "stream",
+          "name": "stdout",
+          "text": [
+            "Cloning into '74xx-liberty'...\n",
+            "remote: Enumerating objects: 238, done.\u001b[K\n",
+            "remote: Counting objects: 100% (68/68), done.\u001b[K\n",
+            "remote: Compressing objects: 100% (10/10), done.\u001b[K\n",
+            "remote: Total 238 (delta 59), reused 58 (delta 58), pack-reused 170 (from 1)\u001b[K\n",
+            "Receiving objects: 100% (238/238), 112.96 KiB | 4.18 MiB/s, done.\n",
+            "Resolving deltas: 100% (128/128), done.\n"
+          ]
+        }
+      ]
+    },
+    {
+      "cell_type": "code",
+      "metadata": {
+        "id": "8FDlOsUe0Bet",
+        "colab": {
+          "base_uri": "https://localhost:8080/"
+        },
+        "outputId": "57b1d9b3-3faf-4a09-9a19-0214e4affd05"
+      },
+      "source": [
+        "%%script miniconda-synth/bin/yosys -Q -T\n",
+        "\n",
+        "read -sv adder.v\n",
+        "hierarchy -top adder\n",
+        "\n",
+        "read -sv -lib 74xx-liberty/74_models.v\n",
+        "synth\n",
+        "abc -liberty 74xx-liberty/74ac.lib\n",
+        "dfflibmap -liberty 74xx-liberty/74ac.lib\n",
+        "\n",
+        "opt_clean\n",
+        "show -format dot -prefix synth_74\n",
+        "stat -liberty 74xx-liberty/74ac.lib"
+      ],
+      "execution_count": 17,
+      "outputs": [
+        {
+          "output_type": "stream",
+          "name": "stdout",
+          "text": [
+            "\n",
+            "yosys> \n",
+            "yosys> \n",
+            "\n",
+            "1. Executing Verilog-2005 frontend: adder.v\n",
+            "Parsing SystemVerilog input from `adder.v' to AST representation.\n",
+            "Storing AST representation for module `$abstract\\adder'.\n",
+            "Successfully finished Verilog frontend.\n",
+            "\n",
+            "yosys> \n",
+            "2. Executing HIERARCHY pass (managing design hierarchy).\n",
+            "\n",
+            "3. Executing AST frontend in derive mode using pre-parsed AST for module `\\adder'.\n",
+            "Generating RTLIL representation for module `\\adder'.\n",
+            "\n",
+            "3.1. Analyzing design hierarchy..\n",
+            "Top module:  \\adder\n",
+            "\n",
+            "3.2. Analyzing design hierarchy..\n",
+            "Top module:  \\adder\n",
+            "Removing unused module `$abstract\\adder'.\n",
+            "Removed 1 unused modules.\n",
+            "\n",
+            "yosys> \n",
+            "yosys> \n",
+            "4. Executing Verilog-2005 frontend: 74xx-liberty/74_models.v\n",
+            "Parsing SystemVerilog input from `74xx-liberty/74_models.v' to AST representation.\n",
+            "Storing AST representation for module `$abstract\\74HC85_1x1CMP4'.\n",
+            "Storing AST representation for module `$abstract\\74AC283_1x1ADD4'.\n",
+            "Storing AST representation for module `$abstract\\74AC377_8x1DFFE'.\n",
+            "Storing AST representation for module `$abstract\\74HC688_1x1EQ8'.\n",
+            "Storing AST representation for module `$abstract\\74AC161_1x1COUNT4'.\n",
+            "Successfully finished Verilog frontend.\n",
+            "\n",
+            "yosys> \n",
+            "5. Executing SYNTH pass.\n",
+            "\n",
+            "5.1. Executing HIERARCHY pass (managing design hierarchy).\n",
+            "\n",
+            "5.1.1. Analyzing design hierarchy..\n",
+            "Top module:  \\adder\n",
+            "\n",
+            "5.1.2. Analyzing design hierarchy..\n",
+            "Top module:  \\adder\n",
+            "Removing unused module `$abstract\\74AC161_1x1COUNT4'.\n",
+            "Removing unused module `$abstract\\74HC688_1x1EQ8'.\n",
+            "Removing unused module `$abstract\\74AC377_8x1DFFE'.\n",
+            "Removing unused module `$abstract\\74AC283_1x1ADD4'.\n",
+            "Removing unused module `$abstract\\74HC85_1x1CMP4'.\n",
+            "Removed 5 unused modules.\n",
+            "\n",
+            "5.2. Executing PROC pass (convert processes to netlists).\n",
+            "\n",
+            "5.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).\n",
+            "Cleaned up 0 empty switches.\n",
+            "\n",
+            "5.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).\n",
+            "Removed a total of 0 dead cases.\n",
+            "\n",
+            "5.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).\n",
+            "Removed 0 redundant assignments.\n",
+            "Promoted 0 assignments to connections.\n",
+            "\n",
+            "5.2.4. Executing PROC_INIT pass (extract init attributes).\n",
+            "\n",
+            "5.2.5. Executing PROC_ARST pass (detect async resets in processes).\n",
+            "\n",
+            "5.2.6. Executing PROC_MUX pass (convert decision trees to multiplexers).\n",
+            "\n",
+            "5.2.7. Executing PROC_DLATCH pass (convert process syncs to latches).\n",
+            "\n",
+            "5.2.8. Executing PROC_DFF pass (convert process syncs to FFs).\n",
+            "\n",
+            "5.2.9. Executing PROC_MEMWR pass (convert process memory writes to cells).\n",
+            "\n",
+            "5.2.10. Executing PROC_CLEAN pass (remove empty switches from decision trees).\n",
+            "Cleaned up 0 empty switches.\n",
+            "\n",
+            "5.2.11. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module adder.\n",
+            "\n",
+            "5.3. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module adder.\n",
+            "\n",
+            "5.4. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\adder..\n",
+            "Removed 0 unused cells and 1 unused wires.\n",
+            "\n",
+            "5.5. Executing CHECK pass (checking for obvious problems).\n",
+            "Checking module adder...\n",
+            "Found and reported 0 problems.\n",
+            "\n",
+            "5.6. Executing OPT pass (performing simple optimizations).\n",
+            "\n",
+            "5.6.1. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module adder.\n",
+            "\n",
+            "5.6.2. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\adder'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "5.6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n",
+            "Running muxtree optimizer on module \\adder..\n",
+            "  Creating internal representation of mux trees.\n",
+            "  No muxes found in this module.\n",
+            "Removed 0 multiplexer ports.\n",
+            "\n",
+            "5.6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n",
+            "  Optimizing cells in module \\adder.\n",
+            "Performed a total of 0 changes.\n",
+            "\n",
+            "5.6.5. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\adder'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "5.6.6. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "5.6.7. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\adder..\n",
+            "\n",
+            "5.6.8. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module adder.\n",
+            "\n",
+            "5.6.9. Finished OPT passes. (There is nothing left to do.)\n",
+            "\n",
+            "5.7. Executing FSM pass (extract and optimize FSM).\n",
+            "\n",
+            "5.7.1. Executing FSM_DETECT pass (finding FSMs in design).\n",
+            "\n",
+            "5.7.2. Executing FSM_EXTRACT pass (extracting FSM from design).\n",
+            "\n",
+            "5.7.3. Executing FSM_OPT pass (simple optimizations of FSMs).\n",
+            "\n",
+            "5.7.4. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\adder..\n",
+            "\n",
+            "5.7.5. Executing FSM_OPT pass (simple optimizations of FSMs).\n",
+            "\n",
+            "5.7.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).\n",
+            "\n",
+            "5.7.7. Executing FSM_INFO pass (dumping all available information on FSM cells).\n",
+            "\n",
+            "5.7.8. Executing FSM_MAP pass (mapping FSMs to basic logic).\n",
+            "\n",
+            "5.8. Executing OPT pass (performing simple optimizations).\n",
+            "\n",
+            "5.8.1. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module adder.\n",
+            "\n",
+            "5.8.2. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\adder'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "5.8.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n",
+            "Running muxtree optimizer on module \\adder..\n",
+            "  Creating internal representation of mux trees.\n",
+            "  No muxes found in this module.\n",
+            "Removed 0 multiplexer ports.\n",
+            "\n",
+            "5.8.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n",
+            "  Optimizing cells in module \\adder.\n",
+            "Performed a total of 0 changes.\n",
+            "\n",
+            "5.8.5. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\adder'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "5.8.6. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "5.8.7. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\adder..\n",
+            "\n",
+            "5.8.8. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module adder.\n",
+            "\n",
+            "5.8.9. Finished OPT passes. (There is nothing left to do.)\n",
+            "\n",
+            "5.9. Executing WREDUCE pass (reducing word size of cells).\n",
+            "\n",
+            "5.10. Executing PEEPOPT pass (run peephole optimizers).\n",
+            "\n",
+            "5.11. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\adder..\n",
+            "\n",
+            "5.12. Executing ALUMACC pass (create $alu and $macc cells).\n",
+            "Extracting $alu and $macc cells in module adder:\n",
+            "  creating $macc model for $add$adder.v:7$1 ($add).\n",
+            "  creating $alu model for $macc $add$adder.v:7$1.\n",
+            "  creating $alu cell for $add$adder.v:7$1: $auto$alumacc.cc:485:replace_alu$2\n",
+            "  created 1 $alu and 0 $macc cells.\n",
+            "\n",
+            "5.13. Executing SHARE pass (SAT-based resource sharing).\n",
+            "\n",
+            "5.14. Executing OPT pass (performing simple optimizations).\n",
+            "\n",
+            "5.14.1. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module adder.\n",
+            "\n",
+            "5.14.2. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\adder'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "5.14.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n",
+            "Running muxtree optimizer on module \\adder..\n",
+            "  Creating internal representation of mux trees.\n",
+            "  No muxes found in this module.\n",
+            "Removed 0 multiplexer ports.\n",
+            "\n",
+            "5.14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n",
+            "  Optimizing cells in module \\adder.\n",
+            "Performed a total of 0 changes.\n",
+            "\n",
+            "5.14.5. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\adder'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "5.14.6. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "5.14.7. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\adder..\n",
+            "\n",
+            "5.14.8. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module adder.\n",
+            "\n",
+            "5.14.9. Finished OPT passes. (There is nothing left to do.)\n",
+            "\n",
+            "5.15. Executing MEMORY pass.\n",
+            "\n",
+            "5.15.1. Executing OPT_MEM pass (optimize memories).\n",
+            "Performed a total of 0 transformations.\n",
+            "\n",
+            "5.15.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).\n",
+            "Performed a total of 0 transformations.\n",
+            "\n",
+            "5.15.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).\n",
+            "\n",
+            "5.15.4. Executing MEMORY_DFF pass (merging $dff cells to $memrd).\n",
+            "\n",
+            "5.15.5. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\adder..\n",
+            "\n",
+            "5.15.6. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).\n",
+            "\n",
+            "5.15.7. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).\n",
+            "Performed a total of 0 transformations.\n",
+            "\n",
+            "5.15.8. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\adder..\n",
+            "\n",
+            "5.15.9. Executing MEMORY_COLLECT pass (generating $mem cells).\n",
+            "\n",
+            "5.16. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\adder..\n",
+            "\n",
+            "5.17. Executing OPT pass (performing simple optimizations).\n",
+            "\n",
+            "5.17.1. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module adder.\n",
+            "\n",
+            "5.17.2. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\adder'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "5.17.3. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "5.17.4. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\adder..\n",
+            "\n",
+            "5.17.5. Finished fast OPT passes.\n",
+            "\n",
+            "5.18. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).\n",
+            "\n",
+            "5.19. Executing OPT pass (performing simple optimizations).\n",
+            "\n",
+            "5.19.1. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module adder.\n",
+            "\n",
+            "5.19.2. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\adder'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "5.19.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n",
+            "Running muxtree optimizer on module \\adder..\n",
+            "  Creating internal representation of mux trees.\n",
+            "  No muxes found in this module.\n",
+            "Removed 0 multiplexer ports.\n",
+            "\n",
+            "5.19.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n",
+            "  Optimizing cells in module \\adder.\n",
+            "Performed a total of 0 changes.\n",
+            "\n",
+            "5.19.5. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\adder'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "5.19.6. Executing OPT_SHARE pass.\n",
+            "\n",
+            "5.19.7. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "5.19.8. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\adder..\n",
+            "\n",
+            "5.19.9. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module adder.\n",
+            "\n",
+            "5.19.10. Finished OPT passes. (There is nothing left to do.)\n",
+            "\n",
+            "5.20. Executing TECHMAP pass (map to technology primitives).\n",
+            "\n",
+            "5.20.1. Executing Verilog-2005 frontend: /content/miniconda-synth/bin/../share/yosys/techmap.v\n",
+            "Parsing Verilog input from `/content/miniconda-synth/bin/../share/yosys/techmap.v' to AST representation.\n",
+            "Generating RTLIL representation for module `\\_90_simplemap_bool_ops'.\n",
+            "Generating RTLIL representation for module `\\_90_simplemap_reduce_ops'.\n",
+            "Generating RTLIL representation for module `\\_90_simplemap_logic_ops'.\n",
+            "Generating RTLIL representation for module `\\_90_simplemap_compare_ops'.\n",
+            "Generating RTLIL representation for module `\\_90_simplemap_various'.\n",
+            "Generating RTLIL representation for module `\\_90_simplemap_registers'.\n",
+            "Generating RTLIL representation for module `\\_90_shift_ops_shr_shl_sshl_sshr'.\n",
+            "Generating RTLIL representation for module `\\_90_shift_shiftx'.\n",
+            "Generating RTLIL representation for module `\\_90_fa'.\n",
+            "Generating RTLIL representation for module `\\_90_lcu'.\n",
+            "Generating RTLIL representation for module `\\_90_alu'.\n",
+            "Generating RTLIL representation for module `\\_90_macc'.\n",
+            "Generating RTLIL representation for module `\\_90_alumacc'.\n",
+            "Generating RTLIL representation for module `\\$__div_mod_u'.\n",
+            "Generating RTLIL representation for module `\\$__div_mod_trunc'.\n",
+            "Generating RTLIL representation for module `\\_90_div'.\n",
+            "Generating RTLIL representation for module `\\_90_mod'.\n",
+            "Generating RTLIL representation for module `\\$__div_mod_floor'.\n",
+            "Generating RTLIL representation for module `\\_90_divfloor'.\n",
+            "Generating RTLIL representation for module `\\_90_modfloor'.\n",
+            "Generating RTLIL representation for module `\\_90_pow'.\n",
+            "Generating RTLIL representation for module `\\_90_pmux'.\n",
+            "Generating RTLIL representation for module `\\_90_demux'.\n",
+            "Generating RTLIL representation for module `\\_90_lut'.\n",
+            "Successfully finished Verilog frontend.\n",
+            "\n",
+            "5.20.2. Continuing TECHMAP pass.\n",
+            "Using template $paramod$1d1e68f77481583066c6d429218f48ea9d5739b3\\_90_alu for cells of type $alu.\n",
+            "Using extmapper simplemap for cells of type $xor.\n",
+            "Using extmapper simplemap for cells of type $and.\n",
+            "Using template $paramod\\_90_lcu\\WIDTH=32'00000000000000000000000000000010 for cells of type $lcu.\n",
+            "Using extmapper simplemap for cells of type $pos.\n",
+            "Using extmapper simplemap for cells of type $mux.\n",
+            "Using extmapper simplemap for cells of type $not.\n",
+            "Using extmapper simplemap for cells of type $or.\n",
+            "No more expansions possible.\n",
+            "\n",
+            "5.21. Executing OPT pass (performing simple optimizations).\n",
+            "\n",
+            "5.21.1. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module adder.\n",
+            "\n",
+            "5.21.2. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\adder'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "5.21.3. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "5.21.4. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\adder..\n",
+            "Removed 1 unused cells and 29 unused wires.\n",
+            "\n",
+            "5.21.5. Finished fast OPT passes.\n",
+            "\n",
+            "5.22. Executing ABC pass (technology mapping using ABC).\n",
+            "\n",
+            "5.22.1. Extracting gate netlist of module `\\adder' to `<abc-temp-dir>/input.blif'..\n",
+            "Extracted 2 gates and 4 wires to a netlist network with 2 inputs and 2 outputs.\n",
+            "\n",
+            "5.22.1.1. Executing ABC.\n",
+            "Running ABC command: <yosys-exe-dir>/yosys-abc -s -f <abc-temp-dir>/abc.script 2>&1\n",
+            "ABC: ABC command line: \"source <abc-temp-dir>/abc.script\".\n",
+            "ABC: \n",
+            "ABC: + read_blif <abc-temp-dir>/input.blif \n",
+            "ABC: + read_library <abc-temp-dir>/stdcells.genlib \n",
+            "ABC: Entered genlib library with 13 gates from file \"<abc-temp-dir>/stdcells.genlib\".\n",
+            "ABC: + strash \n",
+            "ABC: + dretime \n",
+            "ABC: + map \n",
+            "ABC: + write_blif <abc-temp-dir>/output.blif \n",
+            "\n",
+            "5.22.1.2. Re-integrating ABC results.\n",
+            "ABC RESULTS:               AND cells:        1\n",
+            "ABC RESULTS:               XOR cells:        1\n",
+            "ABC RESULTS:        internal signals:        0\n",
+            "ABC RESULTS:           input signals:        2\n",
+            "ABC RESULTS:          output signals:        2\n",
+            "Removing temp directory.\n",
+            "\n",
+            "5.23. Executing OPT pass (performing simple optimizations).\n",
+            "\n",
+            "5.23.1. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module adder.\n",
+            "\n",
+            "5.23.2. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\adder'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "5.23.3. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "5.23.4. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\adder..\n",
+            "Removed 0 unused cells and 4 unused wires.\n",
+            "\n",
+            "5.23.5. Finished fast OPT passes.\n",
+            "\n",
+            "5.24. Executing HIERARCHY pass (managing design hierarchy).\n",
+            "\n",
+            "5.24.1. Analyzing design hierarchy..\n",
+            "Top module:  \\adder\n",
+            "\n",
+            "5.24.2. Analyzing design hierarchy..\n",
+            "Top module:  \\adder\n",
+            "Removed 0 unused modules.\n",
+            "\n",
+            "5.25. Printing statistics.\n",
+            "\n",
+            "=== adder ===\n",
+            "\n",
+            "   Number of wires:                  3\n",
+            "   Number of wire bits:              4\n",
+            "   Number of public wires:           3\n",
+            "   Number of public wire bits:       4\n",
+            "   Number of memories:               0\n",
+            "   Number of memory bits:            0\n",
+            "   Number of processes:              0\n",
+            "   Number of cells:                  2\n",
+            "     $_AND_                          1\n",
+            "     $_XOR_                          1\n",
+            "\n",
+            "5.26. Executing CHECK pass (checking for obvious problems).\n",
+            "Checking module adder...\n",
+            "Found and reported 0 problems.\n",
+            "\n",
+            "yosys> \n",
+            "6. Executing ABC pass (technology mapping using ABC).\n",
+            "\n",
+            "6.1. Extracting gate netlist of module `\\adder' to `<abc-temp-dir>/input.blif'..\n",
+            "Extracted 2 gates and 4 wires to a netlist network with 2 inputs and 2 outputs.\n",
+            "\n",
+            "6.1.1. Executing ABC.\n",
+            "Running ABC command: <yosys-exe-dir>/yosys-abc -s -f <abc-temp-dir>/abc.script 2>&1\n",
+            "ABC: ABC command line: \"source <abc-temp-dir>/abc.script\".\n",
+            "ABC: \n",
+            "ABC: + read_blif <abc-temp-dir>/input.blif \n",
+            "ABC: + read_lib -w /content/74xx-liberty/74ac.lib \n",
+            "ABC: Parsing finished successfully.  Parsing time =     0.00 sec\n",
+            "ABC: Warning: Templates are not defined.\n",
+            "ABC: Scl_LibertyReadGenlib() skipped sequential cell \"74AC74_2x1DFFSR\".\n",
+            "ABC: Scl_LibertyReadGenlib() skipped sequential cell \"74AC273_8x1DFFR\".\n",
+            "ABC: Scl_LibertyReadGenlib() skipped sequential cell \"74AC374_8x1DFF\".\n",
+            "ABC: Library \"74series\" from \"/content/74xx-liberty/74ac.lib\" has 13 cells (3 skipped: 3 seq; 0 tri-state; 0 no func; 0 dont_use).  Time =     0.00 sec\n",
+            "ABC: Memory =    0.02 MB. Time =     0.00 sec\n",
+            "ABC: + strash \n",
+            "ABC: + ifraig \n",
+            "ABC: + scorr \n",
+            "ABC: Warning: The network is combinational (run \"fraig\" or \"fraig_sweep\").\n",
+            "ABC: + dc2 \n",
+            "ABC: + dretime \n",
+            "ABC: + strash \n",
+            "ABC: + &get -n \n",
+            "ABC: + &dch -f \n",
+            "ABC: + &nf \n",
+            "ABC: + &put \n",
+            "ABC: + write_blif <abc-temp-dir>/output.blif \n",
+            "\n",
+            "6.1.2. Re-integrating ABC results.\n",
+            "ABC RESULTS:   \\74AC08_4x1AND2 cells:        1\n",
+            "ABC RESULTS:   \\74AC86_4x1XOR2 cells:        1\n",
+            "ABC RESULTS:        internal signals:        0\n",
+            "ABC RESULTS:           input signals:        2\n",
+            "ABC RESULTS:          output signals:        2\n",
+            "Removing temp directory.\n",
+            "\n",
+            "yosys> \n",
+            "7. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).\n",
+            "  cell 74AC374_8x1DFF (noninv, pins=3, area=2.06) is a direct match for cell type $_DFF_P_.\n",
+            "  cell 74AC273_8x1DFFR (noninv, pins=4, area=2.25) is a direct match for cell type $_DFF_PN0_.\n",
+            "  cell 74AC74_2x1DFFSR (noninv, pins=5, area=5.00) is a direct match for cell type $_DFFSR_PNN_.\n",
+            "  final dff cell mappings:\n",
+            "    unmapped dff cell: $_DFF_N_\n",
+            "    \\74AC374_8x1DFF _DFF_P_ (.CLK( C), .D( D), .Q( Q));\n",
+            "    unmapped dff cell: $_DFF_NN0_\n",
+            "    unmapped dff cell: $_DFF_NN1_\n",
+            "    unmapped dff cell: $_DFF_NP0_\n",
+            "    unmapped dff cell: $_DFF_NP1_\n",
+            "    \\74AC273_8x1DFFR _DFF_PN0_ (.C( R), .CLK( C), .D( D), .Q( Q));\n",
+            "    unmapped dff cell: $_DFF_PN1_\n",
+            "    unmapped dff cell: $_DFF_PP0_\n",
+            "    unmapped dff cell: $_DFF_PP1_\n",
+            "    unmapped dff cell: $_DFFSR_NNN_\n",
+            "    unmapped dff cell: $_DFFSR_NNP_\n",
+            "    unmapped dff cell: $_DFFSR_NPN_\n",
+            "    unmapped dff cell: $_DFFSR_NPP_\n",
+            "    \\74AC74_2x1DFFSR _DFFSR_PNN_ (.C( R), .CLK( C), .D( D), .P( S), .Q( Q));\n",
+            "    unmapped dff cell: $_DFFSR_PNP_\n",
+            "    unmapped dff cell: $_DFFSR_PPN_\n",
+            "    unmapped dff cell: $_DFFSR_PPP_\n",
+            "\n",
+            "7.1. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).\n",
+            "Mapping DFF cells in module `\\adder':\n",
+            "\n",
+            "yosys> \n",
+            "yosys> \n",
+            "8. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\adder..\n",
+            "Removed 0 unused cells and 4 unused wires.\n",
+            "\n",
+            "yosys> \n",
+            "9. Generating Graphviz representation of design.\n",
+            "Writing dot description to `synth_74.dot'.\n",
+            "Dumping module adder to page 1.\n",
+            "\n",
+            "yosys> \n",
+            "10. Printing statistics.\n",
+            "\n",
+            "=== adder ===\n",
+            "\n",
+            "   Number of wires:                  3\n",
+            "   Number of wire bits:              4\n",
+            "   Number of public wires:           3\n",
+            "   Number of public wire bits:       4\n",
+            "   Number of memories:               0\n",
+            "   Number of memory bits:            0\n",
+            "   Number of processes:              0\n",
+            "   Number of cells:                  2\n",
+            "     \\74AC08_4x1AND2                 1\n",
+            "     \\74AC86_4x1XOR2                 1\n",
+            "\n",
+            "   Chip area for module '\\adder': 6.000000\n",
+            "\n",
+            "\n",
+            "yosys> exit\n"
+          ]
+        }
+      ]
+    },
+    {
+      "cell_type": "code",
+      "metadata": {
+        "colab": {
+          "base_uri": "https://localhost:8080/",
+          "height": 330
+        },
+        "id": "JNsm6Rxa0Beu",
+        "outputId": "31893a21-187a-4285-8bef-dd8e43b4fe66"
+      },
+      "source": [
+        "import graphviz\n",
+        "graphviz.Source.from_file('synth_74.dot')"
+      ],
+      "execution_count": 18,
+      "outputs": [
+        {
+          "output_type": "execute_result",
+          "data": {
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+            "text/plain": [
+              "<graphviz.sources.Source at 0x7ee015275b20>"
+            ]
+          },
+          "metadata": {},
+          "execution_count": 18
+        }
+      ]
+    },
+    {
+      "cell_type": "markdown",
+      "metadata": {
+        "id": "xl9IjIbkj4LB"
+      },
+      "source": [
+        "## 🍫Treat #3 nextpnr and SVG floor map\n",
+        "\n",
+        "[nextpnr](https://github.com/YosysHQ/nextpnr) is a vendor neutral place and route tool that support multiple FPGA architectures.\n",
+        "\n",
+        "It takes [Yosys](https://yosyshq.net/yosys/) synthesis `JSON` output and attemps to place and wire the resulting cells on the target FPGA functional blocks.\n",
+        "\n",
+        "This notebook shows the floor map of an `ICE40UP5K` with a simple 8-bit adder that occupies 19 LUTs, and a [Quadratic Polynomial  function from Project F](https://projectf.io/posts/multiplication-fpga-dsps/#quartic-polynomial) that occupies 86% of the available LUTs."
+      ]
+    },
+    {
+      "cell_type": "markdown",
+      "metadata": {
+        "id": "XD98SUcGrVJk"
+      },
+      "source": [
+        "### Install packages\n",
+        "\n",
+        "Install packages from the `LiteX-Hub` and `SymbiFlow` channel."
+      ]
+    },
+    {
+      "cell_type": "code",
+      "metadata": {
+        "id": "xUPEpjPAj3iJ",
+        "colab": {
+          "base_uri": "https://localhost:8080/"
+        },
+        "outputId": "af24be0a-ebfb-4a4d-fe1e-7e8fec972408"
+      },
+      "source": [
+        "!curl -O https://repo.anaconda.com/miniconda/Miniconda3-py37_4.10.3-Linux-x86_64.sh\n",
+        "!bash Miniconda3-py37_4.10.3-Linux-x86_64.sh -b -f -p miniconda-pnr/\n",
+        "!miniconda-pnr/bin/conda install -y -c LiteX-Hub yosys nextpnr-ice40\n",
+        "!miniconda-pnr/bin/conda install --yes -c SymbiFlow verible"
+      ],
+      "execution_count": 19,
+      "outputs": [
+        {
+          "output_type": "stream",
+          "name": "stdout",
+          "text": [
+            "  % Total    % Received % Xferd  Average Speed   Time    Time     Time  Current\n",
+            "                                 Dload  Upload   Total   Spent    Left  Speed\n",
+            "100 84.9M  100 84.9M    0     0  92.6M      0 --:--:-- --:--:-- --:--:-- 92.5M\n",
+            "PREFIX=/content/miniconda-pnr\n",
+            "Unpacking payload ...\n",
+            "Collecting package metadata (current_repodata.json): - \b\b\\ \b\bdone\n",
+            "Solving environment: / \b\b- \b\b\\ \b\bdone\n",
+            "\n",
+            "## Package Plan ##\n",
+            "\n",
+            "  environment location: /content/miniconda-pnr\n",
+            "\n",
+            "  added / updated specs:\n",
+            "    - _libgcc_mutex==0.1=main\n",
+            "    - _openmp_mutex==4.5=1_gnu\n",
+            "    - brotlipy==0.7.0=py37h27cfd23_1003\n",
+            "    - ca-certificates==2021.7.5=h06a4308_1\n",
+            "    - certifi==2021.5.30=py37h06a4308_0\n",
+            "    - cffi==1.14.6=py37h400218f_0\n",
+            "    - chardet==4.0.0=py37h06a4308_1003\n",
+            "    - conda-package-handling==1.7.3=py37h27cfd23_1\n",
+            "    - conda==4.10.3=py37h06a4308_0\n",
+            "    - cryptography==3.4.7=py37hd23ed53_0\n",
+            "    - idna==2.10=pyhd3eb1b0_0\n",
+            "    - ld_impl_linux-64==2.35.1=h7274673_9\n",
+            "    - libffi==3.3=he6710b0_2\n",
+            "    - libgcc-ng==9.3.0=h5101ec6_17\n",
+            "    - libgomp==9.3.0=h5101ec6_17\n",
+            "    - libstdcxx-ng==9.3.0=hd4cf53a_17\n",
+            "    - ncurses==6.2=he6710b0_1\n",
+            "    - openssl==1.1.1k=h27cfd23_0\n",
+            "    - pip==21.1.3=py37h06a4308_0\n",
+            "    - pycosat==0.6.3=py37h27cfd23_0\n",
+            "    - pycparser==2.20=py_2\n",
+            "    - pyopenssl==20.0.1=pyhd3eb1b0_1\n",
+            "    - pysocks==1.7.1=py37_1\n",
+            "    - python==3.7.10=h12debd9_4\n",
+            "    - readline==8.1=h27cfd23_0\n",
+            "    - requests==2.25.1=pyhd3eb1b0_0\n",
+            "    - ruamel_yaml==0.15.100=py37h27cfd23_0\n",
+            "    - setuptools==52.0.0=py37h06a4308_0\n",
+            "    - six==1.16.0=pyhd3eb1b0_0\n",
+            "    - sqlite==3.36.0=hc218d9a_0\n",
+            "    - tk==8.6.10=hbc83047_0\n",
+            "    - tqdm==4.61.2=pyhd3eb1b0_1\n",
+            "    - urllib3==1.26.6=pyhd3eb1b0_1\n",
+            "    - wheel==0.36.2=pyhd3eb1b0_0\n",
+            "    - xz==5.2.5=h7b6447c_0\n",
+            "    - yaml==0.2.5=h7b6447c_0\n",
+            "    - zlib==1.2.11=h7b6447c_3\n",
+            "\n",
+            "\n",
+            "The following NEW packages will be INSTALLED:\n",
+            "\n",
+            "  _libgcc_mutex      pkgs/main/linux-64::_libgcc_mutex-0.1-main\n",
+            "  _openmp_mutex      pkgs/main/linux-64::_openmp_mutex-4.5-1_gnu\n",
+            "  brotlipy           pkgs/main/linux-64::brotlipy-0.7.0-py37h27cfd23_1003\n",
+            "  ca-certificates    pkgs/main/linux-64::ca-certificates-2021.7.5-h06a4308_1\n",
+            "  certifi            pkgs/main/linux-64::certifi-2021.5.30-py37h06a4308_0\n",
+            "  cffi               pkgs/main/linux-64::cffi-1.14.6-py37h400218f_0\n",
+            "  chardet            pkgs/main/linux-64::chardet-4.0.0-py37h06a4308_1003\n",
+            "  conda              pkgs/main/linux-64::conda-4.10.3-py37h06a4308_0\n",
+            "  conda-package-han~ pkgs/main/linux-64::conda-package-handling-1.7.3-py37h27cfd23_1\n",
+            "  cryptography       pkgs/main/linux-64::cryptography-3.4.7-py37hd23ed53_0\n",
+            "  idna               pkgs/main/noarch::idna-2.10-pyhd3eb1b0_0\n",
+            "  ld_impl_linux-64   pkgs/main/linux-64::ld_impl_linux-64-2.35.1-h7274673_9\n",
+            "  libffi             pkgs/main/linux-64::libffi-3.3-he6710b0_2\n",
+            "  libgcc-ng          pkgs/main/linux-64::libgcc-ng-9.3.0-h5101ec6_17\n",
+            "  libgomp            pkgs/main/linux-64::libgomp-9.3.0-h5101ec6_17\n",
+            "  libstdcxx-ng       pkgs/main/linux-64::libstdcxx-ng-9.3.0-hd4cf53a_17\n",
+            "  ncurses            pkgs/main/linux-64::ncurses-6.2-he6710b0_1\n",
+            "  openssl            pkgs/main/linux-64::openssl-1.1.1k-h27cfd23_0\n",
+            "  pip                pkgs/main/linux-64::pip-21.1.3-py37h06a4308_0\n",
+            "  pycosat            pkgs/main/linux-64::pycosat-0.6.3-py37h27cfd23_0\n",
+            "  pycparser          pkgs/main/noarch::pycparser-2.20-py_2\n",
+            "  pyopenssl          pkgs/main/noarch::pyopenssl-20.0.1-pyhd3eb1b0_1\n",
+            "  pysocks            pkgs/main/linux-64::pysocks-1.7.1-py37_1\n",
+            "  python             pkgs/main/linux-64::python-3.7.10-h12debd9_4\n",
+            "  readline           pkgs/main/linux-64::readline-8.1-h27cfd23_0\n",
+            "  requests           pkgs/main/noarch::requests-2.25.1-pyhd3eb1b0_0\n",
+            "  ruamel_yaml        pkgs/main/linux-64::ruamel_yaml-0.15.100-py37h27cfd23_0\n",
+            "  setuptools         pkgs/main/linux-64::setuptools-52.0.0-py37h06a4308_0\n",
+            "  six                pkgs/main/noarch::six-1.16.0-pyhd3eb1b0_0\n",
+            "  sqlite             pkgs/main/linux-64::sqlite-3.36.0-hc218d9a_0\n",
+            "  tk                 pkgs/main/linux-64::tk-8.6.10-hbc83047_0\n",
+            "  tqdm               pkgs/main/noarch::tqdm-4.61.2-pyhd3eb1b0_1\n",
+            "  urllib3            pkgs/main/noarch::urllib3-1.26.6-pyhd3eb1b0_1\n",
+            "  wheel              pkgs/main/noarch::wheel-0.36.2-pyhd3eb1b0_0\n",
+            "  xz                 pkgs/main/linux-64::xz-5.2.5-h7b6447c_0\n",
+            "  yaml               pkgs/main/linux-64::yaml-0.2.5-h7b6447c_0\n",
+            "  zlib               pkgs/main/linux-64::zlib-1.2.11-h7b6447c_3\n",
+            "\n",
+            "\n",
+            "Preparing transaction: / \b\b- \b\b\\ \b\b| \b\bdone\n",
+            "Executing transaction: - \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\bdone\n",
+            "installation finished.\n",
+            "WARNING:\n",
+            "    You currently have a PYTHONPATH environment variable set. This may cause\n",
+            "    unexpected behavior when running the Python interpreter in Miniconda3.\n",
+            "    For best results, please verify that your PYTHONPATH only points to\n",
+            "    directories of packages that are compatible with the Python interpreter\n",
+            "    in Miniconda3: /content/miniconda-pnr\n",
+            "Collecting package metadata (current_repodata.json): - \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\bdone\n",
+            "Solving environment: \\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\bfailed with initial frozen solve. Retrying with flexible solve.\n",
+            "Solving environment: | \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\bfailed with repodata from current_repodata.json, will retry with next repodata source.\n",
+            "Collecting package metadata (repodata.json): / \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\bdone\n",
+            "Solving environment: \\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\bdone\n",
+            "\n",
+            "## Package Plan ##\n",
+            "\n",
+            "  environment location: /content/miniconda-pnr\n",
+            "\n",
+            "  added / updated specs:\n",
+            "    - nextpnr-ice40\n",
+            "    - yosys\n",
+            "\n",
+            "\n",
+            "The following packages will be downloaded:\n",
+            "\n",
+            "    package                    |            build\n",
+            "    ---------------------------|-----------------\n",
+            "    bison-3.7.5                |       h2531618_1         708 KB\n",
+            "    bzip2-1.0.8                |       h7b6447c_0          78 KB\n",
+            "    ca-certificates-2025.12.2  |       h06a4308_0         125 KB\n",
+            "    certifi-2022.12.7          |   py37h06a4308_0         150 KB\n",
+            "    conda-23.1.0               |   py37h06a4308_0         937 KB\n",
+            "    flex-2.6.4                 |       ha10e3a4_1         308 KB\n",
+            "    flit-core-3.6.0            |     pyhd3eb1b0_0          42 KB\n",
+            "    icestorm-0.0_719_g792cef0  |  20220512_085338        13.9 MB  LiteX-Hub\n",
+            "    icu-58.2                   |       he6710b0_3        10.5 MB\n",
+            "    importlib-metadata-4.11.3  |   py37h06a4308_0          40 KB\n",
+            "    importlib_metadata-4.11.3  |       hd3eb1b0_0          12 KB\n",
+            "    libboost-1.73.0            |      h3ff78a5_11        13.9 MB\n",
+            "    lz4-c-1.9.3                |       h295c915_1         185 KB\n",
+            "    m4-1.4.18                  |       h4e445db_0         182 KB\n",
+            "    nextpnr-ice40-0.3_21_g41936fef|20220512_085338_py37        78.8 MB  LiteX-Hub\n",
+            "    openssl-1.1.1w             |       h7f8727e_0         3.7 MB\n",
+            "    pluggy-1.0.0               |   py37h06a4308_1          29 KB\n",
+            "    py-boost-1.73.0            |  py37ha9443f7_11         204 KB\n",
+            "    ruamel.yaml-0.16.12        |   py37h7b6447c_1         173 KB\n",
+            "    ruamel.yaml.clib-0.2.6     |   py37h7f8727e_0         133 KB\n",
+            "    toolz-0.12.0               |   py37h06a4308_0         104 KB\n",
+            "    typing_extensions-4.4.0    |   py37h06a4308_0          45 KB\n",
+            "    yosys-0.13_39_g958c3a46a   |20220202_022309_py37        11.0 MB  LiteX-Hub\n",
+            "    zipp-3.11.0                |   py37h06a4308_0          19 KB\n",
+            "    zstd-1.4.9                 |       haebb681_0         480 KB\n",
+            "    ------------------------------------------------------------\n",
+            "                                           Total:       135.8 MB\n",
+            "\n",
+            "The following NEW packages will be INSTALLED:\n",
+            "\n",
+            "  bison              pkgs/main/linux-64::bison-3.7.5-h2531618_1\n",
+            "  bzip2              pkgs/main/linux-64::bzip2-1.0.8-h7b6447c_0\n",
+            "  flex               pkgs/main/linux-64::flex-2.6.4-ha10e3a4_1\n",
+            "  flit-core          pkgs/main/noarch::flit-core-3.6.0-pyhd3eb1b0_0\n",
+            "  icestorm           LiteX-Hub/linux-64::icestorm-0.0_719_g792cef0-20220512_085338\n",
+            "  icu                pkgs/main/linux-64::icu-58.2-he6710b0_3\n",
+            "  importlib-metadata pkgs/main/linux-64::importlib-metadata-4.11.3-py37h06a4308_0\n",
+            "  importlib_metadata pkgs/main/noarch::importlib_metadata-4.11.3-hd3eb1b0_0\n",
+            "  libboost           pkgs/main/linux-64::libboost-1.73.0-h3ff78a5_11\n",
+            "  lz4-c              pkgs/main/linux-64::lz4-c-1.9.3-h295c915_1\n",
+            "  m4                 pkgs/main/linux-64::m4-1.4.18-h4e445db_0\n",
+            "  nextpnr-ice40      LiteX-Hub/linux-64::nextpnr-ice40-0.3_21_g41936fef-20220512_085338_py37\n",
+            "  pluggy             pkgs/main/linux-64::pluggy-1.0.0-py37h06a4308_1\n",
+            "  py-boost           pkgs/main/linux-64::py-boost-1.73.0-py37ha9443f7_11\n",
+            "  ruamel.yaml        pkgs/main/linux-64::ruamel.yaml-0.16.12-py37h7b6447c_1\n",
+            "  ruamel.yaml.clib   pkgs/main/linux-64::ruamel.yaml.clib-0.2.6-py37h7f8727e_0\n",
+            "  toolz              pkgs/main/linux-64::toolz-0.12.0-py37h06a4308_0\n",
+            "  typing_extensions  pkgs/main/linux-64::typing_extensions-4.4.0-py37h06a4308_0\n",
+            "  yosys              LiteX-Hub/linux-64::yosys-0.13_39_g958c3a46a-20220202_022309_py37\n",
+            "  zipp               pkgs/main/linux-64::zipp-3.11.0-py37h06a4308_0\n",
+            "  zstd               pkgs/main/linux-64::zstd-1.4.9-haebb681_0\n",
+            "\n",
+            "The following packages will be UPDATED:\n",
+            "\n",
+            "  ca-certificates                       2021.7.5-h06a4308_1 --> 2025.12.2-h06a4308_0\n",
+            "  certifi                          2021.5.30-py37h06a4308_0 --> 2022.12.7-py37h06a4308_0\n",
+            "  conda                               4.10.3-py37h06a4308_0 --> 23.1.0-py37h06a4308_0\n",
+            "  openssl                                 1.1.1k-h27cfd23_0 --> 1.1.1w-h7f8727e_0\n",
+            "\n",
+            "\n",
+            "\n",
+            "Downloading and Extracting Packages\n",
+            "bzip2-1.0.8          | 78 KB     | : 100% 1.0/1 [00:00<00:00,  2.90it/s]\n",
+            "bison-3.7.5          | 708 KB    | : 100% 1.0/1 [00:00<00:00,  2.50it/s]\n",
+            "nextpnr-ice40-0.3_21 | 78.8 MB   | : 100% 1.0/1 [00:21<00:00, 21.04s/it]\n",
+            "flex-2.6.4           | 308 KB    | : 100% 1.0/1 [00:00<00:00,  2.93it/s]\n",
+            "flit-core-3.6.0      | 42 KB     | : 100% 1.0/1 [00:00<00:00,  4.10it/s]\n",
+            "openssl-1.1.1w       | 3.7 MB    | : 100% 1.0/1 [00:00<00:00,  2.51it/s]\n",
+            "conda-23.1.0         | 937 KB    | : 100% 1.0/1 [00:00<00:00,  2.62it/s]\n",
+            "icestorm-0.0_719_g79 | 13.9 MB   | : 100% 1.0/1 [00:05<00:00,  5.33s/it]\n",
+            "zstd-1.4.9           | 480 KB    | : 100% 1.0/1 [00:00<00:00,  3.79it/s]\n",
+            "importlib_metadata-4 | 12 KB     | : 100% 1.0/1 [00:00<00:00,  3.98it/s]\n",
+            "m4-1.4.18            | 182 KB    | : 100% 1.0/1 [00:00<00:00,  3.76it/s]\n",
+            "yosys-0.13_39_g958c3 | 11.0 MB   | : 100% 1.0/1 [00:03<00:00,  3.67s/it]\n",
+            "typing_extensions-4. | 45 KB     | : 100% 1.0/1 [00:00<00:00,  3.36it/s]\n",
+            "pluggy-1.0.0         | 29 KB     | : 100% 1.0/1 [00:00<00:00,  4.29it/s]\n",
+            "zipp-3.11.0          | 19 KB     | : 100% 1.0/1 [00:00<00:00,  3.95it/s]\n",
+            "ruamel.yaml.clib-0.2 | 133 KB    | : 100% 1.0/1 [00:00<00:00,  4.29it/s]\n",
+            "certifi-2022.12.7    | 150 KB    | : 100% 1.0/1 [00:00<00:00,  4.23it/s]\n",
+            "py-boost-1.73.0      | 204 KB    | : 100% 1.0/1 [00:00<00:00,  2.74it/s]\n",
+            "lz4-c-1.9.3          | 185 KB    | : 100% 1.0/1 [00:00<00:00,  3.96it/s]\n",
+            "ca-certificates-2025 | 125 KB    | : 100% 1.0/1 [00:00<00:00,  4.39it/s]\n",
+            "toolz-0.12.0         | 104 KB    | : 100% 1.0/1 [00:00<00:00,  3.81it/s]               \n",
+            "libboost-1.73.0      | 13.9 MB   | : 100% 1.0/1 [00:02<00:00,  2.59s/it]\n",
+            "importlib-metadata-4 | 40 KB     | : 100% 1.0/1 [00:00<00:00,  4.07it/s]\n",
+            "ruamel.yaml-0.16.12  | 173 KB    | : 100% 1.0/1 [00:00<00:00,  4.19it/s]\n",
+            "icu-58.2             | 10.5 MB   | : 100% 1.0/1 [00:00<00:00,  1.31it/s]\n",
+            "Preparing transaction: - \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\bdone\n",
+            "Verifying transaction: - \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\bdone\n",
+            "Executing transaction: - \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\bdone\n",
+            "Collecting package metadata (current_repodata.json): - \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\bdone\n",
+            "Solving environment: \\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\b- \b\b\\ \b\b| \b\b/ \b\bdone\n",
+            "\n",
+            "\n",
+            "==> WARNING: A newer version of conda exists. <==\n",
+            "  current version: 23.1.0\n",
+            "  latest version: 26.1.1\n",
+            "\n",
+            "Please update conda by running\n",
+            "\n",
+            "    $ conda update -n base -c defaults conda\n",
+            "\n",
+            "Or to minimize the number of packages updated during conda update use\n",
+            "\n",
+            "     conda install conda=26.1.1\n",
+            "\n",
+            "\n",
+            "\n",
+            "## Package Plan ##\n",
+            "\n",
+            "  environment location: /content/miniconda-pnr\n",
+            "\n",
+            "  added / updated specs:\n",
+            "    - verible\n",
+            "\n",
+            "\n",
+            "The following packages will be downloaded:\n",
+            "\n",
+            "    package                    |            build\n",
+            "    ---------------------------|-----------------\n",
+            "    verible-0.0.836_0000_g1b1294c|  20201231_075710         4.2 MB  SymbiFlow\n",
+            "    ------------------------------------------------------------\n",
+            "                                           Total:         4.2 MB\n",
+            "\n",
+            "The following NEW packages will be INSTALLED:\n",
+            "\n",
+            "  verible            SymbiFlow/linux-64::verible-0.0.836_0000_g1b1294c-20201231_075710 \n",
+            "\n",
+            "\n",
+            "\n",
+            "Downloading and Extracting Packages\n",
+            "                                                                        \n",
+            "Preparing transaction: \\ \b\bdone\n",
+            "Verifying transaction: / \b\bdone\n",
+            "Executing transaction: \\ \b\bdone\n"
+          ]
+        }
+      ]
+    },
+    {
+      "cell_type": "markdown",
+      "metadata": {
+        "id": "KkBfgbGPrahW"
+      },
+      "source": [
+        "### Place and Route 8-bit adder"
+      ]
+    },
+    {
+      "cell_type": "code",
+      "metadata": {
+        "id": "jnaQPjwfEYXn"
+      },
+      "source": [
+        "%%bash -c 'source miniconda-pnr/bin/activate; cat > adder8.v; verible-verilog-lint adder8.v'\n",
+        "\n",
+        "module adder8(\n",
+        "  input wire [7:0] a,\n",
+        "  input wire [7:0] b,\n",
+        "  output wire [7:0] out\n",
+        ");\n",
+        "  assign out = a + b;\n",
+        "endmodule"
+      ],
+      "execution_count": 20,
+      "outputs": []
+    },
+    {
+      "cell_type": "code",
+      "metadata": {
+        "id": "Ba1B7KozC0Sd",
+        "colab": {
+          "base_uri": "https://localhost:8080/"
+        },
+        "outputId": "22a91724-9f74-46d6-9704-e3580f63a790"
+      },
+      "source": [
+        "!miniconda-pnr/bin/yosys -p 'synth_ice40 -top adder8 -json adder8.json' adder8.v\n",
+        "!miniconda-pnr/bin/nextpnr-ice40 --up5k --json adder8.json --asc adder8.asc --placed-svg adder8_placed.svg"
+      ],
+      "execution_count": 21,
+      "outputs": [
+        {
+          "output_type": "stream",
+          "name": "stdout",
+          "text": [
+            "\n",
+            " /----------------------------------------------------------------------------\\\n",
+            " |                                                                            |\n",
+            " |  yosys -- Yosys Open SYnthesis Suite                                       |\n",
+            " |                                                                            |\n",
+            " |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |\n",
+            " |                                                                            |\n",
+            " |  Permission to use, copy, modify, and/or distribute this software for any  |\n",
+            " |  purpose with or without fee is hereby granted, provided that the above    |\n",
+            " |  copyright notice and this permission notice appear in all copies.         |\n",
+            " |                                                                            |\n",
+            " |  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |\n",
+            " |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |\n",
+            " |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |\n",
+            " |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |\n",
+            " |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |\n",
+            " |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |\n",
+            " |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |\n",
+            " |                                                                            |\n",
+            " \\----------------------------------------------------------------------------/\n",
+            "\n",
+            " Yosys 0.13+37 (git sha1 958c3a46a, x86_64-conda_cos6-linux-gnu-gcc 1.24.0.133_b0863d8_dirty -fvisibility-inlines-hidden -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -fdebug-prefix-map=/home/runner/work/conda-eda/conda-eda/workdir/conda-env/conda-bld/yosys_1644188991550/work=/usr/local/src/conda/yosys-0.13_39_g958c3a46a -fdebug-prefix-map=/content/miniconda-pnr=/usr/local/src/conda-prefix -fPIC -Os -fno-merge-constants)\n",
+            "\n",
+            "\n",
+            "-- Parsing `adder8.v' using frontend ` -vlog2k' --\n",
+            "\n",
+            "1. Executing Verilog-2005 frontend: adder8.v\n",
+            "Parsing Verilog input from `adder8.v' to AST representation.\n",
+            "Storing AST representation for module `$abstract\\adder8'.\n",
+            "Successfully finished Verilog frontend.\n",
+            "\n",
+            "-- Running command `synth_ice40 -top adder8 -json adder8.json' --\n",
+            "\n",
+            "2. Executing SYNTH_ICE40 pass.\n",
+            "\n",
+            "2.1. Executing Verilog-2005 frontend: /content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v\n",
+            "Parsing Verilog input from `/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v' to AST representation.\n",
+            "Generating RTLIL representation for module `\\SB_IO'.\n",
+            "Generating RTLIL representation for module `\\SB_GB_IO'.\n",
+            "Generating RTLIL representation for module `\\SB_GB'.\n",
+            "Generating RTLIL representation for module `\\SB_LUT4'.\n",
+            "Generating RTLIL representation for module `\\SB_CARRY'.\n",
+            "Generating RTLIL representation for module `\\SB_DFF'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFE'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFSR'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFR'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFSS'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFS'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFESR'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFER'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFESS'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFES'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFN'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFNE'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFNSR'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFNR'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFNSS'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFNS'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFNESR'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFNER'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFNESS'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFNES'.\n",
+            "Generating RTLIL representation for module `\\SB_RAM40_4K'.\n",
+            "Generating RTLIL representation for module `\\SB_RAM40_4KNR'.\n",
+            "Generating RTLIL representation for module `\\SB_RAM40_4KNW'.\n",
+            "Generating RTLIL representation for module `\\SB_RAM40_4KNRNW'.\n",
+            "Generating RTLIL representation for module `\\ICESTORM_LC'.\n",
+            "Generating RTLIL representation for module `\\SB_PLL40_CORE'.\n",
+            "Generating RTLIL representation for module `\\SB_PLL40_PAD'.\n",
+            "Generating RTLIL representation for module `\\SB_PLL40_2_PAD'.\n",
+            "Generating RTLIL representation for module `\\SB_PLL40_2F_CORE'.\n",
+            "Generating RTLIL representation for module `\\SB_PLL40_2F_PAD'.\n",
+            "Generating RTLIL representation for module `\\SB_WARMBOOT'.\n",
+            "Generating RTLIL representation for module `\\SB_SPRAM256KA'.\n",
+            "Generating RTLIL representation for module `\\SB_HFOSC'.\n",
+            "Generating RTLIL representation for module `\\SB_LFOSC'.\n",
+            "Generating RTLIL representation for module `\\SB_RGBA_DRV'.\n",
+            "Generating RTLIL representation for module `\\SB_LED_DRV_CUR'.\n",
+            "Generating RTLIL representation for module `\\SB_RGB_DRV'.\n",
+            "Generating RTLIL representation for module `\\SB_I2C'.\n",
+            "Generating RTLIL representation for module `\\SB_SPI'.\n",
+            "Generating RTLIL representation for module `\\SB_LEDDA_IP'.\n",
+            "Generating RTLIL representation for module `\\SB_FILTER_50NS'.\n",
+            "Generating RTLIL representation for module `\\SB_IO_I3C'.\n",
+            "Generating RTLIL representation for module `\\SB_IO_OD'.\n",
+            "Generating RTLIL representation for module `\\SB_MAC16'.\n",
+            "Generating RTLIL representation for module `\\ICESTORM_RAM'.\n",
+            "Successfully finished Verilog frontend.\n",
+            "\n",
+            "2.2. Executing HIERARCHY pass (managing design hierarchy).\n",
+            "\n",
+            "2.3. Executing AST frontend in derive mode using pre-parsed AST for module `\\adder8'.\n",
+            "Generating RTLIL representation for module `\\adder8'.\n",
+            "\n",
+            "2.3.1. Analyzing design hierarchy..\n",
+            "Top module:  \\adder8\n",
+            "\n",
+            "2.3.2. Analyzing design hierarchy..\n",
+            "Top module:  \\adder8\n",
+            "Removing unused module `$abstract\\adder8'.\n",
+            "Removed 1 unused modules.\n",
+            "\n",
+            "2.4. Executing PROC pass (convert processes to netlists).\n",
+            "\n",
+            "2.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).\n",
+            "Cleaned up 0 empty switches.\n",
+            "\n",
+            "2.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1386$241 in module SB_DFFNES.\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1328$234 in module SB_DFFNESS.\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1251$230 in module SB_DFFNER.\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1193$223 in module SB_DFFNESR.\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1122$220 in module SB_DFFNS.\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1072$217 in module SB_DFFNSS.\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1001$214 in module SB_DFFNR.\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:951$211 in module SB_DFFNSR.\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:789$203 in module SB_DFFES.\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:731$196 in module SB_DFFESS.\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:654$192 in module SB_DFFER.\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:596$185 in module SB_DFFESR.\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:525$182 in module SB_DFFS.\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:475$179 in module SB_DFFSS.\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:404$176 in module SB_DFFR.\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:354$173 in module SB_DFFSR.\n",
+            "Removed a total of 0 dead cases.\n",
+            "\n",
+            "2.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).\n",
+            "Removed 8 redundant assignments.\n",
+            "Promoted 22 assignments to connections.\n",
+            "\n",
+            "2.4.4. Executing PROC_INIT pass (extract init attributes).\n",
+            "Found init rule in `\\SB_DFFNES.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$244'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFNESS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$240'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFNER.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$233'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFNESR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$229'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFNS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$222'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFNSS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$219'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFNR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$216'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFNSR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$213'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFNE.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$210'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFN.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$208'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFES.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$206'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFESS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$202'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFER.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$195'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFESR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$191'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$184'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFSS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$181'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$178'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFSR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$175'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFE.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$172'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFF.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$170'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "\n",
+            "2.4.5. Executing PROC_ARST pass (detect async resets in processes).\n",
+            "Found async reset \\S in `\\SB_DFFNES.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1386$241'.\n",
+            "Found async reset \\R in `\\SB_DFFNER.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1251$230'.\n",
+            "Found async reset \\S in `\\SB_DFFNS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1122$220'.\n",
+            "Found async reset \\R in `\\SB_DFFNR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1001$214'.\n",
+            "Found async reset \\S in `\\SB_DFFES.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:789$203'.\n",
+            "Found async reset \\R in `\\SB_DFFER.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:654$192'.\n",
+            "Found async reset \\S in `\\SB_DFFS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:525$182'.\n",
+            "Found async reset \\R in `\\SB_DFFR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:404$176'.\n",
+            "\n",
+            "2.4.6. Executing PROC_MUX pass (convert decision trees to multiplexers).\n",
+            "Creating decoders for process `\\SB_DFFNES.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$244'.\n",
+            "Creating decoders for process `\\SB_DFFNES.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1386$241'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFNESS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$240'.\n",
+            "Creating decoders for process `\\SB_DFFNESS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1328$234'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFNER.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$233'.\n",
+            "Creating decoders for process `\\SB_DFFNER.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1251$230'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFNESR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$229'.\n",
+            "Creating decoders for process `\\SB_DFFNESR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1193$223'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFNS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$222'.\n",
+            "Creating decoders for process `\\SB_DFFNS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1122$220'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFNSS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$219'.\n",
+            "Creating decoders for process `\\SB_DFFNSS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1072$217'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFNR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$216'.\n",
+            "Creating decoders for process `\\SB_DFFNR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1001$214'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFNSR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$213'.\n",
+            "Creating decoders for process `\\SB_DFFNSR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:951$211'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFNE.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$210'.\n",
+            "Creating decoders for process `\\SB_DFFNE.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:906$209'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFN.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$208'.\n",
+            "Creating decoders for process `\\SB_DFFN.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:868$207'.\n",
+            "Creating decoders for process `\\SB_DFFES.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$206'.\n",
+            "Creating decoders for process `\\SB_DFFES.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:789$203'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFESS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$202'.\n",
+            "Creating decoders for process `\\SB_DFFESS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:731$196'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFER.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$195'.\n",
+            "Creating decoders for process `\\SB_DFFER.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:654$192'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFESR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$191'.\n",
+            "Creating decoders for process `\\SB_DFFESR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:596$185'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$184'.\n",
+            "Creating decoders for process `\\SB_DFFS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:525$182'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFSS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$181'.\n",
+            "Creating decoders for process `\\SB_DFFSS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:475$179'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$178'.\n",
+            "Creating decoders for process `\\SB_DFFR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:404$176'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFSR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$175'.\n",
+            "Creating decoders for process `\\SB_DFFSR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:354$173'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFE.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$172'.\n",
+            "Creating decoders for process `\\SB_DFFE.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:309$171'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFF.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$170'.\n",
+            "Creating decoders for process `\\SB_DFF.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:271$169'.\n",
+            "\n",
+            "2.4.7. Executing PROC_DLATCH pass (convert process syncs to latches).\n",
+            "\n",
+            "2.4.8. Executing PROC_DFF pass (convert process syncs to FFs).\n",
+            "Creating register for signal `\\SB_DFFNES.\\Q' using process `\\SB_DFFNES.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1386$241'.\n",
+            "  created $adff cell `$procdff$426' with negative edge clock and positive level reset.\n",
+            "Creating register for signal `\\SB_DFFNESS.\\Q' using process `\\SB_DFFNESS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1328$234'.\n",
+            "  created $dff cell `$procdff$427' with negative edge clock.\n",
+            "Creating register for signal `\\SB_DFFNER.\\Q' using process `\\SB_DFFNER.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1251$230'.\n",
+            "  created $adff cell `$procdff$428' with negative edge clock and positive level reset.\n",
+            "Creating register for signal `\\SB_DFFNESR.\\Q' using process `\\SB_DFFNESR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1193$223'.\n",
+            "  created $dff cell `$procdff$429' with negative edge clock.\n",
+            "Creating register for signal `\\SB_DFFNS.\\Q' using process `\\SB_DFFNS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1122$220'.\n",
+            "  created $adff cell `$procdff$430' with negative edge clock and positive level reset.\n",
+            "Creating register for signal `\\SB_DFFNSS.\\Q' using process `\\SB_DFFNSS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1072$217'.\n",
+            "  created $dff cell `$procdff$431' with negative edge clock.\n",
+            "Creating register for signal `\\SB_DFFNR.\\Q' using process `\\SB_DFFNR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1001$214'.\n",
+            "  created $adff cell `$procdff$432' with negative edge clock and positive level reset.\n",
+            "Creating register for signal `\\SB_DFFNSR.\\Q' using process `\\SB_DFFNSR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:951$211'.\n",
+            "  created $dff cell `$procdff$433' with negative edge clock.\n",
+            "Creating register for signal `\\SB_DFFNE.\\Q' using process `\\SB_DFFNE.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:906$209'.\n",
+            "  created $dff cell `$procdff$434' with negative edge clock.\n",
+            "Creating register for signal `\\SB_DFFN.\\Q' using process `\\SB_DFFN.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:868$207'.\n",
+            "  created $dff cell `$procdff$435' with negative edge clock.\n",
+            "Creating register for signal `\\SB_DFFES.\\Q' using process `\\SB_DFFES.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:789$203'.\n",
+            "  created $adff cell `$procdff$436' with positive edge clock and positive level reset.\n",
+            "Creating register for signal `\\SB_DFFESS.\\Q' using process `\\SB_DFFESS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:731$196'.\n",
+            "  created $dff cell `$procdff$437' with positive edge clock.\n",
+            "Creating register for signal `\\SB_DFFER.\\Q' using process `\\SB_DFFER.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:654$192'.\n",
+            "  created $adff cell `$procdff$438' with positive edge clock and positive level reset.\n",
+            "Creating register for signal `\\SB_DFFESR.\\Q' using process `\\SB_DFFESR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:596$185'.\n",
+            "  created $dff cell `$procdff$439' with positive edge clock.\n",
+            "Creating register for signal `\\SB_DFFS.\\Q' using process `\\SB_DFFS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:525$182'.\n",
+            "  created $adff cell `$procdff$440' with positive edge clock and positive level reset.\n",
+            "Creating register for signal `\\SB_DFFSS.\\Q' using process `\\SB_DFFSS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:475$179'.\n",
+            "  created $dff cell `$procdff$441' with positive edge clock.\n",
+            "Creating register for signal `\\SB_DFFR.\\Q' using process `\\SB_DFFR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:404$176'.\n",
+            "  created $adff cell `$procdff$442' with positive edge clock and positive level reset.\n",
+            "Creating register for signal `\\SB_DFFSR.\\Q' using process `\\SB_DFFSR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:354$173'.\n",
+            "  created $dff cell `$procdff$443' with positive edge clock.\n",
+            "Creating register for signal `\\SB_DFFE.\\Q' using process `\\SB_DFFE.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:309$171'.\n",
+            "  created $dff cell `$procdff$444' with positive edge clock.\n",
+            "Creating register for signal `\\SB_DFF.\\Q' using process `\\SB_DFF.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:271$169'.\n",
+            "  created $dff cell `$procdff$445' with positive edge clock.\n",
+            "\n",
+            "2.4.9. Executing PROC_MEMWR pass (convert process memory writes to cells).\n",
+            "\n",
+            "2.4.10. Executing PROC_CLEAN pass (remove empty switches from decision trees).\n",
+            "Removing empty process `SB_DFFNES.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$244'.\n",
+            "Found and cleaned up 1 empty switch in `\\SB_DFFNES.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1386$241'.\n",
+            "Removing empty process `SB_DFFNES.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1386$241'.\n",
+            "Removing empty process `SB_DFFNESS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$240'.\n",
+            "Found and cleaned up 2 empty switches in `\\SB_DFFNESS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1328$234'.\n",
+            "Removing empty process `SB_DFFNESS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1328$234'.\n",
+            "Removing empty process `SB_DFFNER.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$233'.\n",
+            "Found and cleaned up 1 empty switch in `\\SB_DFFNER.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1251$230'.\n",
+            "Removing empty process `SB_DFFNER.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1251$230'.\n",
+            "Removing empty process `SB_DFFNESR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$229'.\n",
+            "Found and cleaned up 2 empty switches in `\\SB_DFFNESR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1193$223'.\n",
+            "Removing empty process `SB_DFFNESR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1193$223'.\n",
+            "Removing empty process `SB_DFFNS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$222'.\n",
+            "Removing empty process `SB_DFFNS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1122$220'.\n",
+            "Removing empty process `SB_DFFNSS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$219'.\n",
+            "Found and cleaned up 1 empty switch in `\\SB_DFFNSS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1072$217'.\n",
+            "Removing empty process `SB_DFFNSS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1072$217'.\n",
+            "Removing empty process `SB_DFFNR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$216'.\n",
+            "Removing empty process `SB_DFFNR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1001$214'.\n",
+            "Removing empty process `SB_DFFNSR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$213'.\n",
+            "Found and cleaned up 1 empty switch in `\\SB_DFFNSR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:951$211'.\n",
+            "Removing empty process `SB_DFFNSR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:951$211'.\n",
+            "Removing empty process `SB_DFFNE.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$210'.\n",
+            "Found and cleaned up 1 empty switch in `\\SB_DFFNE.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:906$209'.\n",
+            "Removing empty process `SB_DFFNE.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:906$209'.\n",
+            "Removing empty process `SB_DFFN.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$208'.\n",
+            "Removing empty process `SB_DFFN.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:868$207'.\n",
+            "Removing empty process `SB_DFFES.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$206'.\n",
+            "Found and cleaned up 1 empty switch in `\\SB_DFFES.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:789$203'.\n",
+            "Removing empty process `SB_DFFES.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:789$203'.\n",
+            "Removing empty process `SB_DFFESS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$202'.\n",
+            "Found and cleaned up 2 empty switches in `\\SB_DFFESS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:731$196'.\n",
+            "Removing empty process `SB_DFFESS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:731$196'.\n",
+            "Removing empty process `SB_DFFER.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$195'.\n",
+            "Found and cleaned up 1 empty switch in `\\SB_DFFER.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:654$192'.\n",
+            "Removing empty process `SB_DFFER.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:654$192'.\n",
+            "Removing empty process `SB_DFFESR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$191'.\n",
+            "Found and cleaned up 2 empty switches in `\\SB_DFFESR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:596$185'.\n",
+            "Removing empty process `SB_DFFESR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:596$185'.\n",
+            "Removing empty process `SB_DFFS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$184'.\n",
+            "Removing empty process `SB_DFFS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:525$182'.\n",
+            "Removing empty process `SB_DFFSS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$181'.\n",
+            "Found and cleaned up 1 empty switch in `\\SB_DFFSS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:475$179'.\n",
+            "Removing empty process `SB_DFFSS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:475$179'.\n",
+            "Removing empty process `SB_DFFR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$178'.\n",
+            "Removing empty process `SB_DFFR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:404$176'.\n",
+            "Removing empty process `SB_DFFSR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$175'.\n",
+            "Found and cleaned up 1 empty switch in `\\SB_DFFSR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:354$173'.\n",
+            "Removing empty process `SB_DFFSR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:354$173'.\n",
+            "Removing empty process `SB_DFFE.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$172'.\n",
+            "Found and cleaned up 1 empty switch in `\\SB_DFFE.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:309$171'.\n",
+            "Removing empty process `SB_DFFE.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:309$171'.\n",
+            "Removing empty process `SB_DFF.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$170'.\n",
+            "Removing empty process `SB_DFF.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:271$169'.\n",
+            "Cleaned up 18 empty switches.\n",
+            "\n",
+            "2.4.11. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module adder8.\n",
+            "\n",
+            "2.5. Executing FLATTEN pass (flatten design).\n",
+            "\n",
+            "2.6. Executing TRIBUF pass.\n",
+            "\n",
+            "2.7. Executing DEMINOUT pass (demote inout ports to input or output).\n",
+            "\n",
+            "2.8. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module adder8.\n",
+            "\n",
+            "2.9. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\adder8..\n",
+            "Removed 0 unused cells and 1 unused wires.\n",
+            "\n",
+            "2.10. Executing CHECK pass (checking for obvious problems).\n",
+            "Checking module adder8...\n",
+            "Found and reported 0 problems.\n",
+            "\n",
+            "2.11. Executing OPT pass (performing simple optimizations).\n",
+            "\n",
+            "2.11.1. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module adder8.\n",
+            "\n",
+            "2.11.2. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\adder8'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "2.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n",
+            "Running muxtree optimizer on module \\adder8..\n",
+            "  Creating internal representation of mux trees.\n",
+            "  No muxes found in this module.\n",
+            "Removed 0 multiplexer ports.\n",
+            "\n",
+            "2.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n",
+            "  Optimizing cells in module \\adder8.\n",
+            "Performed a total of 0 changes.\n",
+            "\n",
+            "2.11.5. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\adder8'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "2.11.6. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "2.11.7. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\adder8..\n",
+            "\n",
+            "2.11.8. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module adder8.\n",
+            "\n",
+            "2.11.9. Finished OPT passes. (There is nothing left to do.)\n",
+            "\n",
+            "2.12. Executing FSM pass (extract and optimize FSM).\n",
+            "\n",
+            "2.12.1. Executing FSM_DETECT pass (finding FSMs in design).\n",
+            "\n",
+            "2.12.2. Executing FSM_EXTRACT pass (extracting FSM from design).\n",
+            "\n",
+            "2.12.3. Executing FSM_OPT pass (simple optimizations of FSMs).\n",
+            "\n",
+            "2.12.4. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\adder8..\n",
+            "\n",
+            "2.12.5. Executing FSM_OPT pass (simple optimizations of FSMs).\n",
+            "\n",
+            "2.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).\n",
+            "\n",
+            "2.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells).\n",
+            "\n",
+            "2.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic).\n",
+            "\n",
+            "2.13. Executing OPT pass (performing simple optimizations).\n",
+            "\n",
+            "2.13.1. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module adder8.\n",
+            "\n",
+            "2.13.2. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\adder8'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "2.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n",
+            "Running muxtree optimizer on module \\adder8..\n",
+            "  Creating internal representation of mux trees.\n",
+            "  No muxes found in this module.\n",
+            "Removed 0 multiplexer ports.\n",
+            "\n",
+            "2.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n",
+            "  Optimizing cells in module \\adder8.\n",
+            "Performed a total of 0 changes.\n",
+            "\n",
+            "2.13.5. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\adder8'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "2.13.6. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "2.13.7. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\adder8..\n",
+            "\n",
+            "2.13.8. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module adder8.\n",
+            "\n",
+            "2.13.9. Finished OPT passes. (There is nothing left to do.)\n",
+            "\n",
+            "2.14. Executing WREDUCE pass (reducing word size of cells).\n",
+            "\n",
+            "2.15. Executing PEEPOPT pass (run peephole optimizers).\n",
+            "\n",
+            "2.16. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\adder8..\n",
+            "\n",
+            "2.17. Executing SHARE pass (SAT-based resource sharing).\n",
+            "\n",
+            "2.18. Executing TECHMAP pass (map to technology primitives).\n",
+            "\n",
+            "2.18.1. Executing Verilog-2005 frontend: /content/miniconda-pnr/bin/../share/yosys/cmp2lut.v\n",
+            "Parsing Verilog input from `/content/miniconda-pnr/bin/../share/yosys/cmp2lut.v' to AST representation.\n",
+            "Generating RTLIL representation for module `\\_90_lut_cmp_'.\n",
+            "Successfully finished Verilog frontend.\n",
+            "\n",
+            "2.18.2. Continuing TECHMAP pass.\n",
+            "No more expansions possible.\n",
+            "\n",
+            "2.19. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module adder8.\n",
+            "\n",
+            "2.20. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\adder8..\n",
+            "\n",
+            "2.21. Executing ALUMACC pass (create $alu and $macc cells).\n",
+            "Extracting $alu and $macc cells in module adder8:\n",
+            "  creating $macc model for $add$adder8.v:7$381 ($add).\n",
+            "  creating $alu model for $macc $add$adder8.v:7$381.\n",
+            "  creating $alu cell for $add$adder8.v:7$381: $auto$alumacc.cc:485:replace_alu$447\n",
+            "  created 1 $alu and 0 $macc cells.\n",
+            "\n",
+            "2.22. Executing OPT pass (performing simple optimizations).\n",
+            "\n",
+            "2.22.1. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module adder8.\n",
+            "\n",
+            "2.22.2. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\adder8'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "2.22.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n",
+            "Running muxtree optimizer on module \\adder8..\n",
+            "  Creating internal representation of mux trees.\n",
+            "  No muxes found in this module.\n",
+            "Removed 0 multiplexer ports.\n",
+            "\n",
+            "2.22.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n",
+            "  Optimizing cells in module \\adder8.\n",
+            "Performed a total of 0 changes.\n",
+            "\n",
+            "2.22.5. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\adder8'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "2.22.6. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "2.22.7. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\adder8..\n",
+            "\n",
+            "2.22.8. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module adder8.\n",
+            "\n",
+            "2.22.9. Finished OPT passes. (There is nothing left to do.)\n",
+            "\n",
+            "2.23. Executing MEMORY pass.\n",
+            "\n",
+            "2.23.1. Executing OPT_MEM pass (optimize memories).\n",
+            "Performed a total of 0 transformations.\n",
+            "\n",
+            "2.23.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).\n",
+            "Performed a total of 0 transformations.\n",
+            "\n",
+            "2.23.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).\n",
+            "\n",
+            "2.23.4. Executing MEMORY_DFF pass (merging $dff cells to $memrd).\n",
+            "\n",
+            "2.23.5. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\adder8..\n",
+            "\n",
+            "2.23.6. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).\n",
+            "\n",
+            "2.23.7. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).\n",
+            "Performed a total of 0 transformations.\n",
+            "\n",
+            "2.23.8. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\adder8..\n",
+            "\n",
+            "2.23.9. Executing MEMORY_COLLECT pass (generating $mem cells).\n",
+            "\n",
+            "2.24. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\adder8..\n",
+            "\n",
+            "2.25. Executing MEMORY_BRAM pass (mapping $mem cells to block memories).\n",
+            "\n",
+            "2.26. Executing TECHMAP pass (map to technology primitives).\n",
+            "\n",
+            "2.26.1. Executing Verilog-2005 frontend: /content/miniconda-pnr/bin/../share/yosys/ice40/brams_map.v\n",
+            "Parsing Verilog input from `/content/miniconda-pnr/bin/../share/yosys/ice40/brams_map.v' to AST representation.\n",
+            "Generating RTLIL representation for module `\\$__ICE40_RAM4K'.\n",
+            "Generating RTLIL representation for module `\\$__ICE40_RAM4K_M0'.\n",
+            "Generating RTLIL representation for module `\\$__ICE40_RAM4K_M123'.\n",
+            "Successfully finished Verilog frontend.\n",
+            "\n",
+            "2.26.2. Continuing TECHMAP pass.\n",
+            "No more expansions possible.\n",
+            "\n",
+            "2.27. Executing ICE40_BRAMINIT pass.\n",
+            "\n",
+            "2.28. Executing OPT pass (performing simple optimizations).\n",
+            "\n",
+            "2.28.1. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module adder8.\n",
+            "\n",
+            "2.28.2. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\adder8'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "2.28.3. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "2.28.4. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\adder8..\n",
+            "\n",
+            "2.28.5. Finished fast OPT passes.\n",
+            "\n",
+            "2.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).\n",
+            "\n",
+            "2.30. Executing OPT pass (performing simple optimizations).\n",
+            "\n",
+            "2.30.1. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module adder8.\n",
+            "\n",
+            "2.30.2. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\adder8'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "2.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n",
+            "Running muxtree optimizer on module \\adder8..\n",
+            "  Creating internal representation of mux trees.\n",
+            "  No muxes found in this module.\n",
+            "Removed 0 multiplexer ports.\n",
+            "\n",
+            "2.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n",
+            "  Optimizing cells in module \\adder8.\n",
+            "Performed a total of 0 changes.\n",
+            "\n",
+            "2.30.5. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\adder8'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "2.30.6. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "2.30.7. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\adder8..\n",
+            "\n",
+            "2.30.8. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module adder8.\n",
+            "\n",
+            "2.30.9. Finished OPT passes. (There is nothing left to do.)\n",
+            "\n",
+            "2.31. Executing ICE40_WRAPCARRY pass (wrap carries).\n",
+            "\n",
+            "2.32. Executing TECHMAP pass (map to technology primitives).\n",
+            "\n",
+            "2.32.1. Executing Verilog-2005 frontend: /content/miniconda-pnr/bin/../share/yosys/techmap.v\n",
+            "Parsing Verilog input from `/content/miniconda-pnr/bin/../share/yosys/techmap.v' to AST representation.\n",
+            "Generating RTLIL representation for module `\\_90_simplemap_bool_ops'.\n",
+            "Generating RTLIL representation for module `\\_90_simplemap_reduce_ops'.\n",
+            "Generating RTLIL representation for module `\\_90_simplemap_logic_ops'.\n",
+            "Generating RTLIL representation for module `\\_90_simplemap_compare_ops'.\n",
+            "Generating RTLIL representation for module `\\_90_simplemap_various'.\n",
+            "Generating RTLIL representation for module `\\_90_simplemap_registers'.\n",
+            "Generating RTLIL representation for module `\\_90_shift_ops_shr_shl_sshl_sshr'.\n",
+            "Generating RTLIL representation for module `\\_90_shift_shiftx'.\n",
+            "Generating RTLIL representation for module `\\_90_fa'.\n",
+            "Generating RTLIL representation for module `\\_90_lcu'.\n",
+            "Generating RTLIL representation for module `\\_90_alu'.\n",
+            "Generating RTLIL representation for module `\\_90_macc'.\n",
+            "Generating RTLIL representation for module `\\_90_alumacc'.\n",
+            "Generating RTLIL representation for module `\\$__div_mod_u'.\n",
+            "Generating RTLIL representation for module `\\$__div_mod_trunc'.\n",
+            "Generating RTLIL representation for module `\\_90_div'.\n",
+            "Generating RTLIL representation for module `\\_90_mod'.\n",
+            "Generating RTLIL representation for module `\\$__div_mod_floor'.\n",
+            "Generating RTLIL representation for module `\\_90_divfloor'.\n",
+            "Generating RTLIL representation for module `\\_90_modfloor'.\n",
+            "Generating RTLIL representation for module `\\_90_pow'.\n",
+            "Generating RTLIL representation for module `\\_90_pmux'.\n",
+            "Generating RTLIL representation for module `\\_90_demux'.\n",
+            "Generating RTLIL representation for module `\\_90_lut'.\n",
+            "Successfully finished Verilog frontend.\n",
+            "\n",
+            "2.32.2. Executing Verilog-2005 frontend: /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v\n",
+            "Parsing Verilog input from `/content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v' to AST representation.\n",
+            "Generating RTLIL representation for module `\\_80_ice40_alu'.\n",
+            "Successfully finished Verilog frontend.\n",
+            "\n",
+            "2.32.3. Continuing TECHMAP pass.\n",
+            "Using template $paramod$a1bc51c02ce12ac21eb18988e83292af48ed7d72\\_80_ice40_alu for cells of type $alu.\n",
+            "Using extmapper simplemap for cells of type $xor.\n",
+            "Using extmapper simplemap for cells of type $mux.\n",
+            "Using extmapper simplemap for cells of type $not.\n",
+            "Using extmapper simplemap for cells of type $pos.\n",
+            "No more expansions possible.\n",
+            "\n",
+            "2.33. Executing OPT pass (performing simple optimizations).\n",
+            "\n",
+            "2.33.1. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module adder8.\n",
+            "\n",
+            "2.33.2. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\adder8'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "2.33.3. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "2.33.4. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\adder8..\n",
+            "Removed 16 unused cells and 16 unused wires.\n",
+            "\n",
+            "2.33.5. Finished fast OPT passes.\n",
+            "\n",
+            "2.34. Executing ICE40_OPT pass (performing simple optimizations).\n",
+            "\n",
+            "2.34.1. Running ICE40 specific optimizations.\n",
+            "\n",
+            "2.34.2. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module adder8.\n",
+            "\n",
+            "2.34.3. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\adder8'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "2.34.4. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "2.34.5. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\adder8..\n",
+            "\n",
+            "2.34.6. Finished OPT passes. (There is nothing left to do.)\n",
+            "\n",
+            "2.35. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).\n",
+            "\n",
+            "2.36. Executing TECHMAP pass (map to technology primitives).\n",
+            "\n",
+            "2.36.1. Executing Verilog-2005 frontend: /content/miniconda-pnr/bin/../share/yosys/ice40/ff_map.v\n",
+            "Parsing Verilog input from `/content/miniconda-pnr/bin/../share/yosys/ice40/ff_map.v' to AST representation.\n",
+            "Generating RTLIL representation for module `\\$_DFF_N_'.\n",
+            "Generating RTLIL representation for module `\\$_DFF_P_'.\n",
+            "Generating RTLIL representation for module `\\$_DFFE_NP_'.\n",
+            "Generating RTLIL representation for module `\\$_DFFE_PP_'.\n",
+            "Generating RTLIL representation for module `\\$_DFF_NP0_'.\n",
+            "Generating RTLIL representation for module `\\$_DFF_NP1_'.\n",
+            "Generating RTLIL representation for module `\\$_DFF_PP0_'.\n",
+            "Generating RTLIL representation for module `\\$_DFF_PP1_'.\n",
+            "Generating RTLIL representation for module `\\$_DFFE_NP0P_'.\n",
+            "Generating RTLIL representation for module `\\$_DFFE_NP1P_'.\n",
+            "Generating RTLIL representation for module `\\$_DFFE_PP0P_'.\n",
+            "Generating RTLIL representation for module `\\$_DFFE_PP1P_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFF_NP0_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFF_NP1_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFF_PP0_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFF_PP1_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFFCE_NP0P_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFFCE_NP1P_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFFCE_PP0P_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFFCE_PP1P_'.\n",
+            "Successfully finished Verilog frontend.\n",
+            "\n",
+            "2.36.2. Continuing TECHMAP pass.\n",
+            "No more expansions possible.\n",
+            "\n",
+            "2.37. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module adder8.\n",
+            "\n",
+            "2.38. Executing SIMPLEMAP pass (map simple cells to gate primitives).\n",
+            "\n",
+            "2.39. Executing ICE40_OPT pass (performing simple optimizations).\n",
+            "\n",
+            "2.39.1. Running ICE40 specific optimizations.\n",
+            "\n",
+            "2.39.2. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module adder8.\n",
+            "\n",
+            "2.39.3. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\adder8'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "2.39.4. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "2.39.5. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\adder8..\n",
+            "\n",
+            "2.39.6. Finished OPT passes. (There is nothing left to do.)\n",
+            "\n",
+            "2.40. Executing TECHMAP pass (map to technology primitives).\n",
+            "\n",
+            "2.40.1. Executing Verilog-2005 frontend: /content/miniconda-pnr/bin/../share/yosys/ice40/latches_map.v\n",
+            "Parsing Verilog input from `/content/miniconda-pnr/bin/../share/yosys/ice40/latches_map.v' to AST representation.\n",
+            "Generating RTLIL representation for module `\\$_DLATCH_N_'.\n",
+            "Generating RTLIL representation for module `\\$_DLATCH_P_'.\n",
+            "Successfully finished Verilog frontend.\n",
+            "\n",
+            "2.40.2. Continuing TECHMAP pass.\n",
+            "No more expansions possible.\n",
+            "\n",
+            "2.41. Executing ABC pass (technology mapping using ABC).\n",
+            "\n",
+            "2.41.1. Extracting gate netlist of module `\\adder8' to `<abc-temp-dir>/input.blif'..\n",
+            "Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs.\n",
+            "Don't call ABC as there is nothing to map.\n",
+            "Removing temp directory.\n",
+            "\n",
+            "2.42. Executing ICE40_WRAPCARRY pass (wrap carries).\n",
+            "\n",
+            "2.43. Executing TECHMAP pass (map to technology primitives).\n",
+            "\n",
+            "2.43.1. Executing Verilog-2005 frontend: /content/miniconda-pnr/bin/../share/yosys/ice40/ff_map.v\n",
+            "Parsing Verilog input from `/content/miniconda-pnr/bin/../share/yosys/ice40/ff_map.v' to AST representation.\n",
+            "Generating RTLIL representation for module `\\$_DFF_N_'.\n",
+            "Generating RTLIL representation for module `\\$_DFF_P_'.\n",
+            "Generating RTLIL representation for module `\\$_DFFE_NP_'.\n",
+            "Generating RTLIL representation for module `\\$_DFFE_PP_'.\n",
+            "Generating RTLIL representation for module `\\$_DFF_NP0_'.\n",
+            "Generating RTLIL representation for module `\\$_DFF_NP1_'.\n",
+            "Generating RTLIL representation for module `\\$_DFF_PP0_'.\n",
+            "Generating RTLIL representation for module `\\$_DFF_PP1_'.\n",
+            "Generating RTLIL representation for module `\\$_DFFE_NP0P_'.\n",
+            "Generating RTLIL representation for module `\\$_DFFE_NP1P_'.\n",
+            "Generating RTLIL representation for module `\\$_DFFE_PP0P_'.\n",
+            "Generating RTLIL representation for module `\\$_DFFE_PP1P_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFF_NP0_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFF_NP1_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFF_PP0_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFF_PP1_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFFCE_NP0P_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFFCE_NP1P_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFFCE_PP0P_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFFCE_PP1P_'.\n",
+            "Successfully finished Verilog frontend.\n",
+            "\n",
+            "2.43.2. Continuing TECHMAP pass.\n",
+            "No more expansions possible.\n",
+            "Removed 1 unused cells and 1 unused wires.\n",
+            "\n",
+            "2.44. Executing OPT_LUT pass (optimize LUTs).\n",
+            "Discovering LUTs.\n",
+            "Number of LUTs:        8\n",
+            "  3-LUT                8\n",
+            "  with \\SB_CARRY    (#0)    7\n",
+            "  with \\SB_CARRY    (#1)    7\n",
+            "\n",
+            "Eliminating LUTs.\n",
+            "Number of LUTs:        8\n",
+            "  3-LUT                8\n",
+            "  with \\SB_CARRY    (#0)    7\n",
+            "  with \\SB_CARRY    (#1)    7\n",
+            "\n",
+            "Combining LUTs.\n",
+            "Number of LUTs:        8\n",
+            "  3-LUT                8\n",
+            "  with \\SB_CARRY    (#0)    7\n",
+            "  with \\SB_CARRY    (#1)    7\n",
+            "\n",
+            "Eliminated 0 LUTs.\n",
+            "Combined 0 LUTs.\n",
+            "\n",
+            "2.45. Executing TECHMAP pass (map to technology primitives).\n",
+            "\n",
+            "2.45.1. Executing Verilog-2005 frontend: /content/miniconda-pnr/bin/../share/yosys/ice40/cells_map.v\n",
+            "Parsing Verilog input from `/content/miniconda-pnr/bin/../share/yosys/ice40/cells_map.v' to AST representation.\n",
+            "Generating RTLIL representation for module `\\$lut'.\n",
+            "Successfully finished Verilog frontend.\n",
+            "\n",
+            "2.45.2. Continuing TECHMAP pass.\n",
+            "Using template $paramod$fd904e9e35cfd343a9df248824bd3f1408724879\\$lut for cells of type $lut.\n",
+            "No more expansions possible.\n",
+            "Removed 0 unused cells and 16 unused wires.\n",
+            "\n",
+            "2.46. Executing AUTONAME pass.\n",
+            "Renamed 23 objects in module adder8 (3 iterations).\n",
+            "\n",
+            "2.47. Executing HIERARCHY pass (managing design hierarchy).\n",
+            "\n",
+            "2.47.1. Analyzing design hierarchy..\n",
+            "Top module:  \\adder8\n",
+            "\n",
+            "2.47.2. Analyzing design hierarchy..\n",
+            "Top module:  \\adder8\n",
+            "Removed 0 unused modules.\n",
+            "\n",
+            "2.48. Printing statistics.\n",
+            "\n",
+            "=== adder8 ===\n",
+            "\n",
+            "   Number of wires:                  4\n",
+            "   Number of wire bits:             32\n",
+            "   Number of public wires:           4\n",
+            "   Number of public wire bits:      32\n",
+            "   Number of memories:               0\n",
+            "   Number of memory bits:            0\n",
+            "   Number of processes:              0\n",
+            "   Number of cells:                 15\n",
+            "     SB_CARRY                        7\n",
+            "     SB_LUT4                         8\n",
+            "\n",
+            "2.49. Executing CHECK pass (checking for obvious problems).\n",
+            "Checking module adder8...\n",
+            "Found and reported 0 problems.\n",
+            "\n",
+            "2.50. Executing JSON backend.\n",
+            "\n",
+            "End of script. Logfile hash: 918e0bdf5e, CPU: user 0.50s system 0.04s, MEM: 106.23 MB peak\n",
+            "Yosys 0.13+37 (git sha1 958c3a46a, x86_64-conda_cos6-linux-gnu-gcc 1.24.0.133_b0863d8_dirty -fvisibility-inlines-hidden -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -fdebug-prefix-map=/home/runner/work/conda-eda/conda-eda/workdir/conda-env/conda-bld/yosys_1644188991550/work=/usr/local/src/conda/yosys-0.13_39_g958c3a46a -fdebug-prefix-map=/content/miniconda-pnr=/usr/local/src/conda-prefix -fPIC -Os -fno-merge-constants)\n",
+            "Time spent: 65% 12x read_verilog (0 sec), 8% 15x opt_clean (0 sec), ...\n",
+            "Warning: Use of default value for --package is deprecated. Please add '--package sg48' to arguments.\n",
+            "Warning: No PCF file specified; IO pins will be placed automatically\n",
+            "\n",
+            "Info: Packing constants..\n",
+            "Info: Packing IOs..\n",
+            "Info: Packing LUT-FFs..\n",
+            "Info:        8 LCs used as LUT4 only\n",
+            "Info:        0 LCs used as LUT4 and DFF\n",
+            "Info: Packing non-LUT FFs..\n",
+            "Info:        0 LCs used as DFF only\n",
+            "Info: Packing carries..\n",
+            "Info:        0 LCs used as CARRY only\n",
+            "Info: Packing indirect carry+LUT pairs...\n",
+            "Info:        0 LUTs merged into carry LCs\n",
+            "Info: Packing RAMs..\n",
+            "Info: Placing PLLs..\n",
+            "Info: Packing special functions..\n",
+            "Info: Packing PLLs..\n",
+            "Info: Promoting globals..\n",
+            "Info: Constraining chains...\n",
+            "Info:        0 LCs used to legalise carry chains.\n",
+            "Info: Checksum: 0xde76ab50\n",
+            "\n",
+            "Info: Annotating ports with timing budgets for target frequency 12.00 MHz\n",
+            "Info: Checksum: 0xfd117054\n",
+            "\n",
+            "Info: Device utilisation:\n",
+            "Info: \t         ICESTORM_LC:    10/ 5280     0%\n",
+            "Info: \t        ICESTORM_RAM:     0/   30     0%\n",
+            "Info: \t               SB_IO:    24/   96    25%\n",
+            "Info: \t               SB_GB:     0/    8     0%\n",
+            "Info: \t        ICESTORM_PLL:     0/    1     0%\n",
+            "Info: \t         SB_WARMBOOT:     0/    1     0%\n",
+            "Info: \t        ICESTORM_DSP:     0/    8     0%\n",
+            "Info: \t      ICESTORM_HFOSC:     0/    1     0%\n",
+            "Info: \t      ICESTORM_LFOSC:     0/    1     0%\n",
+            "Info: \t              SB_I2C:     0/    2     0%\n",
+            "Info: \t              SB_SPI:     0/    2     0%\n",
+            "Info: \t              IO_I3C:     0/    2     0%\n",
+            "Info: \t         SB_LEDDA_IP:     0/    1     0%\n",
+            "Info: \t         SB_RGBA_DRV:     0/    1     0%\n",
+            "Info: \t      ICESTORM_SPRAM:     0/    4     0%\n",
+            "\n",
+            "Info: Placed 0 cells based on constraints.\n",
+            "Info: Creating initial analytic placement for 1 cells, random placement wirelen = 526.\n",
+            "Info:     at initial placer iter 0, wirelen = 496\n",
+            "Info:     at initial placer iter 1, wirelen = 466\n",
+            "Info:     at initial placer iter 2, wirelen = 442\n",
+            "Info:     at initial placer iter 3, wirelen = 424\n",
+            "Info: Running main analytical placer.\n",
+            "Info:     at iteration #1, type ICESTORM_LC: wirelen solved = 412, spread = 412, legal = 412; time = 0.00s\n",
+            "Info: HeAP Placer Time: 0.00s\n",
+            "Info:   of which solving equations: 0.00s\n",
+            "Info:   of which spreading cells: 0.00s\n",
+            "Info:   of which strict legalisation: 0.00s\n",
+            "\n",
+            "Info: Running simulated annealing placer for refinement.\n",
+            "Info:   at iteration #1: temp = 0.000000, timing cost = 0, wirelen = 412\n",
+            "Info:   at iteration #3: temp = 0.000000, timing cost = 0, wirelen = 381 \n",
+            "Info: SA placement time 0.00s\n",
+            "Info: No Fmax available; no interior timing paths found in design.\n",
+            "\n",
+            "Info: Max delay <async> -> <async>: 16.28 ns\n",
+            "\n",
+            "Info: Slack histogram:\n",
+            "Info:  legend: * represents 1 endpoint(s)\n",
+            "Info:          + represents [1,1) endpoint(s)\n",
+            "Info: [ 67052,  67333) |* \n",
+            "Info: [ 67333,  67614) | \n",
+            "Info: [ 67614,  67895) |* \n",
+            "Info: [ 67895,  68176) | \n",
+            "Info: [ 68176,  68457) | \n",
+            "Info: [ 68457,  68738) | \n",
+            "Info: [ 68738,  69019) | \n",
+            "Info: [ 69019,  69300) | \n",
+            "Info: [ 69300,  69581) | \n",
+            "Info: [ 69581,  69862) | \n",
+            "Info: [ 69862,  70143) | \n",
+            "Info: [ 70143,  70424) | \n",
+            "Info: [ 70424,  70705) |* \n",
+            "Info: [ 70705,  70986) | \n",
+            "Info: [ 70986,  71267) | \n",
+            "Info: [ 71267,  71548) | \n",
+            "Info: [ 71548,  71829) |* \n",
+            "Info: [ 71829,  72110) |** \n",
+            "Info: [ 72110,  72391) |* \n",
+            "Info: [ 72391,  72672) |* \n",
+            "Info: Checksum: 0x2b6fd54b\n",
+            "\n",
+            "Info: Routing..\n",
+            "Info: Setting up routing queue.\n",
+            "Info: Routing 37 arcs.\n",
+            "Info:            |   (re-)routed arcs  |   delta    | remaining|       time spent     |\n",
+            "Info:    IterCnt |  w/ripup   wo/ripup |  w/r  wo/r |      arcs| batch(sec) total(sec)|\n",
+            "Info:         37 |        0         31 |    0    31 |         0|       0.02       0.02|\n",
+            "Info: Routing complete.\n",
+            "Info: Router1 time 0.02s\n",
+            "Info: Checksum: 0xeced7674\n",
+            "Info: No Fmax available; no interior timing paths found in design.\n",
+            "\n",
+            "Info: Critical path report for cross-domain path '<async>' -> '<async>':\n",
+            "Info: curr total\n",
+            "Info:  0.0  0.0  Source a[0]$sb_io.D_IN_0\n",
+            "Info:  6.9  6.9    Net a[0]$SB_IO_IN budget 40.057999 ns (13,31) -> (16,2)\n",
+            "Info:                Sink out_SB_LUT4_O_7_LC.I2\n",
+            "Info:                Defined in:\n",
+            "Info:                  adder8.v:3.20-3.21\n",
+            "Info:  0.6  7.5  Source out_SB_LUT4_O_7_LC.COUT\n",
+            "Info:  0.0  7.5    Net out_SB_LUT4_O_I3[1] budget 0.000000 ns (16,2) -> (16,2)\n",
+            "Info:                Sink out_SB_LUT4_O_6_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  adder8.v:7.16-7.21\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3  7.8  Source out_SB_LUT4_O_6_LC.COUT\n",
+            "Info:  0.0  7.8    Net out_SB_LUT4_O_I3[2] budget 0.000000 ns (16,2) -> (16,2)\n",
+            "Info:                Sink out_SB_LUT4_O_5_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  adder8.v:7.16-7.21\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3  8.1  Source out_SB_LUT4_O_5_LC.COUT\n",
+            "Info:  0.0  8.1    Net out_SB_LUT4_O_I3[3] budget 0.000000 ns (16,2) -> (16,2)\n",
+            "Info:                Sink out_SB_LUT4_O_4_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  adder8.v:7.16-7.21\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3  8.4  Source out_SB_LUT4_O_4_LC.COUT\n",
+            "Info:  0.0  8.4    Net out_SB_LUT4_O_I3[4] budget 0.000000 ns (16,2) -> (16,2)\n",
+            "Info:                Sink out_SB_LUT4_O_3_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  adder8.v:7.16-7.21\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3  8.6  Source out_SB_LUT4_O_3_LC.COUT\n",
+            "Info:  0.0  8.6    Net out_SB_LUT4_O_I3[5] budget 0.000000 ns (16,2) -> (16,2)\n",
+            "Info:                Sink out_SB_LUT4_O_2_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  adder8.v:7.16-7.21\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3  8.9  Source out_SB_LUT4_O_2_LC.COUT\n",
+            "Info:  0.0  8.9    Net out_SB_LUT4_O_I3[6] budget 0.000000 ns (16,2) -> (16,2)\n",
+            "Info:                Sink out_SB_LUT4_O_1_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  adder8.v:7.16-7.21\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3  9.2  Source out_SB_LUT4_O_1_LC.COUT\n",
+            "Info:  0.7  9.8    Net out_SB_LUT4_O_I3[7] budget 0.660000 ns (16,2) -> (16,2)\n",
+            "Info:                Sink out_SB_LUT4_O_LC.I3\n",
+            "Info:                Defined in:\n",
+            "Info:                  adder8.v:7.16-7.21\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.9 10.7  Source out_SB_LUT4_O_LC.O\n",
+            "Info:  6.7 17.4    Net out[7]$SB_IO_OUT budget 40.057999 ns (16,2) -> (13,31)\n",
+            "Info:                Sink out[7]$sb_io.D_OUT_0\n",
+            "Info:                Defined in:\n",
+            "Info:                  adder8.v:5.21-5.24\n",
+            "Info: 3.2 ns logic, 14.3 ns routing\n",
+            "\n",
+            "Info: Max delay <async> -> <async>: 17.41 ns\n",
+            "\n",
+            "Info: Slack histogram:\n",
+            "Info:  legend: * represents 1 endpoint(s)\n",
+            "Info:          + represents [1,1) endpoint(s)\n",
+            "Info: [ 65926,  66244) |* \n",
+            "Info: [ 66244,  66562) | \n",
+            "Info: [ 66562,  66880) | \n",
+            "Info: [ 66880,  67198) | \n",
+            "Info: [ 67198,  67516) |* \n",
+            "Info: [ 67516,  67834) | \n",
+            "Info: [ 67834,  68152) | \n",
+            "Info: [ 68152,  68470) | \n",
+            "Info: [ 68470,  68788) | \n",
+            "Info: [ 68788,  69106) |* \n",
+            "Info: [ 69106,  69424) | \n",
+            "Info: [ 69424,  69742) | \n",
+            "Info: [ 69742,  70060) | \n",
+            "Info: [ 70060,  70378) |* \n",
+            "Info: [ 70378,  70696) | \n",
+            "Info: [ 70696,  71014) |* \n",
+            "Info: [ 71014,  71332) |** \n",
+            "Info: [ 71332,  71650) | \n",
+            "Info: [ 71650,  71968) | \n",
+            "Info: [ 71968,  72286) |* \n",
+            "2 warnings, 0 errors\n",
+            "\n",
+            "Info: Program finished normally.\n"
+          ]
+        }
+      ]
+    },
+    {
+      "cell_type": "code",
+      "metadata": {
+        "colab": {
+          "base_uri": "https://localhost:8080/",
+          "height": 1000
+        },
+        "id": "7zFh446sIRSt",
+        "outputId": "44a44e86-90c4-4b10-bd7c-c32d5d8d606e"
+      },
+      "source": [
+        "from IPython.display import SVG\n",
+        "SVG(filename='adder8_placed.svg')"
+      ],
+      "execution_count": 22,
+      "outputs": [
+        {
+          "output_type": "execute_result",
+          "data": {
+            "text/plain": [
+              "<IPython.core.display.SVG object>"
+            ],
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+          },
+          "metadata": {},
+          "execution_count": 22
+        }
+      ]
+    },
+    {
+      "cell_type": "markdown",
+      "metadata": {
+        "id": "od-Og6WeryG6"
+      },
+      "source": [
+        "### Place and Route 18-bit polynomial function"
+      ]
+    },
+    {
+      "cell_type": "code",
+      "metadata": {
+        "id": "d2dqpJW4K3mK",
+        "colab": {
+          "base_uri": "https://localhost:8080/"
+        },
+        "outputId": "9c392232-896e-4b61-f7ea-0bbdfde68d44"
+      },
+      "source": [
+        "!git clone https://github.com/projf/projf-explore.git\n",
+        "# make it bigger!\n",
+        "!sed -i -e s/CORDW=8/CORDW=18/ projf-explore/maths/demo/func_polynomial.sv"
+      ],
+      "execution_count": 23,
+      "outputs": [
+        {
+          "output_type": "stream",
+          "name": "stdout",
+          "text": [
+            "Cloning into 'projf-explore'...\n",
+            "remote: Enumerating objects: 6759, done.\u001b[K\n",
+            "remote: Counting objects: 100% (521/521), done.\u001b[K\n",
+            "remote: Compressing objects: 100% (241/241), done.\u001b[K\n",
+            "remote: Total 6759 (delta 392), reused 293 (delta 278), pack-reused 6238 (from 4)\u001b[K\n",
+            "Receiving objects: 100% (6759/6759), 3.18 MiB | 18.73 MiB/s, done.\n",
+            "Resolving deltas: 100% (4576/4576), done.\n"
+          ]
+        }
+      ]
+    },
+    {
+      "cell_type": "code",
+      "metadata": {
+        "id": "RjppC5AdMluF",
+        "colab": {
+          "base_uri": "https://localhost:8080/"
+        },
+        "outputId": "8fd3dbff-36fb-4edc-ceb4-d3cba859f593"
+      },
+      "source": [
+        "!miniconda-pnr/bin/yosys -p 'synth_ice40 -top func_polynomial -json func_polynomial.json' projf-explore/maths/demo/func_polynomial.sv\n",
+        "!miniconda-pnr/bin/nextpnr-ice40 --up5k --json func_polynomial.json --asc func_polynomial.asc --placed-svg func_polynomial_placed.svg"
+      ],
+      "execution_count": 24,
+      "outputs": [
+        {
+          "output_type": "stream",
+          "name": "stdout",
+          "text": [
+            "\n",
+            " /----------------------------------------------------------------------------\\\n",
+            " |                                                                            |\n",
+            " |  yosys -- Yosys Open SYnthesis Suite                                       |\n",
+            " |                                                                            |\n",
+            " |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <claire@yosyshq.com>         |\n",
+            " |                                                                            |\n",
+            " |  Permission to use, copy, modify, and/or distribute this software for any  |\n",
+            " |  purpose with or without fee is hereby granted, provided that the above    |\n",
+            " |  copyright notice and this permission notice appear in all copies.         |\n",
+            " |                                                                            |\n",
+            " |  THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |\n",
+            " |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |\n",
+            " |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |\n",
+            " |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |\n",
+            " |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |\n",
+            " |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |\n",
+            " |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |\n",
+            " |                                                                            |\n",
+            " \\----------------------------------------------------------------------------/\n",
+            "\n",
+            " Yosys 0.13+37 (git sha1 958c3a46a, x86_64-conda_cos6-linux-gnu-gcc 1.24.0.133_b0863d8_dirty -fvisibility-inlines-hidden -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -fdebug-prefix-map=/home/runner/work/conda-eda/conda-eda/workdir/conda-env/conda-bld/yosys_1644188991550/work=/usr/local/src/conda/yosys-0.13_39_g958c3a46a -fdebug-prefix-map=/content/miniconda-pnr=/usr/local/src/conda-prefix -fPIC -Os -fno-merge-constants)\n",
+            "\n",
+            "\n",
+            "-- Parsing `projf-explore/maths/demo/func_polynomial.sv' using frontend ` -sv' --\n",
+            "\n",
+            "1. Executing Verilog-2005 frontend: projf-explore/maths/demo/func_polynomial.sv\n",
+            "Parsing SystemVerilog input from `projf-explore/maths/demo/func_polynomial.sv' to AST representation.\n",
+            "Storing AST representation for module `$abstract\\func_polynomial'.\n",
+            "Successfully finished Verilog frontend.\n",
+            "\n",
+            "-- Running command `synth_ice40 -top func_polynomial -json func_polynomial.json' --\n",
+            "\n",
+            "2. Executing SYNTH_ICE40 pass.\n",
+            "\n",
+            "2.1. Executing Verilog-2005 frontend: /content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v\n",
+            "Parsing Verilog input from `/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v' to AST representation.\n",
+            "Generating RTLIL representation for module `\\SB_IO'.\n",
+            "Generating RTLIL representation for module `\\SB_GB_IO'.\n",
+            "Generating RTLIL representation for module `\\SB_GB'.\n",
+            "Generating RTLIL representation for module `\\SB_LUT4'.\n",
+            "Generating RTLIL representation for module `\\SB_CARRY'.\n",
+            "Generating RTLIL representation for module `\\SB_DFF'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFE'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFSR'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFR'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFSS'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFS'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFESR'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFER'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFESS'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFES'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFN'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFNE'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFNSR'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFNR'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFNSS'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFNS'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFNESR'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFNER'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFNESS'.\n",
+            "Generating RTLIL representation for module `\\SB_DFFNES'.\n",
+            "Generating RTLIL representation for module `\\SB_RAM40_4K'.\n",
+            "Generating RTLIL representation for module `\\SB_RAM40_4KNR'.\n",
+            "Generating RTLIL representation for module `\\SB_RAM40_4KNW'.\n",
+            "Generating RTLIL representation for module `\\SB_RAM40_4KNRNW'.\n",
+            "Generating RTLIL representation for module `\\ICESTORM_LC'.\n",
+            "Generating RTLIL representation for module `\\SB_PLL40_CORE'.\n",
+            "Generating RTLIL representation for module `\\SB_PLL40_PAD'.\n",
+            "Generating RTLIL representation for module `\\SB_PLL40_2_PAD'.\n",
+            "Generating RTLIL representation for module `\\SB_PLL40_2F_CORE'.\n",
+            "Generating RTLIL representation for module `\\SB_PLL40_2F_PAD'.\n",
+            "Generating RTLIL representation for module `\\SB_WARMBOOT'.\n",
+            "Generating RTLIL representation for module `\\SB_SPRAM256KA'.\n",
+            "Generating RTLIL representation for module `\\SB_HFOSC'.\n",
+            "Generating RTLIL representation for module `\\SB_LFOSC'.\n",
+            "Generating RTLIL representation for module `\\SB_RGBA_DRV'.\n",
+            "Generating RTLIL representation for module `\\SB_LED_DRV_CUR'.\n",
+            "Generating RTLIL representation for module `\\SB_RGB_DRV'.\n",
+            "Generating RTLIL representation for module `\\SB_I2C'.\n",
+            "Generating RTLIL representation for module `\\SB_SPI'.\n",
+            "Generating RTLIL representation for module `\\SB_LEDDA_IP'.\n",
+            "Generating RTLIL representation for module `\\SB_FILTER_50NS'.\n",
+            "Generating RTLIL representation for module `\\SB_IO_I3C'.\n",
+            "Generating RTLIL representation for module `\\SB_IO_OD'.\n",
+            "Generating RTLIL representation for module `\\SB_MAC16'.\n",
+            "Generating RTLIL representation for module `\\ICESTORM_RAM'.\n",
+            "Successfully finished Verilog frontend.\n",
+            "\n",
+            "2.2. Executing HIERARCHY pass (managing design hierarchy).\n",
+            "\n",
+            "2.3. Executing AST frontend in derive mode using pre-parsed AST for module `\\func_polynomial'.\n",
+            "Generating RTLIL representation for module `\\func_polynomial'.\n",
+            "\n",
+            "2.3.1. Analyzing design hierarchy..\n",
+            "Top module:  \\func_polynomial\n",
+            "\n",
+            "2.3.2. Analyzing design hierarchy..\n",
+            "Top module:  \\func_polynomial\n",
+            "Removing unused module `$abstract\\func_polynomial'.\n",
+            "Removed 1 unused modules.\n",
+            "\n",
+            "2.4. Executing PROC pass (convert processes to netlists).\n",
+            "\n",
+            "2.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).\n",
+            "Cleaned up 0 empty switches.\n",
+            "\n",
+            "2.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1386$241 in module SB_DFFNES.\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1328$234 in module SB_DFFNESS.\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1251$230 in module SB_DFFNER.\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1193$223 in module SB_DFFNESR.\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1122$220 in module SB_DFFNS.\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1072$217 in module SB_DFFNSS.\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1001$214 in module SB_DFFNR.\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:951$211 in module SB_DFFNSR.\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:789$203 in module SB_DFFES.\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:731$196 in module SB_DFFESS.\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:654$192 in module SB_DFFER.\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:596$185 in module SB_DFFESR.\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:525$182 in module SB_DFFS.\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:475$179 in module SB_DFFSS.\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:404$176 in module SB_DFFR.\n",
+            "Marked 1 switch rules as full_case in process $proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:354$173 in module SB_DFFSR.\n",
+            "Removed a total of 0 dead cases.\n",
+            "\n",
+            "2.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).\n",
+            "Removed 8 redundant assignments.\n",
+            "Promoted 35 assignments to connections.\n",
+            "\n",
+            "2.4.4. Executing PROC_INIT pass (extract init attributes).\n",
+            "Found init rule in `\\SB_DFFNES.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$244'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFNESS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$240'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFNER.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$233'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFNESR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$229'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFNS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$222'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFNSS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$219'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFNR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$216'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFNSR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$213'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFNE.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$210'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFN.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$208'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFES.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$206'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFESS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$202'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFER.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$195'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFESR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$191'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$184'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFSS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$181'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$178'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFSR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$175'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFFE.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$172'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "Found init rule in `\\SB_DFF.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$170'.\n",
+            "  Set init value: \\Q = 1'0\n",
+            "\n",
+            "2.4.5. Executing PROC_ARST pass (detect async resets in processes).\n",
+            "Found async reset \\S in `\\SB_DFFNES.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1386$241'.\n",
+            "Found async reset \\R in `\\SB_DFFNER.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1251$230'.\n",
+            "Found async reset \\S in `\\SB_DFFNS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1122$220'.\n",
+            "Found async reset \\R in `\\SB_DFFNR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1001$214'.\n",
+            "Found async reset \\S in `\\SB_DFFES.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:789$203'.\n",
+            "Found async reset \\R in `\\SB_DFFER.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:654$192'.\n",
+            "Found async reset \\S in `\\SB_DFFS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:525$182'.\n",
+            "Found async reset \\R in `\\SB_DFFR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:404$176'.\n",
+            "\n",
+            "2.4.6. Executing PROC_MUX pass (convert decision trees to multiplexers).\n",
+            "Creating decoders for process `\\SB_DFFNES.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$244'.\n",
+            "Creating decoders for process `\\SB_DFFNES.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1386$241'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFNESS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$240'.\n",
+            "Creating decoders for process `\\SB_DFFNESS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1328$234'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFNER.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$233'.\n",
+            "Creating decoders for process `\\SB_DFFNER.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1251$230'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFNESR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$229'.\n",
+            "Creating decoders for process `\\SB_DFFNESR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1193$223'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFNS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$222'.\n",
+            "Creating decoders for process `\\SB_DFFNS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1122$220'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFNSS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$219'.\n",
+            "Creating decoders for process `\\SB_DFFNSS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1072$217'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFNR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$216'.\n",
+            "Creating decoders for process `\\SB_DFFNR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1001$214'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFNSR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$213'.\n",
+            "Creating decoders for process `\\SB_DFFNSR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:951$211'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFNE.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$210'.\n",
+            "Creating decoders for process `\\SB_DFFNE.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:906$209'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFN.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$208'.\n",
+            "Creating decoders for process `\\SB_DFFN.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:868$207'.\n",
+            "Creating decoders for process `\\SB_DFFES.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$206'.\n",
+            "Creating decoders for process `\\SB_DFFES.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:789$203'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFESS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$202'.\n",
+            "Creating decoders for process `\\SB_DFFESS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:731$196'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFER.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$195'.\n",
+            "Creating decoders for process `\\SB_DFFER.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:654$192'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFESR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$191'.\n",
+            "Creating decoders for process `\\SB_DFFESR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:596$185'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$184'.\n",
+            "Creating decoders for process `\\SB_DFFS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:525$182'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFSS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$181'.\n",
+            "Creating decoders for process `\\SB_DFFSS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:475$179'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$178'.\n",
+            "Creating decoders for process `\\SB_DFFR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:404$176'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFSR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$175'.\n",
+            "Creating decoders for process `\\SB_DFFSR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:354$173'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFFE.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$172'.\n",
+            "Creating decoders for process `\\SB_DFFE.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:309$171'.\n",
+            "     1/1: $0\\Q[0:0]\n",
+            "Creating decoders for process `\\SB_DFF.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$170'.\n",
+            "Creating decoders for process `\\SB_DFF.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:271$169'.\n",
+            "Creating decoders for process `\\func_polynomial.$proc$projf-explore/maths/demo/func_polynomial.sv:30$381'.\n",
+            "\n",
+            "2.4.7. Executing PROC_DLATCH pass (convert process syncs to latches).\n",
+            "\n",
+            "2.4.8. Executing PROC_DFF pass (convert process syncs to FFs).\n",
+            "Creating register for signal `\\SB_DFFNES.\\Q' using process `\\SB_DFFNES.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1386$241'.\n",
+            "  created $adff cell `$procdff$433' with negative edge clock and positive level reset.\n",
+            "Creating register for signal `\\SB_DFFNESS.\\Q' using process `\\SB_DFFNESS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1328$234'.\n",
+            "  created $dff cell `$procdff$434' with negative edge clock.\n",
+            "Creating register for signal `\\SB_DFFNER.\\Q' using process `\\SB_DFFNER.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1251$230'.\n",
+            "  created $adff cell `$procdff$435' with negative edge clock and positive level reset.\n",
+            "Creating register for signal `\\SB_DFFNESR.\\Q' using process `\\SB_DFFNESR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1193$223'.\n",
+            "  created $dff cell `$procdff$436' with negative edge clock.\n",
+            "Creating register for signal `\\SB_DFFNS.\\Q' using process `\\SB_DFFNS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1122$220'.\n",
+            "  created $adff cell `$procdff$437' with negative edge clock and positive level reset.\n",
+            "Creating register for signal `\\SB_DFFNSS.\\Q' using process `\\SB_DFFNSS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1072$217'.\n",
+            "  created $dff cell `$procdff$438' with negative edge clock.\n",
+            "Creating register for signal `\\SB_DFFNR.\\Q' using process `\\SB_DFFNR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1001$214'.\n",
+            "  created $adff cell `$procdff$439' with negative edge clock and positive level reset.\n",
+            "Creating register for signal `\\SB_DFFNSR.\\Q' using process `\\SB_DFFNSR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:951$211'.\n",
+            "  created $dff cell `$procdff$440' with negative edge clock.\n",
+            "Creating register for signal `\\SB_DFFNE.\\Q' using process `\\SB_DFFNE.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:906$209'.\n",
+            "  created $dff cell `$procdff$441' with negative edge clock.\n",
+            "Creating register for signal `\\SB_DFFN.\\Q' using process `\\SB_DFFN.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:868$207'.\n",
+            "  created $dff cell `$procdff$442' with negative edge clock.\n",
+            "Creating register for signal `\\SB_DFFES.\\Q' using process `\\SB_DFFES.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:789$203'.\n",
+            "  created $adff cell `$procdff$443' with positive edge clock and positive level reset.\n",
+            "Creating register for signal `\\SB_DFFESS.\\Q' using process `\\SB_DFFESS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:731$196'.\n",
+            "  created $dff cell `$procdff$444' with positive edge clock.\n",
+            "Creating register for signal `\\SB_DFFER.\\Q' using process `\\SB_DFFER.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:654$192'.\n",
+            "  created $adff cell `$procdff$445' with positive edge clock and positive level reset.\n",
+            "Creating register for signal `\\SB_DFFESR.\\Q' using process `\\SB_DFFESR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:596$185'.\n",
+            "  created $dff cell `$procdff$446' with positive edge clock.\n",
+            "Creating register for signal `\\SB_DFFS.\\Q' using process `\\SB_DFFS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:525$182'.\n",
+            "  created $adff cell `$procdff$447' with positive edge clock and positive level reset.\n",
+            "Creating register for signal `\\SB_DFFSS.\\Q' using process `\\SB_DFFSS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:475$179'.\n",
+            "  created $dff cell `$procdff$448' with positive edge clock.\n",
+            "Creating register for signal `\\SB_DFFR.\\Q' using process `\\SB_DFFR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:404$176'.\n",
+            "  created $adff cell `$procdff$449' with positive edge clock and positive level reset.\n",
+            "Creating register for signal `\\SB_DFFSR.\\Q' using process `\\SB_DFFSR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:354$173'.\n",
+            "  created $dff cell `$procdff$450' with positive edge clock.\n",
+            "Creating register for signal `\\SB_DFFE.\\Q' using process `\\SB_DFFE.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:309$171'.\n",
+            "  created $dff cell `$procdff$451' with positive edge clock.\n",
+            "Creating register for signal `\\SB_DFF.\\Q' using process `\\SB_DFF.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:271$169'.\n",
+            "  created $dff cell `$procdff$452' with positive edge clock.\n",
+            "Creating register for signal `\\func_polynomial.\\r' using process `\\func_polynomial.$proc$projf-explore/maths/demo/func_polynomial.sv:30$381'.\n",
+            "  created $dff cell `$procdff$453' with positive edge clock.\n",
+            "Creating register for signal `\\func_polynomial.\\x_squared' using process `\\func_polynomial.$proc$projf-explore/maths/demo/func_polynomial.sv:30$381'.\n",
+            "  created $dff cell `$procdff$454' with positive edge clock.\n",
+            "Creating register for signal `\\func_polynomial.\\x_squared_p1' using process `\\func_polynomial.$proc$projf-explore/maths/demo/func_polynomial.sv:30$381'.\n",
+            "  created $dff cell `$procdff$455' with positive edge clock.\n",
+            "Creating register for signal `\\func_polynomial.\\x_squared_p2' using process `\\func_polynomial.$proc$projf-explore/maths/demo/func_polynomial.sv:30$381'.\n",
+            "  created $dff cell `$procdff$456' with positive edge clock.\n",
+            "Creating register for signal `\\func_polynomial.\\x_squared_p3' using process `\\func_polynomial.$proc$projf-explore/maths/demo/func_polynomial.sv:30$381'.\n",
+            "  created $dff cell `$procdff$457' with positive edge clock.\n",
+            "Creating register for signal `\\func_polynomial.\\x_fourth' using process `\\func_polynomial.$proc$projf-explore/maths/demo/func_polynomial.sv:30$381'.\n",
+            "  created $dff cell `$procdff$458' with positive edge clock.\n",
+            "Creating register for signal `\\func_polynomial.\\x_fourth_p1' using process `\\func_polynomial.$proc$projf-explore/maths/demo/func_polynomial.sv:30$381'.\n",
+            "  created $dff cell `$procdff$459' with positive edge clock.\n",
+            "Creating register for signal `\\func_polynomial.\\x_poly' using process `\\func_polynomial.$proc$projf-explore/maths/demo/func_polynomial.sv:30$381'.\n",
+            "  created $dff cell `$procdff$460' with positive edge clock.\n",
+            "Creating register for signal `\\func_polynomial.\\y_scaled' using process `\\func_polynomial.$proc$projf-explore/maths/demo/func_polynomial.sv:30$381'.\n",
+            "  created $dff cell `$procdff$461' with positive edge clock.\n",
+            "Creating register for signal `\\func_polynomial.\\y_scaled_p1' using process `\\func_polynomial.$proc$projf-explore/maths/demo/func_polynomial.sv:30$381'.\n",
+            "  created $dff cell `$procdff$462' with positive edge clock.\n",
+            "Creating register for signal `\\func_polynomial.\\y_scaled_p2' using process `\\func_polynomial.$proc$projf-explore/maths/demo/func_polynomial.sv:30$381'.\n",
+            "  created $dff cell `$procdff$463' with positive edge clock.\n",
+            "Creating register for signal `\\func_polynomial.\\y_scaled_p3' using process `\\func_polynomial.$proc$projf-explore/maths/demo/func_polynomial.sv:30$381'.\n",
+            "  created $dff cell `$procdff$464' with positive edge clock.\n",
+            "Creating register for signal `\\func_polynomial.\\y_scaled_p4' using process `\\func_polynomial.$proc$projf-explore/maths/demo/func_polynomial.sv:30$381'.\n",
+            "  created $dff cell `$procdff$465' with positive edge clock.\n",
+            "\n",
+            "2.4.9. Executing PROC_MEMWR pass (convert process memory writes to cells).\n",
+            "\n",
+            "2.4.10. Executing PROC_CLEAN pass (remove empty switches from decision trees).\n",
+            "Removing empty process `SB_DFFNES.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$244'.\n",
+            "Found and cleaned up 1 empty switch in `\\SB_DFFNES.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1386$241'.\n",
+            "Removing empty process `SB_DFFNES.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1386$241'.\n",
+            "Removing empty process `SB_DFFNESS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$240'.\n",
+            "Found and cleaned up 2 empty switches in `\\SB_DFFNESS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1328$234'.\n",
+            "Removing empty process `SB_DFFNESS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1328$234'.\n",
+            "Removing empty process `SB_DFFNER.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$233'.\n",
+            "Found and cleaned up 1 empty switch in `\\SB_DFFNER.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1251$230'.\n",
+            "Removing empty process `SB_DFFNER.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1251$230'.\n",
+            "Removing empty process `SB_DFFNESR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$229'.\n",
+            "Found and cleaned up 2 empty switches in `\\SB_DFFNESR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1193$223'.\n",
+            "Removing empty process `SB_DFFNESR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1193$223'.\n",
+            "Removing empty process `SB_DFFNS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$222'.\n",
+            "Removing empty process `SB_DFFNS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1122$220'.\n",
+            "Removing empty process `SB_DFFNSS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$219'.\n",
+            "Found and cleaned up 1 empty switch in `\\SB_DFFNSS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1072$217'.\n",
+            "Removing empty process `SB_DFFNSS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1072$217'.\n",
+            "Removing empty process `SB_DFFNR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$216'.\n",
+            "Removing empty process `SB_DFFNR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:1001$214'.\n",
+            "Removing empty process `SB_DFFNSR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$213'.\n",
+            "Found and cleaned up 1 empty switch in `\\SB_DFFNSR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:951$211'.\n",
+            "Removing empty process `SB_DFFNSR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:951$211'.\n",
+            "Removing empty process `SB_DFFNE.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$210'.\n",
+            "Found and cleaned up 1 empty switch in `\\SB_DFFNE.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:906$209'.\n",
+            "Removing empty process `SB_DFFNE.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:906$209'.\n",
+            "Removing empty process `SB_DFFN.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$208'.\n",
+            "Removing empty process `SB_DFFN.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:868$207'.\n",
+            "Removing empty process `SB_DFFES.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$206'.\n",
+            "Found and cleaned up 1 empty switch in `\\SB_DFFES.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:789$203'.\n",
+            "Removing empty process `SB_DFFES.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:789$203'.\n",
+            "Removing empty process `SB_DFFESS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$202'.\n",
+            "Found and cleaned up 2 empty switches in `\\SB_DFFESS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:731$196'.\n",
+            "Removing empty process `SB_DFFESS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:731$196'.\n",
+            "Removing empty process `SB_DFFER.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$195'.\n",
+            "Found and cleaned up 1 empty switch in `\\SB_DFFER.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:654$192'.\n",
+            "Removing empty process `SB_DFFER.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:654$192'.\n",
+            "Removing empty process `SB_DFFESR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$191'.\n",
+            "Found and cleaned up 2 empty switches in `\\SB_DFFESR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:596$185'.\n",
+            "Removing empty process `SB_DFFESR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:596$185'.\n",
+            "Removing empty process `SB_DFFS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$184'.\n",
+            "Removing empty process `SB_DFFS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:525$182'.\n",
+            "Removing empty process `SB_DFFSS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$181'.\n",
+            "Found and cleaned up 1 empty switch in `\\SB_DFFSS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:475$179'.\n",
+            "Removing empty process `SB_DFFSS.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:475$179'.\n",
+            "Removing empty process `SB_DFFR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$178'.\n",
+            "Removing empty process `SB_DFFR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:404$176'.\n",
+            "Removing empty process `SB_DFFSR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$175'.\n",
+            "Found and cleaned up 1 empty switch in `\\SB_DFFSR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:354$173'.\n",
+            "Removing empty process `SB_DFFSR.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:354$173'.\n",
+            "Removing empty process `SB_DFFE.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$172'.\n",
+            "Found and cleaned up 1 empty switch in `\\SB_DFFE.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:309$171'.\n",
+            "Removing empty process `SB_DFFE.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:309$171'.\n",
+            "Removing empty process `SB_DFF.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:0$170'.\n",
+            "Removing empty process `SB_DFF.$proc$/content/miniconda-pnr/bin/../share/yosys/ice40/cells_sim.v:271$169'.\n",
+            "Removing empty process `func_polynomial.$proc$projf-explore/maths/demo/func_polynomial.sv:30$381'.\n",
+            "Cleaned up 18 empty switches.\n",
+            "\n",
+            "2.4.11. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module func_polynomial.\n",
+            "\n",
+            "2.5. Executing FLATTEN pass (flatten design).\n",
+            "\n",
+            "2.6. Executing TRIBUF pass.\n",
+            "\n",
+            "2.7. Executing DEMINOUT pass (demote inout ports to input or output).\n",
+            "\n",
+            "2.8. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module func_polynomial.\n",
+            "\n",
+            "2.9. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\func_polynomial..\n",
+            "Removed 0 unused cells and 14 unused wires.\n",
+            "\n",
+            "2.10. Executing CHECK pass (checking for obvious problems).\n",
+            "Checking module func_polynomial...\n",
+            "Found and reported 0 problems.\n",
+            "\n",
+            "2.11. Executing OPT pass (performing simple optimizations).\n",
+            "\n",
+            "2.11.1. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module func_polynomial.\n",
+            "\n",
+            "2.11.2. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\func_polynomial'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "2.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n",
+            "Running muxtree optimizer on module \\func_polynomial..\n",
+            "  Creating internal representation of mux trees.\n",
+            "  Evaluating internal representation of mux trees.\n",
+            "  Analyzing evaluation results.\n",
+            "Removed 0 multiplexer ports.\n",
+            "\n",
+            "2.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n",
+            "  Optimizing cells in module \\func_polynomial.\n",
+            "Performed a total of 0 changes.\n",
+            "\n",
+            "2.11.5. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\func_polynomial'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "2.11.6. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "Setting constant 0-bit at position 0 on $procdff$465 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 1 on $procdff$465 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 2 on $procdff$465 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 3 on $procdff$465 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 4 on $procdff$465 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 5 on $procdff$465 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 6 on $procdff$465 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 7 on $procdff$465 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 8 on $procdff$465 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 9 on $procdff$465 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 10 on $procdff$465 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 11 on $procdff$465 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 12 on $procdff$465 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 13 on $procdff$465 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 14 on $procdff$465 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 15 on $procdff$465 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 16 on $procdff$465 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 17 on $procdff$465 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 18 on $procdff$465 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 19 on $procdff$465 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 20 on $procdff$465 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 21 on $procdff$465 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 22 on $procdff$465 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 23 on $procdff$465 ($dff) from module func_polynomial.\n",
+            "\n",
+            "2.11.7. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\func_polynomial..\n",
+            "\n",
+            "2.11.8. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module func_polynomial.\n",
+            "\n",
+            "2.11.9. Rerunning OPT passes. (Maybe there is more to do..)\n",
+            "\n",
+            "2.11.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n",
+            "Running muxtree optimizer on module \\func_polynomial..\n",
+            "  Creating internal representation of mux trees.\n",
+            "  Evaluating internal representation of mux trees.\n",
+            "  Analyzing evaluation results.\n",
+            "Removed 0 multiplexer ports.\n",
+            "\n",
+            "2.11.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n",
+            "  Optimizing cells in module \\func_polynomial.\n",
+            "Performed a total of 0 changes.\n",
+            "\n",
+            "2.11.12. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\func_polynomial'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "2.11.13. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "Setting constant 0-bit at position 0 on $procdff$464 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 1 on $procdff$464 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 2 on $procdff$464 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 3 on $procdff$464 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 4 on $procdff$464 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 5 on $procdff$464 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 6 on $procdff$464 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 7 on $procdff$464 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 8 on $procdff$464 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 9 on $procdff$464 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 10 on $procdff$464 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 11 on $procdff$464 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 12 on $procdff$464 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 13 on $procdff$464 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 14 on $procdff$464 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 15 on $procdff$464 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 16 on $procdff$464 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 17 on $procdff$464 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 18 on $procdff$464 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 19 on $procdff$464 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 20 on $procdff$464 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 21 on $procdff$464 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 22 on $procdff$464 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 23 on $procdff$464 ($dff) from module func_polynomial.\n",
+            "\n",
+            "2.11.14. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\func_polynomial..\n",
+            "\n",
+            "2.11.15. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module func_polynomial.\n",
+            "\n",
+            "2.11.16. Rerunning OPT passes. (Maybe there is more to do..)\n",
+            "\n",
+            "2.11.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n",
+            "Running muxtree optimizer on module \\func_polynomial..\n",
+            "  Creating internal representation of mux trees.\n",
+            "  Evaluating internal representation of mux trees.\n",
+            "  Analyzing evaluation results.\n",
+            "Removed 0 multiplexer ports.\n",
+            "\n",
+            "2.11.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n",
+            "  Optimizing cells in module \\func_polynomial.\n",
+            "Performed a total of 0 changes.\n",
+            "\n",
+            "2.11.19. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\func_polynomial'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "2.11.20. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "Setting constant 0-bit at position 0 on $procdff$463 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 1 on $procdff$463 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 2 on $procdff$463 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 3 on $procdff$463 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 4 on $procdff$463 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 5 on $procdff$463 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 6 on $procdff$463 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 7 on $procdff$463 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 8 on $procdff$463 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 9 on $procdff$463 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 10 on $procdff$463 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 11 on $procdff$463 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 12 on $procdff$463 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 13 on $procdff$463 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 14 on $procdff$463 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 15 on $procdff$463 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 16 on $procdff$463 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 17 on $procdff$463 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 18 on $procdff$463 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 19 on $procdff$463 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 20 on $procdff$463 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 21 on $procdff$463 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 22 on $procdff$463 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 23 on $procdff$463 ($dff) from module func_polynomial.\n",
+            "\n",
+            "2.11.21. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\func_polynomial..\n",
+            "\n",
+            "2.11.22. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module func_polynomial.\n",
+            "\n",
+            "2.11.23. Rerunning OPT passes. (Maybe there is more to do..)\n",
+            "\n",
+            "2.11.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n",
+            "Running muxtree optimizer on module \\func_polynomial..\n",
+            "  Creating internal representation of mux trees.\n",
+            "  Evaluating internal representation of mux trees.\n",
+            "  Analyzing evaluation results.\n",
+            "Removed 0 multiplexer ports.\n",
+            "\n",
+            "2.11.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n",
+            "  Optimizing cells in module \\func_polynomial.\n",
+            "Performed a total of 0 changes.\n",
+            "\n",
+            "2.11.26. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\func_polynomial'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "2.11.27. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "Setting constant 0-bit at position 0 on $procdff$462 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 1 on $procdff$462 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 2 on $procdff$462 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 3 on $procdff$462 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 4 on $procdff$462 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 5 on $procdff$462 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 6 on $procdff$462 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 7 on $procdff$462 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 8 on $procdff$462 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 9 on $procdff$462 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 10 on $procdff$462 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 11 on $procdff$462 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 12 on $procdff$462 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 13 on $procdff$462 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 14 on $procdff$462 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 15 on $procdff$462 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 16 on $procdff$462 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 17 on $procdff$462 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 18 on $procdff$462 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 19 on $procdff$462 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 20 on $procdff$462 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 21 on $procdff$462 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 22 on $procdff$462 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 23 on $procdff$462 ($dff) from module func_polynomial.\n",
+            "\n",
+            "2.11.28. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\func_polynomial..\n",
+            "\n",
+            "2.11.29. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module func_polynomial.\n",
+            "\n",
+            "2.11.30. Rerunning OPT passes. (Maybe there is more to do..)\n",
+            "\n",
+            "2.11.31. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n",
+            "Running muxtree optimizer on module \\func_polynomial..\n",
+            "  Creating internal representation of mux trees.\n",
+            "  Evaluating internal representation of mux trees.\n",
+            "  Analyzing evaluation results.\n",
+            "Removed 0 multiplexer ports.\n",
+            "\n",
+            "2.11.32. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n",
+            "  Optimizing cells in module \\func_polynomial.\n",
+            "Performed a total of 0 changes.\n",
+            "\n",
+            "2.11.33. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\func_polynomial'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "2.11.34. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "Setting constant 0-bit at position 0 on $procdff$461 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 1 on $procdff$461 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 2 on $procdff$461 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 3 on $procdff$461 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 4 on $procdff$461 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 5 on $procdff$461 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 6 on $procdff$461 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 7 on $procdff$461 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 8 on $procdff$461 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 9 on $procdff$461 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 10 on $procdff$461 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 11 on $procdff$461 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 12 on $procdff$461 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 13 on $procdff$461 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 14 on $procdff$461 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 15 on $procdff$461 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 16 on $procdff$461 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 17 on $procdff$461 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 18 on $procdff$461 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 19 on $procdff$461 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 20 on $procdff$461 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 21 on $procdff$461 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 22 on $procdff$461 ($dff) from module func_polynomial.\n",
+            "Setting constant 0-bit at position 23 on $procdff$461 ($dff) from module func_polynomial.\n",
+            "\n",
+            "2.11.35. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\func_polynomial..\n",
+            "\n",
+            "2.11.36. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module func_polynomial.\n",
+            "\n",
+            "2.11.37. Rerunning OPT passes. (Maybe there is more to do..)\n",
+            "\n",
+            "2.11.38. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n",
+            "Running muxtree optimizer on module \\func_polynomial..\n",
+            "  Creating internal representation of mux trees.\n",
+            "  Evaluating internal representation of mux trees.\n",
+            "  Analyzing evaluation results.\n",
+            "Removed 0 multiplexer ports.\n",
+            "\n",
+            "2.11.39. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n",
+            "  Optimizing cells in module \\func_polynomial.\n",
+            "Performed a total of 0 changes.\n",
+            "\n",
+            "2.11.40. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\func_polynomial'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "2.11.41. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "2.11.42. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\func_polynomial..\n",
+            "\n",
+            "2.11.43. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module func_polynomial.\n",
+            "\n",
+            "2.11.44. Finished OPT passes. (There is nothing left to do.)\n",
+            "\n",
+            "2.12. Executing FSM pass (extract and optimize FSM).\n",
+            "\n",
+            "2.12.1. Executing FSM_DETECT pass (finding FSMs in design).\n",
+            "\n",
+            "2.12.2. Executing FSM_EXTRACT pass (extracting FSM from design).\n",
+            "\n",
+            "2.12.3. Executing FSM_OPT pass (simple optimizations of FSMs).\n",
+            "\n",
+            "2.12.4. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\func_polynomial..\n",
+            "\n",
+            "2.12.5. Executing FSM_OPT pass (simple optimizations of FSMs).\n",
+            "\n",
+            "2.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).\n",
+            "\n",
+            "2.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells).\n",
+            "\n",
+            "2.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic).\n",
+            "\n",
+            "2.13. Executing OPT pass (performing simple optimizations).\n",
+            "\n",
+            "2.13.1. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module func_polynomial.\n",
+            "\n",
+            "2.13.2. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\func_polynomial'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "2.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n",
+            "Running muxtree optimizer on module \\func_polynomial..\n",
+            "  Creating internal representation of mux trees.\n",
+            "  Evaluating internal representation of mux trees.\n",
+            "  Analyzing evaluation results.\n",
+            "Removed 0 multiplexer ports.\n",
+            "\n",
+            "2.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n",
+            "  Optimizing cells in module \\func_polynomial.\n",
+            "Performed a total of 0 changes.\n",
+            "\n",
+            "2.13.5. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\func_polynomial'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "2.13.6. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "2.13.7. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\func_polynomial..\n",
+            "\n",
+            "2.13.8. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module func_polynomial.\n",
+            "\n",
+            "2.13.9. Finished OPT passes. (There is nothing left to do.)\n",
+            "\n",
+            "2.14. Executing WREDUCE pass (reducing word size of cells).\n",
+            "Removed top 20 bits (of 72) from port B of cell func_polynomial.$sub$projf-explore/maths/demo/func_polynomial.sv:45$386 ($sub).\n",
+            "Removed top 30 bits (of 48) from FF cell func_polynomial.$auto$ff.cc:262:slice$466 ($dff).\n",
+            "Removed top 31 bits (of 32) from mux cell func_polynomial.$ternary$projf-explore/maths/demo/func_polynomial.sv:46$388 ($mux).\n",
+            "Removed top 30 bits (of 48) from FF cell func_polynomial.$auto$ff.cc:262:slice$467 ($dff).\n",
+            "Removed top 30 bits (of 48) from FF cell func_polynomial.$auto$ff.cc:262:slice$468 ($dff).\n",
+            "Removed top 30 bits (of 48) from FF cell func_polynomial.$auto$ff.cc:262:slice$469 ($dff).\n",
+            "Removed top 30 bits (of 48) from FF cell func_polynomial.$auto$ff.cc:262:slice$470 ($dff).\n",
+            "Removed top 30 bits (of 72) from port B of cell func_polynomial.$lt$projf-explore/maths/demo/func_polynomial.sv:46$387 ($lt).\n",
+            "\n",
+            "2.15. Executing PEEPOPT pass (run peephole optimizers).\n",
+            "\n",
+            "2.16. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\func_polynomial..\n",
+            "Removed 0 unused cells and 1 unused wires.\n",
+            "\n",
+            "2.17. Executing SHARE pass (SAT-based resource sharing).\n",
+            "\n",
+            "2.18. Executing TECHMAP pass (map to technology primitives).\n",
+            "\n",
+            "2.18.1. Executing Verilog-2005 frontend: /content/miniconda-pnr/bin/../share/yosys/cmp2lut.v\n",
+            "Parsing Verilog input from `/content/miniconda-pnr/bin/../share/yosys/cmp2lut.v' to AST representation.\n",
+            "Generating RTLIL representation for module `\\_90_lut_cmp_'.\n",
+            "Successfully finished Verilog frontend.\n",
+            "\n",
+            "2.18.2. Continuing TECHMAP pass.\n",
+            "No more expansions possible.\n",
+            "\n",
+            "2.19. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module func_polynomial.\n",
+            "\n",
+            "2.20. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\func_polynomial..\n",
+            "\n",
+            "2.21. Executing ALUMACC pass (create $alu and $macc cells).\n",
+            "Extracting $alu and $macc cells in module func_polynomial:\n",
+            "  creating $macc model for $mul$projf-explore/maths/demo/func_polynomial.sv:37$383 ($mul).\n",
+            "  creating $macc model for $mul$projf-explore/maths/demo/func_polynomial.sv:42$384 ($mul).\n",
+            "  creating $macc model for $sub$projf-explore/maths/demo/func_polynomial.sv:45$386 ($sub).\n",
+            "  creating $alu model for $macc $sub$projf-explore/maths/demo/func_polynomial.sv:45$386.\n",
+            "  creating $macc cell for $mul$projf-explore/maths/demo/func_polynomial.sv:42$384: $auto$alumacc.cc:365:replace_macc$472\n",
+            "  creating $macc cell for $mul$projf-explore/maths/demo/func_polynomial.sv:37$383: $auto$alumacc.cc:365:replace_macc$473\n",
+            "  creating $alu model for $lt$projf-explore/maths/demo/func_polynomial.sv:46$387 ($lt): new $alu\n",
+            "  creating $alu cell for $lt$projf-explore/maths/demo/func_polynomial.sv:46$387: $auto$alumacc.cc:485:replace_alu$475\n",
+            "  creating $alu cell for $sub$projf-explore/maths/demo/func_polynomial.sv:45$386: $auto$alumacc.cc:485:replace_alu$488\n",
+            "  created 2 $alu and 2 $macc cells.\n",
+            "\n",
+            "2.22. Executing OPT pass (performing simple optimizations).\n",
+            "\n",
+            "2.22.1. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module func_polynomial.\n",
+            "\n",
+            "2.22.2. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\func_polynomial'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "2.22.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n",
+            "Running muxtree optimizer on module \\func_polynomial..\n",
+            "  Creating internal representation of mux trees.\n",
+            "  Evaluating internal representation of mux trees.\n",
+            "  Analyzing evaluation results.\n",
+            "Removed 0 multiplexer ports.\n",
+            "\n",
+            "2.22.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n",
+            "  Optimizing cells in module \\func_polynomial.\n",
+            "Performed a total of 0 changes.\n",
+            "\n",
+            "2.22.5. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\func_polynomial'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "2.22.6. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "2.22.7. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\func_polynomial..\n",
+            "Removed 1 unused cells and 2 unused wires.\n",
+            "\n",
+            "2.22.8. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module func_polynomial.\n",
+            "\n",
+            "2.22.9. Rerunning OPT passes. (Maybe there is more to do..)\n",
+            "\n",
+            "2.22.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n",
+            "Running muxtree optimizer on module \\func_polynomial..\n",
+            "  Creating internal representation of mux trees.\n",
+            "  Evaluating internal representation of mux trees.\n",
+            "  Analyzing evaluation results.\n",
+            "Removed 0 multiplexer ports.\n",
+            "\n",
+            "2.22.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n",
+            "  Optimizing cells in module \\func_polynomial.\n",
+            "Performed a total of 0 changes.\n",
+            "\n",
+            "2.22.12. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\func_polynomial'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "2.22.13. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "2.22.14. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\func_polynomial..\n",
+            "\n",
+            "2.22.15. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module func_polynomial.\n",
+            "\n",
+            "2.22.16. Finished OPT passes. (There is nothing left to do.)\n",
+            "\n",
+            "2.23. Executing MEMORY pass.\n",
+            "\n",
+            "2.23.1. Executing OPT_MEM pass (optimize memories).\n",
+            "Performed a total of 0 transformations.\n",
+            "\n",
+            "2.23.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).\n",
+            "Performed a total of 0 transformations.\n",
+            "\n",
+            "2.23.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).\n",
+            "\n",
+            "2.23.4. Executing MEMORY_DFF pass (merging $dff cells to $memrd).\n",
+            "\n",
+            "2.23.5. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\func_polynomial..\n",
+            "\n",
+            "2.23.6. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).\n",
+            "\n",
+            "2.23.7. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).\n",
+            "Performed a total of 0 transformations.\n",
+            "\n",
+            "2.23.8. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\func_polynomial..\n",
+            "\n",
+            "2.23.9. Executing MEMORY_COLLECT pass (generating $mem cells).\n",
+            "\n",
+            "2.24. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\func_polynomial..\n",
+            "\n",
+            "2.25. Executing MEMORY_BRAM pass (mapping $mem cells to block memories).\n",
+            "\n",
+            "2.26. Executing TECHMAP pass (map to technology primitives).\n",
+            "\n",
+            "2.26.1. Executing Verilog-2005 frontend: /content/miniconda-pnr/bin/../share/yosys/ice40/brams_map.v\n",
+            "Parsing Verilog input from `/content/miniconda-pnr/bin/../share/yosys/ice40/brams_map.v' to AST representation.\n",
+            "Generating RTLIL representation for module `\\$__ICE40_RAM4K'.\n",
+            "Generating RTLIL representation for module `\\$__ICE40_RAM4K_M0'.\n",
+            "Generating RTLIL representation for module `\\$__ICE40_RAM4K_M123'.\n",
+            "Successfully finished Verilog frontend.\n",
+            "\n",
+            "2.26.2. Continuing TECHMAP pass.\n",
+            "No more expansions possible.\n",
+            "\n",
+            "2.27. Executing ICE40_BRAMINIT pass.\n",
+            "\n",
+            "2.28. Executing OPT pass (performing simple optimizations).\n",
+            "\n",
+            "2.28.1. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module func_polynomial.\n",
+            "\n",
+            "2.28.2. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\func_polynomial'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "2.28.3. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "2.28.4. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\func_polynomial..\n",
+            "Removed 16 unused cells and 16 unused wires.\n",
+            "\n",
+            "2.28.5. Finished fast OPT passes.\n",
+            "\n",
+            "2.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).\n",
+            "\n",
+            "2.30. Executing OPT pass (performing simple optimizations).\n",
+            "\n",
+            "2.30.1. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module func_polynomial.\n",
+            "\n",
+            "2.30.2. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\func_polynomial'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "2.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n",
+            "Running muxtree optimizer on module \\func_polynomial..\n",
+            "  Creating internal representation of mux trees.\n",
+            "  Evaluating internal representation of mux trees.\n",
+            "  Analyzing evaluation results.\n",
+            "Removed 0 multiplexer ports.\n",
+            "\n",
+            "2.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n",
+            "  Optimizing cells in module \\func_polynomial.\n",
+            "Performed a total of 0 changes.\n",
+            "\n",
+            "2.30.5. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\func_polynomial'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "2.30.6. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "2.30.7. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\func_polynomial..\n",
+            "\n",
+            "2.30.8. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module func_polynomial.\n",
+            "\n",
+            "2.30.9. Finished OPT passes. (There is nothing left to do.)\n",
+            "\n",
+            "2.31. Executing ICE40_WRAPCARRY pass (wrap carries).\n",
+            "\n",
+            "2.32. Executing TECHMAP pass (map to technology primitives).\n",
+            "\n",
+            "2.32.1. Executing Verilog-2005 frontend: /content/miniconda-pnr/bin/../share/yosys/techmap.v\n",
+            "Parsing Verilog input from `/content/miniconda-pnr/bin/../share/yosys/techmap.v' to AST representation.\n",
+            "Generating RTLIL representation for module `\\_90_simplemap_bool_ops'.\n",
+            "Generating RTLIL representation for module `\\_90_simplemap_reduce_ops'.\n",
+            "Generating RTLIL representation for module `\\_90_simplemap_logic_ops'.\n",
+            "Generating RTLIL representation for module `\\_90_simplemap_compare_ops'.\n",
+            "Generating RTLIL representation for module `\\_90_simplemap_various'.\n",
+            "Generating RTLIL representation for module `\\_90_simplemap_registers'.\n",
+            "Generating RTLIL representation for module `\\_90_shift_ops_shr_shl_sshl_sshr'.\n",
+            "Generating RTLIL representation for module `\\_90_shift_shiftx'.\n",
+            "Generating RTLIL representation for module `\\_90_fa'.\n",
+            "Generating RTLIL representation for module `\\_90_lcu'.\n",
+            "Generating RTLIL representation for module `\\_90_alu'.\n",
+            "Generating RTLIL representation for module `\\_90_macc'.\n",
+            "Generating RTLIL representation for module `\\_90_alumacc'.\n",
+            "Generating RTLIL representation for module `\\$__div_mod_u'.\n",
+            "Generating RTLIL representation for module `\\$__div_mod_trunc'.\n",
+            "Generating RTLIL representation for module `\\_90_div'.\n",
+            "Generating RTLIL representation for module `\\_90_mod'.\n",
+            "Generating RTLIL representation for module `\\$__div_mod_floor'.\n",
+            "Generating RTLIL representation for module `\\_90_divfloor'.\n",
+            "Generating RTLIL representation for module `\\_90_modfloor'.\n",
+            "Generating RTLIL representation for module `\\_90_pow'.\n",
+            "Generating RTLIL representation for module `\\_90_pmux'.\n",
+            "Generating RTLIL representation for module `\\_90_demux'.\n",
+            "Generating RTLIL representation for module `\\_90_lut'.\n",
+            "Successfully finished Verilog frontend.\n",
+            "\n",
+            "2.32.2. Executing Verilog-2005 frontend: /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v\n",
+            "Parsing Verilog input from `/content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v' to AST representation.\n",
+            "Generating RTLIL representation for module `\\_80_ice40_alu'.\n",
+            "Successfully finished Verilog frontend.\n",
+            "\n",
+            "2.32.3. Continuing TECHMAP pass.\n",
+            "Using extmapper simplemap for cells of type $or.\n",
+            "Using extmapper simplemap for cells of type $reduce_and.\n",
+            "Using template $paramod$c0f56a9acf88f08192699d673c978f22a6df720d\\_80_ice40_alu for cells of type $alu.\n",
+            "Using extmapper maccmap for cells of type $macc.\n",
+            "  add \\x * \\x (18x18 bits, signed)\n",
+            "Using extmapper simplemap for cells of type $xor.\n",
+            "Using extmapper simplemap for cells of type $dff.\n",
+            "Using template $paramod$5af13fe7b0f0a7b19eedc0ca5d6745996c3f09fc\\_80_ice40_alu for cells of type $alu.\n",
+            "Using extmapper simplemap for cells of type $mux.\n",
+            "  add \\x_squared_p2 * \\x_squared_p2 (36x36 bits, signed)\n",
+            "Using extmapper simplemap for cells of type $and.\n",
+            "Using extmapper simplemap for cells of type $not.\n",
+            "Using extmapper simplemap for cells of type $pos.\n",
+            "Using template $paramod\\_90_fa\\WIDTH=32'00000000000000000000000000100100 for cells of type $fa.\n",
+            "Using template $paramod$9fb24bf0faa43f804d3c379242188667e42c235c\\_80_ice40_alu for cells of type $alu.\n",
+            "Using template $paramod\\_90_fa\\WIDTH=32'00000000000000000000000001001000 for cells of type $fa.\n",
+            "Using template $paramod\\_90_fa\\WIDTH=32'00000000000000000000000001000111 for cells of type $fa.\n",
+            "Using template $paramod$4a36c8f54255b1e66b766d9531a976ba57da137e\\_80_ice40_alu for cells of type $alu.\n",
+            "No more expansions possible.\n",
+            "\n",
+            "2.33. Executing OPT pass (performing simple optimizations).\n",
+            "\n",
+            "2.33.1. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module func_polynomial.\n",
+            "\n",
+            "2.33.2. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\func_polynomial'.\n",
+            "Removed a total of 4622 cells.\n",
+            "\n",
+            "2.33.3. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "2.33.4. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\func_polynomial..\n",
+            "Removed 278 unused cells and 582 unused wires.\n",
+            "\n",
+            "2.33.5. Finished fast OPT passes.\n",
+            "\n",
+            "2.34. Executing ICE40_OPT pass (performing simple optimizations).\n",
+            "\n",
+            "2.34.1. Running ICE40 specific optimizations.\n",
+            "Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) func_polynomial.$auto$alumacc.cc:485:replace_alu$475.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$475.BB [0]\n",
+            "Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) func_polynomial.$auto$maccmap.cc:240:synth$777.slice[0].carry: CO=1'0\n",
+            "Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) func_polynomial.$auto$maccmap.cc:240:synth$983.slice[0].carry: CO=1'0\n",
+            "\n",
+            "2.34.2. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module func_polynomial.\n",
+            "\n",
+            "2.34.3. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\func_polynomial'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "2.34.4. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "2.34.5. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\func_polynomial..\n",
+            "Removed 1 unused cells and 0 unused wires.\n",
+            "\n",
+            "2.34.6. Rerunning OPT passes. (Removed registers in this run.)\n",
+            "\n",
+            "2.34.7. Running ICE40 specific optimizations.\n",
+            "Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) func_polynomial.$auto$maccmap.cc:240:synth$777.slice[1].carry: CO=1'0\n",
+            "Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) func_polynomial.$auto$maccmap.cc:240:synth$983.slice[1].carry: CO=1'0\n",
+            "\n",
+            "2.34.8. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module func_polynomial.\n",
+            "\n",
+            "2.34.9. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\func_polynomial'.\n",
+            "Removed a total of 4 cells.\n",
+            "\n",
+            "2.34.10. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "2.34.11. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\func_polynomial..\n",
+            "\n",
+            "2.34.12. Rerunning OPT passes. (Removed registers in this run.)\n",
+            "\n",
+            "2.34.13. Running ICE40 specific optimizations.\n",
+            "Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) func_polynomial.$auto$maccmap.cc:240:synth$777.slice[2].carry: CO=1'0\n",
+            "Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) func_polynomial.$auto$maccmap.cc:240:synth$983.slice[2].carry: CO=1'0\n",
+            "\n",
+            "2.34.14. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module func_polynomial.\n",
+            "\n",
+            "2.34.15. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\func_polynomial'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "2.34.16. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "2.34.17. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\func_polynomial..\n",
+            "\n",
+            "2.34.18. Rerunning OPT passes. (Removed registers in this run.)\n",
+            "\n",
+            "2.34.19. Running ICE40 specific optimizations.\n",
+            "Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) func_polynomial.$auto$maccmap.cc:240:synth$777.slice[3].carry: CO=1'0\n",
+            "Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) func_polynomial.$auto$maccmap.cc:240:synth$983.slice[3].carry: CO=1'0\n",
+            "\n",
+            "2.34.20. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module func_polynomial.\n",
+            "\n",
+            "2.34.21. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\func_polynomial'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "2.34.22. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "2.34.23. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\func_polynomial..\n",
+            "\n",
+            "2.34.24. Rerunning OPT passes. (Removed registers in this run.)\n",
+            "\n",
+            "2.34.25. Running ICE40 specific optimizations.\n",
+            "Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) func_polynomial.$auto$maccmap.cc:240:synth$777.slice[4].carry: CO=1'0\n",
+            "Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) func_polynomial.$auto$maccmap.cc:240:synth$983.slice[4].carry: CO=1'0\n",
+            "\n",
+            "2.34.26. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module func_polynomial.\n",
+            "\n",
+            "2.34.27. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\func_polynomial'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "2.34.28. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "2.34.29. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\func_polynomial..\n",
+            "\n",
+            "2.34.30. Rerunning OPT passes. (Removed registers in this run.)\n",
+            "\n",
+            "2.34.31. Running ICE40 specific optimizations.\n",
+            "Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) func_polynomial.$auto$maccmap.cc:240:synth$777.slice[5].carry: CO=1'0\n",
+            "Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) func_polynomial.$auto$maccmap.cc:240:synth$983.slice[5].carry: CO=1'0\n",
+            "\n",
+            "2.34.32. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module func_polynomial.\n",
+            "\n",
+            "2.34.33. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\func_polynomial'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "2.34.34. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "2.34.35. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\func_polynomial..\n",
+            "\n",
+            "2.34.36. Rerunning OPT passes. (Removed registers in this run.)\n",
+            "\n",
+            "2.34.37. Running ICE40 specific optimizations.\n",
+            "Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) func_polynomial.$auto$maccmap.cc:240:synth$983.slice[6].carry: CO=1'0\n",
+            "\n",
+            "2.34.38. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module func_polynomial.\n",
+            "\n",
+            "2.34.39. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\func_polynomial'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "2.34.40. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "2.34.41. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\func_polynomial..\n",
+            "\n",
+            "2.34.42. Rerunning OPT passes. (Removed registers in this run.)\n",
+            "\n",
+            "2.34.43. Running ICE40 specific optimizations.\n",
+            "Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) func_polynomial.$auto$maccmap.cc:240:synth$983.slice[7].carry: CO=1'0\n",
+            "\n",
+            "2.34.44. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module func_polynomial.\n",
+            "\n",
+            "2.34.45. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\func_polynomial'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "2.34.46. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "2.34.47. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\func_polynomial..\n",
+            "\n",
+            "2.34.48. Rerunning OPT passes. (Removed registers in this run.)\n",
+            "\n",
+            "2.34.49. Running ICE40 specific optimizations.\n",
+            "\n",
+            "2.34.50. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module func_polynomial.\n",
+            "\n",
+            "2.34.51. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\func_polynomial'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "2.34.52. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "2.34.53. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\func_polynomial..\n",
+            "\n",
+            "2.34.54. Finished OPT passes. (There is nothing left to do.)\n",
+            "\n",
+            "2.35. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).\n",
+            "\n",
+            "2.36. Executing TECHMAP pass (map to technology primitives).\n",
+            "\n",
+            "2.36.1. Executing Verilog-2005 frontend: /content/miniconda-pnr/bin/../share/yosys/ice40/ff_map.v\n",
+            "Parsing Verilog input from `/content/miniconda-pnr/bin/../share/yosys/ice40/ff_map.v' to AST representation.\n",
+            "Generating RTLIL representation for module `\\$_DFF_N_'.\n",
+            "Generating RTLIL representation for module `\\$_DFF_P_'.\n",
+            "Generating RTLIL representation for module `\\$_DFFE_NP_'.\n",
+            "Generating RTLIL representation for module `\\$_DFFE_PP_'.\n",
+            "Generating RTLIL representation for module `\\$_DFF_NP0_'.\n",
+            "Generating RTLIL representation for module `\\$_DFF_NP1_'.\n",
+            "Generating RTLIL representation for module `\\$_DFF_PP0_'.\n",
+            "Generating RTLIL representation for module `\\$_DFF_PP1_'.\n",
+            "Generating RTLIL representation for module `\\$_DFFE_NP0P_'.\n",
+            "Generating RTLIL representation for module `\\$_DFFE_NP1P_'.\n",
+            "Generating RTLIL representation for module `\\$_DFFE_PP0P_'.\n",
+            "Generating RTLIL representation for module `\\$_DFFE_PP1P_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFF_NP0_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFF_NP1_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFF_PP0_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFF_PP1_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFFCE_NP0P_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFFCE_NP1P_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFFCE_PP0P_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFFCE_PP1P_'.\n",
+            "Successfully finished Verilog frontend.\n",
+            "\n",
+            "2.36.2. Continuing TECHMAP pass.\n",
+            "Using template \\$_DFF_P_ for cells of type $_DFF_P_.\n",
+            "No more expansions possible.\n",
+            "\n",
+            "2.37. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module func_polynomial.\n",
+            "\n",
+            "2.38. Executing SIMPLEMAP pass (map simple cells to gate primitives).\n",
+            "Mapping func_polynomial.$auto$maccmap.cc:240:synth$777.slice[0].carry ($lut).\n",
+            "Mapping func_polynomial.$auto$maccmap.cc:240:synth$777.slice[1].carry ($lut).\n",
+            "Mapping func_polynomial.$auto$maccmap.cc:240:synth$777.slice[2].carry ($lut).\n",
+            "Mapping func_polynomial.$auto$maccmap.cc:240:synth$777.slice[3].carry ($lut).\n",
+            "Mapping func_polynomial.$auto$maccmap.cc:240:synth$777.slice[4].carry ($lut).\n",
+            "Mapping func_polynomial.$auto$maccmap.cc:240:synth$777.slice[5].carry ($lut).\n",
+            "Mapping func_polynomial.$auto$maccmap.cc:240:synth$983.slice[0].carry ($lut).\n",
+            "Mapping func_polynomial.$auto$maccmap.cc:240:synth$983.slice[2].carry ($lut).\n",
+            "Mapping func_polynomial.$auto$maccmap.cc:240:synth$983.slice[3].carry ($lut).\n",
+            "Mapping func_polynomial.$auto$maccmap.cc:240:synth$983.slice[4].carry ($lut).\n",
+            "Mapping func_polynomial.$auto$maccmap.cc:240:synth$983.slice[5].carry ($lut).\n",
+            "Mapping func_polynomial.$auto$maccmap.cc:240:synth$983.slice[6].carry ($lut).\n",
+            "Mapping func_polynomial.$auto$maccmap.cc:240:synth$983.slice[7].carry ($lut).\n",
+            "\n",
+            "2.39. Executing ICE40_OPT pass (performing simple optimizations).\n",
+            "\n",
+            "2.39.1. Running ICE40 specific optimizations.\n",
+            "\n",
+            "2.39.2. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module func_polynomial.\n",
+            "\n",
+            "2.39.3. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\func_polynomial'.\n",
+            "Removed a total of 14 cells.\n",
+            "\n",
+            "2.39.4. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "2.39.5. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\func_polynomial..\n",
+            "Removed 10 unused cells and 1844 unused wires.\n",
+            "\n",
+            "2.39.6. Rerunning OPT passes. (Removed registers in this run.)\n",
+            "\n",
+            "2.39.7. Running ICE40 specific optimizations.\n",
+            "\n",
+            "2.39.8. Executing OPT_EXPR pass (perform const folding).\n",
+            "Optimizing module func_polynomial.\n",
+            "\n",
+            "2.39.9. Executing OPT_MERGE pass (detect identical cells).\n",
+            "Finding identical cells in module `\\func_polynomial'.\n",
+            "Removed a total of 0 cells.\n",
+            "\n",
+            "2.39.10. Executing OPT_DFF pass (perform DFF optimizations).\n",
+            "\n",
+            "2.39.11. Executing OPT_CLEAN pass (remove unused cells and wires).\n",
+            "Finding unused cells or wires in module \\func_polynomial..\n",
+            "\n",
+            "2.39.12. Finished OPT passes. (There is nothing left to do.)\n",
+            "\n",
+            "2.40. Executing TECHMAP pass (map to technology primitives).\n",
+            "\n",
+            "2.40.1. Executing Verilog-2005 frontend: /content/miniconda-pnr/bin/../share/yosys/ice40/latches_map.v\n",
+            "Parsing Verilog input from `/content/miniconda-pnr/bin/../share/yosys/ice40/latches_map.v' to AST representation.\n",
+            "Generating RTLIL representation for module `\\$_DLATCH_N_'.\n",
+            "Generating RTLIL representation for module `\\$_DLATCH_P_'.\n",
+            "Successfully finished Verilog frontend.\n",
+            "\n",
+            "2.40.2. Continuing TECHMAP pass.\n",
+            "No more expansions possible.\n",
+            "\n",
+            "2.41. Executing ABC pass (technology mapping using ABC).\n",
+            "\n",
+            "2.41.1. Extracting gate netlist of module `\\func_polynomial' to `<abc-temp-dir>/input.blif'..\n",
+            "Extracted 9381 gates and 9564 wires to a netlist network with 183 inputs and 307 outputs.\n",
+            "\n",
+            "2.41.1.1. Executing ABC.\n",
+            "Running ABC command: <yosys-exe-dir>/yosys-abc -s -f <abc-temp-dir>/abc.script 2>&1\n",
+            "ABC: ABC command line: \"source <abc-temp-dir>/abc.script\".\n",
+            "ABC: \n",
+            "ABC: + read_blif <abc-temp-dir>/input.blif \n",
+            "ABC: + read_lut <abc-temp-dir>/lutdefs.txt \n",
+            "ABC: + strash \n",
+            "ABC: + ifraig \n",
+            "ABC: + scorr \n",
+            "ABC: Warning: The network is combinational (run \"fraig\" or \"fraig_sweep\").\n",
+            "ABC: + dc2 \n",
+            "ABC: + dretime \n",
+            "ABC: + strash \n",
+            "ABC: + dch -f \n",
+            "ABC: + if \n",
+            "ABC: + mfs2 \n",
+            "ABC: + lutpack -S 1 \n",
+            "ABC: + dress \n",
+            "ABC: Total number of equiv classes                =    4005.\n",
+            "ABC: Participating nodes from both networks       =    8105.\n",
+            "ABC: Participating nodes from the first network   =    4006. (  98.55 % of nodes)\n",
+            "ABC: Participating nodes from the second network  =    4099. ( 100.84 % of nodes)\n",
+            "ABC: Node pairs (any polarity)                    =    4004. (  98.50 % of names can be moved)\n",
+            "ABC: Node pairs (same polarity)                   =    2636. (  64.85 % of names can be moved)\n",
+            "ABC: Total runtime =     0.31 sec\n",
+            "ABC: + write_blif <abc-temp-dir>/output.blif \n",
+            "\n",
+            "2.41.1.2. Re-integrating ABC results.\n",
+            "ABC RESULTS:              $lut cells:     4062\n",
+            "ABC RESULTS:        internal signals:     9074\n",
+            "ABC RESULTS:           input signals:      183\n",
+            "ABC RESULTS:          output signals:      307\n",
+            "Removing temp directory.\n",
+            "\n",
+            "2.42. Executing ICE40_WRAPCARRY pass (wrap carries).\n",
+            "\n",
+            "2.43. Executing TECHMAP pass (map to technology primitives).\n",
+            "\n",
+            "2.43.1. Executing Verilog-2005 frontend: /content/miniconda-pnr/bin/../share/yosys/ice40/ff_map.v\n",
+            "Parsing Verilog input from `/content/miniconda-pnr/bin/../share/yosys/ice40/ff_map.v' to AST representation.\n",
+            "Generating RTLIL representation for module `\\$_DFF_N_'.\n",
+            "Generating RTLIL representation for module `\\$_DFF_P_'.\n",
+            "Generating RTLIL representation for module `\\$_DFFE_NP_'.\n",
+            "Generating RTLIL representation for module `\\$_DFFE_PP_'.\n",
+            "Generating RTLIL representation for module `\\$_DFF_NP0_'.\n",
+            "Generating RTLIL representation for module `\\$_DFF_NP1_'.\n",
+            "Generating RTLIL representation for module `\\$_DFF_PP0_'.\n",
+            "Generating RTLIL representation for module `\\$_DFF_PP1_'.\n",
+            "Generating RTLIL representation for module `\\$_DFFE_NP0P_'.\n",
+            "Generating RTLIL representation for module `\\$_DFFE_NP1P_'.\n",
+            "Generating RTLIL representation for module `\\$_DFFE_PP0P_'.\n",
+            "Generating RTLIL representation for module `\\$_DFFE_PP1P_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFF_NP0_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFF_NP1_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFF_PP0_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFF_PP1_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFFCE_NP0P_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFFCE_NP1P_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFFCE_PP0P_'.\n",
+            "Generating RTLIL representation for module `\\$_SDFFCE_PP1P_'.\n",
+            "Successfully finished Verilog frontend.\n",
+            "\n",
+            "2.43.2. Continuing TECHMAP pass.\n",
+            "No more expansions possible.\n",
+            "Removed 73 unused cells and 810 unused wires.\n",
+            "\n",
+            "2.44. Executing OPT_LUT pass (optimize LUTs).\n",
+            "Discovering LUTs.\n",
+            "Number of LUTs:     4213\n",
+            "  1-LUT              108\n",
+            "  2-LUT              794\n",
+            "  3-LUT             1927\n",
+            "  4-LUT             1384\n",
+            "  with \\SB_CARRY    (#0)  148\n",
+            "  with \\SB_CARRY    (#1)  148\n",
+            "\n",
+            "Eliminating LUTs.\n",
+            "Number of LUTs:     4213\n",
+            "  1-LUT              108\n",
+            "  2-LUT              794\n",
+            "  3-LUT             1927\n",
+            "  4-LUT             1384\n",
+            "  with \\SB_CARRY    (#0)  148\n",
+            "  with \\SB_CARRY    (#1)  148\n",
+            "\n",
+            "Combining LUTs.\n",
+            "Number of LUTs:     4212\n",
+            "  1-LUT              108\n",
+            "  2-LUT              794\n",
+            "  3-LUT             1925\n",
+            "  4-LUT             1385\n",
+            "  with \\SB_CARRY    (#0)  148\n",
+            "  with \\SB_CARRY    (#1)  148\n",
+            "\n",
+            "Eliminated 0 LUTs.\n",
+            "Combined 1 LUTs.\n",
+            "\n",
+            "2.45. Executing TECHMAP pass (map to technology primitives).\n",
+            "\n",
+            "2.45.1. Executing Verilog-2005 frontend: /content/miniconda-pnr/bin/../share/yosys/ice40/cells_map.v\n",
+            "Parsing Verilog input from `/content/miniconda-pnr/bin/../share/yosys/ice40/cells_map.v' to AST representation.\n",
+            "Generating RTLIL representation for module `\\$lut'.\n",
+            "Successfully finished Verilog frontend.\n",
+            "\n",
+            "2.45.2. Continuing TECHMAP pass.\n",
+            "Using template $paramod\\$lut\\WIDTH=32'00000000000000000000000000000010\\LUT=4'1000 for cells of type $lut.\n",
+            "Using template $paramod$deba17538f4cd4af4a7f03bc51507e8ef8b1d7d8\\$lut for cells of type $lut.\n",
+            "Using template $paramod\\$lut\\WIDTH=32'00000000000000000000000000000010\\LUT=4'0110 for cells of type $lut.\n",
+            "Using template $paramod\\$lut\\WIDTH=32'00000000000000000000000000000011\\LUT=8'01111000 for cells of type $lut.\n",
+            "Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9\\$lut for cells of type $lut.\n",
+            "Using template $paramod$82b4a585d1edcb5c6e755dc9bd3392228a1c1304\\$lut for cells of type $lut.\n",
+            "Using template $paramod$4282def8dbd6df3d1248ad282c629bee684502c2\\$lut for cells of type $lut.\n",
+            "Using template $paramod$cb92beff9eab733e7181d891fbc8c3950b9abc0a\\$lut for cells of type $lut.\n",
+            "Using template $paramod\\$lut\\WIDTH=32'00000000000000000000000000000011\\LUT=8'00010111 for cells of type $lut.\n",
+            "Using template $paramod\\$lut\\WIDTH=32'00000000000000000000000000000011\\LUT=8'10010110 for cells of type $lut.\n",
+            "Using template $paramod$78e1751931755f088c8bc676bcbc3bb642c26bfc\\$lut for cells of type $lut.\n",
+            "Using template $paramod\\$lut\\WIDTH=32'00000000000000000000000000000011\\LUT=8'10000000 for cells of type $lut.\n",
+            "Using template $paramod\\$lut\\WIDTH=32'00000000000000000000000000000011\\LUT=8'00000111 for cells of type $lut.\n",
+            "Using template $paramod$e5cb8e913f4daae476fde2b364998f21967f1f08\\$lut for cells of type $lut.\n",
+            "Using template $paramod\\$lut\\WIDTH=32'00000000000000000000000000000011\\LUT=8'01101001 for cells of type $lut.\n",
+            "Using template $paramod\\$lut\\WIDTH=32'00000000000000000000000000000011\\LUT=8'00101011 for cells of type $lut.\n",
+            "Using template $paramod\\$lut\\WIDTH=32'00000000000000000000000000000011\\LUT=8'10110010 for cells of type $lut.\n",
+            "Using template $paramod$b66cde2bcb2928dc1b0156b3a12a8631bfc32d9e\\$lut for cells of type $lut.\n",
+            "Using template $paramod\\$lut\\WIDTH=32'00000000000000000000000000000011\\LUT=8'01110001 for cells of type $lut.\n",
+            "Using template $paramod\\$lut\\WIDTH=32'00000000000000000000000000000011\\LUT=8'11010100 for cells of type $lut.\n",
+            "Using template $paramod\\$lut\\WIDTH=32'00000000000000000000000000000011\\LUT=8'10000111 for cells of type $lut.\n",
+            "Using template $paramod\\$lut\\WIDTH=32'00000000000000000000000000000010\\LUT=4'0100 for cells of type $lut.\n",
+            "Using template $paramod$fd904e9e35cfd343a9df248824bd3f1408724879\\$lut for cells of type $lut.\n",
+            "Using template $paramod\\$lut\\WIDTH=32'00000000000000000000000000000011\\LUT=8'01000000 for cells of type $lut.\n",
+            "Using template $paramod$868427562418b5dc988caeac6a54689ec9c9025e\\$lut for cells of type $lut.\n",
+            "Using template $paramod\\$lut\\WIDTH=32'00000000000000000000000000000011\\LUT=8'01001111 for cells of type $lut.\n",
+            "Using template $paramod$89ce1067ddd7d1b862c35a14cf05e043d151c807\\$lut for cells of type $lut.\n",
+            "Using template $paramod$fde34d7b7d817d093917fab37479be42cf9a4427\\$lut for cells of type $lut.\n",
+            "Using template $paramod$e56d99447d8a3ece8eda45209ed4b9fdcdbf8d26\\$lut for cells of type $lut.\n",
+            "Using template $paramod$06b5f7e5a17024622a77ecd9b5b6f113e0b34c96\\$lut for cells of type $lut.\n",
+            "Using template $paramod\\$lut\\WIDTH=32'00000000000000000000000000000011\\LUT=8'01100000 for cells of type $lut.\n",
+            "Using template $paramod$9843d77d4773ab424562cc9655d50a1bc2125488\\$lut for cells of type $lut.\n",
+            "Using template $paramod$4adb41216162ad4c68ce9ea5c48385c753262ac3\\$lut for cells of type $lut.\n",
+            "Using template $paramod$608f40069c27841a5b3bdf03643a34bdc8974072\\$lut for cells of type $lut.\n",
+            "Using template $paramod$50b99034fbf984a51c265442496081454147f31e\\$lut for cells of type $lut.\n",
+            "Using template $paramod$6d23198eb2b8f79a41c7626605a61009695893b1\\$lut for cells of type $lut.\n",
+            "Using template $paramod$af2b970363478c934f632261f05f42c59b0d7a99\\$lut for cells of type $lut.\n",
+            "Using template $paramod\\$lut\\WIDTH=32'00000000000000000000000000000010\\LUT=4'1001 for cells of type $lut.\n",
+            "Using template $paramod\\$lut\\WIDTH=32'00000000000000000000000000000011\\LUT=8'01010011 for cells of type $lut.\n",
+            "Using template $paramod$acf49cb7bd2805dee4b4ebb218aa5924b1be7704\\$lut for cells of type $lut.\n",
+            "Using template $paramod$fceb3a526de44b8f6b38e567360f59f7cf5878fb\\$lut for cells of type $lut.\n",
+            "Using template $paramod$da2f95476331ffa2143f8212db8aff730de806a0\\$lut for cells of type $lut.\n",
+            "Using template $paramod$595b4955041ceff09e28d600fe79275c24ba9878\\$lut for cells of type $lut.\n",
+            "Using template $paramod$5b13d2ee598c87cdbe912286a35c6fd102e2087c\\$lut for cells of type $lut.\n",
+            "Using template $paramod$2e11c0e004fab0373ef80005c65c968bc830b55a\\$lut for cells of type $lut.\n",
+            "Using template $paramod$765dca61dbfa835dacf2a260c8a4c5a36939a046\\$lut for cells of type $lut.\n",
+            "Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8\\$lut for cells of type $lut.\n",
+            "Using template $paramod$0e573fd81731047abcc72636166e5369d25058dc\\$lut for cells of type $lut.\n",
+            "Using template $paramod$041aa1dcdd60d3c4ff6eb6326c9e544a0334c607\\$lut for cells of type $lut.\n",
+            "Using template $paramod\\$lut\\WIDTH=32'00000000000000000000000000000011\\LUT=8'10101100 for cells of type $lut.\n",
+            "Using template $paramod\\$lut\\WIDTH=32'00000000000000000000000000000011\\LUT=8'10110100 for cells of type $lut.\n",
+            "Using template $paramod$c46e26e5a927423cd46556d9948ab62bff492185\\$lut for cells of type $lut.\n",
+            "Using template $paramod\\$lut\\WIDTH=32'00000000000000000000000000000011\\LUT=8'10100011 for cells of type $lut.\n",
+            "Using template $paramod$24ced899438e172604a424008974634c832673b7\\$lut for cells of type $lut.\n",
+            "Using template $paramod$33af9a654d0d8767ce4253c1bfd82206f064cd49\\$lut for cells of type $lut.\n",
+            "Using template $paramod\\$lut\\WIDTH=32'00000000000000000000000000000011\\LUT=8'00011111 for cells of type $lut.\n",
+            "Using template $paramod$80cbd08923107235732b36a5d5a7181977144217\\$lut for cells of type $lut.\n",
+            "Using template $paramod$956157c0497c969d2ee7549e519f18a7bb88f829\\$lut for cells of type $lut.\n",
+            "Using template $paramod$b46331eec3d08a7fe32e060d0598dc549c2cbdf3\\$lut for cells of type $lut.\n",
+            "Using template $paramod$856c0dcb815917dd823d16c42afb9313717d987b\\$lut for cells of type $lut.\n",
+            "Using template $paramod$ecf9cac817e9cbb222dc9e58a122faf05f34c860\\$lut for cells of type $lut.\n",
+            "Using template $paramod$1f3b67373a23476b64a6ed61bde9dbe9df1086de\\$lut for cells of type $lut.\n",
+            "Using template $paramod$b383ebb0e38b07c1d30fbe36272f5349936909f1\\$lut for cells of type $lut.\n",
+            "Using template $paramod$014b659db5d002405936b374e32d204782099707\\$lut for cells of type $lut.\n",
+            "Using template $paramod$19232694b104ec9f70ceb28797a5ac59e9b4cb1a\\$lut for cells of type $lut.\n",
+            "Using template $paramod$44b90213621c1b4a9fa338f7f73c0da64fb66683\\$lut for cells of type $lut.\n",
+            "Using template $paramod\\$lut\\WIDTH=32'00000000000000000000000000000011\\LUT=8'01011100 for cells of type $lut.\n",
+            "Using template $paramod$e96de5e9fcce737e52eacf39c70c8f533dc27d63\\$lut for cells of type $lut.\n",
+            "Using template $paramod$59ad7643a6592a7af331878e9c90559a0d5892f1\\$lut for cells of type $lut.\n",
+            "Using template $paramod$5858bd6d78d6f4fef506811d9419710ec77e5fb5\\$lut for cells of type $lut.\n",
+            "Using template $paramod$59c595af41d4a5cce2d588c3a5f1342749ce7a77\\$lut for cells of type $lut.\n",
+            "Using template $paramod\\$lut\\WIDTH=32'00000000000000000000000000000011\\LUT=8'00101100 for cells of type $lut.\n",
+            "Using template $paramod$d2cb3fa3211a237a33b845a7f5896365de15b614\\$lut for cells of type $lut.\n",
+            "Using template $paramod$2bdfdda73873e8931790d872b72220895e67fee5\\$lut for cells of type $lut.\n",
+            "Using template $paramod\\$lut\\WIDTH=32'00000000000000000000000000000011\\LUT=8'01101011 for cells of type $lut.\n",
+            "Using template $paramod\\$lut\\WIDTH=32'00000000000000000000000000000011\\LUT=8'00001011 for cells of type $lut.\n",
+            "Using template $paramod\\$lut\\WIDTH=32'00000000000000000000000000000010\\LUT=4'0001 for cells of type $lut.\n",
+            "Using template $paramod$834c4e678d55a2d8d648671fa29a5046863df970\\$lut for cells of type $lut.\n",
+            "Using template $paramod$f937daccc17291d2aa6011fab6a99ceaa05cec61\\$lut for cells of type $lut.\n",
+            "Using template $paramod\\$lut\\WIDTH=32'00000000000000000000000000000011\\LUT=8'11100001 for cells of type $lut.\n",
+            "Using template $paramod$a00e45534d91000c8af437243b8a7841b9c3a7af\\$lut for cells of type $lut.\n",
+            "Using template $paramod$c227f721a44fefdada39f6c9acbbd79680d6e12a\\$lut for cells of type $lut.\n",
+            "Using template $paramod\\$lut\\WIDTH=32'00000000000000000000000000000011\\LUT=8'11100111 for cells of type $lut.\n",
+            "Using template $paramod\\$lut\\WIDTH=32'00000000000000000000000000000011\\LUT=8'01000001 for cells of type $lut.\n",
+            "Using template $paramod$c9994e2a733aa21e4bfe57075af37a9c5257c791\\$lut for cells of type $lut.\n",
+            "Using template $paramod\\$lut\\WIDTH=32'00000000000000000000000000000011\\LUT=8'00010000 for cells of type $lut.\n",
+            "Using template $paramod\\$lut\\WIDTH=32'00000000000000000000000000000011\\LUT=8'01000010 for cells of type $lut.\n",
+            "Using template $paramod$7175be614d14889125b95ab0c63846496536dfa8\\$lut for cells of type $lut.\n",
+            "Using template $paramod$69f20e0703606f2ffd2ee27cd26f815bd5eeb6e9\\$lut for cells of type $lut.\n",
+            "Using template $paramod$ef0b432d3f28f1d8b2d96b9802ce965bc4504ebd\\$lut for cells of type $lut.\n",
+            "Using template $paramod$8466aae7f3132f822e70bbd8738850d820750479\\$lut for cells of type $lut.\n",
+            "Using template $paramod$7f88ae8b0ca78f7b736f446522956805c49fb79f\\$lut for cells of type $lut.\n",
+            "Using template $paramod$ddbfe91e78a83b872610cd39ca850c170dfcacd5\\$lut for cells of type $lut.\n",
+            "Using template $paramod$e628c2a8d9b1fa44d10e1de24bfb8e31bf8a4ac6\\$lut for cells of type $lut.\n",
+            "Using template $paramod\\$lut\\WIDTH=32'00000000000000000000000000000011\\LUT=8'00000001 for cells of type $lut.\n",
+            "Using template $paramod$6382f7860648fdb6f8a8dc690c25a62882cc501b\\$lut for cells of type $lut.\n",
+            "Using template $paramod\\$lut\\WIDTH=32'00000000000000000000000000000011\\LUT=8'00111110 for cells of type $lut.\n",
+            "Using template $paramod$cc14edb43bcbbd83b718cef08414cb23048bb6d0\\$lut for cells of type $lut.\n",
+            "Using template $paramod$12618d2e4f24227d6f46ca347b63e1113d3c5831\\$lut for cells of type $lut.\n",
+            "Using template $paramod$56b03bb16189d0df5732f97659a58f26b0c9c41a\\$lut for cells of type $lut.\n",
+            "Using template $paramod$0cf69d223154b4a6209139daec3524052ac22dd1\\$lut for cells of type $lut.\n",
+            "Using template $paramod\\$lut\\WIDTH=32'00000000000000000000000000000011\\LUT=8'00010100 for cells of type $lut.\n",
+            "Using template $paramod$6c15da6150ce36eeff7fb8c09f7ef22f5448d679\\$lut for cells of type $lut.\n",
+            "Using template $paramod\\$lut\\WIDTH=32'00000000000000000000000000000011\\LUT=8'11101000 for cells of type $lut.\n",
+            "Using template $paramod$aa471ad16d82a5785a3cf3d18330169d6ba4059c\\$lut for cells of type $lut.\n",
+            "Using template $paramod$85b779ce5ab505dbf25e5e046fb43ca2b76b878b\\$lut for cells of type $lut.\n",
+            "Using template $paramod$a63d84c9dd26caf4e75c7cc2f6f70f64a5b14aa1\\$lut for cells of type $lut.\n",
+            "Using template $paramod$c3e1dc7b9e539f115f21c9fa61c94c4df05b91c1\\$lut for cells of type $lut.\n",
+            "Using template $paramod$f3e1547c4b47e64c590e75cf09078b2507c8cc75\\$lut for cells of type $lut.\n",
+            "Using template $paramod$e5f3577946f60d63352a885a0122ac782d653d41\\$lut for cells of type $lut.\n",
+            "Using template $paramod$4bd0e644fd52ebb3b742e9f12861aec7d7c3e8e0\\$lut for cells of type $lut.\n",
+            "Using template $paramod\\$lut\\WIDTH=32'00000000000000000000000000000011\\LUT=8'11001010 for cells of type $lut.\n",
+            "Using template $paramod\\$lut\\WIDTH=32'00000000000000000000000000000011\\LUT=8'11000101 for cells of type $lut.\n",
+            "Using template $paramod\\$lut\\WIDTH=32'00000000000000000000000000000011\\LUT=8'00001101 for cells of type $lut.\n",
+            "Using template $paramod$6ad1063397984b2b09aa574378f44b9f2ae1c5b3\\$lut for cells of type $lut.\n",
+            "Using template $paramod$2ea69c779d6c1b79ac5a87b0d1523c67d5628dba\\$lut for cells of type $lut.\n",
+            "Using template $paramod$e65922c95df426132605bfadd57bb20230b64c5b\\$lut for cells of type $lut.\n",
+            "Using template $paramod$19ec49f31a8d230a567aa44ce3ea81a03c101e2b\\$lut for cells of type $lut.\n",
+            "Using template $paramod\\$lut\\WIDTH=32'00000000000000000000000000000011\\LUT=8'00110101 for cells of type $lut.\n",
+            "Using template $paramod\\$lut\\WIDTH=32'00000000000000000000000000000011\\LUT=8'00011110 for cells of type $lut.\n",
+            "Using template $paramod$d9f27eda2527dfc96b6faafb7daca211d693a25f\\$lut for cells of type $lut.\n",
+            "Using template $paramod$1df41e75d8c1af4127c594b13f60ff058fd64e7e\\$lut for cells of type $lut.\n",
+            "Using template $paramod$dbcb26e27c75f5e65d4c2b3160bb46f311a2b796\\$lut for cells of type $lut.\n",
+            "Using template $paramod$98d40e23bb57d56e14345fb0942003de3e361f25\\$lut for cells of type $lut.\n",
+            "Using template $paramod$2f8e8b439f8a3b566e5f7e870c06f6dca60dc55e\\$lut for cells of type $lut.\n",
+            "Using template $paramod$d2c7fffa208b27f0a52dad610b0bcd12ab6fdc92\\$lut for cells of type $lut.\n",
+            "Using template $paramod$3e27c7f584657c61690dac9538f4900ce23f9010\\$lut for cells of type $lut.\n",
+            "Using template $paramod$1a64f21ea15b05b7fc930804a66f6689ebbd6394\\$lut for cells of type $lut.\n",
+            "Using template $paramod$46f6707869970ff81dfceda816a4ec7d9f0b7345\\$lut for cells of type $lut.\n",
+            "Using template $paramod$6a34cd5b50e324824168b4186d0b04ba5e83b039\\$lut for cells of type $lut.\n",
+            "Using template $paramod$f43e533b16c4b44c0f5eeb593a0196cce2e80c58\\$lut for cells of type $lut.\n",
+            "Using template $paramod$272652f6c6fbe9a75eff76e45cc7e2788835518b\\$lut for cells of type $lut.\n",
+            "Using template $paramod$b393e271363631e4b5d4a94a29e84bdf7307c261\\$lut for cells of type $lut.\n",
+            "Using template $paramod$ba05b8a1a425003df083aea0e69541f5cbdc68f2\\$lut for cells of type $lut.\n",
+            "Using template $paramod$baa939b0bd5b3e0c8760492528669bd58f640542\\$lut for cells of type $lut.\n",
+            "Using template $paramod$2d07c1a6c53c7b878509360922c4fa5ebedc3011\\$lut for cells of type $lut.\n",
+            "Using template $paramod$0a14d5e896aa3d4771d458c7bcc847abb47d8244\\$lut for cells of type $lut.\n",
+            "Using template $paramod$ebe302cf675f04f2cc698a4f6888fe67d7e9866d\\$lut for cells of type $lut.\n",
+            "Using template $paramod$df196ed0a1da5c4a58c5e08a1dac304fd3fccaab\\$lut for cells of type $lut.\n",
+            "Using template $paramod$052ca015f1400ebf950f85d5f181f7a5865c336c\\$lut for cells of type $lut.\n",
+            "Using template $paramod$90edf8d4fe439b92725b09f66e94b5afc9f35376\\$lut for cells of type $lut.\n",
+            "Using template $paramod$6e238df02989b317f10820a22773676e71120644\\$lut for cells of type $lut.\n",
+            "Using template $paramod\\$lut\\WIDTH=32'00000000000000000000000000000011\\LUT=8'10010000 for cells of type $lut.\n",
+            "Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8\\$lut for cells of type $lut.\n",
+            "Using template $paramod$76bb3f31cd516c9c55e657a0f044c647e3786880\\$lut for cells of type $lut.\n",
+            "Using template $paramod$d03f82bd2b5d8c5a0aa220358b4130134759138a\\$lut for cells of type $lut.\n",
+            "Using template $paramod\\$lut\\WIDTH=32'00000000000000000000000000000011\\LUT=8'00011000 for cells of type $lut.\n",
+            "Using template $paramod$3d6743674926ab55803009feb6cac14c4decae18\\$lut for cells of type $lut.\n",
+            "Using template $paramod$a15fd389a2f54cb7b94707b25934d226e68d9e2e\\$lut for cells of type $lut.\n",
+            "Using template $paramod\\$lut\\WIDTH=32'00000000000000000000000000000001\\LUT=2'01 for cells of type $lut.\n",
+            "Using template $paramod$fd2847bd008edd03070f42355fdb14fda0191818\\$lut for cells of type $lut.\n",
+            "Using template $paramod$ef6f9494c41321ef63579b1462fd44bdf781fd1c\\$lut for cells of type $lut.\n",
+            "Using template $paramod$6e3b22478ca21c5590744f2e30b92938c4d90996\\$lut for cells of type $lut.\n",
+            "Using template $paramod$f90239dab41c021bca0caaeb9b4595162a1d3311\\$lut for cells of type $lut.\n",
+            "Using template $paramod$2f47a7c8334cbb61bb53bd000efd5e22fa9b617a\\$lut for cells of type $lut.\n",
+            "Using template $paramod$665df91de7fbfc916c50a57bf5b5d17134c39513\\$lut for cells of type $lut.\n",
+            "Using template $paramod$ec731ba0b03f9a8c2f9a148aad53e934d7e8d215\\$lut for cells of type $lut.\n",
+            "Using template $paramod\\$lut\\WIDTH=32'00000000000000000000000000000011\\LUT=8'00111101 for cells of type $lut.\n",
+            "Using template $paramod$a9334a4926470ce1833f9252e5e465c7b1118e6b\\$lut for cells of type $lut.\n",
+            "No more expansions possible.\n",
+            "Removed 0 unused cells and 10544 unused wires.\n",
+            "\n",
+            "2.46. Executing AUTONAME pass.\n",
+            "Renamed 430456 objects in module func_polynomial (304 iterations).\n",
+            "\n",
+            "2.47. Executing HIERARCHY pass (managing design hierarchy).\n",
+            "\n",
+            "2.47.1. Analyzing design hierarchy..\n",
+            "Top module:  \\func_polynomial\n",
+            "\n",
+            "2.47.2. Analyzing design hierarchy..\n",
+            "Top module:  \\func_polynomial\n",
+            "Removed 0 unused modules.\n",
+            "\n",
+            "2.48. Printing statistics.\n",
+            "\n",
+            "=== func_polynomial ===\n",
+            "\n",
+            "   Number of wires:               1677\n",
+            "   Number of wire bits:           7393\n",
+            "   Number of public wires:        1677\n",
+            "   Number of public wire bits:    7393\n",
+            "   Number of memories:               0\n",
+            "   Number of memory bits:            0\n",
+            "   Number of processes:              0\n",
+            "   Number of cells:               4878\n",
+            "     SB_CARRY                      218\n",
+            "     SB_DFF                        448\n",
+            "     SB_LUT4                      4212\n",
+            "\n",
+            "2.49. Executing CHECK pass (checking for obvious problems).\n",
+            "Checking module func_polynomial...\n",
+            "Found and reported 0 problems.\n",
+            "\n",
+            "2.50. Executing JSON backend.\n",
+            "\n",
+            "End of script. Logfile hash: 176b5ecbc3, CPU: user 20.26s system 0.14s, MEM: 153.32 MB peak\n",
+            "Yosys 0.13+37 (git sha1 958c3a46a, x86_64-conda_cos6-linux-gnu-gcc 1.24.0.133_b0863d8_dirty -fvisibility-inlines-hidden -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -fdebug-prefix-map=/home/runner/work/conda-eda/conda-eda/workdir/conda-env/conda-bld/yosys_1644188991550/work=/usr/local/src/conda/yosys-0.13_39_g958c3a46a -fdebug-prefix-map=/content/miniconda-pnr=/usr/local/src/conda-prefix -fPIC -Os -fno-merge-constants)\n",
+            "Time spent: 26% 31x opt_expr (6 sec), 18% 1x abc (4 sec), ...\n",
+            "Warning: Use of default value for --package is deprecated. Please add '--package sg48' to arguments.\n",
+            "Warning: No PCF file specified; IO pins will be placed automatically\n",
+            "\n",
+            "Info: Packing constants..\n",
+            "Info: Packing IOs..\n",
+            "Info: Packing LUT-FFs..\n",
+            "Info:     4051 LCs used as LUT4 only\n",
+            "Info:      161 LCs used as LUT4 and DFF\n",
+            "Info: Packing non-LUT FFs..\n",
+            "Info:      287 LCs used as DFF only\n",
+            "Info: Packing carries..\n",
+            "Info:       70 LCs used as CARRY only\n",
+            "Info: Packing indirect carry+LUT pairs...\n",
+            "Info:       70 LUTs merged into carry LCs\n",
+            "Info: Packing RAMs..\n",
+            "Info: Placing PLLs..\n",
+            "Info: Packing special functions..\n",
+            "Info: Packing PLLs..\n",
+            "Info: Promoting globals..\n",
+            "Info: promoting clk$SB_IO_IN (fanout 448)\n",
+            "Info: Constraining chains...\n",
+            "Info:        2 LCs used to legalise carry chains.\n",
+            "Info: Checksum: 0xf154b5e8\n",
+            "\n",
+            "Info: Annotating ports with timing budgets for target frequency 12.00 MHz\n",
+            "Info: Checksum: 0x604564e8\n",
+            "\n",
+            "Info: Device utilisation:\n",
+            "Info: \t         ICESTORM_LC:  4503/ 5280    85%\n",
+            "Info: \t        ICESTORM_RAM:     0/   30     0%\n",
+            "Info: \t               SB_IO:    38/   96    39%\n",
+            "Info: \t               SB_GB:     1/    8    12%\n",
+            "Info: \t        ICESTORM_PLL:     0/    1     0%\n",
+            "Info: \t         SB_WARMBOOT:     0/    1     0%\n",
+            "Info: \t        ICESTORM_DSP:     0/    8     0%\n",
+            "Info: \t      ICESTORM_HFOSC:     0/    1     0%\n",
+            "Info: \t      ICESTORM_LFOSC:     0/    1     0%\n",
+            "Info: \t              SB_I2C:     0/    2     0%\n",
+            "Info: \t              SB_SPI:     0/    2     0%\n",
+            "Info: \t              IO_I3C:     0/    2     0%\n",
+            "Info: \t         SB_LEDDA_IP:     0/    1     0%\n",
+            "Info: \t         SB_RGBA_DRV:     0/    1     0%\n",
+            "Info: \t      ICESTORM_SPRAM:     0/    4     0%\n",
+            "\n",
+            "Info: Placed 0 cells based on constraints.\n",
+            "Info: Creating initial analytic placement for 4285 cells, random placement wirelen = 121223.\n",
+            "Info:     at initial placer iter 0, wirelen = 1401\n",
+            "Info:     at initial placer iter 1, wirelen = 1416\n",
+            "Info:     at initial placer iter 2, wirelen = 1380\n",
+            "Info:     at initial placer iter 3, wirelen = 1495\n",
+            "Info: Running main analytical placer.\n",
+            "Info:     at iteration #1, type ALL: wirelen solved = 1415, spread = 26954, legal = 27198; time = 0.38s\n",
+            "Info:     at iteration #2, type ALL: wirelen solved = 2157, spread = 21366, legal = 21789; time = 0.40s\n",
+            "Info:     at iteration #3, type ALL: wirelen solved = 3446, spread = 19572, legal = 19778; time = 0.43s\n",
+            "Info:     at iteration #4, type ALL: wirelen solved = 4203, spread = 17484, legal = 17929; time = 0.40s\n",
+            "Info:     at iteration #5, type ALL: wirelen solved = 4687, spread = 17332, legal = 17920; time = 0.40s\n",
+            "Info:     at iteration #6, type ALL: wirelen solved = 5012, spread = 17137, legal = 17728; time = 0.35s\n",
+            "Info:     at iteration #7, type ALL: wirelen solved = 5547, spread = 16859, legal = 17254; time = 0.37s\n",
+            "Info:     at iteration #8, type ALL: wirelen solved = 6045, spread = 16402, legal = 16739; time = 0.38s\n",
+            "Info:     at iteration #9, type ALL: wirelen solved = 6792, spread = 15823, legal = 16480; time = 0.34s\n",
+            "Info:     at iteration #10, type ALL: wirelen solved = 7072, spread = 14999, legal = 15687; time = 0.36s\n",
+            "Info:     at iteration #11, type ALL: wirelen solved = 7670, spread = 14617, legal = 15283; time = 0.34s\n",
+            "Info:     at iteration #12, type ALL: wirelen solved = 7955, spread = 14569, legal = 15273; time = 0.31s\n",
+            "Info:     at iteration #13, type ALL: wirelen solved = 8210, spread = 14747, legal = 15214; time = 0.33s\n",
+            "Info:     at iteration #14, type ALL: wirelen solved = 8447, spread = 14873, legal = 15422; time = 0.18s\n",
+            "Info:     at iteration #15, type ALL: wirelen solved = 8818, spread = 14561, legal = 14917; time = 0.18s\n",
+            "Info:     at iteration #16, type ALL: wirelen solved = 8961, spread = 14461, legal = 15049; time = 0.18s\n",
+            "Info:     at iteration #17, type ALL: wirelen solved = 9085, spread = 14391, legal = 14802; time = 0.17s\n",
+            "Info:     at iteration #18, type ALL: wirelen solved = 9053, spread = 14222, legal = 14764; time = 0.21s\n",
+            "Info:     at iteration #19, type ALL: wirelen solved = 9335, spread = 13983, legal = 14362; time = 0.19s\n",
+            "Info:     at iteration #20, type ALL: wirelen solved = 9453, spread = 13968, legal = 14446; time = 0.18s\n",
+            "Info:     at iteration #21, type ALL: wirelen solved = 9570, spread = 14006, legal = 14316; time = 0.17s\n",
+            "Info:     at iteration #22, type ALL: wirelen solved = 9545, spread = 13723, legal = 14155; time = 0.20s\n",
+            "Info:     at iteration #23, type ALL: wirelen solved = 9688, spread = 13656, legal = 14090; time = 0.17s\n",
+            "Info:     at iteration #24, type ALL: wirelen solved = 9864, spread = 13557, legal = 13929; time = 0.18s\n",
+            "Info:     at iteration #25, type ALL: wirelen solved = 9839, spread = 13577, legal = 13926; time = 0.17s\n",
+            "Info:     at iteration #26, type ALL: wirelen solved = 9926, spread = 13477, legal = 13962; time = 0.17s\n",
+            "Info:     at iteration #27, type ALL: wirelen solved = 10066, spread = 13426, legal = 13921; time = 0.21s\n",
+            "Info:     at iteration #28, type ALL: wirelen solved = 10120, spread = 13380, legal = 13755; time = 0.17s\n",
+            "Info:     at iteration #29, type ALL: wirelen solved = 10149, spread = 13307, legal = 13728; time = 0.17s\n",
+            "Info:     at iteration #30, type ALL: wirelen solved = 10233, spread = 13292, legal = 13692; time = 0.18s\n",
+            "Info:     at iteration #31, type ALL: wirelen solved = 10251, spread = 13258, legal = 13722; time = 0.19s\n",
+            "Info:     at iteration #32, type ALL: wirelen solved = 10260, spread = 13213, legal = 13633; time = 0.17s\n",
+            "Info:     at iteration #33, type ALL: wirelen solved = 10392, spread = 13271, legal = 13754; time = 0.18s\n",
+            "Info:     at iteration #34, type ALL: wirelen solved = 10417, spread = 13187, legal = 13584; time = 0.17s\n",
+            "Info:     at iteration #35, type ALL: wirelen solved = 10424, spread = 13166, legal = 13631; time = 0.17s\n",
+            "Info:     at iteration #36, type ALL: wirelen solved = 10515, spread = 13170, legal = 13565; time = 0.20s\n",
+            "Info:     at iteration #37, type ALL: wirelen solved = 10533, spread = 13121, legal = 13577; time = 0.17s\n",
+            "Info:     at iteration #38, type ALL: wirelen solved = 10535, spread = 13099, legal = 13551; time = 0.17s\n",
+            "Info:     at iteration #39, type ALL: wirelen solved = 10664, spread = 13051, legal = 13450; time = 0.17s\n",
+            "Info:     at iteration #40, type ALL: wirelen solved = 10660, spread = 13088, legal = 13575; time = 0.18s\n",
+            "Info:     at iteration #41, type ALL: wirelen solved = 10724, spread = 13072, legal = 13589; time = 0.17s\n",
+            "Info:     at iteration #42, type ALL: wirelen solved = 10770, spread = 13101, legal = 13558; time = 0.18s\n",
+            "Info:     at iteration #43, type ALL: wirelen solved = 10776, spread = 13047, legal = 13587; time = 0.20s\n",
+            "Info:     at iteration #44, type ALL: wirelen solved = 10841, spread = 13083, legal = 13615; time = 0.20s\n",
+            "Info: HeAP Placer Time: 14.25s\n",
+            "Info:   of which solving equations: 9.80s\n",
+            "Info:   of which spreading cells: 1.22s\n",
+            "Info:   of which strict legalisation: 0.23s\n",
+            "\n",
+            "Info: Running simulated annealing placer for refinement.\n",
+            "Info:   at iteration #1: temp = 0.000000, timing cost = 6431, wirelen = 13450\n",
+            "Info:   at iteration #5: temp = 0.000000, timing cost = 7314, wirelen = 12221\n",
+            "Info:   at iteration #10: temp = 0.000000, timing cost = 7577, wirelen = 11762\n",
+            "Info:   at iteration #15: temp = 0.000000, timing cost = 7253, wirelen = 11537\n",
+            "Info:   at iteration #20: temp = 0.000000, timing cost = 7239, wirelen = 11471\n",
+            "Info:   at iteration #24: temp = 0.000000, timing cost = 7222, wirelen = 11449 \n",
+            "Info: SA placement time 14.72s\n",
+            "\n",
+            "Info: Max frequency for clock 'clk$SB_IO_IN_$glb_clk': 17.85 MHz (PASS at 12.00 MHz)\n",
+            "\n",
+            "Info: Max delay <async>                       -> posedge clk$SB_IO_IN_$glb_clk: 44.18 ns\n",
+            "Info: Max delay posedge clk$SB_IO_IN_$glb_clk -> <async>                      : 6.00 ns\n",
+            "\n",
+            "Info: Slack histogram:\n",
+            "Info:  legend: * represents 3 endpoint(s)\n",
+            "Info:          + represents [1,3) endpoint(s)\n",
+            "Info: [ 27323,  29974) |**+\n",
+            "Info: [ 29974,  32625) |**+\n",
+            "Info: [ 32625,  35276) |**+\n",
+            "Info: [ 35276,  37927) |**+\n",
+            "Info: [ 37927,  40578) |****+\n",
+            "Info: [ 40578,  43229) |*********************+\n",
+            "Info: [ 43229,  45880) |**************************+\n",
+            "Info: [ 45880,  48531) |*********+\n",
+            "Info: [ 48531,  51182) |*******+\n",
+            "Info: [ 51182,  53833) |*+\n",
+            "Info: [ 53833,  56484) |*+\n",
+            "Info: [ 56484,  59135) |**+\n",
+            "Info: [ 59135,  61786) |**+\n",
+            "Info: [ 61786,  64437) |***+\n",
+            "Info: [ 64437,  67088) |***+\n",
+            "Info: [ 67088,  69739) |***+\n",
+            "Info: [ 69739,  72390) |**+\n",
+            "Info: [ 72390,  75041) |*********+\n",
+            "Info: [ 75041,  77692) |***********************************************************+\n",
+            "Info: [ 77692,  80343) |************************************************************ \n",
+            "Info: Checksum: 0xb385659f\n",
+            "\n",
+            "Info: Routing..\n",
+            "Info: Setting up routing queue.\n",
+            "Info: Routing 13760 arcs.\n",
+            "Info:            |   (re-)routed arcs  |   delta    | remaining|       time spent     |\n",
+            "Info:    IterCnt |  w/ripup   wo/ripup |  w/r  wo/r |      arcs| batch(sec) total(sec)|\n",
+            "Info:       1000 |      134        865 |  134   865 |     13087|       2.50       2.50|\n",
+            "Info:       2000 |      225       1774 |   91   909 |     12299|       1.20       3.70|\n",
+            "Info:       3000 |      396       2603 |  171   829 |     11694|       0.86       4.57|\n",
+            "Info:       4000 |      583       3416 |  187   813 |     11103|       1.07       5.64|\n",
+            "Info:       5000 |      792       4207 |  209   791 |     10743|       1.82       7.46|\n",
+            "Info:       6000 |     1056       4943 |  264   736 |     10424|       1.37       8.83|\n",
+            "Info:       7000 |     1330       5669 |  274   726 |      9936|       1.27      10.10|\n",
+            "Info:       8000 |     1410       6537 |   80   868 |      9084|       0.60      10.69|\n",
+            "Info:       9000 |     1618       7328 |  208   791 |      8375|       0.42      11.12|\n",
+            "Info:      10000 |     2124       7821 |  506   493 |      8020|       0.36      11.48|\n",
+            "Info:      11000 |     2449       8496 |  325   675 |      7417|       0.38      11.86|\n",
+            "Info:      12000 |     2741       9204 |  292   708 |      6829|       0.32      12.18|\n",
+            "Info:      13000 |     3098       9846 |  357   642 |      6314|       0.36      12.53|\n",
+            "Info:      14000 |     3324      10620 |  226   774 |      5641|       0.45      12.98|\n",
+            "Info:      15000 |     3609      11335 |  285   715 |      5079|       0.63      13.61|\n",
+            "Info:      16000 |     3837      12107 |  228   772 |      4400|       0.53      14.13|\n",
+            "Info:      17000 |     4053      12891 |  216   784 |      3699|       0.45      14.58|\n",
+            "Info:      18000 |     4185      13648 |  132   757 |      2860|       0.26      14.84|\n",
+            "Info:      19000 |     4625      14208 |  440   560 |      2702|       1.41      16.25|\n",
+            "Info:      20000 |     4689      15131 |   64   923 |      1828|       0.60      16.85|\n",
+            "Info:      21000 |     4791      16022 |  102   891 |      1001|       0.55      17.40|\n",
+            "Info:      22000 |     4924      16884 |  133   862 |       223|       0.59      17.99|\n",
+            "Info:      22311 |     4979      17141 |   55   257 |         0|       0.31      18.30|\n",
+            "Info: Routing complete.\n",
+            "Info: Router1 time 18.30s\n",
+            "Info: Checksum: 0xedf1247e\n",
+            "\n",
+            "Info: Critical path report for clock 'clk$SB_IO_IN_$glb_clk' (posedge -> posedge):\n",
+            "Info: curr total\n",
+            "Info:  1.4  1.4  Source x_squared_p2_SB_DFF_Q_32_DFFLC.O\n",
+            "Info:  4.1  5.5    Net x_fourth_p1_SB_DFF_Q_65_D_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_17_I2_SB_LUT4_O_I1_SB_LUT4_O_I2[2] budget 6.966000 ns (8,8) -> (17,4)\n",
+            "Info:                Sink x_fourth_p1_SB_DFF_Q_65_D_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_6_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_I3_SB_LUT4_I2_I0_SB_LUT4_O_1_I0_SB_LUT4_I3_O_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I0_SB_LUT4_O_1_I1_SB_LUT4_I3_1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I2_SB_LUT4_I2_O_SB_LUT4_O_2_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I1_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_O_1_I1_SB_LUT4_O_1_LC.I2\n",
+            "Info:                Defined in:\n",
+            "Info:                  projf-explore/maths/demo/func_polynomial.sv:27.57-27.69\n",
+            "Info:  1.2  6.7  Source x_fourth_p1_SB_DFF_Q_65_D_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_6_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_I3_SB_LUT4_I2_I0_SB_LUT4_O_1_I0_SB_LUT4_I3_O_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I0_SB_LUT4_O_1_I1_SB_LUT4_I3_1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I2_SB_LUT4_I2_O_SB_LUT4_O_2_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I1_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_O_1_I1_SB_LUT4_O_1_LC.O\n",
+            "Info:  1.8  8.5    Net x_fourth_p1_SB_DFF_Q_65_D_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_6_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_I3_SB_LUT4_I2_I0_SB_LUT4_O_1_I0_SB_LUT4_I3_O_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I0_SB_LUT4_O_1_I1_SB_LUT4_I3_1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I2_SB_LUT4_I2_O_SB_LUT4_O_2_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I1_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_O_1_I1[1] budget 6.966000 ns (17,4) -> (17,4)\n",
+            "Info:                Sink x_fourth_p1_SB_DFF_Q_65_D_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_6_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_I3_SB_LUT4_I2_I0_SB_LUT4_O_1_I0_SB_LUT4_I3_O_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I0_SB_LUT4_O_1_I1_SB_LUT4_I3_1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I2_SB_LUT4_I2_O_SB_LUT4_O_2_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I1_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_O_1_LC.I1\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/cells_map.v:6.21-6.22\n",
+            "Info:  1.2  9.7  Source x_fourth_p1_SB_DFF_Q_65_D_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_6_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_I3_SB_LUT4_I2_I0_SB_LUT4_O_1_I0_SB_LUT4_I3_O_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I0_SB_LUT4_O_1_I1_SB_LUT4_I3_1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I2_SB_LUT4_I2_O_SB_LUT4_O_2_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I1_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_O_1_LC.O\n",
+            "Info:  1.8 11.5    Net x_fourth_p1_SB_DFF_Q_65_D_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_6_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_I3_SB_LUT4_I2_I0_SB_LUT4_O_1_I0_SB_LUT4_I3_O_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I0_SB_LUT4_O_1_I1_SB_LUT4_I3_1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I2_SB_LUT4_I2_O_SB_LUT4_O_2_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I1[0] budget 6.966000 ns (17,4) -> (16,3)\n",
+            "Info:                Sink x_fourth_p1_SB_DFF_Q_65_D_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_6_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_I3_SB_LUT4_I2_I0_SB_LUT4_O_1_I0_SB_LUT4_I3_O_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I0_SB_LUT4_O_1_I1_SB_LUT4_I3_1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I2_SB_LUT4_I2_O_SB_LUT4_O_2_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_1_O_SB_LUT4_O_I1_SB_LUT4_O_LC.I0\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/cells_map.v:6.21-6.22\n",
+            "Info:  1.3 12.8  Source x_fourth_p1_SB_DFF_Q_65_D_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_6_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_I3_SB_LUT4_I2_I0_SB_LUT4_O_1_I0_SB_LUT4_I3_O_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I0_SB_LUT4_O_1_I1_SB_LUT4_I3_1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I2_SB_LUT4_I2_O_SB_LUT4_O_2_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_1_O_SB_LUT4_O_I1_SB_LUT4_O_LC.O\n",
+            "Info:  1.8 14.5    Net x_fourth_p1_SB_DFF_Q_65_D_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_6_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_I3_SB_LUT4_I2_I0_SB_LUT4_O_1_I0_SB_LUT4_I3_O_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I0_SB_LUT4_O_1_I1_SB_LUT4_I3_1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I2_SB_LUT4_I2_O_SB_LUT4_O_2_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_1_O_SB_LUT4_O_I1[0] budget 6.966000 ns (16,3) -> (16,2)\n",
+            "Info:                Sink x_fourth_p1_SB_DFF_Q_65_D_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_6_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_I3_SB_LUT4_I2_I0_SB_LUT4_O_1_I0_SB_LUT4_I3_O_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I0_SB_LUT4_O_1_I1_SB_LUT4_I3_1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I2_SB_LUT4_I2_O_SB_LUT4_O_2_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_1_O_SB_LUT4_O_LC.I1\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/cells_map.v:6.21-6.22\n",
+            "Info:  1.2 15.8  Source x_fourth_p1_SB_DFF_Q_65_D_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_6_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_I3_SB_LUT4_I2_I0_SB_LUT4_O_1_I0_SB_LUT4_I3_O_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I0_SB_LUT4_O_1_I1_SB_LUT4_I3_1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I2_SB_LUT4_I2_O_SB_LUT4_O_2_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_1_O_SB_LUT4_O_LC.O\n",
+            "Info:  2.4 18.2    Net x_fourth_p1_SB_DFF_Q_65_D_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_6_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_I3_SB_LUT4_I2_I0_SB_LUT4_O_1_I0_SB_LUT4_I3_O_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I0_SB_LUT4_O_1_I1_SB_LUT4_I3_1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I2_SB_LUT4_I2_O_SB_LUT4_O_2_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_1_O[1] budget 6.968000 ns (16,2) -> (16,4)\n",
+            "Info:                Sink x_fourth_p1_SB_DFF_Q_65_D_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_6_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_I3_SB_LUT4_I2_I0_SB_LUT4_O_1_I0_SB_LUT4_I3_O_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I0_SB_LUT4_O_1_I1_SB_LUT4_I3_1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I2_SB_LUT4_I2_O_SB_LUT4_O_2_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_1_O_SB_LUT4_I1_LC.I2\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/cells_map.v:6.21-6.22\n",
+            "Info:  1.2 19.4  Source x_fourth_p1_SB_DFF_Q_65_D_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_6_I2_SB_LUT4_O_I1_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_1_I1_SB_LUT4_O_1_I0_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_I3_SB_LUT4_I2_I3_SB_LUT4_I2_I0_SB_LUT4_O_1_I0_SB_LUT4_I3_O_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I0_SB_LUT4_O_1_I1_SB_LUT4_I3_1_O_SB_LUT4_O_I2_SB_LUT4_O_1_I2_SB_LUT4_I2_O_SB_LUT4_O_2_I1_SB_LUT4_I1_O_SB_LUT4_O_1_I3_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_I2_1_O_SB_LUT4_I1_LC.O\n",
+            "Info:  1.8 21.1    Net x_fourth_p1_SB_DFF_Q_65_D_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_21_I2_SB_LUT4_O_I2_SB_LUT4_O_I1[1] budget 6.968000 ns (16,4) -> (15,4)\n",
+            "Info:                Sink x_fourth_p1_SB_DFF_Q_65_D_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_20_I2_SB_LUT4_O_I2_SB_LUT4_O_1_LC.I2\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/cells_map.v:6.21-6.22\n",
+            "Info:  1.2 22.3  Source x_fourth_p1_SB_DFF_Q_65_D_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_20_I2_SB_LUT4_O_I2_SB_LUT4_O_1_LC.O\n",
+            "Info:  1.8 24.1    Net x_fourth_p1_SB_DFF_Q_65_D_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_20_I2_SB_LUT4_O_I2[0] budget 6.968000 ns (15,4) -> (15,4)\n",
+            "Info:                Sink x_fourth_p1_SB_DFF_Q_65_D_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_19_I2_SB_LUT4_O_1_LC.I2\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/cells_map.v:6.21-6.22\n",
+            "Info:  1.2 25.3  Source x_fourth_p1_SB_DFF_Q_65_D_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_19_I2_SB_LUT4_O_1_LC.O\n",
+            "Info:  3.1 28.4    Net x_fourth_p1_SB_DFF_Q_65_D_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_19_I1[1] budget 6.968000 ns (15,4) -> (14,9)\n",
+            "Info:                Sink x_fourth_p1_SB_DFF_Q_65_D_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_18_I1_SB_LUT4_O_LC.I2\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/cells_map.v:6.21-6.22\n",
+            "Info:  1.2 29.6  Source x_fourth_p1_SB_DFF_Q_65_D_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_18_I1_SB_LUT4_O_LC.O\n",
+            "Info:  1.8 31.3    Net x_fourth_p1_SB_DFF_Q_65_D_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_18_I1[0] budget 6.968000 ns (14,9) -> (14,9)\n",
+            "Info:                Sink x_fourth_p1_SB_DFF_Q_65_D_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_18_LC.I1\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/cells_map.v:6.21-6.22\n",
+            "Info:  1.2 32.6  Source x_fourth_p1_SB_DFF_Q_65_D_SB_LUT4_O_I3_SB_LUT4_I2_O_SB_LUT4_O_18_LC.O\n",
+            "Info:  3.1 35.6    Net x_fourth_p1_SB_DFF_Q_65_D_SB_LUT4_O_I3_SB_LUT4_I2_O[14] budget 6.968000 ns (14,9) -> (14,14)\n",
+            "Info:                Sink x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_59_LC.I1\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/techmap.v:200.24-200.25\n",
+            "Info:  0.7 36.3  Source x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_59_LC.COUT\n",
+            "Info:  0.0 36.3    Net x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_I3[15] budget 0.000000 ns (14,14) -> (14,14)\n",
+            "Info:                Sink x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_58_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3 36.6  Source x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_58_LC.COUT\n",
+            "Info:  0.6 37.1    Net x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_I3[16] budget 0.560000 ns (14,14) -> (14,15)\n",
+            "Info:                Sink x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_57_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3 37.4  Source x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_57_LC.COUT\n",
+            "Info:  0.0 37.4    Net x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_I3[17] budget 0.000000 ns (14,15) -> (14,15)\n",
+            "Info:                Sink x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_56_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3 37.7  Source x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_56_LC.COUT\n",
+            "Info:  0.0 37.7    Net x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_I3[18] budget 0.000000 ns (14,15) -> (14,15)\n",
+            "Info:                Sink x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_55_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3 38.0  Source x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_55_LC.COUT\n",
+            "Info:  0.0 38.0    Net x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_I3[19] budget 0.000000 ns (14,15) -> (14,15)\n",
+            "Info:                Sink x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_54_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3 38.2  Source x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_54_LC.COUT\n",
+            "Info:  0.0 38.2    Net x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_I3[20] budget 0.000000 ns (14,15) -> (14,15)\n",
+            "Info:                Sink x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_53_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3 38.5  Source x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_53_LC.COUT\n",
+            "Info:  0.0 38.5    Net x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_I3[21] budget 0.000000 ns (14,15) -> (14,15)\n",
+            "Info:                Sink x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_52_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3 38.8  Source x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_52_LC.COUT\n",
+            "Info:  0.0 38.8    Net x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_I3[22] budget 0.000000 ns (14,15) -> (14,15)\n",
+            "Info:                Sink x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_51_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3 39.1  Source x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_51_LC.COUT\n",
+            "Info:  0.0 39.1    Net x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_I3[23] budget 0.000000 ns (14,15) -> (14,15)\n",
+            "Info:                Sink x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_50_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3 39.4  Source x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_50_LC.COUT\n",
+            "Info:  0.6 39.9    Net x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_I3[24] budget 0.560000 ns (14,15) -> (14,16)\n",
+            "Info:                Sink x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_49_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3 40.2  Source x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_49_LC.COUT\n",
+            "Info:  0.0 40.2    Net x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_I3[25] budget 0.000000 ns (14,16) -> (14,16)\n",
+            "Info:                Sink x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_48_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3 40.5  Source x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_48_LC.COUT\n",
+            "Info:  0.0 40.5    Net x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_I3[26] budget 0.000000 ns (14,16) -> (14,16)\n",
+            "Info:                Sink x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_47_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3 40.7  Source x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_47_LC.COUT\n",
+            "Info:  0.0 40.7    Net x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_I3[27] budget 0.000000 ns (14,16) -> (14,16)\n",
+            "Info:                Sink x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_46_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3 41.0  Source x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_46_LC.COUT\n",
+            "Info:  0.0 41.0    Net x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_I3[28] budget 0.000000 ns (14,16) -> (14,16)\n",
+            "Info:                Sink x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_45_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3 41.3  Source x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_45_LC.COUT\n",
+            "Info:  0.0 41.3    Net x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_I3[29] budget 0.000000 ns (14,16) -> (14,16)\n",
+            "Info:                Sink x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_44_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3 41.6  Source x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_44_LC.COUT\n",
+            "Info:  0.0 41.6    Net x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_I3[30] budget 0.000000 ns (14,16) -> (14,16)\n",
+            "Info:                Sink x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_43_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3 41.9  Source x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_43_LC.COUT\n",
+            "Info:  0.0 41.9    Net x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_I3[31] budget 0.000000 ns (14,16) -> (14,16)\n",
+            "Info:                Sink x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_42_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3 42.1  Source x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_42_LC.COUT\n",
+            "Info:  0.6 42.7    Net x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_I3[32] budget 0.560000 ns (14,16) -> (14,17)\n",
+            "Info:                Sink x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_41_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3 43.0  Source x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_41_LC.COUT\n",
+            "Info:  0.0 43.0    Net x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_I3[33] budget 0.000000 ns (14,17) -> (14,17)\n",
+            "Info:                Sink x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_40_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3 43.2  Source x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_40_LC.COUT\n",
+            "Info:  0.0 43.2    Net x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_I3[34] budget 0.000000 ns (14,17) -> (14,17)\n",
+            "Info:                Sink x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_39_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3 43.5  Source x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_39_LC.COUT\n",
+            "Info:  0.0 43.5    Net x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_I3[35] budget 0.000000 ns (14,17) -> (14,17)\n",
+            "Info:                Sink x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_38_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3 43.8  Source x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_38_LC.COUT\n",
+            "Info:  0.0 43.8    Net x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_I3[36] budget 0.000000 ns (14,17) -> (14,17)\n",
+            "Info:                Sink x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_37_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3 44.1  Source x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_37_LC.COUT\n",
+            "Info:  0.0 44.1    Net x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_I3[37] budget 0.000000 ns (14,17) -> (14,17)\n",
+            "Info:                Sink x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_36_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3 44.4  Source x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_36_LC.COUT\n",
+            "Info:  0.0 44.4    Net x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_I3[38] budget 0.000000 ns (14,17) -> (14,17)\n",
+            "Info:                Sink x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_35_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3 44.6  Source x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_35_LC.COUT\n",
+            "Info:  0.0 44.6    Net x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_I3[39] budget 0.000000 ns (14,17) -> (14,17)\n",
+            "Info:                Sink x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_34_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3 44.9  Source x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_34_LC.COUT\n",
+            "Info:  0.6 45.5    Net x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_I3[40] budget 0.560000 ns (14,17) -> (14,18)\n",
+            "Info:                Sink x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_33_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3 45.8  Source x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_33_LC.COUT\n",
+            "Info:  0.0 45.8    Net x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_I3[41] budget 0.000000 ns (14,18) -> (14,18)\n",
+            "Info:                Sink x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_32_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3 46.0  Source x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_32_LC.COUT\n",
+            "Info:  0.0 46.0    Net x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_I3[42] budget 0.000000 ns (14,18) -> (14,18)\n",
+            "Info:                Sink x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_31_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3 46.3  Source x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_31_LC.COUT\n",
+            "Info:  0.0 46.3    Net x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_I3[43] budget 0.000000 ns (14,18) -> (14,18)\n",
+            "Info:                Sink x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_30_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3 46.6  Source x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_30_LC.COUT\n",
+            "Info:  0.0 46.6    Net x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_I3[44] budget 0.000000 ns (14,18) -> (14,18)\n",
+            "Info:                Sink x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_29_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3 46.9  Source x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_29_LC.COUT\n",
+            "Info:  0.0 46.9    Net x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_I3[45] budget 0.000000 ns (14,18) -> (14,18)\n",
+            "Info:                Sink x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_28_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3 47.1  Source x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_28_LC.COUT\n",
+            "Info:  0.0 47.1    Net x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_I3[46] budget 0.000000 ns (14,18) -> (14,18)\n",
+            "Info:                Sink x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_27_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3 47.4  Source x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_27_LC.COUT\n",
+            "Info:  0.0 47.4    Net x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_I3[47] budget 0.000000 ns (14,18) -> (14,18)\n",
+            "Info:                Sink x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_26_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3 47.7  Source x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_26_LC.COUT\n",
+            "Info:  0.6 48.3    Net x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_I3[48] budget 0.560000 ns (14,18) -> (14,19)\n",
+            "Info:                Sink x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_25_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3 48.5  Source x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_25_LC.COUT\n",
+            "Info:  0.0 48.5    Net x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_I3[49] budget 0.000000 ns (14,19) -> (14,19)\n",
+            "Info:                Sink x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_24_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3 48.8  Source x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_24_LC.COUT\n",
+            "Info:  0.0 48.8    Net x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_I3[50] budget 0.000000 ns (14,19) -> (14,19)\n",
+            "Info:                Sink x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_23_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3 49.1  Source x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_23_LC.COUT\n",
+            "Info:  0.0 49.1    Net x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_I3[51] budget 0.000000 ns (14,19) -> (14,19)\n",
+            "Info:                Sink x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_22_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3 49.4  Source x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_22_LC.COUT\n",
+            "Info:  0.0 49.4    Net x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_I3[52] budget 0.000000 ns (14,19) -> (14,19)\n",
+            "Info:                Sink x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_21_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3 49.6  Source x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_21_LC.COUT\n",
+            "Info:  0.0 49.6    Net x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_I3[53] budget 0.000000 ns (14,19) -> (14,19)\n",
+            "Info:                Sink x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_20_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3 49.9  Source x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_20_LC.COUT\n",
+            "Info:  0.0 49.9    Net x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_I3[54] budget 0.000000 ns (14,19) -> (14,19)\n",
+            "Info:                Sink x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_19_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3 50.2  Source x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_19_LC.COUT\n",
+            "Info:  0.0 50.2    Net x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_I3[55] budget 0.000000 ns (14,19) -> (14,19)\n",
+            "Info:                Sink x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_18_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3 50.5  Source x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_18_LC.COUT\n",
+            "Info:  0.6 51.0    Net x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_I3[56] budget 0.560000 ns (14,19) -> (14,20)\n",
+            "Info:                Sink x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_17_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3 51.3  Source x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_17_LC.COUT\n",
+            "Info:  0.0 51.3    Net x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_I3[57] budget 0.000000 ns (14,20) -> (14,20)\n",
+            "Info:                Sink x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_16_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3 51.6  Source x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_16_LC.COUT\n",
+            "Info:  0.0 51.6    Net x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_I3[58] budget 0.000000 ns (14,20) -> (14,20)\n",
+            "Info:                Sink x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_15_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3 51.9  Source x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_15_LC.COUT\n",
+            "Info:  0.0 51.9    Net x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_I3[59] budget 0.000000 ns (14,20) -> (14,20)\n",
+            "Info:                Sink x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_14_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3 52.1  Source x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_14_LC.COUT\n",
+            "Info:  0.0 52.1    Net x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_I3[60] budget 0.000000 ns (14,20) -> (14,20)\n",
+            "Info:                Sink x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_13_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3 52.4  Source x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_13_LC.COUT\n",
+            "Info:  0.0 52.4    Net x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_I3[61] budget 0.000000 ns (14,20) -> (14,20)\n",
+            "Info:                Sink x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_12_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3 52.7  Source x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_12_LC.COUT\n",
+            "Info:  0.0 52.7    Net x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_I3[62] budget 0.000000 ns (14,20) -> (14,20)\n",
+            "Info:                Sink x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_11_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3 53.0  Source x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_11_LC.COUT\n",
+            "Info:  0.0 53.0    Net x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_I3[63] budget 0.000000 ns (14,20) -> (14,20)\n",
+            "Info:                Sink x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_10_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3 53.3  Source x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_10_LC.COUT\n",
+            "Info:  0.6 53.8    Net x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_I3[64] budget 0.560000 ns (14,20) -> (14,21)\n",
+            "Info:                Sink x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_9_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3 54.1  Source x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_9_LC.COUT\n",
+            "Info:  0.0 54.1    Net x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_I3[65] budget 0.000000 ns (14,21) -> (14,21)\n",
+            "Info:                Sink x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_8_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3 54.4  Source x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_8_LC.COUT\n",
+            "Info:  0.0 54.4    Net x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_I3[66] budget 0.000000 ns (14,21) -> (14,21)\n",
+            "Info:                Sink x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_7_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3 54.6  Source x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_7_LC.COUT\n",
+            "Info:  0.0 54.6    Net x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_I3[67] budget 0.000000 ns (14,21) -> (14,21)\n",
+            "Info:                Sink x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_6_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3 54.9  Source x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_6_LC.COUT\n",
+            "Info:  0.0 54.9    Net x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_I3[68] budget 0.000000 ns (14,21) -> (14,21)\n",
+            "Info:                Sink x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_5_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3 55.2  Source x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_5_LC.COUT\n",
+            "Info:  0.0 55.2    Net x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_I3[69] budget 0.000000 ns (14,21) -> (14,21)\n",
+            "Info:                Sink x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_4_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3 55.5  Source x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_4_LC.COUT\n",
+            "Info:  0.0 55.5    Net x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_I3[70] budget 0.000000 ns (14,21) -> (14,21)\n",
+            "Info:                Sink x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_3_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3 55.8  Source x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_3_LC.COUT\n",
+            "Info:  0.7 56.4    Net x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_I3[71] budget 0.660000 ns (14,21) -> (14,21)\n",
+            "Info:                Sink x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_2_LC.I3\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.8 57.2  Setup x_fourth_p1_SB_DFF_Q_D_SB_LUT4_O_2_LC.I3\n",
+            "Info: 29.5 ns logic, 27.8 ns routing\n",
+            "\n",
+            "Info: Critical path report for cross-domain path '<async>' -> 'posedge clk$SB_IO_IN_$glb_clk':\n",
+            "Info: curr total\n",
+            "Info:  0.0  0.0  Source x[6]$sb_io.D_IN_0\n",
+            "Info:  8.1  8.1    Net x[6]$SB_IO_IN budget 7.999000 ns (19,31) -> (1,2)\n",
+            "Info:                Sink x_squared_p3_SB_DFF_Q_30_D_SB_LUT4_O_7_I2_SB_LUT4_O_1_I0_SB_LUT4_O_1_LC.I3\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/cells_map.v:6.21-6.22\n",
+            "Info:  0.9  9.0  Source x_squared_p3_SB_DFF_Q_30_D_SB_LUT4_O_7_I2_SB_LUT4_O_1_I0_SB_LUT4_O_1_LC.O\n",
+            "Info:  3.0 12.0    Net x_squared_p3_SB_DFF_Q_30_D_SB_LUT4_O_2_I2_SB_LUT4_O_I1_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_O_I1_SB_LUT4_O_I0[3] budget 7.999000 ns (1,2) -> (4,3)\n",
+            "Info:                Sink x_squared_p3_SB_DFF_Q_30_D_SB_LUT4_O_9_I2_SB_LUT4_O_2_I1_SB_LUT4_I1_O_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_I1_O_SB_LUT4_O_I3_SB_LUT4_I3_LC.I2\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/cells_map.v:6.21-6.22\n",
+            "Info:  1.2 13.2  Source x_squared_p3_SB_DFF_Q_30_D_SB_LUT4_O_9_I2_SB_LUT4_O_2_I1_SB_LUT4_I1_O_SB_LUT4_I0_O_SB_LUT4_O_1_I2_SB_LUT4_I2_O_SB_LUT4_O_1_I3_SB_LUT4_I1_O_SB_LUT4_O_I3_SB_LUT4_I3_LC.O\n",
+            "Info:  4.2 17.4    Net x_squared_p3_SB_DFF_Q_30_D_SB_LUT4_O_29_I1_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_O_I0_SB_LUT4_I0_O_SB_LUT4_I0_O_SB_LUT4_O_I1_SB_LUT4_I0_O_SB_LUT4_O_I3[2] budget 7.999000 ns (4,3) -> (1,12)\n",
+            "Info:                Sink x_squared_p3_SB_DFF_Q_30_D_SB_LUT4_O_9_I2_SB_LUT4_O_2_I1_SB_LUT4_I1_I3_SB_LUT4_O_I0_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_1_I1_SB_LUT4_O_2_LC.I3\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/cells_map.v:6.21-6.22\n",
+            "Info:  0.9 18.3  Source x_squared_p3_SB_DFF_Q_30_D_SB_LUT4_O_9_I2_SB_LUT4_O_2_I1_SB_LUT4_I1_I3_SB_LUT4_O_I0_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_1_I1_SB_LUT4_O_2_LC.O\n",
+            "Info:  1.8 20.1    Net x_squared_p3_SB_DFF_Q_30_D_SB_LUT4_O_9_I2_SB_LUT4_O_2_I1_SB_LUT4_I1_I3_SB_LUT4_O_I0_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_1_I1[0] budget 7.999000 ns (1,12) -> (1,13)\n",
+            "Info:                Sink x_squared_p3_SB_DFF_Q_30_D_SB_LUT4_O_9_I2_SB_LUT4_O_2_I1_SB_LUT4_I1_I3_SB_LUT4_O_I0_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_1_LC.I1\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/cells_map.v:6.21-6.22\n",
+            "Info:  1.2 21.3  Source x_squared_p3_SB_DFF_Q_30_D_SB_LUT4_O_9_I2_SB_LUT4_O_2_I1_SB_LUT4_I1_I3_SB_LUT4_O_I0_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_O_1_LC.O\n",
+            "Info:  1.8 23.0    Net x_squared_p3_SB_DFF_Q_30_D_SB_LUT4_O_9_I2_SB_LUT4_O_2_I1_SB_LUT4_I1_I3_SB_LUT4_O_I0_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I3_O_SB_LUT4_I0_O[0] budget 8.062000 ns (1,13) -> (2,12)\n",
+            "Info:                Sink x_squared_p3_SB_DFF_Q_30_D_SB_LUT4_O_9_I2_SB_LUT4_O_2_I1_SB_LUT4_I1_I3_SB_LUT4_O_I0_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_I1_1_LC.I1\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/cells_map.v:6.21-6.22\n",
+            "Info:  1.2 24.3  Source x_squared_p3_SB_DFF_Q_30_D_SB_LUT4_O_9_I2_SB_LUT4_O_2_I1_SB_LUT4_I1_I3_SB_LUT4_O_I0_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_I1_1_LC.O\n",
+            "Info:  1.8 26.0    Net x_squared_p3_SB_DFF_Q_30_D_SB_LUT4_O_9_I2_SB_LUT4_O_2_I1_SB_LUT4_I1_I3_SB_LUT4_O_I0_SB_LUT4_I2_O_SB_LUT4_O_I0_SB_LUT4_I3_O_SB_LUT4_I0_O_SB_LUT4_I1_1_O[1] budget 8.062000 ns (2,12) -> (2,11)\n",
+            "Info:                Sink x_squared_p3_SB_DFF_Q_30_D_SB_LUT4_O_27_I1_SB_LUT4_O_1_I1_SB_LUT4_O_1_LC.I2\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/cells_map.v:6.21-6.22\n",
+            "Info:  1.2 27.2  Source x_squared_p3_SB_DFF_Q_30_D_SB_LUT4_O_27_I1_SB_LUT4_O_1_I1_SB_LUT4_O_1_LC.O\n",
+            "Info:  2.4 29.7    Net x_squared_p3_SB_DFF_Q_30_D_SB_LUT4_O_27_I1_SB_LUT4_O_1_I1[1] budget 8.061000 ns (2,11) -> (3,9)\n",
+            "Info:                Sink x_squared_p3_SB_DFF_Q_30_D_SB_LUT4_O_27_I1_SB_LUT4_O_1_LC.I2\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/cells_map.v:6.21-6.22\n",
+            "Info:  1.2 30.9  Source x_squared_p3_SB_DFF_Q_30_D_SB_LUT4_O_27_I1_SB_LUT4_O_1_LC.O\n",
+            "Info:  1.8 32.6    Net x_squared_p3_SB_DFF_Q_30_D_SB_LUT4_O_27_I1[1] budget 8.061000 ns (3,9) -> (4,9)\n",
+            "Info:                Sink x_squared_p3_SB_DFF_Q_30_D_SB_LUT4_O_27_LC.I2\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/cells_map.v:6.21-6.22\n",
+            "Info:  1.2 33.8  Source x_squared_p3_SB_DFF_Q_30_D_SB_LUT4_O_27_LC.O\n",
+            "Info:  3.6 37.4    Net x_squared_p3_SB_DFF_Q_30_D[18] budget 8.061000 ns (4,9) -> (7,5)\n",
+            "Info:                Sink x_squared_p3_SB_DFF_Q_D_SB_LUT4_O_21_LC.I1\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/techmap.v:200.24-200.25\n",
+            "Info:  0.7 38.1  Source x_squared_p3_SB_DFF_Q_D_SB_LUT4_O_21_LC.COUT\n",
+            "Info:  0.0 38.1    Net x_squared_p3_SB_DFF_Q_D_SB_LUT4_O_I3[19] budget 0.000000 ns (7,5) -> (7,5)\n",
+            "Info:                Sink x_squared_p3_SB_DFF_Q_D_SB_LUT4_O_20_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3 38.4  Source x_squared_p3_SB_DFF_Q_D_SB_LUT4_O_20_LC.COUT\n",
+            "Info:  0.0 38.4    Net x_squared_p3_SB_DFF_Q_D_SB_LUT4_O_I3[20] budget 0.000000 ns (7,5) -> (7,5)\n",
+            "Info:                Sink x_squared_p3_SB_DFF_Q_D_SB_LUT4_O_19_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3 38.7  Source x_squared_p3_SB_DFF_Q_D_SB_LUT4_O_19_LC.COUT\n",
+            "Info:  0.0 38.7    Net x_squared_p3_SB_DFF_Q_D_SB_LUT4_O_I3[21] budget 0.000000 ns (7,5) -> (7,5)\n",
+            "Info:                Sink x_squared_p3_SB_DFF_Q_D_SB_LUT4_O_18_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3 38.9  Source x_squared_p3_SB_DFF_Q_D_SB_LUT4_O_18_LC.COUT\n",
+            "Info:  0.6 39.5    Net x_squared_p3_SB_DFF_Q_D_SB_LUT4_O_I3[22] budget 0.560000 ns (7,5) -> (7,6)\n",
+            "Info:                Sink x_squared_p3_SB_DFF_Q_D_SB_LUT4_O_17_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3 39.8  Source x_squared_p3_SB_DFF_Q_D_SB_LUT4_O_17_LC.COUT\n",
+            "Info:  0.0 39.8    Net x_squared_p3_SB_DFF_Q_D_SB_LUT4_O_I3[23] budget 0.000000 ns (7,6) -> (7,6)\n",
+            "Info:                Sink x_squared_p3_SB_DFF_Q_D_SB_LUT4_O_16_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3 40.0  Source x_squared_p3_SB_DFF_Q_D_SB_LUT4_O_16_LC.COUT\n",
+            "Info:  0.0 40.0    Net x_squared_p3_SB_DFF_Q_D_SB_LUT4_O_I3[24] budget 0.000000 ns (7,6) -> (7,6)\n",
+            "Info:                Sink x_squared_p3_SB_DFF_Q_D_SB_LUT4_O_15_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3 40.3  Source x_squared_p3_SB_DFF_Q_D_SB_LUT4_O_15_LC.COUT\n",
+            "Info:  0.0 40.3    Net x_squared_p3_SB_DFF_Q_D_SB_LUT4_O_I3[25] budget 0.000000 ns (7,6) -> (7,6)\n",
+            "Info:                Sink x_squared_p3_SB_DFF_Q_D_SB_LUT4_O_14_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3 40.6  Source x_squared_p3_SB_DFF_Q_D_SB_LUT4_O_14_LC.COUT\n",
+            "Info:  0.0 40.6    Net x_squared_p3_SB_DFF_Q_D_SB_LUT4_O_I3[26] budget 0.000000 ns (7,6) -> (7,6)\n",
+            "Info:                Sink x_squared_p3_SB_DFF_Q_D_SB_LUT4_O_13_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3 40.9  Source x_squared_p3_SB_DFF_Q_D_SB_LUT4_O_13_LC.COUT\n",
+            "Info:  0.0 40.9    Net x_squared_p3_SB_DFF_Q_D_SB_LUT4_O_I3[27] budget 0.000000 ns (7,6) -> (7,6)\n",
+            "Info:                Sink x_squared_p3_SB_DFF_Q_D_SB_LUT4_O_12_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3 41.2  Source x_squared_p3_SB_DFF_Q_D_SB_LUT4_O_12_LC.COUT\n",
+            "Info:  0.0 41.2    Net x_squared_p3_SB_DFF_Q_D_SB_LUT4_O_I3[28] budget 0.000000 ns (7,6) -> (7,6)\n",
+            "Info:                Sink x_squared_p3_SB_DFF_Q_D_SB_LUT4_O_11_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3 41.4  Source x_squared_p3_SB_DFF_Q_D_SB_LUT4_O_11_LC.COUT\n",
+            "Info:  0.0 41.4    Net x_squared_p3_SB_DFF_Q_D_SB_LUT4_O_I3[29] budget 0.000000 ns (7,6) -> (7,6)\n",
+            "Info:                Sink x_squared_p3_SB_DFF_Q_D_SB_LUT4_O_10_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3 41.7  Source x_squared_p3_SB_DFF_Q_D_SB_LUT4_O_10_LC.COUT\n",
+            "Info:  0.6 42.3    Net x_squared_p3_SB_DFF_Q_D_SB_LUT4_O_I3[30] budget 0.560000 ns (7,6) -> (7,7)\n",
+            "Info:                Sink x_squared_p3_SB_DFF_Q_D_SB_LUT4_O_9_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3 42.5  Source x_squared_p3_SB_DFF_Q_D_SB_LUT4_O_9_LC.COUT\n",
+            "Info:  0.0 42.5    Net x_squared_p3_SB_DFF_Q_D_SB_LUT4_O_I3[31] budget 0.000000 ns (7,7) -> (7,7)\n",
+            "Info:                Sink x_squared_p3_SB_DFF_Q_D_SB_LUT4_O_8_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3 42.8  Source x_squared_p3_SB_DFF_Q_D_SB_LUT4_O_8_LC.COUT\n",
+            "Info:  0.0 42.8    Net x_squared_p3_SB_DFF_Q_D_SB_LUT4_O_I3[32] budget 0.000000 ns (7,7) -> (7,7)\n",
+            "Info:                Sink x_squared_p3_SB_DFF_Q_D_SB_LUT4_O_7_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3 43.1  Source x_squared_p3_SB_DFF_Q_D_SB_LUT4_O_7_LC.COUT\n",
+            "Info:  0.0 43.1    Net x_squared_p3_SB_DFF_Q_D_SB_LUT4_O_I3[33] budget 0.000000 ns (7,7) -> (7,7)\n",
+            "Info:                Sink x_squared_p3_SB_DFF_Q_D_SB_LUT4_O_6_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3 43.4  Source x_squared_p3_SB_DFF_Q_D_SB_LUT4_O_6_LC.COUT\n",
+            "Info:  0.0 43.4    Net x_squared_p3_SB_DFF_Q_D_SB_LUT4_O_I3[34] budget 0.000000 ns (7,7) -> (7,7)\n",
+            "Info:                Sink x_squared_p3_SB_DFF_Q_D_SB_LUT4_O_5_LC.CIN\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.3 43.7  Source x_squared_p3_SB_DFF_Q_D_SB_LUT4_O_5_LC.COUT\n",
+            "Info:  0.7 44.3    Net x_squared_p3_SB_DFF_Q_D_SB_LUT4_O_I3[35] budget 0.660000 ns (7,7) -> (7,7)\n",
+            "Info:                Sink x_squared_p3_SB_DFF_Q_D_SB_LUT4_O_4_LC.I3\n",
+            "Info:                Defined in:\n",
+            "Info:                  /content/miniconda-pnr/bin/../share/yosys/ice40/arith_map.v:51.21-51.22\n",
+            "Info:  0.8 45.1  Setup x_squared_p3_SB_DFF_Q_D_SB_LUT4_O_4_LC.I3\n",
+            "Info: 15.0 ns logic, 30.2 ns routing\n",
+            "\n",
+            "Info: Critical path report for cross-domain path 'posedge clk$SB_IO_IN_$glb_clk' -> '<async>':\n",
+            "Info: curr total\n",
+            "Info:  1.4  1.4  Source r_SB_DFF_Q_D_SB_LUT4_O_LC.O\n",
+            "Info:  4.2  5.6    Net r$SB_IO_OUT budget 81.943001 ns (18,14) -> (18,31)\n",
+            "Info:                Sink r$sb_io.D_OUT_0\n",
+            "Info:                Defined in:\n",
+            "Info:                  projf-explore/maths/demo/func_polynomial.sv:15.18-15.19\n",
+            "Info: 1.4 ns logic, 4.2 ns routing\n",
+            "\n",
+            "Info: Max frequency for clock 'clk$SB_IO_IN_$glb_clk': 17.47 MHz (PASS at 12.00 MHz)\n",
+            "\n",
+            "Info: Max delay <async>                       -> posedge clk$SB_IO_IN_$glb_clk: 45.14 ns\n",
+            "Info: Max delay posedge clk$SB_IO_IN_$glb_clk -> <async>                      : 5.61 ns\n",
+            "\n",
+            "Info: Slack histogram:\n",
+            "Info:  legend: * represents 3 endpoint(s)\n",
+            "Info:          + represents [1,3) endpoint(s)\n",
+            "Info: [ 26090,  28803) |**+\n",
+            "Info: [ 28803,  31516) |**+\n",
+            "Info: [ 31516,  34229) |**+\n",
+            "Info: [ 34229,  36942) |**+\n",
+            "Info: [ 36942,  39655) |***+\n",
+            "Info: [ 39655,  42368) |***********+\n",
+            "Info: [ 42368,  45081) |*************************+\n",
+            "Info: [ 45081,  47794) |**********+\n",
+            "Info: [ 47794,  50507) |********+\n",
+            "Info: [ 50507,  53220) |***+\n",
+            "Info: [ 53220,  55933) |*+\n",
+            "Info: [ 55933,  58646) |***+\n",
+            "Info: [ 58646,  61359) |**+\n",
+            "Info: [ 61359,  64072) |**+\n",
+            "Info: [ 64072,  66785) |**+\n",
+            "Info: [ 66785,  69498) |**+\n",
+            "Info: [ 69498,  72211) |**+\n",
+            "Info: [ 72211,  74924) |*******+\n",
+            "Info: [ 74924,  77637) |*******************************************+\n",
+            "Info: [ 77637,  80350) |************************************************************ \n",
+            "2 warnings, 0 errors\n",
+            "\n",
+            "Info: Program finished normally.\n"
+          ]
+        }
+      ]
+    },
+    {
+      "cell_type": "code",
+      "metadata": {
+        "colab": {
+          "base_uri": "https://localhost:8080/",
+          "height": 1000
+        },
+        "id": "mmL3OX9dMyLQ",
+        "outputId": "a50f6ff4-ca7b-4c1e-f103-37d9d0e5873f"
+      },
+      "source": [
+        "from IPython.display import SVG\n",
+        "SVG(filename='func_polynomial_placed.svg')"
+      ],
+      "execution_count": 30,
+      "outputs": [
+        {
+          "output_type": "execute_result",
+          "data": {
+            "text/plain": [
+              "<IPython.core.display.SVG object>"
+            ],
+            "image/svg+xml": "<svg xmlns=\"http://www.w3.org/2000/svg\" viewBox=\"0 0 1349.166504 1643.375000\" width=\"1349.166504\" height=\"1643.375000\">\n<rect x=\"0\" y=\"0\" width=\"100%\" height=\"100%\" stroke=\"#fff\" fill=\"#fff\"/>\n<rect x=\"67.500000\" y=\"2.500000\" width=\"12.500000\" height=\"34.000000\" stroke=\"#808080\" fill=\"none\"/>\n<rect x=\"81.500000\" y=\"2.500000\" width=\"5.000001\" height=\"25.000000\" stroke=\"#808080\" fill=\"none\"/>\n<rect x=\"117.499992\" y=\"2.500000\" width=\"12.500000\" height=\"34.000000\" stroke=\"#808080\" fill=\"none\"/>\n<rect x=\"131.500000\" y=\"2.500000\" width=\"4.999995\" height=\"25.000000\" stroke=\"#808080\" fill=\"none\"/>\n<rect x=\"167.500000\" y=\"2.500000\" width=\"12.500000\" height=\"34.000000\" stroke=\"#808080\" fill=\"none\"/>\n<rect x=\"181.500000\" y=\"2.500000\" width=\"4.999995\" height=\"25.000000\" stroke=\"#808080\" fill=\"none\"/>\n<rect x=\"217.500000\" y=\"2.500000\" width=\"12.500000\" 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+}
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