diff --git a/LLM4ChipDesign_Course_Syllabus.html b/LLM4ChipDesign_Course_Syllabus.html new file mode 100644 index 0000000..a9cb7e5 --- /dev/null +++ b/LLM4ChipDesign_Course_Syllabus.html @@ -0,0 +1,561 @@ + + + + + + LLM4ChipDesign Course Syllabus + + + +
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LLM4ChipDesign Course Syllabus

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Generative AI for Chip Design - 14 Week Curriculum

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Course Information

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Course Objectives

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By the end of this course, students will:

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Module Schedule Overview

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WeeksModuleTopicKey Technologies
1-2Module 1AutoChip - Automated Verilog GenerationBasic LLM prompting, Error feedback loops
3-4Module 2VeriThoughts - Reasoning-Based GenerationFormal verification, Reasoning frameworks
5-6Module 3ROME - Hierarchical PromptingHierarchical design, Complex systems
7-8Module 4LLM-Aided Testbench GenerationVerification, Coverage analysis
9-10Module 5Hybrid-NL2SVA - Assertion GenerationSystemVerilog assertions, Security
11-12Module 6C2HLSC - Software to Hardware BridgeHigh-level synthesis, C-to-hardware
13-14Module 7PrefixLLM - Specialized Circuit DesignPrefix circuits, Design optimization
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Detailed Module Breakdown

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Module 1: AutoChip - Automated Verilog Generation (Weeks 1-2)

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Week 1: Fundamentals and Introduction

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+ Learning Objectives: +
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  • Understand the basics of LLM-assisted Verilog generation
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  • Learn AutoChip's iterative feedback mechanism
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  • Explore error-driven design refinement
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+ Homework Assignment: +
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  • Design a simple combinational circuit (e.g., 4-bit adder) using AutoChip
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  • Analyze and document the iterative refinement process
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  • Compare LLM-generated code with manual implementation
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Week 2: Problem Solving and Practice

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  • Review homework solutions and common issues
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  • Hands-on workshop with AutoChip tutorial
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  • Debugging techniques for LLM-generated Verilog
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  • Best practices for prompt design
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Module 2: VeriThoughts - Reasoning-Based Verilog Generation (Weeks 3-4)

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Week 1: Fundamentals and Introduction

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+ Learning Objectives: +
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  • Understand reasoning-based approaches to hardware description
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  • Learn formal verification integration with LLM generation
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  • Explore specialized small-scale models for Verilog
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+ Homework Assignment: +
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  • Implement a finite state machine using VeriThoughts methodology
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  • Apply formal verification to validate correctness
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  • Compare reasoning-based vs. direct generation approaches
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Week 2: Problem Solving and Practice

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  • Solution walkthrough for FSM implementation
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  • Formal verification workshop
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  • Performance comparison analysis
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  • Discussion on correctness guarantees
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Module 3: ROME - Hierarchical Prompting for Complex Designs (Weeks 5-6)

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Week 1: Fundamentals and Introduction

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+ Learning Objectives: +
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  • Master hierarchical design decomposition strategies
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  • Understand multi-level prompting techniques
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  • Learn to handle complex hardware modules
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+ Homework Assignment: +
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  • Design a hierarchical processor component (e.g., ALU with multiple sub-modules)
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  • Implement using both flat and hierarchical prompting
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  • Analyze cost and time benefits of hierarchical approach
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Week 2: Problem Solving and Practice

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  • Hierarchical design solution review
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  • Advanced ROME techniques workshop
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  • Cost-benefit analysis discussion
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  • Complex design case studies
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Module 4: LLM-Aided Testbench Generation and Verification (Weeks 7-8)

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Week 1: Fundamentals and Introduction

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+ Learning Objectives: +
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  • Understand automated testbench generation principles
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  • Learn coverage-driven verification with LLMs
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  • Master EDA tool integration techniques
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+ Homework Assignment: +
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  • Generate comprehensive testbenches for a finite state machine
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  • Achieve target coverage metrics
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  • Implement bug detection and reporting workflow
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Week 2: Problem Solving and Practice

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  • Testbench solution analysis
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  • Coverage optimization techniques
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  • EDA tool integration workshop
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  • Real-world verification scenarios
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Module 5: Hybrid-NL2SVA - Natural Language to SystemVerilog Assertions (Weeks 9-10)

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Week 1: Fundamentals and Introduction

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+ Learning Objectives: +
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  • Master assertion-based verification concepts
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  • Learn natural language to SystemVerilog translation
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  • Understand security-centric assertion development
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+ Homework Assignment: +
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  • Convert natural language security requirements to SVA
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  • Implement assertion suite for a cryptographic module
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  • Validate assertions using formal verification
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Week 2: Problem Solving and Practice

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  • SVA implementation review
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  • Security assertion patterns workshop
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  • Formal verification of assertions
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  • Industry best practices discussion
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Module 6: C2HLSC - Software to Hardware Design Bridge (Weeks 11-12)

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Week 1: Fundamentals and Introduction

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+ Learning Objectives: +
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  • Understand High-Level Synthesis (HLS) principles
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  • Learn C-to-hardware translation techniques
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  • Master LLM-guided code transformation
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+ Homework Assignment: +
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  • Transform a C algorithm (e.g., sorting, encryption) to HLS-compatible format
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  • Optimize for area and timing constraints
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  • Compare different optimization strategies
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Week 2: Problem Solving and Practice

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  • HLS optimization solution review
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  • Performance analysis workshop
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  • Area vs. timing trade-offs discussion
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  • Advanced HLS techniques
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Module 7: PrefixLLM - Specialized Circuit Design (Weeks 13-14)

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Week 1: Fundamentals and Introduction

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+ Learning Objectives: +
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  • Understand prefix circuit design principles
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  • Learn structured representation for circuit synthesis
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  • Master design space exploration with LLMs
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+ Homework Assignment: +
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  • Design optimized prefix circuits for different bit widths
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  • Implement design space exploration framework
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  • Compare multiple optimization objectives
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Week 2: Problem Solving and Practice

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  • Optimization results analysis
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  • Design space exploration workshop
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  • Multi-objective optimization discussion
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  • Course wrap-up and future directions
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Assessment Methods

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Continuous Assessment (70%)

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Final Project (30%)

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Required Tools and Resources

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Software Tools

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  • Verilator or equivalent Verilog simulator
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  • Python environment with LLM libraries
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  • Access to LLM APIs (OpenAI, Anthropic, etc.)
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  • EDA tools for synthesis and verification
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  • Git for version control
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Hardware Requirements

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  • Computer with sufficient computational resources
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  • GPU access recommended for training custom models
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Course Resources

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Tutorial Notebooks

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+ AutoChip Tutorial + VeriThoughts Tutorial + ROME Demo + Testbench Generation + Hybrid-NL2SVA + C2HLSC Tutorial + PrefixLLM +
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Reference Papers

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+ AutoChip Paper + VeriThoughts Paper + ROME Paper + LLM Testbench Paper + Hybrid-NL2SVA Paper + C2HLSC Paper + PrefixLLM Paper +
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Prerequisites

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Contact Information

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This syllabus is subject to modification as the course progresses. Students will be notified of any changes in advance.

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+ + \ No newline at end of file diff --git a/LLM4ChipDesign_Course_Syllabus.md b/LLM4ChipDesign_Course_Syllabus.md new file mode 100644 index 0000000..3f4c3a5 --- /dev/null +++ b/LLM4ChipDesign_Course_Syllabus.md @@ -0,0 +1,282 @@ +# LLM4ChipDesign Course Syllabus +## Generative AI for Chip Design - 14 Week Curriculum + +--- + +### Course Information +- **Course Title:** Generative AI for Chip Design +- **Duration:** 14 Weeks (1 Semester) +- **Format:** 7 Modules, 2 Weeks per Module +- **Teaching Structure:** + - Week 1 of each module: Fundamental concepts and homework assignment + - Week 2 of each module: Homework solutions and hands-on practice + +--- + +### Course Objectives +By the end of this course, students will: +- Understand how Large Language Models (LLMs) can be applied to hardware design automation +- Master various LLM-based tools and techniques for Verilog generation, verification, and optimization +- Develop practical skills in prompt engineering for hardware design tasks +- Gain hands-on experience with state-of-the-art AI-assisted chip design workflows +- Learn to integrate LLM tools into existing hardware design methodologies + +--- + +### Prerequisites +- Basic knowledge of digital logic design +- Familiarity with Verilog/SystemVerilog +- Understanding of hardware design verification concepts +- Programming experience (Python preferred) +- Basic machine learning concepts (helpful but not required) + +--- + +## Module Schedule + +### **Module 1: AutoChip - Automated Verilog Generation (Weeks 1-2)** + +**Week 1: Fundamentals and Introduction** +- **Learning Objectives:** + - Understand the basics of LLM-assisted Verilog generation + - Learn AutoChip's iterative feedback mechanism + - Explore error-driven design refinement +- **Topics Covered:** + - Introduction to generative AI in hardware design + - AutoChip framework overview + - Prompt engineering for Verilog generation + - Compilation and simulation feedback loops +- **Homework Assignment:** + - Design a simple combinational circuit (e.g., 4-bit adder) using AutoChip + - Analyze and document the iterative refinement process + - Compare LLM-generated code with manual implementation + +**Week 2: Problem Solving and Practice** +- **Activities:** + - Review homework solutions and common issues + - Hands-on workshop with AutoChip tutorial + - Debugging techniques for LLM-generated Verilog + - Best practices for prompt design + +--- + +### **Module 2: VeriThoughts - Reasoning-Based Verilog Generation (Weeks 3-4)** + +**Week 1: Fundamentals and Introduction** +- **Learning Objectives:** + - Understand reasoning-based approaches to hardware description + - Learn formal verification integration with LLM generation + - Explore specialized small-scale models for Verilog +- **Topics Covered:** + - Reasoning frameworks in hardware design + - Formal verification methods for generated code + - VeriThoughts dataset and benchmarking + - Quality metrics for generated hardware descriptions +- **Homework Assignment:** + - Implement a finite state machine using VeriThoughts methodology + - Apply formal verification to validate correctness + - Compare reasoning-based vs. direct generation approaches + +**Week 2: Problem Solving and Practice** +- **Activities:** + - Solution walkthrough for FSM implementation + - Formal verification workshop + - Performance comparison analysis + - Discussion on correctness guarantees + +--- + +### **Module 3: ROME - Hierarchical Prompting for Complex Designs (Weeks 5-6)** + +**Week 1: Fundamentals and Introduction** +- **Learning Objectives:** + - Master hierarchical design decomposition strategies + - Understand multi-level prompting techniques + - Learn to handle complex hardware modules +- **Topics Covered:** + - Hierarchical design principles + - Bottom-up vs. top-down generation approaches + - ROME framework and scripted prompting + - Scaling challenges and solutions +- **Homework Assignment:** + - Design a hierarchical processor component (e.g., ALU with multiple sub-modules) + - Implement using both flat and hierarchical prompting + - Analyze cost and time benefits of hierarchical approach + +**Week 2: Problem Solving and Practice** +- **Activities:** + - Hierarchical design solution review + - Advanced ROME techniques workshop + - Cost-benefit analysis discussion + - Complex design case studies + +--- + +### **Module 4: LLM-Aided Testbench Generation and Verification (Weeks 7-8)** + +**Week 1: Fundamentals and Introduction** +- **Learning Objectives:** + - Understand automated testbench generation principles + - Learn coverage-driven verification with LLMs + - Master EDA tool integration techniques +- **Topics Covered:** + - Testbench generation methodologies + - Coverage metrics and analysis + - Iterative feedback from EDA tools + - Bug detection and classification +- **Homework Assignment:** + - Generate comprehensive testbenches for a finite state machine + - Achieve target coverage metrics + - Implement bug detection and reporting workflow + +**Week 2: Problem Solving and Practice** +- **Activities:** + - Testbench solution analysis + - Coverage optimization techniques + - EDA tool integration workshop + - Real-world verification scenarios + +--- + +### **Module 5: Hybrid-NL2SVA - Natural Language to SystemVerilog Assertions (Weeks 9-10)** + +**Week 1: Fundamentals and Introduction** +- **Learning Objectives:** + - Master assertion-based verification concepts + - Learn natural language to SystemVerilog translation + - Understand security-centric assertion development +- **Topics Covered:** + - SystemVerilog assertion (SVA) fundamentals + - Natural language processing for hardware properties + - Security assertion patterns + - RAG (Retrieval-Augmented Generation) techniques +- **Homework Assignment:** + - Convert natural language security requirements to SVA + - Implement assertion suite for a cryptographic module + - Validate assertions using formal verification + +**Week 2: Problem Solving and Practice** +- **Activities:** + - SVA implementation review + - Security assertion patterns workshop + - Formal verification of assertions + - Industry best practices discussion + +--- + +### **Module 6: C2HLSC - Software to Hardware Design Bridge (Weeks 11-12)** + +**Week 1: Fundamentals and Introduction** +- **Learning Objectives:** + - Understand High-Level Synthesis (HLS) principles + - Learn C-to-hardware translation techniques + - Master LLM-guided code transformation +- **Topics Covered:** + - HLS design flow and challenges + - C code refactoring for hardware synthesis + - Streaming data and hardware-specific signals + - Hierarchical design decomposition +- **Homework Assignment:** + - Transform a C algorithm (e.g., sorting, encryption) to HLS-compatible format + - Optimize for area and timing constraints + - Compare different optimization strategies + +**Week 2: Problem Solving and Practice** +- **Activities:** + - HLS optimization solution review + - Performance analysis workshop + - Area vs. timing trade-offs discussion + - Advanced HLS techniques + +--- + +### **Module 7: PrefixLLM - Specialized Circuit Design (Weeks 13-14)** + +**Week 1: Fundamentals and Introduction** +- **Learning Objectives:** + - Understand prefix circuit design principles + - Learn structured representation for circuit synthesis + - Master design space exploration with LLMs +- **Topics Covered:** + - Prefix adder architectures + - Structured Prefix Circuit Representation (SPCR) + - Automated design space exploration + - Area and delay optimization techniques +- **Homework Assignment:** + - Design optimized prefix circuits for different bit widths + - Implement design space exploration framework + - Compare multiple optimization objectives + +**Week 2: Problem Solving and Practice** +- **Activities:** + - Optimization results analysis + - Design space exploration workshop + - Multi-objective optimization discussion + - Course wrap-up and future directions + +--- + +### Assessment Methods + +**Continuous Assessment (70%)** +- Weekly homework assignments (40%) +- Module quizzes (20%) +- Participation and engagement (10%) + +**Final Project (30%)** +- Comprehensive project integrating multiple modules +- Original research or advanced implementation +- Presentation and documentation + +--- + +### Required Tools and Resources + +**Software Tools:** +- Verilator or equivalent Verilog simulator +- Python environment with LLM libraries +- Access to LLM APIs (OpenAI, Anthropic, etc.) +- EDA tools for synthesis and verification +- Git for version control + +**Hardware:** +- Computer with sufficient computational resources +- GPU access recommended for training custom models + +**Reading Materials:** +- Research papers provided for each module +- Online documentation and tutorials +- Supplementary materials in colab-scripts directory + +--- + +### Additional Resources + +**Jupyter Notebooks:** +- `AutoChip_Tutorial.ipynb` +- `VeriThoughts_Tutorial.ipynb` +- `ROME_demo.ipynb` +- `LLM_Aided_Testbench_Generation_for_FSM.ipynb` +- `Hybrid_NL2SVA.ipynb` +- `C2HLSC_Tutorial.ipynb` +- `PrefixLLM.ipynb` + +**Reference Papers:** +- AutoChip: https://arxiv.org/abs/2311.04887 +- VeriThoughts: https://arxiv.org/abs/2505.20302 +- ROME: https://arxiv.org/abs/2407.18276 +- LLM Testbench: https://arxiv.org/html/2406.17132v1 +- Hybrid-NL2SVA: https://arxiv.org/pdf/2506.21569 +- C2HLSC: https://arxiv.org/abs/2412.00214 +- PrefixLLM: https://arxiv.org/abs/2412.02594 + +--- + +### Contact Information +- **Instructor:** [To be filled] +- **Office Hours:** [To be scheduled] +- **Course Repository:** https://github.com/FCHXWH823/LLM4ChipDesign + +--- + +*This syllabus is subject to modification as the course progresses. Students will be notified of any changes in advance.* \ No newline at end of file diff --git a/README.md b/README.md index 5a0c872..d38ef3b 100644 --- a/README.md +++ b/README.md @@ -1,5 +1,13 @@ # Generative AI for Chip Design +## 📚 Course Syllabus +**NEW:** [**LLM4ChipDesign Course Syllabus**](LLM4ChipDesign_Course_Syllabus.md) - A comprehensive 14-week curriculum covering all modules with structured learning objectives, homework assignments, and assessment methods. + +- 📄 **Markdown Version:** [LLM4ChipDesign_Course_Syllabus.md](LLM4ChipDesign_Course_Syllabus.md) +- 🌐 **HTML Version:** [LLM4ChipDesign_Course_Syllabus.html](LLM4ChipDesign_Course_Syllabus.html) + +--- + ## Table of Contents - [AutoChip to Generate Functional Verilog](#autochip-to-generate-functional-verilog) - [VeriThoughts: Enabling Automated Verilog Code Generation using Reasoning and Formal Verification](#verithoughts-enabling-automated-verilog-code-generation-using-reasoning-and-formal-verification)