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refactor: enhance verilator command options and update log file naming convention
1 parent d7c8a24 commit 84b95e3

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3 files changed

+16
-5
lines changed

3 files changed

+16
-5
lines changed

api/steps/verilator/02_verilog_event_step.py

Lines changed: 12 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -53,8 +53,18 @@ async def handler(data, context):
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else:
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command = f"mill -i __.test.runMain sims.verilator.Elaborate {config_name} "
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56-
command += "--disable-annotation-unknown -strip-debug-info -O=debug "
57-
command += f"--split-verilog -o={build_dir}"
56+
# Firtool options (CIRCT). Current set; optional Chipyard-style options below.
57+
command += "--disable-annotation-unknown "
58+
command += "--strip-debug-info "
59+
command += "-O=debug "
60+
# command += f"-repl-seq-mem -repl-seq-mem-file={build_dir}/mem.conf "
61+
command += f"--split-verilog -o={build_dir} "
62+
# Optional: --disable-annotation-classless (ignore classless annotations)
63+
# Optional: -repl-seq-mem -repl-seq-mem-file=<path>.conf (SRAM macro replacement)
64+
# Optional: --disable-all-randomization (disable mem/reg init; may break semantics)
65+
# Optional: --disable-opt (no optimization) or -O=release (default is release)
66+
# Optional: --output-annotation-file=<path> (emit annotations after lower-to-hw)
67+
# Optional: --no-dedup (disable module dedup); --strip-fir-debug-info (FIR locators)
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5969
result = stream_run_logger(
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cmd=command,

api/steps/verilator/03_build_event_step.py

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -74,6 +74,7 @@ def pkg_config(flag, pkg):
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])
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# -DBBSIM: selects VBBSimHarness in bdb.h / main.cc
77+
# BDB NDJSON trace (+trace=...) is runtime-only; bbdev sim uses +trace=all (04_sim_event_step.py).
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cflags = f"{inc_flags} -DBBSIM -DTOP_NAME='\"V{topname}\"' -std=c++17"
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7980
ldflags = (
@@ -84,7 +85,7 @@ def pkg_config(flag, pkg):
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)
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obj_dir = f"{build_dir}/obj_dir"
87-
subprocess.run(f"rm -rf {obj_dir}", shell=True)
88+
# subprocess.run(f"rm -rf {obj_dir}", shell=True)
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os.makedirs(obj_dir, exist_ok=True)
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sources = " ".join(vsrcs + csrcs)

api/steps/verilator/04_sim_event_step.py

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -63,7 +63,7 @@ async def handler(data, context):
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bin_path = f"{build_dir}/obj_dir/V{topname}"
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batch = data.get("batch", False)
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66-
log_path = f"{log_dir}/bdb.log"
66+
log_path = f"{log_dir}/bdb.ndjson"
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stdout_path = f"{log_dir}/stdout.log"
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fst_path = f"{waveform_dir}/waveform.fst"
6969

@@ -82,7 +82,7 @@ async def handler(data, context):
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f"+elf={binary_path} "
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f"{'+batch ' if batch else ''}"
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f"{coverage_flag + ' ' if coverage_flag else ''}"
85-
f"+fst={fst_path} +log={log_path} +stdout={stdout_path} +permissive-off "
85+
f"+fst={fst_path} +log={log_path} +stdout={stdout_path} +trace=all +permissive-off "
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f"{binary_path} 2> >(spike-dasm > {log_dir}/disasm.log)"
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)
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script_dir = os.path.dirname(__file__)

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